From 14a4057959f8ee0a2249eb2abd64fd6b1f571d98 Mon Sep 17 00:00:00 2001 From: Ian Wisbon Date: Thu, 10 Feb 2011 17:15:15 -0500 Subject: Digi Release Code - 02142011 Missing Files Fix --- drivers/mxc/amd-gpu/include/reg/g12_reg.h | 41 + drivers/mxc/amd-gpu/include/reg/vgc/vgenums_z160.h | 291 + drivers/mxc/amd-gpu/include/reg/vgc/vgregs_z160.h | 3775 ++ drivers/mxc/amd-gpu/include/reg/yamato.h | 66 + .../amd-gpu/include/reg/yamato/10/yamato_enum.h | 1895 + .../amd-gpu/include/reg/yamato/10/yamato_genenum.h | 1703 + .../amd-gpu/include/reg/yamato/10/yamato_genreg.h | 3404 ++ .../amd-gpu/include/reg/yamato/10/yamato_mask.h | 5920 +++ .../amd-gpu/include/reg/yamato/10/yamato_offset.h | 590 + .../amd-gpu/include/reg/yamato/10/yamato_random.h | 223 + .../include/reg/yamato/10/yamato_registers.h | 14292 +++++ .../amd-gpu/include/reg/yamato/10/yamato_shift.h | 4183 ++ .../amd-gpu/include/reg/yamato/10/yamato_struct.h | 52571 ++++++++++++++++++ .../amd-gpu/include/reg/yamato/10/yamato_typedef.h | 550 + .../mxc/amd-gpu/include/reg/yamato/10/yamatoix.h | 169 + .../amd-gpu/include/reg/yamato/14/yamato_enum.h | 1867 + .../amd-gpu/include/reg/yamato/14/yamato_genenum.h | 1674 + .../amd-gpu/include/reg/yamato/14/yamato_genreg.h | 3310 ++ .../mxc/amd-gpu/include/reg/yamato/14/yamato_ipt.h | 95 + .../amd-gpu/include/reg/yamato/14/yamato_mask.h | 5739 ++ .../amd-gpu/include/reg/yamato/14/yamato_offset.h | 581 + .../amd-gpu/include/reg/yamato/14/yamato_random.h | 221 + .../include/reg/yamato/14/yamato_registers.h | 13962 +++++ .../amd-gpu/include/reg/yamato/14/yamato_shift.h | 4078 ++ .../amd-gpu/include/reg/yamato/14/yamato_struct.h | 51301 ++++++++++++++++++ .../amd-gpu/include/reg/yamato/14/yamato_typedef.h | 540 + .../amd-gpu/include/reg/yamato/22/yamato_enum.h | 1897 + .../amd-gpu/include/reg/yamato/22/yamato_genenum.h | 1703 + .../amd-gpu/include/reg/yamato/22/yamato_genreg.h | 3405 ++ .../mxc/amd-gpu/include/reg/yamato/22/yamato_ipt.h | 95 + .../amd-gpu/include/reg/yamato/22/yamato_mask.h | 5908 +++ .../amd-gpu/include/reg/yamato/22/yamato_offset.h | 591 + .../amd-gpu/include/reg/yamato/22/yamato_random.h | 223 + .../include/reg/yamato/22/yamato_registers.h | 14280 +++++ .../amd-gpu/include/reg/yamato/22/yamato_shift.h | 4184 ++ .../amd-gpu/include/reg/yamato/22/yamato_struct.h | 52583 +++++++++++++++++++ .../amd-gpu/include/reg/yamato/22/yamato_typedef.h | 550 + 37 files changed, 258460 insertions(+) create mode 100644 drivers/mxc/amd-gpu/include/reg/g12_reg.h create mode 100644 drivers/mxc/amd-gpu/include/reg/vgc/vgenums_z160.h create mode 100644 drivers/mxc/amd-gpu/include/reg/vgc/vgregs_z160.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_enum.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_genenum.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_genreg.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_mask.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_offset.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_random.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_registers.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_shift.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_struct.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_typedef.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/10/yamatoix.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_enum.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_genenum.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_genreg.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_ipt.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_mask.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_offset.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_random.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_registers.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_shift.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_struct.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_typedef.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_enum.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_genenum.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_genreg.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_ipt.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_mask.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_offset.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_random.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_registers.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_shift.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_struct.h create mode 100644 drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_typedef.h (limited to 'drivers/mxc/amd-gpu/include/reg') diff --git a/drivers/mxc/amd-gpu/include/reg/g12_reg.h b/drivers/mxc/amd-gpu/include/reg/g12_reg.h new file mode 100644 index 000000000000..d12d419822a2 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/g12_reg.h @@ -0,0 +1,41 @@ +/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of Code Aurora Forum, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _G12_H +#define _G12_H + +#ifdef _Z180 +#include "vgc/vgregs_z180.h" +#include "vgc/vgenums_z180.h" +#else +#include "vgc/vgregs_z160.h" +#include "vgc/vgenums_z160.h" +#endif + +#endif // _G12_H diff --git a/drivers/mxc/amd-gpu/include/reg/vgc/vgenums_z160.h b/drivers/mxc/amd-gpu/include/reg/vgc/vgenums_z160.h new file mode 100644 index 000000000000..911c22fbbba6 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/vgc/vgenums_z160.h @@ -0,0 +1,291 @@ +/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of Code Aurora Forum, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REGS_ENUMS_H +#define __REGS_ENUMS_H + +typedef enum _BB_CULL { + BB_CULL_NONE = 0, + BB_CULL_CW = 1, + BB_CULL_CCW = 2, +} BB_CULL; + +typedef enum _BB_TEXTUREADDRESS { + BB_TADDRESS_WRAP = 0, + BB_TADDRESS_CLAMP = 1, + BB_TADDRESS_BORDER = 2, + BB_TADDRESS_MIRROR = 4, + BB_TADDRESS_MIRRORCLAMP = 5, // Not supported on G3x cores + BB_TADDRESS_MIRRORBORDER = 6, // Not supported on G3x cores +} BB_TEXTUREADDRESS; + +typedef enum _BB_TEXTYPE { + BB_TEXTYPE_4444 = 0, + BB_TEXTYPE_1555 = 1, + BB_TEXTYPE_5551 = 2, + BB_TEXTYPE_565 = 3, + BB_TEXTYPE_8888 = 4, + BB_TEXTYPE_8 = 5, + BB_TEXTYPE_88 = 6, + BB_TEXTYPE_4 = 7, + BB_TEXTYPE_44 = 8, + BB_TEXTYPE_UYVY = 9, + BB_TEXTYPE_YUY2 = 10, + BB_TEXTYPE_YVYU = 11, + BB_TEXTYPE_DXT1 = 12, + BB_TEXTYPE_PACKMAN = 13, + BB_TEXTYPE_PACKMAN_ALPHA4 = 14, + BB_TEXTYPE_1F16 = 15, + BB_TEXTYPE_2F16 = 16, + BB_TEXTYPE_4F16 = 17, + BB_TEXTYPE_IPACKMAN_RGB = 18, + BB_TEXTYPE_IPACKMAN_RGBA = 19, +} BB_TEXTYPE; + +typedef enum _BB_CMPFUNC { + BB_CMP_NEVER = 0, + BB_CMP_LESS = 1, + BB_CMP_EQUAL = 2, + BB_CMP_LESSEQUAL = 3, + BB_CMP_GREATER = 4, + BB_CMP_NOTEQUAL = 5, + BB_CMP_GREATEREQUAL = 6, + BB_CMP_ALWAYS = 7, +} BB_CMPFUNC; + +typedef enum _BB_STENCILOP { + BB_STENCILOP_KEEP = 0, + BB_STENCILOP_ZERO = 1, + BB_STENCILOP_REPLACE = 2, + BB_STENCILOP_INCRSAT = 3, + BB_STENCILOP_DECRSAT = 4, + BB_STENCILOP_INVERT = 5, + BB_STENCILOP_INCR = 6, + BB_STENCILOP_DECR = 7, +} BB_STENCILOP; + +typedef enum _BB_PRIMITIVETYPE { + BB_PT_POINTLIST = 0, + BB_PT_LINELIST = 1, + BB_PT_LINESTRIP = 2, + BB_PT_TRIANGLELIST = 3, + BB_PT_TRIANGLESTRIP = 4, + BB_PT_TRIANGLEFAN = 5, +} BB_PRIMITIVETYPE; + +typedef enum _BB_TEXTUREFILTERTYPE { + BB_TEXF_NONE = 0, // filtering disabled (valid for mip filter only) + BB_TEXF_POINT = 1, // nearest + BB_TEXF_LINEAR = 2, // linear interpolation +} BB_TEXTUREFILTERTYPE; + +typedef enum _BB_BUFFER { + BB_BUFFER_PPCODE = 0, // Pixel processor code + BB_BUFFER_UNUSED = 1, // Unused + BB_BUFFER_CBUF = 2, // Color buffer + BB_BUFFER_ZBUF = 3, // Z buffer + BB_BUFFER_AUXBUF0 = 4, // AUX0 buffer + BB_BUFFER_AUXBUF1 = 5, // AUX1 buffer + BB_BUFFER_AUXBUF2 = 6, // AUX2 buffer + BB_BUFFER_AUXBUF3 = 7, // AUX3 buffer +} BB_BUFFER; + +typedef enum _BB_COLORFORMAT { + BB_COLOR_ARGB4444 = 0, + BB_COLOR_ARGB0565 = 1, + BB_COLOR_ARGB1555 = 2, + BB_COLOR_RGBA5551 = 3, + BB_COLOR_ARGB8888 = 4, + BB_COLOR_R16 = 5, + BB_COLOR_RG1616 = 6, + BB_COLOR_ARGB16161616 = 7, + BB_COLOR_D16 = 8, + BB_COLOR_S4D12 = 9, + BB_COLOR_S1D15 = 10, + BB_COLOR_X8D24 = 11, + BB_COLOR_S8D24 = 12, + BB_COLOR_X2D30 = 13, +} BB_COLORFORMAT; + +typedef enum _BB_PP_REGCONFIG { + BB_PP_REGCONFIG_1 = 0, + BB_PP_REGCONFIG_2 = 1, + BB_PP_REGCONFIG_3 = 8, + BB_PP_REGCONFIG_4 = 2, + BB_PP_REGCONFIG_6 = 9, + BB_PP_REGCONFIG_8 = 3, + BB_PP_REGCONFIG_12 = 10, + BB_PP_REGCONFIG_16 = 4, + BB_PP_REGCONFIG_24 = 11, + BB_PP_REGCONFIG_32 = 5, +} BB_PP_REGCONFIG; + +typedef enum _G2D_read_t { + G2D_READ_DST = 0, + G2D_READ_SRC1 = 1, + G2D_READ_SRC2 = 2, + G2D_READ_SRC3 = 3, +} G2D_read_t; + +typedef enum _G2D_format_t { + G2D_1 = 0, // foreground & background + G2D_1BW = 1, // black & white + G2D_4 = 2, + G2D_8 = 3, // alpha + G2D_4444 = 4, + G2D_1555 = 5, + G2D_0565 = 6, + G2D_8888 = 7, + G2D_YUY2 = 8, + G2D_UYVY = 9, + G2D_YVYU = 10, + G2D_4444_RGBA = 11, + G2D_5551_RGBA = 12, + G2D_8888_RGBA = 13, + G2D_A8 = 14, // for alpha texture only +} G2D_format_t; + +typedef enum _G2D_wrap_t { + G2D_WRAP_CLAMP = 0, + G2D_WRAP_REPEAT = 1, + G2D_WRAP_MIRROR = 2, + G2D_WRAP_BORDER = 3, +} G2D_wrap_t; + +typedef enum _G2D_BLEND_OP { + G2D_BLENDOP_ADD = 0, + G2D_BLENDOP_SUB = 1, + G2D_BLENDOP_MIN = 2, + G2D_BLENDOP_MAX = 3, +} G2D_BLEND_OP; + +typedef enum _G2D_GRAD_OP { + G2D_GRADOP_DOT = 0, + G2D_GRADOP_RCP = 1, + G2D_GRADOP_SQRTMUL = 2, + G2D_GRADOP_SQRTADD = 3, +} G2D_GRAD_OP; + +typedef enum _G2D_BLEND_SRC { + G2D_BLENDSRC_ZERO = 0, // One with invert + G2D_BLENDSRC_SOURCE = 1, // Paint with coverage alpha applied + G2D_BLENDSRC_DESTINATION = 2, + G2D_BLENDSRC_IMAGE = 3, // Second texture + G2D_BLENDSRC_TEMP0 = 4, + G2D_BLENDSRC_TEMP1 = 5, + G2D_BLENDSRC_TEMP2 = 6, +} G2D_BLEND_SRC; + +typedef enum _G2D_BLEND_DST { + G2D_BLENDDST_IGNORE = 0, // Ignore destination + G2D_BLENDDST_TEMP0 = 1, + G2D_BLENDDST_TEMP1 = 2, + G2D_BLENDDST_TEMP2 = 3, +} G2D_BLEND_DST; + +typedef enum _G2D_BLEND_CONST { + G2D_BLENDSRC_CONST0 = 0, + G2D_BLENDSRC_CONST1 = 1, + G2D_BLENDSRC_CONST2 = 2, + G2D_BLENDSRC_CONST3 = 3, + G2D_BLENDSRC_CONST4 = 4, + G2D_BLENDSRC_CONST5 = 5, + G2D_BLENDSRC_CONST6 = 6, + G2D_BLENDSRC_CONST7 = 7, +} G2D_BLEND_CONST; + +typedef enum _V3_NEXTCMD { + VGV3_NEXTCMD_CONTINUE = 0, // Continue reading at current address, COUNT gives size of next packet. + VGV3_NEXTCMD_JUMP = 1, // Jump to CALLADDR, COUNT gives size of next packet. + VGV3_NEXTCMD_CALL = 2, // First call a sub-stream at CALLADDR for CALLCOUNT dwords. Then perform a continue. + VGV3_NEXTCMD_CALLV2TRUE = 3, // Not supported. + VGV3_NEXTCMD_CALLV2FALSE = 4, // Not supported. + VGV3_NEXTCMD_ABORT = 5, // Abort reading. This ends the stream. Normally stream can just be paused (or automatically pauses at the end) which avoids any data being lost. +} V3_NEXTCMD; + +typedef enum _V3_FORMAT { + VGV3_FORMAT_S8 = 0, // Signed 8 bit data (4 writes per data dword) => VGV2-float + VGV3_FORMAT_S16 = 1, // Signed 16 bit data (2 writes per data dword) => VGV2-float + VGV3_FORMAT_S32 = 2, // Signed 32 bit data => VGV2-float + VGV3_FORMAT_F32 = 3, // IEEE 32-bit floating point => VGV2-float + VGV3_FORMAT_RAW = 4, // No conversion +} V3_FORMAT; + +typedef enum _V2_ACTION { + VGV2_ACTION_END = 0, // end previous path + VGV2_ACTION_MOVETOOPEN = 1, // end previous path, C1=C4, start new open subpath + VGV2_ACTION_MOVETOCLOSED = 2, // end previous path, C1=C4, start new closed subpath + VGV2_ACTION_LINETO = 3, // line C1,C4 + VGV2_ACTION_CUBICTO = 4, // cubic C1,C2,C3,C4. + VGV2_ACTION_QUADTO = 5, // quadratic C1,C3,C4. + VGV2_ACTION_SCUBICTO = 6, // smooth cubic C1,C4. + VGV2_ACTION_SQUADTO = 7, // smooth quadratic C1,C3,C4. + VGV2_ACTION_VERTEXTO = 8, // half lineto C4=pos, C3=normal. + VGV2_ACTION_VERTEXTOOPEN = 9, // moveto open + half lineto C4=pos, C3=normal. + VGV2_ACTION_VERTEXTOCLOSED = 10, // moveto closed + half lineto C4=pos, C3=normal. + VGV2_ACTION_MOVETOMOVE = 11, // end previous path, C1=C4, move but do not start a subpath + VGV2_ACTION_FLUSH = 15, // end previous path and block following regwrites until all lines sent +} V2_ACTION; + +typedef enum _V2_CAP { + VGV2_CAP_BUTT = 0, // butt caps (straight line overlappin starting point + VGV2_CAP_ROUND = 1, // round caps (smoothness depends on ARCSIN/ARCCOS registers) + VGV2_CAP_SQUARE = 2, // square caps (square centered on starting point) +} V2_CAP; + +typedef enum _V2_JOIN { + VGV2_JOIN_MITER = 0, // miter joins (both sides extended towards intersection. If angle is too small (compared to STMITER register) the miter is converted into a BEVEL. + VGV2_JOIN_ROUND = 1, // round joins (smoothness depends on ARCSIN/ARCCOS registers) + VGV2_JOIN_BEVEL = 2, // bevel joins (ends of both sides are connected with a single line) +} V2_JOIN; + +enum +{ + G2D_GRADREG_X = 0, // also usable as temp + G2D_GRADREG_Y = 1, // also usable as temp + G2D_GRADREG_OUTX = 8, + G2D_GRADREG_OUTY = 9, + G2D_GRADREG_C0 = 16, + G2D_GRADREG_C1 = 17, + G2D_GRADREG_C2 = 18, + G2D_GRADREG_C3 = 19, + G2D_GRADREG_C4 = 20, + G2D_GRADREG_C5 = 21, + G2D_GRADREG_C6 = 22, + G2D_GRADREG_C7 = 23, + G2D_GRADREG_C8 = 24, + G2D_GRADREG_C9 = 25, + G2D_GRADREG_C10 = 26, + G2D_GRADREG_C11 = 27, + G2D_GRADREG_ZERO = 28, + G2D_GRADREG_ONE = 29, + G2D_GRADREG_MINUSONE = 30, +}; + +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/vgc/vgregs_z160.h b/drivers/mxc/amd-gpu/include/reg/vgc/vgregs_z160.h new file mode 100644 index 000000000000..1660bc1c12a9 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/vgc/vgregs_z160.h @@ -0,0 +1,3775 @@ +/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of Code Aurora Forum, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REGS_G4X_DRIVER_H +#define __REGS_G4X_DRIVER_H + +#ifndef _LINUX +#include +#else +#ifndef assert +#define assert(expr) +#endif +#endif + +//----------------------------------------------------- +// REGISTER ADDRESSES +//----------------------------------------------------- + +#define ADDR_FBC_BASE 0x84 +#define ADDR_FBC_DATA 0x86 +#define ADDR_FBC_HEIGHT 0x8a +#define ADDR_FBC_START 0x8e +#define ADDR_FBC_STRIDE 0x8c +#define ADDR_FBC_WIDTH 0x88 +#define ADDR_VGC_CLOCKEN 0x508 +#define ADDR_VGC_COMMANDSTREAM 0x0 +#define ADDR_VGC_FIFOFREE 0x7c0 +#define ADDR_VGC_IRQENABLE 0x438 +#define ADDR_VGC_IRQSTATUS 0x418 +#define ADDR_VGC_IRQ_ACTIVE_CNT 0x4e0 +#define ADDR_VGC_MMUCOMMANDSTREAM 0x3fc +#define ADDR_VGC_REVISION 0x400 +#define ADDR_VGC_SYSSTATUS 0x410 +#define ADDR_G2D_ALPHABLEND 0xc +#define ADDR_G2D_BACKGROUND 0xb +#define ADDR_G2D_BASE0 0x0 +#define ADDR_G2D_BASE1 0x2 +#define ADDR_G2D_BASE2 0x4 +#define ADDR_G2D_BASE3 0x6 +#define ADDR_G2D_BLENDERCFG 0x11 +#define ADDR_G2D_BLEND_A0 0x14 +#define ADDR_G2D_BLEND_A1 0x15 +#define ADDR_G2D_BLEND_A2 0x16 +#define ADDR_G2D_BLEND_A3 0x17 +#define ADDR_G2D_BLEND_C0 0x18 +#define ADDR_G2D_BLEND_C1 0x19 +#define ADDR_G2D_BLEND_C2 0x1a +#define ADDR_G2D_BLEND_C3 0x1b +#define ADDR_G2D_BLEND_C4 0x1c +#define ADDR_G2D_BLEND_C5 0x1d +#define ADDR_G2D_BLEND_C6 0x1e +#define ADDR_G2D_BLEND_C7 0x1f +#define ADDR_G2D_CFG0 0x1 +#define ADDR_G2D_CFG1 0x3 +#define ADDR_G2D_CFG2 0x5 +#define ADDR_G2D_CFG3 0x7 +#define ADDR_G2D_COLOR 0xff +#define ADDR_G2D_CONFIG 0xe +#define ADDR_G2D_CONST0 0xb0 +#define ADDR_G2D_CONST1 0xb1 +#define ADDR_G2D_CONST2 0xb2 +#define ADDR_G2D_CONST3 0xb3 +#define ADDR_G2D_CONST4 0xb4 +#define ADDR_G2D_CONST5 0xb5 +#define ADDR_G2D_CONST6 0xb6 +#define ADDR_G2D_CONST7 0xb7 +#define ADDR_G2D_FOREGROUND 0xa +#define ADDR_G2D_GRADIENT 0xd0 +#define ADDR_G2D_IDLE 0xfe +#define ADDR_G2D_INPUT 0xf +#define ADDR_G2D_MASK 0x10 +#define ADDR_G2D_ROP 0xd +#define ADDR_G2D_SCISSORX 0x8 +#define ADDR_G2D_SCISSORY 0x9 +#define ADDR_G2D_SXY 0xf2 +#define ADDR_G2D_SXY2 0xf3 +#define ADDR_G2D_VGSPAN 0xf4 +#define ADDR_G2D_WIDTHHEIGHT 0xf1 +#define ADDR_G2D_XY 0xf0 +#define ADDR_GRADW_BORDERCOLOR 0xd4 +#define ADDR_GRADW_CONST0 0xc0 +#define ADDR_GRADW_CONST1 0xc1 +#define ADDR_GRADW_CONST2 0xc2 +#define ADDR_GRADW_CONST3 0xc3 +#define ADDR_GRADW_CONST4 0xc4 +#define ADDR_GRADW_CONST5 0xc5 +#define ADDR_GRADW_CONST6 0xc6 +#define ADDR_GRADW_CONST7 0xc7 +#define ADDR_GRADW_CONST8 0xc8 +#define ADDR_GRADW_CONST9 0xc9 +#define ADDR_GRADW_CONSTA 0xca +#define ADDR_GRADW_CONSTB 0xcb +#define ADDR_GRADW_INST0 0xe0 +#define ADDR_GRADW_INST1 0xe1 +#define ADDR_GRADW_INST2 0xe2 +#define ADDR_GRADW_INST3 0xe3 +#define ADDR_GRADW_INST4 0xe4 +#define ADDR_GRADW_INST5 0xe5 +#define ADDR_GRADW_INST6 0xe6 +#define ADDR_GRADW_INST7 0xe7 +#define ADDR_GRADW_TEXBASE 0xd3 +#define ADDR_GRADW_TEXCFG 0xd1 +#define ADDR_GRADW_TEXSIZE 0xd2 +#define ADDR_MH_ARBITER_CONFIG 0xa40 +#define ADDR_MH_AXI_ERROR 0xa45 +#define ADDR_MH_AXI_HALT_CONTROL 0xa50 +#define ADDR_MH_CLNT_AXI_ID_REUSE 0xa41 +#define ADDR_MH_DEBUG_CTRL 0xa4e +#define ADDR_MH_DEBUG_DATA 0xa4f +#define ADDR_MH_INTERRUPT_CLEAR 0xa44 +#define ADDR_MH_INTERRUPT_MASK 0xa42 +#define ADDR_MH_INTERRUPT_STATUS 0xa43 +#define ADDR_MH_MMU_CONFIG 0x40 +#define ADDR_MH_MMU_INVALIDATE 0x45 +#define ADDR_MH_MMU_MPU_BASE 0x46 +#define ADDR_MH_MMU_MPU_END 0x47 +#define ADDR_MH_MMU_PAGE_FAULT 0x43 +#define ADDR_MH_MMU_PT_BASE 0x42 +#define ADDR_MH_MMU_TRAN_ERROR 0x44 +#define ADDR_MH_MMU_VA_RANGE 0x41 +#define ADDR_MH_PERFCOUNTER0_CONFIG 0xa47 +#define ADDR_MH_PERFCOUNTER0_HI 0xa49 +#define ADDR_MH_PERFCOUNTER0_LOW 0xa48 +#define ADDR_MH_PERFCOUNTER0_SELECT 0xa46 +#define ADDR_MH_PERFCOUNTER1_CONFIG 0xa4b +#define ADDR_MH_PERFCOUNTER1_HI 0xa4d +#define ADDR_MH_PERFCOUNTER1_LOW 0xa4c +#define ADDR_MH_PERFCOUNTER1_SELECT 0xa4a +#define ADDR_MMU_READ_ADDR 0x510 +#define ADDR_MMU_READ_DATA 0x518 +#define ADDR_VGV1_CBASE1 0x2a +#define ADDR_VGV1_CFG1 0x27 +#define ADDR_VGV1_CFG2 0x28 +#define ADDR_VGV1_DIRTYBASE 0x29 +#define ADDR_VGV1_FILL 0x23 +#define ADDR_VGV1_SCISSORX 0x24 +#define ADDR_VGV1_SCISSORY 0x25 +#define ADDR_VGV1_TILEOFS 0x22 +#define ADDR_VGV1_UBASE2 0x2b +#define ADDR_VGV1_VTX0 0x20 +#define ADDR_VGV1_VTX1 0x21 +#define ADDR_VGV2_ACCURACY 0x60 +#define ADDR_VGV2_ACTION 0x6f +#define ADDR_VGV2_ARCCOS 0x62 +#define ADDR_VGV2_ARCSIN 0x63 +#define ADDR_VGV2_ARCTAN 0x64 +#define ADDR_VGV2_BBOXMAXX 0x5c +#define ADDR_VGV2_BBOXMAXY 0x5d +#define ADDR_VGV2_BBOXMINX 0x5a +#define ADDR_VGV2_BBOXMINY 0x5b +#define ADDR_VGV2_BIAS 0x5f +#define ADDR_VGV2_C1X 0x40 +#define ADDR_VGV2_C1XREL 0x48 +#define ADDR_VGV2_C1Y 0x41 +#define ADDR_VGV2_C1YREL 0x49 +#define ADDR_VGV2_C2X 0x42 +#define ADDR_VGV2_C2XREL 0x4a +#define ADDR_VGV2_C2Y 0x43 +#define ADDR_VGV2_C2YREL 0x4b +#define ADDR_VGV2_C3X 0x44 +#define ADDR_VGV2_C3XREL 0x4c +#define ADDR_VGV2_C3Y 0x45 +#define ADDR_VGV2_C3YREL 0x4d +#define ADDR_VGV2_C4X 0x46 +#define ADDR_VGV2_C4XREL 0x4e +#define ADDR_VGV2_C4Y 0x47 +#define ADDR_VGV2_C4YREL 0x4f +#define ADDR_VGV2_CLIP 0x68 +#define ADDR_VGV2_FIRST 0x40 +#define ADDR_VGV2_LAST 0x6f +#define ADDR_VGV2_MITER 0x66 +#define ADDR_VGV2_MODE 0x6e +#define ADDR_VGV2_RADIUS 0x65 +#define ADDR_VGV2_SCALE 0x5e +#define ADDR_VGV2_THINRADIUS 0x61 +#define ADDR_VGV2_XFSTXX 0x56 +#define ADDR_VGV2_XFSTXY 0x58 +#define ADDR_VGV2_XFSTYX 0x57 +#define ADDR_VGV2_XFSTYY 0x59 +#define ADDR_VGV2_XFXA 0x54 +#define ADDR_VGV2_XFXX 0x50 +#define ADDR_VGV2_XFXY 0x52 +#define ADDR_VGV2_XFYA 0x55 +#define ADDR_VGV2_XFYX 0x51 +#define ADDR_VGV2_XFYY 0x53 +#define ADDR_VGV3_CONTROL 0x70 +#define ADDR_VGV3_FIRST 0x70 +#define ADDR_VGV3_LAST 0x7f +#define ADDR_VGV3_MODE 0x71 +#define ADDR_VGV3_NEXTADDR 0x75 +#define ADDR_VGV3_NEXTCMD 0x76 +#define ADDR_VGV3_VGBYPASS 0x77 +#define ADDR_VGV3_WRITE 0x73 +#define ADDR_VGV3_WRITEADDR 0x72 +#define ADDR_VGV3_WRITEDMI 0x7d +#define ADDR_VGV3_WRITEF32 0x7b +#define ADDR_VGV3_WRITEIFPAUSED 0x74 +#define ADDR_VGV3_WRITERAW 0x7c +#define ADDR_VGV3_WRITES16 0x79 +#define ADDR_VGV3_WRITES32 0x7a +#define ADDR_VGV3_WRITES8 0x78 + +// FBC_BASE +typedef struct _REG_FBC_BASE { + unsigned BASE : 32; +} REG_FBC_BASE; + +// FBC_DATA +typedef struct _REG_FBC_DATA { + unsigned DATA : 32; +} REG_FBC_DATA; + +// FBC_HEIGHT +typedef struct _REG_FBC_HEIGHT { + unsigned HEIGHT : 11; +} REG_FBC_HEIGHT; + +// FBC_START +typedef struct _REG_FBC_START { + unsigned DUMMY : 1; +} REG_FBC_START; + +// FBC_STRIDE +typedef struct _REG_FBC_STRIDE { + unsigned STRIDE : 11; +} REG_FBC_STRIDE; + +// FBC_WIDTH +typedef struct _REG_FBC_WIDTH { + unsigned WIDTH : 11; +} REG_FBC_WIDTH; + +// VGC_CLOCKEN +typedef struct _REG_VGC_CLOCKEN { + unsigned BCACHE : 1; + unsigned G2D_VGL3 : 1; + unsigned VG_L1L2 : 1; + unsigned RESERVED : 3; +} REG_VGC_CLOCKEN; + +// VGC_COMMANDSTREAM +typedef struct _REG_VGC_COMMANDSTREAM { + unsigned DATA : 32; +} REG_VGC_COMMANDSTREAM; + +// VGC_FIFOFREE +typedef struct _REG_VGC_FIFOFREE { + unsigned FREE : 1; +} REG_VGC_FIFOFREE; + +// VGC_IRQENABLE +typedef struct _REG_VGC_IRQENABLE { + unsigned MH : 1; + unsigned G2D : 1; + unsigned FIFO : 1; + unsigned FBC : 1; +} REG_VGC_IRQENABLE; + +// VGC_IRQSTATUS +typedef struct _REG_VGC_IRQSTATUS { + unsigned MH : 1; + unsigned G2D : 1; + unsigned FIFO : 1; + unsigned FBC : 1; +} REG_VGC_IRQSTATUS; + +// VGC_IRQ_ACTIVE_CNT +typedef struct _REG_VGC_IRQ_ACTIVE_CNT { + unsigned MH : 8; + unsigned G2D : 8; + unsigned ERRORS : 8; + unsigned FBC : 8; +} REG_VGC_IRQ_ACTIVE_CNT; + +// VGC_MMUCOMMANDSTREAM +typedef struct _REG_VGC_MMUCOMMANDSTREAM { + unsigned DATA : 32; +} REG_VGC_MMUCOMMANDSTREAM; + +// VGC_REVISION +typedef struct _REG_VGC_REVISION { + unsigned MINOR_REVISION : 4; + unsigned MAJOR_REVISION : 4; +} REG_VGC_REVISION; + +// VGC_SYSSTATUS +typedef struct _REG_VGC_SYSSTATUS { + unsigned RESET : 1; +} REG_VGC_SYSSTATUS; + +// G2D_ALPHABLEND +typedef struct _REG_G2D_ALPHABLEND { + unsigned ALPHA : 8; + unsigned OBS_ENABLE : 1; + unsigned CONSTANT : 1; + unsigned INVERT : 1; + unsigned OPTIMIZE : 1; + unsigned MODULATE : 1; + unsigned INVERTMASK : 1; + unsigned PREMULTIPLYDST : 1; + unsigned MASKTOALPHA : 1; +} REG_G2D_ALPHABLEND; + +// G2D_BACKGROUND +typedef struct _REG_G2D_BACKGROUND { + unsigned COLOR : 32; +} REG_G2D_BACKGROUND; + +// G2D_BASE0 +typedef struct _REG_G2D_BASE0 { + unsigned ADDR : 32; +} REG_G2D_BASE0; + +// G2D_BASE1 +typedef struct _REG_G2D_BASE1 { + unsigned ADDR : 32; +} REG_G2D_BASE1; + +// G2D_BASE2 +typedef struct _REG_G2D_BASE2 { + unsigned ADDR : 32; +} REG_G2D_BASE2; + +// G2D_BASE3 +typedef struct _REG_G2D_BASE3 { + unsigned ADDR : 32; +} REG_G2D_BASE3; + +// G2D_BLENDERCFG +typedef struct _REG_G2D_BLENDERCFG { + unsigned PASSES : 3; + unsigned ALPHAPASSES : 2; + unsigned ENABLE : 1; + unsigned OOALPHA : 1; + unsigned OBS_DIVALPHA : 1; + unsigned NOMASK : 1; +} REG_G2D_BLENDERCFG; + +// G2D_BLEND_A0 +typedef struct _REG_G2D_BLEND_A0 { + unsigned OPERATION : 2; + unsigned DST_A : 2; + unsigned DST_B : 2; + unsigned DST_C : 2; + unsigned AR_A : 1; + unsigned AR_B : 1; + unsigned AR_C : 1; + unsigned AR_D : 1; + unsigned INV_A : 1; + unsigned INV_B : 1; + unsigned INV_C : 1; + unsigned INV_D : 1; + unsigned SRC_A : 3; + unsigned SRC_B : 3; + unsigned SRC_C : 3; + unsigned SRC_D : 3; + unsigned CONST_A : 1; + unsigned CONST_B : 1; + unsigned CONST_C : 1; + unsigned CONST_D : 1; +} REG_G2D_BLEND_A0; + +// G2D_BLEND_A1 +typedef struct _REG_G2D_BLEND_A1 { + unsigned OPERATION : 2; + unsigned DST_A : 2; + unsigned DST_B : 2; + unsigned DST_C : 2; + unsigned AR_A : 1; + unsigned AR_B : 1; + unsigned AR_C : 1; + unsigned AR_D : 1; + unsigned INV_A : 1; + unsigned INV_B : 1; + unsigned INV_C : 1; + unsigned INV_D : 1; + unsigned SRC_A : 3; + unsigned SRC_B : 3; + unsigned SRC_C : 3; + unsigned SRC_D : 3; + unsigned CONST_A : 1; + unsigned CONST_B : 1; + unsigned CONST_C : 1; + unsigned CONST_D : 1; +} REG_G2D_BLEND_A1; + +// G2D_BLEND_A2 +typedef struct _REG_G2D_BLEND_A2 { + unsigned OPERATION : 2; + unsigned DST_A : 2; + unsigned DST_B : 2; + unsigned DST_C : 2; + unsigned AR_A : 1; + unsigned AR_B : 1; + unsigned AR_C : 1; + unsigned AR_D : 1; + unsigned INV_A : 1; + unsigned INV_B : 1; + unsigned INV_C : 1; + unsigned INV_D : 1; + unsigned SRC_A : 3; + unsigned SRC_B : 3; + unsigned SRC_C : 3; + unsigned SRC_D : 3; + unsigned CONST_A : 1; + unsigned CONST_B : 1; + unsigned CONST_C : 1; + unsigned CONST_D : 1; +} REG_G2D_BLEND_A2; + +// G2D_BLEND_A3 +typedef struct _REG_G2D_BLEND_A3 { + unsigned OPERATION : 2; + unsigned DST_A : 2; + unsigned DST_B : 2; + unsigned DST_C : 2; + unsigned AR_A : 1; + unsigned AR_B : 1; + unsigned AR_C : 1; + unsigned AR_D : 1; + unsigned INV_A : 1; + unsigned INV_B : 1; + unsigned INV_C : 1; + unsigned INV_D : 1; + unsigned SRC_A : 3; + unsigned SRC_B : 3; + unsigned SRC_C : 3; + unsigned SRC_D : 3; + unsigned CONST_A : 1; + unsigned CONST_B : 1; + unsigned CONST_C : 1; + unsigned CONST_D : 1; +} REG_G2D_BLEND_A3; + +// G2D_BLEND_C0 +typedef struct _REG_G2D_BLEND_C0 { + unsigned OPERATION : 2; + unsigned DST_A : 2; + unsigned DST_B : 2; + unsigned DST_C : 2; + unsigned AR_A : 1; + unsigned AR_B : 1; + unsigned AR_C : 1; + unsigned AR_D : 1; + unsigned INV_A : 1; + unsigned INV_B : 1; + unsigned INV_C : 1; + unsigned INV_D : 1; + unsigned SRC_A : 3; + unsigned SRC_B : 3; + unsigned SRC_C : 3; + unsigned SRC_D : 3; + unsigned CONST_A : 1; + unsigned CONST_B : 1; + unsigned CONST_C : 1; + unsigned CONST_D : 1; +} REG_G2D_BLEND_C0; + +// G2D_BLEND_C1 +typedef struct _REG_G2D_BLEND_C1 { + unsigned OPERATION : 2; + unsigned DST_A : 2; + unsigned DST_B : 2; + unsigned DST_C : 2; + unsigned AR_A : 1; + unsigned AR_B : 1; + unsigned AR_C : 1; + unsigned AR_D : 1; + unsigned INV_A : 1; + unsigned INV_B : 1; + unsigned INV_C : 1; + unsigned INV_D : 1; + unsigned SRC_A : 3; + unsigned SRC_B : 3; + unsigned SRC_C : 3; + unsigned SRC_D : 3; + unsigned CONST_A : 1; + unsigned CONST_B : 1; + unsigned CONST_C : 1; + unsigned CONST_D : 1; +} REG_G2D_BLEND_C1; + +// G2D_BLEND_C2 +typedef struct _REG_G2D_BLEND_C2 { + unsigned OPERATION : 2; + unsigned DST_A : 2; + unsigned DST_B : 2; + unsigned DST_C : 2; + unsigned AR_A : 1; + unsigned AR_B : 1; + unsigned AR_C : 1; + unsigned AR_D : 1; + unsigned INV_A : 1; + unsigned INV_B : 1; + unsigned INV_C : 1; + unsigned INV_D : 1; + unsigned SRC_A : 3; + unsigned SRC_B : 3; + unsigned SRC_C : 3; + unsigned SRC_D : 3; + unsigned CONST_A : 1; + unsigned CONST_B : 1; + unsigned CONST_C : 1; + unsigned CONST_D : 1; +} REG_G2D_BLEND_C2; + +// G2D_BLEND_C3 +typedef struct _REG_G2D_BLEND_C3 { + unsigned OPERATION : 2; + unsigned DST_A : 2; + unsigned DST_B : 2; + unsigned DST_C : 2; + unsigned AR_A : 1; + unsigned AR_B : 1; + unsigned AR_C : 1; + unsigned AR_D : 1; + unsigned INV_A : 1; + unsigned INV_B : 1; + unsigned INV_C : 1; + unsigned INV_D : 1; + unsigned SRC_A : 3; + unsigned SRC_B : 3; + unsigned SRC_C : 3; + unsigned SRC_D : 3; + unsigned CONST_A : 1; + unsigned CONST_B : 1; + unsigned CONST_C : 1; + unsigned CONST_D : 1; +} REG_G2D_BLEND_C3; + +// G2D_BLEND_C4 +typedef struct _REG_G2D_BLEND_C4 { + unsigned OPERATION : 2; + unsigned DST_A : 2; + unsigned DST_B : 2; + unsigned DST_C : 2; + unsigned AR_A : 1; + unsigned AR_B : 1; + unsigned AR_C : 1; + unsigned AR_D : 1; + unsigned INV_A : 1; + unsigned INV_B : 1; + unsigned INV_C : 1; + unsigned INV_D : 1; + unsigned SRC_A : 3; + unsigned SRC_B : 3; + unsigned SRC_C : 3; + unsigned SRC_D : 3; + unsigned CONST_A : 1; + unsigned CONST_B : 1; + unsigned CONST_C : 1; + unsigned CONST_D : 1; +} REG_G2D_BLEND_C4; + +// G2D_BLEND_C5 +typedef struct _REG_G2D_BLEND_C5 { + unsigned OPERATION : 2; + unsigned DST_A : 2; + unsigned DST_B : 2; + unsigned DST_C : 2; + unsigned AR_A : 1; + unsigned AR_B : 1; + unsigned AR_C : 1; + unsigned AR_D : 1; + unsigned INV_A : 1; + unsigned INV_B : 1; + unsigned INV_C : 1; + unsigned INV_D : 1; + unsigned SRC_A : 3; + unsigned SRC_B : 3; + unsigned SRC_C : 3; + unsigned SRC_D : 3; + unsigned CONST_A : 1; + unsigned CONST_B : 1; + unsigned CONST_C : 1; + unsigned CONST_D : 1; +} REG_G2D_BLEND_C5; + +// G2D_BLEND_C6 +typedef struct _REG_G2D_BLEND_C6 { + unsigned OPERATION : 2; + unsigned DST_A : 2; + unsigned DST_B : 2; + unsigned DST_C : 2; + unsigned AR_A : 1; + unsigned AR_B : 1; + unsigned AR_C : 1; + unsigned AR_D : 1; + unsigned INV_A : 1; + unsigned INV_B : 1; + unsigned INV_C : 1; + unsigned INV_D : 1; + unsigned SRC_A : 3; + unsigned SRC_B : 3; + unsigned SRC_C : 3; + unsigned SRC_D : 3; + unsigned CONST_A : 1; + unsigned CONST_B : 1; + unsigned CONST_C : 1; + unsigned CONST_D : 1; +} REG_G2D_BLEND_C6; + +// G2D_BLEND_C7 +typedef struct _REG_G2D_BLEND_C7 { + unsigned OPERATION : 2; + unsigned DST_A : 2; + unsigned DST_B : 2; + unsigned DST_C : 2; + unsigned AR_A : 1; + unsigned AR_B : 1; + unsigned AR_C : 1; + unsigned AR_D : 1; + unsigned INV_A : 1; + unsigned INV_B : 1; + unsigned INV_C : 1; + unsigned INV_D : 1; + unsigned SRC_A : 3; + unsigned SRC_B : 3; + unsigned SRC_C : 3; + unsigned SRC_D : 3; + unsigned CONST_A : 1; + unsigned CONST_B : 1; + unsigned CONST_C : 1; + unsigned CONST_D : 1; +} REG_G2D_BLEND_C7; + +// G2D_CFG0 +typedef struct _REG_G2D_CFG0 { + unsigned STRIDE : 12; + unsigned FORMAT : 4; + unsigned TILED : 1; + unsigned SRGB : 1; + unsigned SWAPWORDS : 1; + unsigned SWAPBYTES : 1; + unsigned SWAPALL : 1; + unsigned SWAPRB : 1; + unsigned SWAPBITS : 1; + unsigned STRIDESIGN : 1; +} REG_G2D_CFG0; + +// G2D_CFG1 +typedef struct _REG_G2D_CFG1 { + unsigned STRIDE : 12; + unsigned FORMAT : 4; + unsigned TILED : 1; + unsigned SRGB : 1; + unsigned SWAPWORDS : 1; + unsigned SWAPBYTES : 1; + unsigned SWAPALL : 1; + unsigned SWAPRB : 1; + unsigned SWAPBITS : 1; + unsigned STRIDESIGN : 1; +} REG_G2D_CFG1; + +// G2D_CFG2 +typedef struct _REG_G2D_CFG2 { + unsigned STRIDE : 12; + unsigned FORMAT : 4; + unsigned TILED : 1; + unsigned SRGB : 1; + unsigned SWAPWORDS : 1; + unsigned SWAPBYTES : 1; + unsigned SWAPALL : 1; + unsigned SWAPRB : 1; + unsigned SWAPBITS : 1; + unsigned STRIDESIGN : 1; +} REG_G2D_CFG2; + +// G2D_CFG3 +typedef struct _REG_G2D_CFG3 { + unsigned STRIDE : 12; + unsigned FORMAT : 4; + unsigned TILED : 1; + unsigned SRGB : 1; + unsigned SWAPWORDS : 1; + unsigned SWAPBYTES : 1; + unsigned SWAPALL : 1; + unsigned SWAPRB : 1; + unsigned SWAPBITS : 1; + unsigned STRIDESIGN : 1; +} REG_G2D_CFG3; + +// G2D_COLOR +typedef struct _REG_G2D_COLOR { + unsigned ARGB : 32; +} REG_G2D_COLOR; + +// G2D_CONFIG +typedef struct _REG_G2D_CONFIG { + unsigned DST : 1; + unsigned SRC1 : 1; + unsigned SRC2 : 1; + unsigned SRC3 : 1; + unsigned SRCCK : 1; + unsigned DSTCK : 1; + unsigned ROTATE : 2; + unsigned OBS_GAMMA : 1; + unsigned IGNORECKALPHA : 1; + unsigned DITHER : 1; + unsigned WRITESRGB : 1; + unsigned ARGBMASK : 4; + unsigned ALPHATEX : 1; + unsigned PALMLINES : 1; + unsigned NOLASTPIXEL : 1; + unsigned NOPROTECT : 1; +} REG_G2D_CONFIG; + +// G2D_CONST0 +typedef struct _REG_G2D_CONST0 { + unsigned ARGB : 32; +} REG_G2D_CONST0; + +// G2D_CONST1 +typedef struct _REG_G2D_CONST1 { + unsigned ARGB : 32; +} REG_G2D_CONST1; + +// G2D_CONST2 +typedef struct _REG_G2D_CONST2 { + unsigned ARGB : 32; +} REG_G2D_CONST2; + +// G2D_CONST3 +typedef struct _REG_G2D_CONST3 { + unsigned ARGB : 32; +} REG_G2D_CONST3; + +// G2D_CONST4 +typedef struct _REG_G2D_CONST4 { + unsigned ARGB : 32; +} REG_G2D_CONST4; + +// G2D_CONST5 +typedef struct _REG_G2D_CONST5 { + unsigned ARGB : 32; +} REG_G2D_CONST5; + +// G2D_CONST6 +typedef struct _REG_G2D_CONST6 { + unsigned ARGB : 32; +} REG_G2D_CONST6; + +// G2D_CONST7 +typedef struct _REG_G2D_CONST7 { + unsigned ARGB : 32; +} REG_G2D_CONST7; + +// G2D_FOREGROUND +typedef struct _REG_G2D_FOREGROUND { + unsigned COLOR : 32; +} REG_G2D_FOREGROUND; + +// G2D_GRADIENT +typedef struct _REG_G2D_GRADIENT { + unsigned INSTRUCTIONS : 3; + unsigned INSTRUCTIONS2 : 3; + unsigned ENABLE : 1; + unsigned ENABLE2 : 1; + unsigned SEL : 1; +} REG_G2D_GRADIENT; + +// G2D_IDLE +typedef struct _REG_G2D_IDLE { + unsigned IRQ : 1; + unsigned BCFLUSH : 1; + unsigned V3 : 1; +} REG_G2D_IDLE; + +// G2D_INPUT +typedef struct _REG_G2D_INPUT { + unsigned COLOR : 1; + unsigned SCOORD1 : 1; + unsigned SCOORD2 : 1; + unsigned COPYCOORD : 1; + unsigned VGMODE : 1; + unsigned LINEMODE : 1; +} REG_G2D_INPUT; + +// G2D_MASK +typedef struct _REG_G2D_MASK { + unsigned YMASK : 12; + unsigned XMASK : 12; +} REG_G2D_MASK; + +// G2D_ROP +typedef struct _REG_G2D_ROP { + unsigned ROP : 16; +} REG_G2D_ROP; + +// G2D_SCISSORX +typedef struct _REG_G2D_SCISSORX { + unsigned LEFT : 11; + unsigned RIGHT : 11; +} REG_G2D_SCISSORX; + +// G2D_SCISSORY +typedef struct _REG_G2D_SCISSORY { + unsigned TOP : 11; + unsigned BOTTOM : 11; +} REG_G2D_SCISSORY; + +// G2D_SXY +typedef struct _REG_G2D_SXY { + unsigned Y : 11; + unsigned PAD : 5; + unsigned X : 11; +} REG_G2D_SXY; + +// G2D_SXY2 +typedef struct _REG_G2D_SXY2 { + unsigned Y : 11; + unsigned PAD : 5; + unsigned X : 11; +} REG_G2D_SXY2; + +// G2D_VGSPAN +typedef struct _REG_G2D_VGSPAN { + int WIDTH : 12; + unsigned PAD : 4; + unsigned COVERAGE : 4; +} REG_G2D_VGSPAN; + +// G2D_WIDTHHEIGHT +typedef struct _REG_G2D_WIDTHHEIGHT { + int HEIGHT : 12; + unsigned PAD : 4; + int WIDTH : 12; +} REG_G2D_WIDTHHEIGHT; + +// G2D_XY +typedef struct _REG_G2D_XY { + int Y : 12; + unsigned PAD : 4; + int X : 12; +} REG_G2D_XY; + +// GRADW_BORDERCOLOR +typedef struct _REG_GRADW_BORDERCOLOR { + unsigned COLOR : 32; +} REG_GRADW_BORDERCOLOR; + +// GRADW_CONST0 +typedef struct _REG_GRADW_CONST0 { + unsigned VALUE : 16; +} REG_GRADW_CONST0; + +// GRADW_CONST1 +typedef struct _REG_GRADW_CONST1 { + unsigned VALUE : 16; +} REG_GRADW_CONST1; + +// GRADW_CONST2 +typedef struct _REG_GRADW_CONST2 { + unsigned VALUE : 16; +} REG_GRADW_CONST2; + +// GRADW_CONST3 +typedef struct _REG_GRADW_CONST3 { + unsigned VALUE : 16; +} REG_GRADW_CONST3; + +// GRADW_CONST4 +typedef struct _REG_GRADW_CONST4 { + unsigned VALUE : 16; +} REG_GRADW_CONST4; + +// GRADW_CONST5 +typedef struct _REG_GRADW_CONST5 { + unsigned VALUE : 16; +} REG_GRADW_CONST5; + +// GRADW_CONST6 +typedef struct _REG_GRADW_CONST6 { + unsigned VALUE : 16; +} REG_GRADW_CONST6; + +// GRADW_CONST7 +typedef struct _REG_GRADW_CONST7 { + unsigned VALUE : 16; +} REG_GRADW_CONST7; + +// GRADW_CONST8 +typedef struct _REG_GRADW_CONST8 { + unsigned VALUE : 16; +} REG_GRADW_CONST8; + +// GRADW_CONST9 +typedef struct _REG_GRADW_CONST9 { + unsigned VALUE : 16; +} REG_GRADW_CONST9; + +// GRADW_CONSTA +typedef struct _REG_GRADW_CONSTA { + unsigned VALUE : 16; +} REG_GRADW_CONSTA; + +// GRADW_CONSTB +typedef struct _REG_GRADW_CONSTB { + unsigned VALUE : 16; +} REG_GRADW_CONSTB; + +// GRADW_INST0 +typedef struct _REG_GRADW_INST0 { + unsigned SRC_E : 5; + unsigned SRC_D : 5; + unsigned SRC_C : 5; + unsigned SRC_B : 5; + unsigned SRC_A : 5; + unsigned DST : 4; + unsigned OPCODE : 2; +} REG_GRADW_INST0; + +// GRADW_INST1 +typedef struct _REG_GRADW_INST1 { + unsigned SRC_E : 5; + unsigned SRC_D : 5; + unsigned SRC_C : 5; + unsigned SRC_B : 5; + unsigned SRC_A : 5; + unsigned DST : 4; + unsigned OPCODE : 2; +} REG_GRADW_INST1; + +// GRADW_INST2 +typedef struct _REG_GRADW_INST2 { + unsigned SRC_E : 5; + unsigned SRC_D : 5; + unsigned SRC_C : 5; + unsigned SRC_B : 5; + unsigned SRC_A : 5; + unsigned DST : 4; + unsigned OPCODE : 2; +} REG_GRADW_INST2; + +// GRADW_INST3 +typedef struct _REG_GRADW_INST3 { + unsigned SRC_E : 5; + unsigned SRC_D : 5; + unsigned SRC_C : 5; + unsigned SRC_B : 5; + unsigned SRC_A : 5; + unsigned DST : 4; + unsigned OPCODE : 2; +} REG_GRADW_INST3; + +// GRADW_INST4 +typedef struct _REG_GRADW_INST4 { + unsigned SRC_E : 5; + unsigned SRC_D : 5; + unsigned SRC_C : 5; + unsigned SRC_B : 5; + unsigned SRC_A : 5; + unsigned DST : 4; + unsigned OPCODE : 2; +} REG_GRADW_INST4; + +// GRADW_INST5 +typedef struct _REG_GRADW_INST5 { + unsigned SRC_E : 5; + unsigned SRC_D : 5; + unsigned SRC_C : 5; + unsigned SRC_B : 5; + unsigned SRC_A : 5; + unsigned DST : 4; + unsigned OPCODE : 2; +} REG_GRADW_INST5; + +// GRADW_INST6 +typedef struct _REG_GRADW_INST6 { + unsigned SRC_E : 5; + unsigned SRC_D : 5; + unsigned SRC_C : 5; + unsigned SRC_B : 5; + unsigned SRC_A : 5; + unsigned DST : 4; + unsigned OPCODE : 2; +} REG_GRADW_INST6; + +// GRADW_INST7 +typedef struct _REG_GRADW_INST7 { + unsigned SRC_E : 5; + unsigned SRC_D : 5; + unsigned SRC_C : 5; + unsigned SRC_B : 5; + unsigned SRC_A : 5; + unsigned DST : 4; + unsigned OPCODE : 2; +} REG_GRADW_INST7; + +// GRADW_TEXBASE +typedef struct _REG_GRADW_TEXBASE { + unsigned ADDR : 32; +} REG_GRADW_TEXBASE; + +// GRADW_TEXCFG +typedef struct _REG_GRADW_TEXCFG { + unsigned STRIDE : 12; + unsigned FORMAT : 4; + unsigned TILED : 1; + unsigned WRAPU : 2; + unsigned WRAPV : 2; + unsigned BILIN : 1; + unsigned SRGB : 1; + unsigned PREMULTIPLY : 1; + unsigned SWAPWORDS : 1; + unsigned SWAPBYTES : 1; + unsigned SWAPALL : 1; + unsigned SWAPRB : 1; + unsigned TEX2D : 1; + unsigned SWAPBITS : 1; +} REG_GRADW_TEXCFG; + +// GRADW_TEXSIZE +typedef struct _REG_GRADW_TEXSIZE { + unsigned WIDTH : 11; + unsigned HEIGHT : 11; +} REG_GRADW_TEXSIZE; + +// MH_ARBITER_CONFIG +typedef struct _REG_MH_ARBITER_CONFIG { + unsigned SAME_PAGE_LIMIT : 6; + unsigned SAME_PAGE_GRANULARITY : 1; + unsigned L1_ARB_ENABLE : 1; + unsigned L1_ARB_HOLD_ENABLE : 1; + unsigned L2_ARB_CONTROL : 1; + unsigned PAGE_SIZE : 3; + unsigned TC_REORDER_ENABLE : 1; + unsigned TC_ARB_HOLD_ENABLE : 1; + unsigned IN_FLIGHT_LIMIT_ENABLE : 1; + unsigned IN_FLIGHT_LIMIT : 6; + unsigned CP_CLNT_ENABLE : 1; + unsigned VGT_CLNT_ENABLE : 1; + unsigned TC_CLNT_ENABLE : 1; + unsigned RB_CLNT_ENABLE : 1; + unsigned PA_CLNT_ENABLE : 1; +} REG_MH_ARBITER_CONFIG; + +// MH_AXI_ERROR +typedef struct _REG_MH_AXI_ERROR { + unsigned AXI_READ_ID : 3; + unsigned AXI_READ_ERROR : 1; + unsigned AXI_WRITE_ID : 3; + unsigned AXI_WRITE_ERROR : 1; +} REG_MH_AXI_ERROR; + +// MH_AXI_HALT_CONTROL +typedef struct _REG_MH_AXI_HALT_CONTROL { + unsigned AXI_HALT : 1; +} REG_MH_AXI_HALT_CONTROL; + +// MH_CLNT_AXI_ID_REUSE +typedef struct _REG_MH_CLNT_AXI_ID_REUSE { + unsigned CPW_ID : 3; + unsigned PAD : 1; + unsigned RBW_ID : 3; + unsigned PAD2 : 1; + unsigned MMUR_ID : 3; + unsigned PAD3 : 1; + unsigned PAW_ID : 3; +} REG_MH_CLNT_AXI_ID_REUSE; + +// MH_DEBUG_CTRL +typedef struct _REG_MH_DEBUG_CTRL { + unsigned INDEX : 6; +} REG_MH_DEBUG_CTRL; + +// MH_DEBUG_DATA +typedef struct _REG_MH_DEBUG_DATA { + unsigned DATA : 32; +} REG_MH_DEBUG_DATA; + +// MH_INTERRUPT_CLEAR +typedef struct _REG_MH_INTERRUPT_CLEAR { + unsigned AXI_READ_ERROR : 1; + unsigned AXI_WRITE_ERROR : 1; + unsigned MMU_PAGE_FAULT : 1; +} REG_MH_INTERRUPT_CLEAR; + +// MH_INTERRUPT_MASK +typedef struct _REG_MH_INTERRUPT_MASK { + unsigned AXI_READ_ERROR : 1; + unsigned AXI_WRITE_ERROR : 1; + unsigned MMU_PAGE_FAULT : 1; +} REG_MH_INTERRUPT_MASK; + +// MH_INTERRUPT_STATUS +typedef struct _REG_MH_INTERRUPT_STATUS { + unsigned AXI_READ_ERROR : 1; + unsigned AXI_WRITE_ERROR : 1; + unsigned MMU_PAGE_FAULT : 1; +} REG_MH_INTERRUPT_STATUS; + +// MH_MMU_CONFIG +typedef struct _REG_MH_MMU_CONFIG { + unsigned MMU_ENABLE : 1; + unsigned SPLIT_MODE_ENABLE : 1; + unsigned PAD : 2; + unsigned RB_W_CLNT_BEHAVIOR : 2; + unsigned CP_W_CLNT_BEHAVIOR : 2; + unsigned CP_R0_CLNT_BEHAVIOR : 2; + unsigned CP_R1_CLNT_BEHAVIOR : 2; + unsigned CP_R2_CLNT_BEHAVIOR : 2; + unsigned CP_R3_CLNT_BEHAVIOR : 2; + unsigned CP_R4_CLNT_BEHAVIOR : 2; + unsigned VGT_R0_CLNT_BEHAVIOR : 2; + unsigned VGT_R1_CLNT_BEHAVIOR : 2; + unsigned TC_R_CLNT_BEHAVIOR : 2; + unsigned PA_W_CLNT_BEHAVIOR : 2; +} REG_MH_MMU_CONFIG; + +// MH_MMU_INVALIDATE +typedef struct _REG_MH_MMU_INVALIDATE { + unsigned INVALIDATE_ALL : 1; + unsigned INVALIDATE_TC : 1; +} REG_MH_MMU_INVALIDATE; + +// MH_MMU_MPU_BASE +typedef struct _REG_MH_MMU_MPU_BASE { + unsigned ZERO : 12; + unsigned MPU_BASE : 20; +} REG_MH_MMU_MPU_BASE; + +// MH_MMU_MPU_END +typedef struct _REG_MH_MMU_MPU_END { + unsigned ZERO : 12; + unsigned MPU_END : 20; +} REG_MH_MMU_MPU_END; + +// MH_MMU_PAGE_FAULT +typedef struct _REG_MH_MMU_PAGE_FAULT { + unsigned PAGE_FAULT : 1; + unsigned OP_TYPE : 1; + unsigned CLNT_BEHAVIOR : 2; + unsigned AXI_ID : 3; + unsigned PAD : 1; + unsigned MPU_ADDRESS_OUT_OF_RANGE : 1; + unsigned ADDRESS_OUT_OF_RANGE : 1; + unsigned READ_PROTECTION_ERROR : 1; + unsigned WRITE_PROTECTION_ERROR : 1; + unsigned REQ_VA : 20; +} REG_MH_MMU_PAGE_FAULT; + +// MH_MMU_PT_BASE +typedef struct _REG_MH_MMU_PT_BASE { + unsigned ZERO : 12; + unsigned PT_BASE : 20; +} REG_MH_MMU_PT_BASE; + +// MH_MMU_TRAN_ERROR +typedef struct _REG_MH_MMU_TRAN_ERROR { + unsigned ZERO : 5; + unsigned TRAN_ERROR : 27; +} REG_MH_MMU_TRAN_ERROR; + +// MH_MMU_VA_RANGE +typedef struct _REG_MH_MMU_VA_RANGE { + unsigned NUM_64KB_REGIONS : 12; + unsigned VA_BASE : 20; +} REG_MH_MMU_VA_RANGE; + +// MH_PERFCOUNTER0_CONFIG +typedef struct _REG_MH_PERFCOUNTER0_CONFIG { + unsigned N_VALUE : 8; +} REG_MH_PERFCOUNTER0_CONFIG; + +// MH_PERFCOUNTER0_HI +typedef struct _REG_MH_PERFCOUNTER0_HI { + unsigned PERF_COUNTER_HI : 16; +} REG_MH_PERFCOUNTER0_HI; + +// MH_PERFCOUNTER0_LOW +typedef struct _REG_MH_PERFCOUNTER0_LOW { + unsigned PERF_COUNTER_LOW : 32; +} REG_MH_PERFCOUNTER0_LOW; + +// MH_PERFCOUNTER0_SELECT +typedef struct _REG_MH_PERFCOUNTER0_SELECT { + unsigned PERF_SEL : 8; +} REG_MH_PERFCOUNTER0_SELECT; + +// MH_PERFCOUNTER1_CONFIG +typedef struct _REG_MH_PERFCOUNTER1_CONFIG { + unsigned N_VALUE : 8; +} REG_MH_PERFCOUNTER1_CONFIG; + +// MH_PERFCOUNTER1_HI +typedef struct _REG_MH_PERFCOUNTER1_HI { + unsigned PERF_COUNTER_HI : 16; +} REG_MH_PERFCOUNTER1_HI; + +// MH_PERFCOUNTER1_LOW +typedef struct _REG_MH_PERFCOUNTER1_LOW { + unsigned PERF_COUNTER_LOW : 32; +} REG_MH_PERFCOUNTER1_LOW; + +// MH_PERFCOUNTER1_SELECT +typedef struct _REG_MH_PERFCOUNTER1_SELECT { + unsigned PERF_SEL : 8; +} REG_MH_PERFCOUNTER1_SELECT; + +// MMU_READ_ADDR +typedef struct _REG_MMU_READ_ADDR { + unsigned ADDR : 15; +} REG_MMU_READ_ADDR; + +// MMU_READ_DATA +typedef struct _REG_MMU_READ_DATA { + unsigned DATA : 32; +} REG_MMU_READ_DATA; + +// VGV1_CBASE1 +typedef struct _REG_VGV1_CBASE1 { + unsigned ADDR : 32; +} REG_VGV1_CBASE1; + +// VGV1_CFG1 +typedef struct _REG_VGV1_CFG1 { + unsigned WINDRULE : 1; +} REG_VGV1_CFG1; + +// VGV1_CFG2 +typedef struct _REG_VGV1_CFG2 { + unsigned AAMODE : 2; +} REG_VGV1_CFG2; + +// VGV1_DIRTYBASE +typedef struct _REG_VGV1_DIRTYBASE { + unsigned ADDR : 32; +} REG_VGV1_DIRTYBASE; + +// VGV1_FILL +typedef struct _REG_VGV1_FILL { + unsigned INHERIT : 1; +} REG_VGV1_FILL; + +// VGV1_SCISSORX +typedef struct _REG_VGV1_SCISSORX { + unsigned LEFT : 11; + unsigned PAD : 5; + unsigned RIGHT : 11; +} REG_VGV1_SCISSORX; + +// VGV1_SCISSORY +typedef struct _REG_VGV1_SCISSORY { + unsigned TOP : 11; + unsigned PAD : 5; + unsigned BOTTOM : 11; +} REG_VGV1_SCISSORY; + +// VGV1_TILEOFS +typedef struct _REG_VGV1_TILEOFS { + unsigned X : 12; + unsigned Y : 12; + unsigned LEFTMOST : 1; +} REG_VGV1_TILEOFS; + +// VGV1_UBASE2 +typedef struct _REG_VGV1_UBASE2 { + unsigned ADDR : 32; +} REG_VGV1_UBASE2; + +// VGV1_VTX0 +typedef struct _REG_VGV1_VTX0 { + int X : 16; + int Y : 16; +} REG_VGV1_VTX0; + +// VGV1_VTX1 +typedef struct _REG_VGV1_VTX1 { + int X : 16; + int Y : 16; +} REG_VGV1_VTX1; + +// VGV2_ACCURACY +typedef struct _REG_VGV2_ACCURACY { + unsigned F : 24; +} REG_VGV2_ACCURACY; + +// VGV2_ACTION +typedef struct _REG_VGV2_ACTION { + unsigned ACTION : 4; +} REG_VGV2_ACTION; + +// VGV2_ARCCOS +typedef struct _REG_VGV2_ARCCOS { + unsigned F : 24; +} REG_VGV2_ARCCOS; + +// VGV2_ARCSIN +typedef struct _REG_VGV2_ARCSIN { + unsigned F : 24; +} REG_VGV2_ARCSIN; + +// VGV2_ARCTAN +typedef struct _REG_VGV2_ARCTAN { + unsigned F : 24; +} REG_VGV2_ARCTAN; + +// VGV2_BBOXMAXX +typedef struct _REG_VGV2_BBOXMAXX { + unsigned F : 24; +} REG_VGV2_BBOXMAXX; + +// VGV2_BBOXMAXY +typedef struct _REG_VGV2_BBOXMAXY { + unsigned F : 24; +} REG_VGV2_BBOXMAXY; + +// VGV2_BBOXMINX +typedef struct _REG_VGV2_BBOXMINX { + unsigned F : 24; +} REG_VGV2_BBOXMINX; + +// VGV2_BBOXMINY +typedef struct _REG_VGV2_BBOXMINY { + unsigned F : 24; +} REG_VGV2_BBOXMINY; + +// VGV2_BIAS +typedef struct _REG_VGV2_BIAS { + unsigned F : 24; +} REG_VGV2_BIAS; + +// VGV2_C1X +typedef struct _REG_VGV2_C1X { + unsigned F : 24; +} REG_VGV2_C1X; + +// VGV2_C1XREL +typedef struct _REG_VGV2_C1XREL { + unsigned F : 24; +} REG_VGV2_C1XREL; + +// VGV2_C1Y +typedef struct _REG_VGV2_C1Y { + unsigned F : 24; +} REG_VGV2_C1Y; + +// VGV2_C1YREL +typedef struct _REG_VGV2_C1YREL { + unsigned F : 24; +} REG_VGV2_C1YREL; + +// VGV2_C2X +typedef struct _REG_VGV2_C2X { + unsigned F : 24; +} REG_VGV2_C2X; + +// VGV2_C2XREL +typedef struct _REG_VGV2_C2XREL { + unsigned F : 24; +} REG_VGV2_C2XREL; + +// VGV2_C2Y +typedef struct _REG_VGV2_C2Y { + unsigned F : 24; +} REG_VGV2_C2Y; + +// VGV2_C2YREL +typedef struct _REG_VGV2_C2YREL { + unsigned F : 24; +} REG_VGV2_C2YREL; + +// VGV2_C3X +typedef struct _REG_VGV2_C3X { + unsigned F : 24; +} REG_VGV2_C3X; + +// VGV2_C3XREL +typedef struct _REG_VGV2_C3XREL { + unsigned F : 24; +} REG_VGV2_C3XREL; + +// VGV2_C3Y +typedef struct _REG_VGV2_C3Y { + unsigned F : 24; +} REG_VGV2_C3Y; + +// VGV2_C3YREL +typedef struct _REG_VGV2_C3YREL { + unsigned F : 24; +} REG_VGV2_C3YREL; + +// VGV2_C4X +typedef struct _REG_VGV2_C4X { + unsigned F : 24; +} REG_VGV2_C4X; + +// VGV2_C4XREL +typedef struct _REG_VGV2_C4XREL { + unsigned F : 24; +} REG_VGV2_C4XREL; + +// VGV2_C4Y +typedef struct _REG_VGV2_C4Y { + unsigned F : 24; +} REG_VGV2_C4Y; + +// VGV2_C4YREL +typedef struct _REG_VGV2_C4YREL { + unsigned F : 24; +} REG_VGV2_C4YREL; + +// VGV2_CLIP +typedef struct _REG_VGV2_CLIP { + unsigned F : 24; +} REG_VGV2_CLIP; + +// VGV2_FIRST +typedef struct _REG_VGV2_FIRST { + unsigned DUMMY : 1; +} REG_VGV2_FIRST; + +// VGV2_LAST +typedef struct _REG_VGV2_LAST { + unsigned DUMMY : 1; +} REG_VGV2_LAST; + +// VGV2_MITER +typedef struct _REG_VGV2_MITER { + unsigned F : 24; +} REG_VGV2_MITER; + +// VGV2_MODE +typedef struct _REG_VGV2_MODE { + unsigned MAXSPLIT : 4; + unsigned CAP : 2; + unsigned JOIN : 2; + unsigned STROKE : 1; + unsigned STROKESPLIT : 1; + unsigned FULLSPLIT : 1; + unsigned NODOTS : 1; + unsigned OPENFILL : 1; + unsigned DROPLEFT : 1; + unsigned DROPOTHER : 1; + unsigned SYMMETRICJOINS : 1; + unsigned SIMPLESTROKE : 1; + unsigned SIMPLECLIP : 1; + int EXPONENTADD : 6; +} REG_VGV2_MODE; + +// VGV2_RADIUS +typedef struct _REG_VGV2_RADIUS { + unsigned F : 24; +} REG_VGV2_RADIUS; + +// VGV2_SCALE +typedef struct _REG_VGV2_SCALE { + unsigned F : 24; +} REG_VGV2_SCALE; + +// VGV2_THINRADIUS +typedef struct _REG_VGV2_THINRADIUS { + unsigned F : 24; +} REG_VGV2_THINRADIUS; + +// VGV2_XFSTXX +typedef struct _REG_VGV2_XFSTXX { + unsigned F : 24; +} REG_VGV2_XFSTXX; + +// VGV2_XFSTXY +typedef struct _REG_VGV2_XFSTXY { + unsigned F : 24; +} REG_VGV2_XFSTXY; + +// VGV2_XFSTYX +typedef struct _REG_VGV2_XFSTYX { + unsigned F : 24; +} REG_VGV2_XFSTYX; + +// VGV2_XFSTYY +typedef struct _REG_VGV2_XFSTYY { + unsigned F : 24; +} REG_VGV2_XFSTYY; + +// VGV2_XFXA +typedef struct _REG_VGV2_XFXA { + unsigned F : 24; +} REG_VGV2_XFXA; + +// VGV2_XFXX +typedef struct _REG_VGV2_XFXX { + unsigned F : 24; +} REG_VGV2_XFXX; + +// VGV2_XFXY +typedef struct _REG_VGV2_XFXY { + unsigned F : 24; +} REG_VGV2_XFXY; + +// VGV2_XFYA +typedef struct _REG_VGV2_XFYA { + unsigned F : 24; +} REG_VGV2_XFYA; + +// VGV2_XFYX +typedef struct _REG_VGV2_XFYX { + unsigned F : 24; +} REG_VGV2_XFYX; + +// VGV2_XFYY +typedef struct _REG_VGV2_XFYY { + unsigned F : 24; +} REG_VGV2_XFYY; + +// VGV3_CONTROL +typedef struct _REG_VGV3_CONTROL { + unsigned MARKADD : 12; + unsigned DMIWAITCHMASK : 4; + unsigned PAUSE : 1; + unsigned ABORT : 1; + unsigned WRITE : 1; + unsigned BCFLUSH : 1; + unsigned V0SYNC : 1; + unsigned DMIWAITBUF : 3; +} REG_VGV3_CONTROL; + +// VGV3_FIRST +typedef struct _REG_VGV3_FIRST { + unsigned DUMMY : 1; +} REG_VGV3_FIRST; + +// VGV3_LAST +typedef struct _REG_VGV3_LAST { + unsigned DUMMY : 1; +} REG_VGV3_LAST; + +// VGV3_MODE +typedef struct _REG_VGV3_MODE { + unsigned FLIPENDIAN : 1; + unsigned UNUSED : 1; + unsigned WRITEFLUSH : 1; + unsigned DMIPAUSETYPE : 1; + unsigned DMIRESET : 1; +} REG_VGV3_MODE; + +// VGV3_NEXTADDR +typedef struct _REG_VGV3_NEXTADDR { + unsigned CALLADDR : 32; +} REG_VGV3_NEXTADDR; + +// VGV3_NEXTCMD +typedef struct _REG_VGV3_NEXTCMD { + unsigned COUNT : 12; + unsigned NEXTCMD : 3; + unsigned MARK : 1; + unsigned CALLCOUNT : 12; +} REG_VGV3_NEXTCMD; + +// VGV3_VGBYPASS +typedef struct _REG_VGV3_VGBYPASS { + unsigned BYPASS : 1; +} REG_VGV3_VGBYPASS; + +// VGV3_WRITE +typedef struct _REG_VGV3_WRITE { + unsigned VALUE : 32; +} REG_VGV3_WRITE; + +// VGV3_WRITEADDR +typedef struct _REG_VGV3_WRITEADDR { + unsigned ADDR : 32; +} REG_VGV3_WRITEADDR; + +// VGV3_WRITEDMI +typedef struct _REG_VGV3_WRITEDMI { + unsigned CHANMASK : 4; + unsigned BUFFER : 3; +} REG_VGV3_WRITEDMI; + +// VGV3_WRITEF32 +typedef struct _REG_VGV3_WRITEF32 { + unsigned ADDR : 8; + unsigned COUNT : 8; + unsigned LOOP : 4; + unsigned ACTION : 4; + unsigned FORMAT : 3; +} REG_VGV3_WRITEF32; + +// VGV3_WRITEIFPAUSED +typedef struct _REG_VGV3_WRITEIFPAUSED { + unsigned VALUE : 32; +} REG_VGV3_WRITEIFPAUSED; + +// VGV3_WRITERAW +typedef struct _REG_VGV3_WRITERAW { + unsigned ADDR : 8; + unsigned COUNT : 8; + unsigned LOOP : 4; + unsigned ACTION : 4; + unsigned FORMAT : 3; +} REG_VGV3_WRITERAW; + +// VGV3_WRITES16 +typedef struct _REG_VGV3_WRITES16 { + unsigned ADDR : 8; + unsigned COUNT : 8; + unsigned LOOP : 4; + unsigned ACTION : 4; + unsigned FORMAT : 3; +} REG_VGV3_WRITES16; + +// VGV3_WRITES32 +typedef struct _REG_VGV3_WRITES32 { + unsigned ADDR : 8; + unsigned COUNT : 8; + unsigned LOOP : 4; + unsigned ACTION : 4; + unsigned FORMAT : 3; +} REG_VGV3_WRITES32; + +// VGV3_WRITES8 +typedef struct _REG_VGV3_WRITES8 { + unsigned ADDR : 8; + unsigned COUNT : 8; + unsigned LOOP : 4; + unsigned ACTION : 4; + unsigned FORMAT : 3; +} REG_VGV3_WRITES8; + +// Register address, down shift, AND mask +#define FBC_BASE_BASE_FADDR ADDR_FBC_BASE +#define FBC_BASE_BASE_FSHIFT 0 +#define FBC_BASE_BASE_FMASK 0xffffffff +#define FBC_DATA_DATA_FADDR ADDR_FBC_DATA +#define FBC_DATA_DATA_FSHIFT 0 +#define FBC_DATA_DATA_FMASK 0xffffffff +#define FBC_HEIGHT_HEIGHT_FADDR ADDR_FBC_HEIGHT +#define FBC_HEIGHT_HEIGHT_FSHIFT 0 +#define FBC_HEIGHT_HEIGHT_FMASK 0x7ff +#define FBC_START_DUMMY_FADDR ADDR_FBC_START +#define FBC_START_DUMMY_FSHIFT 0 +#define FBC_START_DUMMY_FMASK 0x1 +#define FBC_STRIDE_STRIDE_FADDR ADDR_FBC_STRIDE +#define FBC_STRIDE_STRIDE_FSHIFT 0 +#define FBC_STRIDE_STRIDE_FMASK 0x7ff +#define FBC_WIDTH_WIDTH_FADDR ADDR_FBC_WIDTH +#define FBC_WIDTH_WIDTH_FSHIFT 0 +#define FBC_WIDTH_WIDTH_FMASK 0x7ff +#define VGC_CLOCKEN_BCACHE_FADDR ADDR_VGC_CLOCKEN +#define VGC_CLOCKEN_BCACHE_FSHIFT 0 +#define VGC_CLOCKEN_BCACHE_FMASK 0x1 +#define VGC_CLOCKEN_G2D_VGL3_FADDR ADDR_VGC_CLOCKEN +#define VGC_CLOCKEN_G2D_VGL3_FSHIFT 1 +#define VGC_CLOCKEN_G2D_VGL3_FMASK 0x1 +#define VGC_CLOCKEN_VG_L1L2_FADDR ADDR_VGC_CLOCKEN +#define VGC_CLOCKEN_VG_L1L2_FSHIFT 2 +#define VGC_CLOCKEN_VG_L1L2_FMASK 0x1 +#define VGC_CLOCKEN_RESERVED_FADDR ADDR_VGC_CLOCKEN +#define VGC_CLOCKEN_RESERVED_FSHIFT 3 +#define VGC_CLOCKEN_RESERVED_FMASK 0x7 +#define VGC_COMMANDSTREAM_DATA_FADDR ADDR_VGC_COMMANDSTREAM +#define VGC_COMMANDSTREAM_DATA_FSHIFT 0 +#define VGC_COMMANDSTREAM_DATA_FMASK 0xffffffff +#define VGC_FIFOFREE_FREE_FADDR ADDR_VGC_FIFOFREE +#define VGC_FIFOFREE_FREE_FSHIFT 0 +#define VGC_FIFOFREE_FREE_FMASK 0x1 +#define VGC_IRQENABLE_MH_FADDR ADDR_VGC_IRQENABLE +#define VGC_IRQENABLE_MH_FSHIFT 0 +#define VGC_IRQENABLE_MH_FMASK 0x1 +#define VGC_IRQENABLE_G2D_FADDR ADDR_VGC_IRQENABLE +#define VGC_IRQENABLE_G2D_FSHIFT 1 +#define VGC_IRQENABLE_G2D_FMASK 0x1 +#define VGC_IRQENABLE_FIFO_FADDR ADDR_VGC_IRQENABLE +#define VGC_IRQENABLE_FIFO_FSHIFT 2 +#define VGC_IRQENABLE_FIFO_FMASK 0x1 +#define VGC_IRQENABLE_FBC_FADDR ADDR_VGC_IRQENABLE +#define VGC_IRQENABLE_FBC_FSHIFT 3 +#define VGC_IRQENABLE_FBC_FMASK 0x1 +#define VGC_IRQSTATUS_MH_FADDR ADDR_VGC_IRQSTATUS +#define VGC_IRQSTATUS_MH_FSHIFT 0 +#define VGC_IRQSTATUS_MH_FMASK 0x1 +#define VGC_IRQSTATUS_G2D_FADDR ADDR_VGC_IRQSTATUS +#define VGC_IRQSTATUS_G2D_FSHIFT 1 +#define VGC_IRQSTATUS_G2D_FMASK 0x1 +#define VGC_IRQSTATUS_FIFO_FADDR ADDR_VGC_IRQSTATUS +#define VGC_IRQSTATUS_FIFO_FSHIFT 2 +#define VGC_IRQSTATUS_FIFO_FMASK 0x1 +#define VGC_IRQSTATUS_FBC_FADDR ADDR_VGC_IRQSTATUS +#define VGC_IRQSTATUS_FBC_FSHIFT 3 +#define VGC_IRQSTATUS_FBC_FMASK 0x1 +#define VGC_IRQ_ACTIVE_CNT_MH_FADDR ADDR_VGC_IRQ_ACTIVE_CNT +#define VGC_IRQ_ACTIVE_CNT_MH_FSHIFT 0 +#define VGC_IRQ_ACTIVE_CNT_MH_FMASK 0xff +#define VGC_IRQ_ACTIVE_CNT_G2D_FADDR ADDR_VGC_IRQ_ACTIVE_CNT +#define VGC_IRQ_ACTIVE_CNT_G2D_FSHIFT 8 +#define VGC_IRQ_ACTIVE_CNT_G2D_FMASK 0xff +#define VGC_IRQ_ACTIVE_CNT_ERRORS_FADDR ADDR_VGC_IRQ_ACTIVE_CNT +#define VGC_IRQ_ACTIVE_CNT_ERRORS_FSHIFT 16 +#define VGC_IRQ_ACTIVE_CNT_ERRORS_FMASK 0xff +#define VGC_IRQ_ACTIVE_CNT_FBC_FADDR ADDR_VGC_IRQ_ACTIVE_CNT +#define VGC_IRQ_ACTIVE_CNT_FBC_FSHIFT 24 +#define VGC_IRQ_ACTIVE_CNT_FBC_FMASK 0xff +#define VGC_MMUCOMMANDSTREAM_DATA_FADDR ADDR_VGC_MMUCOMMANDSTREAM +#define VGC_MMUCOMMANDSTREAM_DATA_FSHIFT 0 +#define VGC_MMUCOMMANDSTREAM_DATA_FMASK 0xffffffff +#define VGC_REVISION_MINOR_REVISION_FADDR ADDR_VGC_REVISION +#define VGC_REVISION_MINOR_REVISION_FSHIFT 0 +#define VGC_REVISION_MINOR_REVISION_FMASK 0xf +#define VGC_REVISION_MAJOR_REVISION_FADDR ADDR_VGC_REVISION +#define VGC_REVISION_MAJOR_REVISION_FSHIFT 4 +#define VGC_REVISION_MAJOR_REVISION_FMASK 0xf +#define VGC_SYSSTATUS_RESET_FADDR ADDR_VGC_SYSSTATUS +#define VGC_SYSSTATUS_RESET_FSHIFT 0 +#define VGC_SYSSTATUS_RESET_FMASK 0x1 +#define G2D_ALPHABLEND_ALPHA_FADDR ADDR_G2D_ALPHABLEND +#define G2D_ALPHABLEND_ALPHA_FSHIFT 0 +#define G2D_ALPHABLEND_ALPHA_FMASK 0xff +#define G2D_ALPHABLEND_OBS_ENABLE_FADDR ADDR_G2D_ALPHABLEND +#define G2D_ALPHABLEND_OBS_ENABLE_FSHIFT 8 +#define G2D_ALPHABLEND_OBS_ENABLE_FMASK 0x1 +#define G2D_ALPHABLEND_CONSTANT_FADDR ADDR_G2D_ALPHABLEND +#define G2D_ALPHABLEND_CONSTANT_FSHIFT 9 +#define G2D_ALPHABLEND_CONSTANT_FMASK 0x1 +#define G2D_ALPHABLEND_INVERT_FADDR ADDR_G2D_ALPHABLEND +#define G2D_ALPHABLEND_INVERT_FSHIFT 10 +#define G2D_ALPHABLEND_INVERT_FMASK 0x1 +#define G2D_ALPHABLEND_OPTIMIZE_FADDR ADDR_G2D_ALPHABLEND +#define G2D_ALPHABLEND_OPTIMIZE_FSHIFT 11 +#define G2D_ALPHABLEND_OPTIMIZE_FMASK 0x1 +#define G2D_ALPHABLEND_MODULATE_FADDR ADDR_G2D_ALPHABLEND +#define G2D_ALPHABLEND_MODULATE_FSHIFT 12 +#define G2D_ALPHABLEND_MODULATE_FMASK 0x1 +#define G2D_ALPHABLEND_INVERTMASK_FADDR ADDR_G2D_ALPHABLEND +#define G2D_ALPHABLEND_INVERTMASK_FSHIFT 13 +#define G2D_ALPHABLEND_INVERTMASK_FMASK 0x1 +#define G2D_ALPHABLEND_PREMULTIPLYDST_FADDR ADDR_G2D_ALPHABLEND +#define G2D_ALPHABLEND_PREMULTIPLYDST_FSHIFT 14 +#define G2D_ALPHABLEND_PREMULTIPLYDST_FMASK 0x1 +#define G2D_ALPHABLEND_MASKTOALPHA_FADDR ADDR_G2D_ALPHABLEND +#define G2D_ALPHABLEND_MASKTOALPHA_FSHIFT 15 +#define G2D_ALPHABLEND_MASKTOALPHA_FMASK 0x1 +#define G2D_BACKGROUND_COLOR_FADDR ADDR_G2D_BACKGROUND +#define G2D_BACKGROUND_COLOR_FSHIFT 0 +#define G2D_BACKGROUND_COLOR_FMASK 0xffffffff +#define G2D_BASE0_ADDR_FADDR ADDR_G2D_BASE0 +#define G2D_BASE0_ADDR_FSHIFT 0 +#define G2D_BASE0_ADDR_FMASK 0xffffffff +#define G2D_BASE1_ADDR_FADDR ADDR_G2D_BASE1 +#define G2D_BASE1_ADDR_FSHIFT 0 +#define G2D_BASE1_ADDR_FMASK 0xffffffff +#define G2D_BASE2_ADDR_FADDR ADDR_G2D_BASE2 +#define G2D_BASE2_ADDR_FSHIFT 0 +#define G2D_BASE2_ADDR_FMASK 0xffffffff +#define G2D_BASE3_ADDR_FADDR ADDR_G2D_BASE3 +#define G2D_BASE3_ADDR_FSHIFT 0 +#define G2D_BASE3_ADDR_FMASK 0xffffffff +#define G2D_BLENDERCFG_PASSES_FADDR ADDR_G2D_BLENDERCFG +#define G2D_BLENDERCFG_PASSES_FSHIFT 0 +#define G2D_BLENDERCFG_PASSES_FMASK 0x7 +#define G2D_BLENDERCFG_ALPHAPASSES_FADDR ADDR_G2D_BLENDERCFG +#define G2D_BLENDERCFG_ALPHAPASSES_FSHIFT 3 +#define G2D_BLENDERCFG_ALPHAPASSES_FMASK 0x3 +#define G2D_BLENDERCFG_ENABLE_FADDR ADDR_G2D_BLENDERCFG +#define G2D_BLENDERCFG_ENABLE_FSHIFT 5 +#define G2D_BLENDERCFG_ENABLE_FMASK 0x1 +#define G2D_BLENDERCFG_OOALPHA_FADDR ADDR_G2D_BLENDERCFG +#define G2D_BLENDERCFG_OOALPHA_FSHIFT 6 +#define G2D_BLENDERCFG_OOALPHA_FMASK 0x1 +#define G2D_BLENDERCFG_OBS_DIVALPHA_FADDR ADDR_G2D_BLENDERCFG +#define G2D_BLENDERCFG_OBS_DIVALPHA_FSHIFT 7 +#define G2D_BLENDERCFG_OBS_DIVALPHA_FMASK 0x1 +#define G2D_BLENDERCFG_NOMASK_FADDR ADDR_G2D_BLENDERCFG +#define G2D_BLENDERCFG_NOMASK_FSHIFT 8 +#define G2D_BLENDERCFG_NOMASK_FMASK 0x1 +#define G2D_BLEND_A0_OPERATION_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_OPERATION_FSHIFT 0 +#define G2D_BLEND_A0_OPERATION_FMASK 0x3 +#define G2D_BLEND_A0_DST_A_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_DST_A_FSHIFT 2 +#define G2D_BLEND_A0_DST_A_FMASK 0x3 +#define G2D_BLEND_A0_DST_B_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_DST_B_FSHIFT 4 +#define G2D_BLEND_A0_DST_B_FMASK 0x3 +#define G2D_BLEND_A0_DST_C_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_DST_C_FSHIFT 6 +#define G2D_BLEND_A0_DST_C_FMASK 0x3 +#define G2D_BLEND_A0_AR_A_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_AR_A_FSHIFT 8 +#define G2D_BLEND_A0_AR_A_FMASK 0x1 +#define G2D_BLEND_A0_AR_B_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_AR_B_FSHIFT 9 +#define G2D_BLEND_A0_AR_B_FMASK 0x1 +#define G2D_BLEND_A0_AR_C_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_AR_C_FSHIFT 10 +#define G2D_BLEND_A0_AR_C_FMASK 0x1 +#define G2D_BLEND_A0_AR_D_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_AR_D_FSHIFT 11 +#define G2D_BLEND_A0_AR_D_FMASK 0x1 +#define G2D_BLEND_A0_INV_A_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_INV_A_FSHIFT 12 +#define G2D_BLEND_A0_INV_A_FMASK 0x1 +#define G2D_BLEND_A0_INV_B_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_INV_B_FSHIFT 13 +#define G2D_BLEND_A0_INV_B_FMASK 0x1 +#define G2D_BLEND_A0_INV_C_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_INV_C_FSHIFT 14 +#define G2D_BLEND_A0_INV_C_FMASK 0x1 +#define G2D_BLEND_A0_INV_D_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_INV_D_FSHIFT 15 +#define G2D_BLEND_A0_INV_D_FMASK 0x1 +#define G2D_BLEND_A0_SRC_A_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_SRC_A_FSHIFT 16 +#define G2D_BLEND_A0_SRC_A_FMASK 0x7 +#define G2D_BLEND_A0_SRC_B_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_SRC_B_FSHIFT 19 +#define G2D_BLEND_A0_SRC_B_FMASK 0x7 +#define G2D_BLEND_A0_SRC_C_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_SRC_C_FSHIFT 22 +#define G2D_BLEND_A0_SRC_C_FMASK 0x7 +#define G2D_BLEND_A0_SRC_D_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_SRC_D_FSHIFT 25 +#define G2D_BLEND_A0_SRC_D_FMASK 0x7 +#define G2D_BLEND_A0_CONST_A_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_CONST_A_FSHIFT 28 +#define G2D_BLEND_A0_CONST_A_FMASK 0x1 +#define G2D_BLEND_A0_CONST_B_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_CONST_B_FSHIFT 29 +#define G2D_BLEND_A0_CONST_B_FMASK 0x1 +#define G2D_BLEND_A0_CONST_C_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_CONST_C_FSHIFT 30 +#define G2D_BLEND_A0_CONST_C_FMASK 0x1 +#define G2D_BLEND_A0_CONST_D_FADDR ADDR_G2D_BLEND_A0 +#define G2D_BLEND_A0_CONST_D_FSHIFT 31 +#define G2D_BLEND_A0_CONST_D_FMASK 0x1 +#define G2D_BLEND_A1_OPERATION_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_OPERATION_FSHIFT 0 +#define G2D_BLEND_A1_OPERATION_FMASK 0x3 +#define G2D_BLEND_A1_DST_A_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_DST_A_FSHIFT 2 +#define G2D_BLEND_A1_DST_A_FMASK 0x3 +#define G2D_BLEND_A1_DST_B_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_DST_B_FSHIFT 4 +#define G2D_BLEND_A1_DST_B_FMASK 0x3 +#define G2D_BLEND_A1_DST_C_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_DST_C_FSHIFT 6 +#define G2D_BLEND_A1_DST_C_FMASK 0x3 +#define G2D_BLEND_A1_AR_A_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_AR_A_FSHIFT 8 +#define G2D_BLEND_A1_AR_A_FMASK 0x1 +#define G2D_BLEND_A1_AR_B_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_AR_B_FSHIFT 9 +#define G2D_BLEND_A1_AR_B_FMASK 0x1 +#define G2D_BLEND_A1_AR_C_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_AR_C_FSHIFT 10 +#define G2D_BLEND_A1_AR_C_FMASK 0x1 +#define G2D_BLEND_A1_AR_D_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_AR_D_FSHIFT 11 +#define G2D_BLEND_A1_AR_D_FMASK 0x1 +#define G2D_BLEND_A1_INV_A_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_INV_A_FSHIFT 12 +#define G2D_BLEND_A1_INV_A_FMASK 0x1 +#define G2D_BLEND_A1_INV_B_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_INV_B_FSHIFT 13 +#define G2D_BLEND_A1_INV_B_FMASK 0x1 +#define G2D_BLEND_A1_INV_C_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_INV_C_FSHIFT 14 +#define G2D_BLEND_A1_INV_C_FMASK 0x1 +#define G2D_BLEND_A1_INV_D_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_INV_D_FSHIFT 15 +#define G2D_BLEND_A1_INV_D_FMASK 0x1 +#define G2D_BLEND_A1_SRC_A_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_SRC_A_FSHIFT 16 +#define G2D_BLEND_A1_SRC_A_FMASK 0x7 +#define G2D_BLEND_A1_SRC_B_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_SRC_B_FSHIFT 19 +#define G2D_BLEND_A1_SRC_B_FMASK 0x7 +#define G2D_BLEND_A1_SRC_C_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_SRC_C_FSHIFT 22 +#define G2D_BLEND_A1_SRC_C_FMASK 0x7 +#define G2D_BLEND_A1_SRC_D_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_SRC_D_FSHIFT 25 +#define G2D_BLEND_A1_SRC_D_FMASK 0x7 +#define G2D_BLEND_A1_CONST_A_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_CONST_A_FSHIFT 28 +#define G2D_BLEND_A1_CONST_A_FMASK 0x1 +#define G2D_BLEND_A1_CONST_B_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_CONST_B_FSHIFT 29 +#define G2D_BLEND_A1_CONST_B_FMASK 0x1 +#define G2D_BLEND_A1_CONST_C_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_CONST_C_FSHIFT 30 +#define G2D_BLEND_A1_CONST_C_FMASK 0x1 +#define G2D_BLEND_A1_CONST_D_FADDR ADDR_G2D_BLEND_A1 +#define G2D_BLEND_A1_CONST_D_FSHIFT 31 +#define G2D_BLEND_A1_CONST_D_FMASK 0x1 +#define G2D_BLEND_A2_OPERATION_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_OPERATION_FSHIFT 0 +#define G2D_BLEND_A2_OPERATION_FMASK 0x3 +#define G2D_BLEND_A2_DST_A_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_DST_A_FSHIFT 2 +#define G2D_BLEND_A2_DST_A_FMASK 0x3 +#define G2D_BLEND_A2_DST_B_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_DST_B_FSHIFT 4 +#define G2D_BLEND_A2_DST_B_FMASK 0x3 +#define G2D_BLEND_A2_DST_C_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_DST_C_FSHIFT 6 +#define G2D_BLEND_A2_DST_C_FMASK 0x3 +#define G2D_BLEND_A2_AR_A_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_AR_A_FSHIFT 8 +#define G2D_BLEND_A2_AR_A_FMASK 0x1 +#define G2D_BLEND_A2_AR_B_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_AR_B_FSHIFT 9 +#define G2D_BLEND_A2_AR_B_FMASK 0x1 +#define G2D_BLEND_A2_AR_C_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_AR_C_FSHIFT 10 +#define G2D_BLEND_A2_AR_C_FMASK 0x1 +#define G2D_BLEND_A2_AR_D_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_AR_D_FSHIFT 11 +#define G2D_BLEND_A2_AR_D_FMASK 0x1 +#define G2D_BLEND_A2_INV_A_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_INV_A_FSHIFT 12 +#define G2D_BLEND_A2_INV_A_FMASK 0x1 +#define G2D_BLEND_A2_INV_B_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_INV_B_FSHIFT 13 +#define G2D_BLEND_A2_INV_B_FMASK 0x1 +#define G2D_BLEND_A2_INV_C_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_INV_C_FSHIFT 14 +#define G2D_BLEND_A2_INV_C_FMASK 0x1 +#define G2D_BLEND_A2_INV_D_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_INV_D_FSHIFT 15 +#define G2D_BLEND_A2_INV_D_FMASK 0x1 +#define G2D_BLEND_A2_SRC_A_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_SRC_A_FSHIFT 16 +#define G2D_BLEND_A2_SRC_A_FMASK 0x7 +#define G2D_BLEND_A2_SRC_B_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_SRC_B_FSHIFT 19 +#define G2D_BLEND_A2_SRC_B_FMASK 0x7 +#define G2D_BLEND_A2_SRC_C_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_SRC_C_FSHIFT 22 +#define G2D_BLEND_A2_SRC_C_FMASK 0x7 +#define G2D_BLEND_A2_SRC_D_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_SRC_D_FSHIFT 25 +#define G2D_BLEND_A2_SRC_D_FMASK 0x7 +#define G2D_BLEND_A2_CONST_A_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_CONST_A_FSHIFT 28 +#define G2D_BLEND_A2_CONST_A_FMASK 0x1 +#define G2D_BLEND_A2_CONST_B_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_CONST_B_FSHIFT 29 +#define G2D_BLEND_A2_CONST_B_FMASK 0x1 +#define G2D_BLEND_A2_CONST_C_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_CONST_C_FSHIFT 30 +#define G2D_BLEND_A2_CONST_C_FMASK 0x1 +#define G2D_BLEND_A2_CONST_D_FADDR ADDR_G2D_BLEND_A2 +#define G2D_BLEND_A2_CONST_D_FSHIFT 31 +#define G2D_BLEND_A2_CONST_D_FMASK 0x1 +#define G2D_BLEND_A3_OPERATION_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_OPERATION_FSHIFT 0 +#define G2D_BLEND_A3_OPERATION_FMASK 0x3 +#define G2D_BLEND_A3_DST_A_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_DST_A_FSHIFT 2 +#define G2D_BLEND_A3_DST_A_FMASK 0x3 +#define G2D_BLEND_A3_DST_B_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_DST_B_FSHIFT 4 +#define G2D_BLEND_A3_DST_B_FMASK 0x3 +#define G2D_BLEND_A3_DST_C_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_DST_C_FSHIFT 6 +#define G2D_BLEND_A3_DST_C_FMASK 0x3 +#define G2D_BLEND_A3_AR_A_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_AR_A_FSHIFT 8 +#define G2D_BLEND_A3_AR_A_FMASK 0x1 +#define G2D_BLEND_A3_AR_B_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_AR_B_FSHIFT 9 +#define G2D_BLEND_A3_AR_B_FMASK 0x1 +#define G2D_BLEND_A3_AR_C_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_AR_C_FSHIFT 10 +#define G2D_BLEND_A3_AR_C_FMASK 0x1 +#define G2D_BLEND_A3_AR_D_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_AR_D_FSHIFT 11 +#define G2D_BLEND_A3_AR_D_FMASK 0x1 +#define G2D_BLEND_A3_INV_A_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_INV_A_FSHIFT 12 +#define G2D_BLEND_A3_INV_A_FMASK 0x1 +#define G2D_BLEND_A3_INV_B_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_INV_B_FSHIFT 13 +#define G2D_BLEND_A3_INV_B_FMASK 0x1 +#define G2D_BLEND_A3_INV_C_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_INV_C_FSHIFT 14 +#define G2D_BLEND_A3_INV_C_FMASK 0x1 +#define G2D_BLEND_A3_INV_D_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_INV_D_FSHIFT 15 +#define G2D_BLEND_A3_INV_D_FMASK 0x1 +#define G2D_BLEND_A3_SRC_A_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_SRC_A_FSHIFT 16 +#define G2D_BLEND_A3_SRC_A_FMASK 0x7 +#define G2D_BLEND_A3_SRC_B_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_SRC_B_FSHIFT 19 +#define G2D_BLEND_A3_SRC_B_FMASK 0x7 +#define G2D_BLEND_A3_SRC_C_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_SRC_C_FSHIFT 22 +#define G2D_BLEND_A3_SRC_C_FMASK 0x7 +#define G2D_BLEND_A3_SRC_D_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_SRC_D_FSHIFT 25 +#define G2D_BLEND_A3_SRC_D_FMASK 0x7 +#define G2D_BLEND_A3_CONST_A_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_CONST_A_FSHIFT 28 +#define G2D_BLEND_A3_CONST_A_FMASK 0x1 +#define G2D_BLEND_A3_CONST_B_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_CONST_B_FSHIFT 29 +#define G2D_BLEND_A3_CONST_B_FMASK 0x1 +#define G2D_BLEND_A3_CONST_C_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_CONST_C_FSHIFT 30 +#define G2D_BLEND_A3_CONST_C_FMASK 0x1 +#define G2D_BLEND_A3_CONST_D_FADDR ADDR_G2D_BLEND_A3 +#define G2D_BLEND_A3_CONST_D_FSHIFT 31 +#define G2D_BLEND_A3_CONST_D_FMASK 0x1 +#define G2D_BLEND_C0_OPERATION_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_OPERATION_FSHIFT 0 +#define G2D_BLEND_C0_OPERATION_FMASK 0x3 +#define G2D_BLEND_C0_DST_A_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_DST_A_FSHIFT 2 +#define G2D_BLEND_C0_DST_A_FMASK 0x3 +#define G2D_BLEND_C0_DST_B_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_DST_B_FSHIFT 4 +#define G2D_BLEND_C0_DST_B_FMASK 0x3 +#define G2D_BLEND_C0_DST_C_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_DST_C_FSHIFT 6 +#define G2D_BLEND_C0_DST_C_FMASK 0x3 +#define G2D_BLEND_C0_AR_A_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_AR_A_FSHIFT 8 +#define G2D_BLEND_C0_AR_A_FMASK 0x1 +#define G2D_BLEND_C0_AR_B_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_AR_B_FSHIFT 9 +#define G2D_BLEND_C0_AR_B_FMASK 0x1 +#define G2D_BLEND_C0_AR_C_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_AR_C_FSHIFT 10 +#define G2D_BLEND_C0_AR_C_FMASK 0x1 +#define G2D_BLEND_C0_AR_D_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_AR_D_FSHIFT 11 +#define G2D_BLEND_C0_AR_D_FMASK 0x1 +#define G2D_BLEND_C0_INV_A_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_INV_A_FSHIFT 12 +#define G2D_BLEND_C0_INV_A_FMASK 0x1 +#define G2D_BLEND_C0_INV_B_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_INV_B_FSHIFT 13 +#define G2D_BLEND_C0_INV_B_FMASK 0x1 +#define G2D_BLEND_C0_INV_C_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_INV_C_FSHIFT 14 +#define G2D_BLEND_C0_INV_C_FMASK 0x1 +#define G2D_BLEND_C0_INV_D_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_INV_D_FSHIFT 15 +#define G2D_BLEND_C0_INV_D_FMASK 0x1 +#define G2D_BLEND_C0_SRC_A_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_SRC_A_FSHIFT 16 +#define G2D_BLEND_C0_SRC_A_FMASK 0x7 +#define G2D_BLEND_C0_SRC_B_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_SRC_B_FSHIFT 19 +#define G2D_BLEND_C0_SRC_B_FMASK 0x7 +#define G2D_BLEND_C0_SRC_C_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_SRC_C_FSHIFT 22 +#define G2D_BLEND_C0_SRC_C_FMASK 0x7 +#define G2D_BLEND_C0_SRC_D_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_SRC_D_FSHIFT 25 +#define G2D_BLEND_C0_SRC_D_FMASK 0x7 +#define G2D_BLEND_C0_CONST_A_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_CONST_A_FSHIFT 28 +#define G2D_BLEND_C0_CONST_A_FMASK 0x1 +#define G2D_BLEND_C0_CONST_B_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_CONST_B_FSHIFT 29 +#define G2D_BLEND_C0_CONST_B_FMASK 0x1 +#define G2D_BLEND_C0_CONST_C_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_CONST_C_FSHIFT 30 +#define G2D_BLEND_C0_CONST_C_FMASK 0x1 +#define G2D_BLEND_C0_CONST_D_FADDR ADDR_G2D_BLEND_C0 +#define G2D_BLEND_C0_CONST_D_FSHIFT 31 +#define G2D_BLEND_C0_CONST_D_FMASK 0x1 +#define G2D_BLEND_C1_OPERATION_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_OPERATION_FSHIFT 0 +#define G2D_BLEND_C1_OPERATION_FMASK 0x3 +#define G2D_BLEND_C1_DST_A_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_DST_A_FSHIFT 2 +#define G2D_BLEND_C1_DST_A_FMASK 0x3 +#define G2D_BLEND_C1_DST_B_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_DST_B_FSHIFT 4 +#define G2D_BLEND_C1_DST_B_FMASK 0x3 +#define G2D_BLEND_C1_DST_C_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_DST_C_FSHIFT 6 +#define G2D_BLEND_C1_DST_C_FMASK 0x3 +#define G2D_BLEND_C1_AR_A_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_AR_A_FSHIFT 8 +#define G2D_BLEND_C1_AR_A_FMASK 0x1 +#define G2D_BLEND_C1_AR_B_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_AR_B_FSHIFT 9 +#define G2D_BLEND_C1_AR_B_FMASK 0x1 +#define G2D_BLEND_C1_AR_C_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_AR_C_FSHIFT 10 +#define G2D_BLEND_C1_AR_C_FMASK 0x1 +#define G2D_BLEND_C1_AR_D_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_AR_D_FSHIFT 11 +#define G2D_BLEND_C1_AR_D_FMASK 0x1 +#define G2D_BLEND_C1_INV_A_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_INV_A_FSHIFT 12 +#define G2D_BLEND_C1_INV_A_FMASK 0x1 +#define G2D_BLEND_C1_INV_B_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_INV_B_FSHIFT 13 +#define G2D_BLEND_C1_INV_B_FMASK 0x1 +#define G2D_BLEND_C1_INV_C_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_INV_C_FSHIFT 14 +#define G2D_BLEND_C1_INV_C_FMASK 0x1 +#define G2D_BLEND_C1_INV_D_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_INV_D_FSHIFT 15 +#define G2D_BLEND_C1_INV_D_FMASK 0x1 +#define G2D_BLEND_C1_SRC_A_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_SRC_A_FSHIFT 16 +#define G2D_BLEND_C1_SRC_A_FMASK 0x7 +#define G2D_BLEND_C1_SRC_B_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_SRC_B_FSHIFT 19 +#define G2D_BLEND_C1_SRC_B_FMASK 0x7 +#define G2D_BLEND_C1_SRC_C_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_SRC_C_FSHIFT 22 +#define G2D_BLEND_C1_SRC_C_FMASK 0x7 +#define G2D_BLEND_C1_SRC_D_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_SRC_D_FSHIFT 25 +#define G2D_BLEND_C1_SRC_D_FMASK 0x7 +#define G2D_BLEND_C1_CONST_A_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_CONST_A_FSHIFT 28 +#define G2D_BLEND_C1_CONST_A_FMASK 0x1 +#define G2D_BLEND_C1_CONST_B_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_CONST_B_FSHIFT 29 +#define G2D_BLEND_C1_CONST_B_FMASK 0x1 +#define G2D_BLEND_C1_CONST_C_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_CONST_C_FSHIFT 30 +#define G2D_BLEND_C1_CONST_C_FMASK 0x1 +#define G2D_BLEND_C1_CONST_D_FADDR ADDR_G2D_BLEND_C1 +#define G2D_BLEND_C1_CONST_D_FSHIFT 31 +#define G2D_BLEND_C1_CONST_D_FMASK 0x1 +#define G2D_BLEND_C2_OPERATION_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_OPERATION_FSHIFT 0 +#define G2D_BLEND_C2_OPERATION_FMASK 0x3 +#define G2D_BLEND_C2_DST_A_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_DST_A_FSHIFT 2 +#define G2D_BLEND_C2_DST_A_FMASK 0x3 +#define G2D_BLEND_C2_DST_B_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_DST_B_FSHIFT 4 +#define G2D_BLEND_C2_DST_B_FMASK 0x3 +#define G2D_BLEND_C2_DST_C_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_DST_C_FSHIFT 6 +#define G2D_BLEND_C2_DST_C_FMASK 0x3 +#define G2D_BLEND_C2_AR_A_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_AR_A_FSHIFT 8 +#define G2D_BLEND_C2_AR_A_FMASK 0x1 +#define G2D_BLEND_C2_AR_B_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_AR_B_FSHIFT 9 +#define G2D_BLEND_C2_AR_B_FMASK 0x1 +#define G2D_BLEND_C2_AR_C_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_AR_C_FSHIFT 10 +#define G2D_BLEND_C2_AR_C_FMASK 0x1 +#define G2D_BLEND_C2_AR_D_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_AR_D_FSHIFT 11 +#define G2D_BLEND_C2_AR_D_FMASK 0x1 +#define G2D_BLEND_C2_INV_A_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_INV_A_FSHIFT 12 +#define G2D_BLEND_C2_INV_A_FMASK 0x1 +#define G2D_BLEND_C2_INV_B_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_INV_B_FSHIFT 13 +#define G2D_BLEND_C2_INV_B_FMASK 0x1 +#define G2D_BLEND_C2_INV_C_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_INV_C_FSHIFT 14 +#define G2D_BLEND_C2_INV_C_FMASK 0x1 +#define G2D_BLEND_C2_INV_D_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_INV_D_FSHIFT 15 +#define G2D_BLEND_C2_INV_D_FMASK 0x1 +#define G2D_BLEND_C2_SRC_A_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_SRC_A_FSHIFT 16 +#define G2D_BLEND_C2_SRC_A_FMASK 0x7 +#define G2D_BLEND_C2_SRC_B_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_SRC_B_FSHIFT 19 +#define G2D_BLEND_C2_SRC_B_FMASK 0x7 +#define G2D_BLEND_C2_SRC_C_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_SRC_C_FSHIFT 22 +#define G2D_BLEND_C2_SRC_C_FMASK 0x7 +#define G2D_BLEND_C2_SRC_D_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_SRC_D_FSHIFT 25 +#define G2D_BLEND_C2_SRC_D_FMASK 0x7 +#define G2D_BLEND_C2_CONST_A_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_CONST_A_FSHIFT 28 +#define G2D_BLEND_C2_CONST_A_FMASK 0x1 +#define G2D_BLEND_C2_CONST_B_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_CONST_B_FSHIFT 29 +#define G2D_BLEND_C2_CONST_B_FMASK 0x1 +#define G2D_BLEND_C2_CONST_C_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_CONST_C_FSHIFT 30 +#define G2D_BLEND_C2_CONST_C_FMASK 0x1 +#define G2D_BLEND_C2_CONST_D_FADDR ADDR_G2D_BLEND_C2 +#define G2D_BLEND_C2_CONST_D_FSHIFT 31 +#define G2D_BLEND_C2_CONST_D_FMASK 0x1 +#define G2D_BLEND_C3_OPERATION_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_OPERATION_FSHIFT 0 +#define G2D_BLEND_C3_OPERATION_FMASK 0x3 +#define G2D_BLEND_C3_DST_A_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_DST_A_FSHIFT 2 +#define G2D_BLEND_C3_DST_A_FMASK 0x3 +#define G2D_BLEND_C3_DST_B_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_DST_B_FSHIFT 4 +#define G2D_BLEND_C3_DST_B_FMASK 0x3 +#define G2D_BLEND_C3_DST_C_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_DST_C_FSHIFT 6 +#define G2D_BLEND_C3_DST_C_FMASK 0x3 +#define G2D_BLEND_C3_AR_A_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_AR_A_FSHIFT 8 +#define G2D_BLEND_C3_AR_A_FMASK 0x1 +#define G2D_BLEND_C3_AR_B_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_AR_B_FSHIFT 9 +#define G2D_BLEND_C3_AR_B_FMASK 0x1 +#define G2D_BLEND_C3_AR_C_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_AR_C_FSHIFT 10 +#define G2D_BLEND_C3_AR_C_FMASK 0x1 +#define G2D_BLEND_C3_AR_D_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_AR_D_FSHIFT 11 +#define G2D_BLEND_C3_AR_D_FMASK 0x1 +#define G2D_BLEND_C3_INV_A_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_INV_A_FSHIFT 12 +#define G2D_BLEND_C3_INV_A_FMASK 0x1 +#define G2D_BLEND_C3_INV_B_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_INV_B_FSHIFT 13 +#define G2D_BLEND_C3_INV_B_FMASK 0x1 +#define G2D_BLEND_C3_INV_C_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_INV_C_FSHIFT 14 +#define G2D_BLEND_C3_INV_C_FMASK 0x1 +#define G2D_BLEND_C3_INV_D_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_INV_D_FSHIFT 15 +#define G2D_BLEND_C3_INV_D_FMASK 0x1 +#define G2D_BLEND_C3_SRC_A_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_SRC_A_FSHIFT 16 +#define G2D_BLEND_C3_SRC_A_FMASK 0x7 +#define G2D_BLEND_C3_SRC_B_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_SRC_B_FSHIFT 19 +#define G2D_BLEND_C3_SRC_B_FMASK 0x7 +#define G2D_BLEND_C3_SRC_C_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_SRC_C_FSHIFT 22 +#define G2D_BLEND_C3_SRC_C_FMASK 0x7 +#define G2D_BLEND_C3_SRC_D_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_SRC_D_FSHIFT 25 +#define G2D_BLEND_C3_SRC_D_FMASK 0x7 +#define G2D_BLEND_C3_CONST_A_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_CONST_A_FSHIFT 28 +#define G2D_BLEND_C3_CONST_A_FMASK 0x1 +#define G2D_BLEND_C3_CONST_B_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_CONST_B_FSHIFT 29 +#define G2D_BLEND_C3_CONST_B_FMASK 0x1 +#define G2D_BLEND_C3_CONST_C_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_CONST_C_FSHIFT 30 +#define G2D_BLEND_C3_CONST_C_FMASK 0x1 +#define G2D_BLEND_C3_CONST_D_FADDR ADDR_G2D_BLEND_C3 +#define G2D_BLEND_C3_CONST_D_FSHIFT 31 +#define G2D_BLEND_C3_CONST_D_FMASK 0x1 +#define G2D_BLEND_C4_OPERATION_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_OPERATION_FSHIFT 0 +#define G2D_BLEND_C4_OPERATION_FMASK 0x3 +#define G2D_BLEND_C4_DST_A_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_DST_A_FSHIFT 2 +#define G2D_BLEND_C4_DST_A_FMASK 0x3 +#define G2D_BLEND_C4_DST_B_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_DST_B_FSHIFT 4 +#define G2D_BLEND_C4_DST_B_FMASK 0x3 +#define G2D_BLEND_C4_DST_C_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_DST_C_FSHIFT 6 +#define G2D_BLEND_C4_DST_C_FMASK 0x3 +#define G2D_BLEND_C4_AR_A_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_AR_A_FSHIFT 8 +#define G2D_BLEND_C4_AR_A_FMASK 0x1 +#define G2D_BLEND_C4_AR_B_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_AR_B_FSHIFT 9 +#define G2D_BLEND_C4_AR_B_FMASK 0x1 +#define G2D_BLEND_C4_AR_C_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_AR_C_FSHIFT 10 +#define G2D_BLEND_C4_AR_C_FMASK 0x1 +#define G2D_BLEND_C4_AR_D_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_AR_D_FSHIFT 11 +#define G2D_BLEND_C4_AR_D_FMASK 0x1 +#define G2D_BLEND_C4_INV_A_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_INV_A_FSHIFT 12 +#define G2D_BLEND_C4_INV_A_FMASK 0x1 +#define G2D_BLEND_C4_INV_B_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_INV_B_FSHIFT 13 +#define G2D_BLEND_C4_INV_B_FMASK 0x1 +#define G2D_BLEND_C4_INV_C_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_INV_C_FSHIFT 14 +#define G2D_BLEND_C4_INV_C_FMASK 0x1 +#define G2D_BLEND_C4_INV_D_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_INV_D_FSHIFT 15 +#define G2D_BLEND_C4_INV_D_FMASK 0x1 +#define G2D_BLEND_C4_SRC_A_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_SRC_A_FSHIFT 16 +#define G2D_BLEND_C4_SRC_A_FMASK 0x7 +#define G2D_BLEND_C4_SRC_B_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_SRC_B_FSHIFT 19 +#define G2D_BLEND_C4_SRC_B_FMASK 0x7 +#define G2D_BLEND_C4_SRC_C_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_SRC_C_FSHIFT 22 +#define G2D_BLEND_C4_SRC_C_FMASK 0x7 +#define G2D_BLEND_C4_SRC_D_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_SRC_D_FSHIFT 25 +#define G2D_BLEND_C4_SRC_D_FMASK 0x7 +#define G2D_BLEND_C4_CONST_A_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_CONST_A_FSHIFT 28 +#define G2D_BLEND_C4_CONST_A_FMASK 0x1 +#define G2D_BLEND_C4_CONST_B_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_CONST_B_FSHIFT 29 +#define G2D_BLEND_C4_CONST_B_FMASK 0x1 +#define G2D_BLEND_C4_CONST_C_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_CONST_C_FSHIFT 30 +#define G2D_BLEND_C4_CONST_C_FMASK 0x1 +#define G2D_BLEND_C4_CONST_D_FADDR ADDR_G2D_BLEND_C4 +#define G2D_BLEND_C4_CONST_D_FSHIFT 31 +#define G2D_BLEND_C4_CONST_D_FMASK 0x1 +#define G2D_BLEND_C5_OPERATION_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_OPERATION_FSHIFT 0 +#define G2D_BLEND_C5_OPERATION_FMASK 0x3 +#define G2D_BLEND_C5_DST_A_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_DST_A_FSHIFT 2 +#define G2D_BLEND_C5_DST_A_FMASK 0x3 +#define G2D_BLEND_C5_DST_B_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_DST_B_FSHIFT 4 +#define G2D_BLEND_C5_DST_B_FMASK 0x3 +#define G2D_BLEND_C5_DST_C_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_DST_C_FSHIFT 6 +#define G2D_BLEND_C5_DST_C_FMASK 0x3 +#define G2D_BLEND_C5_AR_A_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_AR_A_FSHIFT 8 +#define G2D_BLEND_C5_AR_A_FMASK 0x1 +#define G2D_BLEND_C5_AR_B_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_AR_B_FSHIFT 9 +#define G2D_BLEND_C5_AR_B_FMASK 0x1 +#define G2D_BLEND_C5_AR_C_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_AR_C_FSHIFT 10 +#define G2D_BLEND_C5_AR_C_FMASK 0x1 +#define G2D_BLEND_C5_AR_D_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_AR_D_FSHIFT 11 +#define G2D_BLEND_C5_AR_D_FMASK 0x1 +#define G2D_BLEND_C5_INV_A_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_INV_A_FSHIFT 12 +#define G2D_BLEND_C5_INV_A_FMASK 0x1 +#define G2D_BLEND_C5_INV_B_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_INV_B_FSHIFT 13 +#define G2D_BLEND_C5_INV_B_FMASK 0x1 +#define G2D_BLEND_C5_INV_C_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_INV_C_FSHIFT 14 +#define G2D_BLEND_C5_INV_C_FMASK 0x1 +#define G2D_BLEND_C5_INV_D_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_INV_D_FSHIFT 15 +#define G2D_BLEND_C5_INV_D_FMASK 0x1 +#define G2D_BLEND_C5_SRC_A_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_SRC_A_FSHIFT 16 +#define G2D_BLEND_C5_SRC_A_FMASK 0x7 +#define G2D_BLEND_C5_SRC_B_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_SRC_B_FSHIFT 19 +#define G2D_BLEND_C5_SRC_B_FMASK 0x7 +#define G2D_BLEND_C5_SRC_C_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_SRC_C_FSHIFT 22 +#define G2D_BLEND_C5_SRC_C_FMASK 0x7 +#define G2D_BLEND_C5_SRC_D_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_SRC_D_FSHIFT 25 +#define G2D_BLEND_C5_SRC_D_FMASK 0x7 +#define G2D_BLEND_C5_CONST_A_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_CONST_A_FSHIFT 28 +#define G2D_BLEND_C5_CONST_A_FMASK 0x1 +#define G2D_BLEND_C5_CONST_B_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_CONST_B_FSHIFT 29 +#define G2D_BLEND_C5_CONST_B_FMASK 0x1 +#define G2D_BLEND_C5_CONST_C_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_CONST_C_FSHIFT 30 +#define G2D_BLEND_C5_CONST_C_FMASK 0x1 +#define G2D_BLEND_C5_CONST_D_FADDR ADDR_G2D_BLEND_C5 +#define G2D_BLEND_C5_CONST_D_FSHIFT 31 +#define G2D_BLEND_C5_CONST_D_FMASK 0x1 +#define G2D_BLEND_C6_OPERATION_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_OPERATION_FSHIFT 0 +#define G2D_BLEND_C6_OPERATION_FMASK 0x3 +#define G2D_BLEND_C6_DST_A_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_DST_A_FSHIFT 2 +#define G2D_BLEND_C6_DST_A_FMASK 0x3 +#define G2D_BLEND_C6_DST_B_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_DST_B_FSHIFT 4 +#define G2D_BLEND_C6_DST_B_FMASK 0x3 +#define G2D_BLEND_C6_DST_C_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_DST_C_FSHIFT 6 +#define G2D_BLEND_C6_DST_C_FMASK 0x3 +#define G2D_BLEND_C6_AR_A_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_AR_A_FSHIFT 8 +#define G2D_BLEND_C6_AR_A_FMASK 0x1 +#define G2D_BLEND_C6_AR_B_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_AR_B_FSHIFT 9 +#define G2D_BLEND_C6_AR_B_FMASK 0x1 +#define G2D_BLEND_C6_AR_C_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_AR_C_FSHIFT 10 +#define G2D_BLEND_C6_AR_C_FMASK 0x1 +#define G2D_BLEND_C6_AR_D_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_AR_D_FSHIFT 11 +#define G2D_BLEND_C6_AR_D_FMASK 0x1 +#define G2D_BLEND_C6_INV_A_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_INV_A_FSHIFT 12 +#define G2D_BLEND_C6_INV_A_FMASK 0x1 +#define G2D_BLEND_C6_INV_B_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_INV_B_FSHIFT 13 +#define G2D_BLEND_C6_INV_B_FMASK 0x1 +#define G2D_BLEND_C6_INV_C_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_INV_C_FSHIFT 14 +#define G2D_BLEND_C6_INV_C_FMASK 0x1 +#define G2D_BLEND_C6_INV_D_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_INV_D_FSHIFT 15 +#define G2D_BLEND_C6_INV_D_FMASK 0x1 +#define G2D_BLEND_C6_SRC_A_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_SRC_A_FSHIFT 16 +#define G2D_BLEND_C6_SRC_A_FMASK 0x7 +#define G2D_BLEND_C6_SRC_B_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_SRC_B_FSHIFT 19 +#define G2D_BLEND_C6_SRC_B_FMASK 0x7 +#define G2D_BLEND_C6_SRC_C_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_SRC_C_FSHIFT 22 +#define G2D_BLEND_C6_SRC_C_FMASK 0x7 +#define G2D_BLEND_C6_SRC_D_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_SRC_D_FSHIFT 25 +#define G2D_BLEND_C6_SRC_D_FMASK 0x7 +#define G2D_BLEND_C6_CONST_A_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_CONST_A_FSHIFT 28 +#define G2D_BLEND_C6_CONST_A_FMASK 0x1 +#define G2D_BLEND_C6_CONST_B_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_CONST_B_FSHIFT 29 +#define G2D_BLEND_C6_CONST_B_FMASK 0x1 +#define G2D_BLEND_C6_CONST_C_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_CONST_C_FSHIFT 30 +#define G2D_BLEND_C6_CONST_C_FMASK 0x1 +#define G2D_BLEND_C6_CONST_D_FADDR ADDR_G2D_BLEND_C6 +#define G2D_BLEND_C6_CONST_D_FSHIFT 31 +#define G2D_BLEND_C6_CONST_D_FMASK 0x1 +#define G2D_BLEND_C7_OPERATION_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_OPERATION_FSHIFT 0 +#define G2D_BLEND_C7_OPERATION_FMASK 0x3 +#define G2D_BLEND_C7_DST_A_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_DST_A_FSHIFT 2 +#define G2D_BLEND_C7_DST_A_FMASK 0x3 +#define G2D_BLEND_C7_DST_B_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_DST_B_FSHIFT 4 +#define G2D_BLEND_C7_DST_B_FMASK 0x3 +#define G2D_BLEND_C7_DST_C_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_DST_C_FSHIFT 6 +#define G2D_BLEND_C7_DST_C_FMASK 0x3 +#define G2D_BLEND_C7_AR_A_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_AR_A_FSHIFT 8 +#define G2D_BLEND_C7_AR_A_FMASK 0x1 +#define G2D_BLEND_C7_AR_B_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_AR_B_FSHIFT 9 +#define G2D_BLEND_C7_AR_B_FMASK 0x1 +#define G2D_BLEND_C7_AR_C_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_AR_C_FSHIFT 10 +#define G2D_BLEND_C7_AR_C_FMASK 0x1 +#define G2D_BLEND_C7_AR_D_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_AR_D_FSHIFT 11 +#define G2D_BLEND_C7_AR_D_FMASK 0x1 +#define G2D_BLEND_C7_INV_A_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_INV_A_FSHIFT 12 +#define G2D_BLEND_C7_INV_A_FMASK 0x1 +#define G2D_BLEND_C7_INV_B_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_INV_B_FSHIFT 13 +#define G2D_BLEND_C7_INV_B_FMASK 0x1 +#define G2D_BLEND_C7_INV_C_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_INV_C_FSHIFT 14 +#define G2D_BLEND_C7_INV_C_FMASK 0x1 +#define G2D_BLEND_C7_INV_D_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_INV_D_FSHIFT 15 +#define G2D_BLEND_C7_INV_D_FMASK 0x1 +#define G2D_BLEND_C7_SRC_A_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_SRC_A_FSHIFT 16 +#define G2D_BLEND_C7_SRC_A_FMASK 0x7 +#define G2D_BLEND_C7_SRC_B_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_SRC_B_FSHIFT 19 +#define G2D_BLEND_C7_SRC_B_FMASK 0x7 +#define G2D_BLEND_C7_SRC_C_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_SRC_C_FSHIFT 22 +#define G2D_BLEND_C7_SRC_C_FMASK 0x7 +#define G2D_BLEND_C7_SRC_D_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_SRC_D_FSHIFT 25 +#define G2D_BLEND_C7_SRC_D_FMASK 0x7 +#define G2D_BLEND_C7_CONST_A_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_CONST_A_FSHIFT 28 +#define G2D_BLEND_C7_CONST_A_FMASK 0x1 +#define G2D_BLEND_C7_CONST_B_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_CONST_B_FSHIFT 29 +#define G2D_BLEND_C7_CONST_B_FMASK 0x1 +#define G2D_BLEND_C7_CONST_C_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_CONST_C_FSHIFT 30 +#define G2D_BLEND_C7_CONST_C_FMASK 0x1 +#define G2D_BLEND_C7_CONST_D_FADDR ADDR_G2D_BLEND_C7 +#define G2D_BLEND_C7_CONST_D_FSHIFT 31 +#define G2D_BLEND_C7_CONST_D_FMASK 0x1 +#define G2D_CFG0_STRIDE_FADDR ADDR_G2D_CFG0 +#define G2D_CFG0_STRIDE_FSHIFT 0 +#define G2D_CFG0_STRIDE_FMASK 0xfff +#define G2D_CFG0_FORMAT_FADDR ADDR_G2D_CFG0 +#define G2D_CFG0_FORMAT_FSHIFT 12 +#define G2D_CFG0_FORMAT_FMASK 0xf +#define G2D_CFG0_TILED_FADDR ADDR_G2D_CFG0 +#define G2D_CFG0_TILED_FSHIFT 16 +#define G2D_CFG0_TILED_FMASK 0x1 +#define G2D_CFG0_SRGB_FADDR ADDR_G2D_CFG0 +#define G2D_CFG0_SRGB_FSHIFT 17 +#define G2D_CFG0_SRGB_FMASK 0x1 +#define G2D_CFG0_SWAPWORDS_FADDR ADDR_G2D_CFG0 +#define G2D_CFG0_SWAPWORDS_FSHIFT 18 +#define G2D_CFG0_SWAPWORDS_FMASK 0x1 +#define G2D_CFG0_SWAPBYTES_FADDR ADDR_G2D_CFG0 +#define G2D_CFG0_SWAPBYTES_FSHIFT 19 +#define G2D_CFG0_SWAPBYTES_FMASK 0x1 +#define G2D_CFG0_SWAPALL_FADDR ADDR_G2D_CFG0 +#define G2D_CFG0_SWAPALL_FSHIFT 20 +#define G2D_CFG0_SWAPALL_FMASK 0x1 +#define G2D_CFG0_SWAPRB_FADDR ADDR_G2D_CFG0 +#define G2D_CFG0_SWAPRB_FSHIFT 21 +#define G2D_CFG0_SWAPRB_FMASK 0x1 +#define G2D_CFG0_SWAPBITS_FADDR ADDR_G2D_CFG0 +#define G2D_CFG0_SWAPBITS_FSHIFT 22 +#define G2D_CFG0_SWAPBITS_FMASK 0x1 +#define G2D_CFG0_STRIDESIGN_FADDR ADDR_G2D_CFG0 +#define G2D_CFG0_STRIDESIGN_FSHIFT 23 +#define G2D_CFG0_STRIDESIGN_FMASK 0x1 +#define G2D_CFG1_STRIDE_FADDR ADDR_G2D_CFG1 +#define G2D_CFG1_STRIDE_FSHIFT 0 +#define G2D_CFG1_STRIDE_FMASK 0xfff +#define G2D_CFG1_FORMAT_FADDR ADDR_G2D_CFG1 +#define G2D_CFG1_FORMAT_FSHIFT 12 +#define G2D_CFG1_FORMAT_FMASK 0xf +#define G2D_CFG1_TILED_FADDR ADDR_G2D_CFG1 +#define G2D_CFG1_TILED_FSHIFT 16 +#define G2D_CFG1_TILED_FMASK 0x1 +#define G2D_CFG1_SRGB_FADDR ADDR_G2D_CFG1 +#define G2D_CFG1_SRGB_FSHIFT 17 +#define G2D_CFG1_SRGB_FMASK 0x1 +#define G2D_CFG1_SWAPWORDS_FADDR ADDR_G2D_CFG1 +#define G2D_CFG1_SWAPWORDS_FSHIFT 18 +#define G2D_CFG1_SWAPWORDS_FMASK 0x1 +#define G2D_CFG1_SWAPBYTES_FADDR ADDR_G2D_CFG1 +#define G2D_CFG1_SWAPBYTES_FSHIFT 19 +#define G2D_CFG1_SWAPBYTES_FMASK 0x1 +#define G2D_CFG1_SWAPALL_FADDR ADDR_G2D_CFG1 +#define G2D_CFG1_SWAPALL_FSHIFT 20 +#define G2D_CFG1_SWAPALL_FMASK 0x1 +#define G2D_CFG1_SWAPRB_FADDR ADDR_G2D_CFG1 +#define G2D_CFG1_SWAPRB_FSHIFT 21 +#define G2D_CFG1_SWAPRB_FMASK 0x1 +#define G2D_CFG1_SWAPBITS_FADDR ADDR_G2D_CFG1 +#define G2D_CFG1_SWAPBITS_FSHIFT 22 +#define G2D_CFG1_SWAPBITS_FMASK 0x1 +#define G2D_CFG1_STRIDESIGN_FADDR ADDR_G2D_CFG1 +#define G2D_CFG1_STRIDESIGN_FSHIFT 23 +#define G2D_CFG1_STRIDESIGN_FMASK 0x1 +#define G2D_CFG2_STRIDE_FADDR ADDR_G2D_CFG2 +#define G2D_CFG2_STRIDE_FSHIFT 0 +#define G2D_CFG2_STRIDE_FMASK 0xfff +#define G2D_CFG2_FORMAT_FADDR ADDR_G2D_CFG2 +#define G2D_CFG2_FORMAT_FSHIFT 12 +#define G2D_CFG2_FORMAT_FMASK 0xf +#define G2D_CFG2_TILED_FADDR ADDR_G2D_CFG2 +#define G2D_CFG2_TILED_FSHIFT 16 +#define G2D_CFG2_TILED_FMASK 0x1 +#define G2D_CFG2_SRGB_FADDR ADDR_G2D_CFG2 +#define G2D_CFG2_SRGB_FSHIFT 17 +#define G2D_CFG2_SRGB_FMASK 0x1 +#define G2D_CFG2_SWAPWORDS_FADDR ADDR_G2D_CFG2 +#define G2D_CFG2_SWAPWORDS_FSHIFT 18 +#define G2D_CFG2_SWAPWORDS_FMASK 0x1 +#define G2D_CFG2_SWAPBYTES_FADDR ADDR_G2D_CFG2 +#define G2D_CFG2_SWAPBYTES_FSHIFT 19 +#define G2D_CFG2_SWAPBYTES_FMASK 0x1 +#define G2D_CFG2_SWAPALL_FADDR ADDR_G2D_CFG2 +#define G2D_CFG2_SWAPALL_FSHIFT 20 +#define G2D_CFG2_SWAPALL_FMASK 0x1 +#define G2D_CFG2_SWAPRB_FADDR ADDR_G2D_CFG2 +#define G2D_CFG2_SWAPRB_FSHIFT 21 +#define G2D_CFG2_SWAPRB_FMASK 0x1 +#define G2D_CFG2_SWAPBITS_FADDR ADDR_G2D_CFG2 +#define G2D_CFG2_SWAPBITS_FSHIFT 22 +#define G2D_CFG2_SWAPBITS_FMASK 0x1 +#define G2D_CFG2_STRIDESIGN_FADDR ADDR_G2D_CFG2 +#define G2D_CFG2_STRIDESIGN_FSHIFT 23 +#define G2D_CFG2_STRIDESIGN_FMASK 0x1 +#define G2D_CFG3_STRIDE_FADDR ADDR_G2D_CFG3 +#define G2D_CFG3_STRIDE_FSHIFT 0 +#define G2D_CFG3_STRIDE_FMASK 0xfff +#define G2D_CFG3_FORMAT_FADDR ADDR_G2D_CFG3 +#define G2D_CFG3_FORMAT_FSHIFT 12 +#define G2D_CFG3_FORMAT_FMASK 0xf +#define G2D_CFG3_TILED_FADDR ADDR_G2D_CFG3 +#define G2D_CFG3_TILED_FSHIFT 16 +#define G2D_CFG3_TILED_FMASK 0x1 +#define G2D_CFG3_SRGB_FADDR ADDR_G2D_CFG3 +#define G2D_CFG3_SRGB_FSHIFT 17 +#define G2D_CFG3_SRGB_FMASK 0x1 +#define G2D_CFG3_SWAPWORDS_FADDR ADDR_G2D_CFG3 +#define G2D_CFG3_SWAPWORDS_FSHIFT 18 +#define G2D_CFG3_SWAPWORDS_FMASK 0x1 +#define G2D_CFG3_SWAPBYTES_FADDR ADDR_G2D_CFG3 +#define G2D_CFG3_SWAPBYTES_FSHIFT 19 +#define G2D_CFG3_SWAPBYTES_FMASK 0x1 +#define G2D_CFG3_SWAPALL_FADDR ADDR_G2D_CFG3 +#define G2D_CFG3_SWAPALL_FSHIFT 20 +#define G2D_CFG3_SWAPALL_FMASK 0x1 +#define G2D_CFG3_SWAPRB_FADDR ADDR_G2D_CFG3 +#define G2D_CFG3_SWAPRB_FSHIFT 21 +#define G2D_CFG3_SWAPRB_FMASK 0x1 +#define G2D_CFG3_SWAPBITS_FADDR ADDR_G2D_CFG3 +#define G2D_CFG3_SWAPBITS_FSHIFT 22 +#define G2D_CFG3_SWAPBITS_FMASK 0x1 +#define G2D_CFG3_STRIDESIGN_FADDR ADDR_G2D_CFG3 +#define G2D_CFG3_STRIDESIGN_FSHIFT 23 +#define G2D_CFG3_STRIDESIGN_FMASK 0x1 +#define G2D_COLOR_ARGB_FADDR ADDR_G2D_COLOR +#define G2D_COLOR_ARGB_FSHIFT 0 +#define G2D_COLOR_ARGB_FMASK 0xffffffff +#define G2D_CONFIG_DST_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_DST_FSHIFT 0 +#define G2D_CONFIG_DST_FMASK 0x1 +#define G2D_CONFIG_SRC1_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_SRC1_FSHIFT 1 +#define G2D_CONFIG_SRC1_FMASK 0x1 +#define G2D_CONFIG_SRC2_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_SRC2_FSHIFT 2 +#define G2D_CONFIG_SRC2_FMASK 0x1 +#define G2D_CONFIG_SRC3_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_SRC3_FSHIFT 3 +#define G2D_CONFIG_SRC3_FMASK 0x1 +#define G2D_CONFIG_SRCCK_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_SRCCK_FSHIFT 4 +#define G2D_CONFIG_SRCCK_FMASK 0x1 +#define G2D_CONFIG_DSTCK_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_DSTCK_FSHIFT 5 +#define G2D_CONFIG_DSTCK_FMASK 0x1 +#define G2D_CONFIG_ROTATE_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_ROTATE_FSHIFT 6 +#define G2D_CONFIG_ROTATE_FMASK 0x3 +#define G2D_CONFIG_OBS_GAMMA_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_OBS_GAMMA_FSHIFT 8 +#define G2D_CONFIG_OBS_GAMMA_FMASK 0x1 +#define G2D_CONFIG_IGNORECKALPHA_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_IGNORECKALPHA_FSHIFT 9 +#define G2D_CONFIG_IGNORECKALPHA_FMASK 0x1 +#define G2D_CONFIG_DITHER_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_DITHER_FSHIFT 10 +#define G2D_CONFIG_DITHER_FMASK 0x1 +#define G2D_CONFIG_WRITESRGB_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_WRITESRGB_FSHIFT 11 +#define G2D_CONFIG_WRITESRGB_FMASK 0x1 +#define G2D_CONFIG_ARGBMASK_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_ARGBMASK_FSHIFT 12 +#define G2D_CONFIG_ARGBMASK_FMASK 0xf +#define G2D_CONFIG_ALPHATEX_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_ALPHATEX_FSHIFT 16 +#define G2D_CONFIG_ALPHATEX_FMASK 0x1 +#define G2D_CONFIG_PALMLINES_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_PALMLINES_FSHIFT 17 +#define G2D_CONFIG_PALMLINES_FMASK 0x1 +#define G2D_CONFIG_NOLASTPIXEL_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_NOLASTPIXEL_FSHIFT 18 +#define G2D_CONFIG_NOLASTPIXEL_FMASK 0x1 +#define G2D_CONFIG_NOPROTECT_FADDR ADDR_G2D_CONFIG +#define G2D_CONFIG_NOPROTECT_FSHIFT 19 +#define G2D_CONFIG_NOPROTECT_FMASK 0x1 +#define G2D_CONST0_ARGB_FADDR ADDR_G2D_CONST0 +#define G2D_CONST0_ARGB_FSHIFT 0 +#define G2D_CONST0_ARGB_FMASK 0xffffffff +#define G2D_CONST1_ARGB_FADDR ADDR_G2D_CONST1 +#define G2D_CONST1_ARGB_FSHIFT 0 +#define G2D_CONST1_ARGB_FMASK 0xffffffff +#define G2D_CONST2_ARGB_FADDR ADDR_G2D_CONST2 +#define G2D_CONST2_ARGB_FSHIFT 0 +#define G2D_CONST2_ARGB_FMASK 0xffffffff +#define G2D_CONST3_ARGB_FADDR ADDR_G2D_CONST3 +#define G2D_CONST3_ARGB_FSHIFT 0 +#define G2D_CONST3_ARGB_FMASK 0xffffffff +#define G2D_CONST4_ARGB_FADDR ADDR_G2D_CONST4 +#define G2D_CONST4_ARGB_FSHIFT 0 +#define G2D_CONST4_ARGB_FMASK 0xffffffff +#define G2D_CONST5_ARGB_FADDR ADDR_G2D_CONST5 +#define G2D_CONST5_ARGB_FSHIFT 0 +#define G2D_CONST5_ARGB_FMASK 0xffffffff +#define G2D_CONST6_ARGB_FADDR ADDR_G2D_CONST6 +#define G2D_CONST6_ARGB_FSHIFT 0 +#define G2D_CONST6_ARGB_FMASK 0xffffffff +#define G2D_CONST7_ARGB_FADDR ADDR_G2D_CONST7 +#define G2D_CONST7_ARGB_FSHIFT 0 +#define G2D_CONST7_ARGB_FMASK 0xffffffff +#define G2D_FOREGROUND_COLOR_FADDR ADDR_G2D_FOREGROUND +#define G2D_FOREGROUND_COLOR_FSHIFT 0 +#define G2D_FOREGROUND_COLOR_FMASK 0xffffffff +#define G2D_GRADIENT_INSTRUCTIONS_FADDR ADDR_G2D_GRADIENT +#define G2D_GRADIENT_INSTRUCTIONS_FSHIFT 0 +#define G2D_GRADIENT_INSTRUCTIONS_FMASK 0x7 +#define G2D_GRADIENT_INSTRUCTIONS2_FADDR ADDR_G2D_GRADIENT +#define G2D_GRADIENT_INSTRUCTIONS2_FSHIFT 3 +#define G2D_GRADIENT_INSTRUCTIONS2_FMASK 0x7 +#define G2D_GRADIENT_ENABLE_FADDR ADDR_G2D_GRADIENT +#define G2D_GRADIENT_ENABLE_FSHIFT 6 +#define G2D_GRADIENT_ENABLE_FMASK 0x1 +#define G2D_GRADIENT_ENABLE2_FADDR ADDR_G2D_GRADIENT +#define G2D_GRADIENT_ENABLE2_FSHIFT 7 +#define G2D_GRADIENT_ENABLE2_FMASK 0x1 +#define G2D_GRADIENT_SEL_FADDR ADDR_G2D_GRADIENT +#define G2D_GRADIENT_SEL_FSHIFT 8 +#define G2D_GRADIENT_SEL_FMASK 0x1 +#define G2D_IDLE_IRQ_FADDR ADDR_G2D_IDLE +#define G2D_IDLE_IRQ_FSHIFT 0 +#define G2D_IDLE_IRQ_FMASK 0x1 +#define G2D_IDLE_BCFLUSH_FADDR ADDR_G2D_IDLE +#define G2D_IDLE_BCFLUSH_FSHIFT 1 +#define G2D_IDLE_BCFLUSH_FMASK 0x1 +#define G2D_IDLE_V3_FADDR ADDR_G2D_IDLE +#define G2D_IDLE_V3_FSHIFT 2 +#define G2D_IDLE_V3_FMASK 0x1 +#define G2D_INPUT_COLOR_FADDR ADDR_G2D_INPUT +#define G2D_INPUT_COLOR_FSHIFT 0 +#define G2D_INPUT_COLOR_FMASK 0x1 +#define G2D_INPUT_SCOORD1_FADDR ADDR_G2D_INPUT +#define G2D_INPUT_SCOORD1_FSHIFT 1 +#define G2D_INPUT_SCOORD1_FMASK 0x1 +#define G2D_INPUT_SCOORD2_FADDR ADDR_G2D_INPUT +#define G2D_INPUT_SCOORD2_FSHIFT 2 +#define G2D_INPUT_SCOORD2_FMASK 0x1 +#define G2D_INPUT_COPYCOORD_FADDR ADDR_G2D_INPUT +#define G2D_INPUT_COPYCOORD_FSHIFT 3 +#define G2D_INPUT_COPYCOORD_FMASK 0x1 +#define G2D_INPUT_VGMODE_FADDR ADDR_G2D_INPUT +#define G2D_INPUT_VGMODE_FSHIFT 4 +#define G2D_INPUT_VGMODE_FMASK 0x1 +#define G2D_INPUT_LINEMODE_FADDR ADDR_G2D_INPUT +#define G2D_INPUT_LINEMODE_FSHIFT 5 +#define G2D_INPUT_LINEMODE_FMASK 0x1 +#define G2D_MASK_YMASK_FADDR ADDR_G2D_MASK +#define G2D_MASK_YMASK_FSHIFT 0 +#define G2D_MASK_YMASK_FMASK 0xfff +#define G2D_MASK_XMASK_FADDR ADDR_G2D_MASK +#define G2D_MASK_XMASK_FSHIFT 12 +#define G2D_MASK_XMASK_FMASK 0xfff +#define G2D_ROP_ROP_FADDR ADDR_G2D_ROP +#define G2D_ROP_ROP_FSHIFT 0 +#define G2D_ROP_ROP_FMASK 0xffff +#define G2D_SCISSORX_LEFT_FADDR ADDR_G2D_SCISSORX +#define G2D_SCISSORX_LEFT_FSHIFT 0 +#define G2D_SCISSORX_LEFT_FMASK 0x7ff +#define G2D_SCISSORX_RIGHT_FADDR ADDR_G2D_SCISSORX +#define G2D_SCISSORX_RIGHT_FSHIFT 11 +#define G2D_SCISSORX_RIGHT_FMASK 0x7ff +#define G2D_SCISSORY_TOP_FADDR ADDR_G2D_SCISSORY +#define G2D_SCISSORY_TOP_FSHIFT 0 +#define G2D_SCISSORY_TOP_FMASK 0x7ff +#define G2D_SCISSORY_BOTTOM_FADDR ADDR_G2D_SCISSORY +#define G2D_SCISSORY_BOTTOM_FSHIFT 11 +#define G2D_SCISSORY_BOTTOM_FMASK 0x7ff +#define G2D_SXY_Y_FADDR ADDR_G2D_SXY +#define G2D_SXY_Y_FSHIFT 0 +#define G2D_SXY_Y_FMASK 0x7ff +#define G2D_SXY_PAD_FADDR ADDR_G2D_SXY +#define G2D_SXY_PAD_FSHIFT 11 +#define G2D_SXY_PAD_FMASK 0x1f +#define G2D_SXY_X_FADDR ADDR_G2D_SXY +#define G2D_SXY_X_FSHIFT 16 +#define G2D_SXY_X_FMASK 0x7ff +#define G2D_SXY2_Y_FADDR ADDR_G2D_SXY2 +#define G2D_SXY2_Y_FSHIFT 0 +#define G2D_SXY2_Y_FMASK 0x7ff +#define G2D_SXY2_PAD_FADDR ADDR_G2D_SXY2 +#define G2D_SXY2_PAD_FSHIFT 11 +#define G2D_SXY2_PAD_FMASK 0x1f +#define G2D_SXY2_X_FADDR ADDR_G2D_SXY2 +#define G2D_SXY2_X_FSHIFT 16 +#define G2D_SXY2_X_FMASK 0x7ff +#define G2D_VGSPAN_WIDTH_FADDR ADDR_G2D_VGSPAN +#define G2D_VGSPAN_WIDTH_FSHIFT 0 +#define G2D_VGSPAN_WIDTH_FMASK 0xfff +#define G2D_VGSPAN_PAD_FADDR ADDR_G2D_VGSPAN +#define G2D_VGSPAN_PAD_FSHIFT 12 +#define G2D_VGSPAN_PAD_FMASK 0xf +#define G2D_VGSPAN_COVERAGE_FADDR ADDR_G2D_VGSPAN +#define G2D_VGSPAN_COVERAGE_FSHIFT 16 +#define G2D_VGSPAN_COVERAGE_FMASK 0xf +#define G2D_WIDTHHEIGHT_HEIGHT_FADDR ADDR_G2D_WIDTHHEIGHT +#define G2D_WIDTHHEIGHT_HEIGHT_FSHIFT 0 +#define G2D_WIDTHHEIGHT_HEIGHT_FMASK 0xfff +#define G2D_WIDTHHEIGHT_PAD_FADDR ADDR_G2D_WIDTHHEIGHT +#define G2D_WIDTHHEIGHT_PAD_FSHIFT 12 +#define G2D_WIDTHHEIGHT_PAD_FMASK 0xf +#define G2D_WIDTHHEIGHT_WIDTH_FADDR ADDR_G2D_WIDTHHEIGHT +#define G2D_WIDTHHEIGHT_WIDTH_FSHIFT 16 +#define G2D_WIDTHHEIGHT_WIDTH_FMASK 0xfff +#define G2D_XY_Y_FADDR ADDR_G2D_XY +#define G2D_XY_Y_FSHIFT 0 +#define G2D_XY_Y_FMASK 0xfff +#define G2D_XY_PAD_FADDR ADDR_G2D_XY +#define G2D_XY_PAD_FSHIFT 12 +#define G2D_XY_PAD_FMASK 0xf +#define G2D_XY_X_FADDR ADDR_G2D_XY +#define G2D_XY_X_FSHIFT 16 +#define G2D_XY_X_FMASK 0xfff +#define GRADW_BORDERCOLOR_COLOR_FADDR ADDR_GRADW_BORDERCOLOR +#define GRADW_BORDERCOLOR_COLOR_FSHIFT 0 +#define GRADW_BORDERCOLOR_COLOR_FMASK 0xffffffff +#define GRADW_CONST0_VALUE_FADDR ADDR_GRADW_CONST0 +#define GRADW_CONST0_VALUE_FSHIFT 0 +#define GRADW_CONST0_VALUE_FMASK 0xffff +#define GRADW_CONST1_VALUE_FADDR ADDR_GRADW_CONST1 +#define GRADW_CONST1_VALUE_FSHIFT 0 +#define GRADW_CONST1_VALUE_FMASK 0xffff +#define GRADW_CONST2_VALUE_FADDR ADDR_GRADW_CONST2 +#define GRADW_CONST2_VALUE_FSHIFT 0 +#define GRADW_CONST2_VALUE_FMASK 0xffff +#define GRADW_CONST3_VALUE_FADDR ADDR_GRADW_CONST3 +#define GRADW_CONST3_VALUE_FSHIFT 0 +#define GRADW_CONST3_VALUE_FMASK 0xffff +#define GRADW_CONST4_VALUE_FADDR ADDR_GRADW_CONST4 +#define GRADW_CONST4_VALUE_FSHIFT 0 +#define GRADW_CONST4_VALUE_FMASK 0xffff +#define GRADW_CONST5_VALUE_FADDR ADDR_GRADW_CONST5 +#define GRADW_CONST5_VALUE_FSHIFT 0 +#define GRADW_CONST5_VALUE_FMASK 0xffff +#define GRADW_CONST6_VALUE_FADDR ADDR_GRADW_CONST6 +#define GRADW_CONST6_VALUE_FSHIFT 0 +#define GRADW_CONST6_VALUE_FMASK 0xffff +#define GRADW_CONST7_VALUE_FADDR ADDR_GRADW_CONST7 +#define GRADW_CONST7_VALUE_FSHIFT 0 +#define GRADW_CONST7_VALUE_FMASK 0xffff +#define GRADW_CONST8_VALUE_FADDR ADDR_GRADW_CONST8 +#define GRADW_CONST8_VALUE_FSHIFT 0 +#define GRADW_CONST8_VALUE_FMASK 0xffff +#define GRADW_CONST9_VALUE_FADDR ADDR_GRADW_CONST9 +#define GRADW_CONST9_VALUE_FSHIFT 0 +#define GRADW_CONST9_VALUE_FMASK 0xffff +#define GRADW_CONSTA_VALUE_FADDR ADDR_GRADW_CONSTA +#define GRADW_CONSTA_VALUE_FSHIFT 0 +#define GRADW_CONSTA_VALUE_FMASK 0xffff +#define GRADW_CONSTB_VALUE_FADDR ADDR_GRADW_CONSTB +#define GRADW_CONSTB_VALUE_FSHIFT 0 +#define GRADW_CONSTB_VALUE_FMASK 0xffff +#define GRADW_INST0_SRC_E_FADDR ADDR_GRADW_INST0 +#define GRADW_INST0_SRC_E_FSHIFT 0 +#define GRADW_INST0_SRC_E_FMASK 0x1f +#define GRADW_INST0_SRC_D_FADDR ADDR_GRADW_INST0 +#define GRADW_INST0_SRC_D_FSHIFT 5 +#define GRADW_INST0_SRC_D_FMASK 0x1f +#define GRADW_INST0_SRC_C_FADDR ADDR_GRADW_INST0 +#define GRADW_INST0_SRC_C_FSHIFT 10 +#define GRADW_INST0_SRC_C_FMASK 0x1f +#define GRADW_INST0_SRC_B_FADDR ADDR_GRADW_INST0 +#define GRADW_INST0_SRC_B_FSHIFT 15 +#define GRADW_INST0_SRC_B_FMASK 0x1f +#define GRADW_INST0_SRC_A_FADDR ADDR_GRADW_INST0 +#define GRADW_INST0_SRC_A_FSHIFT 20 +#define GRADW_INST0_SRC_A_FMASK 0x1f +#define GRADW_INST0_DST_FADDR ADDR_GRADW_INST0 +#define GRADW_INST0_DST_FSHIFT 25 +#define GRADW_INST0_DST_FMASK 0xf +#define GRADW_INST0_OPCODE_FADDR ADDR_GRADW_INST0 +#define GRADW_INST0_OPCODE_FSHIFT 29 +#define GRADW_INST0_OPCODE_FMASK 0x3 +#define GRADW_INST1_SRC_E_FADDR ADDR_GRADW_INST1 +#define GRADW_INST1_SRC_E_FSHIFT 0 +#define GRADW_INST1_SRC_E_FMASK 0x1f +#define GRADW_INST1_SRC_D_FADDR ADDR_GRADW_INST1 +#define GRADW_INST1_SRC_D_FSHIFT 5 +#define GRADW_INST1_SRC_D_FMASK 0x1f +#define GRADW_INST1_SRC_C_FADDR ADDR_GRADW_INST1 +#define GRADW_INST1_SRC_C_FSHIFT 10 +#define GRADW_INST1_SRC_C_FMASK 0x1f +#define GRADW_INST1_SRC_B_FADDR ADDR_GRADW_INST1 +#define GRADW_INST1_SRC_B_FSHIFT 15 +#define GRADW_INST1_SRC_B_FMASK 0x1f +#define GRADW_INST1_SRC_A_FADDR ADDR_GRADW_INST1 +#define GRADW_INST1_SRC_A_FSHIFT 20 +#define GRADW_INST1_SRC_A_FMASK 0x1f +#define GRADW_INST1_DST_FADDR ADDR_GRADW_INST1 +#define GRADW_INST1_DST_FSHIFT 25 +#define GRADW_INST1_DST_FMASK 0xf +#define GRADW_INST1_OPCODE_FADDR ADDR_GRADW_INST1 +#define GRADW_INST1_OPCODE_FSHIFT 29 +#define GRADW_INST1_OPCODE_FMASK 0x3 +#define GRADW_INST2_SRC_E_FADDR ADDR_GRADW_INST2 +#define GRADW_INST2_SRC_E_FSHIFT 0 +#define GRADW_INST2_SRC_E_FMASK 0x1f +#define GRADW_INST2_SRC_D_FADDR ADDR_GRADW_INST2 +#define GRADW_INST2_SRC_D_FSHIFT 5 +#define GRADW_INST2_SRC_D_FMASK 0x1f +#define GRADW_INST2_SRC_C_FADDR ADDR_GRADW_INST2 +#define GRADW_INST2_SRC_C_FSHIFT 10 +#define GRADW_INST2_SRC_C_FMASK 0x1f +#define GRADW_INST2_SRC_B_FADDR ADDR_GRADW_INST2 +#define GRADW_INST2_SRC_B_FSHIFT 15 +#define GRADW_INST2_SRC_B_FMASK 0x1f +#define GRADW_INST2_SRC_A_FADDR ADDR_GRADW_INST2 +#define GRADW_INST2_SRC_A_FSHIFT 20 +#define GRADW_INST2_SRC_A_FMASK 0x1f +#define GRADW_INST2_DST_FADDR ADDR_GRADW_INST2 +#define GRADW_INST2_DST_FSHIFT 25 +#define GRADW_INST2_DST_FMASK 0xf +#define GRADW_INST2_OPCODE_FADDR ADDR_GRADW_INST2 +#define GRADW_INST2_OPCODE_FSHIFT 29 +#define GRADW_INST2_OPCODE_FMASK 0x3 +#define GRADW_INST3_SRC_E_FADDR ADDR_GRADW_INST3 +#define GRADW_INST3_SRC_E_FSHIFT 0 +#define GRADW_INST3_SRC_E_FMASK 0x1f +#define GRADW_INST3_SRC_D_FADDR ADDR_GRADW_INST3 +#define GRADW_INST3_SRC_D_FSHIFT 5 +#define GRADW_INST3_SRC_D_FMASK 0x1f +#define GRADW_INST3_SRC_C_FADDR ADDR_GRADW_INST3 +#define GRADW_INST3_SRC_C_FSHIFT 10 +#define GRADW_INST3_SRC_C_FMASK 0x1f +#define GRADW_INST3_SRC_B_FADDR ADDR_GRADW_INST3 +#define GRADW_INST3_SRC_B_FSHIFT 15 +#define GRADW_INST3_SRC_B_FMASK 0x1f +#define GRADW_INST3_SRC_A_FADDR ADDR_GRADW_INST3 +#define GRADW_INST3_SRC_A_FSHIFT 20 +#define GRADW_INST3_SRC_A_FMASK 0x1f +#define GRADW_INST3_DST_FADDR ADDR_GRADW_INST3 +#define GRADW_INST3_DST_FSHIFT 25 +#define GRADW_INST3_DST_FMASK 0xf +#define GRADW_INST3_OPCODE_FADDR ADDR_GRADW_INST3 +#define GRADW_INST3_OPCODE_FSHIFT 29 +#define GRADW_INST3_OPCODE_FMASK 0x3 +#define GRADW_INST4_SRC_E_FADDR ADDR_GRADW_INST4 +#define GRADW_INST4_SRC_E_FSHIFT 0 +#define GRADW_INST4_SRC_E_FMASK 0x1f +#define GRADW_INST4_SRC_D_FADDR ADDR_GRADW_INST4 +#define GRADW_INST4_SRC_D_FSHIFT 5 +#define GRADW_INST4_SRC_D_FMASK 0x1f +#define GRADW_INST4_SRC_C_FADDR ADDR_GRADW_INST4 +#define GRADW_INST4_SRC_C_FSHIFT 10 +#define GRADW_INST4_SRC_C_FMASK 0x1f +#define GRADW_INST4_SRC_B_FADDR ADDR_GRADW_INST4 +#define GRADW_INST4_SRC_B_FSHIFT 15 +#define GRADW_INST4_SRC_B_FMASK 0x1f +#define GRADW_INST4_SRC_A_FADDR ADDR_GRADW_INST4 +#define GRADW_INST4_SRC_A_FSHIFT 20 +#define GRADW_INST4_SRC_A_FMASK 0x1f +#define GRADW_INST4_DST_FADDR ADDR_GRADW_INST4 +#define GRADW_INST4_DST_FSHIFT 25 +#define GRADW_INST4_DST_FMASK 0xf +#define GRADW_INST4_OPCODE_FADDR ADDR_GRADW_INST4 +#define GRADW_INST4_OPCODE_FSHIFT 29 +#define GRADW_INST4_OPCODE_FMASK 0x3 +#define GRADW_INST5_SRC_E_FADDR ADDR_GRADW_INST5 +#define GRADW_INST5_SRC_E_FSHIFT 0 +#define GRADW_INST5_SRC_E_FMASK 0x1f +#define GRADW_INST5_SRC_D_FADDR ADDR_GRADW_INST5 +#define GRADW_INST5_SRC_D_FSHIFT 5 +#define GRADW_INST5_SRC_D_FMASK 0x1f +#define GRADW_INST5_SRC_C_FADDR ADDR_GRADW_INST5 +#define GRADW_INST5_SRC_C_FSHIFT 10 +#define GRADW_INST5_SRC_C_FMASK 0x1f +#define GRADW_INST5_SRC_B_FADDR ADDR_GRADW_INST5 +#define GRADW_INST5_SRC_B_FSHIFT 15 +#define GRADW_INST5_SRC_B_FMASK 0x1f +#define GRADW_INST5_SRC_A_FADDR ADDR_GRADW_INST5 +#define GRADW_INST5_SRC_A_FSHIFT 20 +#define GRADW_INST5_SRC_A_FMASK 0x1f +#define GRADW_INST5_DST_FADDR ADDR_GRADW_INST5 +#define GRADW_INST5_DST_FSHIFT 25 +#define GRADW_INST5_DST_FMASK 0xf +#define GRADW_INST5_OPCODE_FADDR ADDR_GRADW_INST5 +#define GRADW_INST5_OPCODE_FSHIFT 29 +#define GRADW_INST5_OPCODE_FMASK 0x3 +#define GRADW_INST6_SRC_E_FADDR ADDR_GRADW_INST6 +#define GRADW_INST6_SRC_E_FSHIFT 0 +#define GRADW_INST6_SRC_E_FMASK 0x1f +#define GRADW_INST6_SRC_D_FADDR ADDR_GRADW_INST6 +#define GRADW_INST6_SRC_D_FSHIFT 5 +#define GRADW_INST6_SRC_D_FMASK 0x1f +#define GRADW_INST6_SRC_C_FADDR ADDR_GRADW_INST6 +#define GRADW_INST6_SRC_C_FSHIFT 10 +#define GRADW_INST6_SRC_C_FMASK 0x1f +#define GRADW_INST6_SRC_B_FADDR ADDR_GRADW_INST6 +#define GRADW_INST6_SRC_B_FSHIFT 15 +#define GRADW_INST6_SRC_B_FMASK 0x1f +#define GRADW_INST6_SRC_A_FADDR ADDR_GRADW_INST6 +#define GRADW_INST6_SRC_A_FSHIFT 20 +#define GRADW_INST6_SRC_A_FMASK 0x1f +#define GRADW_INST6_DST_FADDR ADDR_GRADW_INST6 +#define GRADW_INST6_DST_FSHIFT 25 +#define GRADW_INST6_DST_FMASK 0xf +#define GRADW_INST6_OPCODE_FADDR ADDR_GRADW_INST6 +#define GRADW_INST6_OPCODE_FSHIFT 29 +#define GRADW_INST6_OPCODE_FMASK 0x3 +#define GRADW_INST7_SRC_E_FADDR ADDR_GRADW_INST7 +#define GRADW_INST7_SRC_E_FSHIFT 0 +#define GRADW_INST7_SRC_E_FMASK 0x1f +#define GRADW_INST7_SRC_D_FADDR ADDR_GRADW_INST7 +#define GRADW_INST7_SRC_D_FSHIFT 5 +#define GRADW_INST7_SRC_D_FMASK 0x1f +#define GRADW_INST7_SRC_C_FADDR ADDR_GRADW_INST7 +#define GRADW_INST7_SRC_C_FSHIFT 10 +#define GRADW_INST7_SRC_C_FMASK 0x1f +#define GRADW_INST7_SRC_B_FADDR ADDR_GRADW_INST7 +#define GRADW_INST7_SRC_B_FSHIFT 15 +#define GRADW_INST7_SRC_B_FMASK 0x1f +#define GRADW_INST7_SRC_A_FADDR ADDR_GRADW_INST7 +#define GRADW_INST7_SRC_A_FSHIFT 20 +#define GRADW_INST7_SRC_A_FMASK 0x1f +#define GRADW_INST7_DST_FADDR ADDR_GRADW_INST7 +#define GRADW_INST7_DST_FSHIFT 25 +#define GRADW_INST7_DST_FMASK 0xf +#define GRADW_INST7_OPCODE_FADDR ADDR_GRADW_INST7 +#define GRADW_INST7_OPCODE_FSHIFT 29 +#define GRADW_INST7_OPCODE_FMASK 0x3 +#define GRADW_TEXBASE_ADDR_FADDR ADDR_GRADW_TEXBASE +#define GRADW_TEXBASE_ADDR_FSHIFT 0 +#define GRADW_TEXBASE_ADDR_FMASK 0xffffffff +#define GRADW_TEXCFG_STRIDE_FADDR ADDR_GRADW_TEXCFG +#define GRADW_TEXCFG_STRIDE_FSHIFT 0 +#define GRADW_TEXCFG_STRIDE_FMASK 0xfff +#define GRADW_TEXCFG_FORMAT_FADDR ADDR_GRADW_TEXCFG +#define GRADW_TEXCFG_FORMAT_FSHIFT 12 +#define GRADW_TEXCFG_FORMAT_FMASK 0xf +#define GRADW_TEXCFG_TILED_FADDR ADDR_GRADW_TEXCFG +#define GRADW_TEXCFG_TILED_FSHIFT 16 +#define GRADW_TEXCFG_TILED_FMASK 0x1 +#define GRADW_TEXCFG_WRAPU_FADDR ADDR_GRADW_TEXCFG +#define GRADW_TEXCFG_WRAPU_FSHIFT 17 +#define GRADW_TEXCFG_WRAPU_FMASK 0x3 +#define GRADW_TEXCFG_WRAPV_FADDR ADDR_GRADW_TEXCFG +#define GRADW_TEXCFG_WRAPV_FSHIFT 19 +#define GRADW_TEXCFG_WRAPV_FMASK 0x3 +#define GRADW_TEXCFG_BILIN_FADDR ADDR_GRADW_TEXCFG +#define GRADW_TEXCFG_BILIN_FSHIFT 21 +#define GRADW_TEXCFG_BILIN_FMASK 0x1 +#define GRADW_TEXCFG_SRGB_FADDR ADDR_GRADW_TEXCFG +#define GRADW_TEXCFG_SRGB_FSHIFT 22 +#define GRADW_TEXCFG_SRGB_FMASK 0x1 +#define GRADW_TEXCFG_PREMULTIPLY_FADDR ADDR_GRADW_TEXCFG +#define GRADW_TEXCFG_PREMULTIPLY_FSHIFT 23 +#define GRADW_TEXCFG_PREMULTIPLY_FMASK 0x1 +#define GRADW_TEXCFG_SWAPWORDS_FADDR ADDR_GRADW_TEXCFG +#define GRADW_TEXCFG_SWAPWORDS_FSHIFT 24 +#define GRADW_TEXCFG_SWAPWORDS_FMASK 0x1 +#define GRADW_TEXCFG_SWAPBYTES_FADDR ADDR_GRADW_TEXCFG +#define GRADW_TEXCFG_SWAPBYTES_FSHIFT 25 +#define GRADW_TEXCFG_SWAPBYTES_FMASK 0x1 +#define GRADW_TEXCFG_SWAPALL_FADDR ADDR_GRADW_TEXCFG +#define GRADW_TEXCFG_SWAPALL_FSHIFT 26 +#define GRADW_TEXCFG_SWAPALL_FMASK 0x1 +#define GRADW_TEXCFG_SWAPRB_FADDR ADDR_GRADW_TEXCFG +#define GRADW_TEXCFG_SWAPRB_FSHIFT 27 +#define GRADW_TEXCFG_SWAPRB_FMASK 0x1 +#define GRADW_TEXCFG_TEX2D_FADDR ADDR_GRADW_TEXCFG +#define GRADW_TEXCFG_TEX2D_FSHIFT 28 +#define GRADW_TEXCFG_TEX2D_FMASK 0x1 +#define GRADW_TEXCFG_SWAPBITS_FADDR ADDR_GRADW_TEXCFG +#define GRADW_TEXCFG_SWAPBITS_FSHIFT 29 +#define GRADW_TEXCFG_SWAPBITS_FMASK 0x1 +#define GRADW_TEXSIZE_WIDTH_FADDR ADDR_GRADW_TEXSIZE +#define GRADW_TEXSIZE_WIDTH_FSHIFT 0 +#define GRADW_TEXSIZE_WIDTH_FMASK 0x7ff +#define GRADW_TEXSIZE_HEIGHT_FADDR ADDR_GRADW_TEXSIZE +#define GRADW_TEXSIZE_HEIGHT_FSHIFT 11 +#define GRADW_TEXSIZE_HEIGHT_FMASK 0x7ff +#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_FSHIFT 0 +#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_FMASK 0x3f +#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_FSHIFT 6 +#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_FMASK 0x1 +#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_FSHIFT 7 +#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_FMASK 0x1 +#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_FSHIFT 8 +#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_FMASK 0x1 +#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_FSHIFT 9 +#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_FMASK 0x1 +#define MH_ARBITER_CONFIG_PAGE_SIZE_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_PAGE_SIZE_FSHIFT 10 +#define MH_ARBITER_CONFIG_PAGE_SIZE_FMASK 0x7 +#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_FSHIFT 13 +#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_FMASK 0x1 +#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_FSHIFT 14 +#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_FMASK 0x1 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_FSHIFT 15 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_FMASK 0x1 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_FSHIFT 16 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_FMASK 0x3f +#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_FSHIFT 22 +#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_FMASK 0x1 +#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_FSHIFT 23 +#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_FMASK 0x1 +#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_FSHIFT 24 +#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_FMASK 0x1 +#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_FSHIFT 25 +#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_FMASK 0x1 +#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_FADDR ADDR_MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_FSHIFT 26 +#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_FMASK 0x1 +#define MH_AXI_ERROR_AXI_READ_ID_FADDR ADDR_MH_AXI_ERROR +#define MH_AXI_ERROR_AXI_READ_ID_FSHIFT 0 +#define MH_AXI_ERROR_AXI_READ_ID_FMASK 0x7 +#define MH_AXI_ERROR_AXI_READ_ERROR_FADDR ADDR_MH_AXI_ERROR +#define MH_AXI_ERROR_AXI_READ_ERROR_FSHIFT 3 +#define MH_AXI_ERROR_AXI_READ_ERROR_FMASK 0x1 +#define MH_AXI_ERROR_AXI_WRITE_ID_FADDR ADDR_MH_AXI_ERROR +#define MH_AXI_ERROR_AXI_WRITE_ID_FSHIFT 4 +#define MH_AXI_ERROR_AXI_WRITE_ID_FMASK 0x7 +#define MH_AXI_ERROR_AXI_WRITE_ERROR_FADDR ADDR_MH_AXI_ERROR +#define MH_AXI_ERROR_AXI_WRITE_ERROR_FSHIFT 7 +#define MH_AXI_ERROR_AXI_WRITE_ERROR_FMASK 0x1 +#define MH_AXI_HALT_CONTROL_AXI_HALT_FADDR ADDR_MH_AXI_HALT_CONTROL +#define MH_AXI_HALT_CONTROL_AXI_HALT_FSHIFT 0 +#define MH_AXI_HALT_CONTROL_AXI_HALT_FMASK 0x1 +#define MH_CLNT_AXI_ID_REUSE_CPW_ID_FADDR ADDR_MH_CLNT_AXI_ID_REUSE +#define MH_CLNT_AXI_ID_REUSE_CPW_ID_FSHIFT 0 +#define MH_CLNT_AXI_ID_REUSE_CPW_ID_FMASK 0x7 +#define MH_CLNT_AXI_ID_REUSE_PAD_FADDR ADDR_MH_CLNT_AXI_ID_REUSE +#define MH_CLNT_AXI_ID_REUSE_PAD_FSHIFT 3 +#define MH_CLNT_AXI_ID_REUSE_PAD_FMASK 0x1 +#define MH_CLNT_AXI_ID_REUSE_RBW_ID_FADDR ADDR_MH_CLNT_AXI_ID_REUSE +#define MH_CLNT_AXI_ID_REUSE_RBW_ID_FSHIFT 4 +#define MH_CLNT_AXI_ID_REUSE_RBW_ID_FMASK 0x7 +#define MH_CLNT_AXI_ID_REUSE_PAD2_FADDR ADDR_MH_CLNT_AXI_ID_REUSE +#define MH_CLNT_AXI_ID_REUSE_PAD2_FSHIFT 7 +#define MH_CLNT_AXI_ID_REUSE_PAD2_FMASK 0x1 +#define MH_CLNT_AXI_ID_REUSE_MMUR_ID_FADDR ADDR_MH_CLNT_AXI_ID_REUSE +#define MH_CLNT_AXI_ID_REUSE_MMUR_ID_FSHIFT 8 +#define MH_CLNT_AXI_ID_REUSE_MMUR_ID_FMASK 0x7 +#define MH_CLNT_AXI_ID_REUSE_PAD3_FADDR ADDR_MH_CLNT_AXI_ID_REUSE +#define MH_CLNT_AXI_ID_REUSE_PAD3_FSHIFT 11 +#define MH_CLNT_AXI_ID_REUSE_PAD3_FMASK 0x1 +#define MH_CLNT_AXI_ID_REUSE_PAW_ID_FADDR ADDR_MH_CLNT_AXI_ID_REUSE +#define MH_CLNT_AXI_ID_REUSE_PAW_ID_FSHIFT 12 +#define MH_CLNT_AXI_ID_REUSE_PAW_ID_FMASK 0x7 +#define MH_DEBUG_CTRL_INDEX_FADDR ADDR_MH_DEBUG_CTRL +#define MH_DEBUG_CTRL_INDEX_FSHIFT 0 +#define MH_DEBUG_CTRL_INDEX_FMASK 0x3f +#define MH_DEBUG_DATA_DATA_FADDR ADDR_MH_DEBUG_DATA +#define MH_DEBUG_DATA_DATA_FSHIFT 0 +#define MH_DEBUG_DATA_DATA_FMASK 0xffffffff +#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_FADDR ADDR_MH_INTERRUPT_CLEAR +#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_FSHIFT 0 +#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_FMASK 0x1 +#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_FADDR ADDR_MH_INTERRUPT_CLEAR +#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_FSHIFT 1 +#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_FMASK 0x1 +#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_FADDR ADDR_MH_INTERRUPT_CLEAR +#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_FSHIFT 2 +#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_FMASK 0x1 +#define MH_INTERRUPT_MASK_AXI_READ_ERROR_FADDR ADDR_MH_INTERRUPT_MASK +#define MH_INTERRUPT_MASK_AXI_READ_ERROR_FSHIFT 0 +#define MH_INTERRUPT_MASK_AXI_READ_ERROR_FMASK 0x1 +#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_FADDR ADDR_MH_INTERRUPT_MASK +#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_FSHIFT 1 +#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_FMASK 0x1 +#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_FADDR ADDR_MH_INTERRUPT_MASK +#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_FSHIFT 2 +#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_FMASK 0x1 +#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_FADDR ADDR_MH_INTERRUPT_STATUS +#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_FSHIFT 0 +#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_FMASK 0x1 +#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_FADDR ADDR_MH_INTERRUPT_STATUS +#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_FSHIFT 1 +#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_FMASK 0x1 +#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_FADDR ADDR_MH_INTERRUPT_STATUS +#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_FSHIFT 2 +#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_FMASK 0x1 +#define MH_MMU_CONFIG_MMU_ENABLE_FADDR ADDR_MH_MMU_CONFIG +#define MH_MMU_CONFIG_MMU_ENABLE_FSHIFT 0 +#define MH_MMU_CONFIG_MMU_ENABLE_FMASK 0x1 +#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_FADDR ADDR_MH_MMU_CONFIG +#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_FSHIFT 1 +#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_FMASK 0x1 +#define MH_MMU_CONFIG_PAD_FADDR ADDR_MH_MMU_CONFIG +#define MH_MMU_CONFIG_PAD_FSHIFT 2 +#define MH_MMU_CONFIG_PAD_FMASK 0x3 +#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG +#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_FSHIFT 4 +#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_FMASK 0x3 +#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG +#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_FSHIFT 6 +#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_FMASK 0x3 +#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG +#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_FSHIFT 8 +#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_FMASK 0x3 +#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG +#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_FSHIFT 10 +#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_FMASK 0x3 +#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG +#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_FSHIFT 12 +#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_FMASK 0x3 +#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG +#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_FSHIFT 14 +#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_FMASK 0x3 +#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG +#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_FSHIFT 16 +#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_FMASK 0x3 +#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG +#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_FSHIFT 18 +#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_FMASK 0x3 +#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG +#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_FSHIFT 20 +#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_FMASK 0x3 +#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG +#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_FSHIFT 22 +#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_FMASK 0x3 +#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_CONFIG +#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_FSHIFT 24 +#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_FMASK 0x3 +#define MH_MMU_INVALIDATE_INVALIDATE_ALL_FADDR ADDR_MH_MMU_INVALIDATE +#define MH_MMU_INVALIDATE_INVALIDATE_ALL_FSHIFT 0 +#define MH_MMU_INVALIDATE_INVALIDATE_ALL_FMASK 0x1 +#define MH_MMU_INVALIDATE_INVALIDATE_TC_FADDR ADDR_MH_MMU_INVALIDATE +#define MH_MMU_INVALIDATE_INVALIDATE_TC_FSHIFT 1 +#define MH_MMU_INVALIDATE_INVALIDATE_TC_FMASK 0x1 +#define MH_MMU_MPU_BASE_ZERO_FADDR ADDR_MH_MMU_MPU_BASE +#define MH_MMU_MPU_BASE_ZERO_FSHIFT 0 +#define MH_MMU_MPU_BASE_ZERO_FMASK 0xfff +#define MH_MMU_MPU_BASE_MPU_BASE_FADDR ADDR_MH_MMU_MPU_BASE +#define MH_MMU_MPU_BASE_MPU_BASE_FSHIFT 12 +#define MH_MMU_MPU_BASE_MPU_BASE_FMASK 0xfffff +#define MH_MMU_MPU_END_ZERO_FADDR ADDR_MH_MMU_MPU_END +#define MH_MMU_MPU_END_ZERO_FSHIFT 0 +#define MH_MMU_MPU_END_ZERO_FMASK 0xfff +#define MH_MMU_MPU_END_MPU_END_FADDR ADDR_MH_MMU_MPU_END +#define MH_MMU_MPU_END_MPU_END_FSHIFT 12 +#define MH_MMU_MPU_END_MPU_END_FMASK 0xfffff +#define MH_MMU_PAGE_FAULT_PAGE_FAULT_FADDR ADDR_MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT_PAGE_FAULT_FSHIFT 0 +#define MH_MMU_PAGE_FAULT_PAGE_FAULT_FMASK 0x1 +#define MH_MMU_PAGE_FAULT_OP_TYPE_FADDR ADDR_MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT_OP_TYPE_FSHIFT 1 +#define MH_MMU_PAGE_FAULT_OP_TYPE_FMASK 0x1 +#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_FADDR ADDR_MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_FSHIFT 2 +#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_FMASK 0x3 +#define MH_MMU_PAGE_FAULT_AXI_ID_FADDR ADDR_MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT_AXI_ID_FSHIFT 4 +#define MH_MMU_PAGE_FAULT_AXI_ID_FMASK 0x7 +#define MH_MMU_PAGE_FAULT_PAD_FADDR ADDR_MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT_PAD_FSHIFT 7 +#define MH_MMU_PAGE_FAULT_PAD_FMASK 0x1 +#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_FADDR ADDR_MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_FSHIFT 8 +#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_FMASK 0x1 +#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_FADDR ADDR_MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_FSHIFT 9 +#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_FMASK 0x1 +#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_FADDR ADDR_MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_FSHIFT 10 +#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_FMASK 0x1 +#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_FADDR ADDR_MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_FSHIFT 11 +#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_FMASK 0x1 +#define MH_MMU_PAGE_FAULT_REQ_VA_FADDR ADDR_MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT_REQ_VA_FSHIFT 12 +#define MH_MMU_PAGE_FAULT_REQ_VA_FMASK 0xfffff +#define MH_MMU_PT_BASE_ZERO_FADDR ADDR_MH_MMU_PT_BASE +#define MH_MMU_PT_BASE_ZERO_FSHIFT 0 +#define MH_MMU_PT_BASE_ZERO_FMASK 0xfff +#define MH_MMU_PT_BASE_PT_BASE_FADDR ADDR_MH_MMU_PT_BASE +#define MH_MMU_PT_BASE_PT_BASE_FSHIFT 12 +#define MH_MMU_PT_BASE_PT_BASE_FMASK 0xfffff +#define MH_MMU_TRAN_ERROR_ZERO_FADDR ADDR_MH_MMU_TRAN_ERROR +#define MH_MMU_TRAN_ERROR_ZERO_FSHIFT 0 +#define MH_MMU_TRAN_ERROR_ZERO_FMASK 0x1f +#define MH_MMU_TRAN_ERROR_TRAN_ERROR_FADDR ADDR_MH_MMU_TRAN_ERROR +#define MH_MMU_TRAN_ERROR_TRAN_ERROR_FSHIFT 5 +#define MH_MMU_TRAN_ERROR_TRAN_ERROR_FMASK 0x7ffffff +#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_FADDR ADDR_MH_MMU_VA_RANGE +#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_FSHIFT 0 +#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_FMASK 0xfff +#define MH_MMU_VA_RANGE_VA_BASE_FADDR ADDR_MH_MMU_VA_RANGE +#define MH_MMU_VA_RANGE_VA_BASE_FSHIFT 12 +#define MH_MMU_VA_RANGE_VA_BASE_FMASK 0xfffff +#define MH_PERFCOUNTER0_CONFIG_N_VALUE_FADDR ADDR_MH_PERFCOUNTER0_CONFIG +#define MH_PERFCOUNTER0_CONFIG_N_VALUE_FSHIFT 0 +#define MH_PERFCOUNTER0_CONFIG_N_VALUE_FMASK 0xff +#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_FADDR ADDR_MH_PERFCOUNTER0_HI +#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_FSHIFT 0 +#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_FMASK 0xffff +#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_FADDR ADDR_MH_PERFCOUNTER0_LOW +#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_FSHIFT 0 +#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_FMASK 0xffffffff +#define MH_PERFCOUNTER0_SELECT_PERF_SEL_FADDR ADDR_MH_PERFCOUNTER0_SELECT +#define MH_PERFCOUNTER0_SELECT_PERF_SEL_FSHIFT 0 +#define MH_PERFCOUNTER0_SELECT_PERF_SEL_FMASK 0xff +#define MH_PERFCOUNTER1_CONFIG_N_VALUE_FADDR ADDR_MH_PERFCOUNTER1_CONFIG +#define MH_PERFCOUNTER1_CONFIG_N_VALUE_FSHIFT 0 +#define MH_PERFCOUNTER1_CONFIG_N_VALUE_FMASK 0xff +#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_FADDR ADDR_MH_PERFCOUNTER1_HI +#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_FSHIFT 0 +#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_FMASK 0xffff +#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_FADDR ADDR_MH_PERFCOUNTER1_LOW +#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_FSHIFT 0 +#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_FMASK 0xffffffff +#define MH_PERFCOUNTER1_SELECT_PERF_SEL_FADDR ADDR_MH_PERFCOUNTER1_SELECT +#define MH_PERFCOUNTER1_SELECT_PERF_SEL_FSHIFT 0 +#define MH_PERFCOUNTER1_SELECT_PERF_SEL_FMASK 0xff +#define MMU_READ_ADDR_ADDR_FADDR ADDR_MMU_READ_ADDR +#define MMU_READ_ADDR_ADDR_FSHIFT 0 +#define MMU_READ_ADDR_ADDR_FMASK 0x7fff +#define MMU_READ_DATA_DATA_FADDR ADDR_MMU_READ_DATA +#define MMU_READ_DATA_DATA_FSHIFT 0 +#define MMU_READ_DATA_DATA_FMASK 0xffffffff +#define VGV1_CBASE1_ADDR_FADDR ADDR_VGV1_CBASE1 +#define VGV1_CBASE1_ADDR_FSHIFT 0 +#define VGV1_CBASE1_ADDR_FMASK 0xffffffff +#define VGV1_CFG1_WINDRULE_FADDR ADDR_VGV1_CFG1 +#define VGV1_CFG1_WINDRULE_FSHIFT 0 +#define VGV1_CFG1_WINDRULE_FMASK 0x1 +#define VGV1_CFG2_AAMODE_FADDR ADDR_VGV1_CFG2 +#define VGV1_CFG2_AAMODE_FSHIFT 0 +#define VGV1_CFG2_AAMODE_FMASK 0x3 +#define VGV1_DIRTYBASE_ADDR_FADDR ADDR_VGV1_DIRTYBASE +#define VGV1_DIRTYBASE_ADDR_FSHIFT 0 +#define VGV1_DIRTYBASE_ADDR_FMASK 0xffffffff +#define VGV1_FILL_INHERIT_FADDR ADDR_VGV1_FILL +#define VGV1_FILL_INHERIT_FSHIFT 0 +#define VGV1_FILL_INHERIT_FMASK 0x1 +#define VGV1_SCISSORX_LEFT_FADDR ADDR_VGV1_SCISSORX +#define VGV1_SCISSORX_LEFT_FSHIFT 0 +#define VGV1_SCISSORX_LEFT_FMASK 0x7ff +#define VGV1_SCISSORX_PAD_FADDR ADDR_VGV1_SCISSORX +#define VGV1_SCISSORX_PAD_FSHIFT 11 +#define VGV1_SCISSORX_PAD_FMASK 0x1f +#define VGV1_SCISSORX_RIGHT_FADDR ADDR_VGV1_SCISSORX +#define VGV1_SCISSORX_RIGHT_FSHIFT 16 +#define VGV1_SCISSORX_RIGHT_FMASK 0x7ff +#define VGV1_SCISSORY_TOP_FADDR ADDR_VGV1_SCISSORY +#define VGV1_SCISSORY_TOP_FSHIFT 0 +#define VGV1_SCISSORY_TOP_FMASK 0x7ff +#define VGV1_SCISSORY_PAD_FADDR ADDR_VGV1_SCISSORY +#define VGV1_SCISSORY_PAD_FSHIFT 11 +#define VGV1_SCISSORY_PAD_FMASK 0x1f +#define VGV1_SCISSORY_BOTTOM_FADDR ADDR_VGV1_SCISSORY +#define VGV1_SCISSORY_BOTTOM_FSHIFT 16 +#define VGV1_SCISSORY_BOTTOM_FMASK 0x7ff +#define VGV1_TILEOFS_X_FADDR ADDR_VGV1_TILEOFS +#define VGV1_TILEOFS_X_FSHIFT 0 +#define VGV1_TILEOFS_X_FMASK 0xfff +#define VGV1_TILEOFS_Y_FADDR ADDR_VGV1_TILEOFS +#define VGV1_TILEOFS_Y_FSHIFT 12 +#define VGV1_TILEOFS_Y_FMASK 0xfff +#define VGV1_TILEOFS_LEFTMOST_FADDR ADDR_VGV1_TILEOFS +#define VGV1_TILEOFS_LEFTMOST_FSHIFT 24 +#define VGV1_TILEOFS_LEFTMOST_FMASK 0x1 +#define VGV1_UBASE2_ADDR_FADDR ADDR_VGV1_UBASE2 +#define VGV1_UBASE2_ADDR_FSHIFT 0 +#define VGV1_UBASE2_ADDR_FMASK 0xffffffff +#define VGV1_VTX0_X_FADDR ADDR_VGV1_VTX0 +#define VGV1_VTX0_X_FSHIFT 0 +#define VGV1_VTX0_X_FMASK 0xffff +#define VGV1_VTX0_Y_FADDR ADDR_VGV1_VTX0 +#define VGV1_VTX0_Y_FSHIFT 16 +#define VGV1_VTX0_Y_FMASK 0xffff +#define VGV1_VTX1_X_FADDR ADDR_VGV1_VTX1 +#define VGV1_VTX1_X_FSHIFT 0 +#define VGV1_VTX1_X_FMASK 0xffff +#define VGV1_VTX1_Y_FADDR ADDR_VGV1_VTX1 +#define VGV1_VTX1_Y_FSHIFT 16 +#define VGV1_VTX1_Y_FMASK 0xffff +#define VGV2_ACCURACY_F_FADDR ADDR_VGV2_ACCURACY +#define VGV2_ACCURACY_F_FSHIFT 0 +#define VGV2_ACCURACY_F_FMASK 0xffffff +#define VGV2_ACTION_ACTION_FADDR ADDR_VGV2_ACTION +#define VGV2_ACTION_ACTION_FSHIFT 0 +#define VGV2_ACTION_ACTION_FMASK 0xf +#define VGV2_ARCCOS_F_FADDR ADDR_VGV2_ARCCOS +#define VGV2_ARCCOS_F_FSHIFT 0 +#define VGV2_ARCCOS_F_FMASK 0xffffff +#define VGV2_ARCSIN_F_FADDR ADDR_VGV2_ARCSIN +#define VGV2_ARCSIN_F_FSHIFT 0 +#define VGV2_ARCSIN_F_FMASK 0xffffff +#define VGV2_ARCTAN_F_FADDR ADDR_VGV2_ARCTAN +#define VGV2_ARCTAN_F_FSHIFT 0 +#define VGV2_ARCTAN_F_FMASK 0xffffff +#define VGV2_BBOXMAXX_F_FADDR ADDR_VGV2_BBOXMAXX +#define VGV2_BBOXMAXX_F_FSHIFT 0 +#define VGV2_BBOXMAXX_F_FMASK 0xffffff +#define VGV2_BBOXMAXY_F_FADDR ADDR_VGV2_BBOXMAXY +#define VGV2_BBOXMAXY_F_FSHIFT 0 +#define VGV2_BBOXMAXY_F_FMASK 0xffffff +#define VGV2_BBOXMINX_F_FADDR ADDR_VGV2_BBOXMINX +#define VGV2_BBOXMINX_F_FSHIFT 0 +#define VGV2_BBOXMINX_F_FMASK 0xffffff +#define VGV2_BBOXMINY_F_FADDR ADDR_VGV2_BBOXMINY +#define VGV2_BBOXMINY_F_FSHIFT 0 +#define VGV2_BBOXMINY_F_FMASK 0xffffff +#define VGV2_BIAS_F_FADDR ADDR_VGV2_BIAS +#define VGV2_BIAS_F_FSHIFT 0 +#define VGV2_BIAS_F_FMASK 0xffffff +#define VGV2_C1X_F_FADDR ADDR_VGV2_C1X +#define VGV2_C1X_F_FSHIFT 0 +#define VGV2_C1X_F_FMASK 0xffffff +#define VGV2_C1XREL_F_FADDR ADDR_VGV2_C1XREL +#define VGV2_C1XREL_F_FSHIFT 0 +#define VGV2_C1XREL_F_FMASK 0xffffff +#define VGV2_C1Y_F_FADDR ADDR_VGV2_C1Y +#define VGV2_C1Y_F_FSHIFT 0 +#define VGV2_C1Y_F_FMASK 0xffffff +#define VGV2_C1YREL_F_FADDR ADDR_VGV2_C1YREL +#define VGV2_C1YREL_F_FSHIFT 0 +#define VGV2_C1YREL_F_FMASK 0xffffff +#define VGV2_C2X_F_FADDR ADDR_VGV2_C2X +#define VGV2_C2X_F_FSHIFT 0 +#define VGV2_C2X_F_FMASK 0xffffff +#define VGV2_C2XREL_F_FADDR ADDR_VGV2_C2XREL +#define VGV2_C2XREL_F_FSHIFT 0 +#define VGV2_C2XREL_F_FMASK 0xffffff +#define VGV2_C2Y_F_FADDR ADDR_VGV2_C2Y +#define VGV2_C2Y_F_FSHIFT 0 +#define VGV2_C2Y_F_FMASK 0xffffff +#define VGV2_C2YREL_F_FADDR ADDR_VGV2_C2YREL +#define VGV2_C2YREL_F_FSHIFT 0 +#define VGV2_C2YREL_F_FMASK 0xffffff +#define VGV2_C3X_F_FADDR ADDR_VGV2_C3X +#define VGV2_C3X_F_FSHIFT 0 +#define VGV2_C3X_F_FMASK 0xffffff +#define VGV2_C3XREL_F_FADDR ADDR_VGV2_C3XREL +#define VGV2_C3XREL_F_FSHIFT 0 +#define VGV2_C3XREL_F_FMASK 0xffffff +#define VGV2_C3Y_F_FADDR ADDR_VGV2_C3Y +#define VGV2_C3Y_F_FSHIFT 0 +#define VGV2_C3Y_F_FMASK 0xffffff +#define VGV2_C3YREL_F_FADDR ADDR_VGV2_C3YREL +#define VGV2_C3YREL_F_FSHIFT 0 +#define VGV2_C3YREL_F_FMASK 0xffffff +#define VGV2_C4X_F_FADDR ADDR_VGV2_C4X +#define VGV2_C4X_F_FSHIFT 0 +#define VGV2_C4X_F_FMASK 0xffffff +#define VGV2_C4XREL_F_FADDR ADDR_VGV2_C4XREL +#define VGV2_C4XREL_F_FSHIFT 0 +#define VGV2_C4XREL_F_FMASK 0xffffff +#define VGV2_C4Y_F_FADDR ADDR_VGV2_C4Y +#define VGV2_C4Y_F_FSHIFT 0 +#define VGV2_C4Y_F_FMASK 0xffffff +#define VGV2_C4YREL_F_FADDR ADDR_VGV2_C4YREL +#define VGV2_C4YREL_F_FSHIFT 0 +#define VGV2_C4YREL_F_FMASK 0xffffff +#define VGV2_CLIP_F_FADDR ADDR_VGV2_CLIP +#define VGV2_CLIP_F_FSHIFT 0 +#define VGV2_CLIP_F_FMASK 0xffffff +#define VGV2_FIRST_DUMMY_FADDR ADDR_VGV2_FIRST +#define VGV2_FIRST_DUMMY_FSHIFT 0 +#define VGV2_FIRST_DUMMY_FMASK 0x1 +#define VGV2_LAST_DUMMY_FADDR ADDR_VGV2_LAST +#define VGV2_LAST_DUMMY_FSHIFT 0 +#define VGV2_LAST_DUMMY_FMASK 0x1 +#define VGV2_MITER_F_FADDR ADDR_VGV2_MITER +#define VGV2_MITER_F_FSHIFT 0 +#define VGV2_MITER_F_FMASK 0xffffff +#define VGV2_MODE_MAXSPLIT_FADDR ADDR_VGV2_MODE +#define VGV2_MODE_MAXSPLIT_FSHIFT 0 +#define VGV2_MODE_MAXSPLIT_FMASK 0xf +#define VGV2_MODE_CAP_FADDR ADDR_VGV2_MODE +#define VGV2_MODE_CAP_FSHIFT 4 +#define VGV2_MODE_CAP_FMASK 0x3 +#define VGV2_MODE_JOIN_FADDR ADDR_VGV2_MODE +#define VGV2_MODE_JOIN_FSHIFT 6 +#define VGV2_MODE_JOIN_FMASK 0x3 +#define VGV2_MODE_STROKE_FADDR ADDR_VGV2_MODE +#define VGV2_MODE_STROKE_FSHIFT 8 +#define VGV2_MODE_STROKE_FMASK 0x1 +#define VGV2_MODE_STROKESPLIT_FADDR ADDR_VGV2_MODE +#define VGV2_MODE_STROKESPLIT_FSHIFT 9 +#define VGV2_MODE_STROKESPLIT_FMASK 0x1 +#define VGV2_MODE_FULLSPLIT_FADDR ADDR_VGV2_MODE +#define VGV2_MODE_FULLSPLIT_FSHIFT 10 +#define VGV2_MODE_FULLSPLIT_FMASK 0x1 +#define VGV2_MODE_NODOTS_FADDR ADDR_VGV2_MODE +#define VGV2_MODE_NODOTS_FSHIFT 11 +#define VGV2_MODE_NODOTS_FMASK 0x1 +#define VGV2_MODE_OPENFILL_FADDR ADDR_VGV2_MODE +#define VGV2_MODE_OPENFILL_FSHIFT 12 +#define VGV2_MODE_OPENFILL_FMASK 0x1 +#define VGV2_MODE_DROPLEFT_FADDR ADDR_VGV2_MODE +#define VGV2_MODE_DROPLEFT_FSHIFT 13 +#define VGV2_MODE_DROPLEFT_FMASK 0x1 +#define VGV2_MODE_DROPOTHER_FADDR ADDR_VGV2_MODE +#define VGV2_MODE_DROPOTHER_FSHIFT 14 +#define VGV2_MODE_DROPOTHER_FMASK 0x1 +#define VGV2_MODE_SYMMETRICJOINS_FADDR ADDR_VGV2_MODE +#define VGV2_MODE_SYMMETRICJOINS_FSHIFT 15 +#define VGV2_MODE_SYMMETRICJOINS_FMASK 0x1 +#define VGV2_MODE_SIMPLESTROKE_FADDR ADDR_VGV2_MODE +#define VGV2_MODE_SIMPLESTROKE_FSHIFT 16 +#define VGV2_MODE_SIMPLESTROKE_FMASK 0x1 +#define VGV2_MODE_SIMPLECLIP_FADDR ADDR_VGV2_MODE +#define VGV2_MODE_SIMPLECLIP_FSHIFT 17 +#define VGV2_MODE_SIMPLECLIP_FMASK 0x1 +#define VGV2_MODE_EXPONENTADD_FADDR ADDR_VGV2_MODE +#define VGV2_MODE_EXPONENTADD_FSHIFT 18 +#define VGV2_MODE_EXPONENTADD_FMASK 0x3f +#define VGV2_RADIUS_F_FADDR ADDR_VGV2_RADIUS +#define VGV2_RADIUS_F_FSHIFT 0 +#define VGV2_RADIUS_F_FMASK 0xffffff +#define VGV2_SCALE_F_FADDR ADDR_VGV2_SCALE +#define VGV2_SCALE_F_FSHIFT 0 +#define VGV2_SCALE_F_FMASK 0xffffff +#define VGV2_THINRADIUS_F_FADDR ADDR_VGV2_THINRADIUS +#define VGV2_THINRADIUS_F_FSHIFT 0 +#define VGV2_THINRADIUS_F_FMASK 0xffffff +#define VGV2_XFSTXX_F_FADDR ADDR_VGV2_XFSTXX +#define VGV2_XFSTXX_F_FSHIFT 0 +#define VGV2_XFSTXX_F_FMASK 0xffffff +#define VGV2_XFSTXY_F_FADDR ADDR_VGV2_XFSTXY +#define VGV2_XFSTXY_F_FSHIFT 0 +#define VGV2_XFSTXY_F_FMASK 0xffffff +#define VGV2_XFSTYX_F_FADDR ADDR_VGV2_XFSTYX +#define VGV2_XFSTYX_F_FSHIFT 0 +#define VGV2_XFSTYX_F_FMASK 0xffffff +#define VGV2_XFSTYY_F_FADDR ADDR_VGV2_XFSTYY +#define VGV2_XFSTYY_F_FSHIFT 0 +#define VGV2_XFSTYY_F_FMASK 0xffffff +#define VGV2_XFXA_F_FADDR ADDR_VGV2_XFXA +#define VGV2_XFXA_F_FSHIFT 0 +#define VGV2_XFXA_F_FMASK 0xffffff +#define VGV2_XFXX_F_FADDR ADDR_VGV2_XFXX +#define VGV2_XFXX_F_FSHIFT 0 +#define VGV2_XFXX_F_FMASK 0xffffff +#define VGV2_XFXY_F_FADDR ADDR_VGV2_XFXY +#define VGV2_XFXY_F_FSHIFT 0 +#define VGV2_XFXY_F_FMASK 0xffffff +#define VGV2_XFYA_F_FADDR ADDR_VGV2_XFYA +#define VGV2_XFYA_F_FSHIFT 0 +#define VGV2_XFYA_F_FMASK 0xffffff +#define VGV2_XFYX_F_FADDR ADDR_VGV2_XFYX +#define VGV2_XFYX_F_FSHIFT 0 +#define VGV2_XFYX_F_FMASK 0xffffff +#define VGV2_XFYY_F_FADDR ADDR_VGV2_XFYY +#define VGV2_XFYY_F_FSHIFT 0 +#define VGV2_XFYY_F_FMASK 0xffffff +#define VGV3_CONTROL_MARKADD_FADDR ADDR_VGV3_CONTROL +#define VGV3_CONTROL_MARKADD_FSHIFT 0 +#define VGV3_CONTROL_MARKADD_FMASK 0xfff +#define VGV3_CONTROL_DMIWAITCHMASK_FADDR ADDR_VGV3_CONTROL +#define VGV3_CONTROL_DMIWAITCHMASK_FSHIFT 12 +#define VGV3_CONTROL_DMIWAITCHMASK_FMASK 0xf +#define VGV3_CONTROL_PAUSE_FADDR ADDR_VGV3_CONTROL +#define VGV3_CONTROL_PAUSE_FSHIFT 16 +#define VGV3_CONTROL_PAUSE_FMASK 0x1 +#define VGV3_CONTROL_ABORT_FADDR ADDR_VGV3_CONTROL +#define VGV3_CONTROL_ABORT_FSHIFT 17 +#define VGV3_CONTROL_ABORT_FMASK 0x1 +#define VGV3_CONTROL_WRITE_FADDR ADDR_VGV3_CONTROL +#define VGV3_CONTROL_WRITE_FSHIFT 18 +#define VGV3_CONTROL_WRITE_FMASK 0x1 +#define VGV3_CONTROL_BCFLUSH_FADDR ADDR_VGV3_CONTROL +#define VGV3_CONTROL_BCFLUSH_FSHIFT 19 +#define VGV3_CONTROL_BCFLUSH_FMASK 0x1 +#define VGV3_CONTROL_V0SYNC_FADDR ADDR_VGV3_CONTROL +#define VGV3_CONTROL_V0SYNC_FSHIFT 20 +#define VGV3_CONTROL_V0SYNC_FMASK 0x1 +#define VGV3_CONTROL_DMIWAITBUF_FADDR ADDR_VGV3_CONTROL +#define VGV3_CONTROL_DMIWAITBUF_FSHIFT 21 +#define VGV3_CONTROL_DMIWAITBUF_FMASK 0x7 +#define VGV3_FIRST_DUMMY_FADDR ADDR_VGV3_FIRST +#define VGV3_FIRST_DUMMY_FSHIFT 0 +#define VGV3_FIRST_DUMMY_FMASK 0x1 +#define VGV3_LAST_DUMMY_FADDR ADDR_VGV3_LAST +#define VGV3_LAST_DUMMY_FSHIFT 0 +#define VGV3_LAST_DUMMY_FMASK 0x1 +#define VGV3_MODE_FLIPENDIAN_FADDR ADDR_VGV3_MODE +#define VGV3_MODE_FLIPENDIAN_FSHIFT 0 +#define VGV3_MODE_FLIPENDIAN_FMASK 0x1 +#define VGV3_MODE_UNUSED_FADDR ADDR_VGV3_MODE +#define VGV3_MODE_UNUSED_FSHIFT 1 +#define VGV3_MODE_UNUSED_FMASK 0x1 +#define VGV3_MODE_WRITEFLUSH_FADDR ADDR_VGV3_MODE +#define VGV3_MODE_WRITEFLUSH_FSHIFT 2 +#define VGV3_MODE_WRITEFLUSH_FMASK 0x1 +#define VGV3_MODE_DMIPAUSETYPE_FADDR ADDR_VGV3_MODE +#define VGV3_MODE_DMIPAUSETYPE_FSHIFT 3 +#define VGV3_MODE_DMIPAUSETYPE_FMASK 0x1 +#define VGV3_MODE_DMIRESET_FADDR ADDR_VGV3_MODE +#define VGV3_MODE_DMIRESET_FSHIFT 4 +#define VGV3_MODE_DMIRESET_FMASK 0x1 +#define VGV3_NEXTADDR_CALLADDR_FADDR ADDR_VGV3_NEXTADDR +#define VGV3_NEXTADDR_CALLADDR_FSHIFT 0 +#define VGV3_NEXTADDR_CALLADDR_FMASK 0xffffffff +#define VGV3_NEXTCMD_COUNT_FADDR ADDR_VGV3_NEXTCMD +#define VGV3_NEXTCMD_COUNT_FSHIFT 0 +#define VGV3_NEXTCMD_COUNT_FMASK 0xfff +#define VGV3_NEXTCMD_NEXTCMD_FADDR ADDR_VGV3_NEXTCMD +#define VGV3_NEXTCMD_NEXTCMD_FSHIFT 12 +#define VGV3_NEXTCMD_NEXTCMD_FMASK 0x7 +#define VGV3_NEXTCMD_MARK_FADDR ADDR_VGV3_NEXTCMD +#define VGV3_NEXTCMD_MARK_FSHIFT 15 +#define VGV3_NEXTCMD_MARK_FMASK 0x1 +#define VGV3_NEXTCMD_CALLCOUNT_FADDR ADDR_VGV3_NEXTCMD +#define VGV3_NEXTCMD_CALLCOUNT_FSHIFT 16 +#define VGV3_NEXTCMD_CALLCOUNT_FMASK 0xfff +#define VGV3_VGBYPASS_BYPASS_FADDR ADDR_VGV3_VGBYPASS +#define VGV3_VGBYPASS_BYPASS_FSHIFT 0 +#define VGV3_VGBYPASS_BYPASS_FMASK 0x1 +#define VGV3_WRITE_VALUE_FADDR ADDR_VGV3_WRITE +#define VGV3_WRITE_VALUE_FSHIFT 0 +#define VGV3_WRITE_VALUE_FMASK 0xffffffff +#define VGV3_WRITEADDR_ADDR_FADDR ADDR_VGV3_WRITEADDR +#define VGV3_WRITEADDR_ADDR_FSHIFT 0 +#define VGV3_WRITEADDR_ADDR_FMASK 0xffffffff +#define VGV3_WRITEDMI_CHANMASK_FADDR ADDR_VGV3_WRITEDMI +#define VGV3_WRITEDMI_CHANMASK_FSHIFT 0 +#define VGV3_WRITEDMI_CHANMASK_FMASK 0xf +#define VGV3_WRITEDMI_BUFFER_FADDR ADDR_VGV3_WRITEDMI +#define VGV3_WRITEDMI_BUFFER_FSHIFT 4 +#define VGV3_WRITEDMI_BUFFER_FMASK 0x7 +#define VGV3_WRITEF32_ADDR_FADDR ADDR_VGV3_WRITEF32 +#define VGV3_WRITEF32_ADDR_FSHIFT 0 +#define VGV3_WRITEF32_ADDR_FMASK 0xff +#define VGV3_WRITEF32_COUNT_FADDR ADDR_VGV3_WRITEF32 +#define VGV3_WRITEF32_COUNT_FSHIFT 8 +#define VGV3_WRITEF32_COUNT_FMASK 0xff +#define VGV3_WRITEF32_LOOP_FADDR ADDR_VGV3_WRITEF32 +#define VGV3_WRITEF32_LOOP_FSHIFT 16 +#define VGV3_WRITEF32_LOOP_FMASK 0xf +#define VGV3_WRITEF32_ACTION_FADDR ADDR_VGV3_WRITEF32 +#define VGV3_WRITEF32_ACTION_FSHIFT 20 +#define VGV3_WRITEF32_ACTION_FMASK 0xf +#define VGV3_WRITEF32_FORMAT_FADDR ADDR_VGV3_WRITEF32 +#define VGV3_WRITEF32_FORMAT_FSHIFT 24 +#define VGV3_WRITEF32_FORMAT_FMASK 0x7 +#define VGV3_WRITEIFPAUSED_VALUE_FADDR ADDR_VGV3_WRITEIFPAUSED +#define VGV3_WRITEIFPAUSED_VALUE_FSHIFT 0 +#define VGV3_WRITEIFPAUSED_VALUE_FMASK 0xffffffff +#define VGV3_WRITERAW_ADDR_FADDR ADDR_VGV3_WRITERAW +#define VGV3_WRITERAW_ADDR_FSHIFT 0 +#define VGV3_WRITERAW_ADDR_FMASK 0xff +#define VGV3_WRITERAW_COUNT_FADDR ADDR_VGV3_WRITERAW +#define VGV3_WRITERAW_COUNT_FSHIFT 8 +#define VGV3_WRITERAW_COUNT_FMASK 0xff +#define VGV3_WRITERAW_LOOP_FADDR ADDR_VGV3_WRITERAW +#define VGV3_WRITERAW_LOOP_FSHIFT 16 +#define VGV3_WRITERAW_LOOP_FMASK 0xf +#define VGV3_WRITERAW_ACTION_FADDR ADDR_VGV3_WRITERAW +#define VGV3_WRITERAW_ACTION_FSHIFT 20 +#define VGV3_WRITERAW_ACTION_FMASK 0xf +#define VGV3_WRITERAW_FORMAT_FADDR ADDR_VGV3_WRITERAW +#define VGV3_WRITERAW_FORMAT_FSHIFT 24 +#define VGV3_WRITERAW_FORMAT_FMASK 0x7 +#define VGV3_WRITES16_ADDR_FADDR ADDR_VGV3_WRITES16 +#define VGV3_WRITES16_ADDR_FSHIFT 0 +#define VGV3_WRITES16_ADDR_FMASK 0xff +#define VGV3_WRITES16_COUNT_FADDR ADDR_VGV3_WRITES16 +#define VGV3_WRITES16_COUNT_FSHIFT 8 +#define VGV3_WRITES16_COUNT_FMASK 0xff +#define VGV3_WRITES16_LOOP_FADDR ADDR_VGV3_WRITES16 +#define VGV3_WRITES16_LOOP_FSHIFT 16 +#define VGV3_WRITES16_LOOP_FMASK 0xf +#define VGV3_WRITES16_ACTION_FADDR ADDR_VGV3_WRITES16 +#define VGV3_WRITES16_ACTION_FSHIFT 20 +#define VGV3_WRITES16_ACTION_FMASK 0xf +#define VGV3_WRITES16_FORMAT_FADDR ADDR_VGV3_WRITES16 +#define VGV3_WRITES16_FORMAT_FSHIFT 24 +#define VGV3_WRITES16_FORMAT_FMASK 0x7 +#define VGV3_WRITES32_ADDR_FADDR ADDR_VGV3_WRITES32 +#define VGV3_WRITES32_ADDR_FSHIFT 0 +#define VGV3_WRITES32_ADDR_FMASK 0xff +#define VGV3_WRITES32_COUNT_FADDR ADDR_VGV3_WRITES32 +#define VGV3_WRITES32_COUNT_FSHIFT 8 +#define VGV3_WRITES32_COUNT_FMASK 0xff +#define VGV3_WRITES32_LOOP_FADDR ADDR_VGV3_WRITES32 +#define VGV3_WRITES32_LOOP_FSHIFT 16 +#define VGV3_WRITES32_LOOP_FMASK 0xf +#define VGV3_WRITES32_ACTION_FADDR ADDR_VGV3_WRITES32 +#define VGV3_WRITES32_ACTION_FSHIFT 20 +#define VGV3_WRITES32_ACTION_FMASK 0xf +#define VGV3_WRITES32_FORMAT_FADDR ADDR_VGV3_WRITES32 +#define VGV3_WRITES32_FORMAT_FSHIFT 24 +#define VGV3_WRITES32_FORMAT_FMASK 0x7 +#define VGV3_WRITES8_ADDR_FADDR ADDR_VGV3_WRITES8 +#define VGV3_WRITES8_ADDR_FSHIFT 0 +#define VGV3_WRITES8_ADDR_FMASK 0xff +#define VGV3_WRITES8_COUNT_FADDR ADDR_VGV3_WRITES8 +#define VGV3_WRITES8_COUNT_FSHIFT 8 +#define VGV3_WRITES8_COUNT_FMASK 0xff +#define VGV3_WRITES8_LOOP_FADDR ADDR_VGV3_WRITES8 +#define VGV3_WRITES8_LOOP_FSHIFT 16 +#define VGV3_WRITES8_LOOP_FMASK 0xf +#define VGV3_WRITES8_ACTION_FADDR ADDR_VGV3_WRITES8 +#define VGV3_WRITES8_ACTION_FSHIFT 20 +#define VGV3_WRITES8_ACTION_FMASK 0xf +#define VGV3_WRITES8_FORMAT_FADDR ADDR_VGV3_WRITES8 +#define VGV3_WRITES8_FORMAT_FSHIFT 24 +#define VGV3_WRITES8_FORMAT_FMASK 0x7 +typedef struct { + unsigned RS[256]; + unsigned GRADW[2][40]; +} regstate_t; + +#define GRADW_WINDOW_START 0xc0 +#define GRADW_WINDOW_LEN 0x28 +#define GRADW_WINDOW_NUM 0x2 + +static unsigned __inline __getwrs__(regstate_t* RS, unsigned win, unsigned addr, unsigned shift, unsigned mask) { + if ( addr >= 0xc0 && addr < 0xe8 ) { + assert( win < 2 ); + return (RS->GRADW[win][addr-0xc0] >> + shift) & mask; + } + return ((RS->RS[addr] >> shift) & mask); +} + +static void __inline __setwrs__(regstate_t* RS, unsigned win, unsigned addr, unsigned shift, unsigned mask, unsigned data) { + if ( addr >= 0xc0 && addr < 0xe8 ) { + assert( win < 2 ); + RS->GRADW[win][addr-0xc0] = (RS->GRADW[win][addr-0xc0] & + ~(mask << shift)) | + ((mask & data) << shift); + } + RS->RS[addr] = (RS->RS[addr] & ~(mask << shift)) | ((mask & data) << shift); +} + +static void __inline __setwreg__(regstate_t* RS, unsigned win, unsigned addr, unsigned data) { + if ( addr >= 0xc0 && addr < 0xe8 ) { + assert( win < 2 ); + RS->GRADW[win][addr-0xc0] = data; + } + RS->RS[addr] = data; +} + +static unsigned __inline __getrs__(regstate_t* RS, unsigned addr, unsigned shift, unsigned mask) { + return ((RS->RS[addr] >> shift) & mask); +} + +static void __inline __setrs__(regstate_t* RS, unsigned addr, unsigned shift, unsigned mask, unsigned data) { + if ( addr >= 0xc0 && addr < 0xe8 ) { + unsigned win = __getrs__(RS, G2D_GRADIENT_SEL_FADDR, G2D_GRADIENT_SEL_FSHIFT, G2D_GRADIENT_SEL_FMASK); + assert( win < 2 ); + RS->GRADW[win][addr-0xc0] = (RS->GRADW[win][addr-0xc0] & + ~(mask << shift)) | ((mask & data) << shift); + } + RS->RS[addr] = (RS->RS[addr] & ~(mask << shift)) | ((mask & data) << shift); +} + +static void __inline __setreg__(regstate_t* RS, unsigned addr, unsigned data) { + if ( addr >= 0xc0 && addr < 0xe8 ) { + unsigned win = __getrs__(RS, G2D_GRADIENT_SEL_FADDR, G2D_GRADIENT_SEL_FSHIFT, G2D_GRADIENT_SEL_FMASK); + assert( win < 2 ); + RS->GRADW[win][addr-0xc0] = data; + } + RS->RS[addr] = data; +} + +#define SETWRS(win, id, value) __setwrs__(&RS, win, id##_FADDR, id##_FSHIFT, id##_FMASK, value) +#define GETWRS(win, id) __getwrs__(&RS, win, id##_FADDR, id##_FSHIFT, id##_FMASK) +#define SETWREG(win, reg, data) __setwreg__(&RS, win, reg, data) +#define SETRS(id, value) __setrs__(&RS, id##_FADDR, id##_FSHIFT, id##_FMASK, value) +#define GETRS(id) __getrs__(&RS, id##_FADDR, id##_FSHIFT, id##_FMASK) +#define SETREG(reg, data) __setreg__(&RS, reg, data) +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato.h b/drivers/mxc/amd-gpu/include/reg/yamato.h new file mode 100644 index 000000000000..05cae6c46403 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato.h @@ -0,0 +1,66 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _YAMATO_H +#define _YAMATO_H + +#ifndef qLittleEndian +#define qLittleEndian +#endif + +#if defined(_YDX14) +#if defined(_WIN32) && !defined(__SYMBIAN32__) +#pragma message("YDX 14 header files\r\n") +#endif +#include "yamato/14/yamato_enum.h" +#include "yamato/14/yamato_ipt.h" +#include "yamato/14/yamato_mask.h" +#include "yamato/14/yamato_offset.h" +#include "yamato/14/yamato_registers.h" +#include "yamato/14/yamato_shift.h" +#include "yamato/14/yamato_struct.h" +#include "yamato/14/yamato_typedef.h" +#define _YAMATO_GENENUM_H "reg/yamato/14/yamato_genenum.h" +#define _YAMATO_GENREG_H "reg/yamato/14/yamato_genreg.h" +#else +#if defined(_WIN32) && !defined(__SYMBIAN32__) +#pragma message("YDX 22 header files\r\n") +#endif +#include "yamato/22/yamato_enum.h" +#include "yamato/22/yamato_ipt.h" +#include "yamato/22/yamato_mask.h" +#include "yamato/22/yamato_offset.h" +#include "yamato/22/yamato_registers.h" +#include "yamato/22/yamato_shift.h" +#include "yamato/22/yamato_struct.h" +#include "yamato/22/yamato_typedef.h" +#define _YAMATO_GENENUM_H "reg/yamato/22/yamato_genenum.h" +#define _YAMATO_GENREG_H "reg/yamato/22/yamato_genreg.h" +#endif + +#endif // _YAMATO_H diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_enum.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_enum.h new file mode 100644 index 000000000000..144e9151fd8a --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_enum.h @@ -0,0 +1,1895 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_ENUM_HEADER) +#define _yamato_ENUM_HEADER + +#ifndef _DRIVER_BUILD +#ifndef GL_ZERO +#define GL__ZERO BLEND_ZERO +#define GL__ONE BLEND_ONE +#define GL__SRC_COLOR BLEND_SRC_COLOR +#define GL__ONE_MINUS_SRC_COLOR BLEND_ONE_MINUS_SRC_COLOR +#define GL__DST_COLOR BLEND_DST_COLOR +#define GL__ONE_MINUS_DST_COLOR BLEND_ONE_MINUS_DST_COLOR +#define GL__SRC_ALPHA BLEND_SRC_ALPHA +#define GL__ONE_MINUS_SRC_ALPHA BLEND_ONE_MINUS_SRC_ALPHA +#define GL__DST_ALPHA BLEND_DST_ALPHA +#define GL__ONE_MINUS_DST_ALPHA BLEND_ONE_MINUS_DST_ALPHA +#define GL__SRC_ALPHA_SATURATE BLEND_SRC_ALPHA_SATURATE +#define GL__CONSTANT_COLOR BLEND_CONSTANT_COLOR +#define GL__ONE_MINUS_CONSTANT_COLOR BLEND_ONE_MINUS_CONSTANT_COLOR +#define GL__CONSTANT_ALPHA BLEND_CONSTANT_ALPHA +#define GL__ONE_MINUS_CONSTANT_ALPHA BLEND_ONE_MINUS_CONSTANT_ALPHA +#endif +#endif + +/******************************************************* + * PA Enums + *******************************************************/ +#ifndef ENUMS_SU_PERFCNT_SELECT_H +#define ENUMS_SU_PERFCNT_SELECT_H +typedef enum SU_PERFCNT_SELECT { + PERF_PAPC_PASX_REQ = 0, + UNUSED1 = 1, + PERF_PAPC_PASX_FIRST_VECTOR = 2, + PERF_PAPC_PASX_SECOND_VECTOR = 3, + PERF_PAPC_PASX_FIRST_DEAD = 4, + PERF_PAPC_PASX_SECOND_DEAD = 5, + PERF_PAPC_PASX_VTX_KILL_DISCARD = 6, + PERF_PAPC_PASX_VTX_NAN_DISCARD = 7, + PERF_PAPC_PA_INPUT_PRIM = 8, + PERF_PAPC_PA_INPUT_NULL_PRIM = 9, + PERF_PAPC_PA_INPUT_EVENT_FLAG = 10, + PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11, + PERF_PAPC_PA_INPUT_END_OF_PACKET = 12, + PERF_PAPC_CLPR_CULL_PRIM = 13, + UNUSED2 = 14, + PERF_PAPC_CLPR_VV_CULL_PRIM = 15, + UNUSED3 = 16, + PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 17, + PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 18, + PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 19, + UNUSED4 = 20, + PERF_PAPC_CLPR_VV_CLIP_PRIM = 21, + UNUSED5 = 22, + PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 23, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 24, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 25, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 26, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 27, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_5 = 28, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_6 = 29, + PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 30, + PERF_PAPC_CLPR_CLIP_PLANE_FAR = 31, + PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 32, + PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 33, + PERF_PAPC_CLPR_CLIP_PLANE_TOP = 34, + PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 35, + PERF_PAPC_CLSM_NULL_PRIM = 36, + PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 37, + PERF_PAPC_CLSM_CLIP_PRIM = 38, + PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 39, + PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 40, + PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 41, + PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 42, + PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 43, + PERF_PAPC_CLSM_OUT_PRIM_CNT_5 = 44, + PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7 = 45, + PERF_PAPC_CLSM_NON_TRIVIAL_CULL = 46, + PERF_PAPC_SU_INPUT_PRIM = 47, + PERF_PAPC_SU_INPUT_CLIP_PRIM = 48, + PERF_PAPC_SU_INPUT_NULL_PRIM = 49, + PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 50, + PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 51, + PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 52, + PERF_PAPC_SU_POLYMODE_FACE_CULL = 53, + PERF_PAPC_SU_POLYMODE_BACK_CULL = 54, + PERF_PAPC_SU_POLYMODE_FRONT_CULL = 55, + PERF_PAPC_SU_POLYMODE_INVALID_FILL = 56, + PERF_PAPC_SU_OUTPUT_PRIM = 57, + PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 58, + PERF_PAPC_SU_OUTPUT_NULL_PRIM = 59, + PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 60, + PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 61, + PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 62, + PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 63, + PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 64, + PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 65, + PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 66, + PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 67, + PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 68, + PERF_PAPC_PASX_REQ_IDLE = 69, + PERF_PAPC_PASX_REQ_BUSY = 70, + PERF_PAPC_PASX_REQ_STALLED = 71, + PERF_PAPC_PASX_REC_IDLE = 72, + PERF_PAPC_PASX_REC_BUSY = 73, + PERF_PAPC_PASX_REC_STARVED_SX = 74, + PERF_PAPC_PASX_REC_STALLED = 75, + PERF_PAPC_PASX_REC_STALLED_POS_MEM = 76, + PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 77, + PERF_PAPC_CCGSM_IDLE = 78, + PERF_PAPC_CCGSM_BUSY = 79, + PERF_PAPC_CCGSM_STALLED = 80, + PERF_PAPC_CLPRIM_IDLE = 81, + PERF_PAPC_CLPRIM_BUSY = 82, + PERF_PAPC_CLPRIM_STALLED = 83, + PERF_PAPC_CLPRIM_STARVED_CCGSM = 84, + PERF_PAPC_CLIPSM_IDLE = 85, + PERF_PAPC_CLIPSM_BUSY = 86, + PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 87, + PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 88, + PERF_PAPC_CLIPSM_WAIT_CLIPGA = 89, + PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 90, + PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 91, + PERF_PAPC_CLIPGA_IDLE = 92, + PERF_PAPC_CLIPGA_BUSY = 93, + PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 94, + PERF_PAPC_CLIPGA_STALLED = 95, + PERF_PAPC_CLIP_IDLE = 96, + PERF_PAPC_CLIP_BUSY = 97, + PERF_PAPC_SU_IDLE = 98, + PERF_PAPC_SU_BUSY = 99, + PERF_PAPC_SU_STARVED_CLIP = 100, + PERF_PAPC_SU_STALLED_SC = 101, + PERF_PAPC_SU_FACENESS_CULL = 102, +} SU_PERFCNT_SELECT; +#endif /*ENUMS_SU_PERFCNT_SELECT_H*/ + +#ifndef ENUMS_SC_PERFCNT_SELECT_H +#define ENUMS_SC_PERFCNT_SELECT_H +typedef enum SC_PERFCNT_SELECT { + SC_SR_WINDOW_VALID = 0, + SC_CW_WINDOW_VALID = 1, + SC_QM_WINDOW_VALID = 2, + SC_FW_WINDOW_VALID = 3, + SC_EZ_WINDOW_VALID = 4, + SC_IT_WINDOW_VALID = 5, + SC_STARVED_BY_PA = 6, + SC_STALLED_BY_RB_TILE = 7, + SC_STALLED_BY_RB_SAMP = 8, + SC_STARVED_BY_RB_EZ = 9, + SC_STALLED_BY_SAMPLE_FF = 10, + SC_STALLED_BY_SQ = 11, + SC_STALLED_BY_SP = 12, + SC_TOTAL_NO_PRIMS = 13, + SC_NON_EMPTY_PRIMS = 14, + SC_NO_TILES_PASSING_QM = 15, + SC_NO_PIXELS_PRE_EZ = 16, + SC_NO_PIXELS_POST_EZ = 17, +} SC_PERFCNT_SELECT; +#endif /*ENUMS_SC_PERFCNT_SELECT_H*/ + +/******************************************************* + * VGT Enums + *******************************************************/ +#ifndef ENUMS_VGT_DI_PRIM_TYPE_H +#define ENUMS_VGT_DI_PRIM_TYPE_H +typedef enum VGT_DI_PRIM_TYPE { + DI_PT_NONE = 0, + DI_PT_POINTLIST = 1, + DI_PT_LINELIST = 2, + DI_PT_LINESTRIP = 3, + DI_PT_TRILIST = 4, + DI_PT_TRIFAN = 5, + DI_PT_TRISTRIP = 6, + DI_PT_UNUSED_1 = 7, + DI_PT_RECTLIST = 8, + DI_PT_UNUSED_2 = 9, + DI_PT_UNUSED_3 = 10, + DI_PT_UNUSED_4 = 11, + DI_PT_UNUSED_5 = 12, + DI_PT_QUADLIST = 13, + DI_PT_QUADSTRIP = 14, + DI_PT_POLYGON = 15, + DI_PT_2D_COPY_RECT_LIST_V0 = 16, + DI_PT_2D_COPY_RECT_LIST_V1 = 17, + DI_PT_2D_COPY_RECT_LIST_V2 = 18, + DI_PT_2D_COPY_RECT_LIST_V3 = 19, + DI_PT_2D_FILL_RECT_LIST = 20, + DI_PT_2D_LINE_STRIP = 21, + DI_PT_2D_TRI_STRIP = 22, +} VGT_DI_PRIM_TYPE; +#endif /*ENUMS_VGT_DI_PRIM_TYPE_H*/ + +#ifndef ENUMS_VGT_DI_SOURCE_SELECT_H +#define ENUMS_VGT_DI_SOURCE_SELECT_H +typedef enum VGT_DI_SOURCE_SELECT { + DI_SRC_SEL_DMA = 0, + DI_SRC_SEL_IMMEDIATE = 1, + DI_SRC_SEL_AUTO_INDEX = 2, + DI_SRC_SEL_RESERVED = 3 +} VGT_DI_SOURCE_SELECT; +#endif /*ENUMS_VGT_DI_SOURCE_SELECT_H*/ + +#ifndef ENUMS_VGT_DI_FACENESS_CULL_SELECT_H +#define ENUMS_VGT_DI_FACENESS_CULL_SELECT_H +typedef enum VGT_DI_FACENESS_CULL_SELECT { + DI_FACE_CULL_NONE = 0, + DI_FACE_CULL_FETCH = 1, + DI_FACE_BACKFACE_CULL = 2, + DI_FACE_FRONTFACE_CULL = 3 +} VGT_DI_FACENESS_CULL_SELECT; +#endif /*ENUMS_VGT_DI_FACENESS_CULL_SELECT_H*/ + +#ifndef ENUMS_VGT_DI_INDEX_SIZE_H +#define ENUMS_VGT_DI_INDEX_SIZE_H +typedef enum VGT_DI_INDEX_SIZE { + DI_INDEX_SIZE_16_BIT = 0, + DI_INDEX_SIZE_32_BIT = 1 +} VGT_DI_INDEX_SIZE; +#endif /*ENUMS_VGT_DI_INDEX_SIZE_H*/ + +#ifndef ENUMS_VGT_DI_SMALL_INDEX_H +#define ENUMS_VGT_DI_SMALL_INDEX_H +typedef enum VGT_DI_SMALL_INDEX { + DI_USE_INDEX_SIZE = 0, + DI_INDEX_SIZE_8_BIT = 1 +} VGT_DI_SMALL_INDEX; +#endif /*ENUMS_VGT_DI_SMALL_INDEX_H*/ + +#ifndef ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H +#define ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H +typedef enum VGT_DI_PRE_FETCH_CULL_ENABLE { + DISABLE_PRE_FETCH_CULL_ENABLE = 0, + PRE_FETCH_CULL_ENABLE = 1 +} VGT_DI_PRE_FETCH_CULL_ENABLE; +#endif /*ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H*/ + +#ifndef ENUMS_VGT_DI_GRP_CULL_ENABLE_H +#define ENUMS_VGT_DI_GRP_CULL_ENABLE_H +typedef enum VGT_DI_GRP_CULL_ENABLE { + DISABLE_GRP_CULL_ENABLE = 0, + GRP_CULL_ENABLE = 1 +} VGT_DI_GRP_CULL_ENABLE; +#endif /*ENUMS_VGT_DI_GRP_CULL_ENABLE_H*/ + +#ifndef ENUMS_VGT_EVENT_TYPE_H +#define ENUMS_VGT_EVENT_TYPE_H +typedef enum VGT_EVENT_TYPE { + VS_DEALLOC = 0, + PS_DEALLOC = 1, + VS_DONE_TS = 2, + PS_DONE_TS = 3, + CACHE_FLUSH_TS = 4, + CONTEXT_DONE = 5, + CACHE_FLUSH = 6, + VIZQUERY_START = 7, + VIZQUERY_END = 8, + SC_WAIT_WC = 9, + RST_PIX_CNT = 13, + RST_VTX_CNT = 14, + TILE_FLUSH = 15, + CACHE_FLUSH_AND_INV_TS_EVENT = 20, + ZPASS_DONE = 21, + CACHE_FLUSH_AND_INV_EVENT = 22, + PERFCOUNTER_START = 23, + PERFCOUNTER_STOP = 24, + VS_FETCH_DONE = 27, + FACENESS_FLUSH = 28, +} VGT_EVENT_TYPE; +#endif /*ENUMS_VGT_EVENT_TYPE_H*/ + +#ifndef ENUMS_VGT_DMA_SWAP_MODE_H +#define ENUMS_VGT_DMA_SWAP_MODE_H +typedef enum VGT_DMA_SWAP_MODE { + VGT_DMA_SWAP_NONE = 0, + VGT_DMA_SWAP_16_BIT = 1, + VGT_DMA_SWAP_32_BIT = 2, + VGT_DMA_SWAP_WORD = 3 +} VGT_DMA_SWAP_MODE; +#endif /*ENUMS_VGT_DMA_SWAP_MODE_H*/ + +#ifndef ENUMS_VGT_PERFCOUNT_SELECT_H +#define ENUMS_VGT_PERFCOUNT_SELECT_H +typedef enum VGT_PERFCOUNT_SELECT { + VGT_SQ_EVENT_WINDOW_ACTIVE = 0, + VGT_SQ_SEND = 1, + VGT_SQ_STALLED = 2, + VGT_SQ_STARVED_BUSY = 3, + VGT_SQ_STARVED_IDLE = 4, + VGT_SQ_STATIC = 5, + VGT_PA_EVENT_WINDOW_ACTIVE = 6, + VGT_PA_CLIP_V_SEND = 7, + VGT_PA_CLIP_V_STALLED = 8, + VGT_PA_CLIP_V_STARVED_BUSY = 9, + VGT_PA_CLIP_V_STARVED_IDLE = 10, + VGT_PA_CLIP_V_STATIC = 11, + VGT_PA_CLIP_P_SEND = 12, + VGT_PA_CLIP_P_STALLED = 13, + VGT_PA_CLIP_P_STARVED_BUSY = 14, + VGT_PA_CLIP_P_STARVED_IDLE = 15, + VGT_PA_CLIP_P_STATIC = 16, + VGT_PA_CLIP_S_SEND = 17, + VGT_PA_CLIP_S_STALLED = 18, + VGT_PA_CLIP_S_STARVED_BUSY = 19, + VGT_PA_CLIP_S_STARVED_IDLE = 20, + VGT_PA_CLIP_S_STATIC = 21, + RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 22, + RBIU_IMMED_DATA_FIFO_STARVED = 23, + RBIU_IMMED_DATA_FIFO_STALLED = 24, + RBIU_DMA_REQUEST_FIFO_STARVED = 25, + RBIU_DMA_REQUEST_FIFO_STALLED = 26, + RBIU_DRAW_INITIATOR_FIFO_STARVED = 27, + RBIU_DRAW_INITIATOR_FIFO_STALLED = 28, + BIN_PRIM_NEAR_CULL = 29, + BIN_PRIM_ZERO_CULL = 30, + BIN_PRIM_FAR_CULL = 31, + BIN_PRIM_BIN_CULL = 32, + BIN_PRIM_FACE_CULL = 33, + SPARE34 = 34, + SPARE35 = 35, + SPARE36 = 36, + SPARE37 = 37, + SPARE38 = 38, + SPARE39 = 39, + TE_SU_IN_VALID = 40, + TE_SU_IN_READ = 41, + TE_SU_IN_PRIM = 42, + TE_SU_IN_EOP = 43, + TE_SU_IN_NULL_PRIM = 44, + TE_WK_IN_VALID = 45, + TE_WK_IN_READ = 46, + TE_OUT_PRIM_VALID = 47, + TE_OUT_PRIM_READ = 48, +} VGT_PERFCOUNT_SELECT; +#endif /*ENUMS_VGT_PERFCOUNT_SELECT_H*/ + +/******************************************************* + * TP Enums + *******************************************************/ +#ifndef ENUMS_TCR_PERFCOUNT_SELECT_H +#define ENUMS_TCR_PERFCOUNT_SELECT_H +typedef enum TCR_PERFCOUNT_SELECT { + DGMMPD_IPMUX0_STALL = 0, + reserved_46 = 1, + reserved_47 = 2, + reserved_48 = 3, + DGMMPD_IPMUX_ALL_STALL = 4, + OPMUX0_L2_WRITES = 5, + reserved_49 = 6, + reserved_50 = 7, + reserved_51 = 8, +} TCR_PERFCOUNT_SELECT; +#endif /*ENUMS_TCR_PERFCOUNT_SELECT_H*/ + +#ifndef ENUMS_TP_PERFCOUNT_SELECT_H +#define ENUMS_TP_PERFCOUNT_SELECT_H +typedef enum TP_PERFCOUNT_SELECT { + POINT_QUADS = 0, + BILIN_QUADS = 1, + ANISO_QUADS = 2, + MIP_QUADS = 3, + VOL_QUADS = 4, + MIP_VOL_QUADS = 5, + MIP_ANISO_QUADS = 6, + VOL_ANISO_QUADS = 7, + ANISO_2_1_QUADS = 8, + ANISO_4_1_QUADS = 9, + ANISO_6_1_QUADS = 10, + ANISO_8_1_QUADS = 11, + ANISO_10_1_QUADS = 12, + ANISO_12_1_QUADS = 13, + ANISO_14_1_QUADS = 14, + ANISO_16_1_QUADS = 15, + MIP_VOL_ANISO_QUADS = 16, + ALIGN_2_QUADS = 17, + ALIGN_4_QUADS = 18, + PIX_0_QUAD = 19, + PIX_1_QUAD = 20, + PIX_2_QUAD = 21, + PIX_3_QUAD = 22, + PIX_4_QUAD = 23, + TP_MIPMAP_LOD0 = 24, + TP_MIPMAP_LOD1 = 25, + TP_MIPMAP_LOD2 = 26, + TP_MIPMAP_LOD3 = 27, + TP_MIPMAP_LOD4 = 28, + TP_MIPMAP_LOD5 = 29, + TP_MIPMAP_LOD6 = 30, + TP_MIPMAP_LOD7 = 31, + TP_MIPMAP_LOD8 = 32, + TP_MIPMAP_LOD9 = 33, + TP_MIPMAP_LOD10 = 34, + TP_MIPMAP_LOD11 = 35, + TP_MIPMAP_LOD12 = 36, + TP_MIPMAP_LOD13 = 37, + TP_MIPMAP_LOD14 = 38, +} TP_PERFCOUNT_SELECT; +#endif /*ENUMS_TP_PERFCOUNT_SELECT_H*/ + +#ifndef ENUMS_TCM_PERFCOUNT_SELECT_H +#define ENUMS_TCM_PERFCOUNT_SELECT_H +typedef enum TCM_PERFCOUNT_SELECT { + QUAD0_RD_LAT_FIFO_EMPTY = 0, + reserved_01 = 1, + reserved_02 = 2, + QUAD0_RD_LAT_FIFO_4TH_FULL = 3, + QUAD0_RD_LAT_FIFO_HALF_FULL = 4, + QUAD0_RD_LAT_FIFO_FULL = 5, + QUAD0_RD_LAT_FIFO_LT_4TH_FULL = 6, + reserved_07 = 7, + reserved_08 = 8, + reserved_09 = 9, + reserved_10 = 10, + reserved_11 = 11, + reserved_12 = 12, + reserved_13 = 13, + reserved_14 = 14, + reserved_15 = 15, + reserved_16 = 16, + reserved_17 = 17, + reserved_18 = 18, + reserved_19 = 19, + reserved_20 = 20, + reserved_21 = 21, + reserved_22 = 22, + reserved_23 = 23, + reserved_24 = 24, + reserved_25 = 25, + reserved_26 = 26, + reserved_27 = 27, + READ_STARVED_QUAD0 = 28, + reserved_29 = 29, + reserved_30 = 30, + reserved_31 = 31, + READ_STARVED = 32, + READ_STALLED_QUAD0 = 33, + reserved_34 = 34, + reserved_35 = 35, + reserved_36 = 36, + READ_STALLED = 37, + VALID_READ_QUAD0 = 38, + reserved_39 = 39, + reserved_40 = 40, + reserved_41 = 41, + TC_TP_STARVED_QUAD0 = 42, + reserved_43 = 43, + reserved_44 = 44, + reserved_45 = 45, + TC_TP_STARVED = 46, +} TCM_PERFCOUNT_SELECT; +#endif /*ENUMS_TCM_PERFCOUNT_SELECT_H*/ + +#ifndef ENUMS_TCF_PERFCOUNT_SELECT_H +#define ENUMS_TCF_PERFCOUNT_SELECT_H +typedef enum TCF_PERFCOUNT_SELECT { + VALID_CYCLES = 0, + SINGLE_PHASES = 1, + ANISO_PHASES = 2, + MIP_PHASES = 3, + VOL_PHASES = 4, + MIP_VOL_PHASES = 5, + MIP_ANISO_PHASES = 6, + VOL_ANISO_PHASES = 7, + ANISO_2_1_PHASES = 8, + ANISO_4_1_PHASES = 9, + ANISO_6_1_PHASES = 10, + ANISO_8_1_PHASES = 11, + ANISO_10_1_PHASES = 12, + ANISO_12_1_PHASES = 13, + ANISO_14_1_PHASES = 14, + ANISO_16_1_PHASES = 15, + MIP_VOL_ANISO_PHASES = 16, + ALIGN_2_PHASES = 17, + ALIGN_4_PHASES = 18, + TPC_BUSY = 19, + TPC_STALLED = 20, + TPC_STARVED = 21, + TPC_WORKING = 22, + TPC_WALKER_BUSY = 23, + TPC_WALKER_STALLED = 24, + TPC_WALKER_WORKING = 25, + TPC_ALIGNER_BUSY = 26, + TPC_ALIGNER_STALLED = 27, + TPC_ALIGNER_STALLED_BY_BLEND = 28, + TPC_ALIGNER_STALLED_BY_CACHE = 29, + TPC_ALIGNER_WORKING = 30, + TPC_BLEND_BUSY = 31, + TPC_BLEND_SYNC = 32, + TPC_BLEND_STARVED = 33, + TPC_BLEND_WORKING = 34, + OPCODE_0x00 = 35, + OPCODE_0x01 = 36, + OPCODE_0x04 = 37, + OPCODE_0x10 = 38, + OPCODE_0x11 = 39, + OPCODE_0x12 = 40, + OPCODE_0x13 = 41, + OPCODE_0x18 = 42, + OPCODE_0x19 = 43, + OPCODE_0x1A = 44, + OPCODE_OTHER = 45, + IN_FIFO_0_EMPTY = 56, + IN_FIFO_0_LT_HALF_FULL = 57, + IN_FIFO_0_HALF_FULL = 58, + IN_FIFO_0_FULL = 59, + IN_FIFO_TPC_EMPTY = 72, + IN_FIFO_TPC_LT_HALF_FULL = 73, + IN_FIFO_TPC_HALF_FULL = 74, + IN_FIFO_TPC_FULL = 75, + TPC_TC_XFC = 76, + TPC_TC_STATE = 77, + TC_STALL = 78, + QUAD0_TAPS = 79, + QUADS = 83, + TCA_SYNC_STALL = 84, + TAG_STALL = 85, + TCB_SYNC_STALL = 88, + TCA_VALID = 89, + PROBES_VALID = 90, + MISS_STALL = 91, + FETCH_FIFO_STALL = 92, + TCO_STALL = 93, + ANY_STALL = 94, + TAG_MISSES = 95, + TAG_HITS = 96, + SUB_TAG_MISSES = 97, + SET0_INVALIDATES = 98, + SET1_INVALIDATES = 99, + SET2_INVALIDATES = 100, + SET3_INVALIDATES = 101, + SET0_TAG_MISSES = 102, + SET1_TAG_MISSES = 103, + SET2_TAG_MISSES = 104, + SET3_TAG_MISSES = 105, + SET0_TAG_HITS = 106, + SET1_TAG_HITS = 107, + SET2_TAG_HITS = 108, + SET3_TAG_HITS = 109, + SET0_SUB_TAG_MISSES = 110, + SET1_SUB_TAG_MISSES = 111, + SET2_SUB_TAG_MISSES = 112, + SET3_SUB_TAG_MISSES = 113, + SET0_EVICT1 = 114, + SET0_EVICT2 = 115, + SET0_EVICT3 = 116, + SET0_EVICT4 = 117, + SET0_EVICT5 = 118, + SET0_EVICT6 = 119, + SET0_EVICT7 = 120, + SET0_EVICT8 = 121, + SET1_EVICT1 = 130, + SET1_EVICT2 = 131, + SET1_EVICT3 = 132, + SET1_EVICT4 = 133, + SET1_EVICT5 = 134, + SET1_EVICT6 = 135, + SET1_EVICT7 = 136, + SET1_EVICT8 = 137, + SET2_EVICT1 = 146, + SET2_EVICT2 = 147, + SET2_EVICT3 = 148, + SET2_EVICT4 = 149, + SET2_EVICT5 = 150, + SET2_EVICT6 = 151, + SET2_EVICT7 = 152, + SET2_EVICT8 = 153, + SET3_EVICT1 = 162, + SET3_EVICT2 = 163, + SET3_EVICT3 = 164, + SET3_EVICT4 = 165, + SET3_EVICT5 = 166, + SET3_EVICT6 = 167, + SET3_EVICT7 = 168, + SET3_EVICT8 = 169, + FF_EMPTY = 178, + FF_LT_HALF_FULL = 179, + FF_HALF_FULL = 180, + FF_FULL = 181, + FF_XFC = 182, + FF_STALLED = 183, + FG_MASKS = 184, + FG_LEFT_MASKS = 185, + FG_LEFT_MASK_STALLED = 186, + FG_LEFT_NOT_DONE_STALL = 187, + FG_LEFT_FG_STALL = 188, + FG_LEFT_SECTORS = 189, + FG0_REQUESTS = 195, + FG0_STALLED = 196, + MEM_REQ512 = 199, + MEM_REQ_SENT = 200, + MEM_LOCAL_READ_REQ = 202, + TC0_MH_STALLED = 203, +} TCF_PERFCOUNT_SELECT; +#endif /*ENUMS_TCF_PERFCOUNT_SELECT_H*/ + +/******************************************************* + * TC Enums + *******************************************************/ +/******************************************************* + * SQ Enums + *******************************************************/ +#ifndef ENUMS_SQ_PERFCNT_SELECT_H +#define ENUMS_SQ_PERFCNT_SELECT_H +typedef enum SQ_PERFCNT_SELECT { + SQ_PIXEL_VECTORS_SUB = 0, + SQ_VERTEX_VECTORS_SUB = 1, + SQ_ALU0_ACTIVE_VTX_SIMD0 = 2, + SQ_ALU1_ACTIVE_VTX_SIMD0 = 3, + SQ_ALU0_ACTIVE_PIX_SIMD0 = 4, + SQ_ALU1_ACTIVE_PIX_SIMD0 = 5, + SQ_ALU0_ACTIVE_VTX_SIMD1 = 6, + SQ_ALU1_ACTIVE_VTX_SIMD1 = 7, + SQ_ALU0_ACTIVE_PIX_SIMD1 = 8, + SQ_ALU1_ACTIVE_PIX_SIMD1 = 9, + SQ_EXPORT_CYCLES = 10, + SQ_ALU_CST_WRITTEN = 11, + SQ_TEX_CST_WRITTEN = 12, + SQ_ALU_CST_STALL = 13, + SQ_ALU_TEX_STALL = 14, + SQ_INST_WRITTEN = 15, + SQ_BOOLEAN_WRITTEN = 16, + SQ_LOOPS_WRITTEN = 17, + SQ_PIXEL_SWAP_IN = 18, + SQ_PIXEL_SWAP_OUT = 19, + SQ_VERTEX_SWAP_IN = 20, + SQ_VERTEX_SWAP_OUT = 21, + SQ_ALU_VTX_INST_ISSUED = 22, + SQ_TEX_VTX_INST_ISSUED = 23, + SQ_VC_VTX_INST_ISSUED = 24, + SQ_CF_VTX_INST_ISSUED = 25, + SQ_ALU_PIX_INST_ISSUED = 26, + SQ_TEX_PIX_INST_ISSUED = 27, + SQ_VC_PIX_INST_ISSUED = 28, + SQ_CF_PIX_INST_ISSUED = 29, + SQ_ALU0_FIFO_EMPTY_SIMD0 = 30, + SQ_ALU1_FIFO_EMPTY_SIMD0 = 31, + SQ_ALU0_FIFO_EMPTY_SIMD1 = 32, + SQ_ALU1_FIFO_EMPTY_SIMD1 = 33, + SQ_ALU_NOPS = 34, + SQ_PRED_SKIP = 35, + SQ_SYNC_ALU_STALL_SIMD0_VTX = 36, + SQ_SYNC_ALU_STALL_SIMD1_VTX = 37, + SQ_SYNC_TEX_STALL_VTX = 38, + SQ_SYNC_VC_STALL_VTX = 39, + SQ_CONSTANTS_USED_SIMD0 = 40, + SQ_CONSTANTS_SENT_SP_SIMD0 = 41, + SQ_GPR_STALL_VTX = 42, + SQ_GPR_STALL_PIX = 43, + SQ_VTX_RS_STALL = 44, + SQ_PIX_RS_STALL = 45, + SQ_SX_PC_FULL = 46, + SQ_SX_EXP_BUFF_FULL = 47, + SQ_SX_POS_BUFF_FULL = 48, + SQ_INTERP_QUADS = 49, + SQ_INTERP_ACTIVE = 50, + SQ_IN_PIXEL_STALL = 51, + SQ_IN_VTX_STALL = 52, + SQ_VTX_CNT = 53, + SQ_VTX_VECTOR2 = 54, + SQ_VTX_VECTOR3 = 55, + SQ_VTX_VECTOR4 = 56, + SQ_PIXEL_VECTOR1 = 57, + SQ_PIXEL_VECTOR23 = 58, + SQ_PIXEL_VECTOR4 = 59, + SQ_CONSTANTS_USED_SIMD1 = 60, + SQ_CONSTANTS_SENT_SP_SIMD1 = 61, + SQ_SX_MEM_EXP_FULL = 62, + SQ_ALU0_ACTIVE_VTX_SIMD2 = 63, + SQ_ALU1_ACTIVE_VTX_SIMD2 = 64, + SQ_ALU0_ACTIVE_PIX_SIMD2 = 65, + SQ_ALU1_ACTIVE_PIX_SIMD2 = 66, + SQ_ALU0_ACTIVE_VTX_SIMD3 = 67, + SQ_PERFCOUNT_VTX_QUAL_TP_DONE = 68, + SQ_ALU0_ACTIVE_PIX_SIMD3 = 69, + SQ_PERFCOUNT_PIX_QUAL_TP_DONE = 70, + SQ_ALU0_FIFO_EMPTY_SIMD2 = 71, + SQ_ALU1_FIFO_EMPTY_SIMD2 = 72, + SQ_ALU0_FIFO_EMPTY_SIMD3 = 73, + SQ_ALU1_FIFO_EMPTY_SIMD3 = 74, + SQ_SYNC_ALU_STALL_SIMD2_VTX = 75, + SQ_PERFCOUNT_VTX_POP_THREAD = 76, + SQ_SYNC_ALU_STALL_SIMD0_PIX = 77, + SQ_SYNC_ALU_STALL_SIMD1_PIX = 78, + SQ_SYNC_ALU_STALL_SIMD2_PIX = 79, + SQ_PERFCOUNT_PIX_POP_THREAD = 80, + SQ_SYNC_TEX_STALL_PIX = 81, + SQ_SYNC_VC_STALL_PIX = 82, + SQ_CONSTANTS_USED_SIMD2 = 83, + SQ_CONSTANTS_SENT_SP_SIMD2 = 84, + SQ_PERFCOUNT_VTX_DEALLOC_ACK = 85, + SQ_PERFCOUNT_PIX_DEALLOC_ACK = 86, + SQ_ALU0_FIFO_FULL_SIMD0 = 87, + SQ_ALU1_FIFO_FULL_SIMD0 = 88, + SQ_ALU0_FIFO_FULL_SIMD1 = 89, + SQ_ALU1_FIFO_FULL_SIMD1 = 90, + SQ_ALU0_FIFO_FULL_SIMD2 = 91, + SQ_ALU1_FIFO_FULL_SIMD2 = 92, + SQ_ALU0_FIFO_FULL_SIMD3 = 93, + SQ_ALU1_FIFO_FULL_SIMD3 = 94, + VC_PERF_STATIC = 95, + VC_PERF_STALLED = 96, + VC_PERF_STARVED = 97, + VC_PERF_SEND = 98, + VC_PERF_ACTUAL_STARVED = 99, + PIXEL_THREAD_0_ACTIVE = 100, + VERTEX_THREAD_0_ACTIVE = 101, + PIXEL_THREAD_0_NUMBER = 102, + VERTEX_THREAD_0_NUMBER = 103, + VERTEX_EVENT_NUMBER = 104, + PIXEL_EVENT_NUMBER = 105, + PTRBUFF_EF_PUSH = 106, + PTRBUFF_EF_POP_EVENT = 107, + PTRBUFF_EF_POP_NEW_VTX = 108, + PTRBUFF_EF_POP_DEALLOC = 109, + PTRBUFF_EF_POP_PVECTOR = 110, + PTRBUFF_EF_POP_PVECTOR_X = 111, + PTRBUFF_EF_POP_PVECTOR_VNZ = 112, + PTRBUFF_PB_DEALLOC = 113, + PTRBUFF_PI_STATE_PPB_POP = 114, + PTRBUFF_PI_RTR = 115, + PTRBUFF_PI_READ_EN = 116, + PTRBUFF_PI_BUFF_SWAP = 117, + PTRBUFF_SQ_FREE_BUFF = 118, + PTRBUFF_SQ_DEC = 119, + PTRBUFF_SC_VALID_CNTL_EVENT = 120, + PTRBUFF_SC_VALID_IJ_XFER = 121, + PTRBUFF_SC_NEW_VECTOR_1_Q = 122, + PTRBUFF_QUAL_NEW_VECTOR = 123, + PTRBUFF_QUAL_EVENT = 124, + PTRBUFF_END_BUFFER = 125, + PTRBUFF_FILL_QUAD = 126, + VERTS_WRITTEN_SPI = 127, + TP_FETCH_INSTR_EXEC = 128, + TP_FETCH_INSTR_REQ = 129, + TP_DATA_RETURN = 130, + SPI_WRITE_CYCLES_SP = 131, + SPI_WRITES_SP = 132, + SP_ALU_INSTR_EXEC = 133, + SP_CONST_ADDR_TO_SQ = 134, + SP_PRED_KILLS_TO_SQ = 135, + SP_EXPORT_CYCLES_TO_SX = 136, + SP_EXPORTS_TO_SX = 137, + SQ_CYCLES_ELAPSED = 138, + SQ_TCFS_OPT_ALLOC_EXEC = 139, + SQ_TCFS_NO_OPT_ALLOC = 140, + SQ_ALU0_NO_OPT_ALLOC = 141, + SQ_ALU1_NO_OPT_ALLOC = 142, + SQ_TCFS_ARB_XFC_CNT = 143, + SQ_ALU0_ARB_XFC_CNT = 144, + SQ_ALU1_ARB_XFC_CNT = 145, + SQ_TCFS_CFS_UPDATE_CNT = 146, + SQ_ALU0_CFS_UPDATE_CNT = 147, + SQ_ALU1_CFS_UPDATE_CNT = 148, + SQ_VTX_PUSH_THREAD_CNT = 149, + SQ_VTX_POP_THREAD_CNT = 150, + SQ_PIX_PUSH_THREAD_CNT = 151, + SQ_PIX_POP_THREAD_CNT = 152, + SQ_PIX_TOTAL = 153, + SQ_PIX_KILLED = 154, +} SQ_PERFCNT_SELECT; +#endif /*ENUMS_SQ_PERFCNT_SELECT_H*/ + +#ifndef ENUMS_SX_PERFCNT_SELECT_H +#define ENUMS_SX_PERFCNT_SELECT_H +typedef enum SX_PERFCNT_SELECT { + SX_EXPORT_VECTORS = 0, + SX_DUMMY_QUADS = 1, + SX_ALPHA_FAIL = 2, + SX_RB_QUAD_BUSY = 3, + SX_RB_COLOR_BUSY = 4, + SX_RB_QUAD_STALL = 5, + SX_RB_COLOR_STALL = 6, +} SX_PERFCNT_SELECT; +#endif /*ENUMS_SX_PERFCNT_SELECT_H*/ + +#ifndef ENUMS_Abs_modifier_H +#define ENUMS_Abs_modifier_H +typedef enum Abs_modifier { + NO_ABS_MOD = 0, + ABS_MOD = 1 +} Abs_modifier; +#endif /*ENUMS_Abs_modifier_H*/ + +#ifndef ENUMS_Exporting_H +#define ENUMS_Exporting_H +typedef enum Exporting { + NOT_EXPORTING = 0, + EXPORTING = 1 +} Exporting; +#endif /*ENUMS_Exporting_H*/ + +#ifndef ENUMS_ScalarOpcode_H +#define ENUMS_ScalarOpcode_H +typedef enum ScalarOpcode { + ADDs = 0, + ADD_PREVs = 1, + MULs = 2, + MUL_PREVs = 3, + MUL_PREV2s = 4, + MAXs = 5, + MINs = 6, + SETEs = 7, + SETGTs = 8, + SETGTEs = 9, + SETNEs = 10, + FRACs = 11, + TRUNCs = 12, + FLOORs = 13, + EXP_IEEE = 14, + LOG_CLAMP = 15, + LOG_IEEE = 16, + RECIP_CLAMP = 17, + RECIP_FF = 18, + RECIP_IEEE = 19, + RECIPSQ_CLAMP = 20, + RECIPSQ_FF = 21, + RECIPSQ_IEEE = 22, + MOVAs = 23, + MOVA_FLOORs = 24, + SUBs = 25, + SUB_PREVs = 26, + PRED_SETEs = 27, + PRED_SETNEs = 28, + PRED_SETGTs = 29, + PRED_SETGTEs = 30, + PRED_SET_INVs = 31, + PRED_SET_POPs = 32, + PRED_SET_CLRs = 33, + PRED_SET_RESTOREs = 34, + KILLEs = 35, + KILLGTs = 36, + KILLGTEs = 37, + KILLNEs = 38, + KILLONEs = 39, + SQRT_IEEE = 40, + MUL_CONST_0 = 42, + MUL_CONST_1 = 43, + ADD_CONST_0 = 44, + ADD_CONST_1 = 45, + SUB_CONST_0 = 46, + SUB_CONST_1 = 47, + SIN = 48, + COS = 49, + RETAIN_PREV = 50, +} ScalarOpcode; +#endif /*ENUMS_ScalarOpcode_H*/ + +#ifndef ENUMS_SwizzleType_H +#define ENUMS_SwizzleType_H +typedef enum SwizzleType { + NO_SWIZZLE = 0, + SHIFT_RIGHT_1 = 1, + SHIFT_RIGHT_2 = 2, + SHIFT_RIGHT_3 = 3 +} SwizzleType; +#endif /*ENUMS_SwizzleType_H*/ + +#ifndef ENUMS_InputModifier_H +#define ENUMS_InputModifier_H +typedef enum InputModifier { + NIL = 0, + NEGATE = 1 +} InputModifier; +#endif /*ENUMS_InputModifier_H*/ + +#ifndef ENUMS_PredicateSelect_H +#define ENUMS_PredicateSelect_H +typedef enum PredicateSelect { + NO_PREDICATION = 0, + PREDICATE_QUAD = 1, + PREDICATED_2 = 2, + PREDICATED_3 = 3 +} PredicateSelect; +#endif /*ENUMS_PredicateSelect_H*/ + +#ifndef ENUMS_OperandSelect1_H +#define ENUMS_OperandSelect1_H +typedef enum OperandSelect1 { + ABSOLUTE_REG = 0, + RELATIVE_REG = 1 +} OperandSelect1; +#endif /*ENUMS_OperandSelect1_H*/ + +#ifndef ENUMS_VectorOpcode_H +#define ENUMS_VectorOpcode_H +typedef enum VectorOpcode { + ADDv = 0, + MULv = 1, + MAXv = 2, + MINv = 3, + SETEv = 4, + SETGTv = 5, + SETGTEv = 6, + SETNEv = 7, + FRACv = 8, + TRUNCv = 9, + FLOORv = 10, + MULADDv = 11, + CNDEv = 12, + CNDGTEv = 13, + CNDGTv = 14, + DOT4v = 15, + DOT3v = 16, + DOT2ADDv = 17, + CUBEv = 18, + MAX4v = 19, + PRED_SETE_PUSHv = 20, + PRED_SETNE_PUSHv = 21, + PRED_SETGT_PUSHv = 22, + PRED_SETGTE_PUSHv = 23, + KILLEv = 24, + KILLGTv = 25, + KILLGTEv = 26, + KILLNEv = 27, + DSTv = 28, + MOVAv = 29, +} VectorOpcode; +#endif /*ENUMS_VectorOpcode_H*/ + +#ifndef ENUMS_OperandSelect0_H +#define ENUMS_OperandSelect0_H +typedef enum OperandSelect0 { + CONSTANT = 0, + NON_CONSTANT = 1 +} OperandSelect0; +#endif /*ENUMS_OperandSelect0_H*/ + +#ifndef ENUMS_Ressource_type_H +#define ENUMS_Ressource_type_H +typedef enum Ressource_type { + ALU = 0, + TEXTURE = 1 +} Ressource_type; +#endif /*ENUMS_Ressource_type_H*/ + +#ifndef ENUMS_Instruction_serial_H +#define ENUMS_Instruction_serial_H +typedef enum Instruction_serial { + NOT_SERIAL = 0, + SERIAL = 1 +} Instruction_serial; +#endif /*ENUMS_Instruction_serial_H*/ + +#ifndef ENUMS_VC_type_H +#define ENUMS_VC_type_H +typedef enum VC_type { + ALU_TP_REQUEST = 0, + VC_REQUEST = 1 +} VC_type; +#endif /*ENUMS_VC_type_H*/ + +#ifndef ENUMS_Addressing_H +#define ENUMS_Addressing_H +typedef enum Addressing { + RELATIVE_ADDR = 0, + ABSOLUTE_ADDR = 1 +} Addressing; +#endif /*ENUMS_Addressing_H*/ + +#ifndef ENUMS_CFOpcode_H +#define ENUMS_CFOpcode_H +typedef enum CFOpcode { + NOP = 0, + EXECUTE = 1, + EXECUTE_END = 2, + COND_EXECUTE = 3, + COND_EXECUTE_END = 4, + COND_PRED_EXECUTE = 5, + COND_PRED_EXECUTE_END = 6, + LOOP_START = 7, + LOOP_END = 8, + COND_CALL = 9, + RETURN = 10, + COND_JMP = 11, + ALLOCATE = 12, + COND_EXECUTE_PRED_CLEAN = 13, + COND_EXECUTE_PRED_CLEAN_END = 14, + MARK_VS_FETCH_DONE = 15 +} CFOpcode; +#endif /*ENUMS_CFOpcode_H*/ + +#ifndef ENUMS_Allocation_type_H +#define ENUMS_Allocation_type_H +typedef enum Allocation_type { + SQ_NO_ALLOC = 0, + SQ_POSITION = 1, + SQ_PARAMETER_PIXEL = 2, + SQ_MEMORY = 3 +} Allocation_type; +#endif /*ENUMS_Allocation_type_H*/ + +#ifndef ENUMS_TexInstOpcode_H +#define ENUMS_TexInstOpcode_H +typedef enum TexInstOpcode { + TEX_INST_FETCH = 1, + TEX_INST_RESERVED_1 = 2, + TEX_INST_RESERVED_2 = 3, + TEX_INST_RESERVED_3 = 4, + TEX_INST_GET_BORDER_COLOR_FRAC = 16, + TEX_INST_GET_COMP_TEX_LOD = 17, + TEX_INST_GET_GRADIENTS = 18, + TEX_INST_GET_WEIGHTS = 19, + TEX_INST_SET_TEX_LOD = 24, + TEX_INST_SET_GRADIENTS_H = 25, + TEX_INST_SET_GRADIENTS_V = 26, + TEX_INST_RESERVED_4 = 27, +} TexInstOpcode; +#endif /*ENUMS_TexInstOpcode_H*/ + +#ifndef ENUMS_Addressmode_H +#define ENUMS_Addressmode_H +typedef enum Addressmode { + LOGICAL = 0, + LOOP_RELATIVE = 1 +} Addressmode; +#endif /*ENUMS_Addressmode_H*/ + +#ifndef ENUMS_TexCoordDenorm_H +#define ENUMS_TexCoordDenorm_H +typedef enum TexCoordDenorm { + TEX_COORD_NORMALIZED = 0, + TEX_COORD_UNNORMALIZED = 1 +} TexCoordDenorm; +#endif /*ENUMS_TexCoordDenorm_H*/ + +#ifndef ENUMS_SrcSel_H +#define ENUMS_SrcSel_H +typedef enum SrcSel { + SRC_SEL_X = 0, + SRC_SEL_Y = 1, + SRC_SEL_Z = 2, + SRC_SEL_W = 3 +} SrcSel; +#endif /*ENUMS_SrcSel_H*/ + +#ifndef ENUMS_DstSel_H +#define ENUMS_DstSel_H +typedef enum DstSel { + DST_SEL_X = 0, + DST_SEL_Y = 1, + DST_SEL_Z = 2, + DST_SEL_W = 3, + DST_SEL_0 = 4, + DST_SEL_1 = 5, + DST_SEL_RSVD = 6, + DST_SEL_MASK = 7 +} DstSel; +#endif /*ENUMS_DstSel_H*/ + +#ifndef ENUMS_MagFilter_H +#define ENUMS_MagFilter_H +typedef enum MagFilter { + MAG_FILTER_POINT = 0, + MAG_FILTER_LINEAR = 1, + MAG_FILTER_RESERVED_0 = 2, + MAG_FILTER_USE_FETCH_CONST = 3 +} MagFilter; +#endif /*ENUMS_MagFilter_H*/ + +#ifndef ENUMS_MinFilter_H +#define ENUMS_MinFilter_H +typedef enum MinFilter { + MIN_FILTER_POINT = 0, + MIN_FILTER_LINEAR = 1, + MIN_FILTER_RESERVED_0 = 2, + MIN_FILTER_USE_FETCH_CONST = 3 +} MinFilter; +#endif /*ENUMS_MinFilter_H*/ + +#ifndef ENUMS_MipFilter_H +#define ENUMS_MipFilter_H +typedef enum MipFilter { + MIP_FILTER_POINT = 0, + MIP_FILTER_LINEAR = 1, + MIP_FILTER_BASEMAP = 2, + MIP_FILTER_USE_FETCH_CONST = 3 +} MipFilter; +#endif /*ENUMS_MipFilter_H*/ + +#ifndef ENUMS_AnisoFilter_H +#define ENUMS_AnisoFilter_H +typedef enum AnisoFilter { + ANISO_FILTER_DISABLED = 0, + ANISO_FILTER_MAX_1_1 = 1, + ANISO_FILTER_MAX_2_1 = 2, + ANISO_FILTER_MAX_4_1 = 3, + ANISO_FILTER_MAX_8_1 = 4, + ANISO_FILTER_MAX_16_1 = 5, + ANISO_FILTER_USE_FETCH_CONST = 7 +} AnisoFilter; +#endif /*ENUMS_AnisoFilter_H*/ + +#ifndef ENUMS_ArbitraryFilter_H +#define ENUMS_ArbitraryFilter_H +typedef enum ArbitraryFilter { + ARBITRARY_FILTER_2X4_SYM = 0, + ARBITRARY_FILTER_2X4_ASYM = 1, + ARBITRARY_FILTER_4X2_SYM = 2, + ARBITRARY_FILTER_4X2_ASYM = 3, + ARBITRARY_FILTER_4X4_SYM = 4, + ARBITRARY_FILTER_4X4_ASYM = 5, + ARBITRARY_FILTER_USE_FETCH_CONST = 7 +} ArbitraryFilter; +#endif /*ENUMS_ArbitraryFilter_H*/ + +#ifndef ENUMS_VolMagFilter_H +#define ENUMS_VolMagFilter_H +typedef enum VolMagFilter { + VOL_MAG_FILTER_POINT = 0, + VOL_MAG_FILTER_LINEAR = 1, + VOL_MAG_FILTER_USE_FETCH_CONST = 3 +} VolMagFilter; +#endif /*ENUMS_VolMagFilter_H*/ + +#ifndef ENUMS_VolMinFilter_H +#define ENUMS_VolMinFilter_H +typedef enum VolMinFilter { + VOL_MIN_FILTER_POINT = 0, + VOL_MIN_FILTER_LINEAR = 1, + VOL_MIN_FILTER_USE_FETCH_CONST = 3 +} VolMinFilter; +#endif /*ENUMS_VolMinFilter_H*/ + +#ifndef ENUMS_PredSelect_H +#define ENUMS_PredSelect_H +typedef enum PredSelect { + NOT_PREDICATED = 0, + PREDICATED = 1 +} PredSelect; +#endif /*ENUMS_PredSelect_H*/ + +#ifndef ENUMS_SampleLocation_H +#define ENUMS_SampleLocation_H +typedef enum SampleLocation { + SAMPLE_CENTROID = 0, + SAMPLE_CENTER = 1 +} SampleLocation; +#endif /*ENUMS_SampleLocation_H*/ + +#ifndef ENUMS_VertexMode_H +#define ENUMS_VertexMode_H +typedef enum VertexMode { + POSITION_1_VECTOR = 0, + POSITION_2_VECTORS_UNUSED = 1, + POSITION_2_VECTORS_SPRITE = 2, + POSITION_2_VECTORS_EDGE = 3, + POSITION_2_VECTORS_KILL = 4, + POSITION_2_VECTORS_SPRITE_KILL = 5, + POSITION_2_VECTORS_EDGE_KILL = 6, + MULTIPASS = 7 +} VertexMode; +#endif /*ENUMS_VertexMode_H*/ + +#ifndef ENUMS_Sample_Cntl_H +#define ENUMS_Sample_Cntl_H +typedef enum Sample_Cntl { + CENTROIDS_ONLY = 0, + CENTERS_ONLY = 1, + CENTROIDS_AND_CENTERS = 2, + UNDEF = 3 +} Sample_Cntl; +#endif /*ENUMS_Sample_Cntl_H*/ + +/******************************************************* + * SX Enums + *******************************************************/ +/******************************************************* + * MH Enums + *******************************************************/ +#ifndef ENUMS_MhPerfEncode_H +#define ENUMS_MhPerfEncode_H +typedef enum MhPerfEncode { + CP_R0_REQUESTS = 0, + CP_R1_REQUESTS = 1, + CP_R2_REQUESTS = 2, + CP_R3_REQUESTS = 3, + CP_R4_REQUESTS = 4, + CP_TOTAL_READ_REQUESTS = 5, + CP_TOTAL_WRITE_REQUESTS = 6, + CP_TOTAL_REQUESTS = 7, + CP_DATA_BYTES_WRITTEN = 8, + CP_WRITE_CLEAN_RESPONSES = 9, + CP_R0_READ_BURSTS_RECEIVED = 10, + CP_R1_READ_BURSTS_RECEIVED = 11, + CP_R2_READ_BURSTS_RECEIVED = 12, + CP_R3_READ_BURSTS_RECEIVED = 13, + CP_R4_READ_BURSTS_RECEIVED = 14, + CP_TOTAL_READ_BURSTS_RECEIVED = 15, + CP_R0_DATA_BEATS_READ = 16, + CP_R1_DATA_BEATS_READ = 17, + CP_R2_DATA_BEATS_READ = 18, + CP_R3_DATA_BEATS_READ = 19, + CP_R4_DATA_BEATS_READ = 20, + CP_TOTAL_DATA_BEATS_READ = 21, + VGT_R0_REQUESTS = 22, + VGT_R1_REQUESTS = 23, + VGT_TOTAL_REQUESTS = 24, + VGT_R0_READ_BURSTS_RECEIVED = 25, + VGT_R1_READ_BURSTS_RECEIVED = 26, + VGT_TOTAL_READ_BURSTS_RECEIVED = 27, + VGT_R0_DATA_BEATS_READ = 28, + VGT_R1_DATA_BEATS_READ = 29, + VGT_TOTAL_DATA_BEATS_READ = 30, + TC_TOTAL_REQUESTS = 31, + TC_ROQ_REQUESTS = 32, + TC_INFO_SENT = 33, + TC_READ_BURSTS_RECEIVED = 34, + TC_DATA_BEATS_READ = 35, + TCD_BURSTS_READ = 36, + RB_REQUESTS = 37, + RB_DATA_BYTES_WRITTEN = 38, + RB_WRITE_CLEAN_RESPONSES = 39, + AXI_READ_REQUESTS_ID_0 = 40, + AXI_READ_REQUESTS_ID_1 = 41, + AXI_READ_REQUESTS_ID_2 = 42, + AXI_READ_REQUESTS_ID_3 = 43, + AXI_READ_REQUESTS_ID_4 = 44, + AXI_READ_REQUESTS_ID_5 = 45, + AXI_READ_REQUESTS_ID_6 = 46, + AXI_READ_REQUESTS_ID_7 = 47, + AXI_TOTAL_READ_REQUESTS = 48, + AXI_WRITE_REQUESTS_ID_0 = 49, + AXI_WRITE_REQUESTS_ID_1 = 50, + AXI_WRITE_REQUESTS_ID_2 = 51, + AXI_WRITE_REQUESTS_ID_3 = 52, + AXI_WRITE_REQUESTS_ID_4 = 53, + AXI_WRITE_REQUESTS_ID_5 = 54, + AXI_WRITE_REQUESTS_ID_6 = 55, + AXI_WRITE_REQUESTS_ID_7 = 56, + AXI_TOTAL_WRITE_REQUESTS = 57, + AXI_TOTAL_REQUESTS_ID_0 = 58, + AXI_TOTAL_REQUESTS_ID_1 = 59, + AXI_TOTAL_REQUESTS_ID_2 = 60, + AXI_TOTAL_REQUESTS_ID_3 = 61, + AXI_TOTAL_REQUESTS_ID_4 = 62, + AXI_TOTAL_REQUESTS_ID_5 = 63, + AXI_TOTAL_REQUESTS_ID_6 = 64, + AXI_TOTAL_REQUESTS_ID_7 = 65, + AXI_TOTAL_REQUESTS = 66, + AXI_READ_CHANNEL_BURSTS_ID_0 = 67, + AXI_READ_CHANNEL_BURSTS_ID_1 = 68, + AXI_READ_CHANNEL_BURSTS_ID_2 = 69, + AXI_READ_CHANNEL_BURSTS_ID_3 = 70, + AXI_READ_CHANNEL_BURSTS_ID_4 = 71, + AXI_READ_CHANNEL_BURSTS_ID_5 = 72, + AXI_READ_CHANNEL_BURSTS_ID_6 = 73, + AXI_READ_CHANNEL_BURSTS_ID_7 = 74, + AXI_READ_CHANNEL_TOTAL_BURSTS = 75, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0 = 76, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1 = 77, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2 = 78, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3 = 79, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4 = 80, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5 = 81, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6 = 82, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7 = 83, + AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ = 84, + AXI_WRITE_CHANNEL_BURSTS_ID_0 = 85, + AXI_WRITE_CHANNEL_BURSTS_ID_1 = 86, + AXI_WRITE_CHANNEL_BURSTS_ID_2 = 87, + AXI_WRITE_CHANNEL_BURSTS_ID_3 = 88, + AXI_WRITE_CHANNEL_BURSTS_ID_4 = 89, + AXI_WRITE_CHANNEL_BURSTS_ID_5 = 90, + AXI_WRITE_CHANNEL_BURSTS_ID_6 = 91, + AXI_WRITE_CHANNEL_BURSTS_ID_7 = 92, + AXI_WRITE_CHANNEL_TOTAL_BURSTS = 93, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0 = 94, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1 = 95, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2 = 96, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3 = 97, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4 = 98, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5 = 99, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6 = 100, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7 = 101, + AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN = 102, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0 = 103, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1 = 104, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2 = 105, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3 = 106, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4 = 107, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5 = 108, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6 = 109, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7 = 110, + AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES = 111, + TOTAL_MMU_MISSES = 112, + MMU_READ_MISSES = 113, + MMU_WRITE_MISSES = 114, + TOTAL_MMU_HITS = 115, + MMU_READ_HITS = 116, + MMU_WRITE_HITS = 117, + SPLIT_MODE_TC_HITS = 118, + SPLIT_MODE_TC_MISSES = 119, + SPLIT_MODE_NON_TC_HITS = 120, + SPLIT_MODE_NON_TC_MISSES = 121, + STALL_AWAITING_TLB_MISS_FETCH = 122, + MMU_TLB_MISS_READ_BURSTS_RECEIVED = 123, + MMU_TLB_MISS_DATA_BEATS_READ = 124, + CP_CYCLES_HELD_OFF = 125, + VGT_CYCLES_HELD_OFF = 126, + TC_CYCLES_HELD_OFF = 127, + TC_ROQ_CYCLES_HELD_OFF = 128, + TC_CYCLES_HELD_OFF_TCD_FULL = 129, + RB_CYCLES_HELD_OFF = 130, + TOTAL_CYCLES_ANY_CLNT_HELD_OFF = 131, + TLB_MISS_CYCLES_HELD_OFF = 132, + AXI_READ_REQUEST_HELD_OFF = 133, + AXI_WRITE_REQUEST_HELD_OFF = 134, + AXI_REQUEST_HELD_OFF = 135, + AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT = 136, + AXI_WRITE_DATA_HELD_OFF = 137, + CP_SAME_PAGE_BANK_REQUESTS = 138, + VGT_SAME_PAGE_BANK_REQUESTS = 139, + TC_SAME_PAGE_BANK_REQUESTS = 140, + TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS = 141, + RB_SAME_PAGE_BANK_REQUESTS = 142, + TOTAL_SAME_PAGE_BANK_REQUESTS = 143, + CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 144, + VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 145, + TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 146, + RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 147, + TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT = 148, + TOTAL_MH_READ_REQUESTS = 149, + TOTAL_MH_WRITE_REQUESTS = 150, + TOTAL_MH_REQUESTS = 151, + MH_BUSY = 152, + CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 153, + VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 154, + TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 155, + RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 156, + TC_ROQ_N_VALID_ENTRIES = 157, + ARQ_N_ENTRIES = 158, + WDB_N_ENTRIES = 159, + MH_READ_LATENCY_OUTST_REQ_SUM = 160, + MC_READ_LATENCY_OUTST_REQ_SUM = 161, + MC_TOTAL_READ_REQUESTS = 162, + ELAPSED_CYCLES_MH_GATED_CLK = 163, + ELAPSED_CLK_CYCLES = 164, + CP_W_16B_REQUESTS = 165, + CP_W_32B_REQUESTS = 166, + TC_16B_REQUESTS = 167, + TC_32B_REQUESTS = 168, + PA_REQUESTS = 169, + PA_DATA_BYTES_WRITTEN = 170, + PA_WRITE_CLEAN_RESPONSES = 171, + PA_CYCLES_HELD_OFF = 172, + AXI_READ_REQUEST_DATA_BEATS_ID_0 = 173, + AXI_READ_REQUEST_DATA_BEATS_ID_1 = 174, + AXI_READ_REQUEST_DATA_BEATS_ID_2 = 175, + AXI_READ_REQUEST_DATA_BEATS_ID_3 = 176, + AXI_READ_REQUEST_DATA_BEATS_ID_4 = 177, + AXI_READ_REQUEST_DATA_BEATS_ID_5 = 178, + AXI_READ_REQUEST_DATA_BEATS_ID_6 = 179, + AXI_READ_REQUEST_DATA_BEATS_ID_7 = 180, + AXI_TOTAL_READ_REQUEST_DATA_BEATS = 181, +} MhPerfEncode; +#endif /*ENUMS_MhPerfEncode_H*/ + +#ifndef ENUMS_MmuClntBeh_H +#define ENUMS_MmuClntBeh_H +typedef enum MmuClntBeh { + BEH_NEVR = 0, + BEH_TRAN_RNG = 1, + BEH_TRAN_FLT = 2, +} MmuClntBeh; +#endif /*ENUMS_MmuClntBeh_H*/ + +/******************************************************* + * RBBM Enums + *******************************************************/ +#ifndef ENUMS_RBBM_PERFCOUNT1_SEL_H +#define ENUMS_RBBM_PERFCOUNT1_SEL_H +typedef enum RBBM_PERFCOUNT1_SEL { + RBBM1_COUNT = 0, + RBBM1_NRT_BUSY = 1, + RBBM1_RB_BUSY = 2, + RBBM1_SQ_CNTX0_BUSY = 3, + RBBM1_SQ_CNTX17_BUSY = 4, + RBBM1_VGT_BUSY = 5, + RBBM1_VGT_NODMA_BUSY = 6, + RBBM1_PA_BUSY = 7, + RBBM1_SC_CNTX_BUSY = 8, + RBBM1_TPC_BUSY = 9, + RBBM1_TC_BUSY = 10, + RBBM1_SX_BUSY = 11, + RBBM1_CP_COHER_BUSY = 12, + RBBM1_CP_NRT_BUSY = 13, + RBBM1_GFX_IDLE_STALL = 14, + RBBM1_INTERRUPT = 15, +} RBBM_PERFCOUNT1_SEL; +#endif /*ENUMS_RBBM_PERFCOUNT1_SEL_H*/ + +/******************************************************* + * CP Enums + *******************************************************/ +#ifndef ENUMS_CP_PERFCOUNT_SEL_H +#define ENUMS_CP_PERFCOUNT_SEL_H +typedef enum CP_PERFCOUNT_SEL { + ALWAYS_COUNT = 0, + TRANS_FIFO_FULL = 1, + TRANS_FIFO_AF = 2, + RCIU_PFPTRANS_WAIT = 3, + Reserved_04 = 4, + Reserved_05 = 5, + RCIU_NRTTRANS_WAIT = 6, + Reserved_07 = 7, + CSF_NRT_READ_WAIT = 8, + CSF_I1_FIFO_FULL = 9, + CSF_I2_FIFO_FULL = 10, + CSF_ST_FIFO_FULL = 11, + Reserved_12 = 12, + CSF_RING_ROQ_FULL = 13, + CSF_I1_ROQ_FULL = 14, + CSF_I2_ROQ_FULL = 15, + CSF_ST_ROQ_FULL = 16, + Reserved_17 = 17, + MIU_TAG_MEM_FULL = 18, + MIU_WRITECLEAN = 19, + Reserved_20 = 20, + Reserved_21 = 21, + MIU_NRT_WRITE_STALLED = 22, + MIU_NRT_READ_STALLED = 23, + ME_WRITE_CONFIRM_FIFO_FULL = 24, + ME_VS_DEALLOC_FIFO_FULL = 25, + ME_PS_DEALLOC_FIFO_FULL = 26, + ME_REGS_VS_EVENT_FIFO_FULL = 27, + ME_REGS_PS_EVENT_FIFO_FULL = 28, + ME_REGS_CF_EVENT_FIFO_FULL = 29, + ME_MICRO_RB_STARVED = 30, + ME_MICRO_I1_STARVED = 31, + ME_MICRO_I2_STARVED = 32, + ME_MICRO_ST_STARVED = 33, + Reserved_34 = 34, + Reserved_35 = 35, + Reserved_36 = 36, + Reserved_37 = 37, + Reserved_38 = 38, + Reserved_39 = 39, + RCIU_RBBM_DWORD_SENT = 40, + ME_BUSY_CLOCKS = 41, + ME_WAIT_CONTEXT_AVAIL = 42, + PFP_TYPE0_PACKET = 43, + PFP_TYPE3_PACKET = 44, + CSF_RB_WPTR_NEQ_RPTR = 45, + CSF_I1_SIZE_NEQ_ZERO = 46, + CSF_I2_SIZE_NEQ_ZERO = 47, + CSF_RBI1I2_FETCHING = 48, + Reserved_49 = 49, + Reserved_50 = 50, + Reserved_51 = 51, + Reserved_52 = 52, + Reserved_53 = 53, + Reserved_54 = 54, + Reserved_55 = 55, + Reserved_56 = 56, + Reserved_57 = 57, + Reserved_58 = 58, + Reserved_59 = 59, + Reserved_60 = 60, + Reserved_61 = 61, + Reserved_62 = 62, + Reserved_63 = 63 +} CP_PERFCOUNT_SEL; +#endif /*ENUMS_CP_PERFCOUNT_SEL_H*/ + +/******************************************************* + * SC Enums + *******************************************************/ +/******************************************************* + * BC Enums + *******************************************************/ +#ifndef ENUMS_ColorformatX_H +#define ENUMS_ColorformatX_H +typedef enum ColorformatX { + COLORX_4_4_4_4 = 0, + COLORX_1_5_5_5 = 1, + COLORX_5_6_5 = 2, + COLORX_8 = 3, + COLORX_8_8 = 4, + COLORX_8_8_8_8 = 5, + COLORX_S8_8_8_8 = 6, + COLORX_16_FLOAT = 7, + COLORX_16_16_FLOAT = 8, + COLORX_16_16_16_16_FLOAT = 9, + COLORX_32_FLOAT = 10, + COLORX_32_32_FLOAT = 11, + COLORX_32_32_32_32_FLOAT = 12, + COLORX_2_3_3 = 13, + COLORX_8_8_8 = 14, +} ColorformatX; +#endif /*ENUMS_ColorformatX_H*/ + +#ifndef ENUMS_DepthformatX_H +#define ENUMS_DepthformatX_H +typedef enum DepthformatX { + DEPTHX_16 = 0, + DEPTHX_24_8 = 1 +} DepthformatX; +#endif /*ENUMS_DepthformatX_H*/ + +#ifndef ENUMS_CompareFrag_H +#define ENUMS_CompareFrag_H +typedef enum CompareFrag { + FRAG_NEVER = 0, + FRAG_LESS = 1, + FRAG_EQUAL = 2, + FRAG_LEQUAL = 3, + FRAG_GREATER = 4, + FRAG_NOTEQUAL = 5, + FRAG_GEQUAL = 6, + FRAG_ALWAYS = 7 +} CompareFrag; +#endif /*ENUMS_CompareFrag_H*/ + +#ifndef ENUMS_CompareRef_H +#define ENUMS_CompareRef_H +typedef enum CompareRef { + REF_NEVER = 0, + REF_LESS = 1, + REF_EQUAL = 2, + REF_LEQUAL = 3, + REF_GREATER = 4, + REF_NOTEQUAL = 5, + REF_GEQUAL = 6, + REF_ALWAYS = 7 +} CompareRef; +#endif /*ENUMS_CompareRef_H*/ + +#ifndef ENUMS_StencilOp_H +#define ENUMS_StencilOp_H +typedef enum StencilOp { + STENCIL_KEEP = 0, + STENCIL_ZERO = 1, + STENCIL_REPLACE = 2, + STENCIL_INCR_CLAMP = 3, + STENCIL_DECR_CLAMP = 4, + STENCIL_INVERT = 5, + STENCIL_INCR_WRAP = 6, + STENCIL_DECR_WRAP = 7 +} StencilOp; +#endif /*ENUMS_StencilOp_H*/ + +#ifndef ENUMS_BlendOpX_H +#define ENUMS_BlendOpX_H +typedef enum BlendOpX { + BLENDX_ZERO = 0, + BLENDX_ONE = 1, + BLENDX_SRC_COLOR = 4, + BLENDX_ONE_MINUS_SRC_COLOR = 5, + BLENDX_SRC_ALPHA = 6, + BLENDX_ONE_MINUS_SRC_ALPHA = 7, + BLENDX_DST_COLOR = 8, + BLENDX_ONE_MINUS_DST_COLOR = 9, + BLENDX_DST_ALPHA = 10, + BLENDX_ONE_MINUS_DST_ALPHA = 11, + BLENDX_CONSTANT_COLOR = 12, + BLENDX_ONE_MINUS_CONSTANT_COLOR = 13, + BLENDX_CONSTANT_ALPHA = 14, + BLENDX_ONE_MINUS_CONSTANT_ALPHA = 15, + BLENDX_SRC_ALPHA_SATURATE = 16, +} BlendOpX; +#endif /*ENUMS_BlendOpX_H*/ + +#ifndef ENUMS_CombFuncX_H +#define ENUMS_CombFuncX_H +typedef enum CombFuncX { + COMB_DST_PLUS_SRC = 0, + COMB_SRC_MINUS_DST = 1, + COMB_MIN_DST_SRC = 2, + COMB_MAX_DST_SRC = 3, + COMB_DST_MINUS_SRC = 4, + COMB_DST_PLUS_SRC_BIAS = 5, +} CombFuncX; +#endif /*ENUMS_CombFuncX_H*/ + +#ifndef ENUMS_DitherModeX_H +#define ENUMS_DitherModeX_H +typedef enum DitherModeX { + DITHER_DISABLE = 0, + DITHER_ALWAYS = 1, + DITHER_IF_ALPHA_OFF = 2, +} DitherModeX; +#endif /*ENUMS_DitherModeX_H*/ + +#ifndef ENUMS_DitherTypeX_H +#define ENUMS_DitherTypeX_H +typedef enum DitherTypeX { + DITHER_PIXEL = 0, + DITHER_SUBPIXEL = 1, +} DitherTypeX; +#endif /*ENUMS_DitherTypeX_H*/ + +#ifndef ENUMS_EdramMode_H +#define ENUMS_EdramMode_H +typedef enum EdramMode { + EDRAM_NOP = 0, + COLOR_DEPTH = 4, + DEPTH_ONLY = 5, + EDRAM_COPY = 6, +} EdramMode; +#endif /*ENUMS_EdramMode_H*/ + +#ifndef ENUMS_SurfaceEndian_H +#define ENUMS_SurfaceEndian_H +typedef enum SurfaceEndian { + ENDIAN_NONE = 0, + ENDIAN_8IN16 = 1, + ENDIAN_8IN32 = 2, + ENDIAN_16IN32 = 3, + ENDIAN_8IN64 = 4, + ENDIAN_8IN128 = 5, +} SurfaceEndian; +#endif /*ENUMS_SurfaceEndian_H*/ + +#ifndef ENUMS_EdramSizeX_H +#define ENUMS_EdramSizeX_H +typedef enum EdramSizeX { + EDRAMSIZE_16KB = 0, + EDRAMSIZE_32KB = 1, + EDRAMSIZE_64KB = 2, + EDRAMSIZE_128KB = 3, + EDRAMSIZE_256KB = 4, + EDRAMSIZE_512KB = 5, + EDRAMSIZE_1MB = 6, + EDRAMSIZE_2MB = 7, + EDRAMSIZE_4MB = 8, + EDRAMSIZE_8MB = 9, + EDRAMSIZE_16MB = 10, +} EdramSizeX; +#endif /*ENUMS_EdramSizeX_H*/ + +#ifndef ENUMS_RB_PERFCNT_SELECT_H +#define ENUMS_RB_PERFCNT_SELECT_H +typedef enum RB_PERFCNT_SELECT { + RBPERF_CNTX_BUSY = 0, + RBPERF_CNTX_BUSY_MAX = 1, + RBPERF_SX_QUAD_STARVED = 2, + RBPERF_SX_QUAD_STARVED_MAX = 3, + RBPERF_GA_GC_CH0_SYS_REQ = 4, + RBPERF_GA_GC_CH0_SYS_REQ_MAX = 5, + RBPERF_GA_GC_CH1_SYS_REQ = 6, + RBPERF_GA_GC_CH1_SYS_REQ_MAX = 7, + RBPERF_MH_STARVED = 8, + RBPERF_MH_STARVED_MAX = 9, + RBPERF_AZ_BC_COLOR_BUSY = 10, + RBPERF_AZ_BC_COLOR_BUSY_MAX = 11, + RBPERF_AZ_BC_Z_BUSY = 12, + RBPERF_AZ_BC_Z_BUSY_MAX = 13, + RBPERF_RB_SC_TILE_RTR_N = 14, + RBPERF_RB_SC_TILE_RTR_N_MAX = 15, + RBPERF_RB_SC_SAMP_RTR_N = 16, + RBPERF_RB_SC_SAMP_RTR_N_MAX = 17, + RBPERF_RB_SX_QUAD_RTR_N = 18, + RBPERF_RB_SX_QUAD_RTR_N_MAX = 19, + RBPERF_RB_SX_COLOR_RTR_N = 20, + RBPERF_RB_SX_COLOR_RTR_N_MAX = 21, + RBPERF_RB_SC_SAMP_LZ_BUSY = 22, + RBPERF_RB_SC_SAMP_LZ_BUSY_MAX = 23, + RBPERF_ZXP_STALL = 24, + RBPERF_ZXP_STALL_MAX = 25, + RBPERF_EVENT_PENDING = 26, + RBPERF_EVENT_PENDING_MAX = 27, + RBPERF_RB_MH_VALID = 28, + RBPERF_RB_MH_VALID_MAX = 29, + RBPERF_SX_RB_QUAD_SEND = 30, + RBPERF_SX_RB_COLOR_SEND = 31, + RBPERF_SC_RB_TILE_SEND = 32, + RBPERF_SC_RB_SAMPLE_SEND = 33, + RBPERF_SX_RB_MEM_EXPORT = 34, + RBPERF_SX_RB_QUAD_EVENT = 35, + RBPERF_SC_RB_TILE_EVENT_FILTERED = 36, + RBPERF_SC_RB_TILE_EVENT_ALL = 37, + RBPERF_RB_SC_EZ_SEND = 38, + RBPERF_RB_SX_INDEX_SEND = 39, + RBPERF_GMEM_INTFO_RD = 40, + RBPERF_GMEM_INTF1_RD = 41, + RBPERF_GMEM_INTFO_WR = 42, + RBPERF_GMEM_INTF1_WR = 43, + RBPERF_RB_CP_CONTEXT_DONE = 44, + RBPERF_RB_CP_CACHE_FLUSH = 45, + RBPERF_ZPASS_DONE = 46, + RBPERF_ZCMD_VALID = 47, + RBPERF_CCMD_VALID = 48, + RBPERF_ACCUM_GRANT = 49, + RBPERF_ACCUM_C0_GRANT = 50, + RBPERF_ACCUM_C1_GRANT = 51, + RBPERF_ACCUM_FULL_BE_WR = 52, + RBPERF_ACCUM_REQUEST_NO_GRANT = 53, + RBPERF_ACCUM_TIMEOUT_PULSE = 54, + RBPERF_ACCUM_LIN_TIMEOUT_PULSE = 55, + RBPERF_ACCUM_CAM_HIT_FLUSHING = 56, +} RB_PERFCNT_SELECT; +#endif /*ENUMS_RB_PERFCNT_SELECT_H*/ + +#ifndef ENUMS_DepthFormat_H +#define ENUMS_DepthFormat_H +typedef enum DepthFormat { + DEPTH_24_8 = 22, + DEPTH_24_8_FLOAT = 23, + DEPTH_16 = 24, +} DepthFormat; +#endif /*ENUMS_DepthFormat_H*/ + +#ifndef ENUMS_SurfaceSwap_H +#define ENUMS_SurfaceSwap_H +typedef enum SurfaceSwap { + SWAP_LOWRED = 0, + SWAP_LOWBLUE = 1 +} SurfaceSwap; +#endif /*ENUMS_SurfaceSwap_H*/ + +#ifndef ENUMS_DepthArray_H +#define ENUMS_DepthArray_H +typedef enum DepthArray { + ARRAY_2D_ALT_DEPTH = 0, + ARRAY_2D_DEPTH = 1, +} DepthArray; +#endif /*ENUMS_DepthArray_H*/ + +#ifndef ENUMS_ColorArray_H +#define ENUMS_ColorArray_H +typedef enum ColorArray { + ARRAY_2D_ALT_COLOR = 0, + ARRAY_2D_COLOR = 1, + ARRAY_3D_SLICE_COLOR = 3 +} ColorArray; +#endif /*ENUMS_ColorArray_H*/ + +#ifndef ENUMS_ColorFormat_H +#define ENUMS_ColorFormat_H +typedef enum ColorFormat { + COLOR_8 = 2, + COLOR_1_5_5_5 = 3, + COLOR_5_6_5 = 4, + COLOR_6_5_5 = 5, + COLOR_8_8_8_8 = 6, + COLOR_2_10_10_10 = 7, + COLOR_8_A = 8, + COLOR_8_B = 9, + COLOR_8_8 = 10, + COLOR_8_8_8 = 11, + COLOR_8_8_8_8_A = 14, + COLOR_4_4_4_4 = 15, + COLOR_10_11_11 = 16, + COLOR_11_11_10 = 17, + COLOR_16 = 24, + COLOR_16_16 = 25, + COLOR_16_16_16_16 = 26, + COLOR_16_FLOAT = 30, + COLOR_16_16_FLOAT = 31, + COLOR_16_16_16_16_FLOAT = 32, + COLOR_32_FLOAT = 36, + COLOR_32_32_FLOAT = 37, + COLOR_32_32_32_32_FLOAT = 38, + COLOR_2_3_3 = 39, +} ColorFormat; +#endif /*ENUMS_ColorFormat_H*/ + +#ifndef ENUMS_SurfaceNumber_H +#define ENUMS_SurfaceNumber_H +typedef enum SurfaceNumber { + NUMBER_UREPEAT = 0, + NUMBER_SREPEAT = 1, + NUMBER_UINTEGER = 2, + NUMBER_SINTEGER = 3, + NUMBER_GAMMA = 4, + NUMBER_FIXED = 5, + NUMBER_FLOAT = 7 +} SurfaceNumber; +#endif /*ENUMS_SurfaceNumber_H*/ + +#ifndef ENUMS_SurfaceFormat_H +#define ENUMS_SurfaceFormat_H +typedef enum SurfaceFormat { + FMT_1_REVERSE = 0, + FMT_1 = 1, + FMT_8 = 2, + FMT_1_5_5_5 = 3, + FMT_5_6_5 = 4, + FMT_6_5_5 = 5, + FMT_8_8_8_8 = 6, + FMT_2_10_10_10 = 7, + FMT_8_A = 8, + FMT_8_B = 9, + FMT_8_8 = 10, + FMT_Cr_Y1_Cb_Y0 = 11, + FMT_Y1_Cr_Y0_Cb = 12, + FMT_5_5_5_1 = 13, + FMT_8_8_8_8_A = 14, + FMT_4_4_4_4 = 15, + FMT_8_8_8 = 16, + FMT_DXT1 = 18, + FMT_DXT2_3 = 19, + FMT_DXT4_5 = 20, + FMT_10_10_10_2 = 21, + FMT_24_8 = 22, + FMT_16 = 24, + FMT_16_16 = 25, + FMT_16_16_16_16 = 26, + FMT_16_EXPAND = 27, + FMT_16_16_EXPAND = 28, + FMT_16_16_16_16_EXPAND = 29, + FMT_16_FLOAT = 30, + FMT_16_16_FLOAT = 31, + FMT_16_16_16_16_FLOAT = 32, + FMT_32 = 33, + FMT_32_32 = 34, + FMT_32_32_32_32 = 35, + FMT_32_FLOAT = 36, + FMT_32_32_FLOAT = 37, + FMT_32_32_32_32_FLOAT = 38, + FMT_ATI_TC_RGB = 39, + FMT_ATI_TC_RGBA = 40, + FMT_ATI_TC_555_565_RGB = 41, + FMT_ATI_TC_555_565_RGBA = 42, + FMT_ATI_TC_RGBA_INTERP = 43, + FMT_ATI_TC_555_565_RGBA_INTERP = 44, + FMT_ETC1_RGBA_INTERP = 46, + FMT_ETC1_RGB = 47, + FMT_ETC1_RGBA = 48, + FMT_DXN = 49, + FMT_2_3_3 = 51, + FMT_2_10_10_10_AS_16_16_16_16 = 54, + FMT_10_10_10_2_AS_16_16_16_16 = 55, + FMT_32_32_32_FLOAT = 57, + FMT_DXT3A = 58, + FMT_DXT5A = 59, + FMT_CTX1 = 60, +} SurfaceFormat; +#endif /*ENUMS_SurfaceFormat_H*/ + +#ifndef ENUMS_SurfaceTiling_H +#define ENUMS_SurfaceTiling_H +typedef enum SurfaceTiling { + ARRAY_LINEAR = 0, + ARRAY_TILED = 1 +} SurfaceTiling; +#endif /*ENUMS_SurfaceTiling_H*/ + +#ifndef ENUMS_SurfaceArray_H +#define ENUMS_SurfaceArray_H +typedef enum SurfaceArray { + ARRAY_1D = 0, + ARRAY_2D = 1, + ARRAY_3D = 2, + ARRAY_3D_SLICE = 3 +} SurfaceArray; +#endif /*ENUMS_SurfaceArray_H*/ + +#ifndef ENUMS_SurfaceNumberX_H +#define ENUMS_SurfaceNumberX_H +typedef enum SurfaceNumberX { + NUMBERX_UREPEAT = 0, + NUMBERX_SREPEAT = 1, + NUMBERX_UINTEGER = 2, + NUMBERX_SINTEGER = 3, + NUMBERX_FLOAT = 7 +} SurfaceNumberX; +#endif /*ENUMS_SurfaceNumberX_H*/ + +#ifndef ENUMS_ColorArrayX_H +#define ENUMS_ColorArrayX_H +typedef enum ColorArrayX { + ARRAYX_2D_COLOR = 0, + ARRAYX_3D_SLICE_COLOR = 1, +} ColorArrayX; +#endif /*ENUMS_ColorArrayX_H*/ + +#endif /*_yamato_ENUM_HEADER*/ + diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_genenum.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_genenum.h new file mode 100644 index 000000000000..87a454a1e38a --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_genenum.h @@ -0,0 +1,1703 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +START_ENUMTYPE(SU_PERFCNT_SELECT) + GENERATE_ENUM(PERF_PAPC_PASX_REQ, 0) + GENERATE_ENUM(UNUSED1, 1) + GENERATE_ENUM(PERF_PAPC_PASX_FIRST_VECTOR, 2) + GENERATE_ENUM(PERF_PAPC_PASX_SECOND_VECTOR, 3) + GENERATE_ENUM(PERF_PAPC_PASX_FIRST_DEAD, 4) + GENERATE_ENUM(PERF_PAPC_PASX_SECOND_DEAD, 5) + GENERATE_ENUM(PERF_PAPC_PASX_VTX_KILL_DISCARD, 6) + GENERATE_ENUM(PERF_PAPC_PASX_VTX_NAN_DISCARD, 7) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_PRIM, 8) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_NULL_PRIM, 9) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_EVENT_FLAG, 10) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT, 11) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_END_OF_PACKET, 12) + GENERATE_ENUM(PERF_PAPC_CLPR_CULL_PRIM, 13) + GENERATE_ENUM(UNUSED2, 14) + GENERATE_ENUM(PERF_PAPC_CLPR_VV_CULL_PRIM, 15) + GENERATE_ENUM(UNUSED3, 16) + GENERATE_ENUM(PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM, 17) + GENERATE_ENUM(PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM, 18) + GENERATE_ENUM(PERF_PAPC_CLPR_CULL_TO_NULL_PRIM, 19) + GENERATE_ENUM(UNUSED4, 20) + GENERATE_ENUM(PERF_PAPC_CLPR_VV_CLIP_PRIM, 21) + GENERATE_ENUM(UNUSED5, 22) + GENERATE_ENUM(PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE, 23) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_1, 24) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_2, 25) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_3, 26) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_4, 27) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_5, 28) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_6, 29) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_NEAR, 30) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_FAR, 31) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_LEFT, 32) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_RIGHT, 33) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_TOP, 34) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM, 35) + GENERATE_ENUM(PERF_PAPC_CLSM_NULL_PRIM, 36) + GENERATE_ENUM(PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM, 37) + GENERATE_ENUM(PERF_PAPC_CLSM_CLIP_PRIM, 38) + GENERATE_ENUM(PERF_PAPC_CLSM_CULL_TO_NULL_PRIM, 39) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_1, 40) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_2, 41) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_3, 42) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_4, 43) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_5, 44) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7, 45) + GENERATE_ENUM(PERF_PAPC_CLSM_NON_TRIVIAL_CULL, 46) + GENERATE_ENUM(PERF_PAPC_SU_INPUT_PRIM, 47) + GENERATE_ENUM(PERF_PAPC_SU_INPUT_CLIP_PRIM, 48) + GENERATE_ENUM(PERF_PAPC_SU_INPUT_NULL_PRIM, 49) + GENERATE_ENUM(PERF_PAPC_SU_ZERO_AREA_CULL_PRIM, 50) + GENERATE_ENUM(PERF_PAPC_SU_BACK_FACE_CULL_PRIM, 51) + GENERATE_ENUM(PERF_PAPC_SU_FRONT_FACE_CULL_PRIM, 52) + GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_FACE_CULL, 53) + GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_BACK_CULL, 54) + GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_FRONT_CULL, 55) + GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_INVALID_FILL, 56) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_PRIM, 57) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_CLIP_PRIM, 58) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_NULL_PRIM, 59) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_EVENT_FLAG, 60) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT, 61) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_END_OF_PACKET, 62) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_FACE, 63) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_BACK, 64) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT, 65) + GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE, 66) + GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK, 67) + GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT, 68) + GENERATE_ENUM(PERF_PAPC_PASX_REQ_IDLE, 69) + GENERATE_ENUM(PERF_PAPC_PASX_REQ_BUSY, 70) + GENERATE_ENUM(PERF_PAPC_PASX_REQ_STALLED, 71) + GENERATE_ENUM(PERF_PAPC_PASX_REC_IDLE, 72) + GENERATE_ENUM(PERF_PAPC_PASX_REC_BUSY, 73) + GENERATE_ENUM(PERF_PAPC_PASX_REC_STARVED_SX, 74) + GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED, 75) + GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED_POS_MEM, 76) + GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED_CCGSM_IN, 77) + GENERATE_ENUM(PERF_PAPC_CCGSM_IDLE, 78) + GENERATE_ENUM(PERF_PAPC_CCGSM_BUSY, 79) + GENERATE_ENUM(PERF_PAPC_CCGSM_STALLED, 80) + GENERATE_ENUM(PERF_PAPC_CLPRIM_IDLE, 81) + GENERATE_ENUM(PERF_PAPC_CLPRIM_BUSY, 82) + GENERATE_ENUM(PERF_PAPC_CLPRIM_STALLED, 83) + GENERATE_ENUM(PERF_PAPC_CLPRIM_STARVED_CCGSM, 84) + GENERATE_ENUM(PERF_PAPC_CLIPSM_IDLE, 85) + GENERATE_ENUM(PERF_PAPC_CLIPSM_BUSY, 86) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH, 87) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ, 88) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIPGA, 89) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP, 90) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM, 91) + GENERATE_ENUM(PERF_PAPC_CLIPGA_IDLE, 92) + GENERATE_ENUM(PERF_PAPC_CLIPGA_BUSY, 93) + GENERATE_ENUM(PERF_PAPC_CLIPGA_STARVED_VTE_CLIP, 94) + GENERATE_ENUM(PERF_PAPC_CLIPGA_STALLED, 95) + GENERATE_ENUM(PERF_PAPC_CLIP_IDLE, 96) + GENERATE_ENUM(PERF_PAPC_CLIP_BUSY, 97) + GENERATE_ENUM(PERF_PAPC_SU_IDLE, 98) + GENERATE_ENUM(PERF_PAPC_SU_BUSY, 99) + GENERATE_ENUM(PERF_PAPC_SU_STARVED_CLIP, 100) + GENERATE_ENUM(PERF_PAPC_SU_STALLED_SC, 101) + GENERATE_ENUM(PERF_PAPC_SU_FACENESS_CULL, 102) +END_ENUMTYPE(SU_PERFCNT_SELECT) + +START_ENUMTYPE(SC_PERFCNT_SELECT) + GENERATE_ENUM(SC_SR_WINDOW_VALID, 0) + GENERATE_ENUM(SC_CW_WINDOW_VALID, 1) + GENERATE_ENUM(SC_QM_WINDOW_VALID, 2) + GENERATE_ENUM(SC_FW_WINDOW_VALID, 3) + GENERATE_ENUM(SC_EZ_WINDOW_VALID, 4) + GENERATE_ENUM(SC_IT_WINDOW_VALID, 5) + GENERATE_ENUM(SC_STARVED_BY_PA, 6) + GENERATE_ENUM(SC_STALLED_BY_RB_TILE, 7) + GENERATE_ENUM(SC_STALLED_BY_RB_SAMP, 8) + GENERATE_ENUM(SC_STARVED_BY_RB_EZ, 9) + GENERATE_ENUM(SC_STALLED_BY_SAMPLE_FF, 10) + GENERATE_ENUM(SC_STALLED_BY_SQ, 11) + GENERATE_ENUM(SC_STALLED_BY_SP, 12) + GENERATE_ENUM(SC_TOTAL_NO_PRIMS, 13) + GENERATE_ENUM(SC_NON_EMPTY_PRIMS, 14) + GENERATE_ENUM(SC_NO_TILES_PASSING_QM, 15) + GENERATE_ENUM(SC_NO_PIXELS_PRE_EZ, 16) + GENERATE_ENUM(SC_NO_PIXELS_POST_EZ, 17) +END_ENUMTYPE(SC_PERFCNT_SELECT) + +START_ENUMTYPE(VGT_DI_PRIM_TYPE) + GENERATE_ENUM(DI_PT_NONE, 0) + GENERATE_ENUM(DI_PT_POINTLIST, 1) + GENERATE_ENUM(DI_PT_LINELIST, 2) + GENERATE_ENUM(DI_PT_LINESTRIP, 3) + GENERATE_ENUM(DI_PT_TRILIST, 4) + GENERATE_ENUM(DI_PT_TRIFAN, 5) + GENERATE_ENUM(DI_PT_TRISTRIP, 6) + GENERATE_ENUM(DI_PT_UNUSED_1, 7) + GENERATE_ENUM(DI_PT_RECTLIST, 8) + GENERATE_ENUM(DI_PT_UNUSED_2, 9) + GENERATE_ENUM(DI_PT_UNUSED_3, 10) + GENERATE_ENUM(DI_PT_UNUSED_4, 11) + GENERATE_ENUM(DI_PT_UNUSED_5, 12) + GENERATE_ENUM(DI_PT_QUADLIST, 13) + GENERATE_ENUM(DI_PT_QUADSTRIP, 14) + GENERATE_ENUM(DI_PT_POLYGON, 15) + GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V0, 16) + GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V1, 17) + GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V2, 18) + GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V3, 19) + GENERATE_ENUM(DI_PT_2D_FILL_RECT_LIST, 20) + GENERATE_ENUM(DI_PT_2D_LINE_STRIP, 21) + GENERATE_ENUM(DI_PT_2D_TRI_STRIP, 22) +END_ENUMTYPE(VGT_DI_PRIM_TYPE) + +START_ENUMTYPE(VGT_DI_SOURCE_SELECT) + GENERATE_ENUM(DI_SRC_SEL_DMA, 0) + GENERATE_ENUM(DI_SRC_SEL_IMMEDIATE, 1) + GENERATE_ENUM(DI_SRC_SEL_AUTO_INDEX, 2) + GENERATE_ENUM(DI_SRC_SEL_RESERVED, 3) +END_ENUMTYPE(VGT_DI_SOURCE_SELECT) + +START_ENUMTYPE(VGT_DI_FACENESS_CULL_SELECT) + GENERATE_ENUM(DI_FACE_CULL_NONE, 0) + GENERATE_ENUM(DI_FACE_CULL_FETCH, 1) + GENERATE_ENUM(DI_FACE_BACKFACE_CULL, 2) + GENERATE_ENUM(DI_FACE_FRONTFACE_CULL, 3) +END_ENUMTYPE(VGT_DI_FACENESS_CULL_SELECT) + +START_ENUMTYPE(VGT_DI_INDEX_SIZE) + GENERATE_ENUM(DI_INDEX_SIZE_16_BIT, 0) + GENERATE_ENUM(DI_INDEX_SIZE_32_BIT, 1) +END_ENUMTYPE(VGT_DI_INDEX_SIZE) + +START_ENUMTYPE(VGT_DI_SMALL_INDEX) + GENERATE_ENUM(DI_USE_INDEX_SIZE, 0) + GENERATE_ENUM(DI_INDEX_SIZE_8_BIT, 1) +END_ENUMTYPE(VGT_DI_SMALL_INDEX) + +START_ENUMTYPE(VGT_DI_PRE_FETCH_CULL_ENABLE) + GENERATE_ENUM(DISABLE_PRE_FETCH_CULL_ENABLE, 0) + GENERATE_ENUM(PRE_FETCH_CULL_ENABLE, 1) +END_ENUMTYPE(VGT_DI_PRE_FETCH_CULL_ENABLE) + +START_ENUMTYPE(VGT_DI_GRP_CULL_ENABLE) + GENERATE_ENUM(DISABLE_GRP_CULL_ENABLE, 0) + GENERATE_ENUM(GRP_CULL_ENABLE, 1) +END_ENUMTYPE(VGT_DI_GRP_CULL_ENABLE) + +START_ENUMTYPE(VGT_EVENT_TYPE) + GENERATE_ENUM(VS_DEALLOC, 0) + GENERATE_ENUM(PS_DEALLOC, 1) + GENERATE_ENUM(VS_DONE_TS, 2) + GENERATE_ENUM(PS_DONE_TS, 3) + GENERATE_ENUM(CACHE_FLUSH_TS, 4) + GENERATE_ENUM(CONTEXT_DONE, 5) + GENERATE_ENUM(CACHE_FLUSH, 6) + GENERATE_ENUM(VIZQUERY_START, 7) + GENERATE_ENUM(VIZQUERY_END, 8) + GENERATE_ENUM(SC_WAIT_WC, 9) + GENERATE_ENUM(RST_PIX_CNT, 13) + GENERATE_ENUM(RST_VTX_CNT, 14) + GENERATE_ENUM(TILE_FLUSH, 15) + GENERATE_ENUM(CACHE_FLUSH_AND_INV_TS_EVENT, 20) + GENERATE_ENUM(ZPASS_DONE, 21) + GENERATE_ENUM(CACHE_FLUSH_AND_INV_EVENT, 22) + GENERATE_ENUM(PERFCOUNTER_START, 23) + GENERATE_ENUM(PERFCOUNTER_STOP, 24) + GENERATE_ENUM(VS_FETCH_DONE, 27) + GENERATE_ENUM(FACENESS_FLUSH, 28) +END_ENUMTYPE(VGT_EVENT_TYPE) + +START_ENUMTYPE(VGT_DMA_SWAP_MODE) + GENERATE_ENUM(VGT_DMA_SWAP_NONE, 0) + GENERATE_ENUM(VGT_DMA_SWAP_16_BIT, 1) + GENERATE_ENUM(VGT_DMA_SWAP_32_BIT, 2) + GENERATE_ENUM(VGT_DMA_SWAP_WORD, 3) +END_ENUMTYPE(VGT_DMA_SWAP_MODE) + +START_ENUMTYPE(VGT_PERFCOUNT_SELECT) + GENERATE_ENUM(VGT_SQ_EVENT_WINDOW_ACTIVE, 0) + GENERATE_ENUM(VGT_SQ_SEND, 1) + GENERATE_ENUM(VGT_SQ_STALLED, 2) + GENERATE_ENUM(VGT_SQ_STARVED_BUSY, 3) + GENERATE_ENUM(VGT_SQ_STARVED_IDLE, 4) + GENERATE_ENUM(VGT_SQ_STATIC, 5) + GENERATE_ENUM(VGT_PA_EVENT_WINDOW_ACTIVE, 6) + GENERATE_ENUM(VGT_PA_CLIP_V_SEND, 7) + GENERATE_ENUM(VGT_PA_CLIP_V_STALLED, 8) + GENERATE_ENUM(VGT_PA_CLIP_V_STARVED_BUSY, 9) + GENERATE_ENUM(VGT_PA_CLIP_V_STARVED_IDLE, 10) + GENERATE_ENUM(VGT_PA_CLIP_V_STATIC, 11) + GENERATE_ENUM(VGT_PA_CLIP_P_SEND, 12) + GENERATE_ENUM(VGT_PA_CLIP_P_STALLED, 13) + GENERATE_ENUM(VGT_PA_CLIP_P_STARVED_BUSY, 14) + GENERATE_ENUM(VGT_PA_CLIP_P_STARVED_IDLE, 15) + GENERATE_ENUM(VGT_PA_CLIP_P_STATIC, 16) + GENERATE_ENUM(VGT_PA_CLIP_S_SEND, 17) + GENERATE_ENUM(VGT_PA_CLIP_S_STALLED, 18) + GENERATE_ENUM(VGT_PA_CLIP_S_STARVED_BUSY, 19) + GENERATE_ENUM(VGT_PA_CLIP_S_STARVED_IDLE, 20) + GENERATE_ENUM(VGT_PA_CLIP_S_STATIC, 21) + GENERATE_ENUM(RBIU_FIFOS_EVENT_WINDOW_ACTIVE, 22) + GENERATE_ENUM(RBIU_IMMED_DATA_FIFO_STARVED, 23) + GENERATE_ENUM(RBIU_IMMED_DATA_FIFO_STALLED, 24) + GENERATE_ENUM(RBIU_DMA_REQUEST_FIFO_STARVED, 25) + GENERATE_ENUM(RBIU_DMA_REQUEST_FIFO_STALLED, 26) + GENERATE_ENUM(RBIU_DRAW_INITIATOR_FIFO_STARVED, 27) + GENERATE_ENUM(RBIU_DRAW_INITIATOR_FIFO_STALLED, 28) + GENERATE_ENUM(BIN_PRIM_NEAR_CULL, 29) + GENERATE_ENUM(BIN_PRIM_ZERO_CULL, 30) + GENERATE_ENUM(BIN_PRIM_FAR_CULL, 31) + GENERATE_ENUM(BIN_PRIM_BIN_CULL, 32) + GENERATE_ENUM(BIN_PRIM_FACE_CULL, 33) + GENERATE_ENUM(SPARE34, 34) + GENERATE_ENUM(SPARE35, 35) + GENERATE_ENUM(SPARE36, 36) + GENERATE_ENUM(SPARE37, 37) + GENERATE_ENUM(SPARE38, 38) + GENERATE_ENUM(SPARE39, 39) + GENERATE_ENUM(TE_SU_IN_VALID, 40) + GENERATE_ENUM(TE_SU_IN_READ, 41) + GENERATE_ENUM(TE_SU_IN_PRIM, 42) + GENERATE_ENUM(TE_SU_IN_EOP, 43) + GENERATE_ENUM(TE_SU_IN_NULL_PRIM, 44) + GENERATE_ENUM(TE_WK_IN_VALID, 45) + GENERATE_ENUM(TE_WK_IN_READ, 46) + GENERATE_ENUM(TE_OUT_PRIM_VALID, 47) + GENERATE_ENUM(TE_OUT_PRIM_READ, 48) +END_ENUMTYPE(VGT_PERFCOUNT_SELECT) + +START_ENUMTYPE(TCR_PERFCOUNT_SELECT) + GENERATE_ENUM(DGMMPD_IPMUX0_STALL, 0) + GENERATE_ENUM(reserved_46, 1) + GENERATE_ENUM(reserved_47, 2) + GENERATE_ENUM(reserved_48, 3) + GENERATE_ENUM(DGMMPD_IPMUX_ALL_STALL, 4) + GENERATE_ENUM(OPMUX0_L2_WRITES, 5) + GENERATE_ENUM(reserved_49, 6) + GENERATE_ENUM(reserved_50, 7) + GENERATE_ENUM(reserved_51, 8) +END_ENUMTYPE(TCR_PERFCOUNT_SELECT) + +START_ENUMTYPE(TP_PERFCOUNT_SELECT) + GENERATE_ENUM(POINT_QUADS, 0) + GENERATE_ENUM(BILIN_QUADS, 1) + GENERATE_ENUM(ANISO_QUADS, 2) + GENERATE_ENUM(MIP_QUADS, 3) + GENERATE_ENUM(VOL_QUADS, 4) + GENERATE_ENUM(MIP_VOL_QUADS, 5) + GENERATE_ENUM(MIP_ANISO_QUADS, 6) + GENERATE_ENUM(VOL_ANISO_QUADS, 7) + GENERATE_ENUM(ANISO_2_1_QUADS, 8) + GENERATE_ENUM(ANISO_4_1_QUADS, 9) + GENERATE_ENUM(ANISO_6_1_QUADS, 10) + GENERATE_ENUM(ANISO_8_1_QUADS, 11) + GENERATE_ENUM(ANISO_10_1_QUADS, 12) + GENERATE_ENUM(ANISO_12_1_QUADS, 13) + GENERATE_ENUM(ANISO_14_1_QUADS, 14) + GENERATE_ENUM(ANISO_16_1_QUADS, 15) + GENERATE_ENUM(MIP_VOL_ANISO_QUADS, 16) + GENERATE_ENUM(ALIGN_2_QUADS, 17) + GENERATE_ENUM(ALIGN_4_QUADS, 18) + GENERATE_ENUM(PIX_0_QUAD, 19) + GENERATE_ENUM(PIX_1_QUAD, 20) + GENERATE_ENUM(PIX_2_QUAD, 21) + GENERATE_ENUM(PIX_3_QUAD, 22) + GENERATE_ENUM(PIX_4_QUAD, 23) + GENERATE_ENUM(TP_MIPMAP_LOD0, 24) + GENERATE_ENUM(TP_MIPMAP_LOD1, 25) + GENERATE_ENUM(TP_MIPMAP_LOD2, 26) + GENERATE_ENUM(TP_MIPMAP_LOD3, 27) + GENERATE_ENUM(TP_MIPMAP_LOD4, 28) + GENERATE_ENUM(TP_MIPMAP_LOD5, 29) + GENERATE_ENUM(TP_MIPMAP_LOD6, 30) + GENERATE_ENUM(TP_MIPMAP_LOD7, 31) + GENERATE_ENUM(TP_MIPMAP_LOD8, 32) + GENERATE_ENUM(TP_MIPMAP_LOD9, 33) + GENERATE_ENUM(TP_MIPMAP_LOD10, 34) + GENERATE_ENUM(TP_MIPMAP_LOD11, 35) + GENERATE_ENUM(TP_MIPMAP_LOD12, 36) + GENERATE_ENUM(TP_MIPMAP_LOD13, 37) + GENERATE_ENUM(TP_MIPMAP_LOD14, 38) +END_ENUMTYPE(TP_PERFCOUNT_SELECT) + +START_ENUMTYPE(TCM_PERFCOUNT_SELECT) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_EMPTY, 0) + GENERATE_ENUM(reserved_01, 1) + GENERATE_ENUM(reserved_02, 2) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_4TH_FULL, 3) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_HALF_FULL, 4) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_FULL, 5) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_LT_4TH_FULL, 6) + GENERATE_ENUM(reserved_07, 7) + GENERATE_ENUM(reserved_08, 8) + GENERATE_ENUM(reserved_09, 9) + GENERATE_ENUM(reserved_10, 10) + GENERATE_ENUM(reserved_11, 11) + GENERATE_ENUM(reserved_12, 12) + GENERATE_ENUM(reserved_13, 13) + GENERATE_ENUM(reserved_14, 14) + GENERATE_ENUM(reserved_15, 15) + GENERATE_ENUM(reserved_16, 16) + GENERATE_ENUM(reserved_17, 17) + GENERATE_ENUM(reserved_18, 18) + GENERATE_ENUM(reserved_19, 19) + GENERATE_ENUM(reserved_20, 20) + GENERATE_ENUM(reserved_21, 21) + GENERATE_ENUM(reserved_22, 22) + GENERATE_ENUM(reserved_23, 23) + GENERATE_ENUM(reserved_24, 24) + GENERATE_ENUM(reserved_25, 25) + GENERATE_ENUM(reserved_26, 26) + GENERATE_ENUM(reserved_27, 27) + GENERATE_ENUM(READ_STARVED_QUAD0, 28) + GENERATE_ENUM(reserved_29, 29) + GENERATE_ENUM(reserved_30, 30) + GENERATE_ENUM(reserved_31, 31) + GENERATE_ENUM(READ_STARVED, 32) + GENERATE_ENUM(READ_STALLED_QUAD0, 33) + GENERATE_ENUM(reserved_34, 34) + GENERATE_ENUM(reserved_35, 35) + GENERATE_ENUM(reserved_36, 36) + GENERATE_ENUM(READ_STALLED, 37) + GENERATE_ENUM(VALID_READ_QUAD0, 38) + GENERATE_ENUM(reserved_39, 39) + GENERATE_ENUM(reserved_40, 40) + GENERATE_ENUM(reserved_41, 41) + GENERATE_ENUM(TC_TP_STARVED_QUAD0, 42) + GENERATE_ENUM(reserved_43, 43) + GENERATE_ENUM(reserved_44, 44) + GENERATE_ENUM(reserved_45, 45) + GENERATE_ENUM(TC_TP_STARVED, 46) +END_ENUMTYPE(TCM_PERFCOUNT_SELECT) + +START_ENUMTYPE(TCF_PERFCOUNT_SELECT) + GENERATE_ENUM(VALID_CYCLES, 0) + GENERATE_ENUM(SINGLE_PHASES, 1) + GENERATE_ENUM(ANISO_PHASES, 2) + GENERATE_ENUM(MIP_PHASES, 3) + GENERATE_ENUM(VOL_PHASES, 4) + GENERATE_ENUM(MIP_VOL_PHASES, 5) + GENERATE_ENUM(MIP_ANISO_PHASES, 6) + GENERATE_ENUM(VOL_ANISO_PHASES, 7) + GENERATE_ENUM(ANISO_2_1_PHASES, 8) + GENERATE_ENUM(ANISO_4_1_PHASES, 9) + GENERATE_ENUM(ANISO_6_1_PHASES, 10) + GENERATE_ENUM(ANISO_8_1_PHASES, 11) + GENERATE_ENUM(ANISO_10_1_PHASES, 12) + GENERATE_ENUM(ANISO_12_1_PHASES, 13) + GENERATE_ENUM(ANISO_14_1_PHASES, 14) + GENERATE_ENUM(ANISO_16_1_PHASES, 15) + GENERATE_ENUM(MIP_VOL_ANISO_PHASES, 16) + GENERATE_ENUM(ALIGN_2_PHASES, 17) + GENERATE_ENUM(ALIGN_4_PHASES, 18) + GENERATE_ENUM(TPC_BUSY, 19) + GENERATE_ENUM(TPC_STALLED, 20) + GENERATE_ENUM(TPC_STARVED, 21) + GENERATE_ENUM(TPC_WORKING, 22) + GENERATE_ENUM(TPC_WALKER_BUSY, 23) + GENERATE_ENUM(TPC_WALKER_STALLED, 24) + GENERATE_ENUM(TPC_WALKER_WORKING, 25) + GENERATE_ENUM(TPC_ALIGNER_BUSY, 26) + GENERATE_ENUM(TPC_ALIGNER_STALLED, 27) + GENERATE_ENUM(TPC_ALIGNER_STALLED_BY_BLEND, 28) + GENERATE_ENUM(TPC_ALIGNER_STALLED_BY_CACHE, 29) + GENERATE_ENUM(TPC_ALIGNER_WORKING, 30) + GENERATE_ENUM(TPC_BLEND_BUSY, 31) + GENERATE_ENUM(TPC_BLEND_SYNC, 32) + GENERATE_ENUM(TPC_BLEND_STARVED, 33) + GENERATE_ENUM(TPC_BLEND_WORKING, 34) + GENERATE_ENUM(OPCODE_0x00, 35) + GENERATE_ENUM(OPCODE_0x01, 36) + GENERATE_ENUM(OPCODE_0x04, 37) + GENERATE_ENUM(OPCODE_0x10, 38) + GENERATE_ENUM(OPCODE_0x11, 39) + GENERATE_ENUM(OPCODE_0x12, 40) + GENERATE_ENUM(OPCODE_0x13, 41) + GENERATE_ENUM(OPCODE_0x18, 42) + GENERATE_ENUM(OPCODE_0x19, 43) + GENERATE_ENUM(OPCODE_0x1A, 44) + GENERATE_ENUM(OPCODE_OTHER, 45) + GENERATE_ENUM(IN_FIFO_0_EMPTY, 56) + GENERATE_ENUM(IN_FIFO_0_LT_HALF_FULL, 57) + GENERATE_ENUM(IN_FIFO_0_HALF_FULL, 58) + GENERATE_ENUM(IN_FIFO_0_FULL, 59) + GENERATE_ENUM(IN_FIFO_TPC_EMPTY, 72) + GENERATE_ENUM(IN_FIFO_TPC_LT_HALF_FULL, 73) + GENERATE_ENUM(IN_FIFO_TPC_HALF_FULL, 74) + GENERATE_ENUM(IN_FIFO_TPC_FULL, 75) + GENERATE_ENUM(TPC_TC_XFC, 76) + GENERATE_ENUM(TPC_TC_STATE, 77) + GENERATE_ENUM(TC_STALL, 78) + GENERATE_ENUM(QUAD0_TAPS, 79) + GENERATE_ENUM(QUADS, 83) + GENERATE_ENUM(TCA_SYNC_STALL, 84) + GENERATE_ENUM(TAG_STALL, 85) + GENERATE_ENUM(TCB_SYNC_STALL, 88) + GENERATE_ENUM(TCA_VALID, 89) + GENERATE_ENUM(PROBES_VALID, 90) + GENERATE_ENUM(MISS_STALL, 91) + GENERATE_ENUM(FETCH_FIFO_STALL, 92) + GENERATE_ENUM(TCO_STALL, 93) + GENERATE_ENUM(ANY_STALL, 94) + GENERATE_ENUM(TAG_MISSES, 95) + GENERATE_ENUM(TAG_HITS, 96) + GENERATE_ENUM(SUB_TAG_MISSES, 97) + GENERATE_ENUM(SET0_INVALIDATES, 98) + GENERATE_ENUM(SET1_INVALIDATES, 99) + GENERATE_ENUM(SET2_INVALIDATES, 100) + GENERATE_ENUM(SET3_INVALIDATES, 101) + GENERATE_ENUM(SET0_TAG_MISSES, 102) + GENERATE_ENUM(SET1_TAG_MISSES, 103) + GENERATE_ENUM(SET2_TAG_MISSES, 104) + GENERATE_ENUM(SET3_TAG_MISSES, 105) + GENERATE_ENUM(SET0_TAG_HITS, 106) + GENERATE_ENUM(SET1_TAG_HITS, 107) + GENERATE_ENUM(SET2_TAG_HITS, 108) + GENERATE_ENUM(SET3_TAG_HITS, 109) + GENERATE_ENUM(SET0_SUB_TAG_MISSES, 110) + GENERATE_ENUM(SET1_SUB_TAG_MISSES, 111) + GENERATE_ENUM(SET2_SUB_TAG_MISSES, 112) + GENERATE_ENUM(SET3_SUB_TAG_MISSES, 113) + GENERATE_ENUM(SET0_EVICT1, 114) + GENERATE_ENUM(SET0_EVICT2, 115) + GENERATE_ENUM(SET0_EVICT3, 116) + GENERATE_ENUM(SET0_EVICT4, 117) + GENERATE_ENUM(SET0_EVICT5, 118) + GENERATE_ENUM(SET0_EVICT6, 119) + GENERATE_ENUM(SET0_EVICT7, 120) + GENERATE_ENUM(SET0_EVICT8, 121) + GENERATE_ENUM(SET1_EVICT1, 130) + GENERATE_ENUM(SET1_EVICT2, 131) + GENERATE_ENUM(SET1_EVICT3, 132) + GENERATE_ENUM(SET1_EVICT4, 133) + GENERATE_ENUM(SET1_EVICT5, 134) + GENERATE_ENUM(SET1_EVICT6, 135) + GENERATE_ENUM(SET1_EVICT7, 136) + GENERATE_ENUM(SET1_EVICT8, 137) + GENERATE_ENUM(SET2_EVICT1, 146) + GENERATE_ENUM(SET2_EVICT2, 147) + GENERATE_ENUM(SET2_EVICT3, 148) + GENERATE_ENUM(SET2_EVICT4, 149) + GENERATE_ENUM(SET2_EVICT5, 150) + GENERATE_ENUM(SET2_EVICT6, 151) + GENERATE_ENUM(SET2_EVICT7, 152) + GENERATE_ENUM(SET2_EVICT8, 153) + GENERATE_ENUM(SET3_EVICT1, 162) + GENERATE_ENUM(SET3_EVICT2, 163) + GENERATE_ENUM(SET3_EVICT3, 164) + GENERATE_ENUM(SET3_EVICT4, 165) + GENERATE_ENUM(SET3_EVICT5, 166) + GENERATE_ENUM(SET3_EVICT6, 167) + GENERATE_ENUM(SET3_EVICT7, 168) + GENERATE_ENUM(SET3_EVICT8, 169) + GENERATE_ENUM(FF_EMPTY, 178) + GENERATE_ENUM(FF_LT_HALF_FULL, 179) + GENERATE_ENUM(FF_HALF_FULL, 180) + GENERATE_ENUM(FF_FULL, 181) + GENERATE_ENUM(FF_XFC, 182) + GENERATE_ENUM(FF_STALLED, 183) + GENERATE_ENUM(FG_MASKS, 184) + GENERATE_ENUM(FG_LEFT_MASKS, 185) + GENERATE_ENUM(FG_LEFT_MASK_STALLED, 186) + GENERATE_ENUM(FG_LEFT_NOT_DONE_STALL, 187) + GENERATE_ENUM(FG_LEFT_FG_STALL, 188) + GENERATE_ENUM(FG_LEFT_SECTORS, 189) + GENERATE_ENUM(FG0_REQUESTS, 195) + GENERATE_ENUM(FG0_STALLED, 196) + GENERATE_ENUM(MEM_REQ512, 199) + GENERATE_ENUM(MEM_REQ_SENT, 200) + GENERATE_ENUM(MEM_LOCAL_READ_REQ, 202) + GENERATE_ENUM(TC0_MH_STALLED, 203) +END_ENUMTYPE(TCF_PERFCOUNT_SELECT) + +START_ENUMTYPE(SQ_PERFCNT_SELECT) + GENERATE_ENUM(SQ_PIXEL_VECTORS_SUB, 0) + GENERATE_ENUM(SQ_VERTEX_VECTORS_SUB, 1) + GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD0, 2) + GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD0, 3) + GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD0, 4) + GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD0, 5) + GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD1, 6) + GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD1, 7) + GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD1, 8) + GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD1, 9) + GENERATE_ENUM(SQ_EXPORT_CYCLES, 10) + GENERATE_ENUM(SQ_ALU_CST_WRITTEN, 11) + GENERATE_ENUM(SQ_TEX_CST_WRITTEN, 12) + GENERATE_ENUM(SQ_ALU_CST_STALL, 13) + GENERATE_ENUM(SQ_ALU_TEX_STALL, 14) + GENERATE_ENUM(SQ_INST_WRITTEN, 15) + GENERATE_ENUM(SQ_BOOLEAN_WRITTEN, 16) + GENERATE_ENUM(SQ_LOOPS_WRITTEN, 17) + GENERATE_ENUM(SQ_PIXEL_SWAP_IN, 18) + GENERATE_ENUM(SQ_PIXEL_SWAP_OUT, 19) + GENERATE_ENUM(SQ_VERTEX_SWAP_IN, 20) + GENERATE_ENUM(SQ_VERTEX_SWAP_OUT, 21) + GENERATE_ENUM(SQ_ALU_VTX_INST_ISSUED, 22) + GENERATE_ENUM(SQ_TEX_VTX_INST_ISSUED, 23) + GENERATE_ENUM(SQ_VC_VTX_INST_ISSUED, 24) + GENERATE_ENUM(SQ_CF_VTX_INST_ISSUED, 25) + GENERATE_ENUM(SQ_ALU_PIX_INST_ISSUED, 26) + GENERATE_ENUM(SQ_TEX_PIX_INST_ISSUED, 27) + GENERATE_ENUM(SQ_VC_PIX_INST_ISSUED, 28) + GENERATE_ENUM(SQ_CF_PIX_INST_ISSUED, 29) + GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD0, 30) + GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD0, 31) + GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD1, 32) + GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD1, 33) + GENERATE_ENUM(SQ_ALU_NOPS, 34) + GENERATE_ENUM(SQ_PRED_SKIP, 35) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD0_VTX, 36) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD1_VTX, 37) + GENERATE_ENUM(SQ_SYNC_TEX_STALL_VTX, 38) + GENERATE_ENUM(SQ_SYNC_VC_STALL_VTX, 39) + GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD0, 40) + GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD0, 41) + GENERATE_ENUM(SQ_GPR_STALL_VTX, 42) + GENERATE_ENUM(SQ_GPR_STALL_PIX, 43) + GENERATE_ENUM(SQ_VTX_RS_STALL, 44) + GENERATE_ENUM(SQ_PIX_RS_STALL, 45) + GENERATE_ENUM(SQ_SX_PC_FULL, 46) + GENERATE_ENUM(SQ_SX_EXP_BUFF_FULL, 47) + GENERATE_ENUM(SQ_SX_POS_BUFF_FULL, 48) + GENERATE_ENUM(SQ_INTERP_QUADS, 49) + GENERATE_ENUM(SQ_INTERP_ACTIVE, 50) + GENERATE_ENUM(SQ_IN_PIXEL_STALL, 51) + GENERATE_ENUM(SQ_IN_VTX_STALL, 52) + GENERATE_ENUM(SQ_VTX_CNT, 53) + GENERATE_ENUM(SQ_VTX_VECTOR2, 54) + GENERATE_ENUM(SQ_VTX_VECTOR3, 55) + GENERATE_ENUM(SQ_VTX_VECTOR4, 56) + GENERATE_ENUM(SQ_PIXEL_VECTOR1, 57) + GENERATE_ENUM(SQ_PIXEL_VECTOR23, 58) + GENERATE_ENUM(SQ_PIXEL_VECTOR4, 59) + GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD1, 60) + GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD1, 61) + GENERATE_ENUM(SQ_SX_MEM_EXP_FULL, 62) + GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD2, 63) + GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD2, 64) + GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD2, 65) + GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD2, 66) + GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD3, 67) + GENERATE_ENUM(SQ_PERFCOUNT_VTX_QUAL_TP_DONE, 68) + GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD3, 69) + GENERATE_ENUM(SQ_PERFCOUNT_PIX_QUAL_TP_DONE, 70) + GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD2, 71) + GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD2, 72) + GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD3, 73) + GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD3, 74) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD2_VTX, 75) + GENERATE_ENUM(SQ_PERFCOUNT_VTX_POP_THREAD, 76) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD0_PIX, 77) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD1_PIX, 78) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD2_PIX, 79) + GENERATE_ENUM(SQ_PERFCOUNT_PIX_POP_THREAD, 80) + GENERATE_ENUM(SQ_SYNC_TEX_STALL_PIX, 81) + GENERATE_ENUM(SQ_SYNC_VC_STALL_PIX, 82) + GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD2, 83) + GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD2, 84) + GENERATE_ENUM(SQ_PERFCOUNT_VTX_DEALLOC_ACK, 85) + GENERATE_ENUM(SQ_PERFCOUNT_PIX_DEALLOC_ACK, 86) + GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD0, 87) + GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD0, 88) + GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD1, 89) + GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD1, 90) + GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD2, 91) + GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD2, 92) + GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD3, 93) + GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD3, 94) + GENERATE_ENUM(VC_PERF_STATIC, 95) + GENERATE_ENUM(VC_PERF_STALLED, 96) + GENERATE_ENUM(VC_PERF_STARVED, 97) + GENERATE_ENUM(VC_PERF_SEND, 98) + GENERATE_ENUM(VC_PERF_ACTUAL_STARVED, 99) + GENERATE_ENUM(PIXEL_THREAD_0_ACTIVE, 100) + GENERATE_ENUM(VERTEX_THREAD_0_ACTIVE, 101) + GENERATE_ENUM(PIXEL_THREAD_0_NUMBER, 102) + GENERATE_ENUM(VERTEX_THREAD_0_NUMBER, 103) + GENERATE_ENUM(VERTEX_EVENT_NUMBER, 104) + GENERATE_ENUM(PIXEL_EVENT_NUMBER, 105) + GENERATE_ENUM(PTRBUFF_EF_PUSH, 106) + GENERATE_ENUM(PTRBUFF_EF_POP_EVENT, 107) + GENERATE_ENUM(PTRBUFF_EF_POP_NEW_VTX, 108) + GENERATE_ENUM(PTRBUFF_EF_POP_DEALLOC, 109) + GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR, 110) + GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR_X, 111) + GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR_VNZ, 112) + GENERATE_ENUM(PTRBUFF_PB_DEALLOC, 113) + GENERATE_ENUM(PTRBUFF_PI_STATE_PPB_POP, 114) + GENERATE_ENUM(PTRBUFF_PI_RTR, 115) + GENERATE_ENUM(PTRBUFF_PI_READ_EN, 116) + GENERATE_ENUM(PTRBUFF_PI_BUFF_SWAP, 117) + GENERATE_ENUM(PTRBUFF_SQ_FREE_BUFF, 118) + GENERATE_ENUM(PTRBUFF_SQ_DEC, 119) + GENERATE_ENUM(PTRBUFF_SC_VALID_CNTL_EVENT, 120) + GENERATE_ENUM(PTRBUFF_SC_VALID_IJ_XFER, 121) + GENERATE_ENUM(PTRBUFF_SC_NEW_VECTOR_1_Q, 122) + GENERATE_ENUM(PTRBUFF_QUAL_NEW_VECTOR, 123) + GENERATE_ENUM(PTRBUFF_QUAL_EVENT, 124) + GENERATE_ENUM(PTRBUFF_END_BUFFER, 125) + GENERATE_ENUM(PTRBUFF_FILL_QUAD, 126) + GENERATE_ENUM(VERTS_WRITTEN_SPI, 127) + GENERATE_ENUM(TP_FETCH_INSTR_EXEC, 128) + GENERATE_ENUM(TP_FETCH_INSTR_REQ, 129) + GENERATE_ENUM(TP_DATA_RETURN, 130) + GENERATE_ENUM(SPI_WRITE_CYCLES_SP, 131) + GENERATE_ENUM(SPI_WRITES_SP, 132) + GENERATE_ENUM(SP_ALU_INSTR_EXEC, 133) + GENERATE_ENUM(SP_CONST_ADDR_TO_SQ, 134) + GENERATE_ENUM(SP_PRED_KILLS_TO_SQ, 135) + GENERATE_ENUM(SP_EXPORT_CYCLES_TO_SX, 136) + GENERATE_ENUM(SP_EXPORTS_TO_SX, 137) + GENERATE_ENUM(SQ_CYCLES_ELAPSED, 138) + GENERATE_ENUM(SQ_TCFS_OPT_ALLOC_EXEC, 139) + GENERATE_ENUM(SQ_TCFS_NO_OPT_ALLOC, 140) + GENERATE_ENUM(SQ_ALU0_NO_OPT_ALLOC, 141) + GENERATE_ENUM(SQ_ALU1_NO_OPT_ALLOC, 142) + GENERATE_ENUM(SQ_TCFS_ARB_XFC_CNT, 143) + GENERATE_ENUM(SQ_ALU0_ARB_XFC_CNT, 144) + GENERATE_ENUM(SQ_ALU1_ARB_XFC_CNT, 145) + GENERATE_ENUM(SQ_TCFS_CFS_UPDATE_CNT, 146) + GENERATE_ENUM(SQ_ALU0_CFS_UPDATE_CNT, 147) + GENERATE_ENUM(SQ_ALU1_CFS_UPDATE_CNT, 148) + GENERATE_ENUM(SQ_VTX_PUSH_THREAD_CNT, 149) + GENERATE_ENUM(SQ_VTX_POP_THREAD_CNT, 150) + GENERATE_ENUM(SQ_PIX_PUSH_THREAD_CNT, 151) + GENERATE_ENUM(SQ_PIX_POP_THREAD_CNT, 152) + GENERATE_ENUM(SQ_PIX_TOTAL, 153) + GENERATE_ENUM(SQ_PIX_KILLED, 154) +END_ENUMTYPE(SQ_PERFCNT_SELECT) + +START_ENUMTYPE(SX_PERFCNT_SELECT) + GENERATE_ENUM(SX_EXPORT_VECTORS, 0) + GENERATE_ENUM(SX_DUMMY_QUADS, 1) + GENERATE_ENUM(SX_ALPHA_FAIL, 2) + GENERATE_ENUM(SX_RB_QUAD_BUSY, 3) + GENERATE_ENUM(SX_RB_COLOR_BUSY, 4) + GENERATE_ENUM(SX_RB_QUAD_STALL, 5) + GENERATE_ENUM(SX_RB_COLOR_STALL, 6) +END_ENUMTYPE(SX_PERFCNT_SELECT) + +START_ENUMTYPE(Abs_modifier) + GENERATE_ENUM(NO_ABS_MOD, 0) + GENERATE_ENUM(ABS_MOD, 1) +END_ENUMTYPE(Abs_modifier) + +START_ENUMTYPE(Exporting) + GENERATE_ENUM(NOT_EXPORTING, 0) + GENERATE_ENUM(EXPORTING, 1) +END_ENUMTYPE(Exporting) + +START_ENUMTYPE(ScalarOpcode) + GENERATE_ENUM(ADDs, 0) + GENERATE_ENUM(ADD_PREVs, 1) + GENERATE_ENUM(MULs, 2) + GENERATE_ENUM(MUL_PREVs, 3) + GENERATE_ENUM(MUL_PREV2s, 4) + GENERATE_ENUM(MAXs, 5) + GENERATE_ENUM(MINs, 6) + GENERATE_ENUM(SETEs, 7) + GENERATE_ENUM(SETGTs, 8) + GENERATE_ENUM(SETGTEs, 9) + GENERATE_ENUM(SETNEs, 10) + GENERATE_ENUM(FRACs, 11) + GENERATE_ENUM(TRUNCs, 12) + GENERATE_ENUM(FLOORs, 13) + GENERATE_ENUM(EXP_IEEE, 14) + GENERATE_ENUM(LOG_CLAMP, 15) + GENERATE_ENUM(LOG_IEEE, 16) + GENERATE_ENUM(RECIP_CLAMP, 17) + GENERATE_ENUM(RECIP_FF, 18) + GENERATE_ENUM(RECIP_IEEE, 19) + GENERATE_ENUM(RECIPSQ_CLAMP, 20) + GENERATE_ENUM(RECIPSQ_FF, 21) + GENERATE_ENUM(RECIPSQ_IEEE, 22) + GENERATE_ENUM(MOVAs, 23) + GENERATE_ENUM(MOVA_FLOORs, 24) + GENERATE_ENUM(SUBs, 25) + GENERATE_ENUM(SUB_PREVs, 26) + GENERATE_ENUM(PRED_SETEs, 27) + GENERATE_ENUM(PRED_SETNEs, 28) + GENERATE_ENUM(PRED_SETGTs, 29) + GENERATE_ENUM(PRED_SETGTEs, 30) + GENERATE_ENUM(PRED_SET_INVs, 31) + GENERATE_ENUM(PRED_SET_POPs, 32) + GENERATE_ENUM(PRED_SET_CLRs, 33) + GENERATE_ENUM(PRED_SET_RESTOREs, 34) + GENERATE_ENUM(KILLEs, 35) + GENERATE_ENUM(KILLGTs, 36) + GENERATE_ENUM(KILLGTEs, 37) + GENERATE_ENUM(KILLNEs, 38) + GENERATE_ENUM(KILLONEs, 39) + GENERATE_ENUM(SQRT_IEEE, 40) + GENERATE_ENUM(MUL_CONST_0, 42) + GENERATE_ENUM(MUL_CONST_1, 43) + GENERATE_ENUM(ADD_CONST_0, 44) + GENERATE_ENUM(ADD_CONST_1, 45) + GENERATE_ENUM(SUB_CONST_0, 46) + GENERATE_ENUM(SUB_CONST_1, 47) + GENERATE_ENUM(SIN, 48) + GENERATE_ENUM(COS, 49) + GENERATE_ENUM(RETAIN_PREV, 50) +END_ENUMTYPE(ScalarOpcode) + +START_ENUMTYPE(SwizzleType) + GENERATE_ENUM(NO_SWIZZLE, 0) + GENERATE_ENUM(SHIFT_RIGHT_1, 1) + GENERATE_ENUM(SHIFT_RIGHT_2, 2) + GENERATE_ENUM(SHIFT_RIGHT_3, 3) +END_ENUMTYPE(SwizzleType) + +START_ENUMTYPE(InputModifier) + GENERATE_ENUM(NIL, 0) + GENERATE_ENUM(NEGATE, 1) +END_ENUMTYPE(InputModifier) + +START_ENUMTYPE(PredicateSelect) + GENERATE_ENUM(NO_PREDICATION, 0) + GENERATE_ENUM(PREDICATE_QUAD, 1) + GENERATE_ENUM(PREDICATED_2, 2) + GENERATE_ENUM(PREDICATED_3, 3) +END_ENUMTYPE(PredicateSelect) + +START_ENUMTYPE(OperandSelect1) + GENERATE_ENUM(ABSOLUTE_REG, 0) + GENERATE_ENUM(RELATIVE_REG, 1) +END_ENUMTYPE(OperandSelect1) + +START_ENUMTYPE(VectorOpcode) + GENERATE_ENUM(ADDv, 0) + GENERATE_ENUM(MULv, 1) + GENERATE_ENUM(MAXv, 2) + GENERATE_ENUM(MINv, 3) + GENERATE_ENUM(SETEv, 4) + GENERATE_ENUM(SETGTv, 5) + GENERATE_ENUM(SETGTEv, 6) + GENERATE_ENUM(SETNEv, 7) + GENERATE_ENUM(FRACv, 8) + GENERATE_ENUM(TRUNCv, 9) + GENERATE_ENUM(FLOORv, 10) + GENERATE_ENUM(MULADDv, 11) + GENERATE_ENUM(CNDEv, 12) + GENERATE_ENUM(CNDGTEv, 13) + GENERATE_ENUM(CNDGTv, 14) + GENERATE_ENUM(DOT4v, 15) + GENERATE_ENUM(DOT3v, 16) + GENERATE_ENUM(DOT2ADDv, 17) + GENERATE_ENUM(CUBEv, 18) + GENERATE_ENUM(MAX4v, 19) + GENERATE_ENUM(PRED_SETE_PUSHv, 20) + GENERATE_ENUM(PRED_SETNE_PUSHv, 21) + GENERATE_ENUM(PRED_SETGT_PUSHv, 22) + GENERATE_ENUM(PRED_SETGTE_PUSHv, 23) + GENERATE_ENUM(KILLEv, 24) + GENERATE_ENUM(KILLGTv, 25) + GENERATE_ENUM(KILLGTEv, 26) + GENERATE_ENUM(KILLNEv, 27) + GENERATE_ENUM(DSTv, 28) + GENERATE_ENUM(MOVAv, 29) +END_ENUMTYPE(VectorOpcode) + +START_ENUMTYPE(OperandSelect0) + GENERATE_ENUM(CONSTANT, 0) + GENERATE_ENUM(NON_CONSTANT, 1) +END_ENUMTYPE(OperandSelect0) + +START_ENUMTYPE(Ressource_type) + GENERATE_ENUM(ALU, 0) + GENERATE_ENUM(TEXTURE, 1) +END_ENUMTYPE(Ressource_type) + +START_ENUMTYPE(Instruction_serial) + GENERATE_ENUM(NOT_SERIAL, 0) + GENERATE_ENUM(SERIAL, 1) +END_ENUMTYPE(Instruction_serial) + +START_ENUMTYPE(VC_type) + GENERATE_ENUM(ALU_TP_REQUEST, 0) + GENERATE_ENUM(VC_REQUEST, 1) +END_ENUMTYPE(VC_type) + +START_ENUMTYPE(Addressing) + GENERATE_ENUM(RELATIVE_ADDR, 0) + GENERATE_ENUM(ABSOLUTE_ADDR, 1) +END_ENUMTYPE(Addressing) + +START_ENUMTYPE(CFOpcode) + GENERATE_ENUM(NOP, 0) + GENERATE_ENUM(EXECUTE, 1) + GENERATE_ENUM(EXECUTE_END, 2) + GENERATE_ENUM(COND_EXECUTE, 3) + GENERATE_ENUM(COND_EXECUTE_END, 4) + GENERATE_ENUM(COND_PRED_EXECUTE, 5) + GENERATE_ENUM(COND_PRED_EXECUTE_END, 6) + GENERATE_ENUM(LOOP_START, 7) + GENERATE_ENUM(LOOP_END, 8) + GENERATE_ENUM(COND_CALL, 9) + GENERATE_ENUM(RETURN, 10) + GENERATE_ENUM(COND_JMP, 11) + GENERATE_ENUM(ALLOCATE, 12) + GENERATE_ENUM(COND_EXECUTE_PRED_CLEAN, 13) + GENERATE_ENUM(COND_EXECUTE_PRED_CLEAN_END, 14) + GENERATE_ENUM(MARK_VS_FETCH_DONE, 15) +END_ENUMTYPE(CFOpcode) + +START_ENUMTYPE(Allocation_type) + GENERATE_ENUM(SQ_NO_ALLOC, 0) + GENERATE_ENUM(SQ_POSITION, 1) + GENERATE_ENUM(SQ_PARAMETER_PIXEL, 2) + GENERATE_ENUM(SQ_MEMORY, 3) +END_ENUMTYPE(Allocation_type) + +START_ENUMTYPE(TexInstOpcode) + GENERATE_ENUM(TEX_INST_FETCH, 1) + GENERATE_ENUM(TEX_INST_RESERVED_1, 2) + GENERATE_ENUM(TEX_INST_RESERVED_2, 3) + GENERATE_ENUM(TEX_INST_RESERVED_3, 4) + GENERATE_ENUM(TEX_INST_GET_BORDER_COLOR_FRAC, 16) + GENERATE_ENUM(TEX_INST_GET_COMP_TEX_LOD, 17) + GENERATE_ENUM(TEX_INST_GET_GRADIENTS, 18) + GENERATE_ENUM(TEX_INST_GET_WEIGHTS, 19) + GENERATE_ENUM(TEX_INST_SET_TEX_LOD, 24) + GENERATE_ENUM(TEX_INST_SET_GRADIENTS_H, 25) + GENERATE_ENUM(TEX_INST_SET_GRADIENTS_V, 26) + GENERATE_ENUM(TEX_INST_RESERVED_4, 27) +END_ENUMTYPE(TexInstOpcode) + +START_ENUMTYPE(Addressmode) + GENERATE_ENUM(LOGICAL, 0) + GENERATE_ENUM(LOOP_RELATIVE, 1) +END_ENUMTYPE(Addressmode) + +START_ENUMTYPE(TexCoordDenorm) + GENERATE_ENUM(TEX_COORD_NORMALIZED, 0) + GENERATE_ENUM(TEX_COORD_UNNORMALIZED, 1) +END_ENUMTYPE(TexCoordDenorm) + +START_ENUMTYPE(SrcSel) + GENERATE_ENUM(SRC_SEL_X, 0) + GENERATE_ENUM(SRC_SEL_Y, 1) + GENERATE_ENUM(SRC_SEL_Z, 2) + GENERATE_ENUM(SRC_SEL_W, 3) +END_ENUMTYPE(SrcSel) + +START_ENUMTYPE(DstSel) + GENERATE_ENUM(DST_SEL_X, 0) + GENERATE_ENUM(DST_SEL_Y, 1) + GENERATE_ENUM(DST_SEL_Z, 2) + GENERATE_ENUM(DST_SEL_W, 3) + GENERATE_ENUM(DST_SEL_0, 4) + GENERATE_ENUM(DST_SEL_1, 5) + GENERATE_ENUM(DST_SEL_RSVD, 6) + GENERATE_ENUM(DST_SEL_MASK, 7) +END_ENUMTYPE(DstSel) + +START_ENUMTYPE(MagFilter) + GENERATE_ENUM(MAG_FILTER_POINT, 0) + GENERATE_ENUM(MAG_FILTER_LINEAR, 1) + GENERATE_ENUM(MAG_FILTER_RESERVED_0, 2) + GENERATE_ENUM(MAG_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(MagFilter) + +START_ENUMTYPE(MinFilter) + GENERATE_ENUM(MIN_FILTER_POINT, 0) + GENERATE_ENUM(MIN_FILTER_LINEAR, 1) + GENERATE_ENUM(MIN_FILTER_RESERVED_0, 2) + GENERATE_ENUM(MIN_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(MinFilter) + +START_ENUMTYPE(MipFilter) + GENERATE_ENUM(MIP_FILTER_POINT, 0) + GENERATE_ENUM(MIP_FILTER_LINEAR, 1) + GENERATE_ENUM(MIP_FILTER_BASEMAP, 2) + GENERATE_ENUM(MIP_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(MipFilter) + +START_ENUMTYPE(AnisoFilter) + GENERATE_ENUM(ANISO_FILTER_DISABLED, 0) + GENERATE_ENUM(ANISO_FILTER_MAX_1_1, 1) + GENERATE_ENUM(ANISO_FILTER_MAX_2_1, 2) + GENERATE_ENUM(ANISO_FILTER_MAX_4_1, 3) + GENERATE_ENUM(ANISO_FILTER_MAX_8_1, 4) + GENERATE_ENUM(ANISO_FILTER_MAX_16_1, 5) + GENERATE_ENUM(ANISO_FILTER_USE_FETCH_CONST, 7) +END_ENUMTYPE(AnisoFilter) + +START_ENUMTYPE(ArbitraryFilter) + GENERATE_ENUM(ARBITRARY_FILTER_2X4_SYM, 0) + GENERATE_ENUM(ARBITRARY_FILTER_2X4_ASYM, 1) + GENERATE_ENUM(ARBITRARY_FILTER_4X2_SYM, 2) + GENERATE_ENUM(ARBITRARY_FILTER_4X2_ASYM, 3) + GENERATE_ENUM(ARBITRARY_FILTER_4X4_SYM, 4) + GENERATE_ENUM(ARBITRARY_FILTER_4X4_ASYM, 5) + GENERATE_ENUM(ARBITRARY_FILTER_USE_FETCH_CONST, 7) +END_ENUMTYPE(ArbitraryFilter) + +START_ENUMTYPE(VolMagFilter) + GENERATE_ENUM(VOL_MAG_FILTER_POINT, 0) + GENERATE_ENUM(VOL_MAG_FILTER_LINEAR, 1) + GENERATE_ENUM(VOL_MAG_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(VolMagFilter) + +START_ENUMTYPE(VolMinFilter) + GENERATE_ENUM(VOL_MIN_FILTER_POINT, 0) + GENERATE_ENUM(VOL_MIN_FILTER_LINEAR, 1) + GENERATE_ENUM(VOL_MIN_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(VolMinFilter) + +START_ENUMTYPE(PredSelect) + GENERATE_ENUM(NOT_PREDICATED, 0) + GENERATE_ENUM(PREDICATED, 1) +END_ENUMTYPE(PredSelect) + +START_ENUMTYPE(SampleLocation) + GENERATE_ENUM(SAMPLE_CENTROID, 0) + GENERATE_ENUM(SAMPLE_CENTER, 1) +END_ENUMTYPE(SampleLocation) + +START_ENUMTYPE(VertexMode) + GENERATE_ENUM(POSITION_1_VECTOR, 0) + GENERATE_ENUM(POSITION_2_VECTORS_UNUSED, 1) + GENERATE_ENUM(POSITION_2_VECTORS_SPRITE, 2) + GENERATE_ENUM(POSITION_2_VECTORS_EDGE, 3) + GENERATE_ENUM(POSITION_2_VECTORS_KILL, 4) + GENERATE_ENUM(POSITION_2_VECTORS_SPRITE_KILL, 5) + GENERATE_ENUM(POSITION_2_VECTORS_EDGE_KILL, 6) + GENERATE_ENUM(MULTIPASS, 7) +END_ENUMTYPE(VertexMode) + +START_ENUMTYPE(Sample_Cntl) + GENERATE_ENUM(CENTROIDS_ONLY, 0) + GENERATE_ENUM(CENTERS_ONLY, 1) + GENERATE_ENUM(CENTROIDS_AND_CENTERS, 2) + GENERATE_ENUM(UNDEF, 3) +END_ENUMTYPE(Sample_Cntl) + +START_ENUMTYPE(MhPerfEncode) + GENERATE_ENUM(CP_R0_REQUESTS, 0) + GENERATE_ENUM(CP_R1_REQUESTS, 1) + GENERATE_ENUM(CP_R2_REQUESTS, 2) + GENERATE_ENUM(CP_R3_REQUESTS, 3) + GENERATE_ENUM(CP_R4_REQUESTS, 4) + GENERATE_ENUM(CP_TOTAL_READ_REQUESTS, 5) + GENERATE_ENUM(CP_TOTAL_WRITE_REQUESTS, 6) + GENERATE_ENUM(CP_TOTAL_REQUESTS, 7) + GENERATE_ENUM(CP_DATA_BYTES_WRITTEN, 8) + GENERATE_ENUM(CP_WRITE_CLEAN_RESPONSES, 9) + GENERATE_ENUM(CP_R0_READ_BURSTS_RECEIVED, 10) + GENERATE_ENUM(CP_R1_READ_BURSTS_RECEIVED, 11) + GENERATE_ENUM(CP_R2_READ_BURSTS_RECEIVED, 12) + GENERATE_ENUM(CP_R3_READ_BURSTS_RECEIVED, 13) + GENERATE_ENUM(CP_R4_READ_BURSTS_RECEIVED, 14) + GENERATE_ENUM(CP_TOTAL_READ_BURSTS_RECEIVED, 15) + GENERATE_ENUM(CP_R0_DATA_BEATS_READ, 16) + GENERATE_ENUM(CP_R1_DATA_BEATS_READ, 17) + GENERATE_ENUM(CP_R2_DATA_BEATS_READ, 18) + GENERATE_ENUM(CP_R3_DATA_BEATS_READ, 19) + GENERATE_ENUM(CP_R4_DATA_BEATS_READ, 20) + GENERATE_ENUM(CP_TOTAL_DATA_BEATS_READ, 21) + GENERATE_ENUM(VGT_R0_REQUESTS, 22) + GENERATE_ENUM(VGT_R1_REQUESTS, 23) + GENERATE_ENUM(VGT_TOTAL_REQUESTS, 24) + GENERATE_ENUM(VGT_R0_READ_BURSTS_RECEIVED, 25) + GENERATE_ENUM(VGT_R1_READ_BURSTS_RECEIVED, 26) + GENERATE_ENUM(VGT_TOTAL_READ_BURSTS_RECEIVED, 27) + GENERATE_ENUM(VGT_R0_DATA_BEATS_READ, 28) + GENERATE_ENUM(VGT_R1_DATA_BEATS_READ, 29) + GENERATE_ENUM(VGT_TOTAL_DATA_BEATS_READ, 30) + GENERATE_ENUM(TC_TOTAL_REQUESTS, 31) + GENERATE_ENUM(TC_ROQ_REQUESTS, 32) + GENERATE_ENUM(TC_INFO_SENT, 33) + GENERATE_ENUM(TC_READ_BURSTS_RECEIVED, 34) + GENERATE_ENUM(TC_DATA_BEATS_READ, 35) + GENERATE_ENUM(TCD_BURSTS_READ, 36) + GENERATE_ENUM(RB_REQUESTS, 37) + GENERATE_ENUM(RB_DATA_BYTES_WRITTEN, 38) + GENERATE_ENUM(RB_WRITE_CLEAN_RESPONSES, 39) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_0, 40) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_1, 41) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_2, 42) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_3, 43) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_4, 44) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_5, 45) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_6, 46) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_7, 47) + GENERATE_ENUM(AXI_TOTAL_READ_REQUESTS, 48) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_0, 49) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_1, 50) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_2, 51) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_3, 52) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_4, 53) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_5, 54) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_6, 55) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_7, 56) + GENERATE_ENUM(AXI_TOTAL_WRITE_REQUESTS, 57) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_0, 58) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_1, 59) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_2, 60) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_3, 61) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_4, 62) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_5, 63) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_6, 64) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_7, 65) + GENERATE_ENUM(AXI_TOTAL_REQUESTS, 66) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_0, 67) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_1, 68) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_2, 69) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_3, 70) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_4, 71) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_5, 72) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_6, 73) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_7, 74) + GENERATE_ENUM(AXI_READ_CHANNEL_TOTAL_BURSTS, 75) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0, 76) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1, 77) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2, 78) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3, 79) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4, 80) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5, 81) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6, 82) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7, 83) + GENERATE_ENUM(AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ, 84) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_0, 85) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_1, 86) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_2, 87) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_3, 88) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_4, 89) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_5, 90) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_6, 91) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_7, 92) + GENERATE_ENUM(AXI_WRITE_CHANNEL_TOTAL_BURSTS, 93) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0, 94) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1, 95) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2, 96) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3, 97) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4, 98) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5, 99) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6, 100) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7, 101) + GENERATE_ENUM(AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN, 102) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0, 103) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1, 104) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2, 105) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3, 106) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4, 107) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5, 108) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6, 109) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7, 110) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES, 111) + GENERATE_ENUM(TOTAL_MMU_MISSES, 112) + GENERATE_ENUM(MMU_READ_MISSES, 113) + GENERATE_ENUM(MMU_WRITE_MISSES, 114) + GENERATE_ENUM(TOTAL_MMU_HITS, 115) + GENERATE_ENUM(MMU_READ_HITS, 116) + GENERATE_ENUM(MMU_WRITE_HITS, 117) + GENERATE_ENUM(SPLIT_MODE_TC_HITS, 118) + GENERATE_ENUM(SPLIT_MODE_TC_MISSES, 119) + GENERATE_ENUM(SPLIT_MODE_NON_TC_HITS, 120) + GENERATE_ENUM(SPLIT_MODE_NON_TC_MISSES, 121) + GENERATE_ENUM(STALL_AWAITING_TLB_MISS_FETCH, 122) + GENERATE_ENUM(MMU_TLB_MISS_READ_BURSTS_RECEIVED, 123) + GENERATE_ENUM(MMU_TLB_MISS_DATA_BEATS_READ, 124) + GENERATE_ENUM(CP_CYCLES_HELD_OFF, 125) + GENERATE_ENUM(VGT_CYCLES_HELD_OFF, 126) + GENERATE_ENUM(TC_CYCLES_HELD_OFF, 127) + GENERATE_ENUM(TC_ROQ_CYCLES_HELD_OFF, 128) + GENERATE_ENUM(TC_CYCLES_HELD_OFF_TCD_FULL, 129) + GENERATE_ENUM(RB_CYCLES_HELD_OFF, 130) + GENERATE_ENUM(TOTAL_CYCLES_ANY_CLNT_HELD_OFF, 131) + GENERATE_ENUM(TLB_MISS_CYCLES_HELD_OFF, 132) + GENERATE_ENUM(AXI_READ_REQUEST_HELD_OFF, 133) + GENERATE_ENUM(AXI_WRITE_REQUEST_HELD_OFF, 134) + GENERATE_ENUM(AXI_REQUEST_HELD_OFF, 135) + GENERATE_ENUM(AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT, 136) + GENERATE_ENUM(AXI_WRITE_DATA_HELD_OFF, 137) + GENERATE_ENUM(CP_SAME_PAGE_BANK_REQUESTS, 138) + GENERATE_ENUM(VGT_SAME_PAGE_BANK_REQUESTS, 139) + GENERATE_ENUM(TC_SAME_PAGE_BANK_REQUESTS, 140) + GENERATE_ENUM(TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS, 141) + GENERATE_ENUM(RB_SAME_PAGE_BANK_REQUESTS, 142) + GENERATE_ENUM(TOTAL_SAME_PAGE_BANK_REQUESTS, 143) + GENERATE_ENUM(CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 144) + GENERATE_ENUM(VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 145) + GENERATE_ENUM(TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 146) + GENERATE_ENUM(RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 147) + GENERATE_ENUM(TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT, 148) + GENERATE_ENUM(TOTAL_MH_READ_REQUESTS, 149) + GENERATE_ENUM(TOTAL_MH_WRITE_REQUESTS, 150) + GENERATE_ENUM(TOTAL_MH_REQUESTS, 151) + GENERATE_ENUM(MH_BUSY, 152) + GENERATE_ENUM(CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 153) + GENERATE_ENUM(VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 154) + GENERATE_ENUM(TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 155) + GENERATE_ENUM(RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 156) + GENERATE_ENUM(TC_ROQ_N_VALID_ENTRIES, 157) + GENERATE_ENUM(ARQ_N_ENTRIES, 158) + GENERATE_ENUM(WDB_N_ENTRIES, 159) + GENERATE_ENUM(MH_READ_LATENCY_OUTST_REQ_SUM, 160) + GENERATE_ENUM(MC_READ_LATENCY_OUTST_REQ_SUM, 161) + GENERATE_ENUM(MC_TOTAL_READ_REQUESTS, 162) + GENERATE_ENUM(ELAPSED_CYCLES_MH_GATED_CLK, 163) + GENERATE_ENUM(ELAPSED_CLK_CYCLES, 164) + GENERATE_ENUM(CP_W_16B_REQUESTS, 165) + GENERATE_ENUM(CP_W_32B_REQUESTS, 166) + GENERATE_ENUM(TC_16B_REQUESTS, 167) + GENERATE_ENUM(TC_32B_REQUESTS, 168) + GENERATE_ENUM(PA_REQUESTS, 169) + GENERATE_ENUM(PA_DATA_BYTES_WRITTEN, 170) + GENERATE_ENUM(PA_WRITE_CLEAN_RESPONSES, 171) + GENERATE_ENUM(PA_CYCLES_HELD_OFF, 172) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_0, 173) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_1, 174) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_2, 175) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_3, 176) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_4, 177) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_5, 178) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_6, 179) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_7, 180) + GENERATE_ENUM(AXI_TOTAL_READ_REQUEST_DATA_BEATS, 181) +END_ENUMTYPE(MhPerfEncode) + +START_ENUMTYPE(MmuClntBeh) + GENERATE_ENUM(BEH_NEVR, 0) + GENERATE_ENUM(BEH_TRAN_RNG, 1) + GENERATE_ENUM(BEH_TRAN_FLT, 2) +END_ENUMTYPE(MmuClntBeh) + +START_ENUMTYPE(RBBM_PERFCOUNT1_SEL) + GENERATE_ENUM(RBBM1_COUNT, 0) + GENERATE_ENUM(RBBM1_NRT_BUSY, 1) + GENERATE_ENUM(RBBM1_RB_BUSY, 2) + GENERATE_ENUM(RBBM1_SQ_CNTX0_BUSY, 3) + GENERATE_ENUM(RBBM1_SQ_CNTX17_BUSY, 4) + GENERATE_ENUM(RBBM1_VGT_BUSY, 5) + GENERATE_ENUM(RBBM1_VGT_NODMA_BUSY, 6) + GENERATE_ENUM(RBBM1_PA_BUSY, 7) + GENERATE_ENUM(RBBM1_SC_CNTX_BUSY, 8) + GENERATE_ENUM(RBBM1_TPC_BUSY, 9) + GENERATE_ENUM(RBBM1_TC_BUSY, 10) + GENERATE_ENUM(RBBM1_SX_BUSY, 11) + GENERATE_ENUM(RBBM1_CP_COHER_BUSY, 12) + GENERATE_ENUM(RBBM1_CP_NRT_BUSY, 13) + GENERATE_ENUM(RBBM1_GFX_IDLE_STALL, 14) + GENERATE_ENUM(RBBM1_INTERRUPT, 15) +END_ENUMTYPE(RBBM_PERFCOUNT1_SEL) + +START_ENUMTYPE(CP_PERFCOUNT_SEL) + GENERATE_ENUM(ALWAYS_COUNT, 0) + GENERATE_ENUM(TRANS_FIFO_FULL, 1) + GENERATE_ENUM(TRANS_FIFO_AF, 2) + GENERATE_ENUM(RCIU_PFPTRANS_WAIT, 3) + GENERATE_ENUM(Reserved_04, 4) + GENERATE_ENUM(Reserved_05, 5) + GENERATE_ENUM(RCIU_NRTTRANS_WAIT, 6) + GENERATE_ENUM(Reserved_07, 7) + GENERATE_ENUM(CSF_NRT_READ_WAIT, 8) + GENERATE_ENUM(CSF_I1_FIFO_FULL, 9) + GENERATE_ENUM(CSF_I2_FIFO_FULL, 10) + GENERATE_ENUM(CSF_ST_FIFO_FULL, 11) + GENERATE_ENUM(Reserved_12, 12) + GENERATE_ENUM(CSF_RING_ROQ_FULL, 13) + GENERATE_ENUM(CSF_I1_ROQ_FULL, 14) + GENERATE_ENUM(CSF_I2_ROQ_FULL, 15) + GENERATE_ENUM(CSF_ST_ROQ_FULL, 16) + GENERATE_ENUM(Reserved_17, 17) + GENERATE_ENUM(MIU_TAG_MEM_FULL, 18) + GENERATE_ENUM(MIU_WRITECLEAN, 19) + GENERATE_ENUM(Reserved_20, 20) + GENERATE_ENUM(Reserved_21, 21) + GENERATE_ENUM(MIU_NRT_WRITE_STALLED, 22) + GENERATE_ENUM(MIU_NRT_READ_STALLED, 23) + GENERATE_ENUM(ME_WRITE_CONFIRM_FIFO_FULL, 24) + GENERATE_ENUM(ME_VS_DEALLOC_FIFO_FULL, 25) + GENERATE_ENUM(ME_PS_DEALLOC_FIFO_FULL, 26) + GENERATE_ENUM(ME_REGS_VS_EVENT_FIFO_FULL, 27) + GENERATE_ENUM(ME_REGS_PS_EVENT_FIFO_FULL, 28) + GENERATE_ENUM(ME_REGS_CF_EVENT_FIFO_FULL, 29) + GENERATE_ENUM(ME_MICRO_RB_STARVED, 30) + GENERATE_ENUM(ME_MICRO_I1_STARVED, 31) + GENERATE_ENUM(ME_MICRO_I2_STARVED, 32) + GENERATE_ENUM(ME_MICRO_ST_STARVED, 33) + GENERATE_ENUM(Reserved_34, 34) + GENERATE_ENUM(Reserved_35, 35) + GENERATE_ENUM(Reserved_36, 36) + GENERATE_ENUM(Reserved_37, 37) + GENERATE_ENUM(Reserved_38, 38) + GENERATE_ENUM(Reserved_39, 39) + GENERATE_ENUM(RCIU_RBBM_DWORD_SENT, 40) + GENERATE_ENUM(ME_BUSY_CLOCKS, 41) + GENERATE_ENUM(ME_WAIT_CONTEXT_AVAIL, 42) + GENERATE_ENUM(PFP_TYPE0_PACKET, 43) + GENERATE_ENUM(PFP_TYPE3_PACKET, 44) + GENERATE_ENUM(CSF_RB_WPTR_NEQ_RPTR, 45) + GENERATE_ENUM(CSF_I1_SIZE_NEQ_ZERO, 46) + GENERATE_ENUM(CSF_I2_SIZE_NEQ_ZERO, 47) + GENERATE_ENUM(CSF_RBI1I2_FETCHING, 48) + GENERATE_ENUM(Reserved_49, 49) + GENERATE_ENUM(Reserved_50, 50) + GENERATE_ENUM(Reserved_51, 51) + GENERATE_ENUM(Reserved_52, 52) + GENERATE_ENUM(Reserved_53, 53) + GENERATE_ENUM(Reserved_54, 54) + GENERATE_ENUM(Reserved_55, 55) + GENERATE_ENUM(Reserved_56, 56) + GENERATE_ENUM(Reserved_57, 57) + GENERATE_ENUM(Reserved_58, 58) + GENERATE_ENUM(Reserved_59, 59) + GENERATE_ENUM(Reserved_60, 60) + GENERATE_ENUM(Reserved_61, 61) + GENERATE_ENUM(Reserved_62, 62) + GENERATE_ENUM(Reserved_63, 63) +END_ENUMTYPE(CP_PERFCOUNT_SEL) + +START_ENUMTYPE(ColorformatX) + GENERATE_ENUM(COLORX_4_4_4_4, 0) + GENERATE_ENUM(COLORX_1_5_5_5, 1) + GENERATE_ENUM(COLORX_5_6_5, 2) + GENERATE_ENUM(COLORX_8, 3) + GENERATE_ENUM(COLORX_8_8, 4) + GENERATE_ENUM(COLORX_8_8_8_8, 5) + GENERATE_ENUM(COLORX_S8_8_8_8, 6) + GENERATE_ENUM(COLORX_16_FLOAT, 7) + GENERATE_ENUM(COLORX_16_16_FLOAT, 8) + GENERATE_ENUM(COLORX_16_16_16_16_FLOAT, 9) + GENERATE_ENUM(COLORX_32_FLOAT, 10) + GENERATE_ENUM(COLORX_32_32_FLOAT, 11) + GENERATE_ENUM(COLORX_32_32_32_32_FLOAT, 12) + GENERATE_ENUM(COLORX_2_3_3, 13) + GENERATE_ENUM(COLORX_8_8_8, 14) +END_ENUMTYPE(ColorformatX) + +START_ENUMTYPE(DepthformatX) + GENERATE_ENUM(DEPTHX_16, 0) + GENERATE_ENUM(DEPTHX_24_8, 1) +END_ENUMTYPE(DepthformatX) + +START_ENUMTYPE(CompareFrag) + GENERATE_ENUM(FRAG_NEVER, 0) + GENERATE_ENUM(FRAG_LESS, 1) + GENERATE_ENUM(FRAG_EQUAL, 2) + GENERATE_ENUM(FRAG_LEQUAL, 3) + GENERATE_ENUM(FRAG_GREATER, 4) + GENERATE_ENUM(FRAG_NOTEQUAL, 5) + GENERATE_ENUM(FRAG_GEQUAL, 6) + GENERATE_ENUM(FRAG_ALWAYS, 7) +END_ENUMTYPE(CompareFrag) + +START_ENUMTYPE(CompareRef) + GENERATE_ENUM(REF_NEVER, 0) + GENERATE_ENUM(REF_LESS, 1) + GENERATE_ENUM(REF_EQUAL, 2) + GENERATE_ENUM(REF_LEQUAL, 3) + GENERATE_ENUM(REF_GREATER, 4) + GENERATE_ENUM(REF_NOTEQUAL, 5) + GENERATE_ENUM(REF_GEQUAL, 6) + GENERATE_ENUM(REF_ALWAYS, 7) +END_ENUMTYPE(CompareRef) + +START_ENUMTYPE(StencilOp) + GENERATE_ENUM(STENCIL_KEEP, 0) + GENERATE_ENUM(STENCIL_ZERO, 1) + GENERATE_ENUM(STENCIL_REPLACE, 2) + GENERATE_ENUM(STENCIL_INCR_CLAMP, 3) + GENERATE_ENUM(STENCIL_DECR_CLAMP, 4) + GENERATE_ENUM(STENCIL_INVERT, 5) + GENERATE_ENUM(STENCIL_INCR_WRAP, 6) + GENERATE_ENUM(STENCIL_DECR_WRAP, 7) +END_ENUMTYPE(StencilOp) + +START_ENUMTYPE(BlendOpX) + GENERATE_ENUM(BLENDX_ZERO, 0) + GENERATE_ENUM(BLENDX_ONE, 1) + GENERATE_ENUM(BLENDX_SRC_COLOR, 4) + GENERATE_ENUM(BLENDX_ONE_MINUS_SRC_COLOR, 5) + GENERATE_ENUM(BLENDX_SRC_ALPHA, 6) + GENERATE_ENUM(BLENDX_ONE_MINUS_SRC_ALPHA, 7) + GENERATE_ENUM(BLENDX_DST_COLOR, 8) + GENERATE_ENUM(BLENDX_ONE_MINUS_DST_COLOR, 9) + GENERATE_ENUM(BLENDX_DST_ALPHA, 10) + GENERATE_ENUM(BLENDX_ONE_MINUS_DST_ALPHA, 11) + GENERATE_ENUM(BLENDX_CONSTANT_COLOR, 12) + GENERATE_ENUM(BLENDX_ONE_MINUS_CONSTANT_COLOR, 13) + GENERATE_ENUM(BLENDX_CONSTANT_ALPHA, 14) + GENERATE_ENUM(BLENDX_ONE_MINUS_CONSTANT_ALPHA, 15) + GENERATE_ENUM(BLENDX_SRC_ALPHA_SATURATE, 16) +END_ENUMTYPE(BlendOpX) + +START_ENUMTYPE(CombFuncX) + GENERATE_ENUM(COMB_DST_PLUS_SRC, 0) + GENERATE_ENUM(COMB_SRC_MINUS_DST, 1) + GENERATE_ENUM(COMB_MIN_DST_SRC, 2) + GENERATE_ENUM(COMB_MAX_DST_SRC, 3) + GENERATE_ENUM(COMB_DST_MINUS_SRC, 4) + GENERATE_ENUM(COMB_DST_PLUS_SRC_BIAS, 5) +END_ENUMTYPE(CombFuncX) + +START_ENUMTYPE(DitherModeX) + GENERATE_ENUM(DITHER_DISABLE, 0) + GENERATE_ENUM(DITHER_ALWAYS, 1) + GENERATE_ENUM(DITHER_IF_ALPHA_OFF, 2) +END_ENUMTYPE(DitherModeX) + +START_ENUMTYPE(DitherTypeX) + GENERATE_ENUM(DITHER_PIXEL, 0) + GENERATE_ENUM(DITHER_SUBPIXEL, 1) +END_ENUMTYPE(DitherTypeX) + +START_ENUMTYPE(EdramMode) + GENERATE_ENUM(EDRAM_NOP, 0) + GENERATE_ENUM(COLOR_DEPTH, 4) + GENERATE_ENUM(DEPTH_ONLY, 5) + GENERATE_ENUM(EDRAM_COPY, 6) +END_ENUMTYPE(EdramMode) + +START_ENUMTYPE(SurfaceEndian) + GENERATE_ENUM(ENDIAN_NONE, 0) + GENERATE_ENUM(ENDIAN_8IN16, 1) + GENERATE_ENUM(ENDIAN_8IN32, 2) + GENERATE_ENUM(ENDIAN_16IN32, 3) + GENERATE_ENUM(ENDIAN_8IN64, 4) + GENERATE_ENUM(ENDIAN_8IN128, 5) +END_ENUMTYPE(SurfaceEndian) + +START_ENUMTYPE(EdramSizeX) + GENERATE_ENUM(EDRAMSIZE_16KB, 0) + GENERATE_ENUM(EDRAMSIZE_32KB, 1) + GENERATE_ENUM(EDRAMSIZE_64KB, 2) + GENERATE_ENUM(EDRAMSIZE_128KB, 3) + GENERATE_ENUM(EDRAMSIZE_256KB, 4) + GENERATE_ENUM(EDRAMSIZE_512KB, 5) + GENERATE_ENUM(EDRAMSIZE_1MB, 6) + GENERATE_ENUM(EDRAMSIZE_2MB, 7) + GENERATE_ENUM(EDRAMSIZE_4MB, 8) + GENERATE_ENUM(EDRAMSIZE_8MB, 9) + GENERATE_ENUM(EDRAMSIZE_16MB, 10) +END_ENUMTYPE(EdramSizeX) + +START_ENUMTYPE(RB_PERFCNT_SELECT) + GENERATE_ENUM(RBPERF_CNTX_BUSY, 0) + GENERATE_ENUM(RBPERF_CNTX_BUSY_MAX, 1) + GENERATE_ENUM(RBPERF_SX_QUAD_STARVED, 2) + GENERATE_ENUM(RBPERF_SX_QUAD_STARVED_MAX, 3) + GENERATE_ENUM(RBPERF_GA_GC_CH0_SYS_REQ, 4) + GENERATE_ENUM(RBPERF_GA_GC_CH0_SYS_REQ_MAX, 5) + GENERATE_ENUM(RBPERF_GA_GC_CH1_SYS_REQ, 6) + GENERATE_ENUM(RBPERF_GA_GC_CH1_SYS_REQ_MAX, 7) + GENERATE_ENUM(RBPERF_MH_STARVED, 8) + GENERATE_ENUM(RBPERF_MH_STARVED_MAX, 9) + GENERATE_ENUM(RBPERF_AZ_BC_COLOR_BUSY, 10) + GENERATE_ENUM(RBPERF_AZ_BC_COLOR_BUSY_MAX, 11) + GENERATE_ENUM(RBPERF_AZ_BC_Z_BUSY, 12) + GENERATE_ENUM(RBPERF_AZ_BC_Z_BUSY_MAX, 13) + GENERATE_ENUM(RBPERF_RB_SC_TILE_RTR_N, 14) + GENERATE_ENUM(RBPERF_RB_SC_TILE_RTR_N_MAX, 15) + GENERATE_ENUM(RBPERF_RB_SC_SAMP_RTR_N, 16) + GENERATE_ENUM(RBPERF_RB_SC_SAMP_RTR_N_MAX, 17) + GENERATE_ENUM(RBPERF_RB_SX_QUAD_RTR_N, 18) + GENERATE_ENUM(RBPERF_RB_SX_QUAD_RTR_N_MAX, 19) + GENERATE_ENUM(RBPERF_RB_SX_COLOR_RTR_N, 20) + GENERATE_ENUM(RBPERF_RB_SX_COLOR_RTR_N_MAX, 21) + GENERATE_ENUM(RBPERF_RB_SC_SAMP_LZ_BUSY, 22) + GENERATE_ENUM(RBPERF_RB_SC_SAMP_LZ_BUSY_MAX, 23) + GENERATE_ENUM(RBPERF_ZXP_STALL, 24) + GENERATE_ENUM(RBPERF_ZXP_STALL_MAX, 25) + GENERATE_ENUM(RBPERF_EVENT_PENDING, 26) + GENERATE_ENUM(RBPERF_EVENT_PENDING_MAX, 27) + GENERATE_ENUM(RBPERF_RB_MH_VALID, 28) + GENERATE_ENUM(RBPERF_RB_MH_VALID_MAX, 29) + GENERATE_ENUM(RBPERF_SX_RB_QUAD_SEND, 30) + GENERATE_ENUM(RBPERF_SX_RB_COLOR_SEND, 31) + GENERATE_ENUM(RBPERF_SC_RB_TILE_SEND, 32) + GENERATE_ENUM(RBPERF_SC_RB_SAMPLE_SEND, 33) + GENERATE_ENUM(RBPERF_SX_RB_MEM_EXPORT, 34) + GENERATE_ENUM(RBPERF_SX_RB_QUAD_EVENT, 35) + GENERATE_ENUM(RBPERF_SC_RB_TILE_EVENT_FILTERED, 36) + GENERATE_ENUM(RBPERF_SC_RB_TILE_EVENT_ALL, 37) + GENERATE_ENUM(RBPERF_RB_SC_EZ_SEND, 38) + GENERATE_ENUM(RBPERF_RB_SX_INDEX_SEND, 39) + GENERATE_ENUM(RBPERF_GMEM_INTFO_RD, 40) + GENERATE_ENUM(RBPERF_GMEM_INTF1_RD, 41) + GENERATE_ENUM(RBPERF_GMEM_INTFO_WR, 42) + GENERATE_ENUM(RBPERF_GMEM_INTF1_WR, 43) + GENERATE_ENUM(RBPERF_RB_CP_CONTEXT_DONE, 44) + GENERATE_ENUM(RBPERF_RB_CP_CACHE_FLUSH, 45) + GENERATE_ENUM(RBPERF_ZPASS_DONE, 46) + GENERATE_ENUM(RBPERF_ZCMD_VALID, 47) + GENERATE_ENUM(RBPERF_CCMD_VALID, 48) + GENERATE_ENUM(RBPERF_ACCUM_GRANT, 49) + GENERATE_ENUM(RBPERF_ACCUM_C0_GRANT, 50) + GENERATE_ENUM(RBPERF_ACCUM_C1_GRANT, 51) + GENERATE_ENUM(RBPERF_ACCUM_FULL_BE_WR, 52) + GENERATE_ENUM(RBPERF_ACCUM_REQUEST_NO_GRANT, 53) + GENERATE_ENUM(RBPERF_ACCUM_TIMEOUT_PULSE, 54) + GENERATE_ENUM(RBPERF_ACCUM_LIN_TIMEOUT_PULSE, 55) + GENERATE_ENUM(RBPERF_ACCUM_CAM_HIT_FLUSHING, 56) +END_ENUMTYPE(RB_PERFCNT_SELECT) + +START_ENUMTYPE(DepthFormat) + GENERATE_ENUM(DEPTH_24_8, 22) + GENERATE_ENUM(DEPTH_24_8_FLOAT, 23) + GENERATE_ENUM(DEPTH_16, 24) +END_ENUMTYPE(DepthFormat) + +START_ENUMTYPE(SurfaceSwap) + GENERATE_ENUM(SWAP_LOWRED, 0) + GENERATE_ENUM(SWAP_LOWBLUE, 1) +END_ENUMTYPE(SurfaceSwap) + +START_ENUMTYPE(DepthArray) + GENERATE_ENUM(ARRAY_2D_ALT_DEPTH, 0) + GENERATE_ENUM(ARRAY_2D_DEPTH, 1) +END_ENUMTYPE(DepthArray) + +START_ENUMTYPE(ColorArray) + GENERATE_ENUM(ARRAY_2D_ALT_COLOR, 0) + GENERATE_ENUM(ARRAY_2D_COLOR, 1) + GENERATE_ENUM(ARRAY_3D_SLICE_COLOR, 3) +END_ENUMTYPE(ColorArray) + +START_ENUMTYPE(ColorFormat) + GENERATE_ENUM(COLOR_8, 2) + GENERATE_ENUM(COLOR_1_5_5_5, 3) + GENERATE_ENUM(COLOR_5_6_5, 4) + GENERATE_ENUM(COLOR_6_5_5, 5) + GENERATE_ENUM(COLOR_8_8_8_8, 6) + GENERATE_ENUM(COLOR_2_10_10_10, 7) + GENERATE_ENUM(COLOR_8_A, 8) + GENERATE_ENUM(COLOR_8_B, 9) + GENERATE_ENUM(COLOR_8_8, 10) + GENERATE_ENUM(COLOR_8_8_8, 11) + GENERATE_ENUM(COLOR_8_8_8_8_A, 14) + GENERATE_ENUM(COLOR_4_4_4_4, 15) + GENERATE_ENUM(COLOR_10_11_11, 16) + GENERATE_ENUM(COLOR_11_11_10, 17) + GENERATE_ENUM(COLOR_16, 24) + GENERATE_ENUM(COLOR_16_16, 25) + GENERATE_ENUM(COLOR_16_16_16_16, 26) + GENERATE_ENUM(COLOR_16_FLOAT, 30) + GENERATE_ENUM(COLOR_16_16_FLOAT, 31) + GENERATE_ENUM(COLOR_16_16_16_16_FLOAT, 32) + GENERATE_ENUM(COLOR_32_FLOAT, 36) + GENERATE_ENUM(COLOR_32_32_FLOAT, 37) + GENERATE_ENUM(COLOR_32_32_32_32_FLOAT, 38) + GENERATE_ENUM(COLOR_2_3_3, 39) +END_ENUMTYPE(ColorFormat) + +START_ENUMTYPE(SurfaceNumber) + GENERATE_ENUM(NUMBER_UREPEAT, 0) + GENERATE_ENUM(NUMBER_SREPEAT, 1) + GENERATE_ENUM(NUMBER_UINTEGER, 2) + GENERATE_ENUM(NUMBER_SINTEGER, 3) + GENERATE_ENUM(NUMBER_GAMMA, 4) + GENERATE_ENUM(NUMBER_FIXED, 5) + GENERATE_ENUM(NUMBER_FLOAT, 7) +END_ENUMTYPE(SurfaceNumber) + +START_ENUMTYPE(SurfaceFormat) + GENERATE_ENUM(FMT_1_REVERSE, 0) + GENERATE_ENUM(FMT_1, 1) + GENERATE_ENUM(FMT_8, 2) + GENERATE_ENUM(FMT_1_5_5_5, 3) + GENERATE_ENUM(FMT_5_6_5, 4) + GENERATE_ENUM(FMT_6_5_5, 5) + GENERATE_ENUM(FMT_8_8_8_8, 6) + GENERATE_ENUM(FMT_2_10_10_10, 7) + GENERATE_ENUM(FMT_8_A, 8) + GENERATE_ENUM(FMT_8_B, 9) + GENERATE_ENUM(FMT_8_8, 10) + GENERATE_ENUM(FMT_Cr_Y1_Cb_Y0, 11) + GENERATE_ENUM(FMT_Y1_Cr_Y0_Cb, 12) + GENERATE_ENUM(FMT_5_5_5_1, 13) + GENERATE_ENUM(FMT_8_8_8_8_A, 14) + GENERATE_ENUM(FMT_4_4_4_4, 15) + GENERATE_ENUM(FMT_8_8_8, 16) + GENERATE_ENUM(FMT_DXT1, 18) + GENERATE_ENUM(FMT_DXT2_3, 19) + GENERATE_ENUM(FMT_DXT4_5, 20) + GENERATE_ENUM(FMT_10_10_10_2, 21) + GENERATE_ENUM(FMT_24_8, 22) + GENERATE_ENUM(FMT_16, 24) + GENERATE_ENUM(FMT_16_16, 25) + GENERATE_ENUM(FMT_16_16_16_16, 26) + GENERATE_ENUM(FMT_16_EXPAND, 27) + GENERATE_ENUM(FMT_16_16_EXPAND, 28) + GENERATE_ENUM(FMT_16_16_16_16_EXPAND, 29) + GENERATE_ENUM(FMT_16_FLOAT, 30) + GENERATE_ENUM(FMT_16_16_FLOAT, 31) + GENERATE_ENUM(FMT_16_16_16_16_FLOAT, 32) + GENERATE_ENUM(FMT_32, 33) + GENERATE_ENUM(FMT_32_32, 34) + GENERATE_ENUM(FMT_32_32_32_32, 35) + GENERATE_ENUM(FMT_32_FLOAT, 36) + GENERATE_ENUM(FMT_32_32_FLOAT, 37) + GENERATE_ENUM(FMT_32_32_32_32_FLOAT, 38) + GENERATE_ENUM(FMT_ATI_TC_RGB, 39) + GENERATE_ENUM(FMT_ATI_TC_RGBA, 40) + GENERATE_ENUM(FMT_ATI_TC_555_565_RGB, 41) + GENERATE_ENUM(FMT_ATI_TC_555_565_RGBA, 42) + GENERATE_ENUM(FMT_ATI_TC_RGBA_INTERP, 43) + GENERATE_ENUM(FMT_ATI_TC_555_565_RGBA_INTERP, 44) + GENERATE_ENUM(FMT_ETC1_RGBA_INTERP, 46) + GENERATE_ENUM(FMT_ETC1_RGB, 47) + GENERATE_ENUM(FMT_ETC1_RGBA, 48) + GENERATE_ENUM(FMT_DXN, 49) + GENERATE_ENUM(FMT_2_3_3, 51) + GENERATE_ENUM(FMT_2_10_10_10_AS_16_16_16_16, 54) + GENERATE_ENUM(FMT_10_10_10_2_AS_16_16_16_16, 55) + GENERATE_ENUM(FMT_32_32_32_FLOAT, 57) + GENERATE_ENUM(FMT_DXT3A, 58) + GENERATE_ENUM(FMT_DXT5A, 59) + GENERATE_ENUM(FMT_CTX1, 60) +END_ENUMTYPE(SurfaceFormat) + +START_ENUMTYPE(SurfaceTiling) + GENERATE_ENUM(ARRAY_LINEAR, 0) + GENERATE_ENUM(ARRAY_TILED, 1) +END_ENUMTYPE(SurfaceTiling) + +START_ENUMTYPE(SurfaceArray) + GENERATE_ENUM(ARRAY_1D, 0) + GENERATE_ENUM(ARRAY_2D, 1) + GENERATE_ENUM(ARRAY_3D, 2) + GENERATE_ENUM(ARRAY_3D_SLICE, 3) +END_ENUMTYPE(SurfaceArray) + +START_ENUMTYPE(SurfaceNumberX) + GENERATE_ENUM(NUMBERX_UREPEAT, 0) + GENERATE_ENUM(NUMBERX_SREPEAT, 1) + GENERATE_ENUM(NUMBERX_UINTEGER, 2) + GENERATE_ENUM(NUMBERX_SINTEGER, 3) + GENERATE_ENUM(NUMBERX_FLOAT, 7) +END_ENUMTYPE(SurfaceNumberX) + +START_ENUMTYPE(ColorArrayX) + GENERATE_ENUM(ARRAYX_2D_COLOR, 0) + GENERATE_ENUM(ARRAYX_3D_SLICE_COLOR, 1) +END_ENUMTYPE(ColorArrayX) + + + + +// ************************************************************************** +// These are ones that had to be added in addition to what's generated +// by the autoreg (in CSIM) +// ************************************************************************** +START_ENUMTYPE(DXClipSpaceDef) + GENERATE_ENUM(DXCLIP_OPENGL, 0) + GENERATE_ENUM(DXCLIP_DIRECTX, 1) +END_ENUMTYPE(DXClipSpaceDef) + +START_ENUMTYPE(PixCenter) + GENERATE_ENUM(PIXCENTER_D3D, 0) + GENERATE_ENUM(PIXCENTER_OGL, 1) +END_ENUMTYPE(PixCenter) + +START_ENUMTYPE(RoundMode) + GENERATE_ENUM(TRUNCATE, 0) + GENERATE_ENUM(ROUND, 1) + GENERATE_ENUM(ROUNDTOEVEN, 2) + GENERATE_ENUM(ROUNDTOODD, 3) +END_ENUMTYPE(RoundMode) + +START_ENUMTYPE(QuantMode) + GENERATE_ENUM(ONE_SIXTEENTH, 0) + GENERATE_ENUM(ONE_EIGHTH, 1) + GENERATE_ENUM(ONE_QUARTER, 2) + GENERATE_ENUM(ONE_HALF, 3) + GENERATE_ENUM(ONE, 4) +END_ENUMTYPE(QuantMode) + +START_ENUMTYPE(FrontFace) + GENERATE_ENUM(FRONT_CCW, 0) + GENERATE_ENUM(FRONT_CW, 1) +END_ENUMTYPE(FrontFace) + +START_ENUMTYPE(PolyMode) + GENERATE_ENUM(DISABLED, 0) + GENERATE_ENUM(DUALMODE, 1) +END_ENUMTYPE(PolyMode) + +START_ENUMTYPE(PType) + GENERATE_ENUM(DRAW_POINTS, 0) + GENERATE_ENUM(DRAW_LINES, 1) + GENERATE_ENUM(DRAW_TRIANGLES, 2) +END_ENUMTYPE(PType) + +START_ENUMTYPE(MSAANumSamples) + GENERATE_ENUM(ONE, 0) + GENERATE_ENUM(TWO, 1) + GENERATE_ENUM(FOUR, 3) +END_ENUMTYPE(MSAANumSamples) + +START_ENUMTYPE(PatternBitOrder) + GENERATE_ENUM(LITTLE, 0) + GENERATE_ENUM(BIG, 1) +END_ENUMTYPE(PatternBitOrder) + +START_ENUMTYPE(AutoResetCntl) + GENERATE_ENUM(NEVER, 0) + GENERATE_ENUM(EACHPRIMITIVE, 1) + GENERATE_ENUM(EACHPACKET, 2) +END_ENUMTYPE(AutoResetCntl) + +START_ENUMTYPE(ParamShade) + GENERATE_ENUM(FLAT, 0) + GENERATE_ENUM(GOURAUD, 1) +END_ENUMTYPE(ParamShade) + +START_ENUMTYPE(SamplingPattern) + GENERATE_ENUM(CENTROID, 0) + GENERATE_ENUM(PIXCENTER, 1) +END_ENUMTYPE(SamplingPattern) + +START_ENUMTYPE(MSAASamples) + GENERATE_ENUM(ONE, 0) + GENERATE_ENUM(TWO, 1) + GENERATE_ENUM(FOUR, 2) +END_ENUMTYPE(MSAASamples) + +START_ENUMTYPE(CopySampleSelect) + GENERATE_ENUM(SAMPLE_0, 0) + GENERATE_ENUM(SAMPLE_1, 1) + GENERATE_ENUM(SAMPLE_2, 2) + GENERATE_ENUM(SAMPLE_3, 3) + GENERATE_ENUM(SAMPLE_01, 4) + GENERATE_ENUM(SAMPLE_23, 5) + GENERATE_ENUM(SAMPLE_0123, 6) +END_ENUMTYPE(CopySampleSelect) + + +#undef START_ENUMTYPE +#undef GENERATE_ENUM +#undef END_ENUMTYPE + + diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_genreg.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_genreg.h new file mode 100644 index 000000000000..f7efe31bc8a8 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_genreg.h @@ -0,0 +1,3404 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +START_REGISTER(PA_CL_VPORT_XSCALE) + GENERATE_FIELD(VPORT_XSCALE, float) +END_REGISTER(PA_CL_VPORT_XSCALE) + +START_REGISTER(PA_CL_VPORT_XOFFSET) + GENERATE_FIELD(VPORT_XOFFSET, float) +END_REGISTER(PA_CL_VPORT_XOFFSET) + +START_REGISTER(PA_CL_VPORT_YSCALE) + GENERATE_FIELD(VPORT_YSCALE, float) +END_REGISTER(PA_CL_VPORT_YSCALE) + +START_REGISTER(PA_CL_VPORT_YOFFSET) + GENERATE_FIELD(VPORT_YOFFSET, float) +END_REGISTER(PA_CL_VPORT_YOFFSET) + +START_REGISTER(PA_CL_VPORT_ZSCALE) + GENERATE_FIELD(VPORT_ZSCALE, float) +END_REGISTER(PA_CL_VPORT_ZSCALE) + +START_REGISTER(PA_CL_VPORT_ZOFFSET) + GENERATE_FIELD(VPORT_ZOFFSET, float) +END_REGISTER(PA_CL_VPORT_ZOFFSET) + +START_REGISTER(PA_CL_VTE_CNTL) + GENERATE_FIELD(PERFCOUNTER_REF, bool) + GENERATE_FIELD(VTX_W0_FMT, bool) + GENERATE_FIELD(VTX_Z_FMT, bool) + GENERATE_FIELD(VTX_XY_FMT, bool) + GENERATE_FIELD(VPORT_Z_OFFSET_ENA, bool) + GENERATE_FIELD(VPORT_Z_SCALE_ENA, bool) + GENERATE_FIELD(VPORT_Y_OFFSET_ENA, bool) + GENERATE_FIELD(VPORT_Y_SCALE_ENA, bool) + GENERATE_FIELD(VPORT_X_OFFSET_ENA, bool) + GENERATE_FIELD(VPORT_X_SCALE_ENA, bool) +END_REGISTER(PA_CL_VTE_CNTL) + +START_REGISTER(PA_CL_CLIP_CNTL) + GENERATE_FIELD(W_NAN_RETAIN, bool) + GENERATE_FIELD(Z_NAN_RETAIN, bool) + GENERATE_FIELD(XY_NAN_RETAIN, bool) + GENERATE_FIELD(VTX_KILL_OR, bool) + GENERATE_FIELD(DIS_CLIP_ERR_DETECT, bool) + GENERATE_FIELD(DX_CLIP_SPACE_DEF, DXClipSpaceDef) + GENERATE_FIELD(BOUNDARY_EDGE_FLAG_ENA, bool) + GENERATE_FIELD(CLIP_DISABLE, bool) +END_REGISTER(PA_CL_CLIP_CNTL) + +START_REGISTER(PA_CL_GB_VERT_CLIP_ADJ) + GENERATE_FIELD(DATA_REGISTER, float) +END_REGISTER(PA_CL_GB_VERT_CLIP_ADJ) + +START_REGISTER(PA_CL_GB_VERT_DISC_ADJ) + GENERATE_FIELD(DATA_REGISTER, float) +END_REGISTER(PA_CL_GB_VERT_DISC_ADJ) + +START_REGISTER(PA_CL_GB_HORZ_CLIP_ADJ) + GENERATE_FIELD(DATA_REGISTER, float) +END_REGISTER(PA_CL_GB_HORZ_CLIP_ADJ) + +START_REGISTER(PA_CL_GB_HORZ_DISC_ADJ) + GENERATE_FIELD(DATA_REGISTER, float) +END_REGISTER(PA_CL_GB_HORZ_DISC_ADJ) + +START_REGISTER(PA_CL_ENHANCE) + GENERATE_FIELD(ECO_SPARE0, int) + GENERATE_FIELD(ECO_SPARE1, int) + GENERATE_FIELD(ECO_SPARE2, int) + GENERATE_FIELD(ECO_SPARE3, int) + GENERATE_FIELD(CLIP_VTX_REORDER_ENA, bool) +END_REGISTER(PA_CL_ENHANCE) + +START_REGISTER(PA_SC_ENHANCE) + GENERATE_FIELD(ECO_SPARE0, int) + GENERATE_FIELD(ECO_SPARE1, int) + GENERATE_FIELD(ECO_SPARE2, int) + GENERATE_FIELD(ECO_SPARE3, int) +END_REGISTER(PA_SC_ENHANCE) + +START_REGISTER(PA_SU_VTX_CNTL) + GENERATE_FIELD(QUANT_MODE, QuantMode) + GENERATE_FIELD(ROUND_MODE, RoundMode) + GENERATE_FIELD(PIX_CENTER, PixCenter) +END_REGISTER(PA_SU_VTX_CNTL) + +START_REGISTER(PA_SU_POINT_SIZE) + GENERATE_FIELD(WIDTH, fixed12_4) + GENERATE_FIELD(HEIGHT, fixed12_4) +END_REGISTER(PA_SU_POINT_SIZE) + +START_REGISTER(PA_SU_POINT_MINMAX) + GENERATE_FIELD(MAX_SIZE, fixed12_4) + GENERATE_FIELD(MIN_SIZE, fixed12_4) +END_REGISTER(PA_SU_POINT_MINMAX) + +START_REGISTER(PA_SU_LINE_CNTL) + GENERATE_FIELD(WIDTH, fixed12_4) +END_REGISTER(PA_SU_LINE_CNTL) + +START_REGISTER(PA_SU_FACE_DATA) + GENERATE_FIELD(BASE_ADDR, int) +END_REGISTER(PA_SU_FACE_DATA) + +START_REGISTER(PA_SU_SC_MODE_CNTL) + GENERATE_FIELD(FACE_WRITE_ENABLE, bool) + GENERATE_FIELD(FACE_KILL_ENABLE, bool) + GENERATE_FIELD(ZERO_AREA_FACENESS, bool) + GENERATE_FIELD(WAIT_RB_IDLE_FIRST_TRI_NEW_STATE, bool) + GENERATE_FIELD(WAIT_RB_IDLE_ALL_TRI, bool) + GENERATE_FIELD(QUAD_ORDER_ENABLE, bool) + GENERATE_FIELD(MULTI_PRIM_IB_ENA, bool) + GENERATE_FIELD(PERSP_CORR_DIS, bool) + GENERATE_FIELD(PROVOKING_VTX_LAST, bool) + GENERATE_FIELD(LINE_STIPPLE_ENABLE, bool) + GENERATE_FIELD(VTX_WINDOW_OFFSET_ENABLE, bool) + GENERATE_FIELD(MSAA_ENABLE, bool) + GENERATE_FIELD(POLY_OFFSET_PARA_ENABLE, bool) + GENERATE_FIELD(POLY_OFFSET_BACK_ENABLE, bool) + GENERATE_FIELD(POLY_OFFSET_FRONT_ENABLE, bool) + GENERATE_FIELD(POLYMODE_BACK_PTYPE, PType) + GENERATE_FIELD(POLYMODE_FRONT_PTYPE, PType) + GENERATE_FIELD(POLY_MODE, PolyMode) + GENERATE_FIELD(FACE, FrontFace) + GENERATE_FIELD(CULL_BACK, bool) + GENERATE_FIELD(CULL_FRONT, bool) +END_REGISTER(PA_SU_SC_MODE_CNTL) + +START_REGISTER(PA_SU_POLY_OFFSET_FRONT_SCALE) + GENERATE_FIELD(SCALE, float) +END_REGISTER(PA_SU_POLY_OFFSET_FRONT_SCALE) + +START_REGISTER(PA_SU_POLY_OFFSET_FRONT_OFFSET) + GENERATE_FIELD(OFFSET, float) +END_REGISTER(PA_SU_POLY_OFFSET_FRONT_OFFSET) + +START_REGISTER(PA_SU_POLY_OFFSET_BACK_SCALE) + GENERATE_FIELD(SCALE, float) +END_REGISTER(PA_SU_POLY_OFFSET_BACK_SCALE) + +START_REGISTER(PA_SU_POLY_OFFSET_BACK_OFFSET) + GENERATE_FIELD(OFFSET, float) +END_REGISTER(PA_SU_POLY_OFFSET_BACK_OFFSET) + +START_REGISTER(PA_SU_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, SU_PERFCNT_SELECT) +END_REGISTER(PA_SU_PERFCOUNTER0_SELECT) + +START_REGISTER(PA_SU_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(PA_SU_PERFCOUNTER1_SELECT) + +START_REGISTER(PA_SU_PERFCOUNTER2_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(PA_SU_PERFCOUNTER2_SELECT) + +START_REGISTER(PA_SU_PERFCOUNTER3_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(PA_SU_PERFCOUNTER3_SELECT) + +START_REGISTER(PA_SU_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER0_LOW) + +START_REGISTER(PA_SU_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER0_HI) + +START_REGISTER(PA_SU_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER1_LOW) + +START_REGISTER(PA_SU_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER1_HI) + +START_REGISTER(PA_SU_PERFCOUNTER2_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER2_LOW) + +START_REGISTER(PA_SU_PERFCOUNTER2_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER2_HI) + +START_REGISTER(PA_SU_PERFCOUNTER3_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER3_LOW) + +START_REGISTER(PA_SU_PERFCOUNTER3_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER3_HI) + +START_REGISTER(PA_SC_WINDOW_OFFSET) + GENERATE_FIELD(WINDOW_Y_OFFSET, signedint15) + GENERATE_FIELD(WINDOW_X_OFFSET, signedint15) +END_REGISTER(PA_SC_WINDOW_OFFSET) + +START_REGISTER(PA_SC_AA_CONFIG) + GENERATE_FIELD(MAX_SAMPLE_DIST, int) + GENERATE_FIELD(MSAA_NUM_SAMPLES, MSAANumSamples) +END_REGISTER(PA_SC_AA_CONFIG) + +START_REGISTER(PA_SC_AA_MASK) + GENERATE_FIELD(AA_MASK, hex) +END_REGISTER(PA_SC_AA_MASK) + +START_REGISTER(PA_SC_LINE_STIPPLE) + GENERATE_FIELD(AUTO_RESET_CNTL, AutoResetCntl) + GENERATE_FIELD(PATTERN_BIT_ORDER, PatternBitOrder) + GENERATE_FIELD(REPEAT_COUNT, intMinusOne) + GENERATE_FIELD(LINE_PATTERN, hex) +END_REGISTER(PA_SC_LINE_STIPPLE) + +START_REGISTER(PA_SC_LINE_CNTL) + GENERATE_FIELD(LAST_PIXEL, bool) + GENERATE_FIELD(EXPAND_LINE_WIDTH, bool) + GENERATE_FIELD(USE_BRES_CNTL, bool) + GENERATE_FIELD(BRES_CNTL, int) +END_REGISTER(PA_SC_LINE_CNTL) + +START_REGISTER(PA_SC_WINDOW_SCISSOR_TL) + GENERATE_FIELD(WINDOW_OFFSET_DISABLE, bool) + GENERATE_FIELD(TL_Y, int) + GENERATE_FIELD(TL_X, int) +END_REGISTER(PA_SC_WINDOW_SCISSOR_TL) + +START_REGISTER(PA_SC_WINDOW_SCISSOR_BR) + GENERATE_FIELD(BR_Y, int) + GENERATE_FIELD(BR_X, int) +END_REGISTER(PA_SC_WINDOW_SCISSOR_BR) + +START_REGISTER(PA_SC_SCREEN_SCISSOR_TL) + GENERATE_FIELD(TL_Y, int) + GENERATE_FIELD(TL_X, int) +END_REGISTER(PA_SC_SCREEN_SCISSOR_TL) + +START_REGISTER(PA_SC_SCREEN_SCISSOR_BR) + GENERATE_FIELD(BR_Y, int) + GENERATE_FIELD(BR_X, int) +END_REGISTER(PA_SC_SCREEN_SCISSOR_BR) + +START_REGISTER(PA_SC_VIZ_QUERY) + GENERATE_FIELD(KILL_PIX_POST_EARLY_Z, bool) + GENERATE_FIELD(VIZ_QUERY_ID, int) + GENERATE_FIELD(VIZ_QUERY_ENA, bool) +END_REGISTER(PA_SC_VIZ_QUERY) + +START_REGISTER(PA_SC_VIZ_QUERY_STATUS) + GENERATE_FIELD(STATUS_BITS, hex) +END_REGISTER(PA_SC_VIZ_QUERY_STATUS) + +START_REGISTER(PA_SC_LINE_STIPPLE_STATE) + GENERATE_FIELD(CURRENT_COUNT, int) + GENERATE_FIELD(CURRENT_PTR, int) +END_REGISTER(PA_SC_LINE_STIPPLE_STATE) + +START_REGISTER(PA_SC_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, SC_PERFCNT_SELECT) +END_REGISTER(PA_SC_PERFCOUNTER0_SELECT) + +START_REGISTER(PA_SC_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SC_PERFCOUNTER0_LOW) + +START_REGISTER(PA_SC_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SC_PERFCOUNTER0_HI) + +START_REGISTER(PA_CL_CNTL_STATUS) + GENERATE_FIELD(CL_BUSY, int) +END_REGISTER(PA_CL_CNTL_STATUS) + +START_REGISTER(PA_SU_CNTL_STATUS) + GENERATE_FIELD(SU_BUSY, int) +END_REGISTER(PA_SU_CNTL_STATUS) + +START_REGISTER(PA_SC_CNTL_STATUS) + GENERATE_FIELD(SC_BUSY, int) +END_REGISTER(PA_SC_CNTL_STATUS) + +START_REGISTER(PA_SU_DEBUG_CNTL) + GENERATE_FIELD(SU_DEBUG_INDX, int) +END_REGISTER(PA_SU_DEBUG_CNTL) + +START_REGISTER(PA_SU_DEBUG_DATA) + GENERATE_FIELD(DATA, hex) +END_REGISTER(PA_SU_DEBUG_DATA) + +START_REGISTER(PA_SC_DEBUG_CNTL) + GENERATE_FIELD(SC_DEBUG_INDX, int) +END_REGISTER(PA_SC_DEBUG_CNTL) + +START_REGISTER(PA_SC_DEBUG_DATA) + GENERATE_FIELD(DATA, int) +END_REGISTER(PA_SC_DEBUG_DATA) + +START_REGISTER(GFX_COPY_STATE) + GENERATE_FIELD(SRC_STATE_ID, int) +END_REGISTER(GFX_COPY_STATE) + +START_REGISTER(VGT_DRAW_INITIATOR) + GENERATE_FIELD(NUM_INDICES, uint) + GENERATE_FIELD(GRP_CULL_ENABLE, VGT_DI_GRP_CULL_ENABLE) + GENERATE_FIELD(PRE_FETCH_CULL_ENABLE, VGT_DI_PRE_FETCH_CULL_ENABLE) + GENERATE_FIELD(SMALL_INDEX, VGT_DI_SMALL_INDEX) + GENERATE_FIELD(NOT_EOP, bool) + GENERATE_FIELD(INDEX_SIZE, VGT_DI_INDEX_SIZE) + GENERATE_FIELD(FACENESS_CULL_SELECT, VGT_DI_FACENESS_CULL_SELECT) + GENERATE_FIELD(SOURCE_SELECT, VGT_DI_SOURCE_SELECT) + GENERATE_FIELD(PRIM_TYPE, VGT_DI_PRIM_TYPE) +END_REGISTER(VGT_DRAW_INITIATOR) + +START_REGISTER(VGT_EVENT_INITIATOR) + GENERATE_FIELD(EVENT_TYPE, VGT_EVENT_TYPE) +END_REGISTER(VGT_EVENT_INITIATOR) + +START_REGISTER(VGT_DMA_BASE) + GENERATE_FIELD(BASE_ADDR, uint) +END_REGISTER(VGT_DMA_BASE) + +START_REGISTER(VGT_DMA_SIZE) + GENERATE_FIELD(SWAP_MODE, VGT_DMA_SWAP_MODE) + GENERATE_FIELD(NUM_WORDS, uint) +END_REGISTER(VGT_DMA_SIZE) + +START_REGISTER(VGT_BIN_BASE) + GENERATE_FIELD(BIN_BASE_ADDR, uint) +END_REGISTER(VGT_BIN_BASE) + +START_REGISTER(VGT_BIN_SIZE) + GENERATE_FIELD(FACENESS_RESET, int) + GENERATE_FIELD(FACENESS_FETCH, int) + GENERATE_FIELD(NUM_WORDS, uint) +END_REGISTER(VGT_BIN_SIZE) + +START_REGISTER(VGT_CURRENT_BIN_ID_MIN) + GENERATE_FIELD(GUARD_BAND, int) + GENERATE_FIELD(ROW, int) + GENERATE_FIELD(COLUMN, int) +END_REGISTER(VGT_CURRENT_BIN_ID_MIN) + +START_REGISTER(VGT_CURRENT_BIN_ID_MAX) + GENERATE_FIELD(GUARD_BAND, int) + GENERATE_FIELD(ROW, int) + GENERATE_FIELD(COLUMN, int) +END_REGISTER(VGT_CURRENT_BIN_ID_MAX) + +START_REGISTER(VGT_IMMED_DATA) + GENERATE_FIELD(DATA, hex) +END_REGISTER(VGT_IMMED_DATA) + +START_REGISTER(VGT_MAX_VTX_INDX) + GENERATE_FIELD(MAX_INDX, int) +END_REGISTER(VGT_MAX_VTX_INDX) + +START_REGISTER(VGT_MIN_VTX_INDX) + GENERATE_FIELD(MIN_INDX, int) +END_REGISTER(VGT_MIN_VTX_INDX) + +START_REGISTER(VGT_INDX_OFFSET) + GENERATE_FIELD(INDX_OFFSET, int) +END_REGISTER(VGT_INDX_OFFSET) + +START_REGISTER(VGT_VERTEX_REUSE_BLOCK_CNTL) + GENERATE_FIELD(VTX_REUSE_DEPTH, int) +END_REGISTER(VGT_VERTEX_REUSE_BLOCK_CNTL) + +START_REGISTER(VGT_OUT_DEALLOC_CNTL) + GENERATE_FIELD(DEALLOC_DIST, int) +END_REGISTER(VGT_OUT_DEALLOC_CNTL) + +START_REGISTER(VGT_MULTI_PRIM_IB_RESET_INDX) + GENERATE_FIELD(RESET_INDX, int) +END_REGISTER(VGT_MULTI_PRIM_IB_RESET_INDX) + +START_REGISTER(VGT_ENHANCE) + GENERATE_FIELD(MISC, hex) +END_REGISTER(VGT_ENHANCE) + +START_REGISTER(VGT_VTX_VECT_EJECT_REG) + GENERATE_FIELD(PRIM_COUNT, int) +END_REGISTER(VGT_VTX_VECT_EJECT_REG) + +START_REGISTER(VGT_LAST_COPY_STATE) + GENERATE_FIELD(DST_STATE_ID, int) + GENERATE_FIELD(SRC_STATE_ID, int) +END_REGISTER(VGT_LAST_COPY_STATE) + +START_REGISTER(VGT_DEBUG_CNTL) + GENERATE_FIELD(VGT_DEBUG_INDX, int) +END_REGISTER(VGT_DEBUG_CNTL) + +START_REGISTER(VGT_DEBUG_DATA) + GENERATE_FIELD(DATA, hex) +END_REGISTER(VGT_DEBUG_DATA) + +START_REGISTER(VGT_CNTL_STATUS) + GENERATE_FIELD(VGT_OUT_INDX_BUSY, int) + GENERATE_FIELD(VGT_OUT_BUSY, int) + GENERATE_FIELD(VGT_PT_BUSY, int) + GENERATE_FIELD(VGT_BIN_BUSY, int) + GENERATE_FIELD(VGT_VR_BUSY, int) + GENERATE_FIELD(VGT_GRP_BUSY, int) + GENERATE_FIELD(VGT_DMA_REQ_BUSY, int) + GENERATE_FIELD(VGT_DMA_BUSY, int) + GENERATE_FIELD(VGT_BUSY, int) +END_REGISTER(VGT_CNTL_STATUS) + +START_REGISTER(VGT_CRC_SQ_DATA) + GENERATE_FIELD(CRC, hex) +END_REGISTER(VGT_CRC_SQ_DATA) + +START_REGISTER(VGT_CRC_SQ_CTRL) + GENERATE_FIELD(CRC, hex) +END_REGISTER(VGT_CRC_SQ_CTRL) + +START_REGISTER(VGT_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT) +END_REGISTER(VGT_PERFCOUNTER0_SELECT) + +START_REGISTER(VGT_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT) +END_REGISTER(VGT_PERFCOUNTER1_SELECT) + +START_REGISTER(VGT_PERFCOUNTER2_SELECT) + GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT) +END_REGISTER(VGT_PERFCOUNTER2_SELECT) + +START_REGISTER(VGT_PERFCOUNTER3_SELECT) + GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT) +END_REGISTER(VGT_PERFCOUNTER3_SELECT) + +START_REGISTER(VGT_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER0_LOW) + +START_REGISTER(VGT_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER1_LOW) + +START_REGISTER(VGT_PERFCOUNTER2_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER2_LOW) + +START_REGISTER(VGT_PERFCOUNTER3_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER3_LOW) + +START_REGISTER(VGT_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER0_HI) + +START_REGISTER(VGT_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER1_HI) + +START_REGISTER(VGT_PERFCOUNTER2_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER2_HI) + +START_REGISTER(VGT_PERFCOUNTER3_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER3_HI) + +START_REGISTER(TC_CNTL_STATUS) + GENERATE_FIELD(TC_BUSY, int) + GENERATE_FIELD(TC_L2_HIT_MISS, int) + GENERATE_FIELD(L2_INVALIDATE, int) +END_REGISTER(TC_CNTL_STATUS) + +START_REGISTER(TCR_CHICKEN) + GENERATE_FIELD(SPARE, hex) +END_REGISTER(TCR_CHICKEN) + +START_REGISTER(TCF_CHICKEN) + GENERATE_FIELD(SPARE, hex) +END_REGISTER(TCF_CHICKEN) + +START_REGISTER(TCM_CHICKEN) + GENERATE_FIELD(SPARE, hex) + GENERATE_FIELD(ETC_COLOR_ENDIAN, int) + GENERATE_FIELD(TCO_READ_LATENCY_FIFO_PROG_DEPTH, int) +END_REGISTER(TCM_CHICKEN) + +START_REGISTER(TCR_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCR_PERFCOUNT_SELECT) +END_REGISTER(TCR_PERFCOUNTER0_SELECT) + +START_REGISTER(TCR_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCR_PERFCOUNT_SELECT) +END_REGISTER(TCR_PERFCOUNTER1_SELECT) + +START_REGISTER(TCR_PERFCOUNTER0_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCR_PERFCOUNTER0_HI) + +START_REGISTER(TCR_PERFCOUNTER1_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCR_PERFCOUNTER1_HI) + +START_REGISTER(TCR_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCR_PERFCOUNTER0_LOW) + +START_REGISTER(TCR_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCR_PERFCOUNTER1_LOW) + +START_REGISTER(TP_TC_CLKGATE_CNTL) + GENERATE_FIELD(TC_BUSY_EXTEND, int) + GENERATE_FIELD(TP_BUSY_EXTEND, int) +END_REGISTER(TP_TC_CLKGATE_CNTL) + +START_REGISTER(TPC_CNTL_STATUS) + GENERATE_FIELD(TPC_BUSY, int) + GENERATE_FIELD(TP_SQ_DEC, int) + GENERATE_FIELD(TA_TF_TC_FIFO_REN, int) + GENERATE_FIELD(TA_TF_RTS, int) + GENERATE_FIELD(TA_TB_RTR, int) + GENERATE_FIELD(TA_TB_TT_RTS, int) + GENERATE_FIELD(TA_TB_RTS, int) + GENERATE_FIELD(TW_TA_RTR, int) + GENERATE_FIELD(TW_TA_LAST_RTS, int) + GENERATE_FIELD(TW_TA_TT_RTS, int) + GENERATE_FIELD(TW_TA_RTS, int) + GENERATE_FIELD(TF_TW_RTR, int) + GENERATE_FIELD(TF_TW_STATE_RTS, int) + GENERATE_FIELD(TF_TW_RTS, int) + GENERATE_FIELD(TPC_BLEND_BUSY, int) + GENERATE_FIELD(TPC_OUT_FIFO_BUSY, int) + GENERATE_FIELD(TPC_BLEND_PIPE_BUSY, int) + GENERATE_FIELD(TPC_RR_FIFO_BUSY, int) + GENERATE_FIELD(TPC_ALIGNER_BUSY, int) + GENERATE_FIELD(TPC_ALIGN_FIFO_BUSY, int) + GENERATE_FIELD(TPC_ALIGNER_PIPE_BUSY, int) + GENERATE_FIELD(TPC_WALKER_BUSY, int) + GENERATE_FIELD(TPC_WALK_FIFO_BUSY, int) + GENERATE_FIELD(TPC_WALKER_PIPE_BUSY, int) + GENERATE_FIELD(TPC_FETCH_FIFO_BUSY, int) + GENERATE_FIELD(TPC_STATE_FIFO_BUSY, int) + GENERATE_FIELD(TPC_TC_FIFO_BUSY, int) + GENERATE_FIELD(TPC_INPUT_BUSY, int) +END_REGISTER(TPC_CNTL_STATUS) + +START_REGISTER(TPC_DEBUG0) + GENERATE_FIELD(SQ_TP_WAKEUP, int) + GENERATE_FIELD(TPC_CLK_EN, int) + GENERATE_FIELD(REG_CLK_EN, int) + GENERATE_FIELD(ALIGNER_STATE, int) + GENERATE_FIELD(WALKER_STATE, int) + GENERATE_FIELD(PREV_TC_STATE_VALID, int) + GENERATE_FIELD(ALIGNER_CNTL, int) + GENERATE_FIELD(WALKER_CNTL, int) + GENERATE_FIELD(IC_CTR, int) + GENERATE_FIELD(LOD_CNTL, int) +END_REGISTER(TPC_DEBUG0) + +START_REGISTER(TPC_DEBUG1) + GENERATE_FIELD(UNUSED, int) +END_REGISTER(TPC_DEBUG1) + +START_REGISTER(TPC_CHICKEN) + GENERATE_FIELD(SPARE, int) + GENERATE_FIELD(BLEND_PRECISION, int) +END_REGISTER(TPC_CHICKEN) + +START_REGISTER(TP0_CNTL_STATUS) + GENERATE_FIELD(TP_BUSY, int) + GENERATE_FIELD(TB_TO_RTS, int) + GENERATE_FIELD(TB_TT_TT_RESET, int) + GENERATE_FIELD(TB_TT_RTS, int) + GENERATE_FIELD(TF_TB_TT_RTS, int) + GENERATE_FIELD(TF_TB_RTS, int) + GENERATE_FIELD(AL_TF_TT_RTS, int) + GENERATE_FIELD(AL_TF_RTS, int) + GENERATE_FIELD(FA_AL_TT_RTS, int) + GENERATE_FIELD(FA_AL_RTS, int) + GENERATE_FIELD(TA_FA_TT_RTS, int) + GENERATE_FIELD(TA_FA_RTS, int) + GENERATE_FIELD(FL_TA_RTS, int) + GENERATE_FIELD(LA_FL_RTS, int) + GENERATE_FIELD(LC_LA_RTS, int) + GENERATE_FIELD(IN_LC_RTS, int) + GENERATE_FIELD(TP_OUTPUT_BUSY, int) + GENERATE_FIELD(TP_OUT_FIFO_BUSY, int) + GENERATE_FIELD(TP_BLEND_BUSY, int) + GENERATE_FIELD(TP_HICOLOR_BUSY, int) + GENERATE_FIELD(TP_TT_BUSY, int) + GENERATE_FIELD(TP_CH_BLEND_BUSY, int) + GENERATE_FIELD(TP_FETCH_BUSY, int) + GENERATE_FIELD(TP_RR_FIFO_BUSY, int) + GENERATE_FIELD(TP_TC_FIFO_BUSY, int) + GENERATE_FIELD(TP_ALIGNER_BUSY, int) + GENERATE_FIELD(TP_ALIGN_FIFO_BUSY, int) + GENERATE_FIELD(TP_ADDR_BUSY, int) + GENERATE_FIELD(TP_LOD_FIFO_BUSY, int) + GENERATE_FIELD(TP_LOD_BUSY, int) + GENERATE_FIELD(TP_INPUT_BUSY, int) +END_REGISTER(TP0_CNTL_STATUS) + +START_REGISTER(TP0_DEBUG) + GENERATE_FIELD(Q_ALIGNER_CNTL, int) + GENERATE_FIELD(Q_WALKER_CNTL, int) + GENERATE_FIELD(TP_CLK_EN, int) + GENERATE_FIELD(PERF_CLK_EN, int) + GENERATE_FIELD(REG_CLK_EN, int) + GENERATE_FIELD(FL_TA_ADDRESSER_CNTL, int) + GENERATE_FIELD(Q_SQ_TP_WAKEUP, int) + GENERATE_FIELD(Q_LOD_CNTL, int) +END_REGISTER(TP0_DEBUG) + +START_REGISTER(TP0_CHICKEN) + GENERATE_FIELD(SPARE, int) + GENERATE_FIELD(VFETCH_ADDRESS_MODE, int) + GENERATE_FIELD(TT_MODE, int) +END_REGISTER(TP0_CHICKEN) + +START_REGISTER(TP0_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TP_PERFCOUNT_SELECT) +END_REGISTER(TP0_PERFCOUNTER0_SELECT) + +START_REGISTER(TP0_PERFCOUNTER0_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TP0_PERFCOUNTER0_HI) + +START_REGISTER(TP0_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TP0_PERFCOUNTER0_LOW) + +START_REGISTER(TP0_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, int) +END_REGISTER(TP0_PERFCOUNTER1_SELECT) + +START_REGISTER(TP0_PERFCOUNTER1_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TP0_PERFCOUNTER1_HI) + +START_REGISTER(TP0_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TP0_PERFCOUNTER1_LOW) + +START_REGISTER(TCM_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCM_PERFCOUNT_SELECT) +END_REGISTER(TCM_PERFCOUNTER0_SELECT) + +START_REGISTER(TCM_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCM_PERFCOUNT_SELECT) +END_REGISTER(TCM_PERFCOUNTER1_SELECT) + +START_REGISTER(TCM_PERFCOUNTER0_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCM_PERFCOUNTER0_HI) + +START_REGISTER(TCM_PERFCOUNTER1_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCM_PERFCOUNTER1_HI) + +START_REGISTER(TCM_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCM_PERFCOUNTER0_LOW) + +START_REGISTER(TCM_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCM_PERFCOUNTER1_LOW) + +START_REGISTER(TCF_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER0_SELECT) + +START_REGISTER(TCF_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER1_SELECT) + +START_REGISTER(TCF_PERFCOUNTER2_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER2_SELECT) + +START_REGISTER(TCF_PERFCOUNTER3_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER3_SELECT) + +START_REGISTER(TCF_PERFCOUNTER4_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER4_SELECT) + +START_REGISTER(TCF_PERFCOUNTER5_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER5_SELECT) + +START_REGISTER(TCF_PERFCOUNTER6_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER6_SELECT) + +START_REGISTER(TCF_PERFCOUNTER7_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER7_SELECT) + +START_REGISTER(TCF_PERFCOUNTER8_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER8_SELECT) + +START_REGISTER(TCF_PERFCOUNTER9_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER9_SELECT) + +START_REGISTER(TCF_PERFCOUNTER10_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER10_SELECT) + +START_REGISTER(TCF_PERFCOUNTER11_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER11_SELECT) + +START_REGISTER(TCF_PERFCOUNTER0_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER0_HI) + +START_REGISTER(TCF_PERFCOUNTER1_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER1_HI) + +START_REGISTER(TCF_PERFCOUNTER2_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER2_HI) + +START_REGISTER(TCF_PERFCOUNTER3_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER3_HI) + +START_REGISTER(TCF_PERFCOUNTER4_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER4_HI) + +START_REGISTER(TCF_PERFCOUNTER5_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER5_HI) + +START_REGISTER(TCF_PERFCOUNTER6_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER6_HI) + +START_REGISTER(TCF_PERFCOUNTER7_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER7_HI) + +START_REGISTER(TCF_PERFCOUNTER8_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER8_HI) + +START_REGISTER(TCF_PERFCOUNTER9_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER9_HI) + +START_REGISTER(TCF_PERFCOUNTER10_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER10_HI) + +START_REGISTER(TCF_PERFCOUNTER11_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER11_HI) + +START_REGISTER(TCF_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER0_LOW) + +START_REGISTER(TCF_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER1_LOW) + +START_REGISTER(TCF_PERFCOUNTER2_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER2_LOW) + +START_REGISTER(TCF_PERFCOUNTER3_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER3_LOW) + +START_REGISTER(TCF_PERFCOUNTER4_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER4_LOW) + +START_REGISTER(TCF_PERFCOUNTER5_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER5_LOW) + +START_REGISTER(TCF_PERFCOUNTER6_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER6_LOW) + +START_REGISTER(TCF_PERFCOUNTER7_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER7_LOW) + +START_REGISTER(TCF_PERFCOUNTER8_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER8_LOW) + +START_REGISTER(TCF_PERFCOUNTER9_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER9_LOW) + +START_REGISTER(TCF_PERFCOUNTER10_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER10_LOW) + +START_REGISTER(TCF_PERFCOUNTER11_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER11_LOW) + +START_REGISTER(TCF_DEBUG) + GENERATE_FIELD(tca_rts, int) + GENERATE_FIELD(tca_state_rts, int) + GENERATE_FIELD(not_TPC_rtr, int) + GENERATE_FIELD(TPC_full, int) + GENERATE_FIELD(TP0_full, int) + GENERATE_FIELD(PF0_stall, int) + GENERATE_FIELD(TCA_TCB_stall, int) + GENERATE_FIELD(TCB_miss_stall, int) + GENERATE_FIELD(TCB_ff_stall, int) + GENERATE_FIELD(not_TCB_TCO_rtr, int) + GENERATE_FIELD(not_FG0_rtr, int) + GENERATE_FIELD(TC_MH_send, int) + GENERATE_FIELD(not_MH_TC_rtr, int) +END_REGISTER(TCF_DEBUG) + +START_REGISTER(TCA_FIFO_DEBUG) + GENERATE_FIELD(FW_tpc_rts, int) + GENERATE_FIELD(not_FW_tpc_rtr, int) + GENERATE_FIELD(FW_rts0, int) + GENERATE_FIELD(not_FW_rtr0, int) + GENERATE_FIELD(FW_full, int) + GENERATE_FIELD(load_tp_fifos, int) + GENERATE_FIELD(load_tpc_fifo, int) + GENERATE_FIELD(tpc_full, int) + GENERATE_FIELD(tp0_full, int) +END_REGISTER(TCA_FIFO_DEBUG) + +START_REGISTER(TCA_PROBE_DEBUG) + GENERATE_FIELD(ProbeFilter_stall, int) +END_REGISTER(TCA_PROBE_DEBUG) + +START_REGISTER(TCA_TPC_DEBUG) + GENERATE_FIELD(capture_tca_rts, int) + GENERATE_FIELD(captue_state_rts, int) +END_REGISTER(TCA_TPC_DEBUG) + +START_REGISTER(TCB_CORE_DEBUG) + GENERATE_FIELD(sector_format512, int) + GENERATE_FIELD(sector_format, int) + GENERATE_FIELD(format, int) + GENERATE_FIELD(opcode, int) + GENERATE_FIELD(tiled, int) + GENERATE_FIELD(access512, int) +END_REGISTER(TCB_CORE_DEBUG) + +START_REGISTER(TCB_TAG0_DEBUG) + GENERATE_FIELD(max_misses, int) + GENERATE_FIELD(num_feee_lines, int) + GENERATE_FIELD(miss_stall, int) + GENERATE_FIELD(tag_access_cycle, int) + GENERATE_FIELD(mem_read_cycle, int) +END_REGISTER(TCB_TAG0_DEBUG) + +START_REGISTER(TCB_TAG1_DEBUG) + GENERATE_FIELD(max_misses, int) + GENERATE_FIELD(num_feee_lines, int) + GENERATE_FIELD(miss_stall, int) + GENERATE_FIELD(tag_access_cycle, int) + GENERATE_FIELD(mem_read_cycle, int) +END_REGISTER(TCB_TAG1_DEBUG) + +START_REGISTER(TCB_TAG2_DEBUG) + GENERATE_FIELD(max_misses, int) + GENERATE_FIELD(num_feee_lines, int) + GENERATE_FIELD(miss_stall, int) + GENERATE_FIELD(tag_access_cycle, int) + GENERATE_FIELD(mem_read_cycle, int) +END_REGISTER(TCB_TAG2_DEBUG) + +START_REGISTER(TCB_TAG3_DEBUG) + GENERATE_FIELD(max_misses, int) + GENERATE_FIELD(num_feee_lines, int) + GENERATE_FIELD(miss_stall, int) + GENERATE_FIELD(tag_access_cycle, int) + GENERATE_FIELD(mem_read_cycle, int) +END_REGISTER(TCB_TAG3_DEBUG) + +START_REGISTER(TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG) + GENERATE_FIELD(valid_left_q, int) + GENERATE_FIELD(sector_mask_left_q, int) + GENERATE_FIELD(sector_mask_left_count_q, int) + GENERATE_FIELD(update_left, int) + GENERATE_FIELD(no_sectors_to_go, int) + GENERATE_FIELD(one_sector_to_go_left_q, int) + GENERATE_FIELD(fg0_sends_left, int) + GENERATE_FIELD(left_done, int) +END_REGISTER(TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG) + +START_REGISTER(TCB_FETCH_GEN_WALKER_DEBUG) + GENERATE_FIELD(setquads_to_send, int) + GENERATE_FIELD(busy, int) + GENERATE_FIELD(ff_fg_type512, int) + GENERATE_FIELD(right_eq_left, int) + GENERATE_FIELD(set_sel_left, int) + GENERATE_FIELD(quad_sel_left, int) +END_REGISTER(TCB_FETCH_GEN_WALKER_DEBUG) + +START_REGISTER(TCB_FETCH_GEN_PIPE0_DEBUG) + GENERATE_FIELD(arb_RTR, int) + GENERATE_FIELD(valid_q, int) + GENERATE_FIELD(mc_sel_q, int) + GENERATE_FIELD(ga_busy, int) + GENERATE_FIELD(fgo_busy, int) + GENERATE_FIELD(busy, int) + GENERATE_FIELD(tc_arb_request_type, int) + GENERATE_FIELD(tc_arb_fmsopcode, int) + GENERATE_FIELD(tc_arb_format, int) + GENERATE_FIELD(ga_out_rts, int) + GENERATE_FIELD(tc0_arb_rts, int) +END_REGISTER(TCB_FETCH_GEN_PIPE0_DEBUG) + +START_REGISTER(TCD_INPUT0_DEBUG) + GENERATE_FIELD(ipbuf_busy, int) + GENERATE_FIELD(ipbuf_dxt_send, int) + GENERATE_FIELD(ip_send, int) + GENERATE_FIELD(last_send_q1, int) + GENERATE_FIELD(cnt_q1, int) + GENERATE_FIELD(valid_q1, int) + GENERATE_FIELD(full, int) + GENERATE_FIELD(empty, int) +END_REGISTER(TCD_INPUT0_DEBUG) + +START_REGISTER(TCD_DEGAMMA_DEBUG) + GENERATE_FIELD(dgmm_pstate, int) + GENERATE_FIELD(dgmm_stall, int) + GENERATE_FIELD(dgmm_ctrl_send, int) + GENERATE_FIELD(dgmm_ctrl_last_send, int) + GENERATE_FIELD(dgmm_ctrl_dgmm8, int) + GENERATE_FIELD(dgmm_ftfconv_dgmmen, int) +END_REGISTER(TCD_DEGAMMA_DEBUG) + +START_REGISTER(TCD_DXTMUX_SCTARB_DEBUG) + GENERATE_FIELD(dcmp_mux_send, int) + GENERATE_FIELD(dxtc_dgmmpd_send, int) + GENERATE_FIELD(dxtc_dgmmpd_last_send, int) + GENERATE_FIELD(dxtc_sctrarb_send, int) + GENERATE_FIELD(sctrmx0_sctrarb_rts, int) + GENERATE_FIELD(sctrarb_multcyl_send, int) + GENERATE_FIELD(dxtc_rtr, int) + GENERATE_FIELD(sctrmx_rtr, int) + GENERATE_FIELD(pstate, int) +END_REGISTER(TCD_DXTMUX_SCTARB_DEBUG) + +START_REGISTER(TCD_DXTC_ARB_DEBUG) + GENERATE_FIELD(n0_dxt2_4_types, int) + GENERATE_FIELD(arb_dcmp01_send, int) + GENERATE_FIELD(arb_dcmp01_format, int) + GENERATE_FIELD(arb_dcmp01_cacheline, int) + GENERATE_FIELD(arb_dcmp01_sector, int) + GENERATE_FIELD(arb_dcmp01_cnt, int) + GENERATE_FIELD(arb_dcmp01_last_send, int) + GENERATE_FIELD(pstate, int) + GENERATE_FIELD(n0_stall, int) +END_REGISTER(TCD_DXTC_ARB_DEBUG) + +START_REGISTER(TCD_STALLS_DEBUG) + GENERATE_FIELD(not_incoming_rtr, int) + GENERATE_FIELD(not_mux_dcmp_rtr, int) + GENERATE_FIELD(not_dgmmpd_dxtc_rtr, int) + GENERATE_FIELD(not_dcmp0_arb_rtr, int) + GENERATE_FIELD(not_sctrmx0_sctrarb_rtr, int) + GENERATE_FIELD(not_multcyl_sctrarb_rtr, int) +END_REGISTER(TCD_STALLS_DEBUG) + +START_REGISTER(TCO_STALLS_DEBUG) + GENERATE_FIELD(quad0_TCO_TCB_rtr_d, int) + GENERATE_FIELD(quad0_rl_sg_RTR, int) + GENERATE_FIELD(quad0_sg_crd_RTR, int) +END_REGISTER(TCO_STALLS_DEBUG) + +START_REGISTER(TCO_QUAD0_DEBUG0) + GENERATE_FIELD(busy, int) + GENERATE_FIELD(all_sectors_written_set0, int) + GENERATE_FIELD(all_sectors_written_set1, int) + GENERATE_FIELD(all_sectors_written_set2, int) + GENERATE_FIELD(all_sectors_written_set3, int) + GENERATE_FIELD(cache_read_RTR, int) + GENERATE_FIELD(read_cache_q, int) + GENERATE_FIELD(stageN1_valid_q, int) + GENERATE_FIELD(sg_crd_rts, int) + GENERATE_FIELD(sg_crd_rtr, int) + GENERATE_FIELD(sg_crd_end_of_sample, int) + GENERATE_FIELD(rl_sg_rts, int) + GENERATE_FIELD(rl_sg_rtr, int) + GENERATE_FIELD(rl_sg_end_of_sample, int) + GENERATE_FIELD(rl_sg_sector_format, int) +END_REGISTER(TCO_QUAD0_DEBUG0) + +START_REGISTER(TCO_QUAD0_DEBUG1) + GENERATE_FIELD(TCO_TCB_read_xfc, int) + GENERATE_FIELD(sg_crd_rts, int) + GENERATE_FIELD(sg_crd_rtr, int) + GENERATE_FIELD(rl_sg_rts, int) + GENERATE_FIELD(rl_sg_rtr, int) + GENERATE_FIELD(TCB_TCO_xfc_q, int) + GENERATE_FIELD(TCB_TCO_rtr_d, int) + GENERATE_FIELD(tco_quad_pipe_busy, int) + GENERATE_FIELD(input_quad_busy, int) + GENERATE_FIELD(latency_fifo_busy, int) + GENERATE_FIELD(cache_read_busy, int) + GENERATE_FIELD(fifo_read_ptr, int) + GENERATE_FIELD(fifo_write_ptr, int) + GENERATE_FIELD(write_enable, int) + GENERATE_FIELD(full, int) + GENERATE_FIELD(empty, int) + GENERATE_FIELD(fifo_busy, int) +END_REGISTER(TCO_QUAD0_DEBUG1) + +START_REGISTER(SQ_GPR_MANAGEMENT) + GENERATE_FIELD(REG_SIZE_VTX, int) + GENERATE_FIELD(REG_SIZE_PIX, int) + GENERATE_FIELD(REG_DYNAMIC, int) +END_REGISTER(SQ_GPR_MANAGEMENT) + +START_REGISTER(SQ_FLOW_CONTROL) + GENERATE_FIELD(PS_PREFETCH_COLOR_ALLOC, int) + GENERATE_FIELD(NO_EARLY_THREAD_TERMINATION, int) + GENERATE_FIELD(POS_EXP_PRIORITY, int) + GENERATE_FIELD(NO_CFS_EJECT, int) + GENERATE_FIELD(NO_ARB_EJECT, int) + GENERATE_FIELD(ALU_ARBITRATION_POLICY, int) + GENERATE_FIELD(VC_ARBITRATION_POLICY, int) + GENERATE_FIELD(TEXTURE_ARBITRATION_POLICY, int) + GENERATE_FIELD(NO_CEXEC_OPTIMIZE, int) + GENERATE_FIELD(NO_LOOP_EXIT, int) + GENERATE_FIELD(NO_PV_PS, int) + GENERATE_FIELD(CF_WR_BASE, hex) + GENERATE_FIELD(ONE_ALU, int) + GENERATE_FIELD(ONE_THREAD, int) + GENERATE_FIELD(INPUT_ARBITRATION_POLICY, int) +END_REGISTER(SQ_FLOW_CONTROL) + +START_REGISTER(SQ_INST_STORE_MANAGMENT) + GENERATE_FIELD(INST_BASE_VTX, int) + GENERATE_FIELD(INST_BASE_PIX, int) +END_REGISTER(SQ_INST_STORE_MANAGMENT) + +START_REGISTER(SQ_RESOURCE_MANAGMENT) + GENERATE_FIELD(EXPORT_BUF_ENTRIES, int) + GENERATE_FIELD(PIX_THREAD_BUF_ENTRIES, int) + GENERATE_FIELD(VTX_THREAD_BUF_ENTRIES, int) +END_REGISTER(SQ_RESOURCE_MANAGMENT) + +START_REGISTER(SQ_EO_RT) + GENERATE_FIELD(EO_TSTATE_RT, int) + GENERATE_FIELD(EO_CONSTANTS_RT, int) +END_REGISTER(SQ_EO_RT) + +START_REGISTER(SQ_DEBUG_MISC) + GENERATE_FIELD(DB_WEN_MEMORY_3, int) + GENERATE_FIELD(DB_WEN_MEMORY_2, int) + GENERATE_FIELD(DB_WEN_MEMORY_1, int) + GENERATE_FIELD(DB_WEN_MEMORY_0, int) + GENERATE_FIELD(DB_READ_MEMORY, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(DB_READ_CTX, int) + GENERATE_FIELD(DB_TSTATE_SIZE, int) + GENERATE_FIELD(DB_ALUCST_SIZE, int) +END_REGISTER(SQ_DEBUG_MISC) + +START_REGISTER(SQ_ACTIVITY_METER_CNTL) + GENERATE_FIELD(SPARE, int) + GENERATE_FIELD(THRESHOLD_HIGH, int) + GENERATE_FIELD(THRESHOLD_LOW, int) + GENERATE_FIELD(TIMEBASE, int) +END_REGISTER(SQ_ACTIVITY_METER_CNTL) + +START_REGISTER(SQ_ACTIVITY_METER_STATUS) + GENERATE_FIELD(PERCENT_BUSY, int) +END_REGISTER(SQ_ACTIVITY_METER_STATUS) + +START_REGISTER(SQ_INPUT_ARB_PRIORITY) + GENERATE_FIELD(THRESHOLD, int) + GENERATE_FIELD(SX_AVAIL_SIGN, int) + GENERATE_FIELD(SX_AVAIL_WEIGHT, int) + GENERATE_FIELD(PC_AVAIL_SIGN, int) + GENERATE_FIELD(PC_AVAIL_WEIGHT, int) +END_REGISTER(SQ_INPUT_ARB_PRIORITY) + +START_REGISTER(SQ_THREAD_ARB_PRIORITY) + GENERATE_FIELD(USE_SERIAL_COUNT_THRESHOLD, int) + GENERATE_FIELD(PS_PRIORITIZE_SERIAL, int) + GENERATE_FIELD(VS_PRIORITIZE_SERIAL, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(THRESHOLD, int) + GENERATE_FIELD(SX_AVAIL_SIGN, int) + GENERATE_FIELD(SX_AVAIL_WEIGHT, int) + GENERATE_FIELD(PC_AVAIL_SIGN, int) + GENERATE_FIELD(PC_AVAIL_WEIGHT, int) +END_REGISTER(SQ_THREAD_ARB_PRIORITY) + +START_REGISTER(SQ_VS_WATCHDOG_TIMER) + GENERATE_FIELD(TIMEOUT_COUNT, int) + GENERATE_FIELD(ENABLE, int) +END_REGISTER(SQ_VS_WATCHDOG_TIMER) + +START_REGISTER(SQ_PS_WATCHDOG_TIMER) + GENERATE_FIELD(TIMEOUT_COUNT, int) + GENERATE_FIELD(ENABLE, int) +END_REGISTER(SQ_PS_WATCHDOG_TIMER) + +START_REGISTER(SQ_INT_CNTL) + GENERATE_FIELD(VS_WATCHDOG_MASK, int) + GENERATE_FIELD(PS_WATCHDOG_MASK, int) +END_REGISTER(SQ_INT_CNTL) + +START_REGISTER(SQ_INT_STATUS) + GENERATE_FIELD(VS_WATCHDOG_TIMEOUT, int) + GENERATE_FIELD(PS_WATCHDOG_TIMEOUT, int) +END_REGISTER(SQ_INT_STATUS) + +START_REGISTER(SQ_INT_ACK) + GENERATE_FIELD(VS_WATCHDOG_ACK, int) + GENERATE_FIELD(PS_WATCHDOG_ACK, int) +END_REGISTER(SQ_INT_ACK) + +START_REGISTER(SQ_DEBUG_INPUT_FSM) + GENERATE_FIELD(PC_GPR_SIZE, int) + GENERATE_FIELD(PC_INTERP_CNT, int) + GENERATE_FIELD(PC_AS, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(PC_PISM, int) + GENERATE_FIELD(VC_GPR_LD, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(VC_VSR_LD, int) +END_REGISTER(SQ_DEBUG_INPUT_FSM) + +START_REGISTER(SQ_DEBUG_CONST_MGR_FSM) + GENERATE_FIELD(CNTX1_PIX_EVENT_DONE, int) + GENERATE_FIELD(CNTX1_VTX_EVENT_DONE, int) + GENERATE_FIELD(CNTX0_PIX_EVENT_DONE, int) + GENERATE_FIELD(CNTX0_VTX_EVENT_DONE, int) + GENERATE_FIELD(TEX_CONST_CNTX_VALID, int) + GENERATE_FIELD(ALU_CONST_CNTX_VALID, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(ALU_CONST_EVENT_STATE, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(TEX_CONST_EVENT_STATE, int) +END_REGISTER(SQ_DEBUG_CONST_MGR_FSM) + +START_REGISTER(SQ_DEBUG_TP_FSM) + GENERATE_FIELD(ARB_TR_TP, int) + GENERATE_FIELD(RESERVED5, int) + GENERATE_FIELD(FCS_TP, int) + GENERATE_FIELD(RESERVED4, int) + GENERATE_FIELD(FCR_TP, int) + GENERATE_FIELD(RESERVED3, int) + GENERATE_FIELD(GS_TP, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(TIS_TP, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(IF_TP, int) + GENERATE_FIELD(CF_TP, int) + GENERATE_FIELD(RESERVED0, int) + GENERATE_FIELD(EX_TP, int) +END_REGISTER(SQ_DEBUG_TP_FSM) + +START_REGISTER(SQ_DEBUG_FSM_ALU_0) + GENERATE_FIELD(ARB_TR_ALU, int) + GENERATE_FIELD(RESERVED5, int) + GENERATE_FIELD(ACS_ALU_0, int) + GENERATE_FIELD(RESERVED4, int) + GENERATE_FIELD(AIS_ALU_0, int) + GENERATE_FIELD(RESERVED3, int) + GENERATE_FIELD(DU0_ALU_0, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(DU1_ALU_0, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(IF_ALU_0, int) + GENERATE_FIELD(CF_ALU_0, int) + GENERATE_FIELD(RESERVED0, int) + GENERATE_FIELD(EX_ALU_0, int) +END_REGISTER(SQ_DEBUG_FSM_ALU_0) + +START_REGISTER(SQ_DEBUG_FSM_ALU_1) + GENERATE_FIELD(ARB_TR_ALU, int) + GENERATE_FIELD(RESERVED5, int) + GENERATE_FIELD(ACS_ALU_0, int) + GENERATE_FIELD(RESERVED4, int) + GENERATE_FIELD(AIS_ALU_0, int) + GENERATE_FIELD(RESERVED3, int) + GENERATE_FIELD(DU0_ALU_0, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(DU1_ALU_0, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(IF_ALU_0, int) + GENERATE_FIELD(CF_ALU_0, int) + GENERATE_FIELD(RESERVED0, int) + GENERATE_FIELD(EX_ALU_0, int) +END_REGISTER(SQ_DEBUG_FSM_ALU_1) + +START_REGISTER(SQ_DEBUG_EXP_ALLOC) + GENERATE_FIELD(ALLOC_TBL_BUF_AVAIL, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(EA_BUF_AVAIL, int) + GENERATE_FIELD(COLOR_BUF_AVAIL, int) + GENERATE_FIELD(POS_BUF_AVAIL, int) +END_REGISTER(SQ_DEBUG_EXP_ALLOC) + +START_REGISTER(SQ_DEBUG_PTR_BUFF) + GENERATE_FIELD(VTX_SYNC_CNT, int) + GENERATE_FIELD(EF_EMPTY, int) + GENERATE_FIELD(PRIM_TYPE_POLYGON, int) + GENERATE_FIELD(QUAL_EVENT, int) + GENERATE_FIELD(SC_EVENT_ID, int) + GENERATE_FIELD(EVENT_CONTEXT_ID, int) + GENERATE_FIELD(QUAL_NEW_VECTOR, int) + GENERATE_FIELD(DEALLOC_CNT, int) + GENERATE_FIELD(END_OF_BUFFER, int) +END_REGISTER(SQ_DEBUG_PTR_BUFF) + +START_REGISTER(SQ_DEBUG_GPR_VTX) + GENERATE_FIELD(VTX_FREE, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(VTX_MAX, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(VTX_HEAD_PTR, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(VTX_TAIL_PTR, int) +END_REGISTER(SQ_DEBUG_GPR_VTX) + +START_REGISTER(SQ_DEBUG_GPR_PIX) + GENERATE_FIELD(PIX_FREE, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(PIX_MAX, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(PIX_HEAD_PTR, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(PIX_TAIL_PTR, int) +END_REGISTER(SQ_DEBUG_GPR_PIX) + +START_REGISTER(SQ_DEBUG_TB_STATUS_SEL) + GENERATE_FIELD(DISABLE_STRICT_CTX_SYNC, int) + GENERATE_FIELD(VC_THREAD_BUF_DLY, int) + GENERATE_FIELD(PIX_TB_STATE_MEM_RD_ADDR, int) + GENERATE_FIELD(PIX_TB_STATE_MEM_DW_SEL, int) + GENERATE_FIELD(PIX_TB_STATUS_REG_SEL, int) + GENERATE_FIELD(DEBUG_BUS_TRIGGER_SEL, int) + GENERATE_FIELD(PIX_TB_STATE_MEM_RD_EN, int) + GENERATE_FIELD(VTX_TB_STATE_MEM_RD_EN, int) + GENERATE_FIELD(VTX_TB_STATE_MEM_RD_ADDR, int) + GENERATE_FIELD(VTX_TB_STATE_MEM_DW_SEL, int) + GENERATE_FIELD(VTX_TB_STATUS_REG_SEL, int) +END_REGISTER(SQ_DEBUG_TB_STATUS_SEL) + +START_REGISTER(SQ_DEBUG_VTX_TB_0) + GENERATE_FIELD(BUSY_Q, int) + GENERATE_FIELD(SX_EVENT_FULL, int) + GENERATE_FIELD(NXT_PC_ALLOC_CNT, int) + GENERATE_FIELD(NXT_POS_ALLOC_CNT, int) + GENERATE_FIELD(FULL_CNT_Q, int) + GENERATE_FIELD(TAIL_PTR_Q, int) + GENERATE_FIELD(VTX_HEAD_PTR_Q, int) +END_REGISTER(SQ_DEBUG_VTX_TB_0) + +START_REGISTER(SQ_DEBUG_VTX_TB_1) + GENERATE_FIELD(VS_DONE_PTR, int) +END_REGISTER(SQ_DEBUG_VTX_TB_1) + +START_REGISTER(SQ_DEBUG_VTX_TB_STATUS_REG) + GENERATE_FIELD(VS_STATUS_REG, int) +END_REGISTER(SQ_DEBUG_VTX_TB_STATUS_REG) + +START_REGISTER(SQ_DEBUG_VTX_TB_STATE_MEM) + GENERATE_FIELD(VS_STATE_MEM, int) +END_REGISTER(SQ_DEBUG_VTX_TB_STATE_MEM) + +START_REGISTER(SQ_DEBUG_PIX_TB_0) + GENERATE_FIELD(BUSY, int) + GENERATE_FIELD(NXT_PIX_EXP_CNT, int) + GENERATE_FIELD(NXT_PIX_ALLOC_CNT, int) + GENERATE_FIELD(FULL_CNT, int) + GENERATE_FIELD(TAIL_PTR, int) + GENERATE_FIELD(PIX_HEAD_PTR, int) +END_REGISTER(SQ_DEBUG_PIX_TB_0) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_0) + GENERATE_FIELD(PIX_TB_STATUS_REG_0, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_0) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_1) + GENERATE_FIELD(PIX_TB_STATUS_REG_1, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_1) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_2) + GENERATE_FIELD(PIX_TB_STATUS_REG_2, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_2) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_3) + GENERATE_FIELD(PIX_TB_STATUS_REG_3, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_3) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATE_MEM) + GENERATE_FIELD(PIX_TB_STATE_MEM, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATE_MEM) + +START_REGISTER(SQ_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, SQ_PERFCNT_SELECT) +END_REGISTER(SQ_PERFCOUNTER0_SELECT) + +START_REGISTER(SQ_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(SQ_PERFCOUNTER1_SELECT) + +START_REGISTER(SQ_PERFCOUNTER2_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(SQ_PERFCOUNTER2_SELECT) + +START_REGISTER(SQ_PERFCOUNTER3_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(SQ_PERFCOUNTER3_SELECT) + +START_REGISTER(SQ_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER0_LOW) + +START_REGISTER(SQ_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER0_HI) + +START_REGISTER(SQ_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER1_LOW) + +START_REGISTER(SQ_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER1_HI) + +START_REGISTER(SQ_PERFCOUNTER2_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER2_LOW) + +START_REGISTER(SQ_PERFCOUNTER2_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER2_HI) + +START_REGISTER(SQ_PERFCOUNTER3_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER3_LOW) + +START_REGISTER(SQ_PERFCOUNTER3_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER3_HI) + +START_REGISTER(SX_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, SX_PERFCNT_SELECT) +END_REGISTER(SX_PERFCOUNTER0_SELECT) + +START_REGISTER(SX_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SX_PERFCOUNTER0_LOW) + +START_REGISTER(SX_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SX_PERFCOUNTER0_HI) + +START_REGISTER(SQ_INSTRUCTION_ALU_0) + GENERATE_FIELD(SCALAR_OPCODE, ScalarOpcode) + GENERATE_FIELD(SCALAR_CLAMP, int) + GENERATE_FIELD(VECTOR_CLAMP, int) + GENERATE_FIELD(SCALAR_WRT_MSK, int) + GENERATE_FIELD(VECTOR_WRT_MSK, int) + GENERATE_FIELD(EXPORT_DATA, Exporting) + GENERATE_FIELD(SCALAR_DST_REL, int) + GENERATE_FIELD(SCALAR_RESULT, int) + GENERATE_FIELD(LOW_PRECISION_16B_FP, int) + GENERATE_FIELD(VECTOR_DST_REL, Abs_modifier) + GENERATE_FIELD(VECTOR_RESULT, int) +END_REGISTER(SQ_INSTRUCTION_ALU_0) + +START_REGISTER(SQ_INSTRUCTION_ALU_1) + GENERATE_FIELD(CONST_0_REL_ABS, int) + GENERATE_FIELD(CONST_1_REL_ABS, int) + GENERATE_FIELD(RELATIVE_ADDR, int) + GENERATE_FIELD(PRED_SELECT, PredicateSelect) + GENERATE_FIELD(SRC_A_ARG_MOD, InputModifier) + GENERATE_FIELD(SRC_B_ARG_MOD, InputModifier) + GENERATE_FIELD(SRC_C_ARG_MOD, InputModifier) + GENERATE_FIELD(SRC_A_SWIZZLE_A, SwizzleType) + GENERATE_FIELD(SRC_A_SWIZZLE_B, SwizzleType) + GENERATE_FIELD(SRC_A_SWIZZLE_G, SwizzleType) + GENERATE_FIELD(SRC_A_SWIZZLE_R, SwizzleType) + GENERATE_FIELD(SRC_B_SWIZZLE_A, SwizzleType) + GENERATE_FIELD(SRC_B_SWIZZLE_B, SwizzleType) + GENERATE_FIELD(SRC_B_SWIZZLE_G, SwizzleType) + GENERATE_FIELD(SRC_B_SWIZZLE_R, SwizzleType) + GENERATE_FIELD(SRC_C_SWIZZLE_A, SwizzleType) + GENERATE_FIELD(SRC_C_SWIZZLE_B, SwizzleType) + GENERATE_FIELD(SRC_C_SWIZZLE_G, SwizzleType) + GENERATE_FIELD(SRC_C_SWIZZLE_R, SwizzleType) +END_REGISTER(SQ_INSTRUCTION_ALU_1) + +START_REGISTER(SQ_INSTRUCTION_ALU_2) + GENERATE_FIELD(SRC_A_SEL, OperandSelect0) + GENERATE_FIELD(SRC_B_SEL, OperandSelect0) + GENERATE_FIELD(SRC_C_SEL, OperandSelect0) + GENERATE_FIELD(VECTOR_OPCODE, VectorOpcode) + GENERATE_FIELD(REG_ABS_MOD_A, Abs_modifier) + GENERATE_FIELD(REG_SELECT_A, OperandSelect1) + GENERATE_FIELD(SRC_A_REG_PTR, int) + GENERATE_FIELD(REG_ABS_MOD_B, Abs_modifier) + GENERATE_FIELD(REG_SELECT_B, OperandSelect1) + GENERATE_FIELD(SRC_B_REG_PTR, int) + GENERATE_FIELD(REG_ABS_MOD_C, Abs_modifier) + GENERATE_FIELD(REG_SELECT_C, OperandSelect1) + GENERATE_FIELD(SRC_C_REG_PTR, int) +END_REGISTER(SQ_INSTRUCTION_ALU_2) + +START_REGISTER(SQ_INSTRUCTION_CF_EXEC_0) + GENERATE_FIELD(INST_VC_3, VC_type) + GENERATE_FIELD(INST_VC_2, VC_type) + GENERATE_FIELD(INST_VC_1, VC_type) + GENERATE_FIELD(INST_VC_0, VC_type) + GENERATE_FIELD(INST_SERIAL_5, Instruction_serial) + GENERATE_FIELD(INST_TYPE_5, Ressource_type) + GENERATE_FIELD(INST_SERIAL_4, Instruction_serial) + GENERATE_FIELD(INST_TYPE_4, Ressource_type) + GENERATE_FIELD(INST_SERIAL_3, Instruction_serial) + GENERATE_FIELD(INST_TYPE_3, Ressource_type) + GENERATE_FIELD(INST_SERIAL_2, Instruction_serial) + GENERATE_FIELD(INST_TYPE_2, Ressource_type) + GENERATE_FIELD(INST_SERIAL_1, Instruction_serial) + GENERATE_FIELD(INST_TYPE_1, Ressource_type) + GENERATE_FIELD(INST_SERIAL_0, Instruction_serial) + GENERATE_FIELD(INST_TYPE_0, Ressource_type) + GENERATE_FIELD(YIELD, int) + GENERATE_FIELD(COUNT, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(ADDRESS, int) +END_REGISTER(SQ_INSTRUCTION_CF_EXEC_0) + +START_REGISTER(SQ_INSTRUCTION_CF_EXEC_1) + GENERATE_FIELD(YIELD, int) + GENERATE_FIELD(COUNT, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(CONDITION, int) + GENERATE_FIELD(BOOL_ADDR, int) + GENERATE_FIELD(INST_VC_5, VC_type) + GENERATE_FIELD(INST_VC_4, VC_type) +END_REGISTER(SQ_INSTRUCTION_CF_EXEC_1) + +START_REGISTER(SQ_INSTRUCTION_CF_EXEC_2) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(CONDITION, int) + GENERATE_FIELD(BOOL_ADDR, int) + GENERATE_FIELD(INST_VC_5, VC_type) + GENERATE_FIELD(INST_VC_4, VC_type) + GENERATE_FIELD(INST_VC_3, VC_type) + GENERATE_FIELD(INST_VC_2, VC_type) + GENERATE_FIELD(INST_VC_1, VC_type) + GENERATE_FIELD(INST_VC_0, VC_type) + GENERATE_FIELD(INST_SERIAL_5, Instruction_serial) + GENERATE_FIELD(INST_TYPE_5, Ressource_type) + GENERATE_FIELD(INST_SERIAL_4, Instruction_serial) + GENERATE_FIELD(INST_TYPE_4, Ressource_type) + GENERATE_FIELD(INST_SERIAL_3, Instruction_serial) + GENERATE_FIELD(INST_TYPE_3, Ressource_type) + GENERATE_FIELD(INST_SERIAL_2, Instruction_serial) + GENERATE_FIELD(INST_TYPE_2, Ressource_type) + GENERATE_FIELD(INST_SERIAL_1, Instruction_serial) + GENERATE_FIELD(INST_TYPE_1, Ressource_type) + GENERATE_FIELD(INST_SERIAL_0, Instruction_serial) + GENERATE_FIELD(INST_TYPE_0, Ressource_type) +END_REGISTER(SQ_INSTRUCTION_CF_EXEC_2) + +START_REGISTER(SQ_INSTRUCTION_CF_LOOP_0) + GENERATE_FIELD(RESERVED_1, int) + GENERATE_FIELD(LOOP_ID, int) + GENERATE_FIELD(RESERVED_0, int) + GENERATE_FIELD(ADDRESS, int) +END_REGISTER(SQ_INSTRUCTION_CF_LOOP_0) + +START_REGISTER(SQ_INSTRUCTION_CF_LOOP_1) + GENERATE_FIELD(RESERVED_1, int) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(RESERVED_0, int) +END_REGISTER(SQ_INSTRUCTION_CF_LOOP_1) + +START_REGISTER(SQ_INSTRUCTION_CF_LOOP_2) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(LOOP_ID, int) +END_REGISTER(SQ_INSTRUCTION_CF_LOOP_2) + +START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_0) + GENERATE_FIELD(RESERVED_1, int) + GENERATE_FIELD(PREDICATED_JMP, int) + GENERATE_FIELD(FORCE_CALL, int) + GENERATE_FIELD(RESERVED_0, int) + GENERATE_FIELD(ADDRESS, int) +END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_0) + +START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_1) + GENERATE_FIELD(RESERVED_2, int) + GENERATE_FIELD(FORCE_CALL, int) + GENERATE_FIELD(RESERVED_1, int) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(CONDITION, int) + GENERATE_FIELD(BOOL_ADDR, int) + GENERATE_FIELD(DIRECTION, int) + GENERATE_FIELD(RESERVED_0, int) +END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_1) + +START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_2) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(CONDITION, int) + GENERATE_FIELD(BOOL_ADDR, int) + GENERATE_FIELD(DIRECTION, int) + GENERATE_FIELD(RESERVED, int) +END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_2) + +START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_0) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(SIZE, int) +END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_0) + +START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_1) + GENERATE_FIELD(RESERVED_1, int) + GENERATE_FIELD(SIZE, int) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(ALLOC_MODE, int) + GENERATE_FIELD(BUFFER_SELECT, Allocation_type) + GENERATE_FIELD(NO_SERIAL, int) + GENERATE_FIELD(RESERVED_0, int) +END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_1) + +START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_2) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(ALLOC_MODE, int) + GENERATE_FIELD(BUFFER_SELECT, Allocation_type) + GENERATE_FIELD(NO_SERIAL, int) + GENERATE_FIELD(RESERVED, int) +END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_2) + +START_REGISTER(SQ_INSTRUCTION_TFETCH_0) + GENERATE_FIELD(SRC_SEL_Z, SrcSel) + GENERATE_FIELD(SRC_SEL_Y, SrcSel) + GENERATE_FIELD(SRC_SEL_X, SrcSel) + GENERATE_FIELD(TX_COORD_DENORM, TexCoordDenorm) + GENERATE_FIELD(CONST_INDEX, int) + GENERATE_FIELD(FETCH_VALID_ONLY, int) + GENERATE_FIELD(DST_GPR_AM, Addressmode) + GENERATE_FIELD(DST_GPR, int) + GENERATE_FIELD(SRC_GPR_AM, Addressmode) + GENERATE_FIELD(SRC_GPR, int) + GENERATE_FIELD(OPCODE, TexInstOpcode) +END_REGISTER(SQ_INSTRUCTION_TFETCH_0) + +START_REGISTER(SQ_INSTRUCTION_TFETCH_1) + GENERATE_FIELD(PRED_SELECT, PredSelect) + GENERATE_FIELD(USE_REG_LOD, int) + GENERATE_FIELD(USE_COMP_LOD, int) + GENERATE_FIELD(VOL_MIN_FILTER, VolMinFilter) + GENERATE_FIELD(VOL_MAG_FILTER, VolMagFilter) + GENERATE_FIELD(ARBITRARY_FILTER, ArbitraryFilter) + GENERATE_FIELD(ANISO_FILTER, AnisoFilter) + GENERATE_FIELD(MIP_FILTER, MipFilter) + GENERATE_FIELD(MIN_FILTER, MinFilter) + GENERATE_FIELD(MAG_FILTER, MagFilter) + GENERATE_FIELD(DST_SEL_W, DstSel) + GENERATE_FIELD(DST_SEL_Z, DstSel) + GENERATE_FIELD(DST_SEL_Y, DstSel) + GENERATE_FIELD(DST_SEL_X, DstSel) +END_REGISTER(SQ_INSTRUCTION_TFETCH_1) + +START_REGISTER(SQ_INSTRUCTION_TFETCH_2) + GENERATE_FIELD(PRED_CONDITION, int) + GENERATE_FIELD(OFFSET_Z, int) + GENERATE_FIELD(OFFSET_Y, int) + GENERATE_FIELD(OFFSET_X, int) + GENERATE_FIELD(UNUSED, int) + GENERATE_FIELD(LOD_BIAS, int) + GENERATE_FIELD(SAMPLE_LOCATION, SampleLocation) + GENERATE_FIELD(USE_REG_GRADIENTS, int) +END_REGISTER(SQ_INSTRUCTION_TFETCH_2) + +START_REGISTER(SQ_INSTRUCTION_VFETCH_0) + GENERATE_FIELD(SRC_SEL, int) + GENERATE_FIELD(CONST_INDEX_SEL, int) + GENERATE_FIELD(CONST_INDEX, int) + GENERATE_FIELD(MUST_BE_ONE, int) + GENERATE_FIELD(DST_GPR_AM, int) + GENERATE_FIELD(DST_GPR, int) + GENERATE_FIELD(SRC_GPR_AM, int) + GENERATE_FIELD(SRC_GPR, int) + GENERATE_FIELD(OPCODE, int) +END_REGISTER(SQ_INSTRUCTION_VFETCH_0) + +START_REGISTER(SQ_INSTRUCTION_VFETCH_1) + GENERATE_FIELD(PRED_SELECT, int) + GENERATE_FIELD(EXP_ADJUST_ALL, int) + GENERATE_FIELD(DATA_FORMAT, int) + GENERATE_FIELD(SIGNED_RF_MODE_ALL, int) + GENERATE_FIELD(NUM_FORMAT_ALL, int) + GENERATE_FIELD(FORMAT_COMP_ALL, int) + GENERATE_FIELD(DST_SEL_W, int) + GENERATE_FIELD(DST_SEL_Z, int) + GENERATE_FIELD(DST_SEL_Y, int) + GENERATE_FIELD(DST_SEL_X, int) +END_REGISTER(SQ_INSTRUCTION_VFETCH_1) + +START_REGISTER(SQ_INSTRUCTION_VFETCH_2) + GENERATE_FIELD(PRED_CONDITION, int) + GENERATE_FIELD(OFFSET, int) + GENERATE_FIELD(STRIDE, int) +END_REGISTER(SQ_INSTRUCTION_VFETCH_2) + +START_REGISTER(SQ_CONSTANT_0) + GENERATE_FIELD(RED, float) +END_REGISTER(SQ_CONSTANT_0) + +START_REGISTER(SQ_CONSTANT_1) + GENERATE_FIELD(GREEN, float) +END_REGISTER(SQ_CONSTANT_1) + +START_REGISTER(SQ_CONSTANT_2) + GENERATE_FIELD(BLUE, float) +END_REGISTER(SQ_CONSTANT_2) + +START_REGISTER(SQ_CONSTANT_3) + GENERATE_FIELD(ALPHA, float) +END_REGISTER(SQ_CONSTANT_3) + +START_REGISTER(SQ_FETCH_0) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_0) + +START_REGISTER(SQ_FETCH_1) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_1) + +START_REGISTER(SQ_FETCH_2) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_2) + +START_REGISTER(SQ_FETCH_3) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_3) + +START_REGISTER(SQ_FETCH_4) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_4) + +START_REGISTER(SQ_FETCH_5) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_5) + +START_REGISTER(SQ_CONSTANT_VFETCH_0) + GENERATE_FIELD(BASE_ADDRESS, hex) + GENERATE_FIELD(STATE, int) + GENERATE_FIELD(TYPE, int) +END_REGISTER(SQ_CONSTANT_VFETCH_0) + +START_REGISTER(SQ_CONSTANT_VFETCH_1) + GENERATE_FIELD(LIMIT_ADDRESS, hex) + GENERATE_FIELD(ENDIAN_SWAP, int) +END_REGISTER(SQ_CONSTANT_VFETCH_1) + +START_REGISTER(SQ_CONSTANT_T2) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_CONSTANT_T2) + +START_REGISTER(SQ_CONSTANT_T3) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_CONSTANT_T3) + +START_REGISTER(SQ_CF_BOOLEANS) + GENERATE_FIELD(CF_BOOLEANS_3, int) + GENERATE_FIELD(CF_BOOLEANS_2, int) + GENERATE_FIELD(CF_BOOLEANS_1, int) + GENERATE_FIELD(CF_BOOLEANS_0, int) +END_REGISTER(SQ_CF_BOOLEANS) + +START_REGISTER(SQ_CF_LOOP) + GENERATE_FIELD(CF_LOOP_STEP, int) + GENERATE_FIELD(CF_LOOP_START, int) + GENERATE_FIELD(CF_LOOP_COUNT, int) +END_REGISTER(SQ_CF_LOOP) + +START_REGISTER(SQ_CONSTANT_RT_0) + GENERATE_FIELD(RED, float) +END_REGISTER(SQ_CONSTANT_RT_0) + +START_REGISTER(SQ_CONSTANT_RT_1) + GENERATE_FIELD(GREEN, float) +END_REGISTER(SQ_CONSTANT_RT_1) + +START_REGISTER(SQ_CONSTANT_RT_2) + GENERATE_FIELD(BLUE, float) +END_REGISTER(SQ_CONSTANT_RT_2) + +START_REGISTER(SQ_CONSTANT_RT_3) + GENERATE_FIELD(ALPHA, float) +END_REGISTER(SQ_CONSTANT_RT_3) + +START_REGISTER(SQ_FETCH_RT_0) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_0) + +START_REGISTER(SQ_FETCH_RT_1) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_1) + +START_REGISTER(SQ_FETCH_RT_2) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_2) + +START_REGISTER(SQ_FETCH_RT_3) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_3) + +START_REGISTER(SQ_FETCH_RT_4) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_4) + +START_REGISTER(SQ_FETCH_RT_5) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_5) + +START_REGISTER(SQ_CF_RT_BOOLEANS) + GENERATE_FIELD(CF_BOOLEANS_3, int) + GENERATE_FIELD(CF_BOOLEANS_2, int) + GENERATE_FIELD(CF_BOOLEANS_1, int) + GENERATE_FIELD(CF_BOOLEANS_0, int) +END_REGISTER(SQ_CF_RT_BOOLEANS) + +START_REGISTER(SQ_CF_RT_LOOP) + GENERATE_FIELD(CF_LOOP_STEP, int) + GENERATE_FIELD(CF_LOOP_START, int) + GENERATE_FIELD(CF_LOOP_COUNT, int) +END_REGISTER(SQ_CF_RT_LOOP) + +START_REGISTER(SQ_VS_PROGRAM) + GENERATE_FIELD(SIZE, int) + GENERATE_FIELD(BASE, int) +END_REGISTER(SQ_VS_PROGRAM) + +START_REGISTER(SQ_PS_PROGRAM) + GENERATE_FIELD(SIZE, int) + GENERATE_FIELD(BASE, int) +END_REGISTER(SQ_PS_PROGRAM) + +START_REGISTER(SQ_CF_PROGRAM_SIZE) + GENERATE_FIELD(PS_CF_SIZE, int) + GENERATE_FIELD(VS_CF_SIZE, int) +END_REGISTER(SQ_CF_PROGRAM_SIZE) + +START_REGISTER(SQ_INTERPOLATOR_CNTL) + GENERATE_FIELD(SAMPLING_PATTERN, SamplingPattern) + GENERATE_FIELD(PARAM_SHADE, ParamShade) +END_REGISTER(SQ_INTERPOLATOR_CNTL) + +START_REGISTER(SQ_PROGRAM_CNTL) + GENERATE_FIELD(GEN_INDEX_VTX, int) + GENERATE_FIELD(PS_EXPORT_MODE, int) + GENERATE_FIELD(VS_EXPORT_MODE, VertexMode) + GENERATE_FIELD(VS_EXPORT_COUNT, intMinusOne) + GENERATE_FIELD(GEN_INDEX_PIX, int) + GENERATE_FIELD(PARAM_GEN, int) + GENERATE_FIELD(PS_RESOURCE, int) + GENERATE_FIELD(VS_RESOURCE, int) + GENERATE_FIELD(PS_NUM_REG, intMinusOne) + GENERATE_FIELD(VS_NUM_REG, intMinusOne) +END_REGISTER(SQ_PROGRAM_CNTL) + +START_REGISTER(SQ_WRAPPING_0) + GENERATE_FIELD(PARAM_WRAP_7, hex) + GENERATE_FIELD(PARAM_WRAP_6, hex) + GENERATE_FIELD(PARAM_WRAP_5, hex) + GENERATE_FIELD(PARAM_WRAP_4, hex) + GENERATE_FIELD(PARAM_WRAP_3, hex) + GENERATE_FIELD(PARAM_WRAP_2, hex) + GENERATE_FIELD(PARAM_WRAP_1, hex) + GENERATE_FIELD(PARAM_WRAP_0, hex) +END_REGISTER(SQ_WRAPPING_0) + +START_REGISTER(SQ_WRAPPING_1) + GENERATE_FIELD(PARAM_WRAP_15, hex) + GENERATE_FIELD(PARAM_WRAP_14, hex) + GENERATE_FIELD(PARAM_WRAP_13, hex) + GENERATE_FIELD(PARAM_WRAP_12, hex) + GENERATE_FIELD(PARAM_WRAP_11, hex) + GENERATE_FIELD(PARAM_WRAP_10, hex) + GENERATE_FIELD(PARAM_WRAP_9, hex) + GENERATE_FIELD(PARAM_WRAP_8, hex) +END_REGISTER(SQ_WRAPPING_1) + +START_REGISTER(SQ_VS_CONST) + GENERATE_FIELD(SIZE, int) + GENERATE_FIELD(BASE, int) +END_REGISTER(SQ_VS_CONST) + +START_REGISTER(SQ_PS_CONST) + GENERATE_FIELD(SIZE, int) + GENERATE_FIELD(BASE, int) +END_REGISTER(SQ_PS_CONST) + +START_REGISTER(SQ_CONTEXT_MISC) + GENERATE_FIELD(TX_CACHE_SEL, int) + GENERATE_FIELD(YEILD_OPTIMIZE, int) + GENERATE_FIELD(PERFCOUNTER_REF, int) + GENERATE_FIELD(PARAM_GEN_POS, int) + GENERATE_FIELD(SC_SAMPLE_CNTL, Sample_Cntl) + GENERATE_FIELD(SC_OUTPUT_SCREEN_XY, int) + GENERATE_FIELD(INST_PRED_OPTIMIZE, int) +END_REGISTER(SQ_CONTEXT_MISC) + +START_REGISTER(SQ_CF_RD_BASE) + GENERATE_FIELD(RD_BASE, hex) +END_REGISTER(SQ_CF_RD_BASE) + +START_REGISTER(SQ_DEBUG_MISC_0) + GENERATE_FIELD(DB_PROB_COUNT, int) + GENERATE_FIELD(DB_PROB_ADDR, int) + GENERATE_FIELD(DB_PROB_BREAK, int) + GENERATE_FIELD(DB_PROB_ON, int) +END_REGISTER(SQ_DEBUG_MISC_0) + +START_REGISTER(SQ_DEBUG_MISC_1) + GENERATE_FIELD(DB_BREAK_ADDR, int) + GENERATE_FIELD(DB_INST_COUNT, int) + GENERATE_FIELD(DB_ON_VTX, int) + GENERATE_FIELD(DB_ON_PIX, int) +END_REGISTER(SQ_DEBUG_MISC_1) + +START_REGISTER(MH_ARBITER_CONFIG) + GENERATE_FIELD(PA_CLNT_ENABLE, bool) + GENERATE_FIELD(RB_CLNT_ENABLE, bool) + GENERATE_FIELD(TC_CLNT_ENABLE, bool) + GENERATE_FIELD(VGT_CLNT_ENABLE, bool) + GENERATE_FIELD(CP_CLNT_ENABLE, bool) + GENERATE_FIELD(IN_FLIGHT_LIMIT, int) + GENERATE_FIELD(IN_FLIGHT_LIMIT_ENABLE, bool) + GENERATE_FIELD(TC_ARB_HOLD_ENABLE, bool) + GENERATE_FIELD(TC_REORDER_ENABLE, bool) + GENERATE_FIELD(PAGE_SIZE, int) + GENERATE_FIELD(L2_ARB_CONTROL, int) + GENERATE_FIELD(L1_ARB_HOLD_ENABLE, int) + GENERATE_FIELD(L1_ARB_ENABLE, bool) + GENERATE_FIELD(SAME_PAGE_GRANULARITY, int) + GENERATE_FIELD(SAME_PAGE_LIMIT, int) +END_REGISTER(MH_ARBITER_CONFIG) + +START_REGISTER(MH_CLNT_AXI_ID_REUSE) + GENERATE_FIELD(PAw_ID, int) + GENERATE_FIELD(RESERVED3, int) + GENERATE_FIELD(MMUr_ID, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(RBw_ID, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(CPw_ID, int) +END_REGISTER(MH_CLNT_AXI_ID_REUSE) + +START_REGISTER(MH_INTERRUPT_MASK) + GENERATE_FIELD(MMU_PAGE_FAULT, bool) + GENERATE_FIELD(AXI_WRITE_ERROR, bool) + GENERATE_FIELD(AXI_READ_ERROR, bool) +END_REGISTER(MH_INTERRUPT_MASK) + +START_REGISTER(MH_INTERRUPT_STATUS) + GENERATE_FIELD(MMU_PAGE_FAULT, int) + GENERATE_FIELD(AXI_WRITE_ERROR, int) + GENERATE_FIELD(AXI_READ_ERROR, int) +END_REGISTER(MH_INTERRUPT_STATUS) + +START_REGISTER(MH_INTERRUPT_CLEAR) + GENERATE_FIELD(MMU_PAGE_FAULT, int) + GENERATE_FIELD(AXI_WRITE_ERROR, int) + GENERATE_FIELD(AXI_READ_ERROR, int) +END_REGISTER(MH_INTERRUPT_CLEAR) + +START_REGISTER(MH_AXI_ERROR) + GENERATE_FIELD(AXI_WRITE_ERROR, int) + GENERATE_FIELD(AXI_WRITE_ID, int) + GENERATE_FIELD(AXI_READ_ERROR, int) + GENERATE_FIELD(AXI_READ_ID, int) +END_REGISTER(MH_AXI_ERROR) + +START_REGISTER(MH_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, MhPerfEncode) +END_REGISTER(MH_PERFCOUNTER0_SELECT) + +START_REGISTER(MH_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_SEL, MhPerfEncode) +END_REGISTER(MH_PERFCOUNTER1_SELECT) + +START_REGISTER(MH_PERFCOUNTER0_CONFIG) + GENERATE_FIELD(N_VALUE, int) +END_REGISTER(MH_PERFCOUNTER0_CONFIG) + +START_REGISTER(MH_PERFCOUNTER1_CONFIG) + GENERATE_FIELD(N_VALUE, int) +END_REGISTER(MH_PERFCOUNTER1_CONFIG) + +START_REGISTER(MH_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNTER_LOW, int) +END_REGISTER(MH_PERFCOUNTER0_LOW) + +START_REGISTER(MH_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERF_COUNTER_LOW, int) +END_REGISTER(MH_PERFCOUNTER1_LOW) + +START_REGISTER(MH_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNTER_HI, int) +END_REGISTER(MH_PERFCOUNTER0_HI) + +START_REGISTER(MH_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNTER_HI, int) +END_REGISTER(MH_PERFCOUNTER1_HI) + +START_REGISTER(MH_DEBUG_CTRL) + GENERATE_FIELD(INDEX, int) +END_REGISTER(MH_DEBUG_CTRL) + +START_REGISTER(MH_DEBUG_DATA) + GENERATE_FIELD(DATA, int) +END_REGISTER(MH_DEBUG_DATA) + +START_REGISTER(MH_AXI_HALT_CONTROL) + GENERATE_FIELD(AXI_HALT, bool) +END_REGISTER(MH_AXI_HALT_CONTROL) + +START_REGISTER(MH_MMU_CONFIG) + GENERATE_FIELD(PA_W_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(TC_R_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(VGT_R1_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(VGT_R0_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R4_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R3_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R2_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R1_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R0_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_W_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(RB_W_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(SPLIT_MODE_ENABLE, bool) + GENERATE_FIELD(MMU_ENABLE, bool) +END_REGISTER(MH_MMU_CONFIG) + +START_REGISTER(MH_MMU_VA_RANGE) + GENERATE_FIELD(VA_BASE, int) + GENERATE_FIELD(NUM_64KB_REGIONS, int) +END_REGISTER(MH_MMU_VA_RANGE) + +START_REGISTER(MH_MMU_PT_BASE) + GENERATE_FIELD(PT_BASE, int) +END_REGISTER(MH_MMU_PT_BASE) + +START_REGISTER(MH_MMU_PAGE_FAULT) + GENERATE_FIELD(REQ_VA, int) + GENERATE_FIELD(WRITE_PROTECTION_ERROR, int) + GENERATE_FIELD(READ_PROTECTION_ERROR, int) + GENERATE_FIELD(ADDRESS_OUT_OF_RANGE, int) + GENERATE_FIELD(MPU_ADDRESS_OUT_OF_RANGE, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(AXI_ID, int) + GENERATE_FIELD(CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(OP_TYPE, int) + GENERATE_FIELD(PAGE_FAULT, int) +END_REGISTER(MH_MMU_PAGE_FAULT) + +START_REGISTER(MH_MMU_TRAN_ERROR) + GENERATE_FIELD(TRAN_ERROR, int) +END_REGISTER(MH_MMU_TRAN_ERROR) + +START_REGISTER(MH_MMU_INVALIDATE) + GENERATE_FIELD(INVALIDATE_TC, int) + GENERATE_FIELD(INVALIDATE_ALL, int) +END_REGISTER(MH_MMU_INVALIDATE) + +START_REGISTER(MH_MMU_MPU_BASE) + GENERATE_FIELD(MPU_BASE, int) +END_REGISTER(MH_MMU_MPU_BASE) + +START_REGISTER(MH_MMU_MPU_END) + GENERATE_FIELD(MPU_END, int) +END_REGISTER(MH_MMU_MPU_END) + +START_REGISTER(WAIT_UNTIL) + GENERATE_FIELD(CMDFIFO_ENTRIES, int) + GENERATE_FIELD(WAIT_3D_IDLECLEAN, int) + GENERATE_FIELD(WAIT_2D_IDLECLEAN, int) + GENERATE_FIELD(WAIT_3D_IDLE, int) + GENERATE_FIELD(WAIT_2D_IDLE, int) + GENERATE_FIELD(WAIT_CMDFIFO, int) + GENERATE_FIELD(WAIT_DSPLY_ID2, int) + GENERATE_FIELD(WAIT_DSPLY_ID1, int) + GENERATE_FIELD(WAIT_DSPLY_ID0, int) + GENERATE_FIELD(WAIT_VSYNC, int) + GENERATE_FIELD(WAIT_FE_VSYNC, int) + GENERATE_FIELD(WAIT_RE_VSYNC, int) +END_REGISTER(WAIT_UNTIL) + +START_REGISTER(RBBM_ISYNC_CNTL) + GENERATE_FIELD(ISYNC_CPSCRATCH_IDLEGUI, int) + GENERATE_FIELD(ISYNC_WAIT_IDLEGUI, int) +END_REGISTER(RBBM_ISYNC_CNTL) + +START_REGISTER(RBBM_STATUS) + GENERATE_FIELD(GUI_ACTIVE, int) + GENERATE_FIELD(RB_CNTX_BUSY, int) + GENERATE_FIELD(SQ_CNTX0_BUSY, int) + GENERATE_FIELD(SQ_CNTX17_BUSY, int) + GENERATE_FIELD(VGT_BUSY, int) + GENERATE_FIELD(PA_BUSY, int) + GENERATE_FIELD(SC_CNTX_BUSY, int) + GENERATE_FIELD(TPC_BUSY, int) + GENERATE_FIELD(SX_BUSY, int) + GENERATE_FIELD(MH_COHERENCY_BUSY, int) + GENERATE_FIELD(MH_BUSY, int) + GENERATE_FIELD(CP_NRT_BUSY, int) + GENERATE_FIELD(RBBM_WU_BUSY, int) + GENERATE_FIELD(VGT_BUSY_NO_DMA, int) + GENERATE_FIELD(PFRQ_PENDING, int) + GENERATE_FIELD(CFRQ_PENDING, int) + GENERATE_FIELD(CPRQ_PENDING, int) + GENERATE_FIELD(HIRQ_PENDING, int) + GENERATE_FIELD(TC_BUSY, int) + GENERATE_FIELD(CMDFIFO_AVAIL, int) +END_REGISTER(RBBM_STATUS) + +START_REGISTER(RBBM_DSPLY) + GENERATE_FIELD(DMI_CH4_NUM_BUFS, int) + GENERATE_FIELD(DMI_CH4_SW_CNTL, int) + GENERATE_FIELD(DMI_CH4_USE_BUFID2, int) + GENERATE_FIELD(DMI_CH4_USE_BUFID1, int) + GENERATE_FIELD(DMI_CH4_USE_BUFID0, int) + GENERATE_FIELD(DMI_CH3_NUM_BUFS, int) + GENERATE_FIELD(DMI_CH3_SW_CNTL, int) + GENERATE_FIELD(DMI_CH3_USE_BUFID2, int) + GENERATE_FIELD(DMI_CH3_USE_BUFID1, int) + GENERATE_FIELD(DMI_CH3_USE_BUFID0, int) + GENERATE_FIELD(DMI_CHANNEL_SELECT, int) + GENERATE_FIELD(DMI_CH2_NUM_BUFS, int) + GENERATE_FIELD(DMI_CH2_SW_CNTL, int) + GENERATE_FIELD(DMI_CH2_USE_BUFID2, int) + GENERATE_FIELD(DMI_CH2_USE_BUFID1, int) + GENERATE_FIELD(DMI_CH2_USE_BUFID0, int) + GENERATE_FIELD(DMI_CH1_NUM_BUFS, int) + GENERATE_FIELD(DMI_CH1_SW_CNTL, int) + GENERATE_FIELD(DMI_CH1_USE_BUFID2, int) + GENERATE_FIELD(DMI_CH1_USE_BUFID1, int) + GENERATE_FIELD(DMI_CH1_USE_BUFID0, int) + GENERATE_FIELD(SEL_DMI_VSYNC_VALID, int) + GENERATE_FIELD(SEL_DMI_ACTIVE_BUFID2, int) + GENERATE_FIELD(SEL_DMI_ACTIVE_BUFID1, int) + GENERATE_FIELD(SEL_DMI_ACTIVE_BUFID0, int) +END_REGISTER(RBBM_DSPLY) + +START_REGISTER(RBBM_RENDER_LATEST) + GENERATE_FIELD(DMI_CH4_BUFFER_ID, int) + GENERATE_FIELD(DMI_CH3_BUFFER_ID, int) + GENERATE_FIELD(DMI_CH2_BUFFER_ID, int) + GENERATE_FIELD(DMI_CH1_BUFFER_ID, int) +END_REGISTER(RBBM_RENDER_LATEST) + +START_REGISTER(RBBM_RTL_RELEASE) + GENERATE_FIELD(CHANGELIST, int) +END_REGISTER(RBBM_RTL_RELEASE) + +START_REGISTER(RBBM_PATCH_RELEASE) + GENERATE_FIELD(CUSTOMER_ID, int) + GENERATE_FIELD(PATCH_SELECTION, int) + GENERATE_FIELD(PATCH_REVISION, int) +END_REGISTER(RBBM_PATCH_RELEASE) + +START_REGISTER(RBBM_AUXILIARY_CONFIG) + GENERATE_FIELD(RESERVED, int) +END_REGISTER(RBBM_AUXILIARY_CONFIG) + +START_REGISTER(RBBM_PERIPHID0) + GENERATE_FIELD(PARTNUMBER0, int) +END_REGISTER(RBBM_PERIPHID0) + +START_REGISTER(RBBM_PERIPHID1) + GENERATE_FIELD(DESIGNER0, int) + GENERATE_FIELD(PARTNUMBER1, int) +END_REGISTER(RBBM_PERIPHID1) + +START_REGISTER(RBBM_PERIPHID2) + GENERATE_FIELD(REVISION, int) + GENERATE_FIELD(DESIGNER1, int) +END_REGISTER(RBBM_PERIPHID2) + +START_REGISTER(RBBM_PERIPHID3) + GENERATE_FIELD(CONTINUATION, int) + GENERATE_FIELD(MH_INTERFACE, int) + GENERATE_FIELD(GARB_SLAVE_INTERFACE, int) + GENERATE_FIELD(RBBM_HOST_INTERFACE, int) +END_REGISTER(RBBM_PERIPHID3) + +START_REGISTER(RBBM_CNTL) + GENERATE_FIELD(REGCLK_DEASSERT_TIME, int) + GENERATE_FIELD(READ_TIMEOUT, int) +END_REGISTER(RBBM_CNTL) + +START_REGISTER(RBBM_SKEW_CNTL) + GENERATE_FIELD(SKEW_COUNT, int) + GENERATE_FIELD(SKEW_TOP_THRESHOLD, int) +END_REGISTER(RBBM_SKEW_CNTL) + +START_REGISTER(RBBM_SOFT_RESET) + GENERATE_FIELD(SOFT_RESET_VGT, int) + GENERATE_FIELD(SOFT_RESET_SC, int) + GENERATE_FIELD(SOFT_RESET_CIB, int) + GENERATE_FIELD(SOFT_RESET_SX, int) + GENERATE_FIELD(SOFT_RESET_SQ, int) + GENERATE_FIELD(SOFT_RESET_BC, int) + GENERATE_FIELD(SOFT_RESET_MH, int) + GENERATE_FIELD(SOFT_RESET_PA, int) + GENERATE_FIELD(SOFT_RESET_CP, int) +END_REGISTER(RBBM_SOFT_RESET) + +START_REGISTER(RBBM_PM_OVERRIDE1) + GENERATE_FIELD(MH_TCROQ_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(MH_MMU_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(MH_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(MH_MH_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(RB_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(RB_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SPI_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(CP_G_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(CP_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(CP_G_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TP_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TP_TP_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCF_TCB_READ_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCF_TCB_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCF_TCA_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TPC_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TPC_TPC_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCM_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCM_TCD_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCM_TCM_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCM_TCO_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SX_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SX_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SQ_SQ_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SQ_CONST_MEM_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SQ_REG_FIFOS_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SQ_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SP_V0_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SP_TOP_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SC_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SC_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(RBBM_AHBCLK_PM_OVERRIDE, int) +END_REGISTER(RBBM_PM_OVERRIDE1) + +START_REGISTER(RBBM_PM_OVERRIDE2) + GENERATE_FIELD(GC_GA_GMEM3_PM_OVERRIDE, int) + GENERATE_FIELD(GC_GA_GMEM2_PM_OVERRIDE, int) + GENERATE_FIELD(GC_GA_GMEM1_PM_OVERRIDE, int) + GENERATE_FIELD(GC_GA_GMEM0_PM_OVERRIDE, int) + GENERATE_FIELD(PERM_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(DEBUG_PERF_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(VGT_VGT_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(VGT_FIFOS_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(VGT_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(PA_AG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(PA_PA_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(PA_REG_SCLK_PM_OVERRIDE, int) +END_REGISTER(RBBM_PM_OVERRIDE2) + +START_REGISTER(GC_SYS_IDLE) + GENERATE_FIELD(GC_SYS_IDLE_OVERRIDE, int) + GENERATE_FIELD(GC_SYS_WAIT_DMI_OVERRIDE, int) + GENERATE_FIELD(GC_SYS_URGENT_RAMP_OVERRIDE, int) + GENERATE_FIELD(GC_SYS_WAIT_DMI, int) + GENERATE_FIELD(GC_SYS_URGENT_RAMP, int) + GENERATE_FIELD(GC_SYS_WAIT_DMI_MASK, int) + GENERATE_FIELD(GC_SYS_IDLE_DELAY, int) +END_REGISTER(GC_SYS_IDLE) + +START_REGISTER(NQWAIT_UNTIL) + GENERATE_FIELD(WAIT_GUI_IDLE, int) +END_REGISTER(NQWAIT_UNTIL) + +START_REGISTER(RBBM_DEBUG_OUT) + GENERATE_FIELD(DEBUG_BUS_OUT, int) +END_REGISTER(RBBM_DEBUG_OUT) + +START_REGISTER(RBBM_DEBUG_CNTL) + GENERATE_FIELD(GPIO_BYTE_LANE_ENB, int) + GENERATE_FIELD(GPIO_SUB_BLOCK_SEL, int) + GENERATE_FIELD(GPIO_SUB_BLOCK_ADDR, int) + GENERATE_FIELD(SW_ENABLE, int) + GENERATE_FIELD(SUB_BLOCK_SEL, int) + GENERATE_FIELD(SUB_BLOCK_ADDR, int) +END_REGISTER(RBBM_DEBUG_CNTL) + +START_REGISTER(RBBM_DEBUG) + GENERATE_FIELD(IGNORE_SX_RBBM_BUSY, int) + GENERATE_FIELD(CLIENTS_FOR_NRT_RTR, int) + GENERATE_FIELD(CLIENTS_FOR_NRT_RTR_FOR_HI, int) + GENERATE_FIELD(SQ_RBBM_NRTRTR, int) + GENERATE_FIELD(VGT_RBBM_NRTRTR, int) + GENERATE_FIELD(CP_RBBM_NRTRTR, int) + GENERATE_FIELD(IGNORE_SQ_RBBM_NRTRTR_FOR_HI, int) + GENERATE_FIELD(IGNORE_VGT_RBBM_NRTRTR_FOR_HI, int) + GENERATE_FIELD(IGNORE_CP_RBBM_NRTRTR_FOR_HI, int) + GENERATE_FIELD(IGNORE_RTR_FOR_HI, int) + GENERATE_FIELD(HYSTERESIS_NRT_GUI_ACTIVE, int) + GENERATE_FIELD(IGNORE_CP_SCHED_NQ_HI, int) + GENERATE_FIELD(IGNORE_CP_SCHED_ISYNC, int) + GENERATE_FIELD(IGNORE_CP_SCHED_WU, int) + GENERATE_FIELD(IGNORE_RTR, int) +END_REGISTER(RBBM_DEBUG) + +START_REGISTER(RBBM_READ_ERROR) + GENERATE_FIELD(READ_ERROR, int) + GENERATE_FIELD(READ_REQUESTER, int) + GENERATE_FIELD(READ_ADDRESS, int) +END_REGISTER(RBBM_READ_ERROR) + +START_REGISTER(RBBM_WAIT_IDLE_CLOCKS) + GENERATE_FIELD(WAIT_IDLE_CLOCKS_NRT, int) +END_REGISTER(RBBM_WAIT_IDLE_CLOCKS) + +START_REGISTER(RBBM_INT_CNTL) + GENERATE_FIELD(GUI_IDLE_INT_MASK, int) + GENERATE_FIELD(DISPLAY_UPDATE_INT_MASK, int) + GENERATE_FIELD(RDERR_INT_MASK, int) +END_REGISTER(RBBM_INT_CNTL) + +START_REGISTER(RBBM_INT_STATUS) + GENERATE_FIELD(GUI_IDLE_INT_STAT, int) + GENERATE_FIELD(DISPLAY_UPDATE_INT_STAT, int) + GENERATE_FIELD(RDERR_INT_STAT, int) +END_REGISTER(RBBM_INT_STATUS) + +START_REGISTER(RBBM_INT_ACK) + GENERATE_FIELD(GUI_IDLE_INT_ACK, int) + GENERATE_FIELD(DISPLAY_UPDATE_INT_ACK, int) + GENERATE_FIELD(RDERR_INT_ACK, int) +END_REGISTER(RBBM_INT_ACK) + +START_REGISTER(MASTER_INT_SIGNAL) + GENERATE_FIELD(RBBM_INT_STAT, int) + GENERATE_FIELD(CP_INT_STAT, int) + GENERATE_FIELD(SQ_INT_STAT, int) + GENERATE_FIELD(MH_INT_STAT, int) +END_REGISTER(MASTER_INT_SIGNAL) + +START_REGISTER(RBBM_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_COUNT1_SEL, RBBM_PERFCOUNT1_SEL) +END_REGISTER(RBBM_PERFCOUNTER1_SELECT) + +START_REGISTER(RBBM_PERFCOUNTER1_LO) + GENERATE_FIELD(PERF_COUNT1_LO, int) +END_REGISTER(RBBM_PERFCOUNTER1_LO) + +START_REGISTER(RBBM_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNT1_HI, int) +END_REGISTER(RBBM_PERFCOUNTER1_HI) + +START_REGISTER(CP_RB_BASE) + GENERATE_FIELD(RB_BASE, int) +END_REGISTER(CP_RB_BASE) + +START_REGISTER(CP_RB_CNTL) + GENERATE_FIELD(RB_RPTR_WR_ENA, int) + GENERATE_FIELD(RB_NO_UPDATE, int) + GENERATE_FIELD(RB_POLL_EN, int) + GENERATE_FIELD(BUF_SWAP, int) + GENERATE_FIELD(RB_BLKSZ, int) + GENERATE_FIELD(RB_BUFSZ, int) +END_REGISTER(CP_RB_CNTL) + +START_REGISTER(CP_RB_RPTR_ADDR) + GENERATE_FIELD(RB_RPTR_ADDR, int) + GENERATE_FIELD(RB_RPTR_SWAP, int) +END_REGISTER(CP_RB_RPTR_ADDR) + +START_REGISTER(CP_RB_RPTR) + GENERATE_FIELD(RB_RPTR, int) +END_REGISTER(CP_RB_RPTR) + +START_REGISTER(CP_RB_RPTR_WR) + GENERATE_FIELD(RB_RPTR_WR, int) +END_REGISTER(CP_RB_RPTR_WR) + +START_REGISTER(CP_RB_WPTR) + GENERATE_FIELD(RB_WPTR, int) +END_REGISTER(CP_RB_WPTR) + +START_REGISTER(CP_RB_WPTR_DELAY) + GENERATE_FIELD(PRE_WRITE_LIMIT, int) + GENERATE_FIELD(PRE_WRITE_TIMER, int) +END_REGISTER(CP_RB_WPTR_DELAY) + +START_REGISTER(CP_RB_WPTR_BASE) + GENERATE_FIELD(RB_WPTR_BASE, int) + GENERATE_FIELD(RB_WPTR_SWAP, int) +END_REGISTER(CP_RB_WPTR_BASE) + +START_REGISTER(CP_IB1_BASE) + GENERATE_FIELD(IB1_BASE, int) +END_REGISTER(CP_IB1_BASE) + +START_REGISTER(CP_IB1_BUFSZ) + GENERATE_FIELD(IB1_BUFSZ, int) +END_REGISTER(CP_IB1_BUFSZ) + +START_REGISTER(CP_IB2_BASE) + GENERATE_FIELD(IB2_BASE, int) +END_REGISTER(CP_IB2_BASE) + +START_REGISTER(CP_IB2_BUFSZ) + GENERATE_FIELD(IB2_BUFSZ, int) +END_REGISTER(CP_IB2_BUFSZ) + +START_REGISTER(CP_ST_BASE) + GENERATE_FIELD(ST_BASE, int) +END_REGISTER(CP_ST_BASE) + +START_REGISTER(CP_ST_BUFSZ) + GENERATE_FIELD(ST_BUFSZ, int) +END_REGISTER(CP_ST_BUFSZ) + +START_REGISTER(CP_QUEUE_THRESHOLDS) + GENERATE_FIELD(CSQ_ST_START, int) + GENERATE_FIELD(CSQ_IB2_START, int) + GENERATE_FIELD(CSQ_IB1_START, int) +END_REGISTER(CP_QUEUE_THRESHOLDS) + +START_REGISTER(CP_MEQ_THRESHOLDS) + GENERATE_FIELD(ROQ_END, int) + GENERATE_FIELD(MEQ_END, int) +END_REGISTER(CP_MEQ_THRESHOLDS) + +START_REGISTER(CP_CSQ_AVAIL) + GENERATE_FIELD(CSQ_CNT_IB2, int) + GENERATE_FIELD(CSQ_CNT_IB1, int) + GENERATE_FIELD(CSQ_CNT_RING, int) +END_REGISTER(CP_CSQ_AVAIL) + +START_REGISTER(CP_STQ_AVAIL) + GENERATE_FIELD(STQ_CNT_ST, int) +END_REGISTER(CP_STQ_AVAIL) + +START_REGISTER(CP_MEQ_AVAIL) + GENERATE_FIELD(MEQ_CNT, int) +END_REGISTER(CP_MEQ_AVAIL) + +START_REGISTER(CP_CSQ_RB_STAT) + GENERATE_FIELD(CSQ_WPTR_PRIMARY, int) + GENERATE_FIELD(CSQ_RPTR_PRIMARY, int) +END_REGISTER(CP_CSQ_RB_STAT) + +START_REGISTER(CP_CSQ_IB1_STAT) + GENERATE_FIELD(CSQ_WPTR_INDIRECT1, int) + GENERATE_FIELD(CSQ_RPTR_INDIRECT1, int) +END_REGISTER(CP_CSQ_IB1_STAT) + +START_REGISTER(CP_CSQ_IB2_STAT) + GENERATE_FIELD(CSQ_WPTR_INDIRECT2, int) + GENERATE_FIELD(CSQ_RPTR_INDIRECT2, int) +END_REGISTER(CP_CSQ_IB2_STAT) + +START_REGISTER(CP_NON_PREFETCH_CNTRS) + GENERATE_FIELD(IB2_COUNTER, int) + GENERATE_FIELD(IB1_COUNTER, int) +END_REGISTER(CP_NON_PREFETCH_CNTRS) + +START_REGISTER(CP_STQ_ST_STAT) + GENERATE_FIELD(STQ_WPTR_ST, int) + GENERATE_FIELD(STQ_RPTR_ST, int) +END_REGISTER(CP_STQ_ST_STAT) + +START_REGISTER(CP_MEQ_STAT) + GENERATE_FIELD(MEQ_WPTR, int) + GENERATE_FIELD(MEQ_RPTR, int) +END_REGISTER(CP_MEQ_STAT) + +START_REGISTER(CP_MIU_TAG_STAT) + GENERATE_FIELD(INVALID_RETURN_TAG, int) + GENERATE_FIELD(TAG_17_STAT, int) + GENERATE_FIELD(TAG_16_STAT, int) + GENERATE_FIELD(TAG_15_STAT, int) + GENERATE_FIELD(TAG_14_STAT, int) + GENERATE_FIELD(TAG_13_STAT, int) + GENERATE_FIELD(TAG_12_STAT, int) + GENERATE_FIELD(TAG_11_STAT, int) + GENERATE_FIELD(TAG_10_STAT, int) + GENERATE_FIELD(TAG_9_STAT, int) + GENERATE_FIELD(TAG_8_STAT, int) + GENERATE_FIELD(TAG_7_STAT, int) + GENERATE_FIELD(TAG_6_STAT, int) + GENERATE_FIELD(TAG_5_STAT, int) + GENERATE_FIELD(TAG_4_STAT, int) + GENERATE_FIELD(TAG_3_STAT, int) + GENERATE_FIELD(TAG_2_STAT, int) + GENERATE_FIELD(TAG_1_STAT, int) + GENERATE_FIELD(TAG_0_STAT, int) +END_REGISTER(CP_MIU_TAG_STAT) + +START_REGISTER(CP_CMD_INDEX) + GENERATE_FIELD(CMD_QUEUE_SEL, int) + GENERATE_FIELD(CMD_INDEX, int) +END_REGISTER(CP_CMD_INDEX) + +START_REGISTER(CP_CMD_DATA) + GENERATE_FIELD(CMD_DATA, int) +END_REGISTER(CP_CMD_DATA) + +START_REGISTER(CP_ME_CNTL) + GENERATE_FIELD(PROG_CNT_SIZE, int) + GENERATE_FIELD(ME_BUSY, int) + GENERATE_FIELD(ME_HALT, int) + GENERATE_FIELD(PIX_DEALLOC_FIFO_EMPTY, int) + GENERATE_FIELD(VTX_DEALLOC_FIFO_EMPTY, int) + GENERATE_FIELD(ME_STATMUX, int) +END_REGISTER(CP_ME_CNTL) + +START_REGISTER(CP_ME_STATUS) + GENERATE_FIELD(ME_DEBUG_DATA, int) +END_REGISTER(CP_ME_STATUS) + +START_REGISTER(CP_ME_RAM_WADDR) + GENERATE_FIELD(ME_RAM_WADDR, int) +END_REGISTER(CP_ME_RAM_WADDR) + +START_REGISTER(CP_ME_RAM_RADDR) + GENERATE_FIELD(ME_RAM_RADDR, int) +END_REGISTER(CP_ME_RAM_RADDR) + +START_REGISTER(CP_ME_RAM_DATA) + GENERATE_FIELD(ME_RAM_DATA, int) +END_REGISTER(CP_ME_RAM_DATA) + +START_REGISTER(CP_ME_RDADDR) + GENERATE_FIELD(ME_RDADDR, int) +END_REGISTER(CP_ME_RDADDR) + +START_REGISTER(CP_DEBUG) + GENERATE_FIELD(MIU_WRITE_PACK_DISABLE, int) + GENERATE_FIELD(SIMPLE_ME_FLOW_CONTROL, int) + GENERATE_FIELD(PREFETCH_MATCH_DISABLE, int) + GENERATE_FIELD(DYNAMIC_CLK_DISABLE, int) + GENERATE_FIELD(PREFETCH_PASS_NOPS, int) + GENERATE_FIELD(MIU_128BIT_WRITE_ENABLE, int) + GENERATE_FIELD(PROG_END_PTR_ENABLE, int) + GENERATE_FIELD(PREDICATE_DISABLE, int) + GENERATE_FIELD(CP_DEBUG_UNUSED_22_to_0, int) +END_REGISTER(CP_DEBUG) + +START_REGISTER(SCRATCH_REG0) + GENERATE_FIELD(SCRATCH_REG0, int) +END_REGISTER(SCRATCH_REG0) + +START_REGISTER(SCRATCH_REG1) + GENERATE_FIELD(SCRATCH_REG1, int) +END_REGISTER(SCRATCH_REG1) + +START_REGISTER(SCRATCH_REG2) + GENERATE_FIELD(SCRATCH_REG2, int) +END_REGISTER(SCRATCH_REG2) + +START_REGISTER(SCRATCH_REG3) + GENERATE_FIELD(SCRATCH_REG3, int) +END_REGISTER(SCRATCH_REG3) + +START_REGISTER(SCRATCH_REG4) + GENERATE_FIELD(SCRATCH_REG4, int) +END_REGISTER(SCRATCH_REG4) + +START_REGISTER(SCRATCH_REG5) + GENERATE_FIELD(SCRATCH_REG5, int) +END_REGISTER(SCRATCH_REG5) + +START_REGISTER(SCRATCH_REG6) + GENERATE_FIELD(SCRATCH_REG6, int) +END_REGISTER(SCRATCH_REG6) + +START_REGISTER(SCRATCH_REG7) + GENERATE_FIELD(SCRATCH_REG7, int) +END_REGISTER(SCRATCH_REG7) + +START_REGISTER(SCRATCH_UMSK) + GENERATE_FIELD(SCRATCH_SWAP, int) + GENERATE_FIELD(SCRATCH_UMSK, int) +END_REGISTER(SCRATCH_UMSK) + +START_REGISTER(SCRATCH_ADDR) + GENERATE_FIELD(SCRATCH_ADDR, hex) +END_REGISTER(SCRATCH_ADDR) + +START_REGISTER(CP_ME_VS_EVENT_SRC) + GENERATE_FIELD(VS_DONE_CNTR, int) + GENERATE_FIELD(VS_DONE_SWM, int) +END_REGISTER(CP_ME_VS_EVENT_SRC) + +START_REGISTER(CP_ME_VS_EVENT_ADDR) + GENERATE_FIELD(VS_DONE_ADDR, int) + GENERATE_FIELD(VS_DONE_SWAP, int) +END_REGISTER(CP_ME_VS_EVENT_ADDR) + +START_REGISTER(CP_ME_VS_EVENT_DATA) + GENERATE_FIELD(VS_DONE_DATA, int) +END_REGISTER(CP_ME_VS_EVENT_DATA) + +START_REGISTER(CP_ME_VS_EVENT_ADDR_SWM) + GENERATE_FIELD(VS_DONE_ADDR_SWM, int) + GENERATE_FIELD(VS_DONE_SWAP_SWM, int) +END_REGISTER(CP_ME_VS_EVENT_ADDR_SWM) + +START_REGISTER(CP_ME_VS_EVENT_DATA_SWM) + GENERATE_FIELD(VS_DONE_DATA_SWM, int) +END_REGISTER(CP_ME_VS_EVENT_DATA_SWM) + +START_REGISTER(CP_ME_PS_EVENT_SRC) + GENERATE_FIELD(PS_DONE_CNTR, int) + GENERATE_FIELD(PS_DONE_SWM, int) +END_REGISTER(CP_ME_PS_EVENT_SRC) + +START_REGISTER(CP_ME_PS_EVENT_ADDR) + GENERATE_FIELD(PS_DONE_ADDR, int) + GENERATE_FIELD(PS_DONE_SWAP, int) +END_REGISTER(CP_ME_PS_EVENT_ADDR) + +START_REGISTER(CP_ME_PS_EVENT_DATA) + GENERATE_FIELD(PS_DONE_DATA, int) +END_REGISTER(CP_ME_PS_EVENT_DATA) + +START_REGISTER(CP_ME_PS_EVENT_ADDR_SWM) + GENERATE_FIELD(PS_DONE_ADDR_SWM, int) + GENERATE_FIELD(PS_DONE_SWAP_SWM, int) +END_REGISTER(CP_ME_PS_EVENT_ADDR_SWM) + +START_REGISTER(CP_ME_PS_EVENT_DATA_SWM) + GENERATE_FIELD(PS_DONE_DATA_SWM, int) +END_REGISTER(CP_ME_PS_EVENT_DATA_SWM) + +START_REGISTER(CP_ME_CF_EVENT_SRC) + GENERATE_FIELD(CF_DONE_SRC, int) +END_REGISTER(CP_ME_CF_EVENT_SRC) + +START_REGISTER(CP_ME_CF_EVENT_ADDR) + GENERATE_FIELD(CF_DONE_ADDR, int) + GENERATE_FIELD(CF_DONE_SWAP, int) +END_REGISTER(CP_ME_CF_EVENT_ADDR) + +START_REGISTER(CP_ME_CF_EVENT_DATA) + GENERATE_FIELD(CF_DONE_DATA, int) +END_REGISTER(CP_ME_CF_EVENT_DATA) + +START_REGISTER(CP_ME_NRT_ADDR) + GENERATE_FIELD(NRT_WRITE_ADDR, int) + GENERATE_FIELD(NRT_WRITE_SWAP, int) +END_REGISTER(CP_ME_NRT_ADDR) + +START_REGISTER(CP_ME_NRT_DATA) + GENERATE_FIELD(NRT_WRITE_DATA, int) +END_REGISTER(CP_ME_NRT_DATA) + +START_REGISTER(CP_ME_VS_FETCH_DONE_SRC) + GENERATE_FIELD(VS_FETCH_DONE_CNTR, int) +END_REGISTER(CP_ME_VS_FETCH_DONE_SRC) + +START_REGISTER(CP_ME_VS_FETCH_DONE_ADDR) + GENERATE_FIELD(VS_FETCH_DONE_ADDR, int) + GENERATE_FIELD(VS_FETCH_DONE_SWAP, int) +END_REGISTER(CP_ME_VS_FETCH_DONE_ADDR) + +START_REGISTER(CP_ME_VS_FETCH_DONE_DATA) + GENERATE_FIELD(VS_FETCH_DONE_DATA, int) +END_REGISTER(CP_ME_VS_FETCH_DONE_DATA) + +START_REGISTER(CP_INT_CNTL) + GENERATE_FIELD(RB_INT_MASK, int) + GENERATE_FIELD(IB1_INT_MASK, int) + GENERATE_FIELD(IB2_INT_MASK, int) + GENERATE_FIELD(IB_ERROR_MASK, int) + GENERATE_FIELD(RESERVED_BIT_ERROR_MASK, int) + GENERATE_FIELD(PROTECTED_MODE_ERROR_MASK, int) + GENERATE_FIELD(OPCODE_ERROR_MASK, int) + GENERATE_FIELD(T0_PACKET_IN_IB_MASK, int) + GENERATE_FIELD(SW_INT_MASK, int) +END_REGISTER(CP_INT_CNTL) + +START_REGISTER(CP_INT_STATUS) + GENERATE_FIELD(RB_INT_STAT, int) + GENERATE_FIELD(IB1_INT_STAT, int) + GENERATE_FIELD(IB2_INT_STAT, int) + GENERATE_FIELD(IB_ERROR_STAT, int) + GENERATE_FIELD(RESERVED_BIT_ERROR_STAT, int) + GENERATE_FIELD(PROTECTED_MODE_ERROR_STAT, int) + GENERATE_FIELD(OPCODE_ERROR_STAT, int) + GENERATE_FIELD(T0_PACKET_IN_IB_STAT, int) + GENERATE_FIELD(SW_INT_STAT, int) +END_REGISTER(CP_INT_STATUS) + +START_REGISTER(CP_INT_ACK) + GENERATE_FIELD(RB_INT_ACK, int) + GENERATE_FIELD(IB1_INT_ACK, int) + GENERATE_FIELD(IB2_INT_ACK, int) + GENERATE_FIELD(IB_ERROR_ACK, int) + GENERATE_FIELD(RESERVED_BIT_ERROR_ACK, int) + GENERATE_FIELD(PROTECTED_MODE_ERROR_ACK, int) + GENERATE_FIELD(OPCODE_ERROR_ACK, int) + GENERATE_FIELD(T0_PACKET_IN_IB_ACK, int) + GENERATE_FIELD(SW_INT_ACK, int) +END_REGISTER(CP_INT_ACK) + +START_REGISTER(CP_PFP_UCODE_ADDR) + GENERATE_FIELD(UCODE_ADDR, hex) +END_REGISTER(CP_PFP_UCODE_ADDR) + +START_REGISTER(CP_PFP_UCODE_DATA) + GENERATE_FIELD(UCODE_DATA, hex) +END_REGISTER(CP_PFP_UCODE_DATA) + +START_REGISTER(CP_PERFMON_CNTL) + GENERATE_FIELD(PERFMON_ENABLE_MODE, int) + GENERATE_FIELD(PERFMON_STATE, int) +END_REGISTER(CP_PERFMON_CNTL) + +START_REGISTER(CP_PERFCOUNTER_SELECT) + GENERATE_FIELD(PERFCOUNT_SEL, CP_PERFCOUNT_SEL) +END_REGISTER(CP_PERFCOUNTER_SELECT) + +START_REGISTER(CP_PERFCOUNTER_LO) + GENERATE_FIELD(PERFCOUNT_LO, int) +END_REGISTER(CP_PERFCOUNTER_LO) + +START_REGISTER(CP_PERFCOUNTER_HI) + GENERATE_FIELD(PERFCOUNT_HI, int) +END_REGISTER(CP_PERFCOUNTER_HI) + +START_REGISTER(CP_BIN_MASK_LO) + GENERATE_FIELD(BIN_MASK_LO, int) +END_REGISTER(CP_BIN_MASK_LO) + +START_REGISTER(CP_BIN_MASK_HI) + GENERATE_FIELD(BIN_MASK_HI, int) +END_REGISTER(CP_BIN_MASK_HI) + +START_REGISTER(CP_BIN_SELECT_LO) + GENERATE_FIELD(BIN_SELECT_LO, int) +END_REGISTER(CP_BIN_SELECT_LO) + +START_REGISTER(CP_BIN_SELECT_HI) + GENERATE_FIELD(BIN_SELECT_HI, int) +END_REGISTER(CP_BIN_SELECT_HI) + +START_REGISTER(CP_NV_FLAGS_0) + GENERATE_FIELD(END_RCVD_15, int) + GENERATE_FIELD(DISCARD_15, int) + GENERATE_FIELD(END_RCVD_14, int) + GENERATE_FIELD(DISCARD_14, int) + GENERATE_FIELD(END_RCVD_13, int) + GENERATE_FIELD(DISCARD_13, int) + GENERATE_FIELD(END_RCVD_12, int) + GENERATE_FIELD(DISCARD_12, int) + GENERATE_FIELD(END_RCVD_11, int) + GENERATE_FIELD(DISCARD_11, int) + GENERATE_FIELD(END_RCVD_10, int) + GENERATE_FIELD(DISCARD_10, int) + GENERATE_FIELD(END_RCVD_9, int) + GENERATE_FIELD(DISCARD_9, int) + GENERATE_FIELD(END_RCVD_8, int) + GENERATE_FIELD(DISCARD_8, int) + GENERATE_FIELD(END_RCVD_7, int) + GENERATE_FIELD(DISCARD_7, int) + GENERATE_FIELD(END_RCVD_6, int) + GENERATE_FIELD(DISCARD_6, int) + GENERATE_FIELD(END_RCVD_5, int) + GENERATE_FIELD(DISCARD_5, int) + GENERATE_FIELD(END_RCVD_4, int) + GENERATE_FIELD(DISCARD_4, int) + GENERATE_FIELD(END_RCVD_3, int) + GENERATE_FIELD(DISCARD_3, int) + GENERATE_FIELD(END_RCVD_2, int) + GENERATE_FIELD(DISCARD_2, int) + GENERATE_FIELD(END_RCVD_1, int) + GENERATE_FIELD(DISCARD_1, int) + GENERATE_FIELD(END_RCVD_0, int) + GENERATE_FIELD(DISCARD_0, int) +END_REGISTER(CP_NV_FLAGS_0) + +START_REGISTER(CP_NV_FLAGS_1) + GENERATE_FIELD(END_RCVD_31, int) + GENERATE_FIELD(DISCARD_31, int) + GENERATE_FIELD(END_RCVD_30, int) + GENERATE_FIELD(DISCARD_30, int) + GENERATE_FIELD(END_RCVD_29, int) + GENERATE_FIELD(DISCARD_29, int) + GENERATE_FIELD(END_RCVD_28, int) + GENERATE_FIELD(DISCARD_28, int) + GENERATE_FIELD(END_RCVD_27, int) + GENERATE_FIELD(DISCARD_27, int) + GENERATE_FIELD(END_RCVD_26, int) + GENERATE_FIELD(DISCARD_26, int) + GENERATE_FIELD(END_RCVD_25, int) + GENERATE_FIELD(DISCARD_25, int) + GENERATE_FIELD(END_RCVD_24, int) + GENERATE_FIELD(DISCARD_24, int) + GENERATE_FIELD(END_RCVD_23, int) + GENERATE_FIELD(DISCARD_23, int) + GENERATE_FIELD(END_RCVD_22, int) + GENERATE_FIELD(DISCARD_22, int) + GENERATE_FIELD(END_RCVD_21, int) + GENERATE_FIELD(DISCARD_21, int) + GENERATE_FIELD(END_RCVD_20, int) + GENERATE_FIELD(DISCARD_20, int) + GENERATE_FIELD(END_RCVD_19, int) + GENERATE_FIELD(DISCARD_19, int) + GENERATE_FIELD(END_RCVD_18, int) + GENERATE_FIELD(DISCARD_18, int) + GENERATE_FIELD(END_RCVD_17, int) + GENERATE_FIELD(DISCARD_17, int) + GENERATE_FIELD(END_RCVD_16, int) + GENERATE_FIELD(DISCARD_16, int) +END_REGISTER(CP_NV_FLAGS_1) + +START_REGISTER(CP_NV_FLAGS_2) + GENERATE_FIELD(END_RCVD_47, int) + GENERATE_FIELD(DISCARD_47, int) + GENERATE_FIELD(END_RCVD_46, int) + GENERATE_FIELD(DISCARD_46, int) + GENERATE_FIELD(END_RCVD_45, int) + GENERATE_FIELD(DISCARD_45, int) + GENERATE_FIELD(END_RCVD_44, int) + GENERATE_FIELD(DISCARD_44, int) + GENERATE_FIELD(END_RCVD_43, int) + GENERATE_FIELD(DISCARD_43, int) + GENERATE_FIELD(END_RCVD_42, int) + GENERATE_FIELD(DISCARD_42, int) + GENERATE_FIELD(END_RCVD_41, int) + GENERATE_FIELD(DISCARD_41, int) + GENERATE_FIELD(END_RCVD_40, int) + GENERATE_FIELD(DISCARD_40, int) + GENERATE_FIELD(END_RCVD_39, int) + GENERATE_FIELD(DISCARD_39, int) + GENERATE_FIELD(END_RCVD_38, int) + GENERATE_FIELD(DISCARD_38, int) + GENERATE_FIELD(END_RCVD_37, int) + GENERATE_FIELD(DISCARD_37, int) + GENERATE_FIELD(END_RCVD_36, int) + GENERATE_FIELD(DISCARD_36, int) + GENERATE_FIELD(END_RCVD_35, int) + GENERATE_FIELD(DISCARD_35, int) + GENERATE_FIELD(END_RCVD_34, int) + GENERATE_FIELD(DISCARD_34, int) + GENERATE_FIELD(END_RCVD_33, int) + GENERATE_FIELD(DISCARD_33, int) + GENERATE_FIELD(END_RCVD_32, int) + GENERATE_FIELD(DISCARD_32, int) +END_REGISTER(CP_NV_FLAGS_2) + +START_REGISTER(CP_NV_FLAGS_3) + GENERATE_FIELD(END_RCVD_63, int) + GENERATE_FIELD(DISCARD_63, int) + GENERATE_FIELD(END_RCVD_62, int) + GENERATE_FIELD(DISCARD_62, int) + GENERATE_FIELD(END_RCVD_61, int) + GENERATE_FIELD(DISCARD_61, int) + GENERATE_FIELD(END_RCVD_60, int) + GENERATE_FIELD(DISCARD_60, int) + GENERATE_FIELD(END_RCVD_59, int) + GENERATE_FIELD(DISCARD_59, int) + GENERATE_FIELD(END_RCVD_58, int) + GENERATE_FIELD(DISCARD_58, int) + GENERATE_FIELD(END_RCVD_57, int) + GENERATE_FIELD(DISCARD_57, int) + GENERATE_FIELD(END_RCVD_56, int) + GENERATE_FIELD(DISCARD_56, int) + GENERATE_FIELD(END_RCVD_55, int) + GENERATE_FIELD(DISCARD_55, int) + GENERATE_FIELD(END_RCVD_54, int) + GENERATE_FIELD(DISCARD_54, int) + GENERATE_FIELD(END_RCVD_53, int) + GENERATE_FIELD(DISCARD_53, int) + GENERATE_FIELD(END_RCVD_52, int) + GENERATE_FIELD(DISCARD_52, int) + GENERATE_FIELD(END_RCVD_51, int) + GENERATE_FIELD(DISCARD_51, int) + GENERATE_FIELD(END_RCVD_50, int) + GENERATE_FIELD(DISCARD_50, int) + GENERATE_FIELD(END_RCVD_49, int) + GENERATE_FIELD(DISCARD_49, int) + GENERATE_FIELD(END_RCVD_48, int) + GENERATE_FIELD(DISCARD_48, int) +END_REGISTER(CP_NV_FLAGS_3) + +START_REGISTER(CP_STATE_DEBUG_INDEX) + GENERATE_FIELD(STATE_DEBUG_INDEX, int) +END_REGISTER(CP_STATE_DEBUG_INDEX) + +START_REGISTER(CP_STATE_DEBUG_DATA) + GENERATE_FIELD(STATE_DEBUG_DATA, int) +END_REGISTER(CP_STATE_DEBUG_DATA) + +START_REGISTER(CP_PROG_COUNTER) + GENERATE_FIELD(COUNTER, int) +END_REGISTER(CP_PROG_COUNTER) + +START_REGISTER(CP_STAT) + GENERATE_FIELD(CP_BUSY, int) + GENERATE_FIELD(MIU_WC_TRACK_FIFO_EMPTY, int) + GENERATE_FIELD(ME_WC_BUSY, int) + GENERATE_FIELD(ME_BUSY, int) + GENERATE_FIELD(_3D_BUSY, int) + GENERATE_FIELD(CP_NRT_BUSY, int) + GENERATE_FIELD(MIU_WC_STALL, int) + GENERATE_FIELD(MEQ_INDIRECT2_BUSY, int) + GENERATE_FIELD(MEQ_INDIRECTS_BUSY, int) + GENERATE_FIELD(MEQ_RING_BUSY, int) + GENERATE_FIELD(PFP_BUSY, int) + GENERATE_FIELD(ST_QUEUE_BUSY, int) + GENERATE_FIELD(INDIRECT2_QUEUE_BUSY, int) + GENERATE_FIELD(INDIRECTS_QUEUE_BUSY, int) + GENERATE_FIELD(RING_QUEUE_BUSY, int) + GENERATE_FIELD(CSF_BUSY, int) + GENERATE_FIELD(CSF_ST_BUSY, int) + GENERATE_FIELD(CSF_INDIRECT2_BUSY, int) + GENERATE_FIELD(CSF_INDIRECTS_BUSY, int) + GENERATE_FIELD(CSF_RING_BUSY, int) + GENERATE_FIELD(RCIU_BUSY, int) + GENERATE_FIELD(RBIU_BUSY, int) + GENERATE_FIELD(MIU_RD_RETURN_BUSY, int) + GENERATE_FIELD(MIU_RD_REQ_BUSY, int) + GENERATE_FIELD(MIU_WR_BUSY, int) +END_REGISTER(CP_STAT) + +START_REGISTER(BIOS_0_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_0_SCRATCH) + +START_REGISTER(BIOS_1_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_1_SCRATCH) + +START_REGISTER(BIOS_2_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_2_SCRATCH) + +START_REGISTER(BIOS_3_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_3_SCRATCH) + +START_REGISTER(BIOS_4_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_4_SCRATCH) + +START_REGISTER(BIOS_5_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_5_SCRATCH) + +START_REGISTER(BIOS_6_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_6_SCRATCH) + +START_REGISTER(BIOS_7_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_7_SCRATCH) + +START_REGISTER(BIOS_8_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_8_SCRATCH) + +START_REGISTER(BIOS_9_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_9_SCRATCH) + +START_REGISTER(BIOS_10_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_10_SCRATCH) + +START_REGISTER(BIOS_11_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_11_SCRATCH) + +START_REGISTER(BIOS_12_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_12_SCRATCH) + +START_REGISTER(BIOS_13_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_13_SCRATCH) + +START_REGISTER(BIOS_14_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_14_SCRATCH) + +START_REGISTER(BIOS_15_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_15_SCRATCH) + +START_REGISTER(COHER_SIZE_PM4) + GENERATE_FIELD(SIZE, int) +END_REGISTER(COHER_SIZE_PM4) + +START_REGISTER(COHER_BASE_PM4) + GENERATE_FIELD(BASE, int) +END_REGISTER(COHER_BASE_PM4) + +START_REGISTER(COHER_STATUS_PM4) + GENERATE_FIELD(STATUS, int) + GENERATE_FIELD(TC_ACTION_ENA, int) + GENERATE_FIELD(RB_COLOR_INFO_ENA, int) + GENERATE_FIELD(DEST_BASE_7_ENA, int) + GENERATE_FIELD(DEST_BASE_6_ENA, int) + GENERATE_FIELD(DEST_BASE_5_ENA, int) + GENERATE_FIELD(DEST_BASE_4_ENA, int) + GENERATE_FIELD(DEST_BASE_3_ENA, int) + GENERATE_FIELD(DEST_BASE_2_ENA, int) + GENERATE_FIELD(DEST_BASE_1_ENA, int) + GENERATE_FIELD(DEST_BASE_0_ENA, int) + GENERATE_FIELD(RB_COPY_DEST_BASE_ENA, int) + GENERATE_FIELD(MATCHING_CONTEXTS, int) +END_REGISTER(COHER_STATUS_PM4) + +START_REGISTER(COHER_SIZE_HOST) + GENERATE_FIELD(SIZE, int) +END_REGISTER(COHER_SIZE_HOST) + +START_REGISTER(COHER_BASE_HOST) + GENERATE_FIELD(BASE, hex) +END_REGISTER(COHER_BASE_HOST) + +START_REGISTER(COHER_STATUS_HOST) + GENERATE_FIELD(STATUS, int) + GENERATE_FIELD(TC_ACTION_ENA, int) + GENERATE_FIELD(RB_COLOR_INFO_ENA, int) + GENERATE_FIELD(DEST_BASE_7_ENA, int) + GENERATE_FIELD(DEST_BASE_6_ENA, int) + GENERATE_FIELD(DEST_BASE_5_ENA, int) + GENERATE_FIELD(DEST_BASE_4_ENA, int) + GENERATE_FIELD(DEST_BASE_3_ENA, int) + GENERATE_FIELD(DEST_BASE_2_ENA, int) + GENERATE_FIELD(DEST_BASE_1_ENA, int) + GENERATE_FIELD(DEST_BASE_0_ENA, int) + GENERATE_FIELD(RB_COPY_DEST_BASE_ENA, int) + GENERATE_FIELD(MATCHING_CONTEXTS, int) +END_REGISTER(COHER_STATUS_HOST) + +START_REGISTER(COHER_DEST_BASE_0) + GENERATE_FIELD(DEST_BASE_0, hex) +END_REGISTER(COHER_DEST_BASE_0) + +START_REGISTER(COHER_DEST_BASE_1) + GENERATE_FIELD(DEST_BASE_1, hex) +END_REGISTER(COHER_DEST_BASE_1) + +START_REGISTER(COHER_DEST_BASE_2) + GENERATE_FIELD(DEST_BASE_2, hex) +END_REGISTER(COHER_DEST_BASE_2) + +START_REGISTER(COHER_DEST_BASE_3) + GENERATE_FIELD(DEST_BASE_3, hex) +END_REGISTER(COHER_DEST_BASE_3) + +START_REGISTER(COHER_DEST_BASE_4) + GENERATE_FIELD(DEST_BASE_4, hex) +END_REGISTER(COHER_DEST_BASE_4) + +START_REGISTER(COHER_DEST_BASE_5) + GENERATE_FIELD(DEST_BASE_5, hex) +END_REGISTER(COHER_DEST_BASE_5) + +START_REGISTER(COHER_DEST_BASE_6) + GENERATE_FIELD(DEST_BASE_6, hex) +END_REGISTER(COHER_DEST_BASE_6) + +START_REGISTER(COHER_DEST_BASE_7) + GENERATE_FIELD(DEST_BASE_7, hex) +END_REGISTER(COHER_DEST_BASE_7) + +START_REGISTER(RB_SURFACE_INFO) + GENERATE_FIELD(MSAA_SAMPLES, MSAASamples) + GENERATE_FIELD(SURFACE_PITCH, uint) +END_REGISTER(RB_SURFACE_INFO) + +START_REGISTER(RB_COLOR_INFO) + GENERATE_FIELD(COLOR_BASE, uint) + GENERATE_FIELD(COLOR_SWAP, uint) + GENERATE_FIELD(COLOR_ENDIAN, uint) + GENERATE_FIELD(COLOR_LINEAR, bool) + GENERATE_FIELD(COLOR_ROUND_MODE, uint) + GENERATE_FIELD(COLOR_FORMAT, ColorformatX) +END_REGISTER(RB_COLOR_INFO) + +START_REGISTER(RB_DEPTH_INFO) + GENERATE_FIELD(DEPTH_BASE, uint) + GENERATE_FIELD(DEPTH_FORMAT, DepthformatX) +END_REGISTER(RB_DEPTH_INFO) + +START_REGISTER(RB_STENCILREFMASK) + GENERATE_FIELD(RESERVED1, bool) + GENERATE_FIELD(RESERVED0, bool) + GENERATE_FIELD(STENCILWRITEMASK, hex) + GENERATE_FIELD(STENCILMASK, hex) + GENERATE_FIELD(STENCILREF, hex) +END_REGISTER(RB_STENCILREFMASK) + +START_REGISTER(RB_ALPHA_REF) + GENERATE_FIELD(ALPHA_REF, float) +END_REGISTER(RB_ALPHA_REF) + +START_REGISTER(RB_COLOR_MASK) + GENERATE_FIELD(RESERVED3, bool) + GENERATE_FIELD(RESERVED2, bool) + GENERATE_FIELD(WRITE_ALPHA, bool) + GENERATE_FIELD(WRITE_BLUE, bool) + GENERATE_FIELD(WRITE_GREEN, bool) + GENERATE_FIELD(WRITE_RED, bool) +END_REGISTER(RB_COLOR_MASK) + +START_REGISTER(RB_BLEND_RED) + GENERATE_FIELD(BLEND_RED, uint) +END_REGISTER(RB_BLEND_RED) + +START_REGISTER(RB_BLEND_GREEN) + GENERATE_FIELD(BLEND_GREEN, uint) +END_REGISTER(RB_BLEND_GREEN) + +START_REGISTER(RB_BLEND_BLUE) + GENERATE_FIELD(BLEND_BLUE, uint) +END_REGISTER(RB_BLEND_BLUE) + +START_REGISTER(RB_BLEND_ALPHA) + GENERATE_FIELD(BLEND_ALPHA, uint) +END_REGISTER(RB_BLEND_ALPHA) + +START_REGISTER(RB_FOG_COLOR) + GENERATE_FIELD(FOG_BLUE, uint) + GENERATE_FIELD(FOG_GREEN, uint) + GENERATE_FIELD(FOG_RED, uint) +END_REGISTER(RB_FOG_COLOR) + +START_REGISTER(RB_STENCILREFMASK_BF) + GENERATE_FIELD(RESERVED5, bool) + GENERATE_FIELD(RESERVED4, bool) + GENERATE_FIELD(STENCILWRITEMASK_BF, hex) + GENERATE_FIELD(STENCILMASK_BF, hex) + GENERATE_FIELD(STENCILREF_BF, hex) +END_REGISTER(RB_STENCILREFMASK_BF) + +START_REGISTER(RB_DEPTHCONTROL) + GENERATE_FIELD(STENCILZFAIL_BF, StencilOp) + GENERATE_FIELD(STENCILZPASS_BF, StencilOp) + GENERATE_FIELD(STENCILFAIL_BF, StencilOp) + GENERATE_FIELD(STENCILFUNC_BF, CompareRef) + GENERATE_FIELD(STENCILZFAIL, StencilOp) + GENERATE_FIELD(STENCILZPASS, StencilOp) + GENERATE_FIELD(STENCILFAIL, StencilOp) + GENERATE_FIELD(STENCILFUNC, CompareRef) + GENERATE_FIELD(BACKFACE_ENABLE, bool) + GENERATE_FIELD(ZFUNC, CompareFrag) + GENERATE_FIELD(EARLY_Z_ENABLE, bool) + GENERATE_FIELD(Z_WRITE_ENABLE, bool) + GENERATE_FIELD(Z_ENABLE, bool) + GENERATE_FIELD(STENCIL_ENABLE, bool) +END_REGISTER(RB_DEPTHCONTROL) + +START_REGISTER(RB_BLENDCONTROL) + GENERATE_FIELD(BLEND_FORCE, bool) + GENERATE_FIELD(BLEND_FORCE_ENABLE, bool) + GENERATE_FIELD(ALPHA_DESTBLEND, BlendOpX) + GENERATE_FIELD(ALPHA_COMB_FCN, CombFuncX) + GENERATE_FIELD(ALPHA_SRCBLEND, BlendOpX) + GENERATE_FIELD(COLOR_DESTBLEND, BlendOpX) + GENERATE_FIELD(COLOR_COMB_FCN, CombFuncX) + GENERATE_FIELD(COLOR_SRCBLEND, BlendOpX) +END_REGISTER(RB_BLENDCONTROL) + +START_REGISTER(RB_COLORCONTROL) + GENERATE_FIELD(ALPHA_TO_MASK_OFFSET3, hex) + GENERATE_FIELD(ALPHA_TO_MASK_OFFSET2, hex) + GENERATE_FIELD(ALPHA_TO_MASK_OFFSET1, hex) + GENERATE_FIELD(ALPHA_TO_MASK_OFFSET0, hex) + GENERATE_FIELD(PIXEL_FOG, bool) + GENERATE_FIELD(DITHER_TYPE, DitherTypeX) + GENERATE_FIELD(DITHER_MODE, DitherModeX) + GENERATE_FIELD(ROP_CODE, uint) + GENERATE_FIELD(VS_EXPORTS_FOG, bool) + GENERATE_FIELD(FOG_ENABLE, bool) + GENERATE_FIELD(BLEND_DISABLE, bool) + GENERATE_FIELD(ALPHA_TO_MASK_ENABLE, bool) + GENERATE_FIELD(ALPHA_TEST_ENABLE, bool) + GENERATE_FIELD(ALPHA_FUNC, CompareRef) +END_REGISTER(RB_COLORCONTROL) + +START_REGISTER(RB_MODECONTROL) + GENERATE_FIELD(EDRAM_MODE, EdramMode) +END_REGISTER(RB_MODECONTROL) + +START_REGISTER(RB_COLOR_DEST_MASK) + GENERATE_FIELD(COLOR_DEST_MASK, uint) +END_REGISTER(RB_COLOR_DEST_MASK) + +START_REGISTER(RB_COPY_CONTROL) + GENERATE_FIELD(CLEAR_MASK, uint) + GENERATE_FIELD(DEPTH_CLEAR_ENABLE, bool) + GENERATE_FIELD(COPY_SAMPLE_SELECT, CopySampleSelect) +END_REGISTER(RB_COPY_CONTROL) + +START_REGISTER(RB_COPY_DEST_BASE) + GENERATE_FIELD(COPY_DEST_BASE, uint) +END_REGISTER(RB_COPY_DEST_BASE) + +START_REGISTER(RB_COPY_DEST_PITCH) + GENERATE_FIELD(COPY_DEST_PITCH, uint) +END_REGISTER(RB_COPY_DEST_PITCH) + +START_REGISTER(RB_COPY_DEST_INFO) + GENERATE_FIELD(COPY_MASK_WRITE_ALPHA, hex) + GENERATE_FIELD(COPY_MASK_WRITE_BLUE, hex) + GENERATE_FIELD(COPY_MASK_WRITE_GREEN, hex) + GENERATE_FIELD(COPY_MASK_WRITE_RED, hex) + GENERATE_FIELD(COPY_DEST_DITHER_TYPE, DitherTypeX) + GENERATE_FIELD(COPY_DEST_DITHER_MODE, DitherModeX) + GENERATE_FIELD(COPY_DEST_SWAP, uint) + GENERATE_FIELD(COPY_DEST_FORMAT, ColorformatX) + GENERATE_FIELD(COPY_DEST_LINEAR, uint) + GENERATE_FIELD(COPY_DEST_ENDIAN, SurfaceEndian) +END_REGISTER(RB_COPY_DEST_INFO) + +START_REGISTER(RB_COPY_DEST_PIXEL_OFFSET) + GENERATE_FIELD(OFFSET_Y, uint) + GENERATE_FIELD(OFFSET_X, uint) +END_REGISTER(RB_COPY_DEST_PIXEL_OFFSET) + +START_REGISTER(RB_DEPTH_CLEAR) + GENERATE_FIELD(DEPTH_CLEAR, uint) +END_REGISTER(RB_DEPTH_CLEAR) + +START_REGISTER(RB_SAMPLE_COUNT_CTL) + GENERATE_FIELD(COPY_SAMPLE_COUNT, bool) + GENERATE_FIELD(RESET_SAMPLE_COUNT, bool) +END_REGISTER(RB_SAMPLE_COUNT_CTL) + +START_REGISTER(RB_SAMPLE_COUNT_ADDR) + GENERATE_FIELD(SAMPLE_COUNT_ADDR, uint) +END_REGISTER(RB_SAMPLE_COUNT_ADDR) + +START_REGISTER(RB_BC_CONTROL) + GENERATE_FIELD(RESERVED6, bool) + GENERATE_FIELD(CRC_SYSTEM, bool) + GENERATE_FIELD(MEM_EXPORT_LINEAR_MODE_ENABLE, bool) + GENERATE_FIELD(MEM_EXPORT_TIMEOUT_SELECT, int) + GENERATE_FIELD(ACCUM_DATA_FIFO_LIMIT, bool) + GENERATE_FIELD(LINEAR_PERFORMANCE_ENABLE, bool) + GENERATE_FIELD(ACCUM_ALLOC_MASK, uint) + GENERATE_FIELD(DISABLE_ACCUM, bool) + GENERATE_FIELD(DISABLE_SAMPLE_COUNTERS, bool) + GENERATE_FIELD(CRC_MODE, bool) + GENERATE_FIELD(ENABLE_CRC_UPDATE, bool) + GENERATE_FIELD(AZ_THROTTLE_COUNT, uint) + GENERATE_FIELD(ENABLE_AZ_THROTTLE, bool) + GENERATE_FIELD(DISABLE_LZ_NULL_ZCMD_DROP, bool) + GENERATE_FIELD(DISABLE_EZ_NULL_ZCMD_DROP, bool) + GENERATE_FIELD(DISABLE_EZ_FAST_CONTEXT_SWITCH, bool) + GENERATE_FIELD(DISABLE_EDRAM_CAM, bool) + GENERATE_FIELD(ACCUM_TIMEOUT_SELECT, uint) + GENERATE_FIELD(ACCUM_LINEAR_MODE_ENABLE, bool) +END_REGISTER(RB_BC_CONTROL) + +START_REGISTER(RB_EDRAM_INFO) + GENERATE_FIELD(EDRAM_RANGE, hex) + GENERATE_FIELD(EDRAM_MAPPING_MODE, uint) + GENERATE_FIELD(EDRAM_SIZE, EdramSizeX) +END_REGISTER(RB_EDRAM_INFO) + +START_REGISTER(RB_CRC_RD_PORT) + GENERATE_FIELD(CRC_DATA, hex) +END_REGISTER(RB_CRC_RD_PORT) + +START_REGISTER(RB_CRC_CONTROL) + GENERATE_FIELD(CRC_RD_ADVANCE, bool) +END_REGISTER(RB_CRC_CONTROL) + +START_REGISTER(RB_CRC_MASK) + GENERATE_FIELD(CRC_MASK, hex) +END_REGISTER(RB_CRC_MASK) + +START_REGISTER(RB_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, RB_PERFCNT_SELECT) +END_REGISTER(RB_PERFCOUNTER0_SELECT) + +START_REGISTER(RB_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(RB_PERFCOUNTER0_LOW) + +START_REGISTER(RB_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(RB_PERFCOUNTER0_HI) + +START_REGISTER(RB_TOTAL_SAMPLES) + GENERATE_FIELD(TOTAL_SAMPLES, int) +END_REGISTER(RB_TOTAL_SAMPLES) + +START_REGISTER(RB_ZPASS_SAMPLES) + GENERATE_FIELD(ZPASS_SAMPLES, int) +END_REGISTER(RB_ZPASS_SAMPLES) + +START_REGISTER(RB_ZFAIL_SAMPLES) + GENERATE_FIELD(ZFAIL_SAMPLES, int) +END_REGISTER(RB_ZFAIL_SAMPLES) + +START_REGISTER(RB_SFAIL_SAMPLES) + GENERATE_FIELD(SFAIL_SAMPLES, int) +END_REGISTER(RB_SFAIL_SAMPLES) + +START_REGISTER(RB_DEBUG_0) + GENERATE_FIELD(EZ_INFSAMP_FULL, bool) + GENERATE_FIELD(C_MASK_FULL, bool) + GENERATE_FIELD(C_REQ_FULL, bool) + GENERATE_FIELD(C_EZ_TILE_FULL, bool) + GENERATE_FIELD(C_SX_CMD_FULL, bool) + GENERATE_FIELD(C_SX_LAT_FULL, bool) + GENERATE_FIELD(CMDFIFO_C_ORDERING_FULL, bool) + GENERATE_FIELD(CMDFIFO_Z_ORDERING_FULL, bool) + GENERATE_FIELD(CMDFIFO_C0_HOLD_FULL, bool) + GENERATE_FIELD(CMDFIFO_C1_HOLD_FULL, bool) + GENERATE_FIELD(CMDFIFO_Z0_HOLD_FULL, bool) + GENERATE_FIELD(CMDFIFO_Z1_HOLD_FULL, bool) + GENERATE_FIELD(WRREQ_C0_FULL, bool) + GENERATE_FIELD(WRREQ_C1_FULL, bool) + GENERATE_FIELD(WRREQ_Z0_FULL, bool) + GENERATE_FIELD(WRREQ_Z1_FULL, bool) + GENERATE_FIELD(WRREQ_C_WE_LO_FULL, bool) + GENERATE_FIELD(WRREQ_C_WE_HI_FULL, bool) + GENERATE_FIELD(WRREQ_E0_MACRO_LO_FULL, bool) + GENERATE_FIELD(WRREQ_E0_MACRO_HI_FULL, bool) + GENERATE_FIELD(WRREQ_E1_MACRO_LO_FULL, bool) + GENERATE_FIELD(WRREQ_E1_MACRO_HI_FULL, bool) + GENERATE_FIELD(RDREQ_C0_FULL, bool) + GENERATE_FIELD(RDREQ_C1_FULL, bool) + GENERATE_FIELD(RDREQ_Z0_FULL, bool) + GENERATE_FIELD(RDREQ_Z1_FULL, bool) + GENERATE_FIELD(RDREQ_E0_ORDERING_FULL, bool) + GENERATE_FIELD(RDREQ_E1_ORDERING_FULL, bool) + GENERATE_FIELD(RDREQ_CTL_C0_PRE_FULL, bool) + GENERATE_FIELD(RDREQ_CTL_C1_PRE_FULL, bool) + GENERATE_FIELD(RDREQ_CTL_Z0_PRE_FULL, bool) + GENERATE_FIELD(RDREQ_CTL_Z1_PRE_FULL, bool) +END_REGISTER(RB_DEBUG_0) + +START_REGISTER(RB_DEBUG_1) + GENERATE_FIELD(EZ_INFSAMP_EMPTY, bool) + GENERATE_FIELD(C_MASK_EMPTY, bool) + GENERATE_FIELD(C_REQ_EMPTY, bool) + GENERATE_FIELD(C_EZ_TILE_EMPTY, bool) + GENERATE_FIELD(C_SX_CMD_EMPTY, bool) + GENERATE_FIELD(C_SX_LAT_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_C_ORDERING_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_Z_ORDERING_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_C0_HOLD_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_C1_HOLD_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_Z0_HOLD_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_Z1_HOLD_EMPTY, bool) + GENERATE_FIELD(WRREQ_C0_PRE_EMPTY, bool) + GENERATE_FIELD(WRREQ_C1_PRE_EMPTY, bool) + GENERATE_FIELD(WRREQ_Z0_EMPTY, bool) + GENERATE_FIELD(WRREQ_Z1_EMPTY, bool) + GENERATE_FIELD(WRREQ_C_WE_LO_EMPTY, bool) + GENERATE_FIELD(WRREQ_C_WE_HI_EMPTY, bool) + GENERATE_FIELD(WRREQ_E0_MACRO_LO_EMPTY, bool) + GENERATE_FIELD(WRREQ_E0_MACRO_HI_EMPTY, bool) + GENERATE_FIELD(WRREQ_E1_MACRO_LO_EMPTY, bool) + GENERATE_FIELD(WRREQ_E1_MACRO_HI_EMPTY, bool) + GENERATE_FIELD(RDREQ_C0_EMPTY, bool) + GENERATE_FIELD(RDREQ_C1_EMPTY, bool) + GENERATE_FIELD(RDREQ_Z0_EMPTY, bool) + GENERATE_FIELD(RDREQ_Z1_EMPTY, bool) + GENERATE_FIELD(RDREQ_E0_ORDERING_EMPTY, bool) + GENERATE_FIELD(RDREQ_E1_ORDERING_EMPTY, bool) + GENERATE_FIELD(RDREQ_C0_CMD_EMPTY, bool) + GENERATE_FIELD(RDREQ_C1_CMD_EMPTY, bool) + GENERATE_FIELD(RDREQ_Z0_CMD_EMPTY, bool) + GENERATE_FIELD(RDREQ_Z1_CMD_EMPTY, bool) +END_REGISTER(RB_DEBUG_1) + +START_REGISTER(RB_DEBUG_2) + GENERATE_FIELD(Z_TILE_EMPTY, bool) + GENERATE_FIELD(Z_SAMP_EMPTY, bool) + GENERATE_FIELD(Z1_REQ_EMPTY, bool) + GENERATE_FIELD(Z0_REQ_EMPTY, bool) + GENERATE_FIELD(Z1_MASK_EMPTY, bool) + GENERATE_FIELD(Z0_MASK_EMPTY, bool) + GENERATE_FIELD(EZ_MASK_UPPER_EMPTY, bool) + GENERATE_FIELD(EZ_MASK_LOWER_EMPTY, bool) + GENERATE_FIELD(EZ_INFTILE_EMPTY, bool) + GENERATE_FIELD(Z_TILE_FULL, bool) + GENERATE_FIELD(Z_SAMP_FULL, bool) + GENERATE_FIELD(Z1_REQ_FULL, bool) + GENERATE_FIELD(Z0_REQ_FULL, bool) + GENERATE_FIELD(Z1_MASK_FULL, bool) + GENERATE_FIELD(Z0_MASK_FULL, bool) + GENERATE_FIELD(EZ_MASK_UPPER_FULL, bool) + GENERATE_FIELD(EZ_MASK_LOWER_FULL, bool) + GENERATE_FIELD(EZ_INFTILE_FULL, bool) + GENERATE_FIELD(CURRENT_TILE_EVENT, bool) + GENERATE_FIELD(SYSMEM_BLEND_FLAG, bool) + GENERATE_FIELD(MEM_EXPORT_FLAG, bool) + GENERATE_FIELD(SX_LAT_FIFO_COUNT, bool) + GENERATE_FIELD(TILE_FIFO_COUNT, bool) +END_REGISTER(RB_DEBUG_2) + +START_REGISTER(RB_DEBUG_3) + GENERATE_FIELD(ZEXP_UPPER_FULL, bool) + GENERATE_FIELD(ZEXP_LOWER_FULL, bool) + GENERATE_FIELD(ZEXP_UPPER_EMPTY, bool) + GENERATE_FIELD(ZEXP_LOWER_EMPTY, bool) + GENERATE_FIELD(EZ_RETURN_UPPER_FULL, bool) + GENERATE_FIELD(EZ_RETURN_LOWER_FULL, bool) + GENERATE_FIELD(EZ_RETURN_UPPER_EMPTY, bool) + GENERATE_FIELD(EZ_RETURN_LOWER_EMPTY, bool) + GENERATE_FIELD(SHD_EMPTY, bool) + GENERATE_FIELD(SHD_FULL, bool) + GENERATE_FIELD(ACCUM_DATA_FIFO_CNT, bool) + GENERATE_FIELD(ACCUM_INPUT_REG_VALID, bool) + GENERATE_FIELD(ACCUM_WRITE_CLEAN_COUNT, bool) + GENERATE_FIELD(ACCUM_FLUSHING, bool) + GENERATE_FIELD(ACCUM_VALID, bool) +END_REGISTER(RB_DEBUG_3) + +START_REGISTER(RB_DEBUG_4) + GENERATE_FIELD(CONTEXT_COUNT_DEBUG, bool) + GENERATE_FIELD(SYSMEM_WRITE_COUNT_OVERFLOW, bool) + GENERATE_FIELD(ACCUM_ORDER_FIFO_FULL, bool) + GENERATE_FIELD(ACCUM_DATA_FIFO_FULL, bool) + GENERATE_FIELD(ACCUM_ORDER_FIFO_EMPTY, bool) + GENERATE_FIELD(ACCUM_DATA_FIFO_EMPTY, bool) + GENERATE_FIELD(SYSMEM_WR_ACCESS_FLAG, bool) + GENERATE_FIELD(SYSMEM_RD_ACCESS_FLAG, bool) + GENERATE_FIELD(GMEM_WR_ACCESS_FLAG, bool) + GENERATE_FIELD(GMEM_RD_ACCESS_FLAG, bool) +END_REGISTER(RB_DEBUG_4) + +START_REGISTER(RB_FLAG_CONTROL) + GENERATE_FIELD(DEBUG_FLAG_CLEAR, bool) +END_REGISTER(RB_FLAG_CONTROL) + +START_REGISTER(RB_BC_SPARES) + GENERATE_FIELD(RESERVED, bool) +END_REGISTER(RB_BC_SPARES) + +START_REGISTER(BC_DUMMY_CRAYRB_ENUMS) + GENERATE_FIELD(DUMMY_RB_COPY_DEST_INFO_NUMBER, SurfaceNumberX) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_ARRAY, SurfaceArray) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_TILING, SurfaceTiling) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_FORMAT, SurfaceFormat) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_NUMBER, SurfaceNumber) + GENERATE_FIELD(DUMMY_CRAYRB_COLOR_FORMAT, ColorFormat) + GENERATE_FIELD(DUMMY_CRAYRB_ARRAY, ColorArray) + GENERATE_FIELD(DUMMY_CRAYRB_DEPTH_ARRAY, DepthArray) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_SWAP, SurfaceSwap) + GENERATE_FIELD(DUMMY_CRAYRB_DEPTH_FORMAT, DepthFormat) +END_REGISTER(BC_DUMMY_CRAYRB_ENUMS) + +START_REGISTER(BC_DUMMY_CRAYRB_MOREENUMS) + GENERATE_FIELD(DUMMY_CRAYRB_COLORARRAYX, ColorArrayX) +END_REGISTER(BC_DUMMY_CRAYRB_MOREENUMS) + diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_mask.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_mask.h new file mode 100644 index 000000000000..f31b2a74d1fa --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_mask.h @@ -0,0 +1,5920 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_MASK_HEADER) +#define _yamato_MASK_HEADER +/* +* yamato_mask.h +* +* Register Spec Release: Chip Spec 1.0 +* +* +* (c) 2000 ATI Technologies Inc. (unpublished) +* +* All rights reserved. This notice is intended as a precaution against +* inadvertent publication and does not imply publication or any waiver +* of confidentiality. The year included in the foregoing notice is the +* year of creation of the work. +* +*/ + +// PA_CL_VPORT_XSCALE +#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xffffffffL + +// PA_CL_VPORT_XOFFSET +#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xffffffffL + +// PA_CL_VPORT_YSCALE +#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xffffffffL + +// PA_CL_VPORT_YOFFSET +#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xffffffffL + +// PA_CL_VPORT_ZSCALE +#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xffffffffL + +// PA_CL_VPORT_ZOFFSET +#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xffffffffL + +// PA_CL_VTE_CNTL +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x00000001L +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA 0x00000001L +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x00000002L +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA 0x00000002L +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x00000004L +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA 0x00000004L +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x00000008L +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA 0x00000008L +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x00000010L +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA 0x00000010L +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x00000020L +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA 0x00000020L +#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100L +#define PA_CL_VTE_CNTL__VTX_XY_FMT 0x00000100L +#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200L +#define PA_CL_VTE_CNTL__VTX_Z_FMT 0x00000200L +#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x00000400L +#define PA_CL_VTE_CNTL__VTX_W0_FMT 0x00000400L +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x00000800L +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF 0x00000800L + +// PA_CL_CLIP_CNTL +#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x00010000L +#define PA_CL_CLIP_CNTL__CLIP_DISABLE 0x00010000L +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000L +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA 0x00040000L +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x00080000L +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF 0x00080000L +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x00100000L +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT 0x00100000L +#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x00200000L +#define PA_CL_CLIP_CNTL__VTX_KILL_OR 0x00200000L +#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN_MASK 0x00400000L +#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN 0x00400000L +#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN_MASK 0x00800000L +#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN 0x00800000L +#define PA_CL_CLIP_CNTL__W_NAN_RETAIN_MASK 0x01000000L +#define PA_CL_CLIP_CNTL__W_NAN_RETAIN 0x01000000L + +// PA_CL_GB_VERT_CLIP_ADJ +#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffffL + +// PA_CL_GB_VERT_DISC_ADJ +#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xffffffffL + +// PA_CL_GB_HORZ_CLIP_ADJ +#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffffL + +// PA_CL_GB_HORZ_DISC_ADJ +#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xffffffffL + +// PA_CL_ENHANCE +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x00000001L +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA 0x00000001L +#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000L +#define PA_CL_ENHANCE__ECO_SPARE3 0x10000000L +#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000L +#define PA_CL_ENHANCE__ECO_SPARE2 0x20000000L +#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000L +#define PA_CL_ENHANCE__ECO_SPARE1 0x40000000L +#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000L +#define PA_CL_ENHANCE__ECO_SPARE0 0x80000000L + +// PA_SC_ENHANCE +#define PA_SC_ENHANCE__ECO_SPARE3_MASK 0x10000000L +#define PA_SC_ENHANCE__ECO_SPARE3 0x10000000L +#define PA_SC_ENHANCE__ECO_SPARE2_MASK 0x20000000L +#define PA_SC_ENHANCE__ECO_SPARE2 0x20000000L +#define PA_SC_ENHANCE__ECO_SPARE1_MASK 0x40000000L +#define PA_SC_ENHANCE__ECO_SPARE1 0x40000000L +#define PA_SC_ENHANCE__ECO_SPARE0_MASK 0x80000000L +#define PA_SC_ENHANCE__ECO_SPARE0 0x80000000L + +// PA_SU_VTX_CNTL +#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x00000001L +#define PA_SU_VTX_CNTL__PIX_CENTER 0x00000001L +#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x00000006L +#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x00000038L + +// PA_SU_POINT_SIZE +#define PA_SU_POINT_SIZE__HEIGHT_MASK 0x0000ffffL +#define PA_SU_POINT_SIZE__WIDTH_MASK 0xffff0000L + +// PA_SU_POINT_MINMAX +#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0x0000ffffL +#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xffff0000L + +// PA_SU_LINE_CNTL +#define PA_SU_LINE_CNTL__WIDTH_MASK 0x0000ffffL + +// PA_SU_FACE_DATA +#define PA_SU_FACE_DATA__BASE_ADDR_MASK 0xffffffe0L + +// PA_SU_SC_MODE_CNTL +#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x00000001L +#define PA_SU_SC_MODE_CNTL__CULL_FRONT 0x00000001L +#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x00000002L +#define PA_SU_SC_MODE_CNTL__CULL_BACK 0x00000002L +#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x00000004L +#define PA_SU_SC_MODE_CNTL__FACE 0x00000004L +#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x00000018L +#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0x000000e0L +#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x00000700L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE 0x00000800L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x00001000L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE 0x00001000L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x00002000L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE 0x00002000L +#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE_MASK 0x00008000L +#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE 0x00008000L +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000L +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE 0x00010000L +#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE_MASK 0x00040000L +#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE 0x00040000L +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x00080000L +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST 0x00080000L +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x00100000L +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS 0x00100000L +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x00200000L +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA 0x00200000L +#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE_MASK 0x00800000L +#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE 0x00800000L +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI_MASK 0x02000000L +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI 0x02000000L +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK 0x04000000L +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE 0x04000000L +#define PA_SU_SC_MODE_CNTL__ZERO_AREA_FACENESS_MASK 0x20000000L +#define PA_SU_SC_MODE_CNTL__ZERO_AREA_FACENESS 0x20000000L +#define PA_SU_SC_MODE_CNTL__FACE_KILL_ENABLE_MASK 0x40000000L +#define PA_SU_SC_MODE_CNTL__FACE_KILL_ENABLE 0x40000000L +#define PA_SU_SC_MODE_CNTL__FACE_WRITE_ENABLE_MASK 0x80000000L +#define PA_SU_SC_MODE_CNTL__FACE_WRITE_ENABLE 0x80000000L + +// PA_SU_POLY_OFFSET_FRONT_SCALE +#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xffffffffL + +// PA_SU_POLY_OFFSET_FRONT_OFFSET +#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xffffffffL + +// PA_SU_POLY_OFFSET_BACK_SCALE +#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xffffffffL + +// PA_SU_POLY_OFFSET_BACK_OFFSET +#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER0_SELECT +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SU_PERFCOUNTER1_SELECT +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SU_PERFCOUNTER2_SELECT +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SU_PERFCOUNTER3_SELECT +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SU_PERFCOUNTER0_LOW +#define PA_SU_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER0_HI +#define PA_SU_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_SU_PERFCOUNTER1_LOW +#define PA_SU_PERFCOUNTER1_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER1_HI +#define PA_SU_PERFCOUNTER1_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_SU_PERFCOUNTER2_LOW +#define PA_SU_PERFCOUNTER2_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER2_HI +#define PA_SU_PERFCOUNTER2_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_SU_PERFCOUNTER3_LOW +#define PA_SU_PERFCOUNTER3_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER3_HI +#define PA_SU_PERFCOUNTER3_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_SC_WINDOW_OFFSET +#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0x00007fffL +#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0x7fff0000L + +// PA_SC_AA_CONFIG +#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x00000007L +#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x0001e000L + +// PA_SC_AA_MASK +#define PA_SC_AA_MASK__AA_MASK_MASK 0x0000ffffL + +// PA_SC_LINE_STIPPLE +#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0x0000ffffL +#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0x00ff0000L +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000L +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER 0x10000000L +#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000L + +// PA_SC_LINE_CNTL +#define PA_SC_LINE_CNTL__BRES_CNTL_MASK 0x000000ffL +#define PA_SC_LINE_CNTL__USE_BRES_CNTL_MASK 0x00000100L +#define PA_SC_LINE_CNTL__USE_BRES_CNTL 0x00000100L +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x00000200L +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH 0x00000200L +#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x00000400L +#define PA_SC_LINE_CNTL__LAST_PIXEL 0x00000400L + +// PA_SC_WINDOW_SCISSOR_TL +#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x00003fffL +#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x3fff0000L +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE 0x80000000L + +// PA_SC_WINDOW_SCISSOR_BR +#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x00003fffL +#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x3fff0000L + +// PA_SC_SCREEN_SCISSOR_TL +#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0x00007fffL +#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0x7fff0000L + +// PA_SC_SCREEN_SCISSOR_BR +#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0x00007fffL +#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0x7fff0000L + +// PA_SC_VIZ_QUERY +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA_MASK 0x00000001L +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA 0x00000001L +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ID_MASK 0x0000003eL +#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z_MASK 0x00000080L +#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z 0x00000080L + +// PA_SC_VIZ_QUERY_STATUS +#define PA_SC_VIZ_QUERY_STATUS__STATUS_BITS_MASK 0xffffffffL + +// PA_SC_LINE_STIPPLE_STATE +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0x0000000fL +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0x0000ff00L + +// PA_SC_PERFCOUNTER0_SELECT +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SC_PERFCOUNTER0_LOW +#define PA_SC_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SC_PERFCOUNTER0_HI +#define PA_SC_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_CL_CNTL_STATUS +#define PA_CL_CNTL_STATUS__CL_BUSY_MASK 0x80000000L +#define PA_CL_CNTL_STATUS__CL_BUSY 0x80000000L + +// PA_SU_CNTL_STATUS +#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000L +#define PA_SU_CNTL_STATUS__SU_BUSY 0x80000000L + +// PA_SC_CNTL_STATUS +#define PA_SC_CNTL_STATUS__SC_BUSY_MASK 0x80000000L +#define PA_SC_CNTL_STATUS__SC_BUSY 0x80000000L + +// PA_SU_DEBUG_CNTL +#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK 0x0000001fL + +// PA_SU_DEBUG_DATA +#define PA_SU_DEBUG_DATA__DATA_MASK 0xffffffffL + +// CLIPPER_DEBUG_REG00 +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK 0x00000001L +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write 0x00000001L +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full_MASK 0x00000002L +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full 0x00000002L +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK 0x00000004L +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write 0x00000004L +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK 0x00000008L +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full 0x00000008L +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x00000010L +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty 0x00000010L +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x00000020L +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full 0x00000020L +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x00000040L +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty 0x00000040L +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK 0x00000080L +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full 0x00000080L +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK 0x00000100L +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty 0x00000100L +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK 0x00000200L +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full 0x00000200L +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK 0x00000400L +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty 0x00000400L +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK 0x00000800L +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full 0x00000800L +#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x00001000L +#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty 0x00001000L +#define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK 0x00002000L +#define CLIPPER_DEBUG_REG00__clipcode_fifo_full 0x00002000L +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x00004000L +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty 0x00004000L +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x00008000L +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full 0x00008000L +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x00010000L +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty 0x00010000L +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x00020000L +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full 0x00020000L +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x00040000L +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty 0x00040000L +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x00080000L +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full 0x00080000L +#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK 0xfff00000L + +// CLIPPER_DEBUG_REG01 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet_MASK 0x00000001L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet 0x00000001L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot_MASK 0x00000002L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot 0x00000002L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0x0000001cL +#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim_MASK 0x00000020L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim 0x00000020L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x00000040L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive 0x00000040L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_2_MASK 0x00000780L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_1_MASK 0x00007800L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_0_MASK 0x00078000L +#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK 0x00380000L +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0x00c00000L +#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK 0xff000000L + +// CLIPPER_DEBUG_REG02 +#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO1_MASK 0x001fffffL +#define CLIPPER_DEBUG_REG02__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00e00000L +#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO0_MASK 0x7f000000L +#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000L +#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid 0x80000000L + +// CLIPPER_DEBUG_REG03 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO3_MASK 0x00000007L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x00000008L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive 0x00000008L +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO2_MASK 0x00000070L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x00000080L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive 0x00000080L +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO1_MASK 0x000fff00L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x03f00000L +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO0_MASK 0xfc000000L + +// CLIPPER_DEBUG_REG04 +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO2_MASK 0x00000007L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x00000008L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot 0x00000008L +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO1_MASK 0x00000070L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x00000080L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event 0x00000080L +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO0_MASK 0xffffff00L + +// CLIPPER_DEBUG_REG05 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx_MASK 0x00000001L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx 0x00000001L +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO3_MASK 0x00000006L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x00000038L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_event_id_MASK 0x00000fc0L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0000f000L +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO2_MASK 0x00030000L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x003c0000L +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO1_MASK 0x00c00000L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x0f000000L +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO0_MASK 0xf0000000L + +// CLIPPER_DEBUG_REG09 +#define CLIPPER_DEBUG_REG09__clprim_in_back_event_MASK 0x00000001L +#define CLIPPER_DEBUG_REG09__clprim_in_back_event 0x00000001L +#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive_MASK 0x00000002L +#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive 0x00000002L +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_2_MASK 0x0000003cL +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO2_MASK 0x000000c0L +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_1_MASK 0x00000f00L +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO1_MASK 0x00003000L +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_0_MASK 0x0003c000L +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO0_MASK 0x000c0000L +#define CLIPPER_DEBUG_REG09__prim_back_valid_MASK 0x00100000L +#define CLIPPER_DEBUG_REG09__prim_back_valid 0x00100000L +#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_out_cnt_MASK 0x01e00000L +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_orig_vertices_MASK 0x06000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait_MASK 0x08000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait 0x08000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty_MASK 0x10000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty 0x10000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full_MASK 0x20000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full 0x20000000L +#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_load_MASK 0xc0000000L + +// CLIPPER_DEBUG_REG10 +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x0000000fL +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO3_MASK 0x00000030L +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x000003c0L +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO2_MASK 0x00000c00L +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x0000f000L +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO1_MASK 0x00030000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx_MASK 0x00040000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx 0x00040000L +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO0_MASK 0x00180000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet_MASK 0x00200000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet 0x00200000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot_MASK 0x00400000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot 0x00400000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_deallocate_slot_MASK 0x03800000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_event_id_MASK 0xfc000000L + +// CLIPPER_DEBUG_REG11 +#define CLIPPER_DEBUG_REG11__vertval_bits_vertex_vertex_store_msb_MASK 0x0000000fL +#define CLIPPER_DEBUG_REG11__ALWAYS_ZERO_MASK 0xfffffff0L + +// CLIPPER_DEBUG_REG12 +#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x00000003L +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO2_MASK 0x0000001cL +#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty_MASK 0x00000020L +#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty 0x00000020L +#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x000007c0L +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO1_MASK 0x00007800L +#define CLIPPER_DEBUG_REG12__vertval_bits_vertex_cc_next_valid_MASK 0x00078000L +#define CLIPPER_DEBUG_REG12__clipcc_vertex_store_indx_MASK 0x00180000L +#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid_MASK 0x00200000L +#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid 0x00200000L +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO0_MASK 0xffc00000L + +// CLIPPER_DEBUG_REG13 +#define CLIPPER_DEBUG_REG13__sm0_clip_vert_cnt_MASK 0x0000000fL +#define CLIPPER_DEBUG_REG13__sm0_prim_end_state_MASK 0x000007f0L +#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO1_MASK 0x00003800L +#define CLIPPER_DEBUG_REG13__sm0_vertex_clip_cnt_MASK 0x0003c000L +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1_MASK 0x00040000L +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1 0x00040000L +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0_MASK 0x00080000L +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0 0x00080000L +#define CLIPPER_DEBUG_REG13__sm0_current_state_MASK 0x07f00000L +#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO0_MASK 0xf8000000L + +// SXIFCCG_DEBUG_REG0 +#define SXIFCCG_DEBUG_REG0__nan_kill_flag_MASK 0x0000000fL +#define SXIFCCG_DEBUG_REG0__position_address_MASK 0x00000070L +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO2_MASK 0x00000380L +#define SXIFCCG_DEBUG_REG0__point_address_MASK 0x00001c00L +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO1_MASK 0x0000e000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx_MASK 0x00010000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx 0x00010000L +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO0_MASK 0x00060000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask_MASK 0x00780000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci_MASK 0x3f800000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc_MASK 0x40000000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc 0x40000000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel_MASK 0x80000000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel 0x80000000L + +// SXIFCCG_DEBUG_REG1 +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO3_MASK 0x00000003L +#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_MASK 0x0000000cL +#define SXIFCCG_DEBUG_REG1__available_positions_MASK 0x00000070L +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO2_MASK 0x00000780L +#define SXIFCCG_DEBUG_REG1__sx_pending_advance_MASK 0x00000800L +#define SXIFCCG_DEBUG_REG1__sx_pending_advance 0x00000800L +#define SXIFCCG_DEBUG_REG1__sx_receive_indx_MASK 0x00007000L +#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector_MASK 0x00008000L +#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector 0x00008000L +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO1_MASK 0x000f0000L +#define SXIFCCG_DEBUG_REG1__aux_sel_MASK 0x00100000L +#define SXIFCCG_DEBUG_REG1__aux_sel 0x00100000L +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO0_MASK 0x00600000L +#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_MASK 0x01800000L +#define SXIFCCG_DEBUG_REG1__param_cache_base_MASK 0xfe000000L + +// SXIFCCG_DEBUG_REG2 +#define SXIFCCG_DEBUG_REG2__sx_sent_MASK 0x00000001L +#define SXIFCCG_DEBUG_REG2__sx_sent 0x00000001L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3_MASK 0x00000002L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3 0x00000002L +#define SXIFCCG_DEBUG_REG2__sx_aux_MASK 0x00000004L +#define SXIFCCG_DEBUG_REG2__sx_aux 0x00000004L +#define SXIFCCG_DEBUG_REG2__sx_request_indx_MASK 0x000001f8L +#define SXIFCCG_DEBUG_REG2__req_active_verts_MASK 0x0000fe00L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2_MASK 0x00010000L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2 0x00010000L +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx_MASK 0x00020000L +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx 0x00020000L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO1_MASK 0x000c0000L +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts_MASK 0x00300000L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO0_MASK 0x03c00000L +#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded_MASK 0x04000000L +#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded 0x04000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty_MASK 0x08000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty 0x08000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full_MASK 0x10000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full 0x10000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_contents_MASK 0xe0000000L + +// SXIFCCG_DEBUG_REG3 +#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable_MASK 0x0000000fL +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3_MASK 0x00000010L +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3 0x00000010L +#define SXIFCCG_DEBUG_REG3__available_positions_MASK 0x000000e0L +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO2_MASK 0x00000f00L +#define SXIFCCG_DEBUG_REG3__current_state_MASK 0x00003000L +#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty_MASK 0x00004000L +#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty 0x00004000L +#define SXIFCCG_DEBUG_REG3__vertex_fifo_full_MASK 0x00008000L +#define SXIFCCG_DEBUG_REG3__vertex_fifo_full 0x00008000L +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO1_MASK 0x00030000L +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty_MASK 0x00040000L +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty 0x00040000L +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full_MASK 0x00080000L +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full 0x00080000L +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty_MASK 0x00100000L +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty 0x00100000L +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full_MASK 0x00200000L +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full 0x00200000L +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO0_MASK 0xffc00000L + +// SETUP_DEBUG_REG0 +#define SETUP_DEBUG_REG0__su_cntl_state_MASK 0x0000001fL +#define SETUP_DEBUG_REG0__pmode_state_MASK 0x000007e0L +#define SETUP_DEBUG_REG0__ge_stallb_MASK 0x00000800L +#define SETUP_DEBUG_REG0__ge_stallb 0x00000800L +#define SETUP_DEBUG_REG0__geom_enable_MASK 0x00001000L +#define SETUP_DEBUG_REG0__geom_enable 0x00001000L +#define SETUP_DEBUG_REG0__su_clip_baryc_rtr_MASK 0x00002000L +#define SETUP_DEBUG_REG0__su_clip_baryc_rtr 0x00002000L +#define SETUP_DEBUG_REG0__su_clip_rtr_MASK 0x00004000L +#define SETUP_DEBUG_REG0__su_clip_rtr 0x00004000L +#define SETUP_DEBUG_REG0__pfifo_busy_MASK 0x00008000L +#define SETUP_DEBUG_REG0__pfifo_busy 0x00008000L +#define SETUP_DEBUG_REG0__su_cntl_busy_MASK 0x00010000L +#define SETUP_DEBUG_REG0__su_cntl_busy 0x00010000L +#define SETUP_DEBUG_REG0__geom_busy_MASK 0x00020000L +#define SETUP_DEBUG_REG0__geom_busy 0x00020000L + +// SETUP_DEBUG_REG1 +#define SETUP_DEBUG_REG1__y_sort0_gated_17_4_MASK 0x00003fffL +#define SETUP_DEBUG_REG1__x_sort0_gated_17_4_MASK 0x0fffc000L + +// SETUP_DEBUG_REG2 +#define SETUP_DEBUG_REG2__y_sort1_gated_17_4_MASK 0x00003fffL +#define SETUP_DEBUG_REG2__x_sort1_gated_17_4_MASK 0x0fffc000L + +// SETUP_DEBUG_REG3 +#define SETUP_DEBUG_REG3__y_sort2_gated_17_4_MASK 0x00003fffL +#define SETUP_DEBUG_REG3__x_sort2_gated_17_4_MASK 0x0fffc000L + +// SETUP_DEBUG_REG4 +#define SETUP_DEBUG_REG4__attr_indx_sort0_gated_MASK 0x000007ffL +#define SETUP_DEBUG_REG4__null_prim_gated_MASK 0x00000800L +#define SETUP_DEBUG_REG4__null_prim_gated 0x00000800L +#define SETUP_DEBUG_REG4__backfacing_gated_MASK 0x00001000L +#define SETUP_DEBUG_REG4__backfacing_gated 0x00001000L +#define SETUP_DEBUG_REG4__st_indx_gated_MASK 0x0000e000L +#define SETUP_DEBUG_REG4__clipped_gated_MASK 0x00010000L +#define SETUP_DEBUG_REG4__clipped_gated 0x00010000L +#define SETUP_DEBUG_REG4__dealloc_slot_gated_MASK 0x000e0000L +#define SETUP_DEBUG_REG4__xmajor_gated_MASK 0x00100000L +#define SETUP_DEBUG_REG4__xmajor_gated 0x00100000L +#define SETUP_DEBUG_REG4__diamond_rule_gated_MASK 0x00600000L +#define SETUP_DEBUG_REG4__type_gated_MASK 0x03800000L +#define SETUP_DEBUG_REG4__fpov_gated_MASK 0x04000000L +#define SETUP_DEBUG_REG4__fpov_gated 0x04000000L +#define SETUP_DEBUG_REG4__pmode_prim_gated_MASK 0x08000000L +#define SETUP_DEBUG_REG4__pmode_prim_gated 0x08000000L +#define SETUP_DEBUG_REG4__event_gated_MASK 0x10000000L +#define SETUP_DEBUG_REG4__event_gated 0x10000000L +#define SETUP_DEBUG_REG4__eop_gated_MASK 0x20000000L +#define SETUP_DEBUG_REG4__eop_gated 0x20000000L + +// SETUP_DEBUG_REG5 +#define SETUP_DEBUG_REG5__attr_indx_sort2_gated_MASK 0x000007ffL +#define SETUP_DEBUG_REG5__attr_indx_sort1_gated_MASK 0x003ff800L +#define SETUP_DEBUG_REG5__provoking_vtx_gated_MASK 0x00c00000L +#define SETUP_DEBUG_REG5__event_id_gated_MASK 0x1f000000L + +// PA_SC_DEBUG_CNTL +#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK 0x0000001fL + +// PA_SC_DEBUG_DATA +#define PA_SC_DEBUG_DATA__DATA_MASK 0xffffffffL + +// SC_DEBUG_0 +#define SC_DEBUG_0__pa_freeze_b1_MASK 0x00000001L +#define SC_DEBUG_0__pa_freeze_b1 0x00000001L +#define SC_DEBUG_0__pa_sc_valid_MASK 0x00000002L +#define SC_DEBUG_0__pa_sc_valid 0x00000002L +#define SC_DEBUG_0__pa_sc_phase_MASK 0x0000001cL +#define SC_DEBUG_0__cntx_cnt_MASK 0x00000fe0L +#define SC_DEBUG_0__decr_cntx_cnt_MASK 0x00001000L +#define SC_DEBUG_0__decr_cntx_cnt 0x00001000L +#define SC_DEBUG_0__incr_cntx_cnt_MASK 0x00002000L +#define SC_DEBUG_0__incr_cntx_cnt 0x00002000L +#define SC_DEBUG_0__trigger_MASK 0x80000000L +#define SC_DEBUG_0__trigger 0x80000000L + +// SC_DEBUG_1 +#define SC_DEBUG_1__em_state_MASK 0x00000007L +#define SC_DEBUG_1__em1_data_ready_MASK 0x00000008L +#define SC_DEBUG_1__em1_data_ready 0x00000008L +#define SC_DEBUG_1__em2_data_ready_MASK 0x00000010L +#define SC_DEBUG_1__em2_data_ready 0x00000010L +#define SC_DEBUG_1__move_em1_to_em2_MASK 0x00000020L +#define SC_DEBUG_1__move_em1_to_em2 0x00000020L +#define SC_DEBUG_1__ef_data_ready_MASK 0x00000040L +#define SC_DEBUG_1__ef_data_ready 0x00000040L +#define SC_DEBUG_1__ef_state_MASK 0x00000180L +#define SC_DEBUG_1__pipe_valid_MASK 0x00000200L +#define SC_DEBUG_1__pipe_valid 0x00000200L +#define SC_DEBUG_1__trigger_MASK 0x80000000L +#define SC_DEBUG_1__trigger 0x80000000L + +// SC_DEBUG_2 +#define SC_DEBUG_2__rc_rtr_dly_MASK 0x00000001L +#define SC_DEBUG_2__rc_rtr_dly 0x00000001L +#define SC_DEBUG_2__qmask_ff_alm_full_d1_MASK 0x00000002L +#define SC_DEBUG_2__qmask_ff_alm_full_d1 0x00000002L +#define SC_DEBUG_2__pipe_freeze_b_MASK 0x00000008L +#define SC_DEBUG_2__pipe_freeze_b 0x00000008L +#define SC_DEBUG_2__prim_rts_MASK 0x00000010L +#define SC_DEBUG_2__prim_rts 0x00000010L +#define SC_DEBUG_2__next_prim_rts_dly_MASK 0x00000020L +#define SC_DEBUG_2__next_prim_rts_dly 0x00000020L +#define SC_DEBUG_2__next_prim_rtr_dly_MASK 0x00000040L +#define SC_DEBUG_2__next_prim_rtr_dly 0x00000040L +#define SC_DEBUG_2__pre_stage1_rts_d1_MASK 0x00000080L +#define SC_DEBUG_2__pre_stage1_rts_d1 0x00000080L +#define SC_DEBUG_2__stage0_rts_MASK 0x00000100L +#define SC_DEBUG_2__stage0_rts 0x00000100L +#define SC_DEBUG_2__phase_rts_dly_MASK 0x00000200L +#define SC_DEBUG_2__phase_rts_dly 0x00000200L +#define SC_DEBUG_2__end_of_prim_s1_dly_MASK 0x00008000L +#define SC_DEBUG_2__end_of_prim_s1_dly 0x00008000L +#define SC_DEBUG_2__pass_empty_prim_s1_MASK 0x00010000L +#define SC_DEBUG_2__pass_empty_prim_s1 0x00010000L +#define SC_DEBUG_2__event_id_s1_MASK 0x003e0000L +#define SC_DEBUG_2__event_s1_MASK 0x00400000L +#define SC_DEBUG_2__event_s1 0x00400000L +#define SC_DEBUG_2__trigger_MASK 0x80000000L +#define SC_DEBUG_2__trigger 0x80000000L + +// SC_DEBUG_3 +#define SC_DEBUG_3__x_curr_s1_MASK 0x000007ffL +#define SC_DEBUG_3__y_curr_s1_MASK 0x003ff800L +#define SC_DEBUG_3__trigger_MASK 0x80000000L +#define SC_DEBUG_3__trigger 0x80000000L + +// SC_DEBUG_4 +#define SC_DEBUG_4__y_end_s1_MASK 0x00003fffL +#define SC_DEBUG_4__y_start_s1_MASK 0x0fffc000L +#define SC_DEBUG_4__y_dir_s1_MASK 0x10000000L +#define SC_DEBUG_4__y_dir_s1 0x10000000L +#define SC_DEBUG_4__trigger_MASK 0x80000000L +#define SC_DEBUG_4__trigger 0x80000000L + +// SC_DEBUG_5 +#define SC_DEBUG_5__x_end_s1_MASK 0x00003fffL +#define SC_DEBUG_5__x_start_s1_MASK 0x0fffc000L +#define SC_DEBUG_5__x_dir_s1_MASK 0x10000000L +#define SC_DEBUG_5__x_dir_s1 0x10000000L +#define SC_DEBUG_5__trigger_MASK 0x80000000L +#define SC_DEBUG_5__trigger 0x80000000L + +// SC_DEBUG_6 +#define SC_DEBUG_6__z_ff_empty_MASK 0x00000001L +#define SC_DEBUG_6__z_ff_empty 0x00000001L +#define SC_DEBUG_6__qmcntl_ff_empty_MASK 0x00000002L +#define SC_DEBUG_6__qmcntl_ff_empty 0x00000002L +#define SC_DEBUG_6__xy_ff_empty_MASK 0x00000004L +#define SC_DEBUG_6__xy_ff_empty 0x00000004L +#define SC_DEBUG_6__event_flag_MASK 0x00000008L +#define SC_DEBUG_6__event_flag 0x00000008L +#define SC_DEBUG_6__z_mask_needed_MASK 0x00000010L +#define SC_DEBUG_6__z_mask_needed 0x00000010L +#define SC_DEBUG_6__state_MASK 0x000000e0L +#define SC_DEBUG_6__state_delayed_MASK 0x00000700L +#define SC_DEBUG_6__data_valid_MASK 0x00000800L +#define SC_DEBUG_6__data_valid 0x00000800L +#define SC_DEBUG_6__data_valid_d_MASK 0x00001000L +#define SC_DEBUG_6__data_valid_d 0x00001000L +#define SC_DEBUG_6__tilex_delayed_MASK 0x003fe000L +#define SC_DEBUG_6__tiley_delayed_MASK 0x7fc00000L +#define SC_DEBUG_6__trigger_MASK 0x80000000L +#define SC_DEBUG_6__trigger 0x80000000L + +// SC_DEBUG_7 +#define SC_DEBUG_7__event_flag_MASK 0x00000001L +#define SC_DEBUG_7__event_flag 0x00000001L +#define SC_DEBUG_7__deallocate_MASK 0x0000000eL +#define SC_DEBUG_7__fposition_MASK 0x00000010L +#define SC_DEBUG_7__fposition 0x00000010L +#define SC_DEBUG_7__sr_prim_we_MASK 0x00000020L +#define SC_DEBUG_7__sr_prim_we 0x00000020L +#define SC_DEBUG_7__last_tile_MASK 0x00000040L +#define SC_DEBUG_7__last_tile 0x00000040L +#define SC_DEBUG_7__tile_ff_we_MASK 0x00000080L +#define SC_DEBUG_7__tile_ff_we 0x00000080L +#define SC_DEBUG_7__qs_data_valid_MASK 0x00000100L +#define SC_DEBUG_7__qs_data_valid 0x00000100L +#define SC_DEBUG_7__qs_q0_y_MASK 0x00000600L +#define SC_DEBUG_7__qs_q0_x_MASK 0x00001800L +#define SC_DEBUG_7__qs_q0_valid_MASK 0x00002000L +#define SC_DEBUG_7__qs_q0_valid 0x00002000L +#define SC_DEBUG_7__prim_ff_we_MASK 0x00004000L +#define SC_DEBUG_7__prim_ff_we 0x00004000L +#define SC_DEBUG_7__tile_ff_re_MASK 0x00008000L +#define SC_DEBUG_7__tile_ff_re 0x00008000L +#define SC_DEBUG_7__fw_prim_data_valid_MASK 0x00010000L +#define SC_DEBUG_7__fw_prim_data_valid 0x00010000L +#define SC_DEBUG_7__last_quad_of_tile_MASK 0x00020000L +#define SC_DEBUG_7__last_quad_of_tile 0x00020000L +#define SC_DEBUG_7__first_quad_of_tile_MASK 0x00040000L +#define SC_DEBUG_7__first_quad_of_tile 0x00040000L +#define SC_DEBUG_7__first_quad_of_prim_MASK 0x00080000L +#define SC_DEBUG_7__first_quad_of_prim 0x00080000L +#define SC_DEBUG_7__new_prim_MASK 0x00100000L +#define SC_DEBUG_7__new_prim 0x00100000L +#define SC_DEBUG_7__load_new_tile_data_MASK 0x00200000L +#define SC_DEBUG_7__load_new_tile_data 0x00200000L +#define SC_DEBUG_7__state_MASK 0x00c00000L +#define SC_DEBUG_7__fifos_ready_MASK 0x01000000L +#define SC_DEBUG_7__fifos_ready 0x01000000L +#define SC_DEBUG_7__trigger_MASK 0x80000000L +#define SC_DEBUG_7__trigger 0x80000000L + +// SC_DEBUG_8 +#define SC_DEBUG_8__sample_last_MASK 0x00000001L +#define SC_DEBUG_8__sample_last 0x00000001L +#define SC_DEBUG_8__sample_mask_MASK 0x0000001eL +#define SC_DEBUG_8__sample_y_MASK 0x00000060L +#define SC_DEBUG_8__sample_x_MASK 0x00000180L +#define SC_DEBUG_8__sample_send_MASK 0x00000200L +#define SC_DEBUG_8__sample_send 0x00000200L +#define SC_DEBUG_8__next_cycle_MASK 0x00000c00L +#define SC_DEBUG_8__ez_sample_ff_full_MASK 0x00001000L +#define SC_DEBUG_8__ez_sample_ff_full 0x00001000L +#define SC_DEBUG_8__rb_sc_samp_rtr_MASK 0x00002000L +#define SC_DEBUG_8__rb_sc_samp_rtr 0x00002000L +#define SC_DEBUG_8__num_samples_MASK 0x0000c000L +#define SC_DEBUG_8__last_quad_of_tile_MASK 0x00010000L +#define SC_DEBUG_8__last_quad_of_tile 0x00010000L +#define SC_DEBUG_8__last_quad_of_prim_MASK 0x00020000L +#define SC_DEBUG_8__last_quad_of_prim 0x00020000L +#define SC_DEBUG_8__first_quad_of_prim_MASK 0x00040000L +#define SC_DEBUG_8__first_quad_of_prim 0x00040000L +#define SC_DEBUG_8__sample_we_MASK 0x00080000L +#define SC_DEBUG_8__sample_we 0x00080000L +#define SC_DEBUG_8__fposition_MASK 0x00100000L +#define SC_DEBUG_8__fposition 0x00100000L +#define SC_DEBUG_8__event_id_MASK 0x03e00000L +#define SC_DEBUG_8__event_flag_MASK 0x04000000L +#define SC_DEBUG_8__event_flag 0x04000000L +#define SC_DEBUG_8__fw_prim_data_valid_MASK 0x08000000L +#define SC_DEBUG_8__fw_prim_data_valid 0x08000000L +#define SC_DEBUG_8__trigger_MASK 0x80000000L +#define SC_DEBUG_8__trigger 0x80000000L + +// SC_DEBUG_9 +#define SC_DEBUG_9__rb_sc_send_MASK 0x00000001L +#define SC_DEBUG_9__rb_sc_send 0x00000001L +#define SC_DEBUG_9__rb_sc_ez_mask_MASK 0x0000001eL +#define SC_DEBUG_9__fifo_data_ready_MASK 0x00000020L +#define SC_DEBUG_9__fifo_data_ready 0x00000020L +#define SC_DEBUG_9__early_z_enable_MASK 0x00000040L +#define SC_DEBUG_9__early_z_enable 0x00000040L +#define SC_DEBUG_9__mask_state_MASK 0x00000180L +#define SC_DEBUG_9__next_ez_mask_MASK 0x01fffe00L +#define SC_DEBUG_9__mask_ready_MASK 0x02000000L +#define SC_DEBUG_9__mask_ready 0x02000000L +#define SC_DEBUG_9__drop_sample_MASK 0x04000000L +#define SC_DEBUG_9__drop_sample 0x04000000L +#define SC_DEBUG_9__fetch_new_sample_data_MASK 0x08000000L +#define SC_DEBUG_9__fetch_new_sample_data 0x08000000L +#define SC_DEBUG_9__fetch_new_ez_sample_mask_MASK 0x10000000L +#define SC_DEBUG_9__fetch_new_ez_sample_mask 0x10000000L +#define SC_DEBUG_9__pkr_fetch_new_sample_data_MASK 0x20000000L +#define SC_DEBUG_9__pkr_fetch_new_sample_data 0x20000000L +#define SC_DEBUG_9__pkr_fetch_new_prim_data_MASK 0x40000000L +#define SC_DEBUG_9__pkr_fetch_new_prim_data 0x40000000L +#define SC_DEBUG_9__trigger_MASK 0x80000000L +#define SC_DEBUG_9__trigger 0x80000000L + +// SC_DEBUG_10 +#define SC_DEBUG_10__combined_sample_mask_MASK 0x0000ffffL +#define SC_DEBUG_10__trigger_MASK 0x80000000L +#define SC_DEBUG_10__trigger 0x80000000L + +// SC_DEBUG_11 +#define SC_DEBUG_11__ez_sample_data_ready_MASK 0x00000001L +#define SC_DEBUG_11__ez_sample_data_ready 0x00000001L +#define SC_DEBUG_11__pkr_fetch_new_sample_data_MASK 0x00000002L +#define SC_DEBUG_11__pkr_fetch_new_sample_data 0x00000002L +#define SC_DEBUG_11__ez_prim_data_ready_MASK 0x00000004L +#define SC_DEBUG_11__ez_prim_data_ready 0x00000004L +#define SC_DEBUG_11__pkr_fetch_new_prim_data_MASK 0x00000008L +#define SC_DEBUG_11__pkr_fetch_new_prim_data 0x00000008L +#define SC_DEBUG_11__iterator_input_fz_MASK 0x00000010L +#define SC_DEBUG_11__iterator_input_fz 0x00000010L +#define SC_DEBUG_11__packer_send_quads_MASK 0x00000020L +#define SC_DEBUG_11__packer_send_quads 0x00000020L +#define SC_DEBUG_11__packer_send_cmd_MASK 0x00000040L +#define SC_DEBUG_11__packer_send_cmd 0x00000040L +#define SC_DEBUG_11__packer_send_event_MASK 0x00000080L +#define SC_DEBUG_11__packer_send_event 0x00000080L +#define SC_DEBUG_11__next_state_MASK 0x00000700L +#define SC_DEBUG_11__state_MASK 0x00003800L +#define SC_DEBUG_11__stall_MASK 0x00004000L +#define SC_DEBUG_11__stall 0x00004000L +#define SC_DEBUG_11__trigger_MASK 0x80000000L +#define SC_DEBUG_11__trigger 0x80000000L + +// SC_DEBUG_12 +#define SC_DEBUG_12__SQ_iterator_free_buff_MASK 0x00000001L +#define SC_DEBUG_12__SQ_iterator_free_buff 0x00000001L +#define SC_DEBUG_12__event_id_MASK 0x0000003eL +#define SC_DEBUG_12__event_flag_MASK 0x00000040L +#define SC_DEBUG_12__event_flag 0x00000040L +#define SC_DEBUG_12__itercmdfifo_busy_nc_dly_MASK 0x00000080L +#define SC_DEBUG_12__itercmdfifo_busy_nc_dly 0x00000080L +#define SC_DEBUG_12__itercmdfifo_full_MASK 0x00000100L +#define SC_DEBUG_12__itercmdfifo_full 0x00000100L +#define SC_DEBUG_12__itercmdfifo_empty_MASK 0x00000200L +#define SC_DEBUG_12__itercmdfifo_empty 0x00000200L +#define SC_DEBUG_12__iter_ds_one_clk_command_MASK 0x00000400L +#define SC_DEBUG_12__iter_ds_one_clk_command 0x00000400L +#define SC_DEBUG_12__iter_ds_end_of_prim0_MASK 0x00000800L +#define SC_DEBUG_12__iter_ds_end_of_prim0 0x00000800L +#define SC_DEBUG_12__iter_ds_end_of_vector_MASK 0x00001000L +#define SC_DEBUG_12__iter_ds_end_of_vector 0x00001000L +#define SC_DEBUG_12__iter_qdhit0_MASK 0x00002000L +#define SC_DEBUG_12__iter_qdhit0 0x00002000L +#define SC_DEBUG_12__bc_use_centers_reg_MASK 0x00004000L +#define SC_DEBUG_12__bc_use_centers_reg 0x00004000L +#define SC_DEBUG_12__bc_output_xy_reg_MASK 0x00008000L +#define SC_DEBUG_12__bc_output_xy_reg 0x00008000L +#define SC_DEBUG_12__iter_phase_out_MASK 0x00030000L +#define SC_DEBUG_12__iter_phase_reg_MASK 0x000c0000L +#define SC_DEBUG_12__iterator_SP_valid_MASK 0x00100000L +#define SC_DEBUG_12__iterator_SP_valid 0x00100000L +#define SC_DEBUG_12__eopv_reg_MASK 0x00200000L +#define SC_DEBUG_12__eopv_reg 0x00200000L +#define SC_DEBUG_12__one_clk_cmd_reg_MASK 0x00400000L +#define SC_DEBUG_12__one_clk_cmd_reg 0x00400000L +#define SC_DEBUG_12__iter_dx_end_of_prim_MASK 0x00800000L +#define SC_DEBUG_12__iter_dx_end_of_prim 0x00800000L +#define SC_DEBUG_12__trigger_MASK 0x80000000L +#define SC_DEBUG_12__trigger 0x80000000L + +// GFX_COPY_STATE +#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x00000001L +#define GFX_COPY_STATE__SRC_STATE_ID 0x00000001L + +// VGT_DRAW_INITIATOR +#define VGT_DRAW_INITIATOR__PRIM_TYPE_MASK 0x0000003fL +#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x000000c0L +#define VGT_DRAW_INITIATOR__FACENESS_CULL_SELECT_MASK 0x00000300L +#define VGT_DRAW_INITIATOR__INDEX_SIZE_MASK 0x00000800L +#define VGT_DRAW_INITIATOR__INDEX_SIZE 0x00000800L +#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x00001000L +#define VGT_DRAW_INITIATOR__NOT_EOP 0x00001000L +#define VGT_DRAW_INITIATOR__SMALL_INDEX_MASK 0x00002000L +#define VGT_DRAW_INITIATOR__SMALL_INDEX 0x00002000L +#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE_MASK 0x00004000L +#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE 0x00004000L +#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE_MASK 0x00008000L +#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE 0x00008000L +#define VGT_DRAW_INITIATOR__NUM_INDICES_MASK 0xffff0000L + +// VGT_EVENT_INITIATOR +#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003fL + +// VGT_DMA_BASE +#define VGT_DMA_BASE__BASE_ADDR_MASK 0xffffffffL + +// VGT_DMA_SIZE +#define VGT_DMA_SIZE__NUM_WORDS_MASK 0x00ffffffL +#define VGT_DMA_SIZE__SWAP_MODE_MASK 0xc0000000L + +// VGT_BIN_BASE +#define VGT_BIN_BASE__BIN_BASE_ADDR_MASK 0xffffffffL + +// VGT_BIN_SIZE +#define VGT_BIN_SIZE__NUM_WORDS_MASK 0x00ffffffL +#define VGT_BIN_SIZE__FACENESS_FETCH_MASK 0x40000000L +#define VGT_BIN_SIZE__FACENESS_FETCH 0x40000000L +#define VGT_BIN_SIZE__FACENESS_RESET_MASK 0x80000000L +#define VGT_BIN_SIZE__FACENESS_RESET 0x80000000L + +// VGT_CURRENT_BIN_ID_MIN +#define VGT_CURRENT_BIN_ID_MIN__COLUMN_MASK 0x00000007L +#define VGT_CURRENT_BIN_ID_MIN__ROW_MASK 0x00000038L +#define VGT_CURRENT_BIN_ID_MIN__GUARD_BAND_MASK 0x000001c0L + +// VGT_CURRENT_BIN_ID_MAX +#define VGT_CURRENT_BIN_ID_MAX__COLUMN_MASK 0x00000007L +#define VGT_CURRENT_BIN_ID_MAX__ROW_MASK 0x00000038L +#define VGT_CURRENT_BIN_ID_MAX__GUARD_BAND_MASK 0x000001c0L + +// VGT_IMMED_DATA +#define VGT_IMMED_DATA__DATA_MASK 0xffffffffL + +// VGT_MAX_VTX_INDX +#define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0x00ffffffL + +// VGT_MIN_VTX_INDX +#define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0x00ffffffL + +// VGT_INDX_OFFSET +#define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0x00ffffffL + +// VGT_VERTEX_REUSE_BLOCK_CNTL +#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0x00000007L + +// VGT_OUT_DEALLOC_CNTL +#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x00000003L + +// VGT_MULTI_PRIM_IB_RESET_INDX +#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0x00ffffffL + +// VGT_ENHANCE +#define VGT_ENHANCE__MISC_MASK 0x0000ffffL + +// VGT_VTX_VECT_EJECT_REG +#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x0000001fL + +// VGT_LAST_COPY_STATE +#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x00000001L +#define VGT_LAST_COPY_STATE__SRC_STATE_ID 0x00000001L +#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x00010000L +#define VGT_LAST_COPY_STATE__DST_STATE_ID 0x00010000L + +// VGT_DEBUG_CNTL +#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX_MASK 0x0000001fL + +// VGT_DEBUG_DATA +#define VGT_DEBUG_DATA__DATA_MASK 0xffffffffL + +// VGT_CNTL_STATUS +#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x00000001L +#define VGT_CNTL_STATUS__VGT_BUSY 0x00000001L +#define VGT_CNTL_STATUS__VGT_DMA_BUSY_MASK 0x00000002L +#define VGT_CNTL_STATUS__VGT_DMA_BUSY 0x00000002L +#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY_MASK 0x00000004L +#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY 0x00000004L +#define VGT_CNTL_STATUS__VGT_GRP_BUSY_MASK 0x00000008L +#define VGT_CNTL_STATUS__VGT_GRP_BUSY 0x00000008L +#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x00000010L +#define VGT_CNTL_STATUS__VGT_VR_BUSY 0x00000010L +#define VGT_CNTL_STATUS__VGT_BIN_BUSY_MASK 0x00000020L +#define VGT_CNTL_STATUS__VGT_BIN_BUSY 0x00000020L +#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x00000040L +#define VGT_CNTL_STATUS__VGT_PT_BUSY 0x00000040L +#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x00000080L +#define VGT_CNTL_STATUS__VGT_OUT_BUSY 0x00000080L +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x00000100L +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY 0x00000100L + +// VGT_DEBUG_REG0 +#define VGT_DEBUG_REG0__te_grp_busy_MASK 0x00000001L +#define VGT_DEBUG_REG0__te_grp_busy 0x00000001L +#define VGT_DEBUG_REG0__pt_grp_busy_MASK 0x00000002L +#define VGT_DEBUG_REG0__pt_grp_busy 0x00000002L +#define VGT_DEBUG_REG0__vr_grp_busy_MASK 0x00000004L +#define VGT_DEBUG_REG0__vr_grp_busy 0x00000004L +#define VGT_DEBUG_REG0__dma_request_busy_MASK 0x00000008L +#define VGT_DEBUG_REG0__dma_request_busy 0x00000008L +#define VGT_DEBUG_REG0__out_busy_MASK 0x00000010L +#define VGT_DEBUG_REG0__out_busy 0x00000010L +#define VGT_DEBUG_REG0__grp_backend_busy_MASK 0x00000020L +#define VGT_DEBUG_REG0__grp_backend_busy 0x00000020L +#define VGT_DEBUG_REG0__grp_busy_MASK 0x00000040L +#define VGT_DEBUG_REG0__grp_busy 0x00000040L +#define VGT_DEBUG_REG0__dma_busy_MASK 0x00000080L +#define VGT_DEBUG_REG0__dma_busy 0x00000080L +#define VGT_DEBUG_REG0__rbiu_dma_request_busy_MASK 0x00000100L +#define VGT_DEBUG_REG0__rbiu_dma_request_busy 0x00000100L +#define VGT_DEBUG_REG0__rbiu_busy_MASK 0x00000200L +#define VGT_DEBUG_REG0__rbiu_busy 0x00000200L +#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended_MASK 0x00000400L +#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended 0x00000400L +#define VGT_DEBUG_REG0__vgt_no_dma_busy_MASK 0x00000800L +#define VGT_DEBUG_REG0__vgt_no_dma_busy 0x00000800L +#define VGT_DEBUG_REG0__vgt_busy_extended_MASK 0x00001000L +#define VGT_DEBUG_REG0__vgt_busy_extended 0x00001000L +#define VGT_DEBUG_REG0__vgt_busy_MASK 0x00002000L +#define VGT_DEBUG_REG0__vgt_busy 0x00002000L +#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out_MASK 0x00004000L +#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out 0x00004000L +#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy_MASK 0x00008000L +#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy 0x00008000L +#define VGT_DEBUG_REG0__VGT_RBBM_busy_MASK 0x00010000L +#define VGT_DEBUG_REG0__VGT_RBBM_busy 0x00010000L + +// VGT_DEBUG_REG1 +#define VGT_DEBUG_REG1__out_te_data_read_MASK 0x00000001L +#define VGT_DEBUG_REG1__out_te_data_read 0x00000001L +#define VGT_DEBUG_REG1__te_out_data_valid_MASK 0x00000002L +#define VGT_DEBUG_REG1__te_out_data_valid 0x00000002L +#define VGT_DEBUG_REG1__out_pt_prim_read_MASK 0x00000004L +#define VGT_DEBUG_REG1__out_pt_prim_read 0x00000004L +#define VGT_DEBUG_REG1__pt_out_prim_valid_MASK 0x00000008L +#define VGT_DEBUG_REG1__pt_out_prim_valid 0x00000008L +#define VGT_DEBUG_REG1__out_pt_data_read_MASK 0x00000010L +#define VGT_DEBUG_REG1__out_pt_data_read 0x00000010L +#define VGT_DEBUG_REG1__pt_out_indx_valid_MASK 0x00000020L +#define VGT_DEBUG_REG1__pt_out_indx_valid 0x00000020L +#define VGT_DEBUG_REG1__out_vr_prim_read_MASK 0x00000040L +#define VGT_DEBUG_REG1__out_vr_prim_read 0x00000040L +#define VGT_DEBUG_REG1__vr_out_prim_valid_MASK 0x00000080L +#define VGT_DEBUG_REG1__vr_out_prim_valid 0x00000080L +#define VGT_DEBUG_REG1__out_vr_indx_read_MASK 0x00000100L +#define VGT_DEBUG_REG1__out_vr_indx_read 0x00000100L +#define VGT_DEBUG_REG1__vr_out_indx_valid_MASK 0x00000200L +#define VGT_DEBUG_REG1__vr_out_indx_valid 0x00000200L +#define VGT_DEBUG_REG1__te_grp_read_MASK 0x00000400L +#define VGT_DEBUG_REG1__te_grp_read 0x00000400L +#define VGT_DEBUG_REG1__grp_te_valid_MASK 0x00000800L +#define VGT_DEBUG_REG1__grp_te_valid 0x00000800L +#define VGT_DEBUG_REG1__pt_grp_read_MASK 0x00001000L +#define VGT_DEBUG_REG1__pt_grp_read 0x00001000L +#define VGT_DEBUG_REG1__grp_pt_valid_MASK 0x00002000L +#define VGT_DEBUG_REG1__grp_pt_valid 0x00002000L +#define VGT_DEBUG_REG1__vr_grp_read_MASK 0x00004000L +#define VGT_DEBUG_REG1__vr_grp_read 0x00004000L +#define VGT_DEBUG_REG1__grp_vr_valid_MASK 0x00008000L +#define VGT_DEBUG_REG1__grp_vr_valid 0x00008000L +#define VGT_DEBUG_REG1__grp_dma_read_MASK 0x00010000L +#define VGT_DEBUG_REG1__grp_dma_read 0x00010000L +#define VGT_DEBUG_REG1__dma_grp_valid_MASK 0x00020000L +#define VGT_DEBUG_REG1__dma_grp_valid 0x00020000L +#define VGT_DEBUG_REG1__grp_rbiu_di_read_MASK 0x00040000L +#define VGT_DEBUG_REG1__grp_rbiu_di_read 0x00040000L +#define VGT_DEBUG_REG1__rbiu_grp_di_valid_MASK 0x00080000L +#define VGT_DEBUG_REG1__rbiu_grp_di_valid 0x00080000L +#define VGT_DEBUG_REG1__MH_VGT_rtr_MASK 0x00100000L +#define VGT_DEBUG_REG1__MH_VGT_rtr 0x00100000L +#define VGT_DEBUG_REG1__VGT_MH_send_MASK 0x00200000L +#define VGT_DEBUG_REG1__VGT_MH_send 0x00200000L +#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr_MASK 0x00400000L +#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr 0x00400000L +#define VGT_DEBUG_REG1__VGT_PA_clip_s_send_MASK 0x00800000L +#define VGT_DEBUG_REG1__VGT_PA_clip_s_send 0x00800000L +#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr_MASK 0x01000000L +#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr 0x01000000L +#define VGT_DEBUG_REG1__VGT_PA_clip_p_send_MASK 0x02000000L +#define VGT_DEBUG_REG1__VGT_PA_clip_p_send 0x02000000L +#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr_MASK 0x04000000L +#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr 0x04000000L +#define VGT_DEBUG_REG1__VGT_PA_clip_v_send_MASK 0x08000000L +#define VGT_DEBUG_REG1__VGT_PA_clip_v_send 0x08000000L +#define VGT_DEBUG_REG1__SQ_VGT_rtr_MASK 0x10000000L +#define VGT_DEBUG_REG1__SQ_VGT_rtr 0x10000000L +#define VGT_DEBUG_REG1__VGT_SQ_send_MASK 0x20000000L +#define VGT_DEBUG_REG1__VGT_SQ_send 0x20000000L +#define VGT_DEBUG_REG1__mh_vgt_tag_7_q_MASK 0x40000000L +#define VGT_DEBUG_REG1__mh_vgt_tag_7_q 0x40000000L + +// VGT_DEBUG_REG3 +#define VGT_DEBUG_REG3__vgt_clk_en_MASK 0x00000001L +#define VGT_DEBUG_REG3__vgt_clk_en 0x00000001L +#define VGT_DEBUG_REG3__reg_fifos_clk_en_MASK 0x00000002L +#define VGT_DEBUG_REG3__reg_fifos_clk_en 0x00000002L + +// VGT_DEBUG_REG6 +#define VGT_DEBUG_REG6__shifter_byte_count_q_MASK 0x0000001fL +#define VGT_DEBUG_REG6__right_word_indx_q_MASK 0x000003e0L +#define VGT_DEBUG_REG6__input_data_valid_MASK 0x00000400L +#define VGT_DEBUG_REG6__input_data_valid 0x00000400L +#define VGT_DEBUG_REG6__input_data_xfer_MASK 0x00000800L +#define VGT_DEBUG_REG6__input_data_xfer 0x00000800L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_q_MASK 0x00001000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_q 0x00001000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_d_MASK 0x00002000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_d 0x00002000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d_MASK 0x00004000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d 0x00004000L +#define VGT_DEBUG_REG6__space_avail_from_shift_MASK 0x00008000L +#define VGT_DEBUG_REG6__space_avail_from_shift 0x00008000L +#define VGT_DEBUG_REG6__shifter_first_load_MASK 0x00010000L +#define VGT_DEBUG_REG6__shifter_first_load 0x00010000L +#define VGT_DEBUG_REG6__di_state_sel_q_MASK 0x00020000L +#define VGT_DEBUG_REG6__di_state_sel_q 0x00020000L +#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q_MASK 0x00040000L +#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q 0x00040000L +#define VGT_DEBUG_REG6__di_first_group_flag_q_MASK 0x00080000L +#define VGT_DEBUG_REG6__di_first_group_flag_q 0x00080000L +#define VGT_DEBUG_REG6__di_event_flag_q_MASK 0x00100000L +#define VGT_DEBUG_REG6__di_event_flag_q 0x00100000L +#define VGT_DEBUG_REG6__read_draw_initiator_MASK 0x00200000L +#define VGT_DEBUG_REG6__read_draw_initiator 0x00200000L +#define VGT_DEBUG_REG6__loading_di_requires_shifter_MASK 0x00400000L +#define VGT_DEBUG_REG6__loading_di_requires_shifter 0x00400000L +#define VGT_DEBUG_REG6__last_shift_of_packet_MASK 0x00800000L +#define VGT_DEBUG_REG6__last_shift_of_packet 0x00800000L +#define VGT_DEBUG_REG6__last_decr_of_packet_MASK 0x01000000L +#define VGT_DEBUG_REG6__last_decr_of_packet 0x01000000L +#define VGT_DEBUG_REG6__extract_vector_MASK 0x02000000L +#define VGT_DEBUG_REG6__extract_vector 0x02000000L +#define VGT_DEBUG_REG6__shift_vect_rtr_MASK 0x04000000L +#define VGT_DEBUG_REG6__shift_vect_rtr 0x04000000L +#define VGT_DEBUG_REG6__destination_rtr_MASK 0x08000000L +#define VGT_DEBUG_REG6__destination_rtr 0x08000000L +#define VGT_DEBUG_REG6__grp_trigger_MASK 0x10000000L +#define VGT_DEBUG_REG6__grp_trigger 0x10000000L + +// VGT_DEBUG_REG7 +#define VGT_DEBUG_REG7__di_index_counter_q_MASK 0x0000ffffL +#define VGT_DEBUG_REG7__shift_amount_no_extract_MASK 0x000f0000L +#define VGT_DEBUG_REG7__shift_amount_extract_MASK 0x00f00000L +#define VGT_DEBUG_REG7__di_prim_type_q_MASK 0x3f000000L +#define VGT_DEBUG_REG7__current_source_sel_MASK 0xc0000000L + +// VGT_DEBUG_REG8 +#define VGT_DEBUG_REG8__current_source_sel_MASK 0x00000003L +#define VGT_DEBUG_REG8__left_word_indx_q_MASK 0x0000007cL +#define VGT_DEBUG_REG8__input_data_cnt_MASK 0x00000f80L +#define VGT_DEBUG_REG8__input_data_lsw_MASK 0x0001f000L +#define VGT_DEBUG_REG8__input_data_msw_MASK 0x003e0000L +#define VGT_DEBUG_REG8__next_small_stride_shift_limit_q_MASK 0x07c00000L +#define VGT_DEBUG_REG8__current_small_stride_shift_limit_q_MASK 0xf8000000L + +// VGT_DEBUG_REG9 +#define VGT_DEBUG_REG9__next_stride_q_MASK 0x0000001fL +#define VGT_DEBUG_REG9__next_stride_d_MASK 0x000003e0L +#define VGT_DEBUG_REG9__current_shift_q_MASK 0x00007c00L +#define VGT_DEBUG_REG9__current_shift_d_MASK 0x000f8000L +#define VGT_DEBUG_REG9__current_stride_q_MASK 0x01f00000L +#define VGT_DEBUG_REG9__current_stride_d_MASK 0x3e000000L +#define VGT_DEBUG_REG9__grp_trigger_MASK 0x40000000L +#define VGT_DEBUG_REG9__grp_trigger 0x40000000L + +// VGT_DEBUG_REG10 +#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0_MASK 0x00000001L +#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0 0x00000001L +#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0_MASK 0x00000002L +#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0 0x00000002L +#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0_MASK 0x00000004L +#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0 0x00000004L +#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0_MASK 0x00000008L +#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0 0x00000008L +#define VGT_DEBUG_REG10__di_state_sel_q_MASK 0x00000010L +#define VGT_DEBUG_REG10__di_state_sel_q 0x00000010L +#define VGT_DEBUG_REG10__last_decr_of_packet_MASK 0x00000020L +#define VGT_DEBUG_REG10__last_decr_of_packet 0x00000020L +#define VGT_DEBUG_REG10__bin_valid_MASK 0x00000040L +#define VGT_DEBUG_REG10__bin_valid 0x00000040L +#define VGT_DEBUG_REG10__read_block_MASK 0x00000080L +#define VGT_DEBUG_REG10__read_block 0x00000080L +#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read_MASK 0x00000100L +#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read 0x00000100L +#define VGT_DEBUG_REG10__last_bit_enable_q_MASK 0x00000200L +#define VGT_DEBUG_REG10__last_bit_enable_q 0x00000200L +#define VGT_DEBUG_REG10__last_bit_end_di_q_MASK 0x00000400L +#define VGT_DEBUG_REG10__last_bit_end_di_q 0x00000400L +#define VGT_DEBUG_REG10__selected_data_MASK 0x0007f800L +#define VGT_DEBUG_REG10__mask_input_data_MASK 0x07f80000L +#define VGT_DEBUG_REG10__gap_q_MASK 0x08000000L +#define VGT_DEBUG_REG10__gap_q 0x08000000L +#define VGT_DEBUG_REG10__temp_mini_reset_z_MASK 0x10000000L +#define VGT_DEBUG_REG10__temp_mini_reset_z 0x10000000L +#define VGT_DEBUG_REG10__temp_mini_reset_y_MASK 0x20000000L +#define VGT_DEBUG_REG10__temp_mini_reset_y 0x20000000L +#define VGT_DEBUG_REG10__temp_mini_reset_x_MASK 0x40000000L +#define VGT_DEBUG_REG10__temp_mini_reset_x 0x40000000L +#define VGT_DEBUG_REG10__grp_trigger_MASK 0x80000000L +#define VGT_DEBUG_REG10__grp_trigger 0x80000000L + +// VGT_DEBUG_REG12 +#define VGT_DEBUG_REG12__shifter_byte_count_q_MASK 0x0000001fL +#define VGT_DEBUG_REG12__right_word_indx_q_MASK 0x000003e0L +#define VGT_DEBUG_REG12__input_data_valid_MASK 0x00000400L +#define VGT_DEBUG_REG12__input_data_valid 0x00000400L +#define VGT_DEBUG_REG12__input_data_xfer_MASK 0x00000800L +#define VGT_DEBUG_REG12__input_data_xfer 0x00000800L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_q_MASK 0x00001000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_q 0x00001000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_d_MASK 0x00002000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_d 0x00002000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d_MASK 0x00004000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d 0x00004000L +#define VGT_DEBUG_REG12__space_avail_from_shift_MASK 0x00008000L +#define VGT_DEBUG_REG12__space_avail_from_shift 0x00008000L +#define VGT_DEBUG_REG12__shifter_first_load_MASK 0x00010000L +#define VGT_DEBUG_REG12__shifter_first_load 0x00010000L +#define VGT_DEBUG_REG12__di_state_sel_q_MASK 0x00020000L +#define VGT_DEBUG_REG12__di_state_sel_q 0x00020000L +#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q_MASK 0x00040000L +#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q 0x00040000L +#define VGT_DEBUG_REG12__di_first_group_flag_q_MASK 0x00080000L +#define VGT_DEBUG_REG12__di_first_group_flag_q 0x00080000L +#define VGT_DEBUG_REG12__di_event_flag_q_MASK 0x00100000L +#define VGT_DEBUG_REG12__di_event_flag_q 0x00100000L +#define VGT_DEBUG_REG12__read_draw_initiator_MASK 0x00200000L +#define VGT_DEBUG_REG12__read_draw_initiator 0x00200000L +#define VGT_DEBUG_REG12__loading_di_requires_shifter_MASK 0x00400000L +#define VGT_DEBUG_REG12__loading_di_requires_shifter 0x00400000L +#define VGT_DEBUG_REG12__last_shift_of_packet_MASK 0x00800000L +#define VGT_DEBUG_REG12__last_shift_of_packet 0x00800000L +#define VGT_DEBUG_REG12__last_decr_of_packet_MASK 0x01000000L +#define VGT_DEBUG_REG12__last_decr_of_packet 0x01000000L +#define VGT_DEBUG_REG12__extract_vector_MASK 0x02000000L +#define VGT_DEBUG_REG12__extract_vector 0x02000000L +#define VGT_DEBUG_REG12__shift_vect_rtr_MASK 0x04000000L +#define VGT_DEBUG_REG12__shift_vect_rtr 0x04000000L +#define VGT_DEBUG_REG12__destination_rtr_MASK 0x08000000L +#define VGT_DEBUG_REG12__destination_rtr 0x08000000L +#define VGT_DEBUG_REG12__bgrp_trigger_MASK 0x10000000L +#define VGT_DEBUG_REG12__bgrp_trigger 0x10000000L + +// VGT_DEBUG_REG13 +#define VGT_DEBUG_REG13__di_index_counter_q_MASK 0x0000ffffL +#define VGT_DEBUG_REG13__shift_amount_no_extract_MASK 0x000f0000L +#define VGT_DEBUG_REG13__shift_amount_extract_MASK 0x00f00000L +#define VGT_DEBUG_REG13__di_prim_type_q_MASK 0x3f000000L +#define VGT_DEBUG_REG13__current_source_sel_MASK 0xc0000000L + +// VGT_DEBUG_REG14 +#define VGT_DEBUG_REG14__current_source_sel_MASK 0x00000003L +#define VGT_DEBUG_REG14__left_word_indx_q_MASK 0x0000007cL +#define VGT_DEBUG_REG14__input_data_cnt_MASK 0x00000f80L +#define VGT_DEBUG_REG14__input_data_lsw_MASK 0x0001f000L +#define VGT_DEBUG_REG14__input_data_msw_MASK 0x003e0000L +#define VGT_DEBUG_REG14__next_small_stride_shift_limit_q_MASK 0x07c00000L +#define VGT_DEBUG_REG14__current_small_stride_shift_limit_q_MASK 0xf8000000L + +// VGT_DEBUG_REG15 +#define VGT_DEBUG_REG15__next_stride_q_MASK 0x0000001fL +#define VGT_DEBUG_REG15__next_stride_d_MASK 0x000003e0L +#define VGT_DEBUG_REG15__current_shift_q_MASK 0x00007c00L +#define VGT_DEBUG_REG15__current_shift_d_MASK 0x000f8000L +#define VGT_DEBUG_REG15__current_stride_q_MASK 0x01f00000L +#define VGT_DEBUG_REG15__current_stride_d_MASK 0x3e000000L +#define VGT_DEBUG_REG15__bgrp_trigger_MASK 0x40000000L +#define VGT_DEBUG_REG15__bgrp_trigger 0x40000000L + +// VGT_DEBUG_REG16 +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full_MASK 0x00000001L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full 0x00000001L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty_MASK 0x00000002L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty 0x00000002L +#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read_MASK 0x00000004L +#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read 0x00000004L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we_MASK 0x00000008L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we 0x00000008L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full_MASK 0x00000010L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full 0x00000010L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty_MASK 0x00000020L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty 0x00000020L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q_MASK 0x00000040L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q 0x00000040L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we_MASK 0x00000080L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we 0x00000080L +#define VGT_DEBUG_REG16__bgrp_dma_mask_kill_MASK 0x00000100L +#define VGT_DEBUG_REG16__bgrp_dma_mask_kill 0x00000100L +#define VGT_DEBUG_REG16__bgrp_grp_bin_valid_MASK 0x00000200L +#define VGT_DEBUG_REG16__bgrp_grp_bin_valid 0x00000200L +#define VGT_DEBUG_REG16__rst_last_bit_MASK 0x00000400L +#define VGT_DEBUG_REG16__rst_last_bit 0x00000400L +#define VGT_DEBUG_REG16__current_state_q_MASK 0x00000800L +#define VGT_DEBUG_REG16__current_state_q 0x00000800L +#define VGT_DEBUG_REG16__old_state_q_MASK 0x00001000L +#define VGT_DEBUG_REG16__old_state_q 0x00001000L +#define VGT_DEBUG_REG16__old_state_en_MASK 0x00002000L +#define VGT_DEBUG_REG16__old_state_en 0x00002000L +#define VGT_DEBUG_REG16__prev_last_bit_q_MASK 0x00004000L +#define VGT_DEBUG_REG16__prev_last_bit_q 0x00004000L +#define VGT_DEBUG_REG16__dbl_last_bit_q_MASK 0x00008000L +#define VGT_DEBUG_REG16__dbl_last_bit_q 0x00008000L +#define VGT_DEBUG_REG16__last_bit_block_q_MASK 0x00010000L +#define VGT_DEBUG_REG16__last_bit_block_q 0x00010000L +#define VGT_DEBUG_REG16__ast_bit_block2_q_MASK 0x00020000L +#define VGT_DEBUG_REG16__ast_bit_block2_q 0x00020000L +#define VGT_DEBUG_REG16__load_empty_reg_MASK 0x00040000L +#define VGT_DEBUG_REG16__load_empty_reg 0x00040000L +#define VGT_DEBUG_REG16__bgrp_grp_byte_mask_rdata_MASK 0x07f80000L +#define VGT_DEBUG_REG16__dma_bgrp_dma_data_fifo_rptr_MASK 0x18000000L +#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable_MASK 0x20000000L +#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable 0x20000000L +#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q_MASK 0x40000000L +#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q 0x40000000L +#define VGT_DEBUG_REG16__bgrp_trigger_MASK 0x80000000L +#define VGT_DEBUG_REG16__bgrp_trigger 0x80000000L + +// VGT_DEBUG_REG17 +#define VGT_DEBUG_REG17__save_read_q_MASK 0x00000001L +#define VGT_DEBUG_REG17__save_read_q 0x00000001L +#define VGT_DEBUG_REG17__extend_read_q_MASK 0x00000002L +#define VGT_DEBUG_REG17__extend_read_q 0x00000002L +#define VGT_DEBUG_REG17__grp_indx_size_MASK 0x0000000cL +#define VGT_DEBUG_REG17__cull_prim_true_MASK 0x00000010L +#define VGT_DEBUG_REG17__cull_prim_true 0x00000010L +#define VGT_DEBUG_REG17__reset_bit2_q_MASK 0x00000020L +#define VGT_DEBUG_REG17__reset_bit2_q 0x00000020L +#define VGT_DEBUG_REG17__reset_bit1_q_MASK 0x00000040L +#define VGT_DEBUG_REG17__reset_bit1_q 0x00000040L +#define VGT_DEBUG_REG17__first_reg_first_q_MASK 0x00000080L +#define VGT_DEBUG_REG17__first_reg_first_q 0x00000080L +#define VGT_DEBUG_REG17__check_second_reg_MASK 0x00000100L +#define VGT_DEBUG_REG17__check_second_reg 0x00000100L +#define VGT_DEBUG_REG17__check_first_reg_MASK 0x00000200L +#define VGT_DEBUG_REG17__check_first_reg 0x00000200L +#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata_MASK 0x00000400L +#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata 0x00000400L +#define VGT_DEBUG_REG17__save_cull_fetch_data2_q_MASK 0x00000800L +#define VGT_DEBUG_REG17__save_cull_fetch_data2_q 0x00000800L +#define VGT_DEBUG_REG17__save_cull_fetch_data1_q_MASK 0x00001000L +#define VGT_DEBUG_REG17__save_cull_fetch_data1_q 0x00001000L +#define VGT_DEBUG_REG17__save_byte_mask_data2_q_MASK 0x00002000L +#define VGT_DEBUG_REG17__save_byte_mask_data2_q 0x00002000L +#define VGT_DEBUG_REG17__save_byte_mask_data1_q_MASK 0x00004000L +#define VGT_DEBUG_REG17__save_byte_mask_data1_q 0x00004000L +#define VGT_DEBUG_REG17__to_second_reg_q_MASK 0x00008000L +#define VGT_DEBUG_REG17__to_second_reg_q 0x00008000L +#define VGT_DEBUG_REG17__roll_over_msk_q_MASK 0x00010000L +#define VGT_DEBUG_REG17__roll_over_msk_q 0x00010000L +#define VGT_DEBUG_REG17__max_msk_ptr_q_MASK 0x00fe0000L +#define VGT_DEBUG_REG17__min_msk_ptr_q_MASK 0x7f000000L +#define VGT_DEBUG_REG17__bgrp_trigger_MASK 0x80000000L +#define VGT_DEBUG_REG17__bgrp_trigger 0x80000000L + +// VGT_DEBUG_REG18 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_raddr_MASK 0x0000003fL +#define VGT_DEBUG_REG18__dma_data_fifo_mem_waddr_MASK 0x00000fc0L +#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re_MASK 0x00001000L +#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re 0x00001000L +#define VGT_DEBUG_REG18__dma_bgrp_dma_data_fifo_rptr_MASK 0x00006000L +#define VGT_DEBUG_REG18__dma_mem_full_MASK 0x00008000L +#define VGT_DEBUG_REG18__dma_mem_full 0x00008000L +#define VGT_DEBUG_REG18__dma_ram_re_MASK 0x00010000L +#define VGT_DEBUG_REG18__dma_ram_re 0x00010000L +#define VGT_DEBUG_REG18__dma_ram_we_MASK 0x00020000L +#define VGT_DEBUG_REG18__dma_ram_we 0x00020000L +#define VGT_DEBUG_REG18__dma_mem_empty_MASK 0x00040000L +#define VGT_DEBUG_REG18__dma_mem_empty 0x00040000L +#define VGT_DEBUG_REG18__dma_data_fifo_mem_re_MASK 0x00080000L +#define VGT_DEBUG_REG18__dma_data_fifo_mem_re 0x00080000L +#define VGT_DEBUG_REG18__dma_data_fifo_mem_we_MASK 0x00100000L +#define VGT_DEBUG_REG18__dma_data_fifo_mem_we 0x00100000L +#define VGT_DEBUG_REG18__bin_mem_full_MASK 0x00200000L +#define VGT_DEBUG_REG18__bin_mem_full 0x00200000L +#define VGT_DEBUG_REG18__bin_ram_we_MASK 0x00400000L +#define VGT_DEBUG_REG18__bin_ram_we 0x00400000L +#define VGT_DEBUG_REG18__bin_ram_re_MASK 0x00800000L +#define VGT_DEBUG_REG18__bin_ram_re 0x00800000L +#define VGT_DEBUG_REG18__bin_mem_empty_MASK 0x01000000L +#define VGT_DEBUG_REG18__bin_mem_empty 0x01000000L +#define VGT_DEBUG_REG18__start_bin_req_MASK 0x02000000L +#define VGT_DEBUG_REG18__start_bin_req 0x02000000L +#define VGT_DEBUG_REG18__fetch_cull_not_used_MASK 0x04000000L +#define VGT_DEBUG_REG18__fetch_cull_not_used 0x04000000L +#define VGT_DEBUG_REG18__dma_req_xfer_MASK 0x08000000L +#define VGT_DEBUG_REG18__dma_req_xfer 0x08000000L +#define VGT_DEBUG_REG18__have_valid_bin_req_MASK 0x10000000L +#define VGT_DEBUG_REG18__have_valid_bin_req 0x10000000L +#define VGT_DEBUG_REG18__have_valid_dma_req_MASK 0x20000000L +#define VGT_DEBUG_REG18__have_valid_dma_req 0x20000000L +#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable_MASK 0x40000000L +#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable 0x40000000L +#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable_MASK 0x80000000L +#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable 0x80000000L + +// VGT_DEBUG_REG20 +#define VGT_DEBUG_REG20__prim_side_indx_valid_MASK 0x00000001L +#define VGT_DEBUG_REG20__prim_side_indx_valid 0x00000001L +#define VGT_DEBUG_REG20__indx_side_fifo_empty_MASK 0x00000002L +#define VGT_DEBUG_REG20__indx_side_fifo_empty 0x00000002L +#define VGT_DEBUG_REG20__indx_side_fifo_re_MASK 0x00000004L +#define VGT_DEBUG_REG20__indx_side_fifo_re 0x00000004L +#define VGT_DEBUG_REG20__indx_side_fifo_we_MASK 0x00000008L +#define VGT_DEBUG_REG20__indx_side_fifo_we 0x00000008L +#define VGT_DEBUG_REG20__indx_side_fifo_full_MASK 0x00000010L +#define VGT_DEBUG_REG20__indx_side_fifo_full 0x00000010L +#define VGT_DEBUG_REG20__prim_buffer_empty_MASK 0x00000020L +#define VGT_DEBUG_REG20__prim_buffer_empty 0x00000020L +#define VGT_DEBUG_REG20__prim_buffer_re_MASK 0x00000040L +#define VGT_DEBUG_REG20__prim_buffer_re 0x00000040L +#define VGT_DEBUG_REG20__prim_buffer_we_MASK 0x00000080L +#define VGT_DEBUG_REG20__prim_buffer_we 0x00000080L +#define VGT_DEBUG_REG20__prim_buffer_full_MASK 0x00000100L +#define VGT_DEBUG_REG20__prim_buffer_full 0x00000100L +#define VGT_DEBUG_REG20__indx_buffer_empty_MASK 0x00000200L +#define VGT_DEBUG_REG20__indx_buffer_empty 0x00000200L +#define VGT_DEBUG_REG20__indx_buffer_re_MASK 0x00000400L +#define VGT_DEBUG_REG20__indx_buffer_re 0x00000400L +#define VGT_DEBUG_REG20__indx_buffer_we_MASK 0x00000800L +#define VGT_DEBUG_REG20__indx_buffer_we 0x00000800L +#define VGT_DEBUG_REG20__indx_buffer_full_MASK 0x00001000L +#define VGT_DEBUG_REG20__indx_buffer_full 0x00001000L +#define VGT_DEBUG_REG20__hold_prim_MASK 0x00002000L +#define VGT_DEBUG_REG20__hold_prim 0x00002000L +#define VGT_DEBUG_REG20__sent_cnt_MASK 0x0003c000L +#define VGT_DEBUG_REG20__start_of_vtx_vector_MASK 0x00040000L +#define VGT_DEBUG_REG20__start_of_vtx_vector 0x00040000L +#define VGT_DEBUG_REG20__clip_s_pre_hold_prim_MASK 0x00080000L +#define VGT_DEBUG_REG20__clip_s_pre_hold_prim 0x00080000L +#define VGT_DEBUG_REG20__clip_p_pre_hold_prim_MASK 0x00100000L +#define VGT_DEBUG_REG20__clip_p_pre_hold_prim 0x00100000L +#define VGT_DEBUG_REG20__buffered_prim_type_event_MASK 0x03e00000L +#define VGT_DEBUG_REG20__out_trigger_MASK 0x04000000L +#define VGT_DEBUG_REG20__out_trigger 0x04000000L + +// VGT_DEBUG_REG21 +#define VGT_DEBUG_REG21__null_terminate_vtx_vector_MASK 0x00000001L +#define VGT_DEBUG_REG21__null_terminate_vtx_vector 0x00000001L +#define VGT_DEBUG_REG21__prim_end_of_vtx_vect_flags_MASK 0x0000000eL +#define VGT_DEBUG_REG21__alloc_counter_q_MASK 0x00000070L +#define VGT_DEBUG_REG21__curr_slot_in_vtx_vect_q_MASK 0x00000380L +#define VGT_DEBUG_REG21__int_vtx_counter_q_MASK 0x00003c00L +#define VGT_DEBUG_REG21__curr_dealloc_distance_q_MASK 0x0003c000L +#define VGT_DEBUG_REG21__new_packet_q_MASK 0x00040000L +#define VGT_DEBUG_REG21__new_packet_q 0x00040000L +#define VGT_DEBUG_REG21__new_allocate_q_MASK 0x00080000L +#define VGT_DEBUG_REG21__new_allocate_q 0x00080000L +#define VGT_DEBUG_REG21__num_new_unique_rel_indx_MASK 0x00300000L +#define VGT_DEBUG_REG21__inserted_null_prim_q_MASK 0x00400000L +#define VGT_DEBUG_REG21__inserted_null_prim_q 0x00400000L +#define VGT_DEBUG_REG21__insert_null_prim_MASK 0x00800000L +#define VGT_DEBUG_REG21__insert_null_prim 0x00800000L +#define VGT_DEBUG_REG21__buffered_prim_eop_mux_MASK 0x01000000L +#define VGT_DEBUG_REG21__buffered_prim_eop_mux 0x01000000L +#define VGT_DEBUG_REG21__prim_buffer_empty_mux_MASK 0x02000000L +#define VGT_DEBUG_REG21__prim_buffer_empty_mux 0x02000000L +#define VGT_DEBUG_REG21__buffered_thread_size_MASK 0x04000000L +#define VGT_DEBUG_REG21__buffered_thread_size 0x04000000L +#define VGT_DEBUG_REG21__out_trigger_MASK 0x80000000L +#define VGT_DEBUG_REG21__out_trigger 0x80000000L + +// VGT_CRC_SQ_DATA +#define VGT_CRC_SQ_DATA__CRC_MASK 0xffffffffL + +// VGT_CRC_SQ_CTRL +#define VGT_CRC_SQ_CTRL__CRC_MASK 0xffffffffL + +// VGT_PERFCOUNTER0_SELECT +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// VGT_PERFCOUNTER1_SELECT +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL + +// VGT_PERFCOUNTER2_SELECT +#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL + +// VGT_PERFCOUNTER3_SELECT +#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL + +// VGT_PERFCOUNTER0_LOW +#define VGT_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// VGT_PERFCOUNTER1_LOW +#define VGT_PERFCOUNTER1_LOW__PERF_COUNT_MASK 0xffffffffL + +// VGT_PERFCOUNTER2_LOW +#define VGT_PERFCOUNTER2_LOW__PERF_COUNT_MASK 0xffffffffL + +// VGT_PERFCOUNTER3_LOW +#define VGT_PERFCOUNTER3_LOW__PERF_COUNT_MASK 0xffffffffL + +// VGT_PERFCOUNTER0_HI +#define VGT_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// VGT_PERFCOUNTER1_HI +#define VGT_PERFCOUNTER1_HI__PERF_COUNT_MASK 0x0000ffffL + +// VGT_PERFCOUNTER2_HI +#define VGT_PERFCOUNTER2_HI__PERF_COUNT_MASK 0x0000ffffL + +// VGT_PERFCOUNTER3_HI +#define VGT_PERFCOUNTER3_HI__PERF_COUNT_MASK 0x0000ffffL + +// TC_CNTL_STATUS +#define TC_CNTL_STATUS__L2_INVALIDATE_MASK 0x00000001L +#define TC_CNTL_STATUS__L2_INVALIDATE 0x00000001L +#define TC_CNTL_STATUS__TC_L2_HIT_MISS_MASK 0x000c0000L +#define TC_CNTL_STATUS__TC_BUSY_MASK 0x80000000L +#define TC_CNTL_STATUS__TC_BUSY 0x80000000L + +// TCR_CHICKEN +#define TCR_CHICKEN__SPARE_MASK 0xffffffffL + +// TCF_CHICKEN +#define TCF_CHICKEN__SPARE_MASK 0xffffffffL + +// TCM_CHICKEN +#define TCM_CHICKEN__TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK 0x000000ffL +#define TCM_CHICKEN__ETC_COLOR_ENDIAN_MASK 0x00000100L +#define TCM_CHICKEN__ETC_COLOR_ENDIAN 0x00000100L +#define TCM_CHICKEN__SPARE_MASK 0xfffffe00L + +// TCR_PERFCOUNTER0_SELECT +#define TCR_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCR_PERFCOUNTER1_SELECT +#define TCR_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCR_PERFCOUNTER0_HI +#define TCR_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCR_PERFCOUNTER1_HI +#define TCR_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCR_PERFCOUNTER0_LOW +#define TCR_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCR_PERFCOUNTER1_LOW +#define TCR_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TP_TC_CLKGATE_CNTL +#define TP_TC_CLKGATE_CNTL__TP_BUSY_EXTEND_MASK 0x00000007L +#define TP_TC_CLKGATE_CNTL__TC_BUSY_EXTEND_MASK 0x00000038L + +// TPC_CNTL_STATUS +#define TPC_CNTL_STATUS__TPC_INPUT_BUSY_MASK 0x00000001L +#define TPC_CNTL_STATUS__TPC_INPUT_BUSY 0x00000001L +#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY_MASK 0x00000002L +#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY 0x00000002L +#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY_MASK 0x00000004L +#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY 0x00000004L +#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY_MASK 0x00000008L +#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY 0x00000008L +#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY_MASK 0x00000010L +#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY 0x00000010L +#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY_MASK 0x00000020L +#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY 0x00000020L +#define TPC_CNTL_STATUS__TPC_WALKER_BUSY_MASK 0x00000040L +#define TPC_CNTL_STATUS__TPC_WALKER_BUSY 0x00000040L +#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY_MASK 0x00000100L +#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY 0x00000100L +#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY_MASK 0x00000200L +#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY 0x00000200L +#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY_MASK 0x00000400L +#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY 0x00000400L +#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY_MASK 0x00001000L +#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY 0x00001000L +#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY_MASK 0x00002000L +#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY 0x00002000L +#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY_MASK 0x00004000L +#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY 0x00004000L +#define TPC_CNTL_STATUS__TPC_BLEND_BUSY_MASK 0x00008000L +#define TPC_CNTL_STATUS__TPC_BLEND_BUSY 0x00008000L +#define TPC_CNTL_STATUS__TF_TW_RTS_MASK 0x00010000L +#define TPC_CNTL_STATUS__TF_TW_RTS 0x00010000L +#define TPC_CNTL_STATUS__TF_TW_STATE_RTS_MASK 0x00020000L +#define TPC_CNTL_STATUS__TF_TW_STATE_RTS 0x00020000L +#define TPC_CNTL_STATUS__TF_TW_RTR_MASK 0x00080000L +#define TPC_CNTL_STATUS__TF_TW_RTR 0x00080000L +#define TPC_CNTL_STATUS__TW_TA_RTS_MASK 0x00100000L +#define TPC_CNTL_STATUS__TW_TA_RTS 0x00100000L +#define TPC_CNTL_STATUS__TW_TA_TT_RTS_MASK 0x00200000L +#define TPC_CNTL_STATUS__TW_TA_TT_RTS 0x00200000L +#define TPC_CNTL_STATUS__TW_TA_LAST_RTS_MASK 0x00400000L +#define TPC_CNTL_STATUS__TW_TA_LAST_RTS 0x00400000L +#define TPC_CNTL_STATUS__TW_TA_RTR_MASK 0x00800000L +#define TPC_CNTL_STATUS__TW_TA_RTR 0x00800000L +#define TPC_CNTL_STATUS__TA_TB_RTS_MASK 0x01000000L +#define TPC_CNTL_STATUS__TA_TB_RTS 0x01000000L +#define TPC_CNTL_STATUS__TA_TB_TT_RTS_MASK 0x02000000L +#define TPC_CNTL_STATUS__TA_TB_TT_RTS 0x02000000L +#define TPC_CNTL_STATUS__TA_TB_RTR_MASK 0x08000000L +#define TPC_CNTL_STATUS__TA_TB_RTR 0x08000000L +#define TPC_CNTL_STATUS__TA_TF_RTS_MASK 0x10000000L +#define TPC_CNTL_STATUS__TA_TF_RTS 0x10000000L +#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN_MASK 0x20000000L +#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN 0x20000000L +#define TPC_CNTL_STATUS__TP_SQ_DEC_MASK 0x40000000L +#define TPC_CNTL_STATUS__TP_SQ_DEC 0x40000000L +#define TPC_CNTL_STATUS__TPC_BUSY_MASK 0x80000000L +#define TPC_CNTL_STATUS__TPC_BUSY 0x80000000L + +// TPC_DEBUG0 +#define TPC_DEBUG0__LOD_CNTL_MASK 0x00000003L +#define TPC_DEBUG0__IC_CTR_MASK 0x0000000cL +#define TPC_DEBUG0__WALKER_CNTL_MASK 0x000000f0L +#define TPC_DEBUG0__ALIGNER_CNTL_MASK 0x00000700L +#define TPC_DEBUG0__PREV_TC_STATE_VALID_MASK 0x00001000L +#define TPC_DEBUG0__PREV_TC_STATE_VALID 0x00001000L +#define TPC_DEBUG0__WALKER_STATE_MASK 0x03ff0000L +#define TPC_DEBUG0__ALIGNER_STATE_MASK 0x0c000000L +#define TPC_DEBUG0__REG_CLK_EN_MASK 0x20000000L +#define TPC_DEBUG0__REG_CLK_EN 0x20000000L +#define TPC_DEBUG0__TPC_CLK_EN_MASK 0x40000000L +#define TPC_DEBUG0__TPC_CLK_EN 0x40000000L +#define TPC_DEBUG0__SQ_TP_WAKEUP_MASK 0x80000000L +#define TPC_DEBUG0__SQ_TP_WAKEUP 0x80000000L + +// TPC_DEBUG1 +#define TPC_DEBUG1__UNUSED_MASK 0x00000001L +#define TPC_DEBUG1__UNUSED 0x00000001L + +// TPC_CHICKEN +#define TPC_CHICKEN__BLEND_PRECISION_MASK 0x00000001L +#define TPC_CHICKEN__BLEND_PRECISION 0x00000001L +#define TPC_CHICKEN__SPARE_MASK 0xfffffffeL + +// TP0_CNTL_STATUS +#define TP0_CNTL_STATUS__TP_INPUT_BUSY_MASK 0x00000001L +#define TP0_CNTL_STATUS__TP_INPUT_BUSY 0x00000001L +#define TP0_CNTL_STATUS__TP_LOD_BUSY_MASK 0x00000002L +#define TP0_CNTL_STATUS__TP_LOD_BUSY 0x00000002L +#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY_MASK 0x00000004L +#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY 0x00000004L +#define TP0_CNTL_STATUS__TP_ADDR_BUSY_MASK 0x00000008L +#define TP0_CNTL_STATUS__TP_ADDR_BUSY 0x00000008L +#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY_MASK 0x00000010L +#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY 0x00000010L +#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY_MASK 0x00000020L +#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY 0x00000020L +#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY_MASK 0x00000040L +#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY 0x00000040L +#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY_MASK 0x00000080L +#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY 0x00000080L +#define TP0_CNTL_STATUS__TP_FETCH_BUSY_MASK 0x00000100L +#define TP0_CNTL_STATUS__TP_FETCH_BUSY 0x00000100L +#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY_MASK 0x00000200L +#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY 0x00000200L +#define TP0_CNTL_STATUS__TP_TT_BUSY_MASK 0x00000400L +#define TP0_CNTL_STATUS__TP_TT_BUSY 0x00000400L +#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY_MASK 0x00000800L +#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY 0x00000800L +#define TP0_CNTL_STATUS__TP_BLEND_BUSY_MASK 0x00001000L +#define TP0_CNTL_STATUS__TP_BLEND_BUSY 0x00001000L +#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY_MASK 0x00002000L +#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY 0x00002000L +#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY_MASK 0x00004000L +#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY 0x00004000L +#define TP0_CNTL_STATUS__IN_LC_RTS_MASK 0x00010000L +#define TP0_CNTL_STATUS__IN_LC_RTS 0x00010000L +#define TP0_CNTL_STATUS__LC_LA_RTS_MASK 0x00020000L +#define TP0_CNTL_STATUS__LC_LA_RTS 0x00020000L +#define TP0_CNTL_STATUS__LA_FL_RTS_MASK 0x00040000L +#define TP0_CNTL_STATUS__LA_FL_RTS 0x00040000L +#define TP0_CNTL_STATUS__FL_TA_RTS_MASK 0x00080000L +#define TP0_CNTL_STATUS__FL_TA_RTS 0x00080000L +#define TP0_CNTL_STATUS__TA_FA_RTS_MASK 0x00100000L +#define TP0_CNTL_STATUS__TA_FA_RTS 0x00100000L +#define TP0_CNTL_STATUS__TA_FA_TT_RTS_MASK 0x00200000L +#define TP0_CNTL_STATUS__TA_FA_TT_RTS 0x00200000L +#define TP0_CNTL_STATUS__FA_AL_RTS_MASK 0x00400000L +#define TP0_CNTL_STATUS__FA_AL_RTS 0x00400000L +#define TP0_CNTL_STATUS__FA_AL_TT_RTS_MASK 0x00800000L +#define TP0_CNTL_STATUS__FA_AL_TT_RTS 0x00800000L +#define TP0_CNTL_STATUS__AL_TF_RTS_MASK 0x01000000L +#define TP0_CNTL_STATUS__AL_TF_RTS 0x01000000L +#define TP0_CNTL_STATUS__AL_TF_TT_RTS_MASK 0x02000000L +#define TP0_CNTL_STATUS__AL_TF_TT_RTS 0x02000000L +#define TP0_CNTL_STATUS__TF_TB_RTS_MASK 0x04000000L +#define TP0_CNTL_STATUS__TF_TB_RTS 0x04000000L +#define TP0_CNTL_STATUS__TF_TB_TT_RTS_MASK 0x08000000L +#define TP0_CNTL_STATUS__TF_TB_TT_RTS 0x08000000L +#define TP0_CNTL_STATUS__TB_TT_RTS_MASK 0x10000000L +#define TP0_CNTL_STATUS__TB_TT_RTS 0x10000000L +#define TP0_CNTL_STATUS__TB_TT_TT_RESET_MASK 0x20000000L +#define TP0_CNTL_STATUS__TB_TT_TT_RESET 0x20000000L +#define TP0_CNTL_STATUS__TB_TO_RTS_MASK 0x40000000L +#define TP0_CNTL_STATUS__TB_TO_RTS 0x40000000L +#define TP0_CNTL_STATUS__TP_BUSY_MASK 0x80000000L +#define TP0_CNTL_STATUS__TP_BUSY 0x80000000L + +// TP0_DEBUG +#define TP0_DEBUG__Q_LOD_CNTL_MASK 0x00000003L +#define TP0_DEBUG__Q_SQ_TP_WAKEUP_MASK 0x00000008L +#define TP0_DEBUG__Q_SQ_TP_WAKEUP 0x00000008L +#define TP0_DEBUG__FL_TA_ADDRESSER_CNTL_MASK 0x001ffff0L +#define TP0_DEBUG__REG_CLK_EN_MASK 0x00200000L +#define TP0_DEBUG__REG_CLK_EN 0x00200000L +#define TP0_DEBUG__PERF_CLK_EN_MASK 0x00400000L +#define TP0_DEBUG__PERF_CLK_EN 0x00400000L +#define TP0_DEBUG__TP_CLK_EN_MASK 0x00800000L +#define TP0_DEBUG__TP_CLK_EN 0x00800000L +#define TP0_DEBUG__Q_WALKER_CNTL_MASK 0x0f000000L +#define TP0_DEBUG__Q_ALIGNER_CNTL_MASK 0x70000000L + +// TP0_CHICKEN +#define TP0_CHICKEN__TT_MODE_MASK 0x00000001L +#define TP0_CHICKEN__TT_MODE 0x00000001L +#define TP0_CHICKEN__VFETCH_ADDRESS_MODE_MASK 0x00000002L +#define TP0_CHICKEN__VFETCH_ADDRESS_MODE 0x00000002L +#define TP0_CHICKEN__SPARE_MASK 0xfffffffcL + +// TP0_PERFCOUNTER0_SELECT +#define TP0_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TP0_PERFCOUNTER0_HI +#define TP0_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TP0_PERFCOUNTER0_LOW +#define TP0_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TP0_PERFCOUNTER1_SELECT +#define TP0_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TP0_PERFCOUNTER1_HI +#define TP0_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TP0_PERFCOUNTER1_LOW +#define TP0_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCM_PERFCOUNTER0_SELECT +#define TCM_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCM_PERFCOUNTER1_SELECT +#define TCM_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCM_PERFCOUNTER0_HI +#define TCM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCM_PERFCOUNTER1_HI +#define TCM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCM_PERFCOUNTER0_LOW +#define TCM_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCM_PERFCOUNTER1_LOW +#define TCM_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER0_SELECT +#define TCF_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER1_SELECT +#define TCF_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER2_SELECT +#define TCF_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER3_SELECT +#define TCF_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER4_SELECT +#define TCF_PERFCOUNTER4_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER5_SELECT +#define TCF_PERFCOUNTER5_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER6_SELECT +#define TCF_PERFCOUNTER6_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER7_SELECT +#define TCF_PERFCOUNTER7_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER8_SELECT +#define TCF_PERFCOUNTER8_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER9_SELECT +#define TCF_PERFCOUNTER9_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER10_SELECT +#define TCF_PERFCOUNTER10_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER11_SELECT +#define TCF_PERFCOUNTER11_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER0_HI +#define TCF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER1_HI +#define TCF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER2_HI +#define TCF_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER3_HI +#define TCF_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER4_HI +#define TCF_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER5_HI +#define TCF_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER6_HI +#define TCF_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER7_HI +#define TCF_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER8_HI +#define TCF_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER9_HI +#define TCF_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER10_HI +#define TCF_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER11_HI +#define TCF_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER0_LOW +#define TCF_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER1_LOW +#define TCF_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER2_LOW +#define TCF_PERFCOUNTER2_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER3_LOW +#define TCF_PERFCOUNTER3_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER4_LOW +#define TCF_PERFCOUNTER4_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER5_LOW +#define TCF_PERFCOUNTER5_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER6_LOW +#define TCF_PERFCOUNTER6_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER7_LOW +#define TCF_PERFCOUNTER7_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER8_LOW +#define TCF_PERFCOUNTER8_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER9_LOW +#define TCF_PERFCOUNTER9_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER10_LOW +#define TCF_PERFCOUNTER10_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER11_LOW +#define TCF_PERFCOUNTER11_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_DEBUG +#define TCF_DEBUG__not_MH_TC_rtr_MASK 0x00000040L +#define TCF_DEBUG__not_MH_TC_rtr 0x00000040L +#define TCF_DEBUG__TC_MH_send_MASK 0x00000080L +#define TCF_DEBUG__TC_MH_send 0x00000080L +#define TCF_DEBUG__not_FG0_rtr_MASK 0x00000100L +#define TCF_DEBUG__not_FG0_rtr 0x00000100L +#define TCF_DEBUG__not_TCB_TCO_rtr_MASK 0x00001000L +#define TCF_DEBUG__not_TCB_TCO_rtr 0x00001000L +#define TCF_DEBUG__TCB_ff_stall_MASK 0x00002000L +#define TCF_DEBUG__TCB_ff_stall 0x00002000L +#define TCF_DEBUG__TCB_miss_stall_MASK 0x00004000L +#define TCF_DEBUG__TCB_miss_stall 0x00004000L +#define TCF_DEBUG__TCA_TCB_stall_MASK 0x00008000L +#define TCF_DEBUG__TCA_TCB_stall 0x00008000L +#define TCF_DEBUG__PF0_stall_MASK 0x00010000L +#define TCF_DEBUG__PF0_stall 0x00010000L +#define TCF_DEBUG__TP0_full_MASK 0x00100000L +#define TCF_DEBUG__TP0_full 0x00100000L +#define TCF_DEBUG__TPC_full_MASK 0x01000000L +#define TCF_DEBUG__TPC_full 0x01000000L +#define TCF_DEBUG__not_TPC_rtr_MASK 0x02000000L +#define TCF_DEBUG__not_TPC_rtr 0x02000000L +#define TCF_DEBUG__tca_state_rts_MASK 0x04000000L +#define TCF_DEBUG__tca_state_rts 0x04000000L +#define TCF_DEBUG__tca_rts_MASK 0x08000000L +#define TCF_DEBUG__tca_rts 0x08000000L + +// TCA_FIFO_DEBUG +#define TCA_FIFO_DEBUG__tp0_full_MASK 0x00000001L +#define TCA_FIFO_DEBUG__tp0_full 0x00000001L +#define TCA_FIFO_DEBUG__tpc_full_MASK 0x00000010L +#define TCA_FIFO_DEBUG__tpc_full 0x00000010L +#define TCA_FIFO_DEBUG__load_tpc_fifo_MASK 0x00000020L +#define TCA_FIFO_DEBUG__load_tpc_fifo 0x00000020L +#define TCA_FIFO_DEBUG__load_tp_fifos_MASK 0x00000040L +#define TCA_FIFO_DEBUG__load_tp_fifos 0x00000040L +#define TCA_FIFO_DEBUG__FW_full_MASK 0x00000080L +#define TCA_FIFO_DEBUG__FW_full 0x00000080L +#define TCA_FIFO_DEBUG__not_FW_rtr0_MASK 0x00000100L +#define TCA_FIFO_DEBUG__not_FW_rtr0 0x00000100L +#define TCA_FIFO_DEBUG__FW_rts0_MASK 0x00001000L +#define TCA_FIFO_DEBUG__FW_rts0 0x00001000L +#define TCA_FIFO_DEBUG__not_FW_tpc_rtr_MASK 0x00010000L +#define TCA_FIFO_DEBUG__not_FW_tpc_rtr 0x00010000L +#define TCA_FIFO_DEBUG__FW_tpc_rts_MASK 0x00020000L +#define TCA_FIFO_DEBUG__FW_tpc_rts 0x00020000L + +// TCA_PROBE_DEBUG +#define TCA_PROBE_DEBUG__ProbeFilter_stall_MASK 0x00000001L +#define TCA_PROBE_DEBUG__ProbeFilter_stall 0x00000001L + +// TCA_TPC_DEBUG +#define TCA_TPC_DEBUG__captue_state_rts_MASK 0x00001000L +#define TCA_TPC_DEBUG__captue_state_rts 0x00001000L +#define TCA_TPC_DEBUG__capture_tca_rts_MASK 0x00002000L +#define TCA_TPC_DEBUG__capture_tca_rts 0x00002000L + +// TCB_CORE_DEBUG +#define TCB_CORE_DEBUG__access512_MASK 0x00000001L +#define TCB_CORE_DEBUG__access512 0x00000001L +#define TCB_CORE_DEBUG__tiled_MASK 0x00000002L +#define TCB_CORE_DEBUG__tiled 0x00000002L +#define TCB_CORE_DEBUG__opcode_MASK 0x00000070L +#define TCB_CORE_DEBUG__format_MASK 0x00003f00L +#define TCB_CORE_DEBUG__sector_format_MASK 0x001f0000L +#define TCB_CORE_DEBUG__sector_format512_MASK 0x07000000L + +// TCB_TAG0_DEBUG +#define TCB_TAG0_DEBUG__mem_read_cycle_MASK 0x000003ffL +#define TCB_TAG0_DEBUG__tag_access_cycle_MASK 0x001ff000L +#define TCB_TAG0_DEBUG__miss_stall_MASK 0x00800000L +#define TCB_TAG0_DEBUG__miss_stall 0x00800000L +#define TCB_TAG0_DEBUG__num_feee_lines_MASK 0x1f000000L +#define TCB_TAG0_DEBUG__max_misses_MASK 0xe0000000L + +// TCB_TAG1_DEBUG +#define TCB_TAG1_DEBUG__mem_read_cycle_MASK 0x000003ffL +#define TCB_TAG1_DEBUG__tag_access_cycle_MASK 0x001ff000L +#define TCB_TAG1_DEBUG__miss_stall_MASK 0x00800000L +#define TCB_TAG1_DEBUG__miss_stall 0x00800000L +#define TCB_TAG1_DEBUG__num_feee_lines_MASK 0x1f000000L +#define TCB_TAG1_DEBUG__max_misses_MASK 0xe0000000L + +// TCB_TAG2_DEBUG +#define TCB_TAG2_DEBUG__mem_read_cycle_MASK 0x000003ffL +#define TCB_TAG2_DEBUG__tag_access_cycle_MASK 0x001ff000L +#define TCB_TAG2_DEBUG__miss_stall_MASK 0x00800000L +#define TCB_TAG2_DEBUG__miss_stall 0x00800000L +#define TCB_TAG2_DEBUG__num_feee_lines_MASK 0x1f000000L +#define TCB_TAG2_DEBUG__max_misses_MASK 0xe0000000L + +// TCB_TAG3_DEBUG +#define TCB_TAG3_DEBUG__mem_read_cycle_MASK 0x000003ffL +#define TCB_TAG3_DEBUG__tag_access_cycle_MASK 0x001ff000L +#define TCB_TAG3_DEBUG__miss_stall_MASK 0x00800000L +#define TCB_TAG3_DEBUG__miss_stall 0x00800000L +#define TCB_TAG3_DEBUG__num_feee_lines_MASK 0x1f000000L +#define TCB_TAG3_DEBUG__max_misses_MASK 0xe0000000L + +// TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done_MASK 0x00000001L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done 0x00000001L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left_MASK 0x00000004L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left 0x00000004L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q_MASK 0x00000010L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q 0x00000010L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go_MASK 0x00000020L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go 0x00000020L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left_MASK 0x00000040L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left 0x00000040L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_count_q_MASK 0x00000f80L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_q_MASK 0x0ffff000L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q_MASK 0x10000000L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q 0x10000000L + +// TCB_FETCH_GEN_WALKER_DEBUG +#define TCB_FETCH_GEN_WALKER_DEBUG__quad_sel_left_MASK 0x00000030L +#define TCB_FETCH_GEN_WALKER_DEBUG__set_sel_left_MASK 0x000000c0L +#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left_MASK 0x00000800L +#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left 0x00000800L +#define TCB_FETCH_GEN_WALKER_DEBUG__ff_fg_type512_MASK 0x00007000L +#define TCB_FETCH_GEN_WALKER_DEBUG__busy_MASK 0x00008000L +#define TCB_FETCH_GEN_WALKER_DEBUG__busy 0x00008000L +#define TCB_FETCH_GEN_WALKER_DEBUG__setquads_to_send_MASK 0x000f0000L + +// TCB_FETCH_GEN_PIPE0_DEBUG +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts_MASK 0x00000001L +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts 0x00000001L +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts_MASK 0x00000004L +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts 0x00000004L +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_format_MASK 0x0000fff0L +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_fmsopcode_MASK 0x001f0000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_request_type_MASK 0x00600000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__busy_MASK 0x00800000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__busy 0x00800000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy_MASK 0x01000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy 0x01000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy_MASK 0x02000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy 0x02000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__mc_sel_q_MASK 0x0c000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q_MASK 0x10000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q 0x10000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR_MASK 0x40000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR 0x40000000L + +// TCD_INPUT0_DEBUG +#define TCD_INPUT0_DEBUG__empty_MASK 0x00010000L +#define TCD_INPUT0_DEBUG__empty 0x00010000L +#define TCD_INPUT0_DEBUG__full_MASK 0x00020000L +#define TCD_INPUT0_DEBUG__full 0x00020000L +#define TCD_INPUT0_DEBUG__valid_q1_MASK 0x00100000L +#define TCD_INPUT0_DEBUG__valid_q1 0x00100000L +#define TCD_INPUT0_DEBUG__cnt_q1_MASK 0x00600000L +#define TCD_INPUT0_DEBUG__last_send_q1_MASK 0x00800000L +#define TCD_INPUT0_DEBUG__last_send_q1 0x00800000L +#define TCD_INPUT0_DEBUG__ip_send_MASK 0x01000000L +#define TCD_INPUT0_DEBUG__ip_send 0x01000000L +#define TCD_INPUT0_DEBUG__ipbuf_dxt_send_MASK 0x02000000L +#define TCD_INPUT0_DEBUG__ipbuf_dxt_send 0x02000000L +#define TCD_INPUT0_DEBUG__ipbuf_busy_MASK 0x04000000L +#define TCD_INPUT0_DEBUG__ipbuf_busy 0x04000000L + +// TCD_DEGAMMA_DEBUG +#define TCD_DEGAMMA_DEBUG__dgmm_ftfconv_dgmmen_MASK 0x00000003L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8_MASK 0x00000004L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8 0x00000004L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send_MASK 0x00000008L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send 0x00000008L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send_MASK 0x00000010L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send 0x00000010L +#define TCD_DEGAMMA_DEBUG__dgmm_stall_MASK 0x00000020L +#define TCD_DEGAMMA_DEBUG__dgmm_stall 0x00000020L +#define TCD_DEGAMMA_DEBUG__dgmm_pstate_MASK 0x00000040L +#define TCD_DEGAMMA_DEBUG__dgmm_pstate 0x00000040L + +// TCD_DXTMUX_SCTARB_DEBUG +#define TCD_DXTMUX_SCTARB_DEBUG__pstate_MASK 0x00000200L +#define TCD_DXTMUX_SCTARB_DEBUG__pstate 0x00000200L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr_MASK 0x00000400L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr 0x00000400L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr_MASK 0x00000800L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr 0x00000800L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send_MASK 0x00008000L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send 0x00008000L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts_MASK 0x00010000L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts 0x00010000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send_MASK 0x00100000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send 0x00100000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send_MASK 0x08000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send 0x08000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send_MASK 0x10000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send 0x10000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send_MASK 0x20000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send 0x20000000L + +// TCD_DXTC_ARB_DEBUG +#define TCD_DXTC_ARB_DEBUG__n0_stall_MASK 0x00000010L +#define TCD_DXTC_ARB_DEBUG__n0_stall 0x00000010L +#define TCD_DXTC_ARB_DEBUG__pstate_MASK 0x00000020L +#define TCD_DXTC_ARB_DEBUG__pstate 0x00000020L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send_MASK 0x00000040L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send 0x00000040L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cnt_MASK 0x00000180L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_sector_MASK 0x00000e00L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cacheline_MASK 0x0003f000L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_format_MASK 0x3ffc0000L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send_MASK 0x40000000L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send 0x40000000L +#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types_MASK 0x80000000L +#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types 0x80000000L + +// TCD_STALLS_DEBUG +#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr_MASK 0x00000400L +#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr 0x00000400L +#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr_MASK 0x00000800L +#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr 0x00000800L +#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr_MASK 0x00020000L +#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr 0x00020000L +#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr_MASK 0x00040000L +#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr 0x00040000L +#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr_MASK 0x00080000L +#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr 0x00080000L +#define TCD_STALLS_DEBUG__not_incoming_rtr_MASK 0x80000000L +#define TCD_STALLS_DEBUG__not_incoming_rtr 0x80000000L + +// TCO_STALLS_DEBUG +#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR_MASK 0x00000020L +#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR 0x00000020L +#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR_MASK 0x00000040L +#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR 0x00000040L +#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d_MASK 0x00000080L +#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d 0x00000080L + +// TCO_QUAD0_DEBUG0 +#define TCO_QUAD0_DEBUG0__rl_sg_sector_format_MASK 0x000000ffL +#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample_MASK 0x00000100L +#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample 0x00000100L +#define TCO_QUAD0_DEBUG0__rl_sg_rtr_MASK 0x00000200L +#define TCO_QUAD0_DEBUG0__rl_sg_rtr 0x00000200L +#define TCO_QUAD0_DEBUG0__rl_sg_rts_MASK 0x00000400L +#define TCO_QUAD0_DEBUG0__rl_sg_rts 0x00000400L +#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample_MASK 0x00000800L +#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample 0x00000800L +#define TCO_QUAD0_DEBUG0__sg_crd_rtr_MASK 0x00001000L +#define TCO_QUAD0_DEBUG0__sg_crd_rtr 0x00001000L +#define TCO_QUAD0_DEBUG0__sg_crd_rts_MASK 0x00002000L +#define TCO_QUAD0_DEBUG0__sg_crd_rts 0x00002000L +#define TCO_QUAD0_DEBUG0__stageN1_valid_q_MASK 0x00010000L +#define TCO_QUAD0_DEBUG0__stageN1_valid_q 0x00010000L +#define TCO_QUAD0_DEBUG0__read_cache_q_MASK 0x01000000L +#define TCO_QUAD0_DEBUG0__read_cache_q 0x01000000L +#define TCO_QUAD0_DEBUG0__cache_read_RTR_MASK 0x02000000L +#define TCO_QUAD0_DEBUG0__cache_read_RTR 0x02000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set3_MASK 0x04000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set3 0x04000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set2_MASK 0x08000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set2 0x08000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set1_MASK 0x10000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set1 0x10000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set0_MASK 0x20000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set0 0x20000000L +#define TCO_QUAD0_DEBUG0__busy_MASK 0x40000000L +#define TCO_QUAD0_DEBUG0__busy 0x40000000L + +// TCO_QUAD0_DEBUG1 +#define TCO_QUAD0_DEBUG1__fifo_busy_MASK 0x00000001L +#define TCO_QUAD0_DEBUG1__fifo_busy 0x00000001L +#define TCO_QUAD0_DEBUG1__empty_MASK 0x00000002L +#define TCO_QUAD0_DEBUG1__empty 0x00000002L +#define TCO_QUAD0_DEBUG1__full_MASK 0x00000004L +#define TCO_QUAD0_DEBUG1__full 0x00000004L +#define TCO_QUAD0_DEBUG1__write_enable_MASK 0x00000008L +#define TCO_QUAD0_DEBUG1__write_enable 0x00000008L +#define TCO_QUAD0_DEBUG1__fifo_write_ptr_MASK 0x000007f0L +#define TCO_QUAD0_DEBUG1__fifo_read_ptr_MASK 0x0003f800L +#define TCO_QUAD0_DEBUG1__cache_read_busy_MASK 0x00100000L +#define TCO_QUAD0_DEBUG1__cache_read_busy 0x00100000L +#define TCO_QUAD0_DEBUG1__latency_fifo_busy_MASK 0x00200000L +#define TCO_QUAD0_DEBUG1__latency_fifo_busy 0x00200000L +#define TCO_QUAD0_DEBUG1__input_quad_busy_MASK 0x00400000L +#define TCO_QUAD0_DEBUG1__input_quad_busy 0x00400000L +#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy_MASK 0x00800000L +#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy 0x00800000L +#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d_MASK 0x01000000L +#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d 0x01000000L +#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q_MASK 0x02000000L +#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q 0x02000000L +#define TCO_QUAD0_DEBUG1__rl_sg_rtr_MASK 0x04000000L +#define TCO_QUAD0_DEBUG1__rl_sg_rtr 0x04000000L +#define TCO_QUAD0_DEBUG1__rl_sg_rts_MASK 0x08000000L +#define TCO_QUAD0_DEBUG1__rl_sg_rts 0x08000000L +#define TCO_QUAD0_DEBUG1__sg_crd_rtr_MASK 0x10000000L +#define TCO_QUAD0_DEBUG1__sg_crd_rtr 0x10000000L +#define TCO_QUAD0_DEBUG1__sg_crd_rts_MASK 0x20000000L +#define TCO_QUAD0_DEBUG1__sg_crd_rts 0x20000000L +#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc_MASK 0x40000000L +#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc 0x40000000L + +// SQ_GPR_MANAGEMENT +#define SQ_GPR_MANAGEMENT__REG_DYNAMIC_MASK 0x00000001L +#define SQ_GPR_MANAGEMENT__REG_DYNAMIC 0x00000001L +#define SQ_GPR_MANAGEMENT__REG_SIZE_PIX_MASK 0x000007f0L +#define SQ_GPR_MANAGEMENT__REG_SIZE_VTX_MASK 0x0007f000L + +// SQ_FLOW_CONTROL +#define SQ_FLOW_CONTROL__INPUT_ARBITRATION_POLICY_MASK 0x00000003L +#define SQ_FLOW_CONTROL__ONE_THREAD_MASK 0x00000010L +#define SQ_FLOW_CONTROL__ONE_THREAD 0x00000010L +#define SQ_FLOW_CONTROL__ONE_ALU_MASK 0x00000100L +#define SQ_FLOW_CONTROL__ONE_ALU 0x00000100L +#define SQ_FLOW_CONTROL__CF_WR_BASE_MASK 0x0000f000L +#define SQ_FLOW_CONTROL__NO_PV_PS_MASK 0x00010000L +#define SQ_FLOW_CONTROL__NO_PV_PS 0x00010000L +#define SQ_FLOW_CONTROL__NO_LOOP_EXIT_MASK 0x00020000L +#define SQ_FLOW_CONTROL__NO_LOOP_EXIT 0x00020000L +#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE_MASK 0x00040000L +#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE 0x00040000L +#define SQ_FLOW_CONTROL__TEXTURE_ARBITRATION_POLICY_MASK 0x00180000L +#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY_MASK 0x00200000L +#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY 0x00200000L +#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY_MASK 0x00400000L +#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY 0x00400000L +#define SQ_FLOW_CONTROL__NO_ARB_EJECT_MASK 0x00800000L +#define SQ_FLOW_CONTROL__NO_ARB_EJECT 0x00800000L +#define SQ_FLOW_CONTROL__NO_CFS_EJECT_MASK 0x01000000L +#define SQ_FLOW_CONTROL__NO_CFS_EJECT 0x01000000L +#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY_MASK 0x02000000L +#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY 0x02000000L +#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION_MASK 0x04000000L +#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION 0x04000000L +#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC_MASK 0x08000000L +#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC 0x08000000L + +// SQ_INST_STORE_MANAGMENT +#define SQ_INST_STORE_MANAGMENT__INST_BASE_PIX_MASK 0x00000fffL +#define SQ_INST_STORE_MANAGMENT__INST_BASE_VTX_MASK 0x0fff0000L + +// SQ_RESOURCE_MANAGMENT +#define SQ_RESOURCE_MANAGMENT__VTX_THREAD_BUF_ENTRIES_MASK 0x000000ffL +#define SQ_RESOURCE_MANAGMENT__PIX_THREAD_BUF_ENTRIES_MASK 0x0000ff00L +#define SQ_RESOURCE_MANAGMENT__EXPORT_BUF_ENTRIES_MASK 0x01ff0000L + +// SQ_EO_RT +#define SQ_EO_RT__EO_CONSTANTS_RT_MASK 0x000000ffL +#define SQ_EO_RT__EO_TSTATE_RT_MASK 0x00ff0000L + +// SQ_DEBUG_MISC +#define SQ_DEBUG_MISC__DB_ALUCST_SIZE_MASK 0x000007ffL +#define SQ_DEBUG_MISC__DB_TSTATE_SIZE_MASK 0x000ff000L +#define SQ_DEBUG_MISC__DB_READ_CTX_MASK 0x00100000L +#define SQ_DEBUG_MISC__DB_READ_CTX 0x00100000L +#define SQ_DEBUG_MISC__RESERVED_MASK 0x00600000L +#define SQ_DEBUG_MISC__DB_READ_MEMORY_MASK 0x01800000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0_MASK 0x02000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0 0x02000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1_MASK 0x04000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1 0x04000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2_MASK 0x08000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2 0x08000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3_MASK 0x10000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3 0x10000000L + +// SQ_ACTIVITY_METER_CNTL +#define SQ_ACTIVITY_METER_CNTL__TIMEBASE_MASK 0x000000ffL +#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_LOW_MASK 0x0000ff00L +#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_HIGH_MASK 0x00ff0000L +#define SQ_ACTIVITY_METER_CNTL__SPARE_MASK 0xff000000L + +// SQ_ACTIVITY_METER_STATUS +#define SQ_ACTIVITY_METER_STATUS__PERCENT_BUSY_MASK 0x000000ffL + +// SQ_INPUT_ARB_PRIORITY +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_WEIGHT_MASK 0x00000007L +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN_MASK 0x00000008L +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN 0x00000008L +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_WEIGHT_MASK 0x00000070L +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN_MASK 0x00000080L +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN 0x00000080L +#define SQ_INPUT_ARB_PRIORITY__THRESHOLD_MASK 0x0003ff00L + +// SQ_THREAD_ARB_PRIORITY +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_WEIGHT_MASK 0x00000007L +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN_MASK 0x00000008L +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN 0x00000008L +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_WEIGHT_MASK 0x00000070L +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN_MASK 0x00000080L +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN 0x00000080L +#define SQ_THREAD_ARB_PRIORITY__THRESHOLD_MASK 0x0003ff00L +#define SQ_THREAD_ARB_PRIORITY__RESERVED_MASK 0x000c0000L +#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL_MASK 0x00100000L +#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL 0x00100000L +#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL_MASK 0x00200000L +#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL 0x00200000L +#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD_MASK 0x00400000L +#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD 0x00400000L + +// SQ_VS_WATCHDOG_TIMER +#define SQ_VS_WATCHDOG_TIMER__ENABLE_MASK 0x00000001L +#define SQ_VS_WATCHDOG_TIMER__ENABLE 0x00000001L +#define SQ_VS_WATCHDOG_TIMER__TIMEOUT_COUNT_MASK 0xfffffffeL + +// SQ_PS_WATCHDOG_TIMER +#define SQ_PS_WATCHDOG_TIMER__ENABLE_MASK 0x00000001L +#define SQ_PS_WATCHDOG_TIMER__ENABLE 0x00000001L +#define SQ_PS_WATCHDOG_TIMER__TIMEOUT_COUNT_MASK 0xfffffffeL + +// SQ_INT_CNTL +#define SQ_INT_CNTL__PS_WATCHDOG_MASK_MASK 0x00000001L +#define SQ_INT_CNTL__PS_WATCHDOG_MASK 0x00000001L +#define SQ_INT_CNTL__VS_WATCHDOG_MASK_MASK 0x00000002L +#define SQ_INT_CNTL__VS_WATCHDOG_MASK 0x00000002L + +// SQ_INT_STATUS +#define SQ_INT_STATUS__PS_WATCHDOG_TIMEOUT_MASK 0x00000001L +#define SQ_INT_STATUS__PS_WATCHDOG_TIMEOUT 0x00000001L +#define SQ_INT_STATUS__VS_WATCHDOG_TIMEOUT_MASK 0x00000002L +#define SQ_INT_STATUS__VS_WATCHDOG_TIMEOUT 0x00000002L + +// SQ_INT_ACK +#define SQ_INT_ACK__PS_WATCHDOG_ACK_MASK 0x00000001L +#define SQ_INT_ACK__PS_WATCHDOG_ACK 0x00000001L +#define SQ_INT_ACK__VS_WATCHDOG_ACK_MASK 0x00000002L +#define SQ_INT_ACK__VS_WATCHDOG_ACK 0x00000002L + +// SQ_DEBUG_INPUT_FSM +#define SQ_DEBUG_INPUT_FSM__VC_VSR_LD_MASK 0x00000007L +#define SQ_DEBUG_INPUT_FSM__RESERVED_MASK 0x00000008L +#define SQ_DEBUG_INPUT_FSM__RESERVED 0x00000008L +#define SQ_DEBUG_INPUT_FSM__VC_GPR_LD_MASK 0x000000f0L +#define SQ_DEBUG_INPUT_FSM__PC_PISM_MASK 0x00000700L +#define SQ_DEBUG_INPUT_FSM__RESERVED1_MASK 0x00000800L +#define SQ_DEBUG_INPUT_FSM__RESERVED1 0x00000800L +#define SQ_DEBUG_INPUT_FSM__PC_AS_MASK 0x00007000L +#define SQ_DEBUG_INPUT_FSM__PC_INTERP_CNT_MASK 0x000f8000L +#define SQ_DEBUG_INPUT_FSM__PC_GPR_SIZE_MASK 0x0ff00000L + +// SQ_DEBUG_CONST_MGR_FSM +#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_EVENT_STATE_MASK 0x0000001fL +#define SQ_DEBUG_CONST_MGR_FSM__RESERVED1_MASK 0x000000e0L +#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_EVENT_STATE_MASK 0x00001f00L +#define SQ_DEBUG_CONST_MGR_FSM__RESERVED2_MASK 0x0000e000L +#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_CNTX_VALID_MASK 0x00030000L +#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_CNTX_VALID_MASK 0x000c0000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE_MASK 0x00100000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE 0x00100000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE_MASK 0x00200000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE 0x00200000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE_MASK 0x00400000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE 0x00400000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE_MASK 0x00800000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE 0x00800000L + +// SQ_DEBUG_TP_FSM +#define SQ_DEBUG_TP_FSM__EX_TP_MASK 0x00000007L +#define SQ_DEBUG_TP_FSM__RESERVED0_MASK 0x00000008L +#define SQ_DEBUG_TP_FSM__RESERVED0 0x00000008L +#define SQ_DEBUG_TP_FSM__CF_TP_MASK 0x000000f0L +#define SQ_DEBUG_TP_FSM__IF_TP_MASK 0x00000700L +#define SQ_DEBUG_TP_FSM__RESERVED1_MASK 0x00000800L +#define SQ_DEBUG_TP_FSM__RESERVED1 0x00000800L +#define SQ_DEBUG_TP_FSM__TIS_TP_MASK 0x00003000L +#define SQ_DEBUG_TP_FSM__RESERVED2_MASK 0x0000c000L +#define SQ_DEBUG_TP_FSM__GS_TP_MASK 0x00030000L +#define SQ_DEBUG_TP_FSM__RESERVED3_MASK 0x000c0000L +#define SQ_DEBUG_TP_FSM__FCR_TP_MASK 0x00300000L +#define SQ_DEBUG_TP_FSM__RESERVED4_MASK 0x00c00000L +#define SQ_DEBUG_TP_FSM__FCS_TP_MASK 0x03000000L +#define SQ_DEBUG_TP_FSM__RESERVED5_MASK 0x0c000000L +#define SQ_DEBUG_TP_FSM__ARB_TR_TP_MASK 0x70000000L + +// SQ_DEBUG_FSM_ALU_0 +#define SQ_DEBUG_FSM_ALU_0__EX_ALU_0_MASK 0x00000007L +#define SQ_DEBUG_FSM_ALU_0__RESERVED0_MASK 0x00000008L +#define SQ_DEBUG_FSM_ALU_0__RESERVED0 0x00000008L +#define SQ_DEBUG_FSM_ALU_0__CF_ALU_0_MASK 0x000000f0L +#define SQ_DEBUG_FSM_ALU_0__IF_ALU_0_MASK 0x00000700L +#define SQ_DEBUG_FSM_ALU_0__RESERVED1_MASK 0x00000800L +#define SQ_DEBUG_FSM_ALU_0__RESERVED1 0x00000800L +#define SQ_DEBUG_FSM_ALU_0__DU1_ALU_0_MASK 0x00007000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED2_MASK 0x00008000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED2 0x00008000L +#define SQ_DEBUG_FSM_ALU_0__DU0_ALU_0_MASK 0x00070000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED3_MASK 0x00080000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED3 0x00080000L +#define SQ_DEBUG_FSM_ALU_0__AIS_ALU_0_MASK 0x00700000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED4_MASK 0x00800000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED4 0x00800000L +#define SQ_DEBUG_FSM_ALU_0__ACS_ALU_0_MASK 0x07000000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED5_MASK 0x08000000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED5 0x08000000L +#define SQ_DEBUG_FSM_ALU_0__ARB_TR_ALU_MASK 0x70000000L + +// SQ_DEBUG_FSM_ALU_1 +#define SQ_DEBUG_FSM_ALU_1__EX_ALU_0_MASK 0x00000007L +#define SQ_DEBUG_FSM_ALU_1__RESERVED0_MASK 0x00000008L +#define SQ_DEBUG_FSM_ALU_1__RESERVED0 0x00000008L +#define SQ_DEBUG_FSM_ALU_1__CF_ALU_0_MASK 0x000000f0L +#define SQ_DEBUG_FSM_ALU_1__IF_ALU_0_MASK 0x00000700L +#define SQ_DEBUG_FSM_ALU_1__RESERVED1_MASK 0x00000800L +#define SQ_DEBUG_FSM_ALU_1__RESERVED1 0x00000800L +#define SQ_DEBUG_FSM_ALU_1__DU1_ALU_0_MASK 0x00007000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED2_MASK 0x00008000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED2 0x00008000L +#define SQ_DEBUG_FSM_ALU_1__DU0_ALU_0_MASK 0x00070000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED3_MASK 0x00080000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED3 0x00080000L +#define SQ_DEBUG_FSM_ALU_1__AIS_ALU_0_MASK 0x00700000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED4_MASK 0x00800000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED4 0x00800000L +#define SQ_DEBUG_FSM_ALU_1__ACS_ALU_0_MASK 0x07000000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED5_MASK 0x08000000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED5 0x08000000L +#define SQ_DEBUG_FSM_ALU_1__ARB_TR_ALU_MASK 0x70000000L + +// SQ_DEBUG_EXP_ALLOC +#define SQ_DEBUG_EXP_ALLOC__POS_BUF_AVAIL_MASK 0x0000000fL +#define SQ_DEBUG_EXP_ALLOC__COLOR_BUF_AVAIL_MASK 0x00000ff0L +#define SQ_DEBUG_EXP_ALLOC__EA_BUF_AVAIL_MASK 0x00007000L +#define SQ_DEBUG_EXP_ALLOC__RESERVED_MASK 0x00008000L +#define SQ_DEBUG_EXP_ALLOC__RESERVED 0x00008000L +#define SQ_DEBUG_EXP_ALLOC__ALLOC_TBL_BUF_AVAIL_MASK 0x003f0000L + +// SQ_DEBUG_PTR_BUFF +#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER_MASK 0x00000001L +#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER 0x00000001L +#define SQ_DEBUG_PTR_BUFF__DEALLOC_CNT_MASK 0x0000001eL +#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR_MASK 0x00000020L +#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR 0x00000020L +#define SQ_DEBUG_PTR_BUFF__EVENT_CONTEXT_ID_MASK 0x000001c0L +#define SQ_DEBUG_PTR_BUFF__SC_EVENT_ID_MASK 0x00003e00L +#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT_MASK 0x00004000L +#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT 0x00004000L +#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON_MASK 0x00008000L +#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON 0x00008000L +#define SQ_DEBUG_PTR_BUFF__EF_EMPTY_MASK 0x00010000L +#define SQ_DEBUG_PTR_BUFF__EF_EMPTY 0x00010000L +#define SQ_DEBUG_PTR_BUFF__VTX_SYNC_CNT_MASK 0x0ffe0000L + +// SQ_DEBUG_GPR_VTX +#define SQ_DEBUG_GPR_VTX__VTX_TAIL_PTR_MASK 0x0000007fL +#define SQ_DEBUG_GPR_VTX__RESERVED_MASK 0x00000080L +#define SQ_DEBUG_GPR_VTX__RESERVED 0x00000080L +#define SQ_DEBUG_GPR_VTX__VTX_HEAD_PTR_MASK 0x00007f00L +#define SQ_DEBUG_GPR_VTX__RESERVED1_MASK 0x00008000L +#define SQ_DEBUG_GPR_VTX__RESERVED1 0x00008000L +#define SQ_DEBUG_GPR_VTX__VTX_MAX_MASK 0x007f0000L +#define SQ_DEBUG_GPR_VTX__RESERVED2_MASK 0x00800000L +#define SQ_DEBUG_GPR_VTX__RESERVED2 0x00800000L +#define SQ_DEBUG_GPR_VTX__VTX_FREE_MASK 0x7f000000L + +// SQ_DEBUG_GPR_PIX +#define SQ_DEBUG_GPR_PIX__PIX_TAIL_PTR_MASK 0x0000007fL +#define SQ_DEBUG_GPR_PIX__RESERVED_MASK 0x00000080L +#define SQ_DEBUG_GPR_PIX__RESERVED 0x00000080L +#define SQ_DEBUG_GPR_PIX__PIX_HEAD_PTR_MASK 0x00007f00L +#define SQ_DEBUG_GPR_PIX__RESERVED1_MASK 0x00008000L +#define SQ_DEBUG_GPR_PIX__RESERVED1 0x00008000L +#define SQ_DEBUG_GPR_PIX__PIX_MAX_MASK 0x007f0000L +#define SQ_DEBUG_GPR_PIX__RESERVED2_MASK 0x00800000L +#define SQ_DEBUG_GPR_PIX__RESERVED2 0x00800000L +#define SQ_DEBUG_GPR_PIX__PIX_FREE_MASK 0x7f000000L + +// SQ_DEBUG_TB_STATUS_SEL +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATUS_REG_SEL_MASK 0x0000000fL +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_DW_SEL_MASK 0x00000070L +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_ADDR_MASK 0x00000780L +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN_MASK 0x00000800L +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN 0x00000800L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN_MASK 0x00001000L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN 0x00001000L +#define SQ_DEBUG_TB_STATUS_SEL__DEBUG_BUS_TRIGGER_SEL_MASK 0x0000c000L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATUS_REG_SEL_MASK 0x000f0000L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_DW_SEL_MASK 0x00700000L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_ADDR_MASK 0x1f800000L +#define SQ_DEBUG_TB_STATUS_SEL__VC_THREAD_BUF_DLY_MASK 0x60000000L +#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC_MASK 0x80000000L +#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC 0x80000000L + +// SQ_DEBUG_VTX_TB_0 +#define SQ_DEBUG_VTX_TB_0__VTX_HEAD_PTR_Q_MASK 0x0000000fL +#define SQ_DEBUG_VTX_TB_0__TAIL_PTR_Q_MASK 0x000000f0L +#define SQ_DEBUG_VTX_TB_0__FULL_CNT_Q_MASK 0x00000f00L +#define SQ_DEBUG_VTX_TB_0__NXT_POS_ALLOC_CNT_MASK 0x0000f000L +#define SQ_DEBUG_VTX_TB_0__NXT_PC_ALLOC_CNT_MASK 0x000f0000L +#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL_MASK 0x00100000L +#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL 0x00100000L +#define SQ_DEBUG_VTX_TB_0__BUSY_Q_MASK 0x00200000L +#define SQ_DEBUG_VTX_TB_0__BUSY_Q 0x00200000L + +// SQ_DEBUG_VTX_TB_1 +#define SQ_DEBUG_VTX_TB_1__VS_DONE_PTR_MASK 0x0000ffffL + +// SQ_DEBUG_VTX_TB_STATUS_REG +#define SQ_DEBUG_VTX_TB_STATUS_REG__VS_STATUS_REG_MASK 0xffffffffL + +// SQ_DEBUG_VTX_TB_STATE_MEM +#define SQ_DEBUG_VTX_TB_STATE_MEM__VS_STATE_MEM_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_0 +#define SQ_DEBUG_PIX_TB_0__PIX_HEAD_PTR_MASK 0x0000003fL +#define SQ_DEBUG_PIX_TB_0__TAIL_PTR_MASK 0x00000fc0L +#define SQ_DEBUG_PIX_TB_0__FULL_CNT_MASK 0x0007f000L +#define SQ_DEBUG_PIX_TB_0__NXT_PIX_ALLOC_CNT_MASK 0x01f80000L +#define SQ_DEBUG_PIX_TB_0__NXT_PIX_EXP_CNT_MASK 0x7e000000L +#define SQ_DEBUG_PIX_TB_0__BUSY_MASK 0x80000000L +#define SQ_DEBUG_PIX_TB_0__BUSY 0x80000000L + +// SQ_DEBUG_PIX_TB_STATUS_REG_0 +#define SQ_DEBUG_PIX_TB_STATUS_REG_0__PIX_TB_STATUS_REG_0_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_STATUS_REG_1 +#define SQ_DEBUG_PIX_TB_STATUS_REG_1__PIX_TB_STATUS_REG_1_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_STATUS_REG_2 +#define SQ_DEBUG_PIX_TB_STATUS_REG_2__PIX_TB_STATUS_REG_2_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_STATUS_REG_3 +#define SQ_DEBUG_PIX_TB_STATUS_REG_3__PIX_TB_STATUS_REG_3_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_STATE_MEM +#define SQ_DEBUG_PIX_TB_STATE_MEM__PIX_TB_STATE_MEM_MASK 0xffffffffL + +// SQ_PERFCOUNTER0_SELECT +#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// SQ_PERFCOUNTER1_SELECT +#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL + +// SQ_PERFCOUNTER2_SELECT +#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL + +// SQ_PERFCOUNTER3_SELECT +#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL + +// SQ_PERFCOUNTER0_LOW +#define SQ_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// SQ_PERFCOUNTER0_HI +#define SQ_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// SQ_PERFCOUNTER1_LOW +#define SQ_PERFCOUNTER1_LOW__PERF_COUNT_MASK 0xffffffffL + +// SQ_PERFCOUNTER1_HI +#define SQ_PERFCOUNTER1_HI__PERF_COUNT_MASK 0x0000ffffL + +// SQ_PERFCOUNTER2_LOW +#define SQ_PERFCOUNTER2_LOW__PERF_COUNT_MASK 0xffffffffL + +// SQ_PERFCOUNTER2_HI +#define SQ_PERFCOUNTER2_HI__PERF_COUNT_MASK 0x0000ffffL + +// SQ_PERFCOUNTER3_LOW +#define SQ_PERFCOUNTER3_LOW__PERF_COUNT_MASK 0xffffffffL + +// SQ_PERFCOUNTER3_HI +#define SQ_PERFCOUNTER3_HI__PERF_COUNT_MASK 0x0000ffffL + +// SX_PERFCOUNTER0_SELECT +#define SX_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// SX_PERFCOUNTER0_LOW +#define SX_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// SX_PERFCOUNTER0_HI +#define SX_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// SQ_INSTRUCTION_ALU_0 +#define SQ_INSTRUCTION_ALU_0__VECTOR_RESULT_MASK 0x0000003fL +#define SQ_INSTRUCTION_ALU_0__VECTOR_DST_REL_MASK 0x00000040L +#define SQ_INSTRUCTION_ALU_0__VECTOR_DST_REL 0x00000040L +#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP_MASK 0x00000080L +#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP 0x00000080L +#define SQ_INSTRUCTION_ALU_0__SCALAR_RESULT_MASK 0x00003f00L +#define SQ_INSTRUCTION_ALU_0__SCALAR_DST_REL_MASK 0x00004000L +#define SQ_INSTRUCTION_ALU_0__SCALAR_DST_REL 0x00004000L +#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA_MASK 0x00008000L +#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA 0x00008000L +#define SQ_INSTRUCTION_ALU_0__VECTOR_WRT_MSK_MASK 0x000f0000L +#define SQ_INSTRUCTION_ALU_0__SCALAR_WRT_MSK_MASK 0x00f00000L +#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP_MASK 0x01000000L +#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP 0x01000000L +#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP_MASK 0x02000000L +#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP 0x02000000L +#define SQ_INSTRUCTION_ALU_0__SCALAR_OPCODE_MASK 0xfc000000L + +// SQ_INSTRUCTION_ALU_1 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_R_MASK 0x00000003L +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_G_MASK 0x0000000cL +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_B_MASK 0x00000030L +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_A_MASK 0x000000c0L +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_R_MASK 0x00000300L +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_G_MASK 0x00000c00L +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_B_MASK 0x00003000L +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_A_MASK 0x0000c000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_R_MASK 0x00030000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_G_MASK 0x000c0000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_B_MASK 0x00300000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_A_MASK 0x00c00000L +#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD_MASK 0x01000000L +#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD 0x01000000L +#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD_MASK 0x02000000L +#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD 0x02000000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD_MASK 0x04000000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD 0x04000000L +#define SQ_INSTRUCTION_ALU_1__PRED_SELECT_MASK 0x18000000L +#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR_MASK 0x20000000L +#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR 0x20000000L +#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS_MASK 0x40000000L +#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS 0x40000000L +#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS_MASK 0x80000000L +#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS 0x80000000L + +// SQ_INSTRUCTION_ALU_2 +#define SQ_INSTRUCTION_ALU_2__SRC_C_REG_PTR_MASK 0x0000003fL +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C_MASK 0x00000040L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C 0x00000040L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C_MASK 0x00000080L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C 0x00000080L +#define SQ_INSTRUCTION_ALU_2__SRC_B_REG_PTR_MASK 0x00003f00L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B_MASK 0x00004000L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B 0x00004000L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B_MASK 0x00008000L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B 0x00008000L +#define SQ_INSTRUCTION_ALU_2__SRC_A_REG_PTR_MASK 0x003f0000L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A_MASK 0x00400000L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A 0x00400000L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A_MASK 0x00800000L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A 0x00800000L +#define SQ_INSTRUCTION_ALU_2__VECTOR_OPCODE_MASK 0x1f000000L +#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL_MASK 0x20000000L +#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL 0x20000000L +#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL_MASK 0x40000000L +#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL 0x40000000L +#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL_MASK 0x80000000L +#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL 0x80000000L + +// SQ_INSTRUCTION_CF_EXEC_0 +#define SQ_INSTRUCTION_CF_EXEC_0__ADDRESS_MASK 0x000001ffL +#define SQ_INSTRUCTION_CF_EXEC_0__RESERVED_MASK 0x00000e00L +#define SQ_INSTRUCTION_CF_EXEC_0__COUNT_MASK 0x00007000L +#define SQ_INSTRUCTION_CF_EXEC_0__YIELD_MASK 0x00008000L +#define SQ_INSTRUCTION_CF_EXEC_0__YIELD 0x00008000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0_MASK 0x00010000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0 0x00010000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0_MASK 0x00020000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0 0x00020000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1_MASK 0x00040000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1 0x00040000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1_MASK 0x00080000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1 0x00080000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2_MASK 0x00100000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2 0x00100000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2_MASK 0x00200000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2 0x00200000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3_MASK 0x00400000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3 0x00400000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3_MASK 0x00800000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3 0x00800000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4_MASK 0x01000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4 0x01000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4_MASK 0x02000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4 0x02000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5_MASK 0x04000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5 0x04000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5 0x08000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0_MASK 0x10000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0 0x10000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1_MASK 0x20000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1 0x20000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2_MASK 0x40000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2 0x40000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3_MASK 0x80000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3 0x80000000L + +// SQ_INSTRUCTION_CF_EXEC_1 +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4_MASK 0x00000001L +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4 0x00000001L +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5_MASK 0x00000002L +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5 0x00000002L +#define SQ_INSTRUCTION_CF_EXEC_1__BOOL_ADDR_MASK 0x000003fcL +#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION_MASK 0x00000400L +#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION 0x00000400L +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE 0x00000800L +#define SQ_INSTRUCTION_CF_EXEC_1__OPCODE_MASK 0x0000f000L +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MASK 0x01ff0000L +#define SQ_INSTRUCTION_CF_EXEC_1__RESERVED_MASK 0x0e000000L +#define SQ_INSTRUCTION_CF_EXEC_1__COUNT_MASK 0x70000000L +#define SQ_INSTRUCTION_CF_EXEC_1__YIELD_MASK 0x80000000L +#define SQ_INSTRUCTION_CF_EXEC_1__YIELD 0x80000000L + +// SQ_INSTRUCTION_CF_EXEC_2 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0_MASK 0x00000001L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0 0x00000001L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0_MASK 0x00000002L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0 0x00000002L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1_MASK 0x00000004L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1 0x00000004L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1_MASK 0x00000008L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1 0x00000008L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2_MASK 0x00000010L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2 0x00000010L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2_MASK 0x00000020L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2 0x00000020L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3_MASK 0x00000040L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3 0x00000040L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3_MASK 0x00000080L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3 0x00000080L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4_MASK 0x00000100L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4 0x00000100L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4_MASK 0x00000200L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4 0x00000200L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5_MASK 0x00000400L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5 0x00000400L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5 0x00000800L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0_MASK 0x00001000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0 0x00001000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1_MASK 0x00002000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1 0x00002000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2_MASK 0x00004000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2 0x00004000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3_MASK 0x00008000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3 0x00008000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4_MASK 0x00010000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4 0x00010000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5_MASK 0x00020000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5 0x00020000L +#define SQ_INSTRUCTION_CF_EXEC_2__BOOL_ADDR_MASK 0x03fc0000L +#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION_MASK 0x04000000L +#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION 0x04000000L +#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE 0x08000000L +#define SQ_INSTRUCTION_CF_EXEC_2__OPCODE_MASK 0xf0000000L + +// SQ_INSTRUCTION_CF_LOOP_0 +#define SQ_INSTRUCTION_CF_LOOP_0__ADDRESS_MASK 0x000003ffL +#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_0_MASK 0x0000fc00L +#define SQ_INSTRUCTION_CF_LOOP_0__LOOP_ID_MASK 0x001f0000L +#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_1_MASK 0xffe00000L + +// SQ_INSTRUCTION_CF_LOOP_1 +#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_0_MASK 0x000007ffL +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE 0x00000800L +#define SQ_INSTRUCTION_CF_LOOP_1__OPCODE_MASK 0x0000f000L +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MASK 0x03ff0000L +#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_1_MASK 0xfc000000L + +// SQ_INSTRUCTION_CF_LOOP_2 +#define SQ_INSTRUCTION_CF_LOOP_2__LOOP_ID_MASK 0x0000001fL +#define SQ_INSTRUCTION_CF_LOOP_2__RESERVED_MASK 0x07ffffe0L +#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE 0x08000000L +#define SQ_INSTRUCTION_CF_LOOP_2__OPCODE_MASK 0xf0000000L + +// SQ_INSTRUCTION_CF_JMP_CALL_0 +#define SQ_INSTRUCTION_CF_JMP_CALL_0__ADDRESS_MASK 0x000003ffL +#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_0_MASK 0x00001c00L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL_MASK 0x00002000L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL 0x00002000L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP_MASK 0x00004000L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP 0x00004000L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_1_MASK 0xffff8000L + +// SQ_INSTRUCTION_CF_JMP_CALL_1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0_MASK 0x00000001L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0 0x00000001L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION_MASK 0x00000002L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION 0x00000002L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__BOOL_ADDR_MASK 0x000003fcL +#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION_MASK 0x00000400L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION 0x00000400L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE 0x00000800L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__OPCODE_MASK 0x0000f000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MASK 0x03ff0000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_1_MASK 0x1c000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL_MASK 0x20000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL 0x20000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_2_MASK 0xc0000000L + +// SQ_INSTRUCTION_CF_JMP_CALL_2 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__RESERVED_MASK 0x0001ffffL +#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION_MASK 0x00020000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION 0x00020000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__BOOL_ADDR_MASK 0x03fc0000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION_MASK 0x04000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION 0x04000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE 0x08000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__OPCODE_MASK 0xf0000000L + +// SQ_INSTRUCTION_CF_ALLOC_0 +#define SQ_INSTRUCTION_CF_ALLOC_0__SIZE_MASK 0x0000000fL +#define SQ_INSTRUCTION_CF_ALLOC_0__RESERVED_MASK 0xfffffff0L + +// SQ_INSTRUCTION_CF_ALLOC_1 +#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_0_MASK 0x000000ffL +#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL_MASK 0x00000100L +#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL 0x00000100L +#define SQ_INSTRUCTION_CF_ALLOC_1__BUFFER_SELECT_MASK 0x00000600L +#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE 0x00000800L +#define SQ_INSTRUCTION_CF_ALLOC_1__OPCODE_MASK 0x0000f000L +#define SQ_INSTRUCTION_CF_ALLOC_1__SIZE_MASK 0x000f0000L +#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_1_MASK 0xfff00000L + +// SQ_INSTRUCTION_CF_ALLOC_2 +#define SQ_INSTRUCTION_CF_ALLOC_2__RESERVED_MASK 0x00ffffffL +#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL_MASK 0x01000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL 0x01000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__BUFFER_SELECT_MASK 0x06000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE 0x08000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__OPCODE_MASK 0xf0000000L + +// SQ_INSTRUCTION_TFETCH_0 +#define SQ_INSTRUCTION_TFETCH_0__OPCODE_MASK 0x0000001fL +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_MASK 0x000007e0L +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM_MASK 0x00000800L +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM 0x00000800L +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_MASK 0x0003f000L +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM_MASK 0x00040000L +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM 0x00040000L +#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY_MASK 0x00080000L +#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY 0x00080000L +#define SQ_INSTRUCTION_TFETCH_0__CONST_INDEX_MASK 0x01f00000L +#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM_MASK 0x02000000L +#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM 0x02000000L +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_X_MASK 0x0c000000L +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Y_MASK 0x30000000L +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Z_MASK 0xc0000000L + +// SQ_INSTRUCTION_TFETCH_1 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_X_MASK 0x00000007L +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Y_MASK 0x00000038L +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Z_MASK 0x000001c0L +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_W_MASK 0x00000e00L +#define SQ_INSTRUCTION_TFETCH_1__MAG_FILTER_MASK 0x00003000L +#define SQ_INSTRUCTION_TFETCH_1__MIN_FILTER_MASK 0x0000c000L +#define SQ_INSTRUCTION_TFETCH_1__MIP_FILTER_MASK 0x00030000L +#define SQ_INSTRUCTION_TFETCH_1__ANISO_FILTER_MASK 0x001c0000L +#define SQ_INSTRUCTION_TFETCH_1__ARBITRARY_FILTER_MASK 0x00e00000L +#define SQ_INSTRUCTION_TFETCH_1__VOL_MAG_FILTER_MASK 0x03000000L +#define SQ_INSTRUCTION_TFETCH_1__VOL_MIN_FILTER_MASK 0x0c000000L +#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD_MASK 0x10000000L +#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD 0x10000000L +#define SQ_INSTRUCTION_TFETCH_1__USE_REG_LOD_MASK 0x60000000L +#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT_MASK 0x80000000L +#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT 0x80000000L + +// SQ_INSTRUCTION_TFETCH_2 +#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS_MASK 0x00000001L +#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS 0x00000001L +#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION_MASK 0x00000002L +#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION 0x00000002L +#define SQ_INSTRUCTION_TFETCH_2__LOD_BIAS_MASK 0x000001fcL +#define SQ_INSTRUCTION_TFETCH_2__UNUSED_MASK 0x0000fe00L +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_X_MASK 0x001f0000L +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Y_MASK 0x03e00000L +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Z_MASK 0x7c000000L +#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION_MASK 0x80000000L +#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION 0x80000000L + +// SQ_INSTRUCTION_VFETCH_0 +#define SQ_INSTRUCTION_VFETCH_0__OPCODE_MASK 0x0000001fL +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_MASK 0x000007e0L +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM_MASK 0x00000800L +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM 0x00000800L +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_MASK 0x0003f000L +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM_MASK 0x00040000L +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM 0x00040000L +#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE_MASK 0x00080000L +#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE 0x00080000L +#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_MASK 0x01f00000L +#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_SEL_MASK 0x06000000L +#define SQ_INSTRUCTION_VFETCH_0__SRC_SEL_MASK 0xc0000000L + +// SQ_INSTRUCTION_VFETCH_1 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_X_MASK 0x00000007L +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Y_MASK 0x00000038L +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Z_MASK 0x000001c0L +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_W_MASK 0x00000e00L +#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL_MASK 0x00001000L +#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL 0x00001000L +#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL_MASK 0x00002000L +#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL 0x00002000L +#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL_MASK 0x00004000L +#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL 0x00004000L +#define SQ_INSTRUCTION_VFETCH_1__DATA_FORMAT_MASK 0x003f0000L +#define SQ_INSTRUCTION_VFETCH_1__EXP_ADJUST_ALL_MASK 0x3f800000L +#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT_MASK 0x80000000L +#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT 0x80000000L + +// SQ_INSTRUCTION_VFETCH_2 +#define SQ_INSTRUCTION_VFETCH_2__STRIDE_MASK 0x000000ffL +#define SQ_INSTRUCTION_VFETCH_2__OFFSET_MASK 0x00ff0000L +#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION_MASK 0x80000000L +#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION 0x80000000L + +// SQ_CONSTANT_0 +#define SQ_CONSTANT_0__RED_MASK 0xffffffffL + +// SQ_CONSTANT_1 +#define SQ_CONSTANT_1__GREEN_MASK 0xffffffffL + +// SQ_CONSTANT_2 +#define SQ_CONSTANT_2__BLUE_MASK 0xffffffffL + +// SQ_CONSTANT_3 +#define SQ_CONSTANT_3__ALPHA_MASK 0xffffffffL + +// SQ_FETCH_0 +#define SQ_FETCH_0__VALUE_MASK 0xffffffffL + +// SQ_FETCH_1 +#define SQ_FETCH_1__VALUE_MASK 0xffffffffL + +// SQ_FETCH_2 +#define SQ_FETCH_2__VALUE_MASK 0xffffffffL + +// SQ_FETCH_3 +#define SQ_FETCH_3__VALUE_MASK 0xffffffffL + +// SQ_FETCH_4 +#define SQ_FETCH_4__VALUE_MASK 0xffffffffL + +// SQ_FETCH_5 +#define SQ_FETCH_5__VALUE_MASK 0xffffffffL + +// SQ_CONSTANT_VFETCH_0 +#define SQ_CONSTANT_VFETCH_0__TYPE_MASK 0x00000001L +#define SQ_CONSTANT_VFETCH_0__TYPE 0x00000001L +#define SQ_CONSTANT_VFETCH_0__STATE_MASK 0x00000002L +#define SQ_CONSTANT_VFETCH_0__STATE 0x00000002L +#define SQ_CONSTANT_VFETCH_0__BASE_ADDRESS_MASK 0xfffffffcL + +// SQ_CONSTANT_VFETCH_1 +#define SQ_CONSTANT_VFETCH_1__ENDIAN_SWAP_MASK 0x00000003L +#define SQ_CONSTANT_VFETCH_1__LIMIT_ADDRESS_MASK 0xfffffffcL + +// SQ_CONSTANT_T2 +#define SQ_CONSTANT_T2__VALUE_MASK 0xffffffffL + +// SQ_CONSTANT_T3 +#define SQ_CONSTANT_T3__VALUE_MASK 0xffffffffL + +// SQ_CF_BOOLEANS +#define SQ_CF_BOOLEANS__CF_BOOLEANS_0_MASK 0x000000ffL +#define SQ_CF_BOOLEANS__CF_BOOLEANS_1_MASK 0x0000ff00L +#define SQ_CF_BOOLEANS__CF_BOOLEANS_2_MASK 0x00ff0000L +#define SQ_CF_BOOLEANS__CF_BOOLEANS_3_MASK 0xff000000L + +// SQ_CF_LOOP +#define SQ_CF_LOOP__CF_LOOP_COUNT_MASK 0x000000ffL +#define SQ_CF_LOOP__CF_LOOP_START_MASK 0x0000ff00L +#define SQ_CF_LOOP__CF_LOOP_STEP_MASK 0x00ff0000L + +// SQ_CONSTANT_RT_0 +#define SQ_CONSTANT_RT_0__RED_MASK 0xffffffffL + +// SQ_CONSTANT_RT_1 +#define SQ_CONSTANT_RT_1__GREEN_MASK 0xffffffffL + +// SQ_CONSTANT_RT_2 +#define SQ_CONSTANT_RT_2__BLUE_MASK 0xffffffffL + +// SQ_CONSTANT_RT_3 +#define SQ_CONSTANT_RT_3__ALPHA_MASK 0xffffffffL + +// SQ_FETCH_RT_0 +#define SQ_FETCH_RT_0__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_1 +#define SQ_FETCH_RT_1__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_2 +#define SQ_FETCH_RT_2__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_3 +#define SQ_FETCH_RT_3__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_4 +#define SQ_FETCH_RT_4__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_5 +#define SQ_FETCH_RT_5__VALUE_MASK 0xffffffffL + +// SQ_CF_RT_BOOLEANS +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_0_MASK 0x000000ffL +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_1_MASK 0x0000ff00L +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_2_MASK 0x00ff0000L +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_3_MASK 0xff000000L + +// SQ_CF_RT_LOOP +#define SQ_CF_RT_LOOP__CF_LOOP_COUNT_MASK 0x000000ffL +#define SQ_CF_RT_LOOP__CF_LOOP_START_MASK 0x0000ff00L +#define SQ_CF_RT_LOOP__CF_LOOP_STEP_MASK 0x00ff0000L + +// SQ_VS_PROGRAM +#define SQ_VS_PROGRAM__BASE_MASK 0x00000fffL +#define SQ_VS_PROGRAM__SIZE_MASK 0x00fff000L + +// SQ_PS_PROGRAM +#define SQ_PS_PROGRAM__BASE_MASK 0x00000fffL +#define SQ_PS_PROGRAM__SIZE_MASK 0x00fff000L + +// SQ_CF_PROGRAM_SIZE +#define SQ_CF_PROGRAM_SIZE__VS_CF_SIZE_MASK 0x000007ffL +#define SQ_CF_PROGRAM_SIZE__PS_CF_SIZE_MASK 0x007ff000L + +// SQ_INTERPOLATOR_CNTL +#define SQ_INTERPOLATOR_CNTL__PARAM_SHADE_MASK 0x0000ffffL +#define SQ_INTERPOLATOR_CNTL__SAMPLING_PATTERN_MASK 0xffff0000L + +// SQ_PROGRAM_CNTL +#define SQ_PROGRAM_CNTL__VS_NUM_REG_MASK 0x0000003fL +#define SQ_PROGRAM_CNTL__PS_NUM_REG_MASK 0x00003f00L +#define SQ_PROGRAM_CNTL__VS_RESOURCE_MASK 0x00010000L +#define SQ_PROGRAM_CNTL__VS_RESOURCE 0x00010000L +#define SQ_PROGRAM_CNTL__PS_RESOURCE_MASK 0x00020000L +#define SQ_PROGRAM_CNTL__PS_RESOURCE 0x00020000L +#define SQ_PROGRAM_CNTL__PARAM_GEN_MASK 0x00040000L +#define SQ_PROGRAM_CNTL__PARAM_GEN 0x00040000L +#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX_MASK 0x00080000L +#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX 0x00080000L +#define SQ_PROGRAM_CNTL__VS_EXPORT_COUNT_MASK 0x00f00000L +#define SQ_PROGRAM_CNTL__VS_EXPORT_MODE_MASK 0x07000000L +#define SQ_PROGRAM_CNTL__PS_EXPORT_MODE_MASK 0x78000000L +#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX_MASK 0x80000000L +#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX 0x80000000L + +// SQ_WRAPPING_0 +#define SQ_WRAPPING_0__PARAM_WRAP_0_MASK 0x0000000fL +#define SQ_WRAPPING_0__PARAM_WRAP_1_MASK 0x000000f0L +#define SQ_WRAPPING_0__PARAM_WRAP_2_MASK 0x00000f00L +#define SQ_WRAPPING_0__PARAM_WRAP_3_MASK 0x0000f000L +#define SQ_WRAPPING_0__PARAM_WRAP_4_MASK 0x000f0000L +#define SQ_WRAPPING_0__PARAM_WRAP_5_MASK 0x00f00000L +#define SQ_WRAPPING_0__PARAM_WRAP_6_MASK 0x0f000000L +#define SQ_WRAPPING_0__PARAM_WRAP_7_MASK 0xf0000000L + +// SQ_WRAPPING_1 +#define SQ_WRAPPING_1__PARAM_WRAP_8_MASK 0x0000000fL +#define SQ_WRAPPING_1__PARAM_WRAP_9_MASK 0x000000f0L +#define SQ_WRAPPING_1__PARAM_WRAP_10_MASK 0x00000f00L +#define SQ_WRAPPING_1__PARAM_WRAP_11_MASK 0x0000f000L +#define SQ_WRAPPING_1__PARAM_WRAP_12_MASK 0x000f0000L +#define SQ_WRAPPING_1__PARAM_WRAP_13_MASK 0x00f00000L +#define SQ_WRAPPING_1__PARAM_WRAP_14_MASK 0x0f000000L +#define SQ_WRAPPING_1__PARAM_WRAP_15_MASK 0xf0000000L + +// SQ_VS_CONST +#define SQ_VS_CONST__BASE_MASK 0x000001ffL +#define SQ_VS_CONST__SIZE_MASK 0x001ff000L + +// SQ_PS_CONST +#define SQ_PS_CONST__BASE_MASK 0x000001ffL +#define SQ_PS_CONST__SIZE_MASK 0x001ff000L + +// SQ_CONTEXT_MISC +#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE_MASK 0x00000001L +#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE 0x00000001L +#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY_MASK 0x00000002L +#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY 0x00000002L +#define SQ_CONTEXT_MISC__SC_SAMPLE_CNTL_MASK 0x0000000cL +#define SQ_CONTEXT_MISC__PARAM_GEN_POS_MASK 0x0000ff00L +#define SQ_CONTEXT_MISC__PERFCOUNTER_REF_MASK 0x00010000L +#define SQ_CONTEXT_MISC__PERFCOUNTER_REF 0x00010000L +#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE_MASK 0x00020000L +#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE 0x00020000L +#define SQ_CONTEXT_MISC__TX_CACHE_SEL_MASK 0x00040000L +#define SQ_CONTEXT_MISC__TX_CACHE_SEL 0x00040000L + +// SQ_CF_RD_BASE +#define SQ_CF_RD_BASE__RD_BASE_MASK 0x00000007L + +// SQ_DEBUG_MISC_0 +#define SQ_DEBUG_MISC_0__DB_PROB_ON_MASK 0x00000001L +#define SQ_DEBUG_MISC_0__DB_PROB_ON 0x00000001L +#define SQ_DEBUG_MISC_0__DB_PROB_BREAK_MASK 0x00000010L +#define SQ_DEBUG_MISC_0__DB_PROB_BREAK 0x00000010L +#define SQ_DEBUG_MISC_0__DB_PROB_ADDR_MASK 0x0007ff00L +#define SQ_DEBUG_MISC_0__DB_PROB_COUNT_MASK 0xff000000L + +// SQ_DEBUG_MISC_1 +#define SQ_DEBUG_MISC_1__DB_ON_PIX_MASK 0x00000001L +#define SQ_DEBUG_MISC_1__DB_ON_PIX 0x00000001L +#define SQ_DEBUG_MISC_1__DB_ON_VTX_MASK 0x00000002L +#define SQ_DEBUG_MISC_1__DB_ON_VTX 0x00000002L +#define SQ_DEBUG_MISC_1__DB_INST_COUNT_MASK 0x0000ff00L +#define SQ_DEBUG_MISC_1__DB_BREAK_ADDR_MASK 0x07ff0000L + +// MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG__SAME_PAGE_LIMIT_MASK 0x0000003fL +#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY_MASK 0x00000040L +#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY 0x00000040L +#define MH_ARBITER_CONFIG__L1_ARB_ENABLE_MASK 0x00000080L +#define MH_ARBITER_CONFIG__L1_ARB_ENABLE 0x00000080L +#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE_MASK 0x00000100L +#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE 0x00000100L +#define MH_ARBITER_CONFIG__L2_ARB_CONTROL_MASK 0x00000200L +#define MH_ARBITER_CONFIG__L2_ARB_CONTROL 0x00000200L +#define MH_ARBITER_CONFIG__PAGE_SIZE_MASK 0x00001c00L +#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE_MASK 0x00002000L +#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE 0x00002000L +#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE_MASK 0x00004000L +#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE 0x00004000L +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE_MASK 0x00008000L +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE 0x00008000L +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_MASK 0x003f0000L +#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE_MASK 0x00400000L +#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE 0x00400000L +#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE_MASK 0x00800000L +#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE 0x00800000L +#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE_MASK 0x01000000L +#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE 0x01000000L +#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE_MASK 0x02000000L +#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE 0x02000000L +#define MH_ARBITER_CONFIG__PA_CLNT_ENABLE_MASK 0x04000000L +#define MH_ARBITER_CONFIG__PA_CLNT_ENABLE 0x04000000L + +// MH_CLNT_AXI_ID_REUSE +#define MH_CLNT_AXI_ID_REUSE__CPw_ID_MASK 0x00000007L +#define MH_CLNT_AXI_ID_REUSE__RESERVED1_MASK 0x00000008L +#define MH_CLNT_AXI_ID_REUSE__RESERVED1 0x00000008L +#define MH_CLNT_AXI_ID_REUSE__RBw_ID_MASK 0x00000070L +#define MH_CLNT_AXI_ID_REUSE__RESERVED2_MASK 0x00000080L +#define MH_CLNT_AXI_ID_REUSE__RESERVED2 0x00000080L +#define MH_CLNT_AXI_ID_REUSE__MMUr_ID_MASK 0x00000700L +#define MH_CLNT_AXI_ID_REUSE__RESERVED3_MASK 0x00000800L +#define MH_CLNT_AXI_ID_REUSE__RESERVED3 0x00000800L +#define MH_CLNT_AXI_ID_REUSE__PAw_ID_MASK 0x00007000L + +// MH_INTERRUPT_MASK +#define MH_INTERRUPT_MASK__AXI_READ_ERROR_MASK 0x00000001L +#define MH_INTERRUPT_MASK__AXI_READ_ERROR 0x00000001L +#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR_MASK 0x00000002L +#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR 0x00000002L +#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT_MASK 0x00000004L +#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT 0x00000004L + +// MH_INTERRUPT_STATUS +#define MH_INTERRUPT_STATUS__AXI_READ_ERROR_MASK 0x00000001L +#define MH_INTERRUPT_STATUS__AXI_READ_ERROR 0x00000001L +#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR_MASK 0x00000002L +#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR 0x00000002L +#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT_MASK 0x00000004L +#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT 0x00000004L + +// MH_INTERRUPT_CLEAR +#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR_MASK 0x00000001L +#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR 0x00000001L +#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR_MASK 0x00000002L +#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR 0x00000002L +#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT_MASK 0x00000004L +#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT 0x00000004L + +// MH_AXI_ERROR +#define MH_AXI_ERROR__AXI_READ_ID_MASK 0x00000007L +#define MH_AXI_ERROR__AXI_READ_ERROR_MASK 0x00000008L +#define MH_AXI_ERROR__AXI_READ_ERROR 0x00000008L +#define MH_AXI_ERROR__AXI_WRITE_ID_MASK 0x00000070L +#define MH_AXI_ERROR__AXI_WRITE_ERROR_MASK 0x00000080L +#define MH_AXI_ERROR__AXI_WRITE_ERROR 0x00000080L + +// MH_PERFCOUNTER0_SELECT +#define MH_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// MH_PERFCOUNTER1_SELECT +#define MH_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL + +// MH_PERFCOUNTER0_CONFIG +#define MH_PERFCOUNTER0_CONFIG__N_VALUE_MASK 0x000000ffL + +// MH_PERFCOUNTER1_CONFIG +#define MH_PERFCOUNTER1_CONFIG__N_VALUE_MASK 0x000000ffL + +// MH_PERFCOUNTER0_LOW +#define MH_PERFCOUNTER0_LOW__PERF_COUNTER_LOW_MASK 0xffffffffL + +// MH_PERFCOUNTER1_LOW +#define MH_PERFCOUNTER1_LOW__PERF_COUNTER_LOW_MASK 0xffffffffL + +// MH_PERFCOUNTER0_HI +#define MH_PERFCOUNTER0_HI__PERF_COUNTER_HI_MASK 0x0000ffffL + +// MH_PERFCOUNTER1_HI +#define MH_PERFCOUNTER1_HI__PERF_COUNTER_HI_MASK 0x0000ffffL + +// MH_DEBUG_CTRL +#define MH_DEBUG_CTRL__INDEX_MASK 0x0000003fL + +// MH_DEBUG_DATA +#define MH_DEBUG_DATA__DATA_MASK 0xffffffffL + +// MH_AXI_HALT_CONTROL +#define MH_AXI_HALT_CONTROL__AXI_HALT_MASK 0x00000001L +#define MH_AXI_HALT_CONTROL__AXI_HALT 0x00000001L + +// MH_DEBUG_REG00 +#define MH_DEBUG_REG00__MH_BUSY_MASK 0x00000001L +#define MH_DEBUG_REG00__MH_BUSY 0x00000001L +#define MH_DEBUG_REG00__TRANS_OUTSTANDING_MASK 0x00000002L +#define MH_DEBUG_REG00__TRANS_OUTSTANDING 0x00000002L +#define MH_DEBUG_REG00__CP_REQUEST_MASK 0x00000004L +#define MH_DEBUG_REG00__CP_REQUEST 0x00000004L +#define MH_DEBUG_REG00__VGT_REQUEST_MASK 0x00000008L +#define MH_DEBUG_REG00__VGT_REQUEST 0x00000008L +#define MH_DEBUG_REG00__TC_REQUEST_MASK 0x00000010L +#define MH_DEBUG_REG00__TC_REQUEST 0x00000010L +#define MH_DEBUG_REG00__TC_CAM_EMPTY_MASK 0x00000020L +#define MH_DEBUG_REG00__TC_CAM_EMPTY 0x00000020L +#define MH_DEBUG_REG00__TC_CAM_FULL_MASK 0x00000040L +#define MH_DEBUG_REG00__TC_CAM_FULL 0x00000040L +#define MH_DEBUG_REG00__TCD_EMPTY_MASK 0x00000080L +#define MH_DEBUG_REG00__TCD_EMPTY 0x00000080L +#define MH_DEBUG_REG00__TCD_FULL_MASK 0x00000100L +#define MH_DEBUG_REG00__TCD_FULL 0x00000100L +#define MH_DEBUG_REG00__RB_REQUEST_MASK 0x00000200L +#define MH_DEBUG_REG00__RB_REQUEST 0x00000200L +#define MH_DEBUG_REG00__PA_REQUEST_MASK 0x00000400L +#define MH_DEBUG_REG00__PA_REQUEST 0x00000400L +#define MH_DEBUG_REG00__MH_CLK_EN_STATE_MASK 0x00000800L +#define MH_DEBUG_REG00__MH_CLK_EN_STATE 0x00000800L +#define MH_DEBUG_REG00__ARQ_EMPTY_MASK 0x00001000L +#define MH_DEBUG_REG00__ARQ_EMPTY 0x00001000L +#define MH_DEBUG_REG00__ARQ_FULL_MASK 0x00002000L +#define MH_DEBUG_REG00__ARQ_FULL 0x00002000L +#define MH_DEBUG_REG00__WDB_EMPTY_MASK 0x00004000L +#define MH_DEBUG_REG00__WDB_EMPTY 0x00004000L +#define MH_DEBUG_REG00__WDB_FULL_MASK 0x00008000L +#define MH_DEBUG_REG00__WDB_FULL 0x00008000L +#define MH_DEBUG_REG00__AXI_AVALID_MASK 0x00010000L +#define MH_DEBUG_REG00__AXI_AVALID 0x00010000L +#define MH_DEBUG_REG00__AXI_AREADY_MASK 0x00020000L +#define MH_DEBUG_REG00__AXI_AREADY 0x00020000L +#define MH_DEBUG_REG00__AXI_ARVALID_MASK 0x00040000L +#define MH_DEBUG_REG00__AXI_ARVALID 0x00040000L +#define MH_DEBUG_REG00__AXI_ARREADY_MASK 0x00080000L +#define MH_DEBUG_REG00__AXI_ARREADY 0x00080000L +#define MH_DEBUG_REG00__AXI_WVALID_MASK 0x00100000L +#define MH_DEBUG_REG00__AXI_WVALID 0x00100000L +#define MH_DEBUG_REG00__AXI_WREADY_MASK 0x00200000L +#define MH_DEBUG_REG00__AXI_WREADY 0x00200000L +#define MH_DEBUG_REG00__AXI_RVALID_MASK 0x00400000L +#define MH_DEBUG_REG00__AXI_RVALID 0x00400000L +#define MH_DEBUG_REG00__AXI_RREADY_MASK 0x00800000L +#define MH_DEBUG_REG00__AXI_RREADY 0x00800000L +#define MH_DEBUG_REG00__AXI_BVALID_MASK 0x01000000L +#define MH_DEBUG_REG00__AXI_BVALID 0x01000000L +#define MH_DEBUG_REG00__AXI_BREADY_MASK 0x02000000L +#define MH_DEBUG_REG00__AXI_BREADY 0x02000000L +#define MH_DEBUG_REG00__AXI_HALT_REQ_MASK 0x04000000L +#define MH_DEBUG_REG00__AXI_HALT_REQ 0x04000000L +#define MH_DEBUG_REG00__AXI_HALT_ACK_MASK 0x08000000L +#define MH_DEBUG_REG00__AXI_HALT_ACK 0x08000000L +#define MH_DEBUG_REG00__AXI_RDY_ENA_MASK 0x10000000L +#define MH_DEBUG_REG00__AXI_RDY_ENA 0x10000000L + +// MH_DEBUG_REG01 +#define MH_DEBUG_REG01__CP_SEND_q_MASK 0x00000001L +#define MH_DEBUG_REG01__CP_SEND_q 0x00000001L +#define MH_DEBUG_REG01__CP_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG01__CP_RTR_q 0x00000002L +#define MH_DEBUG_REG01__CP_WRITE_q_MASK 0x00000004L +#define MH_DEBUG_REG01__CP_WRITE_q 0x00000004L +#define MH_DEBUG_REG01__CP_TAG_q_MASK 0x00000038L +#define MH_DEBUG_REG01__CP_BLEN_q_MASK 0x00000040L +#define MH_DEBUG_REG01__CP_BLEN_q 0x00000040L +#define MH_DEBUG_REG01__VGT_SEND_q_MASK 0x00000080L +#define MH_DEBUG_REG01__VGT_SEND_q 0x00000080L +#define MH_DEBUG_REG01__VGT_RTR_q_MASK 0x00000100L +#define MH_DEBUG_REG01__VGT_RTR_q 0x00000100L +#define MH_DEBUG_REG01__VGT_TAG_q_MASK 0x00000200L +#define MH_DEBUG_REG01__VGT_TAG_q 0x00000200L +#define MH_DEBUG_REG01__TC_SEND_q_MASK 0x00000400L +#define MH_DEBUG_REG01__TC_SEND_q 0x00000400L +#define MH_DEBUG_REG01__TC_RTR_q_MASK 0x00000800L +#define MH_DEBUG_REG01__TC_RTR_q 0x00000800L +#define MH_DEBUG_REG01__TC_BLEN_q_MASK 0x00001000L +#define MH_DEBUG_REG01__TC_BLEN_q 0x00001000L +#define MH_DEBUG_REG01__TC_ROQ_SEND_q_MASK 0x00002000L +#define MH_DEBUG_REG01__TC_ROQ_SEND_q 0x00002000L +#define MH_DEBUG_REG01__TC_ROQ_RTR_q_MASK 0x00004000L +#define MH_DEBUG_REG01__TC_ROQ_RTR_q 0x00004000L +#define MH_DEBUG_REG01__TC_MH_written_MASK 0x00008000L +#define MH_DEBUG_REG01__TC_MH_written 0x00008000L +#define MH_DEBUG_REG01__RB_SEND_q_MASK 0x00010000L +#define MH_DEBUG_REG01__RB_SEND_q 0x00010000L +#define MH_DEBUG_REG01__RB_RTR_q_MASK 0x00020000L +#define MH_DEBUG_REG01__RB_RTR_q 0x00020000L +#define MH_DEBUG_REG01__PA_SEND_q_MASK 0x00040000L +#define MH_DEBUG_REG01__PA_SEND_q 0x00040000L +#define MH_DEBUG_REG01__PA_RTR_q_MASK 0x00080000L +#define MH_DEBUG_REG01__PA_RTR_q 0x00080000L + +// MH_DEBUG_REG02 +#define MH_DEBUG_REG02__MH_CP_grb_send_MASK 0x00000001L +#define MH_DEBUG_REG02__MH_CP_grb_send 0x00000001L +#define MH_DEBUG_REG02__MH_VGT_grb_send_MASK 0x00000002L +#define MH_DEBUG_REG02__MH_VGT_grb_send 0x00000002L +#define MH_DEBUG_REG02__MH_TC_mcsend_MASK 0x00000004L +#define MH_DEBUG_REG02__MH_TC_mcsend 0x00000004L +#define MH_DEBUG_REG02__MH_CLNT_rlast_MASK 0x00000008L +#define MH_DEBUG_REG02__MH_CLNT_rlast 0x00000008L +#define MH_DEBUG_REG02__MH_CLNT_tag_MASK 0x00000070L +#define MH_DEBUG_REG02__RDC_RID_MASK 0x00000380L +#define MH_DEBUG_REG02__RDC_RRESP_MASK 0x00000c00L +#define MH_DEBUG_REG02__MH_CP_writeclean_MASK 0x00001000L +#define MH_DEBUG_REG02__MH_CP_writeclean 0x00001000L +#define MH_DEBUG_REG02__MH_RB_writeclean_MASK 0x00002000L +#define MH_DEBUG_REG02__MH_RB_writeclean 0x00002000L +#define MH_DEBUG_REG02__MH_PA_writeclean_MASK 0x00004000L +#define MH_DEBUG_REG02__MH_PA_writeclean 0x00004000L +#define MH_DEBUG_REG02__BRC_BID_MASK 0x00038000L +#define MH_DEBUG_REG02__BRC_BRESP_MASK 0x000c0000L + +// MH_DEBUG_REG03 +#define MH_DEBUG_REG03__MH_CLNT_data_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG04 +#define MH_DEBUG_REG04__MH_CLNT_data_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG05 +#define MH_DEBUG_REG05__CP_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG05__CP_MH_send 0x00000001L +#define MH_DEBUG_REG05__CP_MH_write_MASK 0x00000002L +#define MH_DEBUG_REG05__CP_MH_write 0x00000002L +#define MH_DEBUG_REG05__CP_MH_tag_MASK 0x0000001cL +#define MH_DEBUG_REG05__CP_MH_ad_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG06 +#define MH_DEBUG_REG06__CP_MH_data_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG07 +#define MH_DEBUG_REG07__CP_MH_data_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG08 +#define MH_DEBUG_REG08__CP_MH_be_MASK 0x000000ffL +#define MH_DEBUG_REG08__RB_MH_be_MASK 0x0000ff00L +#define MH_DEBUG_REG08__PA_MH_be_MASK 0x00ff0000L + +// MH_DEBUG_REG09 +#define MH_DEBUG_REG09__ALWAYS_ZERO_MASK 0x00000007L +#define MH_DEBUG_REG09__VGT_MH_send_MASK 0x00000008L +#define MH_DEBUG_REG09__VGT_MH_send 0x00000008L +#define MH_DEBUG_REG09__VGT_MH_tagbe_MASK 0x00000010L +#define MH_DEBUG_REG09__VGT_MH_tagbe 0x00000010L +#define MH_DEBUG_REG09__VGT_MH_ad_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG10 +#define MH_DEBUG_REG10__ALWAYS_ZERO_MASK 0x00000003L +#define MH_DEBUG_REG10__TC_MH_send_MASK 0x00000004L +#define MH_DEBUG_REG10__TC_MH_send 0x00000004L +#define MH_DEBUG_REG10__TC_MH_mask_MASK 0x00000018L +#define MH_DEBUG_REG10__TC_MH_addr_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG11 +#define MH_DEBUG_REG11__TC_MH_info_MASK 0x01ffffffL +#define MH_DEBUG_REG11__TC_MH_send_MASK 0x02000000L +#define MH_DEBUG_REG11__TC_MH_send 0x02000000L + +// MH_DEBUG_REG12 +#define MH_DEBUG_REG12__MH_TC_mcinfo_MASK 0x01ffffffL +#define MH_DEBUG_REG12__MH_TC_mcinfo_send_MASK 0x02000000L +#define MH_DEBUG_REG12__MH_TC_mcinfo_send 0x02000000L +#define MH_DEBUG_REG12__TC_MH_written_MASK 0x04000000L +#define MH_DEBUG_REG12__TC_MH_written 0x04000000L + +// MH_DEBUG_REG13 +#define MH_DEBUG_REG13__ALWAYS_ZERO_MASK 0x00000003L +#define MH_DEBUG_REG13__TC_ROQ_SEND_MASK 0x00000004L +#define MH_DEBUG_REG13__TC_ROQ_SEND 0x00000004L +#define MH_DEBUG_REG13__TC_ROQ_MASK_MASK 0x00000018L +#define MH_DEBUG_REG13__TC_ROQ_ADDR_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG14 +#define MH_DEBUG_REG14__TC_ROQ_INFO_MASK 0x01ffffffL +#define MH_DEBUG_REG14__TC_ROQ_SEND_MASK 0x02000000L +#define MH_DEBUG_REG14__TC_ROQ_SEND 0x02000000L + +// MH_DEBUG_REG15 +#define MH_DEBUG_REG15__ALWAYS_ZERO_MASK 0x0000000fL +#define MH_DEBUG_REG15__RB_MH_send_MASK 0x00000010L +#define MH_DEBUG_REG15__RB_MH_send 0x00000010L +#define MH_DEBUG_REG15__RB_MH_addr_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG16 +#define MH_DEBUG_REG16__RB_MH_data_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG17 +#define MH_DEBUG_REG17__RB_MH_data_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG18 +#define MH_DEBUG_REG18__ALWAYS_ZERO_MASK 0x0000000fL +#define MH_DEBUG_REG18__PA_MH_send_MASK 0x00000010L +#define MH_DEBUG_REG18__PA_MH_send 0x00000010L +#define MH_DEBUG_REG18__PA_MH_addr_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG19 +#define MH_DEBUG_REG19__PA_MH_data_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG20 +#define MH_DEBUG_REG20__PA_MH_data_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG21 +#define MH_DEBUG_REG21__AVALID_q_MASK 0x00000001L +#define MH_DEBUG_REG21__AVALID_q 0x00000001L +#define MH_DEBUG_REG21__AREADY_q_MASK 0x00000002L +#define MH_DEBUG_REG21__AREADY_q 0x00000002L +#define MH_DEBUG_REG21__AID_q_MASK 0x0000001cL +#define MH_DEBUG_REG21__ALEN_q_2_0_MASK 0x000000e0L +#define MH_DEBUG_REG21__ARVALID_q_MASK 0x00000100L +#define MH_DEBUG_REG21__ARVALID_q 0x00000100L +#define MH_DEBUG_REG21__ARREADY_q_MASK 0x00000200L +#define MH_DEBUG_REG21__ARREADY_q 0x00000200L +#define MH_DEBUG_REG21__ARID_q_MASK 0x00001c00L +#define MH_DEBUG_REG21__ARLEN_q_1_0_MASK 0x00006000L +#define MH_DEBUG_REG21__RVALID_q_MASK 0x00008000L +#define MH_DEBUG_REG21__RVALID_q 0x00008000L +#define MH_DEBUG_REG21__RREADY_q_MASK 0x00010000L +#define MH_DEBUG_REG21__RREADY_q 0x00010000L +#define MH_DEBUG_REG21__RLAST_q_MASK 0x00020000L +#define MH_DEBUG_REG21__RLAST_q 0x00020000L +#define MH_DEBUG_REG21__RID_q_MASK 0x001c0000L +#define MH_DEBUG_REG21__WVALID_q_MASK 0x00200000L +#define MH_DEBUG_REG21__WVALID_q 0x00200000L +#define MH_DEBUG_REG21__WREADY_q_MASK 0x00400000L +#define MH_DEBUG_REG21__WREADY_q 0x00400000L +#define MH_DEBUG_REG21__WLAST_q_MASK 0x00800000L +#define MH_DEBUG_REG21__WLAST_q 0x00800000L +#define MH_DEBUG_REG21__WID_q_MASK 0x07000000L +#define MH_DEBUG_REG21__BVALID_q_MASK 0x08000000L +#define MH_DEBUG_REG21__BVALID_q 0x08000000L +#define MH_DEBUG_REG21__BREADY_q_MASK 0x10000000L +#define MH_DEBUG_REG21__BREADY_q 0x10000000L +#define MH_DEBUG_REG21__BID_q_MASK 0xe0000000L + +// MH_DEBUG_REG22 +#define MH_DEBUG_REG22__AVALID_q_MASK 0x00000001L +#define MH_DEBUG_REG22__AVALID_q 0x00000001L +#define MH_DEBUG_REG22__AREADY_q_MASK 0x00000002L +#define MH_DEBUG_REG22__AREADY_q 0x00000002L +#define MH_DEBUG_REG22__AID_q_MASK 0x0000001cL +#define MH_DEBUG_REG22__ALEN_q_1_0_MASK 0x00000060L +#define MH_DEBUG_REG22__ARVALID_q_MASK 0x00000080L +#define MH_DEBUG_REG22__ARVALID_q 0x00000080L +#define MH_DEBUG_REG22__ARREADY_q_MASK 0x00000100L +#define MH_DEBUG_REG22__ARREADY_q 0x00000100L +#define MH_DEBUG_REG22__ARID_q_MASK 0x00000e00L +#define MH_DEBUG_REG22__ARLEN_q_1_1_MASK 0x00001000L +#define MH_DEBUG_REG22__ARLEN_q_1_1 0x00001000L +#define MH_DEBUG_REG22__WVALID_q_MASK 0x00002000L +#define MH_DEBUG_REG22__WVALID_q 0x00002000L +#define MH_DEBUG_REG22__WREADY_q_MASK 0x00004000L +#define MH_DEBUG_REG22__WREADY_q 0x00004000L +#define MH_DEBUG_REG22__WLAST_q_MASK 0x00008000L +#define MH_DEBUG_REG22__WLAST_q 0x00008000L +#define MH_DEBUG_REG22__WID_q_MASK 0x00070000L +#define MH_DEBUG_REG22__WSTRB_q_MASK 0x07f80000L +#define MH_DEBUG_REG22__BVALID_q_MASK 0x08000000L +#define MH_DEBUG_REG22__BVALID_q 0x08000000L +#define MH_DEBUG_REG22__BREADY_q_MASK 0x10000000L +#define MH_DEBUG_REG22__BREADY_q 0x10000000L +#define MH_DEBUG_REG22__BID_q_MASK 0xe0000000L + +// MH_DEBUG_REG23 +#define MH_DEBUG_REG23__ARC_CTRL_RE_q_MASK 0x00000001L +#define MH_DEBUG_REG23__ARC_CTRL_RE_q 0x00000001L +#define MH_DEBUG_REG23__CTRL_ARC_ID_MASK 0x0000000eL +#define MH_DEBUG_REG23__CTRL_ARC_PAD_MASK 0xfffffff0L + +// MH_DEBUG_REG24 +#define MH_DEBUG_REG24__ALWAYS_ZERO_MASK 0x00000003L +#define MH_DEBUG_REG24__REG_A_MASK 0x0000fffcL +#define MH_DEBUG_REG24__REG_RE_MASK 0x00010000L +#define MH_DEBUG_REG24__REG_RE 0x00010000L +#define MH_DEBUG_REG24__REG_WE_MASK 0x00020000L +#define MH_DEBUG_REG24__REG_WE 0x00020000L +#define MH_DEBUG_REG24__BLOCK_RS_MASK 0x00040000L +#define MH_DEBUG_REG24__BLOCK_RS 0x00040000L + +// MH_DEBUG_REG25 +#define MH_DEBUG_REG25__REG_WD_MASK 0xffffffffL + +// MH_DEBUG_REG26 +#define MH_DEBUG_REG26__MH_RBBM_busy_MASK 0x00000001L +#define MH_DEBUG_REG26__MH_RBBM_busy 0x00000001L +#define MH_DEBUG_REG26__MH_CIB_mh_clk_en_int_MASK 0x00000002L +#define MH_DEBUG_REG26__MH_CIB_mh_clk_en_int 0x00000002L +#define MH_DEBUG_REG26__MH_CIB_mmu_clk_en_int_MASK 0x00000004L +#define MH_DEBUG_REG26__MH_CIB_mmu_clk_en_int 0x00000004L +#define MH_DEBUG_REG26__MH_CIB_tcroq_clk_en_int_MASK 0x00000008L +#define MH_DEBUG_REG26__MH_CIB_tcroq_clk_en_int 0x00000008L +#define MH_DEBUG_REG26__GAT_CLK_ENA_MASK 0x00000010L +#define MH_DEBUG_REG26__GAT_CLK_ENA 0x00000010L +#define MH_DEBUG_REG26__RBBM_MH_clk_en_override_MASK 0x00000020L +#define MH_DEBUG_REG26__RBBM_MH_clk_en_override 0x00000020L +#define MH_DEBUG_REG26__CNT_q_MASK 0x00000fc0L +#define MH_DEBUG_REG26__TCD_EMPTY_q_MASK 0x00001000L +#define MH_DEBUG_REG26__TCD_EMPTY_q 0x00001000L +#define MH_DEBUG_REG26__TC_ROQ_EMPTY_MASK 0x00002000L +#define MH_DEBUG_REG26__TC_ROQ_EMPTY 0x00002000L +#define MH_DEBUG_REG26__MH_BUSY_d_MASK 0x00004000L +#define MH_DEBUG_REG26__MH_BUSY_d 0x00004000L +#define MH_DEBUG_REG26__ANY_CLNT_BUSY_MASK 0x00008000L +#define MH_DEBUG_REG26__ANY_CLNT_BUSY 0x00008000L +#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00010000L +#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_ALL 0x00010000L +#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_TC_MASK 0x00020000L +#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_TC 0x00020000L +#define MH_DEBUG_REG26__CP_SEND_q_MASK 0x00040000L +#define MH_DEBUG_REG26__CP_SEND_q 0x00040000L +#define MH_DEBUG_REG26__CP_RTR_q_MASK 0x00080000L +#define MH_DEBUG_REG26__CP_RTR_q 0x00080000L +#define MH_DEBUG_REG26__VGT_SEND_q_MASK 0x00100000L +#define MH_DEBUG_REG26__VGT_SEND_q 0x00100000L +#define MH_DEBUG_REG26__VGT_RTR_q_MASK 0x00200000L +#define MH_DEBUG_REG26__VGT_RTR_q 0x00200000L +#define MH_DEBUG_REG26__TC_ROQ_SEND_q_MASK 0x00400000L +#define MH_DEBUG_REG26__TC_ROQ_SEND_q 0x00400000L +#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q_MASK 0x00800000L +#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q 0x00800000L +#define MH_DEBUG_REG26__RB_SEND_q_MASK 0x01000000L +#define MH_DEBUG_REG26__RB_SEND_q 0x01000000L +#define MH_DEBUG_REG26__RB_RTR_q_MASK 0x02000000L +#define MH_DEBUG_REG26__RB_RTR_q 0x02000000L +#define MH_DEBUG_REG26__PA_SEND_q_MASK 0x04000000L +#define MH_DEBUG_REG26__PA_SEND_q 0x04000000L +#define MH_DEBUG_REG26__PA_RTR_q_MASK 0x08000000L +#define MH_DEBUG_REG26__PA_RTR_q 0x08000000L +#define MH_DEBUG_REG26__RDC_VALID_MASK 0x10000000L +#define MH_DEBUG_REG26__RDC_VALID 0x10000000L +#define MH_DEBUG_REG26__RDC_RLAST_MASK 0x20000000L +#define MH_DEBUG_REG26__RDC_RLAST 0x20000000L +#define MH_DEBUG_REG26__TLBMISS_VALID_MASK 0x40000000L +#define MH_DEBUG_REG26__TLBMISS_VALID 0x40000000L +#define MH_DEBUG_REG26__BRC_VALID_MASK 0x80000000L +#define MH_DEBUG_REG26__BRC_VALID 0x80000000L + +// MH_DEBUG_REG27 +#define MH_DEBUG_REG27__EFF2_FP_WINNER_MASK 0x00000007L +#define MH_DEBUG_REG27__EFF2_LRU_WINNER_out_MASK 0x00000038L +#define MH_DEBUG_REG27__EFF1_WINNER_MASK 0x000001c0L +#define MH_DEBUG_REG27__ARB_WINNER_MASK 0x00000e00L +#define MH_DEBUG_REG27__ARB_WINNER_q_MASK 0x00007000L +#define MH_DEBUG_REG27__EFF1_WIN_MASK 0x00008000L +#define MH_DEBUG_REG27__EFF1_WIN 0x00008000L +#define MH_DEBUG_REG27__KILL_EFF1_MASK 0x00010000L +#define MH_DEBUG_REG27__KILL_EFF1 0x00010000L +#define MH_DEBUG_REG27__ARB_HOLD_MASK 0x00020000L +#define MH_DEBUG_REG27__ARB_HOLD 0x00020000L +#define MH_DEBUG_REG27__ARB_RTR_q_MASK 0x00040000L +#define MH_DEBUG_REG27__ARB_RTR_q 0x00040000L +#define MH_DEBUG_REG27__CP_SEND_QUAL_MASK 0x00080000L +#define MH_DEBUG_REG27__CP_SEND_QUAL 0x00080000L +#define MH_DEBUG_REG27__VGT_SEND_QUAL_MASK 0x00100000L +#define MH_DEBUG_REG27__VGT_SEND_QUAL 0x00100000L +#define MH_DEBUG_REG27__TC_SEND_QUAL_MASK 0x00200000L +#define MH_DEBUG_REG27__TC_SEND_QUAL 0x00200000L +#define MH_DEBUG_REG27__TC_SEND_EFF1_QUAL_MASK 0x00400000L +#define MH_DEBUG_REG27__TC_SEND_EFF1_QUAL 0x00400000L +#define MH_DEBUG_REG27__RB_SEND_QUAL_MASK 0x00800000L +#define MH_DEBUG_REG27__RB_SEND_QUAL 0x00800000L +#define MH_DEBUG_REG27__PA_SEND_QUAL_MASK 0x01000000L +#define MH_DEBUG_REG27__PA_SEND_QUAL 0x01000000L +#define MH_DEBUG_REG27__ARB_QUAL_MASK 0x02000000L +#define MH_DEBUG_REG27__ARB_QUAL 0x02000000L +#define MH_DEBUG_REG27__CP_EFF1_REQ_MASK 0x04000000L +#define MH_DEBUG_REG27__CP_EFF1_REQ 0x04000000L +#define MH_DEBUG_REG27__VGT_EFF1_REQ_MASK 0x08000000L +#define MH_DEBUG_REG27__VGT_EFF1_REQ 0x08000000L +#define MH_DEBUG_REG27__TC_EFF1_REQ_MASK 0x10000000L +#define MH_DEBUG_REG27__TC_EFF1_REQ 0x10000000L +#define MH_DEBUG_REG27__RB_EFF1_REQ_MASK 0x20000000L +#define MH_DEBUG_REG27__RB_EFF1_REQ 0x20000000L +#define MH_DEBUG_REG27__TCD_NEARFULL_q_MASK 0x40000000L +#define MH_DEBUG_REG27__TCD_NEARFULL_q 0x40000000L +#define MH_DEBUG_REG27__TCHOLD_IP_q_MASK 0x80000000L +#define MH_DEBUG_REG27__TCHOLD_IP_q 0x80000000L + +// MH_DEBUG_REG28 +#define MH_DEBUG_REG28__EFF1_WINNER_MASK 0x00000007L +#define MH_DEBUG_REG28__ARB_WINNER_MASK 0x00000038L +#define MH_DEBUG_REG28__CP_SEND_QUAL_MASK 0x00000040L +#define MH_DEBUG_REG28__CP_SEND_QUAL 0x00000040L +#define MH_DEBUG_REG28__VGT_SEND_QUAL_MASK 0x00000080L +#define MH_DEBUG_REG28__VGT_SEND_QUAL 0x00000080L +#define MH_DEBUG_REG28__TC_SEND_QUAL_MASK 0x00000100L +#define MH_DEBUG_REG28__TC_SEND_QUAL 0x00000100L +#define MH_DEBUG_REG28__TC_SEND_EFF1_QUAL_MASK 0x00000200L +#define MH_DEBUG_REG28__TC_SEND_EFF1_QUAL 0x00000200L +#define MH_DEBUG_REG28__RB_SEND_QUAL_MASK 0x00000400L +#define MH_DEBUG_REG28__RB_SEND_QUAL 0x00000400L +#define MH_DEBUG_REG28__ARB_QUAL_MASK 0x00000800L +#define MH_DEBUG_REG28__ARB_QUAL 0x00000800L +#define MH_DEBUG_REG28__CP_EFF1_REQ_MASK 0x00001000L +#define MH_DEBUG_REG28__CP_EFF1_REQ 0x00001000L +#define MH_DEBUG_REG28__VGT_EFF1_REQ_MASK 0x00002000L +#define MH_DEBUG_REG28__VGT_EFF1_REQ 0x00002000L +#define MH_DEBUG_REG28__TC_EFF1_REQ_MASK 0x00004000L +#define MH_DEBUG_REG28__TC_EFF1_REQ 0x00004000L +#define MH_DEBUG_REG28__RB_EFF1_REQ_MASK 0x00008000L +#define MH_DEBUG_REG28__RB_EFF1_REQ 0x00008000L +#define MH_DEBUG_REG28__EFF1_WIN_MASK 0x00010000L +#define MH_DEBUG_REG28__EFF1_WIN 0x00010000L +#define MH_DEBUG_REG28__KILL_EFF1_MASK 0x00020000L +#define MH_DEBUG_REG28__KILL_EFF1 0x00020000L +#define MH_DEBUG_REG28__TCD_NEARFULL_q_MASK 0x00040000L +#define MH_DEBUG_REG28__TCD_NEARFULL_q 0x00040000L +#define MH_DEBUG_REG28__TC_ARB_HOLD_MASK 0x00080000L +#define MH_DEBUG_REG28__TC_ARB_HOLD 0x00080000L +#define MH_DEBUG_REG28__ARB_HOLD_MASK 0x00100000L +#define MH_DEBUG_REG28__ARB_HOLD 0x00100000L +#define MH_DEBUG_REG28__ARB_RTR_q_MASK 0x00200000L +#define MH_DEBUG_REG28__ARB_RTR_q 0x00200000L +#define MH_DEBUG_REG28__SAME_PAGE_LIMIT_COUNT_q_MASK 0xffc00000L + +// MH_DEBUG_REG29 +#define MH_DEBUG_REG29__EFF2_LRU_WINNER_out_MASK 0x00000007L +#define MH_DEBUG_REG29__LEAST_RECENT_INDEX_d_MASK 0x00000038L +#define MH_DEBUG_REG29__LEAST_RECENT_d_MASK 0x000001c0L +#define MH_DEBUG_REG29__UPDATE_RECENT_STACK_d_MASK 0x00000200L +#define MH_DEBUG_REG29__UPDATE_RECENT_STACK_d 0x00000200L +#define MH_DEBUG_REG29__ARB_HOLD_MASK 0x00000400L +#define MH_DEBUG_REG29__ARB_HOLD 0x00000400L +#define MH_DEBUG_REG29__ARB_RTR_q_MASK 0x00000800L +#define MH_DEBUG_REG29__ARB_RTR_q 0x00000800L +#define MH_DEBUG_REG29__CLNT_REQ_MASK 0x0001f000L +#define MH_DEBUG_REG29__RECENT_d_0_MASK 0x000e0000L +#define MH_DEBUG_REG29__RECENT_d_1_MASK 0x00700000L +#define MH_DEBUG_REG29__RECENT_d_2_MASK 0x03800000L +#define MH_DEBUG_REG29__RECENT_d_3_MASK 0x1c000000L +#define MH_DEBUG_REG29__RECENT_d_4_MASK 0xe0000000L + +// MH_DEBUG_REG30 +#define MH_DEBUG_REG30__TC_ARB_HOLD_MASK 0x00000001L +#define MH_DEBUG_REG30__TC_ARB_HOLD 0x00000001L +#define MH_DEBUG_REG30__TC_NOROQ_SAME_ROW_BANK_MASK 0x00000002L +#define MH_DEBUG_REG30__TC_NOROQ_SAME_ROW_BANK 0x00000002L +#define MH_DEBUG_REG30__TC_ROQ_SAME_ROW_BANK_MASK 0x00000004L +#define MH_DEBUG_REG30__TC_ROQ_SAME_ROW_BANK 0x00000004L +#define MH_DEBUG_REG30__TCD_NEARFULL_q_MASK 0x00000008L +#define MH_DEBUG_REG30__TCD_NEARFULL_q 0x00000008L +#define MH_DEBUG_REG30__TCHOLD_IP_q_MASK 0x00000010L +#define MH_DEBUG_REG30__TCHOLD_IP_q 0x00000010L +#define MH_DEBUG_REG30__TCHOLD_CNT_q_MASK 0x000000e0L +#define MH_DEBUG_REG30__MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00000100L +#define MH_DEBUG_REG30__MH_ARBITER_CONFIG_TC_REORDER_ENABLE 0x00000100L +#define MH_DEBUG_REG30__TC_ROQ_RTR_DBG_q_MASK 0x00000200L +#define MH_DEBUG_REG30__TC_ROQ_RTR_DBG_q 0x00000200L +#define MH_DEBUG_REG30__TC_ROQ_SEND_q_MASK 0x00000400L +#define MH_DEBUG_REG30__TC_ROQ_SEND_q 0x00000400L +#define MH_DEBUG_REG30__TC_MH_written_MASK 0x00000800L +#define MH_DEBUG_REG30__TC_MH_written 0x00000800L +#define MH_DEBUG_REG30__TCD_FULLNESS_CNT_q_MASK 0x0007f000L +#define MH_DEBUG_REG30__WBURST_ACTIVE_MASK 0x00080000L +#define MH_DEBUG_REG30__WBURST_ACTIVE 0x00080000L +#define MH_DEBUG_REG30__WLAST_q_MASK 0x00100000L +#define MH_DEBUG_REG30__WLAST_q 0x00100000L +#define MH_DEBUG_REG30__WBURST_IP_q_MASK 0x00200000L +#define MH_DEBUG_REG30__WBURST_IP_q 0x00200000L +#define MH_DEBUG_REG30__WBURST_CNT_q_MASK 0x01c00000L +#define MH_DEBUG_REG30__CP_SEND_QUAL_MASK 0x02000000L +#define MH_DEBUG_REG30__CP_SEND_QUAL 0x02000000L +#define MH_DEBUG_REG30__CP_MH_write_MASK 0x04000000L +#define MH_DEBUG_REG30__CP_MH_write 0x04000000L +#define MH_DEBUG_REG30__RB_SEND_QUAL_MASK 0x08000000L +#define MH_DEBUG_REG30__RB_SEND_QUAL 0x08000000L +#define MH_DEBUG_REG30__PA_SEND_QUAL_MASK 0x10000000L +#define MH_DEBUG_REG30__PA_SEND_QUAL 0x10000000L +#define MH_DEBUG_REG30__ARB_WINNER_MASK 0xe0000000L + +// MH_DEBUG_REG31 +#define MH_DEBUG_REG31__RF_ARBITER_CONFIG_q_MASK 0x03ffffffL +#define MH_DEBUG_REG31__MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x1c000000L + +// MH_DEBUG_REG32 +#define MH_DEBUG_REG32__SAME_ROW_BANK_q_MASK 0x000000ffL +#define MH_DEBUG_REG32__ROQ_MARK_q_MASK 0x0000ff00L +#define MH_DEBUG_REG32__ROQ_VALID_q_MASK 0x00ff0000L +#define MH_DEBUG_REG32__TC_MH_send_MASK 0x01000000L +#define MH_DEBUG_REG32__TC_MH_send 0x01000000L +#define MH_DEBUG_REG32__TC_ROQ_RTR_q_MASK 0x02000000L +#define MH_DEBUG_REG32__TC_ROQ_RTR_q 0x02000000L +#define MH_DEBUG_REG32__KILL_EFF1_MASK 0x04000000L +#define MH_DEBUG_REG32__KILL_EFF1 0x04000000L +#define MH_DEBUG_REG32__TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000L +#define MH_DEBUG_REG32__TC_ROQ_SAME_ROW_BANK_SEL 0x08000000L +#define MH_DEBUG_REG32__ANY_SAME_ROW_BANK_MASK 0x10000000L +#define MH_DEBUG_REG32__ANY_SAME_ROW_BANK 0x10000000L +#define MH_DEBUG_REG32__TC_EFF1_QUAL_MASK 0x20000000L +#define MH_DEBUG_REG32__TC_EFF1_QUAL 0x20000000L +#define MH_DEBUG_REG32__TC_ROQ_EMPTY_MASK 0x40000000L +#define MH_DEBUG_REG32__TC_ROQ_EMPTY 0x40000000L +#define MH_DEBUG_REG32__TC_ROQ_FULL_MASK 0x80000000L +#define MH_DEBUG_REG32__TC_ROQ_FULL 0x80000000L + +// MH_DEBUG_REG33 +#define MH_DEBUG_REG33__SAME_ROW_BANK_q_MASK 0x000000ffL +#define MH_DEBUG_REG33__ROQ_MARK_d_MASK 0x0000ff00L +#define MH_DEBUG_REG33__ROQ_VALID_d_MASK 0x00ff0000L +#define MH_DEBUG_REG33__TC_MH_send_MASK 0x01000000L +#define MH_DEBUG_REG33__TC_MH_send 0x01000000L +#define MH_DEBUG_REG33__TC_ROQ_RTR_q_MASK 0x02000000L +#define MH_DEBUG_REG33__TC_ROQ_RTR_q 0x02000000L +#define MH_DEBUG_REG33__KILL_EFF1_MASK 0x04000000L +#define MH_DEBUG_REG33__KILL_EFF1 0x04000000L +#define MH_DEBUG_REG33__TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000L +#define MH_DEBUG_REG33__TC_ROQ_SAME_ROW_BANK_SEL 0x08000000L +#define MH_DEBUG_REG33__ANY_SAME_ROW_BANK_MASK 0x10000000L +#define MH_DEBUG_REG33__ANY_SAME_ROW_BANK 0x10000000L +#define MH_DEBUG_REG33__TC_EFF1_QUAL_MASK 0x20000000L +#define MH_DEBUG_REG33__TC_EFF1_QUAL 0x20000000L +#define MH_DEBUG_REG33__TC_ROQ_EMPTY_MASK 0x40000000L +#define MH_DEBUG_REG33__TC_ROQ_EMPTY 0x40000000L +#define MH_DEBUG_REG33__TC_ROQ_FULL_MASK 0x80000000L +#define MH_DEBUG_REG33__TC_ROQ_FULL 0x80000000L + +// MH_DEBUG_REG34 +#define MH_DEBUG_REG34__SAME_ROW_BANK_WIN_MASK 0x000000ffL +#define MH_DEBUG_REG34__SAME_ROW_BANK_REQ_MASK 0x0000ff00L +#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_WIN_MASK 0x00ff0000L +#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_REQ_MASK 0xff000000L + +// MH_DEBUG_REG35 +#define MH_DEBUG_REG35__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG35__TC_MH_send 0x00000001L +#define MH_DEBUG_REG35__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG35__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG35__ROQ_MARK_q_0_MASK 0x00000004L +#define MH_DEBUG_REG35__ROQ_MARK_q_0 0x00000004L +#define MH_DEBUG_REG35__ROQ_VALID_q_0_MASK 0x00000008L +#define MH_DEBUG_REG35__ROQ_VALID_q_0 0x00000008L +#define MH_DEBUG_REG35__SAME_ROW_BANK_q_0_MASK 0x00000010L +#define MH_DEBUG_REG35__SAME_ROW_BANK_q_0 0x00000010L +#define MH_DEBUG_REG35__ROQ_ADDR_0_MASK 0xffffffe0L + +// MH_DEBUG_REG36 +#define MH_DEBUG_REG36__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG36__TC_MH_send 0x00000001L +#define MH_DEBUG_REG36__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG36__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG36__ROQ_MARK_q_1_MASK 0x00000004L +#define MH_DEBUG_REG36__ROQ_MARK_q_1 0x00000004L +#define MH_DEBUG_REG36__ROQ_VALID_q_1_MASK 0x00000008L +#define MH_DEBUG_REG36__ROQ_VALID_q_1 0x00000008L +#define MH_DEBUG_REG36__SAME_ROW_BANK_q_1_MASK 0x00000010L +#define MH_DEBUG_REG36__SAME_ROW_BANK_q_1 0x00000010L +#define MH_DEBUG_REG36__ROQ_ADDR_1_MASK 0xffffffe0L + +// MH_DEBUG_REG37 +#define MH_DEBUG_REG37__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG37__TC_MH_send 0x00000001L +#define MH_DEBUG_REG37__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG37__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG37__ROQ_MARK_q_2_MASK 0x00000004L +#define MH_DEBUG_REG37__ROQ_MARK_q_2 0x00000004L +#define MH_DEBUG_REG37__ROQ_VALID_q_2_MASK 0x00000008L +#define MH_DEBUG_REG37__ROQ_VALID_q_2 0x00000008L +#define MH_DEBUG_REG37__SAME_ROW_BANK_q_2_MASK 0x00000010L +#define MH_DEBUG_REG37__SAME_ROW_BANK_q_2 0x00000010L +#define MH_DEBUG_REG37__ROQ_ADDR_2_MASK 0xffffffe0L + +// MH_DEBUG_REG38 +#define MH_DEBUG_REG38__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG38__TC_MH_send 0x00000001L +#define MH_DEBUG_REG38__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG38__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG38__ROQ_MARK_q_3_MASK 0x00000004L +#define MH_DEBUG_REG38__ROQ_MARK_q_3 0x00000004L +#define MH_DEBUG_REG38__ROQ_VALID_q_3_MASK 0x00000008L +#define MH_DEBUG_REG38__ROQ_VALID_q_3 0x00000008L +#define MH_DEBUG_REG38__SAME_ROW_BANK_q_3_MASK 0x00000010L +#define MH_DEBUG_REG38__SAME_ROW_BANK_q_3 0x00000010L +#define MH_DEBUG_REG38__ROQ_ADDR_3_MASK 0xffffffe0L + +// MH_DEBUG_REG39 +#define MH_DEBUG_REG39__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG39__TC_MH_send 0x00000001L +#define MH_DEBUG_REG39__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG39__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG39__ROQ_MARK_q_4_MASK 0x00000004L +#define MH_DEBUG_REG39__ROQ_MARK_q_4 0x00000004L +#define MH_DEBUG_REG39__ROQ_VALID_q_4_MASK 0x00000008L +#define MH_DEBUG_REG39__ROQ_VALID_q_4 0x00000008L +#define MH_DEBUG_REG39__SAME_ROW_BANK_q_4_MASK 0x00000010L +#define MH_DEBUG_REG39__SAME_ROW_BANK_q_4 0x00000010L +#define MH_DEBUG_REG39__ROQ_ADDR_4_MASK 0xffffffe0L + +// MH_DEBUG_REG40 +#define MH_DEBUG_REG40__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG40__TC_MH_send 0x00000001L +#define MH_DEBUG_REG40__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG40__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG40__ROQ_MARK_q_5_MASK 0x00000004L +#define MH_DEBUG_REG40__ROQ_MARK_q_5 0x00000004L +#define MH_DEBUG_REG40__ROQ_VALID_q_5_MASK 0x00000008L +#define MH_DEBUG_REG40__ROQ_VALID_q_5 0x00000008L +#define MH_DEBUG_REG40__SAME_ROW_BANK_q_5_MASK 0x00000010L +#define MH_DEBUG_REG40__SAME_ROW_BANK_q_5 0x00000010L +#define MH_DEBUG_REG40__ROQ_ADDR_5_MASK 0xffffffe0L + +// MH_DEBUG_REG41 +#define MH_DEBUG_REG41__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG41__TC_MH_send 0x00000001L +#define MH_DEBUG_REG41__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG41__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG41__ROQ_MARK_q_6_MASK 0x00000004L +#define MH_DEBUG_REG41__ROQ_MARK_q_6 0x00000004L +#define MH_DEBUG_REG41__ROQ_VALID_q_6_MASK 0x00000008L +#define MH_DEBUG_REG41__ROQ_VALID_q_6 0x00000008L +#define MH_DEBUG_REG41__SAME_ROW_BANK_q_6_MASK 0x00000010L +#define MH_DEBUG_REG41__SAME_ROW_BANK_q_6 0x00000010L +#define MH_DEBUG_REG41__ROQ_ADDR_6_MASK 0xffffffe0L + +// MH_DEBUG_REG42 +#define MH_DEBUG_REG42__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG42__TC_MH_send 0x00000001L +#define MH_DEBUG_REG42__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG42__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG42__ROQ_MARK_q_7_MASK 0x00000004L +#define MH_DEBUG_REG42__ROQ_MARK_q_7 0x00000004L +#define MH_DEBUG_REG42__ROQ_VALID_q_7_MASK 0x00000008L +#define MH_DEBUG_REG42__ROQ_VALID_q_7 0x00000008L +#define MH_DEBUG_REG42__SAME_ROW_BANK_q_7_MASK 0x00000010L +#define MH_DEBUG_REG42__SAME_ROW_BANK_q_7 0x00000010L +#define MH_DEBUG_REG42__ROQ_ADDR_7_MASK 0xffffffe0L + +// MH_DEBUG_REG43 +#define MH_DEBUG_REG43__ARB_REG_WE_q_MASK 0x00000001L +#define MH_DEBUG_REG43__ARB_REG_WE_q 0x00000001L +#define MH_DEBUG_REG43__ARB_WE_MASK 0x00000002L +#define MH_DEBUG_REG43__ARB_WE 0x00000002L +#define MH_DEBUG_REG43__ARB_REG_VALID_q_MASK 0x00000004L +#define MH_DEBUG_REG43__ARB_REG_VALID_q 0x00000004L +#define MH_DEBUG_REG43__ARB_RTR_q_MASK 0x00000008L +#define MH_DEBUG_REG43__ARB_RTR_q 0x00000008L +#define MH_DEBUG_REG43__ARB_REG_RTR_MASK 0x00000010L +#define MH_DEBUG_REG43__ARB_REG_RTR 0x00000010L +#define MH_DEBUG_REG43__WDAT_BURST_RTR_MASK 0x00000020L +#define MH_DEBUG_REG43__WDAT_BURST_RTR 0x00000020L +#define MH_DEBUG_REG43__MMU_RTR_MASK 0x00000040L +#define MH_DEBUG_REG43__MMU_RTR 0x00000040L +#define MH_DEBUG_REG43__ARB_ID_q_MASK 0x00000380L +#define MH_DEBUG_REG43__ARB_WRITE_q_MASK 0x00000400L +#define MH_DEBUG_REG43__ARB_WRITE_q 0x00000400L +#define MH_DEBUG_REG43__ARB_BLEN_q_MASK 0x00000800L +#define MH_DEBUG_REG43__ARB_BLEN_q 0x00000800L +#define MH_DEBUG_REG43__ARQ_CTRL_EMPTY_MASK 0x00001000L +#define MH_DEBUG_REG43__ARQ_CTRL_EMPTY 0x00001000L +#define MH_DEBUG_REG43__ARQ_FIFO_CNT_q_MASK 0x0000e000L +#define MH_DEBUG_REG43__MMU_WE_MASK 0x00010000L +#define MH_DEBUG_REG43__MMU_WE 0x00010000L +#define MH_DEBUG_REG43__ARQ_RTR_MASK 0x00020000L +#define MH_DEBUG_REG43__ARQ_RTR 0x00020000L +#define MH_DEBUG_REG43__MMU_ID_MASK 0x001c0000L +#define MH_DEBUG_REG43__MMU_WRITE_MASK 0x00200000L +#define MH_DEBUG_REG43__MMU_WRITE 0x00200000L +#define MH_DEBUG_REG43__MMU_BLEN_MASK 0x00400000L +#define MH_DEBUG_REG43__MMU_BLEN 0x00400000L +#define MH_DEBUG_REG43__WBURST_IP_q_MASK 0x00800000L +#define MH_DEBUG_REG43__WBURST_IP_q 0x00800000L +#define MH_DEBUG_REG43__WDAT_REG_WE_q_MASK 0x01000000L +#define MH_DEBUG_REG43__WDAT_REG_WE_q 0x01000000L +#define MH_DEBUG_REG43__WDB_WE_MASK 0x02000000L +#define MH_DEBUG_REG43__WDB_WE 0x02000000L +#define MH_DEBUG_REG43__WDB_RTR_SKID_4_MASK 0x04000000L +#define MH_DEBUG_REG43__WDB_RTR_SKID_4 0x04000000L +#define MH_DEBUG_REG43__WDB_RTR_SKID_3_MASK 0x08000000L +#define MH_DEBUG_REG43__WDB_RTR_SKID_3 0x08000000L + +// MH_DEBUG_REG44 +#define MH_DEBUG_REG44__ARB_WE_MASK 0x00000001L +#define MH_DEBUG_REG44__ARB_WE 0x00000001L +#define MH_DEBUG_REG44__ARB_ID_q_MASK 0x0000000eL +#define MH_DEBUG_REG44__ARB_VAD_q_MASK 0xfffffff0L + +// MH_DEBUG_REG45 +#define MH_DEBUG_REG45__MMU_WE_MASK 0x00000001L +#define MH_DEBUG_REG45__MMU_WE 0x00000001L +#define MH_DEBUG_REG45__MMU_ID_MASK 0x0000000eL +#define MH_DEBUG_REG45__MMU_PAD_MASK 0xfffffff0L + +// MH_DEBUG_REG46 +#define MH_DEBUG_REG46__WDAT_REG_WE_q_MASK 0x00000001L +#define MH_DEBUG_REG46__WDAT_REG_WE_q 0x00000001L +#define MH_DEBUG_REG46__WDB_WE_MASK 0x00000002L +#define MH_DEBUG_REG46__WDB_WE 0x00000002L +#define MH_DEBUG_REG46__WDAT_REG_VALID_q_MASK 0x00000004L +#define MH_DEBUG_REG46__WDAT_REG_VALID_q 0x00000004L +#define MH_DEBUG_REG46__WDB_RTR_SKID_4_MASK 0x00000008L +#define MH_DEBUG_REG46__WDB_RTR_SKID_4 0x00000008L +#define MH_DEBUG_REG46__ARB_WSTRB_q_MASK 0x00000ff0L +#define MH_DEBUG_REG46__ARB_WLAST_MASK 0x00001000L +#define MH_DEBUG_REG46__ARB_WLAST 0x00001000L +#define MH_DEBUG_REG46__WDB_CTRL_EMPTY_MASK 0x00002000L +#define MH_DEBUG_REG46__WDB_CTRL_EMPTY 0x00002000L +#define MH_DEBUG_REG46__WDB_FIFO_CNT_q_MASK 0x0007c000L +#define MH_DEBUG_REG46__WDC_WDB_RE_q_MASK 0x00080000L +#define MH_DEBUG_REG46__WDC_WDB_RE_q 0x00080000L +#define MH_DEBUG_REG46__WDB_WDC_WID_MASK 0x00700000L +#define MH_DEBUG_REG46__WDB_WDC_WLAST_MASK 0x00800000L +#define MH_DEBUG_REG46__WDB_WDC_WLAST 0x00800000L +#define MH_DEBUG_REG46__WDB_WDC_WSTRB_MASK 0xff000000L + +// MH_DEBUG_REG47 +#define MH_DEBUG_REG47__WDB_WDC_WDATA_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG48 +#define MH_DEBUG_REG48__WDB_WDC_WDATA_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG49 +#define MH_DEBUG_REG49__CTRL_ARC_EMPTY_MASK 0x00000001L +#define MH_DEBUG_REG49__CTRL_ARC_EMPTY 0x00000001L +#define MH_DEBUG_REG49__CTRL_RARC_EMPTY_MASK 0x00000002L +#define MH_DEBUG_REG49__CTRL_RARC_EMPTY 0x00000002L +#define MH_DEBUG_REG49__ARQ_CTRL_EMPTY_MASK 0x00000004L +#define MH_DEBUG_REG49__ARQ_CTRL_EMPTY 0x00000004L +#define MH_DEBUG_REG49__ARQ_CTRL_WRITE_MASK 0x00000008L +#define MH_DEBUG_REG49__ARQ_CTRL_WRITE 0x00000008L +#define MH_DEBUG_REG49__TLBMISS_CTRL_RTS_MASK 0x00000010L +#define MH_DEBUG_REG49__TLBMISS_CTRL_RTS 0x00000010L +#define MH_DEBUG_REG49__CTRL_TLBMISS_RE_q_MASK 0x00000020L +#define MH_DEBUG_REG49__CTRL_TLBMISS_RE_q 0x00000020L +#define MH_DEBUG_REG49__INFLT_LIMIT_q_MASK 0x00000040L +#define MH_DEBUG_REG49__INFLT_LIMIT_q 0x00000040L +#define MH_DEBUG_REG49__INFLT_LIMIT_CNT_q_MASK 0x00001f80L +#define MH_DEBUG_REG49__ARC_CTRL_RE_q_MASK 0x00002000L +#define MH_DEBUG_REG49__ARC_CTRL_RE_q 0x00002000L +#define MH_DEBUG_REG49__RARC_CTRL_RE_q_MASK 0x00004000L +#define MH_DEBUG_REG49__RARC_CTRL_RE_q 0x00004000L +#define MH_DEBUG_REG49__RVALID_q_MASK 0x00008000L +#define MH_DEBUG_REG49__RVALID_q 0x00008000L +#define MH_DEBUG_REG49__RREADY_q_MASK 0x00010000L +#define MH_DEBUG_REG49__RREADY_q 0x00010000L +#define MH_DEBUG_REG49__RLAST_q_MASK 0x00020000L +#define MH_DEBUG_REG49__RLAST_q 0x00020000L +#define MH_DEBUG_REG49__BVALID_q_MASK 0x00040000L +#define MH_DEBUG_REG49__BVALID_q 0x00040000L +#define MH_DEBUG_REG49__BREADY_q_MASK 0x00080000L +#define MH_DEBUG_REG49__BREADY_q 0x00080000L + +// MH_DEBUG_REG50 +#define MH_DEBUG_REG50__MH_CP_grb_send_MASK 0x00000001L +#define MH_DEBUG_REG50__MH_CP_grb_send 0x00000001L +#define MH_DEBUG_REG50__MH_VGT_grb_send_MASK 0x00000002L +#define MH_DEBUG_REG50__MH_VGT_grb_send 0x00000002L +#define MH_DEBUG_REG50__MH_TC_mcsend_MASK 0x00000004L +#define MH_DEBUG_REG50__MH_TC_mcsend 0x00000004L +#define MH_DEBUG_REG50__MH_TLBMISS_SEND_MASK 0x00000008L +#define MH_DEBUG_REG50__MH_TLBMISS_SEND 0x00000008L +#define MH_DEBUG_REG50__TLBMISS_VALID_MASK 0x00000010L +#define MH_DEBUG_REG50__TLBMISS_VALID 0x00000010L +#define MH_DEBUG_REG50__RDC_VALID_MASK 0x00000020L +#define MH_DEBUG_REG50__RDC_VALID 0x00000020L +#define MH_DEBUG_REG50__RDC_RID_MASK 0x000001c0L +#define MH_DEBUG_REG50__RDC_RLAST_MASK 0x00000200L +#define MH_DEBUG_REG50__RDC_RLAST 0x00000200L +#define MH_DEBUG_REG50__RDC_RRESP_MASK 0x00000c00L +#define MH_DEBUG_REG50__TLBMISS_CTRL_RTS_MASK 0x00001000L +#define MH_DEBUG_REG50__TLBMISS_CTRL_RTS 0x00001000L +#define MH_DEBUG_REG50__CTRL_TLBMISS_RE_q_MASK 0x00002000L +#define MH_DEBUG_REG50__CTRL_TLBMISS_RE_q 0x00002000L +#define MH_DEBUG_REG50__MMU_ID_REQUEST_q_MASK 0x00004000L +#define MH_DEBUG_REG50__MMU_ID_REQUEST_q 0x00004000L +#define MH_DEBUG_REG50__OUTSTANDING_MMUID_CNT_q_MASK 0x001f8000L +#define MH_DEBUG_REG50__MMU_ID_RESPONSE_MASK 0x00200000L +#define MH_DEBUG_REG50__MMU_ID_RESPONSE 0x00200000L +#define MH_DEBUG_REG50__TLBMISS_RETURN_CNT_q_MASK 0x0fc00000L +#define MH_DEBUG_REG50__CNT_HOLD_q1_MASK 0x10000000L +#define MH_DEBUG_REG50__CNT_HOLD_q1 0x10000000L +#define MH_DEBUG_REG50__MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0xe0000000L + +// MH_DEBUG_REG51 +#define MH_DEBUG_REG51__RF_MMU_PAGE_FAULT_MASK 0xffffffffL + +// MH_DEBUG_REG52 +#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_1_to_0_MASK 0x00000003L +#define MH_DEBUG_REG52__ARB_WE_MASK 0x00000004L +#define MH_DEBUG_REG52__ARB_WE 0x00000004L +#define MH_DEBUG_REG52__MMU_RTR_MASK 0x00000008L +#define MH_DEBUG_REG52__MMU_RTR 0x00000008L +#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_25_to_4_MASK 0x03fffff0L +#define MH_DEBUG_REG52__ARB_ID_q_MASK 0x1c000000L +#define MH_DEBUG_REG52__ARB_WRITE_q_MASK 0x20000000L +#define MH_DEBUG_REG52__ARB_WRITE_q 0x20000000L +#define MH_DEBUG_REG52__client_behavior_q_MASK 0xc0000000L + +// MH_DEBUG_REG53 +#define MH_DEBUG_REG53__stage1_valid_MASK 0x00000001L +#define MH_DEBUG_REG53__stage1_valid 0x00000001L +#define MH_DEBUG_REG53__IGNORE_TAG_MISS_q_MASK 0x00000002L +#define MH_DEBUG_REG53__IGNORE_TAG_MISS_q 0x00000002L +#define MH_DEBUG_REG53__pa_in_mpu_range_MASK 0x00000004L +#define MH_DEBUG_REG53__pa_in_mpu_range 0x00000004L +#define MH_DEBUG_REG53__tag_match_q_MASK 0x00000008L +#define MH_DEBUG_REG53__tag_match_q 0x00000008L +#define MH_DEBUG_REG53__tag_miss_q_MASK 0x00000010L +#define MH_DEBUG_REG53__tag_miss_q 0x00000010L +#define MH_DEBUG_REG53__va_in_range_q_MASK 0x00000020L +#define MH_DEBUG_REG53__va_in_range_q 0x00000020L +#define MH_DEBUG_REG53__MMU_MISS_MASK 0x00000040L +#define MH_DEBUG_REG53__MMU_MISS 0x00000040L +#define MH_DEBUG_REG53__MMU_READ_MISS_MASK 0x00000080L +#define MH_DEBUG_REG53__MMU_READ_MISS 0x00000080L +#define MH_DEBUG_REG53__MMU_WRITE_MISS_MASK 0x00000100L +#define MH_DEBUG_REG53__MMU_WRITE_MISS 0x00000100L +#define MH_DEBUG_REG53__MMU_HIT_MASK 0x00000200L +#define MH_DEBUG_REG53__MMU_HIT 0x00000200L +#define MH_DEBUG_REG53__MMU_READ_HIT_MASK 0x00000400L +#define MH_DEBUG_REG53__MMU_READ_HIT 0x00000400L +#define MH_DEBUG_REG53__MMU_WRITE_HIT_MASK 0x00000800L +#define MH_DEBUG_REG53__MMU_WRITE_HIT 0x00000800L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_MISS_MASK 0x00001000L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_MISS 0x00001000L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_HIT_MASK 0x00002000L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_HIT 0x00002000L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_MISS_MASK 0x00004000L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_MISS 0x00004000L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_HIT_MASK 0x00008000L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_HIT 0x00008000L +#define MH_DEBUG_REG53__REQ_VA_OFFSET_q_MASK 0xffff0000L + +// MH_DEBUG_REG54 +#define MH_DEBUG_REG54__ARQ_RTR_MASK 0x00000001L +#define MH_DEBUG_REG54__ARQ_RTR 0x00000001L +#define MH_DEBUG_REG54__MMU_WE_MASK 0x00000002L +#define MH_DEBUG_REG54__MMU_WE 0x00000002L +#define MH_DEBUG_REG54__CTRL_TLBMISS_RE_q_MASK 0x00000004L +#define MH_DEBUG_REG54__CTRL_TLBMISS_RE_q 0x00000004L +#define MH_DEBUG_REG54__TLBMISS_CTRL_RTS_MASK 0x00000008L +#define MH_DEBUG_REG54__TLBMISS_CTRL_RTS 0x00000008L +#define MH_DEBUG_REG54__MH_TLBMISS_SEND_MASK 0x00000010L +#define MH_DEBUG_REG54__MH_TLBMISS_SEND 0x00000010L +#define MH_DEBUG_REG54__MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK 0x00000020L +#define MH_DEBUG_REG54__MMU_STALL_AWAITING_TLB_MISS_FETCH 0x00000020L +#define MH_DEBUG_REG54__pa_in_mpu_range_MASK 0x00000040L +#define MH_DEBUG_REG54__pa_in_mpu_range 0x00000040L +#define MH_DEBUG_REG54__stage1_valid_MASK 0x00000080L +#define MH_DEBUG_REG54__stage1_valid 0x00000080L +#define MH_DEBUG_REG54__stage2_valid_MASK 0x00000100L +#define MH_DEBUG_REG54__stage2_valid 0x00000100L +#define MH_DEBUG_REG54__client_behavior_q_MASK 0x00000600L +#define MH_DEBUG_REG54__IGNORE_TAG_MISS_q_MASK 0x00000800L +#define MH_DEBUG_REG54__IGNORE_TAG_MISS_q 0x00000800L +#define MH_DEBUG_REG54__tag_match_q_MASK 0x00001000L +#define MH_DEBUG_REG54__tag_match_q 0x00001000L +#define MH_DEBUG_REG54__tag_miss_q_MASK 0x00002000L +#define MH_DEBUG_REG54__tag_miss_q 0x00002000L +#define MH_DEBUG_REG54__va_in_range_q_MASK 0x00004000L +#define MH_DEBUG_REG54__va_in_range_q 0x00004000L +#define MH_DEBUG_REG54__PTE_FETCH_COMPLETE_q_MASK 0x00008000L +#define MH_DEBUG_REG54__PTE_FETCH_COMPLETE_q 0x00008000L +#define MH_DEBUG_REG54__TAG_valid_q_MASK 0xffff0000L + +// MH_DEBUG_REG55 +#define MH_DEBUG_REG55__TAG0_VA_MASK 0x00001fffL +#define MH_DEBUG_REG55__TAG_valid_q_0_MASK 0x00002000L +#define MH_DEBUG_REG55__TAG_valid_q_0 0x00002000L +#define MH_DEBUG_REG55__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG55__TAG1_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG55__TAG_valid_q_1_MASK 0x20000000L +#define MH_DEBUG_REG55__TAG_valid_q_1 0x20000000L + +// MH_DEBUG_REG56 +#define MH_DEBUG_REG56__TAG2_VA_MASK 0x00001fffL +#define MH_DEBUG_REG56__TAG_valid_q_2_MASK 0x00002000L +#define MH_DEBUG_REG56__TAG_valid_q_2 0x00002000L +#define MH_DEBUG_REG56__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG56__TAG3_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG56__TAG_valid_q_3_MASK 0x20000000L +#define MH_DEBUG_REG56__TAG_valid_q_3 0x20000000L + +// MH_DEBUG_REG57 +#define MH_DEBUG_REG57__TAG4_VA_MASK 0x00001fffL +#define MH_DEBUG_REG57__TAG_valid_q_4_MASK 0x00002000L +#define MH_DEBUG_REG57__TAG_valid_q_4 0x00002000L +#define MH_DEBUG_REG57__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG57__TAG5_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG57__TAG_valid_q_5_MASK 0x20000000L +#define MH_DEBUG_REG57__TAG_valid_q_5 0x20000000L + +// MH_DEBUG_REG58 +#define MH_DEBUG_REG58__TAG6_VA_MASK 0x00001fffL +#define MH_DEBUG_REG58__TAG_valid_q_6_MASK 0x00002000L +#define MH_DEBUG_REG58__TAG_valid_q_6 0x00002000L +#define MH_DEBUG_REG58__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG58__TAG7_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG58__TAG_valid_q_7_MASK 0x20000000L +#define MH_DEBUG_REG58__TAG_valid_q_7 0x20000000L + +// MH_DEBUG_REG59 +#define MH_DEBUG_REG59__TAG8_VA_MASK 0x00001fffL +#define MH_DEBUG_REG59__TAG_valid_q_8_MASK 0x00002000L +#define MH_DEBUG_REG59__TAG_valid_q_8 0x00002000L +#define MH_DEBUG_REG59__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG59__TAG9_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG59__TAG_valid_q_9_MASK 0x20000000L +#define MH_DEBUG_REG59__TAG_valid_q_9 0x20000000L + +// MH_DEBUG_REG60 +#define MH_DEBUG_REG60__TAG10_VA_MASK 0x00001fffL +#define MH_DEBUG_REG60__TAG_valid_q_10_MASK 0x00002000L +#define MH_DEBUG_REG60__TAG_valid_q_10 0x00002000L +#define MH_DEBUG_REG60__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG60__TAG11_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG60__TAG_valid_q_11_MASK 0x20000000L +#define MH_DEBUG_REG60__TAG_valid_q_11 0x20000000L + +// MH_DEBUG_REG61 +#define MH_DEBUG_REG61__TAG12_VA_MASK 0x00001fffL +#define MH_DEBUG_REG61__TAG_valid_q_12_MASK 0x00002000L +#define MH_DEBUG_REG61__TAG_valid_q_12 0x00002000L +#define MH_DEBUG_REG61__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG61__TAG13_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG61__TAG_valid_q_13_MASK 0x20000000L +#define MH_DEBUG_REG61__TAG_valid_q_13 0x20000000L + +// MH_DEBUG_REG62 +#define MH_DEBUG_REG62__TAG14_VA_MASK 0x00001fffL +#define MH_DEBUG_REG62__TAG_valid_q_14_MASK 0x00002000L +#define MH_DEBUG_REG62__TAG_valid_q_14 0x00002000L +#define MH_DEBUG_REG62__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG62__TAG15_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG62__TAG_valid_q_15_MASK 0x20000000L +#define MH_DEBUG_REG62__TAG_valid_q_15 0x20000000L + +// MH_DEBUG_REG63 +#define MH_DEBUG_REG63__MH_DBG_DEFAULT_MASK 0xffffffffL + +// MH_MMU_CONFIG +#define MH_MMU_CONFIG__MMU_ENABLE_MASK 0x00000001L +#define MH_MMU_CONFIG__MMU_ENABLE 0x00000001L +#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE_MASK 0x00000002L +#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE 0x00000002L +#define MH_MMU_CONFIG__RESERVED1_MASK 0x0000000cL +#define MH_MMU_CONFIG__RB_W_CLNT_BEHAVIOR_MASK 0x00000030L +#define MH_MMU_CONFIG__CP_W_CLNT_BEHAVIOR_MASK 0x000000c0L +#define MH_MMU_CONFIG__CP_R0_CLNT_BEHAVIOR_MASK 0x00000300L +#define MH_MMU_CONFIG__CP_R1_CLNT_BEHAVIOR_MASK 0x00000c00L +#define MH_MMU_CONFIG__CP_R2_CLNT_BEHAVIOR_MASK 0x00003000L +#define MH_MMU_CONFIG__CP_R3_CLNT_BEHAVIOR_MASK 0x0000c000L +#define MH_MMU_CONFIG__CP_R4_CLNT_BEHAVIOR_MASK 0x00030000L +#define MH_MMU_CONFIG__VGT_R0_CLNT_BEHAVIOR_MASK 0x000c0000L +#define MH_MMU_CONFIG__VGT_R1_CLNT_BEHAVIOR_MASK 0x00300000L +#define MH_MMU_CONFIG__TC_R_CLNT_BEHAVIOR_MASK 0x00c00000L +#define MH_MMU_CONFIG__PA_W_CLNT_BEHAVIOR_MASK 0x03000000L + +// MH_MMU_VA_RANGE +#define MH_MMU_VA_RANGE__NUM_64KB_REGIONS_MASK 0x00000fffL +#define MH_MMU_VA_RANGE__VA_BASE_MASK 0xfffff000L + +// MH_MMU_PT_BASE +#define MH_MMU_PT_BASE__PT_BASE_MASK 0xfffff000L + +// MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT__PAGE_FAULT_MASK 0x00000001L +#define MH_MMU_PAGE_FAULT__PAGE_FAULT 0x00000001L +#define MH_MMU_PAGE_FAULT__OP_TYPE_MASK 0x00000002L +#define MH_MMU_PAGE_FAULT__OP_TYPE 0x00000002L +#define MH_MMU_PAGE_FAULT__CLNT_BEHAVIOR_MASK 0x0000000cL +#define MH_MMU_PAGE_FAULT__AXI_ID_MASK 0x00000070L +#define MH_MMU_PAGE_FAULT__RESERVED1_MASK 0x00000080L +#define MH_MMU_PAGE_FAULT__RESERVED1 0x00000080L +#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE_MASK 0x00000100L +#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE 0x00000100L +#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE_MASK 0x00000200L +#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE 0x00000200L +#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR_MASK 0x00000400L +#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR 0x00000400L +#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR_MASK 0x00000800L +#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR 0x00000800L +#define MH_MMU_PAGE_FAULT__REQ_VA_MASK 0xfffff000L + +// MH_MMU_TRAN_ERROR +#define MH_MMU_TRAN_ERROR__TRAN_ERROR_MASK 0xffffffe0L + +// MH_MMU_INVALIDATE +#define MH_MMU_INVALIDATE__INVALIDATE_ALL_MASK 0x00000001L +#define MH_MMU_INVALIDATE__INVALIDATE_ALL 0x00000001L +#define MH_MMU_INVALIDATE__INVALIDATE_TC_MASK 0x00000002L +#define MH_MMU_INVALIDATE__INVALIDATE_TC 0x00000002L + +// MH_MMU_MPU_BASE +#define MH_MMU_MPU_BASE__MPU_BASE_MASK 0xfffff000L + +// MH_MMU_MPU_END +#define MH_MMU_MPU_END__MPU_END_MASK 0xfffff000L + +// WAIT_UNTIL +#define WAIT_UNTIL__WAIT_RE_VSYNC_MASK 0x00000002L +#define WAIT_UNTIL__WAIT_RE_VSYNC 0x00000002L +#define WAIT_UNTIL__WAIT_FE_VSYNC_MASK 0x00000004L +#define WAIT_UNTIL__WAIT_FE_VSYNC 0x00000004L +#define WAIT_UNTIL__WAIT_VSYNC_MASK 0x00000008L +#define WAIT_UNTIL__WAIT_VSYNC 0x00000008L +#define WAIT_UNTIL__WAIT_DSPLY_ID0_MASK 0x00000010L +#define WAIT_UNTIL__WAIT_DSPLY_ID0 0x00000010L +#define WAIT_UNTIL__WAIT_DSPLY_ID1_MASK 0x00000020L +#define WAIT_UNTIL__WAIT_DSPLY_ID1 0x00000020L +#define WAIT_UNTIL__WAIT_DSPLY_ID2_MASK 0x00000040L +#define WAIT_UNTIL__WAIT_DSPLY_ID2 0x00000040L +#define WAIT_UNTIL__WAIT_CMDFIFO_MASK 0x00000400L +#define WAIT_UNTIL__WAIT_CMDFIFO 0x00000400L +#define WAIT_UNTIL__WAIT_2D_IDLE_MASK 0x00004000L +#define WAIT_UNTIL__WAIT_2D_IDLE 0x00004000L +#define WAIT_UNTIL__WAIT_3D_IDLE_MASK 0x00008000L +#define WAIT_UNTIL__WAIT_3D_IDLE 0x00008000L +#define WAIT_UNTIL__WAIT_2D_IDLECLEAN_MASK 0x00010000L +#define WAIT_UNTIL__WAIT_2D_IDLECLEAN 0x00010000L +#define WAIT_UNTIL__WAIT_3D_IDLECLEAN_MASK 0x00020000L +#define WAIT_UNTIL__WAIT_3D_IDLECLEAN 0x00020000L +#define WAIT_UNTIL__CMDFIFO_ENTRIES_MASK 0x00f00000L + +// RBBM_ISYNC_CNTL +#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI_MASK 0x00000010L +#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI 0x00000010L +#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI_MASK 0x00000020L +#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI 0x00000020L + +// RBBM_STATUS +#define RBBM_STATUS__CMDFIFO_AVAIL_MASK 0x0000001fL +#define RBBM_STATUS__TC_BUSY_MASK 0x00000020L +#define RBBM_STATUS__TC_BUSY 0x00000020L +#define RBBM_STATUS__HIRQ_PENDING_MASK 0x00000100L +#define RBBM_STATUS__HIRQ_PENDING 0x00000100L +#define RBBM_STATUS__CPRQ_PENDING_MASK 0x00000200L +#define RBBM_STATUS__CPRQ_PENDING 0x00000200L +#define RBBM_STATUS__CFRQ_PENDING_MASK 0x00000400L +#define RBBM_STATUS__CFRQ_PENDING 0x00000400L +#define RBBM_STATUS__PFRQ_PENDING_MASK 0x00000800L +#define RBBM_STATUS__PFRQ_PENDING 0x00000800L +#define RBBM_STATUS__VGT_BUSY_NO_DMA_MASK 0x00001000L +#define RBBM_STATUS__VGT_BUSY_NO_DMA 0x00001000L +#define RBBM_STATUS__RBBM_WU_BUSY_MASK 0x00004000L +#define RBBM_STATUS__RBBM_WU_BUSY 0x00004000L +#define RBBM_STATUS__CP_NRT_BUSY_MASK 0x00010000L +#define RBBM_STATUS__CP_NRT_BUSY 0x00010000L +#define RBBM_STATUS__MH_BUSY_MASK 0x00040000L +#define RBBM_STATUS__MH_BUSY 0x00040000L +#define RBBM_STATUS__MH_COHERENCY_BUSY_MASK 0x00080000L +#define RBBM_STATUS__MH_COHERENCY_BUSY 0x00080000L +#define RBBM_STATUS__SX_BUSY_MASK 0x00200000L +#define RBBM_STATUS__SX_BUSY 0x00200000L +#define RBBM_STATUS__TPC_BUSY_MASK 0x00400000L +#define RBBM_STATUS__TPC_BUSY 0x00400000L +#define RBBM_STATUS__SC_CNTX_BUSY_MASK 0x01000000L +#define RBBM_STATUS__SC_CNTX_BUSY 0x01000000L +#define RBBM_STATUS__PA_BUSY_MASK 0x02000000L +#define RBBM_STATUS__PA_BUSY 0x02000000L +#define RBBM_STATUS__VGT_BUSY_MASK 0x04000000L +#define RBBM_STATUS__VGT_BUSY 0x04000000L +#define RBBM_STATUS__SQ_CNTX17_BUSY_MASK 0x08000000L +#define RBBM_STATUS__SQ_CNTX17_BUSY 0x08000000L +#define RBBM_STATUS__SQ_CNTX0_BUSY_MASK 0x10000000L +#define RBBM_STATUS__SQ_CNTX0_BUSY 0x10000000L +#define RBBM_STATUS__RB_CNTX_BUSY_MASK 0x40000000L +#define RBBM_STATUS__RB_CNTX_BUSY 0x40000000L +#define RBBM_STATUS__GUI_ACTIVE_MASK 0x80000000L +#define RBBM_STATUS__GUI_ACTIVE 0x80000000L + +// RBBM_DSPLY +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID0_MASK 0x00000001L +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID0 0x00000001L +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID1_MASK 0x00000002L +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID1 0x00000002L +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID2_MASK 0x00000004L +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID2 0x00000004L +#define RBBM_DSPLY__SEL_DMI_VSYNC_VALID_MASK 0x00000008L +#define RBBM_DSPLY__SEL_DMI_VSYNC_VALID 0x00000008L +#define RBBM_DSPLY__DMI_CH1_USE_BUFID0_MASK 0x00000010L +#define RBBM_DSPLY__DMI_CH1_USE_BUFID0 0x00000010L +#define RBBM_DSPLY__DMI_CH1_USE_BUFID1_MASK 0x00000020L +#define RBBM_DSPLY__DMI_CH1_USE_BUFID1 0x00000020L +#define RBBM_DSPLY__DMI_CH1_USE_BUFID2_MASK 0x00000040L +#define RBBM_DSPLY__DMI_CH1_USE_BUFID2 0x00000040L +#define RBBM_DSPLY__DMI_CH1_SW_CNTL_MASK 0x00000080L +#define RBBM_DSPLY__DMI_CH1_SW_CNTL 0x00000080L +#define RBBM_DSPLY__DMI_CH1_NUM_BUFS_MASK 0x00000300L +#define RBBM_DSPLY__DMI_CH2_USE_BUFID0_MASK 0x00000400L +#define RBBM_DSPLY__DMI_CH2_USE_BUFID0 0x00000400L +#define RBBM_DSPLY__DMI_CH2_USE_BUFID1_MASK 0x00000800L +#define RBBM_DSPLY__DMI_CH2_USE_BUFID1 0x00000800L +#define RBBM_DSPLY__DMI_CH2_USE_BUFID2_MASK 0x00001000L +#define RBBM_DSPLY__DMI_CH2_USE_BUFID2 0x00001000L +#define RBBM_DSPLY__DMI_CH2_SW_CNTL_MASK 0x00002000L +#define RBBM_DSPLY__DMI_CH2_SW_CNTL 0x00002000L +#define RBBM_DSPLY__DMI_CH2_NUM_BUFS_MASK 0x0000c000L +#define RBBM_DSPLY__DMI_CHANNEL_SELECT_MASK 0x00030000L +#define RBBM_DSPLY__DMI_CH3_USE_BUFID0_MASK 0x00100000L +#define RBBM_DSPLY__DMI_CH3_USE_BUFID0 0x00100000L +#define RBBM_DSPLY__DMI_CH3_USE_BUFID1_MASK 0x00200000L +#define RBBM_DSPLY__DMI_CH3_USE_BUFID1 0x00200000L +#define RBBM_DSPLY__DMI_CH3_USE_BUFID2_MASK 0x00400000L +#define RBBM_DSPLY__DMI_CH3_USE_BUFID2 0x00400000L +#define RBBM_DSPLY__DMI_CH3_SW_CNTL_MASK 0x00800000L +#define RBBM_DSPLY__DMI_CH3_SW_CNTL 0x00800000L +#define RBBM_DSPLY__DMI_CH3_NUM_BUFS_MASK 0x03000000L +#define RBBM_DSPLY__DMI_CH4_USE_BUFID0_MASK 0x04000000L +#define RBBM_DSPLY__DMI_CH4_USE_BUFID0 0x04000000L +#define RBBM_DSPLY__DMI_CH4_USE_BUFID1_MASK 0x08000000L +#define RBBM_DSPLY__DMI_CH4_USE_BUFID1 0x08000000L +#define RBBM_DSPLY__DMI_CH4_USE_BUFID2_MASK 0x10000000L +#define RBBM_DSPLY__DMI_CH4_USE_BUFID2 0x10000000L +#define RBBM_DSPLY__DMI_CH4_SW_CNTL_MASK 0x20000000L +#define RBBM_DSPLY__DMI_CH4_SW_CNTL 0x20000000L +#define RBBM_DSPLY__DMI_CH4_NUM_BUFS_MASK 0xc0000000L + +// RBBM_RENDER_LATEST +#define RBBM_RENDER_LATEST__DMI_CH1_BUFFER_ID_MASK 0x00000003L +#define RBBM_RENDER_LATEST__DMI_CH2_BUFFER_ID_MASK 0x00000300L +#define RBBM_RENDER_LATEST__DMI_CH3_BUFFER_ID_MASK 0x00030000L +#define RBBM_RENDER_LATEST__DMI_CH4_BUFFER_ID_MASK 0x03000000L + +// RBBM_RTL_RELEASE +#define RBBM_RTL_RELEASE__CHANGELIST_MASK 0xffffffffL + +// RBBM_PATCH_RELEASE +#define RBBM_PATCH_RELEASE__PATCH_REVISION_MASK 0x0000ffffL +#define RBBM_PATCH_RELEASE__PATCH_SELECTION_MASK 0x00ff0000L +#define RBBM_PATCH_RELEASE__CUSTOMER_ID_MASK 0xff000000L + +// RBBM_AUXILIARY_CONFIG +#define RBBM_AUXILIARY_CONFIG__RESERVED_MASK 0xffffffffL + +// RBBM_PERIPHID0 +#define RBBM_PERIPHID0__PARTNUMBER0_MASK 0x000000ffL + +// RBBM_PERIPHID1 +#define RBBM_PERIPHID1__PARTNUMBER1_MASK 0x0000000fL +#define RBBM_PERIPHID1__DESIGNER0_MASK 0x000000f0L + +// RBBM_PERIPHID2 +#define RBBM_PERIPHID2__DESIGNER1_MASK 0x0000000fL +#define RBBM_PERIPHID2__REVISION_MASK 0x000000f0L + +// RBBM_PERIPHID3 +#define RBBM_PERIPHID3__RBBM_HOST_INTERFACE_MASK 0x00000003L +#define RBBM_PERIPHID3__GARB_SLAVE_INTERFACE_MASK 0x0000000cL +#define RBBM_PERIPHID3__MH_INTERFACE_MASK 0x00000030L +#define RBBM_PERIPHID3__CONTINUATION_MASK 0x00000080L +#define RBBM_PERIPHID3__CONTINUATION 0x00000080L + +// RBBM_CNTL +#define RBBM_CNTL__READ_TIMEOUT_MASK 0x000000ffL +#define RBBM_CNTL__REGCLK_DEASSERT_TIME_MASK 0x0001ff00L + +// RBBM_SKEW_CNTL +#define RBBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x0000001fL +#define RBBM_SKEW_CNTL__SKEW_COUNT_MASK 0x000003e0L + +// RBBM_SOFT_RESET +#define RBBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L +#define RBBM_SOFT_RESET__SOFT_RESET_CP 0x00000001L +#define RBBM_SOFT_RESET__SOFT_RESET_PA_MASK 0x00000004L +#define RBBM_SOFT_RESET__SOFT_RESET_PA 0x00000004L +#define RBBM_SOFT_RESET__SOFT_RESET_MH_MASK 0x00000008L +#define RBBM_SOFT_RESET__SOFT_RESET_MH 0x00000008L +#define RBBM_SOFT_RESET__SOFT_RESET_BC_MASK 0x00000010L +#define RBBM_SOFT_RESET__SOFT_RESET_BC 0x00000010L +#define RBBM_SOFT_RESET__SOFT_RESET_SQ_MASK 0x00000020L +#define RBBM_SOFT_RESET__SOFT_RESET_SQ 0x00000020L +#define RBBM_SOFT_RESET__SOFT_RESET_SX_MASK 0x00000040L +#define RBBM_SOFT_RESET__SOFT_RESET_SX 0x00000040L +#define RBBM_SOFT_RESET__SOFT_RESET_CIB_MASK 0x00001000L +#define RBBM_SOFT_RESET__SOFT_RESET_CIB 0x00001000L +#define RBBM_SOFT_RESET__SOFT_RESET_SC_MASK 0x00008000L +#define RBBM_SOFT_RESET__SOFT_RESET_SC 0x00008000L +#define RBBM_SOFT_RESET__SOFT_RESET_VGT_MASK 0x00010000L +#define RBBM_SOFT_RESET__SOFT_RESET_VGT 0x00010000L + +// RBBM_PM_OVERRIDE1 +#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE_MASK 0x00000001L +#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE 0x00000001L +#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE_MASK 0x00000002L +#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE 0x00000002L +#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE_MASK 0x00000004L +#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE 0x00000004L +#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE_MASK 0x00000008L +#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE 0x00000008L +#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE_MASK 0x00000010L +#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE 0x00000010L +#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE_MASK 0x00000020L +#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE 0x00000020L +#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000040L +#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE 0x00000040L +#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK 0x00000080L +#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE 0x00000080L +#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE_MASK 0x00000100L +#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE 0x00000100L +#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE_MASK 0x00000200L +#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE 0x00000200L +#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE_MASK 0x00000400L +#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE 0x00000400L +#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE_MASK 0x00000800L +#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE 0x00000800L +#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE_MASK 0x00001000L +#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE 0x00001000L +#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE_MASK 0x00002000L +#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE 0x00002000L +#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE_MASK 0x00004000L +#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE 0x00004000L +#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE_MASK 0x00008000L +#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE 0x00008000L +#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE_MASK 0x00010000L +#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE 0x00010000L +#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE_MASK 0x00020000L +#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE 0x00020000L +#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE_MASK 0x00040000L +#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE 0x00040000L +#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK 0x00080000L +#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE 0x00080000L +#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE_MASK 0x00100000L +#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE 0x00100000L +#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE_MASK 0x00200000L +#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE 0x00200000L +#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE_MASK 0x00400000L +#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE 0x00400000L +#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE_MASK 0x00800000L +#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE 0x00800000L +#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE_MASK 0x01000000L +#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE 0x01000000L +#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE_MASK 0x02000000L +#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE 0x02000000L +#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE_MASK 0x04000000L +#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE 0x04000000L +#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE_MASK 0x08000000L +#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE 0x08000000L +#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE_MASK 0x10000000L +#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE 0x10000000L +#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE_MASK 0x20000000L +#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE 0x20000000L +#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE_MASK 0x40000000L +#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE 0x40000000L +#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE_MASK 0x80000000L +#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE 0x80000000L + +// RBBM_PM_OVERRIDE2 +#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE_MASK 0x00000001L +#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE 0x00000001L +#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE_MASK 0x00000002L +#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE 0x00000002L +#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE_MASK 0x00000004L +#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE 0x00000004L +#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE_MASK 0x00000008L +#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE 0x00000008L +#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000010L +#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE 0x00000010L +#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE_MASK 0x00000020L +#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE 0x00000020L +#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE_MASK 0x00000040L +#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE 0x00000040L +#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE_MASK 0x00000080L +#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE 0x00000080L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE_MASK 0x00000100L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE 0x00000100L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE_MASK 0x00000200L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE 0x00000200L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE_MASK 0x00000400L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE 0x00000400L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE_MASK 0x00000800L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE 0x00000800L + +// GC_SYS_IDLE +#define GC_SYS_IDLE__GC_SYS_IDLE_DELAY_MASK 0x0000ffffL +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_MASK_MASK 0x003f0000L +#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_MASK 0x01000000L +#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP 0x01000000L +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_MASK 0x02000000L +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI 0x02000000L +#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_OVERRIDE_MASK 0x20000000L +#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_OVERRIDE 0x20000000L +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_OVERRIDE_MASK 0x40000000L +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_OVERRIDE 0x40000000L +#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE_MASK 0x80000000L +#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE 0x80000000L + +// NQWAIT_UNTIL +#define NQWAIT_UNTIL__WAIT_GUI_IDLE_MASK 0x00000001L +#define NQWAIT_UNTIL__WAIT_GUI_IDLE 0x00000001L + +// RBBM_DEBUG_OUT +#define RBBM_DEBUG_OUT__DEBUG_BUS_OUT_MASK 0xffffffffL + +// RBBM_DEBUG_CNTL +#define RBBM_DEBUG_CNTL__SUB_BLOCK_ADDR_MASK 0x0000003fL +#define RBBM_DEBUG_CNTL__SUB_BLOCK_SEL_MASK 0x00000f00L +#define RBBM_DEBUG_CNTL__SW_ENABLE_MASK 0x00001000L +#define RBBM_DEBUG_CNTL__SW_ENABLE 0x00001000L +#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_ADDR_MASK 0x003f0000L +#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_SEL_MASK 0x0f000000L +#define RBBM_DEBUG_CNTL__GPIO_BYTE_LANE_ENB_MASK 0xf0000000L + +// RBBM_DEBUG +#define RBBM_DEBUG__IGNORE_RTR_MASK 0x00000002L +#define RBBM_DEBUG__IGNORE_RTR 0x00000002L +#define RBBM_DEBUG__IGNORE_CP_SCHED_WU_MASK 0x00000004L +#define RBBM_DEBUG__IGNORE_CP_SCHED_WU 0x00000004L +#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC_MASK 0x00000008L +#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC 0x00000008L +#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI_MASK 0x00000010L +#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI 0x00000010L +#define RBBM_DEBUG__HYSTERESIS_NRT_GUI_ACTIVE_MASK 0x00000f00L +#define RBBM_DEBUG__IGNORE_RTR_FOR_HI_MASK 0x00010000L +#define RBBM_DEBUG__IGNORE_RTR_FOR_HI 0x00010000L +#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK 0x00020000L +#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI 0x00020000L +#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK 0x00040000L +#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI 0x00040000L +#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK 0x00080000L +#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI 0x00080000L +#define RBBM_DEBUG__CP_RBBM_NRTRTR_MASK 0x00100000L +#define RBBM_DEBUG__CP_RBBM_NRTRTR 0x00100000L +#define RBBM_DEBUG__VGT_RBBM_NRTRTR_MASK 0x00200000L +#define RBBM_DEBUG__VGT_RBBM_NRTRTR 0x00200000L +#define RBBM_DEBUG__SQ_RBBM_NRTRTR_MASK 0x00400000L +#define RBBM_DEBUG__SQ_RBBM_NRTRTR 0x00400000L +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI_MASK 0x00800000L +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI 0x00800000L +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_MASK 0x01000000L +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR 0x01000000L +#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY_MASK 0x80000000L +#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY 0x80000000L + +// RBBM_READ_ERROR +#define RBBM_READ_ERROR__READ_ADDRESS_MASK 0x0001fffcL +#define RBBM_READ_ERROR__READ_REQUESTER_MASK 0x40000000L +#define RBBM_READ_ERROR__READ_REQUESTER 0x40000000L +#define RBBM_READ_ERROR__READ_ERROR_MASK 0x80000000L +#define RBBM_READ_ERROR__READ_ERROR 0x80000000L + +// RBBM_WAIT_IDLE_CLOCKS +#define RBBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_NRT_MASK 0x000000ffL + +// RBBM_INT_CNTL +#define RBBM_INT_CNTL__RDERR_INT_MASK_MASK 0x00000001L +#define RBBM_INT_CNTL__RDERR_INT_MASK 0x00000001L +#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK_MASK 0x00000002L +#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK 0x00000002L +#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK_MASK 0x00080000L +#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK 0x00080000L + +// RBBM_INT_STATUS +#define RBBM_INT_STATUS__RDERR_INT_STAT_MASK 0x00000001L +#define RBBM_INT_STATUS__RDERR_INT_STAT 0x00000001L +#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT_MASK 0x00000002L +#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT 0x00000002L +#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT_MASK 0x00080000L +#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT 0x00080000L + +// RBBM_INT_ACK +#define RBBM_INT_ACK__RDERR_INT_ACK_MASK 0x00000001L +#define RBBM_INT_ACK__RDERR_INT_ACK 0x00000001L +#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK_MASK 0x00000002L +#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK 0x00000002L +#define RBBM_INT_ACK__GUI_IDLE_INT_ACK_MASK 0x00080000L +#define RBBM_INT_ACK__GUI_IDLE_INT_ACK 0x00080000L + +// MASTER_INT_SIGNAL +#define MASTER_INT_SIGNAL__MH_INT_STAT_MASK 0x00000020L +#define MASTER_INT_SIGNAL__MH_INT_STAT 0x00000020L +#define MASTER_INT_SIGNAL__SQ_INT_STAT_MASK 0x04000000L +#define MASTER_INT_SIGNAL__SQ_INT_STAT 0x04000000L +#define MASTER_INT_SIGNAL__CP_INT_STAT_MASK 0x40000000L +#define MASTER_INT_SIGNAL__CP_INT_STAT 0x40000000L +#define MASTER_INT_SIGNAL__RBBM_INT_STAT_MASK 0x80000000L +#define MASTER_INT_SIGNAL__RBBM_INT_STAT 0x80000000L + +// RBBM_PERFCOUNTER1_SELECT +#define RBBM_PERFCOUNTER1_SELECT__PERF_COUNT1_SEL_MASK 0x0000003fL + +// RBBM_PERFCOUNTER1_LO +#define RBBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK 0xffffffffL + +// RBBM_PERFCOUNTER1_HI +#define RBBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK 0x0000ffffL + +// CP_RB_BASE +#define CP_RB_BASE__RB_BASE_MASK 0xffffffe0L + +// CP_RB_CNTL +#define CP_RB_CNTL__RB_BUFSZ_MASK 0x0000003fL +#define CP_RB_CNTL__RB_BLKSZ_MASK 0x00003f00L +#define CP_RB_CNTL__BUF_SWAP_MASK 0x00030000L +#define CP_RB_CNTL__RB_POLL_EN_MASK 0x00100000L +#define CP_RB_CNTL__RB_POLL_EN 0x00100000L +#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x08000000L +#define CP_RB_CNTL__RB_NO_UPDATE 0x08000000L +#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L +#define CP_RB_CNTL__RB_RPTR_WR_ENA 0x80000000L + +// CP_RB_RPTR_ADDR +#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x00000003L +#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffcL + +// CP_RB_RPTR +#define CP_RB_RPTR__RB_RPTR_MASK 0x000fffffL + +// CP_RB_RPTR_WR +#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0x000fffffL + +// CP_RB_WPTR +#define CP_RB_WPTR__RB_WPTR_MASK 0x000fffffL + +// CP_RB_WPTR_DELAY +#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0x0fffffffL +#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xf0000000L + +// CP_RB_WPTR_BASE +#define CP_RB_WPTR_BASE__RB_WPTR_SWAP_MASK 0x00000003L +#define CP_RB_WPTR_BASE__RB_WPTR_BASE_MASK 0xfffffffcL + +// CP_IB1_BASE +#define CP_IB1_BASE__IB1_BASE_MASK 0xfffffffcL + +// CP_IB1_BUFSZ +#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000fffffL + +// CP_IB2_BASE +#define CP_IB2_BASE__IB2_BASE_MASK 0xfffffffcL + +// CP_IB2_BUFSZ +#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000fffffL + +// CP_ST_BASE +#define CP_ST_BASE__ST_BASE_MASK 0xfffffffcL + +// CP_ST_BUFSZ +#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0x000fffffL + +// CP_QUEUE_THRESHOLDS +#define CP_QUEUE_THRESHOLDS__CSQ_IB1_START_MASK 0x0000000fL +#define CP_QUEUE_THRESHOLDS__CSQ_IB2_START_MASK 0x00000f00L +#define CP_QUEUE_THRESHOLDS__CSQ_ST_START_MASK 0x000f0000L + +// CP_MEQ_THRESHOLDS +#define CP_MEQ_THRESHOLDS__MEQ_END_MASK 0x001f0000L +#define CP_MEQ_THRESHOLDS__ROQ_END_MASK 0x1f000000L + +// CP_CSQ_AVAIL +#define CP_CSQ_AVAIL__CSQ_CNT_RING_MASK 0x0000007fL +#define CP_CSQ_AVAIL__CSQ_CNT_IB1_MASK 0x00007f00L +#define CP_CSQ_AVAIL__CSQ_CNT_IB2_MASK 0x007f0000L + +// CP_STQ_AVAIL +#define CP_STQ_AVAIL__STQ_CNT_ST_MASK 0x0000007fL + +// CP_MEQ_AVAIL +#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x0000001fL + +// CP_CSQ_RB_STAT +#define CP_CSQ_RB_STAT__CSQ_RPTR_PRIMARY_MASK 0x0000007fL +#define CP_CSQ_RB_STAT__CSQ_WPTR_PRIMARY_MASK 0x007f0000L + +// CP_CSQ_IB1_STAT +#define CP_CSQ_IB1_STAT__CSQ_RPTR_INDIRECT1_MASK 0x0000007fL +#define CP_CSQ_IB1_STAT__CSQ_WPTR_INDIRECT1_MASK 0x007f0000L + +// CP_CSQ_IB2_STAT +#define CP_CSQ_IB2_STAT__CSQ_RPTR_INDIRECT2_MASK 0x0000007fL +#define CP_CSQ_IB2_STAT__CSQ_WPTR_INDIRECT2_MASK 0x007f0000L + +// CP_NON_PREFETCH_CNTRS +#define CP_NON_PREFETCH_CNTRS__IB1_COUNTER_MASK 0x00000007L +#define CP_NON_PREFETCH_CNTRS__IB2_COUNTER_MASK 0x00000700L + +// CP_STQ_ST_STAT +#define CP_STQ_ST_STAT__STQ_RPTR_ST_MASK 0x0000007fL +#define CP_STQ_ST_STAT__STQ_WPTR_ST_MASK 0x007f0000L + +// CP_MEQ_STAT +#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x000003ffL +#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x03ff0000L + +// CP_MIU_TAG_STAT +#define CP_MIU_TAG_STAT__TAG_0_STAT_MASK 0x00000001L +#define CP_MIU_TAG_STAT__TAG_0_STAT 0x00000001L +#define CP_MIU_TAG_STAT__TAG_1_STAT_MASK 0x00000002L +#define CP_MIU_TAG_STAT__TAG_1_STAT 0x00000002L +#define CP_MIU_TAG_STAT__TAG_2_STAT_MASK 0x00000004L +#define CP_MIU_TAG_STAT__TAG_2_STAT 0x00000004L +#define CP_MIU_TAG_STAT__TAG_3_STAT_MASK 0x00000008L +#define CP_MIU_TAG_STAT__TAG_3_STAT 0x00000008L +#define CP_MIU_TAG_STAT__TAG_4_STAT_MASK 0x00000010L +#define CP_MIU_TAG_STAT__TAG_4_STAT 0x00000010L +#define CP_MIU_TAG_STAT__TAG_5_STAT_MASK 0x00000020L +#define CP_MIU_TAG_STAT__TAG_5_STAT 0x00000020L +#define CP_MIU_TAG_STAT__TAG_6_STAT_MASK 0x00000040L +#define CP_MIU_TAG_STAT__TAG_6_STAT 0x00000040L +#define CP_MIU_TAG_STAT__TAG_7_STAT_MASK 0x00000080L +#define CP_MIU_TAG_STAT__TAG_7_STAT 0x00000080L +#define CP_MIU_TAG_STAT__TAG_8_STAT_MASK 0x00000100L +#define CP_MIU_TAG_STAT__TAG_8_STAT 0x00000100L +#define CP_MIU_TAG_STAT__TAG_9_STAT_MASK 0x00000200L +#define CP_MIU_TAG_STAT__TAG_9_STAT 0x00000200L +#define CP_MIU_TAG_STAT__TAG_10_STAT_MASK 0x00000400L +#define CP_MIU_TAG_STAT__TAG_10_STAT 0x00000400L +#define CP_MIU_TAG_STAT__TAG_11_STAT_MASK 0x00000800L +#define CP_MIU_TAG_STAT__TAG_11_STAT 0x00000800L +#define CP_MIU_TAG_STAT__TAG_12_STAT_MASK 0x00001000L +#define CP_MIU_TAG_STAT__TAG_12_STAT 0x00001000L +#define CP_MIU_TAG_STAT__TAG_13_STAT_MASK 0x00002000L +#define CP_MIU_TAG_STAT__TAG_13_STAT 0x00002000L +#define CP_MIU_TAG_STAT__TAG_14_STAT_MASK 0x00004000L +#define CP_MIU_TAG_STAT__TAG_14_STAT 0x00004000L +#define CP_MIU_TAG_STAT__TAG_15_STAT_MASK 0x00008000L +#define CP_MIU_TAG_STAT__TAG_15_STAT 0x00008000L +#define CP_MIU_TAG_STAT__TAG_16_STAT_MASK 0x00010000L +#define CP_MIU_TAG_STAT__TAG_16_STAT 0x00010000L +#define CP_MIU_TAG_STAT__TAG_17_STAT_MASK 0x00020000L +#define CP_MIU_TAG_STAT__TAG_17_STAT 0x00020000L +#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG_MASK 0x80000000L +#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG 0x80000000L + +// CP_CMD_INDEX +#define CP_CMD_INDEX__CMD_INDEX_MASK 0x0000007fL +#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x00030000L + +// CP_CMD_DATA +#define CP_CMD_DATA__CMD_DATA_MASK 0xffffffffL + +// CP_ME_CNTL +#define CP_ME_CNTL__ME_STATMUX_MASK 0x0000ffffL +#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY_MASK 0x02000000L +#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY 0x02000000L +#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY_MASK 0x04000000L +#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY 0x04000000L +#define CP_ME_CNTL__ME_HALT_MASK 0x10000000L +#define CP_ME_CNTL__ME_HALT 0x10000000L +#define CP_ME_CNTL__ME_BUSY_MASK 0x20000000L +#define CP_ME_CNTL__ME_BUSY 0x20000000L +#define CP_ME_CNTL__PROG_CNT_SIZE_MASK 0x80000000L +#define CP_ME_CNTL__PROG_CNT_SIZE 0x80000000L + +// CP_ME_STATUS +#define CP_ME_STATUS__ME_DEBUG_DATA_MASK 0xffffffffL + +// CP_ME_RAM_WADDR +#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x000003ffL + +// CP_ME_RAM_RADDR +#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x000003ffL + +// CP_ME_RAM_DATA +#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xffffffffL + +// CP_ME_RDADDR +#define CP_ME_RDADDR__ME_RDADDR_MASK 0xffffffffL + +// CP_DEBUG +#define CP_DEBUG__CP_DEBUG_UNUSED_22_to_0_MASK 0x007fffffL +#define CP_DEBUG__PREDICATE_DISABLE_MASK 0x00800000L +#define CP_DEBUG__PREDICATE_DISABLE 0x00800000L +#define CP_DEBUG__PROG_END_PTR_ENABLE_MASK 0x01000000L +#define CP_DEBUG__PROG_END_PTR_ENABLE 0x01000000L +#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE_MASK 0x02000000L +#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE 0x02000000L +#define CP_DEBUG__PREFETCH_PASS_NOPS_MASK 0x04000000L +#define CP_DEBUG__PREFETCH_PASS_NOPS 0x04000000L +#define CP_DEBUG__DYNAMIC_CLK_DISABLE_MASK 0x08000000L +#define CP_DEBUG__DYNAMIC_CLK_DISABLE 0x08000000L +#define CP_DEBUG__PREFETCH_MATCH_DISABLE_MASK 0x10000000L +#define CP_DEBUG__PREFETCH_MATCH_DISABLE 0x10000000L +#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL_MASK 0x40000000L +#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL 0x40000000L +#define CP_DEBUG__MIU_WRITE_PACK_DISABLE_MASK 0x80000000L +#define CP_DEBUG__MIU_WRITE_PACK_DISABLE 0x80000000L + +// SCRATCH_REG0 +#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffffL +#define GUI_SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffffL + +// SCRATCH_REG1 +#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffffL +#define GUI_SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffffL + +// SCRATCH_REG2 +#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffffL +#define GUI_SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffffL + +// SCRATCH_REG3 +#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffffL +#define GUI_SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffffL + +// SCRATCH_REG4 +#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffffL +#define GUI_SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffffL + +// SCRATCH_REG5 +#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffffL +#define GUI_SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffffL + +// SCRATCH_REG6 +#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffffL +#define GUI_SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffffL + +// SCRATCH_REG7 +#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffffL +#define GUI_SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffffL + +// SCRATCH_UMSK +#define SCRATCH_UMSK__SCRATCH_UMSK_MASK 0x000000ffL +#define SCRATCH_UMSK__SCRATCH_SWAP_MASK 0x00030000L + +// SCRATCH_ADDR +#define SCRATCH_ADDR__SCRATCH_ADDR_MASK 0xffffffe0L + +// CP_ME_VS_EVENT_SRC +#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM_MASK 0x00000001L +#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM 0x00000001L +#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR_MASK 0x00000002L +#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR 0x00000002L + +// CP_ME_VS_EVENT_ADDR +#define CP_ME_VS_EVENT_ADDR__VS_DONE_SWAP_MASK 0x00000003L +#define CP_ME_VS_EVENT_ADDR__VS_DONE_ADDR_MASK 0xfffffffcL + +// CP_ME_VS_EVENT_DATA +#define CP_ME_VS_EVENT_DATA__VS_DONE_DATA_MASK 0xffffffffL + +// CP_ME_VS_EVENT_ADDR_SWM +#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_SWAP_SWM_MASK 0x00000003L +#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_ADDR_SWM_MASK 0xfffffffcL + +// CP_ME_VS_EVENT_DATA_SWM +#define CP_ME_VS_EVENT_DATA_SWM__VS_DONE_DATA_SWM_MASK 0xffffffffL + +// CP_ME_PS_EVENT_SRC +#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM_MASK 0x00000001L +#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM 0x00000001L +#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR_MASK 0x00000002L +#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR 0x00000002L + +// CP_ME_PS_EVENT_ADDR +#define CP_ME_PS_EVENT_ADDR__PS_DONE_SWAP_MASK 0x00000003L +#define CP_ME_PS_EVENT_ADDR__PS_DONE_ADDR_MASK 0xfffffffcL + +// CP_ME_PS_EVENT_DATA +#define CP_ME_PS_EVENT_DATA__PS_DONE_DATA_MASK 0xffffffffL + +// CP_ME_PS_EVENT_ADDR_SWM +#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_SWAP_SWM_MASK 0x00000003L +#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_ADDR_SWM_MASK 0xfffffffcL + +// CP_ME_PS_EVENT_DATA_SWM +#define CP_ME_PS_EVENT_DATA_SWM__PS_DONE_DATA_SWM_MASK 0xffffffffL + +// CP_ME_CF_EVENT_SRC +#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC_MASK 0x00000001L +#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC 0x00000001L + +// CP_ME_CF_EVENT_ADDR +#define CP_ME_CF_EVENT_ADDR__CF_DONE_SWAP_MASK 0x00000003L +#define CP_ME_CF_EVENT_ADDR__CF_DONE_ADDR_MASK 0xfffffffcL + +// CP_ME_CF_EVENT_DATA +#define CP_ME_CF_EVENT_DATA__CF_DONE_DATA_MASK 0xffffffffL + +// CP_ME_NRT_ADDR +#define CP_ME_NRT_ADDR__NRT_WRITE_SWAP_MASK 0x00000003L +#define CP_ME_NRT_ADDR__NRT_WRITE_ADDR_MASK 0xfffffffcL + +// CP_ME_NRT_DATA +#define CP_ME_NRT_DATA__NRT_WRITE_DATA_MASK 0xffffffffL + +// CP_ME_VS_FETCH_DONE_SRC +#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR_MASK 0x00000001L +#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR 0x00000001L + +// CP_ME_VS_FETCH_DONE_ADDR +#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_SWAP_MASK 0x00000003L +#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_ADDR_MASK 0xfffffffcL + +// CP_ME_VS_FETCH_DONE_DATA +#define CP_ME_VS_FETCH_DONE_DATA__VS_FETCH_DONE_DATA_MASK 0xffffffffL + +// CP_INT_CNTL +#define CP_INT_CNTL__SW_INT_MASK_MASK 0x00080000L +#define CP_INT_CNTL__SW_INT_MASK 0x00080000L +#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK_MASK 0x00800000L +#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK 0x00800000L +#define CP_INT_CNTL__OPCODE_ERROR_MASK_MASK 0x01000000L +#define CP_INT_CNTL__OPCODE_ERROR_MASK 0x01000000L +#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK_MASK 0x02000000L +#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK 0x02000000L +#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK_MASK 0x04000000L +#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK 0x04000000L +#define CP_INT_CNTL__IB_ERROR_MASK_MASK 0x08000000L +#define CP_INT_CNTL__IB_ERROR_MASK 0x08000000L +#define CP_INT_CNTL__IB2_INT_MASK_MASK 0x20000000L +#define CP_INT_CNTL__IB2_INT_MASK 0x20000000L +#define CP_INT_CNTL__IB1_INT_MASK_MASK 0x40000000L +#define CP_INT_CNTL__IB1_INT_MASK 0x40000000L +#define CP_INT_CNTL__RB_INT_MASK_MASK 0x80000000L +#define CP_INT_CNTL__RB_INT_MASK 0x80000000L + +// CP_INT_STATUS +#define CP_INT_STATUS__SW_INT_STAT_MASK 0x00080000L +#define CP_INT_STATUS__SW_INT_STAT 0x00080000L +#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT_MASK 0x00800000L +#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT 0x00800000L +#define CP_INT_STATUS__OPCODE_ERROR_STAT_MASK 0x01000000L +#define CP_INT_STATUS__OPCODE_ERROR_STAT 0x01000000L +#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT_MASK 0x02000000L +#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT 0x02000000L +#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT_MASK 0x04000000L +#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT 0x04000000L +#define CP_INT_STATUS__IB_ERROR_STAT_MASK 0x08000000L +#define CP_INT_STATUS__IB_ERROR_STAT 0x08000000L +#define CP_INT_STATUS__IB2_INT_STAT_MASK 0x20000000L +#define CP_INT_STATUS__IB2_INT_STAT 0x20000000L +#define CP_INT_STATUS__IB1_INT_STAT_MASK 0x40000000L +#define CP_INT_STATUS__IB1_INT_STAT 0x40000000L +#define CP_INT_STATUS__RB_INT_STAT_MASK 0x80000000L +#define CP_INT_STATUS__RB_INT_STAT 0x80000000L + +// CP_INT_ACK +#define CP_INT_ACK__SW_INT_ACK_MASK 0x00080000L +#define CP_INT_ACK__SW_INT_ACK 0x00080000L +#define CP_INT_ACK__T0_PACKET_IN_IB_ACK_MASK 0x00800000L +#define CP_INT_ACK__T0_PACKET_IN_IB_ACK 0x00800000L +#define CP_INT_ACK__OPCODE_ERROR_ACK_MASK 0x01000000L +#define CP_INT_ACK__OPCODE_ERROR_ACK 0x01000000L +#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK_MASK 0x02000000L +#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK 0x02000000L +#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK_MASK 0x04000000L +#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK 0x04000000L +#define CP_INT_ACK__IB_ERROR_ACK_MASK 0x08000000L +#define CP_INT_ACK__IB_ERROR_ACK 0x08000000L +#define CP_INT_ACK__IB2_INT_ACK_MASK 0x20000000L +#define CP_INT_ACK__IB2_INT_ACK 0x20000000L +#define CP_INT_ACK__IB1_INT_ACK_MASK 0x40000000L +#define CP_INT_ACK__IB1_INT_ACK 0x40000000L +#define CP_INT_ACK__RB_INT_ACK_MASK 0x80000000L +#define CP_INT_ACK__RB_INT_ACK 0x80000000L + +// CP_PFP_UCODE_ADDR +#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x000001ffL + +// CP_PFP_UCODE_DATA +#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0x00ffffffL + +// CP_PERFMON_CNTL +#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000fL +#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L + +// CP_PERFCOUNTER_SELECT +#define CP_PERFCOUNTER_SELECT__PERFCOUNT_SEL_MASK 0x0000003fL + +// CP_PERFCOUNTER_LO +#define CP_PERFCOUNTER_LO__PERFCOUNT_LO_MASK 0xffffffffL + +// CP_PERFCOUNTER_HI +#define CP_PERFCOUNTER_HI__PERFCOUNT_HI_MASK 0x0000ffffL + +// CP_BIN_MASK_LO +#define CP_BIN_MASK_LO__BIN_MASK_LO_MASK 0xffffffffL + +// CP_BIN_MASK_HI +#define CP_BIN_MASK_HI__BIN_MASK_HI_MASK 0xffffffffL + +// CP_BIN_SELECT_LO +#define CP_BIN_SELECT_LO__BIN_SELECT_LO_MASK 0xffffffffL + +// CP_BIN_SELECT_HI +#define CP_BIN_SELECT_HI__BIN_SELECT_HI_MASK 0xffffffffL + +// CP_NV_FLAGS_0 +#define CP_NV_FLAGS_0__DISCARD_0_MASK 0x00000001L +#define CP_NV_FLAGS_0__DISCARD_0 0x00000001L +#define CP_NV_FLAGS_0__END_RCVD_0_MASK 0x00000002L +#define CP_NV_FLAGS_0__END_RCVD_0 0x00000002L +#define CP_NV_FLAGS_0__DISCARD_1_MASK 0x00000004L +#define CP_NV_FLAGS_0__DISCARD_1 0x00000004L +#define CP_NV_FLAGS_0__END_RCVD_1_MASK 0x00000008L +#define CP_NV_FLAGS_0__END_RCVD_1 0x00000008L +#define CP_NV_FLAGS_0__DISCARD_2_MASK 0x00000010L +#define CP_NV_FLAGS_0__DISCARD_2 0x00000010L +#define CP_NV_FLAGS_0__END_RCVD_2_MASK 0x00000020L +#define CP_NV_FLAGS_0__END_RCVD_2 0x00000020L +#define CP_NV_FLAGS_0__DISCARD_3_MASK 0x00000040L +#define CP_NV_FLAGS_0__DISCARD_3 0x00000040L +#define CP_NV_FLAGS_0__END_RCVD_3_MASK 0x00000080L +#define CP_NV_FLAGS_0__END_RCVD_3 0x00000080L +#define CP_NV_FLAGS_0__DISCARD_4_MASK 0x00000100L +#define CP_NV_FLAGS_0__DISCARD_4 0x00000100L +#define CP_NV_FLAGS_0__END_RCVD_4_MASK 0x00000200L +#define CP_NV_FLAGS_0__END_RCVD_4 0x00000200L +#define CP_NV_FLAGS_0__DISCARD_5_MASK 0x00000400L +#define CP_NV_FLAGS_0__DISCARD_5 0x00000400L +#define CP_NV_FLAGS_0__END_RCVD_5_MASK 0x00000800L +#define CP_NV_FLAGS_0__END_RCVD_5 0x00000800L +#define CP_NV_FLAGS_0__DISCARD_6_MASK 0x00001000L +#define CP_NV_FLAGS_0__DISCARD_6 0x00001000L +#define CP_NV_FLAGS_0__END_RCVD_6_MASK 0x00002000L +#define CP_NV_FLAGS_0__END_RCVD_6 0x00002000L +#define CP_NV_FLAGS_0__DISCARD_7_MASK 0x00004000L +#define CP_NV_FLAGS_0__DISCARD_7 0x00004000L +#define CP_NV_FLAGS_0__END_RCVD_7_MASK 0x00008000L +#define CP_NV_FLAGS_0__END_RCVD_7 0x00008000L +#define CP_NV_FLAGS_0__DISCARD_8_MASK 0x00010000L +#define CP_NV_FLAGS_0__DISCARD_8 0x00010000L +#define CP_NV_FLAGS_0__END_RCVD_8_MASK 0x00020000L +#define CP_NV_FLAGS_0__END_RCVD_8 0x00020000L +#define CP_NV_FLAGS_0__DISCARD_9_MASK 0x00040000L +#define CP_NV_FLAGS_0__DISCARD_9 0x00040000L +#define CP_NV_FLAGS_0__END_RCVD_9_MASK 0x00080000L +#define CP_NV_FLAGS_0__END_RCVD_9 0x00080000L +#define CP_NV_FLAGS_0__DISCARD_10_MASK 0x00100000L +#define CP_NV_FLAGS_0__DISCARD_10 0x00100000L +#define CP_NV_FLAGS_0__END_RCVD_10_MASK 0x00200000L +#define CP_NV_FLAGS_0__END_RCVD_10 0x00200000L +#define CP_NV_FLAGS_0__DISCARD_11_MASK 0x00400000L +#define CP_NV_FLAGS_0__DISCARD_11 0x00400000L +#define CP_NV_FLAGS_0__END_RCVD_11_MASK 0x00800000L +#define CP_NV_FLAGS_0__END_RCVD_11 0x00800000L +#define CP_NV_FLAGS_0__DISCARD_12_MASK 0x01000000L +#define CP_NV_FLAGS_0__DISCARD_12 0x01000000L +#define CP_NV_FLAGS_0__END_RCVD_12_MASK 0x02000000L +#define CP_NV_FLAGS_0__END_RCVD_12 0x02000000L +#define CP_NV_FLAGS_0__DISCARD_13_MASK 0x04000000L +#define CP_NV_FLAGS_0__DISCARD_13 0x04000000L +#define CP_NV_FLAGS_0__END_RCVD_13_MASK 0x08000000L +#define CP_NV_FLAGS_0__END_RCVD_13 0x08000000L +#define CP_NV_FLAGS_0__DISCARD_14_MASK 0x10000000L +#define CP_NV_FLAGS_0__DISCARD_14 0x10000000L +#define CP_NV_FLAGS_0__END_RCVD_14_MASK 0x20000000L +#define CP_NV_FLAGS_0__END_RCVD_14 0x20000000L +#define CP_NV_FLAGS_0__DISCARD_15_MASK 0x40000000L +#define CP_NV_FLAGS_0__DISCARD_15 0x40000000L +#define CP_NV_FLAGS_0__END_RCVD_15_MASK 0x80000000L +#define CP_NV_FLAGS_0__END_RCVD_15 0x80000000L + +// CP_NV_FLAGS_1 +#define CP_NV_FLAGS_1__DISCARD_16_MASK 0x00000001L +#define CP_NV_FLAGS_1__DISCARD_16 0x00000001L +#define CP_NV_FLAGS_1__END_RCVD_16_MASK 0x00000002L +#define CP_NV_FLAGS_1__END_RCVD_16 0x00000002L +#define CP_NV_FLAGS_1__DISCARD_17_MASK 0x00000004L +#define CP_NV_FLAGS_1__DISCARD_17 0x00000004L +#define CP_NV_FLAGS_1__END_RCVD_17_MASK 0x00000008L +#define CP_NV_FLAGS_1__END_RCVD_17 0x00000008L +#define CP_NV_FLAGS_1__DISCARD_18_MASK 0x00000010L +#define CP_NV_FLAGS_1__DISCARD_18 0x00000010L +#define CP_NV_FLAGS_1__END_RCVD_18_MASK 0x00000020L +#define CP_NV_FLAGS_1__END_RCVD_18 0x00000020L +#define CP_NV_FLAGS_1__DISCARD_19_MASK 0x00000040L +#define CP_NV_FLAGS_1__DISCARD_19 0x00000040L +#define CP_NV_FLAGS_1__END_RCVD_19_MASK 0x00000080L +#define CP_NV_FLAGS_1__END_RCVD_19 0x00000080L +#define CP_NV_FLAGS_1__DISCARD_20_MASK 0x00000100L +#define CP_NV_FLAGS_1__DISCARD_20 0x00000100L +#define CP_NV_FLAGS_1__END_RCVD_20_MASK 0x00000200L +#define CP_NV_FLAGS_1__END_RCVD_20 0x00000200L +#define CP_NV_FLAGS_1__DISCARD_21_MASK 0x00000400L +#define CP_NV_FLAGS_1__DISCARD_21 0x00000400L +#define CP_NV_FLAGS_1__END_RCVD_21_MASK 0x00000800L +#define CP_NV_FLAGS_1__END_RCVD_21 0x00000800L +#define CP_NV_FLAGS_1__DISCARD_22_MASK 0x00001000L +#define CP_NV_FLAGS_1__DISCARD_22 0x00001000L +#define CP_NV_FLAGS_1__END_RCVD_22_MASK 0x00002000L +#define CP_NV_FLAGS_1__END_RCVD_22 0x00002000L +#define CP_NV_FLAGS_1__DISCARD_23_MASK 0x00004000L +#define CP_NV_FLAGS_1__DISCARD_23 0x00004000L +#define CP_NV_FLAGS_1__END_RCVD_23_MASK 0x00008000L +#define CP_NV_FLAGS_1__END_RCVD_23 0x00008000L +#define CP_NV_FLAGS_1__DISCARD_24_MASK 0x00010000L +#define CP_NV_FLAGS_1__DISCARD_24 0x00010000L +#define CP_NV_FLAGS_1__END_RCVD_24_MASK 0x00020000L +#define CP_NV_FLAGS_1__END_RCVD_24 0x00020000L +#define CP_NV_FLAGS_1__DISCARD_25_MASK 0x00040000L +#define CP_NV_FLAGS_1__DISCARD_25 0x00040000L +#define CP_NV_FLAGS_1__END_RCVD_25_MASK 0x00080000L +#define CP_NV_FLAGS_1__END_RCVD_25 0x00080000L +#define CP_NV_FLAGS_1__DISCARD_26_MASK 0x00100000L +#define CP_NV_FLAGS_1__DISCARD_26 0x00100000L +#define CP_NV_FLAGS_1__END_RCVD_26_MASK 0x00200000L +#define CP_NV_FLAGS_1__END_RCVD_26 0x00200000L +#define CP_NV_FLAGS_1__DISCARD_27_MASK 0x00400000L +#define CP_NV_FLAGS_1__DISCARD_27 0x00400000L +#define CP_NV_FLAGS_1__END_RCVD_27_MASK 0x00800000L +#define CP_NV_FLAGS_1__END_RCVD_27 0x00800000L +#define CP_NV_FLAGS_1__DISCARD_28_MASK 0x01000000L +#define CP_NV_FLAGS_1__DISCARD_28 0x01000000L +#define CP_NV_FLAGS_1__END_RCVD_28_MASK 0x02000000L +#define CP_NV_FLAGS_1__END_RCVD_28 0x02000000L +#define CP_NV_FLAGS_1__DISCARD_29_MASK 0x04000000L +#define CP_NV_FLAGS_1__DISCARD_29 0x04000000L +#define CP_NV_FLAGS_1__END_RCVD_29_MASK 0x08000000L +#define CP_NV_FLAGS_1__END_RCVD_29 0x08000000L +#define CP_NV_FLAGS_1__DISCARD_30_MASK 0x10000000L +#define CP_NV_FLAGS_1__DISCARD_30 0x10000000L +#define CP_NV_FLAGS_1__END_RCVD_30_MASK 0x20000000L +#define CP_NV_FLAGS_1__END_RCVD_30 0x20000000L +#define CP_NV_FLAGS_1__DISCARD_31_MASK 0x40000000L +#define CP_NV_FLAGS_1__DISCARD_31 0x40000000L +#define CP_NV_FLAGS_1__END_RCVD_31_MASK 0x80000000L +#define CP_NV_FLAGS_1__END_RCVD_31 0x80000000L + +// CP_NV_FLAGS_2 +#define CP_NV_FLAGS_2__DISCARD_32_MASK 0x00000001L +#define CP_NV_FLAGS_2__DISCARD_32 0x00000001L +#define CP_NV_FLAGS_2__END_RCVD_32_MASK 0x00000002L +#define CP_NV_FLAGS_2__END_RCVD_32 0x00000002L +#define CP_NV_FLAGS_2__DISCARD_33_MASK 0x00000004L +#define CP_NV_FLAGS_2__DISCARD_33 0x00000004L +#define CP_NV_FLAGS_2__END_RCVD_33_MASK 0x00000008L +#define CP_NV_FLAGS_2__END_RCVD_33 0x00000008L +#define CP_NV_FLAGS_2__DISCARD_34_MASK 0x00000010L +#define CP_NV_FLAGS_2__DISCARD_34 0x00000010L +#define CP_NV_FLAGS_2__END_RCVD_34_MASK 0x00000020L +#define CP_NV_FLAGS_2__END_RCVD_34 0x00000020L +#define CP_NV_FLAGS_2__DISCARD_35_MASK 0x00000040L +#define CP_NV_FLAGS_2__DISCARD_35 0x00000040L +#define CP_NV_FLAGS_2__END_RCVD_35_MASK 0x00000080L +#define CP_NV_FLAGS_2__END_RCVD_35 0x00000080L +#define CP_NV_FLAGS_2__DISCARD_36_MASK 0x00000100L +#define CP_NV_FLAGS_2__DISCARD_36 0x00000100L +#define CP_NV_FLAGS_2__END_RCVD_36_MASK 0x00000200L +#define CP_NV_FLAGS_2__END_RCVD_36 0x00000200L +#define CP_NV_FLAGS_2__DISCARD_37_MASK 0x00000400L +#define CP_NV_FLAGS_2__DISCARD_37 0x00000400L +#define CP_NV_FLAGS_2__END_RCVD_37_MASK 0x00000800L +#define CP_NV_FLAGS_2__END_RCVD_37 0x00000800L +#define CP_NV_FLAGS_2__DISCARD_38_MASK 0x00001000L +#define CP_NV_FLAGS_2__DISCARD_38 0x00001000L +#define CP_NV_FLAGS_2__END_RCVD_38_MASK 0x00002000L +#define CP_NV_FLAGS_2__END_RCVD_38 0x00002000L +#define CP_NV_FLAGS_2__DISCARD_39_MASK 0x00004000L +#define CP_NV_FLAGS_2__DISCARD_39 0x00004000L +#define CP_NV_FLAGS_2__END_RCVD_39_MASK 0x00008000L +#define CP_NV_FLAGS_2__END_RCVD_39 0x00008000L +#define CP_NV_FLAGS_2__DISCARD_40_MASK 0x00010000L +#define CP_NV_FLAGS_2__DISCARD_40 0x00010000L +#define CP_NV_FLAGS_2__END_RCVD_40_MASK 0x00020000L +#define CP_NV_FLAGS_2__END_RCVD_40 0x00020000L +#define CP_NV_FLAGS_2__DISCARD_41_MASK 0x00040000L +#define CP_NV_FLAGS_2__DISCARD_41 0x00040000L +#define CP_NV_FLAGS_2__END_RCVD_41_MASK 0x00080000L +#define CP_NV_FLAGS_2__END_RCVD_41 0x00080000L +#define CP_NV_FLAGS_2__DISCARD_42_MASK 0x00100000L +#define CP_NV_FLAGS_2__DISCARD_42 0x00100000L +#define CP_NV_FLAGS_2__END_RCVD_42_MASK 0x00200000L +#define CP_NV_FLAGS_2__END_RCVD_42 0x00200000L +#define CP_NV_FLAGS_2__DISCARD_43_MASK 0x00400000L +#define CP_NV_FLAGS_2__DISCARD_43 0x00400000L +#define CP_NV_FLAGS_2__END_RCVD_43_MASK 0x00800000L +#define CP_NV_FLAGS_2__END_RCVD_43 0x00800000L +#define CP_NV_FLAGS_2__DISCARD_44_MASK 0x01000000L +#define CP_NV_FLAGS_2__DISCARD_44 0x01000000L +#define CP_NV_FLAGS_2__END_RCVD_44_MASK 0x02000000L +#define CP_NV_FLAGS_2__END_RCVD_44 0x02000000L +#define CP_NV_FLAGS_2__DISCARD_45_MASK 0x04000000L +#define CP_NV_FLAGS_2__DISCARD_45 0x04000000L +#define CP_NV_FLAGS_2__END_RCVD_45_MASK 0x08000000L +#define CP_NV_FLAGS_2__END_RCVD_45 0x08000000L +#define CP_NV_FLAGS_2__DISCARD_46_MASK 0x10000000L +#define CP_NV_FLAGS_2__DISCARD_46 0x10000000L +#define CP_NV_FLAGS_2__END_RCVD_46_MASK 0x20000000L +#define CP_NV_FLAGS_2__END_RCVD_46 0x20000000L +#define CP_NV_FLAGS_2__DISCARD_47_MASK 0x40000000L +#define CP_NV_FLAGS_2__DISCARD_47 0x40000000L +#define CP_NV_FLAGS_2__END_RCVD_47_MASK 0x80000000L +#define CP_NV_FLAGS_2__END_RCVD_47 0x80000000L + +// CP_NV_FLAGS_3 +#define CP_NV_FLAGS_3__DISCARD_48_MASK 0x00000001L +#define CP_NV_FLAGS_3__DISCARD_48 0x00000001L +#define CP_NV_FLAGS_3__END_RCVD_48_MASK 0x00000002L +#define CP_NV_FLAGS_3__END_RCVD_48 0x00000002L +#define CP_NV_FLAGS_3__DISCARD_49_MASK 0x00000004L +#define CP_NV_FLAGS_3__DISCARD_49 0x00000004L +#define CP_NV_FLAGS_3__END_RCVD_49_MASK 0x00000008L +#define CP_NV_FLAGS_3__END_RCVD_49 0x00000008L +#define CP_NV_FLAGS_3__DISCARD_50_MASK 0x00000010L +#define CP_NV_FLAGS_3__DISCARD_50 0x00000010L +#define CP_NV_FLAGS_3__END_RCVD_50_MASK 0x00000020L +#define CP_NV_FLAGS_3__END_RCVD_50 0x00000020L +#define CP_NV_FLAGS_3__DISCARD_51_MASK 0x00000040L +#define CP_NV_FLAGS_3__DISCARD_51 0x00000040L +#define CP_NV_FLAGS_3__END_RCVD_51_MASK 0x00000080L +#define CP_NV_FLAGS_3__END_RCVD_51 0x00000080L +#define CP_NV_FLAGS_3__DISCARD_52_MASK 0x00000100L +#define CP_NV_FLAGS_3__DISCARD_52 0x00000100L +#define CP_NV_FLAGS_3__END_RCVD_52_MASK 0x00000200L +#define CP_NV_FLAGS_3__END_RCVD_52 0x00000200L +#define CP_NV_FLAGS_3__DISCARD_53_MASK 0x00000400L +#define CP_NV_FLAGS_3__DISCARD_53 0x00000400L +#define CP_NV_FLAGS_3__END_RCVD_53_MASK 0x00000800L +#define CP_NV_FLAGS_3__END_RCVD_53 0x00000800L +#define CP_NV_FLAGS_3__DISCARD_54_MASK 0x00001000L +#define CP_NV_FLAGS_3__DISCARD_54 0x00001000L +#define CP_NV_FLAGS_3__END_RCVD_54_MASK 0x00002000L +#define CP_NV_FLAGS_3__END_RCVD_54 0x00002000L +#define CP_NV_FLAGS_3__DISCARD_55_MASK 0x00004000L +#define CP_NV_FLAGS_3__DISCARD_55 0x00004000L +#define CP_NV_FLAGS_3__END_RCVD_55_MASK 0x00008000L +#define CP_NV_FLAGS_3__END_RCVD_55 0x00008000L +#define CP_NV_FLAGS_3__DISCARD_56_MASK 0x00010000L +#define CP_NV_FLAGS_3__DISCARD_56 0x00010000L +#define CP_NV_FLAGS_3__END_RCVD_56_MASK 0x00020000L +#define CP_NV_FLAGS_3__END_RCVD_56 0x00020000L +#define CP_NV_FLAGS_3__DISCARD_57_MASK 0x00040000L +#define CP_NV_FLAGS_3__DISCARD_57 0x00040000L +#define CP_NV_FLAGS_3__END_RCVD_57_MASK 0x00080000L +#define CP_NV_FLAGS_3__END_RCVD_57 0x00080000L +#define CP_NV_FLAGS_3__DISCARD_58_MASK 0x00100000L +#define CP_NV_FLAGS_3__DISCARD_58 0x00100000L +#define CP_NV_FLAGS_3__END_RCVD_58_MASK 0x00200000L +#define CP_NV_FLAGS_3__END_RCVD_58 0x00200000L +#define CP_NV_FLAGS_3__DISCARD_59_MASK 0x00400000L +#define CP_NV_FLAGS_3__DISCARD_59 0x00400000L +#define CP_NV_FLAGS_3__END_RCVD_59_MASK 0x00800000L +#define CP_NV_FLAGS_3__END_RCVD_59 0x00800000L +#define CP_NV_FLAGS_3__DISCARD_60_MASK 0x01000000L +#define CP_NV_FLAGS_3__DISCARD_60 0x01000000L +#define CP_NV_FLAGS_3__END_RCVD_60_MASK 0x02000000L +#define CP_NV_FLAGS_3__END_RCVD_60 0x02000000L +#define CP_NV_FLAGS_3__DISCARD_61_MASK 0x04000000L +#define CP_NV_FLAGS_3__DISCARD_61 0x04000000L +#define CP_NV_FLAGS_3__END_RCVD_61_MASK 0x08000000L +#define CP_NV_FLAGS_3__END_RCVD_61 0x08000000L +#define CP_NV_FLAGS_3__DISCARD_62_MASK 0x10000000L +#define CP_NV_FLAGS_3__DISCARD_62 0x10000000L +#define CP_NV_FLAGS_3__END_RCVD_62_MASK 0x20000000L +#define CP_NV_FLAGS_3__END_RCVD_62 0x20000000L +#define CP_NV_FLAGS_3__DISCARD_63_MASK 0x40000000L +#define CP_NV_FLAGS_3__DISCARD_63 0x40000000L +#define CP_NV_FLAGS_3__END_RCVD_63_MASK 0x80000000L +#define CP_NV_FLAGS_3__END_RCVD_63 0x80000000L + +// CP_STATE_DEBUG_INDEX +#define CP_STATE_DEBUG_INDEX__STATE_DEBUG_INDEX_MASK 0x0000001fL + +// CP_STATE_DEBUG_DATA +#define CP_STATE_DEBUG_DATA__STATE_DEBUG_DATA_MASK 0xffffffffL + +// CP_PROG_COUNTER +#define CP_PROG_COUNTER__COUNTER_MASK 0xffffffffL + +// CP_STAT +#define CP_STAT__MIU_WR_BUSY_MASK 0x00000001L +#define CP_STAT__MIU_WR_BUSY 0x00000001L +#define CP_STAT__MIU_RD_REQ_BUSY_MASK 0x00000002L +#define CP_STAT__MIU_RD_REQ_BUSY 0x00000002L +#define CP_STAT__MIU_RD_RETURN_BUSY_MASK 0x00000004L +#define CP_STAT__MIU_RD_RETURN_BUSY 0x00000004L +#define CP_STAT__RBIU_BUSY_MASK 0x00000008L +#define CP_STAT__RBIU_BUSY 0x00000008L +#define CP_STAT__RCIU_BUSY_MASK 0x00000010L +#define CP_STAT__RCIU_BUSY 0x00000010L +#define CP_STAT__CSF_RING_BUSY_MASK 0x00000020L +#define CP_STAT__CSF_RING_BUSY 0x00000020L +#define CP_STAT__CSF_INDIRECTS_BUSY_MASK 0x00000040L +#define CP_STAT__CSF_INDIRECTS_BUSY 0x00000040L +#define CP_STAT__CSF_INDIRECT2_BUSY_MASK 0x00000080L +#define CP_STAT__CSF_INDIRECT2_BUSY 0x00000080L +#define CP_STAT__CSF_ST_BUSY_MASK 0x00000200L +#define CP_STAT__CSF_ST_BUSY 0x00000200L +#define CP_STAT__CSF_BUSY_MASK 0x00000400L +#define CP_STAT__CSF_BUSY 0x00000400L +#define CP_STAT__RING_QUEUE_BUSY_MASK 0x00000800L +#define CP_STAT__RING_QUEUE_BUSY 0x00000800L +#define CP_STAT__INDIRECTS_QUEUE_BUSY_MASK 0x00001000L +#define CP_STAT__INDIRECTS_QUEUE_BUSY 0x00001000L +#define CP_STAT__INDIRECT2_QUEUE_BUSY_MASK 0x00002000L +#define CP_STAT__INDIRECT2_QUEUE_BUSY 0x00002000L +#define CP_STAT__ST_QUEUE_BUSY_MASK 0x00010000L +#define CP_STAT__ST_QUEUE_BUSY 0x00010000L +#define CP_STAT__PFP_BUSY_MASK 0x00020000L +#define CP_STAT__PFP_BUSY 0x00020000L +#define CP_STAT__MEQ_RING_BUSY_MASK 0x00040000L +#define CP_STAT__MEQ_RING_BUSY 0x00040000L +#define CP_STAT__MEQ_INDIRECTS_BUSY_MASK 0x00080000L +#define CP_STAT__MEQ_INDIRECTS_BUSY 0x00080000L +#define CP_STAT__MEQ_INDIRECT2_BUSY_MASK 0x00100000L +#define CP_STAT__MEQ_INDIRECT2_BUSY 0x00100000L +#define CP_STAT__MIU_WC_STALL_MASK 0x00200000L +#define CP_STAT__MIU_WC_STALL 0x00200000L +#define CP_STAT__CP_NRT_BUSY_MASK 0x00400000L +#define CP_STAT__CP_NRT_BUSY 0x00400000L +#define CP_STAT___3D_BUSY_MASK 0x00800000L +#define CP_STAT___3D_BUSY 0x00800000L +#define CP_STAT__ME_BUSY_MASK 0x04000000L +#define CP_STAT__ME_BUSY 0x04000000L +#define CP_STAT__ME_WC_BUSY_MASK 0x20000000L +#define CP_STAT__ME_WC_BUSY 0x20000000L +#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY_MASK 0x40000000L +#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY 0x40000000L +#define CP_STAT__CP_BUSY_MASK 0x80000000L +#define CP_STAT__CP_BUSY 0x80000000L + +// BIOS_0_SCRATCH +#define BIOS_0_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_1_SCRATCH +#define BIOS_1_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_2_SCRATCH +#define BIOS_2_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_3_SCRATCH +#define BIOS_3_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_4_SCRATCH +#define BIOS_4_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_5_SCRATCH +#define BIOS_5_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_6_SCRATCH +#define BIOS_6_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_7_SCRATCH +#define BIOS_7_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_8_SCRATCH +#define BIOS_8_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_9_SCRATCH +#define BIOS_9_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_10_SCRATCH +#define BIOS_10_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_11_SCRATCH +#define BIOS_11_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_12_SCRATCH +#define BIOS_12_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_13_SCRATCH +#define BIOS_13_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_14_SCRATCH +#define BIOS_14_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_15_SCRATCH +#define BIOS_15_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// COHER_SIZE_PM4 +#define COHER_SIZE_PM4__SIZE_MASK 0xffffffffL + +// COHER_BASE_PM4 +#define COHER_BASE_PM4__BASE_MASK 0xffffffffL + +// COHER_STATUS_PM4 +#define COHER_STATUS_PM4__MATCHING_CONTEXTS_MASK 0x000000ffL +#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA_MASK 0x00000100L +#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA 0x00000100L +#define COHER_STATUS_PM4__DEST_BASE_0_ENA_MASK 0x00000200L +#define COHER_STATUS_PM4__DEST_BASE_0_ENA 0x00000200L +#define COHER_STATUS_PM4__DEST_BASE_1_ENA_MASK 0x00000400L +#define COHER_STATUS_PM4__DEST_BASE_1_ENA 0x00000400L +#define COHER_STATUS_PM4__DEST_BASE_2_ENA_MASK 0x00000800L +#define COHER_STATUS_PM4__DEST_BASE_2_ENA 0x00000800L +#define COHER_STATUS_PM4__DEST_BASE_3_ENA_MASK 0x00001000L +#define COHER_STATUS_PM4__DEST_BASE_3_ENA 0x00001000L +#define COHER_STATUS_PM4__DEST_BASE_4_ENA_MASK 0x00002000L +#define COHER_STATUS_PM4__DEST_BASE_4_ENA 0x00002000L +#define COHER_STATUS_PM4__DEST_BASE_5_ENA_MASK 0x00004000L +#define COHER_STATUS_PM4__DEST_BASE_5_ENA 0x00004000L +#define COHER_STATUS_PM4__DEST_BASE_6_ENA_MASK 0x00008000L +#define COHER_STATUS_PM4__DEST_BASE_6_ENA 0x00008000L +#define COHER_STATUS_PM4__DEST_BASE_7_ENA_MASK 0x00010000L +#define COHER_STATUS_PM4__DEST_BASE_7_ENA 0x00010000L +#define COHER_STATUS_PM4__RB_COLOR_INFO_ENA_MASK 0x00020000L +#define COHER_STATUS_PM4__RB_COLOR_INFO_ENA 0x00020000L +#define COHER_STATUS_PM4__TC_ACTION_ENA_MASK 0x02000000L +#define COHER_STATUS_PM4__TC_ACTION_ENA 0x02000000L +#define COHER_STATUS_PM4__STATUS_MASK 0x80000000L +#define COHER_STATUS_PM4__STATUS 0x80000000L + +// COHER_SIZE_HOST +#define COHER_SIZE_HOST__SIZE_MASK 0xffffffffL + +// COHER_BASE_HOST +#define COHER_BASE_HOST__BASE_MASK 0xffffffffL + +// COHER_STATUS_HOST +#define COHER_STATUS_HOST__MATCHING_CONTEXTS_MASK 0x000000ffL +#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA_MASK 0x00000100L +#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA 0x00000100L +#define COHER_STATUS_HOST__DEST_BASE_0_ENA_MASK 0x00000200L +#define COHER_STATUS_HOST__DEST_BASE_0_ENA 0x00000200L +#define COHER_STATUS_HOST__DEST_BASE_1_ENA_MASK 0x00000400L +#define COHER_STATUS_HOST__DEST_BASE_1_ENA 0x00000400L +#define COHER_STATUS_HOST__DEST_BASE_2_ENA_MASK 0x00000800L +#define COHER_STATUS_HOST__DEST_BASE_2_ENA 0x00000800L +#define COHER_STATUS_HOST__DEST_BASE_3_ENA_MASK 0x00001000L +#define COHER_STATUS_HOST__DEST_BASE_3_ENA 0x00001000L +#define COHER_STATUS_HOST__DEST_BASE_4_ENA_MASK 0x00002000L +#define COHER_STATUS_HOST__DEST_BASE_4_ENA 0x00002000L +#define COHER_STATUS_HOST__DEST_BASE_5_ENA_MASK 0x00004000L +#define COHER_STATUS_HOST__DEST_BASE_5_ENA 0x00004000L +#define COHER_STATUS_HOST__DEST_BASE_6_ENA_MASK 0x00008000L +#define COHER_STATUS_HOST__DEST_BASE_6_ENA 0x00008000L +#define COHER_STATUS_HOST__DEST_BASE_7_ENA_MASK 0x00010000L +#define COHER_STATUS_HOST__DEST_BASE_7_ENA 0x00010000L +#define COHER_STATUS_HOST__RB_COLOR_INFO_ENA_MASK 0x00020000L +#define COHER_STATUS_HOST__RB_COLOR_INFO_ENA 0x00020000L +#define COHER_STATUS_HOST__TC_ACTION_ENA_MASK 0x02000000L +#define COHER_STATUS_HOST__TC_ACTION_ENA 0x02000000L +#define COHER_STATUS_HOST__STATUS_MASK 0x80000000L +#define COHER_STATUS_HOST__STATUS 0x80000000L + +// COHER_DEST_BASE_0 +#define COHER_DEST_BASE_0__DEST_BASE_0_MASK 0xfffff000L + +// COHER_DEST_BASE_1 +#define COHER_DEST_BASE_1__DEST_BASE_1_MASK 0xfffff000L + +// COHER_DEST_BASE_2 +#define COHER_DEST_BASE_2__DEST_BASE_2_MASK 0xfffff000L + +// COHER_DEST_BASE_3 +#define COHER_DEST_BASE_3__DEST_BASE_3_MASK 0xfffff000L + +// COHER_DEST_BASE_4 +#define COHER_DEST_BASE_4__DEST_BASE_4_MASK 0xfffff000L + +// COHER_DEST_BASE_5 +#define COHER_DEST_BASE_5__DEST_BASE_5_MASK 0xfffff000L + +// COHER_DEST_BASE_6 +#define COHER_DEST_BASE_6__DEST_BASE_6_MASK 0xfffff000L + +// COHER_DEST_BASE_7 +#define COHER_DEST_BASE_7__DEST_BASE_7_MASK 0xfffff000L + +// RB_SURFACE_INFO +#define RB_SURFACE_INFO__SURFACE_PITCH_MASK 0x00003fffL +#define RB_SURFACE_INFO__MSAA_SAMPLES_MASK 0x0000c000L + +// RB_COLOR_INFO +#define RB_COLOR_INFO__COLOR_FORMAT_MASK 0x0000000fL +#define RB_COLOR_INFO__COLOR_ROUND_MODE_MASK 0x00000030L +#define RB_COLOR_INFO__COLOR_LINEAR_MASK 0x00000040L +#define RB_COLOR_INFO__COLOR_LINEAR 0x00000040L +#define RB_COLOR_INFO__COLOR_ENDIAN_MASK 0x00000180L +#define RB_COLOR_INFO__COLOR_SWAP_MASK 0x00000600L +#define RB_COLOR_INFO__COLOR_BASE_MASK 0xfffff000L + +// RB_DEPTH_INFO +#define RB_DEPTH_INFO__DEPTH_FORMAT_MASK 0x00000001L +#define RB_DEPTH_INFO__DEPTH_FORMAT 0x00000001L +#define RB_DEPTH_INFO__DEPTH_BASE_MASK 0xfffff000L + +// RB_STENCILREFMASK +#define RB_STENCILREFMASK__STENCILREF_MASK 0x000000ffL +#define RB_STENCILREFMASK__STENCILMASK_MASK 0x0000ff00L +#define RB_STENCILREFMASK__STENCILWRITEMASK_MASK 0x00ff0000L +#define RB_STENCILREFMASK__RESERVED0_MASK 0x01000000L +#define RB_STENCILREFMASK__RESERVED0 0x01000000L +#define RB_STENCILREFMASK__RESERVED1_MASK 0x02000000L +#define RB_STENCILREFMASK__RESERVED1 0x02000000L + +// RB_ALPHA_REF +#define RB_ALPHA_REF__ALPHA_REF_MASK 0xffffffffL + +// RB_COLOR_MASK +#define RB_COLOR_MASK__WRITE_RED_MASK 0x00000001L +#define RB_COLOR_MASK__WRITE_RED 0x00000001L +#define RB_COLOR_MASK__WRITE_GREEN_MASK 0x00000002L +#define RB_COLOR_MASK__WRITE_GREEN 0x00000002L +#define RB_COLOR_MASK__WRITE_BLUE_MASK 0x00000004L +#define RB_COLOR_MASK__WRITE_BLUE 0x00000004L +#define RB_COLOR_MASK__WRITE_ALPHA_MASK 0x00000008L +#define RB_COLOR_MASK__WRITE_ALPHA 0x00000008L +#define RB_COLOR_MASK__RESERVED2_MASK 0x00000010L +#define RB_COLOR_MASK__RESERVED2 0x00000010L +#define RB_COLOR_MASK__RESERVED3_MASK 0x00000020L +#define RB_COLOR_MASK__RESERVED3 0x00000020L + +// RB_BLEND_RED +#define RB_BLEND_RED__BLEND_RED_MASK 0x000000ffL + +// RB_BLEND_GREEN +#define RB_BLEND_GREEN__BLEND_GREEN_MASK 0x000000ffL + +// RB_BLEND_BLUE +#define RB_BLEND_BLUE__BLEND_BLUE_MASK 0x000000ffL + +// RB_BLEND_ALPHA +#define RB_BLEND_ALPHA__BLEND_ALPHA_MASK 0x000000ffL + +// RB_FOG_COLOR +#define RB_FOG_COLOR__FOG_RED_MASK 0x000000ffL +#define RB_FOG_COLOR__FOG_GREEN_MASK 0x0000ff00L +#define RB_FOG_COLOR__FOG_BLUE_MASK 0x00ff0000L + +// RB_STENCILREFMASK_BF +#define RB_STENCILREFMASK_BF__STENCILREF_BF_MASK 0x000000ffL +#define RB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0x0000ff00L +#define RB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0x00ff0000L +#define RB_STENCILREFMASK_BF__RESERVED4_MASK 0x01000000L +#define RB_STENCILREFMASK_BF__RESERVED4 0x01000000L +#define RB_STENCILREFMASK_BF__RESERVED5_MASK 0x02000000L +#define RB_STENCILREFMASK_BF__RESERVED5 0x02000000L + +// RB_DEPTHCONTROL +#define RB_DEPTHCONTROL__STENCIL_ENABLE_MASK 0x00000001L +#define RB_DEPTHCONTROL__STENCIL_ENABLE 0x00000001L +#define RB_DEPTHCONTROL__Z_ENABLE_MASK 0x00000002L +#define RB_DEPTHCONTROL__Z_ENABLE 0x00000002L +#define RB_DEPTHCONTROL__Z_WRITE_ENABLE_MASK 0x00000004L +#define RB_DEPTHCONTROL__Z_WRITE_ENABLE 0x00000004L +#define RB_DEPTHCONTROL__EARLY_Z_ENABLE_MASK 0x00000008L +#define RB_DEPTHCONTROL__EARLY_Z_ENABLE 0x00000008L +#define RB_DEPTHCONTROL__ZFUNC_MASK 0x00000070L +#define RB_DEPTHCONTROL__BACKFACE_ENABLE_MASK 0x00000080L +#define RB_DEPTHCONTROL__BACKFACE_ENABLE 0x00000080L +#define RB_DEPTHCONTROL__STENCILFUNC_MASK 0x00000700L +#define RB_DEPTHCONTROL__STENCILFAIL_MASK 0x00003800L +#define RB_DEPTHCONTROL__STENCILZPASS_MASK 0x0001c000L +#define RB_DEPTHCONTROL__STENCILZFAIL_MASK 0x000e0000L +#define RB_DEPTHCONTROL__STENCILFUNC_BF_MASK 0x00700000L +#define RB_DEPTHCONTROL__STENCILFAIL_BF_MASK 0x03800000L +#define RB_DEPTHCONTROL__STENCILZPASS_BF_MASK 0x1c000000L +#define RB_DEPTHCONTROL__STENCILZFAIL_BF_MASK 0xe0000000L + +// RB_BLENDCONTROL +#define RB_BLENDCONTROL__COLOR_SRCBLEND_MASK 0x0000001fL +#define RB_BLENDCONTROL__COLOR_COMB_FCN_MASK 0x000000e0L +#define RB_BLENDCONTROL__COLOR_DESTBLEND_MASK 0x00001f00L +#define RB_BLENDCONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L +#define RB_BLENDCONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L +#define RB_BLENDCONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L +#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE_MASK 0x20000000L +#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE 0x20000000L +#define RB_BLENDCONTROL__BLEND_FORCE_MASK 0x40000000L +#define RB_BLENDCONTROL__BLEND_FORCE 0x40000000L + +// RB_COLORCONTROL +#define RB_COLORCONTROL__ALPHA_FUNC_MASK 0x00000007L +#define RB_COLORCONTROL__ALPHA_TEST_ENABLE_MASK 0x00000008L +#define RB_COLORCONTROL__ALPHA_TEST_ENABLE 0x00000008L +#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE_MASK 0x00000010L +#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE 0x00000010L +#define RB_COLORCONTROL__BLEND_DISABLE_MASK 0x00000020L +#define RB_COLORCONTROL__BLEND_DISABLE 0x00000020L +#define RB_COLORCONTROL__FOG_ENABLE_MASK 0x00000040L +#define RB_COLORCONTROL__FOG_ENABLE 0x00000040L +#define RB_COLORCONTROL__VS_EXPORTS_FOG_MASK 0x00000080L +#define RB_COLORCONTROL__VS_EXPORTS_FOG 0x00000080L +#define RB_COLORCONTROL__ROP_CODE_MASK 0x00000f00L +#define RB_COLORCONTROL__DITHER_MODE_MASK 0x00003000L +#define RB_COLORCONTROL__DITHER_TYPE_MASK 0x0000c000L +#define RB_COLORCONTROL__PIXEL_FOG_MASK 0x00010000L +#define RB_COLORCONTROL__PIXEL_FOG 0x00010000L +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET0_MASK 0x03000000L +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET1_MASK 0x0c000000L +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET2_MASK 0x30000000L +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET3_MASK 0xc0000000L + +// RB_MODECONTROL +#define RB_MODECONTROL__EDRAM_MODE_MASK 0x00000007L + +// RB_COLOR_DEST_MASK +#define RB_COLOR_DEST_MASK__COLOR_DEST_MASK_MASK 0xffffffffL + +// RB_COPY_CONTROL +#define RB_COPY_CONTROL__COPY_SAMPLE_SELECT_MASK 0x00000007L +#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x00000008L +#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE 0x00000008L +#define RB_COPY_CONTROL__CLEAR_MASK_MASK 0x000000f0L + +// RB_COPY_DEST_BASE +#define RB_COPY_DEST_BASE__COPY_DEST_BASE_MASK 0xfffff000L + +// RB_COPY_DEST_PITCH +#define RB_COPY_DEST_PITCH__COPY_DEST_PITCH_MASK 0x000001ffL + +// RB_COPY_DEST_INFO +#define RB_COPY_DEST_INFO__COPY_DEST_ENDIAN_MASK 0x00000007L +#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR_MASK 0x00000008L +#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR 0x00000008L +#define RB_COPY_DEST_INFO__COPY_DEST_FORMAT_MASK 0x000000f0L +#define RB_COPY_DEST_INFO__COPY_DEST_SWAP_MASK 0x00000300L +#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_MODE_MASK 0x00000c00L +#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_TYPE_MASK 0x00003000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED_MASK 0x00004000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED 0x00004000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN_MASK 0x00008000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN 0x00008000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE_MASK 0x00010000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE 0x00010000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA_MASK 0x00020000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA 0x00020000L + +// RB_COPY_DEST_PIXEL_OFFSET +#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_X_MASK 0x00001fffL +#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_Y_MASK 0x03ffe000L + +// RB_DEPTH_CLEAR +#define RB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xffffffffL + +// RB_SAMPLE_COUNT_CTL +#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT_MASK 0x00000001L +#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT 0x00000001L +#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT_MASK 0x00000002L +#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT 0x00000002L + +// RB_SAMPLE_COUNT_ADDR +#define RB_SAMPLE_COUNT_ADDR__SAMPLE_COUNT_ADDR_MASK 0xffffffffL + +// RB_BC_CONTROL +#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE_MASK 0x00000001L +#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE 0x00000001L +#define RB_BC_CONTROL__ACCUM_TIMEOUT_SELECT_MASK 0x00000006L +#define RB_BC_CONTROL__DISABLE_EDRAM_CAM_MASK 0x00000008L +#define RB_BC_CONTROL__DISABLE_EDRAM_CAM 0x00000008L +#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK 0x00000010L +#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH 0x00000010L +#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP_MASK 0x00000020L +#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP 0x00000020L +#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP_MASK 0x00000040L +#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP 0x00000040L +#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE_MASK 0x00000080L +#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE 0x00000080L +#define RB_BC_CONTROL__AZ_THROTTLE_COUNT_MASK 0x00001f00L +#define RB_BC_CONTROL__ENABLE_CRC_UPDATE_MASK 0x00004000L +#define RB_BC_CONTROL__ENABLE_CRC_UPDATE 0x00004000L +#define RB_BC_CONTROL__CRC_MODE_MASK 0x00008000L +#define RB_BC_CONTROL__CRC_MODE 0x00008000L +#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS_MASK 0x00010000L +#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS 0x00010000L +#define RB_BC_CONTROL__DISABLE_ACCUM_MASK 0x00020000L +#define RB_BC_CONTROL__DISABLE_ACCUM 0x00020000L +#define RB_BC_CONTROL__ACCUM_ALLOC_MASK_MASK 0x003c0000L +#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE_MASK 0x00400000L +#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE 0x00400000L +#define RB_BC_CONTROL__ACCUM_DATA_FIFO_LIMIT_MASK 0x07800000L +#define RB_BC_CONTROL__MEM_EXPORT_TIMEOUT_SELECT_MASK 0x18000000L +#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE_MASK 0x20000000L +#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE 0x20000000L +#define RB_BC_CONTROL__CRC_SYSTEM_MASK 0x40000000L +#define RB_BC_CONTROL__CRC_SYSTEM 0x40000000L +#define RB_BC_CONTROL__RESERVED6_MASK 0x80000000L +#define RB_BC_CONTROL__RESERVED6 0x80000000L + +// RB_EDRAM_INFO +#define RB_EDRAM_INFO__EDRAM_SIZE_MASK 0x0000000fL +#define RB_EDRAM_INFO__EDRAM_MAPPING_MODE_MASK 0x00000030L +#define RB_EDRAM_INFO__EDRAM_RANGE_MASK 0xffffc000L + +// RB_CRC_RD_PORT +#define RB_CRC_RD_PORT__CRC_DATA_MASK 0xffffffffL + +// RB_CRC_CONTROL +#define RB_CRC_CONTROL__CRC_RD_ADVANCE_MASK 0x00000001L +#define RB_CRC_CONTROL__CRC_RD_ADVANCE 0x00000001L + +// RB_CRC_MASK +#define RB_CRC_MASK__CRC_MASK_MASK 0xffffffffL + +// RB_PERFCOUNTER0_SELECT +#define RB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// RB_PERFCOUNTER0_LOW +#define RB_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// RB_PERFCOUNTER0_HI +#define RB_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// RB_TOTAL_SAMPLES +#define RB_TOTAL_SAMPLES__TOTAL_SAMPLES_MASK 0xffffffffL + +// RB_ZPASS_SAMPLES +#define RB_ZPASS_SAMPLES__ZPASS_SAMPLES_MASK 0xffffffffL + +// RB_ZFAIL_SAMPLES +#define RB_ZFAIL_SAMPLES__ZFAIL_SAMPLES_MASK 0xffffffffL + +// RB_SFAIL_SAMPLES +#define RB_SFAIL_SAMPLES__SFAIL_SAMPLES_MASK 0xffffffffL + +// RB_DEBUG_0 +#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL_MASK 0x00000001L +#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL 0x00000001L +#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL_MASK 0x00000002L +#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL 0x00000002L +#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL_MASK 0x00000004L +#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL 0x00000004L +#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL_MASK 0x00000008L +#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL 0x00000008L +#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL_MASK 0x00000010L +#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL 0x00000010L +#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL_MASK 0x00000020L +#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL 0x00000020L +#define RB_DEBUG_0__RDREQ_Z1_FULL_MASK 0x00000040L +#define RB_DEBUG_0__RDREQ_Z1_FULL 0x00000040L +#define RB_DEBUG_0__RDREQ_Z0_FULL_MASK 0x00000080L +#define RB_DEBUG_0__RDREQ_Z0_FULL 0x00000080L +#define RB_DEBUG_0__RDREQ_C1_FULL_MASK 0x00000100L +#define RB_DEBUG_0__RDREQ_C1_FULL 0x00000100L +#define RB_DEBUG_0__RDREQ_C0_FULL_MASK 0x00000200L +#define RB_DEBUG_0__RDREQ_C0_FULL 0x00000200L +#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL_MASK 0x00000400L +#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL 0x00000400L +#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL_MASK 0x00000800L +#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL 0x00000800L +#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL_MASK 0x00001000L +#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL 0x00001000L +#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL_MASK 0x00002000L +#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL 0x00002000L +#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL_MASK 0x00004000L +#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL 0x00004000L +#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL_MASK 0x00008000L +#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL 0x00008000L +#define RB_DEBUG_0__WRREQ_Z1_FULL_MASK 0x00010000L +#define RB_DEBUG_0__WRREQ_Z1_FULL 0x00010000L +#define RB_DEBUG_0__WRREQ_Z0_FULL_MASK 0x00020000L +#define RB_DEBUG_0__WRREQ_Z0_FULL 0x00020000L +#define RB_DEBUG_0__WRREQ_C1_FULL_MASK 0x00040000L +#define RB_DEBUG_0__WRREQ_C1_FULL 0x00040000L +#define RB_DEBUG_0__WRREQ_C0_FULL_MASK 0x00080000L +#define RB_DEBUG_0__WRREQ_C0_FULL 0x00080000L +#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL_MASK 0x00100000L +#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL 0x00100000L +#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL_MASK 0x00200000L +#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL 0x00200000L +#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL_MASK 0x00400000L +#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL 0x00400000L +#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL_MASK 0x00800000L +#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL 0x00800000L +#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL_MASK 0x01000000L +#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL 0x01000000L +#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL_MASK 0x02000000L +#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL 0x02000000L +#define RB_DEBUG_0__C_SX_LAT_FULL_MASK 0x04000000L +#define RB_DEBUG_0__C_SX_LAT_FULL 0x04000000L +#define RB_DEBUG_0__C_SX_CMD_FULL_MASK 0x08000000L +#define RB_DEBUG_0__C_SX_CMD_FULL 0x08000000L +#define RB_DEBUG_0__C_EZ_TILE_FULL_MASK 0x10000000L +#define RB_DEBUG_0__C_EZ_TILE_FULL 0x10000000L +#define RB_DEBUG_0__C_REQ_FULL_MASK 0x20000000L +#define RB_DEBUG_0__C_REQ_FULL 0x20000000L +#define RB_DEBUG_0__C_MASK_FULL_MASK 0x40000000L +#define RB_DEBUG_0__C_MASK_FULL 0x40000000L +#define RB_DEBUG_0__EZ_INFSAMP_FULL_MASK 0x80000000L +#define RB_DEBUG_0__EZ_INFSAMP_FULL 0x80000000L + +// RB_DEBUG_1 +#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY_MASK 0x00000001L +#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY 0x00000001L +#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY_MASK 0x00000002L +#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY 0x00000002L +#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY_MASK 0x00000004L +#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY 0x00000004L +#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY_MASK 0x00000008L +#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY 0x00000008L +#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY_MASK 0x00000010L +#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY 0x00000010L +#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY_MASK 0x00000020L +#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY 0x00000020L +#define RB_DEBUG_1__RDREQ_Z1_EMPTY_MASK 0x00000040L +#define RB_DEBUG_1__RDREQ_Z1_EMPTY 0x00000040L +#define RB_DEBUG_1__RDREQ_Z0_EMPTY_MASK 0x00000080L +#define RB_DEBUG_1__RDREQ_Z0_EMPTY 0x00000080L +#define RB_DEBUG_1__RDREQ_C1_EMPTY_MASK 0x00000100L +#define RB_DEBUG_1__RDREQ_C1_EMPTY 0x00000100L +#define RB_DEBUG_1__RDREQ_C0_EMPTY_MASK 0x00000200L +#define RB_DEBUG_1__RDREQ_C0_EMPTY 0x00000200L +#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY_MASK 0x00000400L +#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY 0x00000400L +#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY_MASK 0x00000800L +#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY 0x00000800L +#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY_MASK 0x00001000L +#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY 0x00001000L +#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY_MASK 0x00002000L +#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY 0x00002000L +#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY_MASK 0x00004000L +#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY 0x00004000L +#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY_MASK 0x00008000L +#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY 0x00008000L +#define RB_DEBUG_1__WRREQ_Z1_EMPTY_MASK 0x00010000L +#define RB_DEBUG_1__WRREQ_Z1_EMPTY 0x00010000L +#define RB_DEBUG_1__WRREQ_Z0_EMPTY_MASK 0x00020000L +#define RB_DEBUG_1__WRREQ_Z0_EMPTY 0x00020000L +#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY_MASK 0x00040000L +#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY 0x00040000L +#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY_MASK 0x00080000L +#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY 0x00080000L +#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY_MASK 0x00100000L +#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY 0x00100000L +#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY_MASK 0x00200000L +#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY 0x00200000L +#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY_MASK 0x00400000L +#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY 0x00400000L +#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY_MASK 0x00800000L +#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY 0x00800000L +#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY_MASK 0x01000000L +#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY 0x01000000L +#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY_MASK 0x02000000L +#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY 0x02000000L +#define RB_DEBUG_1__C_SX_LAT_EMPTY_MASK 0x04000000L +#define RB_DEBUG_1__C_SX_LAT_EMPTY 0x04000000L +#define RB_DEBUG_1__C_SX_CMD_EMPTY_MASK 0x08000000L +#define RB_DEBUG_1__C_SX_CMD_EMPTY 0x08000000L +#define RB_DEBUG_1__C_EZ_TILE_EMPTY_MASK 0x10000000L +#define RB_DEBUG_1__C_EZ_TILE_EMPTY 0x10000000L +#define RB_DEBUG_1__C_REQ_EMPTY_MASK 0x20000000L +#define RB_DEBUG_1__C_REQ_EMPTY 0x20000000L +#define RB_DEBUG_1__C_MASK_EMPTY_MASK 0x40000000L +#define RB_DEBUG_1__C_MASK_EMPTY 0x40000000L +#define RB_DEBUG_1__EZ_INFSAMP_EMPTY_MASK 0x80000000L +#define RB_DEBUG_1__EZ_INFSAMP_EMPTY 0x80000000L + +// RB_DEBUG_2 +#define RB_DEBUG_2__TILE_FIFO_COUNT_MASK 0x0000000fL +#define RB_DEBUG_2__SX_LAT_FIFO_COUNT_MASK 0x000007f0L +#define RB_DEBUG_2__MEM_EXPORT_FLAG_MASK 0x00000800L +#define RB_DEBUG_2__MEM_EXPORT_FLAG 0x00000800L +#define RB_DEBUG_2__SYSMEM_BLEND_FLAG_MASK 0x00001000L +#define RB_DEBUG_2__SYSMEM_BLEND_FLAG 0x00001000L +#define RB_DEBUG_2__CURRENT_TILE_EVENT_MASK 0x00002000L +#define RB_DEBUG_2__CURRENT_TILE_EVENT 0x00002000L +#define RB_DEBUG_2__EZ_INFTILE_FULL_MASK 0x00004000L +#define RB_DEBUG_2__EZ_INFTILE_FULL 0x00004000L +#define RB_DEBUG_2__EZ_MASK_LOWER_FULL_MASK 0x00008000L +#define RB_DEBUG_2__EZ_MASK_LOWER_FULL 0x00008000L +#define RB_DEBUG_2__EZ_MASK_UPPER_FULL_MASK 0x00010000L +#define RB_DEBUG_2__EZ_MASK_UPPER_FULL 0x00010000L +#define RB_DEBUG_2__Z0_MASK_FULL_MASK 0x00020000L +#define RB_DEBUG_2__Z0_MASK_FULL 0x00020000L +#define RB_DEBUG_2__Z1_MASK_FULL_MASK 0x00040000L +#define RB_DEBUG_2__Z1_MASK_FULL 0x00040000L +#define RB_DEBUG_2__Z0_REQ_FULL_MASK 0x00080000L +#define RB_DEBUG_2__Z0_REQ_FULL 0x00080000L +#define RB_DEBUG_2__Z1_REQ_FULL_MASK 0x00100000L +#define RB_DEBUG_2__Z1_REQ_FULL 0x00100000L +#define RB_DEBUG_2__Z_SAMP_FULL_MASK 0x00200000L +#define RB_DEBUG_2__Z_SAMP_FULL 0x00200000L +#define RB_DEBUG_2__Z_TILE_FULL_MASK 0x00400000L +#define RB_DEBUG_2__Z_TILE_FULL 0x00400000L +#define RB_DEBUG_2__EZ_INFTILE_EMPTY_MASK 0x00800000L +#define RB_DEBUG_2__EZ_INFTILE_EMPTY 0x00800000L +#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY_MASK 0x01000000L +#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY 0x01000000L +#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY_MASK 0x02000000L +#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY 0x02000000L +#define RB_DEBUG_2__Z0_MASK_EMPTY_MASK 0x04000000L +#define RB_DEBUG_2__Z0_MASK_EMPTY 0x04000000L +#define RB_DEBUG_2__Z1_MASK_EMPTY_MASK 0x08000000L +#define RB_DEBUG_2__Z1_MASK_EMPTY 0x08000000L +#define RB_DEBUG_2__Z0_REQ_EMPTY_MASK 0x10000000L +#define RB_DEBUG_2__Z0_REQ_EMPTY 0x10000000L +#define RB_DEBUG_2__Z1_REQ_EMPTY_MASK 0x20000000L +#define RB_DEBUG_2__Z1_REQ_EMPTY 0x20000000L +#define RB_DEBUG_2__Z_SAMP_EMPTY_MASK 0x40000000L +#define RB_DEBUG_2__Z_SAMP_EMPTY 0x40000000L +#define RB_DEBUG_2__Z_TILE_EMPTY_MASK 0x80000000L +#define RB_DEBUG_2__Z_TILE_EMPTY 0x80000000L + +// RB_DEBUG_3 +#define RB_DEBUG_3__ACCUM_VALID_MASK 0x0000000fL +#define RB_DEBUG_3__ACCUM_FLUSHING_MASK 0x000000f0L +#define RB_DEBUG_3__ACCUM_WRITE_CLEAN_COUNT_MASK 0x00003f00L +#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID_MASK 0x00004000L +#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID 0x00004000L +#define RB_DEBUG_3__ACCUM_DATA_FIFO_CNT_MASK 0x00078000L +#define RB_DEBUG_3__SHD_FULL_MASK 0x00080000L +#define RB_DEBUG_3__SHD_FULL 0x00080000L +#define RB_DEBUG_3__SHD_EMPTY_MASK 0x00100000L +#define RB_DEBUG_3__SHD_EMPTY 0x00100000L +#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY_MASK 0x00200000L +#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY 0x00200000L +#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY_MASK 0x00400000L +#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY 0x00400000L +#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL_MASK 0x00800000L +#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL 0x00800000L +#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL_MASK 0x01000000L +#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL 0x01000000L +#define RB_DEBUG_3__ZEXP_LOWER_EMPTY_MASK 0x02000000L +#define RB_DEBUG_3__ZEXP_LOWER_EMPTY 0x02000000L +#define RB_DEBUG_3__ZEXP_UPPER_EMPTY_MASK 0x04000000L +#define RB_DEBUG_3__ZEXP_UPPER_EMPTY 0x04000000L +#define RB_DEBUG_3__ZEXP_LOWER_FULL_MASK 0x08000000L +#define RB_DEBUG_3__ZEXP_LOWER_FULL 0x08000000L +#define RB_DEBUG_3__ZEXP_UPPER_FULL_MASK 0x10000000L +#define RB_DEBUG_3__ZEXP_UPPER_FULL 0x10000000L + +// RB_DEBUG_4 +#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG_MASK 0x00000001L +#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG 0x00000001L +#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG_MASK 0x00000002L +#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG 0x00000002L +#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG_MASK 0x00000004L +#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG 0x00000004L +#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG_MASK 0x00000008L +#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG 0x00000008L +#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY_MASK 0x00000010L +#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY 0x00000010L +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY_MASK 0x00000020L +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY 0x00000020L +#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL_MASK 0x00000040L +#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL 0x00000040L +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL_MASK 0x00000080L +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL 0x00000080L +#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW_MASK 0x00000100L +#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW 0x00000100L +#define RB_DEBUG_4__CONTEXT_COUNT_DEBUG_MASK 0x00001e00L + +// RB_FLAG_CONTROL +#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR_MASK 0x00000001L +#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR 0x00000001L + +// RB_BC_SPARES +#define RB_BC_SPARES__RESERVED_MASK 0xffffffffL + +// BC_DUMMY_CRAYRB_ENUMS +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_FORMAT_MASK 0x0000003fL +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP_MASK 0x00000040L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP 0x00000040L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_ARRAY_MASK 0x00000180L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_ARRAY_MASK 0x00000600L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_COLOR_FORMAT_MASK 0x0001f800L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_NUMBER_MASK 0x000e0000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_FORMAT_MASK 0x03f00000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING_MASK 0x04000000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING 0x04000000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_ARRAY_MASK 0x18000000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK 0xe0000000L + +// BC_DUMMY_CRAYRB_MOREENUMS +#define BC_DUMMY_CRAYRB_MOREENUMS__DUMMY_CRAYRB_COLORARRAYX_MASK 0x00000003L + +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_offset.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_offset.h new file mode 100644 index 000000000000..ec7c7e126612 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_offset.h @@ -0,0 +1,590 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _yamato_OFFSET_HEADER +#define _yamato_OFFSET_HEADER + +// Registers from PA block + +#define mmPA_CL_VPORT_XSCALE 0x210F +#define mmPA_CL_VPORT_XOFFSET 0x2110 +#define mmPA_CL_VPORT_YSCALE 0x2111 +#define mmPA_CL_VPORT_YOFFSET 0x2112 +#define mmPA_CL_VPORT_ZSCALE 0x2113 +#define mmPA_CL_VPORT_ZOFFSET 0x2114 +#define mmPA_CL_VTE_CNTL 0x2206 +#define mmPA_CL_CLIP_CNTL 0x2204 +#define mmPA_CL_GB_VERT_CLIP_ADJ 0x2303 +#define mmPA_CL_GB_VERT_DISC_ADJ 0x2304 +#define mmPA_CL_GB_HORZ_CLIP_ADJ 0x2305 +#define mmPA_CL_GB_HORZ_DISC_ADJ 0x2306 +#define mmPA_CL_ENHANCE 0x0C85 +#define mmPA_SC_ENHANCE 0x0CA5 +#define mmPA_SU_VTX_CNTL 0x2302 +#define mmPA_SU_POINT_SIZE 0x2280 +#define mmPA_SU_POINT_MINMAX 0x2281 +#define mmPA_SU_LINE_CNTL 0x2282 +#define mmPA_SU_FACE_DATA 0x0C86 +#define mmPA_SU_SC_MODE_CNTL 0x2205 +#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0x2380 +#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0x2381 +#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0x2382 +#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0x2383 +#define mmPA_SU_PERFCOUNTER0_SELECT 0x0C88 +#define mmPA_SU_PERFCOUNTER1_SELECT 0x0C89 +#define mmPA_SU_PERFCOUNTER2_SELECT 0x0C8A +#define mmPA_SU_PERFCOUNTER3_SELECT 0x0C8B +#define mmPA_SU_PERFCOUNTER0_LOW 0x0C8C +#define mmPA_SU_PERFCOUNTER0_HI 0x0C8D +#define mmPA_SU_PERFCOUNTER1_LOW 0x0C8E +#define mmPA_SU_PERFCOUNTER1_HI 0x0C8F +#define mmPA_SU_PERFCOUNTER2_LOW 0x0C90 +#define mmPA_SU_PERFCOUNTER2_HI 0x0C91 +#define mmPA_SU_PERFCOUNTER3_LOW 0x0C92 +#define mmPA_SU_PERFCOUNTER3_HI 0x0C93 +#define mmPA_SC_WINDOW_OFFSET 0x2080 +#define mmPA_SC_AA_CONFIG 0x2301 +#define mmPA_SC_AA_MASK 0x2312 +#define mmPA_SC_LINE_STIPPLE 0x2283 +#define mmPA_SC_LINE_CNTL 0x2300 +#define mmPA_SC_WINDOW_SCISSOR_TL 0x2081 +#define mmPA_SC_WINDOW_SCISSOR_BR 0x2082 +#define mmPA_SC_SCREEN_SCISSOR_TL 0x200E +#define mmPA_SC_SCREEN_SCISSOR_BR 0x200F +#define mmPA_SC_VIZ_QUERY 0x2293 +#define mmPA_SC_VIZ_QUERY_STATUS 0x0C44 +#define mmPA_SC_LINE_STIPPLE_STATE 0x0C40 +#define mmPA_SC_PERFCOUNTER0_SELECT 0x0C98 +#define mmPA_SC_PERFCOUNTER0_LOW 0x0C99 +#define mmPA_SC_PERFCOUNTER0_HI 0x0C9A +#define mmPA_CL_CNTL_STATUS 0x0C84 +#define mmPA_SU_CNTL_STATUS 0x0C94 +#define mmPA_SC_CNTL_STATUS 0x0CA4 +#define mmPA_SU_DEBUG_CNTL 0x0C80 +#define mmPA_SU_DEBUG_DATA 0x0C81 +#define mmPA_SC_DEBUG_CNTL 0x0C82 +#define mmPA_SC_DEBUG_DATA 0x0C83 + + +// Registers from VGT block + +#define mmGFX_COPY_STATE 0x21F4 +#define mmVGT_DRAW_INITIATOR 0x21FC +#define mmVGT_EVENT_INITIATOR 0x21F9 +#define mmVGT_DMA_BASE 0x21FA +#define mmVGT_DMA_SIZE 0x21FB +#define mmVGT_BIN_BASE 0x21FE +#define mmVGT_BIN_SIZE 0x21FF +#define mmVGT_CURRENT_BIN_ID_MIN 0x2207 +#define mmVGT_CURRENT_BIN_ID_MAX 0x2203 +#define mmVGT_IMMED_DATA 0x21FD +#define mmVGT_MAX_VTX_INDX 0x2100 +#define mmVGT_MIN_VTX_INDX 0x2101 +#define mmVGT_INDX_OFFSET 0x2102 +#define mmVGT_VERTEX_REUSE_BLOCK_CNTL 0x2316 +#define mmVGT_OUT_DEALLOC_CNTL 0x2317 +#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0x2103 +#define mmVGT_ENHANCE 0x2294 +#define mmVGT_VTX_VECT_EJECT_REG 0x0C2C +#define mmVGT_LAST_COPY_STATE 0x0C30 +#define mmVGT_DEBUG_CNTL 0x0C38 +#define mmVGT_DEBUG_DATA 0x0C39 +#define mmVGT_CNTL_STATUS 0x0C3C +#define mmVGT_CRC_SQ_DATA 0x0C3A +#define mmVGT_CRC_SQ_CTRL 0x0C3B +#define mmVGT_PERFCOUNTER0_SELECT 0x0C48 +#define mmVGT_PERFCOUNTER1_SELECT 0x0C49 +#define mmVGT_PERFCOUNTER2_SELECT 0x0C4A +#define mmVGT_PERFCOUNTER3_SELECT 0x0C4B +#define mmVGT_PERFCOUNTER0_LOW 0x0C4C +#define mmVGT_PERFCOUNTER1_LOW 0x0C4E +#define mmVGT_PERFCOUNTER2_LOW 0x0C50 +#define mmVGT_PERFCOUNTER3_LOW 0x0C52 +#define mmVGT_PERFCOUNTER0_HI 0x0C4D +#define mmVGT_PERFCOUNTER1_HI 0x0C4F +#define mmVGT_PERFCOUNTER2_HI 0x0C51 +#define mmVGT_PERFCOUNTER3_HI 0x0C53 + + +// Registers from TP block + +#define mmTC_CNTL_STATUS 0x0E00 +#define mmTCR_CHICKEN 0x0E02 +#define mmTCF_CHICKEN 0x0E03 +#define mmTCM_CHICKEN 0x0E04 +#define mmTCR_PERFCOUNTER0_SELECT 0x0E05 +#define mmTCR_PERFCOUNTER1_SELECT 0x0E08 +#define mmTCR_PERFCOUNTER0_HI 0x0E06 +#define mmTCR_PERFCOUNTER1_HI 0x0E09 +#define mmTCR_PERFCOUNTER0_LOW 0x0E07 +#define mmTCR_PERFCOUNTER1_LOW 0x0E0A +#define mmTP_TC_CLKGATE_CNTL 0x0E17 +#define mmTPC_CNTL_STATUS 0x0E18 +#define mmTPC_DEBUG0 0x0E19 +#define mmTPC_DEBUG1 0x0E1A +#define mmTPC_CHICKEN 0x0E1B +#define mmTP0_CNTL_STATUS 0x0E1C +#define mmTP0_DEBUG 0x0E1D +#define mmTP0_CHICKEN 0x0E1E +#define mmTP0_PERFCOUNTER0_SELECT 0x0E1F +#define mmTP0_PERFCOUNTER0_HI 0x0E20 +#define mmTP0_PERFCOUNTER0_LOW 0x0E21 +#define mmTP0_PERFCOUNTER1_SELECT 0x0E22 +#define mmTP0_PERFCOUNTER1_HI 0x0E23 +#define mmTP0_PERFCOUNTER1_LOW 0x0E24 +#define mmTCM_PERFCOUNTER0_SELECT 0x0E54 +#define mmTCM_PERFCOUNTER1_SELECT 0x0E57 +#define mmTCM_PERFCOUNTER0_HI 0x0E55 +#define mmTCM_PERFCOUNTER1_HI 0x0E58 +#define mmTCM_PERFCOUNTER0_LOW 0x0E56 +#define mmTCM_PERFCOUNTER1_LOW 0x0E59 +#define mmTCF_PERFCOUNTER0_SELECT 0x0E5A +#define mmTCF_PERFCOUNTER1_SELECT 0x0E5D +#define mmTCF_PERFCOUNTER2_SELECT 0x0E60 +#define mmTCF_PERFCOUNTER3_SELECT 0x0E63 +#define mmTCF_PERFCOUNTER4_SELECT 0x0E66 +#define mmTCF_PERFCOUNTER5_SELECT 0x0E69 +#define mmTCF_PERFCOUNTER6_SELECT 0x0E6C +#define mmTCF_PERFCOUNTER7_SELECT 0x0E6F +#define mmTCF_PERFCOUNTER8_SELECT 0x0E72 +#define mmTCF_PERFCOUNTER9_SELECT 0x0E75 +#define mmTCF_PERFCOUNTER10_SELECT 0x0E78 +#define mmTCF_PERFCOUNTER11_SELECT 0x0E7B +#define mmTCF_PERFCOUNTER0_HI 0x0E5B +#define mmTCF_PERFCOUNTER1_HI 0x0E5E +#define mmTCF_PERFCOUNTER2_HI 0x0E61 +#define mmTCF_PERFCOUNTER3_HI 0x0E64 +#define mmTCF_PERFCOUNTER4_HI 0x0E67 +#define mmTCF_PERFCOUNTER5_HI 0x0E6A +#define mmTCF_PERFCOUNTER6_HI 0x0E6D +#define mmTCF_PERFCOUNTER7_HI 0x0E70 +#define mmTCF_PERFCOUNTER8_HI 0x0E73 +#define mmTCF_PERFCOUNTER9_HI 0x0E76 +#define mmTCF_PERFCOUNTER10_HI 0x0E79 +#define mmTCF_PERFCOUNTER11_HI 0x0E7C +#define mmTCF_PERFCOUNTER0_LOW 0x0E5C +#define mmTCF_PERFCOUNTER1_LOW 0x0E5F +#define mmTCF_PERFCOUNTER2_LOW 0x0E62 +#define mmTCF_PERFCOUNTER3_LOW 0x0E65 +#define mmTCF_PERFCOUNTER4_LOW 0x0E68 +#define mmTCF_PERFCOUNTER5_LOW 0x0E6B +#define mmTCF_PERFCOUNTER6_LOW 0x0E6E +#define mmTCF_PERFCOUNTER7_LOW 0x0E71 +#define mmTCF_PERFCOUNTER8_LOW 0x0E74 +#define mmTCF_PERFCOUNTER9_LOW 0x0E77 +#define mmTCF_PERFCOUNTER10_LOW 0x0E7A +#define mmTCF_PERFCOUNTER11_LOW 0x0E7D +#define mmTCF_DEBUG 0x0EC0 +#define mmTCA_FIFO_DEBUG 0x0EC1 +#define mmTCA_PROBE_DEBUG 0x0EC2 +#define mmTCA_TPC_DEBUG 0x0EC3 +#define mmTCB_CORE_DEBUG 0x0EC4 +#define mmTCB_TAG0_DEBUG 0x0EC5 +#define mmTCB_TAG1_DEBUG 0x0EC6 +#define mmTCB_TAG2_DEBUG 0x0EC7 +#define mmTCB_TAG3_DEBUG 0x0EC8 +#define mmTCB_FETCH_GEN_SECTOR_WALKER0_DEBUG 0x0EC9 +#define mmTCB_FETCH_GEN_WALKER_DEBUG 0x0ECB +#define mmTCB_FETCH_GEN_PIPE0_DEBUG 0x0ECC +#define mmTCD_INPUT0_DEBUG 0x0ED0 +#define mmTCD_DEGAMMA_DEBUG 0x0ED4 +#define mmTCD_DXTMUX_SCTARB_DEBUG 0x0ED5 +#define mmTCD_DXTC_ARB_DEBUG 0x0ED6 +#define mmTCD_STALLS_DEBUG 0x0ED7 +#define mmTCO_STALLS_DEBUG 0x0EE0 +#define mmTCO_QUAD0_DEBUG0 0x0EE1 +#define mmTCO_QUAD0_DEBUG1 0x0EE2 + + +// Registers from TC block + + + +// Registers from SQ block + +#define mmSQ_GPR_MANAGEMENT 0x0D00 +#define mmSQ_FLOW_CONTROL 0x0D01 +#define mmSQ_INST_STORE_MANAGMENT 0x0D02 +#define mmSQ_RESOURCE_MANAGMENT 0x0D03 +#define mmSQ_EO_RT 0x0D04 +#define mmSQ_DEBUG_MISC 0x0D05 +#define mmSQ_ACTIVITY_METER_CNTL 0x0D06 +#define mmSQ_ACTIVITY_METER_STATUS 0x0D07 +#define mmSQ_INPUT_ARB_PRIORITY 0x0D08 +#define mmSQ_THREAD_ARB_PRIORITY 0x0D09 +#define mmSQ_VS_WATCHDOG_TIMER 0x0D0A +#define mmSQ_PS_WATCHDOG_TIMER 0x0D0B +#define mmSQ_INT_CNTL 0x0D34 +#define mmSQ_INT_STATUS 0x0D35 +#define mmSQ_INT_ACK 0x0D36 +#define mmSQ_DEBUG_INPUT_FSM 0x0DAE +#define mmSQ_DEBUG_CONST_MGR_FSM 0x0DAF +#define mmSQ_DEBUG_TP_FSM 0x0DB0 +#define mmSQ_DEBUG_FSM_ALU_0 0x0DB1 +#define mmSQ_DEBUG_FSM_ALU_1 0x0DB2 +#define mmSQ_DEBUG_EXP_ALLOC 0x0DB3 +#define mmSQ_DEBUG_PTR_BUFF 0x0DB4 +#define mmSQ_DEBUG_GPR_VTX 0x0DB5 +#define mmSQ_DEBUG_GPR_PIX 0x0DB6 +#define mmSQ_DEBUG_TB_STATUS_SEL 0x0DB7 +#define mmSQ_DEBUG_VTX_TB_0 0x0DB8 +#define mmSQ_DEBUG_VTX_TB_1 0x0DB9 +#define mmSQ_DEBUG_VTX_TB_STATUS_REG 0x0DBA +#define mmSQ_DEBUG_VTX_TB_STATE_MEM 0x0DBB +#define mmSQ_DEBUG_PIX_TB_0 0x0DBC +#define mmSQ_DEBUG_PIX_TB_STATUS_REG_0 0x0DBD +#define mmSQ_DEBUG_PIX_TB_STATUS_REG_1 0x0DBE +#define mmSQ_DEBUG_PIX_TB_STATUS_REG_2 0x0DBF +#define mmSQ_DEBUG_PIX_TB_STATUS_REG_3 0x0DC0 +#define mmSQ_DEBUG_PIX_TB_STATE_MEM 0x0DC1 +#define mmSQ_PERFCOUNTER0_SELECT 0x0DC8 +#define mmSQ_PERFCOUNTER1_SELECT 0x0DC9 +#define mmSQ_PERFCOUNTER2_SELECT 0x0DCA +#define mmSQ_PERFCOUNTER3_SELECT 0x0DCB +#define mmSQ_PERFCOUNTER0_LOW 0x0DCC +#define mmSQ_PERFCOUNTER0_HI 0x0DCD +#define mmSQ_PERFCOUNTER1_LOW 0x0DCE +#define mmSQ_PERFCOUNTER1_HI 0x0DCF +#define mmSQ_PERFCOUNTER2_LOW 0x0DD0 +#define mmSQ_PERFCOUNTER2_HI 0x0DD1 +#define mmSQ_PERFCOUNTER3_LOW 0x0DD2 +#define mmSQ_PERFCOUNTER3_HI 0x0DD3 +#define mmSX_PERFCOUNTER0_SELECT 0x0DD4 +#define mmSX_PERFCOUNTER0_LOW 0x0DD8 +#define mmSX_PERFCOUNTER0_HI 0x0DD9 +#define mmSQ_INSTRUCTION_ALU_0 0x5000 +#define mmSQ_INSTRUCTION_ALU_1 0x5001 +#define mmSQ_INSTRUCTION_ALU_2 0x5002 +#define mmSQ_INSTRUCTION_CF_EXEC_0 0x5080 +#define mmSQ_INSTRUCTION_CF_EXEC_1 0x5081 +#define mmSQ_INSTRUCTION_CF_EXEC_2 0x5082 +#define mmSQ_INSTRUCTION_CF_LOOP_0 0x5083 +#define mmSQ_INSTRUCTION_CF_LOOP_1 0x5084 +#define mmSQ_INSTRUCTION_CF_LOOP_2 0x5085 +#define mmSQ_INSTRUCTION_CF_JMP_CALL_0 0x5086 +#define mmSQ_INSTRUCTION_CF_JMP_CALL_1 0x5087 +#define mmSQ_INSTRUCTION_CF_JMP_CALL_2 0x5088 +#define mmSQ_INSTRUCTION_CF_ALLOC_0 0x5089 +#define mmSQ_INSTRUCTION_CF_ALLOC_1 0x508A +#define mmSQ_INSTRUCTION_CF_ALLOC_2 0x508B +#define mmSQ_INSTRUCTION_TFETCH_0 0x5043 +#define mmSQ_INSTRUCTION_TFETCH_1 0x5044 +#define mmSQ_INSTRUCTION_TFETCH_2 0x5045 +#define mmSQ_INSTRUCTION_VFETCH_0 0x5040 +#define mmSQ_INSTRUCTION_VFETCH_1 0x5041 +#define mmSQ_INSTRUCTION_VFETCH_2 0x5042 +#define mmSQ_CONSTANT_0 0x4000 +#define mmSQ_CONSTANT_1 0x4001 +#define mmSQ_CONSTANT_2 0x4002 +#define mmSQ_CONSTANT_3 0x4003 +#define mmSQ_FETCH_0 0x4800 +#define mmSQ_FETCH_1 0x4801 +#define mmSQ_FETCH_2 0x4802 +#define mmSQ_FETCH_3 0x4803 +#define mmSQ_FETCH_4 0x4804 +#define mmSQ_FETCH_5 0x4805 +#define mmSQ_CONSTANT_VFETCH_0 0x4806 +#define mmSQ_CONSTANT_VFETCH_1 0x4808 +#define mmSQ_CONSTANT_T2 0x480C +#define mmSQ_CONSTANT_T3 0x4812 +#define mmSQ_CF_BOOLEANS 0x4900 +#define mmSQ_CF_LOOP 0x4908 +#define mmSQ_CONSTANT_RT_0 0x4940 +#define mmSQ_CONSTANT_RT_1 0x4941 +#define mmSQ_CONSTANT_RT_2 0x4942 +#define mmSQ_CONSTANT_RT_3 0x4943 +#define mmSQ_FETCH_RT_0 0x4D40 +#define mmSQ_FETCH_RT_1 0x4D41 +#define mmSQ_FETCH_RT_2 0x4D42 +#define mmSQ_FETCH_RT_3 0x4D43 +#define mmSQ_FETCH_RT_4 0x4D44 +#define mmSQ_FETCH_RT_5 0x4D45 +#define mmSQ_CF_RT_BOOLEANS 0x4E00 +#define mmSQ_CF_RT_LOOP 0x4E14 +#define mmSQ_VS_PROGRAM 0x21F7 +#define mmSQ_PS_PROGRAM 0x21F6 +#define mmSQ_CF_PROGRAM_SIZE 0x2315 +#define mmSQ_INTERPOLATOR_CNTL 0x2182 +#define mmSQ_PROGRAM_CNTL 0x2180 +#define mmSQ_WRAPPING_0 0x2183 +#define mmSQ_WRAPPING_1 0x2184 +#define mmSQ_VS_CONST 0x2307 +#define mmSQ_PS_CONST 0x2308 +#define mmSQ_CONTEXT_MISC 0x2181 +#define mmSQ_CF_RD_BASE 0x21F5 +#define mmSQ_DEBUG_MISC_0 0x2309 +#define mmSQ_DEBUG_MISC_1 0x230A + + +// Registers from SX block + + + +// Registers from MH block + +#define mmMH_ARBITER_CONFIG 0x0A40 +#define mmMH_CLNT_AXI_ID_REUSE 0x0A41 +#define mmMH_INTERRUPT_MASK 0x0A42 +#define mmMH_INTERRUPT_STATUS 0x0A43 +#define mmMH_INTERRUPT_CLEAR 0x0A44 +#define mmMH_AXI_ERROR 0x0A45 +#define mmMH_PERFCOUNTER0_SELECT 0x0A46 +#define mmMH_PERFCOUNTER1_SELECT 0x0A4A +#define mmMH_PERFCOUNTER0_CONFIG 0x0A47 +#define mmMH_PERFCOUNTER1_CONFIG 0x0A4B +#define mmMH_PERFCOUNTER0_LOW 0x0A48 +#define mmMH_PERFCOUNTER1_LOW 0x0A4C +#define mmMH_PERFCOUNTER0_HI 0x0A49 +#define mmMH_PERFCOUNTER1_HI 0x0A4D +#define mmMH_DEBUG_CTRL 0x0A4E +#define mmMH_DEBUG_DATA 0x0A4F +#define mmMH_AXI_HALT_CONTROL 0x0A50 +#define mmMH_MMU_CONFIG 0x0040 +#define mmMH_MMU_VA_RANGE 0x0041 +#define mmMH_MMU_PT_BASE 0x0042 +#define mmMH_MMU_PAGE_FAULT 0x0043 +#define mmMH_MMU_TRAN_ERROR 0x0044 +#define mmMH_MMU_INVALIDATE 0x0045 +#define mmMH_MMU_MPU_BASE 0x0046 +#define mmMH_MMU_MPU_END 0x0047 + + +// Registers from RBBM block + +#define mmWAIT_UNTIL 0x05C8 +#define mmRBBM_ISYNC_CNTL 0x05C9 +#define mmRBBM_STATUS 0x05D0 +#define mmRBBM_DSPLY 0x0391 +#define mmRBBM_RENDER_LATEST 0x0392 +#define mmRBBM_RTL_RELEASE 0x0000 +#define mmRBBM_PATCH_RELEASE 0x0001 +#define mmRBBM_AUXILIARY_CONFIG 0x0002 +#define mmRBBM_PERIPHID0 0x03F8 +#define mmRBBM_PERIPHID1 0x03F9 +#define mmRBBM_PERIPHID2 0x03FA +#define mmRBBM_PERIPHID3 0x03FB +#define mmRBBM_CNTL 0x003B +#define mmRBBM_SKEW_CNTL 0x003D +#define mmRBBM_SOFT_RESET 0x003C +#define mmRBBM_PM_OVERRIDE1 0x039C +#define mmRBBM_PM_OVERRIDE2 0x039D +#define mmGC_SYS_IDLE 0x039E +#define mmNQWAIT_UNTIL 0x0394 +#define mmRBBM_DEBUG_OUT 0x03A0 +#define mmRBBM_DEBUG_CNTL 0x03A1 +#define mmRBBM_DEBUG 0x039B +#define mmRBBM_READ_ERROR 0x03B3 +#define mmRBBM_WAIT_IDLE_CLOCKS 0x03B2 +#define mmRBBM_INT_CNTL 0x03B4 +#define mmRBBM_INT_STATUS 0x03B5 +#define mmRBBM_INT_ACK 0x03B6 +#define mmMASTER_INT_SIGNAL 0x03B7 +#define mmRBBM_PERFCOUNTER1_SELECT 0x0395 +#define mmRBBM_PERFCOUNTER1_LO 0x0397 +#define mmRBBM_PERFCOUNTER1_HI 0x0398 + + +// Registers from CP block + +#define mmCP_RB_BASE 0x01C0 +#define mmCP_RB_CNTL 0x01C1 +#define mmCP_RB_RPTR_ADDR 0x01C3 +#define mmCP_RB_RPTR 0x01C4 +#define mmCP_RB_RPTR_WR 0x01C7 +#define mmCP_RB_WPTR 0x01C5 +#define mmCP_RB_WPTR_DELAY 0x01C6 +#define mmCP_RB_WPTR_BASE 0x01C8 +#define mmCP_IB1_BASE 0x0458 +#define mmCP_IB1_BUFSZ 0x0459 +#define mmCP_IB2_BASE 0x045A +#define mmCP_IB2_BUFSZ 0x045B +#define mmCP_ST_BASE 0x044D +#define mmCP_ST_BUFSZ 0x044E +#define mmCP_QUEUE_THRESHOLDS 0x01D5 +#define mmCP_MEQ_THRESHOLDS 0x01D6 +#define mmCP_CSQ_AVAIL 0x01D7 +#define mmCP_STQ_AVAIL 0x01D8 +#define mmCP_MEQ_AVAIL 0x01D9 +#define mmCP_CSQ_RB_STAT 0x01FD +#define mmCP_CSQ_IB1_STAT 0x01FE +#define mmCP_CSQ_IB2_STAT 0x01FF +#define mmCP_NON_PREFETCH_CNTRS 0x0440 +#define mmCP_STQ_ST_STAT 0x0443 +#define mmCP_MEQ_STAT 0x044F +#define mmCP_MIU_TAG_STAT 0x0452 +#define mmCP_CMD_INDEX 0x01DA +#define mmCP_CMD_DATA 0x01DB +#define mmCP_ME_CNTL 0x01F6 +#define mmCP_ME_STATUS 0x01F7 +#define mmCP_ME_RAM_WADDR 0x01F8 +#define mmCP_ME_RAM_RADDR 0x01F9 +#define mmCP_ME_RAM_DATA 0x01FA +#define mmCP_ME_RDADDR 0x01EA +#define mmCP_DEBUG 0x01FC +#define mmSCRATCH_REG0 0x0578 +#define mmGUI_SCRATCH_REG0 0x0578 +#define mmSCRATCH_REG1 0x0579 +#define mmGUI_SCRATCH_REG1 0x0579 +#define mmSCRATCH_REG2 0x057A +#define mmGUI_SCRATCH_REG2 0x057A +#define mmSCRATCH_REG3 0x057B +#define mmGUI_SCRATCH_REG3 0x057B +#define mmSCRATCH_REG4 0x057C +#define mmGUI_SCRATCH_REG4 0x057C +#define mmSCRATCH_REG5 0x057D +#define mmGUI_SCRATCH_REG5 0x057D +#define mmSCRATCH_REG6 0x057E +#define mmGUI_SCRATCH_REG6 0x057E +#define mmSCRATCH_REG7 0x057F +#define mmGUI_SCRATCH_REG7 0x057F +#define mmSCRATCH_UMSK 0x01DC +#define mmSCRATCH_ADDR 0x01DD +#define mmCP_ME_VS_EVENT_SRC 0x0600 +#define mmCP_ME_VS_EVENT_ADDR 0x0601 +#define mmCP_ME_VS_EVENT_DATA 0x0602 +#define mmCP_ME_VS_EVENT_ADDR_SWM 0x0603 +#define mmCP_ME_VS_EVENT_DATA_SWM 0x0604 +#define mmCP_ME_PS_EVENT_SRC 0x0605 +#define mmCP_ME_PS_EVENT_ADDR 0x0606 +#define mmCP_ME_PS_EVENT_DATA 0x0607 +#define mmCP_ME_PS_EVENT_ADDR_SWM 0x0608 +#define mmCP_ME_PS_EVENT_DATA_SWM 0x0609 +#define mmCP_ME_CF_EVENT_SRC 0x060A +#define mmCP_ME_CF_EVENT_ADDR 0x060B +#define mmCP_ME_CF_EVENT_DATA 0x060C +#define mmCP_ME_NRT_ADDR 0x060D +#define mmCP_ME_NRT_DATA 0x060E +#define mmCP_ME_VS_FETCH_DONE_SRC 0x0612 +#define mmCP_ME_VS_FETCH_DONE_ADDR 0x0613 +#define mmCP_ME_VS_FETCH_DONE_DATA 0x0614 +#define mmCP_INT_CNTL 0x01F2 +#define mmCP_INT_STATUS 0x01F3 +#define mmCP_INT_ACK 0x01F4 +#define mmCP_PFP_UCODE_ADDR 0x00C0 +#define mmCP_PFP_UCODE_DATA 0x00C1 +#define mmCP_PERFMON_CNTL 0x0444 +#define mmCP_PERFCOUNTER_SELECT 0x0445 +#define mmCP_PERFCOUNTER_LO 0x0446 +#define mmCP_PERFCOUNTER_HI 0x0447 +#define mmCP_BIN_MASK_LO 0x0454 +#define mmCP_BIN_MASK_HI 0x0455 +#define mmCP_BIN_SELECT_LO 0x0456 +#define mmCP_BIN_SELECT_HI 0x0457 +#define mmCP_NV_FLAGS_0 0x01EE +#define mmCP_NV_FLAGS_1 0x01EF +#define mmCP_NV_FLAGS_2 0x01F0 +#define mmCP_NV_FLAGS_3 0x01F1 +#define mmCP_STATE_DEBUG_INDEX 0x01EC +#define mmCP_STATE_DEBUG_DATA 0x01ED +#define mmCP_PROG_COUNTER 0x044B +#define mmCP_STAT 0x047F +#define mmBIOS_0_SCRATCH 0x0004 +#define mmBIOS_1_SCRATCH 0x0005 +#define mmBIOS_2_SCRATCH 0x0006 +#define mmBIOS_3_SCRATCH 0x0007 +#define mmBIOS_4_SCRATCH 0x0008 +#define mmBIOS_5_SCRATCH 0x0009 +#define mmBIOS_6_SCRATCH 0x000A +#define mmBIOS_7_SCRATCH 0x000B +#define mmBIOS_8_SCRATCH 0x0580 +#define mmBIOS_9_SCRATCH 0x0581 +#define mmBIOS_10_SCRATCH 0x0582 +#define mmBIOS_11_SCRATCH 0x0583 +#define mmBIOS_12_SCRATCH 0x0584 +#define mmBIOS_13_SCRATCH 0x0585 +#define mmBIOS_14_SCRATCH 0x0586 +#define mmBIOS_15_SCRATCH 0x0587 +#define mmCOHER_SIZE_PM4 0x0A29 +#define mmCOHER_BASE_PM4 0x0A2A +#define mmCOHER_STATUS_PM4 0x0A2B +#define mmCOHER_SIZE_HOST 0x0A2F +#define mmCOHER_BASE_HOST 0x0A30 +#define mmCOHER_STATUS_HOST 0x0A31 +#define mmCOHER_DEST_BASE_0 0x2006 +#define mmCOHER_DEST_BASE_1 0x2007 +#define mmCOHER_DEST_BASE_2 0x2008 +#define mmCOHER_DEST_BASE_3 0x2009 +#define mmCOHER_DEST_BASE_4 0x200A +#define mmCOHER_DEST_BASE_5 0x200B +#define mmCOHER_DEST_BASE_6 0x200C +#define mmCOHER_DEST_BASE_7 0x200D + + +// Registers from SC block + + + +// Registers from BC block + +#define mmRB_SURFACE_INFO 0x2000 +#define mmRB_COLOR_INFO 0x2001 +#define mmRB_DEPTH_INFO 0x2002 +#define mmRB_STENCILREFMASK 0x210D +#define mmRB_ALPHA_REF 0x210E +#define mmRB_COLOR_MASK 0x2104 +#define mmRB_BLEND_RED 0x2105 +#define mmRB_BLEND_GREEN 0x2106 +#define mmRB_BLEND_BLUE 0x2107 +#define mmRB_BLEND_ALPHA 0x2108 +#define mmRB_FOG_COLOR 0x2109 +#define mmRB_STENCILREFMASK_BF 0x210C +#define mmRB_DEPTHCONTROL 0x2200 +#define mmRB_BLENDCONTROL 0x2201 +#define mmRB_COLORCONTROL 0x2202 +#define mmRB_MODECONTROL 0x2208 +#define mmRB_COLOR_DEST_MASK 0x2326 +#define mmRB_COPY_CONTROL 0x2318 +#define mmRB_COPY_DEST_BASE 0x2319 +#define mmRB_COPY_DEST_PITCH 0x231A +#define mmRB_COPY_DEST_INFO 0x231B +#define mmRB_COPY_DEST_PIXEL_OFFSET 0x231C +#define mmRB_DEPTH_CLEAR 0x231D +#define mmRB_SAMPLE_COUNT_CTL 0x2324 +#define mmRB_SAMPLE_COUNT_ADDR 0x2325 +#define mmRB_BC_CONTROL 0x0F01 +#define mmRB_EDRAM_INFO 0x0F02 +#define mmRB_CRC_RD_PORT 0x0F0C +#define mmRB_CRC_CONTROL 0x0F0D +#define mmRB_CRC_MASK 0x0F0E +#define mmRB_PERFCOUNTER0_SELECT 0x0F04 +#define mmRB_PERFCOUNTER0_LOW 0x0F08 +#define mmRB_PERFCOUNTER0_HI 0x0F09 +#define mmRB_TOTAL_SAMPLES 0x0F0F +#define mmRB_ZPASS_SAMPLES 0x0F10 +#define mmRB_ZFAIL_SAMPLES 0x0F11 +#define mmRB_SFAIL_SAMPLES 0x0F12 +#define mmRB_DEBUG_0 0x0F26 +#define mmRB_DEBUG_1 0x0F27 +#define mmRB_DEBUG_2 0x0F28 +#define mmRB_DEBUG_3 0x0F29 +#define mmRB_DEBUG_4 0x0F2A +#define mmRB_FLAG_CONTROL 0x0F2B +#define mmRB_BC_SPARES 0x0F2C +#define mmBC_DUMMY_CRAYRB_ENUMS 0x0F15 +#define mmBC_DUMMY_CRAYRB_MOREENUMS 0x0F16 +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_random.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_random.h new file mode 100644 index 000000000000..17379dcfa0e7 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_random.h @@ -0,0 +1,223 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_RANDOM_HEADER) +#define _yamato_RANDOM_HEADER + +/************************************************************* + * THIS FILE IS AUTOMATICALLY CREATED. DO NOT EDIT THIS FILE. + *************************************************************/ +/******************************************************* + * PA Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * VGT Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * TP Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * TC Enums + *******************************************************/ +/******************************************************* + * SQ Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * SX Enums + *******************************************************/ +/******************************************************* + * MH Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * RBBM Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * CP Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * SC Enums + *******************************************************/ +/******************************************************* + * BC Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +#endif /*_yamato_RANDOM_HEADER*/ + diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_registers.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_registers.h new file mode 100644 index 000000000000..3cd315f903db --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_registers.h @@ -0,0 +1,14292 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_REG_HEADER) +#define _yamato_REG_HEADER +/* +* yamato_registers.h +* +* Register Spec Release: Chip Spec 1.0 +* +* +* (c) 2000 ATI Technologies Inc. (unpublished) +* +* All rights reserved. This notice is intended as a precaution against +* inadvertent publication and does not imply publication or any waiver +* of confidentiality. The year included in the foregoing notice is the +* year of creation of the work. +* +*/ + + union PA_CL_VPORT_XSCALE { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_XSCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_XSCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_XOFFSET { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_XOFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_XOFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_YSCALE { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_YSCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_YSCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_YOFFSET { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_YOFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_YOFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_ZSCALE { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_ZSCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_ZSCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_ZOFFSET { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_ZOFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_ZOFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VTE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_X_SCALE_ENA : 1; + unsigned int VPORT_X_OFFSET_ENA : 1; + unsigned int VPORT_Y_SCALE_ENA : 1; + unsigned int VPORT_Y_OFFSET_ENA : 1; + unsigned int VPORT_Z_SCALE_ENA : 1; + unsigned int VPORT_Z_OFFSET_ENA : 1; + unsigned int : 2; + unsigned int VTX_XY_FMT : 1; + unsigned int VTX_Z_FMT : 1; + unsigned int VTX_W0_FMT : 1; + unsigned int PERFCOUNTER_REF : 1; + unsigned int : 20; +#else /* !defined(qLittleEndian) */ + unsigned int : 20; + unsigned int PERFCOUNTER_REF : 1; + unsigned int VTX_W0_FMT : 1; + unsigned int VTX_Z_FMT : 1; + unsigned int VTX_XY_FMT : 1; + unsigned int : 2; + unsigned int VPORT_Z_OFFSET_ENA : 1; + unsigned int VPORT_Z_SCALE_ENA : 1; + unsigned int VPORT_Y_OFFSET_ENA : 1; + unsigned int VPORT_Y_SCALE_ENA : 1; + unsigned int VPORT_X_OFFSET_ENA : 1; + unsigned int VPORT_X_SCALE_ENA : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_CLIP_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int : 16; + unsigned int CLIP_DISABLE : 1; + unsigned int : 1; + unsigned int BOUNDARY_EDGE_FLAG_ENA : 1; + unsigned int DX_CLIP_SPACE_DEF : 1; + unsigned int DIS_CLIP_ERR_DETECT : 1; + unsigned int VTX_KILL_OR : 1; + unsigned int XY_NAN_RETAIN : 1; + unsigned int Z_NAN_RETAIN : 1; + unsigned int W_NAN_RETAIN : 1; + unsigned int : 7; +#else /* !defined(qLittleEndian) */ + unsigned int : 7; + unsigned int W_NAN_RETAIN : 1; + unsigned int Z_NAN_RETAIN : 1; + unsigned int XY_NAN_RETAIN : 1; + unsigned int VTX_KILL_OR : 1; + unsigned int DIS_CLIP_ERR_DETECT : 1; + unsigned int DX_CLIP_SPACE_DEF : 1; + unsigned int BOUNDARY_EDGE_FLAG_ENA : 1; + unsigned int : 1; + unsigned int CLIP_DISABLE : 1; + unsigned int : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_GB_VERT_CLIP_ADJ { + struct { +#if defined(qLittleEndian) + unsigned int DATA_REGISTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA_REGISTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_GB_VERT_DISC_ADJ { + struct { +#if defined(qLittleEndian) + unsigned int DATA_REGISTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA_REGISTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_GB_HORZ_CLIP_ADJ { + struct { +#if defined(qLittleEndian) + unsigned int DATA_REGISTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA_REGISTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_GB_HORZ_DISC_ADJ { + struct { +#if defined(qLittleEndian) + unsigned int DATA_REGISTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA_REGISTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_ENHANCE { + struct { +#if defined(qLittleEndian) + unsigned int CLIP_VTX_REORDER_ENA : 1; + unsigned int : 27; + unsigned int ECO_SPARE3 : 1; + unsigned int ECO_SPARE2 : 1; + unsigned int ECO_SPARE1 : 1; + unsigned int ECO_SPARE0 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int ECO_SPARE0 : 1; + unsigned int ECO_SPARE1 : 1; + unsigned int ECO_SPARE2 : 1; + unsigned int ECO_SPARE3 : 1; + unsigned int : 27; + unsigned int CLIP_VTX_REORDER_ENA : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_ENHANCE { + struct { +#if defined(qLittleEndian) + unsigned int : 28; + unsigned int ECO_SPARE3 : 1; + unsigned int ECO_SPARE2 : 1; + unsigned int ECO_SPARE1 : 1; + unsigned int ECO_SPARE0 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int ECO_SPARE0 : 1; + unsigned int ECO_SPARE1 : 1; + unsigned int ECO_SPARE2 : 1; + unsigned int ECO_SPARE3 : 1; + unsigned int : 28; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_VTX_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int PIX_CENTER : 1; + unsigned int ROUND_MODE : 2; + unsigned int QUANT_MODE : 3; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int QUANT_MODE : 3; + unsigned int ROUND_MODE : 2; + unsigned int PIX_CENTER : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POINT_SIZE { + struct { +#if defined(qLittleEndian) + unsigned int HEIGHT : 16; + unsigned int WIDTH : 16; +#else /* !defined(qLittleEndian) */ + unsigned int WIDTH : 16; + unsigned int HEIGHT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POINT_MINMAX { + struct { +#if defined(qLittleEndian) + unsigned int MIN_SIZE : 16; + unsigned int MAX_SIZE : 16; +#else /* !defined(qLittleEndian) */ + unsigned int MAX_SIZE : 16; + unsigned int MIN_SIZE : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_LINE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int WIDTH : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int WIDTH : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_FACE_DATA { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int BASE_ADDR : 27; +#else /* !defined(qLittleEndian) */ + unsigned int BASE_ADDR : 27; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_SC_MODE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int CULL_FRONT : 1; + unsigned int CULL_BACK : 1; + unsigned int FACE : 1; + unsigned int POLY_MODE : 2; + unsigned int POLYMODE_FRONT_PTYPE : 3; + unsigned int POLYMODE_BACK_PTYPE : 3; + unsigned int POLY_OFFSET_FRONT_ENABLE : 1; + unsigned int POLY_OFFSET_BACK_ENABLE : 1; + unsigned int POLY_OFFSET_PARA_ENABLE : 1; + unsigned int : 1; + unsigned int MSAA_ENABLE : 1; + unsigned int VTX_WINDOW_OFFSET_ENABLE : 1; + unsigned int : 1; + unsigned int LINE_STIPPLE_ENABLE : 1; + unsigned int PROVOKING_VTX_LAST : 1; + unsigned int PERSP_CORR_DIS : 1; + unsigned int MULTI_PRIM_IB_ENA : 1; + unsigned int : 1; + unsigned int QUAD_ORDER_ENABLE : 1; + unsigned int : 1; + unsigned int WAIT_RB_IDLE_ALL_TRI : 1; + unsigned int WAIT_RB_IDLE_FIRST_TRI_NEW_STATE : 1; + unsigned int : 2; + unsigned int ZERO_AREA_FACENESS : 1; + unsigned int FACE_KILL_ENABLE : 1; + unsigned int FACE_WRITE_ENABLE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int FACE_WRITE_ENABLE : 1; + unsigned int FACE_KILL_ENABLE : 1; + unsigned int ZERO_AREA_FACENESS : 1; + unsigned int : 2; + unsigned int WAIT_RB_IDLE_FIRST_TRI_NEW_STATE : 1; + unsigned int WAIT_RB_IDLE_ALL_TRI : 1; + unsigned int : 1; + unsigned int QUAD_ORDER_ENABLE : 1; + unsigned int : 1; + unsigned int MULTI_PRIM_IB_ENA : 1; + unsigned int PERSP_CORR_DIS : 1; + unsigned int PROVOKING_VTX_LAST : 1; + unsigned int LINE_STIPPLE_ENABLE : 1; + unsigned int : 1; + unsigned int VTX_WINDOW_OFFSET_ENABLE : 1; + unsigned int MSAA_ENABLE : 1; + unsigned int : 1; + unsigned int POLY_OFFSET_PARA_ENABLE : 1; + unsigned int POLY_OFFSET_BACK_ENABLE : 1; + unsigned int POLY_OFFSET_FRONT_ENABLE : 1; + unsigned int POLYMODE_BACK_PTYPE : 3; + unsigned int POLYMODE_FRONT_PTYPE : 3; + unsigned int POLY_MODE : 2; + unsigned int FACE : 1; + unsigned int CULL_BACK : 1; + unsigned int CULL_FRONT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POLY_OFFSET_FRONT_SCALE { + struct { +#if defined(qLittleEndian) + unsigned int SCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POLY_OFFSET_FRONT_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int OFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int OFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POLY_OFFSET_BACK_SCALE { + struct { +#if defined(qLittleEndian) + unsigned int SCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POLY_OFFSET_BACK_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int OFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int OFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER2_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER3_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER2_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER2_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER3_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER3_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_WINDOW_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int WINDOW_X_OFFSET : 15; + unsigned int : 1; + unsigned int WINDOW_Y_OFFSET : 15; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int WINDOW_Y_OFFSET : 15; + unsigned int : 1; + unsigned int WINDOW_X_OFFSET : 15; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_AA_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int MSAA_NUM_SAMPLES : 3; + unsigned int : 10; + unsigned int MAX_SAMPLE_DIST : 4; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int MAX_SAMPLE_DIST : 4; + unsigned int : 10; + unsigned int MSAA_NUM_SAMPLES : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_AA_MASK { + struct { +#if defined(qLittleEndian) + unsigned int AA_MASK : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int AA_MASK : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_LINE_STIPPLE { + struct { +#if defined(qLittleEndian) + unsigned int LINE_PATTERN : 16; + unsigned int REPEAT_COUNT : 8; + unsigned int : 4; + unsigned int PATTERN_BIT_ORDER : 1; + unsigned int AUTO_RESET_CNTL : 2; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int AUTO_RESET_CNTL : 2; + unsigned int PATTERN_BIT_ORDER : 1; + unsigned int : 4; + unsigned int REPEAT_COUNT : 8; + unsigned int LINE_PATTERN : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_LINE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int BRES_CNTL : 8; + unsigned int USE_BRES_CNTL : 1; + unsigned int EXPAND_LINE_WIDTH : 1; + unsigned int LAST_PIXEL : 1; + unsigned int : 21; +#else /* !defined(qLittleEndian) */ + unsigned int : 21; + unsigned int LAST_PIXEL : 1; + unsigned int EXPAND_LINE_WIDTH : 1; + unsigned int USE_BRES_CNTL : 1; + unsigned int BRES_CNTL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_WINDOW_SCISSOR_TL { + struct { +#if defined(qLittleEndian) + unsigned int TL_X : 14; + unsigned int : 2; + unsigned int TL_Y : 14; + unsigned int : 1; + unsigned int WINDOW_OFFSET_DISABLE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int WINDOW_OFFSET_DISABLE : 1; + unsigned int : 1; + unsigned int TL_Y : 14; + unsigned int : 2; + unsigned int TL_X : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_WINDOW_SCISSOR_BR { + struct { +#if defined(qLittleEndian) + unsigned int BR_X : 14; + unsigned int : 2; + unsigned int BR_Y : 14; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int BR_Y : 14; + unsigned int : 2; + unsigned int BR_X : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_SCREEN_SCISSOR_TL { + struct { +#if defined(qLittleEndian) + unsigned int TL_X : 15; + unsigned int : 1; + unsigned int TL_Y : 15; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int TL_Y : 15; + unsigned int : 1; + unsigned int TL_X : 15; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_SCREEN_SCISSOR_BR { + struct { +#if defined(qLittleEndian) + unsigned int BR_X : 15; + unsigned int : 1; + unsigned int BR_Y : 15; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int BR_Y : 15; + unsigned int : 1; + unsigned int BR_X : 15; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_VIZ_QUERY { + struct { +#if defined(qLittleEndian) + unsigned int VIZ_QUERY_ENA : 1; + unsigned int VIZ_QUERY_ID : 5; + unsigned int : 1; + unsigned int KILL_PIX_POST_EARLY_Z : 1; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int KILL_PIX_POST_EARLY_Z : 1; + unsigned int : 1; + unsigned int VIZ_QUERY_ID : 5; + unsigned int VIZ_QUERY_ENA : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_VIZ_QUERY_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int STATUS_BITS : 32; +#else /* !defined(qLittleEndian) */ + unsigned int STATUS_BITS : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_LINE_STIPPLE_STATE { + struct { +#if defined(qLittleEndian) + unsigned int CURRENT_PTR : 4; + unsigned int : 4; + unsigned int CURRENT_COUNT : 8; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int CURRENT_COUNT : 8; + unsigned int : 4; + unsigned int CURRENT_PTR : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int : 31; + unsigned int CL_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int CL_BUSY : 1; + unsigned int : 31; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int : 31; + unsigned int SU_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int SU_BUSY : 1; + unsigned int : 31; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int : 31; + unsigned int SC_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int SC_BUSY : 1; + unsigned int : 31; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_DEBUG_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int SU_DEBUG_INDX : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int SU_DEBUG_INDX : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG00 { + struct { +#if defined(qLittleEndian) + unsigned int clip_ga_bc_fifo_write : 1; + unsigned int clip_ga_bc_fifo_full : 1; + unsigned int clip_to_ga_fifo_write : 1; + unsigned int clip_to_ga_fifo_full : 1; + unsigned int primic_to_clprim_fifo_empty : 1; + unsigned int primic_to_clprim_fifo_full : 1; + unsigned int clip_to_outsm_fifo_empty : 1; + unsigned int clip_to_outsm_fifo_full : 1; + unsigned int vgt_to_clipp_fifo_empty : 1; + unsigned int vgt_to_clipp_fifo_full : 1; + unsigned int vgt_to_clips_fifo_empty : 1; + unsigned int vgt_to_clips_fifo_full : 1; + unsigned int clipcode_fifo_fifo_empty : 1; + unsigned int clipcode_fifo_full : 1; + unsigned int vte_out_clip_fifo_fifo_empty : 1; + unsigned int vte_out_clip_fifo_fifo_full : 1; + unsigned int vte_out_orig_fifo_fifo_empty : 1; + unsigned int vte_out_orig_fifo_fifo_full : 1; + unsigned int ccgen_to_clipcc_fifo_empty : 1; + unsigned int ccgen_to_clipcc_fifo_full : 1; + unsigned int ALWAYS_ZERO : 12; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO : 12; + unsigned int ccgen_to_clipcc_fifo_full : 1; + unsigned int ccgen_to_clipcc_fifo_empty : 1; + unsigned int vte_out_orig_fifo_fifo_full : 1; + unsigned int vte_out_orig_fifo_fifo_empty : 1; + unsigned int vte_out_clip_fifo_fifo_full : 1; + unsigned int vte_out_clip_fifo_fifo_empty : 1; + unsigned int clipcode_fifo_full : 1; + unsigned int clipcode_fifo_fifo_empty : 1; + unsigned int vgt_to_clips_fifo_full : 1; + unsigned int vgt_to_clips_fifo_empty : 1; + unsigned int vgt_to_clipp_fifo_full : 1; + unsigned int vgt_to_clipp_fifo_empty : 1; + unsigned int clip_to_outsm_fifo_full : 1; + unsigned int clip_to_outsm_fifo_empty : 1; + unsigned int primic_to_clprim_fifo_full : 1; + unsigned int primic_to_clprim_fifo_empty : 1; + unsigned int clip_to_ga_fifo_full : 1; + unsigned int clip_to_ga_fifo_write : 1; + unsigned int clip_ga_bc_fifo_full : 1; + unsigned int clip_ga_bc_fifo_write : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG01 { + struct { +#if defined(qLittleEndian) + unsigned int clip_to_outsm_end_of_packet : 1; + unsigned int clip_to_outsm_first_prim_of_slot : 1; + unsigned int clip_to_outsm_deallocate_slot : 3; + unsigned int clip_to_outsm_clipped_prim : 1; + unsigned int clip_to_outsm_null_primitive : 1; + unsigned int clip_to_outsm_vertex_store_indx_2 : 4; + unsigned int clip_to_outsm_vertex_store_indx_1 : 4; + unsigned int clip_to_outsm_vertex_store_indx_0 : 4; + unsigned int clip_vert_vte_valid : 3; + unsigned int vte_out_clip_rd_vertex_store_indx : 2; + unsigned int ALWAYS_ZERO : 8; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO : 8; + unsigned int vte_out_clip_rd_vertex_store_indx : 2; + unsigned int clip_vert_vte_valid : 3; + unsigned int clip_to_outsm_vertex_store_indx_0 : 4; + unsigned int clip_to_outsm_vertex_store_indx_1 : 4; + unsigned int clip_to_outsm_vertex_store_indx_2 : 4; + unsigned int clip_to_outsm_null_primitive : 1; + unsigned int clip_to_outsm_clipped_prim : 1; + unsigned int clip_to_outsm_deallocate_slot : 3; + unsigned int clip_to_outsm_first_prim_of_slot : 1; + unsigned int clip_to_outsm_end_of_packet : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG02 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO1 : 21; + unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : 3; + unsigned int ALWAYS_ZERO0 : 7; + unsigned int clipsm0_clprim_to_clip_prim_valid : 1; +#else /* !defined(qLittleEndian) */ + unsigned int clipsm0_clprim_to_clip_prim_valid : 1; + unsigned int ALWAYS_ZERO0 : 7; + unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : 3; + unsigned int ALWAYS_ZERO1 : 21; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG03 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO3 : 3; + unsigned int clipsm0_clprim_to_clip_clip_primitive : 1; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clipsm0_clprim_to_clip_null_primitive : 1; + unsigned int ALWAYS_ZERO1 : 12; + unsigned int clipsm0_clprim_to_clip_clip_code_or : 6; + unsigned int ALWAYS_ZERO0 : 6; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 6; + unsigned int clipsm0_clprim_to_clip_clip_code_or : 6; + unsigned int ALWAYS_ZERO1 : 12; + unsigned int clipsm0_clprim_to_clip_null_primitive : 1; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clipsm0_clprim_to_clip_clip_primitive : 1; + unsigned int ALWAYS_ZERO3 : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG04 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : 1; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int clipsm0_clprim_to_clip_event : 1; + unsigned int ALWAYS_ZERO0 : 24; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 24; + unsigned int clipsm0_clprim_to_clip_event : 1; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : 1; + unsigned int ALWAYS_ZERO2 : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG05 { + struct { +#if defined(qLittleEndian) + unsigned int clipsm0_clprim_to_clip_state_var_indx : 1; + unsigned int ALWAYS_ZERO3 : 2; + unsigned int clipsm0_clprim_to_clip_deallocate_slot : 3; + unsigned int clipsm0_clprim_to_clip_event_id : 6; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO0 : 4; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 4; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : 4; + unsigned int clipsm0_clprim_to_clip_event_id : 6; + unsigned int clipsm0_clprim_to_clip_deallocate_slot : 3; + unsigned int ALWAYS_ZERO3 : 2; + unsigned int clipsm0_clprim_to_clip_state_var_indx : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG09 { + struct { +#if defined(qLittleEndian) + unsigned int clprim_in_back_event : 1; + unsigned int outputclprimtoclip_null_primitive : 1; + unsigned int clprim_in_back_vertex_store_indx_2 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int clprim_in_back_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clprim_in_back_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int prim_back_valid : 1; + unsigned int clip_priority_seq_indx_out_cnt : 4; + unsigned int outsm_clr_rd_orig_vertices : 2; + unsigned int outsm_clr_rd_clipsm_wait : 1; + unsigned int outsm_clr_fifo_empty : 1; + unsigned int outsm_clr_fifo_full : 1; + unsigned int clip_priority_seq_indx_load : 2; +#else /* !defined(qLittleEndian) */ + unsigned int clip_priority_seq_indx_load : 2; + unsigned int outsm_clr_fifo_full : 1; + unsigned int outsm_clr_fifo_empty : 1; + unsigned int outsm_clr_rd_clipsm_wait : 1; + unsigned int outsm_clr_rd_orig_vertices : 2; + unsigned int clip_priority_seq_indx_out_cnt : 4; + unsigned int prim_back_valid : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int clprim_in_back_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clprim_in_back_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int clprim_in_back_vertex_store_indx_2 : 4; + unsigned int outputclprimtoclip_null_primitive : 1; + unsigned int clprim_in_back_event : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG10 { + struct { +#if defined(qLittleEndian) + unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : 4; + unsigned int ALWAYS_ZERO3 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clprim_in_back_state_var_indx : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int clprim_in_back_end_of_packet : 1; + unsigned int clprim_in_back_first_prim_of_slot : 1; + unsigned int clprim_in_back_deallocate_slot : 3; + unsigned int clprim_in_back_event_id : 6; +#else /* !defined(qLittleEndian) */ + unsigned int clprim_in_back_event_id : 6; + unsigned int clprim_in_back_deallocate_slot : 3; + unsigned int clprim_in_back_first_prim_of_slot : 1; + unsigned int clprim_in_back_end_of_packet : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int clprim_in_back_state_var_indx : 1; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO3 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG11 { + struct { +#if defined(qLittleEndian) + unsigned int vertval_bits_vertex_vertex_store_msb : 4; + unsigned int ALWAYS_ZERO : 28; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO : 28; + unsigned int vertval_bits_vertex_vertex_store_msb : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG12 { + struct { +#if defined(qLittleEndian) + unsigned int clip_priority_available_vte_out_clip : 2; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clip_vertex_fifo_empty : 1; + unsigned int clip_priority_available_clip_verts : 5; + unsigned int ALWAYS_ZERO1 : 4; + unsigned int vertval_bits_vertex_cc_next_valid : 4; + unsigned int clipcc_vertex_store_indx : 2; + unsigned int primic_to_clprim_valid : 1; + unsigned int ALWAYS_ZERO0 : 10; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 10; + unsigned int primic_to_clprim_valid : 1; + unsigned int clipcc_vertex_store_indx : 2; + unsigned int vertval_bits_vertex_cc_next_valid : 4; + unsigned int ALWAYS_ZERO1 : 4; + unsigned int clip_priority_available_clip_verts : 5; + unsigned int clip_vertex_fifo_empty : 1; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clip_priority_available_vte_out_clip : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG13 { + struct { +#if defined(qLittleEndian) + unsigned int sm0_clip_vert_cnt : 4; + unsigned int sm0_prim_end_state : 7; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int sm0_vertex_clip_cnt : 4; + unsigned int sm0_inv_to_clip_data_valid_1 : 1; + unsigned int sm0_inv_to_clip_data_valid_0 : 1; + unsigned int sm0_current_state : 7; + unsigned int ALWAYS_ZERO0 : 5; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 5; + unsigned int sm0_current_state : 7; + unsigned int sm0_inv_to_clip_data_valid_0 : 1; + unsigned int sm0_inv_to_clip_data_valid_1 : 1; + unsigned int sm0_vertex_clip_cnt : 4; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int sm0_prim_end_state : 7; + unsigned int sm0_clip_vert_cnt : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SXIFCCG_DEBUG_REG0 { + struct { +#if defined(qLittleEndian) + unsigned int nan_kill_flag : 4; + unsigned int position_address : 3; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int point_address : 3; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int sx_pending_rd_state_var_indx : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int sx_pending_rd_req_mask : 4; + unsigned int sx_pending_rd_pci : 7; + unsigned int sx_pending_rd_aux_inc : 1; + unsigned int sx_pending_rd_aux_sel : 1; +#else /* !defined(qLittleEndian) */ + unsigned int sx_pending_rd_aux_sel : 1; + unsigned int sx_pending_rd_aux_inc : 1; + unsigned int sx_pending_rd_pci : 7; + unsigned int sx_pending_rd_req_mask : 4; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int sx_pending_rd_state_var_indx : 1; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int point_address : 3; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int position_address : 3; + unsigned int nan_kill_flag : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SXIFCCG_DEBUG_REG1 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO3 : 2; + unsigned int sx_to_pa_empty : 2; + unsigned int available_positions : 3; + unsigned int ALWAYS_ZERO2 : 4; + unsigned int sx_pending_advance : 1; + unsigned int sx_receive_indx : 3; + unsigned int statevar_bits_sxpa_aux_vector : 1; + unsigned int ALWAYS_ZERO1 : 4; + unsigned int aux_sel : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int pasx_req_cnt : 2; + unsigned int param_cache_base : 7; +#else /* !defined(qLittleEndian) */ + unsigned int param_cache_base : 7; + unsigned int pasx_req_cnt : 2; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int aux_sel : 1; + unsigned int ALWAYS_ZERO1 : 4; + unsigned int statevar_bits_sxpa_aux_vector : 1; + unsigned int sx_receive_indx : 3; + unsigned int sx_pending_advance : 1; + unsigned int ALWAYS_ZERO2 : 4; + unsigned int available_positions : 3; + unsigned int sx_to_pa_empty : 2; + unsigned int ALWAYS_ZERO3 : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SXIFCCG_DEBUG_REG2 { + struct { +#if defined(qLittleEndian) + unsigned int sx_sent : 1; + unsigned int ALWAYS_ZERO3 : 1; + unsigned int sx_aux : 1; + unsigned int sx_request_indx : 6; + unsigned int req_active_verts : 7; + unsigned int ALWAYS_ZERO2 : 1; + unsigned int vgt_to_ccgen_state_var_indx : 1; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int vgt_to_ccgen_active_verts : 2; + unsigned int ALWAYS_ZERO0 : 4; + unsigned int req_active_verts_loaded : 1; + unsigned int sx_pending_fifo_empty : 1; + unsigned int sx_pending_fifo_full : 1; + unsigned int sx_pending_fifo_contents : 3; +#else /* !defined(qLittleEndian) */ + unsigned int sx_pending_fifo_contents : 3; + unsigned int sx_pending_fifo_full : 1; + unsigned int sx_pending_fifo_empty : 1; + unsigned int req_active_verts_loaded : 1; + unsigned int ALWAYS_ZERO0 : 4; + unsigned int vgt_to_ccgen_active_verts : 2; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int vgt_to_ccgen_state_var_indx : 1; + unsigned int ALWAYS_ZERO2 : 1; + unsigned int req_active_verts : 7; + unsigned int sx_request_indx : 6; + unsigned int sx_aux : 1; + unsigned int ALWAYS_ZERO3 : 1; + unsigned int sx_sent : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SXIFCCG_DEBUG_REG3 { + struct { +#if defined(qLittleEndian) + unsigned int vertex_fifo_entriesavailable : 4; + unsigned int ALWAYS_ZERO3 : 1; + unsigned int available_positions : 3; + unsigned int ALWAYS_ZERO2 : 4; + unsigned int current_state : 2; + unsigned int vertex_fifo_empty : 1; + unsigned int vertex_fifo_full : 1; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int sx0_receive_fifo_empty : 1; + unsigned int sx0_receive_fifo_full : 1; + unsigned int vgt_to_ccgen_fifo_empty : 1; + unsigned int vgt_to_ccgen_fifo_full : 1; + unsigned int ALWAYS_ZERO0 : 10; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 10; + unsigned int vgt_to_ccgen_fifo_full : 1; + unsigned int vgt_to_ccgen_fifo_empty : 1; + unsigned int sx0_receive_fifo_full : 1; + unsigned int sx0_receive_fifo_empty : 1; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int vertex_fifo_full : 1; + unsigned int vertex_fifo_empty : 1; + unsigned int current_state : 2; + unsigned int ALWAYS_ZERO2 : 4; + unsigned int available_positions : 3; + unsigned int ALWAYS_ZERO3 : 1; + unsigned int vertex_fifo_entriesavailable : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG0 { + struct { +#if defined(qLittleEndian) + unsigned int su_cntl_state : 5; + unsigned int pmode_state : 6; + unsigned int ge_stallb : 1; + unsigned int geom_enable : 1; + unsigned int su_clip_baryc_rtr : 1; + unsigned int su_clip_rtr : 1; + unsigned int pfifo_busy : 1; + unsigned int su_cntl_busy : 1; + unsigned int geom_busy : 1; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int geom_busy : 1; + unsigned int su_cntl_busy : 1; + unsigned int pfifo_busy : 1; + unsigned int su_clip_rtr : 1; + unsigned int su_clip_baryc_rtr : 1; + unsigned int geom_enable : 1; + unsigned int ge_stallb : 1; + unsigned int pmode_state : 6; + unsigned int su_cntl_state : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG1 { + struct { +#if defined(qLittleEndian) + unsigned int y_sort0_gated_17_4 : 14; + unsigned int x_sort0_gated_17_4 : 14; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int x_sort0_gated_17_4 : 14; + unsigned int y_sort0_gated_17_4 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG2 { + struct { +#if defined(qLittleEndian) + unsigned int y_sort1_gated_17_4 : 14; + unsigned int x_sort1_gated_17_4 : 14; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int x_sort1_gated_17_4 : 14; + unsigned int y_sort1_gated_17_4 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG3 { + struct { +#if defined(qLittleEndian) + unsigned int y_sort2_gated_17_4 : 14; + unsigned int x_sort2_gated_17_4 : 14; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int x_sort2_gated_17_4 : 14; + unsigned int y_sort2_gated_17_4 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG4 { + struct { +#if defined(qLittleEndian) + unsigned int attr_indx_sort0_gated : 11; + unsigned int null_prim_gated : 1; + unsigned int backfacing_gated : 1; + unsigned int st_indx_gated : 3; + unsigned int clipped_gated : 1; + unsigned int dealloc_slot_gated : 3; + unsigned int xmajor_gated : 1; + unsigned int diamond_rule_gated : 2; + unsigned int type_gated : 3; + unsigned int fpov_gated : 1; + unsigned int pmode_prim_gated : 1; + unsigned int event_gated : 1; + unsigned int eop_gated : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int eop_gated : 1; + unsigned int event_gated : 1; + unsigned int pmode_prim_gated : 1; + unsigned int fpov_gated : 1; + unsigned int type_gated : 3; + unsigned int diamond_rule_gated : 2; + unsigned int xmajor_gated : 1; + unsigned int dealloc_slot_gated : 3; + unsigned int clipped_gated : 1; + unsigned int st_indx_gated : 3; + unsigned int backfacing_gated : 1; + unsigned int null_prim_gated : 1; + unsigned int attr_indx_sort0_gated : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG5 { + struct { +#if defined(qLittleEndian) + unsigned int attr_indx_sort2_gated : 11; + unsigned int attr_indx_sort1_gated : 11; + unsigned int provoking_vtx_gated : 2; + unsigned int event_id_gated : 5; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int event_id_gated : 5; + unsigned int provoking_vtx_gated : 2; + unsigned int attr_indx_sort1_gated : 11; + unsigned int attr_indx_sort2_gated : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_DEBUG_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int SC_DEBUG_INDX : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int SC_DEBUG_INDX : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_0 { + struct { +#if defined(qLittleEndian) + unsigned int pa_freeze_b1 : 1; + unsigned int pa_sc_valid : 1; + unsigned int pa_sc_phase : 3; + unsigned int cntx_cnt : 7; + unsigned int decr_cntx_cnt : 1; + unsigned int incr_cntx_cnt : 1; + unsigned int : 17; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 17; + unsigned int incr_cntx_cnt : 1; + unsigned int decr_cntx_cnt : 1; + unsigned int cntx_cnt : 7; + unsigned int pa_sc_phase : 3; + unsigned int pa_sc_valid : 1; + unsigned int pa_freeze_b1 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_1 { + struct { +#if defined(qLittleEndian) + unsigned int em_state : 3; + unsigned int em1_data_ready : 1; + unsigned int em2_data_ready : 1; + unsigned int move_em1_to_em2 : 1; + unsigned int ef_data_ready : 1; + unsigned int ef_state : 2; + unsigned int pipe_valid : 1; + unsigned int : 21; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 21; + unsigned int pipe_valid : 1; + unsigned int ef_state : 2; + unsigned int ef_data_ready : 1; + unsigned int move_em1_to_em2 : 1; + unsigned int em2_data_ready : 1; + unsigned int em1_data_ready : 1; + unsigned int em_state : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_2 { + struct { +#if defined(qLittleEndian) + unsigned int rc_rtr_dly : 1; + unsigned int qmask_ff_alm_full_d1 : 1; + unsigned int : 1; + unsigned int pipe_freeze_b : 1; + unsigned int prim_rts : 1; + unsigned int next_prim_rts_dly : 1; + unsigned int next_prim_rtr_dly : 1; + unsigned int pre_stage1_rts_d1 : 1; + unsigned int stage0_rts : 1; + unsigned int phase_rts_dly : 1; + unsigned int : 5; + unsigned int end_of_prim_s1_dly : 1; + unsigned int pass_empty_prim_s1 : 1; + unsigned int event_id_s1 : 5; + unsigned int event_s1 : 1; + unsigned int : 8; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 8; + unsigned int event_s1 : 1; + unsigned int event_id_s1 : 5; + unsigned int pass_empty_prim_s1 : 1; + unsigned int end_of_prim_s1_dly : 1; + unsigned int : 5; + unsigned int phase_rts_dly : 1; + unsigned int stage0_rts : 1; + unsigned int pre_stage1_rts_d1 : 1; + unsigned int next_prim_rtr_dly : 1; + unsigned int next_prim_rts_dly : 1; + unsigned int prim_rts : 1; + unsigned int pipe_freeze_b : 1; + unsigned int : 1; + unsigned int qmask_ff_alm_full_d1 : 1; + unsigned int rc_rtr_dly : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_3 { + struct { +#if defined(qLittleEndian) + unsigned int x_curr_s1 : 11; + unsigned int y_curr_s1 : 11; + unsigned int : 9; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 9; + unsigned int y_curr_s1 : 11; + unsigned int x_curr_s1 : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_4 { + struct { +#if defined(qLittleEndian) + unsigned int y_end_s1 : 14; + unsigned int y_start_s1 : 14; + unsigned int y_dir_s1 : 1; + unsigned int : 2; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 2; + unsigned int y_dir_s1 : 1; + unsigned int y_start_s1 : 14; + unsigned int y_end_s1 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_5 { + struct { +#if defined(qLittleEndian) + unsigned int x_end_s1 : 14; + unsigned int x_start_s1 : 14; + unsigned int x_dir_s1 : 1; + unsigned int : 2; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 2; + unsigned int x_dir_s1 : 1; + unsigned int x_start_s1 : 14; + unsigned int x_end_s1 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_6 { + struct { +#if defined(qLittleEndian) + unsigned int z_ff_empty : 1; + unsigned int qmcntl_ff_empty : 1; + unsigned int xy_ff_empty : 1; + unsigned int event_flag : 1; + unsigned int z_mask_needed : 1; + unsigned int state : 3; + unsigned int state_delayed : 3; + unsigned int data_valid : 1; + unsigned int data_valid_d : 1; + unsigned int tilex_delayed : 9; + unsigned int tiley_delayed : 9; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int tiley_delayed : 9; + unsigned int tilex_delayed : 9; + unsigned int data_valid_d : 1; + unsigned int data_valid : 1; + unsigned int state_delayed : 3; + unsigned int state : 3; + unsigned int z_mask_needed : 1; + unsigned int event_flag : 1; + unsigned int xy_ff_empty : 1; + unsigned int qmcntl_ff_empty : 1; + unsigned int z_ff_empty : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_7 { + struct { +#if defined(qLittleEndian) + unsigned int event_flag : 1; + unsigned int deallocate : 3; + unsigned int fposition : 1; + unsigned int sr_prim_we : 1; + unsigned int last_tile : 1; + unsigned int tile_ff_we : 1; + unsigned int qs_data_valid : 1; + unsigned int qs_q0_y : 2; + unsigned int qs_q0_x : 2; + unsigned int qs_q0_valid : 1; + unsigned int prim_ff_we : 1; + unsigned int tile_ff_re : 1; + unsigned int fw_prim_data_valid : 1; + unsigned int last_quad_of_tile : 1; + unsigned int first_quad_of_tile : 1; + unsigned int first_quad_of_prim : 1; + unsigned int new_prim : 1; + unsigned int load_new_tile_data : 1; + unsigned int state : 2; + unsigned int fifos_ready : 1; + unsigned int : 6; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 6; + unsigned int fifos_ready : 1; + unsigned int state : 2; + unsigned int load_new_tile_data : 1; + unsigned int new_prim : 1; + unsigned int first_quad_of_prim : 1; + unsigned int first_quad_of_tile : 1; + unsigned int last_quad_of_tile : 1; + unsigned int fw_prim_data_valid : 1; + unsigned int tile_ff_re : 1; + unsigned int prim_ff_we : 1; + unsigned int qs_q0_valid : 1; + unsigned int qs_q0_x : 2; + unsigned int qs_q0_y : 2; + unsigned int qs_data_valid : 1; + unsigned int tile_ff_we : 1; + unsigned int last_tile : 1; + unsigned int sr_prim_we : 1; + unsigned int fposition : 1; + unsigned int deallocate : 3; + unsigned int event_flag : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_8 { + struct { +#if defined(qLittleEndian) + unsigned int sample_last : 1; + unsigned int sample_mask : 4; + unsigned int sample_y : 2; + unsigned int sample_x : 2; + unsigned int sample_send : 1; + unsigned int next_cycle : 2; + unsigned int ez_sample_ff_full : 1; + unsigned int rb_sc_samp_rtr : 1; + unsigned int num_samples : 2; + unsigned int last_quad_of_tile : 1; + unsigned int last_quad_of_prim : 1; + unsigned int first_quad_of_prim : 1; + unsigned int sample_we : 1; + unsigned int fposition : 1; + unsigned int event_id : 5; + unsigned int event_flag : 1; + unsigned int fw_prim_data_valid : 1; + unsigned int : 3; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 3; + unsigned int fw_prim_data_valid : 1; + unsigned int event_flag : 1; + unsigned int event_id : 5; + unsigned int fposition : 1; + unsigned int sample_we : 1; + unsigned int first_quad_of_prim : 1; + unsigned int last_quad_of_prim : 1; + unsigned int last_quad_of_tile : 1; + unsigned int num_samples : 2; + unsigned int rb_sc_samp_rtr : 1; + unsigned int ez_sample_ff_full : 1; + unsigned int next_cycle : 2; + unsigned int sample_send : 1; + unsigned int sample_x : 2; + unsigned int sample_y : 2; + unsigned int sample_mask : 4; + unsigned int sample_last : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_9 { + struct { +#if defined(qLittleEndian) + unsigned int rb_sc_send : 1; + unsigned int rb_sc_ez_mask : 4; + unsigned int fifo_data_ready : 1; + unsigned int early_z_enable : 1; + unsigned int mask_state : 2; + unsigned int next_ez_mask : 16; + unsigned int mask_ready : 1; + unsigned int drop_sample : 1; + unsigned int fetch_new_sample_data : 1; + unsigned int fetch_new_ez_sample_mask : 1; + unsigned int pkr_fetch_new_sample_data : 1; + unsigned int pkr_fetch_new_prim_data : 1; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int pkr_fetch_new_prim_data : 1; + unsigned int pkr_fetch_new_sample_data : 1; + unsigned int fetch_new_ez_sample_mask : 1; + unsigned int fetch_new_sample_data : 1; + unsigned int drop_sample : 1; + unsigned int mask_ready : 1; + unsigned int next_ez_mask : 16; + unsigned int mask_state : 2; + unsigned int early_z_enable : 1; + unsigned int fifo_data_ready : 1; + unsigned int rb_sc_ez_mask : 4; + unsigned int rb_sc_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_10 { + struct { +#if defined(qLittleEndian) + unsigned int combined_sample_mask : 16; + unsigned int : 15; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 15; + unsigned int combined_sample_mask : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_11 { + struct { +#if defined(qLittleEndian) + unsigned int ez_sample_data_ready : 1; + unsigned int pkr_fetch_new_sample_data : 1; + unsigned int ez_prim_data_ready : 1; + unsigned int pkr_fetch_new_prim_data : 1; + unsigned int iterator_input_fz : 1; + unsigned int packer_send_quads : 1; + unsigned int packer_send_cmd : 1; + unsigned int packer_send_event : 1; + unsigned int next_state : 3; + unsigned int state : 3; + unsigned int stall : 1; + unsigned int : 16; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 16; + unsigned int stall : 1; + unsigned int state : 3; + unsigned int next_state : 3; + unsigned int packer_send_event : 1; + unsigned int packer_send_cmd : 1; + unsigned int packer_send_quads : 1; + unsigned int iterator_input_fz : 1; + unsigned int pkr_fetch_new_prim_data : 1; + unsigned int ez_prim_data_ready : 1; + unsigned int pkr_fetch_new_sample_data : 1; + unsigned int ez_sample_data_ready : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_12 { + struct { +#if defined(qLittleEndian) + unsigned int SQ_iterator_free_buff : 1; + unsigned int event_id : 5; + unsigned int event_flag : 1; + unsigned int itercmdfifo_busy_nc_dly : 1; + unsigned int itercmdfifo_full : 1; + unsigned int itercmdfifo_empty : 1; + unsigned int iter_ds_one_clk_command : 1; + unsigned int iter_ds_end_of_prim0 : 1; + unsigned int iter_ds_end_of_vector : 1; + unsigned int iter_qdhit0 : 1; + unsigned int bc_use_centers_reg : 1; + unsigned int bc_output_xy_reg : 1; + unsigned int iter_phase_out : 2; + unsigned int iter_phase_reg : 2; + unsigned int iterator_SP_valid : 1; + unsigned int eopv_reg : 1; + unsigned int one_clk_cmd_reg : 1; + unsigned int iter_dx_end_of_prim : 1; + unsigned int : 7; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 7; + unsigned int iter_dx_end_of_prim : 1; + unsigned int one_clk_cmd_reg : 1; + unsigned int eopv_reg : 1; + unsigned int iterator_SP_valid : 1; + unsigned int iter_phase_reg : 2; + unsigned int iter_phase_out : 2; + unsigned int bc_output_xy_reg : 1; + unsigned int bc_use_centers_reg : 1; + unsigned int iter_qdhit0 : 1; + unsigned int iter_ds_end_of_vector : 1; + unsigned int iter_ds_end_of_prim0 : 1; + unsigned int iter_ds_one_clk_command : 1; + unsigned int itercmdfifo_empty : 1; + unsigned int itercmdfifo_full : 1; + unsigned int itercmdfifo_busy_nc_dly : 1; + unsigned int event_flag : 1; + unsigned int event_id : 5; + unsigned int SQ_iterator_free_buff : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union GFX_COPY_STATE { + struct { +#if defined(qLittleEndian) + unsigned int SRC_STATE_ID : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int SRC_STATE_ID : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DRAW_INITIATOR { + struct { +#if defined(qLittleEndian) + unsigned int PRIM_TYPE : 6; + unsigned int SOURCE_SELECT : 2; + unsigned int FACENESS_CULL_SELECT : 2; + unsigned int : 1; + unsigned int INDEX_SIZE : 1; + unsigned int NOT_EOP : 1; + unsigned int SMALL_INDEX : 1; + unsigned int PRE_FETCH_CULL_ENABLE : 1; + unsigned int GRP_CULL_ENABLE : 1; + unsigned int NUM_INDICES : 16; +#else /* !defined(qLittleEndian) */ + unsigned int NUM_INDICES : 16; + unsigned int GRP_CULL_ENABLE : 1; + unsigned int PRE_FETCH_CULL_ENABLE : 1; + unsigned int SMALL_INDEX : 1; + unsigned int NOT_EOP : 1; + unsigned int INDEX_SIZE : 1; + unsigned int : 1; + unsigned int FACENESS_CULL_SELECT : 2; + unsigned int SOURCE_SELECT : 2; + unsigned int PRIM_TYPE : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_EVENT_INITIATOR { + struct { +#if defined(qLittleEndian) + unsigned int EVENT_TYPE : 6; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int EVENT_TYPE : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DMA_BASE { + struct { +#if defined(qLittleEndian) + unsigned int BASE_ADDR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BASE_ADDR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DMA_SIZE { + struct { +#if defined(qLittleEndian) + unsigned int NUM_WORDS : 24; + unsigned int : 6; + unsigned int SWAP_MODE : 2; +#else /* !defined(qLittleEndian) */ + unsigned int SWAP_MODE : 2; + unsigned int : 6; + unsigned int NUM_WORDS : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_BIN_BASE { + struct { +#if defined(qLittleEndian) + unsigned int BIN_BASE_ADDR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_BASE_ADDR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_BIN_SIZE { + struct { +#if defined(qLittleEndian) + unsigned int NUM_WORDS : 24; + unsigned int : 6; + unsigned int FACENESS_FETCH : 1; + unsigned int FACENESS_RESET : 1; +#else /* !defined(qLittleEndian) */ + unsigned int FACENESS_RESET : 1; + unsigned int FACENESS_FETCH : 1; + unsigned int : 6; + unsigned int NUM_WORDS : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CURRENT_BIN_ID_MIN { + struct { +#if defined(qLittleEndian) + unsigned int COLUMN : 3; + unsigned int ROW : 3; + unsigned int GUARD_BAND : 3; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int GUARD_BAND : 3; + unsigned int ROW : 3; + unsigned int COLUMN : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CURRENT_BIN_ID_MAX { + struct { +#if defined(qLittleEndian) + unsigned int COLUMN : 3; + unsigned int ROW : 3; + unsigned int GUARD_BAND : 3; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int GUARD_BAND : 3; + unsigned int ROW : 3; + unsigned int COLUMN : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_IMMED_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_MAX_VTX_INDX { + struct { +#if defined(qLittleEndian) + unsigned int MAX_INDX : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int MAX_INDX : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_MIN_VTX_INDX { + struct { +#if defined(qLittleEndian) + unsigned int MIN_INDX : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int MIN_INDX : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_INDX_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int INDX_OFFSET : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int INDX_OFFSET : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_VERTEX_REUSE_BLOCK_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int VTX_REUSE_DEPTH : 3; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int VTX_REUSE_DEPTH : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_OUT_DEALLOC_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int DEALLOC_DIST : 2; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int DEALLOC_DIST : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_MULTI_PRIM_IB_RESET_INDX { + struct { +#if defined(qLittleEndian) + unsigned int RESET_INDX : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int RESET_INDX : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_ENHANCE { + struct { +#if defined(qLittleEndian) + unsigned int MISC : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int MISC : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_VTX_VECT_EJECT_REG { + struct { +#if defined(qLittleEndian) + unsigned int PRIM_COUNT : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int PRIM_COUNT : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_LAST_COPY_STATE { + struct { +#if defined(qLittleEndian) + unsigned int SRC_STATE_ID : 1; + unsigned int : 15; + unsigned int DST_STATE_ID : 1; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int DST_STATE_ID : 1; + unsigned int : 15; + unsigned int SRC_STATE_ID : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int VGT_DEBUG_INDX : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int VGT_DEBUG_INDX : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int VGT_BUSY : 1; + unsigned int VGT_DMA_BUSY : 1; + unsigned int VGT_DMA_REQ_BUSY : 1; + unsigned int VGT_GRP_BUSY : 1; + unsigned int VGT_VR_BUSY : 1; + unsigned int VGT_BIN_BUSY : 1; + unsigned int VGT_PT_BUSY : 1; + unsigned int VGT_OUT_BUSY : 1; + unsigned int VGT_OUT_INDX_BUSY : 1; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int VGT_OUT_INDX_BUSY : 1; + unsigned int VGT_OUT_BUSY : 1; + unsigned int VGT_PT_BUSY : 1; + unsigned int VGT_BIN_BUSY : 1; + unsigned int VGT_VR_BUSY : 1; + unsigned int VGT_GRP_BUSY : 1; + unsigned int VGT_DMA_REQ_BUSY : 1; + unsigned int VGT_DMA_BUSY : 1; + unsigned int VGT_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG0 { + struct { +#if defined(qLittleEndian) + unsigned int te_grp_busy : 1; + unsigned int pt_grp_busy : 1; + unsigned int vr_grp_busy : 1; + unsigned int dma_request_busy : 1; + unsigned int out_busy : 1; + unsigned int grp_backend_busy : 1; + unsigned int grp_busy : 1; + unsigned int dma_busy : 1; + unsigned int rbiu_dma_request_busy : 1; + unsigned int rbiu_busy : 1; + unsigned int vgt_no_dma_busy_extended : 1; + unsigned int vgt_no_dma_busy : 1; + unsigned int vgt_busy_extended : 1; + unsigned int vgt_busy : 1; + unsigned int rbbm_skid_fifo_busy_out : 1; + unsigned int VGT_RBBM_no_dma_busy : 1; + unsigned int VGT_RBBM_busy : 1; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int VGT_RBBM_busy : 1; + unsigned int VGT_RBBM_no_dma_busy : 1; + unsigned int rbbm_skid_fifo_busy_out : 1; + unsigned int vgt_busy : 1; + unsigned int vgt_busy_extended : 1; + unsigned int vgt_no_dma_busy : 1; + unsigned int vgt_no_dma_busy_extended : 1; + unsigned int rbiu_busy : 1; + unsigned int rbiu_dma_request_busy : 1; + unsigned int dma_busy : 1; + unsigned int grp_busy : 1; + unsigned int grp_backend_busy : 1; + unsigned int out_busy : 1; + unsigned int dma_request_busy : 1; + unsigned int vr_grp_busy : 1; + unsigned int pt_grp_busy : 1; + unsigned int te_grp_busy : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG1 { + struct { +#if defined(qLittleEndian) + unsigned int out_te_data_read : 1; + unsigned int te_out_data_valid : 1; + unsigned int out_pt_prim_read : 1; + unsigned int pt_out_prim_valid : 1; + unsigned int out_pt_data_read : 1; + unsigned int pt_out_indx_valid : 1; + unsigned int out_vr_prim_read : 1; + unsigned int vr_out_prim_valid : 1; + unsigned int out_vr_indx_read : 1; + unsigned int vr_out_indx_valid : 1; + unsigned int te_grp_read : 1; + unsigned int grp_te_valid : 1; + unsigned int pt_grp_read : 1; + unsigned int grp_pt_valid : 1; + unsigned int vr_grp_read : 1; + unsigned int grp_vr_valid : 1; + unsigned int grp_dma_read : 1; + unsigned int dma_grp_valid : 1; + unsigned int grp_rbiu_di_read : 1; + unsigned int rbiu_grp_di_valid : 1; + unsigned int MH_VGT_rtr : 1; + unsigned int VGT_MH_send : 1; + unsigned int PA_VGT_clip_s_rtr : 1; + unsigned int VGT_PA_clip_s_send : 1; + unsigned int PA_VGT_clip_p_rtr : 1; + unsigned int VGT_PA_clip_p_send : 1; + unsigned int PA_VGT_clip_v_rtr : 1; + unsigned int VGT_PA_clip_v_send : 1; + unsigned int SQ_VGT_rtr : 1; + unsigned int VGT_SQ_send : 1; + unsigned int mh_vgt_tag_7_q : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int mh_vgt_tag_7_q : 1; + unsigned int VGT_SQ_send : 1; + unsigned int SQ_VGT_rtr : 1; + unsigned int VGT_PA_clip_v_send : 1; + unsigned int PA_VGT_clip_v_rtr : 1; + unsigned int VGT_PA_clip_p_send : 1; + unsigned int PA_VGT_clip_p_rtr : 1; + unsigned int VGT_PA_clip_s_send : 1; + unsigned int PA_VGT_clip_s_rtr : 1; + unsigned int VGT_MH_send : 1; + unsigned int MH_VGT_rtr : 1; + unsigned int rbiu_grp_di_valid : 1; + unsigned int grp_rbiu_di_read : 1; + unsigned int dma_grp_valid : 1; + unsigned int grp_dma_read : 1; + unsigned int grp_vr_valid : 1; + unsigned int vr_grp_read : 1; + unsigned int grp_pt_valid : 1; + unsigned int pt_grp_read : 1; + unsigned int grp_te_valid : 1; + unsigned int te_grp_read : 1; + unsigned int vr_out_indx_valid : 1; + unsigned int out_vr_indx_read : 1; + unsigned int vr_out_prim_valid : 1; + unsigned int out_vr_prim_read : 1; + unsigned int pt_out_indx_valid : 1; + unsigned int out_pt_data_read : 1; + unsigned int pt_out_prim_valid : 1; + unsigned int out_pt_prim_read : 1; + unsigned int te_out_data_valid : 1; + unsigned int out_te_data_read : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG3 { + struct { +#if defined(qLittleEndian) + unsigned int vgt_clk_en : 1; + unsigned int reg_fifos_clk_en : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int reg_fifos_clk_en : 1; + unsigned int vgt_clk_en : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG6 { + struct { +#if defined(qLittleEndian) + unsigned int shifter_byte_count_q : 5; + unsigned int right_word_indx_q : 5; + unsigned int input_data_valid : 1; + unsigned int input_data_xfer : 1; + unsigned int next_shift_is_vect_1_q : 1; + unsigned int next_shift_is_vect_1_d : 1; + unsigned int next_shift_is_vect_1_pre_d : 1; + unsigned int space_avail_from_shift : 1; + unsigned int shifter_first_load : 1; + unsigned int di_state_sel_q : 1; + unsigned int shifter_waiting_for_first_load_q : 1; + unsigned int di_first_group_flag_q : 1; + unsigned int di_event_flag_q : 1; + unsigned int read_draw_initiator : 1; + unsigned int loading_di_requires_shifter : 1; + unsigned int last_shift_of_packet : 1; + unsigned int last_decr_of_packet : 1; + unsigned int extract_vector : 1; + unsigned int shift_vect_rtr : 1; + unsigned int destination_rtr : 1; + unsigned int grp_trigger : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int grp_trigger : 1; + unsigned int destination_rtr : 1; + unsigned int shift_vect_rtr : 1; + unsigned int extract_vector : 1; + unsigned int last_decr_of_packet : 1; + unsigned int last_shift_of_packet : 1; + unsigned int loading_di_requires_shifter : 1; + unsigned int read_draw_initiator : 1; + unsigned int di_event_flag_q : 1; + unsigned int di_first_group_flag_q : 1; + unsigned int shifter_waiting_for_first_load_q : 1; + unsigned int di_state_sel_q : 1; + unsigned int shifter_first_load : 1; + unsigned int space_avail_from_shift : 1; + unsigned int next_shift_is_vect_1_pre_d : 1; + unsigned int next_shift_is_vect_1_d : 1; + unsigned int next_shift_is_vect_1_q : 1; + unsigned int input_data_xfer : 1; + unsigned int input_data_valid : 1; + unsigned int right_word_indx_q : 5; + unsigned int shifter_byte_count_q : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG7 { + struct { +#if defined(qLittleEndian) + unsigned int di_index_counter_q : 16; + unsigned int shift_amount_no_extract : 4; + unsigned int shift_amount_extract : 4; + unsigned int di_prim_type_q : 6; + unsigned int current_source_sel : 2; +#else /* !defined(qLittleEndian) */ + unsigned int current_source_sel : 2; + unsigned int di_prim_type_q : 6; + unsigned int shift_amount_extract : 4; + unsigned int shift_amount_no_extract : 4; + unsigned int di_index_counter_q : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG8 { + struct { +#if defined(qLittleEndian) + unsigned int current_source_sel : 2; + unsigned int left_word_indx_q : 5; + unsigned int input_data_cnt : 5; + unsigned int input_data_lsw : 5; + unsigned int input_data_msw : 5; + unsigned int next_small_stride_shift_limit_q : 5; + unsigned int current_small_stride_shift_limit_q : 5; +#else /* !defined(qLittleEndian) */ + unsigned int current_small_stride_shift_limit_q : 5; + unsigned int next_small_stride_shift_limit_q : 5; + unsigned int input_data_msw : 5; + unsigned int input_data_lsw : 5; + unsigned int input_data_cnt : 5; + unsigned int left_word_indx_q : 5; + unsigned int current_source_sel : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG9 { + struct { +#if defined(qLittleEndian) + unsigned int next_stride_q : 5; + unsigned int next_stride_d : 5; + unsigned int current_shift_q : 5; + unsigned int current_shift_d : 5; + unsigned int current_stride_q : 5; + unsigned int current_stride_d : 5; + unsigned int grp_trigger : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int grp_trigger : 1; + unsigned int current_stride_d : 5; + unsigned int current_stride_q : 5; + unsigned int current_shift_d : 5; + unsigned int current_shift_q : 5; + unsigned int next_stride_d : 5; + unsigned int next_stride_q : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG10 { + struct { +#if defined(qLittleEndian) + unsigned int temp_derived_di_prim_type_t0 : 1; + unsigned int temp_derived_di_small_index_t0 : 1; + unsigned int temp_derived_di_cull_enable_t0 : 1; + unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : 1; + unsigned int di_state_sel_q : 1; + unsigned int last_decr_of_packet : 1; + unsigned int bin_valid : 1; + unsigned int read_block : 1; + unsigned int grp_bgrp_last_bit_read : 1; + unsigned int last_bit_enable_q : 1; + unsigned int last_bit_end_di_q : 1; + unsigned int selected_data : 8; + unsigned int mask_input_data : 8; + unsigned int gap_q : 1; + unsigned int temp_mini_reset_z : 1; + unsigned int temp_mini_reset_y : 1; + unsigned int temp_mini_reset_x : 1; + unsigned int grp_trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int grp_trigger : 1; + unsigned int temp_mini_reset_x : 1; + unsigned int temp_mini_reset_y : 1; + unsigned int temp_mini_reset_z : 1; + unsigned int gap_q : 1; + unsigned int mask_input_data : 8; + unsigned int selected_data : 8; + unsigned int last_bit_end_di_q : 1; + unsigned int last_bit_enable_q : 1; + unsigned int grp_bgrp_last_bit_read : 1; + unsigned int read_block : 1; + unsigned int bin_valid : 1; + unsigned int last_decr_of_packet : 1; + unsigned int di_state_sel_q : 1; + unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : 1; + unsigned int temp_derived_di_cull_enable_t0 : 1; + unsigned int temp_derived_di_small_index_t0 : 1; + unsigned int temp_derived_di_prim_type_t0 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG12 { + struct { +#if defined(qLittleEndian) + unsigned int shifter_byte_count_q : 5; + unsigned int right_word_indx_q : 5; + unsigned int input_data_valid : 1; + unsigned int input_data_xfer : 1; + unsigned int next_shift_is_vect_1_q : 1; + unsigned int next_shift_is_vect_1_d : 1; + unsigned int next_shift_is_vect_1_pre_d : 1; + unsigned int space_avail_from_shift : 1; + unsigned int shifter_first_load : 1; + unsigned int di_state_sel_q : 1; + unsigned int shifter_waiting_for_first_load_q : 1; + unsigned int di_first_group_flag_q : 1; + unsigned int di_event_flag_q : 1; + unsigned int read_draw_initiator : 1; + unsigned int loading_di_requires_shifter : 1; + unsigned int last_shift_of_packet : 1; + unsigned int last_decr_of_packet : 1; + unsigned int extract_vector : 1; + unsigned int shift_vect_rtr : 1; + unsigned int destination_rtr : 1; + unsigned int bgrp_trigger : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int bgrp_trigger : 1; + unsigned int destination_rtr : 1; + unsigned int shift_vect_rtr : 1; + unsigned int extract_vector : 1; + unsigned int last_decr_of_packet : 1; + unsigned int last_shift_of_packet : 1; + unsigned int loading_di_requires_shifter : 1; + unsigned int read_draw_initiator : 1; + unsigned int di_event_flag_q : 1; + unsigned int di_first_group_flag_q : 1; + unsigned int shifter_waiting_for_first_load_q : 1; + unsigned int di_state_sel_q : 1; + unsigned int shifter_first_load : 1; + unsigned int space_avail_from_shift : 1; + unsigned int next_shift_is_vect_1_pre_d : 1; + unsigned int next_shift_is_vect_1_d : 1; + unsigned int next_shift_is_vect_1_q : 1; + unsigned int input_data_xfer : 1; + unsigned int input_data_valid : 1; + unsigned int right_word_indx_q : 5; + unsigned int shifter_byte_count_q : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG13 { + struct { +#if defined(qLittleEndian) + unsigned int di_index_counter_q : 16; + unsigned int shift_amount_no_extract : 4; + unsigned int shift_amount_extract : 4; + unsigned int di_prim_type_q : 6; + unsigned int current_source_sel : 2; +#else /* !defined(qLittleEndian) */ + unsigned int current_source_sel : 2; + unsigned int di_prim_type_q : 6; + unsigned int shift_amount_extract : 4; + unsigned int shift_amount_no_extract : 4; + unsigned int di_index_counter_q : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG14 { + struct { +#if defined(qLittleEndian) + unsigned int current_source_sel : 2; + unsigned int left_word_indx_q : 5; + unsigned int input_data_cnt : 5; + unsigned int input_data_lsw : 5; + unsigned int input_data_msw : 5; + unsigned int next_small_stride_shift_limit_q : 5; + unsigned int current_small_stride_shift_limit_q : 5; +#else /* !defined(qLittleEndian) */ + unsigned int current_small_stride_shift_limit_q : 5; + unsigned int next_small_stride_shift_limit_q : 5; + unsigned int input_data_msw : 5; + unsigned int input_data_lsw : 5; + unsigned int input_data_cnt : 5; + unsigned int left_word_indx_q : 5; + unsigned int current_source_sel : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG15 { + struct { +#if defined(qLittleEndian) + unsigned int next_stride_q : 5; + unsigned int next_stride_d : 5; + unsigned int current_shift_q : 5; + unsigned int current_shift_d : 5; + unsigned int current_stride_q : 5; + unsigned int current_stride_d : 5; + unsigned int bgrp_trigger : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int bgrp_trigger : 1; + unsigned int current_stride_d : 5; + unsigned int current_stride_q : 5; + unsigned int current_shift_d : 5; + unsigned int current_shift_q : 5; + unsigned int next_stride_d : 5; + unsigned int next_stride_q : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG16 { + struct { +#if defined(qLittleEndian) + unsigned int bgrp_cull_fetch_fifo_full : 1; + unsigned int bgrp_cull_fetch_fifo_empty : 1; + unsigned int dma_bgrp_cull_fetch_read : 1; + unsigned int bgrp_cull_fetch_fifo_we : 1; + unsigned int bgrp_byte_mask_fifo_full : 1; + unsigned int bgrp_byte_mask_fifo_empty : 1; + unsigned int bgrp_byte_mask_fifo_re_q : 1; + unsigned int bgrp_byte_mask_fifo_we : 1; + unsigned int bgrp_dma_mask_kill : 1; + unsigned int bgrp_grp_bin_valid : 1; + unsigned int rst_last_bit : 1; + unsigned int current_state_q : 1; + unsigned int old_state_q : 1; + unsigned int old_state_en : 1; + unsigned int prev_last_bit_q : 1; + unsigned int dbl_last_bit_q : 1; + unsigned int last_bit_block_q : 1; + unsigned int ast_bit_block2_q : 1; + unsigned int load_empty_reg : 1; + unsigned int bgrp_grp_byte_mask_rdata : 8; + unsigned int dma_bgrp_dma_data_fifo_rptr : 2; + unsigned int top_di_pre_fetch_cull_enable : 1; + unsigned int top_di_grp_cull_enable_q : 1; + unsigned int bgrp_trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int bgrp_trigger : 1; + unsigned int top_di_grp_cull_enable_q : 1; + unsigned int top_di_pre_fetch_cull_enable : 1; + unsigned int dma_bgrp_dma_data_fifo_rptr : 2; + unsigned int bgrp_grp_byte_mask_rdata : 8; + unsigned int load_empty_reg : 1; + unsigned int ast_bit_block2_q : 1; + unsigned int last_bit_block_q : 1; + unsigned int dbl_last_bit_q : 1; + unsigned int prev_last_bit_q : 1; + unsigned int old_state_en : 1; + unsigned int old_state_q : 1; + unsigned int current_state_q : 1; + unsigned int rst_last_bit : 1; + unsigned int bgrp_grp_bin_valid : 1; + unsigned int bgrp_dma_mask_kill : 1; + unsigned int bgrp_byte_mask_fifo_we : 1; + unsigned int bgrp_byte_mask_fifo_re_q : 1; + unsigned int bgrp_byte_mask_fifo_empty : 1; + unsigned int bgrp_byte_mask_fifo_full : 1; + unsigned int bgrp_cull_fetch_fifo_we : 1; + unsigned int dma_bgrp_cull_fetch_read : 1; + unsigned int bgrp_cull_fetch_fifo_empty : 1; + unsigned int bgrp_cull_fetch_fifo_full : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG17 { + struct { +#if defined(qLittleEndian) + unsigned int save_read_q : 1; + unsigned int extend_read_q : 1; + unsigned int grp_indx_size : 2; + unsigned int cull_prim_true : 1; + unsigned int reset_bit2_q : 1; + unsigned int reset_bit1_q : 1; + unsigned int first_reg_first_q : 1; + unsigned int check_second_reg : 1; + unsigned int check_first_reg : 1; + unsigned int bgrp_cull_fetch_fifo_wdata : 1; + unsigned int save_cull_fetch_data2_q : 1; + unsigned int save_cull_fetch_data1_q : 1; + unsigned int save_byte_mask_data2_q : 1; + unsigned int save_byte_mask_data1_q : 1; + unsigned int to_second_reg_q : 1; + unsigned int roll_over_msk_q : 1; + unsigned int max_msk_ptr_q : 7; + unsigned int min_msk_ptr_q : 7; + unsigned int bgrp_trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int bgrp_trigger : 1; + unsigned int min_msk_ptr_q : 7; + unsigned int max_msk_ptr_q : 7; + unsigned int roll_over_msk_q : 1; + unsigned int to_second_reg_q : 1; + unsigned int save_byte_mask_data1_q : 1; + unsigned int save_byte_mask_data2_q : 1; + unsigned int save_cull_fetch_data1_q : 1; + unsigned int save_cull_fetch_data2_q : 1; + unsigned int bgrp_cull_fetch_fifo_wdata : 1; + unsigned int check_first_reg : 1; + unsigned int check_second_reg : 1; + unsigned int first_reg_first_q : 1; + unsigned int reset_bit1_q : 1; + unsigned int reset_bit2_q : 1; + unsigned int cull_prim_true : 1; + unsigned int grp_indx_size : 2; + unsigned int extend_read_q : 1; + unsigned int save_read_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG18 { + struct { +#if defined(qLittleEndian) + unsigned int dma_data_fifo_mem_raddr : 6; + unsigned int dma_data_fifo_mem_waddr : 6; + unsigned int dma_bgrp_byte_mask_fifo_re : 1; + unsigned int dma_bgrp_dma_data_fifo_rptr : 2; + unsigned int dma_mem_full : 1; + unsigned int dma_ram_re : 1; + unsigned int dma_ram_we : 1; + unsigned int dma_mem_empty : 1; + unsigned int dma_data_fifo_mem_re : 1; + unsigned int dma_data_fifo_mem_we : 1; + unsigned int bin_mem_full : 1; + unsigned int bin_ram_we : 1; + unsigned int bin_ram_re : 1; + unsigned int bin_mem_empty : 1; + unsigned int start_bin_req : 1; + unsigned int fetch_cull_not_used : 1; + unsigned int dma_req_xfer : 1; + unsigned int have_valid_bin_req : 1; + unsigned int have_valid_dma_req : 1; + unsigned int bgrp_dma_di_grp_cull_enable : 1; + unsigned int bgrp_dma_di_pre_fetch_cull_enable : 1; +#else /* !defined(qLittleEndian) */ + unsigned int bgrp_dma_di_pre_fetch_cull_enable : 1; + unsigned int bgrp_dma_di_grp_cull_enable : 1; + unsigned int have_valid_dma_req : 1; + unsigned int have_valid_bin_req : 1; + unsigned int dma_req_xfer : 1; + unsigned int fetch_cull_not_used : 1; + unsigned int start_bin_req : 1; + unsigned int bin_mem_empty : 1; + unsigned int bin_ram_re : 1; + unsigned int bin_ram_we : 1; + unsigned int bin_mem_full : 1; + unsigned int dma_data_fifo_mem_we : 1; + unsigned int dma_data_fifo_mem_re : 1; + unsigned int dma_mem_empty : 1; + unsigned int dma_ram_we : 1; + unsigned int dma_ram_re : 1; + unsigned int dma_mem_full : 1; + unsigned int dma_bgrp_dma_data_fifo_rptr : 2; + unsigned int dma_bgrp_byte_mask_fifo_re : 1; + unsigned int dma_data_fifo_mem_waddr : 6; + unsigned int dma_data_fifo_mem_raddr : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG20 { + struct { +#if defined(qLittleEndian) + unsigned int prim_side_indx_valid : 1; + unsigned int indx_side_fifo_empty : 1; + unsigned int indx_side_fifo_re : 1; + unsigned int indx_side_fifo_we : 1; + unsigned int indx_side_fifo_full : 1; + unsigned int prim_buffer_empty : 1; + unsigned int prim_buffer_re : 1; + unsigned int prim_buffer_we : 1; + unsigned int prim_buffer_full : 1; + unsigned int indx_buffer_empty : 1; + unsigned int indx_buffer_re : 1; + unsigned int indx_buffer_we : 1; + unsigned int indx_buffer_full : 1; + unsigned int hold_prim : 1; + unsigned int sent_cnt : 4; + unsigned int start_of_vtx_vector : 1; + unsigned int clip_s_pre_hold_prim : 1; + unsigned int clip_p_pre_hold_prim : 1; + unsigned int buffered_prim_type_event : 5; + unsigned int out_trigger : 1; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int out_trigger : 1; + unsigned int buffered_prim_type_event : 5; + unsigned int clip_p_pre_hold_prim : 1; + unsigned int clip_s_pre_hold_prim : 1; + unsigned int start_of_vtx_vector : 1; + unsigned int sent_cnt : 4; + unsigned int hold_prim : 1; + unsigned int indx_buffer_full : 1; + unsigned int indx_buffer_we : 1; + unsigned int indx_buffer_re : 1; + unsigned int indx_buffer_empty : 1; + unsigned int prim_buffer_full : 1; + unsigned int prim_buffer_we : 1; + unsigned int prim_buffer_re : 1; + unsigned int prim_buffer_empty : 1; + unsigned int indx_side_fifo_full : 1; + unsigned int indx_side_fifo_we : 1; + unsigned int indx_side_fifo_re : 1; + unsigned int indx_side_fifo_empty : 1; + unsigned int prim_side_indx_valid : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG21 { + struct { +#if defined(qLittleEndian) + unsigned int null_terminate_vtx_vector : 1; + unsigned int prim_end_of_vtx_vect_flags : 3; + unsigned int alloc_counter_q : 3; + unsigned int curr_slot_in_vtx_vect_q : 3; + unsigned int int_vtx_counter_q : 4; + unsigned int curr_dealloc_distance_q : 4; + unsigned int new_packet_q : 1; + unsigned int new_allocate_q : 1; + unsigned int num_new_unique_rel_indx : 2; + unsigned int inserted_null_prim_q : 1; + unsigned int insert_null_prim : 1; + unsigned int buffered_prim_eop_mux : 1; + unsigned int prim_buffer_empty_mux : 1; + unsigned int buffered_thread_size : 1; + unsigned int : 4; + unsigned int out_trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int out_trigger : 1; + unsigned int : 4; + unsigned int buffered_thread_size : 1; + unsigned int prim_buffer_empty_mux : 1; + unsigned int buffered_prim_eop_mux : 1; + unsigned int insert_null_prim : 1; + unsigned int inserted_null_prim_q : 1; + unsigned int num_new_unique_rel_indx : 2; + unsigned int new_allocate_q : 1; + unsigned int new_packet_q : 1; + unsigned int curr_dealloc_distance_q : 4; + unsigned int int_vtx_counter_q : 4; + unsigned int curr_slot_in_vtx_vect_q : 3; + unsigned int alloc_counter_q : 3; + unsigned int prim_end_of_vtx_vect_flags : 3; + unsigned int null_terminate_vtx_vector : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CRC_SQ_DATA { + struct { +#if defined(qLittleEndian) + unsigned int CRC : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CRC : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CRC_SQ_CTRL { + struct { +#if defined(qLittleEndian) + unsigned int CRC : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CRC : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER2_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER3_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER2_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER3_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER2_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER3_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TC_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int L2_INVALIDATE : 1; + unsigned int : 17; + unsigned int TC_L2_HIT_MISS : 2; + unsigned int : 11; + unsigned int TC_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TC_BUSY : 1; + unsigned int : 11; + unsigned int TC_L2_HIT_MISS : 2; + unsigned int : 17; + unsigned int L2_INVALIDATE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int SPARE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int SPARE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int TCO_READ_LATENCY_FIFO_PROG_DEPTH : 8; + unsigned int ETC_COLOR_ENDIAN : 1; + unsigned int SPARE : 23; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 23; + unsigned int ETC_COLOR_ENDIAN : 1; + unsigned int TCO_READ_LATENCY_FIFO_PROG_DEPTH : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP_TC_CLKGATE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int TP_BUSY_EXTEND : 3; + unsigned int TC_BUSY_EXTEND : 3; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int TC_BUSY_EXTEND : 3; + unsigned int TP_BUSY_EXTEND : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TPC_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int TPC_INPUT_BUSY : 1; + unsigned int TPC_TC_FIFO_BUSY : 1; + unsigned int TPC_STATE_FIFO_BUSY : 1; + unsigned int TPC_FETCH_FIFO_BUSY : 1; + unsigned int TPC_WALKER_PIPE_BUSY : 1; + unsigned int TPC_WALK_FIFO_BUSY : 1; + unsigned int TPC_WALKER_BUSY : 1; + unsigned int : 1; + unsigned int TPC_ALIGNER_PIPE_BUSY : 1; + unsigned int TPC_ALIGN_FIFO_BUSY : 1; + unsigned int TPC_ALIGNER_BUSY : 1; + unsigned int : 1; + unsigned int TPC_RR_FIFO_BUSY : 1; + unsigned int TPC_BLEND_PIPE_BUSY : 1; + unsigned int TPC_OUT_FIFO_BUSY : 1; + unsigned int TPC_BLEND_BUSY : 1; + unsigned int TF_TW_RTS : 1; + unsigned int TF_TW_STATE_RTS : 1; + unsigned int : 1; + unsigned int TF_TW_RTR : 1; + unsigned int TW_TA_RTS : 1; + unsigned int TW_TA_TT_RTS : 1; + unsigned int TW_TA_LAST_RTS : 1; + unsigned int TW_TA_RTR : 1; + unsigned int TA_TB_RTS : 1; + unsigned int TA_TB_TT_RTS : 1; + unsigned int : 1; + unsigned int TA_TB_RTR : 1; + unsigned int TA_TF_RTS : 1; + unsigned int TA_TF_TC_FIFO_REN : 1; + unsigned int TP_SQ_DEC : 1; + unsigned int TPC_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TPC_BUSY : 1; + unsigned int TP_SQ_DEC : 1; + unsigned int TA_TF_TC_FIFO_REN : 1; + unsigned int TA_TF_RTS : 1; + unsigned int TA_TB_RTR : 1; + unsigned int : 1; + unsigned int TA_TB_TT_RTS : 1; + unsigned int TA_TB_RTS : 1; + unsigned int TW_TA_RTR : 1; + unsigned int TW_TA_LAST_RTS : 1; + unsigned int TW_TA_TT_RTS : 1; + unsigned int TW_TA_RTS : 1; + unsigned int TF_TW_RTR : 1; + unsigned int : 1; + unsigned int TF_TW_STATE_RTS : 1; + unsigned int TF_TW_RTS : 1; + unsigned int TPC_BLEND_BUSY : 1; + unsigned int TPC_OUT_FIFO_BUSY : 1; + unsigned int TPC_BLEND_PIPE_BUSY : 1; + unsigned int TPC_RR_FIFO_BUSY : 1; + unsigned int : 1; + unsigned int TPC_ALIGNER_BUSY : 1; + unsigned int TPC_ALIGN_FIFO_BUSY : 1; + unsigned int TPC_ALIGNER_PIPE_BUSY : 1; + unsigned int : 1; + unsigned int TPC_WALKER_BUSY : 1; + unsigned int TPC_WALK_FIFO_BUSY : 1; + unsigned int TPC_WALKER_PIPE_BUSY : 1; + unsigned int TPC_FETCH_FIFO_BUSY : 1; + unsigned int TPC_STATE_FIFO_BUSY : 1; + unsigned int TPC_TC_FIFO_BUSY : 1; + unsigned int TPC_INPUT_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TPC_DEBUG0 { + struct { +#if defined(qLittleEndian) + unsigned int LOD_CNTL : 2; + unsigned int IC_CTR : 2; + unsigned int WALKER_CNTL : 4; + unsigned int ALIGNER_CNTL : 3; + unsigned int : 1; + unsigned int PREV_TC_STATE_VALID : 1; + unsigned int : 3; + unsigned int WALKER_STATE : 10; + unsigned int ALIGNER_STATE : 2; + unsigned int : 1; + unsigned int REG_CLK_EN : 1; + unsigned int TPC_CLK_EN : 1; + unsigned int SQ_TP_WAKEUP : 1; +#else /* !defined(qLittleEndian) */ + unsigned int SQ_TP_WAKEUP : 1; + unsigned int TPC_CLK_EN : 1; + unsigned int REG_CLK_EN : 1; + unsigned int : 1; + unsigned int ALIGNER_STATE : 2; + unsigned int WALKER_STATE : 10; + unsigned int : 3; + unsigned int PREV_TC_STATE_VALID : 1; + unsigned int : 1; + unsigned int ALIGNER_CNTL : 3; + unsigned int WALKER_CNTL : 4; + unsigned int IC_CTR : 2; + unsigned int LOD_CNTL : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TPC_DEBUG1 { + struct { +#if defined(qLittleEndian) + unsigned int UNUSED : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int UNUSED : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TPC_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_PRECISION : 1; + unsigned int SPARE : 31; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 31; + unsigned int BLEND_PRECISION : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int TP_INPUT_BUSY : 1; + unsigned int TP_LOD_BUSY : 1; + unsigned int TP_LOD_FIFO_BUSY : 1; + unsigned int TP_ADDR_BUSY : 1; + unsigned int TP_ALIGN_FIFO_BUSY : 1; + unsigned int TP_ALIGNER_BUSY : 1; + unsigned int TP_TC_FIFO_BUSY : 1; + unsigned int TP_RR_FIFO_BUSY : 1; + unsigned int TP_FETCH_BUSY : 1; + unsigned int TP_CH_BLEND_BUSY : 1; + unsigned int TP_TT_BUSY : 1; + unsigned int TP_HICOLOR_BUSY : 1; + unsigned int TP_BLEND_BUSY : 1; + unsigned int TP_OUT_FIFO_BUSY : 1; + unsigned int TP_OUTPUT_BUSY : 1; + unsigned int : 1; + unsigned int IN_LC_RTS : 1; + unsigned int LC_LA_RTS : 1; + unsigned int LA_FL_RTS : 1; + unsigned int FL_TA_RTS : 1; + unsigned int TA_FA_RTS : 1; + unsigned int TA_FA_TT_RTS : 1; + unsigned int FA_AL_RTS : 1; + unsigned int FA_AL_TT_RTS : 1; + unsigned int AL_TF_RTS : 1; + unsigned int AL_TF_TT_RTS : 1; + unsigned int TF_TB_RTS : 1; + unsigned int TF_TB_TT_RTS : 1; + unsigned int TB_TT_RTS : 1; + unsigned int TB_TT_TT_RESET : 1; + unsigned int TB_TO_RTS : 1; + unsigned int TP_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TP_BUSY : 1; + unsigned int TB_TO_RTS : 1; + unsigned int TB_TT_TT_RESET : 1; + unsigned int TB_TT_RTS : 1; + unsigned int TF_TB_TT_RTS : 1; + unsigned int TF_TB_RTS : 1; + unsigned int AL_TF_TT_RTS : 1; + unsigned int AL_TF_RTS : 1; + unsigned int FA_AL_TT_RTS : 1; + unsigned int FA_AL_RTS : 1; + unsigned int TA_FA_TT_RTS : 1; + unsigned int TA_FA_RTS : 1; + unsigned int FL_TA_RTS : 1; + unsigned int LA_FL_RTS : 1; + unsigned int LC_LA_RTS : 1; + unsigned int IN_LC_RTS : 1; + unsigned int : 1; + unsigned int TP_OUTPUT_BUSY : 1; + unsigned int TP_OUT_FIFO_BUSY : 1; + unsigned int TP_BLEND_BUSY : 1; + unsigned int TP_HICOLOR_BUSY : 1; + unsigned int TP_TT_BUSY : 1; + unsigned int TP_CH_BLEND_BUSY : 1; + unsigned int TP_FETCH_BUSY : 1; + unsigned int TP_RR_FIFO_BUSY : 1; + unsigned int TP_TC_FIFO_BUSY : 1; + unsigned int TP_ALIGNER_BUSY : 1; + unsigned int TP_ALIGN_FIFO_BUSY : 1; + unsigned int TP_ADDR_BUSY : 1; + unsigned int TP_LOD_FIFO_BUSY : 1; + unsigned int TP_LOD_BUSY : 1; + unsigned int TP_INPUT_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int Q_LOD_CNTL : 2; + unsigned int : 1; + unsigned int Q_SQ_TP_WAKEUP : 1; + unsigned int FL_TA_ADDRESSER_CNTL : 17; + unsigned int REG_CLK_EN : 1; + unsigned int PERF_CLK_EN : 1; + unsigned int TP_CLK_EN : 1; + unsigned int Q_WALKER_CNTL : 4; + unsigned int Q_ALIGNER_CNTL : 3; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int Q_ALIGNER_CNTL : 3; + unsigned int Q_WALKER_CNTL : 4; + unsigned int TP_CLK_EN : 1; + unsigned int PERF_CLK_EN : 1; + unsigned int REG_CLK_EN : 1; + unsigned int FL_TA_ADDRESSER_CNTL : 17; + unsigned int Q_SQ_TP_WAKEUP : 1; + unsigned int : 1; + unsigned int Q_LOD_CNTL : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int TT_MODE : 1; + unsigned int VFETCH_ADDRESS_MODE : 1; + unsigned int SPARE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 30; + unsigned int VFETCH_ADDRESS_MODE : 1; + unsigned int TT_MODE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER2_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER3_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER4_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER5_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER6_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER7_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER8_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER9_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER10_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER11_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER2_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER3_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER4_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER5_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER6_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER7_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER8_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER9_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER10_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER11_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER2_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER3_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER4_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER5_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER6_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER7_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER8_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER9_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER10_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER11_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 6; + unsigned int not_MH_TC_rtr : 1; + unsigned int TC_MH_send : 1; + unsigned int not_FG0_rtr : 1; + unsigned int : 3; + unsigned int not_TCB_TCO_rtr : 1; + unsigned int TCB_ff_stall : 1; + unsigned int TCB_miss_stall : 1; + unsigned int TCA_TCB_stall : 1; + unsigned int PF0_stall : 1; + unsigned int : 3; + unsigned int TP0_full : 1; + unsigned int : 3; + unsigned int TPC_full : 1; + unsigned int not_TPC_rtr : 1; + unsigned int tca_state_rts : 1; + unsigned int tca_rts : 1; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int tca_rts : 1; + unsigned int tca_state_rts : 1; + unsigned int not_TPC_rtr : 1; + unsigned int TPC_full : 1; + unsigned int : 3; + unsigned int TP0_full : 1; + unsigned int : 3; + unsigned int PF0_stall : 1; + unsigned int TCA_TCB_stall : 1; + unsigned int TCB_miss_stall : 1; + unsigned int TCB_ff_stall : 1; + unsigned int not_TCB_TCO_rtr : 1; + unsigned int : 3; + unsigned int not_FG0_rtr : 1; + unsigned int TC_MH_send : 1; + unsigned int not_MH_TC_rtr : 1; + unsigned int : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCA_FIFO_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int tp0_full : 1; + unsigned int : 3; + unsigned int tpc_full : 1; + unsigned int load_tpc_fifo : 1; + unsigned int load_tp_fifos : 1; + unsigned int FW_full : 1; + unsigned int not_FW_rtr0 : 1; + unsigned int : 3; + unsigned int FW_rts0 : 1; + unsigned int : 3; + unsigned int not_FW_tpc_rtr : 1; + unsigned int FW_tpc_rts : 1; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int FW_tpc_rts : 1; + unsigned int not_FW_tpc_rtr : 1; + unsigned int : 3; + unsigned int FW_rts0 : 1; + unsigned int : 3; + unsigned int not_FW_rtr0 : 1; + unsigned int FW_full : 1; + unsigned int load_tp_fifos : 1; + unsigned int load_tpc_fifo : 1; + unsigned int tpc_full : 1; + unsigned int : 3; + unsigned int tp0_full : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCA_PROBE_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int ProbeFilter_stall : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int ProbeFilter_stall : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCA_TPC_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int captue_state_rts : 1; + unsigned int capture_tca_rts : 1; + unsigned int : 18; +#else /* !defined(qLittleEndian) */ + unsigned int : 18; + unsigned int capture_tca_rts : 1; + unsigned int captue_state_rts : 1; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_CORE_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int access512 : 1; + unsigned int tiled : 1; + unsigned int : 2; + unsigned int opcode : 3; + unsigned int : 1; + unsigned int format : 6; + unsigned int : 2; + unsigned int sector_format : 5; + unsigned int : 3; + unsigned int sector_format512 : 3; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int sector_format512 : 3; + unsigned int : 3; + unsigned int sector_format : 5; + unsigned int : 2; + unsigned int format : 6; + unsigned int : 1; + unsigned int opcode : 3; + unsigned int : 2; + unsigned int tiled : 1; + unsigned int access512 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_TAG0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int mem_read_cycle : 10; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int miss_stall : 1; + unsigned int num_feee_lines : 5; + unsigned int max_misses : 3; +#else /* !defined(qLittleEndian) */ + unsigned int max_misses : 3; + unsigned int num_feee_lines : 5; + unsigned int miss_stall : 1; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int mem_read_cycle : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_TAG1_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int mem_read_cycle : 10; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int miss_stall : 1; + unsigned int num_feee_lines : 5; + unsigned int max_misses : 3; +#else /* !defined(qLittleEndian) */ + unsigned int max_misses : 3; + unsigned int num_feee_lines : 5; + unsigned int miss_stall : 1; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int mem_read_cycle : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_TAG2_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int mem_read_cycle : 10; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int miss_stall : 1; + unsigned int num_feee_lines : 5; + unsigned int max_misses : 3; +#else /* !defined(qLittleEndian) */ + unsigned int max_misses : 3; + unsigned int num_feee_lines : 5; + unsigned int miss_stall : 1; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int mem_read_cycle : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_TAG3_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int mem_read_cycle : 10; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int miss_stall : 1; + unsigned int num_feee_lines : 5; + unsigned int max_misses : 3; +#else /* !defined(qLittleEndian) */ + unsigned int max_misses : 3; + unsigned int num_feee_lines : 5; + unsigned int miss_stall : 1; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int mem_read_cycle : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int left_done : 1; + unsigned int : 1; + unsigned int fg0_sends_left : 1; + unsigned int : 1; + unsigned int one_sector_to_go_left_q : 1; + unsigned int no_sectors_to_go : 1; + unsigned int update_left : 1; + unsigned int sector_mask_left_count_q : 5; + unsigned int sector_mask_left_q : 16; + unsigned int valid_left_q : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int valid_left_q : 1; + unsigned int sector_mask_left_q : 16; + unsigned int sector_mask_left_count_q : 5; + unsigned int update_left : 1; + unsigned int no_sectors_to_go : 1; + unsigned int one_sector_to_go_left_q : 1; + unsigned int : 1; + unsigned int fg0_sends_left : 1; + unsigned int : 1; + unsigned int left_done : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_FETCH_GEN_WALKER_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 4; + unsigned int quad_sel_left : 2; + unsigned int set_sel_left : 2; + unsigned int : 3; + unsigned int right_eq_left : 1; + unsigned int ff_fg_type512 : 3; + unsigned int busy : 1; + unsigned int setquads_to_send : 4; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int setquads_to_send : 4; + unsigned int busy : 1; + unsigned int ff_fg_type512 : 3; + unsigned int right_eq_left : 1; + unsigned int : 3; + unsigned int set_sel_left : 2; + unsigned int quad_sel_left : 2; + unsigned int : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_FETCH_GEN_PIPE0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int tc0_arb_rts : 1; + unsigned int : 1; + unsigned int ga_out_rts : 1; + unsigned int : 1; + unsigned int tc_arb_format : 12; + unsigned int tc_arb_fmsopcode : 5; + unsigned int tc_arb_request_type : 2; + unsigned int busy : 1; + unsigned int fgo_busy : 1; + unsigned int ga_busy : 1; + unsigned int mc_sel_q : 2; + unsigned int valid_q : 1; + unsigned int : 1; + unsigned int arb_RTR : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int arb_RTR : 1; + unsigned int : 1; + unsigned int valid_q : 1; + unsigned int mc_sel_q : 2; + unsigned int ga_busy : 1; + unsigned int fgo_busy : 1; + unsigned int busy : 1; + unsigned int tc_arb_request_type : 2; + unsigned int tc_arb_fmsopcode : 5; + unsigned int tc_arb_format : 12; + unsigned int : 1; + unsigned int ga_out_rts : 1; + unsigned int : 1; + unsigned int tc0_arb_rts : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_INPUT0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 16; + unsigned int empty : 1; + unsigned int full : 1; + unsigned int : 2; + unsigned int valid_q1 : 1; + unsigned int cnt_q1 : 2; + unsigned int last_send_q1 : 1; + unsigned int ip_send : 1; + unsigned int ipbuf_dxt_send : 1; + unsigned int ipbuf_busy : 1; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int ipbuf_busy : 1; + unsigned int ipbuf_dxt_send : 1; + unsigned int ip_send : 1; + unsigned int last_send_q1 : 1; + unsigned int cnt_q1 : 2; + unsigned int valid_q1 : 1; + unsigned int : 2; + unsigned int full : 1; + unsigned int empty : 1; + unsigned int : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_DEGAMMA_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int dgmm_ftfconv_dgmmen : 2; + unsigned int dgmm_ctrl_dgmm8 : 1; + unsigned int dgmm_ctrl_last_send : 1; + unsigned int dgmm_ctrl_send : 1; + unsigned int dgmm_stall : 1; + unsigned int dgmm_pstate : 1; + unsigned int : 25; +#else /* !defined(qLittleEndian) */ + unsigned int : 25; + unsigned int dgmm_pstate : 1; + unsigned int dgmm_stall : 1; + unsigned int dgmm_ctrl_send : 1; + unsigned int dgmm_ctrl_last_send : 1; + unsigned int dgmm_ctrl_dgmm8 : 1; + unsigned int dgmm_ftfconv_dgmmen : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_DXTMUX_SCTARB_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 9; + unsigned int pstate : 1; + unsigned int sctrmx_rtr : 1; + unsigned int dxtc_rtr : 1; + unsigned int : 3; + unsigned int sctrarb_multcyl_send : 1; + unsigned int sctrmx0_sctrarb_rts : 1; + unsigned int : 3; + unsigned int dxtc_sctrarb_send : 1; + unsigned int : 6; + unsigned int dxtc_dgmmpd_last_send : 1; + unsigned int dxtc_dgmmpd_send : 1; + unsigned int dcmp_mux_send : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int dcmp_mux_send : 1; + unsigned int dxtc_dgmmpd_send : 1; + unsigned int dxtc_dgmmpd_last_send : 1; + unsigned int : 6; + unsigned int dxtc_sctrarb_send : 1; + unsigned int : 3; + unsigned int sctrmx0_sctrarb_rts : 1; + unsigned int sctrarb_multcyl_send : 1; + unsigned int : 3; + unsigned int dxtc_rtr : 1; + unsigned int sctrmx_rtr : 1; + unsigned int pstate : 1; + unsigned int : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_DXTC_ARB_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 4; + unsigned int n0_stall : 1; + unsigned int pstate : 1; + unsigned int arb_dcmp01_last_send : 1; + unsigned int arb_dcmp01_cnt : 2; + unsigned int arb_dcmp01_sector : 3; + unsigned int arb_dcmp01_cacheline : 6; + unsigned int arb_dcmp01_format : 12; + unsigned int arb_dcmp01_send : 1; + unsigned int n0_dxt2_4_types : 1; +#else /* !defined(qLittleEndian) */ + unsigned int n0_dxt2_4_types : 1; + unsigned int arb_dcmp01_send : 1; + unsigned int arb_dcmp01_format : 12; + unsigned int arb_dcmp01_cacheline : 6; + unsigned int arb_dcmp01_sector : 3; + unsigned int arb_dcmp01_cnt : 2; + unsigned int arb_dcmp01_last_send : 1; + unsigned int pstate : 1; + unsigned int n0_stall : 1; + unsigned int : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_STALLS_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 10; + unsigned int not_multcyl_sctrarb_rtr : 1; + unsigned int not_sctrmx0_sctrarb_rtr : 1; + unsigned int : 5; + unsigned int not_dcmp0_arb_rtr : 1; + unsigned int not_dgmmpd_dxtc_rtr : 1; + unsigned int not_mux_dcmp_rtr : 1; + unsigned int : 11; + unsigned int not_incoming_rtr : 1; +#else /* !defined(qLittleEndian) */ + unsigned int not_incoming_rtr : 1; + unsigned int : 11; + unsigned int not_mux_dcmp_rtr : 1; + unsigned int not_dgmmpd_dxtc_rtr : 1; + unsigned int not_dcmp0_arb_rtr : 1; + unsigned int : 5; + unsigned int not_sctrmx0_sctrarb_rtr : 1; + unsigned int not_multcyl_sctrarb_rtr : 1; + unsigned int : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCO_STALLS_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int quad0_sg_crd_RTR : 1; + unsigned int quad0_rl_sg_RTR : 1; + unsigned int quad0_TCO_TCB_rtr_d : 1; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int quad0_TCO_TCB_rtr_d : 1; + unsigned int quad0_rl_sg_RTR : 1; + unsigned int quad0_sg_crd_RTR : 1; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCO_QUAD0_DEBUG0 { + struct { +#if defined(qLittleEndian) + unsigned int rl_sg_sector_format : 8; + unsigned int rl_sg_end_of_sample : 1; + unsigned int rl_sg_rtr : 1; + unsigned int rl_sg_rts : 1; + unsigned int sg_crd_end_of_sample : 1; + unsigned int sg_crd_rtr : 1; + unsigned int sg_crd_rts : 1; + unsigned int : 2; + unsigned int stageN1_valid_q : 1; + unsigned int : 7; + unsigned int read_cache_q : 1; + unsigned int cache_read_RTR : 1; + unsigned int all_sectors_written_set3 : 1; + unsigned int all_sectors_written_set2 : 1; + unsigned int all_sectors_written_set1 : 1; + unsigned int all_sectors_written_set0 : 1; + unsigned int busy : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int busy : 1; + unsigned int all_sectors_written_set0 : 1; + unsigned int all_sectors_written_set1 : 1; + unsigned int all_sectors_written_set2 : 1; + unsigned int all_sectors_written_set3 : 1; + unsigned int cache_read_RTR : 1; + unsigned int read_cache_q : 1; + unsigned int : 7; + unsigned int stageN1_valid_q : 1; + unsigned int : 2; + unsigned int sg_crd_rts : 1; + unsigned int sg_crd_rtr : 1; + unsigned int sg_crd_end_of_sample : 1; + unsigned int rl_sg_rts : 1; + unsigned int rl_sg_rtr : 1; + unsigned int rl_sg_end_of_sample : 1; + unsigned int rl_sg_sector_format : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCO_QUAD0_DEBUG1 { + struct { +#if defined(qLittleEndian) + unsigned int fifo_busy : 1; + unsigned int empty : 1; + unsigned int full : 1; + unsigned int write_enable : 1; + unsigned int fifo_write_ptr : 7; + unsigned int fifo_read_ptr : 7; + unsigned int : 2; + unsigned int cache_read_busy : 1; + unsigned int latency_fifo_busy : 1; + unsigned int input_quad_busy : 1; + unsigned int tco_quad_pipe_busy : 1; + unsigned int TCB_TCO_rtr_d : 1; + unsigned int TCB_TCO_xfc_q : 1; + unsigned int rl_sg_rtr : 1; + unsigned int rl_sg_rts : 1; + unsigned int sg_crd_rtr : 1; + unsigned int sg_crd_rts : 1; + unsigned int TCO_TCB_read_xfc : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int TCO_TCB_read_xfc : 1; + unsigned int sg_crd_rts : 1; + unsigned int sg_crd_rtr : 1; + unsigned int rl_sg_rts : 1; + unsigned int rl_sg_rtr : 1; + unsigned int TCB_TCO_xfc_q : 1; + unsigned int TCB_TCO_rtr_d : 1; + unsigned int tco_quad_pipe_busy : 1; + unsigned int input_quad_busy : 1; + unsigned int latency_fifo_busy : 1; + unsigned int cache_read_busy : 1; + unsigned int : 2; + unsigned int fifo_read_ptr : 7; + unsigned int fifo_write_ptr : 7; + unsigned int write_enable : 1; + unsigned int full : 1; + unsigned int empty : 1; + unsigned int fifo_busy : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_GPR_MANAGEMENT { + struct { +#if defined(qLittleEndian) + unsigned int REG_DYNAMIC : 1; + unsigned int : 3; + unsigned int REG_SIZE_PIX : 7; + unsigned int : 1; + unsigned int REG_SIZE_VTX : 7; + unsigned int : 13; +#else /* !defined(qLittleEndian) */ + unsigned int : 13; + unsigned int REG_SIZE_VTX : 7; + unsigned int : 1; + unsigned int REG_SIZE_PIX : 7; + unsigned int : 3; + unsigned int REG_DYNAMIC : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FLOW_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int INPUT_ARBITRATION_POLICY : 2; + unsigned int : 2; + unsigned int ONE_THREAD : 1; + unsigned int : 3; + unsigned int ONE_ALU : 1; + unsigned int : 3; + unsigned int CF_WR_BASE : 4; + unsigned int NO_PV_PS : 1; + unsigned int NO_LOOP_EXIT : 1; + unsigned int NO_CEXEC_OPTIMIZE : 1; + unsigned int TEXTURE_ARBITRATION_POLICY : 2; + unsigned int VC_ARBITRATION_POLICY : 1; + unsigned int ALU_ARBITRATION_POLICY : 1; + unsigned int NO_ARB_EJECT : 1; + unsigned int NO_CFS_EJECT : 1; + unsigned int POS_EXP_PRIORITY : 1; + unsigned int NO_EARLY_THREAD_TERMINATION : 1; + unsigned int PS_PREFETCH_COLOR_ALLOC : 1; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int PS_PREFETCH_COLOR_ALLOC : 1; + unsigned int NO_EARLY_THREAD_TERMINATION : 1; + unsigned int POS_EXP_PRIORITY : 1; + unsigned int NO_CFS_EJECT : 1; + unsigned int NO_ARB_EJECT : 1; + unsigned int ALU_ARBITRATION_POLICY : 1; + unsigned int VC_ARBITRATION_POLICY : 1; + unsigned int TEXTURE_ARBITRATION_POLICY : 2; + unsigned int NO_CEXEC_OPTIMIZE : 1; + unsigned int NO_LOOP_EXIT : 1; + unsigned int NO_PV_PS : 1; + unsigned int CF_WR_BASE : 4; + unsigned int : 3; + unsigned int ONE_ALU : 1; + unsigned int : 3; + unsigned int ONE_THREAD : 1; + unsigned int : 2; + unsigned int INPUT_ARBITRATION_POLICY : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INST_STORE_MANAGMENT { + struct { +#if defined(qLittleEndian) + unsigned int INST_BASE_PIX : 12; + unsigned int : 4; + unsigned int INST_BASE_VTX : 12; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int INST_BASE_VTX : 12; + unsigned int : 4; + unsigned int INST_BASE_PIX : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_RESOURCE_MANAGMENT { + struct { +#if defined(qLittleEndian) + unsigned int VTX_THREAD_BUF_ENTRIES : 8; + unsigned int PIX_THREAD_BUF_ENTRIES : 8; + unsigned int EXPORT_BUF_ENTRIES : 9; + unsigned int : 7; +#else /* !defined(qLittleEndian) */ + unsigned int : 7; + unsigned int EXPORT_BUF_ENTRIES : 9; + unsigned int PIX_THREAD_BUF_ENTRIES : 8; + unsigned int VTX_THREAD_BUF_ENTRIES : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_EO_RT { + struct { +#if defined(qLittleEndian) + unsigned int EO_CONSTANTS_RT : 8; + unsigned int : 8; + unsigned int EO_TSTATE_RT : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int EO_TSTATE_RT : 8; + unsigned int : 8; + unsigned int EO_CONSTANTS_RT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_MISC { + struct { +#if defined(qLittleEndian) + unsigned int DB_ALUCST_SIZE : 11; + unsigned int : 1; + unsigned int DB_TSTATE_SIZE : 8; + unsigned int DB_READ_CTX : 1; + unsigned int RESERVED : 2; + unsigned int DB_READ_MEMORY : 2; + unsigned int DB_WEN_MEMORY_0 : 1; + unsigned int DB_WEN_MEMORY_1 : 1; + unsigned int DB_WEN_MEMORY_2 : 1; + unsigned int DB_WEN_MEMORY_3 : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int DB_WEN_MEMORY_3 : 1; + unsigned int DB_WEN_MEMORY_2 : 1; + unsigned int DB_WEN_MEMORY_1 : 1; + unsigned int DB_WEN_MEMORY_0 : 1; + unsigned int DB_READ_MEMORY : 2; + unsigned int RESERVED : 2; + unsigned int DB_READ_CTX : 1; + unsigned int DB_TSTATE_SIZE : 8; + unsigned int : 1; + unsigned int DB_ALUCST_SIZE : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_ACTIVITY_METER_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int TIMEBASE : 8; + unsigned int THRESHOLD_LOW : 8; + unsigned int THRESHOLD_HIGH : 8; + unsigned int SPARE : 8; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 8; + unsigned int THRESHOLD_HIGH : 8; + unsigned int THRESHOLD_LOW : 8; + unsigned int TIMEBASE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_ACTIVITY_METER_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int PERCENT_BUSY : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERCENT_BUSY : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INPUT_ARB_PRIORITY { + struct { +#if defined(qLittleEndian) + unsigned int PC_AVAIL_WEIGHT : 3; + unsigned int PC_AVAIL_SIGN : 1; + unsigned int SX_AVAIL_WEIGHT : 3; + unsigned int SX_AVAIL_SIGN : 1; + unsigned int THRESHOLD : 10; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int THRESHOLD : 10; + unsigned int SX_AVAIL_SIGN : 1; + unsigned int SX_AVAIL_WEIGHT : 3; + unsigned int PC_AVAIL_SIGN : 1; + unsigned int PC_AVAIL_WEIGHT : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_THREAD_ARB_PRIORITY { + struct { +#if defined(qLittleEndian) + unsigned int PC_AVAIL_WEIGHT : 3; + unsigned int PC_AVAIL_SIGN : 1; + unsigned int SX_AVAIL_WEIGHT : 3; + unsigned int SX_AVAIL_SIGN : 1; + unsigned int THRESHOLD : 10; + unsigned int RESERVED : 2; + unsigned int VS_PRIORITIZE_SERIAL : 1; + unsigned int PS_PRIORITIZE_SERIAL : 1; + unsigned int USE_SERIAL_COUNT_THRESHOLD : 1; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int USE_SERIAL_COUNT_THRESHOLD : 1; + unsigned int PS_PRIORITIZE_SERIAL : 1; + unsigned int VS_PRIORITIZE_SERIAL : 1; + unsigned int RESERVED : 2; + unsigned int THRESHOLD : 10; + unsigned int SX_AVAIL_SIGN : 1; + unsigned int SX_AVAIL_WEIGHT : 3; + unsigned int PC_AVAIL_SIGN : 1; + unsigned int PC_AVAIL_WEIGHT : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_VS_WATCHDOG_TIMER { + struct { +#if defined(qLittleEndian) + unsigned int ENABLE : 1; + unsigned int TIMEOUT_COUNT : 31; +#else /* !defined(qLittleEndian) */ + unsigned int TIMEOUT_COUNT : 31; + unsigned int ENABLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PS_WATCHDOG_TIMER { + struct { +#if defined(qLittleEndian) + unsigned int ENABLE : 1; + unsigned int TIMEOUT_COUNT : 31; +#else /* !defined(qLittleEndian) */ + unsigned int TIMEOUT_COUNT : 31; + unsigned int ENABLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INT_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int PS_WATCHDOG_MASK : 1; + unsigned int VS_WATCHDOG_MASK : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int VS_WATCHDOG_MASK : 1; + unsigned int PS_WATCHDOG_MASK : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INT_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int PS_WATCHDOG_TIMEOUT : 1; + unsigned int VS_WATCHDOG_TIMEOUT : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int VS_WATCHDOG_TIMEOUT : 1; + unsigned int PS_WATCHDOG_TIMEOUT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INT_ACK { + struct { +#if defined(qLittleEndian) + unsigned int PS_WATCHDOG_ACK : 1; + unsigned int VS_WATCHDOG_ACK : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int VS_WATCHDOG_ACK : 1; + unsigned int PS_WATCHDOG_ACK : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_INPUT_FSM { + struct { +#if defined(qLittleEndian) + unsigned int VC_VSR_LD : 3; + unsigned int RESERVED : 1; + unsigned int VC_GPR_LD : 4; + unsigned int PC_PISM : 3; + unsigned int RESERVED1 : 1; + unsigned int PC_AS : 3; + unsigned int PC_INTERP_CNT : 5; + unsigned int PC_GPR_SIZE : 8; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int PC_GPR_SIZE : 8; + unsigned int PC_INTERP_CNT : 5; + unsigned int PC_AS : 3; + unsigned int RESERVED1 : 1; + unsigned int PC_PISM : 3; + unsigned int VC_GPR_LD : 4; + unsigned int RESERVED : 1; + unsigned int VC_VSR_LD : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_CONST_MGR_FSM { + struct { +#if defined(qLittleEndian) + unsigned int TEX_CONST_EVENT_STATE : 5; + unsigned int RESERVED1 : 3; + unsigned int ALU_CONST_EVENT_STATE : 5; + unsigned int RESERVED2 : 3; + unsigned int ALU_CONST_CNTX_VALID : 2; + unsigned int TEX_CONST_CNTX_VALID : 2; + unsigned int CNTX0_VTX_EVENT_DONE : 1; + unsigned int CNTX0_PIX_EVENT_DONE : 1; + unsigned int CNTX1_VTX_EVENT_DONE : 1; + unsigned int CNTX1_PIX_EVENT_DONE : 1; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int CNTX1_PIX_EVENT_DONE : 1; + unsigned int CNTX1_VTX_EVENT_DONE : 1; + unsigned int CNTX0_PIX_EVENT_DONE : 1; + unsigned int CNTX0_VTX_EVENT_DONE : 1; + unsigned int TEX_CONST_CNTX_VALID : 2; + unsigned int ALU_CONST_CNTX_VALID : 2; + unsigned int RESERVED2 : 3; + unsigned int ALU_CONST_EVENT_STATE : 5; + unsigned int RESERVED1 : 3; + unsigned int TEX_CONST_EVENT_STATE : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_TP_FSM { + struct { +#if defined(qLittleEndian) + unsigned int EX_TP : 3; + unsigned int RESERVED0 : 1; + unsigned int CF_TP : 4; + unsigned int IF_TP : 3; + unsigned int RESERVED1 : 1; + unsigned int TIS_TP : 2; + unsigned int RESERVED2 : 2; + unsigned int GS_TP : 2; + unsigned int RESERVED3 : 2; + unsigned int FCR_TP : 2; + unsigned int RESERVED4 : 2; + unsigned int FCS_TP : 2; + unsigned int RESERVED5 : 2; + unsigned int ARB_TR_TP : 3; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int ARB_TR_TP : 3; + unsigned int RESERVED5 : 2; + unsigned int FCS_TP : 2; + unsigned int RESERVED4 : 2; + unsigned int FCR_TP : 2; + unsigned int RESERVED3 : 2; + unsigned int GS_TP : 2; + unsigned int RESERVED2 : 2; + unsigned int TIS_TP : 2; + unsigned int RESERVED1 : 1; + unsigned int IF_TP : 3; + unsigned int CF_TP : 4; + unsigned int RESERVED0 : 1; + unsigned int EX_TP : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_FSM_ALU_0 { + struct { +#if defined(qLittleEndian) + unsigned int EX_ALU_0 : 3; + unsigned int RESERVED0 : 1; + unsigned int CF_ALU_0 : 4; + unsigned int IF_ALU_0 : 3; + unsigned int RESERVED1 : 1; + unsigned int DU1_ALU_0 : 3; + unsigned int RESERVED2 : 1; + unsigned int DU0_ALU_0 : 3; + unsigned int RESERVED3 : 1; + unsigned int AIS_ALU_0 : 3; + unsigned int RESERVED4 : 1; + unsigned int ACS_ALU_0 : 3; + unsigned int RESERVED5 : 1; + unsigned int ARB_TR_ALU : 3; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int ARB_TR_ALU : 3; + unsigned int RESERVED5 : 1; + unsigned int ACS_ALU_0 : 3; + unsigned int RESERVED4 : 1; + unsigned int AIS_ALU_0 : 3; + unsigned int RESERVED3 : 1; + unsigned int DU0_ALU_0 : 3; + unsigned int RESERVED2 : 1; + unsigned int DU1_ALU_0 : 3; + unsigned int RESERVED1 : 1; + unsigned int IF_ALU_0 : 3; + unsigned int CF_ALU_0 : 4; + unsigned int RESERVED0 : 1; + unsigned int EX_ALU_0 : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_FSM_ALU_1 { + struct { +#if defined(qLittleEndian) + unsigned int EX_ALU_0 : 3; + unsigned int RESERVED0 : 1; + unsigned int CF_ALU_0 : 4; + unsigned int IF_ALU_0 : 3; + unsigned int RESERVED1 : 1; + unsigned int DU1_ALU_0 : 3; + unsigned int RESERVED2 : 1; + unsigned int DU0_ALU_0 : 3; + unsigned int RESERVED3 : 1; + unsigned int AIS_ALU_0 : 3; + unsigned int RESERVED4 : 1; + unsigned int ACS_ALU_0 : 3; + unsigned int RESERVED5 : 1; + unsigned int ARB_TR_ALU : 3; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int ARB_TR_ALU : 3; + unsigned int RESERVED5 : 1; + unsigned int ACS_ALU_0 : 3; + unsigned int RESERVED4 : 1; + unsigned int AIS_ALU_0 : 3; + unsigned int RESERVED3 : 1; + unsigned int DU0_ALU_0 : 3; + unsigned int RESERVED2 : 1; + unsigned int DU1_ALU_0 : 3; + unsigned int RESERVED1 : 1; + unsigned int IF_ALU_0 : 3; + unsigned int CF_ALU_0 : 4; + unsigned int RESERVED0 : 1; + unsigned int EX_ALU_0 : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_EXP_ALLOC { + struct { +#if defined(qLittleEndian) + unsigned int POS_BUF_AVAIL : 4; + unsigned int COLOR_BUF_AVAIL : 8; + unsigned int EA_BUF_AVAIL : 3; + unsigned int RESERVED : 1; + unsigned int ALLOC_TBL_BUF_AVAIL : 6; + unsigned int : 10; +#else /* !defined(qLittleEndian) */ + unsigned int : 10; + unsigned int ALLOC_TBL_BUF_AVAIL : 6; + unsigned int RESERVED : 1; + unsigned int EA_BUF_AVAIL : 3; + unsigned int COLOR_BUF_AVAIL : 8; + unsigned int POS_BUF_AVAIL : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PTR_BUFF { + struct { +#if defined(qLittleEndian) + unsigned int END_OF_BUFFER : 1; + unsigned int DEALLOC_CNT : 4; + unsigned int QUAL_NEW_VECTOR : 1; + unsigned int EVENT_CONTEXT_ID : 3; + unsigned int SC_EVENT_ID : 5; + unsigned int QUAL_EVENT : 1; + unsigned int PRIM_TYPE_POLYGON : 1; + unsigned int EF_EMPTY : 1; + unsigned int VTX_SYNC_CNT : 11; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int VTX_SYNC_CNT : 11; + unsigned int EF_EMPTY : 1; + unsigned int PRIM_TYPE_POLYGON : 1; + unsigned int QUAL_EVENT : 1; + unsigned int SC_EVENT_ID : 5; + unsigned int EVENT_CONTEXT_ID : 3; + unsigned int QUAL_NEW_VECTOR : 1; + unsigned int DEALLOC_CNT : 4; + unsigned int END_OF_BUFFER : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_GPR_VTX { + struct { +#if defined(qLittleEndian) + unsigned int VTX_TAIL_PTR : 7; + unsigned int RESERVED : 1; + unsigned int VTX_HEAD_PTR : 7; + unsigned int RESERVED1 : 1; + unsigned int VTX_MAX : 7; + unsigned int RESERVED2 : 1; + unsigned int VTX_FREE : 7; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int VTX_FREE : 7; + unsigned int RESERVED2 : 1; + unsigned int VTX_MAX : 7; + unsigned int RESERVED1 : 1; + unsigned int VTX_HEAD_PTR : 7; + unsigned int RESERVED : 1; + unsigned int VTX_TAIL_PTR : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_GPR_PIX { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TAIL_PTR : 7; + unsigned int RESERVED : 1; + unsigned int PIX_HEAD_PTR : 7; + unsigned int RESERVED1 : 1; + unsigned int PIX_MAX : 7; + unsigned int RESERVED2 : 1; + unsigned int PIX_FREE : 7; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int PIX_FREE : 7; + unsigned int RESERVED2 : 1; + unsigned int PIX_MAX : 7; + unsigned int RESERVED1 : 1; + unsigned int PIX_HEAD_PTR : 7; + unsigned int RESERVED : 1; + unsigned int PIX_TAIL_PTR : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_TB_STATUS_SEL { + struct { +#if defined(qLittleEndian) + unsigned int VTX_TB_STATUS_REG_SEL : 4; + unsigned int VTX_TB_STATE_MEM_DW_SEL : 3; + unsigned int VTX_TB_STATE_MEM_RD_ADDR : 4; + unsigned int VTX_TB_STATE_MEM_RD_EN : 1; + unsigned int PIX_TB_STATE_MEM_RD_EN : 1; + unsigned int : 1; + unsigned int DEBUG_BUS_TRIGGER_SEL : 2; + unsigned int PIX_TB_STATUS_REG_SEL : 4; + unsigned int PIX_TB_STATE_MEM_DW_SEL : 3; + unsigned int PIX_TB_STATE_MEM_RD_ADDR : 6; + unsigned int VC_THREAD_BUF_DLY : 2; + unsigned int DISABLE_STRICT_CTX_SYNC : 1; +#else /* !defined(qLittleEndian) */ + unsigned int DISABLE_STRICT_CTX_SYNC : 1; + unsigned int VC_THREAD_BUF_DLY : 2; + unsigned int PIX_TB_STATE_MEM_RD_ADDR : 6; + unsigned int PIX_TB_STATE_MEM_DW_SEL : 3; + unsigned int PIX_TB_STATUS_REG_SEL : 4; + unsigned int DEBUG_BUS_TRIGGER_SEL : 2; + unsigned int : 1; + unsigned int PIX_TB_STATE_MEM_RD_EN : 1; + unsigned int VTX_TB_STATE_MEM_RD_EN : 1; + unsigned int VTX_TB_STATE_MEM_RD_ADDR : 4; + unsigned int VTX_TB_STATE_MEM_DW_SEL : 3; + unsigned int VTX_TB_STATUS_REG_SEL : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_VTX_TB_0 { + struct { +#if defined(qLittleEndian) + unsigned int VTX_HEAD_PTR_Q : 4; + unsigned int TAIL_PTR_Q : 4; + unsigned int FULL_CNT_Q : 4; + unsigned int NXT_POS_ALLOC_CNT : 4; + unsigned int NXT_PC_ALLOC_CNT : 4; + unsigned int SX_EVENT_FULL : 1; + unsigned int BUSY_Q : 1; + unsigned int : 10; +#else /* !defined(qLittleEndian) */ + unsigned int : 10; + unsigned int BUSY_Q : 1; + unsigned int SX_EVENT_FULL : 1; + unsigned int NXT_PC_ALLOC_CNT : 4; + unsigned int NXT_POS_ALLOC_CNT : 4; + unsigned int FULL_CNT_Q : 4; + unsigned int TAIL_PTR_Q : 4; + unsigned int VTX_HEAD_PTR_Q : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_VTX_TB_1 { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_PTR : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int VS_DONE_PTR : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_VTX_TB_STATUS_REG { + struct { +#if defined(qLittleEndian) + unsigned int VS_STATUS_REG : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_STATUS_REG : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_VTX_TB_STATE_MEM { + struct { +#if defined(qLittleEndian) + unsigned int VS_STATE_MEM : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_STATE_MEM : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_0 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_HEAD_PTR : 6; + unsigned int TAIL_PTR : 6; + unsigned int FULL_CNT : 7; + unsigned int NXT_PIX_ALLOC_CNT : 6; + unsigned int NXT_PIX_EXP_CNT : 6; + unsigned int BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int BUSY : 1; + unsigned int NXT_PIX_EXP_CNT : 6; + unsigned int NXT_PIX_ALLOC_CNT : 6; + unsigned int FULL_CNT : 7; + unsigned int TAIL_PTR : 6; + unsigned int PIX_HEAD_PTR : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATUS_REG_0 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATUS_REG_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATUS_REG_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATUS_REG_1 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATUS_REG_1 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATUS_REG_1 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATUS_REG_2 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATUS_REG_2 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATUS_REG_2 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATUS_REG_3 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATUS_REG_3 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATUS_REG_3 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATE_MEM { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATE_MEM : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATE_MEM : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER2_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER3_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER2_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER2_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER3_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER3_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SX_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SX_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SX_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_ALU_0 { + struct { +#if defined(qLittleEndian) + unsigned int VECTOR_RESULT : 6; + unsigned int VECTOR_DST_REL : 1; + unsigned int LOW_PRECISION_16B_FP : 1; + unsigned int SCALAR_RESULT : 6; + unsigned int SCALAR_DST_REL : 1; + unsigned int EXPORT_DATA : 1; + unsigned int VECTOR_WRT_MSK : 4; + unsigned int SCALAR_WRT_MSK : 4; + unsigned int VECTOR_CLAMP : 1; + unsigned int SCALAR_CLAMP : 1; + unsigned int SCALAR_OPCODE : 6; +#else /* !defined(qLittleEndian) */ + unsigned int SCALAR_OPCODE : 6; + unsigned int SCALAR_CLAMP : 1; + unsigned int VECTOR_CLAMP : 1; + unsigned int SCALAR_WRT_MSK : 4; + unsigned int VECTOR_WRT_MSK : 4; + unsigned int EXPORT_DATA : 1; + unsigned int SCALAR_DST_REL : 1; + unsigned int SCALAR_RESULT : 6; + unsigned int LOW_PRECISION_16B_FP : 1; + unsigned int VECTOR_DST_REL : 1; + unsigned int VECTOR_RESULT : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_ALU_1 { + struct { +#if defined(qLittleEndian) + unsigned int SRC_C_SWIZZLE_R : 2; + unsigned int SRC_C_SWIZZLE_G : 2; + unsigned int SRC_C_SWIZZLE_B : 2; + unsigned int SRC_C_SWIZZLE_A : 2; + unsigned int SRC_B_SWIZZLE_R : 2; + unsigned int SRC_B_SWIZZLE_G : 2; + unsigned int SRC_B_SWIZZLE_B : 2; + unsigned int SRC_B_SWIZZLE_A : 2; + unsigned int SRC_A_SWIZZLE_R : 2; + unsigned int SRC_A_SWIZZLE_G : 2; + unsigned int SRC_A_SWIZZLE_B : 2; + unsigned int SRC_A_SWIZZLE_A : 2; + unsigned int SRC_C_ARG_MOD : 1; + unsigned int SRC_B_ARG_MOD : 1; + unsigned int SRC_A_ARG_MOD : 1; + unsigned int PRED_SELECT : 2; + unsigned int RELATIVE_ADDR : 1; + unsigned int CONST_1_REL_ABS : 1; + unsigned int CONST_0_REL_ABS : 1; +#else /* !defined(qLittleEndian) */ + unsigned int CONST_0_REL_ABS : 1; + unsigned int CONST_1_REL_ABS : 1; + unsigned int RELATIVE_ADDR : 1; + unsigned int PRED_SELECT : 2; + unsigned int SRC_A_ARG_MOD : 1; + unsigned int SRC_B_ARG_MOD : 1; + unsigned int SRC_C_ARG_MOD : 1; + unsigned int SRC_A_SWIZZLE_A : 2; + unsigned int SRC_A_SWIZZLE_B : 2; + unsigned int SRC_A_SWIZZLE_G : 2; + unsigned int SRC_A_SWIZZLE_R : 2; + unsigned int SRC_B_SWIZZLE_A : 2; + unsigned int SRC_B_SWIZZLE_B : 2; + unsigned int SRC_B_SWIZZLE_G : 2; + unsigned int SRC_B_SWIZZLE_R : 2; + unsigned int SRC_C_SWIZZLE_A : 2; + unsigned int SRC_C_SWIZZLE_B : 2; + unsigned int SRC_C_SWIZZLE_G : 2; + unsigned int SRC_C_SWIZZLE_R : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_ALU_2 { + struct { +#if defined(qLittleEndian) + unsigned int SRC_C_REG_PTR : 6; + unsigned int REG_SELECT_C : 1; + unsigned int REG_ABS_MOD_C : 1; + unsigned int SRC_B_REG_PTR : 6; + unsigned int REG_SELECT_B : 1; + unsigned int REG_ABS_MOD_B : 1; + unsigned int SRC_A_REG_PTR : 6; + unsigned int REG_SELECT_A : 1; + unsigned int REG_ABS_MOD_A : 1; + unsigned int VECTOR_OPCODE : 5; + unsigned int SRC_C_SEL : 1; + unsigned int SRC_B_SEL : 1; + unsigned int SRC_A_SEL : 1; +#else /* !defined(qLittleEndian) */ + unsigned int SRC_A_SEL : 1; + unsigned int SRC_B_SEL : 1; + unsigned int SRC_C_SEL : 1; + unsigned int VECTOR_OPCODE : 5; + unsigned int REG_ABS_MOD_A : 1; + unsigned int REG_SELECT_A : 1; + unsigned int SRC_A_REG_PTR : 6; + unsigned int REG_ABS_MOD_B : 1; + unsigned int REG_SELECT_B : 1; + unsigned int SRC_B_REG_PTR : 6; + unsigned int REG_ABS_MOD_C : 1; + unsigned int REG_SELECT_C : 1; + unsigned int SRC_C_REG_PTR : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_EXEC_0 { + struct { +#if defined(qLittleEndian) + unsigned int ADDRESS : 9; + unsigned int RESERVED : 3; + unsigned int COUNT : 3; + unsigned int YIELD : 1; + unsigned int INST_TYPE_0 : 1; + unsigned int INST_SERIAL_0 : 1; + unsigned int INST_TYPE_1 : 1; + unsigned int INST_SERIAL_1 : 1; + unsigned int INST_TYPE_2 : 1; + unsigned int INST_SERIAL_2 : 1; + unsigned int INST_TYPE_3 : 1; + unsigned int INST_SERIAL_3 : 1; + unsigned int INST_TYPE_4 : 1; + unsigned int INST_SERIAL_4 : 1; + unsigned int INST_TYPE_5 : 1; + unsigned int INST_SERIAL_5 : 1; + unsigned int INST_VC_0 : 1; + unsigned int INST_VC_1 : 1; + unsigned int INST_VC_2 : 1; + unsigned int INST_VC_3 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int INST_VC_3 : 1; + unsigned int INST_VC_2 : 1; + unsigned int INST_VC_1 : 1; + unsigned int INST_VC_0 : 1; + unsigned int INST_SERIAL_5 : 1; + unsigned int INST_TYPE_5 : 1; + unsigned int INST_SERIAL_4 : 1; + unsigned int INST_TYPE_4 : 1; + unsigned int INST_SERIAL_3 : 1; + unsigned int INST_TYPE_3 : 1; + unsigned int INST_SERIAL_2 : 1; + unsigned int INST_TYPE_2 : 1; + unsigned int INST_SERIAL_1 : 1; + unsigned int INST_TYPE_1 : 1; + unsigned int INST_SERIAL_0 : 1; + unsigned int INST_TYPE_0 : 1; + unsigned int YIELD : 1; + unsigned int COUNT : 3; + unsigned int RESERVED : 3; + unsigned int ADDRESS : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_EXEC_1 { + struct { +#if defined(qLittleEndian) + unsigned int INST_VC_4 : 1; + unsigned int INST_VC_5 : 1; + unsigned int BOOL_ADDR : 8; + unsigned int CONDITION : 1; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; + unsigned int ADDRESS : 9; + unsigned int RESERVED : 3; + unsigned int COUNT : 3; + unsigned int YIELD : 1; +#else /* !defined(qLittleEndian) */ + unsigned int YIELD : 1; + unsigned int COUNT : 3; + unsigned int RESERVED : 3; + unsigned int ADDRESS : 9; + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int CONDITION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int INST_VC_5 : 1; + unsigned int INST_VC_4 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_EXEC_2 { + struct { +#if defined(qLittleEndian) + unsigned int INST_TYPE_0 : 1; + unsigned int INST_SERIAL_0 : 1; + unsigned int INST_TYPE_1 : 1; + unsigned int INST_SERIAL_1 : 1; + unsigned int INST_TYPE_2 : 1; + unsigned int INST_SERIAL_2 : 1; + unsigned int INST_TYPE_3 : 1; + unsigned int INST_SERIAL_3 : 1; + unsigned int INST_TYPE_4 : 1; + unsigned int INST_SERIAL_4 : 1; + unsigned int INST_TYPE_5 : 1; + unsigned int INST_SERIAL_5 : 1; + unsigned int INST_VC_0 : 1; + unsigned int INST_VC_1 : 1; + unsigned int INST_VC_2 : 1; + unsigned int INST_VC_3 : 1; + unsigned int INST_VC_4 : 1; + unsigned int INST_VC_5 : 1; + unsigned int BOOL_ADDR : 8; + unsigned int CONDITION : 1; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; +#else /* !defined(qLittleEndian) */ + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int CONDITION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int INST_VC_5 : 1; + unsigned int INST_VC_4 : 1; + unsigned int INST_VC_3 : 1; + unsigned int INST_VC_2 : 1; + unsigned int INST_VC_1 : 1; + unsigned int INST_VC_0 : 1; + unsigned int INST_SERIAL_5 : 1; + unsigned int INST_TYPE_5 : 1; + unsigned int INST_SERIAL_4 : 1; + unsigned int INST_TYPE_4 : 1; + unsigned int INST_SERIAL_3 : 1; + unsigned int INST_TYPE_3 : 1; + unsigned int INST_SERIAL_2 : 1; + unsigned int INST_TYPE_2 : 1; + unsigned int INST_SERIAL_1 : 1; + unsigned int INST_TYPE_1 : 1; + unsigned int INST_SERIAL_0 : 1; + unsigned int INST_TYPE_0 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_LOOP_0 { + struct { +#if defined(qLittleEndian) + unsigned int ADDRESS : 10; + unsigned int RESERVED_0 : 6; + unsigned int LOOP_ID : 5; + unsigned int RESERVED_1 : 11; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_1 : 11; + unsigned int LOOP_ID : 5; + unsigned int RESERVED_0 : 6; + unsigned int ADDRESS : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_LOOP_1 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED_0 : 11; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; + unsigned int ADDRESS : 10; + unsigned int RESERVED_1 : 6; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_1 : 6; + unsigned int ADDRESS : 10; + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int RESERVED_0 : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_LOOP_2 { + struct { +#if defined(qLittleEndian) + unsigned int LOOP_ID : 5; + unsigned int RESERVED : 22; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; +#else /* !defined(qLittleEndian) */ + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int RESERVED : 22; + unsigned int LOOP_ID : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_JMP_CALL_0 { + struct { +#if defined(qLittleEndian) + unsigned int ADDRESS : 10; + unsigned int RESERVED_0 : 3; + unsigned int FORCE_CALL : 1; + unsigned int PREDICATED_JMP : 1; + unsigned int RESERVED_1 : 17; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_1 : 17; + unsigned int PREDICATED_JMP : 1; + unsigned int FORCE_CALL : 1; + unsigned int RESERVED_0 : 3; + unsigned int ADDRESS : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_JMP_CALL_1 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED_0 : 1; + unsigned int DIRECTION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int CONDITION : 1; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; + unsigned int ADDRESS : 10; + unsigned int RESERVED_1 : 3; + unsigned int FORCE_CALL : 1; + unsigned int RESERVED_2 : 2; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_2 : 2; + unsigned int FORCE_CALL : 1; + unsigned int RESERVED_1 : 3; + unsigned int ADDRESS : 10; + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int CONDITION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int DIRECTION : 1; + unsigned int RESERVED_0 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_JMP_CALL_2 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED : 17; + unsigned int DIRECTION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int CONDITION : 1; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; +#else /* !defined(qLittleEndian) */ + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int CONDITION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int DIRECTION : 1; + unsigned int RESERVED : 17; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_ALLOC_0 { + struct { +#if defined(qLittleEndian) + unsigned int SIZE : 4; + unsigned int RESERVED : 28; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED : 28; + unsigned int SIZE : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_ALLOC_1 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED_0 : 8; + unsigned int NO_SERIAL : 1; + unsigned int BUFFER_SELECT : 2; + unsigned int ALLOC_MODE : 1; + unsigned int OPCODE : 4; + unsigned int SIZE : 4; + unsigned int RESERVED_1 : 12; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_1 : 12; + unsigned int SIZE : 4; + unsigned int OPCODE : 4; + unsigned int ALLOC_MODE : 1; + unsigned int BUFFER_SELECT : 2; + unsigned int NO_SERIAL : 1; + unsigned int RESERVED_0 : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_ALLOC_2 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED : 24; + unsigned int NO_SERIAL : 1; + unsigned int BUFFER_SELECT : 2; + unsigned int ALLOC_MODE : 1; + unsigned int OPCODE : 4; +#else /* !defined(qLittleEndian) */ + unsigned int OPCODE : 4; + unsigned int ALLOC_MODE : 1; + unsigned int BUFFER_SELECT : 2; + unsigned int NO_SERIAL : 1; + unsigned int RESERVED : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_TFETCH_0 { + struct { +#if defined(qLittleEndian) + unsigned int OPCODE : 5; + unsigned int SRC_GPR : 6; + unsigned int SRC_GPR_AM : 1; + unsigned int DST_GPR : 6; + unsigned int DST_GPR_AM : 1; + unsigned int FETCH_VALID_ONLY : 1; + unsigned int CONST_INDEX : 5; + unsigned int TX_COORD_DENORM : 1; + unsigned int SRC_SEL_X : 2; + unsigned int SRC_SEL_Y : 2; + unsigned int SRC_SEL_Z : 2; +#else /* !defined(qLittleEndian) */ + unsigned int SRC_SEL_Z : 2; + unsigned int SRC_SEL_Y : 2; + unsigned int SRC_SEL_X : 2; + unsigned int TX_COORD_DENORM : 1; + unsigned int CONST_INDEX : 5; + unsigned int FETCH_VALID_ONLY : 1; + unsigned int DST_GPR_AM : 1; + unsigned int DST_GPR : 6; + unsigned int SRC_GPR_AM : 1; + unsigned int SRC_GPR : 6; + unsigned int OPCODE : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_TFETCH_1 { + struct { +#if defined(qLittleEndian) + unsigned int DST_SEL_X : 3; + unsigned int DST_SEL_Y : 3; + unsigned int DST_SEL_Z : 3; + unsigned int DST_SEL_W : 3; + unsigned int MAG_FILTER : 2; + unsigned int MIN_FILTER : 2; + unsigned int MIP_FILTER : 2; + unsigned int ANISO_FILTER : 3; + unsigned int ARBITRARY_FILTER : 3; + unsigned int VOL_MAG_FILTER : 2; + unsigned int VOL_MIN_FILTER : 2; + unsigned int USE_COMP_LOD : 1; + unsigned int USE_REG_LOD : 2; + unsigned int PRED_SELECT : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PRED_SELECT : 1; + unsigned int USE_REG_LOD : 2; + unsigned int USE_COMP_LOD : 1; + unsigned int VOL_MIN_FILTER : 2; + unsigned int VOL_MAG_FILTER : 2; + unsigned int ARBITRARY_FILTER : 3; + unsigned int ANISO_FILTER : 3; + unsigned int MIP_FILTER : 2; + unsigned int MIN_FILTER : 2; + unsigned int MAG_FILTER : 2; + unsigned int DST_SEL_W : 3; + unsigned int DST_SEL_Z : 3; + unsigned int DST_SEL_Y : 3; + unsigned int DST_SEL_X : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_TFETCH_2 { + struct { +#if defined(qLittleEndian) + unsigned int USE_REG_GRADIENTS : 1; + unsigned int SAMPLE_LOCATION : 1; + unsigned int LOD_BIAS : 7; + unsigned int UNUSED : 7; + unsigned int OFFSET_X : 5; + unsigned int OFFSET_Y : 5; + unsigned int OFFSET_Z : 5; + unsigned int PRED_CONDITION : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PRED_CONDITION : 1; + unsigned int OFFSET_Z : 5; + unsigned int OFFSET_Y : 5; + unsigned int OFFSET_X : 5; + unsigned int UNUSED : 7; + unsigned int LOD_BIAS : 7; + unsigned int SAMPLE_LOCATION : 1; + unsigned int USE_REG_GRADIENTS : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_VFETCH_0 { + struct { +#if defined(qLittleEndian) + unsigned int OPCODE : 5; + unsigned int SRC_GPR : 6; + unsigned int SRC_GPR_AM : 1; + unsigned int DST_GPR : 6; + unsigned int DST_GPR_AM : 1; + unsigned int MUST_BE_ONE : 1; + unsigned int CONST_INDEX : 5; + unsigned int CONST_INDEX_SEL : 2; + unsigned int : 3; + unsigned int SRC_SEL : 2; +#else /* !defined(qLittleEndian) */ + unsigned int SRC_SEL : 2; + unsigned int : 3; + unsigned int CONST_INDEX_SEL : 2; + unsigned int CONST_INDEX : 5; + unsigned int MUST_BE_ONE : 1; + unsigned int DST_GPR_AM : 1; + unsigned int DST_GPR : 6; + unsigned int SRC_GPR_AM : 1; + unsigned int SRC_GPR : 6; + unsigned int OPCODE : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_VFETCH_1 { + struct { +#if defined(qLittleEndian) + unsigned int DST_SEL_X : 3; + unsigned int DST_SEL_Y : 3; + unsigned int DST_SEL_Z : 3; + unsigned int DST_SEL_W : 3; + unsigned int FORMAT_COMP_ALL : 1; + unsigned int NUM_FORMAT_ALL : 1; + unsigned int SIGNED_RF_MODE_ALL : 1; + unsigned int : 1; + unsigned int DATA_FORMAT : 6; + unsigned int : 1; + unsigned int EXP_ADJUST_ALL : 7; + unsigned int : 1; + unsigned int PRED_SELECT : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PRED_SELECT : 1; + unsigned int : 1; + unsigned int EXP_ADJUST_ALL : 7; + unsigned int : 1; + unsigned int DATA_FORMAT : 6; + unsigned int : 1; + unsigned int SIGNED_RF_MODE_ALL : 1; + unsigned int NUM_FORMAT_ALL : 1; + unsigned int FORMAT_COMP_ALL : 1; + unsigned int DST_SEL_W : 3; + unsigned int DST_SEL_Z : 3; + unsigned int DST_SEL_Y : 3; + unsigned int DST_SEL_X : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_VFETCH_2 { + struct { +#if defined(qLittleEndian) + unsigned int STRIDE : 8; + unsigned int : 8; + unsigned int OFFSET : 8; + unsigned int : 7; + unsigned int PRED_CONDITION : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PRED_CONDITION : 1; + unsigned int : 7; + unsigned int OFFSET : 8; + unsigned int : 8; + unsigned int STRIDE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_0 { + struct { +#if defined(qLittleEndian) + unsigned int RED : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RED : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_1 { + struct { +#if defined(qLittleEndian) + unsigned int GREEN : 32; +#else /* !defined(qLittleEndian) */ + unsigned int GREEN : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_2 { + struct { +#if defined(qLittleEndian) + unsigned int BLUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BLUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_3 { + struct { +#if defined(qLittleEndian) + unsigned int ALPHA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ALPHA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_0 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_1 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_2 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_3 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_4 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_5 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_VFETCH_0 { + struct { +#if defined(qLittleEndian) + unsigned int TYPE : 1; + unsigned int STATE : 1; + unsigned int BASE_ADDRESS : 30; +#else /* !defined(qLittleEndian) */ + unsigned int BASE_ADDRESS : 30; + unsigned int STATE : 1; + unsigned int TYPE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_VFETCH_1 { + struct { +#if defined(qLittleEndian) + unsigned int ENDIAN_SWAP : 2; + unsigned int LIMIT_ADDRESS : 30; +#else /* !defined(qLittleEndian) */ + unsigned int LIMIT_ADDRESS : 30; + unsigned int ENDIAN_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_T2 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_T3 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_BOOLEANS { + struct { +#if defined(qLittleEndian) + unsigned int CF_BOOLEANS_0 : 8; + unsigned int CF_BOOLEANS_1 : 8; + unsigned int CF_BOOLEANS_2 : 8; + unsigned int CF_BOOLEANS_3 : 8; +#else /* !defined(qLittleEndian) */ + unsigned int CF_BOOLEANS_3 : 8; + unsigned int CF_BOOLEANS_2 : 8; + unsigned int CF_BOOLEANS_1 : 8; + unsigned int CF_BOOLEANS_0 : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_LOOP { + struct { +#if defined(qLittleEndian) + unsigned int CF_LOOP_COUNT : 8; + unsigned int CF_LOOP_START : 8; + unsigned int CF_LOOP_STEP : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int CF_LOOP_STEP : 8; + unsigned int CF_LOOP_START : 8; + unsigned int CF_LOOP_COUNT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_RT_0 { + struct { +#if defined(qLittleEndian) + unsigned int RED : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RED : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_RT_1 { + struct { +#if defined(qLittleEndian) + unsigned int GREEN : 32; +#else /* !defined(qLittleEndian) */ + unsigned int GREEN : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_RT_2 { + struct { +#if defined(qLittleEndian) + unsigned int BLUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BLUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_RT_3 { + struct { +#if defined(qLittleEndian) + unsigned int ALPHA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ALPHA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_0 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_1 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_2 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_3 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_4 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_5 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_RT_BOOLEANS { + struct { +#if defined(qLittleEndian) + unsigned int CF_BOOLEANS_0 : 8; + unsigned int CF_BOOLEANS_1 : 8; + unsigned int CF_BOOLEANS_2 : 8; + unsigned int CF_BOOLEANS_3 : 8; +#else /* !defined(qLittleEndian) */ + unsigned int CF_BOOLEANS_3 : 8; + unsigned int CF_BOOLEANS_2 : 8; + unsigned int CF_BOOLEANS_1 : 8; + unsigned int CF_BOOLEANS_0 : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_RT_LOOP { + struct { +#if defined(qLittleEndian) + unsigned int CF_LOOP_COUNT : 8; + unsigned int CF_LOOP_START : 8; + unsigned int CF_LOOP_STEP : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int CF_LOOP_STEP : 8; + unsigned int CF_LOOP_START : 8; + unsigned int CF_LOOP_COUNT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_VS_PROGRAM { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 12; + unsigned int SIZE : 12; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int SIZE : 12; + unsigned int BASE : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PS_PROGRAM { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 12; + unsigned int SIZE : 12; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int SIZE : 12; + unsigned int BASE : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_PROGRAM_SIZE { + struct { +#if defined(qLittleEndian) + unsigned int VS_CF_SIZE : 11; + unsigned int : 1; + unsigned int PS_CF_SIZE : 11; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int PS_CF_SIZE : 11; + unsigned int : 1; + unsigned int VS_CF_SIZE : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INTERPOLATOR_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int PARAM_SHADE : 16; + unsigned int SAMPLING_PATTERN : 16; +#else /* !defined(qLittleEndian) */ + unsigned int SAMPLING_PATTERN : 16; + unsigned int PARAM_SHADE : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PROGRAM_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int VS_NUM_REG : 6; + unsigned int : 2; + unsigned int PS_NUM_REG : 6; + unsigned int : 2; + unsigned int VS_RESOURCE : 1; + unsigned int PS_RESOURCE : 1; + unsigned int PARAM_GEN : 1; + unsigned int GEN_INDEX_PIX : 1; + unsigned int VS_EXPORT_COUNT : 4; + unsigned int VS_EXPORT_MODE : 3; + unsigned int PS_EXPORT_MODE : 4; + unsigned int GEN_INDEX_VTX : 1; +#else /* !defined(qLittleEndian) */ + unsigned int GEN_INDEX_VTX : 1; + unsigned int PS_EXPORT_MODE : 4; + unsigned int VS_EXPORT_MODE : 3; + unsigned int VS_EXPORT_COUNT : 4; + unsigned int GEN_INDEX_PIX : 1; + unsigned int PARAM_GEN : 1; + unsigned int PS_RESOURCE : 1; + unsigned int VS_RESOURCE : 1; + unsigned int : 2; + unsigned int PS_NUM_REG : 6; + unsigned int : 2; + unsigned int VS_NUM_REG : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_WRAPPING_0 { + struct { +#if defined(qLittleEndian) + unsigned int PARAM_WRAP_0 : 4; + unsigned int PARAM_WRAP_1 : 4; + unsigned int PARAM_WRAP_2 : 4; + unsigned int PARAM_WRAP_3 : 4; + unsigned int PARAM_WRAP_4 : 4; + unsigned int PARAM_WRAP_5 : 4; + unsigned int PARAM_WRAP_6 : 4; + unsigned int PARAM_WRAP_7 : 4; +#else /* !defined(qLittleEndian) */ + unsigned int PARAM_WRAP_7 : 4; + unsigned int PARAM_WRAP_6 : 4; + unsigned int PARAM_WRAP_5 : 4; + unsigned int PARAM_WRAP_4 : 4; + unsigned int PARAM_WRAP_3 : 4; + unsigned int PARAM_WRAP_2 : 4; + unsigned int PARAM_WRAP_1 : 4; + unsigned int PARAM_WRAP_0 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_WRAPPING_1 { + struct { +#if defined(qLittleEndian) + unsigned int PARAM_WRAP_8 : 4; + unsigned int PARAM_WRAP_9 : 4; + unsigned int PARAM_WRAP_10 : 4; + unsigned int PARAM_WRAP_11 : 4; + unsigned int PARAM_WRAP_12 : 4; + unsigned int PARAM_WRAP_13 : 4; + unsigned int PARAM_WRAP_14 : 4; + unsigned int PARAM_WRAP_15 : 4; +#else /* !defined(qLittleEndian) */ + unsigned int PARAM_WRAP_15 : 4; + unsigned int PARAM_WRAP_14 : 4; + unsigned int PARAM_WRAP_13 : 4; + unsigned int PARAM_WRAP_12 : 4; + unsigned int PARAM_WRAP_11 : 4; + unsigned int PARAM_WRAP_10 : 4; + unsigned int PARAM_WRAP_9 : 4; + unsigned int PARAM_WRAP_8 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_VS_CONST { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 9; + unsigned int : 3; + unsigned int SIZE : 9; + unsigned int : 11; +#else /* !defined(qLittleEndian) */ + unsigned int : 11; + unsigned int SIZE : 9; + unsigned int : 3; + unsigned int BASE : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PS_CONST { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 9; + unsigned int : 3; + unsigned int SIZE : 9; + unsigned int : 11; +#else /* !defined(qLittleEndian) */ + unsigned int : 11; + unsigned int SIZE : 9; + unsigned int : 3; + unsigned int BASE : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONTEXT_MISC { + struct { +#if defined(qLittleEndian) + unsigned int INST_PRED_OPTIMIZE : 1; + unsigned int SC_OUTPUT_SCREEN_XY : 1; + unsigned int SC_SAMPLE_CNTL : 2; + unsigned int : 4; + unsigned int PARAM_GEN_POS : 8; + unsigned int PERFCOUNTER_REF : 1; + unsigned int YEILD_OPTIMIZE : 1; + unsigned int TX_CACHE_SEL : 1; + unsigned int : 13; +#else /* !defined(qLittleEndian) */ + unsigned int : 13; + unsigned int TX_CACHE_SEL : 1; + unsigned int YEILD_OPTIMIZE : 1; + unsigned int PERFCOUNTER_REF : 1; + unsigned int PARAM_GEN_POS : 8; + unsigned int : 4; + unsigned int SC_SAMPLE_CNTL : 2; + unsigned int SC_OUTPUT_SCREEN_XY : 1; + unsigned int INST_PRED_OPTIMIZE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_RD_BASE { + struct { +#if defined(qLittleEndian) + unsigned int RD_BASE : 3; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int RD_BASE : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_MISC_0 { + struct { +#if defined(qLittleEndian) + unsigned int DB_PROB_ON : 1; + unsigned int : 3; + unsigned int DB_PROB_BREAK : 1; + unsigned int : 3; + unsigned int DB_PROB_ADDR : 11; + unsigned int : 5; + unsigned int DB_PROB_COUNT : 8; +#else /* !defined(qLittleEndian) */ + unsigned int DB_PROB_COUNT : 8; + unsigned int : 5; + unsigned int DB_PROB_ADDR : 11; + unsigned int : 3; + unsigned int DB_PROB_BREAK : 1; + unsigned int : 3; + unsigned int DB_PROB_ON : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_MISC_1 { + struct { +#if defined(qLittleEndian) + unsigned int DB_ON_PIX : 1; + unsigned int DB_ON_VTX : 1; + unsigned int : 6; + unsigned int DB_INST_COUNT : 8; + unsigned int DB_BREAK_ADDR : 11; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int DB_BREAK_ADDR : 11; + unsigned int DB_INST_COUNT : 8; + unsigned int : 6; + unsigned int DB_ON_VTX : 1; + unsigned int DB_ON_PIX : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_ARBITER_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int SAME_PAGE_LIMIT : 6; + unsigned int SAME_PAGE_GRANULARITY : 1; + unsigned int L1_ARB_ENABLE : 1; + unsigned int L1_ARB_HOLD_ENABLE : 1; + unsigned int L2_ARB_CONTROL : 1; + unsigned int PAGE_SIZE : 3; + unsigned int TC_REORDER_ENABLE : 1; + unsigned int TC_ARB_HOLD_ENABLE : 1; + unsigned int IN_FLIGHT_LIMIT_ENABLE : 1; + unsigned int IN_FLIGHT_LIMIT : 6; + unsigned int CP_CLNT_ENABLE : 1; + unsigned int VGT_CLNT_ENABLE : 1; + unsigned int TC_CLNT_ENABLE : 1; + unsigned int RB_CLNT_ENABLE : 1; + unsigned int PA_CLNT_ENABLE : 1; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int PA_CLNT_ENABLE : 1; + unsigned int RB_CLNT_ENABLE : 1; + unsigned int TC_CLNT_ENABLE : 1; + unsigned int VGT_CLNT_ENABLE : 1; + unsigned int CP_CLNT_ENABLE : 1; + unsigned int IN_FLIGHT_LIMIT : 6; + unsigned int IN_FLIGHT_LIMIT_ENABLE : 1; + unsigned int TC_ARB_HOLD_ENABLE : 1; + unsigned int TC_REORDER_ENABLE : 1; + unsigned int PAGE_SIZE : 3; + unsigned int L2_ARB_CONTROL : 1; + unsigned int L1_ARB_HOLD_ENABLE : 1; + unsigned int L1_ARB_ENABLE : 1; + unsigned int SAME_PAGE_GRANULARITY : 1; + unsigned int SAME_PAGE_LIMIT : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_CLNT_AXI_ID_REUSE { + struct { +#if defined(qLittleEndian) + unsigned int CPw_ID : 3; + unsigned int RESERVED1 : 1; + unsigned int RBw_ID : 3; + unsigned int RESERVED2 : 1; + unsigned int MMUr_ID : 3; + unsigned int RESERVED3 : 1; + unsigned int PAw_ID : 3; + unsigned int : 17; +#else /* !defined(qLittleEndian) */ + unsigned int : 17; + unsigned int PAw_ID : 3; + unsigned int RESERVED3 : 1; + unsigned int MMUr_ID : 3; + unsigned int RESERVED2 : 1; + unsigned int RBw_ID : 3; + unsigned int RESERVED1 : 1; + unsigned int CPw_ID : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_INTERRUPT_MASK { + struct { +#if defined(qLittleEndian) + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int AXI_READ_ERROR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_INTERRUPT_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int AXI_READ_ERROR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_INTERRUPT_CLEAR { + struct { +#if defined(qLittleEndian) + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int AXI_READ_ERROR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_AXI_ERROR { + struct { +#if defined(qLittleEndian) + unsigned int AXI_READ_ID : 3; + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_WRITE_ID : 3; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int AXI_WRITE_ID : 3; + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_READ_ID : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER0_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int N_VALUE : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int N_VALUE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER1_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int N_VALUE : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int N_VALUE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_CTRL { + struct { +#if defined(qLittleEndian) + unsigned int INDEX : 6; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int INDEX : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_AXI_HALT_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int AXI_HALT : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int AXI_HALT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG00 { + struct { +#if defined(qLittleEndian) + unsigned int MH_BUSY : 1; + unsigned int TRANS_OUTSTANDING : 1; + unsigned int CP_REQUEST : 1; + unsigned int VGT_REQUEST : 1; + unsigned int TC_REQUEST : 1; + unsigned int TC_CAM_EMPTY : 1; + unsigned int TC_CAM_FULL : 1; + unsigned int TCD_EMPTY : 1; + unsigned int TCD_FULL : 1; + unsigned int RB_REQUEST : 1; + unsigned int PA_REQUEST : 1; + unsigned int MH_CLK_EN_STATE : 1; + unsigned int ARQ_EMPTY : 1; + unsigned int ARQ_FULL : 1; + unsigned int WDB_EMPTY : 1; + unsigned int WDB_FULL : 1; + unsigned int AXI_AVALID : 1; + unsigned int AXI_AREADY : 1; + unsigned int AXI_ARVALID : 1; + unsigned int AXI_ARREADY : 1; + unsigned int AXI_WVALID : 1; + unsigned int AXI_WREADY : 1; + unsigned int AXI_RVALID : 1; + unsigned int AXI_RREADY : 1; + unsigned int AXI_BVALID : 1; + unsigned int AXI_BREADY : 1; + unsigned int AXI_HALT_REQ : 1; + unsigned int AXI_HALT_ACK : 1; + unsigned int AXI_RDY_ENA : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int AXI_RDY_ENA : 1; + unsigned int AXI_HALT_ACK : 1; + unsigned int AXI_HALT_REQ : 1; + unsigned int AXI_BREADY : 1; + unsigned int AXI_BVALID : 1; + unsigned int AXI_RREADY : 1; + unsigned int AXI_RVALID : 1; + unsigned int AXI_WREADY : 1; + unsigned int AXI_WVALID : 1; + unsigned int AXI_ARREADY : 1; + unsigned int AXI_ARVALID : 1; + unsigned int AXI_AREADY : 1; + unsigned int AXI_AVALID : 1; + unsigned int WDB_FULL : 1; + unsigned int WDB_EMPTY : 1; + unsigned int ARQ_FULL : 1; + unsigned int ARQ_EMPTY : 1; + unsigned int MH_CLK_EN_STATE : 1; + unsigned int PA_REQUEST : 1; + unsigned int RB_REQUEST : 1; + unsigned int TCD_FULL : 1; + unsigned int TCD_EMPTY : 1; + unsigned int TC_CAM_FULL : 1; + unsigned int TC_CAM_EMPTY : 1; + unsigned int TC_REQUEST : 1; + unsigned int VGT_REQUEST : 1; + unsigned int CP_REQUEST : 1; + unsigned int TRANS_OUTSTANDING : 1; + unsigned int MH_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG01 { + struct { +#if defined(qLittleEndian) + unsigned int CP_SEND_q : 1; + unsigned int CP_RTR_q : 1; + unsigned int CP_WRITE_q : 1; + unsigned int CP_TAG_q : 3; + unsigned int CP_BLEN_q : 1; + unsigned int VGT_SEND_q : 1; + unsigned int VGT_RTR_q : 1; + unsigned int VGT_TAG_q : 1; + unsigned int TC_SEND_q : 1; + unsigned int TC_RTR_q : 1; + unsigned int TC_BLEN_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_written : 1; + unsigned int RB_SEND_q : 1; + unsigned int RB_RTR_q : 1; + unsigned int PA_SEND_q : 1; + unsigned int PA_RTR_q : 1; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int PA_RTR_q : 1; + unsigned int PA_SEND_q : 1; + unsigned int RB_RTR_q : 1; + unsigned int RB_SEND_q : 1; + unsigned int TC_MH_written : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_BLEN_q : 1; + unsigned int TC_RTR_q : 1; + unsigned int TC_SEND_q : 1; + unsigned int VGT_TAG_q : 1; + unsigned int VGT_RTR_q : 1; + unsigned int VGT_SEND_q : 1; + unsigned int CP_BLEN_q : 1; + unsigned int CP_TAG_q : 3; + unsigned int CP_WRITE_q : 1; + unsigned int CP_RTR_q : 1; + unsigned int CP_SEND_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG02 { + struct { +#if defined(qLittleEndian) + unsigned int MH_CP_grb_send : 1; + unsigned int MH_VGT_grb_send : 1; + unsigned int MH_TC_mcsend : 1; + unsigned int MH_CLNT_rlast : 1; + unsigned int MH_CLNT_tag : 3; + unsigned int RDC_RID : 3; + unsigned int RDC_RRESP : 2; + unsigned int MH_CP_writeclean : 1; + unsigned int MH_RB_writeclean : 1; + unsigned int MH_PA_writeclean : 1; + unsigned int BRC_BID : 3; + unsigned int BRC_BRESP : 2; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int BRC_BRESP : 2; + unsigned int BRC_BID : 3; + unsigned int MH_PA_writeclean : 1; + unsigned int MH_RB_writeclean : 1; + unsigned int MH_CP_writeclean : 1; + unsigned int RDC_RRESP : 2; + unsigned int RDC_RID : 3; + unsigned int MH_CLNT_tag : 3; + unsigned int MH_CLNT_rlast : 1; + unsigned int MH_TC_mcsend : 1; + unsigned int MH_VGT_grb_send : 1; + unsigned int MH_CP_grb_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG03 { + struct { +#if defined(qLittleEndian) + unsigned int MH_CLNT_data_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int MH_CLNT_data_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG04 { + struct { +#if defined(qLittleEndian) + unsigned int MH_CLNT_data_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int MH_CLNT_data_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG05 { + struct { +#if defined(qLittleEndian) + unsigned int CP_MH_send : 1; + unsigned int CP_MH_write : 1; + unsigned int CP_MH_tag : 3; + unsigned int CP_MH_ad_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int CP_MH_ad_31_5 : 27; + unsigned int CP_MH_tag : 3; + unsigned int CP_MH_write : 1; + unsigned int CP_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG06 { + struct { +#if defined(qLittleEndian) + unsigned int CP_MH_data_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CP_MH_data_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG07 { + struct { +#if defined(qLittleEndian) + unsigned int CP_MH_data_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CP_MH_data_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG08 { + struct { +#if defined(qLittleEndian) + unsigned int CP_MH_be : 8; + unsigned int RB_MH_be : 8; + unsigned int PA_MH_be : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int PA_MH_be : 8; + unsigned int RB_MH_be : 8; + unsigned int CP_MH_be : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG09 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 3; + unsigned int VGT_MH_send : 1; + unsigned int VGT_MH_tagbe : 1; + unsigned int VGT_MH_ad_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int VGT_MH_ad_31_5 : 27; + unsigned int VGT_MH_tagbe : 1; + unsigned int VGT_MH_send : 1; + unsigned int ALWAYS_ZERO : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG10 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 2; + unsigned int TC_MH_send : 1; + unsigned int TC_MH_mask : 2; + unsigned int TC_MH_addr_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int TC_MH_addr_31_5 : 27; + unsigned int TC_MH_mask : 2; + unsigned int TC_MH_send : 1; + unsigned int ALWAYS_ZERO : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG11 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_info : 25; + unsigned int TC_MH_send : 1; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int TC_MH_send : 1; + unsigned int TC_MH_info : 25; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG12 { + struct { +#if defined(qLittleEndian) + unsigned int MH_TC_mcinfo : 25; + unsigned int MH_TC_mcinfo_send : 1; + unsigned int TC_MH_written : 1; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int TC_MH_written : 1; + unsigned int MH_TC_mcinfo_send : 1; + unsigned int MH_TC_mcinfo : 25; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG13 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 2; + unsigned int TC_ROQ_SEND : 1; + unsigned int TC_ROQ_MASK : 2; + unsigned int TC_ROQ_ADDR_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int TC_ROQ_ADDR_31_5 : 27; + unsigned int TC_ROQ_MASK : 2; + unsigned int TC_ROQ_SEND : 1; + unsigned int ALWAYS_ZERO : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG14 { + struct { +#if defined(qLittleEndian) + unsigned int TC_ROQ_INFO : 25; + unsigned int TC_ROQ_SEND : 1; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int TC_ROQ_SEND : 1; + unsigned int TC_ROQ_INFO : 25; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG15 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 4; + unsigned int RB_MH_send : 1; + unsigned int RB_MH_addr_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int RB_MH_addr_31_5 : 27; + unsigned int RB_MH_send : 1; + unsigned int ALWAYS_ZERO : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG16 { + struct { +#if defined(qLittleEndian) + unsigned int RB_MH_data_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RB_MH_data_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG17 { + struct { +#if defined(qLittleEndian) + unsigned int RB_MH_data_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RB_MH_data_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG18 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 4; + unsigned int PA_MH_send : 1; + unsigned int PA_MH_addr_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int PA_MH_addr_31_5 : 27; + unsigned int PA_MH_send : 1; + unsigned int ALWAYS_ZERO : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG19 { + struct { +#if defined(qLittleEndian) + unsigned int PA_MH_data_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PA_MH_data_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG20 { + struct { +#if defined(qLittleEndian) + unsigned int PA_MH_data_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PA_MH_data_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG21 { + struct { +#if defined(qLittleEndian) + unsigned int AVALID_q : 1; + unsigned int AREADY_q : 1; + unsigned int AID_q : 3; + unsigned int ALEN_q_2_0 : 3; + unsigned int ARVALID_q : 1; + unsigned int ARREADY_q : 1; + unsigned int ARID_q : 3; + unsigned int ARLEN_q_1_0 : 2; + unsigned int RVALID_q : 1; + unsigned int RREADY_q : 1; + unsigned int RLAST_q : 1; + unsigned int RID_q : 3; + unsigned int WVALID_q : 1; + unsigned int WREADY_q : 1; + unsigned int WLAST_q : 1; + unsigned int WID_q : 3; + unsigned int BVALID_q : 1; + unsigned int BREADY_q : 1; + unsigned int BID_q : 3; +#else /* !defined(qLittleEndian) */ + unsigned int BID_q : 3; + unsigned int BREADY_q : 1; + unsigned int BVALID_q : 1; + unsigned int WID_q : 3; + unsigned int WLAST_q : 1; + unsigned int WREADY_q : 1; + unsigned int WVALID_q : 1; + unsigned int RID_q : 3; + unsigned int RLAST_q : 1; + unsigned int RREADY_q : 1; + unsigned int RVALID_q : 1; + unsigned int ARLEN_q_1_0 : 2; + unsigned int ARID_q : 3; + unsigned int ARREADY_q : 1; + unsigned int ARVALID_q : 1; + unsigned int ALEN_q_2_0 : 3; + unsigned int AID_q : 3; + unsigned int AREADY_q : 1; + unsigned int AVALID_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG22 { + struct { +#if defined(qLittleEndian) + unsigned int AVALID_q : 1; + unsigned int AREADY_q : 1; + unsigned int AID_q : 3; + unsigned int ALEN_q_1_0 : 2; + unsigned int ARVALID_q : 1; + unsigned int ARREADY_q : 1; + unsigned int ARID_q : 3; + unsigned int ARLEN_q_1_1 : 1; + unsigned int WVALID_q : 1; + unsigned int WREADY_q : 1; + unsigned int WLAST_q : 1; + unsigned int WID_q : 3; + unsigned int WSTRB_q : 8; + unsigned int BVALID_q : 1; + unsigned int BREADY_q : 1; + unsigned int BID_q : 3; +#else /* !defined(qLittleEndian) */ + unsigned int BID_q : 3; + unsigned int BREADY_q : 1; + unsigned int BVALID_q : 1; + unsigned int WSTRB_q : 8; + unsigned int WID_q : 3; + unsigned int WLAST_q : 1; + unsigned int WREADY_q : 1; + unsigned int WVALID_q : 1; + unsigned int ARLEN_q_1_1 : 1; + unsigned int ARID_q : 3; + unsigned int ARREADY_q : 1; + unsigned int ARVALID_q : 1; + unsigned int ALEN_q_1_0 : 2; + unsigned int AID_q : 3; + unsigned int AREADY_q : 1; + unsigned int AVALID_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG23 { + struct { +#if defined(qLittleEndian) + unsigned int ARC_CTRL_RE_q : 1; + unsigned int CTRL_ARC_ID : 3; + unsigned int CTRL_ARC_PAD : 28; +#else /* !defined(qLittleEndian) */ + unsigned int CTRL_ARC_PAD : 28; + unsigned int CTRL_ARC_ID : 3; + unsigned int ARC_CTRL_RE_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG24 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 2; + unsigned int REG_A : 14; + unsigned int REG_RE : 1; + unsigned int REG_WE : 1; + unsigned int BLOCK_RS : 1; + unsigned int : 13; +#else /* !defined(qLittleEndian) */ + unsigned int : 13; + unsigned int BLOCK_RS : 1; + unsigned int REG_WE : 1; + unsigned int REG_RE : 1; + unsigned int REG_A : 14; + unsigned int ALWAYS_ZERO : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG25 { + struct { +#if defined(qLittleEndian) + unsigned int REG_WD : 32; +#else /* !defined(qLittleEndian) */ + unsigned int REG_WD : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG26 { + struct { +#if defined(qLittleEndian) + unsigned int MH_RBBM_busy : 1; + unsigned int MH_CIB_mh_clk_en_int : 1; + unsigned int MH_CIB_mmu_clk_en_int : 1; + unsigned int MH_CIB_tcroq_clk_en_int : 1; + unsigned int GAT_CLK_ENA : 1; + unsigned int RBBM_MH_clk_en_override : 1; + unsigned int CNT_q : 6; + unsigned int TCD_EMPTY_q : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int MH_BUSY_d : 1; + unsigned int ANY_CLNT_BUSY : 1; + unsigned int MH_MMU_INVALIDATE_INVALIDATE_ALL : 1; + unsigned int MH_MMU_INVALIDATE_INVALIDATE_TC : 1; + unsigned int CP_SEND_q : 1; + unsigned int CP_RTR_q : 1; + unsigned int VGT_SEND_q : 1; + unsigned int VGT_RTR_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_ROQ_RTR_DBG_q : 1; + unsigned int RB_SEND_q : 1; + unsigned int RB_RTR_q : 1; + unsigned int PA_SEND_q : 1; + unsigned int PA_RTR_q : 1; + unsigned int RDC_VALID : 1; + unsigned int RDC_RLAST : 1; + unsigned int TLBMISS_VALID : 1; + unsigned int BRC_VALID : 1; +#else /* !defined(qLittleEndian) */ + unsigned int BRC_VALID : 1; + unsigned int TLBMISS_VALID : 1; + unsigned int RDC_RLAST : 1; + unsigned int RDC_VALID : 1; + unsigned int PA_RTR_q : 1; + unsigned int PA_SEND_q : 1; + unsigned int RB_RTR_q : 1; + unsigned int RB_SEND_q : 1; + unsigned int TC_ROQ_RTR_DBG_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int VGT_RTR_q : 1; + unsigned int VGT_SEND_q : 1; + unsigned int CP_RTR_q : 1; + unsigned int CP_SEND_q : 1; + unsigned int MH_MMU_INVALIDATE_INVALIDATE_TC : 1; + unsigned int MH_MMU_INVALIDATE_INVALIDATE_ALL : 1; + unsigned int ANY_CLNT_BUSY : 1; + unsigned int MH_BUSY_d : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TCD_EMPTY_q : 1; + unsigned int CNT_q : 6; + unsigned int RBBM_MH_clk_en_override : 1; + unsigned int GAT_CLK_ENA : 1; + unsigned int MH_CIB_tcroq_clk_en_int : 1; + unsigned int MH_CIB_mmu_clk_en_int : 1; + unsigned int MH_CIB_mh_clk_en_int : 1; + unsigned int MH_RBBM_busy : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG27 { + struct { +#if defined(qLittleEndian) + unsigned int EFF2_FP_WINNER : 3; + unsigned int EFF2_LRU_WINNER_out : 3; + unsigned int EFF1_WINNER : 3; + unsigned int ARB_WINNER : 3; + unsigned int ARB_WINNER_q : 3; + unsigned int EFF1_WIN : 1; + unsigned int KILL_EFF1 : 1; + unsigned int ARB_HOLD : 1; + unsigned int ARB_RTR_q : 1; + unsigned int CP_SEND_QUAL : 1; + unsigned int VGT_SEND_QUAL : 1; + unsigned int TC_SEND_QUAL : 1; + unsigned int TC_SEND_EFF1_QUAL : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int PA_SEND_QUAL : 1; + unsigned int ARB_QUAL : 1; + unsigned int CP_EFF1_REQ : 1; + unsigned int VGT_EFF1_REQ : 1; + unsigned int TC_EFF1_REQ : 1; + unsigned int RB_EFF1_REQ : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int TCHOLD_IP_q : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TCHOLD_IP_q : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int RB_EFF1_REQ : 1; + unsigned int TC_EFF1_REQ : 1; + unsigned int VGT_EFF1_REQ : 1; + unsigned int CP_EFF1_REQ : 1; + unsigned int ARB_QUAL : 1; + unsigned int PA_SEND_QUAL : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int TC_SEND_EFF1_QUAL : 1; + unsigned int TC_SEND_QUAL : 1; + unsigned int VGT_SEND_QUAL : 1; + unsigned int CP_SEND_QUAL : 1; + unsigned int ARB_RTR_q : 1; + unsigned int ARB_HOLD : 1; + unsigned int KILL_EFF1 : 1; + unsigned int EFF1_WIN : 1; + unsigned int ARB_WINNER_q : 3; + unsigned int ARB_WINNER : 3; + unsigned int EFF1_WINNER : 3; + unsigned int EFF2_LRU_WINNER_out : 3; + unsigned int EFF2_FP_WINNER : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG28 { + struct { +#if defined(qLittleEndian) + unsigned int EFF1_WINNER : 3; + unsigned int ARB_WINNER : 3; + unsigned int CP_SEND_QUAL : 1; + unsigned int VGT_SEND_QUAL : 1; + unsigned int TC_SEND_QUAL : 1; + unsigned int TC_SEND_EFF1_QUAL : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int ARB_QUAL : 1; + unsigned int CP_EFF1_REQ : 1; + unsigned int VGT_EFF1_REQ : 1; + unsigned int TC_EFF1_REQ : 1; + unsigned int RB_EFF1_REQ : 1; + unsigned int EFF1_WIN : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int TC_ARB_HOLD : 1; + unsigned int ARB_HOLD : 1; + unsigned int ARB_RTR_q : 1; + unsigned int SAME_PAGE_LIMIT_COUNT_q : 10; +#else /* !defined(qLittleEndian) */ + unsigned int SAME_PAGE_LIMIT_COUNT_q : 10; + unsigned int ARB_RTR_q : 1; + unsigned int ARB_HOLD : 1; + unsigned int TC_ARB_HOLD : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int KILL_EFF1 : 1; + unsigned int EFF1_WIN : 1; + unsigned int RB_EFF1_REQ : 1; + unsigned int TC_EFF1_REQ : 1; + unsigned int VGT_EFF1_REQ : 1; + unsigned int CP_EFF1_REQ : 1; + unsigned int ARB_QUAL : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int TC_SEND_EFF1_QUAL : 1; + unsigned int TC_SEND_QUAL : 1; + unsigned int VGT_SEND_QUAL : 1; + unsigned int CP_SEND_QUAL : 1; + unsigned int ARB_WINNER : 3; + unsigned int EFF1_WINNER : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG29 { + struct { +#if defined(qLittleEndian) + unsigned int EFF2_LRU_WINNER_out : 3; + unsigned int LEAST_RECENT_INDEX_d : 3; + unsigned int LEAST_RECENT_d : 3; + unsigned int UPDATE_RECENT_STACK_d : 1; + unsigned int ARB_HOLD : 1; + unsigned int ARB_RTR_q : 1; + unsigned int CLNT_REQ : 5; + unsigned int RECENT_d_0 : 3; + unsigned int RECENT_d_1 : 3; + unsigned int RECENT_d_2 : 3; + unsigned int RECENT_d_3 : 3; + unsigned int RECENT_d_4 : 3; +#else /* !defined(qLittleEndian) */ + unsigned int RECENT_d_4 : 3; + unsigned int RECENT_d_3 : 3; + unsigned int RECENT_d_2 : 3; + unsigned int RECENT_d_1 : 3; + unsigned int RECENT_d_0 : 3; + unsigned int CLNT_REQ : 5; + unsigned int ARB_RTR_q : 1; + unsigned int ARB_HOLD : 1; + unsigned int UPDATE_RECENT_STACK_d : 1; + unsigned int LEAST_RECENT_d : 3; + unsigned int LEAST_RECENT_INDEX_d : 3; + unsigned int EFF2_LRU_WINNER_out : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG30 { + struct { +#if defined(qLittleEndian) + unsigned int TC_ARB_HOLD : 1; + unsigned int TC_NOROQ_SAME_ROW_BANK : 1; + unsigned int TC_ROQ_SAME_ROW_BANK : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int TCHOLD_IP_q : 1; + unsigned int TCHOLD_CNT_q : 3; + unsigned int MH_ARBITER_CONFIG_TC_REORDER_ENABLE : 1; + unsigned int TC_ROQ_RTR_DBG_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_MH_written : 1; + unsigned int TCD_FULLNESS_CNT_q : 7; + unsigned int WBURST_ACTIVE : 1; + unsigned int WLAST_q : 1; + unsigned int WBURST_IP_q : 1; + unsigned int WBURST_CNT_q : 3; + unsigned int CP_SEND_QUAL : 1; + unsigned int CP_MH_write : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int PA_SEND_QUAL : 1; + unsigned int ARB_WINNER : 3; +#else /* !defined(qLittleEndian) */ + unsigned int ARB_WINNER : 3; + unsigned int PA_SEND_QUAL : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int CP_MH_write : 1; + unsigned int CP_SEND_QUAL : 1; + unsigned int WBURST_CNT_q : 3; + unsigned int WBURST_IP_q : 1; + unsigned int WLAST_q : 1; + unsigned int WBURST_ACTIVE : 1; + unsigned int TCD_FULLNESS_CNT_q : 7; + unsigned int TC_MH_written : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_ROQ_RTR_DBG_q : 1; + unsigned int MH_ARBITER_CONFIG_TC_REORDER_ENABLE : 1; + unsigned int TCHOLD_CNT_q : 3; + unsigned int TCHOLD_IP_q : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int TC_ROQ_SAME_ROW_BANK : 1; + unsigned int TC_NOROQ_SAME_ROW_BANK : 1; + unsigned int TC_ARB_HOLD : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG31 { + struct { +#if defined(qLittleEndian) + unsigned int RF_ARBITER_CONFIG_q : 26; + unsigned int MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3; + unsigned int RF_ARBITER_CONFIG_q : 26; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG32 { + struct { +#if defined(qLittleEndian) + unsigned int SAME_ROW_BANK_q : 8; + unsigned int ROQ_MARK_q : 8; + unsigned int ROQ_VALID_q : 8; + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TC_ROQ_SAME_ROW_BANK_SEL : 1; + unsigned int ANY_SAME_ROW_BANK : 1; + unsigned int TC_EFF1_QUAL : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TC_ROQ_FULL : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TC_ROQ_FULL : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TC_EFF1_QUAL : 1; + unsigned int ANY_SAME_ROW_BANK : 1; + unsigned int TC_ROQ_SAME_ROW_BANK_SEL : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; + unsigned int ROQ_VALID_q : 8; + unsigned int ROQ_MARK_q : 8; + unsigned int SAME_ROW_BANK_q : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG33 { + struct { +#if defined(qLittleEndian) + unsigned int SAME_ROW_BANK_q : 8; + unsigned int ROQ_MARK_d : 8; + unsigned int ROQ_VALID_d : 8; + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TC_ROQ_SAME_ROW_BANK_SEL : 1; + unsigned int ANY_SAME_ROW_BANK : 1; + unsigned int TC_EFF1_QUAL : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TC_ROQ_FULL : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TC_ROQ_FULL : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TC_EFF1_QUAL : 1; + unsigned int ANY_SAME_ROW_BANK : 1; + unsigned int TC_ROQ_SAME_ROW_BANK_SEL : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; + unsigned int ROQ_VALID_d : 8; + unsigned int ROQ_MARK_d : 8; + unsigned int SAME_ROW_BANK_q : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG34 { + struct { +#if defined(qLittleEndian) + unsigned int SAME_ROW_BANK_WIN : 8; + unsigned int SAME_ROW_BANK_REQ : 8; + unsigned int NON_SAME_ROW_BANK_WIN : 8; + unsigned int NON_SAME_ROW_BANK_REQ : 8; +#else /* !defined(qLittleEndian) */ + unsigned int NON_SAME_ROW_BANK_REQ : 8; + unsigned int NON_SAME_ROW_BANK_WIN : 8; + unsigned int SAME_ROW_BANK_REQ : 8; + unsigned int SAME_ROW_BANK_WIN : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG35 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_0 : 1; + unsigned int ROQ_VALID_q_0 : 1; + unsigned int SAME_ROW_BANK_q_0 : 1; + unsigned int ROQ_ADDR_0 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_0 : 27; + unsigned int SAME_ROW_BANK_q_0 : 1; + unsigned int ROQ_VALID_q_0 : 1; + unsigned int ROQ_MARK_q_0 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG36 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_1 : 1; + unsigned int ROQ_VALID_q_1 : 1; + unsigned int SAME_ROW_BANK_q_1 : 1; + unsigned int ROQ_ADDR_1 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_1 : 27; + unsigned int SAME_ROW_BANK_q_1 : 1; + unsigned int ROQ_VALID_q_1 : 1; + unsigned int ROQ_MARK_q_1 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG37 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_2 : 1; + unsigned int ROQ_VALID_q_2 : 1; + unsigned int SAME_ROW_BANK_q_2 : 1; + unsigned int ROQ_ADDR_2 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_2 : 27; + unsigned int SAME_ROW_BANK_q_2 : 1; + unsigned int ROQ_VALID_q_2 : 1; + unsigned int ROQ_MARK_q_2 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG38 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_3 : 1; + unsigned int ROQ_VALID_q_3 : 1; + unsigned int SAME_ROW_BANK_q_3 : 1; + unsigned int ROQ_ADDR_3 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_3 : 27; + unsigned int SAME_ROW_BANK_q_3 : 1; + unsigned int ROQ_VALID_q_3 : 1; + unsigned int ROQ_MARK_q_3 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG39 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_4 : 1; + unsigned int ROQ_VALID_q_4 : 1; + unsigned int SAME_ROW_BANK_q_4 : 1; + unsigned int ROQ_ADDR_4 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_4 : 27; + unsigned int SAME_ROW_BANK_q_4 : 1; + unsigned int ROQ_VALID_q_4 : 1; + unsigned int ROQ_MARK_q_4 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG40 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_5 : 1; + unsigned int ROQ_VALID_q_5 : 1; + unsigned int SAME_ROW_BANK_q_5 : 1; + unsigned int ROQ_ADDR_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_5 : 27; + unsigned int SAME_ROW_BANK_q_5 : 1; + unsigned int ROQ_VALID_q_5 : 1; + unsigned int ROQ_MARK_q_5 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG41 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_6 : 1; + unsigned int ROQ_VALID_q_6 : 1; + unsigned int SAME_ROW_BANK_q_6 : 1; + unsigned int ROQ_ADDR_6 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_6 : 27; + unsigned int SAME_ROW_BANK_q_6 : 1; + unsigned int ROQ_VALID_q_6 : 1; + unsigned int ROQ_MARK_q_6 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG42 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_7 : 1; + unsigned int ROQ_VALID_q_7 : 1; + unsigned int SAME_ROW_BANK_q_7 : 1; + unsigned int ROQ_ADDR_7 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_7 : 27; + unsigned int SAME_ROW_BANK_q_7 : 1; + unsigned int ROQ_VALID_q_7 : 1; + unsigned int ROQ_MARK_q_7 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG43 { + struct { +#if defined(qLittleEndian) + unsigned int ARB_REG_WE_q : 1; + unsigned int ARB_WE : 1; + unsigned int ARB_REG_VALID_q : 1; + unsigned int ARB_RTR_q : 1; + unsigned int ARB_REG_RTR : 1; + unsigned int WDAT_BURST_RTR : 1; + unsigned int MMU_RTR : 1; + unsigned int ARB_ID_q : 3; + unsigned int ARB_WRITE_q : 1; + unsigned int ARB_BLEN_q : 1; + unsigned int ARQ_CTRL_EMPTY : 1; + unsigned int ARQ_FIFO_CNT_q : 3; + unsigned int MMU_WE : 1; + unsigned int ARQ_RTR : 1; + unsigned int MMU_ID : 3; + unsigned int MMU_WRITE : 1; + unsigned int MMU_BLEN : 1; + unsigned int WBURST_IP_q : 1; + unsigned int WDAT_REG_WE_q : 1; + unsigned int WDB_WE : 1; + unsigned int WDB_RTR_SKID_4 : 1; + unsigned int WDB_RTR_SKID_3 : 1; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int WDB_RTR_SKID_3 : 1; + unsigned int WDB_RTR_SKID_4 : 1; + unsigned int WDB_WE : 1; + unsigned int WDAT_REG_WE_q : 1; + unsigned int WBURST_IP_q : 1; + unsigned int MMU_BLEN : 1; + unsigned int MMU_WRITE : 1; + unsigned int MMU_ID : 3; + unsigned int ARQ_RTR : 1; + unsigned int MMU_WE : 1; + unsigned int ARQ_FIFO_CNT_q : 3; + unsigned int ARQ_CTRL_EMPTY : 1; + unsigned int ARB_BLEN_q : 1; + unsigned int ARB_WRITE_q : 1; + unsigned int ARB_ID_q : 3; + unsigned int MMU_RTR : 1; + unsigned int WDAT_BURST_RTR : 1; + unsigned int ARB_REG_RTR : 1; + unsigned int ARB_RTR_q : 1; + unsigned int ARB_REG_VALID_q : 1; + unsigned int ARB_WE : 1; + unsigned int ARB_REG_WE_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG44 { + struct { +#if defined(qLittleEndian) + unsigned int ARB_WE : 1; + unsigned int ARB_ID_q : 3; + unsigned int ARB_VAD_q : 28; +#else /* !defined(qLittleEndian) */ + unsigned int ARB_VAD_q : 28; + unsigned int ARB_ID_q : 3; + unsigned int ARB_WE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG45 { + struct { +#if defined(qLittleEndian) + unsigned int MMU_WE : 1; + unsigned int MMU_ID : 3; + unsigned int MMU_PAD : 28; +#else /* !defined(qLittleEndian) */ + unsigned int MMU_PAD : 28; + unsigned int MMU_ID : 3; + unsigned int MMU_WE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG46 { + struct { +#if defined(qLittleEndian) + unsigned int WDAT_REG_WE_q : 1; + unsigned int WDB_WE : 1; + unsigned int WDAT_REG_VALID_q : 1; + unsigned int WDB_RTR_SKID_4 : 1; + unsigned int ARB_WSTRB_q : 8; + unsigned int ARB_WLAST : 1; + unsigned int WDB_CTRL_EMPTY : 1; + unsigned int WDB_FIFO_CNT_q : 5; + unsigned int WDC_WDB_RE_q : 1; + unsigned int WDB_WDC_WID : 3; + unsigned int WDB_WDC_WLAST : 1; + unsigned int WDB_WDC_WSTRB : 8; +#else /* !defined(qLittleEndian) */ + unsigned int WDB_WDC_WSTRB : 8; + unsigned int WDB_WDC_WLAST : 1; + unsigned int WDB_WDC_WID : 3; + unsigned int WDC_WDB_RE_q : 1; + unsigned int WDB_FIFO_CNT_q : 5; + unsigned int WDB_CTRL_EMPTY : 1; + unsigned int ARB_WLAST : 1; + unsigned int ARB_WSTRB_q : 8; + unsigned int WDB_RTR_SKID_4 : 1; + unsigned int WDAT_REG_VALID_q : 1; + unsigned int WDB_WE : 1; + unsigned int WDAT_REG_WE_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG47 { + struct { +#if defined(qLittleEndian) + unsigned int WDB_WDC_WDATA_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int WDB_WDC_WDATA_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG48 { + struct { +#if defined(qLittleEndian) + unsigned int WDB_WDC_WDATA_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int WDB_WDC_WDATA_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG49 { + struct { +#if defined(qLittleEndian) + unsigned int CTRL_ARC_EMPTY : 1; + unsigned int CTRL_RARC_EMPTY : 1; + unsigned int ARQ_CTRL_EMPTY : 1; + unsigned int ARQ_CTRL_WRITE : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int INFLT_LIMIT_q : 1; + unsigned int INFLT_LIMIT_CNT_q : 6; + unsigned int ARC_CTRL_RE_q : 1; + unsigned int RARC_CTRL_RE_q : 1; + unsigned int RVALID_q : 1; + unsigned int RREADY_q : 1; + unsigned int RLAST_q : 1; + unsigned int BVALID_q : 1; + unsigned int BREADY_q : 1; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int BREADY_q : 1; + unsigned int BVALID_q : 1; + unsigned int RLAST_q : 1; + unsigned int RREADY_q : 1; + unsigned int RVALID_q : 1; + unsigned int RARC_CTRL_RE_q : 1; + unsigned int ARC_CTRL_RE_q : 1; + unsigned int INFLT_LIMIT_CNT_q : 6; + unsigned int INFLT_LIMIT_q : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int ARQ_CTRL_WRITE : 1; + unsigned int ARQ_CTRL_EMPTY : 1; + unsigned int CTRL_RARC_EMPTY : 1; + unsigned int CTRL_ARC_EMPTY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG50 { + struct { +#if defined(qLittleEndian) + unsigned int MH_CP_grb_send : 1; + unsigned int MH_VGT_grb_send : 1; + unsigned int MH_TC_mcsend : 1; + unsigned int MH_TLBMISS_SEND : 1; + unsigned int TLBMISS_VALID : 1; + unsigned int RDC_VALID : 1; + unsigned int RDC_RID : 3; + unsigned int RDC_RLAST : 1; + unsigned int RDC_RRESP : 2; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int MMU_ID_REQUEST_q : 1; + unsigned int OUTSTANDING_MMUID_CNT_q : 6; + unsigned int MMU_ID_RESPONSE : 1; + unsigned int TLBMISS_RETURN_CNT_q : 6; + unsigned int CNT_HOLD_q1 : 1; + unsigned int MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3; +#else /* !defined(qLittleEndian) */ + unsigned int MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3; + unsigned int CNT_HOLD_q1 : 1; + unsigned int TLBMISS_RETURN_CNT_q : 6; + unsigned int MMU_ID_RESPONSE : 1; + unsigned int OUTSTANDING_MMUID_CNT_q : 6; + unsigned int MMU_ID_REQUEST_q : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int RDC_RRESP : 2; + unsigned int RDC_RLAST : 1; + unsigned int RDC_RID : 3; + unsigned int RDC_VALID : 1; + unsigned int TLBMISS_VALID : 1; + unsigned int MH_TLBMISS_SEND : 1; + unsigned int MH_TC_mcsend : 1; + unsigned int MH_VGT_grb_send : 1; + unsigned int MH_CP_grb_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG51 { + struct { +#if defined(qLittleEndian) + unsigned int RF_MMU_PAGE_FAULT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RF_MMU_PAGE_FAULT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG52 { + struct { +#if defined(qLittleEndian) + unsigned int RF_MMU_CONFIG_q_1_to_0 : 2; + unsigned int ARB_WE : 1; + unsigned int MMU_RTR : 1; + unsigned int RF_MMU_CONFIG_q_25_to_4 : 22; + unsigned int ARB_ID_q : 3; + unsigned int ARB_WRITE_q : 1; + unsigned int client_behavior_q : 2; +#else /* !defined(qLittleEndian) */ + unsigned int client_behavior_q : 2; + unsigned int ARB_WRITE_q : 1; + unsigned int ARB_ID_q : 3; + unsigned int RF_MMU_CONFIG_q_25_to_4 : 22; + unsigned int MMU_RTR : 1; + unsigned int ARB_WE : 1; + unsigned int RF_MMU_CONFIG_q_1_to_0 : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG53 { + struct { +#if defined(qLittleEndian) + unsigned int stage1_valid : 1; + unsigned int IGNORE_TAG_MISS_q : 1; + unsigned int pa_in_mpu_range : 1; + unsigned int tag_match_q : 1; + unsigned int tag_miss_q : 1; + unsigned int va_in_range_q : 1; + unsigned int MMU_MISS : 1; + unsigned int MMU_READ_MISS : 1; + unsigned int MMU_WRITE_MISS : 1; + unsigned int MMU_HIT : 1; + unsigned int MMU_READ_HIT : 1; + unsigned int MMU_WRITE_HIT : 1; + unsigned int MMU_SPLIT_MODE_TC_MISS : 1; + unsigned int MMU_SPLIT_MODE_TC_HIT : 1; + unsigned int MMU_SPLIT_MODE_nonTC_MISS : 1; + unsigned int MMU_SPLIT_MODE_nonTC_HIT : 1; + unsigned int REQ_VA_OFFSET_q : 16; +#else /* !defined(qLittleEndian) */ + unsigned int REQ_VA_OFFSET_q : 16; + unsigned int MMU_SPLIT_MODE_nonTC_HIT : 1; + unsigned int MMU_SPLIT_MODE_nonTC_MISS : 1; + unsigned int MMU_SPLIT_MODE_TC_HIT : 1; + unsigned int MMU_SPLIT_MODE_TC_MISS : 1; + unsigned int MMU_WRITE_HIT : 1; + unsigned int MMU_READ_HIT : 1; + unsigned int MMU_HIT : 1; + unsigned int MMU_WRITE_MISS : 1; + unsigned int MMU_READ_MISS : 1; + unsigned int MMU_MISS : 1; + unsigned int va_in_range_q : 1; + unsigned int tag_miss_q : 1; + unsigned int tag_match_q : 1; + unsigned int pa_in_mpu_range : 1; + unsigned int IGNORE_TAG_MISS_q : 1; + unsigned int stage1_valid : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG54 { + struct { +#if defined(qLittleEndian) + unsigned int ARQ_RTR : 1; + unsigned int MMU_WE : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int MH_TLBMISS_SEND : 1; + unsigned int MMU_STALL_AWAITING_TLB_MISS_FETCH : 1; + unsigned int pa_in_mpu_range : 1; + unsigned int stage1_valid : 1; + unsigned int stage2_valid : 1; + unsigned int client_behavior_q : 2; + unsigned int IGNORE_TAG_MISS_q : 1; + unsigned int tag_match_q : 1; + unsigned int tag_miss_q : 1; + unsigned int va_in_range_q : 1; + unsigned int PTE_FETCH_COMPLETE_q : 1; + unsigned int TAG_valid_q : 16; +#else /* !defined(qLittleEndian) */ + unsigned int TAG_valid_q : 16; + unsigned int PTE_FETCH_COMPLETE_q : 1; + unsigned int va_in_range_q : 1; + unsigned int tag_miss_q : 1; + unsigned int tag_match_q : 1; + unsigned int IGNORE_TAG_MISS_q : 1; + unsigned int client_behavior_q : 2; + unsigned int stage2_valid : 1; + unsigned int stage1_valid : 1; + unsigned int pa_in_mpu_range : 1; + unsigned int MMU_STALL_AWAITING_TLB_MISS_FETCH : 1; + unsigned int MH_TLBMISS_SEND : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int MMU_WE : 1; + unsigned int ARQ_RTR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG55 { + struct { +#if defined(qLittleEndian) + unsigned int TAG0_VA : 13; + unsigned int TAG_valid_q_0 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG1_VA : 13; + unsigned int TAG_valid_q_1 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_1 : 1; + unsigned int TAG1_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_0 : 1; + unsigned int TAG0_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG56 { + struct { +#if defined(qLittleEndian) + unsigned int TAG2_VA : 13; + unsigned int TAG_valid_q_2 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG3_VA : 13; + unsigned int TAG_valid_q_3 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_3 : 1; + unsigned int TAG3_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_2 : 1; + unsigned int TAG2_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG57 { + struct { +#if defined(qLittleEndian) + unsigned int TAG4_VA : 13; + unsigned int TAG_valid_q_4 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG5_VA : 13; + unsigned int TAG_valid_q_5 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_5 : 1; + unsigned int TAG5_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_4 : 1; + unsigned int TAG4_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG58 { + struct { +#if defined(qLittleEndian) + unsigned int TAG6_VA : 13; + unsigned int TAG_valid_q_6 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG7_VA : 13; + unsigned int TAG_valid_q_7 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_7 : 1; + unsigned int TAG7_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_6 : 1; + unsigned int TAG6_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG59 { + struct { +#if defined(qLittleEndian) + unsigned int TAG8_VA : 13; + unsigned int TAG_valid_q_8 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG9_VA : 13; + unsigned int TAG_valid_q_9 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_9 : 1; + unsigned int TAG9_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_8 : 1; + unsigned int TAG8_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG60 { + struct { +#if defined(qLittleEndian) + unsigned int TAG10_VA : 13; + unsigned int TAG_valid_q_10 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG11_VA : 13; + unsigned int TAG_valid_q_11 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_11 : 1; + unsigned int TAG11_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_10 : 1; + unsigned int TAG10_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG61 { + struct { +#if defined(qLittleEndian) + unsigned int TAG12_VA : 13; + unsigned int TAG_valid_q_12 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG13_VA : 13; + unsigned int TAG_valid_q_13 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_13 : 1; + unsigned int TAG13_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_12 : 1; + unsigned int TAG12_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG62 { + struct { +#if defined(qLittleEndian) + unsigned int TAG14_VA : 13; + unsigned int TAG_valid_q_14 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG15_VA : 13; + unsigned int TAG_valid_q_15 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_15 : 1; + unsigned int TAG15_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_14 : 1; + unsigned int TAG14_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG63 { + struct { +#if defined(qLittleEndian) + unsigned int MH_DBG_DEFAULT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int MH_DBG_DEFAULT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int MMU_ENABLE : 1; + unsigned int SPLIT_MODE_ENABLE : 1; + unsigned int RESERVED1 : 2; + unsigned int RB_W_CLNT_BEHAVIOR : 2; + unsigned int CP_W_CLNT_BEHAVIOR : 2; + unsigned int CP_R0_CLNT_BEHAVIOR : 2; + unsigned int CP_R1_CLNT_BEHAVIOR : 2; + unsigned int CP_R2_CLNT_BEHAVIOR : 2; + unsigned int CP_R3_CLNT_BEHAVIOR : 2; + unsigned int CP_R4_CLNT_BEHAVIOR : 2; + unsigned int VGT_R0_CLNT_BEHAVIOR : 2; + unsigned int VGT_R1_CLNT_BEHAVIOR : 2; + unsigned int TC_R_CLNT_BEHAVIOR : 2; + unsigned int PA_W_CLNT_BEHAVIOR : 2; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int PA_W_CLNT_BEHAVIOR : 2; + unsigned int TC_R_CLNT_BEHAVIOR : 2; + unsigned int VGT_R1_CLNT_BEHAVIOR : 2; + unsigned int VGT_R0_CLNT_BEHAVIOR : 2; + unsigned int CP_R4_CLNT_BEHAVIOR : 2; + unsigned int CP_R3_CLNT_BEHAVIOR : 2; + unsigned int CP_R2_CLNT_BEHAVIOR : 2; + unsigned int CP_R1_CLNT_BEHAVIOR : 2; + unsigned int CP_R0_CLNT_BEHAVIOR : 2; + unsigned int CP_W_CLNT_BEHAVIOR : 2; + unsigned int RB_W_CLNT_BEHAVIOR : 2; + unsigned int RESERVED1 : 2; + unsigned int SPLIT_MODE_ENABLE : 1; + unsigned int MMU_ENABLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_VA_RANGE { + struct { +#if defined(qLittleEndian) + unsigned int NUM_64KB_REGIONS : 12; + unsigned int VA_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int VA_BASE : 20; + unsigned int NUM_64KB_REGIONS : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_PT_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int PT_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int PT_BASE : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_PAGE_FAULT { + struct { +#if defined(qLittleEndian) + unsigned int PAGE_FAULT : 1; + unsigned int OP_TYPE : 1; + unsigned int CLNT_BEHAVIOR : 2; + unsigned int AXI_ID : 3; + unsigned int RESERVED1 : 1; + unsigned int MPU_ADDRESS_OUT_OF_RANGE : 1; + unsigned int ADDRESS_OUT_OF_RANGE : 1; + unsigned int READ_PROTECTION_ERROR : 1; + unsigned int WRITE_PROTECTION_ERROR : 1; + unsigned int REQ_VA : 20; +#else /* !defined(qLittleEndian) */ + unsigned int REQ_VA : 20; + unsigned int WRITE_PROTECTION_ERROR : 1; + unsigned int READ_PROTECTION_ERROR : 1; + unsigned int ADDRESS_OUT_OF_RANGE : 1; + unsigned int MPU_ADDRESS_OUT_OF_RANGE : 1; + unsigned int RESERVED1 : 1; + unsigned int AXI_ID : 3; + unsigned int CLNT_BEHAVIOR : 2; + unsigned int OP_TYPE : 1; + unsigned int PAGE_FAULT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_TRAN_ERROR { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int TRAN_ERROR : 27; +#else /* !defined(qLittleEndian) */ + unsigned int TRAN_ERROR : 27; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_INVALIDATE { + struct { +#if defined(qLittleEndian) + unsigned int INVALIDATE_ALL : 1; + unsigned int INVALIDATE_TC : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int INVALIDATE_TC : 1; + unsigned int INVALIDATE_ALL : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_MPU_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int MPU_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int MPU_BASE : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_MPU_END { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int MPU_END : 20; +#else /* !defined(qLittleEndian) */ + unsigned int MPU_END : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union WAIT_UNTIL { + struct { +#if defined(qLittleEndian) + unsigned int : 1; + unsigned int WAIT_RE_VSYNC : 1; + unsigned int WAIT_FE_VSYNC : 1; + unsigned int WAIT_VSYNC : 1; + unsigned int WAIT_DSPLY_ID0 : 1; + unsigned int WAIT_DSPLY_ID1 : 1; + unsigned int WAIT_DSPLY_ID2 : 1; + unsigned int : 3; + unsigned int WAIT_CMDFIFO : 1; + unsigned int : 3; + unsigned int WAIT_2D_IDLE : 1; + unsigned int WAIT_3D_IDLE : 1; + unsigned int WAIT_2D_IDLECLEAN : 1; + unsigned int WAIT_3D_IDLECLEAN : 1; + unsigned int : 2; + unsigned int CMDFIFO_ENTRIES : 4; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int CMDFIFO_ENTRIES : 4; + unsigned int : 2; + unsigned int WAIT_3D_IDLECLEAN : 1; + unsigned int WAIT_2D_IDLECLEAN : 1; + unsigned int WAIT_3D_IDLE : 1; + unsigned int WAIT_2D_IDLE : 1; + unsigned int : 3; + unsigned int WAIT_CMDFIFO : 1; + unsigned int : 3; + unsigned int WAIT_DSPLY_ID2 : 1; + unsigned int WAIT_DSPLY_ID1 : 1; + unsigned int WAIT_DSPLY_ID0 : 1; + unsigned int WAIT_VSYNC : 1; + unsigned int WAIT_FE_VSYNC : 1; + unsigned int WAIT_RE_VSYNC : 1; + unsigned int : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_ISYNC_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int : 4; + unsigned int ISYNC_WAIT_IDLEGUI : 1; + unsigned int ISYNC_CPSCRATCH_IDLEGUI : 1; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int ISYNC_CPSCRATCH_IDLEGUI : 1; + unsigned int ISYNC_WAIT_IDLEGUI : 1; + unsigned int : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int CMDFIFO_AVAIL : 5; + unsigned int TC_BUSY : 1; + unsigned int : 2; + unsigned int HIRQ_PENDING : 1; + unsigned int CPRQ_PENDING : 1; + unsigned int CFRQ_PENDING : 1; + unsigned int PFRQ_PENDING : 1; + unsigned int VGT_BUSY_NO_DMA : 1; + unsigned int : 1; + unsigned int RBBM_WU_BUSY : 1; + unsigned int : 1; + unsigned int CP_NRT_BUSY : 1; + unsigned int : 1; + unsigned int MH_BUSY : 1; + unsigned int MH_COHERENCY_BUSY : 1; + unsigned int : 1; + unsigned int SX_BUSY : 1; + unsigned int TPC_BUSY : 1; + unsigned int : 1; + unsigned int SC_CNTX_BUSY : 1; + unsigned int PA_BUSY : 1; + unsigned int VGT_BUSY : 1; + unsigned int SQ_CNTX17_BUSY : 1; + unsigned int SQ_CNTX0_BUSY : 1; + unsigned int : 1; + unsigned int RB_CNTX_BUSY : 1; + unsigned int GUI_ACTIVE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int GUI_ACTIVE : 1; + unsigned int RB_CNTX_BUSY : 1; + unsigned int : 1; + unsigned int SQ_CNTX0_BUSY : 1; + unsigned int SQ_CNTX17_BUSY : 1; + unsigned int VGT_BUSY : 1; + unsigned int PA_BUSY : 1; + unsigned int SC_CNTX_BUSY : 1; + unsigned int : 1; + unsigned int TPC_BUSY : 1; + unsigned int SX_BUSY : 1; + unsigned int : 1; + unsigned int MH_COHERENCY_BUSY : 1; + unsigned int MH_BUSY : 1; + unsigned int : 1; + unsigned int CP_NRT_BUSY : 1; + unsigned int : 1; + unsigned int RBBM_WU_BUSY : 1; + unsigned int : 1; + unsigned int VGT_BUSY_NO_DMA : 1; + unsigned int PFRQ_PENDING : 1; + unsigned int CFRQ_PENDING : 1; + unsigned int CPRQ_PENDING : 1; + unsigned int HIRQ_PENDING : 1; + unsigned int : 2; + unsigned int TC_BUSY : 1; + unsigned int CMDFIFO_AVAIL : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_DSPLY { + struct { +#if defined(qLittleEndian) + unsigned int SEL_DMI_ACTIVE_BUFID0 : 1; + unsigned int SEL_DMI_ACTIVE_BUFID1 : 1; + unsigned int SEL_DMI_ACTIVE_BUFID2 : 1; + unsigned int SEL_DMI_VSYNC_VALID : 1; + unsigned int DMI_CH1_USE_BUFID0 : 1; + unsigned int DMI_CH1_USE_BUFID1 : 1; + unsigned int DMI_CH1_USE_BUFID2 : 1; + unsigned int DMI_CH1_SW_CNTL : 1; + unsigned int DMI_CH1_NUM_BUFS : 2; + unsigned int DMI_CH2_USE_BUFID0 : 1; + unsigned int DMI_CH2_USE_BUFID1 : 1; + unsigned int DMI_CH2_USE_BUFID2 : 1; + unsigned int DMI_CH2_SW_CNTL : 1; + unsigned int DMI_CH2_NUM_BUFS : 2; + unsigned int DMI_CHANNEL_SELECT : 2; + unsigned int : 2; + unsigned int DMI_CH3_USE_BUFID0 : 1; + unsigned int DMI_CH3_USE_BUFID1 : 1; + unsigned int DMI_CH3_USE_BUFID2 : 1; + unsigned int DMI_CH3_SW_CNTL : 1; + unsigned int DMI_CH3_NUM_BUFS : 2; + unsigned int DMI_CH4_USE_BUFID0 : 1; + unsigned int DMI_CH4_USE_BUFID1 : 1; + unsigned int DMI_CH4_USE_BUFID2 : 1; + unsigned int DMI_CH4_SW_CNTL : 1; + unsigned int DMI_CH4_NUM_BUFS : 2; +#else /* !defined(qLittleEndian) */ + unsigned int DMI_CH4_NUM_BUFS : 2; + unsigned int DMI_CH4_SW_CNTL : 1; + unsigned int DMI_CH4_USE_BUFID2 : 1; + unsigned int DMI_CH4_USE_BUFID1 : 1; + unsigned int DMI_CH4_USE_BUFID0 : 1; + unsigned int DMI_CH3_NUM_BUFS : 2; + unsigned int DMI_CH3_SW_CNTL : 1; + unsigned int DMI_CH3_USE_BUFID2 : 1; + unsigned int DMI_CH3_USE_BUFID1 : 1; + unsigned int DMI_CH3_USE_BUFID0 : 1; + unsigned int : 2; + unsigned int DMI_CHANNEL_SELECT : 2; + unsigned int DMI_CH2_NUM_BUFS : 2; + unsigned int DMI_CH2_SW_CNTL : 1; + unsigned int DMI_CH2_USE_BUFID2 : 1; + unsigned int DMI_CH2_USE_BUFID1 : 1; + unsigned int DMI_CH2_USE_BUFID0 : 1; + unsigned int DMI_CH1_NUM_BUFS : 2; + unsigned int DMI_CH1_SW_CNTL : 1; + unsigned int DMI_CH1_USE_BUFID2 : 1; + unsigned int DMI_CH1_USE_BUFID1 : 1; + unsigned int DMI_CH1_USE_BUFID0 : 1; + unsigned int SEL_DMI_VSYNC_VALID : 1; + unsigned int SEL_DMI_ACTIVE_BUFID2 : 1; + unsigned int SEL_DMI_ACTIVE_BUFID1 : 1; + unsigned int SEL_DMI_ACTIVE_BUFID0 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_RENDER_LATEST { + struct { +#if defined(qLittleEndian) + unsigned int DMI_CH1_BUFFER_ID : 2; + unsigned int : 6; + unsigned int DMI_CH2_BUFFER_ID : 2; + unsigned int : 6; + unsigned int DMI_CH3_BUFFER_ID : 2; + unsigned int : 6; + unsigned int DMI_CH4_BUFFER_ID : 2; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int DMI_CH4_BUFFER_ID : 2; + unsigned int : 6; + unsigned int DMI_CH3_BUFFER_ID : 2; + unsigned int : 6; + unsigned int DMI_CH2_BUFFER_ID : 2; + unsigned int : 6; + unsigned int DMI_CH1_BUFFER_ID : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_RTL_RELEASE { + struct { +#if defined(qLittleEndian) + unsigned int CHANGELIST : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CHANGELIST : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PATCH_RELEASE { + struct { +#if defined(qLittleEndian) + unsigned int PATCH_REVISION : 16; + unsigned int PATCH_SELECTION : 8; + unsigned int CUSTOMER_ID : 8; +#else /* !defined(qLittleEndian) */ + unsigned int CUSTOMER_ID : 8; + unsigned int PATCH_SELECTION : 8; + unsigned int PATCH_REVISION : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_AUXILIARY_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERIPHID0 { + struct { +#if defined(qLittleEndian) + unsigned int PARTNUMBER0 : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PARTNUMBER0 : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERIPHID1 { + struct { +#if defined(qLittleEndian) + unsigned int PARTNUMBER1 : 4; + unsigned int DESIGNER0 : 4; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int DESIGNER0 : 4; + unsigned int PARTNUMBER1 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERIPHID2 { + struct { +#if defined(qLittleEndian) + unsigned int DESIGNER1 : 4; + unsigned int REVISION : 4; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int REVISION : 4; + unsigned int DESIGNER1 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERIPHID3 { + struct { +#if defined(qLittleEndian) + unsigned int RBBM_HOST_INTERFACE : 2; + unsigned int GARB_SLAVE_INTERFACE : 2; + unsigned int MH_INTERFACE : 2; + unsigned int : 1; + unsigned int CONTINUATION : 1; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int CONTINUATION : 1; + unsigned int : 1; + unsigned int MH_INTERFACE : 2; + unsigned int GARB_SLAVE_INTERFACE : 2; + unsigned int RBBM_HOST_INTERFACE : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int READ_TIMEOUT : 8; + unsigned int REGCLK_DEASSERT_TIME : 9; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int REGCLK_DEASSERT_TIME : 9; + unsigned int READ_TIMEOUT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_SKEW_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int SKEW_TOP_THRESHOLD : 5; + unsigned int SKEW_COUNT : 5; + unsigned int : 22; +#else /* !defined(qLittleEndian) */ + unsigned int : 22; + unsigned int SKEW_COUNT : 5; + unsigned int SKEW_TOP_THRESHOLD : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_SOFT_RESET { + struct { +#if defined(qLittleEndian) + unsigned int SOFT_RESET_CP : 1; + unsigned int : 1; + unsigned int SOFT_RESET_PA : 1; + unsigned int SOFT_RESET_MH : 1; + unsigned int SOFT_RESET_BC : 1; + unsigned int SOFT_RESET_SQ : 1; + unsigned int SOFT_RESET_SX : 1; + unsigned int : 5; + unsigned int SOFT_RESET_CIB : 1; + unsigned int : 2; + unsigned int SOFT_RESET_SC : 1; + unsigned int SOFT_RESET_VGT : 1; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int SOFT_RESET_VGT : 1; + unsigned int SOFT_RESET_SC : 1; + unsigned int : 2; + unsigned int SOFT_RESET_CIB : 1; + unsigned int : 5; + unsigned int SOFT_RESET_SX : 1; + unsigned int SOFT_RESET_SQ : 1; + unsigned int SOFT_RESET_BC : 1; + unsigned int SOFT_RESET_MH : 1; + unsigned int SOFT_RESET_PA : 1; + unsigned int : 1; + unsigned int SOFT_RESET_CP : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PM_OVERRIDE1 { + struct { +#if defined(qLittleEndian) + unsigned int RBBM_AHBCLK_PM_OVERRIDE : 1; + unsigned int SC_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SC_SCLK_PM_OVERRIDE : 1; + unsigned int SP_TOP_SCLK_PM_OVERRIDE : 1; + unsigned int SP_V0_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_REG_FIFOS_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_CONST_MEM_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_SQ_SCLK_PM_OVERRIDE : 1; + unsigned int SX_SCLK_PM_OVERRIDE : 1; + unsigned int SX_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCO_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCM_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCD_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TPC_TPC_SCLK_PM_OVERRIDE : 1; + unsigned int TPC_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCA_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCB_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCB_READ_SCLK_PM_OVERRIDE : 1; + unsigned int TP_TP_SCLK_PM_OVERRIDE : 1; + unsigned int TP_REG_SCLK_PM_OVERRIDE : 1; + unsigned int CP_G_SCLK_PM_OVERRIDE : 1; + unsigned int CP_REG_SCLK_PM_OVERRIDE : 1; + unsigned int CP_G_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SPI_SCLK_PM_OVERRIDE : 1; + unsigned int RB_REG_SCLK_PM_OVERRIDE : 1; + unsigned int RB_SCLK_PM_OVERRIDE : 1; + unsigned int MH_MH_SCLK_PM_OVERRIDE : 1; + unsigned int MH_REG_SCLK_PM_OVERRIDE : 1; + unsigned int MH_MMU_SCLK_PM_OVERRIDE : 1; + unsigned int MH_TCROQ_SCLK_PM_OVERRIDE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int MH_TCROQ_SCLK_PM_OVERRIDE : 1; + unsigned int MH_MMU_SCLK_PM_OVERRIDE : 1; + unsigned int MH_REG_SCLK_PM_OVERRIDE : 1; + unsigned int MH_MH_SCLK_PM_OVERRIDE : 1; + unsigned int RB_SCLK_PM_OVERRIDE : 1; + unsigned int RB_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SPI_SCLK_PM_OVERRIDE : 1; + unsigned int CP_G_REG_SCLK_PM_OVERRIDE : 1; + unsigned int CP_REG_SCLK_PM_OVERRIDE : 1; + unsigned int CP_G_SCLK_PM_OVERRIDE : 1; + unsigned int TP_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TP_TP_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCB_READ_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCB_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCA_SCLK_PM_OVERRIDE : 1; + unsigned int TPC_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TPC_TPC_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCD_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCM_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCO_SCLK_PM_OVERRIDE : 1; + unsigned int SX_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SX_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_SQ_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_CONST_MEM_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_REG_FIFOS_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SP_V0_SCLK_PM_OVERRIDE : 1; + unsigned int SP_TOP_SCLK_PM_OVERRIDE : 1; + unsigned int SC_SCLK_PM_OVERRIDE : 1; + unsigned int SC_REG_SCLK_PM_OVERRIDE : 1; + unsigned int RBBM_AHBCLK_PM_OVERRIDE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PM_OVERRIDE2 { + struct { +#if defined(qLittleEndian) + unsigned int PA_REG_SCLK_PM_OVERRIDE : 1; + unsigned int PA_PA_SCLK_PM_OVERRIDE : 1; + unsigned int PA_AG_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_REG_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_FIFOS_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_VGT_SCLK_PM_OVERRIDE : 1; + unsigned int DEBUG_PERF_SCLK_PM_OVERRIDE : 1; + unsigned int PERM_SCLK_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM0_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM1_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM2_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM3_PM_OVERRIDE : 1; + unsigned int : 20; +#else /* !defined(qLittleEndian) */ + unsigned int : 20; + unsigned int GC_GA_GMEM3_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM2_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM1_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM0_PM_OVERRIDE : 1; + unsigned int PERM_SCLK_PM_OVERRIDE : 1; + unsigned int DEBUG_PERF_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_VGT_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_FIFOS_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_REG_SCLK_PM_OVERRIDE : 1; + unsigned int PA_AG_SCLK_PM_OVERRIDE : 1; + unsigned int PA_PA_SCLK_PM_OVERRIDE : 1; + unsigned int PA_REG_SCLK_PM_OVERRIDE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union GC_SYS_IDLE { + struct { +#if defined(qLittleEndian) + unsigned int GC_SYS_IDLE_DELAY : 16; + unsigned int GC_SYS_WAIT_DMI_MASK : 6; + unsigned int : 2; + unsigned int GC_SYS_URGENT_RAMP : 1; + unsigned int GC_SYS_WAIT_DMI : 1; + unsigned int : 3; + unsigned int GC_SYS_URGENT_RAMP_OVERRIDE : 1; + unsigned int GC_SYS_WAIT_DMI_OVERRIDE : 1; + unsigned int GC_SYS_IDLE_OVERRIDE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int GC_SYS_IDLE_OVERRIDE : 1; + unsigned int GC_SYS_WAIT_DMI_OVERRIDE : 1; + unsigned int GC_SYS_URGENT_RAMP_OVERRIDE : 1; + unsigned int : 3; + unsigned int GC_SYS_WAIT_DMI : 1; + unsigned int GC_SYS_URGENT_RAMP : 1; + unsigned int : 2; + unsigned int GC_SYS_WAIT_DMI_MASK : 6; + unsigned int GC_SYS_IDLE_DELAY : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union NQWAIT_UNTIL { + struct { +#if defined(qLittleEndian) + unsigned int WAIT_GUI_IDLE : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int WAIT_GUI_IDLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_DEBUG_OUT { + struct { +#if defined(qLittleEndian) + unsigned int DEBUG_BUS_OUT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DEBUG_BUS_OUT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_DEBUG_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int SUB_BLOCK_ADDR : 6; + unsigned int : 2; + unsigned int SUB_BLOCK_SEL : 4; + unsigned int SW_ENABLE : 1; + unsigned int : 3; + unsigned int GPIO_SUB_BLOCK_ADDR : 6; + unsigned int : 2; + unsigned int GPIO_SUB_BLOCK_SEL : 4; + unsigned int GPIO_BYTE_LANE_ENB : 4; +#else /* !defined(qLittleEndian) */ + unsigned int GPIO_BYTE_LANE_ENB : 4; + unsigned int GPIO_SUB_BLOCK_SEL : 4; + unsigned int : 2; + unsigned int GPIO_SUB_BLOCK_ADDR : 6; + unsigned int : 3; + unsigned int SW_ENABLE : 1; + unsigned int SUB_BLOCK_SEL : 4; + unsigned int : 2; + unsigned int SUB_BLOCK_ADDR : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 1; + unsigned int IGNORE_RTR : 1; + unsigned int IGNORE_CP_SCHED_WU : 1; + unsigned int IGNORE_CP_SCHED_ISYNC : 1; + unsigned int IGNORE_CP_SCHED_NQ_HI : 1; + unsigned int : 3; + unsigned int HYSTERESIS_NRT_GUI_ACTIVE : 4; + unsigned int : 4; + unsigned int IGNORE_RTR_FOR_HI : 1; + unsigned int IGNORE_CP_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_VGT_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_SQ_RBBM_NRTRTR_FOR_HI : 1; + unsigned int CP_RBBM_NRTRTR : 1; + unsigned int VGT_RBBM_NRTRTR : 1; + unsigned int SQ_RBBM_NRTRTR : 1; + unsigned int CLIENTS_FOR_NRT_RTR_FOR_HI : 1; + unsigned int CLIENTS_FOR_NRT_RTR : 1; + unsigned int : 6; + unsigned int IGNORE_SX_RBBM_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int IGNORE_SX_RBBM_BUSY : 1; + unsigned int : 6; + unsigned int CLIENTS_FOR_NRT_RTR : 1; + unsigned int CLIENTS_FOR_NRT_RTR_FOR_HI : 1; + unsigned int SQ_RBBM_NRTRTR : 1; + unsigned int VGT_RBBM_NRTRTR : 1; + unsigned int CP_RBBM_NRTRTR : 1; + unsigned int IGNORE_SQ_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_VGT_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_CP_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_RTR_FOR_HI : 1; + unsigned int : 4; + unsigned int HYSTERESIS_NRT_GUI_ACTIVE : 4; + unsigned int : 3; + unsigned int IGNORE_CP_SCHED_NQ_HI : 1; + unsigned int IGNORE_CP_SCHED_ISYNC : 1; + unsigned int IGNORE_CP_SCHED_WU : 1; + unsigned int IGNORE_RTR : 1; + unsigned int : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_READ_ERROR { + struct { +#if defined(qLittleEndian) + unsigned int : 2; + unsigned int READ_ADDRESS : 15; + unsigned int : 13; + unsigned int READ_REQUESTER : 1; + unsigned int READ_ERROR : 1; +#else /* !defined(qLittleEndian) */ + unsigned int READ_ERROR : 1; + unsigned int READ_REQUESTER : 1; + unsigned int : 13; + unsigned int READ_ADDRESS : 15; + unsigned int : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_WAIT_IDLE_CLOCKS { + struct { +#if defined(qLittleEndian) + unsigned int WAIT_IDLE_CLOCKS_NRT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int WAIT_IDLE_CLOCKS_NRT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_INT_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int RDERR_INT_MASK : 1; + unsigned int DISPLAY_UPDATE_INT_MASK : 1; + unsigned int : 17; + unsigned int GUI_IDLE_INT_MASK : 1; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int GUI_IDLE_INT_MASK : 1; + unsigned int : 17; + unsigned int DISPLAY_UPDATE_INT_MASK : 1; + unsigned int RDERR_INT_MASK : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_INT_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int RDERR_INT_STAT : 1; + unsigned int DISPLAY_UPDATE_INT_STAT : 1; + unsigned int : 17; + unsigned int GUI_IDLE_INT_STAT : 1; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int GUI_IDLE_INT_STAT : 1; + unsigned int : 17; + unsigned int DISPLAY_UPDATE_INT_STAT : 1; + unsigned int RDERR_INT_STAT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_INT_ACK { + struct { +#if defined(qLittleEndian) + unsigned int RDERR_INT_ACK : 1; + unsigned int DISPLAY_UPDATE_INT_ACK : 1; + unsigned int : 17; + unsigned int GUI_IDLE_INT_ACK : 1; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int GUI_IDLE_INT_ACK : 1; + unsigned int : 17; + unsigned int DISPLAY_UPDATE_INT_ACK : 1; + unsigned int RDERR_INT_ACK : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MASTER_INT_SIGNAL { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int MH_INT_STAT : 1; + unsigned int : 20; + unsigned int SQ_INT_STAT : 1; + unsigned int : 3; + unsigned int CP_INT_STAT : 1; + unsigned int RBBM_INT_STAT : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RBBM_INT_STAT : 1; + unsigned int CP_INT_STAT : 1; + unsigned int : 3; + unsigned int SQ_INT_STAT : 1; + unsigned int : 20; + unsigned int MH_INT_STAT : 1; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT1_SEL : 6; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int PERF_COUNT1_SEL : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERFCOUNTER1_LO { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT1_LO : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT1_LO : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT1_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT1_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int RB_BASE : 27; +#else /* !defined(qLittleEndian) */ + unsigned int RB_BASE : 27; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int RB_BUFSZ : 6; + unsigned int : 2; + unsigned int RB_BLKSZ : 6; + unsigned int : 2; + unsigned int BUF_SWAP : 2; + unsigned int : 2; + unsigned int RB_POLL_EN : 1; + unsigned int : 6; + unsigned int RB_NO_UPDATE : 1; + unsigned int : 3; + unsigned int RB_RPTR_WR_ENA : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RB_RPTR_WR_ENA : 1; + unsigned int : 3; + unsigned int RB_NO_UPDATE : 1; + unsigned int : 6; + unsigned int RB_POLL_EN : 1; + unsigned int : 2; + unsigned int BUF_SWAP : 2; + unsigned int : 2; + unsigned int RB_BLKSZ : 6; + unsigned int : 2; + unsigned int RB_BUFSZ : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_RPTR_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int RB_RPTR_SWAP : 2; + unsigned int RB_RPTR_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int RB_RPTR_ADDR : 30; + unsigned int RB_RPTR_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_RPTR { + struct { +#if defined(qLittleEndian) + unsigned int RB_RPTR : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int RB_RPTR : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_RPTR_WR { + struct { +#if defined(qLittleEndian) + unsigned int RB_RPTR_WR : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int RB_RPTR_WR : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_WPTR { + struct { +#if defined(qLittleEndian) + unsigned int RB_WPTR : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int RB_WPTR : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_WPTR_DELAY { + struct { +#if defined(qLittleEndian) + unsigned int PRE_WRITE_TIMER : 28; + unsigned int PRE_WRITE_LIMIT : 4; +#else /* !defined(qLittleEndian) */ + unsigned int PRE_WRITE_LIMIT : 4; + unsigned int PRE_WRITE_TIMER : 28; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_WPTR_BASE { + struct { +#if defined(qLittleEndian) + unsigned int RB_WPTR_SWAP : 2; + unsigned int RB_WPTR_BASE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int RB_WPTR_BASE : 30; + unsigned int RB_WPTR_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_IB1_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 2; + unsigned int IB1_BASE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int IB1_BASE : 30; + unsigned int : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_IB1_BUFSZ { + struct { +#if defined(qLittleEndian) + unsigned int IB1_BUFSZ : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int IB1_BUFSZ : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_IB2_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 2; + unsigned int IB2_BASE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int IB2_BASE : 30; + unsigned int : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_IB2_BUFSZ { + struct { +#if defined(qLittleEndian) + unsigned int IB2_BUFSZ : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int IB2_BUFSZ : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ST_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 2; + unsigned int ST_BASE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int ST_BASE : 30; + unsigned int : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ST_BUFSZ { + struct { +#if defined(qLittleEndian) + unsigned int ST_BUFSZ : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int ST_BUFSZ : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_QUEUE_THRESHOLDS { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_IB1_START : 4; + unsigned int : 4; + unsigned int CSQ_IB2_START : 4; + unsigned int : 4; + unsigned int CSQ_ST_START : 4; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int CSQ_ST_START : 4; + unsigned int : 4; + unsigned int CSQ_IB2_START : 4; + unsigned int : 4; + unsigned int CSQ_IB1_START : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_MEQ_THRESHOLDS { + struct { +#if defined(qLittleEndian) + unsigned int : 16; + unsigned int MEQ_END : 5; + unsigned int : 3; + unsigned int ROQ_END : 5; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int ROQ_END : 5; + unsigned int : 3; + unsigned int MEQ_END : 5; + unsigned int : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CSQ_AVAIL { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_CNT_RING : 7; + unsigned int : 1; + unsigned int CSQ_CNT_IB1 : 7; + unsigned int : 1; + unsigned int CSQ_CNT_IB2 : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int CSQ_CNT_IB2 : 7; + unsigned int : 1; + unsigned int CSQ_CNT_IB1 : 7; + unsigned int : 1; + unsigned int CSQ_CNT_RING : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STQ_AVAIL { + struct { +#if defined(qLittleEndian) + unsigned int STQ_CNT_ST : 7; + unsigned int : 25; +#else /* !defined(qLittleEndian) */ + unsigned int : 25; + unsigned int STQ_CNT_ST : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_MEQ_AVAIL { + struct { +#if defined(qLittleEndian) + unsigned int MEQ_CNT : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int MEQ_CNT : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CSQ_RB_STAT { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_RPTR_PRIMARY : 7; + unsigned int : 9; + unsigned int CSQ_WPTR_PRIMARY : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int CSQ_WPTR_PRIMARY : 7; + unsigned int : 9; + unsigned int CSQ_RPTR_PRIMARY : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CSQ_IB1_STAT { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_RPTR_INDIRECT1 : 7; + unsigned int : 9; + unsigned int CSQ_WPTR_INDIRECT1 : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int CSQ_WPTR_INDIRECT1 : 7; + unsigned int : 9; + unsigned int CSQ_RPTR_INDIRECT1 : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CSQ_IB2_STAT { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_RPTR_INDIRECT2 : 7; + unsigned int : 9; + unsigned int CSQ_WPTR_INDIRECT2 : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int CSQ_WPTR_INDIRECT2 : 7; + unsigned int : 9; + unsigned int CSQ_RPTR_INDIRECT2 : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NON_PREFETCH_CNTRS { + struct { +#if defined(qLittleEndian) + unsigned int IB1_COUNTER : 3; + unsigned int : 5; + unsigned int IB2_COUNTER : 3; + unsigned int : 21; +#else /* !defined(qLittleEndian) */ + unsigned int : 21; + unsigned int IB2_COUNTER : 3; + unsigned int : 5; + unsigned int IB1_COUNTER : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STQ_ST_STAT { + struct { +#if defined(qLittleEndian) + unsigned int STQ_RPTR_ST : 7; + unsigned int : 9; + unsigned int STQ_WPTR_ST : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int STQ_WPTR_ST : 7; + unsigned int : 9; + unsigned int STQ_RPTR_ST : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_MEQ_STAT { + struct { +#if defined(qLittleEndian) + unsigned int MEQ_RPTR : 10; + unsigned int : 6; + unsigned int MEQ_WPTR : 10; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int MEQ_WPTR : 10; + unsigned int : 6; + unsigned int MEQ_RPTR : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_MIU_TAG_STAT { + struct { +#if defined(qLittleEndian) + unsigned int TAG_0_STAT : 1; + unsigned int TAG_1_STAT : 1; + unsigned int TAG_2_STAT : 1; + unsigned int TAG_3_STAT : 1; + unsigned int TAG_4_STAT : 1; + unsigned int TAG_5_STAT : 1; + unsigned int TAG_6_STAT : 1; + unsigned int TAG_7_STAT : 1; + unsigned int TAG_8_STAT : 1; + unsigned int TAG_9_STAT : 1; + unsigned int TAG_10_STAT : 1; + unsigned int TAG_11_STAT : 1; + unsigned int TAG_12_STAT : 1; + unsigned int TAG_13_STAT : 1; + unsigned int TAG_14_STAT : 1; + unsigned int TAG_15_STAT : 1; + unsigned int TAG_16_STAT : 1; + unsigned int TAG_17_STAT : 1; + unsigned int : 13; + unsigned int INVALID_RETURN_TAG : 1; +#else /* !defined(qLittleEndian) */ + unsigned int INVALID_RETURN_TAG : 1; + unsigned int : 13; + unsigned int TAG_17_STAT : 1; + unsigned int TAG_16_STAT : 1; + unsigned int TAG_15_STAT : 1; + unsigned int TAG_14_STAT : 1; + unsigned int TAG_13_STAT : 1; + unsigned int TAG_12_STAT : 1; + unsigned int TAG_11_STAT : 1; + unsigned int TAG_10_STAT : 1; + unsigned int TAG_9_STAT : 1; + unsigned int TAG_8_STAT : 1; + unsigned int TAG_7_STAT : 1; + unsigned int TAG_6_STAT : 1; + unsigned int TAG_5_STAT : 1; + unsigned int TAG_4_STAT : 1; + unsigned int TAG_3_STAT : 1; + unsigned int TAG_2_STAT : 1; + unsigned int TAG_1_STAT : 1; + unsigned int TAG_0_STAT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CMD_INDEX { + struct { +#if defined(qLittleEndian) + unsigned int CMD_INDEX : 7; + unsigned int : 9; + unsigned int CMD_QUEUE_SEL : 2; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int CMD_QUEUE_SEL : 2; + unsigned int : 9; + unsigned int CMD_INDEX : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CMD_DATA { + struct { +#if defined(qLittleEndian) + unsigned int CMD_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CMD_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int ME_STATMUX : 16; + unsigned int : 9; + unsigned int VTX_DEALLOC_FIFO_EMPTY : 1; + unsigned int PIX_DEALLOC_FIFO_EMPTY : 1; + unsigned int : 1; + unsigned int ME_HALT : 1; + unsigned int ME_BUSY : 1; + unsigned int : 1; + unsigned int PROG_CNT_SIZE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PROG_CNT_SIZE : 1; + unsigned int : 1; + unsigned int ME_BUSY : 1; + unsigned int ME_HALT : 1; + unsigned int : 1; + unsigned int PIX_DEALLOC_FIFO_EMPTY : 1; + unsigned int VTX_DEALLOC_FIFO_EMPTY : 1; + unsigned int : 9; + unsigned int ME_STATMUX : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int ME_DEBUG_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ME_DEBUG_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_RAM_WADDR { + struct { +#if defined(qLittleEndian) + unsigned int ME_RAM_WADDR : 10; + unsigned int : 22; +#else /* !defined(qLittleEndian) */ + unsigned int : 22; + unsigned int ME_RAM_WADDR : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_RAM_RADDR { + struct { +#if defined(qLittleEndian) + unsigned int ME_RAM_RADDR : 10; + unsigned int : 22; +#else /* !defined(qLittleEndian) */ + unsigned int : 22; + unsigned int ME_RAM_RADDR : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_RAM_DATA { + struct { +#if defined(qLittleEndian) + unsigned int ME_RAM_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ME_RAM_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_RDADDR { + struct { +#if defined(qLittleEndian) + unsigned int ME_RDADDR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ME_RDADDR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int CP_DEBUG_UNUSED_22_to_0 : 23; + unsigned int PREDICATE_DISABLE : 1; + unsigned int PROG_END_PTR_ENABLE : 1; + unsigned int MIU_128BIT_WRITE_ENABLE : 1; + unsigned int PREFETCH_PASS_NOPS : 1; + unsigned int DYNAMIC_CLK_DISABLE : 1; + unsigned int PREFETCH_MATCH_DISABLE : 1; + unsigned int : 1; + unsigned int SIMPLE_ME_FLOW_CONTROL : 1; + unsigned int MIU_WRITE_PACK_DISABLE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int MIU_WRITE_PACK_DISABLE : 1; + unsigned int SIMPLE_ME_FLOW_CONTROL : 1; + unsigned int : 1; + unsigned int PREFETCH_MATCH_DISABLE : 1; + unsigned int DYNAMIC_CLK_DISABLE : 1; + unsigned int PREFETCH_PASS_NOPS : 1; + unsigned int MIU_128BIT_WRITE_ENABLE : 1; + unsigned int PROG_END_PTR_ENABLE : 1; + unsigned int PREDICATE_DISABLE : 1; + unsigned int CP_DEBUG_UNUSED_22_to_0 : 23; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG0 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG1 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG1 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG1 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG2 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG2 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG2 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG3 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG3 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG3 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG4 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG4 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG4 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG5 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG5 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG5 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG6 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG6 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG6 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG7 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG7 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG7 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_UMSK { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_UMSK : 8; + unsigned int : 8; + unsigned int SCRATCH_SWAP : 2; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int SCRATCH_SWAP : 2; + unsigned int : 8; + unsigned int SCRATCH_UMSK : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int SCRATCH_ADDR : 27; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_ADDR : 27; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_SRC { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_SWM : 1; + unsigned int VS_DONE_CNTR : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int VS_DONE_CNTR : 1; + unsigned int VS_DONE_SWM : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_SWAP : 2; + unsigned int VS_DONE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int VS_DONE_ADDR : 30; + unsigned int VS_DONE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_DATA { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_DONE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_ADDR_SWM { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_SWAP_SWM : 2; + unsigned int VS_DONE_ADDR_SWM : 30; +#else /* !defined(qLittleEndian) */ + unsigned int VS_DONE_ADDR_SWM : 30; + unsigned int VS_DONE_SWAP_SWM : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_DATA_SWM { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_DATA_SWM : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_DONE_DATA_SWM : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_SRC { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_SWM : 1; + unsigned int PS_DONE_CNTR : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int PS_DONE_CNTR : 1; + unsigned int PS_DONE_SWM : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_SWAP : 2; + unsigned int PS_DONE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int PS_DONE_ADDR : 30; + unsigned int PS_DONE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_DATA { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PS_DONE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_ADDR_SWM { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_SWAP_SWM : 2; + unsigned int PS_DONE_ADDR_SWM : 30; +#else /* !defined(qLittleEndian) */ + unsigned int PS_DONE_ADDR_SWM : 30; + unsigned int PS_DONE_SWAP_SWM : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_DATA_SWM { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_DATA_SWM : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PS_DONE_DATA_SWM : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_CF_EVENT_SRC { + struct { +#if defined(qLittleEndian) + unsigned int CF_DONE_SRC : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int CF_DONE_SRC : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_CF_EVENT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int CF_DONE_SWAP : 2; + unsigned int CF_DONE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int CF_DONE_ADDR : 30; + unsigned int CF_DONE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_CF_EVENT_DATA { + struct { +#if defined(qLittleEndian) + unsigned int CF_DONE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CF_DONE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_NRT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int NRT_WRITE_SWAP : 2; + unsigned int NRT_WRITE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int NRT_WRITE_ADDR : 30; + unsigned int NRT_WRITE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_NRT_DATA { + struct { +#if defined(qLittleEndian) + unsigned int NRT_WRITE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int NRT_WRITE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_FETCH_DONE_SRC { + struct { +#if defined(qLittleEndian) + unsigned int VS_FETCH_DONE_CNTR : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int VS_FETCH_DONE_CNTR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_FETCH_DONE_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int VS_FETCH_DONE_SWAP : 2; + unsigned int VS_FETCH_DONE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int VS_FETCH_DONE_ADDR : 30; + unsigned int VS_FETCH_DONE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_FETCH_DONE_DATA { + struct { +#if defined(qLittleEndian) + unsigned int VS_FETCH_DONE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_FETCH_DONE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_INT_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int : 19; + unsigned int SW_INT_MASK : 1; + unsigned int : 3; + unsigned int T0_PACKET_IN_IB_MASK : 1; + unsigned int OPCODE_ERROR_MASK : 1; + unsigned int PROTECTED_MODE_ERROR_MASK : 1; + unsigned int RESERVED_BIT_ERROR_MASK : 1; + unsigned int IB_ERROR_MASK : 1; + unsigned int : 1; + unsigned int IB2_INT_MASK : 1; + unsigned int IB1_INT_MASK : 1; + unsigned int RB_INT_MASK : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RB_INT_MASK : 1; + unsigned int IB1_INT_MASK : 1; + unsigned int IB2_INT_MASK : 1; + unsigned int : 1; + unsigned int IB_ERROR_MASK : 1; + unsigned int RESERVED_BIT_ERROR_MASK : 1; + unsigned int PROTECTED_MODE_ERROR_MASK : 1; + unsigned int OPCODE_ERROR_MASK : 1; + unsigned int T0_PACKET_IN_IB_MASK : 1; + unsigned int : 3; + unsigned int SW_INT_MASK : 1; + unsigned int : 19; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_INT_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int : 19; + unsigned int SW_INT_STAT : 1; + unsigned int : 3; + unsigned int T0_PACKET_IN_IB_STAT : 1; + unsigned int OPCODE_ERROR_STAT : 1; + unsigned int PROTECTED_MODE_ERROR_STAT : 1; + unsigned int RESERVED_BIT_ERROR_STAT : 1; + unsigned int IB_ERROR_STAT : 1; + unsigned int : 1; + unsigned int IB2_INT_STAT : 1; + unsigned int IB1_INT_STAT : 1; + unsigned int RB_INT_STAT : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RB_INT_STAT : 1; + unsigned int IB1_INT_STAT : 1; + unsigned int IB2_INT_STAT : 1; + unsigned int : 1; + unsigned int IB_ERROR_STAT : 1; + unsigned int RESERVED_BIT_ERROR_STAT : 1; + unsigned int PROTECTED_MODE_ERROR_STAT : 1; + unsigned int OPCODE_ERROR_STAT : 1; + unsigned int T0_PACKET_IN_IB_STAT : 1; + unsigned int : 3; + unsigned int SW_INT_STAT : 1; + unsigned int : 19; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_INT_ACK { + struct { +#if defined(qLittleEndian) + unsigned int : 19; + unsigned int SW_INT_ACK : 1; + unsigned int : 3; + unsigned int T0_PACKET_IN_IB_ACK : 1; + unsigned int OPCODE_ERROR_ACK : 1; + unsigned int PROTECTED_MODE_ERROR_ACK : 1; + unsigned int RESERVED_BIT_ERROR_ACK : 1; + unsigned int IB_ERROR_ACK : 1; + unsigned int : 1; + unsigned int IB2_INT_ACK : 1; + unsigned int IB1_INT_ACK : 1; + unsigned int RB_INT_ACK : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RB_INT_ACK : 1; + unsigned int IB1_INT_ACK : 1; + unsigned int IB2_INT_ACK : 1; + unsigned int : 1; + unsigned int IB_ERROR_ACK : 1; + unsigned int RESERVED_BIT_ERROR_ACK : 1; + unsigned int PROTECTED_MODE_ERROR_ACK : 1; + unsigned int OPCODE_ERROR_ACK : 1; + unsigned int T0_PACKET_IN_IB_ACK : 1; + unsigned int : 3; + unsigned int SW_INT_ACK : 1; + unsigned int : 19; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PFP_UCODE_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int UCODE_ADDR : 9; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int UCODE_ADDR : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PFP_UCODE_DATA { + struct { +#if defined(qLittleEndian) + unsigned int UCODE_DATA : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int UCODE_DATA : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PERFMON_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int PERFMON_STATE : 4; + unsigned int : 4; + unsigned int PERFMON_ENABLE_MODE : 2; + unsigned int : 22; +#else /* !defined(qLittleEndian) */ + unsigned int : 22; + unsigned int PERFMON_ENABLE_MODE : 2; + unsigned int : 4; + unsigned int PERFMON_STATE : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PERFCOUNTER_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNT_SEL : 6; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int PERFCOUNT_SEL : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PERFCOUNTER_LO { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNT_LO : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNT_LO : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PERFCOUNTER_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNT_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNT_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_BIN_MASK_LO { + struct { +#if defined(qLittleEndian) + unsigned int BIN_MASK_LO : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_MASK_LO : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_BIN_MASK_HI { + struct { +#if defined(qLittleEndian) + unsigned int BIN_MASK_HI : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_MASK_HI : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_BIN_SELECT_LO { + struct { +#if defined(qLittleEndian) + unsigned int BIN_SELECT_LO : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_SELECT_LO : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_BIN_SELECT_HI { + struct { +#if defined(qLittleEndian) + unsigned int BIN_SELECT_HI : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_SELECT_HI : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NV_FLAGS_0 { + struct { +#if defined(qLittleEndian) + unsigned int DISCARD_0 : 1; + unsigned int END_RCVD_0 : 1; + unsigned int DISCARD_1 : 1; + unsigned int END_RCVD_1 : 1; + unsigned int DISCARD_2 : 1; + unsigned int END_RCVD_2 : 1; + unsigned int DISCARD_3 : 1; + unsigned int END_RCVD_3 : 1; + unsigned int DISCARD_4 : 1; + unsigned int END_RCVD_4 : 1; + unsigned int DISCARD_5 : 1; + unsigned int END_RCVD_5 : 1; + unsigned int DISCARD_6 : 1; + unsigned int END_RCVD_6 : 1; + unsigned int DISCARD_7 : 1; + unsigned int END_RCVD_7 : 1; + unsigned int DISCARD_8 : 1; + unsigned int END_RCVD_8 : 1; + unsigned int DISCARD_9 : 1; + unsigned int END_RCVD_9 : 1; + unsigned int DISCARD_10 : 1; + unsigned int END_RCVD_10 : 1; + unsigned int DISCARD_11 : 1; + unsigned int END_RCVD_11 : 1; + unsigned int DISCARD_12 : 1; + unsigned int END_RCVD_12 : 1; + unsigned int DISCARD_13 : 1; + unsigned int END_RCVD_13 : 1; + unsigned int DISCARD_14 : 1; + unsigned int END_RCVD_14 : 1; + unsigned int DISCARD_15 : 1; + unsigned int END_RCVD_15 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int END_RCVD_15 : 1; + unsigned int DISCARD_15 : 1; + unsigned int END_RCVD_14 : 1; + unsigned int DISCARD_14 : 1; + unsigned int END_RCVD_13 : 1; + unsigned int DISCARD_13 : 1; + unsigned int END_RCVD_12 : 1; + unsigned int DISCARD_12 : 1; + unsigned int END_RCVD_11 : 1; + unsigned int DISCARD_11 : 1; + unsigned int END_RCVD_10 : 1; + unsigned int DISCARD_10 : 1; + unsigned int END_RCVD_9 : 1; + unsigned int DISCARD_9 : 1; + unsigned int END_RCVD_8 : 1; + unsigned int DISCARD_8 : 1; + unsigned int END_RCVD_7 : 1; + unsigned int DISCARD_7 : 1; + unsigned int END_RCVD_6 : 1; + unsigned int DISCARD_6 : 1; + unsigned int END_RCVD_5 : 1; + unsigned int DISCARD_5 : 1; + unsigned int END_RCVD_4 : 1; + unsigned int DISCARD_4 : 1; + unsigned int END_RCVD_3 : 1; + unsigned int DISCARD_3 : 1; + unsigned int END_RCVD_2 : 1; + unsigned int DISCARD_2 : 1; + unsigned int END_RCVD_1 : 1; + unsigned int DISCARD_1 : 1; + unsigned int END_RCVD_0 : 1; + unsigned int DISCARD_0 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NV_FLAGS_1 { + struct { +#if defined(qLittleEndian) + unsigned int DISCARD_16 : 1; + unsigned int END_RCVD_16 : 1; + unsigned int DISCARD_17 : 1; + unsigned int END_RCVD_17 : 1; + unsigned int DISCARD_18 : 1; + unsigned int END_RCVD_18 : 1; + unsigned int DISCARD_19 : 1; + unsigned int END_RCVD_19 : 1; + unsigned int DISCARD_20 : 1; + unsigned int END_RCVD_20 : 1; + unsigned int DISCARD_21 : 1; + unsigned int END_RCVD_21 : 1; + unsigned int DISCARD_22 : 1; + unsigned int END_RCVD_22 : 1; + unsigned int DISCARD_23 : 1; + unsigned int END_RCVD_23 : 1; + unsigned int DISCARD_24 : 1; + unsigned int END_RCVD_24 : 1; + unsigned int DISCARD_25 : 1; + unsigned int END_RCVD_25 : 1; + unsigned int DISCARD_26 : 1; + unsigned int END_RCVD_26 : 1; + unsigned int DISCARD_27 : 1; + unsigned int END_RCVD_27 : 1; + unsigned int DISCARD_28 : 1; + unsigned int END_RCVD_28 : 1; + unsigned int DISCARD_29 : 1; + unsigned int END_RCVD_29 : 1; + unsigned int DISCARD_30 : 1; + unsigned int END_RCVD_30 : 1; + unsigned int DISCARD_31 : 1; + unsigned int END_RCVD_31 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int END_RCVD_31 : 1; + unsigned int DISCARD_31 : 1; + unsigned int END_RCVD_30 : 1; + unsigned int DISCARD_30 : 1; + unsigned int END_RCVD_29 : 1; + unsigned int DISCARD_29 : 1; + unsigned int END_RCVD_28 : 1; + unsigned int DISCARD_28 : 1; + unsigned int END_RCVD_27 : 1; + unsigned int DISCARD_27 : 1; + unsigned int END_RCVD_26 : 1; + unsigned int DISCARD_26 : 1; + unsigned int END_RCVD_25 : 1; + unsigned int DISCARD_25 : 1; + unsigned int END_RCVD_24 : 1; + unsigned int DISCARD_24 : 1; + unsigned int END_RCVD_23 : 1; + unsigned int DISCARD_23 : 1; + unsigned int END_RCVD_22 : 1; + unsigned int DISCARD_22 : 1; + unsigned int END_RCVD_21 : 1; + unsigned int DISCARD_21 : 1; + unsigned int END_RCVD_20 : 1; + unsigned int DISCARD_20 : 1; + unsigned int END_RCVD_19 : 1; + unsigned int DISCARD_19 : 1; + unsigned int END_RCVD_18 : 1; + unsigned int DISCARD_18 : 1; + unsigned int END_RCVD_17 : 1; + unsigned int DISCARD_17 : 1; + unsigned int END_RCVD_16 : 1; + unsigned int DISCARD_16 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NV_FLAGS_2 { + struct { +#if defined(qLittleEndian) + unsigned int DISCARD_32 : 1; + unsigned int END_RCVD_32 : 1; + unsigned int DISCARD_33 : 1; + unsigned int END_RCVD_33 : 1; + unsigned int DISCARD_34 : 1; + unsigned int END_RCVD_34 : 1; + unsigned int DISCARD_35 : 1; + unsigned int END_RCVD_35 : 1; + unsigned int DISCARD_36 : 1; + unsigned int END_RCVD_36 : 1; + unsigned int DISCARD_37 : 1; + unsigned int END_RCVD_37 : 1; + unsigned int DISCARD_38 : 1; + unsigned int END_RCVD_38 : 1; + unsigned int DISCARD_39 : 1; + unsigned int END_RCVD_39 : 1; + unsigned int DISCARD_40 : 1; + unsigned int END_RCVD_40 : 1; + unsigned int DISCARD_41 : 1; + unsigned int END_RCVD_41 : 1; + unsigned int DISCARD_42 : 1; + unsigned int END_RCVD_42 : 1; + unsigned int DISCARD_43 : 1; + unsigned int END_RCVD_43 : 1; + unsigned int DISCARD_44 : 1; + unsigned int END_RCVD_44 : 1; + unsigned int DISCARD_45 : 1; + unsigned int END_RCVD_45 : 1; + unsigned int DISCARD_46 : 1; + unsigned int END_RCVD_46 : 1; + unsigned int DISCARD_47 : 1; + unsigned int END_RCVD_47 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int END_RCVD_47 : 1; + unsigned int DISCARD_47 : 1; + unsigned int END_RCVD_46 : 1; + unsigned int DISCARD_46 : 1; + unsigned int END_RCVD_45 : 1; + unsigned int DISCARD_45 : 1; + unsigned int END_RCVD_44 : 1; + unsigned int DISCARD_44 : 1; + unsigned int END_RCVD_43 : 1; + unsigned int DISCARD_43 : 1; + unsigned int END_RCVD_42 : 1; + unsigned int DISCARD_42 : 1; + unsigned int END_RCVD_41 : 1; + unsigned int DISCARD_41 : 1; + unsigned int END_RCVD_40 : 1; + unsigned int DISCARD_40 : 1; + unsigned int END_RCVD_39 : 1; + unsigned int DISCARD_39 : 1; + unsigned int END_RCVD_38 : 1; + unsigned int DISCARD_38 : 1; + unsigned int END_RCVD_37 : 1; + unsigned int DISCARD_37 : 1; + unsigned int END_RCVD_36 : 1; + unsigned int DISCARD_36 : 1; + unsigned int END_RCVD_35 : 1; + unsigned int DISCARD_35 : 1; + unsigned int END_RCVD_34 : 1; + unsigned int DISCARD_34 : 1; + unsigned int END_RCVD_33 : 1; + unsigned int DISCARD_33 : 1; + unsigned int END_RCVD_32 : 1; + unsigned int DISCARD_32 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NV_FLAGS_3 { + struct { +#if defined(qLittleEndian) + unsigned int DISCARD_48 : 1; + unsigned int END_RCVD_48 : 1; + unsigned int DISCARD_49 : 1; + unsigned int END_RCVD_49 : 1; + unsigned int DISCARD_50 : 1; + unsigned int END_RCVD_50 : 1; + unsigned int DISCARD_51 : 1; + unsigned int END_RCVD_51 : 1; + unsigned int DISCARD_52 : 1; + unsigned int END_RCVD_52 : 1; + unsigned int DISCARD_53 : 1; + unsigned int END_RCVD_53 : 1; + unsigned int DISCARD_54 : 1; + unsigned int END_RCVD_54 : 1; + unsigned int DISCARD_55 : 1; + unsigned int END_RCVD_55 : 1; + unsigned int DISCARD_56 : 1; + unsigned int END_RCVD_56 : 1; + unsigned int DISCARD_57 : 1; + unsigned int END_RCVD_57 : 1; + unsigned int DISCARD_58 : 1; + unsigned int END_RCVD_58 : 1; + unsigned int DISCARD_59 : 1; + unsigned int END_RCVD_59 : 1; + unsigned int DISCARD_60 : 1; + unsigned int END_RCVD_60 : 1; + unsigned int DISCARD_61 : 1; + unsigned int END_RCVD_61 : 1; + unsigned int DISCARD_62 : 1; + unsigned int END_RCVD_62 : 1; + unsigned int DISCARD_63 : 1; + unsigned int END_RCVD_63 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int END_RCVD_63 : 1; + unsigned int DISCARD_63 : 1; + unsigned int END_RCVD_62 : 1; + unsigned int DISCARD_62 : 1; + unsigned int END_RCVD_61 : 1; + unsigned int DISCARD_61 : 1; + unsigned int END_RCVD_60 : 1; + unsigned int DISCARD_60 : 1; + unsigned int END_RCVD_59 : 1; + unsigned int DISCARD_59 : 1; + unsigned int END_RCVD_58 : 1; + unsigned int DISCARD_58 : 1; + unsigned int END_RCVD_57 : 1; + unsigned int DISCARD_57 : 1; + unsigned int END_RCVD_56 : 1; + unsigned int DISCARD_56 : 1; + unsigned int END_RCVD_55 : 1; + unsigned int DISCARD_55 : 1; + unsigned int END_RCVD_54 : 1; + unsigned int DISCARD_54 : 1; + unsigned int END_RCVD_53 : 1; + unsigned int DISCARD_53 : 1; + unsigned int END_RCVD_52 : 1; + unsigned int DISCARD_52 : 1; + unsigned int END_RCVD_51 : 1; + unsigned int DISCARD_51 : 1; + unsigned int END_RCVD_50 : 1; + unsigned int DISCARD_50 : 1; + unsigned int END_RCVD_49 : 1; + unsigned int DISCARD_49 : 1; + unsigned int END_RCVD_48 : 1; + unsigned int DISCARD_48 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STATE_DEBUG_INDEX { + struct { +#if defined(qLittleEndian) + unsigned int STATE_DEBUG_INDEX : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int STATE_DEBUG_INDEX : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STATE_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int STATE_DEBUG_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int STATE_DEBUG_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PROG_COUNTER { + struct { +#if defined(qLittleEndian) + unsigned int COUNTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int COUNTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STAT { + struct { +#if defined(qLittleEndian) + unsigned int MIU_WR_BUSY : 1; + unsigned int MIU_RD_REQ_BUSY : 1; + unsigned int MIU_RD_RETURN_BUSY : 1; + unsigned int RBIU_BUSY : 1; + unsigned int RCIU_BUSY : 1; + unsigned int CSF_RING_BUSY : 1; + unsigned int CSF_INDIRECTS_BUSY : 1; + unsigned int CSF_INDIRECT2_BUSY : 1; + unsigned int : 1; + unsigned int CSF_ST_BUSY : 1; + unsigned int CSF_BUSY : 1; + unsigned int RING_QUEUE_BUSY : 1; + unsigned int INDIRECTS_QUEUE_BUSY : 1; + unsigned int INDIRECT2_QUEUE_BUSY : 1; + unsigned int : 2; + unsigned int ST_QUEUE_BUSY : 1; + unsigned int PFP_BUSY : 1; + unsigned int MEQ_RING_BUSY : 1; + unsigned int MEQ_INDIRECTS_BUSY : 1; + unsigned int MEQ_INDIRECT2_BUSY : 1; + unsigned int MIU_WC_STALL : 1; + unsigned int CP_NRT_BUSY : 1; + unsigned int _3D_BUSY : 1; + unsigned int : 2; + unsigned int ME_BUSY : 1; + unsigned int : 2; + unsigned int ME_WC_BUSY : 1; + unsigned int MIU_WC_TRACK_FIFO_EMPTY : 1; + unsigned int CP_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int CP_BUSY : 1; + unsigned int MIU_WC_TRACK_FIFO_EMPTY : 1; + unsigned int ME_WC_BUSY : 1; + unsigned int : 2; + unsigned int ME_BUSY : 1; + unsigned int : 2; + unsigned int _3D_BUSY : 1; + unsigned int CP_NRT_BUSY : 1; + unsigned int MIU_WC_STALL : 1; + unsigned int MEQ_INDIRECT2_BUSY : 1; + unsigned int MEQ_INDIRECTS_BUSY : 1; + unsigned int MEQ_RING_BUSY : 1; + unsigned int PFP_BUSY : 1; + unsigned int ST_QUEUE_BUSY : 1; + unsigned int : 2; + unsigned int INDIRECT2_QUEUE_BUSY : 1; + unsigned int INDIRECTS_QUEUE_BUSY : 1; + unsigned int RING_QUEUE_BUSY : 1; + unsigned int CSF_BUSY : 1; + unsigned int CSF_ST_BUSY : 1; + unsigned int : 1; + unsigned int CSF_INDIRECT2_BUSY : 1; + unsigned int CSF_INDIRECTS_BUSY : 1; + unsigned int CSF_RING_BUSY : 1; + unsigned int RCIU_BUSY : 1; + unsigned int RBIU_BUSY : 1; + unsigned int MIU_RD_RETURN_BUSY : 1; + unsigned int MIU_RD_REQ_BUSY : 1; + unsigned int MIU_WR_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_0_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_1_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_2_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_3_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_4_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_5_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_6_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_7_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_8_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_9_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_10_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_11_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_12_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_13_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_14_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_15_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_SIZE_PM4 { + struct { +#if defined(qLittleEndian) + unsigned int SIZE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SIZE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_BASE_PM4 { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BASE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_STATUS_PM4 { + struct { +#if defined(qLittleEndian) + unsigned int MATCHING_CONTEXTS : 8; + unsigned int RB_COPY_DEST_BASE_ENA : 1; + unsigned int DEST_BASE_0_ENA : 1; + unsigned int DEST_BASE_1_ENA : 1; + unsigned int DEST_BASE_2_ENA : 1; + unsigned int DEST_BASE_3_ENA : 1; + unsigned int DEST_BASE_4_ENA : 1; + unsigned int DEST_BASE_5_ENA : 1; + unsigned int DEST_BASE_6_ENA : 1; + unsigned int DEST_BASE_7_ENA : 1; + unsigned int RB_COLOR_INFO_ENA : 1; + unsigned int : 7; + unsigned int TC_ACTION_ENA : 1; + unsigned int : 5; + unsigned int STATUS : 1; +#else /* !defined(qLittleEndian) */ + unsigned int STATUS : 1; + unsigned int : 5; + unsigned int TC_ACTION_ENA : 1; + unsigned int : 7; + unsigned int RB_COLOR_INFO_ENA : 1; + unsigned int DEST_BASE_7_ENA : 1; + unsigned int DEST_BASE_6_ENA : 1; + unsigned int DEST_BASE_5_ENA : 1; + unsigned int DEST_BASE_4_ENA : 1; + unsigned int DEST_BASE_3_ENA : 1; + unsigned int DEST_BASE_2_ENA : 1; + unsigned int DEST_BASE_1_ENA : 1; + unsigned int DEST_BASE_0_ENA : 1; + unsigned int RB_COPY_DEST_BASE_ENA : 1; + unsigned int MATCHING_CONTEXTS : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_SIZE_HOST { + struct { +#if defined(qLittleEndian) + unsigned int SIZE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SIZE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_BASE_HOST { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BASE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_STATUS_HOST { + struct { +#if defined(qLittleEndian) + unsigned int MATCHING_CONTEXTS : 8; + unsigned int RB_COPY_DEST_BASE_ENA : 1; + unsigned int DEST_BASE_0_ENA : 1; + unsigned int DEST_BASE_1_ENA : 1; + unsigned int DEST_BASE_2_ENA : 1; + unsigned int DEST_BASE_3_ENA : 1; + unsigned int DEST_BASE_4_ENA : 1; + unsigned int DEST_BASE_5_ENA : 1; + unsigned int DEST_BASE_6_ENA : 1; + unsigned int DEST_BASE_7_ENA : 1; + unsigned int RB_COLOR_INFO_ENA : 1; + unsigned int : 7; + unsigned int TC_ACTION_ENA : 1; + unsigned int : 5; + unsigned int STATUS : 1; +#else /* !defined(qLittleEndian) */ + unsigned int STATUS : 1; + unsigned int : 5; + unsigned int TC_ACTION_ENA : 1; + unsigned int : 7; + unsigned int RB_COLOR_INFO_ENA : 1; + unsigned int DEST_BASE_7_ENA : 1; + unsigned int DEST_BASE_6_ENA : 1; + unsigned int DEST_BASE_5_ENA : 1; + unsigned int DEST_BASE_4_ENA : 1; + unsigned int DEST_BASE_3_ENA : 1; + unsigned int DEST_BASE_2_ENA : 1; + unsigned int DEST_BASE_1_ENA : 1; + unsigned int DEST_BASE_0_ENA : 1; + unsigned int RB_COPY_DEST_BASE_ENA : 1; + unsigned int MATCHING_CONTEXTS : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_0 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_0 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_0 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_1 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_1 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_1 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_2 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_2 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_2 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_3 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_3 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_3 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_4 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_4 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_4 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_5 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_5 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_5 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_6 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_6 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_6 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_7 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_7 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_7 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_SURFACE_INFO { + struct { +#if defined(qLittleEndian) + unsigned int SURFACE_PITCH : 14; + unsigned int MSAA_SAMPLES : 2; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int MSAA_SAMPLES : 2; + unsigned int SURFACE_PITCH : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COLOR_INFO { + struct { +#if defined(qLittleEndian) + unsigned int COLOR_FORMAT : 4; + unsigned int COLOR_ROUND_MODE : 2; + unsigned int COLOR_LINEAR : 1; + unsigned int COLOR_ENDIAN : 2; + unsigned int COLOR_SWAP : 2; + unsigned int : 1; + unsigned int COLOR_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int COLOR_BASE : 20; + unsigned int : 1; + unsigned int COLOR_SWAP : 2; + unsigned int COLOR_ENDIAN : 2; + unsigned int COLOR_LINEAR : 1; + unsigned int COLOR_ROUND_MODE : 2; + unsigned int COLOR_FORMAT : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEPTH_INFO { + struct { +#if defined(qLittleEndian) + unsigned int DEPTH_FORMAT : 1; + unsigned int : 11; + unsigned int DEPTH_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEPTH_BASE : 20; + unsigned int : 11; + unsigned int DEPTH_FORMAT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_STENCILREFMASK { + struct { +#if defined(qLittleEndian) + unsigned int STENCILREF : 8; + unsigned int STENCILMASK : 8; + unsigned int STENCILWRITEMASK : 8; + unsigned int RESERVED0 : 1; + unsigned int RESERVED1 : 1; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int RESERVED1 : 1; + unsigned int RESERVED0 : 1; + unsigned int STENCILWRITEMASK : 8; + unsigned int STENCILMASK : 8; + unsigned int STENCILREF : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_ALPHA_REF { + struct { +#if defined(qLittleEndian) + unsigned int ALPHA_REF : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ALPHA_REF : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COLOR_MASK { + struct { +#if defined(qLittleEndian) + unsigned int WRITE_RED : 1; + unsigned int WRITE_GREEN : 1; + unsigned int WRITE_BLUE : 1; + unsigned int WRITE_ALPHA : 1; + unsigned int RESERVED2 : 1; + unsigned int RESERVED3 : 1; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int RESERVED3 : 1; + unsigned int RESERVED2 : 1; + unsigned int WRITE_ALPHA : 1; + unsigned int WRITE_BLUE : 1; + unsigned int WRITE_GREEN : 1; + unsigned int WRITE_RED : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLEND_RED { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_RED : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int BLEND_RED : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLEND_GREEN { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_GREEN : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int BLEND_GREEN : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLEND_BLUE { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_BLUE : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int BLEND_BLUE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLEND_ALPHA { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_ALPHA : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int BLEND_ALPHA : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_FOG_COLOR { + struct { +#if defined(qLittleEndian) + unsigned int FOG_RED : 8; + unsigned int FOG_GREEN : 8; + unsigned int FOG_BLUE : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int FOG_BLUE : 8; + unsigned int FOG_GREEN : 8; + unsigned int FOG_RED : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_STENCILREFMASK_BF { + struct { +#if defined(qLittleEndian) + unsigned int STENCILREF_BF : 8; + unsigned int STENCILMASK_BF : 8; + unsigned int STENCILWRITEMASK_BF : 8; + unsigned int RESERVED4 : 1; + unsigned int RESERVED5 : 1; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int RESERVED5 : 1; + unsigned int RESERVED4 : 1; + unsigned int STENCILWRITEMASK_BF : 8; + unsigned int STENCILMASK_BF : 8; + unsigned int STENCILREF_BF : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEPTHCONTROL { + struct { +#if defined(qLittleEndian) + unsigned int STENCIL_ENABLE : 1; + unsigned int Z_ENABLE : 1; + unsigned int Z_WRITE_ENABLE : 1; + unsigned int EARLY_Z_ENABLE : 1; + unsigned int ZFUNC : 3; + unsigned int BACKFACE_ENABLE : 1; + unsigned int STENCILFUNC : 3; + unsigned int STENCILFAIL : 3; + unsigned int STENCILZPASS : 3; + unsigned int STENCILZFAIL : 3; + unsigned int STENCILFUNC_BF : 3; + unsigned int STENCILFAIL_BF : 3; + unsigned int STENCILZPASS_BF : 3; + unsigned int STENCILZFAIL_BF : 3; +#else /* !defined(qLittleEndian) */ + unsigned int STENCILZFAIL_BF : 3; + unsigned int STENCILZPASS_BF : 3; + unsigned int STENCILFAIL_BF : 3; + unsigned int STENCILFUNC_BF : 3; + unsigned int STENCILZFAIL : 3; + unsigned int STENCILZPASS : 3; + unsigned int STENCILFAIL : 3; + unsigned int STENCILFUNC : 3; + unsigned int BACKFACE_ENABLE : 1; + unsigned int ZFUNC : 3; + unsigned int EARLY_Z_ENABLE : 1; + unsigned int Z_WRITE_ENABLE : 1; + unsigned int Z_ENABLE : 1; + unsigned int STENCIL_ENABLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLENDCONTROL { + struct { +#if defined(qLittleEndian) + unsigned int COLOR_SRCBLEND : 5; + unsigned int COLOR_COMB_FCN : 3; + unsigned int COLOR_DESTBLEND : 5; + unsigned int : 3; + unsigned int ALPHA_SRCBLEND : 5; + unsigned int ALPHA_COMB_FCN : 3; + unsigned int ALPHA_DESTBLEND : 5; + unsigned int BLEND_FORCE_ENABLE : 1; + unsigned int BLEND_FORCE : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int BLEND_FORCE : 1; + unsigned int BLEND_FORCE_ENABLE : 1; + unsigned int ALPHA_DESTBLEND : 5; + unsigned int ALPHA_COMB_FCN : 3; + unsigned int ALPHA_SRCBLEND : 5; + unsigned int : 3; + unsigned int COLOR_DESTBLEND : 5; + unsigned int COLOR_COMB_FCN : 3; + unsigned int COLOR_SRCBLEND : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COLORCONTROL { + struct { +#if defined(qLittleEndian) + unsigned int ALPHA_FUNC : 3; + unsigned int ALPHA_TEST_ENABLE : 1; + unsigned int ALPHA_TO_MASK_ENABLE : 1; + unsigned int BLEND_DISABLE : 1; + unsigned int FOG_ENABLE : 1; + unsigned int VS_EXPORTS_FOG : 1; + unsigned int ROP_CODE : 4; + unsigned int DITHER_MODE : 2; + unsigned int DITHER_TYPE : 2; + unsigned int PIXEL_FOG : 1; + unsigned int : 7; + unsigned int ALPHA_TO_MASK_OFFSET0 : 2; + unsigned int ALPHA_TO_MASK_OFFSET1 : 2; + unsigned int ALPHA_TO_MASK_OFFSET2 : 2; + unsigned int ALPHA_TO_MASK_OFFSET3 : 2; +#else /* !defined(qLittleEndian) */ + unsigned int ALPHA_TO_MASK_OFFSET3 : 2; + unsigned int ALPHA_TO_MASK_OFFSET2 : 2; + unsigned int ALPHA_TO_MASK_OFFSET1 : 2; + unsigned int ALPHA_TO_MASK_OFFSET0 : 2; + unsigned int : 7; + unsigned int PIXEL_FOG : 1; + unsigned int DITHER_TYPE : 2; + unsigned int DITHER_MODE : 2; + unsigned int ROP_CODE : 4; + unsigned int VS_EXPORTS_FOG : 1; + unsigned int FOG_ENABLE : 1; + unsigned int BLEND_DISABLE : 1; + unsigned int ALPHA_TO_MASK_ENABLE : 1; + unsigned int ALPHA_TEST_ENABLE : 1; + unsigned int ALPHA_FUNC : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_MODECONTROL { + struct { +#if defined(qLittleEndian) + unsigned int EDRAM_MODE : 3; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int EDRAM_MODE : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COLOR_DEST_MASK { + struct { +#if defined(qLittleEndian) + unsigned int COLOR_DEST_MASK : 32; +#else /* !defined(qLittleEndian) */ + unsigned int COLOR_DEST_MASK : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int COPY_SAMPLE_SELECT : 3; + unsigned int DEPTH_CLEAR_ENABLE : 1; + unsigned int CLEAR_MASK : 4; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int CLEAR_MASK : 4; + unsigned int DEPTH_CLEAR_ENABLE : 1; + unsigned int COPY_SAMPLE_SELECT : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_DEST_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int COPY_DEST_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int COPY_DEST_BASE : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_DEST_PITCH { + struct { +#if defined(qLittleEndian) + unsigned int COPY_DEST_PITCH : 9; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int COPY_DEST_PITCH : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_DEST_INFO { + struct { +#if defined(qLittleEndian) + unsigned int COPY_DEST_ENDIAN : 3; + unsigned int COPY_DEST_LINEAR : 1; + unsigned int COPY_DEST_FORMAT : 4; + unsigned int COPY_DEST_SWAP : 2; + unsigned int COPY_DEST_DITHER_MODE : 2; + unsigned int COPY_DEST_DITHER_TYPE : 2; + unsigned int COPY_MASK_WRITE_RED : 1; + unsigned int COPY_MASK_WRITE_GREEN : 1; + unsigned int COPY_MASK_WRITE_BLUE : 1; + unsigned int COPY_MASK_WRITE_ALPHA : 1; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int COPY_MASK_WRITE_ALPHA : 1; + unsigned int COPY_MASK_WRITE_BLUE : 1; + unsigned int COPY_MASK_WRITE_GREEN : 1; + unsigned int COPY_MASK_WRITE_RED : 1; + unsigned int COPY_DEST_DITHER_TYPE : 2; + unsigned int COPY_DEST_DITHER_MODE : 2; + unsigned int COPY_DEST_SWAP : 2; + unsigned int COPY_DEST_FORMAT : 4; + unsigned int COPY_DEST_LINEAR : 1; + unsigned int COPY_DEST_ENDIAN : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_DEST_PIXEL_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int OFFSET_X : 13; + unsigned int OFFSET_Y : 13; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int OFFSET_Y : 13; + unsigned int OFFSET_X : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEPTH_CLEAR { + struct { +#if defined(qLittleEndian) + unsigned int DEPTH_CLEAR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DEPTH_CLEAR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_SAMPLE_COUNT_CTL { + struct { +#if defined(qLittleEndian) + unsigned int RESET_SAMPLE_COUNT : 1; + unsigned int COPY_SAMPLE_COUNT : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int COPY_SAMPLE_COUNT : 1; + unsigned int RESET_SAMPLE_COUNT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_SAMPLE_COUNT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int SAMPLE_COUNT_ADDR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SAMPLE_COUNT_ADDR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BC_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int ACCUM_LINEAR_MODE_ENABLE : 1; + unsigned int ACCUM_TIMEOUT_SELECT : 2; + unsigned int DISABLE_EDRAM_CAM : 1; + unsigned int DISABLE_EZ_FAST_CONTEXT_SWITCH : 1; + unsigned int DISABLE_EZ_NULL_ZCMD_DROP : 1; + unsigned int DISABLE_LZ_NULL_ZCMD_DROP : 1; + unsigned int ENABLE_AZ_THROTTLE : 1; + unsigned int AZ_THROTTLE_COUNT : 5; + unsigned int : 1; + unsigned int ENABLE_CRC_UPDATE : 1; + unsigned int CRC_MODE : 1; + unsigned int DISABLE_SAMPLE_COUNTERS : 1; + unsigned int DISABLE_ACCUM : 1; + unsigned int ACCUM_ALLOC_MASK : 4; + unsigned int LINEAR_PERFORMANCE_ENABLE : 1; + unsigned int ACCUM_DATA_FIFO_LIMIT : 4; + unsigned int MEM_EXPORT_TIMEOUT_SELECT : 2; + unsigned int MEM_EXPORT_LINEAR_MODE_ENABLE : 1; + unsigned int CRC_SYSTEM : 1; + unsigned int RESERVED6 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED6 : 1; + unsigned int CRC_SYSTEM : 1; + unsigned int MEM_EXPORT_LINEAR_MODE_ENABLE : 1; + unsigned int MEM_EXPORT_TIMEOUT_SELECT : 2; + unsigned int ACCUM_DATA_FIFO_LIMIT : 4; + unsigned int LINEAR_PERFORMANCE_ENABLE : 1; + unsigned int ACCUM_ALLOC_MASK : 4; + unsigned int DISABLE_ACCUM : 1; + unsigned int DISABLE_SAMPLE_COUNTERS : 1; + unsigned int CRC_MODE : 1; + unsigned int ENABLE_CRC_UPDATE : 1; + unsigned int : 1; + unsigned int AZ_THROTTLE_COUNT : 5; + unsigned int ENABLE_AZ_THROTTLE : 1; + unsigned int DISABLE_LZ_NULL_ZCMD_DROP : 1; + unsigned int DISABLE_EZ_NULL_ZCMD_DROP : 1; + unsigned int DISABLE_EZ_FAST_CONTEXT_SWITCH : 1; + unsigned int DISABLE_EDRAM_CAM : 1; + unsigned int ACCUM_TIMEOUT_SELECT : 2; + unsigned int ACCUM_LINEAR_MODE_ENABLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_EDRAM_INFO { + struct { +#if defined(qLittleEndian) + unsigned int EDRAM_SIZE : 4; + unsigned int EDRAM_MAPPING_MODE : 2; + unsigned int : 8; + unsigned int EDRAM_RANGE : 18; +#else /* !defined(qLittleEndian) */ + unsigned int EDRAM_RANGE : 18; + unsigned int : 8; + unsigned int EDRAM_MAPPING_MODE : 2; + unsigned int EDRAM_SIZE : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_CRC_RD_PORT { + struct { +#if defined(qLittleEndian) + unsigned int CRC_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CRC_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_CRC_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int CRC_RD_ADVANCE : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int CRC_RD_ADVANCE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_CRC_MASK { + struct { +#if defined(qLittleEndian) + unsigned int CRC_MASK : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CRC_MASK : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_TOTAL_SAMPLES { + struct { +#if defined(qLittleEndian) + unsigned int TOTAL_SAMPLES : 32; +#else /* !defined(qLittleEndian) */ + unsigned int TOTAL_SAMPLES : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_ZPASS_SAMPLES { + struct { +#if defined(qLittleEndian) + unsigned int ZPASS_SAMPLES : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ZPASS_SAMPLES : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_ZFAIL_SAMPLES { + struct { +#if defined(qLittleEndian) + unsigned int ZFAIL_SAMPLES : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ZFAIL_SAMPLES : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_SFAIL_SAMPLES { + struct { +#if defined(qLittleEndian) + unsigned int SFAIL_SAMPLES : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SFAIL_SAMPLES : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_0 { + struct { +#if defined(qLittleEndian) + unsigned int RDREQ_CTL_Z1_PRE_FULL : 1; + unsigned int RDREQ_CTL_Z0_PRE_FULL : 1; + unsigned int RDREQ_CTL_C1_PRE_FULL : 1; + unsigned int RDREQ_CTL_C0_PRE_FULL : 1; + unsigned int RDREQ_E1_ORDERING_FULL : 1; + unsigned int RDREQ_E0_ORDERING_FULL : 1; + unsigned int RDREQ_Z1_FULL : 1; + unsigned int RDREQ_Z0_FULL : 1; + unsigned int RDREQ_C1_FULL : 1; + unsigned int RDREQ_C0_FULL : 1; + unsigned int WRREQ_E1_MACRO_HI_FULL : 1; + unsigned int WRREQ_E1_MACRO_LO_FULL : 1; + unsigned int WRREQ_E0_MACRO_HI_FULL : 1; + unsigned int WRREQ_E0_MACRO_LO_FULL : 1; + unsigned int WRREQ_C_WE_HI_FULL : 1; + unsigned int WRREQ_C_WE_LO_FULL : 1; + unsigned int WRREQ_Z1_FULL : 1; + unsigned int WRREQ_Z0_FULL : 1; + unsigned int WRREQ_C1_FULL : 1; + unsigned int WRREQ_C0_FULL : 1; + unsigned int CMDFIFO_Z1_HOLD_FULL : 1; + unsigned int CMDFIFO_Z0_HOLD_FULL : 1; + unsigned int CMDFIFO_C1_HOLD_FULL : 1; + unsigned int CMDFIFO_C0_HOLD_FULL : 1; + unsigned int CMDFIFO_Z_ORDERING_FULL : 1; + unsigned int CMDFIFO_C_ORDERING_FULL : 1; + unsigned int C_SX_LAT_FULL : 1; + unsigned int C_SX_CMD_FULL : 1; + unsigned int C_EZ_TILE_FULL : 1; + unsigned int C_REQ_FULL : 1; + unsigned int C_MASK_FULL : 1; + unsigned int EZ_INFSAMP_FULL : 1; +#else /* !defined(qLittleEndian) */ + unsigned int EZ_INFSAMP_FULL : 1; + unsigned int C_MASK_FULL : 1; + unsigned int C_REQ_FULL : 1; + unsigned int C_EZ_TILE_FULL : 1; + unsigned int C_SX_CMD_FULL : 1; + unsigned int C_SX_LAT_FULL : 1; + unsigned int CMDFIFO_C_ORDERING_FULL : 1; + unsigned int CMDFIFO_Z_ORDERING_FULL : 1; + unsigned int CMDFIFO_C0_HOLD_FULL : 1; + unsigned int CMDFIFO_C1_HOLD_FULL : 1; + unsigned int CMDFIFO_Z0_HOLD_FULL : 1; + unsigned int CMDFIFO_Z1_HOLD_FULL : 1; + unsigned int WRREQ_C0_FULL : 1; + unsigned int WRREQ_C1_FULL : 1; + unsigned int WRREQ_Z0_FULL : 1; + unsigned int WRREQ_Z1_FULL : 1; + unsigned int WRREQ_C_WE_LO_FULL : 1; + unsigned int WRREQ_C_WE_HI_FULL : 1; + unsigned int WRREQ_E0_MACRO_LO_FULL : 1; + unsigned int WRREQ_E0_MACRO_HI_FULL : 1; + unsigned int WRREQ_E1_MACRO_LO_FULL : 1; + unsigned int WRREQ_E1_MACRO_HI_FULL : 1; + unsigned int RDREQ_C0_FULL : 1; + unsigned int RDREQ_C1_FULL : 1; + unsigned int RDREQ_Z0_FULL : 1; + unsigned int RDREQ_Z1_FULL : 1; + unsigned int RDREQ_E0_ORDERING_FULL : 1; + unsigned int RDREQ_E1_ORDERING_FULL : 1; + unsigned int RDREQ_CTL_C0_PRE_FULL : 1; + unsigned int RDREQ_CTL_C1_PRE_FULL : 1; + unsigned int RDREQ_CTL_Z0_PRE_FULL : 1; + unsigned int RDREQ_CTL_Z1_PRE_FULL : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_1 { + struct { +#if defined(qLittleEndian) + unsigned int RDREQ_Z1_CMD_EMPTY : 1; + unsigned int RDREQ_Z0_CMD_EMPTY : 1; + unsigned int RDREQ_C1_CMD_EMPTY : 1; + unsigned int RDREQ_C0_CMD_EMPTY : 1; + unsigned int RDREQ_E1_ORDERING_EMPTY : 1; + unsigned int RDREQ_E0_ORDERING_EMPTY : 1; + unsigned int RDREQ_Z1_EMPTY : 1; + unsigned int RDREQ_Z0_EMPTY : 1; + unsigned int RDREQ_C1_EMPTY : 1; + unsigned int RDREQ_C0_EMPTY : 1; + unsigned int WRREQ_E1_MACRO_HI_EMPTY : 1; + unsigned int WRREQ_E1_MACRO_LO_EMPTY : 1; + unsigned int WRREQ_E0_MACRO_HI_EMPTY : 1; + unsigned int WRREQ_E0_MACRO_LO_EMPTY : 1; + unsigned int WRREQ_C_WE_HI_EMPTY : 1; + unsigned int WRREQ_C_WE_LO_EMPTY : 1; + unsigned int WRREQ_Z1_EMPTY : 1; + unsigned int WRREQ_Z0_EMPTY : 1; + unsigned int WRREQ_C1_PRE_EMPTY : 1; + unsigned int WRREQ_C0_PRE_EMPTY : 1; + unsigned int CMDFIFO_Z1_HOLD_EMPTY : 1; + unsigned int CMDFIFO_Z0_HOLD_EMPTY : 1; + unsigned int CMDFIFO_C1_HOLD_EMPTY : 1; + unsigned int CMDFIFO_C0_HOLD_EMPTY : 1; + unsigned int CMDFIFO_Z_ORDERING_EMPTY : 1; + unsigned int CMDFIFO_C_ORDERING_EMPTY : 1; + unsigned int C_SX_LAT_EMPTY : 1; + unsigned int C_SX_CMD_EMPTY : 1; + unsigned int C_EZ_TILE_EMPTY : 1; + unsigned int C_REQ_EMPTY : 1; + unsigned int C_MASK_EMPTY : 1; + unsigned int EZ_INFSAMP_EMPTY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int EZ_INFSAMP_EMPTY : 1; + unsigned int C_MASK_EMPTY : 1; + unsigned int C_REQ_EMPTY : 1; + unsigned int C_EZ_TILE_EMPTY : 1; + unsigned int C_SX_CMD_EMPTY : 1; + unsigned int C_SX_LAT_EMPTY : 1; + unsigned int CMDFIFO_C_ORDERING_EMPTY : 1; + unsigned int CMDFIFO_Z_ORDERING_EMPTY : 1; + unsigned int CMDFIFO_C0_HOLD_EMPTY : 1; + unsigned int CMDFIFO_C1_HOLD_EMPTY : 1; + unsigned int CMDFIFO_Z0_HOLD_EMPTY : 1; + unsigned int CMDFIFO_Z1_HOLD_EMPTY : 1; + unsigned int WRREQ_C0_PRE_EMPTY : 1; + unsigned int WRREQ_C1_PRE_EMPTY : 1; + unsigned int WRREQ_Z0_EMPTY : 1; + unsigned int WRREQ_Z1_EMPTY : 1; + unsigned int WRREQ_C_WE_LO_EMPTY : 1; + unsigned int WRREQ_C_WE_HI_EMPTY : 1; + unsigned int WRREQ_E0_MACRO_LO_EMPTY : 1; + unsigned int WRREQ_E0_MACRO_HI_EMPTY : 1; + unsigned int WRREQ_E1_MACRO_LO_EMPTY : 1; + unsigned int WRREQ_E1_MACRO_HI_EMPTY : 1; + unsigned int RDREQ_C0_EMPTY : 1; + unsigned int RDREQ_C1_EMPTY : 1; + unsigned int RDREQ_Z0_EMPTY : 1; + unsigned int RDREQ_Z1_EMPTY : 1; + unsigned int RDREQ_E0_ORDERING_EMPTY : 1; + unsigned int RDREQ_E1_ORDERING_EMPTY : 1; + unsigned int RDREQ_C0_CMD_EMPTY : 1; + unsigned int RDREQ_C1_CMD_EMPTY : 1; + unsigned int RDREQ_Z0_CMD_EMPTY : 1; + unsigned int RDREQ_Z1_CMD_EMPTY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_2 { + struct { +#if defined(qLittleEndian) + unsigned int TILE_FIFO_COUNT : 4; + unsigned int SX_LAT_FIFO_COUNT : 7; + unsigned int MEM_EXPORT_FLAG : 1; + unsigned int SYSMEM_BLEND_FLAG : 1; + unsigned int CURRENT_TILE_EVENT : 1; + unsigned int EZ_INFTILE_FULL : 1; + unsigned int EZ_MASK_LOWER_FULL : 1; + unsigned int EZ_MASK_UPPER_FULL : 1; + unsigned int Z0_MASK_FULL : 1; + unsigned int Z1_MASK_FULL : 1; + unsigned int Z0_REQ_FULL : 1; + unsigned int Z1_REQ_FULL : 1; + unsigned int Z_SAMP_FULL : 1; + unsigned int Z_TILE_FULL : 1; + unsigned int EZ_INFTILE_EMPTY : 1; + unsigned int EZ_MASK_LOWER_EMPTY : 1; + unsigned int EZ_MASK_UPPER_EMPTY : 1; + unsigned int Z0_MASK_EMPTY : 1; + unsigned int Z1_MASK_EMPTY : 1; + unsigned int Z0_REQ_EMPTY : 1; + unsigned int Z1_REQ_EMPTY : 1; + unsigned int Z_SAMP_EMPTY : 1; + unsigned int Z_TILE_EMPTY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int Z_TILE_EMPTY : 1; + unsigned int Z_SAMP_EMPTY : 1; + unsigned int Z1_REQ_EMPTY : 1; + unsigned int Z0_REQ_EMPTY : 1; + unsigned int Z1_MASK_EMPTY : 1; + unsigned int Z0_MASK_EMPTY : 1; + unsigned int EZ_MASK_UPPER_EMPTY : 1; + unsigned int EZ_MASK_LOWER_EMPTY : 1; + unsigned int EZ_INFTILE_EMPTY : 1; + unsigned int Z_TILE_FULL : 1; + unsigned int Z_SAMP_FULL : 1; + unsigned int Z1_REQ_FULL : 1; + unsigned int Z0_REQ_FULL : 1; + unsigned int Z1_MASK_FULL : 1; + unsigned int Z0_MASK_FULL : 1; + unsigned int EZ_MASK_UPPER_FULL : 1; + unsigned int EZ_MASK_LOWER_FULL : 1; + unsigned int EZ_INFTILE_FULL : 1; + unsigned int CURRENT_TILE_EVENT : 1; + unsigned int SYSMEM_BLEND_FLAG : 1; + unsigned int MEM_EXPORT_FLAG : 1; + unsigned int SX_LAT_FIFO_COUNT : 7; + unsigned int TILE_FIFO_COUNT : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_3 { + struct { +#if defined(qLittleEndian) + unsigned int ACCUM_VALID : 4; + unsigned int ACCUM_FLUSHING : 4; + unsigned int ACCUM_WRITE_CLEAN_COUNT : 6; + unsigned int ACCUM_INPUT_REG_VALID : 1; + unsigned int ACCUM_DATA_FIFO_CNT : 4; + unsigned int SHD_FULL : 1; + unsigned int SHD_EMPTY : 1; + unsigned int EZ_RETURN_LOWER_EMPTY : 1; + unsigned int EZ_RETURN_UPPER_EMPTY : 1; + unsigned int EZ_RETURN_LOWER_FULL : 1; + unsigned int EZ_RETURN_UPPER_FULL : 1; + unsigned int ZEXP_LOWER_EMPTY : 1; + unsigned int ZEXP_UPPER_EMPTY : 1; + unsigned int ZEXP_LOWER_FULL : 1; + unsigned int ZEXP_UPPER_FULL : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int ZEXP_UPPER_FULL : 1; + unsigned int ZEXP_LOWER_FULL : 1; + unsigned int ZEXP_UPPER_EMPTY : 1; + unsigned int ZEXP_LOWER_EMPTY : 1; + unsigned int EZ_RETURN_UPPER_FULL : 1; + unsigned int EZ_RETURN_LOWER_FULL : 1; + unsigned int EZ_RETURN_UPPER_EMPTY : 1; + unsigned int EZ_RETURN_LOWER_EMPTY : 1; + unsigned int SHD_EMPTY : 1; + unsigned int SHD_FULL : 1; + unsigned int ACCUM_DATA_FIFO_CNT : 4; + unsigned int ACCUM_INPUT_REG_VALID : 1; + unsigned int ACCUM_WRITE_CLEAN_COUNT : 6; + unsigned int ACCUM_FLUSHING : 4; + unsigned int ACCUM_VALID : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_4 { + struct { +#if defined(qLittleEndian) + unsigned int GMEM_RD_ACCESS_FLAG : 1; + unsigned int GMEM_WR_ACCESS_FLAG : 1; + unsigned int SYSMEM_RD_ACCESS_FLAG : 1; + unsigned int SYSMEM_WR_ACCESS_FLAG : 1; + unsigned int ACCUM_DATA_FIFO_EMPTY : 1; + unsigned int ACCUM_ORDER_FIFO_EMPTY : 1; + unsigned int ACCUM_DATA_FIFO_FULL : 1; + unsigned int ACCUM_ORDER_FIFO_FULL : 1; + unsigned int SYSMEM_WRITE_COUNT_OVERFLOW : 1; + unsigned int CONTEXT_COUNT_DEBUG : 4; + unsigned int : 19; +#else /* !defined(qLittleEndian) */ + unsigned int : 19; + unsigned int CONTEXT_COUNT_DEBUG : 4; + unsigned int SYSMEM_WRITE_COUNT_OVERFLOW : 1; + unsigned int ACCUM_ORDER_FIFO_FULL : 1; + unsigned int ACCUM_DATA_FIFO_FULL : 1; + unsigned int ACCUM_ORDER_FIFO_EMPTY : 1; + unsigned int ACCUM_DATA_FIFO_EMPTY : 1; + unsigned int SYSMEM_WR_ACCESS_FLAG : 1; + unsigned int SYSMEM_RD_ACCESS_FLAG : 1; + unsigned int GMEM_WR_ACCESS_FLAG : 1; + unsigned int GMEM_RD_ACCESS_FLAG : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_FLAG_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int DEBUG_FLAG_CLEAR : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int DEBUG_FLAG_CLEAR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BC_SPARES { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BC_DUMMY_CRAYRB_ENUMS { + struct { +#if defined(qLittleEndian) + unsigned int DUMMY_CRAYRB_DEPTH_FORMAT : 6; + unsigned int DUMMY_CRAYRB_SURFACE_SWAP : 1; + unsigned int DUMMY_CRAYRB_DEPTH_ARRAY : 2; + unsigned int DUMMY_CRAYRB_ARRAY : 2; + unsigned int DUMMY_CRAYRB_COLOR_FORMAT : 6; + unsigned int DUMMY_CRAYRB_SURFACE_NUMBER : 3; + unsigned int DUMMY_CRAYRB_SURFACE_FORMAT : 6; + unsigned int DUMMY_CRAYRB_SURFACE_TILING : 1; + unsigned int DUMMY_CRAYRB_SURFACE_ARRAY : 2; + unsigned int DUMMY_RB_COPY_DEST_INFO_NUMBER : 3; +#else /* !defined(qLittleEndian) */ + unsigned int DUMMY_RB_COPY_DEST_INFO_NUMBER : 3; + unsigned int DUMMY_CRAYRB_SURFACE_ARRAY : 2; + unsigned int DUMMY_CRAYRB_SURFACE_TILING : 1; + unsigned int DUMMY_CRAYRB_SURFACE_FORMAT : 6; + unsigned int DUMMY_CRAYRB_SURFACE_NUMBER : 3; + unsigned int DUMMY_CRAYRB_COLOR_FORMAT : 6; + unsigned int DUMMY_CRAYRB_ARRAY : 2; + unsigned int DUMMY_CRAYRB_DEPTH_ARRAY : 2; + unsigned int DUMMY_CRAYRB_SURFACE_SWAP : 1; + unsigned int DUMMY_CRAYRB_DEPTH_FORMAT : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BC_DUMMY_CRAYRB_MOREENUMS { + struct { +#if defined(qLittleEndian) + unsigned int DUMMY_CRAYRB_COLORARRAYX : 2; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int DUMMY_CRAYRB_COLORARRAYX : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_shift.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_shift.h new file mode 100644 index 000000000000..10807b43ea44 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_shift.h @@ -0,0 +1,4183 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_SHIFT_HEADER) +#define _yamato_SHIFT_HEADER + +// PA_CL_VPORT_XSCALE +#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x00000000 + +// PA_CL_VPORT_XOFFSET +#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x00000000 + +// PA_CL_VPORT_YSCALE +#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x00000000 + +// PA_CL_VPORT_YOFFSET +#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x00000000 + +// PA_CL_VPORT_ZSCALE +#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x00000000 + +// PA_CL_VPORT_ZOFFSET +#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x00000000 + +// PA_CL_VTE_CNTL +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x00000000 +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x00000001 +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x00000002 +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x00000003 +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x00000004 +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x00000005 +#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x00000008 +#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x00000009 +#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0x0000000a +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0x0000000b + +// PA_CL_CLIP_CNTL +#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x00000010 +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x00000012 +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x00000013 +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x00000014 +#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x00000015 +#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN__SHIFT 0x00000016 +#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN__SHIFT 0x00000017 +#define PA_CL_CLIP_CNTL__W_NAN_RETAIN__SHIFT 0x00000018 + +// PA_CL_GB_VERT_CLIP_ADJ +#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x00000000 + +// PA_CL_GB_VERT_DISC_ADJ +#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x00000000 + +// PA_CL_GB_HORZ_CLIP_ADJ +#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x00000000 + +// PA_CL_GB_HORZ_DISC_ADJ +#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x00000000 + +// PA_CL_ENHANCE +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x00000000 +#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x0000001c +#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x0000001d +#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x0000001e +#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x0000001f + +// PA_SC_ENHANCE +#define PA_SC_ENHANCE__ECO_SPARE3__SHIFT 0x0000001c +#define PA_SC_ENHANCE__ECO_SPARE2__SHIFT 0x0000001d +#define PA_SC_ENHANCE__ECO_SPARE1__SHIFT 0x0000001e +#define PA_SC_ENHANCE__ECO_SPARE0__SHIFT 0x0000001f + +// PA_SU_VTX_CNTL +#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x00000000 +#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x00000001 +#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x00000003 + +// PA_SU_POINT_SIZE +#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x00000000 +#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x00000010 + +// PA_SU_POINT_MINMAX +#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x00000000 +#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x00000010 + +// PA_SU_LINE_CNTL +#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x00000000 + +// PA_SU_FACE_DATA +#define PA_SU_FACE_DATA__BASE_ADDR__SHIFT 0x00000005 + +// PA_SU_SC_MODE_CNTL +#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x00000000 +#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x00000001 +#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x00000002 +#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x00000003 +#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x00000005 +#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x00000008 +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0x0000000b +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0x0000000c +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0x0000000d +#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE__SHIFT 0x0000000f +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x00000010 +#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE__SHIFT 0x00000012 +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x00000013 +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x00000014 +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x00000015 +#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE__SHIFT 0x00000017 +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI__SHIFT 0x00000019 +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE__SHIFT 0x0000001a +#define PA_SU_SC_MODE_CNTL__ZERO_AREA_FACENESS__SHIFT 0x0000001d +#define PA_SU_SC_MODE_CNTL__FACE_KILL_ENABLE__SHIFT 0x0000001e +#define PA_SU_SC_MODE_CNTL__FACE_WRITE_ENABLE__SHIFT 0x0000001f + +// PA_SU_POLY_OFFSET_FRONT_SCALE +#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x00000000 + +// PA_SU_POLY_OFFSET_FRONT_OFFSET +#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x00000000 + +// PA_SU_POLY_OFFSET_BACK_SCALE +#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x00000000 + +// PA_SU_POLY_OFFSET_BACK_OFFSET +#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER0_SELECT +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER1_SELECT +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER2_SELECT +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER3_SELECT +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER0_LOW +#define PA_SU_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER0_HI +#define PA_SU_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER1_LOW +#define PA_SU_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER1_HI +#define PA_SU_PERFCOUNTER1_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER2_LOW +#define PA_SU_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER2_HI +#define PA_SU_PERFCOUNTER2_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER3_LOW +#define PA_SU_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER3_HI +#define PA_SU_PERFCOUNTER3_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_SC_WINDOW_OFFSET +#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x00000000 +#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x00000010 + +// PA_SC_AA_CONFIG +#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x00000000 +#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0x0000000d + +// PA_SC_AA_MASK +#define PA_SC_AA_MASK__AA_MASK__SHIFT 0x00000000 + +// PA_SC_LINE_STIPPLE +#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x00000000 +#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x00000010 +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x0000001c +#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x0000001d + +// PA_SC_LINE_CNTL +#define PA_SC_LINE_CNTL__BRES_CNTL__SHIFT 0x00000000 +#define PA_SC_LINE_CNTL__USE_BRES_CNTL__SHIFT 0x00000008 +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x00000009 +#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0x0000000a + +// PA_SC_WINDOW_SCISSOR_TL +#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f + +// PA_SC_WINDOW_SCISSOR_BR +#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x00000010 + +// PA_SC_SCREEN_SCISSOR_TL +#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x00000010 + +// PA_SC_SCREEN_SCISSOR_BR +#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x00000010 + +// PA_SC_VIZ_QUERY +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA__SHIFT 0x00000000 +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ID__SHIFT 0x00000001 +#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z__SHIFT 0x00000007 + +// PA_SC_VIZ_QUERY_STATUS +#define PA_SC_VIZ_QUERY_STATUS__STATUS_BITS__SHIFT 0x00000000 + +// PA_SC_LINE_STIPPLE_STATE +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x00000000 +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x00000008 + +// PA_SC_PERFCOUNTER0_SELECT +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SC_PERFCOUNTER0_LOW +#define PA_SC_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SC_PERFCOUNTER0_HI +#define PA_SC_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_CL_CNTL_STATUS +#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT 0x0000001f + +// PA_SU_CNTL_STATUS +#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x0000001f + +// PA_SC_CNTL_STATUS +#define PA_SC_CNTL_STATUS__SC_BUSY__SHIFT 0x0000001f + +// PA_SU_DEBUG_CNTL +#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT 0x00000000 + +// PA_SU_DEBUG_DATA +#define PA_SU_DEBUG_DATA__DATA__SHIFT 0x00000000 + +// CLIPPER_DEBUG_REG00 +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT 0x00000002 +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT 0x00000003 +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0x00000005 +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x00000009 +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x0000000a +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT 0x0000000d +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x0000000e +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x0000000f +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x00000010 +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x00000011 +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT 0x00000014 + +// CLIPPER_DEBUG_REG01 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x00000002 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim__SHIFT 0x00000005 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_2__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_1__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_0__SHIFT 0x0000000f +#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x00000016 +#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT 0x00000018 + +// CLIPPER_DEBUG_REG02 +#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO1__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG02__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO0__SHIFT 0x00000018 +#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f + +// CLIPPER_DEBUG_REG03 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO3__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x00000003 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO2__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO1__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO0__SHIFT 0x0000001a + +// CLIPPER_DEBUG_REG04 +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO2__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x00000003 +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO1__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO0__SHIFT 0x00000008 + +// CLIPPER_DEBUG_REG05 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO3__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x00000003 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_event_id__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO2__SHIFT 0x00000010 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO1__SHIFT 0x00000016 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000018 +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO0__SHIFT 0x0000001c + +// CLIPPER_DEBUG_REG09 +#define CLIPPER_DEBUG_REG09__clprim_in_back_event__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_2__SHIFT 0x00000002 +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO2__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_1__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO1__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_0__SHIFT 0x0000000e +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO0__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG09__prim_back_valid__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_out_cnt__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_orig_vertices__SHIFT 0x00000019 +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait__SHIFT 0x0000001b +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty__SHIFT 0x0000001c +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_load__SHIFT 0x0000001e + +// CLIPPER_DEBUG_REG10 +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO3__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO2__SHIFT 0x0000000a +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO1__SHIFT 0x00000010 +#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO0__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot__SHIFT 0x00000016 +#define CLIPPER_DEBUG_REG10__clprim_in_back_deallocate_slot__SHIFT 0x00000017 +#define CLIPPER_DEBUG_REG10__clprim_in_back_event_id__SHIFT 0x0000001a + +// CLIPPER_DEBUG_REG11 +#define CLIPPER_DEBUG_REG11__vertval_bits_vertex_vertex_store_msb__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG11__ALWAYS_ZERO__SHIFT 0x00000004 + +// CLIPPER_DEBUG_REG12 +#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO2__SHIFT 0x00000002 +#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty__SHIFT 0x00000005 +#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO1__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG12__vertval_bits_vertex_cc_next_valid__SHIFT 0x0000000f +#define CLIPPER_DEBUG_REG12__clipcc_vertex_store_indx__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO0__SHIFT 0x00000016 + +// CLIPPER_DEBUG_REG13 +#define CLIPPER_DEBUG_REG13__sm0_clip_vert_cnt__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG13__sm0_prim_end_state__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO1__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG13__sm0_vertex_clip_cnt__SHIFT 0x0000000e +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG13__sm0_current_state__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO0__SHIFT 0x0000001b + +// SXIFCCG_DEBUG_REG0 +#define SXIFCCG_DEBUG_REG0__nan_kill_flag__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG0__position_address__SHIFT 0x00000004 +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO2__SHIFT 0x00000007 +#define SXIFCCG_DEBUG_REG0__point_address__SHIFT 0x0000000a +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO1__SHIFT 0x0000000d +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx__SHIFT 0x00000010 +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO0__SHIFT 0x00000011 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask__SHIFT 0x00000013 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci__SHIFT 0x00000017 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc__SHIFT 0x0000001e +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel__SHIFT 0x0000001f + +// SXIFCCG_DEBUG_REG1 +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO3__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty__SHIFT 0x00000002 +#define SXIFCCG_DEBUG_REG1__available_positions__SHIFT 0x00000004 +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO2__SHIFT 0x00000007 +#define SXIFCCG_DEBUG_REG1__sx_pending_advance__SHIFT 0x0000000b +#define SXIFCCG_DEBUG_REG1__sx_receive_indx__SHIFT 0x0000000c +#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector__SHIFT 0x0000000f +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO1__SHIFT 0x00000010 +#define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT 0x00000014 +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO0__SHIFT 0x00000015 +#define SXIFCCG_DEBUG_REG1__pasx_req_cnt__SHIFT 0x00000017 +#define SXIFCCG_DEBUG_REG1__param_cache_base__SHIFT 0x00000019 + +// SXIFCCG_DEBUG_REG2 +#define SXIFCCG_DEBUG_REG2__sx_sent__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3__SHIFT 0x00000001 +#define SXIFCCG_DEBUG_REG2__sx_aux__SHIFT 0x00000002 +#define SXIFCCG_DEBUG_REG2__sx_request_indx__SHIFT 0x00000003 +#define SXIFCCG_DEBUG_REG2__req_active_verts__SHIFT 0x00000009 +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2__SHIFT 0x00000010 +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx__SHIFT 0x00000011 +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO1__SHIFT 0x00000012 +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts__SHIFT 0x00000014 +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO0__SHIFT 0x00000016 +#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded__SHIFT 0x0000001a +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty__SHIFT 0x0000001b +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full__SHIFT 0x0000001c +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_contents__SHIFT 0x0000001d + +// SXIFCCG_DEBUG_REG3 +#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3__SHIFT 0x00000004 +#define SXIFCCG_DEBUG_REG3__available_positions__SHIFT 0x00000005 +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO2__SHIFT 0x00000008 +#define SXIFCCG_DEBUG_REG3__current_state__SHIFT 0x0000000c +#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty__SHIFT 0x0000000e +#define SXIFCCG_DEBUG_REG3__vertex_fifo_full__SHIFT 0x0000000f +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO1__SHIFT 0x00000010 +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty__SHIFT 0x00000012 +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full__SHIFT 0x00000013 +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty__SHIFT 0x00000014 +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full__SHIFT 0x00000015 +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO0__SHIFT 0x00000016 + +// SETUP_DEBUG_REG0 +#define SETUP_DEBUG_REG0__su_cntl_state__SHIFT 0x00000000 +#define SETUP_DEBUG_REG0__pmode_state__SHIFT 0x00000005 +#define SETUP_DEBUG_REG0__ge_stallb__SHIFT 0x0000000b +#define SETUP_DEBUG_REG0__geom_enable__SHIFT 0x0000000c +#define SETUP_DEBUG_REG0__su_clip_baryc_rtr__SHIFT 0x0000000d +#define SETUP_DEBUG_REG0__su_clip_rtr__SHIFT 0x0000000e +#define SETUP_DEBUG_REG0__pfifo_busy__SHIFT 0x0000000f +#define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT 0x00000010 +#define SETUP_DEBUG_REG0__geom_busy__SHIFT 0x00000011 + +// SETUP_DEBUG_REG1 +#define SETUP_DEBUG_REG1__y_sort0_gated_17_4__SHIFT 0x00000000 +#define SETUP_DEBUG_REG1__x_sort0_gated_17_4__SHIFT 0x0000000e + +// SETUP_DEBUG_REG2 +#define SETUP_DEBUG_REG2__y_sort1_gated_17_4__SHIFT 0x00000000 +#define SETUP_DEBUG_REG2__x_sort1_gated_17_4__SHIFT 0x0000000e + +// SETUP_DEBUG_REG3 +#define SETUP_DEBUG_REG3__y_sort2_gated_17_4__SHIFT 0x00000000 +#define SETUP_DEBUG_REG3__x_sort2_gated_17_4__SHIFT 0x0000000e + +// SETUP_DEBUG_REG4 +#define SETUP_DEBUG_REG4__attr_indx_sort0_gated__SHIFT 0x00000000 +#define SETUP_DEBUG_REG4__null_prim_gated__SHIFT 0x0000000b +#define SETUP_DEBUG_REG4__backfacing_gated__SHIFT 0x0000000c +#define SETUP_DEBUG_REG4__st_indx_gated__SHIFT 0x0000000d +#define SETUP_DEBUG_REG4__clipped_gated__SHIFT 0x00000010 +#define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT 0x00000011 +#define SETUP_DEBUG_REG4__xmajor_gated__SHIFT 0x00000014 +#define SETUP_DEBUG_REG4__diamond_rule_gated__SHIFT 0x00000015 +#define SETUP_DEBUG_REG4__type_gated__SHIFT 0x00000017 +#define SETUP_DEBUG_REG4__fpov_gated__SHIFT 0x0000001a +#define SETUP_DEBUG_REG4__pmode_prim_gated__SHIFT 0x0000001b +#define SETUP_DEBUG_REG4__event_gated__SHIFT 0x0000001c +#define SETUP_DEBUG_REG4__eop_gated__SHIFT 0x0000001d + +// SETUP_DEBUG_REG5 +#define SETUP_DEBUG_REG5__attr_indx_sort2_gated__SHIFT 0x00000000 +#define SETUP_DEBUG_REG5__attr_indx_sort1_gated__SHIFT 0x0000000b +#define SETUP_DEBUG_REG5__provoking_vtx_gated__SHIFT 0x00000016 +#define SETUP_DEBUG_REG5__event_id_gated__SHIFT 0x00000018 + +// PA_SC_DEBUG_CNTL +#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT 0x00000000 + +// PA_SC_DEBUG_DATA +#define PA_SC_DEBUG_DATA__DATA__SHIFT 0x00000000 + +// SC_DEBUG_0 +#define SC_DEBUG_0__pa_freeze_b1__SHIFT 0x00000000 +#define SC_DEBUG_0__pa_sc_valid__SHIFT 0x00000001 +#define SC_DEBUG_0__pa_sc_phase__SHIFT 0x00000002 +#define SC_DEBUG_0__cntx_cnt__SHIFT 0x00000005 +#define SC_DEBUG_0__decr_cntx_cnt__SHIFT 0x0000000c +#define SC_DEBUG_0__incr_cntx_cnt__SHIFT 0x0000000d +#define SC_DEBUG_0__trigger__SHIFT 0x0000001f + +// SC_DEBUG_1 +#define SC_DEBUG_1__em_state__SHIFT 0x00000000 +#define SC_DEBUG_1__em1_data_ready__SHIFT 0x00000003 +#define SC_DEBUG_1__em2_data_ready__SHIFT 0x00000004 +#define SC_DEBUG_1__move_em1_to_em2__SHIFT 0x00000005 +#define SC_DEBUG_1__ef_data_ready__SHIFT 0x00000006 +#define SC_DEBUG_1__ef_state__SHIFT 0x00000007 +#define SC_DEBUG_1__pipe_valid__SHIFT 0x00000009 +#define SC_DEBUG_1__trigger__SHIFT 0x0000001f + +// SC_DEBUG_2 +#define SC_DEBUG_2__rc_rtr_dly__SHIFT 0x00000000 +#define SC_DEBUG_2__qmask_ff_alm_full_d1__SHIFT 0x00000001 +#define SC_DEBUG_2__pipe_freeze_b__SHIFT 0x00000003 +#define SC_DEBUG_2__prim_rts__SHIFT 0x00000004 +#define SC_DEBUG_2__next_prim_rts_dly__SHIFT 0x00000005 +#define SC_DEBUG_2__next_prim_rtr_dly__SHIFT 0x00000006 +#define SC_DEBUG_2__pre_stage1_rts_d1__SHIFT 0x00000007 +#define SC_DEBUG_2__stage0_rts__SHIFT 0x00000008 +#define SC_DEBUG_2__phase_rts_dly__SHIFT 0x00000009 +#define SC_DEBUG_2__end_of_prim_s1_dly__SHIFT 0x0000000f +#define SC_DEBUG_2__pass_empty_prim_s1__SHIFT 0x00000010 +#define SC_DEBUG_2__event_id_s1__SHIFT 0x00000011 +#define SC_DEBUG_2__event_s1__SHIFT 0x00000016 +#define SC_DEBUG_2__trigger__SHIFT 0x0000001f + +// SC_DEBUG_3 +#define SC_DEBUG_3__x_curr_s1__SHIFT 0x00000000 +#define SC_DEBUG_3__y_curr_s1__SHIFT 0x0000000b +#define SC_DEBUG_3__trigger__SHIFT 0x0000001f + +// SC_DEBUG_4 +#define SC_DEBUG_4__y_end_s1__SHIFT 0x00000000 +#define SC_DEBUG_4__y_start_s1__SHIFT 0x0000000e +#define SC_DEBUG_4__y_dir_s1__SHIFT 0x0000001c +#define SC_DEBUG_4__trigger__SHIFT 0x0000001f + +// SC_DEBUG_5 +#define SC_DEBUG_5__x_end_s1__SHIFT 0x00000000 +#define SC_DEBUG_5__x_start_s1__SHIFT 0x0000000e +#define SC_DEBUG_5__x_dir_s1__SHIFT 0x0000001c +#define SC_DEBUG_5__trigger__SHIFT 0x0000001f + +// SC_DEBUG_6 +#define SC_DEBUG_6__z_ff_empty__SHIFT 0x00000000 +#define SC_DEBUG_6__qmcntl_ff_empty__SHIFT 0x00000001 +#define SC_DEBUG_6__xy_ff_empty__SHIFT 0x00000002 +#define SC_DEBUG_6__event_flag__SHIFT 0x00000003 +#define SC_DEBUG_6__z_mask_needed__SHIFT 0x00000004 +#define SC_DEBUG_6__state__SHIFT 0x00000005 +#define SC_DEBUG_6__state_delayed__SHIFT 0x00000008 +#define SC_DEBUG_6__data_valid__SHIFT 0x0000000b +#define SC_DEBUG_6__data_valid_d__SHIFT 0x0000000c +#define SC_DEBUG_6__tilex_delayed__SHIFT 0x0000000d +#define SC_DEBUG_6__tiley_delayed__SHIFT 0x00000016 +#define SC_DEBUG_6__trigger__SHIFT 0x0000001f + +// SC_DEBUG_7 +#define SC_DEBUG_7__event_flag__SHIFT 0x00000000 +#define SC_DEBUG_7__deallocate__SHIFT 0x00000001 +#define SC_DEBUG_7__fposition__SHIFT 0x00000004 +#define SC_DEBUG_7__sr_prim_we__SHIFT 0x00000005 +#define SC_DEBUG_7__last_tile__SHIFT 0x00000006 +#define SC_DEBUG_7__tile_ff_we__SHIFT 0x00000007 +#define SC_DEBUG_7__qs_data_valid__SHIFT 0x00000008 +#define SC_DEBUG_7__qs_q0_y__SHIFT 0x00000009 +#define SC_DEBUG_7__qs_q0_x__SHIFT 0x0000000b +#define SC_DEBUG_7__qs_q0_valid__SHIFT 0x0000000d +#define SC_DEBUG_7__prim_ff_we__SHIFT 0x0000000e +#define SC_DEBUG_7__tile_ff_re__SHIFT 0x0000000f +#define SC_DEBUG_7__fw_prim_data_valid__SHIFT 0x00000010 +#define SC_DEBUG_7__last_quad_of_tile__SHIFT 0x00000011 +#define SC_DEBUG_7__first_quad_of_tile__SHIFT 0x00000012 +#define SC_DEBUG_7__first_quad_of_prim__SHIFT 0x00000013 +#define SC_DEBUG_7__new_prim__SHIFT 0x00000014 +#define SC_DEBUG_7__load_new_tile_data__SHIFT 0x00000015 +#define SC_DEBUG_7__state__SHIFT 0x00000016 +#define SC_DEBUG_7__fifos_ready__SHIFT 0x00000018 +#define SC_DEBUG_7__trigger__SHIFT 0x0000001f + +// SC_DEBUG_8 +#define SC_DEBUG_8__sample_last__SHIFT 0x00000000 +#define SC_DEBUG_8__sample_mask__SHIFT 0x00000001 +#define SC_DEBUG_8__sample_y__SHIFT 0x00000005 +#define SC_DEBUG_8__sample_x__SHIFT 0x00000007 +#define SC_DEBUG_8__sample_send__SHIFT 0x00000009 +#define SC_DEBUG_8__next_cycle__SHIFT 0x0000000a +#define SC_DEBUG_8__ez_sample_ff_full__SHIFT 0x0000000c +#define SC_DEBUG_8__rb_sc_samp_rtr__SHIFT 0x0000000d +#define SC_DEBUG_8__num_samples__SHIFT 0x0000000e +#define SC_DEBUG_8__last_quad_of_tile__SHIFT 0x00000010 +#define SC_DEBUG_8__last_quad_of_prim__SHIFT 0x00000011 +#define SC_DEBUG_8__first_quad_of_prim__SHIFT 0x00000012 +#define SC_DEBUG_8__sample_we__SHIFT 0x00000013 +#define SC_DEBUG_8__fposition__SHIFT 0x00000014 +#define SC_DEBUG_8__event_id__SHIFT 0x00000015 +#define SC_DEBUG_8__event_flag__SHIFT 0x0000001a +#define SC_DEBUG_8__fw_prim_data_valid__SHIFT 0x0000001b +#define SC_DEBUG_8__trigger__SHIFT 0x0000001f + +// SC_DEBUG_9 +#define SC_DEBUG_9__rb_sc_send__SHIFT 0x00000000 +#define SC_DEBUG_9__rb_sc_ez_mask__SHIFT 0x00000001 +#define SC_DEBUG_9__fifo_data_ready__SHIFT 0x00000005 +#define SC_DEBUG_9__early_z_enable__SHIFT 0x00000006 +#define SC_DEBUG_9__mask_state__SHIFT 0x00000007 +#define SC_DEBUG_9__next_ez_mask__SHIFT 0x00000009 +#define SC_DEBUG_9__mask_ready__SHIFT 0x00000019 +#define SC_DEBUG_9__drop_sample__SHIFT 0x0000001a +#define SC_DEBUG_9__fetch_new_sample_data__SHIFT 0x0000001b +#define SC_DEBUG_9__fetch_new_ez_sample_mask__SHIFT 0x0000001c +#define SC_DEBUG_9__pkr_fetch_new_sample_data__SHIFT 0x0000001d +#define SC_DEBUG_9__pkr_fetch_new_prim_data__SHIFT 0x0000001e +#define SC_DEBUG_9__trigger__SHIFT 0x0000001f + +// SC_DEBUG_10 +#define SC_DEBUG_10__combined_sample_mask__SHIFT 0x00000000 +#define SC_DEBUG_10__trigger__SHIFT 0x0000001f + +// SC_DEBUG_11 +#define SC_DEBUG_11__ez_sample_data_ready__SHIFT 0x00000000 +#define SC_DEBUG_11__pkr_fetch_new_sample_data__SHIFT 0x00000001 +#define SC_DEBUG_11__ez_prim_data_ready__SHIFT 0x00000002 +#define SC_DEBUG_11__pkr_fetch_new_prim_data__SHIFT 0x00000003 +#define SC_DEBUG_11__iterator_input_fz__SHIFT 0x00000004 +#define SC_DEBUG_11__packer_send_quads__SHIFT 0x00000005 +#define SC_DEBUG_11__packer_send_cmd__SHIFT 0x00000006 +#define SC_DEBUG_11__packer_send_event__SHIFT 0x00000007 +#define SC_DEBUG_11__next_state__SHIFT 0x00000008 +#define SC_DEBUG_11__state__SHIFT 0x0000000b +#define SC_DEBUG_11__stall__SHIFT 0x0000000e +#define SC_DEBUG_11__trigger__SHIFT 0x0000001f + +// SC_DEBUG_12 +#define SC_DEBUG_12__SQ_iterator_free_buff__SHIFT 0x00000000 +#define SC_DEBUG_12__event_id__SHIFT 0x00000001 +#define SC_DEBUG_12__event_flag__SHIFT 0x00000006 +#define SC_DEBUG_12__itercmdfifo_busy_nc_dly__SHIFT 0x00000007 +#define SC_DEBUG_12__itercmdfifo_full__SHIFT 0x00000008 +#define SC_DEBUG_12__itercmdfifo_empty__SHIFT 0x00000009 +#define SC_DEBUG_12__iter_ds_one_clk_command__SHIFT 0x0000000a +#define SC_DEBUG_12__iter_ds_end_of_prim0__SHIFT 0x0000000b +#define SC_DEBUG_12__iter_ds_end_of_vector__SHIFT 0x0000000c +#define SC_DEBUG_12__iter_qdhit0__SHIFT 0x0000000d +#define SC_DEBUG_12__bc_use_centers_reg__SHIFT 0x0000000e +#define SC_DEBUG_12__bc_output_xy_reg__SHIFT 0x0000000f +#define SC_DEBUG_12__iter_phase_out__SHIFT 0x00000010 +#define SC_DEBUG_12__iter_phase_reg__SHIFT 0x00000012 +#define SC_DEBUG_12__iterator_SP_valid__SHIFT 0x00000014 +#define SC_DEBUG_12__eopv_reg__SHIFT 0x00000015 +#define SC_DEBUG_12__one_clk_cmd_reg__SHIFT 0x00000016 +#define SC_DEBUG_12__iter_dx_end_of_prim__SHIFT 0x00000017 +#define SC_DEBUG_12__trigger__SHIFT 0x0000001f + +// GFX_COPY_STATE +#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x00000000 + +// VGT_DRAW_INITIATOR +#define VGT_DRAW_INITIATOR__PRIM_TYPE__SHIFT 0x00000000 +#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x00000006 +#define VGT_DRAW_INITIATOR__FACENESS_CULL_SELECT__SHIFT 0x00000008 +#define VGT_DRAW_INITIATOR__INDEX_SIZE__SHIFT 0x0000000b +#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x0000000c +#define VGT_DRAW_INITIATOR__SMALL_INDEX__SHIFT 0x0000000d +#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE__SHIFT 0x0000000e +#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE__SHIFT 0x0000000f +#define VGT_DRAW_INITIATOR__NUM_INDICES__SHIFT 0x00000010 + +// VGT_EVENT_INITIATOR +#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x00000000 + +// VGT_DMA_BASE +#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x00000000 + +// VGT_DMA_SIZE +#define VGT_DMA_SIZE__NUM_WORDS__SHIFT 0x00000000 +#define VGT_DMA_SIZE__SWAP_MODE__SHIFT 0x0000001e + +// VGT_BIN_BASE +#define VGT_BIN_BASE__BIN_BASE_ADDR__SHIFT 0x00000000 + +// VGT_BIN_SIZE +#define VGT_BIN_SIZE__NUM_WORDS__SHIFT 0x00000000 +#define VGT_BIN_SIZE__FACENESS_FETCH__SHIFT 0x0000001e +#define VGT_BIN_SIZE__FACENESS_RESET__SHIFT 0x0000001f + +// VGT_CURRENT_BIN_ID_MIN +#define VGT_CURRENT_BIN_ID_MIN__COLUMN__SHIFT 0x00000000 +#define VGT_CURRENT_BIN_ID_MIN__ROW__SHIFT 0x00000003 +#define VGT_CURRENT_BIN_ID_MIN__GUARD_BAND__SHIFT 0x00000006 + +// VGT_CURRENT_BIN_ID_MAX +#define VGT_CURRENT_BIN_ID_MAX__COLUMN__SHIFT 0x00000000 +#define VGT_CURRENT_BIN_ID_MAX__ROW__SHIFT 0x00000003 +#define VGT_CURRENT_BIN_ID_MAX__GUARD_BAND__SHIFT 0x00000006 + +// VGT_IMMED_DATA +#define VGT_IMMED_DATA__DATA__SHIFT 0x00000000 + +// VGT_MAX_VTX_INDX +#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x00000000 + +// VGT_MIN_VTX_INDX +#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x00000000 + +// VGT_INDX_OFFSET +#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x00000000 + +// VGT_VERTEX_REUSE_BLOCK_CNTL +#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x00000000 + +// VGT_OUT_DEALLOC_CNTL +#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x00000000 + +// VGT_MULTI_PRIM_IB_RESET_INDX +#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x00000000 + +// VGT_ENHANCE +#define VGT_ENHANCE__MISC__SHIFT 0x00000000 + +// VGT_VTX_VECT_EJECT_REG +#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x00000000 + +// VGT_LAST_COPY_STATE +#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x00000000 +#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x00000010 + +// VGT_DEBUG_CNTL +#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX__SHIFT 0x00000000 + +// VGT_DEBUG_DATA +#define VGT_DEBUG_DATA__DATA__SHIFT 0x00000000 + +// VGT_CNTL_STATUS +#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x00000000 +#define VGT_CNTL_STATUS__VGT_DMA_BUSY__SHIFT 0x00000001 +#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY__SHIFT 0x00000002 +#define VGT_CNTL_STATUS__VGT_GRP_BUSY__SHIFT 0x00000003 +#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x00000004 +#define VGT_CNTL_STATUS__VGT_BIN_BUSY__SHIFT 0x00000005 +#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x00000006 +#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x00000007 +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x00000008 + +// VGT_DEBUG_REG0 +#define VGT_DEBUG_REG0__te_grp_busy__SHIFT 0x00000000 +#define VGT_DEBUG_REG0__pt_grp_busy__SHIFT 0x00000001 +#define VGT_DEBUG_REG0__vr_grp_busy__SHIFT 0x00000002 +#define VGT_DEBUG_REG0__dma_request_busy__SHIFT 0x00000003 +#define VGT_DEBUG_REG0__out_busy__SHIFT 0x00000004 +#define VGT_DEBUG_REG0__grp_backend_busy__SHIFT 0x00000005 +#define VGT_DEBUG_REG0__grp_busy__SHIFT 0x00000006 +#define VGT_DEBUG_REG0__dma_busy__SHIFT 0x00000007 +#define VGT_DEBUG_REG0__rbiu_dma_request_busy__SHIFT 0x00000008 +#define VGT_DEBUG_REG0__rbiu_busy__SHIFT 0x00000009 +#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended__SHIFT 0x0000000a +#define VGT_DEBUG_REG0__vgt_no_dma_busy__SHIFT 0x0000000b +#define VGT_DEBUG_REG0__vgt_busy_extended__SHIFT 0x0000000c +#define VGT_DEBUG_REG0__vgt_busy__SHIFT 0x0000000d +#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out__SHIFT 0x0000000e +#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy__SHIFT 0x0000000f +#define VGT_DEBUG_REG0__VGT_RBBM_busy__SHIFT 0x00000010 + +// VGT_DEBUG_REG1 +#define VGT_DEBUG_REG1__out_te_data_read__SHIFT 0x00000000 +#define VGT_DEBUG_REG1__te_out_data_valid__SHIFT 0x00000001 +#define VGT_DEBUG_REG1__out_pt_prim_read__SHIFT 0x00000002 +#define VGT_DEBUG_REG1__pt_out_prim_valid__SHIFT 0x00000003 +#define VGT_DEBUG_REG1__out_pt_data_read__SHIFT 0x00000004 +#define VGT_DEBUG_REG1__pt_out_indx_valid__SHIFT 0x00000005 +#define VGT_DEBUG_REG1__out_vr_prim_read__SHIFT 0x00000006 +#define VGT_DEBUG_REG1__vr_out_prim_valid__SHIFT 0x00000007 +#define VGT_DEBUG_REG1__out_vr_indx_read__SHIFT 0x00000008 +#define VGT_DEBUG_REG1__vr_out_indx_valid__SHIFT 0x00000009 +#define VGT_DEBUG_REG1__te_grp_read__SHIFT 0x0000000a +#define VGT_DEBUG_REG1__grp_te_valid__SHIFT 0x0000000b +#define VGT_DEBUG_REG1__pt_grp_read__SHIFT 0x0000000c +#define VGT_DEBUG_REG1__grp_pt_valid__SHIFT 0x0000000d +#define VGT_DEBUG_REG1__vr_grp_read__SHIFT 0x0000000e +#define VGT_DEBUG_REG1__grp_vr_valid__SHIFT 0x0000000f +#define VGT_DEBUG_REG1__grp_dma_read__SHIFT 0x00000010 +#define VGT_DEBUG_REG1__dma_grp_valid__SHIFT 0x00000011 +#define VGT_DEBUG_REG1__grp_rbiu_di_read__SHIFT 0x00000012 +#define VGT_DEBUG_REG1__rbiu_grp_di_valid__SHIFT 0x00000013 +#define VGT_DEBUG_REG1__MH_VGT_rtr__SHIFT 0x00000014 +#define VGT_DEBUG_REG1__VGT_MH_send__SHIFT 0x00000015 +#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr__SHIFT 0x00000016 +#define VGT_DEBUG_REG1__VGT_PA_clip_s_send__SHIFT 0x00000017 +#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr__SHIFT 0x00000018 +#define VGT_DEBUG_REG1__VGT_PA_clip_p_send__SHIFT 0x00000019 +#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr__SHIFT 0x0000001a +#define VGT_DEBUG_REG1__VGT_PA_clip_v_send__SHIFT 0x0000001b +#define VGT_DEBUG_REG1__SQ_VGT_rtr__SHIFT 0x0000001c +#define VGT_DEBUG_REG1__VGT_SQ_send__SHIFT 0x0000001d +#define VGT_DEBUG_REG1__mh_vgt_tag_7_q__SHIFT 0x0000001e + +// VGT_DEBUG_REG3 +#define VGT_DEBUG_REG3__vgt_clk_en__SHIFT 0x00000000 +#define VGT_DEBUG_REG3__reg_fifos_clk_en__SHIFT 0x00000001 + +// VGT_DEBUG_REG6 +#define VGT_DEBUG_REG6__shifter_byte_count_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG6__right_word_indx_q__SHIFT 0x00000005 +#define VGT_DEBUG_REG6__input_data_valid__SHIFT 0x0000000a +#define VGT_DEBUG_REG6__input_data_xfer__SHIFT 0x0000000b +#define VGT_DEBUG_REG6__next_shift_is_vect_1_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG6__next_shift_is_vect_1_d__SHIFT 0x0000000d +#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d__SHIFT 0x0000000e +#define VGT_DEBUG_REG6__space_avail_from_shift__SHIFT 0x0000000f +#define VGT_DEBUG_REG6__shifter_first_load__SHIFT 0x00000010 +#define VGT_DEBUG_REG6__di_state_sel_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q__SHIFT 0x00000012 +#define VGT_DEBUG_REG6__di_first_group_flag_q__SHIFT 0x00000013 +#define VGT_DEBUG_REG6__di_event_flag_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG6__read_draw_initiator__SHIFT 0x00000015 +#define VGT_DEBUG_REG6__loading_di_requires_shifter__SHIFT 0x00000016 +#define VGT_DEBUG_REG6__last_shift_of_packet__SHIFT 0x00000017 +#define VGT_DEBUG_REG6__last_decr_of_packet__SHIFT 0x00000018 +#define VGT_DEBUG_REG6__extract_vector__SHIFT 0x00000019 +#define VGT_DEBUG_REG6__shift_vect_rtr__SHIFT 0x0000001a +#define VGT_DEBUG_REG6__destination_rtr__SHIFT 0x0000001b +#define VGT_DEBUG_REG6__grp_trigger__SHIFT 0x0000001c + +// VGT_DEBUG_REG7 +#define VGT_DEBUG_REG7__di_index_counter_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG7__shift_amount_no_extract__SHIFT 0x00000010 +#define VGT_DEBUG_REG7__shift_amount_extract__SHIFT 0x00000014 +#define VGT_DEBUG_REG7__di_prim_type_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG7__current_source_sel__SHIFT 0x0000001e + +// VGT_DEBUG_REG8 +#define VGT_DEBUG_REG8__current_source_sel__SHIFT 0x00000000 +#define VGT_DEBUG_REG8__left_word_indx_q__SHIFT 0x00000002 +#define VGT_DEBUG_REG8__input_data_cnt__SHIFT 0x00000007 +#define VGT_DEBUG_REG8__input_data_lsw__SHIFT 0x0000000c +#define VGT_DEBUG_REG8__input_data_msw__SHIFT 0x00000011 +#define VGT_DEBUG_REG8__next_small_stride_shift_limit_q__SHIFT 0x00000016 +#define VGT_DEBUG_REG8__current_small_stride_shift_limit_q__SHIFT 0x0000001b + +// VGT_DEBUG_REG9 +#define VGT_DEBUG_REG9__next_stride_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG9__next_stride_d__SHIFT 0x00000005 +#define VGT_DEBUG_REG9__current_shift_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG9__current_shift_d__SHIFT 0x0000000f +#define VGT_DEBUG_REG9__current_stride_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG9__current_stride_d__SHIFT 0x00000019 +#define VGT_DEBUG_REG9__grp_trigger__SHIFT 0x0000001e + +// VGT_DEBUG_REG10 +#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0__SHIFT 0x00000000 +#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0__SHIFT 0x00000001 +#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0__SHIFT 0x00000002 +#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0__SHIFT 0x00000003 +#define VGT_DEBUG_REG10__di_state_sel_q__SHIFT 0x00000004 +#define VGT_DEBUG_REG10__last_decr_of_packet__SHIFT 0x00000005 +#define VGT_DEBUG_REG10__bin_valid__SHIFT 0x00000006 +#define VGT_DEBUG_REG10__read_block__SHIFT 0x00000007 +#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read__SHIFT 0x00000008 +#define VGT_DEBUG_REG10__last_bit_enable_q__SHIFT 0x00000009 +#define VGT_DEBUG_REG10__last_bit_end_di_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG10__selected_data__SHIFT 0x0000000b +#define VGT_DEBUG_REG10__mask_input_data__SHIFT 0x00000013 +#define VGT_DEBUG_REG10__gap_q__SHIFT 0x0000001b +#define VGT_DEBUG_REG10__temp_mini_reset_z__SHIFT 0x0000001c +#define VGT_DEBUG_REG10__temp_mini_reset_y__SHIFT 0x0000001d +#define VGT_DEBUG_REG10__temp_mini_reset_x__SHIFT 0x0000001e +#define VGT_DEBUG_REG10__grp_trigger__SHIFT 0x0000001f + +// VGT_DEBUG_REG12 +#define VGT_DEBUG_REG12__shifter_byte_count_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG12__right_word_indx_q__SHIFT 0x00000005 +#define VGT_DEBUG_REG12__input_data_valid__SHIFT 0x0000000a +#define VGT_DEBUG_REG12__input_data_xfer__SHIFT 0x0000000b +#define VGT_DEBUG_REG12__next_shift_is_vect_1_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG12__next_shift_is_vect_1_d__SHIFT 0x0000000d +#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d__SHIFT 0x0000000e +#define VGT_DEBUG_REG12__space_avail_from_shift__SHIFT 0x0000000f +#define VGT_DEBUG_REG12__shifter_first_load__SHIFT 0x00000010 +#define VGT_DEBUG_REG12__di_state_sel_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q__SHIFT 0x00000012 +#define VGT_DEBUG_REG12__di_first_group_flag_q__SHIFT 0x00000013 +#define VGT_DEBUG_REG12__di_event_flag_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG12__read_draw_initiator__SHIFT 0x00000015 +#define VGT_DEBUG_REG12__loading_di_requires_shifter__SHIFT 0x00000016 +#define VGT_DEBUG_REG12__last_shift_of_packet__SHIFT 0x00000017 +#define VGT_DEBUG_REG12__last_decr_of_packet__SHIFT 0x00000018 +#define VGT_DEBUG_REG12__extract_vector__SHIFT 0x00000019 +#define VGT_DEBUG_REG12__shift_vect_rtr__SHIFT 0x0000001a +#define VGT_DEBUG_REG12__destination_rtr__SHIFT 0x0000001b +#define VGT_DEBUG_REG12__bgrp_trigger__SHIFT 0x0000001c + +// VGT_DEBUG_REG13 +#define VGT_DEBUG_REG13__di_index_counter_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG13__shift_amount_no_extract__SHIFT 0x00000010 +#define VGT_DEBUG_REG13__shift_amount_extract__SHIFT 0x00000014 +#define VGT_DEBUG_REG13__di_prim_type_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG13__current_source_sel__SHIFT 0x0000001e + +// VGT_DEBUG_REG14 +#define VGT_DEBUG_REG14__current_source_sel__SHIFT 0x00000000 +#define VGT_DEBUG_REG14__left_word_indx_q__SHIFT 0x00000002 +#define VGT_DEBUG_REG14__input_data_cnt__SHIFT 0x00000007 +#define VGT_DEBUG_REG14__input_data_lsw__SHIFT 0x0000000c +#define VGT_DEBUG_REG14__input_data_msw__SHIFT 0x00000011 +#define VGT_DEBUG_REG14__next_small_stride_shift_limit_q__SHIFT 0x00000016 +#define VGT_DEBUG_REG14__current_small_stride_shift_limit_q__SHIFT 0x0000001b + +// VGT_DEBUG_REG15 +#define VGT_DEBUG_REG15__next_stride_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG15__next_stride_d__SHIFT 0x00000005 +#define VGT_DEBUG_REG15__current_shift_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG15__current_shift_d__SHIFT 0x0000000f +#define VGT_DEBUG_REG15__current_stride_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG15__current_stride_d__SHIFT 0x00000019 +#define VGT_DEBUG_REG15__bgrp_trigger__SHIFT 0x0000001e + +// VGT_DEBUG_REG16 +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full__SHIFT 0x00000000 +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty__SHIFT 0x00000001 +#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read__SHIFT 0x00000002 +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we__SHIFT 0x00000003 +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full__SHIFT 0x00000004 +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty__SHIFT 0x00000005 +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q__SHIFT 0x00000006 +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we__SHIFT 0x00000007 +#define VGT_DEBUG_REG16__bgrp_dma_mask_kill__SHIFT 0x00000008 +#define VGT_DEBUG_REG16__bgrp_grp_bin_valid__SHIFT 0x00000009 +#define VGT_DEBUG_REG16__rst_last_bit__SHIFT 0x0000000a +#define VGT_DEBUG_REG16__current_state_q__SHIFT 0x0000000b +#define VGT_DEBUG_REG16__old_state_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG16__old_state_en__SHIFT 0x0000000d +#define VGT_DEBUG_REG16__prev_last_bit_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG16__dbl_last_bit_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG16__last_bit_block_q__SHIFT 0x00000010 +#define VGT_DEBUG_REG16__ast_bit_block2_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG16__load_empty_reg__SHIFT 0x00000012 +#define VGT_DEBUG_REG16__bgrp_grp_byte_mask_rdata__SHIFT 0x00000013 +#define VGT_DEBUG_REG16__dma_bgrp_dma_data_fifo_rptr__SHIFT 0x0000001b +#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable__SHIFT 0x0000001d +#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q__SHIFT 0x0000001e +#define VGT_DEBUG_REG16__bgrp_trigger__SHIFT 0x0000001f + +// VGT_DEBUG_REG17 +#define VGT_DEBUG_REG17__save_read_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG17__extend_read_q__SHIFT 0x00000001 +#define VGT_DEBUG_REG17__grp_indx_size__SHIFT 0x00000002 +#define VGT_DEBUG_REG17__cull_prim_true__SHIFT 0x00000004 +#define VGT_DEBUG_REG17__reset_bit2_q__SHIFT 0x00000005 +#define VGT_DEBUG_REG17__reset_bit1_q__SHIFT 0x00000006 +#define VGT_DEBUG_REG17__first_reg_first_q__SHIFT 0x00000007 +#define VGT_DEBUG_REG17__check_second_reg__SHIFT 0x00000008 +#define VGT_DEBUG_REG17__check_first_reg__SHIFT 0x00000009 +#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata__SHIFT 0x0000000a +#define VGT_DEBUG_REG17__save_cull_fetch_data2_q__SHIFT 0x0000000b +#define VGT_DEBUG_REG17__save_cull_fetch_data1_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG17__save_byte_mask_data2_q__SHIFT 0x0000000d +#define VGT_DEBUG_REG17__save_byte_mask_data1_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG17__to_second_reg_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG17__roll_over_msk_q__SHIFT 0x00000010 +#define VGT_DEBUG_REG17__max_msk_ptr_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG17__min_msk_ptr_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG17__bgrp_trigger__SHIFT 0x0000001f + +// VGT_DEBUG_REG18 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_raddr__SHIFT 0x00000000 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_waddr__SHIFT 0x00000006 +#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re__SHIFT 0x0000000c +#define VGT_DEBUG_REG18__dma_bgrp_dma_data_fifo_rptr__SHIFT 0x0000000d +#define VGT_DEBUG_REG18__dma_mem_full__SHIFT 0x0000000f +#define VGT_DEBUG_REG18__dma_ram_re__SHIFT 0x00000010 +#define VGT_DEBUG_REG18__dma_ram_we__SHIFT 0x00000011 +#define VGT_DEBUG_REG18__dma_mem_empty__SHIFT 0x00000012 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_re__SHIFT 0x00000013 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_we__SHIFT 0x00000014 +#define VGT_DEBUG_REG18__bin_mem_full__SHIFT 0x00000015 +#define VGT_DEBUG_REG18__bin_ram_we__SHIFT 0x00000016 +#define VGT_DEBUG_REG18__bin_ram_re__SHIFT 0x00000017 +#define VGT_DEBUG_REG18__bin_mem_empty__SHIFT 0x00000018 +#define VGT_DEBUG_REG18__start_bin_req__SHIFT 0x00000019 +#define VGT_DEBUG_REG18__fetch_cull_not_used__SHIFT 0x0000001a +#define VGT_DEBUG_REG18__dma_req_xfer__SHIFT 0x0000001b +#define VGT_DEBUG_REG18__have_valid_bin_req__SHIFT 0x0000001c +#define VGT_DEBUG_REG18__have_valid_dma_req__SHIFT 0x0000001d +#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable__SHIFT 0x0000001e +#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable__SHIFT 0x0000001f + +// VGT_DEBUG_REG20 +#define VGT_DEBUG_REG20__prim_side_indx_valid__SHIFT 0x00000000 +#define VGT_DEBUG_REG20__indx_side_fifo_empty__SHIFT 0x00000001 +#define VGT_DEBUG_REG20__indx_side_fifo_re__SHIFT 0x00000002 +#define VGT_DEBUG_REG20__indx_side_fifo_we__SHIFT 0x00000003 +#define VGT_DEBUG_REG20__indx_side_fifo_full__SHIFT 0x00000004 +#define VGT_DEBUG_REG20__prim_buffer_empty__SHIFT 0x00000005 +#define VGT_DEBUG_REG20__prim_buffer_re__SHIFT 0x00000006 +#define VGT_DEBUG_REG20__prim_buffer_we__SHIFT 0x00000007 +#define VGT_DEBUG_REG20__prim_buffer_full__SHIFT 0x00000008 +#define VGT_DEBUG_REG20__indx_buffer_empty__SHIFT 0x00000009 +#define VGT_DEBUG_REG20__indx_buffer_re__SHIFT 0x0000000a +#define VGT_DEBUG_REG20__indx_buffer_we__SHIFT 0x0000000b +#define VGT_DEBUG_REG20__indx_buffer_full__SHIFT 0x0000000c +#define VGT_DEBUG_REG20__hold_prim__SHIFT 0x0000000d +#define VGT_DEBUG_REG20__sent_cnt__SHIFT 0x0000000e +#define VGT_DEBUG_REG20__start_of_vtx_vector__SHIFT 0x00000012 +#define VGT_DEBUG_REG20__clip_s_pre_hold_prim__SHIFT 0x00000013 +#define VGT_DEBUG_REG20__clip_p_pre_hold_prim__SHIFT 0x00000014 +#define VGT_DEBUG_REG20__buffered_prim_type_event__SHIFT 0x00000015 +#define VGT_DEBUG_REG20__out_trigger__SHIFT 0x0000001a + +// VGT_DEBUG_REG21 +#define VGT_DEBUG_REG21__null_terminate_vtx_vector__SHIFT 0x00000000 +#define VGT_DEBUG_REG21__prim_end_of_vtx_vect_flags__SHIFT 0x00000001 +#define VGT_DEBUG_REG21__alloc_counter_q__SHIFT 0x00000004 +#define VGT_DEBUG_REG21__curr_slot_in_vtx_vect_q__SHIFT 0x00000007 +#define VGT_DEBUG_REG21__int_vtx_counter_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG21__curr_dealloc_distance_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG21__new_packet_q__SHIFT 0x00000012 +#define VGT_DEBUG_REG21__new_allocate_q__SHIFT 0x00000013 +#define VGT_DEBUG_REG21__num_new_unique_rel_indx__SHIFT 0x00000014 +#define VGT_DEBUG_REG21__inserted_null_prim_q__SHIFT 0x00000016 +#define VGT_DEBUG_REG21__insert_null_prim__SHIFT 0x00000017 +#define VGT_DEBUG_REG21__buffered_prim_eop_mux__SHIFT 0x00000018 +#define VGT_DEBUG_REG21__prim_buffer_empty_mux__SHIFT 0x00000019 +#define VGT_DEBUG_REG21__buffered_thread_size__SHIFT 0x0000001a +#define VGT_DEBUG_REG21__out_trigger__SHIFT 0x0000001f + +// VGT_CRC_SQ_DATA +#define VGT_CRC_SQ_DATA__CRC__SHIFT 0x00000000 + +// VGT_CRC_SQ_CTRL +#define VGT_CRC_SQ_CTRL__CRC__SHIFT 0x00000000 + +// VGT_PERFCOUNTER0_SELECT +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// VGT_PERFCOUNTER1_SELECT +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 + +// VGT_PERFCOUNTER2_SELECT +#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 + +// VGT_PERFCOUNTER3_SELECT +#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 + +// VGT_PERFCOUNTER0_LOW +#define VGT_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER1_LOW +#define VGT_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER2_LOW +#define VGT_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER3_LOW +#define VGT_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER0_HI +#define VGT_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER1_HI +#define VGT_PERFCOUNTER1_HI__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER2_HI +#define VGT_PERFCOUNTER2_HI__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER3_HI +#define VGT_PERFCOUNTER3_HI__PERF_COUNT__SHIFT 0x00000000 + +// TC_CNTL_STATUS +#define TC_CNTL_STATUS__L2_INVALIDATE__SHIFT 0x00000000 +#define TC_CNTL_STATUS__TC_L2_HIT_MISS__SHIFT 0x00000012 +#define TC_CNTL_STATUS__TC_BUSY__SHIFT 0x0000001f + +// TCR_CHICKEN +#define TCR_CHICKEN__SPARE__SHIFT 0x00000000 + +// TCF_CHICKEN +#define TCF_CHICKEN__SPARE__SHIFT 0x00000000 + +// TCM_CHICKEN +#define TCM_CHICKEN__TCO_READ_LATENCY_FIFO_PROG_DEPTH__SHIFT 0x00000000 +#define TCM_CHICKEN__ETC_COLOR_ENDIAN__SHIFT 0x00000008 +#define TCM_CHICKEN__SPARE__SHIFT 0x00000009 + +// TCR_PERFCOUNTER0_SELECT +#define TCR_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCR_PERFCOUNTER1_SELECT +#define TCR_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCR_PERFCOUNTER0_HI +#define TCR_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCR_PERFCOUNTER1_HI +#define TCR_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCR_PERFCOUNTER0_LOW +#define TCR_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCR_PERFCOUNTER1_LOW +#define TCR_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TP_TC_CLKGATE_CNTL +#define TP_TC_CLKGATE_CNTL__TP_BUSY_EXTEND__SHIFT 0x00000000 +#define TP_TC_CLKGATE_CNTL__TC_BUSY_EXTEND__SHIFT 0x00000003 + +// TPC_CNTL_STATUS +#define TPC_CNTL_STATUS__TPC_INPUT_BUSY__SHIFT 0x00000000 +#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY__SHIFT 0x00000001 +#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY__SHIFT 0x00000002 +#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY__SHIFT 0x00000003 +#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY__SHIFT 0x00000004 +#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY__SHIFT 0x00000005 +#define TPC_CNTL_STATUS__TPC_WALKER_BUSY__SHIFT 0x00000006 +#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY__SHIFT 0x00000008 +#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY__SHIFT 0x00000009 +#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY__SHIFT 0x0000000a +#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY__SHIFT 0x0000000c +#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY__SHIFT 0x0000000d +#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY__SHIFT 0x0000000e +#define TPC_CNTL_STATUS__TPC_BLEND_BUSY__SHIFT 0x0000000f +#define TPC_CNTL_STATUS__TF_TW_RTS__SHIFT 0x00000010 +#define TPC_CNTL_STATUS__TF_TW_STATE_RTS__SHIFT 0x00000011 +#define TPC_CNTL_STATUS__TF_TW_RTR__SHIFT 0x00000013 +#define TPC_CNTL_STATUS__TW_TA_RTS__SHIFT 0x00000014 +#define TPC_CNTL_STATUS__TW_TA_TT_RTS__SHIFT 0x00000015 +#define TPC_CNTL_STATUS__TW_TA_LAST_RTS__SHIFT 0x00000016 +#define TPC_CNTL_STATUS__TW_TA_RTR__SHIFT 0x00000017 +#define TPC_CNTL_STATUS__TA_TB_RTS__SHIFT 0x00000018 +#define TPC_CNTL_STATUS__TA_TB_TT_RTS__SHIFT 0x00000019 +#define TPC_CNTL_STATUS__TA_TB_RTR__SHIFT 0x0000001b +#define TPC_CNTL_STATUS__TA_TF_RTS__SHIFT 0x0000001c +#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN__SHIFT 0x0000001d +#define TPC_CNTL_STATUS__TP_SQ_DEC__SHIFT 0x0000001e +#define TPC_CNTL_STATUS__TPC_BUSY__SHIFT 0x0000001f + +// TPC_DEBUG0 +#define TPC_DEBUG0__LOD_CNTL__SHIFT 0x00000000 +#define TPC_DEBUG0__IC_CTR__SHIFT 0x00000002 +#define TPC_DEBUG0__WALKER_CNTL__SHIFT 0x00000004 +#define TPC_DEBUG0__ALIGNER_CNTL__SHIFT 0x00000008 +#define TPC_DEBUG0__PREV_TC_STATE_VALID__SHIFT 0x0000000c +#define TPC_DEBUG0__WALKER_STATE__SHIFT 0x00000010 +#define TPC_DEBUG0__ALIGNER_STATE__SHIFT 0x0000001a +#define TPC_DEBUG0__REG_CLK_EN__SHIFT 0x0000001d +#define TPC_DEBUG0__TPC_CLK_EN__SHIFT 0x0000001e +#define TPC_DEBUG0__SQ_TP_WAKEUP__SHIFT 0x0000001f + +// TPC_DEBUG1 +#define TPC_DEBUG1__UNUSED__SHIFT 0x00000000 + +// TPC_CHICKEN +#define TPC_CHICKEN__BLEND_PRECISION__SHIFT 0x00000000 +#define TPC_CHICKEN__SPARE__SHIFT 0x00000001 + +// TP0_CNTL_STATUS +#define TP0_CNTL_STATUS__TP_INPUT_BUSY__SHIFT 0x00000000 +#define TP0_CNTL_STATUS__TP_LOD_BUSY__SHIFT 0x00000001 +#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY__SHIFT 0x00000002 +#define TP0_CNTL_STATUS__TP_ADDR_BUSY__SHIFT 0x00000003 +#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY__SHIFT 0x00000004 +#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY__SHIFT 0x00000005 +#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY__SHIFT 0x00000006 +#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY__SHIFT 0x00000007 +#define TP0_CNTL_STATUS__TP_FETCH_BUSY__SHIFT 0x00000008 +#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY__SHIFT 0x00000009 +#define TP0_CNTL_STATUS__TP_TT_BUSY__SHIFT 0x0000000a +#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY__SHIFT 0x0000000b +#define TP0_CNTL_STATUS__TP_BLEND_BUSY__SHIFT 0x0000000c +#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY__SHIFT 0x0000000d +#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY__SHIFT 0x0000000e +#define TP0_CNTL_STATUS__IN_LC_RTS__SHIFT 0x00000010 +#define TP0_CNTL_STATUS__LC_LA_RTS__SHIFT 0x00000011 +#define TP0_CNTL_STATUS__LA_FL_RTS__SHIFT 0x00000012 +#define TP0_CNTL_STATUS__FL_TA_RTS__SHIFT 0x00000013 +#define TP0_CNTL_STATUS__TA_FA_RTS__SHIFT 0x00000014 +#define TP0_CNTL_STATUS__TA_FA_TT_RTS__SHIFT 0x00000015 +#define TP0_CNTL_STATUS__FA_AL_RTS__SHIFT 0x00000016 +#define TP0_CNTL_STATUS__FA_AL_TT_RTS__SHIFT 0x00000017 +#define TP0_CNTL_STATUS__AL_TF_RTS__SHIFT 0x00000018 +#define TP0_CNTL_STATUS__AL_TF_TT_RTS__SHIFT 0x00000019 +#define TP0_CNTL_STATUS__TF_TB_RTS__SHIFT 0x0000001a +#define TP0_CNTL_STATUS__TF_TB_TT_RTS__SHIFT 0x0000001b +#define TP0_CNTL_STATUS__TB_TT_RTS__SHIFT 0x0000001c +#define TP0_CNTL_STATUS__TB_TT_TT_RESET__SHIFT 0x0000001d +#define TP0_CNTL_STATUS__TB_TO_RTS__SHIFT 0x0000001e +#define TP0_CNTL_STATUS__TP_BUSY__SHIFT 0x0000001f + +// TP0_DEBUG +#define TP0_DEBUG__Q_LOD_CNTL__SHIFT 0x00000000 +#define TP0_DEBUG__Q_SQ_TP_WAKEUP__SHIFT 0x00000003 +#define TP0_DEBUG__FL_TA_ADDRESSER_CNTL__SHIFT 0x00000004 +#define TP0_DEBUG__REG_CLK_EN__SHIFT 0x00000015 +#define TP0_DEBUG__PERF_CLK_EN__SHIFT 0x00000016 +#define TP0_DEBUG__TP_CLK_EN__SHIFT 0x00000017 +#define TP0_DEBUG__Q_WALKER_CNTL__SHIFT 0x00000018 +#define TP0_DEBUG__Q_ALIGNER_CNTL__SHIFT 0x0000001c + +// TP0_CHICKEN +#define TP0_CHICKEN__TT_MODE__SHIFT 0x00000000 +#define TP0_CHICKEN__VFETCH_ADDRESS_MODE__SHIFT 0x00000001 +#define TP0_CHICKEN__SPARE__SHIFT 0x00000002 + +// TP0_PERFCOUNTER0_SELECT +#define TP0_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TP0_PERFCOUNTER0_HI +#define TP0_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TP0_PERFCOUNTER0_LOW +#define TP0_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TP0_PERFCOUNTER1_SELECT +#define TP0_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TP0_PERFCOUNTER1_HI +#define TP0_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TP0_PERFCOUNTER1_LOW +#define TP0_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCM_PERFCOUNTER0_SELECT +#define TCM_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCM_PERFCOUNTER1_SELECT +#define TCM_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCM_PERFCOUNTER0_HI +#define TCM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCM_PERFCOUNTER1_HI +#define TCM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCM_PERFCOUNTER0_LOW +#define TCM_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCM_PERFCOUNTER1_LOW +#define TCM_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER0_SELECT +#define TCF_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER1_SELECT +#define TCF_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER2_SELECT +#define TCF_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER3_SELECT +#define TCF_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER4_SELECT +#define TCF_PERFCOUNTER4_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER5_SELECT +#define TCF_PERFCOUNTER5_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER6_SELECT +#define TCF_PERFCOUNTER6_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER7_SELECT +#define TCF_PERFCOUNTER7_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER8_SELECT +#define TCF_PERFCOUNTER8_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER9_SELECT +#define TCF_PERFCOUNTER9_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER10_SELECT +#define TCF_PERFCOUNTER10_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER11_SELECT +#define TCF_PERFCOUNTER11_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER0_HI +#define TCF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER1_HI +#define TCF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER2_HI +#define TCF_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER3_HI +#define TCF_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER4_HI +#define TCF_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER5_HI +#define TCF_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER6_HI +#define TCF_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER7_HI +#define TCF_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER8_HI +#define TCF_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER9_HI +#define TCF_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER10_HI +#define TCF_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER11_HI +#define TCF_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER0_LOW +#define TCF_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER1_LOW +#define TCF_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER2_LOW +#define TCF_PERFCOUNTER2_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER3_LOW +#define TCF_PERFCOUNTER3_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER4_LOW +#define TCF_PERFCOUNTER4_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER5_LOW +#define TCF_PERFCOUNTER5_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER6_LOW +#define TCF_PERFCOUNTER6_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER7_LOW +#define TCF_PERFCOUNTER7_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER8_LOW +#define TCF_PERFCOUNTER8_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER9_LOW +#define TCF_PERFCOUNTER9_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER10_LOW +#define TCF_PERFCOUNTER10_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER11_LOW +#define TCF_PERFCOUNTER11_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_DEBUG +#define TCF_DEBUG__not_MH_TC_rtr__SHIFT 0x00000006 +#define TCF_DEBUG__TC_MH_send__SHIFT 0x00000007 +#define TCF_DEBUG__not_FG0_rtr__SHIFT 0x00000008 +#define TCF_DEBUG__not_TCB_TCO_rtr__SHIFT 0x0000000c +#define TCF_DEBUG__TCB_ff_stall__SHIFT 0x0000000d +#define TCF_DEBUG__TCB_miss_stall__SHIFT 0x0000000e +#define TCF_DEBUG__TCA_TCB_stall__SHIFT 0x0000000f +#define TCF_DEBUG__PF0_stall__SHIFT 0x00000010 +#define TCF_DEBUG__TP0_full__SHIFT 0x00000014 +#define TCF_DEBUG__TPC_full__SHIFT 0x00000018 +#define TCF_DEBUG__not_TPC_rtr__SHIFT 0x00000019 +#define TCF_DEBUG__tca_state_rts__SHIFT 0x0000001a +#define TCF_DEBUG__tca_rts__SHIFT 0x0000001b + +// TCA_FIFO_DEBUG +#define TCA_FIFO_DEBUG__tp0_full__SHIFT 0x00000000 +#define TCA_FIFO_DEBUG__tpc_full__SHIFT 0x00000004 +#define TCA_FIFO_DEBUG__load_tpc_fifo__SHIFT 0x00000005 +#define TCA_FIFO_DEBUG__load_tp_fifos__SHIFT 0x00000006 +#define TCA_FIFO_DEBUG__FW_full__SHIFT 0x00000007 +#define TCA_FIFO_DEBUG__not_FW_rtr0__SHIFT 0x00000008 +#define TCA_FIFO_DEBUG__FW_rts0__SHIFT 0x0000000c +#define TCA_FIFO_DEBUG__not_FW_tpc_rtr__SHIFT 0x00000010 +#define TCA_FIFO_DEBUG__FW_tpc_rts__SHIFT 0x00000011 + +// TCA_PROBE_DEBUG +#define TCA_PROBE_DEBUG__ProbeFilter_stall__SHIFT 0x00000000 + +// TCA_TPC_DEBUG +#define TCA_TPC_DEBUG__captue_state_rts__SHIFT 0x0000000c +#define TCA_TPC_DEBUG__capture_tca_rts__SHIFT 0x0000000d + +// TCB_CORE_DEBUG +#define TCB_CORE_DEBUG__access512__SHIFT 0x00000000 +#define TCB_CORE_DEBUG__tiled__SHIFT 0x00000001 +#define TCB_CORE_DEBUG__opcode__SHIFT 0x00000004 +#define TCB_CORE_DEBUG__format__SHIFT 0x00000008 +#define TCB_CORE_DEBUG__sector_format__SHIFT 0x00000010 +#define TCB_CORE_DEBUG__sector_format512__SHIFT 0x00000018 + +// TCB_TAG0_DEBUG +#define TCB_TAG0_DEBUG__mem_read_cycle__SHIFT 0x00000000 +#define TCB_TAG0_DEBUG__tag_access_cycle__SHIFT 0x0000000c +#define TCB_TAG0_DEBUG__miss_stall__SHIFT 0x00000017 +#define TCB_TAG0_DEBUG__num_feee_lines__SHIFT 0x00000018 +#define TCB_TAG0_DEBUG__max_misses__SHIFT 0x0000001d + +// TCB_TAG1_DEBUG +#define TCB_TAG1_DEBUG__mem_read_cycle__SHIFT 0x00000000 +#define TCB_TAG1_DEBUG__tag_access_cycle__SHIFT 0x0000000c +#define TCB_TAG1_DEBUG__miss_stall__SHIFT 0x00000017 +#define TCB_TAG1_DEBUG__num_feee_lines__SHIFT 0x00000018 +#define TCB_TAG1_DEBUG__max_misses__SHIFT 0x0000001d + +// TCB_TAG2_DEBUG +#define TCB_TAG2_DEBUG__mem_read_cycle__SHIFT 0x00000000 +#define TCB_TAG2_DEBUG__tag_access_cycle__SHIFT 0x0000000c +#define TCB_TAG2_DEBUG__miss_stall__SHIFT 0x00000017 +#define TCB_TAG2_DEBUG__num_feee_lines__SHIFT 0x00000018 +#define TCB_TAG2_DEBUG__max_misses__SHIFT 0x0000001d + +// TCB_TAG3_DEBUG +#define TCB_TAG3_DEBUG__mem_read_cycle__SHIFT 0x00000000 +#define TCB_TAG3_DEBUG__tag_access_cycle__SHIFT 0x0000000c +#define TCB_TAG3_DEBUG__miss_stall__SHIFT 0x00000017 +#define TCB_TAG3_DEBUG__num_feee_lines__SHIFT 0x00000018 +#define TCB_TAG3_DEBUG__max_misses__SHIFT 0x0000001d + +// TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done__SHIFT 0x00000000 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left__SHIFT 0x00000002 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q__SHIFT 0x00000004 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go__SHIFT 0x00000005 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left__SHIFT 0x00000006 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_count_q__SHIFT 0x00000007 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_q__SHIFT 0x0000000c +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q__SHIFT 0x0000001c + +// TCB_FETCH_GEN_WALKER_DEBUG +#define TCB_FETCH_GEN_WALKER_DEBUG__quad_sel_left__SHIFT 0x00000004 +#define TCB_FETCH_GEN_WALKER_DEBUG__set_sel_left__SHIFT 0x00000006 +#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left__SHIFT 0x0000000b +#define TCB_FETCH_GEN_WALKER_DEBUG__ff_fg_type512__SHIFT 0x0000000c +#define TCB_FETCH_GEN_WALKER_DEBUG__busy__SHIFT 0x0000000f +#define TCB_FETCH_GEN_WALKER_DEBUG__setquads_to_send__SHIFT 0x00000010 + +// TCB_FETCH_GEN_PIPE0_DEBUG +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts__SHIFT 0x00000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts__SHIFT 0x00000002 +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_format__SHIFT 0x00000004 +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_fmsopcode__SHIFT 0x00000010 +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_request_type__SHIFT 0x00000015 +#define TCB_FETCH_GEN_PIPE0_DEBUG__busy__SHIFT 0x00000017 +#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy__SHIFT 0x00000018 +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy__SHIFT 0x00000019 +#define TCB_FETCH_GEN_PIPE0_DEBUG__mc_sel_q__SHIFT 0x0000001a +#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q__SHIFT 0x0000001c +#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR__SHIFT 0x0000001e + +// TCD_INPUT0_DEBUG +#define TCD_INPUT0_DEBUG__empty__SHIFT 0x00000010 +#define TCD_INPUT0_DEBUG__full__SHIFT 0x00000011 +#define TCD_INPUT0_DEBUG__valid_q1__SHIFT 0x00000014 +#define TCD_INPUT0_DEBUG__cnt_q1__SHIFT 0x00000015 +#define TCD_INPUT0_DEBUG__last_send_q1__SHIFT 0x00000017 +#define TCD_INPUT0_DEBUG__ip_send__SHIFT 0x00000018 +#define TCD_INPUT0_DEBUG__ipbuf_dxt_send__SHIFT 0x00000019 +#define TCD_INPUT0_DEBUG__ipbuf_busy__SHIFT 0x0000001a + +// TCD_DEGAMMA_DEBUG +#define TCD_DEGAMMA_DEBUG__dgmm_ftfconv_dgmmen__SHIFT 0x00000000 +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8__SHIFT 0x00000002 +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send__SHIFT 0x00000003 +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send__SHIFT 0x00000004 +#define TCD_DEGAMMA_DEBUG__dgmm_stall__SHIFT 0x00000005 +#define TCD_DEGAMMA_DEBUG__dgmm_pstate__SHIFT 0x00000006 + +// TCD_DXTMUX_SCTARB_DEBUG +#define TCD_DXTMUX_SCTARB_DEBUG__pstate__SHIFT 0x00000009 +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr__SHIFT 0x0000000a +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr__SHIFT 0x0000000b +#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send__SHIFT 0x0000000f +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts__SHIFT 0x00000010 +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send__SHIFT 0x00000014 +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send__SHIFT 0x0000001b +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send__SHIFT 0x0000001c +#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send__SHIFT 0x0000001d + +// TCD_DXTC_ARB_DEBUG +#define TCD_DXTC_ARB_DEBUG__n0_stall__SHIFT 0x00000004 +#define TCD_DXTC_ARB_DEBUG__pstate__SHIFT 0x00000005 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send__SHIFT 0x00000006 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cnt__SHIFT 0x00000007 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_sector__SHIFT 0x00000009 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cacheline__SHIFT 0x0000000c +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_format__SHIFT 0x00000012 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send__SHIFT 0x0000001e +#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types__SHIFT 0x0000001f + +// TCD_STALLS_DEBUG +#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr__SHIFT 0x0000000a +#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr__SHIFT 0x0000000b +#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr__SHIFT 0x00000011 +#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr__SHIFT 0x00000012 +#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr__SHIFT 0x00000013 +#define TCD_STALLS_DEBUG__not_incoming_rtr__SHIFT 0x0000001f + +// TCO_STALLS_DEBUG +#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR__SHIFT 0x00000005 +#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR__SHIFT 0x00000006 +#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d__SHIFT 0x00000007 + +// TCO_QUAD0_DEBUG0 +#define TCO_QUAD0_DEBUG0__rl_sg_sector_format__SHIFT 0x00000000 +#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample__SHIFT 0x00000008 +#define TCO_QUAD0_DEBUG0__rl_sg_rtr__SHIFT 0x00000009 +#define TCO_QUAD0_DEBUG0__rl_sg_rts__SHIFT 0x0000000a +#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample__SHIFT 0x0000000b +#define TCO_QUAD0_DEBUG0__sg_crd_rtr__SHIFT 0x0000000c +#define TCO_QUAD0_DEBUG0__sg_crd_rts__SHIFT 0x0000000d +#define TCO_QUAD0_DEBUG0__stageN1_valid_q__SHIFT 0x00000010 +#define TCO_QUAD0_DEBUG0__read_cache_q__SHIFT 0x00000018 +#define TCO_QUAD0_DEBUG0__cache_read_RTR__SHIFT 0x00000019 +#define TCO_QUAD0_DEBUG0__all_sectors_written_set3__SHIFT 0x0000001a +#define TCO_QUAD0_DEBUG0__all_sectors_written_set2__SHIFT 0x0000001b +#define TCO_QUAD0_DEBUG0__all_sectors_written_set1__SHIFT 0x0000001c +#define TCO_QUAD0_DEBUG0__all_sectors_written_set0__SHIFT 0x0000001d +#define TCO_QUAD0_DEBUG0__busy__SHIFT 0x0000001e + +// TCO_QUAD0_DEBUG1 +#define TCO_QUAD0_DEBUG1__fifo_busy__SHIFT 0x00000000 +#define TCO_QUAD0_DEBUG1__empty__SHIFT 0x00000001 +#define TCO_QUAD0_DEBUG1__full__SHIFT 0x00000002 +#define TCO_QUAD0_DEBUG1__write_enable__SHIFT 0x00000003 +#define TCO_QUAD0_DEBUG1__fifo_write_ptr__SHIFT 0x00000004 +#define TCO_QUAD0_DEBUG1__fifo_read_ptr__SHIFT 0x0000000b +#define TCO_QUAD0_DEBUG1__cache_read_busy__SHIFT 0x00000014 +#define TCO_QUAD0_DEBUG1__latency_fifo_busy__SHIFT 0x00000015 +#define TCO_QUAD0_DEBUG1__input_quad_busy__SHIFT 0x00000016 +#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy__SHIFT 0x00000017 +#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d__SHIFT 0x00000018 +#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q__SHIFT 0x00000019 +#define TCO_QUAD0_DEBUG1__rl_sg_rtr__SHIFT 0x0000001a +#define TCO_QUAD0_DEBUG1__rl_sg_rts__SHIFT 0x0000001b +#define TCO_QUAD0_DEBUG1__sg_crd_rtr__SHIFT 0x0000001c +#define TCO_QUAD0_DEBUG1__sg_crd_rts__SHIFT 0x0000001d +#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc__SHIFT 0x0000001e + +// SQ_GPR_MANAGEMENT +#define SQ_GPR_MANAGEMENT__REG_DYNAMIC__SHIFT 0x00000000 +#define SQ_GPR_MANAGEMENT__REG_SIZE_PIX__SHIFT 0x00000004 +#define SQ_GPR_MANAGEMENT__REG_SIZE_VTX__SHIFT 0x0000000c + +// SQ_FLOW_CONTROL +#define SQ_FLOW_CONTROL__INPUT_ARBITRATION_POLICY__SHIFT 0x00000000 +#define SQ_FLOW_CONTROL__ONE_THREAD__SHIFT 0x00000004 +#define SQ_FLOW_CONTROL__ONE_ALU__SHIFT 0x00000008 +#define SQ_FLOW_CONTROL__CF_WR_BASE__SHIFT 0x0000000c +#define SQ_FLOW_CONTROL__NO_PV_PS__SHIFT 0x00000010 +#define SQ_FLOW_CONTROL__NO_LOOP_EXIT__SHIFT 0x00000011 +#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE__SHIFT 0x00000012 +#define SQ_FLOW_CONTROL__TEXTURE_ARBITRATION_POLICY__SHIFT 0x00000013 +#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY__SHIFT 0x00000015 +#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY__SHIFT 0x00000016 +#define SQ_FLOW_CONTROL__NO_ARB_EJECT__SHIFT 0x00000017 +#define SQ_FLOW_CONTROL__NO_CFS_EJECT__SHIFT 0x00000018 +#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY__SHIFT 0x00000019 +#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION__SHIFT 0x0000001a +#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC__SHIFT 0x0000001b + +// SQ_INST_STORE_MANAGMENT +#define SQ_INST_STORE_MANAGMENT__INST_BASE_PIX__SHIFT 0x00000000 +#define SQ_INST_STORE_MANAGMENT__INST_BASE_VTX__SHIFT 0x00000010 + +// SQ_RESOURCE_MANAGMENT +#define SQ_RESOURCE_MANAGMENT__VTX_THREAD_BUF_ENTRIES__SHIFT 0x00000000 +#define SQ_RESOURCE_MANAGMENT__PIX_THREAD_BUF_ENTRIES__SHIFT 0x00000008 +#define SQ_RESOURCE_MANAGMENT__EXPORT_BUF_ENTRIES__SHIFT 0x00000010 + +// SQ_EO_RT +#define SQ_EO_RT__EO_CONSTANTS_RT__SHIFT 0x00000000 +#define SQ_EO_RT__EO_TSTATE_RT__SHIFT 0x00000010 + +// SQ_DEBUG_MISC +#define SQ_DEBUG_MISC__DB_ALUCST_SIZE__SHIFT 0x00000000 +#define SQ_DEBUG_MISC__DB_TSTATE_SIZE__SHIFT 0x0000000c +#define SQ_DEBUG_MISC__DB_READ_CTX__SHIFT 0x00000014 +#define SQ_DEBUG_MISC__RESERVED__SHIFT 0x00000015 +#define SQ_DEBUG_MISC__DB_READ_MEMORY__SHIFT 0x00000017 +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0__SHIFT 0x00000019 +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1__SHIFT 0x0000001a +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2__SHIFT 0x0000001b +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3__SHIFT 0x0000001c + +// SQ_ACTIVITY_METER_CNTL +#define SQ_ACTIVITY_METER_CNTL__TIMEBASE__SHIFT 0x00000000 +#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_LOW__SHIFT 0x00000008 +#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_HIGH__SHIFT 0x00000010 +#define SQ_ACTIVITY_METER_CNTL__SPARE__SHIFT 0x00000018 + +// SQ_ACTIVITY_METER_STATUS +#define SQ_ACTIVITY_METER_STATUS__PERCENT_BUSY__SHIFT 0x00000000 + +// SQ_INPUT_ARB_PRIORITY +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_WEIGHT__SHIFT 0x00000000 +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN__SHIFT 0x00000003 +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_WEIGHT__SHIFT 0x00000004 +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN__SHIFT 0x00000007 +#define SQ_INPUT_ARB_PRIORITY__THRESHOLD__SHIFT 0x00000008 + +// SQ_THREAD_ARB_PRIORITY +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_WEIGHT__SHIFT 0x00000000 +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN__SHIFT 0x00000003 +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_WEIGHT__SHIFT 0x00000004 +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN__SHIFT 0x00000007 +#define SQ_THREAD_ARB_PRIORITY__THRESHOLD__SHIFT 0x00000008 +#define SQ_THREAD_ARB_PRIORITY__RESERVED__SHIFT 0x00000012 +#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL__SHIFT 0x00000014 +#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL__SHIFT 0x00000015 +#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD__SHIFT 0x00000016 + +// SQ_VS_WATCHDOG_TIMER +#define SQ_VS_WATCHDOG_TIMER__ENABLE__SHIFT 0x00000000 +#define SQ_VS_WATCHDOG_TIMER__TIMEOUT_COUNT__SHIFT 0x00000001 + +// SQ_PS_WATCHDOG_TIMER +#define SQ_PS_WATCHDOG_TIMER__ENABLE__SHIFT 0x00000000 +#define SQ_PS_WATCHDOG_TIMER__TIMEOUT_COUNT__SHIFT 0x00000001 + +// SQ_INT_CNTL +#define SQ_INT_CNTL__PS_WATCHDOG_MASK__SHIFT 0x00000000 +#define SQ_INT_CNTL__VS_WATCHDOG_MASK__SHIFT 0x00000001 + +// SQ_INT_STATUS +#define SQ_INT_STATUS__PS_WATCHDOG_TIMEOUT__SHIFT 0x00000000 +#define SQ_INT_STATUS__VS_WATCHDOG_TIMEOUT__SHIFT 0x00000001 + +// SQ_INT_ACK +#define SQ_INT_ACK__PS_WATCHDOG_ACK__SHIFT 0x00000000 +#define SQ_INT_ACK__VS_WATCHDOG_ACK__SHIFT 0x00000001 + +// SQ_DEBUG_INPUT_FSM +#define SQ_DEBUG_INPUT_FSM__VC_VSR_LD__SHIFT 0x00000000 +#define SQ_DEBUG_INPUT_FSM__RESERVED__SHIFT 0x00000003 +#define SQ_DEBUG_INPUT_FSM__VC_GPR_LD__SHIFT 0x00000004 +#define SQ_DEBUG_INPUT_FSM__PC_PISM__SHIFT 0x00000008 +#define SQ_DEBUG_INPUT_FSM__RESERVED1__SHIFT 0x0000000b +#define SQ_DEBUG_INPUT_FSM__PC_AS__SHIFT 0x0000000c +#define SQ_DEBUG_INPUT_FSM__PC_INTERP_CNT__SHIFT 0x0000000f +#define SQ_DEBUG_INPUT_FSM__PC_GPR_SIZE__SHIFT 0x00000014 + +// SQ_DEBUG_CONST_MGR_FSM +#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_EVENT_STATE__SHIFT 0x00000000 +#define SQ_DEBUG_CONST_MGR_FSM__RESERVED1__SHIFT 0x00000005 +#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_EVENT_STATE__SHIFT 0x00000008 +#define SQ_DEBUG_CONST_MGR_FSM__RESERVED2__SHIFT 0x0000000d +#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_CNTX_VALID__SHIFT 0x00000010 +#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_CNTX_VALID__SHIFT 0x00000012 +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE__SHIFT 0x00000014 +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE__SHIFT 0x00000015 +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE__SHIFT 0x00000016 +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE__SHIFT 0x00000017 + +// SQ_DEBUG_TP_FSM +#define SQ_DEBUG_TP_FSM__EX_TP__SHIFT 0x00000000 +#define SQ_DEBUG_TP_FSM__RESERVED0__SHIFT 0x00000003 +#define SQ_DEBUG_TP_FSM__CF_TP__SHIFT 0x00000004 +#define SQ_DEBUG_TP_FSM__IF_TP__SHIFT 0x00000008 +#define SQ_DEBUG_TP_FSM__RESERVED1__SHIFT 0x0000000b +#define SQ_DEBUG_TP_FSM__TIS_TP__SHIFT 0x0000000c +#define SQ_DEBUG_TP_FSM__RESERVED2__SHIFT 0x0000000e +#define SQ_DEBUG_TP_FSM__GS_TP__SHIFT 0x00000010 +#define SQ_DEBUG_TP_FSM__RESERVED3__SHIFT 0x00000012 +#define SQ_DEBUG_TP_FSM__FCR_TP__SHIFT 0x00000014 +#define SQ_DEBUG_TP_FSM__RESERVED4__SHIFT 0x00000016 +#define SQ_DEBUG_TP_FSM__FCS_TP__SHIFT 0x00000018 +#define SQ_DEBUG_TP_FSM__RESERVED5__SHIFT 0x0000001a +#define SQ_DEBUG_TP_FSM__ARB_TR_TP__SHIFT 0x0000001c + +// SQ_DEBUG_FSM_ALU_0 +#define SQ_DEBUG_FSM_ALU_0__EX_ALU_0__SHIFT 0x00000000 +#define SQ_DEBUG_FSM_ALU_0__RESERVED0__SHIFT 0x00000003 +#define SQ_DEBUG_FSM_ALU_0__CF_ALU_0__SHIFT 0x00000004 +#define SQ_DEBUG_FSM_ALU_0__IF_ALU_0__SHIFT 0x00000008 +#define SQ_DEBUG_FSM_ALU_0__RESERVED1__SHIFT 0x0000000b +#define SQ_DEBUG_FSM_ALU_0__DU1_ALU_0__SHIFT 0x0000000c +#define SQ_DEBUG_FSM_ALU_0__RESERVED2__SHIFT 0x0000000f +#define SQ_DEBUG_FSM_ALU_0__DU0_ALU_0__SHIFT 0x00000010 +#define SQ_DEBUG_FSM_ALU_0__RESERVED3__SHIFT 0x00000013 +#define SQ_DEBUG_FSM_ALU_0__AIS_ALU_0__SHIFT 0x00000014 +#define SQ_DEBUG_FSM_ALU_0__RESERVED4__SHIFT 0x00000017 +#define SQ_DEBUG_FSM_ALU_0__ACS_ALU_0__SHIFT 0x00000018 +#define SQ_DEBUG_FSM_ALU_0__RESERVED5__SHIFT 0x0000001b +#define SQ_DEBUG_FSM_ALU_0__ARB_TR_ALU__SHIFT 0x0000001c + +// SQ_DEBUG_FSM_ALU_1 +#define SQ_DEBUG_FSM_ALU_1__EX_ALU_0__SHIFT 0x00000000 +#define SQ_DEBUG_FSM_ALU_1__RESERVED0__SHIFT 0x00000003 +#define SQ_DEBUG_FSM_ALU_1__CF_ALU_0__SHIFT 0x00000004 +#define SQ_DEBUG_FSM_ALU_1__IF_ALU_0__SHIFT 0x00000008 +#define SQ_DEBUG_FSM_ALU_1__RESERVED1__SHIFT 0x0000000b +#define SQ_DEBUG_FSM_ALU_1__DU1_ALU_0__SHIFT 0x0000000c +#define SQ_DEBUG_FSM_ALU_1__RESERVED2__SHIFT 0x0000000f +#define SQ_DEBUG_FSM_ALU_1__DU0_ALU_0__SHIFT 0x00000010 +#define SQ_DEBUG_FSM_ALU_1__RESERVED3__SHIFT 0x00000013 +#define SQ_DEBUG_FSM_ALU_1__AIS_ALU_0__SHIFT 0x00000014 +#define SQ_DEBUG_FSM_ALU_1__RESERVED4__SHIFT 0x00000017 +#define SQ_DEBUG_FSM_ALU_1__ACS_ALU_0__SHIFT 0x00000018 +#define SQ_DEBUG_FSM_ALU_1__RESERVED5__SHIFT 0x0000001b +#define SQ_DEBUG_FSM_ALU_1__ARB_TR_ALU__SHIFT 0x0000001c + +// SQ_DEBUG_EXP_ALLOC +#define SQ_DEBUG_EXP_ALLOC__POS_BUF_AVAIL__SHIFT 0x00000000 +#define SQ_DEBUG_EXP_ALLOC__COLOR_BUF_AVAIL__SHIFT 0x00000004 +#define SQ_DEBUG_EXP_ALLOC__EA_BUF_AVAIL__SHIFT 0x0000000c +#define SQ_DEBUG_EXP_ALLOC__RESERVED__SHIFT 0x0000000f +#define SQ_DEBUG_EXP_ALLOC__ALLOC_TBL_BUF_AVAIL__SHIFT 0x00000010 + +// SQ_DEBUG_PTR_BUFF +#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER__SHIFT 0x00000000 +#define SQ_DEBUG_PTR_BUFF__DEALLOC_CNT__SHIFT 0x00000001 +#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR__SHIFT 0x00000005 +#define SQ_DEBUG_PTR_BUFF__EVENT_CONTEXT_ID__SHIFT 0x00000006 +#define SQ_DEBUG_PTR_BUFF__SC_EVENT_ID__SHIFT 0x00000009 +#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT__SHIFT 0x0000000e +#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON__SHIFT 0x0000000f +#define SQ_DEBUG_PTR_BUFF__EF_EMPTY__SHIFT 0x00000010 +#define SQ_DEBUG_PTR_BUFF__VTX_SYNC_CNT__SHIFT 0x00000011 + +// SQ_DEBUG_GPR_VTX +#define SQ_DEBUG_GPR_VTX__VTX_TAIL_PTR__SHIFT 0x00000000 +#define SQ_DEBUG_GPR_VTX__RESERVED__SHIFT 0x00000007 +#define SQ_DEBUG_GPR_VTX__VTX_HEAD_PTR__SHIFT 0x00000008 +#define SQ_DEBUG_GPR_VTX__RESERVED1__SHIFT 0x0000000f +#define SQ_DEBUG_GPR_VTX__VTX_MAX__SHIFT 0x00000010 +#define SQ_DEBUG_GPR_VTX__RESERVED2__SHIFT 0x00000017 +#define SQ_DEBUG_GPR_VTX__VTX_FREE__SHIFT 0x00000018 + +// SQ_DEBUG_GPR_PIX +#define SQ_DEBUG_GPR_PIX__PIX_TAIL_PTR__SHIFT 0x00000000 +#define SQ_DEBUG_GPR_PIX__RESERVED__SHIFT 0x00000007 +#define SQ_DEBUG_GPR_PIX__PIX_HEAD_PTR__SHIFT 0x00000008 +#define SQ_DEBUG_GPR_PIX__RESERVED1__SHIFT 0x0000000f +#define SQ_DEBUG_GPR_PIX__PIX_MAX__SHIFT 0x00000010 +#define SQ_DEBUG_GPR_PIX__RESERVED2__SHIFT 0x00000017 +#define SQ_DEBUG_GPR_PIX__PIX_FREE__SHIFT 0x00000018 + +// SQ_DEBUG_TB_STATUS_SEL +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATUS_REG_SEL__SHIFT 0x00000000 +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_DW_SEL__SHIFT 0x00000004 +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_ADDR__SHIFT 0x00000007 +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN__SHIFT 0x0000000b +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN__SHIFT 0x0000000c +#define SQ_DEBUG_TB_STATUS_SEL__DEBUG_BUS_TRIGGER_SEL__SHIFT 0x0000000e +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATUS_REG_SEL__SHIFT 0x00000010 +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_DW_SEL__SHIFT 0x00000014 +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_ADDR__SHIFT 0x00000017 +#define SQ_DEBUG_TB_STATUS_SEL__VC_THREAD_BUF_DLY__SHIFT 0x0000001d +#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC__SHIFT 0x0000001f + +// SQ_DEBUG_VTX_TB_0 +#define SQ_DEBUG_VTX_TB_0__VTX_HEAD_PTR_Q__SHIFT 0x00000000 +#define SQ_DEBUG_VTX_TB_0__TAIL_PTR_Q__SHIFT 0x00000004 +#define SQ_DEBUG_VTX_TB_0__FULL_CNT_Q__SHIFT 0x00000008 +#define SQ_DEBUG_VTX_TB_0__NXT_POS_ALLOC_CNT__SHIFT 0x0000000c +#define SQ_DEBUG_VTX_TB_0__NXT_PC_ALLOC_CNT__SHIFT 0x00000010 +#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL__SHIFT 0x00000014 +#define SQ_DEBUG_VTX_TB_0__BUSY_Q__SHIFT 0x00000015 + +// SQ_DEBUG_VTX_TB_1 +#define SQ_DEBUG_VTX_TB_1__VS_DONE_PTR__SHIFT 0x00000000 + +// SQ_DEBUG_VTX_TB_STATUS_REG +#define SQ_DEBUG_VTX_TB_STATUS_REG__VS_STATUS_REG__SHIFT 0x00000000 + +// SQ_DEBUG_VTX_TB_STATE_MEM +#define SQ_DEBUG_VTX_TB_STATE_MEM__VS_STATE_MEM__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_0 +#define SQ_DEBUG_PIX_TB_0__PIX_HEAD_PTR__SHIFT 0x00000000 +#define SQ_DEBUG_PIX_TB_0__TAIL_PTR__SHIFT 0x00000006 +#define SQ_DEBUG_PIX_TB_0__FULL_CNT__SHIFT 0x0000000c +#define SQ_DEBUG_PIX_TB_0__NXT_PIX_ALLOC_CNT__SHIFT 0x00000013 +#define SQ_DEBUG_PIX_TB_0__NXT_PIX_EXP_CNT__SHIFT 0x00000019 +#define SQ_DEBUG_PIX_TB_0__BUSY__SHIFT 0x0000001f + +// SQ_DEBUG_PIX_TB_STATUS_REG_0 +#define SQ_DEBUG_PIX_TB_STATUS_REG_0__PIX_TB_STATUS_REG_0__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_STATUS_REG_1 +#define SQ_DEBUG_PIX_TB_STATUS_REG_1__PIX_TB_STATUS_REG_1__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_STATUS_REG_2 +#define SQ_DEBUG_PIX_TB_STATUS_REG_2__PIX_TB_STATUS_REG_2__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_STATUS_REG_3 +#define SQ_DEBUG_PIX_TB_STATUS_REG_3__PIX_TB_STATUS_REG_3__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_STATE_MEM +#define SQ_DEBUG_PIX_TB_STATE_MEM__PIX_TB_STATE_MEM__SHIFT 0x00000000 + +// SQ_PERFCOUNTER0_SELECT +#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SQ_PERFCOUNTER1_SELECT +#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SQ_PERFCOUNTER2_SELECT +#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SQ_PERFCOUNTER3_SELECT +#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SQ_PERFCOUNTER0_LOW +#define SQ_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER0_HI +#define SQ_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER1_LOW +#define SQ_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER1_HI +#define SQ_PERFCOUNTER1_HI__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER2_LOW +#define SQ_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER2_HI +#define SQ_PERFCOUNTER2_HI__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER3_LOW +#define SQ_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER3_HI +#define SQ_PERFCOUNTER3_HI__PERF_COUNT__SHIFT 0x00000000 + +// SX_PERFCOUNTER0_SELECT +#define SX_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SX_PERFCOUNTER0_LOW +#define SX_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SX_PERFCOUNTER0_HI +#define SX_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// SQ_INSTRUCTION_ALU_0 +#define SQ_INSTRUCTION_ALU_0__VECTOR_RESULT__SHIFT 0x00000000 +#define SQ_INSTRUCTION_ALU_0__VECTOR_DST_REL__SHIFT 0x00000006 +#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP__SHIFT 0x00000007 +#define SQ_INSTRUCTION_ALU_0__SCALAR_RESULT__SHIFT 0x00000008 +#define SQ_INSTRUCTION_ALU_0__SCALAR_DST_REL__SHIFT 0x0000000e +#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA__SHIFT 0x0000000f +#define SQ_INSTRUCTION_ALU_0__VECTOR_WRT_MSK__SHIFT 0x00000010 +#define SQ_INSTRUCTION_ALU_0__SCALAR_WRT_MSK__SHIFT 0x00000014 +#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP__SHIFT 0x00000018 +#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP__SHIFT 0x00000019 +#define SQ_INSTRUCTION_ALU_0__SCALAR_OPCODE__SHIFT 0x0000001a + +// SQ_INSTRUCTION_ALU_1 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_R__SHIFT 0x00000000 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_G__SHIFT 0x00000002 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_B__SHIFT 0x00000004 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_A__SHIFT 0x00000006 +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_R__SHIFT 0x00000008 +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_G__SHIFT 0x0000000a +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_B__SHIFT 0x0000000c +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_A__SHIFT 0x0000000e +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_R__SHIFT 0x00000010 +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_G__SHIFT 0x00000012 +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_B__SHIFT 0x00000014 +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_A__SHIFT 0x00000016 +#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD__SHIFT 0x00000018 +#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD__SHIFT 0x00000019 +#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD__SHIFT 0x0000001a +#define SQ_INSTRUCTION_ALU_1__PRED_SELECT__SHIFT 0x0000001b +#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR__SHIFT 0x0000001d +#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS__SHIFT 0x0000001e +#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS__SHIFT 0x0000001f + +// SQ_INSTRUCTION_ALU_2 +#define SQ_INSTRUCTION_ALU_2__SRC_C_REG_PTR__SHIFT 0x00000000 +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C__SHIFT 0x00000006 +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C__SHIFT 0x00000007 +#define SQ_INSTRUCTION_ALU_2__SRC_B_REG_PTR__SHIFT 0x00000008 +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B__SHIFT 0x0000000e +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B__SHIFT 0x0000000f +#define SQ_INSTRUCTION_ALU_2__SRC_A_REG_PTR__SHIFT 0x00000010 +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A__SHIFT 0x00000016 +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A__SHIFT 0x00000017 +#define SQ_INSTRUCTION_ALU_2__VECTOR_OPCODE__SHIFT 0x00000018 +#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL__SHIFT 0x0000001d +#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL__SHIFT 0x0000001e +#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL__SHIFT 0x0000001f + +// SQ_INSTRUCTION_CF_EXEC_0 +#define SQ_INSTRUCTION_CF_EXEC_0__ADDRESS__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_EXEC_0__RESERVED__SHIFT 0x00000009 +#define SQ_INSTRUCTION_CF_EXEC_0__COUNT__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_EXEC_0__YIELD__SHIFT 0x0000000f +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0__SHIFT 0x00000011 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1__SHIFT 0x00000012 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1__SHIFT 0x00000013 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2__SHIFT 0x00000014 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2__SHIFT 0x00000015 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3__SHIFT 0x00000016 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3__SHIFT 0x00000017 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4__SHIFT 0x00000018 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4__SHIFT 0x00000019 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5__SHIFT 0x0000001a +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0__SHIFT 0x0000001c +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1__SHIFT 0x0000001d +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2__SHIFT 0x0000001e +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3__SHIFT 0x0000001f + +// SQ_INSTRUCTION_CF_EXEC_1 +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5__SHIFT 0x00000001 +#define SQ_INSTRUCTION_CF_EXEC_1__BOOL_ADDR__SHIFT 0x00000002 +#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_EXEC_1__OPCODE__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_EXEC_1__RESERVED__SHIFT 0x00000019 +#define SQ_INSTRUCTION_CF_EXEC_1__COUNT__SHIFT 0x0000001c +#define SQ_INSTRUCTION_CF_EXEC_1__YIELD__SHIFT 0x0000001f + +// SQ_INSTRUCTION_CF_EXEC_2 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0__SHIFT 0x00000001 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1__SHIFT 0x00000002 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1__SHIFT 0x00000003 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2__SHIFT 0x00000004 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2__SHIFT 0x00000005 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3__SHIFT 0x00000006 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3__SHIFT 0x00000007 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4__SHIFT 0x00000008 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4__SHIFT 0x00000009 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1__SHIFT 0x0000000d +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2__SHIFT 0x0000000e +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3__SHIFT 0x0000000f +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5__SHIFT 0x00000011 +#define SQ_INSTRUCTION_CF_EXEC_2__BOOL_ADDR__SHIFT 0x00000012 +#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION__SHIFT 0x0000001a +#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_EXEC_2__OPCODE__SHIFT 0x0000001c + +// SQ_INSTRUCTION_CF_LOOP_0 +#define SQ_INSTRUCTION_CF_LOOP_0__ADDRESS__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_0__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_LOOP_0__LOOP_ID__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_1__SHIFT 0x00000015 + +// SQ_INSTRUCTION_CF_LOOP_1 +#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_0__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_LOOP_1__OPCODE__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_1__SHIFT 0x0000001a + +// SQ_INSTRUCTION_CF_LOOP_2 +#define SQ_INSTRUCTION_CF_LOOP_2__LOOP_ID__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_LOOP_2__RESERVED__SHIFT 0x00000005 +#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_LOOP_2__OPCODE__SHIFT 0x0000001c + +// SQ_INSTRUCTION_CF_JMP_CALL_0 +#define SQ_INSTRUCTION_CF_JMP_CALL_0__ADDRESS__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_0__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL__SHIFT 0x0000000d +#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP__SHIFT 0x0000000e +#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_1__SHIFT 0x0000000f + +// SQ_INSTRUCTION_CF_JMP_CALL_1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION__SHIFT 0x00000001 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__BOOL_ADDR__SHIFT 0x00000002 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_JMP_CALL_1__OPCODE__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_1__SHIFT 0x0000001a +#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL__SHIFT 0x0000001d +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_2__SHIFT 0x0000001e + +// SQ_INSTRUCTION_CF_JMP_CALL_2 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__RESERVED__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION__SHIFT 0x00000011 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__BOOL_ADDR__SHIFT 0x00000012 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION__SHIFT 0x0000001a +#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_JMP_CALL_2__OPCODE__SHIFT 0x0000001c + +// SQ_INSTRUCTION_CF_ALLOC_0 +#define SQ_INSTRUCTION_CF_ALLOC_0__SIZE__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_ALLOC_0__RESERVED__SHIFT 0x00000004 + +// SQ_INSTRUCTION_CF_ALLOC_1 +#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_0__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL__SHIFT 0x00000008 +#define SQ_INSTRUCTION_CF_ALLOC_1__BUFFER_SELECT__SHIFT 0x00000009 +#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_ALLOC_1__OPCODE__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_ALLOC_1__SIZE__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_1__SHIFT 0x00000014 + +// SQ_INSTRUCTION_CF_ALLOC_2 +#define SQ_INSTRUCTION_CF_ALLOC_2__RESERVED__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL__SHIFT 0x00000018 +#define SQ_INSTRUCTION_CF_ALLOC_2__BUFFER_SELECT__SHIFT 0x00000019 +#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_ALLOC_2__OPCODE__SHIFT 0x0000001c + +// SQ_INSTRUCTION_TFETCH_0 +#define SQ_INSTRUCTION_TFETCH_0__OPCODE__SHIFT 0x00000000 +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR__SHIFT 0x00000005 +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM__SHIFT 0x0000000b +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR__SHIFT 0x0000000c +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM__SHIFT 0x00000012 +#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY__SHIFT 0x00000013 +#define SQ_INSTRUCTION_TFETCH_0__CONST_INDEX__SHIFT 0x00000014 +#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM__SHIFT 0x00000019 +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_X__SHIFT 0x0000001a +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Y__SHIFT 0x0000001c +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Z__SHIFT 0x0000001e + +// SQ_INSTRUCTION_TFETCH_1 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_X__SHIFT 0x00000000 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Y__SHIFT 0x00000003 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Z__SHIFT 0x00000006 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_W__SHIFT 0x00000009 +#define SQ_INSTRUCTION_TFETCH_1__MAG_FILTER__SHIFT 0x0000000c +#define SQ_INSTRUCTION_TFETCH_1__MIN_FILTER__SHIFT 0x0000000e +#define SQ_INSTRUCTION_TFETCH_1__MIP_FILTER__SHIFT 0x00000010 +#define SQ_INSTRUCTION_TFETCH_1__ANISO_FILTER__SHIFT 0x00000012 +#define SQ_INSTRUCTION_TFETCH_1__ARBITRARY_FILTER__SHIFT 0x00000015 +#define SQ_INSTRUCTION_TFETCH_1__VOL_MAG_FILTER__SHIFT 0x00000018 +#define SQ_INSTRUCTION_TFETCH_1__VOL_MIN_FILTER__SHIFT 0x0000001a +#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD__SHIFT 0x0000001c +#define SQ_INSTRUCTION_TFETCH_1__USE_REG_LOD__SHIFT 0x0000001d +#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT__SHIFT 0x0000001f + +// SQ_INSTRUCTION_TFETCH_2 +#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS__SHIFT 0x00000000 +#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION__SHIFT 0x00000001 +#define SQ_INSTRUCTION_TFETCH_2__LOD_BIAS__SHIFT 0x00000002 +#define SQ_INSTRUCTION_TFETCH_2__UNUSED__SHIFT 0x00000009 +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_X__SHIFT 0x00000010 +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Y__SHIFT 0x00000015 +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Z__SHIFT 0x0000001a +#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION__SHIFT 0x0000001f + +// SQ_INSTRUCTION_VFETCH_0 +#define SQ_INSTRUCTION_VFETCH_0__OPCODE__SHIFT 0x00000000 +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR__SHIFT 0x00000005 +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM__SHIFT 0x0000000b +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR__SHIFT 0x0000000c +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM__SHIFT 0x00000012 +#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE__SHIFT 0x00000013 +#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX__SHIFT 0x00000014 +#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_SEL__SHIFT 0x00000019 +#define SQ_INSTRUCTION_VFETCH_0__SRC_SEL__SHIFT 0x0000001e + +// SQ_INSTRUCTION_VFETCH_1 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_X__SHIFT 0x00000000 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Y__SHIFT 0x00000003 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Z__SHIFT 0x00000006 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_W__SHIFT 0x00000009 +#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL__SHIFT 0x0000000c +#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL__SHIFT 0x0000000d +#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL__SHIFT 0x0000000e +#define SQ_INSTRUCTION_VFETCH_1__DATA_FORMAT__SHIFT 0x00000010 +#define SQ_INSTRUCTION_VFETCH_1__EXP_ADJUST_ALL__SHIFT 0x00000017 +#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT__SHIFT 0x0000001f + +// SQ_INSTRUCTION_VFETCH_2 +#define SQ_INSTRUCTION_VFETCH_2__STRIDE__SHIFT 0x00000000 +#define SQ_INSTRUCTION_VFETCH_2__OFFSET__SHIFT 0x00000010 +#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION__SHIFT 0x0000001f + +// SQ_CONSTANT_0 +#define SQ_CONSTANT_0__RED__SHIFT 0x00000000 + +// SQ_CONSTANT_1 +#define SQ_CONSTANT_1__GREEN__SHIFT 0x00000000 + +// SQ_CONSTANT_2 +#define SQ_CONSTANT_2__BLUE__SHIFT 0x00000000 + +// SQ_CONSTANT_3 +#define SQ_CONSTANT_3__ALPHA__SHIFT 0x00000000 + +// SQ_FETCH_0 +#define SQ_FETCH_0__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_1 +#define SQ_FETCH_1__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_2 +#define SQ_FETCH_2__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_3 +#define SQ_FETCH_3__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_4 +#define SQ_FETCH_4__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_5 +#define SQ_FETCH_5__VALUE__SHIFT 0x00000000 + +// SQ_CONSTANT_VFETCH_0 +#define SQ_CONSTANT_VFETCH_0__TYPE__SHIFT 0x00000000 +#define SQ_CONSTANT_VFETCH_0__STATE__SHIFT 0x00000001 +#define SQ_CONSTANT_VFETCH_0__BASE_ADDRESS__SHIFT 0x00000002 + +// SQ_CONSTANT_VFETCH_1 +#define SQ_CONSTANT_VFETCH_1__ENDIAN_SWAP__SHIFT 0x00000000 +#define SQ_CONSTANT_VFETCH_1__LIMIT_ADDRESS__SHIFT 0x00000002 + +// SQ_CONSTANT_T2 +#define SQ_CONSTANT_T2__VALUE__SHIFT 0x00000000 + +// SQ_CONSTANT_T3 +#define SQ_CONSTANT_T3__VALUE__SHIFT 0x00000000 + +// SQ_CF_BOOLEANS +#define SQ_CF_BOOLEANS__CF_BOOLEANS_0__SHIFT 0x00000000 +#define SQ_CF_BOOLEANS__CF_BOOLEANS_1__SHIFT 0x00000008 +#define SQ_CF_BOOLEANS__CF_BOOLEANS_2__SHIFT 0x00000010 +#define SQ_CF_BOOLEANS__CF_BOOLEANS_3__SHIFT 0x00000018 + +// SQ_CF_LOOP +#define SQ_CF_LOOP__CF_LOOP_COUNT__SHIFT 0x00000000 +#define SQ_CF_LOOP__CF_LOOP_START__SHIFT 0x00000008 +#define SQ_CF_LOOP__CF_LOOP_STEP__SHIFT 0x00000010 + +// SQ_CONSTANT_RT_0 +#define SQ_CONSTANT_RT_0__RED__SHIFT 0x00000000 + +// SQ_CONSTANT_RT_1 +#define SQ_CONSTANT_RT_1__GREEN__SHIFT 0x00000000 + +// SQ_CONSTANT_RT_2 +#define SQ_CONSTANT_RT_2__BLUE__SHIFT 0x00000000 + +// SQ_CONSTANT_RT_3 +#define SQ_CONSTANT_RT_3__ALPHA__SHIFT 0x00000000 + +// SQ_FETCH_RT_0 +#define SQ_FETCH_RT_0__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_1 +#define SQ_FETCH_RT_1__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_2 +#define SQ_FETCH_RT_2__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_3 +#define SQ_FETCH_RT_3__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_4 +#define SQ_FETCH_RT_4__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_5 +#define SQ_FETCH_RT_5__VALUE__SHIFT 0x00000000 + +// SQ_CF_RT_BOOLEANS +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_0__SHIFT 0x00000000 +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_1__SHIFT 0x00000008 +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_2__SHIFT 0x00000010 +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_3__SHIFT 0x00000018 + +// SQ_CF_RT_LOOP +#define SQ_CF_RT_LOOP__CF_LOOP_COUNT__SHIFT 0x00000000 +#define SQ_CF_RT_LOOP__CF_LOOP_START__SHIFT 0x00000008 +#define SQ_CF_RT_LOOP__CF_LOOP_STEP__SHIFT 0x00000010 + +// SQ_VS_PROGRAM +#define SQ_VS_PROGRAM__BASE__SHIFT 0x00000000 +#define SQ_VS_PROGRAM__SIZE__SHIFT 0x0000000c + +// SQ_PS_PROGRAM +#define SQ_PS_PROGRAM__BASE__SHIFT 0x00000000 +#define SQ_PS_PROGRAM__SIZE__SHIFT 0x0000000c + +// SQ_CF_PROGRAM_SIZE +#define SQ_CF_PROGRAM_SIZE__VS_CF_SIZE__SHIFT 0x00000000 +#define SQ_CF_PROGRAM_SIZE__PS_CF_SIZE__SHIFT 0x0000000c + +// SQ_INTERPOLATOR_CNTL +#define SQ_INTERPOLATOR_CNTL__PARAM_SHADE__SHIFT 0x00000000 +#define SQ_INTERPOLATOR_CNTL__SAMPLING_PATTERN__SHIFT 0x00000010 + +// SQ_PROGRAM_CNTL +#define SQ_PROGRAM_CNTL__VS_NUM_REG__SHIFT 0x00000000 +#define SQ_PROGRAM_CNTL__PS_NUM_REG__SHIFT 0x00000008 +#define SQ_PROGRAM_CNTL__VS_RESOURCE__SHIFT 0x00000010 +#define SQ_PROGRAM_CNTL__PS_RESOURCE__SHIFT 0x00000011 +#define SQ_PROGRAM_CNTL__PARAM_GEN__SHIFT 0x00000012 +#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX__SHIFT 0x00000013 +#define SQ_PROGRAM_CNTL__VS_EXPORT_COUNT__SHIFT 0x00000014 +#define SQ_PROGRAM_CNTL__VS_EXPORT_MODE__SHIFT 0x00000018 +#define SQ_PROGRAM_CNTL__PS_EXPORT_MODE__SHIFT 0x0000001b +#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX__SHIFT 0x0000001f + +// SQ_WRAPPING_0 +#define SQ_WRAPPING_0__PARAM_WRAP_0__SHIFT 0x00000000 +#define SQ_WRAPPING_0__PARAM_WRAP_1__SHIFT 0x00000004 +#define SQ_WRAPPING_0__PARAM_WRAP_2__SHIFT 0x00000008 +#define SQ_WRAPPING_0__PARAM_WRAP_3__SHIFT 0x0000000c +#define SQ_WRAPPING_0__PARAM_WRAP_4__SHIFT 0x00000010 +#define SQ_WRAPPING_0__PARAM_WRAP_5__SHIFT 0x00000014 +#define SQ_WRAPPING_0__PARAM_WRAP_6__SHIFT 0x00000018 +#define SQ_WRAPPING_0__PARAM_WRAP_7__SHIFT 0x0000001c + +// SQ_WRAPPING_1 +#define SQ_WRAPPING_1__PARAM_WRAP_8__SHIFT 0x00000000 +#define SQ_WRAPPING_1__PARAM_WRAP_9__SHIFT 0x00000004 +#define SQ_WRAPPING_1__PARAM_WRAP_10__SHIFT 0x00000008 +#define SQ_WRAPPING_1__PARAM_WRAP_11__SHIFT 0x0000000c +#define SQ_WRAPPING_1__PARAM_WRAP_12__SHIFT 0x00000010 +#define SQ_WRAPPING_1__PARAM_WRAP_13__SHIFT 0x00000014 +#define SQ_WRAPPING_1__PARAM_WRAP_14__SHIFT 0x00000018 +#define SQ_WRAPPING_1__PARAM_WRAP_15__SHIFT 0x0000001c + +// SQ_VS_CONST +#define SQ_VS_CONST__BASE__SHIFT 0x00000000 +#define SQ_VS_CONST__SIZE__SHIFT 0x0000000c + +// SQ_PS_CONST +#define SQ_PS_CONST__BASE__SHIFT 0x00000000 +#define SQ_PS_CONST__SIZE__SHIFT 0x0000000c + +// SQ_CONTEXT_MISC +#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE__SHIFT 0x00000000 +#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY__SHIFT 0x00000001 +#define SQ_CONTEXT_MISC__SC_SAMPLE_CNTL__SHIFT 0x00000002 +#define SQ_CONTEXT_MISC__PARAM_GEN_POS__SHIFT 0x00000008 +#define SQ_CONTEXT_MISC__PERFCOUNTER_REF__SHIFT 0x00000010 +#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE__SHIFT 0x00000011 +#define SQ_CONTEXT_MISC__TX_CACHE_SEL__SHIFT 0x00000012 + +// SQ_CF_RD_BASE +#define SQ_CF_RD_BASE__RD_BASE__SHIFT 0x00000000 + +// SQ_DEBUG_MISC_0 +#define SQ_DEBUG_MISC_0__DB_PROB_ON__SHIFT 0x00000000 +#define SQ_DEBUG_MISC_0__DB_PROB_BREAK__SHIFT 0x00000004 +#define SQ_DEBUG_MISC_0__DB_PROB_ADDR__SHIFT 0x00000008 +#define SQ_DEBUG_MISC_0__DB_PROB_COUNT__SHIFT 0x00000018 + +// SQ_DEBUG_MISC_1 +#define SQ_DEBUG_MISC_1__DB_ON_PIX__SHIFT 0x00000000 +#define SQ_DEBUG_MISC_1__DB_ON_VTX__SHIFT 0x00000001 +#define SQ_DEBUG_MISC_1__DB_INST_COUNT__SHIFT 0x00000008 +#define SQ_DEBUG_MISC_1__DB_BREAK_ADDR__SHIFT 0x00000010 + +// MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG__SAME_PAGE_LIMIT__SHIFT 0x00000000 +#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY__SHIFT 0x00000006 +#define MH_ARBITER_CONFIG__L1_ARB_ENABLE__SHIFT 0x00000007 +#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE__SHIFT 0x00000008 +#define MH_ARBITER_CONFIG__L2_ARB_CONTROL__SHIFT 0x00000009 +#define MH_ARBITER_CONFIG__PAGE_SIZE__SHIFT 0x0000000a +#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE__SHIFT 0x0000000d +#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE__SHIFT 0x0000000e +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE__SHIFT 0x0000000f +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT__SHIFT 0x00000010 +#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE__SHIFT 0x00000016 +#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE__SHIFT 0x00000017 +#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE__SHIFT 0x00000018 +#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE__SHIFT 0x00000019 +#define MH_ARBITER_CONFIG__PA_CLNT_ENABLE__SHIFT 0x0000001a + +// MH_CLNT_AXI_ID_REUSE +#define MH_CLNT_AXI_ID_REUSE__CPw_ID__SHIFT 0x00000000 +#define MH_CLNT_AXI_ID_REUSE__RESERVED1__SHIFT 0x00000003 +#define MH_CLNT_AXI_ID_REUSE__RBw_ID__SHIFT 0x00000004 +#define MH_CLNT_AXI_ID_REUSE__RESERVED2__SHIFT 0x00000007 +#define MH_CLNT_AXI_ID_REUSE__MMUr_ID__SHIFT 0x00000008 +#define MH_CLNT_AXI_ID_REUSE__RESERVED3__SHIFT 0x0000000b +#define MH_CLNT_AXI_ID_REUSE__PAw_ID__SHIFT 0x0000000c + +// MH_INTERRUPT_MASK +#define MH_INTERRUPT_MASK__AXI_READ_ERROR__SHIFT 0x00000000 +#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR__SHIFT 0x00000001 +#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT__SHIFT 0x00000002 + +// MH_INTERRUPT_STATUS +#define MH_INTERRUPT_STATUS__AXI_READ_ERROR__SHIFT 0x00000000 +#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR__SHIFT 0x00000001 +#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT__SHIFT 0x00000002 + +// MH_INTERRUPT_CLEAR +#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR__SHIFT 0x00000000 +#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR__SHIFT 0x00000001 +#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT__SHIFT 0x00000002 + +// MH_AXI_ERROR +#define MH_AXI_ERROR__AXI_READ_ID__SHIFT 0x00000000 +#define MH_AXI_ERROR__AXI_READ_ERROR__SHIFT 0x00000003 +#define MH_AXI_ERROR__AXI_WRITE_ID__SHIFT 0x00000004 +#define MH_AXI_ERROR__AXI_WRITE_ERROR__SHIFT 0x00000007 + +// MH_PERFCOUNTER0_SELECT +#define MH_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// MH_PERFCOUNTER1_SELECT +#define MH_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 + +// MH_PERFCOUNTER0_CONFIG +#define MH_PERFCOUNTER0_CONFIG__N_VALUE__SHIFT 0x00000000 + +// MH_PERFCOUNTER1_CONFIG +#define MH_PERFCOUNTER1_CONFIG__N_VALUE__SHIFT 0x00000000 + +// MH_PERFCOUNTER0_LOW +#define MH_PERFCOUNTER0_LOW__PERF_COUNTER_LOW__SHIFT 0x00000000 + +// MH_PERFCOUNTER1_LOW +#define MH_PERFCOUNTER1_LOW__PERF_COUNTER_LOW__SHIFT 0x00000000 + +// MH_PERFCOUNTER0_HI +#define MH_PERFCOUNTER0_HI__PERF_COUNTER_HI__SHIFT 0x00000000 + +// MH_PERFCOUNTER1_HI +#define MH_PERFCOUNTER1_HI__PERF_COUNTER_HI__SHIFT 0x00000000 + +// MH_DEBUG_CTRL +#define MH_DEBUG_CTRL__INDEX__SHIFT 0x00000000 + +// MH_DEBUG_DATA +#define MH_DEBUG_DATA__DATA__SHIFT 0x00000000 + +// MH_AXI_HALT_CONTROL +#define MH_AXI_HALT_CONTROL__AXI_HALT__SHIFT 0x00000000 + +// MH_DEBUG_REG00 +#define MH_DEBUG_REG00__MH_BUSY__SHIFT 0x00000000 +#define MH_DEBUG_REG00__TRANS_OUTSTANDING__SHIFT 0x00000001 +#define MH_DEBUG_REG00__CP_REQUEST__SHIFT 0x00000002 +#define MH_DEBUG_REG00__VGT_REQUEST__SHIFT 0x00000003 +#define MH_DEBUG_REG00__TC_REQUEST__SHIFT 0x00000004 +#define MH_DEBUG_REG00__TC_CAM_EMPTY__SHIFT 0x00000005 +#define MH_DEBUG_REG00__TC_CAM_FULL__SHIFT 0x00000006 +#define MH_DEBUG_REG00__TCD_EMPTY__SHIFT 0x00000007 +#define MH_DEBUG_REG00__TCD_FULL__SHIFT 0x00000008 +#define MH_DEBUG_REG00__RB_REQUEST__SHIFT 0x00000009 +#define MH_DEBUG_REG00__PA_REQUEST__SHIFT 0x0000000a +#define MH_DEBUG_REG00__MH_CLK_EN_STATE__SHIFT 0x0000000b +#define MH_DEBUG_REG00__ARQ_EMPTY__SHIFT 0x0000000c +#define MH_DEBUG_REG00__ARQ_FULL__SHIFT 0x0000000d +#define MH_DEBUG_REG00__WDB_EMPTY__SHIFT 0x0000000e +#define MH_DEBUG_REG00__WDB_FULL__SHIFT 0x0000000f +#define MH_DEBUG_REG00__AXI_AVALID__SHIFT 0x00000010 +#define MH_DEBUG_REG00__AXI_AREADY__SHIFT 0x00000011 +#define MH_DEBUG_REG00__AXI_ARVALID__SHIFT 0x00000012 +#define MH_DEBUG_REG00__AXI_ARREADY__SHIFT 0x00000013 +#define MH_DEBUG_REG00__AXI_WVALID__SHIFT 0x00000014 +#define MH_DEBUG_REG00__AXI_WREADY__SHIFT 0x00000015 +#define MH_DEBUG_REG00__AXI_RVALID__SHIFT 0x00000016 +#define MH_DEBUG_REG00__AXI_RREADY__SHIFT 0x00000017 +#define MH_DEBUG_REG00__AXI_BVALID__SHIFT 0x00000018 +#define MH_DEBUG_REG00__AXI_BREADY__SHIFT 0x00000019 +#define MH_DEBUG_REG00__AXI_HALT_REQ__SHIFT 0x0000001a +#define MH_DEBUG_REG00__AXI_HALT_ACK__SHIFT 0x0000001b +#define MH_DEBUG_REG00__AXI_RDY_ENA__SHIFT 0x0000001c + +// MH_DEBUG_REG01 +#define MH_DEBUG_REG01__CP_SEND_q__SHIFT 0x00000000 +#define MH_DEBUG_REG01__CP_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG01__CP_WRITE_q__SHIFT 0x00000002 +#define MH_DEBUG_REG01__CP_TAG_q__SHIFT 0x00000003 +#define MH_DEBUG_REG01__CP_BLEN_q__SHIFT 0x00000006 +#define MH_DEBUG_REG01__VGT_SEND_q__SHIFT 0x00000007 +#define MH_DEBUG_REG01__VGT_RTR_q__SHIFT 0x00000008 +#define MH_DEBUG_REG01__VGT_TAG_q__SHIFT 0x00000009 +#define MH_DEBUG_REG01__TC_SEND_q__SHIFT 0x0000000a +#define MH_DEBUG_REG01__TC_RTR_q__SHIFT 0x0000000b +#define MH_DEBUG_REG01__TC_BLEN_q__SHIFT 0x0000000c +#define MH_DEBUG_REG01__TC_ROQ_SEND_q__SHIFT 0x0000000d +#define MH_DEBUG_REG01__TC_ROQ_RTR_q__SHIFT 0x0000000e +#define MH_DEBUG_REG01__TC_MH_written__SHIFT 0x0000000f +#define MH_DEBUG_REG01__RB_SEND_q__SHIFT 0x00000010 +#define MH_DEBUG_REG01__RB_RTR_q__SHIFT 0x00000011 +#define MH_DEBUG_REG01__PA_SEND_q__SHIFT 0x00000012 +#define MH_DEBUG_REG01__PA_RTR_q__SHIFT 0x00000013 + +// MH_DEBUG_REG02 +#define MH_DEBUG_REG02__MH_CP_grb_send__SHIFT 0x00000000 +#define MH_DEBUG_REG02__MH_VGT_grb_send__SHIFT 0x00000001 +#define MH_DEBUG_REG02__MH_TC_mcsend__SHIFT 0x00000002 +#define MH_DEBUG_REG02__MH_CLNT_rlast__SHIFT 0x00000003 +#define MH_DEBUG_REG02__MH_CLNT_tag__SHIFT 0x00000004 +#define MH_DEBUG_REG02__RDC_RID__SHIFT 0x00000007 +#define MH_DEBUG_REG02__RDC_RRESP__SHIFT 0x0000000a +#define MH_DEBUG_REG02__MH_CP_writeclean__SHIFT 0x0000000c +#define MH_DEBUG_REG02__MH_RB_writeclean__SHIFT 0x0000000d +#define MH_DEBUG_REG02__MH_PA_writeclean__SHIFT 0x0000000e +#define MH_DEBUG_REG02__BRC_BID__SHIFT 0x0000000f +#define MH_DEBUG_REG02__BRC_BRESP__SHIFT 0x00000012 + +// MH_DEBUG_REG03 +#define MH_DEBUG_REG03__MH_CLNT_data_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG04 +#define MH_DEBUG_REG04__MH_CLNT_data_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG05 +#define MH_DEBUG_REG05__CP_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG05__CP_MH_write__SHIFT 0x00000001 +#define MH_DEBUG_REG05__CP_MH_tag__SHIFT 0x00000002 +#define MH_DEBUG_REG05__CP_MH_ad_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG06 +#define MH_DEBUG_REG06__CP_MH_data_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG07 +#define MH_DEBUG_REG07__CP_MH_data_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG08 +#define MH_DEBUG_REG08__CP_MH_be__SHIFT 0x00000000 +#define MH_DEBUG_REG08__RB_MH_be__SHIFT 0x00000008 +#define MH_DEBUG_REG08__PA_MH_be__SHIFT 0x00000010 + +// MH_DEBUG_REG09 +#define MH_DEBUG_REG09__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG09__VGT_MH_send__SHIFT 0x00000003 +#define MH_DEBUG_REG09__VGT_MH_tagbe__SHIFT 0x00000004 +#define MH_DEBUG_REG09__VGT_MH_ad_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG10 +#define MH_DEBUG_REG10__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG10__TC_MH_send__SHIFT 0x00000002 +#define MH_DEBUG_REG10__TC_MH_mask__SHIFT 0x00000003 +#define MH_DEBUG_REG10__TC_MH_addr_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG11 +#define MH_DEBUG_REG11__TC_MH_info__SHIFT 0x00000000 +#define MH_DEBUG_REG11__TC_MH_send__SHIFT 0x00000019 + +// MH_DEBUG_REG12 +#define MH_DEBUG_REG12__MH_TC_mcinfo__SHIFT 0x00000000 +#define MH_DEBUG_REG12__MH_TC_mcinfo_send__SHIFT 0x00000019 +#define MH_DEBUG_REG12__TC_MH_written__SHIFT 0x0000001a + +// MH_DEBUG_REG13 +#define MH_DEBUG_REG13__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG13__TC_ROQ_SEND__SHIFT 0x00000002 +#define MH_DEBUG_REG13__TC_ROQ_MASK__SHIFT 0x00000003 +#define MH_DEBUG_REG13__TC_ROQ_ADDR_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG14 +#define MH_DEBUG_REG14__TC_ROQ_INFO__SHIFT 0x00000000 +#define MH_DEBUG_REG14__TC_ROQ_SEND__SHIFT 0x00000019 + +// MH_DEBUG_REG15 +#define MH_DEBUG_REG15__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG15__RB_MH_send__SHIFT 0x00000004 +#define MH_DEBUG_REG15__RB_MH_addr_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG16 +#define MH_DEBUG_REG16__RB_MH_data_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG17 +#define MH_DEBUG_REG17__RB_MH_data_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG18 +#define MH_DEBUG_REG18__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG18__PA_MH_send__SHIFT 0x00000004 +#define MH_DEBUG_REG18__PA_MH_addr_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG19 +#define MH_DEBUG_REG19__PA_MH_data_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG20 +#define MH_DEBUG_REG20__PA_MH_data_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG21 +#define MH_DEBUG_REG21__AVALID_q__SHIFT 0x00000000 +#define MH_DEBUG_REG21__AREADY_q__SHIFT 0x00000001 +#define MH_DEBUG_REG21__AID_q__SHIFT 0x00000002 +#define MH_DEBUG_REG21__ALEN_q_2_0__SHIFT 0x00000005 +#define MH_DEBUG_REG21__ARVALID_q__SHIFT 0x00000008 +#define MH_DEBUG_REG21__ARREADY_q__SHIFT 0x00000009 +#define MH_DEBUG_REG21__ARID_q__SHIFT 0x0000000a +#define MH_DEBUG_REG21__ARLEN_q_1_0__SHIFT 0x0000000d +#define MH_DEBUG_REG21__RVALID_q__SHIFT 0x0000000f +#define MH_DEBUG_REG21__RREADY_q__SHIFT 0x00000010 +#define MH_DEBUG_REG21__RLAST_q__SHIFT 0x00000011 +#define MH_DEBUG_REG21__RID_q__SHIFT 0x00000012 +#define MH_DEBUG_REG21__WVALID_q__SHIFT 0x00000015 +#define MH_DEBUG_REG21__WREADY_q__SHIFT 0x00000016 +#define MH_DEBUG_REG21__WLAST_q__SHIFT 0x00000017 +#define MH_DEBUG_REG21__WID_q__SHIFT 0x00000018 +#define MH_DEBUG_REG21__BVALID_q__SHIFT 0x0000001b +#define MH_DEBUG_REG21__BREADY_q__SHIFT 0x0000001c +#define MH_DEBUG_REG21__BID_q__SHIFT 0x0000001d + +// MH_DEBUG_REG22 +#define MH_DEBUG_REG22__AVALID_q__SHIFT 0x00000000 +#define MH_DEBUG_REG22__AREADY_q__SHIFT 0x00000001 +#define MH_DEBUG_REG22__AID_q__SHIFT 0x00000002 +#define MH_DEBUG_REG22__ALEN_q_1_0__SHIFT 0x00000005 +#define MH_DEBUG_REG22__ARVALID_q__SHIFT 0x00000007 +#define MH_DEBUG_REG22__ARREADY_q__SHIFT 0x00000008 +#define MH_DEBUG_REG22__ARID_q__SHIFT 0x00000009 +#define MH_DEBUG_REG22__ARLEN_q_1_1__SHIFT 0x0000000c +#define MH_DEBUG_REG22__WVALID_q__SHIFT 0x0000000d +#define MH_DEBUG_REG22__WREADY_q__SHIFT 0x0000000e +#define MH_DEBUG_REG22__WLAST_q__SHIFT 0x0000000f +#define MH_DEBUG_REG22__WID_q__SHIFT 0x00000010 +#define MH_DEBUG_REG22__WSTRB_q__SHIFT 0x00000013 +#define MH_DEBUG_REG22__BVALID_q__SHIFT 0x0000001b +#define MH_DEBUG_REG22__BREADY_q__SHIFT 0x0000001c +#define MH_DEBUG_REG22__BID_q__SHIFT 0x0000001d + +// MH_DEBUG_REG23 +#define MH_DEBUG_REG23__ARC_CTRL_RE_q__SHIFT 0x00000000 +#define MH_DEBUG_REG23__CTRL_ARC_ID__SHIFT 0x00000001 +#define MH_DEBUG_REG23__CTRL_ARC_PAD__SHIFT 0x00000004 + +// MH_DEBUG_REG24 +#define MH_DEBUG_REG24__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG24__REG_A__SHIFT 0x00000002 +#define MH_DEBUG_REG24__REG_RE__SHIFT 0x00000010 +#define MH_DEBUG_REG24__REG_WE__SHIFT 0x00000011 +#define MH_DEBUG_REG24__BLOCK_RS__SHIFT 0x00000012 + +// MH_DEBUG_REG25 +#define MH_DEBUG_REG25__REG_WD__SHIFT 0x00000000 + +// MH_DEBUG_REG26 +#define MH_DEBUG_REG26__MH_RBBM_busy__SHIFT 0x00000000 +#define MH_DEBUG_REG26__MH_CIB_mh_clk_en_int__SHIFT 0x00000001 +#define MH_DEBUG_REG26__MH_CIB_mmu_clk_en_int__SHIFT 0x00000002 +#define MH_DEBUG_REG26__MH_CIB_tcroq_clk_en_int__SHIFT 0x00000003 +#define MH_DEBUG_REG26__GAT_CLK_ENA__SHIFT 0x00000004 +#define MH_DEBUG_REG26__RBBM_MH_clk_en_override__SHIFT 0x00000005 +#define MH_DEBUG_REG26__CNT_q__SHIFT 0x00000006 +#define MH_DEBUG_REG26__TCD_EMPTY_q__SHIFT 0x0000000c +#define MH_DEBUG_REG26__TC_ROQ_EMPTY__SHIFT 0x0000000d +#define MH_DEBUG_REG26__MH_BUSY_d__SHIFT 0x0000000e +#define MH_DEBUG_REG26__ANY_CLNT_BUSY__SHIFT 0x0000000f +#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_ALL__SHIFT 0x00000010 +#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_TC__SHIFT 0x00000011 +#define MH_DEBUG_REG26__CP_SEND_q__SHIFT 0x00000012 +#define MH_DEBUG_REG26__CP_RTR_q__SHIFT 0x00000013 +#define MH_DEBUG_REG26__VGT_SEND_q__SHIFT 0x00000014 +#define MH_DEBUG_REG26__VGT_RTR_q__SHIFT 0x00000015 +#define MH_DEBUG_REG26__TC_ROQ_SEND_q__SHIFT 0x00000016 +#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q__SHIFT 0x00000017 +#define MH_DEBUG_REG26__RB_SEND_q__SHIFT 0x00000018 +#define MH_DEBUG_REG26__RB_RTR_q__SHIFT 0x00000019 +#define MH_DEBUG_REG26__PA_SEND_q__SHIFT 0x0000001a +#define MH_DEBUG_REG26__PA_RTR_q__SHIFT 0x0000001b +#define MH_DEBUG_REG26__RDC_VALID__SHIFT 0x0000001c +#define MH_DEBUG_REG26__RDC_RLAST__SHIFT 0x0000001d +#define MH_DEBUG_REG26__TLBMISS_VALID__SHIFT 0x0000001e +#define MH_DEBUG_REG26__BRC_VALID__SHIFT 0x0000001f + +// MH_DEBUG_REG27 +#define MH_DEBUG_REG27__EFF2_FP_WINNER__SHIFT 0x00000000 +#define MH_DEBUG_REG27__EFF2_LRU_WINNER_out__SHIFT 0x00000003 +#define MH_DEBUG_REG27__EFF1_WINNER__SHIFT 0x00000006 +#define MH_DEBUG_REG27__ARB_WINNER__SHIFT 0x00000009 +#define MH_DEBUG_REG27__ARB_WINNER_q__SHIFT 0x0000000c +#define MH_DEBUG_REG27__EFF1_WIN__SHIFT 0x0000000f +#define MH_DEBUG_REG27__KILL_EFF1__SHIFT 0x00000010 +#define MH_DEBUG_REG27__ARB_HOLD__SHIFT 0x00000011 +#define MH_DEBUG_REG27__ARB_RTR_q__SHIFT 0x00000012 +#define MH_DEBUG_REG27__CP_SEND_QUAL__SHIFT 0x00000013 +#define MH_DEBUG_REG27__VGT_SEND_QUAL__SHIFT 0x00000014 +#define MH_DEBUG_REG27__TC_SEND_QUAL__SHIFT 0x00000015 +#define MH_DEBUG_REG27__TC_SEND_EFF1_QUAL__SHIFT 0x00000016 +#define MH_DEBUG_REG27__RB_SEND_QUAL__SHIFT 0x00000017 +#define MH_DEBUG_REG27__PA_SEND_QUAL__SHIFT 0x00000018 +#define MH_DEBUG_REG27__ARB_QUAL__SHIFT 0x00000019 +#define MH_DEBUG_REG27__CP_EFF1_REQ__SHIFT 0x0000001a +#define MH_DEBUG_REG27__VGT_EFF1_REQ__SHIFT 0x0000001b +#define MH_DEBUG_REG27__TC_EFF1_REQ__SHIFT 0x0000001c +#define MH_DEBUG_REG27__RB_EFF1_REQ__SHIFT 0x0000001d +#define MH_DEBUG_REG27__TCD_NEARFULL_q__SHIFT 0x0000001e +#define MH_DEBUG_REG27__TCHOLD_IP_q__SHIFT 0x0000001f + +// MH_DEBUG_REG28 +#define MH_DEBUG_REG28__EFF1_WINNER__SHIFT 0x00000000 +#define MH_DEBUG_REG28__ARB_WINNER__SHIFT 0x00000003 +#define MH_DEBUG_REG28__CP_SEND_QUAL__SHIFT 0x00000006 +#define MH_DEBUG_REG28__VGT_SEND_QUAL__SHIFT 0x00000007 +#define MH_DEBUG_REG28__TC_SEND_QUAL__SHIFT 0x00000008 +#define MH_DEBUG_REG28__TC_SEND_EFF1_QUAL__SHIFT 0x00000009 +#define MH_DEBUG_REG28__RB_SEND_QUAL__SHIFT 0x0000000a +#define MH_DEBUG_REG28__ARB_QUAL__SHIFT 0x0000000b +#define MH_DEBUG_REG28__CP_EFF1_REQ__SHIFT 0x0000000c +#define MH_DEBUG_REG28__VGT_EFF1_REQ__SHIFT 0x0000000d +#define MH_DEBUG_REG28__TC_EFF1_REQ__SHIFT 0x0000000e +#define MH_DEBUG_REG28__RB_EFF1_REQ__SHIFT 0x0000000f +#define MH_DEBUG_REG28__EFF1_WIN__SHIFT 0x00000010 +#define MH_DEBUG_REG28__KILL_EFF1__SHIFT 0x00000011 +#define MH_DEBUG_REG28__TCD_NEARFULL_q__SHIFT 0x00000012 +#define MH_DEBUG_REG28__TC_ARB_HOLD__SHIFT 0x00000013 +#define MH_DEBUG_REG28__ARB_HOLD__SHIFT 0x00000014 +#define MH_DEBUG_REG28__ARB_RTR_q__SHIFT 0x00000015 +#define MH_DEBUG_REG28__SAME_PAGE_LIMIT_COUNT_q__SHIFT 0x00000016 + +// MH_DEBUG_REG29 +#define MH_DEBUG_REG29__EFF2_LRU_WINNER_out__SHIFT 0x00000000 +#define MH_DEBUG_REG29__LEAST_RECENT_INDEX_d__SHIFT 0x00000003 +#define MH_DEBUG_REG29__LEAST_RECENT_d__SHIFT 0x00000006 +#define MH_DEBUG_REG29__UPDATE_RECENT_STACK_d__SHIFT 0x00000009 +#define MH_DEBUG_REG29__ARB_HOLD__SHIFT 0x0000000a +#define MH_DEBUG_REG29__ARB_RTR_q__SHIFT 0x0000000b +#define MH_DEBUG_REG29__CLNT_REQ__SHIFT 0x0000000c +#define MH_DEBUG_REG29__RECENT_d_0__SHIFT 0x00000011 +#define MH_DEBUG_REG29__RECENT_d_1__SHIFT 0x00000014 +#define MH_DEBUG_REG29__RECENT_d_2__SHIFT 0x00000017 +#define MH_DEBUG_REG29__RECENT_d_3__SHIFT 0x0000001a +#define MH_DEBUG_REG29__RECENT_d_4__SHIFT 0x0000001d + +// MH_DEBUG_REG30 +#define MH_DEBUG_REG30__TC_ARB_HOLD__SHIFT 0x00000000 +#define MH_DEBUG_REG30__TC_NOROQ_SAME_ROW_BANK__SHIFT 0x00000001 +#define MH_DEBUG_REG30__TC_ROQ_SAME_ROW_BANK__SHIFT 0x00000002 +#define MH_DEBUG_REG30__TCD_NEARFULL_q__SHIFT 0x00000003 +#define MH_DEBUG_REG30__TCHOLD_IP_q__SHIFT 0x00000004 +#define MH_DEBUG_REG30__TCHOLD_CNT_q__SHIFT 0x00000005 +#define MH_DEBUG_REG30__MH_ARBITER_CONFIG_TC_REORDER_ENABLE__SHIFT 0x00000008 +#define MH_DEBUG_REG30__TC_ROQ_RTR_DBG_q__SHIFT 0x00000009 +#define MH_DEBUG_REG30__TC_ROQ_SEND_q__SHIFT 0x0000000a +#define MH_DEBUG_REG30__TC_MH_written__SHIFT 0x0000000b +#define MH_DEBUG_REG30__TCD_FULLNESS_CNT_q__SHIFT 0x0000000c +#define MH_DEBUG_REG30__WBURST_ACTIVE__SHIFT 0x00000013 +#define MH_DEBUG_REG30__WLAST_q__SHIFT 0x00000014 +#define MH_DEBUG_REG30__WBURST_IP_q__SHIFT 0x00000015 +#define MH_DEBUG_REG30__WBURST_CNT_q__SHIFT 0x00000016 +#define MH_DEBUG_REG30__CP_SEND_QUAL__SHIFT 0x00000019 +#define MH_DEBUG_REG30__CP_MH_write__SHIFT 0x0000001a +#define MH_DEBUG_REG30__RB_SEND_QUAL__SHIFT 0x0000001b +#define MH_DEBUG_REG30__PA_SEND_QUAL__SHIFT 0x0000001c +#define MH_DEBUG_REG30__ARB_WINNER__SHIFT 0x0000001d + +// MH_DEBUG_REG31 +#define MH_DEBUG_REG31__RF_ARBITER_CONFIG_q__SHIFT 0x00000000 +#define MH_DEBUG_REG31__MH_CLNT_AXI_ID_REUSE_MMUr_ID__SHIFT 0x0000001a + +// MH_DEBUG_REG32 +#define MH_DEBUG_REG32__SAME_ROW_BANK_q__SHIFT 0x00000000 +#define MH_DEBUG_REG32__ROQ_MARK_q__SHIFT 0x00000008 +#define MH_DEBUG_REG32__ROQ_VALID_q__SHIFT 0x00000010 +#define MH_DEBUG_REG32__TC_MH_send__SHIFT 0x00000018 +#define MH_DEBUG_REG32__TC_ROQ_RTR_q__SHIFT 0x00000019 +#define MH_DEBUG_REG32__KILL_EFF1__SHIFT 0x0000001a +#define MH_DEBUG_REG32__TC_ROQ_SAME_ROW_BANK_SEL__SHIFT 0x0000001b +#define MH_DEBUG_REG32__ANY_SAME_ROW_BANK__SHIFT 0x0000001c +#define MH_DEBUG_REG32__TC_EFF1_QUAL__SHIFT 0x0000001d +#define MH_DEBUG_REG32__TC_ROQ_EMPTY__SHIFT 0x0000001e +#define MH_DEBUG_REG32__TC_ROQ_FULL__SHIFT 0x0000001f + +// MH_DEBUG_REG33 +#define MH_DEBUG_REG33__SAME_ROW_BANK_q__SHIFT 0x00000000 +#define MH_DEBUG_REG33__ROQ_MARK_d__SHIFT 0x00000008 +#define MH_DEBUG_REG33__ROQ_VALID_d__SHIFT 0x00000010 +#define MH_DEBUG_REG33__TC_MH_send__SHIFT 0x00000018 +#define MH_DEBUG_REG33__TC_ROQ_RTR_q__SHIFT 0x00000019 +#define MH_DEBUG_REG33__KILL_EFF1__SHIFT 0x0000001a +#define MH_DEBUG_REG33__TC_ROQ_SAME_ROW_BANK_SEL__SHIFT 0x0000001b +#define MH_DEBUG_REG33__ANY_SAME_ROW_BANK__SHIFT 0x0000001c +#define MH_DEBUG_REG33__TC_EFF1_QUAL__SHIFT 0x0000001d +#define MH_DEBUG_REG33__TC_ROQ_EMPTY__SHIFT 0x0000001e +#define MH_DEBUG_REG33__TC_ROQ_FULL__SHIFT 0x0000001f + +// MH_DEBUG_REG34 +#define MH_DEBUG_REG34__SAME_ROW_BANK_WIN__SHIFT 0x00000000 +#define MH_DEBUG_REG34__SAME_ROW_BANK_REQ__SHIFT 0x00000008 +#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_WIN__SHIFT 0x00000010 +#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_REQ__SHIFT 0x00000018 + +// MH_DEBUG_REG35 +#define MH_DEBUG_REG35__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG35__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG35__ROQ_MARK_q_0__SHIFT 0x00000002 +#define MH_DEBUG_REG35__ROQ_VALID_q_0__SHIFT 0x00000003 +#define MH_DEBUG_REG35__SAME_ROW_BANK_q_0__SHIFT 0x00000004 +#define MH_DEBUG_REG35__ROQ_ADDR_0__SHIFT 0x00000005 + +// MH_DEBUG_REG36 +#define MH_DEBUG_REG36__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG36__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG36__ROQ_MARK_q_1__SHIFT 0x00000002 +#define MH_DEBUG_REG36__ROQ_VALID_q_1__SHIFT 0x00000003 +#define MH_DEBUG_REG36__SAME_ROW_BANK_q_1__SHIFT 0x00000004 +#define MH_DEBUG_REG36__ROQ_ADDR_1__SHIFT 0x00000005 + +// MH_DEBUG_REG37 +#define MH_DEBUG_REG37__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG37__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG37__ROQ_MARK_q_2__SHIFT 0x00000002 +#define MH_DEBUG_REG37__ROQ_VALID_q_2__SHIFT 0x00000003 +#define MH_DEBUG_REG37__SAME_ROW_BANK_q_2__SHIFT 0x00000004 +#define MH_DEBUG_REG37__ROQ_ADDR_2__SHIFT 0x00000005 + +// MH_DEBUG_REG38 +#define MH_DEBUG_REG38__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG38__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG38__ROQ_MARK_q_3__SHIFT 0x00000002 +#define MH_DEBUG_REG38__ROQ_VALID_q_3__SHIFT 0x00000003 +#define MH_DEBUG_REG38__SAME_ROW_BANK_q_3__SHIFT 0x00000004 +#define MH_DEBUG_REG38__ROQ_ADDR_3__SHIFT 0x00000005 + +// MH_DEBUG_REG39 +#define MH_DEBUG_REG39__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG39__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG39__ROQ_MARK_q_4__SHIFT 0x00000002 +#define MH_DEBUG_REG39__ROQ_VALID_q_4__SHIFT 0x00000003 +#define MH_DEBUG_REG39__SAME_ROW_BANK_q_4__SHIFT 0x00000004 +#define MH_DEBUG_REG39__ROQ_ADDR_4__SHIFT 0x00000005 + +// MH_DEBUG_REG40 +#define MH_DEBUG_REG40__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG40__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG40__ROQ_MARK_q_5__SHIFT 0x00000002 +#define MH_DEBUG_REG40__ROQ_VALID_q_5__SHIFT 0x00000003 +#define MH_DEBUG_REG40__SAME_ROW_BANK_q_5__SHIFT 0x00000004 +#define MH_DEBUG_REG40__ROQ_ADDR_5__SHIFT 0x00000005 + +// MH_DEBUG_REG41 +#define MH_DEBUG_REG41__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG41__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG41__ROQ_MARK_q_6__SHIFT 0x00000002 +#define MH_DEBUG_REG41__ROQ_VALID_q_6__SHIFT 0x00000003 +#define MH_DEBUG_REG41__SAME_ROW_BANK_q_6__SHIFT 0x00000004 +#define MH_DEBUG_REG41__ROQ_ADDR_6__SHIFT 0x00000005 + +// MH_DEBUG_REG42 +#define MH_DEBUG_REG42__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG42__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG42__ROQ_MARK_q_7__SHIFT 0x00000002 +#define MH_DEBUG_REG42__ROQ_VALID_q_7__SHIFT 0x00000003 +#define MH_DEBUG_REG42__SAME_ROW_BANK_q_7__SHIFT 0x00000004 +#define MH_DEBUG_REG42__ROQ_ADDR_7__SHIFT 0x00000005 + +// MH_DEBUG_REG43 +#define MH_DEBUG_REG43__ARB_REG_WE_q__SHIFT 0x00000000 +#define MH_DEBUG_REG43__ARB_WE__SHIFT 0x00000001 +#define MH_DEBUG_REG43__ARB_REG_VALID_q__SHIFT 0x00000002 +#define MH_DEBUG_REG43__ARB_RTR_q__SHIFT 0x00000003 +#define MH_DEBUG_REG43__ARB_REG_RTR__SHIFT 0x00000004 +#define MH_DEBUG_REG43__WDAT_BURST_RTR__SHIFT 0x00000005 +#define MH_DEBUG_REG43__MMU_RTR__SHIFT 0x00000006 +#define MH_DEBUG_REG43__ARB_ID_q__SHIFT 0x00000007 +#define MH_DEBUG_REG43__ARB_WRITE_q__SHIFT 0x0000000a +#define MH_DEBUG_REG43__ARB_BLEN_q__SHIFT 0x0000000b +#define MH_DEBUG_REG43__ARQ_CTRL_EMPTY__SHIFT 0x0000000c +#define MH_DEBUG_REG43__ARQ_FIFO_CNT_q__SHIFT 0x0000000d +#define MH_DEBUG_REG43__MMU_WE__SHIFT 0x00000010 +#define MH_DEBUG_REG43__ARQ_RTR__SHIFT 0x00000011 +#define MH_DEBUG_REG43__MMU_ID__SHIFT 0x00000012 +#define MH_DEBUG_REG43__MMU_WRITE__SHIFT 0x00000015 +#define MH_DEBUG_REG43__MMU_BLEN__SHIFT 0x00000016 +#define MH_DEBUG_REG43__WBURST_IP_q__SHIFT 0x00000017 +#define MH_DEBUG_REG43__WDAT_REG_WE_q__SHIFT 0x00000018 +#define MH_DEBUG_REG43__WDB_WE__SHIFT 0x00000019 +#define MH_DEBUG_REG43__WDB_RTR_SKID_4__SHIFT 0x0000001a +#define MH_DEBUG_REG43__WDB_RTR_SKID_3__SHIFT 0x0000001b + +// MH_DEBUG_REG44 +#define MH_DEBUG_REG44__ARB_WE__SHIFT 0x00000000 +#define MH_DEBUG_REG44__ARB_ID_q__SHIFT 0x00000001 +#define MH_DEBUG_REG44__ARB_VAD_q__SHIFT 0x00000004 + +// MH_DEBUG_REG45 +#define MH_DEBUG_REG45__MMU_WE__SHIFT 0x00000000 +#define MH_DEBUG_REG45__MMU_ID__SHIFT 0x00000001 +#define MH_DEBUG_REG45__MMU_PAD__SHIFT 0x00000004 + +// MH_DEBUG_REG46 +#define MH_DEBUG_REG46__WDAT_REG_WE_q__SHIFT 0x00000000 +#define MH_DEBUG_REG46__WDB_WE__SHIFT 0x00000001 +#define MH_DEBUG_REG46__WDAT_REG_VALID_q__SHIFT 0x00000002 +#define MH_DEBUG_REG46__WDB_RTR_SKID_4__SHIFT 0x00000003 +#define MH_DEBUG_REG46__ARB_WSTRB_q__SHIFT 0x00000004 +#define MH_DEBUG_REG46__ARB_WLAST__SHIFT 0x0000000c +#define MH_DEBUG_REG46__WDB_CTRL_EMPTY__SHIFT 0x0000000d +#define MH_DEBUG_REG46__WDB_FIFO_CNT_q__SHIFT 0x0000000e +#define MH_DEBUG_REG46__WDC_WDB_RE_q__SHIFT 0x00000013 +#define MH_DEBUG_REG46__WDB_WDC_WID__SHIFT 0x00000014 +#define MH_DEBUG_REG46__WDB_WDC_WLAST__SHIFT 0x00000017 +#define MH_DEBUG_REG46__WDB_WDC_WSTRB__SHIFT 0x00000018 + +// MH_DEBUG_REG47 +#define MH_DEBUG_REG47__WDB_WDC_WDATA_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG48 +#define MH_DEBUG_REG48__WDB_WDC_WDATA_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG49 +#define MH_DEBUG_REG49__CTRL_ARC_EMPTY__SHIFT 0x00000000 +#define MH_DEBUG_REG49__CTRL_RARC_EMPTY__SHIFT 0x00000001 +#define MH_DEBUG_REG49__ARQ_CTRL_EMPTY__SHIFT 0x00000002 +#define MH_DEBUG_REG49__ARQ_CTRL_WRITE__SHIFT 0x00000003 +#define MH_DEBUG_REG49__TLBMISS_CTRL_RTS__SHIFT 0x00000004 +#define MH_DEBUG_REG49__CTRL_TLBMISS_RE_q__SHIFT 0x00000005 +#define MH_DEBUG_REG49__INFLT_LIMIT_q__SHIFT 0x00000006 +#define MH_DEBUG_REG49__INFLT_LIMIT_CNT_q__SHIFT 0x00000007 +#define MH_DEBUG_REG49__ARC_CTRL_RE_q__SHIFT 0x0000000d +#define MH_DEBUG_REG49__RARC_CTRL_RE_q__SHIFT 0x0000000e +#define MH_DEBUG_REG49__RVALID_q__SHIFT 0x0000000f +#define MH_DEBUG_REG49__RREADY_q__SHIFT 0x00000010 +#define MH_DEBUG_REG49__RLAST_q__SHIFT 0x00000011 +#define MH_DEBUG_REG49__BVALID_q__SHIFT 0x00000012 +#define MH_DEBUG_REG49__BREADY_q__SHIFT 0x00000013 + +// MH_DEBUG_REG50 +#define MH_DEBUG_REG50__MH_CP_grb_send__SHIFT 0x00000000 +#define MH_DEBUG_REG50__MH_VGT_grb_send__SHIFT 0x00000001 +#define MH_DEBUG_REG50__MH_TC_mcsend__SHIFT 0x00000002 +#define MH_DEBUG_REG50__MH_TLBMISS_SEND__SHIFT 0x00000003 +#define MH_DEBUG_REG50__TLBMISS_VALID__SHIFT 0x00000004 +#define MH_DEBUG_REG50__RDC_VALID__SHIFT 0x00000005 +#define MH_DEBUG_REG50__RDC_RID__SHIFT 0x00000006 +#define MH_DEBUG_REG50__RDC_RLAST__SHIFT 0x00000009 +#define MH_DEBUG_REG50__RDC_RRESP__SHIFT 0x0000000a +#define MH_DEBUG_REG50__TLBMISS_CTRL_RTS__SHIFT 0x0000000c +#define MH_DEBUG_REG50__CTRL_TLBMISS_RE_q__SHIFT 0x0000000d +#define MH_DEBUG_REG50__MMU_ID_REQUEST_q__SHIFT 0x0000000e +#define MH_DEBUG_REG50__OUTSTANDING_MMUID_CNT_q__SHIFT 0x0000000f +#define MH_DEBUG_REG50__MMU_ID_RESPONSE__SHIFT 0x00000015 +#define MH_DEBUG_REG50__TLBMISS_RETURN_CNT_q__SHIFT 0x00000016 +#define MH_DEBUG_REG50__CNT_HOLD_q1__SHIFT 0x0000001c +#define MH_DEBUG_REG50__MH_CLNT_AXI_ID_REUSE_MMUr_ID__SHIFT 0x0000001d + +// MH_DEBUG_REG51 +#define MH_DEBUG_REG51__RF_MMU_PAGE_FAULT__SHIFT 0x00000000 + +// MH_DEBUG_REG52 +#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_1_to_0__SHIFT 0x00000000 +#define MH_DEBUG_REG52__ARB_WE__SHIFT 0x00000002 +#define MH_DEBUG_REG52__MMU_RTR__SHIFT 0x00000003 +#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_25_to_4__SHIFT 0x00000004 +#define MH_DEBUG_REG52__ARB_ID_q__SHIFT 0x0000001a +#define MH_DEBUG_REG52__ARB_WRITE_q__SHIFT 0x0000001d +#define MH_DEBUG_REG52__client_behavior_q__SHIFT 0x0000001e + +// MH_DEBUG_REG53 +#define MH_DEBUG_REG53__stage1_valid__SHIFT 0x00000000 +#define MH_DEBUG_REG53__IGNORE_TAG_MISS_q__SHIFT 0x00000001 +#define MH_DEBUG_REG53__pa_in_mpu_range__SHIFT 0x00000002 +#define MH_DEBUG_REG53__tag_match_q__SHIFT 0x00000003 +#define MH_DEBUG_REG53__tag_miss_q__SHIFT 0x00000004 +#define MH_DEBUG_REG53__va_in_range_q__SHIFT 0x00000005 +#define MH_DEBUG_REG53__MMU_MISS__SHIFT 0x00000006 +#define MH_DEBUG_REG53__MMU_READ_MISS__SHIFT 0x00000007 +#define MH_DEBUG_REG53__MMU_WRITE_MISS__SHIFT 0x00000008 +#define MH_DEBUG_REG53__MMU_HIT__SHIFT 0x00000009 +#define MH_DEBUG_REG53__MMU_READ_HIT__SHIFT 0x0000000a +#define MH_DEBUG_REG53__MMU_WRITE_HIT__SHIFT 0x0000000b +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_MISS__SHIFT 0x0000000c +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_HIT__SHIFT 0x0000000d +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_MISS__SHIFT 0x0000000e +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_HIT__SHIFT 0x0000000f +#define MH_DEBUG_REG53__REQ_VA_OFFSET_q__SHIFT 0x00000010 + +// MH_DEBUG_REG54 +#define MH_DEBUG_REG54__ARQ_RTR__SHIFT 0x00000000 +#define MH_DEBUG_REG54__MMU_WE__SHIFT 0x00000001 +#define MH_DEBUG_REG54__CTRL_TLBMISS_RE_q__SHIFT 0x00000002 +#define MH_DEBUG_REG54__TLBMISS_CTRL_RTS__SHIFT 0x00000003 +#define MH_DEBUG_REG54__MH_TLBMISS_SEND__SHIFT 0x00000004 +#define MH_DEBUG_REG54__MMU_STALL_AWAITING_TLB_MISS_FETCH__SHIFT 0x00000005 +#define MH_DEBUG_REG54__pa_in_mpu_range__SHIFT 0x00000006 +#define MH_DEBUG_REG54__stage1_valid__SHIFT 0x00000007 +#define MH_DEBUG_REG54__stage2_valid__SHIFT 0x00000008 +#define MH_DEBUG_REG54__client_behavior_q__SHIFT 0x00000009 +#define MH_DEBUG_REG54__IGNORE_TAG_MISS_q__SHIFT 0x0000000b +#define MH_DEBUG_REG54__tag_match_q__SHIFT 0x0000000c +#define MH_DEBUG_REG54__tag_miss_q__SHIFT 0x0000000d +#define MH_DEBUG_REG54__va_in_range_q__SHIFT 0x0000000e +#define MH_DEBUG_REG54__PTE_FETCH_COMPLETE_q__SHIFT 0x0000000f +#define MH_DEBUG_REG54__TAG_valid_q__SHIFT 0x00000010 + +// MH_DEBUG_REG55 +#define MH_DEBUG_REG55__TAG0_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG55__TAG_valid_q_0__SHIFT 0x0000000d +#define MH_DEBUG_REG55__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG55__TAG1_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG55__TAG_valid_q_1__SHIFT 0x0000001d + +// MH_DEBUG_REG56 +#define MH_DEBUG_REG56__TAG2_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG56__TAG_valid_q_2__SHIFT 0x0000000d +#define MH_DEBUG_REG56__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG56__TAG3_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG56__TAG_valid_q_3__SHIFT 0x0000001d + +// MH_DEBUG_REG57 +#define MH_DEBUG_REG57__TAG4_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG57__TAG_valid_q_4__SHIFT 0x0000000d +#define MH_DEBUG_REG57__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG57__TAG5_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG57__TAG_valid_q_5__SHIFT 0x0000001d + +// MH_DEBUG_REG58 +#define MH_DEBUG_REG58__TAG6_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG58__TAG_valid_q_6__SHIFT 0x0000000d +#define MH_DEBUG_REG58__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG58__TAG7_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG58__TAG_valid_q_7__SHIFT 0x0000001d + +// MH_DEBUG_REG59 +#define MH_DEBUG_REG59__TAG8_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG59__TAG_valid_q_8__SHIFT 0x0000000d +#define MH_DEBUG_REG59__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG59__TAG9_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG59__TAG_valid_q_9__SHIFT 0x0000001d + +// MH_DEBUG_REG60 +#define MH_DEBUG_REG60__TAG10_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG60__TAG_valid_q_10__SHIFT 0x0000000d +#define MH_DEBUG_REG60__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG60__TAG11_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG60__TAG_valid_q_11__SHIFT 0x0000001d + +// MH_DEBUG_REG61 +#define MH_DEBUG_REG61__TAG12_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG61__TAG_valid_q_12__SHIFT 0x0000000d +#define MH_DEBUG_REG61__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG61__TAG13_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG61__TAG_valid_q_13__SHIFT 0x0000001d + +// MH_DEBUG_REG62 +#define MH_DEBUG_REG62__TAG14_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG62__TAG_valid_q_14__SHIFT 0x0000000d +#define MH_DEBUG_REG62__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG62__TAG15_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG62__TAG_valid_q_15__SHIFT 0x0000001d + +// MH_DEBUG_REG63 +#define MH_DEBUG_REG63__MH_DBG_DEFAULT__SHIFT 0x00000000 + +// MH_MMU_CONFIG +#define MH_MMU_CONFIG__MMU_ENABLE__SHIFT 0x00000000 +#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE__SHIFT 0x00000001 +#define MH_MMU_CONFIG__RESERVED1__SHIFT 0x00000002 +#define MH_MMU_CONFIG__RB_W_CLNT_BEHAVIOR__SHIFT 0x00000004 +#define MH_MMU_CONFIG__CP_W_CLNT_BEHAVIOR__SHIFT 0x00000006 +#define MH_MMU_CONFIG__CP_R0_CLNT_BEHAVIOR__SHIFT 0x00000008 +#define MH_MMU_CONFIG__CP_R1_CLNT_BEHAVIOR__SHIFT 0x0000000a +#define MH_MMU_CONFIG__CP_R2_CLNT_BEHAVIOR__SHIFT 0x0000000c +#define MH_MMU_CONFIG__CP_R3_CLNT_BEHAVIOR__SHIFT 0x0000000e +#define MH_MMU_CONFIG__CP_R4_CLNT_BEHAVIOR__SHIFT 0x00000010 +#define MH_MMU_CONFIG__VGT_R0_CLNT_BEHAVIOR__SHIFT 0x00000012 +#define MH_MMU_CONFIG__VGT_R1_CLNT_BEHAVIOR__SHIFT 0x00000014 +#define MH_MMU_CONFIG__TC_R_CLNT_BEHAVIOR__SHIFT 0x00000016 +#define MH_MMU_CONFIG__PA_W_CLNT_BEHAVIOR__SHIFT 0x00000018 + +// MH_MMU_VA_RANGE +#define MH_MMU_VA_RANGE__NUM_64KB_REGIONS__SHIFT 0x00000000 +#define MH_MMU_VA_RANGE__VA_BASE__SHIFT 0x0000000c + +// MH_MMU_PT_BASE +#define MH_MMU_PT_BASE__PT_BASE__SHIFT 0x0000000c + +// MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT__PAGE_FAULT__SHIFT 0x00000000 +#define MH_MMU_PAGE_FAULT__OP_TYPE__SHIFT 0x00000001 +#define MH_MMU_PAGE_FAULT__CLNT_BEHAVIOR__SHIFT 0x00000002 +#define MH_MMU_PAGE_FAULT__AXI_ID__SHIFT 0x00000004 +#define MH_MMU_PAGE_FAULT__RESERVED1__SHIFT 0x00000007 +#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE__SHIFT 0x00000008 +#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE__SHIFT 0x00000009 +#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR__SHIFT 0x0000000a +#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR__SHIFT 0x0000000b +#define MH_MMU_PAGE_FAULT__REQ_VA__SHIFT 0x0000000c + +// MH_MMU_TRAN_ERROR +#define MH_MMU_TRAN_ERROR__TRAN_ERROR__SHIFT 0x00000005 + +// MH_MMU_INVALIDATE +#define MH_MMU_INVALIDATE__INVALIDATE_ALL__SHIFT 0x00000000 +#define MH_MMU_INVALIDATE__INVALIDATE_TC__SHIFT 0x00000001 + +// MH_MMU_MPU_BASE +#define MH_MMU_MPU_BASE__MPU_BASE__SHIFT 0x0000000c + +// MH_MMU_MPU_END +#define MH_MMU_MPU_END__MPU_END__SHIFT 0x0000000c + +// WAIT_UNTIL +#define WAIT_UNTIL__WAIT_RE_VSYNC__SHIFT 0x00000001 +#define WAIT_UNTIL__WAIT_FE_VSYNC__SHIFT 0x00000002 +#define WAIT_UNTIL__WAIT_VSYNC__SHIFT 0x00000003 +#define WAIT_UNTIL__WAIT_DSPLY_ID0__SHIFT 0x00000004 +#define WAIT_UNTIL__WAIT_DSPLY_ID1__SHIFT 0x00000005 +#define WAIT_UNTIL__WAIT_DSPLY_ID2__SHIFT 0x00000006 +#define WAIT_UNTIL__WAIT_CMDFIFO__SHIFT 0x0000000a +#define WAIT_UNTIL__WAIT_2D_IDLE__SHIFT 0x0000000e +#define WAIT_UNTIL__WAIT_3D_IDLE__SHIFT 0x0000000f +#define WAIT_UNTIL__WAIT_2D_IDLECLEAN__SHIFT 0x00000010 +#define WAIT_UNTIL__WAIT_3D_IDLECLEAN__SHIFT 0x00000011 +#define WAIT_UNTIL__CMDFIFO_ENTRIES__SHIFT 0x00000014 + +// RBBM_ISYNC_CNTL +#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI__SHIFT 0x00000004 +#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI__SHIFT 0x00000005 + +// RBBM_STATUS +#define RBBM_STATUS__CMDFIFO_AVAIL__SHIFT 0x00000000 +#define RBBM_STATUS__TC_BUSY__SHIFT 0x00000005 +#define RBBM_STATUS__HIRQ_PENDING__SHIFT 0x00000008 +#define RBBM_STATUS__CPRQ_PENDING__SHIFT 0x00000009 +#define RBBM_STATUS__CFRQ_PENDING__SHIFT 0x0000000a +#define RBBM_STATUS__PFRQ_PENDING__SHIFT 0x0000000b +#define RBBM_STATUS__VGT_BUSY_NO_DMA__SHIFT 0x0000000c +#define RBBM_STATUS__RBBM_WU_BUSY__SHIFT 0x0000000e +#define RBBM_STATUS__CP_NRT_BUSY__SHIFT 0x00000010 +#define RBBM_STATUS__MH_BUSY__SHIFT 0x00000012 +#define RBBM_STATUS__MH_COHERENCY_BUSY__SHIFT 0x00000013 +#define RBBM_STATUS__SX_BUSY__SHIFT 0x00000015 +#define RBBM_STATUS__TPC_BUSY__SHIFT 0x00000016 +#define RBBM_STATUS__SC_CNTX_BUSY__SHIFT 0x00000018 +#define RBBM_STATUS__PA_BUSY__SHIFT 0x00000019 +#define RBBM_STATUS__VGT_BUSY__SHIFT 0x0000001a +#define RBBM_STATUS__SQ_CNTX17_BUSY__SHIFT 0x0000001b +#define RBBM_STATUS__SQ_CNTX0_BUSY__SHIFT 0x0000001c +#define RBBM_STATUS__RB_CNTX_BUSY__SHIFT 0x0000001e +#define RBBM_STATUS__GUI_ACTIVE__SHIFT 0x0000001f + +// RBBM_DSPLY +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID0__SHIFT 0x00000000 +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID1__SHIFT 0x00000001 +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID2__SHIFT 0x00000002 +#define RBBM_DSPLY__SEL_DMI_VSYNC_VALID__SHIFT 0x00000003 +#define RBBM_DSPLY__DMI_CH1_USE_BUFID0__SHIFT 0x00000004 +#define RBBM_DSPLY__DMI_CH1_USE_BUFID1__SHIFT 0x00000005 +#define RBBM_DSPLY__DMI_CH1_USE_BUFID2__SHIFT 0x00000006 +#define RBBM_DSPLY__DMI_CH1_SW_CNTL__SHIFT 0x00000007 +#define RBBM_DSPLY__DMI_CH1_NUM_BUFS__SHIFT 0x00000008 +#define RBBM_DSPLY__DMI_CH2_USE_BUFID0__SHIFT 0x0000000a +#define RBBM_DSPLY__DMI_CH2_USE_BUFID1__SHIFT 0x0000000b +#define RBBM_DSPLY__DMI_CH2_USE_BUFID2__SHIFT 0x0000000c +#define RBBM_DSPLY__DMI_CH2_SW_CNTL__SHIFT 0x0000000d +#define RBBM_DSPLY__DMI_CH2_NUM_BUFS__SHIFT 0x0000000e +#define RBBM_DSPLY__DMI_CHANNEL_SELECT__SHIFT 0x00000010 +#define RBBM_DSPLY__DMI_CH3_USE_BUFID0__SHIFT 0x00000014 +#define RBBM_DSPLY__DMI_CH3_USE_BUFID1__SHIFT 0x00000015 +#define RBBM_DSPLY__DMI_CH3_USE_BUFID2__SHIFT 0x00000016 +#define RBBM_DSPLY__DMI_CH3_SW_CNTL__SHIFT 0x00000017 +#define RBBM_DSPLY__DMI_CH3_NUM_BUFS__SHIFT 0x00000018 +#define RBBM_DSPLY__DMI_CH4_USE_BUFID0__SHIFT 0x0000001a +#define RBBM_DSPLY__DMI_CH4_USE_BUFID1__SHIFT 0x0000001b +#define RBBM_DSPLY__DMI_CH4_USE_BUFID2__SHIFT 0x0000001c +#define RBBM_DSPLY__DMI_CH4_SW_CNTL__SHIFT 0x0000001d +#define RBBM_DSPLY__DMI_CH4_NUM_BUFS__SHIFT 0x0000001e + +// RBBM_RENDER_LATEST +#define RBBM_RENDER_LATEST__DMI_CH1_BUFFER_ID__SHIFT 0x00000000 +#define RBBM_RENDER_LATEST__DMI_CH2_BUFFER_ID__SHIFT 0x00000008 +#define RBBM_RENDER_LATEST__DMI_CH3_BUFFER_ID__SHIFT 0x00000010 +#define RBBM_RENDER_LATEST__DMI_CH4_BUFFER_ID__SHIFT 0x00000018 + +// RBBM_RTL_RELEASE +#define RBBM_RTL_RELEASE__CHANGELIST__SHIFT 0x00000000 + +// RBBM_PATCH_RELEASE +#define RBBM_PATCH_RELEASE__PATCH_REVISION__SHIFT 0x00000000 +#define RBBM_PATCH_RELEASE__PATCH_SELECTION__SHIFT 0x00000010 +#define RBBM_PATCH_RELEASE__CUSTOMER_ID__SHIFT 0x00000018 + +// RBBM_AUXILIARY_CONFIG +#define RBBM_AUXILIARY_CONFIG__RESERVED__SHIFT 0x00000000 + +// RBBM_PERIPHID0 +#define RBBM_PERIPHID0__PARTNUMBER0__SHIFT 0x00000000 + +// RBBM_PERIPHID1 +#define RBBM_PERIPHID1__PARTNUMBER1__SHIFT 0x00000000 +#define RBBM_PERIPHID1__DESIGNER0__SHIFT 0x00000004 + +// RBBM_PERIPHID2 +#define RBBM_PERIPHID2__DESIGNER1__SHIFT 0x00000000 +#define RBBM_PERIPHID2__REVISION__SHIFT 0x00000004 + +// RBBM_PERIPHID3 +#define RBBM_PERIPHID3__RBBM_HOST_INTERFACE__SHIFT 0x00000000 +#define RBBM_PERIPHID3__GARB_SLAVE_INTERFACE__SHIFT 0x00000002 +#define RBBM_PERIPHID3__MH_INTERFACE__SHIFT 0x00000004 +#define RBBM_PERIPHID3__CONTINUATION__SHIFT 0x00000007 + +// RBBM_CNTL +#define RBBM_CNTL__READ_TIMEOUT__SHIFT 0x00000000 +#define RBBM_CNTL__REGCLK_DEASSERT_TIME__SHIFT 0x00000008 + +// RBBM_SKEW_CNTL +#define RBBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x00000000 +#define RBBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x00000005 + +// RBBM_SOFT_RESET +#define RBBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x00000000 +#define RBBM_SOFT_RESET__SOFT_RESET_PA__SHIFT 0x00000002 +#define RBBM_SOFT_RESET__SOFT_RESET_MH__SHIFT 0x00000003 +#define RBBM_SOFT_RESET__SOFT_RESET_BC__SHIFT 0x00000004 +#define RBBM_SOFT_RESET__SOFT_RESET_SQ__SHIFT 0x00000005 +#define RBBM_SOFT_RESET__SOFT_RESET_SX__SHIFT 0x00000006 +#define RBBM_SOFT_RESET__SOFT_RESET_CIB__SHIFT 0x0000000c +#define RBBM_SOFT_RESET__SOFT_RESET_SC__SHIFT 0x0000000f +#define RBBM_SOFT_RESET__SOFT_RESET_VGT__SHIFT 0x00000010 + +// RBBM_PM_OVERRIDE1 +#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE__SHIFT 0x00000000 +#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000001 +#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE__SHIFT 0x00000002 +#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE__SHIFT 0x00000003 +#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE__SHIFT 0x00000004 +#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000005 +#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE__SHIFT 0x00000006 +#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE__SHIFT 0x00000007 +#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE__SHIFT 0x00000008 +#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE__SHIFT 0x00000009 +#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000000a +#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE__SHIFT 0x0000000b +#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE__SHIFT 0x0000000c +#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE__SHIFT 0x0000000d +#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000000e +#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE__SHIFT 0x0000000f +#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000010 +#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE__SHIFT 0x00000011 +#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE__SHIFT 0x00000012 +#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE__SHIFT 0x00000013 +#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE__SHIFT 0x00000014 +#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000015 +#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE__SHIFT 0x00000016 +#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000017 +#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000018 +#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE__SHIFT 0x00000019 +#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000001a +#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE__SHIFT 0x0000001b +#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE__SHIFT 0x0000001c +#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000001d +#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE__SHIFT 0x0000001e +#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE__SHIFT 0x0000001f + +// RBBM_PM_OVERRIDE2 +#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000000 +#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE__SHIFT 0x00000001 +#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE__SHIFT 0x00000002 +#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000003 +#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE__SHIFT 0x00000004 +#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE__SHIFT 0x00000005 +#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE__SHIFT 0x00000006 +#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE__SHIFT 0x00000007 +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE__SHIFT 0x00000008 +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE__SHIFT 0x00000009 +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE__SHIFT 0x0000000a +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE__SHIFT 0x0000000b + +// GC_SYS_IDLE +#define GC_SYS_IDLE__GC_SYS_IDLE_DELAY__SHIFT 0x00000000 +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_MASK__SHIFT 0x00000010 +#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP__SHIFT 0x00000018 +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI__SHIFT 0x00000019 +#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_OVERRIDE__SHIFT 0x0000001d +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_OVERRIDE__SHIFT 0x0000001e +#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE__SHIFT 0x0000001f + +// NQWAIT_UNTIL +#define NQWAIT_UNTIL__WAIT_GUI_IDLE__SHIFT 0x00000000 + +// RBBM_DEBUG_OUT +#define RBBM_DEBUG_OUT__DEBUG_BUS_OUT__SHIFT 0x00000000 + +// RBBM_DEBUG_CNTL +#define RBBM_DEBUG_CNTL__SUB_BLOCK_ADDR__SHIFT 0x00000000 +#define RBBM_DEBUG_CNTL__SUB_BLOCK_SEL__SHIFT 0x00000008 +#define RBBM_DEBUG_CNTL__SW_ENABLE__SHIFT 0x0000000c +#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_ADDR__SHIFT 0x00000010 +#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_SEL__SHIFT 0x00000018 +#define RBBM_DEBUG_CNTL__GPIO_BYTE_LANE_ENB__SHIFT 0x0000001c + +// RBBM_DEBUG +#define RBBM_DEBUG__IGNORE_RTR__SHIFT 0x00000001 +#define RBBM_DEBUG__IGNORE_CP_SCHED_WU__SHIFT 0x00000002 +#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC__SHIFT 0x00000003 +#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI__SHIFT 0x00000004 +#define RBBM_DEBUG__HYSTERESIS_NRT_GUI_ACTIVE__SHIFT 0x00000008 +#define RBBM_DEBUG__IGNORE_RTR_FOR_HI__SHIFT 0x00000010 +#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI__SHIFT 0x00000011 +#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI__SHIFT 0x00000012 +#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI__SHIFT 0x00000013 +#define RBBM_DEBUG__CP_RBBM_NRTRTR__SHIFT 0x00000014 +#define RBBM_DEBUG__VGT_RBBM_NRTRTR__SHIFT 0x00000015 +#define RBBM_DEBUG__SQ_RBBM_NRTRTR__SHIFT 0x00000016 +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI__SHIFT 0x00000017 +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR__SHIFT 0x00000018 +#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY__SHIFT 0x0000001f + +// RBBM_READ_ERROR +#define RBBM_READ_ERROR__READ_ADDRESS__SHIFT 0x00000002 +#define RBBM_READ_ERROR__READ_REQUESTER__SHIFT 0x0000001e +#define RBBM_READ_ERROR__READ_ERROR__SHIFT 0x0000001f + +// RBBM_WAIT_IDLE_CLOCKS +#define RBBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_NRT__SHIFT 0x00000000 + +// RBBM_INT_CNTL +#define RBBM_INT_CNTL__RDERR_INT_MASK__SHIFT 0x00000000 +#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK__SHIFT 0x00000001 +#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK__SHIFT 0x00000013 + +// RBBM_INT_STATUS +#define RBBM_INT_STATUS__RDERR_INT_STAT__SHIFT 0x00000000 +#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT__SHIFT 0x00000001 +#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT__SHIFT 0x00000013 + +// RBBM_INT_ACK +#define RBBM_INT_ACK__RDERR_INT_ACK__SHIFT 0x00000000 +#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK__SHIFT 0x00000001 +#define RBBM_INT_ACK__GUI_IDLE_INT_ACK__SHIFT 0x00000013 + +// MASTER_INT_SIGNAL +#define MASTER_INT_SIGNAL__MH_INT_STAT__SHIFT 0x00000005 +#define MASTER_INT_SIGNAL__SQ_INT_STAT__SHIFT 0x0000001a +#define MASTER_INT_SIGNAL__CP_INT_STAT__SHIFT 0x0000001e +#define MASTER_INT_SIGNAL__RBBM_INT_STAT__SHIFT 0x0000001f + +// RBBM_PERFCOUNTER1_SELECT +#define RBBM_PERFCOUNTER1_SELECT__PERF_COUNT1_SEL__SHIFT 0x00000000 + +// RBBM_PERFCOUNTER1_LO +#define RBBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT 0x00000000 + +// RBBM_PERFCOUNTER1_HI +#define RBBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT 0x00000000 + +// CP_RB_BASE +#define CP_RB_BASE__RB_BASE__SHIFT 0x00000005 + +// CP_RB_CNTL +#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x00000000 +#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x00000008 +#define CP_RB_CNTL__BUF_SWAP__SHIFT 0x00000010 +#define CP_RB_CNTL__RB_POLL_EN__SHIFT 0x00000014 +#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b +#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x0000001f + +// CP_RB_RPTR_ADDR +#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x00000000 +#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000002 + +// CP_RB_RPTR +#define CP_RB_RPTR__RB_RPTR__SHIFT 0x00000000 + +// CP_RB_RPTR_WR +#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x00000000 + +// CP_RB_WPTR +#define CP_RB_WPTR__RB_WPTR__SHIFT 0x00000000 + +// CP_RB_WPTR_DELAY +#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x00000000 +#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x0000001c + +// CP_RB_WPTR_BASE +#define CP_RB_WPTR_BASE__RB_WPTR_SWAP__SHIFT 0x00000000 +#define CP_RB_WPTR_BASE__RB_WPTR_BASE__SHIFT 0x00000002 + +// CP_IB1_BASE +#define CP_IB1_BASE__IB1_BASE__SHIFT 0x00000002 + +// CP_IB1_BUFSZ +#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x00000000 + +// CP_IB2_BASE +#define CP_IB2_BASE__IB2_BASE__SHIFT 0x00000002 + +// CP_IB2_BUFSZ +#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x00000000 + +// CP_ST_BASE +#define CP_ST_BASE__ST_BASE__SHIFT 0x00000002 + +// CP_ST_BUFSZ +#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x00000000 + +// CP_QUEUE_THRESHOLDS +#define CP_QUEUE_THRESHOLDS__CSQ_IB1_START__SHIFT 0x00000000 +#define CP_QUEUE_THRESHOLDS__CSQ_IB2_START__SHIFT 0x00000008 +#define CP_QUEUE_THRESHOLDS__CSQ_ST_START__SHIFT 0x00000010 + +// CP_MEQ_THRESHOLDS +#define CP_MEQ_THRESHOLDS__MEQ_END__SHIFT 0x00000010 +#define CP_MEQ_THRESHOLDS__ROQ_END__SHIFT 0x00000018 + +// CP_CSQ_AVAIL +#define CP_CSQ_AVAIL__CSQ_CNT_RING__SHIFT 0x00000000 +#define CP_CSQ_AVAIL__CSQ_CNT_IB1__SHIFT 0x00000008 +#define CP_CSQ_AVAIL__CSQ_CNT_IB2__SHIFT 0x00000010 + +// CP_STQ_AVAIL +#define CP_STQ_AVAIL__STQ_CNT_ST__SHIFT 0x00000000 + +// CP_MEQ_AVAIL +#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x00000000 + +// CP_CSQ_RB_STAT +#define CP_CSQ_RB_STAT__CSQ_RPTR_PRIMARY__SHIFT 0x00000000 +#define CP_CSQ_RB_STAT__CSQ_WPTR_PRIMARY__SHIFT 0x00000010 + +// CP_CSQ_IB1_STAT +#define CP_CSQ_IB1_STAT__CSQ_RPTR_INDIRECT1__SHIFT 0x00000000 +#define CP_CSQ_IB1_STAT__CSQ_WPTR_INDIRECT1__SHIFT 0x00000010 + +// CP_CSQ_IB2_STAT +#define CP_CSQ_IB2_STAT__CSQ_RPTR_INDIRECT2__SHIFT 0x00000000 +#define CP_CSQ_IB2_STAT__CSQ_WPTR_INDIRECT2__SHIFT 0x00000010 + +// CP_NON_PREFETCH_CNTRS +#define CP_NON_PREFETCH_CNTRS__IB1_COUNTER__SHIFT 0x00000000 +#define CP_NON_PREFETCH_CNTRS__IB2_COUNTER__SHIFT 0x00000008 + +// CP_STQ_ST_STAT +#define CP_STQ_ST_STAT__STQ_RPTR_ST__SHIFT 0x00000000 +#define CP_STQ_ST_STAT__STQ_WPTR_ST__SHIFT 0x00000010 + +// CP_MEQ_STAT +#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x00000000 +#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x00000010 + +// CP_MIU_TAG_STAT +#define CP_MIU_TAG_STAT__TAG_0_STAT__SHIFT 0x00000000 +#define CP_MIU_TAG_STAT__TAG_1_STAT__SHIFT 0x00000001 +#define CP_MIU_TAG_STAT__TAG_2_STAT__SHIFT 0x00000002 +#define CP_MIU_TAG_STAT__TAG_3_STAT__SHIFT 0x00000003 +#define CP_MIU_TAG_STAT__TAG_4_STAT__SHIFT 0x00000004 +#define CP_MIU_TAG_STAT__TAG_5_STAT__SHIFT 0x00000005 +#define CP_MIU_TAG_STAT__TAG_6_STAT__SHIFT 0x00000006 +#define CP_MIU_TAG_STAT__TAG_7_STAT__SHIFT 0x00000007 +#define CP_MIU_TAG_STAT__TAG_8_STAT__SHIFT 0x00000008 +#define CP_MIU_TAG_STAT__TAG_9_STAT__SHIFT 0x00000009 +#define CP_MIU_TAG_STAT__TAG_10_STAT__SHIFT 0x0000000a +#define CP_MIU_TAG_STAT__TAG_11_STAT__SHIFT 0x0000000b +#define CP_MIU_TAG_STAT__TAG_12_STAT__SHIFT 0x0000000c +#define CP_MIU_TAG_STAT__TAG_13_STAT__SHIFT 0x0000000d +#define CP_MIU_TAG_STAT__TAG_14_STAT__SHIFT 0x0000000e +#define CP_MIU_TAG_STAT__TAG_15_STAT__SHIFT 0x0000000f +#define CP_MIU_TAG_STAT__TAG_16_STAT__SHIFT 0x00000010 +#define CP_MIU_TAG_STAT__TAG_17_STAT__SHIFT 0x00000011 +#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG__SHIFT 0x0000001f + +// CP_CMD_INDEX +#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x00000000 +#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x00000010 + +// CP_CMD_DATA +#define CP_CMD_DATA__CMD_DATA__SHIFT 0x00000000 + +// CP_ME_CNTL +#define CP_ME_CNTL__ME_STATMUX__SHIFT 0x00000000 +#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY__SHIFT 0x00000019 +#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY__SHIFT 0x0000001a +#define CP_ME_CNTL__ME_HALT__SHIFT 0x0000001c +#define CP_ME_CNTL__ME_BUSY__SHIFT 0x0000001d +#define CP_ME_CNTL__PROG_CNT_SIZE__SHIFT 0x0000001f + +// CP_ME_STATUS +#define CP_ME_STATUS__ME_DEBUG_DATA__SHIFT 0x00000000 + +// CP_ME_RAM_WADDR +#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x00000000 + +// CP_ME_RAM_RADDR +#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x00000000 + +// CP_ME_RAM_DATA +#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x00000000 + +// CP_ME_RDADDR +#define CP_ME_RDADDR__ME_RDADDR__SHIFT 0x00000000 + +// CP_DEBUG +#define CP_DEBUG__CP_DEBUG_UNUSED_22_to_0__SHIFT 0x00000000 +#define CP_DEBUG__PREDICATE_DISABLE__SHIFT 0x00000017 +#define CP_DEBUG__PROG_END_PTR_ENABLE__SHIFT 0x00000018 +#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE__SHIFT 0x00000019 +#define CP_DEBUG__PREFETCH_PASS_NOPS__SHIFT 0x0000001a +#define CP_DEBUG__DYNAMIC_CLK_DISABLE__SHIFT 0x0000001b +#define CP_DEBUG__PREFETCH_MATCH_DISABLE__SHIFT 0x0000001c +#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL__SHIFT 0x0000001e +#define CP_DEBUG__MIU_WRITE_PACK_DISABLE__SHIFT 0x0000001f + +// SCRATCH_REG0 +#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x00000000 +#define GUI_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x00000000 + +// SCRATCH_REG1 +#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x00000000 +#define GUI_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x00000000 + +// SCRATCH_REG2 +#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x00000000 +#define GUI_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x00000000 + +// SCRATCH_REG3 +#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x00000000 +#define GUI_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x00000000 + +// SCRATCH_REG4 +#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x00000000 +#define GUI_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x00000000 + +// SCRATCH_REG5 +#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x00000000 +#define GUI_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x00000000 + +// SCRATCH_REG6 +#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x00000000 +#define GUI_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x00000000 + +// SCRATCH_REG7 +#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x00000000 +#define GUI_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x00000000 + +// SCRATCH_UMSK +#define SCRATCH_UMSK__SCRATCH_UMSK__SHIFT 0x00000000 +#define SCRATCH_UMSK__SCRATCH_SWAP__SHIFT 0x00000010 + +// SCRATCH_ADDR +#define SCRATCH_ADDR__SCRATCH_ADDR__SHIFT 0x00000005 + +// CP_ME_VS_EVENT_SRC +#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM__SHIFT 0x00000000 +#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR__SHIFT 0x00000001 + +// CP_ME_VS_EVENT_ADDR +#define CP_ME_VS_EVENT_ADDR__VS_DONE_SWAP__SHIFT 0x00000000 +#define CP_ME_VS_EVENT_ADDR__VS_DONE_ADDR__SHIFT 0x00000002 + +// CP_ME_VS_EVENT_DATA +#define CP_ME_VS_EVENT_DATA__VS_DONE_DATA__SHIFT 0x00000000 + +// CP_ME_VS_EVENT_ADDR_SWM +#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_SWAP_SWM__SHIFT 0x00000000 +#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_ADDR_SWM__SHIFT 0x00000002 + +// CP_ME_VS_EVENT_DATA_SWM +#define CP_ME_VS_EVENT_DATA_SWM__VS_DONE_DATA_SWM__SHIFT 0x00000000 + +// CP_ME_PS_EVENT_SRC +#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM__SHIFT 0x00000000 +#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR__SHIFT 0x00000001 + +// CP_ME_PS_EVENT_ADDR +#define CP_ME_PS_EVENT_ADDR__PS_DONE_SWAP__SHIFT 0x00000000 +#define CP_ME_PS_EVENT_ADDR__PS_DONE_ADDR__SHIFT 0x00000002 + +// CP_ME_PS_EVENT_DATA +#define CP_ME_PS_EVENT_DATA__PS_DONE_DATA__SHIFT 0x00000000 + +// CP_ME_PS_EVENT_ADDR_SWM +#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_SWAP_SWM__SHIFT 0x00000000 +#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_ADDR_SWM__SHIFT 0x00000002 + +// CP_ME_PS_EVENT_DATA_SWM +#define CP_ME_PS_EVENT_DATA_SWM__PS_DONE_DATA_SWM__SHIFT 0x00000000 + +// CP_ME_CF_EVENT_SRC +#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC__SHIFT 0x00000000 + +// CP_ME_CF_EVENT_ADDR +#define CP_ME_CF_EVENT_ADDR__CF_DONE_SWAP__SHIFT 0x00000000 +#define CP_ME_CF_EVENT_ADDR__CF_DONE_ADDR__SHIFT 0x00000002 + +// CP_ME_CF_EVENT_DATA +#define CP_ME_CF_EVENT_DATA__CF_DONE_DATA__SHIFT 0x00000000 + +// CP_ME_NRT_ADDR +#define CP_ME_NRT_ADDR__NRT_WRITE_SWAP__SHIFT 0x00000000 +#define CP_ME_NRT_ADDR__NRT_WRITE_ADDR__SHIFT 0x00000002 + +// CP_ME_NRT_DATA +#define CP_ME_NRT_DATA__NRT_WRITE_DATA__SHIFT 0x00000000 + +// CP_ME_VS_FETCH_DONE_SRC +#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR__SHIFT 0x00000000 + +// CP_ME_VS_FETCH_DONE_ADDR +#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_SWAP__SHIFT 0x00000000 +#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_ADDR__SHIFT 0x00000002 + +// CP_ME_VS_FETCH_DONE_DATA +#define CP_ME_VS_FETCH_DONE_DATA__VS_FETCH_DONE_DATA__SHIFT 0x00000000 + +// CP_INT_CNTL +#define CP_INT_CNTL__SW_INT_MASK__SHIFT 0x00000013 +#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK__SHIFT 0x00000017 +#define CP_INT_CNTL__OPCODE_ERROR_MASK__SHIFT 0x00000018 +#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK__SHIFT 0x00000019 +#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK__SHIFT 0x0000001a +#define CP_INT_CNTL__IB_ERROR_MASK__SHIFT 0x0000001b +#define CP_INT_CNTL__IB2_INT_MASK__SHIFT 0x0000001d +#define CP_INT_CNTL__IB1_INT_MASK__SHIFT 0x0000001e +#define CP_INT_CNTL__RB_INT_MASK__SHIFT 0x0000001f + +// CP_INT_STATUS +#define CP_INT_STATUS__SW_INT_STAT__SHIFT 0x00000013 +#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT__SHIFT 0x00000017 +#define CP_INT_STATUS__OPCODE_ERROR_STAT__SHIFT 0x00000018 +#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT__SHIFT 0x00000019 +#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT__SHIFT 0x0000001a +#define CP_INT_STATUS__IB_ERROR_STAT__SHIFT 0x0000001b +#define CP_INT_STATUS__IB2_INT_STAT__SHIFT 0x0000001d +#define CP_INT_STATUS__IB1_INT_STAT__SHIFT 0x0000001e +#define CP_INT_STATUS__RB_INT_STAT__SHIFT 0x0000001f + +// CP_INT_ACK +#define CP_INT_ACK__SW_INT_ACK__SHIFT 0x00000013 +#define CP_INT_ACK__T0_PACKET_IN_IB_ACK__SHIFT 0x00000017 +#define CP_INT_ACK__OPCODE_ERROR_ACK__SHIFT 0x00000018 +#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK__SHIFT 0x00000019 +#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK__SHIFT 0x0000001a +#define CP_INT_ACK__IB_ERROR_ACK__SHIFT 0x0000001b +#define CP_INT_ACK__IB2_INT_ACK__SHIFT 0x0000001d +#define CP_INT_ACK__IB1_INT_ACK__SHIFT 0x0000001e +#define CP_INT_ACK__RB_INT_ACK__SHIFT 0x0000001f + +// CP_PFP_UCODE_ADDR +#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x00000000 + +// CP_PFP_UCODE_DATA +#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x00000000 + +// CP_PERFMON_CNTL +#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x00000000 +#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x00000008 + +// CP_PERFCOUNTER_SELECT +#define CP_PERFCOUNTER_SELECT__PERFCOUNT_SEL__SHIFT 0x00000000 + +// CP_PERFCOUNTER_LO +#define CP_PERFCOUNTER_LO__PERFCOUNT_LO__SHIFT 0x00000000 + +// CP_PERFCOUNTER_HI +#define CP_PERFCOUNTER_HI__PERFCOUNT_HI__SHIFT 0x00000000 + +// CP_BIN_MASK_LO +#define CP_BIN_MASK_LO__BIN_MASK_LO__SHIFT 0x00000000 + +// CP_BIN_MASK_HI +#define CP_BIN_MASK_HI__BIN_MASK_HI__SHIFT 0x00000000 + +// CP_BIN_SELECT_LO +#define CP_BIN_SELECT_LO__BIN_SELECT_LO__SHIFT 0x00000000 + +// CP_BIN_SELECT_HI +#define CP_BIN_SELECT_HI__BIN_SELECT_HI__SHIFT 0x00000000 + +// CP_NV_FLAGS_0 +#define CP_NV_FLAGS_0__DISCARD_0__SHIFT 0x00000000 +#define CP_NV_FLAGS_0__END_RCVD_0__SHIFT 0x00000001 +#define CP_NV_FLAGS_0__DISCARD_1__SHIFT 0x00000002 +#define CP_NV_FLAGS_0__END_RCVD_1__SHIFT 0x00000003 +#define CP_NV_FLAGS_0__DISCARD_2__SHIFT 0x00000004 +#define CP_NV_FLAGS_0__END_RCVD_2__SHIFT 0x00000005 +#define CP_NV_FLAGS_0__DISCARD_3__SHIFT 0x00000006 +#define CP_NV_FLAGS_0__END_RCVD_3__SHIFT 0x00000007 +#define CP_NV_FLAGS_0__DISCARD_4__SHIFT 0x00000008 +#define CP_NV_FLAGS_0__END_RCVD_4__SHIFT 0x00000009 +#define CP_NV_FLAGS_0__DISCARD_5__SHIFT 0x0000000a +#define CP_NV_FLAGS_0__END_RCVD_5__SHIFT 0x0000000b +#define CP_NV_FLAGS_0__DISCARD_6__SHIFT 0x0000000c +#define CP_NV_FLAGS_0__END_RCVD_6__SHIFT 0x0000000d +#define CP_NV_FLAGS_0__DISCARD_7__SHIFT 0x0000000e +#define CP_NV_FLAGS_0__END_RCVD_7__SHIFT 0x0000000f +#define CP_NV_FLAGS_0__DISCARD_8__SHIFT 0x00000010 +#define CP_NV_FLAGS_0__END_RCVD_8__SHIFT 0x00000011 +#define CP_NV_FLAGS_0__DISCARD_9__SHIFT 0x00000012 +#define CP_NV_FLAGS_0__END_RCVD_9__SHIFT 0x00000013 +#define CP_NV_FLAGS_0__DISCARD_10__SHIFT 0x00000014 +#define CP_NV_FLAGS_0__END_RCVD_10__SHIFT 0x00000015 +#define CP_NV_FLAGS_0__DISCARD_11__SHIFT 0x00000016 +#define CP_NV_FLAGS_0__END_RCVD_11__SHIFT 0x00000017 +#define CP_NV_FLAGS_0__DISCARD_12__SHIFT 0x00000018 +#define CP_NV_FLAGS_0__END_RCVD_12__SHIFT 0x00000019 +#define CP_NV_FLAGS_0__DISCARD_13__SHIFT 0x0000001a +#define CP_NV_FLAGS_0__END_RCVD_13__SHIFT 0x0000001b +#define CP_NV_FLAGS_0__DISCARD_14__SHIFT 0x0000001c +#define CP_NV_FLAGS_0__END_RCVD_14__SHIFT 0x0000001d +#define CP_NV_FLAGS_0__DISCARD_15__SHIFT 0x0000001e +#define CP_NV_FLAGS_0__END_RCVD_15__SHIFT 0x0000001f + +// CP_NV_FLAGS_1 +#define CP_NV_FLAGS_1__DISCARD_16__SHIFT 0x00000000 +#define CP_NV_FLAGS_1__END_RCVD_16__SHIFT 0x00000001 +#define CP_NV_FLAGS_1__DISCARD_17__SHIFT 0x00000002 +#define CP_NV_FLAGS_1__END_RCVD_17__SHIFT 0x00000003 +#define CP_NV_FLAGS_1__DISCARD_18__SHIFT 0x00000004 +#define CP_NV_FLAGS_1__END_RCVD_18__SHIFT 0x00000005 +#define CP_NV_FLAGS_1__DISCARD_19__SHIFT 0x00000006 +#define CP_NV_FLAGS_1__END_RCVD_19__SHIFT 0x00000007 +#define CP_NV_FLAGS_1__DISCARD_20__SHIFT 0x00000008 +#define CP_NV_FLAGS_1__END_RCVD_20__SHIFT 0x00000009 +#define CP_NV_FLAGS_1__DISCARD_21__SHIFT 0x0000000a +#define CP_NV_FLAGS_1__END_RCVD_21__SHIFT 0x0000000b +#define CP_NV_FLAGS_1__DISCARD_22__SHIFT 0x0000000c +#define CP_NV_FLAGS_1__END_RCVD_22__SHIFT 0x0000000d +#define CP_NV_FLAGS_1__DISCARD_23__SHIFT 0x0000000e +#define CP_NV_FLAGS_1__END_RCVD_23__SHIFT 0x0000000f +#define CP_NV_FLAGS_1__DISCARD_24__SHIFT 0x00000010 +#define CP_NV_FLAGS_1__END_RCVD_24__SHIFT 0x00000011 +#define CP_NV_FLAGS_1__DISCARD_25__SHIFT 0x00000012 +#define CP_NV_FLAGS_1__END_RCVD_25__SHIFT 0x00000013 +#define CP_NV_FLAGS_1__DISCARD_26__SHIFT 0x00000014 +#define CP_NV_FLAGS_1__END_RCVD_26__SHIFT 0x00000015 +#define CP_NV_FLAGS_1__DISCARD_27__SHIFT 0x00000016 +#define CP_NV_FLAGS_1__END_RCVD_27__SHIFT 0x00000017 +#define CP_NV_FLAGS_1__DISCARD_28__SHIFT 0x00000018 +#define CP_NV_FLAGS_1__END_RCVD_28__SHIFT 0x00000019 +#define CP_NV_FLAGS_1__DISCARD_29__SHIFT 0x0000001a +#define CP_NV_FLAGS_1__END_RCVD_29__SHIFT 0x0000001b +#define CP_NV_FLAGS_1__DISCARD_30__SHIFT 0x0000001c +#define CP_NV_FLAGS_1__END_RCVD_30__SHIFT 0x0000001d +#define CP_NV_FLAGS_1__DISCARD_31__SHIFT 0x0000001e +#define CP_NV_FLAGS_1__END_RCVD_31__SHIFT 0x0000001f + +// CP_NV_FLAGS_2 +#define CP_NV_FLAGS_2__DISCARD_32__SHIFT 0x00000000 +#define CP_NV_FLAGS_2__END_RCVD_32__SHIFT 0x00000001 +#define CP_NV_FLAGS_2__DISCARD_33__SHIFT 0x00000002 +#define CP_NV_FLAGS_2__END_RCVD_33__SHIFT 0x00000003 +#define CP_NV_FLAGS_2__DISCARD_34__SHIFT 0x00000004 +#define CP_NV_FLAGS_2__END_RCVD_34__SHIFT 0x00000005 +#define CP_NV_FLAGS_2__DISCARD_35__SHIFT 0x00000006 +#define CP_NV_FLAGS_2__END_RCVD_35__SHIFT 0x00000007 +#define CP_NV_FLAGS_2__DISCARD_36__SHIFT 0x00000008 +#define CP_NV_FLAGS_2__END_RCVD_36__SHIFT 0x00000009 +#define CP_NV_FLAGS_2__DISCARD_37__SHIFT 0x0000000a +#define CP_NV_FLAGS_2__END_RCVD_37__SHIFT 0x0000000b +#define CP_NV_FLAGS_2__DISCARD_38__SHIFT 0x0000000c +#define CP_NV_FLAGS_2__END_RCVD_38__SHIFT 0x0000000d +#define CP_NV_FLAGS_2__DISCARD_39__SHIFT 0x0000000e +#define CP_NV_FLAGS_2__END_RCVD_39__SHIFT 0x0000000f +#define CP_NV_FLAGS_2__DISCARD_40__SHIFT 0x00000010 +#define CP_NV_FLAGS_2__END_RCVD_40__SHIFT 0x00000011 +#define CP_NV_FLAGS_2__DISCARD_41__SHIFT 0x00000012 +#define CP_NV_FLAGS_2__END_RCVD_41__SHIFT 0x00000013 +#define CP_NV_FLAGS_2__DISCARD_42__SHIFT 0x00000014 +#define CP_NV_FLAGS_2__END_RCVD_42__SHIFT 0x00000015 +#define CP_NV_FLAGS_2__DISCARD_43__SHIFT 0x00000016 +#define CP_NV_FLAGS_2__END_RCVD_43__SHIFT 0x00000017 +#define CP_NV_FLAGS_2__DISCARD_44__SHIFT 0x00000018 +#define CP_NV_FLAGS_2__END_RCVD_44__SHIFT 0x00000019 +#define CP_NV_FLAGS_2__DISCARD_45__SHIFT 0x0000001a +#define CP_NV_FLAGS_2__END_RCVD_45__SHIFT 0x0000001b +#define CP_NV_FLAGS_2__DISCARD_46__SHIFT 0x0000001c +#define CP_NV_FLAGS_2__END_RCVD_46__SHIFT 0x0000001d +#define CP_NV_FLAGS_2__DISCARD_47__SHIFT 0x0000001e +#define CP_NV_FLAGS_2__END_RCVD_47__SHIFT 0x0000001f + +// CP_NV_FLAGS_3 +#define CP_NV_FLAGS_3__DISCARD_48__SHIFT 0x00000000 +#define CP_NV_FLAGS_3__END_RCVD_48__SHIFT 0x00000001 +#define CP_NV_FLAGS_3__DISCARD_49__SHIFT 0x00000002 +#define CP_NV_FLAGS_3__END_RCVD_49__SHIFT 0x00000003 +#define CP_NV_FLAGS_3__DISCARD_50__SHIFT 0x00000004 +#define CP_NV_FLAGS_3__END_RCVD_50__SHIFT 0x00000005 +#define CP_NV_FLAGS_3__DISCARD_51__SHIFT 0x00000006 +#define CP_NV_FLAGS_3__END_RCVD_51__SHIFT 0x00000007 +#define CP_NV_FLAGS_3__DISCARD_52__SHIFT 0x00000008 +#define CP_NV_FLAGS_3__END_RCVD_52__SHIFT 0x00000009 +#define CP_NV_FLAGS_3__DISCARD_53__SHIFT 0x0000000a +#define CP_NV_FLAGS_3__END_RCVD_53__SHIFT 0x0000000b +#define CP_NV_FLAGS_3__DISCARD_54__SHIFT 0x0000000c +#define CP_NV_FLAGS_3__END_RCVD_54__SHIFT 0x0000000d +#define CP_NV_FLAGS_3__DISCARD_55__SHIFT 0x0000000e +#define CP_NV_FLAGS_3__END_RCVD_55__SHIFT 0x0000000f +#define CP_NV_FLAGS_3__DISCARD_56__SHIFT 0x00000010 +#define CP_NV_FLAGS_3__END_RCVD_56__SHIFT 0x00000011 +#define CP_NV_FLAGS_3__DISCARD_57__SHIFT 0x00000012 +#define CP_NV_FLAGS_3__END_RCVD_57__SHIFT 0x00000013 +#define CP_NV_FLAGS_3__DISCARD_58__SHIFT 0x00000014 +#define CP_NV_FLAGS_3__END_RCVD_58__SHIFT 0x00000015 +#define CP_NV_FLAGS_3__DISCARD_59__SHIFT 0x00000016 +#define CP_NV_FLAGS_3__END_RCVD_59__SHIFT 0x00000017 +#define CP_NV_FLAGS_3__DISCARD_60__SHIFT 0x00000018 +#define CP_NV_FLAGS_3__END_RCVD_60__SHIFT 0x00000019 +#define CP_NV_FLAGS_3__DISCARD_61__SHIFT 0x0000001a +#define CP_NV_FLAGS_3__END_RCVD_61__SHIFT 0x0000001b +#define CP_NV_FLAGS_3__DISCARD_62__SHIFT 0x0000001c +#define CP_NV_FLAGS_3__END_RCVD_62__SHIFT 0x0000001d +#define CP_NV_FLAGS_3__DISCARD_63__SHIFT 0x0000001e +#define CP_NV_FLAGS_3__END_RCVD_63__SHIFT 0x0000001f + +// CP_STATE_DEBUG_INDEX +#define CP_STATE_DEBUG_INDEX__STATE_DEBUG_INDEX__SHIFT 0x00000000 + +// CP_STATE_DEBUG_DATA +#define CP_STATE_DEBUG_DATA__STATE_DEBUG_DATA__SHIFT 0x00000000 + +// CP_PROG_COUNTER +#define CP_PROG_COUNTER__COUNTER__SHIFT 0x00000000 + +// CP_STAT +#define CP_STAT__MIU_WR_BUSY__SHIFT 0x00000000 +#define CP_STAT__MIU_RD_REQ_BUSY__SHIFT 0x00000001 +#define CP_STAT__MIU_RD_RETURN_BUSY__SHIFT 0x00000002 +#define CP_STAT__RBIU_BUSY__SHIFT 0x00000003 +#define CP_STAT__RCIU_BUSY__SHIFT 0x00000004 +#define CP_STAT__CSF_RING_BUSY__SHIFT 0x00000005 +#define CP_STAT__CSF_INDIRECTS_BUSY__SHIFT 0x00000006 +#define CP_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x00000007 +#define CP_STAT__CSF_ST_BUSY__SHIFT 0x00000009 +#define CP_STAT__CSF_BUSY__SHIFT 0x0000000a +#define CP_STAT__RING_QUEUE_BUSY__SHIFT 0x0000000b +#define CP_STAT__INDIRECTS_QUEUE_BUSY__SHIFT 0x0000000c +#define CP_STAT__INDIRECT2_QUEUE_BUSY__SHIFT 0x0000000d +#define CP_STAT__ST_QUEUE_BUSY__SHIFT 0x00000010 +#define CP_STAT__PFP_BUSY__SHIFT 0x00000011 +#define CP_STAT__MEQ_RING_BUSY__SHIFT 0x00000012 +#define CP_STAT__MEQ_INDIRECTS_BUSY__SHIFT 0x00000013 +#define CP_STAT__MEQ_INDIRECT2_BUSY__SHIFT 0x00000014 +#define CP_STAT__MIU_WC_STALL__SHIFT 0x00000015 +#define CP_STAT__CP_NRT_BUSY__SHIFT 0x00000016 +#define CP_STAT___3D_BUSY__SHIFT 0x00000017 +#define CP_STAT__ME_BUSY__SHIFT 0x0000001a +#define CP_STAT__ME_WC_BUSY__SHIFT 0x0000001d +#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY__SHIFT 0x0000001e +#define CP_STAT__CP_BUSY__SHIFT 0x0000001f + +// BIOS_0_SCRATCH +#define BIOS_0_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_1_SCRATCH +#define BIOS_1_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_2_SCRATCH +#define BIOS_2_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_3_SCRATCH +#define BIOS_3_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_4_SCRATCH +#define BIOS_4_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_5_SCRATCH +#define BIOS_5_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_6_SCRATCH +#define BIOS_6_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_7_SCRATCH +#define BIOS_7_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_8_SCRATCH +#define BIOS_8_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_9_SCRATCH +#define BIOS_9_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_10_SCRATCH +#define BIOS_10_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_11_SCRATCH +#define BIOS_11_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_12_SCRATCH +#define BIOS_12_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_13_SCRATCH +#define BIOS_13_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_14_SCRATCH +#define BIOS_14_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_15_SCRATCH +#define BIOS_15_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// COHER_SIZE_PM4 +#define COHER_SIZE_PM4__SIZE__SHIFT 0x00000000 + +// COHER_BASE_PM4 +#define COHER_BASE_PM4__BASE__SHIFT 0x00000000 + +// COHER_STATUS_PM4 +#define COHER_STATUS_PM4__MATCHING_CONTEXTS__SHIFT 0x00000000 +#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA__SHIFT 0x00000008 +#define COHER_STATUS_PM4__DEST_BASE_0_ENA__SHIFT 0x00000009 +#define COHER_STATUS_PM4__DEST_BASE_1_ENA__SHIFT 0x0000000a +#define COHER_STATUS_PM4__DEST_BASE_2_ENA__SHIFT 0x0000000b +#define COHER_STATUS_PM4__DEST_BASE_3_ENA__SHIFT 0x0000000c +#define COHER_STATUS_PM4__DEST_BASE_4_ENA__SHIFT 0x0000000d +#define COHER_STATUS_PM4__DEST_BASE_5_ENA__SHIFT 0x0000000e +#define COHER_STATUS_PM4__DEST_BASE_6_ENA__SHIFT 0x0000000f +#define COHER_STATUS_PM4__DEST_BASE_7_ENA__SHIFT 0x00000010 +#define COHER_STATUS_PM4__RB_COLOR_INFO_ENA__SHIFT 0x00000011 +#define COHER_STATUS_PM4__TC_ACTION_ENA__SHIFT 0x00000019 +#define COHER_STATUS_PM4__STATUS__SHIFT 0x0000001f + +// COHER_SIZE_HOST +#define COHER_SIZE_HOST__SIZE__SHIFT 0x00000000 + +// COHER_BASE_HOST +#define COHER_BASE_HOST__BASE__SHIFT 0x00000000 + +// COHER_STATUS_HOST +#define COHER_STATUS_HOST__MATCHING_CONTEXTS__SHIFT 0x00000000 +#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA__SHIFT 0x00000008 +#define COHER_STATUS_HOST__DEST_BASE_0_ENA__SHIFT 0x00000009 +#define COHER_STATUS_HOST__DEST_BASE_1_ENA__SHIFT 0x0000000a +#define COHER_STATUS_HOST__DEST_BASE_2_ENA__SHIFT 0x0000000b +#define COHER_STATUS_HOST__DEST_BASE_3_ENA__SHIFT 0x0000000c +#define COHER_STATUS_HOST__DEST_BASE_4_ENA__SHIFT 0x0000000d +#define COHER_STATUS_HOST__DEST_BASE_5_ENA__SHIFT 0x0000000e +#define COHER_STATUS_HOST__DEST_BASE_6_ENA__SHIFT 0x0000000f +#define COHER_STATUS_HOST__DEST_BASE_7_ENA__SHIFT 0x00000010 +#define COHER_STATUS_HOST__RB_COLOR_INFO_ENA__SHIFT 0x00000011 +#define COHER_STATUS_HOST__TC_ACTION_ENA__SHIFT 0x00000019 +#define COHER_STATUS_HOST__STATUS__SHIFT 0x0000001f + +// COHER_DEST_BASE_0 +#define COHER_DEST_BASE_0__DEST_BASE_0__SHIFT 0x0000000c + +// COHER_DEST_BASE_1 +#define COHER_DEST_BASE_1__DEST_BASE_1__SHIFT 0x0000000c + +// COHER_DEST_BASE_2 +#define COHER_DEST_BASE_2__DEST_BASE_2__SHIFT 0x0000000c + +// COHER_DEST_BASE_3 +#define COHER_DEST_BASE_3__DEST_BASE_3__SHIFT 0x0000000c + +// COHER_DEST_BASE_4 +#define COHER_DEST_BASE_4__DEST_BASE_4__SHIFT 0x0000000c + +// COHER_DEST_BASE_5 +#define COHER_DEST_BASE_5__DEST_BASE_5__SHIFT 0x0000000c + +// COHER_DEST_BASE_6 +#define COHER_DEST_BASE_6__DEST_BASE_6__SHIFT 0x0000000c + +// COHER_DEST_BASE_7 +#define COHER_DEST_BASE_7__DEST_BASE_7__SHIFT 0x0000000c + +// RB_SURFACE_INFO +#define RB_SURFACE_INFO__SURFACE_PITCH__SHIFT 0x00000000 +#define RB_SURFACE_INFO__MSAA_SAMPLES__SHIFT 0x0000000e + +// RB_COLOR_INFO +#define RB_COLOR_INFO__COLOR_FORMAT__SHIFT 0x00000000 +#define RB_COLOR_INFO__COLOR_ROUND_MODE__SHIFT 0x00000004 +#define RB_COLOR_INFO__COLOR_LINEAR__SHIFT 0x00000006 +#define RB_COLOR_INFO__COLOR_ENDIAN__SHIFT 0x00000007 +#define RB_COLOR_INFO__COLOR_SWAP__SHIFT 0x00000009 +#define RB_COLOR_INFO__COLOR_BASE__SHIFT 0x0000000c + +// RB_DEPTH_INFO +#define RB_DEPTH_INFO__DEPTH_FORMAT__SHIFT 0x00000000 +#define RB_DEPTH_INFO__DEPTH_BASE__SHIFT 0x0000000c + +// RB_STENCILREFMASK +#define RB_STENCILREFMASK__STENCILREF__SHIFT 0x00000000 +#define RB_STENCILREFMASK__STENCILMASK__SHIFT 0x00000008 +#define RB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x00000010 +#define RB_STENCILREFMASK__RESERVED0__SHIFT 0x00000018 +#define RB_STENCILREFMASK__RESERVED1__SHIFT 0x00000019 + +// RB_ALPHA_REF +#define RB_ALPHA_REF__ALPHA_REF__SHIFT 0x00000000 + +// RB_COLOR_MASK +#define RB_COLOR_MASK__WRITE_RED__SHIFT 0x00000000 +#define RB_COLOR_MASK__WRITE_GREEN__SHIFT 0x00000001 +#define RB_COLOR_MASK__WRITE_BLUE__SHIFT 0x00000002 +#define RB_COLOR_MASK__WRITE_ALPHA__SHIFT 0x00000003 +#define RB_COLOR_MASK__RESERVED2__SHIFT 0x00000004 +#define RB_COLOR_MASK__RESERVED3__SHIFT 0x00000005 + +// RB_BLEND_RED +#define RB_BLEND_RED__BLEND_RED__SHIFT 0x00000000 + +// RB_BLEND_GREEN +#define RB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x00000000 + +// RB_BLEND_BLUE +#define RB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x00000000 + +// RB_BLEND_ALPHA +#define RB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x00000000 + +// RB_FOG_COLOR +#define RB_FOG_COLOR__FOG_RED__SHIFT 0x00000000 +#define RB_FOG_COLOR__FOG_GREEN__SHIFT 0x00000008 +#define RB_FOG_COLOR__FOG_BLUE__SHIFT 0x00000010 + +// RB_STENCILREFMASK_BF +#define RB_STENCILREFMASK_BF__STENCILREF_BF__SHIFT 0x00000000 +#define RB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x00000008 +#define RB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x00000010 +#define RB_STENCILREFMASK_BF__RESERVED4__SHIFT 0x00000018 +#define RB_STENCILREFMASK_BF__RESERVED5__SHIFT 0x00000019 + +// RB_DEPTHCONTROL +#define RB_DEPTHCONTROL__STENCIL_ENABLE__SHIFT 0x00000000 +#define RB_DEPTHCONTROL__Z_ENABLE__SHIFT 0x00000001 +#define RB_DEPTHCONTROL__Z_WRITE_ENABLE__SHIFT 0x00000002 +#define RB_DEPTHCONTROL__EARLY_Z_ENABLE__SHIFT 0x00000003 +#define RB_DEPTHCONTROL__ZFUNC__SHIFT 0x00000004 +#define RB_DEPTHCONTROL__BACKFACE_ENABLE__SHIFT 0x00000007 +#define RB_DEPTHCONTROL__STENCILFUNC__SHIFT 0x00000008 +#define RB_DEPTHCONTROL__STENCILFAIL__SHIFT 0x0000000b +#define RB_DEPTHCONTROL__STENCILZPASS__SHIFT 0x0000000e +#define RB_DEPTHCONTROL__STENCILZFAIL__SHIFT 0x00000011 +#define RB_DEPTHCONTROL__STENCILFUNC_BF__SHIFT 0x00000014 +#define RB_DEPTHCONTROL__STENCILFAIL_BF__SHIFT 0x00000017 +#define RB_DEPTHCONTROL__STENCILZPASS_BF__SHIFT 0x0000001a +#define RB_DEPTHCONTROL__STENCILZFAIL_BF__SHIFT 0x0000001d + +// RB_BLENDCONTROL +#define RB_BLENDCONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 +#define RB_BLENDCONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 +#define RB_BLENDCONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 +#define RB_BLENDCONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 +#define RB_BLENDCONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 +#define RB_BLENDCONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 +#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE__SHIFT 0x0000001d +#define RB_BLENDCONTROL__BLEND_FORCE__SHIFT 0x0000001e + +// RB_COLORCONTROL +#define RB_COLORCONTROL__ALPHA_FUNC__SHIFT 0x00000000 +#define RB_COLORCONTROL__ALPHA_TEST_ENABLE__SHIFT 0x00000003 +#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE__SHIFT 0x00000004 +#define RB_COLORCONTROL__BLEND_DISABLE__SHIFT 0x00000005 +#define RB_COLORCONTROL__FOG_ENABLE__SHIFT 0x00000006 +#define RB_COLORCONTROL__VS_EXPORTS_FOG__SHIFT 0x00000007 +#define RB_COLORCONTROL__ROP_CODE__SHIFT 0x00000008 +#define RB_COLORCONTROL__DITHER_MODE__SHIFT 0x0000000c +#define RB_COLORCONTROL__DITHER_TYPE__SHIFT 0x0000000e +#define RB_COLORCONTROL__PIXEL_FOG__SHIFT 0x00000010 +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET0__SHIFT 0x00000018 +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET1__SHIFT 0x0000001a +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET2__SHIFT 0x0000001c +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET3__SHIFT 0x0000001e + +// RB_MODECONTROL +#define RB_MODECONTROL__EDRAM_MODE__SHIFT 0x00000000 + +// RB_COLOR_DEST_MASK +#define RB_COLOR_DEST_MASK__COLOR_DEST_MASK__SHIFT 0x00000000 + +// RB_COPY_CONTROL +#define RB_COPY_CONTROL__COPY_SAMPLE_SELECT__SHIFT 0x00000000 +#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x00000003 +#define RB_COPY_CONTROL__CLEAR_MASK__SHIFT 0x00000004 + +// RB_COPY_DEST_BASE +#define RB_COPY_DEST_BASE__COPY_DEST_BASE__SHIFT 0x0000000c + +// RB_COPY_DEST_PITCH +#define RB_COPY_DEST_PITCH__COPY_DEST_PITCH__SHIFT 0x00000000 + +// RB_COPY_DEST_INFO +#define RB_COPY_DEST_INFO__COPY_DEST_ENDIAN__SHIFT 0x00000000 +#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR__SHIFT 0x00000003 +#define RB_COPY_DEST_INFO__COPY_DEST_FORMAT__SHIFT 0x00000004 +#define RB_COPY_DEST_INFO__COPY_DEST_SWAP__SHIFT 0x00000008 +#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_MODE__SHIFT 0x0000000a +#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_TYPE__SHIFT 0x0000000c +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED__SHIFT 0x0000000e +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN__SHIFT 0x0000000f +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE__SHIFT 0x00000010 +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA__SHIFT 0x00000011 + +// RB_COPY_DEST_PIXEL_OFFSET +#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_X__SHIFT 0x00000000 +#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_Y__SHIFT 0x0000000d + +// RB_DEPTH_CLEAR +#define RB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x00000000 + +// RB_SAMPLE_COUNT_CTL +#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT__SHIFT 0x00000000 +#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT__SHIFT 0x00000001 + +// RB_SAMPLE_COUNT_ADDR +#define RB_SAMPLE_COUNT_ADDR__SAMPLE_COUNT_ADDR__SHIFT 0x00000000 + +// RB_BC_CONTROL +#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE__SHIFT 0x00000000 +#define RB_BC_CONTROL__ACCUM_TIMEOUT_SELECT__SHIFT 0x00000001 +#define RB_BC_CONTROL__DISABLE_EDRAM_CAM__SHIFT 0x00000003 +#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH__SHIFT 0x00000004 +#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP__SHIFT 0x00000005 +#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP__SHIFT 0x00000006 +#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE__SHIFT 0x00000007 +#define RB_BC_CONTROL__AZ_THROTTLE_COUNT__SHIFT 0x00000008 +#define RB_BC_CONTROL__ENABLE_CRC_UPDATE__SHIFT 0x0000000e +#define RB_BC_CONTROL__CRC_MODE__SHIFT 0x0000000f +#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS__SHIFT 0x00000010 +#define RB_BC_CONTROL__DISABLE_ACCUM__SHIFT 0x00000011 +#define RB_BC_CONTROL__ACCUM_ALLOC_MASK__SHIFT 0x00000012 +#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE__SHIFT 0x00000016 +#define RB_BC_CONTROL__ACCUM_DATA_FIFO_LIMIT__SHIFT 0x00000017 +#define RB_BC_CONTROL__MEM_EXPORT_TIMEOUT_SELECT__SHIFT 0x0000001b +#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE__SHIFT 0x0000001d +#define RB_BC_CONTROL__CRC_SYSTEM__SHIFT 0x0000001e +#define RB_BC_CONTROL__RESERVED6__SHIFT 0x0000001f + +// RB_EDRAM_INFO +#define RB_EDRAM_INFO__EDRAM_SIZE__SHIFT 0x00000000 +#define RB_EDRAM_INFO__EDRAM_MAPPING_MODE__SHIFT 0x00000004 +#define RB_EDRAM_INFO__EDRAM_RANGE__SHIFT 0x0000000e + +// RB_CRC_RD_PORT +#define RB_CRC_RD_PORT__CRC_DATA__SHIFT 0x00000000 + +// RB_CRC_CONTROL +#define RB_CRC_CONTROL__CRC_RD_ADVANCE__SHIFT 0x00000000 + +// RB_CRC_MASK +#define RB_CRC_MASK__CRC_MASK__SHIFT 0x00000000 + +// RB_PERFCOUNTER0_SELECT +#define RB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// RB_PERFCOUNTER0_LOW +#define RB_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// RB_PERFCOUNTER0_HI +#define RB_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// RB_TOTAL_SAMPLES +#define RB_TOTAL_SAMPLES__TOTAL_SAMPLES__SHIFT 0x00000000 + +// RB_ZPASS_SAMPLES +#define RB_ZPASS_SAMPLES__ZPASS_SAMPLES__SHIFT 0x00000000 + +// RB_ZFAIL_SAMPLES +#define RB_ZFAIL_SAMPLES__ZFAIL_SAMPLES__SHIFT 0x00000000 + +// RB_SFAIL_SAMPLES +#define RB_SFAIL_SAMPLES__SFAIL_SAMPLES__SHIFT 0x00000000 + +// RB_DEBUG_0 +#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL__SHIFT 0x00000000 +#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL__SHIFT 0x00000001 +#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL__SHIFT 0x00000002 +#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL__SHIFT 0x00000003 +#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL__SHIFT 0x00000004 +#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL__SHIFT 0x00000005 +#define RB_DEBUG_0__RDREQ_Z1_FULL__SHIFT 0x00000006 +#define RB_DEBUG_0__RDREQ_Z0_FULL__SHIFT 0x00000007 +#define RB_DEBUG_0__RDREQ_C1_FULL__SHIFT 0x00000008 +#define RB_DEBUG_0__RDREQ_C0_FULL__SHIFT 0x00000009 +#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL__SHIFT 0x0000000a +#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL__SHIFT 0x0000000b +#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL__SHIFT 0x0000000c +#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL__SHIFT 0x0000000d +#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL__SHIFT 0x0000000e +#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL__SHIFT 0x0000000f +#define RB_DEBUG_0__WRREQ_Z1_FULL__SHIFT 0x00000010 +#define RB_DEBUG_0__WRREQ_Z0_FULL__SHIFT 0x00000011 +#define RB_DEBUG_0__WRREQ_C1_FULL__SHIFT 0x00000012 +#define RB_DEBUG_0__WRREQ_C0_FULL__SHIFT 0x00000013 +#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL__SHIFT 0x00000014 +#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL__SHIFT 0x00000015 +#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL__SHIFT 0x00000016 +#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL__SHIFT 0x00000017 +#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL__SHIFT 0x00000018 +#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL__SHIFT 0x00000019 +#define RB_DEBUG_0__C_SX_LAT_FULL__SHIFT 0x0000001a +#define RB_DEBUG_0__C_SX_CMD_FULL__SHIFT 0x0000001b +#define RB_DEBUG_0__C_EZ_TILE_FULL__SHIFT 0x0000001c +#define RB_DEBUG_0__C_REQ_FULL__SHIFT 0x0000001d +#define RB_DEBUG_0__C_MASK_FULL__SHIFT 0x0000001e +#define RB_DEBUG_0__EZ_INFSAMP_FULL__SHIFT 0x0000001f + +// RB_DEBUG_1 +#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY__SHIFT 0x00000000 +#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY__SHIFT 0x00000001 +#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY__SHIFT 0x00000002 +#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY__SHIFT 0x00000003 +#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY__SHIFT 0x00000004 +#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY__SHIFT 0x00000005 +#define RB_DEBUG_1__RDREQ_Z1_EMPTY__SHIFT 0x00000006 +#define RB_DEBUG_1__RDREQ_Z0_EMPTY__SHIFT 0x00000007 +#define RB_DEBUG_1__RDREQ_C1_EMPTY__SHIFT 0x00000008 +#define RB_DEBUG_1__RDREQ_C0_EMPTY__SHIFT 0x00000009 +#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY__SHIFT 0x0000000a +#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY__SHIFT 0x0000000b +#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY__SHIFT 0x0000000c +#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY__SHIFT 0x0000000d +#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY__SHIFT 0x0000000e +#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY__SHIFT 0x0000000f +#define RB_DEBUG_1__WRREQ_Z1_EMPTY__SHIFT 0x00000010 +#define RB_DEBUG_1__WRREQ_Z0_EMPTY__SHIFT 0x00000011 +#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY__SHIFT 0x00000012 +#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY__SHIFT 0x00000013 +#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY__SHIFT 0x00000014 +#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY__SHIFT 0x00000015 +#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY__SHIFT 0x00000016 +#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY__SHIFT 0x00000017 +#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY__SHIFT 0x00000018 +#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY__SHIFT 0x00000019 +#define RB_DEBUG_1__C_SX_LAT_EMPTY__SHIFT 0x0000001a +#define RB_DEBUG_1__C_SX_CMD_EMPTY__SHIFT 0x0000001b +#define RB_DEBUG_1__C_EZ_TILE_EMPTY__SHIFT 0x0000001c +#define RB_DEBUG_1__C_REQ_EMPTY__SHIFT 0x0000001d +#define RB_DEBUG_1__C_MASK_EMPTY__SHIFT 0x0000001e +#define RB_DEBUG_1__EZ_INFSAMP_EMPTY__SHIFT 0x0000001f + +// RB_DEBUG_2 +#define RB_DEBUG_2__TILE_FIFO_COUNT__SHIFT 0x00000000 +#define RB_DEBUG_2__SX_LAT_FIFO_COUNT__SHIFT 0x00000004 +#define RB_DEBUG_2__MEM_EXPORT_FLAG__SHIFT 0x0000000b +#define RB_DEBUG_2__SYSMEM_BLEND_FLAG__SHIFT 0x0000000c +#define RB_DEBUG_2__CURRENT_TILE_EVENT__SHIFT 0x0000000d +#define RB_DEBUG_2__EZ_INFTILE_FULL__SHIFT 0x0000000e +#define RB_DEBUG_2__EZ_MASK_LOWER_FULL__SHIFT 0x0000000f +#define RB_DEBUG_2__EZ_MASK_UPPER_FULL__SHIFT 0x00000010 +#define RB_DEBUG_2__Z0_MASK_FULL__SHIFT 0x00000011 +#define RB_DEBUG_2__Z1_MASK_FULL__SHIFT 0x00000012 +#define RB_DEBUG_2__Z0_REQ_FULL__SHIFT 0x00000013 +#define RB_DEBUG_2__Z1_REQ_FULL__SHIFT 0x00000014 +#define RB_DEBUG_2__Z_SAMP_FULL__SHIFT 0x00000015 +#define RB_DEBUG_2__Z_TILE_FULL__SHIFT 0x00000016 +#define RB_DEBUG_2__EZ_INFTILE_EMPTY__SHIFT 0x00000017 +#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY__SHIFT 0x00000018 +#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY__SHIFT 0x00000019 +#define RB_DEBUG_2__Z0_MASK_EMPTY__SHIFT 0x0000001a +#define RB_DEBUG_2__Z1_MASK_EMPTY__SHIFT 0x0000001b +#define RB_DEBUG_2__Z0_REQ_EMPTY__SHIFT 0x0000001c +#define RB_DEBUG_2__Z1_REQ_EMPTY__SHIFT 0x0000001d +#define RB_DEBUG_2__Z_SAMP_EMPTY__SHIFT 0x0000001e +#define RB_DEBUG_2__Z_TILE_EMPTY__SHIFT 0x0000001f + +// RB_DEBUG_3 +#define RB_DEBUG_3__ACCUM_VALID__SHIFT 0x00000000 +#define RB_DEBUG_3__ACCUM_FLUSHING__SHIFT 0x00000004 +#define RB_DEBUG_3__ACCUM_WRITE_CLEAN_COUNT__SHIFT 0x00000008 +#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID__SHIFT 0x0000000e +#define RB_DEBUG_3__ACCUM_DATA_FIFO_CNT__SHIFT 0x0000000f +#define RB_DEBUG_3__SHD_FULL__SHIFT 0x00000013 +#define RB_DEBUG_3__SHD_EMPTY__SHIFT 0x00000014 +#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY__SHIFT 0x00000015 +#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY__SHIFT 0x00000016 +#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL__SHIFT 0x00000017 +#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL__SHIFT 0x00000018 +#define RB_DEBUG_3__ZEXP_LOWER_EMPTY__SHIFT 0x00000019 +#define RB_DEBUG_3__ZEXP_UPPER_EMPTY__SHIFT 0x0000001a +#define RB_DEBUG_3__ZEXP_LOWER_FULL__SHIFT 0x0000001b +#define RB_DEBUG_3__ZEXP_UPPER_FULL__SHIFT 0x0000001c + +// RB_DEBUG_4 +#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG__SHIFT 0x00000000 +#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG__SHIFT 0x00000001 +#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG__SHIFT 0x00000002 +#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG__SHIFT 0x00000003 +#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY__SHIFT 0x00000004 +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY__SHIFT 0x00000005 +#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL__SHIFT 0x00000006 +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL__SHIFT 0x00000007 +#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW__SHIFT 0x00000008 +#define RB_DEBUG_4__CONTEXT_COUNT_DEBUG__SHIFT 0x00000009 + +// RB_FLAG_CONTROL +#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR__SHIFT 0x00000000 + +// RB_BC_SPARES +#define RB_BC_SPARES__RESERVED__SHIFT 0x00000000 + +// BC_DUMMY_CRAYRB_ENUMS +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_FORMAT__SHIFT 0x00000000 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP__SHIFT 0x00000006 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_ARRAY__SHIFT 0x00000007 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_ARRAY__SHIFT 0x00000009 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_COLOR_FORMAT__SHIFT 0x0000000b +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_NUMBER__SHIFT 0x00000011 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_FORMAT__SHIFT 0x00000014 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING__SHIFT 0x0000001a +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_ARRAY__SHIFT 0x0000001b +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_RB_COPY_DEST_INFO_NUMBER__SHIFT 0x0000001d + +// BC_DUMMY_CRAYRB_MOREENUMS +#define BC_DUMMY_CRAYRB_MOREENUMS__DUMMY_CRAYRB_COLORARRAYX__SHIFT 0x00000000 + +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_struct.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_struct.h new file mode 100644 index 000000000000..9e9c7282dcdb --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_struct.h @@ -0,0 +1,52571 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_CP_FIDDLE_H) +#define _CP_FIDDLE_H + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * CP_RB_BASE struct + */ + +#define CP_RB_BASE_RB_BASE_SIZE 27 + +#define CP_RB_BASE_RB_BASE_SHIFT 5 + +#define CP_RB_BASE_RB_BASE_MASK 0xffffffe0 + +#define CP_RB_BASE_MASK \ + (CP_RB_BASE_RB_BASE_MASK) + +#define CP_RB_BASE(rb_base) \ + ((rb_base << CP_RB_BASE_RB_BASE_SHIFT)) + +#define CP_RB_BASE_GET_RB_BASE(cp_rb_base) \ + ((cp_rb_base & CP_RB_BASE_RB_BASE_MASK) >> CP_RB_BASE_RB_BASE_SHIFT) + +#define CP_RB_BASE_SET_RB_BASE(cp_rb_base_reg, rb_base) \ + cp_rb_base_reg = (cp_rb_base_reg & ~CP_RB_BASE_RB_BASE_MASK) | (rb_base << CP_RB_BASE_RB_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_base_t { + unsigned int : 5; + unsigned int rb_base : CP_RB_BASE_RB_BASE_SIZE; + } cp_rb_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_base_t { + unsigned int rb_base : CP_RB_BASE_RB_BASE_SIZE; + unsigned int : 5; + } cp_rb_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_base_t f; +} cp_rb_base_u; + + +/* + * CP_RB_CNTL struct + */ + +#define CP_RB_CNTL_RB_BUFSZ_SIZE 6 +#define CP_RB_CNTL_RB_BLKSZ_SIZE 6 +#define CP_RB_CNTL_BUF_SWAP_SIZE 2 +#define CP_RB_CNTL_RB_POLL_EN_SIZE 1 +#define CP_RB_CNTL_RB_NO_UPDATE_SIZE 1 +#define CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE 1 + +#define CP_RB_CNTL_RB_BUFSZ_SHIFT 0 +#define CP_RB_CNTL_RB_BLKSZ_SHIFT 8 +#define CP_RB_CNTL_BUF_SWAP_SHIFT 16 +#define CP_RB_CNTL_RB_POLL_EN_SHIFT 20 +#define CP_RB_CNTL_RB_NO_UPDATE_SHIFT 27 +#define CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT 31 + +#define CP_RB_CNTL_RB_BUFSZ_MASK 0x0000003f +#define CP_RB_CNTL_RB_BLKSZ_MASK 0x00003f00 +#define CP_RB_CNTL_BUF_SWAP_MASK 0x00030000 +#define CP_RB_CNTL_RB_POLL_EN_MASK 0x00100000 +#define CP_RB_CNTL_RB_NO_UPDATE_MASK 0x08000000 +#define CP_RB_CNTL_RB_RPTR_WR_ENA_MASK 0x80000000 + +#define CP_RB_CNTL_MASK \ + (CP_RB_CNTL_RB_BUFSZ_MASK | \ + CP_RB_CNTL_RB_BLKSZ_MASK | \ + CP_RB_CNTL_BUF_SWAP_MASK | \ + CP_RB_CNTL_RB_POLL_EN_MASK | \ + CP_RB_CNTL_RB_NO_UPDATE_MASK | \ + CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) + +#define CP_RB_CNTL(rb_bufsz, rb_blksz, buf_swap, rb_poll_en, rb_no_update, rb_rptr_wr_ena) \ + ((rb_bufsz << CP_RB_CNTL_RB_BUFSZ_SHIFT) | \ + (rb_blksz << CP_RB_CNTL_RB_BLKSZ_SHIFT) | \ + (buf_swap << CP_RB_CNTL_BUF_SWAP_SHIFT) | \ + (rb_poll_en << CP_RB_CNTL_RB_POLL_EN_SHIFT) | \ + (rb_no_update << CP_RB_CNTL_RB_NO_UPDATE_SHIFT) | \ + (rb_rptr_wr_ena << CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT)) + +#define CP_RB_CNTL_GET_RB_BUFSZ(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_BUFSZ_MASK) >> CP_RB_CNTL_RB_BUFSZ_SHIFT) +#define CP_RB_CNTL_GET_RB_BLKSZ(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_BLKSZ_MASK) >> CP_RB_CNTL_RB_BLKSZ_SHIFT) +#define CP_RB_CNTL_GET_BUF_SWAP(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_BUF_SWAP_MASK) >> CP_RB_CNTL_BUF_SWAP_SHIFT) +#define CP_RB_CNTL_GET_RB_POLL_EN(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_POLL_EN_MASK) >> CP_RB_CNTL_RB_POLL_EN_SHIFT) +#define CP_RB_CNTL_GET_RB_NO_UPDATE(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_NO_UPDATE_MASK) >> CP_RB_CNTL_RB_NO_UPDATE_SHIFT) +#define CP_RB_CNTL_GET_RB_RPTR_WR_ENA(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) >> CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT) + +#define CP_RB_CNTL_SET_RB_BUFSZ(cp_rb_cntl_reg, rb_bufsz) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_BUFSZ_MASK) | (rb_bufsz << CP_RB_CNTL_RB_BUFSZ_SHIFT) +#define CP_RB_CNTL_SET_RB_BLKSZ(cp_rb_cntl_reg, rb_blksz) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_BLKSZ_MASK) | (rb_blksz << CP_RB_CNTL_RB_BLKSZ_SHIFT) +#define CP_RB_CNTL_SET_BUF_SWAP(cp_rb_cntl_reg, buf_swap) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_BUF_SWAP_MASK) | (buf_swap << CP_RB_CNTL_BUF_SWAP_SHIFT) +#define CP_RB_CNTL_SET_RB_POLL_EN(cp_rb_cntl_reg, rb_poll_en) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_POLL_EN_MASK) | (rb_poll_en << CP_RB_CNTL_RB_POLL_EN_SHIFT) +#define CP_RB_CNTL_SET_RB_NO_UPDATE(cp_rb_cntl_reg, rb_no_update) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_NO_UPDATE_MASK) | (rb_no_update << CP_RB_CNTL_RB_NO_UPDATE_SHIFT) +#define CP_RB_CNTL_SET_RB_RPTR_WR_ENA(cp_rb_cntl_reg, rb_rptr_wr_ena) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) | (rb_rptr_wr_ena << CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_cntl_t { + unsigned int rb_bufsz : CP_RB_CNTL_RB_BUFSZ_SIZE; + unsigned int : 2; + unsigned int rb_blksz : CP_RB_CNTL_RB_BLKSZ_SIZE; + unsigned int : 2; + unsigned int buf_swap : CP_RB_CNTL_BUF_SWAP_SIZE; + unsigned int : 2; + unsigned int rb_poll_en : CP_RB_CNTL_RB_POLL_EN_SIZE; + unsigned int : 6; + unsigned int rb_no_update : CP_RB_CNTL_RB_NO_UPDATE_SIZE; + unsigned int : 3; + unsigned int rb_rptr_wr_ena : CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE; + } cp_rb_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_cntl_t { + unsigned int rb_rptr_wr_ena : CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE; + unsigned int : 3; + unsigned int rb_no_update : CP_RB_CNTL_RB_NO_UPDATE_SIZE; + unsigned int : 6; + unsigned int rb_poll_en : CP_RB_CNTL_RB_POLL_EN_SIZE; + unsigned int : 2; + unsigned int buf_swap : CP_RB_CNTL_BUF_SWAP_SIZE; + unsigned int : 2; + unsigned int rb_blksz : CP_RB_CNTL_RB_BLKSZ_SIZE; + unsigned int : 2; + unsigned int rb_bufsz : CP_RB_CNTL_RB_BUFSZ_SIZE; + } cp_rb_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_cntl_t f; +} cp_rb_cntl_u; + + +/* + * CP_RB_RPTR_ADDR struct + */ + +#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE 2 +#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE 30 + +#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT 0 +#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT 2 + +#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK 0x00000003 +#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK 0xfffffffc + +#define CP_RB_RPTR_ADDR_MASK \ + (CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK | \ + CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) + +#define CP_RB_RPTR_ADDR(rb_rptr_swap, rb_rptr_addr) \ + ((rb_rptr_swap << CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT) | \ + (rb_rptr_addr << CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT)) + +#define CP_RB_RPTR_ADDR_GET_RB_RPTR_SWAP(cp_rb_rptr_addr) \ + ((cp_rb_rptr_addr & CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK) >> CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT) +#define CP_RB_RPTR_ADDR_GET_RB_RPTR_ADDR(cp_rb_rptr_addr) \ + ((cp_rb_rptr_addr & CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) >> CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT) + +#define CP_RB_RPTR_ADDR_SET_RB_RPTR_SWAP(cp_rb_rptr_addr_reg, rb_rptr_swap) \ + cp_rb_rptr_addr_reg = (cp_rb_rptr_addr_reg & ~CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK) | (rb_rptr_swap << CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT) +#define CP_RB_RPTR_ADDR_SET_RB_RPTR_ADDR(cp_rb_rptr_addr_reg, rb_rptr_addr) \ + cp_rb_rptr_addr_reg = (cp_rb_rptr_addr_reg & ~CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) | (rb_rptr_addr << CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_rptr_addr_t { + unsigned int rb_rptr_swap : CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE; + unsigned int rb_rptr_addr : CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE; + } cp_rb_rptr_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_rptr_addr_t { + unsigned int rb_rptr_addr : CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE; + unsigned int rb_rptr_swap : CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE; + } cp_rb_rptr_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_rptr_addr_t f; +} cp_rb_rptr_addr_u; + + +/* + * CP_RB_RPTR struct + */ + +#define CP_RB_RPTR_RB_RPTR_SIZE 20 + +#define CP_RB_RPTR_RB_RPTR_SHIFT 0 + +#define CP_RB_RPTR_RB_RPTR_MASK 0x000fffff + +#define CP_RB_RPTR_MASK \ + (CP_RB_RPTR_RB_RPTR_MASK) + +#define CP_RB_RPTR(rb_rptr) \ + ((rb_rptr << CP_RB_RPTR_RB_RPTR_SHIFT)) + +#define CP_RB_RPTR_GET_RB_RPTR(cp_rb_rptr) \ + ((cp_rb_rptr & CP_RB_RPTR_RB_RPTR_MASK) >> CP_RB_RPTR_RB_RPTR_SHIFT) + +#define CP_RB_RPTR_SET_RB_RPTR(cp_rb_rptr_reg, rb_rptr) \ + cp_rb_rptr_reg = (cp_rb_rptr_reg & ~CP_RB_RPTR_RB_RPTR_MASK) | (rb_rptr << CP_RB_RPTR_RB_RPTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_rptr_t { + unsigned int rb_rptr : CP_RB_RPTR_RB_RPTR_SIZE; + unsigned int : 12; + } cp_rb_rptr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_rptr_t { + unsigned int : 12; + unsigned int rb_rptr : CP_RB_RPTR_RB_RPTR_SIZE; + } cp_rb_rptr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_rptr_t f; +} cp_rb_rptr_u; + + +/* + * CP_RB_RPTR_WR struct + */ + +#define CP_RB_RPTR_WR_RB_RPTR_WR_SIZE 20 + +#define CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT 0 + +#define CP_RB_RPTR_WR_RB_RPTR_WR_MASK 0x000fffff + +#define CP_RB_RPTR_WR_MASK \ + (CP_RB_RPTR_WR_RB_RPTR_WR_MASK) + +#define CP_RB_RPTR_WR(rb_rptr_wr) \ + ((rb_rptr_wr << CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT)) + +#define CP_RB_RPTR_WR_GET_RB_RPTR_WR(cp_rb_rptr_wr) \ + ((cp_rb_rptr_wr & CP_RB_RPTR_WR_RB_RPTR_WR_MASK) >> CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT) + +#define CP_RB_RPTR_WR_SET_RB_RPTR_WR(cp_rb_rptr_wr_reg, rb_rptr_wr) \ + cp_rb_rptr_wr_reg = (cp_rb_rptr_wr_reg & ~CP_RB_RPTR_WR_RB_RPTR_WR_MASK) | (rb_rptr_wr << CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_rptr_wr_t { + unsigned int rb_rptr_wr : CP_RB_RPTR_WR_RB_RPTR_WR_SIZE; + unsigned int : 12; + } cp_rb_rptr_wr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_rptr_wr_t { + unsigned int : 12; + unsigned int rb_rptr_wr : CP_RB_RPTR_WR_RB_RPTR_WR_SIZE; + } cp_rb_rptr_wr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_rptr_wr_t f; +} cp_rb_rptr_wr_u; + + +/* + * CP_RB_WPTR struct + */ + +#define CP_RB_WPTR_RB_WPTR_SIZE 20 + +#define CP_RB_WPTR_RB_WPTR_SHIFT 0 + +#define CP_RB_WPTR_RB_WPTR_MASK 0x000fffff + +#define CP_RB_WPTR_MASK \ + (CP_RB_WPTR_RB_WPTR_MASK) + +#define CP_RB_WPTR(rb_wptr) \ + ((rb_wptr << CP_RB_WPTR_RB_WPTR_SHIFT)) + +#define CP_RB_WPTR_GET_RB_WPTR(cp_rb_wptr) \ + ((cp_rb_wptr & CP_RB_WPTR_RB_WPTR_MASK) >> CP_RB_WPTR_RB_WPTR_SHIFT) + +#define CP_RB_WPTR_SET_RB_WPTR(cp_rb_wptr_reg, rb_wptr) \ + cp_rb_wptr_reg = (cp_rb_wptr_reg & ~CP_RB_WPTR_RB_WPTR_MASK) | (rb_wptr << CP_RB_WPTR_RB_WPTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_wptr_t { + unsigned int rb_wptr : CP_RB_WPTR_RB_WPTR_SIZE; + unsigned int : 12; + } cp_rb_wptr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_wptr_t { + unsigned int : 12; + unsigned int rb_wptr : CP_RB_WPTR_RB_WPTR_SIZE; + } cp_rb_wptr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_wptr_t f; +} cp_rb_wptr_u; + + +/* + * CP_RB_WPTR_DELAY struct + */ + +#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE 28 +#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE 4 + +#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT 0 +#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT 28 + +#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK 0x0fffffff +#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK 0xf0000000 + +#define CP_RB_WPTR_DELAY_MASK \ + (CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK | \ + CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) + +#define CP_RB_WPTR_DELAY(pre_write_timer, pre_write_limit) \ + ((pre_write_timer << CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT) | \ + (pre_write_limit << CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT)) + +#define CP_RB_WPTR_DELAY_GET_PRE_WRITE_TIMER(cp_rb_wptr_delay) \ + ((cp_rb_wptr_delay & CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK) >> CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT) +#define CP_RB_WPTR_DELAY_GET_PRE_WRITE_LIMIT(cp_rb_wptr_delay) \ + ((cp_rb_wptr_delay & CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) >> CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT) + +#define CP_RB_WPTR_DELAY_SET_PRE_WRITE_TIMER(cp_rb_wptr_delay_reg, pre_write_timer) \ + cp_rb_wptr_delay_reg = (cp_rb_wptr_delay_reg & ~CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK) | (pre_write_timer << CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT) +#define CP_RB_WPTR_DELAY_SET_PRE_WRITE_LIMIT(cp_rb_wptr_delay_reg, pre_write_limit) \ + cp_rb_wptr_delay_reg = (cp_rb_wptr_delay_reg & ~CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) | (pre_write_limit << CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_wptr_delay_t { + unsigned int pre_write_timer : CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE; + unsigned int pre_write_limit : CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE; + } cp_rb_wptr_delay_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_wptr_delay_t { + unsigned int pre_write_limit : CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE; + unsigned int pre_write_timer : CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE; + } cp_rb_wptr_delay_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_wptr_delay_t f; +} cp_rb_wptr_delay_u; + + +/* + * CP_RB_WPTR_BASE struct + */ + +#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE 2 +#define CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE 30 + +#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT 0 +#define CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT 2 + +#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK 0x00000003 +#define CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK 0xfffffffc + +#define CP_RB_WPTR_BASE_MASK \ + (CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK | \ + CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) + +#define CP_RB_WPTR_BASE(rb_wptr_swap, rb_wptr_base) \ + ((rb_wptr_swap << CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT) | \ + (rb_wptr_base << CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT)) + +#define CP_RB_WPTR_BASE_GET_RB_WPTR_SWAP(cp_rb_wptr_base) \ + ((cp_rb_wptr_base & CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK) >> CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT) +#define CP_RB_WPTR_BASE_GET_RB_WPTR_BASE(cp_rb_wptr_base) \ + ((cp_rb_wptr_base & CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) >> CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT) + +#define CP_RB_WPTR_BASE_SET_RB_WPTR_SWAP(cp_rb_wptr_base_reg, rb_wptr_swap) \ + cp_rb_wptr_base_reg = (cp_rb_wptr_base_reg & ~CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK) | (rb_wptr_swap << CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT) +#define CP_RB_WPTR_BASE_SET_RB_WPTR_BASE(cp_rb_wptr_base_reg, rb_wptr_base) \ + cp_rb_wptr_base_reg = (cp_rb_wptr_base_reg & ~CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) | (rb_wptr_base << CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_wptr_base_t { + unsigned int rb_wptr_swap : CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE; + unsigned int rb_wptr_base : CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE; + } cp_rb_wptr_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_wptr_base_t { + unsigned int rb_wptr_base : CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE; + unsigned int rb_wptr_swap : CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE; + } cp_rb_wptr_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_wptr_base_t f; +} cp_rb_wptr_base_u; + + +/* + * CP_IB1_BASE struct + */ + +#define CP_IB1_BASE_IB1_BASE_SIZE 30 + +#define CP_IB1_BASE_IB1_BASE_SHIFT 2 + +#define CP_IB1_BASE_IB1_BASE_MASK 0xfffffffc + +#define CP_IB1_BASE_MASK \ + (CP_IB1_BASE_IB1_BASE_MASK) + +#define CP_IB1_BASE(ib1_base) \ + ((ib1_base << CP_IB1_BASE_IB1_BASE_SHIFT)) + +#define CP_IB1_BASE_GET_IB1_BASE(cp_ib1_base) \ + ((cp_ib1_base & CP_IB1_BASE_IB1_BASE_MASK) >> CP_IB1_BASE_IB1_BASE_SHIFT) + +#define CP_IB1_BASE_SET_IB1_BASE(cp_ib1_base_reg, ib1_base) \ + cp_ib1_base_reg = (cp_ib1_base_reg & ~CP_IB1_BASE_IB1_BASE_MASK) | (ib1_base << CP_IB1_BASE_IB1_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_ib1_base_t { + unsigned int : 2; + unsigned int ib1_base : CP_IB1_BASE_IB1_BASE_SIZE; + } cp_ib1_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_ib1_base_t { + unsigned int ib1_base : CP_IB1_BASE_IB1_BASE_SIZE; + unsigned int : 2; + } cp_ib1_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_ib1_base_t f; +} cp_ib1_base_u; + + +/* + * CP_IB1_BUFSZ struct + */ + +#define CP_IB1_BUFSZ_IB1_BUFSZ_SIZE 20 + +#define CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT 0 + +#define CP_IB1_BUFSZ_IB1_BUFSZ_MASK 0x000fffff + +#define CP_IB1_BUFSZ_MASK \ + (CP_IB1_BUFSZ_IB1_BUFSZ_MASK) + +#define CP_IB1_BUFSZ(ib1_bufsz) \ + ((ib1_bufsz << CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT)) + +#define CP_IB1_BUFSZ_GET_IB1_BUFSZ(cp_ib1_bufsz) \ + ((cp_ib1_bufsz & CP_IB1_BUFSZ_IB1_BUFSZ_MASK) >> CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT) + +#define CP_IB1_BUFSZ_SET_IB1_BUFSZ(cp_ib1_bufsz_reg, ib1_bufsz) \ + cp_ib1_bufsz_reg = (cp_ib1_bufsz_reg & ~CP_IB1_BUFSZ_IB1_BUFSZ_MASK) | (ib1_bufsz << CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_ib1_bufsz_t { + unsigned int ib1_bufsz : CP_IB1_BUFSZ_IB1_BUFSZ_SIZE; + unsigned int : 12; + } cp_ib1_bufsz_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_ib1_bufsz_t { + unsigned int : 12; + unsigned int ib1_bufsz : CP_IB1_BUFSZ_IB1_BUFSZ_SIZE; + } cp_ib1_bufsz_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_ib1_bufsz_t f; +} cp_ib1_bufsz_u; + + +/* + * CP_IB2_BASE struct + */ + +#define CP_IB2_BASE_IB2_BASE_SIZE 30 + +#define CP_IB2_BASE_IB2_BASE_SHIFT 2 + +#define CP_IB2_BASE_IB2_BASE_MASK 0xfffffffc + +#define CP_IB2_BASE_MASK \ + (CP_IB2_BASE_IB2_BASE_MASK) + +#define CP_IB2_BASE(ib2_base) \ + ((ib2_base << CP_IB2_BASE_IB2_BASE_SHIFT)) + +#define CP_IB2_BASE_GET_IB2_BASE(cp_ib2_base) \ + ((cp_ib2_base & CP_IB2_BASE_IB2_BASE_MASK) >> CP_IB2_BASE_IB2_BASE_SHIFT) + +#define CP_IB2_BASE_SET_IB2_BASE(cp_ib2_base_reg, ib2_base) \ + cp_ib2_base_reg = (cp_ib2_base_reg & ~CP_IB2_BASE_IB2_BASE_MASK) | (ib2_base << CP_IB2_BASE_IB2_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_ib2_base_t { + unsigned int : 2; + unsigned int ib2_base : CP_IB2_BASE_IB2_BASE_SIZE; + } cp_ib2_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_ib2_base_t { + unsigned int ib2_base : CP_IB2_BASE_IB2_BASE_SIZE; + unsigned int : 2; + } cp_ib2_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_ib2_base_t f; +} cp_ib2_base_u; + + +/* + * CP_IB2_BUFSZ struct + */ + +#define CP_IB2_BUFSZ_IB2_BUFSZ_SIZE 20 + +#define CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT 0 + +#define CP_IB2_BUFSZ_IB2_BUFSZ_MASK 0x000fffff + +#define CP_IB2_BUFSZ_MASK \ + (CP_IB2_BUFSZ_IB2_BUFSZ_MASK) + +#define CP_IB2_BUFSZ(ib2_bufsz) \ + ((ib2_bufsz << CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT)) + +#define CP_IB2_BUFSZ_GET_IB2_BUFSZ(cp_ib2_bufsz) \ + ((cp_ib2_bufsz & CP_IB2_BUFSZ_IB2_BUFSZ_MASK) >> CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT) + +#define CP_IB2_BUFSZ_SET_IB2_BUFSZ(cp_ib2_bufsz_reg, ib2_bufsz) \ + cp_ib2_bufsz_reg = (cp_ib2_bufsz_reg & ~CP_IB2_BUFSZ_IB2_BUFSZ_MASK) | (ib2_bufsz << CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_ib2_bufsz_t { + unsigned int ib2_bufsz : CP_IB2_BUFSZ_IB2_BUFSZ_SIZE; + unsigned int : 12; + } cp_ib2_bufsz_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_ib2_bufsz_t { + unsigned int : 12; + unsigned int ib2_bufsz : CP_IB2_BUFSZ_IB2_BUFSZ_SIZE; + } cp_ib2_bufsz_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_ib2_bufsz_t f; +} cp_ib2_bufsz_u; + + +/* + * CP_ST_BASE struct + */ + +#define CP_ST_BASE_ST_BASE_SIZE 30 + +#define CP_ST_BASE_ST_BASE_SHIFT 2 + +#define CP_ST_BASE_ST_BASE_MASK 0xfffffffc + +#define CP_ST_BASE_MASK \ + (CP_ST_BASE_ST_BASE_MASK) + +#define CP_ST_BASE(st_base) \ + ((st_base << CP_ST_BASE_ST_BASE_SHIFT)) + +#define CP_ST_BASE_GET_ST_BASE(cp_st_base) \ + ((cp_st_base & CP_ST_BASE_ST_BASE_MASK) >> CP_ST_BASE_ST_BASE_SHIFT) + +#define CP_ST_BASE_SET_ST_BASE(cp_st_base_reg, st_base) \ + cp_st_base_reg = (cp_st_base_reg & ~CP_ST_BASE_ST_BASE_MASK) | (st_base << CP_ST_BASE_ST_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_st_base_t { + unsigned int : 2; + unsigned int st_base : CP_ST_BASE_ST_BASE_SIZE; + } cp_st_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_st_base_t { + unsigned int st_base : CP_ST_BASE_ST_BASE_SIZE; + unsigned int : 2; + } cp_st_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_st_base_t f; +} cp_st_base_u; + + +/* + * CP_ST_BUFSZ struct + */ + +#define CP_ST_BUFSZ_ST_BUFSZ_SIZE 20 + +#define CP_ST_BUFSZ_ST_BUFSZ_SHIFT 0 + +#define CP_ST_BUFSZ_ST_BUFSZ_MASK 0x000fffff + +#define CP_ST_BUFSZ_MASK \ + (CP_ST_BUFSZ_ST_BUFSZ_MASK) + +#define CP_ST_BUFSZ(st_bufsz) \ + ((st_bufsz << CP_ST_BUFSZ_ST_BUFSZ_SHIFT)) + +#define CP_ST_BUFSZ_GET_ST_BUFSZ(cp_st_bufsz) \ + ((cp_st_bufsz & CP_ST_BUFSZ_ST_BUFSZ_MASK) >> CP_ST_BUFSZ_ST_BUFSZ_SHIFT) + +#define CP_ST_BUFSZ_SET_ST_BUFSZ(cp_st_bufsz_reg, st_bufsz) \ + cp_st_bufsz_reg = (cp_st_bufsz_reg & ~CP_ST_BUFSZ_ST_BUFSZ_MASK) | (st_bufsz << CP_ST_BUFSZ_ST_BUFSZ_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_st_bufsz_t { + unsigned int st_bufsz : CP_ST_BUFSZ_ST_BUFSZ_SIZE; + unsigned int : 12; + } cp_st_bufsz_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_st_bufsz_t { + unsigned int : 12; + unsigned int st_bufsz : CP_ST_BUFSZ_ST_BUFSZ_SIZE; + } cp_st_bufsz_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_st_bufsz_t f; +} cp_st_bufsz_u; + + +/* + * CP_QUEUE_THRESHOLDS struct + */ + +#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE 4 +#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE 4 +#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE 4 + +#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT 0 +#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT 8 +#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT 16 + +#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK 0x0000000f +#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK 0x00000f00 +#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK 0x000f0000 + +#define CP_QUEUE_THRESHOLDS_MASK \ + (CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK | \ + CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK | \ + CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) + +#define CP_QUEUE_THRESHOLDS(csq_ib1_start, csq_ib2_start, csq_st_start) \ + ((csq_ib1_start << CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT) | \ + (csq_ib2_start << CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT) | \ + (csq_st_start << CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT)) + +#define CP_QUEUE_THRESHOLDS_GET_CSQ_IB1_START(cp_queue_thresholds) \ + ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT) +#define CP_QUEUE_THRESHOLDS_GET_CSQ_IB2_START(cp_queue_thresholds) \ + ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT) +#define CP_QUEUE_THRESHOLDS_GET_CSQ_ST_START(cp_queue_thresholds) \ + ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT) + +#define CP_QUEUE_THRESHOLDS_SET_CSQ_IB1_START(cp_queue_thresholds_reg, csq_ib1_start) \ + cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK) | (csq_ib1_start << CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT) +#define CP_QUEUE_THRESHOLDS_SET_CSQ_IB2_START(cp_queue_thresholds_reg, csq_ib2_start) \ + cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK) | (csq_ib2_start << CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT) +#define CP_QUEUE_THRESHOLDS_SET_CSQ_ST_START(cp_queue_thresholds_reg, csq_st_start) \ + cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) | (csq_st_start << CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_queue_thresholds_t { + unsigned int csq_ib1_start : CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE; + unsigned int : 4; + unsigned int csq_ib2_start : CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE; + unsigned int : 4; + unsigned int csq_st_start : CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE; + unsigned int : 12; + } cp_queue_thresholds_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_queue_thresholds_t { + unsigned int : 12; + unsigned int csq_st_start : CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE; + unsigned int : 4; + unsigned int csq_ib2_start : CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE; + unsigned int : 4; + unsigned int csq_ib1_start : CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE; + } cp_queue_thresholds_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_queue_thresholds_t f; +} cp_queue_thresholds_u; + + +/* + * CP_MEQ_THRESHOLDS struct + */ + +#define CP_MEQ_THRESHOLDS_MEQ_END_SIZE 5 +#define CP_MEQ_THRESHOLDS_ROQ_END_SIZE 5 + +#define CP_MEQ_THRESHOLDS_MEQ_END_SHIFT 16 +#define CP_MEQ_THRESHOLDS_ROQ_END_SHIFT 24 + +#define CP_MEQ_THRESHOLDS_MEQ_END_MASK 0x001f0000 +#define CP_MEQ_THRESHOLDS_ROQ_END_MASK 0x1f000000 + +#define CP_MEQ_THRESHOLDS_MASK \ + (CP_MEQ_THRESHOLDS_MEQ_END_MASK | \ + CP_MEQ_THRESHOLDS_ROQ_END_MASK) + +#define CP_MEQ_THRESHOLDS(meq_end, roq_end) \ + ((meq_end << CP_MEQ_THRESHOLDS_MEQ_END_SHIFT) | \ + (roq_end << CP_MEQ_THRESHOLDS_ROQ_END_SHIFT)) + +#define CP_MEQ_THRESHOLDS_GET_MEQ_END(cp_meq_thresholds) \ + ((cp_meq_thresholds & CP_MEQ_THRESHOLDS_MEQ_END_MASK) >> CP_MEQ_THRESHOLDS_MEQ_END_SHIFT) +#define CP_MEQ_THRESHOLDS_GET_ROQ_END(cp_meq_thresholds) \ + ((cp_meq_thresholds & CP_MEQ_THRESHOLDS_ROQ_END_MASK) >> CP_MEQ_THRESHOLDS_ROQ_END_SHIFT) + +#define CP_MEQ_THRESHOLDS_SET_MEQ_END(cp_meq_thresholds_reg, meq_end) \ + cp_meq_thresholds_reg = (cp_meq_thresholds_reg & ~CP_MEQ_THRESHOLDS_MEQ_END_MASK) | (meq_end << CP_MEQ_THRESHOLDS_MEQ_END_SHIFT) +#define CP_MEQ_THRESHOLDS_SET_ROQ_END(cp_meq_thresholds_reg, roq_end) \ + cp_meq_thresholds_reg = (cp_meq_thresholds_reg & ~CP_MEQ_THRESHOLDS_ROQ_END_MASK) | (roq_end << CP_MEQ_THRESHOLDS_ROQ_END_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_meq_thresholds_t { + unsigned int : 16; + unsigned int meq_end : CP_MEQ_THRESHOLDS_MEQ_END_SIZE; + unsigned int : 3; + unsigned int roq_end : CP_MEQ_THRESHOLDS_ROQ_END_SIZE; + unsigned int : 3; + } cp_meq_thresholds_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_meq_thresholds_t { + unsigned int : 3; + unsigned int roq_end : CP_MEQ_THRESHOLDS_ROQ_END_SIZE; + unsigned int : 3; + unsigned int meq_end : CP_MEQ_THRESHOLDS_MEQ_END_SIZE; + unsigned int : 16; + } cp_meq_thresholds_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_meq_thresholds_t f; +} cp_meq_thresholds_u; + + +/* + * CP_CSQ_AVAIL struct + */ + +#define CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE 7 +#define CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE 7 +#define CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE 7 + +#define CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT 0 +#define CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT 8 +#define CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT 16 + +#define CP_CSQ_AVAIL_CSQ_CNT_RING_MASK 0x0000007f +#define CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK 0x00007f00 +#define CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK 0x007f0000 + +#define CP_CSQ_AVAIL_MASK \ + (CP_CSQ_AVAIL_CSQ_CNT_RING_MASK | \ + CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK | \ + CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) + +#define CP_CSQ_AVAIL(csq_cnt_ring, csq_cnt_ib1, csq_cnt_ib2) \ + ((csq_cnt_ring << CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT) | \ + (csq_cnt_ib1 << CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT) | \ + (csq_cnt_ib2 << CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT)) + +#define CP_CSQ_AVAIL_GET_CSQ_CNT_RING(cp_csq_avail) \ + ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_RING_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT) +#define CP_CSQ_AVAIL_GET_CSQ_CNT_IB1(cp_csq_avail) \ + ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT) +#define CP_CSQ_AVAIL_GET_CSQ_CNT_IB2(cp_csq_avail) \ + ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT) + +#define CP_CSQ_AVAIL_SET_CSQ_CNT_RING(cp_csq_avail_reg, csq_cnt_ring) \ + cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_RING_MASK) | (csq_cnt_ring << CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT) +#define CP_CSQ_AVAIL_SET_CSQ_CNT_IB1(cp_csq_avail_reg, csq_cnt_ib1) \ + cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK) | (csq_cnt_ib1 << CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT) +#define CP_CSQ_AVAIL_SET_CSQ_CNT_IB2(cp_csq_avail_reg, csq_cnt_ib2) \ + cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) | (csq_cnt_ib2 << CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_csq_avail_t { + unsigned int csq_cnt_ring : CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE; + unsigned int : 1; + unsigned int csq_cnt_ib1 : CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE; + unsigned int : 1; + unsigned int csq_cnt_ib2 : CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE; + unsigned int : 9; + } cp_csq_avail_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_csq_avail_t { + unsigned int : 9; + unsigned int csq_cnt_ib2 : CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE; + unsigned int : 1; + unsigned int csq_cnt_ib1 : CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE; + unsigned int : 1; + unsigned int csq_cnt_ring : CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE; + } cp_csq_avail_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_csq_avail_t f; +} cp_csq_avail_u; + + +/* + * CP_STQ_AVAIL struct + */ + +#define CP_STQ_AVAIL_STQ_CNT_ST_SIZE 7 + +#define CP_STQ_AVAIL_STQ_CNT_ST_SHIFT 0 + +#define CP_STQ_AVAIL_STQ_CNT_ST_MASK 0x0000007f + +#define CP_STQ_AVAIL_MASK \ + (CP_STQ_AVAIL_STQ_CNT_ST_MASK) + +#define CP_STQ_AVAIL(stq_cnt_st) \ + ((stq_cnt_st << CP_STQ_AVAIL_STQ_CNT_ST_SHIFT)) + +#define CP_STQ_AVAIL_GET_STQ_CNT_ST(cp_stq_avail) \ + ((cp_stq_avail & CP_STQ_AVAIL_STQ_CNT_ST_MASK) >> CP_STQ_AVAIL_STQ_CNT_ST_SHIFT) + +#define CP_STQ_AVAIL_SET_STQ_CNT_ST(cp_stq_avail_reg, stq_cnt_st) \ + cp_stq_avail_reg = (cp_stq_avail_reg & ~CP_STQ_AVAIL_STQ_CNT_ST_MASK) | (stq_cnt_st << CP_STQ_AVAIL_STQ_CNT_ST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_stq_avail_t { + unsigned int stq_cnt_st : CP_STQ_AVAIL_STQ_CNT_ST_SIZE; + unsigned int : 25; + } cp_stq_avail_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_stq_avail_t { + unsigned int : 25; + unsigned int stq_cnt_st : CP_STQ_AVAIL_STQ_CNT_ST_SIZE; + } cp_stq_avail_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_stq_avail_t f; +} cp_stq_avail_u; + + +/* + * CP_MEQ_AVAIL struct + */ + +#define CP_MEQ_AVAIL_MEQ_CNT_SIZE 5 + +#define CP_MEQ_AVAIL_MEQ_CNT_SHIFT 0 + +#define CP_MEQ_AVAIL_MEQ_CNT_MASK 0x0000001f + +#define CP_MEQ_AVAIL_MASK \ + (CP_MEQ_AVAIL_MEQ_CNT_MASK) + +#define CP_MEQ_AVAIL(meq_cnt) \ + ((meq_cnt << CP_MEQ_AVAIL_MEQ_CNT_SHIFT)) + +#define CP_MEQ_AVAIL_GET_MEQ_CNT(cp_meq_avail) \ + ((cp_meq_avail & CP_MEQ_AVAIL_MEQ_CNT_MASK) >> CP_MEQ_AVAIL_MEQ_CNT_SHIFT) + +#define CP_MEQ_AVAIL_SET_MEQ_CNT(cp_meq_avail_reg, meq_cnt) \ + cp_meq_avail_reg = (cp_meq_avail_reg & ~CP_MEQ_AVAIL_MEQ_CNT_MASK) | (meq_cnt << CP_MEQ_AVAIL_MEQ_CNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_meq_avail_t { + unsigned int meq_cnt : CP_MEQ_AVAIL_MEQ_CNT_SIZE; + unsigned int : 27; + } cp_meq_avail_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_meq_avail_t { + unsigned int : 27; + unsigned int meq_cnt : CP_MEQ_AVAIL_MEQ_CNT_SIZE; + } cp_meq_avail_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_meq_avail_t f; +} cp_meq_avail_u; + + +/* + * CP_CSQ_RB_STAT struct + */ + +#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE 7 +#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE 7 + +#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT 0 +#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT 16 + +#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK 0x0000007f +#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK 0x007f0000 + +#define CP_CSQ_RB_STAT_MASK \ + (CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK | \ + CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) + +#define CP_CSQ_RB_STAT(csq_rptr_primary, csq_wptr_primary) \ + ((csq_rptr_primary << CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT) | \ + (csq_wptr_primary << CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT)) + +#define CP_CSQ_RB_STAT_GET_CSQ_RPTR_PRIMARY(cp_csq_rb_stat) \ + ((cp_csq_rb_stat & CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK) >> CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT) +#define CP_CSQ_RB_STAT_GET_CSQ_WPTR_PRIMARY(cp_csq_rb_stat) \ + ((cp_csq_rb_stat & CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) >> CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT) + +#define CP_CSQ_RB_STAT_SET_CSQ_RPTR_PRIMARY(cp_csq_rb_stat_reg, csq_rptr_primary) \ + cp_csq_rb_stat_reg = (cp_csq_rb_stat_reg & ~CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK) | (csq_rptr_primary << CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT) +#define CP_CSQ_RB_STAT_SET_CSQ_WPTR_PRIMARY(cp_csq_rb_stat_reg, csq_wptr_primary) \ + cp_csq_rb_stat_reg = (cp_csq_rb_stat_reg & ~CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) | (csq_wptr_primary << CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_csq_rb_stat_t { + unsigned int csq_rptr_primary : CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE; + unsigned int : 9; + unsigned int csq_wptr_primary : CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE; + unsigned int : 9; + } cp_csq_rb_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_csq_rb_stat_t { + unsigned int : 9; + unsigned int csq_wptr_primary : CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE; + unsigned int : 9; + unsigned int csq_rptr_primary : CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE; + } cp_csq_rb_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_csq_rb_stat_t f; +} cp_csq_rb_stat_u; + + +/* + * CP_CSQ_IB1_STAT struct + */ + +#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE 7 +#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE 7 + +#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT 0 +#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT 16 + +#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK 0x0000007f +#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK 0x007f0000 + +#define CP_CSQ_IB1_STAT_MASK \ + (CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK | \ + CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) + +#define CP_CSQ_IB1_STAT(csq_rptr_indirect1, csq_wptr_indirect1) \ + ((csq_rptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT) | \ + (csq_wptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT)) + +#define CP_CSQ_IB1_STAT_GET_CSQ_RPTR_INDIRECT1(cp_csq_ib1_stat) \ + ((cp_csq_ib1_stat & CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK) >> CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT) +#define CP_CSQ_IB1_STAT_GET_CSQ_WPTR_INDIRECT1(cp_csq_ib1_stat) \ + ((cp_csq_ib1_stat & CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) >> CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT) + +#define CP_CSQ_IB1_STAT_SET_CSQ_RPTR_INDIRECT1(cp_csq_ib1_stat_reg, csq_rptr_indirect1) \ + cp_csq_ib1_stat_reg = (cp_csq_ib1_stat_reg & ~CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK) | (csq_rptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT) +#define CP_CSQ_IB1_STAT_SET_CSQ_WPTR_INDIRECT1(cp_csq_ib1_stat_reg, csq_wptr_indirect1) \ + cp_csq_ib1_stat_reg = (cp_csq_ib1_stat_reg & ~CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) | (csq_wptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_csq_ib1_stat_t { + unsigned int csq_rptr_indirect1 : CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE; + unsigned int : 9; + unsigned int csq_wptr_indirect1 : CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE; + unsigned int : 9; + } cp_csq_ib1_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_csq_ib1_stat_t { + unsigned int : 9; + unsigned int csq_wptr_indirect1 : CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE; + unsigned int : 9; + unsigned int csq_rptr_indirect1 : CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE; + } cp_csq_ib1_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_csq_ib1_stat_t f; +} cp_csq_ib1_stat_u; + + +/* + * CP_CSQ_IB2_STAT struct + */ + +#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE 7 +#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE 7 + +#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT 0 +#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT 16 + +#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK 0x0000007f +#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK 0x007f0000 + +#define CP_CSQ_IB2_STAT_MASK \ + (CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK | \ + CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) + +#define CP_CSQ_IB2_STAT(csq_rptr_indirect2, csq_wptr_indirect2) \ + ((csq_rptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT) | \ + (csq_wptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT)) + +#define CP_CSQ_IB2_STAT_GET_CSQ_RPTR_INDIRECT2(cp_csq_ib2_stat) \ + ((cp_csq_ib2_stat & CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK) >> CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT) +#define CP_CSQ_IB2_STAT_GET_CSQ_WPTR_INDIRECT2(cp_csq_ib2_stat) \ + ((cp_csq_ib2_stat & CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) >> CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT) + +#define CP_CSQ_IB2_STAT_SET_CSQ_RPTR_INDIRECT2(cp_csq_ib2_stat_reg, csq_rptr_indirect2) \ + cp_csq_ib2_stat_reg = (cp_csq_ib2_stat_reg & ~CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK) | (csq_rptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT) +#define CP_CSQ_IB2_STAT_SET_CSQ_WPTR_INDIRECT2(cp_csq_ib2_stat_reg, csq_wptr_indirect2) \ + cp_csq_ib2_stat_reg = (cp_csq_ib2_stat_reg & ~CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) | (csq_wptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_csq_ib2_stat_t { + unsigned int csq_rptr_indirect2 : CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE; + unsigned int : 9; + unsigned int csq_wptr_indirect2 : CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE; + unsigned int : 9; + } cp_csq_ib2_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_csq_ib2_stat_t { + unsigned int : 9; + unsigned int csq_wptr_indirect2 : CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE; + unsigned int : 9; + unsigned int csq_rptr_indirect2 : CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE; + } cp_csq_ib2_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_csq_ib2_stat_t f; +} cp_csq_ib2_stat_u; + + +/* + * CP_NON_PREFETCH_CNTRS struct + */ + +#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE 3 +#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE 3 + +#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT 0 +#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT 8 + +#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK 0x00000007 +#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK 0x00000700 + +#define CP_NON_PREFETCH_CNTRS_MASK \ + (CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK | \ + CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) + +#define CP_NON_PREFETCH_CNTRS(ib1_counter, ib2_counter) \ + ((ib1_counter << CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT) | \ + (ib2_counter << CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT)) + +#define CP_NON_PREFETCH_CNTRS_GET_IB1_COUNTER(cp_non_prefetch_cntrs) \ + ((cp_non_prefetch_cntrs & CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK) >> CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT) +#define CP_NON_PREFETCH_CNTRS_GET_IB2_COUNTER(cp_non_prefetch_cntrs) \ + ((cp_non_prefetch_cntrs & CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) >> CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT) + +#define CP_NON_PREFETCH_CNTRS_SET_IB1_COUNTER(cp_non_prefetch_cntrs_reg, ib1_counter) \ + cp_non_prefetch_cntrs_reg = (cp_non_prefetch_cntrs_reg & ~CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK) | (ib1_counter << CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT) +#define CP_NON_PREFETCH_CNTRS_SET_IB2_COUNTER(cp_non_prefetch_cntrs_reg, ib2_counter) \ + cp_non_prefetch_cntrs_reg = (cp_non_prefetch_cntrs_reg & ~CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) | (ib2_counter << CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_non_prefetch_cntrs_t { + unsigned int ib1_counter : CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE; + unsigned int : 5; + unsigned int ib2_counter : CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE; + unsigned int : 21; + } cp_non_prefetch_cntrs_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_non_prefetch_cntrs_t { + unsigned int : 21; + unsigned int ib2_counter : CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE; + unsigned int : 5; + unsigned int ib1_counter : CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE; + } cp_non_prefetch_cntrs_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_non_prefetch_cntrs_t f; +} cp_non_prefetch_cntrs_u; + + +/* + * CP_STQ_ST_STAT struct + */ + +#define CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE 7 +#define CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE 7 + +#define CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT 0 +#define CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT 16 + +#define CP_STQ_ST_STAT_STQ_RPTR_ST_MASK 0x0000007f +#define CP_STQ_ST_STAT_STQ_WPTR_ST_MASK 0x007f0000 + +#define CP_STQ_ST_STAT_MASK \ + (CP_STQ_ST_STAT_STQ_RPTR_ST_MASK | \ + CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) + +#define CP_STQ_ST_STAT(stq_rptr_st, stq_wptr_st) \ + ((stq_rptr_st << CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT) | \ + (stq_wptr_st << CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT)) + +#define CP_STQ_ST_STAT_GET_STQ_RPTR_ST(cp_stq_st_stat) \ + ((cp_stq_st_stat & CP_STQ_ST_STAT_STQ_RPTR_ST_MASK) >> CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT) +#define CP_STQ_ST_STAT_GET_STQ_WPTR_ST(cp_stq_st_stat) \ + ((cp_stq_st_stat & CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) >> CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT) + +#define CP_STQ_ST_STAT_SET_STQ_RPTR_ST(cp_stq_st_stat_reg, stq_rptr_st) \ + cp_stq_st_stat_reg = (cp_stq_st_stat_reg & ~CP_STQ_ST_STAT_STQ_RPTR_ST_MASK) | (stq_rptr_st << CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT) +#define CP_STQ_ST_STAT_SET_STQ_WPTR_ST(cp_stq_st_stat_reg, stq_wptr_st) \ + cp_stq_st_stat_reg = (cp_stq_st_stat_reg & ~CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) | (stq_wptr_st << CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_stq_st_stat_t { + unsigned int stq_rptr_st : CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE; + unsigned int : 9; + unsigned int stq_wptr_st : CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE; + unsigned int : 9; + } cp_stq_st_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_stq_st_stat_t { + unsigned int : 9; + unsigned int stq_wptr_st : CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE; + unsigned int : 9; + unsigned int stq_rptr_st : CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE; + } cp_stq_st_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_stq_st_stat_t f; +} cp_stq_st_stat_u; + + +/* + * CP_MEQ_STAT struct + */ + +#define CP_MEQ_STAT_MEQ_RPTR_SIZE 10 +#define CP_MEQ_STAT_MEQ_WPTR_SIZE 10 + +#define CP_MEQ_STAT_MEQ_RPTR_SHIFT 0 +#define CP_MEQ_STAT_MEQ_WPTR_SHIFT 16 + +#define CP_MEQ_STAT_MEQ_RPTR_MASK 0x000003ff +#define CP_MEQ_STAT_MEQ_WPTR_MASK 0x03ff0000 + +#define CP_MEQ_STAT_MASK \ + (CP_MEQ_STAT_MEQ_RPTR_MASK | \ + CP_MEQ_STAT_MEQ_WPTR_MASK) + +#define CP_MEQ_STAT(meq_rptr, meq_wptr) \ + ((meq_rptr << CP_MEQ_STAT_MEQ_RPTR_SHIFT) | \ + (meq_wptr << CP_MEQ_STAT_MEQ_WPTR_SHIFT)) + +#define CP_MEQ_STAT_GET_MEQ_RPTR(cp_meq_stat) \ + ((cp_meq_stat & CP_MEQ_STAT_MEQ_RPTR_MASK) >> CP_MEQ_STAT_MEQ_RPTR_SHIFT) +#define CP_MEQ_STAT_GET_MEQ_WPTR(cp_meq_stat) \ + ((cp_meq_stat & CP_MEQ_STAT_MEQ_WPTR_MASK) >> CP_MEQ_STAT_MEQ_WPTR_SHIFT) + +#define CP_MEQ_STAT_SET_MEQ_RPTR(cp_meq_stat_reg, meq_rptr) \ + cp_meq_stat_reg = (cp_meq_stat_reg & ~CP_MEQ_STAT_MEQ_RPTR_MASK) | (meq_rptr << CP_MEQ_STAT_MEQ_RPTR_SHIFT) +#define CP_MEQ_STAT_SET_MEQ_WPTR(cp_meq_stat_reg, meq_wptr) \ + cp_meq_stat_reg = (cp_meq_stat_reg & ~CP_MEQ_STAT_MEQ_WPTR_MASK) | (meq_wptr << CP_MEQ_STAT_MEQ_WPTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_meq_stat_t { + unsigned int meq_rptr : CP_MEQ_STAT_MEQ_RPTR_SIZE; + unsigned int : 6; + unsigned int meq_wptr : CP_MEQ_STAT_MEQ_WPTR_SIZE; + unsigned int : 6; + } cp_meq_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_meq_stat_t { + unsigned int : 6; + unsigned int meq_wptr : CP_MEQ_STAT_MEQ_WPTR_SIZE; + unsigned int : 6; + unsigned int meq_rptr : CP_MEQ_STAT_MEQ_RPTR_SIZE; + } cp_meq_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_meq_stat_t f; +} cp_meq_stat_u; + + +/* + * CP_MIU_TAG_STAT struct + */ + +#define CP_MIU_TAG_STAT_TAG_0_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_1_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_2_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_3_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_4_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_5_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_6_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_7_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_8_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_9_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_10_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_11_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_12_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_13_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_14_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_15_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_16_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_17_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE 1 + +#define CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT 0 +#define CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT 1 +#define CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT 2 +#define CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT 3 +#define CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT 4 +#define CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT 5 +#define CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT 6 +#define CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT 7 +#define CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT 8 +#define CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT 9 +#define CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT 10 +#define CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT 11 +#define CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT 12 +#define CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT 13 +#define CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT 14 +#define CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT 15 +#define CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT 16 +#define CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT 17 +#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT 31 + +#define CP_MIU_TAG_STAT_TAG_0_STAT_MASK 0x00000001 +#define CP_MIU_TAG_STAT_TAG_1_STAT_MASK 0x00000002 +#define CP_MIU_TAG_STAT_TAG_2_STAT_MASK 0x00000004 +#define CP_MIU_TAG_STAT_TAG_3_STAT_MASK 0x00000008 +#define CP_MIU_TAG_STAT_TAG_4_STAT_MASK 0x00000010 +#define CP_MIU_TAG_STAT_TAG_5_STAT_MASK 0x00000020 +#define CP_MIU_TAG_STAT_TAG_6_STAT_MASK 0x00000040 +#define CP_MIU_TAG_STAT_TAG_7_STAT_MASK 0x00000080 +#define CP_MIU_TAG_STAT_TAG_8_STAT_MASK 0x00000100 +#define CP_MIU_TAG_STAT_TAG_9_STAT_MASK 0x00000200 +#define CP_MIU_TAG_STAT_TAG_10_STAT_MASK 0x00000400 +#define CP_MIU_TAG_STAT_TAG_11_STAT_MASK 0x00000800 +#define CP_MIU_TAG_STAT_TAG_12_STAT_MASK 0x00001000 +#define CP_MIU_TAG_STAT_TAG_13_STAT_MASK 0x00002000 +#define CP_MIU_TAG_STAT_TAG_14_STAT_MASK 0x00004000 +#define CP_MIU_TAG_STAT_TAG_15_STAT_MASK 0x00008000 +#define CP_MIU_TAG_STAT_TAG_16_STAT_MASK 0x00010000 +#define CP_MIU_TAG_STAT_TAG_17_STAT_MASK 0x00020000 +#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK 0x80000000 + +#define CP_MIU_TAG_STAT_MASK \ + (CP_MIU_TAG_STAT_TAG_0_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_1_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_2_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_3_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_4_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_5_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_6_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_7_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_8_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_9_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_10_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_11_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_12_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_13_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_14_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_15_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_16_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_17_STAT_MASK | \ + CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) + +#define CP_MIU_TAG_STAT(tag_0_stat, tag_1_stat, tag_2_stat, tag_3_stat, tag_4_stat, tag_5_stat, tag_6_stat, tag_7_stat, tag_8_stat, tag_9_stat, tag_10_stat, tag_11_stat, tag_12_stat, tag_13_stat, tag_14_stat, tag_15_stat, tag_16_stat, tag_17_stat, invalid_return_tag) \ + ((tag_0_stat << CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT) | \ + (tag_1_stat << CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT) | \ + (tag_2_stat << CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT) | \ + (tag_3_stat << CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT) | \ + (tag_4_stat << CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT) | \ + (tag_5_stat << CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT) | \ + (tag_6_stat << CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT) | \ + (tag_7_stat << CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT) | \ + (tag_8_stat << CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT) | \ + (tag_9_stat << CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT) | \ + (tag_10_stat << CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT) | \ + (tag_11_stat << CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT) | \ + (tag_12_stat << CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT) | \ + (tag_13_stat << CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT) | \ + (tag_14_stat << CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT) | \ + (tag_15_stat << CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT) | \ + (tag_16_stat << CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT) | \ + (tag_17_stat << CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT) | \ + (invalid_return_tag << CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT)) + +#define CP_MIU_TAG_STAT_GET_TAG_0_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_0_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_1_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_1_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_2_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_2_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_3_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_3_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_4_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_4_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_5_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_5_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_6_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_6_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_7_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_7_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_8_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_8_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_9_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_9_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_10_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_10_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_11_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_11_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_12_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_12_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_13_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_13_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_14_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_14_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_15_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_15_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_16_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_16_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_17_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_17_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_INVALID_RETURN_TAG(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) >> CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT) + +#define CP_MIU_TAG_STAT_SET_TAG_0_STAT(cp_miu_tag_stat_reg, tag_0_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_0_STAT_MASK) | (tag_0_stat << CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_1_STAT(cp_miu_tag_stat_reg, tag_1_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_1_STAT_MASK) | (tag_1_stat << CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_2_STAT(cp_miu_tag_stat_reg, tag_2_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_2_STAT_MASK) | (tag_2_stat << CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_3_STAT(cp_miu_tag_stat_reg, tag_3_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_3_STAT_MASK) | (tag_3_stat << CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_4_STAT(cp_miu_tag_stat_reg, tag_4_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_4_STAT_MASK) | (tag_4_stat << CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_5_STAT(cp_miu_tag_stat_reg, tag_5_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_5_STAT_MASK) | (tag_5_stat << CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_6_STAT(cp_miu_tag_stat_reg, tag_6_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_6_STAT_MASK) | (tag_6_stat << CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_7_STAT(cp_miu_tag_stat_reg, tag_7_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_7_STAT_MASK) | (tag_7_stat << CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_8_STAT(cp_miu_tag_stat_reg, tag_8_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_8_STAT_MASK) | (tag_8_stat << CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_9_STAT(cp_miu_tag_stat_reg, tag_9_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_9_STAT_MASK) | (tag_9_stat << CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_10_STAT(cp_miu_tag_stat_reg, tag_10_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_10_STAT_MASK) | (tag_10_stat << CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_11_STAT(cp_miu_tag_stat_reg, tag_11_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_11_STAT_MASK) | (tag_11_stat << CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_12_STAT(cp_miu_tag_stat_reg, tag_12_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_12_STAT_MASK) | (tag_12_stat << CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_13_STAT(cp_miu_tag_stat_reg, tag_13_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_13_STAT_MASK) | (tag_13_stat << CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_14_STAT(cp_miu_tag_stat_reg, tag_14_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_14_STAT_MASK) | (tag_14_stat << CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_15_STAT(cp_miu_tag_stat_reg, tag_15_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_15_STAT_MASK) | (tag_15_stat << CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_16_STAT(cp_miu_tag_stat_reg, tag_16_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_16_STAT_MASK) | (tag_16_stat << CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_17_STAT(cp_miu_tag_stat_reg, tag_17_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_17_STAT_MASK) | (tag_17_stat << CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_INVALID_RETURN_TAG(cp_miu_tag_stat_reg, invalid_return_tag) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) | (invalid_return_tag << CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_miu_tag_stat_t { + unsigned int tag_0_stat : CP_MIU_TAG_STAT_TAG_0_STAT_SIZE; + unsigned int tag_1_stat : CP_MIU_TAG_STAT_TAG_1_STAT_SIZE; + unsigned int tag_2_stat : CP_MIU_TAG_STAT_TAG_2_STAT_SIZE; + unsigned int tag_3_stat : CP_MIU_TAG_STAT_TAG_3_STAT_SIZE; + unsigned int tag_4_stat : CP_MIU_TAG_STAT_TAG_4_STAT_SIZE; + unsigned int tag_5_stat : CP_MIU_TAG_STAT_TAG_5_STAT_SIZE; + unsigned int tag_6_stat : CP_MIU_TAG_STAT_TAG_6_STAT_SIZE; + unsigned int tag_7_stat : CP_MIU_TAG_STAT_TAG_7_STAT_SIZE; + unsigned int tag_8_stat : CP_MIU_TAG_STAT_TAG_8_STAT_SIZE; + unsigned int tag_9_stat : CP_MIU_TAG_STAT_TAG_9_STAT_SIZE; + unsigned int tag_10_stat : CP_MIU_TAG_STAT_TAG_10_STAT_SIZE; + unsigned int tag_11_stat : CP_MIU_TAG_STAT_TAG_11_STAT_SIZE; + unsigned int tag_12_stat : CP_MIU_TAG_STAT_TAG_12_STAT_SIZE; + unsigned int tag_13_stat : CP_MIU_TAG_STAT_TAG_13_STAT_SIZE; + unsigned int tag_14_stat : CP_MIU_TAG_STAT_TAG_14_STAT_SIZE; + unsigned int tag_15_stat : CP_MIU_TAG_STAT_TAG_15_STAT_SIZE; + unsigned int tag_16_stat : CP_MIU_TAG_STAT_TAG_16_STAT_SIZE; + unsigned int tag_17_stat : CP_MIU_TAG_STAT_TAG_17_STAT_SIZE; + unsigned int : 13; + unsigned int invalid_return_tag : CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE; + } cp_miu_tag_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_miu_tag_stat_t { + unsigned int invalid_return_tag : CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE; + unsigned int : 13; + unsigned int tag_17_stat : CP_MIU_TAG_STAT_TAG_17_STAT_SIZE; + unsigned int tag_16_stat : CP_MIU_TAG_STAT_TAG_16_STAT_SIZE; + unsigned int tag_15_stat : CP_MIU_TAG_STAT_TAG_15_STAT_SIZE; + unsigned int tag_14_stat : CP_MIU_TAG_STAT_TAG_14_STAT_SIZE; + unsigned int tag_13_stat : CP_MIU_TAG_STAT_TAG_13_STAT_SIZE; + unsigned int tag_12_stat : CP_MIU_TAG_STAT_TAG_12_STAT_SIZE; + unsigned int tag_11_stat : CP_MIU_TAG_STAT_TAG_11_STAT_SIZE; + unsigned int tag_10_stat : CP_MIU_TAG_STAT_TAG_10_STAT_SIZE; + unsigned int tag_9_stat : CP_MIU_TAG_STAT_TAG_9_STAT_SIZE; + unsigned int tag_8_stat : CP_MIU_TAG_STAT_TAG_8_STAT_SIZE; + unsigned int tag_7_stat : CP_MIU_TAG_STAT_TAG_7_STAT_SIZE; + unsigned int tag_6_stat : CP_MIU_TAG_STAT_TAG_6_STAT_SIZE; + unsigned int tag_5_stat : CP_MIU_TAG_STAT_TAG_5_STAT_SIZE; + unsigned int tag_4_stat : CP_MIU_TAG_STAT_TAG_4_STAT_SIZE; + unsigned int tag_3_stat : CP_MIU_TAG_STAT_TAG_3_STAT_SIZE; + unsigned int tag_2_stat : CP_MIU_TAG_STAT_TAG_2_STAT_SIZE; + unsigned int tag_1_stat : CP_MIU_TAG_STAT_TAG_1_STAT_SIZE; + unsigned int tag_0_stat : CP_MIU_TAG_STAT_TAG_0_STAT_SIZE; + } cp_miu_tag_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_miu_tag_stat_t f; +} cp_miu_tag_stat_u; + + +/* + * CP_CMD_INDEX struct + */ + +#define CP_CMD_INDEX_CMD_INDEX_SIZE 7 +#define CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE 2 + +#define CP_CMD_INDEX_CMD_INDEX_SHIFT 0 +#define CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT 16 + +#define CP_CMD_INDEX_CMD_INDEX_MASK 0x0000007f +#define CP_CMD_INDEX_CMD_QUEUE_SEL_MASK 0x00030000 + +#define CP_CMD_INDEX_MASK \ + (CP_CMD_INDEX_CMD_INDEX_MASK | \ + CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) + +#define CP_CMD_INDEX(cmd_index, cmd_queue_sel) \ + ((cmd_index << CP_CMD_INDEX_CMD_INDEX_SHIFT) | \ + (cmd_queue_sel << CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT)) + +#define CP_CMD_INDEX_GET_CMD_INDEX(cp_cmd_index) \ + ((cp_cmd_index & CP_CMD_INDEX_CMD_INDEX_MASK) >> CP_CMD_INDEX_CMD_INDEX_SHIFT) +#define CP_CMD_INDEX_GET_CMD_QUEUE_SEL(cp_cmd_index) \ + ((cp_cmd_index & CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) >> CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT) + +#define CP_CMD_INDEX_SET_CMD_INDEX(cp_cmd_index_reg, cmd_index) \ + cp_cmd_index_reg = (cp_cmd_index_reg & ~CP_CMD_INDEX_CMD_INDEX_MASK) | (cmd_index << CP_CMD_INDEX_CMD_INDEX_SHIFT) +#define CP_CMD_INDEX_SET_CMD_QUEUE_SEL(cp_cmd_index_reg, cmd_queue_sel) \ + cp_cmd_index_reg = (cp_cmd_index_reg & ~CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) | (cmd_queue_sel << CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_cmd_index_t { + unsigned int cmd_index : CP_CMD_INDEX_CMD_INDEX_SIZE; + unsigned int : 9; + unsigned int cmd_queue_sel : CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE; + unsigned int : 14; + } cp_cmd_index_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_cmd_index_t { + unsigned int : 14; + unsigned int cmd_queue_sel : CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE; + unsigned int : 9; + unsigned int cmd_index : CP_CMD_INDEX_CMD_INDEX_SIZE; + } cp_cmd_index_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_cmd_index_t f; +} cp_cmd_index_u; + + +/* + * CP_CMD_DATA struct + */ + +#define CP_CMD_DATA_CMD_DATA_SIZE 32 + +#define CP_CMD_DATA_CMD_DATA_SHIFT 0 + +#define CP_CMD_DATA_CMD_DATA_MASK 0xffffffff + +#define CP_CMD_DATA_MASK \ + (CP_CMD_DATA_CMD_DATA_MASK) + +#define CP_CMD_DATA(cmd_data) \ + ((cmd_data << CP_CMD_DATA_CMD_DATA_SHIFT)) + +#define CP_CMD_DATA_GET_CMD_DATA(cp_cmd_data) \ + ((cp_cmd_data & CP_CMD_DATA_CMD_DATA_MASK) >> CP_CMD_DATA_CMD_DATA_SHIFT) + +#define CP_CMD_DATA_SET_CMD_DATA(cp_cmd_data_reg, cmd_data) \ + cp_cmd_data_reg = (cp_cmd_data_reg & ~CP_CMD_DATA_CMD_DATA_MASK) | (cmd_data << CP_CMD_DATA_CMD_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_cmd_data_t { + unsigned int cmd_data : CP_CMD_DATA_CMD_DATA_SIZE; + } cp_cmd_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_cmd_data_t { + unsigned int cmd_data : CP_CMD_DATA_CMD_DATA_SIZE; + } cp_cmd_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_cmd_data_t f; +} cp_cmd_data_u; + + +/* + * CP_ME_CNTL struct + */ + +#define CP_ME_CNTL_ME_STATMUX_SIZE 16 +#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE 1 +#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE 1 +#define CP_ME_CNTL_ME_HALT_SIZE 1 +#define CP_ME_CNTL_ME_BUSY_SIZE 1 +#define CP_ME_CNTL_PROG_CNT_SIZE_SIZE 1 + +#define CP_ME_CNTL_ME_STATMUX_SHIFT 0 +#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT 25 +#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT 26 +#define CP_ME_CNTL_ME_HALT_SHIFT 28 +#define CP_ME_CNTL_ME_BUSY_SHIFT 29 +#define CP_ME_CNTL_PROG_CNT_SIZE_SHIFT 31 + +#define CP_ME_CNTL_ME_STATMUX_MASK 0x0000ffff +#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK 0x02000000 +#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK 0x04000000 +#define CP_ME_CNTL_ME_HALT_MASK 0x10000000 +#define CP_ME_CNTL_ME_BUSY_MASK 0x20000000 +#define CP_ME_CNTL_PROG_CNT_SIZE_MASK 0x80000000 + +#define CP_ME_CNTL_MASK \ + (CP_ME_CNTL_ME_STATMUX_MASK | \ + CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK | \ + CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK | \ + CP_ME_CNTL_ME_HALT_MASK | \ + CP_ME_CNTL_ME_BUSY_MASK | \ + CP_ME_CNTL_PROG_CNT_SIZE_MASK) + +#define CP_ME_CNTL(me_statmux, vtx_dealloc_fifo_empty, pix_dealloc_fifo_empty, me_halt, me_busy, prog_cnt_size) \ + ((me_statmux << CP_ME_CNTL_ME_STATMUX_SHIFT) | \ + (vtx_dealloc_fifo_empty << CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT) | \ + (pix_dealloc_fifo_empty << CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT) | \ + (me_halt << CP_ME_CNTL_ME_HALT_SHIFT) | \ + (me_busy << CP_ME_CNTL_ME_BUSY_SHIFT) | \ + (prog_cnt_size << CP_ME_CNTL_PROG_CNT_SIZE_SHIFT)) + +#define CP_ME_CNTL_GET_ME_STATMUX(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_ME_STATMUX_MASK) >> CP_ME_CNTL_ME_STATMUX_SHIFT) +#define CP_ME_CNTL_GET_VTX_DEALLOC_FIFO_EMPTY(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK) >> CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT) +#define CP_ME_CNTL_GET_PIX_DEALLOC_FIFO_EMPTY(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK) >> CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT) +#define CP_ME_CNTL_GET_ME_HALT(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_ME_HALT_MASK) >> CP_ME_CNTL_ME_HALT_SHIFT) +#define CP_ME_CNTL_GET_ME_BUSY(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_ME_BUSY_MASK) >> CP_ME_CNTL_ME_BUSY_SHIFT) +#define CP_ME_CNTL_GET_PROG_CNT_SIZE(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_PROG_CNT_SIZE_MASK) >> CP_ME_CNTL_PROG_CNT_SIZE_SHIFT) + +#define CP_ME_CNTL_SET_ME_STATMUX(cp_me_cntl_reg, me_statmux) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_STATMUX_MASK) | (me_statmux << CP_ME_CNTL_ME_STATMUX_SHIFT) +#define CP_ME_CNTL_SET_VTX_DEALLOC_FIFO_EMPTY(cp_me_cntl_reg, vtx_dealloc_fifo_empty) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK) | (vtx_dealloc_fifo_empty << CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT) +#define CP_ME_CNTL_SET_PIX_DEALLOC_FIFO_EMPTY(cp_me_cntl_reg, pix_dealloc_fifo_empty) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK) | (pix_dealloc_fifo_empty << CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT) +#define CP_ME_CNTL_SET_ME_HALT(cp_me_cntl_reg, me_halt) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_HALT_MASK) | (me_halt << CP_ME_CNTL_ME_HALT_SHIFT) +#define CP_ME_CNTL_SET_ME_BUSY(cp_me_cntl_reg, me_busy) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_BUSY_MASK) | (me_busy << CP_ME_CNTL_ME_BUSY_SHIFT) +#define CP_ME_CNTL_SET_PROG_CNT_SIZE(cp_me_cntl_reg, prog_cnt_size) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_PROG_CNT_SIZE_MASK) | (prog_cnt_size << CP_ME_CNTL_PROG_CNT_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_cntl_t { + unsigned int me_statmux : CP_ME_CNTL_ME_STATMUX_SIZE; + unsigned int : 9; + unsigned int vtx_dealloc_fifo_empty : CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE; + unsigned int pix_dealloc_fifo_empty : CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE; + unsigned int : 1; + unsigned int me_halt : CP_ME_CNTL_ME_HALT_SIZE; + unsigned int me_busy : CP_ME_CNTL_ME_BUSY_SIZE; + unsigned int : 1; + unsigned int prog_cnt_size : CP_ME_CNTL_PROG_CNT_SIZE_SIZE; + } cp_me_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_cntl_t { + unsigned int prog_cnt_size : CP_ME_CNTL_PROG_CNT_SIZE_SIZE; + unsigned int : 1; + unsigned int me_busy : CP_ME_CNTL_ME_BUSY_SIZE; + unsigned int me_halt : CP_ME_CNTL_ME_HALT_SIZE; + unsigned int : 1; + unsigned int pix_dealloc_fifo_empty : CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE; + unsigned int vtx_dealloc_fifo_empty : CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE; + unsigned int : 9; + unsigned int me_statmux : CP_ME_CNTL_ME_STATMUX_SIZE; + } cp_me_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_cntl_t f; +} cp_me_cntl_u; + + +/* + * CP_ME_STATUS struct + */ + +#define CP_ME_STATUS_ME_DEBUG_DATA_SIZE 32 + +#define CP_ME_STATUS_ME_DEBUG_DATA_SHIFT 0 + +#define CP_ME_STATUS_ME_DEBUG_DATA_MASK 0xffffffff + +#define CP_ME_STATUS_MASK \ + (CP_ME_STATUS_ME_DEBUG_DATA_MASK) + +#define CP_ME_STATUS(me_debug_data) \ + ((me_debug_data << CP_ME_STATUS_ME_DEBUG_DATA_SHIFT)) + +#define CP_ME_STATUS_GET_ME_DEBUG_DATA(cp_me_status) \ + ((cp_me_status & CP_ME_STATUS_ME_DEBUG_DATA_MASK) >> CP_ME_STATUS_ME_DEBUG_DATA_SHIFT) + +#define CP_ME_STATUS_SET_ME_DEBUG_DATA(cp_me_status_reg, me_debug_data) \ + cp_me_status_reg = (cp_me_status_reg & ~CP_ME_STATUS_ME_DEBUG_DATA_MASK) | (me_debug_data << CP_ME_STATUS_ME_DEBUG_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_status_t { + unsigned int me_debug_data : CP_ME_STATUS_ME_DEBUG_DATA_SIZE; + } cp_me_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_status_t { + unsigned int me_debug_data : CP_ME_STATUS_ME_DEBUG_DATA_SIZE; + } cp_me_status_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_status_t f; +} cp_me_status_u; + + +/* + * CP_ME_RAM_WADDR struct + */ + +#define CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE 10 + +#define CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT 0 + +#define CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK 0x000003ff + +#define CP_ME_RAM_WADDR_MASK \ + (CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) + +#define CP_ME_RAM_WADDR(me_ram_waddr) \ + ((me_ram_waddr << CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT)) + +#define CP_ME_RAM_WADDR_GET_ME_RAM_WADDR(cp_me_ram_waddr) \ + ((cp_me_ram_waddr & CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) >> CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT) + +#define CP_ME_RAM_WADDR_SET_ME_RAM_WADDR(cp_me_ram_waddr_reg, me_ram_waddr) \ + cp_me_ram_waddr_reg = (cp_me_ram_waddr_reg & ~CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) | (me_ram_waddr << CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ram_waddr_t { + unsigned int me_ram_waddr : CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE; + unsigned int : 22; + } cp_me_ram_waddr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ram_waddr_t { + unsigned int : 22; + unsigned int me_ram_waddr : CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE; + } cp_me_ram_waddr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ram_waddr_t f; +} cp_me_ram_waddr_u; + + +/* + * CP_ME_RAM_RADDR struct + */ + +#define CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE 10 + +#define CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT 0 + +#define CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK 0x000003ff + +#define CP_ME_RAM_RADDR_MASK \ + (CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) + +#define CP_ME_RAM_RADDR(me_ram_raddr) \ + ((me_ram_raddr << CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT)) + +#define CP_ME_RAM_RADDR_GET_ME_RAM_RADDR(cp_me_ram_raddr) \ + ((cp_me_ram_raddr & CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) >> CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT) + +#define CP_ME_RAM_RADDR_SET_ME_RAM_RADDR(cp_me_ram_raddr_reg, me_ram_raddr) \ + cp_me_ram_raddr_reg = (cp_me_ram_raddr_reg & ~CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) | (me_ram_raddr << CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ram_raddr_t { + unsigned int me_ram_raddr : CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE; + unsigned int : 22; + } cp_me_ram_raddr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ram_raddr_t { + unsigned int : 22; + unsigned int me_ram_raddr : CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE; + } cp_me_ram_raddr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ram_raddr_t f; +} cp_me_ram_raddr_u; + + +/* + * CP_ME_RAM_DATA struct + */ + +#define CP_ME_RAM_DATA_ME_RAM_DATA_SIZE 32 + +#define CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT 0 + +#define CP_ME_RAM_DATA_ME_RAM_DATA_MASK 0xffffffff + +#define CP_ME_RAM_DATA_MASK \ + (CP_ME_RAM_DATA_ME_RAM_DATA_MASK) + +#define CP_ME_RAM_DATA(me_ram_data) \ + ((me_ram_data << CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT)) + +#define CP_ME_RAM_DATA_GET_ME_RAM_DATA(cp_me_ram_data) \ + ((cp_me_ram_data & CP_ME_RAM_DATA_ME_RAM_DATA_MASK) >> CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT) + +#define CP_ME_RAM_DATA_SET_ME_RAM_DATA(cp_me_ram_data_reg, me_ram_data) \ + cp_me_ram_data_reg = (cp_me_ram_data_reg & ~CP_ME_RAM_DATA_ME_RAM_DATA_MASK) | (me_ram_data << CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ram_data_t { + unsigned int me_ram_data : CP_ME_RAM_DATA_ME_RAM_DATA_SIZE; + } cp_me_ram_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ram_data_t { + unsigned int me_ram_data : CP_ME_RAM_DATA_ME_RAM_DATA_SIZE; + } cp_me_ram_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ram_data_t f; +} cp_me_ram_data_u; + + +/* + * CP_ME_RDADDR struct + */ + +#define CP_ME_RDADDR_ME_RDADDR_SIZE 32 + +#define CP_ME_RDADDR_ME_RDADDR_SHIFT 0 + +#define CP_ME_RDADDR_ME_RDADDR_MASK 0xffffffff + +#define CP_ME_RDADDR_MASK \ + (CP_ME_RDADDR_ME_RDADDR_MASK) + +#define CP_ME_RDADDR(me_rdaddr) \ + ((me_rdaddr << CP_ME_RDADDR_ME_RDADDR_SHIFT)) + +#define CP_ME_RDADDR_GET_ME_RDADDR(cp_me_rdaddr) \ + ((cp_me_rdaddr & CP_ME_RDADDR_ME_RDADDR_MASK) >> CP_ME_RDADDR_ME_RDADDR_SHIFT) + +#define CP_ME_RDADDR_SET_ME_RDADDR(cp_me_rdaddr_reg, me_rdaddr) \ + cp_me_rdaddr_reg = (cp_me_rdaddr_reg & ~CP_ME_RDADDR_ME_RDADDR_MASK) | (me_rdaddr << CP_ME_RDADDR_ME_RDADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_rdaddr_t { + unsigned int me_rdaddr : CP_ME_RDADDR_ME_RDADDR_SIZE; + } cp_me_rdaddr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_rdaddr_t { + unsigned int me_rdaddr : CP_ME_RDADDR_ME_RDADDR_SIZE; + } cp_me_rdaddr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_rdaddr_t f; +} cp_me_rdaddr_u; + + +/* + * CP_DEBUG struct + */ + +#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE 23 +#define CP_DEBUG_PREDICATE_DISABLE_SIZE 1 +#define CP_DEBUG_PROG_END_PTR_ENABLE_SIZE 1 +#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE 1 +#define CP_DEBUG_PREFETCH_PASS_NOPS_SIZE 1 +#define CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE 1 +#define CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE 1 +#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE 1 +#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE 1 + +#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT 0 +#define CP_DEBUG_PREDICATE_DISABLE_SHIFT 23 +#define CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT 24 +#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT 25 +#define CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT 26 +#define CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT 27 +#define CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT 28 +#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT 30 +#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT 31 + +#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK 0x007fffff +#define CP_DEBUG_PREDICATE_DISABLE_MASK 0x00800000 +#define CP_DEBUG_PROG_END_PTR_ENABLE_MASK 0x01000000 +#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK 0x02000000 +#define CP_DEBUG_PREFETCH_PASS_NOPS_MASK 0x04000000 +#define CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK 0x08000000 +#define CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK 0x10000000 +#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK 0x40000000 +#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK 0x80000000 + +#define CP_DEBUG_MASK \ + (CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK | \ + CP_DEBUG_PREDICATE_DISABLE_MASK | \ + CP_DEBUG_PROG_END_PTR_ENABLE_MASK | \ + CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK | \ + CP_DEBUG_PREFETCH_PASS_NOPS_MASK | \ + CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK | \ + CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK | \ + CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK | \ + CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) + +#define CP_DEBUG(cp_debug_unused_22_to_0, predicate_disable, prog_end_ptr_enable, miu_128bit_write_enable, prefetch_pass_nops, dynamic_clk_disable, prefetch_match_disable, simple_me_flow_control, miu_write_pack_disable) \ + ((cp_debug_unused_22_to_0 << CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT) | \ + (predicate_disable << CP_DEBUG_PREDICATE_DISABLE_SHIFT) | \ + (prog_end_ptr_enable << CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT) | \ + (miu_128bit_write_enable << CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT) | \ + (prefetch_pass_nops << CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT) | \ + (dynamic_clk_disable << CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT) | \ + (prefetch_match_disable << CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT) | \ + (simple_me_flow_control << CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT) | \ + (miu_write_pack_disable << CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT)) + +#define CP_DEBUG_GET_CP_DEBUG_UNUSED_22_to_0(cp_debug) \ + ((cp_debug & CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK) >> CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT) +#define CP_DEBUG_GET_PREDICATE_DISABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_PREDICATE_DISABLE_MASK) >> CP_DEBUG_PREDICATE_DISABLE_SHIFT) +#define CP_DEBUG_GET_PROG_END_PTR_ENABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_PROG_END_PTR_ENABLE_MASK) >> CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT) +#define CP_DEBUG_GET_MIU_128BIT_WRITE_ENABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK) >> CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT) +#define CP_DEBUG_GET_PREFETCH_PASS_NOPS(cp_debug) \ + ((cp_debug & CP_DEBUG_PREFETCH_PASS_NOPS_MASK) >> CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT) +#define CP_DEBUG_GET_DYNAMIC_CLK_DISABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK) >> CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT) +#define CP_DEBUG_GET_PREFETCH_MATCH_DISABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK) >> CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT) +#define CP_DEBUG_GET_SIMPLE_ME_FLOW_CONTROL(cp_debug) \ + ((cp_debug & CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK) >> CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT) +#define CP_DEBUG_GET_MIU_WRITE_PACK_DISABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) >> CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT) + +#define CP_DEBUG_SET_CP_DEBUG_UNUSED_22_to_0(cp_debug_reg, cp_debug_unused_22_to_0) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK) | (cp_debug_unused_22_to_0 << CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT) +#define CP_DEBUG_SET_PREDICATE_DISABLE(cp_debug_reg, predicate_disable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREDICATE_DISABLE_MASK) | (predicate_disable << CP_DEBUG_PREDICATE_DISABLE_SHIFT) +#define CP_DEBUG_SET_PROG_END_PTR_ENABLE(cp_debug_reg, prog_end_ptr_enable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PROG_END_PTR_ENABLE_MASK) | (prog_end_ptr_enable << CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT) +#define CP_DEBUG_SET_MIU_128BIT_WRITE_ENABLE(cp_debug_reg, miu_128bit_write_enable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK) | (miu_128bit_write_enable << CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT) +#define CP_DEBUG_SET_PREFETCH_PASS_NOPS(cp_debug_reg, prefetch_pass_nops) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREFETCH_PASS_NOPS_MASK) | (prefetch_pass_nops << CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT) +#define CP_DEBUG_SET_DYNAMIC_CLK_DISABLE(cp_debug_reg, dynamic_clk_disable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK) | (dynamic_clk_disable << CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT) +#define CP_DEBUG_SET_PREFETCH_MATCH_DISABLE(cp_debug_reg, prefetch_match_disable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK) | (prefetch_match_disable << CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT) +#define CP_DEBUG_SET_SIMPLE_ME_FLOW_CONTROL(cp_debug_reg, simple_me_flow_control) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK) | (simple_me_flow_control << CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT) +#define CP_DEBUG_SET_MIU_WRITE_PACK_DISABLE(cp_debug_reg, miu_write_pack_disable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) | (miu_write_pack_disable << CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_debug_t { + unsigned int cp_debug_unused_22_to_0 : CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE; + unsigned int predicate_disable : CP_DEBUG_PREDICATE_DISABLE_SIZE; + unsigned int prog_end_ptr_enable : CP_DEBUG_PROG_END_PTR_ENABLE_SIZE; + unsigned int miu_128bit_write_enable : CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE; + unsigned int prefetch_pass_nops : CP_DEBUG_PREFETCH_PASS_NOPS_SIZE; + unsigned int dynamic_clk_disable : CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE; + unsigned int prefetch_match_disable : CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE; + unsigned int : 1; + unsigned int simple_me_flow_control : CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE; + unsigned int miu_write_pack_disable : CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE; + } cp_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_debug_t { + unsigned int miu_write_pack_disable : CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE; + unsigned int simple_me_flow_control : CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE; + unsigned int : 1; + unsigned int prefetch_match_disable : CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE; + unsigned int dynamic_clk_disable : CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE; + unsigned int prefetch_pass_nops : CP_DEBUG_PREFETCH_PASS_NOPS_SIZE; + unsigned int miu_128bit_write_enable : CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE; + unsigned int prog_end_ptr_enable : CP_DEBUG_PROG_END_PTR_ENABLE_SIZE; + unsigned int predicate_disable : CP_DEBUG_PREDICATE_DISABLE_SIZE; + unsigned int cp_debug_unused_22_to_0 : CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE; + } cp_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_debug_t f; +} cp_debug_u; + + +/* + * SCRATCH_REG0 struct + */ + +#define SCRATCH_REG0_SCRATCH_REG0_SIZE 32 + +#define SCRATCH_REG0_SCRATCH_REG0_SHIFT 0 + +#define SCRATCH_REG0_SCRATCH_REG0_MASK 0xffffffff + +#define SCRATCH_REG0_MASK \ + (SCRATCH_REG0_SCRATCH_REG0_MASK) + +#define SCRATCH_REG0(scratch_reg0) \ + ((scratch_reg0 << SCRATCH_REG0_SCRATCH_REG0_SHIFT)) + +#define SCRATCH_REG0_GET_SCRATCH_REG0(scratch_reg0) \ + ((scratch_reg0 & SCRATCH_REG0_SCRATCH_REG0_MASK) >> SCRATCH_REG0_SCRATCH_REG0_SHIFT) + +#define SCRATCH_REG0_SET_SCRATCH_REG0(scratch_reg0_reg, scratch_reg0) \ + scratch_reg0_reg = (scratch_reg0_reg & ~SCRATCH_REG0_SCRATCH_REG0_MASK) | (scratch_reg0 << SCRATCH_REG0_SCRATCH_REG0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg0_t { + unsigned int scratch_reg0 : SCRATCH_REG0_SCRATCH_REG0_SIZE; + } scratch_reg0_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg0_t { + unsigned int scratch_reg0 : SCRATCH_REG0_SCRATCH_REG0_SIZE; + } scratch_reg0_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg0_t f; +} scratch_reg0_u; + + +/* + * SCRATCH_REG1 struct + */ + +#define SCRATCH_REG1_SCRATCH_REG1_SIZE 32 + +#define SCRATCH_REG1_SCRATCH_REG1_SHIFT 0 + +#define SCRATCH_REG1_SCRATCH_REG1_MASK 0xffffffff + +#define SCRATCH_REG1_MASK \ + (SCRATCH_REG1_SCRATCH_REG1_MASK) + +#define SCRATCH_REG1(scratch_reg1) \ + ((scratch_reg1 << SCRATCH_REG1_SCRATCH_REG1_SHIFT)) + +#define SCRATCH_REG1_GET_SCRATCH_REG1(scratch_reg1) \ + ((scratch_reg1 & SCRATCH_REG1_SCRATCH_REG1_MASK) >> SCRATCH_REG1_SCRATCH_REG1_SHIFT) + +#define SCRATCH_REG1_SET_SCRATCH_REG1(scratch_reg1_reg, scratch_reg1) \ + scratch_reg1_reg = (scratch_reg1_reg & ~SCRATCH_REG1_SCRATCH_REG1_MASK) | (scratch_reg1 << SCRATCH_REG1_SCRATCH_REG1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg1_t { + unsigned int scratch_reg1 : SCRATCH_REG1_SCRATCH_REG1_SIZE; + } scratch_reg1_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg1_t { + unsigned int scratch_reg1 : SCRATCH_REG1_SCRATCH_REG1_SIZE; + } scratch_reg1_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg1_t f; +} scratch_reg1_u; + + +/* + * SCRATCH_REG2 struct + */ + +#define SCRATCH_REG2_SCRATCH_REG2_SIZE 32 + +#define SCRATCH_REG2_SCRATCH_REG2_SHIFT 0 + +#define SCRATCH_REG2_SCRATCH_REG2_MASK 0xffffffff + +#define SCRATCH_REG2_MASK \ + (SCRATCH_REG2_SCRATCH_REG2_MASK) + +#define SCRATCH_REG2(scratch_reg2) \ + ((scratch_reg2 << SCRATCH_REG2_SCRATCH_REG2_SHIFT)) + +#define SCRATCH_REG2_GET_SCRATCH_REG2(scratch_reg2) \ + ((scratch_reg2 & SCRATCH_REG2_SCRATCH_REG2_MASK) >> SCRATCH_REG2_SCRATCH_REG2_SHIFT) + +#define SCRATCH_REG2_SET_SCRATCH_REG2(scratch_reg2_reg, scratch_reg2) \ + scratch_reg2_reg = (scratch_reg2_reg & ~SCRATCH_REG2_SCRATCH_REG2_MASK) | (scratch_reg2 << SCRATCH_REG2_SCRATCH_REG2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg2_t { + unsigned int scratch_reg2 : SCRATCH_REG2_SCRATCH_REG2_SIZE; + } scratch_reg2_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg2_t { + unsigned int scratch_reg2 : SCRATCH_REG2_SCRATCH_REG2_SIZE; + } scratch_reg2_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg2_t f; +} scratch_reg2_u; + + +/* + * SCRATCH_REG3 struct + */ + +#define SCRATCH_REG3_SCRATCH_REG3_SIZE 32 + +#define SCRATCH_REG3_SCRATCH_REG3_SHIFT 0 + +#define SCRATCH_REG3_SCRATCH_REG3_MASK 0xffffffff + +#define SCRATCH_REG3_MASK \ + (SCRATCH_REG3_SCRATCH_REG3_MASK) + +#define SCRATCH_REG3(scratch_reg3) \ + ((scratch_reg3 << SCRATCH_REG3_SCRATCH_REG3_SHIFT)) + +#define SCRATCH_REG3_GET_SCRATCH_REG3(scratch_reg3) \ + ((scratch_reg3 & SCRATCH_REG3_SCRATCH_REG3_MASK) >> SCRATCH_REG3_SCRATCH_REG3_SHIFT) + +#define SCRATCH_REG3_SET_SCRATCH_REG3(scratch_reg3_reg, scratch_reg3) \ + scratch_reg3_reg = (scratch_reg3_reg & ~SCRATCH_REG3_SCRATCH_REG3_MASK) | (scratch_reg3 << SCRATCH_REG3_SCRATCH_REG3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg3_t { + unsigned int scratch_reg3 : SCRATCH_REG3_SCRATCH_REG3_SIZE; + } scratch_reg3_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg3_t { + unsigned int scratch_reg3 : SCRATCH_REG3_SCRATCH_REG3_SIZE; + } scratch_reg3_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg3_t f; +} scratch_reg3_u; + + +/* + * SCRATCH_REG4 struct + */ + +#define SCRATCH_REG4_SCRATCH_REG4_SIZE 32 + +#define SCRATCH_REG4_SCRATCH_REG4_SHIFT 0 + +#define SCRATCH_REG4_SCRATCH_REG4_MASK 0xffffffff + +#define SCRATCH_REG4_MASK \ + (SCRATCH_REG4_SCRATCH_REG4_MASK) + +#define SCRATCH_REG4(scratch_reg4) \ + ((scratch_reg4 << SCRATCH_REG4_SCRATCH_REG4_SHIFT)) + +#define SCRATCH_REG4_GET_SCRATCH_REG4(scratch_reg4) \ + ((scratch_reg4 & SCRATCH_REG4_SCRATCH_REG4_MASK) >> SCRATCH_REG4_SCRATCH_REG4_SHIFT) + +#define SCRATCH_REG4_SET_SCRATCH_REG4(scratch_reg4_reg, scratch_reg4) \ + scratch_reg4_reg = (scratch_reg4_reg & ~SCRATCH_REG4_SCRATCH_REG4_MASK) | (scratch_reg4 << SCRATCH_REG4_SCRATCH_REG4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg4_t { + unsigned int scratch_reg4 : SCRATCH_REG4_SCRATCH_REG4_SIZE; + } scratch_reg4_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg4_t { + unsigned int scratch_reg4 : SCRATCH_REG4_SCRATCH_REG4_SIZE; + } scratch_reg4_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg4_t f; +} scratch_reg4_u; + + +/* + * SCRATCH_REG5 struct + */ + +#define SCRATCH_REG5_SCRATCH_REG5_SIZE 32 + +#define SCRATCH_REG5_SCRATCH_REG5_SHIFT 0 + +#define SCRATCH_REG5_SCRATCH_REG5_MASK 0xffffffff + +#define SCRATCH_REG5_MASK \ + (SCRATCH_REG5_SCRATCH_REG5_MASK) + +#define SCRATCH_REG5(scratch_reg5) \ + ((scratch_reg5 << SCRATCH_REG5_SCRATCH_REG5_SHIFT)) + +#define SCRATCH_REG5_GET_SCRATCH_REG5(scratch_reg5) \ + ((scratch_reg5 & SCRATCH_REG5_SCRATCH_REG5_MASK) >> SCRATCH_REG5_SCRATCH_REG5_SHIFT) + +#define SCRATCH_REG5_SET_SCRATCH_REG5(scratch_reg5_reg, scratch_reg5) \ + scratch_reg5_reg = (scratch_reg5_reg & ~SCRATCH_REG5_SCRATCH_REG5_MASK) | (scratch_reg5 << SCRATCH_REG5_SCRATCH_REG5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg5_t { + unsigned int scratch_reg5 : SCRATCH_REG5_SCRATCH_REG5_SIZE; + } scratch_reg5_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg5_t { + unsigned int scratch_reg5 : SCRATCH_REG5_SCRATCH_REG5_SIZE; + } scratch_reg5_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg5_t f; +} scratch_reg5_u; + + +/* + * SCRATCH_REG6 struct + */ + +#define SCRATCH_REG6_SCRATCH_REG6_SIZE 32 + +#define SCRATCH_REG6_SCRATCH_REG6_SHIFT 0 + +#define SCRATCH_REG6_SCRATCH_REG6_MASK 0xffffffff + +#define SCRATCH_REG6_MASK \ + (SCRATCH_REG6_SCRATCH_REG6_MASK) + +#define SCRATCH_REG6(scratch_reg6) \ + ((scratch_reg6 << SCRATCH_REG6_SCRATCH_REG6_SHIFT)) + +#define SCRATCH_REG6_GET_SCRATCH_REG6(scratch_reg6) \ + ((scratch_reg6 & SCRATCH_REG6_SCRATCH_REG6_MASK) >> SCRATCH_REG6_SCRATCH_REG6_SHIFT) + +#define SCRATCH_REG6_SET_SCRATCH_REG6(scratch_reg6_reg, scratch_reg6) \ + scratch_reg6_reg = (scratch_reg6_reg & ~SCRATCH_REG6_SCRATCH_REG6_MASK) | (scratch_reg6 << SCRATCH_REG6_SCRATCH_REG6_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg6_t { + unsigned int scratch_reg6 : SCRATCH_REG6_SCRATCH_REG6_SIZE; + } scratch_reg6_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg6_t { + unsigned int scratch_reg6 : SCRATCH_REG6_SCRATCH_REG6_SIZE; + } scratch_reg6_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg6_t f; +} scratch_reg6_u; + + +/* + * SCRATCH_REG7 struct + */ + +#define SCRATCH_REG7_SCRATCH_REG7_SIZE 32 + +#define SCRATCH_REG7_SCRATCH_REG7_SHIFT 0 + +#define SCRATCH_REG7_SCRATCH_REG7_MASK 0xffffffff + +#define SCRATCH_REG7_MASK \ + (SCRATCH_REG7_SCRATCH_REG7_MASK) + +#define SCRATCH_REG7(scratch_reg7) \ + ((scratch_reg7 << SCRATCH_REG7_SCRATCH_REG7_SHIFT)) + +#define SCRATCH_REG7_GET_SCRATCH_REG7(scratch_reg7) \ + ((scratch_reg7 & SCRATCH_REG7_SCRATCH_REG7_MASK) >> SCRATCH_REG7_SCRATCH_REG7_SHIFT) + +#define SCRATCH_REG7_SET_SCRATCH_REG7(scratch_reg7_reg, scratch_reg7) \ + scratch_reg7_reg = (scratch_reg7_reg & ~SCRATCH_REG7_SCRATCH_REG7_MASK) | (scratch_reg7 << SCRATCH_REG7_SCRATCH_REG7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg7_t { + unsigned int scratch_reg7 : SCRATCH_REG7_SCRATCH_REG7_SIZE; + } scratch_reg7_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg7_t { + unsigned int scratch_reg7 : SCRATCH_REG7_SCRATCH_REG7_SIZE; + } scratch_reg7_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg7_t f; +} scratch_reg7_u; + + +/* + * SCRATCH_UMSK struct + */ + +#define SCRATCH_UMSK_SCRATCH_UMSK_SIZE 8 +#define SCRATCH_UMSK_SCRATCH_SWAP_SIZE 2 + +#define SCRATCH_UMSK_SCRATCH_UMSK_SHIFT 0 +#define SCRATCH_UMSK_SCRATCH_SWAP_SHIFT 16 + +#define SCRATCH_UMSK_SCRATCH_UMSK_MASK 0x000000ff +#define SCRATCH_UMSK_SCRATCH_SWAP_MASK 0x00030000 + +#define SCRATCH_UMSK_MASK \ + (SCRATCH_UMSK_SCRATCH_UMSK_MASK | \ + SCRATCH_UMSK_SCRATCH_SWAP_MASK) + +#define SCRATCH_UMSK(scratch_umsk, scratch_swap) \ + ((scratch_umsk << SCRATCH_UMSK_SCRATCH_UMSK_SHIFT) | \ + (scratch_swap << SCRATCH_UMSK_SCRATCH_SWAP_SHIFT)) + +#define SCRATCH_UMSK_GET_SCRATCH_UMSK(scratch_umsk) \ + ((scratch_umsk & SCRATCH_UMSK_SCRATCH_UMSK_MASK) >> SCRATCH_UMSK_SCRATCH_UMSK_SHIFT) +#define SCRATCH_UMSK_GET_SCRATCH_SWAP(scratch_umsk) \ + ((scratch_umsk & SCRATCH_UMSK_SCRATCH_SWAP_MASK) >> SCRATCH_UMSK_SCRATCH_SWAP_SHIFT) + +#define SCRATCH_UMSK_SET_SCRATCH_UMSK(scratch_umsk_reg, scratch_umsk) \ + scratch_umsk_reg = (scratch_umsk_reg & ~SCRATCH_UMSK_SCRATCH_UMSK_MASK) | (scratch_umsk << SCRATCH_UMSK_SCRATCH_UMSK_SHIFT) +#define SCRATCH_UMSK_SET_SCRATCH_SWAP(scratch_umsk_reg, scratch_swap) \ + scratch_umsk_reg = (scratch_umsk_reg & ~SCRATCH_UMSK_SCRATCH_SWAP_MASK) | (scratch_swap << SCRATCH_UMSK_SCRATCH_SWAP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_umsk_t { + unsigned int scratch_umsk : SCRATCH_UMSK_SCRATCH_UMSK_SIZE; + unsigned int : 8; + unsigned int scratch_swap : SCRATCH_UMSK_SCRATCH_SWAP_SIZE; + unsigned int : 14; + } scratch_umsk_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_umsk_t { + unsigned int : 14; + unsigned int scratch_swap : SCRATCH_UMSK_SCRATCH_SWAP_SIZE; + unsigned int : 8; + unsigned int scratch_umsk : SCRATCH_UMSK_SCRATCH_UMSK_SIZE; + } scratch_umsk_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_umsk_t f; +} scratch_umsk_u; + + +/* + * SCRATCH_ADDR struct + */ + +#define SCRATCH_ADDR_SCRATCH_ADDR_SIZE 27 + +#define SCRATCH_ADDR_SCRATCH_ADDR_SHIFT 5 + +#define SCRATCH_ADDR_SCRATCH_ADDR_MASK 0xffffffe0 + +#define SCRATCH_ADDR_MASK \ + (SCRATCH_ADDR_SCRATCH_ADDR_MASK) + +#define SCRATCH_ADDR(scratch_addr) \ + ((scratch_addr << SCRATCH_ADDR_SCRATCH_ADDR_SHIFT)) + +#define SCRATCH_ADDR_GET_SCRATCH_ADDR(scratch_addr) \ + ((scratch_addr & SCRATCH_ADDR_SCRATCH_ADDR_MASK) >> SCRATCH_ADDR_SCRATCH_ADDR_SHIFT) + +#define SCRATCH_ADDR_SET_SCRATCH_ADDR(scratch_addr_reg, scratch_addr) \ + scratch_addr_reg = (scratch_addr_reg & ~SCRATCH_ADDR_SCRATCH_ADDR_MASK) | (scratch_addr << SCRATCH_ADDR_SCRATCH_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_addr_t { + unsigned int : 5; + unsigned int scratch_addr : SCRATCH_ADDR_SCRATCH_ADDR_SIZE; + } scratch_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_addr_t { + unsigned int scratch_addr : SCRATCH_ADDR_SCRATCH_ADDR_SIZE; + unsigned int : 5; + } scratch_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_addr_t f; +} scratch_addr_u; + + +/* + * CP_ME_VS_EVENT_SRC struct + */ + +#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE 1 +#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE 1 + +#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT 0 +#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT 1 + +#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK 0x00000001 +#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK 0x00000002 + +#define CP_ME_VS_EVENT_SRC_MASK \ + (CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK | \ + CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) + +#define CP_ME_VS_EVENT_SRC(vs_done_swm, vs_done_cntr) \ + ((vs_done_swm << CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT) | \ + (vs_done_cntr << CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT)) + +#define CP_ME_VS_EVENT_SRC_GET_VS_DONE_SWM(cp_me_vs_event_src) \ + ((cp_me_vs_event_src & CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK) >> CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT) +#define CP_ME_VS_EVENT_SRC_GET_VS_DONE_CNTR(cp_me_vs_event_src) \ + ((cp_me_vs_event_src & CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) >> CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT) + +#define CP_ME_VS_EVENT_SRC_SET_VS_DONE_SWM(cp_me_vs_event_src_reg, vs_done_swm) \ + cp_me_vs_event_src_reg = (cp_me_vs_event_src_reg & ~CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK) | (vs_done_swm << CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT) +#define CP_ME_VS_EVENT_SRC_SET_VS_DONE_CNTR(cp_me_vs_event_src_reg, vs_done_cntr) \ + cp_me_vs_event_src_reg = (cp_me_vs_event_src_reg & ~CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) | (vs_done_cntr << CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_src_t { + unsigned int vs_done_swm : CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE; + unsigned int vs_done_cntr : CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE; + unsigned int : 30; + } cp_me_vs_event_src_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_src_t { + unsigned int : 30; + unsigned int vs_done_cntr : CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE; + unsigned int vs_done_swm : CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE; + } cp_me_vs_event_src_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_src_t f; +} cp_me_vs_event_src_u; + + +/* + * CP_ME_VS_EVENT_ADDR struct + */ + +#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE 2 +#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE 30 + +#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT 0 +#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT 2 + +#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK 0x00000003 +#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK 0xfffffffc + +#define CP_ME_VS_EVENT_ADDR_MASK \ + (CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK | \ + CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) + +#define CP_ME_VS_EVENT_ADDR(vs_done_swap, vs_done_addr) \ + ((vs_done_swap << CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT) | \ + (vs_done_addr << CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT)) + +#define CP_ME_VS_EVENT_ADDR_GET_VS_DONE_SWAP(cp_me_vs_event_addr) \ + ((cp_me_vs_event_addr & CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK) >> CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT) +#define CP_ME_VS_EVENT_ADDR_GET_VS_DONE_ADDR(cp_me_vs_event_addr) \ + ((cp_me_vs_event_addr & CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) >> CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT) + +#define CP_ME_VS_EVENT_ADDR_SET_VS_DONE_SWAP(cp_me_vs_event_addr_reg, vs_done_swap) \ + cp_me_vs_event_addr_reg = (cp_me_vs_event_addr_reg & ~CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK) | (vs_done_swap << CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT) +#define CP_ME_VS_EVENT_ADDR_SET_VS_DONE_ADDR(cp_me_vs_event_addr_reg, vs_done_addr) \ + cp_me_vs_event_addr_reg = (cp_me_vs_event_addr_reg & ~CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) | (vs_done_addr << CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_addr_t { + unsigned int vs_done_swap : CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE; + unsigned int vs_done_addr : CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE; + } cp_me_vs_event_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_addr_t { + unsigned int vs_done_addr : CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE; + unsigned int vs_done_swap : CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE; + } cp_me_vs_event_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_addr_t f; +} cp_me_vs_event_addr_u; + + +/* + * CP_ME_VS_EVENT_DATA struct + */ + +#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE 32 + +#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT 0 + +#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK 0xffffffff + +#define CP_ME_VS_EVENT_DATA_MASK \ + (CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) + +#define CP_ME_VS_EVENT_DATA(vs_done_data) \ + ((vs_done_data << CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT)) + +#define CP_ME_VS_EVENT_DATA_GET_VS_DONE_DATA(cp_me_vs_event_data) \ + ((cp_me_vs_event_data & CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) >> CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT) + +#define CP_ME_VS_EVENT_DATA_SET_VS_DONE_DATA(cp_me_vs_event_data_reg, vs_done_data) \ + cp_me_vs_event_data_reg = (cp_me_vs_event_data_reg & ~CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) | (vs_done_data << CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_data_t { + unsigned int vs_done_data : CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE; + } cp_me_vs_event_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_data_t { + unsigned int vs_done_data : CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE; + } cp_me_vs_event_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_data_t f; +} cp_me_vs_event_data_u; + + +/* + * CP_ME_VS_EVENT_ADDR_SWM struct + */ + +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE 2 +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE 30 + +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT 0 +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT 2 + +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK 0x00000003 +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK 0xfffffffc + +#define CP_ME_VS_EVENT_ADDR_SWM_MASK \ + (CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK | \ + CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) + +#define CP_ME_VS_EVENT_ADDR_SWM(vs_done_swap_swm, vs_done_addr_swm) \ + ((vs_done_swap_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT) | \ + (vs_done_addr_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT)) + +#define CP_ME_VS_EVENT_ADDR_SWM_GET_VS_DONE_SWAP_SWM(cp_me_vs_event_addr_swm) \ + ((cp_me_vs_event_addr_swm & CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK) >> CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT) +#define CP_ME_VS_EVENT_ADDR_SWM_GET_VS_DONE_ADDR_SWM(cp_me_vs_event_addr_swm) \ + ((cp_me_vs_event_addr_swm & CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) >> CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT) + +#define CP_ME_VS_EVENT_ADDR_SWM_SET_VS_DONE_SWAP_SWM(cp_me_vs_event_addr_swm_reg, vs_done_swap_swm) \ + cp_me_vs_event_addr_swm_reg = (cp_me_vs_event_addr_swm_reg & ~CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK) | (vs_done_swap_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT) +#define CP_ME_VS_EVENT_ADDR_SWM_SET_VS_DONE_ADDR_SWM(cp_me_vs_event_addr_swm_reg, vs_done_addr_swm) \ + cp_me_vs_event_addr_swm_reg = (cp_me_vs_event_addr_swm_reg & ~CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) | (vs_done_addr_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_addr_swm_t { + unsigned int vs_done_swap_swm : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE; + unsigned int vs_done_addr_swm : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE; + } cp_me_vs_event_addr_swm_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_addr_swm_t { + unsigned int vs_done_addr_swm : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE; + unsigned int vs_done_swap_swm : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE; + } cp_me_vs_event_addr_swm_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_addr_swm_t f; +} cp_me_vs_event_addr_swm_u; + + +/* + * CP_ME_VS_EVENT_DATA_SWM struct + */ + +#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE 32 + +#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT 0 + +#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK 0xffffffff + +#define CP_ME_VS_EVENT_DATA_SWM_MASK \ + (CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) + +#define CP_ME_VS_EVENT_DATA_SWM(vs_done_data_swm) \ + ((vs_done_data_swm << CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT)) + +#define CP_ME_VS_EVENT_DATA_SWM_GET_VS_DONE_DATA_SWM(cp_me_vs_event_data_swm) \ + ((cp_me_vs_event_data_swm & CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) >> CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT) + +#define CP_ME_VS_EVENT_DATA_SWM_SET_VS_DONE_DATA_SWM(cp_me_vs_event_data_swm_reg, vs_done_data_swm) \ + cp_me_vs_event_data_swm_reg = (cp_me_vs_event_data_swm_reg & ~CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) | (vs_done_data_swm << CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_data_swm_t { + unsigned int vs_done_data_swm : CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE; + } cp_me_vs_event_data_swm_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_data_swm_t { + unsigned int vs_done_data_swm : CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE; + } cp_me_vs_event_data_swm_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_data_swm_t f; +} cp_me_vs_event_data_swm_u; + + +/* + * CP_ME_PS_EVENT_SRC struct + */ + +#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE 1 +#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE 1 + +#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT 0 +#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT 1 + +#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK 0x00000001 +#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK 0x00000002 + +#define CP_ME_PS_EVENT_SRC_MASK \ + (CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK | \ + CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) + +#define CP_ME_PS_EVENT_SRC(ps_done_swm, ps_done_cntr) \ + ((ps_done_swm << CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT) | \ + (ps_done_cntr << CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT)) + +#define CP_ME_PS_EVENT_SRC_GET_PS_DONE_SWM(cp_me_ps_event_src) \ + ((cp_me_ps_event_src & CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK) >> CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT) +#define CP_ME_PS_EVENT_SRC_GET_PS_DONE_CNTR(cp_me_ps_event_src) \ + ((cp_me_ps_event_src & CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) >> CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT) + +#define CP_ME_PS_EVENT_SRC_SET_PS_DONE_SWM(cp_me_ps_event_src_reg, ps_done_swm) \ + cp_me_ps_event_src_reg = (cp_me_ps_event_src_reg & ~CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK) | (ps_done_swm << CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT) +#define CP_ME_PS_EVENT_SRC_SET_PS_DONE_CNTR(cp_me_ps_event_src_reg, ps_done_cntr) \ + cp_me_ps_event_src_reg = (cp_me_ps_event_src_reg & ~CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) | (ps_done_cntr << CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_src_t { + unsigned int ps_done_swm : CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE; + unsigned int ps_done_cntr : CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE; + unsigned int : 30; + } cp_me_ps_event_src_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_src_t { + unsigned int : 30; + unsigned int ps_done_cntr : CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE; + unsigned int ps_done_swm : CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE; + } cp_me_ps_event_src_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_src_t f; +} cp_me_ps_event_src_u; + + +/* + * CP_ME_PS_EVENT_ADDR struct + */ + +#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE 2 +#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE 30 + +#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT 0 +#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT 2 + +#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK 0x00000003 +#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK 0xfffffffc + +#define CP_ME_PS_EVENT_ADDR_MASK \ + (CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK | \ + CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) + +#define CP_ME_PS_EVENT_ADDR(ps_done_swap, ps_done_addr) \ + ((ps_done_swap << CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT) | \ + (ps_done_addr << CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT)) + +#define CP_ME_PS_EVENT_ADDR_GET_PS_DONE_SWAP(cp_me_ps_event_addr) \ + ((cp_me_ps_event_addr & CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK) >> CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT) +#define CP_ME_PS_EVENT_ADDR_GET_PS_DONE_ADDR(cp_me_ps_event_addr) \ + ((cp_me_ps_event_addr & CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) >> CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT) + +#define CP_ME_PS_EVENT_ADDR_SET_PS_DONE_SWAP(cp_me_ps_event_addr_reg, ps_done_swap) \ + cp_me_ps_event_addr_reg = (cp_me_ps_event_addr_reg & ~CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK) | (ps_done_swap << CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT) +#define CP_ME_PS_EVENT_ADDR_SET_PS_DONE_ADDR(cp_me_ps_event_addr_reg, ps_done_addr) \ + cp_me_ps_event_addr_reg = (cp_me_ps_event_addr_reg & ~CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) | (ps_done_addr << CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_addr_t { + unsigned int ps_done_swap : CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE; + unsigned int ps_done_addr : CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE; + } cp_me_ps_event_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_addr_t { + unsigned int ps_done_addr : CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE; + unsigned int ps_done_swap : CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE; + } cp_me_ps_event_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_addr_t f; +} cp_me_ps_event_addr_u; + + +/* + * CP_ME_PS_EVENT_DATA struct + */ + +#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE 32 + +#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT 0 + +#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK 0xffffffff + +#define CP_ME_PS_EVENT_DATA_MASK \ + (CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) + +#define CP_ME_PS_EVENT_DATA(ps_done_data) \ + ((ps_done_data << CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT)) + +#define CP_ME_PS_EVENT_DATA_GET_PS_DONE_DATA(cp_me_ps_event_data) \ + ((cp_me_ps_event_data & CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) >> CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT) + +#define CP_ME_PS_EVENT_DATA_SET_PS_DONE_DATA(cp_me_ps_event_data_reg, ps_done_data) \ + cp_me_ps_event_data_reg = (cp_me_ps_event_data_reg & ~CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) | (ps_done_data << CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_data_t { + unsigned int ps_done_data : CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE; + } cp_me_ps_event_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_data_t { + unsigned int ps_done_data : CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE; + } cp_me_ps_event_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_data_t f; +} cp_me_ps_event_data_u; + + +/* + * CP_ME_PS_EVENT_ADDR_SWM struct + */ + +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE 2 +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE 30 + +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT 0 +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT 2 + +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK 0x00000003 +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK 0xfffffffc + +#define CP_ME_PS_EVENT_ADDR_SWM_MASK \ + (CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK | \ + CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) + +#define CP_ME_PS_EVENT_ADDR_SWM(ps_done_swap_swm, ps_done_addr_swm) \ + ((ps_done_swap_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT) | \ + (ps_done_addr_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT)) + +#define CP_ME_PS_EVENT_ADDR_SWM_GET_PS_DONE_SWAP_SWM(cp_me_ps_event_addr_swm) \ + ((cp_me_ps_event_addr_swm & CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK) >> CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT) +#define CP_ME_PS_EVENT_ADDR_SWM_GET_PS_DONE_ADDR_SWM(cp_me_ps_event_addr_swm) \ + ((cp_me_ps_event_addr_swm & CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) >> CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT) + +#define CP_ME_PS_EVENT_ADDR_SWM_SET_PS_DONE_SWAP_SWM(cp_me_ps_event_addr_swm_reg, ps_done_swap_swm) \ + cp_me_ps_event_addr_swm_reg = (cp_me_ps_event_addr_swm_reg & ~CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK) | (ps_done_swap_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT) +#define CP_ME_PS_EVENT_ADDR_SWM_SET_PS_DONE_ADDR_SWM(cp_me_ps_event_addr_swm_reg, ps_done_addr_swm) \ + cp_me_ps_event_addr_swm_reg = (cp_me_ps_event_addr_swm_reg & ~CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) | (ps_done_addr_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_addr_swm_t { + unsigned int ps_done_swap_swm : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE; + unsigned int ps_done_addr_swm : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE; + } cp_me_ps_event_addr_swm_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_addr_swm_t { + unsigned int ps_done_addr_swm : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE; + unsigned int ps_done_swap_swm : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE; + } cp_me_ps_event_addr_swm_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_addr_swm_t f; +} cp_me_ps_event_addr_swm_u; + + +/* + * CP_ME_PS_EVENT_DATA_SWM struct + */ + +#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE 32 + +#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT 0 + +#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK 0xffffffff + +#define CP_ME_PS_EVENT_DATA_SWM_MASK \ + (CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) + +#define CP_ME_PS_EVENT_DATA_SWM(ps_done_data_swm) \ + ((ps_done_data_swm << CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT)) + +#define CP_ME_PS_EVENT_DATA_SWM_GET_PS_DONE_DATA_SWM(cp_me_ps_event_data_swm) \ + ((cp_me_ps_event_data_swm & CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) >> CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT) + +#define CP_ME_PS_EVENT_DATA_SWM_SET_PS_DONE_DATA_SWM(cp_me_ps_event_data_swm_reg, ps_done_data_swm) \ + cp_me_ps_event_data_swm_reg = (cp_me_ps_event_data_swm_reg & ~CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) | (ps_done_data_swm << CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_data_swm_t { + unsigned int ps_done_data_swm : CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE; + } cp_me_ps_event_data_swm_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_data_swm_t { + unsigned int ps_done_data_swm : CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE; + } cp_me_ps_event_data_swm_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_data_swm_t f; +} cp_me_ps_event_data_swm_u; + + +/* + * CP_ME_CF_EVENT_SRC struct + */ + +#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE 1 + +#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT 0 + +#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK 0x00000001 + +#define CP_ME_CF_EVENT_SRC_MASK \ + (CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) + +#define CP_ME_CF_EVENT_SRC(cf_done_src) \ + ((cf_done_src << CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT)) + +#define CP_ME_CF_EVENT_SRC_GET_CF_DONE_SRC(cp_me_cf_event_src) \ + ((cp_me_cf_event_src & CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) >> CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT) + +#define CP_ME_CF_EVENT_SRC_SET_CF_DONE_SRC(cp_me_cf_event_src_reg, cf_done_src) \ + cp_me_cf_event_src_reg = (cp_me_cf_event_src_reg & ~CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) | (cf_done_src << CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_cf_event_src_t { + unsigned int cf_done_src : CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE; + unsigned int : 31; + } cp_me_cf_event_src_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_cf_event_src_t { + unsigned int : 31; + unsigned int cf_done_src : CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE; + } cp_me_cf_event_src_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_cf_event_src_t f; +} cp_me_cf_event_src_u; + + +/* + * CP_ME_CF_EVENT_ADDR struct + */ + +#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE 2 +#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE 30 + +#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT 0 +#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT 2 + +#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK 0x00000003 +#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK 0xfffffffc + +#define CP_ME_CF_EVENT_ADDR_MASK \ + (CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK | \ + CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) + +#define CP_ME_CF_EVENT_ADDR(cf_done_swap, cf_done_addr) \ + ((cf_done_swap << CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT) | \ + (cf_done_addr << CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT)) + +#define CP_ME_CF_EVENT_ADDR_GET_CF_DONE_SWAP(cp_me_cf_event_addr) \ + ((cp_me_cf_event_addr & CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK) >> CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT) +#define CP_ME_CF_EVENT_ADDR_GET_CF_DONE_ADDR(cp_me_cf_event_addr) \ + ((cp_me_cf_event_addr & CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) >> CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT) + +#define CP_ME_CF_EVENT_ADDR_SET_CF_DONE_SWAP(cp_me_cf_event_addr_reg, cf_done_swap) \ + cp_me_cf_event_addr_reg = (cp_me_cf_event_addr_reg & ~CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK) | (cf_done_swap << CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT) +#define CP_ME_CF_EVENT_ADDR_SET_CF_DONE_ADDR(cp_me_cf_event_addr_reg, cf_done_addr) \ + cp_me_cf_event_addr_reg = (cp_me_cf_event_addr_reg & ~CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) | (cf_done_addr << CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_cf_event_addr_t { + unsigned int cf_done_swap : CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE; + unsigned int cf_done_addr : CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE; + } cp_me_cf_event_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_cf_event_addr_t { + unsigned int cf_done_addr : CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE; + unsigned int cf_done_swap : CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE; + } cp_me_cf_event_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_cf_event_addr_t f; +} cp_me_cf_event_addr_u; + + +/* + * CP_ME_CF_EVENT_DATA struct + */ + +#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE 32 + +#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT 0 + +#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK 0xffffffff + +#define CP_ME_CF_EVENT_DATA_MASK \ + (CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) + +#define CP_ME_CF_EVENT_DATA(cf_done_data) \ + ((cf_done_data << CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT)) + +#define CP_ME_CF_EVENT_DATA_GET_CF_DONE_DATA(cp_me_cf_event_data) \ + ((cp_me_cf_event_data & CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) >> CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT) + +#define CP_ME_CF_EVENT_DATA_SET_CF_DONE_DATA(cp_me_cf_event_data_reg, cf_done_data) \ + cp_me_cf_event_data_reg = (cp_me_cf_event_data_reg & ~CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) | (cf_done_data << CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_cf_event_data_t { + unsigned int cf_done_data : CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE; + } cp_me_cf_event_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_cf_event_data_t { + unsigned int cf_done_data : CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE; + } cp_me_cf_event_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_cf_event_data_t f; +} cp_me_cf_event_data_u; + + +/* + * CP_ME_NRT_ADDR struct + */ + +#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE 2 +#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE 30 + +#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT 0 +#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT 2 + +#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK 0x00000003 +#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK 0xfffffffc + +#define CP_ME_NRT_ADDR_MASK \ + (CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK | \ + CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) + +#define CP_ME_NRT_ADDR(nrt_write_swap, nrt_write_addr) \ + ((nrt_write_swap << CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT) | \ + (nrt_write_addr << CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT)) + +#define CP_ME_NRT_ADDR_GET_NRT_WRITE_SWAP(cp_me_nrt_addr) \ + ((cp_me_nrt_addr & CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK) >> CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT) +#define CP_ME_NRT_ADDR_GET_NRT_WRITE_ADDR(cp_me_nrt_addr) \ + ((cp_me_nrt_addr & CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) >> CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT) + +#define CP_ME_NRT_ADDR_SET_NRT_WRITE_SWAP(cp_me_nrt_addr_reg, nrt_write_swap) \ + cp_me_nrt_addr_reg = (cp_me_nrt_addr_reg & ~CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK) | (nrt_write_swap << CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT) +#define CP_ME_NRT_ADDR_SET_NRT_WRITE_ADDR(cp_me_nrt_addr_reg, nrt_write_addr) \ + cp_me_nrt_addr_reg = (cp_me_nrt_addr_reg & ~CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) | (nrt_write_addr << CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_nrt_addr_t { + unsigned int nrt_write_swap : CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE; + unsigned int nrt_write_addr : CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE; + } cp_me_nrt_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_nrt_addr_t { + unsigned int nrt_write_addr : CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE; + unsigned int nrt_write_swap : CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE; + } cp_me_nrt_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_nrt_addr_t f; +} cp_me_nrt_addr_u; + + +/* + * CP_ME_NRT_DATA struct + */ + +#define CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE 32 + +#define CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT 0 + +#define CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK 0xffffffff + +#define CP_ME_NRT_DATA_MASK \ + (CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) + +#define CP_ME_NRT_DATA(nrt_write_data) \ + ((nrt_write_data << CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT)) + +#define CP_ME_NRT_DATA_GET_NRT_WRITE_DATA(cp_me_nrt_data) \ + ((cp_me_nrt_data & CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) >> CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT) + +#define CP_ME_NRT_DATA_SET_NRT_WRITE_DATA(cp_me_nrt_data_reg, nrt_write_data) \ + cp_me_nrt_data_reg = (cp_me_nrt_data_reg & ~CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) | (nrt_write_data << CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_nrt_data_t { + unsigned int nrt_write_data : CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE; + } cp_me_nrt_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_nrt_data_t { + unsigned int nrt_write_data : CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE; + } cp_me_nrt_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_nrt_data_t f; +} cp_me_nrt_data_u; + + +/* + * CP_ME_VS_FETCH_DONE_SRC struct + */ + +#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE 1 + +#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT 0 + +#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK 0x00000001 + +#define CP_ME_VS_FETCH_DONE_SRC_MASK \ + (CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) + +#define CP_ME_VS_FETCH_DONE_SRC(vs_fetch_done_cntr) \ + ((vs_fetch_done_cntr << CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT)) + +#define CP_ME_VS_FETCH_DONE_SRC_GET_VS_FETCH_DONE_CNTR(cp_me_vs_fetch_done_src) \ + ((cp_me_vs_fetch_done_src & CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) >> CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT) + +#define CP_ME_VS_FETCH_DONE_SRC_SET_VS_FETCH_DONE_CNTR(cp_me_vs_fetch_done_src_reg, vs_fetch_done_cntr) \ + cp_me_vs_fetch_done_src_reg = (cp_me_vs_fetch_done_src_reg & ~CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) | (vs_fetch_done_cntr << CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_src_t { + unsigned int vs_fetch_done_cntr : CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE; + unsigned int : 31; + } cp_me_vs_fetch_done_src_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_src_t { + unsigned int : 31; + unsigned int vs_fetch_done_cntr : CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE; + } cp_me_vs_fetch_done_src_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_fetch_done_src_t f; +} cp_me_vs_fetch_done_src_u; + + +/* + * CP_ME_VS_FETCH_DONE_ADDR struct + */ + +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE 2 +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE 30 + +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT 0 +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT 2 + +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK 0x00000003 +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK 0xfffffffc + +#define CP_ME_VS_FETCH_DONE_ADDR_MASK \ + (CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK | \ + CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) + +#define CP_ME_VS_FETCH_DONE_ADDR(vs_fetch_done_swap, vs_fetch_done_addr) \ + ((vs_fetch_done_swap << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT) | \ + (vs_fetch_done_addr << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT)) + +#define CP_ME_VS_FETCH_DONE_ADDR_GET_VS_FETCH_DONE_SWAP(cp_me_vs_fetch_done_addr) \ + ((cp_me_vs_fetch_done_addr & CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK) >> CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT) +#define CP_ME_VS_FETCH_DONE_ADDR_GET_VS_FETCH_DONE_ADDR(cp_me_vs_fetch_done_addr) \ + ((cp_me_vs_fetch_done_addr & CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) >> CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT) + +#define CP_ME_VS_FETCH_DONE_ADDR_SET_VS_FETCH_DONE_SWAP(cp_me_vs_fetch_done_addr_reg, vs_fetch_done_swap) \ + cp_me_vs_fetch_done_addr_reg = (cp_me_vs_fetch_done_addr_reg & ~CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK) | (vs_fetch_done_swap << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT) +#define CP_ME_VS_FETCH_DONE_ADDR_SET_VS_FETCH_DONE_ADDR(cp_me_vs_fetch_done_addr_reg, vs_fetch_done_addr) \ + cp_me_vs_fetch_done_addr_reg = (cp_me_vs_fetch_done_addr_reg & ~CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) | (vs_fetch_done_addr << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_addr_t { + unsigned int vs_fetch_done_swap : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE; + unsigned int vs_fetch_done_addr : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE; + } cp_me_vs_fetch_done_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_addr_t { + unsigned int vs_fetch_done_addr : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE; + unsigned int vs_fetch_done_swap : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE; + } cp_me_vs_fetch_done_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_fetch_done_addr_t f; +} cp_me_vs_fetch_done_addr_u; + + +/* + * CP_ME_VS_FETCH_DONE_DATA struct + */ + +#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE 32 + +#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT 0 + +#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK 0xffffffff + +#define CP_ME_VS_FETCH_DONE_DATA_MASK \ + (CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) + +#define CP_ME_VS_FETCH_DONE_DATA(vs_fetch_done_data) \ + ((vs_fetch_done_data << CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT)) + +#define CP_ME_VS_FETCH_DONE_DATA_GET_VS_FETCH_DONE_DATA(cp_me_vs_fetch_done_data) \ + ((cp_me_vs_fetch_done_data & CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) >> CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT) + +#define CP_ME_VS_FETCH_DONE_DATA_SET_VS_FETCH_DONE_DATA(cp_me_vs_fetch_done_data_reg, vs_fetch_done_data) \ + cp_me_vs_fetch_done_data_reg = (cp_me_vs_fetch_done_data_reg & ~CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) | (vs_fetch_done_data << CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_data_t { + unsigned int vs_fetch_done_data : CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE; + } cp_me_vs_fetch_done_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_data_t { + unsigned int vs_fetch_done_data : CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE; + } cp_me_vs_fetch_done_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_fetch_done_data_t f; +} cp_me_vs_fetch_done_data_u; + + +/* + * CP_INT_CNTL struct + */ + +#define CP_INT_CNTL_SW_INT_MASK_SIZE 1 +#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE 1 +#define CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE 1 +#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE 1 +#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE 1 +#define CP_INT_CNTL_IB_ERROR_MASK_SIZE 1 +#define CP_INT_CNTL_IB2_INT_MASK_SIZE 1 +#define CP_INT_CNTL_IB1_INT_MASK_SIZE 1 +#define CP_INT_CNTL_RB_INT_MASK_SIZE 1 + +#define CP_INT_CNTL_SW_INT_MASK_SHIFT 19 +#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT 23 +#define CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT 24 +#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT 25 +#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT 26 +#define CP_INT_CNTL_IB_ERROR_MASK_SHIFT 27 +#define CP_INT_CNTL_IB2_INT_MASK_SHIFT 29 +#define CP_INT_CNTL_IB1_INT_MASK_SHIFT 30 +#define CP_INT_CNTL_RB_INT_MASK_SHIFT 31 + +#define CP_INT_CNTL_SW_INT_MASK_MASK 0x00080000 +#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK 0x00800000 +#define CP_INT_CNTL_OPCODE_ERROR_MASK_MASK 0x01000000 +#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK 0x02000000 +#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK 0x04000000 +#define CP_INT_CNTL_IB_ERROR_MASK_MASK 0x08000000 +#define CP_INT_CNTL_IB2_INT_MASK_MASK 0x20000000 +#define CP_INT_CNTL_IB1_INT_MASK_MASK 0x40000000 +#define CP_INT_CNTL_RB_INT_MASK_MASK 0x80000000 + +#define CP_INT_CNTL_MASK \ + (CP_INT_CNTL_SW_INT_MASK_MASK | \ + CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK | \ + CP_INT_CNTL_OPCODE_ERROR_MASK_MASK | \ + CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK | \ + CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK | \ + CP_INT_CNTL_IB_ERROR_MASK_MASK | \ + CP_INT_CNTL_IB2_INT_MASK_MASK | \ + CP_INT_CNTL_IB1_INT_MASK_MASK | \ + CP_INT_CNTL_RB_INT_MASK_MASK) + +#define CP_INT_CNTL(sw_int_mask, t0_packet_in_ib_mask, opcode_error_mask, protected_mode_error_mask, reserved_bit_error_mask, ib_error_mask, ib2_int_mask, ib1_int_mask, rb_int_mask) \ + ((sw_int_mask << CP_INT_CNTL_SW_INT_MASK_SHIFT) | \ + (t0_packet_in_ib_mask << CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT) | \ + (opcode_error_mask << CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT) | \ + (protected_mode_error_mask << CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT) | \ + (reserved_bit_error_mask << CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT) | \ + (ib_error_mask << CP_INT_CNTL_IB_ERROR_MASK_SHIFT) | \ + (ib2_int_mask << CP_INT_CNTL_IB2_INT_MASK_SHIFT) | \ + (ib1_int_mask << CP_INT_CNTL_IB1_INT_MASK_SHIFT) | \ + (rb_int_mask << CP_INT_CNTL_RB_INT_MASK_SHIFT)) + +#define CP_INT_CNTL_GET_SW_INT_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_SW_INT_MASK_MASK) >> CP_INT_CNTL_SW_INT_MASK_SHIFT) +#define CP_INT_CNTL_GET_T0_PACKET_IN_IB_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK) >> CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT) +#define CP_INT_CNTL_GET_OPCODE_ERROR_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_OPCODE_ERROR_MASK_MASK) >> CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_GET_PROTECTED_MODE_ERROR_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK) >> CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_GET_RESERVED_BIT_ERROR_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK) >> CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_GET_IB_ERROR_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_IB_ERROR_MASK_MASK) >> CP_INT_CNTL_IB_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_GET_IB2_INT_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_IB2_INT_MASK_MASK) >> CP_INT_CNTL_IB2_INT_MASK_SHIFT) +#define CP_INT_CNTL_GET_IB1_INT_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_IB1_INT_MASK_MASK) >> CP_INT_CNTL_IB1_INT_MASK_SHIFT) +#define CP_INT_CNTL_GET_RB_INT_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_RB_INT_MASK_MASK) >> CP_INT_CNTL_RB_INT_MASK_SHIFT) + +#define CP_INT_CNTL_SET_SW_INT_MASK(cp_int_cntl_reg, sw_int_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_SW_INT_MASK_MASK) | (sw_int_mask << CP_INT_CNTL_SW_INT_MASK_SHIFT) +#define CP_INT_CNTL_SET_T0_PACKET_IN_IB_MASK(cp_int_cntl_reg, t0_packet_in_ib_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK) | (t0_packet_in_ib_mask << CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT) +#define CP_INT_CNTL_SET_OPCODE_ERROR_MASK(cp_int_cntl_reg, opcode_error_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_OPCODE_ERROR_MASK_MASK) | (opcode_error_mask << CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_SET_PROTECTED_MODE_ERROR_MASK(cp_int_cntl_reg, protected_mode_error_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK) | (protected_mode_error_mask << CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_SET_RESERVED_BIT_ERROR_MASK(cp_int_cntl_reg, reserved_bit_error_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK) | (reserved_bit_error_mask << CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_SET_IB_ERROR_MASK(cp_int_cntl_reg, ib_error_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB_ERROR_MASK_MASK) | (ib_error_mask << CP_INT_CNTL_IB_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_SET_IB2_INT_MASK(cp_int_cntl_reg, ib2_int_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB2_INT_MASK_MASK) | (ib2_int_mask << CP_INT_CNTL_IB2_INT_MASK_SHIFT) +#define CP_INT_CNTL_SET_IB1_INT_MASK(cp_int_cntl_reg, ib1_int_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB1_INT_MASK_MASK) | (ib1_int_mask << CP_INT_CNTL_IB1_INT_MASK_SHIFT) +#define CP_INT_CNTL_SET_RB_INT_MASK(cp_int_cntl_reg, rb_int_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_RB_INT_MASK_MASK) | (rb_int_mask << CP_INT_CNTL_RB_INT_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_int_cntl_t { + unsigned int : 19; + unsigned int sw_int_mask : CP_INT_CNTL_SW_INT_MASK_SIZE; + unsigned int : 3; + unsigned int t0_packet_in_ib_mask : CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE; + unsigned int opcode_error_mask : CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE; + unsigned int protected_mode_error_mask : CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE; + unsigned int reserved_bit_error_mask : CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE; + unsigned int ib_error_mask : CP_INT_CNTL_IB_ERROR_MASK_SIZE; + unsigned int : 1; + unsigned int ib2_int_mask : CP_INT_CNTL_IB2_INT_MASK_SIZE; + unsigned int ib1_int_mask : CP_INT_CNTL_IB1_INT_MASK_SIZE; + unsigned int rb_int_mask : CP_INT_CNTL_RB_INT_MASK_SIZE; + } cp_int_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_int_cntl_t { + unsigned int rb_int_mask : CP_INT_CNTL_RB_INT_MASK_SIZE; + unsigned int ib1_int_mask : CP_INT_CNTL_IB1_INT_MASK_SIZE; + unsigned int ib2_int_mask : CP_INT_CNTL_IB2_INT_MASK_SIZE; + unsigned int : 1; + unsigned int ib_error_mask : CP_INT_CNTL_IB_ERROR_MASK_SIZE; + unsigned int reserved_bit_error_mask : CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE; + unsigned int protected_mode_error_mask : CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE; + unsigned int opcode_error_mask : CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE; + unsigned int t0_packet_in_ib_mask : CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE; + unsigned int : 3; + unsigned int sw_int_mask : CP_INT_CNTL_SW_INT_MASK_SIZE; + unsigned int : 19; + } cp_int_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_int_cntl_t f; +} cp_int_cntl_u; + + +/* + * CP_INT_STATUS struct + */ + +#define CP_INT_STATUS_SW_INT_STAT_SIZE 1 +#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE 1 +#define CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE 1 +#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE 1 +#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE 1 +#define CP_INT_STATUS_IB_ERROR_STAT_SIZE 1 +#define CP_INT_STATUS_IB2_INT_STAT_SIZE 1 +#define CP_INT_STATUS_IB1_INT_STAT_SIZE 1 +#define CP_INT_STATUS_RB_INT_STAT_SIZE 1 + +#define CP_INT_STATUS_SW_INT_STAT_SHIFT 19 +#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT 23 +#define CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT 24 +#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT 25 +#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT 26 +#define CP_INT_STATUS_IB_ERROR_STAT_SHIFT 27 +#define CP_INT_STATUS_IB2_INT_STAT_SHIFT 29 +#define CP_INT_STATUS_IB1_INT_STAT_SHIFT 30 +#define CP_INT_STATUS_RB_INT_STAT_SHIFT 31 + +#define CP_INT_STATUS_SW_INT_STAT_MASK 0x00080000 +#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK 0x00800000 +#define CP_INT_STATUS_OPCODE_ERROR_STAT_MASK 0x01000000 +#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK 0x02000000 +#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK 0x04000000 +#define CP_INT_STATUS_IB_ERROR_STAT_MASK 0x08000000 +#define CP_INT_STATUS_IB2_INT_STAT_MASK 0x20000000 +#define CP_INT_STATUS_IB1_INT_STAT_MASK 0x40000000 +#define CP_INT_STATUS_RB_INT_STAT_MASK 0x80000000 + +#define CP_INT_STATUS_MASK \ + (CP_INT_STATUS_SW_INT_STAT_MASK | \ + CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK | \ + CP_INT_STATUS_OPCODE_ERROR_STAT_MASK | \ + CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK | \ + CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK | \ + CP_INT_STATUS_IB_ERROR_STAT_MASK | \ + CP_INT_STATUS_IB2_INT_STAT_MASK | \ + CP_INT_STATUS_IB1_INT_STAT_MASK | \ + CP_INT_STATUS_RB_INT_STAT_MASK) + +#define CP_INT_STATUS(sw_int_stat, t0_packet_in_ib_stat, opcode_error_stat, protected_mode_error_stat, reserved_bit_error_stat, ib_error_stat, ib2_int_stat, ib1_int_stat, rb_int_stat) \ + ((sw_int_stat << CP_INT_STATUS_SW_INT_STAT_SHIFT) | \ + (t0_packet_in_ib_stat << CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT) | \ + (opcode_error_stat << CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT) | \ + (protected_mode_error_stat << CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT) | \ + (reserved_bit_error_stat << CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT) | \ + (ib_error_stat << CP_INT_STATUS_IB_ERROR_STAT_SHIFT) | \ + (ib2_int_stat << CP_INT_STATUS_IB2_INT_STAT_SHIFT) | \ + (ib1_int_stat << CP_INT_STATUS_IB1_INT_STAT_SHIFT) | \ + (rb_int_stat << CP_INT_STATUS_RB_INT_STAT_SHIFT)) + +#define CP_INT_STATUS_GET_SW_INT_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_SW_INT_STAT_MASK) >> CP_INT_STATUS_SW_INT_STAT_SHIFT) +#define CP_INT_STATUS_GET_T0_PACKET_IN_IB_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK) >> CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT) +#define CP_INT_STATUS_GET_OPCODE_ERROR_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_OPCODE_ERROR_STAT_MASK) >> CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_GET_PROTECTED_MODE_ERROR_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK) >> CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_GET_RESERVED_BIT_ERROR_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK) >> CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_GET_IB_ERROR_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_IB_ERROR_STAT_MASK) >> CP_INT_STATUS_IB_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_GET_IB2_INT_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_IB2_INT_STAT_MASK) >> CP_INT_STATUS_IB2_INT_STAT_SHIFT) +#define CP_INT_STATUS_GET_IB1_INT_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_IB1_INT_STAT_MASK) >> CP_INT_STATUS_IB1_INT_STAT_SHIFT) +#define CP_INT_STATUS_GET_RB_INT_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_RB_INT_STAT_MASK) >> CP_INT_STATUS_RB_INT_STAT_SHIFT) + +#define CP_INT_STATUS_SET_SW_INT_STAT(cp_int_status_reg, sw_int_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_SW_INT_STAT_MASK) | (sw_int_stat << CP_INT_STATUS_SW_INT_STAT_SHIFT) +#define CP_INT_STATUS_SET_T0_PACKET_IN_IB_STAT(cp_int_status_reg, t0_packet_in_ib_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK) | (t0_packet_in_ib_stat << CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT) +#define CP_INT_STATUS_SET_OPCODE_ERROR_STAT(cp_int_status_reg, opcode_error_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_OPCODE_ERROR_STAT_MASK) | (opcode_error_stat << CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_SET_PROTECTED_MODE_ERROR_STAT(cp_int_status_reg, protected_mode_error_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK) | (protected_mode_error_stat << CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_SET_RESERVED_BIT_ERROR_STAT(cp_int_status_reg, reserved_bit_error_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK) | (reserved_bit_error_stat << CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_SET_IB_ERROR_STAT(cp_int_status_reg, ib_error_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB_ERROR_STAT_MASK) | (ib_error_stat << CP_INT_STATUS_IB_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_SET_IB2_INT_STAT(cp_int_status_reg, ib2_int_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB2_INT_STAT_MASK) | (ib2_int_stat << CP_INT_STATUS_IB2_INT_STAT_SHIFT) +#define CP_INT_STATUS_SET_IB1_INT_STAT(cp_int_status_reg, ib1_int_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB1_INT_STAT_MASK) | (ib1_int_stat << CP_INT_STATUS_IB1_INT_STAT_SHIFT) +#define CP_INT_STATUS_SET_RB_INT_STAT(cp_int_status_reg, rb_int_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_RB_INT_STAT_MASK) | (rb_int_stat << CP_INT_STATUS_RB_INT_STAT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_int_status_t { + unsigned int : 19; + unsigned int sw_int_stat : CP_INT_STATUS_SW_INT_STAT_SIZE; + unsigned int : 3; + unsigned int t0_packet_in_ib_stat : CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE; + unsigned int opcode_error_stat : CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE; + unsigned int protected_mode_error_stat : CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE; + unsigned int reserved_bit_error_stat : CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE; + unsigned int ib_error_stat : CP_INT_STATUS_IB_ERROR_STAT_SIZE; + unsigned int : 1; + unsigned int ib2_int_stat : CP_INT_STATUS_IB2_INT_STAT_SIZE; + unsigned int ib1_int_stat : CP_INT_STATUS_IB1_INT_STAT_SIZE; + unsigned int rb_int_stat : CP_INT_STATUS_RB_INT_STAT_SIZE; + } cp_int_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_int_status_t { + unsigned int rb_int_stat : CP_INT_STATUS_RB_INT_STAT_SIZE; + unsigned int ib1_int_stat : CP_INT_STATUS_IB1_INT_STAT_SIZE; + unsigned int ib2_int_stat : CP_INT_STATUS_IB2_INT_STAT_SIZE; + unsigned int : 1; + unsigned int ib_error_stat : CP_INT_STATUS_IB_ERROR_STAT_SIZE; + unsigned int reserved_bit_error_stat : CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE; + unsigned int protected_mode_error_stat : CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE; + unsigned int opcode_error_stat : CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE; + unsigned int t0_packet_in_ib_stat : CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE; + unsigned int : 3; + unsigned int sw_int_stat : CP_INT_STATUS_SW_INT_STAT_SIZE; + unsigned int : 19; + } cp_int_status_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_int_status_t f; +} cp_int_status_u; + + +/* + * CP_INT_ACK struct + */ + +#define CP_INT_ACK_SW_INT_ACK_SIZE 1 +#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE 1 +#define CP_INT_ACK_OPCODE_ERROR_ACK_SIZE 1 +#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE 1 +#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE 1 +#define CP_INT_ACK_IB_ERROR_ACK_SIZE 1 +#define CP_INT_ACK_IB2_INT_ACK_SIZE 1 +#define CP_INT_ACK_IB1_INT_ACK_SIZE 1 +#define CP_INT_ACK_RB_INT_ACK_SIZE 1 + +#define CP_INT_ACK_SW_INT_ACK_SHIFT 19 +#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT 23 +#define CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT 24 +#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT 25 +#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT 26 +#define CP_INT_ACK_IB_ERROR_ACK_SHIFT 27 +#define CP_INT_ACK_IB2_INT_ACK_SHIFT 29 +#define CP_INT_ACK_IB1_INT_ACK_SHIFT 30 +#define CP_INT_ACK_RB_INT_ACK_SHIFT 31 + +#define CP_INT_ACK_SW_INT_ACK_MASK 0x00080000 +#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK 0x00800000 +#define CP_INT_ACK_OPCODE_ERROR_ACK_MASK 0x01000000 +#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK 0x02000000 +#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK 0x04000000 +#define CP_INT_ACK_IB_ERROR_ACK_MASK 0x08000000 +#define CP_INT_ACK_IB2_INT_ACK_MASK 0x20000000 +#define CP_INT_ACK_IB1_INT_ACK_MASK 0x40000000 +#define CP_INT_ACK_RB_INT_ACK_MASK 0x80000000 + +#define CP_INT_ACK_MASK \ + (CP_INT_ACK_SW_INT_ACK_MASK | \ + CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK | \ + CP_INT_ACK_OPCODE_ERROR_ACK_MASK | \ + CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK | \ + CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK | \ + CP_INT_ACK_IB_ERROR_ACK_MASK | \ + CP_INT_ACK_IB2_INT_ACK_MASK | \ + CP_INT_ACK_IB1_INT_ACK_MASK | \ + CP_INT_ACK_RB_INT_ACK_MASK) + +#define CP_INT_ACK(sw_int_ack, t0_packet_in_ib_ack, opcode_error_ack, protected_mode_error_ack, reserved_bit_error_ack, ib_error_ack, ib2_int_ack, ib1_int_ack, rb_int_ack) \ + ((sw_int_ack << CP_INT_ACK_SW_INT_ACK_SHIFT) | \ + (t0_packet_in_ib_ack << CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT) | \ + (opcode_error_ack << CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT) | \ + (protected_mode_error_ack << CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT) | \ + (reserved_bit_error_ack << CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT) | \ + (ib_error_ack << CP_INT_ACK_IB_ERROR_ACK_SHIFT) | \ + (ib2_int_ack << CP_INT_ACK_IB2_INT_ACK_SHIFT) | \ + (ib1_int_ack << CP_INT_ACK_IB1_INT_ACK_SHIFT) | \ + (rb_int_ack << CP_INT_ACK_RB_INT_ACK_SHIFT)) + +#define CP_INT_ACK_GET_SW_INT_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_SW_INT_ACK_MASK) >> CP_INT_ACK_SW_INT_ACK_SHIFT) +#define CP_INT_ACK_GET_T0_PACKET_IN_IB_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK) >> CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT) +#define CP_INT_ACK_GET_OPCODE_ERROR_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_OPCODE_ERROR_ACK_MASK) >> CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT) +#define CP_INT_ACK_GET_PROTECTED_MODE_ERROR_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK) >> CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT) +#define CP_INT_ACK_GET_RESERVED_BIT_ERROR_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK) >> CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT) +#define CP_INT_ACK_GET_IB_ERROR_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_IB_ERROR_ACK_MASK) >> CP_INT_ACK_IB_ERROR_ACK_SHIFT) +#define CP_INT_ACK_GET_IB2_INT_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_IB2_INT_ACK_MASK) >> CP_INT_ACK_IB2_INT_ACK_SHIFT) +#define CP_INT_ACK_GET_IB1_INT_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_IB1_INT_ACK_MASK) >> CP_INT_ACK_IB1_INT_ACK_SHIFT) +#define CP_INT_ACK_GET_RB_INT_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_RB_INT_ACK_MASK) >> CP_INT_ACK_RB_INT_ACK_SHIFT) + +#define CP_INT_ACK_SET_SW_INT_ACK(cp_int_ack_reg, sw_int_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_SW_INT_ACK_MASK) | (sw_int_ack << CP_INT_ACK_SW_INT_ACK_SHIFT) +#define CP_INT_ACK_SET_T0_PACKET_IN_IB_ACK(cp_int_ack_reg, t0_packet_in_ib_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK) | (t0_packet_in_ib_ack << CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT) +#define CP_INT_ACK_SET_OPCODE_ERROR_ACK(cp_int_ack_reg, opcode_error_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_OPCODE_ERROR_ACK_MASK) | (opcode_error_ack << CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT) +#define CP_INT_ACK_SET_PROTECTED_MODE_ERROR_ACK(cp_int_ack_reg, protected_mode_error_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK) | (protected_mode_error_ack << CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT) +#define CP_INT_ACK_SET_RESERVED_BIT_ERROR_ACK(cp_int_ack_reg, reserved_bit_error_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK) | (reserved_bit_error_ack << CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT) +#define CP_INT_ACK_SET_IB_ERROR_ACK(cp_int_ack_reg, ib_error_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB_ERROR_ACK_MASK) | (ib_error_ack << CP_INT_ACK_IB_ERROR_ACK_SHIFT) +#define CP_INT_ACK_SET_IB2_INT_ACK(cp_int_ack_reg, ib2_int_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB2_INT_ACK_MASK) | (ib2_int_ack << CP_INT_ACK_IB2_INT_ACK_SHIFT) +#define CP_INT_ACK_SET_IB1_INT_ACK(cp_int_ack_reg, ib1_int_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB1_INT_ACK_MASK) | (ib1_int_ack << CP_INT_ACK_IB1_INT_ACK_SHIFT) +#define CP_INT_ACK_SET_RB_INT_ACK(cp_int_ack_reg, rb_int_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_RB_INT_ACK_MASK) | (rb_int_ack << CP_INT_ACK_RB_INT_ACK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_int_ack_t { + unsigned int : 19; + unsigned int sw_int_ack : CP_INT_ACK_SW_INT_ACK_SIZE; + unsigned int : 3; + unsigned int t0_packet_in_ib_ack : CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE; + unsigned int opcode_error_ack : CP_INT_ACK_OPCODE_ERROR_ACK_SIZE; + unsigned int protected_mode_error_ack : CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE; + unsigned int reserved_bit_error_ack : CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE; + unsigned int ib_error_ack : CP_INT_ACK_IB_ERROR_ACK_SIZE; + unsigned int : 1; + unsigned int ib2_int_ack : CP_INT_ACK_IB2_INT_ACK_SIZE; + unsigned int ib1_int_ack : CP_INT_ACK_IB1_INT_ACK_SIZE; + unsigned int rb_int_ack : CP_INT_ACK_RB_INT_ACK_SIZE; + } cp_int_ack_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_int_ack_t { + unsigned int rb_int_ack : CP_INT_ACK_RB_INT_ACK_SIZE; + unsigned int ib1_int_ack : CP_INT_ACK_IB1_INT_ACK_SIZE; + unsigned int ib2_int_ack : CP_INT_ACK_IB2_INT_ACK_SIZE; + unsigned int : 1; + unsigned int ib_error_ack : CP_INT_ACK_IB_ERROR_ACK_SIZE; + unsigned int reserved_bit_error_ack : CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE; + unsigned int protected_mode_error_ack : CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE; + unsigned int opcode_error_ack : CP_INT_ACK_OPCODE_ERROR_ACK_SIZE; + unsigned int t0_packet_in_ib_ack : CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE; + unsigned int : 3; + unsigned int sw_int_ack : CP_INT_ACK_SW_INT_ACK_SIZE; + unsigned int : 19; + } cp_int_ack_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_int_ack_t f; +} cp_int_ack_u; + + +/* + * CP_PFP_UCODE_ADDR struct + */ + +#define CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE 9 + +#define CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT 0 + +#define CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK 0x000001ff + +#define CP_PFP_UCODE_ADDR_MASK \ + (CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) + +#define CP_PFP_UCODE_ADDR(ucode_addr) \ + ((ucode_addr << CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT)) + +#define CP_PFP_UCODE_ADDR_GET_UCODE_ADDR(cp_pfp_ucode_addr) \ + ((cp_pfp_ucode_addr & CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) >> CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT) + +#define CP_PFP_UCODE_ADDR_SET_UCODE_ADDR(cp_pfp_ucode_addr_reg, ucode_addr) \ + cp_pfp_ucode_addr_reg = (cp_pfp_ucode_addr_reg & ~CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) | (ucode_addr << CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_pfp_ucode_addr_t { + unsigned int ucode_addr : CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE; + unsigned int : 23; + } cp_pfp_ucode_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_pfp_ucode_addr_t { + unsigned int : 23; + unsigned int ucode_addr : CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE; + } cp_pfp_ucode_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_pfp_ucode_addr_t f; +} cp_pfp_ucode_addr_u; + + +/* + * CP_PFP_UCODE_DATA struct + */ + +#define CP_PFP_UCODE_DATA_UCODE_DATA_SIZE 24 + +#define CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT 0 + +#define CP_PFP_UCODE_DATA_UCODE_DATA_MASK 0x00ffffff + +#define CP_PFP_UCODE_DATA_MASK \ + (CP_PFP_UCODE_DATA_UCODE_DATA_MASK) + +#define CP_PFP_UCODE_DATA(ucode_data) \ + ((ucode_data << CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT)) + +#define CP_PFP_UCODE_DATA_GET_UCODE_DATA(cp_pfp_ucode_data) \ + ((cp_pfp_ucode_data & CP_PFP_UCODE_DATA_UCODE_DATA_MASK) >> CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT) + +#define CP_PFP_UCODE_DATA_SET_UCODE_DATA(cp_pfp_ucode_data_reg, ucode_data) \ + cp_pfp_ucode_data_reg = (cp_pfp_ucode_data_reg & ~CP_PFP_UCODE_DATA_UCODE_DATA_MASK) | (ucode_data << CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_pfp_ucode_data_t { + unsigned int ucode_data : CP_PFP_UCODE_DATA_UCODE_DATA_SIZE; + unsigned int : 8; + } cp_pfp_ucode_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_pfp_ucode_data_t { + unsigned int : 8; + unsigned int ucode_data : CP_PFP_UCODE_DATA_UCODE_DATA_SIZE; + } cp_pfp_ucode_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_pfp_ucode_data_t f; +} cp_pfp_ucode_data_u; + + +/* + * CP_PERFMON_CNTL struct + */ + +#define CP_PERFMON_CNTL_PERFMON_STATE_SIZE 4 +#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE 2 + +#define CP_PERFMON_CNTL_PERFMON_STATE_SHIFT 0 +#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT 8 + +#define CP_PERFMON_CNTL_PERFMON_STATE_MASK 0x0000000f +#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK 0x00000300 + +#define CP_PERFMON_CNTL_MASK \ + (CP_PERFMON_CNTL_PERFMON_STATE_MASK | \ + CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) + +#define CP_PERFMON_CNTL(perfmon_state, perfmon_enable_mode) \ + ((perfmon_state << CP_PERFMON_CNTL_PERFMON_STATE_SHIFT) | \ + (perfmon_enable_mode << CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT)) + +#define CP_PERFMON_CNTL_GET_PERFMON_STATE(cp_perfmon_cntl) \ + ((cp_perfmon_cntl & CP_PERFMON_CNTL_PERFMON_STATE_MASK) >> CP_PERFMON_CNTL_PERFMON_STATE_SHIFT) +#define CP_PERFMON_CNTL_GET_PERFMON_ENABLE_MODE(cp_perfmon_cntl) \ + ((cp_perfmon_cntl & CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) >> CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT) + +#define CP_PERFMON_CNTL_SET_PERFMON_STATE(cp_perfmon_cntl_reg, perfmon_state) \ + cp_perfmon_cntl_reg = (cp_perfmon_cntl_reg & ~CP_PERFMON_CNTL_PERFMON_STATE_MASK) | (perfmon_state << CP_PERFMON_CNTL_PERFMON_STATE_SHIFT) +#define CP_PERFMON_CNTL_SET_PERFMON_ENABLE_MODE(cp_perfmon_cntl_reg, perfmon_enable_mode) \ + cp_perfmon_cntl_reg = (cp_perfmon_cntl_reg & ~CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) | (perfmon_enable_mode << CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_perfmon_cntl_t { + unsigned int perfmon_state : CP_PERFMON_CNTL_PERFMON_STATE_SIZE; + unsigned int : 4; + unsigned int perfmon_enable_mode : CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE; + unsigned int : 22; + } cp_perfmon_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_perfmon_cntl_t { + unsigned int : 22; + unsigned int perfmon_enable_mode : CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE; + unsigned int : 4; + unsigned int perfmon_state : CP_PERFMON_CNTL_PERFMON_STATE_SIZE; + } cp_perfmon_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_perfmon_cntl_t f; +} cp_perfmon_cntl_u; + + +/* + * CP_PERFCOUNTER_SELECT struct + */ + +#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE 6 + +#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT 0 + +#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK 0x0000003f + +#define CP_PERFCOUNTER_SELECT_MASK \ + (CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) + +#define CP_PERFCOUNTER_SELECT(perfcount_sel) \ + ((perfcount_sel << CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT)) + +#define CP_PERFCOUNTER_SELECT_GET_PERFCOUNT_SEL(cp_perfcounter_select) \ + ((cp_perfcounter_select & CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) >> CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT) + +#define CP_PERFCOUNTER_SELECT_SET_PERFCOUNT_SEL(cp_perfcounter_select_reg, perfcount_sel) \ + cp_perfcounter_select_reg = (cp_perfcounter_select_reg & ~CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) | (perfcount_sel << CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_perfcounter_select_t { + unsigned int perfcount_sel : CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE; + unsigned int : 26; + } cp_perfcounter_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_perfcounter_select_t { + unsigned int : 26; + unsigned int perfcount_sel : CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE; + } cp_perfcounter_select_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_perfcounter_select_t f; +} cp_perfcounter_select_u; + + +/* + * CP_PERFCOUNTER_LO struct + */ + +#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE 32 + +#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT 0 + +#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK 0xffffffff + +#define CP_PERFCOUNTER_LO_MASK \ + (CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) + +#define CP_PERFCOUNTER_LO(perfcount_lo) \ + ((perfcount_lo << CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT)) + +#define CP_PERFCOUNTER_LO_GET_PERFCOUNT_LO(cp_perfcounter_lo) \ + ((cp_perfcounter_lo & CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) >> CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT) + +#define CP_PERFCOUNTER_LO_SET_PERFCOUNT_LO(cp_perfcounter_lo_reg, perfcount_lo) \ + cp_perfcounter_lo_reg = (cp_perfcounter_lo_reg & ~CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) | (perfcount_lo << CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_perfcounter_lo_t { + unsigned int perfcount_lo : CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE; + } cp_perfcounter_lo_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_perfcounter_lo_t { + unsigned int perfcount_lo : CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE; + } cp_perfcounter_lo_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_perfcounter_lo_t f; +} cp_perfcounter_lo_u; + + +/* + * CP_PERFCOUNTER_HI struct + */ + +#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE 16 + +#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT 0 + +#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK 0x0000ffff + +#define CP_PERFCOUNTER_HI_MASK \ + (CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) + +#define CP_PERFCOUNTER_HI(perfcount_hi) \ + ((perfcount_hi << CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT)) + +#define CP_PERFCOUNTER_HI_GET_PERFCOUNT_HI(cp_perfcounter_hi) \ + ((cp_perfcounter_hi & CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) >> CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT) + +#define CP_PERFCOUNTER_HI_SET_PERFCOUNT_HI(cp_perfcounter_hi_reg, perfcount_hi) \ + cp_perfcounter_hi_reg = (cp_perfcounter_hi_reg & ~CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) | (perfcount_hi << CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_perfcounter_hi_t { + unsigned int perfcount_hi : CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE; + unsigned int : 16; + } cp_perfcounter_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_perfcounter_hi_t { + unsigned int : 16; + unsigned int perfcount_hi : CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE; + } cp_perfcounter_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_perfcounter_hi_t f; +} cp_perfcounter_hi_u; + + +/* + * CP_BIN_MASK_LO struct + */ + +#define CP_BIN_MASK_LO_BIN_MASK_LO_SIZE 32 + +#define CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT 0 + +#define CP_BIN_MASK_LO_BIN_MASK_LO_MASK 0xffffffff + +#define CP_BIN_MASK_LO_MASK \ + (CP_BIN_MASK_LO_BIN_MASK_LO_MASK) + +#define CP_BIN_MASK_LO(bin_mask_lo) \ + ((bin_mask_lo << CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT)) + +#define CP_BIN_MASK_LO_GET_BIN_MASK_LO(cp_bin_mask_lo) \ + ((cp_bin_mask_lo & CP_BIN_MASK_LO_BIN_MASK_LO_MASK) >> CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT) + +#define CP_BIN_MASK_LO_SET_BIN_MASK_LO(cp_bin_mask_lo_reg, bin_mask_lo) \ + cp_bin_mask_lo_reg = (cp_bin_mask_lo_reg & ~CP_BIN_MASK_LO_BIN_MASK_LO_MASK) | (bin_mask_lo << CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_bin_mask_lo_t { + unsigned int bin_mask_lo : CP_BIN_MASK_LO_BIN_MASK_LO_SIZE; + } cp_bin_mask_lo_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_bin_mask_lo_t { + unsigned int bin_mask_lo : CP_BIN_MASK_LO_BIN_MASK_LO_SIZE; + } cp_bin_mask_lo_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_bin_mask_lo_t f; +} cp_bin_mask_lo_u; + + +/* + * CP_BIN_MASK_HI struct + */ + +#define CP_BIN_MASK_HI_BIN_MASK_HI_SIZE 32 + +#define CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT 0 + +#define CP_BIN_MASK_HI_BIN_MASK_HI_MASK 0xffffffff + +#define CP_BIN_MASK_HI_MASK \ + (CP_BIN_MASK_HI_BIN_MASK_HI_MASK) + +#define CP_BIN_MASK_HI(bin_mask_hi) \ + ((bin_mask_hi << CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT)) + +#define CP_BIN_MASK_HI_GET_BIN_MASK_HI(cp_bin_mask_hi) \ + ((cp_bin_mask_hi & CP_BIN_MASK_HI_BIN_MASK_HI_MASK) >> CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT) + +#define CP_BIN_MASK_HI_SET_BIN_MASK_HI(cp_bin_mask_hi_reg, bin_mask_hi) \ + cp_bin_mask_hi_reg = (cp_bin_mask_hi_reg & ~CP_BIN_MASK_HI_BIN_MASK_HI_MASK) | (bin_mask_hi << CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_bin_mask_hi_t { + unsigned int bin_mask_hi : CP_BIN_MASK_HI_BIN_MASK_HI_SIZE; + } cp_bin_mask_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_bin_mask_hi_t { + unsigned int bin_mask_hi : CP_BIN_MASK_HI_BIN_MASK_HI_SIZE; + } cp_bin_mask_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_bin_mask_hi_t f; +} cp_bin_mask_hi_u; + + +/* + * CP_BIN_SELECT_LO struct + */ + +#define CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE 32 + +#define CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT 0 + +#define CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK 0xffffffff + +#define CP_BIN_SELECT_LO_MASK \ + (CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) + +#define CP_BIN_SELECT_LO(bin_select_lo) \ + ((bin_select_lo << CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT)) + +#define CP_BIN_SELECT_LO_GET_BIN_SELECT_LO(cp_bin_select_lo) \ + ((cp_bin_select_lo & CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) >> CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT) + +#define CP_BIN_SELECT_LO_SET_BIN_SELECT_LO(cp_bin_select_lo_reg, bin_select_lo) \ + cp_bin_select_lo_reg = (cp_bin_select_lo_reg & ~CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) | (bin_select_lo << CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_bin_select_lo_t { + unsigned int bin_select_lo : CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE; + } cp_bin_select_lo_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_bin_select_lo_t { + unsigned int bin_select_lo : CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE; + } cp_bin_select_lo_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_bin_select_lo_t f; +} cp_bin_select_lo_u; + + +/* + * CP_BIN_SELECT_HI struct + */ + +#define CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE 32 + +#define CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT 0 + +#define CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK 0xffffffff + +#define CP_BIN_SELECT_HI_MASK \ + (CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) + +#define CP_BIN_SELECT_HI(bin_select_hi) \ + ((bin_select_hi << CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT)) + +#define CP_BIN_SELECT_HI_GET_BIN_SELECT_HI(cp_bin_select_hi) \ + ((cp_bin_select_hi & CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) >> CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT) + +#define CP_BIN_SELECT_HI_SET_BIN_SELECT_HI(cp_bin_select_hi_reg, bin_select_hi) \ + cp_bin_select_hi_reg = (cp_bin_select_hi_reg & ~CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) | (bin_select_hi << CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_bin_select_hi_t { + unsigned int bin_select_hi : CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE; + } cp_bin_select_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_bin_select_hi_t { + unsigned int bin_select_hi : CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE; + } cp_bin_select_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_bin_select_hi_t f; +} cp_bin_select_hi_u; + + +/* + * CP_NV_FLAGS_0 struct + */ + +#define CP_NV_FLAGS_0_DISCARD_0_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_0_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_1_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_1_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_2_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_2_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_3_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_3_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_4_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_4_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_5_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_5_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_6_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_6_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_7_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_7_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_8_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_8_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_9_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_9_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_10_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_10_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_11_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_11_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_12_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_12_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_13_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_13_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_14_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_14_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_15_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_15_SIZE 1 + +#define CP_NV_FLAGS_0_DISCARD_0_SHIFT 0 +#define CP_NV_FLAGS_0_END_RCVD_0_SHIFT 1 +#define CP_NV_FLAGS_0_DISCARD_1_SHIFT 2 +#define CP_NV_FLAGS_0_END_RCVD_1_SHIFT 3 +#define CP_NV_FLAGS_0_DISCARD_2_SHIFT 4 +#define CP_NV_FLAGS_0_END_RCVD_2_SHIFT 5 +#define CP_NV_FLAGS_0_DISCARD_3_SHIFT 6 +#define CP_NV_FLAGS_0_END_RCVD_3_SHIFT 7 +#define CP_NV_FLAGS_0_DISCARD_4_SHIFT 8 +#define CP_NV_FLAGS_0_END_RCVD_4_SHIFT 9 +#define CP_NV_FLAGS_0_DISCARD_5_SHIFT 10 +#define CP_NV_FLAGS_0_END_RCVD_5_SHIFT 11 +#define CP_NV_FLAGS_0_DISCARD_6_SHIFT 12 +#define CP_NV_FLAGS_0_END_RCVD_6_SHIFT 13 +#define CP_NV_FLAGS_0_DISCARD_7_SHIFT 14 +#define CP_NV_FLAGS_0_END_RCVD_7_SHIFT 15 +#define CP_NV_FLAGS_0_DISCARD_8_SHIFT 16 +#define CP_NV_FLAGS_0_END_RCVD_8_SHIFT 17 +#define CP_NV_FLAGS_0_DISCARD_9_SHIFT 18 +#define CP_NV_FLAGS_0_END_RCVD_9_SHIFT 19 +#define CP_NV_FLAGS_0_DISCARD_10_SHIFT 20 +#define CP_NV_FLAGS_0_END_RCVD_10_SHIFT 21 +#define CP_NV_FLAGS_0_DISCARD_11_SHIFT 22 +#define CP_NV_FLAGS_0_END_RCVD_11_SHIFT 23 +#define CP_NV_FLAGS_0_DISCARD_12_SHIFT 24 +#define CP_NV_FLAGS_0_END_RCVD_12_SHIFT 25 +#define CP_NV_FLAGS_0_DISCARD_13_SHIFT 26 +#define CP_NV_FLAGS_0_END_RCVD_13_SHIFT 27 +#define CP_NV_FLAGS_0_DISCARD_14_SHIFT 28 +#define CP_NV_FLAGS_0_END_RCVD_14_SHIFT 29 +#define CP_NV_FLAGS_0_DISCARD_15_SHIFT 30 +#define CP_NV_FLAGS_0_END_RCVD_15_SHIFT 31 + +#define CP_NV_FLAGS_0_DISCARD_0_MASK 0x00000001 +#define CP_NV_FLAGS_0_END_RCVD_0_MASK 0x00000002 +#define CP_NV_FLAGS_0_DISCARD_1_MASK 0x00000004 +#define CP_NV_FLAGS_0_END_RCVD_1_MASK 0x00000008 +#define CP_NV_FLAGS_0_DISCARD_2_MASK 0x00000010 +#define CP_NV_FLAGS_0_END_RCVD_2_MASK 0x00000020 +#define CP_NV_FLAGS_0_DISCARD_3_MASK 0x00000040 +#define CP_NV_FLAGS_0_END_RCVD_3_MASK 0x00000080 +#define CP_NV_FLAGS_0_DISCARD_4_MASK 0x00000100 +#define CP_NV_FLAGS_0_END_RCVD_4_MASK 0x00000200 +#define CP_NV_FLAGS_0_DISCARD_5_MASK 0x00000400 +#define CP_NV_FLAGS_0_END_RCVD_5_MASK 0x00000800 +#define CP_NV_FLAGS_0_DISCARD_6_MASK 0x00001000 +#define CP_NV_FLAGS_0_END_RCVD_6_MASK 0x00002000 +#define CP_NV_FLAGS_0_DISCARD_7_MASK 0x00004000 +#define CP_NV_FLAGS_0_END_RCVD_7_MASK 0x00008000 +#define CP_NV_FLAGS_0_DISCARD_8_MASK 0x00010000 +#define CP_NV_FLAGS_0_END_RCVD_8_MASK 0x00020000 +#define CP_NV_FLAGS_0_DISCARD_9_MASK 0x00040000 +#define CP_NV_FLAGS_0_END_RCVD_9_MASK 0x00080000 +#define CP_NV_FLAGS_0_DISCARD_10_MASK 0x00100000 +#define CP_NV_FLAGS_0_END_RCVD_10_MASK 0x00200000 +#define CP_NV_FLAGS_0_DISCARD_11_MASK 0x00400000 +#define CP_NV_FLAGS_0_END_RCVD_11_MASK 0x00800000 +#define CP_NV_FLAGS_0_DISCARD_12_MASK 0x01000000 +#define CP_NV_FLAGS_0_END_RCVD_12_MASK 0x02000000 +#define CP_NV_FLAGS_0_DISCARD_13_MASK 0x04000000 +#define CP_NV_FLAGS_0_END_RCVD_13_MASK 0x08000000 +#define CP_NV_FLAGS_0_DISCARD_14_MASK 0x10000000 +#define CP_NV_FLAGS_0_END_RCVD_14_MASK 0x20000000 +#define CP_NV_FLAGS_0_DISCARD_15_MASK 0x40000000 +#define CP_NV_FLAGS_0_END_RCVD_15_MASK 0x80000000 + +#define CP_NV_FLAGS_0_MASK \ + (CP_NV_FLAGS_0_DISCARD_0_MASK | \ + CP_NV_FLAGS_0_END_RCVD_0_MASK | \ + CP_NV_FLAGS_0_DISCARD_1_MASK | \ + CP_NV_FLAGS_0_END_RCVD_1_MASK | \ + CP_NV_FLAGS_0_DISCARD_2_MASK | \ + CP_NV_FLAGS_0_END_RCVD_2_MASK | \ + CP_NV_FLAGS_0_DISCARD_3_MASK | \ + CP_NV_FLAGS_0_END_RCVD_3_MASK | \ + CP_NV_FLAGS_0_DISCARD_4_MASK | \ + CP_NV_FLAGS_0_END_RCVD_4_MASK | \ + CP_NV_FLAGS_0_DISCARD_5_MASK | \ + CP_NV_FLAGS_0_END_RCVD_5_MASK | \ + CP_NV_FLAGS_0_DISCARD_6_MASK | \ + CP_NV_FLAGS_0_END_RCVD_6_MASK | \ + CP_NV_FLAGS_0_DISCARD_7_MASK | \ + CP_NV_FLAGS_0_END_RCVD_7_MASK | \ + CP_NV_FLAGS_0_DISCARD_8_MASK | \ + CP_NV_FLAGS_0_END_RCVD_8_MASK | \ + CP_NV_FLAGS_0_DISCARD_9_MASK | \ + CP_NV_FLAGS_0_END_RCVD_9_MASK | \ + CP_NV_FLAGS_0_DISCARD_10_MASK | \ + CP_NV_FLAGS_0_END_RCVD_10_MASK | \ + CP_NV_FLAGS_0_DISCARD_11_MASK | \ + CP_NV_FLAGS_0_END_RCVD_11_MASK | \ + CP_NV_FLAGS_0_DISCARD_12_MASK | \ + CP_NV_FLAGS_0_END_RCVD_12_MASK | \ + CP_NV_FLAGS_0_DISCARD_13_MASK | \ + CP_NV_FLAGS_0_END_RCVD_13_MASK | \ + CP_NV_FLAGS_0_DISCARD_14_MASK | \ + CP_NV_FLAGS_0_END_RCVD_14_MASK | \ + CP_NV_FLAGS_0_DISCARD_15_MASK | \ + CP_NV_FLAGS_0_END_RCVD_15_MASK) + +#define CP_NV_FLAGS_0(discard_0, end_rcvd_0, discard_1, end_rcvd_1, discard_2, end_rcvd_2, discard_3, end_rcvd_3, discard_4, end_rcvd_4, discard_5, end_rcvd_5, discard_6, end_rcvd_6, discard_7, end_rcvd_7, discard_8, end_rcvd_8, discard_9, end_rcvd_9, discard_10, end_rcvd_10, discard_11, end_rcvd_11, discard_12, end_rcvd_12, discard_13, end_rcvd_13, discard_14, end_rcvd_14, discard_15, end_rcvd_15) \ + ((discard_0 << CP_NV_FLAGS_0_DISCARD_0_SHIFT) | \ + (end_rcvd_0 << CP_NV_FLAGS_0_END_RCVD_0_SHIFT) | \ + (discard_1 << CP_NV_FLAGS_0_DISCARD_1_SHIFT) | \ + (end_rcvd_1 << CP_NV_FLAGS_0_END_RCVD_1_SHIFT) | \ + (discard_2 << CP_NV_FLAGS_0_DISCARD_2_SHIFT) | \ + (end_rcvd_2 << CP_NV_FLAGS_0_END_RCVD_2_SHIFT) | \ + (discard_3 << CP_NV_FLAGS_0_DISCARD_3_SHIFT) | \ + (end_rcvd_3 << CP_NV_FLAGS_0_END_RCVD_3_SHIFT) | \ + (discard_4 << CP_NV_FLAGS_0_DISCARD_4_SHIFT) | \ + (end_rcvd_4 << CP_NV_FLAGS_0_END_RCVD_4_SHIFT) | \ + (discard_5 << CP_NV_FLAGS_0_DISCARD_5_SHIFT) | \ + (end_rcvd_5 << CP_NV_FLAGS_0_END_RCVD_5_SHIFT) | \ + (discard_6 << CP_NV_FLAGS_0_DISCARD_6_SHIFT) | \ + (end_rcvd_6 << CP_NV_FLAGS_0_END_RCVD_6_SHIFT) | \ + (discard_7 << CP_NV_FLAGS_0_DISCARD_7_SHIFT) | \ + (end_rcvd_7 << CP_NV_FLAGS_0_END_RCVD_7_SHIFT) | \ + (discard_8 << CP_NV_FLAGS_0_DISCARD_8_SHIFT) | \ + (end_rcvd_8 << CP_NV_FLAGS_0_END_RCVD_8_SHIFT) | \ + (discard_9 << CP_NV_FLAGS_0_DISCARD_9_SHIFT) | \ + (end_rcvd_9 << CP_NV_FLAGS_0_END_RCVD_9_SHIFT) | \ + (discard_10 << CP_NV_FLAGS_0_DISCARD_10_SHIFT) | \ + (end_rcvd_10 << CP_NV_FLAGS_0_END_RCVD_10_SHIFT) | \ + (discard_11 << CP_NV_FLAGS_0_DISCARD_11_SHIFT) | \ + (end_rcvd_11 << CP_NV_FLAGS_0_END_RCVD_11_SHIFT) | \ + (discard_12 << CP_NV_FLAGS_0_DISCARD_12_SHIFT) | \ + (end_rcvd_12 << CP_NV_FLAGS_0_END_RCVD_12_SHIFT) | \ + (discard_13 << CP_NV_FLAGS_0_DISCARD_13_SHIFT) | \ + (end_rcvd_13 << CP_NV_FLAGS_0_END_RCVD_13_SHIFT) | \ + (discard_14 << CP_NV_FLAGS_0_DISCARD_14_SHIFT) | \ + (end_rcvd_14 << CP_NV_FLAGS_0_END_RCVD_14_SHIFT) | \ + (discard_15 << CP_NV_FLAGS_0_DISCARD_15_SHIFT) | \ + (end_rcvd_15 << CP_NV_FLAGS_0_END_RCVD_15_SHIFT)) + +#define CP_NV_FLAGS_0_GET_DISCARD_0(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_0_MASK) >> CP_NV_FLAGS_0_DISCARD_0_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_0(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_0_MASK) >> CP_NV_FLAGS_0_END_RCVD_0_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_1(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_1_MASK) >> CP_NV_FLAGS_0_DISCARD_1_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_1(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_1_MASK) >> CP_NV_FLAGS_0_END_RCVD_1_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_2(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_2_MASK) >> CP_NV_FLAGS_0_DISCARD_2_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_2(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_2_MASK) >> CP_NV_FLAGS_0_END_RCVD_2_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_3(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_3_MASK) >> CP_NV_FLAGS_0_DISCARD_3_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_3(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_3_MASK) >> CP_NV_FLAGS_0_END_RCVD_3_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_4(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_4_MASK) >> CP_NV_FLAGS_0_DISCARD_4_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_4(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_4_MASK) >> CP_NV_FLAGS_0_END_RCVD_4_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_5(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_5_MASK) >> CP_NV_FLAGS_0_DISCARD_5_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_5(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_5_MASK) >> CP_NV_FLAGS_0_END_RCVD_5_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_6(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_6_MASK) >> CP_NV_FLAGS_0_DISCARD_6_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_6(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_6_MASK) >> CP_NV_FLAGS_0_END_RCVD_6_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_7(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_7_MASK) >> CP_NV_FLAGS_0_DISCARD_7_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_7(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_7_MASK) >> CP_NV_FLAGS_0_END_RCVD_7_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_8(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_8_MASK) >> CP_NV_FLAGS_0_DISCARD_8_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_8(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_8_MASK) >> CP_NV_FLAGS_0_END_RCVD_8_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_9(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_9_MASK) >> CP_NV_FLAGS_0_DISCARD_9_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_9(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_9_MASK) >> CP_NV_FLAGS_0_END_RCVD_9_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_10(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_10_MASK) >> CP_NV_FLAGS_0_DISCARD_10_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_10(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_10_MASK) >> CP_NV_FLAGS_0_END_RCVD_10_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_11(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_11_MASK) >> CP_NV_FLAGS_0_DISCARD_11_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_11(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_11_MASK) >> CP_NV_FLAGS_0_END_RCVD_11_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_12(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_12_MASK) >> CP_NV_FLAGS_0_DISCARD_12_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_12(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_12_MASK) >> CP_NV_FLAGS_0_END_RCVD_12_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_13(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_13_MASK) >> CP_NV_FLAGS_0_DISCARD_13_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_13(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_13_MASK) >> CP_NV_FLAGS_0_END_RCVD_13_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_14(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_14_MASK) >> CP_NV_FLAGS_0_DISCARD_14_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_14(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_14_MASK) >> CP_NV_FLAGS_0_END_RCVD_14_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_15(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_15_MASK) >> CP_NV_FLAGS_0_DISCARD_15_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_15(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_15_MASK) >> CP_NV_FLAGS_0_END_RCVD_15_SHIFT) + +#define CP_NV_FLAGS_0_SET_DISCARD_0(cp_nv_flags_0_reg, discard_0) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_0_MASK) | (discard_0 << CP_NV_FLAGS_0_DISCARD_0_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_0(cp_nv_flags_0_reg, end_rcvd_0) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_0_MASK) | (end_rcvd_0 << CP_NV_FLAGS_0_END_RCVD_0_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_1(cp_nv_flags_0_reg, discard_1) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_1_MASK) | (discard_1 << CP_NV_FLAGS_0_DISCARD_1_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_1(cp_nv_flags_0_reg, end_rcvd_1) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_1_MASK) | (end_rcvd_1 << CP_NV_FLAGS_0_END_RCVD_1_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_2(cp_nv_flags_0_reg, discard_2) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_2_MASK) | (discard_2 << CP_NV_FLAGS_0_DISCARD_2_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_2(cp_nv_flags_0_reg, end_rcvd_2) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_2_MASK) | (end_rcvd_2 << CP_NV_FLAGS_0_END_RCVD_2_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_3(cp_nv_flags_0_reg, discard_3) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_3_MASK) | (discard_3 << CP_NV_FLAGS_0_DISCARD_3_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_3(cp_nv_flags_0_reg, end_rcvd_3) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_3_MASK) | (end_rcvd_3 << CP_NV_FLAGS_0_END_RCVD_3_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_4(cp_nv_flags_0_reg, discard_4) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_4_MASK) | (discard_4 << CP_NV_FLAGS_0_DISCARD_4_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_4(cp_nv_flags_0_reg, end_rcvd_4) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_4_MASK) | (end_rcvd_4 << CP_NV_FLAGS_0_END_RCVD_4_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_5(cp_nv_flags_0_reg, discard_5) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_5_MASK) | (discard_5 << CP_NV_FLAGS_0_DISCARD_5_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_5(cp_nv_flags_0_reg, end_rcvd_5) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_5_MASK) | (end_rcvd_5 << CP_NV_FLAGS_0_END_RCVD_5_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_6(cp_nv_flags_0_reg, discard_6) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_6_MASK) | (discard_6 << CP_NV_FLAGS_0_DISCARD_6_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_6(cp_nv_flags_0_reg, end_rcvd_6) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_6_MASK) | (end_rcvd_6 << CP_NV_FLAGS_0_END_RCVD_6_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_7(cp_nv_flags_0_reg, discard_7) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_7_MASK) | (discard_7 << CP_NV_FLAGS_0_DISCARD_7_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_7(cp_nv_flags_0_reg, end_rcvd_7) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_7_MASK) | (end_rcvd_7 << CP_NV_FLAGS_0_END_RCVD_7_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_8(cp_nv_flags_0_reg, discard_8) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_8_MASK) | (discard_8 << CP_NV_FLAGS_0_DISCARD_8_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_8(cp_nv_flags_0_reg, end_rcvd_8) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_8_MASK) | (end_rcvd_8 << CP_NV_FLAGS_0_END_RCVD_8_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_9(cp_nv_flags_0_reg, discard_9) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_9_MASK) | (discard_9 << CP_NV_FLAGS_0_DISCARD_9_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_9(cp_nv_flags_0_reg, end_rcvd_9) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_9_MASK) | (end_rcvd_9 << CP_NV_FLAGS_0_END_RCVD_9_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_10(cp_nv_flags_0_reg, discard_10) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_10_MASK) | (discard_10 << CP_NV_FLAGS_0_DISCARD_10_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_10(cp_nv_flags_0_reg, end_rcvd_10) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_10_MASK) | (end_rcvd_10 << CP_NV_FLAGS_0_END_RCVD_10_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_11(cp_nv_flags_0_reg, discard_11) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_11_MASK) | (discard_11 << CP_NV_FLAGS_0_DISCARD_11_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_11(cp_nv_flags_0_reg, end_rcvd_11) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_11_MASK) | (end_rcvd_11 << CP_NV_FLAGS_0_END_RCVD_11_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_12(cp_nv_flags_0_reg, discard_12) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_12_MASK) | (discard_12 << CP_NV_FLAGS_0_DISCARD_12_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_12(cp_nv_flags_0_reg, end_rcvd_12) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_12_MASK) | (end_rcvd_12 << CP_NV_FLAGS_0_END_RCVD_12_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_13(cp_nv_flags_0_reg, discard_13) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_13_MASK) | (discard_13 << CP_NV_FLAGS_0_DISCARD_13_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_13(cp_nv_flags_0_reg, end_rcvd_13) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_13_MASK) | (end_rcvd_13 << CP_NV_FLAGS_0_END_RCVD_13_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_14(cp_nv_flags_0_reg, discard_14) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_14_MASK) | (discard_14 << CP_NV_FLAGS_0_DISCARD_14_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_14(cp_nv_flags_0_reg, end_rcvd_14) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_14_MASK) | (end_rcvd_14 << CP_NV_FLAGS_0_END_RCVD_14_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_15(cp_nv_flags_0_reg, discard_15) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_15_MASK) | (discard_15 << CP_NV_FLAGS_0_DISCARD_15_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_15(cp_nv_flags_0_reg, end_rcvd_15) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_15_MASK) | (end_rcvd_15 << CP_NV_FLAGS_0_END_RCVD_15_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_nv_flags_0_t { + unsigned int discard_0 : CP_NV_FLAGS_0_DISCARD_0_SIZE; + unsigned int end_rcvd_0 : CP_NV_FLAGS_0_END_RCVD_0_SIZE; + unsigned int discard_1 : CP_NV_FLAGS_0_DISCARD_1_SIZE; + unsigned int end_rcvd_1 : CP_NV_FLAGS_0_END_RCVD_1_SIZE; + unsigned int discard_2 : CP_NV_FLAGS_0_DISCARD_2_SIZE; + unsigned int end_rcvd_2 : CP_NV_FLAGS_0_END_RCVD_2_SIZE; + unsigned int discard_3 : CP_NV_FLAGS_0_DISCARD_3_SIZE; + unsigned int end_rcvd_3 : CP_NV_FLAGS_0_END_RCVD_3_SIZE; + unsigned int discard_4 : CP_NV_FLAGS_0_DISCARD_4_SIZE; + unsigned int end_rcvd_4 : CP_NV_FLAGS_0_END_RCVD_4_SIZE; + unsigned int discard_5 : CP_NV_FLAGS_0_DISCARD_5_SIZE; + unsigned int end_rcvd_5 : CP_NV_FLAGS_0_END_RCVD_5_SIZE; + unsigned int discard_6 : CP_NV_FLAGS_0_DISCARD_6_SIZE; + unsigned int end_rcvd_6 : CP_NV_FLAGS_0_END_RCVD_6_SIZE; + unsigned int discard_7 : CP_NV_FLAGS_0_DISCARD_7_SIZE; + unsigned int end_rcvd_7 : CP_NV_FLAGS_0_END_RCVD_7_SIZE; + unsigned int discard_8 : CP_NV_FLAGS_0_DISCARD_8_SIZE; + unsigned int end_rcvd_8 : CP_NV_FLAGS_0_END_RCVD_8_SIZE; + unsigned int discard_9 : CP_NV_FLAGS_0_DISCARD_9_SIZE; + unsigned int end_rcvd_9 : CP_NV_FLAGS_0_END_RCVD_9_SIZE; + unsigned int discard_10 : CP_NV_FLAGS_0_DISCARD_10_SIZE; + unsigned int end_rcvd_10 : CP_NV_FLAGS_0_END_RCVD_10_SIZE; + unsigned int discard_11 : CP_NV_FLAGS_0_DISCARD_11_SIZE; + unsigned int end_rcvd_11 : CP_NV_FLAGS_0_END_RCVD_11_SIZE; + unsigned int discard_12 : CP_NV_FLAGS_0_DISCARD_12_SIZE; + unsigned int end_rcvd_12 : CP_NV_FLAGS_0_END_RCVD_12_SIZE; + unsigned int discard_13 : CP_NV_FLAGS_0_DISCARD_13_SIZE; + unsigned int end_rcvd_13 : CP_NV_FLAGS_0_END_RCVD_13_SIZE; + unsigned int discard_14 : CP_NV_FLAGS_0_DISCARD_14_SIZE; + unsigned int end_rcvd_14 : CP_NV_FLAGS_0_END_RCVD_14_SIZE; + unsigned int discard_15 : CP_NV_FLAGS_0_DISCARD_15_SIZE; + unsigned int end_rcvd_15 : CP_NV_FLAGS_0_END_RCVD_15_SIZE; + } cp_nv_flags_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_nv_flags_0_t { + unsigned int end_rcvd_15 : CP_NV_FLAGS_0_END_RCVD_15_SIZE; + unsigned int discard_15 : CP_NV_FLAGS_0_DISCARD_15_SIZE; + unsigned int end_rcvd_14 : CP_NV_FLAGS_0_END_RCVD_14_SIZE; + unsigned int discard_14 : CP_NV_FLAGS_0_DISCARD_14_SIZE; + unsigned int end_rcvd_13 : CP_NV_FLAGS_0_END_RCVD_13_SIZE; + unsigned int discard_13 : CP_NV_FLAGS_0_DISCARD_13_SIZE; + unsigned int end_rcvd_12 : CP_NV_FLAGS_0_END_RCVD_12_SIZE; + unsigned int discard_12 : CP_NV_FLAGS_0_DISCARD_12_SIZE; + unsigned int end_rcvd_11 : CP_NV_FLAGS_0_END_RCVD_11_SIZE; + unsigned int discard_11 : CP_NV_FLAGS_0_DISCARD_11_SIZE; + unsigned int end_rcvd_10 : CP_NV_FLAGS_0_END_RCVD_10_SIZE; + unsigned int discard_10 : CP_NV_FLAGS_0_DISCARD_10_SIZE; + unsigned int end_rcvd_9 : CP_NV_FLAGS_0_END_RCVD_9_SIZE; + unsigned int discard_9 : CP_NV_FLAGS_0_DISCARD_9_SIZE; + unsigned int end_rcvd_8 : CP_NV_FLAGS_0_END_RCVD_8_SIZE; + unsigned int discard_8 : CP_NV_FLAGS_0_DISCARD_8_SIZE; + unsigned int end_rcvd_7 : CP_NV_FLAGS_0_END_RCVD_7_SIZE; + unsigned int discard_7 : CP_NV_FLAGS_0_DISCARD_7_SIZE; + unsigned int end_rcvd_6 : CP_NV_FLAGS_0_END_RCVD_6_SIZE; + unsigned int discard_6 : CP_NV_FLAGS_0_DISCARD_6_SIZE; + unsigned int end_rcvd_5 : CP_NV_FLAGS_0_END_RCVD_5_SIZE; + unsigned int discard_5 : CP_NV_FLAGS_0_DISCARD_5_SIZE; + unsigned int end_rcvd_4 : CP_NV_FLAGS_0_END_RCVD_4_SIZE; + unsigned int discard_4 : CP_NV_FLAGS_0_DISCARD_4_SIZE; + unsigned int end_rcvd_3 : CP_NV_FLAGS_0_END_RCVD_3_SIZE; + unsigned int discard_3 : CP_NV_FLAGS_0_DISCARD_3_SIZE; + unsigned int end_rcvd_2 : CP_NV_FLAGS_0_END_RCVD_2_SIZE; + unsigned int discard_2 : CP_NV_FLAGS_0_DISCARD_2_SIZE; + unsigned int end_rcvd_1 : CP_NV_FLAGS_0_END_RCVD_1_SIZE; + unsigned int discard_1 : CP_NV_FLAGS_0_DISCARD_1_SIZE; + unsigned int end_rcvd_0 : CP_NV_FLAGS_0_END_RCVD_0_SIZE; + unsigned int discard_0 : CP_NV_FLAGS_0_DISCARD_0_SIZE; + } cp_nv_flags_0_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_nv_flags_0_t f; +} cp_nv_flags_0_u; + + +/* + * CP_NV_FLAGS_1 struct + */ + +#define CP_NV_FLAGS_1_DISCARD_16_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_16_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_17_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_17_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_18_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_18_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_19_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_19_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_20_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_20_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_21_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_21_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_22_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_22_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_23_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_23_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_24_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_24_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_25_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_25_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_26_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_26_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_27_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_27_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_28_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_28_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_29_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_29_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_30_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_30_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_31_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_31_SIZE 1 + +#define CP_NV_FLAGS_1_DISCARD_16_SHIFT 0 +#define CP_NV_FLAGS_1_END_RCVD_16_SHIFT 1 +#define CP_NV_FLAGS_1_DISCARD_17_SHIFT 2 +#define CP_NV_FLAGS_1_END_RCVD_17_SHIFT 3 +#define CP_NV_FLAGS_1_DISCARD_18_SHIFT 4 +#define CP_NV_FLAGS_1_END_RCVD_18_SHIFT 5 +#define CP_NV_FLAGS_1_DISCARD_19_SHIFT 6 +#define CP_NV_FLAGS_1_END_RCVD_19_SHIFT 7 +#define CP_NV_FLAGS_1_DISCARD_20_SHIFT 8 +#define CP_NV_FLAGS_1_END_RCVD_20_SHIFT 9 +#define CP_NV_FLAGS_1_DISCARD_21_SHIFT 10 +#define CP_NV_FLAGS_1_END_RCVD_21_SHIFT 11 +#define CP_NV_FLAGS_1_DISCARD_22_SHIFT 12 +#define CP_NV_FLAGS_1_END_RCVD_22_SHIFT 13 +#define CP_NV_FLAGS_1_DISCARD_23_SHIFT 14 +#define CP_NV_FLAGS_1_END_RCVD_23_SHIFT 15 +#define CP_NV_FLAGS_1_DISCARD_24_SHIFT 16 +#define CP_NV_FLAGS_1_END_RCVD_24_SHIFT 17 +#define CP_NV_FLAGS_1_DISCARD_25_SHIFT 18 +#define CP_NV_FLAGS_1_END_RCVD_25_SHIFT 19 +#define CP_NV_FLAGS_1_DISCARD_26_SHIFT 20 +#define CP_NV_FLAGS_1_END_RCVD_26_SHIFT 21 +#define CP_NV_FLAGS_1_DISCARD_27_SHIFT 22 +#define CP_NV_FLAGS_1_END_RCVD_27_SHIFT 23 +#define CP_NV_FLAGS_1_DISCARD_28_SHIFT 24 +#define CP_NV_FLAGS_1_END_RCVD_28_SHIFT 25 +#define CP_NV_FLAGS_1_DISCARD_29_SHIFT 26 +#define CP_NV_FLAGS_1_END_RCVD_29_SHIFT 27 +#define CP_NV_FLAGS_1_DISCARD_30_SHIFT 28 +#define CP_NV_FLAGS_1_END_RCVD_30_SHIFT 29 +#define CP_NV_FLAGS_1_DISCARD_31_SHIFT 30 +#define CP_NV_FLAGS_1_END_RCVD_31_SHIFT 31 + +#define CP_NV_FLAGS_1_DISCARD_16_MASK 0x00000001 +#define CP_NV_FLAGS_1_END_RCVD_16_MASK 0x00000002 +#define CP_NV_FLAGS_1_DISCARD_17_MASK 0x00000004 +#define CP_NV_FLAGS_1_END_RCVD_17_MASK 0x00000008 +#define CP_NV_FLAGS_1_DISCARD_18_MASK 0x00000010 +#define CP_NV_FLAGS_1_END_RCVD_18_MASK 0x00000020 +#define CP_NV_FLAGS_1_DISCARD_19_MASK 0x00000040 +#define CP_NV_FLAGS_1_END_RCVD_19_MASK 0x00000080 +#define CP_NV_FLAGS_1_DISCARD_20_MASK 0x00000100 +#define CP_NV_FLAGS_1_END_RCVD_20_MASK 0x00000200 +#define CP_NV_FLAGS_1_DISCARD_21_MASK 0x00000400 +#define CP_NV_FLAGS_1_END_RCVD_21_MASK 0x00000800 +#define CP_NV_FLAGS_1_DISCARD_22_MASK 0x00001000 +#define CP_NV_FLAGS_1_END_RCVD_22_MASK 0x00002000 +#define CP_NV_FLAGS_1_DISCARD_23_MASK 0x00004000 +#define CP_NV_FLAGS_1_END_RCVD_23_MASK 0x00008000 +#define CP_NV_FLAGS_1_DISCARD_24_MASK 0x00010000 +#define CP_NV_FLAGS_1_END_RCVD_24_MASK 0x00020000 +#define CP_NV_FLAGS_1_DISCARD_25_MASK 0x00040000 +#define CP_NV_FLAGS_1_END_RCVD_25_MASK 0x00080000 +#define CP_NV_FLAGS_1_DISCARD_26_MASK 0x00100000 +#define CP_NV_FLAGS_1_END_RCVD_26_MASK 0x00200000 +#define CP_NV_FLAGS_1_DISCARD_27_MASK 0x00400000 +#define CP_NV_FLAGS_1_END_RCVD_27_MASK 0x00800000 +#define CP_NV_FLAGS_1_DISCARD_28_MASK 0x01000000 +#define CP_NV_FLAGS_1_END_RCVD_28_MASK 0x02000000 +#define CP_NV_FLAGS_1_DISCARD_29_MASK 0x04000000 +#define CP_NV_FLAGS_1_END_RCVD_29_MASK 0x08000000 +#define CP_NV_FLAGS_1_DISCARD_30_MASK 0x10000000 +#define CP_NV_FLAGS_1_END_RCVD_30_MASK 0x20000000 +#define CP_NV_FLAGS_1_DISCARD_31_MASK 0x40000000 +#define CP_NV_FLAGS_1_END_RCVD_31_MASK 0x80000000 + +#define CP_NV_FLAGS_1_MASK \ + (CP_NV_FLAGS_1_DISCARD_16_MASK | \ + CP_NV_FLAGS_1_END_RCVD_16_MASK | \ + CP_NV_FLAGS_1_DISCARD_17_MASK | \ + CP_NV_FLAGS_1_END_RCVD_17_MASK | \ + CP_NV_FLAGS_1_DISCARD_18_MASK | \ + CP_NV_FLAGS_1_END_RCVD_18_MASK | \ + CP_NV_FLAGS_1_DISCARD_19_MASK | \ + CP_NV_FLAGS_1_END_RCVD_19_MASK | \ + CP_NV_FLAGS_1_DISCARD_20_MASK | \ + CP_NV_FLAGS_1_END_RCVD_20_MASK | \ + CP_NV_FLAGS_1_DISCARD_21_MASK | \ + CP_NV_FLAGS_1_END_RCVD_21_MASK | \ + CP_NV_FLAGS_1_DISCARD_22_MASK | \ + CP_NV_FLAGS_1_END_RCVD_22_MASK | \ + CP_NV_FLAGS_1_DISCARD_23_MASK | \ + CP_NV_FLAGS_1_END_RCVD_23_MASK | \ + CP_NV_FLAGS_1_DISCARD_24_MASK | \ + CP_NV_FLAGS_1_END_RCVD_24_MASK | \ + CP_NV_FLAGS_1_DISCARD_25_MASK | \ + CP_NV_FLAGS_1_END_RCVD_25_MASK | \ + CP_NV_FLAGS_1_DISCARD_26_MASK | \ + CP_NV_FLAGS_1_END_RCVD_26_MASK | \ + CP_NV_FLAGS_1_DISCARD_27_MASK | \ + CP_NV_FLAGS_1_END_RCVD_27_MASK | \ + CP_NV_FLAGS_1_DISCARD_28_MASK | \ + CP_NV_FLAGS_1_END_RCVD_28_MASK | \ + CP_NV_FLAGS_1_DISCARD_29_MASK | \ + CP_NV_FLAGS_1_END_RCVD_29_MASK | \ + CP_NV_FLAGS_1_DISCARD_30_MASK | \ + CP_NV_FLAGS_1_END_RCVD_30_MASK | \ + CP_NV_FLAGS_1_DISCARD_31_MASK | \ + CP_NV_FLAGS_1_END_RCVD_31_MASK) + +#define CP_NV_FLAGS_1(discard_16, end_rcvd_16, discard_17, end_rcvd_17, discard_18, end_rcvd_18, discard_19, end_rcvd_19, discard_20, end_rcvd_20, discard_21, end_rcvd_21, discard_22, end_rcvd_22, discard_23, end_rcvd_23, discard_24, end_rcvd_24, discard_25, end_rcvd_25, discard_26, end_rcvd_26, discard_27, end_rcvd_27, discard_28, end_rcvd_28, discard_29, end_rcvd_29, discard_30, end_rcvd_30, discard_31, end_rcvd_31) \ + ((discard_16 << CP_NV_FLAGS_1_DISCARD_16_SHIFT) | \ + (end_rcvd_16 << CP_NV_FLAGS_1_END_RCVD_16_SHIFT) | \ + (discard_17 << CP_NV_FLAGS_1_DISCARD_17_SHIFT) | \ + (end_rcvd_17 << CP_NV_FLAGS_1_END_RCVD_17_SHIFT) | \ + (discard_18 << CP_NV_FLAGS_1_DISCARD_18_SHIFT) | \ + (end_rcvd_18 << CP_NV_FLAGS_1_END_RCVD_18_SHIFT) | \ + (discard_19 << CP_NV_FLAGS_1_DISCARD_19_SHIFT) | \ + (end_rcvd_19 << CP_NV_FLAGS_1_END_RCVD_19_SHIFT) | \ + (discard_20 << CP_NV_FLAGS_1_DISCARD_20_SHIFT) | \ + (end_rcvd_20 << CP_NV_FLAGS_1_END_RCVD_20_SHIFT) | \ + (discard_21 << CP_NV_FLAGS_1_DISCARD_21_SHIFT) | \ + (end_rcvd_21 << CP_NV_FLAGS_1_END_RCVD_21_SHIFT) | \ + (discard_22 << CP_NV_FLAGS_1_DISCARD_22_SHIFT) | \ + (end_rcvd_22 << CP_NV_FLAGS_1_END_RCVD_22_SHIFT) | \ + (discard_23 << CP_NV_FLAGS_1_DISCARD_23_SHIFT) | \ + (end_rcvd_23 << CP_NV_FLAGS_1_END_RCVD_23_SHIFT) | \ + (discard_24 << CP_NV_FLAGS_1_DISCARD_24_SHIFT) | \ + (end_rcvd_24 << CP_NV_FLAGS_1_END_RCVD_24_SHIFT) | \ + (discard_25 << CP_NV_FLAGS_1_DISCARD_25_SHIFT) | \ + (end_rcvd_25 << CP_NV_FLAGS_1_END_RCVD_25_SHIFT) | \ + (discard_26 << CP_NV_FLAGS_1_DISCARD_26_SHIFT) | \ + (end_rcvd_26 << CP_NV_FLAGS_1_END_RCVD_26_SHIFT) | \ + (discard_27 << CP_NV_FLAGS_1_DISCARD_27_SHIFT) | \ + (end_rcvd_27 << CP_NV_FLAGS_1_END_RCVD_27_SHIFT) | \ + (discard_28 << CP_NV_FLAGS_1_DISCARD_28_SHIFT) | \ + (end_rcvd_28 << CP_NV_FLAGS_1_END_RCVD_28_SHIFT) | \ + (discard_29 << CP_NV_FLAGS_1_DISCARD_29_SHIFT) | \ + (end_rcvd_29 << CP_NV_FLAGS_1_END_RCVD_29_SHIFT) | \ + (discard_30 << CP_NV_FLAGS_1_DISCARD_30_SHIFT) | \ + (end_rcvd_30 << CP_NV_FLAGS_1_END_RCVD_30_SHIFT) | \ + (discard_31 << CP_NV_FLAGS_1_DISCARD_31_SHIFT) | \ + (end_rcvd_31 << CP_NV_FLAGS_1_END_RCVD_31_SHIFT)) + +#define CP_NV_FLAGS_1_GET_DISCARD_16(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_16_MASK) >> CP_NV_FLAGS_1_DISCARD_16_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_16(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_16_MASK) >> CP_NV_FLAGS_1_END_RCVD_16_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_17(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_17_MASK) >> CP_NV_FLAGS_1_DISCARD_17_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_17(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_17_MASK) >> CP_NV_FLAGS_1_END_RCVD_17_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_18(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_18_MASK) >> CP_NV_FLAGS_1_DISCARD_18_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_18(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_18_MASK) >> CP_NV_FLAGS_1_END_RCVD_18_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_19(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_19_MASK) >> CP_NV_FLAGS_1_DISCARD_19_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_19(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_19_MASK) >> CP_NV_FLAGS_1_END_RCVD_19_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_20(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_20_MASK) >> CP_NV_FLAGS_1_DISCARD_20_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_20(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_20_MASK) >> CP_NV_FLAGS_1_END_RCVD_20_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_21(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_21_MASK) >> CP_NV_FLAGS_1_DISCARD_21_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_21(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_21_MASK) >> CP_NV_FLAGS_1_END_RCVD_21_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_22(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_22_MASK) >> CP_NV_FLAGS_1_DISCARD_22_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_22(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_22_MASK) >> CP_NV_FLAGS_1_END_RCVD_22_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_23(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_23_MASK) >> CP_NV_FLAGS_1_DISCARD_23_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_23(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_23_MASK) >> CP_NV_FLAGS_1_END_RCVD_23_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_24(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_24_MASK) >> CP_NV_FLAGS_1_DISCARD_24_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_24(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_24_MASK) >> CP_NV_FLAGS_1_END_RCVD_24_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_25(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_25_MASK) >> CP_NV_FLAGS_1_DISCARD_25_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_25(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_25_MASK) >> CP_NV_FLAGS_1_END_RCVD_25_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_26(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_26_MASK) >> CP_NV_FLAGS_1_DISCARD_26_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_26(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_26_MASK) >> CP_NV_FLAGS_1_END_RCVD_26_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_27(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_27_MASK) >> CP_NV_FLAGS_1_DISCARD_27_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_27(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_27_MASK) >> CP_NV_FLAGS_1_END_RCVD_27_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_28(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_28_MASK) >> CP_NV_FLAGS_1_DISCARD_28_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_28(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_28_MASK) >> CP_NV_FLAGS_1_END_RCVD_28_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_29(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_29_MASK) >> CP_NV_FLAGS_1_DISCARD_29_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_29(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_29_MASK) >> CP_NV_FLAGS_1_END_RCVD_29_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_30(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_30_MASK) >> CP_NV_FLAGS_1_DISCARD_30_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_30(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_30_MASK) >> CP_NV_FLAGS_1_END_RCVD_30_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_31(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_31_MASK) >> CP_NV_FLAGS_1_DISCARD_31_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_31(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_31_MASK) >> CP_NV_FLAGS_1_END_RCVD_31_SHIFT) + +#define CP_NV_FLAGS_1_SET_DISCARD_16(cp_nv_flags_1_reg, discard_16) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_16_MASK) | (discard_16 << CP_NV_FLAGS_1_DISCARD_16_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_16(cp_nv_flags_1_reg, end_rcvd_16) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_16_MASK) | (end_rcvd_16 << CP_NV_FLAGS_1_END_RCVD_16_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_17(cp_nv_flags_1_reg, discard_17) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_17_MASK) | (discard_17 << CP_NV_FLAGS_1_DISCARD_17_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_17(cp_nv_flags_1_reg, end_rcvd_17) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_17_MASK) | (end_rcvd_17 << CP_NV_FLAGS_1_END_RCVD_17_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_18(cp_nv_flags_1_reg, discard_18) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_18_MASK) | (discard_18 << CP_NV_FLAGS_1_DISCARD_18_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_18(cp_nv_flags_1_reg, end_rcvd_18) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_18_MASK) | (end_rcvd_18 << CP_NV_FLAGS_1_END_RCVD_18_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_19(cp_nv_flags_1_reg, discard_19) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_19_MASK) | (discard_19 << CP_NV_FLAGS_1_DISCARD_19_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_19(cp_nv_flags_1_reg, end_rcvd_19) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_19_MASK) | (end_rcvd_19 << CP_NV_FLAGS_1_END_RCVD_19_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_20(cp_nv_flags_1_reg, discard_20) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_20_MASK) | (discard_20 << CP_NV_FLAGS_1_DISCARD_20_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_20(cp_nv_flags_1_reg, end_rcvd_20) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_20_MASK) | (end_rcvd_20 << CP_NV_FLAGS_1_END_RCVD_20_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_21(cp_nv_flags_1_reg, discard_21) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_21_MASK) | (discard_21 << CP_NV_FLAGS_1_DISCARD_21_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_21(cp_nv_flags_1_reg, end_rcvd_21) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_21_MASK) | (end_rcvd_21 << CP_NV_FLAGS_1_END_RCVD_21_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_22(cp_nv_flags_1_reg, discard_22) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_22_MASK) | (discard_22 << CP_NV_FLAGS_1_DISCARD_22_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_22(cp_nv_flags_1_reg, end_rcvd_22) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_22_MASK) | (end_rcvd_22 << CP_NV_FLAGS_1_END_RCVD_22_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_23(cp_nv_flags_1_reg, discard_23) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_23_MASK) | (discard_23 << CP_NV_FLAGS_1_DISCARD_23_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_23(cp_nv_flags_1_reg, end_rcvd_23) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_23_MASK) | (end_rcvd_23 << CP_NV_FLAGS_1_END_RCVD_23_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_24(cp_nv_flags_1_reg, discard_24) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_24_MASK) | (discard_24 << CP_NV_FLAGS_1_DISCARD_24_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_24(cp_nv_flags_1_reg, end_rcvd_24) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_24_MASK) | (end_rcvd_24 << CP_NV_FLAGS_1_END_RCVD_24_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_25(cp_nv_flags_1_reg, discard_25) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_25_MASK) | (discard_25 << CP_NV_FLAGS_1_DISCARD_25_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_25(cp_nv_flags_1_reg, end_rcvd_25) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_25_MASK) | (end_rcvd_25 << CP_NV_FLAGS_1_END_RCVD_25_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_26(cp_nv_flags_1_reg, discard_26) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_26_MASK) | (discard_26 << CP_NV_FLAGS_1_DISCARD_26_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_26(cp_nv_flags_1_reg, end_rcvd_26) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_26_MASK) | (end_rcvd_26 << CP_NV_FLAGS_1_END_RCVD_26_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_27(cp_nv_flags_1_reg, discard_27) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_27_MASK) | (discard_27 << CP_NV_FLAGS_1_DISCARD_27_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_27(cp_nv_flags_1_reg, end_rcvd_27) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_27_MASK) | (end_rcvd_27 << CP_NV_FLAGS_1_END_RCVD_27_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_28(cp_nv_flags_1_reg, discard_28) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_28_MASK) | (discard_28 << CP_NV_FLAGS_1_DISCARD_28_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_28(cp_nv_flags_1_reg, end_rcvd_28) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_28_MASK) | (end_rcvd_28 << CP_NV_FLAGS_1_END_RCVD_28_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_29(cp_nv_flags_1_reg, discard_29) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_29_MASK) | (discard_29 << CP_NV_FLAGS_1_DISCARD_29_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_29(cp_nv_flags_1_reg, end_rcvd_29) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_29_MASK) | (end_rcvd_29 << CP_NV_FLAGS_1_END_RCVD_29_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_30(cp_nv_flags_1_reg, discard_30) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_30_MASK) | (discard_30 << CP_NV_FLAGS_1_DISCARD_30_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_30(cp_nv_flags_1_reg, end_rcvd_30) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_30_MASK) | (end_rcvd_30 << CP_NV_FLAGS_1_END_RCVD_30_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_31(cp_nv_flags_1_reg, discard_31) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_31_MASK) | (discard_31 << CP_NV_FLAGS_1_DISCARD_31_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_31(cp_nv_flags_1_reg, end_rcvd_31) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_31_MASK) | (end_rcvd_31 << CP_NV_FLAGS_1_END_RCVD_31_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_nv_flags_1_t { + unsigned int discard_16 : CP_NV_FLAGS_1_DISCARD_16_SIZE; + unsigned int end_rcvd_16 : CP_NV_FLAGS_1_END_RCVD_16_SIZE; + unsigned int discard_17 : CP_NV_FLAGS_1_DISCARD_17_SIZE; + unsigned int end_rcvd_17 : CP_NV_FLAGS_1_END_RCVD_17_SIZE; + unsigned int discard_18 : CP_NV_FLAGS_1_DISCARD_18_SIZE; + unsigned int end_rcvd_18 : CP_NV_FLAGS_1_END_RCVD_18_SIZE; + unsigned int discard_19 : CP_NV_FLAGS_1_DISCARD_19_SIZE; + unsigned int end_rcvd_19 : CP_NV_FLAGS_1_END_RCVD_19_SIZE; + unsigned int discard_20 : CP_NV_FLAGS_1_DISCARD_20_SIZE; + unsigned int end_rcvd_20 : CP_NV_FLAGS_1_END_RCVD_20_SIZE; + unsigned int discard_21 : CP_NV_FLAGS_1_DISCARD_21_SIZE; + unsigned int end_rcvd_21 : CP_NV_FLAGS_1_END_RCVD_21_SIZE; + unsigned int discard_22 : CP_NV_FLAGS_1_DISCARD_22_SIZE; + unsigned int end_rcvd_22 : CP_NV_FLAGS_1_END_RCVD_22_SIZE; + unsigned int discard_23 : CP_NV_FLAGS_1_DISCARD_23_SIZE; + unsigned int end_rcvd_23 : CP_NV_FLAGS_1_END_RCVD_23_SIZE; + unsigned int discard_24 : CP_NV_FLAGS_1_DISCARD_24_SIZE; + unsigned int end_rcvd_24 : CP_NV_FLAGS_1_END_RCVD_24_SIZE; + unsigned int discard_25 : CP_NV_FLAGS_1_DISCARD_25_SIZE; + unsigned int end_rcvd_25 : CP_NV_FLAGS_1_END_RCVD_25_SIZE; + unsigned int discard_26 : CP_NV_FLAGS_1_DISCARD_26_SIZE; + unsigned int end_rcvd_26 : CP_NV_FLAGS_1_END_RCVD_26_SIZE; + unsigned int discard_27 : CP_NV_FLAGS_1_DISCARD_27_SIZE; + unsigned int end_rcvd_27 : CP_NV_FLAGS_1_END_RCVD_27_SIZE; + unsigned int discard_28 : CP_NV_FLAGS_1_DISCARD_28_SIZE; + unsigned int end_rcvd_28 : CP_NV_FLAGS_1_END_RCVD_28_SIZE; + unsigned int discard_29 : CP_NV_FLAGS_1_DISCARD_29_SIZE; + unsigned int end_rcvd_29 : CP_NV_FLAGS_1_END_RCVD_29_SIZE; + unsigned int discard_30 : CP_NV_FLAGS_1_DISCARD_30_SIZE; + unsigned int end_rcvd_30 : CP_NV_FLAGS_1_END_RCVD_30_SIZE; + unsigned int discard_31 : CP_NV_FLAGS_1_DISCARD_31_SIZE; + unsigned int end_rcvd_31 : CP_NV_FLAGS_1_END_RCVD_31_SIZE; + } cp_nv_flags_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_nv_flags_1_t { + unsigned int end_rcvd_31 : CP_NV_FLAGS_1_END_RCVD_31_SIZE; + unsigned int discard_31 : CP_NV_FLAGS_1_DISCARD_31_SIZE; + unsigned int end_rcvd_30 : CP_NV_FLAGS_1_END_RCVD_30_SIZE; + unsigned int discard_30 : CP_NV_FLAGS_1_DISCARD_30_SIZE; + unsigned int end_rcvd_29 : CP_NV_FLAGS_1_END_RCVD_29_SIZE; + unsigned int discard_29 : CP_NV_FLAGS_1_DISCARD_29_SIZE; + unsigned int end_rcvd_28 : CP_NV_FLAGS_1_END_RCVD_28_SIZE; + unsigned int discard_28 : CP_NV_FLAGS_1_DISCARD_28_SIZE; + unsigned int end_rcvd_27 : CP_NV_FLAGS_1_END_RCVD_27_SIZE; + unsigned int discard_27 : CP_NV_FLAGS_1_DISCARD_27_SIZE; + unsigned int end_rcvd_26 : CP_NV_FLAGS_1_END_RCVD_26_SIZE; + unsigned int discard_26 : CP_NV_FLAGS_1_DISCARD_26_SIZE; + unsigned int end_rcvd_25 : CP_NV_FLAGS_1_END_RCVD_25_SIZE; + unsigned int discard_25 : CP_NV_FLAGS_1_DISCARD_25_SIZE; + unsigned int end_rcvd_24 : CP_NV_FLAGS_1_END_RCVD_24_SIZE; + unsigned int discard_24 : CP_NV_FLAGS_1_DISCARD_24_SIZE; + unsigned int end_rcvd_23 : CP_NV_FLAGS_1_END_RCVD_23_SIZE; + unsigned int discard_23 : CP_NV_FLAGS_1_DISCARD_23_SIZE; + unsigned int end_rcvd_22 : CP_NV_FLAGS_1_END_RCVD_22_SIZE; + unsigned int discard_22 : CP_NV_FLAGS_1_DISCARD_22_SIZE; + unsigned int end_rcvd_21 : CP_NV_FLAGS_1_END_RCVD_21_SIZE; + unsigned int discard_21 : CP_NV_FLAGS_1_DISCARD_21_SIZE; + unsigned int end_rcvd_20 : CP_NV_FLAGS_1_END_RCVD_20_SIZE; + unsigned int discard_20 : CP_NV_FLAGS_1_DISCARD_20_SIZE; + unsigned int end_rcvd_19 : CP_NV_FLAGS_1_END_RCVD_19_SIZE; + unsigned int discard_19 : CP_NV_FLAGS_1_DISCARD_19_SIZE; + unsigned int end_rcvd_18 : CP_NV_FLAGS_1_END_RCVD_18_SIZE; + unsigned int discard_18 : CP_NV_FLAGS_1_DISCARD_18_SIZE; + unsigned int end_rcvd_17 : CP_NV_FLAGS_1_END_RCVD_17_SIZE; + unsigned int discard_17 : CP_NV_FLAGS_1_DISCARD_17_SIZE; + unsigned int end_rcvd_16 : CP_NV_FLAGS_1_END_RCVD_16_SIZE; + unsigned int discard_16 : CP_NV_FLAGS_1_DISCARD_16_SIZE; + } cp_nv_flags_1_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_nv_flags_1_t f; +} cp_nv_flags_1_u; + + +/* + * CP_NV_FLAGS_2 struct + */ + +#define CP_NV_FLAGS_2_DISCARD_32_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_32_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_33_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_33_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_34_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_34_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_35_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_35_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_36_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_36_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_37_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_37_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_38_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_38_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_39_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_39_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_40_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_40_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_41_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_41_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_42_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_42_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_43_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_43_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_44_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_44_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_45_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_45_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_46_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_46_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_47_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_47_SIZE 1 + +#define CP_NV_FLAGS_2_DISCARD_32_SHIFT 0 +#define CP_NV_FLAGS_2_END_RCVD_32_SHIFT 1 +#define CP_NV_FLAGS_2_DISCARD_33_SHIFT 2 +#define CP_NV_FLAGS_2_END_RCVD_33_SHIFT 3 +#define CP_NV_FLAGS_2_DISCARD_34_SHIFT 4 +#define CP_NV_FLAGS_2_END_RCVD_34_SHIFT 5 +#define CP_NV_FLAGS_2_DISCARD_35_SHIFT 6 +#define CP_NV_FLAGS_2_END_RCVD_35_SHIFT 7 +#define CP_NV_FLAGS_2_DISCARD_36_SHIFT 8 +#define CP_NV_FLAGS_2_END_RCVD_36_SHIFT 9 +#define CP_NV_FLAGS_2_DISCARD_37_SHIFT 10 +#define CP_NV_FLAGS_2_END_RCVD_37_SHIFT 11 +#define CP_NV_FLAGS_2_DISCARD_38_SHIFT 12 +#define CP_NV_FLAGS_2_END_RCVD_38_SHIFT 13 +#define CP_NV_FLAGS_2_DISCARD_39_SHIFT 14 +#define CP_NV_FLAGS_2_END_RCVD_39_SHIFT 15 +#define CP_NV_FLAGS_2_DISCARD_40_SHIFT 16 +#define CP_NV_FLAGS_2_END_RCVD_40_SHIFT 17 +#define CP_NV_FLAGS_2_DISCARD_41_SHIFT 18 +#define CP_NV_FLAGS_2_END_RCVD_41_SHIFT 19 +#define CP_NV_FLAGS_2_DISCARD_42_SHIFT 20 +#define CP_NV_FLAGS_2_END_RCVD_42_SHIFT 21 +#define CP_NV_FLAGS_2_DISCARD_43_SHIFT 22 +#define CP_NV_FLAGS_2_END_RCVD_43_SHIFT 23 +#define CP_NV_FLAGS_2_DISCARD_44_SHIFT 24 +#define CP_NV_FLAGS_2_END_RCVD_44_SHIFT 25 +#define CP_NV_FLAGS_2_DISCARD_45_SHIFT 26 +#define CP_NV_FLAGS_2_END_RCVD_45_SHIFT 27 +#define CP_NV_FLAGS_2_DISCARD_46_SHIFT 28 +#define CP_NV_FLAGS_2_END_RCVD_46_SHIFT 29 +#define CP_NV_FLAGS_2_DISCARD_47_SHIFT 30 +#define CP_NV_FLAGS_2_END_RCVD_47_SHIFT 31 + +#define CP_NV_FLAGS_2_DISCARD_32_MASK 0x00000001 +#define CP_NV_FLAGS_2_END_RCVD_32_MASK 0x00000002 +#define CP_NV_FLAGS_2_DISCARD_33_MASK 0x00000004 +#define CP_NV_FLAGS_2_END_RCVD_33_MASK 0x00000008 +#define CP_NV_FLAGS_2_DISCARD_34_MASK 0x00000010 +#define CP_NV_FLAGS_2_END_RCVD_34_MASK 0x00000020 +#define CP_NV_FLAGS_2_DISCARD_35_MASK 0x00000040 +#define CP_NV_FLAGS_2_END_RCVD_35_MASK 0x00000080 +#define CP_NV_FLAGS_2_DISCARD_36_MASK 0x00000100 +#define CP_NV_FLAGS_2_END_RCVD_36_MASK 0x00000200 +#define CP_NV_FLAGS_2_DISCARD_37_MASK 0x00000400 +#define CP_NV_FLAGS_2_END_RCVD_37_MASK 0x00000800 +#define CP_NV_FLAGS_2_DISCARD_38_MASK 0x00001000 +#define CP_NV_FLAGS_2_END_RCVD_38_MASK 0x00002000 +#define CP_NV_FLAGS_2_DISCARD_39_MASK 0x00004000 +#define CP_NV_FLAGS_2_END_RCVD_39_MASK 0x00008000 +#define CP_NV_FLAGS_2_DISCARD_40_MASK 0x00010000 +#define CP_NV_FLAGS_2_END_RCVD_40_MASK 0x00020000 +#define CP_NV_FLAGS_2_DISCARD_41_MASK 0x00040000 +#define CP_NV_FLAGS_2_END_RCVD_41_MASK 0x00080000 +#define CP_NV_FLAGS_2_DISCARD_42_MASK 0x00100000 +#define CP_NV_FLAGS_2_END_RCVD_42_MASK 0x00200000 +#define CP_NV_FLAGS_2_DISCARD_43_MASK 0x00400000 +#define CP_NV_FLAGS_2_END_RCVD_43_MASK 0x00800000 +#define CP_NV_FLAGS_2_DISCARD_44_MASK 0x01000000 +#define CP_NV_FLAGS_2_END_RCVD_44_MASK 0x02000000 +#define CP_NV_FLAGS_2_DISCARD_45_MASK 0x04000000 +#define CP_NV_FLAGS_2_END_RCVD_45_MASK 0x08000000 +#define CP_NV_FLAGS_2_DISCARD_46_MASK 0x10000000 +#define CP_NV_FLAGS_2_END_RCVD_46_MASK 0x20000000 +#define CP_NV_FLAGS_2_DISCARD_47_MASK 0x40000000 +#define CP_NV_FLAGS_2_END_RCVD_47_MASK 0x80000000 + +#define CP_NV_FLAGS_2_MASK \ + (CP_NV_FLAGS_2_DISCARD_32_MASK | \ + CP_NV_FLAGS_2_END_RCVD_32_MASK | \ + CP_NV_FLAGS_2_DISCARD_33_MASK | \ + CP_NV_FLAGS_2_END_RCVD_33_MASK | \ + CP_NV_FLAGS_2_DISCARD_34_MASK | \ + CP_NV_FLAGS_2_END_RCVD_34_MASK | \ + CP_NV_FLAGS_2_DISCARD_35_MASK | \ + CP_NV_FLAGS_2_END_RCVD_35_MASK | \ + CP_NV_FLAGS_2_DISCARD_36_MASK | \ + CP_NV_FLAGS_2_END_RCVD_36_MASK | \ + CP_NV_FLAGS_2_DISCARD_37_MASK | \ + CP_NV_FLAGS_2_END_RCVD_37_MASK | \ + CP_NV_FLAGS_2_DISCARD_38_MASK | \ + CP_NV_FLAGS_2_END_RCVD_38_MASK | \ + CP_NV_FLAGS_2_DISCARD_39_MASK | \ + CP_NV_FLAGS_2_END_RCVD_39_MASK | \ + CP_NV_FLAGS_2_DISCARD_40_MASK | \ + CP_NV_FLAGS_2_END_RCVD_40_MASK | \ + CP_NV_FLAGS_2_DISCARD_41_MASK | \ + CP_NV_FLAGS_2_END_RCVD_41_MASK | \ + CP_NV_FLAGS_2_DISCARD_42_MASK | \ + CP_NV_FLAGS_2_END_RCVD_42_MASK | \ + CP_NV_FLAGS_2_DISCARD_43_MASK | \ + CP_NV_FLAGS_2_END_RCVD_43_MASK | \ + CP_NV_FLAGS_2_DISCARD_44_MASK | \ + CP_NV_FLAGS_2_END_RCVD_44_MASK | \ + CP_NV_FLAGS_2_DISCARD_45_MASK | \ + CP_NV_FLAGS_2_END_RCVD_45_MASK | \ + CP_NV_FLAGS_2_DISCARD_46_MASK | \ + CP_NV_FLAGS_2_END_RCVD_46_MASK | \ + CP_NV_FLAGS_2_DISCARD_47_MASK | \ + CP_NV_FLAGS_2_END_RCVD_47_MASK) + +#define CP_NV_FLAGS_2(discard_32, end_rcvd_32, discard_33, end_rcvd_33, discard_34, end_rcvd_34, discard_35, end_rcvd_35, discard_36, end_rcvd_36, discard_37, end_rcvd_37, discard_38, end_rcvd_38, discard_39, end_rcvd_39, discard_40, end_rcvd_40, discard_41, end_rcvd_41, discard_42, end_rcvd_42, discard_43, end_rcvd_43, discard_44, end_rcvd_44, discard_45, end_rcvd_45, discard_46, end_rcvd_46, discard_47, end_rcvd_47) \ + ((discard_32 << CP_NV_FLAGS_2_DISCARD_32_SHIFT) | \ + (end_rcvd_32 << CP_NV_FLAGS_2_END_RCVD_32_SHIFT) | \ + (discard_33 << CP_NV_FLAGS_2_DISCARD_33_SHIFT) | \ + (end_rcvd_33 << CP_NV_FLAGS_2_END_RCVD_33_SHIFT) | \ + (discard_34 << CP_NV_FLAGS_2_DISCARD_34_SHIFT) | \ + (end_rcvd_34 << CP_NV_FLAGS_2_END_RCVD_34_SHIFT) | \ + (discard_35 << CP_NV_FLAGS_2_DISCARD_35_SHIFT) | \ + (end_rcvd_35 << CP_NV_FLAGS_2_END_RCVD_35_SHIFT) | \ + (discard_36 << CP_NV_FLAGS_2_DISCARD_36_SHIFT) | \ + (end_rcvd_36 << CP_NV_FLAGS_2_END_RCVD_36_SHIFT) | \ + (discard_37 << CP_NV_FLAGS_2_DISCARD_37_SHIFT) | \ + (end_rcvd_37 << CP_NV_FLAGS_2_END_RCVD_37_SHIFT) | \ + (discard_38 << CP_NV_FLAGS_2_DISCARD_38_SHIFT) | \ + (end_rcvd_38 << CP_NV_FLAGS_2_END_RCVD_38_SHIFT) | \ + (discard_39 << CP_NV_FLAGS_2_DISCARD_39_SHIFT) | \ + (end_rcvd_39 << CP_NV_FLAGS_2_END_RCVD_39_SHIFT) | \ + (discard_40 << CP_NV_FLAGS_2_DISCARD_40_SHIFT) | \ + (end_rcvd_40 << CP_NV_FLAGS_2_END_RCVD_40_SHIFT) | \ + (discard_41 << CP_NV_FLAGS_2_DISCARD_41_SHIFT) | \ + (end_rcvd_41 << CP_NV_FLAGS_2_END_RCVD_41_SHIFT) | \ + (discard_42 << CP_NV_FLAGS_2_DISCARD_42_SHIFT) | \ + (end_rcvd_42 << CP_NV_FLAGS_2_END_RCVD_42_SHIFT) | \ + (discard_43 << CP_NV_FLAGS_2_DISCARD_43_SHIFT) | \ + (end_rcvd_43 << CP_NV_FLAGS_2_END_RCVD_43_SHIFT) | \ + (discard_44 << CP_NV_FLAGS_2_DISCARD_44_SHIFT) | \ + (end_rcvd_44 << CP_NV_FLAGS_2_END_RCVD_44_SHIFT) | \ + (discard_45 << CP_NV_FLAGS_2_DISCARD_45_SHIFT) | \ + (end_rcvd_45 << CP_NV_FLAGS_2_END_RCVD_45_SHIFT) | \ + (discard_46 << CP_NV_FLAGS_2_DISCARD_46_SHIFT) | \ + (end_rcvd_46 << CP_NV_FLAGS_2_END_RCVD_46_SHIFT) | \ + (discard_47 << CP_NV_FLAGS_2_DISCARD_47_SHIFT) | \ + (end_rcvd_47 << CP_NV_FLAGS_2_END_RCVD_47_SHIFT)) + +#define CP_NV_FLAGS_2_GET_DISCARD_32(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_32_MASK) >> CP_NV_FLAGS_2_DISCARD_32_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_32(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_32_MASK) >> CP_NV_FLAGS_2_END_RCVD_32_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_33(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_33_MASK) >> CP_NV_FLAGS_2_DISCARD_33_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_33(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_33_MASK) >> CP_NV_FLAGS_2_END_RCVD_33_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_34(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_34_MASK) >> CP_NV_FLAGS_2_DISCARD_34_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_34(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_34_MASK) >> CP_NV_FLAGS_2_END_RCVD_34_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_35(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_35_MASK) >> CP_NV_FLAGS_2_DISCARD_35_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_35(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_35_MASK) >> CP_NV_FLAGS_2_END_RCVD_35_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_36(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_36_MASK) >> CP_NV_FLAGS_2_DISCARD_36_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_36(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_36_MASK) >> CP_NV_FLAGS_2_END_RCVD_36_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_37(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_37_MASK) >> CP_NV_FLAGS_2_DISCARD_37_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_37(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_37_MASK) >> CP_NV_FLAGS_2_END_RCVD_37_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_38(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_38_MASK) >> CP_NV_FLAGS_2_DISCARD_38_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_38(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_38_MASK) >> CP_NV_FLAGS_2_END_RCVD_38_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_39(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_39_MASK) >> CP_NV_FLAGS_2_DISCARD_39_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_39(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_39_MASK) >> CP_NV_FLAGS_2_END_RCVD_39_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_40(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_40_MASK) >> CP_NV_FLAGS_2_DISCARD_40_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_40(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_40_MASK) >> CP_NV_FLAGS_2_END_RCVD_40_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_41(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_41_MASK) >> CP_NV_FLAGS_2_DISCARD_41_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_41(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_41_MASK) >> CP_NV_FLAGS_2_END_RCVD_41_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_42(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_42_MASK) >> CP_NV_FLAGS_2_DISCARD_42_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_42(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_42_MASK) >> CP_NV_FLAGS_2_END_RCVD_42_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_43(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_43_MASK) >> CP_NV_FLAGS_2_DISCARD_43_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_43(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_43_MASK) >> CP_NV_FLAGS_2_END_RCVD_43_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_44(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_44_MASK) >> CP_NV_FLAGS_2_DISCARD_44_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_44(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_44_MASK) >> CP_NV_FLAGS_2_END_RCVD_44_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_45(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_45_MASK) >> CP_NV_FLAGS_2_DISCARD_45_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_45(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_45_MASK) >> CP_NV_FLAGS_2_END_RCVD_45_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_46(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_46_MASK) >> CP_NV_FLAGS_2_DISCARD_46_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_46(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_46_MASK) >> CP_NV_FLAGS_2_END_RCVD_46_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_47(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_47_MASK) >> CP_NV_FLAGS_2_DISCARD_47_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_47(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_47_MASK) >> CP_NV_FLAGS_2_END_RCVD_47_SHIFT) + +#define CP_NV_FLAGS_2_SET_DISCARD_32(cp_nv_flags_2_reg, discard_32) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_32_MASK) | (discard_32 << CP_NV_FLAGS_2_DISCARD_32_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_32(cp_nv_flags_2_reg, end_rcvd_32) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_32_MASK) | (end_rcvd_32 << CP_NV_FLAGS_2_END_RCVD_32_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_33(cp_nv_flags_2_reg, discard_33) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_33_MASK) | (discard_33 << CP_NV_FLAGS_2_DISCARD_33_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_33(cp_nv_flags_2_reg, end_rcvd_33) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_33_MASK) | (end_rcvd_33 << CP_NV_FLAGS_2_END_RCVD_33_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_34(cp_nv_flags_2_reg, discard_34) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_34_MASK) | (discard_34 << CP_NV_FLAGS_2_DISCARD_34_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_34(cp_nv_flags_2_reg, end_rcvd_34) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_34_MASK) | (end_rcvd_34 << CP_NV_FLAGS_2_END_RCVD_34_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_35(cp_nv_flags_2_reg, discard_35) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_35_MASK) | (discard_35 << CP_NV_FLAGS_2_DISCARD_35_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_35(cp_nv_flags_2_reg, end_rcvd_35) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_35_MASK) | (end_rcvd_35 << CP_NV_FLAGS_2_END_RCVD_35_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_36(cp_nv_flags_2_reg, discard_36) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_36_MASK) | (discard_36 << CP_NV_FLAGS_2_DISCARD_36_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_36(cp_nv_flags_2_reg, end_rcvd_36) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_36_MASK) | (end_rcvd_36 << CP_NV_FLAGS_2_END_RCVD_36_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_37(cp_nv_flags_2_reg, discard_37) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_37_MASK) | (discard_37 << CP_NV_FLAGS_2_DISCARD_37_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_37(cp_nv_flags_2_reg, end_rcvd_37) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_37_MASK) | (end_rcvd_37 << CP_NV_FLAGS_2_END_RCVD_37_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_38(cp_nv_flags_2_reg, discard_38) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_38_MASK) | (discard_38 << CP_NV_FLAGS_2_DISCARD_38_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_38(cp_nv_flags_2_reg, end_rcvd_38) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_38_MASK) | (end_rcvd_38 << CP_NV_FLAGS_2_END_RCVD_38_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_39(cp_nv_flags_2_reg, discard_39) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_39_MASK) | (discard_39 << CP_NV_FLAGS_2_DISCARD_39_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_39(cp_nv_flags_2_reg, end_rcvd_39) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_39_MASK) | (end_rcvd_39 << CP_NV_FLAGS_2_END_RCVD_39_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_40(cp_nv_flags_2_reg, discard_40) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_40_MASK) | (discard_40 << CP_NV_FLAGS_2_DISCARD_40_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_40(cp_nv_flags_2_reg, end_rcvd_40) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_40_MASK) | (end_rcvd_40 << CP_NV_FLAGS_2_END_RCVD_40_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_41(cp_nv_flags_2_reg, discard_41) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_41_MASK) | (discard_41 << CP_NV_FLAGS_2_DISCARD_41_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_41(cp_nv_flags_2_reg, end_rcvd_41) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_41_MASK) | (end_rcvd_41 << CP_NV_FLAGS_2_END_RCVD_41_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_42(cp_nv_flags_2_reg, discard_42) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_42_MASK) | (discard_42 << CP_NV_FLAGS_2_DISCARD_42_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_42(cp_nv_flags_2_reg, end_rcvd_42) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_42_MASK) | (end_rcvd_42 << CP_NV_FLAGS_2_END_RCVD_42_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_43(cp_nv_flags_2_reg, discard_43) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_43_MASK) | (discard_43 << CP_NV_FLAGS_2_DISCARD_43_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_43(cp_nv_flags_2_reg, end_rcvd_43) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_43_MASK) | (end_rcvd_43 << CP_NV_FLAGS_2_END_RCVD_43_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_44(cp_nv_flags_2_reg, discard_44) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_44_MASK) | (discard_44 << CP_NV_FLAGS_2_DISCARD_44_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_44(cp_nv_flags_2_reg, end_rcvd_44) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_44_MASK) | (end_rcvd_44 << CP_NV_FLAGS_2_END_RCVD_44_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_45(cp_nv_flags_2_reg, discard_45) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_45_MASK) | (discard_45 << CP_NV_FLAGS_2_DISCARD_45_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_45(cp_nv_flags_2_reg, end_rcvd_45) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_45_MASK) | (end_rcvd_45 << CP_NV_FLAGS_2_END_RCVD_45_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_46(cp_nv_flags_2_reg, discard_46) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_46_MASK) | (discard_46 << CP_NV_FLAGS_2_DISCARD_46_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_46(cp_nv_flags_2_reg, end_rcvd_46) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_46_MASK) | (end_rcvd_46 << CP_NV_FLAGS_2_END_RCVD_46_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_47(cp_nv_flags_2_reg, discard_47) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_47_MASK) | (discard_47 << CP_NV_FLAGS_2_DISCARD_47_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_47(cp_nv_flags_2_reg, end_rcvd_47) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_47_MASK) | (end_rcvd_47 << CP_NV_FLAGS_2_END_RCVD_47_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_nv_flags_2_t { + unsigned int discard_32 : CP_NV_FLAGS_2_DISCARD_32_SIZE; + unsigned int end_rcvd_32 : CP_NV_FLAGS_2_END_RCVD_32_SIZE; + unsigned int discard_33 : CP_NV_FLAGS_2_DISCARD_33_SIZE; + unsigned int end_rcvd_33 : CP_NV_FLAGS_2_END_RCVD_33_SIZE; + unsigned int discard_34 : CP_NV_FLAGS_2_DISCARD_34_SIZE; + unsigned int end_rcvd_34 : CP_NV_FLAGS_2_END_RCVD_34_SIZE; + unsigned int discard_35 : CP_NV_FLAGS_2_DISCARD_35_SIZE; + unsigned int end_rcvd_35 : CP_NV_FLAGS_2_END_RCVD_35_SIZE; + unsigned int discard_36 : CP_NV_FLAGS_2_DISCARD_36_SIZE; + unsigned int end_rcvd_36 : CP_NV_FLAGS_2_END_RCVD_36_SIZE; + unsigned int discard_37 : CP_NV_FLAGS_2_DISCARD_37_SIZE; + unsigned int end_rcvd_37 : CP_NV_FLAGS_2_END_RCVD_37_SIZE; + unsigned int discard_38 : CP_NV_FLAGS_2_DISCARD_38_SIZE; + unsigned int end_rcvd_38 : CP_NV_FLAGS_2_END_RCVD_38_SIZE; + unsigned int discard_39 : CP_NV_FLAGS_2_DISCARD_39_SIZE; + unsigned int end_rcvd_39 : CP_NV_FLAGS_2_END_RCVD_39_SIZE; + unsigned int discard_40 : CP_NV_FLAGS_2_DISCARD_40_SIZE; + unsigned int end_rcvd_40 : CP_NV_FLAGS_2_END_RCVD_40_SIZE; + unsigned int discard_41 : CP_NV_FLAGS_2_DISCARD_41_SIZE; + unsigned int end_rcvd_41 : CP_NV_FLAGS_2_END_RCVD_41_SIZE; + unsigned int discard_42 : CP_NV_FLAGS_2_DISCARD_42_SIZE; + unsigned int end_rcvd_42 : CP_NV_FLAGS_2_END_RCVD_42_SIZE; + unsigned int discard_43 : CP_NV_FLAGS_2_DISCARD_43_SIZE; + unsigned int end_rcvd_43 : CP_NV_FLAGS_2_END_RCVD_43_SIZE; + unsigned int discard_44 : CP_NV_FLAGS_2_DISCARD_44_SIZE; + unsigned int end_rcvd_44 : CP_NV_FLAGS_2_END_RCVD_44_SIZE; + unsigned int discard_45 : CP_NV_FLAGS_2_DISCARD_45_SIZE; + unsigned int end_rcvd_45 : CP_NV_FLAGS_2_END_RCVD_45_SIZE; + unsigned int discard_46 : CP_NV_FLAGS_2_DISCARD_46_SIZE; + unsigned int end_rcvd_46 : CP_NV_FLAGS_2_END_RCVD_46_SIZE; + unsigned int discard_47 : CP_NV_FLAGS_2_DISCARD_47_SIZE; + unsigned int end_rcvd_47 : CP_NV_FLAGS_2_END_RCVD_47_SIZE; + } cp_nv_flags_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_nv_flags_2_t { + unsigned int end_rcvd_47 : CP_NV_FLAGS_2_END_RCVD_47_SIZE; + unsigned int discard_47 : CP_NV_FLAGS_2_DISCARD_47_SIZE; + unsigned int end_rcvd_46 : CP_NV_FLAGS_2_END_RCVD_46_SIZE; + unsigned int discard_46 : CP_NV_FLAGS_2_DISCARD_46_SIZE; + unsigned int end_rcvd_45 : CP_NV_FLAGS_2_END_RCVD_45_SIZE; + unsigned int discard_45 : CP_NV_FLAGS_2_DISCARD_45_SIZE; + unsigned int end_rcvd_44 : CP_NV_FLAGS_2_END_RCVD_44_SIZE; + unsigned int discard_44 : CP_NV_FLAGS_2_DISCARD_44_SIZE; + unsigned int end_rcvd_43 : CP_NV_FLAGS_2_END_RCVD_43_SIZE; + unsigned int discard_43 : CP_NV_FLAGS_2_DISCARD_43_SIZE; + unsigned int end_rcvd_42 : CP_NV_FLAGS_2_END_RCVD_42_SIZE; + unsigned int discard_42 : CP_NV_FLAGS_2_DISCARD_42_SIZE; + unsigned int end_rcvd_41 : CP_NV_FLAGS_2_END_RCVD_41_SIZE; + unsigned int discard_41 : CP_NV_FLAGS_2_DISCARD_41_SIZE; + unsigned int end_rcvd_40 : CP_NV_FLAGS_2_END_RCVD_40_SIZE; + unsigned int discard_40 : CP_NV_FLAGS_2_DISCARD_40_SIZE; + unsigned int end_rcvd_39 : CP_NV_FLAGS_2_END_RCVD_39_SIZE; + unsigned int discard_39 : CP_NV_FLAGS_2_DISCARD_39_SIZE; + unsigned int end_rcvd_38 : CP_NV_FLAGS_2_END_RCVD_38_SIZE; + unsigned int discard_38 : CP_NV_FLAGS_2_DISCARD_38_SIZE; + unsigned int end_rcvd_37 : CP_NV_FLAGS_2_END_RCVD_37_SIZE; + unsigned int discard_37 : CP_NV_FLAGS_2_DISCARD_37_SIZE; + unsigned int end_rcvd_36 : CP_NV_FLAGS_2_END_RCVD_36_SIZE; + unsigned int discard_36 : CP_NV_FLAGS_2_DISCARD_36_SIZE; + unsigned int end_rcvd_35 : CP_NV_FLAGS_2_END_RCVD_35_SIZE; + unsigned int discard_35 : CP_NV_FLAGS_2_DISCARD_35_SIZE; + unsigned int end_rcvd_34 : CP_NV_FLAGS_2_END_RCVD_34_SIZE; + unsigned int discard_34 : CP_NV_FLAGS_2_DISCARD_34_SIZE; + unsigned int end_rcvd_33 : CP_NV_FLAGS_2_END_RCVD_33_SIZE; + unsigned int discard_33 : CP_NV_FLAGS_2_DISCARD_33_SIZE; + unsigned int end_rcvd_32 : CP_NV_FLAGS_2_END_RCVD_32_SIZE; + unsigned int discard_32 : CP_NV_FLAGS_2_DISCARD_32_SIZE; + } cp_nv_flags_2_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_nv_flags_2_t f; +} cp_nv_flags_2_u; + + +/* + * CP_NV_FLAGS_3 struct + */ + +#define CP_NV_FLAGS_3_DISCARD_48_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_48_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_49_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_49_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_50_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_50_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_51_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_51_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_52_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_52_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_53_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_53_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_54_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_54_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_55_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_55_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_56_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_56_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_57_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_57_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_58_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_58_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_59_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_59_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_60_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_60_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_61_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_61_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_62_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_62_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_63_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_63_SIZE 1 + +#define CP_NV_FLAGS_3_DISCARD_48_SHIFT 0 +#define CP_NV_FLAGS_3_END_RCVD_48_SHIFT 1 +#define CP_NV_FLAGS_3_DISCARD_49_SHIFT 2 +#define CP_NV_FLAGS_3_END_RCVD_49_SHIFT 3 +#define CP_NV_FLAGS_3_DISCARD_50_SHIFT 4 +#define CP_NV_FLAGS_3_END_RCVD_50_SHIFT 5 +#define CP_NV_FLAGS_3_DISCARD_51_SHIFT 6 +#define CP_NV_FLAGS_3_END_RCVD_51_SHIFT 7 +#define CP_NV_FLAGS_3_DISCARD_52_SHIFT 8 +#define CP_NV_FLAGS_3_END_RCVD_52_SHIFT 9 +#define CP_NV_FLAGS_3_DISCARD_53_SHIFT 10 +#define CP_NV_FLAGS_3_END_RCVD_53_SHIFT 11 +#define CP_NV_FLAGS_3_DISCARD_54_SHIFT 12 +#define CP_NV_FLAGS_3_END_RCVD_54_SHIFT 13 +#define CP_NV_FLAGS_3_DISCARD_55_SHIFT 14 +#define CP_NV_FLAGS_3_END_RCVD_55_SHIFT 15 +#define CP_NV_FLAGS_3_DISCARD_56_SHIFT 16 +#define CP_NV_FLAGS_3_END_RCVD_56_SHIFT 17 +#define CP_NV_FLAGS_3_DISCARD_57_SHIFT 18 +#define CP_NV_FLAGS_3_END_RCVD_57_SHIFT 19 +#define CP_NV_FLAGS_3_DISCARD_58_SHIFT 20 +#define CP_NV_FLAGS_3_END_RCVD_58_SHIFT 21 +#define CP_NV_FLAGS_3_DISCARD_59_SHIFT 22 +#define CP_NV_FLAGS_3_END_RCVD_59_SHIFT 23 +#define CP_NV_FLAGS_3_DISCARD_60_SHIFT 24 +#define CP_NV_FLAGS_3_END_RCVD_60_SHIFT 25 +#define CP_NV_FLAGS_3_DISCARD_61_SHIFT 26 +#define CP_NV_FLAGS_3_END_RCVD_61_SHIFT 27 +#define CP_NV_FLAGS_3_DISCARD_62_SHIFT 28 +#define CP_NV_FLAGS_3_END_RCVD_62_SHIFT 29 +#define CP_NV_FLAGS_3_DISCARD_63_SHIFT 30 +#define CP_NV_FLAGS_3_END_RCVD_63_SHIFT 31 + +#define CP_NV_FLAGS_3_DISCARD_48_MASK 0x00000001 +#define CP_NV_FLAGS_3_END_RCVD_48_MASK 0x00000002 +#define CP_NV_FLAGS_3_DISCARD_49_MASK 0x00000004 +#define CP_NV_FLAGS_3_END_RCVD_49_MASK 0x00000008 +#define CP_NV_FLAGS_3_DISCARD_50_MASK 0x00000010 +#define CP_NV_FLAGS_3_END_RCVD_50_MASK 0x00000020 +#define CP_NV_FLAGS_3_DISCARD_51_MASK 0x00000040 +#define CP_NV_FLAGS_3_END_RCVD_51_MASK 0x00000080 +#define CP_NV_FLAGS_3_DISCARD_52_MASK 0x00000100 +#define CP_NV_FLAGS_3_END_RCVD_52_MASK 0x00000200 +#define CP_NV_FLAGS_3_DISCARD_53_MASK 0x00000400 +#define CP_NV_FLAGS_3_END_RCVD_53_MASK 0x00000800 +#define CP_NV_FLAGS_3_DISCARD_54_MASK 0x00001000 +#define CP_NV_FLAGS_3_END_RCVD_54_MASK 0x00002000 +#define CP_NV_FLAGS_3_DISCARD_55_MASK 0x00004000 +#define CP_NV_FLAGS_3_END_RCVD_55_MASK 0x00008000 +#define CP_NV_FLAGS_3_DISCARD_56_MASK 0x00010000 +#define CP_NV_FLAGS_3_END_RCVD_56_MASK 0x00020000 +#define CP_NV_FLAGS_3_DISCARD_57_MASK 0x00040000 +#define CP_NV_FLAGS_3_END_RCVD_57_MASK 0x00080000 +#define CP_NV_FLAGS_3_DISCARD_58_MASK 0x00100000 +#define CP_NV_FLAGS_3_END_RCVD_58_MASK 0x00200000 +#define CP_NV_FLAGS_3_DISCARD_59_MASK 0x00400000 +#define CP_NV_FLAGS_3_END_RCVD_59_MASK 0x00800000 +#define CP_NV_FLAGS_3_DISCARD_60_MASK 0x01000000 +#define CP_NV_FLAGS_3_END_RCVD_60_MASK 0x02000000 +#define CP_NV_FLAGS_3_DISCARD_61_MASK 0x04000000 +#define CP_NV_FLAGS_3_END_RCVD_61_MASK 0x08000000 +#define CP_NV_FLAGS_3_DISCARD_62_MASK 0x10000000 +#define CP_NV_FLAGS_3_END_RCVD_62_MASK 0x20000000 +#define CP_NV_FLAGS_3_DISCARD_63_MASK 0x40000000 +#define CP_NV_FLAGS_3_END_RCVD_63_MASK 0x80000000 + +#define CP_NV_FLAGS_3_MASK \ + (CP_NV_FLAGS_3_DISCARD_48_MASK | \ + CP_NV_FLAGS_3_END_RCVD_48_MASK | \ + CP_NV_FLAGS_3_DISCARD_49_MASK | \ + CP_NV_FLAGS_3_END_RCVD_49_MASK | \ + CP_NV_FLAGS_3_DISCARD_50_MASK | \ + CP_NV_FLAGS_3_END_RCVD_50_MASK | \ + CP_NV_FLAGS_3_DISCARD_51_MASK | \ + CP_NV_FLAGS_3_END_RCVD_51_MASK | \ + CP_NV_FLAGS_3_DISCARD_52_MASK | \ + CP_NV_FLAGS_3_END_RCVD_52_MASK | \ + CP_NV_FLAGS_3_DISCARD_53_MASK | \ + CP_NV_FLAGS_3_END_RCVD_53_MASK | \ + CP_NV_FLAGS_3_DISCARD_54_MASK | \ + CP_NV_FLAGS_3_END_RCVD_54_MASK | \ + CP_NV_FLAGS_3_DISCARD_55_MASK | \ + CP_NV_FLAGS_3_END_RCVD_55_MASK | \ + CP_NV_FLAGS_3_DISCARD_56_MASK | \ + CP_NV_FLAGS_3_END_RCVD_56_MASK | \ + CP_NV_FLAGS_3_DISCARD_57_MASK | \ + CP_NV_FLAGS_3_END_RCVD_57_MASK | \ + CP_NV_FLAGS_3_DISCARD_58_MASK | \ + CP_NV_FLAGS_3_END_RCVD_58_MASK | \ + CP_NV_FLAGS_3_DISCARD_59_MASK | \ + CP_NV_FLAGS_3_END_RCVD_59_MASK | \ + CP_NV_FLAGS_3_DISCARD_60_MASK | \ + CP_NV_FLAGS_3_END_RCVD_60_MASK | \ + CP_NV_FLAGS_3_DISCARD_61_MASK | \ + CP_NV_FLAGS_3_END_RCVD_61_MASK | \ + CP_NV_FLAGS_3_DISCARD_62_MASK | \ + CP_NV_FLAGS_3_END_RCVD_62_MASK | \ + CP_NV_FLAGS_3_DISCARD_63_MASK | \ + CP_NV_FLAGS_3_END_RCVD_63_MASK) + +#define CP_NV_FLAGS_3(discard_48, end_rcvd_48, discard_49, end_rcvd_49, discard_50, end_rcvd_50, discard_51, end_rcvd_51, discard_52, end_rcvd_52, discard_53, end_rcvd_53, discard_54, end_rcvd_54, discard_55, end_rcvd_55, discard_56, end_rcvd_56, discard_57, end_rcvd_57, discard_58, end_rcvd_58, discard_59, end_rcvd_59, discard_60, end_rcvd_60, discard_61, end_rcvd_61, discard_62, end_rcvd_62, discard_63, end_rcvd_63) \ + ((discard_48 << CP_NV_FLAGS_3_DISCARD_48_SHIFT) | \ + (end_rcvd_48 << CP_NV_FLAGS_3_END_RCVD_48_SHIFT) | \ + (discard_49 << CP_NV_FLAGS_3_DISCARD_49_SHIFT) | \ + (end_rcvd_49 << CP_NV_FLAGS_3_END_RCVD_49_SHIFT) | \ + (discard_50 << CP_NV_FLAGS_3_DISCARD_50_SHIFT) | \ + (end_rcvd_50 << CP_NV_FLAGS_3_END_RCVD_50_SHIFT) | \ + (discard_51 << CP_NV_FLAGS_3_DISCARD_51_SHIFT) | \ + (end_rcvd_51 << CP_NV_FLAGS_3_END_RCVD_51_SHIFT) | \ + (discard_52 << CP_NV_FLAGS_3_DISCARD_52_SHIFT) | \ + (end_rcvd_52 << CP_NV_FLAGS_3_END_RCVD_52_SHIFT) | \ + (discard_53 << CP_NV_FLAGS_3_DISCARD_53_SHIFT) | \ + (end_rcvd_53 << CP_NV_FLAGS_3_END_RCVD_53_SHIFT) | \ + (discard_54 << CP_NV_FLAGS_3_DISCARD_54_SHIFT) | \ + (end_rcvd_54 << CP_NV_FLAGS_3_END_RCVD_54_SHIFT) | \ + (discard_55 << CP_NV_FLAGS_3_DISCARD_55_SHIFT) | \ + (end_rcvd_55 << CP_NV_FLAGS_3_END_RCVD_55_SHIFT) | \ + (discard_56 << CP_NV_FLAGS_3_DISCARD_56_SHIFT) | \ + (end_rcvd_56 << CP_NV_FLAGS_3_END_RCVD_56_SHIFT) | \ + (discard_57 << CP_NV_FLAGS_3_DISCARD_57_SHIFT) | \ + (end_rcvd_57 << CP_NV_FLAGS_3_END_RCVD_57_SHIFT) | \ + (discard_58 << CP_NV_FLAGS_3_DISCARD_58_SHIFT) | \ + (end_rcvd_58 << CP_NV_FLAGS_3_END_RCVD_58_SHIFT) | \ + (discard_59 << CP_NV_FLAGS_3_DISCARD_59_SHIFT) | \ + (end_rcvd_59 << CP_NV_FLAGS_3_END_RCVD_59_SHIFT) | \ + (discard_60 << CP_NV_FLAGS_3_DISCARD_60_SHIFT) | \ + (end_rcvd_60 << CP_NV_FLAGS_3_END_RCVD_60_SHIFT) | \ + (discard_61 << CP_NV_FLAGS_3_DISCARD_61_SHIFT) | \ + (end_rcvd_61 << CP_NV_FLAGS_3_END_RCVD_61_SHIFT) | \ + (discard_62 << CP_NV_FLAGS_3_DISCARD_62_SHIFT) | \ + (end_rcvd_62 << CP_NV_FLAGS_3_END_RCVD_62_SHIFT) | \ + (discard_63 << CP_NV_FLAGS_3_DISCARD_63_SHIFT) | \ + (end_rcvd_63 << CP_NV_FLAGS_3_END_RCVD_63_SHIFT)) + +#define CP_NV_FLAGS_3_GET_DISCARD_48(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_48_MASK) >> CP_NV_FLAGS_3_DISCARD_48_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_48(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_48_MASK) >> CP_NV_FLAGS_3_END_RCVD_48_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_49(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_49_MASK) >> CP_NV_FLAGS_3_DISCARD_49_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_49(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_49_MASK) >> CP_NV_FLAGS_3_END_RCVD_49_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_50(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_50_MASK) >> CP_NV_FLAGS_3_DISCARD_50_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_50(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_50_MASK) >> CP_NV_FLAGS_3_END_RCVD_50_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_51(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_51_MASK) >> CP_NV_FLAGS_3_DISCARD_51_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_51(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_51_MASK) >> CP_NV_FLAGS_3_END_RCVD_51_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_52(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_52_MASK) >> CP_NV_FLAGS_3_DISCARD_52_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_52(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_52_MASK) >> CP_NV_FLAGS_3_END_RCVD_52_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_53(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_53_MASK) >> CP_NV_FLAGS_3_DISCARD_53_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_53(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_53_MASK) >> CP_NV_FLAGS_3_END_RCVD_53_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_54(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_54_MASK) >> CP_NV_FLAGS_3_DISCARD_54_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_54(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_54_MASK) >> CP_NV_FLAGS_3_END_RCVD_54_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_55(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_55_MASK) >> CP_NV_FLAGS_3_DISCARD_55_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_55(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_55_MASK) >> CP_NV_FLAGS_3_END_RCVD_55_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_56(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_56_MASK) >> CP_NV_FLAGS_3_DISCARD_56_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_56(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_56_MASK) >> CP_NV_FLAGS_3_END_RCVD_56_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_57(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_57_MASK) >> CP_NV_FLAGS_3_DISCARD_57_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_57(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_57_MASK) >> CP_NV_FLAGS_3_END_RCVD_57_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_58(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_58_MASK) >> CP_NV_FLAGS_3_DISCARD_58_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_58(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_58_MASK) >> CP_NV_FLAGS_3_END_RCVD_58_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_59(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_59_MASK) >> CP_NV_FLAGS_3_DISCARD_59_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_59(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_59_MASK) >> CP_NV_FLAGS_3_END_RCVD_59_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_60(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_60_MASK) >> CP_NV_FLAGS_3_DISCARD_60_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_60(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_60_MASK) >> CP_NV_FLAGS_3_END_RCVD_60_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_61(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_61_MASK) >> CP_NV_FLAGS_3_DISCARD_61_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_61(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_61_MASK) >> CP_NV_FLAGS_3_END_RCVD_61_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_62(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_62_MASK) >> CP_NV_FLAGS_3_DISCARD_62_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_62(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_62_MASK) >> CP_NV_FLAGS_3_END_RCVD_62_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_63(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_63_MASK) >> CP_NV_FLAGS_3_DISCARD_63_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_63(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_63_MASK) >> CP_NV_FLAGS_3_END_RCVD_63_SHIFT) + +#define CP_NV_FLAGS_3_SET_DISCARD_48(cp_nv_flags_3_reg, discard_48) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_48_MASK) | (discard_48 << CP_NV_FLAGS_3_DISCARD_48_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_48(cp_nv_flags_3_reg, end_rcvd_48) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_48_MASK) | (end_rcvd_48 << CP_NV_FLAGS_3_END_RCVD_48_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_49(cp_nv_flags_3_reg, discard_49) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_49_MASK) | (discard_49 << CP_NV_FLAGS_3_DISCARD_49_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_49(cp_nv_flags_3_reg, end_rcvd_49) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_49_MASK) | (end_rcvd_49 << CP_NV_FLAGS_3_END_RCVD_49_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_50(cp_nv_flags_3_reg, discard_50) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_50_MASK) | (discard_50 << CP_NV_FLAGS_3_DISCARD_50_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_50(cp_nv_flags_3_reg, end_rcvd_50) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_50_MASK) | (end_rcvd_50 << CP_NV_FLAGS_3_END_RCVD_50_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_51(cp_nv_flags_3_reg, discard_51) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_51_MASK) | (discard_51 << CP_NV_FLAGS_3_DISCARD_51_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_51(cp_nv_flags_3_reg, end_rcvd_51) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_51_MASK) | (end_rcvd_51 << CP_NV_FLAGS_3_END_RCVD_51_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_52(cp_nv_flags_3_reg, discard_52) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_52_MASK) | (discard_52 << CP_NV_FLAGS_3_DISCARD_52_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_52(cp_nv_flags_3_reg, end_rcvd_52) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_52_MASK) | (end_rcvd_52 << CP_NV_FLAGS_3_END_RCVD_52_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_53(cp_nv_flags_3_reg, discard_53) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_53_MASK) | (discard_53 << CP_NV_FLAGS_3_DISCARD_53_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_53(cp_nv_flags_3_reg, end_rcvd_53) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_53_MASK) | (end_rcvd_53 << CP_NV_FLAGS_3_END_RCVD_53_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_54(cp_nv_flags_3_reg, discard_54) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_54_MASK) | (discard_54 << CP_NV_FLAGS_3_DISCARD_54_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_54(cp_nv_flags_3_reg, end_rcvd_54) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_54_MASK) | (end_rcvd_54 << CP_NV_FLAGS_3_END_RCVD_54_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_55(cp_nv_flags_3_reg, discard_55) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_55_MASK) | (discard_55 << CP_NV_FLAGS_3_DISCARD_55_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_55(cp_nv_flags_3_reg, end_rcvd_55) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_55_MASK) | (end_rcvd_55 << CP_NV_FLAGS_3_END_RCVD_55_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_56(cp_nv_flags_3_reg, discard_56) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_56_MASK) | (discard_56 << CP_NV_FLAGS_3_DISCARD_56_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_56(cp_nv_flags_3_reg, end_rcvd_56) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_56_MASK) | (end_rcvd_56 << CP_NV_FLAGS_3_END_RCVD_56_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_57(cp_nv_flags_3_reg, discard_57) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_57_MASK) | (discard_57 << CP_NV_FLAGS_3_DISCARD_57_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_57(cp_nv_flags_3_reg, end_rcvd_57) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_57_MASK) | (end_rcvd_57 << CP_NV_FLAGS_3_END_RCVD_57_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_58(cp_nv_flags_3_reg, discard_58) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_58_MASK) | (discard_58 << CP_NV_FLAGS_3_DISCARD_58_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_58(cp_nv_flags_3_reg, end_rcvd_58) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_58_MASK) | (end_rcvd_58 << CP_NV_FLAGS_3_END_RCVD_58_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_59(cp_nv_flags_3_reg, discard_59) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_59_MASK) | (discard_59 << CP_NV_FLAGS_3_DISCARD_59_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_59(cp_nv_flags_3_reg, end_rcvd_59) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_59_MASK) | (end_rcvd_59 << CP_NV_FLAGS_3_END_RCVD_59_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_60(cp_nv_flags_3_reg, discard_60) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_60_MASK) | (discard_60 << CP_NV_FLAGS_3_DISCARD_60_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_60(cp_nv_flags_3_reg, end_rcvd_60) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_60_MASK) | (end_rcvd_60 << CP_NV_FLAGS_3_END_RCVD_60_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_61(cp_nv_flags_3_reg, discard_61) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_61_MASK) | (discard_61 << CP_NV_FLAGS_3_DISCARD_61_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_61(cp_nv_flags_3_reg, end_rcvd_61) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_61_MASK) | (end_rcvd_61 << CP_NV_FLAGS_3_END_RCVD_61_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_62(cp_nv_flags_3_reg, discard_62) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_62_MASK) | (discard_62 << CP_NV_FLAGS_3_DISCARD_62_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_62(cp_nv_flags_3_reg, end_rcvd_62) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_62_MASK) | (end_rcvd_62 << CP_NV_FLAGS_3_END_RCVD_62_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_63(cp_nv_flags_3_reg, discard_63) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_63_MASK) | (discard_63 << CP_NV_FLAGS_3_DISCARD_63_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_63(cp_nv_flags_3_reg, end_rcvd_63) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_63_MASK) | (end_rcvd_63 << CP_NV_FLAGS_3_END_RCVD_63_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_nv_flags_3_t { + unsigned int discard_48 : CP_NV_FLAGS_3_DISCARD_48_SIZE; + unsigned int end_rcvd_48 : CP_NV_FLAGS_3_END_RCVD_48_SIZE; + unsigned int discard_49 : CP_NV_FLAGS_3_DISCARD_49_SIZE; + unsigned int end_rcvd_49 : CP_NV_FLAGS_3_END_RCVD_49_SIZE; + unsigned int discard_50 : CP_NV_FLAGS_3_DISCARD_50_SIZE; + unsigned int end_rcvd_50 : CP_NV_FLAGS_3_END_RCVD_50_SIZE; + unsigned int discard_51 : CP_NV_FLAGS_3_DISCARD_51_SIZE; + unsigned int end_rcvd_51 : CP_NV_FLAGS_3_END_RCVD_51_SIZE; + unsigned int discard_52 : CP_NV_FLAGS_3_DISCARD_52_SIZE; + unsigned int end_rcvd_52 : CP_NV_FLAGS_3_END_RCVD_52_SIZE; + unsigned int discard_53 : CP_NV_FLAGS_3_DISCARD_53_SIZE; + unsigned int end_rcvd_53 : CP_NV_FLAGS_3_END_RCVD_53_SIZE; + unsigned int discard_54 : CP_NV_FLAGS_3_DISCARD_54_SIZE; + unsigned int end_rcvd_54 : CP_NV_FLAGS_3_END_RCVD_54_SIZE; + unsigned int discard_55 : CP_NV_FLAGS_3_DISCARD_55_SIZE; + unsigned int end_rcvd_55 : CP_NV_FLAGS_3_END_RCVD_55_SIZE; + unsigned int discard_56 : CP_NV_FLAGS_3_DISCARD_56_SIZE; + unsigned int end_rcvd_56 : CP_NV_FLAGS_3_END_RCVD_56_SIZE; + unsigned int discard_57 : CP_NV_FLAGS_3_DISCARD_57_SIZE; + unsigned int end_rcvd_57 : CP_NV_FLAGS_3_END_RCVD_57_SIZE; + unsigned int discard_58 : CP_NV_FLAGS_3_DISCARD_58_SIZE; + unsigned int end_rcvd_58 : CP_NV_FLAGS_3_END_RCVD_58_SIZE; + unsigned int discard_59 : CP_NV_FLAGS_3_DISCARD_59_SIZE; + unsigned int end_rcvd_59 : CP_NV_FLAGS_3_END_RCVD_59_SIZE; + unsigned int discard_60 : CP_NV_FLAGS_3_DISCARD_60_SIZE; + unsigned int end_rcvd_60 : CP_NV_FLAGS_3_END_RCVD_60_SIZE; + unsigned int discard_61 : CP_NV_FLAGS_3_DISCARD_61_SIZE; + unsigned int end_rcvd_61 : CP_NV_FLAGS_3_END_RCVD_61_SIZE; + unsigned int discard_62 : CP_NV_FLAGS_3_DISCARD_62_SIZE; + unsigned int end_rcvd_62 : CP_NV_FLAGS_3_END_RCVD_62_SIZE; + unsigned int discard_63 : CP_NV_FLAGS_3_DISCARD_63_SIZE; + unsigned int end_rcvd_63 : CP_NV_FLAGS_3_END_RCVD_63_SIZE; + } cp_nv_flags_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_nv_flags_3_t { + unsigned int end_rcvd_63 : CP_NV_FLAGS_3_END_RCVD_63_SIZE; + unsigned int discard_63 : CP_NV_FLAGS_3_DISCARD_63_SIZE; + unsigned int end_rcvd_62 : CP_NV_FLAGS_3_END_RCVD_62_SIZE; + unsigned int discard_62 : CP_NV_FLAGS_3_DISCARD_62_SIZE; + unsigned int end_rcvd_61 : CP_NV_FLAGS_3_END_RCVD_61_SIZE; + unsigned int discard_61 : CP_NV_FLAGS_3_DISCARD_61_SIZE; + unsigned int end_rcvd_60 : CP_NV_FLAGS_3_END_RCVD_60_SIZE; + unsigned int discard_60 : CP_NV_FLAGS_3_DISCARD_60_SIZE; + unsigned int end_rcvd_59 : CP_NV_FLAGS_3_END_RCVD_59_SIZE; + unsigned int discard_59 : CP_NV_FLAGS_3_DISCARD_59_SIZE; + unsigned int end_rcvd_58 : CP_NV_FLAGS_3_END_RCVD_58_SIZE; + unsigned int discard_58 : CP_NV_FLAGS_3_DISCARD_58_SIZE; + unsigned int end_rcvd_57 : CP_NV_FLAGS_3_END_RCVD_57_SIZE; + unsigned int discard_57 : CP_NV_FLAGS_3_DISCARD_57_SIZE; + unsigned int end_rcvd_56 : CP_NV_FLAGS_3_END_RCVD_56_SIZE; + unsigned int discard_56 : CP_NV_FLAGS_3_DISCARD_56_SIZE; + unsigned int end_rcvd_55 : CP_NV_FLAGS_3_END_RCVD_55_SIZE; + unsigned int discard_55 : CP_NV_FLAGS_3_DISCARD_55_SIZE; + unsigned int end_rcvd_54 : CP_NV_FLAGS_3_END_RCVD_54_SIZE; + unsigned int discard_54 : CP_NV_FLAGS_3_DISCARD_54_SIZE; + unsigned int end_rcvd_53 : CP_NV_FLAGS_3_END_RCVD_53_SIZE; + unsigned int discard_53 : CP_NV_FLAGS_3_DISCARD_53_SIZE; + unsigned int end_rcvd_52 : CP_NV_FLAGS_3_END_RCVD_52_SIZE; + unsigned int discard_52 : CP_NV_FLAGS_3_DISCARD_52_SIZE; + unsigned int end_rcvd_51 : CP_NV_FLAGS_3_END_RCVD_51_SIZE; + unsigned int discard_51 : CP_NV_FLAGS_3_DISCARD_51_SIZE; + unsigned int end_rcvd_50 : CP_NV_FLAGS_3_END_RCVD_50_SIZE; + unsigned int discard_50 : CP_NV_FLAGS_3_DISCARD_50_SIZE; + unsigned int end_rcvd_49 : CP_NV_FLAGS_3_END_RCVD_49_SIZE; + unsigned int discard_49 : CP_NV_FLAGS_3_DISCARD_49_SIZE; + unsigned int end_rcvd_48 : CP_NV_FLAGS_3_END_RCVD_48_SIZE; + unsigned int discard_48 : CP_NV_FLAGS_3_DISCARD_48_SIZE; + } cp_nv_flags_3_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_nv_flags_3_t f; +} cp_nv_flags_3_u; + + +/* + * CP_STATE_DEBUG_INDEX struct + */ + +#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE 5 + +#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT 0 + +#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK 0x0000001f + +#define CP_STATE_DEBUG_INDEX_MASK \ + (CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) + +#define CP_STATE_DEBUG_INDEX(state_debug_index) \ + ((state_debug_index << CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT)) + +#define CP_STATE_DEBUG_INDEX_GET_STATE_DEBUG_INDEX(cp_state_debug_index) \ + ((cp_state_debug_index & CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) >> CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT) + +#define CP_STATE_DEBUG_INDEX_SET_STATE_DEBUG_INDEX(cp_state_debug_index_reg, state_debug_index) \ + cp_state_debug_index_reg = (cp_state_debug_index_reg & ~CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) | (state_debug_index << CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_state_debug_index_t { + unsigned int state_debug_index : CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE; + unsigned int : 27; + } cp_state_debug_index_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_state_debug_index_t { + unsigned int : 27; + unsigned int state_debug_index : CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE; + } cp_state_debug_index_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_state_debug_index_t f; +} cp_state_debug_index_u; + + +/* + * CP_STATE_DEBUG_DATA struct + */ + +#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE 32 + +#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT 0 + +#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK 0xffffffff + +#define CP_STATE_DEBUG_DATA_MASK \ + (CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) + +#define CP_STATE_DEBUG_DATA(state_debug_data) \ + ((state_debug_data << CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT)) + +#define CP_STATE_DEBUG_DATA_GET_STATE_DEBUG_DATA(cp_state_debug_data) \ + ((cp_state_debug_data & CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) >> CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT) + +#define CP_STATE_DEBUG_DATA_SET_STATE_DEBUG_DATA(cp_state_debug_data_reg, state_debug_data) \ + cp_state_debug_data_reg = (cp_state_debug_data_reg & ~CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) | (state_debug_data << CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_state_debug_data_t { + unsigned int state_debug_data : CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE; + } cp_state_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_state_debug_data_t { + unsigned int state_debug_data : CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE; + } cp_state_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_state_debug_data_t f; +} cp_state_debug_data_u; + + +/* + * CP_PROG_COUNTER struct + */ + +#define CP_PROG_COUNTER_COUNTER_SIZE 32 + +#define CP_PROG_COUNTER_COUNTER_SHIFT 0 + +#define CP_PROG_COUNTER_COUNTER_MASK 0xffffffff + +#define CP_PROG_COUNTER_MASK \ + (CP_PROG_COUNTER_COUNTER_MASK) + +#define CP_PROG_COUNTER(counter) \ + ((counter << CP_PROG_COUNTER_COUNTER_SHIFT)) + +#define CP_PROG_COUNTER_GET_COUNTER(cp_prog_counter) \ + ((cp_prog_counter & CP_PROG_COUNTER_COUNTER_MASK) >> CP_PROG_COUNTER_COUNTER_SHIFT) + +#define CP_PROG_COUNTER_SET_COUNTER(cp_prog_counter_reg, counter) \ + cp_prog_counter_reg = (cp_prog_counter_reg & ~CP_PROG_COUNTER_COUNTER_MASK) | (counter << CP_PROG_COUNTER_COUNTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_prog_counter_t { + unsigned int counter : CP_PROG_COUNTER_COUNTER_SIZE; + } cp_prog_counter_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_prog_counter_t { + unsigned int counter : CP_PROG_COUNTER_COUNTER_SIZE; + } cp_prog_counter_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_prog_counter_t f; +} cp_prog_counter_u; + + +/* + * CP_STAT struct + */ + +#define CP_STAT_MIU_WR_BUSY_SIZE 1 +#define CP_STAT_MIU_RD_REQ_BUSY_SIZE 1 +#define CP_STAT_MIU_RD_RETURN_BUSY_SIZE 1 +#define CP_STAT_RBIU_BUSY_SIZE 1 +#define CP_STAT_RCIU_BUSY_SIZE 1 +#define CP_STAT_CSF_RING_BUSY_SIZE 1 +#define CP_STAT_CSF_INDIRECTS_BUSY_SIZE 1 +#define CP_STAT_CSF_INDIRECT2_BUSY_SIZE 1 +#define CP_STAT_CSF_ST_BUSY_SIZE 1 +#define CP_STAT_CSF_BUSY_SIZE 1 +#define CP_STAT_RING_QUEUE_BUSY_SIZE 1 +#define CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE 1 +#define CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE 1 +#define CP_STAT_ST_QUEUE_BUSY_SIZE 1 +#define CP_STAT_PFP_BUSY_SIZE 1 +#define CP_STAT_MEQ_RING_BUSY_SIZE 1 +#define CP_STAT_MEQ_INDIRECTS_BUSY_SIZE 1 +#define CP_STAT_MEQ_INDIRECT2_BUSY_SIZE 1 +#define CP_STAT_MIU_WC_STALL_SIZE 1 +#define CP_STAT_CP_NRT_BUSY_SIZE 1 +#define CP_STAT__3D_BUSY_SIZE 1 +#define CP_STAT_ME_BUSY_SIZE 1 +#define CP_STAT_ME_WC_BUSY_SIZE 1 +#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE 1 +#define CP_STAT_CP_BUSY_SIZE 1 + +#define CP_STAT_MIU_WR_BUSY_SHIFT 0 +#define CP_STAT_MIU_RD_REQ_BUSY_SHIFT 1 +#define CP_STAT_MIU_RD_RETURN_BUSY_SHIFT 2 +#define CP_STAT_RBIU_BUSY_SHIFT 3 +#define CP_STAT_RCIU_BUSY_SHIFT 4 +#define CP_STAT_CSF_RING_BUSY_SHIFT 5 +#define CP_STAT_CSF_INDIRECTS_BUSY_SHIFT 6 +#define CP_STAT_CSF_INDIRECT2_BUSY_SHIFT 7 +#define CP_STAT_CSF_ST_BUSY_SHIFT 9 +#define CP_STAT_CSF_BUSY_SHIFT 10 +#define CP_STAT_RING_QUEUE_BUSY_SHIFT 11 +#define CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT 12 +#define CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT 13 +#define CP_STAT_ST_QUEUE_BUSY_SHIFT 16 +#define CP_STAT_PFP_BUSY_SHIFT 17 +#define CP_STAT_MEQ_RING_BUSY_SHIFT 18 +#define CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT 19 +#define CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT 20 +#define CP_STAT_MIU_WC_STALL_SHIFT 21 +#define CP_STAT_CP_NRT_BUSY_SHIFT 22 +#define CP_STAT__3D_BUSY_SHIFT 23 +#define CP_STAT_ME_BUSY_SHIFT 26 +#define CP_STAT_ME_WC_BUSY_SHIFT 29 +#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT 30 +#define CP_STAT_CP_BUSY_SHIFT 31 + +#define CP_STAT_MIU_WR_BUSY_MASK 0x00000001 +#define CP_STAT_MIU_RD_REQ_BUSY_MASK 0x00000002 +#define CP_STAT_MIU_RD_RETURN_BUSY_MASK 0x00000004 +#define CP_STAT_RBIU_BUSY_MASK 0x00000008 +#define CP_STAT_RCIU_BUSY_MASK 0x00000010 +#define CP_STAT_CSF_RING_BUSY_MASK 0x00000020 +#define CP_STAT_CSF_INDIRECTS_BUSY_MASK 0x00000040 +#define CP_STAT_CSF_INDIRECT2_BUSY_MASK 0x00000080 +#define CP_STAT_CSF_ST_BUSY_MASK 0x00000200 +#define CP_STAT_CSF_BUSY_MASK 0x00000400 +#define CP_STAT_RING_QUEUE_BUSY_MASK 0x00000800 +#define CP_STAT_INDIRECTS_QUEUE_BUSY_MASK 0x00001000 +#define CP_STAT_INDIRECT2_QUEUE_BUSY_MASK 0x00002000 +#define CP_STAT_ST_QUEUE_BUSY_MASK 0x00010000 +#define CP_STAT_PFP_BUSY_MASK 0x00020000 +#define CP_STAT_MEQ_RING_BUSY_MASK 0x00040000 +#define CP_STAT_MEQ_INDIRECTS_BUSY_MASK 0x00080000 +#define CP_STAT_MEQ_INDIRECT2_BUSY_MASK 0x00100000 +#define CP_STAT_MIU_WC_STALL_MASK 0x00200000 +#define CP_STAT_CP_NRT_BUSY_MASK 0x00400000 +#define CP_STAT__3D_BUSY_MASK 0x00800000 +#define CP_STAT_ME_BUSY_MASK 0x04000000 +#define CP_STAT_ME_WC_BUSY_MASK 0x20000000 +#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK 0x40000000 +#define CP_STAT_CP_BUSY_MASK 0x80000000 + +#define CP_STAT_MASK \ + (CP_STAT_MIU_WR_BUSY_MASK | \ + CP_STAT_MIU_RD_REQ_BUSY_MASK | \ + CP_STAT_MIU_RD_RETURN_BUSY_MASK | \ + CP_STAT_RBIU_BUSY_MASK | \ + CP_STAT_RCIU_BUSY_MASK | \ + CP_STAT_CSF_RING_BUSY_MASK | \ + CP_STAT_CSF_INDIRECTS_BUSY_MASK | \ + CP_STAT_CSF_INDIRECT2_BUSY_MASK | \ + CP_STAT_CSF_ST_BUSY_MASK | \ + CP_STAT_CSF_BUSY_MASK | \ + CP_STAT_RING_QUEUE_BUSY_MASK | \ + CP_STAT_INDIRECTS_QUEUE_BUSY_MASK | \ + CP_STAT_INDIRECT2_QUEUE_BUSY_MASK | \ + CP_STAT_ST_QUEUE_BUSY_MASK | \ + CP_STAT_PFP_BUSY_MASK | \ + CP_STAT_MEQ_RING_BUSY_MASK | \ + CP_STAT_MEQ_INDIRECTS_BUSY_MASK | \ + CP_STAT_MEQ_INDIRECT2_BUSY_MASK | \ + CP_STAT_MIU_WC_STALL_MASK | \ + CP_STAT_CP_NRT_BUSY_MASK | \ + CP_STAT__3D_BUSY_MASK | \ + CP_STAT_ME_BUSY_MASK | \ + CP_STAT_ME_WC_BUSY_MASK | \ + CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK | \ + CP_STAT_CP_BUSY_MASK) + +#define CP_STAT(miu_wr_busy, miu_rd_req_busy, miu_rd_return_busy, rbiu_busy, rciu_busy, csf_ring_busy, csf_indirects_busy, csf_indirect2_busy, csf_st_busy, csf_busy, ring_queue_busy, indirects_queue_busy, indirect2_queue_busy, st_queue_busy, pfp_busy, meq_ring_busy, meq_indirects_busy, meq_indirect2_busy, miu_wc_stall, cp_nrt_busy, _3d_busy, me_busy, me_wc_busy, miu_wc_track_fifo_empty, cp_busy) \ + ((miu_wr_busy << CP_STAT_MIU_WR_BUSY_SHIFT) | \ + (miu_rd_req_busy << CP_STAT_MIU_RD_REQ_BUSY_SHIFT) | \ + (miu_rd_return_busy << CP_STAT_MIU_RD_RETURN_BUSY_SHIFT) | \ + (rbiu_busy << CP_STAT_RBIU_BUSY_SHIFT) | \ + (rciu_busy << CP_STAT_RCIU_BUSY_SHIFT) | \ + (csf_ring_busy << CP_STAT_CSF_RING_BUSY_SHIFT) | \ + (csf_indirects_busy << CP_STAT_CSF_INDIRECTS_BUSY_SHIFT) | \ + (csf_indirect2_busy << CP_STAT_CSF_INDIRECT2_BUSY_SHIFT) | \ + (csf_st_busy << CP_STAT_CSF_ST_BUSY_SHIFT) | \ + (csf_busy << CP_STAT_CSF_BUSY_SHIFT) | \ + (ring_queue_busy << CP_STAT_RING_QUEUE_BUSY_SHIFT) | \ + (indirects_queue_busy << CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT) | \ + (indirect2_queue_busy << CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT) | \ + (st_queue_busy << CP_STAT_ST_QUEUE_BUSY_SHIFT) | \ + (pfp_busy << CP_STAT_PFP_BUSY_SHIFT) | \ + (meq_ring_busy << CP_STAT_MEQ_RING_BUSY_SHIFT) | \ + (meq_indirects_busy << CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT) | \ + (meq_indirect2_busy << CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT) | \ + (miu_wc_stall << CP_STAT_MIU_WC_STALL_SHIFT) | \ + (cp_nrt_busy << CP_STAT_CP_NRT_BUSY_SHIFT) | \ + (_3d_busy << CP_STAT__3D_BUSY_SHIFT) | \ + (me_busy << CP_STAT_ME_BUSY_SHIFT) | \ + (me_wc_busy << CP_STAT_ME_WC_BUSY_SHIFT) | \ + (miu_wc_track_fifo_empty << CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT) | \ + (cp_busy << CP_STAT_CP_BUSY_SHIFT)) + +#define CP_STAT_GET_MIU_WR_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MIU_WR_BUSY_MASK) >> CP_STAT_MIU_WR_BUSY_SHIFT) +#define CP_STAT_GET_MIU_RD_REQ_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MIU_RD_REQ_BUSY_MASK) >> CP_STAT_MIU_RD_REQ_BUSY_SHIFT) +#define CP_STAT_GET_MIU_RD_RETURN_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MIU_RD_RETURN_BUSY_MASK) >> CP_STAT_MIU_RD_RETURN_BUSY_SHIFT) +#define CP_STAT_GET_RBIU_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_RBIU_BUSY_MASK) >> CP_STAT_RBIU_BUSY_SHIFT) +#define CP_STAT_GET_RCIU_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_RCIU_BUSY_MASK) >> CP_STAT_RCIU_BUSY_SHIFT) +#define CP_STAT_GET_CSF_RING_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_RING_BUSY_MASK) >> CP_STAT_CSF_RING_BUSY_SHIFT) +#define CP_STAT_GET_CSF_INDIRECTS_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_INDIRECTS_BUSY_MASK) >> CP_STAT_CSF_INDIRECTS_BUSY_SHIFT) +#define CP_STAT_GET_CSF_INDIRECT2_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_INDIRECT2_BUSY_MASK) >> CP_STAT_CSF_INDIRECT2_BUSY_SHIFT) +#define CP_STAT_GET_CSF_ST_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_ST_BUSY_MASK) >> CP_STAT_CSF_ST_BUSY_SHIFT) +#define CP_STAT_GET_CSF_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_BUSY_MASK) >> CP_STAT_CSF_BUSY_SHIFT) +#define CP_STAT_GET_RING_QUEUE_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_RING_QUEUE_BUSY_MASK) >> CP_STAT_RING_QUEUE_BUSY_SHIFT) +#define CP_STAT_GET_INDIRECTS_QUEUE_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_INDIRECTS_QUEUE_BUSY_MASK) >> CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT) +#define CP_STAT_GET_INDIRECT2_QUEUE_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_INDIRECT2_QUEUE_BUSY_MASK) >> CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT) +#define CP_STAT_GET_ST_QUEUE_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_ST_QUEUE_BUSY_MASK) >> CP_STAT_ST_QUEUE_BUSY_SHIFT) +#define CP_STAT_GET_PFP_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_PFP_BUSY_MASK) >> CP_STAT_PFP_BUSY_SHIFT) +#define CP_STAT_GET_MEQ_RING_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MEQ_RING_BUSY_MASK) >> CP_STAT_MEQ_RING_BUSY_SHIFT) +#define CP_STAT_GET_MEQ_INDIRECTS_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MEQ_INDIRECTS_BUSY_MASK) >> CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT) +#define CP_STAT_GET_MEQ_INDIRECT2_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MEQ_INDIRECT2_BUSY_MASK) >> CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT) +#define CP_STAT_GET_MIU_WC_STALL(cp_stat) \ + ((cp_stat & CP_STAT_MIU_WC_STALL_MASK) >> CP_STAT_MIU_WC_STALL_SHIFT) +#define CP_STAT_GET_CP_NRT_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CP_NRT_BUSY_MASK) >> CP_STAT_CP_NRT_BUSY_SHIFT) +#define CP_STAT_GET__3D_BUSY(cp_stat) \ + ((cp_stat & CP_STAT__3D_BUSY_MASK) >> CP_STAT__3D_BUSY_SHIFT) +#define CP_STAT_GET_ME_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_ME_BUSY_MASK) >> CP_STAT_ME_BUSY_SHIFT) +#define CP_STAT_GET_ME_WC_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_ME_WC_BUSY_MASK) >> CP_STAT_ME_WC_BUSY_SHIFT) +#define CP_STAT_GET_MIU_WC_TRACK_FIFO_EMPTY(cp_stat) \ + ((cp_stat & CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK) >> CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT) +#define CP_STAT_GET_CP_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CP_BUSY_MASK) >> CP_STAT_CP_BUSY_SHIFT) + +#define CP_STAT_SET_MIU_WR_BUSY(cp_stat_reg, miu_wr_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WR_BUSY_MASK) | (miu_wr_busy << CP_STAT_MIU_WR_BUSY_SHIFT) +#define CP_STAT_SET_MIU_RD_REQ_BUSY(cp_stat_reg, miu_rd_req_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_RD_REQ_BUSY_MASK) | (miu_rd_req_busy << CP_STAT_MIU_RD_REQ_BUSY_SHIFT) +#define CP_STAT_SET_MIU_RD_RETURN_BUSY(cp_stat_reg, miu_rd_return_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_RD_RETURN_BUSY_MASK) | (miu_rd_return_busy << CP_STAT_MIU_RD_RETURN_BUSY_SHIFT) +#define CP_STAT_SET_RBIU_BUSY(cp_stat_reg, rbiu_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_RBIU_BUSY_MASK) | (rbiu_busy << CP_STAT_RBIU_BUSY_SHIFT) +#define CP_STAT_SET_RCIU_BUSY(cp_stat_reg, rciu_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_RCIU_BUSY_MASK) | (rciu_busy << CP_STAT_RCIU_BUSY_SHIFT) +#define CP_STAT_SET_CSF_RING_BUSY(cp_stat_reg, csf_ring_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_RING_BUSY_MASK) | (csf_ring_busy << CP_STAT_CSF_RING_BUSY_SHIFT) +#define CP_STAT_SET_CSF_INDIRECTS_BUSY(cp_stat_reg, csf_indirects_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_INDIRECTS_BUSY_MASK) | (csf_indirects_busy << CP_STAT_CSF_INDIRECTS_BUSY_SHIFT) +#define CP_STAT_SET_CSF_INDIRECT2_BUSY(cp_stat_reg, csf_indirect2_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_INDIRECT2_BUSY_MASK) | (csf_indirect2_busy << CP_STAT_CSF_INDIRECT2_BUSY_SHIFT) +#define CP_STAT_SET_CSF_ST_BUSY(cp_stat_reg, csf_st_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_ST_BUSY_MASK) | (csf_st_busy << CP_STAT_CSF_ST_BUSY_SHIFT) +#define CP_STAT_SET_CSF_BUSY(cp_stat_reg, csf_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_BUSY_MASK) | (csf_busy << CP_STAT_CSF_BUSY_SHIFT) +#define CP_STAT_SET_RING_QUEUE_BUSY(cp_stat_reg, ring_queue_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_RING_QUEUE_BUSY_MASK) | (ring_queue_busy << CP_STAT_RING_QUEUE_BUSY_SHIFT) +#define CP_STAT_SET_INDIRECTS_QUEUE_BUSY(cp_stat_reg, indirects_queue_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_INDIRECTS_QUEUE_BUSY_MASK) | (indirects_queue_busy << CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT) +#define CP_STAT_SET_INDIRECT2_QUEUE_BUSY(cp_stat_reg, indirect2_queue_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_INDIRECT2_QUEUE_BUSY_MASK) | (indirect2_queue_busy << CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT) +#define CP_STAT_SET_ST_QUEUE_BUSY(cp_stat_reg, st_queue_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_ST_QUEUE_BUSY_MASK) | (st_queue_busy << CP_STAT_ST_QUEUE_BUSY_SHIFT) +#define CP_STAT_SET_PFP_BUSY(cp_stat_reg, pfp_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_PFP_BUSY_MASK) | (pfp_busy << CP_STAT_PFP_BUSY_SHIFT) +#define CP_STAT_SET_MEQ_RING_BUSY(cp_stat_reg, meq_ring_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_RING_BUSY_MASK) | (meq_ring_busy << CP_STAT_MEQ_RING_BUSY_SHIFT) +#define CP_STAT_SET_MEQ_INDIRECTS_BUSY(cp_stat_reg, meq_indirects_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_INDIRECTS_BUSY_MASK) | (meq_indirects_busy << CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT) +#define CP_STAT_SET_MEQ_INDIRECT2_BUSY(cp_stat_reg, meq_indirect2_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_INDIRECT2_BUSY_MASK) | (meq_indirect2_busy << CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT) +#define CP_STAT_SET_MIU_WC_STALL(cp_stat_reg, miu_wc_stall) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WC_STALL_MASK) | (miu_wc_stall << CP_STAT_MIU_WC_STALL_SHIFT) +#define CP_STAT_SET_CP_NRT_BUSY(cp_stat_reg, cp_nrt_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CP_NRT_BUSY_MASK) | (cp_nrt_busy << CP_STAT_CP_NRT_BUSY_SHIFT) +#define CP_STAT_SET__3D_BUSY(cp_stat_reg, _3d_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT__3D_BUSY_MASK) | (_3d_busy << CP_STAT__3D_BUSY_SHIFT) +#define CP_STAT_SET_ME_BUSY(cp_stat_reg, me_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_ME_BUSY_MASK) | (me_busy << CP_STAT_ME_BUSY_SHIFT) +#define CP_STAT_SET_ME_WC_BUSY(cp_stat_reg, me_wc_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_ME_WC_BUSY_MASK) | (me_wc_busy << CP_STAT_ME_WC_BUSY_SHIFT) +#define CP_STAT_SET_MIU_WC_TRACK_FIFO_EMPTY(cp_stat_reg, miu_wc_track_fifo_empty) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK) | (miu_wc_track_fifo_empty << CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT) +#define CP_STAT_SET_CP_BUSY(cp_stat_reg, cp_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CP_BUSY_MASK) | (cp_busy << CP_STAT_CP_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_stat_t { + unsigned int miu_wr_busy : CP_STAT_MIU_WR_BUSY_SIZE; + unsigned int miu_rd_req_busy : CP_STAT_MIU_RD_REQ_BUSY_SIZE; + unsigned int miu_rd_return_busy : CP_STAT_MIU_RD_RETURN_BUSY_SIZE; + unsigned int rbiu_busy : CP_STAT_RBIU_BUSY_SIZE; + unsigned int rciu_busy : CP_STAT_RCIU_BUSY_SIZE; + unsigned int csf_ring_busy : CP_STAT_CSF_RING_BUSY_SIZE; + unsigned int csf_indirects_busy : CP_STAT_CSF_INDIRECTS_BUSY_SIZE; + unsigned int csf_indirect2_busy : CP_STAT_CSF_INDIRECT2_BUSY_SIZE; + unsigned int : 1; + unsigned int csf_st_busy : CP_STAT_CSF_ST_BUSY_SIZE; + unsigned int csf_busy : CP_STAT_CSF_BUSY_SIZE; + unsigned int ring_queue_busy : CP_STAT_RING_QUEUE_BUSY_SIZE; + unsigned int indirects_queue_busy : CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE; + unsigned int indirect2_queue_busy : CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE; + unsigned int : 2; + unsigned int st_queue_busy : CP_STAT_ST_QUEUE_BUSY_SIZE; + unsigned int pfp_busy : CP_STAT_PFP_BUSY_SIZE; + unsigned int meq_ring_busy : CP_STAT_MEQ_RING_BUSY_SIZE; + unsigned int meq_indirects_busy : CP_STAT_MEQ_INDIRECTS_BUSY_SIZE; + unsigned int meq_indirect2_busy : CP_STAT_MEQ_INDIRECT2_BUSY_SIZE; + unsigned int miu_wc_stall : CP_STAT_MIU_WC_STALL_SIZE; + unsigned int cp_nrt_busy : CP_STAT_CP_NRT_BUSY_SIZE; + unsigned int _3d_busy : CP_STAT__3D_BUSY_SIZE; + unsigned int : 2; + unsigned int me_busy : CP_STAT_ME_BUSY_SIZE; + unsigned int : 2; + unsigned int me_wc_busy : CP_STAT_ME_WC_BUSY_SIZE; + unsigned int miu_wc_track_fifo_empty : CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE; + unsigned int cp_busy : CP_STAT_CP_BUSY_SIZE; + } cp_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_stat_t { + unsigned int cp_busy : CP_STAT_CP_BUSY_SIZE; + unsigned int miu_wc_track_fifo_empty : CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE; + unsigned int me_wc_busy : CP_STAT_ME_WC_BUSY_SIZE; + unsigned int : 2; + unsigned int me_busy : CP_STAT_ME_BUSY_SIZE; + unsigned int : 2; + unsigned int _3d_busy : CP_STAT__3D_BUSY_SIZE; + unsigned int cp_nrt_busy : CP_STAT_CP_NRT_BUSY_SIZE; + unsigned int miu_wc_stall : CP_STAT_MIU_WC_STALL_SIZE; + unsigned int meq_indirect2_busy : CP_STAT_MEQ_INDIRECT2_BUSY_SIZE; + unsigned int meq_indirects_busy : CP_STAT_MEQ_INDIRECTS_BUSY_SIZE; + unsigned int meq_ring_busy : CP_STAT_MEQ_RING_BUSY_SIZE; + unsigned int pfp_busy : CP_STAT_PFP_BUSY_SIZE; + unsigned int st_queue_busy : CP_STAT_ST_QUEUE_BUSY_SIZE; + unsigned int : 2; + unsigned int indirect2_queue_busy : CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE; + unsigned int indirects_queue_busy : CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE; + unsigned int ring_queue_busy : CP_STAT_RING_QUEUE_BUSY_SIZE; + unsigned int csf_busy : CP_STAT_CSF_BUSY_SIZE; + unsigned int csf_st_busy : CP_STAT_CSF_ST_BUSY_SIZE; + unsigned int : 1; + unsigned int csf_indirect2_busy : CP_STAT_CSF_INDIRECT2_BUSY_SIZE; + unsigned int csf_indirects_busy : CP_STAT_CSF_INDIRECTS_BUSY_SIZE; + unsigned int csf_ring_busy : CP_STAT_CSF_RING_BUSY_SIZE; + unsigned int rciu_busy : CP_STAT_RCIU_BUSY_SIZE; + unsigned int rbiu_busy : CP_STAT_RBIU_BUSY_SIZE; + unsigned int miu_rd_return_busy : CP_STAT_MIU_RD_RETURN_BUSY_SIZE; + unsigned int miu_rd_req_busy : CP_STAT_MIU_RD_REQ_BUSY_SIZE; + unsigned int miu_wr_busy : CP_STAT_MIU_WR_BUSY_SIZE; + } cp_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_stat_t f; +} cp_stat_u; + + +/* + * BIOS_0_SCRATCH struct + */ + +#define BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_0_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_0_SCRATCH_MASK \ + (BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_0_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_0_SCRATCH_GET_BIOS_SCRATCH(bios_0_scratch) \ + ((bios_0_scratch & BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_0_SCRATCH_SET_BIOS_SCRATCH(bios_0_scratch_reg, bios_scratch) \ + bios_0_scratch_reg = (bios_0_scratch_reg & ~BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_0_scratch_t { + unsigned int bios_scratch : BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_0_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_0_scratch_t { + unsigned int bios_scratch : BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_0_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_0_scratch_t f; +} bios_0_scratch_u; + + +/* + * BIOS_1_SCRATCH struct + */ + +#define BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_1_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_1_SCRATCH_MASK \ + (BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_1_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_1_SCRATCH_GET_BIOS_SCRATCH(bios_1_scratch) \ + ((bios_1_scratch & BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_1_SCRATCH_SET_BIOS_SCRATCH(bios_1_scratch_reg, bios_scratch) \ + bios_1_scratch_reg = (bios_1_scratch_reg & ~BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_1_scratch_t { + unsigned int bios_scratch : BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_1_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_1_scratch_t { + unsigned int bios_scratch : BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_1_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_1_scratch_t f; +} bios_1_scratch_u; + + +/* + * BIOS_2_SCRATCH struct + */ + +#define BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_2_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_2_SCRATCH_MASK \ + (BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_2_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_2_SCRATCH_GET_BIOS_SCRATCH(bios_2_scratch) \ + ((bios_2_scratch & BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_2_SCRATCH_SET_BIOS_SCRATCH(bios_2_scratch_reg, bios_scratch) \ + bios_2_scratch_reg = (bios_2_scratch_reg & ~BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_2_scratch_t { + unsigned int bios_scratch : BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_2_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_2_scratch_t { + unsigned int bios_scratch : BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_2_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_2_scratch_t f; +} bios_2_scratch_u; + + +/* + * BIOS_3_SCRATCH struct + */ + +#define BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_3_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_3_SCRATCH_MASK \ + (BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_3_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_3_SCRATCH_GET_BIOS_SCRATCH(bios_3_scratch) \ + ((bios_3_scratch & BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_3_SCRATCH_SET_BIOS_SCRATCH(bios_3_scratch_reg, bios_scratch) \ + bios_3_scratch_reg = (bios_3_scratch_reg & ~BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_3_scratch_t { + unsigned int bios_scratch : BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_3_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_3_scratch_t { + unsigned int bios_scratch : BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_3_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_3_scratch_t f; +} bios_3_scratch_u; + + +/* + * BIOS_4_SCRATCH struct + */ + +#define BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_4_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_4_SCRATCH_MASK \ + (BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_4_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_4_SCRATCH_GET_BIOS_SCRATCH(bios_4_scratch) \ + ((bios_4_scratch & BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_4_SCRATCH_SET_BIOS_SCRATCH(bios_4_scratch_reg, bios_scratch) \ + bios_4_scratch_reg = (bios_4_scratch_reg & ~BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_4_scratch_t { + unsigned int bios_scratch : BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_4_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_4_scratch_t { + unsigned int bios_scratch : BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_4_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_4_scratch_t f; +} bios_4_scratch_u; + + +/* + * BIOS_5_SCRATCH struct + */ + +#define BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_5_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_5_SCRATCH_MASK \ + (BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_5_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_5_SCRATCH_GET_BIOS_SCRATCH(bios_5_scratch) \ + ((bios_5_scratch & BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_5_SCRATCH_SET_BIOS_SCRATCH(bios_5_scratch_reg, bios_scratch) \ + bios_5_scratch_reg = (bios_5_scratch_reg & ~BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_5_scratch_t { + unsigned int bios_scratch : BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_5_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_5_scratch_t { + unsigned int bios_scratch : BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_5_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_5_scratch_t f; +} bios_5_scratch_u; + + +/* + * BIOS_6_SCRATCH struct + */ + +#define BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_6_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_6_SCRATCH_MASK \ + (BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_6_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_6_SCRATCH_GET_BIOS_SCRATCH(bios_6_scratch) \ + ((bios_6_scratch & BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_6_SCRATCH_SET_BIOS_SCRATCH(bios_6_scratch_reg, bios_scratch) \ + bios_6_scratch_reg = (bios_6_scratch_reg & ~BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_6_scratch_t { + unsigned int bios_scratch : BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_6_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_6_scratch_t { + unsigned int bios_scratch : BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_6_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_6_scratch_t f; +} bios_6_scratch_u; + + +/* + * BIOS_7_SCRATCH struct + */ + +#define BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_7_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_7_SCRATCH_MASK \ + (BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_7_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_7_SCRATCH_GET_BIOS_SCRATCH(bios_7_scratch) \ + ((bios_7_scratch & BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_7_SCRATCH_SET_BIOS_SCRATCH(bios_7_scratch_reg, bios_scratch) \ + bios_7_scratch_reg = (bios_7_scratch_reg & ~BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_7_scratch_t { + unsigned int bios_scratch : BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_7_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_7_scratch_t { + unsigned int bios_scratch : BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_7_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_7_scratch_t f; +} bios_7_scratch_u; + + +/* + * BIOS_8_SCRATCH struct + */ + +#define BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_8_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_8_SCRATCH_MASK \ + (BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_8_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_8_SCRATCH_GET_BIOS_SCRATCH(bios_8_scratch) \ + ((bios_8_scratch & BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_8_SCRATCH_SET_BIOS_SCRATCH(bios_8_scratch_reg, bios_scratch) \ + bios_8_scratch_reg = (bios_8_scratch_reg & ~BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_8_scratch_t { + unsigned int bios_scratch : BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_8_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_8_scratch_t { + unsigned int bios_scratch : BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_8_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_8_scratch_t f; +} bios_8_scratch_u; + + +/* + * BIOS_9_SCRATCH struct + */ + +#define BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_9_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_9_SCRATCH_MASK \ + (BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_9_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_9_SCRATCH_GET_BIOS_SCRATCH(bios_9_scratch) \ + ((bios_9_scratch & BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_9_SCRATCH_SET_BIOS_SCRATCH(bios_9_scratch_reg, bios_scratch) \ + bios_9_scratch_reg = (bios_9_scratch_reg & ~BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_9_scratch_t { + unsigned int bios_scratch : BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_9_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_9_scratch_t { + unsigned int bios_scratch : BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_9_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_9_scratch_t f; +} bios_9_scratch_u; + + +/* + * BIOS_10_SCRATCH struct + */ + +#define BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_10_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_10_SCRATCH_MASK \ + (BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_10_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_10_SCRATCH_GET_BIOS_SCRATCH(bios_10_scratch) \ + ((bios_10_scratch & BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_10_SCRATCH_SET_BIOS_SCRATCH(bios_10_scratch_reg, bios_scratch) \ + bios_10_scratch_reg = (bios_10_scratch_reg & ~BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_10_scratch_t { + unsigned int bios_scratch : BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_10_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_10_scratch_t { + unsigned int bios_scratch : BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_10_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_10_scratch_t f; +} bios_10_scratch_u; + + +/* + * BIOS_11_SCRATCH struct + */ + +#define BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_11_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_11_SCRATCH_MASK \ + (BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_11_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_11_SCRATCH_GET_BIOS_SCRATCH(bios_11_scratch) \ + ((bios_11_scratch & BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_11_SCRATCH_SET_BIOS_SCRATCH(bios_11_scratch_reg, bios_scratch) \ + bios_11_scratch_reg = (bios_11_scratch_reg & ~BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_11_scratch_t { + unsigned int bios_scratch : BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_11_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_11_scratch_t { + unsigned int bios_scratch : BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_11_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_11_scratch_t f; +} bios_11_scratch_u; + + +/* + * BIOS_12_SCRATCH struct + */ + +#define BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_12_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_12_SCRATCH_MASK \ + (BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_12_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_12_SCRATCH_GET_BIOS_SCRATCH(bios_12_scratch) \ + ((bios_12_scratch & BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_12_SCRATCH_SET_BIOS_SCRATCH(bios_12_scratch_reg, bios_scratch) \ + bios_12_scratch_reg = (bios_12_scratch_reg & ~BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_12_scratch_t { + unsigned int bios_scratch : BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_12_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_12_scratch_t { + unsigned int bios_scratch : BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_12_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_12_scratch_t f; +} bios_12_scratch_u; + + +/* + * BIOS_13_SCRATCH struct + */ + +#define BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_13_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_13_SCRATCH_MASK \ + (BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_13_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_13_SCRATCH_GET_BIOS_SCRATCH(bios_13_scratch) \ + ((bios_13_scratch & BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_13_SCRATCH_SET_BIOS_SCRATCH(bios_13_scratch_reg, bios_scratch) \ + bios_13_scratch_reg = (bios_13_scratch_reg & ~BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_13_scratch_t { + unsigned int bios_scratch : BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_13_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_13_scratch_t { + unsigned int bios_scratch : BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_13_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_13_scratch_t f; +} bios_13_scratch_u; + + +/* + * BIOS_14_SCRATCH struct + */ + +#define BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_14_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_14_SCRATCH_MASK \ + (BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_14_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_14_SCRATCH_GET_BIOS_SCRATCH(bios_14_scratch) \ + ((bios_14_scratch & BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_14_SCRATCH_SET_BIOS_SCRATCH(bios_14_scratch_reg, bios_scratch) \ + bios_14_scratch_reg = (bios_14_scratch_reg & ~BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_14_scratch_t { + unsigned int bios_scratch : BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_14_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_14_scratch_t { + unsigned int bios_scratch : BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_14_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_14_scratch_t f; +} bios_14_scratch_u; + + +/* + * BIOS_15_SCRATCH struct + */ + +#define BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_15_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_15_SCRATCH_MASK \ + (BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_15_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_15_SCRATCH_GET_BIOS_SCRATCH(bios_15_scratch) \ + ((bios_15_scratch & BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_15_SCRATCH_SET_BIOS_SCRATCH(bios_15_scratch_reg, bios_scratch) \ + bios_15_scratch_reg = (bios_15_scratch_reg & ~BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_15_scratch_t { + unsigned int bios_scratch : BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_15_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_15_scratch_t { + unsigned int bios_scratch : BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_15_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_15_scratch_t f; +} bios_15_scratch_u; + + +/* + * COHER_SIZE_PM4 struct + */ + +#define COHER_SIZE_PM4_SIZE_SIZE 32 + +#define COHER_SIZE_PM4_SIZE_SHIFT 0 + +#define COHER_SIZE_PM4_SIZE_MASK 0xffffffff + +#define COHER_SIZE_PM4_MASK \ + (COHER_SIZE_PM4_SIZE_MASK) + +#define COHER_SIZE_PM4(size) \ + ((size << COHER_SIZE_PM4_SIZE_SHIFT)) + +#define COHER_SIZE_PM4_GET_SIZE(coher_size_pm4) \ + ((coher_size_pm4 & COHER_SIZE_PM4_SIZE_MASK) >> COHER_SIZE_PM4_SIZE_SHIFT) + +#define COHER_SIZE_PM4_SET_SIZE(coher_size_pm4_reg, size) \ + coher_size_pm4_reg = (coher_size_pm4_reg & ~COHER_SIZE_PM4_SIZE_MASK) | (size << COHER_SIZE_PM4_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_size_pm4_t { + unsigned int size : COHER_SIZE_PM4_SIZE_SIZE; + } coher_size_pm4_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_size_pm4_t { + unsigned int size : COHER_SIZE_PM4_SIZE_SIZE; + } coher_size_pm4_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_size_pm4_t f; +} coher_size_pm4_u; + + +/* + * COHER_BASE_PM4 struct + */ + +#define COHER_BASE_PM4_BASE_SIZE 32 + +#define COHER_BASE_PM4_BASE_SHIFT 0 + +#define COHER_BASE_PM4_BASE_MASK 0xffffffff + +#define COHER_BASE_PM4_MASK \ + (COHER_BASE_PM4_BASE_MASK) + +#define COHER_BASE_PM4(base) \ + ((base << COHER_BASE_PM4_BASE_SHIFT)) + +#define COHER_BASE_PM4_GET_BASE(coher_base_pm4) \ + ((coher_base_pm4 & COHER_BASE_PM4_BASE_MASK) >> COHER_BASE_PM4_BASE_SHIFT) + +#define COHER_BASE_PM4_SET_BASE(coher_base_pm4_reg, base) \ + coher_base_pm4_reg = (coher_base_pm4_reg & ~COHER_BASE_PM4_BASE_MASK) | (base << COHER_BASE_PM4_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_base_pm4_t { + unsigned int base : COHER_BASE_PM4_BASE_SIZE; + } coher_base_pm4_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_base_pm4_t { + unsigned int base : COHER_BASE_PM4_BASE_SIZE; + } coher_base_pm4_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_base_pm4_t f; +} coher_base_pm4_u; + + +/* + * COHER_STATUS_PM4 struct + */ + +#define COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE 8 +#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE 1 +#define COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SIZE 1 +#define COHER_STATUS_PM4_TC_ACTION_ENA_SIZE 1 +#define COHER_STATUS_PM4_STATUS_SIZE 1 + +#define COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT 0 +#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT 8 +#define COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT 9 +#define COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT 10 +#define COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT 11 +#define COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT 12 +#define COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT 13 +#define COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT 14 +#define COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT 15 +#define COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT 16 +#define COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT 17 +#define COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT 25 +#define COHER_STATUS_PM4_STATUS_SHIFT 31 + +#define COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK 0x000000ff +#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK 0x00000100 +#define COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK 0x00000200 +#define COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK 0x00000400 +#define COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK 0x00000800 +#define COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK 0x00001000 +#define COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK 0x00002000 +#define COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK 0x00004000 +#define COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK 0x00008000 +#define COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK 0x00010000 +#define COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK 0x00020000 +#define COHER_STATUS_PM4_TC_ACTION_ENA_MASK 0x02000000 +#define COHER_STATUS_PM4_STATUS_MASK 0x80000000 + +#define COHER_STATUS_PM4_MASK \ + (COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK | \ + COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK | \ + COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK | \ + COHER_STATUS_PM4_TC_ACTION_ENA_MASK | \ + COHER_STATUS_PM4_STATUS_MASK) + +#define COHER_STATUS_PM4(matching_contexts, rb_copy_dest_base_ena, dest_base_0_ena, dest_base_1_ena, dest_base_2_ena, dest_base_3_ena, dest_base_4_ena, dest_base_5_ena, dest_base_6_ena, dest_base_7_ena, rb_color_info_ena, tc_action_ena, status) \ + ((matching_contexts << COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT) | \ + (rb_copy_dest_base_ena << COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT) | \ + (dest_base_0_ena << COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT) | \ + (dest_base_1_ena << COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT) | \ + (dest_base_2_ena << COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT) | \ + (dest_base_3_ena << COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT) | \ + (dest_base_4_ena << COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT) | \ + (dest_base_5_ena << COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT) | \ + (dest_base_6_ena << COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT) | \ + (dest_base_7_ena << COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT) | \ + (rb_color_info_ena << COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT) | \ + (tc_action_ena << COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT) | \ + (status << COHER_STATUS_PM4_STATUS_SHIFT)) + +#define COHER_STATUS_PM4_GET_MATCHING_CONTEXTS(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK) >> COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT) +#define COHER_STATUS_PM4_GET_RB_COPY_DEST_BASE_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK) >> COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_0_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_1_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_2_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_3_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_4_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_5_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_6_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_7_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_RB_COLOR_INFO_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK) >> COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_TC_ACTION_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_TC_ACTION_ENA_MASK) >> COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_STATUS(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_STATUS_MASK) >> COHER_STATUS_PM4_STATUS_SHIFT) + +#define COHER_STATUS_PM4_SET_MATCHING_CONTEXTS(coher_status_pm4_reg, matching_contexts) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK) | (matching_contexts << COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT) +#define COHER_STATUS_PM4_SET_RB_COPY_DEST_BASE_ENA(coher_status_pm4_reg, rb_copy_dest_base_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK) | (rb_copy_dest_base_ena << COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_0_ENA(coher_status_pm4_reg, dest_base_0_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK) | (dest_base_0_ena << COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_1_ENA(coher_status_pm4_reg, dest_base_1_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK) | (dest_base_1_ena << COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_2_ENA(coher_status_pm4_reg, dest_base_2_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK) | (dest_base_2_ena << COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_3_ENA(coher_status_pm4_reg, dest_base_3_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK) | (dest_base_3_ena << COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_4_ENA(coher_status_pm4_reg, dest_base_4_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK) | (dest_base_4_ena << COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_5_ENA(coher_status_pm4_reg, dest_base_5_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK) | (dest_base_5_ena << COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_6_ENA(coher_status_pm4_reg, dest_base_6_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK) | (dest_base_6_ena << COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_7_ENA(coher_status_pm4_reg, dest_base_7_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK) | (dest_base_7_ena << COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_RB_COLOR_INFO_ENA(coher_status_pm4_reg, rb_color_info_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK) | (rb_color_info_ena << COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_TC_ACTION_ENA(coher_status_pm4_reg, tc_action_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_TC_ACTION_ENA_MASK) | (tc_action_ena << COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_STATUS(coher_status_pm4_reg, status) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_STATUS_MASK) | (status << COHER_STATUS_PM4_STATUS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_status_pm4_t { + unsigned int matching_contexts : COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE; + unsigned int rb_copy_dest_base_ena : COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE; + unsigned int dest_base_0_ena : COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE; + unsigned int dest_base_1_ena : COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE; + unsigned int dest_base_2_ena : COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE; + unsigned int dest_base_3_ena : COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE; + unsigned int dest_base_4_ena : COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE; + unsigned int dest_base_5_ena : COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE; + unsigned int dest_base_6_ena : COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE; + unsigned int dest_base_7_ena : COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE; + unsigned int rb_color_info_ena : COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SIZE; + unsigned int : 7; + unsigned int tc_action_ena : COHER_STATUS_PM4_TC_ACTION_ENA_SIZE; + unsigned int : 5; + unsigned int status : COHER_STATUS_PM4_STATUS_SIZE; + } coher_status_pm4_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_status_pm4_t { + unsigned int status : COHER_STATUS_PM4_STATUS_SIZE; + unsigned int : 5; + unsigned int tc_action_ena : COHER_STATUS_PM4_TC_ACTION_ENA_SIZE; + unsigned int : 7; + unsigned int rb_color_info_ena : COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SIZE; + unsigned int dest_base_7_ena : COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE; + unsigned int dest_base_6_ena : COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE; + unsigned int dest_base_5_ena : COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE; + unsigned int dest_base_4_ena : COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE; + unsigned int dest_base_3_ena : COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE; + unsigned int dest_base_2_ena : COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE; + unsigned int dest_base_1_ena : COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE; + unsigned int dest_base_0_ena : COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE; + unsigned int rb_copy_dest_base_ena : COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE; + unsigned int matching_contexts : COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE; + } coher_status_pm4_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_status_pm4_t f; +} coher_status_pm4_u; + + +/* + * COHER_SIZE_HOST struct + */ + +#define COHER_SIZE_HOST_SIZE_SIZE 32 + +#define COHER_SIZE_HOST_SIZE_SHIFT 0 + +#define COHER_SIZE_HOST_SIZE_MASK 0xffffffff + +#define COHER_SIZE_HOST_MASK \ + (COHER_SIZE_HOST_SIZE_MASK) + +#define COHER_SIZE_HOST(size) \ + ((size << COHER_SIZE_HOST_SIZE_SHIFT)) + +#define COHER_SIZE_HOST_GET_SIZE(coher_size_host) \ + ((coher_size_host & COHER_SIZE_HOST_SIZE_MASK) >> COHER_SIZE_HOST_SIZE_SHIFT) + +#define COHER_SIZE_HOST_SET_SIZE(coher_size_host_reg, size) \ + coher_size_host_reg = (coher_size_host_reg & ~COHER_SIZE_HOST_SIZE_MASK) | (size << COHER_SIZE_HOST_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_size_host_t { + unsigned int size : COHER_SIZE_HOST_SIZE_SIZE; + } coher_size_host_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_size_host_t { + unsigned int size : COHER_SIZE_HOST_SIZE_SIZE; + } coher_size_host_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_size_host_t f; +} coher_size_host_u; + + +/* + * COHER_BASE_HOST struct + */ + +#define COHER_BASE_HOST_BASE_SIZE 32 + +#define COHER_BASE_HOST_BASE_SHIFT 0 + +#define COHER_BASE_HOST_BASE_MASK 0xffffffff + +#define COHER_BASE_HOST_MASK \ + (COHER_BASE_HOST_BASE_MASK) + +#define COHER_BASE_HOST(base) \ + ((base << COHER_BASE_HOST_BASE_SHIFT)) + +#define COHER_BASE_HOST_GET_BASE(coher_base_host) \ + ((coher_base_host & COHER_BASE_HOST_BASE_MASK) >> COHER_BASE_HOST_BASE_SHIFT) + +#define COHER_BASE_HOST_SET_BASE(coher_base_host_reg, base) \ + coher_base_host_reg = (coher_base_host_reg & ~COHER_BASE_HOST_BASE_MASK) | (base << COHER_BASE_HOST_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_base_host_t { + unsigned int base : COHER_BASE_HOST_BASE_SIZE; + } coher_base_host_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_base_host_t { + unsigned int base : COHER_BASE_HOST_BASE_SIZE; + } coher_base_host_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_base_host_t f; +} coher_base_host_u; + + +/* + * COHER_STATUS_HOST struct + */ + +#define COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE 8 +#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE 1 +#define COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SIZE 1 +#define COHER_STATUS_HOST_TC_ACTION_ENA_SIZE 1 +#define COHER_STATUS_HOST_STATUS_SIZE 1 + +#define COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT 0 +#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT 8 +#define COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT 9 +#define COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT 10 +#define COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT 11 +#define COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT 12 +#define COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT 13 +#define COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT 14 +#define COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT 15 +#define COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT 16 +#define COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT 17 +#define COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT 25 +#define COHER_STATUS_HOST_STATUS_SHIFT 31 + +#define COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK 0x000000ff +#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK 0x00000100 +#define COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK 0x00000200 +#define COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK 0x00000400 +#define COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK 0x00000800 +#define COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK 0x00001000 +#define COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK 0x00002000 +#define COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK 0x00004000 +#define COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK 0x00008000 +#define COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK 0x00010000 +#define COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK 0x00020000 +#define COHER_STATUS_HOST_TC_ACTION_ENA_MASK 0x02000000 +#define COHER_STATUS_HOST_STATUS_MASK 0x80000000 + +#define COHER_STATUS_HOST_MASK \ + (COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK | \ + COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK | \ + COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK | \ + COHER_STATUS_HOST_TC_ACTION_ENA_MASK | \ + COHER_STATUS_HOST_STATUS_MASK) + +#define COHER_STATUS_HOST(matching_contexts, rb_copy_dest_base_ena, dest_base_0_ena, dest_base_1_ena, dest_base_2_ena, dest_base_3_ena, dest_base_4_ena, dest_base_5_ena, dest_base_6_ena, dest_base_7_ena, rb_color_info_ena, tc_action_ena, status) \ + ((matching_contexts << COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT) | \ + (rb_copy_dest_base_ena << COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT) | \ + (dest_base_0_ena << COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT) | \ + (dest_base_1_ena << COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT) | \ + (dest_base_2_ena << COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT) | \ + (dest_base_3_ena << COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT) | \ + (dest_base_4_ena << COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT) | \ + (dest_base_5_ena << COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT) | \ + (dest_base_6_ena << COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT) | \ + (dest_base_7_ena << COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT) | \ + (rb_color_info_ena << COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT) | \ + (tc_action_ena << COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT) | \ + (status << COHER_STATUS_HOST_STATUS_SHIFT)) + +#define COHER_STATUS_HOST_GET_MATCHING_CONTEXTS(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK) >> COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT) +#define COHER_STATUS_HOST_GET_RB_COPY_DEST_BASE_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK) >> COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_0_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_1_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_2_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_3_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_4_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_5_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_6_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_7_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_RB_COLOR_INFO_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK) >> COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_TC_ACTION_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_TC_ACTION_ENA_MASK) >> COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_STATUS(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_STATUS_MASK) >> COHER_STATUS_HOST_STATUS_SHIFT) + +#define COHER_STATUS_HOST_SET_MATCHING_CONTEXTS(coher_status_host_reg, matching_contexts) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK) | (matching_contexts << COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT) +#define COHER_STATUS_HOST_SET_RB_COPY_DEST_BASE_ENA(coher_status_host_reg, rb_copy_dest_base_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK) | (rb_copy_dest_base_ena << COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_0_ENA(coher_status_host_reg, dest_base_0_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK) | (dest_base_0_ena << COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_1_ENA(coher_status_host_reg, dest_base_1_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK) | (dest_base_1_ena << COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_2_ENA(coher_status_host_reg, dest_base_2_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK) | (dest_base_2_ena << COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_3_ENA(coher_status_host_reg, dest_base_3_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK) | (dest_base_3_ena << COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_4_ENA(coher_status_host_reg, dest_base_4_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK) | (dest_base_4_ena << COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_5_ENA(coher_status_host_reg, dest_base_5_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK) | (dest_base_5_ena << COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_6_ENA(coher_status_host_reg, dest_base_6_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK) | (dest_base_6_ena << COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_7_ENA(coher_status_host_reg, dest_base_7_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK) | (dest_base_7_ena << COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_RB_COLOR_INFO_ENA(coher_status_host_reg, rb_color_info_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK) | (rb_color_info_ena << COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_TC_ACTION_ENA(coher_status_host_reg, tc_action_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_TC_ACTION_ENA_MASK) | (tc_action_ena << COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_STATUS(coher_status_host_reg, status) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_STATUS_MASK) | (status << COHER_STATUS_HOST_STATUS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_status_host_t { + unsigned int matching_contexts : COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE; + unsigned int rb_copy_dest_base_ena : COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE; + unsigned int dest_base_0_ena : COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE; + unsigned int dest_base_1_ena : COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE; + unsigned int dest_base_2_ena : COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE; + unsigned int dest_base_3_ena : COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE; + unsigned int dest_base_4_ena : COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE; + unsigned int dest_base_5_ena : COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE; + unsigned int dest_base_6_ena : COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE; + unsigned int dest_base_7_ena : COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE; + unsigned int rb_color_info_ena : COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SIZE; + unsigned int : 7; + unsigned int tc_action_ena : COHER_STATUS_HOST_TC_ACTION_ENA_SIZE; + unsigned int : 5; + unsigned int status : COHER_STATUS_HOST_STATUS_SIZE; + } coher_status_host_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_status_host_t { + unsigned int status : COHER_STATUS_HOST_STATUS_SIZE; + unsigned int : 5; + unsigned int tc_action_ena : COHER_STATUS_HOST_TC_ACTION_ENA_SIZE; + unsigned int : 7; + unsigned int rb_color_info_ena : COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SIZE; + unsigned int dest_base_7_ena : COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE; + unsigned int dest_base_6_ena : COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE; + unsigned int dest_base_5_ena : COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE; + unsigned int dest_base_4_ena : COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE; + unsigned int dest_base_3_ena : COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE; + unsigned int dest_base_2_ena : COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE; + unsigned int dest_base_1_ena : COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE; + unsigned int dest_base_0_ena : COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE; + unsigned int rb_copy_dest_base_ena : COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE; + unsigned int matching_contexts : COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE; + } coher_status_host_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_status_host_t f; +} coher_status_host_u; + + +/* + * COHER_DEST_BASE_0 struct + */ + +#define COHER_DEST_BASE_0_DEST_BASE_0_SIZE 20 + +#define COHER_DEST_BASE_0_DEST_BASE_0_SHIFT 12 + +#define COHER_DEST_BASE_0_DEST_BASE_0_MASK 0xfffff000 + +#define COHER_DEST_BASE_0_MASK \ + (COHER_DEST_BASE_0_DEST_BASE_0_MASK) + +#define COHER_DEST_BASE_0(dest_base_0) \ + ((dest_base_0 << COHER_DEST_BASE_0_DEST_BASE_0_SHIFT)) + +#define COHER_DEST_BASE_0_GET_DEST_BASE_0(coher_dest_base_0) \ + ((coher_dest_base_0 & COHER_DEST_BASE_0_DEST_BASE_0_MASK) >> COHER_DEST_BASE_0_DEST_BASE_0_SHIFT) + +#define COHER_DEST_BASE_0_SET_DEST_BASE_0(coher_dest_base_0_reg, dest_base_0) \ + coher_dest_base_0_reg = (coher_dest_base_0_reg & ~COHER_DEST_BASE_0_DEST_BASE_0_MASK) | (dest_base_0 << COHER_DEST_BASE_0_DEST_BASE_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_0_t { + unsigned int : 12; + unsigned int dest_base_0 : COHER_DEST_BASE_0_DEST_BASE_0_SIZE; + } coher_dest_base_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_0_t { + unsigned int dest_base_0 : COHER_DEST_BASE_0_DEST_BASE_0_SIZE; + unsigned int : 12; + } coher_dest_base_0_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_0_t f; +} coher_dest_base_0_u; + + +/* + * COHER_DEST_BASE_1 struct + */ + +#define COHER_DEST_BASE_1_DEST_BASE_1_SIZE 20 + +#define COHER_DEST_BASE_1_DEST_BASE_1_SHIFT 12 + +#define COHER_DEST_BASE_1_DEST_BASE_1_MASK 0xfffff000 + +#define COHER_DEST_BASE_1_MASK \ + (COHER_DEST_BASE_1_DEST_BASE_1_MASK) + +#define COHER_DEST_BASE_1(dest_base_1) \ + ((dest_base_1 << COHER_DEST_BASE_1_DEST_BASE_1_SHIFT)) + +#define COHER_DEST_BASE_1_GET_DEST_BASE_1(coher_dest_base_1) \ + ((coher_dest_base_1 & COHER_DEST_BASE_1_DEST_BASE_1_MASK) >> COHER_DEST_BASE_1_DEST_BASE_1_SHIFT) + +#define COHER_DEST_BASE_1_SET_DEST_BASE_1(coher_dest_base_1_reg, dest_base_1) \ + coher_dest_base_1_reg = (coher_dest_base_1_reg & ~COHER_DEST_BASE_1_DEST_BASE_1_MASK) | (dest_base_1 << COHER_DEST_BASE_1_DEST_BASE_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_1_t { + unsigned int : 12; + unsigned int dest_base_1 : COHER_DEST_BASE_1_DEST_BASE_1_SIZE; + } coher_dest_base_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_1_t { + unsigned int dest_base_1 : COHER_DEST_BASE_1_DEST_BASE_1_SIZE; + unsigned int : 12; + } coher_dest_base_1_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_1_t f; +} coher_dest_base_1_u; + + +/* + * COHER_DEST_BASE_2 struct + */ + +#define COHER_DEST_BASE_2_DEST_BASE_2_SIZE 20 + +#define COHER_DEST_BASE_2_DEST_BASE_2_SHIFT 12 + +#define COHER_DEST_BASE_2_DEST_BASE_2_MASK 0xfffff000 + +#define COHER_DEST_BASE_2_MASK \ + (COHER_DEST_BASE_2_DEST_BASE_2_MASK) + +#define COHER_DEST_BASE_2(dest_base_2) \ + ((dest_base_2 << COHER_DEST_BASE_2_DEST_BASE_2_SHIFT)) + +#define COHER_DEST_BASE_2_GET_DEST_BASE_2(coher_dest_base_2) \ + ((coher_dest_base_2 & COHER_DEST_BASE_2_DEST_BASE_2_MASK) >> COHER_DEST_BASE_2_DEST_BASE_2_SHIFT) + +#define COHER_DEST_BASE_2_SET_DEST_BASE_2(coher_dest_base_2_reg, dest_base_2) \ + coher_dest_base_2_reg = (coher_dest_base_2_reg & ~COHER_DEST_BASE_2_DEST_BASE_2_MASK) | (dest_base_2 << COHER_DEST_BASE_2_DEST_BASE_2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_2_t { + unsigned int : 12; + unsigned int dest_base_2 : COHER_DEST_BASE_2_DEST_BASE_2_SIZE; + } coher_dest_base_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_2_t { + unsigned int dest_base_2 : COHER_DEST_BASE_2_DEST_BASE_2_SIZE; + unsigned int : 12; + } coher_dest_base_2_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_2_t f; +} coher_dest_base_2_u; + + +/* + * COHER_DEST_BASE_3 struct + */ + +#define COHER_DEST_BASE_3_DEST_BASE_3_SIZE 20 + +#define COHER_DEST_BASE_3_DEST_BASE_3_SHIFT 12 + +#define COHER_DEST_BASE_3_DEST_BASE_3_MASK 0xfffff000 + +#define COHER_DEST_BASE_3_MASK \ + (COHER_DEST_BASE_3_DEST_BASE_3_MASK) + +#define COHER_DEST_BASE_3(dest_base_3) \ + ((dest_base_3 << COHER_DEST_BASE_3_DEST_BASE_3_SHIFT)) + +#define COHER_DEST_BASE_3_GET_DEST_BASE_3(coher_dest_base_3) \ + ((coher_dest_base_3 & COHER_DEST_BASE_3_DEST_BASE_3_MASK) >> COHER_DEST_BASE_3_DEST_BASE_3_SHIFT) + +#define COHER_DEST_BASE_3_SET_DEST_BASE_3(coher_dest_base_3_reg, dest_base_3) \ + coher_dest_base_3_reg = (coher_dest_base_3_reg & ~COHER_DEST_BASE_3_DEST_BASE_3_MASK) | (dest_base_3 << COHER_DEST_BASE_3_DEST_BASE_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_3_t { + unsigned int : 12; + unsigned int dest_base_3 : COHER_DEST_BASE_3_DEST_BASE_3_SIZE; + } coher_dest_base_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_3_t { + unsigned int dest_base_3 : COHER_DEST_BASE_3_DEST_BASE_3_SIZE; + unsigned int : 12; + } coher_dest_base_3_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_3_t f; +} coher_dest_base_3_u; + + +/* + * COHER_DEST_BASE_4 struct + */ + +#define COHER_DEST_BASE_4_DEST_BASE_4_SIZE 20 + +#define COHER_DEST_BASE_4_DEST_BASE_4_SHIFT 12 + +#define COHER_DEST_BASE_4_DEST_BASE_4_MASK 0xfffff000 + +#define COHER_DEST_BASE_4_MASK \ + (COHER_DEST_BASE_4_DEST_BASE_4_MASK) + +#define COHER_DEST_BASE_4(dest_base_4) \ + ((dest_base_4 << COHER_DEST_BASE_4_DEST_BASE_4_SHIFT)) + +#define COHER_DEST_BASE_4_GET_DEST_BASE_4(coher_dest_base_4) \ + ((coher_dest_base_4 & COHER_DEST_BASE_4_DEST_BASE_4_MASK) >> COHER_DEST_BASE_4_DEST_BASE_4_SHIFT) + +#define COHER_DEST_BASE_4_SET_DEST_BASE_4(coher_dest_base_4_reg, dest_base_4) \ + coher_dest_base_4_reg = (coher_dest_base_4_reg & ~COHER_DEST_BASE_4_DEST_BASE_4_MASK) | (dest_base_4 << COHER_DEST_BASE_4_DEST_BASE_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_4_t { + unsigned int : 12; + unsigned int dest_base_4 : COHER_DEST_BASE_4_DEST_BASE_4_SIZE; + } coher_dest_base_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_4_t { + unsigned int dest_base_4 : COHER_DEST_BASE_4_DEST_BASE_4_SIZE; + unsigned int : 12; + } coher_dest_base_4_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_4_t f; +} coher_dest_base_4_u; + + +/* + * COHER_DEST_BASE_5 struct + */ + +#define COHER_DEST_BASE_5_DEST_BASE_5_SIZE 20 + +#define COHER_DEST_BASE_5_DEST_BASE_5_SHIFT 12 + +#define COHER_DEST_BASE_5_DEST_BASE_5_MASK 0xfffff000 + +#define COHER_DEST_BASE_5_MASK \ + (COHER_DEST_BASE_5_DEST_BASE_5_MASK) + +#define COHER_DEST_BASE_5(dest_base_5) \ + ((dest_base_5 << COHER_DEST_BASE_5_DEST_BASE_5_SHIFT)) + +#define COHER_DEST_BASE_5_GET_DEST_BASE_5(coher_dest_base_5) \ + ((coher_dest_base_5 & COHER_DEST_BASE_5_DEST_BASE_5_MASK) >> COHER_DEST_BASE_5_DEST_BASE_5_SHIFT) + +#define COHER_DEST_BASE_5_SET_DEST_BASE_5(coher_dest_base_5_reg, dest_base_5) \ + coher_dest_base_5_reg = (coher_dest_base_5_reg & ~COHER_DEST_BASE_5_DEST_BASE_5_MASK) | (dest_base_5 << COHER_DEST_BASE_5_DEST_BASE_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_5_t { + unsigned int : 12; + unsigned int dest_base_5 : COHER_DEST_BASE_5_DEST_BASE_5_SIZE; + } coher_dest_base_5_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_5_t { + unsigned int dest_base_5 : COHER_DEST_BASE_5_DEST_BASE_5_SIZE; + unsigned int : 12; + } coher_dest_base_5_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_5_t f; +} coher_dest_base_5_u; + + +/* + * COHER_DEST_BASE_6 struct + */ + +#define COHER_DEST_BASE_6_DEST_BASE_6_SIZE 20 + +#define COHER_DEST_BASE_6_DEST_BASE_6_SHIFT 12 + +#define COHER_DEST_BASE_6_DEST_BASE_6_MASK 0xfffff000 + +#define COHER_DEST_BASE_6_MASK \ + (COHER_DEST_BASE_6_DEST_BASE_6_MASK) + +#define COHER_DEST_BASE_6(dest_base_6) \ + ((dest_base_6 << COHER_DEST_BASE_6_DEST_BASE_6_SHIFT)) + +#define COHER_DEST_BASE_6_GET_DEST_BASE_6(coher_dest_base_6) \ + ((coher_dest_base_6 & COHER_DEST_BASE_6_DEST_BASE_6_MASK) >> COHER_DEST_BASE_6_DEST_BASE_6_SHIFT) + +#define COHER_DEST_BASE_6_SET_DEST_BASE_6(coher_dest_base_6_reg, dest_base_6) \ + coher_dest_base_6_reg = (coher_dest_base_6_reg & ~COHER_DEST_BASE_6_DEST_BASE_6_MASK) | (dest_base_6 << COHER_DEST_BASE_6_DEST_BASE_6_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_6_t { + unsigned int : 12; + unsigned int dest_base_6 : COHER_DEST_BASE_6_DEST_BASE_6_SIZE; + } coher_dest_base_6_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_6_t { + unsigned int dest_base_6 : COHER_DEST_BASE_6_DEST_BASE_6_SIZE; + unsigned int : 12; + } coher_dest_base_6_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_6_t f; +} coher_dest_base_6_u; + + +/* + * COHER_DEST_BASE_7 struct + */ + +#define COHER_DEST_BASE_7_DEST_BASE_7_SIZE 20 + +#define COHER_DEST_BASE_7_DEST_BASE_7_SHIFT 12 + +#define COHER_DEST_BASE_7_DEST_BASE_7_MASK 0xfffff000 + +#define COHER_DEST_BASE_7_MASK \ + (COHER_DEST_BASE_7_DEST_BASE_7_MASK) + +#define COHER_DEST_BASE_7(dest_base_7) \ + ((dest_base_7 << COHER_DEST_BASE_7_DEST_BASE_7_SHIFT)) + +#define COHER_DEST_BASE_7_GET_DEST_BASE_7(coher_dest_base_7) \ + ((coher_dest_base_7 & COHER_DEST_BASE_7_DEST_BASE_7_MASK) >> COHER_DEST_BASE_7_DEST_BASE_7_SHIFT) + +#define COHER_DEST_BASE_7_SET_DEST_BASE_7(coher_dest_base_7_reg, dest_base_7) \ + coher_dest_base_7_reg = (coher_dest_base_7_reg & ~COHER_DEST_BASE_7_DEST_BASE_7_MASK) | (dest_base_7 << COHER_DEST_BASE_7_DEST_BASE_7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_7_t { + unsigned int : 12; + unsigned int dest_base_7 : COHER_DEST_BASE_7_DEST_BASE_7_SIZE; + } coher_dest_base_7_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_7_t { + unsigned int dest_base_7 : COHER_DEST_BASE_7_DEST_BASE_7_SIZE; + unsigned int : 12; + } coher_dest_base_7_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_7_t f; +} coher_dest_base_7_u; + + +#endif + + +#if !defined (_RBBM_FIDDLE_H) +#define _RBBM_FIDDLE_H + +/***************************************************************************************************************** + * + * rbbm_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * WAIT_UNTIL struct + */ + +#define WAIT_UNTIL_WAIT_RE_VSYNC_SIZE 1 +#define WAIT_UNTIL_WAIT_FE_VSYNC_SIZE 1 +#define WAIT_UNTIL_WAIT_VSYNC_SIZE 1 +#define WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE 1 +#define WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE 1 +#define WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE 1 +#define WAIT_UNTIL_WAIT_CMDFIFO_SIZE 1 +#define WAIT_UNTIL_WAIT_2D_IDLE_SIZE 1 +#define WAIT_UNTIL_WAIT_3D_IDLE_SIZE 1 +#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE 1 +#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE 1 +#define WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE 4 + +#define WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT 1 +#define WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT 2 +#define WAIT_UNTIL_WAIT_VSYNC_SHIFT 3 +#define WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT 4 +#define WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT 5 +#define WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT 6 +#define WAIT_UNTIL_WAIT_CMDFIFO_SHIFT 10 +#define WAIT_UNTIL_WAIT_2D_IDLE_SHIFT 14 +#define WAIT_UNTIL_WAIT_3D_IDLE_SHIFT 15 +#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT 16 +#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT 17 +#define WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT 20 + +#define WAIT_UNTIL_WAIT_RE_VSYNC_MASK 0x00000002 +#define WAIT_UNTIL_WAIT_FE_VSYNC_MASK 0x00000004 +#define WAIT_UNTIL_WAIT_VSYNC_MASK 0x00000008 +#define WAIT_UNTIL_WAIT_DSPLY_ID0_MASK 0x00000010 +#define WAIT_UNTIL_WAIT_DSPLY_ID1_MASK 0x00000020 +#define WAIT_UNTIL_WAIT_DSPLY_ID2_MASK 0x00000040 +#define WAIT_UNTIL_WAIT_CMDFIFO_MASK 0x00000400 +#define WAIT_UNTIL_WAIT_2D_IDLE_MASK 0x00004000 +#define WAIT_UNTIL_WAIT_3D_IDLE_MASK 0x00008000 +#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK 0x00010000 +#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK 0x00020000 +#define WAIT_UNTIL_CMDFIFO_ENTRIES_MASK 0x00f00000 + +#define WAIT_UNTIL_MASK \ + (WAIT_UNTIL_WAIT_RE_VSYNC_MASK | \ + WAIT_UNTIL_WAIT_FE_VSYNC_MASK | \ + WAIT_UNTIL_WAIT_VSYNC_MASK | \ + WAIT_UNTIL_WAIT_DSPLY_ID0_MASK | \ + WAIT_UNTIL_WAIT_DSPLY_ID1_MASK | \ + WAIT_UNTIL_WAIT_DSPLY_ID2_MASK | \ + WAIT_UNTIL_WAIT_CMDFIFO_MASK | \ + WAIT_UNTIL_WAIT_2D_IDLE_MASK | \ + WAIT_UNTIL_WAIT_3D_IDLE_MASK | \ + WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK | \ + WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK | \ + WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) + +#define WAIT_UNTIL(wait_re_vsync, wait_fe_vsync, wait_vsync, wait_dsply_id0, wait_dsply_id1, wait_dsply_id2, wait_cmdfifo, wait_2d_idle, wait_3d_idle, wait_2d_idleclean, wait_3d_idleclean, cmdfifo_entries) \ + ((wait_re_vsync << WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT) | \ + (wait_fe_vsync << WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT) | \ + (wait_vsync << WAIT_UNTIL_WAIT_VSYNC_SHIFT) | \ + (wait_dsply_id0 << WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT) | \ + (wait_dsply_id1 << WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT) | \ + (wait_dsply_id2 << WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT) | \ + (wait_cmdfifo << WAIT_UNTIL_WAIT_CMDFIFO_SHIFT) | \ + (wait_2d_idle << WAIT_UNTIL_WAIT_2D_IDLE_SHIFT) | \ + (wait_3d_idle << WAIT_UNTIL_WAIT_3D_IDLE_SHIFT) | \ + (wait_2d_idleclean << WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT) | \ + (wait_3d_idleclean << WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT) | \ + (cmdfifo_entries << WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT)) + +#define WAIT_UNTIL_GET_WAIT_RE_VSYNC(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_RE_VSYNC_MASK) >> WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT) +#define WAIT_UNTIL_GET_WAIT_FE_VSYNC(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_FE_VSYNC_MASK) >> WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT) +#define WAIT_UNTIL_GET_WAIT_VSYNC(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_VSYNC_MASK) >> WAIT_UNTIL_WAIT_VSYNC_SHIFT) +#define WAIT_UNTIL_GET_WAIT_DSPLY_ID0(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID0_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT) +#define WAIT_UNTIL_GET_WAIT_DSPLY_ID1(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID1_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT) +#define WAIT_UNTIL_GET_WAIT_DSPLY_ID2(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID2_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT) +#define WAIT_UNTIL_GET_WAIT_CMDFIFO(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_CMDFIFO_MASK) >> WAIT_UNTIL_WAIT_CMDFIFO_SHIFT) +#define WAIT_UNTIL_GET_WAIT_2D_IDLE(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_2D_IDLE_MASK) >> WAIT_UNTIL_WAIT_2D_IDLE_SHIFT) +#define WAIT_UNTIL_GET_WAIT_3D_IDLE(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_3D_IDLE_MASK) >> WAIT_UNTIL_WAIT_3D_IDLE_SHIFT) +#define WAIT_UNTIL_GET_WAIT_2D_IDLECLEAN(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK) >> WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT) +#define WAIT_UNTIL_GET_WAIT_3D_IDLECLEAN(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK) >> WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT) +#define WAIT_UNTIL_GET_CMDFIFO_ENTRIES(wait_until) \ + ((wait_until & WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) >> WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT) + +#define WAIT_UNTIL_SET_WAIT_RE_VSYNC(wait_until_reg, wait_re_vsync) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_RE_VSYNC_MASK) | (wait_re_vsync << WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT) +#define WAIT_UNTIL_SET_WAIT_FE_VSYNC(wait_until_reg, wait_fe_vsync) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_FE_VSYNC_MASK) | (wait_fe_vsync << WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT) +#define WAIT_UNTIL_SET_WAIT_VSYNC(wait_until_reg, wait_vsync) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_VSYNC_MASK) | (wait_vsync << WAIT_UNTIL_WAIT_VSYNC_SHIFT) +#define WAIT_UNTIL_SET_WAIT_DSPLY_ID0(wait_until_reg, wait_dsply_id0) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID0_MASK) | (wait_dsply_id0 << WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT) +#define WAIT_UNTIL_SET_WAIT_DSPLY_ID1(wait_until_reg, wait_dsply_id1) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID1_MASK) | (wait_dsply_id1 << WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT) +#define WAIT_UNTIL_SET_WAIT_DSPLY_ID2(wait_until_reg, wait_dsply_id2) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID2_MASK) | (wait_dsply_id2 << WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT) +#define WAIT_UNTIL_SET_WAIT_CMDFIFO(wait_until_reg, wait_cmdfifo) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_CMDFIFO_MASK) | (wait_cmdfifo << WAIT_UNTIL_WAIT_CMDFIFO_SHIFT) +#define WAIT_UNTIL_SET_WAIT_2D_IDLE(wait_until_reg, wait_2d_idle) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_2D_IDLE_MASK) | (wait_2d_idle << WAIT_UNTIL_WAIT_2D_IDLE_SHIFT) +#define WAIT_UNTIL_SET_WAIT_3D_IDLE(wait_until_reg, wait_3d_idle) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_3D_IDLE_MASK) | (wait_3d_idle << WAIT_UNTIL_WAIT_3D_IDLE_SHIFT) +#define WAIT_UNTIL_SET_WAIT_2D_IDLECLEAN(wait_until_reg, wait_2d_idleclean) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK) | (wait_2d_idleclean << WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT) +#define WAIT_UNTIL_SET_WAIT_3D_IDLECLEAN(wait_until_reg, wait_3d_idleclean) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK) | (wait_3d_idleclean << WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT) +#define WAIT_UNTIL_SET_CMDFIFO_ENTRIES(wait_until_reg, cmdfifo_entries) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) | (cmdfifo_entries << WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _wait_until_t { + unsigned int : 1; + unsigned int wait_re_vsync : WAIT_UNTIL_WAIT_RE_VSYNC_SIZE; + unsigned int wait_fe_vsync : WAIT_UNTIL_WAIT_FE_VSYNC_SIZE; + unsigned int wait_vsync : WAIT_UNTIL_WAIT_VSYNC_SIZE; + unsigned int wait_dsply_id0 : WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE; + unsigned int wait_dsply_id1 : WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE; + unsigned int wait_dsply_id2 : WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE; + unsigned int : 3; + unsigned int wait_cmdfifo : WAIT_UNTIL_WAIT_CMDFIFO_SIZE; + unsigned int : 3; + unsigned int wait_2d_idle : WAIT_UNTIL_WAIT_2D_IDLE_SIZE; + unsigned int wait_3d_idle : WAIT_UNTIL_WAIT_3D_IDLE_SIZE; + unsigned int wait_2d_idleclean : WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE; + unsigned int wait_3d_idleclean : WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE; + unsigned int : 2; + unsigned int cmdfifo_entries : WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE; + unsigned int : 8; + } wait_until_t; + +#else // !BIGENDIAN_OS + + typedef struct _wait_until_t { + unsigned int : 8; + unsigned int cmdfifo_entries : WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE; + unsigned int : 2; + unsigned int wait_3d_idleclean : WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE; + unsigned int wait_2d_idleclean : WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE; + unsigned int wait_3d_idle : WAIT_UNTIL_WAIT_3D_IDLE_SIZE; + unsigned int wait_2d_idle : WAIT_UNTIL_WAIT_2D_IDLE_SIZE; + unsigned int : 3; + unsigned int wait_cmdfifo : WAIT_UNTIL_WAIT_CMDFIFO_SIZE; + unsigned int : 3; + unsigned int wait_dsply_id2 : WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE; + unsigned int wait_dsply_id1 : WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE; + unsigned int wait_dsply_id0 : WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE; + unsigned int wait_vsync : WAIT_UNTIL_WAIT_VSYNC_SIZE; + unsigned int wait_fe_vsync : WAIT_UNTIL_WAIT_FE_VSYNC_SIZE; + unsigned int wait_re_vsync : WAIT_UNTIL_WAIT_RE_VSYNC_SIZE; + unsigned int : 1; + } wait_until_t; + +#endif + +typedef union { + unsigned int val : 32; + wait_until_t f; +} wait_until_u; + + +/* + * RBBM_ISYNC_CNTL struct + */ + +#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE 1 +#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE 1 + +#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT 4 +#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT 5 + +#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK 0x00000010 +#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK 0x00000020 + +#define RBBM_ISYNC_CNTL_MASK \ + (RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK | \ + RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) + +#define RBBM_ISYNC_CNTL(isync_wait_idlegui, isync_cpscratch_idlegui) \ + ((isync_wait_idlegui << RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT) | \ + (isync_cpscratch_idlegui << RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT)) + +#define RBBM_ISYNC_CNTL_GET_ISYNC_WAIT_IDLEGUI(rbbm_isync_cntl) \ + ((rbbm_isync_cntl & RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK) >> RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT) +#define RBBM_ISYNC_CNTL_GET_ISYNC_CPSCRATCH_IDLEGUI(rbbm_isync_cntl) \ + ((rbbm_isync_cntl & RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) >> RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT) + +#define RBBM_ISYNC_CNTL_SET_ISYNC_WAIT_IDLEGUI(rbbm_isync_cntl_reg, isync_wait_idlegui) \ + rbbm_isync_cntl_reg = (rbbm_isync_cntl_reg & ~RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK) | (isync_wait_idlegui << RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT) +#define RBBM_ISYNC_CNTL_SET_ISYNC_CPSCRATCH_IDLEGUI(rbbm_isync_cntl_reg, isync_cpscratch_idlegui) \ + rbbm_isync_cntl_reg = (rbbm_isync_cntl_reg & ~RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) | (isync_cpscratch_idlegui << RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_isync_cntl_t { + unsigned int : 4; + unsigned int isync_wait_idlegui : RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE; + unsigned int isync_cpscratch_idlegui : RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE; + unsigned int : 26; + } rbbm_isync_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_isync_cntl_t { + unsigned int : 26; + unsigned int isync_cpscratch_idlegui : RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE; + unsigned int isync_wait_idlegui : RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE; + unsigned int : 4; + } rbbm_isync_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_isync_cntl_t f; +} rbbm_isync_cntl_u; + + +/* + * RBBM_STATUS struct + */ + +#define RBBM_STATUS_CMDFIFO_AVAIL_SIZE 5 +#define RBBM_STATUS_TC_BUSY_SIZE 1 +#define RBBM_STATUS_HIRQ_PENDING_SIZE 1 +#define RBBM_STATUS_CPRQ_PENDING_SIZE 1 +#define RBBM_STATUS_CFRQ_PENDING_SIZE 1 +#define RBBM_STATUS_PFRQ_PENDING_SIZE 1 +#define RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE 1 +#define RBBM_STATUS_RBBM_WU_BUSY_SIZE 1 +#define RBBM_STATUS_CP_NRT_BUSY_SIZE 1 +#define RBBM_STATUS_MH_BUSY_SIZE 1 +#define RBBM_STATUS_MH_COHERENCY_BUSY_SIZE 1 +#define RBBM_STATUS_SX_BUSY_SIZE 1 +#define RBBM_STATUS_TPC_BUSY_SIZE 1 +#define RBBM_STATUS_SC_CNTX_BUSY_SIZE 1 +#define RBBM_STATUS_PA_BUSY_SIZE 1 +#define RBBM_STATUS_VGT_BUSY_SIZE 1 +#define RBBM_STATUS_SQ_CNTX17_BUSY_SIZE 1 +#define RBBM_STATUS_SQ_CNTX0_BUSY_SIZE 1 +#define RBBM_STATUS_RB_CNTX_BUSY_SIZE 1 +#define RBBM_STATUS_GUI_ACTIVE_SIZE 1 + +#define RBBM_STATUS_CMDFIFO_AVAIL_SHIFT 0 +#define RBBM_STATUS_TC_BUSY_SHIFT 5 +#define RBBM_STATUS_HIRQ_PENDING_SHIFT 8 +#define RBBM_STATUS_CPRQ_PENDING_SHIFT 9 +#define RBBM_STATUS_CFRQ_PENDING_SHIFT 10 +#define RBBM_STATUS_PFRQ_PENDING_SHIFT 11 +#define RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT 12 +#define RBBM_STATUS_RBBM_WU_BUSY_SHIFT 14 +#define RBBM_STATUS_CP_NRT_BUSY_SHIFT 16 +#define RBBM_STATUS_MH_BUSY_SHIFT 18 +#define RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT 19 +#define RBBM_STATUS_SX_BUSY_SHIFT 21 +#define RBBM_STATUS_TPC_BUSY_SHIFT 22 +#define RBBM_STATUS_SC_CNTX_BUSY_SHIFT 24 +#define RBBM_STATUS_PA_BUSY_SHIFT 25 +#define RBBM_STATUS_VGT_BUSY_SHIFT 26 +#define RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT 27 +#define RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT 28 +#define RBBM_STATUS_RB_CNTX_BUSY_SHIFT 30 +#define RBBM_STATUS_GUI_ACTIVE_SHIFT 31 + +#define RBBM_STATUS_CMDFIFO_AVAIL_MASK 0x0000001f +#define RBBM_STATUS_TC_BUSY_MASK 0x00000020 +#define RBBM_STATUS_HIRQ_PENDING_MASK 0x00000100 +#define RBBM_STATUS_CPRQ_PENDING_MASK 0x00000200 +#define RBBM_STATUS_CFRQ_PENDING_MASK 0x00000400 +#define RBBM_STATUS_PFRQ_PENDING_MASK 0x00000800 +#define RBBM_STATUS_VGT_BUSY_NO_DMA_MASK 0x00001000 +#define RBBM_STATUS_RBBM_WU_BUSY_MASK 0x00004000 +#define RBBM_STATUS_CP_NRT_BUSY_MASK 0x00010000 +#define RBBM_STATUS_MH_BUSY_MASK 0x00040000 +#define RBBM_STATUS_MH_COHERENCY_BUSY_MASK 0x00080000 +#define RBBM_STATUS_SX_BUSY_MASK 0x00200000 +#define RBBM_STATUS_TPC_BUSY_MASK 0x00400000 +#define RBBM_STATUS_SC_CNTX_BUSY_MASK 0x01000000 +#define RBBM_STATUS_PA_BUSY_MASK 0x02000000 +#define RBBM_STATUS_VGT_BUSY_MASK 0x04000000 +#define RBBM_STATUS_SQ_CNTX17_BUSY_MASK 0x08000000 +#define RBBM_STATUS_SQ_CNTX0_BUSY_MASK 0x10000000 +#define RBBM_STATUS_RB_CNTX_BUSY_MASK 0x40000000 +#define RBBM_STATUS_GUI_ACTIVE_MASK 0x80000000 + +#define RBBM_STATUS_MASK \ + (RBBM_STATUS_CMDFIFO_AVAIL_MASK | \ + RBBM_STATUS_TC_BUSY_MASK | \ + RBBM_STATUS_HIRQ_PENDING_MASK | \ + RBBM_STATUS_CPRQ_PENDING_MASK | \ + RBBM_STATUS_CFRQ_PENDING_MASK | \ + RBBM_STATUS_PFRQ_PENDING_MASK | \ + RBBM_STATUS_VGT_BUSY_NO_DMA_MASK | \ + RBBM_STATUS_RBBM_WU_BUSY_MASK | \ + RBBM_STATUS_CP_NRT_BUSY_MASK | \ + RBBM_STATUS_MH_BUSY_MASK | \ + RBBM_STATUS_MH_COHERENCY_BUSY_MASK | \ + RBBM_STATUS_SX_BUSY_MASK | \ + RBBM_STATUS_TPC_BUSY_MASK | \ + RBBM_STATUS_SC_CNTX_BUSY_MASK | \ + RBBM_STATUS_PA_BUSY_MASK | \ + RBBM_STATUS_VGT_BUSY_MASK | \ + RBBM_STATUS_SQ_CNTX17_BUSY_MASK | \ + RBBM_STATUS_SQ_CNTX0_BUSY_MASK | \ + RBBM_STATUS_RB_CNTX_BUSY_MASK | \ + RBBM_STATUS_GUI_ACTIVE_MASK) + +#define RBBM_STATUS(cmdfifo_avail, tc_busy, hirq_pending, cprq_pending, cfrq_pending, pfrq_pending, vgt_busy_no_dma, rbbm_wu_busy, cp_nrt_busy, mh_busy, mh_coherency_busy, sx_busy, tpc_busy, sc_cntx_busy, pa_busy, vgt_busy, sq_cntx17_busy, sq_cntx0_busy, rb_cntx_busy, gui_active) \ + ((cmdfifo_avail << RBBM_STATUS_CMDFIFO_AVAIL_SHIFT) | \ + (tc_busy << RBBM_STATUS_TC_BUSY_SHIFT) | \ + (hirq_pending << RBBM_STATUS_HIRQ_PENDING_SHIFT) | \ + (cprq_pending << RBBM_STATUS_CPRQ_PENDING_SHIFT) | \ + (cfrq_pending << RBBM_STATUS_CFRQ_PENDING_SHIFT) | \ + (pfrq_pending << RBBM_STATUS_PFRQ_PENDING_SHIFT) | \ + (vgt_busy_no_dma << RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT) | \ + (rbbm_wu_busy << RBBM_STATUS_RBBM_WU_BUSY_SHIFT) | \ + (cp_nrt_busy << RBBM_STATUS_CP_NRT_BUSY_SHIFT) | \ + (mh_busy << RBBM_STATUS_MH_BUSY_SHIFT) | \ + (mh_coherency_busy << RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT) | \ + (sx_busy << RBBM_STATUS_SX_BUSY_SHIFT) | \ + (tpc_busy << RBBM_STATUS_TPC_BUSY_SHIFT) | \ + (sc_cntx_busy << RBBM_STATUS_SC_CNTX_BUSY_SHIFT) | \ + (pa_busy << RBBM_STATUS_PA_BUSY_SHIFT) | \ + (vgt_busy << RBBM_STATUS_VGT_BUSY_SHIFT) | \ + (sq_cntx17_busy << RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT) | \ + (sq_cntx0_busy << RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT) | \ + (rb_cntx_busy << RBBM_STATUS_RB_CNTX_BUSY_SHIFT) | \ + (gui_active << RBBM_STATUS_GUI_ACTIVE_SHIFT)) + +#define RBBM_STATUS_GET_CMDFIFO_AVAIL(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_CMDFIFO_AVAIL_MASK) >> RBBM_STATUS_CMDFIFO_AVAIL_SHIFT) +#define RBBM_STATUS_GET_TC_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_TC_BUSY_MASK) >> RBBM_STATUS_TC_BUSY_SHIFT) +#define RBBM_STATUS_GET_HIRQ_PENDING(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_HIRQ_PENDING_MASK) >> RBBM_STATUS_HIRQ_PENDING_SHIFT) +#define RBBM_STATUS_GET_CPRQ_PENDING(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_CPRQ_PENDING_MASK) >> RBBM_STATUS_CPRQ_PENDING_SHIFT) +#define RBBM_STATUS_GET_CFRQ_PENDING(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_CFRQ_PENDING_MASK) >> RBBM_STATUS_CFRQ_PENDING_SHIFT) +#define RBBM_STATUS_GET_PFRQ_PENDING(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_PFRQ_PENDING_MASK) >> RBBM_STATUS_PFRQ_PENDING_SHIFT) +#define RBBM_STATUS_GET_VGT_BUSY_NO_DMA(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_VGT_BUSY_NO_DMA_MASK) >> RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT) +#define RBBM_STATUS_GET_RBBM_WU_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_RBBM_WU_BUSY_MASK) >> RBBM_STATUS_RBBM_WU_BUSY_SHIFT) +#define RBBM_STATUS_GET_CP_NRT_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_CP_NRT_BUSY_MASK) >> RBBM_STATUS_CP_NRT_BUSY_SHIFT) +#define RBBM_STATUS_GET_MH_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_MH_BUSY_MASK) >> RBBM_STATUS_MH_BUSY_SHIFT) +#define RBBM_STATUS_GET_MH_COHERENCY_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_MH_COHERENCY_BUSY_MASK) >> RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT) +#define RBBM_STATUS_GET_SX_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_SX_BUSY_MASK) >> RBBM_STATUS_SX_BUSY_SHIFT) +#define RBBM_STATUS_GET_TPC_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_TPC_BUSY_MASK) >> RBBM_STATUS_TPC_BUSY_SHIFT) +#define RBBM_STATUS_GET_SC_CNTX_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_SC_CNTX_BUSY_MASK) >> RBBM_STATUS_SC_CNTX_BUSY_SHIFT) +#define RBBM_STATUS_GET_PA_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_PA_BUSY_MASK) >> RBBM_STATUS_PA_BUSY_SHIFT) +#define RBBM_STATUS_GET_VGT_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_VGT_BUSY_MASK) >> RBBM_STATUS_VGT_BUSY_SHIFT) +#define RBBM_STATUS_GET_SQ_CNTX17_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_SQ_CNTX17_BUSY_MASK) >> RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT) +#define RBBM_STATUS_GET_SQ_CNTX0_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_SQ_CNTX0_BUSY_MASK) >> RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT) +#define RBBM_STATUS_GET_RB_CNTX_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_RB_CNTX_BUSY_MASK) >> RBBM_STATUS_RB_CNTX_BUSY_SHIFT) +#define RBBM_STATUS_GET_GUI_ACTIVE(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_GUI_ACTIVE_MASK) >> RBBM_STATUS_GUI_ACTIVE_SHIFT) + +#define RBBM_STATUS_SET_CMDFIFO_AVAIL(rbbm_status_reg, cmdfifo_avail) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CMDFIFO_AVAIL_MASK) | (cmdfifo_avail << RBBM_STATUS_CMDFIFO_AVAIL_SHIFT) +#define RBBM_STATUS_SET_TC_BUSY(rbbm_status_reg, tc_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_TC_BUSY_MASK) | (tc_busy << RBBM_STATUS_TC_BUSY_SHIFT) +#define RBBM_STATUS_SET_HIRQ_PENDING(rbbm_status_reg, hirq_pending) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_HIRQ_PENDING_MASK) | (hirq_pending << RBBM_STATUS_HIRQ_PENDING_SHIFT) +#define RBBM_STATUS_SET_CPRQ_PENDING(rbbm_status_reg, cprq_pending) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CPRQ_PENDING_MASK) | (cprq_pending << RBBM_STATUS_CPRQ_PENDING_SHIFT) +#define RBBM_STATUS_SET_CFRQ_PENDING(rbbm_status_reg, cfrq_pending) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CFRQ_PENDING_MASK) | (cfrq_pending << RBBM_STATUS_CFRQ_PENDING_SHIFT) +#define RBBM_STATUS_SET_PFRQ_PENDING(rbbm_status_reg, pfrq_pending) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_PFRQ_PENDING_MASK) | (pfrq_pending << RBBM_STATUS_PFRQ_PENDING_SHIFT) +#define RBBM_STATUS_SET_VGT_BUSY_NO_DMA(rbbm_status_reg, vgt_busy_no_dma) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_VGT_BUSY_NO_DMA_MASK) | (vgt_busy_no_dma << RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT) +#define RBBM_STATUS_SET_RBBM_WU_BUSY(rbbm_status_reg, rbbm_wu_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_RBBM_WU_BUSY_MASK) | (rbbm_wu_busy << RBBM_STATUS_RBBM_WU_BUSY_SHIFT) +#define RBBM_STATUS_SET_CP_NRT_BUSY(rbbm_status_reg, cp_nrt_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CP_NRT_BUSY_MASK) | (cp_nrt_busy << RBBM_STATUS_CP_NRT_BUSY_SHIFT) +#define RBBM_STATUS_SET_MH_BUSY(rbbm_status_reg, mh_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_MH_BUSY_MASK) | (mh_busy << RBBM_STATUS_MH_BUSY_SHIFT) +#define RBBM_STATUS_SET_MH_COHERENCY_BUSY(rbbm_status_reg, mh_coherency_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_MH_COHERENCY_BUSY_MASK) | (mh_coherency_busy << RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT) +#define RBBM_STATUS_SET_SX_BUSY(rbbm_status_reg, sx_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SX_BUSY_MASK) | (sx_busy << RBBM_STATUS_SX_BUSY_SHIFT) +#define RBBM_STATUS_SET_TPC_BUSY(rbbm_status_reg, tpc_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_TPC_BUSY_MASK) | (tpc_busy << RBBM_STATUS_TPC_BUSY_SHIFT) +#define RBBM_STATUS_SET_SC_CNTX_BUSY(rbbm_status_reg, sc_cntx_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SC_CNTX_BUSY_MASK) | (sc_cntx_busy << RBBM_STATUS_SC_CNTX_BUSY_SHIFT) +#define RBBM_STATUS_SET_PA_BUSY(rbbm_status_reg, pa_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_PA_BUSY_MASK) | (pa_busy << RBBM_STATUS_PA_BUSY_SHIFT) +#define RBBM_STATUS_SET_VGT_BUSY(rbbm_status_reg, vgt_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_VGT_BUSY_MASK) | (vgt_busy << RBBM_STATUS_VGT_BUSY_SHIFT) +#define RBBM_STATUS_SET_SQ_CNTX17_BUSY(rbbm_status_reg, sq_cntx17_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SQ_CNTX17_BUSY_MASK) | (sq_cntx17_busy << RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT) +#define RBBM_STATUS_SET_SQ_CNTX0_BUSY(rbbm_status_reg, sq_cntx0_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SQ_CNTX0_BUSY_MASK) | (sq_cntx0_busy << RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT) +#define RBBM_STATUS_SET_RB_CNTX_BUSY(rbbm_status_reg, rb_cntx_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_RB_CNTX_BUSY_MASK) | (rb_cntx_busy << RBBM_STATUS_RB_CNTX_BUSY_SHIFT) +#define RBBM_STATUS_SET_GUI_ACTIVE(rbbm_status_reg, gui_active) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_GUI_ACTIVE_MASK) | (gui_active << RBBM_STATUS_GUI_ACTIVE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_status_t { + unsigned int cmdfifo_avail : RBBM_STATUS_CMDFIFO_AVAIL_SIZE; + unsigned int tc_busy : RBBM_STATUS_TC_BUSY_SIZE; + unsigned int : 2; + unsigned int hirq_pending : RBBM_STATUS_HIRQ_PENDING_SIZE; + unsigned int cprq_pending : RBBM_STATUS_CPRQ_PENDING_SIZE; + unsigned int cfrq_pending : RBBM_STATUS_CFRQ_PENDING_SIZE; + unsigned int pfrq_pending : RBBM_STATUS_PFRQ_PENDING_SIZE; + unsigned int vgt_busy_no_dma : RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE; + unsigned int : 1; + unsigned int rbbm_wu_busy : RBBM_STATUS_RBBM_WU_BUSY_SIZE; + unsigned int : 1; + unsigned int cp_nrt_busy : RBBM_STATUS_CP_NRT_BUSY_SIZE; + unsigned int : 1; + unsigned int mh_busy : RBBM_STATUS_MH_BUSY_SIZE; + unsigned int mh_coherency_busy : RBBM_STATUS_MH_COHERENCY_BUSY_SIZE; + unsigned int : 1; + unsigned int sx_busy : RBBM_STATUS_SX_BUSY_SIZE; + unsigned int tpc_busy : RBBM_STATUS_TPC_BUSY_SIZE; + unsigned int : 1; + unsigned int sc_cntx_busy : RBBM_STATUS_SC_CNTX_BUSY_SIZE; + unsigned int pa_busy : RBBM_STATUS_PA_BUSY_SIZE; + unsigned int vgt_busy : RBBM_STATUS_VGT_BUSY_SIZE; + unsigned int sq_cntx17_busy : RBBM_STATUS_SQ_CNTX17_BUSY_SIZE; + unsigned int sq_cntx0_busy : RBBM_STATUS_SQ_CNTX0_BUSY_SIZE; + unsigned int : 1; + unsigned int rb_cntx_busy : RBBM_STATUS_RB_CNTX_BUSY_SIZE; + unsigned int gui_active : RBBM_STATUS_GUI_ACTIVE_SIZE; + } rbbm_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_status_t { + unsigned int gui_active : RBBM_STATUS_GUI_ACTIVE_SIZE; + unsigned int rb_cntx_busy : RBBM_STATUS_RB_CNTX_BUSY_SIZE; + unsigned int : 1; + unsigned int sq_cntx0_busy : RBBM_STATUS_SQ_CNTX0_BUSY_SIZE; + unsigned int sq_cntx17_busy : RBBM_STATUS_SQ_CNTX17_BUSY_SIZE; + unsigned int vgt_busy : RBBM_STATUS_VGT_BUSY_SIZE; + unsigned int pa_busy : RBBM_STATUS_PA_BUSY_SIZE; + unsigned int sc_cntx_busy : RBBM_STATUS_SC_CNTX_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_busy : RBBM_STATUS_TPC_BUSY_SIZE; + unsigned int sx_busy : RBBM_STATUS_SX_BUSY_SIZE; + unsigned int : 1; + unsigned int mh_coherency_busy : RBBM_STATUS_MH_COHERENCY_BUSY_SIZE; + unsigned int mh_busy : RBBM_STATUS_MH_BUSY_SIZE; + unsigned int : 1; + unsigned int cp_nrt_busy : RBBM_STATUS_CP_NRT_BUSY_SIZE; + unsigned int : 1; + unsigned int rbbm_wu_busy : RBBM_STATUS_RBBM_WU_BUSY_SIZE; + unsigned int : 1; + unsigned int vgt_busy_no_dma : RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE; + unsigned int pfrq_pending : RBBM_STATUS_PFRQ_PENDING_SIZE; + unsigned int cfrq_pending : RBBM_STATUS_CFRQ_PENDING_SIZE; + unsigned int cprq_pending : RBBM_STATUS_CPRQ_PENDING_SIZE; + unsigned int hirq_pending : RBBM_STATUS_HIRQ_PENDING_SIZE; + unsigned int : 2; + unsigned int tc_busy : RBBM_STATUS_TC_BUSY_SIZE; + unsigned int cmdfifo_avail : RBBM_STATUS_CMDFIFO_AVAIL_SIZE; + } rbbm_status_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_status_t f; +} rbbm_status_u; + + +/* + * RBBM_DSPLY struct + */ + +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SIZE 1 +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SIZE 1 +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SIZE 1 +#define RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SIZE 1 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID0_SIZE 1 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID1_SIZE 1 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID2_SIZE 1 +#define RBBM_DSPLY_DMI_CH1_SW_CNTL_SIZE 1 +#define RBBM_DSPLY_DMI_CH1_NUM_BUFS_SIZE 2 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID0_SIZE 1 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID1_SIZE 1 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID2_SIZE 1 +#define RBBM_DSPLY_DMI_CH2_SW_CNTL_SIZE 1 +#define RBBM_DSPLY_DMI_CH2_NUM_BUFS_SIZE 2 +#define RBBM_DSPLY_DMI_CHANNEL_SELECT_SIZE 2 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID0_SIZE 1 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID1_SIZE 1 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID2_SIZE 1 +#define RBBM_DSPLY_DMI_CH3_SW_CNTL_SIZE 1 +#define RBBM_DSPLY_DMI_CH3_NUM_BUFS_SIZE 2 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID0_SIZE 1 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID1_SIZE 1 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID2_SIZE 1 +#define RBBM_DSPLY_DMI_CH4_SW_CNTL_SIZE 1 +#define RBBM_DSPLY_DMI_CH4_NUM_BUFS_SIZE 2 + +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT 0 +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT 1 +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT 2 +#define RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT 3 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT 4 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT 5 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT 6 +#define RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT 7 +#define RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT 8 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT 10 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT 11 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT 12 +#define RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT 13 +#define RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT 14 +#define RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT 16 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT 20 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT 21 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT 22 +#define RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT 23 +#define RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT 24 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT 26 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT 27 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT 28 +#define RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT 29 +#define RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT 30 + +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK 0x00000001 +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK 0x00000002 +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK 0x00000004 +#define RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK 0x00000008 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK 0x00000010 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK 0x00000020 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK 0x00000040 +#define RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK 0x00000080 +#define RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK 0x00000300 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK 0x00000400 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK 0x00000800 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK 0x00001000 +#define RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK 0x00002000 +#define RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK 0x0000c000 +#define RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK 0x00030000 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK 0x00100000 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK 0x00200000 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK 0x00400000 +#define RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK 0x00800000 +#define RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK 0x03000000 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK 0x04000000 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK 0x08000000 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK 0x10000000 +#define RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK 0x20000000 +#define RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK 0xc0000000 + +#define RBBM_DSPLY_MASK \ + (RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK | \ + RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK | \ + RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK | \ + RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK | \ + RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK | \ + RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK | \ + RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK | \ + RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK | \ + RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK | \ + RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK | \ + RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK | \ + RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK | \ + RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK | \ + RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK | \ + RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK | \ + RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK | \ + RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK | \ + RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK | \ + RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK | \ + RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK | \ + RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK | \ + RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK | \ + RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK | \ + RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK | \ + RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK) + +#define RBBM_DSPLY(sel_dmi_active_bufid0, sel_dmi_active_bufid1, sel_dmi_active_bufid2, sel_dmi_vsync_valid, dmi_ch1_use_bufid0, dmi_ch1_use_bufid1, dmi_ch1_use_bufid2, dmi_ch1_sw_cntl, dmi_ch1_num_bufs, dmi_ch2_use_bufid0, dmi_ch2_use_bufid1, dmi_ch2_use_bufid2, dmi_ch2_sw_cntl, dmi_ch2_num_bufs, dmi_channel_select, dmi_ch3_use_bufid0, dmi_ch3_use_bufid1, dmi_ch3_use_bufid2, dmi_ch3_sw_cntl, dmi_ch3_num_bufs, dmi_ch4_use_bufid0, dmi_ch4_use_bufid1, dmi_ch4_use_bufid2, dmi_ch4_sw_cntl, dmi_ch4_num_bufs) \ + ((sel_dmi_active_bufid0 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT) | \ + (sel_dmi_active_bufid1 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT) | \ + (sel_dmi_active_bufid2 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT) | \ + (sel_dmi_vsync_valid << RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT) | \ + (dmi_ch1_use_bufid0 << RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT) | \ + (dmi_ch1_use_bufid1 << RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT) | \ + (dmi_ch1_use_bufid2 << RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT) | \ + (dmi_ch1_sw_cntl << RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT) | \ + (dmi_ch1_num_bufs << RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT) | \ + (dmi_ch2_use_bufid0 << RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT) | \ + (dmi_ch2_use_bufid1 << RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT) | \ + (dmi_ch2_use_bufid2 << RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT) | \ + (dmi_ch2_sw_cntl << RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT) | \ + (dmi_ch2_num_bufs << RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT) | \ + (dmi_channel_select << RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT) | \ + (dmi_ch3_use_bufid0 << RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT) | \ + (dmi_ch3_use_bufid1 << RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT) | \ + (dmi_ch3_use_bufid2 << RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT) | \ + (dmi_ch3_sw_cntl << RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT) | \ + (dmi_ch3_num_bufs << RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT) | \ + (dmi_ch4_use_bufid0 << RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT) | \ + (dmi_ch4_use_bufid1 << RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT) | \ + (dmi_ch4_use_bufid2 << RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT) | \ + (dmi_ch4_sw_cntl << RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT) | \ + (dmi_ch4_num_bufs << RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT)) + +#define RBBM_DSPLY_GET_SEL_DMI_ACTIVE_BUFID0(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK) >> RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT) +#define RBBM_DSPLY_GET_SEL_DMI_ACTIVE_BUFID1(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK) >> RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT) +#define RBBM_DSPLY_GET_SEL_DMI_ACTIVE_BUFID2(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK) >> RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT) +#define RBBM_DSPLY_GET_SEL_DMI_VSYNC_VALID(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK) >> RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH1_USE_BUFID0(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH1_USE_BUFID1(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH1_USE_BUFID2(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH1_SW_CNTL(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH1_NUM_BUFS(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH2_USE_BUFID0(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH2_USE_BUFID1(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH2_USE_BUFID2(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH2_SW_CNTL(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH2_NUM_BUFS(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT) +#define RBBM_DSPLY_GET_DMI_CHANNEL_SELECT(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK) >> RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH3_USE_BUFID0(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH3_USE_BUFID1(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH3_USE_BUFID2(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH3_SW_CNTL(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH3_NUM_BUFS(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH4_USE_BUFID0(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH4_USE_BUFID1(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH4_USE_BUFID2(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH4_SW_CNTL(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH4_NUM_BUFS(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT) + +#define RBBM_DSPLY_SET_SEL_DMI_ACTIVE_BUFID0(rbbm_dsply_reg, sel_dmi_active_bufid0) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK) | (sel_dmi_active_bufid0 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT) +#define RBBM_DSPLY_SET_SEL_DMI_ACTIVE_BUFID1(rbbm_dsply_reg, sel_dmi_active_bufid1) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK) | (sel_dmi_active_bufid1 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT) +#define RBBM_DSPLY_SET_SEL_DMI_ACTIVE_BUFID2(rbbm_dsply_reg, sel_dmi_active_bufid2) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK) | (sel_dmi_active_bufid2 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT) +#define RBBM_DSPLY_SET_SEL_DMI_VSYNC_VALID(rbbm_dsply_reg, sel_dmi_vsync_valid) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK) | (sel_dmi_vsync_valid << RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH1_USE_BUFID0(rbbm_dsply_reg, dmi_ch1_use_bufid0) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK) | (dmi_ch1_use_bufid0 << RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH1_USE_BUFID1(rbbm_dsply_reg, dmi_ch1_use_bufid1) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK) | (dmi_ch1_use_bufid1 << RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH1_USE_BUFID2(rbbm_dsply_reg, dmi_ch1_use_bufid2) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK) | (dmi_ch1_use_bufid2 << RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH1_SW_CNTL(rbbm_dsply_reg, dmi_ch1_sw_cntl) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK) | (dmi_ch1_sw_cntl << RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH1_NUM_BUFS(rbbm_dsply_reg, dmi_ch1_num_bufs) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK) | (dmi_ch1_num_bufs << RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH2_USE_BUFID0(rbbm_dsply_reg, dmi_ch2_use_bufid0) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK) | (dmi_ch2_use_bufid0 << RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH2_USE_BUFID1(rbbm_dsply_reg, dmi_ch2_use_bufid1) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK) | (dmi_ch2_use_bufid1 << RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH2_USE_BUFID2(rbbm_dsply_reg, dmi_ch2_use_bufid2) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK) | (dmi_ch2_use_bufid2 << RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH2_SW_CNTL(rbbm_dsply_reg, dmi_ch2_sw_cntl) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK) | (dmi_ch2_sw_cntl << RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH2_NUM_BUFS(rbbm_dsply_reg, dmi_ch2_num_bufs) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK) | (dmi_ch2_num_bufs << RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT) +#define RBBM_DSPLY_SET_DMI_CHANNEL_SELECT(rbbm_dsply_reg, dmi_channel_select) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK) | (dmi_channel_select << RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH3_USE_BUFID0(rbbm_dsply_reg, dmi_ch3_use_bufid0) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK) | (dmi_ch3_use_bufid0 << RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH3_USE_BUFID1(rbbm_dsply_reg, dmi_ch3_use_bufid1) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK) | (dmi_ch3_use_bufid1 << RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH3_USE_BUFID2(rbbm_dsply_reg, dmi_ch3_use_bufid2) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK) | (dmi_ch3_use_bufid2 << RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH3_SW_CNTL(rbbm_dsply_reg, dmi_ch3_sw_cntl) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK) | (dmi_ch3_sw_cntl << RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH3_NUM_BUFS(rbbm_dsply_reg, dmi_ch3_num_bufs) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK) | (dmi_ch3_num_bufs << RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH4_USE_BUFID0(rbbm_dsply_reg, dmi_ch4_use_bufid0) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK) | (dmi_ch4_use_bufid0 << RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH4_USE_BUFID1(rbbm_dsply_reg, dmi_ch4_use_bufid1) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK) | (dmi_ch4_use_bufid1 << RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH4_USE_BUFID2(rbbm_dsply_reg, dmi_ch4_use_bufid2) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK) | (dmi_ch4_use_bufid2 << RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH4_SW_CNTL(rbbm_dsply_reg, dmi_ch4_sw_cntl) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK) | (dmi_ch4_sw_cntl << RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH4_NUM_BUFS(rbbm_dsply_reg, dmi_ch4_num_bufs) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK) | (dmi_ch4_num_bufs << RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_dsply_t { + unsigned int sel_dmi_active_bufid0 : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SIZE; + unsigned int sel_dmi_active_bufid1 : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SIZE; + unsigned int sel_dmi_active_bufid2 : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SIZE; + unsigned int sel_dmi_vsync_valid : RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SIZE; + unsigned int dmi_ch1_use_bufid0 : RBBM_DSPLY_DMI_CH1_USE_BUFID0_SIZE; + unsigned int dmi_ch1_use_bufid1 : RBBM_DSPLY_DMI_CH1_USE_BUFID1_SIZE; + unsigned int dmi_ch1_use_bufid2 : RBBM_DSPLY_DMI_CH1_USE_BUFID2_SIZE; + unsigned int dmi_ch1_sw_cntl : RBBM_DSPLY_DMI_CH1_SW_CNTL_SIZE; + unsigned int dmi_ch1_num_bufs : RBBM_DSPLY_DMI_CH1_NUM_BUFS_SIZE; + unsigned int dmi_ch2_use_bufid0 : RBBM_DSPLY_DMI_CH2_USE_BUFID0_SIZE; + unsigned int dmi_ch2_use_bufid1 : RBBM_DSPLY_DMI_CH2_USE_BUFID1_SIZE; + unsigned int dmi_ch2_use_bufid2 : RBBM_DSPLY_DMI_CH2_USE_BUFID2_SIZE; + unsigned int dmi_ch2_sw_cntl : RBBM_DSPLY_DMI_CH2_SW_CNTL_SIZE; + unsigned int dmi_ch2_num_bufs : RBBM_DSPLY_DMI_CH2_NUM_BUFS_SIZE; + unsigned int dmi_channel_select : RBBM_DSPLY_DMI_CHANNEL_SELECT_SIZE; + unsigned int : 2; + unsigned int dmi_ch3_use_bufid0 : RBBM_DSPLY_DMI_CH3_USE_BUFID0_SIZE; + unsigned int dmi_ch3_use_bufid1 : RBBM_DSPLY_DMI_CH3_USE_BUFID1_SIZE; + unsigned int dmi_ch3_use_bufid2 : RBBM_DSPLY_DMI_CH3_USE_BUFID2_SIZE; + unsigned int dmi_ch3_sw_cntl : RBBM_DSPLY_DMI_CH3_SW_CNTL_SIZE; + unsigned int dmi_ch3_num_bufs : RBBM_DSPLY_DMI_CH3_NUM_BUFS_SIZE; + unsigned int dmi_ch4_use_bufid0 : RBBM_DSPLY_DMI_CH4_USE_BUFID0_SIZE; + unsigned int dmi_ch4_use_bufid1 : RBBM_DSPLY_DMI_CH4_USE_BUFID1_SIZE; + unsigned int dmi_ch4_use_bufid2 : RBBM_DSPLY_DMI_CH4_USE_BUFID2_SIZE; + unsigned int dmi_ch4_sw_cntl : RBBM_DSPLY_DMI_CH4_SW_CNTL_SIZE; + unsigned int dmi_ch4_num_bufs : RBBM_DSPLY_DMI_CH4_NUM_BUFS_SIZE; + } rbbm_dsply_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_dsply_t { + unsigned int dmi_ch4_num_bufs : RBBM_DSPLY_DMI_CH4_NUM_BUFS_SIZE; + unsigned int dmi_ch4_sw_cntl : RBBM_DSPLY_DMI_CH4_SW_CNTL_SIZE; + unsigned int dmi_ch4_use_bufid2 : RBBM_DSPLY_DMI_CH4_USE_BUFID2_SIZE; + unsigned int dmi_ch4_use_bufid1 : RBBM_DSPLY_DMI_CH4_USE_BUFID1_SIZE; + unsigned int dmi_ch4_use_bufid0 : RBBM_DSPLY_DMI_CH4_USE_BUFID0_SIZE; + unsigned int dmi_ch3_num_bufs : RBBM_DSPLY_DMI_CH3_NUM_BUFS_SIZE; + unsigned int dmi_ch3_sw_cntl : RBBM_DSPLY_DMI_CH3_SW_CNTL_SIZE; + unsigned int dmi_ch3_use_bufid2 : RBBM_DSPLY_DMI_CH3_USE_BUFID2_SIZE; + unsigned int dmi_ch3_use_bufid1 : RBBM_DSPLY_DMI_CH3_USE_BUFID1_SIZE; + unsigned int dmi_ch3_use_bufid0 : RBBM_DSPLY_DMI_CH3_USE_BUFID0_SIZE; + unsigned int : 2; + unsigned int dmi_channel_select : RBBM_DSPLY_DMI_CHANNEL_SELECT_SIZE; + unsigned int dmi_ch2_num_bufs : RBBM_DSPLY_DMI_CH2_NUM_BUFS_SIZE; + unsigned int dmi_ch2_sw_cntl : RBBM_DSPLY_DMI_CH2_SW_CNTL_SIZE; + unsigned int dmi_ch2_use_bufid2 : RBBM_DSPLY_DMI_CH2_USE_BUFID2_SIZE; + unsigned int dmi_ch2_use_bufid1 : RBBM_DSPLY_DMI_CH2_USE_BUFID1_SIZE; + unsigned int dmi_ch2_use_bufid0 : RBBM_DSPLY_DMI_CH2_USE_BUFID0_SIZE; + unsigned int dmi_ch1_num_bufs : RBBM_DSPLY_DMI_CH1_NUM_BUFS_SIZE; + unsigned int dmi_ch1_sw_cntl : RBBM_DSPLY_DMI_CH1_SW_CNTL_SIZE; + unsigned int dmi_ch1_use_bufid2 : RBBM_DSPLY_DMI_CH1_USE_BUFID2_SIZE; + unsigned int dmi_ch1_use_bufid1 : RBBM_DSPLY_DMI_CH1_USE_BUFID1_SIZE; + unsigned int dmi_ch1_use_bufid0 : RBBM_DSPLY_DMI_CH1_USE_BUFID0_SIZE; + unsigned int sel_dmi_vsync_valid : RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SIZE; + unsigned int sel_dmi_active_bufid2 : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SIZE; + unsigned int sel_dmi_active_bufid1 : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SIZE; + unsigned int sel_dmi_active_bufid0 : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SIZE; + } rbbm_dsply_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_dsply_t f; +} rbbm_dsply_u; + + +/* + * RBBM_RENDER_LATEST struct + */ + +#define RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SIZE 2 +#define RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SIZE 2 +#define RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SIZE 2 +#define RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SIZE 2 + +#define RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT 0 +#define RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT 8 +#define RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT 16 +#define RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT 24 + +#define RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK 0x00000003 +#define RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK 0x00000300 +#define RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK 0x00030000 +#define RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK 0x03000000 + +#define RBBM_RENDER_LATEST_MASK \ + (RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK | \ + RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK | \ + RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK | \ + RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK) + +#define RBBM_RENDER_LATEST(dmi_ch1_buffer_id, dmi_ch2_buffer_id, dmi_ch3_buffer_id, dmi_ch4_buffer_id) \ + ((dmi_ch1_buffer_id << RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT) | \ + (dmi_ch2_buffer_id << RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT) | \ + (dmi_ch3_buffer_id << RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT) | \ + (dmi_ch4_buffer_id << RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT)) + +#define RBBM_RENDER_LATEST_GET_DMI_CH1_BUFFER_ID(rbbm_render_latest) \ + ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT) +#define RBBM_RENDER_LATEST_GET_DMI_CH2_BUFFER_ID(rbbm_render_latest) \ + ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT) +#define RBBM_RENDER_LATEST_GET_DMI_CH3_BUFFER_ID(rbbm_render_latest) \ + ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT) +#define RBBM_RENDER_LATEST_GET_DMI_CH4_BUFFER_ID(rbbm_render_latest) \ + ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT) + +#define RBBM_RENDER_LATEST_SET_DMI_CH1_BUFFER_ID(rbbm_render_latest_reg, dmi_ch1_buffer_id) \ + rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK) | (dmi_ch1_buffer_id << RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT) +#define RBBM_RENDER_LATEST_SET_DMI_CH2_BUFFER_ID(rbbm_render_latest_reg, dmi_ch2_buffer_id) \ + rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK) | (dmi_ch2_buffer_id << RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT) +#define RBBM_RENDER_LATEST_SET_DMI_CH3_BUFFER_ID(rbbm_render_latest_reg, dmi_ch3_buffer_id) \ + rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK) | (dmi_ch3_buffer_id << RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT) +#define RBBM_RENDER_LATEST_SET_DMI_CH4_BUFFER_ID(rbbm_render_latest_reg, dmi_ch4_buffer_id) \ + rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK) | (dmi_ch4_buffer_id << RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_render_latest_t { + unsigned int dmi_ch1_buffer_id : RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SIZE; + unsigned int : 6; + unsigned int dmi_ch2_buffer_id : RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SIZE; + unsigned int : 6; + unsigned int dmi_ch3_buffer_id : RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SIZE; + unsigned int : 6; + unsigned int dmi_ch4_buffer_id : RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SIZE; + unsigned int : 6; + } rbbm_render_latest_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_render_latest_t { + unsigned int : 6; + unsigned int dmi_ch4_buffer_id : RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SIZE; + unsigned int : 6; + unsigned int dmi_ch3_buffer_id : RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SIZE; + unsigned int : 6; + unsigned int dmi_ch2_buffer_id : RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SIZE; + unsigned int : 6; + unsigned int dmi_ch1_buffer_id : RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SIZE; + } rbbm_render_latest_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_render_latest_t f; +} rbbm_render_latest_u; + + +/* + * RBBM_RTL_RELEASE struct + */ + +#define RBBM_RTL_RELEASE_CHANGELIST_SIZE 32 + +#define RBBM_RTL_RELEASE_CHANGELIST_SHIFT 0 + +#define RBBM_RTL_RELEASE_CHANGELIST_MASK 0xffffffff + +#define RBBM_RTL_RELEASE_MASK \ + (RBBM_RTL_RELEASE_CHANGELIST_MASK) + +#define RBBM_RTL_RELEASE(changelist) \ + ((changelist << RBBM_RTL_RELEASE_CHANGELIST_SHIFT)) + +#define RBBM_RTL_RELEASE_GET_CHANGELIST(rbbm_rtl_release) \ + ((rbbm_rtl_release & RBBM_RTL_RELEASE_CHANGELIST_MASK) >> RBBM_RTL_RELEASE_CHANGELIST_SHIFT) + +#define RBBM_RTL_RELEASE_SET_CHANGELIST(rbbm_rtl_release_reg, changelist) \ + rbbm_rtl_release_reg = (rbbm_rtl_release_reg & ~RBBM_RTL_RELEASE_CHANGELIST_MASK) | (changelist << RBBM_RTL_RELEASE_CHANGELIST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_rtl_release_t { + unsigned int changelist : RBBM_RTL_RELEASE_CHANGELIST_SIZE; + } rbbm_rtl_release_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_rtl_release_t { + unsigned int changelist : RBBM_RTL_RELEASE_CHANGELIST_SIZE; + } rbbm_rtl_release_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_rtl_release_t f; +} rbbm_rtl_release_u; + + +/* + * RBBM_PATCH_RELEASE struct + */ + +#define RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE 16 +#define RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE 8 +#define RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE 8 + +#define RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT 0 +#define RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT 16 +#define RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT 24 + +#define RBBM_PATCH_RELEASE_PATCH_REVISION_MASK 0x0000ffff +#define RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK 0x00ff0000 +#define RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK 0xff000000 + +#define RBBM_PATCH_RELEASE_MASK \ + (RBBM_PATCH_RELEASE_PATCH_REVISION_MASK | \ + RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK | \ + RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) + +#define RBBM_PATCH_RELEASE(patch_revision, patch_selection, customer_id) \ + ((patch_revision << RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT) | \ + (patch_selection << RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT) | \ + (customer_id << RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT)) + +#define RBBM_PATCH_RELEASE_GET_PATCH_REVISION(rbbm_patch_release) \ + ((rbbm_patch_release & RBBM_PATCH_RELEASE_PATCH_REVISION_MASK) >> RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT) +#define RBBM_PATCH_RELEASE_GET_PATCH_SELECTION(rbbm_patch_release) \ + ((rbbm_patch_release & RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK) >> RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT) +#define RBBM_PATCH_RELEASE_GET_CUSTOMER_ID(rbbm_patch_release) \ + ((rbbm_patch_release & RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) >> RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT) + +#define RBBM_PATCH_RELEASE_SET_PATCH_REVISION(rbbm_patch_release_reg, patch_revision) \ + rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_PATCH_REVISION_MASK) | (patch_revision << RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT) +#define RBBM_PATCH_RELEASE_SET_PATCH_SELECTION(rbbm_patch_release_reg, patch_selection) \ + rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK) | (patch_selection << RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT) +#define RBBM_PATCH_RELEASE_SET_CUSTOMER_ID(rbbm_patch_release_reg, customer_id) \ + rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) | (customer_id << RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_patch_release_t { + unsigned int patch_revision : RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE; + unsigned int patch_selection : RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE; + unsigned int customer_id : RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE; + } rbbm_patch_release_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_patch_release_t { + unsigned int customer_id : RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE; + unsigned int patch_selection : RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE; + unsigned int patch_revision : RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE; + } rbbm_patch_release_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_patch_release_t f; +} rbbm_patch_release_u; + + +/* + * RBBM_AUXILIARY_CONFIG struct + */ + +#define RBBM_AUXILIARY_CONFIG_RESERVED_SIZE 32 + +#define RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT 0 + +#define RBBM_AUXILIARY_CONFIG_RESERVED_MASK 0xffffffff + +#define RBBM_AUXILIARY_CONFIG_MASK \ + (RBBM_AUXILIARY_CONFIG_RESERVED_MASK) + +#define RBBM_AUXILIARY_CONFIG(reserved) \ + ((reserved << RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT)) + +#define RBBM_AUXILIARY_CONFIG_GET_RESERVED(rbbm_auxiliary_config) \ + ((rbbm_auxiliary_config & RBBM_AUXILIARY_CONFIG_RESERVED_MASK) >> RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT) + +#define RBBM_AUXILIARY_CONFIG_SET_RESERVED(rbbm_auxiliary_config_reg, reserved) \ + rbbm_auxiliary_config_reg = (rbbm_auxiliary_config_reg & ~RBBM_AUXILIARY_CONFIG_RESERVED_MASK) | (reserved << RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_auxiliary_config_t { + unsigned int reserved : RBBM_AUXILIARY_CONFIG_RESERVED_SIZE; + } rbbm_auxiliary_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_auxiliary_config_t { + unsigned int reserved : RBBM_AUXILIARY_CONFIG_RESERVED_SIZE; + } rbbm_auxiliary_config_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_auxiliary_config_t f; +} rbbm_auxiliary_config_u; + + +/* + * RBBM_PERIPHID0 struct + */ + +#define RBBM_PERIPHID0_PARTNUMBER0_SIZE 8 + +#define RBBM_PERIPHID0_PARTNUMBER0_SHIFT 0 + +#define RBBM_PERIPHID0_PARTNUMBER0_MASK 0x000000ff + +#define RBBM_PERIPHID0_MASK \ + (RBBM_PERIPHID0_PARTNUMBER0_MASK) + +#define RBBM_PERIPHID0(partnumber0) \ + ((partnumber0 << RBBM_PERIPHID0_PARTNUMBER0_SHIFT)) + +#define RBBM_PERIPHID0_GET_PARTNUMBER0(rbbm_periphid0) \ + ((rbbm_periphid0 & RBBM_PERIPHID0_PARTNUMBER0_MASK) >> RBBM_PERIPHID0_PARTNUMBER0_SHIFT) + +#define RBBM_PERIPHID0_SET_PARTNUMBER0(rbbm_periphid0_reg, partnumber0) \ + rbbm_periphid0_reg = (rbbm_periphid0_reg & ~RBBM_PERIPHID0_PARTNUMBER0_MASK) | (partnumber0 << RBBM_PERIPHID0_PARTNUMBER0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_periphid0_t { + unsigned int partnumber0 : RBBM_PERIPHID0_PARTNUMBER0_SIZE; + unsigned int : 24; + } rbbm_periphid0_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_periphid0_t { + unsigned int : 24; + unsigned int partnumber0 : RBBM_PERIPHID0_PARTNUMBER0_SIZE; + } rbbm_periphid0_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_periphid0_t f; +} rbbm_periphid0_u; + + +/* + * RBBM_PERIPHID1 struct + */ + +#define RBBM_PERIPHID1_PARTNUMBER1_SIZE 4 +#define RBBM_PERIPHID1_DESIGNER0_SIZE 4 + +#define RBBM_PERIPHID1_PARTNUMBER1_SHIFT 0 +#define RBBM_PERIPHID1_DESIGNER0_SHIFT 4 + +#define RBBM_PERIPHID1_PARTNUMBER1_MASK 0x0000000f +#define RBBM_PERIPHID1_DESIGNER0_MASK 0x000000f0 + +#define RBBM_PERIPHID1_MASK \ + (RBBM_PERIPHID1_PARTNUMBER1_MASK | \ + RBBM_PERIPHID1_DESIGNER0_MASK) + +#define RBBM_PERIPHID1(partnumber1, designer0) \ + ((partnumber1 << RBBM_PERIPHID1_PARTNUMBER1_SHIFT) | \ + (designer0 << RBBM_PERIPHID1_DESIGNER0_SHIFT)) + +#define RBBM_PERIPHID1_GET_PARTNUMBER1(rbbm_periphid1) \ + ((rbbm_periphid1 & RBBM_PERIPHID1_PARTNUMBER1_MASK) >> RBBM_PERIPHID1_PARTNUMBER1_SHIFT) +#define RBBM_PERIPHID1_GET_DESIGNER0(rbbm_periphid1) \ + ((rbbm_periphid1 & RBBM_PERIPHID1_DESIGNER0_MASK) >> RBBM_PERIPHID1_DESIGNER0_SHIFT) + +#define RBBM_PERIPHID1_SET_PARTNUMBER1(rbbm_periphid1_reg, partnumber1) \ + rbbm_periphid1_reg = (rbbm_periphid1_reg & ~RBBM_PERIPHID1_PARTNUMBER1_MASK) | (partnumber1 << RBBM_PERIPHID1_PARTNUMBER1_SHIFT) +#define RBBM_PERIPHID1_SET_DESIGNER0(rbbm_periphid1_reg, designer0) \ + rbbm_periphid1_reg = (rbbm_periphid1_reg & ~RBBM_PERIPHID1_DESIGNER0_MASK) | (designer0 << RBBM_PERIPHID1_DESIGNER0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_periphid1_t { + unsigned int partnumber1 : RBBM_PERIPHID1_PARTNUMBER1_SIZE; + unsigned int designer0 : RBBM_PERIPHID1_DESIGNER0_SIZE; + unsigned int : 24; + } rbbm_periphid1_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_periphid1_t { + unsigned int : 24; + unsigned int designer0 : RBBM_PERIPHID1_DESIGNER0_SIZE; + unsigned int partnumber1 : RBBM_PERIPHID1_PARTNUMBER1_SIZE; + } rbbm_periphid1_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_periphid1_t f; +} rbbm_periphid1_u; + + +/* + * RBBM_PERIPHID2 struct + */ + +#define RBBM_PERIPHID2_DESIGNER1_SIZE 4 +#define RBBM_PERIPHID2_REVISION_SIZE 4 + +#define RBBM_PERIPHID2_DESIGNER1_SHIFT 0 +#define RBBM_PERIPHID2_REVISION_SHIFT 4 + +#define RBBM_PERIPHID2_DESIGNER1_MASK 0x0000000f +#define RBBM_PERIPHID2_REVISION_MASK 0x000000f0 + +#define RBBM_PERIPHID2_MASK \ + (RBBM_PERIPHID2_DESIGNER1_MASK | \ + RBBM_PERIPHID2_REVISION_MASK) + +#define RBBM_PERIPHID2(designer1, revision) \ + ((designer1 << RBBM_PERIPHID2_DESIGNER1_SHIFT) | \ + (revision << RBBM_PERIPHID2_REVISION_SHIFT)) + +#define RBBM_PERIPHID2_GET_DESIGNER1(rbbm_periphid2) \ + ((rbbm_periphid2 & RBBM_PERIPHID2_DESIGNER1_MASK) >> RBBM_PERIPHID2_DESIGNER1_SHIFT) +#define RBBM_PERIPHID2_GET_REVISION(rbbm_periphid2) \ + ((rbbm_periphid2 & RBBM_PERIPHID2_REVISION_MASK) >> RBBM_PERIPHID2_REVISION_SHIFT) + +#define RBBM_PERIPHID2_SET_DESIGNER1(rbbm_periphid2_reg, designer1) \ + rbbm_periphid2_reg = (rbbm_periphid2_reg & ~RBBM_PERIPHID2_DESIGNER1_MASK) | (designer1 << RBBM_PERIPHID2_DESIGNER1_SHIFT) +#define RBBM_PERIPHID2_SET_REVISION(rbbm_periphid2_reg, revision) \ + rbbm_periphid2_reg = (rbbm_periphid2_reg & ~RBBM_PERIPHID2_REVISION_MASK) | (revision << RBBM_PERIPHID2_REVISION_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_periphid2_t { + unsigned int designer1 : RBBM_PERIPHID2_DESIGNER1_SIZE; + unsigned int revision : RBBM_PERIPHID2_REVISION_SIZE; + unsigned int : 24; + } rbbm_periphid2_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_periphid2_t { + unsigned int : 24; + unsigned int revision : RBBM_PERIPHID2_REVISION_SIZE; + unsigned int designer1 : RBBM_PERIPHID2_DESIGNER1_SIZE; + } rbbm_periphid2_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_periphid2_t f; +} rbbm_periphid2_u; + + +/* + * RBBM_PERIPHID3 struct + */ + +#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE 2 +#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE 2 +#define RBBM_PERIPHID3_MH_INTERFACE_SIZE 2 +#define RBBM_PERIPHID3_CONTINUATION_SIZE 1 + +#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT 0 +#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT 2 +#define RBBM_PERIPHID3_MH_INTERFACE_SHIFT 4 +#define RBBM_PERIPHID3_CONTINUATION_SHIFT 7 + +#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK 0x00000003 +#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK 0x0000000c +#define RBBM_PERIPHID3_MH_INTERFACE_MASK 0x00000030 +#define RBBM_PERIPHID3_CONTINUATION_MASK 0x00000080 + +#define RBBM_PERIPHID3_MASK \ + (RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK | \ + RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK | \ + RBBM_PERIPHID3_MH_INTERFACE_MASK | \ + RBBM_PERIPHID3_CONTINUATION_MASK) + +#define RBBM_PERIPHID3(rbbm_host_interface, garb_slave_interface, mh_interface, continuation) \ + ((rbbm_host_interface << RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT) | \ + (garb_slave_interface << RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT) | \ + (mh_interface << RBBM_PERIPHID3_MH_INTERFACE_SHIFT) | \ + (continuation << RBBM_PERIPHID3_CONTINUATION_SHIFT)) + +#define RBBM_PERIPHID3_GET_RBBM_HOST_INTERFACE(rbbm_periphid3) \ + ((rbbm_periphid3 & RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK) >> RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_GET_GARB_SLAVE_INTERFACE(rbbm_periphid3) \ + ((rbbm_periphid3 & RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK) >> RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_GET_MH_INTERFACE(rbbm_periphid3) \ + ((rbbm_periphid3 & RBBM_PERIPHID3_MH_INTERFACE_MASK) >> RBBM_PERIPHID3_MH_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_GET_CONTINUATION(rbbm_periphid3) \ + ((rbbm_periphid3 & RBBM_PERIPHID3_CONTINUATION_MASK) >> RBBM_PERIPHID3_CONTINUATION_SHIFT) + +#define RBBM_PERIPHID3_SET_RBBM_HOST_INTERFACE(rbbm_periphid3_reg, rbbm_host_interface) \ + rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK) | (rbbm_host_interface << RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_SET_GARB_SLAVE_INTERFACE(rbbm_periphid3_reg, garb_slave_interface) \ + rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK) | (garb_slave_interface << RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_SET_MH_INTERFACE(rbbm_periphid3_reg, mh_interface) \ + rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_MH_INTERFACE_MASK) | (mh_interface << RBBM_PERIPHID3_MH_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_SET_CONTINUATION(rbbm_periphid3_reg, continuation) \ + rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_CONTINUATION_MASK) | (continuation << RBBM_PERIPHID3_CONTINUATION_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_periphid3_t { + unsigned int rbbm_host_interface : RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE; + unsigned int garb_slave_interface : RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE; + unsigned int mh_interface : RBBM_PERIPHID3_MH_INTERFACE_SIZE; + unsigned int : 1; + unsigned int continuation : RBBM_PERIPHID3_CONTINUATION_SIZE; + unsigned int : 24; + } rbbm_periphid3_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_periphid3_t { + unsigned int : 24; + unsigned int continuation : RBBM_PERIPHID3_CONTINUATION_SIZE; + unsigned int : 1; + unsigned int mh_interface : RBBM_PERIPHID3_MH_INTERFACE_SIZE; + unsigned int garb_slave_interface : RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE; + unsigned int rbbm_host_interface : RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE; + } rbbm_periphid3_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_periphid3_t f; +} rbbm_periphid3_u; + + +/* + * RBBM_CNTL struct + */ + +#define RBBM_CNTL_READ_TIMEOUT_SIZE 8 +#define RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE 9 + +#define RBBM_CNTL_READ_TIMEOUT_SHIFT 0 +#define RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT 8 + +#define RBBM_CNTL_READ_TIMEOUT_MASK 0x000000ff +#define RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK 0x0001ff00 + +#define RBBM_CNTL_MASK \ + (RBBM_CNTL_READ_TIMEOUT_MASK | \ + RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) + +#define RBBM_CNTL(read_timeout, regclk_deassert_time) \ + ((read_timeout << RBBM_CNTL_READ_TIMEOUT_SHIFT) | \ + (regclk_deassert_time << RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT)) + +#define RBBM_CNTL_GET_READ_TIMEOUT(rbbm_cntl) \ + ((rbbm_cntl & RBBM_CNTL_READ_TIMEOUT_MASK) >> RBBM_CNTL_READ_TIMEOUT_SHIFT) +#define RBBM_CNTL_GET_REGCLK_DEASSERT_TIME(rbbm_cntl) \ + ((rbbm_cntl & RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) >> RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT) + +#define RBBM_CNTL_SET_READ_TIMEOUT(rbbm_cntl_reg, read_timeout) \ + rbbm_cntl_reg = (rbbm_cntl_reg & ~RBBM_CNTL_READ_TIMEOUT_MASK) | (read_timeout << RBBM_CNTL_READ_TIMEOUT_SHIFT) +#define RBBM_CNTL_SET_REGCLK_DEASSERT_TIME(rbbm_cntl_reg, regclk_deassert_time) \ + rbbm_cntl_reg = (rbbm_cntl_reg & ~RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) | (regclk_deassert_time << RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_cntl_t { + unsigned int read_timeout : RBBM_CNTL_READ_TIMEOUT_SIZE; + unsigned int regclk_deassert_time : RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE; + unsigned int : 15; + } rbbm_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_cntl_t { + unsigned int : 15; + unsigned int regclk_deassert_time : RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE; + unsigned int read_timeout : RBBM_CNTL_READ_TIMEOUT_SIZE; + } rbbm_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_cntl_t f; +} rbbm_cntl_u; + + +/* + * RBBM_SKEW_CNTL struct + */ + +#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE 5 +#define RBBM_SKEW_CNTL_SKEW_COUNT_SIZE 5 + +#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT 0 +#define RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT 5 + +#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK 0x0000001f +#define RBBM_SKEW_CNTL_SKEW_COUNT_MASK 0x000003e0 + +#define RBBM_SKEW_CNTL_MASK \ + (RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK | \ + RBBM_SKEW_CNTL_SKEW_COUNT_MASK) + +#define RBBM_SKEW_CNTL(skew_top_threshold, skew_count) \ + ((skew_top_threshold << RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT) | \ + (skew_count << RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT)) + +#define RBBM_SKEW_CNTL_GET_SKEW_TOP_THRESHOLD(rbbm_skew_cntl) \ + ((rbbm_skew_cntl & RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK) >> RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT) +#define RBBM_SKEW_CNTL_GET_SKEW_COUNT(rbbm_skew_cntl) \ + ((rbbm_skew_cntl & RBBM_SKEW_CNTL_SKEW_COUNT_MASK) >> RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT) + +#define RBBM_SKEW_CNTL_SET_SKEW_TOP_THRESHOLD(rbbm_skew_cntl_reg, skew_top_threshold) \ + rbbm_skew_cntl_reg = (rbbm_skew_cntl_reg & ~RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK) | (skew_top_threshold << RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT) +#define RBBM_SKEW_CNTL_SET_SKEW_COUNT(rbbm_skew_cntl_reg, skew_count) \ + rbbm_skew_cntl_reg = (rbbm_skew_cntl_reg & ~RBBM_SKEW_CNTL_SKEW_COUNT_MASK) | (skew_count << RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_skew_cntl_t { + unsigned int skew_top_threshold : RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE; + unsigned int skew_count : RBBM_SKEW_CNTL_SKEW_COUNT_SIZE; + unsigned int : 22; + } rbbm_skew_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_skew_cntl_t { + unsigned int : 22; + unsigned int skew_count : RBBM_SKEW_CNTL_SKEW_COUNT_SIZE; + unsigned int skew_top_threshold : RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE; + } rbbm_skew_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_skew_cntl_t f; +} rbbm_skew_cntl_u; + + +/* + * RBBM_SOFT_RESET struct + */ + +#define RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE 1 + +#define RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT 0 +#define RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT 2 +#define RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT 3 +#define RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT 4 +#define RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT 5 +#define RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT 6 +#define RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT 12 +#define RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT 15 +#define RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT 16 + +#define RBBM_SOFT_RESET_SOFT_RESET_CP_MASK 0x00000001 +#define RBBM_SOFT_RESET_SOFT_RESET_PA_MASK 0x00000004 +#define RBBM_SOFT_RESET_SOFT_RESET_MH_MASK 0x00000008 +#define RBBM_SOFT_RESET_SOFT_RESET_BC_MASK 0x00000010 +#define RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK 0x00000020 +#define RBBM_SOFT_RESET_SOFT_RESET_SX_MASK 0x00000040 +#define RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK 0x00001000 +#define RBBM_SOFT_RESET_SOFT_RESET_SC_MASK 0x00008000 +#define RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK 0x00010000 + +#define RBBM_SOFT_RESET_MASK \ + (RBBM_SOFT_RESET_SOFT_RESET_CP_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_PA_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_MH_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_BC_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_SX_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_SC_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) + +#define RBBM_SOFT_RESET(soft_reset_cp, soft_reset_pa, soft_reset_mh, soft_reset_bc, soft_reset_sq, soft_reset_sx, soft_reset_cib, soft_reset_sc, soft_reset_vgt) \ + ((soft_reset_cp << RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT) | \ + (soft_reset_pa << RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT) | \ + (soft_reset_mh << RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT) | \ + (soft_reset_bc << RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT) | \ + (soft_reset_sq << RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT) | \ + (soft_reset_sx << RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT) | \ + (soft_reset_cib << RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT) | \ + (soft_reset_sc << RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT) | \ + (soft_reset_vgt << RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT)) + +#define RBBM_SOFT_RESET_GET_SOFT_RESET_CP(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_CP_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_PA(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_PA_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_MH(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_MH_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_BC(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_BC_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_SQ(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_SX(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SX_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_CIB(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_SC(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SC_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_VGT(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT) + +#define RBBM_SOFT_RESET_SET_SOFT_RESET_CP(rbbm_soft_reset_reg, soft_reset_cp) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_CP_MASK) | (soft_reset_cp << RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_PA(rbbm_soft_reset_reg, soft_reset_pa) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_PA_MASK) | (soft_reset_pa << RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_MH(rbbm_soft_reset_reg, soft_reset_mh) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_MH_MASK) | (soft_reset_mh << RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_BC(rbbm_soft_reset_reg, soft_reset_bc) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_BC_MASK) | (soft_reset_bc << RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_SQ(rbbm_soft_reset_reg, soft_reset_sq) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK) | (soft_reset_sq << RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_SX(rbbm_soft_reset_reg, soft_reset_sx) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SX_MASK) | (soft_reset_sx << RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_CIB(rbbm_soft_reset_reg, soft_reset_cib) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK) | (soft_reset_cib << RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_SC(rbbm_soft_reset_reg, soft_reset_sc) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SC_MASK) | (soft_reset_sc << RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_VGT(rbbm_soft_reset_reg, soft_reset_vgt) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) | (soft_reset_vgt << RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_soft_reset_t { + unsigned int soft_reset_cp : RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE; + unsigned int : 1; + unsigned int soft_reset_pa : RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE; + unsigned int soft_reset_mh : RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE; + unsigned int soft_reset_bc : RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE; + unsigned int soft_reset_sq : RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE; + unsigned int soft_reset_sx : RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE; + unsigned int : 5; + unsigned int soft_reset_cib : RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE; + unsigned int : 2; + unsigned int soft_reset_sc : RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE; + unsigned int soft_reset_vgt : RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE; + unsigned int : 15; + } rbbm_soft_reset_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_soft_reset_t { + unsigned int : 15; + unsigned int soft_reset_vgt : RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE; + unsigned int soft_reset_sc : RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE; + unsigned int : 2; + unsigned int soft_reset_cib : RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE; + unsigned int : 5; + unsigned int soft_reset_sx : RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE; + unsigned int soft_reset_sq : RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE; + unsigned int soft_reset_bc : RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE; + unsigned int soft_reset_mh : RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE; + unsigned int soft_reset_pa : RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE; + unsigned int : 1; + unsigned int soft_reset_cp : RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE; + } rbbm_soft_reset_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_soft_reset_t f; +} rbbm_soft_reset_u; + + +/* + * RBBM_PM_OVERRIDE1 struct + */ + +#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE 1 + +#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT 0 +#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT 1 +#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT 2 +#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT 3 +#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT 4 +#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT 5 +#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT 6 +#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT 7 +#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT 8 +#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT 9 +#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT 10 +#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT 11 +#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT 12 +#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT 13 +#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT 14 +#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT 15 +#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT 16 +#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT 17 +#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT 18 +#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT 19 +#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT 20 +#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT 21 +#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT 22 +#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT 23 +#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT 24 +#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT 25 +#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT 26 +#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT 27 +#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT 28 +#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT 29 +#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT 30 +#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT 31 + +#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK 0x00000001 +#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK 0x00000002 +#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK 0x00000004 +#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK 0x00000008 +#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK 0x00000010 +#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK 0x00000020 +#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000040 +#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK 0x00000080 +#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK 0x00000100 +#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK 0x00000200 +#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK 0x00000400 +#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK 0x00000800 +#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK 0x00001000 +#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK 0x00002000 +#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK 0x00004000 +#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK 0x00008000 +#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK 0x00010000 +#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK 0x00020000 +#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK 0x00040000 +#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK 0x00080000 +#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK 0x00100000 +#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK 0x00200000 +#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK 0x00400000 +#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK 0x00800000 +#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK 0x01000000 +#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK 0x02000000 +#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK 0x04000000 +#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK 0x08000000 +#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK 0x10000000 +#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK 0x20000000 +#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK 0x40000000 +#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK 0x80000000 + +#define RBBM_PM_OVERRIDE1_MASK \ + (RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) + +#define RBBM_PM_OVERRIDE1(rbbm_ahbclk_pm_override, sc_reg_sclk_pm_override, sc_sclk_pm_override, sp_top_sclk_pm_override, sp_v0_sclk_pm_override, sq_reg_sclk_pm_override, sq_reg_fifos_sclk_pm_override, sq_const_mem_sclk_pm_override, sq_sq_sclk_pm_override, sx_sclk_pm_override, sx_reg_sclk_pm_override, tcm_tco_sclk_pm_override, tcm_tcm_sclk_pm_override, tcm_tcd_sclk_pm_override, tcm_reg_sclk_pm_override, tpc_tpc_sclk_pm_override, tpc_reg_sclk_pm_override, tcf_tca_sclk_pm_override, tcf_tcb_sclk_pm_override, tcf_tcb_read_sclk_pm_override, tp_tp_sclk_pm_override, tp_reg_sclk_pm_override, cp_g_sclk_pm_override, cp_reg_sclk_pm_override, cp_g_reg_sclk_pm_override, spi_sclk_pm_override, rb_reg_sclk_pm_override, rb_sclk_pm_override, mh_mh_sclk_pm_override, mh_reg_sclk_pm_override, mh_mmu_sclk_pm_override, mh_tcroq_sclk_pm_override) \ + ((rbbm_ahbclk_pm_override << RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT) | \ + (sc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (sc_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT) | \ + (sp_top_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT) | \ + (sp_v0_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT) | \ + (sq_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (sq_reg_fifos_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT) | \ + (sq_const_mem_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT) | \ + (sq_sq_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT) | \ + (sx_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT) | \ + (sx_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcm_tco_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcm_tcm_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcm_tcd_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcm_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (tpc_tpc_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT) | \ + (tpc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcf_tca_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcf_tcb_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcf_tcb_read_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT) | \ + (tp_tp_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT) | \ + (tp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (cp_g_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT) | \ + (cp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (cp_g_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (spi_sclk_pm_override << RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT) | \ + (rb_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (rb_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT) | \ + (mh_mh_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT) | \ + (mh_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (mh_mmu_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT) | \ + (mh_tcroq_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT)) + +#define RBBM_PM_OVERRIDE1_GET_RBBM_AHBCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SC_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SP_TOP_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SP_V0_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SQ_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SQ_REG_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SQ_CONST_MEM_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SQ_SQ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SX_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SX_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCM_TCO_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCM_TCM_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCM_TCD_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCM_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TPC_TPC_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TPC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCF_TCA_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCF_TCB_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCF_TCB_READ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TP_TP_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_CP_G_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_CP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_CP_G_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SPI_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_RB_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_RB_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_MH_MH_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_MH_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_MH_MMU_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_MH_TCROQ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT) + +#define RBBM_PM_OVERRIDE1_SET_RBBM_AHBCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rbbm_ahbclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK) | (rbbm_ahbclk_pm_override << RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sc_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK) | (sc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SC_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sc_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK) | (sc_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SP_TOP_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sp_top_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK) | (sp_top_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SP_V0_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sp_v0_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK) | (sp_v0_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SQ_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK) | (sq_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SQ_REG_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_reg_fifos_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK) | (sq_reg_fifos_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SQ_CONST_MEM_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_const_mem_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK) | (sq_const_mem_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SQ_SQ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_sq_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK) | (sq_sq_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SX_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sx_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK) | (sx_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SX_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sx_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK) | (sx_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCM_TCO_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tco_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK) | (tcm_tco_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCM_TCM_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tcm_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK) | (tcm_tcm_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCM_TCD_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tcd_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK) | (tcm_tcd_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCM_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK) | (tcm_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TPC_TPC_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tpc_tpc_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK) | (tpc_tpc_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TPC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tpc_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK) | (tpc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCF_TCA_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tca_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK) | (tcf_tca_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCF_TCB_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tcb_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK) | (tcf_tcb_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCF_TCB_READ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tcb_read_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK) | (tcf_tcb_read_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TP_TP_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tp_tp_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK) | (tp_tp_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tp_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK) | (tp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_CP_G_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_g_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK) | (cp_g_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_CP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK) | (cp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_CP_G_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_g_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK) | (cp_g_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SPI_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, spi_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK) | (spi_sclk_pm_override << RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_RB_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rb_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK) | (rb_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_RB_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rb_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK) | (rb_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_MH_MH_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_mh_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK) | (mh_mh_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_MH_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK) | (mh_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_MH_MMU_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_mmu_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK) | (mh_mmu_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_MH_TCROQ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_tcroq_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) | (mh_tcroq_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_pm_override1_t { + unsigned int rbbm_ahbclk_pm_override : RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE; + unsigned int sc_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int sc_sclk_pm_override : RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE; + unsigned int sp_top_sclk_pm_override : RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE; + unsigned int sp_v0_sclk_pm_override : RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_reg_fifos_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_const_mem_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_sq_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE; + unsigned int sx_sclk_pm_override : RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE; + unsigned int sx_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tco_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tcm_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tcd_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tpc_tpc_sclk_pm_override : RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE; + unsigned int tpc_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tca_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tcb_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tcb_read_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE; + unsigned int tp_tp_sclk_pm_override : RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE; + unsigned int tp_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_g_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_g_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int spi_sclk_pm_override : RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE; + unsigned int rb_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int rb_sclk_pm_override : RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_mh_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_mmu_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_tcroq_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE; + } rbbm_pm_override1_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_pm_override1_t { + unsigned int mh_tcroq_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_mmu_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_mh_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE; + unsigned int rb_sclk_pm_override : RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE; + unsigned int rb_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int spi_sclk_pm_override : RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_g_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_g_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE; + unsigned int tp_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tp_tp_sclk_pm_override : RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tcb_read_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tcb_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tca_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE; + unsigned int tpc_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tpc_tpc_sclk_pm_override : RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tcd_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tcm_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tco_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE; + unsigned int sx_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int sx_sclk_pm_override : RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_sq_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_const_mem_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_reg_fifos_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int sp_v0_sclk_pm_override : RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE; + unsigned int sp_top_sclk_pm_override : RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE; + unsigned int sc_sclk_pm_override : RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE; + unsigned int sc_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int rbbm_ahbclk_pm_override : RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE; + } rbbm_pm_override1_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_pm_override1_t f; +} rbbm_pm_override1_u; + + +/* + * RBBM_PM_OVERRIDE2 struct + */ + +#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE 1 + +#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT 0 +#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT 1 +#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT 2 +#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT 3 +#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT 4 +#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT 5 +#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT 6 +#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT 7 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT 8 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT 9 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT 10 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT 11 + +#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK 0x00000001 +#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK 0x00000002 +#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK 0x00000004 +#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK 0x00000008 +#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000010 +#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK 0x00000020 +#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK 0x00000040 +#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK 0x00000080 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK 0x00000100 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK 0x00000200 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK 0x00000400 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK 0x00000800 + +#define RBBM_PM_OVERRIDE2_MASK \ + (RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) + +#define RBBM_PM_OVERRIDE2(pa_reg_sclk_pm_override, pa_pa_sclk_pm_override, pa_ag_sclk_pm_override, vgt_reg_sclk_pm_override, vgt_fifos_sclk_pm_override, vgt_vgt_sclk_pm_override, debug_perf_sclk_pm_override, perm_sclk_pm_override, gc_ga_gmem0_pm_override, gc_ga_gmem1_pm_override, gc_ga_gmem2_pm_override, gc_ga_gmem3_pm_override) \ + ((pa_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (pa_pa_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT) | \ + (pa_ag_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT) | \ + (vgt_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (vgt_fifos_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT) | \ + (vgt_vgt_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT) | \ + (debug_perf_sclk_pm_override << RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT) | \ + (perm_sclk_pm_override << RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT) | \ + (gc_ga_gmem0_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT) | \ + (gc_ga_gmem1_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT) | \ + (gc_ga_gmem2_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT) | \ + (gc_ga_gmem3_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT)) + +#define RBBM_PM_OVERRIDE2_GET_PA_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_PA_PA_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_PA_AG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_VGT_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_VGT_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_VGT_VGT_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_DEBUG_PERF_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_PERM_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM0_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM1_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM2_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM3_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT) + +#define RBBM_PM_OVERRIDE2_SET_PA_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_reg_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK) | (pa_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_PA_PA_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_pa_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK) | (pa_pa_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_PA_AG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_ag_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK) | (pa_ag_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_VGT_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_reg_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK) | (vgt_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_VGT_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_fifos_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK) | (vgt_fifos_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_VGT_VGT_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_vgt_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK) | (vgt_vgt_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_DEBUG_PERF_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, debug_perf_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK) | (debug_perf_sclk_pm_override << RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_PERM_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, perm_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK) | (perm_sclk_pm_override << RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM0_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem0_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK) | (gc_ga_gmem0_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM1_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem1_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK) | (gc_ga_gmem1_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM2_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem2_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK) | (gc_ga_gmem2_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM3_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem3_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) | (gc_ga_gmem3_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_pm_override2_t { + unsigned int pa_reg_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_pa_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_ag_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_reg_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_fifos_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_vgt_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE; + unsigned int debug_perf_sclk_pm_override : RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE; + unsigned int perm_sclk_pm_override : RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem0_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem1_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem2_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem3_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE; + unsigned int : 20; + } rbbm_pm_override2_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_pm_override2_t { + unsigned int : 20; + unsigned int gc_ga_gmem3_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem2_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem1_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem0_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE; + unsigned int perm_sclk_pm_override : RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE; + unsigned int debug_perf_sclk_pm_override : RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_vgt_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_fifos_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_reg_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_ag_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_pa_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_reg_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE; + } rbbm_pm_override2_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_pm_override2_t f; +} rbbm_pm_override2_u; + + +/* + * GC_SYS_IDLE struct + */ + +#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE 16 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SIZE 6 +#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SIZE 1 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_SIZE 1 +#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SIZE 1 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SIZE 1 +#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE 1 + +#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT 0 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT 16 +#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT 24 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT 25 +#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT 29 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT 30 +#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT 31 + +#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK 0x0000ffff +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK 0x003f0000 +#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK 0x01000000 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK 0x02000000 +#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK 0x20000000 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK 0x40000000 +#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK 0x80000000 + +#define GC_SYS_IDLE_MASK \ + (GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK | \ + GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK | \ + GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK | \ + GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK | \ + GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK | \ + GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK | \ + GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) + +#define GC_SYS_IDLE(gc_sys_idle_delay, gc_sys_wait_dmi_mask, gc_sys_urgent_ramp, gc_sys_wait_dmi, gc_sys_urgent_ramp_override, gc_sys_wait_dmi_override, gc_sys_idle_override) \ + ((gc_sys_idle_delay << GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT) | \ + (gc_sys_wait_dmi_mask << GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT) | \ + (gc_sys_urgent_ramp << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT) | \ + (gc_sys_wait_dmi << GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT) | \ + (gc_sys_urgent_ramp_override << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT) | \ + (gc_sys_wait_dmi_override << GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT) | \ + (gc_sys_idle_override << GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT)) + +#define GC_SYS_IDLE_GET_GC_SYS_IDLE_DELAY(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK) >> GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT) +#define GC_SYS_IDLE_GET_GC_SYS_WAIT_DMI_MASK(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK) >> GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT) +#define GC_SYS_IDLE_GET_GC_SYS_URGENT_RAMP(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK) >> GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT) +#define GC_SYS_IDLE_GET_GC_SYS_WAIT_DMI(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK) >> GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT) +#define GC_SYS_IDLE_GET_GC_SYS_URGENT_RAMP_OVERRIDE(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK) >> GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT) +#define GC_SYS_IDLE_GET_GC_SYS_WAIT_DMI_OVERRIDE(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK) >> GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT) +#define GC_SYS_IDLE_GET_GC_SYS_IDLE_OVERRIDE(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) >> GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT) + +#define GC_SYS_IDLE_SET_GC_SYS_IDLE_DELAY(gc_sys_idle_reg, gc_sys_idle_delay) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK) | (gc_sys_idle_delay << GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT) +#define GC_SYS_IDLE_SET_GC_SYS_WAIT_DMI_MASK(gc_sys_idle_reg, gc_sys_wait_dmi_mask) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK) | (gc_sys_wait_dmi_mask << GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT) +#define GC_SYS_IDLE_SET_GC_SYS_URGENT_RAMP(gc_sys_idle_reg, gc_sys_urgent_ramp) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK) | (gc_sys_urgent_ramp << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT) +#define GC_SYS_IDLE_SET_GC_SYS_WAIT_DMI(gc_sys_idle_reg, gc_sys_wait_dmi) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK) | (gc_sys_wait_dmi << GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT) +#define GC_SYS_IDLE_SET_GC_SYS_URGENT_RAMP_OVERRIDE(gc_sys_idle_reg, gc_sys_urgent_ramp_override) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK) | (gc_sys_urgent_ramp_override << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT) +#define GC_SYS_IDLE_SET_GC_SYS_WAIT_DMI_OVERRIDE(gc_sys_idle_reg, gc_sys_wait_dmi_override) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK) | (gc_sys_wait_dmi_override << GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT) +#define GC_SYS_IDLE_SET_GC_SYS_IDLE_OVERRIDE(gc_sys_idle_reg, gc_sys_idle_override) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) | (gc_sys_idle_override << GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _gc_sys_idle_t { + unsigned int gc_sys_idle_delay : GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE; + unsigned int gc_sys_wait_dmi_mask : GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SIZE; + unsigned int : 2; + unsigned int gc_sys_urgent_ramp : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SIZE; + unsigned int gc_sys_wait_dmi : GC_SYS_IDLE_GC_SYS_WAIT_DMI_SIZE; + unsigned int : 3; + unsigned int gc_sys_urgent_ramp_override : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SIZE; + unsigned int gc_sys_wait_dmi_override : GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SIZE; + unsigned int gc_sys_idle_override : GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE; + } gc_sys_idle_t; + +#else // !BIGENDIAN_OS + + typedef struct _gc_sys_idle_t { + unsigned int gc_sys_idle_override : GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE; + unsigned int gc_sys_wait_dmi_override : GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SIZE; + unsigned int gc_sys_urgent_ramp_override : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SIZE; + unsigned int : 3; + unsigned int gc_sys_wait_dmi : GC_SYS_IDLE_GC_SYS_WAIT_DMI_SIZE; + unsigned int gc_sys_urgent_ramp : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SIZE; + unsigned int : 2; + unsigned int gc_sys_wait_dmi_mask : GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SIZE; + unsigned int gc_sys_idle_delay : GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE; + } gc_sys_idle_t; + +#endif + +typedef union { + unsigned int val : 32; + gc_sys_idle_t f; +} gc_sys_idle_u; + + +/* + * NQWAIT_UNTIL struct + */ + +#define NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE 1 + +#define NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT 0 + +#define NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK 0x00000001 + +#define NQWAIT_UNTIL_MASK \ + (NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) + +#define NQWAIT_UNTIL(wait_gui_idle) \ + ((wait_gui_idle << NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT)) + +#define NQWAIT_UNTIL_GET_WAIT_GUI_IDLE(nqwait_until) \ + ((nqwait_until & NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) >> NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT) + +#define NQWAIT_UNTIL_SET_WAIT_GUI_IDLE(nqwait_until_reg, wait_gui_idle) \ + nqwait_until_reg = (nqwait_until_reg & ~NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) | (wait_gui_idle << NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _nqwait_until_t { + unsigned int wait_gui_idle : NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE; + unsigned int : 31; + } nqwait_until_t; + +#else // !BIGENDIAN_OS + + typedef struct _nqwait_until_t { + unsigned int : 31; + unsigned int wait_gui_idle : NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE; + } nqwait_until_t; + +#endif + +typedef union { + unsigned int val : 32; + nqwait_until_t f; +} nqwait_until_u; + + +/* + * RBBM_DEBUG_OUT struct + */ + +#define RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SIZE 32 + +#define RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT 0 + +#define RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK 0xffffffff + +#define RBBM_DEBUG_OUT_MASK \ + (RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK) + +#define RBBM_DEBUG_OUT(debug_bus_out) \ + ((debug_bus_out << RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT)) + +#define RBBM_DEBUG_OUT_GET_DEBUG_BUS_OUT(rbbm_debug_out) \ + ((rbbm_debug_out & RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK) >> RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT) + +#define RBBM_DEBUG_OUT_SET_DEBUG_BUS_OUT(rbbm_debug_out_reg, debug_bus_out) \ + rbbm_debug_out_reg = (rbbm_debug_out_reg & ~RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK) | (debug_bus_out << RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_debug_out_t { + unsigned int debug_bus_out : RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SIZE; + } rbbm_debug_out_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_debug_out_t { + unsigned int debug_bus_out : RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SIZE; + } rbbm_debug_out_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_debug_out_t f; +} rbbm_debug_out_u; + + +/* + * RBBM_DEBUG_CNTL struct + */ + +#define RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SIZE 6 +#define RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SIZE 4 +#define RBBM_DEBUG_CNTL_SW_ENABLE_SIZE 1 +#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SIZE 6 +#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SIZE 4 +#define RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SIZE 4 + +#define RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT 0 +#define RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT 8 +#define RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT 12 +#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT 16 +#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT 24 +#define RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT 28 + +#define RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK 0x0000003f +#define RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK 0x00000f00 +#define RBBM_DEBUG_CNTL_SW_ENABLE_MASK 0x00001000 +#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK 0x003f0000 +#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK 0x0f000000 +#define RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK 0xf0000000 + +#define RBBM_DEBUG_CNTL_MASK \ + (RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK | \ + RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK | \ + RBBM_DEBUG_CNTL_SW_ENABLE_MASK | \ + RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK | \ + RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK | \ + RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK) + +#define RBBM_DEBUG_CNTL(sub_block_addr, sub_block_sel, sw_enable, gpio_sub_block_addr, gpio_sub_block_sel, gpio_byte_lane_enb) \ + ((sub_block_addr << RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT) | \ + (sub_block_sel << RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT) | \ + (sw_enable << RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT) | \ + (gpio_sub_block_addr << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT) | \ + (gpio_sub_block_sel << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT) | \ + (gpio_byte_lane_enb << RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT)) + +#define RBBM_DEBUG_CNTL_GET_SUB_BLOCK_ADDR(rbbm_debug_cntl) \ + ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK) >> RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT) +#define RBBM_DEBUG_CNTL_GET_SUB_BLOCK_SEL(rbbm_debug_cntl) \ + ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK) >> RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT) +#define RBBM_DEBUG_CNTL_GET_SW_ENABLE(rbbm_debug_cntl) \ + ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_SW_ENABLE_MASK) >> RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT) +#define RBBM_DEBUG_CNTL_GET_GPIO_SUB_BLOCK_ADDR(rbbm_debug_cntl) \ + ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK) >> RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT) +#define RBBM_DEBUG_CNTL_GET_GPIO_SUB_BLOCK_SEL(rbbm_debug_cntl) \ + ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK) >> RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT) +#define RBBM_DEBUG_CNTL_GET_GPIO_BYTE_LANE_ENB(rbbm_debug_cntl) \ + ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK) >> RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT) + +#define RBBM_DEBUG_CNTL_SET_SUB_BLOCK_ADDR(rbbm_debug_cntl_reg, sub_block_addr) \ + rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK) | (sub_block_addr << RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT) +#define RBBM_DEBUG_CNTL_SET_SUB_BLOCK_SEL(rbbm_debug_cntl_reg, sub_block_sel) \ + rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK) | (sub_block_sel << RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT) +#define RBBM_DEBUG_CNTL_SET_SW_ENABLE(rbbm_debug_cntl_reg, sw_enable) \ + rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_SW_ENABLE_MASK) | (sw_enable << RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT) +#define RBBM_DEBUG_CNTL_SET_GPIO_SUB_BLOCK_ADDR(rbbm_debug_cntl_reg, gpio_sub_block_addr) \ + rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK) | (gpio_sub_block_addr << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT) +#define RBBM_DEBUG_CNTL_SET_GPIO_SUB_BLOCK_SEL(rbbm_debug_cntl_reg, gpio_sub_block_sel) \ + rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK) | (gpio_sub_block_sel << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT) +#define RBBM_DEBUG_CNTL_SET_GPIO_BYTE_LANE_ENB(rbbm_debug_cntl_reg, gpio_byte_lane_enb) \ + rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK) | (gpio_byte_lane_enb << RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_debug_cntl_t { + unsigned int sub_block_addr : RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SIZE; + unsigned int : 2; + unsigned int sub_block_sel : RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SIZE; + unsigned int sw_enable : RBBM_DEBUG_CNTL_SW_ENABLE_SIZE; + unsigned int : 3; + unsigned int gpio_sub_block_addr : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SIZE; + unsigned int : 2; + unsigned int gpio_sub_block_sel : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SIZE; + unsigned int gpio_byte_lane_enb : RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SIZE; + } rbbm_debug_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_debug_cntl_t { + unsigned int gpio_byte_lane_enb : RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SIZE; + unsigned int gpio_sub_block_sel : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SIZE; + unsigned int : 2; + unsigned int gpio_sub_block_addr : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SIZE; + unsigned int : 3; + unsigned int sw_enable : RBBM_DEBUG_CNTL_SW_ENABLE_SIZE; + unsigned int sub_block_sel : RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SIZE; + unsigned int : 2; + unsigned int sub_block_addr : RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SIZE; + } rbbm_debug_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_debug_cntl_t f; +} rbbm_debug_cntl_u; + + +/* + * RBBM_DEBUG struct + */ + +#define RBBM_DEBUG_IGNORE_RTR_SIZE 1 +#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE 1 +#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE 1 +#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE 1 +#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE 4 +#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE 1 +#define RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE 1 +#define RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE 1 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE 1 +#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE 1 + +#define RBBM_DEBUG_IGNORE_RTR_SHIFT 1 +#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT 2 +#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT 3 +#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT 4 +#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT 8 +#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT 16 +#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT 17 +#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT 18 +#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT 19 +#define RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT 20 +#define RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT 21 +#define RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT 22 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT 23 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT 24 +#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT 31 + +#define RBBM_DEBUG_IGNORE_RTR_MASK 0x00000002 +#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK 0x00000004 +#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK 0x00000008 +#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK 0x00000010 +#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK 0x00000f00 +#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK 0x00010000 +#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK 0x00020000 +#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK 0x00040000 +#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK 0x00080000 +#define RBBM_DEBUG_CP_RBBM_NRTRTR_MASK 0x00100000 +#define RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK 0x00200000 +#define RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK 0x00400000 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK 0x00800000 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK 0x01000000 +#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK 0x80000000 + +#define RBBM_DEBUG_MASK \ + (RBBM_DEBUG_IGNORE_RTR_MASK | \ + RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK | \ + RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK | \ + RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK | \ + RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK | \ + RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK | \ + RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK | \ + RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK | \ + RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK | \ + RBBM_DEBUG_CP_RBBM_NRTRTR_MASK | \ + RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK | \ + RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK | \ + RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK | \ + RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK | \ + RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) + +#define RBBM_DEBUG(ignore_rtr, ignore_cp_sched_wu, ignore_cp_sched_isync, ignore_cp_sched_nq_hi, hysteresis_nrt_gui_active, ignore_rtr_for_hi, ignore_cp_rbbm_nrtrtr_for_hi, ignore_vgt_rbbm_nrtrtr_for_hi, ignore_sq_rbbm_nrtrtr_for_hi, cp_rbbm_nrtrtr, vgt_rbbm_nrtrtr, sq_rbbm_nrtrtr, clients_for_nrt_rtr_for_hi, clients_for_nrt_rtr, ignore_sx_rbbm_busy) \ + ((ignore_rtr << RBBM_DEBUG_IGNORE_RTR_SHIFT) | \ + (ignore_cp_sched_wu << RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT) | \ + (ignore_cp_sched_isync << RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT) | \ + (ignore_cp_sched_nq_hi << RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT) | \ + (hysteresis_nrt_gui_active << RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT) | \ + (ignore_rtr_for_hi << RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT) | \ + (ignore_cp_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT) | \ + (ignore_vgt_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT) | \ + (ignore_sq_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT) | \ + (cp_rbbm_nrtrtr << RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT) | \ + (vgt_rbbm_nrtrtr << RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT) | \ + (sq_rbbm_nrtrtr << RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT) | \ + (clients_for_nrt_rtr_for_hi << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT) | \ + (clients_for_nrt_rtr << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT) | \ + (ignore_sx_rbbm_busy << RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT)) + +#define RBBM_DEBUG_GET_IGNORE_RTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_RTR_MASK) >> RBBM_DEBUG_IGNORE_RTR_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_WU(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_ISYNC(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_NQ_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT) +#define RBBM_DEBUG_GET_HYSTERESIS_NRT_GUI_ACTIVE(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK) >> RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_RTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_CP_RBBM_NRTRTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_VGT_RBBM_NRTRTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_SQ_RBBM_NRTRTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_CP_RBBM_NRTRTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_CP_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_GET_VGT_RBBM_NRTRTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_GET_SQ_RBBM_NRTRTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_GET_CLIENTS_FOR_NRT_RTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK) >> RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_CLIENTS_FOR_NRT_RTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK) >> RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_SX_RBBM_BUSY(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) >> RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT) + +#define RBBM_DEBUG_SET_IGNORE_RTR(rbbm_debug_reg, ignore_rtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_RTR_MASK) | (ignore_rtr << RBBM_DEBUG_IGNORE_RTR_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_WU(rbbm_debug_reg, ignore_cp_sched_wu) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK) | (ignore_cp_sched_wu << RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_ISYNC(rbbm_debug_reg, ignore_cp_sched_isync) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK) | (ignore_cp_sched_isync << RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_NQ_HI(rbbm_debug_reg, ignore_cp_sched_nq_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK) | (ignore_cp_sched_nq_hi << RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT) +#define RBBM_DEBUG_SET_HYSTERESIS_NRT_GUI_ACTIVE(rbbm_debug_reg, hysteresis_nrt_gui_active) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK) | (hysteresis_nrt_gui_active << RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_RTR_FOR_HI(rbbm_debug_reg, ignore_rtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK) | (ignore_rtr_for_hi << RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_CP_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_cp_rbbm_nrtrtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_cp_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_VGT_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_vgt_rbbm_nrtrtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_vgt_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_SQ_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_sq_rbbm_nrtrtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_sq_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_CP_RBBM_NRTRTR(rbbm_debug_reg, cp_rbbm_nrtrtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CP_RBBM_NRTRTR_MASK) | (cp_rbbm_nrtrtr << RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_SET_VGT_RBBM_NRTRTR(rbbm_debug_reg, vgt_rbbm_nrtrtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK) | (vgt_rbbm_nrtrtr << RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_SET_SQ_RBBM_NRTRTR(rbbm_debug_reg, sq_rbbm_nrtrtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK) | (sq_rbbm_nrtrtr << RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_SET_CLIENTS_FOR_NRT_RTR_FOR_HI(rbbm_debug_reg, clients_for_nrt_rtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK) | (clients_for_nrt_rtr_for_hi << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_CLIENTS_FOR_NRT_RTR(rbbm_debug_reg, clients_for_nrt_rtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK) | (clients_for_nrt_rtr << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_SX_RBBM_BUSY(rbbm_debug_reg, ignore_sx_rbbm_busy) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) | (ignore_sx_rbbm_busy << RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_debug_t { + unsigned int : 1; + unsigned int ignore_rtr : RBBM_DEBUG_IGNORE_RTR_SIZE; + unsigned int ignore_cp_sched_wu : RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE; + unsigned int ignore_cp_sched_isync : RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE; + unsigned int ignore_cp_sched_nq_hi : RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE; + unsigned int : 3; + unsigned int hysteresis_nrt_gui_active : RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE; + unsigned int : 4; + unsigned int ignore_rtr_for_hi : RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE; + unsigned int ignore_cp_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_vgt_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_sq_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int cp_rbbm_nrtrtr : RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE; + unsigned int vgt_rbbm_nrtrtr : RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE; + unsigned int sq_rbbm_nrtrtr : RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE; + unsigned int clients_for_nrt_rtr_for_hi : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE; + unsigned int clients_for_nrt_rtr : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE; + unsigned int : 6; + unsigned int ignore_sx_rbbm_busy : RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE; + } rbbm_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_debug_t { + unsigned int ignore_sx_rbbm_busy : RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE; + unsigned int : 6; + unsigned int clients_for_nrt_rtr : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE; + unsigned int clients_for_nrt_rtr_for_hi : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE; + unsigned int sq_rbbm_nrtrtr : RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE; + unsigned int vgt_rbbm_nrtrtr : RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE; + unsigned int cp_rbbm_nrtrtr : RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE; + unsigned int ignore_sq_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_vgt_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_cp_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_rtr_for_hi : RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE; + unsigned int : 4; + unsigned int hysteresis_nrt_gui_active : RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE; + unsigned int : 3; + unsigned int ignore_cp_sched_nq_hi : RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE; + unsigned int ignore_cp_sched_isync : RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE; + unsigned int ignore_cp_sched_wu : RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE; + unsigned int ignore_rtr : RBBM_DEBUG_IGNORE_RTR_SIZE; + unsigned int : 1; + } rbbm_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_debug_t f; +} rbbm_debug_u; + + +/* + * RBBM_READ_ERROR struct + */ + +#define RBBM_READ_ERROR_READ_ADDRESS_SIZE 15 +#define RBBM_READ_ERROR_READ_REQUESTER_SIZE 1 +#define RBBM_READ_ERROR_READ_ERROR_SIZE 1 + +#define RBBM_READ_ERROR_READ_ADDRESS_SHIFT 2 +#define RBBM_READ_ERROR_READ_REQUESTER_SHIFT 30 +#define RBBM_READ_ERROR_READ_ERROR_SHIFT 31 + +#define RBBM_READ_ERROR_READ_ADDRESS_MASK 0x0001fffc +#define RBBM_READ_ERROR_READ_REQUESTER_MASK 0x40000000 +#define RBBM_READ_ERROR_READ_ERROR_MASK 0x80000000 + +#define RBBM_READ_ERROR_MASK \ + (RBBM_READ_ERROR_READ_ADDRESS_MASK | \ + RBBM_READ_ERROR_READ_REQUESTER_MASK | \ + RBBM_READ_ERROR_READ_ERROR_MASK) + +#define RBBM_READ_ERROR(read_address, read_requester, read_error) \ + ((read_address << RBBM_READ_ERROR_READ_ADDRESS_SHIFT) | \ + (read_requester << RBBM_READ_ERROR_READ_REQUESTER_SHIFT) | \ + (read_error << RBBM_READ_ERROR_READ_ERROR_SHIFT)) + +#define RBBM_READ_ERROR_GET_READ_ADDRESS(rbbm_read_error) \ + ((rbbm_read_error & RBBM_READ_ERROR_READ_ADDRESS_MASK) >> RBBM_READ_ERROR_READ_ADDRESS_SHIFT) +#define RBBM_READ_ERROR_GET_READ_REQUESTER(rbbm_read_error) \ + ((rbbm_read_error & RBBM_READ_ERROR_READ_REQUESTER_MASK) >> RBBM_READ_ERROR_READ_REQUESTER_SHIFT) +#define RBBM_READ_ERROR_GET_READ_ERROR(rbbm_read_error) \ + ((rbbm_read_error & RBBM_READ_ERROR_READ_ERROR_MASK) >> RBBM_READ_ERROR_READ_ERROR_SHIFT) + +#define RBBM_READ_ERROR_SET_READ_ADDRESS(rbbm_read_error_reg, read_address) \ + rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_ADDRESS_MASK) | (read_address << RBBM_READ_ERROR_READ_ADDRESS_SHIFT) +#define RBBM_READ_ERROR_SET_READ_REQUESTER(rbbm_read_error_reg, read_requester) \ + rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_REQUESTER_MASK) | (read_requester << RBBM_READ_ERROR_READ_REQUESTER_SHIFT) +#define RBBM_READ_ERROR_SET_READ_ERROR(rbbm_read_error_reg, read_error) \ + rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_ERROR_MASK) | (read_error << RBBM_READ_ERROR_READ_ERROR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_read_error_t { + unsigned int : 2; + unsigned int read_address : RBBM_READ_ERROR_READ_ADDRESS_SIZE; + unsigned int : 13; + unsigned int read_requester : RBBM_READ_ERROR_READ_REQUESTER_SIZE; + unsigned int read_error : RBBM_READ_ERROR_READ_ERROR_SIZE; + } rbbm_read_error_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_read_error_t { + unsigned int read_error : RBBM_READ_ERROR_READ_ERROR_SIZE; + unsigned int read_requester : RBBM_READ_ERROR_READ_REQUESTER_SIZE; + unsigned int : 13; + unsigned int read_address : RBBM_READ_ERROR_READ_ADDRESS_SIZE; + unsigned int : 2; + } rbbm_read_error_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_read_error_t f; +} rbbm_read_error_u; + + +/* + * RBBM_WAIT_IDLE_CLOCKS struct + */ + +#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE 8 + +#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT 0 + +#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK 0x000000ff + +#define RBBM_WAIT_IDLE_CLOCKS_MASK \ + (RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) + +#define RBBM_WAIT_IDLE_CLOCKS(wait_idle_clocks_nrt) \ + ((wait_idle_clocks_nrt << RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT)) + +#define RBBM_WAIT_IDLE_CLOCKS_GET_WAIT_IDLE_CLOCKS_NRT(rbbm_wait_idle_clocks) \ + ((rbbm_wait_idle_clocks & RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) >> RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT) + +#define RBBM_WAIT_IDLE_CLOCKS_SET_WAIT_IDLE_CLOCKS_NRT(rbbm_wait_idle_clocks_reg, wait_idle_clocks_nrt) \ + rbbm_wait_idle_clocks_reg = (rbbm_wait_idle_clocks_reg & ~RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) | (wait_idle_clocks_nrt << RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_wait_idle_clocks_t { + unsigned int wait_idle_clocks_nrt : RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE; + unsigned int : 24; + } rbbm_wait_idle_clocks_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_wait_idle_clocks_t { + unsigned int : 24; + unsigned int wait_idle_clocks_nrt : RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE; + } rbbm_wait_idle_clocks_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_wait_idle_clocks_t f; +} rbbm_wait_idle_clocks_u; + + +/* + * RBBM_INT_CNTL struct + */ + +#define RBBM_INT_CNTL_RDERR_INT_MASK_SIZE 1 +#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE 1 +#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE 1 + +#define RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT 0 +#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT 1 +#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT 19 + +#define RBBM_INT_CNTL_RDERR_INT_MASK_MASK 0x00000001 +#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK 0x00000002 +#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK 0x00080000 + +#define RBBM_INT_CNTL_MASK \ + (RBBM_INT_CNTL_RDERR_INT_MASK_MASK | \ + RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK | \ + RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) + +#define RBBM_INT_CNTL(rderr_int_mask, display_update_int_mask, gui_idle_int_mask) \ + ((rderr_int_mask << RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT) | \ + (display_update_int_mask << RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT) | \ + (gui_idle_int_mask << RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT)) + +#define RBBM_INT_CNTL_GET_RDERR_INT_MASK(rbbm_int_cntl) \ + ((rbbm_int_cntl & RBBM_INT_CNTL_RDERR_INT_MASK_MASK) >> RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT) +#define RBBM_INT_CNTL_GET_DISPLAY_UPDATE_INT_MASK(rbbm_int_cntl) \ + ((rbbm_int_cntl & RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK) >> RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT) +#define RBBM_INT_CNTL_GET_GUI_IDLE_INT_MASK(rbbm_int_cntl) \ + ((rbbm_int_cntl & RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) >> RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT) + +#define RBBM_INT_CNTL_SET_RDERR_INT_MASK(rbbm_int_cntl_reg, rderr_int_mask) \ + rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_RDERR_INT_MASK_MASK) | (rderr_int_mask << RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT) +#define RBBM_INT_CNTL_SET_DISPLAY_UPDATE_INT_MASK(rbbm_int_cntl_reg, display_update_int_mask) \ + rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK) | (display_update_int_mask << RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT) +#define RBBM_INT_CNTL_SET_GUI_IDLE_INT_MASK(rbbm_int_cntl_reg, gui_idle_int_mask) \ + rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) | (gui_idle_int_mask << RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_int_cntl_t { + unsigned int rderr_int_mask : RBBM_INT_CNTL_RDERR_INT_MASK_SIZE; + unsigned int display_update_int_mask : RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE; + unsigned int : 17; + unsigned int gui_idle_int_mask : RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE; + unsigned int : 12; + } rbbm_int_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_int_cntl_t { + unsigned int : 12; + unsigned int gui_idle_int_mask : RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE; + unsigned int : 17; + unsigned int display_update_int_mask : RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE; + unsigned int rderr_int_mask : RBBM_INT_CNTL_RDERR_INT_MASK_SIZE; + } rbbm_int_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_int_cntl_t f; +} rbbm_int_cntl_u; + + +/* + * RBBM_INT_STATUS struct + */ + +#define RBBM_INT_STATUS_RDERR_INT_STAT_SIZE 1 +#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE 1 +#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE 1 + +#define RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT 0 +#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT 1 +#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT 19 + +#define RBBM_INT_STATUS_RDERR_INT_STAT_MASK 0x00000001 +#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK 0x00000002 +#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK 0x00080000 + +#define RBBM_INT_STATUS_MASK \ + (RBBM_INT_STATUS_RDERR_INT_STAT_MASK | \ + RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK | \ + RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) + +#define RBBM_INT_STATUS(rderr_int_stat, display_update_int_stat, gui_idle_int_stat) \ + ((rderr_int_stat << RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT) | \ + (display_update_int_stat << RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT) | \ + (gui_idle_int_stat << RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT)) + +#define RBBM_INT_STATUS_GET_RDERR_INT_STAT(rbbm_int_status) \ + ((rbbm_int_status & RBBM_INT_STATUS_RDERR_INT_STAT_MASK) >> RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT) +#define RBBM_INT_STATUS_GET_DISPLAY_UPDATE_INT_STAT(rbbm_int_status) \ + ((rbbm_int_status & RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK) >> RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT) +#define RBBM_INT_STATUS_GET_GUI_IDLE_INT_STAT(rbbm_int_status) \ + ((rbbm_int_status & RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) >> RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT) + +#define RBBM_INT_STATUS_SET_RDERR_INT_STAT(rbbm_int_status_reg, rderr_int_stat) \ + rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_RDERR_INT_STAT_MASK) | (rderr_int_stat << RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT) +#define RBBM_INT_STATUS_SET_DISPLAY_UPDATE_INT_STAT(rbbm_int_status_reg, display_update_int_stat) \ + rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK) | (display_update_int_stat << RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT) +#define RBBM_INT_STATUS_SET_GUI_IDLE_INT_STAT(rbbm_int_status_reg, gui_idle_int_stat) \ + rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) | (gui_idle_int_stat << RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_int_status_t { + unsigned int rderr_int_stat : RBBM_INT_STATUS_RDERR_INT_STAT_SIZE; + unsigned int display_update_int_stat : RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE; + unsigned int : 17; + unsigned int gui_idle_int_stat : RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE; + unsigned int : 12; + } rbbm_int_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_int_status_t { + unsigned int : 12; + unsigned int gui_idle_int_stat : RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE; + unsigned int : 17; + unsigned int display_update_int_stat : RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE; + unsigned int rderr_int_stat : RBBM_INT_STATUS_RDERR_INT_STAT_SIZE; + } rbbm_int_status_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_int_status_t f; +} rbbm_int_status_u; + + +/* + * RBBM_INT_ACK struct + */ + +#define RBBM_INT_ACK_RDERR_INT_ACK_SIZE 1 +#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE 1 +#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE 1 + +#define RBBM_INT_ACK_RDERR_INT_ACK_SHIFT 0 +#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT 1 +#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT 19 + +#define RBBM_INT_ACK_RDERR_INT_ACK_MASK 0x00000001 +#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK 0x00000002 +#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK 0x00080000 + +#define RBBM_INT_ACK_MASK \ + (RBBM_INT_ACK_RDERR_INT_ACK_MASK | \ + RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK | \ + RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) + +#define RBBM_INT_ACK(rderr_int_ack, display_update_int_ack, gui_idle_int_ack) \ + ((rderr_int_ack << RBBM_INT_ACK_RDERR_INT_ACK_SHIFT) | \ + (display_update_int_ack << RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT) | \ + (gui_idle_int_ack << RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT)) + +#define RBBM_INT_ACK_GET_RDERR_INT_ACK(rbbm_int_ack) \ + ((rbbm_int_ack & RBBM_INT_ACK_RDERR_INT_ACK_MASK) >> RBBM_INT_ACK_RDERR_INT_ACK_SHIFT) +#define RBBM_INT_ACK_GET_DISPLAY_UPDATE_INT_ACK(rbbm_int_ack) \ + ((rbbm_int_ack & RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK) >> RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT) +#define RBBM_INT_ACK_GET_GUI_IDLE_INT_ACK(rbbm_int_ack) \ + ((rbbm_int_ack & RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) >> RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT) + +#define RBBM_INT_ACK_SET_RDERR_INT_ACK(rbbm_int_ack_reg, rderr_int_ack) \ + rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_RDERR_INT_ACK_MASK) | (rderr_int_ack << RBBM_INT_ACK_RDERR_INT_ACK_SHIFT) +#define RBBM_INT_ACK_SET_DISPLAY_UPDATE_INT_ACK(rbbm_int_ack_reg, display_update_int_ack) \ + rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK) | (display_update_int_ack << RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT) +#define RBBM_INT_ACK_SET_GUI_IDLE_INT_ACK(rbbm_int_ack_reg, gui_idle_int_ack) \ + rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) | (gui_idle_int_ack << RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_int_ack_t { + unsigned int rderr_int_ack : RBBM_INT_ACK_RDERR_INT_ACK_SIZE; + unsigned int display_update_int_ack : RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE; + unsigned int : 17; + unsigned int gui_idle_int_ack : RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE; + unsigned int : 12; + } rbbm_int_ack_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_int_ack_t { + unsigned int : 12; + unsigned int gui_idle_int_ack : RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE; + unsigned int : 17; + unsigned int display_update_int_ack : RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE; + unsigned int rderr_int_ack : RBBM_INT_ACK_RDERR_INT_ACK_SIZE; + } rbbm_int_ack_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_int_ack_t f; +} rbbm_int_ack_u; + + +/* + * MASTER_INT_SIGNAL struct + */ + +#define MASTER_INT_SIGNAL_MH_INT_STAT_SIZE 1 +#define MASTER_INT_SIGNAL_SQ_INT_STAT_SIZE 1 +#define MASTER_INT_SIGNAL_CP_INT_STAT_SIZE 1 +#define MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE 1 + +#define MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT 5 +#define MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT 26 +#define MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT 30 +#define MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT 31 + +#define MASTER_INT_SIGNAL_MH_INT_STAT_MASK 0x00000020 +#define MASTER_INT_SIGNAL_SQ_INT_STAT_MASK 0x04000000 +#define MASTER_INT_SIGNAL_CP_INT_STAT_MASK 0x40000000 +#define MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK 0x80000000 + +#define MASTER_INT_SIGNAL_MASK \ + (MASTER_INT_SIGNAL_MH_INT_STAT_MASK | \ + MASTER_INT_SIGNAL_SQ_INT_STAT_MASK | \ + MASTER_INT_SIGNAL_CP_INT_STAT_MASK | \ + MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) + +#define MASTER_INT_SIGNAL(mh_int_stat, sq_int_stat, cp_int_stat, rbbm_int_stat) \ + ((mh_int_stat << MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT) | \ + (sq_int_stat << MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT) | \ + (cp_int_stat << MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT) | \ + (rbbm_int_stat << MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT)) + +#define MASTER_INT_SIGNAL_GET_MH_INT_STAT(master_int_signal) \ + ((master_int_signal & MASTER_INT_SIGNAL_MH_INT_STAT_MASK) >> MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_GET_SQ_INT_STAT(master_int_signal) \ + ((master_int_signal & MASTER_INT_SIGNAL_SQ_INT_STAT_MASK) >> MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_GET_CP_INT_STAT(master_int_signal) \ + ((master_int_signal & MASTER_INT_SIGNAL_CP_INT_STAT_MASK) >> MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_GET_RBBM_INT_STAT(master_int_signal) \ + ((master_int_signal & MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) >> MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT) + +#define MASTER_INT_SIGNAL_SET_MH_INT_STAT(master_int_signal_reg, mh_int_stat) \ + master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_MH_INT_STAT_MASK) | (mh_int_stat << MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_SET_SQ_INT_STAT(master_int_signal_reg, sq_int_stat) \ + master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_SQ_INT_STAT_MASK) | (sq_int_stat << MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_SET_CP_INT_STAT(master_int_signal_reg, cp_int_stat) \ + master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_CP_INT_STAT_MASK) | (cp_int_stat << MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_SET_RBBM_INT_STAT(master_int_signal_reg, rbbm_int_stat) \ + master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) | (rbbm_int_stat << MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _master_int_signal_t { + unsigned int : 5; + unsigned int mh_int_stat : MASTER_INT_SIGNAL_MH_INT_STAT_SIZE; + unsigned int : 20; + unsigned int sq_int_stat : MASTER_INT_SIGNAL_SQ_INT_STAT_SIZE; + unsigned int : 3; + unsigned int cp_int_stat : MASTER_INT_SIGNAL_CP_INT_STAT_SIZE; + unsigned int rbbm_int_stat : MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE; + } master_int_signal_t; + +#else // !BIGENDIAN_OS + + typedef struct _master_int_signal_t { + unsigned int rbbm_int_stat : MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE; + unsigned int cp_int_stat : MASTER_INT_SIGNAL_CP_INT_STAT_SIZE; + unsigned int : 3; + unsigned int sq_int_stat : MASTER_INT_SIGNAL_SQ_INT_STAT_SIZE; + unsigned int : 20; + unsigned int mh_int_stat : MASTER_INT_SIGNAL_MH_INT_STAT_SIZE; + unsigned int : 5; + } master_int_signal_t; + +#endif + +typedef union { + unsigned int val : 32; + master_int_signal_t f; +} master_int_signal_u; + + +/* + * RBBM_PERFCOUNTER1_SELECT struct + */ + +#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE 6 + +#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT 0 + +#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK 0x0000003f + +#define RBBM_PERFCOUNTER1_SELECT_MASK \ + (RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) + +#define RBBM_PERFCOUNTER1_SELECT(perf_count1_sel) \ + ((perf_count1_sel << RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT)) + +#define RBBM_PERFCOUNTER1_SELECT_GET_PERF_COUNT1_SEL(rbbm_perfcounter1_select) \ + ((rbbm_perfcounter1_select & RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) >> RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT) + +#define RBBM_PERFCOUNTER1_SELECT_SET_PERF_COUNT1_SEL(rbbm_perfcounter1_select_reg, perf_count1_sel) \ + rbbm_perfcounter1_select_reg = (rbbm_perfcounter1_select_reg & ~RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) | (perf_count1_sel << RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_select_t { + unsigned int perf_count1_sel : RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE; + unsigned int : 26; + } rbbm_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_select_t { + unsigned int : 26; + unsigned int perf_count1_sel : RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE; + } rbbm_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_perfcounter1_select_t f; +} rbbm_perfcounter1_select_u; + + +/* + * RBBM_PERFCOUNTER1_LO struct + */ + +#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE 32 + +#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT 0 + +#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK 0xffffffff + +#define RBBM_PERFCOUNTER1_LO_MASK \ + (RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) + +#define RBBM_PERFCOUNTER1_LO(perf_count1_lo) \ + ((perf_count1_lo << RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT)) + +#define RBBM_PERFCOUNTER1_LO_GET_PERF_COUNT1_LO(rbbm_perfcounter1_lo) \ + ((rbbm_perfcounter1_lo & RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) >> RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT) + +#define RBBM_PERFCOUNTER1_LO_SET_PERF_COUNT1_LO(rbbm_perfcounter1_lo_reg, perf_count1_lo) \ + rbbm_perfcounter1_lo_reg = (rbbm_perfcounter1_lo_reg & ~RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) | (perf_count1_lo << RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_lo_t { + unsigned int perf_count1_lo : RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE; + } rbbm_perfcounter1_lo_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_lo_t { + unsigned int perf_count1_lo : RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE; + } rbbm_perfcounter1_lo_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_perfcounter1_lo_t f; +} rbbm_perfcounter1_lo_u; + + +/* + * RBBM_PERFCOUNTER1_HI struct + */ + +#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE 16 + +#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT 0 + +#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK 0x0000ffff + +#define RBBM_PERFCOUNTER1_HI_MASK \ + (RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) + +#define RBBM_PERFCOUNTER1_HI(perf_count1_hi) \ + ((perf_count1_hi << RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT)) + +#define RBBM_PERFCOUNTER1_HI_GET_PERF_COUNT1_HI(rbbm_perfcounter1_hi) \ + ((rbbm_perfcounter1_hi & RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) >> RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT) + +#define RBBM_PERFCOUNTER1_HI_SET_PERF_COUNT1_HI(rbbm_perfcounter1_hi_reg, perf_count1_hi) \ + rbbm_perfcounter1_hi_reg = (rbbm_perfcounter1_hi_reg & ~RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) | (perf_count1_hi << RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_hi_t { + unsigned int perf_count1_hi : RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE; + unsigned int : 16; + } rbbm_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_count1_hi : RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE; + } rbbm_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_perfcounter1_hi_t f; +} rbbm_perfcounter1_hi_u; + + +#endif + + +#if !defined (_MH_FIDDLE_H) +#define _MH_FIDDLE_H + +/***************************************************************************************************************** + * + * mh_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * MH_ARBITER_CONFIG struct + */ + +#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE 6 +#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE 1 +#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE 1 +#define MH_ARBITER_CONFIG_PAGE_SIZE_SIZE 3 +#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE 6 +#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SIZE 1 + +#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT 0 +#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT 6 +#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT 7 +#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT 8 +#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT 9 +#define MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT 10 +#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT 13 +#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT 14 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT 15 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT 16 +#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT 22 +#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT 23 +#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT 24 +#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT 25 +#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT 26 + +#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK 0x0000003f +#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK 0x00000040 +#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK 0x00000080 +#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK 0x00000100 +#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK 0x00000200 +#define MH_ARBITER_CONFIG_PAGE_SIZE_MASK 0x00001c00 +#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00002000 +#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK 0x00004000 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK 0x00008000 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK 0x003f0000 +#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK 0x00400000 +#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK 0x00800000 +#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK 0x01000000 +#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK 0x02000000 +#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK 0x04000000 + +#define MH_ARBITER_CONFIG_MASK \ + (MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK | \ + MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK | \ + MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK | \ + MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK | \ + MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK | \ + MH_ARBITER_CONFIG_PAGE_SIZE_MASK | \ + MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK | \ + MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK | \ + MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK | \ + MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK | \ + MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK | \ + MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK | \ + MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK | \ + MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK | \ + MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK) + +#define MH_ARBITER_CONFIG(same_page_limit, same_page_granularity, l1_arb_enable, l1_arb_hold_enable, l2_arb_control, page_size, tc_reorder_enable, tc_arb_hold_enable, in_flight_limit_enable, in_flight_limit, cp_clnt_enable, vgt_clnt_enable, tc_clnt_enable, rb_clnt_enable, pa_clnt_enable) \ + ((same_page_limit << MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT) | \ + (same_page_granularity << MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT) | \ + (l1_arb_enable << MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT) | \ + (l1_arb_hold_enable << MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT) | \ + (l2_arb_control << MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT) | \ + (page_size << MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT) | \ + (tc_reorder_enable << MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) | \ + (tc_arb_hold_enable << MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT) | \ + (in_flight_limit_enable << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT) | \ + (in_flight_limit << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT) | \ + (cp_clnt_enable << MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT) | \ + (vgt_clnt_enable << MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT) | \ + (tc_clnt_enable << MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT) | \ + (rb_clnt_enable << MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT) | \ + (pa_clnt_enable << MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT)) + +#define MH_ARBITER_CONFIG_GET_SAME_PAGE_LIMIT(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK) >> MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT) +#define MH_ARBITER_CONFIG_GET_SAME_PAGE_GRANULARITY(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK) >> MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT) +#define MH_ARBITER_CONFIG_GET_L1_ARB_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK) >> MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_L1_ARB_HOLD_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK) >> MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_L2_ARB_CONTROL(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK) >> MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT) +#define MH_ARBITER_CONFIG_GET_PAGE_SIZE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_PAGE_SIZE_MASK) >> MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT) +#define MH_ARBITER_CONFIG_GET_TC_REORDER_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_TC_ARB_HOLD_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_IN_FLIGHT_LIMIT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK) >> MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_IN_FLIGHT_LIMIT(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK) >> MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT) +#define MH_ARBITER_CONFIG_GET_CP_CLNT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_VGT_CLNT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_TC_CLNT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_RB_CLNT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_PA_CLNT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT) + +#define MH_ARBITER_CONFIG_SET_SAME_PAGE_LIMIT(mh_arbiter_config_reg, same_page_limit) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK) | (same_page_limit << MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT) +#define MH_ARBITER_CONFIG_SET_SAME_PAGE_GRANULARITY(mh_arbiter_config_reg, same_page_granularity) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK) | (same_page_granularity << MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT) +#define MH_ARBITER_CONFIG_SET_L1_ARB_ENABLE(mh_arbiter_config_reg, l1_arb_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK) | (l1_arb_enable << MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_L1_ARB_HOLD_ENABLE(mh_arbiter_config_reg, l1_arb_hold_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK) | (l1_arb_hold_enable << MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_L2_ARB_CONTROL(mh_arbiter_config_reg, l2_arb_control) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK) | (l2_arb_control << MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT) +#define MH_ARBITER_CONFIG_SET_PAGE_SIZE(mh_arbiter_config_reg, page_size) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_PAGE_SIZE_MASK) | (page_size << MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT) +#define MH_ARBITER_CONFIG_SET_TC_REORDER_ENABLE(mh_arbiter_config_reg, tc_reorder_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) | (tc_reorder_enable << MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_TC_ARB_HOLD_ENABLE(mh_arbiter_config_reg, tc_arb_hold_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK) | (tc_arb_hold_enable << MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_IN_FLIGHT_LIMIT_ENABLE(mh_arbiter_config_reg, in_flight_limit_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK) | (in_flight_limit_enable << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_IN_FLIGHT_LIMIT(mh_arbiter_config_reg, in_flight_limit) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK) | (in_flight_limit << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT) +#define MH_ARBITER_CONFIG_SET_CP_CLNT_ENABLE(mh_arbiter_config_reg, cp_clnt_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK) | (cp_clnt_enable << MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_VGT_CLNT_ENABLE(mh_arbiter_config_reg, vgt_clnt_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK) | (vgt_clnt_enable << MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_TC_CLNT_ENABLE(mh_arbiter_config_reg, tc_clnt_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK) | (tc_clnt_enable << MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_RB_CLNT_ENABLE(mh_arbiter_config_reg, rb_clnt_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK) | (rb_clnt_enable << MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_PA_CLNT_ENABLE(mh_arbiter_config_reg, pa_clnt_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK) | (pa_clnt_enable << MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_arbiter_config_t { + unsigned int same_page_limit : MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE; + unsigned int same_page_granularity : MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE; + unsigned int l1_arb_enable : MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE; + unsigned int l1_arb_hold_enable : MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE; + unsigned int l2_arb_control : MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE; + unsigned int page_size : MH_ARBITER_CONFIG_PAGE_SIZE_SIZE; + unsigned int tc_reorder_enable : MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE; + unsigned int tc_arb_hold_enable : MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE; + unsigned int in_flight_limit_enable : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE; + unsigned int in_flight_limit : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE; + unsigned int cp_clnt_enable : MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE; + unsigned int vgt_clnt_enable : MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE; + unsigned int tc_clnt_enable : MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE; + unsigned int rb_clnt_enable : MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE; + unsigned int pa_clnt_enable : MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SIZE; + unsigned int : 5; + } mh_arbiter_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_arbiter_config_t { + unsigned int : 5; + unsigned int pa_clnt_enable : MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SIZE; + unsigned int rb_clnt_enable : MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE; + unsigned int tc_clnt_enable : MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE; + unsigned int vgt_clnt_enable : MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE; + unsigned int cp_clnt_enable : MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE; + unsigned int in_flight_limit : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE; + unsigned int in_flight_limit_enable : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE; + unsigned int tc_arb_hold_enable : MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE; + unsigned int tc_reorder_enable : MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE; + unsigned int page_size : MH_ARBITER_CONFIG_PAGE_SIZE_SIZE; + unsigned int l2_arb_control : MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE; + unsigned int l1_arb_hold_enable : MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE; + unsigned int l1_arb_enable : MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE; + unsigned int same_page_granularity : MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE; + unsigned int same_page_limit : MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE; + } mh_arbiter_config_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_arbiter_config_t f; +} mh_arbiter_config_u; + + +/* + * MH_CLNT_AXI_ID_REUSE struct + */ + +#define MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE 3 +#define MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE 1 +#define MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE 3 +#define MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE 1 +#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3 +#define MH_CLNT_AXI_ID_REUSE_RESERVED3_SIZE 1 +#define MH_CLNT_AXI_ID_REUSE_PAw_ID_SIZE 3 + +#define MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT 0 +#define MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT 3 +#define MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT 4 +#define MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT 7 +#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 8 +#define MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT 11 +#define MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT 12 + +#define MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK 0x00000007 +#define MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK 0x00000008 +#define MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK 0x00000070 +#define MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK 0x00000080 +#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x00000700 +#define MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK 0x00000800 +#define MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK 0x00007000 + +#define MH_CLNT_AXI_ID_REUSE_MASK \ + (MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK | \ + MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK | \ + MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK | \ + MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK | \ + MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK | \ + MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK | \ + MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK) + +#define MH_CLNT_AXI_ID_REUSE(cpw_id, reserved1, rbw_id, reserved2, mmur_id, reserved3, paw_id) \ + ((cpw_id << MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT) | \ + (reserved1 << MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT) | \ + (rbw_id << MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT) | \ + (reserved2 << MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT) | \ + (mmur_id << MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) | \ + (reserved3 << MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT) | \ + (paw_id << MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT)) + +#define MH_CLNT_AXI_ID_REUSE_GET_CPw_ID(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED1(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_RBw_ID(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED2(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_MMUr_ID(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED3(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_PAw_ID(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT) + +#define MH_CLNT_AXI_ID_REUSE_SET_CPw_ID(mh_clnt_axi_id_reuse_reg, cpw_id) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK) | (cpw_id << MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED1(mh_clnt_axi_id_reuse_reg, reserved1) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK) | (reserved1 << MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_RBw_ID(mh_clnt_axi_id_reuse_reg, rbw_id) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK) | (rbw_id << MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED2(mh_clnt_axi_id_reuse_reg, reserved2) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK) | (reserved2 << MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_MMUr_ID(mh_clnt_axi_id_reuse_reg, mmur_id) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mmur_id << MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED3(mh_clnt_axi_id_reuse_reg, reserved3) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK) | (reserved3 << MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_PAw_ID(mh_clnt_axi_id_reuse_reg, paw_id) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK) | (paw_id << MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_clnt_axi_id_reuse_t { + unsigned int cpw_id : MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE; + unsigned int reserved1 : MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE; + unsigned int rbw_id : MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE; + unsigned int reserved2 : MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE; + unsigned int mmur_id : MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int reserved3 : MH_CLNT_AXI_ID_REUSE_RESERVED3_SIZE; + unsigned int paw_id : MH_CLNT_AXI_ID_REUSE_PAw_ID_SIZE; + unsigned int : 17; + } mh_clnt_axi_id_reuse_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_clnt_axi_id_reuse_t { + unsigned int : 17; + unsigned int paw_id : MH_CLNT_AXI_ID_REUSE_PAw_ID_SIZE; + unsigned int reserved3 : MH_CLNT_AXI_ID_REUSE_RESERVED3_SIZE; + unsigned int mmur_id : MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int reserved2 : MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE; + unsigned int rbw_id : MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE; + unsigned int reserved1 : MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE; + unsigned int cpw_id : MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE; + } mh_clnt_axi_id_reuse_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_clnt_axi_id_reuse_t f; +} mh_clnt_axi_id_reuse_u; + + +/* + * MH_INTERRUPT_MASK struct + */ + +#define MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE 1 +#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE 1 +#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE 1 + +#define MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT 0 +#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT 1 +#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT 2 + +#define MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK 0x00000001 +#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK 0x00000002 +#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK 0x00000004 + +#define MH_INTERRUPT_MASK_MASK \ + (MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK | \ + MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK | \ + MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) + +#define MH_INTERRUPT_MASK(axi_read_error, axi_write_error, mmu_page_fault) \ + ((axi_read_error << MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT) | \ + (axi_write_error << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT) | \ + (mmu_page_fault << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT)) + +#define MH_INTERRUPT_MASK_GET_AXI_READ_ERROR(mh_interrupt_mask) \ + ((mh_interrupt_mask & MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_MASK_GET_AXI_WRITE_ERROR(mh_interrupt_mask) \ + ((mh_interrupt_mask & MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_MASK_GET_MMU_PAGE_FAULT(mh_interrupt_mask) \ + ((mh_interrupt_mask & MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT) + +#define MH_INTERRUPT_MASK_SET_AXI_READ_ERROR(mh_interrupt_mask_reg, axi_read_error) \ + mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_MASK_SET_AXI_WRITE_ERROR(mh_interrupt_mask_reg, axi_write_error) \ + mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_MASK_SET_MMU_PAGE_FAULT(mh_interrupt_mask_reg, mmu_page_fault) \ + mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_interrupt_mask_t { + unsigned int axi_read_error : MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE; + unsigned int mmu_page_fault : MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE; + unsigned int : 29; + } mh_interrupt_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_interrupt_mask_t { + unsigned int : 29; + unsigned int mmu_page_fault : MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE; + unsigned int axi_read_error : MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE; + } mh_interrupt_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_interrupt_mask_t f; +} mh_interrupt_mask_u; + + +/* + * MH_INTERRUPT_STATUS struct + */ + +#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE 1 +#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE 1 +#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE 1 + +#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT 0 +#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT 1 +#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT 2 + +#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK 0x00000001 +#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK 0x00000002 +#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK 0x00000004 + +#define MH_INTERRUPT_STATUS_MASK \ + (MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK | \ + MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK | \ + MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) + +#define MH_INTERRUPT_STATUS(axi_read_error, axi_write_error, mmu_page_fault) \ + ((axi_read_error << MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT) | \ + (axi_write_error << MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT) | \ + (mmu_page_fault << MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT)) + +#define MH_INTERRUPT_STATUS_GET_AXI_READ_ERROR(mh_interrupt_status) \ + ((mh_interrupt_status & MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_STATUS_GET_AXI_WRITE_ERROR(mh_interrupt_status) \ + ((mh_interrupt_status & MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_STATUS_GET_MMU_PAGE_FAULT(mh_interrupt_status) \ + ((mh_interrupt_status & MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT) + +#define MH_INTERRUPT_STATUS_SET_AXI_READ_ERROR(mh_interrupt_status_reg, axi_read_error) \ + mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_STATUS_SET_AXI_WRITE_ERROR(mh_interrupt_status_reg, axi_write_error) \ + mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_STATUS_SET_MMU_PAGE_FAULT(mh_interrupt_status_reg, mmu_page_fault) \ + mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_interrupt_status_t { + unsigned int axi_read_error : MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE; + unsigned int mmu_page_fault : MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE; + unsigned int : 29; + } mh_interrupt_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_interrupt_status_t { + unsigned int : 29; + unsigned int mmu_page_fault : MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE; + unsigned int axi_read_error : MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE; + } mh_interrupt_status_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_interrupt_status_t f; +} mh_interrupt_status_u; + + +/* + * MH_INTERRUPT_CLEAR struct + */ + +#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE 1 +#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE 1 +#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE 1 + +#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT 0 +#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT 1 +#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT 2 + +#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK 0x00000001 +#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK 0x00000002 +#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK 0x00000004 + +#define MH_INTERRUPT_CLEAR_MASK \ + (MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK | \ + MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK | \ + MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) + +#define MH_INTERRUPT_CLEAR(axi_read_error, axi_write_error, mmu_page_fault) \ + ((axi_read_error << MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT) | \ + (axi_write_error << MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT) | \ + (mmu_page_fault << MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT)) + +#define MH_INTERRUPT_CLEAR_GET_AXI_READ_ERROR(mh_interrupt_clear) \ + ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_CLEAR_GET_AXI_WRITE_ERROR(mh_interrupt_clear) \ + ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_CLEAR_GET_MMU_PAGE_FAULT(mh_interrupt_clear) \ + ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT) + +#define MH_INTERRUPT_CLEAR_SET_AXI_READ_ERROR(mh_interrupt_clear_reg, axi_read_error) \ + mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_CLEAR_SET_AXI_WRITE_ERROR(mh_interrupt_clear_reg, axi_write_error) \ + mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_CLEAR_SET_MMU_PAGE_FAULT(mh_interrupt_clear_reg, mmu_page_fault) \ + mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_interrupt_clear_t { + unsigned int axi_read_error : MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE; + unsigned int mmu_page_fault : MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE; + unsigned int : 29; + } mh_interrupt_clear_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_interrupt_clear_t { + unsigned int : 29; + unsigned int mmu_page_fault : MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE; + unsigned int axi_read_error : MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE; + } mh_interrupt_clear_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_interrupt_clear_t f; +} mh_interrupt_clear_u; + + +/* + * MH_AXI_ERROR struct + */ + +#define MH_AXI_ERROR_AXI_READ_ID_SIZE 3 +#define MH_AXI_ERROR_AXI_READ_ERROR_SIZE 1 +#define MH_AXI_ERROR_AXI_WRITE_ID_SIZE 3 +#define MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE 1 + +#define MH_AXI_ERROR_AXI_READ_ID_SHIFT 0 +#define MH_AXI_ERROR_AXI_READ_ERROR_SHIFT 3 +#define MH_AXI_ERROR_AXI_WRITE_ID_SHIFT 4 +#define MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT 7 + +#define MH_AXI_ERROR_AXI_READ_ID_MASK 0x00000007 +#define MH_AXI_ERROR_AXI_READ_ERROR_MASK 0x00000008 +#define MH_AXI_ERROR_AXI_WRITE_ID_MASK 0x00000070 +#define MH_AXI_ERROR_AXI_WRITE_ERROR_MASK 0x00000080 + +#define MH_AXI_ERROR_MASK \ + (MH_AXI_ERROR_AXI_READ_ID_MASK | \ + MH_AXI_ERROR_AXI_READ_ERROR_MASK | \ + MH_AXI_ERROR_AXI_WRITE_ID_MASK | \ + MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) + +#define MH_AXI_ERROR(axi_read_id, axi_read_error, axi_write_id, axi_write_error) \ + ((axi_read_id << MH_AXI_ERROR_AXI_READ_ID_SHIFT) | \ + (axi_read_error << MH_AXI_ERROR_AXI_READ_ERROR_SHIFT) | \ + (axi_write_id << MH_AXI_ERROR_AXI_WRITE_ID_SHIFT) | \ + (axi_write_error << MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT)) + +#define MH_AXI_ERROR_GET_AXI_READ_ID(mh_axi_error) \ + ((mh_axi_error & MH_AXI_ERROR_AXI_READ_ID_MASK) >> MH_AXI_ERROR_AXI_READ_ID_SHIFT) +#define MH_AXI_ERROR_GET_AXI_READ_ERROR(mh_axi_error) \ + ((mh_axi_error & MH_AXI_ERROR_AXI_READ_ERROR_MASK) >> MH_AXI_ERROR_AXI_READ_ERROR_SHIFT) +#define MH_AXI_ERROR_GET_AXI_WRITE_ID(mh_axi_error) \ + ((mh_axi_error & MH_AXI_ERROR_AXI_WRITE_ID_MASK) >> MH_AXI_ERROR_AXI_WRITE_ID_SHIFT) +#define MH_AXI_ERROR_GET_AXI_WRITE_ERROR(mh_axi_error) \ + ((mh_axi_error & MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) >> MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT) + +#define MH_AXI_ERROR_SET_AXI_READ_ID(mh_axi_error_reg, axi_read_id) \ + mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_READ_ID_MASK) | (axi_read_id << MH_AXI_ERROR_AXI_READ_ID_SHIFT) +#define MH_AXI_ERROR_SET_AXI_READ_ERROR(mh_axi_error_reg, axi_read_error) \ + mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_READ_ERROR_MASK) | (axi_read_error << MH_AXI_ERROR_AXI_READ_ERROR_SHIFT) +#define MH_AXI_ERROR_SET_AXI_WRITE_ID(mh_axi_error_reg, axi_write_id) \ + mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_WRITE_ID_MASK) | (axi_write_id << MH_AXI_ERROR_AXI_WRITE_ID_SHIFT) +#define MH_AXI_ERROR_SET_AXI_WRITE_ERROR(mh_axi_error_reg, axi_write_error) \ + mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_axi_error_t { + unsigned int axi_read_id : MH_AXI_ERROR_AXI_READ_ID_SIZE; + unsigned int axi_read_error : MH_AXI_ERROR_AXI_READ_ERROR_SIZE; + unsigned int axi_write_id : MH_AXI_ERROR_AXI_WRITE_ID_SIZE; + unsigned int axi_write_error : MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE; + unsigned int : 24; + } mh_axi_error_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_axi_error_t { + unsigned int : 24; + unsigned int axi_write_error : MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE; + unsigned int axi_write_id : MH_AXI_ERROR_AXI_WRITE_ID_SIZE; + unsigned int axi_read_error : MH_AXI_ERROR_AXI_READ_ERROR_SIZE; + unsigned int axi_read_id : MH_AXI_ERROR_AXI_READ_ID_SIZE; + } mh_axi_error_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_axi_error_t f; +} mh_axi_error_u; + + +/* + * MH_PERFCOUNTER0_SELECT struct + */ + +#define MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define MH_PERFCOUNTER0_SELECT_MASK \ + (MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define MH_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define MH_PERFCOUNTER0_SELECT_GET_PERF_SEL(mh_perfcounter0_select) \ + ((mh_perfcounter0_select & MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define MH_PERFCOUNTER0_SELECT_SET_PERF_SEL(mh_perfcounter0_select_reg, perf_sel) \ + mh_perfcounter0_select_reg = (mh_perfcounter0_select_reg & ~MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter0_select_t { + unsigned int perf_sel : MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } mh_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } mh_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter0_select_t f; +} mh_perfcounter0_select_u; + + +/* + * MH_PERFCOUNTER1_SELECT struct + */ + +#define MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8 + +#define MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0 + +#define MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff + +#define MH_PERFCOUNTER1_SELECT_MASK \ + (MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) + +#define MH_PERFCOUNTER1_SELECT(perf_sel) \ + ((perf_sel << MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)) + +#define MH_PERFCOUNTER1_SELECT_GET_PERF_SEL(mh_perfcounter1_select) \ + ((mh_perfcounter1_select & MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#define MH_PERFCOUNTER1_SELECT_SET_PERF_SEL(mh_perfcounter1_select_reg, perf_sel) \ + mh_perfcounter1_select_reg = (mh_perfcounter1_select_reg & ~MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter1_select_t { + unsigned int perf_sel : MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } mh_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter1_select_t { + unsigned int : 24; + unsigned int perf_sel : MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + } mh_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter1_select_t f; +} mh_perfcounter1_select_u; + + +/* + * MH_PERFCOUNTER0_CONFIG struct + */ + +#define MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE 8 + +#define MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT 0 + +#define MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK 0x000000ff + +#define MH_PERFCOUNTER0_CONFIG_MASK \ + (MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) + +#define MH_PERFCOUNTER0_CONFIG(n_value) \ + ((n_value << MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT)) + +#define MH_PERFCOUNTER0_CONFIG_GET_N_VALUE(mh_perfcounter0_config) \ + ((mh_perfcounter0_config & MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) >> MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT) + +#define MH_PERFCOUNTER0_CONFIG_SET_N_VALUE(mh_perfcounter0_config_reg, n_value) \ + mh_perfcounter0_config_reg = (mh_perfcounter0_config_reg & ~MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) | (n_value << MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter0_config_t { + unsigned int n_value : MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE; + unsigned int : 24; + } mh_perfcounter0_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter0_config_t { + unsigned int : 24; + unsigned int n_value : MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE; + } mh_perfcounter0_config_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter0_config_t f; +} mh_perfcounter0_config_u; + + +/* + * MH_PERFCOUNTER1_CONFIG struct + */ + +#define MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE 8 + +#define MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT 0 + +#define MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK 0x000000ff + +#define MH_PERFCOUNTER1_CONFIG_MASK \ + (MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) + +#define MH_PERFCOUNTER1_CONFIG(n_value) \ + ((n_value << MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT)) + +#define MH_PERFCOUNTER1_CONFIG_GET_N_VALUE(mh_perfcounter1_config) \ + ((mh_perfcounter1_config & MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) >> MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT) + +#define MH_PERFCOUNTER1_CONFIG_SET_N_VALUE(mh_perfcounter1_config_reg, n_value) \ + mh_perfcounter1_config_reg = (mh_perfcounter1_config_reg & ~MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) | (n_value << MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter1_config_t { + unsigned int n_value : MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE; + unsigned int : 24; + } mh_perfcounter1_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter1_config_t { + unsigned int : 24; + unsigned int n_value : MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE; + } mh_perfcounter1_config_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter1_config_t f; +} mh_perfcounter1_config_u; + + +/* + * MH_PERFCOUNTER0_LOW struct + */ + +#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE 32 + +#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT 0 + +#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK 0xffffffff + +#define MH_PERFCOUNTER0_LOW_MASK \ + (MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) + +#define MH_PERFCOUNTER0_LOW(perf_counter_low) \ + ((perf_counter_low << MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT)) + +#define MH_PERFCOUNTER0_LOW_GET_PERF_COUNTER_LOW(mh_perfcounter0_low) \ + ((mh_perfcounter0_low & MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) >> MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT) + +#define MH_PERFCOUNTER0_LOW_SET_PERF_COUNTER_LOW(mh_perfcounter0_low_reg, perf_counter_low) \ + mh_perfcounter0_low_reg = (mh_perfcounter0_low_reg & ~MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) | (perf_counter_low << MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter0_low_t { + unsigned int perf_counter_low : MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE; + } mh_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter0_low_t { + unsigned int perf_counter_low : MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE; + } mh_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter0_low_t f; +} mh_perfcounter0_low_u; + + +/* + * MH_PERFCOUNTER1_LOW struct + */ + +#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE 32 + +#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT 0 + +#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK 0xffffffff + +#define MH_PERFCOUNTER1_LOW_MASK \ + (MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) + +#define MH_PERFCOUNTER1_LOW(perf_counter_low) \ + ((perf_counter_low << MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT)) + +#define MH_PERFCOUNTER1_LOW_GET_PERF_COUNTER_LOW(mh_perfcounter1_low) \ + ((mh_perfcounter1_low & MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) >> MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT) + +#define MH_PERFCOUNTER1_LOW_SET_PERF_COUNTER_LOW(mh_perfcounter1_low_reg, perf_counter_low) \ + mh_perfcounter1_low_reg = (mh_perfcounter1_low_reg & ~MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) | (perf_counter_low << MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter1_low_t { + unsigned int perf_counter_low : MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE; + } mh_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter1_low_t { + unsigned int perf_counter_low : MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE; + } mh_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter1_low_t f; +} mh_perfcounter1_low_u; + + +/* + * MH_PERFCOUNTER0_HI struct + */ + +#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE 16 + +#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT 0 + +#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK 0x0000ffff + +#define MH_PERFCOUNTER0_HI_MASK \ + (MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) + +#define MH_PERFCOUNTER0_HI(perf_counter_hi) \ + ((perf_counter_hi << MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT)) + +#define MH_PERFCOUNTER0_HI_GET_PERF_COUNTER_HI(mh_perfcounter0_hi) \ + ((mh_perfcounter0_hi & MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) >> MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT) + +#define MH_PERFCOUNTER0_HI_SET_PERF_COUNTER_HI(mh_perfcounter0_hi_reg, perf_counter_hi) \ + mh_perfcounter0_hi_reg = (mh_perfcounter0_hi_reg & ~MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) | (perf_counter_hi << MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter0_hi_t { + unsigned int perf_counter_hi : MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE; + unsigned int : 16; + } mh_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_counter_hi : MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE; + } mh_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter0_hi_t f; +} mh_perfcounter0_hi_u; + + +/* + * MH_PERFCOUNTER1_HI struct + */ + +#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE 16 + +#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT 0 + +#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK 0x0000ffff + +#define MH_PERFCOUNTER1_HI_MASK \ + (MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) + +#define MH_PERFCOUNTER1_HI(perf_counter_hi) \ + ((perf_counter_hi << MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT)) + +#define MH_PERFCOUNTER1_HI_GET_PERF_COUNTER_HI(mh_perfcounter1_hi) \ + ((mh_perfcounter1_hi & MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) >> MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT) + +#define MH_PERFCOUNTER1_HI_SET_PERF_COUNTER_HI(mh_perfcounter1_hi_reg, perf_counter_hi) \ + mh_perfcounter1_hi_reg = (mh_perfcounter1_hi_reg & ~MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) | (perf_counter_hi << MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter1_hi_t { + unsigned int perf_counter_hi : MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE; + unsigned int : 16; + } mh_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_counter_hi : MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE; + } mh_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter1_hi_t f; +} mh_perfcounter1_hi_u; + + +/* + * MH_DEBUG_CTRL struct + */ + +#define MH_DEBUG_CTRL_INDEX_SIZE 6 + +#define MH_DEBUG_CTRL_INDEX_SHIFT 0 + +#define MH_DEBUG_CTRL_INDEX_MASK 0x0000003f + +#define MH_DEBUG_CTRL_MASK \ + (MH_DEBUG_CTRL_INDEX_MASK) + +#define MH_DEBUG_CTRL(index) \ + ((index << MH_DEBUG_CTRL_INDEX_SHIFT)) + +#define MH_DEBUG_CTRL_GET_INDEX(mh_debug_ctrl) \ + ((mh_debug_ctrl & MH_DEBUG_CTRL_INDEX_MASK) >> MH_DEBUG_CTRL_INDEX_SHIFT) + +#define MH_DEBUG_CTRL_SET_INDEX(mh_debug_ctrl_reg, index) \ + mh_debug_ctrl_reg = (mh_debug_ctrl_reg & ~MH_DEBUG_CTRL_INDEX_MASK) | (index << MH_DEBUG_CTRL_INDEX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_ctrl_t { + unsigned int index : MH_DEBUG_CTRL_INDEX_SIZE; + unsigned int : 26; + } mh_debug_ctrl_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_ctrl_t { + unsigned int : 26; + unsigned int index : MH_DEBUG_CTRL_INDEX_SIZE; + } mh_debug_ctrl_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_ctrl_t f; +} mh_debug_ctrl_u; + + +/* + * MH_DEBUG_DATA struct + */ + +#define MH_DEBUG_DATA_DATA_SIZE 32 + +#define MH_DEBUG_DATA_DATA_SHIFT 0 + +#define MH_DEBUG_DATA_DATA_MASK 0xffffffff + +#define MH_DEBUG_DATA_MASK \ + (MH_DEBUG_DATA_DATA_MASK) + +#define MH_DEBUG_DATA(data) \ + ((data << MH_DEBUG_DATA_DATA_SHIFT)) + +#define MH_DEBUG_DATA_GET_DATA(mh_debug_data) \ + ((mh_debug_data & MH_DEBUG_DATA_DATA_MASK) >> MH_DEBUG_DATA_DATA_SHIFT) + +#define MH_DEBUG_DATA_SET_DATA(mh_debug_data_reg, data) \ + mh_debug_data_reg = (mh_debug_data_reg & ~MH_DEBUG_DATA_DATA_MASK) | (data << MH_DEBUG_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_data_t { + unsigned int data : MH_DEBUG_DATA_DATA_SIZE; + } mh_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_data_t { + unsigned int data : MH_DEBUG_DATA_DATA_SIZE; + } mh_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_data_t f; +} mh_debug_data_u; + + +/* + * MH_AXI_HALT_CONTROL struct + */ + +#define MH_AXI_HALT_CONTROL_AXI_HALT_SIZE 1 + +#define MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT 0 + +#define MH_AXI_HALT_CONTROL_AXI_HALT_MASK 0x00000001 + +#define MH_AXI_HALT_CONTROL_MASK \ + (MH_AXI_HALT_CONTROL_AXI_HALT_MASK) + +#define MH_AXI_HALT_CONTROL(axi_halt) \ + ((axi_halt << MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT)) + +#define MH_AXI_HALT_CONTROL_GET_AXI_HALT(mh_axi_halt_control) \ + ((mh_axi_halt_control & MH_AXI_HALT_CONTROL_AXI_HALT_MASK) >> MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT) + +#define MH_AXI_HALT_CONTROL_SET_AXI_HALT(mh_axi_halt_control_reg, axi_halt) \ + mh_axi_halt_control_reg = (mh_axi_halt_control_reg & ~MH_AXI_HALT_CONTROL_AXI_HALT_MASK) | (axi_halt << MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_axi_halt_control_t { + unsigned int axi_halt : MH_AXI_HALT_CONTROL_AXI_HALT_SIZE; + unsigned int : 31; + } mh_axi_halt_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_axi_halt_control_t { + unsigned int : 31; + unsigned int axi_halt : MH_AXI_HALT_CONTROL_AXI_HALT_SIZE; + } mh_axi_halt_control_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_axi_halt_control_t f; +} mh_axi_halt_control_u; + + +/* + * MH_DEBUG_REG00 struct + */ + +#define MH_DEBUG_REG00_MH_BUSY_SIZE 1 +#define MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE 1 +#define MH_DEBUG_REG00_CP_REQUEST_SIZE 1 +#define MH_DEBUG_REG00_VGT_REQUEST_SIZE 1 +#define MH_DEBUG_REG00_TC_REQUEST_SIZE 1 +#define MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE 1 +#define MH_DEBUG_REG00_TC_CAM_FULL_SIZE 1 +#define MH_DEBUG_REG00_TCD_EMPTY_SIZE 1 +#define MH_DEBUG_REG00_TCD_FULL_SIZE 1 +#define MH_DEBUG_REG00_RB_REQUEST_SIZE 1 +#define MH_DEBUG_REG00_PA_REQUEST_SIZE 1 +#define MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE 1 +#define MH_DEBUG_REG00_ARQ_EMPTY_SIZE 1 +#define MH_DEBUG_REG00_ARQ_FULL_SIZE 1 +#define MH_DEBUG_REG00_WDB_EMPTY_SIZE 1 +#define MH_DEBUG_REG00_WDB_FULL_SIZE 1 +#define MH_DEBUG_REG00_AXI_AVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_AREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_ARVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_ARREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_WVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_WREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_RVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_RREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_BVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_BREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_HALT_REQ_SIZE 1 +#define MH_DEBUG_REG00_AXI_HALT_ACK_SIZE 1 +#define MH_DEBUG_REG00_AXI_RDY_ENA_SIZE 1 + +#define MH_DEBUG_REG00_MH_BUSY_SHIFT 0 +#define MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT 1 +#define MH_DEBUG_REG00_CP_REQUEST_SHIFT 2 +#define MH_DEBUG_REG00_VGT_REQUEST_SHIFT 3 +#define MH_DEBUG_REG00_TC_REQUEST_SHIFT 4 +#define MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT 5 +#define MH_DEBUG_REG00_TC_CAM_FULL_SHIFT 6 +#define MH_DEBUG_REG00_TCD_EMPTY_SHIFT 7 +#define MH_DEBUG_REG00_TCD_FULL_SHIFT 8 +#define MH_DEBUG_REG00_RB_REQUEST_SHIFT 9 +#define MH_DEBUG_REG00_PA_REQUEST_SHIFT 10 +#define MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT 11 +#define MH_DEBUG_REG00_ARQ_EMPTY_SHIFT 12 +#define MH_DEBUG_REG00_ARQ_FULL_SHIFT 13 +#define MH_DEBUG_REG00_WDB_EMPTY_SHIFT 14 +#define MH_DEBUG_REG00_WDB_FULL_SHIFT 15 +#define MH_DEBUG_REG00_AXI_AVALID_SHIFT 16 +#define MH_DEBUG_REG00_AXI_AREADY_SHIFT 17 +#define MH_DEBUG_REG00_AXI_ARVALID_SHIFT 18 +#define MH_DEBUG_REG00_AXI_ARREADY_SHIFT 19 +#define MH_DEBUG_REG00_AXI_WVALID_SHIFT 20 +#define MH_DEBUG_REG00_AXI_WREADY_SHIFT 21 +#define MH_DEBUG_REG00_AXI_RVALID_SHIFT 22 +#define MH_DEBUG_REG00_AXI_RREADY_SHIFT 23 +#define MH_DEBUG_REG00_AXI_BVALID_SHIFT 24 +#define MH_DEBUG_REG00_AXI_BREADY_SHIFT 25 +#define MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT 26 +#define MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT 27 +#define MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT 28 + +#define MH_DEBUG_REG00_MH_BUSY_MASK 0x00000001 +#define MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK 0x00000002 +#define MH_DEBUG_REG00_CP_REQUEST_MASK 0x00000004 +#define MH_DEBUG_REG00_VGT_REQUEST_MASK 0x00000008 +#define MH_DEBUG_REG00_TC_REQUEST_MASK 0x00000010 +#define MH_DEBUG_REG00_TC_CAM_EMPTY_MASK 0x00000020 +#define MH_DEBUG_REG00_TC_CAM_FULL_MASK 0x00000040 +#define MH_DEBUG_REG00_TCD_EMPTY_MASK 0x00000080 +#define MH_DEBUG_REG00_TCD_FULL_MASK 0x00000100 +#define MH_DEBUG_REG00_RB_REQUEST_MASK 0x00000200 +#define MH_DEBUG_REG00_PA_REQUEST_MASK 0x00000400 +#define MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK 0x00000800 +#define MH_DEBUG_REG00_ARQ_EMPTY_MASK 0x00001000 +#define MH_DEBUG_REG00_ARQ_FULL_MASK 0x00002000 +#define MH_DEBUG_REG00_WDB_EMPTY_MASK 0x00004000 +#define MH_DEBUG_REG00_WDB_FULL_MASK 0x00008000 +#define MH_DEBUG_REG00_AXI_AVALID_MASK 0x00010000 +#define MH_DEBUG_REG00_AXI_AREADY_MASK 0x00020000 +#define MH_DEBUG_REG00_AXI_ARVALID_MASK 0x00040000 +#define MH_DEBUG_REG00_AXI_ARREADY_MASK 0x00080000 +#define MH_DEBUG_REG00_AXI_WVALID_MASK 0x00100000 +#define MH_DEBUG_REG00_AXI_WREADY_MASK 0x00200000 +#define MH_DEBUG_REG00_AXI_RVALID_MASK 0x00400000 +#define MH_DEBUG_REG00_AXI_RREADY_MASK 0x00800000 +#define MH_DEBUG_REG00_AXI_BVALID_MASK 0x01000000 +#define MH_DEBUG_REG00_AXI_BREADY_MASK 0x02000000 +#define MH_DEBUG_REG00_AXI_HALT_REQ_MASK 0x04000000 +#define MH_DEBUG_REG00_AXI_HALT_ACK_MASK 0x08000000 +#define MH_DEBUG_REG00_AXI_RDY_ENA_MASK 0x10000000 + +#define MH_DEBUG_REG00_MASK \ + (MH_DEBUG_REG00_MH_BUSY_MASK | \ + MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK | \ + MH_DEBUG_REG00_CP_REQUEST_MASK | \ + MH_DEBUG_REG00_VGT_REQUEST_MASK | \ + MH_DEBUG_REG00_TC_REQUEST_MASK | \ + MH_DEBUG_REG00_TC_CAM_EMPTY_MASK | \ + MH_DEBUG_REG00_TC_CAM_FULL_MASK | \ + MH_DEBUG_REG00_TCD_EMPTY_MASK | \ + MH_DEBUG_REG00_TCD_FULL_MASK | \ + MH_DEBUG_REG00_RB_REQUEST_MASK | \ + MH_DEBUG_REG00_PA_REQUEST_MASK | \ + MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK | \ + MH_DEBUG_REG00_ARQ_EMPTY_MASK | \ + MH_DEBUG_REG00_ARQ_FULL_MASK | \ + MH_DEBUG_REG00_WDB_EMPTY_MASK | \ + MH_DEBUG_REG00_WDB_FULL_MASK | \ + MH_DEBUG_REG00_AXI_AVALID_MASK | \ + MH_DEBUG_REG00_AXI_AREADY_MASK | \ + MH_DEBUG_REG00_AXI_ARVALID_MASK | \ + MH_DEBUG_REG00_AXI_ARREADY_MASK | \ + MH_DEBUG_REG00_AXI_WVALID_MASK | \ + MH_DEBUG_REG00_AXI_WREADY_MASK | \ + MH_DEBUG_REG00_AXI_RVALID_MASK | \ + MH_DEBUG_REG00_AXI_RREADY_MASK | \ + MH_DEBUG_REG00_AXI_BVALID_MASK | \ + MH_DEBUG_REG00_AXI_BREADY_MASK | \ + MH_DEBUG_REG00_AXI_HALT_REQ_MASK | \ + MH_DEBUG_REG00_AXI_HALT_ACK_MASK | \ + MH_DEBUG_REG00_AXI_RDY_ENA_MASK) + +#define MH_DEBUG_REG00(mh_busy, trans_outstanding, cp_request, vgt_request, tc_request, tc_cam_empty, tc_cam_full, tcd_empty, tcd_full, rb_request, pa_request, mh_clk_en_state, arq_empty, arq_full, wdb_empty, wdb_full, axi_avalid, axi_aready, axi_arvalid, axi_arready, axi_wvalid, axi_wready, axi_rvalid, axi_rready, axi_bvalid, axi_bready, axi_halt_req, axi_halt_ack, axi_rdy_ena) \ + ((mh_busy << MH_DEBUG_REG00_MH_BUSY_SHIFT) | \ + (trans_outstanding << MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT) | \ + (cp_request << MH_DEBUG_REG00_CP_REQUEST_SHIFT) | \ + (vgt_request << MH_DEBUG_REG00_VGT_REQUEST_SHIFT) | \ + (tc_request << MH_DEBUG_REG00_TC_REQUEST_SHIFT) | \ + (tc_cam_empty << MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT) | \ + (tc_cam_full << MH_DEBUG_REG00_TC_CAM_FULL_SHIFT) | \ + (tcd_empty << MH_DEBUG_REG00_TCD_EMPTY_SHIFT) | \ + (tcd_full << MH_DEBUG_REG00_TCD_FULL_SHIFT) | \ + (rb_request << MH_DEBUG_REG00_RB_REQUEST_SHIFT) | \ + (pa_request << MH_DEBUG_REG00_PA_REQUEST_SHIFT) | \ + (mh_clk_en_state << MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT) | \ + (arq_empty << MH_DEBUG_REG00_ARQ_EMPTY_SHIFT) | \ + (arq_full << MH_DEBUG_REG00_ARQ_FULL_SHIFT) | \ + (wdb_empty << MH_DEBUG_REG00_WDB_EMPTY_SHIFT) | \ + (wdb_full << MH_DEBUG_REG00_WDB_FULL_SHIFT) | \ + (axi_avalid << MH_DEBUG_REG00_AXI_AVALID_SHIFT) | \ + (axi_aready << MH_DEBUG_REG00_AXI_AREADY_SHIFT) | \ + (axi_arvalid << MH_DEBUG_REG00_AXI_ARVALID_SHIFT) | \ + (axi_arready << MH_DEBUG_REG00_AXI_ARREADY_SHIFT) | \ + (axi_wvalid << MH_DEBUG_REG00_AXI_WVALID_SHIFT) | \ + (axi_wready << MH_DEBUG_REG00_AXI_WREADY_SHIFT) | \ + (axi_rvalid << MH_DEBUG_REG00_AXI_RVALID_SHIFT) | \ + (axi_rready << MH_DEBUG_REG00_AXI_RREADY_SHIFT) | \ + (axi_bvalid << MH_DEBUG_REG00_AXI_BVALID_SHIFT) | \ + (axi_bready << MH_DEBUG_REG00_AXI_BREADY_SHIFT) | \ + (axi_halt_req << MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT) | \ + (axi_halt_ack << MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT) | \ + (axi_rdy_ena << MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT)) + +#define MH_DEBUG_REG00_GET_MH_BUSY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_MH_BUSY_MASK) >> MH_DEBUG_REG00_MH_BUSY_SHIFT) +#define MH_DEBUG_REG00_GET_TRANS_OUTSTANDING(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK) >> MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT) +#define MH_DEBUG_REG00_GET_CP_REQUEST(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_CP_REQUEST_MASK) >> MH_DEBUG_REG00_CP_REQUEST_SHIFT) +#define MH_DEBUG_REG00_GET_VGT_REQUEST(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_VGT_REQUEST_MASK) >> MH_DEBUG_REG00_VGT_REQUEST_SHIFT) +#define MH_DEBUG_REG00_GET_TC_REQUEST(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TC_REQUEST_MASK) >> MH_DEBUG_REG00_TC_REQUEST_SHIFT) +#define MH_DEBUG_REG00_GET_TC_CAM_EMPTY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TC_CAM_EMPTY_MASK) >> MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT) +#define MH_DEBUG_REG00_GET_TC_CAM_FULL(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TC_CAM_FULL_MASK) >> MH_DEBUG_REG00_TC_CAM_FULL_SHIFT) +#define MH_DEBUG_REG00_GET_TCD_EMPTY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TCD_EMPTY_MASK) >> MH_DEBUG_REG00_TCD_EMPTY_SHIFT) +#define MH_DEBUG_REG00_GET_TCD_FULL(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TCD_FULL_MASK) >> MH_DEBUG_REG00_TCD_FULL_SHIFT) +#define MH_DEBUG_REG00_GET_RB_REQUEST(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_RB_REQUEST_MASK) >> MH_DEBUG_REG00_RB_REQUEST_SHIFT) +#define MH_DEBUG_REG00_GET_PA_REQUEST(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_PA_REQUEST_MASK) >> MH_DEBUG_REG00_PA_REQUEST_SHIFT) +#define MH_DEBUG_REG00_GET_MH_CLK_EN_STATE(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK) >> MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT) +#define MH_DEBUG_REG00_GET_ARQ_EMPTY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_ARQ_EMPTY_MASK) >> MH_DEBUG_REG00_ARQ_EMPTY_SHIFT) +#define MH_DEBUG_REG00_GET_ARQ_FULL(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_ARQ_FULL_MASK) >> MH_DEBUG_REG00_ARQ_FULL_SHIFT) +#define MH_DEBUG_REG00_GET_WDB_EMPTY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_WDB_EMPTY_MASK) >> MH_DEBUG_REG00_WDB_EMPTY_SHIFT) +#define MH_DEBUG_REG00_GET_WDB_FULL(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_WDB_FULL_MASK) >> MH_DEBUG_REG00_WDB_FULL_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_AVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_AVALID_MASK) >> MH_DEBUG_REG00_AXI_AVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_AREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_AREADY_MASK) >> MH_DEBUG_REG00_AXI_AREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_ARVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_ARVALID_MASK) >> MH_DEBUG_REG00_AXI_ARVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_ARREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_ARREADY_MASK) >> MH_DEBUG_REG00_AXI_ARREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_WVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_WVALID_MASK) >> MH_DEBUG_REG00_AXI_WVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_WREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_WREADY_MASK) >> MH_DEBUG_REG00_AXI_WREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_RVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RVALID_MASK) >> MH_DEBUG_REG00_AXI_RVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_RREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RREADY_MASK) >> MH_DEBUG_REG00_AXI_RREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_BVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_BVALID_MASK) >> MH_DEBUG_REG00_AXI_BVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_BREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_BREADY_MASK) >> MH_DEBUG_REG00_AXI_BREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_HALT_REQ(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_HALT_REQ_MASK) >> MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_HALT_ACK(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_HALT_ACK_MASK) >> MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_RDY_ENA(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RDY_ENA_MASK) >> MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT) + +#define MH_DEBUG_REG00_SET_MH_BUSY(mh_debug_reg00_reg, mh_busy) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_MH_BUSY_MASK) | (mh_busy << MH_DEBUG_REG00_MH_BUSY_SHIFT) +#define MH_DEBUG_REG00_SET_TRANS_OUTSTANDING(mh_debug_reg00_reg, trans_outstanding) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK) | (trans_outstanding << MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT) +#define MH_DEBUG_REG00_SET_CP_REQUEST(mh_debug_reg00_reg, cp_request) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_CP_REQUEST_MASK) | (cp_request << MH_DEBUG_REG00_CP_REQUEST_SHIFT) +#define MH_DEBUG_REG00_SET_VGT_REQUEST(mh_debug_reg00_reg, vgt_request) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_VGT_REQUEST_MASK) | (vgt_request << MH_DEBUG_REG00_VGT_REQUEST_SHIFT) +#define MH_DEBUG_REG00_SET_TC_REQUEST(mh_debug_reg00_reg, tc_request) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_REQUEST_MASK) | (tc_request << MH_DEBUG_REG00_TC_REQUEST_SHIFT) +#define MH_DEBUG_REG00_SET_TC_CAM_EMPTY(mh_debug_reg00_reg, tc_cam_empty) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_CAM_EMPTY_MASK) | (tc_cam_empty << MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT) +#define MH_DEBUG_REG00_SET_TC_CAM_FULL(mh_debug_reg00_reg, tc_cam_full) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_CAM_FULL_MASK) | (tc_cam_full << MH_DEBUG_REG00_TC_CAM_FULL_SHIFT) +#define MH_DEBUG_REG00_SET_TCD_EMPTY(mh_debug_reg00_reg, tcd_empty) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TCD_EMPTY_MASK) | (tcd_empty << MH_DEBUG_REG00_TCD_EMPTY_SHIFT) +#define MH_DEBUG_REG00_SET_TCD_FULL(mh_debug_reg00_reg, tcd_full) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TCD_FULL_MASK) | (tcd_full << MH_DEBUG_REG00_TCD_FULL_SHIFT) +#define MH_DEBUG_REG00_SET_RB_REQUEST(mh_debug_reg00_reg, rb_request) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_RB_REQUEST_MASK) | (rb_request << MH_DEBUG_REG00_RB_REQUEST_SHIFT) +#define MH_DEBUG_REG00_SET_PA_REQUEST(mh_debug_reg00_reg, pa_request) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_PA_REQUEST_MASK) | (pa_request << MH_DEBUG_REG00_PA_REQUEST_SHIFT) +#define MH_DEBUG_REG00_SET_MH_CLK_EN_STATE(mh_debug_reg00_reg, mh_clk_en_state) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK) | (mh_clk_en_state << MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT) +#define MH_DEBUG_REG00_SET_ARQ_EMPTY(mh_debug_reg00_reg, arq_empty) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_ARQ_EMPTY_MASK) | (arq_empty << MH_DEBUG_REG00_ARQ_EMPTY_SHIFT) +#define MH_DEBUG_REG00_SET_ARQ_FULL(mh_debug_reg00_reg, arq_full) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_ARQ_FULL_MASK) | (arq_full << MH_DEBUG_REG00_ARQ_FULL_SHIFT) +#define MH_DEBUG_REG00_SET_WDB_EMPTY(mh_debug_reg00_reg, wdb_empty) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_WDB_EMPTY_MASK) | (wdb_empty << MH_DEBUG_REG00_WDB_EMPTY_SHIFT) +#define MH_DEBUG_REG00_SET_WDB_FULL(mh_debug_reg00_reg, wdb_full) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_WDB_FULL_MASK) | (wdb_full << MH_DEBUG_REG00_WDB_FULL_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_AVALID(mh_debug_reg00_reg, axi_avalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_AVALID_MASK) | (axi_avalid << MH_DEBUG_REG00_AXI_AVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_AREADY(mh_debug_reg00_reg, axi_aready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_AREADY_MASK) | (axi_aready << MH_DEBUG_REG00_AXI_AREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_ARVALID(mh_debug_reg00_reg, axi_arvalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_ARVALID_MASK) | (axi_arvalid << MH_DEBUG_REG00_AXI_ARVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_ARREADY(mh_debug_reg00_reg, axi_arready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_ARREADY_MASK) | (axi_arready << MH_DEBUG_REG00_AXI_ARREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_WVALID(mh_debug_reg00_reg, axi_wvalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_WVALID_MASK) | (axi_wvalid << MH_DEBUG_REG00_AXI_WVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_WREADY(mh_debug_reg00_reg, axi_wready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_WREADY_MASK) | (axi_wready << MH_DEBUG_REG00_AXI_WREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_RVALID(mh_debug_reg00_reg, axi_rvalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RVALID_MASK) | (axi_rvalid << MH_DEBUG_REG00_AXI_RVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_RREADY(mh_debug_reg00_reg, axi_rready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RREADY_MASK) | (axi_rready << MH_DEBUG_REG00_AXI_RREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_BVALID(mh_debug_reg00_reg, axi_bvalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_BVALID_MASK) | (axi_bvalid << MH_DEBUG_REG00_AXI_BVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_BREADY(mh_debug_reg00_reg, axi_bready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_BREADY_MASK) | (axi_bready << MH_DEBUG_REG00_AXI_BREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_HALT_REQ(mh_debug_reg00_reg, axi_halt_req) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_HALT_REQ_MASK) | (axi_halt_req << MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_HALT_ACK(mh_debug_reg00_reg, axi_halt_ack) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_HALT_ACK_MASK) | (axi_halt_ack << MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_RDY_ENA(mh_debug_reg00_reg, axi_rdy_ena) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RDY_ENA_MASK) | (axi_rdy_ena << MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg00_t { + unsigned int mh_busy : MH_DEBUG_REG00_MH_BUSY_SIZE; + unsigned int trans_outstanding : MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE; + unsigned int cp_request : MH_DEBUG_REG00_CP_REQUEST_SIZE; + unsigned int vgt_request : MH_DEBUG_REG00_VGT_REQUEST_SIZE; + unsigned int tc_request : MH_DEBUG_REG00_TC_REQUEST_SIZE; + unsigned int tc_cam_empty : MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE; + unsigned int tc_cam_full : MH_DEBUG_REG00_TC_CAM_FULL_SIZE; + unsigned int tcd_empty : MH_DEBUG_REG00_TCD_EMPTY_SIZE; + unsigned int tcd_full : MH_DEBUG_REG00_TCD_FULL_SIZE; + unsigned int rb_request : MH_DEBUG_REG00_RB_REQUEST_SIZE; + unsigned int pa_request : MH_DEBUG_REG00_PA_REQUEST_SIZE; + unsigned int mh_clk_en_state : MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE; + unsigned int arq_empty : MH_DEBUG_REG00_ARQ_EMPTY_SIZE; + unsigned int arq_full : MH_DEBUG_REG00_ARQ_FULL_SIZE; + unsigned int wdb_empty : MH_DEBUG_REG00_WDB_EMPTY_SIZE; + unsigned int wdb_full : MH_DEBUG_REG00_WDB_FULL_SIZE; + unsigned int axi_avalid : MH_DEBUG_REG00_AXI_AVALID_SIZE; + unsigned int axi_aready : MH_DEBUG_REG00_AXI_AREADY_SIZE; + unsigned int axi_arvalid : MH_DEBUG_REG00_AXI_ARVALID_SIZE; + unsigned int axi_arready : MH_DEBUG_REG00_AXI_ARREADY_SIZE; + unsigned int axi_wvalid : MH_DEBUG_REG00_AXI_WVALID_SIZE; + unsigned int axi_wready : MH_DEBUG_REG00_AXI_WREADY_SIZE; + unsigned int axi_rvalid : MH_DEBUG_REG00_AXI_RVALID_SIZE; + unsigned int axi_rready : MH_DEBUG_REG00_AXI_RREADY_SIZE; + unsigned int axi_bvalid : MH_DEBUG_REG00_AXI_BVALID_SIZE; + unsigned int axi_bready : MH_DEBUG_REG00_AXI_BREADY_SIZE; + unsigned int axi_halt_req : MH_DEBUG_REG00_AXI_HALT_REQ_SIZE; + unsigned int axi_halt_ack : MH_DEBUG_REG00_AXI_HALT_ACK_SIZE; + unsigned int axi_rdy_ena : MH_DEBUG_REG00_AXI_RDY_ENA_SIZE; + unsigned int : 3; + } mh_debug_reg00_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg00_t { + unsigned int : 3; + unsigned int axi_rdy_ena : MH_DEBUG_REG00_AXI_RDY_ENA_SIZE; + unsigned int axi_halt_ack : MH_DEBUG_REG00_AXI_HALT_ACK_SIZE; + unsigned int axi_halt_req : MH_DEBUG_REG00_AXI_HALT_REQ_SIZE; + unsigned int axi_bready : MH_DEBUG_REG00_AXI_BREADY_SIZE; + unsigned int axi_bvalid : MH_DEBUG_REG00_AXI_BVALID_SIZE; + unsigned int axi_rready : MH_DEBUG_REG00_AXI_RREADY_SIZE; + unsigned int axi_rvalid : MH_DEBUG_REG00_AXI_RVALID_SIZE; + unsigned int axi_wready : MH_DEBUG_REG00_AXI_WREADY_SIZE; + unsigned int axi_wvalid : MH_DEBUG_REG00_AXI_WVALID_SIZE; + unsigned int axi_arready : MH_DEBUG_REG00_AXI_ARREADY_SIZE; + unsigned int axi_arvalid : MH_DEBUG_REG00_AXI_ARVALID_SIZE; + unsigned int axi_aready : MH_DEBUG_REG00_AXI_AREADY_SIZE; + unsigned int axi_avalid : MH_DEBUG_REG00_AXI_AVALID_SIZE; + unsigned int wdb_full : MH_DEBUG_REG00_WDB_FULL_SIZE; + unsigned int wdb_empty : MH_DEBUG_REG00_WDB_EMPTY_SIZE; + unsigned int arq_full : MH_DEBUG_REG00_ARQ_FULL_SIZE; + unsigned int arq_empty : MH_DEBUG_REG00_ARQ_EMPTY_SIZE; + unsigned int mh_clk_en_state : MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE; + unsigned int pa_request : MH_DEBUG_REG00_PA_REQUEST_SIZE; + unsigned int rb_request : MH_DEBUG_REG00_RB_REQUEST_SIZE; + unsigned int tcd_full : MH_DEBUG_REG00_TCD_FULL_SIZE; + unsigned int tcd_empty : MH_DEBUG_REG00_TCD_EMPTY_SIZE; + unsigned int tc_cam_full : MH_DEBUG_REG00_TC_CAM_FULL_SIZE; + unsigned int tc_cam_empty : MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE; + unsigned int tc_request : MH_DEBUG_REG00_TC_REQUEST_SIZE; + unsigned int vgt_request : MH_DEBUG_REG00_VGT_REQUEST_SIZE; + unsigned int cp_request : MH_DEBUG_REG00_CP_REQUEST_SIZE; + unsigned int trans_outstanding : MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE; + unsigned int mh_busy : MH_DEBUG_REG00_MH_BUSY_SIZE; + } mh_debug_reg00_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg00_t f; +} mh_debug_reg00_u; + + +/* + * MH_DEBUG_REG01 struct + */ + +#define MH_DEBUG_REG01_CP_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_CP_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_CP_WRITE_q_SIZE 1 +#define MH_DEBUG_REG01_CP_TAG_q_SIZE 3 +#define MH_DEBUG_REG01_CP_BLEN_q_SIZE 1 +#define MH_DEBUG_REG01_VGT_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_VGT_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_VGT_TAG_q_SIZE 1 +#define MH_DEBUG_REG01_TC_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_TC_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_TC_BLEN_q_SIZE 1 +#define MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_TC_MH_written_SIZE 1 +#define MH_DEBUG_REG01_RB_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_RB_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_PA_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_PA_RTR_q_SIZE 1 + +#define MH_DEBUG_REG01_CP_SEND_q_SHIFT 0 +#define MH_DEBUG_REG01_CP_RTR_q_SHIFT 1 +#define MH_DEBUG_REG01_CP_WRITE_q_SHIFT 2 +#define MH_DEBUG_REG01_CP_TAG_q_SHIFT 3 +#define MH_DEBUG_REG01_CP_BLEN_q_SHIFT 6 +#define MH_DEBUG_REG01_VGT_SEND_q_SHIFT 7 +#define MH_DEBUG_REG01_VGT_RTR_q_SHIFT 8 +#define MH_DEBUG_REG01_VGT_TAG_q_SHIFT 9 +#define MH_DEBUG_REG01_TC_SEND_q_SHIFT 10 +#define MH_DEBUG_REG01_TC_RTR_q_SHIFT 11 +#define MH_DEBUG_REG01_TC_BLEN_q_SHIFT 12 +#define MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT 13 +#define MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT 14 +#define MH_DEBUG_REG01_TC_MH_written_SHIFT 15 +#define MH_DEBUG_REG01_RB_SEND_q_SHIFT 16 +#define MH_DEBUG_REG01_RB_RTR_q_SHIFT 17 +#define MH_DEBUG_REG01_PA_SEND_q_SHIFT 18 +#define MH_DEBUG_REG01_PA_RTR_q_SHIFT 19 + +#define MH_DEBUG_REG01_CP_SEND_q_MASK 0x00000001 +#define MH_DEBUG_REG01_CP_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG01_CP_WRITE_q_MASK 0x00000004 +#define MH_DEBUG_REG01_CP_TAG_q_MASK 0x00000038 +#define MH_DEBUG_REG01_CP_BLEN_q_MASK 0x00000040 +#define MH_DEBUG_REG01_VGT_SEND_q_MASK 0x00000080 +#define MH_DEBUG_REG01_VGT_RTR_q_MASK 0x00000100 +#define MH_DEBUG_REG01_VGT_TAG_q_MASK 0x00000200 +#define MH_DEBUG_REG01_TC_SEND_q_MASK 0x00000400 +#define MH_DEBUG_REG01_TC_RTR_q_MASK 0x00000800 +#define MH_DEBUG_REG01_TC_BLEN_q_MASK 0x00001000 +#define MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK 0x00002000 +#define MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK 0x00004000 +#define MH_DEBUG_REG01_TC_MH_written_MASK 0x00008000 +#define MH_DEBUG_REG01_RB_SEND_q_MASK 0x00010000 +#define MH_DEBUG_REG01_RB_RTR_q_MASK 0x00020000 +#define MH_DEBUG_REG01_PA_SEND_q_MASK 0x00040000 +#define MH_DEBUG_REG01_PA_RTR_q_MASK 0x00080000 + +#define MH_DEBUG_REG01_MASK \ + (MH_DEBUG_REG01_CP_SEND_q_MASK | \ + MH_DEBUG_REG01_CP_RTR_q_MASK | \ + MH_DEBUG_REG01_CP_WRITE_q_MASK | \ + MH_DEBUG_REG01_CP_TAG_q_MASK | \ + MH_DEBUG_REG01_CP_BLEN_q_MASK | \ + MH_DEBUG_REG01_VGT_SEND_q_MASK | \ + MH_DEBUG_REG01_VGT_RTR_q_MASK | \ + MH_DEBUG_REG01_VGT_TAG_q_MASK | \ + MH_DEBUG_REG01_TC_SEND_q_MASK | \ + MH_DEBUG_REG01_TC_RTR_q_MASK | \ + MH_DEBUG_REG01_TC_BLEN_q_MASK | \ + MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK | \ + MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG01_TC_MH_written_MASK | \ + MH_DEBUG_REG01_RB_SEND_q_MASK | \ + MH_DEBUG_REG01_RB_RTR_q_MASK | \ + MH_DEBUG_REG01_PA_SEND_q_MASK | \ + MH_DEBUG_REG01_PA_RTR_q_MASK) + +#define MH_DEBUG_REG01(cp_send_q, cp_rtr_q, cp_write_q, cp_tag_q, cp_blen_q, vgt_send_q, vgt_rtr_q, vgt_tag_q, tc_send_q, tc_rtr_q, tc_blen_q, tc_roq_send_q, tc_roq_rtr_q, tc_mh_written, rb_send_q, rb_rtr_q, pa_send_q, pa_rtr_q) \ + ((cp_send_q << MH_DEBUG_REG01_CP_SEND_q_SHIFT) | \ + (cp_rtr_q << MH_DEBUG_REG01_CP_RTR_q_SHIFT) | \ + (cp_write_q << MH_DEBUG_REG01_CP_WRITE_q_SHIFT) | \ + (cp_tag_q << MH_DEBUG_REG01_CP_TAG_q_SHIFT) | \ + (cp_blen_q << MH_DEBUG_REG01_CP_BLEN_q_SHIFT) | \ + (vgt_send_q << MH_DEBUG_REG01_VGT_SEND_q_SHIFT) | \ + (vgt_rtr_q << MH_DEBUG_REG01_VGT_RTR_q_SHIFT) | \ + (vgt_tag_q << MH_DEBUG_REG01_VGT_TAG_q_SHIFT) | \ + (tc_send_q << MH_DEBUG_REG01_TC_SEND_q_SHIFT) | \ + (tc_rtr_q << MH_DEBUG_REG01_TC_RTR_q_SHIFT) | \ + (tc_blen_q << MH_DEBUG_REG01_TC_BLEN_q_SHIFT) | \ + (tc_roq_send_q << MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT) | \ + (tc_mh_written << MH_DEBUG_REG01_TC_MH_written_SHIFT) | \ + (rb_send_q << MH_DEBUG_REG01_RB_SEND_q_SHIFT) | \ + (rb_rtr_q << MH_DEBUG_REG01_RB_RTR_q_SHIFT) | \ + (pa_send_q << MH_DEBUG_REG01_PA_SEND_q_SHIFT) | \ + (pa_rtr_q << MH_DEBUG_REG01_PA_RTR_q_SHIFT)) + +#define MH_DEBUG_REG01_GET_CP_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_SEND_q_MASK) >> MH_DEBUG_REG01_CP_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_CP_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_RTR_q_MASK) >> MH_DEBUG_REG01_CP_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_CP_WRITE_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_WRITE_q_MASK) >> MH_DEBUG_REG01_CP_WRITE_q_SHIFT) +#define MH_DEBUG_REG01_GET_CP_TAG_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_TAG_q_MASK) >> MH_DEBUG_REG01_CP_TAG_q_SHIFT) +#define MH_DEBUG_REG01_GET_CP_BLEN_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_BLEN_q_MASK) >> MH_DEBUG_REG01_CP_BLEN_q_SHIFT) +#define MH_DEBUG_REG01_GET_VGT_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_SEND_q_MASK) >> MH_DEBUG_REG01_VGT_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_VGT_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_RTR_q_MASK) >> MH_DEBUG_REG01_VGT_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_VGT_TAG_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_TAG_q_MASK) >> MH_DEBUG_REG01_VGT_TAG_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_SEND_q_MASK) >> MH_DEBUG_REG01_TC_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_RTR_q_MASK) >> MH_DEBUG_REG01_TC_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_BLEN_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_BLEN_q_MASK) >> MH_DEBUG_REG01_TC_BLEN_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_ROQ_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_ROQ_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_MH_written(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_MH_written_MASK) >> MH_DEBUG_REG01_TC_MH_written_SHIFT) +#define MH_DEBUG_REG01_GET_RB_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_RB_SEND_q_MASK) >> MH_DEBUG_REG01_RB_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_RB_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_RB_RTR_q_MASK) >> MH_DEBUG_REG01_RB_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_PA_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_PA_SEND_q_MASK) >> MH_DEBUG_REG01_PA_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_PA_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_PA_RTR_q_MASK) >> MH_DEBUG_REG01_PA_RTR_q_SHIFT) + +#define MH_DEBUG_REG01_SET_CP_SEND_q(mh_debug_reg01_reg, cp_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_SEND_q_MASK) | (cp_send_q << MH_DEBUG_REG01_CP_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_CP_RTR_q(mh_debug_reg01_reg, cp_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_RTR_q_MASK) | (cp_rtr_q << MH_DEBUG_REG01_CP_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_CP_WRITE_q(mh_debug_reg01_reg, cp_write_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_WRITE_q_MASK) | (cp_write_q << MH_DEBUG_REG01_CP_WRITE_q_SHIFT) +#define MH_DEBUG_REG01_SET_CP_TAG_q(mh_debug_reg01_reg, cp_tag_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_TAG_q_MASK) | (cp_tag_q << MH_DEBUG_REG01_CP_TAG_q_SHIFT) +#define MH_DEBUG_REG01_SET_CP_BLEN_q(mh_debug_reg01_reg, cp_blen_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_BLEN_q_MASK) | (cp_blen_q << MH_DEBUG_REG01_CP_BLEN_q_SHIFT) +#define MH_DEBUG_REG01_SET_VGT_SEND_q(mh_debug_reg01_reg, vgt_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_SEND_q_MASK) | (vgt_send_q << MH_DEBUG_REG01_VGT_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_VGT_RTR_q(mh_debug_reg01_reg, vgt_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_RTR_q_MASK) | (vgt_rtr_q << MH_DEBUG_REG01_VGT_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_VGT_TAG_q(mh_debug_reg01_reg, vgt_tag_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_TAG_q_MASK) | (vgt_tag_q << MH_DEBUG_REG01_VGT_TAG_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_SEND_q(mh_debug_reg01_reg, tc_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_SEND_q_MASK) | (tc_send_q << MH_DEBUG_REG01_TC_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_RTR_q(mh_debug_reg01_reg, tc_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_RTR_q_MASK) | (tc_rtr_q << MH_DEBUG_REG01_TC_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_BLEN_q(mh_debug_reg01_reg, tc_blen_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_BLEN_q_MASK) | (tc_blen_q << MH_DEBUG_REG01_TC_BLEN_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_ROQ_SEND_q(mh_debug_reg01_reg, tc_roq_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_ROQ_RTR_q(mh_debug_reg01_reg, tc_roq_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_MH_written(mh_debug_reg01_reg, tc_mh_written) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG01_TC_MH_written_SHIFT) +#define MH_DEBUG_REG01_SET_RB_SEND_q(mh_debug_reg01_reg, rb_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_RB_SEND_q_MASK) | (rb_send_q << MH_DEBUG_REG01_RB_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_RB_RTR_q(mh_debug_reg01_reg, rb_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_RB_RTR_q_MASK) | (rb_rtr_q << MH_DEBUG_REG01_RB_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_PA_SEND_q(mh_debug_reg01_reg, pa_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_PA_SEND_q_MASK) | (pa_send_q << MH_DEBUG_REG01_PA_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_PA_RTR_q(mh_debug_reg01_reg, pa_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_PA_RTR_q_MASK) | (pa_rtr_q << MH_DEBUG_REG01_PA_RTR_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg01_t { + unsigned int cp_send_q : MH_DEBUG_REG01_CP_SEND_q_SIZE; + unsigned int cp_rtr_q : MH_DEBUG_REG01_CP_RTR_q_SIZE; + unsigned int cp_write_q : MH_DEBUG_REG01_CP_WRITE_q_SIZE; + unsigned int cp_tag_q : MH_DEBUG_REG01_CP_TAG_q_SIZE; + unsigned int cp_blen_q : MH_DEBUG_REG01_CP_BLEN_q_SIZE; + unsigned int vgt_send_q : MH_DEBUG_REG01_VGT_SEND_q_SIZE; + unsigned int vgt_rtr_q : MH_DEBUG_REG01_VGT_RTR_q_SIZE; + unsigned int vgt_tag_q : MH_DEBUG_REG01_VGT_TAG_q_SIZE; + unsigned int tc_send_q : MH_DEBUG_REG01_TC_SEND_q_SIZE; + unsigned int tc_rtr_q : MH_DEBUG_REG01_TC_RTR_q_SIZE; + unsigned int tc_blen_q : MH_DEBUG_REG01_TC_BLEN_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG01_TC_MH_written_SIZE; + unsigned int rb_send_q : MH_DEBUG_REG01_RB_SEND_q_SIZE; + unsigned int rb_rtr_q : MH_DEBUG_REG01_RB_RTR_q_SIZE; + unsigned int pa_send_q : MH_DEBUG_REG01_PA_SEND_q_SIZE; + unsigned int pa_rtr_q : MH_DEBUG_REG01_PA_RTR_q_SIZE; + unsigned int : 12; + } mh_debug_reg01_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg01_t { + unsigned int : 12; + unsigned int pa_rtr_q : MH_DEBUG_REG01_PA_RTR_q_SIZE; + unsigned int pa_send_q : MH_DEBUG_REG01_PA_SEND_q_SIZE; + unsigned int rb_rtr_q : MH_DEBUG_REG01_RB_RTR_q_SIZE; + unsigned int rb_send_q : MH_DEBUG_REG01_RB_SEND_q_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG01_TC_MH_written_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE; + unsigned int tc_blen_q : MH_DEBUG_REG01_TC_BLEN_q_SIZE; + unsigned int tc_rtr_q : MH_DEBUG_REG01_TC_RTR_q_SIZE; + unsigned int tc_send_q : MH_DEBUG_REG01_TC_SEND_q_SIZE; + unsigned int vgt_tag_q : MH_DEBUG_REG01_VGT_TAG_q_SIZE; + unsigned int vgt_rtr_q : MH_DEBUG_REG01_VGT_RTR_q_SIZE; + unsigned int vgt_send_q : MH_DEBUG_REG01_VGT_SEND_q_SIZE; + unsigned int cp_blen_q : MH_DEBUG_REG01_CP_BLEN_q_SIZE; + unsigned int cp_tag_q : MH_DEBUG_REG01_CP_TAG_q_SIZE; + unsigned int cp_write_q : MH_DEBUG_REG01_CP_WRITE_q_SIZE; + unsigned int cp_rtr_q : MH_DEBUG_REG01_CP_RTR_q_SIZE; + unsigned int cp_send_q : MH_DEBUG_REG01_CP_SEND_q_SIZE; + } mh_debug_reg01_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg01_t f; +} mh_debug_reg01_u; + + +/* + * MH_DEBUG_REG02 struct + */ + +#define MH_DEBUG_REG02_MH_CP_grb_send_SIZE 1 +#define MH_DEBUG_REG02_MH_VGT_grb_send_SIZE 1 +#define MH_DEBUG_REG02_MH_TC_mcsend_SIZE 1 +#define MH_DEBUG_REG02_MH_CLNT_rlast_SIZE 1 +#define MH_DEBUG_REG02_MH_CLNT_tag_SIZE 3 +#define MH_DEBUG_REG02_RDC_RID_SIZE 3 +#define MH_DEBUG_REG02_RDC_RRESP_SIZE 2 +#define MH_DEBUG_REG02_MH_CP_writeclean_SIZE 1 +#define MH_DEBUG_REG02_MH_RB_writeclean_SIZE 1 +#define MH_DEBUG_REG02_MH_PA_writeclean_SIZE 1 +#define MH_DEBUG_REG02_BRC_BID_SIZE 3 +#define MH_DEBUG_REG02_BRC_BRESP_SIZE 2 + +#define MH_DEBUG_REG02_MH_CP_grb_send_SHIFT 0 +#define MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT 1 +#define MH_DEBUG_REG02_MH_TC_mcsend_SHIFT 2 +#define MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT 3 +#define MH_DEBUG_REG02_MH_CLNT_tag_SHIFT 4 +#define MH_DEBUG_REG02_RDC_RID_SHIFT 7 +#define MH_DEBUG_REG02_RDC_RRESP_SHIFT 10 +#define MH_DEBUG_REG02_MH_CP_writeclean_SHIFT 12 +#define MH_DEBUG_REG02_MH_RB_writeclean_SHIFT 13 +#define MH_DEBUG_REG02_MH_PA_writeclean_SHIFT 14 +#define MH_DEBUG_REG02_BRC_BID_SHIFT 15 +#define MH_DEBUG_REG02_BRC_BRESP_SHIFT 18 + +#define MH_DEBUG_REG02_MH_CP_grb_send_MASK 0x00000001 +#define MH_DEBUG_REG02_MH_VGT_grb_send_MASK 0x00000002 +#define MH_DEBUG_REG02_MH_TC_mcsend_MASK 0x00000004 +#define MH_DEBUG_REG02_MH_CLNT_rlast_MASK 0x00000008 +#define MH_DEBUG_REG02_MH_CLNT_tag_MASK 0x00000070 +#define MH_DEBUG_REG02_RDC_RID_MASK 0x00000380 +#define MH_DEBUG_REG02_RDC_RRESP_MASK 0x00000c00 +#define MH_DEBUG_REG02_MH_CP_writeclean_MASK 0x00001000 +#define MH_DEBUG_REG02_MH_RB_writeclean_MASK 0x00002000 +#define MH_DEBUG_REG02_MH_PA_writeclean_MASK 0x00004000 +#define MH_DEBUG_REG02_BRC_BID_MASK 0x00038000 +#define MH_DEBUG_REG02_BRC_BRESP_MASK 0x000c0000 + +#define MH_DEBUG_REG02_MASK \ + (MH_DEBUG_REG02_MH_CP_grb_send_MASK | \ + MH_DEBUG_REG02_MH_VGT_grb_send_MASK | \ + MH_DEBUG_REG02_MH_TC_mcsend_MASK | \ + MH_DEBUG_REG02_MH_CLNT_rlast_MASK | \ + MH_DEBUG_REG02_MH_CLNT_tag_MASK | \ + MH_DEBUG_REG02_RDC_RID_MASK | \ + MH_DEBUG_REG02_RDC_RRESP_MASK | \ + MH_DEBUG_REG02_MH_CP_writeclean_MASK | \ + MH_DEBUG_REG02_MH_RB_writeclean_MASK | \ + MH_DEBUG_REG02_MH_PA_writeclean_MASK | \ + MH_DEBUG_REG02_BRC_BID_MASK | \ + MH_DEBUG_REG02_BRC_BRESP_MASK) + +#define MH_DEBUG_REG02(mh_cp_grb_send, mh_vgt_grb_send, mh_tc_mcsend, mh_clnt_rlast, mh_clnt_tag, rdc_rid, rdc_rresp, mh_cp_writeclean, mh_rb_writeclean, mh_pa_writeclean, brc_bid, brc_bresp) \ + ((mh_cp_grb_send << MH_DEBUG_REG02_MH_CP_grb_send_SHIFT) | \ + (mh_vgt_grb_send << MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT) | \ + (mh_tc_mcsend << MH_DEBUG_REG02_MH_TC_mcsend_SHIFT) | \ + (mh_clnt_rlast << MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT) | \ + (mh_clnt_tag << MH_DEBUG_REG02_MH_CLNT_tag_SHIFT) | \ + (rdc_rid << MH_DEBUG_REG02_RDC_RID_SHIFT) | \ + (rdc_rresp << MH_DEBUG_REG02_RDC_RRESP_SHIFT) | \ + (mh_cp_writeclean << MH_DEBUG_REG02_MH_CP_writeclean_SHIFT) | \ + (mh_rb_writeclean << MH_DEBUG_REG02_MH_RB_writeclean_SHIFT) | \ + (mh_pa_writeclean << MH_DEBUG_REG02_MH_PA_writeclean_SHIFT) | \ + (brc_bid << MH_DEBUG_REG02_BRC_BID_SHIFT) | \ + (brc_bresp << MH_DEBUG_REG02_BRC_BRESP_SHIFT)) + +#define MH_DEBUG_REG02_GET_MH_CP_grb_send(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CP_grb_send_MASK) >> MH_DEBUG_REG02_MH_CP_grb_send_SHIFT) +#define MH_DEBUG_REG02_GET_MH_VGT_grb_send(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_VGT_grb_send_MASK) >> MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT) +#define MH_DEBUG_REG02_GET_MH_TC_mcsend(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_TC_mcsend_MASK) >> MH_DEBUG_REG02_MH_TC_mcsend_SHIFT) +#define MH_DEBUG_REG02_GET_MH_CLNT_rlast(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CLNT_rlast_MASK) >> MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT) +#define MH_DEBUG_REG02_GET_MH_CLNT_tag(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CLNT_tag_MASK) >> MH_DEBUG_REG02_MH_CLNT_tag_SHIFT) +#define MH_DEBUG_REG02_GET_RDC_RID(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_RDC_RID_MASK) >> MH_DEBUG_REG02_RDC_RID_SHIFT) +#define MH_DEBUG_REG02_GET_RDC_RRESP(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_RDC_RRESP_MASK) >> MH_DEBUG_REG02_RDC_RRESP_SHIFT) +#define MH_DEBUG_REG02_GET_MH_CP_writeclean(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CP_writeclean_MASK) >> MH_DEBUG_REG02_MH_CP_writeclean_SHIFT) +#define MH_DEBUG_REG02_GET_MH_RB_writeclean(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_RB_writeclean_MASK) >> MH_DEBUG_REG02_MH_RB_writeclean_SHIFT) +#define MH_DEBUG_REG02_GET_MH_PA_writeclean(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_PA_writeclean_MASK) >> MH_DEBUG_REG02_MH_PA_writeclean_SHIFT) +#define MH_DEBUG_REG02_GET_BRC_BID(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_BRC_BID_MASK) >> MH_DEBUG_REG02_BRC_BID_SHIFT) +#define MH_DEBUG_REG02_GET_BRC_BRESP(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_BRC_BRESP_MASK) >> MH_DEBUG_REG02_BRC_BRESP_SHIFT) + +#define MH_DEBUG_REG02_SET_MH_CP_grb_send(mh_debug_reg02_reg, mh_cp_grb_send) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CP_grb_send_MASK) | (mh_cp_grb_send << MH_DEBUG_REG02_MH_CP_grb_send_SHIFT) +#define MH_DEBUG_REG02_SET_MH_VGT_grb_send(mh_debug_reg02_reg, mh_vgt_grb_send) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_VGT_grb_send_MASK) | (mh_vgt_grb_send << MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT) +#define MH_DEBUG_REG02_SET_MH_TC_mcsend(mh_debug_reg02_reg, mh_tc_mcsend) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_TC_mcsend_MASK) | (mh_tc_mcsend << MH_DEBUG_REG02_MH_TC_mcsend_SHIFT) +#define MH_DEBUG_REG02_SET_MH_CLNT_rlast(mh_debug_reg02_reg, mh_clnt_rlast) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CLNT_rlast_MASK) | (mh_clnt_rlast << MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT) +#define MH_DEBUG_REG02_SET_MH_CLNT_tag(mh_debug_reg02_reg, mh_clnt_tag) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CLNT_tag_MASK) | (mh_clnt_tag << MH_DEBUG_REG02_MH_CLNT_tag_SHIFT) +#define MH_DEBUG_REG02_SET_RDC_RID(mh_debug_reg02_reg, rdc_rid) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_RDC_RID_MASK) | (rdc_rid << MH_DEBUG_REG02_RDC_RID_SHIFT) +#define MH_DEBUG_REG02_SET_RDC_RRESP(mh_debug_reg02_reg, rdc_rresp) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_RDC_RRESP_MASK) | (rdc_rresp << MH_DEBUG_REG02_RDC_RRESP_SHIFT) +#define MH_DEBUG_REG02_SET_MH_CP_writeclean(mh_debug_reg02_reg, mh_cp_writeclean) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CP_writeclean_MASK) | (mh_cp_writeclean << MH_DEBUG_REG02_MH_CP_writeclean_SHIFT) +#define MH_DEBUG_REG02_SET_MH_RB_writeclean(mh_debug_reg02_reg, mh_rb_writeclean) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_RB_writeclean_MASK) | (mh_rb_writeclean << MH_DEBUG_REG02_MH_RB_writeclean_SHIFT) +#define MH_DEBUG_REG02_SET_MH_PA_writeclean(mh_debug_reg02_reg, mh_pa_writeclean) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_PA_writeclean_MASK) | (mh_pa_writeclean << MH_DEBUG_REG02_MH_PA_writeclean_SHIFT) +#define MH_DEBUG_REG02_SET_BRC_BID(mh_debug_reg02_reg, brc_bid) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_BRC_BID_MASK) | (brc_bid << MH_DEBUG_REG02_BRC_BID_SHIFT) +#define MH_DEBUG_REG02_SET_BRC_BRESP(mh_debug_reg02_reg, brc_bresp) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_BRC_BRESP_MASK) | (brc_bresp << MH_DEBUG_REG02_BRC_BRESP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg02_t { + unsigned int mh_cp_grb_send : MH_DEBUG_REG02_MH_CP_grb_send_SIZE; + unsigned int mh_vgt_grb_send : MH_DEBUG_REG02_MH_VGT_grb_send_SIZE; + unsigned int mh_tc_mcsend : MH_DEBUG_REG02_MH_TC_mcsend_SIZE; + unsigned int mh_clnt_rlast : MH_DEBUG_REG02_MH_CLNT_rlast_SIZE; + unsigned int mh_clnt_tag : MH_DEBUG_REG02_MH_CLNT_tag_SIZE; + unsigned int rdc_rid : MH_DEBUG_REG02_RDC_RID_SIZE; + unsigned int rdc_rresp : MH_DEBUG_REG02_RDC_RRESP_SIZE; + unsigned int mh_cp_writeclean : MH_DEBUG_REG02_MH_CP_writeclean_SIZE; + unsigned int mh_rb_writeclean : MH_DEBUG_REG02_MH_RB_writeclean_SIZE; + unsigned int mh_pa_writeclean : MH_DEBUG_REG02_MH_PA_writeclean_SIZE; + unsigned int brc_bid : MH_DEBUG_REG02_BRC_BID_SIZE; + unsigned int brc_bresp : MH_DEBUG_REG02_BRC_BRESP_SIZE; + unsigned int : 12; + } mh_debug_reg02_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg02_t { + unsigned int : 12; + unsigned int brc_bresp : MH_DEBUG_REG02_BRC_BRESP_SIZE; + unsigned int brc_bid : MH_DEBUG_REG02_BRC_BID_SIZE; + unsigned int mh_pa_writeclean : MH_DEBUG_REG02_MH_PA_writeclean_SIZE; + unsigned int mh_rb_writeclean : MH_DEBUG_REG02_MH_RB_writeclean_SIZE; + unsigned int mh_cp_writeclean : MH_DEBUG_REG02_MH_CP_writeclean_SIZE; + unsigned int rdc_rresp : MH_DEBUG_REG02_RDC_RRESP_SIZE; + unsigned int rdc_rid : MH_DEBUG_REG02_RDC_RID_SIZE; + unsigned int mh_clnt_tag : MH_DEBUG_REG02_MH_CLNT_tag_SIZE; + unsigned int mh_clnt_rlast : MH_DEBUG_REG02_MH_CLNT_rlast_SIZE; + unsigned int mh_tc_mcsend : MH_DEBUG_REG02_MH_TC_mcsend_SIZE; + unsigned int mh_vgt_grb_send : MH_DEBUG_REG02_MH_VGT_grb_send_SIZE; + unsigned int mh_cp_grb_send : MH_DEBUG_REG02_MH_CP_grb_send_SIZE; + } mh_debug_reg02_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg02_t f; +} mh_debug_reg02_u; + + +/* + * MH_DEBUG_REG03 struct + */ + +#define MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE 32 + +#define MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT 0 + +#define MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG03_MASK \ + (MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) + +#define MH_DEBUG_REG03(mh_clnt_data_31_0) \ + ((mh_clnt_data_31_0 << MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT)) + +#define MH_DEBUG_REG03_GET_MH_CLNT_data_31_0(mh_debug_reg03) \ + ((mh_debug_reg03 & MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) >> MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT) + +#define MH_DEBUG_REG03_SET_MH_CLNT_data_31_0(mh_debug_reg03_reg, mh_clnt_data_31_0) \ + mh_debug_reg03_reg = (mh_debug_reg03_reg & ~MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) | (mh_clnt_data_31_0 << MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg03_t { + unsigned int mh_clnt_data_31_0 : MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE; + } mh_debug_reg03_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg03_t { + unsigned int mh_clnt_data_31_0 : MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE; + } mh_debug_reg03_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg03_t f; +} mh_debug_reg03_u; + + +/* + * MH_DEBUG_REG04 struct + */ + +#define MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE 32 + +#define MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT 0 + +#define MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG04_MASK \ + (MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) + +#define MH_DEBUG_REG04(mh_clnt_data_63_32) \ + ((mh_clnt_data_63_32 << MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT)) + +#define MH_DEBUG_REG04_GET_MH_CLNT_data_63_32(mh_debug_reg04) \ + ((mh_debug_reg04 & MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) >> MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT) + +#define MH_DEBUG_REG04_SET_MH_CLNT_data_63_32(mh_debug_reg04_reg, mh_clnt_data_63_32) \ + mh_debug_reg04_reg = (mh_debug_reg04_reg & ~MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) | (mh_clnt_data_63_32 << MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg04_t { + unsigned int mh_clnt_data_63_32 : MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE; + } mh_debug_reg04_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg04_t { + unsigned int mh_clnt_data_63_32 : MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE; + } mh_debug_reg04_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg04_t f; +} mh_debug_reg04_u; + + +/* + * MH_DEBUG_REG05 struct + */ + +#define MH_DEBUG_REG05_CP_MH_send_SIZE 1 +#define MH_DEBUG_REG05_CP_MH_write_SIZE 1 +#define MH_DEBUG_REG05_CP_MH_tag_SIZE 3 +#define MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE 27 + +#define MH_DEBUG_REG05_CP_MH_send_SHIFT 0 +#define MH_DEBUG_REG05_CP_MH_write_SHIFT 1 +#define MH_DEBUG_REG05_CP_MH_tag_SHIFT 2 +#define MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT 5 + +#define MH_DEBUG_REG05_CP_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG05_CP_MH_write_MASK 0x00000002 +#define MH_DEBUG_REG05_CP_MH_tag_MASK 0x0000001c +#define MH_DEBUG_REG05_CP_MH_ad_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG05_MASK \ + (MH_DEBUG_REG05_CP_MH_send_MASK | \ + MH_DEBUG_REG05_CP_MH_write_MASK | \ + MH_DEBUG_REG05_CP_MH_tag_MASK | \ + MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) + +#define MH_DEBUG_REG05(cp_mh_send, cp_mh_write, cp_mh_tag, cp_mh_ad_31_5) \ + ((cp_mh_send << MH_DEBUG_REG05_CP_MH_send_SHIFT) | \ + (cp_mh_write << MH_DEBUG_REG05_CP_MH_write_SHIFT) | \ + (cp_mh_tag << MH_DEBUG_REG05_CP_MH_tag_SHIFT) | \ + (cp_mh_ad_31_5 << MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT)) + +#define MH_DEBUG_REG05_GET_CP_MH_send(mh_debug_reg05) \ + ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_send_MASK) >> MH_DEBUG_REG05_CP_MH_send_SHIFT) +#define MH_DEBUG_REG05_GET_CP_MH_write(mh_debug_reg05) \ + ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_write_MASK) >> MH_DEBUG_REG05_CP_MH_write_SHIFT) +#define MH_DEBUG_REG05_GET_CP_MH_tag(mh_debug_reg05) \ + ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_tag_MASK) >> MH_DEBUG_REG05_CP_MH_tag_SHIFT) +#define MH_DEBUG_REG05_GET_CP_MH_ad_31_5(mh_debug_reg05) \ + ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) >> MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT) + +#define MH_DEBUG_REG05_SET_CP_MH_send(mh_debug_reg05_reg, cp_mh_send) \ + mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_send_MASK) | (cp_mh_send << MH_DEBUG_REG05_CP_MH_send_SHIFT) +#define MH_DEBUG_REG05_SET_CP_MH_write(mh_debug_reg05_reg, cp_mh_write) \ + mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_write_MASK) | (cp_mh_write << MH_DEBUG_REG05_CP_MH_write_SHIFT) +#define MH_DEBUG_REG05_SET_CP_MH_tag(mh_debug_reg05_reg, cp_mh_tag) \ + mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_tag_MASK) | (cp_mh_tag << MH_DEBUG_REG05_CP_MH_tag_SHIFT) +#define MH_DEBUG_REG05_SET_CP_MH_ad_31_5(mh_debug_reg05_reg, cp_mh_ad_31_5) \ + mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) | (cp_mh_ad_31_5 << MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg05_t { + unsigned int cp_mh_send : MH_DEBUG_REG05_CP_MH_send_SIZE; + unsigned int cp_mh_write : MH_DEBUG_REG05_CP_MH_write_SIZE; + unsigned int cp_mh_tag : MH_DEBUG_REG05_CP_MH_tag_SIZE; + unsigned int cp_mh_ad_31_5 : MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE; + } mh_debug_reg05_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg05_t { + unsigned int cp_mh_ad_31_5 : MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE; + unsigned int cp_mh_tag : MH_DEBUG_REG05_CP_MH_tag_SIZE; + unsigned int cp_mh_write : MH_DEBUG_REG05_CP_MH_write_SIZE; + unsigned int cp_mh_send : MH_DEBUG_REG05_CP_MH_send_SIZE; + } mh_debug_reg05_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg05_t f; +} mh_debug_reg05_u; + + +/* + * MH_DEBUG_REG06 struct + */ + +#define MH_DEBUG_REG06_CP_MH_data_31_0_SIZE 32 + +#define MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT 0 + +#define MH_DEBUG_REG06_CP_MH_data_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG06_MASK \ + (MH_DEBUG_REG06_CP_MH_data_31_0_MASK) + +#define MH_DEBUG_REG06(cp_mh_data_31_0) \ + ((cp_mh_data_31_0 << MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT)) + +#define MH_DEBUG_REG06_GET_CP_MH_data_31_0(mh_debug_reg06) \ + ((mh_debug_reg06 & MH_DEBUG_REG06_CP_MH_data_31_0_MASK) >> MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT) + +#define MH_DEBUG_REG06_SET_CP_MH_data_31_0(mh_debug_reg06_reg, cp_mh_data_31_0) \ + mh_debug_reg06_reg = (mh_debug_reg06_reg & ~MH_DEBUG_REG06_CP_MH_data_31_0_MASK) | (cp_mh_data_31_0 << MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg06_t { + unsigned int cp_mh_data_31_0 : MH_DEBUG_REG06_CP_MH_data_31_0_SIZE; + } mh_debug_reg06_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg06_t { + unsigned int cp_mh_data_31_0 : MH_DEBUG_REG06_CP_MH_data_31_0_SIZE; + } mh_debug_reg06_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg06_t f; +} mh_debug_reg06_u; + + +/* + * MH_DEBUG_REG07 struct + */ + +#define MH_DEBUG_REG07_CP_MH_data_63_32_SIZE 32 + +#define MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT 0 + +#define MH_DEBUG_REG07_CP_MH_data_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG07_MASK \ + (MH_DEBUG_REG07_CP_MH_data_63_32_MASK) + +#define MH_DEBUG_REG07(cp_mh_data_63_32) \ + ((cp_mh_data_63_32 << MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT)) + +#define MH_DEBUG_REG07_GET_CP_MH_data_63_32(mh_debug_reg07) \ + ((mh_debug_reg07 & MH_DEBUG_REG07_CP_MH_data_63_32_MASK) >> MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT) + +#define MH_DEBUG_REG07_SET_CP_MH_data_63_32(mh_debug_reg07_reg, cp_mh_data_63_32) \ + mh_debug_reg07_reg = (mh_debug_reg07_reg & ~MH_DEBUG_REG07_CP_MH_data_63_32_MASK) | (cp_mh_data_63_32 << MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg07_t { + unsigned int cp_mh_data_63_32 : MH_DEBUG_REG07_CP_MH_data_63_32_SIZE; + } mh_debug_reg07_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg07_t { + unsigned int cp_mh_data_63_32 : MH_DEBUG_REG07_CP_MH_data_63_32_SIZE; + } mh_debug_reg07_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg07_t f; +} mh_debug_reg07_u; + + +/* + * MH_DEBUG_REG08 struct + */ + +#define MH_DEBUG_REG08_CP_MH_be_SIZE 8 +#define MH_DEBUG_REG08_RB_MH_be_SIZE 8 +#define MH_DEBUG_REG08_PA_MH_be_SIZE 8 + +#define MH_DEBUG_REG08_CP_MH_be_SHIFT 0 +#define MH_DEBUG_REG08_RB_MH_be_SHIFT 8 +#define MH_DEBUG_REG08_PA_MH_be_SHIFT 16 + +#define MH_DEBUG_REG08_CP_MH_be_MASK 0x000000ff +#define MH_DEBUG_REG08_RB_MH_be_MASK 0x0000ff00 +#define MH_DEBUG_REG08_PA_MH_be_MASK 0x00ff0000 + +#define MH_DEBUG_REG08_MASK \ + (MH_DEBUG_REG08_CP_MH_be_MASK | \ + MH_DEBUG_REG08_RB_MH_be_MASK | \ + MH_DEBUG_REG08_PA_MH_be_MASK) + +#define MH_DEBUG_REG08(cp_mh_be, rb_mh_be, pa_mh_be) \ + ((cp_mh_be << MH_DEBUG_REG08_CP_MH_be_SHIFT) | \ + (rb_mh_be << MH_DEBUG_REG08_RB_MH_be_SHIFT) | \ + (pa_mh_be << MH_DEBUG_REG08_PA_MH_be_SHIFT)) + +#define MH_DEBUG_REG08_GET_CP_MH_be(mh_debug_reg08) \ + ((mh_debug_reg08 & MH_DEBUG_REG08_CP_MH_be_MASK) >> MH_DEBUG_REG08_CP_MH_be_SHIFT) +#define MH_DEBUG_REG08_GET_RB_MH_be(mh_debug_reg08) \ + ((mh_debug_reg08 & MH_DEBUG_REG08_RB_MH_be_MASK) >> MH_DEBUG_REG08_RB_MH_be_SHIFT) +#define MH_DEBUG_REG08_GET_PA_MH_be(mh_debug_reg08) \ + ((mh_debug_reg08 & MH_DEBUG_REG08_PA_MH_be_MASK) >> MH_DEBUG_REG08_PA_MH_be_SHIFT) + +#define MH_DEBUG_REG08_SET_CP_MH_be(mh_debug_reg08_reg, cp_mh_be) \ + mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_CP_MH_be_MASK) | (cp_mh_be << MH_DEBUG_REG08_CP_MH_be_SHIFT) +#define MH_DEBUG_REG08_SET_RB_MH_be(mh_debug_reg08_reg, rb_mh_be) \ + mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_RB_MH_be_MASK) | (rb_mh_be << MH_DEBUG_REG08_RB_MH_be_SHIFT) +#define MH_DEBUG_REG08_SET_PA_MH_be(mh_debug_reg08_reg, pa_mh_be) \ + mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_PA_MH_be_MASK) | (pa_mh_be << MH_DEBUG_REG08_PA_MH_be_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg08_t { + unsigned int cp_mh_be : MH_DEBUG_REG08_CP_MH_be_SIZE; + unsigned int rb_mh_be : MH_DEBUG_REG08_RB_MH_be_SIZE; + unsigned int pa_mh_be : MH_DEBUG_REG08_PA_MH_be_SIZE; + unsigned int : 8; + } mh_debug_reg08_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg08_t { + unsigned int : 8; + unsigned int pa_mh_be : MH_DEBUG_REG08_PA_MH_be_SIZE; + unsigned int rb_mh_be : MH_DEBUG_REG08_RB_MH_be_SIZE; + unsigned int cp_mh_be : MH_DEBUG_REG08_CP_MH_be_SIZE; + } mh_debug_reg08_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg08_t f; +} mh_debug_reg08_u; + + +/* + * MH_DEBUG_REG09 struct + */ + +#define MH_DEBUG_REG09_ALWAYS_ZERO_SIZE 3 +#define MH_DEBUG_REG09_VGT_MH_send_SIZE 1 +#define MH_DEBUG_REG09_VGT_MH_tagbe_SIZE 1 +#define MH_DEBUG_REG09_VGT_MH_ad_31_5_SIZE 27 + +#define MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG09_VGT_MH_send_SHIFT 3 +#define MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT 4 +#define MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT 5 + +#define MH_DEBUG_REG09_ALWAYS_ZERO_MASK 0x00000007 +#define MH_DEBUG_REG09_VGT_MH_send_MASK 0x00000008 +#define MH_DEBUG_REG09_VGT_MH_tagbe_MASK 0x00000010 +#define MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG09_MASK \ + (MH_DEBUG_REG09_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG09_VGT_MH_send_MASK | \ + MH_DEBUG_REG09_VGT_MH_tagbe_MASK | \ + MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK) + +#define MH_DEBUG_REG09(always_zero, vgt_mh_send, vgt_mh_tagbe, vgt_mh_ad_31_5) \ + ((always_zero << MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT) | \ + (vgt_mh_send << MH_DEBUG_REG09_VGT_MH_send_SHIFT) | \ + (vgt_mh_tagbe << MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT) | \ + (vgt_mh_ad_31_5 << MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT)) + +#define MH_DEBUG_REG09_GET_ALWAYS_ZERO(mh_debug_reg09) \ + ((mh_debug_reg09 & MH_DEBUG_REG09_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG09_GET_VGT_MH_send(mh_debug_reg09) \ + ((mh_debug_reg09 & MH_DEBUG_REG09_VGT_MH_send_MASK) >> MH_DEBUG_REG09_VGT_MH_send_SHIFT) +#define MH_DEBUG_REG09_GET_VGT_MH_tagbe(mh_debug_reg09) \ + ((mh_debug_reg09 & MH_DEBUG_REG09_VGT_MH_tagbe_MASK) >> MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT) +#define MH_DEBUG_REG09_GET_VGT_MH_ad_31_5(mh_debug_reg09) \ + ((mh_debug_reg09 & MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK) >> MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT) + +#define MH_DEBUG_REG09_SET_ALWAYS_ZERO(mh_debug_reg09_reg, always_zero) \ + mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG09_SET_VGT_MH_send(mh_debug_reg09_reg, vgt_mh_send) \ + mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_VGT_MH_send_MASK) | (vgt_mh_send << MH_DEBUG_REG09_VGT_MH_send_SHIFT) +#define MH_DEBUG_REG09_SET_VGT_MH_tagbe(mh_debug_reg09_reg, vgt_mh_tagbe) \ + mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_VGT_MH_tagbe_MASK) | (vgt_mh_tagbe << MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT) +#define MH_DEBUG_REG09_SET_VGT_MH_ad_31_5(mh_debug_reg09_reg, vgt_mh_ad_31_5) \ + mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK) | (vgt_mh_ad_31_5 << MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg09_t { + unsigned int always_zero : MH_DEBUG_REG09_ALWAYS_ZERO_SIZE; + unsigned int vgt_mh_send : MH_DEBUG_REG09_VGT_MH_send_SIZE; + unsigned int vgt_mh_tagbe : MH_DEBUG_REG09_VGT_MH_tagbe_SIZE; + unsigned int vgt_mh_ad_31_5 : MH_DEBUG_REG09_VGT_MH_ad_31_5_SIZE; + } mh_debug_reg09_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg09_t { + unsigned int vgt_mh_ad_31_5 : MH_DEBUG_REG09_VGT_MH_ad_31_5_SIZE; + unsigned int vgt_mh_tagbe : MH_DEBUG_REG09_VGT_MH_tagbe_SIZE; + unsigned int vgt_mh_send : MH_DEBUG_REG09_VGT_MH_send_SIZE; + unsigned int always_zero : MH_DEBUG_REG09_ALWAYS_ZERO_SIZE; + } mh_debug_reg09_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg09_t f; +} mh_debug_reg09_u; + + +/* + * MH_DEBUG_REG10 struct + */ + +#define MH_DEBUG_REG10_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG10_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG10_TC_MH_mask_SIZE 2 +#define MH_DEBUG_REG10_TC_MH_addr_31_5_SIZE 27 + +#define MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG10_TC_MH_send_SHIFT 2 +#define MH_DEBUG_REG10_TC_MH_mask_SHIFT 3 +#define MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT 5 + +#define MH_DEBUG_REG10_ALWAYS_ZERO_MASK 0x00000003 +#define MH_DEBUG_REG10_TC_MH_send_MASK 0x00000004 +#define MH_DEBUG_REG10_TC_MH_mask_MASK 0x00000018 +#define MH_DEBUG_REG10_TC_MH_addr_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG10_MASK \ + (MH_DEBUG_REG10_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG10_TC_MH_send_MASK | \ + MH_DEBUG_REG10_TC_MH_mask_MASK | \ + MH_DEBUG_REG10_TC_MH_addr_31_5_MASK) + +#define MH_DEBUG_REG10(always_zero, tc_mh_send, tc_mh_mask, tc_mh_addr_31_5) \ + ((always_zero << MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT) | \ + (tc_mh_send << MH_DEBUG_REG10_TC_MH_send_SHIFT) | \ + (tc_mh_mask << MH_DEBUG_REG10_TC_MH_mask_SHIFT) | \ + (tc_mh_addr_31_5 << MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT)) + +#define MH_DEBUG_REG10_GET_ALWAYS_ZERO(mh_debug_reg10) \ + ((mh_debug_reg10 & MH_DEBUG_REG10_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG10_GET_TC_MH_send(mh_debug_reg10) \ + ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_send_MASK) >> MH_DEBUG_REG10_TC_MH_send_SHIFT) +#define MH_DEBUG_REG10_GET_TC_MH_mask(mh_debug_reg10) \ + ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_mask_MASK) >> MH_DEBUG_REG10_TC_MH_mask_SHIFT) +#define MH_DEBUG_REG10_GET_TC_MH_addr_31_5(mh_debug_reg10) \ + ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_addr_31_5_MASK) >> MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT) + +#define MH_DEBUG_REG10_SET_ALWAYS_ZERO(mh_debug_reg10_reg, always_zero) \ + mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG10_SET_TC_MH_send(mh_debug_reg10_reg, tc_mh_send) \ + mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG10_TC_MH_send_SHIFT) +#define MH_DEBUG_REG10_SET_TC_MH_mask(mh_debug_reg10_reg, tc_mh_mask) \ + mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_mask_MASK) | (tc_mh_mask << MH_DEBUG_REG10_TC_MH_mask_SHIFT) +#define MH_DEBUG_REG10_SET_TC_MH_addr_31_5(mh_debug_reg10_reg, tc_mh_addr_31_5) \ + mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_addr_31_5_MASK) | (tc_mh_addr_31_5 << MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg10_t { + unsigned int always_zero : MH_DEBUG_REG10_ALWAYS_ZERO_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG10_TC_MH_send_SIZE; + unsigned int tc_mh_mask : MH_DEBUG_REG10_TC_MH_mask_SIZE; + unsigned int tc_mh_addr_31_5 : MH_DEBUG_REG10_TC_MH_addr_31_5_SIZE; + } mh_debug_reg10_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg10_t { + unsigned int tc_mh_addr_31_5 : MH_DEBUG_REG10_TC_MH_addr_31_5_SIZE; + unsigned int tc_mh_mask : MH_DEBUG_REG10_TC_MH_mask_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG10_TC_MH_send_SIZE; + unsigned int always_zero : MH_DEBUG_REG10_ALWAYS_ZERO_SIZE; + } mh_debug_reg10_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg10_t f; +} mh_debug_reg10_u; + + +/* + * MH_DEBUG_REG11 struct + */ + +#define MH_DEBUG_REG11_TC_MH_info_SIZE 25 +#define MH_DEBUG_REG11_TC_MH_send_SIZE 1 + +#define MH_DEBUG_REG11_TC_MH_info_SHIFT 0 +#define MH_DEBUG_REG11_TC_MH_send_SHIFT 25 + +#define MH_DEBUG_REG11_TC_MH_info_MASK 0x01ffffff +#define MH_DEBUG_REG11_TC_MH_send_MASK 0x02000000 + +#define MH_DEBUG_REG11_MASK \ + (MH_DEBUG_REG11_TC_MH_info_MASK | \ + MH_DEBUG_REG11_TC_MH_send_MASK) + +#define MH_DEBUG_REG11(tc_mh_info, tc_mh_send) \ + ((tc_mh_info << MH_DEBUG_REG11_TC_MH_info_SHIFT) | \ + (tc_mh_send << MH_DEBUG_REG11_TC_MH_send_SHIFT)) + +#define MH_DEBUG_REG11_GET_TC_MH_info(mh_debug_reg11) \ + ((mh_debug_reg11 & MH_DEBUG_REG11_TC_MH_info_MASK) >> MH_DEBUG_REG11_TC_MH_info_SHIFT) +#define MH_DEBUG_REG11_GET_TC_MH_send(mh_debug_reg11) \ + ((mh_debug_reg11 & MH_DEBUG_REG11_TC_MH_send_MASK) >> MH_DEBUG_REG11_TC_MH_send_SHIFT) + +#define MH_DEBUG_REG11_SET_TC_MH_info(mh_debug_reg11_reg, tc_mh_info) \ + mh_debug_reg11_reg = (mh_debug_reg11_reg & ~MH_DEBUG_REG11_TC_MH_info_MASK) | (tc_mh_info << MH_DEBUG_REG11_TC_MH_info_SHIFT) +#define MH_DEBUG_REG11_SET_TC_MH_send(mh_debug_reg11_reg, tc_mh_send) \ + mh_debug_reg11_reg = (mh_debug_reg11_reg & ~MH_DEBUG_REG11_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG11_TC_MH_send_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg11_t { + unsigned int tc_mh_info : MH_DEBUG_REG11_TC_MH_info_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG11_TC_MH_send_SIZE; + unsigned int : 6; + } mh_debug_reg11_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg11_t { + unsigned int : 6; + unsigned int tc_mh_send : MH_DEBUG_REG11_TC_MH_send_SIZE; + unsigned int tc_mh_info : MH_DEBUG_REG11_TC_MH_info_SIZE; + } mh_debug_reg11_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg11_t f; +} mh_debug_reg11_u; + + +/* + * MH_DEBUG_REG12 struct + */ + +#define MH_DEBUG_REG12_MH_TC_mcinfo_SIZE 25 +#define MH_DEBUG_REG12_MH_TC_mcinfo_send_SIZE 1 +#define MH_DEBUG_REG12_TC_MH_written_SIZE 1 + +#define MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT 0 +#define MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT 25 +#define MH_DEBUG_REG12_TC_MH_written_SHIFT 26 + +#define MH_DEBUG_REG12_MH_TC_mcinfo_MASK 0x01ffffff +#define MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK 0x02000000 +#define MH_DEBUG_REG12_TC_MH_written_MASK 0x04000000 + +#define MH_DEBUG_REG12_MASK \ + (MH_DEBUG_REG12_MH_TC_mcinfo_MASK | \ + MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK | \ + MH_DEBUG_REG12_TC_MH_written_MASK) + +#define MH_DEBUG_REG12(mh_tc_mcinfo, mh_tc_mcinfo_send, tc_mh_written) \ + ((mh_tc_mcinfo << MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT) | \ + (mh_tc_mcinfo_send << MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT) | \ + (tc_mh_written << MH_DEBUG_REG12_TC_MH_written_SHIFT)) + +#define MH_DEBUG_REG12_GET_MH_TC_mcinfo(mh_debug_reg12) \ + ((mh_debug_reg12 & MH_DEBUG_REG12_MH_TC_mcinfo_MASK) >> MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT) +#define MH_DEBUG_REG12_GET_MH_TC_mcinfo_send(mh_debug_reg12) \ + ((mh_debug_reg12 & MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK) >> MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT) +#define MH_DEBUG_REG12_GET_TC_MH_written(mh_debug_reg12) \ + ((mh_debug_reg12 & MH_DEBUG_REG12_TC_MH_written_MASK) >> MH_DEBUG_REG12_TC_MH_written_SHIFT) + +#define MH_DEBUG_REG12_SET_MH_TC_mcinfo(mh_debug_reg12_reg, mh_tc_mcinfo) \ + mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_MH_TC_mcinfo_MASK) | (mh_tc_mcinfo << MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT) +#define MH_DEBUG_REG12_SET_MH_TC_mcinfo_send(mh_debug_reg12_reg, mh_tc_mcinfo_send) \ + mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK) | (mh_tc_mcinfo_send << MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT) +#define MH_DEBUG_REG12_SET_TC_MH_written(mh_debug_reg12_reg, tc_mh_written) \ + mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG12_TC_MH_written_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg12_t { + unsigned int mh_tc_mcinfo : MH_DEBUG_REG12_MH_TC_mcinfo_SIZE; + unsigned int mh_tc_mcinfo_send : MH_DEBUG_REG12_MH_TC_mcinfo_send_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG12_TC_MH_written_SIZE; + unsigned int : 5; + } mh_debug_reg12_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg12_t { + unsigned int : 5; + unsigned int tc_mh_written : MH_DEBUG_REG12_TC_MH_written_SIZE; + unsigned int mh_tc_mcinfo_send : MH_DEBUG_REG12_MH_TC_mcinfo_send_SIZE; + unsigned int mh_tc_mcinfo : MH_DEBUG_REG12_MH_TC_mcinfo_SIZE; + } mh_debug_reg12_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg12_t f; +} mh_debug_reg12_u; + + +/* + * MH_DEBUG_REG13 struct + */ + +#define MH_DEBUG_REG13_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG13_TC_ROQ_SEND_SIZE 1 +#define MH_DEBUG_REG13_TC_ROQ_MASK_SIZE 2 +#define MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SIZE 27 + +#define MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT 2 +#define MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT 3 +#define MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT 5 + +#define MH_DEBUG_REG13_ALWAYS_ZERO_MASK 0x00000003 +#define MH_DEBUG_REG13_TC_ROQ_SEND_MASK 0x00000004 +#define MH_DEBUG_REG13_TC_ROQ_MASK_MASK 0x00000018 +#define MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG13_MASK \ + (MH_DEBUG_REG13_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG13_TC_ROQ_SEND_MASK | \ + MH_DEBUG_REG13_TC_ROQ_MASK_MASK | \ + MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK) + +#define MH_DEBUG_REG13(always_zero, tc_roq_send, tc_roq_mask, tc_roq_addr_31_5) \ + ((always_zero << MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT) | \ + (tc_roq_send << MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT) | \ + (tc_roq_mask << MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT) | \ + (tc_roq_addr_31_5 << MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT)) + +#define MH_DEBUG_REG13_GET_ALWAYS_ZERO(mh_debug_reg13) \ + ((mh_debug_reg13 & MH_DEBUG_REG13_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG13_GET_TC_ROQ_SEND(mh_debug_reg13) \ + ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_SEND_MASK) >> MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT) +#define MH_DEBUG_REG13_GET_TC_ROQ_MASK(mh_debug_reg13) \ + ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_MASK_MASK) >> MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT) +#define MH_DEBUG_REG13_GET_TC_ROQ_ADDR_31_5(mh_debug_reg13) \ + ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK) >> MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT) + +#define MH_DEBUG_REG13_SET_ALWAYS_ZERO(mh_debug_reg13_reg, always_zero) \ + mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG13_SET_TC_ROQ_SEND(mh_debug_reg13_reg, tc_roq_send) \ + mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_SEND_MASK) | (tc_roq_send << MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT) +#define MH_DEBUG_REG13_SET_TC_ROQ_MASK(mh_debug_reg13_reg, tc_roq_mask) \ + mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_MASK_MASK) | (tc_roq_mask << MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT) +#define MH_DEBUG_REG13_SET_TC_ROQ_ADDR_31_5(mh_debug_reg13_reg, tc_roq_addr_31_5) \ + mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK) | (tc_roq_addr_31_5 << MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg13_t { + unsigned int always_zero : MH_DEBUG_REG13_ALWAYS_ZERO_SIZE; + unsigned int tc_roq_send : MH_DEBUG_REG13_TC_ROQ_SEND_SIZE; + unsigned int tc_roq_mask : MH_DEBUG_REG13_TC_ROQ_MASK_SIZE; + unsigned int tc_roq_addr_31_5 : MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SIZE; + } mh_debug_reg13_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg13_t { + unsigned int tc_roq_addr_31_5 : MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SIZE; + unsigned int tc_roq_mask : MH_DEBUG_REG13_TC_ROQ_MASK_SIZE; + unsigned int tc_roq_send : MH_DEBUG_REG13_TC_ROQ_SEND_SIZE; + unsigned int always_zero : MH_DEBUG_REG13_ALWAYS_ZERO_SIZE; + } mh_debug_reg13_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg13_t f; +} mh_debug_reg13_u; + + +/* + * MH_DEBUG_REG14 struct + */ + +#define MH_DEBUG_REG14_TC_ROQ_INFO_SIZE 25 +#define MH_DEBUG_REG14_TC_ROQ_SEND_SIZE 1 + +#define MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT 0 +#define MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT 25 + +#define MH_DEBUG_REG14_TC_ROQ_INFO_MASK 0x01ffffff +#define MH_DEBUG_REG14_TC_ROQ_SEND_MASK 0x02000000 + +#define MH_DEBUG_REG14_MASK \ + (MH_DEBUG_REG14_TC_ROQ_INFO_MASK | \ + MH_DEBUG_REG14_TC_ROQ_SEND_MASK) + +#define MH_DEBUG_REG14(tc_roq_info, tc_roq_send) \ + ((tc_roq_info << MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT) | \ + (tc_roq_send << MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT)) + +#define MH_DEBUG_REG14_GET_TC_ROQ_INFO(mh_debug_reg14) \ + ((mh_debug_reg14 & MH_DEBUG_REG14_TC_ROQ_INFO_MASK) >> MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT) +#define MH_DEBUG_REG14_GET_TC_ROQ_SEND(mh_debug_reg14) \ + ((mh_debug_reg14 & MH_DEBUG_REG14_TC_ROQ_SEND_MASK) >> MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT) + +#define MH_DEBUG_REG14_SET_TC_ROQ_INFO(mh_debug_reg14_reg, tc_roq_info) \ + mh_debug_reg14_reg = (mh_debug_reg14_reg & ~MH_DEBUG_REG14_TC_ROQ_INFO_MASK) | (tc_roq_info << MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT) +#define MH_DEBUG_REG14_SET_TC_ROQ_SEND(mh_debug_reg14_reg, tc_roq_send) \ + mh_debug_reg14_reg = (mh_debug_reg14_reg & ~MH_DEBUG_REG14_TC_ROQ_SEND_MASK) | (tc_roq_send << MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg14_t { + unsigned int tc_roq_info : MH_DEBUG_REG14_TC_ROQ_INFO_SIZE; + unsigned int tc_roq_send : MH_DEBUG_REG14_TC_ROQ_SEND_SIZE; + unsigned int : 6; + } mh_debug_reg14_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg14_t { + unsigned int : 6; + unsigned int tc_roq_send : MH_DEBUG_REG14_TC_ROQ_SEND_SIZE; + unsigned int tc_roq_info : MH_DEBUG_REG14_TC_ROQ_INFO_SIZE; + } mh_debug_reg14_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg14_t f; +} mh_debug_reg14_u; + + +/* + * MH_DEBUG_REG15 struct + */ + +#define MH_DEBUG_REG15_ALWAYS_ZERO_SIZE 4 +#define MH_DEBUG_REG15_RB_MH_send_SIZE 1 +#define MH_DEBUG_REG15_RB_MH_addr_31_5_SIZE 27 + +#define MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG15_RB_MH_send_SHIFT 4 +#define MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT 5 + +#define MH_DEBUG_REG15_ALWAYS_ZERO_MASK 0x0000000f +#define MH_DEBUG_REG15_RB_MH_send_MASK 0x00000010 +#define MH_DEBUG_REG15_RB_MH_addr_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG15_MASK \ + (MH_DEBUG_REG15_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG15_RB_MH_send_MASK | \ + MH_DEBUG_REG15_RB_MH_addr_31_5_MASK) + +#define MH_DEBUG_REG15(always_zero, rb_mh_send, rb_mh_addr_31_5) \ + ((always_zero << MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT) | \ + (rb_mh_send << MH_DEBUG_REG15_RB_MH_send_SHIFT) | \ + (rb_mh_addr_31_5 << MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT)) + +#define MH_DEBUG_REG15_GET_ALWAYS_ZERO(mh_debug_reg15) \ + ((mh_debug_reg15 & MH_DEBUG_REG15_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG15_GET_RB_MH_send(mh_debug_reg15) \ + ((mh_debug_reg15 & MH_DEBUG_REG15_RB_MH_send_MASK) >> MH_DEBUG_REG15_RB_MH_send_SHIFT) +#define MH_DEBUG_REG15_GET_RB_MH_addr_31_5(mh_debug_reg15) \ + ((mh_debug_reg15 & MH_DEBUG_REG15_RB_MH_addr_31_5_MASK) >> MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT) + +#define MH_DEBUG_REG15_SET_ALWAYS_ZERO(mh_debug_reg15_reg, always_zero) \ + mh_debug_reg15_reg = (mh_debug_reg15_reg & ~MH_DEBUG_REG15_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG15_SET_RB_MH_send(mh_debug_reg15_reg, rb_mh_send) \ + mh_debug_reg15_reg = (mh_debug_reg15_reg & ~MH_DEBUG_REG15_RB_MH_send_MASK) | (rb_mh_send << MH_DEBUG_REG15_RB_MH_send_SHIFT) +#define MH_DEBUG_REG15_SET_RB_MH_addr_31_5(mh_debug_reg15_reg, rb_mh_addr_31_5) \ + mh_debug_reg15_reg = (mh_debug_reg15_reg & ~MH_DEBUG_REG15_RB_MH_addr_31_5_MASK) | (rb_mh_addr_31_5 << MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg15_t { + unsigned int always_zero : MH_DEBUG_REG15_ALWAYS_ZERO_SIZE; + unsigned int rb_mh_send : MH_DEBUG_REG15_RB_MH_send_SIZE; + unsigned int rb_mh_addr_31_5 : MH_DEBUG_REG15_RB_MH_addr_31_5_SIZE; + } mh_debug_reg15_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg15_t { + unsigned int rb_mh_addr_31_5 : MH_DEBUG_REG15_RB_MH_addr_31_5_SIZE; + unsigned int rb_mh_send : MH_DEBUG_REG15_RB_MH_send_SIZE; + unsigned int always_zero : MH_DEBUG_REG15_ALWAYS_ZERO_SIZE; + } mh_debug_reg15_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg15_t f; +} mh_debug_reg15_u; + + +/* + * MH_DEBUG_REG16 struct + */ + +#define MH_DEBUG_REG16_RB_MH_data_31_0_SIZE 32 + +#define MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT 0 + +#define MH_DEBUG_REG16_RB_MH_data_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG16_MASK \ + (MH_DEBUG_REG16_RB_MH_data_31_0_MASK) + +#define MH_DEBUG_REG16(rb_mh_data_31_0) \ + ((rb_mh_data_31_0 << MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT)) + +#define MH_DEBUG_REG16_GET_RB_MH_data_31_0(mh_debug_reg16) \ + ((mh_debug_reg16 & MH_DEBUG_REG16_RB_MH_data_31_0_MASK) >> MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT) + +#define MH_DEBUG_REG16_SET_RB_MH_data_31_0(mh_debug_reg16_reg, rb_mh_data_31_0) \ + mh_debug_reg16_reg = (mh_debug_reg16_reg & ~MH_DEBUG_REG16_RB_MH_data_31_0_MASK) | (rb_mh_data_31_0 << MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg16_t { + unsigned int rb_mh_data_31_0 : MH_DEBUG_REG16_RB_MH_data_31_0_SIZE; + } mh_debug_reg16_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg16_t { + unsigned int rb_mh_data_31_0 : MH_DEBUG_REG16_RB_MH_data_31_0_SIZE; + } mh_debug_reg16_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg16_t f; +} mh_debug_reg16_u; + + +/* + * MH_DEBUG_REG17 struct + */ + +#define MH_DEBUG_REG17_RB_MH_data_63_32_SIZE 32 + +#define MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT 0 + +#define MH_DEBUG_REG17_RB_MH_data_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG17_MASK \ + (MH_DEBUG_REG17_RB_MH_data_63_32_MASK) + +#define MH_DEBUG_REG17(rb_mh_data_63_32) \ + ((rb_mh_data_63_32 << MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT)) + +#define MH_DEBUG_REG17_GET_RB_MH_data_63_32(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_RB_MH_data_63_32_MASK) >> MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT) + +#define MH_DEBUG_REG17_SET_RB_MH_data_63_32(mh_debug_reg17_reg, rb_mh_data_63_32) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_RB_MH_data_63_32_MASK) | (rb_mh_data_63_32 << MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg17_t { + unsigned int rb_mh_data_63_32 : MH_DEBUG_REG17_RB_MH_data_63_32_SIZE; + } mh_debug_reg17_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg17_t { + unsigned int rb_mh_data_63_32 : MH_DEBUG_REG17_RB_MH_data_63_32_SIZE; + } mh_debug_reg17_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg17_t f; +} mh_debug_reg17_u; + + +/* + * MH_DEBUG_REG18 struct + */ + +#define MH_DEBUG_REG18_ALWAYS_ZERO_SIZE 4 +#define MH_DEBUG_REG18_PA_MH_send_SIZE 1 +#define MH_DEBUG_REG18_PA_MH_addr_31_5_SIZE 27 + +#define MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG18_PA_MH_send_SHIFT 4 +#define MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT 5 + +#define MH_DEBUG_REG18_ALWAYS_ZERO_MASK 0x0000000f +#define MH_DEBUG_REG18_PA_MH_send_MASK 0x00000010 +#define MH_DEBUG_REG18_PA_MH_addr_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG18_MASK \ + (MH_DEBUG_REG18_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG18_PA_MH_send_MASK | \ + MH_DEBUG_REG18_PA_MH_addr_31_5_MASK) + +#define MH_DEBUG_REG18(always_zero, pa_mh_send, pa_mh_addr_31_5) \ + ((always_zero << MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT) | \ + (pa_mh_send << MH_DEBUG_REG18_PA_MH_send_SHIFT) | \ + (pa_mh_addr_31_5 << MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT)) + +#define MH_DEBUG_REG18_GET_ALWAYS_ZERO(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG18_GET_PA_MH_send(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_PA_MH_send_MASK) >> MH_DEBUG_REG18_PA_MH_send_SHIFT) +#define MH_DEBUG_REG18_GET_PA_MH_addr_31_5(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_PA_MH_addr_31_5_MASK) >> MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT) + +#define MH_DEBUG_REG18_SET_ALWAYS_ZERO(mh_debug_reg18_reg, always_zero) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG18_SET_PA_MH_send(mh_debug_reg18_reg, pa_mh_send) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_PA_MH_send_MASK) | (pa_mh_send << MH_DEBUG_REG18_PA_MH_send_SHIFT) +#define MH_DEBUG_REG18_SET_PA_MH_addr_31_5(mh_debug_reg18_reg, pa_mh_addr_31_5) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_PA_MH_addr_31_5_MASK) | (pa_mh_addr_31_5 << MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg18_t { + unsigned int always_zero : MH_DEBUG_REG18_ALWAYS_ZERO_SIZE; + unsigned int pa_mh_send : MH_DEBUG_REG18_PA_MH_send_SIZE; + unsigned int pa_mh_addr_31_5 : MH_DEBUG_REG18_PA_MH_addr_31_5_SIZE; + } mh_debug_reg18_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg18_t { + unsigned int pa_mh_addr_31_5 : MH_DEBUG_REG18_PA_MH_addr_31_5_SIZE; + unsigned int pa_mh_send : MH_DEBUG_REG18_PA_MH_send_SIZE; + unsigned int always_zero : MH_DEBUG_REG18_ALWAYS_ZERO_SIZE; + } mh_debug_reg18_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg18_t f; +} mh_debug_reg18_u; + + +/* + * MH_DEBUG_REG19 struct + */ + +#define MH_DEBUG_REG19_PA_MH_data_31_0_SIZE 32 + +#define MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT 0 + +#define MH_DEBUG_REG19_PA_MH_data_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG19_MASK \ + (MH_DEBUG_REG19_PA_MH_data_31_0_MASK) + +#define MH_DEBUG_REG19(pa_mh_data_31_0) \ + ((pa_mh_data_31_0 << MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT)) + +#define MH_DEBUG_REG19_GET_PA_MH_data_31_0(mh_debug_reg19) \ + ((mh_debug_reg19 & MH_DEBUG_REG19_PA_MH_data_31_0_MASK) >> MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT) + +#define MH_DEBUG_REG19_SET_PA_MH_data_31_0(mh_debug_reg19_reg, pa_mh_data_31_0) \ + mh_debug_reg19_reg = (mh_debug_reg19_reg & ~MH_DEBUG_REG19_PA_MH_data_31_0_MASK) | (pa_mh_data_31_0 << MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg19_t { + unsigned int pa_mh_data_31_0 : MH_DEBUG_REG19_PA_MH_data_31_0_SIZE; + } mh_debug_reg19_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg19_t { + unsigned int pa_mh_data_31_0 : MH_DEBUG_REG19_PA_MH_data_31_0_SIZE; + } mh_debug_reg19_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg19_t f; +} mh_debug_reg19_u; + + +/* + * MH_DEBUG_REG20 struct + */ + +#define MH_DEBUG_REG20_PA_MH_data_63_32_SIZE 32 + +#define MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT 0 + +#define MH_DEBUG_REG20_PA_MH_data_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG20_MASK \ + (MH_DEBUG_REG20_PA_MH_data_63_32_MASK) + +#define MH_DEBUG_REG20(pa_mh_data_63_32) \ + ((pa_mh_data_63_32 << MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT)) + +#define MH_DEBUG_REG20_GET_PA_MH_data_63_32(mh_debug_reg20) \ + ((mh_debug_reg20 & MH_DEBUG_REG20_PA_MH_data_63_32_MASK) >> MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT) + +#define MH_DEBUG_REG20_SET_PA_MH_data_63_32(mh_debug_reg20_reg, pa_mh_data_63_32) \ + mh_debug_reg20_reg = (mh_debug_reg20_reg & ~MH_DEBUG_REG20_PA_MH_data_63_32_MASK) | (pa_mh_data_63_32 << MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg20_t { + unsigned int pa_mh_data_63_32 : MH_DEBUG_REG20_PA_MH_data_63_32_SIZE; + } mh_debug_reg20_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg20_t { + unsigned int pa_mh_data_63_32 : MH_DEBUG_REG20_PA_MH_data_63_32_SIZE; + } mh_debug_reg20_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg20_t f; +} mh_debug_reg20_u; + + +/* + * MH_DEBUG_REG21 struct + */ + +#define MH_DEBUG_REG21_AVALID_q_SIZE 1 +#define MH_DEBUG_REG21_AREADY_q_SIZE 1 +#define MH_DEBUG_REG21_AID_q_SIZE 3 +#define MH_DEBUG_REG21_ALEN_q_2_0_SIZE 3 +#define MH_DEBUG_REG21_ARVALID_q_SIZE 1 +#define MH_DEBUG_REG21_ARREADY_q_SIZE 1 +#define MH_DEBUG_REG21_ARID_q_SIZE 3 +#define MH_DEBUG_REG21_ARLEN_q_1_0_SIZE 2 +#define MH_DEBUG_REG21_RVALID_q_SIZE 1 +#define MH_DEBUG_REG21_RREADY_q_SIZE 1 +#define MH_DEBUG_REG21_RLAST_q_SIZE 1 +#define MH_DEBUG_REG21_RID_q_SIZE 3 +#define MH_DEBUG_REG21_WVALID_q_SIZE 1 +#define MH_DEBUG_REG21_WREADY_q_SIZE 1 +#define MH_DEBUG_REG21_WLAST_q_SIZE 1 +#define MH_DEBUG_REG21_WID_q_SIZE 3 +#define MH_DEBUG_REG21_BVALID_q_SIZE 1 +#define MH_DEBUG_REG21_BREADY_q_SIZE 1 +#define MH_DEBUG_REG21_BID_q_SIZE 3 + +#define MH_DEBUG_REG21_AVALID_q_SHIFT 0 +#define MH_DEBUG_REG21_AREADY_q_SHIFT 1 +#define MH_DEBUG_REG21_AID_q_SHIFT 2 +#define MH_DEBUG_REG21_ALEN_q_2_0_SHIFT 5 +#define MH_DEBUG_REG21_ARVALID_q_SHIFT 8 +#define MH_DEBUG_REG21_ARREADY_q_SHIFT 9 +#define MH_DEBUG_REG21_ARID_q_SHIFT 10 +#define MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT 13 +#define MH_DEBUG_REG21_RVALID_q_SHIFT 15 +#define MH_DEBUG_REG21_RREADY_q_SHIFT 16 +#define MH_DEBUG_REG21_RLAST_q_SHIFT 17 +#define MH_DEBUG_REG21_RID_q_SHIFT 18 +#define MH_DEBUG_REG21_WVALID_q_SHIFT 21 +#define MH_DEBUG_REG21_WREADY_q_SHIFT 22 +#define MH_DEBUG_REG21_WLAST_q_SHIFT 23 +#define MH_DEBUG_REG21_WID_q_SHIFT 24 +#define MH_DEBUG_REG21_BVALID_q_SHIFT 27 +#define MH_DEBUG_REG21_BREADY_q_SHIFT 28 +#define MH_DEBUG_REG21_BID_q_SHIFT 29 + +#define MH_DEBUG_REG21_AVALID_q_MASK 0x00000001 +#define MH_DEBUG_REG21_AREADY_q_MASK 0x00000002 +#define MH_DEBUG_REG21_AID_q_MASK 0x0000001c +#define MH_DEBUG_REG21_ALEN_q_2_0_MASK 0x000000e0 +#define MH_DEBUG_REG21_ARVALID_q_MASK 0x00000100 +#define MH_DEBUG_REG21_ARREADY_q_MASK 0x00000200 +#define MH_DEBUG_REG21_ARID_q_MASK 0x00001c00 +#define MH_DEBUG_REG21_ARLEN_q_1_0_MASK 0x00006000 +#define MH_DEBUG_REG21_RVALID_q_MASK 0x00008000 +#define MH_DEBUG_REG21_RREADY_q_MASK 0x00010000 +#define MH_DEBUG_REG21_RLAST_q_MASK 0x00020000 +#define MH_DEBUG_REG21_RID_q_MASK 0x001c0000 +#define MH_DEBUG_REG21_WVALID_q_MASK 0x00200000 +#define MH_DEBUG_REG21_WREADY_q_MASK 0x00400000 +#define MH_DEBUG_REG21_WLAST_q_MASK 0x00800000 +#define MH_DEBUG_REG21_WID_q_MASK 0x07000000 +#define MH_DEBUG_REG21_BVALID_q_MASK 0x08000000 +#define MH_DEBUG_REG21_BREADY_q_MASK 0x10000000 +#define MH_DEBUG_REG21_BID_q_MASK 0xe0000000 + +#define MH_DEBUG_REG21_MASK \ + (MH_DEBUG_REG21_AVALID_q_MASK | \ + MH_DEBUG_REG21_AREADY_q_MASK | \ + MH_DEBUG_REG21_AID_q_MASK | \ + MH_DEBUG_REG21_ALEN_q_2_0_MASK | \ + MH_DEBUG_REG21_ARVALID_q_MASK | \ + MH_DEBUG_REG21_ARREADY_q_MASK | \ + MH_DEBUG_REG21_ARID_q_MASK | \ + MH_DEBUG_REG21_ARLEN_q_1_0_MASK | \ + MH_DEBUG_REG21_RVALID_q_MASK | \ + MH_DEBUG_REG21_RREADY_q_MASK | \ + MH_DEBUG_REG21_RLAST_q_MASK | \ + MH_DEBUG_REG21_RID_q_MASK | \ + MH_DEBUG_REG21_WVALID_q_MASK | \ + MH_DEBUG_REG21_WREADY_q_MASK | \ + MH_DEBUG_REG21_WLAST_q_MASK | \ + MH_DEBUG_REG21_WID_q_MASK | \ + MH_DEBUG_REG21_BVALID_q_MASK | \ + MH_DEBUG_REG21_BREADY_q_MASK | \ + MH_DEBUG_REG21_BID_q_MASK) + +#define MH_DEBUG_REG21(avalid_q, aready_q, aid_q, alen_q_2_0, arvalid_q, arready_q, arid_q, arlen_q_1_0, rvalid_q, rready_q, rlast_q, rid_q, wvalid_q, wready_q, wlast_q, wid_q, bvalid_q, bready_q, bid_q) \ + ((avalid_q << MH_DEBUG_REG21_AVALID_q_SHIFT) | \ + (aready_q << MH_DEBUG_REG21_AREADY_q_SHIFT) | \ + (aid_q << MH_DEBUG_REG21_AID_q_SHIFT) | \ + (alen_q_2_0 << MH_DEBUG_REG21_ALEN_q_2_0_SHIFT) | \ + (arvalid_q << MH_DEBUG_REG21_ARVALID_q_SHIFT) | \ + (arready_q << MH_DEBUG_REG21_ARREADY_q_SHIFT) | \ + (arid_q << MH_DEBUG_REG21_ARID_q_SHIFT) | \ + (arlen_q_1_0 << MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT) | \ + (rvalid_q << MH_DEBUG_REG21_RVALID_q_SHIFT) | \ + (rready_q << MH_DEBUG_REG21_RREADY_q_SHIFT) | \ + (rlast_q << MH_DEBUG_REG21_RLAST_q_SHIFT) | \ + (rid_q << MH_DEBUG_REG21_RID_q_SHIFT) | \ + (wvalid_q << MH_DEBUG_REG21_WVALID_q_SHIFT) | \ + (wready_q << MH_DEBUG_REG21_WREADY_q_SHIFT) | \ + (wlast_q << MH_DEBUG_REG21_WLAST_q_SHIFT) | \ + (wid_q << MH_DEBUG_REG21_WID_q_SHIFT) | \ + (bvalid_q << MH_DEBUG_REG21_BVALID_q_SHIFT) | \ + (bready_q << MH_DEBUG_REG21_BREADY_q_SHIFT) | \ + (bid_q << MH_DEBUG_REG21_BID_q_SHIFT)) + +#define MH_DEBUG_REG21_GET_AVALID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_AVALID_q_MASK) >> MH_DEBUG_REG21_AVALID_q_SHIFT) +#define MH_DEBUG_REG21_GET_AREADY_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_AREADY_q_MASK) >> MH_DEBUG_REG21_AREADY_q_SHIFT) +#define MH_DEBUG_REG21_GET_AID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_AID_q_MASK) >> MH_DEBUG_REG21_AID_q_SHIFT) +#define MH_DEBUG_REG21_GET_ALEN_q_2_0(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_ALEN_q_2_0_MASK) >> MH_DEBUG_REG21_ALEN_q_2_0_SHIFT) +#define MH_DEBUG_REG21_GET_ARVALID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_ARVALID_q_MASK) >> MH_DEBUG_REG21_ARVALID_q_SHIFT) +#define MH_DEBUG_REG21_GET_ARREADY_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_ARREADY_q_MASK) >> MH_DEBUG_REG21_ARREADY_q_SHIFT) +#define MH_DEBUG_REG21_GET_ARID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_ARID_q_MASK) >> MH_DEBUG_REG21_ARID_q_SHIFT) +#define MH_DEBUG_REG21_GET_ARLEN_q_1_0(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_ARLEN_q_1_0_MASK) >> MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT) +#define MH_DEBUG_REG21_GET_RVALID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_RVALID_q_MASK) >> MH_DEBUG_REG21_RVALID_q_SHIFT) +#define MH_DEBUG_REG21_GET_RREADY_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_RREADY_q_MASK) >> MH_DEBUG_REG21_RREADY_q_SHIFT) +#define MH_DEBUG_REG21_GET_RLAST_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_RLAST_q_MASK) >> MH_DEBUG_REG21_RLAST_q_SHIFT) +#define MH_DEBUG_REG21_GET_RID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_RID_q_MASK) >> MH_DEBUG_REG21_RID_q_SHIFT) +#define MH_DEBUG_REG21_GET_WVALID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_WVALID_q_MASK) >> MH_DEBUG_REG21_WVALID_q_SHIFT) +#define MH_DEBUG_REG21_GET_WREADY_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_WREADY_q_MASK) >> MH_DEBUG_REG21_WREADY_q_SHIFT) +#define MH_DEBUG_REG21_GET_WLAST_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_WLAST_q_MASK) >> MH_DEBUG_REG21_WLAST_q_SHIFT) +#define MH_DEBUG_REG21_GET_WID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_WID_q_MASK) >> MH_DEBUG_REG21_WID_q_SHIFT) +#define MH_DEBUG_REG21_GET_BVALID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_BVALID_q_MASK) >> MH_DEBUG_REG21_BVALID_q_SHIFT) +#define MH_DEBUG_REG21_GET_BREADY_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_BREADY_q_MASK) >> MH_DEBUG_REG21_BREADY_q_SHIFT) +#define MH_DEBUG_REG21_GET_BID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_BID_q_MASK) >> MH_DEBUG_REG21_BID_q_SHIFT) + +#define MH_DEBUG_REG21_SET_AVALID_q(mh_debug_reg21_reg, avalid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_AVALID_q_MASK) | (avalid_q << MH_DEBUG_REG21_AVALID_q_SHIFT) +#define MH_DEBUG_REG21_SET_AREADY_q(mh_debug_reg21_reg, aready_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_AREADY_q_MASK) | (aready_q << MH_DEBUG_REG21_AREADY_q_SHIFT) +#define MH_DEBUG_REG21_SET_AID_q(mh_debug_reg21_reg, aid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_AID_q_MASK) | (aid_q << MH_DEBUG_REG21_AID_q_SHIFT) +#define MH_DEBUG_REG21_SET_ALEN_q_2_0(mh_debug_reg21_reg, alen_q_2_0) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ALEN_q_2_0_MASK) | (alen_q_2_0 << MH_DEBUG_REG21_ALEN_q_2_0_SHIFT) +#define MH_DEBUG_REG21_SET_ARVALID_q(mh_debug_reg21_reg, arvalid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARVALID_q_MASK) | (arvalid_q << MH_DEBUG_REG21_ARVALID_q_SHIFT) +#define MH_DEBUG_REG21_SET_ARREADY_q(mh_debug_reg21_reg, arready_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARREADY_q_MASK) | (arready_q << MH_DEBUG_REG21_ARREADY_q_SHIFT) +#define MH_DEBUG_REG21_SET_ARID_q(mh_debug_reg21_reg, arid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARID_q_MASK) | (arid_q << MH_DEBUG_REG21_ARID_q_SHIFT) +#define MH_DEBUG_REG21_SET_ARLEN_q_1_0(mh_debug_reg21_reg, arlen_q_1_0) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARLEN_q_1_0_MASK) | (arlen_q_1_0 << MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT) +#define MH_DEBUG_REG21_SET_RVALID_q(mh_debug_reg21_reg, rvalid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RVALID_q_MASK) | (rvalid_q << MH_DEBUG_REG21_RVALID_q_SHIFT) +#define MH_DEBUG_REG21_SET_RREADY_q(mh_debug_reg21_reg, rready_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RREADY_q_MASK) | (rready_q << MH_DEBUG_REG21_RREADY_q_SHIFT) +#define MH_DEBUG_REG21_SET_RLAST_q(mh_debug_reg21_reg, rlast_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RLAST_q_MASK) | (rlast_q << MH_DEBUG_REG21_RLAST_q_SHIFT) +#define MH_DEBUG_REG21_SET_RID_q(mh_debug_reg21_reg, rid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RID_q_MASK) | (rid_q << MH_DEBUG_REG21_RID_q_SHIFT) +#define MH_DEBUG_REG21_SET_WVALID_q(mh_debug_reg21_reg, wvalid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WVALID_q_MASK) | (wvalid_q << MH_DEBUG_REG21_WVALID_q_SHIFT) +#define MH_DEBUG_REG21_SET_WREADY_q(mh_debug_reg21_reg, wready_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WREADY_q_MASK) | (wready_q << MH_DEBUG_REG21_WREADY_q_SHIFT) +#define MH_DEBUG_REG21_SET_WLAST_q(mh_debug_reg21_reg, wlast_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG21_WLAST_q_SHIFT) +#define MH_DEBUG_REG21_SET_WID_q(mh_debug_reg21_reg, wid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WID_q_MASK) | (wid_q << MH_DEBUG_REG21_WID_q_SHIFT) +#define MH_DEBUG_REG21_SET_BVALID_q(mh_debug_reg21_reg, bvalid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG21_BVALID_q_SHIFT) +#define MH_DEBUG_REG21_SET_BREADY_q(mh_debug_reg21_reg, bready_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG21_BREADY_q_SHIFT) +#define MH_DEBUG_REG21_SET_BID_q(mh_debug_reg21_reg, bid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_BID_q_MASK) | (bid_q << MH_DEBUG_REG21_BID_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg21_t { + unsigned int avalid_q : MH_DEBUG_REG21_AVALID_q_SIZE; + unsigned int aready_q : MH_DEBUG_REG21_AREADY_q_SIZE; + unsigned int aid_q : MH_DEBUG_REG21_AID_q_SIZE; + unsigned int alen_q_2_0 : MH_DEBUG_REG21_ALEN_q_2_0_SIZE; + unsigned int arvalid_q : MH_DEBUG_REG21_ARVALID_q_SIZE; + unsigned int arready_q : MH_DEBUG_REG21_ARREADY_q_SIZE; + unsigned int arid_q : MH_DEBUG_REG21_ARID_q_SIZE; + unsigned int arlen_q_1_0 : MH_DEBUG_REG21_ARLEN_q_1_0_SIZE; + unsigned int rvalid_q : MH_DEBUG_REG21_RVALID_q_SIZE; + unsigned int rready_q : MH_DEBUG_REG21_RREADY_q_SIZE; + unsigned int rlast_q : MH_DEBUG_REG21_RLAST_q_SIZE; + unsigned int rid_q : MH_DEBUG_REG21_RID_q_SIZE; + unsigned int wvalid_q : MH_DEBUG_REG21_WVALID_q_SIZE; + unsigned int wready_q : MH_DEBUG_REG21_WREADY_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG21_WLAST_q_SIZE; + unsigned int wid_q : MH_DEBUG_REG21_WID_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG21_BVALID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG21_BREADY_q_SIZE; + unsigned int bid_q : MH_DEBUG_REG21_BID_q_SIZE; + } mh_debug_reg21_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg21_t { + unsigned int bid_q : MH_DEBUG_REG21_BID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG21_BREADY_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG21_BVALID_q_SIZE; + unsigned int wid_q : MH_DEBUG_REG21_WID_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG21_WLAST_q_SIZE; + unsigned int wready_q : MH_DEBUG_REG21_WREADY_q_SIZE; + unsigned int wvalid_q : MH_DEBUG_REG21_WVALID_q_SIZE; + unsigned int rid_q : MH_DEBUG_REG21_RID_q_SIZE; + unsigned int rlast_q : MH_DEBUG_REG21_RLAST_q_SIZE; + unsigned int rready_q : MH_DEBUG_REG21_RREADY_q_SIZE; + unsigned int rvalid_q : MH_DEBUG_REG21_RVALID_q_SIZE; + unsigned int arlen_q_1_0 : MH_DEBUG_REG21_ARLEN_q_1_0_SIZE; + unsigned int arid_q : MH_DEBUG_REG21_ARID_q_SIZE; + unsigned int arready_q : MH_DEBUG_REG21_ARREADY_q_SIZE; + unsigned int arvalid_q : MH_DEBUG_REG21_ARVALID_q_SIZE; + unsigned int alen_q_2_0 : MH_DEBUG_REG21_ALEN_q_2_0_SIZE; + unsigned int aid_q : MH_DEBUG_REG21_AID_q_SIZE; + unsigned int aready_q : MH_DEBUG_REG21_AREADY_q_SIZE; + unsigned int avalid_q : MH_DEBUG_REG21_AVALID_q_SIZE; + } mh_debug_reg21_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg21_t f; +} mh_debug_reg21_u; + + +/* + * MH_DEBUG_REG22 struct + */ + +#define MH_DEBUG_REG22_AVALID_q_SIZE 1 +#define MH_DEBUG_REG22_AREADY_q_SIZE 1 +#define MH_DEBUG_REG22_AID_q_SIZE 3 +#define MH_DEBUG_REG22_ALEN_q_1_0_SIZE 2 +#define MH_DEBUG_REG22_ARVALID_q_SIZE 1 +#define MH_DEBUG_REG22_ARREADY_q_SIZE 1 +#define MH_DEBUG_REG22_ARID_q_SIZE 3 +#define MH_DEBUG_REG22_ARLEN_q_1_1_SIZE 1 +#define MH_DEBUG_REG22_WVALID_q_SIZE 1 +#define MH_DEBUG_REG22_WREADY_q_SIZE 1 +#define MH_DEBUG_REG22_WLAST_q_SIZE 1 +#define MH_DEBUG_REG22_WID_q_SIZE 3 +#define MH_DEBUG_REG22_WSTRB_q_SIZE 8 +#define MH_DEBUG_REG22_BVALID_q_SIZE 1 +#define MH_DEBUG_REG22_BREADY_q_SIZE 1 +#define MH_DEBUG_REG22_BID_q_SIZE 3 + +#define MH_DEBUG_REG22_AVALID_q_SHIFT 0 +#define MH_DEBUG_REG22_AREADY_q_SHIFT 1 +#define MH_DEBUG_REG22_AID_q_SHIFT 2 +#define MH_DEBUG_REG22_ALEN_q_1_0_SHIFT 5 +#define MH_DEBUG_REG22_ARVALID_q_SHIFT 7 +#define MH_DEBUG_REG22_ARREADY_q_SHIFT 8 +#define MH_DEBUG_REG22_ARID_q_SHIFT 9 +#define MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT 12 +#define MH_DEBUG_REG22_WVALID_q_SHIFT 13 +#define MH_DEBUG_REG22_WREADY_q_SHIFT 14 +#define MH_DEBUG_REG22_WLAST_q_SHIFT 15 +#define MH_DEBUG_REG22_WID_q_SHIFT 16 +#define MH_DEBUG_REG22_WSTRB_q_SHIFT 19 +#define MH_DEBUG_REG22_BVALID_q_SHIFT 27 +#define MH_DEBUG_REG22_BREADY_q_SHIFT 28 +#define MH_DEBUG_REG22_BID_q_SHIFT 29 + +#define MH_DEBUG_REG22_AVALID_q_MASK 0x00000001 +#define MH_DEBUG_REG22_AREADY_q_MASK 0x00000002 +#define MH_DEBUG_REG22_AID_q_MASK 0x0000001c +#define MH_DEBUG_REG22_ALEN_q_1_0_MASK 0x00000060 +#define MH_DEBUG_REG22_ARVALID_q_MASK 0x00000080 +#define MH_DEBUG_REG22_ARREADY_q_MASK 0x00000100 +#define MH_DEBUG_REG22_ARID_q_MASK 0x00000e00 +#define MH_DEBUG_REG22_ARLEN_q_1_1_MASK 0x00001000 +#define MH_DEBUG_REG22_WVALID_q_MASK 0x00002000 +#define MH_DEBUG_REG22_WREADY_q_MASK 0x00004000 +#define MH_DEBUG_REG22_WLAST_q_MASK 0x00008000 +#define MH_DEBUG_REG22_WID_q_MASK 0x00070000 +#define MH_DEBUG_REG22_WSTRB_q_MASK 0x07f80000 +#define MH_DEBUG_REG22_BVALID_q_MASK 0x08000000 +#define MH_DEBUG_REG22_BREADY_q_MASK 0x10000000 +#define MH_DEBUG_REG22_BID_q_MASK 0xe0000000 + +#define MH_DEBUG_REG22_MASK \ + (MH_DEBUG_REG22_AVALID_q_MASK | \ + MH_DEBUG_REG22_AREADY_q_MASK | \ + MH_DEBUG_REG22_AID_q_MASK | \ + MH_DEBUG_REG22_ALEN_q_1_0_MASK | \ + MH_DEBUG_REG22_ARVALID_q_MASK | \ + MH_DEBUG_REG22_ARREADY_q_MASK | \ + MH_DEBUG_REG22_ARID_q_MASK | \ + MH_DEBUG_REG22_ARLEN_q_1_1_MASK | \ + MH_DEBUG_REG22_WVALID_q_MASK | \ + MH_DEBUG_REG22_WREADY_q_MASK | \ + MH_DEBUG_REG22_WLAST_q_MASK | \ + MH_DEBUG_REG22_WID_q_MASK | \ + MH_DEBUG_REG22_WSTRB_q_MASK | \ + MH_DEBUG_REG22_BVALID_q_MASK | \ + MH_DEBUG_REG22_BREADY_q_MASK | \ + MH_DEBUG_REG22_BID_q_MASK) + +#define MH_DEBUG_REG22(avalid_q, aready_q, aid_q, alen_q_1_0, arvalid_q, arready_q, arid_q, arlen_q_1_1, wvalid_q, wready_q, wlast_q, wid_q, wstrb_q, bvalid_q, bready_q, bid_q) \ + ((avalid_q << MH_DEBUG_REG22_AVALID_q_SHIFT) | \ + (aready_q << MH_DEBUG_REG22_AREADY_q_SHIFT) | \ + (aid_q << MH_DEBUG_REG22_AID_q_SHIFT) | \ + (alen_q_1_0 << MH_DEBUG_REG22_ALEN_q_1_0_SHIFT) | \ + (arvalid_q << MH_DEBUG_REG22_ARVALID_q_SHIFT) | \ + (arready_q << MH_DEBUG_REG22_ARREADY_q_SHIFT) | \ + (arid_q << MH_DEBUG_REG22_ARID_q_SHIFT) | \ + (arlen_q_1_1 << MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT) | \ + (wvalid_q << MH_DEBUG_REG22_WVALID_q_SHIFT) | \ + (wready_q << MH_DEBUG_REG22_WREADY_q_SHIFT) | \ + (wlast_q << MH_DEBUG_REG22_WLAST_q_SHIFT) | \ + (wid_q << MH_DEBUG_REG22_WID_q_SHIFT) | \ + (wstrb_q << MH_DEBUG_REG22_WSTRB_q_SHIFT) | \ + (bvalid_q << MH_DEBUG_REG22_BVALID_q_SHIFT) | \ + (bready_q << MH_DEBUG_REG22_BREADY_q_SHIFT) | \ + (bid_q << MH_DEBUG_REG22_BID_q_SHIFT)) + +#define MH_DEBUG_REG22_GET_AVALID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_AVALID_q_MASK) >> MH_DEBUG_REG22_AVALID_q_SHIFT) +#define MH_DEBUG_REG22_GET_AREADY_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_AREADY_q_MASK) >> MH_DEBUG_REG22_AREADY_q_SHIFT) +#define MH_DEBUG_REG22_GET_AID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_AID_q_MASK) >> MH_DEBUG_REG22_AID_q_SHIFT) +#define MH_DEBUG_REG22_GET_ALEN_q_1_0(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_ALEN_q_1_0_MASK) >> MH_DEBUG_REG22_ALEN_q_1_0_SHIFT) +#define MH_DEBUG_REG22_GET_ARVALID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_ARVALID_q_MASK) >> MH_DEBUG_REG22_ARVALID_q_SHIFT) +#define MH_DEBUG_REG22_GET_ARREADY_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_ARREADY_q_MASK) >> MH_DEBUG_REG22_ARREADY_q_SHIFT) +#define MH_DEBUG_REG22_GET_ARID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_ARID_q_MASK) >> MH_DEBUG_REG22_ARID_q_SHIFT) +#define MH_DEBUG_REG22_GET_ARLEN_q_1_1(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_ARLEN_q_1_1_MASK) >> MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT) +#define MH_DEBUG_REG22_GET_WVALID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_WVALID_q_MASK) >> MH_DEBUG_REG22_WVALID_q_SHIFT) +#define MH_DEBUG_REG22_GET_WREADY_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_WREADY_q_MASK) >> MH_DEBUG_REG22_WREADY_q_SHIFT) +#define MH_DEBUG_REG22_GET_WLAST_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_WLAST_q_MASK) >> MH_DEBUG_REG22_WLAST_q_SHIFT) +#define MH_DEBUG_REG22_GET_WID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_WID_q_MASK) >> MH_DEBUG_REG22_WID_q_SHIFT) +#define MH_DEBUG_REG22_GET_WSTRB_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_WSTRB_q_MASK) >> MH_DEBUG_REG22_WSTRB_q_SHIFT) +#define MH_DEBUG_REG22_GET_BVALID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_BVALID_q_MASK) >> MH_DEBUG_REG22_BVALID_q_SHIFT) +#define MH_DEBUG_REG22_GET_BREADY_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_BREADY_q_MASK) >> MH_DEBUG_REG22_BREADY_q_SHIFT) +#define MH_DEBUG_REG22_GET_BID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_BID_q_MASK) >> MH_DEBUG_REG22_BID_q_SHIFT) + +#define MH_DEBUG_REG22_SET_AVALID_q(mh_debug_reg22_reg, avalid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_AVALID_q_MASK) | (avalid_q << MH_DEBUG_REG22_AVALID_q_SHIFT) +#define MH_DEBUG_REG22_SET_AREADY_q(mh_debug_reg22_reg, aready_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_AREADY_q_MASK) | (aready_q << MH_DEBUG_REG22_AREADY_q_SHIFT) +#define MH_DEBUG_REG22_SET_AID_q(mh_debug_reg22_reg, aid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_AID_q_MASK) | (aid_q << MH_DEBUG_REG22_AID_q_SHIFT) +#define MH_DEBUG_REG22_SET_ALEN_q_1_0(mh_debug_reg22_reg, alen_q_1_0) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ALEN_q_1_0_MASK) | (alen_q_1_0 << MH_DEBUG_REG22_ALEN_q_1_0_SHIFT) +#define MH_DEBUG_REG22_SET_ARVALID_q(mh_debug_reg22_reg, arvalid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARVALID_q_MASK) | (arvalid_q << MH_DEBUG_REG22_ARVALID_q_SHIFT) +#define MH_DEBUG_REG22_SET_ARREADY_q(mh_debug_reg22_reg, arready_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARREADY_q_MASK) | (arready_q << MH_DEBUG_REG22_ARREADY_q_SHIFT) +#define MH_DEBUG_REG22_SET_ARID_q(mh_debug_reg22_reg, arid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARID_q_MASK) | (arid_q << MH_DEBUG_REG22_ARID_q_SHIFT) +#define MH_DEBUG_REG22_SET_ARLEN_q_1_1(mh_debug_reg22_reg, arlen_q_1_1) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARLEN_q_1_1_MASK) | (arlen_q_1_1 << MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT) +#define MH_DEBUG_REG22_SET_WVALID_q(mh_debug_reg22_reg, wvalid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WVALID_q_MASK) | (wvalid_q << MH_DEBUG_REG22_WVALID_q_SHIFT) +#define MH_DEBUG_REG22_SET_WREADY_q(mh_debug_reg22_reg, wready_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WREADY_q_MASK) | (wready_q << MH_DEBUG_REG22_WREADY_q_SHIFT) +#define MH_DEBUG_REG22_SET_WLAST_q(mh_debug_reg22_reg, wlast_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG22_WLAST_q_SHIFT) +#define MH_DEBUG_REG22_SET_WID_q(mh_debug_reg22_reg, wid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WID_q_MASK) | (wid_q << MH_DEBUG_REG22_WID_q_SHIFT) +#define MH_DEBUG_REG22_SET_WSTRB_q(mh_debug_reg22_reg, wstrb_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WSTRB_q_MASK) | (wstrb_q << MH_DEBUG_REG22_WSTRB_q_SHIFT) +#define MH_DEBUG_REG22_SET_BVALID_q(mh_debug_reg22_reg, bvalid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG22_BVALID_q_SHIFT) +#define MH_DEBUG_REG22_SET_BREADY_q(mh_debug_reg22_reg, bready_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG22_BREADY_q_SHIFT) +#define MH_DEBUG_REG22_SET_BID_q(mh_debug_reg22_reg, bid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_BID_q_MASK) | (bid_q << MH_DEBUG_REG22_BID_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg22_t { + unsigned int avalid_q : MH_DEBUG_REG22_AVALID_q_SIZE; + unsigned int aready_q : MH_DEBUG_REG22_AREADY_q_SIZE; + unsigned int aid_q : MH_DEBUG_REG22_AID_q_SIZE; + unsigned int alen_q_1_0 : MH_DEBUG_REG22_ALEN_q_1_0_SIZE; + unsigned int arvalid_q : MH_DEBUG_REG22_ARVALID_q_SIZE; + unsigned int arready_q : MH_DEBUG_REG22_ARREADY_q_SIZE; + unsigned int arid_q : MH_DEBUG_REG22_ARID_q_SIZE; + unsigned int arlen_q_1_1 : MH_DEBUG_REG22_ARLEN_q_1_1_SIZE; + unsigned int wvalid_q : MH_DEBUG_REG22_WVALID_q_SIZE; + unsigned int wready_q : MH_DEBUG_REG22_WREADY_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG22_WLAST_q_SIZE; + unsigned int wid_q : MH_DEBUG_REG22_WID_q_SIZE; + unsigned int wstrb_q : MH_DEBUG_REG22_WSTRB_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG22_BVALID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG22_BREADY_q_SIZE; + unsigned int bid_q : MH_DEBUG_REG22_BID_q_SIZE; + } mh_debug_reg22_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg22_t { + unsigned int bid_q : MH_DEBUG_REG22_BID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG22_BREADY_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG22_BVALID_q_SIZE; + unsigned int wstrb_q : MH_DEBUG_REG22_WSTRB_q_SIZE; + unsigned int wid_q : MH_DEBUG_REG22_WID_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG22_WLAST_q_SIZE; + unsigned int wready_q : MH_DEBUG_REG22_WREADY_q_SIZE; + unsigned int wvalid_q : MH_DEBUG_REG22_WVALID_q_SIZE; + unsigned int arlen_q_1_1 : MH_DEBUG_REG22_ARLEN_q_1_1_SIZE; + unsigned int arid_q : MH_DEBUG_REG22_ARID_q_SIZE; + unsigned int arready_q : MH_DEBUG_REG22_ARREADY_q_SIZE; + unsigned int arvalid_q : MH_DEBUG_REG22_ARVALID_q_SIZE; + unsigned int alen_q_1_0 : MH_DEBUG_REG22_ALEN_q_1_0_SIZE; + unsigned int aid_q : MH_DEBUG_REG22_AID_q_SIZE; + unsigned int aready_q : MH_DEBUG_REG22_AREADY_q_SIZE; + unsigned int avalid_q : MH_DEBUG_REG22_AVALID_q_SIZE; + } mh_debug_reg22_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg22_t f; +} mh_debug_reg22_u; + + +/* + * MH_DEBUG_REG23 struct + */ + +#define MH_DEBUG_REG23_ARC_CTRL_RE_q_SIZE 1 +#define MH_DEBUG_REG23_CTRL_ARC_ID_SIZE 3 +#define MH_DEBUG_REG23_CTRL_ARC_PAD_SIZE 28 + +#define MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT 0 +#define MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT 1 +#define MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT 4 + +#define MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK 0x00000001 +#define MH_DEBUG_REG23_CTRL_ARC_ID_MASK 0x0000000e +#define MH_DEBUG_REG23_CTRL_ARC_PAD_MASK 0xfffffff0 + +#define MH_DEBUG_REG23_MASK \ + (MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK | \ + MH_DEBUG_REG23_CTRL_ARC_ID_MASK | \ + MH_DEBUG_REG23_CTRL_ARC_PAD_MASK) + +#define MH_DEBUG_REG23(arc_ctrl_re_q, ctrl_arc_id, ctrl_arc_pad) \ + ((arc_ctrl_re_q << MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT) | \ + (ctrl_arc_id << MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT) | \ + (ctrl_arc_pad << MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT)) + +#define MH_DEBUG_REG23_GET_ARC_CTRL_RE_q(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG23_GET_CTRL_ARC_ID(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_CTRL_ARC_ID_MASK) >> MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT) +#define MH_DEBUG_REG23_GET_CTRL_ARC_PAD(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_CTRL_ARC_PAD_MASK) >> MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT) + +#define MH_DEBUG_REG23_SET_ARC_CTRL_RE_q(mh_debug_reg23_reg, arc_ctrl_re_q) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK) | (arc_ctrl_re_q << MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG23_SET_CTRL_ARC_ID(mh_debug_reg23_reg, ctrl_arc_id) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_CTRL_ARC_ID_MASK) | (ctrl_arc_id << MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT) +#define MH_DEBUG_REG23_SET_CTRL_ARC_PAD(mh_debug_reg23_reg, ctrl_arc_pad) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_CTRL_ARC_PAD_MASK) | (ctrl_arc_pad << MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg23_t { + unsigned int arc_ctrl_re_q : MH_DEBUG_REG23_ARC_CTRL_RE_q_SIZE; + unsigned int ctrl_arc_id : MH_DEBUG_REG23_CTRL_ARC_ID_SIZE; + unsigned int ctrl_arc_pad : MH_DEBUG_REG23_CTRL_ARC_PAD_SIZE; + } mh_debug_reg23_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg23_t { + unsigned int ctrl_arc_pad : MH_DEBUG_REG23_CTRL_ARC_PAD_SIZE; + unsigned int ctrl_arc_id : MH_DEBUG_REG23_CTRL_ARC_ID_SIZE; + unsigned int arc_ctrl_re_q : MH_DEBUG_REG23_ARC_CTRL_RE_q_SIZE; + } mh_debug_reg23_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg23_t f; +} mh_debug_reg23_u; + + +/* + * MH_DEBUG_REG24 struct + */ + +#define MH_DEBUG_REG24_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG24_REG_A_SIZE 14 +#define MH_DEBUG_REG24_REG_RE_SIZE 1 +#define MH_DEBUG_REG24_REG_WE_SIZE 1 +#define MH_DEBUG_REG24_BLOCK_RS_SIZE 1 + +#define MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG24_REG_A_SHIFT 2 +#define MH_DEBUG_REG24_REG_RE_SHIFT 16 +#define MH_DEBUG_REG24_REG_WE_SHIFT 17 +#define MH_DEBUG_REG24_BLOCK_RS_SHIFT 18 + +#define MH_DEBUG_REG24_ALWAYS_ZERO_MASK 0x00000003 +#define MH_DEBUG_REG24_REG_A_MASK 0x0000fffc +#define MH_DEBUG_REG24_REG_RE_MASK 0x00010000 +#define MH_DEBUG_REG24_REG_WE_MASK 0x00020000 +#define MH_DEBUG_REG24_BLOCK_RS_MASK 0x00040000 + +#define MH_DEBUG_REG24_MASK \ + (MH_DEBUG_REG24_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG24_REG_A_MASK | \ + MH_DEBUG_REG24_REG_RE_MASK | \ + MH_DEBUG_REG24_REG_WE_MASK | \ + MH_DEBUG_REG24_BLOCK_RS_MASK) + +#define MH_DEBUG_REG24(always_zero, reg_a, reg_re, reg_we, block_rs) \ + ((always_zero << MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT) | \ + (reg_a << MH_DEBUG_REG24_REG_A_SHIFT) | \ + (reg_re << MH_DEBUG_REG24_REG_RE_SHIFT) | \ + (reg_we << MH_DEBUG_REG24_REG_WE_SHIFT) | \ + (block_rs << MH_DEBUG_REG24_BLOCK_RS_SHIFT)) + +#define MH_DEBUG_REG24_GET_ALWAYS_ZERO(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG24_GET_REG_A(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_REG_A_MASK) >> MH_DEBUG_REG24_REG_A_SHIFT) +#define MH_DEBUG_REG24_GET_REG_RE(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_REG_RE_MASK) >> MH_DEBUG_REG24_REG_RE_SHIFT) +#define MH_DEBUG_REG24_GET_REG_WE(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_REG_WE_MASK) >> MH_DEBUG_REG24_REG_WE_SHIFT) +#define MH_DEBUG_REG24_GET_BLOCK_RS(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_BLOCK_RS_MASK) >> MH_DEBUG_REG24_BLOCK_RS_SHIFT) + +#define MH_DEBUG_REG24_SET_ALWAYS_ZERO(mh_debug_reg24_reg, always_zero) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG24_SET_REG_A(mh_debug_reg24_reg, reg_a) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_REG_A_MASK) | (reg_a << MH_DEBUG_REG24_REG_A_SHIFT) +#define MH_DEBUG_REG24_SET_REG_RE(mh_debug_reg24_reg, reg_re) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_REG_RE_MASK) | (reg_re << MH_DEBUG_REG24_REG_RE_SHIFT) +#define MH_DEBUG_REG24_SET_REG_WE(mh_debug_reg24_reg, reg_we) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_REG_WE_MASK) | (reg_we << MH_DEBUG_REG24_REG_WE_SHIFT) +#define MH_DEBUG_REG24_SET_BLOCK_RS(mh_debug_reg24_reg, block_rs) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_BLOCK_RS_MASK) | (block_rs << MH_DEBUG_REG24_BLOCK_RS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg24_t { + unsigned int always_zero : MH_DEBUG_REG24_ALWAYS_ZERO_SIZE; + unsigned int reg_a : MH_DEBUG_REG24_REG_A_SIZE; + unsigned int reg_re : MH_DEBUG_REG24_REG_RE_SIZE; + unsigned int reg_we : MH_DEBUG_REG24_REG_WE_SIZE; + unsigned int block_rs : MH_DEBUG_REG24_BLOCK_RS_SIZE; + unsigned int : 13; + } mh_debug_reg24_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg24_t { + unsigned int : 13; + unsigned int block_rs : MH_DEBUG_REG24_BLOCK_RS_SIZE; + unsigned int reg_we : MH_DEBUG_REG24_REG_WE_SIZE; + unsigned int reg_re : MH_DEBUG_REG24_REG_RE_SIZE; + unsigned int reg_a : MH_DEBUG_REG24_REG_A_SIZE; + unsigned int always_zero : MH_DEBUG_REG24_ALWAYS_ZERO_SIZE; + } mh_debug_reg24_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg24_t f; +} mh_debug_reg24_u; + + +/* + * MH_DEBUG_REG25 struct + */ + +#define MH_DEBUG_REG25_REG_WD_SIZE 32 + +#define MH_DEBUG_REG25_REG_WD_SHIFT 0 + +#define MH_DEBUG_REG25_REG_WD_MASK 0xffffffff + +#define MH_DEBUG_REG25_MASK \ + (MH_DEBUG_REG25_REG_WD_MASK) + +#define MH_DEBUG_REG25(reg_wd) \ + ((reg_wd << MH_DEBUG_REG25_REG_WD_SHIFT)) + +#define MH_DEBUG_REG25_GET_REG_WD(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_REG_WD_MASK) >> MH_DEBUG_REG25_REG_WD_SHIFT) + +#define MH_DEBUG_REG25_SET_REG_WD(mh_debug_reg25_reg, reg_wd) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_REG_WD_MASK) | (reg_wd << MH_DEBUG_REG25_REG_WD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg25_t { + unsigned int reg_wd : MH_DEBUG_REG25_REG_WD_SIZE; + } mh_debug_reg25_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg25_t { + unsigned int reg_wd : MH_DEBUG_REG25_REG_WD_SIZE; + } mh_debug_reg25_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg25_t f; +} mh_debug_reg25_u; + + +/* + * MH_DEBUG_REG26 struct + */ + +#define MH_DEBUG_REG26_MH_RBBM_busy_SIZE 1 +#define MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SIZE 1 +#define MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SIZE 1 +#define MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SIZE 1 +#define MH_DEBUG_REG26_GAT_CLK_ENA_SIZE 1 +#define MH_DEBUG_REG26_RBBM_MH_clk_en_override_SIZE 1 +#define MH_DEBUG_REG26_CNT_q_SIZE 6 +#define MH_DEBUG_REG26_TCD_EMPTY_q_SIZE 1 +#define MH_DEBUG_REG26_TC_ROQ_EMPTY_SIZE 1 +#define MH_DEBUG_REG26_MH_BUSY_d_SIZE 1 +#define MH_DEBUG_REG26_ANY_CLNT_BUSY_SIZE 1 +#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE 1 +#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE 1 +#define MH_DEBUG_REG26_CP_SEND_q_SIZE 1 +#define MH_DEBUG_REG26_CP_RTR_q_SIZE 1 +#define MH_DEBUG_REG26_VGT_SEND_q_SIZE 1 +#define MH_DEBUG_REG26_VGT_RTR_q_SIZE 1 +#define MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE 1 +#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE 1 +#define MH_DEBUG_REG26_RB_SEND_q_SIZE 1 +#define MH_DEBUG_REG26_RB_RTR_q_SIZE 1 +#define MH_DEBUG_REG26_PA_SEND_q_SIZE 1 +#define MH_DEBUG_REG26_PA_RTR_q_SIZE 1 +#define MH_DEBUG_REG26_RDC_VALID_SIZE 1 +#define MH_DEBUG_REG26_RDC_RLAST_SIZE 1 +#define MH_DEBUG_REG26_TLBMISS_VALID_SIZE 1 +#define MH_DEBUG_REG26_BRC_VALID_SIZE 1 + +#define MH_DEBUG_REG26_MH_RBBM_busy_SHIFT 0 +#define MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT 1 +#define MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT 2 +#define MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT 3 +#define MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT 4 +#define MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT 5 +#define MH_DEBUG_REG26_CNT_q_SHIFT 6 +#define MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT 12 +#define MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT 13 +#define MH_DEBUG_REG26_MH_BUSY_d_SHIFT 14 +#define MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT 15 +#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT 16 +#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT 17 +#define MH_DEBUG_REG26_CP_SEND_q_SHIFT 18 +#define MH_DEBUG_REG26_CP_RTR_q_SHIFT 19 +#define MH_DEBUG_REG26_VGT_SEND_q_SHIFT 20 +#define MH_DEBUG_REG26_VGT_RTR_q_SHIFT 21 +#define MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT 22 +#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT 23 +#define MH_DEBUG_REG26_RB_SEND_q_SHIFT 24 +#define MH_DEBUG_REG26_RB_RTR_q_SHIFT 25 +#define MH_DEBUG_REG26_PA_SEND_q_SHIFT 26 +#define MH_DEBUG_REG26_PA_RTR_q_SHIFT 27 +#define MH_DEBUG_REG26_RDC_VALID_SHIFT 28 +#define MH_DEBUG_REG26_RDC_RLAST_SHIFT 29 +#define MH_DEBUG_REG26_TLBMISS_VALID_SHIFT 30 +#define MH_DEBUG_REG26_BRC_VALID_SHIFT 31 + +#define MH_DEBUG_REG26_MH_RBBM_busy_MASK 0x00000001 +#define MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK 0x00000002 +#define MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK 0x00000004 +#define MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK 0x00000008 +#define MH_DEBUG_REG26_GAT_CLK_ENA_MASK 0x00000010 +#define MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK 0x00000020 +#define MH_DEBUG_REG26_CNT_q_MASK 0x00000fc0 +#define MH_DEBUG_REG26_TCD_EMPTY_q_MASK 0x00001000 +#define MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK 0x00002000 +#define MH_DEBUG_REG26_MH_BUSY_d_MASK 0x00004000 +#define MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK 0x00008000 +#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00010000 +#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK 0x00020000 +#define MH_DEBUG_REG26_CP_SEND_q_MASK 0x00040000 +#define MH_DEBUG_REG26_CP_RTR_q_MASK 0x00080000 +#define MH_DEBUG_REG26_VGT_SEND_q_MASK 0x00100000 +#define MH_DEBUG_REG26_VGT_RTR_q_MASK 0x00200000 +#define MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK 0x00400000 +#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK 0x00800000 +#define MH_DEBUG_REG26_RB_SEND_q_MASK 0x01000000 +#define MH_DEBUG_REG26_RB_RTR_q_MASK 0x02000000 +#define MH_DEBUG_REG26_PA_SEND_q_MASK 0x04000000 +#define MH_DEBUG_REG26_PA_RTR_q_MASK 0x08000000 +#define MH_DEBUG_REG26_RDC_VALID_MASK 0x10000000 +#define MH_DEBUG_REG26_RDC_RLAST_MASK 0x20000000 +#define MH_DEBUG_REG26_TLBMISS_VALID_MASK 0x40000000 +#define MH_DEBUG_REG26_BRC_VALID_MASK 0x80000000 + +#define MH_DEBUG_REG26_MASK \ + (MH_DEBUG_REG26_MH_RBBM_busy_MASK | \ + MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK | \ + MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK | \ + MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK | \ + MH_DEBUG_REG26_GAT_CLK_ENA_MASK | \ + MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK | \ + MH_DEBUG_REG26_CNT_q_MASK | \ + MH_DEBUG_REG26_TCD_EMPTY_q_MASK | \ + MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK | \ + MH_DEBUG_REG26_MH_BUSY_d_MASK | \ + MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK | \ + MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK | \ + MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK | \ + MH_DEBUG_REG26_CP_SEND_q_MASK | \ + MH_DEBUG_REG26_CP_RTR_q_MASK | \ + MH_DEBUG_REG26_VGT_SEND_q_MASK | \ + MH_DEBUG_REG26_VGT_RTR_q_MASK | \ + MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK | \ + MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK | \ + MH_DEBUG_REG26_RB_SEND_q_MASK | \ + MH_DEBUG_REG26_RB_RTR_q_MASK | \ + MH_DEBUG_REG26_PA_SEND_q_MASK | \ + MH_DEBUG_REG26_PA_RTR_q_MASK | \ + MH_DEBUG_REG26_RDC_VALID_MASK | \ + MH_DEBUG_REG26_RDC_RLAST_MASK | \ + MH_DEBUG_REG26_TLBMISS_VALID_MASK | \ + MH_DEBUG_REG26_BRC_VALID_MASK) + +#define MH_DEBUG_REG26(mh_rbbm_busy, mh_cib_mh_clk_en_int, mh_cib_mmu_clk_en_int, mh_cib_tcroq_clk_en_int, gat_clk_ena, rbbm_mh_clk_en_override, cnt_q, tcd_empty_q, tc_roq_empty, mh_busy_d, any_clnt_busy, mh_mmu_invalidate_invalidate_all, mh_mmu_invalidate_invalidate_tc, cp_send_q, cp_rtr_q, vgt_send_q, vgt_rtr_q, tc_roq_send_q, tc_roq_rtr_dbg_q, rb_send_q, rb_rtr_q, pa_send_q, pa_rtr_q, rdc_valid, rdc_rlast, tlbmiss_valid, brc_valid) \ + ((mh_rbbm_busy << MH_DEBUG_REG26_MH_RBBM_busy_SHIFT) | \ + (mh_cib_mh_clk_en_int << MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT) | \ + (mh_cib_mmu_clk_en_int << MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT) | \ + (mh_cib_tcroq_clk_en_int << MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT) | \ + (gat_clk_ena << MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT) | \ + (rbbm_mh_clk_en_override << MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT) | \ + (cnt_q << MH_DEBUG_REG26_CNT_q_SHIFT) | \ + (tcd_empty_q << MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT) | \ + (tc_roq_empty << MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT) | \ + (mh_busy_d << MH_DEBUG_REG26_MH_BUSY_d_SHIFT) | \ + (any_clnt_busy << MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT) | \ + (mh_mmu_invalidate_invalidate_all << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) | \ + (mh_mmu_invalidate_invalidate_tc << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT) | \ + (cp_send_q << MH_DEBUG_REG26_CP_SEND_q_SHIFT) | \ + (cp_rtr_q << MH_DEBUG_REG26_CP_RTR_q_SHIFT) | \ + (vgt_send_q << MH_DEBUG_REG26_VGT_SEND_q_SHIFT) | \ + (vgt_rtr_q << MH_DEBUG_REG26_VGT_RTR_q_SHIFT) | \ + (tc_roq_send_q << MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT) | \ + (tc_roq_rtr_dbg_q << MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT) | \ + (rb_send_q << MH_DEBUG_REG26_RB_SEND_q_SHIFT) | \ + (rb_rtr_q << MH_DEBUG_REG26_RB_RTR_q_SHIFT) | \ + (pa_send_q << MH_DEBUG_REG26_PA_SEND_q_SHIFT) | \ + (pa_rtr_q << MH_DEBUG_REG26_PA_RTR_q_SHIFT) | \ + (rdc_valid << MH_DEBUG_REG26_RDC_VALID_SHIFT) | \ + (rdc_rlast << MH_DEBUG_REG26_RDC_RLAST_SHIFT) | \ + (tlbmiss_valid << MH_DEBUG_REG26_TLBMISS_VALID_SHIFT) | \ + (brc_valid << MH_DEBUG_REG26_BRC_VALID_SHIFT)) + +#define MH_DEBUG_REG26_GET_MH_RBBM_busy(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_RBBM_busy_MASK) >> MH_DEBUG_REG26_MH_RBBM_busy_SHIFT) +#define MH_DEBUG_REG26_GET_MH_CIB_mh_clk_en_int(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK) >> MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT) +#define MH_DEBUG_REG26_GET_MH_CIB_mmu_clk_en_int(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK) >> MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT) +#define MH_DEBUG_REG26_GET_MH_CIB_tcroq_clk_en_int(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK) >> MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT) +#define MH_DEBUG_REG26_GET_GAT_CLK_ENA(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_GAT_CLK_ENA_MASK) >> MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT) +#define MH_DEBUG_REG26_GET_RBBM_MH_clk_en_override(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK) >> MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT) +#define MH_DEBUG_REG26_GET_CNT_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_CNT_q_MASK) >> MH_DEBUG_REG26_CNT_q_SHIFT) +#define MH_DEBUG_REG26_GET_TCD_EMPTY_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TCD_EMPTY_q_MASK) >> MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT) +#define MH_DEBUG_REG26_GET_TC_ROQ_EMPTY(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG26_GET_MH_BUSY_d(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_BUSY_d_MASK) >> MH_DEBUG_REG26_MH_BUSY_d_SHIFT) +#define MH_DEBUG_REG26_GET_ANY_CLNT_BUSY(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK) >> MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT) +#define MH_DEBUG_REG26_GET_MH_MMU_INVALIDATE_INVALIDATE_ALL(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) >> MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) +#define MH_DEBUG_REG26_GET_MH_MMU_INVALIDATE_INVALIDATE_TC(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) >> MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT) +#define MH_DEBUG_REG26_GET_CP_SEND_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_CP_SEND_q_MASK) >> MH_DEBUG_REG26_CP_SEND_q_SHIFT) +#define MH_DEBUG_REG26_GET_CP_RTR_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_CP_RTR_q_MASK) >> MH_DEBUG_REG26_CP_RTR_q_SHIFT) +#define MH_DEBUG_REG26_GET_VGT_SEND_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_VGT_SEND_q_MASK) >> MH_DEBUG_REG26_VGT_SEND_q_SHIFT) +#define MH_DEBUG_REG26_GET_VGT_RTR_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_VGT_RTR_q_MASK) >> MH_DEBUG_REG26_VGT_RTR_q_SHIFT) +#define MH_DEBUG_REG26_GET_TC_ROQ_SEND_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG26_GET_TC_ROQ_RTR_DBG_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK) >> MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT) +#define MH_DEBUG_REG26_GET_RB_SEND_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_RB_SEND_q_MASK) >> MH_DEBUG_REG26_RB_SEND_q_SHIFT) +#define MH_DEBUG_REG26_GET_RB_RTR_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_RB_RTR_q_MASK) >> MH_DEBUG_REG26_RB_RTR_q_SHIFT) +#define MH_DEBUG_REG26_GET_PA_SEND_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_PA_SEND_q_MASK) >> MH_DEBUG_REG26_PA_SEND_q_SHIFT) +#define MH_DEBUG_REG26_GET_PA_RTR_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_PA_RTR_q_MASK) >> MH_DEBUG_REG26_PA_RTR_q_SHIFT) +#define MH_DEBUG_REG26_GET_RDC_VALID(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_RDC_VALID_MASK) >> MH_DEBUG_REG26_RDC_VALID_SHIFT) +#define MH_DEBUG_REG26_GET_RDC_RLAST(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_RDC_RLAST_MASK) >> MH_DEBUG_REG26_RDC_RLAST_SHIFT) +#define MH_DEBUG_REG26_GET_TLBMISS_VALID(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TLBMISS_VALID_MASK) >> MH_DEBUG_REG26_TLBMISS_VALID_SHIFT) +#define MH_DEBUG_REG26_GET_BRC_VALID(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_BRC_VALID_MASK) >> MH_DEBUG_REG26_BRC_VALID_SHIFT) + +#define MH_DEBUG_REG26_SET_MH_RBBM_busy(mh_debug_reg26_reg, mh_rbbm_busy) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_RBBM_busy_MASK) | (mh_rbbm_busy << MH_DEBUG_REG26_MH_RBBM_busy_SHIFT) +#define MH_DEBUG_REG26_SET_MH_CIB_mh_clk_en_int(mh_debug_reg26_reg, mh_cib_mh_clk_en_int) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK) | (mh_cib_mh_clk_en_int << MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT) +#define MH_DEBUG_REG26_SET_MH_CIB_mmu_clk_en_int(mh_debug_reg26_reg, mh_cib_mmu_clk_en_int) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK) | (mh_cib_mmu_clk_en_int << MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT) +#define MH_DEBUG_REG26_SET_MH_CIB_tcroq_clk_en_int(mh_debug_reg26_reg, mh_cib_tcroq_clk_en_int) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK) | (mh_cib_tcroq_clk_en_int << MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT) +#define MH_DEBUG_REG26_SET_GAT_CLK_ENA(mh_debug_reg26_reg, gat_clk_ena) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_GAT_CLK_ENA_MASK) | (gat_clk_ena << MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT) +#define MH_DEBUG_REG26_SET_RBBM_MH_clk_en_override(mh_debug_reg26_reg, rbbm_mh_clk_en_override) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK) | (rbbm_mh_clk_en_override << MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT) +#define MH_DEBUG_REG26_SET_CNT_q(mh_debug_reg26_reg, cnt_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CNT_q_MASK) | (cnt_q << MH_DEBUG_REG26_CNT_q_SHIFT) +#define MH_DEBUG_REG26_SET_TCD_EMPTY_q(mh_debug_reg26_reg, tcd_empty_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TCD_EMPTY_q_MASK) | (tcd_empty_q << MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT) +#define MH_DEBUG_REG26_SET_TC_ROQ_EMPTY(mh_debug_reg26_reg, tc_roq_empty) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG26_SET_MH_BUSY_d(mh_debug_reg26_reg, mh_busy_d) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_BUSY_d_MASK) | (mh_busy_d << MH_DEBUG_REG26_MH_BUSY_d_SHIFT) +#define MH_DEBUG_REG26_SET_ANY_CLNT_BUSY(mh_debug_reg26_reg, any_clnt_busy) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK) | (any_clnt_busy << MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT) +#define MH_DEBUG_REG26_SET_MH_MMU_INVALIDATE_INVALIDATE_ALL(mh_debug_reg26_reg, mh_mmu_invalidate_invalidate_all) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) | (mh_mmu_invalidate_invalidate_all << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) +#define MH_DEBUG_REG26_SET_MH_MMU_INVALIDATE_INVALIDATE_TC(mh_debug_reg26_reg, mh_mmu_invalidate_invalidate_tc) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) | (mh_mmu_invalidate_invalidate_tc << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT) +#define MH_DEBUG_REG26_SET_CP_SEND_q(mh_debug_reg26_reg, cp_send_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CP_SEND_q_MASK) | (cp_send_q << MH_DEBUG_REG26_CP_SEND_q_SHIFT) +#define MH_DEBUG_REG26_SET_CP_RTR_q(mh_debug_reg26_reg, cp_rtr_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CP_RTR_q_MASK) | (cp_rtr_q << MH_DEBUG_REG26_CP_RTR_q_SHIFT) +#define MH_DEBUG_REG26_SET_VGT_SEND_q(mh_debug_reg26_reg, vgt_send_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_VGT_SEND_q_MASK) | (vgt_send_q << MH_DEBUG_REG26_VGT_SEND_q_SHIFT) +#define MH_DEBUG_REG26_SET_VGT_RTR_q(mh_debug_reg26_reg, vgt_rtr_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_VGT_RTR_q_MASK) | (vgt_rtr_q << MH_DEBUG_REG26_VGT_RTR_q_SHIFT) +#define MH_DEBUG_REG26_SET_TC_ROQ_SEND_q(mh_debug_reg26_reg, tc_roq_send_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG26_SET_TC_ROQ_RTR_DBG_q(mh_debug_reg26_reg, tc_roq_rtr_dbg_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK) | (tc_roq_rtr_dbg_q << MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT) +#define MH_DEBUG_REG26_SET_RB_SEND_q(mh_debug_reg26_reg, rb_send_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RB_SEND_q_MASK) | (rb_send_q << MH_DEBUG_REG26_RB_SEND_q_SHIFT) +#define MH_DEBUG_REG26_SET_RB_RTR_q(mh_debug_reg26_reg, rb_rtr_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RB_RTR_q_MASK) | (rb_rtr_q << MH_DEBUG_REG26_RB_RTR_q_SHIFT) +#define MH_DEBUG_REG26_SET_PA_SEND_q(mh_debug_reg26_reg, pa_send_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_PA_SEND_q_MASK) | (pa_send_q << MH_DEBUG_REG26_PA_SEND_q_SHIFT) +#define MH_DEBUG_REG26_SET_PA_RTR_q(mh_debug_reg26_reg, pa_rtr_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_PA_RTR_q_MASK) | (pa_rtr_q << MH_DEBUG_REG26_PA_RTR_q_SHIFT) +#define MH_DEBUG_REG26_SET_RDC_VALID(mh_debug_reg26_reg, rdc_valid) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RDC_VALID_MASK) | (rdc_valid << MH_DEBUG_REG26_RDC_VALID_SHIFT) +#define MH_DEBUG_REG26_SET_RDC_RLAST(mh_debug_reg26_reg, rdc_rlast) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RDC_RLAST_MASK) | (rdc_rlast << MH_DEBUG_REG26_RDC_RLAST_SHIFT) +#define MH_DEBUG_REG26_SET_TLBMISS_VALID(mh_debug_reg26_reg, tlbmiss_valid) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TLBMISS_VALID_MASK) | (tlbmiss_valid << MH_DEBUG_REG26_TLBMISS_VALID_SHIFT) +#define MH_DEBUG_REG26_SET_BRC_VALID(mh_debug_reg26_reg, brc_valid) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_BRC_VALID_MASK) | (brc_valid << MH_DEBUG_REG26_BRC_VALID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg26_t { + unsigned int mh_rbbm_busy : MH_DEBUG_REG26_MH_RBBM_busy_SIZE; + unsigned int mh_cib_mh_clk_en_int : MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SIZE; + unsigned int mh_cib_mmu_clk_en_int : MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SIZE; + unsigned int mh_cib_tcroq_clk_en_int : MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SIZE; + unsigned int gat_clk_ena : MH_DEBUG_REG26_GAT_CLK_ENA_SIZE; + unsigned int rbbm_mh_clk_en_override : MH_DEBUG_REG26_RBBM_MH_clk_en_override_SIZE; + unsigned int cnt_q : MH_DEBUG_REG26_CNT_q_SIZE; + unsigned int tcd_empty_q : MH_DEBUG_REG26_TCD_EMPTY_q_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG26_TC_ROQ_EMPTY_SIZE; + unsigned int mh_busy_d : MH_DEBUG_REG26_MH_BUSY_d_SIZE; + unsigned int any_clnt_busy : MH_DEBUG_REG26_ANY_CLNT_BUSY_SIZE; + unsigned int mh_mmu_invalidate_invalidate_all : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE; + unsigned int mh_mmu_invalidate_invalidate_tc : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE; + unsigned int cp_send_q : MH_DEBUG_REG26_CP_SEND_q_SIZE; + unsigned int cp_rtr_q : MH_DEBUG_REG26_CP_RTR_q_SIZE; + unsigned int vgt_send_q : MH_DEBUG_REG26_VGT_SEND_q_SIZE; + unsigned int vgt_rtr_q : MH_DEBUG_REG26_VGT_RTR_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE; + unsigned int tc_roq_rtr_dbg_q : MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE; + unsigned int rb_send_q : MH_DEBUG_REG26_RB_SEND_q_SIZE; + unsigned int rb_rtr_q : MH_DEBUG_REG26_RB_RTR_q_SIZE; + unsigned int pa_send_q : MH_DEBUG_REG26_PA_SEND_q_SIZE; + unsigned int pa_rtr_q : MH_DEBUG_REG26_PA_RTR_q_SIZE; + unsigned int rdc_valid : MH_DEBUG_REG26_RDC_VALID_SIZE; + unsigned int rdc_rlast : MH_DEBUG_REG26_RDC_RLAST_SIZE; + unsigned int tlbmiss_valid : MH_DEBUG_REG26_TLBMISS_VALID_SIZE; + unsigned int brc_valid : MH_DEBUG_REG26_BRC_VALID_SIZE; + } mh_debug_reg26_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg26_t { + unsigned int brc_valid : MH_DEBUG_REG26_BRC_VALID_SIZE; + unsigned int tlbmiss_valid : MH_DEBUG_REG26_TLBMISS_VALID_SIZE; + unsigned int rdc_rlast : MH_DEBUG_REG26_RDC_RLAST_SIZE; + unsigned int rdc_valid : MH_DEBUG_REG26_RDC_VALID_SIZE; + unsigned int pa_rtr_q : MH_DEBUG_REG26_PA_RTR_q_SIZE; + unsigned int pa_send_q : MH_DEBUG_REG26_PA_SEND_q_SIZE; + unsigned int rb_rtr_q : MH_DEBUG_REG26_RB_RTR_q_SIZE; + unsigned int rb_send_q : MH_DEBUG_REG26_RB_SEND_q_SIZE; + unsigned int tc_roq_rtr_dbg_q : MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE; + unsigned int vgt_rtr_q : MH_DEBUG_REG26_VGT_RTR_q_SIZE; + unsigned int vgt_send_q : MH_DEBUG_REG26_VGT_SEND_q_SIZE; + unsigned int cp_rtr_q : MH_DEBUG_REG26_CP_RTR_q_SIZE; + unsigned int cp_send_q : MH_DEBUG_REG26_CP_SEND_q_SIZE; + unsigned int mh_mmu_invalidate_invalidate_tc : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE; + unsigned int mh_mmu_invalidate_invalidate_all : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE; + unsigned int any_clnt_busy : MH_DEBUG_REG26_ANY_CLNT_BUSY_SIZE; + unsigned int mh_busy_d : MH_DEBUG_REG26_MH_BUSY_d_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG26_TC_ROQ_EMPTY_SIZE; + unsigned int tcd_empty_q : MH_DEBUG_REG26_TCD_EMPTY_q_SIZE; + unsigned int cnt_q : MH_DEBUG_REG26_CNT_q_SIZE; + unsigned int rbbm_mh_clk_en_override : MH_DEBUG_REG26_RBBM_MH_clk_en_override_SIZE; + unsigned int gat_clk_ena : MH_DEBUG_REG26_GAT_CLK_ENA_SIZE; + unsigned int mh_cib_tcroq_clk_en_int : MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SIZE; + unsigned int mh_cib_mmu_clk_en_int : MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SIZE; + unsigned int mh_cib_mh_clk_en_int : MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SIZE; + unsigned int mh_rbbm_busy : MH_DEBUG_REG26_MH_RBBM_busy_SIZE; + } mh_debug_reg26_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg26_t f; +} mh_debug_reg26_u; + + +/* + * MH_DEBUG_REG27 struct + */ + +#define MH_DEBUG_REG27_EFF2_FP_WINNER_SIZE 3 +#define MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SIZE 3 +#define MH_DEBUG_REG27_EFF1_WINNER_SIZE 3 +#define MH_DEBUG_REG27_ARB_WINNER_SIZE 3 +#define MH_DEBUG_REG27_ARB_WINNER_q_SIZE 3 +#define MH_DEBUG_REG27_EFF1_WIN_SIZE 1 +#define MH_DEBUG_REG27_KILL_EFF1_SIZE 1 +#define MH_DEBUG_REG27_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG27_ARB_RTR_q_SIZE 1 +#define MH_DEBUG_REG27_CP_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG27_VGT_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG27_TC_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SIZE 1 +#define MH_DEBUG_REG27_RB_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG27_PA_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG27_ARB_QUAL_SIZE 1 +#define MH_DEBUG_REG27_CP_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG27_VGT_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG27_TC_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG27_RB_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG27_TCD_NEARFULL_q_SIZE 1 +#define MH_DEBUG_REG27_TCHOLD_IP_q_SIZE 1 + +#define MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT 0 +#define MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT 3 +#define MH_DEBUG_REG27_EFF1_WINNER_SHIFT 6 +#define MH_DEBUG_REG27_ARB_WINNER_SHIFT 9 +#define MH_DEBUG_REG27_ARB_WINNER_q_SHIFT 12 +#define MH_DEBUG_REG27_EFF1_WIN_SHIFT 15 +#define MH_DEBUG_REG27_KILL_EFF1_SHIFT 16 +#define MH_DEBUG_REG27_ARB_HOLD_SHIFT 17 +#define MH_DEBUG_REG27_ARB_RTR_q_SHIFT 18 +#define MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT 19 +#define MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT 20 +#define MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT 21 +#define MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT 22 +#define MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT 23 +#define MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT 24 +#define MH_DEBUG_REG27_ARB_QUAL_SHIFT 25 +#define MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT 26 +#define MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT 27 +#define MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT 28 +#define MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT 29 +#define MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT 30 +#define MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT 31 + +#define MH_DEBUG_REG27_EFF2_FP_WINNER_MASK 0x00000007 +#define MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK 0x00000038 +#define MH_DEBUG_REG27_EFF1_WINNER_MASK 0x000001c0 +#define MH_DEBUG_REG27_ARB_WINNER_MASK 0x00000e00 +#define MH_DEBUG_REG27_ARB_WINNER_q_MASK 0x00007000 +#define MH_DEBUG_REG27_EFF1_WIN_MASK 0x00008000 +#define MH_DEBUG_REG27_KILL_EFF1_MASK 0x00010000 +#define MH_DEBUG_REG27_ARB_HOLD_MASK 0x00020000 +#define MH_DEBUG_REG27_ARB_RTR_q_MASK 0x00040000 +#define MH_DEBUG_REG27_CP_SEND_QUAL_MASK 0x00080000 +#define MH_DEBUG_REG27_VGT_SEND_QUAL_MASK 0x00100000 +#define MH_DEBUG_REG27_TC_SEND_QUAL_MASK 0x00200000 +#define MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK 0x00400000 +#define MH_DEBUG_REG27_RB_SEND_QUAL_MASK 0x00800000 +#define MH_DEBUG_REG27_PA_SEND_QUAL_MASK 0x01000000 +#define MH_DEBUG_REG27_ARB_QUAL_MASK 0x02000000 +#define MH_DEBUG_REG27_CP_EFF1_REQ_MASK 0x04000000 +#define MH_DEBUG_REG27_VGT_EFF1_REQ_MASK 0x08000000 +#define MH_DEBUG_REG27_TC_EFF1_REQ_MASK 0x10000000 +#define MH_DEBUG_REG27_RB_EFF1_REQ_MASK 0x20000000 +#define MH_DEBUG_REG27_TCD_NEARFULL_q_MASK 0x40000000 +#define MH_DEBUG_REG27_TCHOLD_IP_q_MASK 0x80000000 + +#define MH_DEBUG_REG27_MASK \ + (MH_DEBUG_REG27_EFF2_FP_WINNER_MASK | \ + MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK | \ + MH_DEBUG_REG27_EFF1_WINNER_MASK | \ + MH_DEBUG_REG27_ARB_WINNER_MASK | \ + MH_DEBUG_REG27_ARB_WINNER_q_MASK | \ + MH_DEBUG_REG27_EFF1_WIN_MASK | \ + MH_DEBUG_REG27_KILL_EFF1_MASK | \ + MH_DEBUG_REG27_ARB_HOLD_MASK | \ + MH_DEBUG_REG27_ARB_RTR_q_MASK | \ + MH_DEBUG_REG27_CP_SEND_QUAL_MASK | \ + MH_DEBUG_REG27_VGT_SEND_QUAL_MASK | \ + MH_DEBUG_REG27_TC_SEND_QUAL_MASK | \ + MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK | \ + MH_DEBUG_REG27_RB_SEND_QUAL_MASK | \ + MH_DEBUG_REG27_PA_SEND_QUAL_MASK | \ + MH_DEBUG_REG27_ARB_QUAL_MASK | \ + MH_DEBUG_REG27_CP_EFF1_REQ_MASK | \ + MH_DEBUG_REG27_VGT_EFF1_REQ_MASK | \ + MH_DEBUG_REG27_TC_EFF1_REQ_MASK | \ + MH_DEBUG_REG27_RB_EFF1_REQ_MASK | \ + MH_DEBUG_REG27_TCD_NEARFULL_q_MASK | \ + MH_DEBUG_REG27_TCHOLD_IP_q_MASK) + +#define MH_DEBUG_REG27(eff2_fp_winner, eff2_lru_winner_out, eff1_winner, arb_winner, arb_winner_q, eff1_win, kill_eff1, arb_hold, arb_rtr_q, cp_send_qual, vgt_send_qual, tc_send_qual, tc_send_eff1_qual, rb_send_qual, pa_send_qual, arb_qual, cp_eff1_req, vgt_eff1_req, tc_eff1_req, rb_eff1_req, tcd_nearfull_q, tchold_ip_q) \ + ((eff2_fp_winner << MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT) | \ + (eff2_lru_winner_out << MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT) | \ + (eff1_winner << MH_DEBUG_REG27_EFF1_WINNER_SHIFT) | \ + (arb_winner << MH_DEBUG_REG27_ARB_WINNER_SHIFT) | \ + (arb_winner_q << MH_DEBUG_REG27_ARB_WINNER_q_SHIFT) | \ + (eff1_win << MH_DEBUG_REG27_EFF1_WIN_SHIFT) | \ + (kill_eff1 << MH_DEBUG_REG27_KILL_EFF1_SHIFT) | \ + (arb_hold << MH_DEBUG_REG27_ARB_HOLD_SHIFT) | \ + (arb_rtr_q << MH_DEBUG_REG27_ARB_RTR_q_SHIFT) | \ + (cp_send_qual << MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT) | \ + (vgt_send_qual << MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT) | \ + (tc_send_qual << MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT) | \ + (tc_send_eff1_qual << MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT) | \ + (rb_send_qual << MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT) | \ + (pa_send_qual << MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT) | \ + (arb_qual << MH_DEBUG_REG27_ARB_QUAL_SHIFT) | \ + (cp_eff1_req << MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT) | \ + (vgt_eff1_req << MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT) | \ + (tc_eff1_req << MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT) | \ + (rb_eff1_req << MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT) | \ + (tcd_nearfull_q << MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT) | \ + (tchold_ip_q << MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT)) + +#define MH_DEBUG_REG27_GET_EFF2_FP_WINNER(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_EFF2_FP_WINNER_MASK) >> MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT) +#define MH_DEBUG_REG27_GET_EFF2_LRU_WINNER_out(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK) >> MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT) +#define MH_DEBUG_REG27_GET_EFF1_WINNER(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_EFF1_WINNER_MASK) >> MH_DEBUG_REG27_EFF1_WINNER_SHIFT) +#define MH_DEBUG_REG27_GET_ARB_WINNER(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_WINNER_MASK) >> MH_DEBUG_REG27_ARB_WINNER_SHIFT) +#define MH_DEBUG_REG27_GET_ARB_WINNER_q(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_WINNER_q_MASK) >> MH_DEBUG_REG27_ARB_WINNER_q_SHIFT) +#define MH_DEBUG_REG27_GET_EFF1_WIN(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_EFF1_WIN_MASK) >> MH_DEBUG_REG27_EFF1_WIN_SHIFT) +#define MH_DEBUG_REG27_GET_KILL_EFF1(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_KILL_EFF1_MASK) >> MH_DEBUG_REG27_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG27_GET_ARB_HOLD(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_HOLD_MASK) >> MH_DEBUG_REG27_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG27_GET_ARB_RTR_q(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_RTR_q_MASK) >> MH_DEBUG_REG27_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG27_GET_CP_SEND_QUAL(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_GET_VGT_SEND_QUAL(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_VGT_SEND_QUAL_MASK) >> MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_GET_TC_SEND_QUAL(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_TC_SEND_QUAL_MASK) >> MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_GET_TC_SEND_EFF1_QUAL(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK) >> MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG27_GET_RB_SEND_QUAL(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_GET_PA_SEND_QUAL(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_PA_SEND_QUAL_MASK) >> MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_GET_ARB_QUAL(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_QUAL_MASK) >> MH_DEBUG_REG27_ARB_QUAL_SHIFT) +#define MH_DEBUG_REG27_GET_CP_EFF1_REQ(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_CP_EFF1_REQ_MASK) >> MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_GET_VGT_EFF1_REQ(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_VGT_EFF1_REQ_MASK) >> MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_GET_TC_EFF1_REQ(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_TC_EFF1_REQ_MASK) >> MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_GET_RB_EFF1_REQ(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_RB_EFF1_REQ_MASK) >> MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_GET_TCD_NEARFULL_q(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG27_GET_TCHOLD_IP_q(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_TCHOLD_IP_q_MASK) >> MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT) + +#define MH_DEBUG_REG27_SET_EFF2_FP_WINNER(mh_debug_reg27_reg, eff2_fp_winner) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF2_FP_WINNER_MASK) | (eff2_fp_winner << MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT) +#define MH_DEBUG_REG27_SET_EFF2_LRU_WINNER_out(mh_debug_reg27_reg, eff2_lru_winner_out) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK) | (eff2_lru_winner_out << MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT) +#define MH_DEBUG_REG27_SET_EFF1_WINNER(mh_debug_reg27_reg, eff1_winner) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF1_WINNER_MASK) | (eff1_winner << MH_DEBUG_REG27_EFF1_WINNER_SHIFT) +#define MH_DEBUG_REG27_SET_ARB_WINNER(mh_debug_reg27_reg, arb_winner) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG27_ARB_WINNER_SHIFT) +#define MH_DEBUG_REG27_SET_ARB_WINNER_q(mh_debug_reg27_reg, arb_winner_q) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_WINNER_q_MASK) | (arb_winner_q << MH_DEBUG_REG27_ARB_WINNER_q_SHIFT) +#define MH_DEBUG_REG27_SET_EFF1_WIN(mh_debug_reg27_reg, eff1_win) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF1_WIN_MASK) | (eff1_win << MH_DEBUG_REG27_EFF1_WIN_SHIFT) +#define MH_DEBUG_REG27_SET_KILL_EFF1(mh_debug_reg27_reg, kill_eff1) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG27_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG27_SET_ARB_HOLD(mh_debug_reg27_reg, arb_hold) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG27_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG27_SET_ARB_RTR_q(mh_debug_reg27_reg, arb_rtr_q) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG27_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG27_SET_CP_SEND_QUAL(mh_debug_reg27_reg, cp_send_qual) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_SET_VGT_SEND_QUAL(mh_debug_reg27_reg, vgt_send_qual) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_VGT_SEND_QUAL_MASK) | (vgt_send_qual << MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_SET_TC_SEND_QUAL(mh_debug_reg27_reg, tc_send_qual) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TC_SEND_QUAL_MASK) | (tc_send_qual << MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_SET_TC_SEND_EFF1_QUAL(mh_debug_reg27_reg, tc_send_eff1_qual) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK) | (tc_send_eff1_qual << MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG27_SET_RB_SEND_QUAL(mh_debug_reg27_reg, rb_send_qual) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_SET_PA_SEND_QUAL(mh_debug_reg27_reg, pa_send_qual) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_PA_SEND_QUAL_MASK) | (pa_send_qual << MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_SET_ARB_QUAL(mh_debug_reg27_reg, arb_qual) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_QUAL_MASK) | (arb_qual << MH_DEBUG_REG27_ARB_QUAL_SHIFT) +#define MH_DEBUG_REG27_SET_CP_EFF1_REQ(mh_debug_reg27_reg, cp_eff1_req) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_CP_EFF1_REQ_MASK) | (cp_eff1_req << MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_SET_VGT_EFF1_REQ(mh_debug_reg27_reg, vgt_eff1_req) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_VGT_EFF1_REQ_MASK) | (vgt_eff1_req << MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_SET_TC_EFF1_REQ(mh_debug_reg27_reg, tc_eff1_req) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TC_EFF1_REQ_MASK) | (tc_eff1_req << MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_SET_RB_EFF1_REQ(mh_debug_reg27_reg, rb_eff1_req) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_RB_EFF1_REQ_MASK) | (rb_eff1_req << MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_SET_TCD_NEARFULL_q(mh_debug_reg27_reg, tcd_nearfull_q) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG27_SET_TCHOLD_IP_q(mh_debug_reg27_reg, tchold_ip_q) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TCHOLD_IP_q_MASK) | (tchold_ip_q << MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg27_t { + unsigned int eff2_fp_winner : MH_DEBUG_REG27_EFF2_FP_WINNER_SIZE; + unsigned int eff2_lru_winner_out : MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SIZE; + unsigned int eff1_winner : MH_DEBUG_REG27_EFF1_WINNER_SIZE; + unsigned int arb_winner : MH_DEBUG_REG27_ARB_WINNER_SIZE; + unsigned int arb_winner_q : MH_DEBUG_REG27_ARB_WINNER_q_SIZE; + unsigned int eff1_win : MH_DEBUG_REG27_EFF1_WIN_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG27_KILL_EFF1_SIZE; + unsigned int arb_hold : MH_DEBUG_REG27_ARB_HOLD_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG27_ARB_RTR_q_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG27_CP_SEND_QUAL_SIZE; + unsigned int vgt_send_qual : MH_DEBUG_REG27_VGT_SEND_QUAL_SIZE; + unsigned int tc_send_qual : MH_DEBUG_REG27_TC_SEND_QUAL_SIZE; + unsigned int tc_send_eff1_qual : MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG27_RB_SEND_QUAL_SIZE; + unsigned int pa_send_qual : MH_DEBUG_REG27_PA_SEND_QUAL_SIZE; + unsigned int arb_qual : MH_DEBUG_REG27_ARB_QUAL_SIZE; + unsigned int cp_eff1_req : MH_DEBUG_REG27_CP_EFF1_REQ_SIZE; + unsigned int vgt_eff1_req : MH_DEBUG_REG27_VGT_EFF1_REQ_SIZE; + unsigned int tc_eff1_req : MH_DEBUG_REG27_TC_EFF1_REQ_SIZE; + unsigned int rb_eff1_req : MH_DEBUG_REG27_RB_EFF1_REQ_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG27_TCD_NEARFULL_q_SIZE; + unsigned int tchold_ip_q : MH_DEBUG_REG27_TCHOLD_IP_q_SIZE; + } mh_debug_reg27_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg27_t { + unsigned int tchold_ip_q : MH_DEBUG_REG27_TCHOLD_IP_q_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG27_TCD_NEARFULL_q_SIZE; + unsigned int rb_eff1_req : MH_DEBUG_REG27_RB_EFF1_REQ_SIZE; + unsigned int tc_eff1_req : MH_DEBUG_REG27_TC_EFF1_REQ_SIZE; + unsigned int vgt_eff1_req : MH_DEBUG_REG27_VGT_EFF1_REQ_SIZE; + unsigned int cp_eff1_req : MH_DEBUG_REG27_CP_EFF1_REQ_SIZE; + unsigned int arb_qual : MH_DEBUG_REG27_ARB_QUAL_SIZE; + unsigned int pa_send_qual : MH_DEBUG_REG27_PA_SEND_QUAL_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG27_RB_SEND_QUAL_SIZE; + unsigned int tc_send_eff1_qual : MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SIZE; + unsigned int tc_send_qual : MH_DEBUG_REG27_TC_SEND_QUAL_SIZE; + unsigned int vgt_send_qual : MH_DEBUG_REG27_VGT_SEND_QUAL_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG27_CP_SEND_QUAL_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG27_ARB_RTR_q_SIZE; + unsigned int arb_hold : MH_DEBUG_REG27_ARB_HOLD_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG27_KILL_EFF1_SIZE; + unsigned int eff1_win : MH_DEBUG_REG27_EFF1_WIN_SIZE; + unsigned int arb_winner_q : MH_DEBUG_REG27_ARB_WINNER_q_SIZE; + unsigned int arb_winner : MH_DEBUG_REG27_ARB_WINNER_SIZE; + unsigned int eff1_winner : MH_DEBUG_REG27_EFF1_WINNER_SIZE; + unsigned int eff2_lru_winner_out : MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SIZE; + unsigned int eff2_fp_winner : MH_DEBUG_REG27_EFF2_FP_WINNER_SIZE; + } mh_debug_reg27_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg27_t f; +} mh_debug_reg27_u; + + +/* + * MH_DEBUG_REG28 struct + */ + +#define MH_DEBUG_REG28_EFF1_WINNER_SIZE 3 +#define MH_DEBUG_REG28_ARB_WINNER_SIZE 3 +#define MH_DEBUG_REG28_CP_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG28_VGT_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG28_TC_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SIZE 1 +#define MH_DEBUG_REG28_RB_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG28_ARB_QUAL_SIZE 1 +#define MH_DEBUG_REG28_CP_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG28_VGT_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG28_TC_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG28_RB_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG28_EFF1_WIN_SIZE 1 +#define MH_DEBUG_REG28_KILL_EFF1_SIZE 1 +#define MH_DEBUG_REG28_TCD_NEARFULL_q_SIZE 1 +#define MH_DEBUG_REG28_TC_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG28_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG28_ARB_RTR_q_SIZE 1 +#define MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SIZE 10 + +#define MH_DEBUG_REG28_EFF1_WINNER_SHIFT 0 +#define MH_DEBUG_REG28_ARB_WINNER_SHIFT 3 +#define MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT 6 +#define MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT 7 +#define MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT 8 +#define MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT 9 +#define MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT 10 +#define MH_DEBUG_REG28_ARB_QUAL_SHIFT 11 +#define MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT 12 +#define MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT 13 +#define MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT 14 +#define MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT 15 +#define MH_DEBUG_REG28_EFF1_WIN_SHIFT 16 +#define MH_DEBUG_REG28_KILL_EFF1_SHIFT 17 +#define MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT 18 +#define MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT 19 +#define MH_DEBUG_REG28_ARB_HOLD_SHIFT 20 +#define MH_DEBUG_REG28_ARB_RTR_q_SHIFT 21 +#define MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT 22 + +#define MH_DEBUG_REG28_EFF1_WINNER_MASK 0x00000007 +#define MH_DEBUG_REG28_ARB_WINNER_MASK 0x00000038 +#define MH_DEBUG_REG28_CP_SEND_QUAL_MASK 0x00000040 +#define MH_DEBUG_REG28_VGT_SEND_QUAL_MASK 0x00000080 +#define MH_DEBUG_REG28_TC_SEND_QUAL_MASK 0x00000100 +#define MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK 0x00000200 +#define MH_DEBUG_REG28_RB_SEND_QUAL_MASK 0x00000400 +#define MH_DEBUG_REG28_ARB_QUAL_MASK 0x00000800 +#define MH_DEBUG_REG28_CP_EFF1_REQ_MASK 0x00001000 +#define MH_DEBUG_REG28_VGT_EFF1_REQ_MASK 0x00002000 +#define MH_DEBUG_REG28_TC_EFF1_REQ_MASK 0x00004000 +#define MH_DEBUG_REG28_RB_EFF1_REQ_MASK 0x00008000 +#define MH_DEBUG_REG28_EFF1_WIN_MASK 0x00010000 +#define MH_DEBUG_REG28_KILL_EFF1_MASK 0x00020000 +#define MH_DEBUG_REG28_TCD_NEARFULL_q_MASK 0x00040000 +#define MH_DEBUG_REG28_TC_ARB_HOLD_MASK 0x00080000 +#define MH_DEBUG_REG28_ARB_HOLD_MASK 0x00100000 +#define MH_DEBUG_REG28_ARB_RTR_q_MASK 0x00200000 +#define MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK 0xffc00000 + +#define MH_DEBUG_REG28_MASK \ + (MH_DEBUG_REG28_EFF1_WINNER_MASK | \ + MH_DEBUG_REG28_ARB_WINNER_MASK | \ + MH_DEBUG_REG28_CP_SEND_QUAL_MASK | \ + MH_DEBUG_REG28_VGT_SEND_QUAL_MASK | \ + MH_DEBUG_REG28_TC_SEND_QUAL_MASK | \ + MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK | \ + MH_DEBUG_REG28_RB_SEND_QUAL_MASK | \ + MH_DEBUG_REG28_ARB_QUAL_MASK | \ + MH_DEBUG_REG28_CP_EFF1_REQ_MASK | \ + MH_DEBUG_REG28_VGT_EFF1_REQ_MASK | \ + MH_DEBUG_REG28_TC_EFF1_REQ_MASK | \ + MH_DEBUG_REG28_RB_EFF1_REQ_MASK | \ + MH_DEBUG_REG28_EFF1_WIN_MASK | \ + MH_DEBUG_REG28_KILL_EFF1_MASK | \ + MH_DEBUG_REG28_TCD_NEARFULL_q_MASK | \ + MH_DEBUG_REG28_TC_ARB_HOLD_MASK | \ + MH_DEBUG_REG28_ARB_HOLD_MASK | \ + MH_DEBUG_REG28_ARB_RTR_q_MASK | \ + MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK) + +#define MH_DEBUG_REG28(eff1_winner, arb_winner, cp_send_qual, vgt_send_qual, tc_send_qual, tc_send_eff1_qual, rb_send_qual, arb_qual, cp_eff1_req, vgt_eff1_req, tc_eff1_req, rb_eff1_req, eff1_win, kill_eff1, tcd_nearfull_q, tc_arb_hold, arb_hold, arb_rtr_q, same_page_limit_count_q) \ + ((eff1_winner << MH_DEBUG_REG28_EFF1_WINNER_SHIFT) | \ + (arb_winner << MH_DEBUG_REG28_ARB_WINNER_SHIFT) | \ + (cp_send_qual << MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT) | \ + (vgt_send_qual << MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT) | \ + (tc_send_qual << MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT) | \ + (tc_send_eff1_qual << MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT) | \ + (rb_send_qual << MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT) | \ + (arb_qual << MH_DEBUG_REG28_ARB_QUAL_SHIFT) | \ + (cp_eff1_req << MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT) | \ + (vgt_eff1_req << MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT) | \ + (tc_eff1_req << MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT) | \ + (rb_eff1_req << MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT) | \ + (eff1_win << MH_DEBUG_REG28_EFF1_WIN_SHIFT) | \ + (kill_eff1 << MH_DEBUG_REG28_KILL_EFF1_SHIFT) | \ + (tcd_nearfull_q << MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT) | \ + (tc_arb_hold << MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT) | \ + (arb_hold << MH_DEBUG_REG28_ARB_HOLD_SHIFT) | \ + (arb_rtr_q << MH_DEBUG_REG28_ARB_RTR_q_SHIFT) | \ + (same_page_limit_count_q << MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT)) + +#define MH_DEBUG_REG28_GET_EFF1_WINNER(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_EFF1_WINNER_MASK) >> MH_DEBUG_REG28_EFF1_WINNER_SHIFT) +#define MH_DEBUG_REG28_GET_ARB_WINNER(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_WINNER_MASK) >> MH_DEBUG_REG28_ARB_WINNER_SHIFT) +#define MH_DEBUG_REG28_GET_CP_SEND_QUAL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_GET_VGT_SEND_QUAL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_VGT_SEND_QUAL_MASK) >> MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_GET_TC_SEND_QUAL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TC_SEND_QUAL_MASK) >> MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_GET_TC_SEND_EFF1_QUAL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK) >> MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG28_GET_RB_SEND_QUAL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_GET_ARB_QUAL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_QUAL_MASK) >> MH_DEBUG_REG28_ARB_QUAL_SHIFT) +#define MH_DEBUG_REG28_GET_CP_EFF1_REQ(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_CP_EFF1_REQ_MASK) >> MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_GET_VGT_EFF1_REQ(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_VGT_EFF1_REQ_MASK) >> MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_GET_TC_EFF1_REQ(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TC_EFF1_REQ_MASK) >> MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_GET_RB_EFF1_REQ(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_RB_EFF1_REQ_MASK) >> MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_GET_EFF1_WIN(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_EFF1_WIN_MASK) >> MH_DEBUG_REG28_EFF1_WIN_SHIFT) +#define MH_DEBUG_REG28_GET_KILL_EFF1(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_KILL_EFF1_MASK) >> MH_DEBUG_REG28_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG28_GET_TCD_NEARFULL_q(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG28_GET_TC_ARB_HOLD(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TC_ARB_HOLD_MASK) >> MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG28_GET_ARB_HOLD(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_HOLD_MASK) >> MH_DEBUG_REG28_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG28_GET_ARB_RTR_q(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_RTR_q_MASK) >> MH_DEBUG_REG28_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG28_GET_SAME_PAGE_LIMIT_COUNT_q(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK) >> MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT) + +#define MH_DEBUG_REG28_SET_EFF1_WINNER(mh_debug_reg28_reg, eff1_winner) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_EFF1_WINNER_MASK) | (eff1_winner << MH_DEBUG_REG28_EFF1_WINNER_SHIFT) +#define MH_DEBUG_REG28_SET_ARB_WINNER(mh_debug_reg28_reg, arb_winner) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG28_ARB_WINNER_SHIFT) +#define MH_DEBUG_REG28_SET_CP_SEND_QUAL(mh_debug_reg28_reg, cp_send_qual) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_SET_VGT_SEND_QUAL(mh_debug_reg28_reg, vgt_send_qual) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_VGT_SEND_QUAL_MASK) | (vgt_send_qual << MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_SET_TC_SEND_QUAL(mh_debug_reg28_reg, tc_send_qual) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_SEND_QUAL_MASK) | (tc_send_qual << MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_SET_TC_SEND_EFF1_QUAL(mh_debug_reg28_reg, tc_send_eff1_qual) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK) | (tc_send_eff1_qual << MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG28_SET_RB_SEND_QUAL(mh_debug_reg28_reg, rb_send_qual) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_SET_ARB_QUAL(mh_debug_reg28_reg, arb_qual) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_QUAL_MASK) | (arb_qual << MH_DEBUG_REG28_ARB_QUAL_SHIFT) +#define MH_DEBUG_REG28_SET_CP_EFF1_REQ(mh_debug_reg28_reg, cp_eff1_req) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_CP_EFF1_REQ_MASK) | (cp_eff1_req << MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_SET_VGT_EFF1_REQ(mh_debug_reg28_reg, vgt_eff1_req) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_VGT_EFF1_REQ_MASK) | (vgt_eff1_req << MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_SET_TC_EFF1_REQ(mh_debug_reg28_reg, tc_eff1_req) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_EFF1_REQ_MASK) | (tc_eff1_req << MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_SET_RB_EFF1_REQ(mh_debug_reg28_reg, rb_eff1_req) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_RB_EFF1_REQ_MASK) | (rb_eff1_req << MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_SET_EFF1_WIN(mh_debug_reg28_reg, eff1_win) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_EFF1_WIN_MASK) | (eff1_win << MH_DEBUG_REG28_EFF1_WIN_SHIFT) +#define MH_DEBUG_REG28_SET_KILL_EFF1(mh_debug_reg28_reg, kill_eff1) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG28_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG28_SET_TCD_NEARFULL_q(mh_debug_reg28_reg, tcd_nearfull_q) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG28_SET_TC_ARB_HOLD(mh_debug_reg28_reg, tc_arb_hold) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_ARB_HOLD_MASK) | (tc_arb_hold << MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG28_SET_ARB_HOLD(mh_debug_reg28_reg, arb_hold) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG28_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG28_SET_ARB_RTR_q(mh_debug_reg28_reg, arb_rtr_q) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG28_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG28_SET_SAME_PAGE_LIMIT_COUNT_q(mh_debug_reg28_reg, same_page_limit_count_q) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK) | (same_page_limit_count_q << MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg28_t { + unsigned int eff1_winner : MH_DEBUG_REG28_EFF1_WINNER_SIZE; + unsigned int arb_winner : MH_DEBUG_REG28_ARB_WINNER_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG28_CP_SEND_QUAL_SIZE; + unsigned int vgt_send_qual : MH_DEBUG_REG28_VGT_SEND_QUAL_SIZE; + unsigned int tc_send_qual : MH_DEBUG_REG28_TC_SEND_QUAL_SIZE; + unsigned int tc_send_eff1_qual : MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG28_RB_SEND_QUAL_SIZE; + unsigned int arb_qual : MH_DEBUG_REG28_ARB_QUAL_SIZE; + unsigned int cp_eff1_req : MH_DEBUG_REG28_CP_EFF1_REQ_SIZE; + unsigned int vgt_eff1_req : MH_DEBUG_REG28_VGT_EFF1_REQ_SIZE; + unsigned int tc_eff1_req : MH_DEBUG_REG28_TC_EFF1_REQ_SIZE; + unsigned int rb_eff1_req : MH_DEBUG_REG28_RB_EFF1_REQ_SIZE; + unsigned int eff1_win : MH_DEBUG_REG28_EFF1_WIN_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG28_KILL_EFF1_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG28_TCD_NEARFULL_q_SIZE; + unsigned int tc_arb_hold : MH_DEBUG_REG28_TC_ARB_HOLD_SIZE; + unsigned int arb_hold : MH_DEBUG_REG28_ARB_HOLD_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG28_ARB_RTR_q_SIZE; + unsigned int same_page_limit_count_q : MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SIZE; + } mh_debug_reg28_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg28_t { + unsigned int same_page_limit_count_q : MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG28_ARB_RTR_q_SIZE; + unsigned int arb_hold : MH_DEBUG_REG28_ARB_HOLD_SIZE; + unsigned int tc_arb_hold : MH_DEBUG_REG28_TC_ARB_HOLD_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG28_TCD_NEARFULL_q_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG28_KILL_EFF1_SIZE; + unsigned int eff1_win : MH_DEBUG_REG28_EFF1_WIN_SIZE; + unsigned int rb_eff1_req : MH_DEBUG_REG28_RB_EFF1_REQ_SIZE; + unsigned int tc_eff1_req : MH_DEBUG_REG28_TC_EFF1_REQ_SIZE; + unsigned int vgt_eff1_req : MH_DEBUG_REG28_VGT_EFF1_REQ_SIZE; + unsigned int cp_eff1_req : MH_DEBUG_REG28_CP_EFF1_REQ_SIZE; + unsigned int arb_qual : MH_DEBUG_REG28_ARB_QUAL_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG28_RB_SEND_QUAL_SIZE; + unsigned int tc_send_eff1_qual : MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SIZE; + unsigned int tc_send_qual : MH_DEBUG_REG28_TC_SEND_QUAL_SIZE; + unsigned int vgt_send_qual : MH_DEBUG_REG28_VGT_SEND_QUAL_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG28_CP_SEND_QUAL_SIZE; + unsigned int arb_winner : MH_DEBUG_REG28_ARB_WINNER_SIZE; + unsigned int eff1_winner : MH_DEBUG_REG28_EFF1_WINNER_SIZE; + } mh_debug_reg28_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg28_t f; +} mh_debug_reg28_u; + + +/* + * MH_DEBUG_REG29 struct + */ + +#define MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SIZE 3 +#define MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SIZE 3 +#define MH_DEBUG_REG29_LEAST_RECENT_d_SIZE 3 +#define MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SIZE 1 +#define MH_DEBUG_REG29_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG29_ARB_RTR_q_SIZE 1 +#define MH_DEBUG_REG29_CLNT_REQ_SIZE 5 +#define MH_DEBUG_REG29_RECENT_d_0_SIZE 3 +#define MH_DEBUG_REG29_RECENT_d_1_SIZE 3 +#define MH_DEBUG_REG29_RECENT_d_2_SIZE 3 +#define MH_DEBUG_REG29_RECENT_d_3_SIZE 3 +#define MH_DEBUG_REG29_RECENT_d_4_SIZE 3 + +#define MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT 0 +#define MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT 3 +#define MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT 6 +#define MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT 9 +#define MH_DEBUG_REG29_ARB_HOLD_SHIFT 10 +#define MH_DEBUG_REG29_ARB_RTR_q_SHIFT 11 +#define MH_DEBUG_REG29_CLNT_REQ_SHIFT 12 +#define MH_DEBUG_REG29_RECENT_d_0_SHIFT 17 +#define MH_DEBUG_REG29_RECENT_d_1_SHIFT 20 +#define MH_DEBUG_REG29_RECENT_d_2_SHIFT 23 +#define MH_DEBUG_REG29_RECENT_d_3_SHIFT 26 +#define MH_DEBUG_REG29_RECENT_d_4_SHIFT 29 + +#define MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK 0x00000007 +#define MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK 0x00000038 +#define MH_DEBUG_REG29_LEAST_RECENT_d_MASK 0x000001c0 +#define MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK 0x00000200 +#define MH_DEBUG_REG29_ARB_HOLD_MASK 0x00000400 +#define MH_DEBUG_REG29_ARB_RTR_q_MASK 0x00000800 +#define MH_DEBUG_REG29_CLNT_REQ_MASK 0x0001f000 +#define MH_DEBUG_REG29_RECENT_d_0_MASK 0x000e0000 +#define MH_DEBUG_REG29_RECENT_d_1_MASK 0x00700000 +#define MH_DEBUG_REG29_RECENT_d_2_MASK 0x03800000 +#define MH_DEBUG_REG29_RECENT_d_3_MASK 0x1c000000 +#define MH_DEBUG_REG29_RECENT_d_4_MASK 0xe0000000 + +#define MH_DEBUG_REG29_MASK \ + (MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK | \ + MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK | \ + MH_DEBUG_REG29_LEAST_RECENT_d_MASK | \ + MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK | \ + MH_DEBUG_REG29_ARB_HOLD_MASK | \ + MH_DEBUG_REG29_ARB_RTR_q_MASK | \ + MH_DEBUG_REG29_CLNT_REQ_MASK | \ + MH_DEBUG_REG29_RECENT_d_0_MASK | \ + MH_DEBUG_REG29_RECENT_d_1_MASK | \ + MH_DEBUG_REG29_RECENT_d_2_MASK | \ + MH_DEBUG_REG29_RECENT_d_3_MASK | \ + MH_DEBUG_REG29_RECENT_d_4_MASK) + +#define MH_DEBUG_REG29(eff2_lru_winner_out, least_recent_index_d, least_recent_d, update_recent_stack_d, arb_hold, arb_rtr_q, clnt_req, recent_d_0, recent_d_1, recent_d_2, recent_d_3, recent_d_4) \ + ((eff2_lru_winner_out << MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT) | \ + (least_recent_index_d << MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT) | \ + (least_recent_d << MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT) | \ + (update_recent_stack_d << MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT) | \ + (arb_hold << MH_DEBUG_REG29_ARB_HOLD_SHIFT) | \ + (arb_rtr_q << MH_DEBUG_REG29_ARB_RTR_q_SHIFT) | \ + (clnt_req << MH_DEBUG_REG29_CLNT_REQ_SHIFT) | \ + (recent_d_0 << MH_DEBUG_REG29_RECENT_d_0_SHIFT) | \ + (recent_d_1 << MH_DEBUG_REG29_RECENT_d_1_SHIFT) | \ + (recent_d_2 << MH_DEBUG_REG29_RECENT_d_2_SHIFT) | \ + (recent_d_3 << MH_DEBUG_REG29_RECENT_d_3_SHIFT) | \ + (recent_d_4 << MH_DEBUG_REG29_RECENT_d_4_SHIFT)) + +#define MH_DEBUG_REG29_GET_EFF2_LRU_WINNER_out(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK) >> MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT) +#define MH_DEBUG_REG29_GET_LEAST_RECENT_INDEX_d(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK) >> MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT) +#define MH_DEBUG_REG29_GET_LEAST_RECENT_d(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_LEAST_RECENT_d_MASK) >> MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT) +#define MH_DEBUG_REG29_GET_UPDATE_RECENT_STACK_d(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK) >> MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT) +#define MH_DEBUG_REG29_GET_ARB_HOLD(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_ARB_HOLD_MASK) >> MH_DEBUG_REG29_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG29_GET_ARB_RTR_q(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_ARB_RTR_q_MASK) >> MH_DEBUG_REG29_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG29_GET_CLNT_REQ(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_CLNT_REQ_MASK) >> MH_DEBUG_REG29_CLNT_REQ_SHIFT) +#define MH_DEBUG_REG29_GET_RECENT_d_0(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_0_MASK) >> MH_DEBUG_REG29_RECENT_d_0_SHIFT) +#define MH_DEBUG_REG29_GET_RECENT_d_1(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_1_MASK) >> MH_DEBUG_REG29_RECENT_d_1_SHIFT) +#define MH_DEBUG_REG29_GET_RECENT_d_2(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_2_MASK) >> MH_DEBUG_REG29_RECENT_d_2_SHIFT) +#define MH_DEBUG_REG29_GET_RECENT_d_3(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_3_MASK) >> MH_DEBUG_REG29_RECENT_d_3_SHIFT) +#define MH_DEBUG_REG29_GET_RECENT_d_4(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_4_MASK) >> MH_DEBUG_REG29_RECENT_d_4_SHIFT) + +#define MH_DEBUG_REG29_SET_EFF2_LRU_WINNER_out(mh_debug_reg29_reg, eff2_lru_winner_out) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK) | (eff2_lru_winner_out << MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT) +#define MH_DEBUG_REG29_SET_LEAST_RECENT_INDEX_d(mh_debug_reg29_reg, least_recent_index_d) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK) | (least_recent_index_d << MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT) +#define MH_DEBUG_REG29_SET_LEAST_RECENT_d(mh_debug_reg29_reg, least_recent_d) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_LEAST_RECENT_d_MASK) | (least_recent_d << MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT) +#define MH_DEBUG_REG29_SET_UPDATE_RECENT_STACK_d(mh_debug_reg29_reg, update_recent_stack_d) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK) | (update_recent_stack_d << MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT) +#define MH_DEBUG_REG29_SET_ARB_HOLD(mh_debug_reg29_reg, arb_hold) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG29_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG29_SET_ARB_RTR_q(mh_debug_reg29_reg, arb_rtr_q) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG29_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG29_SET_CLNT_REQ(mh_debug_reg29_reg, clnt_req) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_CLNT_REQ_MASK) | (clnt_req << MH_DEBUG_REG29_CLNT_REQ_SHIFT) +#define MH_DEBUG_REG29_SET_RECENT_d_0(mh_debug_reg29_reg, recent_d_0) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_0_MASK) | (recent_d_0 << MH_DEBUG_REG29_RECENT_d_0_SHIFT) +#define MH_DEBUG_REG29_SET_RECENT_d_1(mh_debug_reg29_reg, recent_d_1) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_1_MASK) | (recent_d_1 << MH_DEBUG_REG29_RECENT_d_1_SHIFT) +#define MH_DEBUG_REG29_SET_RECENT_d_2(mh_debug_reg29_reg, recent_d_2) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_2_MASK) | (recent_d_2 << MH_DEBUG_REG29_RECENT_d_2_SHIFT) +#define MH_DEBUG_REG29_SET_RECENT_d_3(mh_debug_reg29_reg, recent_d_3) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_3_MASK) | (recent_d_3 << MH_DEBUG_REG29_RECENT_d_3_SHIFT) +#define MH_DEBUG_REG29_SET_RECENT_d_4(mh_debug_reg29_reg, recent_d_4) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_4_MASK) | (recent_d_4 << MH_DEBUG_REG29_RECENT_d_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg29_t { + unsigned int eff2_lru_winner_out : MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SIZE; + unsigned int least_recent_index_d : MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SIZE; + unsigned int least_recent_d : MH_DEBUG_REG29_LEAST_RECENT_d_SIZE; + unsigned int update_recent_stack_d : MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SIZE; + unsigned int arb_hold : MH_DEBUG_REG29_ARB_HOLD_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG29_ARB_RTR_q_SIZE; + unsigned int clnt_req : MH_DEBUG_REG29_CLNT_REQ_SIZE; + unsigned int recent_d_0 : MH_DEBUG_REG29_RECENT_d_0_SIZE; + unsigned int recent_d_1 : MH_DEBUG_REG29_RECENT_d_1_SIZE; + unsigned int recent_d_2 : MH_DEBUG_REG29_RECENT_d_2_SIZE; + unsigned int recent_d_3 : MH_DEBUG_REG29_RECENT_d_3_SIZE; + unsigned int recent_d_4 : MH_DEBUG_REG29_RECENT_d_4_SIZE; + } mh_debug_reg29_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg29_t { + unsigned int recent_d_4 : MH_DEBUG_REG29_RECENT_d_4_SIZE; + unsigned int recent_d_3 : MH_DEBUG_REG29_RECENT_d_3_SIZE; + unsigned int recent_d_2 : MH_DEBUG_REG29_RECENT_d_2_SIZE; + unsigned int recent_d_1 : MH_DEBUG_REG29_RECENT_d_1_SIZE; + unsigned int recent_d_0 : MH_DEBUG_REG29_RECENT_d_0_SIZE; + unsigned int clnt_req : MH_DEBUG_REG29_CLNT_REQ_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG29_ARB_RTR_q_SIZE; + unsigned int arb_hold : MH_DEBUG_REG29_ARB_HOLD_SIZE; + unsigned int update_recent_stack_d : MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SIZE; + unsigned int least_recent_d : MH_DEBUG_REG29_LEAST_RECENT_d_SIZE; + unsigned int least_recent_index_d : MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SIZE; + unsigned int eff2_lru_winner_out : MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SIZE; + } mh_debug_reg29_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg29_t f; +} mh_debug_reg29_u; + + +/* + * MH_DEBUG_REG30 struct + */ + +#define MH_DEBUG_REG30_TC_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SIZE 1 +#define MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SIZE 1 +#define MH_DEBUG_REG30_TCD_NEARFULL_q_SIZE 1 +#define MH_DEBUG_REG30_TCHOLD_IP_q_SIZE 1 +#define MH_DEBUG_REG30_TCHOLD_CNT_q_SIZE 3 +#define MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE 1 +#define MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SIZE 1 +#define MH_DEBUG_REG30_TC_ROQ_SEND_q_SIZE 1 +#define MH_DEBUG_REG30_TC_MH_written_SIZE 1 +#define MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SIZE 7 +#define MH_DEBUG_REG30_WBURST_ACTIVE_SIZE 1 +#define MH_DEBUG_REG30_WLAST_q_SIZE 1 +#define MH_DEBUG_REG30_WBURST_IP_q_SIZE 1 +#define MH_DEBUG_REG30_WBURST_CNT_q_SIZE 3 +#define MH_DEBUG_REG30_CP_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG30_CP_MH_write_SIZE 1 +#define MH_DEBUG_REG30_RB_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG30_PA_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG30_ARB_WINNER_SIZE 3 + +#define MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT 0 +#define MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT 1 +#define MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT 2 +#define MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT 3 +#define MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT 4 +#define MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT 5 +#define MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT 8 +#define MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT 9 +#define MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT 10 +#define MH_DEBUG_REG30_TC_MH_written_SHIFT 11 +#define MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT 12 +#define MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT 19 +#define MH_DEBUG_REG30_WLAST_q_SHIFT 20 +#define MH_DEBUG_REG30_WBURST_IP_q_SHIFT 21 +#define MH_DEBUG_REG30_WBURST_CNT_q_SHIFT 22 +#define MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT 25 +#define MH_DEBUG_REG30_CP_MH_write_SHIFT 26 +#define MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT 27 +#define MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT 28 +#define MH_DEBUG_REG30_ARB_WINNER_SHIFT 29 + +#define MH_DEBUG_REG30_TC_ARB_HOLD_MASK 0x00000001 +#define MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK 0x00000002 +#define MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK 0x00000004 +#define MH_DEBUG_REG30_TCD_NEARFULL_q_MASK 0x00000008 +#define MH_DEBUG_REG30_TCHOLD_IP_q_MASK 0x00000010 +#define MH_DEBUG_REG30_TCHOLD_CNT_q_MASK 0x000000e0 +#define MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00000100 +#define MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK 0x00000200 +#define MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK 0x00000400 +#define MH_DEBUG_REG30_TC_MH_written_MASK 0x00000800 +#define MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK 0x0007f000 +#define MH_DEBUG_REG30_WBURST_ACTIVE_MASK 0x00080000 +#define MH_DEBUG_REG30_WLAST_q_MASK 0x00100000 +#define MH_DEBUG_REG30_WBURST_IP_q_MASK 0x00200000 +#define MH_DEBUG_REG30_WBURST_CNT_q_MASK 0x01c00000 +#define MH_DEBUG_REG30_CP_SEND_QUAL_MASK 0x02000000 +#define MH_DEBUG_REG30_CP_MH_write_MASK 0x04000000 +#define MH_DEBUG_REG30_RB_SEND_QUAL_MASK 0x08000000 +#define MH_DEBUG_REG30_PA_SEND_QUAL_MASK 0x10000000 +#define MH_DEBUG_REG30_ARB_WINNER_MASK 0xe0000000 + +#define MH_DEBUG_REG30_MASK \ + (MH_DEBUG_REG30_TC_ARB_HOLD_MASK | \ + MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK | \ + MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK | \ + MH_DEBUG_REG30_TCD_NEARFULL_q_MASK | \ + MH_DEBUG_REG30_TCHOLD_IP_q_MASK | \ + MH_DEBUG_REG30_TCHOLD_CNT_q_MASK | \ + MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK | \ + MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK | \ + MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK | \ + MH_DEBUG_REG30_TC_MH_written_MASK | \ + MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK | \ + MH_DEBUG_REG30_WBURST_ACTIVE_MASK | \ + MH_DEBUG_REG30_WLAST_q_MASK | \ + MH_DEBUG_REG30_WBURST_IP_q_MASK | \ + MH_DEBUG_REG30_WBURST_CNT_q_MASK | \ + MH_DEBUG_REG30_CP_SEND_QUAL_MASK | \ + MH_DEBUG_REG30_CP_MH_write_MASK | \ + MH_DEBUG_REG30_RB_SEND_QUAL_MASK | \ + MH_DEBUG_REG30_PA_SEND_QUAL_MASK | \ + MH_DEBUG_REG30_ARB_WINNER_MASK) + +#define MH_DEBUG_REG30(tc_arb_hold, tc_noroq_same_row_bank, tc_roq_same_row_bank, tcd_nearfull_q, tchold_ip_q, tchold_cnt_q, mh_arbiter_config_tc_reorder_enable, tc_roq_rtr_dbg_q, tc_roq_send_q, tc_mh_written, tcd_fullness_cnt_q, wburst_active, wlast_q, wburst_ip_q, wburst_cnt_q, cp_send_qual, cp_mh_write, rb_send_qual, pa_send_qual, arb_winner) \ + ((tc_arb_hold << MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT) | \ + (tc_noroq_same_row_bank << MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT) | \ + (tc_roq_same_row_bank << MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT) | \ + (tcd_nearfull_q << MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT) | \ + (tchold_ip_q << MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT) | \ + (tchold_cnt_q << MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT) | \ + (mh_arbiter_config_tc_reorder_enable << MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) | \ + (tc_roq_rtr_dbg_q << MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT) | \ + (tc_roq_send_q << MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT) | \ + (tc_mh_written << MH_DEBUG_REG30_TC_MH_written_SHIFT) | \ + (tcd_fullness_cnt_q << MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT) | \ + (wburst_active << MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT) | \ + (wlast_q << MH_DEBUG_REG30_WLAST_q_SHIFT) | \ + (wburst_ip_q << MH_DEBUG_REG30_WBURST_IP_q_SHIFT) | \ + (wburst_cnt_q << MH_DEBUG_REG30_WBURST_CNT_q_SHIFT) | \ + (cp_send_qual << MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT) | \ + (cp_mh_write << MH_DEBUG_REG30_CP_MH_write_SHIFT) | \ + (rb_send_qual << MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT) | \ + (pa_send_qual << MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT) | \ + (arb_winner << MH_DEBUG_REG30_ARB_WINNER_SHIFT)) + +#define MH_DEBUG_REG30_GET_TC_ARB_HOLD(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ARB_HOLD_MASK) >> MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG30_GET_TC_NOROQ_SAME_ROW_BANK(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG30_GET_TC_ROQ_SAME_ROW_BANK(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG30_GET_TCD_NEARFULL_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG30_GET_TCHOLD_IP_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TCHOLD_IP_q_MASK) >> MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT) +#define MH_DEBUG_REG30_GET_TCHOLD_CNT_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TCHOLD_CNT_q_MASK) >> MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT) +#define MH_DEBUG_REG30_GET_MH_ARBITER_CONFIG_TC_REORDER_ENABLE(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) >> MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) +#define MH_DEBUG_REG30_GET_TC_ROQ_RTR_DBG_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK) >> MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT) +#define MH_DEBUG_REG30_GET_TC_ROQ_SEND_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG30_GET_TC_MH_written(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TC_MH_written_MASK) >> MH_DEBUG_REG30_TC_MH_written_SHIFT) +#define MH_DEBUG_REG30_GET_TCD_FULLNESS_CNT_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK) >> MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT) +#define MH_DEBUG_REG30_GET_WBURST_ACTIVE(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_WBURST_ACTIVE_MASK) >> MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT) +#define MH_DEBUG_REG30_GET_WLAST_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_WLAST_q_MASK) >> MH_DEBUG_REG30_WLAST_q_SHIFT) +#define MH_DEBUG_REG30_GET_WBURST_IP_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_WBURST_IP_q_MASK) >> MH_DEBUG_REG30_WBURST_IP_q_SHIFT) +#define MH_DEBUG_REG30_GET_WBURST_CNT_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_WBURST_CNT_q_MASK) >> MH_DEBUG_REG30_WBURST_CNT_q_SHIFT) +#define MH_DEBUG_REG30_GET_CP_SEND_QUAL(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG30_GET_CP_MH_write(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_CP_MH_write_MASK) >> MH_DEBUG_REG30_CP_MH_write_SHIFT) +#define MH_DEBUG_REG30_GET_RB_SEND_QUAL(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG30_GET_PA_SEND_QUAL(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_PA_SEND_QUAL_MASK) >> MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG30_GET_ARB_WINNER(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_ARB_WINNER_MASK) >> MH_DEBUG_REG30_ARB_WINNER_SHIFT) + +#define MH_DEBUG_REG30_SET_TC_ARB_HOLD(mh_debug_reg30_reg, tc_arb_hold) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ARB_HOLD_MASK) | (tc_arb_hold << MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG30_SET_TC_NOROQ_SAME_ROW_BANK(mh_debug_reg30_reg, tc_noroq_same_row_bank) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK) | (tc_noroq_same_row_bank << MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG30_SET_TC_ROQ_SAME_ROW_BANK(mh_debug_reg30_reg, tc_roq_same_row_bank) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK) | (tc_roq_same_row_bank << MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG30_SET_TCD_NEARFULL_q(mh_debug_reg30_reg, tcd_nearfull_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG30_SET_TCHOLD_IP_q(mh_debug_reg30_reg, tchold_ip_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCHOLD_IP_q_MASK) | (tchold_ip_q << MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT) +#define MH_DEBUG_REG30_SET_TCHOLD_CNT_q(mh_debug_reg30_reg, tchold_cnt_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCHOLD_CNT_q_MASK) | (tchold_cnt_q << MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT) +#define MH_DEBUG_REG30_SET_MH_ARBITER_CONFIG_TC_REORDER_ENABLE(mh_debug_reg30_reg, mh_arbiter_config_tc_reorder_enable) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) | (mh_arbiter_config_tc_reorder_enable << MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) +#define MH_DEBUG_REG30_SET_TC_ROQ_RTR_DBG_q(mh_debug_reg30_reg, tc_roq_rtr_dbg_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK) | (tc_roq_rtr_dbg_q << MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT) +#define MH_DEBUG_REG30_SET_TC_ROQ_SEND_q(mh_debug_reg30_reg, tc_roq_send_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG30_SET_TC_MH_written(mh_debug_reg30_reg, tc_mh_written) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG30_TC_MH_written_SHIFT) +#define MH_DEBUG_REG30_SET_TCD_FULLNESS_CNT_q(mh_debug_reg30_reg, tcd_fullness_cnt_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK) | (tcd_fullness_cnt_q << MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT) +#define MH_DEBUG_REG30_SET_WBURST_ACTIVE(mh_debug_reg30_reg, wburst_active) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WBURST_ACTIVE_MASK) | (wburst_active << MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT) +#define MH_DEBUG_REG30_SET_WLAST_q(mh_debug_reg30_reg, wlast_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG30_WLAST_q_SHIFT) +#define MH_DEBUG_REG30_SET_WBURST_IP_q(mh_debug_reg30_reg, wburst_ip_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WBURST_IP_q_MASK) | (wburst_ip_q << MH_DEBUG_REG30_WBURST_IP_q_SHIFT) +#define MH_DEBUG_REG30_SET_WBURST_CNT_q(mh_debug_reg30_reg, wburst_cnt_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WBURST_CNT_q_MASK) | (wburst_cnt_q << MH_DEBUG_REG30_WBURST_CNT_q_SHIFT) +#define MH_DEBUG_REG30_SET_CP_SEND_QUAL(mh_debug_reg30_reg, cp_send_qual) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG30_SET_CP_MH_write(mh_debug_reg30_reg, cp_mh_write) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_CP_MH_write_MASK) | (cp_mh_write << MH_DEBUG_REG30_CP_MH_write_SHIFT) +#define MH_DEBUG_REG30_SET_RB_SEND_QUAL(mh_debug_reg30_reg, rb_send_qual) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG30_SET_PA_SEND_QUAL(mh_debug_reg30_reg, pa_send_qual) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_PA_SEND_QUAL_MASK) | (pa_send_qual << MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG30_SET_ARB_WINNER(mh_debug_reg30_reg, arb_winner) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG30_ARB_WINNER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg30_t { + unsigned int tc_arb_hold : MH_DEBUG_REG30_TC_ARB_HOLD_SIZE; + unsigned int tc_noroq_same_row_bank : MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SIZE; + unsigned int tc_roq_same_row_bank : MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG30_TCD_NEARFULL_q_SIZE; + unsigned int tchold_ip_q : MH_DEBUG_REG30_TCHOLD_IP_q_SIZE; + unsigned int tchold_cnt_q : MH_DEBUG_REG30_TCHOLD_CNT_q_SIZE; + unsigned int mh_arbiter_config_tc_reorder_enable : MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE; + unsigned int tc_roq_rtr_dbg_q : MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG30_TC_ROQ_SEND_q_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG30_TC_MH_written_SIZE; + unsigned int tcd_fullness_cnt_q : MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SIZE; + unsigned int wburst_active : MH_DEBUG_REG30_WBURST_ACTIVE_SIZE; + unsigned int wlast_q : MH_DEBUG_REG30_WLAST_q_SIZE; + unsigned int wburst_ip_q : MH_DEBUG_REG30_WBURST_IP_q_SIZE; + unsigned int wburst_cnt_q : MH_DEBUG_REG30_WBURST_CNT_q_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG30_CP_SEND_QUAL_SIZE; + unsigned int cp_mh_write : MH_DEBUG_REG30_CP_MH_write_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG30_RB_SEND_QUAL_SIZE; + unsigned int pa_send_qual : MH_DEBUG_REG30_PA_SEND_QUAL_SIZE; + unsigned int arb_winner : MH_DEBUG_REG30_ARB_WINNER_SIZE; + } mh_debug_reg30_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg30_t { + unsigned int arb_winner : MH_DEBUG_REG30_ARB_WINNER_SIZE; + unsigned int pa_send_qual : MH_DEBUG_REG30_PA_SEND_QUAL_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG30_RB_SEND_QUAL_SIZE; + unsigned int cp_mh_write : MH_DEBUG_REG30_CP_MH_write_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG30_CP_SEND_QUAL_SIZE; + unsigned int wburst_cnt_q : MH_DEBUG_REG30_WBURST_CNT_q_SIZE; + unsigned int wburst_ip_q : MH_DEBUG_REG30_WBURST_IP_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG30_WLAST_q_SIZE; + unsigned int wburst_active : MH_DEBUG_REG30_WBURST_ACTIVE_SIZE; + unsigned int tcd_fullness_cnt_q : MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG30_TC_MH_written_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG30_TC_ROQ_SEND_q_SIZE; + unsigned int tc_roq_rtr_dbg_q : MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SIZE; + unsigned int mh_arbiter_config_tc_reorder_enable : MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE; + unsigned int tchold_cnt_q : MH_DEBUG_REG30_TCHOLD_CNT_q_SIZE; + unsigned int tchold_ip_q : MH_DEBUG_REG30_TCHOLD_IP_q_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG30_TCD_NEARFULL_q_SIZE; + unsigned int tc_roq_same_row_bank : MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SIZE; + unsigned int tc_noroq_same_row_bank : MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SIZE; + unsigned int tc_arb_hold : MH_DEBUG_REG30_TC_ARB_HOLD_SIZE; + } mh_debug_reg30_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg30_t f; +} mh_debug_reg30_u; + + +/* + * MH_DEBUG_REG31 struct + */ + +#define MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SIZE 26 +#define MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3 + +#define MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT 0 +#define MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 26 + +#define MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK 0x03ffffff +#define MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x1c000000 + +#define MH_DEBUG_REG31_MASK \ + (MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK | \ + MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) + +#define MH_DEBUG_REG31(rf_arbiter_config_q, mh_clnt_axi_id_reuse_mmur_id) \ + ((rf_arbiter_config_q << MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT) | \ + (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)) + +#define MH_DEBUG_REG31_GET_RF_ARBITER_CONFIG_q(mh_debug_reg31) \ + ((mh_debug_reg31 & MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK) >> MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT) +#define MH_DEBUG_REG31_GET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg31) \ + ((mh_debug_reg31 & MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) + +#define MH_DEBUG_REG31_SET_RF_ARBITER_CONFIG_q(mh_debug_reg31_reg, rf_arbiter_config_q) \ + mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK) | (rf_arbiter_config_q << MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT) +#define MH_DEBUG_REG31_SET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg31_reg, mh_clnt_axi_id_reuse_mmur_id) \ + mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg31_t { + unsigned int rf_arbiter_config_q : MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SIZE; + unsigned int mh_clnt_axi_id_reuse_mmur_id : MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int : 3; + } mh_debug_reg31_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg31_t { + unsigned int : 3; + unsigned int mh_clnt_axi_id_reuse_mmur_id : MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int rf_arbiter_config_q : MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SIZE; + } mh_debug_reg31_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg31_t f; +} mh_debug_reg31_u; + + +/* + * MH_DEBUG_REG32 struct + */ + +#define MH_DEBUG_REG32_SAME_ROW_BANK_q_SIZE 8 +#define MH_DEBUG_REG32_ROQ_MARK_q_SIZE 8 +#define MH_DEBUG_REG32_ROQ_VALID_q_SIZE 8 +#define MH_DEBUG_REG32_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG32_KILL_EFF1_SIZE 1 +#define MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SIZE 1 +#define MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SIZE 1 +#define MH_DEBUG_REG32_TC_EFF1_QUAL_SIZE 1 +#define MH_DEBUG_REG32_TC_ROQ_EMPTY_SIZE 1 +#define MH_DEBUG_REG32_TC_ROQ_FULL_SIZE 1 + +#define MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT 0 +#define MH_DEBUG_REG32_ROQ_MARK_q_SHIFT 8 +#define MH_DEBUG_REG32_ROQ_VALID_q_SHIFT 16 +#define MH_DEBUG_REG32_TC_MH_send_SHIFT 24 +#define MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT 25 +#define MH_DEBUG_REG32_KILL_EFF1_SHIFT 26 +#define MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT 27 +#define MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT 28 +#define MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT 29 +#define MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT 30 +#define MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT 31 + +#define MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK 0x000000ff +#define MH_DEBUG_REG32_ROQ_MARK_q_MASK 0x0000ff00 +#define MH_DEBUG_REG32_ROQ_VALID_q_MASK 0x00ff0000 +#define MH_DEBUG_REG32_TC_MH_send_MASK 0x01000000 +#define MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK 0x02000000 +#define MH_DEBUG_REG32_KILL_EFF1_MASK 0x04000000 +#define MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000 +#define MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK 0x10000000 +#define MH_DEBUG_REG32_TC_EFF1_QUAL_MASK 0x20000000 +#define MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK 0x40000000 +#define MH_DEBUG_REG32_TC_ROQ_FULL_MASK 0x80000000 + +#define MH_DEBUG_REG32_MASK \ + (MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK | \ + MH_DEBUG_REG32_ROQ_MARK_q_MASK | \ + MH_DEBUG_REG32_ROQ_VALID_q_MASK | \ + MH_DEBUG_REG32_TC_MH_send_MASK | \ + MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG32_KILL_EFF1_MASK | \ + MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK | \ + MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK | \ + MH_DEBUG_REG32_TC_EFF1_QUAL_MASK | \ + MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK | \ + MH_DEBUG_REG32_TC_ROQ_FULL_MASK) + +#define MH_DEBUG_REG32(same_row_bank_q, roq_mark_q, roq_valid_q, tc_mh_send, tc_roq_rtr_q, kill_eff1, tc_roq_same_row_bank_sel, any_same_row_bank, tc_eff1_qual, tc_roq_empty, tc_roq_full) \ + ((same_row_bank_q << MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT) | \ + (roq_mark_q << MH_DEBUG_REG32_ROQ_MARK_q_SHIFT) | \ + (roq_valid_q << MH_DEBUG_REG32_ROQ_VALID_q_SHIFT) | \ + (tc_mh_send << MH_DEBUG_REG32_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT) | \ + (kill_eff1 << MH_DEBUG_REG32_KILL_EFF1_SHIFT) | \ + (tc_roq_same_row_bank_sel << MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) | \ + (any_same_row_bank << MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT) | \ + (tc_eff1_qual << MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT) | \ + (tc_roq_empty << MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT) | \ + (tc_roq_full << MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT)) + +#define MH_DEBUG_REG32_GET_SAME_ROW_BANK_q(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK) >> MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT) +#define MH_DEBUG_REG32_GET_ROQ_MARK_q(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_ROQ_MARK_q_MASK) >> MH_DEBUG_REG32_ROQ_MARK_q_SHIFT) +#define MH_DEBUG_REG32_GET_ROQ_VALID_q(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_ROQ_VALID_q_MASK) >> MH_DEBUG_REG32_ROQ_VALID_q_SHIFT) +#define MH_DEBUG_REG32_GET_TC_MH_send(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_TC_MH_send_MASK) >> MH_DEBUG_REG32_TC_MH_send_SHIFT) +#define MH_DEBUG_REG32_GET_TC_ROQ_RTR_q(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG32_GET_KILL_EFF1(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_KILL_EFF1_MASK) >> MH_DEBUG_REG32_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG32_GET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK) >> MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) +#define MH_DEBUG_REG32_GET_ANY_SAME_ROW_BANK(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG32_GET_TC_EFF1_QUAL(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_TC_EFF1_QUAL_MASK) >> MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG32_GET_TC_ROQ_EMPTY(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG32_GET_TC_ROQ_FULL(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_FULL_MASK) >> MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT) + +#define MH_DEBUG_REG32_SET_SAME_ROW_BANK_q(mh_debug_reg32_reg, same_row_bank_q) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK) | (same_row_bank_q << MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT) +#define MH_DEBUG_REG32_SET_ROQ_MARK_q(mh_debug_reg32_reg, roq_mark_q) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ROQ_MARK_q_MASK) | (roq_mark_q << MH_DEBUG_REG32_ROQ_MARK_q_SHIFT) +#define MH_DEBUG_REG32_SET_ROQ_VALID_q(mh_debug_reg32_reg, roq_valid_q) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ROQ_VALID_q_MASK) | (roq_valid_q << MH_DEBUG_REG32_ROQ_VALID_q_SHIFT) +#define MH_DEBUG_REG32_SET_TC_MH_send(mh_debug_reg32_reg, tc_mh_send) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG32_TC_MH_send_SHIFT) +#define MH_DEBUG_REG32_SET_TC_ROQ_RTR_q(mh_debug_reg32_reg, tc_roq_rtr_q) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG32_SET_KILL_EFF1(mh_debug_reg32_reg, kill_eff1) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG32_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG32_SET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg32_reg, tc_roq_same_row_bank_sel) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK) | (tc_roq_same_row_bank_sel << MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) +#define MH_DEBUG_REG32_SET_ANY_SAME_ROW_BANK(mh_debug_reg32_reg, any_same_row_bank) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK) | (any_same_row_bank << MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG32_SET_TC_EFF1_QUAL(mh_debug_reg32_reg, tc_eff1_qual) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_EFF1_QUAL_MASK) | (tc_eff1_qual << MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG32_SET_TC_ROQ_EMPTY(mh_debug_reg32_reg, tc_roq_empty) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG32_SET_TC_ROQ_FULL(mh_debug_reg32_reg, tc_roq_full) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_FULL_MASK) | (tc_roq_full << MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg32_t { + unsigned int same_row_bank_q : MH_DEBUG_REG32_SAME_ROW_BANK_q_SIZE; + unsigned int roq_mark_q : MH_DEBUG_REG32_ROQ_MARK_q_SIZE; + unsigned int roq_valid_q : MH_DEBUG_REG32_ROQ_VALID_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG32_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG32_KILL_EFF1_SIZE; + unsigned int tc_roq_same_row_bank_sel : MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SIZE; + unsigned int any_same_row_bank : MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SIZE; + unsigned int tc_eff1_qual : MH_DEBUG_REG32_TC_EFF1_QUAL_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG32_TC_ROQ_EMPTY_SIZE; + unsigned int tc_roq_full : MH_DEBUG_REG32_TC_ROQ_FULL_SIZE; + } mh_debug_reg32_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg32_t { + unsigned int tc_roq_full : MH_DEBUG_REG32_TC_ROQ_FULL_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG32_TC_ROQ_EMPTY_SIZE; + unsigned int tc_eff1_qual : MH_DEBUG_REG32_TC_EFF1_QUAL_SIZE; + unsigned int any_same_row_bank : MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SIZE; + unsigned int tc_roq_same_row_bank_sel : MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG32_KILL_EFF1_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG32_TC_MH_send_SIZE; + unsigned int roq_valid_q : MH_DEBUG_REG32_ROQ_VALID_q_SIZE; + unsigned int roq_mark_q : MH_DEBUG_REG32_ROQ_MARK_q_SIZE; + unsigned int same_row_bank_q : MH_DEBUG_REG32_SAME_ROW_BANK_q_SIZE; + } mh_debug_reg32_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg32_t f; +} mh_debug_reg32_u; + + +/* + * MH_DEBUG_REG33 struct + */ + +#define MH_DEBUG_REG33_SAME_ROW_BANK_q_SIZE 8 +#define MH_DEBUG_REG33_ROQ_MARK_d_SIZE 8 +#define MH_DEBUG_REG33_ROQ_VALID_d_SIZE 8 +#define MH_DEBUG_REG33_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG33_KILL_EFF1_SIZE 1 +#define MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SIZE 1 +#define MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SIZE 1 +#define MH_DEBUG_REG33_TC_EFF1_QUAL_SIZE 1 +#define MH_DEBUG_REG33_TC_ROQ_EMPTY_SIZE 1 +#define MH_DEBUG_REG33_TC_ROQ_FULL_SIZE 1 + +#define MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT 0 +#define MH_DEBUG_REG33_ROQ_MARK_d_SHIFT 8 +#define MH_DEBUG_REG33_ROQ_VALID_d_SHIFT 16 +#define MH_DEBUG_REG33_TC_MH_send_SHIFT 24 +#define MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT 25 +#define MH_DEBUG_REG33_KILL_EFF1_SHIFT 26 +#define MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT 27 +#define MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT 28 +#define MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT 29 +#define MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT 30 +#define MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT 31 + +#define MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK 0x000000ff +#define MH_DEBUG_REG33_ROQ_MARK_d_MASK 0x0000ff00 +#define MH_DEBUG_REG33_ROQ_VALID_d_MASK 0x00ff0000 +#define MH_DEBUG_REG33_TC_MH_send_MASK 0x01000000 +#define MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK 0x02000000 +#define MH_DEBUG_REG33_KILL_EFF1_MASK 0x04000000 +#define MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000 +#define MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK 0x10000000 +#define MH_DEBUG_REG33_TC_EFF1_QUAL_MASK 0x20000000 +#define MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK 0x40000000 +#define MH_DEBUG_REG33_TC_ROQ_FULL_MASK 0x80000000 + +#define MH_DEBUG_REG33_MASK \ + (MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK | \ + MH_DEBUG_REG33_ROQ_MARK_d_MASK | \ + MH_DEBUG_REG33_ROQ_VALID_d_MASK | \ + MH_DEBUG_REG33_TC_MH_send_MASK | \ + MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG33_KILL_EFF1_MASK | \ + MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK | \ + MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK | \ + MH_DEBUG_REG33_TC_EFF1_QUAL_MASK | \ + MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK | \ + MH_DEBUG_REG33_TC_ROQ_FULL_MASK) + +#define MH_DEBUG_REG33(same_row_bank_q, roq_mark_d, roq_valid_d, tc_mh_send, tc_roq_rtr_q, kill_eff1, tc_roq_same_row_bank_sel, any_same_row_bank, tc_eff1_qual, tc_roq_empty, tc_roq_full) \ + ((same_row_bank_q << MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT) | \ + (roq_mark_d << MH_DEBUG_REG33_ROQ_MARK_d_SHIFT) | \ + (roq_valid_d << MH_DEBUG_REG33_ROQ_VALID_d_SHIFT) | \ + (tc_mh_send << MH_DEBUG_REG33_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT) | \ + (kill_eff1 << MH_DEBUG_REG33_KILL_EFF1_SHIFT) | \ + (tc_roq_same_row_bank_sel << MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) | \ + (any_same_row_bank << MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT) | \ + (tc_eff1_qual << MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT) | \ + (tc_roq_empty << MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT) | \ + (tc_roq_full << MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT)) + +#define MH_DEBUG_REG33_GET_SAME_ROW_BANK_q(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK) >> MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT) +#define MH_DEBUG_REG33_GET_ROQ_MARK_d(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_ROQ_MARK_d_MASK) >> MH_DEBUG_REG33_ROQ_MARK_d_SHIFT) +#define MH_DEBUG_REG33_GET_ROQ_VALID_d(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_ROQ_VALID_d_MASK) >> MH_DEBUG_REG33_ROQ_VALID_d_SHIFT) +#define MH_DEBUG_REG33_GET_TC_MH_send(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_TC_MH_send_MASK) >> MH_DEBUG_REG33_TC_MH_send_SHIFT) +#define MH_DEBUG_REG33_GET_TC_ROQ_RTR_q(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG33_GET_KILL_EFF1(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_KILL_EFF1_MASK) >> MH_DEBUG_REG33_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG33_GET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK) >> MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) +#define MH_DEBUG_REG33_GET_ANY_SAME_ROW_BANK(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG33_GET_TC_EFF1_QUAL(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_TC_EFF1_QUAL_MASK) >> MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG33_GET_TC_ROQ_EMPTY(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG33_GET_TC_ROQ_FULL(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_FULL_MASK) >> MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT) + +#define MH_DEBUG_REG33_SET_SAME_ROW_BANK_q(mh_debug_reg33_reg, same_row_bank_q) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK) | (same_row_bank_q << MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT) +#define MH_DEBUG_REG33_SET_ROQ_MARK_d(mh_debug_reg33_reg, roq_mark_d) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ROQ_MARK_d_MASK) | (roq_mark_d << MH_DEBUG_REG33_ROQ_MARK_d_SHIFT) +#define MH_DEBUG_REG33_SET_ROQ_VALID_d(mh_debug_reg33_reg, roq_valid_d) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ROQ_VALID_d_MASK) | (roq_valid_d << MH_DEBUG_REG33_ROQ_VALID_d_SHIFT) +#define MH_DEBUG_REG33_SET_TC_MH_send(mh_debug_reg33_reg, tc_mh_send) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG33_TC_MH_send_SHIFT) +#define MH_DEBUG_REG33_SET_TC_ROQ_RTR_q(mh_debug_reg33_reg, tc_roq_rtr_q) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG33_SET_KILL_EFF1(mh_debug_reg33_reg, kill_eff1) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG33_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG33_SET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg33_reg, tc_roq_same_row_bank_sel) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK) | (tc_roq_same_row_bank_sel << MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) +#define MH_DEBUG_REG33_SET_ANY_SAME_ROW_BANK(mh_debug_reg33_reg, any_same_row_bank) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK) | (any_same_row_bank << MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG33_SET_TC_EFF1_QUAL(mh_debug_reg33_reg, tc_eff1_qual) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_EFF1_QUAL_MASK) | (tc_eff1_qual << MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG33_SET_TC_ROQ_EMPTY(mh_debug_reg33_reg, tc_roq_empty) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG33_SET_TC_ROQ_FULL(mh_debug_reg33_reg, tc_roq_full) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_FULL_MASK) | (tc_roq_full << MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg33_t { + unsigned int same_row_bank_q : MH_DEBUG_REG33_SAME_ROW_BANK_q_SIZE; + unsigned int roq_mark_d : MH_DEBUG_REG33_ROQ_MARK_d_SIZE; + unsigned int roq_valid_d : MH_DEBUG_REG33_ROQ_VALID_d_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG33_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG33_KILL_EFF1_SIZE; + unsigned int tc_roq_same_row_bank_sel : MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SIZE; + unsigned int any_same_row_bank : MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SIZE; + unsigned int tc_eff1_qual : MH_DEBUG_REG33_TC_EFF1_QUAL_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG33_TC_ROQ_EMPTY_SIZE; + unsigned int tc_roq_full : MH_DEBUG_REG33_TC_ROQ_FULL_SIZE; + } mh_debug_reg33_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg33_t { + unsigned int tc_roq_full : MH_DEBUG_REG33_TC_ROQ_FULL_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG33_TC_ROQ_EMPTY_SIZE; + unsigned int tc_eff1_qual : MH_DEBUG_REG33_TC_EFF1_QUAL_SIZE; + unsigned int any_same_row_bank : MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SIZE; + unsigned int tc_roq_same_row_bank_sel : MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG33_KILL_EFF1_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG33_TC_MH_send_SIZE; + unsigned int roq_valid_d : MH_DEBUG_REG33_ROQ_VALID_d_SIZE; + unsigned int roq_mark_d : MH_DEBUG_REG33_ROQ_MARK_d_SIZE; + unsigned int same_row_bank_q : MH_DEBUG_REG33_SAME_ROW_BANK_q_SIZE; + } mh_debug_reg33_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg33_t f; +} mh_debug_reg33_u; + + +/* + * MH_DEBUG_REG34 struct + */ + +#define MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SIZE 8 +#define MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SIZE 8 +#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SIZE 8 +#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SIZE 8 + +#define MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT 0 +#define MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT 8 +#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT 16 +#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT 24 + +#define MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK 0x000000ff +#define MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK 0x0000ff00 +#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK 0x00ff0000 +#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK 0xff000000 + +#define MH_DEBUG_REG34_MASK \ + (MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK | \ + MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK | \ + MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK | \ + MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK) + +#define MH_DEBUG_REG34(same_row_bank_win, same_row_bank_req, non_same_row_bank_win, non_same_row_bank_req) \ + ((same_row_bank_win << MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT) | \ + (same_row_bank_req << MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT) | \ + (non_same_row_bank_win << MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT) | \ + (non_same_row_bank_req << MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT)) + +#define MH_DEBUG_REG34_GET_SAME_ROW_BANK_WIN(mh_debug_reg34) \ + ((mh_debug_reg34 & MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK) >> MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT) +#define MH_DEBUG_REG34_GET_SAME_ROW_BANK_REQ(mh_debug_reg34) \ + ((mh_debug_reg34 & MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK) >> MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT) +#define MH_DEBUG_REG34_GET_NON_SAME_ROW_BANK_WIN(mh_debug_reg34) \ + ((mh_debug_reg34 & MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK) >> MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT) +#define MH_DEBUG_REG34_GET_NON_SAME_ROW_BANK_REQ(mh_debug_reg34) \ + ((mh_debug_reg34 & MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK) >> MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT) + +#define MH_DEBUG_REG34_SET_SAME_ROW_BANK_WIN(mh_debug_reg34_reg, same_row_bank_win) \ + mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK) | (same_row_bank_win << MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT) +#define MH_DEBUG_REG34_SET_SAME_ROW_BANK_REQ(mh_debug_reg34_reg, same_row_bank_req) \ + mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK) | (same_row_bank_req << MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT) +#define MH_DEBUG_REG34_SET_NON_SAME_ROW_BANK_WIN(mh_debug_reg34_reg, non_same_row_bank_win) \ + mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK) | (non_same_row_bank_win << MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT) +#define MH_DEBUG_REG34_SET_NON_SAME_ROW_BANK_REQ(mh_debug_reg34_reg, non_same_row_bank_req) \ + mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK) | (non_same_row_bank_req << MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg34_t { + unsigned int same_row_bank_win : MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SIZE; + unsigned int same_row_bank_req : MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SIZE; + unsigned int non_same_row_bank_win : MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SIZE; + unsigned int non_same_row_bank_req : MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SIZE; + } mh_debug_reg34_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg34_t { + unsigned int non_same_row_bank_req : MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SIZE; + unsigned int non_same_row_bank_win : MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SIZE; + unsigned int same_row_bank_req : MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SIZE; + unsigned int same_row_bank_win : MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SIZE; + } mh_debug_reg34_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg34_t f; +} mh_debug_reg34_u; + + +/* + * MH_DEBUG_REG35 struct + */ + +#define MH_DEBUG_REG35_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG35_ROQ_MARK_q_0_SIZE 1 +#define MH_DEBUG_REG35_ROQ_VALID_q_0_SIZE 1 +#define MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SIZE 1 +#define MH_DEBUG_REG35_ROQ_ADDR_0_SIZE 27 + +#define MH_DEBUG_REG35_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT 2 +#define MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT 3 +#define MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT 4 +#define MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT 5 + +#define MH_DEBUG_REG35_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG35_ROQ_MARK_q_0_MASK 0x00000004 +#define MH_DEBUG_REG35_ROQ_VALID_q_0_MASK 0x00000008 +#define MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK 0x00000010 +#define MH_DEBUG_REG35_ROQ_ADDR_0_MASK 0xffffffe0 + +#define MH_DEBUG_REG35_MASK \ + (MH_DEBUG_REG35_TC_MH_send_MASK | \ + MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG35_ROQ_MARK_q_0_MASK | \ + MH_DEBUG_REG35_ROQ_VALID_q_0_MASK | \ + MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK | \ + MH_DEBUG_REG35_ROQ_ADDR_0_MASK) + +#define MH_DEBUG_REG35(tc_mh_send, tc_roq_rtr_q, roq_mark_q_0, roq_valid_q_0, same_row_bank_q_0, roq_addr_0) \ + ((tc_mh_send << MH_DEBUG_REG35_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_0 << MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT) | \ + (roq_valid_q_0 << MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT) | \ + (same_row_bank_q_0 << MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT) | \ + (roq_addr_0 << MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT)) + +#define MH_DEBUG_REG35_GET_TC_MH_send(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_TC_MH_send_MASK) >> MH_DEBUG_REG35_TC_MH_send_SHIFT) +#define MH_DEBUG_REG35_GET_TC_ROQ_RTR_q(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG35_GET_ROQ_MARK_q_0(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_MARK_q_0_MASK) >> MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT) +#define MH_DEBUG_REG35_GET_ROQ_VALID_q_0(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_VALID_q_0_MASK) >> MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT) +#define MH_DEBUG_REG35_GET_SAME_ROW_BANK_q_0(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK) >> MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT) +#define MH_DEBUG_REG35_GET_ROQ_ADDR_0(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_ADDR_0_MASK) >> MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT) + +#define MH_DEBUG_REG35_SET_TC_MH_send(mh_debug_reg35_reg, tc_mh_send) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG35_TC_MH_send_SHIFT) +#define MH_DEBUG_REG35_SET_TC_ROQ_RTR_q(mh_debug_reg35_reg, tc_roq_rtr_q) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG35_SET_ROQ_MARK_q_0(mh_debug_reg35_reg, roq_mark_q_0) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_MARK_q_0_MASK) | (roq_mark_q_0 << MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT) +#define MH_DEBUG_REG35_SET_ROQ_VALID_q_0(mh_debug_reg35_reg, roq_valid_q_0) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_VALID_q_0_MASK) | (roq_valid_q_0 << MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT) +#define MH_DEBUG_REG35_SET_SAME_ROW_BANK_q_0(mh_debug_reg35_reg, same_row_bank_q_0) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK) | (same_row_bank_q_0 << MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT) +#define MH_DEBUG_REG35_SET_ROQ_ADDR_0(mh_debug_reg35_reg, roq_addr_0) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_ADDR_0_MASK) | (roq_addr_0 << MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg35_t { + unsigned int tc_mh_send : MH_DEBUG_REG35_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_0 : MH_DEBUG_REG35_ROQ_MARK_q_0_SIZE; + unsigned int roq_valid_q_0 : MH_DEBUG_REG35_ROQ_VALID_q_0_SIZE; + unsigned int same_row_bank_q_0 : MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SIZE; + unsigned int roq_addr_0 : MH_DEBUG_REG35_ROQ_ADDR_0_SIZE; + } mh_debug_reg35_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg35_t { + unsigned int roq_addr_0 : MH_DEBUG_REG35_ROQ_ADDR_0_SIZE; + unsigned int same_row_bank_q_0 : MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SIZE; + unsigned int roq_valid_q_0 : MH_DEBUG_REG35_ROQ_VALID_q_0_SIZE; + unsigned int roq_mark_q_0 : MH_DEBUG_REG35_ROQ_MARK_q_0_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG35_TC_MH_send_SIZE; + } mh_debug_reg35_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg35_t f; +} mh_debug_reg35_u; + + +/* + * MH_DEBUG_REG36 struct + */ + +#define MH_DEBUG_REG36_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG36_ROQ_MARK_q_1_SIZE 1 +#define MH_DEBUG_REG36_ROQ_VALID_q_1_SIZE 1 +#define MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SIZE 1 +#define MH_DEBUG_REG36_ROQ_ADDR_1_SIZE 27 + +#define MH_DEBUG_REG36_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT 2 +#define MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT 3 +#define MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT 4 +#define MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT 5 + +#define MH_DEBUG_REG36_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG36_ROQ_MARK_q_1_MASK 0x00000004 +#define MH_DEBUG_REG36_ROQ_VALID_q_1_MASK 0x00000008 +#define MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK 0x00000010 +#define MH_DEBUG_REG36_ROQ_ADDR_1_MASK 0xffffffe0 + +#define MH_DEBUG_REG36_MASK \ + (MH_DEBUG_REG36_TC_MH_send_MASK | \ + MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG36_ROQ_MARK_q_1_MASK | \ + MH_DEBUG_REG36_ROQ_VALID_q_1_MASK | \ + MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK | \ + MH_DEBUG_REG36_ROQ_ADDR_1_MASK) + +#define MH_DEBUG_REG36(tc_mh_send, tc_roq_rtr_q, roq_mark_q_1, roq_valid_q_1, same_row_bank_q_1, roq_addr_1) \ + ((tc_mh_send << MH_DEBUG_REG36_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_1 << MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT) | \ + (roq_valid_q_1 << MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT) | \ + (same_row_bank_q_1 << MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT) | \ + (roq_addr_1 << MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT)) + +#define MH_DEBUG_REG36_GET_TC_MH_send(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_TC_MH_send_MASK) >> MH_DEBUG_REG36_TC_MH_send_SHIFT) +#define MH_DEBUG_REG36_GET_TC_ROQ_RTR_q(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG36_GET_ROQ_MARK_q_1(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_MARK_q_1_MASK) >> MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT) +#define MH_DEBUG_REG36_GET_ROQ_VALID_q_1(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_VALID_q_1_MASK) >> MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT) +#define MH_DEBUG_REG36_GET_SAME_ROW_BANK_q_1(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK) >> MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT) +#define MH_DEBUG_REG36_GET_ROQ_ADDR_1(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_ADDR_1_MASK) >> MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT) + +#define MH_DEBUG_REG36_SET_TC_MH_send(mh_debug_reg36_reg, tc_mh_send) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG36_TC_MH_send_SHIFT) +#define MH_DEBUG_REG36_SET_TC_ROQ_RTR_q(mh_debug_reg36_reg, tc_roq_rtr_q) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG36_SET_ROQ_MARK_q_1(mh_debug_reg36_reg, roq_mark_q_1) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_MARK_q_1_MASK) | (roq_mark_q_1 << MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT) +#define MH_DEBUG_REG36_SET_ROQ_VALID_q_1(mh_debug_reg36_reg, roq_valid_q_1) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_VALID_q_1_MASK) | (roq_valid_q_1 << MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT) +#define MH_DEBUG_REG36_SET_SAME_ROW_BANK_q_1(mh_debug_reg36_reg, same_row_bank_q_1) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK) | (same_row_bank_q_1 << MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT) +#define MH_DEBUG_REG36_SET_ROQ_ADDR_1(mh_debug_reg36_reg, roq_addr_1) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_ADDR_1_MASK) | (roq_addr_1 << MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg36_t { + unsigned int tc_mh_send : MH_DEBUG_REG36_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_1 : MH_DEBUG_REG36_ROQ_MARK_q_1_SIZE; + unsigned int roq_valid_q_1 : MH_DEBUG_REG36_ROQ_VALID_q_1_SIZE; + unsigned int same_row_bank_q_1 : MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SIZE; + unsigned int roq_addr_1 : MH_DEBUG_REG36_ROQ_ADDR_1_SIZE; + } mh_debug_reg36_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg36_t { + unsigned int roq_addr_1 : MH_DEBUG_REG36_ROQ_ADDR_1_SIZE; + unsigned int same_row_bank_q_1 : MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SIZE; + unsigned int roq_valid_q_1 : MH_DEBUG_REG36_ROQ_VALID_q_1_SIZE; + unsigned int roq_mark_q_1 : MH_DEBUG_REG36_ROQ_MARK_q_1_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG36_TC_MH_send_SIZE; + } mh_debug_reg36_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg36_t f; +} mh_debug_reg36_u; + + +/* + * MH_DEBUG_REG37 struct + */ + +#define MH_DEBUG_REG37_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG37_ROQ_MARK_q_2_SIZE 1 +#define MH_DEBUG_REG37_ROQ_VALID_q_2_SIZE 1 +#define MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SIZE 1 +#define MH_DEBUG_REG37_ROQ_ADDR_2_SIZE 27 + +#define MH_DEBUG_REG37_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT 2 +#define MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT 3 +#define MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT 4 +#define MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT 5 + +#define MH_DEBUG_REG37_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG37_ROQ_MARK_q_2_MASK 0x00000004 +#define MH_DEBUG_REG37_ROQ_VALID_q_2_MASK 0x00000008 +#define MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK 0x00000010 +#define MH_DEBUG_REG37_ROQ_ADDR_2_MASK 0xffffffe0 + +#define MH_DEBUG_REG37_MASK \ + (MH_DEBUG_REG37_TC_MH_send_MASK | \ + MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG37_ROQ_MARK_q_2_MASK | \ + MH_DEBUG_REG37_ROQ_VALID_q_2_MASK | \ + MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK | \ + MH_DEBUG_REG37_ROQ_ADDR_2_MASK) + +#define MH_DEBUG_REG37(tc_mh_send, tc_roq_rtr_q, roq_mark_q_2, roq_valid_q_2, same_row_bank_q_2, roq_addr_2) \ + ((tc_mh_send << MH_DEBUG_REG37_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_2 << MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT) | \ + (roq_valid_q_2 << MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT) | \ + (same_row_bank_q_2 << MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT) | \ + (roq_addr_2 << MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT)) + +#define MH_DEBUG_REG37_GET_TC_MH_send(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_TC_MH_send_MASK) >> MH_DEBUG_REG37_TC_MH_send_SHIFT) +#define MH_DEBUG_REG37_GET_TC_ROQ_RTR_q(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG37_GET_ROQ_MARK_q_2(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_MARK_q_2_MASK) >> MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT) +#define MH_DEBUG_REG37_GET_ROQ_VALID_q_2(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_VALID_q_2_MASK) >> MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT) +#define MH_DEBUG_REG37_GET_SAME_ROW_BANK_q_2(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK) >> MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT) +#define MH_DEBUG_REG37_GET_ROQ_ADDR_2(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_ADDR_2_MASK) >> MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT) + +#define MH_DEBUG_REG37_SET_TC_MH_send(mh_debug_reg37_reg, tc_mh_send) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG37_TC_MH_send_SHIFT) +#define MH_DEBUG_REG37_SET_TC_ROQ_RTR_q(mh_debug_reg37_reg, tc_roq_rtr_q) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG37_SET_ROQ_MARK_q_2(mh_debug_reg37_reg, roq_mark_q_2) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_MARK_q_2_MASK) | (roq_mark_q_2 << MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT) +#define MH_DEBUG_REG37_SET_ROQ_VALID_q_2(mh_debug_reg37_reg, roq_valid_q_2) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_VALID_q_2_MASK) | (roq_valid_q_2 << MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT) +#define MH_DEBUG_REG37_SET_SAME_ROW_BANK_q_2(mh_debug_reg37_reg, same_row_bank_q_2) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK) | (same_row_bank_q_2 << MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT) +#define MH_DEBUG_REG37_SET_ROQ_ADDR_2(mh_debug_reg37_reg, roq_addr_2) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_ADDR_2_MASK) | (roq_addr_2 << MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg37_t { + unsigned int tc_mh_send : MH_DEBUG_REG37_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_2 : MH_DEBUG_REG37_ROQ_MARK_q_2_SIZE; + unsigned int roq_valid_q_2 : MH_DEBUG_REG37_ROQ_VALID_q_2_SIZE; + unsigned int same_row_bank_q_2 : MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SIZE; + unsigned int roq_addr_2 : MH_DEBUG_REG37_ROQ_ADDR_2_SIZE; + } mh_debug_reg37_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg37_t { + unsigned int roq_addr_2 : MH_DEBUG_REG37_ROQ_ADDR_2_SIZE; + unsigned int same_row_bank_q_2 : MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SIZE; + unsigned int roq_valid_q_2 : MH_DEBUG_REG37_ROQ_VALID_q_2_SIZE; + unsigned int roq_mark_q_2 : MH_DEBUG_REG37_ROQ_MARK_q_2_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG37_TC_MH_send_SIZE; + } mh_debug_reg37_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg37_t f; +} mh_debug_reg37_u; + + +/* + * MH_DEBUG_REG38 struct + */ + +#define MH_DEBUG_REG38_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG38_ROQ_MARK_q_3_SIZE 1 +#define MH_DEBUG_REG38_ROQ_VALID_q_3_SIZE 1 +#define MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SIZE 1 +#define MH_DEBUG_REG38_ROQ_ADDR_3_SIZE 27 + +#define MH_DEBUG_REG38_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT 2 +#define MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT 3 +#define MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT 4 +#define MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT 5 + +#define MH_DEBUG_REG38_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG38_ROQ_MARK_q_3_MASK 0x00000004 +#define MH_DEBUG_REG38_ROQ_VALID_q_3_MASK 0x00000008 +#define MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK 0x00000010 +#define MH_DEBUG_REG38_ROQ_ADDR_3_MASK 0xffffffe0 + +#define MH_DEBUG_REG38_MASK \ + (MH_DEBUG_REG38_TC_MH_send_MASK | \ + MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG38_ROQ_MARK_q_3_MASK | \ + MH_DEBUG_REG38_ROQ_VALID_q_3_MASK | \ + MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK | \ + MH_DEBUG_REG38_ROQ_ADDR_3_MASK) + +#define MH_DEBUG_REG38(tc_mh_send, tc_roq_rtr_q, roq_mark_q_3, roq_valid_q_3, same_row_bank_q_3, roq_addr_3) \ + ((tc_mh_send << MH_DEBUG_REG38_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_3 << MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT) | \ + (roq_valid_q_3 << MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT) | \ + (same_row_bank_q_3 << MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT) | \ + (roq_addr_3 << MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT)) + +#define MH_DEBUG_REG38_GET_TC_MH_send(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_TC_MH_send_MASK) >> MH_DEBUG_REG38_TC_MH_send_SHIFT) +#define MH_DEBUG_REG38_GET_TC_ROQ_RTR_q(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG38_GET_ROQ_MARK_q_3(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_MARK_q_3_MASK) >> MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT) +#define MH_DEBUG_REG38_GET_ROQ_VALID_q_3(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_VALID_q_3_MASK) >> MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT) +#define MH_DEBUG_REG38_GET_SAME_ROW_BANK_q_3(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK) >> MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT) +#define MH_DEBUG_REG38_GET_ROQ_ADDR_3(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_ADDR_3_MASK) >> MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT) + +#define MH_DEBUG_REG38_SET_TC_MH_send(mh_debug_reg38_reg, tc_mh_send) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG38_TC_MH_send_SHIFT) +#define MH_DEBUG_REG38_SET_TC_ROQ_RTR_q(mh_debug_reg38_reg, tc_roq_rtr_q) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG38_SET_ROQ_MARK_q_3(mh_debug_reg38_reg, roq_mark_q_3) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_MARK_q_3_MASK) | (roq_mark_q_3 << MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT) +#define MH_DEBUG_REG38_SET_ROQ_VALID_q_3(mh_debug_reg38_reg, roq_valid_q_3) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_VALID_q_3_MASK) | (roq_valid_q_3 << MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT) +#define MH_DEBUG_REG38_SET_SAME_ROW_BANK_q_3(mh_debug_reg38_reg, same_row_bank_q_3) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK) | (same_row_bank_q_3 << MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT) +#define MH_DEBUG_REG38_SET_ROQ_ADDR_3(mh_debug_reg38_reg, roq_addr_3) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_ADDR_3_MASK) | (roq_addr_3 << MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg38_t { + unsigned int tc_mh_send : MH_DEBUG_REG38_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_3 : MH_DEBUG_REG38_ROQ_MARK_q_3_SIZE; + unsigned int roq_valid_q_3 : MH_DEBUG_REG38_ROQ_VALID_q_3_SIZE; + unsigned int same_row_bank_q_3 : MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SIZE; + unsigned int roq_addr_3 : MH_DEBUG_REG38_ROQ_ADDR_3_SIZE; + } mh_debug_reg38_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg38_t { + unsigned int roq_addr_3 : MH_DEBUG_REG38_ROQ_ADDR_3_SIZE; + unsigned int same_row_bank_q_3 : MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SIZE; + unsigned int roq_valid_q_3 : MH_DEBUG_REG38_ROQ_VALID_q_3_SIZE; + unsigned int roq_mark_q_3 : MH_DEBUG_REG38_ROQ_MARK_q_3_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG38_TC_MH_send_SIZE; + } mh_debug_reg38_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg38_t f; +} mh_debug_reg38_u; + + +/* + * MH_DEBUG_REG39 struct + */ + +#define MH_DEBUG_REG39_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG39_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG39_ROQ_MARK_q_4_SIZE 1 +#define MH_DEBUG_REG39_ROQ_VALID_q_4_SIZE 1 +#define MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SIZE 1 +#define MH_DEBUG_REG39_ROQ_ADDR_4_SIZE 27 + +#define MH_DEBUG_REG39_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT 2 +#define MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT 3 +#define MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT 4 +#define MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT 5 + +#define MH_DEBUG_REG39_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG39_ROQ_MARK_q_4_MASK 0x00000004 +#define MH_DEBUG_REG39_ROQ_VALID_q_4_MASK 0x00000008 +#define MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK 0x00000010 +#define MH_DEBUG_REG39_ROQ_ADDR_4_MASK 0xffffffe0 + +#define MH_DEBUG_REG39_MASK \ + (MH_DEBUG_REG39_TC_MH_send_MASK | \ + MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG39_ROQ_MARK_q_4_MASK | \ + MH_DEBUG_REG39_ROQ_VALID_q_4_MASK | \ + MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK | \ + MH_DEBUG_REG39_ROQ_ADDR_4_MASK) + +#define MH_DEBUG_REG39(tc_mh_send, tc_roq_rtr_q, roq_mark_q_4, roq_valid_q_4, same_row_bank_q_4, roq_addr_4) \ + ((tc_mh_send << MH_DEBUG_REG39_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_4 << MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT) | \ + (roq_valid_q_4 << MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT) | \ + (same_row_bank_q_4 << MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT) | \ + (roq_addr_4 << MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT)) + +#define MH_DEBUG_REG39_GET_TC_MH_send(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_TC_MH_send_MASK) >> MH_DEBUG_REG39_TC_MH_send_SHIFT) +#define MH_DEBUG_REG39_GET_TC_ROQ_RTR_q(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG39_GET_ROQ_MARK_q_4(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_ROQ_MARK_q_4_MASK) >> MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT) +#define MH_DEBUG_REG39_GET_ROQ_VALID_q_4(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_ROQ_VALID_q_4_MASK) >> MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT) +#define MH_DEBUG_REG39_GET_SAME_ROW_BANK_q_4(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK) >> MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT) +#define MH_DEBUG_REG39_GET_ROQ_ADDR_4(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_ROQ_ADDR_4_MASK) >> MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT) + +#define MH_DEBUG_REG39_SET_TC_MH_send(mh_debug_reg39_reg, tc_mh_send) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG39_TC_MH_send_SHIFT) +#define MH_DEBUG_REG39_SET_TC_ROQ_RTR_q(mh_debug_reg39_reg, tc_roq_rtr_q) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG39_SET_ROQ_MARK_q_4(mh_debug_reg39_reg, roq_mark_q_4) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ROQ_MARK_q_4_MASK) | (roq_mark_q_4 << MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT) +#define MH_DEBUG_REG39_SET_ROQ_VALID_q_4(mh_debug_reg39_reg, roq_valid_q_4) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ROQ_VALID_q_4_MASK) | (roq_valid_q_4 << MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT) +#define MH_DEBUG_REG39_SET_SAME_ROW_BANK_q_4(mh_debug_reg39_reg, same_row_bank_q_4) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK) | (same_row_bank_q_4 << MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT) +#define MH_DEBUG_REG39_SET_ROQ_ADDR_4(mh_debug_reg39_reg, roq_addr_4) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ROQ_ADDR_4_MASK) | (roq_addr_4 << MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg39_t { + unsigned int tc_mh_send : MH_DEBUG_REG39_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG39_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_4 : MH_DEBUG_REG39_ROQ_MARK_q_4_SIZE; + unsigned int roq_valid_q_4 : MH_DEBUG_REG39_ROQ_VALID_q_4_SIZE; + unsigned int same_row_bank_q_4 : MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SIZE; + unsigned int roq_addr_4 : MH_DEBUG_REG39_ROQ_ADDR_4_SIZE; + } mh_debug_reg39_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg39_t { + unsigned int roq_addr_4 : MH_DEBUG_REG39_ROQ_ADDR_4_SIZE; + unsigned int same_row_bank_q_4 : MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SIZE; + unsigned int roq_valid_q_4 : MH_DEBUG_REG39_ROQ_VALID_q_4_SIZE; + unsigned int roq_mark_q_4 : MH_DEBUG_REG39_ROQ_MARK_q_4_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG39_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG39_TC_MH_send_SIZE; + } mh_debug_reg39_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg39_t f; +} mh_debug_reg39_u; + + +/* + * MH_DEBUG_REG40 struct + */ + +#define MH_DEBUG_REG40_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG40_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG40_ROQ_MARK_q_5_SIZE 1 +#define MH_DEBUG_REG40_ROQ_VALID_q_5_SIZE 1 +#define MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SIZE 1 +#define MH_DEBUG_REG40_ROQ_ADDR_5_SIZE 27 + +#define MH_DEBUG_REG40_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT 2 +#define MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT 3 +#define MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT 4 +#define MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT 5 + +#define MH_DEBUG_REG40_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG40_ROQ_MARK_q_5_MASK 0x00000004 +#define MH_DEBUG_REG40_ROQ_VALID_q_5_MASK 0x00000008 +#define MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK 0x00000010 +#define MH_DEBUG_REG40_ROQ_ADDR_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG40_MASK \ + (MH_DEBUG_REG40_TC_MH_send_MASK | \ + MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG40_ROQ_MARK_q_5_MASK | \ + MH_DEBUG_REG40_ROQ_VALID_q_5_MASK | \ + MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK | \ + MH_DEBUG_REG40_ROQ_ADDR_5_MASK) + +#define MH_DEBUG_REG40(tc_mh_send, tc_roq_rtr_q, roq_mark_q_5, roq_valid_q_5, same_row_bank_q_5, roq_addr_5) \ + ((tc_mh_send << MH_DEBUG_REG40_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_5 << MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT) | \ + (roq_valid_q_5 << MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT) | \ + (same_row_bank_q_5 << MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT) | \ + (roq_addr_5 << MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT)) + +#define MH_DEBUG_REG40_GET_TC_MH_send(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_TC_MH_send_MASK) >> MH_DEBUG_REG40_TC_MH_send_SHIFT) +#define MH_DEBUG_REG40_GET_TC_ROQ_RTR_q(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG40_GET_ROQ_MARK_q_5(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_ROQ_MARK_q_5_MASK) >> MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT) +#define MH_DEBUG_REG40_GET_ROQ_VALID_q_5(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_ROQ_VALID_q_5_MASK) >> MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT) +#define MH_DEBUG_REG40_GET_SAME_ROW_BANK_q_5(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK) >> MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT) +#define MH_DEBUG_REG40_GET_ROQ_ADDR_5(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_ROQ_ADDR_5_MASK) >> MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT) + +#define MH_DEBUG_REG40_SET_TC_MH_send(mh_debug_reg40_reg, tc_mh_send) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG40_TC_MH_send_SHIFT) +#define MH_DEBUG_REG40_SET_TC_ROQ_RTR_q(mh_debug_reg40_reg, tc_roq_rtr_q) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG40_SET_ROQ_MARK_q_5(mh_debug_reg40_reg, roq_mark_q_5) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ROQ_MARK_q_5_MASK) | (roq_mark_q_5 << MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT) +#define MH_DEBUG_REG40_SET_ROQ_VALID_q_5(mh_debug_reg40_reg, roq_valid_q_5) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ROQ_VALID_q_5_MASK) | (roq_valid_q_5 << MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT) +#define MH_DEBUG_REG40_SET_SAME_ROW_BANK_q_5(mh_debug_reg40_reg, same_row_bank_q_5) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK) | (same_row_bank_q_5 << MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT) +#define MH_DEBUG_REG40_SET_ROQ_ADDR_5(mh_debug_reg40_reg, roq_addr_5) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ROQ_ADDR_5_MASK) | (roq_addr_5 << MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg40_t { + unsigned int tc_mh_send : MH_DEBUG_REG40_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG40_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_5 : MH_DEBUG_REG40_ROQ_MARK_q_5_SIZE; + unsigned int roq_valid_q_5 : MH_DEBUG_REG40_ROQ_VALID_q_5_SIZE; + unsigned int same_row_bank_q_5 : MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SIZE; + unsigned int roq_addr_5 : MH_DEBUG_REG40_ROQ_ADDR_5_SIZE; + } mh_debug_reg40_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg40_t { + unsigned int roq_addr_5 : MH_DEBUG_REG40_ROQ_ADDR_5_SIZE; + unsigned int same_row_bank_q_5 : MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SIZE; + unsigned int roq_valid_q_5 : MH_DEBUG_REG40_ROQ_VALID_q_5_SIZE; + unsigned int roq_mark_q_5 : MH_DEBUG_REG40_ROQ_MARK_q_5_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG40_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG40_TC_MH_send_SIZE; + } mh_debug_reg40_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg40_t f; +} mh_debug_reg40_u; + + +/* + * MH_DEBUG_REG41 struct + */ + +#define MH_DEBUG_REG41_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG41_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG41_ROQ_MARK_q_6_SIZE 1 +#define MH_DEBUG_REG41_ROQ_VALID_q_6_SIZE 1 +#define MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SIZE 1 +#define MH_DEBUG_REG41_ROQ_ADDR_6_SIZE 27 + +#define MH_DEBUG_REG41_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT 2 +#define MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT 3 +#define MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT 4 +#define MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT 5 + +#define MH_DEBUG_REG41_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG41_ROQ_MARK_q_6_MASK 0x00000004 +#define MH_DEBUG_REG41_ROQ_VALID_q_6_MASK 0x00000008 +#define MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK 0x00000010 +#define MH_DEBUG_REG41_ROQ_ADDR_6_MASK 0xffffffe0 + +#define MH_DEBUG_REG41_MASK \ + (MH_DEBUG_REG41_TC_MH_send_MASK | \ + MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG41_ROQ_MARK_q_6_MASK | \ + MH_DEBUG_REG41_ROQ_VALID_q_6_MASK | \ + MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK | \ + MH_DEBUG_REG41_ROQ_ADDR_6_MASK) + +#define MH_DEBUG_REG41(tc_mh_send, tc_roq_rtr_q, roq_mark_q_6, roq_valid_q_6, same_row_bank_q_6, roq_addr_6) \ + ((tc_mh_send << MH_DEBUG_REG41_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_6 << MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT) | \ + (roq_valid_q_6 << MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT) | \ + (same_row_bank_q_6 << MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT) | \ + (roq_addr_6 << MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT)) + +#define MH_DEBUG_REG41_GET_TC_MH_send(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_TC_MH_send_MASK) >> MH_DEBUG_REG41_TC_MH_send_SHIFT) +#define MH_DEBUG_REG41_GET_TC_ROQ_RTR_q(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG41_GET_ROQ_MARK_q_6(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_ROQ_MARK_q_6_MASK) >> MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT) +#define MH_DEBUG_REG41_GET_ROQ_VALID_q_6(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_ROQ_VALID_q_6_MASK) >> MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT) +#define MH_DEBUG_REG41_GET_SAME_ROW_BANK_q_6(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK) >> MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT) +#define MH_DEBUG_REG41_GET_ROQ_ADDR_6(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_ROQ_ADDR_6_MASK) >> MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT) + +#define MH_DEBUG_REG41_SET_TC_MH_send(mh_debug_reg41_reg, tc_mh_send) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG41_TC_MH_send_SHIFT) +#define MH_DEBUG_REG41_SET_TC_ROQ_RTR_q(mh_debug_reg41_reg, tc_roq_rtr_q) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG41_SET_ROQ_MARK_q_6(mh_debug_reg41_reg, roq_mark_q_6) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_ROQ_MARK_q_6_MASK) | (roq_mark_q_6 << MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT) +#define MH_DEBUG_REG41_SET_ROQ_VALID_q_6(mh_debug_reg41_reg, roq_valid_q_6) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_ROQ_VALID_q_6_MASK) | (roq_valid_q_6 << MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT) +#define MH_DEBUG_REG41_SET_SAME_ROW_BANK_q_6(mh_debug_reg41_reg, same_row_bank_q_6) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK) | (same_row_bank_q_6 << MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT) +#define MH_DEBUG_REG41_SET_ROQ_ADDR_6(mh_debug_reg41_reg, roq_addr_6) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_ROQ_ADDR_6_MASK) | (roq_addr_6 << MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg41_t { + unsigned int tc_mh_send : MH_DEBUG_REG41_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG41_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_6 : MH_DEBUG_REG41_ROQ_MARK_q_6_SIZE; + unsigned int roq_valid_q_6 : MH_DEBUG_REG41_ROQ_VALID_q_6_SIZE; + unsigned int same_row_bank_q_6 : MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SIZE; + unsigned int roq_addr_6 : MH_DEBUG_REG41_ROQ_ADDR_6_SIZE; + } mh_debug_reg41_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg41_t { + unsigned int roq_addr_6 : MH_DEBUG_REG41_ROQ_ADDR_6_SIZE; + unsigned int same_row_bank_q_6 : MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SIZE; + unsigned int roq_valid_q_6 : MH_DEBUG_REG41_ROQ_VALID_q_6_SIZE; + unsigned int roq_mark_q_6 : MH_DEBUG_REG41_ROQ_MARK_q_6_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG41_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG41_TC_MH_send_SIZE; + } mh_debug_reg41_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg41_t f; +} mh_debug_reg41_u; + + +/* + * MH_DEBUG_REG42 struct + */ + +#define MH_DEBUG_REG42_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG42_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG42_ROQ_MARK_q_7_SIZE 1 +#define MH_DEBUG_REG42_ROQ_VALID_q_7_SIZE 1 +#define MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SIZE 1 +#define MH_DEBUG_REG42_ROQ_ADDR_7_SIZE 27 + +#define MH_DEBUG_REG42_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT 2 +#define MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT 3 +#define MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT 4 +#define MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT 5 + +#define MH_DEBUG_REG42_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG42_ROQ_MARK_q_7_MASK 0x00000004 +#define MH_DEBUG_REG42_ROQ_VALID_q_7_MASK 0x00000008 +#define MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK 0x00000010 +#define MH_DEBUG_REG42_ROQ_ADDR_7_MASK 0xffffffe0 + +#define MH_DEBUG_REG42_MASK \ + (MH_DEBUG_REG42_TC_MH_send_MASK | \ + MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG42_ROQ_MARK_q_7_MASK | \ + MH_DEBUG_REG42_ROQ_VALID_q_7_MASK | \ + MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK | \ + MH_DEBUG_REG42_ROQ_ADDR_7_MASK) + +#define MH_DEBUG_REG42(tc_mh_send, tc_roq_rtr_q, roq_mark_q_7, roq_valid_q_7, same_row_bank_q_7, roq_addr_7) \ + ((tc_mh_send << MH_DEBUG_REG42_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_7 << MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT) | \ + (roq_valid_q_7 << MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT) | \ + (same_row_bank_q_7 << MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT) | \ + (roq_addr_7 << MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT)) + +#define MH_DEBUG_REG42_GET_TC_MH_send(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_TC_MH_send_MASK) >> MH_DEBUG_REG42_TC_MH_send_SHIFT) +#define MH_DEBUG_REG42_GET_TC_ROQ_RTR_q(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG42_GET_ROQ_MARK_q_7(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_ROQ_MARK_q_7_MASK) >> MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT) +#define MH_DEBUG_REG42_GET_ROQ_VALID_q_7(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_ROQ_VALID_q_7_MASK) >> MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT) +#define MH_DEBUG_REG42_GET_SAME_ROW_BANK_q_7(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK) >> MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT) +#define MH_DEBUG_REG42_GET_ROQ_ADDR_7(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_ROQ_ADDR_7_MASK) >> MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT) + +#define MH_DEBUG_REG42_SET_TC_MH_send(mh_debug_reg42_reg, tc_mh_send) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG42_TC_MH_send_SHIFT) +#define MH_DEBUG_REG42_SET_TC_ROQ_RTR_q(mh_debug_reg42_reg, tc_roq_rtr_q) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG42_SET_ROQ_MARK_q_7(mh_debug_reg42_reg, roq_mark_q_7) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ROQ_MARK_q_7_MASK) | (roq_mark_q_7 << MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT) +#define MH_DEBUG_REG42_SET_ROQ_VALID_q_7(mh_debug_reg42_reg, roq_valid_q_7) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ROQ_VALID_q_7_MASK) | (roq_valid_q_7 << MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT) +#define MH_DEBUG_REG42_SET_SAME_ROW_BANK_q_7(mh_debug_reg42_reg, same_row_bank_q_7) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK) | (same_row_bank_q_7 << MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT) +#define MH_DEBUG_REG42_SET_ROQ_ADDR_7(mh_debug_reg42_reg, roq_addr_7) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ROQ_ADDR_7_MASK) | (roq_addr_7 << MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg42_t { + unsigned int tc_mh_send : MH_DEBUG_REG42_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG42_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_7 : MH_DEBUG_REG42_ROQ_MARK_q_7_SIZE; + unsigned int roq_valid_q_7 : MH_DEBUG_REG42_ROQ_VALID_q_7_SIZE; + unsigned int same_row_bank_q_7 : MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SIZE; + unsigned int roq_addr_7 : MH_DEBUG_REG42_ROQ_ADDR_7_SIZE; + } mh_debug_reg42_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg42_t { + unsigned int roq_addr_7 : MH_DEBUG_REG42_ROQ_ADDR_7_SIZE; + unsigned int same_row_bank_q_7 : MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SIZE; + unsigned int roq_valid_q_7 : MH_DEBUG_REG42_ROQ_VALID_q_7_SIZE; + unsigned int roq_mark_q_7 : MH_DEBUG_REG42_ROQ_MARK_q_7_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG42_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG42_TC_MH_send_SIZE; + } mh_debug_reg42_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg42_t f; +} mh_debug_reg42_u; + + +/* + * MH_DEBUG_REG43 struct + */ + +#define MH_DEBUG_REG43_ARB_REG_WE_q_SIZE 1 +#define MH_DEBUG_REG43_ARB_WE_SIZE 1 +#define MH_DEBUG_REG43_ARB_REG_VALID_q_SIZE 1 +#define MH_DEBUG_REG43_ARB_RTR_q_SIZE 1 +#define MH_DEBUG_REG43_ARB_REG_RTR_SIZE 1 +#define MH_DEBUG_REG43_WDAT_BURST_RTR_SIZE 1 +#define MH_DEBUG_REG43_MMU_RTR_SIZE 1 +#define MH_DEBUG_REG43_ARB_ID_q_SIZE 3 +#define MH_DEBUG_REG43_ARB_WRITE_q_SIZE 1 +#define MH_DEBUG_REG43_ARB_BLEN_q_SIZE 1 +#define MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SIZE 1 +#define MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SIZE 3 +#define MH_DEBUG_REG43_MMU_WE_SIZE 1 +#define MH_DEBUG_REG43_ARQ_RTR_SIZE 1 +#define MH_DEBUG_REG43_MMU_ID_SIZE 3 +#define MH_DEBUG_REG43_MMU_WRITE_SIZE 1 +#define MH_DEBUG_REG43_MMU_BLEN_SIZE 1 +#define MH_DEBUG_REG43_WBURST_IP_q_SIZE 1 +#define MH_DEBUG_REG43_WDAT_REG_WE_q_SIZE 1 +#define MH_DEBUG_REG43_WDB_WE_SIZE 1 +#define MH_DEBUG_REG43_WDB_RTR_SKID_4_SIZE 1 +#define MH_DEBUG_REG43_WDB_RTR_SKID_3_SIZE 1 + +#define MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT 0 +#define MH_DEBUG_REG43_ARB_WE_SHIFT 1 +#define MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT 2 +#define MH_DEBUG_REG43_ARB_RTR_q_SHIFT 3 +#define MH_DEBUG_REG43_ARB_REG_RTR_SHIFT 4 +#define MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT 5 +#define MH_DEBUG_REG43_MMU_RTR_SHIFT 6 +#define MH_DEBUG_REG43_ARB_ID_q_SHIFT 7 +#define MH_DEBUG_REG43_ARB_WRITE_q_SHIFT 10 +#define MH_DEBUG_REG43_ARB_BLEN_q_SHIFT 11 +#define MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT 12 +#define MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT 13 +#define MH_DEBUG_REG43_MMU_WE_SHIFT 16 +#define MH_DEBUG_REG43_ARQ_RTR_SHIFT 17 +#define MH_DEBUG_REG43_MMU_ID_SHIFT 18 +#define MH_DEBUG_REG43_MMU_WRITE_SHIFT 21 +#define MH_DEBUG_REG43_MMU_BLEN_SHIFT 22 +#define MH_DEBUG_REG43_WBURST_IP_q_SHIFT 23 +#define MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT 24 +#define MH_DEBUG_REG43_WDB_WE_SHIFT 25 +#define MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT 26 +#define MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT 27 + +#define MH_DEBUG_REG43_ARB_REG_WE_q_MASK 0x00000001 +#define MH_DEBUG_REG43_ARB_WE_MASK 0x00000002 +#define MH_DEBUG_REG43_ARB_REG_VALID_q_MASK 0x00000004 +#define MH_DEBUG_REG43_ARB_RTR_q_MASK 0x00000008 +#define MH_DEBUG_REG43_ARB_REG_RTR_MASK 0x00000010 +#define MH_DEBUG_REG43_WDAT_BURST_RTR_MASK 0x00000020 +#define MH_DEBUG_REG43_MMU_RTR_MASK 0x00000040 +#define MH_DEBUG_REG43_ARB_ID_q_MASK 0x00000380 +#define MH_DEBUG_REG43_ARB_WRITE_q_MASK 0x00000400 +#define MH_DEBUG_REG43_ARB_BLEN_q_MASK 0x00000800 +#define MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK 0x00001000 +#define MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK 0x0000e000 +#define MH_DEBUG_REG43_MMU_WE_MASK 0x00010000 +#define MH_DEBUG_REG43_ARQ_RTR_MASK 0x00020000 +#define MH_DEBUG_REG43_MMU_ID_MASK 0x001c0000 +#define MH_DEBUG_REG43_MMU_WRITE_MASK 0x00200000 +#define MH_DEBUG_REG43_MMU_BLEN_MASK 0x00400000 +#define MH_DEBUG_REG43_WBURST_IP_q_MASK 0x00800000 +#define MH_DEBUG_REG43_WDAT_REG_WE_q_MASK 0x01000000 +#define MH_DEBUG_REG43_WDB_WE_MASK 0x02000000 +#define MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK 0x04000000 +#define MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK 0x08000000 + +#define MH_DEBUG_REG43_MASK \ + (MH_DEBUG_REG43_ARB_REG_WE_q_MASK | \ + MH_DEBUG_REG43_ARB_WE_MASK | \ + MH_DEBUG_REG43_ARB_REG_VALID_q_MASK | \ + MH_DEBUG_REG43_ARB_RTR_q_MASK | \ + MH_DEBUG_REG43_ARB_REG_RTR_MASK | \ + MH_DEBUG_REG43_WDAT_BURST_RTR_MASK | \ + MH_DEBUG_REG43_MMU_RTR_MASK | \ + MH_DEBUG_REG43_ARB_ID_q_MASK | \ + MH_DEBUG_REG43_ARB_WRITE_q_MASK | \ + MH_DEBUG_REG43_ARB_BLEN_q_MASK | \ + MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK | \ + MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK | \ + MH_DEBUG_REG43_MMU_WE_MASK | \ + MH_DEBUG_REG43_ARQ_RTR_MASK | \ + MH_DEBUG_REG43_MMU_ID_MASK | \ + MH_DEBUG_REG43_MMU_WRITE_MASK | \ + MH_DEBUG_REG43_MMU_BLEN_MASK | \ + MH_DEBUG_REG43_WBURST_IP_q_MASK | \ + MH_DEBUG_REG43_WDAT_REG_WE_q_MASK | \ + MH_DEBUG_REG43_WDB_WE_MASK | \ + MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK | \ + MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK) + +#define MH_DEBUG_REG43(arb_reg_we_q, arb_we, arb_reg_valid_q, arb_rtr_q, arb_reg_rtr, wdat_burst_rtr, mmu_rtr, arb_id_q, arb_write_q, arb_blen_q, arq_ctrl_empty, arq_fifo_cnt_q, mmu_we, arq_rtr, mmu_id, mmu_write, mmu_blen, wburst_ip_q, wdat_reg_we_q, wdb_we, wdb_rtr_skid_4, wdb_rtr_skid_3) \ + ((arb_reg_we_q << MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT) | \ + (arb_we << MH_DEBUG_REG43_ARB_WE_SHIFT) | \ + (arb_reg_valid_q << MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT) | \ + (arb_rtr_q << MH_DEBUG_REG43_ARB_RTR_q_SHIFT) | \ + (arb_reg_rtr << MH_DEBUG_REG43_ARB_REG_RTR_SHIFT) | \ + (wdat_burst_rtr << MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT) | \ + (mmu_rtr << MH_DEBUG_REG43_MMU_RTR_SHIFT) | \ + (arb_id_q << MH_DEBUG_REG43_ARB_ID_q_SHIFT) | \ + (arb_write_q << MH_DEBUG_REG43_ARB_WRITE_q_SHIFT) | \ + (arb_blen_q << MH_DEBUG_REG43_ARB_BLEN_q_SHIFT) | \ + (arq_ctrl_empty << MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT) | \ + (arq_fifo_cnt_q << MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT) | \ + (mmu_we << MH_DEBUG_REG43_MMU_WE_SHIFT) | \ + (arq_rtr << MH_DEBUG_REG43_ARQ_RTR_SHIFT) | \ + (mmu_id << MH_DEBUG_REG43_MMU_ID_SHIFT) | \ + (mmu_write << MH_DEBUG_REG43_MMU_WRITE_SHIFT) | \ + (mmu_blen << MH_DEBUG_REG43_MMU_BLEN_SHIFT) | \ + (wburst_ip_q << MH_DEBUG_REG43_WBURST_IP_q_SHIFT) | \ + (wdat_reg_we_q << MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT) | \ + (wdb_we << MH_DEBUG_REG43_WDB_WE_SHIFT) | \ + (wdb_rtr_skid_4 << MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT) | \ + (wdb_rtr_skid_3 << MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT)) + +#define MH_DEBUG_REG43_GET_ARB_REG_WE_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_REG_WE_q_MASK) >> MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT) +#define MH_DEBUG_REG43_GET_ARB_WE(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_WE_MASK) >> MH_DEBUG_REG43_ARB_WE_SHIFT) +#define MH_DEBUG_REG43_GET_ARB_REG_VALID_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_REG_VALID_q_MASK) >> MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT) +#define MH_DEBUG_REG43_GET_ARB_RTR_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_RTR_q_MASK) >> MH_DEBUG_REG43_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG43_GET_ARB_REG_RTR(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_REG_RTR_MASK) >> MH_DEBUG_REG43_ARB_REG_RTR_SHIFT) +#define MH_DEBUG_REG43_GET_WDAT_BURST_RTR(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_WDAT_BURST_RTR_MASK) >> MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT) +#define MH_DEBUG_REG43_GET_MMU_RTR(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_RTR_MASK) >> MH_DEBUG_REG43_MMU_RTR_SHIFT) +#define MH_DEBUG_REG43_GET_ARB_ID_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_ID_q_MASK) >> MH_DEBUG_REG43_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG43_GET_ARB_WRITE_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_WRITE_q_MASK) >> MH_DEBUG_REG43_ARB_WRITE_q_SHIFT) +#define MH_DEBUG_REG43_GET_ARB_BLEN_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_BLEN_q_MASK) >> MH_DEBUG_REG43_ARB_BLEN_q_SHIFT) +#define MH_DEBUG_REG43_GET_ARQ_CTRL_EMPTY(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK) >> MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG43_GET_ARQ_FIFO_CNT_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK) >> MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT) +#define MH_DEBUG_REG43_GET_MMU_WE(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_WE_MASK) >> MH_DEBUG_REG43_MMU_WE_SHIFT) +#define MH_DEBUG_REG43_GET_ARQ_RTR(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARQ_RTR_MASK) >> MH_DEBUG_REG43_ARQ_RTR_SHIFT) +#define MH_DEBUG_REG43_GET_MMU_ID(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_ID_MASK) >> MH_DEBUG_REG43_MMU_ID_SHIFT) +#define MH_DEBUG_REG43_GET_MMU_WRITE(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_WRITE_MASK) >> MH_DEBUG_REG43_MMU_WRITE_SHIFT) +#define MH_DEBUG_REG43_GET_MMU_BLEN(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_BLEN_MASK) >> MH_DEBUG_REG43_MMU_BLEN_SHIFT) +#define MH_DEBUG_REG43_GET_WBURST_IP_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_WBURST_IP_q_MASK) >> MH_DEBUG_REG43_WBURST_IP_q_SHIFT) +#define MH_DEBUG_REG43_GET_WDAT_REG_WE_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_WDAT_REG_WE_q_MASK) >> MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT) +#define MH_DEBUG_REG43_GET_WDB_WE(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_WDB_WE_MASK) >> MH_DEBUG_REG43_WDB_WE_SHIFT) +#define MH_DEBUG_REG43_GET_WDB_RTR_SKID_4(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK) >> MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT) +#define MH_DEBUG_REG43_GET_WDB_RTR_SKID_3(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK) >> MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT) + +#define MH_DEBUG_REG43_SET_ARB_REG_WE_q(mh_debug_reg43_reg, arb_reg_we_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_REG_WE_q_MASK) | (arb_reg_we_q << MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT) +#define MH_DEBUG_REG43_SET_ARB_WE(mh_debug_reg43_reg, arb_we) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG43_ARB_WE_SHIFT) +#define MH_DEBUG_REG43_SET_ARB_REG_VALID_q(mh_debug_reg43_reg, arb_reg_valid_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_REG_VALID_q_MASK) | (arb_reg_valid_q << MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT) +#define MH_DEBUG_REG43_SET_ARB_RTR_q(mh_debug_reg43_reg, arb_rtr_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG43_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG43_SET_ARB_REG_RTR(mh_debug_reg43_reg, arb_reg_rtr) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_REG_RTR_MASK) | (arb_reg_rtr << MH_DEBUG_REG43_ARB_REG_RTR_SHIFT) +#define MH_DEBUG_REG43_SET_WDAT_BURST_RTR(mh_debug_reg43_reg, wdat_burst_rtr) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDAT_BURST_RTR_MASK) | (wdat_burst_rtr << MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT) +#define MH_DEBUG_REG43_SET_MMU_RTR(mh_debug_reg43_reg, mmu_rtr) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_RTR_MASK) | (mmu_rtr << MH_DEBUG_REG43_MMU_RTR_SHIFT) +#define MH_DEBUG_REG43_SET_ARB_ID_q(mh_debug_reg43_reg, arb_id_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG43_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG43_SET_ARB_WRITE_q(mh_debug_reg43_reg, arb_write_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_WRITE_q_MASK) | (arb_write_q << MH_DEBUG_REG43_ARB_WRITE_q_SHIFT) +#define MH_DEBUG_REG43_SET_ARB_BLEN_q(mh_debug_reg43_reg, arb_blen_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_BLEN_q_MASK) | (arb_blen_q << MH_DEBUG_REG43_ARB_BLEN_q_SHIFT) +#define MH_DEBUG_REG43_SET_ARQ_CTRL_EMPTY(mh_debug_reg43_reg, arq_ctrl_empty) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK) | (arq_ctrl_empty << MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG43_SET_ARQ_FIFO_CNT_q(mh_debug_reg43_reg, arq_fifo_cnt_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK) | (arq_fifo_cnt_q << MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT) +#define MH_DEBUG_REG43_SET_MMU_WE(mh_debug_reg43_reg, mmu_we) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG43_MMU_WE_SHIFT) +#define MH_DEBUG_REG43_SET_ARQ_RTR(mh_debug_reg43_reg, arq_rtr) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARQ_RTR_MASK) | (arq_rtr << MH_DEBUG_REG43_ARQ_RTR_SHIFT) +#define MH_DEBUG_REG43_SET_MMU_ID(mh_debug_reg43_reg, mmu_id) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_ID_MASK) | (mmu_id << MH_DEBUG_REG43_MMU_ID_SHIFT) +#define MH_DEBUG_REG43_SET_MMU_WRITE(mh_debug_reg43_reg, mmu_write) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_WRITE_MASK) | (mmu_write << MH_DEBUG_REG43_MMU_WRITE_SHIFT) +#define MH_DEBUG_REG43_SET_MMU_BLEN(mh_debug_reg43_reg, mmu_blen) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_BLEN_MASK) | (mmu_blen << MH_DEBUG_REG43_MMU_BLEN_SHIFT) +#define MH_DEBUG_REG43_SET_WBURST_IP_q(mh_debug_reg43_reg, wburst_ip_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WBURST_IP_q_MASK) | (wburst_ip_q << MH_DEBUG_REG43_WBURST_IP_q_SHIFT) +#define MH_DEBUG_REG43_SET_WDAT_REG_WE_q(mh_debug_reg43_reg, wdat_reg_we_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDAT_REG_WE_q_MASK) | (wdat_reg_we_q << MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT) +#define MH_DEBUG_REG43_SET_WDB_WE(mh_debug_reg43_reg, wdb_we) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDB_WE_MASK) | (wdb_we << MH_DEBUG_REG43_WDB_WE_SHIFT) +#define MH_DEBUG_REG43_SET_WDB_RTR_SKID_4(mh_debug_reg43_reg, wdb_rtr_skid_4) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK) | (wdb_rtr_skid_4 << MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT) +#define MH_DEBUG_REG43_SET_WDB_RTR_SKID_3(mh_debug_reg43_reg, wdb_rtr_skid_3) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK) | (wdb_rtr_skid_3 << MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg43_t { + unsigned int arb_reg_we_q : MH_DEBUG_REG43_ARB_REG_WE_q_SIZE; + unsigned int arb_we : MH_DEBUG_REG43_ARB_WE_SIZE; + unsigned int arb_reg_valid_q : MH_DEBUG_REG43_ARB_REG_VALID_q_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG43_ARB_RTR_q_SIZE; + unsigned int arb_reg_rtr : MH_DEBUG_REG43_ARB_REG_RTR_SIZE; + unsigned int wdat_burst_rtr : MH_DEBUG_REG43_WDAT_BURST_RTR_SIZE; + unsigned int mmu_rtr : MH_DEBUG_REG43_MMU_RTR_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG43_ARB_ID_q_SIZE; + unsigned int arb_write_q : MH_DEBUG_REG43_ARB_WRITE_q_SIZE; + unsigned int arb_blen_q : MH_DEBUG_REG43_ARB_BLEN_q_SIZE; + unsigned int arq_ctrl_empty : MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SIZE; + unsigned int arq_fifo_cnt_q : MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SIZE; + unsigned int mmu_we : MH_DEBUG_REG43_MMU_WE_SIZE; + unsigned int arq_rtr : MH_DEBUG_REG43_ARQ_RTR_SIZE; + unsigned int mmu_id : MH_DEBUG_REG43_MMU_ID_SIZE; + unsigned int mmu_write : MH_DEBUG_REG43_MMU_WRITE_SIZE; + unsigned int mmu_blen : MH_DEBUG_REG43_MMU_BLEN_SIZE; + unsigned int wburst_ip_q : MH_DEBUG_REG43_WBURST_IP_q_SIZE; + unsigned int wdat_reg_we_q : MH_DEBUG_REG43_WDAT_REG_WE_q_SIZE; + unsigned int wdb_we : MH_DEBUG_REG43_WDB_WE_SIZE; + unsigned int wdb_rtr_skid_4 : MH_DEBUG_REG43_WDB_RTR_SKID_4_SIZE; + unsigned int wdb_rtr_skid_3 : MH_DEBUG_REG43_WDB_RTR_SKID_3_SIZE; + unsigned int : 4; + } mh_debug_reg43_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg43_t { + unsigned int : 4; + unsigned int wdb_rtr_skid_3 : MH_DEBUG_REG43_WDB_RTR_SKID_3_SIZE; + unsigned int wdb_rtr_skid_4 : MH_DEBUG_REG43_WDB_RTR_SKID_4_SIZE; + unsigned int wdb_we : MH_DEBUG_REG43_WDB_WE_SIZE; + unsigned int wdat_reg_we_q : MH_DEBUG_REG43_WDAT_REG_WE_q_SIZE; + unsigned int wburst_ip_q : MH_DEBUG_REG43_WBURST_IP_q_SIZE; + unsigned int mmu_blen : MH_DEBUG_REG43_MMU_BLEN_SIZE; + unsigned int mmu_write : MH_DEBUG_REG43_MMU_WRITE_SIZE; + unsigned int mmu_id : MH_DEBUG_REG43_MMU_ID_SIZE; + unsigned int arq_rtr : MH_DEBUG_REG43_ARQ_RTR_SIZE; + unsigned int mmu_we : MH_DEBUG_REG43_MMU_WE_SIZE; + unsigned int arq_fifo_cnt_q : MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SIZE; + unsigned int arq_ctrl_empty : MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SIZE; + unsigned int arb_blen_q : MH_DEBUG_REG43_ARB_BLEN_q_SIZE; + unsigned int arb_write_q : MH_DEBUG_REG43_ARB_WRITE_q_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG43_ARB_ID_q_SIZE; + unsigned int mmu_rtr : MH_DEBUG_REG43_MMU_RTR_SIZE; + unsigned int wdat_burst_rtr : MH_DEBUG_REG43_WDAT_BURST_RTR_SIZE; + unsigned int arb_reg_rtr : MH_DEBUG_REG43_ARB_REG_RTR_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG43_ARB_RTR_q_SIZE; + unsigned int arb_reg_valid_q : MH_DEBUG_REG43_ARB_REG_VALID_q_SIZE; + unsigned int arb_we : MH_DEBUG_REG43_ARB_WE_SIZE; + unsigned int arb_reg_we_q : MH_DEBUG_REG43_ARB_REG_WE_q_SIZE; + } mh_debug_reg43_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg43_t f; +} mh_debug_reg43_u; + + +/* + * MH_DEBUG_REG44 struct + */ + +#define MH_DEBUG_REG44_ARB_WE_SIZE 1 +#define MH_DEBUG_REG44_ARB_ID_q_SIZE 3 +#define MH_DEBUG_REG44_ARB_VAD_q_SIZE 28 + +#define MH_DEBUG_REG44_ARB_WE_SHIFT 0 +#define MH_DEBUG_REG44_ARB_ID_q_SHIFT 1 +#define MH_DEBUG_REG44_ARB_VAD_q_SHIFT 4 + +#define MH_DEBUG_REG44_ARB_WE_MASK 0x00000001 +#define MH_DEBUG_REG44_ARB_ID_q_MASK 0x0000000e +#define MH_DEBUG_REG44_ARB_VAD_q_MASK 0xfffffff0 + +#define MH_DEBUG_REG44_MASK \ + (MH_DEBUG_REG44_ARB_WE_MASK | \ + MH_DEBUG_REG44_ARB_ID_q_MASK | \ + MH_DEBUG_REG44_ARB_VAD_q_MASK) + +#define MH_DEBUG_REG44(arb_we, arb_id_q, arb_vad_q) \ + ((arb_we << MH_DEBUG_REG44_ARB_WE_SHIFT) | \ + (arb_id_q << MH_DEBUG_REG44_ARB_ID_q_SHIFT) | \ + (arb_vad_q << MH_DEBUG_REG44_ARB_VAD_q_SHIFT)) + +#define MH_DEBUG_REG44_GET_ARB_WE(mh_debug_reg44) \ + ((mh_debug_reg44 & MH_DEBUG_REG44_ARB_WE_MASK) >> MH_DEBUG_REG44_ARB_WE_SHIFT) +#define MH_DEBUG_REG44_GET_ARB_ID_q(mh_debug_reg44) \ + ((mh_debug_reg44 & MH_DEBUG_REG44_ARB_ID_q_MASK) >> MH_DEBUG_REG44_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG44_GET_ARB_VAD_q(mh_debug_reg44) \ + ((mh_debug_reg44 & MH_DEBUG_REG44_ARB_VAD_q_MASK) >> MH_DEBUG_REG44_ARB_VAD_q_SHIFT) + +#define MH_DEBUG_REG44_SET_ARB_WE(mh_debug_reg44_reg, arb_we) \ + mh_debug_reg44_reg = (mh_debug_reg44_reg & ~MH_DEBUG_REG44_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG44_ARB_WE_SHIFT) +#define MH_DEBUG_REG44_SET_ARB_ID_q(mh_debug_reg44_reg, arb_id_q) \ + mh_debug_reg44_reg = (mh_debug_reg44_reg & ~MH_DEBUG_REG44_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG44_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG44_SET_ARB_VAD_q(mh_debug_reg44_reg, arb_vad_q) \ + mh_debug_reg44_reg = (mh_debug_reg44_reg & ~MH_DEBUG_REG44_ARB_VAD_q_MASK) | (arb_vad_q << MH_DEBUG_REG44_ARB_VAD_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg44_t { + unsigned int arb_we : MH_DEBUG_REG44_ARB_WE_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG44_ARB_ID_q_SIZE; + unsigned int arb_vad_q : MH_DEBUG_REG44_ARB_VAD_q_SIZE; + } mh_debug_reg44_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg44_t { + unsigned int arb_vad_q : MH_DEBUG_REG44_ARB_VAD_q_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG44_ARB_ID_q_SIZE; + unsigned int arb_we : MH_DEBUG_REG44_ARB_WE_SIZE; + } mh_debug_reg44_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg44_t f; +} mh_debug_reg44_u; + + +/* + * MH_DEBUG_REG45 struct + */ + +#define MH_DEBUG_REG45_MMU_WE_SIZE 1 +#define MH_DEBUG_REG45_MMU_ID_SIZE 3 +#define MH_DEBUG_REG45_MMU_PAD_SIZE 28 + +#define MH_DEBUG_REG45_MMU_WE_SHIFT 0 +#define MH_DEBUG_REG45_MMU_ID_SHIFT 1 +#define MH_DEBUG_REG45_MMU_PAD_SHIFT 4 + +#define MH_DEBUG_REG45_MMU_WE_MASK 0x00000001 +#define MH_DEBUG_REG45_MMU_ID_MASK 0x0000000e +#define MH_DEBUG_REG45_MMU_PAD_MASK 0xfffffff0 + +#define MH_DEBUG_REG45_MASK \ + (MH_DEBUG_REG45_MMU_WE_MASK | \ + MH_DEBUG_REG45_MMU_ID_MASK | \ + MH_DEBUG_REG45_MMU_PAD_MASK) + +#define MH_DEBUG_REG45(mmu_we, mmu_id, mmu_pad) \ + ((mmu_we << MH_DEBUG_REG45_MMU_WE_SHIFT) | \ + (mmu_id << MH_DEBUG_REG45_MMU_ID_SHIFT) | \ + (mmu_pad << MH_DEBUG_REG45_MMU_PAD_SHIFT)) + +#define MH_DEBUG_REG45_GET_MMU_WE(mh_debug_reg45) \ + ((mh_debug_reg45 & MH_DEBUG_REG45_MMU_WE_MASK) >> MH_DEBUG_REG45_MMU_WE_SHIFT) +#define MH_DEBUG_REG45_GET_MMU_ID(mh_debug_reg45) \ + ((mh_debug_reg45 & MH_DEBUG_REG45_MMU_ID_MASK) >> MH_DEBUG_REG45_MMU_ID_SHIFT) +#define MH_DEBUG_REG45_GET_MMU_PAD(mh_debug_reg45) \ + ((mh_debug_reg45 & MH_DEBUG_REG45_MMU_PAD_MASK) >> MH_DEBUG_REG45_MMU_PAD_SHIFT) + +#define MH_DEBUG_REG45_SET_MMU_WE(mh_debug_reg45_reg, mmu_we) \ + mh_debug_reg45_reg = (mh_debug_reg45_reg & ~MH_DEBUG_REG45_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG45_MMU_WE_SHIFT) +#define MH_DEBUG_REG45_SET_MMU_ID(mh_debug_reg45_reg, mmu_id) \ + mh_debug_reg45_reg = (mh_debug_reg45_reg & ~MH_DEBUG_REG45_MMU_ID_MASK) | (mmu_id << MH_DEBUG_REG45_MMU_ID_SHIFT) +#define MH_DEBUG_REG45_SET_MMU_PAD(mh_debug_reg45_reg, mmu_pad) \ + mh_debug_reg45_reg = (mh_debug_reg45_reg & ~MH_DEBUG_REG45_MMU_PAD_MASK) | (mmu_pad << MH_DEBUG_REG45_MMU_PAD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg45_t { + unsigned int mmu_we : MH_DEBUG_REG45_MMU_WE_SIZE; + unsigned int mmu_id : MH_DEBUG_REG45_MMU_ID_SIZE; + unsigned int mmu_pad : MH_DEBUG_REG45_MMU_PAD_SIZE; + } mh_debug_reg45_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg45_t { + unsigned int mmu_pad : MH_DEBUG_REG45_MMU_PAD_SIZE; + unsigned int mmu_id : MH_DEBUG_REG45_MMU_ID_SIZE; + unsigned int mmu_we : MH_DEBUG_REG45_MMU_WE_SIZE; + } mh_debug_reg45_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg45_t f; +} mh_debug_reg45_u; + + +/* + * MH_DEBUG_REG46 struct + */ + +#define MH_DEBUG_REG46_WDAT_REG_WE_q_SIZE 1 +#define MH_DEBUG_REG46_WDB_WE_SIZE 1 +#define MH_DEBUG_REG46_WDAT_REG_VALID_q_SIZE 1 +#define MH_DEBUG_REG46_WDB_RTR_SKID_4_SIZE 1 +#define MH_DEBUG_REG46_ARB_WSTRB_q_SIZE 8 +#define MH_DEBUG_REG46_ARB_WLAST_SIZE 1 +#define MH_DEBUG_REG46_WDB_CTRL_EMPTY_SIZE 1 +#define MH_DEBUG_REG46_WDB_FIFO_CNT_q_SIZE 5 +#define MH_DEBUG_REG46_WDC_WDB_RE_q_SIZE 1 +#define MH_DEBUG_REG46_WDB_WDC_WID_SIZE 3 +#define MH_DEBUG_REG46_WDB_WDC_WLAST_SIZE 1 +#define MH_DEBUG_REG46_WDB_WDC_WSTRB_SIZE 8 + +#define MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT 0 +#define MH_DEBUG_REG46_WDB_WE_SHIFT 1 +#define MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT 2 +#define MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT 3 +#define MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT 4 +#define MH_DEBUG_REG46_ARB_WLAST_SHIFT 12 +#define MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT 13 +#define MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT 14 +#define MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT 19 +#define MH_DEBUG_REG46_WDB_WDC_WID_SHIFT 20 +#define MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT 23 +#define MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT 24 + +#define MH_DEBUG_REG46_WDAT_REG_WE_q_MASK 0x00000001 +#define MH_DEBUG_REG46_WDB_WE_MASK 0x00000002 +#define MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK 0x00000004 +#define MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK 0x00000008 +#define MH_DEBUG_REG46_ARB_WSTRB_q_MASK 0x00000ff0 +#define MH_DEBUG_REG46_ARB_WLAST_MASK 0x00001000 +#define MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK 0x00002000 +#define MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK 0x0007c000 +#define MH_DEBUG_REG46_WDC_WDB_RE_q_MASK 0x00080000 +#define MH_DEBUG_REG46_WDB_WDC_WID_MASK 0x00700000 +#define MH_DEBUG_REG46_WDB_WDC_WLAST_MASK 0x00800000 +#define MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK 0xff000000 + +#define MH_DEBUG_REG46_MASK \ + (MH_DEBUG_REG46_WDAT_REG_WE_q_MASK | \ + MH_DEBUG_REG46_WDB_WE_MASK | \ + MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK | \ + MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK | \ + MH_DEBUG_REG46_ARB_WSTRB_q_MASK | \ + MH_DEBUG_REG46_ARB_WLAST_MASK | \ + MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK | \ + MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK | \ + MH_DEBUG_REG46_WDC_WDB_RE_q_MASK | \ + MH_DEBUG_REG46_WDB_WDC_WID_MASK | \ + MH_DEBUG_REG46_WDB_WDC_WLAST_MASK | \ + MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK) + +#define MH_DEBUG_REG46(wdat_reg_we_q, wdb_we, wdat_reg_valid_q, wdb_rtr_skid_4, arb_wstrb_q, arb_wlast, wdb_ctrl_empty, wdb_fifo_cnt_q, wdc_wdb_re_q, wdb_wdc_wid, wdb_wdc_wlast, wdb_wdc_wstrb) \ + ((wdat_reg_we_q << MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT) | \ + (wdb_we << MH_DEBUG_REG46_WDB_WE_SHIFT) | \ + (wdat_reg_valid_q << MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT) | \ + (wdb_rtr_skid_4 << MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT) | \ + (arb_wstrb_q << MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT) | \ + (arb_wlast << MH_DEBUG_REG46_ARB_WLAST_SHIFT) | \ + (wdb_ctrl_empty << MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT) | \ + (wdb_fifo_cnt_q << MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT) | \ + (wdc_wdb_re_q << MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT) | \ + (wdb_wdc_wid << MH_DEBUG_REG46_WDB_WDC_WID_SHIFT) | \ + (wdb_wdc_wlast << MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT) | \ + (wdb_wdc_wstrb << MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT)) + +#define MH_DEBUG_REG46_GET_WDAT_REG_WE_q(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDAT_REG_WE_q_MASK) >> MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT) +#define MH_DEBUG_REG46_GET_WDB_WE(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WE_MASK) >> MH_DEBUG_REG46_WDB_WE_SHIFT) +#define MH_DEBUG_REG46_GET_WDAT_REG_VALID_q(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK) >> MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT) +#define MH_DEBUG_REG46_GET_WDB_RTR_SKID_4(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK) >> MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT) +#define MH_DEBUG_REG46_GET_ARB_WSTRB_q(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_ARB_WSTRB_q_MASK) >> MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT) +#define MH_DEBUG_REG46_GET_ARB_WLAST(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_ARB_WLAST_MASK) >> MH_DEBUG_REG46_ARB_WLAST_SHIFT) +#define MH_DEBUG_REG46_GET_WDB_CTRL_EMPTY(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK) >> MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG46_GET_WDB_FIFO_CNT_q(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK) >> MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT) +#define MH_DEBUG_REG46_GET_WDC_WDB_RE_q(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDC_WDB_RE_q_MASK) >> MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT) +#define MH_DEBUG_REG46_GET_WDB_WDC_WID(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WDC_WID_MASK) >> MH_DEBUG_REG46_WDB_WDC_WID_SHIFT) +#define MH_DEBUG_REG46_GET_WDB_WDC_WLAST(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WDC_WLAST_MASK) >> MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT) +#define MH_DEBUG_REG46_GET_WDB_WDC_WSTRB(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK) >> MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT) + +#define MH_DEBUG_REG46_SET_WDAT_REG_WE_q(mh_debug_reg46_reg, wdat_reg_we_q) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDAT_REG_WE_q_MASK) | (wdat_reg_we_q << MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT) +#define MH_DEBUG_REG46_SET_WDB_WE(mh_debug_reg46_reg, wdb_we) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WE_MASK) | (wdb_we << MH_DEBUG_REG46_WDB_WE_SHIFT) +#define MH_DEBUG_REG46_SET_WDAT_REG_VALID_q(mh_debug_reg46_reg, wdat_reg_valid_q) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK) | (wdat_reg_valid_q << MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT) +#define MH_DEBUG_REG46_SET_WDB_RTR_SKID_4(mh_debug_reg46_reg, wdb_rtr_skid_4) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK) | (wdb_rtr_skid_4 << MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT) +#define MH_DEBUG_REG46_SET_ARB_WSTRB_q(mh_debug_reg46_reg, arb_wstrb_q) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_ARB_WSTRB_q_MASK) | (arb_wstrb_q << MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT) +#define MH_DEBUG_REG46_SET_ARB_WLAST(mh_debug_reg46_reg, arb_wlast) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_ARB_WLAST_MASK) | (arb_wlast << MH_DEBUG_REG46_ARB_WLAST_SHIFT) +#define MH_DEBUG_REG46_SET_WDB_CTRL_EMPTY(mh_debug_reg46_reg, wdb_ctrl_empty) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK) | (wdb_ctrl_empty << MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG46_SET_WDB_FIFO_CNT_q(mh_debug_reg46_reg, wdb_fifo_cnt_q) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK) | (wdb_fifo_cnt_q << MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT) +#define MH_DEBUG_REG46_SET_WDC_WDB_RE_q(mh_debug_reg46_reg, wdc_wdb_re_q) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDC_WDB_RE_q_MASK) | (wdc_wdb_re_q << MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT) +#define MH_DEBUG_REG46_SET_WDB_WDC_WID(mh_debug_reg46_reg, wdb_wdc_wid) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WDC_WID_MASK) | (wdb_wdc_wid << MH_DEBUG_REG46_WDB_WDC_WID_SHIFT) +#define MH_DEBUG_REG46_SET_WDB_WDC_WLAST(mh_debug_reg46_reg, wdb_wdc_wlast) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WDC_WLAST_MASK) | (wdb_wdc_wlast << MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT) +#define MH_DEBUG_REG46_SET_WDB_WDC_WSTRB(mh_debug_reg46_reg, wdb_wdc_wstrb) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK) | (wdb_wdc_wstrb << MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg46_t { + unsigned int wdat_reg_we_q : MH_DEBUG_REG46_WDAT_REG_WE_q_SIZE; + unsigned int wdb_we : MH_DEBUG_REG46_WDB_WE_SIZE; + unsigned int wdat_reg_valid_q : MH_DEBUG_REG46_WDAT_REG_VALID_q_SIZE; + unsigned int wdb_rtr_skid_4 : MH_DEBUG_REG46_WDB_RTR_SKID_4_SIZE; + unsigned int arb_wstrb_q : MH_DEBUG_REG46_ARB_WSTRB_q_SIZE; + unsigned int arb_wlast : MH_DEBUG_REG46_ARB_WLAST_SIZE; + unsigned int wdb_ctrl_empty : MH_DEBUG_REG46_WDB_CTRL_EMPTY_SIZE; + unsigned int wdb_fifo_cnt_q : MH_DEBUG_REG46_WDB_FIFO_CNT_q_SIZE; + unsigned int wdc_wdb_re_q : MH_DEBUG_REG46_WDC_WDB_RE_q_SIZE; + unsigned int wdb_wdc_wid : MH_DEBUG_REG46_WDB_WDC_WID_SIZE; + unsigned int wdb_wdc_wlast : MH_DEBUG_REG46_WDB_WDC_WLAST_SIZE; + unsigned int wdb_wdc_wstrb : MH_DEBUG_REG46_WDB_WDC_WSTRB_SIZE; + } mh_debug_reg46_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg46_t { + unsigned int wdb_wdc_wstrb : MH_DEBUG_REG46_WDB_WDC_WSTRB_SIZE; + unsigned int wdb_wdc_wlast : MH_DEBUG_REG46_WDB_WDC_WLAST_SIZE; + unsigned int wdb_wdc_wid : MH_DEBUG_REG46_WDB_WDC_WID_SIZE; + unsigned int wdc_wdb_re_q : MH_DEBUG_REG46_WDC_WDB_RE_q_SIZE; + unsigned int wdb_fifo_cnt_q : MH_DEBUG_REG46_WDB_FIFO_CNT_q_SIZE; + unsigned int wdb_ctrl_empty : MH_DEBUG_REG46_WDB_CTRL_EMPTY_SIZE; + unsigned int arb_wlast : MH_DEBUG_REG46_ARB_WLAST_SIZE; + unsigned int arb_wstrb_q : MH_DEBUG_REG46_ARB_WSTRB_q_SIZE; + unsigned int wdb_rtr_skid_4 : MH_DEBUG_REG46_WDB_RTR_SKID_4_SIZE; + unsigned int wdat_reg_valid_q : MH_DEBUG_REG46_WDAT_REG_VALID_q_SIZE; + unsigned int wdb_we : MH_DEBUG_REG46_WDB_WE_SIZE; + unsigned int wdat_reg_we_q : MH_DEBUG_REG46_WDAT_REG_WE_q_SIZE; + } mh_debug_reg46_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg46_t f; +} mh_debug_reg46_u; + + +/* + * MH_DEBUG_REG47 struct + */ + +#define MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SIZE 32 + +#define MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT 0 + +#define MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG47_MASK \ + (MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK) + +#define MH_DEBUG_REG47(wdb_wdc_wdata_31_0) \ + ((wdb_wdc_wdata_31_0 << MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT)) + +#define MH_DEBUG_REG47_GET_WDB_WDC_WDATA_31_0(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK) >> MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT) + +#define MH_DEBUG_REG47_SET_WDB_WDC_WDATA_31_0(mh_debug_reg47_reg, wdb_wdc_wdata_31_0) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK) | (wdb_wdc_wdata_31_0 << MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg47_t { + unsigned int wdb_wdc_wdata_31_0 : MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SIZE; + } mh_debug_reg47_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg47_t { + unsigned int wdb_wdc_wdata_31_0 : MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SIZE; + } mh_debug_reg47_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg47_t f; +} mh_debug_reg47_u; + + +/* + * MH_DEBUG_REG48 struct + */ + +#define MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SIZE 32 + +#define MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT 0 + +#define MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG48_MASK \ + (MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK) + +#define MH_DEBUG_REG48(wdb_wdc_wdata_63_32) \ + ((wdb_wdc_wdata_63_32 << MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT)) + +#define MH_DEBUG_REG48_GET_WDB_WDC_WDATA_63_32(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK) >> MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT) + +#define MH_DEBUG_REG48_SET_WDB_WDC_WDATA_63_32(mh_debug_reg48_reg, wdb_wdc_wdata_63_32) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK) | (wdb_wdc_wdata_63_32 << MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg48_t { + unsigned int wdb_wdc_wdata_63_32 : MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SIZE; + } mh_debug_reg48_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg48_t { + unsigned int wdb_wdc_wdata_63_32 : MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SIZE; + } mh_debug_reg48_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg48_t f; +} mh_debug_reg48_u; + + +/* + * MH_DEBUG_REG49 struct + */ + +#define MH_DEBUG_REG49_CTRL_ARC_EMPTY_SIZE 1 +#define MH_DEBUG_REG49_CTRL_RARC_EMPTY_SIZE 1 +#define MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SIZE 1 +#define MH_DEBUG_REG49_ARQ_CTRL_WRITE_SIZE 1 +#define MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SIZE 1 +#define MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SIZE 1 +#define MH_DEBUG_REG49_INFLT_LIMIT_q_SIZE 1 +#define MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SIZE 6 +#define MH_DEBUG_REG49_ARC_CTRL_RE_q_SIZE 1 +#define MH_DEBUG_REG49_RARC_CTRL_RE_q_SIZE 1 +#define MH_DEBUG_REG49_RVALID_q_SIZE 1 +#define MH_DEBUG_REG49_RREADY_q_SIZE 1 +#define MH_DEBUG_REG49_RLAST_q_SIZE 1 +#define MH_DEBUG_REG49_BVALID_q_SIZE 1 +#define MH_DEBUG_REG49_BREADY_q_SIZE 1 + +#define MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT 0 +#define MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT 1 +#define MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT 2 +#define MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT 3 +#define MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT 4 +#define MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT 5 +#define MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT 6 +#define MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT 7 +#define MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT 13 +#define MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT 14 +#define MH_DEBUG_REG49_RVALID_q_SHIFT 15 +#define MH_DEBUG_REG49_RREADY_q_SHIFT 16 +#define MH_DEBUG_REG49_RLAST_q_SHIFT 17 +#define MH_DEBUG_REG49_BVALID_q_SHIFT 18 +#define MH_DEBUG_REG49_BREADY_q_SHIFT 19 + +#define MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK 0x00000001 +#define MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK 0x00000002 +#define MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK 0x00000004 +#define MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK 0x00000008 +#define MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK 0x00000010 +#define MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK 0x00000020 +#define MH_DEBUG_REG49_INFLT_LIMIT_q_MASK 0x00000040 +#define MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK 0x00001f80 +#define MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK 0x00002000 +#define MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK 0x00004000 +#define MH_DEBUG_REG49_RVALID_q_MASK 0x00008000 +#define MH_DEBUG_REG49_RREADY_q_MASK 0x00010000 +#define MH_DEBUG_REG49_RLAST_q_MASK 0x00020000 +#define MH_DEBUG_REG49_BVALID_q_MASK 0x00040000 +#define MH_DEBUG_REG49_BREADY_q_MASK 0x00080000 + +#define MH_DEBUG_REG49_MASK \ + (MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK | \ + MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK | \ + MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK | \ + MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK | \ + MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK | \ + MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK | \ + MH_DEBUG_REG49_INFLT_LIMIT_q_MASK | \ + MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK | \ + MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK | \ + MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK | \ + MH_DEBUG_REG49_RVALID_q_MASK | \ + MH_DEBUG_REG49_RREADY_q_MASK | \ + MH_DEBUG_REG49_RLAST_q_MASK | \ + MH_DEBUG_REG49_BVALID_q_MASK | \ + MH_DEBUG_REG49_BREADY_q_MASK) + +#define MH_DEBUG_REG49(ctrl_arc_empty, ctrl_rarc_empty, arq_ctrl_empty, arq_ctrl_write, tlbmiss_ctrl_rts, ctrl_tlbmiss_re_q, inflt_limit_q, inflt_limit_cnt_q, arc_ctrl_re_q, rarc_ctrl_re_q, rvalid_q, rready_q, rlast_q, bvalid_q, bready_q) \ + ((ctrl_arc_empty << MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT) | \ + (ctrl_rarc_empty << MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT) | \ + (arq_ctrl_empty << MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT) | \ + (arq_ctrl_write << MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT) | \ + (tlbmiss_ctrl_rts << MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT) | \ + (ctrl_tlbmiss_re_q << MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT) | \ + (inflt_limit_q << MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT) | \ + (inflt_limit_cnt_q << MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT) | \ + (arc_ctrl_re_q << MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT) | \ + (rarc_ctrl_re_q << MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT) | \ + (rvalid_q << MH_DEBUG_REG49_RVALID_q_SHIFT) | \ + (rready_q << MH_DEBUG_REG49_RREADY_q_SHIFT) | \ + (rlast_q << MH_DEBUG_REG49_RLAST_q_SHIFT) | \ + (bvalid_q << MH_DEBUG_REG49_BVALID_q_SHIFT) | \ + (bready_q << MH_DEBUG_REG49_BREADY_q_SHIFT)) + +#define MH_DEBUG_REG49_GET_CTRL_ARC_EMPTY(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK) >> MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT) +#define MH_DEBUG_REG49_GET_CTRL_RARC_EMPTY(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK) >> MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT) +#define MH_DEBUG_REG49_GET_ARQ_CTRL_EMPTY(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK) >> MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG49_GET_ARQ_CTRL_WRITE(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK) >> MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT) +#define MH_DEBUG_REG49_GET_TLBMISS_CTRL_RTS(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG49_GET_CTRL_TLBMISS_RE_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG49_GET_INFLT_LIMIT_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_INFLT_LIMIT_q_MASK) >> MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT) +#define MH_DEBUG_REG49_GET_INFLT_LIMIT_CNT_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK) >> MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT) +#define MH_DEBUG_REG49_GET_ARC_CTRL_RE_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG49_GET_RARC_CTRL_RE_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG49_GET_RVALID_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_RVALID_q_MASK) >> MH_DEBUG_REG49_RVALID_q_SHIFT) +#define MH_DEBUG_REG49_GET_RREADY_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_RREADY_q_MASK) >> MH_DEBUG_REG49_RREADY_q_SHIFT) +#define MH_DEBUG_REG49_GET_RLAST_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_RLAST_q_MASK) >> MH_DEBUG_REG49_RLAST_q_SHIFT) +#define MH_DEBUG_REG49_GET_BVALID_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_BVALID_q_MASK) >> MH_DEBUG_REG49_BVALID_q_SHIFT) +#define MH_DEBUG_REG49_GET_BREADY_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_BREADY_q_MASK) >> MH_DEBUG_REG49_BREADY_q_SHIFT) + +#define MH_DEBUG_REG49_SET_CTRL_ARC_EMPTY(mh_debug_reg49_reg, ctrl_arc_empty) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK) | (ctrl_arc_empty << MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT) +#define MH_DEBUG_REG49_SET_CTRL_RARC_EMPTY(mh_debug_reg49_reg, ctrl_rarc_empty) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK) | (ctrl_rarc_empty << MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT) +#define MH_DEBUG_REG49_SET_ARQ_CTRL_EMPTY(mh_debug_reg49_reg, arq_ctrl_empty) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK) | (arq_ctrl_empty << MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG49_SET_ARQ_CTRL_WRITE(mh_debug_reg49_reg, arq_ctrl_write) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK) | (arq_ctrl_write << MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT) +#define MH_DEBUG_REG49_SET_TLBMISS_CTRL_RTS(mh_debug_reg49_reg, tlbmiss_ctrl_rts) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG49_SET_CTRL_TLBMISS_RE_q(mh_debug_reg49_reg, ctrl_tlbmiss_re_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG49_SET_INFLT_LIMIT_q(mh_debug_reg49_reg, inflt_limit_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_INFLT_LIMIT_q_MASK) | (inflt_limit_q << MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT) +#define MH_DEBUG_REG49_SET_INFLT_LIMIT_CNT_q(mh_debug_reg49_reg, inflt_limit_cnt_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK) | (inflt_limit_cnt_q << MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT) +#define MH_DEBUG_REG49_SET_ARC_CTRL_RE_q(mh_debug_reg49_reg, arc_ctrl_re_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK) | (arc_ctrl_re_q << MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG49_SET_RARC_CTRL_RE_q(mh_debug_reg49_reg, rarc_ctrl_re_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK) | (rarc_ctrl_re_q << MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG49_SET_RVALID_q(mh_debug_reg49_reg, rvalid_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RVALID_q_MASK) | (rvalid_q << MH_DEBUG_REG49_RVALID_q_SHIFT) +#define MH_DEBUG_REG49_SET_RREADY_q(mh_debug_reg49_reg, rready_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RREADY_q_MASK) | (rready_q << MH_DEBUG_REG49_RREADY_q_SHIFT) +#define MH_DEBUG_REG49_SET_RLAST_q(mh_debug_reg49_reg, rlast_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RLAST_q_MASK) | (rlast_q << MH_DEBUG_REG49_RLAST_q_SHIFT) +#define MH_DEBUG_REG49_SET_BVALID_q(mh_debug_reg49_reg, bvalid_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG49_BVALID_q_SHIFT) +#define MH_DEBUG_REG49_SET_BREADY_q(mh_debug_reg49_reg, bready_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG49_BREADY_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg49_t { + unsigned int ctrl_arc_empty : MH_DEBUG_REG49_CTRL_ARC_EMPTY_SIZE; + unsigned int ctrl_rarc_empty : MH_DEBUG_REG49_CTRL_RARC_EMPTY_SIZE; + unsigned int arq_ctrl_empty : MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SIZE; + unsigned int arq_ctrl_write : MH_DEBUG_REG49_ARQ_CTRL_WRITE_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SIZE; + unsigned int inflt_limit_q : MH_DEBUG_REG49_INFLT_LIMIT_q_SIZE; + unsigned int inflt_limit_cnt_q : MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SIZE; + unsigned int arc_ctrl_re_q : MH_DEBUG_REG49_ARC_CTRL_RE_q_SIZE; + unsigned int rarc_ctrl_re_q : MH_DEBUG_REG49_RARC_CTRL_RE_q_SIZE; + unsigned int rvalid_q : MH_DEBUG_REG49_RVALID_q_SIZE; + unsigned int rready_q : MH_DEBUG_REG49_RREADY_q_SIZE; + unsigned int rlast_q : MH_DEBUG_REG49_RLAST_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG49_BVALID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG49_BREADY_q_SIZE; + unsigned int : 12; + } mh_debug_reg49_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg49_t { + unsigned int : 12; + unsigned int bready_q : MH_DEBUG_REG49_BREADY_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG49_BVALID_q_SIZE; + unsigned int rlast_q : MH_DEBUG_REG49_RLAST_q_SIZE; + unsigned int rready_q : MH_DEBUG_REG49_RREADY_q_SIZE; + unsigned int rvalid_q : MH_DEBUG_REG49_RVALID_q_SIZE; + unsigned int rarc_ctrl_re_q : MH_DEBUG_REG49_RARC_CTRL_RE_q_SIZE; + unsigned int arc_ctrl_re_q : MH_DEBUG_REG49_ARC_CTRL_RE_q_SIZE; + unsigned int inflt_limit_cnt_q : MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SIZE; + unsigned int inflt_limit_q : MH_DEBUG_REG49_INFLT_LIMIT_q_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SIZE; + unsigned int arq_ctrl_write : MH_DEBUG_REG49_ARQ_CTRL_WRITE_SIZE; + unsigned int arq_ctrl_empty : MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SIZE; + unsigned int ctrl_rarc_empty : MH_DEBUG_REG49_CTRL_RARC_EMPTY_SIZE; + unsigned int ctrl_arc_empty : MH_DEBUG_REG49_CTRL_ARC_EMPTY_SIZE; + } mh_debug_reg49_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg49_t f; +} mh_debug_reg49_u; + + +/* + * MH_DEBUG_REG50 struct + */ + +#define MH_DEBUG_REG50_MH_CP_grb_send_SIZE 1 +#define MH_DEBUG_REG50_MH_VGT_grb_send_SIZE 1 +#define MH_DEBUG_REG50_MH_TC_mcsend_SIZE 1 +#define MH_DEBUG_REG50_MH_TLBMISS_SEND_SIZE 1 +#define MH_DEBUG_REG50_TLBMISS_VALID_SIZE 1 +#define MH_DEBUG_REG50_RDC_VALID_SIZE 1 +#define MH_DEBUG_REG50_RDC_RID_SIZE 3 +#define MH_DEBUG_REG50_RDC_RLAST_SIZE 1 +#define MH_DEBUG_REG50_RDC_RRESP_SIZE 2 +#define MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SIZE 1 +#define MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SIZE 1 +#define MH_DEBUG_REG50_MMU_ID_REQUEST_q_SIZE 1 +#define MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SIZE 6 +#define MH_DEBUG_REG50_MMU_ID_RESPONSE_SIZE 1 +#define MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SIZE 6 +#define MH_DEBUG_REG50_CNT_HOLD_q1_SIZE 1 +#define MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3 + +#define MH_DEBUG_REG50_MH_CP_grb_send_SHIFT 0 +#define MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT 1 +#define MH_DEBUG_REG50_MH_TC_mcsend_SHIFT 2 +#define MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT 3 +#define MH_DEBUG_REG50_TLBMISS_VALID_SHIFT 4 +#define MH_DEBUG_REG50_RDC_VALID_SHIFT 5 +#define MH_DEBUG_REG50_RDC_RID_SHIFT 6 +#define MH_DEBUG_REG50_RDC_RLAST_SHIFT 9 +#define MH_DEBUG_REG50_RDC_RRESP_SHIFT 10 +#define MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT 12 +#define MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT 13 +#define MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT 14 +#define MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT 15 +#define MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT 21 +#define MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT 22 +#define MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT 28 +#define MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 29 + +#define MH_DEBUG_REG50_MH_CP_grb_send_MASK 0x00000001 +#define MH_DEBUG_REG50_MH_VGT_grb_send_MASK 0x00000002 +#define MH_DEBUG_REG50_MH_TC_mcsend_MASK 0x00000004 +#define MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK 0x00000008 +#define MH_DEBUG_REG50_TLBMISS_VALID_MASK 0x00000010 +#define MH_DEBUG_REG50_RDC_VALID_MASK 0x00000020 +#define MH_DEBUG_REG50_RDC_RID_MASK 0x000001c0 +#define MH_DEBUG_REG50_RDC_RLAST_MASK 0x00000200 +#define MH_DEBUG_REG50_RDC_RRESP_MASK 0x00000c00 +#define MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK 0x00001000 +#define MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK 0x00002000 +#define MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK 0x00004000 +#define MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK 0x001f8000 +#define MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK 0x00200000 +#define MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK 0x0fc00000 +#define MH_DEBUG_REG50_CNT_HOLD_q1_MASK 0x10000000 +#define MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0xe0000000 + +#define MH_DEBUG_REG50_MASK \ + (MH_DEBUG_REG50_MH_CP_grb_send_MASK | \ + MH_DEBUG_REG50_MH_VGT_grb_send_MASK | \ + MH_DEBUG_REG50_MH_TC_mcsend_MASK | \ + MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK | \ + MH_DEBUG_REG50_TLBMISS_VALID_MASK | \ + MH_DEBUG_REG50_RDC_VALID_MASK | \ + MH_DEBUG_REG50_RDC_RID_MASK | \ + MH_DEBUG_REG50_RDC_RLAST_MASK | \ + MH_DEBUG_REG50_RDC_RRESP_MASK | \ + MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK | \ + MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK | \ + MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK | \ + MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK | \ + MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK | \ + MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK | \ + MH_DEBUG_REG50_CNT_HOLD_q1_MASK | \ + MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) + +#define MH_DEBUG_REG50(mh_cp_grb_send, mh_vgt_grb_send, mh_tc_mcsend, mh_tlbmiss_send, tlbmiss_valid, rdc_valid, rdc_rid, rdc_rlast, rdc_rresp, tlbmiss_ctrl_rts, ctrl_tlbmiss_re_q, mmu_id_request_q, outstanding_mmuid_cnt_q, mmu_id_response, tlbmiss_return_cnt_q, cnt_hold_q1, mh_clnt_axi_id_reuse_mmur_id) \ + ((mh_cp_grb_send << MH_DEBUG_REG50_MH_CP_grb_send_SHIFT) | \ + (mh_vgt_grb_send << MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT) | \ + (mh_tc_mcsend << MH_DEBUG_REG50_MH_TC_mcsend_SHIFT) | \ + (mh_tlbmiss_send << MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT) | \ + (tlbmiss_valid << MH_DEBUG_REG50_TLBMISS_VALID_SHIFT) | \ + (rdc_valid << MH_DEBUG_REG50_RDC_VALID_SHIFT) | \ + (rdc_rid << MH_DEBUG_REG50_RDC_RID_SHIFT) | \ + (rdc_rlast << MH_DEBUG_REG50_RDC_RLAST_SHIFT) | \ + (rdc_rresp << MH_DEBUG_REG50_RDC_RRESP_SHIFT) | \ + (tlbmiss_ctrl_rts << MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT) | \ + (ctrl_tlbmiss_re_q << MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT) | \ + (mmu_id_request_q << MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT) | \ + (outstanding_mmuid_cnt_q << MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT) | \ + (mmu_id_response << MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT) | \ + (tlbmiss_return_cnt_q << MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT) | \ + (cnt_hold_q1 << MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT) | \ + (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)) + +#define MH_DEBUG_REG50_GET_MH_CP_grb_send(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MH_CP_grb_send_MASK) >> MH_DEBUG_REG50_MH_CP_grb_send_SHIFT) +#define MH_DEBUG_REG50_GET_MH_VGT_grb_send(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MH_VGT_grb_send_MASK) >> MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT) +#define MH_DEBUG_REG50_GET_MH_TC_mcsend(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MH_TC_mcsend_MASK) >> MH_DEBUG_REG50_MH_TC_mcsend_SHIFT) +#define MH_DEBUG_REG50_GET_MH_TLBMISS_SEND(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK) >> MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT) +#define MH_DEBUG_REG50_GET_TLBMISS_VALID(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_TLBMISS_VALID_MASK) >> MH_DEBUG_REG50_TLBMISS_VALID_SHIFT) +#define MH_DEBUG_REG50_GET_RDC_VALID(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_VALID_MASK) >> MH_DEBUG_REG50_RDC_VALID_SHIFT) +#define MH_DEBUG_REG50_GET_RDC_RID(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_RID_MASK) >> MH_DEBUG_REG50_RDC_RID_SHIFT) +#define MH_DEBUG_REG50_GET_RDC_RLAST(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_RLAST_MASK) >> MH_DEBUG_REG50_RDC_RLAST_SHIFT) +#define MH_DEBUG_REG50_GET_RDC_RRESP(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_RRESP_MASK) >> MH_DEBUG_REG50_RDC_RRESP_SHIFT) +#define MH_DEBUG_REG50_GET_TLBMISS_CTRL_RTS(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG50_GET_CTRL_TLBMISS_RE_q(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG50_GET_MMU_ID_REQUEST_q(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK) >> MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT) +#define MH_DEBUG_REG50_GET_OUTSTANDING_MMUID_CNT_q(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK) >> MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT) +#define MH_DEBUG_REG50_GET_MMU_ID_RESPONSE(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK) >> MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT) +#define MH_DEBUG_REG50_GET_TLBMISS_RETURN_CNT_q(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK) >> MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT) +#define MH_DEBUG_REG50_GET_CNT_HOLD_q1(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_CNT_HOLD_q1_MASK) >> MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT) +#define MH_DEBUG_REG50_GET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) + +#define MH_DEBUG_REG50_SET_MH_CP_grb_send(mh_debug_reg50_reg, mh_cp_grb_send) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_CP_grb_send_MASK) | (mh_cp_grb_send << MH_DEBUG_REG50_MH_CP_grb_send_SHIFT) +#define MH_DEBUG_REG50_SET_MH_VGT_grb_send(mh_debug_reg50_reg, mh_vgt_grb_send) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_VGT_grb_send_MASK) | (mh_vgt_grb_send << MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT) +#define MH_DEBUG_REG50_SET_MH_TC_mcsend(mh_debug_reg50_reg, mh_tc_mcsend) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_TC_mcsend_MASK) | (mh_tc_mcsend << MH_DEBUG_REG50_MH_TC_mcsend_SHIFT) +#define MH_DEBUG_REG50_SET_MH_TLBMISS_SEND(mh_debug_reg50_reg, mh_tlbmiss_send) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK) | (mh_tlbmiss_send << MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT) +#define MH_DEBUG_REG50_SET_TLBMISS_VALID(mh_debug_reg50_reg, tlbmiss_valid) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_TLBMISS_VALID_MASK) | (tlbmiss_valid << MH_DEBUG_REG50_TLBMISS_VALID_SHIFT) +#define MH_DEBUG_REG50_SET_RDC_VALID(mh_debug_reg50_reg, rdc_valid) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_VALID_MASK) | (rdc_valid << MH_DEBUG_REG50_RDC_VALID_SHIFT) +#define MH_DEBUG_REG50_SET_RDC_RID(mh_debug_reg50_reg, rdc_rid) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_RID_MASK) | (rdc_rid << MH_DEBUG_REG50_RDC_RID_SHIFT) +#define MH_DEBUG_REG50_SET_RDC_RLAST(mh_debug_reg50_reg, rdc_rlast) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_RLAST_MASK) | (rdc_rlast << MH_DEBUG_REG50_RDC_RLAST_SHIFT) +#define MH_DEBUG_REG50_SET_RDC_RRESP(mh_debug_reg50_reg, rdc_rresp) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_RRESP_MASK) | (rdc_rresp << MH_DEBUG_REG50_RDC_RRESP_SHIFT) +#define MH_DEBUG_REG50_SET_TLBMISS_CTRL_RTS(mh_debug_reg50_reg, tlbmiss_ctrl_rts) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG50_SET_CTRL_TLBMISS_RE_q(mh_debug_reg50_reg, ctrl_tlbmiss_re_q) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG50_SET_MMU_ID_REQUEST_q(mh_debug_reg50_reg, mmu_id_request_q) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK) | (mmu_id_request_q << MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT) +#define MH_DEBUG_REG50_SET_OUTSTANDING_MMUID_CNT_q(mh_debug_reg50_reg, outstanding_mmuid_cnt_q) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK) | (outstanding_mmuid_cnt_q << MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT) +#define MH_DEBUG_REG50_SET_MMU_ID_RESPONSE(mh_debug_reg50_reg, mmu_id_response) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK) | (mmu_id_response << MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT) +#define MH_DEBUG_REG50_SET_TLBMISS_RETURN_CNT_q(mh_debug_reg50_reg, tlbmiss_return_cnt_q) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK) | (tlbmiss_return_cnt_q << MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT) +#define MH_DEBUG_REG50_SET_CNT_HOLD_q1(mh_debug_reg50_reg, cnt_hold_q1) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_CNT_HOLD_q1_MASK) | (cnt_hold_q1 << MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT) +#define MH_DEBUG_REG50_SET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg50_reg, mh_clnt_axi_id_reuse_mmur_id) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg50_t { + unsigned int mh_cp_grb_send : MH_DEBUG_REG50_MH_CP_grb_send_SIZE; + unsigned int mh_vgt_grb_send : MH_DEBUG_REG50_MH_VGT_grb_send_SIZE; + unsigned int mh_tc_mcsend : MH_DEBUG_REG50_MH_TC_mcsend_SIZE; + unsigned int mh_tlbmiss_send : MH_DEBUG_REG50_MH_TLBMISS_SEND_SIZE; + unsigned int tlbmiss_valid : MH_DEBUG_REG50_TLBMISS_VALID_SIZE; + unsigned int rdc_valid : MH_DEBUG_REG50_RDC_VALID_SIZE; + unsigned int rdc_rid : MH_DEBUG_REG50_RDC_RID_SIZE; + unsigned int rdc_rlast : MH_DEBUG_REG50_RDC_RLAST_SIZE; + unsigned int rdc_rresp : MH_DEBUG_REG50_RDC_RRESP_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SIZE; + unsigned int mmu_id_request_q : MH_DEBUG_REG50_MMU_ID_REQUEST_q_SIZE; + unsigned int outstanding_mmuid_cnt_q : MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SIZE; + unsigned int mmu_id_response : MH_DEBUG_REG50_MMU_ID_RESPONSE_SIZE; + unsigned int tlbmiss_return_cnt_q : MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SIZE; + unsigned int cnt_hold_q1 : MH_DEBUG_REG50_CNT_HOLD_q1_SIZE; + unsigned int mh_clnt_axi_id_reuse_mmur_id : MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + } mh_debug_reg50_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg50_t { + unsigned int mh_clnt_axi_id_reuse_mmur_id : MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int cnt_hold_q1 : MH_DEBUG_REG50_CNT_HOLD_q1_SIZE; + unsigned int tlbmiss_return_cnt_q : MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SIZE; + unsigned int mmu_id_response : MH_DEBUG_REG50_MMU_ID_RESPONSE_SIZE; + unsigned int outstanding_mmuid_cnt_q : MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SIZE; + unsigned int mmu_id_request_q : MH_DEBUG_REG50_MMU_ID_REQUEST_q_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SIZE; + unsigned int rdc_rresp : MH_DEBUG_REG50_RDC_RRESP_SIZE; + unsigned int rdc_rlast : MH_DEBUG_REG50_RDC_RLAST_SIZE; + unsigned int rdc_rid : MH_DEBUG_REG50_RDC_RID_SIZE; + unsigned int rdc_valid : MH_DEBUG_REG50_RDC_VALID_SIZE; + unsigned int tlbmiss_valid : MH_DEBUG_REG50_TLBMISS_VALID_SIZE; + unsigned int mh_tlbmiss_send : MH_DEBUG_REG50_MH_TLBMISS_SEND_SIZE; + unsigned int mh_tc_mcsend : MH_DEBUG_REG50_MH_TC_mcsend_SIZE; + unsigned int mh_vgt_grb_send : MH_DEBUG_REG50_MH_VGT_grb_send_SIZE; + unsigned int mh_cp_grb_send : MH_DEBUG_REG50_MH_CP_grb_send_SIZE; + } mh_debug_reg50_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg50_t f; +} mh_debug_reg50_u; + + +/* + * MH_DEBUG_REG51 struct + */ + +#define MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SIZE 32 + +#define MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT 0 + +#define MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK 0xffffffff + +#define MH_DEBUG_REG51_MASK \ + (MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK) + +#define MH_DEBUG_REG51(rf_mmu_page_fault) \ + ((rf_mmu_page_fault << MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT)) + +#define MH_DEBUG_REG51_GET_RF_MMU_PAGE_FAULT(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK) >> MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT) + +#define MH_DEBUG_REG51_SET_RF_MMU_PAGE_FAULT(mh_debug_reg51_reg, rf_mmu_page_fault) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK) | (rf_mmu_page_fault << MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg51_t { + unsigned int rf_mmu_page_fault : MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SIZE; + } mh_debug_reg51_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg51_t { + unsigned int rf_mmu_page_fault : MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SIZE; + } mh_debug_reg51_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg51_t f; +} mh_debug_reg51_u; + + +/* + * MH_DEBUG_REG52 struct + */ + +#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SIZE 2 +#define MH_DEBUG_REG52_ARB_WE_SIZE 1 +#define MH_DEBUG_REG52_MMU_RTR_SIZE 1 +#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SIZE 22 +#define MH_DEBUG_REG52_ARB_ID_q_SIZE 3 +#define MH_DEBUG_REG52_ARB_WRITE_q_SIZE 1 +#define MH_DEBUG_REG52_client_behavior_q_SIZE 2 + +#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT 0 +#define MH_DEBUG_REG52_ARB_WE_SHIFT 2 +#define MH_DEBUG_REG52_MMU_RTR_SHIFT 3 +#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT 4 +#define MH_DEBUG_REG52_ARB_ID_q_SHIFT 26 +#define MH_DEBUG_REG52_ARB_WRITE_q_SHIFT 29 +#define MH_DEBUG_REG52_client_behavior_q_SHIFT 30 + +#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK 0x00000003 +#define MH_DEBUG_REG52_ARB_WE_MASK 0x00000004 +#define MH_DEBUG_REG52_MMU_RTR_MASK 0x00000008 +#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK 0x03fffff0 +#define MH_DEBUG_REG52_ARB_ID_q_MASK 0x1c000000 +#define MH_DEBUG_REG52_ARB_WRITE_q_MASK 0x20000000 +#define MH_DEBUG_REG52_client_behavior_q_MASK 0xc0000000 + +#define MH_DEBUG_REG52_MASK \ + (MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK | \ + MH_DEBUG_REG52_ARB_WE_MASK | \ + MH_DEBUG_REG52_MMU_RTR_MASK | \ + MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK | \ + MH_DEBUG_REG52_ARB_ID_q_MASK | \ + MH_DEBUG_REG52_ARB_WRITE_q_MASK | \ + MH_DEBUG_REG52_client_behavior_q_MASK) + +#define MH_DEBUG_REG52(rf_mmu_config_q_1_to_0, arb_we, mmu_rtr, rf_mmu_config_q_25_to_4, arb_id_q, arb_write_q, client_behavior_q) \ + ((rf_mmu_config_q_1_to_0 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT) | \ + (arb_we << MH_DEBUG_REG52_ARB_WE_SHIFT) | \ + (mmu_rtr << MH_DEBUG_REG52_MMU_RTR_SHIFT) | \ + (rf_mmu_config_q_25_to_4 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT) | \ + (arb_id_q << MH_DEBUG_REG52_ARB_ID_q_SHIFT) | \ + (arb_write_q << MH_DEBUG_REG52_ARB_WRITE_q_SHIFT) | \ + (client_behavior_q << MH_DEBUG_REG52_client_behavior_q_SHIFT)) + +#define MH_DEBUG_REG52_GET_RF_MMU_CONFIG_q_1_to_0(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK) >> MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT) +#define MH_DEBUG_REG52_GET_ARB_WE(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_ARB_WE_MASK) >> MH_DEBUG_REG52_ARB_WE_SHIFT) +#define MH_DEBUG_REG52_GET_MMU_RTR(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_MMU_RTR_MASK) >> MH_DEBUG_REG52_MMU_RTR_SHIFT) +#define MH_DEBUG_REG52_GET_RF_MMU_CONFIG_q_25_to_4(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK) >> MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT) +#define MH_DEBUG_REG52_GET_ARB_ID_q(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_ARB_ID_q_MASK) >> MH_DEBUG_REG52_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG52_GET_ARB_WRITE_q(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_ARB_WRITE_q_MASK) >> MH_DEBUG_REG52_ARB_WRITE_q_SHIFT) +#define MH_DEBUG_REG52_GET_client_behavior_q(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_client_behavior_q_MASK) >> MH_DEBUG_REG52_client_behavior_q_SHIFT) + +#define MH_DEBUG_REG52_SET_RF_MMU_CONFIG_q_1_to_0(mh_debug_reg52_reg, rf_mmu_config_q_1_to_0) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK) | (rf_mmu_config_q_1_to_0 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT) +#define MH_DEBUG_REG52_SET_ARB_WE(mh_debug_reg52_reg, arb_we) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG52_ARB_WE_SHIFT) +#define MH_DEBUG_REG52_SET_MMU_RTR(mh_debug_reg52_reg, mmu_rtr) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_MMU_RTR_MASK) | (mmu_rtr << MH_DEBUG_REG52_MMU_RTR_SHIFT) +#define MH_DEBUG_REG52_SET_RF_MMU_CONFIG_q_25_to_4(mh_debug_reg52_reg, rf_mmu_config_q_25_to_4) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK) | (rf_mmu_config_q_25_to_4 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT) +#define MH_DEBUG_REG52_SET_ARB_ID_q(mh_debug_reg52_reg, arb_id_q) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG52_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG52_SET_ARB_WRITE_q(mh_debug_reg52_reg, arb_write_q) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_ARB_WRITE_q_MASK) | (arb_write_q << MH_DEBUG_REG52_ARB_WRITE_q_SHIFT) +#define MH_DEBUG_REG52_SET_client_behavior_q(mh_debug_reg52_reg, client_behavior_q) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_client_behavior_q_MASK) | (client_behavior_q << MH_DEBUG_REG52_client_behavior_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg52_t { + unsigned int rf_mmu_config_q_1_to_0 : MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SIZE; + unsigned int arb_we : MH_DEBUG_REG52_ARB_WE_SIZE; + unsigned int mmu_rtr : MH_DEBUG_REG52_MMU_RTR_SIZE; + unsigned int rf_mmu_config_q_25_to_4 : MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG52_ARB_ID_q_SIZE; + unsigned int arb_write_q : MH_DEBUG_REG52_ARB_WRITE_q_SIZE; + unsigned int client_behavior_q : MH_DEBUG_REG52_client_behavior_q_SIZE; + } mh_debug_reg52_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg52_t { + unsigned int client_behavior_q : MH_DEBUG_REG52_client_behavior_q_SIZE; + unsigned int arb_write_q : MH_DEBUG_REG52_ARB_WRITE_q_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG52_ARB_ID_q_SIZE; + unsigned int rf_mmu_config_q_25_to_4 : MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SIZE; + unsigned int mmu_rtr : MH_DEBUG_REG52_MMU_RTR_SIZE; + unsigned int arb_we : MH_DEBUG_REG52_ARB_WE_SIZE; + unsigned int rf_mmu_config_q_1_to_0 : MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SIZE; + } mh_debug_reg52_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg52_t f; +} mh_debug_reg52_u; + + +/* + * MH_DEBUG_REG53 struct + */ + +#define MH_DEBUG_REG53_stage1_valid_SIZE 1 +#define MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SIZE 1 +#define MH_DEBUG_REG53_pa_in_mpu_range_SIZE 1 +#define MH_DEBUG_REG53_tag_match_q_SIZE 1 +#define MH_DEBUG_REG53_tag_miss_q_SIZE 1 +#define MH_DEBUG_REG53_va_in_range_q_SIZE 1 +#define MH_DEBUG_REG53_MMU_MISS_SIZE 1 +#define MH_DEBUG_REG53_MMU_READ_MISS_SIZE 1 +#define MH_DEBUG_REG53_MMU_WRITE_MISS_SIZE 1 +#define MH_DEBUG_REG53_MMU_HIT_SIZE 1 +#define MH_DEBUG_REG53_MMU_READ_HIT_SIZE 1 +#define MH_DEBUG_REG53_MMU_WRITE_HIT_SIZE 1 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SIZE 1 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SIZE 1 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SIZE 1 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SIZE 1 +#define MH_DEBUG_REG53_REQ_VA_OFFSET_q_SIZE 16 + +#define MH_DEBUG_REG53_stage1_valid_SHIFT 0 +#define MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT 1 +#define MH_DEBUG_REG53_pa_in_mpu_range_SHIFT 2 +#define MH_DEBUG_REG53_tag_match_q_SHIFT 3 +#define MH_DEBUG_REG53_tag_miss_q_SHIFT 4 +#define MH_DEBUG_REG53_va_in_range_q_SHIFT 5 +#define MH_DEBUG_REG53_MMU_MISS_SHIFT 6 +#define MH_DEBUG_REG53_MMU_READ_MISS_SHIFT 7 +#define MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT 8 +#define MH_DEBUG_REG53_MMU_HIT_SHIFT 9 +#define MH_DEBUG_REG53_MMU_READ_HIT_SHIFT 10 +#define MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT 11 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT 12 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT 13 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT 14 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT 15 +#define MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT 16 + +#define MH_DEBUG_REG53_stage1_valid_MASK 0x00000001 +#define MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK 0x00000002 +#define MH_DEBUG_REG53_pa_in_mpu_range_MASK 0x00000004 +#define MH_DEBUG_REG53_tag_match_q_MASK 0x00000008 +#define MH_DEBUG_REG53_tag_miss_q_MASK 0x00000010 +#define MH_DEBUG_REG53_va_in_range_q_MASK 0x00000020 +#define MH_DEBUG_REG53_MMU_MISS_MASK 0x00000040 +#define MH_DEBUG_REG53_MMU_READ_MISS_MASK 0x00000080 +#define MH_DEBUG_REG53_MMU_WRITE_MISS_MASK 0x00000100 +#define MH_DEBUG_REG53_MMU_HIT_MASK 0x00000200 +#define MH_DEBUG_REG53_MMU_READ_HIT_MASK 0x00000400 +#define MH_DEBUG_REG53_MMU_WRITE_HIT_MASK 0x00000800 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK 0x00001000 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK 0x00002000 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK 0x00004000 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK 0x00008000 +#define MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK 0xffff0000 + +#define MH_DEBUG_REG53_MASK \ + (MH_DEBUG_REG53_stage1_valid_MASK | \ + MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK | \ + MH_DEBUG_REG53_pa_in_mpu_range_MASK | \ + MH_DEBUG_REG53_tag_match_q_MASK | \ + MH_DEBUG_REG53_tag_miss_q_MASK | \ + MH_DEBUG_REG53_va_in_range_q_MASK | \ + MH_DEBUG_REG53_MMU_MISS_MASK | \ + MH_DEBUG_REG53_MMU_READ_MISS_MASK | \ + MH_DEBUG_REG53_MMU_WRITE_MISS_MASK | \ + MH_DEBUG_REG53_MMU_HIT_MASK | \ + MH_DEBUG_REG53_MMU_READ_HIT_MASK | \ + MH_DEBUG_REG53_MMU_WRITE_HIT_MASK | \ + MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK | \ + MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK | \ + MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK | \ + MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK | \ + MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK) + +#define MH_DEBUG_REG53(stage1_valid, ignore_tag_miss_q, pa_in_mpu_range, tag_match_q, tag_miss_q, va_in_range_q, mmu_miss, mmu_read_miss, mmu_write_miss, mmu_hit, mmu_read_hit, mmu_write_hit, mmu_split_mode_tc_miss, mmu_split_mode_tc_hit, mmu_split_mode_nontc_miss, mmu_split_mode_nontc_hit, req_va_offset_q) \ + ((stage1_valid << MH_DEBUG_REG53_stage1_valid_SHIFT) | \ + (ignore_tag_miss_q << MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT) | \ + (pa_in_mpu_range << MH_DEBUG_REG53_pa_in_mpu_range_SHIFT) | \ + (tag_match_q << MH_DEBUG_REG53_tag_match_q_SHIFT) | \ + (tag_miss_q << MH_DEBUG_REG53_tag_miss_q_SHIFT) | \ + (va_in_range_q << MH_DEBUG_REG53_va_in_range_q_SHIFT) | \ + (mmu_miss << MH_DEBUG_REG53_MMU_MISS_SHIFT) | \ + (mmu_read_miss << MH_DEBUG_REG53_MMU_READ_MISS_SHIFT) | \ + (mmu_write_miss << MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT) | \ + (mmu_hit << MH_DEBUG_REG53_MMU_HIT_SHIFT) | \ + (mmu_read_hit << MH_DEBUG_REG53_MMU_READ_HIT_SHIFT) | \ + (mmu_write_hit << MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT) | \ + (mmu_split_mode_tc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT) | \ + (mmu_split_mode_tc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT) | \ + (mmu_split_mode_nontc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT) | \ + (mmu_split_mode_nontc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT) | \ + (req_va_offset_q << MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT)) + +#define MH_DEBUG_REG53_GET_stage1_valid(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_stage1_valid_MASK) >> MH_DEBUG_REG53_stage1_valid_SHIFT) +#define MH_DEBUG_REG53_GET_IGNORE_TAG_MISS_q(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK) >> MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT) +#define MH_DEBUG_REG53_GET_pa_in_mpu_range(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_pa_in_mpu_range_MASK) >> MH_DEBUG_REG53_pa_in_mpu_range_SHIFT) +#define MH_DEBUG_REG53_GET_tag_match_q(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_tag_match_q_MASK) >> MH_DEBUG_REG53_tag_match_q_SHIFT) +#define MH_DEBUG_REG53_GET_tag_miss_q(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_tag_miss_q_MASK) >> MH_DEBUG_REG53_tag_miss_q_SHIFT) +#define MH_DEBUG_REG53_GET_va_in_range_q(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_va_in_range_q_MASK) >> MH_DEBUG_REG53_va_in_range_q_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_MISS(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_MISS_MASK) >> MH_DEBUG_REG53_MMU_MISS_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_READ_MISS(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_READ_MISS_MASK) >> MH_DEBUG_REG53_MMU_READ_MISS_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_WRITE_MISS(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_WRITE_MISS_MASK) >> MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_HIT(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_HIT_MASK) >> MH_DEBUG_REG53_MMU_HIT_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_READ_HIT(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_READ_HIT_MASK) >> MH_DEBUG_REG53_MMU_READ_HIT_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_WRITE_HIT(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_WRITE_HIT_MASK) >> MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_TC_MISS(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_TC_HIT(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_nonTC_MISS(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_nonTC_HIT(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT) +#define MH_DEBUG_REG53_GET_REQ_VA_OFFSET_q(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK) >> MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT) + +#define MH_DEBUG_REG53_SET_stage1_valid(mh_debug_reg53_reg, stage1_valid) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_stage1_valid_MASK) | (stage1_valid << MH_DEBUG_REG53_stage1_valid_SHIFT) +#define MH_DEBUG_REG53_SET_IGNORE_TAG_MISS_q(mh_debug_reg53_reg, ignore_tag_miss_q) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK) | (ignore_tag_miss_q << MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT) +#define MH_DEBUG_REG53_SET_pa_in_mpu_range(mh_debug_reg53_reg, pa_in_mpu_range) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_pa_in_mpu_range_MASK) | (pa_in_mpu_range << MH_DEBUG_REG53_pa_in_mpu_range_SHIFT) +#define MH_DEBUG_REG53_SET_tag_match_q(mh_debug_reg53_reg, tag_match_q) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_tag_match_q_MASK) | (tag_match_q << MH_DEBUG_REG53_tag_match_q_SHIFT) +#define MH_DEBUG_REG53_SET_tag_miss_q(mh_debug_reg53_reg, tag_miss_q) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_tag_miss_q_MASK) | (tag_miss_q << MH_DEBUG_REG53_tag_miss_q_SHIFT) +#define MH_DEBUG_REG53_SET_va_in_range_q(mh_debug_reg53_reg, va_in_range_q) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_va_in_range_q_MASK) | (va_in_range_q << MH_DEBUG_REG53_va_in_range_q_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_MISS(mh_debug_reg53_reg, mmu_miss) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_MISS_MASK) | (mmu_miss << MH_DEBUG_REG53_MMU_MISS_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_READ_MISS(mh_debug_reg53_reg, mmu_read_miss) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_READ_MISS_MASK) | (mmu_read_miss << MH_DEBUG_REG53_MMU_READ_MISS_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_WRITE_MISS(mh_debug_reg53_reg, mmu_write_miss) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_WRITE_MISS_MASK) | (mmu_write_miss << MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_HIT(mh_debug_reg53_reg, mmu_hit) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_HIT_MASK) | (mmu_hit << MH_DEBUG_REG53_MMU_HIT_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_READ_HIT(mh_debug_reg53_reg, mmu_read_hit) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_READ_HIT_MASK) | (mmu_read_hit << MH_DEBUG_REG53_MMU_READ_HIT_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_WRITE_HIT(mh_debug_reg53_reg, mmu_write_hit) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_WRITE_HIT_MASK) | (mmu_write_hit << MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_TC_MISS(mh_debug_reg53_reg, mmu_split_mode_tc_miss) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK) | (mmu_split_mode_tc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_TC_HIT(mh_debug_reg53_reg, mmu_split_mode_tc_hit) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK) | (mmu_split_mode_tc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_nonTC_MISS(mh_debug_reg53_reg, mmu_split_mode_nontc_miss) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK) | (mmu_split_mode_nontc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_nonTC_HIT(mh_debug_reg53_reg, mmu_split_mode_nontc_hit) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK) | (mmu_split_mode_nontc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT) +#define MH_DEBUG_REG53_SET_REQ_VA_OFFSET_q(mh_debug_reg53_reg, req_va_offset_q) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK) | (req_va_offset_q << MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg53_t { + unsigned int stage1_valid : MH_DEBUG_REG53_stage1_valid_SIZE; + unsigned int ignore_tag_miss_q : MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SIZE; + unsigned int pa_in_mpu_range : MH_DEBUG_REG53_pa_in_mpu_range_SIZE; + unsigned int tag_match_q : MH_DEBUG_REG53_tag_match_q_SIZE; + unsigned int tag_miss_q : MH_DEBUG_REG53_tag_miss_q_SIZE; + unsigned int va_in_range_q : MH_DEBUG_REG53_va_in_range_q_SIZE; + unsigned int mmu_miss : MH_DEBUG_REG53_MMU_MISS_SIZE; + unsigned int mmu_read_miss : MH_DEBUG_REG53_MMU_READ_MISS_SIZE; + unsigned int mmu_write_miss : MH_DEBUG_REG53_MMU_WRITE_MISS_SIZE; + unsigned int mmu_hit : MH_DEBUG_REG53_MMU_HIT_SIZE; + unsigned int mmu_read_hit : MH_DEBUG_REG53_MMU_READ_HIT_SIZE; + unsigned int mmu_write_hit : MH_DEBUG_REG53_MMU_WRITE_HIT_SIZE; + unsigned int mmu_split_mode_tc_miss : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SIZE; + unsigned int mmu_split_mode_tc_hit : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SIZE; + unsigned int mmu_split_mode_nontc_miss : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SIZE; + unsigned int mmu_split_mode_nontc_hit : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SIZE; + unsigned int req_va_offset_q : MH_DEBUG_REG53_REQ_VA_OFFSET_q_SIZE; + } mh_debug_reg53_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg53_t { + unsigned int req_va_offset_q : MH_DEBUG_REG53_REQ_VA_OFFSET_q_SIZE; + unsigned int mmu_split_mode_nontc_hit : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SIZE; + unsigned int mmu_split_mode_nontc_miss : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SIZE; + unsigned int mmu_split_mode_tc_hit : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SIZE; + unsigned int mmu_split_mode_tc_miss : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SIZE; + unsigned int mmu_write_hit : MH_DEBUG_REG53_MMU_WRITE_HIT_SIZE; + unsigned int mmu_read_hit : MH_DEBUG_REG53_MMU_READ_HIT_SIZE; + unsigned int mmu_hit : MH_DEBUG_REG53_MMU_HIT_SIZE; + unsigned int mmu_write_miss : MH_DEBUG_REG53_MMU_WRITE_MISS_SIZE; + unsigned int mmu_read_miss : MH_DEBUG_REG53_MMU_READ_MISS_SIZE; + unsigned int mmu_miss : MH_DEBUG_REG53_MMU_MISS_SIZE; + unsigned int va_in_range_q : MH_DEBUG_REG53_va_in_range_q_SIZE; + unsigned int tag_miss_q : MH_DEBUG_REG53_tag_miss_q_SIZE; + unsigned int tag_match_q : MH_DEBUG_REG53_tag_match_q_SIZE; + unsigned int pa_in_mpu_range : MH_DEBUG_REG53_pa_in_mpu_range_SIZE; + unsigned int ignore_tag_miss_q : MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SIZE; + unsigned int stage1_valid : MH_DEBUG_REG53_stage1_valid_SIZE; + } mh_debug_reg53_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg53_t f; +} mh_debug_reg53_u; + + +/* + * MH_DEBUG_REG54 struct + */ + +#define MH_DEBUG_REG54_ARQ_RTR_SIZE 1 +#define MH_DEBUG_REG54_MMU_WE_SIZE 1 +#define MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SIZE 1 +#define MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SIZE 1 +#define MH_DEBUG_REG54_MH_TLBMISS_SEND_SIZE 1 +#define MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE 1 +#define MH_DEBUG_REG54_pa_in_mpu_range_SIZE 1 +#define MH_DEBUG_REG54_stage1_valid_SIZE 1 +#define MH_DEBUG_REG54_stage2_valid_SIZE 1 +#define MH_DEBUG_REG54_client_behavior_q_SIZE 2 +#define MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SIZE 1 +#define MH_DEBUG_REG54_tag_match_q_SIZE 1 +#define MH_DEBUG_REG54_tag_miss_q_SIZE 1 +#define MH_DEBUG_REG54_va_in_range_q_SIZE 1 +#define MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SIZE 1 +#define MH_DEBUG_REG54_TAG_valid_q_SIZE 16 + +#define MH_DEBUG_REG54_ARQ_RTR_SHIFT 0 +#define MH_DEBUG_REG54_MMU_WE_SHIFT 1 +#define MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT 2 +#define MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT 3 +#define MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT 4 +#define MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT 5 +#define MH_DEBUG_REG54_pa_in_mpu_range_SHIFT 6 +#define MH_DEBUG_REG54_stage1_valid_SHIFT 7 +#define MH_DEBUG_REG54_stage2_valid_SHIFT 8 +#define MH_DEBUG_REG54_client_behavior_q_SHIFT 9 +#define MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT 11 +#define MH_DEBUG_REG54_tag_match_q_SHIFT 12 +#define MH_DEBUG_REG54_tag_miss_q_SHIFT 13 +#define MH_DEBUG_REG54_va_in_range_q_SHIFT 14 +#define MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT 15 +#define MH_DEBUG_REG54_TAG_valid_q_SHIFT 16 + +#define MH_DEBUG_REG54_ARQ_RTR_MASK 0x00000001 +#define MH_DEBUG_REG54_MMU_WE_MASK 0x00000002 +#define MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK 0x00000004 +#define MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK 0x00000008 +#define MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK 0x00000010 +#define MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK 0x00000020 +#define MH_DEBUG_REG54_pa_in_mpu_range_MASK 0x00000040 +#define MH_DEBUG_REG54_stage1_valid_MASK 0x00000080 +#define MH_DEBUG_REG54_stage2_valid_MASK 0x00000100 +#define MH_DEBUG_REG54_client_behavior_q_MASK 0x00000600 +#define MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK 0x00000800 +#define MH_DEBUG_REG54_tag_match_q_MASK 0x00001000 +#define MH_DEBUG_REG54_tag_miss_q_MASK 0x00002000 +#define MH_DEBUG_REG54_va_in_range_q_MASK 0x00004000 +#define MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK 0x00008000 +#define MH_DEBUG_REG54_TAG_valid_q_MASK 0xffff0000 + +#define MH_DEBUG_REG54_MASK \ + (MH_DEBUG_REG54_ARQ_RTR_MASK | \ + MH_DEBUG_REG54_MMU_WE_MASK | \ + MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK | \ + MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK | \ + MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK | \ + MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK | \ + MH_DEBUG_REG54_pa_in_mpu_range_MASK | \ + MH_DEBUG_REG54_stage1_valid_MASK | \ + MH_DEBUG_REG54_stage2_valid_MASK | \ + MH_DEBUG_REG54_client_behavior_q_MASK | \ + MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK | \ + MH_DEBUG_REG54_tag_match_q_MASK | \ + MH_DEBUG_REG54_tag_miss_q_MASK | \ + MH_DEBUG_REG54_va_in_range_q_MASK | \ + MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK | \ + MH_DEBUG_REG54_TAG_valid_q_MASK) + +#define MH_DEBUG_REG54(arq_rtr, mmu_we, ctrl_tlbmiss_re_q, tlbmiss_ctrl_rts, mh_tlbmiss_send, mmu_stall_awaiting_tlb_miss_fetch, pa_in_mpu_range, stage1_valid, stage2_valid, client_behavior_q, ignore_tag_miss_q, tag_match_q, tag_miss_q, va_in_range_q, pte_fetch_complete_q, tag_valid_q) \ + ((arq_rtr << MH_DEBUG_REG54_ARQ_RTR_SHIFT) | \ + (mmu_we << MH_DEBUG_REG54_MMU_WE_SHIFT) | \ + (ctrl_tlbmiss_re_q << MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT) | \ + (tlbmiss_ctrl_rts << MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT) | \ + (mh_tlbmiss_send << MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT) | \ + (mmu_stall_awaiting_tlb_miss_fetch << MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT) | \ + (pa_in_mpu_range << MH_DEBUG_REG54_pa_in_mpu_range_SHIFT) | \ + (stage1_valid << MH_DEBUG_REG54_stage1_valid_SHIFT) | \ + (stage2_valid << MH_DEBUG_REG54_stage2_valid_SHIFT) | \ + (client_behavior_q << MH_DEBUG_REG54_client_behavior_q_SHIFT) | \ + (ignore_tag_miss_q << MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT) | \ + (tag_match_q << MH_DEBUG_REG54_tag_match_q_SHIFT) | \ + (tag_miss_q << MH_DEBUG_REG54_tag_miss_q_SHIFT) | \ + (va_in_range_q << MH_DEBUG_REG54_va_in_range_q_SHIFT) | \ + (pte_fetch_complete_q << MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT) | \ + (tag_valid_q << MH_DEBUG_REG54_TAG_valid_q_SHIFT)) + +#define MH_DEBUG_REG54_GET_ARQ_RTR(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_ARQ_RTR_MASK) >> MH_DEBUG_REG54_ARQ_RTR_SHIFT) +#define MH_DEBUG_REG54_GET_MMU_WE(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_MMU_WE_MASK) >> MH_DEBUG_REG54_MMU_WE_SHIFT) +#define MH_DEBUG_REG54_GET_CTRL_TLBMISS_RE_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG54_GET_TLBMISS_CTRL_RTS(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG54_GET_MH_TLBMISS_SEND(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK) >> MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT) +#define MH_DEBUG_REG54_GET_MMU_STALL_AWAITING_TLB_MISS_FETCH(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK) >> MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT) +#define MH_DEBUG_REG54_GET_pa_in_mpu_range(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_pa_in_mpu_range_MASK) >> MH_DEBUG_REG54_pa_in_mpu_range_SHIFT) +#define MH_DEBUG_REG54_GET_stage1_valid(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_stage1_valid_MASK) >> MH_DEBUG_REG54_stage1_valid_SHIFT) +#define MH_DEBUG_REG54_GET_stage2_valid(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_stage2_valid_MASK) >> MH_DEBUG_REG54_stage2_valid_SHIFT) +#define MH_DEBUG_REG54_GET_client_behavior_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_client_behavior_q_MASK) >> MH_DEBUG_REG54_client_behavior_q_SHIFT) +#define MH_DEBUG_REG54_GET_IGNORE_TAG_MISS_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK) >> MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT) +#define MH_DEBUG_REG54_GET_tag_match_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_tag_match_q_MASK) >> MH_DEBUG_REG54_tag_match_q_SHIFT) +#define MH_DEBUG_REG54_GET_tag_miss_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_tag_miss_q_MASK) >> MH_DEBUG_REG54_tag_miss_q_SHIFT) +#define MH_DEBUG_REG54_GET_va_in_range_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_va_in_range_q_MASK) >> MH_DEBUG_REG54_va_in_range_q_SHIFT) +#define MH_DEBUG_REG54_GET_PTE_FETCH_COMPLETE_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK) >> MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT) +#define MH_DEBUG_REG54_GET_TAG_valid_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_TAG_valid_q_MASK) >> MH_DEBUG_REG54_TAG_valid_q_SHIFT) + +#define MH_DEBUG_REG54_SET_ARQ_RTR(mh_debug_reg54_reg, arq_rtr) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_ARQ_RTR_MASK) | (arq_rtr << MH_DEBUG_REG54_ARQ_RTR_SHIFT) +#define MH_DEBUG_REG54_SET_MMU_WE(mh_debug_reg54_reg, mmu_we) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG54_MMU_WE_SHIFT) +#define MH_DEBUG_REG54_SET_CTRL_TLBMISS_RE_q(mh_debug_reg54_reg, ctrl_tlbmiss_re_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG54_SET_TLBMISS_CTRL_RTS(mh_debug_reg54_reg, tlbmiss_ctrl_rts) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG54_SET_MH_TLBMISS_SEND(mh_debug_reg54_reg, mh_tlbmiss_send) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK) | (mh_tlbmiss_send << MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT) +#define MH_DEBUG_REG54_SET_MMU_STALL_AWAITING_TLB_MISS_FETCH(mh_debug_reg54_reg, mmu_stall_awaiting_tlb_miss_fetch) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK) | (mmu_stall_awaiting_tlb_miss_fetch << MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT) +#define MH_DEBUG_REG54_SET_pa_in_mpu_range(mh_debug_reg54_reg, pa_in_mpu_range) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_pa_in_mpu_range_MASK) | (pa_in_mpu_range << MH_DEBUG_REG54_pa_in_mpu_range_SHIFT) +#define MH_DEBUG_REG54_SET_stage1_valid(mh_debug_reg54_reg, stage1_valid) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_stage1_valid_MASK) | (stage1_valid << MH_DEBUG_REG54_stage1_valid_SHIFT) +#define MH_DEBUG_REG54_SET_stage2_valid(mh_debug_reg54_reg, stage2_valid) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_stage2_valid_MASK) | (stage2_valid << MH_DEBUG_REG54_stage2_valid_SHIFT) +#define MH_DEBUG_REG54_SET_client_behavior_q(mh_debug_reg54_reg, client_behavior_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_client_behavior_q_MASK) | (client_behavior_q << MH_DEBUG_REG54_client_behavior_q_SHIFT) +#define MH_DEBUG_REG54_SET_IGNORE_TAG_MISS_q(mh_debug_reg54_reg, ignore_tag_miss_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK) | (ignore_tag_miss_q << MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT) +#define MH_DEBUG_REG54_SET_tag_match_q(mh_debug_reg54_reg, tag_match_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_tag_match_q_MASK) | (tag_match_q << MH_DEBUG_REG54_tag_match_q_SHIFT) +#define MH_DEBUG_REG54_SET_tag_miss_q(mh_debug_reg54_reg, tag_miss_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_tag_miss_q_MASK) | (tag_miss_q << MH_DEBUG_REG54_tag_miss_q_SHIFT) +#define MH_DEBUG_REG54_SET_va_in_range_q(mh_debug_reg54_reg, va_in_range_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_va_in_range_q_MASK) | (va_in_range_q << MH_DEBUG_REG54_va_in_range_q_SHIFT) +#define MH_DEBUG_REG54_SET_PTE_FETCH_COMPLETE_q(mh_debug_reg54_reg, pte_fetch_complete_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK) | (pte_fetch_complete_q << MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT) +#define MH_DEBUG_REG54_SET_TAG_valid_q(mh_debug_reg54_reg, tag_valid_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TAG_valid_q_MASK) | (tag_valid_q << MH_DEBUG_REG54_TAG_valid_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg54_t { + unsigned int arq_rtr : MH_DEBUG_REG54_ARQ_RTR_SIZE; + unsigned int mmu_we : MH_DEBUG_REG54_MMU_WE_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SIZE; + unsigned int mh_tlbmiss_send : MH_DEBUG_REG54_MH_TLBMISS_SEND_SIZE; + unsigned int mmu_stall_awaiting_tlb_miss_fetch : MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE; + unsigned int pa_in_mpu_range : MH_DEBUG_REG54_pa_in_mpu_range_SIZE; + unsigned int stage1_valid : MH_DEBUG_REG54_stage1_valid_SIZE; + unsigned int stage2_valid : MH_DEBUG_REG54_stage2_valid_SIZE; + unsigned int client_behavior_q : MH_DEBUG_REG54_client_behavior_q_SIZE; + unsigned int ignore_tag_miss_q : MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SIZE; + unsigned int tag_match_q : MH_DEBUG_REG54_tag_match_q_SIZE; + unsigned int tag_miss_q : MH_DEBUG_REG54_tag_miss_q_SIZE; + unsigned int va_in_range_q : MH_DEBUG_REG54_va_in_range_q_SIZE; + unsigned int pte_fetch_complete_q : MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SIZE; + unsigned int tag_valid_q : MH_DEBUG_REG54_TAG_valid_q_SIZE; + } mh_debug_reg54_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg54_t { + unsigned int tag_valid_q : MH_DEBUG_REG54_TAG_valid_q_SIZE; + unsigned int pte_fetch_complete_q : MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SIZE; + unsigned int va_in_range_q : MH_DEBUG_REG54_va_in_range_q_SIZE; + unsigned int tag_miss_q : MH_DEBUG_REG54_tag_miss_q_SIZE; + unsigned int tag_match_q : MH_DEBUG_REG54_tag_match_q_SIZE; + unsigned int ignore_tag_miss_q : MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SIZE; + unsigned int client_behavior_q : MH_DEBUG_REG54_client_behavior_q_SIZE; + unsigned int stage2_valid : MH_DEBUG_REG54_stage2_valid_SIZE; + unsigned int stage1_valid : MH_DEBUG_REG54_stage1_valid_SIZE; + unsigned int pa_in_mpu_range : MH_DEBUG_REG54_pa_in_mpu_range_SIZE; + unsigned int mmu_stall_awaiting_tlb_miss_fetch : MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE; + unsigned int mh_tlbmiss_send : MH_DEBUG_REG54_MH_TLBMISS_SEND_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SIZE; + unsigned int mmu_we : MH_DEBUG_REG54_MMU_WE_SIZE; + unsigned int arq_rtr : MH_DEBUG_REG54_ARQ_RTR_SIZE; + } mh_debug_reg54_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg54_t f; +} mh_debug_reg54_u; + + +/* + * MH_DEBUG_REG55 struct + */ + +#define MH_DEBUG_REG55_TAG0_VA_SIZE 13 +#define MH_DEBUG_REG55_TAG_valid_q_0_SIZE 1 +#define MH_DEBUG_REG55_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG55_TAG1_VA_SIZE 13 +#define MH_DEBUG_REG55_TAG_valid_q_1_SIZE 1 + +#define MH_DEBUG_REG55_TAG0_VA_SHIFT 0 +#define MH_DEBUG_REG55_TAG_valid_q_0_SHIFT 13 +#define MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG55_TAG1_VA_SHIFT 16 +#define MH_DEBUG_REG55_TAG_valid_q_1_SHIFT 29 + +#define MH_DEBUG_REG55_TAG0_VA_MASK 0x00001fff +#define MH_DEBUG_REG55_TAG_valid_q_0_MASK 0x00002000 +#define MH_DEBUG_REG55_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG55_TAG1_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG55_TAG_valid_q_1_MASK 0x20000000 + +#define MH_DEBUG_REG55_MASK \ + (MH_DEBUG_REG55_TAG0_VA_MASK | \ + MH_DEBUG_REG55_TAG_valid_q_0_MASK | \ + MH_DEBUG_REG55_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG55_TAG1_VA_MASK | \ + MH_DEBUG_REG55_TAG_valid_q_1_MASK) + +#define MH_DEBUG_REG55(tag0_va, tag_valid_q_0, always_zero, tag1_va, tag_valid_q_1) \ + ((tag0_va << MH_DEBUG_REG55_TAG0_VA_SHIFT) | \ + (tag_valid_q_0 << MH_DEBUG_REG55_TAG_valid_q_0_SHIFT) | \ + (always_zero << MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT) | \ + (tag1_va << MH_DEBUG_REG55_TAG1_VA_SHIFT) | \ + (tag_valid_q_1 << MH_DEBUG_REG55_TAG_valid_q_1_SHIFT)) + +#define MH_DEBUG_REG55_GET_TAG0_VA(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_TAG0_VA_MASK) >> MH_DEBUG_REG55_TAG0_VA_SHIFT) +#define MH_DEBUG_REG55_GET_TAG_valid_q_0(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_TAG_valid_q_0_MASK) >> MH_DEBUG_REG55_TAG_valid_q_0_SHIFT) +#define MH_DEBUG_REG55_GET_ALWAYS_ZERO(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG55_GET_TAG1_VA(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_TAG1_VA_MASK) >> MH_DEBUG_REG55_TAG1_VA_SHIFT) +#define MH_DEBUG_REG55_GET_TAG_valid_q_1(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_TAG_valid_q_1_MASK) >> MH_DEBUG_REG55_TAG_valid_q_1_SHIFT) + +#define MH_DEBUG_REG55_SET_TAG0_VA(mh_debug_reg55_reg, tag0_va) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG0_VA_MASK) | (tag0_va << MH_DEBUG_REG55_TAG0_VA_SHIFT) +#define MH_DEBUG_REG55_SET_TAG_valid_q_0(mh_debug_reg55_reg, tag_valid_q_0) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG_valid_q_0_MASK) | (tag_valid_q_0 << MH_DEBUG_REG55_TAG_valid_q_0_SHIFT) +#define MH_DEBUG_REG55_SET_ALWAYS_ZERO(mh_debug_reg55_reg, always_zero) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG55_SET_TAG1_VA(mh_debug_reg55_reg, tag1_va) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG1_VA_MASK) | (tag1_va << MH_DEBUG_REG55_TAG1_VA_SHIFT) +#define MH_DEBUG_REG55_SET_TAG_valid_q_1(mh_debug_reg55_reg, tag_valid_q_1) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG_valid_q_1_MASK) | (tag_valid_q_1 << MH_DEBUG_REG55_TAG_valid_q_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg55_t { + unsigned int tag0_va : MH_DEBUG_REG55_TAG0_VA_SIZE; + unsigned int tag_valid_q_0 : MH_DEBUG_REG55_TAG_valid_q_0_SIZE; + unsigned int always_zero : MH_DEBUG_REG55_ALWAYS_ZERO_SIZE; + unsigned int tag1_va : MH_DEBUG_REG55_TAG1_VA_SIZE; + unsigned int tag_valid_q_1 : MH_DEBUG_REG55_TAG_valid_q_1_SIZE; + unsigned int : 2; + } mh_debug_reg55_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg55_t { + unsigned int : 2; + unsigned int tag_valid_q_1 : MH_DEBUG_REG55_TAG_valid_q_1_SIZE; + unsigned int tag1_va : MH_DEBUG_REG55_TAG1_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG55_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_0 : MH_DEBUG_REG55_TAG_valid_q_0_SIZE; + unsigned int tag0_va : MH_DEBUG_REG55_TAG0_VA_SIZE; + } mh_debug_reg55_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg55_t f; +} mh_debug_reg55_u; + + +/* + * MH_DEBUG_REG56 struct + */ + +#define MH_DEBUG_REG56_TAG2_VA_SIZE 13 +#define MH_DEBUG_REG56_TAG_valid_q_2_SIZE 1 +#define MH_DEBUG_REG56_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG56_TAG3_VA_SIZE 13 +#define MH_DEBUG_REG56_TAG_valid_q_3_SIZE 1 + +#define MH_DEBUG_REG56_TAG2_VA_SHIFT 0 +#define MH_DEBUG_REG56_TAG_valid_q_2_SHIFT 13 +#define MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG56_TAG3_VA_SHIFT 16 +#define MH_DEBUG_REG56_TAG_valid_q_3_SHIFT 29 + +#define MH_DEBUG_REG56_TAG2_VA_MASK 0x00001fff +#define MH_DEBUG_REG56_TAG_valid_q_2_MASK 0x00002000 +#define MH_DEBUG_REG56_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG56_TAG3_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG56_TAG_valid_q_3_MASK 0x20000000 + +#define MH_DEBUG_REG56_MASK \ + (MH_DEBUG_REG56_TAG2_VA_MASK | \ + MH_DEBUG_REG56_TAG_valid_q_2_MASK | \ + MH_DEBUG_REG56_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG56_TAG3_VA_MASK | \ + MH_DEBUG_REG56_TAG_valid_q_3_MASK) + +#define MH_DEBUG_REG56(tag2_va, tag_valid_q_2, always_zero, tag3_va, tag_valid_q_3) \ + ((tag2_va << MH_DEBUG_REG56_TAG2_VA_SHIFT) | \ + (tag_valid_q_2 << MH_DEBUG_REG56_TAG_valid_q_2_SHIFT) | \ + (always_zero << MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT) | \ + (tag3_va << MH_DEBUG_REG56_TAG3_VA_SHIFT) | \ + (tag_valid_q_3 << MH_DEBUG_REG56_TAG_valid_q_3_SHIFT)) + +#define MH_DEBUG_REG56_GET_TAG2_VA(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_TAG2_VA_MASK) >> MH_DEBUG_REG56_TAG2_VA_SHIFT) +#define MH_DEBUG_REG56_GET_TAG_valid_q_2(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_TAG_valid_q_2_MASK) >> MH_DEBUG_REG56_TAG_valid_q_2_SHIFT) +#define MH_DEBUG_REG56_GET_ALWAYS_ZERO(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG56_GET_TAG3_VA(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_TAG3_VA_MASK) >> MH_DEBUG_REG56_TAG3_VA_SHIFT) +#define MH_DEBUG_REG56_GET_TAG_valid_q_3(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_TAG_valid_q_3_MASK) >> MH_DEBUG_REG56_TAG_valid_q_3_SHIFT) + +#define MH_DEBUG_REG56_SET_TAG2_VA(mh_debug_reg56_reg, tag2_va) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG2_VA_MASK) | (tag2_va << MH_DEBUG_REG56_TAG2_VA_SHIFT) +#define MH_DEBUG_REG56_SET_TAG_valid_q_2(mh_debug_reg56_reg, tag_valid_q_2) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG_valid_q_2_MASK) | (tag_valid_q_2 << MH_DEBUG_REG56_TAG_valid_q_2_SHIFT) +#define MH_DEBUG_REG56_SET_ALWAYS_ZERO(mh_debug_reg56_reg, always_zero) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG56_SET_TAG3_VA(mh_debug_reg56_reg, tag3_va) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG3_VA_MASK) | (tag3_va << MH_DEBUG_REG56_TAG3_VA_SHIFT) +#define MH_DEBUG_REG56_SET_TAG_valid_q_3(mh_debug_reg56_reg, tag_valid_q_3) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG_valid_q_3_MASK) | (tag_valid_q_3 << MH_DEBUG_REG56_TAG_valid_q_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg56_t { + unsigned int tag2_va : MH_DEBUG_REG56_TAG2_VA_SIZE; + unsigned int tag_valid_q_2 : MH_DEBUG_REG56_TAG_valid_q_2_SIZE; + unsigned int always_zero : MH_DEBUG_REG56_ALWAYS_ZERO_SIZE; + unsigned int tag3_va : MH_DEBUG_REG56_TAG3_VA_SIZE; + unsigned int tag_valid_q_3 : MH_DEBUG_REG56_TAG_valid_q_3_SIZE; + unsigned int : 2; + } mh_debug_reg56_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg56_t { + unsigned int : 2; + unsigned int tag_valid_q_3 : MH_DEBUG_REG56_TAG_valid_q_3_SIZE; + unsigned int tag3_va : MH_DEBUG_REG56_TAG3_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG56_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_2 : MH_DEBUG_REG56_TAG_valid_q_2_SIZE; + unsigned int tag2_va : MH_DEBUG_REG56_TAG2_VA_SIZE; + } mh_debug_reg56_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg56_t f; +} mh_debug_reg56_u; + + +/* + * MH_DEBUG_REG57 struct + */ + +#define MH_DEBUG_REG57_TAG4_VA_SIZE 13 +#define MH_DEBUG_REG57_TAG_valid_q_4_SIZE 1 +#define MH_DEBUG_REG57_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG57_TAG5_VA_SIZE 13 +#define MH_DEBUG_REG57_TAG_valid_q_5_SIZE 1 + +#define MH_DEBUG_REG57_TAG4_VA_SHIFT 0 +#define MH_DEBUG_REG57_TAG_valid_q_4_SHIFT 13 +#define MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG57_TAG5_VA_SHIFT 16 +#define MH_DEBUG_REG57_TAG_valid_q_5_SHIFT 29 + +#define MH_DEBUG_REG57_TAG4_VA_MASK 0x00001fff +#define MH_DEBUG_REG57_TAG_valid_q_4_MASK 0x00002000 +#define MH_DEBUG_REG57_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG57_TAG5_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG57_TAG_valid_q_5_MASK 0x20000000 + +#define MH_DEBUG_REG57_MASK \ + (MH_DEBUG_REG57_TAG4_VA_MASK | \ + MH_DEBUG_REG57_TAG_valid_q_4_MASK | \ + MH_DEBUG_REG57_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG57_TAG5_VA_MASK | \ + MH_DEBUG_REG57_TAG_valid_q_5_MASK) + +#define MH_DEBUG_REG57(tag4_va, tag_valid_q_4, always_zero, tag5_va, tag_valid_q_5) \ + ((tag4_va << MH_DEBUG_REG57_TAG4_VA_SHIFT) | \ + (tag_valid_q_4 << MH_DEBUG_REG57_TAG_valid_q_4_SHIFT) | \ + (always_zero << MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT) | \ + (tag5_va << MH_DEBUG_REG57_TAG5_VA_SHIFT) | \ + (tag_valid_q_5 << MH_DEBUG_REG57_TAG_valid_q_5_SHIFT)) + +#define MH_DEBUG_REG57_GET_TAG4_VA(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_TAG4_VA_MASK) >> MH_DEBUG_REG57_TAG4_VA_SHIFT) +#define MH_DEBUG_REG57_GET_TAG_valid_q_4(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_TAG_valid_q_4_MASK) >> MH_DEBUG_REG57_TAG_valid_q_4_SHIFT) +#define MH_DEBUG_REG57_GET_ALWAYS_ZERO(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG57_GET_TAG5_VA(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_TAG5_VA_MASK) >> MH_DEBUG_REG57_TAG5_VA_SHIFT) +#define MH_DEBUG_REG57_GET_TAG_valid_q_5(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_TAG_valid_q_5_MASK) >> MH_DEBUG_REG57_TAG_valid_q_5_SHIFT) + +#define MH_DEBUG_REG57_SET_TAG4_VA(mh_debug_reg57_reg, tag4_va) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG4_VA_MASK) | (tag4_va << MH_DEBUG_REG57_TAG4_VA_SHIFT) +#define MH_DEBUG_REG57_SET_TAG_valid_q_4(mh_debug_reg57_reg, tag_valid_q_4) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG_valid_q_4_MASK) | (tag_valid_q_4 << MH_DEBUG_REG57_TAG_valid_q_4_SHIFT) +#define MH_DEBUG_REG57_SET_ALWAYS_ZERO(mh_debug_reg57_reg, always_zero) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG57_SET_TAG5_VA(mh_debug_reg57_reg, tag5_va) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG5_VA_MASK) | (tag5_va << MH_DEBUG_REG57_TAG5_VA_SHIFT) +#define MH_DEBUG_REG57_SET_TAG_valid_q_5(mh_debug_reg57_reg, tag_valid_q_5) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG_valid_q_5_MASK) | (tag_valid_q_5 << MH_DEBUG_REG57_TAG_valid_q_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg57_t { + unsigned int tag4_va : MH_DEBUG_REG57_TAG4_VA_SIZE; + unsigned int tag_valid_q_4 : MH_DEBUG_REG57_TAG_valid_q_4_SIZE; + unsigned int always_zero : MH_DEBUG_REG57_ALWAYS_ZERO_SIZE; + unsigned int tag5_va : MH_DEBUG_REG57_TAG5_VA_SIZE; + unsigned int tag_valid_q_5 : MH_DEBUG_REG57_TAG_valid_q_5_SIZE; + unsigned int : 2; + } mh_debug_reg57_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg57_t { + unsigned int : 2; + unsigned int tag_valid_q_5 : MH_DEBUG_REG57_TAG_valid_q_5_SIZE; + unsigned int tag5_va : MH_DEBUG_REG57_TAG5_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG57_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_4 : MH_DEBUG_REG57_TAG_valid_q_4_SIZE; + unsigned int tag4_va : MH_DEBUG_REG57_TAG4_VA_SIZE; + } mh_debug_reg57_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg57_t f; +} mh_debug_reg57_u; + + +/* + * MH_DEBUG_REG58 struct + */ + +#define MH_DEBUG_REG58_TAG6_VA_SIZE 13 +#define MH_DEBUG_REG58_TAG_valid_q_6_SIZE 1 +#define MH_DEBUG_REG58_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG58_TAG7_VA_SIZE 13 +#define MH_DEBUG_REG58_TAG_valid_q_7_SIZE 1 + +#define MH_DEBUG_REG58_TAG6_VA_SHIFT 0 +#define MH_DEBUG_REG58_TAG_valid_q_6_SHIFT 13 +#define MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG58_TAG7_VA_SHIFT 16 +#define MH_DEBUG_REG58_TAG_valid_q_7_SHIFT 29 + +#define MH_DEBUG_REG58_TAG6_VA_MASK 0x00001fff +#define MH_DEBUG_REG58_TAG_valid_q_6_MASK 0x00002000 +#define MH_DEBUG_REG58_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG58_TAG7_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG58_TAG_valid_q_7_MASK 0x20000000 + +#define MH_DEBUG_REG58_MASK \ + (MH_DEBUG_REG58_TAG6_VA_MASK | \ + MH_DEBUG_REG58_TAG_valid_q_6_MASK | \ + MH_DEBUG_REG58_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG58_TAG7_VA_MASK | \ + MH_DEBUG_REG58_TAG_valid_q_7_MASK) + +#define MH_DEBUG_REG58(tag6_va, tag_valid_q_6, always_zero, tag7_va, tag_valid_q_7) \ + ((tag6_va << MH_DEBUG_REG58_TAG6_VA_SHIFT) | \ + (tag_valid_q_6 << MH_DEBUG_REG58_TAG_valid_q_6_SHIFT) | \ + (always_zero << MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT) | \ + (tag7_va << MH_DEBUG_REG58_TAG7_VA_SHIFT) | \ + (tag_valid_q_7 << MH_DEBUG_REG58_TAG_valid_q_7_SHIFT)) + +#define MH_DEBUG_REG58_GET_TAG6_VA(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_TAG6_VA_MASK) >> MH_DEBUG_REG58_TAG6_VA_SHIFT) +#define MH_DEBUG_REG58_GET_TAG_valid_q_6(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_TAG_valid_q_6_MASK) >> MH_DEBUG_REG58_TAG_valid_q_6_SHIFT) +#define MH_DEBUG_REG58_GET_ALWAYS_ZERO(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG58_GET_TAG7_VA(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_TAG7_VA_MASK) >> MH_DEBUG_REG58_TAG7_VA_SHIFT) +#define MH_DEBUG_REG58_GET_TAG_valid_q_7(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_TAG_valid_q_7_MASK) >> MH_DEBUG_REG58_TAG_valid_q_7_SHIFT) + +#define MH_DEBUG_REG58_SET_TAG6_VA(mh_debug_reg58_reg, tag6_va) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG6_VA_MASK) | (tag6_va << MH_DEBUG_REG58_TAG6_VA_SHIFT) +#define MH_DEBUG_REG58_SET_TAG_valid_q_6(mh_debug_reg58_reg, tag_valid_q_6) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG_valid_q_6_MASK) | (tag_valid_q_6 << MH_DEBUG_REG58_TAG_valid_q_6_SHIFT) +#define MH_DEBUG_REG58_SET_ALWAYS_ZERO(mh_debug_reg58_reg, always_zero) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG58_SET_TAG7_VA(mh_debug_reg58_reg, tag7_va) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG7_VA_MASK) | (tag7_va << MH_DEBUG_REG58_TAG7_VA_SHIFT) +#define MH_DEBUG_REG58_SET_TAG_valid_q_7(mh_debug_reg58_reg, tag_valid_q_7) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG_valid_q_7_MASK) | (tag_valid_q_7 << MH_DEBUG_REG58_TAG_valid_q_7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg58_t { + unsigned int tag6_va : MH_DEBUG_REG58_TAG6_VA_SIZE; + unsigned int tag_valid_q_6 : MH_DEBUG_REG58_TAG_valid_q_6_SIZE; + unsigned int always_zero : MH_DEBUG_REG58_ALWAYS_ZERO_SIZE; + unsigned int tag7_va : MH_DEBUG_REG58_TAG7_VA_SIZE; + unsigned int tag_valid_q_7 : MH_DEBUG_REG58_TAG_valid_q_7_SIZE; + unsigned int : 2; + } mh_debug_reg58_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg58_t { + unsigned int : 2; + unsigned int tag_valid_q_7 : MH_DEBUG_REG58_TAG_valid_q_7_SIZE; + unsigned int tag7_va : MH_DEBUG_REG58_TAG7_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG58_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_6 : MH_DEBUG_REG58_TAG_valid_q_6_SIZE; + unsigned int tag6_va : MH_DEBUG_REG58_TAG6_VA_SIZE; + } mh_debug_reg58_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg58_t f; +} mh_debug_reg58_u; + + +/* + * MH_DEBUG_REG59 struct + */ + +#define MH_DEBUG_REG59_TAG8_VA_SIZE 13 +#define MH_DEBUG_REG59_TAG_valid_q_8_SIZE 1 +#define MH_DEBUG_REG59_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG59_TAG9_VA_SIZE 13 +#define MH_DEBUG_REG59_TAG_valid_q_9_SIZE 1 + +#define MH_DEBUG_REG59_TAG8_VA_SHIFT 0 +#define MH_DEBUG_REG59_TAG_valid_q_8_SHIFT 13 +#define MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG59_TAG9_VA_SHIFT 16 +#define MH_DEBUG_REG59_TAG_valid_q_9_SHIFT 29 + +#define MH_DEBUG_REG59_TAG8_VA_MASK 0x00001fff +#define MH_DEBUG_REG59_TAG_valid_q_8_MASK 0x00002000 +#define MH_DEBUG_REG59_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG59_TAG9_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG59_TAG_valid_q_9_MASK 0x20000000 + +#define MH_DEBUG_REG59_MASK \ + (MH_DEBUG_REG59_TAG8_VA_MASK | \ + MH_DEBUG_REG59_TAG_valid_q_8_MASK | \ + MH_DEBUG_REG59_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG59_TAG9_VA_MASK | \ + MH_DEBUG_REG59_TAG_valid_q_9_MASK) + +#define MH_DEBUG_REG59(tag8_va, tag_valid_q_8, always_zero, tag9_va, tag_valid_q_9) \ + ((tag8_va << MH_DEBUG_REG59_TAG8_VA_SHIFT) | \ + (tag_valid_q_8 << MH_DEBUG_REG59_TAG_valid_q_8_SHIFT) | \ + (always_zero << MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT) | \ + (tag9_va << MH_DEBUG_REG59_TAG9_VA_SHIFT) | \ + (tag_valid_q_9 << MH_DEBUG_REG59_TAG_valid_q_9_SHIFT)) + +#define MH_DEBUG_REG59_GET_TAG8_VA(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_TAG8_VA_MASK) >> MH_DEBUG_REG59_TAG8_VA_SHIFT) +#define MH_DEBUG_REG59_GET_TAG_valid_q_8(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_TAG_valid_q_8_MASK) >> MH_DEBUG_REG59_TAG_valid_q_8_SHIFT) +#define MH_DEBUG_REG59_GET_ALWAYS_ZERO(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG59_GET_TAG9_VA(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_TAG9_VA_MASK) >> MH_DEBUG_REG59_TAG9_VA_SHIFT) +#define MH_DEBUG_REG59_GET_TAG_valid_q_9(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_TAG_valid_q_9_MASK) >> MH_DEBUG_REG59_TAG_valid_q_9_SHIFT) + +#define MH_DEBUG_REG59_SET_TAG8_VA(mh_debug_reg59_reg, tag8_va) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG8_VA_MASK) | (tag8_va << MH_DEBUG_REG59_TAG8_VA_SHIFT) +#define MH_DEBUG_REG59_SET_TAG_valid_q_8(mh_debug_reg59_reg, tag_valid_q_8) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG_valid_q_8_MASK) | (tag_valid_q_8 << MH_DEBUG_REG59_TAG_valid_q_8_SHIFT) +#define MH_DEBUG_REG59_SET_ALWAYS_ZERO(mh_debug_reg59_reg, always_zero) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG59_SET_TAG9_VA(mh_debug_reg59_reg, tag9_va) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG9_VA_MASK) | (tag9_va << MH_DEBUG_REG59_TAG9_VA_SHIFT) +#define MH_DEBUG_REG59_SET_TAG_valid_q_9(mh_debug_reg59_reg, tag_valid_q_9) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG_valid_q_9_MASK) | (tag_valid_q_9 << MH_DEBUG_REG59_TAG_valid_q_9_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg59_t { + unsigned int tag8_va : MH_DEBUG_REG59_TAG8_VA_SIZE; + unsigned int tag_valid_q_8 : MH_DEBUG_REG59_TAG_valid_q_8_SIZE; + unsigned int always_zero : MH_DEBUG_REG59_ALWAYS_ZERO_SIZE; + unsigned int tag9_va : MH_DEBUG_REG59_TAG9_VA_SIZE; + unsigned int tag_valid_q_9 : MH_DEBUG_REG59_TAG_valid_q_9_SIZE; + unsigned int : 2; + } mh_debug_reg59_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg59_t { + unsigned int : 2; + unsigned int tag_valid_q_9 : MH_DEBUG_REG59_TAG_valid_q_9_SIZE; + unsigned int tag9_va : MH_DEBUG_REG59_TAG9_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG59_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_8 : MH_DEBUG_REG59_TAG_valid_q_8_SIZE; + unsigned int tag8_va : MH_DEBUG_REG59_TAG8_VA_SIZE; + } mh_debug_reg59_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg59_t f; +} mh_debug_reg59_u; + + +/* + * MH_DEBUG_REG60 struct + */ + +#define MH_DEBUG_REG60_TAG10_VA_SIZE 13 +#define MH_DEBUG_REG60_TAG_valid_q_10_SIZE 1 +#define MH_DEBUG_REG60_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG60_TAG11_VA_SIZE 13 +#define MH_DEBUG_REG60_TAG_valid_q_11_SIZE 1 + +#define MH_DEBUG_REG60_TAG10_VA_SHIFT 0 +#define MH_DEBUG_REG60_TAG_valid_q_10_SHIFT 13 +#define MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG60_TAG11_VA_SHIFT 16 +#define MH_DEBUG_REG60_TAG_valid_q_11_SHIFT 29 + +#define MH_DEBUG_REG60_TAG10_VA_MASK 0x00001fff +#define MH_DEBUG_REG60_TAG_valid_q_10_MASK 0x00002000 +#define MH_DEBUG_REG60_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG60_TAG11_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG60_TAG_valid_q_11_MASK 0x20000000 + +#define MH_DEBUG_REG60_MASK \ + (MH_DEBUG_REG60_TAG10_VA_MASK | \ + MH_DEBUG_REG60_TAG_valid_q_10_MASK | \ + MH_DEBUG_REG60_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG60_TAG11_VA_MASK | \ + MH_DEBUG_REG60_TAG_valid_q_11_MASK) + +#define MH_DEBUG_REG60(tag10_va, tag_valid_q_10, always_zero, tag11_va, tag_valid_q_11) \ + ((tag10_va << MH_DEBUG_REG60_TAG10_VA_SHIFT) | \ + (tag_valid_q_10 << MH_DEBUG_REG60_TAG_valid_q_10_SHIFT) | \ + (always_zero << MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT) | \ + (tag11_va << MH_DEBUG_REG60_TAG11_VA_SHIFT) | \ + (tag_valid_q_11 << MH_DEBUG_REG60_TAG_valid_q_11_SHIFT)) + +#define MH_DEBUG_REG60_GET_TAG10_VA(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_TAG10_VA_MASK) >> MH_DEBUG_REG60_TAG10_VA_SHIFT) +#define MH_DEBUG_REG60_GET_TAG_valid_q_10(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_TAG_valid_q_10_MASK) >> MH_DEBUG_REG60_TAG_valid_q_10_SHIFT) +#define MH_DEBUG_REG60_GET_ALWAYS_ZERO(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG60_GET_TAG11_VA(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_TAG11_VA_MASK) >> MH_DEBUG_REG60_TAG11_VA_SHIFT) +#define MH_DEBUG_REG60_GET_TAG_valid_q_11(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_TAG_valid_q_11_MASK) >> MH_DEBUG_REG60_TAG_valid_q_11_SHIFT) + +#define MH_DEBUG_REG60_SET_TAG10_VA(mh_debug_reg60_reg, tag10_va) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG10_VA_MASK) | (tag10_va << MH_DEBUG_REG60_TAG10_VA_SHIFT) +#define MH_DEBUG_REG60_SET_TAG_valid_q_10(mh_debug_reg60_reg, tag_valid_q_10) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG_valid_q_10_MASK) | (tag_valid_q_10 << MH_DEBUG_REG60_TAG_valid_q_10_SHIFT) +#define MH_DEBUG_REG60_SET_ALWAYS_ZERO(mh_debug_reg60_reg, always_zero) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG60_SET_TAG11_VA(mh_debug_reg60_reg, tag11_va) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG11_VA_MASK) | (tag11_va << MH_DEBUG_REG60_TAG11_VA_SHIFT) +#define MH_DEBUG_REG60_SET_TAG_valid_q_11(mh_debug_reg60_reg, tag_valid_q_11) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG_valid_q_11_MASK) | (tag_valid_q_11 << MH_DEBUG_REG60_TAG_valid_q_11_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg60_t { + unsigned int tag10_va : MH_DEBUG_REG60_TAG10_VA_SIZE; + unsigned int tag_valid_q_10 : MH_DEBUG_REG60_TAG_valid_q_10_SIZE; + unsigned int always_zero : MH_DEBUG_REG60_ALWAYS_ZERO_SIZE; + unsigned int tag11_va : MH_DEBUG_REG60_TAG11_VA_SIZE; + unsigned int tag_valid_q_11 : MH_DEBUG_REG60_TAG_valid_q_11_SIZE; + unsigned int : 2; + } mh_debug_reg60_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg60_t { + unsigned int : 2; + unsigned int tag_valid_q_11 : MH_DEBUG_REG60_TAG_valid_q_11_SIZE; + unsigned int tag11_va : MH_DEBUG_REG60_TAG11_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG60_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_10 : MH_DEBUG_REG60_TAG_valid_q_10_SIZE; + unsigned int tag10_va : MH_DEBUG_REG60_TAG10_VA_SIZE; + } mh_debug_reg60_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg60_t f; +} mh_debug_reg60_u; + + +/* + * MH_DEBUG_REG61 struct + */ + +#define MH_DEBUG_REG61_TAG12_VA_SIZE 13 +#define MH_DEBUG_REG61_TAG_valid_q_12_SIZE 1 +#define MH_DEBUG_REG61_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG61_TAG13_VA_SIZE 13 +#define MH_DEBUG_REG61_TAG_valid_q_13_SIZE 1 + +#define MH_DEBUG_REG61_TAG12_VA_SHIFT 0 +#define MH_DEBUG_REG61_TAG_valid_q_12_SHIFT 13 +#define MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG61_TAG13_VA_SHIFT 16 +#define MH_DEBUG_REG61_TAG_valid_q_13_SHIFT 29 + +#define MH_DEBUG_REG61_TAG12_VA_MASK 0x00001fff +#define MH_DEBUG_REG61_TAG_valid_q_12_MASK 0x00002000 +#define MH_DEBUG_REG61_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG61_TAG13_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG61_TAG_valid_q_13_MASK 0x20000000 + +#define MH_DEBUG_REG61_MASK \ + (MH_DEBUG_REG61_TAG12_VA_MASK | \ + MH_DEBUG_REG61_TAG_valid_q_12_MASK | \ + MH_DEBUG_REG61_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG61_TAG13_VA_MASK | \ + MH_DEBUG_REG61_TAG_valid_q_13_MASK) + +#define MH_DEBUG_REG61(tag12_va, tag_valid_q_12, always_zero, tag13_va, tag_valid_q_13) \ + ((tag12_va << MH_DEBUG_REG61_TAG12_VA_SHIFT) | \ + (tag_valid_q_12 << MH_DEBUG_REG61_TAG_valid_q_12_SHIFT) | \ + (always_zero << MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT) | \ + (tag13_va << MH_DEBUG_REG61_TAG13_VA_SHIFT) | \ + (tag_valid_q_13 << MH_DEBUG_REG61_TAG_valid_q_13_SHIFT)) + +#define MH_DEBUG_REG61_GET_TAG12_VA(mh_debug_reg61) \ + ((mh_debug_reg61 & MH_DEBUG_REG61_TAG12_VA_MASK) >> MH_DEBUG_REG61_TAG12_VA_SHIFT) +#define MH_DEBUG_REG61_GET_TAG_valid_q_12(mh_debug_reg61) \ + ((mh_debug_reg61 & MH_DEBUG_REG61_TAG_valid_q_12_MASK) >> MH_DEBUG_REG61_TAG_valid_q_12_SHIFT) +#define MH_DEBUG_REG61_GET_ALWAYS_ZERO(mh_debug_reg61) \ + ((mh_debug_reg61 & MH_DEBUG_REG61_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG61_GET_TAG13_VA(mh_debug_reg61) \ + ((mh_debug_reg61 & MH_DEBUG_REG61_TAG13_VA_MASK) >> MH_DEBUG_REG61_TAG13_VA_SHIFT) +#define MH_DEBUG_REG61_GET_TAG_valid_q_13(mh_debug_reg61) \ + ((mh_debug_reg61 & MH_DEBUG_REG61_TAG_valid_q_13_MASK) >> MH_DEBUG_REG61_TAG_valid_q_13_SHIFT) + +#define MH_DEBUG_REG61_SET_TAG12_VA(mh_debug_reg61_reg, tag12_va) \ + mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG12_VA_MASK) | (tag12_va << MH_DEBUG_REG61_TAG12_VA_SHIFT) +#define MH_DEBUG_REG61_SET_TAG_valid_q_12(mh_debug_reg61_reg, tag_valid_q_12) \ + mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG_valid_q_12_MASK) | (tag_valid_q_12 << MH_DEBUG_REG61_TAG_valid_q_12_SHIFT) +#define MH_DEBUG_REG61_SET_ALWAYS_ZERO(mh_debug_reg61_reg, always_zero) \ + mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG61_SET_TAG13_VA(mh_debug_reg61_reg, tag13_va) \ + mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG13_VA_MASK) | (tag13_va << MH_DEBUG_REG61_TAG13_VA_SHIFT) +#define MH_DEBUG_REG61_SET_TAG_valid_q_13(mh_debug_reg61_reg, tag_valid_q_13) \ + mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG_valid_q_13_MASK) | (tag_valid_q_13 << MH_DEBUG_REG61_TAG_valid_q_13_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg61_t { + unsigned int tag12_va : MH_DEBUG_REG61_TAG12_VA_SIZE; + unsigned int tag_valid_q_12 : MH_DEBUG_REG61_TAG_valid_q_12_SIZE; + unsigned int always_zero : MH_DEBUG_REG61_ALWAYS_ZERO_SIZE; + unsigned int tag13_va : MH_DEBUG_REG61_TAG13_VA_SIZE; + unsigned int tag_valid_q_13 : MH_DEBUG_REG61_TAG_valid_q_13_SIZE; + unsigned int : 2; + } mh_debug_reg61_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg61_t { + unsigned int : 2; + unsigned int tag_valid_q_13 : MH_DEBUG_REG61_TAG_valid_q_13_SIZE; + unsigned int tag13_va : MH_DEBUG_REG61_TAG13_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG61_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_12 : MH_DEBUG_REG61_TAG_valid_q_12_SIZE; + unsigned int tag12_va : MH_DEBUG_REG61_TAG12_VA_SIZE; + } mh_debug_reg61_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg61_t f; +} mh_debug_reg61_u; + + +/* + * MH_DEBUG_REG62 struct + */ + +#define MH_DEBUG_REG62_TAG14_VA_SIZE 13 +#define MH_DEBUG_REG62_TAG_valid_q_14_SIZE 1 +#define MH_DEBUG_REG62_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG62_TAG15_VA_SIZE 13 +#define MH_DEBUG_REG62_TAG_valid_q_15_SIZE 1 + +#define MH_DEBUG_REG62_TAG14_VA_SHIFT 0 +#define MH_DEBUG_REG62_TAG_valid_q_14_SHIFT 13 +#define MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG62_TAG15_VA_SHIFT 16 +#define MH_DEBUG_REG62_TAG_valid_q_15_SHIFT 29 + +#define MH_DEBUG_REG62_TAG14_VA_MASK 0x00001fff +#define MH_DEBUG_REG62_TAG_valid_q_14_MASK 0x00002000 +#define MH_DEBUG_REG62_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG62_TAG15_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG62_TAG_valid_q_15_MASK 0x20000000 + +#define MH_DEBUG_REG62_MASK \ + (MH_DEBUG_REG62_TAG14_VA_MASK | \ + MH_DEBUG_REG62_TAG_valid_q_14_MASK | \ + MH_DEBUG_REG62_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG62_TAG15_VA_MASK | \ + MH_DEBUG_REG62_TAG_valid_q_15_MASK) + +#define MH_DEBUG_REG62(tag14_va, tag_valid_q_14, always_zero, tag15_va, tag_valid_q_15) \ + ((tag14_va << MH_DEBUG_REG62_TAG14_VA_SHIFT) | \ + (tag_valid_q_14 << MH_DEBUG_REG62_TAG_valid_q_14_SHIFT) | \ + (always_zero << MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT) | \ + (tag15_va << MH_DEBUG_REG62_TAG15_VA_SHIFT) | \ + (tag_valid_q_15 << MH_DEBUG_REG62_TAG_valid_q_15_SHIFT)) + +#define MH_DEBUG_REG62_GET_TAG14_VA(mh_debug_reg62) \ + ((mh_debug_reg62 & MH_DEBUG_REG62_TAG14_VA_MASK) >> MH_DEBUG_REG62_TAG14_VA_SHIFT) +#define MH_DEBUG_REG62_GET_TAG_valid_q_14(mh_debug_reg62) \ + ((mh_debug_reg62 & MH_DEBUG_REG62_TAG_valid_q_14_MASK) >> MH_DEBUG_REG62_TAG_valid_q_14_SHIFT) +#define MH_DEBUG_REG62_GET_ALWAYS_ZERO(mh_debug_reg62) \ + ((mh_debug_reg62 & MH_DEBUG_REG62_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG62_GET_TAG15_VA(mh_debug_reg62) \ + ((mh_debug_reg62 & MH_DEBUG_REG62_TAG15_VA_MASK) >> MH_DEBUG_REG62_TAG15_VA_SHIFT) +#define MH_DEBUG_REG62_GET_TAG_valid_q_15(mh_debug_reg62) \ + ((mh_debug_reg62 & MH_DEBUG_REG62_TAG_valid_q_15_MASK) >> MH_DEBUG_REG62_TAG_valid_q_15_SHIFT) + +#define MH_DEBUG_REG62_SET_TAG14_VA(mh_debug_reg62_reg, tag14_va) \ + mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG14_VA_MASK) | (tag14_va << MH_DEBUG_REG62_TAG14_VA_SHIFT) +#define MH_DEBUG_REG62_SET_TAG_valid_q_14(mh_debug_reg62_reg, tag_valid_q_14) \ + mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG_valid_q_14_MASK) | (tag_valid_q_14 << MH_DEBUG_REG62_TAG_valid_q_14_SHIFT) +#define MH_DEBUG_REG62_SET_ALWAYS_ZERO(mh_debug_reg62_reg, always_zero) \ + mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG62_SET_TAG15_VA(mh_debug_reg62_reg, tag15_va) \ + mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG15_VA_MASK) | (tag15_va << MH_DEBUG_REG62_TAG15_VA_SHIFT) +#define MH_DEBUG_REG62_SET_TAG_valid_q_15(mh_debug_reg62_reg, tag_valid_q_15) \ + mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG_valid_q_15_MASK) | (tag_valid_q_15 << MH_DEBUG_REG62_TAG_valid_q_15_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg62_t { + unsigned int tag14_va : MH_DEBUG_REG62_TAG14_VA_SIZE; + unsigned int tag_valid_q_14 : MH_DEBUG_REG62_TAG_valid_q_14_SIZE; + unsigned int always_zero : MH_DEBUG_REG62_ALWAYS_ZERO_SIZE; + unsigned int tag15_va : MH_DEBUG_REG62_TAG15_VA_SIZE; + unsigned int tag_valid_q_15 : MH_DEBUG_REG62_TAG_valid_q_15_SIZE; + unsigned int : 2; + } mh_debug_reg62_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg62_t { + unsigned int : 2; + unsigned int tag_valid_q_15 : MH_DEBUG_REG62_TAG_valid_q_15_SIZE; + unsigned int tag15_va : MH_DEBUG_REG62_TAG15_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG62_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_14 : MH_DEBUG_REG62_TAG_valid_q_14_SIZE; + unsigned int tag14_va : MH_DEBUG_REG62_TAG14_VA_SIZE; + } mh_debug_reg62_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg62_t f; +} mh_debug_reg62_u; + + +/* + * MH_DEBUG_REG63 struct + */ + +#define MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE 32 + +#define MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT 0 + +#define MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK 0xffffffff + +#define MH_DEBUG_REG63_MASK \ + (MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) + +#define MH_DEBUG_REG63(mh_dbg_default) \ + ((mh_dbg_default << MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT)) + +#define MH_DEBUG_REG63_GET_MH_DBG_DEFAULT(mh_debug_reg63) \ + ((mh_debug_reg63 & MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) >> MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT) + +#define MH_DEBUG_REG63_SET_MH_DBG_DEFAULT(mh_debug_reg63_reg, mh_dbg_default) \ + mh_debug_reg63_reg = (mh_debug_reg63_reg & ~MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) | (mh_dbg_default << MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg63_t { + unsigned int mh_dbg_default : MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE; + } mh_debug_reg63_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg63_t { + unsigned int mh_dbg_default : MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE; + } mh_debug_reg63_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg63_t f; +} mh_debug_reg63_u; + + +/* + * MH_MMU_CONFIG struct + */ + +#define MH_MMU_CONFIG_MMU_ENABLE_SIZE 1 +#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE 1 +#define MH_MMU_CONFIG_RESERVED1_SIZE 2 +#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SIZE 2 + +#define MH_MMU_CONFIG_MMU_ENABLE_SHIFT 0 +#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT 1 +#define MH_MMU_CONFIG_RESERVED1_SHIFT 2 +#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT 4 +#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT 6 +#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT 8 +#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT 10 +#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT 12 +#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT 14 +#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT 16 +#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT 18 +#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT 20 +#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT 22 +#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT 24 + +#define MH_MMU_CONFIG_MMU_ENABLE_MASK 0x00000001 +#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK 0x00000002 +#define MH_MMU_CONFIG_RESERVED1_MASK 0x0000000c +#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK 0x00000030 +#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK 0x000000c0 +#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK 0x00000300 +#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK 0x00000c00 +#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK 0x00003000 +#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK 0x0000c000 +#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK 0x00030000 +#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK 0x000c0000 +#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK 0x00300000 +#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK 0x00c00000 +#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK 0x03000000 + +#define MH_MMU_CONFIG_MASK \ + (MH_MMU_CONFIG_MMU_ENABLE_MASK | \ + MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK | \ + MH_MMU_CONFIG_RESERVED1_MASK | \ + MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK) + +#define MH_MMU_CONFIG(mmu_enable, split_mode_enable, reserved1, rb_w_clnt_behavior, cp_w_clnt_behavior, cp_r0_clnt_behavior, cp_r1_clnt_behavior, cp_r2_clnt_behavior, cp_r3_clnt_behavior, cp_r4_clnt_behavior, vgt_r0_clnt_behavior, vgt_r1_clnt_behavior, tc_r_clnt_behavior, pa_w_clnt_behavior) \ + ((mmu_enable << MH_MMU_CONFIG_MMU_ENABLE_SHIFT) | \ + (split_mode_enable << MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT) | \ + (reserved1 << MH_MMU_CONFIG_RESERVED1_SHIFT) | \ + (rb_w_clnt_behavior << MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT) | \ + (cp_w_clnt_behavior << MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r0_clnt_behavior << MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r1_clnt_behavior << MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r2_clnt_behavior << MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r3_clnt_behavior << MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r4_clnt_behavior << MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT) | \ + (vgt_r0_clnt_behavior << MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT) | \ + (vgt_r1_clnt_behavior << MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT) | \ + (tc_r_clnt_behavior << MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT) | \ + (pa_w_clnt_behavior << MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT)) + +#define MH_MMU_CONFIG_GET_MMU_ENABLE(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_MMU_ENABLE_MASK) >> MH_MMU_CONFIG_MMU_ENABLE_SHIFT) +#define MH_MMU_CONFIG_GET_SPLIT_MODE_ENABLE(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK) >> MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT) +#define MH_MMU_CONFIG_GET_RESERVED1(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_RESERVED1_MASK) >> MH_MMU_CONFIG_RESERVED1_SHIFT) +#define MH_MMU_CONFIG_GET_RB_W_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_W_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R0_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R1_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R2_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R3_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R4_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_VGT_R0_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_VGT_R1_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_TC_R_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_PA_W_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT) + +#define MH_MMU_CONFIG_SET_MMU_ENABLE(mh_mmu_config_reg, mmu_enable) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_MMU_ENABLE_MASK) | (mmu_enable << MH_MMU_CONFIG_MMU_ENABLE_SHIFT) +#define MH_MMU_CONFIG_SET_SPLIT_MODE_ENABLE(mh_mmu_config_reg, split_mode_enable) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK) | (split_mode_enable << MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT) +#define MH_MMU_CONFIG_SET_RESERVED1(mh_mmu_config_reg, reserved1) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_RESERVED1_MASK) | (reserved1 << MH_MMU_CONFIG_RESERVED1_SHIFT) +#define MH_MMU_CONFIG_SET_RB_W_CLNT_BEHAVIOR(mh_mmu_config_reg, rb_w_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK) | (rb_w_clnt_behavior << MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_W_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_w_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK) | (cp_w_clnt_behavior << MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R0_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r0_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK) | (cp_r0_clnt_behavior << MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R1_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r1_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK) | (cp_r1_clnt_behavior << MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R2_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r2_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK) | (cp_r2_clnt_behavior << MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R3_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r3_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK) | (cp_r3_clnt_behavior << MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R4_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r4_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK) | (cp_r4_clnt_behavior << MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_VGT_R0_CLNT_BEHAVIOR(mh_mmu_config_reg, vgt_r0_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK) | (vgt_r0_clnt_behavior << MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_VGT_R1_CLNT_BEHAVIOR(mh_mmu_config_reg, vgt_r1_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK) | (vgt_r1_clnt_behavior << MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_TC_R_CLNT_BEHAVIOR(mh_mmu_config_reg, tc_r_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK) | (tc_r_clnt_behavior << MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_PA_W_CLNT_BEHAVIOR(mh_mmu_config_reg, pa_w_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK) | (pa_w_clnt_behavior << MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_config_t { + unsigned int mmu_enable : MH_MMU_CONFIG_MMU_ENABLE_SIZE; + unsigned int split_mode_enable : MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE; + unsigned int reserved1 : MH_MMU_CONFIG_RESERVED1_SIZE; + unsigned int rb_w_clnt_behavior : MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE; + unsigned int cp_w_clnt_behavior : MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r0_clnt_behavior : MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r1_clnt_behavior : MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r2_clnt_behavior : MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r3_clnt_behavior : MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r4_clnt_behavior : MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE; + unsigned int vgt_r0_clnt_behavior : MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE; + unsigned int vgt_r1_clnt_behavior : MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE; + unsigned int tc_r_clnt_behavior : MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE; + unsigned int pa_w_clnt_behavior : MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SIZE; + unsigned int : 6; + } mh_mmu_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_config_t { + unsigned int : 6; + unsigned int pa_w_clnt_behavior : MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SIZE; + unsigned int tc_r_clnt_behavior : MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE; + unsigned int vgt_r1_clnt_behavior : MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE; + unsigned int vgt_r0_clnt_behavior : MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r4_clnt_behavior : MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r3_clnt_behavior : MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r2_clnt_behavior : MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r1_clnt_behavior : MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r0_clnt_behavior : MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE; + unsigned int cp_w_clnt_behavior : MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE; + unsigned int rb_w_clnt_behavior : MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE; + unsigned int reserved1 : MH_MMU_CONFIG_RESERVED1_SIZE; + unsigned int split_mode_enable : MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE; + unsigned int mmu_enable : MH_MMU_CONFIG_MMU_ENABLE_SIZE; + } mh_mmu_config_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_config_t f; +} mh_mmu_config_u; + + +/* + * MH_MMU_VA_RANGE struct + */ + +#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE 12 +#define MH_MMU_VA_RANGE_VA_BASE_SIZE 20 + +#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT 0 +#define MH_MMU_VA_RANGE_VA_BASE_SHIFT 12 + +#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK 0x00000fff +#define MH_MMU_VA_RANGE_VA_BASE_MASK 0xfffff000 + +#define MH_MMU_VA_RANGE_MASK \ + (MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK | \ + MH_MMU_VA_RANGE_VA_BASE_MASK) + +#define MH_MMU_VA_RANGE(num_64kb_regions, va_base) \ + ((num_64kb_regions << MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT) | \ + (va_base << MH_MMU_VA_RANGE_VA_BASE_SHIFT)) + +#define MH_MMU_VA_RANGE_GET_NUM_64KB_REGIONS(mh_mmu_va_range) \ + ((mh_mmu_va_range & MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK) >> MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT) +#define MH_MMU_VA_RANGE_GET_VA_BASE(mh_mmu_va_range) \ + ((mh_mmu_va_range & MH_MMU_VA_RANGE_VA_BASE_MASK) >> MH_MMU_VA_RANGE_VA_BASE_SHIFT) + +#define MH_MMU_VA_RANGE_SET_NUM_64KB_REGIONS(mh_mmu_va_range_reg, num_64kb_regions) \ + mh_mmu_va_range_reg = (mh_mmu_va_range_reg & ~MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK) | (num_64kb_regions << MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT) +#define MH_MMU_VA_RANGE_SET_VA_BASE(mh_mmu_va_range_reg, va_base) \ + mh_mmu_va_range_reg = (mh_mmu_va_range_reg & ~MH_MMU_VA_RANGE_VA_BASE_MASK) | (va_base << MH_MMU_VA_RANGE_VA_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_va_range_t { + unsigned int num_64kb_regions : MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE; + unsigned int va_base : MH_MMU_VA_RANGE_VA_BASE_SIZE; + } mh_mmu_va_range_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_va_range_t { + unsigned int va_base : MH_MMU_VA_RANGE_VA_BASE_SIZE; + unsigned int num_64kb_regions : MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE; + } mh_mmu_va_range_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_va_range_t f; +} mh_mmu_va_range_u; + + +/* + * MH_MMU_PT_BASE struct + */ + +#define MH_MMU_PT_BASE_PT_BASE_SIZE 20 + +#define MH_MMU_PT_BASE_PT_BASE_SHIFT 12 + +#define MH_MMU_PT_BASE_PT_BASE_MASK 0xfffff000 + +#define MH_MMU_PT_BASE_MASK \ + (MH_MMU_PT_BASE_PT_BASE_MASK) + +#define MH_MMU_PT_BASE(pt_base) \ + ((pt_base << MH_MMU_PT_BASE_PT_BASE_SHIFT)) + +#define MH_MMU_PT_BASE_GET_PT_BASE(mh_mmu_pt_base) \ + ((mh_mmu_pt_base & MH_MMU_PT_BASE_PT_BASE_MASK) >> MH_MMU_PT_BASE_PT_BASE_SHIFT) + +#define MH_MMU_PT_BASE_SET_PT_BASE(mh_mmu_pt_base_reg, pt_base) \ + mh_mmu_pt_base_reg = (mh_mmu_pt_base_reg & ~MH_MMU_PT_BASE_PT_BASE_MASK) | (pt_base << MH_MMU_PT_BASE_PT_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_pt_base_t { + unsigned int : 12; + unsigned int pt_base : MH_MMU_PT_BASE_PT_BASE_SIZE; + } mh_mmu_pt_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_pt_base_t { + unsigned int pt_base : MH_MMU_PT_BASE_PT_BASE_SIZE; + unsigned int : 12; + } mh_mmu_pt_base_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_pt_base_t f; +} mh_mmu_pt_base_u; + + +/* + * MH_MMU_PAGE_FAULT struct + */ + +#define MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE 1 +#define MH_MMU_PAGE_FAULT_OP_TYPE_SIZE 1 +#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_PAGE_FAULT_AXI_ID_SIZE 3 +#define MH_MMU_PAGE_FAULT_RESERVED1_SIZE 1 +#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE 1 +#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE 1 +#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE 1 +#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE 1 +#define MH_MMU_PAGE_FAULT_REQ_VA_SIZE 20 + +#define MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT 0 +#define MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT 1 +#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT 2 +#define MH_MMU_PAGE_FAULT_AXI_ID_SHIFT 4 +#define MH_MMU_PAGE_FAULT_RESERVED1_SHIFT 7 +#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT 8 +#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT 9 +#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT 10 +#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT 11 +#define MH_MMU_PAGE_FAULT_REQ_VA_SHIFT 12 + +#define MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK 0x00000001 +#define MH_MMU_PAGE_FAULT_OP_TYPE_MASK 0x00000002 +#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK 0x0000000c +#define MH_MMU_PAGE_FAULT_AXI_ID_MASK 0x00000070 +#define MH_MMU_PAGE_FAULT_RESERVED1_MASK 0x00000080 +#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK 0x00000100 +#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK 0x00000200 +#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK 0x00000400 +#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK 0x00000800 +#define MH_MMU_PAGE_FAULT_REQ_VA_MASK 0xfffff000 + +#define MH_MMU_PAGE_FAULT_MASK \ + (MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK | \ + MH_MMU_PAGE_FAULT_OP_TYPE_MASK | \ + MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK | \ + MH_MMU_PAGE_FAULT_AXI_ID_MASK | \ + MH_MMU_PAGE_FAULT_RESERVED1_MASK | \ + MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK | \ + MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK | \ + MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK | \ + MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK | \ + MH_MMU_PAGE_FAULT_REQ_VA_MASK) + +#define MH_MMU_PAGE_FAULT(page_fault, op_type, clnt_behavior, axi_id, reserved1, mpu_address_out_of_range, address_out_of_range, read_protection_error, write_protection_error, req_va) \ + ((page_fault << MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT) | \ + (op_type << MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT) | \ + (clnt_behavior << MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT) | \ + (axi_id << MH_MMU_PAGE_FAULT_AXI_ID_SHIFT) | \ + (reserved1 << MH_MMU_PAGE_FAULT_RESERVED1_SHIFT) | \ + (mpu_address_out_of_range << MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT) | \ + (address_out_of_range << MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT) | \ + (read_protection_error << MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT) | \ + (write_protection_error << MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT) | \ + (req_va << MH_MMU_PAGE_FAULT_REQ_VA_SHIFT)) + +#define MH_MMU_PAGE_FAULT_GET_PAGE_FAULT(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK) >> MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_OP_TYPE(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_OP_TYPE_MASK) >> MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_CLNT_BEHAVIOR(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK) >> MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_AXI_ID(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_AXI_ID_MASK) >> MH_MMU_PAGE_FAULT_AXI_ID_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_RESERVED1(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_RESERVED1_MASK) >> MH_MMU_PAGE_FAULT_RESERVED1_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_MPU_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK) >> MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK) >> MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_READ_PROTECTION_ERROR(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK) >> MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_WRITE_PROTECTION_ERROR(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK) >> MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_REQ_VA(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_REQ_VA_MASK) >> MH_MMU_PAGE_FAULT_REQ_VA_SHIFT) + +#define MH_MMU_PAGE_FAULT_SET_PAGE_FAULT(mh_mmu_page_fault_reg, page_fault) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK) | (page_fault << MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_OP_TYPE(mh_mmu_page_fault_reg, op_type) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_OP_TYPE_MASK) | (op_type << MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_CLNT_BEHAVIOR(mh_mmu_page_fault_reg, clnt_behavior) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK) | (clnt_behavior << MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_AXI_ID(mh_mmu_page_fault_reg, axi_id) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_AXI_ID_MASK) | (axi_id << MH_MMU_PAGE_FAULT_AXI_ID_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_RESERVED1(mh_mmu_page_fault_reg, reserved1) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_RESERVED1_MASK) | (reserved1 << MH_MMU_PAGE_FAULT_RESERVED1_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_MPU_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault_reg, mpu_address_out_of_range) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK) | (mpu_address_out_of_range << MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault_reg, address_out_of_range) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK) | (address_out_of_range << MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_READ_PROTECTION_ERROR(mh_mmu_page_fault_reg, read_protection_error) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK) | (read_protection_error << MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_WRITE_PROTECTION_ERROR(mh_mmu_page_fault_reg, write_protection_error) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK) | (write_protection_error << MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_REQ_VA(mh_mmu_page_fault_reg, req_va) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_REQ_VA_MASK) | (req_va << MH_MMU_PAGE_FAULT_REQ_VA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_page_fault_t { + unsigned int page_fault : MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE; + unsigned int op_type : MH_MMU_PAGE_FAULT_OP_TYPE_SIZE; + unsigned int clnt_behavior : MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE; + unsigned int axi_id : MH_MMU_PAGE_FAULT_AXI_ID_SIZE; + unsigned int reserved1 : MH_MMU_PAGE_FAULT_RESERVED1_SIZE; + unsigned int mpu_address_out_of_range : MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE; + unsigned int address_out_of_range : MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE; + unsigned int read_protection_error : MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE; + unsigned int write_protection_error : MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE; + unsigned int req_va : MH_MMU_PAGE_FAULT_REQ_VA_SIZE; + } mh_mmu_page_fault_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_page_fault_t { + unsigned int req_va : MH_MMU_PAGE_FAULT_REQ_VA_SIZE; + unsigned int write_protection_error : MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE; + unsigned int read_protection_error : MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE; + unsigned int address_out_of_range : MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE; + unsigned int mpu_address_out_of_range : MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE; + unsigned int reserved1 : MH_MMU_PAGE_FAULT_RESERVED1_SIZE; + unsigned int axi_id : MH_MMU_PAGE_FAULT_AXI_ID_SIZE; + unsigned int clnt_behavior : MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE; + unsigned int op_type : MH_MMU_PAGE_FAULT_OP_TYPE_SIZE; + unsigned int page_fault : MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE; + } mh_mmu_page_fault_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_page_fault_t f; +} mh_mmu_page_fault_u; + + +/* + * MH_MMU_TRAN_ERROR struct + */ + +#define MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE 27 + +#define MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT 5 + +#define MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK 0xffffffe0 + +#define MH_MMU_TRAN_ERROR_MASK \ + (MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) + +#define MH_MMU_TRAN_ERROR(tran_error) \ + ((tran_error << MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT)) + +#define MH_MMU_TRAN_ERROR_GET_TRAN_ERROR(mh_mmu_tran_error) \ + ((mh_mmu_tran_error & MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) >> MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT) + +#define MH_MMU_TRAN_ERROR_SET_TRAN_ERROR(mh_mmu_tran_error_reg, tran_error) \ + mh_mmu_tran_error_reg = (mh_mmu_tran_error_reg & ~MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) | (tran_error << MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_tran_error_t { + unsigned int : 5; + unsigned int tran_error : MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE; + } mh_mmu_tran_error_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_tran_error_t { + unsigned int tran_error : MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE; + unsigned int : 5; + } mh_mmu_tran_error_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_tran_error_t f; +} mh_mmu_tran_error_u; + + +/* + * MH_MMU_INVALIDATE struct + */ + +#define MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE 1 +#define MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE 1 + +#define MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT 0 +#define MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT 1 + +#define MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00000001 +#define MH_MMU_INVALIDATE_INVALIDATE_TC_MASK 0x00000002 + +#define MH_MMU_INVALIDATE_MASK \ + (MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK | \ + MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) + +#define MH_MMU_INVALIDATE(invalidate_all, invalidate_tc) \ + ((invalidate_all << MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) | \ + (invalidate_tc << MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT)) + +#define MH_MMU_INVALIDATE_GET_INVALIDATE_ALL(mh_mmu_invalidate) \ + ((mh_mmu_invalidate & MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) >> MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) +#define MH_MMU_INVALIDATE_GET_INVALIDATE_TC(mh_mmu_invalidate) \ + ((mh_mmu_invalidate & MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) >> MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT) + +#define MH_MMU_INVALIDATE_SET_INVALIDATE_ALL(mh_mmu_invalidate_reg, invalidate_all) \ + mh_mmu_invalidate_reg = (mh_mmu_invalidate_reg & ~MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) | (invalidate_all << MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) +#define MH_MMU_INVALIDATE_SET_INVALIDATE_TC(mh_mmu_invalidate_reg, invalidate_tc) \ + mh_mmu_invalidate_reg = (mh_mmu_invalidate_reg & ~MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) | (invalidate_tc << MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_invalidate_t { + unsigned int invalidate_all : MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE; + unsigned int invalidate_tc : MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE; + unsigned int : 30; + } mh_mmu_invalidate_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_invalidate_t { + unsigned int : 30; + unsigned int invalidate_tc : MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE; + unsigned int invalidate_all : MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE; + } mh_mmu_invalidate_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_invalidate_t f; +} mh_mmu_invalidate_u; + + +/* + * MH_MMU_MPU_BASE struct + */ + +#define MH_MMU_MPU_BASE_MPU_BASE_SIZE 20 + +#define MH_MMU_MPU_BASE_MPU_BASE_SHIFT 12 + +#define MH_MMU_MPU_BASE_MPU_BASE_MASK 0xfffff000 + +#define MH_MMU_MPU_BASE_MASK \ + (MH_MMU_MPU_BASE_MPU_BASE_MASK) + +#define MH_MMU_MPU_BASE(mpu_base) \ + ((mpu_base << MH_MMU_MPU_BASE_MPU_BASE_SHIFT)) + +#define MH_MMU_MPU_BASE_GET_MPU_BASE(mh_mmu_mpu_base) \ + ((mh_mmu_mpu_base & MH_MMU_MPU_BASE_MPU_BASE_MASK) >> MH_MMU_MPU_BASE_MPU_BASE_SHIFT) + +#define MH_MMU_MPU_BASE_SET_MPU_BASE(mh_mmu_mpu_base_reg, mpu_base) \ + mh_mmu_mpu_base_reg = (mh_mmu_mpu_base_reg & ~MH_MMU_MPU_BASE_MPU_BASE_MASK) | (mpu_base << MH_MMU_MPU_BASE_MPU_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_mpu_base_t { + unsigned int : 12; + unsigned int mpu_base : MH_MMU_MPU_BASE_MPU_BASE_SIZE; + } mh_mmu_mpu_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_mpu_base_t { + unsigned int mpu_base : MH_MMU_MPU_BASE_MPU_BASE_SIZE; + unsigned int : 12; + } mh_mmu_mpu_base_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_mpu_base_t f; +} mh_mmu_mpu_base_u; + + +/* + * MH_MMU_MPU_END struct + */ + +#define MH_MMU_MPU_END_MPU_END_SIZE 20 + +#define MH_MMU_MPU_END_MPU_END_SHIFT 12 + +#define MH_MMU_MPU_END_MPU_END_MASK 0xfffff000 + +#define MH_MMU_MPU_END_MASK \ + (MH_MMU_MPU_END_MPU_END_MASK) + +#define MH_MMU_MPU_END(mpu_end) \ + ((mpu_end << MH_MMU_MPU_END_MPU_END_SHIFT)) + +#define MH_MMU_MPU_END_GET_MPU_END(mh_mmu_mpu_end) \ + ((mh_mmu_mpu_end & MH_MMU_MPU_END_MPU_END_MASK) >> MH_MMU_MPU_END_MPU_END_SHIFT) + +#define MH_MMU_MPU_END_SET_MPU_END(mh_mmu_mpu_end_reg, mpu_end) \ + mh_mmu_mpu_end_reg = (mh_mmu_mpu_end_reg & ~MH_MMU_MPU_END_MPU_END_MASK) | (mpu_end << MH_MMU_MPU_END_MPU_END_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_mpu_end_t { + unsigned int : 12; + unsigned int mpu_end : MH_MMU_MPU_END_MPU_END_SIZE; + } mh_mmu_mpu_end_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_mpu_end_t { + unsigned int mpu_end : MH_MMU_MPU_END_MPU_END_SIZE; + unsigned int : 12; + } mh_mmu_mpu_end_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_mpu_end_t f; +} mh_mmu_mpu_end_u; + + +#endif + + +#if !defined (_PA_FIDDLE_H) +#define _PA_FIDDLE_H + +/***************************************************************************************************************** + * + * pa_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * PA_CL_VPORT_XSCALE struct + */ + +#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE 32 + +#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT 0 + +#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK 0xffffffff + +#define PA_CL_VPORT_XSCALE_MASK \ + (PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) + +#define PA_CL_VPORT_XSCALE(vport_xscale) \ + ((vport_xscale << PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT)) + +#define PA_CL_VPORT_XSCALE_GET_VPORT_XSCALE(pa_cl_vport_xscale) \ + ((pa_cl_vport_xscale & PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) >> PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT) + +#define PA_CL_VPORT_XSCALE_SET_VPORT_XSCALE(pa_cl_vport_xscale_reg, vport_xscale) \ + pa_cl_vport_xscale_reg = (pa_cl_vport_xscale_reg & ~PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) | (vport_xscale << PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_xscale_t { + unsigned int vport_xscale : PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE; + } pa_cl_vport_xscale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_xscale_t { + unsigned int vport_xscale : PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE; + } pa_cl_vport_xscale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_xscale_t f; +} pa_cl_vport_xscale_u; + + +/* + * PA_CL_VPORT_XOFFSET struct + */ + +#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE 32 + +#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT 0 + +#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK 0xffffffff + +#define PA_CL_VPORT_XOFFSET_MASK \ + (PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) + +#define PA_CL_VPORT_XOFFSET(vport_xoffset) \ + ((vport_xoffset << PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT)) + +#define PA_CL_VPORT_XOFFSET_GET_VPORT_XOFFSET(pa_cl_vport_xoffset) \ + ((pa_cl_vport_xoffset & PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) >> PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT) + +#define PA_CL_VPORT_XOFFSET_SET_VPORT_XOFFSET(pa_cl_vport_xoffset_reg, vport_xoffset) \ + pa_cl_vport_xoffset_reg = (pa_cl_vport_xoffset_reg & ~PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) | (vport_xoffset << PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_xoffset_t { + unsigned int vport_xoffset : PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE; + } pa_cl_vport_xoffset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_xoffset_t { + unsigned int vport_xoffset : PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE; + } pa_cl_vport_xoffset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_xoffset_t f; +} pa_cl_vport_xoffset_u; + + +/* + * PA_CL_VPORT_YSCALE struct + */ + +#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE 32 + +#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT 0 + +#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK 0xffffffff + +#define PA_CL_VPORT_YSCALE_MASK \ + (PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) + +#define PA_CL_VPORT_YSCALE(vport_yscale) \ + ((vport_yscale << PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT)) + +#define PA_CL_VPORT_YSCALE_GET_VPORT_YSCALE(pa_cl_vport_yscale) \ + ((pa_cl_vport_yscale & PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) >> PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT) + +#define PA_CL_VPORT_YSCALE_SET_VPORT_YSCALE(pa_cl_vport_yscale_reg, vport_yscale) \ + pa_cl_vport_yscale_reg = (pa_cl_vport_yscale_reg & ~PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) | (vport_yscale << PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_yscale_t { + unsigned int vport_yscale : PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE; + } pa_cl_vport_yscale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_yscale_t { + unsigned int vport_yscale : PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE; + } pa_cl_vport_yscale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_yscale_t f; +} pa_cl_vport_yscale_u; + + +/* + * PA_CL_VPORT_YOFFSET struct + */ + +#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE 32 + +#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT 0 + +#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK 0xffffffff + +#define PA_CL_VPORT_YOFFSET_MASK \ + (PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) + +#define PA_CL_VPORT_YOFFSET(vport_yoffset) \ + ((vport_yoffset << PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT)) + +#define PA_CL_VPORT_YOFFSET_GET_VPORT_YOFFSET(pa_cl_vport_yoffset) \ + ((pa_cl_vport_yoffset & PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) >> PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT) + +#define PA_CL_VPORT_YOFFSET_SET_VPORT_YOFFSET(pa_cl_vport_yoffset_reg, vport_yoffset) \ + pa_cl_vport_yoffset_reg = (pa_cl_vport_yoffset_reg & ~PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) | (vport_yoffset << PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_yoffset_t { + unsigned int vport_yoffset : PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE; + } pa_cl_vport_yoffset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_yoffset_t { + unsigned int vport_yoffset : PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE; + } pa_cl_vport_yoffset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_yoffset_t f; +} pa_cl_vport_yoffset_u; + + +/* + * PA_CL_VPORT_ZSCALE struct + */ + +#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE 32 + +#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT 0 + +#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK 0xffffffff + +#define PA_CL_VPORT_ZSCALE_MASK \ + (PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) + +#define PA_CL_VPORT_ZSCALE(vport_zscale) \ + ((vport_zscale << PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT)) + +#define PA_CL_VPORT_ZSCALE_GET_VPORT_ZSCALE(pa_cl_vport_zscale) \ + ((pa_cl_vport_zscale & PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) >> PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT) + +#define PA_CL_VPORT_ZSCALE_SET_VPORT_ZSCALE(pa_cl_vport_zscale_reg, vport_zscale) \ + pa_cl_vport_zscale_reg = (pa_cl_vport_zscale_reg & ~PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) | (vport_zscale << PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_zscale_t { + unsigned int vport_zscale : PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE; + } pa_cl_vport_zscale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_zscale_t { + unsigned int vport_zscale : PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE; + } pa_cl_vport_zscale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_zscale_t f; +} pa_cl_vport_zscale_u; + + +/* + * PA_CL_VPORT_ZOFFSET struct + */ + +#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE 32 + +#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT 0 + +#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK 0xffffffff + +#define PA_CL_VPORT_ZOFFSET_MASK \ + (PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) + +#define PA_CL_VPORT_ZOFFSET(vport_zoffset) \ + ((vport_zoffset << PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT)) + +#define PA_CL_VPORT_ZOFFSET_GET_VPORT_ZOFFSET(pa_cl_vport_zoffset) \ + ((pa_cl_vport_zoffset & PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) >> PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT) + +#define PA_CL_VPORT_ZOFFSET_SET_VPORT_ZOFFSET(pa_cl_vport_zoffset_reg, vport_zoffset) \ + pa_cl_vport_zoffset_reg = (pa_cl_vport_zoffset_reg & ~PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) | (vport_zoffset << PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_zoffset_t { + unsigned int vport_zoffset : PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE; + } pa_cl_vport_zoffset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_zoffset_t { + unsigned int vport_zoffset : PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE; + } pa_cl_vport_zoffset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_zoffset_t f; +} pa_cl_vport_zoffset_u; + + +/* + * PA_CL_VTE_CNTL struct + */ + +#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE 1 +#define PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE 1 +#define PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE 1 +#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE 1 + +#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT 0 +#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT 1 +#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT 2 +#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT 3 +#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT 4 +#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT 5 +#define PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT 8 +#define PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT 9 +#define PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT 10 +#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT 11 + +#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK 0x00000001 +#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK 0x00000002 +#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK 0x00000004 +#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK 0x00000008 +#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK 0x00000010 +#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK 0x00000020 +#define PA_CL_VTE_CNTL_VTX_XY_FMT_MASK 0x00000100 +#define PA_CL_VTE_CNTL_VTX_Z_FMT_MASK 0x00000200 +#define PA_CL_VTE_CNTL_VTX_W0_FMT_MASK 0x00000400 +#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK 0x00000800 + +#define PA_CL_VTE_CNTL_MASK \ + (PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK | \ + PA_CL_VTE_CNTL_VTX_XY_FMT_MASK | \ + PA_CL_VTE_CNTL_VTX_Z_FMT_MASK | \ + PA_CL_VTE_CNTL_VTX_W0_FMT_MASK | \ + PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) + +#define PA_CL_VTE_CNTL(vport_x_scale_ena, vport_x_offset_ena, vport_y_scale_ena, vport_y_offset_ena, vport_z_scale_ena, vport_z_offset_ena, vtx_xy_fmt, vtx_z_fmt, vtx_w0_fmt, perfcounter_ref) \ + ((vport_x_scale_ena << PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT) | \ + (vport_x_offset_ena << PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT) | \ + (vport_y_scale_ena << PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT) | \ + (vport_y_offset_ena << PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT) | \ + (vport_z_scale_ena << PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT) | \ + (vport_z_offset_ena << PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT) | \ + (vtx_xy_fmt << PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT) | \ + (vtx_z_fmt << PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT) | \ + (vtx_w0_fmt << PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT) | \ + (perfcounter_ref << PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT)) + +#define PA_CL_VTE_CNTL_GET_VPORT_X_SCALE_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_X_OFFSET_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_Y_SCALE_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_Y_OFFSET_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_Z_SCALE_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_Z_OFFSET_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VTX_XY_FMT(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_XY_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT) +#define PA_CL_VTE_CNTL_GET_VTX_Z_FMT(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_Z_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT) +#define PA_CL_VTE_CNTL_GET_VTX_W0_FMT(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_W0_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT) +#define PA_CL_VTE_CNTL_GET_PERFCOUNTER_REF(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) >> PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT) + +#define PA_CL_VTE_CNTL_SET_VPORT_X_SCALE_ENA(pa_cl_vte_cntl_reg, vport_x_scale_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK) | (vport_x_scale_ena << PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_X_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_x_offset_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK) | (vport_x_offset_ena << PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_Y_SCALE_ENA(pa_cl_vte_cntl_reg, vport_y_scale_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK) | (vport_y_scale_ena << PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_Y_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_y_offset_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK) | (vport_y_offset_ena << PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_Z_SCALE_ENA(pa_cl_vte_cntl_reg, vport_z_scale_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK) | (vport_z_scale_ena << PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_Z_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_z_offset_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK) | (vport_z_offset_ena << PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VTX_XY_FMT(pa_cl_vte_cntl_reg, vtx_xy_fmt) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_XY_FMT_MASK) | (vtx_xy_fmt << PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT) +#define PA_CL_VTE_CNTL_SET_VTX_Z_FMT(pa_cl_vte_cntl_reg, vtx_z_fmt) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_Z_FMT_MASK) | (vtx_z_fmt << PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT) +#define PA_CL_VTE_CNTL_SET_VTX_W0_FMT(pa_cl_vte_cntl_reg, vtx_w0_fmt) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_W0_FMT_MASK) | (vtx_w0_fmt << PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT) +#define PA_CL_VTE_CNTL_SET_PERFCOUNTER_REF(pa_cl_vte_cntl_reg, perfcounter_ref) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) | (perfcounter_ref << PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vte_cntl_t { + unsigned int vport_x_scale_ena : PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE; + unsigned int vport_x_offset_ena : PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE; + unsigned int vport_y_scale_ena : PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE; + unsigned int vport_y_offset_ena : PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE; + unsigned int vport_z_scale_ena : PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE; + unsigned int vport_z_offset_ena : PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE; + unsigned int : 2; + unsigned int vtx_xy_fmt : PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE; + unsigned int vtx_z_fmt : PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE; + unsigned int vtx_w0_fmt : PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE; + unsigned int perfcounter_ref : PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE; + unsigned int : 20; + } pa_cl_vte_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vte_cntl_t { + unsigned int : 20; + unsigned int perfcounter_ref : PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE; + unsigned int vtx_w0_fmt : PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE; + unsigned int vtx_z_fmt : PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE; + unsigned int vtx_xy_fmt : PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE; + unsigned int : 2; + unsigned int vport_z_offset_ena : PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE; + unsigned int vport_z_scale_ena : PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE; + unsigned int vport_y_offset_ena : PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE; + unsigned int vport_y_scale_ena : PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE; + unsigned int vport_x_offset_ena : PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE; + unsigned int vport_x_scale_ena : PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE; + } pa_cl_vte_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vte_cntl_t f; +} pa_cl_vte_cntl_u; + + +/* + * PA_CL_CLIP_CNTL struct + */ + +#define PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE 1 +#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE 1 +#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE 1 +#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE 1 +#define PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE 1 +#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE 1 +#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE 1 +#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE 1 + +#define PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT 16 +#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT 18 +#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT 19 +#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT 20 +#define PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT 21 +#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT 22 +#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT 23 +#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT 24 + +#define PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK 0x00010000 +#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000 +#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK 0x00080000 +#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK 0x00100000 +#define PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK 0x00200000 +#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK 0x00400000 +#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK 0x00800000 +#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK 0x01000000 + +#define PA_CL_CLIP_CNTL_MASK \ + (PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK | \ + PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK | \ + PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK | \ + PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK | \ + PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK | \ + PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK | \ + PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK | \ + PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) + +#define PA_CL_CLIP_CNTL(clip_disable, boundary_edge_flag_ena, dx_clip_space_def, dis_clip_err_detect, vtx_kill_or, xy_nan_retain, z_nan_retain, w_nan_retain) \ + ((clip_disable << PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT) | \ + (boundary_edge_flag_ena << PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT) | \ + (dx_clip_space_def << PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT) | \ + (dis_clip_err_detect << PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT) | \ + (vtx_kill_or << PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT) | \ + (xy_nan_retain << PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT) | \ + (z_nan_retain << PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT) | \ + (w_nan_retain << PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT)) + +#define PA_CL_CLIP_CNTL_GET_CLIP_DISABLE(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK) >> PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT) +#define PA_CL_CLIP_CNTL_GET_BOUNDARY_EDGE_FLAG_ENA(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK) >> PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT) +#define PA_CL_CLIP_CNTL_GET_DX_CLIP_SPACE_DEF(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK) >> PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT) +#define PA_CL_CLIP_CNTL_GET_DIS_CLIP_ERR_DETECT(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK) >> PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT) +#define PA_CL_CLIP_CNTL_GET_VTX_KILL_OR(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK) >> PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT) +#define PA_CL_CLIP_CNTL_GET_XY_NAN_RETAIN(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT) +#define PA_CL_CLIP_CNTL_GET_Z_NAN_RETAIN(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT) +#define PA_CL_CLIP_CNTL_GET_W_NAN_RETAIN(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT) + +#define PA_CL_CLIP_CNTL_SET_CLIP_DISABLE(pa_cl_clip_cntl_reg, clip_disable) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK) | (clip_disable << PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT) +#define PA_CL_CLIP_CNTL_SET_BOUNDARY_EDGE_FLAG_ENA(pa_cl_clip_cntl_reg, boundary_edge_flag_ena) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK) | (boundary_edge_flag_ena << PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT) +#define PA_CL_CLIP_CNTL_SET_DX_CLIP_SPACE_DEF(pa_cl_clip_cntl_reg, dx_clip_space_def) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK) | (dx_clip_space_def << PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT) +#define PA_CL_CLIP_CNTL_SET_DIS_CLIP_ERR_DETECT(pa_cl_clip_cntl_reg, dis_clip_err_detect) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK) | (dis_clip_err_detect << PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT) +#define PA_CL_CLIP_CNTL_SET_VTX_KILL_OR(pa_cl_clip_cntl_reg, vtx_kill_or) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK) | (vtx_kill_or << PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT) +#define PA_CL_CLIP_CNTL_SET_XY_NAN_RETAIN(pa_cl_clip_cntl_reg, xy_nan_retain) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK) | (xy_nan_retain << PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT) +#define PA_CL_CLIP_CNTL_SET_Z_NAN_RETAIN(pa_cl_clip_cntl_reg, z_nan_retain) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK) | (z_nan_retain << PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT) +#define PA_CL_CLIP_CNTL_SET_W_NAN_RETAIN(pa_cl_clip_cntl_reg, w_nan_retain) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) | (w_nan_retain << PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_clip_cntl_t { + unsigned int : 16; + unsigned int clip_disable : PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE; + unsigned int : 1; + unsigned int boundary_edge_flag_ena : PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE; + unsigned int dx_clip_space_def : PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE; + unsigned int dis_clip_err_detect : PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE; + unsigned int vtx_kill_or : PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE; + unsigned int xy_nan_retain : PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE; + unsigned int z_nan_retain : PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE; + unsigned int w_nan_retain : PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE; + unsigned int : 7; + } pa_cl_clip_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_clip_cntl_t { + unsigned int : 7; + unsigned int w_nan_retain : PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE; + unsigned int z_nan_retain : PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE; + unsigned int xy_nan_retain : PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE; + unsigned int vtx_kill_or : PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE; + unsigned int dis_clip_err_detect : PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE; + unsigned int dx_clip_space_def : PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE; + unsigned int boundary_edge_flag_ena : PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE; + unsigned int : 1; + unsigned int clip_disable : PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE; + unsigned int : 16; + } pa_cl_clip_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_clip_cntl_t f; +} pa_cl_clip_cntl_u; + + +/* + * PA_CL_GB_VERT_CLIP_ADJ struct + */ + +#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE 32 + +#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT 0 + +#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK 0xffffffff + +#define PA_CL_GB_VERT_CLIP_ADJ_MASK \ + (PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) + +#define PA_CL_GB_VERT_CLIP_ADJ(data_register) \ + ((data_register << PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT)) + +#define PA_CL_GB_VERT_CLIP_ADJ_GET_DATA_REGISTER(pa_cl_gb_vert_clip_adj) \ + ((pa_cl_gb_vert_clip_adj & PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT) + +#define PA_CL_GB_VERT_CLIP_ADJ_SET_DATA_REGISTER(pa_cl_gb_vert_clip_adj_reg, data_register) \ + pa_cl_gb_vert_clip_adj_reg = (pa_cl_gb_vert_clip_adj_reg & ~PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_gb_vert_clip_adj_t { + unsigned int data_register : PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_vert_clip_adj_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_gb_vert_clip_adj_t { + unsigned int data_register : PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_vert_clip_adj_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_gb_vert_clip_adj_t f; +} pa_cl_gb_vert_clip_adj_u; + + +/* + * PA_CL_GB_VERT_DISC_ADJ struct + */ + +#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE 32 + +#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT 0 + +#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK 0xffffffff + +#define PA_CL_GB_VERT_DISC_ADJ_MASK \ + (PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) + +#define PA_CL_GB_VERT_DISC_ADJ(data_register) \ + ((data_register << PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT)) + +#define PA_CL_GB_VERT_DISC_ADJ_GET_DATA_REGISTER(pa_cl_gb_vert_disc_adj) \ + ((pa_cl_gb_vert_disc_adj & PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT) + +#define PA_CL_GB_VERT_DISC_ADJ_SET_DATA_REGISTER(pa_cl_gb_vert_disc_adj_reg, data_register) \ + pa_cl_gb_vert_disc_adj_reg = (pa_cl_gb_vert_disc_adj_reg & ~PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_gb_vert_disc_adj_t { + unsigned int data_register : PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_vert_disc_adj_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_gb_vert_disc_adj_t { + unsigned int data_register : PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_vert_disc_adj_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_gb_vert_disc_adj_t f; +} pa_cl_gb_vert_disc_adj_u; + + +/* + * PA_CL_GB_HORZ_CLIP_ADJ struct + */ + +#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE 32 + +#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT 0 + +#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK 0xffffffff + +#define PA_CL_GB_HORZ_CLIP_ADJ_MASK \ + (PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) + +#define PA_CL_GB_HORZ_CLIP_ADJ(data_register) \ + ((data_register << PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT)) + +#define PA_CL_GB_HORZ_CLIP_ADJ_GET_DATA_REGISTER(pa_cl_gb_horz_clip_adj) \ + ((pa_cl_gb_horz_clip_adj & PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT) + +#define PA_CL_GB_HORZ_CLIP_ADJ_SET_DATA_REGISTER(pa_cl_gb_horz_clip_adj_reg, data_register) \ + pa_cl_gb_horz_clip_adj_reg = (pa_cl_gb_horz_clip_adj_reg & ~PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_gb_horz_clip_adj_t { + unsigned int data_register : PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_horz_clip_adj_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_gb_horz_clip_adj_t { + unsigned int data_register : PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_horz_clip_adj_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_gb_horz_clip_adj_t f; +} pa_cl_gb_horz_clip_adj_u; + + +/* + * PA_CL_GB_HORZ_DISC_ADJ struct + */ + +#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE 32 + +#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT 0 + +#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK 0xffffffff + +#define PA_CL_GB_HORZ_DISC_ADJ_MASK \ + (PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) + +#define PA_CL_GB_HORZ_DISC_ADJ(data_register) \ + ((data_register << PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT)) + +#define PA_CL_GB_HORZ_DISC_ADJ_GET_DATA_REGISTER(pa_cl_gb_horz_disc_adj) \ + ((pa_cl_gb_horz_disc_adj & PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT) + +#define PA_CL_GB_HORZ_DISC_ADJ_SET_DATA_REGISTER(pa_cl_gb_horz_disc_adj_reg, data_register) \ + pa_cl_gb_horz_disc_adj_reg = (pa_cl_gb_horz_disc_adj_reg & ~PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_gb_horz_disc_adj_t { + unsigned int data_register : PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_horz_disc_adj_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_gb_horz_disc_adj_t { + unsigned int data_register : PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_horz_disc_adj_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_gb_horz_disc_adj_t f; +} pa_cl_gb_horz_disc_adj_u; + + +/* + * PA_CL_ENHANCE struct + */ + +#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE 1 +#define PA_CL_ENHANCE_ECO_SPARE3_SIZE 1 +#define PA_CL_ENHANCE_ECO_SPARE2_SIZE 1 +#define PA_CL_ENHANCE_ECO_SPARE1_SIZE 1 +#define PA_CL_ENHANCE_ECO_SPARE0_SIZE 1 + +#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT 0 +#define PA_CL_ENHANCE_ECO_SPARE3_SHIFT 28 +#define PA_CL_ENHANCE_ECO_SPARE2_SHIFT 29 +#define PA_CL_ENHANCE_ECO_SPARE1_SHIFT 30 +#define PA_CL_ENHANCE_ECO_SPARE0_SHIFT 31 + +#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK 0x00000001 +#define PA_CL_ENHANCE_ECO_SPARE3_MASK 0x10000000 +#define PA_CL_ENHANCE_ECO_SPARE2_MASK 0x20000000 +#define PA_CL_ENHANCE_ECO_SPARE1_MASK 0x40000000 +#define PA_CL_ENHANCE_ECO_SPARE0_MASK 0x80000000 + +#define PA_CL_ENHANCE_MASK \ + (PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK | \ + PA_CL_ENHANCE_ECO_SPARE3_MASK | \ + PA_CL_ENHANCE_ECO_SPARE2_MASK | \ + PA_CL_ENHANCE_ECO_SPARE1_MASK | \ + PA_CL_ENHANCE_ECO_SPARE0_MASK) + +#define PA_CL_ENHANCE(clip_vtx_reorder_ena, eco_spare3, eco_spare2, eco_spare1, eco_spare0) \ + ((clip_vtx_reorder_ena << PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT) | \ + (eco_spare3 << PA_CL_ENHANCE_ECO_SPARE3_SHIFT) | \ + (eco_spare2 << PA_CL_ENHANCE_ECO_SPARE2_SHIFT) | \ + (eco_spare1 << PA_CL_ENHANCE_ECO_SPARE1_SHIFT) | \ + (eco_spare0 << PA_CL_ENHANCE_ECO_SPARE0_SHIFT)) + +#define PA_CL_ENHANCE_GET_CLIP_VTX_REORDER_ENA(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK) >> PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT) +#define PA_CL_ENHANCE_GET_ECO_SPARE3(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE3_MASK) >> PA_CL_ENHANCE_ECO_SPARE3_SHIFT) +#define PA_CL_ENHANCE_GET_ECO_SPARE2(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE2_MASK) >> PA_CL_ENHANCE_ECO_SPARE2_SHIFT) +#define PA_CL_ENHANCE_GET_ECO_SPARE1(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE1_MASK) >> PA_CL_ENHANCE_ECO_SPARE1_SHIFT) +#define PA_CL_ENHANCE_GET_ECO_SPARE0(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE0_MASK) >> PA_CL_ENHANCE_ECO_SPARE0_SHIFT) + +#define PA_CL_ENHANCE_SET_CLIP_VTX_REORDER_ENA(pa_cl_enhance_reg, clip_vtx_reorder_ena) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK) | (clip_vtx_reorder_ena << PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT) +#define PA_CL_ENHANCE_SET_ECO_SPARE3(pa_cl_enhance_reg, eco_spare3) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE3_MASK) | (eco_spare3 << PA_CL_ENHANCE_ECO_SPARE3_SHIFT) +#define PA_CL_ENHANCE_SET_ECO_SPARE2(pa_cl_enhance_reg, eco_spare2) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE2_MASK) | (eco_spare2 << PA_CL_ENHANCE_ECO_SPARE2_SHIFT) +#define PA_CL_ENHANCE_SET_ECO_SPARE1(pa_cl_enhance_reg, eco_spare1) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE1_MASK) | (eco_spare1 << PA_CL_ENHANCE_ECO_SPARE1_SHIFT) +#define PA_CL_ENHANCE_SET_ECO_SPARE0(pa_cl_enhance_reg, eco_spare0) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE0_MASK) | (eco_spare0 << PA_CL_ENHANCE_ECO_SPARE0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_enhance_t { + unsigned int clip_vtx_reorder_ena : PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE; + unsigned int : 27; + unsigned int eco_spare3 : PA_CL_ENHANCE_ECO_SPARE3_SIZE; + unsigned int eco_spare2 : PA_CL_ENHANCE_ECO_SPARE2_SIZE; + unsigned int eco_spare1 : PA_CL_ENHANCE_ECO_SPARE1_SIZE; + unsigned int eco_spare0 : PA_CL_ENHANCE_ECO_SPARE0_SIZE; + } pa_cl_enhance_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_enhance_t { + unsigned int eco_spare0 : PA_CL_ENHANCE_ECO_SPARE0_SIZE; + unsigned int eco_spare1 : PA_CL_ENHANCE_ECO_SPARE1_SIZE; + unsigned int eco_spare2 : PA_CL_ENHANCE_ECO_SPARE2_SIZE; + unsigned int eco_spare3 : PA_CL_ENHANCE_ECO_SPARE3_SIZE; + unsigned int : 27; + unsigned int clip_vtx_reorder_ena : PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE; + } pa_cl_enhance_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_enhance_t f; +} pa_cl_enhance_u; + + +/* + * PA_SC_ENHANCE struct + */ + +#define PA_SC_ENHANCE_ECO_SPARE3_SIZE 1 +#define PA_SC_ENHANCE_ECO_SPARE2_SIZE 1 +#define PA_SC_ENHANCE_ECO_SPARE1_SIZE 1 +#define PA_SC_ENHANCE_ECO_SPARE0_SIZE 1 + +#define PA_SC_ENHANCE_ECO_SPARE3_SHIFT 28 +#define PA_SC_ENHANCE_ECO_SPARE2_SHIFT 29 +#define PA_SC_ENHANCE_ECO_SPARE1_SHIFT 30 +#define PA_SC_ENHANCE_ECO_SPARE0_SHIFT 31 + +#define PA_SC_ENHANCE_ECO_SPARE3_MASK 0x10000000 +#define PA_SC_ENHANCE_ECO_SPARE2_MASK 0x20000000 +#define PA_SC_ENHANCE_ECO_SPARE1_MASK 0x40000000 +#define PA_SC_ENHANCE_ECO_SPARE0_MASK 0x80000000 + +#define PA_SC_ENHANCE_MASK \ + (PA_SC_ENHANCE_ECO_SPARE3_MASK | \ + PA_SC_ENHANCE_ECO_SPARE2_MASK | \ + PA_SC_ENHANCE_ECO_SPARE1_MASK | \ + PA_SC_ENHANCE_ECO_SPARE0_MASK) + +#define PA_SC_ENHANCE(eco_spare3, eco_spare2, eco_spare1, eco_spare0) \ + ((eco_spare3 << PA_SC_ENHANCE_ECO_SPARE3_SHIFT) | \ + (eco_spare2 << PA_SC_ENHANCE_ECO_SPARE2_SHIFT) | \ + (eco_spare1 << PA_SC_ENHANCE_ECO_SPARE1_SHIFT) | \ + (eco_spare0 << PA_SC_ENHANCE_ECO_SPARE0_SHIFT)) + +#define PA_SC_ENHANCE_GET_ECO_SPARE3(pa_sc_enhance) \ + ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE3_MASK) >> PA_SC_ENHANCE_ECO_SPARE3_SHIFT) +#define PA_SC_ENHANCE_GET_ECO_SPARE2(pa_sc_enhance) \ + ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE2_MASK) >> PA_SC_ENHANCE_ECO_SPARE2_SHIFT) +#define PA_SC_ENHANCE_GET_ECO_SPARE1(pa_sc_enhance) \ + ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE1_MASK) >> PA_SC_ENHANCE_ECO_SPARE1_SHIFT) +#define PA_SC_ENHANCE_GET_ECO_SPARE0(pa_sc_enhance) \ + ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE0_MASK) >> PA_SC_ENHANCE_ECO_SPARE0_SHIFT) + +#define PA_SC_ENHANCE_SET_ECO_SPARE3(pa_sc_enhance_reg, eco_spare3) \ + pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE3_MASK) | (eco_spare3 << PA_SC_ENHANCE_ECO_SPARE3_SHIFT) +#define PA_SC_ENHANCE_SET_ECO_SPARE2(pa_sc_enhance_reg, eco_spare2) \ + pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE2_MASK) | (eco_spare2 << PA_SC_ENHANCE_ECO_SPARE2_SHIFT) +#define PA_SC_ENHANCE_SET_ECO_SPARE1(pa_sc_enhance_reg, eco_spare1) \ + pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE1_MASK) | (eco_spare1 << PA_SC_ENHANCE_ECO_SPARE1_SHIFT) +#define PA_SC_ENHANCE_SET_ECO_SPARE0(pa_sc_enhance_reg, eco_spare0) \ + pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE0_MASK) | (eco_spare0 << PA_SC_ENHANCE_ECO_SPARE0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_enhance_t { + unsigned int : 28; + unsigned int eco_spare3 : PA_SC_ENHANCE_ECO_SPARE3_SIZE; + unsigned int eco_spare2 : PA_SC_ENHANCE_ECO_SPARE2_SIZE; + unsigned int eco_spare1 : PA_SC_ENHANCE_ECO_SPARE1_SIZE; + unsigned int eco_spare0 : PA_SC_ENHANCE_ECO_SPARE0_SIZE; + } pa_sc_enhance_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_enhance_t { + unsigned int eco_spare0 : PA_SC_ENHANCE_ECO_SPARE0_SIZE; + unsigned int eco_spare1 : PA_SC_ENHANCE_ECO_SPARE1_SIZE; + unsigned int eco_spare2 : PA_SC_ENHANCE_ECO_SPARE2_SIZE; + unsigned int eco_spare3 : PA_SC_ENHANCE_ECO_SPARE3_SIZE; + unsigned int : 28; + } pa_sc_enhance_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_enhance_t f; +} pa_sc_enhance_u; + + +/* + * PA_SU_VTX_CNTL struct + */ + +#define PA_SU_VTX_CNTL_PIX_CENTER_SIZE 1 +#define PA_SU_VTX_CNTL_ROUND_MODE_SIZE 2 +#define PA_SU_VTX_CNTL_QUANT_MODE_SIZE 3 + +#define PA_SU_VTX_CNTL_PIX_CENTER_SHIFT 0 +#define PA_SU_VTX_CNTL_ROUND_MODE_SHIFT 1 +#define PA_SU_VTX_CNTL_QUANT_MODE_SHIFT 3 + +#define PA_SU_VTX_CNTL_PIX_CENTER_MASK 0x00000001 +#define PA_SU_VTX_CNTL_ROUND_MODE_MASK 0x00000006 +#define PA_SU_VTX_CNTL_QUANT_MODE_MASK 0x00000038 + +#define PA_SU_VTX_CNTL_MASK \ + (PA_SU_VTX_CNTL_PIX_CENTER_MASK | \ + PA_SU_VTX_CNTL_ROUND_MODE_MASK | \ + PA_SU_VTX_CNTL_QUANT_MODE_MASK) + +#define PA_SU_VTX_CNTL(pix_center, round_mode, quant_mode) \ + ((pix_center << PA_SU_VTX_CNTL_PIX_CENTER_SHIFT) | \ + (round_mode << PA_SU_VTX_CNTL_ROUND_MODE_SHIFT) | \ + (quant_mode << PA_SU_VTX_CNTL_QUANT_MODE_SHIFT)) + +#define PA_SU_VTX_CNTL_GET_PIX_CENTER(pa_su_vtx_cntl) \ + ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_PIX_CENTER_MASK) >> PA_SU_VTX_CNTL_PIX_CENTER_SHIFT) +#define PA_SU_VTX_CNTL_GET_ROUND_MODE(pa_su_vtx_cntl) \ + ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_ROUND_MODE_MASK) >> PA_SU_VTX_CNTL_ROUND_MODE_SHIFT) +#define PA_SU_VTX_CNTL_GET_QUANT_MODE(pa_su_vtx_cntl) \ + ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_QUANT_MODE_MASK) >> PA_SU_VTX_CNTL_QUANT_MODE_SHIFT) + +#define PA_SU_VTX_CNTL_SET_PIX_CENTER(pa_su_vtx_cntl_reg, pix_center) \ + pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_PIX_CENTER_MASK) | (pix_center << PA_SU_VTX_CNTL_PIX_CENTER_SHIFT) +#define PA_SU_VTX_CNTL_SET_ROUND_MODE(pa_su_vtx_cntl_reg, round_mode) \ + pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_ROUND_MODE_MASK) | (round_mode << PA_SU_VTX_CNTL_ROUND_MODE_SHIFT) +#define PA_SU_VTX_CNTL_SET_QUANT_MODE(pa_su_vtx_cntl_reg, quant_mode) \ + pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_QUANT_MODE_MASK) | (quant_mode << PA_SU_VTX_CNTL_QUANT_MODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_vtx_cntl_t { + unsigned int pix_center : PA_SU_VTX_CNTL_PIX_CENTER_SIZE; + unsigned int round_mode : PA_SU_VTX_CNTL_ROUND_MODE_SIZE; + unsigned int quant_mode : PA_SU_VTX_CNTL_QUANT_MODE_SIZE; + unsigned int : 26; + } pa_su_vtx_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_vtx_cntl_t { + unsigned int : 26; + unsigned int quant_mode : PA_SU_VTX_CNTL_QUANT_MODE_SIZE; + unsigned int round_mode : PA_SU_VTX_CNTL_ROUND_MODE_SIZE; + unsigned int pix_center : PA_SU_VTX_CNTL_PIX_CENTER_SIZE; + } pa_su_vtx_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_vtx_cntl_t f; +} pa_su_vtx_cntl_u; + + +/* + * PA_SU_POINT_SIZE struct + */ + +#define PA_SU_POINT_SIZE_HEIGHT_SIZE 16 +#define PA_SU_POINT_SIZE_WIDTH_SIZE 16 + +#define PA_SU_POINT_SIZE_HEIGHT_SHIFT 0 +#define PA_SU_POINT_SIZE_WIDTH_SHIFT 16 + +#define PA_SU_POINT_SIZE_HEIGHT_MASK 0x0000ffff +#define PA_SU_POINT_SIZE_WIDTH_MASK 0xffff0000 + +#define PA_SU_POINT_SIZE_MASK \ + (PA_SU_POINT_SIZE_HEIGHT_MASK | \ + PA_SU_POINT_SIZE_WIDTH_MASK) + +#define PA_SU_POINT_SIZE(height, width) \ + ((height << PA_SU_POINT_SIZE_HEIGHT_SHIFT) | \ + (width << PA_SU_POINT_SIZE_WIDTH_SHIFT)) + +#define PA_SU_POINT_SIZE_GET_HEIGHT(pa_su_point_size) \ + ((pa_su_point_size & PA_SU_POINT_SIZE_HEIGHT_MASK) >> PA_SU_POINT_SIZE_HEIGHT_SHIFT) +#define PA_SU_POINT_SIZE_GET_WIDTH(pa_su_point_size) \ + ((pa_su_point_size & PA_SU_POINT_SIZE_WIDTH_MASK) >> PA_SU_POINT_SIZE_WIDTH_SHIFT) + +#define PA_SU_POINT_SIZE_SET_HEIGHT(pa_su_point_size_reg, height) \ + pa_su_point_size_reg = (pa_su_point_size_reg & ~PA_SU_POINT_SIZE_HEIGHT_MASK) | (height << PA_SU_POINT_SIZE_HEIGHT_SHIFT) +#define PA_SU_POINT_SIZE_SET_WIDTH(pa_su_point_size_reg, width) \ + pa_su_point_size_reg = (pa_su_point_size_reg & ~PA_SU_POINT_SIZE_WIDTH_MASK) | (width << PA_SU_POINT_SIZE_WIDTH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_point_size_t { + unsigned int height : PA_SU_POINT_SIZE_HEIGHT_SIZE; + unsigned int width : PA_SU_POINT_SIZE_WIDTH_SIZE; + } pa_su_point_size_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_point_size_t { + unsigned int width : PA_SU_POINT_SIZE_WIDTH_SIZE; + unsigned int height : PA_SU_POINT_SIZE_HEIGHT_SIZE; + } pa_su_point_size_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_point_size_t f; +} pa_su_point_size_u; + + +/* + * PA_SU_POINT_MINMAX struct + */ + +#define PA_SU_POINT_MINMAX_MIN_SIZE_SIZE 16 +#define PA_SU_POINT_MINMAX_MAX_SIZE_SIZE 16 + +#define PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT 0 +#define PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT 16 + +#define PA_SU_POINT_MINMAX_MIN_SIZE_MASK 0x0000ffff +#define PA_SU_POINT_MINMAX_MAX_SIZE_MASK 0xffff0000 + +#define PA_SU_POINT_MINMAX_MASK \ + (PA_SU_POINT_MINMAX_MIN_SIZE_MASK | \ + PA_SU_POINT_MINMAX_MAX_SIZE_MASK) + +#define PA_SU_POINT_MINMAX(min_size, max_size) \ + ((min_size << PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT) | \ + (max_size << PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT)) + +#define PA_SU_POINT_MINMAX_GET_MIN_SIZE(pa_su_point_minmax) \ + ((pa_su_point_minmax & PA_SU_POINT_MINMAX_MIN_SIZE_MASK) >> PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT) +#define PA_SU_POINT_MINMAX_GET_MAX_SIZE(pa_su_point_minmax) \ + ((pa_su_point_minmax & PA_SU_POINT_MINMAX_MAX_SIZE_MASK) >> PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT) + +#define PA_SU_POINT_MINMAX_SET_MIN_SIZE(pa_su_point_minmax_reg, min_size) \ + pa_su_point_minmax_reg = (pa_su_point_minmax_reg & ~PA_SU_POINT_MINMAX_MIN_SIZE_MASK) | (min_size << PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT) +#define PA_SU_POINT_MINMAX_SET_MAX_SIZE(pa_su_point_minmax_reg, max_size) \ + pa_su_point_minmax_reg = (pa_su_point_minmax_reg & ~PA_SU_POINT_MINMAX_MAX_SIZE_MASK) | (max_size << PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_point_minmax_t { + unsigned int min_size : PA_SU_POINT_MINMAX_MIN_SIZE_SIZE; + unsigned int max_size : PA_SU_POINT_MINMAX_MAX_SIZE_SIZE; + } pa_su_point_minmax_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_point_minmax_t { + unsigned int max_size : PA_SU_POINT_MINMAX_MAX_SIZE_SIZE; + unsigned int min_size : PA_SU_POINT_MINMAX_MIN_SIZE_SIZE; + } pa_su_point_minmax_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_point_minmax_t f; +} pa_su_point_minmax_u; + + +/* + * PA_SU_LINE_CNTL struct + */ + +#define PA_SU_LINE_CNTL_WIDTH_SIZE 16 + +#define PA_SU_LINE_CNTL_WIDTH_SHIFT 0 + +#define PA_SU_LINE_CNTL_WIDTH_MASK 0x0000ffff + +#define PA_SU_LINE_CNTL_MASK \ + (PA_SU_LINE_CNTL_WIDTH_MASK) + +#define PA_SU_LINE_CNTL(width) \ + ((width << PA_SU_LINE_CNTL_WIDTH_SHIFT)) + +#define PA_SU_LINE_CNTL_GET_WIDTH(pa_su_line_cntl) \ + ((pa_su_line_cntl & PA_SU_LINE_CNTL_WIDTH_MASK) >> PA_SU_LINE_CNTL_WIDTH_SHIFT) + +#define PA_SU_LINE_CNTL_SET_WIDTH(pa_su_line_cntl_reg, width) \ + pa_su_line_cntl_reg = (pa_su_line_cntl_reg & ~PA_SU_LINE_CNTL_WIDTH_MASK) | (width << PA_SU_LINE_CNTL_WIDTH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_line_cntl_t { + unsigned int width : PA_SU_LINE_CNTL_WIDTH_SIZE; + unsigned int : 16; + } pa_su_line_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_line_cntl_t { + unsigned int : 16; + unsigned int width : PA_SU_LINE_CNTL_WIDTH_SIZE; + } pa_su_line_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_line_cntl_t f; +} pa_su_line_cntl_u; + + +/* + * PA_SU_FACE_DATA struct + */ + +#define PA_SU_FACE_DATA_BASE_ADDR_SIZE 27 + +#define PA_SU_FACE_DATA_BASE_ADDR_SHIFT 5 + +#define PA_SU_FACE_DATA_BASE_ADDR_MASK 0xffffffe0 + +#define PA_SU_FACE_DATA_MASK \ + (PA_SU_FACE_DATA_BASE_ADDR_MASK) + +#define PA_SU_FACE_DATA(base_addr) \ + ((base_addr << PA_SU_FACE_DATA_BASE_ADDR_SHIFT)) + +#define PA_SU_FACE_DATA_GET_BASE_ADDR(pa_su_face_data) \ + ((pa_su_face_data & PA_SU_FACE_DATA_BASE_ADDR_MASK) >> PA_SU_FACE_DATA_BASE_ADDR_SHIFT) + +#define PA_SU_FACE_DATA_SET_BASE_ADDR(pa_su_face_data_reg, base_addr) \ + pa_su_face_data_reg = (pa_su_face_data_reg & ~PA_SU_FACE_DATA_BASE_ADDR_MASK) | (base_addr << PA_SU_FACE_DATA_BASE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_face_data_t { + unsigned int : 5; + unsigned int base_addr : PA_SU_FACE_DATA_BASE_ADDR_SIZE; + } pa_su_face_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_face_data_t { + unsigned int base_addr : PA_SU_FACE_DATA_BASE_ADDR_SIZE; + unsigned int : 5; + } pa_su_face_data_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_face_data_t f; +} pa_su_face_data_u; + + +/* + * PA_SU_SC_MODE_CNTL struct + */ + +#define PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE 1 +#define PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE 1 +#define PA_SU_SC_MODE_CNTL_FACE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE 2 +#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE 3 +#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE 3 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE 1 +#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE 1 +#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE 1 +#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE 1 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SIZE 1 +#define PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SIZE 1 + +#define PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT 0 +#define PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT 1 +#define PA_SU_SC_MODE_CNTL_FACE_SHIFT 2 +#define PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT 3 +#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT 5 +#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT 8 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT 11 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT 12 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT 13 +#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT 15 +#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT 16 +#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT 18 +#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT 19 +#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT 20 +#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT 21 +#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT 23 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT 25 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT 26 +#define PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT 29 +#define PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT 30 +#define PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT 31 + +#define PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK 0x00000001 +#define PA_SU_SC_MODE_CNTL_CULL_BACK_MASK 0x00000002 +#define PA_SU_SC_MODE_CNTL_FACE_MASK 0x00000004 +#define PA_SU_SC_MODE_CNTL_POLY_MODE_MASK 0x00000018 +#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK 0x000000e0 +#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK 0x00000700 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK 0x00001000 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK 0x00002000 +#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK 0x00008000 +#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000 +#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK 0x00040000 +#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK 0x00080000 +#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK 0x00100000 +#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK 0x00200000 +#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK 0x00800000 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK 0x02000000 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK 0x04000000 +#define PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK 0x20000000 +#define PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK 0x40000000 +#define PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK 0x80000000 + +#define PA_SU_SC_MODE_CNTL_MASK \ + (PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK | \ + PA_SU_SC_MODE_CNTL_CULL_BACK_MASK | \ + PA_SU_SC_MODE_CNTL_FACE_MASK | \ + PA_SU_SC_MODE_CNTL_POLY_MODE_MASK | \ + PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK | \ + PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK | \ + PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK | \ + PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK | \ + PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK | \ + PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK | \ + PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK | \ + PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK | \ + PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK) + +#define PA_SU_SC_MODE_CNTL(cull_front, cull_back, face, poly_mode, polymode_front_ptype, polymode_back_ptype, poly_offset_front_enable, poly_offset_back_enable, poly_offset_para_enable, msaa_enable, vtx_window_offset_enable, line_stipple_enable, provoking_vtx_last, persp_corr_dis, multi_prim_ib_ena, quad_order_enable, wait_rb_idle_all_tri, wait_rb_idle_first_tri_new_state, zero_area_faceness, face_kill_enable, face_write_enable) \ + ((cull_front << PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT) | \ + (cull_back << PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT) | \ + (face << PA_SU_SC_MODE_CNTL_FACE_SHIFT) | \ + (poly_mode << PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT) | \ + (polymode_front_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT) | \ + (polymode_back_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT) | \ + (poly_offset_front_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT) | \ + (poly_offset_back_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT) | \ + (poly_offset_para_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT) | \ + (msaa_enable << PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT) | \ + (vtx_window_offset_enable << PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT) | \ + (line_stipple_enable << PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT) | \ + (provoking_vtx_last << PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT) | \ + (persp_corr_dis << PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT) | \ + (multi_prim_ib_ena << PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT) | \ + (quad_order_enable << PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT) | \ + (wait_rb_idle_all_tri << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT) | \ + (wait_rb_idle_first_tri_new_state << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT) | \ + (zero_area_faceness << PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT) | \ + (face_kill_enable << PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT) | \ + (face_write_enable << PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT)) + +#define PA_SU_SC_MODE_CNTL_GET_CULL_FRONT(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK) >> PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_CULL_BACK(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_CULL_BACK_MASK) >> PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_FACE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_FACE_MASK) >> PA_SU_SC_MODE_CNTL_FACE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLY_MODE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_MODE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLYMODE_FRONT_PTYPE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK) >> PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLYMODE_BACK_PTYPE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK) >> PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_FRONT_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_BACK_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_PARA_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_MSAA_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_VTX_WINDOW_OFFSET_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_LINE_STIPPLE_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_PROVOKING_VTX_LAST(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK) >> PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_PERSP_CORR_DIS(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK) >> PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_MULTI_PRIM_IB_ENA(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK) >> PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_QUAD_ORDER_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_WAIT_RB_IDLE_ALL_TRI(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK) >> PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK) >> PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_ZERO_AREA_FACENESS(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK) >> PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_FACE_KILL_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_FACE_WRITE_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT) + +#define PA_SU_SC_MODE_CNTL_SET_CULL_FRONT(pa_su_sc_mode_cntl_reg, cull_front) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK) | (cull_front << PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_CULL_BACK(pa_su_sc_mode_cntl_reg, cull_back) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_CULL_BACK_MASK) | (cull_back << PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_FACE(pa_su_sc_mode_cntl_reg, face) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_FACE_MASK) | (face << PA_SU_SC_MODE_CNTL_FACE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLY_MODE(pa_su_sc_mode_cntl_reg, poly_mode) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_MODE_MASK) | (poly_mode << PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLYMODE_FRONT_PTYPE(pa_su_sc_mode_cntl_reg, polymode_front_ptype) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK) | (polymode_front_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLYMODE_BACK_PTYPE(pa_su_sc_mode_cntl_reg, polymode_back_ptype) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK) | (polymode_back_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_FRONT_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_front_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK) | (poly_offset_front_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_BACK_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_back_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK) | (poly_offset_back_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_PARA_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_para_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK) | (poly_offset_para_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_MSAA_ENABLE(pa_su_sc_mode_cntl_reg, msaa_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK) | (msaa_enable << PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_VTX_WINDOW_OFFSET_ENABLE(pa_su_sc_mode_cntl_reg, vtx_window_offset_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK) | (vtx_window_offset_enable << PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_LINE_STIPPLE_ENABLE(pa_su_sc_mode_cntl_reg, line_stipple_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK) | (line_stipple_enable << PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_PROVOKING_VTX_LAST(pa_su_sc_mode_cntl_reg, provoking_vtx_last) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK) | (provoking_vtx_last << PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_PERSP_CORR_DIS(pa_su_sc_mode_cntl_reg, persp_corr_dis) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK) | (persp_corr_dis << PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_MULTI_PRIM_IB_ENA(pa_su_sc_mode_cntl_reg, multi_prim_ib_ena) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK) | (multi_prim_ib_ena << PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_QUAD_ORDER_ENABLE(pa_su_sc_mode_cntl_reg, quad_order_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK) | (quad_order_enable << PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_WAIT_RB_IDLE_ALL_TRI(pa_su_sc_mode_cntl_reg, wait_rb_idle_all_tri) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK) | (wait_rb_idle_all_tri << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE(pa_su_sc_mode_cntl_reg, wait_rb_idle_first_tri_new_state) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK) | (wait_rb_idle_first_tri_new_state << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_ZERO_AREA_FACENESS(pa_su_sc_mode_cntl_reg, zero_area_faceness) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK) | (zero_area_faceness << PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_FACE_KILL_ENABLE(pa_su_sc_mode_cntl_reg, face_kill_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK) | (face_kill_enable << PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_FACE_WRITE_ENABLE(pa_su_sc_mode_cntl_reg, face_write_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK) | (face_write_enable << PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_sc_mode_cntl_t { + unsigned int cull_front : PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE; + unsigned int cull_back : PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE; + unsigned int face : PA_SU_SC_MODE_CNTL_FACE_SIZE; + unsigned int poly_mode : PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE; + unsigned int polymode_front_ptype : PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE; + unsigned int polymode_back_ptype : PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE; + unsigned int poly_offset_front_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE; + unsigned int poly_offset_back_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE; + unsigned int poly_offset_para_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE; + unsigned int : 1; + unsigned int msaa_enable : PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE; + unsigned int vtx_window_offset_enable : PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE; + unsigned int : 1; + unsigned int line_stipple_enable : PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE; + unsigned int provoking_vtx_last : PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE; + unsigned int persp_corr_dis : PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE; + unsigned int multi_prim_ib_ena : PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE; + unsigned int : 1; + unsigned int quad_order_enable : PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE; + unsigned int : 1; + unsigned int wait_rb_idle_all_tri : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE; + unsigned int wait_rb_idle_first_tri_new_state : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE; + unsigned int : 2; + unsigned int zero_area_faceness : PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SIZE; + unsigned int face_kill_enable : PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SIZE; + unsigned int face_write_enable : PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SIZE; + } pa_su_sc_mode_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_sc_mode_cntl_t { + unsigned int face_write_enable : PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SIZE; + unsigned int face_kill_enable : PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SIZE; + unsigned int zero_area_faceness : PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SIZE; + unsigned int : 2; + unsigned int wait_rb_idle_first_tri_new_state : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE; + unsigned int wait_rb_idle_all_tri : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE; + unsigned int : 1; + unsigned int quad_order_enable : PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE; + unsigned int : 1; + unsigned int multi_prim_ib_ena : PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE; + unsigned int persp_corr_dis : PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE; + unsigned int provoking_vtx_last : PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE; + unsigned int line_stipple_enable : PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE; + unsigned int : 1; + unsigned int vtx_window_offset_enable : PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE; + unsigned int msaa_enable : PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE; + unsigned int : 1; + unsigned int poly_offset_para_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE; + unsigned int poly_offset_back_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE; + unsigned int poly_offset_front_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE; + unsigned int polymode_back_ptype : PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE; + unsigned int polymode_front_ptype : PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE; + unsigned int poly_mode : PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE; + unsigned int face : PA_SU_SC_MODE_CNTL_FACE_SIZE; + unsigned int cull_back : PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE; + unsigned int cull_front : PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE; + } pa_su_sc_mode_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_sc_mode_cntl_t f; +} pa_su_sc_mode_cntl_u; + + +/* + * PA_SU_POLY_OFFSET_FRONT_SCALE struct + */ + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE 32 + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT 0 + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK 0xffffffff + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_MASK \ + (PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) + +#define PA_SU_POLY_OFFSET_FRONT_SCALE(scale) \ + ((scale << PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT)) + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_GET_SCALE(pa_su_poly_offset_front_scale) \ + ((pa_su_poly_offset_front_scale & PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) >> PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT) + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_SET_SCALE(pa_su_poly_offset_front_scale_reg, scale) \ + pa_su_poly_offset_front_scale_reg = (pa_su_poly_offset_front_scale_reg & ~PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) | (scale << PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_front_scale_t { + unsigned int scale : PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE; + } pa_su_poly_offset_front_scale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_front_scale_t { + unsigned int scale : PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE; + } pa_su_poly_offset_front_scale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_poly_offset_front_scale_t f; +} pa_su_poly_offset_front_scale_u; + + +/* + * PA_SU_POLY_OFFSET_FRONT_OFFSET struct + */ + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE 32 + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT 0 + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK 0xffffffff + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_MASK \ + (PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET(offset) \ + ((offset << PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT)) + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_GET_OFFSET(pa_su_poly_offset_front_offset) \ + ((pa_su_poly_offset_front_offset & PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) >> PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT) + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_SET_OFFSET(pa_su_poly_offset_front_offset_reg, offset) \ + pa_su_poly_offset_front_offset_reg = (pa_su_poly_offset_front_offset_reg & ~PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) | (offset << PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_front_offset_t { + unsigned int offset : PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE; + } pa_su_poly_offset_front_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_front_offset_t { + unsigned int offset : PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE; + } pa_su_poly_offset_front_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_poly_offset_front_offset_t f; +} pa_su_poly_offset_front_offset_u; + + +/* + * PA_SU_POLY_OFFSET_BACK_SCALE struct + */ + +#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE 32 + +#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT 0 + +#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK 0xffffffff + +#define PA_SU_POLY_OFFSET_BACK_SCALE_MASK \ + (PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) + +#define PA_SU_POLY_OFFSET_BACK_SCALE(scale) \ + ((scale << PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT)) + +#define PA_SU_POLY_OFFSET_BACK_SCALE_GET_SCALE(pa_su_poly_offset_back_scale) \ + ((pa_su_poly_offset_back_scale & PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) >> PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT) + +#define PA_SU_POLY_OFFSET_BACK_SCALE_SET_SCALE(pa_su_poly_offset_back_scale_reg, scale) \ + pa_su_poly_offset_back_scale_reg = (pa_su_poly_offset_back_scale_reg & ~PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) | (scale << PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_back_scale_t { + unsigned int scale : PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE; + } pa_su_poly_offset_back_scale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_back_scale_t { + unsigned int scale : PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE; + } pa_su_poly_offset_back_scale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_poly_offset_back_scale_t f; +} pa_su_poly_offset_back_scale_u; + + +/* + * PA_SU_POLY_OFFSET_BACK_OFFSET struct + */ + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE 32 + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT 0 + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK 0xffffffff + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_MASK \ + (PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) + +#define PA_SU_POLY_OFFSET_BACK_OFFSET(offset) \ + ((offset << PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT)) + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_GET_OFFSET(pa_su_poly_offset_back_offset) \ + ((pa_su_poly_offset_back_offset & PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) >> PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT) + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_SET_OFFSET(pa_su_poly_offset_back_offset_reg, offset) \ + pa_su_poly_offset_back_offset_reg = (pa_su_poly_offset_back_offset_reg & ~PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) | (offset << PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_back_offset_t { + unsigned int offset : PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE; + } pa_su_poly_offset_back_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_back_offset_t { + unsigned int offset : PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE; + } pa_su_poly_offset_back_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_poly_offset_back_offset_t f; +} pa_su_poly_offset_back_offset_u; + + +/* + * PA_SU_PERFCOUNTER0_SELECT struct + */ + +#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SU_PERFCOUNTER0_SELECT_MASK \ + (PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define PA_SU_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define PA_SU_PERFCOUNTER0_SELECT_GET_PERF_SEL(pa_su_perfcounter0_select) \ + ((pa_su_perfcounter0_select & PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define PA_SU_PERFCOUNTER0_SELECT_SET_PERF_SEL(pa_su_perfcounter0_select_reg, perf_sel) \ + pa_su_perfcounter0_select_reg = (pa_su_perfcounter0_select_reg & ~PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_select_t { + unsigned int perf_sel : PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_su_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } pa_su_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter0_select_t f; +} pa_su_perfcounter0_select_u; + + +/* + * PA_SU_PERFCOUNTER1_SELECT struct + */ + +#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8 + +#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SU_PERFCOUNTER1_SELECT_MASK \ + (PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) + +#define PA_SU_PERFCOUNTER1_SELECT(perf_sel) \ + ((perf_sel << PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)) + +#define PA_SU_PERFCOUNTER1_SELECT_GET_PERF_SEL(pa_su_perfcounter1_select) \ + ((pa_su_perfcounter1_select & PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#define PA_SU_PERFCOUNTER1_SELECT_SET_PERF_SEL(pa_su_perfcounter1_select_reg, perf_sel) \ + pa_su_perfcounter1_select_reg = (pa_su_perfcounter1_select_reg & ~PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_select_t { + unsigned int perf_sel : PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_su_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + } pa_su_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter1_select_t f; +} pa_su_perfcounter1_select_u; + + +/* + * PA_SU_PERFCOUNTER2_SELECT struct + */ + +#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8 + +#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SU_PERFCOUNTER2_SELECT_MASK \ + (PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) + +#define PA_SU_PERFCOUNTER2_SELECT(perf_sel) \ + ((perf_sel << PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)) + +#define PA_SU_PERFCOUNTER2_SELECT_GET_PERF_SEL(pa_su_perfcounter2_select) \ + ((pa_su_perfcounter2_select & PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#define PA_SU_PERFCOUNTER2_SELECT_SET_PERF_SEL(pa_su_perfcounter2_select_reg, perf_sel) \ + pa_su_perfcounter2_select_reg = (pa_su_perfcounter2_select_reg & ~PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_select_t { + unsigned int perf_sel : PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_su_perfcounter2_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + } pa_su_perfcounter2_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter2_select_t f; +} pa_su_perfcounter2_select_u; + + +/* + * PA_SU_PERFCOUNTER3_SELECT struct + */ + +#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8 + +#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SU_PERFCOUNTER3_SELECT_MASK \ + (PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) + +#define PA_SU_PERFCOUNTER3_SELECT(perf_sel) \ + ((perf_sel << PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)) + +#define PA_SU_PERFCOUNTER3_SELECT_GET_PERF_SEL(pa_su_perfcounter3_select) \ + ((pa_su_perfcounter3_select & PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#define PA_SU_PERFCOUNTER3_SELECT_SET_PERF_SEL(pa_su_perfcounter3_select_reg, perf_sel) \ + pa_su_perfcounter3_select_reg = (pa_su_perfcounter3_select_reg & ~PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_select_t { + unsigned int perf_sel : PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_su_perfcounter3_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + } pa_su_perfcounter3_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter3_select_t f; +} pa_su_perfcounter3_select_u; + + +/* + * PA_SU_PERFCOUNTER0_LOW struct + */ + +#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SU_PERFCOUNTER0_LOW_MASK \ + (PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER0_LOW_GET_PERF_COUNT(pa_su_perfcounter0_low) \ + ((pa_su_perfcounter0_low & PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER0_LOW_SET_PERF_COUNT(pa_su_perfcounter0_low_reg, perf_count) \ + pa_su_perfcounter0_low_reg = (pa_su_perfcounter0_low_reg & ~PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter0_low_t f; +} pa_su_perfcounter0_low_u; + + +/* + * PA_SU_PERFCOUNTER0_HI struct + */ + +#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SU_PERFCOUNTER0_HI_MASK \ + (PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER0_HI_GET_PERF_COUNT(pa_su_perfcounter0_hi) \ + ((pa_su_perfcounter0_hi & PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER0_HI_SET_PERF_COUNT(pa_su_perfcounter0_hi_reg, perf_count) \ + pa_su_perfcounter0_hi_reg = (pa_su_perfcounter0_hi_reg & ~PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_hi_t { + unsigned int perf_count : PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_su_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } pa_su_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter0_hi_t f; +} pa_su_perfcounter0_hi_u; + + +/* + * PA_SU_PERFCOUNTER1_LOW struct + */ + +#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32 + +#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SU_PERFCOUNTER1_LOW_MASK \ + (PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER1_LOW(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER1_LOW_GET_PERF_COUNT(pa_su_perfcounter1_low) \ + ((pa_su_perfcounter1_low & PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER1_LOW_SET_PERF_COUNT(pa_su_perfcounter1_low_reg, perf_count) \ + pa_su_perfcounter1_low_reg = (pa_su_perfcounter1_low_reg & ~PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter1_low_t f; +} pa_su_perfcounter1_low_u; + + +/* + * PA_SU_PERFCOUNTER1_HI struct + */ + +#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16 + +#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SU_PERFCOUNTER1_HI_MASK \ + (PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER1_HI(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER1_HI_GET_PERF_COUNT(pa_su_perfcounter1_hi) \ + ((pa_su_perfcounter1_hi & PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER1_HI_SET_PERF_COUNT(pa_su_perfcounter1_hi_reg, perf_count) \ + pa_su_perfcounter1_hi_reg = (pa_su_perfcounter1_hi_reg & ~PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_hi_t { + unsigned int perf_count : PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_su_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + } pa_su_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter1_hi_t f; +} pa_su_perfcounter1_hi_u; + + +/* + * PA_SU_PERFCOUNTER2_LOW struct + */ + +#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32 + +#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SU_PERFCOUNTER2_LOW_MASK \ + (PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER2_LOW(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER2_LOW_GET_PERF_COUNT(pa_su_perfcounter2_low) \ + ((pa_su_perfcounter2_low & PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER2_LOW_SET_PERF_COUNT(pa_su_perfcounter2_low_reg, perf_count) \ + pa_su_perfcounter2_low_reg = (pa_su_perfcounter2_low_reg & ~PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter2_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter2_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter2_low_t f; +} pa_su_perfcounter2_low_u; + + +/* + * PA_SU_PERFCOUNTER2_HI struct + */ + +#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16 + +#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SU_PERFCOUNTER2_HI_MASK \ + (PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER2_HI(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER2_HI_GET_PERF_COUNT(pa_su_perfcounter2_hi) \ + ((pa_su_perfcounter2_hi & PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER2_HI_SET_PERF_COUNT(pa_su_perfcounter2_hi_reg, perf_count) \ + pa_su_perfcounter2_hi_reg = (pa_su_perfcounter2_hi_reg & ~PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_hi_t { + unsigned int perf_count : PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_su_perfcounter2_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + } pa_su_perfcounter2_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter2_hi_t f; +} pa_su_perfcounter2_hi_u; + + +/* + * PA_SU_PERFCOUNTER3_LOW struct + */ + +#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32 + +#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SU_PERFCOUNTER3_LOW_MASK \ + (PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER3_LOW(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER3_LOW_GET_PERF_COUNT(pa_su_perfcounter3_low) \ + ((pa_su_perfcounter3_low & PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER3_LOW_SET_PERF_COUNT(pa_su_perfcounter3_low_reg, perf_count) \ + pa_su_perfcounter3_low_reg = (pa_su_perfcounter3_low_reg & ~PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter3_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter3_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter3_low_t f; +} pa_su_perfcounter3_low_u; + + +/* + * PA_SU_PERFCOUNTER3_HI struct + */ + +#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16 + +#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SU_PERFCOUNTER3_HI_MASK \ + (PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER3_HI(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER3_HI_GET_PERF_COUNT(pa_su_perfcounter3_hi) \ + ((pa_su_perfcounter3_hi & PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER3_HI_SET_PERF_COUNT(pa_su_perfcounter3_hi_reg, perf_count) \ + pa_su_perfcounter3_hi_reg = (pa_su_perfcounter3_hi_reg & ~PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_hi_t { + unsigned int perf_count : PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_su_perfcounter3_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + } pa_su_perfcounter3_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter3_hi_t f; +} pa_su_perfcounter3_hi_u; + + +/* + * PA_SC_WINDOW_OFFSET struct + */ + +#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE 15 +#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE 15 + +#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT 0 +#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT 16 + +#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK 0x00007fff +#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK 0x7fff0000 + +#define PA_SC_WINDOW_OFFSET_MASK \ + (PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK | \ + PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) + +#define PA_SC_WINDOW_OFFSET(window_x_offset, window_y_offset) \ + ((window_x_offset << PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT) | \ + (window_y_offset << PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT)) + +#define PA_SC_WINDOW_OFFSET_GET_WINDOW_X_OFFSET(pa_sc_window_offset) \ + ((pa_sc_window_offset & PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK) >> PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT) +#define PA_SC_WINDOW_OFFSET_GET_WINDOW_Y_OFFSET(pa_sc_window_offset) \ + ((pa_sc_window_offset & PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) >> PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT) + +#define PA_SC_WINDOW_OFFSET_SET_WINDOW_X_OFFSET(pa_sc_window_offset_reg, window_x_offset) \ + pa_sc_window_offset_reg = (pa_sc_window_offset_reg & ~PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK) | (window_x_offset << PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT) +#define PA_SC_WINDOW_OFFSET_SET_WINDOW_Y_OFFSET(pa_sc_window_offset_reg, window_y_offset) \ + pa_sc_window_offset_reg = (pa_sc_window_offset_reg & ~PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) | (window_y_offset << PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_window_offset_t { + unsigned int window_x_offset : PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE; + unsigned int : 1; + unsigned int window_y_offset : PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE; + unsigned int : 1; + } pa_sc_window_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_window_offset_t { + unsigned int : 1; + unsigned int window_y_offset : PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE; + unsigned int : 1; + unsigned int window_x_offset : PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE; + } pa_sc_window_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_window_offset_t f; +} pa_sc_window_offset_u; + + +/* + * PA_SC_AA_CONFIG struct + */ + +#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE 3 +#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE 4 + +#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT 0 +#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT 13 + +#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK 0x00000007 +#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK 0x0001e000 + +#define PA_SC_AA_CONFIG_MASK \ + (PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK | \ + PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) + +#define PA_SC_AA_CONFIG(msaa_num_samples, max_sample_dist) \ + ((msaa_num_samples << PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT) | \ + (max_sample_dist << PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT)) + +#define PA_SC_AA_CONFIG_GET_MSAA_NUM_SAMPLES(pa_sc_aa_config) \ + ((pa_sc_aa_config & PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK) >> PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT) +#define PA_SC_AA_CONFIG_GET_MAX_SAMPLE_DIST(pa_sc_aa_config) \ + ((pa_sc_aa_config & PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) >> PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT) + +#define PA_SC_AA_CONFIG_SET_MSAA_NUM_SAMPLES(pa_sc_aa_config_reg, msaa_num_samples) \ + pa_sc_aa_config_reg = (pa_sc_aa_config_reg & ~PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK) | (msaa_num_samples << PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT) +#define PA_SC_AA_CONFIG_SET_MAX_SAMPLE_DIST(pa_sc_aa_config_reg, max_sample_dist) \ + pa_sc_aa_config_reg = (pa_sc_aa_config_reg & ~PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) | (max_sample_dist << PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_aa_config_t { + unsigned int msaa_num_samples : PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE; + unsigned int : 10; + unsigned int max_sample_dist : PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE; + unsigned int : 15; + } pa_sc_aa_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_aa_config_t { + unsigned int : 15; + unsigned int max_sample_dist : PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE; + unsigned int : 10; + unsigned int msaa_num_samples : PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE; + } pa_sc_aa_config_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_aa_config_t f; +} pa_sc_aa_config_u; + + +/* + * PA_SC_AA_MASK struct + */ + +#define PA_SC_AA_MASK_AA_MASK_SIZE 16 + +#define PA_SC_AA_MASK_AA_MASK_SHIFT 0 + +#define PA_SC_AA_MASK_AA_MASK_MASK 0x0000ffff + +#define PA_SC_AA_MASK_MASK \ + (PA_SC_AA_MASK_AA_MASK_MASK) + +#define PA_SC_AA_MASK(aa_mask) \ + ((aa_mask << PA_SC_AA_MASK_AA_MASK_SHIFT)) + +#define PA_SC_AA_MASK_GET_AA_MASK(pa_sc_aa_mask) \ + ((pa_sc_aa_mask & PA_SC_AA_MASK_AA_MASK_MASK) >> PA_SC_AA_MASK_AA_MASK_SHIFT) + +#define PA_SC_AA_MASK_SET_AA_MASK(pa_sc_aa_mask_reg, aa_mask) \ + pa_sc_aa_mask_reg = (pa_sc_aa_mask_reg & ~PA_SC_AA_MASK_AA_MASK_MASK) | (aa_mask << PA_SC_AA_MASK_AA_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_aa_mask_t { + unsigned int aa_mask : PA_SC_AA_MASK_AA_MASK_SIZE; + unsigned int : 16; + } pa_sc_aa_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_aa_mask_t { + unsigned int : 16; + unsigned int aa_mask : PA_SC_AA_MASK_AA_MASK_SIZE; + } pa_sc_aa_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_aa_mask_t f; +} pa_sc_aa_mask_u; + + +/* + * PA_SC_LINE_STIPPLE struct + */ + +#define PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE 16 +#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE 8 +#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE 1 +#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE 2 + +#define PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT 0 +#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT 16 +#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT 28 +#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT 29 + +#define PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK 0x0000ffff +#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK 0x00ff0000 +#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK 0x10000000 +#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK 0x60000000 + +#define PA_SC_LINE_STIPPLE_MASK \ + (PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK | \ + PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK | \ + PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK | \ + PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) + +#define PA_SC_LINE_STIPPLE(line_pattern, repeat_count, pattern_bit_order, auto_reset_cntl) \ + ((line_pattern << PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT) | \ + (repeat_count << PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT) | \ + (pattern_bit_order << PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT) | \ + (auto_reset_cntl << PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT)) + +#define PA_SC_LINE_STIPPLE_GET_LINE_PATTERN(pa_sc_line_stipple) \ + ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK) >> PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT) +#define PA_SC_LINE_STIPPLE_GET_REPEAT_COUNT(pa_sc_line_stipple) \ + ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK) >> PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT) +#define PA_SC_LINE_STIPPLE_GET_PATTERN_BIT_ORDER(pa_sc_line_stipple) \ + ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK) >> PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT) +#define PA_SC_LINE_STIPPLE_GET_AUTO_RESET_CNTL(pa_sc_line_stipple) \ + ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) >> PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT) + +#define PA_SC_LINE_STIPPLE_SET_LINE_PATTERN(pa_sc_line_stipple_reg, line_pattern) \ + pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK) | (line_pattern << PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT) +#define PA_SC_LINE_STIPPLE_SET_REPEAT_COUNT(pa_sc_line_stipple_reg, repeat_count) \ + pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK) | (repeat_count << PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT) +#define PA_SC_LINE_STIPPLE_SET_PATTERN_BIT_ORDER(pa_sc_line_stipple_reg, pattern_bit_order) \ + pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK) | (pattern_bit_order << PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT) +#define PA_SC_LINE_STIPPLE_SET_AUTO_RESET_CNTL(pa_sc_line_stipple_reg, auto_reset_cntl) \ + pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) | (auto_reset_cntl << PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_line_stipple_t { + unsigned int line_pattern : PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE; + unsigned int repeat_count : PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE; + unsigned int : 4; + unsigned int pattern_bit_order : PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE; + unsigned int auto_reset_cntl : PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE; + unsigned int : 1; + } pa_sc_line_stipple_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_line_stipple_t { + unsigned int : 1; + unsigned int auto_reset_cntl : PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE; + unsigned int pattern_bit_order : PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE; + unsigned int : 4; + unsigned int repeat_count : PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE; + unsigned int line_pattern : PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE; + } pa_sc_line_stipple_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_line_stipple_t f; +} pa_sc_line_stipple_u; + + +/* + * PA_SC_LINE_CNTL struct + */ + +#define PA_SC_LINE_CNTL_BRES_CNTL_SIZE 8 +#define PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE 1 +#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE 1 +#define PA_SC_LINE_CNTL_LAST_PIXEL_SIZE 1 + +#define PA_SC_LINE_CNTL_BRES_CNTL_SHIFT 0 +#define PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT 8 +#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT 9 +#define PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT 10 + +#define PA_SC_LINE_CNTL_BRES_CNTL_MASK 0x000000ff +#define PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK 0x00000100 +#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK 0x00000200 +#define PA_SC_LINE_CNTL_LAST_PIXEL_MASK 0x00000400 + +#define PA_SC_LINE_CNTL_MASK \ + (PA_SC_LINE_CNTL_BRES_CNTL_MASK | \ + PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK | \ + PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK | \ + PA_SC_LINE_CNTL_LAST_PIXEL_MASK) + +#define PA_SC_LINE_CNTL(bres_cntl, use_bres_cntl, expand_line_width, last_pixel) \ + ((bres_cntl << PA_SC_LINE_CNTL_BRES_CNTL_SHIFT) | \ + (use_bres_cntl << PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT) | \ + (expand_line_width << PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT) | \ + (last_pixel << PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT)) + +#define PA_SC_LINE_CNTL_GET_BRES_CNTL(pa_sc_line_cntl) \ + ((pa_sc_line_cntl & PA_SC_LINE_CNTL_BRES_CNTL_MASK) >> PA_SC_LINE_CNTL_BRES_CNTL_SHIFT) +#define PA_SC_LINE_CNTL_GET_USE_BRES_CNTL(pa_sc_line_cntl) \ + ((pa_sc_line_cntl & PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK) >> PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT) +#define PA_SC_LINE_CNTL_GET_EXPAND_LINE_WIDTH(pa_sc_line_cntl) \ + ((pa_sc_line_cntl & PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK) >> PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT) +#define PA_SC_LINE_CNTL_GET_LAST_PIXEL(pa_sc_line_cntl) \ + ((pa_sc_line_cntl & PA_SC_LINE_CNTL_LAST_PIXEL_MASK) >> PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT) + +#define PA_SC_LINE_CNTL_SET_BRES_CNTL(pa_sc_line_cntl_reg, bres_cntl) \ + pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_BRES_CNTL_MASK) | (bres_cntl << PA_SC_LINE_CNTL_BRES_CNTL_SHIFT) +#define PA_SC_LINE_CNTL_SET_USE_BRES_CNTL(pa_sc_line_cntl_reg, use_bres_cntl) \ + pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK) | (use_bres_cntl << PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT) +#define PA_SC_LINE_CNTL_SET_EXPAND_LINE_WIDTH(pa_sc_line_cntl_reg, expand_line_width) \ + pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK) | (expand_line_width << PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT) +#define PA_SC_LINE_CNTL_SET_LAST_PIXEL(pa_sc_line_cntl_reg, last_pixel) \ + pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_LAST_PIXEL_MASK) | (last_pixel << PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_line_cntl_t { + unsigned int bres_cntl : PA_SC_LINE_CNTL_BRES_CNTL_SIZE; + unsigned int use_bres_cntl : PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE; + unsigned int expand_line_width : PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE; + unsigned int last_pixel : PA_SC_LINE_CNTL_LAST_PIXEL_SIZE; + unsigned int : 21; + } pa_sc_line_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_line_cntl_t { + unsigned int : 21; + unsigned int last_pixel : PA_SC_LINE_CNTL_LAST_PIXEL_SIZE; + unsigned int expand_line_width : PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE; + unsigned int use_bres_cntl : PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE; + unsigned int bres_cntl : PA_SC_LINE_CNTL_BRES_CNTL_SIZE; + } pa_sc_line_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_line_cntl_t f; +} pa_sc_line_cntl_u; + + +/* + * PA_SC_WINDOW_SCISSOR_TL struct + */ + +#define PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE 14 +#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE 14 +#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE 1 + +#define PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT 0 +#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT 16 +#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT 31 + +#define PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK 0x00003fff +#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK 0x3fff0000 +#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK 0x80000000 + +#define PA_SC_WINDOW_SCISSOR_TL_MASK \ + (PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK | \ + PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK | \ + PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) + +#define PA_SC_WINDOW_SCISSOR_TL(tl_x, tl_y, window_offset_disable) \ + ((tl_x << PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT) | \ + (tl_y << PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT) | \ + (window_offset_disable << PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT)) + +#define PA_SC_WINDOW_SCISSOR_TL_GET_TL_X(pa_sc_window_scissor_tl) \ + ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK) >> PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT) +#define PA_SC_WINDOW_SCISSOR_TL_GET_TL_Y(pa_sc_window_scissor_tl) \ + ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK) >> PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT) +#define PA_SC_WINDOW_SCISSOR_TL_GET_WINDOW_OFFSET_DISABLE(pa_sc_window_scissor_tl) \ + ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) >> PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT) + +#define PA_SC_WINDOW_SCISSOR_TL_SET_TL_X(pa_sc_window_scissor_tl_reg, tl_x) \ + pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK) | (tl_x << PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT) +#define PA_SC_WINDOW_SCISSOR_TL_SET_TL_Y(pa_sc_window_scissor_tl_reg, tl_y) \ + pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK) | (tl_y << PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT) +#define PA_SC_WINDOW_SCISSOR_TL_SET_WINDOW_OFFSET_DISABLE(pa_sc_window_scissor_tl_reg, window_offset_disable) \ + pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) | (window_offset_disable << PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_window_scissor_tl_t { + unsigned int tl_x : PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE; + unsigned int : 2; + unsigned int tl_y : PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE; + unsigned int : 1; + unsigned int window_offset_disable : PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE; + } pa_sc_window_scissor_tl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_window_scissor_tl_t { + unsigned int window_offset_disable : PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE; + unsigned int : 1; + unsigned int tl_y : PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE; + unsigned int : 2; + unsigned int tl_x : PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE; + } pa_sc_window_scissor_tl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_window_scissor_tl_t f; +} pa_sc_window_scissor_tl_u; + + +/* + * PA_SC_WINDOW_SCISSOR_BR struct + */ + +#define PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE 14 +#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE 14 + +#define PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT 0 +#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT 16 + +#define PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK 0x00003fff +#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK 0x3fff0000 + +#define PA_SC_WINDOW_SCISSOR_BR_MASK \ + (PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK | \ + PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) + +#define PA_SC_WINDOW_SCISSOR_BR(br_x, br_y) \ + ((br_x << PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT) | \ + (br_y << PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT)) + +#define PA_SC_WINDOW_SCISSOR_BR_GET_BR_X(pa_sc_window_scissor_br) \ + ((pa_sc_window_scissor_br & PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK) >> PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT) +#define PA_SC_WINDOW_SCISSOR_BR_GET_BR_Y(pa_sc_window_scissor_br) \ + ((pa_sc_window_scissor_br & PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) >> PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT) + +#define PA_SC_WINDOW_SCISSOR_BR_SET_BR_X(pa_sc_window_scissor_br_reg, br_x) \ + pa_sc_window_scissor_br_reg = (pa_sc_window_scissor_br_reg & ~PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK) | (br_x << PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT) +#define PA_SC_WINDOW_SCISSOR_BR_SET_BR_Y(pa_sc_window_scissor_br_reg, br_y) \ + pa_sc_window_scissor_br_reg = (pa_sc_window_scissor_br_reg & ~PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) | (br_y << PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_window_scissor_br_t { + unsigned int br_x : PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE; + unsigned int : 2; + unsigned int br_y : PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE; + unsigned int : 2; + } pa_sc_window_scissor_br_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_window_scissor_br_t { + unsigned int : 2; + unsigned int br_y : PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE; + unsigned int : 2; + unsigned int br_x : PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE; + } pa_sc_window_scissor_br_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_window_scissor_br_t f; +} pa_sc_window_scissor_br_u; + + +/* + * PA_SC_SCREEN_SCISSOR_TL struct + */ + +#define PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE 15 +#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE 15 + +#define PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT 0 +#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT 16 + +#define PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK 0x00007fff +#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK 0x7fff0000 + +#define PA_SC_SCREEN_SCISSOR_TL_MASK \ + (PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK | \ + PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) + +#define PA_SC_SCREEN_SCISSOR_TL(tl_x, tl_y) \ + ((tl_x << PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT) | \ + (tl_y << PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT)) + +#define PA_SC_SCREEN_SCISSOR_TL_GET_TL_X(pa_sc_screen_scissor_tl) \ + ((pa_sc_screen_scissor_tl & PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK) >> PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT) +#define PA_SC_SCREEN_SCISSOR_TL_GET_TL_Y(pa_sc_screen_scissor_tl) \ + ((pa_sc_screen_scissor_tl & PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) >> PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT) + +#define PA_SC_SCREEN_SCISSOR_TL_SET_TL_X(pa_sc_screen_scissor_tl_reg, tl_x) \ + pa_sc_screen_scissor_tl_reg = (pa_sc_screen_scissor_tl_reg & ~PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK) | (tl_x << PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT) +#define PA_SC_SCREEN_SCISSOR_TL_SET_TL_Y(pa_sc_screen_scissor_tl_reg, tl_y) \ + pa_sc_screen_scissor_tl_reg = (pa_sc_screen_scissor_tl_reg & ~PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) | (tl_y << PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_screen_scissor_tl_t { + unsigned int tl_x : PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE; + unsigned int : 1; + unsigned int tl_y : PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE; + unsigned int : 1; + } pa_sc_screen_scissor_tl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_screen_scissor_tl_t { + unsigned int : 1; + unsigned int tl_y : PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE; + unsigned int : 1; + unsigned int tl_x : PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE; + } pa_sc_screen_scissor_tl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_screen_scissor_tl_t f; +} pa_sc_screen_scissor_tl_u; + + +/* + * PA_SC_SCREEN_SCISSOR_BR struct + */ + +#define PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE 15 +#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE 15 + +#define PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT 0 +#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT 16 + +#define PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK 0x00007fff +#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK 0x7fff0000 + +#define PA_SC_SCREEN_SCISSOR_BR_MASK \ + (PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK | \ + PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) + +#define PA_SC_SCREEN_SCISSOR_BR(br_x, br_y) \ + ((br_x << PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT) | \ + (br_y << PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT)) + +#define PA_SC_SCREEN_SCISSOR_BR_GET_BR_X(pa_sc_screen_scissor_br) \ + ((pa_sc_screen_scissor_br & PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK) >> PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT) +#define PA_SC_SCREEN_SCISSOR_BR_GET_BR_Y(pa_sc_screen_scissor_br) \ + ((pa_sc_screen_scissor_br & PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) >> PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT) + +#define PA_SC_SCREEN_SCISSOR_BR_SET_BR_X(pa_sc_screen_scissor_br_reg, br_x) \ + pa_sc_screen_scissor_br_reg = (pa_sc_screen_scissor_br_reg & ~PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK) | (br_x << PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT) +#define PA_SC_SCREEN_SCISSOR_BR_SET_BR_Y(pa_sc_screen_scissor_br_reg, br_y) \ + pa_sc_screen_scissor_br_reg = (pa_sc_screen_scissor_br_reg & ~PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) | (br_y << PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_screen_scissor_br_t { + unsigned int br_x : PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE; + unsigned int : 1; + unsigned int br_y : PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE; + unsigned int : 1; + } pa_sc_screen_scissor_br_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_screen_scissor_br_t { + unsigned int : 1; + unsigned int br_y : PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE; + unsigned int : 1; + unsigned int br_x : PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE; + } pa_sc_screen_scissor_br_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_screen_scissor_br_t f; +} pa_sc_screen_scissor_br_u; + + +/* + * PA_SC_VIZ_QUERY struct + */ + +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE 1 +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE 5 +#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE 1 + +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT 0 +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT 1 +#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT 7 + +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK 0x00000001 +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK 0x0000003e +#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK 0x00000080 + +#define PA_SC_VIZ_QUERY_MASK \ + (PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK | \ + PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK | \ + PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) + +#define PA_SC_VIZ_QUERY(viz_query_ena, viz_query_id, kill_pix_post_early_z) \ + ((viz_query_ena << PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT) | \ + (viz_query_id << PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT) | \ + (kill_pix_post_early_z << PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT)) + +#define PA_SC_VIZ_QUERY_GET_VIZ_QUERY_ENA(pa_sc_viz_query) \ + ((pa_sc_viz_query & PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK) >> PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT) +#define PA_SC_VIZ_QUERY_GET_VIZ_QUERY_ID(pa_sc_viz_query) \ + ((pa_sc_viz_query & PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK) >> PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT) +#define PA_SC_VIZ_QUERY_GET_KILL_PIX_POST_EARLY_Z(pa_sc_viz_query) \ + ((pa_sc_viz_query & PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) >> PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT) + +#define PA_SC_VIZ_QUERY_SET_VIZ_QUERY_ENA(pa_sc_viz_query_reg, viz_query_ena) \ + pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK) | (viz_query_ena << PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT) +#define PA_SC_VIZ_QUERY_SET_VIZ_QUERY_ID(pa_sc_viz_query_reg, viz_query_id) \ + pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK) | (viz_query_id << PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT) +#define PA_SC_VIZ_QUERY_SET_KILL_PIX_POST_EARLY_Z(pa_sc_viz_query_reg, kill_pix_post_early_z) \ + pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) | (kill_pix_post_early_z << PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_viz_query_t { + unsigned int viz_query_ena : PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE; + unsigned int viz_query_id : PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE; + unsigned int : 1; + unsigned int kill_pix_post_early_z : PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE; + unsigned int : 24; + } pa_sc_viz_query_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_viz_query_t { + unsigned int : 24; + unsigned int kill_pix_post_early_z : PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE; + unsigned int : 1; + unsigned int viz_query_id : PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE; + unsigned int viz_query_ena : PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE; + } pa_sc_viz_query_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_viz_query_t f; +} pa_sc_viz_query_u; + + +/* + * PA_SC_VIZ_QUERY_STATUS struct + */ + +#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE 32 + +#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT 0 + +#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK 0xffffffff + +#define PA_SC_VIZ_QUERY_STATUS_MASK \ + (PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) + +#define PA_SC_VIZ_QUERY_STATUS(status_bits) \ + ((status_bits << PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT)) + +#define PA_SC_VIZ_QUERY_STATUS_GET_STATUS_BITS(pa_sc_viz_query_status) \ + ((pa_sc_viz_query_status & PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) >> PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT) + +#define PA_SC_VIZ_QUERY_STATUS_SET_STATUS_BITS(pa_sc_viz_query_status_reg, status_bits) \ + pa_sc_viz_query_status_reg = (pa_sc_viz_query_status_reg & ~PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) | (status_bits << PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_viz_query_status_t { + unsigned int status_bits : PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE; + } pa_sc_viz_query_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_viz_query_status_t { + unsigned int status_bits : PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE; + } pa_sc_viz_query_status_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_viz_query_status_t f; +} pa_sc_viz_query_status_u; + + +/* + * PA_SC_LINE_STIPPLE_STATE struct + */ + +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE 4 +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE 8 + +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT 0 +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT 8 + +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK 0x0000000f +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK 0x0000ff00 + +#define PA_SC_LINE_STIPPLE_STATE_MASK \ + (PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK | \ + PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) + +#define PA_SC_LINE_STIPPLE_STATE(current_ptr, current_count) \ + ((current_ptr << PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT) | \ + (current_count << PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT)) + +#define PA_SC_LINE_STIPPLE_STATE_GET_CURRENT_PTR(pa_sc_line_stipple_state) \ + ((pa_sc_line_stipple_state & PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK) >> PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT) +#define PA_SC_LINE_STIPPLE_STATE_GET_CURRENT_COUNT(pa_sc_line_stipple_state) \ + ((pa_sc_line_stipple_state & PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) >> PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT) + +#define PA_SC_LINE_STIPPLE_STATE_SET_CURRENT_PTR(pa_sc_line_stipple_state_reg, current_ptr) \ + pa_sc_line_stipple_state_reg = (pa_sc_line_stipple_state_reg & ~PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK) | (current_ptr << PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT) +#define PA_SC_LINE_STIPPLE_STATE_SET_CURRENT_COUNT(pa_sc_line_stipple_state_reg, current_count) \ + pa_sc_line_stipple_state_reg = (pa_sc_line_stipple_state_reg & ~PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) | (current_count << PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_line_stipple_state_t { + unsigned int current_ptr : PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE; + unsigned int : 4; + unsigned int current_count : PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE; + unsigned int : 16; + } pa_sc_line_stipple_state_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_line_stipple_state_t { + unsigned int : 16; + unsigned int current_count : PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE; + unsigned int : 4; + unsigned int current_ptr : PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE; + } pa_sc_line_stipple_state_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_line_stipple_state_t f; +} pa_sc_line_stipple_state_u; + + +/* + * PA_SC_PERFCOUNTER0_SELECT struct + */ + +#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SC_PERFCOUNTER0_SELECT_MASK \ + (PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define PA_SC_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define PA_SC_PERFCOUNTER0_SELECT_GET_PERF_SEL(pa_sc_perfcounter0_select) \ + ((pa_sc_perfcounter0_select & PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define PA_SC_PERFCOUNTER0_SELECT_SET_PERF_SEL(pa_sc_perfcounter0_select_reg, perf_sel) \ + pa_sc_perfcounter0_select_reg = (pa_sc_perfcounter0_select_reg & ~PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_select_t { + unsigned int perf_sel : PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_sc_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } pa_sc_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_perfcounter0_select_t f; +} pa_sc_perfcounter0_select_u; + + +/* + * PA_SC_PERFCOUNTER0_LOW struct + */ + +#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SC_PERFCOUNTER0_LOW_MASK \ + (PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define PA_SC_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define PA_SC_PERFCOUNTER0_LOW_GET_PERF_COUNT(pa_sc_perfcounter0_low) \ + ((pa_sc_perfcounter0_low & PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define PA_SC_PERFCOUNTER0_LOW_SET_PERF_COUNT(pa_sc_perfcounter0_low_reg, perf_count) \ + pa_sc_perfcounter0_low_reg = (pa_sc_perfcounter0_low_reg & ~PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_low_t { + unsigned int perf_count : PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } pa_sc_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_low_t { + unsigned int perf_count : PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } pa_sc_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_perfcounter0_low_t f; +} pa_sc_perfcounter0_low_u; + + +/* + * PA_SC_PERFCOUNTER0_HI struct + */ + +#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SC_PERFCOUNTER0_HI_MASK \ + (PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define PA_SC_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define PA_SC_PERFCOUNTER0_HI_GET_PERF_COUNT(pa_sc_perfcounter0_hi) \ + ((pa_sc_perfcounter0_hi & PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define PA_SC_PERFCOUNTER0_HI_SET_PERF_COUNT(pa_sc_perfcounter0_hi_reg, perf_count) \ + pa_sc_perfcounter0_hi_reg = (pa_sc_perfcounter0_hi_reg & ~PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_hi_t { + unsigned int perf_count : PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_sc_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } pa_sc_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_perfcounter0_hi_t f; +} pa_sc_perfcounter0_hi_u; + + +/* + * PA_CL_CNTL_STATUS struct + */ + +#define PA_CL_CNTL_STATUS_CL_BUSY_SIZE 1 + +#define PA_CL_CNTL_STATUS_CL_BUSY_SHIFT 31 + +#define PA_CL_CNTL_STATUS_CL_BUSY_MASK 0x80000000 + +#define PA_CL_CNTL_STATUS_MASK \ + (PA_CL_CNTL_STATUS_CL_BUSY_MASK) + +#define PA_CL_CNTL_STATUS(cl_busy) \ + ((cl_busy << PA_CL_CNTL_STATUS_CL_BUSY_SHIFT)) + +#define PA_CL_CNTL_STATUS_GET_CL_BUSY(pa_cl_cntl_status) \ + ((pa_cl_cntl_status & PA_CL_CNTL_STATUS_CL_BUSY_MASK) >> PA_CL_CNTL_STATUS_CL_BUSY_SHIFT) + +#define PA_CL_CNTL_STATUS_SET_CL_BUSY(pa_cl_cntl_status_reg, cl_busy) \ + pa_cl_cntl_status_reg = (pa_cl_cntl_status_reg & ~PA_CL_CNTL_STATUS_CL_BUSY_MASK) | (cl_busy << PA_CL_CNTL_STATUS_CL_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_cntl_status_t { + unsigned int : 31; + unsigned int cl_busy : PA_CL_CNTL_STATUS_CL_BUSY_SIZE; + } pa_cl_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_cntl_status_t { + unsigned int cl_busy : PA_CL_CNTL_STATUS_CL_BUSY_SIZE; + unsigned int : 31; + } pa_cl_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_cntl_status_t f; +} pa_cl_cntl_status_u; + + +/* + * PA_SU_CNTL_STATUS struct + */ + +#define PA_SU_CNTL_STATUS_SU_BUSY_SIZE 1 + +#define PA_SU_CNTL_STATUS_SU_BUSY_SHIFT 31 + +#define PA_SU_CNTL_STATUS_SU_BUSY_MASK 0x80000000 + +#define PA_SU_CNTL_STATUS_MASK \ + (PA_SU_CNTL_STATUS_SU_BUSY_MASK) + +#define PA_SU_CNTL_STATUS(su_busy) \ + ((su_busy << PA_SU_CNTL_STATUS_SU_BUSY_SHIFT)) + +#define PA_SU_CNTL_STATUS_GET_SU_BUSY(pa_su_cntl_status) \ + ((pa_su_cntl_status & PA_SU_CNTL_STATUS_SU_BUSY_MASK) >> PA_SU_CNTL_STATUS_SU_BUSY_SHIFT) + +#define PA_SU_CNTL_STATUS_SET_SU_BUSY(pa_su_cntl_status_reg, su_busy) \ + pa_su_cntl_status_reg = (pa_su_cntl_status_reg & ~PA_SU_CNTL_STATUS_SU_BUSY_MASK) | (su_busy << PA_SU_CNTL_STATUS_SU_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_cntl_status_t { + unsigned int : 31; + unsigned int su_busy : PA_SU_CNTL_STATUS_SU_BUSY_SIZE; + } pa_su_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_cntl_status_t { + unsigned int su_busy : PA_SU_CNTL_STATUS_SU_BUSY_SIZE; + unsigned int : 31; + } pa_su_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_cntl_status_t f; +} pa_su_cntl_status_u; + + +/* + * PA_SC_CNTL_STATUS struct + */ + +#define PA_SC_CNTL_STATUS_SC_BUSY_SIZE 1 + +#define PA_SC_CNTL_STATUS_SC_BUSY_SHIFT 31 + +#define PA_SC_CNTL_STATUS_SC_BUSY_MASK 0x80000000 + +#define PA_SC_CNTL_STATUS_MASK \ + (PA_SC_CNTL_STATUS_SC_BUSY_MASK) + +#define PA_SC_CNTL_STATUS(sc_busy) \ + ((sc_busy << PA_SC_CNTL_STATUS_SC_BUSY_SHIFT)) + +#define PA_SC_CNTL_STATUS_GET_SC_BUSY(pa_sc_cntl_status) \ + ((pa_sc_cntl_status & PA_SC_CNTL_STATUS_SC_BUSY_MASK) >> PA_SC_CNTL_STATUS_SC_BUSY_SHIFT) + +#define PA_SC_CNTL_STATUS_SET_SC_BUSY(pa_sc_cntl_status_reg, sc_busy) \ + pa_sc_cntl_status_reg = (pa_sc_cntl_status_reg & ~PA_SC_CNTL_STATUS_SC_BUSY_MASK) | (sc_busy << PA_SC_CNTL_STATUS_SC_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_cntl_status_t { + unsigned int : 31; + unsigned int sc_busy : PA_SC_CNTL_STATUS_SC_BUSY_SIZE; + } pa_sc_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_cntl_status_t { + unsigned int sc_busy : PA_SC_CNTL_STATUS_SC_BUSY_SIZE; + unsigned int : 31; + } pa_sc_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_cntl_status_t f; +} pa_sc_cntl_status_u; + + +/* + * PA_SU_DEBUG_CNTL struct + */ + +#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE 5 + +#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT 0 + +#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK 0x0000001f + +#define PA_SU_DEBUG_CNTL_MASK \ + (PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) + +#define PA_SU_DEBUG_CNTL(su_debug_indx) \ + ((su_debug_indx << PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT)) + +#define PA_SU_DEBUG_CNTL_GET_SU_DEBUG_INDX(pa_su_debug_cntl) \ + ((pa_su_debug_cntl & PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) >> PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT) + +#define PA_SU_DEBUG_CNTL_SET_SU_DEBUG_INDX(pa_su_debug_cntl_reg, su_debug_indx) \ + pa_su_debug_cntl_reg = (pa_su_debug_cntl_reg & ~PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) | (su_debug_indx << PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_debug_cntl_t { + unsigned int su_debug_indx : PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE; + unsigned int : 27; + } pa_su_debug_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_debug_cntl_t { + unsigned int : 27; + unsigned int su_debug_indx : PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE; + } pa_su_debug_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_debug_cntl_t f; +} pa_su_debug_cntl_u; + + +/* + * PA_SU_DEBUG_DATA struct + */ + +#define PA_SU_DEBUG_DATA_DATA_SIZE 32 + +#define PA_SU_DEBUG_DATA_DATA_SHIFT 0 + +#define PA_SU_DEBUG_DATA_DATA_MASK 0xffffffff + +#define PA_SU_DEBUG_DATA_MASK \ + (PA_SU_DEBUG_DATA_DATA_MASK) + +#define PA_SU_DEBUG_DATA(data) \ + ((data << PA_SU_DEBUG_DATA_DATA_SHIFT)) + +#define PA_SU_DEBUG_DATA_GET_DATA(pa_su_debug_data) \ + ((pa_su_debug_data & PA_SU_DEBUG_DATA_DATA_MASK) >> PA_SU_DEBUG_DATA_DATA_SHIFT) + +#define PA_SU_DEBUG_DATA_SET_DATA(pa_su_debug_data_reg, data) \ + pa_su_debug_data_reg = (pa_su_debug_data_reg & ~PA_SU_DEBUG_DATA_DATA_MASK) | (data << PA_SU_DEBUG_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_debug_data_t { + unsigned int data : PA_SU_DEBUG_DATA_DATA_SIZE; + } pa_su_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_debug_data_t { + unsigned int data : PA_SU_DEBUG_DATA_DATA_SIZE; + } pa_su_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_debug_data_t f; +} pa_su_debug_data_u; + + +/* + * CLIPPER_DEBUG_REG00 struct + */ + +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE 12 + +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT 0 +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT 1 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT 2 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT 3 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT 4 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT 5 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT 6 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT 7 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT 8 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT 9 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT 10 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT 11 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT 12 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT 13 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT 14 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT 15 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT 16 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT 17 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT 18 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT 19 +#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT 20 + +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK 0x00000001 +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK 0x00000002 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK 0x00000004 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK 0x00000008 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK 0x00000010 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK 0x00000020 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK 0x00000040 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK 0x00000080 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK 0x00000100 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK 0x00000200 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK 0x00000400 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK 0x00000800 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK 0x00001000 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK 0x00002000 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK 0x00004000 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK 0x00008000 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK 0x00010000 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK 0x00020000 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK 0x00040000 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK 0x00080000 +#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK 0xfff00000 + +#define CLIPPER_DEBUG_REG00_MASK \ + (CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK | \ + CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK | \ + CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) + +#define CLIPPER_DEBUG_REG00(clip_ga_bc_fifo_write, clip_ga_bc_fifo_full, clip_to_ga_fifo_write, clip_to_ga_fifo_full, primic_to_clprim_fifo_empty, primic_to_clprim_fifo_full, clip_to_outsm_fifo_empty, clip_to_outsm_fifo_full, vgt_to_clipp_fifo_empty, vgt_to_clipp_fifo_full, vgt_to_clips_fifo_empty, vgt_to_clips_fifo_full, clipcode_fifo_fifo_empty, clipcode_fifo_full, vte_out_clip_fifo_fifo_empty, vte_out_clip_fifo_fifo_full, vte_out_orig_fifo_fifo_empty, vte_out_orig_fifo_fifo_full, ccgen_to_clipcc_fifo_empty, ccgen_to_clipcc_fifo_full, always_zero) \ + ((clip_ga_bc_fifo_write << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT) | \ + (clip_ga_bc_fifo_full << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT) | \ + (clip_to_ga_fifo_write << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT) | \ + (clip_to_ga_fifo_full << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT) | \ + (primic_to_clprim_fifo_empty << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT) | \ + (primic_to_clprim_fifo_full << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT) | \ + (clip_to_outsm_fifo_empty << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT) | \ + (clip_to_outsm_fifo_full << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT) | \ + (vgt_to_clipp_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT) | \ + (vgt_to_clipp_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT) | \ + (vgt_to_clips_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT) | \ + (vgt_to_clips_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT) | \ + (clipcode_fifo_fifo_empty << CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT) | \ + (clipcode_fifo_full << CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT) | \ + (vte_out_clip_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT) | \ + (vte_out_clip_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT) | \ + (vte_out_orig_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT) | \ + (vte_out_orig_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT) | \ + (ccgen_to_clipcc_fifo_empty << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT) | \ + (ccgen_to_clipcc_fifo_full << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT) | \ + (always_zero << CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT)) + +#define CLIPPER_DEBUG_REG00_GET_clip_ga_bc_fifo_write(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK) >> CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_ga_bc_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_to_ga_fifo_write(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK) >> CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_to_ga_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_primic_to_clprim_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_primic_to_clprim_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_to_outsm_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_to_outsm_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vgt_to_clipp_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vgt_to_clipp_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vgt_to_clips_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vgt_to_clips_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clipcode_fifo_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clipcode_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vte_out_clip_fifo_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vte_out_clip_fifo_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vte_out_orig_fifo_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vte_out_orig_fifo_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_ccgen_to_clipcc_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_ccgen_to_clipcc_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_ALWAYS_ZERO(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT) + +#define CLIPPER_DEBUG_REG00_SET_clip_ga_bc_fifo_write(clipper_debug_reg00_reg, clip_ga_bc_fifo_write) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK) | (clip_ga_bc_fifo_write << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_ga_bc_fifo_full(clipper_debug_reg00_reg, clip_ga_bc_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK) | (clip_ga_bc_fifo_full << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_to_ga_fifo_write(clipper_debug_reg00_reg, clip_to_ga_fifo_write) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK) | (clip_to_ga_fifo_write << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_to_ga_fifo_full(clipper_debug_reg00_reg, clip_to_ga_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK) | (clip_to_ga_fifo_full << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_primic_to_clprim_fifo_empty(clipper_debug_reg00_reg, primic_to_clprim_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK) | (primic_to_clprim_fifo_empty << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_primic_to_clprim_fifo_full(clipper_debug_reg00_reg, primic_to_clprim_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK) | (primic_to_clprim_fifo_full << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_to_outsm_fifo_empty(clipper_debug_reg00_reg, clip_to_outsm_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK) | (clip_to_outsm_fifo_empty << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_to_outsm_fifo_full(clipper_debug_reg00_reg, clip_to_outsm_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK) | (clip_to_outsm_fifo_full << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vgt_to_clipp_fifo_empty(clipper_debug_reg00_reg, vgt_to_clipp_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK) | (vgt_to_clipp_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vgt_to_clipp_fifo_full(clipper_debug_reg00_reg, vgt_to_clipp_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK) | (vgt_to_clipp_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vgt_to_clips_fifo_empty(clipper_debug_reg00_reg, vgt_to_clips_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK) | (vgt_to_clips_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vgt_to_clips_fifo_full(clipper_debug_reg00_reg, vgt_to_clips_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK) | (vgt_to_clips_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clipcode_fifo_fifo_empty(clipper_debug_reg00_reg, clipcode_fifo_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK) | (clipcode_fifo_fifo_empty << CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clipcode_fifo_full(clipper_debug_reg00_reg, clipcode_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK) | (clipcode_fifo_full << CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vte_out_clip_fifo_fifo_empty(clipper_debug_reg00_reg, vte_out_clip_fifo_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK) | (vte_out_clip_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vte_out_clip_fifo_fifo_full(clipper_debug_reg00_reg, vte_out_clip_fifo_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK) | (vte_out_clip_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vte_out_orig_fifo_fifo_empty(clipper_debug_reg00_reg, vte_out_orig_fifo_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK) | (vte_out_orig_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vte_out_orig_fifo_fifo_full(clipper_debug_reg00_reg, vte_out_orig_fifo_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK) | (vte_out_orig_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_ccgen_to_clipcc_fifo_empty(clipper_debug_reg00_reg, ccgen_to_clipcc_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK) | (ccgen_to_clipcc_fifo_empty << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_ccgen_to_clipcc_fifo_full(clipper_debug_reg00_reg, ccgen_to_clipcc_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK) | (ccgen_to_clipcc_fifo_full << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_ALWAYS_ZERO(clipper_debug_reg00_reg, always_zero) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg00_t { + unsigned int clip_ga_bc_fifo_write : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE; + unsigned int clip_ga_bc_fifo_full : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE; + unsigned int clip_to_ga_fifo_write : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE; + unsigned int clip_to_ga_fifo_full : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE; + unsigned int primic_to_clprim_fifo_empty : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE; + unsigned int primic_to_clprim_fifo_full : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE; + unsigned int clip_to_outsm_fifo_empty : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE; + unsigned int clip_to_outsm_fifo_full : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE; + unsigned int vgt_to_clipp_fifo_empty : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE; + unsigned int vgt_to_clipp_fifo_full : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE; + unsigned int vgt_to_clips_fifo_empty : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE; + unsigned int vgt_to_clips_fifo_full : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE; + unsigned int clipcode_fifo_fifo_empty : CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE; + unsigned int clipcode_fifo_full : CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE; + unsigned int vte_out_clip_fifo_fifo_empty : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE; + unsigned int vte_out_clip_fifo_fifo_full : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE; + unsigned int vte_out_orig_fifo_fifo_empty : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE; + unsigned int vte_out_orig_fifo_fifo_full : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE; + unsigned int ccgen_to_clipcc_fifo_empty : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE; + unsigned int ccgen_to_clipcc_fifo_full : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE; + unsigned int always_zero : CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE; + } clipper_debug_reg00_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg00_t { + unsigned int always_zero : CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE; + unsigned int ccgen_to_clipcc_fifo_full : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE; + unsigned int ccgen_to_clipcc_fifo_empty : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE; + unsigned int vte_out_orig_fifo_fifo_full : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE; + unsigned int vte_out_orig_fifo_fifo_empty : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE; + unsigned int vte_out_clip_fifo_fifo_full : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE; + unsigned int vte_out_clip_fifo_fifo_empty : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE; + unsigned int clipcode_fifo_full : CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE; + unsigned int clipcode_fifo_fifo_empty : CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE; + unsigned int vgt_to_clips_fifo_full : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE; + unsigned int vgt_to_clips_fifo_empty : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE; + unsigned int vgt_to_clipp_fifo_full : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE; + unsigned int vgt_to_clipp_fifo_empty : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE; + unsigned int clip_to_outsm_fifo_full : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE; + unsigned int clip_to_outsm_fifo_empty : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE; + unsigned int primic_to_clprim_fifo_full : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE; + unsigned int primic_to_clprim_fifo_empty : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE; + unsigned int clip_to_ga_fifo_full : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE; + unsigned int clip_to_ga_fifo_write : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE; + unsigned int clip_ga_bc_fifo_full : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE; + unsigned int clip_ga_bc_fifo_write : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE; + } clipper_debug_reg00_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg00_t f; +} clipper_debug_reg00_u; + + +/* + * CLIPPER_DEBUG_REG01 struct + */ + +#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE 3 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE 4 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE 4 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE 4 +#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE 3 +#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE 2 +#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE 8 + +#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT 0 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT 2 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT 5 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT 6 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT 7 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT 11 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT 15 +#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT 19 +#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT 22 +#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT 24 + +#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK 0x00000001 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK 0x00000002 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK 0x0000001c +#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK 0x00000020 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK 0x00000040 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK 0x00000780 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK 0x00007800 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK 0x00078000 +#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK 0x00380000 +#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK 0x00c00000 +#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK 0xff000000 + +#define CLIPPER_DEBUG_REG01_MASK \ + (CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK | \ + CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK | \ + CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK | \ + CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) + +#define CLIPPER_DEBUG_REG01(clip_to_outsm_end_of_packet, clip_to_outsm_first_prim_of_slot, clip_to_outsm_deallocate_slot, clip_to_outsm_clipped_prim, clip_to_outsm_null_primitive, clip_to_outsm_vertex_store_indx_2, clip_to_outsm_vertex_store_indx_1, clip_to_outsm_vertex_store_indx_0, clip_vert_vte_valid, vte_out_clip_rd_vertex_store_indx, always_zero) \ + ((clip_to_outsm_end_of_packet << CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT) | \ + (clip_to_outsm_first_prim_of_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT) | \ + (clip_to_outsm_deallocate_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT) | \ + (clip_to_outsm_clipped_prim << CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT) | \ + (clip_to_outsm_null_primitive << CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT) | \ + (clip_to_outsm_vertex_store_indx_2 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT) | \ + (clip_to_outsm_vertex_store_indx_1 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT) | \ + (clip_to_outsm_vertex_store_indx_0 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT) | \ + (clip_vert_vte_valid << CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT) | \ + (vte_out_clip_rd_vertex_store_indx << CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT) | \ + (always_zero << CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT)) + +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_end_of_packet(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_first_prim_of_slot(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_deallocate_slot(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_clipped_prim(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_null_primitive(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_2(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_1(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_0(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_vert_vte_valid(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK) >> CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_vte_out_clip_rd_vertex_store_indx(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK) >> CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_ALWAYS_ZERO(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT) + +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_end_of_packet(clipper_debug_reg01_reg, clip_to_outsm_end_of_packet) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK) | (clip_to_outsm_end_of_packet << CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_first_prim_of_slot(clipper_debug_reg01_reg, clip_to_outsm_first_prim_of_slot) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK) | (clip_to_outsm_first_prim_of_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_deallocate_slot(clipper_debug_reg01_reg, clip_to_outsm_deallocate_slot) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK) | (clip_to_outsm_deallocate_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_clipped_prim(clipper_debug_reg01_reg, clip_to_outsm_clipped_prim) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK) | (clip_to_outsm_clipped_prim << CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_null_primitive(clipper_debug_reg01_reg, clip_to_outsm_null_primitive) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK) | (clip_to_outsm_null_primitive << CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_2(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_2) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK) | (clip_to_outsm_vertex_store_indx_2 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_1(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_1) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK) | (clip_to_outsm_vertex_store_indx_1 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_0(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_0) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK) | (clip_to_outsm_vertex_store_indx_0 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_vert_vte_valid(clipper_debug_reg01_reg, clip_vert_vte_valid) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK) | (clip_vert_vte_valid << CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_vte_out_clip_rd_vertex_store_indx(clipper_debug_reg01_reg, vte_out_clip_rd_vertex_store_indx) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK) | (vte_out_clip_rd_vertex_store_indx << CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_ALWAYS_ZERO(clipper_debug_reg01_reg, always_zero) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg01_t { + unsigned int clip_to_outsm_end_of_packet : CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE; + unsigned int clip_to_outsm_first_prim_of_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE; + unsigned int clip_to_outsm_deallocate_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE; + unsigned int clip_to_outsm_clipped_prim : CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE; + unsigned int clip_to_outsm_null_primitive : CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_2 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_1 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_0 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE; + unsigned int clip_vert_vte_valid : CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE; + unsigned int vte_out_clip_rd_vertex_store_indx : CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE; + unsigned int always_zero : CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE; + } clipper_debug_reg01_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg01_t { + unsigned int always_zero : CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE; + unsigned int vte_out_clip_rd_vertex_store_indx : CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE; + unsigned int clip_vert_vte_valid : CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_0 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_1 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_2 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE; + unsigned int clip_to_outsm_null_primitive : CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE; + unsigned int clip_to_outsm_clipped_prim : CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE; + unsigned int clip_to_outsm_deallocate_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE; + unsigned int clip_to_outsm_first_prim_of_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE; + unsigned int clip_to_outsm_end_of_packet : CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE; + } clipper_debug_reg01_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg01_t f; +} clipper_debug_reg01_u; + + +/* + * CLIPPER_DEBUG_REG02 struct + */ + +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE 21 +#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE 3 +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE 7 +#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE 1 + +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT 0 +#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT 21 +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT 24 +#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT 31 + +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK 0x001fffff +#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00e00000 +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK 0x7f000000 +#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000 + +#define CLIPPER_DEBUG_REG02_MASK \ + (CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK | \ + CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK | \ + CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) + +#define CLIPPER_DEBUG_REG02(always_zero1, clipsm0_clip_to_clipga_clip_to_outsm_cnt, always_zero0, clipsm0_clprim_to_clip_prim_valid) \ + ((always_zero1 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT) | \ + (clipsm0_clip_to_clipga_clip_to_outsm_cnt << CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT) | \ + (clipsm0_clprim_to_clip_prim_valid << CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT)) + +#define CLIPPER_DEBUG_REG02_GET_ALWAYS_ZERO1(clipper_debug_reg02) \ + ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG02_GET_clipsm0_clip_to_clipga_clip_to_outsm_cnt(clipper_debug_reg02) \ + ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK) >> CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT) +#define CLIPPER_DEBUG_REG02_GET_ALWAYS_ZERO0(clipper_debug_reg02) \ + ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG02_GET_clipsm0_clprim_to_clip_prim_valid(clipper_debug_reg02) \ + ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) >> CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT) + +#define CLIPPER_DEBUG_REG02_SET_ALWAYS_ZERO1(clipper_debug_reg02_reg, always_zero1) \ + clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG02_SET_clipsm0_clip_to_clipga_clip_to_outsm_cnt(clipper_debug_reg02_reg, clipsm0_clip_to_clipga_clip_to_outsm_cnt) \ + clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK) | (clipsm0_clip_to_clipga_clip_to_outsm_cnt << CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT) +#define CLIPPER_DEBUG_REG02_SET_ALWAYS_ZERO0(clipper_debug_reg02_reg, always_zero0) \ + clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG02_SET_clipsm0_clprim_to_clip_prim_valid(clipper_debug_reg02_reg, clipsm0_clprim_to_clip_prim_valid) \ + clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) | (clipsm0_clprim_to_clip_prim_valid << CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg02_t { + unsigned int always_zero1 : CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clprim_to_clip_prim_valid : CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE; + } clipper_debug_reg02_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg02_t { + unsigned int clipsm0_clprim_to_clip_prim_valid : CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE; + } clipper_debug_reg02_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg02_t f; +} clipper_debug_reg02_u; + + +/* + * CLIPPER_DEBUG_REG03 struct + */ + +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE 3 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE 1 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE 3 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE 1 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE 12 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE 6 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE 6 + +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT 0 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT 3 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT 4 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT 7 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT 8 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT 20 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT 26 + +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK 0x00000007 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK 0x00000008 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK 0x00000070 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK 0x00000080 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK 0x000fff00 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK 0x03f00000 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK 0xfc000000 + +#define CLIPPER_DEBUG_REG03_MASK \ + (CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK | \ + CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK | \ + CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK | \ + CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK | \ + CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG03(always_zero3, clipsm0_clprim_to_clip_clip_primitive, always_zero2, clipsm0_clprim_to_clip_null_primitive, always_zero1, clipsm0_clprim_to_clip_clip_code_or, always_zero0) \ + ((always_zero3 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT) | \ + (clipsm0_clprim_to_clip_clip_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT) | \ + (clipsm0_clprim_to_clip_null_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT) | \ + (clipsm0_clprim_to_clip_clip_code_or << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO3(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_clip_primitive(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO2(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_null_primitive(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO1(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_clip_code_or(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO0(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO3(clipper_debug_reg03_reg, always_zero3) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_clip_primitive(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_clip_primitive) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK) | (clipsm0_clprim_to_clip_clip_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO2(clipper_debug_reg03_reg, always_zero2) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_null_primitive(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_null_primitive) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK) | (clipsm0_clprim_to_clip_null_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO1(clipper_debug_reg03_reg, always_zero1) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_clip_code_or(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_clip_code_or) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK) | (clipsm0_clprim_to_clip_clip_code_or << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO0(clipper_debug_reg03_reg, always_zero0) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg03_t { + unsigned int always_zero3 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE; + unsigned int clipsm0_clprim_to_clip_clip_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_null_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_clip_code_or : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg03_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg03_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clprim_to_clip_clip_code_or : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_null_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_clip_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE; + } clipper_debug_reg03_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg03_t f; +} clipper_debug_reg03_u; + + +/* + * CLIPPER_DEBUG_REG04 struct + */ + +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE 3 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE 1 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE 3 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE 1 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE 24 + +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT 0 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT 3 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT 4 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT 7 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT 8 + +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK 0x00000007 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x00000008 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK 0x00000070 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK 0x00000080 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK 0xffffff00 + +#define CLIPPER_DEBUG_REG04_MASK \ + (CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK | \ + CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK | \ + CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG04(always_zero2, clipsm0_clprim_to_clip_first_prim_of_slot, always_zero1, clipsm0_clprim_to_clip_event, always_zero0) \ + ((always_zero2 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT) | \ + (clipsm0_clprim_to_clip_first_prim_of_slot << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT) | \ + (clipsm0_clprim_to_clip_event << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO2(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG04_GET_clipsm0_clprim_to_clip_first_prim_of_slot(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO1(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG04_GET_clipsm0_clprim_to_clip_event(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK) >> CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT) +#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO0(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO2(clipper_debug_reg04_reg, always_zero2) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG04_SET_clipsm0_clprim_to_clip_first_prim_of_slot(clipper_debug_reg04_reg, clipsm0_clprim_to_clip_first_prim_of_slot) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK) | (clipsm0_clprim_to_clip_first_prim_of_slot << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO1(clipper_debug_reg04_reg, always_zero1) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG04_SET_clipsm0_clprim_to_clip_event(clipper_debug_reg04_reg, clipsm0_clprim_to_clip_event) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK) | (clipsm0_clprim_to_clip_event << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT) +#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO0(clipper_debug_reg04_reg, always_zero0) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg04_t { + unsigned int always_zero2 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_event : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg04_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg04_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clprim_to_clip_event : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE; + } clipper_debug_reg04_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg04_t f; +} clipper_debug_reg04_u; + + +/* + * CLIPPER_DEBUG_REG05 struct + */ + +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE 1 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE 2 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE 3 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE 6 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE 4 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE 2 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE 4 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE 2 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE 4 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE 4 + +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT 0 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT 1 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT 3 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT 6 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT 12 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT 16 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT 18 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT 22 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT 24 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT 28 + +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK 0x00000001 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK 0x00000006 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK 0x00000038 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK 0x00000fc0 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0000f000 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK 0x00030000 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x003c0000 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK 0x00c00000 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x0f000000 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK 0xf0000000 + +#define CLIPPER_DEBUG_REG05_MASK \ + (CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK | \ + CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK | \ + CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK | \ + CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK | \ + CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG05(clipsm0_clprim_to_clip_state_var_indx, always_zero3, clipsm0_clprim_to_clip_deallocate_slot, clipsm0_clprim_to_clip_event_id, clipsm0_clprim_to_clip_vertex_store_indx_2, always_zero2, clipsm0_clprim_to_clip_vertex_store_indx_1, always_zero1, clipsm0_clprim_to_clip_vertex_store_indx_0, always_zero0) \ + ((clipsm0_clprim_to_clip_state_var_indx << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT) | \ + (always_zero3 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT) | \ + (clipsm0_clprim_to_clip_deallocate_slot << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT) | \ + (clipsm0_clprim_to_clip_event_id << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT) | \ + (clipsm0_clprim_to_clip_vertex_store_indx_2 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT) | \ + (clipsm0_clprim_to_clip_vertex_store_indx_1 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT) | \ + (clipsm0_clprim_to_clip_vertex_store_indx_0 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_state_var_indx(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO3(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_deallocate_slot(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_event_id(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_2(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO2(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_1(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO1(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_0(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO0(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_state_var_indx(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_state_var_indx) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK) | (clipsm0_clprim_to_clip_state_var_indx << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO3(clipper_debug_reg05_reg, always_zero3) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_deallocate_slot(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_deallocate_slot) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK) | (clipsm0_clprim_to_clip_deallocate_slot << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_event_id(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_event_id) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK) | (clipsm0_clprim_to_clip_event_id << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_2(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_2) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_2 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO2(clipper_debug_reg05_reg, always_zero2) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_1(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_1) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_1 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO1(clipper_debug_reg05_reg, always_zero1) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_0(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_0) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_0 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO0(clipper_debug_reg05_reg, always_zero0) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg05_t { + unsigned int clipsm0_clprim_to_clip_state_var_indx : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE; + unsigned int clipsm0_clprim_to_clip_deallocate_slot : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE; + unsigned int clipsm0_clprim_to_clip_event_id : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg05_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg05_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE; + unsigned int clipsm0_clprim_to_clip_event_id : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE; + unsigned int clipsm0_clprim_to_clip_deallocate_slot : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE; + unsigned int clipsm0_clprim_to_clip_state_var_indx : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE; + } clipper_debug_reg05_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg05_t f; +} clipper_debug_reg05_u; + + +/* + * CLIPPER_DEBUG_REG09 struct + */ + +#define CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE 1 +#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE 1 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE 4 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE 2 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE 4 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE 2 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE 4 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE 2 +#define CLIPPER_DEBUG_REG09_prim_back_valid_SIZE 1 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE 4 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE 2 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE 1 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE 2 + +#define CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT 0 +#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT 1 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT 2 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT 6 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT 8 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT 12 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT 14 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT 18 +#define CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT 20 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT 21 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT 25 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT 27 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT 28 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT 29 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT 30 + +#define CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK 0x00000001 +#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK 0x00000002 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK 0x0000003c +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK 0x000000c0 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK 0x00000f00 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK 0x00003000 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK 0x0003c000 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK 0x000c0000 +#define CLIPPER_DEBUG_REG09_prim_back_valid_MASK 0x00100000 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK 0x01e00000 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK 0x06000000 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK 0x08000000 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK 0x10000000 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK 0x20000000 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK 0xc0000000 + +#define CLIPPER_DEBUG_REG09_MASK \ + (CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK | \ + CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK | \ + CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK | \ + CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK | \ + CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK | \ + CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK | \ + CLIPPER_DEBUG_REG09_prim_back_valid_MASK | \ + CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK | \ + CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK | \ + CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK | \ + CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK | \ + CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) + +#define CLIPPER_DEBUG_REG09(clprim_in_back_event, outputclprimtoclip_null_primitive, clprim_in_back_vertex_store_indx_2, always_zero2, clprim_in_back_vertex_store_indx_1, always_zero1, clprim_in_back_vertex_store_indx_0, always_zero0, prim_back_valid, clip_priority_seq_indx_out_cnt, outsm_clr_rd_orig_vertices, outsm_clr_rd_clipsm_wait, outsm_clr_fifo_empty, outsm_clr_fifo_full, clip_priority_seq_indx_load) \ + ((clprim_in_back_event << CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT) | \ + (outputclprimtoclip_null_primitive << CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT) | \ + (clprim_in_back_vertex_store_indx_2 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT) | \ + (clprim_in_back_vertex_store_indx_1 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT) | \ + (clprim_in_back_vertex_store_indx_0 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT) | \ + (prim_back_valid << CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT) | \ + (clip_priority_seq_indx_out_cnt << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT) | \ + (outsm_clr_rd_orig_vertices << CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT) | \ + (outsm_clr_rd_clipsm_wait << CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT) | \ + (outsm_clr_fifo_empty << CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT) | \ + (outsm_clr_fifo_full << CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT) | \ + (clip_priority_seq_indx_load << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT)) + +#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_event(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outputclprimtoclip_null_primitive(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK) >> CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_2(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO2(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_1(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO1(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_0(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO0(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_prim_back_valid(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_prim_back_valid_MASK) >> CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clip_priority_seq_indx_out_cnt(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK) >> CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outsm_clr_rd_orig_vertices(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outsm_clr_rd_clipsm_wait(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outsm_clr_fifo_empty(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outsm_clr_fifo_full(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clip_priority_seq_indx_load(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) >> CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT) + +#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_event(clipper_debug_reg09_reg, clprim_in_back_event) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK) | (clprim_in_back_event << CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outputclprimtoclip_null_primitive(clipper_debug_reg09_reg, outputclprimtoclip_null_primitive) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK) | (outputclprimtoclip_null_primitive << CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_2(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_2) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK) | (clprim_in_back_vertex_store_indx_2 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO2(clipper_debug_reg09_reg, always_zero2) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_1(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_1) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK) | (clprim_in_back_vertex_store_indx_1 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO1(clipper_debug_reg09_reg, always_zero1) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_0(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_0) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK) | (clprim_in_back_vertex_store_indx_0 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO0(clipper_debug_reg09_reg, always_zero0) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_prim_back_valid(clipper_debug_reg09_reg, prim_back_valid) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_prim_back_valid_MASK) | (prim_back_valid << CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clip_priority_seq_indx_out_cnt(clipper_debug_reg09_reg, clip_priority_seq_indx_out_cnt) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK) | (clip_priority_seq_indx_out_cnt << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outsm_clr_rd_orig_vertices(clipper_debug_reg09_reg, outsm_clr_rd_orig_vertices) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK) | (outsm_clr_rd_orig_vertices << CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outsm_clr_rd_clipsm_wait(clipper_debug_reg09_reg, outsm_clr_rd_clipsm_wait) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK) | (outsm_clr_rd_clipsm_wait << CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outsm_clr_fifo_empty(clipper_debug_reg09_reg, outsm_clr_fifo_empty) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK) | (outsm_clr_fifo_empty << CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outsm_clr_fifo_full(clipper_debug_reg09_reg, outsm_clr_fifo_full) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK) | (outsm_clr_fifo_full << CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clip_priority_seq_indx_load(clipper_debug_reg09_reg, clip_priority_seq_indx_load) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) | (clip_priority_seq_indx_load << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg09_t { + unsigned int clprim_in_back_event : CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE; + unsigned int outputclprimtoclip_null_primitive : CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE; + unsigned int clprim_in_back_vertex_store_indx_2 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE; + unsigned int clprim_in_back_vertex_store_indx_1 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE; + unsigned int clprim_in_back_vertex_store_indx_0 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE; + unsigned int prim_back_valid : CLIPPER_DEBUG_REG09_prim_back_valid_SIZE; + unsigned int clip_priority_seq_indx_out_cnt : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE; + unsigned int outsm_clr_rd_orig_vertices : CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE; + unsigned int outsm_clr_rd_clipsm_wait : CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE; + unsigned int outsm_clr_fifo_empty : CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE; + unsigned int outsm_clr_fifo_full : CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE; + unsigned int clip_priority_seq_indx_load : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE; + } clipper_debug_reg09_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg09_t { + unsigned int clip_priority_seq_indx_load : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE; + unsigned int outsm_clr_fifo_full : CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE; + unsigned int outsm_clr_fifo_empty : CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE; + unsigned int outsm_clr_rd_clipsm_wait : CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE; + unsigned int outsm_clr_rd_orig_vertices : CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE; + unsigned int clip_priority_seq_indx_out_cnt : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE; + unsigned int prim_back_valid : CLIPPER_DEBUG_REG09_prim_back_valid_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE; + unsigned int clprim_in_back_vertex_store_indx_0 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE; + unsigned int clprim_in_back_vertex_store_indx_1 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE; + unsigned int clprim_in_back_vertex_store_indx_2 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE; + unsigned int outputclprimtoclip_null_primitive : CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE; + unsigned int clprim_in_back_event : CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE; + } clipper_debug_reg09_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg09_t f; +} clipper_debug_reg09_u; + + +/* + * CLIPPER_DEBUG_REG10 struct + */ + +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE 4 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE 2 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE 4 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE 2 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE 4 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE 2 +#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE 1 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE 2 +#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE 1 +#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE 1 +#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE 3 +#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE 6 + +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT 0 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT 4 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT 6 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT 10 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT 12 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT 16 +#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT 18 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT 19 +#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT 21 +#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT 22 +#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT 23 +#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT 26 + +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x0000000f +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK 0x00000030 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x000003c0 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK 0x00000c00 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x0000f000 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK 0x00030000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK 0x00040000 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK 0x00180000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK 0x00200000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK 0x00400000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK 0x03800000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK 0xfc000000 + +#define CLIPPER_DEBUG_REG10_MASK \ + (CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK | \ + CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK | \ + CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK | \ + CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK | \ + CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK | \ + CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) + +#define CLIPPER_DEBUG_REG10(primic_to_clprim_fifo_vertex_store_indx_2, always_zero3, primic_to_clprim_fifo_vertex_store_indx_1, always_zero2, primic_to_clprim_fifo_vertex_store_indx_0, always_zero1, clprim_in_back_state_var_indx, always_zero0, clprim_in_back_end_of_packet, clprim_in_back_first_prim_of_slot, clprim_in_back_deallocate_slot, clprim_in_back_event_id) \ + ((primic_to_clprim_fifo_vertex_store_indx_2 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT) | \ + (always_zero3 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT) | \ + (primic_to_clprim_fifo_vertex_store_indx_1 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT) | \ + (primic_to_clprim_fifo_vertex_store_indx_0 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT) | \ + (clprim_in_back_state_var_indx << CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT) | \ + (clprim_in_back_end_of_packet << CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT) | \ + (clprim_in_back_first_prim_of_slot << CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT) | \ + (clprim_in_back_deallocate_slot << CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT) | \ + (clprim_in_back_event_id << CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT)) + +#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_2(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO3(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_1(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO2(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_0(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO1(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_state_var_indx(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO0(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_end_of_packet(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_first_prim_of_slot(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_deallocate_slot(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_event_id(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT) + +#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_2(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_2) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK) | (primic_to_clprim_fifo_vertex_store_indx_2 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO3(clipper_debug_reg10_reg, always_zero3) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_1(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_1) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK) | (primic_to_clprim_fifo_vertex_store_indx_1 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO2(clipper_debug_reg10_reg, always_zero2) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_0(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_0) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK) | (primic_to_clprim_fifo_vertex_store_indx_0 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO1(clipper_debug_reg10_reg, always_zero1) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_state_var_indx(clipper_debug_reg10_reg, clprim_in_back_state_var_indx) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK) | (clprim_in_back_state_var_indx << CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO0(clipper_debug_reg10_reg, always_zero0) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_end_of_packet(clipper_debug_reg10_reg, clprim_in_back_end_of_packet) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK) | (clprim_in_back_end_of_packet << CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_first_prim_of_slot(clipper_debug_reg10_reg, clprim_in_back_first_prim_of_slot) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK) | (clprim_in_back_first_prim_of_slot << CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_deallocate_slot(clipper_debug_reg10_reg, clprim_in_back_deallocate_slot) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK) | (clprim_in_back_deallocate_slot << CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_event_id(clipper_debug_reg10_reg, clprim_in_back_event_id) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) | (clprim_in_back_event_id << CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg10_t { + unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE; + unsigned int clprim_in_back_state_var_indx : CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE; + unsigned int clprim_in_back_end_of_packet : CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE; + unsigned int clprim_in_back_first_prim_of_slot : CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE; + unsigned int clprim_in_back_deallocate_slot : CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE; + unsigned int clprim_in_back_event_id : CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE; + } clipper_debug_reg10_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg10_t { + unsigned int clprim_in_back_event_id : CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE; + unsigned int clprim_in_back_deallocate_slot : CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE; + unsigned int clprim_in_back_first_prim_of_slot : CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE; + unsigned int clprim_in_back_end_of_packet : CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE; + unsigned int clprim_in_back_state_var_indx : CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE; + } clipper_debug_reg10_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg10_t f; +} clipper_debug_reg10_u; + + +/* + * CLIPPER_DEBUG_REG11 struct + */ + +#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE 4 +#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE 28 + +#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT 0 +#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT 4 + +#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK 0x0000000f +#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK 0xfffffff0 + +#define CLIPPER_DEBUG_REG11_MASK \ + (CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK | \ + CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) + +#define CLIPPER_DEBUG_REG11(vertval_bits_vertex_vertex_store_msb, always_zero) \ + ((vertval_bits_vertex_vertex_store_msb << CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT) | \ + (always_zero << CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT)) + +#define CLIPPER_DEBUG_REG11_GET_vertval_bits_vertex_vertex_store_msb(clipper_debug_reg11) \ + ((clipper_debug_reg11 & CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK) >> CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT) +#define CLIPPER_DEBUG_REG11_GET_ALWAYS_ZERO(clipper_debug_reg11) \ + ((clipper_debug_reg11 & CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT) + +#define CLIPPER_DEBUG_REG11_SET_vertval_bits_vertex_vertex_store_msb(clipper_debug_reg11_reg, vertval_bits_vertex_vertex_store_msb) \ + clipper_debug_reg11_reg = (clipper_debug_reg11_reg & ~CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK) | (vertval_bits_vertex_vertex_store_msb << CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT) +#define CLIPPER_DEBUG_REG11_SET_ALWAYS_ZERO(clipper_debug_reg11_reg, always_zero) \ + clipper_debug_reg11_reg = (clipper_debug_reg11_reg & ~CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg11_t { + unsigned int vertval_bits_vertex_vertex_store_msb : CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE; + unsigned int always_zero : CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE; + } clipper_debug_reg11_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg11_t { + unsigned int always_zero : CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE; + unsigned int vertval_bits_vertex_vertex_store_msb : CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE; + } clipper_debug_reg11_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg11_t f; +} clipper_debug_reg11_u; + + +/* + * CLIPPER_DEBUG_REG12 struct + */ + +#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE 2 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE 3 +#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE 5 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE 4 +#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE 4 +#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE 2 +#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE 1 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE 10 + +#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT 0 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT 2 +#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT 5 +#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT 6 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT 11 +#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT 15 +#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT 19 +#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT 21 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT 22 + +#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK 0x00000003 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK 0x0000001c +#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK 0x00000020 +#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK 0x000007c0 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK 0x00007800 +#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK 0x00078000 +#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK 0x00180000 +#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK 0x00200000 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK 0xffc00000 + +#define CLIPPER_DEBUG_REG12_MASK \ + (CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK | \ + CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK | \ + CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK | \ + CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK | \ + CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK | \ + CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG12(clip_priority_available_vte_out_clip, always_zero2, clip_vertex_fifo_empty, clip_priority_available_clip_verts, always_zero1, vertval_bits_vertex_cc_next_valid, clipcc_vertex_store_indx, primic_to_clprim_valid, always_zero0) \ + ((clip_priority_available_vte_out_clip << CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT) | \ + (clip_vertex_fifo_empty << CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT) | \ + (clip_priority_available_clip_verts << CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT) | \ + (vertval_bits_vertex_cc_next_valid << CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT) | \ + (clipcc_vertex_store_indx << CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT) | \ + (primic_to_clprim_valid << CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG12_GET_clip_priority_available_vte_out_clip(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK) >> CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO2(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_clip_vertex_fifo_empty(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK) >> CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_clip_priority_available_clip_verts(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK) >> CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO1(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_vertval_bits_vertex_cc_next_valid(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK) >> CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_clipcc_vertex_store_indx(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK) >> CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_primic_to_clprim_valid(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK) >> CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO0(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG12_SET_clip_priority_available_vte_out_clip(clipper_debug_reg12_reg, clip_priority_available_vte_out_clip) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK) | (clip_priority_available_vte_out_clip << CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO2(clipper_debug_reg12_reg, always_zero2) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_clip_vertex_fifo_empty(clipper_debug_reg12_reg, clip_vertex_fifo_empty) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK) | (clip_vertex_fifo_empty << CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_clip_priority_available_clip_verts(clipper_debug_reg12_reg, clip_priority_available_clip_verts) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK) | (clip_priority_available_clip_verts << CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO1(clipper_debug_reg12_reg, always_zero1) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_vertval_bits_vertex_cc_next_valid(clipper_debug_reg12_reg, vertval_bits_vertex_cc_next_valid) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK) | (vertval_bits_vertex_cc_next_valid << CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_clipcc_vertex_store_indx(clipper_debug_reg12_reg, clipcc_vertex_store_indx) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK) | (clipcc_vertex_store_indx << CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_primic_to_clprim_valid(clipper_debug_reg12_reg, primic_to_clprim_valid) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK) | (primic_to_clprim_valid << CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO0(clipper_debug_reg12_reg, always_zero0) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg12_t { + unsigned int clip_priority_available_vte_out_clip : CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE; + unsigned int clip_vertex_fifo_empty : CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE; + unsigned int clip_priority_available_clip_verts : CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE; + unsigned int vertval_bits_vertex_cc_next_valid : CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE; + unsigned int clipcc_vertex_store_indx : CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE; + unsigned int primic_to_clprim_valid : CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg12_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg12_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE; + unsigned int primic_to_clprim_valid : CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE; + unsigned int clipcc_vertex_store_indx : CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE; + unsigned int vertval_bits_vertex_cc_next_valid : CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE; + unsigned int clip_priority_available_clip_verts : CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE; + unsigned int clip_vertex_fifo_empty : CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE; + unsigned int clip_priority_available_vte_out_clip : CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE; + } clipper_debug_reg12_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg12_t f; +} clipper_debug_reg12_u; + + +/* + * CLIPPER_DEBUG_REG13 struct + */ + +#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE 4 +#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE 7 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE 3 +#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE 4 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE 1 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE 1 +#define CLIPPER_DEBUG_REG13_sm0_current_state_SIZE 7 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE 5 + +#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT 0 +#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT 4 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT 11 +#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT 14 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT 18 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT 19 +#define CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT 20 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT 27 + +#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK 0x0000000f +#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK 0x000007f0 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK 0x00003800 +#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK 0x0003c000 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK 0x00040000 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK 0x00080000 +#define CLIPPER_DEBUG_REG13_sm0_current_state_MASK 0x07f00000 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK 0xf8000000 + +#define CLIPPER_DEBUG_REG13_MASK \ + (CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK | \ + CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK | \ + CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK | \ + CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK | \ + CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK | \ + CLIPPER_DEBUG_REG13_sm0_current_state_MASK | \ + CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG13(sm0_clip_vert_cnt, sm0_prim_end_state, always_zero1, sm0_vertex_clip_cnt, sm0_inv_to_clip_data_valid_1, sm0_inv_to_clip_data_valid_0, sm0_current_state, always_zero0) \ + ((sm0_clip_vert_cnt << CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT) | \ + (sm0_prim_end_state << CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT) | \ + (sm0_vertex_clip_cnt << CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT) | \ + (sm0_inv_to_clip_data_valid_1 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT) | \ + (sm0_inv_to_clip_data_valid_0 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT) | \ + (sm0_current_state << CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG13_GET_sm0_clip_vert_cnt(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK) >> CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_prim_end_state(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK) >> CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_ALWAYS_ZERO1(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_vertex_clip_cnt(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK) >> CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_inv_to_clip_data_valid_1(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK) >> CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_inv_to_clip_data_valid_0(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK) >> CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_current_state(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_current_state_MASK) >> CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_ALWAYS_ZERO0(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG13_SET_sm0_clip_vert_cnt(clipper_debug_reg13_reg, sm0_clip_vert_cnt) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK) | (sm0_clip_vert_cnt << CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_prim_end_state(clipper_debug_reg13_reg, sm0_prim_end_state) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK) | (sm0_prim_end_state << CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_ALWAYS_ZERO1(clipper_debug_reg13_reg, always_zero1) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_vertex_clip_cnt(clipper_debug_reg13_reg, sm0_vertex_clip_cnt) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK) | (sm0_vertex_clip_cnt << CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_inv_to_clip_data_valid_1(clipper_debug_reg13_reg, sm0_inv_to_clip_data_valid_1) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK) | (sm0_inv_to_clip_data_valid_1 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_inv_to_clip_data_valid_0(clipper_debug_reg13_reg, sm0_inv_to_clip_data_valid_0) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK) | (sm0_inv_to_clip_data_valid_0 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_current_state(clipper_debug_reg13_reg, sm0_current_state) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_current_state_MASK) | (sm0_current_state << CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_ALWAYS_ZERO0(clipper_debug_reg13_reg, always_zero0) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg13_t { + unsigned int sm0_clip_vert_cnt : CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE; + unsigned int sm0_prim_end_state : CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE; + unsigned int sm0_vertex_clip_cnt : CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE; + unsigned int sm0_inv_to_clip_data_valid_1 : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE; + unsigned int sm0_inv_to_clip_data_valid_0 : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE; + unsigned int sm0_current_state : CLIPPER_DEBUG_REG13_sm0_current_state_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg13_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg13_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE; + unsigned int sm0_current_state : CLIPPER_DEBUG_REG13_sm0_current_state_SIZE; + unsigned int sm0_inv_to_clip_data_valid_0 : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE; + unsigned int sm0_inv_to_clip_data_valid_1 : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE; + unsigned int sm0_vertex_clip_cnt : CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE; + unsigned int sm0_prim_end_state : CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE; + unsigned int sm0_clip_vert_cnt : CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE; + } clipper_debug_reg13_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg13_t f; +} clipper_debug_reg13_u; + + +/* + * SXIFCCG_DEBUG_REG0 struct + */ + +#define SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE 4 +#define SXIFCCG_DEBUG_REG0_position_address_SIZE 3 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE 3 +#define SXIFCCG_DEBUG_REG0_point_address_SIZE 3 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE 3 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE 1 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE 2 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE 4 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE 7 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE 1 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE 1 + +#define SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT 0 +#define SXIFCCG_DEBUG_REG0_position_address_SHIFT 4 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT 7 +#define SXIFCCG_DEBUG_REG0_point_address_SHIFT 10 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT 13 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT 16 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT 17 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT 19 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT 23 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT 30 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT 31 + +#define SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK 0x0000000f +#define SXIFCCG_DEBUG_REG0_position_address_MASK 0x00000070 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK 0x00000380 +#define SXIFCCG_DEBUG_REG0_point_address_MASK 0x00001c00 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK 0x0000e000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK 0x00010000 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK 0x00060000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK 0x00780000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK 0x3f800000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK 0x40000000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK 0x80000000 + +#define SXIFCCG_DEBUG_REG0_MASK \ + (SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK | \ + SXIFCCG_DEBUG_REG0_position_address_MASK | \ + SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK | \ + SXIFCCG_DEBUG_REG0_point_address_MASK | \ + SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK | \ + SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) + +#define SXIFCCG_DEBUG_REG0(nan_kill_flag, position_address, always_zero2, point_address, always_zero1, sx_pending_rd_state_var_indx, always_zero0, sx_pending_rd_req_mask, sx_pending_rd_pci, sx_pending_rd_aux_inc, sx_pending_rd_aux_sel) \ + ((nan_kill_flag << SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT) | \ + (position_address << SXIFCCG_DEBUG_REG0_position_address_SHIFT) | \ + (always_zero2 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT) | \ + (point_address << SXIFCCG_DEBUG_REG0_point_address_SHIFT) | \ + (always_zero1 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT) | \ + (sx_pending_rd_state_var_indx << SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT) | \ + (always_zero0 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT) | \ + (sx_pending_rd_req_mask << SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT) | \ + (sx_pending_rd_pci << SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT) | \ + (sx_pending_rd_aux_inc << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT) | \ + (sx_pending_rd_aux_sel << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT)) + +#define SXIFCCG_DEBUG_REG0_GET_nan_kill_flag(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK) >> SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_position_address(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_position_address_MASK) >> SXIFCCG_DEBUG_REG0_position_address_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO2(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_point_address(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_point_address_MASK) >> SXIFCCG_DEBUG_REG0_point_address_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO1(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_state_var_indx(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO0(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_req_mask(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_pci(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_aux_inc(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_aux_sel(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT) + +#define SXIFCCG_DEBUG_REG0_SET_nan_kill_flag(sxifccg_debug_reg0_reg, nan_kill_flag) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK) | (nan_kill_flag << SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_position_address(sxifccg_debug_reg0_reg, position_address) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_position_address_MASK) | (position_address << SXIFCCG_DEBUG_REG0_position_address_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO2(sxifccg_debug_reg0_reg, always_zero2) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_point_address(sxifccg_debug_reg0_reg, point_address) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_point_address_MASK) | (point_address << SXIFCCG_DEBUG_REG0_point_address_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO1(sxifccg_debug_reg0_reg, always_zero1) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_state_var_indx(sxifccg_debug_reg0_reg, sx_pending_rd_state_var_indx) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK) | (sx_pending_rd_state_var_indx << SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO0(sxifccg_debug_reg0_reg, always_zero0) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_req_mask(sxifccg_debug_reg0_reg, sx_pending_rd_req_mask) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK) | (sx_pending_rd_req_mask << SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_pci(sxifccg_debug_reg0_reg, sx_pending_rd_pci) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK) | (sx_pending_rd_pci << SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_aux_inc(sxifccg_debug_reg0_reg, sx_pending_rd_aux_inc) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK) | (sx_pending_rd_aux_inc << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_aux_sel(sxifccg_debug_reg0_reg, sx_pending_rd_aux_sel) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) | (sx_pending_rd_aux_sel << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg0_t { + unsigned int nan_kill_flag : SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE; + unsigned int position_address : SXIFCCG_DEBUG_REG0_position_address_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE; + unsigned int point_address : SXIFCCG_DEBUG_REG0_point_address_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE; + unsigned int sx_pending_rd_state_var_indx : SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE; + unsigned int sx_pending_rd_req_mask : SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE; + unsigned int sx_pending_rd_pci : SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE; + unsigned int sx_pending_rd_aux_inc : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE; + unsigned int sx_pending_rd_aux_sel : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE; + } sxifccg_debug_reg0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg0_t { + unsigned int sx_pending_rd_aux_sel : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE; + unsigned int sx_pending_rd_aux_inc : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE; + unsigned int sx_pending_rd_pci : SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE; + unsigned int sx_pending_rd_req_mask : SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE; + unsigned int sx_pending_rd_state_var_indx : SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE; + unsigned int point_address : SXIFCCG_DEBUG_REG0_point_address_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE; + unsigned int position_address : SXIFCCG_DEBUG_REG0_position_address_SIZE; + unsigned int nan_kill_flag : SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE; + } sxifccg_debug_reg0_t; + +#endif + +typedef union { + unsigned int val : 32; + sxifccg_debug_reg0_t f; +} sxifccg_debug_reg0_u; + + +/* + * SXIFCCG_DEBUG_REG1 struct + */ + +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE 2 +#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE 2 +#define SXIFCCG_DEBUG_REG1_available_positions_SIZE 3 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE 4 +#define SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE 1 +#define SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE 3 +#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE 1 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE 4 +#define SXIFCCG_DEBUG_REG1_aux_sel_SIZE 1 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE 2 +#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE 2 +#define SXIFCCG_DEBUG_REG1_param_cache_base_SIZE 7 + +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT 0 +#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT 2 +#define SXIFCCG_DEBUG_REG1_available_positions_SHIFT 4 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT 7 +#define SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT 11 +#define SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT 12 +#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT 15 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT 16 +#define SXIFCCG_DEBUG_REG1_aux_sel_SHIFT 20 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT 21 +#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT 23 +#define SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT 25 + +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK 0x00000003 +#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK 0x0000000c +#define SXIFCCG_DEBUG_REG1_available_positions_MASK 0x00000070 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK 0x00000780 +#define SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK 0x00000800 +#define SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK 0x00007000 +#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK 0x00008000 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK 0x000f0000 +#define SXIFCCG_DEBUG_REG1_aux_sel_MASK 0x00100000 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK 0x00600000 +#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK 0x01800000 +#define SXIFCCG_DEBUG_REG1_param_cache_base_MASK 0xfe000000 + +#define SXIFCCG_DEBUG_REG1_MASK \ + (SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK | \ + SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK | \ + SXIFCCG_DEBUG_REG1_available_positions_MASK | \ + SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK | \ + SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK | \ + SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK | \ + SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK | \ + SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK | \ + SXIFCCG_DEBUG_REG1_aux_sel_MASK | \ + SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK | \ + SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK | \ + SXIFCCG_DEBUG_REG1_param_cache_base_MASK) + +#define SXIFCCG_DEBUG_REG1(always_zero3, sx_to_pa_empty, available_positions, always_zero2, sx_pending_advance, sx_receive_indx, statevar_bits_sxpa_aux_vector, always_zero1, aux_sel, always_zero0, pasx_req_cnt, param_cache_base) \ + ((always_zero3 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT) | \ + (sx_to_pa_empty << SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT) | \ + (available_positions << SXIFCCG_DEBUG_REG1_available_positions_SHIFT) | \ + (always_zero2 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT) | \ + (sx_pending_advance << SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT) | \ + (sx_receive_indx << SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT) | \ + (statevar_bits_sxpa_aux_vector << SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT) | \ + (always_zero1 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT) | \ + (aux_sel << SXIFCCG_DEBUG_REG1_aux_sel_SHIFT) | \ + (always_zero0 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT) | \ + (pasx_req_cnt << SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT) | \ + (param_cache_base << SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT)) + +#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO3(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_sx_to_pa_empty(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK) >> SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_available_positions(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_available_positions_MASK) >> SXIFCCG_DEBUG_REG1_available_positions_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO2(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_sx_pending_advance(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK) >> SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_sx_receive_indx(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK) >> SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_statevar_bits_sxpa_aux_vector(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK) >> SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO1(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_aux_sel(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_aux_sel_MASK) >> SXIFCCG_DEBUG_REG1_aux_sel_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO0(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_pasx_req_cnt(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK) >> SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_param_cache_base(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_param_cache_base_MASK) >> SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT) + +#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO3(sxifccg_debug_reg1_reg, always_zero3) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_sx_to_pa_empty(sxifccg_debug_reg1_reg, sx_to_pa_empty) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK) | (sx_to_pa_empty << SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_available_positions(sxifccg_debug_reg1_reg, available_positions) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_available_positions_MASK) | (available_positions << SXIFCCG_DEBUG_REG1_available_positions_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO2(sxifccg_debug_reg1_reg, always_zero2) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_sx_pending_advance(sxifccg_debug_reg1_reg, sx_pending_advance) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK) | (sx_pending_advance << SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_sx_receive_indx(sxifccg_debug_reg1_reg, sx_receive_indx) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK) | (sx_receive_indx << SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_statevar_bits_sxpa_aux_vector(sxifccg_debug_reg1_reg, statevar_bits_sxpa_aux_vector) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK) | (statevar_bits_sxpa_aux_vector << SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO1(sxifccg_debug_reg1_reg, always_zero1) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_aux_sel(sxifccg_debug_reg1_reg, aux_sel) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_aux_sel_MASK) | (aux_sel << SXIFCCG_DEBUG_REG1_aux_sel_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO0(sxifccg_debug_reg1_reg, always_zero0) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_pasx_req_cnt(sxifccg_debug_reg1_reg, pasx_req_cnt) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK) | (pasx_req_cnt << SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_param_cache_base(sxifccg_debug_reg1_reg, param_cache_base) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_param_cache_base_MASK) | (param_cache_base << SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg1_t { + unsigned int always_zero3 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE; + unsigned int sx_to_pa_empty : SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE; + unsigned int available_positions : SXIFCCG_DEBUG_REG1_available_positions_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE; + unsigned int sx_pending_advance : SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE; + unsigned int sx_receive_indx : SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE; + unsigned int statevar_bits_sxpa_aux_vector : SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE; + unsigned int aux_sel : SXIFCCG_DEBUG_REG1_aux_sel_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE; + unsigned int pasx_req_cnt : SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE; + unsigned int param_cache_base : SXIFCCG_DEBUG_REG1_param_cache_base_SIZE; + } sxifccg_debug_reg1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg1_t { + unsigned int param_cache_base : SXIFCCG_DEBUG_REG1_param_cache_base_SIZE; + unsigned int pasx_req_cnt : SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE; + unsigned int aux_sel : SXIFCCG_DEBUG_REG1_aux_sel_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE; + unsigned int statevar_bits_sxpa_aux_vector : SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE; + unsigned int sx_receive_indx : SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE; + unsigned int sx_pending_advance : SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE; + unsigned int available_positions : SXIFCCG_DEBUG_REG1_available_positions_SIZE; + unsigned int sx_to_pa_empty : SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE; + } sxifccg_debug_reg1_t; + +#endif + +typedef union { + unsigned int val : 32; + sxifccg_debug_reg1_t f; +} sxifccg_debug_reg1_u; + + +/* + * SXIFCCG_DEBUG_REG2 struct + */ + +#define SXIFCCG_DEBUG_REG2_sx_sent_SIZE 1 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_aux_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE 6 +#define SXIFCCG_DEBUG_REG2_req_active_verts_SIZE 7 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE 1 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE 1 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE 2 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE 2 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE 4 +#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE 3 + +#define SXIFCCG_DEBUG_REG2_sx_sent_SHIFT 0 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT 1 +#define SXIFCCG_DEBUG_REG2_sx_aux_SHIFT 2 +#define SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT 3 +#define SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT 9 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT 16 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT 17 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT 18 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT 20 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT 22 +#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT 26 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT 27 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT 28 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT 29 + +#define SXIFCCG_DEBUG_REG2_sx_sent_MASK 0x00000001 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK 0x00000002 +#define SXIFCCG_DEBUG_REG2_sx_aux_MASK 0x00000004 +#define SXIFCCG_DEBUG_REG2_sx_request_indx_MASK 0x000001f8 +#define SXIFCCG_DEBUG_REG2_req_active_verts_MASK 0x0000fe00 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK 0x00010000 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK 0x00020000 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK 0x000c0000 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK 0x00300000 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK 0x03c00000 +#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK 0x04000000 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK 0x08000000 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK 0x10000000 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK 0xe0000000 + +#define SXIFCCG_DEBUG_REG2_MASK \ + (SXIFCCG_DEBUG_REG2_sx_sent_MASK | \ + SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK | \ + SXIFCCG_DEBUG_REG2_sx_aux_MASK | \ + SXIFCCG_DEBUG_REG2_sx_request_indx_MASK | \ + SXIFCCG_DEBUG_REG2_req_active_verts_MASK | \ + SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK | \ + SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK | \ + SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK | \ + SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK | \ + SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK | \ + SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK | \ + SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK | \ + SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK | \ + SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) + +#define SXIFCCG_DEBUG_REG2(sx_sent, always_zero3, sx_aux, sx_request_indx, req_active_verts, always_zero2, vgt_to_ccgen_state_var_indx, always_zero1, vgt_to_ccgen_active_verts, always_zero0, req_active_verts_loaded, sx_pending_fifo_empty, sx_pending_fifo_full, sx_pending_fifo_contents) \ + ((sx_sent << SXIFCCG_DEBUG_REG2_sx_sent_SHIFT) | \ + (always_zero3 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT) | \ + (sx_aux << SXIFCCG_DEBUG_REG2_sx_aux_SHIFT) | \ + (sx_request_indx << SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT) | \ + (req_active_verts << SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT) | \ + (always_zero2 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT) | \ + (vgt_to_ccgen_state_var_indx << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT) | \ + (always_zero1 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT) | \ + (vgt_to_ccgen_active_verts << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT) | \ + (always_zero0 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT) | \ + (req_active_verts_loaded << SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT) | \ + (sx_pending_fifo_empty << SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT) | \ + (sx_pending_fifo_full << SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT) | \ + (sx_pending_fifo_contents << SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT)) + +#define SXIFCCG_DEBUG_REG2_GET_sx_sent(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_sent_MASK) >> SXIFCCG_DEBUG_REG2_sx_sent_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO3(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_aux(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_aux_MASK) >> SXIFCCG_DEBUG_REG2_sx_aux_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_request_indx(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_request_indx_MASK) >> SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_req_active_verts(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_req_active_verts_MASK) >> SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO2(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_vgt_to_ccgen_state_var_indx(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK) >> SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO1(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_vgt_to_ccgen_active_verts(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK) >> SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO0(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_req_active_verts_loaded(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK) >> SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_empty(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_full(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_contents(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT) + +#define SXIFCCG_DEBUG_REG2_SET_sx_sent(sxifccg_debug_reg2_reg, sx_sent) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_sent_MASK) | (sx_sent << SXIFCCG_DEBUG_REG2_sx_sent_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO3(sxifccg_debug_reg2_reg, always_zero3) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_aux(sxifccg_debug_reg2_reg, sx_aux) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_aux_MASK) | (sx_aux << SXIFCCG_DEBUG_REG2_sx_aux_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_request_indx(sxifccg_debug_reg2_reg, sx_request_indx) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_request_indx_MASK) | (sx_request_indx << SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_req_active_verts(sxifccg_debug_reg2_reg, req_active_verts) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_req_active_verts_MASK) | (req_active_verts << SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO2(sxifccg_debug_reg2_reg, always_zero2) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_vgt_to_ccgen_state_var_indx(sxifccg_debug_reg2_reg, vgt_to_ccgen_state_var_indx) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK) | (vgt_to_ccgen_state_var_indx << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO1(sxifccg_debug_reg2_reg, always_zero1) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_vgt_to_ccgen_active_verts(sxifccg_debug_reg2_reg, vgt_to_ccgen_active_verts) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK) | (vgt_to_ccgen_active_verts << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO0(sxifccg_debug_reg2_reg, always_zero0) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_req_active_verts_loaded(sxifccg_debug_reg2_reg, req_active_verts_loaded) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK) | (req_active_verts_loaded << SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_empty(sxifccg_debug_reg2_reg, sx_pending_fifo_empty) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK) | (sx_pending_fifo_empty << SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_full(sxifccg_debug_reg2_reg, sx_pending_fifo_full) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK) | (sx_pending_fifo_full << SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_contents(sxifccg_debug_reg2_reg, sx_pending_fifo_contents) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) | (sx_pending_fifo_contents << SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg2_t { + unsigned int sx_sent : SXIFCCG_DEBUG_REG2_sx_sent_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE; + unsigned int sx_aux : SXIFCCG_DEBUG_REG2_sx_aux_SIZE; + unsigned int sx_request_indx : SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE; + unsigned int req_active_verts : SXIFCCG_DEBUG_REG2_req_active_verts_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE; + unsigned int vgt_to_ccgen_state_var_indx : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE; + unsigned int vgt_to_ccgen_active_verts : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE; + unsigned int req_active_verts_loaded : SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE; + unsigned int sx_pending_fifo_empty : SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE; + unsigned int sx_pending_fifo_full : SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE; + unsigned int sx_pending_fifo_contents : SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE; + } sxifccg_debug_reg2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg2_t { + unsigned int sx_pending_fifo_contents : SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE; + unsigned int sx_pending_fifo_full : SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE; + unsigned int sx_pending_fifo_empty : SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE; + unsigned int req_active_verts_loaded : SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE; + unsigned int vgt_to_ccgen_active_verts : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE; + unsigned int vgt_to_ccgen_state_var_indx : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE; + unsigned int req_active_verts : SXIFCCG_DEBUG_REG2_req_active_verts_SIZE; + unsigned int sx_request_indx : SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE; + unsigned int sx_aux : SXIFCCG_DEBUG_REG2_sx_aux_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE; + unsigned int sx_sent : SXIFCCG_DEBUG_REG2_sx_sent_SIZE; + } sxifccg_debug_reg2_t; + +#endif + +typedef union { + unsigned int val : 32; + sxifccg_debug_reg2_t f; +} sxifccg_debug_reg2_u; + + +/* + * SXIFCCG_DEBUG_REG3 struct + */ + +#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE 4 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE 1 +#define SXIFCCG_DEBUG_REG3_available_positions_SIZE 3 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE 4 +#define SXIFCCG_DEBUG_REG3_current_state_SIZE 2 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE 1 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE 1 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE 2 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE 1 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE 1 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE 1 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE 1 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE 10 + +#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT 0 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT 4 +#define SXIFCCG_DEBUG_REG3_available_positions_SHIFT 5 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT 8 +#define SXIFCCG_DEBUG_REG3_current_state_SHIFT 12 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT 14 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT 15 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT 16 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT 18 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT 19 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT 20 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT 21 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT 22 + +#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK 0x0000000f +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK 0x00000010 +#define SXIFCCG_DEBUG_REG3_available_positions_MASK 0x000000e0 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK 0x00000f00 +#define SXIFCCG_DEBUG_REG3_current_state_MASK 0x00003000 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK 0x00004000 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK 0x00008000 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK 0x00030000 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK 0x00040000 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK 0x00080000 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK 0x00100000 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK 0x00200000 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK 0xffc00000 + +#define SXIFCCG_DEBUG_REG3_MASK \ + (SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK | \ + SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK | \ + SXIFCCG_DEBUG_REG3_available_positions_MASK | \ + SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK | \ + SXIFCCG_DEBUG_REG3_current_state_MASK | \ + SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK | \ + SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK | \ + SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK | \ + SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK | \ + SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK | \ + SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK | \ + SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK | \ + SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) + +#define SXIFCCG_DEBUG_REG3(vertex_fifo_entriesavailable, always_zero3, available_positions, always_zero2, current_state, vertex_fifo_empty, vertex_fifo_full, always_zero1, sx0_receive_fifo_empty, sx0_receive_fifo_full, vgt_to_ccgen_fifo_empty, vgt_to_ccgen_fifo_full, always_zero0) \ + ((vertex_fifo_entriesavailable << SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT) | \ + (always_zero3 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT) | \ + (available_positions << SXIFCCG_DEBUG_REG3_available_positions_SHIFT) | \ + (always_zero2 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT) | \ + (current_state << SXIFCCG_DEBUG_REG3_current_state_SHIFT) | \ + (vertex_fifo_empty << SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT) | \ + (vertex_fifo_full << SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT) | \ + (always_zero1 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT) | \ + (sx0_receive_fifo_empty << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT) | \ + (sx0_receive_fifo_full << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT) | \ + (vgt_to_ccgen_fifo_empty << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT) | \ + (vgt_to_ccgen_fifo_full << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT) | \ + (always_zero0 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT)) + +#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_entriesavailable(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO3(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_available_positions(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_available_positions_MASK) >> SXIFCCG_DEBUG_REG3_available_positions_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO2(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_current_state(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_current_state_MASK) >> SXIFCCG_DEBUG_REG3_current_state_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_empty(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_full(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO1(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_sx0_receive_fifo_empty(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_sx0_receive_fifo_full(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_vgt_to_ccgen_fifo_empty(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_vgt_to_ccgen_fifo_full(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO0(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT) + +#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_entriesavailable(sxifccg_debug_reg3_reg, vertex_fifo_entriesavailable) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK) | (vertex_fifo_entriesavailable << SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO3(sxifccg_debug_reg3_reg, always_zero3) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_available_positions(sxifccg_debug_reg3_reg, available_positions) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_available_positions_MASK) | (available_positions << SXIFCCG_DEBUG_REG3_available_positions_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO2(sxifccg_debug_reg3_reg, always_zero2) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_current_state(sxifccg_debug_reg3_reg, current_state) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_current_state_MASK) | (current_state << SXIFCCG_DEBUG_REG3_current_state_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_empty(sxifccg_debug_reg3_reg, vertex_fifo_empty) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK) | (vertex_fifo_empty << SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_full(sxifccg_debug_reg3_reg, vertex_fifo_full) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK) | (vertex_fifo_full << SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO1(sxifccg_debug_reg3_reg, always_zero1) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_sx0_receive_fifo_empty(sxifccg_debug_reg3_reg, sx0_receive_fifo_empty) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK) | (sx0_receive_fifo_empty << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_sx0_receive_fifo_full(sxifccg_debug_reg3_reg, sx0_receive_fifo_full) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK) | (sx0_receive_fifo_full << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_vgt_to_ccgen_fifo_empty(sxifccg_debug_reg3_reg, vgt_to_ccgen_fifo_empty) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK) | (vgt_to_ccgen_fifo_empty << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_vgt_to_ccgen_fifo_full(sxifccg_debug_reg3_reg, vgt_to_ccgen_fifo_full) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK) | (vgt_to_ccgen_fifo_full << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO0(sxifccg_debug_reg3_reg, always_zero0) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg3_t { + unsigned int vertex_fifo_entriesavailable : SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE; + unsigned int available_positions : SXIFCCG_DEBUG_REG3_available_positions_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE; + unsigned int current_state : SXIFCCG_DEBUG_REG3_current_state_SIZE; + unsigned int vertex_fifo_empty : SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE; + unsigned int vertex_fifo_full : SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE; + unsigned int sx0_receive_fifo_empty : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE; + unsigned int sx0_receive_fifo_full : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE; + unsigned int vgt_to_ccgen_fifo_empty : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE; + unsigned int vgt_to_ccgen_fifo_full : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE; + } sxifccg_debug_reg3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg3_t { + unsigned int always_zero0 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE; + unsigned int vgt_to_ccgen_fifo_full : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE; + unsigned int vgt_to_ccgen_fifo_empty : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE; + unsigned int sx0_receive_fifo_full : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE; + unsigned int sx0_receive_fifo_empty : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE; + unsigned int vertex_fifo_full : SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE; + unsigned int vertex_fifo_empty : SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE; + unsigned int current_state : SXIFCCG_DEBUG_REG3_current_state_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE; + unsigned int available_positions : SXIFCCG_DEBUG_REG3_available_positions_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE; + unsigned int vertex_fifo_entriesavailable : SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE; + } sxifccg_debug_reg3_t; + +#endif + +typedef union { + unsigned int val : 32; + sxifccg_debug_reg3_t f; +} sxifccg_debug_reg3_u; + + +/* + * SETUP_DEBUG_REG0 struct + */ + +#define SETUP_DEBUG_REG0_su_cntl_state_SIZE 5 +#define SETUP_DEBUG_REG0_pmode_state_SIZE 6 +#define SETUP_DEBUG_REG0_ge_stallb_SIZE 1 +#define SETUP_DEBUG_REG0_geom_enable_SIZE 1 +#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE 1 +#define SETUP_DEBUG_REG0_su_clip_rtr_SIZE 1 +#define SETUP_DEBUG_REG0_pfifo_busy_SIZE 1 +#define SETUP_DEBUG_REG0_su_cntl_busy_SIZE 1 +#define SETUP_DEBUG_REG0_geom_busy_SIZE 1 + +#define SETUP_DEBUG_REG0_su_cntl_state_SHIFT 0 +#define SETUP_DEBUG_REG0_pmode_state_SHIFT 5 +#define SETUP_DEBUG_REG0_ge_stallb_SHIFT 11 +#define SETUP_DEBUG_REG0_geom_enable_SHIFT 12 +#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT 13 +#define SETUP_DEBUG_REG0_su_clip_rtr_SHIFT 14 +#define SETUP_DEBUG_REG0_pfifo_busy_SHIFT 15 +#define SETUP_DEBUG_REG0_su_cntl_busy_SHIFT 16 +#define SETUP_DEBUG_REG0_geom_busy_SHIFT 17 + +#define SETUP_DEBUG_REG0_su_cntl_state_MASK 0x0000001f +#define SETUP_DEBUG_REG0_pmode_state_MASK 0x000007e0 +#define SETUP_DEBUG_REG0_ge_stallb_MASK 0x00000800 +#define SETUP_DEBUG_REG0_geom_enable_MASK 0x00001000 +#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK 0x00002000 +#define SETUP_DEBUG_REG0_su_clip_rtr_MASK 0x00004000 +#define SETUP_DEBUG_REG0_pfifo_busy_MASK 0x00008000 +#define SETUP_DEBUG_REG0_su_cntl_busy_MASK 0x00010000 +#define SETUP_DEBUG_REG0_geom_busy_MASK 0x00020000 + +#define SETUP_DEBUG_REG0_MASK \ + (SETUP_DEBUG_REG0_su_cntl_state_MASK | \ + SETUP_DEBUG_REG0_pmode_state_MASK | \ + SETUP_DEBUG_REG0_ge_stallb_MASK | \ + SETUP_DEBUG_REG0_geom_enable_MASK | \ + SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK | \ + SETUP_DEBUG_REG0_su_clip_rtr_MASK | \ + SETUP_DEBUG_REG0_pfifo_busy_MASK | \ + SETUP_DEBUG_REG0_su_cntl_busy_MASK | \ + SETUP_DEBUG_REG0_geom_busy_MASK) + +#define SETUP_DEBUG_REG0(su_cntl_state, pmode_state, ge_stallb, geom_enable, su_clip_baryc_rtr, su_clip_rtr, pfifo_busy, su_cntl_busy, geom_busy) \ + ((su_cntl_state << SETUP_DEBUG_REG0_su_cntl_state_SHIFT) | \ + (pmode_state << SETUP_DEBUG_REG0_pmode_state_SHIFT) | \ + (ge_stallb << SETUP_DEBUG_REG0_ge_stallb_SHIFT) | \ + (geom_enable << SETUP_DEBUG_REG0_geom_enable_SHIFT) | \ + (su_clip_baryc_rtr << SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT) | \ + (su_clip_rtr << SETUP_DEBUG_REG0_su_clip_rtr_SHIFT) | \ + (pfifo_busy << SETUP_DEBUG_REG0_pfifo_busy_SHIFT) | \ + (su_cntl_busy << SETUP_DEBUG_REG0_su_cntl_busy_SHIFT) | \ + (geom_busy << SETUP_DEBUG_REG0_geom_busy_SHIFT)) + +#define SETUP_DEBUG_REG0_GET_su_cntl_state(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_cntl_state_MASK) >> SETUP_DEBUG_REG0_su_cntl_state_SHIFT) +#define SETUP_DEBUG_REG0_GET_pmode_state(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_pmode_state_MASK) >> SETUP_DEBUG_REG0_pmode_state_SHIFT) +#define SETUP_DEBUG_REG0_GET_ge_stallb(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_ge_stallb_MASK) >> SETUP_DEBUG_REG0_ge_stallb_SHIFT) +#define SETUP_DEBUG_REG0_GET_geom_enable(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_geom_enable_MASK) >> SETUP_DEBUG_REG0_geom_enable_SHIFT) +#define SETUP_DEBUG_REG0_GET_su_clip_baryc_rtr(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK) >> SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT) +#define SETUP_DEBUG_REG0_GET_su_clip_rtr(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_clip_rtr_MASK) >> SETUP_DEBUG_REG0_su_clip_rtr_SHIFT) +#define SETUP_DEBUG_REG0_GET_pfifo_busy(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_pfifo_busy_MASK) >> SETUP_DEBUG_REG0_pfifo_busy_SHIFT) +#define SETUP_DEBUG_REG0_GET_su_cntl_busy(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_cntl_busy_MASK) >> SETUP_DEBUG_REG0_su_cntl_busy_SHIFT) +#define SETUP_DEBUG_REG0_GET_geom_busy(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_geom_busy_MASK) >> SETUP_DEBUG_REG0_geom_busy_SHIFT) + +#define SETUP_DEBUG_REG0_SET_su_cntl_state(setup_debug_reg0_reg, su_cntl_state) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_cntl_state_MASK) | (su_cntl_state << SETUP_DEBUG_REG0_su_cntl_state_SHIFT) +#define SETUP_DEBUG_REG0_SET_pmode_state(setup_debug_reg0_reg, pmode_state) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_pmode_state_MASK) | (pmode_state << SETUP_DEBUG_REG0_pmode_state_SHIFT) +#define SETUP_DEBUG_REG0_SET_ge_stallb(setup_debug_reg0_reg, ge_stallb) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_ge_stallb_MASK) | (ge_stallb << SETUP_DEBUG_REG0_ge_stallb_SHIFT) +#define SETUP_DEBUG_REG0_SET_geom_enable(setup_debug_reg0_reg, geom_enable) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_geom_enable_MASK) | (geom_enable << SETUP_DEBUG_REG0_geom_enable_SHIFT) +#define SETUP_DEBUG_REG0_SET_su_clip_baryc_rtr(setup_debug_reg0_reg, su_clip_baryc_rtr) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK) | (su_clip_baryc_rtr << SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT) +#define SETUP_DEBUG_REG0_SET_su_clip_rtr(setup_debug_reg0_reg, su_clip_rtr) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_clip_rtr_MASK) | (su_clip_rtr << SETUP_DEBUG_REG0_su_clip_rtr_SHIFT) +#define SETUP_DEBUG_REG0_SET_pfifo_busy(setup_debug_reg0_reg, pfifo_busy) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_pfifo_busy_MASK) | (pfifo_busy << SETUP_DEBUG_REG0_pfifo_busy_SHIFT) +#define SETUP_DEBUG_REG0_SET_su_cntl_busy(setup_debug_reg0_reg, su_cntl_busy) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_cntl_busy_MASK) | (su_cntl_busy << SETUP_DEBUG_REG0_su_cntl_busy_SHIFT) +#define SETUP_DEBUG_REG0_SET_geom_busy(setup_debug_reg0_reg, geom_busy) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_geom_busy_MASK) | (geom_busy << SETUP_DEBUG_REG0_geom_busy_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg0_t { + unsigned int su_cntl_state : SETUP_DEBUG_REG0_su_cntl_state_SIZE; + unsigned int pmode_state : SETUP_DEBUG_REG0_pmode_state_SIZE; + unsigned int ge_stallb : SETUP_DEBUG_REG0_ge_stallb_SIZE; + unsigned int geom_enable : SETUP_DEBUG_REG0_geom_enable_SIZE; + unsigned int su_clip_baryc_rtr : SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE; + unsigned int su_clip_rtr : SETUP_DEBUG_REG0_su_clip_rtr_SIZE; + unsigned int pfifo_busy : SETUP_DEBUG_REG0_pfifo_busy_SIZE; + unsigned int su_cntl_busy : SETUP_DEBUG_REG0_su_cntl_busy_SIZE; + unsigned int geom_busy : SETUP_DEBUG_REG0_geom_busy_SIZE; + unsigned int : 14; + } setup_debug_reg0_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg0_t { + unsigned int : 14; + unsigned int geom_busy : SETUP_DEBUG_REG0_geom_busy_SIZE; + unsigned int su_cntl_busy : SETUP_DEBUG_REG0_su_cntl_busy_SIZE; + unsigned int pfifo_busy : SETUP_DEBUG_REG0_pfifo_busy_SIZE; + unsigned int su_clip_rtr : SETUP_DEBUG_REG0_su_clip_rtr_SIZE; + unsigned int su_clip_baryc_rtr : SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE; + unsigned int geom_enable : SETUP_DEBUG_REG0_geom_enable_SIZE; + unsigned int ge_stallb : SETUP_DEBUG_REG0_ge_stallb_SIZE; + unsigned int pmode_state : SETUP_DEBUG_REG0_pmode_state_SIZE; + unsigned int su_cntl_state : SETUP_DEBUG_REG0_su_cntl_state_SIZE; + } setup_debug_reg0_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg0_t f; +} setup_debug_reg0_u; + + +/* + * SETUP_DEBUG_REG1 struct + */ + +#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE 14 +#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE 14 + +#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT 0 +#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT 14 + +#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK 0x00003fff +#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK 0x0fffc000 + +#define SETUP_DEBUG_REG1_MASK \ + (SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK | \ + SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) + +#define SETUP_DEBUG_REG1(y_sort0_gated_17_4, x_sort0_gated_17_4) \ + ((y_sort0_gated_17_4 << SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT) | \ + (x_sort0_gated_17_4 << SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT)) + +#define SETUP_DEBUG_REG1_GET_y_sort0_gated_17_4(setup_debug_reg1) \ + ((setup_debug_reg1 & SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK) >> SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG1_GET_x_sort0_gated_17_4(setup_debug_reg1) \ + ((setup_debug_reg1 & SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) >> SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT) + +#define SETUP_DEBUG_REG1_SET_y_sort0_gated_17_4(setup_debug_reg1_reg, y_sort0_gated_17_4) \ + setup_debug_reg1_reg = (setup_debug_reg1_reg & ~SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK) | (y_sort0_gated_17_4 << SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG1_SET_x_sort0_gated_17_4(setup_debug_reg1_reg, x_sort0_gated_17_4) \ + setup_debug_reg1_reg = (setup_debug_reg1_reg & ~SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) | (x_sort0_gated_17_4 << SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg1_t { + unsigned int y_sort0_gated_17_4 : SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE; + unsigned int x_sort0_gated_17_4 : SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE; + unsigned int : 4; + } setup_debug_reg1_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg1_t { + unsigned int : 4; + unsigned int x_sort0_gated_17_4 : SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE; + unsigned int y_sort0_gated_17_4 : SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE; + } setup_debug_reg1_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg1_t f; +} setup_debug_reg1_u; + + +/* + * SETUP_DEBUG_REG2 struct + */ + +#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE 14 +#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE 14 + +#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT 0 +#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT 14 + +#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK 0x00003fff +#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK 0x0fffc000 + +#define SETUP_DEBUG_REG2_MASK \ + (SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK | \ + SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) + +#define SETUP_DEBUG_REG2(y_sort1_gated_17_4, x_sort1_gated_17_4) \ + ((y_sort1_gated_17_4 << SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT) | \ + (x_sort1_gated_17_4 << SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT)) + +#define SETUP_DEBUG_REG2_GET_y_sort1_gated_17_4(setup_debug_reg2) \ + ((setup_debug_reg2 & SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK) >> SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG2_GET_x_sort1_gated_17_4(setup_debug_reg2) \ + ((setup_debug_reg2 & SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) >> SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT) + +#define SETUP_DEBUG_REG2_SET_y_sort1_gated_17_4(setup_debug_reg2_reg, y_sort1_gated_17_4) \ + setup_debug_reg2_reg = (setup_debug_reg2_reg & ~SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK) | (y_sort1_gated_17_4 << SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG2_SET_x_sort1_gated_17_4(setup_debug_reg2_reg, x_sort1_gated_17_4) \ + setup_debug_reg2_reg = (setup_debug_reg2_reg & ~SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) | (x_sort1_gated_17_4 << SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg2_t { + unsigned int y_sort1_gated_17_4 : SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE; + unsigned int x_sort1_gated_17_4 : SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE; + unsigned int : 4; + } setup_debug_reg2_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg2_t { + unsigned int : 4; + unsigned int x_sort1_gated_17_4 : SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE; + unsigned int y_sort1_gated_17_4 : SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE; + } setup_debug_reg2_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg2_t f; +} setup_debug_reg2_u; + + +/* + * SETUP_DEBUG_REG3 struct + */ + +#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE 14 +#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE 14 + +#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT 0 +#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT 14 + +#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK 0x00003fff +#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK 0x0fffc000 + +#define SETUP_DEBUG_REG3_MASK \ + (SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK | \ + SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) + +#define SETUP_DEBUG_REG3(y_sort2_gated_17_4, x_sort2_gated_17_4) \ + ((y_sort2_gated_17_4 << SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT) | \ + (x_sort2_gated_17_4 << SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT)) + +#define SETUP_DEBUG_REG3_GET_y_sort2_gated_17_4(setup_debug_reg3) \ + ((setup_debug_reg3 & SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK) >> SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG3_GET_x_sort2_gated_17_4(setup_debug_reg3) \ + ((setup_debug_reg3 & SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) >> SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT) + +#define SETUP_DEBUG_REG3_SET_y_sort2_gated_17_4(setup_debug_reg3_reg, y_sort2_gated_17_4) \ + setup_debug_reg3_reg = (setup_debug_reg3_reg & ~SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK) | (y_sort2_gated_17_4 << SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG3_SET_x_sort2_gated_17_4(setup_debug_reg3_reg, x_sort2_gated_17_4) \ + setup_debug_reg3_reg = (setup_debug_reg3_reg & ~SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) | (x_sort2_gated_17_4 << SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg3_t { + unsigned int y_sort2_gated_17_4 : SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE; + unsigned int x_sort2_gated_17_4 : SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE; + unsigned int : 4; + } setup_debug_reg3_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg3_t { + unsigned int : 4; + unsigned int x_sort2_gated_17_4 : SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE; + unsigned int y_sort2_gated_17_4 : SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE; + } setup_debug_reg3_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg3_t f; +} setup_debug_reg3_u; + + +/* + * SETUP_DEBUG_REG4 struct + */ + +#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE 11 +#define SETUP_DEBUG_REG4_null_prim_gated_SIZE 1 +#define SETUP_DEBUG_REG4_backfacing_gated_SIZE 1 +#define SETUP_DEBUG_REG4_st_indx_gated_SIZE 3 +#define SETUP_DEBUG_REG4_clipped_gated_SIZE 1 +#define SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE 3 +#define SETUP_DEBUG_REG4_xmajor_gated_SIZE 1 +#define SETUP_DEBUG_REG4_diamond_rule_gated_SIZE 2 +#define SETUP_DEBUG_REG4_type_gated_SIZE 3 +#define SETUP_DEBUG_REG4_fpov_gated_SIZE 1 +#define SETUP_DEBUG_REG4_pmode_prim_gated_SIZE 1 +#define SETUP_DEBUG_REG4_event_gated_SIZE 1 +#define SETUP_DEBUG_REG4_eop_gated_SIZE 1 + +#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT 0 +#define SETUP_DEBUG_REG4_null_prim_gated_SHIFT 11 +#define SETUP_DEBUG_REG4_backfacing_gated_SHIFT 12 +#define SETUP_DEBUG_REG4_st_indx_gated_SHIFT 13 +#define SETUP_DEBUG_REG4_clipped_gated_SHIFT 16 +#define SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT 17 +#define SETUP_DEBUG_REG4_xmajor_gated_SHIFT 20 +#define SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT 21 +#define SETUP_DEBUG_REG4_type_gated_SHIFT 23 +#define SETUP_DEBUG_REG4_fpov_gated_SHIFT 26 +#define SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT 27 +#define SETUP_DEBUG_REG4_event_gated_SHIFT 28 +#define SETUP_DEBUG_REG4_eop_gated_SHIFT 29 + +#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK 0x000007ff +#define SETUP_DEBUG_REG4_null_prim_gated_MASK 0x00000800 +#define SETUP_DEBUG_REG4_backfacing_gated_MASK 0x00001000 +#define SETUP_DEBUG_REG4_st_indx_gated_MASK 0x0000e000 +#define SETUP_DEBUG_REG4_clipped_gated_MASK 0x00010000 +#define SETUP_DEBUG_REG4_dealloc_slot_gated_MASK 0x000e0000 +#define SETUP_DEBUG_REG4_xmajor_gated_MASK 0x00100000 +#define SETUP_DEBUG_REG4_diamond_rule_gated_MASK 0x00600000 +#define SETUP_DEBUG_REG4_type_gated_MASK 0x03800000 +#define SETUP_DEBUG_REG4_fpov_gated_MASK 0x04000000 +#define SETUP_DEBUG_REG4_pmode_prim_gated_MASK 0x08000000 +#define SETUP_DEBUG_REG4_event_gated_MASK 0x10000000 +#define SETUP_DEBUG_REG4_eop_gated_MASK 0x20000000 + +#define SETUP_DEBUG_REG4_MASK \ + (SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK | \ + SETUP_DEBUG_REG4_null_prim_gated_MASK | \ + SETUP_DEBUG_REG4_backfacing_gated_MASK | \ + SETUP_DEBUG_REG4_st_indx_gated_MASK | \ + SETUP_DEBUG_REG4_clipped_gated_MASK | \ + SETUP_DEBUG_REG4_dealloc_slot_gated_MASK | \ + SETUP_DEBUG_REG4_xmajor_gated_MASK | \ + SETUP_DEBUG_REG4_diamond_rule_gated_MASK | \ + SETUP_DEBUG_REG4_type_gated_MASK | \ + SETUP_DEBUG_REG4_fpov_gated_MASK | \ + SETUP_DEBUG_REG4_pmode_prim_gated_MASK | \ + SETUP_DEBUG_REG4_event_gated_MASK | \ + SETUP_DEBUG_REG4_eop_gated_MASK) + +#define SETUP_DEBUG_REG4(attr_indx_sort0_gated, null_prim_gated, backfacing_gated, st_indx_gated, clipped_gated, dealloc_slot_gated, xmajor_gated, diamond_rule_gated, type_gated, fpov_gated, pmode_prim_gated, event_gated, eop_gated) \ + ((attr_indx_sort0_gated << SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT) | \ + (null_prim_gated << SETUP_DEBUG_REG4_null_prim_gated_SHIFT) | \ + (backfacing_gated << SETUP_DEBUG_REG4_backfacing_gated_SHIFT) | \ + (st_indx_gated << SETUP_DEBUG_REG4_st_indx_gated_SHIFT) | \ + (clipped_gated << SETUP_DEBUG_REG4_clipped_gated_SHIFT) | \ + (dealloc_slot_gated << SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT) | \ + (xmajor_gated << SETUP_DEBUG_REG4_xmajor_gated_SHIFT) | \ + (diamond_rule_gated << SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT) | \ + (type_gated << SETUP_DEBUG_REG4_type_gated_SHIFT) | \ + (fpov_gated << SETUP_DEBUG_REG4_fpov_gated_SHIFT) | \ + (pmode_prim_gated << SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT) | \ + (event_gated << SETUP_DEBUG_REG4_event_gated_SHIFT) | \ + (eop_gated << SETUP_DEBUG_REG4_eop_gated_SHIFT)) + +#define SETUP_DEBUG_REG4_GET_attr_indx_sort0_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK) >> SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_null_prim_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_null_prim_gated_MASK) >> SETUP_DEBUG_REG4_null_prim_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_backfacing_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_backfacing_gated_MASK) >> SETUP_DEBUG_REG4_backfacing_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_st_indx_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_st_indx_gated_MASK) >> SETUP_DEBUG_REG4_st_indx_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_clipped_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_clipped_gated_MASK) >> SETUP_DEBUG_REG4_clipped_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_dealloc_slot_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_dealloc_slot_gated_MASK) >> SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_xmajor_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_xmajor_gated_MASK) >> SETUP_DEBUG_REG4_xmajor_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_diamond_rule_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_diamond_rule_gated_MASK) >> SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_type_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_type_gated_MASK) >> SETUP_DEBUG_REG4_type_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_fpov_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_fpov_gated_MASK) >> SETUP_DEBUG_REG4_fpov_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_pmode_prim_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_pmode_prim_gated_MASK) >> SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_event_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_event_gated_MASK) >> SETUP_DEBUG_REG4_event_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_eop_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_eop_gated_MASK) >> SETUP_DEBUG_REG4_eop_gated_SHIFT) + +#define SETUP_DEBUG_REG4_SET_attr_indx_sort0_gated(setup_debug_reg4_reg, attr_indx_sort0_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK) | (attr_indx_sort0_gated << SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_null_prim_gated(setup_debug_reg4_reg, null_prim_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_null_prim_gated_MASK) | (null_prim_gated << SETUP_DEBUG_REG4_null_prim_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_backfacing_gated(setup_debug_reg4_reg, backfacing_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_backfacing_gated_MASK) | (backfacing_gated << SETUP_DEBUG_REG4_backfacing_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_st_indx_gated(setup_debug_reg4_reg, st_indx_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_st_indx_gated_MASK) | (st_indx_gated << SETUP_DEBUG_REG4_st_indx_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_clipped_gated(setup_debug_reg4_reg, clipped_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_clipped_gated_MASK) | (clipped_gated << SETUP_DEBUG_REG4_clipped_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_dealloc_slot_gated(setup_debug_reg4_reg, dealloc_slot_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_dealloc_slot_gated_MASK) | (dealloc_slot_gated << SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_xmajor_gated(setup_debug_reg4_reg, xmajor_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_xmajor_gated_MASK) | (xmajor_gated << SETUP_DEBUG_REG4_xmajor_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_diamond_rule_gated(setup_debug_reg4_reg, diamond_rule_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_diamond_rule_gated_MASK) | (diamond_rule_gated << SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_type_gated(setup_debug_reg4_reg, type_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_type_gated_MASK) | (type_gated << SETUP_DEBUG_REG4_type_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_fpov_gated(setup_debug_reg4_reg, fpov_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_fpov_gated_MASK) | (fpov_gated << SETUP_DEBUG_REG4_fpov_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_pmode_prim_gated(setup_debug_reg4_reg, pmode_prim_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_pmode_prim_gated_MASK) | (pmode_prim_gated << SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_event_gated(setup_debug_reg4_reg, event_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_event_gated_MASK) | (event_gated << SETUP_DEBUG_REG4_event_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_eop_gated(setup_debug_reg4_reg, eop_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_eop_gated_MASK) | (eop_gated << SETUP_DEBUG_REG4_eop_gated_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg4_t { + unsigned int attr_indx_sort0_gated : SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE; + unsigned int null_prim_gated : SETUP_DEBUG_REG4_null_prim_gated_SIZE; + unsigned int backfacing_gated : SETUP_DEBUG_REG4_backfacing_gated_SIZE; + unsigned int st_indx_gated : SETUP_DEBUG_REG4_st_indx_gated_SIZE; + unsigned int clipped_gated : SETUP_DEBUG_REG4_clipped_gated_SIZE; + unsigned int dealloc_slot_gated : SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE; + unsigned int xmajor_gated : SETUP_DEBUG_REG4_xmajor_gated_SIZE; + unsigned int diamond_rule_gated : SETUP_DEBUG_REG4_diamond_rule_gated_SIZE; + unsigned int type_gated : SETUP_DEBUG_REG4_type_gated_SIZE; + unsigned int fpov_gated : SETUP_DEBUG_REG4_fpov_gated_SIZE; + unsigned int pmode_prim_gated : SETUP_DEBUG_REG4_pmode_prim_gated_SIZE; + unsigned int event_gated : SETUP_DEBUG_REG4_event_gated_SIZE; + unsigned int eop_gated : SETUP_DEBUG_REG4_eop_gated_SIZE; + unsigned int : 2; + } setup_debug_reg4_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg4_t { + unsigned int : 2; + unsigned int eop_gated : SETUP_DEBUG_REG4_eop_gated_SIZE; + unsigned int event_gated : SETUP_DEBUG_REG4_event_gated_SIZE; + unsigned int pmode_prim_gated : SETUP_DEBUG_REG4_pmode_prim_gated_SIZE; + unsigned int fpov_gated : SETUP_DEBUG_REG4_fpov_gated_SIZE; + unsigned int type_gated : SETUP_DEBUG_REG4_type_gated_SIZE; + unsigned int diamond_rule_gated : SETUP_DEBUG_REG4_diamond_rule_gated_SIZE; + unsigned int xmajor_gated : SETUP_DEBUG_REG4_xmajor_gated_SIZE; + unsigned int dealloc_slot_gated : SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE; + unsigned int clipped_gated : SETUP_DEBUG_REG4_clipped_gated_SIZE; + unsigned int st_indx_gated : SETUP_DEBUG_REG4_st_indx_gated_SIZE; + unsigned int backfacing_gated : SETUP_DEBUG_REG4_backfacing_gated_SIZE; + unsigned int null_prim_gated : SETUP_DEBUG_REG4_null_prim_gated_SIZE; + unsigned int attr_indx_sort0_gated : SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE; + } setup_debug_reg4_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg4_t f; +} setup_debug_reg4_u; + + +/* + * SETUP_DEBUG_REG5 struct + */ + +#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE 11 +#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE 11 +#define SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE 2 +#define SETUP_DEBUG_REG5_event_id_gated_SIZE 5 + +#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT 0 +#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT 11 +#define SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT 22 +#define SETUP_DEBUG_REG5_event_id_gated_SHIFT 24 + +#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK 0x000007ff +#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK 0x003ff800 +#define SETUP_DEBUG_REG5_provoking_vtx_gated_MASK 0x00c00000 +#define SETUP_DEBUG_REG5_event_id_gated_MASK 0x1f000000 + +#define SETUP_DEBUG_REG5_MASK \ + (SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK | \ + SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK | \ + SETUP_DEBUG_REG5_provoking_vtx_gated_MASK | \ + SETUP_DEBUG_REG5_event_id_gated_MASK) + +#define SETUP_DEBUG_REG5(attr_indx_sort2_gated, attr_indx_sort1_gated, provoking_vtx_gated, event_id_gated) \ + ((attr_indx_sort2_gated << SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT) | \ + (attr_indx_sort1_gated << SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT) | \ + (provoking_vtx_gated << SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT) | \ + (event_id_gated << SETUP_DEBUG_REG5_event_id_gated_SHIFT)) + +#define SETUP_DEBUG_REG5_GET_attr_indx_sort2_gated(setup_debug_reg5) \ + ((setup_debug_reg5 & SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK) >> SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT) +#define SETUP_DEBUG_REG5_GET_attr_indx_sort1_gated(setup_debug_reg5) \ + ((setup_debug_reg5 & SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK) >> SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT) +#define SETUP_DEBUG_REG5_GET_provoking_vtx_gated(setup_debug_reg5) \ + ((setup_debug_reg5 & SETUP_DEBUG_REG5_provoking_vtx_gated_MASK) >> SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT) +#define SETUP_DEBUG_REG5_GET_event_id_gated(setup_debug_reg5) \ + ((setup_debug_reg5 & SETUP_DEBUG_REG5_event_id_gated_MASK) >> SETUP_DEBUG_REG5_event_id_gated_SHIFT) + +#define SETUP_DEBUG_REG5_SET_attr_indx_sort2_gated(setup_debug_reg5_reg, attr_indx_sort2_gated) \ + setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK) | (attr_indx_sort2_gated << SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT) +#define SETUP_DEBUG_REG5_SET_attr_indx_sort1_gated(setup_debug_reg5_reg, attr_indx_sort1_gated) \ + setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK) | (attr_indx_sort1_gated << SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT) +#define SETUP_DEBUG_REG5_SET_provoking_vtx_gated(setup_debug_reg5_reg, provoking_vtx_gated) \ + setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_provoking_vtx_gated_MASK) | (provoking_vtx_gated << SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT) +#define SETUP_DEBUG_REG5_SET_event_id_gated(setup_debug_reg5_reg, event_id_gated) \ + setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_event_id_gated_MASK) | (event_id_gated << SETUP_DEBUG_REG5_event_id_gated_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg5_t { + unsigned int attr_indx_sort2_gated : SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE; + unsigned int attr_indx_sort1_gated : SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE; + unsigned int provoking_vtx_gated : SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE; + unsigned int event_id_gated : SETUP_DEBUG_REG5_event_id_gated_SIZE; + unsigned int : 3; + } setup_debug_reg5_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg5_t { + unsigned int : 3; + unsigned int event_id_gated : SETUP_DEBUG_REG5_event_id_gated_SIZE; + unsigned int provoking_vtx_gated : SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE; + unsigned int attr_indx_sort1_gated : SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE; + unsigned int attr_indx_sort2_gated : SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE; + } setup_debug_reg5_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg5_t f; +} setup_debug_reg5_u; + + +/* + * PA_SC_DEBUG_CNTL struct + */ + +#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE 5 + +#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT 0 + +#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK 0x0000001f + +#define PA_SC_DEBUG_CNTL_MASK \ + (PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) + +#define PA_SC_DEBUG_CNTL(sc_debug_indx) \ + ((sc_debug_indx << PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT)) + +#define PA_SC_DEBUG_CNTL_GET_SC_DEBUG_INDX(pa_sc_debug_cntl) \ + ((pa_sc_debug_cntl & PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) >> PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT) + +#define PA_SC_DEBUG_CNTL_SET_SC_DEBUG_INDX(pa_sc_debug_cntl_reg, sc_debug_indx) \ + pa_sc_debug_cntl_reg = (pa_sc_debug_cntl_reg & ~PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) | (sc_debug_indx << PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_debug_cntl_t { + unsigned int sc_debug_indx : PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE; + unsigned int : 27; + } pa_sc_debug_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_debug_cntl_t { + unsigned int : 27; + unsigned int sc_debug_indx : PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE; + } pa_sc_debug_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_debug_cntl_t f; +} pa_sc_debug_cntl_u; + + +/* + * PA_SC_DEBUG_DATA struct + */ + +#define PA_SC_DEBUG_DATA_DATA_SIZE 32 + +#define PA_SC_DEBUG_DATA_DATA_SHIFT 0 + +#define PA_SC_DEBUG_DATA_DATA_MASK 0xffffffff + +#define PA_SC_DEBUG_DATA_MASK \ + (PA_SC_DEBUG_DATA_DATA_MASK) + +#define PA_SC_DEBUG_DATA(data) \ + ((data << PA_SC_DEBUG_DATA_DATA_SHIFT)) + +#define PA_SC_DEBUG_DATA_GET_DATA(pa_sc_debug_data) \ + ((pa_sc_debug_data & PA_SC_DEBUG_DATA_DATA_MASK) >> PA_SC_DEBUG_DATA_DATA_SHIFT) + +#define PA_SC_DEBUG_DATA_SET_DATA(pa_sc_debug_data_reg, data) \ + pa_sc_debug_data_reg = (pa_sc_debug_data_reg & ~PA_SC_DEBUG_DATA_DATA_MASK) | (data << PA_SC_DEBUG_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_debug_data_t { + unsigned int data : PA_SC_DEBUG_DATA_DATA_SIZE; + } pa_sc_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_debug_data_t { + unsigned int data : PA_SC_DEBUG_DATA_DATA_SIZE; + } pa_sc_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_debug_data_t f; +} pa_sc_debug_data_u; + + +/* + * SC_DEBUG_0 struct + */ + +#define SC_DEBUG_0_pa_freeze_b1_SIZE 1 +#define SC_DEBUG_0_pa_sc_valid_SIZE 1 +#define SC_DEBUG_0_pa_sc_phase_SIZE 3 +#define SC_DEBUG_0_cntx_cnt_SIZE 7 +#define SC_DEBUG_0_decr_cntx_cnt_SIZE 1 +#define SC_DEBUG_0_incr_cntx_cnt_SIZE 1 +#define SC_DEBUG_0_trigger_SIZE 1 + +#define SC_DEBUG_0_pa_freeze_b1_SHIFT 0 +#define SC_DEBUG_0_pa_sc_valid_SHIFT 1 +#define SC_DEBUG_0_pa_sc_phase_SHIFT 2 +#define SC_DEBUG_0_cntx_cnt_SHIFT 5 +#define SC_DEBUG_0_decr_cntx_cnt_SHIFT 12 +#define SC_DEBUG_0_incr_cntx_cnt_SHIFT 13 +#define SC_DEBUG_0_trigger_SHIFT 31 + +#define SC_DEBUG_0_pa_freeze_b1_MASK 0x00000001 +#define SC_DEBUG_0_pa_sc_valid_MASK 0x00000002 +#define SC_DEBUG_0_pa_sc_phase_MASK 0x0000001c +#define SC_DEBUG_0_cntx_cnt_MASK 0x00000fe0 +#define SC_DEBUG_0_decr_cntx_cnt_MASK 0x00001000 +#define SC_DEBUG_0_incr_cntx_cnt_MASK 0x00002000 +#define SC_DEBUG_0_trigger_MASK 0x80000000 + +#define SC_DEBUG_0_MASK \ + (SC_DEBUG_0_pa_freeze_b1_MASK | \ + SC_DEBUG_0_pa_sc_valid_MASK | \ + SC_DEBUG_0_pa_sc_phase_MASK | \ + SC_DEBUG_0_cntx_cnt_MASK | \ + SC_DEBUG_0_decr_cntx_cnt_MASK | \ + SC_DEBUG_0_incr_cntx_cnt_MASK | \ + SC_DEBUG_0_trigger_MASK) + +#define SC_DEBUG_0(pa_freeze_b1, pa_sc_valid, pa_sc_phase, cntx_cnt, decr_cntx_cnt, incr_cntx_cnt, trigger) \ + ((pa_freeze_b1 << SC_DEBUG_0_pa_freeze_b1_SHIFT) | \ + (pa_sc_valid << SC_DEBUG_0_pa_sc_valid_SHIFT) | \ + (pa_sc_phase << SC_DEBUG_0_pa_sc_phase_SHIFT) | \ + (cntx_cnt << SC_DEBUG_0_cntx_cnt_SHIFT) | \ + (decr_cntx_cnt << SC_DEBUG_0_decr_cntx_cnt_SHIFT) | \ + (incr_cntx_cnt << SC_DEBUG_0_incr_cntx_cnt_SHIFT) | \ + (trigger << SC_DEBUG_0_trigger_SHIFT)) + +#define SC_DEBUG_0_GET_pa_freeze_b1(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_pa_freeze_b1_MASK) >> SC_DEBUG_0_pa_freeze_b1_SHIFT) +#define SC_DEBUG_0_GET_pa_sc_valid(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_pa_sc_valid_MASK) >> SC_DEBUG_0_pa_sc_valid_SHIFT) +#define SC_DEBUG_0_GET_pa_sc_phase(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_pa_sc_phase_MASK) >> SC_DEBUG_0_pa_sc_phase_SHIFT) +#define SC_DEBUG_0_GET_cntx_cnt(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_cntx_cnt_MASK) >> SC_DEBUG_0_cntx_cnt_SHIFT) +#define SC_DEBUG_0_GET_decr_cntx_cnt(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_decr_cntx_cnt_MASK) >> SC_DEBUG_0_decr_cntx_cnt_SHIFT) +#define SC_DEBUG_0_GET_incr_cntx_cnt(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_incr_cntx_cnt_MASK) >> SC_DEBUG_0_incr_cntx_cnt_SHIFT) +#define SC_DEBUG_0_GET_trigger(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_trigger_MASK) >> SC_DEBUG_0_trigger_SHIFT) + +#define SC_DEBUG_0_SET_pa_freeze_b1(sc_debug_0_reg, pa_freeze_b1) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_freeze_b1_MASK) | (pa_freeze_b1 << SC_DEBUG_0_pa_freeze_b1_SHIFT) +#define SC_DEBUG_0_SET_pa_sc_valid(sc_debug_0_reg, pa_sc_valid) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_sc_valid_MASK) | (pa_sc_valid << SC_DEBUG_0_pa_sc_valid_SHIFT) +#define SC_DEBUG_0_SET_pa_sc_phase(sc_debug_0_reg, pa_sc_phase) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_sc_phase_MASK) | (pa_sc_phase << SC_DEBUG_0_pa_sc_phase_SHIFT) +#define SC_DEBUG_0_SET_cntx_cnt(sc_debug_0_reg, cntx_cnt) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_cntx_cnt_MASK) | (cntx_cnt << SC_DEBUG_0_cntx_cnt_SHIFT) +#define SC_DEBUG_0_SET_decr_cntx_cnt(sc_debug_0_reg, decr_cntx_cnt) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_decr_cntx_cnt_MASK) | (decr_cntx_cnt << SC_DEBUG_0_decr_cntx_cnt_SHIFT) +#define SC_DEBUG_0_SET_incr_cntx_cnt(sc_debug_0_reg, incr_cntx_cnt) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_incr_cntx_cnt_MASK) | (incr_cntx_cnt << SC_DEBUG_0_incr_cntx_cnt_SHIFT) +#define SC_DEBUG_0_SET_trigger(sc_debug_0_reg, trigger) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_trigger_MASK) | (trigger << SC_DEBUG_0_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_0_t { + unsigned int pa_freeze_b1 : SC_DEBUG_0_pa_freeze_b1_SIZE; + unsigned int pa_sc_valid : SC_DEBUG_0_pa_sc_valid_SIZE; + unsigned int pa_sc_phase : SC_DEBUG_0_pa_sc_phase_SIZE; + unsigned int cntx_cnt : SC_DEBUG_0_cntx_cnt_SIZE; + unsigned int decr_cntx_cnt : SC_DEBUG_0_decr_cntx_cnt_SIZE; + unsigned int incr_cntx_cnt : SC_DEBUG_0_incr_cntx_cnt_SIZE; + unsigned int : 17; + unsigned int trigger : SC_DEBUG_0_trigger_SIZE; + } sc_debug_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_0_t { + unsigned int trigger : SC_DEBUG_0_trigger_SIZE; + unsigned int : 17; + unsigned int incr_cntx_cnt : SC_DEBUG_0_incr_cntx_cnt_SIZE; + unsigned int decr_cntx_cnt : SC_DEBUG_0_decr_cntx_cnt_SIZE; + unsigned int cntx_cnt : SC_DEBUG_0_cntx_cnt_SIZE; + unsigned int pa_sc_phase : SC_DEBUG_0_pa_sc_phase_SIZE; + unsigned int pa_sc_valid : SC_DEBUG_0_pa_sc_valid_SIZE; + unsigned int pa_freeze_b1 : SC_DEBUG_0_pa_freeze_b1_SIZE; + } sc_debug_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_0_t f; +} sc_debug_0_u; + + +/* + * SC_DEBUG_1 struct + */ + +#define SC_DEBUG_1_em_state_SIZE 3 +#define SC_DEBUG_1_em1_data_ready_SIZE 1 +#define SC_DEBUG_1_em2_data_ready_SIZE 1 +#define SC_DEBUG_1_move_em1_to_em2_SIZE 1 +#define SC_DEBUG_1_ef_data_ready_SIZE 1 +#define SC_DEBUG_1_ef_state_SIZE 2 +#define SC_DEBUG_1_pipe_valid_SIZE 1 +#define SC_DEBUG_1_trigger_SIZE 1 + +#define SC_DEBUG_1_em_state_SHIFT 0 +#define SC_DEBUG_1_em1_data_ready_SHIFT 3 +#define SC_DEBUG_1_em2_data_ready_SHIFT 4 +#define SC_DEBUG_1_move_em1_to_em2_SHIFT 5 +#define SC_DEBUG_1_ef_data_ready_SHIFT 6 +#define SC_DEBUG_1_ef_state_SHIFT 7 +#define SC_DEBUG_1_pipe_valid_SHIFT 9 +#define SC_DEBUG_1_trigger_SHIFT 31 + +#define SC_DEBUG_1_em_state_MASK 0x00000007 +#define SC_DEBUG_1_em1_data_ready_MASK 0x00000008 +#define SC_DEBUG_1_em2_data_ready_MASK 0x00000010 +#define SC_DEBUG_1_move_em1_to_em2_MASK 0x00000020 +#define SC_DEBUG_1_ef_data_ready_MASK 0x00000040 +#define SC_DEBUG_1_ef_state_MASK 0x00000180 +#define SC_DEBUG_1_pipe_valid_MASK 0x00000200 +#define SC_DEBUG_1_trigger_MASK 0x80000000 + +#define SC_DEBUG_1_MASK \ + (SC_DEBUG_1_em_state_MASK | \ + SC_DEBUG_1_em1_data_ready_MASK | \ + SC_DEBUG_1_em2_data_ready_MASK | \ + SC_DEBUG_1_move_em1_to_em2_MASK | \ + SC_DEBUG_1_ef_data_ready_MASK | \ + SC_DEBUG_1_ef_state_MASK | \ + SC_DEBUG_1_pipe_valid_MASK | \ + SC_DEBUG_1_trigger_MASK) + +#define SC_DEBUG_1(em_state, em1_data_ready, em2_data_ready, move_em1_to_em2, ef_data_ready, ef_state, pipe_valid, trigger) \ + ((em_state << SC_DEBUG_1_em_state_SHIFT) | \ + (em1_data_ready << SC_DEBUG_1_em1_data_ready_SHIFT) | \ + (em2_data_ready << SC_DEBUG_1_em2_data_ready_SHIFT) | \ + (move_em1_to_em2 << SC_DEBUG_1_move_em1_to_em2_SHIFT) | \ + (ef_data_ready << SC_DEBUG_1_ef_data_ready_SHIFT) | \ + (ef_state << SC_DEBUG_1_ef_state_SHIFT) | \ + (pipe_valid << SC_DEBUG_1_pipe_valid_SHIFT) | \ + (trigger << SC_DEBUG_1_trigger_SHIFT)) + +#define SC_DEBUG_1_GET_em_state(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_em_state_MASK) >> SC_DEBUG_1_em_state_SHIFT) +#define SC_DEBUG_1_GET_em1_data_ready(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_em1_data_ready_MASK) >> SC_DEBUG_1_em1_data_ready_SHIFT) +#define SC_DEBUG_1_GET_em2_data_ready(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_em2_data_ready_MASK) >> SC_DEBUG_1_em2_data_ready_SHIFT) +#define SC_DEBUG_1_GET_move_em1_to_em2(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_move_em1_to_em2_MASK) >> SC_DEBUG_1_move_em1_to_em2_SHIFT) +#define SC_DEBUG_1_GET_ef_data_ready(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_ef_data_ready_MASK) >> SC_DEBUG_1_ef_data_ready_SHIFT) +#define SC_DEBUG_1_GET_ef_state(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_ef_state_MASK) >> SC_DEBUG_1_ef_state_SHIFT) +#define SC_DEBUG_1_GET_pipe_valid(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_pipe_valid_MASK) >> SC_DEBUG_1_pipe_valid_SHIFT) +#define SC_DEBUG_1_GET_trigger(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_trigger_MASK) >> SC_DEBUG_1_trigger_SHIFT) + +#define SC_DEBUG_1_SET_em_state(sc_debug_1_reg, em_state) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em_state_MASK) | (em_state << SC_DEBUG_1_em_state_SHIFT) +#define SC_DEBUG_1_SET_em1_data_ready(sc_debug_1_reg, em1_data_ready) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em1_data_ready_MASK) | (em1_data_ready << SC_DEBUG_1_em1_data_ready_SHIFT) +#define SC_DEBUG_1_SET_em2_data_ready(sc_debug_1_reg, em2_data_ready) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em2_data_ready_MASK) | (em2_data_ready << SC_DEBUG_1_em2_data_ready_SHIFT) +#define SC_DEBUG_1_SET_move_em1_to_em2(sc_debug_1_reg, move_em1_to_em2) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_move_em1_to_em2_MASK) | (move_em1_to_em2 << SC_DEBUG_1_move_em1_to_em2_SHIFT) +#define SC_DEBUG_1_SET_ef_data_ready(sc_debug_1_reg, ef_data_ready) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_ef_data_ready_MASK) | (ef_data_ready << SC_DEBUG_1_ef_data_ready_SHIFT) +#define SC_DEBUG_1_SET_ef_state(sc_debug_1_reg, ef_state) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_ef_state_MASK) | (ef_state << SC_DEBUG_1_ef_state_SHIFT) +#define SC_DEBUG_1_SET_pipe_valid(sc_debug_1_reg, pipe_valid) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_pipe_valid_MASK) | (pipe_valid << SC_DEBUG_1_pipe_valid_SHIFT) +#define SC_DEBUG_1_SET_trigger(sc_debug_1_reg, trigger) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_trigger_MASK) | (trigger << SC_DEBUG_1_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_1_t { + unsigned int em_state : SC_DEBUG_1_em_state_SIZE; + unsigned int em1_data_ready : SC_DEBUG_1_em1_data_ready_SIZE; + unsigned int em2_data_ready : SC_DEBUG_1_em2_data_ready_SIZE; + unsigned int move_em1_to_em2 : SC_DEBUG_1_move_em1_to_em2_SIZE; + unsigned int ef_data_ready : SC_DEBUG_1_ef_data_ready_SIZE; + unsigned int ef_state : SC_DEBUG_1_ef_state_SIZE; + unsigned int pipe_valid : SC_DEBUG_1_pipe_valid_SIZE; + unsigned int : 21; + unsigned int trigger : SC_DEBUG_1_trigger_SIZE; + } sc_debug_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_1_t { + unsigned int trigger : SC_DEBUG_1_trigger_SIZE; + unsigned int : 21; + unsigned int pipe_valid : SC_DEBUG_1_pipe_valid_SIZE; + unsigned int ef_state : SC_DEBUG_1_ef_state_SIZE; + unsigned int ef_data_ready : SC_DEBUG_1_ef_data_ready_SIZE; + unsigned int move_em1_to_em2 : SC_DEBUG_1_move_em1_to_em2_SIZE; + unsigned int em2_data_ready : SC_DEBUG_1_em2_data_ready_SIZE; + unsigned int em1_data_ready : SC_DEBUG_1_em1_data_ready_SIZE; + unsigned int em_state : SC_DEBUG_1_em_state_SIZE; + } sc_debug_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_1_t f; +} sc_debug_1_u; + + +/* + * SC_DEBUG_2 struct + */ + +#define SC_DEBUG_2_rc_rtr_dly_SIZE 1 +#define SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE 1 +#define SC_DEBUG_2_pipe_freeze_b_SIZE 1 +#define SC_DEBUG_2_prim_rts_SIZE 1 +#define SC_DEBUG_2_next_prim_rts_dly_SIZE 1 +#define SC_DEBUG_2_next_prim_rtr_dly_SIZE 1 +#define SC_DEBUG_2_pre_stage1_rts_d1_SIZE 1 +#define SC_DEBUG_2_stage0_rts_SIZE 1 +#define SC_DEBUG_2_phase_rts_dly_SIZE 1 +#define SC_DEBUG_2_end_of_prim_s1_dly_SIZE 1 +#define SC_DEBUG_2_pass_empty_prim_s1_SIZE 1 +#define SC_DEBUG_2_event_id_s1_SIZE 5 +#define SC_DEBUG_2_event_s1_SIZE 1 +#define SC_DEBUG_2_trigger_SIZE 1 + +#define SC_DEBUG_2_rc_rtr_dly_SHIFT 0 +#define SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT 1 +#define SC_DEBUG_2_pipe_freeze_b_SHIFT 3 +#define SC_DEBUG_2_prim_rts_SHIFT 4 +#define SC_DEBUG_2_next_prim_rts_dly_SHIFT 5 +#define SC_DEBUG_2_next_prim_rtr_dly_SHIFT 6 +#define SC_DEBUG_2_pre_stage1_rts_d1_SHIFT 7 +#define SC_DEBUG_2_stage0_rts_SHIFT 8 +#define SC_DEBUG_2_phase_rts_dly_SHIFT 9 +#define SC_DEBUG_2_end_of_prim_s1_dly_SHIFT 15 +#define SC_DEBUG_2_pass_empty_prim_s1_SHIFT 16 +#define SC_DEBUG_2_event_id_s1_SHIFT 17 +#define SC_DEBUG_2_event_s1_SHIFT 22 +#define SC_DEBUG_2_trigger_SHIFT 31 + +#define SC_DEBUG_2_rc_rtr_dly_MASK 0x00000001 +#define SC_DEBUG_2_qmask_ff_alm_full_d1_MASK 0x00000002 +#define SC_DEBUG_2_pipe_freeze_b_MASK 0x00000008 +#define SC_DEBUG_2_prim_rts_MASK 0x00000010 +#define SC_DEBUG_2_next_prim_rts_dly_MASK 0x00000020 +#define SC_DEBUG_2_next_prim_rtr_dly_MASK 0x00000040 +#define SC_DEBUG_2_pre_stage1_rts_d1_MASK 0x00000080 +#define SC_DEBUG_2_stage0_rts_MASK 0x00000100 +#define SC_DEBUG_2_phase_rts_dly_MASK 0x00000200 +#define SC_DEBUG_2_end_of_prim_s1_dly_MASK 0x00008000 +#define SC_DEBUG_2_pass_empty_prim_s1_MASK 0x00010000 +#define SC_DEBUG_2_event_id_s1_MASK 0x003e0000 +#define SC_DEBUG_2_event_s1_MASK 0x00400000 +#define SC_DEBUG_2_trigger_MASK 0x80000000 + +#define SC_DEBUG_2_MASK \ + (SC_DEBUG_2_rc_rtr_dly_MASK | \ + SC_DEBUG_2_qmask_ff_alm_full_d1_MASK | \ + SC_DEBUG_2_pipe_freeze_b_MASK | \ + SC_DEBUG_2_prim_rts_MASK | \ + SC_DEBUG_2_next_prim_rts_dly_MASK | \ + SC_DEBUG_2_next_prim_rtr_dly_MASK | \ + SC_DEBUG_2_pre_stage1_rts_d1_MASK | \ + SC_DEBUG_2_stage0_rts_MASK | \ + SC_DEBUG_2_phase_rts_dly_MASK | \ + SC_DEBUG_2_end_of_prim_s1_dly_MASK | \ + SC_DEBUG_2_pass_empty_prim_s1_MASK | \ + SC_DEBUG_2_event_id_s1_MASK | \ + SC_DEBUG_2_event_s1_MASK | \ + SC_DEBUG_2_trigger_MASK) + +#define SC_DEBUG_2(rc_rtr_dly, qmask_ff_alm_full_d1, pipe_freeze_b, prim_rts, next_prim_rts_dly, next_prim_rtr_dly, pre_stage1_rts_d1, stage0_rts, phase_rts_dly, end_of_prim_s1_dly, pass_empty_prim_s1, event_id_s1, event_s1, trigger) \ + ((rc_rtr_dly << SC_DEBUG_2_rc_rtr_dly_SHIFT) | \ + (qmask_ff_alm_full_d1 << SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT) | \ + (pipe_freeze_b << SC_DEBUG_2_pipe_freeze_b_SHIFT) | \ + (prim_rts << SC_DEBUG_2_prim_rts_SHIFT) | \ + (next_prim_rts_dly << SC_DEBUG_2_next_prim_rts_dly_SHIFT) | \ + (next_prim_rtr_dly << SC_DEBUG_2_next_prim_rtr_dly_SHIFT) | \ + (pre_stage1_rts_d1 << SC_DEBUG_2_pre_stage1_rts_d1_SHIFT) | \ + (stage0_rts << SC_DEBUG_2_stage0_rts_SHIFT) | \ + (phase_rts_dly << SC_DEBUG_2_phase_rts_dly_SHIFT) | \ + (end_of_prim_s1_dly << SC_DEBUG_2_end_of_prim_s1_dly_SHIFT) | \ + (pass_empty_prim_s1 << SC_DEBUG_2_pass_empty_prim_s1_SHIFT) | \ + (event_id_s1 << SC_DEBUG_2_event_id_s1_SHIFT) | \ + (event_s1 << SC_DEBUG_2_event_s1_SHIFT) | \ + (trigger << SC_DEBUG_2_trigger_SHIFT)) + +#define SC_DEBUG_2_GET_rc_rtr_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_rc_rtr_dly_MASK) >> SC_DEBUG_2_rc_rtr_dly_SHIFT) +#define SC_DEBUG_2_GET_qmask_ff_alm_full_d1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_qmask_ff_alm_full_d1_MASK) >> SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT) +#define SC_DEBUG_2_GET_pipe_freeze_b(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_pipe_freeze_b_MASK) >> SC_DEBUG_2_pipe_freeze_b_SHIFT) +#define SC_DEBUG_2_GET_prim_rts(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_prim_rts_MASK) >> SC_DEBUG_2_prim_rts_SHIFT) +#define SC_DEBUG_2_GET_next_prim_rts_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_next_prim_rts_dly_MASK) >> SC_DEBUG_2_next_prim_rts_dly_SHIFT) +#define SC_DEBUG_2_GET_next_prim_rtr_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_next_prim_rtr_dly_MASK) >> SC_DEBUG_2_next_prim_rtr_dly_SHIFT) +#define SC_DEBUG_2_GET_pre_stage1_rts_d1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_pre_stage1_rts_d1_MASK) >> SC_DEBUG_2_pre_stage1_rts_d1_SHIFT) +#define SC_DEBUG_2_GET_stage0_rts(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_stage0_rts_MASK) >> SC_DEBUG_2_stage0_rts_SHIFT) +#define SC_DEBUG_2_GET_phase_rts_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_phase_rts_dly_MASK) >> SC_DEBUG_2_phase_rts_dly_SHIFT) +#define SC_DEBUG_2_GET_end_of_prim_s1_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_end_of_prim_s1_dly_MASK) >> SC_DEBUG_2_end_of_prim_s1_dly_SHIFT) +#define SC_DEBUG_2_GET_pass_empty_prim_s1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_pass_empty_prim_s1_MASK) >> SC_DEBUG_2_pass_empty_prim_s1_SHIFT) +#define SC_DEBUG_2_GET_event_id_s1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_event_id_s1_MASK) >> SC_DEBUG_2_event_id_s1_SHIFT) +#define SC_DEBUG_2_GET_event_s1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_event_s1_MASK) >> SC_DEBUG_2_event_s1_SHIFT) +#define SC_DEBUG_2_GET_trigger(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_trigger_MASK) >> SC_DEBUG_2_trigger_SHIFT) + +#define SC_DEBUG_2_SET_rc_rtr_dly(sc_debug_2_reg, rc_rtr_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_rc_rtr_dly_MASK) | (rc_rtr_dly << SC_DEBUG_2_rc_rtr_dly_SHIFT) +#define SC_DEBUG_2_SET_qmask_ff_alm_full_d1(sc_debug_2_reg, qmask_ff_alm_full_d1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_qmask_ff_alm_full_d1_MASK) | (qmask_ff_alm_full_d1 << SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT) +#define SC_DEBUG_2_SET_pipe_freeze_b(sc_debug_2_reg, pipe_freeze_b) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pipe_freeze_b_MASK) | (pipe_freeze_b << SC_DEBUG_2_pipe_freeze_b_SHIFT) +#define SC_DEBUG_2_SET_prim_rts(sc_debug_2_reg, prim_rts) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_prim_rts_MASK) | (prim_rts << SC_DEBUG_2_prim_rts_SHIFT) +#define SC_DEBUG_2_SET_next_prim_rts_dly(sc_debug_2_reg, next_prim_rts_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_next_prim_rts_dly_MASK) | (next_prim_rts_dly << SC_DEBUG_2_next_prim_rts_dly_SHIFT) +#define SC_DEBUG_2_SET_next_prim_rtr_dly(sc_debug_2_reg, next_prim_rtr_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_next_prim_rtr_dly_MASK) | (next_prim_rtr_dly << SC_DEBUG_2_next_prim_rtr_dly_SHIFT) +#define SC_DEBUG_2_SET_pre_stage1_rts_d1(sc_debug_2_reg, pre_stage1_rts_d1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pre_stage1_rts_d1_MASK) | (pre_stage1_rts_d1 << SC_DEBUG_2_pre_stage1_rts_d1_SHIFT) +#define SC_DEBUG_2_SET_stage0_rts(sc_debug_2_reg, stage0_rts) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_stage0_rts_MASK) | (stage0_rts << SC_DEBUG_2_stage0_rts_SHIFT) +#define SC_DEBUG_2_SET_phase_rts_dly(sc_debug_2_reg, phase_rts_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_phase_rts_dly_MASK) | (phase_rts_dly << SC_DEBUG_2_phase_rts_dly_SHIFT) +#define SC_DEBUG_2_SET_end_of_prim_s1_dly(sc_debug_2_reg, end_of_prim_s1_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_end_of_prim_s1_dly_MASK) | (end_of_prim_s1_dly << SC_DEBUG_2_end_of_prim_s1_dly_SHIFT) +#define SC_DEBUG_2_SET_pass_empty_prim_s1(sc_debug_2_reg, pass_empty_prim_s1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pass_empty_prim_s1_MASK) | (pass_empty_prim_s1 << SC_DEBUG_2_pass_empty_prim_s1_SHIFT) +#define SC_DEBUG_2_SET_event_id_s1(sc_debug_2_reg, event_id_s1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_event_id_s1_MASK) | (event_id_s1 << SC_DEBUG_2_event_id_s1_SHIFT) +#define SC_DEBUG_2_SET_event_s1(sc_debug_2_reg, event_s1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_event_s1_MASK) | (event_s1 << SC_DEBUG_2_event_s1_SHIFT) +#define SC_DEBUG_2_SET_trigger(sc_debug_2_reg, trigger) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_trigger_MASK) | (trigger << SC_DEBUG_2_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_2_t { + unsigned int rc_rtr_dly : SC_DEBUG_2_rc_rtr_dly_SIZE; + unsigned int qmask_ff_alm_full_d1 : SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE; + unsigned int : 1; + unsigned int pipe_freeze_b : SC_DEBUG_2_pipe_freeze_b_SIZE; + unsigned int prim_rts : SC_DEBUG_2_prim_rts_SIZE; + unsigned int next_prim_rts_dly : SC_DEBUG_2_next_prim_rts_dly_SIZE; + unsigned int next_prim_rtr_dly : SC_DEBUG_2_next_prim_rtr_dly_SIZE; + unsigned int pre_stage1_rts_d1 : SC_DEBUG_2_pre_stage1_rts_d1_SIZE; + unsigned int stage0_rts : SC_DEBUG_2_stage0_rts_SIZE; + unsigned int phase_rts_dly : SC_DEBUG_2_phase_rts_dly_SIZE; + unsigned int : 5; + unsigned int end_of_prim_s1_dly : SC_DEBUG_2_end_of_prim_s1_dly_SIZE; + unsigned int pass_empty_prim_s1 : SC_DEBUG_2_pass_empty_prim_s1_SIZE; + unsigned int event_id_s1 : SC_DEBUG_2_event_id_s1_SIZE; + unsigned int event_s1 : SC_DEBUG_2_event_s1_SIZE; + unsigned int : 8; + unsigned int trigger : SC_DEBUG_2_trigger_SIZE; + } sc_debug_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_2_t { + unsigned int trigger : SC_DEBUG_2_trigger_SIZE; + unsigned int : 8; + unsigned int event_s1 : SC_DEBUG_2_event_s1_SIZE; + unsigned int event_id_s1 : SC_DEBUG_2_event_id_s1_SIZE; + unsigned int pass_empty_prim_s1 : SC_DEBUG_2_pass_empty_prim_s1_SIZE; + unsigned int end_of_prim_s1_dly : SC_DEBUG_2_end_of_prim_s1_dly_SIZE; + unsigned int : 5; + unsigned int phase_rts_dly : SC_DEBUG_2_phase_rts_dly_SIZE; + unsigned int stage0_rts : SC_DEBUG_2_stage0_rts_SIZE; + unsigned int pre_stage1_rts_d1 : SC_DEBUG_2_pre_stage1_rts_d1_SIZE; + unsigned int next_prim_rtr_dly : SC_DEBUG_2_next_prim_rtr_dly_SIZE; + unsigned int next_prim_rts_dly : SC_DEBUG_2_next_prim_rts_dly_SIZE; + unsigned int prim_rts : SC_DEBUG_2_prim_rts_SIZE; + unsigned int pipe_freeze_b : SC_DEBUG_2_pipe_freeze_b_SIZE; + unsigned int : 1; + unsigned int qmask_ff_alm_full_d1 : SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE; + unsigned int rc_rtr_dly : SC_DEBUG_2_rc_rtr_dly_SIZE; + } sc_debug_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_2_t f; +} sc_debug_2_u; + + +/* + * SC_DEBUG_3 struct + */ + +#define SC_DEBUG_3_x_curr_s1_SIZE 11 +#define SC_DEBUG_3_y_curr_s1_SIZE 11 +#define SC_DEBUG_3_trigger_SIZE 1 + +#define SC_DEBUG_3_x_curr_s1_SHIFT 0 +#define SC_DEBUG_3_y_curr_s1_SHIFT 11 +#define SC_DEBUG_3_trigger_SHIFT 31 + +#define SC_DEBUG_3_x_curr_s1_MASK 0x000007ff +#define SC_DEBUG_3_y_curr_s1_MASK 0x003ff800 +#define SC_DEBUG_3_trigger_MASK 0x80000000 + +#define SC_DEBUG_3_MASK \ + (SC_DEBUG_3_x_curr_s1_MASK | \ + SC_DEBUG_3_y_curr_s1_MASK | \ + SC_DEBUG_3_trigger_MASK) + +#define SC_DEBUG_3(x_curr_s1, y_curr_s1, trigger) \ + ((x_curr_s1 << SC_DEBUG_3_x_curr_s1_SHIFT) | \ + (y_curr_s1 << SC_DEBUG_3_y_curr_s1_SHIFT) | \ + (trigger << SC_DEBUG_3_trigger_SHIFT)) + +#define SC_DEBUG_3_GET_x_curr_s1(sc_debug_3) \ + ((sc_debug_3 & SC_DEBUG_3_x_curr_s1_MASK) >> SC_DEBUG_3_x_curr_s1_SHIFT) +#define SC_DEBUG_3_GET_y_curr_s1(sc_debug_3) \ + ((sc_debug_3 & SC_DEBUG_3_y_curr_s1_MASK) >> SC_DEBUG_3_y_curr_s1_SHIFT) +#define SC_DEBUG_3_GET_trigger(sc_debug_3) \ + ((sc_debug_3 & SC_DEBUG_3_trigger_MASK) >> SC_DEBUG_3_trigger_SHIFT) + +#define SC_DEBUG_3_SET_x_curr_s1(sc_debug_3_reg, x_curr_s1) \ + sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_x_curr_s1_MASK) | (x_curr_s1 << SC_DEBUG_3_x_curr_s1_SHIFT) +#define SC_DEBUG_3_SET_y_curr_s1(sc_debug_3_reg, y_curr_s1) \ + sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_y_curr_s1_MASK) | (y_curr_s1 << SC_DEBUG_3_y_curr_s1_SHIFT) +#define SC_DEBUG_3_SET_trigger(sc_debug_3_reg, trigger) \ + sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_trigger_MASK) | (trigger << SC_DEBUG_3_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_3_t { + unsigned int x_curr_s1 : SC_DEBUG_3_x_curr_s1_SIZE; + unsigned int y_curr_s1 : SC_DEBUG_3_y_curr_s1_SIZE; + unsigned int : 9; + unsigned int trigger : SC_DEBUG_3_trigger_SIZE; + } sc_debug_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_3_t { + unsigned int trigger : SC_DEBUG_3_trigger_SIZE; + unsigned int : 9; + unsigned int y_curr_s1 : SC_DEBUG_3_y_curr_s1_SIZE; + unsigned int x_curr_s1 : SC_DEBUG_3_x_curr_s1_SIZE; + } sc_debug_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_3_t f; +} sc_debug_3_u; + + +/* + * SC_DEBUG_4 struct + */ + +#define SC_DEBUG_4_y_end_s1_SIZE 14 +#define SC_DEBUG_4_y_start_s1_SIZE 14 +#define SC_DEBUG_4_y_dir_s1_SIZE 1 +#define SC_DEBUG_4_trigger_SIZE 1 + +#define SC_DEBUG_4_y_end_s1_SHIFT 0 +#define SC_DEBUG_4_y_start_s1_SHIFT 14 +#define SC_DEBUG_4_y_dir_s1_SHIFT 28 +#define SC_DEBUG_4_trigger_SHIFT 31 + +#define SC_DEBUG_4_y_end_s1_MASK 0x00003fff +#define SC_DEBUG_4_y_start_s1_MASK 0x0fffc000 +#define SC_DEBUG_4_y_dir_s1_MASK 0x10000000 +#define SC_DEBUG_4_trigger_MASK 0x80000000 + +#define SC_DEBUG_4_MASK \ + (SC_DEBUG_4_y_end_s1_MASK | \ + SC_DEBUG_4_y_start_s1_MASK | \ + SC_DEBUG_4_y_dir_s1_MASK | \ + SC_DEBUG_4_trigger_MASK) + +#define SC_DEBUG_4(y_end_s1, y_start_s1, y_dir_s1, trigger) \ + ((y_end_s1 << SC_DEBUG_4_y_end_s1_SHIFT) | \ + (y_start_s1 << SC_DEBUG_4_y_start_s1_SHIFT) | \ + (y_dir_s1 << SC_DEBUG_4_y_dir_s1_SHIFT) | \ + (trigger << SC_DEBUG_4_trigger_SHIFT)) + +#define SC_DEBUG_4_GET_y_end_s1(sc_debug_4) \ + ((sc_debug_4 & SC_DEBUG_4_y_end_s1_MASK) >> SC_DEBUG_4_y_end_s1_SHIFT) +#define SC_DEBUG_4_GET_y_start_s1(sc_debug_4) \ + ((sc_debug_4 & SC_DEBUG_4_y_start_s1_MASK) >> SC_DEBUG_4_y_start_s1_SHIFT) +#define SC_DEBUG_4_GET_y_dir_s1(sc_debug_4) \ + ((sc_debug_4 & SC_DEBUG_4_y_dir_s1_MASK) >> SC_DEBUG_4_y_dir_s1_SHIFT) +#define SC_DEBUG_4_GET_trigger(sc_debug_4) \ + ((sc_debug_4 & SC_DEBUG_4_trigger_MASK) >> SC_DEBUG_4_trigger_SHIFT) + +#define SC_DEBUG_4_SET_y_end_s1(sc_debug_4_reg, y_end_s1) \ + sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_end_s1_MASK) | (y_end_s1 << SC_DEBUG_4_y_end_s1_SHIFT) +#define SC_DEBUG_4_SET_y_start_s1(sc_debug_4_reg, y_start_s1) \ + sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_start_s1_MASK) | (y_start_s1 << SC_DEBUG_4_y_start_s1_SHIFT) +#define SC_DEBUG_4_SET_y_dir_s1(sc_debug_4_reg, y_dir_s1) \ + sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_dir_s1_MASK) | (y_dir_s1 << SC_DEBUG_4_y_dir_s1_SHIFT) +#define SC_DEBUG_4_SET_trigger(sc_debug_4_reg, trigger) \ + sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_trigger_MASK) | (trigger << SC_DEBUG_4_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_4_t { + unsigned int y_end_s1 : SC_DEBUG_4_y_end_s1_SIZE; + unsigned int y_start_s1 : SC_DEBUG_4_y_start_s1_SIZE; + unsigned int y_dir_s1 : SC_DEBUG_4_y_dir_s1_SIZE; + unsigned int : 2; + unsigned int trigger : SC_DEBUG_4_trigger_SIZE; + } sc_debug_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_4_t { + unsigned int trigger : SC_DEBUG_4_trigger_SIZE; + unsigned int : 2; + unsigned int y_dir_s1 : SC_DEBUG_4_y_dir_s1_SIZE; + unsigned int y_start_s1 : SC_DEBUG_4_y_start_s1_SIZE; + unsigned int y_end_s1 : SC_DEBUG_4_y_end_s1_SIZE; + } sc_debug_4_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_4_t f; +} sc_debug_4_u; + + +/* + * SC_DEBUG_5 struct + */ + +#define SC_DEBUG_5_x_end_s1_SIZE 14 +#define SC_DEBUG_5_x_start_s1_SIZE 14 +#define SC_DEBUG_5_x_dir_s1_SIZE 1 +#define SC_DEBUG_5_trigger_SIZE 1 + +#define SC_DEBUG_5_x_end_s1_SHIFT 0 +#define SC_DEBUG_5_x_start_s1_SHIFT 14 +#define SC_DEBUG_5_x_dir_s1_SHIFT 28 +#define SC_DEBUG_5_trigger_SHIFT 31 + +#define SC_DEBUG_5_x_end_s1_MASK 0x00003fff +#define SC_DEBUG_5_x_start_s1_MASK 0x0fffc000 +#define SC_DEBUG_5_x_dir_s1_MASK 0x10000000 +#define SC_DEBUG_5_trigger_MASK 0x80000000 + +#define SC_DEBUG_5_MASK \ + (SC_DEBUG_5_x_end_s1_MASK | \ + SC_DEBUG_5_x_start_s1_MASK | \ + SC_DEBUG_5_x_dir_s1_MASK | \ + SC_DEBUG_5_trigger_MASK) + +#define SC_DEBUG_5(x_end_s1, x_start_s1, x_dir_s1, trigger) \ + ((x_end_s1 << SC_DEBUG_5_x_end_s1_SHIFT) | \ + (x_start_s1 << SC_DEBUG_5_x_start_s1_SHIFT) | \ + (x_dir_s1 << SC_DEBUG_5_x_dir_s1_SHIFT) | \ + (trigger << SC_DEBUG_5_trigger_SHIFT)) + +#define SC_DEBUG_5_GET_x_end_s1(sc_debug_5) \ + ((sc_debug_5 & SC_DEBUG_5_x_end_s1_MASK) >> SC_DEBUG_5_x_end_s1_SHIFT) +#define SC_DEBUG_5_GET_x_start_s1(sc_debug_5) \ + ((sc_debug_5 & SC_DEBUG_5_x_start_s1_MASK) >> SC_DEBUG_5_x_start_s1_SHIFT) +#define SC_DEBUG_5_GET_x_dir_s1(sc_debug_5) \ + ((sc_debug_5 & SC_DEBUG_5_x_dir_s1_MASK) >> SC_DEBUG_5_x_dir_s1_SHIFT) +#define SC_DEBUG_5_GET_trigger(sc_debug_5) \ + ((sc_debug_5 & SC_DEBUG_5_trigger_MASK) >> SC_DEBUG_5_trigger_SHIFT) + +#define SC_DEBUG_5_SET_x_end_s1(sc_debug_5_reg, x_end_s1) \ + sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_end_s1_MASK) | (x_end_s1 << SC_DEBUG_5_x_end_s1_SHIFT) +#define SC_DEBUG_5_SET_x_start_s1(sc_debug_5_reg, x_start_s1) \ + sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_start_s1_MASK) | (x_start_s1 << SC_DEBUG_5_x_start_s1_SHIFT) +#define SC_DEBUG_5_SET_x_dir_s1(sc_debug_5_reg, x_dir_s1) \ + sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_dir_s1_MASK) | (x_dir_s1 << SC_DEBUG_5_x_dir_s1_SHIFT) +#define SC_DEBUG_5_SET_trigger(sc_debug_5_reg, trigger) \ + sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_trigger_MASK) | (trigger << SC_DEBUG_5_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_5_t { + unsigned int x_end_s1 : SC_DEBUG_5_x_end_s1_SIZE; + unsigned int x_start_s1 : SC_DEBUG_5_x_start_s1_SIZE; + unsigned int x_dir_s1 : SC_DEBUG_5_x_dir_s1_SIZE; + unsigned int : 2; + unsigned int trigger : SC_DEBUG_5_trigger_SIZE; + } sc_debug_5_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_5_t { + unsigned int trigger : SC_DEBUG_5_trigger_SIZE; + unsigned int : 2; + unsigned int x_dir_s1 : SC_DEBUG_5_x_dir_s1_SIZE; + unsigned int x_start_s1 : SC_DEBUG_5_x_start_s1_SIZE; + unsigned int x_end_s1 : SC_DEBUG_5_x_end_s1_SIZE; + } sc_debug_5_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_5_t f; +} sc_debug_5_u; + + +/* + * SC_DEBUG_6 struct + */ + +#define SC_DEBUG_6_z_ff_empty_SIZE 1 +#define SC_DEBUG_6_qmcntl_ff_empty_SIZE 1 +#define SC_DEBUG_6_xy_ff_empty_SIZE 1 +#define SC_DEBUG_6_event_flag_SIZE 1 +#define SC_DEBUG_6_z_mask_needed_SIZE 1 +#define SC_DEBUG_6_state_SIZE 3 +#define SC_DEBUG_6_state_delayed_SIZE 3 +#define SC_DEBUG_6_data_valid_SIZE 1 +#define SC_DEBUG_6_data_valid_d_SIZE 1 +#define SC_DEBUG_6_tilex_delayed_SIZE 9 +#define SC_DEBUG_6_tiley_delayed_SIZE 9 +#define SC_DEBUG_6_trigger_SIZE 1 + +#define SC_DEBUG_6_z_ff_empty_SHIFT 0 +#define SC_DEBUG_6_qmcntl_ff_empty_SHIFT 1 +#define SC_DEBUG_6_xy_ff_empty_SHIFT 2 +#define SC_DEBUG_6_event_flag_SHIFT 3 +#define SC_DEBUG_6_z_mask_needed_SHIFT 4 +#define SC_DEBUG_6_state_SHIFT 5 +#define SC_DEBUG_6_state_delayed_SHIFT 8 +#define SC_DEBUG_6_data_valid_SHIFT 11 +#define SC_DEBUG_6_data_valid_d_SHIFT 12 +#define SC_DEBUG_6_tilex_delayed_SHIFT 13 +#define SC_DEBUG_6_tiley_delayed_SHIFT 22 +#define SC_DEBUG_6_trigger_SHIFT 31 + +#define SC_DEBUG_6_z_ff_empty_MASK 0x00000001 +#define SC_DEBUG_6_qmcntl_ff_empty_MASK 0x00000002 +#define SC_DEBUG_6_xy_ff_empty_MASK 0x00000004 +#define SC_DEBUG_6_event_flag_MASK 0x00000008 +#define SC_DEBUG_6_z_mask_needed_MASK 0x00000010 +#define SC_DEBUG_6_state_MASK 0x000000e0 +#define SC_DEBUG_6_state_delayed_MASK 0x00000700 +#define SC_DEBUG_6_data_valid_MASK 0x00000800 +#define SC_DEBUG_6_data_valid_d_MASK 0x00001000 +#define SC_DEBUG_6_tilex_delayed_MASK 0x003fe000 +#define SC_DEBUG_6_tiley_delayed_MASK 0x7fc00000 +#define SC_DEBUG_6_trigger_MASK 0x80000000 + +#define SC_DEBUG_6_MASK \ + (SC_DEBUG_6_z_ff_empty_MASK | \ + SC_DEBUG_6_qmcntl_ff_empty_MASK | \ + SC_DEBUG_6_xy_ff_empty_MASK | \ + SC_DEBUG_6_event_flag_MASK | \ + SC_DEBUG_6_z_mask_needed_MASK | \ + SC_DEBUG_6_state_MASK | \ + SC_DEBUG_6_state_delayed_MASK | \ + SC_DEBUG_6_data_valid_MASK | \ + SC_DEBUG_6_data_valid_d_MASK | \ + SC_DEBUG_6_tilex_delayed_MASK | \ + SC_DEBUG_6_tiley_delayed_MASK | \ + SC_DEBUG_6_trigger_MASK) + +#define SC_DEBUG_6(z_ff_empty, qmcntl_ff_empty, xy_ff_empty, event_flag, z_mask_needed, state, state_delayed, data_valid, data_valid_d, tilex_delayed, tiley_delayed, trigger) \ + ((z_ff_empty << SC_DEBUG_6_z_ff_empty_SHIFT) | \ + (qmcntl_ff_empty << SC_DEBUG_6_qmcntl_ff_empty_SHIFT) | \ + (xy_ff_empty << SC_DEBUG_6_xy_ff_empty_SHIFT) | \ + (event_flag << SC_DEBUG_6_event_flag_SHIFT) | \ + (z_mask_needed << SC_DEBUG_6_z_mask_needed_SHIFT) | \ + (state << SC_DEBUG_6_state_SHIFT) | \ + (state_delayed << SC_DEBUG_6_state_delayed_SHIFT) | \ + (data_valid << SC_DEBUG_6_data_valid_SHIFT) | \ + (data_valid_d << SC_DEBUG_6_data_valid_d_SHIFT) | \ + (tilex_delayed << SC_DEBUG_6_tilex_delayed_SHIFT) | \ + (tiley_delayed << SC_DEBUG_6_tiley_delayed_SHIFT) | \ + (trigger << SC_DEBUG_6_trigger_SHIFT)) + +#define SC_DEBUG_6_GET_z_ff_empty(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_z_ff_empty_MASK) >> SC_DEBUG_6_z_ff_empty_SHIFT) +#define SC_DEBUG_6_GET_qmcntl_ff_empty(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_qmcntl_ff_empty_MASK) >> SC_DEBUG_6_qmcntl_ff_empty_SHIFT) +#define SC_DEBUG_6_GET_xy_ff_empty(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_xy_ff_empty_MASK) >> SC_DEBUG_6_xy_ff_empty_SHIFT) +#define SC_DEBUG_6_GET_event_flag(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_event_flag_MASK) >> SC_DEBUG_6_event_flag_SHIFT) +#define SC_DEBUG_6_GET_z_mask_needed(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_z_mask_needed_MASK) >> SC_DEBUG_6_z_mask_needed_SHIFT) +#define SC_DEBUG_6_GET_state(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_state_MASK) >> SC_DEBUG_6_state_SHIFT) +#define SC_DEBUG_6_GET_state_delayed(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_state_delayed_MASK) >> SC_DEBUG_6_state_delayed_SHIFT) +#define SC_DEBUG_6_GET_data_valid(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_data_valid_MASK) >> SC_DEBUG_6_data_valid_SHIFT) +#define SC_DEBUG_6_GET_data_valid_d(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_data_valid_d_MASK) >> SC_DEBUG_6_data_valid_d_SHIFT) +#define SC_DEBUG_6_GET_tilex_delayed(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_tilex_delayed_MASK) >> SC_DEBUG_6_tilex_delayed_SHIFT) +#define SC_DEBUG_6_GET_tiley_delayed(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_tiley_delayed_MASK) >> SC_DEBUG_6_tiley_delayed_SHIFT) +#define SC_DEBUG_6_GET_trigger(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_trigger_MASK) >> SC_DEBUG_6_trigger_SHIFT) + +#define SC_DEBUG_6_SET_z_ff_empty(sc_debug_6_reg, z_ff_empty) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_z_ff_empty_MASK) | (z_ff_empty << SC_DEBUG_6_z_ff_empty_SHIFT) +#define SC_DEBUG_6_SET_qmcntl_ff_empty(sc_debug_6_reg, qmcntl_ff_empty) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_qmcntl_ff_empty_MASK) | (qmcntl_ff_empty << SC_DEBUG_6_qmcntl_ff_empty_SHIFT) +#define SC_DEBUG_6_SET_xy_ff_empty(sc_debug_6_reg, xy_ff_empty) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_xy_ff_empty_MASK) | (xy_ff_empty << SC_DEBUG_6_xy_ff_empty_SHIFT) +#define SC_DEBUG_6_SET_event_flag(sc_debug_6_reg, event_flag) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_event_flag_MASK) | (event_flag << SC_DEBUG_6_event_flag_SHIFT) +#define SC_DEBUG_6_SET_z_mask_needed(sc_debug_6_reg, z_mask_needed) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_z_mask_needed_MASK) | (z_mask_needed << SC_DEBUG_6_z_mask_needed_SHIFT) +#define SC_DEBUG_6_SET_state(sc_debug_6_reg, state) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_state_MASK) | (state << SC_DEBUG_6_state_SHIFT) +#define SC_DEBUG_6_SET_state_delayed(sc_debug_6_reg, state_delayed) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_state_delayed_MASK) | (state_delayed << SC_DEBUG_6_state_delayed_SHIFT) +#define SC_DEBUG_6_SET_data_valid(sc_debug_6_reg, data_valid) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_data_valid_MASK) | (data_valid << SC_DEBUG_6_data_valid_SHIFT) +#define SC_DEBUG_6_SET_data_valid_d(sc_debug_6_reg, data_valid_d) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_data_valid_d_MASK) | (data_valid_d << SC_DEBUG_6_data_valid_d_SHIFT) +#define SC_DEBUG_6_SET_tilex_delayed(sc_debug_6_reg, tilex_delayed) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_tilex_delayed_MASK) | (tilex_delayed << SC_DEBUG_6_tilex_delayed_SHIFT) +#define SC_DEBUG_6_SET_tiley_delayed(sc_debug_6_reg, tiley_delayed) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_tiley_delayed_MASK) | (tiley_delayed << SC_DEBUG_6_tiley_delayed_SHIFT) +#define SC_DEBUG_6_SET_trigger(sc_debug_6_reg, trigger) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_trigger_MASK) | (trigger << SC_DEBUG_6_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_6_t { + unsigned int z_ff_empty : SC_DEBUG_6_z_ff_empty_SIZE; + unsigned int qmcntl_ff_empty : SC_DEBUG_6_qmcntl_ff_empty_SIZE; + unsigned int xy_ff_empty : SC_DEBUG_6_xy_ff_empty_SIZE; + unsigned int event_flag : SC_DEBUG_6_event_flag_SIZE; + unsigned int z_mask_needed : SC_DEBUG_6_z_mask_needed_SIZE; + unsigned int state : SC_DEBUG_6_state_SIZE; + unsigned int state_delayed : SC_DEBUG_6_state_delayed_SIZE; + unsigned int data_valid : SC_DEBUG_6_data_valid_SIZE; + unsigned int data_valid_d : SC_DEBUG_6_data_valid_d_SIZE; + unsigned int tilex_delayed : SC_DEBUG_6_tilex_delayed_SIZE; + unsigned int tiley_delayed : SC_DEBUG_6_tiley_delayed_SIZE; + unsigned int trigger : SC_DEBUG_6_trigger_SIZE; + } sc_debug_6_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_6_t { + unsigned int trigger : SC_DEBUG_6_trigger_SIZE; + unsigned int tiley_delayed : SC_DEBUG_6_tiley_delayed_SIZE; + unsigned int tilex_delayed : SC_DEBUG_6_tilex_delayed_SIZE; + unsigned int data_valid_d : SC_DEBUG_6_data_valid_d_SIZE; + unsigned int data_valid : SC_DEBUG_6_data_valid_SIZE; + unsigned int state_delayed : SC_DEBUG_6_state_delayed_SIZE; + unsigned int state : SC_DEBUG_6_state_SIZE; + unsigned int z_mask_needed : SC_DEBUG_6_z_mask_needed_SIZE; + unsigned int event_flag : SC_DEBUG_6_event_flag_SIZE; + unsigned int xy_ff_empty : SC_DEBUG_6_xy_ff_empty_SIZE; + unsigned int qmcntl_ff_empty : SC_DEBUG_6_qmcntl_ff_empty_SIZE; + unsigned int z_ff_empty : SC_DEBUG_6_z_ff_empty_SIZE; + } sc_debug_6_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_6_t f; +} sc_debug_6_u; + + +/* + * SC_DEBUG_7 struct + */ + +#define SC_DEBUG_7_event_flag_SIZE 1 +#define SC_DEBUG_7_deallocate_SIZE 3 +#define SC_DEBUG_7_fposition_SIZE 1 +#define SC_DEBUG_7_sr_prim_we_SIZE 1 +#define SC_DEBUG_7_last_tile_SIZE 1 +#define SC_DEBUG_7_tile_ff_we_SIZE 1 +#define SC_DEBUG_7_qs_data_valid_SIZE 1 +#define SC_DEBUG_7_qs_q0_y_SIZE 2 +#define SC_DEBUG_7_qs_q0_x_SIZE 2 +#define SC_DEBUG_7_qs_q0_valid_SIZE 1 +#define SC_DEBUG_7_prim_ff_we_SIZE 1 +#define SC_DEBUG_7_tile_ff_re_SIZE 1 +#define SC_DEBUG_7_fw_prim_data_valid_SIZE 1 +#define SC_DEBUG_7_last_quad_of_tile_SIZE 1 +#define SC_DEBUG_7_first_quad_of_tile_SIZE 1 +#define SC_DEBUG_7_first_quad_of_prim_SIZE 1 +#define SC_DEBUG_7_new_prim_SIZE 1 +#define SC_DEBUG_7_load_new_tile_data_SIZE 1 +#define SC_DEBUG_7_state_SIZE 2 +#define SC_DEBUG_7_fifos_ready_SIZE 1 +#define SC_DEBUG_7_trigger_SIZE 1 + +#define SC_DEBUG_7_event_flag_SHIFT 0 +#define SC_DEBUG_7_deallocate_SHIFT 1 +#define SC_DEBUG_7_fposition_SHIFT 4 +#define SC_DEBUG_7_sr_prim_we_SHIFT 5 +#define SC_DEBUG_7_last_tile_SHIFT 6 +#define SC_DEBUG_7_tile_ff_we_SHIFT 7 +#define SC_DEBUG_7_qs_data_valid_SHIFT 8 +#define SC_DEBUG_7_qs_q0_y_SHIFT 9 +#define SC_DEBUG_7_qs_q0_x_SHIFT 11 +#define SC_DEBUG_7_qs_q0_valid_SHIFT 13 +#define SC_DEBUG_7_prim_ff_we_SHIFT 14 +#define SC_DEBUG_7_tile_ff_re_SHIFT 15 +#define SC_DEBUG_7_fw_prim_data_valid_SHIFT 16 +#define SC_DEBUG_7_last_quad_of_tile_SHIFT 17 +#define SC_DEBUG_7_first_quad_of_tile_SHIFT 18 +#define SC_DEBUG_7_first_quad_of_prim_SHIFT 19 +#define SC_DEBUG_7_new_prim_SHIFT 20 +#define SC_DEBUG_7_load_new_tile_data_SHIFT 21 +#define SC_DEBUG_7_state_SHIFT 22 +#define SC_DEBUG_7_fifos_ready_SHIFT 24 +#define SC_DEBUG_7_trigger_SHIFT 31 + +#define SC_DEBUG_7_event_flag_MASK 0x00000001 +#define SC_DEBUG_7_deallocate_MASK 0x0000000e +#define SC_DEBUG_7_fposition_MASK 0x00000010 +#define SC_DEBUG_7_sr_prim_we_MASK 0x00000020 +#define SC_DEBUG_7_last_tile_MASK 0x00000040 +#define SC_DEBUG_7_tile_ff_we_MASK 0x00000080 +#define SC_DEBUG_7_qs_data_valid_MASK 0x00000100 +#define SC_DEBUG_7_qs_q0_y_MASK 0x00000600 +#define SC_DEBUG_7_qs_q0_x_MASK 0x00001800 +#define SC_DEBUG_7_qs_q0_valid_MASK 0x00002000 +#define SC_DEBUG_7_prim_ff_we_MASK 0x00004000 +#define SC_DEBUG_7_tile_ff_re_MASK 0x00008000 +#define SC_DEBUG_7_fw_prim_data_valid_MASK 0x00010000 +#define SC_DEBUG_7_last_quad_of_tile_MASK 0x00020000 +#define SC_DEBUG_7_first_quad_of_tile_MASK 0x00040000 +#define SC_DEBUG_7_first_quad_of_prim_MASK 0x00080000 +#define SC_DEBUG_7_new_prim_MASK 0x00100000 +#define SC_DEBUG_7_load_new_tile_data_MASK 0x00200000 +#define SC_DEBUG_7_state_MASK 0x00c00000 +#define SC_DEBUG_7_fifos_ready_MASK 0x01000000 +#define SC_DEBUG_7_trigger_MASK 0x80000000 + +#define SC_DEBUG_7_MASK \ + (SC_DEBUG_7_event_flag_MASK | \ + SC_DEBUG_7_deallocate_MASK | \ + SC_DEBUG_7_fposition_MASK | \ + SC_DEBUG_7_sr_prim_we_MASK | \ + SC_DEBUG_7_last_tile_MASK | \ + SC_DEBUG_7_tile_ff_we_MASK | \ + SC_DEBUG_7_qs_data_valid_MASK | \ + SC_DEBUG_7_qs_q0_y_MASK | \ + SC_DEBUG_7_qs_q0_x_MASK | \ + SC_DEBUG_7_qs_q0_valid_MASK | \ + SC_DEBUG_7_prim_ff_we_MASK | \ + SC_DEBUG_7_tile_ff_re_MASK | \ + SC_DEBUG_7_fw_prim_data_valid_MASK | \ + SC_DEBUG_7_last_quad_of_tile_MASK | \ + SC_DEBUG_7_first_quad_of_tile_MASK | \ + SC_DEBUG_7_first_quad_of_prim_MASK | \ + SC_DEBUG_7_new_prim_MASK | \ + SC_DEBUG_7_load_new_tile_data_MASK | \ + SC_DEBUG_7_state_MASK | \ + SC_DEBUG_7_fifos_ready_MASK | \ + SC_DEBUG_7_trigger_MASK) + +#define SC_DEBUG_7(event_flag, deallocate, fposition, sr_prim_we, last_tile, tile_ff_we, qs_data_valid, qs_q0_y, qs_q0_x, qs_q0_valid, prim_ff_we, tile_ff_re, fw_prim_data_valid, last_quad_of_tile, first_quad_of_tile, first_quad_of_prim, new_prim, load_new_tile_data, state, fifos_ready, trigger) \ + ((event_flag << SC_DEBUG_7_event_flag_SHIFT) | \ + (deallocate << SC_DEBUG_7_deallocate_SHIFT) | \ + (fposition << SC_DEBUG_7_fposition_SHIFT) | \ + (sr_prim_we << SC_DEBUG_7_sr_prim_we_SHIFT) | \ + (last_tile << SC_DEBUG_7_last_tile_SHIFT) | \ + (tile_ff_we << SC_DEBUG_7_tile_ff_we_SHIFT) | \ + (qs_data_valid << SC_DEBUG_7_qs_data_valid_SHIFT) | \ + (qs_q0_y << SC_DEBUG_7_qs_q0_y_SHIFT) | \ + (qs_q0_x << SC_DEBUG_7_qs_q0_x_SHIFT) | \ + (qs_q0_valid << SC_DEBUG_7_qs_q0_valid_SHIFT) | \ + (prim_ff_we << SC_DEBUG_7_prim_ff_we_SHIFT) | \ + (tile_ff_re << SC_DEBUG_7_tile_ff_re_SHIFT) | \ + (fw_prim_data_valid << SC_DEBUG_7_fw_prim_data_valid_SHIFT) | \ + (last_quad_of_tile << SC_DEBUG_7_last_quad_of_tile_SHIFT) | \ + (first_quad_of_tile << SC_DEBUG_7_first_quad_of_tile_SHIFT) | \ + (first_quad_of_prim << SC_DEBUG_7_first_quad_of_prim_SHIFT) | \ + (new_prim << SC_DEBUG_7_new_prim_SHIFT) | \ + (load_new_tile_data << SC_DEBUG_7_load_new_tile_data_SHIFT) | \ + (state << SC_DEBUG_7_state_SHIFT) | \ + (fifos_ready << SC_DEBUG_7_fifos_ready_SHIFT) | \ + (trigger << SC_DEBUG_7_trigger_SHIFT)) + +#define SC_DEBUG_7_GET_event_flag(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_event_flag_MASK) >> SC_DEBUG_7_event_flag_SHIFT) +#define SC_DEBUG_7_GET_deallocate(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_deallocate_MASK) >> SC_DEBUG_7_deallocate_SHIFT) +#define SC_DEBUG_7_GET_fposition(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_fposition_MASK) >> SC_DEBUG_7_fposition_SHIFT) +#define SC_DEBUG_7_GET_sr_prim_we(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_sr_prim_we_MASK) >> SC_DEBUG_7_sr_prim_we_SHIFT) +#define SC_DEBUG_7_GET_last_tile(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_last_tile_MASK) >> SC_DEBUG_7_last_tile_SHIFT) +#define SC_DEBUG_7_GET_tile_ff_we(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_tile_ff_we_MASK) >> SC_DEBUG_7_tile_ff_we_SHIFT) +#define SC_DEBUG_7_GET_qs_data_valid(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_qs_data_valid_MASK) >> SC_DEBUG_7_qs_data_valid_SHIFT) +#define SC_DEBUG_7_GET_qs_q0_y(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_qs_q0_y_MASK) >> SC_DEBUG_7_qs_q0_y_SHIFT) +#define SC_DEBUG_7_GET_qs_q0_x(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_qs_q0_x_MASK) >> SC_DEBUG_7_qs_q0_x_SHIFT) +#define SC_DEBUG_7_GET_qs_q0_valid(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_qs_q0_valid_MASK) >> SC_DEBUG_7_qs_q0_valid_SHIFT) +#define SC_DEBUG_7_GET_prim_ff_we(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_prim_ff_we_MASK) >> SC_DEBUG_7_prim_ff_we_SHIFT) +#define SC_DEBUG_7_GET_tile_ff_re(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_tile_ff_re_MASK) >> SC_DEBUG_7_tile_ff_re_SHIFT) +#define SC_DEBUG_7_GET_fw_prim_data_valid(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_fw_prim_data_valid_MASK) >> SC_DEBUG_7_fw_prim_data_valid_SHIFT) +#define SC_DEBUG_7_GET_last_quad_of_tile(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_last_quad_of_tile_MASK) >> SC_DEBUG_7_last_quad_of_tile_SHIFT) +#define SC_DEBUG_7_GET_first_quad_of_tile(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_first_quad_of_tile_MASK) >> SC_DEBUG_7_first_quad_of_tile_SHIFT) +#define SC_DEBUG_7_GET_first_quad_of_prim(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_first_quad_of_prim_MASK) >> SC_DEBUG_7_first_quad_of_prim_SHIFT) +#define SC_DEBUG_7_GET_new_prim(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_new_prim_MASK) >> SC_DEBUG_7_new_prim_SHIFT) +#define SC_DEBUG_7_GET_load_new_tile_data(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_load_new_tile_data_MASK) >> SC_DEBUG_7_load_new_tile_data_SHIFT) +#define SC_DEBUG_7_GET_state(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_state_MASK) >> SC_DEBUG_7_state_SHIFT) +#define SC_DEBUG_7_GET_fifos_ready(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_fifos_ready_MASK) >> SC_DEBUG_7_fifos_ready_SHIFT) +#define SC_DEBUG_7_GET_trigger(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_trigger_MASK) >> SC_DEBUG_7_trigger_SHIFT) + +#define SC_DEBUG_7_SET_event_flag(sc_debug_7_reg, event_flag) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_event_flag_MASK) | (event_flag << SC_DEBUG_7_event_flag_SHIFT) +#define SC_DEBUG_7_SET_deallocate(sc_debug_7_reg, deallocate) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_deallocate_MASK) | (deallocate << SC_DEBUG_7_deallocate_SHIFT) +#define SC_DEBUG_7_SET_fposition(sc_debug_7_reg, fposition) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fposition_MASK) | (fposition << SC_DEBUG_7_fposition_SHIFT) +#define SC_DEBUG_7_SET_sr_prim_we(sc_debug_7_reg, sr_prim_we) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_sr_prim_we_MASK) | (sr_prim_we << SC_DEBUG_7_sr_prim_we_SHIFT) +#define SC_DEBUG_7_SET_last_tile(sc_debug_7_reg, last_tile) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_last_tile_MASK) | (last_tile << SC_DEBUG_7_last_tile_SHIFT) +#define SC_DEBUG_7_SET_tile_ff_we(sc_debug_7_reg, tile_ff_we) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_tile_ff_we_MASK) | (tile_ff_we << SC_DEBUG_7_tile_ff_we_SHIFT) +#define SC_DEBUG_7_SET_qs_data_valid(sc_debug_7_reg, qs_data_valid) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_data_valid_MASK) | (qs_data_valid << SC_DEBUG_7_qs_data_valid_SHIFT) +#define SC_DEBUG_7_SET_qs_q0_y(sc_debug_7_reg, qs_q0_y) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_y_MASK) | (qs_q0_y << SC_DEBUG_7_qs_q0_y_SHIFT) +#define SC_DEBUG_7_SET_qs_q0_x(sc_debug_7_reg, qs_q0_x) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_x_MASK) | (qs_q0_x << SC_DEBUG_7_qs_q0_x_SHIFT) +#define SC_DEBUG_7_SET_qs_q0_valid(sc_debug_7_reg, qs_q0_valid) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_valid_MASK) | (qs_q0_valid << SC_DEBUG_7_qs_q0_valid_SHIFT) +#define SC_DEBUG_7_SET_prim_ff_we(sc_debug_7_reg, prim_ff_we) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_prim_ff_we_MASK) | (prim_ff_we << SC_DEBUG_7_prim_ff_we_SHIFT) +#define SC_DEBUG_7_SET_tile_ff_re(sc_debug_7_reg, tile_ff_re) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_tile_ff_re_MASK) | (tile_ff_re << SC_DEBUG_7_tile_ff_re_SHIFT) +#define SC_DEBUG_7_SET_fw_prim_data_valid(sc_debug_7_reg, fw_prim_data_valid) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fw_prim_data_valid_MASK) | (fw_prim_data_valid << SC_DEBUG_7_fw_prim_data_valid_SHIFT) +#define SC_DEBUG_7_SET_last_quad_of_tile(sc_debug_7_reg, last_quad_of_tile) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_last_quad_of_tile_MASK) | (last_quad_of_tile << SC_DEBUG_7_last_quad_of_tile_SHIFT) +#define SC_DEBUG_7_SET_first_quad_of_tile(sc_debug_7_reg, first_quad_of_tile) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_first_quad_of_tile_MASK) | (first_quad_of_tile << SC_DEBUG_7_first_quad_of_tile_SHIFT) +#define SC_DEBUG_7_SET_first_quad_of_prim(sc_debug_7_reg, first_quad_of_prim) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_first_quad_of_prim_MASK) | (first_quad_of_prim << SC_DEBUG_7_first_quad_of_prim_SHIFT) +#define SC_DEBUG_7_SET_new_prim(sc_debug_7_reg, new_prim) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_new_prim_MASK) | (new_prim << SC_DEBUG_7_new_prim_SHIFT) +#define SC_DEBUG_7_SET_load_new_tile_data(sc_debug_7_reg, load_new_tile_data) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_load_new_tile_data_MASK) | (load_new_tile_data << SC_DEBUG_7_load_new_tile_data_SHIFT) +#define SC_DEBUG_7_SET_state(sc_debug_7_reg, state) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_state_MASK) | (state << SC_DEBUG_7_state_SHIFT) +#define SC_DEBUG_7_SET_fifos_ready(sc_debug_7_reg, fifos_ready) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fifos_ready_MASK) | (fifos_ready << SC_DEBUG_7_fifos_ready_SHIFT) +#define SC_DEBUG_7_SET_trigger(sc_debug_7_reg, trigger) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_trigger_MASK) | (trigger << SC_DEBUG_7_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_7_t { + unsigned int event_flag : SC_DEBUG_7_event_flag_SIZE; + unsigned int deallocate : SC_DEBUG_7_deallocate_SIZE; + unsigned int fposition : SC_DEBUG_7_fposition_SIZE; + unsigned int sr_prim_we : SC_DEBUG_7_sr_prim_we_SIZE; + unsigned int last_tile : SC_DEBUG_7_last_tile_SIZE; + unsigned int tile_ff_we : SC_DEBUG_7_tile_ff_we_SIZE; + unsigned int qs_data_valid : SC_DEBUG_7_qs_data_valid_SIZE; + unsigned int qs_q0_y : SC_DEBUG_7_qs_q0_y_SIZE; + unsigned int qs_q0_x : SC_DEBUG_7_qs_q0_x_SIZE; + unsigned int qs_q0_valid : SC_DEBUG_7_qs_q0_valid_SIZE; + unsigned int prim_ff_we : SC_DEBUG_7_prim_ff_we_SIZE; + unsigned int tile_ff_re : SC_DEBUG_7_tile_ff_re_SIZE; + unsigned int fw_prim_data_valid : SC_DEBUG_7_fw_prim_data_valid_SIZE; + unsigned int last_quad_of_tile : SC_DEBUG_7_last_quad_of_tile_SIZE; + unsigned int first_quad_of_tile : SC_DEBUG_7_first_quad_of_tile_SIZE; + unsigned int first_quad_of_prim : SC_DEBUG_7_first_quad_of_prim_SIZE; + unsigned int new_prim : SC_DEBUG_7_new_prim_SIZE; + unsigned int load_new_tile_data : SC_DEBUG_7_load_new_tile_data_SIZE; + unsigned int state : SC_DEBUG_7_state_SIZE; + unsigned int fifos_ready : SC_DEBUG_7_fifos_ready_SIZE; + unsigned int : 6; + unsigned int trigger : SC_DEBUG_7_trigger_SIZE; + } sc_debug_7_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_7_t { + unsigned int trigger : SC_DEBUG_7_trigger_SIZE; + unsigned int : 6; + unsigned int fifos_ready : SC_DEBUG_7_fifos_ready_SIZE; + unsigned int state : SC_DEBUG_7_state_SIZE; + unsigned int load_new_tile_data : SC_DEBUG_7_load_new_tile_data_SIZE; + unsigned int new_prim : SC_DEBUG_7_new_prim_SIZE; + unsigned int first_quad_of_prim : SC_DEBUG_7_first_quad_of_prim_SIZE; + unsigned int first_quad_of_tile : SC_DEBUG_7_first_quad_of_tile_SIZE; + unsigned int last_quad_of_tile : SC_DEBUG_7_last_quad_of_tile_SIZE; + unsigned int fw_prim_data_valid : SC_DEBUG_7_fw_prim_data_valid_SIZE; + unsigned int tile_ff_re : SC_DEBUG_7_tile_ff_re_SIZE; + unsigned int prim_ff_we : SC_DEBUG_7_prim_ff_we_SIZE; + unsigned int qs_q0_valid : SC_DEBUG_7_qs_q0_valid_SIZE; + unsigned int qs_q0_x : SC_DEBUG_7_qs_q0_x_SIZE; + unsigned int qs_q0_y : SC_DEBUG_7_qs_q0_y_SIZE; + unsigned int qs_data_valid : SC_DEBUG_7_qs_data_valid_SIZE; + unsigned int tile_ff_we : SC_DEBUG_7_tile_ff_we_SIZE; + unsigned int last_tile : SC_DEBUG_7_last_tile_SIZE; + unsigned int sr_prim_we : SC_DEBUG_7_sr_prim_we_SIZE; + unsigned int fposition : SC_DEBUG_7_fposition_SIZE; + unsigned int deallocate : SC_DEBUG_7_deallocate_SIZE; + unsigned int event_flag : SC_DEBUG_7_event_flag_SIZE; + } sc_debug_7_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_7_t f; +} sc_debug_7_u; + + +/* + * SC_DEBUG_8 struct + */ + +#define SC_DEBUG_8_sample_last_SIZE 1 +#define SC_DEBUG_8_sample_mask_SIZE 4 +#define SC_DEBUG_8_sample_y_SIZE 2 +#define SC_DEBUG_8_sample_x_SIZE 2 +#define SC_DEBUG_8_sample_send_SIZE 1 +#define SC_DEBUG_8_next_cycle_SIZE 2 +#define SC_DEBUG_8_ez_sample_ff_full_SIZE 1 +#define SC_DEBUG_8_rb_sc_samp_rtr_SIZE 1 +#define SC_DEBUG_8_num_samples_SIZE 2 +#define SC_DEBUG_8_last_quad_of_tile_SIZE 1 +#define SC_DEBUG_8_last_quad_of_prim_SIZE 1 +#define SC_DEBUG_8_first_quad_of_prim_SIZE 1 +#define SC_DEBUG_8_sample_we_SIZE 1 +#define SC_DEBUG_8_fposition_SIZE 1 +#define SC_DEBUG_8_event_id_SIZE 5 +#define SC_DEBUG_8_event_flag_SIZE 1 +#define SC_DEBUG_8_fw_prim_data_valid_SIZE 1 +#define SC_DEBUG_8_trigger_SIZE 1 + +#define SC_DEBUG_8_sample_last_SHIFT 0 +#define SC_DEBUG_8_sample_mask_SHIFT 1 +#define SC_DEBUG_8_sample_y_SHIFT 5 +#define SC_DEBUG_8_sample_x_SHIFT 7 +#define SC_DEBUG_8_sample_send_SHIFT 9 +#define SC_DEBUG_8_next_cycle_SHIFT 10 +#define SC_DEBUG_8_ez_sample_ff_full_SHIFT 12 +#define SC_DEBUG_8_rb_sc_samp_rtr_SHIFT 13 +#define SC_DEBUG_8_num_samples_SHIFT 14 +#define SC_DEBUG_8_last_quad_of_tile_SHIFT 16 +#define SC_DEBUG_8_last_quad_of_prim_SHIFT 17 +#define SC_DEBUG_8_first_quad_of_prim_SHIFT 18 +#define SC_DEBUG_8_sample_we_SHIFT 19 +#define SC_DEBUG_8_fposition_SHIFT 20 +#define SC_DEBUG_8_event_id_SHIFT 21 +#define SC_DEBUG_8_event_flag_SHIFT 26 +#define SC_DEBUG_8_fw_prim_data_valid_SHIFT 27 +#define SC_DEBUG_8_trigger_SHIFT 31 + +#define SC_DEBUG_8_sample_last_MASK 0x00000001 +#define SC_DEBUG_8_sample_mask_MASK 0x0000001e +#define SC_DEBUG_8_sample_y_MASK 0x00000060 +#define SC_DEBUG_8_sample_x_MASK 0x00000180 +#define SC_DEBUG_8_sample_send_MASK 0x00000200 +#define SC_DEBUG_8_next_cycle_MASK 0x00000c00 +#define SC_DEBUG_8_ez_sample_ff_full_MASK 0x00001000 +#define SC_DEBUG_8_rb_sc_samp_rtr_MASK 0x00002000 +#define SC_DEBUG_8_num_samples_MASK 0x0000c000 +#define SC_DEBUG_8_last_quad_of_tile_MASK 0x00010000 +#define SC_DEBUG_8_last_quad_of_prim_MASK 0x00020000 +#define SC_DEBUG_8_first_quad_of_prim_MASK 0x00040000 +#define SC_DEBUG_8_sample_we_MASK 0x00080000 +#define SC_DEBUG_8_fposition_MASK 0x00100000 +#define SC_DEBUG_8_event_id_MASK 0x03e00000 +#define SC_DEBUG_8_event_flag_MASK 0x04000000 +#define SC_DEBUG_8_fw_prim_data_valid_MASK 0x08000000 +#define SC_DEBUG_8_trigger_MASK 0x80000000 + +#define SC_DEBUG_8_MASK \ + (SC_DEBUG_8_sample_last_MASK | \ + SC_DEBUG_8_sample_mask_MASK | \ + SC_DEBUG_8_sample_y_MASK | \ + SC_DEBUG_8_sample_x_MASK | \ + SC_DEBUG_8_sample_send_MASK | \ + SC_DEBUG_8_next_cycle_MASK | \ + SC_DEBUG_8_ez_sample_ff_full_MASK | \ + SC_DEBUG_8_rb_sc_samp_rtr_MASK | \ + SC_DEBUG_8_num_samples_MASK | \ + SC_DEBUG_8_last_quad_of_tile_MASK | \ + SC_DEBUG_8_last_quad_of_prim_MASK | \ + SC_DEBUG_8_first_quad_of_prim_MASK | \ + SC_DEBUG_8_sample_we_MASK | \ + SC_DEBUG_8_fposition_MASK | \ + SC_DEBUG_8_event_id_MASK | \ + SC_DEBUG_8_event_flag_MASK | \ + SC_DEBUG_8_fw_prim_data_valid_MASK | \ + SC_DEBUG_8_trigger_MASK) + +#define SC_DEBUG_8(sample_last, sample_mask, sample_y, sample_x, sample_send, next_cycle, ez_sample_ff_full, rb_sc_samp_rtr, num_samples, last_quad_of_tile, last_quad_of_prim, first_quad_of_prim, sample_we, fposition, event_id, event_flag, fw_prim_data_valid, trigger) \ + ((sample_last << SC_DEBUG_8_sample_last_SHIFT) | \ + (sample_mask << SC_DEBUG_8_sample_mask_SHIFT) | \ + (sample_y << SC_DEBUG_8_sample_y_SHIFT) | \ + (sample_x << SC_DEBUG_8_sample_x_SHIFT) | \ + (sample_send << SC_DEBUG_8_sample_send_SHIFT) | \ + (next_cycle << SC_DEBUG_8_next_cycle_SHIFT) | \ + (ez_sample_ff_full << SC_DEBUG_8_ez_sample_ff_full_SHIFT) | \ + (rb_sc_samp_rtr << SC_DEBUG_8_rb_sc_samp_rtr_SHIFT) | \ + (num_samples << SC_DEBUG_8_num_samples_SHIFT) | \ + (last_quad_of_tile << SC_DEBUG_8_last_quad_of_tile_SHIFT) | \ + (last_quad_of_prim << SC_DEBUG_8_last_quad_of_prim_SHIFT) | \ + (first_quad_of_prim << SC_DEBUG_8_first_quad_of_prim_SHIFT) | \ + (sample_we << SC_DEBUG_8_sample_we_SHIFT) | \ + (fposition << SC_DEBUG_8_fposition_SHIFT) | \ + (event_id << SC_DEBUG_8_event_id_SHIFT) | \ + (event_flag << SC_DEBUG_8_event_flag_SHIFT) | \ + (fw_prim_data_valid << SC_DEBUG_8_fw_prim_data_valid_SHIFT) | \ + (trigger << SC_DEBUG_8_trigger_SHIFT)) + +#define SC_DEBUG_8_GET_sample_last(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_last_MASK) >> SC_DEBUG_8_sample_last_SHIFT) +#define SC_DEBUG_8_GET_sample_mask(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_mask_MASK) >> SC_DEBUG_8_sample_mask_SHIFT) +#define SC_DEBUG_8_GET_sample_y(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_y_MASK) >> SC_DEBUG_8_sample_y_SHIFT) +#define SC_DEBUG_8_GET_sample_x(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_x_MASK) >> SC_DEBUG_8_sample_x_SHIFT) +#define SC_DEBUG_8_GET_sample_send(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_send_MASK) >> SC_DEBUG_8_sample_send_SHIFT) +#define SC_DEBUG_8_GET_next_cycle(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_next_cycle_MASK) >> SC_DEBUG_8_next_cycle_SHIFT) +#define SC_DEBUG_8_GET_ez_sample_ff_full(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_ez_sample_ff_full_MASK) >> SC_DEBUG_8_ez_sample_ff_full_SHIFT) +#define SC_DEBUG_8_GET_rb_sc_samp_rtr(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_rb_sc_samp_rtr_MASK) >> SC_DEBUG_8_rb_sc_samp_rtr_SHIFT) +#define SC_DEBUG_8_GET_num_samples(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_num_samples_MASK) >> SC_DEBUG_8_num_samples_SHIFT) +#define SC_DEBUG_8_GET_last_quad_of_tile(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_last_quad_of_tile_MASK) >> SC_DEBUG_8_last_quad_of_tile_SHIFT) +#define SC_DEBUG_8_GET_last_quad_of_prim(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_last_quad_of_prim_MASK) >> SC_DEBUG_8_last_quad_of_prim_SHIFT) +#define SC_DEBUG_8_GET_first_quad_of_prim(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_first_quad_of_prim_MASK) >> SC_DEBUG_8_first_quad_of_prim_SHIFT) +#define SC_DEBUG_8_GET_sample_we(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_we_MASK) >> SC_DEBUG_8_sample_we_SHIFT) +#define SC_DEBUG_8_GET_fposition(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_fposition_MASK) >> SC_DEBUG_8_fposition_SHIFT) +#define SC_DEBUG_8_GET_event_id(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_event_id_MASK) >> SC_DEBUG_8_event_id_SHIFT) +#define SC_DEBUG_8_GET_event_flag(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_event_flag_MASK) >> SC_DEBUG_8_event_flag_SHIFT) +#define SC_DEBUG_8_GET_fw_prim_data_valid(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_fw_prim_data_valid_MASK) >> SC_DEBUG_8_fw_prim_data_valid_SHIFT) +#define SC_DEBUG_8_GET_trigger(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_trigger_MASK) >> SC_DEBUG_8_trigger_SHIFT) + +#define SC_DEBUG_8_SET_sample_last(sc_debug_8_reg, sample_last) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_last_MASK) | (sample_last << SC_DEBUG_8_sample_last_SHIFT) +#define SC_DEBUG_8_SET_sample_mask(sc_debug_8_reg, sample_mask) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_mask_MASK) | (sample_mask << SC_DEBUG_8_sample_mask_SHIFT) +#define SC_DEBUG_8_SET_sample_y(sc_debug_8_reg, sample_y) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_y_MASK) | (sample_y << SC_DEBUG_8_sample_y_SHIFT) +#define SC_DEBUG_8_SET_sample_x(sc_debug_8_reg, sample_x) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_x_MASK) | (sample_x << SC_DEBUG_8_sample_x_SHIFT) +#define SC_DEBUG_8_SET_sample_send(sc_debug_8_reg, sample_send) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_send_MASK) | (sample_send << SC_DEBUG_8_sample_send_SHIFT) +#define SC_DEBUG_8_SET_next_cycle(sc_debug_8_reg, next_cycle) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_next_cycle_MASK) | (next_cycle << SC_DEBUG_8_next_cycle_SHIFT) +#define SC_DEBUG_8_SET_ez_sample_ff_full(sc_debug_8_reg, ez_sample_ff_full) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_ez_sample_ff_full_MASK) | (ez_sample_ff_full << SC_DEBUG_8_ez_sample_ff_full_SHIFT) +#define SC_DEBUG_8_SET_rb_sc_samp_rtr(sc_debug_8_reg, rb_sc_samp_rtr) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_rb_sc_samp_rtr_MASK) | (rb_sc_samp_rtr << SC_DEBUG_8_rb_sc_samp_rtr_SHIFT) +#define SC_DEBUG_8_SET_num_samples(sc_debug_8_reg, num_samples) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_num_samples_MASK) | (num_samples << SC_DEBUG_8_num_samples_SHIFT) +#define SC_DEBUG_8_SET_last_quad_of_tile(sc_debug_8_reg, last_quad_of_tile) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_last_quad_of_tile_MASK) | (last_quad_of_tile << SC_DEBUG_8_last_quad_of_tile_SHIFT) +#define SC_DEBUG_8_SET_last_quad_of_prim(sc_debug_8_reg, last_quad_of_prim) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_last_quad_of_prim_MASK) | (last_quad_of_prim << SC_DEBUG_8_last_quad_of_prim_SHIFT) +#define SC_DEBUG_8_SET_first_quad_of_prim(sc_debug_8_reg, first_quad_of_prim) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_first_quad_of_prim_MASK) | (first_quad_of_prim << SC_DEBUG_8_first_quad_of_prim_SHIFT) +#define SC_DEBUG_8_SET_sample_we(sc_debug_8_reg, sample_we) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_we_MASK) | (sample_we << SC_DEBUG_8_sample_we_SHIFT) +#define SC_DEBUG_8_SET_fposition(sc_debug_8_reg, fposition) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_fposition_MASK) | (fposition << SC_DEBUG_8_fposition_SHIFT) +#define SC_DEBUG_8_SET_event_id(sc_debug_8_reg, event_id) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_event_id_MASK) | (event_id << SC_DEBUG_8_event_id_SHIFT) +#define SC_DEBUG_8_SET_event_flag(sc_debug_8_reg, event_flag) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_event_flag_MASK) | (event_flag << SC_DEBUG_8_event_flag_SHIFT) +#define SC_DEBUG_8_SET_fw_prim_data_valid(sc_debug_8_reg, fw_prim_data_valid) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_fw_prim_data_valid_MASK) | (fw_prim_data_valid << SC_DEBUG_8_fw_prim_data_valid_SHIFT) +#define SC_DEBUG_8_SET_trigger(sc_debug_8_reg, trigger) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_trigger_MASK) | (trigger << SC_DEBUG_8_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_8_t { + unsigned int sample_last : SC_DEBUG_8_sample_last_SIZE; + unsigned int sample_mask : SC_DEBUG_8_sample_mask_SIZE; + unsigned int sample_y : SC_DEBUG_8_sample_y_SIZE; + unsigned int sample_x : SC_DEBUG_8_sample_x_SIZE; + unsigned int sample_send : SC_DEBUG_8_sample_send_SIZE; + unsigned int next_cycle : SC_DEBUG_8_next_cycle_SIZE; + unsigned int ez_sample_ff_full : SC_DEBUG_8_ez_sample_ff_full_SIZE; + unsigned int rb_sc_samp_rtr : SC_DEBUG_8_rb_sc_samp_rtr_SIZE; + unsigned int num_samples : SC_DEBUG_8_num_samples_SIZE; + unsigned int last_quad_of_tile : SC_DEBUG_8_last_quad_of_tile_SIZE; + unsigned int last_quad_of_prim : SC_DEBUG_8_last_quad_of_prim_SIZE; + unsigned int first_quad_of_prim : SC_DEBUG_8_first_quad_of_prim_SIZE; + unsigned int sample_we : SC_DEBUG_8_sample_we_SIZE; + unsigned int fposition : SC_DEBUG_8_fposition_SIZE; + unsigned int event_id : SC_DEBUG_8_event_id_SIZE; + unsigned int event_flag : SC_DEBUG_8_event_flag_SIZE; + unsigned int fw_prim_data_valid : SC_DEBUG_8_fw_prim_data_valid_SIZE; + unsigned int : 3; + unsigned int trigger : SC_DEBUG_8_trigger_SIZE; + } sc_debug_8_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_8_t { + unsigned int trigger : SC_DEBUG_8_trigger_SIZE; + unsigned int : 3; + unsigned int fw_prim_data_valid : SC_DEBUG_8_fw_prim_data_valid_SIZE; + unsigned int event_flag : SC_DEBUG_8_event_flag_SIZE; + unsigned int event_id : SC_DEBUG_8_event_id_SIZE; + unsigned int fposition : SC_DEBUG_8_fposition_SIZE; + unsigned int sample_we : SC_DEBUG_8_sample_we_SIZE; + unsigned int first_quad_of_prim : SC_DEBUG_8_first_quad_of_prim_SIZE; + unsigned int last_quad_of_prim : SC_DEBUG_8_last_quad_of_prim_SIZE; + unsigned int last_quad_of_tile : SC_DEBUG_8_last_quad_of_tile_SIZE; + unsigned int num_samples : SC_DEBUG_8_num_samples_SIZE; + unsigned int rb_sc_samp_rtr : SC_DEBUG_8_rb_sc_samp_rtr_SIZE; + unsigned int ez_sample_ff_full : SC_DEBUG_8_ez_sample_ff_full_SIZE; + unsigned int next_cycle : SC_DEBUG_8_next_cycle_SIZE; + unsigned int sample_send : SC_DEBUG_8_sample_send_SIZE; + unsigned int sample_x : SC_DEBUG_8_sample_x_SIZE; + unsigned int sample_y : SC_DEBUG_8_sample_y_SIZE; + unsigned int sample_mask : SC_DEBUG_8_sample_mask_SIZE; + unsigned int sample_last : SC_DEBUG_8_sample_last_SIZE; + } sc_debug_8_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_8_t f; +} sc_debug_8_u; + + +/* + * SC_DEBUG_9 struct + */ + +#define SC_DEBUG_9_rb_sc_send_SIZE 1 +#define SC_DEBUG_9_rb_sc_ez_mask_SIZE 4 +#define SC_DEBUG_9_fifo_data_ready_SIZE 1 +#define SC_DEBUG_9_early_z_enable_SIZE 1 +#define SC_DEBUG_9_mask_state_SIZE 2 +#define SC_DEBUG_9_next_ez_mask_SIZE 16 +#define SC_DEBUG_9_mask_ready_SIZE 1 +#define SC_DEBUG_9_drop_sample_SIZE 1 +#define SC_DEBUG_9_fetch_new_sample_data_SIZE 1 +#define SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE 1 +#define SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE 1 +#define SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE 1 +#define SC_DEBUG_9_trigger_SIZE 1 + +#define SC_DEBUG_9_rb_sc_send_SHIFT 0 +#define SC_DEBUG_9_rb_sc_ez_mask_SHIFT 1 +#define SC_DEBUG_9_fifo_data_ready_SHIFT 5 +#define SC_DEBUG_9_early_z_enable_SHIFT 6 +#define SC_DEBUG_9_mask_state_SHIFT 7 +#define SC_DEBUG_9_next_ez_mask_SHIFT 9 +#define SC_DEBUG_9_mask_ready_SHIFT 25 +#define SC_DEBUG_9_drop_sample_SHIFT 26 +#define SC_DEBUG_9_fetch_new_sample_data_SHIFT 27 +#define SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT 28 +#define SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT 29 +#define SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT 30 +#define SC_DEBUG_9_trigger_SHIFT 31 + +#define SC_DEBUG_9_rb_sc_send_MASK 0x00000001 +#define SC_DEBUG_9_rb_sc_ez_mask_MASK 0x0000001e +#define SC_DEBUG_9_fifo_data_ready_MASK 0x00000020 +#define SC_DEBUG_9_early_z_enable_MASK 0x00000040 +#define SC_DEBUG_9_mask_state_MASK 0x00000180 +#define SC_DEBUG_9_next_ez_mask_MASK 0x01fffe00 +#define SC_DEBUG_9_mask_ready_MASK 0x02000000 +#define SC_DEBUG_9_drop_sample_MASK 0x04000000 +#define SC_DEBUG_9_fetch_new_sample_data_MASK 0x08000000 +#define SC_DEBUG_9_fetch_new_ez_sample_mask_MASK 0x10000000 +#define SC_DEBUG_9_pkr_fetch_new_sample_data_MASK 0x20000000 +#define SC_DEBUG_9_pkr_fetch_new_prim_data_MASK 0x40000000 +#define SC_DEBUG_9_trigger_MASK 0x80000000 + +#define SC_DEBUG_9_MASK \ + (SC_DEBUG_9_rb_sc_send_MASK | \ + SC_DEBUG_9_rb_sc_ez_mask_MASK | \ + SC_DEBUG_9_fifo_data_ready_MASK | \ + SC_DEBUG_9_early_z_enable_MASK | \ + SC_DEBUG_9_mask_state_MASK | \ + SC_DEBUG_9_next_ez_mask_MASK | \ + SC_DEBUG_9_mask_ready_MASK | \ + SC_DEBUG_9_drop_sample_MASK | \ + SC_DEBUG_9_fetch_new_sample_data_MASK | \ + SC_DEBUG_9_fetch_new_ez_sample_mask_MASK | \ + SC_DEBUG_9_pkr_fetch_new_sample_data_MASK | \ + SC_DEBUG_9_pkr_fetch_new_prim_data_MASK | \ + SC_DEBUG_9_trigger_MASK) + +#define SC_DEBUG_9(rb_sc_send, rb_sc_ez_mask, fifo_data_ready, early_z_enable, mask_state, next_ez_mask, mask_ready, drop_sample, fetch_new_sample_data, fetch_new_ez_sample_mask, pkr_fetch_new_sample_data, pkr_fetch_new_prim_data, trigger) \ + ((rb_sc_send << SC_DEBUG_9_rb_sc_send_SHIFT) | \ + (rb_sc_ez_mask << SC_DEBUG_9_rb_sc_ez_mask_SHIFT) | \ + (fifo_data_ready << SC_DEBUG_9_fifo_data_ready_SHIFT) | \ + (early_z_enable << SC_DEBUG_9_early_z_enable_SHIFT) | \ + (mask_state << SC_DEBUG_9_mask_state_SHIFT) | \ + (next_ez_mask << SC_DEBUG_9_next_ez_mask_SHIFT) | \ + (mask_ready << SC_DEBUG_9_mask_ready_SHIFT) | \ + (drop_sample << SC_DEBUG_9_drop_sample_SHIFT) | \ + (fetch_new_sample_data << SC_DEBUG_9_fetch_new_sample_data_SHIFT) | \ + (fetch_new_ez_sample_mask << SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT) | \ + (pkr_fetch_new_sample_data << SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT) | \ + (pkr_fetch_new_prim_data << SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT) | \ + (trigger << SC_DEBUG_9_trigger_SHIFT)) + +#define SC_DEBUG_9_GET_rb_sc_send(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_rb_sc_send_MASK) >> SC_DEBUG_9_rb_sc_send_SHIFT) +#define SC_DEBUG_9_GET_rb_sc_ez_mask(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_rb_sc_ez_mask_MASK) >> SC_DEBUG_9_rb_sc_ez_mask_SHIFT) +#define SC_DEBUG_9_GET_fifo_data_ready(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_fifo_data_ready_MASK) >> SC_DEBUG_9_fifo_data_ready_SHIFT) +#define SC_DEBUG_9_GET_early_z_enable(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_early_z_enable_MASK) >> SC_DEBUG_9_early_z_enable_SHIFT) +#define SC_DEBUG_9_GET_mask_state(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_mask_state_MASK) >> SC_DEBUG_9_mask_state_SHIFT) +#define SC_DEBUG_9_GET_next_ez_mask(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_next_ez_mask_MASK) >> SC_DEBUG_9_next_ez_mask_SHIFT) +#define SC_DEBUG_9_GET_mask_ready(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_mask_ready_MASK) >> SC_DEBUG_9_mask_ready_SHIFT) +#define SC_DEBUG_9_GET_drop_sample(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_drop_sample_MASK) >> SC_DEBUG_9_drop_sample_SHIFT) +#define SC_DEBUG_9_GET_fetch_new_sample_data(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_fetch_new_sample_data_MASK) >> SC_DEBUG_9_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_9_GET_fetch_new_ez_sample_mask(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_fetch_new_ez_sample_mask_MASK) >> SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT) +#define SC_DEBUG_9_GET_pkr_fetch_new_sample_data(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_pkr_fetch_new_sample_data_MASK) >> SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_9_GET_pkr_fetch_new_prim_data(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_pkr_fetch_new_prim_data_MASK) >> SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT) +#define SC_DEBUG_9_GET_trigger(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_trigger_MASK) >> SC_DEBUG_9_trigger_SHIFT) + +#define SC_DEBUG_9_SET_rb_sc_send(sc_debug_9_reg, rb_sc_send) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_rb_sc_send_MASK) | (rb_sc_send << SC_DEBUG_9_rb_sc_send_SHIFT) +#define SC_DEBUG_9_SET_rb_sc_ez_mask(sc_debug_9_reg, rb_sc_ez_mask) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_rb_sc_ez_mask_MASK) | (rb_sc_ez_mask << SC_DEBUG_9_rb_sc_ez_mask_SHIFT) +#define SC_DEBUG_9_SET_fifo_data_ready(sc_debug_9_reg, fifo_data_ready) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fifo_data_ready_MASK) | (fifo_data_ready << SC_DEBUG_9_fifo_data_ready_SHIFT) +#define SC_DEBUG_9_SET_early_z_enable(sc_debug_9_reg, early_z_enable) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_early_z_enable_MASK) | (early_z_enable << SC_DEBUG_9_early_z_enable_SHIFT) +#define SC_DEBUG_9_SET_mask_state(sc_debug_9_reg, mask_state) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_mask_state_MASK) | (mask_state << SC_DEBUG_9_mask_state_SHIFT) +#define SC_DEBUG_9_SET_next_ez_mask(sc_debug_9_reg, next_ez_mask) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_next_ez_mask_MASK) | (next_ez_mask << SC_DEBUG_9_next_ez_mask_SHIFT) +#define SC_DEBUG_9_SET_mask_ready(sc_debug_9_reg, mask_ready) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_mask_ready_MASK) | (mask_ready << SC_DEBUG_9_mask_ready_SHIFT) +#define SC_DEBUG_9_SET_drop_sample(sc_debug_9_reg, drop_sample) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_drop_sample_MASK) | (drop_sample << SC_DEBUG_9_drop_sample_SHIFT) +#define SC_DEBUG_9_SET_fetch_new_sample_data(sc_debug_9_reg, fetch_new_sample_data) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fetch_new_sample_data_MASK) | (fetch_new_sample_data << SC_DEBUG_9_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_9_SET_fetch_new_ez_sample_mask(sc_debug_9_reg, fetch_new_ez_sample_mask) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fetch_new_ez_sample_mask_MASK) | (fetch_new_ez_sample_mask << SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT) +#define SC_DEBUG_9_SET_pkr_fetch_new_sample_data(sc_debug_9_reg, pkr_fetch_new_sample_data) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_pkr_fetch_new_sample_data_MASK) | (pkr_fetch_new_sample_data << SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_9_SET_pkr_fetch_new_prim_data(sc_debug_9_reg, pkr_fetch_new_prim_data) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_pkr_fetch_new_prim_data_MASK) | (pkr_fetch_new_prim_data << SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT) +#define SC_DEBUG_9_SET_trigger(sc_debug_9_reg, trigger) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_trigger_MASK) | (trigger << SC_DEBUG_9_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_9_t { + unsigned int rb_sc_send : SC_DEBUG_9_rb_sc_send_SIZE; + unsigned int rb_sc_ez_mask : SC_DEBUG_9_rb_sc_ez_mask_SIZE; + unsigned int fifo_data_ready : SC_DEBUG_9_fifo_data_ready_SIZE; + unsigned int early_z_enable : SC_DEBUG_9_early_z_enable_SIZE; + unsigned int mask_state : SC_DEBUG_9_mask_state_SIZE; + unsigned int next_ez_mask : SC_DEBUG_9_next_ez_mask_SIZE; + unsigned int mask_ready : SC_DEBUG_9_mask_ready_SIZE; + unsigned int drop_sample : SC_DEBUG_9_drop_sample_SIZE; + unsigned int fetch_new_sample_data : SC_DEBUG_9_fetch_new_sample_data_SIZE; + unsigned int fetch_new_ez_sample_mask : SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE; + unsigned int pkr_fetch_new_sample_data : SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE; + unsigned int pkr_fetch_new_prim_data : SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE; + unsigned int trigger : SC_DEBUG_9_trigger_SIZE; + } sc_debug_9_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_9_t { + unsigned int trigger : SC_DEBUG_9_trigger_SIZE; + unsigned int pkr_fetch_new_prim_data : SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE; + unsigned int pkr_fetch_new_sample_data : SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE; + unsigned int fetch_new_ez_sample_mask : SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE; + unsigned int fetch_new_sample_data : SC_DEBUG_9_fetch_new_sample_data_SIZE; + unsigned int drop_sample : SC_DEBUG_9_drop_sample_SIZE; + unsigned int mask_ready : SC_DEBUG_9_mask_ready_SIZE; + unsigned int next_ez_mask : SC_DEBUG_9_next_ez_mask_SIZE; + unsigned int mask_state : SC_DEBUG_9_mask_state_SIZE; + unsigned int early_z_enable : SC_DEBUG_9_early_z_enable_SIZE; + unsigned int fifo_data_ready : SC_DEBUG_9_fifo_data_ready_SIZE; + unsigned int rb_sc_ez_mask : SC_DEBUG_9_rb_sc_ez_mask_SIZE; + unsigned int rb_sc_send : SC_DEBUG_9_rb_sc_send_SIZE; + } sc_debug_9_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_9_t f; +} sc_debug_9_u; + + +/* + * SC_DEBUG_10 struct + */ + +#define SC_DEBUG_10_combined_sample_mask_SIZE 16 +#define SC_DEBUG_10_trigger_SIZE 1 + +#define SC_DEBUG_10_combined_sample_mask_SHIFT 0 +#define SC_DEBUG_10_trigger_SHIFT 31 + +#define SC_DEBUG_10_combined_sample_mask_MASK 0x0000ffff +#define SC_DEBUG_10_trigger_MASK 0x80000000 + +#define SC_DEBUG_10_MASK \ + (SC_DEBUG_10_combined_sample_mask_MASK | \ + SC_DEBUG_10_trigger_MASK) + +#define SC_DEBUG_10(combined_sample_mask, trigger) \ + ((combined_sample_mask << SC_DEBUG_10_combined_sample_mask_SHIFT) | \ + (trigger << SC_DEBUG_10_trigger_SHIFT)) + +#define SC_DEBUG_10_GET_combined_sample_mask(sc_debug_10) \ + ((sc_debug_10 & SC_DEBUG_10_combined_sample_mask_MASK) >> SC_DEBUG_10_combined_sample_mask_SHIFT) +#define SC_DEBUG_10_GET_trigger(sc_debug_10) \ + ((sc_debug_10 & SC_DEBUG_10_trigger_MASK) >> SC_DEBUG_10_trigger_SHIFT) + +#define SC_DEBUG_10_SET_combined_sample_mask(sc_debug_10_reg, combined_sample_mask) \ + sc_debug_10_reg = (sc_debug_10_reg & ~SC_DEBUG_10_combined_sample_mask_MASK) | (combined_sample_mask << SC_DEBUG_10_combined_sample_mask_SHIFT) +#define SC_DEBUG_10_SET_trigger(sc_debug_10_reg, trigger) \ + sc_debug_10_reg = (sc_debug_10_reg & ~SC_DEBUG_10_trigger_MASK) | (trigger << SC_DEBUG_10_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_10_t { + unsigned int combined_sample_mask : SC_DEBUG_10_combined_sample_mask_SIZE; + unsigned int : 15; + unsigned int trigger : SC_DEBUG_10_trigger_SIZE; + } sc_debug_10_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_10_t { + unsigned int trigger : SC_DEBUG_10_trigger_SIZE; + unsigned int : 15; + unsigned int combined_sample_mask : SC_DEBUG_10_combined_sample_mask_SIZE; + } sc_debug_10_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_10_t f; +} sc_debug_10_u; + + +/* + * SC_DEBUG_11 struct + */ + +#define SC_DEBUG_11_ez_sample_data_ready_SIZE 1 +#define SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE 1 +#define SC_DEBUG_11_ez_prim_data_ready_SIZE 1 +#define SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE 1 +#define SC_DEBUG_11_iterator_input_fz_SIZE 1 +#define SC_DEBUG_11_packer_send_quads_SIZE 1 +#define SC_DEBUG_11_packer_send_cmd_SIZE 1 +#define SC_DEBUG_11_packer_send_event_SIZE 1 +#define SC_DEBUG_11_next_state_SIZE 3 +#define SC_DEBUG_11_state_SIZE 3 +#define SC_DEBUG_11_stall_SIZE 1 +#define SC_DEBUG_11_trigger_SIZE 1 + +#define SC_DEBUG_11_ez_sample_data_ready_SHIFT 0 +#define SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT 1 +#define SC_DEBUG_11_ez_prim_data_ready_SHIFT 2 +#define SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT 3 +#define SC_DEBUG_11_iterator_input_fz_SHIFT 4 +#define SC_DEBUG_11_packer_send_quads_SHIFT 5 +#define SC_DEBUG_11_packer_send_cmd_SHIFT 6 +#define SC_DEBUG_11_packer_send_event_SHIFT 7 +#define SC_DEBUG_11_next_state_SHIFT 8 +#define SC_DEBUG_11_state_SHIFT 11 +#define SC_DEBUG_11_stall_SHIFT 14 +#define SC_DEBUG_11_trigger_SHIFT 31 + +#define SC_DEBUG_11_ez_sample_data_ready_MASK 0x00000001 +#define SC_DEBUG_11_pkr_fetch_new_sample_data_MASK 0x00000002 +#define SC_DEBUG_11_ez_prim_data_ready_MASK 0x00000004 +#define SC_DEBUG_11_pkr_fetch_new_prim_data_MASK 0x00000008 +#define SC_DEBUG_11_iterator_input_fz_MASK 0x00000010 +#define SC_DEBUG_11_packer_send_quads_MASK 0x00000020 +#define SC_DEBUG_11_packer_send_cmd_MASK 0x00000040 +#define SC_DEBUG_11_packer_send_event_MASK 0x00000080 +#define SC_DEBUG_11_next_state_MASK 0x00000700 +#define SC_DEBUG_11_state_MASK 0x00003800 +#define SC_DEBUG_11_stall_MASK 0x00004000 +#define SC_DEBUG_11_trigger_MASK 0x80000000 + +#define SC_DEBUG_11_MASK \ + (SC_DEBUG_11_ez_sample_data_ready_MASK | \ + SC_DEBUG_11_pkr_fetch_new_sample_data_MASK | \ + SC_DEBUG_11_ez_prim_data_ready_MASK | \ + SC_DEBUG_11_pkr_fetch_new_prim_data_MASK | \ + SC_DEBUG_11_iterator_input_fz_MASK | \ + SC_DEBUG_11_packer_send_quads_MASK | \ + SC_DEBUG_11_packer_send_cmd_MASK | \ + SC_DEBUG_11_packer_send_event_MASK | \ + SC_DEBUG_11_next_state_MASK | \ + SC_DEBUG_11_state_MASK | \ + SC_DEBUG_11_stall_MASK | \ + SC_DEBUG_11_trigger_MASK) + +#define SC_DEBUG_11(ez_sample_data_ready, pkr_fetch_new_sample_data, ez_prim_data_ready, pkr_fetch_new_prim_data, iterator_input_fz, packer_send_quads, packer_send_cmd, packer_send_event, next_state, state, stall, trigger) \ + ((ez_sample_data_ready << SC_DEBUG_11_ez_sample_data_ready_SHIFT) | \ + (pkr_fetch_new_sample_data << SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT) | \ + (ez_prim_data_ready << SC_DEBUG_11_ez_prim_data_ready_SHIFT) | \ + (pkr_fetch_new_prim_data << SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT) | \ + (iterator_input_fz << SC_DEBUG_11_iterator_input_fz_SHIFT) | \ + (packer_send_quads << SC_DEBUG_11_packer_send_quads_SHIFT) | \ + (packer_send_cmd << SC_DEBUG_11_packer_send_cmd_SHIFT) | \ + (packer_send_event << SC_DEBUG_11_packer_send_event_SHIFT) | \ + (next_state << SC_DEBUG_11_next_state_SHIFT) | \ + (state << SC_DEBUG_11_state_SHIFT) | \ + (stall << SC_DEBUG_11_stall_SHIFT) | \ + (trigger << SC_DEBUG_11_trigger_SHIFT)) + +#define SC_DEBUG_11_GET_ez_sample_data_ready(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_ez_sample_data_ready_MASK) >> SC_DEBUG_11_ez_sample_data_ready_SHIFT) +#define SC_DEBUG_11_GET_pkr_fetch_new_sample_data(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_pkr_fetch_new_sample_data_MASK) >> SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_11_GET_ez_prim_data_ready(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_ez_prim_data_ready_MASK) >> SC_DEBUG_11_ez_prim_data_ready_SHIFT) +#define SC_DEBUG_11_GET_pkr_fetch_new_prim_data(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_pkr_fetch_new_prim_data_MASK) >> SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT) +#define SC_DEBUG_11_GET_iterator_input_fz(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_iterator_input_fz_MASK) >> SC_DEBUG_11_iterator_input_fz_SHIFT) +#define SC_DEBUG_11_GET_packer_send_quads(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_packer_send_quads_MASK) >> SC_DEBUG_11_packer_send_quads_SHIFT) +#define SC_DEBUG_11_GET_packer_send_cmd(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_packer_send_cmd_MASK) >> SC_DEBUG_11_packer_send_cmd_SHIFT) +#define SC_DEBUG_11_GET_packer_send_event(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_packer_send_event_MASK) >> SC_DEBUG_11_packer_send_event_SHIFT) +#define SC_DEBUG_11_GET_next_state(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_next_state_MASK) >> SC_DEBUG_11_next_state_SHIFT) +#define SC_DEBUG_11_GET_state(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_state_MASK) >> SC_DEBUG_11_state_SHIFT) +#define SC_DEBUG_11_GET_stall(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_stall_MASK) >> SC_DEBUG_11_stall_SHIFT) +#define SC_DEBUG_11_GET_trigger(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_trigger_MASK) >> SC_DEBUG_11_trigger_SHIFT) + +#define SC_DEBUG_11_SET_ez_sample_data_ready(sc_debug_11_reg, ez_sample_data_ready) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_ez_sample_data_ready_MASK) | (ez_sample_data_ready << SC_DEBUG_11_ez_sample_data_ready_SHIFT) +#define SC_DEBUG_11_SET_pkr_fetch_new_sample_data(sc_debug_11_reg, pkr_fetch_new_sample_data) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_pkr_fetch_new_sample_data_MASK) | (pkr_fetch_new_sample_data << SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_11_SET_ez_prim_data_ready(sc_debug_11_reg, ez_prim_data_ready) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_ez_prim_data_ready_MASK) | (ez_prim_data_ready << SC_DEBUG_11_ez_prim_data_ready_SHIFT) +#define SC_DEBUG_11_SET_pkr_fetch_new_prim_data(sc_debug_11_reg, pkr_fetch_new_prim_data) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_pkr_fetch_new_prim_data_MASK) | (pkr_fetch_new_prim_data << SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT) +#define SC_DEBUG_11_SET_iterator_input_fz(sc_debug_11_reg, iterator_input_fz) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_iterator_input_fz_MASK) | (iterator_input_fz << SC_DEBUG_11_iterator_input_fz_SHIFT) +#define SC_DEBUG_11_SET_packer_send_quads(sc_debug_11_reg, packer_send_quads) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_quads_MASK) | (packer_send_quads << SC_DEBUG_11_packer_send_quads_SHIFT) +#define SC_DEBUG_11_SET_packer_send_cmd(sc_debug_11_reg, packer_send_cmd) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_cmd_MASK) | (packer_send_cmd << SC_DEBUG_11_packer_send_cmd_SHIFT) +#define SC_DEBUG_11_SET_packer_send_event(sc_debug_11_reg, packer_send_event) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_event_MASK) | (packer_send_event << SC_DEBUG_11_packer_send_event_SHIFT) +#define SC_DEBUG_11_SET_next_state(sc_debug_11_reg, next_state) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_next_state_MASK) | (next_state << SC_DEBUG_11_next_state_SHIFT) +#define SC_DEBUG_11_SET_state(sc_debug_11_reg, state) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_state_MASK) | (state << SC_DEBUG_11_state_SHIFT) +#define SC_DEBUG_11_SET_stall(sc_debug_11_reg, stall) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_stall_MASK) | (stall << SC_DEBUG_11_stall_SHIFT) +#define SC_DEBUG_11_SET_trigger(sc_debug_11_reg, trigger) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_trigger_MASK) | (trigger << SC_DEBUG_11_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_11_t { + unsigned int ez_sample_data_ready : SC_DEBUG_11_ez_sample_data_ready_SIZE; + unsigned int pkr_fetch_new_sample_data : SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE; + unsigned int ez_prim_data_ready : SC_DEBUG_11_ez_prim_data_ready_SIZE; + unsigned int pkr_fetch_new_prim_data : SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE; + unsigned int iterator_input_fz : SC_DEBUG_11_iterator_input_fz_SIZE; + unsigned int packer_send_quads : SC_DEBUG_11_packer_send_quads_SIZE; + unsigned int packer_send_cmd : SC_DEBUG_11_packer_send_cmd_SIZE; + unsigned int packer_send_event : SC_DEBUG_11_packer_send_event_SIZE; + unsigned int next_state : SC_DEBUG_11_next_state_SIZE; + unsigned int state : SC_DEBUG_11_state_SIZE; + unsigned int stall : SC_DEBUG_11_stall_SIZE; + unsigned int : 16; + unsigned int trigger : SC_DEBUG_11_trigger_SIZE; + } sc_debug_11_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_11_t { + unsigned int trigger : SC_DEBUG_11_trigger_SIZE; + unsigned int : 16; + unsigned int stall : SC_DEBUG_11_stall_SIZE; + unsigned int state : SC_DEBUG_11_state_SIZE; + unsigned int next_state : SC_DEBUG_11_next_state_SIZE; + unsigned int packer_send_event : SC_DEBUG_11_packer_send_event_SIZE; + unsigned int packer_send_cmd : SC_DEBUG_11_packer_send_cmd_SIZE; + unsigned int packer_send_quads : SC_DEBUG_11_packer_send_quads_SIZE; + unsigned int iterator_input_fz : SC_DEBUG_11_iterator_input_fz_SIZE; + unsigned int pkr_fetch_new_prim_data : SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE; + unsigned int ez_prim_data_ready : SC_DEBUG_11_ez_prim_data_ready_SIZE; + unsigned int pkr_fetch_new_sample_data : SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE; + unsigned int ez_sample_data_ready : SC_DEBUG_11_ez_sample_data_ready_SIZE; + } sc_debug_11_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_11_t f; +} sc_debug_11_u; + + +/* + * SC_DEBUG_12 struct + */ + +#define SC_DEBUG_12_SQ_iterator_free_buff_SIZE 1 +#define SC_DEBUG_12_event_id_SIZE 5 +#define SC_DEBUG_12_event_flag_SIZE 1 +#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE 1 +#define SC_DEBUG_12_itercmdfifo_full_SIZE 1 +#define SC_DEBUG_12_itercmdfifo_empty_SIZE 1 +#define SC_DEBUG_12_iter_ds_one_clk_command_SIZE 1 +#define SC_DEBUG_12_iter_ds_end_of_prim0_SIZE 1 +#define SC_DEBUG_12_iter_ds_end_of_vector_SIZE 1 +#define SC_DEBUG_12_iter_qdhit0_SIZE 1 +#define SC_DEBUG_12_bc_use_centers_reg_SIZE 1 +#define SC_DEBUG_12_bc_output_xy_reg_SIZE 1 +#define SC_DEBUG_12_iter_phase_out_SIZE 2 +#define SC_DEBUG_12_iter_phase_reg_SIZE 2 +#define SC_DEBUG_12_iterator_SP_valid_SIZE 1 +#define SC_DEBUG_12_eopv_reg_SIZE 1 +#define SC_DEBUG_12_one_clk_cmd_reg_SIZE 1 +#define SC_DEBUG_12_iter_dx_end_of_prim_SIZE 1 +#define SC_DEBUG_12_trigger_SIZE 1 + +#define SC_DEBUG_12_SQ_iterator_free_buff_SHIFT 0 +#define SC_DEBUG_12_event_id_SHIFT 1 +#define SC_DEBUG_12_event_flag_SHIFT 6 +#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT 7 +#define SC_DEBUG_12_itercmdfifo_full_SHIFT 8 +#define SC_DEBUG_12_itercmdfifo_empty_SHIFT 9 +#define SC_DEBUG_12_iter_ds_one_clk_command_SHIFT 10 +#define SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT 11 +#define SC_DEBUG_12_iter_ds_end_of_vector_SHIFT 12 +#define SC_DEBUG_12_iter_qdhit0_SHIFT 13 +#define SC_DEBUG_12_bc_use_centers_reg_SHIFT 14 +#define SC_DEBUG_12_bc_output_xy_reg_SHIFT 15 +#define SC_DEBUG_12_iter_phase_out_SHIFT 16 +#define SC_DEBUG_12_iter_phase_reg_SHIFT 18 +#define SC_DEBUG_12_iterator_SP_valid_SHIFT 20 +#define SC_DEBUG_12_eopv_reg_SHIFT 21 +#define SC_DEBUG_12_one_clk_cmd_reg_SHIFT 22 +#define SC_DEBUG_12_iter_dx_end_of_prim_SHIFT 23 +#define SC_DEBUG_12_trigger_SHIFT 31 + +#define SC_DEBUG_12_SQ_iterator_free_buff_MASK 0x00000001 +#define SC_DEBUG_12_event_id_MASK 0x0000003e +#define SC_DEBUG_12_event_flag_MASK 0x00000040 +#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK 0x00000080 +#define SC_DEBUG_12_itercmdfifo_full_MASK 0x00000100 +#define SC_DEBUG_12_itercmdfifo_empty_MASK 0x00000200 +#define SC_DEBUG_12_iter_ds_one_clk_command_MASK 0x00000400 +#define SC_DEBUG_12_iter_ds_end_of_prim0_MASK 0x00000800 +#define SC_DEBUG_12_iter_ds_end_of_vector_MASK 0x00001000 +#define SC_DEBUG_12_iter_qdhit0_MASK 0x00002000 +#define SC_DEBUG_12_bc_use_centers_reg_MASK 0x00004000 +#define SC_DEBUG_12_bc_output_xy_reg_MASK 0x00008000 +#define SC_DEBUG_12_iter_phase_out_MASK 0x00030000 +#define SC_DEBUG_12_iter_phase_reg_MASK 0x000c0000 +#define SC_DEBUG_12_iterator_SP_valid_MASK 0x00100000 +#define SC_DEBUG_12_eopv_reg_MASK 0x00200000 +#define SC_DEBUG_12_one_clk_cmd_reg_MASK 0x00400000 +#define SC_DEBUG_12_iter_dx_end_of_prim_MASK 0x00800000 +#define SC_DEBUG_12_trigger_MASK 0x80000000 + +#define SC_DEBUG_12_MASK \ + (SC_DEBUG_12_SQ_iterator_free_buff_MASK | \ + SC_DEBUG_12_event_id_MASK | \ + SC_DEBUG_12_event_flag_MASK | \ + SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK | \ + SC_DEBUG_12_itercmdfifo_full_MASK | \ + SC_DEBUG_12_itercmdfifo_empty_MASK | \ + SC_DEBUG_12_iter_ds_one_clk_command_MASK | \ + SC_DEBUG_12_iter_ds_end_of_prim0_MASK | \ + SC_DEBUG_12_iter_ds_end_of_vector_MASK | \ + SC_DEBUG_12_iter_qdhit0_MASK | \ + SC_DEBUG_12_bc_use_centers_reg_MASK | \ + SC_DEBUG_12_bc_output_xy_reg_MASK | \ + SC_DEBUG_12_iter_phase_out_MASK | \ + SC_DEBUG_12_iter_phase_reg_MASK | \ + SC_DEBUG_12_iterator_SP_valid_MASK | \ + SC_DEBUG_12_eopv_reg_MASK | \ + SC_DEBUG_12_one_clk_cmd_reg_MASK | \ + SC_DEBUG_12_iter_dx_end_of_prim_MASK | \ + SC_DEBUG_12_trigger_MASK) + +#define SC_DEBUG_12(sq_iterator_free_buff, event_id, event_flag, itercmdfifo_busy_nc_dly, itercmdfifo_full, itercmdfifo_empty, iter_ds_one_clk_command, iter_ds_end_of_prim0, iter_ds_end_of_vector, iter_qdhit0, bc_use_centers_reg, bc_output_xy_reg, iter_phase_out, iter_phase_reg, iterator_sp_valid, eopv_reg, one_clk_cmd_reg, iter_dx_end_of_prim, trigger) \ + ((sq_iterator_free_buff << SC_DEBUG_12_SQ_iterator_free_buff_SHIFT) | \ + (event_id << SC_DEBUG_12_event_id_SHIFT) | \ + (event_flag << SC_DEBUG_12_event_flag_SHIFT) | \ + (itercmdfifo_busy_nc_dly << SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT) | \ + (itercmdfifo_full << SC_DEBUG_12_itercmdfifo_full_SHIFT) | \ + (itercmdfifo_empty << SC_DEBUG_12_itercmdfifo_empty_SHIFT) | \ + (iter_ds_one_clk_command << SC_DEBUG_12_iter_ds_one_clk_command_SHIFT) | \ + (iter_ds_end_of_prim0 << SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT) | \ + (iter_ds_end_of_vector << SC_DEBUG_12_iter_ds_end_of_vector_SHIFT) | \ + (iter_qdhit0 << SC_DEBUG_12_iter_qdhit0_SHIFT) | \ + (bc_use_centers_reg << SC_DEBUG_12_bc_use_centers_reg_SHIFT) | \ + (bc_output_xy_reg << SC_DEBUG_12_bc_output_xy_reg_SHIFT) | \ + (iter_phase_out << SC_DEBUG_12_iter_phase_out_SHIFT) | \ + (iter_phase_reg << SC_DEBUG_12_iter_phase_reg_SHIFT) | \ + (iterator_sp_valid << SC_DEBUG_12_iterator_SP_valid_SHIFT) | \ + (eopv_reg << SC_DEBUG_12_eopv_reg_SHIFT) | \ + (one_clk_cmd_reg << SC_DEBUG_12_one_clk_cmd_reg_SHIFT) | \ + (iter_dx_end_of_prim << SC_DEBUG_12_iter_dx_end_of_prim_SHIFT) | \ + (trigger << SC_DEBUG_12_trigger_SHIFT)) + +#define SC_DEBUG_12_GET_SQ_iterator_free_buff(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_SQ_iterator_free_buff_MASK) >> SC_DEBUG_12_SQ_iterator_free_buff_SHIFT) +#define SC_DEBUG_12_GET_event_id(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_event_id_MASK) >> SC_DEBUG_12_event_id_SHIFT) +#define SC_DEBUG_12_GET_event_flag(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_event_flag_MASK) >> SC_DEBUG_12_event_flag_SHIFT) +#define SC_DEBUG_12_GET_itercmdfifo_busy_nc_dly(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK) >> SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT) +#define SC_DEBUG_12_GET_itercmdfifo_full(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_full_MASK) >> SC_DEBUG_12_itercmdfifo_full_SHIFT) +#define SC_DEBUG_12_GET_itercmdfifo_empty(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_empty_MASK) >> SC_DEBUG_12_itercmdfifo_empty_SHIFT) +#define SC_DEBUG_12_GET_iter_ds_one_clk_command(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_ds_one_clk_command_MASK) >> SC_DEBUG_12_iter_ds_one_clk_command_SHIFT) +#define SC_DEBUG_12_GET_iter_ds_end_of_prim0(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_ds_end_of_prim0_MASK) >> SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT) +#define SC_DEBUG_12_GET_iter_ds_end_of_vector(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_ds_end_of_vector_MASK) >> SC_DEBUG_12_iter_ds_end_of_vector_SHIFT) +#define SC_DEBUG_12_GET_iter_qdhit0(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_qdhit0_MASK) >> SC_DEBUG_12_iter_qdhit0_SHIFT) +#define SC_DEBUG_12_GET_bc_use_centers_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_bc_use_centers_reg_MASK) >> SC_DEBUG_12_bc_use_centers_reg_SHIFT) +#define SC_DEBUG_12_GET_bc_output_xy_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_bc_output_xy_reg_MASK) >> SC_DEBUG_12_bc_output_xy_reg_SHIFT) +#define SC_DEBUG_12_GET_iter_phase_out(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_phase_out_MASK) >> SC_DEBUG_12_iter_phase_out_SHIFT) +#define SC_DEBUG_12_GET_iter_phase_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_phase_reg_MASK) >> SC_DEBUG_12_iter_phase_reg_SHIFT) +#define SC_DEBUG_12_GET_iterator_SP_valid(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iterator_SP_valid_MASK) >> SC_DEBUG_12_iterator_SP_valid_SHIFT) +#define SC_DEBUG_12_GET_eopv_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_eopv_reg_MASK) >> SC_DEBUG_12_eopv_reg_SHIFT) +#define SC_DEBUG_12_GET_one_clk_cmd_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_one_clk_cmd_reg_MASK) >> SC_DEBUG_12_one_clk_cmd_reg_SHIFT) +#define SC_DEBUG_12_GET_iter_dx_end_of_prim(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_dx_end_of_prim_MASK) >> SC_DEBUG_12_iter_dx_end_of_prim_SHIFT) +#define SC_DEBUG_12_GET_trigger(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_trigger_MASK) >> SC_DEBUG_12_trigger_SHIFT) + +#define SC_DEBUG_12_SET_SQ_iterator_free_buff(sc_debug_12_reg, sq_iterator_free_buff) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_SQ_iterator_free_buff_MASK) | (sq_iterator_free_buff << SC_DEBUG_12_SQ_iterator_free_buff_SHIFT) +#define SC_DEBUG_12_SET_event_id(sc_debug_12_reg, event_id) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_event_id_MASK) | (event_id << SC_DEBUG_12_event_id_SHIFT) +#define SC_DEBUG_12_SET_event_flag(sc_debug_12_reg, event_flag) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_event_flag_MASK) | (event_flag << SC_DEBUG_12_event_flag_SHIFT) +#define SC_DEBUG_12_SET_itercmdfifo_busy_nc_dly(sc_debug_12_reg, itercmdfifo_busy_nc_dly) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK) | (itercmdfifo_busy_nc_dly << SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT) +#define SC_DEBUG_12_SET_itercmdfifo_full(sc_debug_12_reg, itercmdfifo_full) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_full_MASK) | (itercmdfifo_full << SC_DEBUG_12_itercmdfifo_full_SHIFT) +#define SC_DEBUG_12_SET_itercmdfifo_empty(sc_debug_12_reg, itercmdfifo_empty) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_empty_MASK) | (itercmdfifo_empty << SC_DEBUG_12_itercmdfifo_empty_SHIFT) +#define SC_DEBUG_12_SET_iter_ds_one_clk_command(sc_debug_12_reg, iter_ds_one_clk_command) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_one_clk_command_MASK) | (iter_ds_one_clk_command << SC_DEBUG_12_iter_ds_one_clk_command_SHIFT) +#define SC_DEBUG_12_SET_iter_ds_end_of_prim0(sc_debug_12_reg, iter_ds_end_of_prim0) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_end_of_prim0_MASK) | (iter_ds_end_of_prim0 << SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT) +#define SC_DEBUG_12_SET_iter_ds_end_of_vector(sc_debug_12_reg, iter_ds_end_of_vector) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_end_of_vector_MASK) | (iter_ds_end_of_vector << SC_DEBUG_12_iter_ds_end_of_vector_SHIFT) +#define SC_DEBUG_12_SET_iter_qdhit0(sc_debug_12_reg, iter_qdhit0) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_qdhit0_MASK) | (iter_qdhit0 << SC_DEBUG_12_iter_qdhit0_SHIFT) +#define SC_DEBUG_12_SET_bc_use_centers_reg(sc_debug_12_reg, bc_use_centers_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_bc_use_centers_reg_MASK) | (bc_use_centers_reg << SC_DEBUG_12_bc_use_centers_reg_SHIFT) +#define SC_DEBUG_12_SET_bc_output_xy_reg(sc_debug_12_reg, bc_output_xy_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_bc_output_xy_reg_MASK) | (bc_output_xy_reg << SC_DEBUG_12_bc_output_xy_reg_SHIFT) +#define SC_DEBUG_12_SET_iter_phase_out(sc_debug_12_reg, iter_phase_out) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_phase_out_MASK) | (iter_phase_out << SC_DEBUG_12_iter_phase_out_SHIFT) +#define SC_DEBUG_12_SET_iter_phase_reg(sc_debug_12_reg, iter_phase_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_phase_reg_MASK) | (iter_phase_reg << SC_DEBUG_12_iter_phase_reg_SHIFT) +#define SC_DEBUG_12_SET_iterator_SP_valid(sc_debug_12_reg, iterator_sp_valid) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iterator_SP_valid_MASK) | (iterator_sp_valid << SC_DEBUG_12_iterator_SP_valid_SHIFT) +#define SC_DEBUG_12_SET_eopv_reg(sc_debug_12_reg, eopv_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_eopv_reg_MASK) | (eopv_reg << SC_DEBUG_12_eopv_reg_SHIFT) +#define SC_DEBUG_12_SET_one_clk_cmd_reg(sc_debug_12_reg, one_clk_cmd_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_one_clk_cmd_reg_MASK) | (one_clk_cmd_reg << SC_DEBUG_12_one_clk_cmd_reg_SHIFT) +#define SC_DEBUG_12_SET_iter_dx_end_of_prim(sc_debug_12_reg, iter_dx_end_of_prim) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_dx_end_of_prim_MASK) | (iter_dx_end_of_prim << SC_DEBUG_12_iter_dx_end_of_prim_SHIFT) +#define SC_DEBUG_12_SET_trigger(sc_debug_12_reg, trigger) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_trigger_MASK) | (trigger << SC_DEBUG_12_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_12_t { + unsigned int sq_iterator_free_buff : SC_DEBUG_12_SQ_iterator_free_buff_SIZE; + unsigned int event_id : SC_DEBUG_12_event_id_SIZE; + unsigned int event_flag : SC_DEBUG_12_event_flag_SIZE; + unsigned int itercmdfifo_busy_nc_dly : SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE; + unsigned int itercmdfifo_full : SC_DEBUG_12_itercmdfifo_full_SIZE; + unsigned int itercmdfifo_empty : SC_DEBUG_12_itercmdfifo_empty_SIZE; + unsigned int iter_ds_one_clk_command : SC_DEBUG_12_iter_ds_one_clk_command_SIZE; + unsigned int iter_ds_end_of_prim0 : SC_DEBUG_12_iter_ds_end_of_prim0_SIZE; + unsigned int iter_ds_end_of_vector : SC_DEBUG_12_iter_ds_end_of_vector_SIZE; + unsigned int iter_qdhit0 : SC_DEBUG_12_iter_qdhit0_SIZE; + unsigned int bc_use_centers_reg : SC_DEBUG_12_bc_use_centers_reg_SIZE; + unsigned int bc_output_xy_reg : SC_DEBUG_12_bc_output_xy_reg_SIZE; + unsigned int iter_phase_out : SC_DEBUG_12_iter_phase_out_SIZE; + unsigned int iter_phase_reg : SC_DEBUG_12_iter_phase_reg_SIZE; + unsigned int iterator_sp_valid : SC_DEBUG_12_iterator_SP_valid_SIZE; + unsigned int eopv_reg : SC_DEBUG_12_eopv_reg_SIZE; + unsigned int one_clk_cmd_reg : SC_DEBUG_12_one_clk_cmd_reg_SIZE; + unsigned int iter_dx_end_of_prim : SC_DEBUG_12_iter_dx_end_of_prim_SIZE; + unsigned int : 7; + unsigned int trigger : SC_DEBUG_12_trigger_SIZE; + } sc_debug_12_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_12_t { + unsigned int trigger : SC_DEBUG_12_trigger_SIZE; + unsigned int : 7; + unsigned int iter_dx_end_of_prim : SC_DEBUG_12_iter_dx_end_of_prim_SIZE; + unsigned int one_clk_cmd_reg : SC_DEBUG_12_one_clk_cmd_reg_SIZE; + unsigned int eopv_reg : SC_DEBUG_12_eopv_reg_SIZE; + unsigned int iterator_sp_valid : SC_DEBUG_12_iterator_SP_valid_SIZE; + unsigned int iter_phase_reg : SC_DEBUG_12_iter_phase_reg_SIZE; + unsigned int iter_phase_out : SC_DEBUG_12_iter_phase_out_SIZE; + unsigned int bc_output_xy_reg : SC_DEBUG_12_bc_output_xy_reg_SIZE; + unsigned int bc_use_centers_reg : SC_DEBUG_12_bc_use_centers_reg_SIZE; + unsigned int iter_qdhit0 : SC_DEBUG_12_iter_qdhit0_SIZE; + unsigned int iter_ds_end_of_vector : SC_DEBUG_12_iter_ds_end_of_vector_SIZE; + unsigned int iter_ds_end_of_prim0 : SC_DEBUG_12_iter_ds_end_of_prim0_SIZE; + unsigned int iter_ds_one_clk_command : SC_DEBUG_12_iter_ds_one_clk_command_SIZE; + unsigned int itercmdfifo_empty : SC_DEBUG_12_itercmdfifo_empty_SIZE; + unsigned int itercmdfifo_full : SC_DEBUG_12_itercmdfifo_full_SIZE; + unsigned int itercmdfifo_busy_nc_dly : SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE; + unsigned int event_flag : SC_DEBUG_12_event_flag_SIZE; + unsigned int event_id : SC_DEBUG_12_event_id_SIZE; + unsigned int sq_iterator_free_buff : SC_DEBUG_12_SQ_iterator_free_buff_SIZE; + } sc_debug_12_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_12_t f; +} sc_debug_12_u; + + +#endif + + +#if !defined (_VGT_FIDDLE_H) +#define _VGT_FIDDLE_H + +/***************************************************************************************************************** + * + * vgt_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + +/* + * VGT_OUT_PRIM_TYPE enum + */ + +#define VGT_OUT_POINT 0x00000000 +#define VGT_OUT_LINE 0x00000001 +#define VGT_OUT_TRI 0x00000002 +#define VGT_OUT_RECT_V0 0x00000003 +#define VGT_OUT_RECT_V1 0x00000004 +#define VGT_OUT_RECT_V2 0x00000005 +#define VGT_OUT_RECT_V3 0x00000006 +#define VGT_OUT_RESERVED 0x00000007 +#define VGT_TE_QUAD 0x00000008 +#define VGT_TE_PRIM_INDEX_LINE 0x00000009 +#define VGT_TE_PRIM_INDEX_TRI 0x0000000a +#define VGT_TE_PRIM_INDEX_QUAD 0x0000000b + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * GFX_COPY_STATE struct + */ + +#define GFX_COPY_STATE_SRC_STATE_ID_SIZE 1 + +#define GFX_COPY_STATE_SRC_STATE_ID_SHIFT 0 + +#define GFX_COPY_STATE_SRC_STATE_ID_MASK 0x00000001 + +#define GFX_COPY_STATE_MASK \ + (GFX_COPY_STATE_SRC_STATE_ID_MASK) + +#define GFX_COPY_STATE(src_state_id) \ + ((src_state_id << GFX_COPY_STATE_SRC_STATE_ID_SHIFT)) + +#define GFX_COPY_STATE_GET_SRC_STATE_ID(gfx_copy_state) \ + ((gfx_copy_state & GFX_COPY_STATE_SRC_STATE_ID_MASK) >> GFX_COPY_STATE_SRC_STATE_ID_SHIFT) + +#define GFX_COPY_STATE_SET_SRC_STATE_ID(gfx_copy_state_reg, src_state_id) \ + gfx_copy_state_reg = (gfx_copy_state_reg & ~GFX_COPY_STATE_SRC_STATE_ID_MASK) | (src_state_id << GFX_COPY_STATE_SRC_STATE_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _gfx_copy_state_t { + unsigned int src_state_id : GFX_COPY_STATE_SRC_STATE_ID_SIZE; + unsigned int : 31; + } gfx_copy_state_t; + +#else // !BIGENDIAN_OS + + typedef struct _gfx_copy_state_t { + unsigned int : 31; + unsigned int src_state_id : GFX_COPY_STATE_SRC_STATE_ID_SIZE; + } gfx_copy_state_t; + +#endif + +typedef union { + unsigned int val : 32; + gfx_copy_state_t f; +} gfx_copy_state_u; + + +/* + * VGT_DRAW_INITIATOR struct + */ + +#define VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE 6 +#define VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE 2 +#define VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SIZE 2 +#define VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE 1 +#define VGT_DRAW_INITIATOR_NOT_EOP_SIZE 1 +#define VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE 1 +#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE 1 +#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE 1 +#define VGT_DRAW_INITIATOR_NUM_INDICES_SIZE 16 + +#define VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT 0 +#define VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT 6 +#define VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT 8 +#define VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT 11 +#define VGT_DRAW_INITIATOR_NOT_EOP_SHIFT 12 +#define VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT 13 +#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT 14 +#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT 15 +#define VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT 16 + +#define VGT_DRAW_INITIATOR_PRIM_TYPE_MASK 0x0000003f +#define VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK 0x000000c0 +#define VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK 0x00000300 +#define VGT_DRAW_INITIATOR_INDEX_SIZE_MASK 0x00000800 +#define VGT_DRAW_INITIATOR_NOT_EOP_MASK 0x00001000 +#define VGT_DRAW_INITIATOR_SMALL_INDEX_MASK 0x00002000 +#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK 0x00004000 +#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK 0x00008000 +#define VGT_DRAW_INITIATOR_NUM_INDICES_MASK 0xffff0000 + +#define VGT_DRAW_INITIATOR_MASK \ + (VGT_DRAW_INITIATOR_PRIM_TYPE_MASK | \ + VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK | \ + VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK | \ + VGT_DRAW_INITIATOR_INDEX_SIZE_MASK | \ + VGT_DRAW_INITIATOR_NOT_EOP_MASK | \ + VGT_DRAW_INITIATOR_SMALL_INDEX_MASK | \ + VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK | \ + VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK | \ + VGT_DRAW_INITIATOR_NUM_INDICES_MASK) + +#define VGT_DRAW_INITIATOR(prim_type, source_select, faceness_cull_select, index_size, not_eop, small_index, pre_fetch_cull_enable, grp_cull_enable, num_indices) \ + ((prim_type << VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT) | \ + (source_select << VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT) | \ + (faceness_cull_select << VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT) | \ + (index_size << VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT) | \ + (not_eop << VGT_DRAW_INITIATOR_NOT_EOP_SHIFT) | \ + (small_index << VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT) | \ + (pre_fetch_cull_enable << VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT) | \ + (grp_cull_enable << VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT) | \ + (num_indices << VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT)) + +#define VGT_DRAW_INITIATOR_GET_PRIM_TYPE(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_PRIM_TYPE_MASK) >> VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT) +#define VGT_DRAW_INITIATOR_GET_SOURCE_SELECT(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK) >> VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT) +#define VGT_DRAW_INITIATOR_GET_FACENESS_CULL_SELECT(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK) >> VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT) +#define VGT_DRAW_INITIATOR_GET_INDEX_SIZE(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_INDEX_SIZE_MASK) >> VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT) +#define VGT_DRAW_INITIATOR_GET_NOT_EOP(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_NOT_EOP_MASK) >> VGT_DRAW_INITIATOR_NOT_EOP_SHIFT) +#define VGT_DRAW_INITIATOR_GET_SMALL_INDEX(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_SMALL_INDEX_MASK) >> VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT) +#define VGT_DRAW_INITIATOR_GET_PRE_FETCH_CULL_ENABLE(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK) >> VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT) +#define VGT_DRAW_INITIATOR_GET_GRP_CULL_ENABLE(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK) >> VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT) +#define VGT_DRAW_INITIATOR_GET_NUM_INDICES(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_NUM_INDICES_MASK) >> VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT) + +#define VGT_DRAW_INITIATOR_SET_PRIM_TYPE(vgt_draw_initiator_reg, prim_type) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_PRIM_TYPE_MASK) | (prim_type << VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT) +#define VGT_DRAW_INITIATOR_SET_SOURCE_SELECT(vgt_draw_initiator_reg, source_select) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK) | (source_select << VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT) +#define VGT_DRAW_INITIATOR_SET_FACENESS_CULL_SELECT(vgt_draw_initiator_reg, faceness_cull_select) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK) | (faceness_cull_select << VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT) +#define VGT_DRAW_INITIATOR_SET_INDEX_SIZE(vgt_draw_initiator_reg, index_size) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_INDEX_SIZE_MASK) | (index_size << VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT) +#define VGT_DRAW_INITIATOR_SET_NOT_EOP(vgt_draw_initiator_reg, not_eop) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_NOT_EOP_MASK) | (not_eop << VGT_DRAW_INITIATOR_NOT_EOP_SHIFT) +#define VGT_DRAW_INITIATOR_SET_SMALL_INDEX(vgt_draw_initiator_reg, small_index) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_SMALL_INDEX_MASK) | (small_index << VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT) +#define VGT_DRAW_INITIATOR_SET_PRE_FETCH_CULL_ENABLE(vgt_draw_initiator_reg, pre_fetch_cull_enable) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK) | (pre_fetch_cull_enable << VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT) +#define VGT_DRAW_INITIATOR_SET_GRP_CULL_ENABLE(vgt_draw_initiator_reg, grp_cull_enable) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK) | (grp_cull_enable << VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT) +#define VGT_DRAW_INITIATOR_SET_NUM_INDICES(vgt_draw_initiator_reg, num_indices) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_NUM_INDICES_MASK) | (num_indices << VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_draw_initiator_t { + unsigned int prim_type : VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE; + unsigned int source_select : VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE; + unsigned int faceness_cull_select : VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SIZE; + unsigned int : 1; + unsigned int index_size : VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE; + unsigned int not_eop : VGT_DRAW_INITIATOR_NOT_EOP_SIZE; + unsigned int small_index : VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE; + unsigned int pre_fetch_cull_enable : VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE; + unsigned int grp_cull_enable : VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE; + unsigned int num_indices : VGT_DRAW_INITIATOR_NUM_INDICES_SIZE; + } vgt_draw_initiator_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_draw_initiator_t { + unsigned int num_indices : VGT_DRAW_INITIATOR_NUM_INDICES_SIZE; + unsigned int grp_cull_enable : VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE; + unsigned int pre_fetch_cull_enable : VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE; + unsigned int small_index : VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE; + unsigned int not_eop : VGT_DRAW_INITIATOR_NOT_EOP_SIZE; + unsigned int index_size : VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE; + unsigned int : 1; + unsigned int faceness_cull_select : VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SIZE; + unsigned int source_select : VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE; + unsigned int prim_type : VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE; + } vgt_draw_initiator_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_draw_initiator_t f; +} vgt_draw_initiator_u; + + +/* + * VGT_EVENT_INITIATOR struct + */ + +#define VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE 6 + +#define VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT 0 + +#define VGT_EVENT_INITIATOR_EVENT_TYPE_MASK 0x0000003f + +#define VGT_EVENT_INITIATOR_MASK \ + (VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) + +#define VGT_EVENT_INITIATOR(event_type) \ + ((event_type << VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT)) + +#define VGT_EVENT_INITIATOR_GET_EVENT_TYPE(vgt_event_initiator) \ + ((vgt_event_initiator & VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) >> VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT) + +#define VGT_EVENT_INITIATOR_SET_EVENT_TYPE(vgt_event_initiator_reg, event_type) \ + vgt_event_initiator_reg = (vgt_event_initiator_reg & ~VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) | (event_type << VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_event_initiator_t { + unsigned int event_type : VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE; + unsigned int : 26; + } vgt_event_initiator_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_event_initiator_t { + unsigned int : 26; + unsigned int event_type : VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE; + } vgt_event_initiator_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_event_initiator_t f; +} vgt_event_initiator_u; + + +/* + * VGT_DMA_BASE struct + */ + +#define VGT_DMA_BASE_BASE_ADDR_SIZE 32 + +#define VGT_DMA_BASE_BASE_ADDR_SHIFT 0 + +#define VGT_DMA_BASE_BASE_ADDR_MASK 0xffffffff + +#define VGT_DMA_BASE_MASK \ + (VGT_DMA_BASE_BASE_ADDR_MASK) + +#define VGT_DMA_BASE(base_addr) \ + ((base_addr << VGT_DMA_BASE_BASE_ADDR_SHIFT)) + +#define VGT_DMA_BASE_GET_BASE_ADDR(vgt_dma_base) \ + ((vgt_dma_base & VGT_DMA_BASE_BASE_ADDR_MASK) >> VGT_DMA_BASE_BASE_ADDR_SHIFT) + +#define VGT_DMA_BASE_SET_BASE_ADDR(vgt_dma_base_reg, base_addr) \ + vgt_dma_base_reg = (vgt_dma_base_reg & ~VGT_DMA_BASE_BASE_ADDR_MASK) | (base_addr << VGT_DMA_BASE_BASE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_dma_base_t { + unsigned int base_addr : VGT_DMA_BASE_BASE_ADDR_SIZE; + } vgt_dma_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_dma_base_t { + unsigned int base_addr : VGT_DMA_BASE_BASE_ADDR_SIZE; + } vgt_dma_base_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_dma_base_t f; +} vgt_dma_base_u; + + +/* + * VGT_DMA_SIZE struct + */ + +#define VGT_DMA_SIZE_NUM_WORDS_SIZE 24 +#define VGT_DMA_SIZE_SWAP_MODE_SIZE 2 + +#define VGT_DMA_SIZE_NUM_WORDS_SHIFT 0 +#define VGT_DMA_SIZE_SWAP_MODE_SHIFT 30 + +#define VGT_DMA_SIZE_NUM_WORDS_MASK 0x00ffffff +#define VGT_DMA_SIZE_SWAP_MODE_MASK 0xc0000000 + +#define VGT_DMA_SIZE_MASK \ + (VGT_DMA_SIZE_NUM_WORDS_MASK | \ + VGT_DMA_SIZE_SWAP_MODE_MASK) + +#define VGT_DMA_SIZE(num_words, swap_mode) \ + ((num_words << VGT_DMA_SIZE_NUM_WORDS_SHIFT) | \ + (swap_mode << VGT_DMA_SIZE_SWAP_MODE_SHIFT)) + +#define VGT_DMA_SIZE_GET_NUM_WORDS(vgt_dma_size) \ + ((vgt_dma_size & VGT_DMA_SIZE_NUM_WORDS_MASK) >> VGT_DMA_SIZE_NUM_WORDS_SHIFT) +#define VGT_DMA_SIZE_GET_SWAP_MODE(vgt_dma_size) \ + ((vgt_dma_size & VGT_DMA_SIZE_SWAP_MODE_MASK) >> VGT_DMA_SIZE_SWAP_MODE_SHIFT) + +#define VGT_DMA_SIZE_SET_NUM_WORDS(vgt_dma_size_reg, num_words) \ + vgt_dma_size_reg = (vgt_dma_size_reg & ~VGT_DMA_SIZE_NUM_WORDS_MASK) | (num_words << VGT_DMA_SIZE_NUM_WORDS_SHIFT) +#define VGT_DMA_SIZE_SET_SWAP_MODE(vgt_dma_size_reg, swap_mode) \ + vgt_dma_size_reg = (vgt_dma_size_reg & ~VGT_DMA_SIZE_SWAP_MODE_MASK) | (swap_mode << VGT_DMA_SIZE_SWAP_MODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_dma_size_t { + unsigned int num_words : VGT_DMA_SIZE_NUM_WORDS_SIZE; + unsigned int : 6; + unsigned int swap_mode : VGT_DMA_SIZE_SWAP_MODE_SIZE; + } vgt_dma_size_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_dma_size_t { + unsigned int swap_mode : VGT_DMA_SIZE_SWAP_MODE_SIZE; + unsigned int : 6; + unsigned int num_words : VGT_DMA_SIZE_NUM_WORDS_SIZE; + } vgt_dma_size_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_dma_size_t f; +} vgt_dma_size_u; + + +/* + * VGT_BIN_BASE struct + */ + +#define VGT_BIN_BASE_BIN_BASE_ADDR_SIZE 32 + +#define VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT 0 + +#define VGT_BIN_BASE_BIN_BASE_ADDR_MASK 0xffffffff + +#define VGT_BIN_BASE_MASK \ + (VGT_BIN_BASE_BIN_BASE_ADDR_MASK) + +#define VGT_BIN_BASE(bin_base_addr) \ + ((bin_base_addr << VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT)) + +#define VGT_BIN_BASE_GET_BIN_BASE_ADDR(vgt_bin_base) \ + ((vgt_bin_base & VGT_BIN_BASE_BIN_BASE_ADDR_MASK) >> VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT) + +#define VGT_BIN_BASE_SET_BIN_BASE_ADDR(vgt_bin_base_reg, bin_base_addr) \ + vgt_bin_base_reg = (vgt_bin_base_reg & ~VGT_BIN_BASE_BIN_BASE_ADDR_MASK) | (bin_base_addr << VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_bin_base_t { + unsigned int bin_base_addr : VGT_BIN_BASE_BIN_BASE_ADDR_SIZE; + } vgt_bin_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_bin_base_t { + unsigned int bin_base_addr : VGT_BIN_BASE_BIN_BASE_ADDR_SIZE; + } vgt_bin_base_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_bin_base_t f; +} vgt_bin_base_u; + + +/* + * VGT_BIN_SIZE struct + */ + +#define VGT_BIN_SIZE_NUM_WORDS_SIZE 24 +#define VGT_BIN_SIZE_FACENESS_FETCH_SIZE 1 +#define VGT_BIN_SIZE_FACENESS_RESET_SIZE 1 + +#define VGT_BIN_SIZE_NUM_WORDS_SHIFT 0 +#define VGT_BIN_SIZE_FACENESS_FETCH_SHIFT 30 +#define VGT_BIN_SIZE_FACENESS_RESET_SHIFT 31 + +#define VGT_BIN_SIZE_NUM_WORDS_MASK 0x00ffffff +#define VGT_BIN_SIZE_FACENESS_FETCH_MASK 0x40000000 +#define VGT_BIN_SIZE_FACENESS_RESET_MASK 0x80000000 + +#define VGT_BIN_SIZE_MASK \ + (VGT_BIN_SIZE_NUM_WORDS_MASK | \ + VGT_BIN_SIZE_FACENESS_FETCH_MASK | \ + VGT_BIN_SIZE_FACENESS_RESET_MASK) + +#define VGT_BIN_SIZE(num_words, faceness_fetch, faceness_reset) \ + ((num_words << VGT_BIN_SIZE_NUM_WORDS_SHIFT) | \ + (faceness_fetch << VGT_BIN_SIZE_FACENESS_FETCH_SHIFT) | \ + (faceness_reset << VGT_BIN_SIZE_FACENESS_RESET_SHIFT)) + +#define VGT_BIN_SIZE_GET_NUM_WORDS(vgt_bin_size) \ + ((vgt_bin_size & VGT_BIN_SIZE_NUM_WORDS_MASK) >> VGT_BIN_SIZE_NUM_WORDS_SHIFT) +#define VGT_BIN_SIZE_GET_FACENESS_FETCH(vgt_bin_size) \ + ((vgt_bin_size & VGT_BIN_SIZE_FACENESS_FETCH_MASK) >> VGT_BIN_SIZE_FACENESS_FETCH_SHIFT) +#define VGT_BIN_SIZE_GET_FACENESS_RESET(vgt_bin_size) \ + ((vgt_bin_size & VGT_BIN_SIZE_FACENESS_RESET_MASK) >> VGT_BIN_SIZE_FACENESS_RESET_SHIFT) + +#define VGT_BIN_SIZE_SET_NUM_WORDS(vgt_bin_size_reg, num_words) \ + vgt_bin_size_reg = (vgt_bin_size_reg & ~VGT_BIN_SIZE_NUM_WORDS_MASK) | (num_words << VGT_BIN_SIZE_NUM_WORDS_SHIFT) +#define VGT_BIN_SIZE_SET_FACENESS_FETCH(vgt_bin_size_reg, faceness_fetch) \ + vgt_bin_size_reg = (vgt_bin_size_reg & ~VGT_BIN_SIZE_FACENESS_FETCH_MASK) | (faceness_fetch << VGT_BIN_SIZE_FACENESS_FETCH_SHIFT) +#define VGT_BIN_SIZE_SET_FACENESS_RESET(vgt_bin_size_reg, faceness_reset) \ + vgt_bin_size_reg = (vgt_bin_size_reg & ~VGT_BIN_SIZE_FACENESS_RESET_MASK) | (faceness_reset << VGT_BIN_SIZE_FACENESS_RESET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_bin_size_t { + unsigned int num_words : VGT_BIN_SIZE_NUM_WORDS_SIZE; + unsigned int : 6; + unsigned int faceness_fetch : VGT_BIN_SIZE_FACENESS_FETCH_SIZE; + unsigned int faceness_reset : VGT_BIN_SIZE_FACENESS_RESET_SIZE; + } vgt_bin_size_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_bin_size_t { + unsigned int faceness_reset : VGT_BIN_SIZE_FACENESS_RESET_SIZE; + unsigned int faceness_fetch : VGT_BIN_SIZE_FACENESS_FETCH_SIZE; + unsigned int : 6; + unsigned int num_words : VGT_BIN_SIZE_NUM_WORDS_SIZE; + } vgt_bin_size_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_bin_size_t f; +} vgt_bin_size_u; + + +/* + * VGT_CURRENT_BIN_ID_MIN struct + */ + +#define VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE 3 +#define VGT_CURRENT_BIN_ID_MIN_ROW_SIZE 3 +#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE 3 + +#define VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT 0 +#define VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT 3 +#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT 6 + +#define VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK 0x00000007 +#define VGT_CURRENT_BIN_ID_MIN_ROW_MASK 0x00000038 +#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK 0x000001c0 + +#define VGT_CURRENT_BIN_ID_MIN_MASK \ + (VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK | \ + VGT_CURRENT_BIN_ID_MIN_ROW_MASK | \ + VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) + +#define VGT_CURRENT_BIN_ID_MIN(column, row, guard_band) \ + ((column << VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT) | \ + (row << VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT) | \ + (guard_band << VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT)) + +#define VGT_CURRENT_BIN_ID_MIN_GET_COLUMN(vgt_current_bin_id_min) \ + ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK) >> VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT) +#define VGT_CURRENT_BIN_ID_MIN_GET_ROW(vgt_current_bin_id_min) \ + ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_ROW_MASK) >> VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT) +#define VGT_CURRENT_BIN_ID_MIN_GET_GUARD_BAND(vgt_current_bin_id_min) \ + ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) >> VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT) + +#define VGT_CURRENT_BIN_ID_MIN_SET_COLUMN(vgt_current_bin_id_min_reg, column) \ + vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK) | (column << VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT) +#define VGT_CURRENT_BIN_ID_MIN_SET_ROW(vgt_current_bin_id_min_reg, row) \ + vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_ROW_MASK) | (row << VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT) +#define VGT_CURRENT_BIN_ID_MIN_SET_GUARD_BAND(vgt_current_bin_id_min_reg, guard_band) \ + vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) | (guard_band << VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_current_bin_id_min_t { + unsigned int column : VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE; + unsigned int row : VGT_CURRENT_BIN_ID_MIN_ROW_SIZE; + unsigned int guard_band : VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE; + unsigned int : 23; + } vgt_current_bin_id_min_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_current_bin_id_min_t { + unsigned int : 23; + unsigned int guard_band : VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE; + unsigned int row : VGT_CURRENT_BIN_ID_MIN_ROW_SIZE; + unsigned int column : VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE; + } vgt_current_bin_id_min_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_current_bin_id_min_t f; +} vgt_current_bin_id_min_u; + + +/* + * VGT_CURRENT_BIN_ID_MAX struct + */ + +#define VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE 3 +#define VGT_CURRENT_BIN_ID_MAX_ROW_SIZE 3 +#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE 3 + +#define VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT 0 +#define VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT 3 +#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT 6 + +#define VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK 0x00000007 +#define VGT_CURRENT_BIN_ID_MAX_ROW_MASK 0x00000038 +#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK 0x000001c0 + +#define VGT_CURRENT_BIN_ID_MAX_MASK \ + (VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK | \ + VGT_CURRENT_BIN_ID_MAX_ROW_MASK | \ + VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) + +#define VGT_CURRENT_BIN_ID_MAX(column, row, guard_band) \ + ((column << VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT) | \ + (row << VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT) | \ + (guard_band << VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT)) + +#define VGT_CURRENT_BIN_ID_MAX_GET_COLUMN(vgt_current_bin_id_max) \ + ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK) >> VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT) +#define VGT_CURRENT_BIN_ID_MAX_GET_ROW(vgt_current_bin_id_max) \ + ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_ROW_MASK) >> VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT) +#define VGT_CURRENT_BIN_ID_MAX_GET_GUARD_BAND(vgt_current_bin_id_max) \ + ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) >> VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT) + +#define VGT_CURRENT_BIN_ID_MAX_SET_COLUMN(vgt_current_bin_id_max_reg, column) \ + vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK) | (column << VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT) +#define VGT_CURRENT_BIN_ID_MAX_SET_ROW(vgt_current_bin_id_max_reg, row) \ + vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_ROW_MASK) | (row << VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT) +#define VGT_CURRENT_BIN_ID_MAX_SET_GUARD_BAND(vgt_current_bin_id_max_reg, guard_band) \ + vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) | (guard_band << VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_current_bin_id_max_t { + unsigned int column : VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE; + unsigned int row : VGT_CURRENT_BIN_ID_MAX_ROW_SIZE; + unsigned int guard_band : VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE; + unsigned int : 23; + } vgt_current_bin_id_max_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_current_bin_id_max_t { + unsigned int : 23; + unsigned int guard_band : VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE; + unsigned int row : VGT_CURRENT_BIN_ID_MAX_ROW_SIZE; + unsigned int column : VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE; + } vgt_current_bin_id_max_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_current_bin_id_max_t f; +} vgt_current_bin_id_max_u; + + +/* + * VGT_IMMED_DATA struct + */ + +#define VGT_IMMED_DATA_DATA_SIZE 32 + +#define VGT_IMMED_DATA_DATA_SHIFT 0 + +#define VGT_IMMED_DATA_DATA_MASK 0xffffffff + +#define VGT_IMMED_DATA_MASK \ + (VGT_IMMED_DATA_DATA_MASK) + +#define VGT_IMMED_DATA(data) \ + ((data << VGT_IMMED_DATA_DATA_SHIFT)) + +#define VGT_IMMED_DATA_GET_DATA(vgt_immed_data) \ + ((vgt_immed_data & VGT_IMMED_DATA_DATA_MASK) >> VGT_IMMED_DATA_DATA_SHIFT) + +#define VGT_IMMED_DATA_SET_DATA(vgt_immed_data_reg, data) \ + vgt_immed_data_reg = (vgt_immed_data_reg & ~VGT_IMMED_DATA_DATA_MASK) | (data << VGT_IMMED_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_immed_data_t { + unsigned int data : VGT_IMMED_DATA_DATA_SIZE; + } vgt_immed_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_immed_data_t { + unsigned int data : VGT_IMMED_DATA_DATA_SIZE; + } vgt_immed_data_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_immed_data_t f; +} vgt_immed_data_u; + + +/* + * VGT_MAX_VTX_INDX struct + */ + +#define VGT_MAX_VTX_INDX_MAX_INDX_SIZE 24 + +#define VGT_MAX_VTX_INDX_MAX_INDX_SHIFT 0 + +#define VGT_MAX_VTX_INDX_MAX_INDX_MASK 0x00ffffff + +#define VGT_MAX_VTX_INDX_MASK \ + (VGT_MAX_VTX_INDX_MAX_INDX_MASK) + +#define VGT_MAX_VTX_INDX(max_indx) \ + ((max_indx << VGT_MAX_VTX_INDX_MAX_INDX_SHIFT)) + +#define VGT_MAX_VTX_INDX_GET_MAX_INDX(vgt_max_vtx_indx) \ + ((vgt_max_vtx_indx & VGT_MAX_VTX_INDX_MAX_INDX_MASK) >> VGT_MAX_VTX_INDX_MAX_INDX_SHIFT) + +#define VGT_MAX_VTX_INDX_SET_MAX_INDX(vgt_max_vtx_indx_reg, max_indx) \ + vgt_max_vtx_indx_reg = (vgt_max_vtx_indx_reg & ~VGT_MAX_VTX_INDX_MAX_INDX_MASK) | (max_indx << VGT_MAX_VTX_INDX_MAX_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_max_vtx_indx_t { + unsigned int max_indx : VGT_MAX_VTX_INDX_MAX_INDX_SIZE; + unsigned int : 8; + } vgt_max_vtx_indx_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_max_vtx_indx_t { + unsigned int : 8; + unsigned int max_indx : VGT_MAX_VTX_INDX_MAX_INDX_SIZE; + } vgt_max_vtx_indx_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_max_vtx_indx_t f; +} vgt_max_vtx_indx_u; + + +/* + * VGT_MIN_VTX_INDX struct + */ + +#define VGT_MIN_VTX_INDX_MIN_INDX_SIZE 24 + +#define VGT_MIN_VTX_INDX_MIN_INDX_SHIFT 0 + +#define VGT_MIN_VTX_INDX_MIN_INDX_MASK 0x00ffffff + +#define VGT_MIN_VTX_INDX_MASK \ + (VGT_MIN_VTX_INDX_MIN_INDX_MASK) + +#define VGT_MIN_VTX_INDX(min_indx) \ + ((min_indx << VGT_MIN_VTX_INDX_MIN_INDX_SHIFT)) + +#define VGT_MIN_VTX_INDX_GET_MIN_INDX(vgt_min_vtx_indx) \ + ((vgt_min_vtx_indx & VGT_MIN_VTX_INDX_MIN_INDX_MASK) >> VGT_MIN_VTX_INDX_MIN_INDX_SHIFT) + +#define VGT_MIN_VTX_INDX_SET_MIN_INDX(vgt_min_vtx_indx_reg, min_indx) \ + vgt_min_vtx_indx_reg = (vgt_min_vtx_indx_reg & ~VGT_MIN_VTX_INDX_MIN_INDX_MASK) | (min_indx << VGT_MIN_VTX_INDX_MIN_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_min_vtx_indx_t { + unsigned int min_indx : VGT_MIN_VTX_INDX_MIN_INDX_SIZE; + unsigned int : 8; + } vgt_min_vtx_indx_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_min_vtx_indx_t { + unsigned int : 8; + unsigned int min_indx : VGT_MIN_VTX_INDX_MIN_INDX_SIZE; + } vgt_min_vtx_indx_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_min_vtx_indx_t f; +} vgt_min_vtx_indx_u; + + +/* + * VGT_INDX_OFFSET struct + */ + +#define VGT_INDX_OFFSET_INDX_OFFSET_SIZE 24 + +#define VGT_INDX_OFFSET_INDX_OFFSET_SHIFT 0 + +#define VGT_INDX_OFFSET_INDX_OFFSET_MASK 0x00ffffff + +#define VGT_INDX_OFFSET_MASK \ + (VGT_INDX_OFFSET_INDX_OFFSET_MASK) + +#define VGT_INDX_OFFSET(indx_offset) \ + ((indx_offset << VGT_INDX_OFFSET_INDX_OFFSET_SHIFT)) + +#define VGT_INDX_OFFSET_GET_INDX_OFFSET(vgt_indx_offset) \ + ((vgt_indx_offset & VGT_INDX_OFFSET_INDX_OFFSET_MASK) >> VGT_INDX_OFFSET_INDX_OFFSET_SHIFT) + +#define VGT_INDX_OFFSET_SET_INDX_OFFSET(vgt_indx_offset_reg, indx_offset) \ + vgt_indx_offset_reg = (vgt_indx_offset_reg & ~VGT_INDX_OFFSET_INDX_OFFSET_MASK) | (indx_offset << VGT_INDX_OFFSET_INDX_OFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_indx_offset_t { + unsigned int indx_offset : VGT_INDX_OFFSET_INDX_OFFSET_SIZE; + unsigned int : 8; + } vgt_indx_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_indx_offset_t { + unsigned int : 8; + unsigned int indx_offset : VGT_INDX_OFFSET_INDX_OFFSET_SIZE; + } vgt_indx_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_indx_offset_t f; +} vgt_indx_offset_u; + + +/* + * VGT_VERTEX_REUSE_BLOCK_CNTL struct + */ + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE 3 + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT 0 + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK 0x00000007 + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_MASK \ + (VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) + +#define VGT_VERTEX_REUSE_BLOCK_CNTL(vtx_reuse_depth) \ + ((vtx_reuse_depth << VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT)) + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_GET_VTX_REUSE_DEPTH(vgt_vertex_reuse_block_cntl) \ + ((vgt_vertex_reuse_block_cntl & VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) >> VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT) + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_SET_VTX_REUSE_DEPTH(vgt_vertex_reuse_block_cntl_reg, vtx_reuse_depth) \ + vgt_vertex_reuse_block_cntl_reg = (vgt_vertex_reuse_block_cntl_reg & ~VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) | (vtx_reuse_depth << VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_vertex_reuse_block_cntl_t { + unsigned int vtx_reuse_depth : VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE; + unsigned int : 29; + } vgt_vertex_reuse_block_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_vertex_reuse_block_cntl_t { + unsigned int : 29; + unsigned int vtx_reuse_depth : VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE; + } vgt_vertex_reuse_block_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_vertex_reuse_block_cntl_t f; +} vgt_vertex_reuse_block_cntl_u; + + +/* + * VGT_OUT_DEALLOC_CNTL struct + */ + +#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE 2 + +#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT 0 + +#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK 0x00000003 + +#define VGT_OUT_DEALLOC_CNTL_MASK \ + (VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) + +#define VGT_OUT_DEALLOC_CNTL(dealloc_dist) \ + ((dealloc_dist << VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT)) + +#define VGT_OUT_DEALLOC_CNTL_GET_DEALLOC_DIST(vgt_out_dealloc_cntl) \ + ((vgt_out_dealloc_cntl & VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) >> VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT) + +#define VGT_OUT_DEALLOC_CNTL_SET_DEALLOC_DIST(vgt_out_dealloc_cntl_reg, dealloc_dist) \ + vgt_out_dealloc_cntl_reg = (vgt_out_dealloc_cntl_reg & ~VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) | (dealloc_dist << VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_out_dealloc_cntl_t { + unsigned int dealloc_dist : VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE; + unsigned int : 30; + } vgt_out_dealloc_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_out_dealloc_cntl_t { + unsigned int : 30; + unsigned int dealloc_dist : VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE; + } vgt_out_dealloc_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_out_dealloc_cntl_t f; +} vgt_out_dealloc_cntl_u; + + +/* + * VGT_MULTI_PRIM_IB_RESET_INDX struct + */ + +#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE 24 + +#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT 0 + +#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK 0x00ffffff + +#define VGT_MULTI_PRIM_IB_RESET_INDX_MASK \ + (VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) + +#define VGT_MULTI_PRIM_IB_RESET_INDX(reset_indx) \ + ((reset_indx << VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT)) + +#define VGT_MULTI_PRIM_IB_RESET_INDX_GET_RESET_INDX(vgt_multi_prim_ib_reset_indx) \ + ((vgt_multi_prim_ib_reset_indx & VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) >> VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT) + +#define VGT_MULTI_PRIM_IB_RESET_INDX_SET_RESET_INDX(vgt_multi_prim_ib_reset_indx_reg, reset_indx) \ + vgt_multi_prim_ib_reset_indx_reg = (vgt_multi_prim_ib_reset_indx_reg & ~VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) | (reset_indx << VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_multi_prim_ib_reset_indx_t { + unsigned int reset_indx : VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE; + unsigned int : 8; + } vgt_multi_prim_ib_reset_indx_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_multi_prim_ib_reset_indx_t { + unsigned int : 8; + unsigned int reset_indx : VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE; + } vgt_multi_prim_ib_reset_indx_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_multi_prim_ib_reset_indx_t f; +} vgt_multi_prim_ib_reset_indx_u; + + +/* + * VGT_ENHANCE struct + */ + +#define VGT_ENHANCE_MISC_SIZE 16 + +#define VGT_ENHANCE_MISC_SHIFT 0 + +#define VGT_ENHANCE_MISC_MASK 0x0000ffff + +#define VGT_ENHANCE_MASK \ + (VGT_ENHANCE_MISC_MASK) + +#define VGT_ENHANCE(misc) \ + ((misc << VGT_ENHANCE_MISC_SHIFT)) + +#define VGT_ENHANCE_GET_MISC(vgt_enhance) \ + ((vgt_enhance & VGT_ENHANCE_MISC_MASK) >> VGT_ENHANCE_MISC_SHIFT) + +#define VGT_ENHANCE_SET_MISC(vgt_enhance_reg, misc) \ + vgt_enhance_reg = (vgt_enhance_reg & ~VGT_ENHANCE_MISC_MASK) | (misc << VGT_ENHANCE_MISC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_enhance_t { + unsigned int misc : VGT_ENHANCE_MISC_SIZE; + unsigned int : 16; + } vgt_enhance_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_enhance_t { + unsigned int : 16; + unsigned int misc : VGT_ENHANCE_MISC_SIZE; + } vgt_enhance_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_enhance_t f; +} vgt_enhance_u; + + +/* + * VGT_VTX_VECT_EJECT_REG struct + */ + +#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE 5 + +#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT 0 + +#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK 0x0000001f + +#define VGT_VTX_VECT_EJECT_REG_MASK \ + (VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) + +#define VGT_VTX_VECT_EJECT_REG(prim_count) \ + ((prim_count << VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT)) + +#define VGT_VTX_VECT_EJECT_REG_GET_PRIM_COUNT(vgt_vtx_vect_eject_reg) \ + ((vgt_vtx_vect_eject_reg & VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) >> VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT) + +#define VGT_VTX_VECT_EJECT_REG_SET_PRIM_COUNT(vgt_vtx_vect_eject_reg_reg, prim_count) \ + vgt_vtx_vect_eject_reg_reg = (vgt_vtx_vect_eject_reg_reg & ~VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) | (prim_count << VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_vtx_vect_eject_reg_t { + unsigned int prim_count : VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE; + unsigned int : 27; + } vgt_vtx_vect_eject_reg_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_vtx_vect_eject_reg_t { + unsigned int : 27; + unsigned int prim_count : VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE; + } vgt_vtx_vect_eject_reg_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_vtx_vect_eject_reg_t f; +} vgt_vtx_vect_eject_reg_u; + + +/* + * VGT_LAST_COPY_STATE struct + */ + +#define VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE 1 +#define VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE 1 + +#define VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT 0 +#define VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT 16 + +#define VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK 0x00000001 +#define VGT_LAST_COPY_STATE_DST_STATE_ID_MASK 0x00010000 + +#define VGT_LAST_COPY_STATE_MASK \ + (VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK | \ + VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) + +#define VGT_LAST_COPY_STATE(src_state_id, dst_state_id) \ + ((src_state_id << VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT) | \ + (dst_state_id << VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT)) + +#define VGT_LAST_COPY_STATE_GET_SRC_STATE_ID(vgt_last_copy_state) \ + ((vgt_last_copy_state & VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK) >> VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT) +#define VGT_LAST_COPY_STATE_GET_DST_STATE_ID(vgt_last_copy_state) \ + ((vgt_last_copy_state & VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) >> VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT) + +#define VGT_LAST_COPY_STATE_SET_SRC_STATE_ID(vgt_last_copy_state_reg, src_state_id) \ + vgt_last_copy_state_reg = (vgt_last_copy_state_reg & ~VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK) | (src_state_id << VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT) +#define VGT_LAST_COPY_STATE_SET_DST_STATE_ID(vgt_last_copy_state_reg, dst_state_id) \ + vgt_last_copy_state_reg = (vgt_last_copy_state_reg & ~VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) | (dst_state_id << VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_last_copy_state_t { + unsigned int src_state_id : VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE; + unsigned int : 15; + unsigned int dst_state_id : VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE; + unsigned int : 15; + } vgt_last_copy_state_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_last_copy_state_t { + unsigned int : 15; + unsigned int dst_state_id : VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE; + unsigned int : 15; + unsigned int src_state_id : VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE; + } vgt_last_copy_state_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_last_copy_state_t f; +} vgt_last_copy_state_u; + + +/* + * VGT_DEBUG_CNTL struct + */ + +#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE 5 + +#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT 0 + +#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK 0x0000001f + +#define VGT_DEBUG_CNTL_MASK \ + (VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) + +#define VGT_DEBUG_CNTL(vgt_debug_indx) \ + ((vgt_debug_indx << VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT)) + +#define VGT_DEBUG_CNTL_GET_VGT_DEBUG_INDX(vgt_debug_cntl) \ + ((vgt_debug_cntl & VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) >> VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT) + +#define VGT_DEBUG_CNTL_SET_VGT_DEBUG_INDX(vgt_debug_cntl_reg, vgt_debug_indx) \ + vgt_debug_cntl_reg = (vgt_debug_cntl_reg & ~VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) | (vgt_debug_indx << VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_cntl_t { + unsigned int vgt_debug_indx : VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE; + unsigned int : 27; + } vgt_debug_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_cntl_t { + unsigned int : 27; + unsigned int vgt_debug_indx : VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE; + } vgt_debug_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_cntl_t f; +} vgt_debug_cntl_u; + + +/* + * VGT_DEBUG_DATA struct + */ + +#define VGT_DEBUG_DATA_DATA_SIZE 32 + +#define VGT_DEBUG_DATA_DATA_SHIFT 0 + +#define VGT_DEBUG_DATA_DATA_MASK 0xffffffff + +#define VGT_DEBUG_DATA_MASK \ + (VGT_DEBUG_DATA_DATA_MASK) + +#define VGT_DEBUG_DATA(data) \ + ((data << VGT_DEBUG_DATA_DATA_SHIFT)) + +#define VGT_DEBUG_DATA_GET_DATA(vgt_debug_data) \ + ((vgt_debug_data & VGT_DEBUG_DATA_DATA_MASK) >> VGT_DEBUG_DATA_DATA_SHIFT) + +#define VGT_DEBUG_DATA_SET_DATA(vgt_debug_data_reg, data) \ + vgt_debug_data_reg = (vgt_debug_data_reg & ~VGT_DEBUG_DATA_DATA_MASK) | (data << VGT_DEBUG_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_data_t { + unsigned int data : VGT_DEBUG_DATA_DATA_SIZE; + } vgt_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_data_t { + unsigned int data : VGT_DEBUG_DATA_DATA_SIZE; + } vgt_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_data_t f; +} vgt_debug_data_u; + + +/* + * VGT_CNTL_STATUS struct + */ + +#define VGT_CNTL_STATUS_VGT_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE 1 + +#define VGT_CNTL_STATUS_VGT_BUSY_SHIFT 0 +#define VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT 1 +#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT 2 +#define VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT 3 +#define VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT 4 +#define VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT 5 +#define VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT 6 +#define VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT 7 +#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT 8 + +#define VGT_CNTL_STATUS_VGT_BUSY_MASK 0x00000001 +#define VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK 0x00000002 +#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK 0x00000004 +#define VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK 0x00000008 +#define VGT_CNTL_STATUS_VGT_VR_BUSY_MASK 0x00000010 +#define VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK 0x00000020 +#define VGT_CNTL_STATUS_VGT_PT_BUSY_MASK 0x00000040 +#define VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK 0x00000080 +#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK 0x00000100 + +#define VGT_CNTL_STATUS_MASK \ + (VGT_CNTL_STATUS_VGT_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_VR_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_PT_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) + +#define VGT_CNTL_STATUS(vgt_busy, vgt_dma_busy, vgt_dma_req_busy, vgt_grp_busy, vgt_vr_busy, vgt_bin_busy, vgt_pt_busy, vgt_out_busy, vgt_out_indx_busy) \ + ((vgt_busy << VGT_CNTL_STATUS_VGT_BUSY_SHIFT) | \ + (vgt_dma_busy << VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT) | \ + (vgt_dma_req_busy << VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT) | \ + (vgt_grp_busy << VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT) | \ + (vgt_vr_busy << VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT) | \ + (vgt_bin_busy << VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT) | \ + (vgt_pt_busy << VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT) | \ + (vgt_out_busy << VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT) | \ + (vgt_out_indx_busy << VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT)) + +#define VGT_CNTL_STATUS_GET_VGT_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_DMA_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_DMA_REQ_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_GRP_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_VR_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_VR_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_BIN_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_PT_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_PT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_OUT_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_OUT_INDX_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT) + +#define VGT_CNTL_STATUS_SET_VGT_BUSY(vgt_cntl_status_reg, vgt_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_BUSY_MASK) | (vgt_busy << VGT_CNTL_STATUS_VGT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_DMA_BUSY(vgt_cntl_status_reg, vgt_dma_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK) | (vgt_dma_busy << VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_DMA_REQ_BUSY(vgt_cntl_status_reg, vgt_dma_req_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK) | (vgt_dma_req_busy << VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_GRP_BUSY(vgt_cntl_status_reg, vgt_grp_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK) | (vgt_grp_busy << VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_VR_BUSY(vgt_cntl_status_reg, vgt_vr_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_VR_BUSY_MASK) | (vgt_vr_busy << VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_BIN_BUSY(vgt_cntl_status_reg, vgt_bin_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK) | (vgt_bin_busy << VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_PT_BUSY(vgt_cntl_status_reg, vgt_pt_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_PT_BUSY_MASK) | (vgt_pt_busy << VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_OUT_BUSY(vgt_cntl_status_reg, vgt_out_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK) | (vgt_out_busy << VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_OUT_INDX_BUSY(vgt_cntl_status_reg, vgt_out_indx_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) | (vgt_out_indx_busy << VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_cntl_status_t { + unsigned int vgt_busy : VGT_CNTL_STATUS_VGT_BUSY_SIZE; + unsigned int vgt_dma_busy : VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE; + unsigned int vgt_dma_req_busy : VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE; + unsigned int vgt_grp_busy : VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE; + unsigned int vgt_vr_busy : VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE; + unsigned int vgt_bin_busy : VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE; + unsigned int vgt_pt_busy : VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE; + unsigned int vgt_out_busy : VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE; + unsigned int vgt_out_indx_busy : VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE; + unsigned int : 23; + } vgt_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_cntl_status_t { + unsigned int : 23; + unsigned int vgt_out_indx_busy : VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE; + unsigned int vgt_out_busy : VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE; + unsigned int vgt_pt_busy : VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE; + unsigned int vgt_bin_busy : VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE; + unsigned int vgt_vr_busy : VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE; + unsigned int vgt_grp_busy : VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE; + unsigned int vgt_dma_req_busy : VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE; + unsigned int vgt_dma_busy : VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE; + unsigned int vgt_busy : VGT_CNTL_STATUS_VGT_BUSY_SIZE; + } vgt_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_cntl_status_t f; +} vgt_cntl_status_u; + + +/* + * VGT_DEBUG_REG0 struct + */ + +#define VGT_DEBUG_REG0_te_grp_busy_SIZE 1 +#define VGT_DEBUG_REG0_pt_grp_busy_SIZE 1 +#define VGT_DEBUG_REG0_vr_grp_busy_SIZE 1 +#define VGT_DEBUG_REG0_dma_request_busy_SIZE 1 +#define VGT_DEBUG_REG0_out_busy_SIZE 1 +#define VGT_DEBUG_REG0_grp_backend_busy_SIZE 1 +#define VGT_DEBUG_REG0_grp_busy_SIZE 1 +#define VGT_DEBUG_REG0_dma_busy_SIZE 1 +#define VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE 1 +#define VGT_DEBUG_REG0_rbiu_busy_SIZE 1 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE 1 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE 1 +#define VGT_DEBUG_REG0_vgt_busy_extended_SIZE 1 +#define VGT_DEBUG_REG0_vgt_busy_SIZE 1 +#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE 1 +#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE 1 +#define VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE 1 + +#define VGT_DEBUG_REG0_te_grp_busy_SHIFT 0 +#define VGT_DEBUG_REG0_pt_grp_busy_SHIFT 1 +#define VGT_DEBUG_REG0_vr_grp_busy_SHIFT 2 +#define VGT_DEBUG_REG0_dma_request_busy_SHIFT 3 +#define VGT_DEBUG_REG0_out_busy_SHIFT 4 +#define VGT_DEBUG_REG0_grp_backend_busy_SHIFT 5 +#define VGT_DEBUG_REG0_grp_busy_SHIFT 6 +#define VGT_DEBUG_REG0_dma_busy_SHIFT 7 +#define VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT 8 +#define VGT_DEBUG_REG0_rbiu_busy_SHIFT 9 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT 10 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT 11 +#define VGT_DEBUG_REG0_vgt_busy_extended_SHIFT 12 +#define VGT_DEBUG_REG0_vgt_busy_SHIFT 13 +#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT 14 +#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT 15 +#define VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT 16 + +#define VGT_DEBUG_REG0_te_grp_busy_MASK 0x00000001 +#define VGT_DEBUG_REG0_pt_grp_busy_MASK 0x00000002 +#define VGT_DEBUG_REG0_vr_grp_busy_MASK 0x00000004 +#define VGT_DEBUG_REG0_dma_request_busy_MASK 0x00000008 +#define VGT_DEBUG_REG0_out_busy_MASK 0x00000010 +#define VGT_DEBUG_REG0_grp_backend_busy_MASK 0x00000020 +#define VGT_DEBUG_REG0_grp_busy_MASK 0x00000040 +#define VGT_DEBUG_REG0_dma_busy_MASK 0x00000080 +#define VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK 0x00000100 +#define VGT_DEBUG_REG0_rbiu_busy_MASK 0x00000200 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK 0x00000400 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_MASK 0x00000800 +#define VGT_DEBUG_REG0_vgt_busy_extended_MASK 0x00001000 +#define VGT_DEBUG_REG0_vgt_busy_MASK 0x00002000 +#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK 0x00004000 +#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK 0x00008000 +#define VGT_DEBUG_REG0_VGT_RBBM_busy_MASK 0x00010000 + +#define VGT_DEBUG_REG0_MASK \ + (VGT_DEBUG_REG0_te_grp_busy_MASK | \ + VGT_DEBUG_REG0_pt_grp_busy_MASK | \ + VGT_DEBUG_REG0_vr_grp_busy_MASK | \ + VGT_DEBUG_REG0_dma_request_busy_MASK | \ + VGT_DEBUG_REG0_out_busy_MASK | \ + VGT_DEBUG_REG0_grp_backend_busy_MASK | \ + VGT_DEBUG_REG0_grp_busy_MASK | \ + VGT_DEBUG_REG0_dma_busy_MASK | \ + VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK | \ + VGT_DEBUG_REG0_rbiu_busy_MASK | \ + VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK | \ + VGT_DEBUG_REG0_vgt_no_dma_busy_MASK | \ + VGT_DEBUG_REG0_vgt_busy_extended_MASK | \ + VGT_DEBUG_REG0_vgt_busy_MASK | \ + VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK | \ + VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK | \ + VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) + +#define VGT_DEBUG_REG0(te_grp_busy, pt_grp_busy, vr_grp_busy, dma_request_busy, out_busy, grp_backend_busy, grp_busy, dma_busy, rbiu_dma_request_busy, rbiu_busy, vgt_no_dma_busy_extended, vgt_no_dma_busy, vgt_busy_extended, vgt_busy, rbbm_skid_fifo_busy_out, vgt_rbbm_no_dma_busy, vgt_rbbm_busy) \ + ((te_grp_busy << VGT_DEBUG_REG0_te_grp_busy_SHIFT) | \ + (pt_grp_busy << VGT_DEBUG_REG0_pt_grp_busy_SHIFT) | \ + (vr_grp_busy << VGT_DEBUG_REG0_vr_grp_busy_SHIFT) | \ + (dma_request_busy << VGT_DEBUG_REG0_dma_request_busy_SHIFT) | \ + (out_busy << VGT_DEBUG_REG0_out_busy_SHIFT) | \ + (grp_backend_busy << VGT_DEBUG_REG0_grp_backend_busy_SHIFT) | \ + (grp_busy << VGT_DEBUG_REG0_grp_busy_SHIFT) | \ + (dma_busy << VGT_DEBUG_REG0_dma_busy_SHIFT) | \ + (rbiu_dma_request_busy << VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT) | \ + (rbiu_busy << VGT_DEBUG_REG0_rbiu_busy_SHIFT) | \ + (vgt_no_dma_busy_extended << VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT) | \ + (vgt_no_dma_busy << VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT) | \ + (vgt_busy_extended << VGT_DEBUG_REG0_vgt_busy_extended_SHIFT) | \ + (vgt_busy << VGT_DEBUG_REG0_vgt_busy_SHIFT) | \ + (rbbm_skid_fifo_busy_out << VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT) | \ + (vgt_rbbm_no_dma_busy << VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT) | \ + (vgt_rbbm_busy << VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT)) + +#define VGT_DEBUG_REG0_GET_te_grp_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_te_grp_busy_MASK) >> VGT_DEBUG_REG0_te_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_pt_grp_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_pt_grp_busy_MASK) >> VGT_DEBUG_REG0_pt_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_vr_grp_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vr_grp_busy_MASK) >> VGT_DEBUG_REG0_vr_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_dma_request_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_dma_request_busy_MASK) >> VGT_DEBUG_REG0_dma_request_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_out_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_out_busy_MASK) >> VGT_DEBUG_REG0_out_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_grp_backend_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_grp_backend_busy_MASK) >> VGT_DEBUG_REG0_grp_backend_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_grp_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_grp_busy_MASK) >> VGT_DEBUG_REG0_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_dma_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_dma_busy_MASK) >> VGT_DEBUG_REG0_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_rbiu_dma_request_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK) >> VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_rbiu_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbiu_busy_MASK) >> VGT_DEBUG_REG0_rbiu_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_vgt_no_dma_busy_extended(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK) >> VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT) +#define VGT_DEBUG_REG0_GET_vgt_no_dma_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_no_dma_busy_MASK) >> VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_vgt_busy_extended(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_busy_extended_MASK) >> VGT_DEBUG_REG0_vgt_busy_extended_SHIFT) +#define VGT_DEBUG_REG0_GET_vgt_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_busy_MASK) >> VGT_DEBUG_REG0_vgt_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_rbbm_skid_fifo_busy_out(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK) >> VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT) +#define VGT_DEBUG_REG0_GET_VGT_RBBM_no_dma_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK) >> VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_VGT_RBBM_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) >> VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT) + +#define VGT_DEBUG_REG0_SET_te_grp_busy(vgt_debug_reg0_reg, te_grp_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_te_grp_busy_MASK) | (te_grp_busy << VGT_DEBUG_REG0_te_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_pt_grp_busy(vgt_debug_reg0_reg, pt_grp_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_pt_grp_busy_MASK) | (pt_grp_busy << VGT_DEBUG_REG0_pt_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_vr_grp_busy(vgt_debug_reg0_reg, vr_grp_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vr_grp_busy_MASK) | (vr_grp_busy << VGT_DEBUG_REG0_vr_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_dma_request_busy(vgt_debug_reg0_reg, dma_request_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_dma_request_busy_MASK) | (dma_request_busy << VGT_DEBUG_REG0_dma_request_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_out_busy(vgt_debug_reg0_reg, out_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_out_busy_MASK) | (out_busy << VGT_DEBUG_REG0_out_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_grp_backend_busy(vgt_debug_reg0_reg, grp_backend_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_grp_backend_busy_MASK) | (grp_backend_busy << VGT_DEBUG_REG0_grp_backend_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_grp_busy(vgt_debug_reg0_reg, grp_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_grp_busy_MASK) | (grp_busy << VGT_DEBUG_REG0_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_dma_busy(vgt_debug_reg0_reg, dma_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_dma_busy_MASK) | (dma_busy << VGT_DEBUG_REG0_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_rbiu_dma_request_busy(vgt_debug_reg0_reg, rbiu_dma_request_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK) | (rbiu_dma_request_busy << VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_rbiu_busy(vgt_debug_reg0_reg, rbiu_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbiu_busy_MASK) | (rbiu_busy << VGT_DEBUG_REG0_rbiu_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_vgt_no_dma_busy_extended(vgt_debug_reg0_reg, vgt_no_dma_busy_extended) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK) | (vgt_no_dma_busy_extended << VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT) +#define VGT_DEBUG_REG0_SET_vgt_no_dma_busy(vgt_debug_reg0_reg, vgt_no_dma_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_no_dma_busy_MASK) | (vgt_no_dma_busy << VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_vgt_busy_extended(vgt_debug_reg0_reg, vgt_busy_extended) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_busy_extended_MASK) | (vgt_busy_extended << VGT_DEBUG_REG0_vgt_busy_extended_SHIFT) +#define VGT_DEBUG_REG0_SET_vgt_busy(vgt_debug_reg0_reg, vgt_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_busy_MASK) | (vgt_busy << VGT_DEBUG_REG0_vgt_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_rbbm_skid_fifo_busy_out(vgt_debug_reg0_reg, rbbm_skid_fifo_busy_out) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK) | (rbbm_skid_fifo_busy_out << VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT) +#define VGT_DEBUG_REG0_SET_VGT_RBBM_no_dma_busy(vgt_debug_reg0_reg, vgt_rbbm_no_dma_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK) | (vgt_rbbm_no_dma_busy << VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_VGT_RBBM_busy(vgt_debug_reg0_reg, vgt_rbbm_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) | (vgt_rbbm_busy << VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg0_t { + unsigned int te_grp_busy : VGT_DEBUG_REG0_te_grp_busy_SIZE; + unsigned int pt_grp_busy : VGT_DEBUG_REG0_pt_grp_busy_SIZE; + unsigned int vr_grp_busy : VGT_DEBUG_REG0_vr_grp_busy_SIZE; + unsigned int dma_request_busy : VGT_DEBUG_REG0_dma_request_busy_SIZE; + unsigned int out_busy : VGT_DEBUG_REG0_out_busy_SIZE; + unsigned int grp_backend_busy : VGT_DEBUG_REG0_grp_backend_busy_SIZE; + unsigned int grp_busy : VGT_DEBUG_REG0_grp_busy_SIZE; + unsigned int dma_busy : VGT_DEBUG_REG0_dma_busy_SIZE; + unsigned int rbiu_dma_request_busy : VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE; + unsigned int rbiu_busy : VGT_DEBUG_REG0_rbiu_busy_SIZE; + unsigned int vgt_no_dma_busy_extended : VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE; + unsigned int vgt_no_dma_busy : VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE; + unsigned int vgt_busy_extended : VGT_DEBUG_REG0_vgt_busy_extended_SIZE; + unsigned int vgt_busy : VGT_DEBUG_REG0_vgt_busy_SIZE; + unsigned int rbbm_skid_fifo_busy_out : VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE; + unsigned int vgt_rbbm_no_dma_busy : VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE; + unsigned int vgt_rbbm_busy : VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE; + unsigned int : 15; + } vgt_debug_reg0_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg0_t { + unsigned int : 15; + unsigned int vgt_rbbm_busy : VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE; + unsigned int vgt_rbbm_no_dma_busy : VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE; + unsigned int rbbm_skid_fifo_busy_out : VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE; + unsigned int vgt_busy : VGT_DEBUG_REG0_vgt_busy_SIZE; + unsigned int vgt_busy_extended : VGT_DEBUG_REG0_vgt_busy_extended_SIZE; + unsigned int vgt_no_dma_busy : VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE; + unsigned int vgt_no_dma_busy_extended : VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE; + unsigned int rbiu_busy : VGT_DEBUG_REG0_rbiu_busy_SIZE; + unsigned int rbiu_dma_request_busy : VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE; + unsigned int dma_busy : VGT_DEBUG_REG0_dma_busy_SIZE; + unsigned int grp_busy : VGT_DEBUG_REG0_grp_busy_SIZE; + unsigned int grp_backend_busy : VGT_DEBUG_REG0_grp_backend_busy_SIZE; + unsigned int out_busy : VGT_DEBUG_REG0_out_busy_SIZE; + unsigned int dma_request_busy : VGT_DEBUG_REG0_dma_request_busy_SIZE; + unsigned int vr_grp_busy : VGT_DEBUG_REG0_vr_grp_busy_SIZE; + unsigned int pt_grp_busy : VGT_DEBUG_REG0_pt_grp_busy_SIZE; + unsigned int te_grp_busy : VGT_DEBUG_REG0_te_grp_busy_SIZE; + } vgt_debug_reg0_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg0_t f; +} vgt_debug_reg0_u; + + +/* + * VGT_DEBUG_REG1 struct + */ + +#define VGT_DEBUG_REG1_out_te_data_read_SIZE 1 +#define VGT_DEBUG_REG1_te_out_data_valid_SIZE 1 +#define VGT_DEBUG_REG1_out_pt_prim_read_SIZE 1 +#define VGT_DEBUG_REG1_pt_out_prim_valid_SIZE 1 +#define VGT_DEBUG_REG1_out_pt_data_read_SIZE 1 +#define VGT_DEBUG_REG1_pt_out_indx_valid_SIZE 1 +#define VGT_DEBUG_REG1_out_vr_prim_read_SIZE 1 +#define VGT_DEBUG_REG1_vr_out_prim_valid_SIZE 1 +#define VGT_DEBUG_REG1_out_vr_indx_read_SIZE 1 +#define VGT_DEBUG_REG1_vr_out_indx_valid_SIZE 1 +#define VGT_DEBUG_REG1_te_grp_read_SIZE 1 +#define VGT_DEBUG_REG1_grp_te_valid_SIZE 1 +#define VGT_DEBUG_REG1_pt_grp_read_SIZE 1 +#define VGT_DEBUG_REG1_grp_pt_valid_SIZE 1 +#define VGT_DEBUG_REG1_vr_grp_read_SIZE 1 +#define VGT_DEBUG_REG1_grp_vr_valid_SIZE 1 +#define VGT_DEBUG_REG1_grp_dma_read_SIZE 1 +#define VGT_DEBUG_REG1_dma_grp_valid_SIZE 1 +#define VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE 1 +#define VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE 1 +#define VGT_DEBUG_REG1_MH_VGT_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_MH_send_SIZE 1 +#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE 1 +#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE 1 +#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE 1 +#define VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_SQ_send_SIZE 1 +#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE 1 + +#define VGT_DEBUG_REG1_out_te_data_read_SHIFT 0 +#define VGT_DEBUG_REG1_te_out_data_valid_SHIFT 1 +#define VGT_DEBUG_REG1_out_pt_prim_read_SHIFT 2 +#define VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT 3 +#define VGT_DEBUG_REG1_out_pt_data_read_SHIFT 4 +#define VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT 5 +#define VGT_DEBUG_REG1_out_vr_prim_read_SHIFT 6 +#define VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT 7 +#define VGT_DEBUG_REG1_out_vr_indx_read_SHIFT 8 +#define VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT 9 +#define VGT_DEBUG_REG1_te_grp_read_SHIFT 10 +#define VGT_DEBUG_REG1_grp_te_valid_SHIFT 11 +#define VGT_DEBUG_REG1_pt_grp_read_SHIFT 12 +#define VGT_DEBUG_REG1_grp_pt_valid_SHIFT 13 +#define VGT_DEBUG_REG1_vr_grp_read_SHIFT 14 +#define VGT_DEBUG_REG1_grp_vr_valid_SHIFT 15 +#define VGT_DEBUG_REG1_grp_dma_read_SHIFT 16 +#define VGT_DEBUG_REG1_dma_grp_valid_SHIFT 17 +#define VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT 18 +#define VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT 19 +#define VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT 20 +#define VGT_DEBUG_REG1_VGT_MH_send_SHIFT 21 +#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT 22 +#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT 23 +#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT 24 +#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT 25 +#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT 26 +#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT 27 +#define VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT 28 +#define VGT_DEBUG_REG1_VGT_SQ_send_SHIFT 29 +#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT 30 + +#define VGT_DEBUG_REG1_out_te_data_read_MASK 0x00000001 +#define VGT_DEBUG_REG1_te_out_data_valid_MASK 0x00000002 +#define VGT_DEBUG_REG1_out_pt_prim_read_MASK 0x00000004 +#define VGT_DEBUG_REG1_pt_out_prim_valid_MASK 0x00000008 +#define VGT_DEBUG_REG1_out_pt_data_read_MASK 0x00000010 +#define VGT_DEBUG_REG1_pt_out_indx_valid_MASK 0x00000020 +#define VGT_DEBUG_REG1_out_vr_prim_read_MASK 0x00000040 +#define VGT_DEBUG_REG1_vr_out_prim_valid_MASK 0x00000080 +#define VGT_DEBUG_REG1_out_vr_indx_read_MASK 0x00000100 +#define VGT_DEBUG_REG1_vr_out_indx_valid_MASK 0x00000200 +#define VGT_DEBUG_REG1_te_grp_read_MASK 0x00000400 +#define VGT_DEBUG_REG1_grp_te_valid_MASK 0x00000800 +#define VGT_DEBUG_REG1_pt_grp_read_MASK 0x00001000 +#define VGT_DEBUG_REG1_grp_pt_valid_MASK 0x00002000 +#define VGT_DEBUG_REG1_vr_grp_read_MASK 0x00004000 +#define VGT_DEBUG_REG1_grp_vr_valid_MASK 0x00008000 +#define VGT_DEBUG_REG1_grp_dma_read_MASK 0x00010000 +#define VGT_DEBUG_REG1_dma_grp_valid_MASK 0x00020000 +#define VGT_DEBUG_REG1_grp_rbiu_di_read_MASK 0x00040000 +#define VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK 0x00080000 +#define VGT_DEBUG_REG1_MH_VGT_rtr_MASK 0x00100000 +#define VGT_DEBUG_REG1_VGT_MH_send_MASK 0x00200000 +#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK 0x00400000 +#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK 0x00800000 +#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK 0x01000000 +#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK 0x02000000 +#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK 0x04000000 +#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK 0x08000000 +#define VGT_DEBUG_REG1_SQ_VGT_rtr_MASK 0x10000000 +#define VGT_DEBUG_REG1_VGT_SQ_send_MASK 0x20000000 +#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK 0x40000000 + +#define VGT_DEBUG_REG1_MASK \ + (VGT_DEBUG_REG1_out_te_data_read_MASK | \ + VGT_DEBUG_REG1_te_out_data_valid_MASK | \ + VGT_DEBUG_REG1_out_pt_prim_read_MASK | \ + VGT_DEBUG_REG1_pt_out_prim_valid_MASK | \ + VGT_DEBUG_REG1_out_pt_data_read_MASK | \ + VGT_DEBUG_REG1_pt_out_indx_valid_MASK | \ + VGT_DEBUG_REG1_out_vr_prim_read_MASK | \ + VGT_DEBUG_REG1_vr_out_prim_valid_MASK | \ + VGT_DEBUG_REG1_out_vr_indx_read_MASK | \ + VGT_DEBUG_REG1_vr_out_indx_valid_MASK | \ + VGT_DEBUG_REG1_te_grp_read_MASK | \ + VGT_DEBUG_REG1_grp_te_valid_MASK | \ + VGT_DEBUG_REG1_pt_grp_read_MASK | \ + VGT_DEBUG_REG1_grp_pt_valid_MASK | \ + VGT_DEBUG_REG1_vr_grp_read_MASK | \ + VGT_DEBUG_REG1_grp_vr_valid_MASK | \ + VGT_DEBUG_REG1_grp_dma_read_MASK | \ + VGT_DEBUG_REG1_dma_grp_valid_MASK | \ + VGT_DEBUG_REG1_grp_rbiu_di_read_MASK | \ + VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK | \ + VGT_DEBUG_REG1_MH_VGT_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_MH_send_MASK | \ + VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK | \ + VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK | \ + VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK | \ + VGT_DEBUG_REG1_SQ_VGT_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_SQ_send_MASK | \ + VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) + +#define VGT_DEBUG_REG1(out_te_data_read, te_out_data_valid, out_pt_prim_read, pt_out_prim_valid, out_pt_data_read, pt_out_indx_valid, out_vr_prim_read, vr_out_prim_valid, out_vr_indx_read, vr_out_indx_valid, te_grp_read, grp_te_valid, pt_grp_read, grp_pt_valid, vr_grp_read, grp_vr_valid, grp_dma_read, dma_grp_valid, grp_rbiu_di_read, rbiu_grp_di_valid, mh_vgt_rtr, vgt_mh_send, pa_vgt_clip_s_rtr, vgt_pa_clip_s_send, pa_vgt_clip_p_rtr, vgt_pa_clip_p_send, pa_vgt_clip_v_rtr, vgt_pa_clip_v_send, sq_vgt_rtr, vgt_sq_send, mh_vgt_tag_7_q) \ + ((out_te_data_read << VGT_DEBUG_REG1_out_te_data_read_SHIFT) | \ + (te_out_data_valid << VGT_DEBUG_REG1_te_out_data_valid_SHIFT) | \ + (out_pt_prim_read << VGT_DEBUG_REG1_out_pt_prim_read_SHIFT) | \ + (pt_out_prim_valid << VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT) | \ + (out_pt_data_read << VGT_DEBUG_REG1_out_pt_data_read_SHIFT) | \ + (pt_out_indx_valid << VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT) | \ + (out_vr_prim_read << VGT_DEBUG_REG1_out_vr_prim_read_SHIFT) | \ + (vr_out_prim_valid << VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT) | \ + (out_vr_indx_read << VGT_DEBUG_REG1_out_vr_indx_read_SHIFT) | \ + (vr_out_indx_valid << VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT) | \ + (te_grp_read << VGT_DEBUG_REG1_te_grp_read_SHIFT) | \ + (grp_te_valid << VGT_DEBUG_REG1_grp_te_valid_SHIFT) | \ + (pt_grp_read << VGT_DEBUG_REG1_pt_grp_read_SHIFT) | \ + (grp_pt_valid << VGT_DEBUG_REG1_grp_pt_valid_SHIFT) | \ + (vr_grp_read << VGT_DEBUG_REG1_vr_grp_read_SHIFT) | \ + (grp_vr_valid << VGT_DEBUG_REG1_grp_vr_valid_SHIFT) | \ + (grp_dma_read << VGT_DEBUG_REG1_grp_dma_read_SHIFT) | \ + (dma_grp_valid << VGT_DEBUG_REG1_dma_grp_valid_SHIFT) | \ + (grp_rbiu_di_read << VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT) | \ + (rbiu_grp_di_valid << VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT) | \ + (mh_vgt_rtr << VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT) | \ + (vgt_mh_send << VGT_DEBUG_REG1_VGT_MH_send_SHIFT) | \ + (pa_vgt_clip_s_rtr << VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT) | \ + (vgt_pa_clip_s_send << VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT) | \ + (pa_vgt_clip_p_rtr << VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT) | \ + (vgt_pa_clip_p_send << VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT) | \ + (pa_vgt_clip_v_rtr << VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT) | \ + (vgt_pa_clip_v_send << VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT) | \ + (sq_vgt_rtr << VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT) | \ + (vgt_sq_send << VGT_DEBUG_REG1_VGT_SQ_send_SHIFT) | \ + (mh_vgt_tag_7_q << VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT)) + +#define VGT_DEBUG_REG1_GET_out_te_data_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_te_data_read_MASK) >> VGT_DEBUG_REG1_out_te_data_read_SHIFT) +#define VGT_DEBUG_REG1_GET_te_out_data_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_te_out_data_valid_MASK) >> VGT_DEBUG_REG1_te_out_data_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_out_pt_prim_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_pt_prim_read_MASK) >> VGT_DEBUG_REG1_out_pt_prim_read_SHIFT) +#define VGT_DEBUG_REG1_GET_pt_out_prim_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_out_prim_valid_MASK) >> VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_out_pt_data_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_pt_data_read_MASK) >> VGT_DEBUG_REG1_out_pt_data_read_SHIFT) +#define VGT_DEBUG_REG1_GET_pt_out_indx_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_out_indx_valid_MASK) >> VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_out_vr_prim_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_vr_prim_read_MASK) >> VGT_DEBUG_REG1_out_vr_prim_read_SHIFT) +#define VGT_DEBUG_REG1_GET_vr_out_prim_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_out_prim_valid_MASK) >> VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_out_vr_indx_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_vr_indx_read_MASK) >> VGT_DEBUG_REG1_out_vr_indx_read_SHIFT) +#define VGT_DEBUG_REG1_GET_vr_out_indx_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_out_indx_valid_MASK) >> VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_te_grp_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_te_grp_read_MASK) >> VGT_DEBUG_REG1_te_grp_read_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_te_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_te_valid_MASK) >> VGT_DEBUG_REG1_grp_te_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_pt_grp_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_grp_read_MASK) >> VGT_DEBUG_REG1_pt_grp_read_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_pt_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_pt_valid_MASK) >> VGT_DEBUG_REG1_grp_pt_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_vr_grp_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_grp_read_MASK) >> VGT_DEBUG_REG1_vr_grp_read_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_vr_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_vr_valid_MASK) >> VGT_DEBUG_REG1_grp_vr_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_dma_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_dma_read_MASK) >> VGT_DEBUG_REG1_grp_dma_read_SHIFT) +#define VGT_DEBUG_REG1_GET_dma_grp_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_dma_grp_valid_MASK) >> VGT_DEBUG_REG1_dma_grp_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_rbiu_di_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_rbiu_di_read_MASK) >> VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT) +#define VGT_DEBUG_REG1_GET_rbiu_grp_di_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK) >> VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_MH_VGT_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_MH_VGT_rtr_MASK) >> VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_MH_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_MH_send_MASK) >> VGT_DEBUG_REG1_VGT_MH_send_SHIFT) +#define VGT_DEBUG_REG1_GET_PA_VGT_clip_s_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_PA_clip_s_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT) +#define VGT_DEBUG_REG1_GET_PA_VGT_clip_p_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_PA_clip_p_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT) +#define VGT_DEBUG_REG1_GET_PA_VGT_clip_v_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_PA_clip_v_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT) +#define VGT_DEBUG_REG1_GET_SQ_VGT_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_SQ_VGT_rtr_MASK) >> VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_SQ_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_SQ_send_MASK) >> VGT_DEBUG_REG1_VGT_SQ_send_SHIFT) +#define VGT_DEBUG_REG1_GET_mh_vgt_tag_7_q(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) >> VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT) + +#define VGT_DEBUG_REG1_SET_out_te_data_read(vgt_debug_reg1_reg, out_te_data_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_te_data_read_MASK) | (out_te_data_read << VGT_DEBUG_REG1_out_te_data_read_SHIFT) +#define VGT_DEBUG_REG1_SET_te_out_data_valid(vgt_debug_reg1_reg, te_out_data_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_te_out_data_valid_MASK) | (te_out_data_valid << VGT_DEBUG_REG1_te_out_data_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_out_pt_prim_read(vgt_debug_reg1_reg, out_pt_prim_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_pt_prim_read_MASK) | (out_pt_prim_read << VGT_DEBUG_REG1_out_pt_prim_read_SHIFT) +#define VGT_DEBUG_REG1_SET_pt_out_prim_valid(vgt_debug_reg1_reg, pt_out_prim_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_out_prim_valid_MASK) | (pt_out_prim_valid << VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_out_pt_data_read(vgt_debug_reg1_reg, out_pt_data_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_pt_data_read_MASK) | (out_pt_data_read << VGT_DEBUG_REG1_out_pt_data_read_SHIFT) +#define VGT_DEBUG_REG1_SET_pt_out_indx_valid(vgt_debug_reg1_reg, pt_out_indx_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_out_indx_valid_MASK) | (pt_out_indx_valid << VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_out_vr_prim_read(vgt_debug_reg1_reg, out_vr_prim_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_vr_prim_read_MASK) | (out_vr_prim_read << VGT_DEBUG_REG1_out_vr_prim_read_SHIFT) +#define VGT_DEBUG_REG1_SET_vr_out_prim_valid(vgt_debug_reg1_reg, vr_out_prim_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_out_prim_valid_MASK) | (vr_out_prim_valid << VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_out_vr_indx_read(vgt_debug_reg1_reg, out_vr_indx_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_vr_indx_read_MASK) | (out_vr_indx_read << VGT_DEBUG_REG1_out_vr_indx_read_SHIFT) +#define VGT_DEBUG_REG1_SET_vr_out_indx_valid(vgt_debug_reg1_reg, vr_out_indx_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_out_indx_valid_MASK) | (vr_out_indx_valid << VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_te_grp_read(vgt_debug_reg1_reg, te_grp_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_te_grp_read_MASK) | (te_grp_read << VGT_DEBUG_REG1_te_grp_read_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_te_valid(vgt_debug_reg1_reg, grp_te_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_te_valid_MASK) | (grp_te_valid << VGT_DEBUG_REG1_grp_te_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_pt_grp_read(vgt_debug_reg1_reg, pt_grp_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_grp_read_MASK) | (pt_grp_read << VGT_DEBUG_REG1_pt_grp_read_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_pt_valid(vgt_debug_reg1_reg, grp_pt_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_pt_valid_MASK) | (grp_pt_valid << VGT_DEBUG_REG1_grp_pt_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_vr_grp_read(vgt_debug_reg1_reg, vr_grp_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_grp_read_MASK) | (vr_grp_read << VGT_DEBUG_REG1_vr_grp_read_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_vr_valid(vgt_debug_reg1_reg, grp_vr_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_vr_valid_MASK) | (grp_vr_valid << VGT_DEBUG_REG1_grp_vr_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_dma_read(vgt_debug_reg1_reg, grp_dma_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_dma_read_MASK) | (grp_dma_read << VGT_DEBUG_REG1_grp_dma_read_SHIFT) +#define VGT_DEBUG_REG1_SET_dma_grp_valid(vgt_debug_reg1_reg, dma_grp_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_dma_grp_valid_MASK) | (dma_grp_valid << VGT_DEBUG_REG1_dma_grp_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_rbiu_di_read(vgt_debug_reg1_reg, grp_rbiu_di_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_rbiu_di_read_MASK) | (grp_rbiu_di_read << VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT) +#define VGT_DEBUG_REG1_SET_rbiu_grp_di_valid(vgt_debug_reg1_reg, rbiu_grp_di_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK) | (rbiu_grp_di_valid << VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_MH_VGT_rtr(vgt_debug_reg1_reg, mh_vgt_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_MH_VGT_rtr_MASK) | (mh_vgt_rtr << VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_MH_send(vgt_debug_reg1_reg, vgt_mh_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_MH_send_MASK) | (vgt_mh_send << VGT_DEBUG_REG1_VGT_MH_send_SHIFT) +#define VGT_DEBUG_REG1_SET_PA_VGT_clip_s_rtr(vgt_debug_reg1_reg, pa_vgt_clip_s_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK) | (pa_vgt_clip_s_rtr << VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_PA_clip_s_send(vgt_debug_reg1_reg, vgt_pa_clip_s_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK) | (vgt_pa_clip_s_send << VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT) +#define VGT_DEBUG_REG1_SET_PA_VGT_clip_p_rtr(vgt_debug_reg1_reg, pa_vgt_clip_p_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK) | (pa_vgt_clip_p_rtr << VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_PA_clip_p_send(vgt_debug_reg1_reg, vgt_pa_clip_p_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK) | (vgt_pa_clip_p_send << VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT) +#define VGT_DEBUG_REG1_SET_PA_VGT_clip_v_rtr(vgt_debug_reg1_reg, pa_vgt_clip_v_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK) | (pa_vgt_clip_v_rtr << VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_PA_clip_v_send(vgt_debug_reg1_reg, vgt_pa_clip_v_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK) | (vgt_pa_clip_v_send << VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT) +#define VGT_DEBUG_REG1_SET_SQ_VGT_rtr(vgt_debug_reg1_reg, sq_vgt_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_SQ_VGT_rtr_MASK) | (sq_vgt_rtr << VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_SQ_send(vgt_debug_reg1_reg, vgt_sq_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_SQ_send_MASK) | (vgt_sq_send << VGT_DEBUG_REG1_VGT_SQ_send_SHIFT) +#define VGT_DEBUG_REG1_SET_mh_vgt_tag_7_q(vgt_debug_reg1_reg, mh_vgt_tag_7_q) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) | (mh_vgt_tag_7_q << VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg1_t { + unsigned int out_te_data_read : VGT_DEBUG_REG1_out_te_data_read_SIZE; + unsigned int te_out_data_valid : VGT_DEBUG_REG1_te_out_data_valid_SIZE; + unsigned int out_pt_prim_read : VGT_DEBUG_REG1_out_pt_prim_read_SIZE; + unsigned int pt_out_prim_valid : VGT_DEBUG_REG1_pt_out_prim_valid_SIZE; + unsigned int out_pt_data_read : VGT_DEBUG_REG1_out_pt_data_read_SIZE; + unsigned int pt_out_indx_valid : VGT_DEBUG_REG1_pt_out_indx_valid_SIZE; + unsigned int out_vr_prim_read : VGT_DEBUG_REG1_out_vr_prim_read_SIZE; + unsigned int vr_out_prim_valid : VGT_DEBUG_REG1_vr_out_prim_valid_SIZE; + unsigned int out_vr_indx_read : VGT_DEBUG_REG1_out_vr_indx_read_SIZE; + unsigned int vr_out_indx_valid : VGT_DEBUG_REG1_vr_out_indx_valid_SIZE; + unsigned int te_grp_read : VGT_DEBUG_REG1_te_grp_read_SIZE; + unsigned int grp_te_valid : VGT_DEBUG_REG1_grp_te_valid_SIZE; + unsigned int pt_grp_read : VGT_DEBUG_REG1_pt_grp_read_SIZE; + unsigned int grp_pt_valid : VGT_DEBUG_REG1_grp_pt_valid_SIZE; + unsigned int vr_grp_read : VGT_DEBUG_REG1_vr_grp_read_SIZE; + unsigned int grp_vr_valid : VGT_DEBUG_REG1_grp_vr_valid_SIZE; + unsigned int grp_dma_read : VGT_DEBUG_REG1_grp_dma_read_SIZE; + unsigned int dma_grp_valid : VGT_DEBUG_REG1_dma_grp_valid_SIZE; + unsigned int grp_rbiu_di_read : VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE; + unsigned int rbiu_grp_di_valid : VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE; + unsigned int mh_vgt_rtr : VGT_DEBUG_REG1_MH_VGT_rtr_SIZE; + unsigned int vgt_mh_send : VGT_DEBUG_REG1_VGT_MH_send_SIZE; + unsigned int pa_vgt_clip_s_rtr : VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE; + unsigned int vgt_pa_clip_s_send : VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE; + unsigned int pa_vgt_clip_p_rtr : VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE; + unsigned int vgt_pa_clip_p_send : VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE; + unsigned int pa_vgt_clip_v_rtr : VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE; + unsigned int vgt_pa_clip_v_send : VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE; + unsigned int sq_vgt_rtr : VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE; + unsigned int vgt_sq_send : VGT_DEBUG_REG1_VGT_SQ_send_SIZE; + unsigned int mh_vgt_tag_7_q : VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE; + unsigned int : 1; + } vgt_debug_reg1_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg1_t { + unsigned int : 1; + unsigned int mh_vgt_tag_7_q : VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE; + unsigned int vgt_sq_send : VGT_DEBUG_REG1_VGT_SQ_send_SIZE; + unsigned int sq_vgt_rtr : VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE; + unsigned int vgt_pa_clip_v_send : VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE; + unsigned int pa_vgt_clip_v_rtr : VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE; + unsigned int vgt_pa_clip_p_send : VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE; + unsigned int pa_vgt_clip_p_rtr : VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE; + unsigned int vgt_pa_clip_s_send : VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE; + unsigned int pa_vgt_clip_s_rtr : VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE; + unsigned int vgt_mh_send : VGT_DEBUG_REG1_VGT_MH_send_SIZE; + unsigned int mh_vgt_rtr : VGT_DEBUG_REG1_MH_VGT_rtr_SIZE; + unsigned int rbiu_grp_di_valid : VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE; + unsigned int grp_rbiu_di_read : VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE; + unsigned int dma_grp_valid : VGT_DEBUG_REG1_dma_grp_valid_SIZE; + unsigned int grp_dma_read : VGT_DEBUG_REG1_grp_dma_read_SIZE; + unsigned int grp_vr_valid : VGT_DEBUG_REG1_grp_vr_valid_SIZE; + unsigned int vr_grp_read : VGT_DEBUG_REG1_vr_grp_read_SIZE; + unsigned int grp_pt_valid : VGT_DEBUG_REG1_grp_pt_valid_SIZE; + unsigned int pt_grp_read : VGT_DEBUG_REG1_pt_grp_read_SIZE; + unsigned int grp_te_valid : VGT_DEBUG_REG1_grp_te_valid_SIZE; + unsigned int te_grp_read : VGT_DEBUG_REG1_te_grp_read_SIZE; + unsigned int vr_out_indx_valid : VGT_DEBUG_REG1_vr_out_indx_valid_SIZE; + unsigned int out_vr_indx_read : VGT_DEBUG_REG1_out_vr_indx_read_SIZE; + unsigned int vr_out_prim_valid : VGT_DEBUG_REG1_vr_out_prim_valid_SIZE; + unsigned int out_vr_prim_read : VGT_DEBUG_REG1_out_vr_prim_read_SIZE; + unsigned int pt_out_indx_valid : VGT_DEBUG_REG1_pt_out_indx_valid_SIZE; + unsigned int out_pt_data_read : VGT_DEBUG_REG1_out_pt_data_read_SIZE; + unsigned int pt_out_prim_valid : VGT_DEBUG_REG1_pt_out_prim_valid_SIZE; + unsigned int out_pt_prim_read : VGT_DEBUG_REG1_out_pt_prim_read_SIZE; + unsigned int te_out_data_valid : VGT_DEBUG_REG1_te_out_data_valid_SIZE; + unsigned int out_te_data_read : VGT_DEBUG_REG1_out_te_data_read_SIZE; + } vgt_debug_reg1_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg1_t f; +} vgt_debug_reg1_u; + + +/* + * VGT_DEBUG_REG3 struct + */ + +#define VGT_DEBUG_REG3_vgt_clk_en_SIZE 1 +#define VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE 1 + +#define VGT_DEBUG_REG3_vgt_clk_en_SHIFT 0 +#define VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT 1 + +#define VGT_DEBUG_REG3_vgt_clk_en_MASK 0x00000001 +#define VGT_DEBUG_REG3_reg_fifos_clk_en_MASK 0x00000002 + +#define VGT_DEBUG_REG3_MASK \ + (VGT_DEBUG_REG3_vgt_clk_en_MASK | \ + VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) + +#define VGT_DEBUG_REG3(vgt_clk_en, reg_fifos_clk_en) \ + ((vgt_clk_en << VGT_DEBUG_REG3_vgt_clk_en_SHIFT) | \ + (reg_fifos_clk_en << VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT)) + +#define VGT_DEBUG_REG3_GET_vgt_clk_en(vgt_debug_reg3) \ + ((vgt_debug_reg3 & VGT_DEBUG_REG3_vgt_clk_en_MASK) >> VGT_DEBUG_REG3_vgt_clk_en_SHIFT) +#define VGT_DEBUG_REG3_GET_reg_fifos_clk_en(vgt_debug_reg3) \ + ((vgt_debug_reg3 & VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) >> VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT) + +#define VGT_DEBUG_REG3_SET_vgt_clk_en(vgt_debug_reg3_reg, vgt_clk_en) \ + vgt_debug_reg3_reg = (vgt_debug_reg3_reg & ~VGT_DEBUG_REG3_vgt_clk_en_MASK) | (vgt_clk_en << VGT_DEBUG_REG3_vgt_clk_en_SHIFT) +#define VGT_DEBUG_REG3_SET_reg_fifos_clk_en(vgt_debug_reg3_reg, reg_fifos_clk_en) \ + vgt_debug_reg3_reg = (vgt_debug_reg3_reg & ~VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) | (reg_fifos_clk_en << VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg3_t { + unsigned int vgt_clk_en : VGT_DEBUG_REG3_vgt_clk_en_SIZE; + unsigned int reg_fifos_clk_en : VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE; + unsigned int : 30; + } vgt_debug_reg3_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg3_t { + unsigned int : 30; + unsigned int reg_fifos_clk_en : VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE; + unsigned int vgt_clk_en : VGT_DEBUG_REG3_vgt_clk_en_SIZE; + } vgt_debug_reg3_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg3_t f; +} vgt_debug_reg3_u; + + +/* + * VGT_DEBUG_REG6 struct + */ + +#define VGT_DEBUG_REG6_shifter_byte_count_q_SIZE 5 +#define VGT_DEBUG_REG6_right_word_indx_q_SIZE 5 +#define VGT_DEBUG_REG6_input_data_valid_SIZE 1 +#define VGT_DEBUG_REG6_input_data_xfer_SIZE 1 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE 1 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE 1 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE 1 +#define VGT_DEBUG_REG6_space_avail_from_shift_SIZE 1 +#define VGT_DEBUG_REG6_shifter_first_load_SIZE 1 +#define VGT_DEBUG_REG6_di_state_sel_q_SIZE 1 +#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE 1 +#define VGT_DEBUG_REG6_di_first_group_flag_q_SIZE 1 +#define VGT_DEBUG_REG6_di_event_flag_q_SIZE 1 +#define VGT_DEBUG_REG6_read_draw_initiator_SIZE 1 +#define VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE 1 +#define VGT_DEBUG_REG6_last_shift_of_packet_SIZE 1 +#define VGT_DEBUG_REG6_last_decr_of_packet_SIZE 1 +#define VGT_DEBUG_REG6_extract_vector_SIZE 1 +#define VGT_DEBUG_REG6_shift_vect_rtr_SIZE 1 +#define VGT_DEBUG_REG6_destination_rtr_SIZE 1 +#define VGT_DEBUG_REG6_grp_trigger_SIZE 1 + +#define VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT 0 +#define VGT_DEBUG_REG6_right_word_indx_q_SHIFT 5 +#define VGT_DEBUG_REG6_input_data_valid_SHIFT 10 +#define VGT_DEBUG_REG6_input_data_xfer_SHIFT 11 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT 12 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT 13 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT 14 +#define VGT_DEBUG_REG6_space_avail_from_shift_SHIFT 15 +#define VGT_DEBUG_REG6_shifter_first_load_SHIFT 16 +#define VGT_DEBUG_REG6_di_state_sel_q_SHIFT 17 +#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT 18 +#define VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT 19 +#define VGT_DEBUG_REG6_di_event_flag_q_SHIFT 20 +#define VGT_DEBUG_REG6_read_draw_initiator_SHIFT 21 +#define VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT 22 +#define VGT_DEBUG_REG6_last_shift_of_packet_SHIFT 23 +#define VGT_DEBUG_REG6_last_decr_of_packet_SHIFT 24 +#define VGT_DEBUG_REG6_extract_vector_SHIFT 25 +#define VGT_DEBUG_REG6_shift_vect_rtr_SHIFT 26 +#define VGT_DEBUG_REG6_destination_rtr_SHIFT 27 +#define VGT_DEBUG_REG6_grp_trigger_SHIFT 28 + +#define VGT_DEBUG_REG6_shifter_byte_count_q_MASK 0x0000001f +#define VGT_DEBUG_REG6_right_word_indx_q_MASK 0x000003e0 +#define VGT_DEBUG_REG6_input_data_valid_MASK 0x00000400 +#define VGT_DEBUG_REG6_input_data_xfer_MASK 0x00000800 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK 0x00001000 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK 0x00002000 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK 0x00004000 +#define VGT_DEBUG_REG6_space_avail_from_shift_MASK 0x00008000 +#define VGT_DEBUG_REG6_shifter_first_load_MASK 0x00010000 +#define VGT_DEBUG_REG6_di_state_sel_q_MASK 0x00020000 +#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK 0x00040000 +#define VGT_DEBUG_REG6_di_first_group_flag_q_MASK 0x00080000 +#define VGT_DEBUG_REG6_di_event_flag_q_MASK 0x00100000 +#define VGT_DEBUG_REG6_read_draw_initiator_MASK 0x00200000 +#define VGT_DEBUG_REG6_loading_di_requires_shifter_MASK 0x00400000 +#define VGT_DEBUG_REG6_last_shift_of_packet_MASK 0x00800000 +#define VGT_DEBUG_REG6_last_decr_of_packet_MASK 0x01000000 +#define VGT_DEBUG_REG6_extract_vector_MASK 0x02000000 +#define VGT_DEBUG_REG6_shift_vect_rtr_MASK 0x04000000 +#define VGT_DEBUG_REG6_destination_rtr_MASK 0x08000000 +#define VGT_DEBUG_REG6_grp_trigger_MASK 0x10000000 + +#define VGT_DEBUG_REG6_MASK \ + (VGT_DEBUG_REG6_shifter_byte_count_q_MASK | \ + VGT_DEBUG_REG6_right_word_indx_q_MASK | \ + VGT_DEBUG_REG6_input_data_valid_MASK | \ + VGT_DEBUG_REG6_input_data_xfer_MASK | \ + VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK | \ + VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK | \ + VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK | \ + VGT_DEBUG_REG6_space_avail_from_shift_MASK | \ + VGT_DEBUG_REG6_shifter_first_load_MASK | \ + VGT_DEBUG_REG6_di_state_sel_q_MASK | \ + VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK | \ + VGT_DEBUG_REG6_di_first_group_flag_q_MASK | \ + VGT_DEBUG_REG6_di_event_flag_q_MASK | \ + VGT_DEBUG_REG6_read_draw_initiator_MASK | \ + VGT_DEBUG_REG6_loading_di_requires_shifter_MASK | \ + VGT_DEBUG_REG6_last_shift_of_packet_MASK | \ + VGT_DEBUG_REG6_last_decr_of_packet_MASK | \ + VGT_DEBUG_REG6_extract_vector_MASK | \ + VGT_DEBUG_REG6_shift_vect_rtr_MASK | \ + VGT_DEBUG_REG6_destination_rtr_MASK | \ + VGT_DEBUG_REG6_grp_trigger_MASK) + +#define VGT_DEBUG_REG6(shifter_byte_count_q, right_word_indx_q, input_data_valid, input_data_xfer, next_shift_is_vect_1_q, next_shift_is_vect_1_d, next_shift_is_vect_1_pre_d, space_avail_from_shift, shifter_first_load, di_state_sel_q, shifter_waiting_for_first_load_q, di_first_group_flag_q, di_event_flag_q, read_draw_initiator, loading_di_requires_shifter, last_shift_of_packet, last_decr_of_packet, extract_vector, shift_vect_rtr, destination_rtr, grp_trigger) \ + ((shifter_byte_count_q << VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT) | \ + (right_word_indx_q << VGT_DEBUG_REG6_right_word_indx_q_SHIFT) | \ + (input_data_valid << VGT_DEBUG_REG6_input_data_valid_SHIFT) | \ + (input_data_xfer << VGT_DEBUG_REG6_input_data_xfer_SHIFT) | \ + (next_shift_is_vect_1_q << VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT) | \ + (next_shift_is_vect_1_d << VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT) | \ + (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT) | \ + (space_avail_from_shift << VGT_DEBUG_REG6_space_avail_from_shift_SHIFT) | \ + (shifter_first_load << VGT_DEBUG_REG6_shifter_first_load_SHIFT) | \ + (di_state_sel_q << VGT_DEBUG_REG6_di_state_sel_q_SHIFT) | \ + (shifter_waiting_for_first_load_q << VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT) | \ + (di_first_group_flag_q << VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT) | \ + (di_event_flag_q << VGT_DEBUG_REG6_di_event_flag_q_SHIFT) | \ + (read_draw_initiator << VGT_DEBUG_REG6_read_draw_initiator_SHIFT) | \ + (loading_di_requires_shifter << VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT) | \ + (last_shift_of_packet << VGT_DEBUG_REG6_last_shift_of_packet_SHIFT) | \ + (last_decr_of_packet << VGT_DEBUG_REG6_last_decr_of_packet_SHIFT) | \ + (extract_vector << VGT_DEBUG_REG6_extract_vector_SHIFT) | \ + (shift_vect_rtr << VGT_DEBUG_REG6_shift_vect_rtr_SHIFT) | \ + (destination_rtr << VGT_DEBUG_REG6_destination_rtr_SHIFT) | \ + (grp_trigger << VGT_DEBUG_REG6_grp_trigger_SHIFT)) + +#define VGT_DEBUG_REG6_GET_shifter_byte_count_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_byte_count_q_MASK) >> VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT) +#define VGT_DEBUG_REG6_GET_right_word_indx_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_right_word_indx_q_MASK) >> VGT_DEBUG_REG6_right_word_indx_q_SHIFT) +#define VGT_DEBUG_REG6_GET_input_data_valid(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_input_data_valid_MASK) >> VGT_DEBUG_REG6_input_data_valid_SHIFT) +#define VGT_DEBUG_REG6_GET_input_data_xfer(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_input_data_xfer_MASK) >> VGT_DEBUG_REG6_input_data_xfer_SHIFT) +#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT) +#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_d(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT) +#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_pre_d(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT) +#define VGT_DEBUG_REG6_GET_space_avail_from_shift(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_space_avail_from_shift_MASK) >> VGT_DEBUG_REG6_space_avail_from_shift_SHIFT) +#define VGT_DEBUG_REG6_GET_shifter_first_load(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_first_load_MASK) >> VGT_DEBUG_REG6_shifter_first_load_SHIFT) +#define VGT_DEBUG_REG6_GET_di_state_sel_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_state_sel_q_MASK) >> VGT_DEBUG_REG6_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG6_GET_shifter_waiting_for_first_load_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK) >> VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT) +#define VGT_DEBUG_REG6_GET_di_first_group_flag_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_first_group_flag_q_MASK) >> VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT) +#define VGT_DEBUG_REG6_GET_di_event_flag_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_event_flag_q_MASK) >> VGT_DEBUG_REG6_di_event_flag_q_SHIFT) +#define VGT_DEBUG_REG6_GET_read_draw_initiator(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_read_draw_initiator_MASK) >> VGT_DEBUG_REG6_read_draw_initiator_SHIFT) +#define VGT_DEBUG_REG6_GET_loading_di_requires_shifter(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_loading_di_requires_shifter_MASK) >> VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT) +#define VGT_DEBUG_REG6_GET_last_shift_of_packet(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_last_shift_of_packet_MASK) >> VGT_DEBUG_REG6_last_shift_of_packet_SHIFT) +#define VGT_DEBUG_REG6_GET_last_decr_of_packet(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_last_decr_of_packet_MASK) >> VGT_DEBUG_REG6_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG6_GET_extract_vector(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_extract_vector_MASK) >> VGT_DEBUG_REG6_extract_vector_SHIFT) +#define VGT_DEBUG_REG6_GET_shift_vect_rtr(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_shift_vect_rtr_MASK) >> VGT_DEBUG_REG6_shift_vect_rtr_SHIFT) +#define VGT_DEBUG_REG6_GET_destination_rtr(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_destination_rtr_MASK) >> VGT_DEBUG_REG6_destination_rtr_SHIFT) +#define VGT_DEBUG_REG6_GET_grp_trigger(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_grp_trigger_MASK) >> VGT_DEBUG_REG6_grp_trigger_SHIFT) + +#define VGT_DEBUG_REG6_SET_shifter_byte_count_q(vgt_debug_reg6_reg, shifter_byte_count_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_byte_count_q_MASK) | (shifter_byte_count_q << VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT) +#define VGT_DEBUG_REG6_SET_right_word_indx_q(vgt_debug_reg6_reg, right_word_indx_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_right_word_indx_q_MASK) | (right_word_indx_q << VGT_DEBUG_REG6_right_word_indx_q_SHIFT) +#define VGT_DEBUG_REG6_SET_input_data_valid(vgt_debug_reg6_reg, input_data_valid) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_input_data_valid_MASK) | (input_data_valid << VGT_DEBUG_REG6_input_data_valid_SHIFT) +#define VGT_DEBUG_REG6_SET_input_data_xfer(vgt_debug_reg6_reg, input_data_xfer) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_input_data_xfer_MASK) | (input_data_xfer << VGT_DEBUG_REG6_input_data_xfer_SHIFT) +#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_q(vgt_debug_reg6_reg, next_shift_is_vect_1_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK) | (next_shift_is_vect_1_q << VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT) +#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_d(vgt_debug_reg6_reg, next_shift_is_vect_1_d) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK) | (next_shift_is_vect_1_d << VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT) +#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_pre_d(vgt_debug_reg6_reg, next_shift_is_vect_1_pre_d) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK) | (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT) +#define VGT_DEBUG_REG6_SET_space_avail_from_shift(vgt_debug_reg6_reg, space_avail_from_shift) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_space_avail_from_shift_MASK) | (space_avail_from_shift << VGT_DEBUG_REG6_space_avail_from_shift_SHIFT) +#define VGT_DEBUG_REG6_SET_shifter_first_load(vgt_debug_reg6_reg, shifter_first_load) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_first_load_MASK) | (shifter_first_load << VGT_DEBUG_REG6_shifter_first_load_SHIFT) +#define VGT_DEBUG_REG6_SET_di_state_sel_q(vgt_debug_reg6_reg, di_state_sel_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG6_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG6_SET_shifter_waiting_for_first_load_q(vgt_debug_reg6_reg, shifter_waiting_for_first_load_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK) | (shifter_waiting_for_first_load_q << VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT) +#define VGT_DEBUG_REG6_SET_di_first_group_flag_q(vgt_debug_reg6_reg, di_first_group_flag_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_first_group_flag_q_MASK) | (di_first_group_flag_q << VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT) +#define VGT_DEBUG_REG6_SET_di_event_flag_q(vgt_debug_reg6_reg, di_event_flag_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_event_flag_q_MASK) | (di_event_flag_q << VGT_DEBUG_REG6_di_event_flag_q_SHIFT) +#define VGT_DEBUG_REG6_SET_read_draw_initiator(vgt_debug_reg6_reg, read_draw_initiator) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_read_draw_initiator_MASK) | (read_draw_initiator << VGT_DEBUG_REG6_read_draw_initiator_SHIFT) +#define VGT_DEBUG_REG6_SET_loading_di_requires_shifter(vgt_debug_reg6_reg, loading_di_requires_shifter) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_loading_di_requires_shifter_MASK) | (loading_di_requires_shifter << VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT) +#define VGT_DEBUG_REG6_SET_last_shift_of_packet(vgt_debug_reg6_reg, last_shift_of_packet) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_last_shift_of_packet_MASK) | (last_shift_of_packet << VGT_DEBUG_REG6_last_shift_of_packet_SHIFT) +#define VGT_DEBUG_REG6_SET_last_decr_of_packet(vgt_debug_reg6_reg, last_decr_of_packet) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG6_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG6_SET_extract_vector(vgt_debug_reg6_reg, extract_vector) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_extract_vector_MASK) | (extract_vector << VGT_DEBUG_REG6_extract_vector_SHIFT) +#define VGT_DEBUG_REG6_SET_shift_vect_rtr(vgt_debug_reg6_reg, shift_vect_rtr) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shift_vect_rtr_MASK) | (shift_vect_rtr << VGT_DEBUG_REG6_shift_vect_rtr_SHIFT) +#define VGT_DEBUG_REG6_SET_destination_rtr(vgt_debug_reg6_reg, destination_rtr) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_destination_rtr_MASK) | (destination_rtr << VGT_DEBUG_REG6_destination_rtr_SHIFT) +#define VGT_DEBUG_REG6_SET_grp_trigger(vgt_debug_reg6_reg, grp_trigger) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG6_grp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg6_t { + unsigned int shifter_byte_count_q : VGT_DEBUG_REG6_shifter_byte_count_q_SIZE; + unsigned int right_word_indx_q : VGT_DEBUG_REG6_right_word_indx_q_SIZE; + unsigned int input_data_valid : VGT_DEBUG_REG6_input_data_valid_SIZE; + unsigned int input_data_xfer : VGT_DEBUG_REG6_input_data_xfer_SIZE; + unsigned int next_shift_is_vect_1_q : VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE; + unsigned int next_shift_is_vect_1_d : VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE; + unsigned int next_shift_is_vect_1_pre_d : VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE; + unsigned int space_avail_from_shift : VGT_DEBUG_REG6_space_avail_from_shift_SIZE; + unsigned int shifter_first_load : VGT_DEBUG_REG6_shifter_first_load_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG6_di_state_sel_q_SIZE; + unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE; + unsigned int di_first_group_flag_q : VGT_DEBUG_REG6_di_first_group_flag_q_SIZE; + unsigned int di_event_flag_q : VGT_DEBUG_REG6_di_event_flag_q_SIZE; + unsigned int read_draw_initiator : VGT_DEBUG_REG6_read_draw_initiator_SIZE; + unsigned int loading_di_requires_shifter : VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE; + unsigned int last_shift_of_packet : VGT_DEBUG_REG6_last_shift_of_packet_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG6_last_decr_of_packet_SIZE; + unsigned int extract_vector : VGT_DEBUG_REG6_extract_vector_SIZE; + unsigned int shift_vect_rtr : VGT_DEBUG_REG6_shift_vect_rtr_SIZE; + unsigned int destination_rtr : VGT_DEBUG_REG6_destination_rtr_SIZE; + unsigned int grp_trigger : VGT_DEBUG_REG6_grp_trigger_SIZE; + unsigned int : 3; + } vgt_debug_reg6_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg6_t { + unsigned int : 3; + unsigned int grp_trigger : VGT_DEBUG_REG6_grp_trigger_SIZE; + unsigned int destination_rtr : VGT_DEBUG_REG6_destination_rtr_SIZE; + unsigned int shift_vect_rtr : VGT_DEBUG_REG6_shift_vect_rtr_SIZE; + unsigned int extract_vector : VGT_DEBUG_REG6_extract_vector_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG6_last_decr_of_packet_SIZE; + unsigned int last_shift_of_packet : VGT_DEBUG_REG6_last_shift_of_packet_SIZE; + unsigned int loading_di_requires_shifter : VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE; + unsigned int read_draw_initiator : VGT_DEBUG_REG6_read_draw_initiator_SIZE; + unsigned int di_event_flag_q : VGT_DEBUG_REG6_di_event_flag_q_SIZE; + unsigned int di_first_group_flag_q : VGT_DEBUG_REG6_di_first_group_flag_q_SIZE; + unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG6_di_state_sel_q_SIZE; + unsigned int shifter_first_load : VGT_DEBUG_REG6_shifter_first_load_SIZE; + unsigned int space_avail_from_shift : VGT_DEBUG_REG6_space_avail_from_shift_SIZE; + unsigned int next_shift_is_vect_1_pre_d : VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE; + unsigned int next_shift_is_vect_1_d : VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE; + unsigned int next_shift_is_vect_1_q : VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE; + unsigned int input_data_xfer : VGT_DEBUG_REG6_input_data_xfer_SIZE; + unsigned int input_data_valid : VGT_DEBUG_REG6_input_data_valid_SIZE; + unsigned int right_word_indx_q : VGT_DEBUG_REG6_right_word_indx_q_SIZE; + unsigned int shifter_byte_count_q : VGT_DEBUG_REG6_shifter_byte_count_q_SIZE; + } vgt_debug_reg6_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg6_t f; +} vgt_debug_reg6_u; + + +/* + * VGT_DEBUG_REG7 struct + */ + +#define VGT_DEBUG_REG7_di_index_counter_q_SIZE 16 +#define VGT_DEBUG_REG7_shift_amount_no_extract_SIZE 4 +#define VGT_DEBUG_REG7_shift_amount_extract_SIZE 4 +#define VGT_DEBUG_REG7_di_prim_type_q_SIZE 6 +#define VGT_DEBUG_REG7_current_source_sel_SIZE 2 + +#define VGT_DEBUG_REG7_di_index_counter_q_SHIFT 0 +#define VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT 16 +#define VGT_DEBUG_REG7_shift_amount_extract_SHIFT 20 +#define VGT_DEBUG_REG7_di_prim_type_q_SHIFT 24 +#define VGT_DEBUG_REG7_current_source_sel_SHIFT 30 + +#define VGT_DEBUG_REG7_di_index_counter_q_MASK 0x0000ffff +#define VGT_DEBUG_REG7_shift_amount_no_extract_MASK 0x000f0000 +#define VGT_DEBUG_REG7_shift_amount_extract_MASK 0x00f00000 +#define VGT_DEBUG_REG7_di_prim_type_q_MASK 0x3f000000 +#define VGT_DEBUG_REG7_current_source_sel_MASK 0xc0000000 + +#define VGT_DEBUG_REG7_MASK \ + (VGT_DEBUG_REG7_di_index_counter_q_MASK | \ + VGT_DEBUG_REG7_shift_amount_no_extract_MASK | \ + VGT_DEBUG_REG7_shift_amount_extract_MASK | \ + VGT_DEBUG_REG7_di_prim_type_q_MASK | \ + VGT_DEBUG_REG7_current_source_sel_MASK) + +#define VGT_DEBUG_REG7(di_index_counter_q, shift_amount_no_extract, shift_amount_extract, di_prim_type_q, current_source_sel) \ + ((di_index_counter_q << VGT_DEBUG_REG7_di_index_counter_q_SHIFT) | \ + (shift_amount_no_extract << VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT) | \ + (shift_amount_extract << VGT_DEBUG_REG7_shift_amount_extract_SHIFT) | \ + (di_prim_type_q << VGT_DEBUG_REG7_di_prim_type_q_SHIFT) | \ + (current_source_sel << VGT_DEBUG_REG7_current_source_sel_SHIFT)) + +#define VGT_DEBUG_REG7_GET_di_index_counter_q(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_di_index_counter_q_MASK) >> VGT_DEBUG_REG7_di_index_counter_q_SHIFT) +#define VGT_DEBUG_REG7_GET_shift_amount_no_extract(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_shift_amount_no_extract_MASK) >> VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT) +#define VGT_DEBUG_REG7_GET_shift_amount_extract(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_shift_amount_extract_MASK) >> VGT_DEBUG_REG7_shift_amount_extract_SHIFT) +#define VGT_DEBUG_REG7_GET_di_prim_type_q(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_di_prim_type_q_MASK) >> VGT_DEBUG_REG7_di_prim_type_q_SHIFT) +#define VGT_DEBUG_REG7_GET_current_source_sel(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_current_source_sel_MASK) >> VGT_DEBUG_REG7_current_source_sel_SHIFT) + +#define VGT_DEBUG_REG7_SET_di_index_counter_q(vgt_debug_reg7_reg, di_index_counter_q) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_di_index_counter_q_MASK) | (di_index_counter_q << VGT_DEBUG_REG7_di_index_counter_q_SHIFT) +#define VGT_DEBUG_REG7_SET_shift_amount_no_extract(vgt_debug_reg7_reg, shift_amount_no_extract) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_shift_amount_no_extract_MASK) | (shift_amount_no_extract << VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT) +#define VGT_DEBUG_REG7_SET_shift_amount_extract(vgt_debug_reg7_reg, shift_amount_extract) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_shift_amount_extract_MASK) | (shift_amount_extract << VGT_DEBUG_REG7_shift_amount_extract_SHIFT) +#define VGT_DEBUG_REG7_SET_di_prim_type_q(vgt_debug_reg7_reg, di_prim_type_q) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_di_prim_type_q_MASK) | (di_prim_type_q << VGT_DEBUG_REG7_di_prim_type_q_SHIFT) +#define VGT_DEBUG_REG7_SET_current_source_sel(vgt_debug_reg7_reg, current_source_sel) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG7_current_source_sel_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg7_t { + unsigned int di_index_counter_q : VGT_DEBUG_REG7_di_index_counter_q_SIZE; + unsigned int shift_amount_no_extract : VGT_DEBUG_REG7_shift_amount_no_extract_SIZE; + unsigned int shift_amount_extract : VGT_DEBUG_REG7_shift_amount_extract_SIZE; + unsigned int di_prim_type_q : VGT_DEBUG_REG7_di_prim_type_q_SIZE; + unsigned int current_source_sel : VGT_DEBUG_REG7_current_source_sel_SIZE; + } vgt_debug_reg7_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg7_t { + unsigned int current_source_sel : VGT_DEBUG_REG7_current_source_sel_SIZE; + unsigned int di_prim_type_q : VGT_DEBUG_REG7_di_prim_type_q_SIZE; + unsigned int shift_amount_extract : VGT_DEBUG_REG7_shift_amount_extract_SIZE; + unsigned int shift_amount_no_extract : VGT_DEBUG_REG7_shift_amount_no_extract_SIZE; + unsigned int di_index_counter_q : VGT_DEBUG_REG7_di_index_counter_q_SIZE; + } vgt_debug_reg7_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg7_t f; +} vgt_debug_reg7_u; + + +/* + * VGT_DEBUG_REG8 struct + */ + +#define VGT_DEBUG_REG8_current_source_sel_SIZE 2 +#define VGT_DEBUG_REG8_left_word_indx_q_SIZE 5 +#define VGT_DEBUG_REG8_input_data_cnt_SIZE 5 +#define VGT_DEBUG_REG8_input_data_lsw_SIZE 5 +#define VGT_DEBUG_REG8_input_data_msw_SIZE 5 +#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE 5 +#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE 5 + +#define VGT_DEBUG_REG8_current_source_sel_SHIFT 0 +#define VGT_DEBUG_REG8_left_word_indx_q_SHIFT 2 +#define VGT_DEBUG_REG8_input_data_cnt_SHIFT 7 +#define VGT_DEBUG_REG8_input_data_lsw_SHIFT 12 +#define VGT_DEBUG_REG8_input_data_msw_SHIFT 17 +#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT 22 +#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT 27 + +#define VGT_DEBUG_REG8_current_source_sel_MASK 0x00000003 +#define VGT_DEBUG_REG8_left_word_indx_q_MASK 0x0000007c +#define VGT_DEBUG_REG8_input_data_cnt_MASK 0x00000f80 +#define VGT_DEBUG_REG8_input_data_lsw_MASK 0x0001f000 +#define VGT_DEBUG_REG8_input_data_msw_MASK 0x003e0000 +#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK 0x07c00000 +#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK 0xf8000000 + +#define VGT_DEBUG_REG8_MASK \ + (VGT_DEBUG_REG8_current_source_sel_MASK | \ + VGT_DEBUG_REG8_left_word_indx_q_MASK | \ + VGT_DEBUG_REG8_input_data_cnt_MASK | \ + VGT_DEBUG_REG8_input_data_lsw_MASK | \ + VGT_DEBUG_REG8_input_data_msw_MASK | \ + VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK | \ + VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) + +#define VGT_DEBUG_REG8(current_source_sel, left_word_indx_q, input_data_cnt, input_data_lsw, input_data_msw, next_small_stride_shift_limit_q, current_small_stride_shift_limit_q) \ + ((current_source_sel << VGT_DEBUG_REG8_current_source_sel_SHIFT) | \ + (left_word_indx_q << VGT_DEBUG_REG8_left_word_indx_q_SHIFT) | \ + (input_data_cnt << VGT_DEBUG_REG8_input_data_cnt_SHIFT) | \ + (input_data_lsw << VGT_DEBUG_REG8_input_data_lsw_SHIFT) | \ + (input_data_msw << VGT_DEBUG_REG8_input_data_msw_SHIFT) | \ + (next_small_stride_shift_limit_q << VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT) | \ + (current_small_stride_shift_limit_q << VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT)) + +#define VGT_DEBUG_REG8_GET_current_source_sel(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_current_source_sel_MASK) >> VGT_DEBUG_REG8_current_source_sel_SHIFT) +#define VGT_DEBUG_REG8_GET_left_word_indx_q(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_left_word_indx_q_MASK) >> VGT_DEBUG_REG8_left_word_indx_q_SHIFT) +#define VGT_DEBUG_REG8_GET_input_data_cnt(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_cnt_MASK) >> VGT_DEBUG_REG8_input_data_cnt_SHIFT) +#define VGT_DEBUG_REG8_GET_input_data_lsw(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_lsw_MASK) >> VGT_DEBUG_REG8_input_data_lsw_SHIFT) +#define VGT_DEBUG_REG8_GET_input_data_msw(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_msw_MASK) >> VGT_DEBUG_REG8_input_data_msw_SHIFT) +#define VGT_DEBUG_REG8_GET_next_small_stride_shift_limit_q(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT) +#define VGT_DEBUG_REG8_GET_current_small_stride_shift_limit_q(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT) + +#define VGT_DEBUG_REG8_SET_current_source_sel(vgt_debug_reg8_reg, current_source_sel) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG8_current_source_sel_SHIFT) +#define VGT_DEBUG_REG8_SET_left_word_indx_q(vgt_debug_reg8_reg, left_word_indx_q) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_left_word_indx_q_MASK) | (left_word_indx_q << VGT_DEBUG_REG8_left_word_indx_q_SHIFT) +#define VGT_DEBUG_REG8_SET_input_data_cnt(vgt_debug_reg8_reg, input_data_cnt) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_cnt_MASK) | (input_data_cnt << VGT_DEBUG_REG8_input_data_cnt_SHIFT) +#define VGT_DEBUG_REG8_SET_input_data_lsw(vgt_debug_reg8_reg, input_data_lsw) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_lsw_MASK) | (input_data_lsw << VGT_DEBUG_REG8_input_data_lsw_SHIFT) +#define VGT_DEBUG_REG8_SET_input_data_msw(vgt_debug_reg8_reg, input_data_msw) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_msw_MASK) | (input_data_msw << VGT_DEBUG_REG8_input_data_msw_SHIFT) +#define VGT_DEBUG_REG8_SET_next_small_stride_shift_limit_q(vgt_debug_reg8_reg, next_small_stride_shift_limit_q) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK) | (next_small_stride_shift_limit_q << VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT) +#define VGT_DEBUG_REG8_SET_current_small_stride_shift_limit_q(vgt_debug_reg8_reg, current_small_stride_shift_limit_q) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) | (current_small_stride_shift_limit_q << VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg8_t { + unsigned int current_source_sel : VGT_DEBUG_REG8_current_source_sel_SIZE; + unsigned int left_word_indx_q : VGT_DEBUG_REG8_left_word_indx_q_SIZE; + unsigned int input_data_cnt : VGT_DEBUG_REG8_input_data_cnt_SIZE; + unsigned int input_data_lsw : VGT_DEBUG_REG8_input_data_lsw_SIZE; + unsigned int input_data_msw : VGT_DEBUG_REG8_input_data_msw_SIZE; + unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE; + unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE; + } vgt_debug_reg8_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg8_t { + unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE; + unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE; + unsigned int input_data_msw : VGT_DEBUG_REG8_input_data_msw_SIZE; + unsigned int input_data_lsw : VGT_DEBUG_REG8_input_data_lsw_SIZE; + unsigned int input_data_cnt : VGT_DEBUG_REG8_input_data_cnt_SIZE; + unsigned int left_word_indx_q : VGT_DEBUG_REG8_left_word_indx_q_SIZE; + unsigned int current_source_sel : VGT_DEBUG_REG8_current_source_sel_SIZE; + } vgt_debug_reg8_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg8_t f; +} vgt_debug_reg8_u; + + +/* + * VGT_DEBUG_REG9 struct + */ + +#define VGT_DEBUG_REG9_next_stride_q_SIZE 5 +#define VGT_DEBUG_REG9_next_stride_d_SIZE 5 +#define VGT_DEBUG_REG9_current_shift_q_SIZE 5 +#define VGT_DEBUG_REG9_current_shift_d_SIZE 5 +#define VGT_DEBUG_REG9_current_stride_q_SIZE 5 +#define VGT_DEBUG_REG9_current_stride_d_SIZE 5 +#define VGT_DEBUG_REG9_grp_trigger_SIZE 1 + +#define VGT_DEBUG_REG9_next_stride_q_SHIFT 0 +#define VGT_DEBUG_REG9_next_stride_d_SHIFT 5 +#define VGT_DEBUG_REG9_current_shift_q_SHIFT 10 +#define VGT_DEBUG_REG9_current_shift_d_SHIFT 15 +#define VGT_DEBUG_REG9_current_stride_q_SHIFT 20 +#define VGT_DEBUG_REG9_current_stride_d_SHIFT 25 +#define VGT_DEBUG_REG9_grp_trigger_SHIFT 30 + +#define VGT_DEBUG_REG9_next_stride_q_MASK 0x0000001f +#define VGT_DEBUG_REG9_next_stride_d_MASK 0x000003e0 +#define VGT_DEBUG_REG9_current_shift_q_MASK 0x00007c00 +#define VGT_DEBUG_REG9_current_shift_d_MASK 0x000f8000 +#define VGT_DEBUG_REG9_current_stride_q_MASK 0x01f00000 +#define VGT_DEBUG_REG9_current_stride_d_MASK 0x3e000000 +#define VGT_DEBUG_REG9_grp_trigger_MASK 0x40000000 + +#define VGT_DEBUG_REG9_MASK \ + (VGT_DEBUG_REG9_next_stride_q_MASK | \ + VGT_DEBUG_REG9_next_stride_d_MASK | \ + VGT_DEBUG_REG9_current_shift_q_MASK | \ + VGT_DEBUG_REG9_current_shift_d_MASK | \ + VGT_DEBUG_REG9_current_stride_q_MASK | \ + VGT_DEBUG_REG9_current_stride_d_MASK | \ + VGT_DEBUG_REG9_grp_trigger_MASK) + +#define VGT_DEBUG_REG9(next_stride_q, next_stride_d, current_shift_q, current_shift_d, current_stride_q, current_stride_d, grp_trigger) \ + ((next_stride_q << VGT_DEBUG_REG9_next_stride_q_SHIFT) | \ + (next_stride_d << VGT_DEBUG_REG9_next_stride_d_SHIFT) | \ + (current_shift_q << VGT_DEBUG_REG9_current_shift_q_SHIFT) | \ + (current_shift_d << VGT_DEBUG_REG9_current_shift_d_SHIFT) | \ + (current_stride_q << VGT_DEBUG_REG9_current_stride_q_SHIFT) | \ + (current_stride_d << VGT_DEBUG_REG9_current_stride_d_SHIFT) | \ + (grp_trigger << VGT_DEBUG_REG9_grp_trigger_SHIFT)) + +#define VGT_DEBUG_REG9_GET_next_stride_q(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_next_stride_q_MASK) >> VGT_DEBUG_REG9_next_stride_q_SHIFT) +#define VGT_DEBUG_REG9_GET_next_stride_d(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_next_stride_d_MASK) >> VGT_DEBUG_REG9_next_stride_d_SHIFT) +#define VGT_DEBUG_REG9_GET_current_shift_q(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_shift_q_MASK) >> VGT_DEBUG_REG9_current_shift_q_SHIFT) +#define VGT_DEBUG_REG9_GET_current_shift_d(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_shift_d_MASK) >> VGT_DEBUG_REG9_current_shift_d_SHIFT) +#define VGT_DEBUG_REG9_GET_current_stride_q(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_stride_q_MASK) >> VGT_DEBUG_REG9_current_stride_q_SHIFT) +#define VGT_DEBUG_REG9_GET_current_stride_d(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_stride_d_MASK) >> VGT_DEBUG_REG9_current_stride_d_SHIFT) +#define VGT_DEBUG_REG9_GET_grp_trigger(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_grp_trigger_MASK) >> VGT_DEBUG_REG9_grp_trigger_SHIFT) + +#define VGT_DEBUG_REG9_SET_next_stride_q(vgt_debug_reg9_reg, next_stride_q) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_next_stride_q_MASK) | (next_stride_q << VGT_DEBUG_REG9_next_stride_q_SHIFT) +#define VGT_DEBUG_REG9_SET_next_stride_d(vgt_debug_reg9_reg, next_stride_d) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_next_stride_d_MASK) | (next_stride_d << VGT_DEBUG_REG9_next_stride_d_SHIFT) +#define VGT_DEBUG_REG9_SET_current_shift_q(vgt_debug_reg9_reg, current_shift_q) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_shift_q_MASK) | (current_shift_q << VGT_DEBUG_REG9_current_shift_q_SHIFT) +#define VGT_DEBUG_REG9_SET_current_shift_d(vgt_debug_reg9_reg, current_shift_d) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_shift_d_MASK) | (current_shift_d << VGT_DEBUG_REG9_current_shift_d_SHIFT) +#define VGT_DEBUG_REG9_SET_current_stride_q(vgt_debug_reg9_reg, current_stride_q) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_stride_q_MASK) | (current_stride_q << VGT_DEBUG_REG9_current_stride_q_SHIFT) +#define VGT_DEBUG_REG9_SET_current_stride_d(vgt_debug_reg9_reg, current_stride_d) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_stride_d_MASK) | (current_stride_d << VGT_DEBUG_REG9_current_stride_d_SHIFT) +#define VGT_DEBUG_REG9_SET_grp_trigger(vgt_debug_reg9_reg, grp_trigger) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG9_grp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg9_t { + unsigned int next_stride_q : VGT_DEBUG_REG9_next_stride_q_SIZE; + unsigned int next_stride_d : VGT_DEBUG_REG9_next_stride_d_SIZE; + unsigned int current_shift_q : VGT_DEBUG_REG9_current_shift_q_SIZE; + unsigned int current_shift_d : VGT_DEBUG_REG9_current_shift_d_SIZE; + unsigned int current_stride_q : VGT_DEBUG_REG9_current_stride_q_SIZE; + unsigned int current_stride_d : VGT_DEBUG_REG9_current_stride_d_SIZE; + unsigned int grp_trigger : VGT_DEBUG_REG9_grp_trigger_SIZE; + unsigned int : 1; + } vgt_debug_reg9_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg9_t { + unsigned int : 1; + unsigned int grp_trigger : VGT_DEBUG_REG9_grp_trigger_SIZE; + unsigned int current_stride_d : VGT_DEBUG_REG9_current_stride_d_SIZE; + unsigned int current_stride_q : VGT_DEBUG_REG9_current_stride_q_SIZE; + unsigned int current_shift_d : VGT_DEBUG_REG9_current_shift_d_SIZE; + unsigned int current_shift_q : VGT_DEBUG_REG9_current_shift_q_SIZE; + unsigned int next_stride_d : VGT_DEBUG_REG9_next_stride_d_SIZE; + unsigned int next_stride_q : VGT_DEBUG_REG9_next_stride_q_SIZE; + } vgt_debug_reg9_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg9_t f; +} vgt_debug_reg9_u; + + +/* + * VGT_DEBUG_REG10 struct + */ + +#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE 1 +#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE 1 +#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE 1 +#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE 1 +#define VGT_DEBUG_REG10_di_state_sel_q_SIZE 1 +#define VGT_DEBUG_REG10_last_decr_of_packet_SIZE 1 +#define VGT_DEBUG_REG10_bin_valid_SIZE 1 +#define VGT_DEBUG_REG10_read_block_SIZE 1 +#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE 1 +#define VGT_DEBUG_REG10_last_bit_enable_q_SIZE 1 +#define VGT_DEBUG_REG10_last_bit_end_di_q_SIZE 1 +#define VGT_DEBUG_REG10_selected_data_SIZE 8 +#define VGT_DEBUG_REG10_mask_input_data_SIZE 8 +#define VGT_DEBUG_REG10_gap_q_SIZE 1 +#define VGT_DEBUG_REG10_temp_mini_reset_z_SIZE 1 +#define VGT_DEBUG_REG10_temp_mini_reset_y_SIZE 1 +#define VGT_DEBUG_REG10_temp_mini_reset_x_SIZE 1 +#define VGT_DEBUG_REG10_grp_trigger_SIZE 1 + +#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT 0 +#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT 1 +#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT 2 +#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT 3 +#define VGT_DEBUG_REG10_di_state_sel_q_SHIFT 4 +#define VGT_DEBUG_REG10_last_decr_of_packet_SHIFT 5 +#define VGT_DEBUG_REG10_bin_valid_SHIFT 6 +#define VGT_DEBUG_REG10_read_block_SHIFT 7 +#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT 8 +#define VGT_DEBUG_REG10_last_bit_enable_q_SHIFT 9 +#define VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT 10 +#define VGT_DEBUG_REG10_selected_data_SHIFT 11 +#define VGT_DEBUG_REG10_mask_input_data_SHIFT 19 +#define VGT_DEBUG_REG10_gap_q_SHIFT 27 +#define VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT 28 +#define VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT 29 +#define VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT 30 +#define VGT_DEBUG_REG10_grp_trigger_SHIFT 31 + +#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK 0x00000001 +#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK 0x00000002 +#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK 0x00000004 +#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK 0x00000008 +#define VGT_DEBUG_REG10_di_state_sel_q_MASK 0x00000010 +#define VGT_DEBUG_REG10_last_decr_of_packet_MASK 0x00000020 +#define VGT_DEBUG_REG10_bin_valid_MASK 0x00000040 +#define VGT_DEBUG_REG10_read_block_MASK 0x00000080 +#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK 0x00000100 +#define VGT_DEBUG_REG10_last_bit_enable_q_MASK 0x00000200 +#define VGT_DEBUG_REG10_last_bit_end_di_q_MASK 0x00000400 +#define VGT_DEBUG_REG10_selected_data_MASK 0x0007f800 +#define VGT_DEBUG_REG10_mask_input_data_MASK 0x07f80000 +#define VGT_DEBUG_REG10_gap_q_MASK 0x08000000 +#define VGT_DEBUG_REG10_temp_mini_reset_z_MASK 0x10000000 +#define VGT_DEBUG_REG10_temp_mini_reset_y_MASK 0x20000000 +#define VGT_DEBUG_REG10_temp_mini_reset_x_MASK 0x40000000 +#define VGT_DEBUG_REG10_grp_trigger_MASK 0x80000000 + +#define VGT_DEBUG_REG10_MASK \ + (VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK | \ + VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK | \ + VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK | \ + VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK | \ + VGT_DEBUG_REG10_di_state_sel_q_MASK | \ + VGT_DEBUG_REG10_last_decr_of_packet_MASK | \ + VGT_DEBUG_REG10_bin_valid_MASK | \ + VGT_DEBUG_REG10_read_block_MASK | \ + VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK | \ + VGT_DEBUG_REG10_last_bit_enable_q_MASK | \ + VGT_DEBUG_REG10_last_bit_end_di_q_MASK | \ + VGT_DEBUG_REG10_selected_data_MASK | \ + VGT_DEBUG_REG10_mask_input_data_MASK | \ + VGT_DEBUG_REG10_gap_q_MASK | \ + VGT_DEBUG_REG10_temp_mini_reset_z_MASK | \ + VGT_DEBUG_REG10_temp_mini_reset_y_MASK | \ + VGT_DEBUG_REG10_temp_mini_reset_x_MASK | \ + VGT_DEBUG_REG10_grp_trigger_MASK) + +#define VGT_DEBUG_REG10(temp_derived_di_prim_type_t0, temp_derived_di_small_index_t0, temp_derived_di_cull_enable_t0, temp_derived_di_pre_fetch_cull_enable_t0, di_state_sel_q, last_decr_of_packet, bin_valid, read_block, grp_bgrp_last_bit_read, last_bit_enable_q, last_bit_end_di_q, selected_data, mask_input_data, gap_q, temp_mini_reset_z, temp_mini_reset_y, temp_mini_reset_x, grp_trigger) \ + ((temp_derived_di_prim_type_t0 << VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT) | \ + (temp_derived_di_small_index_t0 << VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT) | \ + (temp_derived_di_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT) | \ + (temp_derived_di_pre_fetch_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT) | \ + (di_state_sel_q << VGT_DEBUG_REG10_di_state_sel_q_SHIFT) | \ + (last_decr_of_packet << VGT_DEBUG_REG10_last_decr_of_packet_SHIFT) | \ + (bin_valid << VGT_DEBUG_REG10_bin_valid_SHIFT) | \ + (read_block << VGT_DEBUG_REG10_read_block_SHIFT) | \ + (grp_bgrp_last_bit_read << VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT) | \ + (last_bit_enable_q << VGT_DEBUG_REG10_last_bit_enable_q_SHIFT) | \ + (last_bit_end_di_q << VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT) | \ + (selected_data << VGT_DEBUG_REG10_selected_data_SHIFT) | \ + (mask_input_data << VGT_DEBUG_REG10_mask_input_data_SHIFT) | \ + (gap_q << VGT_DEBUG_REG10_gap_q_SHIFT) | \ + (temp_mini_reset_z << VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT) | \ + (temp_mini_reset_y << VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT) | \ + (temp_mini_reset_x << VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT) | \ + (grp_trigger << VGT_DEBUG_REG10_grp_trigger_SHIFT)) + +#define VGT_DEBUG_REG10_GET_temp_derived_di_prim_type_t0(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_derived_di_small_index_t0(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_derived_di_cull_enable_t0(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_derived_di_pre_fetch_cull_enable_t0(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT) +#define VGT_DEBUG_REG10_GET_di_state_sel_q(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_di_state_sel_q_MASK) >> VGT_DEBUG_REG10_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG10_GET_last_decr_of_packet(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_decr_of_packet_MASK) >> VGT_DEBUG_REG10_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG10_GET_bin_valid(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_bin_valid_MASK) >> VGT_DEBUG_REG10_bin_valid_SHIFT) +#define VGT_DEBUG_REG10_GET_read_block(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_read_block_MASK) >> VGT_DEBUG_REG10_read_block_SHIFT) +#define VGT_DEBUG_REG10_GET_grp_bgrp_last_bit_read(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK) >> VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT) +#define VGT_DEBUG_REG10_GET_last_bit_enable_q(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_bit_enable_q_MASK) >> VGT_DEBUG_REG10_last_bit_enable_q_SHIFT) +#define VGT_DEBUG_REG10_GET_last_bit_end_di_q(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_bit_end_di_q_MASK) >> VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT) +#define VGT_DEBUG_REG10_GET_selected_data(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_selected_data_MASK) >> VGT_DEBUG_REG10_selected_data_SHIFT) +#define VGT_DEBUG_REG10_GET_mask_input_data(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_mask_input_data_MASK) >> VGT_DEBUG_REG10_mask_input_data_SHIFT) +#define VGT_DEBUG_REG10_GET_gap_q(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_gap_q_MASK) >> VGT_DEBUG_REG10_gap_q_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_mini_reset_z(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_z_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_mini_reset_y(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_y_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_mini_reset_x(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_x_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT) +#define VGT_DEBUG_REG10_GET_grp_trigger(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_grp_trigger_MASK) >> VGT_DEBUG_REG10_grp_trigger_SHIFT) + +#define VGT_DEBUG_REG10_SET_temp_derived_di_prim_type_t0(vgt_debug_reg10_reg, temp_derived_di_prim_type_t0) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK) | (temp_derived_di_prim_type_t0 << VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_derived_di_small_index_t0(vgt_debug_reg10_reg, temp_derived_di_small_index_t0) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK) | (temp_derived_di_small_index_t0 << VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_derived_di_cull_enable_t0(vgt_debug_reg10_reg, temp_derived_di_cull_enable_t0) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK) | (temp_derived_di_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_derived_di_pre_fetch_cull_enable_t0(vgt_debug_reg10_reg, temp_derived_di_pre_fetch_cull_enable_t0) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK) | (temp_derived_di_pre_fetch_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT) +#define VGT_DEBUG_REG10_SET_di_state_sel_q(vgt_debug_reg10_reg, di_state_sel_q) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG10_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG10_SET_last_decr_of_packet(vgt_debug_reg10_reg, last_decr_of_packet) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG10_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG10_SET_bin_valid(vgt_debug_reg10_reg, bin_valid) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_bin_valid_MASK) | (bin_valid << VGT_DEBUG_REG10_bin_valid_SHIFT) +#define VGT_DEBUG_REG10_SET_read_block(vgt_debug_reg10_reg, read_block) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_read_block_MASK) | (read_block << VGT_DEBUG_REG10_read_block_SHIFT) +#define VGT_DEBUG_REG10_SET_grp_bgrp_last_bit_read(vgt_debug_reg10_reg, grp_bgrp_last_bit_read) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK) | (grp_bgrp_last_bit_read << VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT) +#define VGT_DEBUG_REG10_SET_last_bit_enable_q(vgt_debug_reg10_reg, last_bit_enable_q) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_bit_enable_q_MASK) | (last_bit_enable_q << VGT_DEBUG_REG10_last_bit_enable_q_SHIFT) +#define VGT_DEBUG_REG10_SET_last_bit_end_di_q(vgt_debug_reg10_reg, last_bit_end_di_q) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_bit_end_di_q_MASK) | (last_bit_end_di_q << VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT) +#define VGT_DEBUG_REG10_SET_selected_data(vgt_debug_reg10_reg, selected_data) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_selected_data_MASK) | (selected_data << VGT_DEBUG_REG10_selected_data_SHIFT) +#define VGT_DEBUG_REG10_SET_mask_input_data(vgt_debug_reg10_reg, mask_input_data) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_mask_input_data_MASK) | (mask_input_data << VGT_DEBUG_REG10_mask_input_data_SHIFT) +#define VGT_DEBUG_REG10_SET_gap_q(vgt_debug_reg10_reg, gap_q) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_gap_q_MASK) | (gap_q << VGT_DEBUG_REG10_gap_q_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_mini_reset_z(vgt_debug_reg10_reg, temp_mini_reset_z) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_z_MASK) | (temp_mini_reset_z << VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_mini_reset_y(vgt_debug_reg10_reg, temp_mini_reset_y) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_y_MASK) | (temp_mini_reset_y << VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_mini_reset_x(vgt_debug_reg10_reg, temp_mini_reset_x) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_x_MASK) | (temp_mini_reset_x << VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT) +#define VGT_DEBUG_REG10_SET_grp_trigger(vgt_debug_reg10_reg, grp_trigger) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG10_grp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg10_t { + unsigned int temp_derived_di_prim_type_t0 : VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE; + unsigned int temp_derived_di_small_index_t0 : VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE; + unsigned int temp_derived_di_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE; + unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG10_di_state_sel_q_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG10_last_decr_of_packet_SIZE; + unsigned int bin_valid : VGT_DEBUG_REG10_bin_valid_SIZE; + unsigned int read_block : VGT_DEBUG_REG10_read_block_SIZE; + unsigned int grp_bgrp_last_bit_read : VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE; + unsigned int last_bit_enable_q : VGT_DEBUG_REG10_last_bit_enable_q_SIZE; + unsigned int last_bit_end_di_q : VGT_DEBUG_REG10_last_bit_end_di_q_SIZE; + unsigned int selected_data : VGT_DEBUG_REG10_selected_data_SIZE; + unsigned int mask_input_data : VGT_DEBUG_REG10_mask_input_data_SIZE; + unsigned int gap_q : VGT_DEBUG_REG10_gap_q_SIZE; + unsigned int temp_mini_reset_z : VGT_DEBUG_REG10_temp_mini_reset_z_SIZE; + unsigned int temp_mini_reset_y : VGT_DEBUG_REG10_temp_mini_reset_y_SIZE; + unsigned int temp_mini_reset_x : VGT_DEBUG_REG10_temp_mini_reset_x_SIZE; + unsigned int grp_trigger : VGT_DEBUG_REG10_grp_trigger_SIZE; + } vgt_debug_reg10_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg10_t { + unsigned int grp_trigger : VGT_DEBUG_REG10_grp_trigger_SIZE; + unsigned int temp_mini_reset_x : VGT_DEBUG_REG10_temp_mini_reset_x_SIZE; + unsigned int temp_mini_reset_y : VGT_DEBUG_REG10_temp_mini_reset_y_SIZE; + unsigned int temp_mini_reset_z : VGT_DEBUG_REG10_temp_mini_reset_z_SIZE; + unsigned int gap_q : VGT_DEBUG_REG10_gap_q_SIZE; + unsigned int mask_input_data : VGT_DEBUG_REG10_mask_input_data_SIZE; + unsigned int selected_data : VGT_DEBUG_REG10_selected_data_SIZE; + unsigned int last_bit_end_di_q : VGT_DEBUG_REG10_last_bit_end_di_q_SIZE; + unsigned int last_bit_enable_q : VGT_DEBUG_REG10_last_bit_enable_q_SIZE; + unsigned int grp_bgrp_last_bit_read : VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE; + unsigned int read_block : VGT_DEBUG_REG10_read_block_SIZE; + unsigned int bin_valid : VGT_DEBUG_REG10_bin_valid_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG10_last_decr_of_packet_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG10_di_state_sel_q_SIZE; + unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE; + unsigned int temp_derived_di_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE; + unsigned int temp_derived_di_small_index_t0 : VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE; + unsigned int temp_derived_di_prim_type_t0 : VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE; + } vgt_debug_reg10_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg10_t f; +} vgt_debug_reg10_u; + + +/* + * VGT_DEBUG_REG12 struct + */ + +#define VGT_DEBUG_REG12_shifter_byte_count_q_SIZE 5 +#define VGT_DEBUG_REG12_right_word_indx_q_SIZE 5 +#define VGT_DEBUG_REG12_input_data_valid_SIZE 1 +#define VGT_DEBUG_REG12_input_data_xfer_SIZE 1 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE 1 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE 1 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE 1 +#define VGT_DEBUG_REG12_space_avail_from_shift_SIZE 1 +#define VGT_DEBUG_REG12_shifter_first_load_SIZE 1 +#define VGT_DEBUG_REG12_di_state_sel_q_SIZE 1 +#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE 1 +#define VGT_DEBUG_REG12_di_first_group_flag_q_SIZE 1 +#define VGT_DEBUG_REG12_di_event_flag_q_SIZE 1 +#define VGT_DEBUG_REG12_read_draw_initiator_SIZE 1 +#define VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE 1 +#define VGT_DEBUG_REG12_last_shift_of_packet_SIZE 1 +#define VGT_DEBUG_REG12_last_decr_of_packet_SIZE 1 +#define VGT_DEBUG_REG12_extract_vector_SIZE 1 +#define VGT_DEBUG_REG12_shift_vect_rtr_SIZE 1 +#define VGT_DEBUG_REG12_destination_rtr_SIZE 1 +#define VGT_DEBUG_REG12_bgrp_trigger_SIZE 1 + +#define VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT 0 +#define VGT_DEBUG_REG12_right_word_indx_q_SHIFT 5 +#define VGT_DEBUG_REG12_input_data_valid_SHIFT 10 +#define VGT_DEBUG_REG12_input_data_xfer_SHIFT 11 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT 12 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT 13 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT 14 +#define VGT_DEBUG_REG12_space_avail_from_shift_SHIFT 15 +#define VGT_DEBUG_REG12_shifter_first_load_SHIFT 16 +#define VGT_DEBUG_REG12_di_state_sel_q_SHIFT 17 +#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT 18 +#define VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT 19 +#define VGT_DEBUG_REG12_di_event_flag_q_SHIFT 20 +#define VGT_DEBUG_REG12_read_draw_initiator_SHIFT 21 +#define VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT 22 +#define VGT_DEBUG_REG12_last_shift_of_packet_SHIFT 23 +#define VGT_DEBUG_REG12_last_decr_of_packet_SHIFT 24 +#define VGT_DEBUG_REG12_extract_vector_SHIFT 25 +#define VGT_DEBUG_REG12_shift_vect_rtr_SHIFT 26 +#define VGT_DEBUG_REG12_destination_rtr_SHIFT 27 +#define VGT_DEBUG_REG12_bgrp_trigger_SHIFT 28 + +#define VGT_DEBUG_REG12_shifter_byte_count_q_MASK 0x0000001f +#define VGT_DEBUG_REG12_right_word_indx_q_MASK 0x000003e0 +#define VGT_DEBUG_REG12_input_data_valid_MASK 0x00000400 +#define VGT_DEBUG_REG12_input_data_xfer_MASK 0x00000800 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK 0x00001000 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK 0x00002000 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK 0x00004000 +#define VGT_DEBUG_REG12_space_avail_from_shift_MASK 0x00008000 +#define VGT_DEBUG_REG12_shifter_first_load_MASK 0x00010000 +#define VGT_DEBUG_REG12_di_state_sel_q_MASK 0x00020000 +#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK 0x00040000 +#define VGT_DEBUG_REG12_di_first_group_flag_q_MASK 0x00080000 +#define VGT_DEBUG_REG12_di_event_flag_q_MASK 0x00100000 +#define VGT_DEBUG_REG12_read_draw_initiator_MASK 0x00200000 +#define VGT_DEBUG_REG12_loading_di_requires_shifter_MASK 0x00400000 +#define VGT_DEBUG_REG12_last_shift_of_packet_MASK 0x00800000 +#define VGT_DEBUG_REG12_last_decr_of_packet_MASK 0x01000000 +#define VGT_DEBUG_REG12_extract_vector_MASK 0x02000000 +#define VGT_DEBUG_REG12_shift_vect_rtr_MASK 0x04000000 +#define VGT_DEBUG_REG12_destination_rtr_MASK 0x08000000 +#define VGT_DEBUG_REG12_bgrp_trigger_MASK 0x10000000 + +#define VGT_DEBUG_REG12_MASK \ + (VGT_DEBUG_REG12_shifter_byte_count_q_MASK | \ + VGT_DEBUG_REG12_right_word_indx_q_MASK | \ + VGT_DEBUG_REG12_input_data_valid_MASK | \ + VGT_DEBUG_REG12_input_data_xfer_MASK | \ + VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK | \ + VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK | \ + VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK | \ + VGT_DEBUG_REG12_space_avail_from_shift_MASK | \ + VGT_DEBUG_REG12_shifter_first_load_MASK | \ + VGT_DEBUG_REG12_di_state_sel_q_MASK | \ + VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK | \ + VGT_DEBUG_REG12_di_first_group_flag_q_MASK | \ + VGT_DEBUG_REG12_di_event_flag_q_MASK | \ + VGT_DEBUG_REG12_read_draw_initiator_MASK | \ + VGT_DEBUG_REG12_loading_di_requires_shifter_MASK | \ + VGT_DEBUG_REG12_last_shift_of_packet_MASK | \ + VGT_DEBUG_REG12_last_decr_of_packet_MASK | \ + VGT_DEBUG_REG12_extract_vector_MASK | \ + VGT_DEBUG_REG12_shift_vect_rtr_MASK | \ + VGT_DEBUG_REG12_destination_rtr_MASK | \ + VGT_DEBUG_REG12_bgrp_trigger_MASK) + +#define VGT_DEBUG_REG12(shifter_byte_count_q, right_word_indx_q, input_data_valid, input_data_xfer, next_shift_is_vect_1_q, next_shift_is_vect_1_d, next_shift_is_vect_1_pre_d, space_avail_from_shift, shifter_first_load, di_state_sel_q, shifter_waiting_for_first_load_q, di_first_group_flag_q, di_event_flag_q, read_draw_initiator, loading_di_requires_shifter, last_shift_of_packet, last_decr_of_packet, extract_vector, shift_vect_rtr, destination_rtr, bgrp_trigger) \ + ((shifter_byte_count_q << VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT) | \ + (right_word_indx_q << VGT_DEBUG_REG12_right_word_indx_q_SHIFT) | \ + (input_data_valid << VGT_DEBUG_REG12_input_data_valid_SHIFT) | \ + (input_data_xfer << VGT_DEBUG_REG12_input_data_xfer_SHIFT) | \ + (next_shift_is_vect_1_q << VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT) | \ + (next_shift_is_vect_1_d << VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT) | \ + (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT) | \ + (space_avail_from_shift << VGT_DEBUG_REG12_space_avail_from_shift_SHIFT) | \ + (shifter_first_load << VGT_DEBUG_REG12_shifter_first_load_SHIFT) | \ + (di_state_sel_q << VGT_DEBUG_REG12_di_state_sel_q_SHIFT) | \ + (shifter_waiting_for_first_load_q << VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT) | \ + (di_first_group_flag_q << VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT) | \ + (di_event_flag_q << VGT_DEBUG_REG12_di_event_flag_q_SHIFT) | \ + (read_draw_initiator << VGT_DEBUG_REG12_read_draw_initiator_SHIFT) | \ + (loading_di_requires_shifter << VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT) | \ + (last_shift_of_packet << VGT_DEBUG_REG12_last_shift_of_packet_SHIFT) | \ + (last_decr_of_packet << VGT_DEBUG_REG12_last_decr_of_packet_SHIFT) | \ + (extract_vector << VGT_DEBUG_REG12_extract_vector_SHIFT) | \ + (shift_vect_rtr << VGT_DEBUG_REG12_shift_vect_rtr_SHIFT) | \ + (destination_rtr << VGT_DEBUG_REG12_destination_rtr_SHIFT) | \ + (bgrp_trigger << VGT_DEBUG_REG12_bgrp_trigger_SHIFT)) + +#define VGT_DEBUG_REG12_GET_shifter_byte_count_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_byte_count_q_MASK) >> VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT) +#define VGT_DEBUG_REG12_GET_right_word_indx_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_right_word_indx_q_MASK) >> VGT_DEBUG_REG12_right_word_indx_q_SHIFT) +#define VGT_DEBUG_REG12_GET_input_data_valid(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_input_data_valid_MASK) >> VGT_DEBUG_REG12_input_data_valid_SHIFT) +#define VGT_DEBUG_REG12_GET_input_data_xfer(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_input_data_xfer_MASK) >> VGT_DEBUG_REG12_input_data_xfer_SHIFT) +#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT) +#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_d(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT) +#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_pre_d(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT) +#define VGT_DEBUG_REG12_GET_space_avail_from_shift(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_space_avail_from_shift_MASK) >> VGT_DEBUG_REG12_space_avail_from_shift_SHIFT) +#define VGT_DEBUG_REG12_GET_shifter_first_load(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_first_load_MASK) >> VGT_DEBUG_REG12_shifter_first_load_SHIFT) +#define VGT_DEBUG_REG12_GET_di_state_sel_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_state_sel_q_MASK) >> VGT_DEBUG_REG12_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG12_GET_shifter_waiting_for_first_load_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK) >> VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT) +#define VGT_DEBUG_REG12_GET_di_first_group_flag_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_first_group_flag_q_MASK) >> VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT) +#define VGT_DEBUG_REG12_GET_di_event_flag_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_event_flag_q_MASK) >> VGT_DEBUG_REG12_di_event_flag_q_SHIFT) +#define VGT_DEBUG_REG12_GET_read_draw_initiator(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_read_draw_initiator_MASK) >> VGT_DEBUG_REG12_read_draw_initiator_SHIFT) +#define VGT_DEBUG_REG12_GET_loading_di_requires_shifter(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_loading_di_requires_shifter_MASK) >> VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT) +#define VGT_DEBUG_REG12_GET_last_shift_of_packet(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_last_shift_of_packet_MASK) >> VGT_DEBUG_REG12_last_shift_of_packet_SHIFT) +#define VGT_DEBUG_REG12_GET_last_decr_of_packet(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_last_decr_of_packet_MASK) >> VGT_DEBUG_REG12_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG12_GET_extract_vector(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_extract_vector_MASK) >> VGT_DEBUG_REG12_extract_vector_SHIFT) +#define VGT_DEBUG_REG12_GET_shift_vect_rtr(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_shift_vect_rtr_MASK) >> VGT_DEBUG_REG12_shift_vect_rtr_SHIFT) +#define VGT_DEBUG_REG12_GET_destination_rtr(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_destination_rtr_MASK) >> VGT_DEBUG_REG12_destination_rtr_SHIFT) +#define VGT_DEBUG_REG12_GET_bgrp_trigger(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_bgrp_trigger_MASK) >> VGT_DEBUG_REG12_bgrp_trigger_SHIFT) + +#define VGT_DEBUG_REG12_SET_shifter_byte_count_q(vgt_debug_reg12_reg, shifter_byte_count_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_byte_count_q_MASK) | (shifter_byte_count_q << VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT) +#define VGT_DEBUG_REG12_SET_right_word_indx_q(vgt_debug_reg12_reg, right_word_indx_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_right_word_indx_q_MASK) | (right_word_indx_q << VGT_DEBUG_REG12_right_word_indx_q_SHIFT) +#define VGT_DEBUG_REG12_SET_input_data_valid(vgt_debug_reg12_reg, input_data_valid) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_input_data_valid_MASK) | (input_data_valid << VGT_DEBUG_REG12_input_data_valid_SHIFT) +#define VGT_DEBUG_REG12_SET_input_data_xfer(vgt_debug_reg12_reg, input_data_xfer) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_input_data_xfer_MASK) | (input_data_xfer << VGT_DEBUG_REG12_input_data_xfer_SHIFT) +#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_q(vgt_debug_reg12_reg, next_shift_is_vect_1_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK) | (next_shift_is_vect_1_q << VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT) +#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_d(vgt_debug_reg12_reg, next_shift_is_vect_1_d) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK) | (next_shift_is_vect_1_d << VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT) +#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_pre_d(vgt_debug_reg12_reg, next_shift_is_vect_1_pre_d) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK) | (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT) +#define VGT_DEBUG_REG12_SET_space_avail_from_shift(vgt_debug_reg12_reg, space_avail_from_shift) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_space_avail_from_shift_MASK) | (space_avail_from_shift << VGT_DEBUG_REG12_space_avail_from_shift_SHIFT) +#define VGT_DEBUG_REG12_SET_shifter_first_load(vgt_debug_reg12_reg, shifter_first_load) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_first_load_MASK) | (shifter_first_load << VGT_DEBUG_REG12_shifter_first_load_SHIFT) +#define VGT_DEBUG_REG12_SET_di_state_sel_q(vgt_debug_reg12_reg, di_state_sel_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG12_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG12_SET_shifter_waiting_for_first_load_q(vgt_debug_reg12_reg, shifter_waiting_for_first_load_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK) | (shifter_waiting_for_first_load_q << VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT) +#define VGT_DEBUG_REG12_SET_di_first_group_flag_q(vgt_debug_reg12_reg, di_first_group_flag_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_first_group_flag_q_MASK) | (di_first_group_flag_q << VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT) +#define VGT_DEBUG_REG12_SET_di_event_flag_q(vgt_debug_reg12_reg, di_event_flag_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_event_flag_q_MASK) | (di_event_flag_q << VGT_DEBUG_REG12_di_event_flag_q_SHIFT) +#define VGT_DEBUG_REG12_SET_read_draw_initiator(vgt_debug_reg12_reg, read_draw_initiator) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_read_draw_initiator_MASK) | (read_draw_initiator << VGT_DEBUG_REG12_read_draw_initiator_SHIFT) +#define VGT_DEBUG_REG12_SET_loading_di_requires_shifter(vgt_debug_reg12_reg, loading_di_requires_shifter) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_loading_di_requires_shifter_MASK) | (loading_di_requires_shifter << VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT) +#define VGT_DEBUG_REG12_SET_last_shift_of_packet(vgt_debug_reg12_reg, last_shift_of_packet) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_last_shift_of_packet_MASK) | (last_shift_of_packet << VGT_DEBUG_REG12_last_shift_of_packet_SHIFT) +#define VGT_DEBUG_REG12_SET_last_decr_of_packet(vgt_debug_reg12_reg, last_decr_of_packet) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG12_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG12_SET_extract_vector(vgt_debug_reg12_reg, extract_vector) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_extract_vector_MASK) | (extract_vector << VGT_DEBUG_REG12_extract_vector_SHIFT) +#define VGT_DEBUG_REG12_SET_shift_vect_rtr(vgt_debug_reg12_reg, shift_vect_rtr) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shift_vect_rtr_MASK) | (shift_vect_rtr << VGT_DEBUG_REG12_shift_vect_rtr_SHIFT) +#define VGT_DEBUG_REG12_SET_destination_rtr(vgt_debug_reg12_reg, destination_rtr) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_destination_rtr_MASK) | (destination_rtr << VGT_DEBUG_REG12_destination_rtr_SHIFT) +#define VGT_DEBUG_REG12_SET_bgrp_trigger(vgt_debug_reg12_reg, bgrp_trigger) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG12_bgrp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg12_t { + unsigned int shifter_byte_count_q : VGT_DEBUG_REG12_shifter_byte_count_q_SIZE; + unsigned int right_word_indx_q : VGT_DEBUG_REG12_right_word_indx_q_SIZE; + unsigned int input_data_valid : VGT_DEBUG_REG12_input_data_valid_SIZE; + unsigned int input_data_xfer : VGT_DEBUG_REG12_input_data_xfer_SIZE; + unsigned int next_shift_is_vect_1_q : VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE; + unsigned int next_shift_is_vect_1_d : VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE; + unsigned int next_shift_is_vect_1_pre_d : VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE; + unsigned int space_avail_from_shift : VGT_DEBUG_REG12_space_avail_from_shift_SIZE; + unsigned int shifter_first_load : VGT_DEBUG_REG12_shifter_first_load_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG12_di_state_sel_q_SIZE; + unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE; + unsigned int di_first_group_flag_q : VGT_DEBUG_REG12_di_first_group_flag_q_SIZE; + unsigned int di_event_flag_q : VGT_DEBUG_REG12_di_event_flag_q_SIZE; + unsigned int read_draw_initiator : VGT_DEBUG_REG12_read_draw_initiator_SIZE; + unsigned int loading_di_requires_shifter : VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE; + unsigned int last_shift_of_packet : VGT_DEBUG_REG12_last_shift_of_packet_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG12_last_decr_of_packet_SIZE; + unsigned int extract_vector : VGT_DEBUG_REG12_extract_vector_SIZE; + unsigned int shift_vect_rtr : VGT_DEBUG_REG12_shift_vect_rtr_SIZE; + unsigned int destination_rtr : VGT_DEBUG_REG12_destination_rtr_SIZE; + unsigned int bgrp_trigger : VGT_DEBUG_REG12_bgrp_trigger_SIZE; + unsigned int : 3; + } vgt_debug_reg12_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg12_t { + unsigned int : 3; + unsigned int bgrp_trigger : VGT_DEBUG_REG12_bgrp_trigger_SIZE; + unsigned int destination_rtr : VGT_DEBUG_REG12_destination_rtr_SIZE; + unsigned int shift_vect_rtr : VGT_DEBUG_REG12_shift_vect_rtr_SIZE; + unsigned int extract_vector : VGT_DEBUG_REG12_extract_vector_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG12_last_decr_of_packet_SIZE; + unsigned int last_shift_of_packet : VGT_DEBUG_REG12_last_shift_of_packet_SIZE; + unsigned int loading_di_requires_shifter : VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE; + unsigned int read_draw_initiator : VGT_DEBUG_REG12_read_draw_initiator_SIZE; + unsigned int di_event_flag_q : VGT_DEBUG_REG12_di_event_flag_q_SIZE; + unsigned int di_first_group_flag_q : VGT_DEBUG_REG12_di_first_group_flag_q_SIZE; + unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG12_di_state_sel_q_SIZE; + unsigned int shifter_first_load : VGT_DEBUG_REG12_shifter_first_load_SIZE; + unsigned int space_avail_from_shift : VGT_DEBUG_REG12_space_avail_from_shift_SIZE; + unsigned int next_shift_is_vect_1_pre_d : VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE; + unsigned int next_shift_is_vect_1_d : VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE; + unsigned int next_shift_is_vect_1_q : VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE; + unsigned int input_data_xfer : VGT_DEBUG_REG12_input_data_xfer_SIZE; + unsigned int input_data_valid : VGT_DEBUG_REG12_input_data_valid_SIZE; + unsigned int right_word_indx_q : VGT_DEBUG_REG12_right_word_indx_q_SIZE; + unsigned int shifter_byte_count_q : VGT_DEBUG_REG12_shifter_byte_count_q_SIZE; + } vgt_debug_reg12_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg12_t f; +} vgt_debug_reg12_u; + + +/* + * VGT_DEBUG_REG13 struct + */ + +#define VGT_DEBUG_REG13_di_index_counter_q_SIZE 16 +#define VGT_DEBUG_REG13_shift_amount_no_extract_SIZE 4 +#define VGT_DEBUG_REG13_shift_amount_extract_SIZE 4 +#define VGT_DEBUG_REG13_di_prim_type_q_SIZE 6 +#define VGT_DEBUG_REG13_current_source_sel_SIZE 2 + +#define VGT_DEBUG_REG13_di_index_counter_q_SHIFT 0 +#define VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT 16 +#define VGT_DEBUG_REG13_shift_amount_extract_SHIFT 20 +#define VGT_DEBUG_REG13_di_prim_type_q_SHIFT 24 +#define VGT_DEBUG_REG13_current_source_sel_SHIFT 30 + +#define VGT_DEBUG_REG13_di_index_counter_q_MASK 0x0000ffff +#define VGT_DEBUG_REG13_shift_amount_no_extract_MASK 0x000f0000 +#define VGT_DEBUG_REG13_shift_amount_extract_MASK 0x00f00000 +#define VGT_DEBUG_REG13_di_prim_type_q_MASK 0x3f000000 +#define VGT_DEBUG_REG13_current_source_sel_MASK 0xc0000000 + +#define VGT_DEBUG_REG13_MASK \ + (VGT_DEBUG_REG13_di_index_counter_q_MASK | \ + VGT_DEBUG_REG13_shift_amount_no_extract_MASK | \ + VGT_DEBUG_REG13_shift_amount_extract_MASK | \ + VGT_DEBUG_REG13_di_prim_type_q_MASK | \ + VGT_DEBUG_REG13_current_source_sel_MASK) + +#define VGT_DEBUG_REG13(di_index_counter_q, shift_amount_no_extract, shift_amount_extract, di_prim_type_q, current_source_sel) \ + ((di_index_counter_q << VGT_DEBUG_REG13_di_index_counter_q_SHIFT) | \ + (shift_amount_no_extract << VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT) | \ + (shift_amount_extract << VGT_DEBUG_REG13_shift_amount_extract_SHIFT) | \ + (di_prim_type_q << VGT_DEBUG_REG13_di_prim_type_q_SHIFT) | \ + (current_source_sel << VGT_DEBUG_REG13_current_source_sel_SHIFT)) + +#define VGT_DEBUG_REG13_GET_di_index_counter_q(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_di_index_counter_q_MASK) >> VGT_DEBUG_REG13_di_index_counter_q_SHIFT) +#define VGT_DEBUG_REG13_GET_shift_amount_no_extract(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_shift_amount_no_extract_MASK) >> VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT) +#define VGT_DEBUG_REG13_GET_shift_amount_extract(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_shift_amount_extract_MASK) >> VGT_DEBUG_REG13_shift_amount_extract_SHIFT) +#define VGT_DEBUG_REG13_GET_di_prim_type_q(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_di_prim_type_q_MASK) >> VGT_DEBUG_REG13_di_prim_type_q_SHIFT) +#define VGT_DEBUG_REG13_GET_current_source_sel(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_current_source_sel_MASK) >> VGT_DEBUG_REG13_current_source_sel_SHIFT) + +#define VGT_DEBUG_REG13_SET_di_index_counter_q(vgt_debug_reg13_reg, di_index_counter_q) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_di_index_counter_q_MASK) | (di_index_counter_q << VGT_DEBUG_REG13_di_index_counter_q_SHIFT) +#define VGT_DEBUG_REG13_SET_shift_amount_no_extract(vgt_debug_reg13_reg, shift_amount_no_extract) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_shift_amount_no_extract_MASK) | (shift_amount_no_extract << VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT) +#define VGT_DEBUG_REG13_SET_shift_amount_extract(vgt_debug_reg13_reg, shift_amount_extract) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_shift_amount_extract_MASK) | (shift_amount_extract << VGT_DEBUG_REG13_shift_amount_extract_SHIFT) +#define VGT_DEBUG_REG13_SET_di_prim_type_q(vgt_debug_reg13_reg, di_prim_type_q) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_di_prim_type_q_MASK) | (di_prim_type_q << VGT_DEBUG_REG13_di_prim_type_q_SHIFT) +#define VGT_DEBUG_REG13_SET_current_source_sel(vgt_debug_reg13_reg, current_source_sel) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG13_current_source_sel_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg13_t { + unsigned int di_index_counter_q : VGT_DEBUG_REG13_di_index_counter_q_SIZE; + unsigned int shift_amount_no_extract : VGT_DEBUG_REG13_shift_amount_no_extract_SIZE; + unsigned int shift_amount_extract : VGT_DEBUG_REG13_shift_amount_extract_SIZE; + unsigned int di_prim_type_q : VGT_DEBUG_REG13_di_prim_type_q_SIZE; + unsigned int current_source_sel : VGT_DEBUG_REG13_current_source_sel_SIZE; + } vgt_debug_reg13_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg13_t { + unsigned int current_source_sel : VGT_DEBUG_REG13_current_source_sel_SIZE; + unsigned int di_prim_type_q : VGT_DEBUG_REG13_di_prim_type_q_SIZE; + unsigned int shift_amount_extract : VGT_DEBUG_REG13_shift_amount_extract_SIZE; + unsigned int shift_amount_no_extract : VGT_DEBUG_REG13_shift_amount_no_extract_SIZE; + unsigned int di_index_counter_q : VGT_DEBUG_REG13_di_index_counter_q_SIZE; + } vgt_debug_reg13_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg13_t f; +} vgt_debug_reg13_u; + + +/* + * VGT_DEBUG_REG14 struct + */ + +#define VGT_DEBUG_REG14_current_source_sel_SIZE 2 +#define VGT_DEBUG_REG14_left_word_indx_q_SIZE 5 +#define VGT_DEBUG_REG14_input_data_cnt_SIZE 5 +#define VGT_DEBUG_REG14_input_data_lsw_SIZE 5 +#define VGT_DEBUG_REG14_input_data_msw_SIZE 5 +#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE 5 +#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE 5 + +#define VGT_DEBUG_REG14_current_source_sel_SHIFT 0 +#define VGT_DEBUG_REG14_left_word_indx_q_SHIFT 2 +#define VGT_DEBUG_REG14_input_data_cnt_SHIFT 7 +#define VGT_DEBUG_REG14_input_data_lsw_SHIFT 12 +#define VGT_DEBUG_REG14_input_data_msw_SHIFT 17 +#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT 22 +#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT 27 + +#define VGT_DEBUG_REG14_current_source_sel_MASK 0x00000003 +#define VGT_DEBUG_REG14_left_word_indx_q_MASK 0x0000007c +#define VGT_DEBUG_REG14_input_data_cnt_MASK 0x00000f80 +#define VGT_DEBUG_REG14_input_data_lsw_MASK 0x0001f000 +#define VGT_DEBUG_REG14_input_data_msw_MASK 0x003e0000 +#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK 0x07c00000 +#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK 0xf8000000 + +#define VGT_DEBUG_REG14_MASK \ + (VGT_DEBUG_REG14_current_source_sel_MASK | \ + VGT_DEBUG_REG14_left_word_indx_q_MASK | \ + VGT_DEBUG_REG14_input_data_cnt_MASK | \ + VGT_DEBUG_REG14_input_data_lsw_MASK | \ + VGT_DEBUG_REG14_input_data_msw_MASK | \ + VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK | \ + VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) + +#define VGT_DEBUG_REG14(current_source_sel, left_word_indx_q, input_data_cnt, input_data_lsw, input_data_msw, next_small_stride_shift_limit_q, current_small_stride_shift_limit_q) \ + ((current_source_sel << VGT_DEBUG_REG14_current_source_sel_SHIFT) | \ + (left_word_indx_q << VGT_DEBUG_REG14_left_word_indx_q_SHIFT) | \ + (input_data_cnt << VGT_DEBUG_REG14_input_data_cnt_SHIFT) | \ + (input_data_lsw << VGT_DEBUG_REG14_input_data_lsw_SHIFT) | \ + (input_data_msw << VGT_DEBUG_REG14_input_data_msw_SHIFT) | \ + (next_small_stride_shift_limit_q << VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT) | \ + (current_small_stride_shift_limit_q << VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT)) + +#define VGT_DEBUG_REG14_GET_current_source_sel(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_current_source_sel_MASK) >> VGT_DEBUG_REG14_current_source_sel_SHIFT) +#define VGT_DEBUG_REG14_GET_left_word_indx_q(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_left_word_indx_q_MASK) >> VGT_DEBUG_REG14_left_word_indx_q_SHIFT) +#define VGT_DEBUG_REG14_GET_input_data_cnt(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_cnt_MASK) >> VGT_DEBUG_REG14_input_data_cnt_SHIFT) +#define VGT_DEBUG_REG14_GET_input_data_lsw(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_lsw_MASK) >> VGT_DEBUG_REG14_input_data_lsw_SHIFT) +#define VGT_DEBUG_REG14_GET_input_data_msw(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_msw_MASK) >> VGT_DEBUG_REG14_input_data_msw_SHIFT) +#define VGT_DEBUG_REG14_GET_next_small_stride_shift_limit_q(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT) +#define VGT_DEBUG_REG14_GET_current_small_stride_shift_limit_q(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT) + +#define VGT_DEBUG_REG14_SET_current_source_sel(vgt_debug_reg14_reg, current_source_sel) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG14_current_source_sel_SHIFT) +#define VGT_DEBUG_REG14_SET_left_word_indx_q(vgt_debug_reg14_reg, left_word_indx_q) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_left_word_indx_q_MASK) | (left_word_indx_q << VGT_DEBUG_REG14_left_word_indx_q_SHIFT) +#define VGT_DEBUG_REG14_SET_input_data_cnt(vgt_debug_reg14_reg, input_data_cnt) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_cnt_MASK) | (input_data_cnt << VGT_DEBUG_REG14_input_data_cnt_SHIFT) +#define VGT_DEBUG_REG14_SET_input_data_lsw(vgt_debug_reg14_reg, input_data_lsw) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_lsw_MASK) | (input_data_lsw << VGT_DEBUG_REG14_input_data_lsw_SHIFT) +#define VGT_DEBUG_REG14_SET_input_data_msw(vgt_debug_reg14_reg, input_data_msw) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_msw_MASK) | (input_data_msw << VGT_DEBUG_REG14_input_data_msw_SHIFT) +#define VGT_DEBUG_REG14_SET_next_small_stride_shift_limit_q(vgt_debug_reg14_reg, next_small_stride_shift_limit_q) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK) | (next_small_stride_shift_limit_q << VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT) +#define VGT_DEBUG_REG14_SET_current_small_stride_shift_limit_q(vgt_debug_reg14_reg, current_small_stride_shift_limit_q) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) | (current_small_stride_shift_limit_q << VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg14_t { + unsigned int current_source_sel : VGT_DEBUG_REG14_current_source_sel_SIZE; + unsigned int left_word_indx_q : VGT_DEBUG_REG14_left_word_indx_q_SIZE; + unsigned int input_data_cnt : VGT_DEBUG_REG14_input_data_cnt_SIZE; + unsigned int input_data_lsw : VGT_DEBUG_REG14_input_data_lsw_SIZE; + unsigned int input_data_msw : VGT_DEBUG_REG14_input_data_msw_SIZE; + unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE; + unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE; + } vgt_debug_reg14_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg14_t { + unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE; + unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE; + unsigned int input_data_msw : VGT_DEBUG_REG14_input_data_msw_SIZE; + unsigned int input_data_lsw : VGT_DEBUG_REG14_input_data_lsw_SIZE; + unsigned int input_data_cnt : VGT_DEBUG_REG14_input_data_cnt_SIZE; + unsigned int left_word_indx_q : VGT_DEBUG_REG14_left_word_indx_q_SIZE; + unsigned int current_source_sel : VGT_DEBUG_REG14_current_source_sel_SIZE; + } vgt_debug_reg14_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg14_t f; +} vgt_debug_reg14_u; + + +/* + * VGT_DEBUG_REG15 struct + */ + +#define VGT_DEBUG_REG15_next_stride_q_SIZE 5 +#define VGT_DEBUG_REG15_next_stride_d_SIZE 5 +#define VGT_DEBUG_REG15_current_shift_q_SIZE 5 +#define VGT_DEBUG_REG15_current_shift_d_SIZE 5 +#define VGT_DEBUG_REG15_current_stride_q_SIZE 5 +#define VGT_DEBUG_REG15_current_stride_d_SIZE 5 +#define VGT_DEBUG_REG15_bgrp_trigger_SIZE 1 + +#define VGT_DEBUG_REG15_next_stride_q_SHIFT 0 +#define VGT_DEBUG_REG15_next_stride_d_SHIFT 5 +#define VGT_DEBUG_REG15_current_shift_q_SHIFT 10 +#define VGT_DEBUG_REG15_current_shift_d_SHIFT 15 +#define VGT_DEBUG_REG15_current_stride_q_SHIFT 20 +#define VGT_DEBUG_REG15_current_stride_d_SHIFT 25 +#define VGT_DEBUG_REG15_bgrp_trigger_SHIFT 30 + +#define VGT_DEBUG_REG15_next_stride_q_MASK 0x0000001f +#define VGT_DEBUG_REG15_next_stride_d_MASK 0x000003e0 +#define VGT_DEBUG_REG15_current_shift_q_MASK 0x00007c00 +#define VGT_DEBUG_REG15_current_shift_d_MASK 0x000f8000 +#define VGT_DEBUG_REG15_current_stride_q_MASK 0x01f00000 +#define VGT_DEBUG_REG15_current_stride_d_MASK 0x3e000000 +#define VGT_DEBUG_REG15_bgrp_trigger_MASK 0x40000000 + +#define VGT_DEBUG_REG15_MASK \ + (VGT_DEBUG_REG15_next_stride_q_MASK | \ + VGT_DEBUG_REG15_next_stride_d_MASK | \ + VGT_DEBUG_REG15_current_shift_q_MASK | \ + VGT_DEBUG_REG15_current_shift_d_MASK | \ + VGT_DEBUG_REG15_current_stride_q_MASK | \ + VGT_DEBUG_REG15_current_stride_d_MASK | \ + VGT_DEBUG_REG15_bgrp_trigger_MASK) + +#define VGT_DEBUG_REG15(next_stride_q, next_stride_d, current_shift_q, current_shift_d, current_stride_q, current_stride_d, bgrp_trigger) \ + ((next_stride_q << VGT_DEBUG_REG15_next_stride_q_SHIFT) | \ + (next_stride_d << VGT_DEBUG_REG15_next_stride_d_SHIFT) | \ + (current_shift_q << VGT_DEBUG_REG15_current_shift_q_SHIFT) | \ + (current_shift_d << VGT_DEBUG_REG15_current_shift_d_SHIFT) | \ + (current_stride_q << VGT_DEBUG_REG15_current_stride_q_SHIFT) | \ + (current_stride_d << VGT_DEBUG_REG15_current_stride_d_SHIFT) | \ + (bgrp_trigger << VGT_DEBUG_REG15_bgrp_trigger_SHIFT)) + +#define VGT_DEBUG_REG15_GET_next_stride_q(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_next_stride_q_MASK) >> VGT_DEBUG_REG15_next_stride_q_SHIFT) +#define VGT_DEBUG_REG15_GET_next_stride_d(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_next_stride_d_MASK) >> VGT_DEBUG_REG15_next_stride_d_SHIFT) +#define VGT_DEBUG_REG15_GET_current_shift_q(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_shift_q_MASK) >> VGT_DEBUG_REG15_current_shift_q_SHIFT) +#define VGT_DEBUG_REG15_GET_current_shift_d(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_shift_d_MASK) >> VGT_DEBUG_REG15_current_shift_d_SHIFT) +#define VGT_DEBUG_REG15_GET_current_stride_q(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_stride_q_MASK) >> VGT_DEBUG_REG15_current_stride_q_SHIFT) +#define VGT_DEBUG_REG15_GET_current_stride_d(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_stride_d_MASK) >> VGT_DEBUG_REG15_current_stride_d_SHIFT) +#define VGT_DEBUG_REG15_GET_bgrp_trigger(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_bgrp_trigger_MASK) >> VGT_DEBUG_REG15_bgrp_trigger_SHIFT) + +#define VGT_DEBUG_REG15_SET_next_stride_q(vgt_debug_reg15_reg, next_stride_q) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_next_stride_q_MASK) | (next_stride_q << VGT_DEBUG_REG15_next_stride_q_SHIFT) +#define VGT_DEBUG_REG15_SET_next_stride_d(vgt_debug_reg15_reg, next_stride_d) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_next_stride_d_MASK) | (next_stride_d << VGT_DEBUG_REG15_next_stride_d_SHIFT) +#define VGT_DEBUG_REG15_SET_current_shift_q(vgt_debug_reg15_reg, current_shift_q) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_shift_q_MASK) | (current_shift_q << VGT_DEBUG_REG15_current_shift_q_SHIFT) +#define VGT_DEBUG_REG15_SET_current_shift_d(vgt_debug_reg15_reg, current_shift_d) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_shift_d_MASK) | (current_shift_d << VGT_DEBUG_REG15_current_shift_d_SHIFT) +#define VGT_DEBUG_REG15_SET_current_stride_q(vgt_debug_reg15_reg, current_stride_q) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_stride_q_MASK) | (current_stride_q << VGT_DEBUG_REG15_current_stride_q_SHIFT) +#define VGT_DEBUG_REG15_SET_current_stride_d(vgt_debug_reg15_reg, current_stride_d) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_stride_d_MASK) | (current_stride_d << VGT_DEBUG_REG15_current_stride_d_SHIFT) +#define VGT_DEBUG_REG15_SET_bgrp_trigger(vgt_debug_reg15_reg, bgrp_trigger) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG15_bgrp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg15_t { + unsigned int next_stride_q : VGT_DEBUG_REG15_next_stride_q_SIZE; + unsigned int next_stride_d : VGT_DEBUG_REG15_next_stride_d_SIZE; + unsigned int current_shift_q : VGT_DEBUG_REG15_current_shift_q_SIZE; + unsigned int current_shift_d : VGT_DEBUG_REG15_current_shift_d_SIZE; + unsigned int current_stride_q : VGT_DEBUG_REG15_current_stride_q_SIZE; + unsigned int current_stride_d : VGT_DEBUG_REG15_current_stride_d_SIZE; + unsigned int bgrp_trigger : VGT_DEBUG_REG15_bgrp_trigger_SIZE; + unsigned int : 1; + } vgt_debug_reg15_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg15_t { + unsigned int : 1; + unsigned int bgrp_trigger : VGT_DEBUG_REG15_bgrp_trigger_SIZE; + unsigned int current_stride_d : VGT_DEBUG_REG15_current_stride_d_SIZE; + unsigned int current_stride_q : VGT_DEBUG_REG15_current_stride_q_SIZE; + unsigned int current_shift_d : VGT_DEBUG_REG15_current_shift_d_SIZE; + unsigned int current_shift_q : VGT_DEBUG_REG15_current_shift_q_SIZE; + unsigned int next_stride_d : VGT_DEBUG_REG15_next_stride_d_SIZE; + unsigned int next_stride_q : VGT_DEBUG_REG15_next_stride_q_SIZE; + } vgt_debug_reg15_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg15_t f; +} vgt_debug_reg15_u; + + +/* + * VGT_DEBUG_REG16 struct + */ + +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE 1 +#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE 1 +#define VGT_DEBUG_REG16_rst_last_bit_SIZE 1 +#define VGT_DEBUG_REG16_current_state_q_SIZE 1 +#define VGT_DEBUG_REG16_old_state_q_SIZE 1 +#define VGT_DEBUG_REG16_old_state_en_SIZE 1 +#define VGT_DEBUG_REG16_prev_last_bit_q_SIZE 1 +#define VGT_DEBUG_REG16_dbl_last_bit_q_SIZE 1 +#define VGT_DEBUG_REG16_last_bit_block_q_SIZE 1 +#define VGT_DEBUG_REG16_ast_bit_block2_q_SIZE 1 +#define VGT_DEBUG_REG16_load_empty_reg_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE 8 +#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE 2 +#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE 1 +#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_trigger_SIZE 1 + +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT 0 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT 1 +#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT 2 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT 3 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT 4 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT 5 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT 6 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT 7 +#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT 8 +#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT 9 +#define VGT_DEBUG_REG16_rst_last_bit_SHIFT 10 +#define VGT_DEBUG_REG16_current_state_q_SHIFT 11 +#define VGT_DEBUG_REG16_old_state_q_SHIFT 12 +#define VGT_DEBUG_REG16_old_state_en_SHIFT 13 +#define VGT_DEBUG_REG16_prev_last_bit_q_SHIFT 14 +#define VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT 15 +#define VGT_DEBUG_REG16_last_bit_block_q_SHIFT 16 +#define VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT 17 +#define VGT_DEBUG_REG16_load_empty_reg_SHIFT 18 +#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT 19 +#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT 27 +#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT 29 +#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT 30 +#define VGT_DEBUG_REG16_bgrp_trigger_SHIFT 31 + +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK 0x00000001 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK 0x00000002 +#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK 0x00000004 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK 0x00000008 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK 0x00000010 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK 0x00000020 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK 0x00000040 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK 0x00000080 +#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK 0x00000100 +#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK 0x00000200 +#define VGT_DEBUG_REG16_rst_last_bit_MASK 0x00000400 +#define VGT_DEBUG_REG16_current_state_q_MASK 0x00000800 +#define VGT_DEBUG_REG16_old_state_q_MASK 0x00001000 +#define VGT_DEBUG_REG16_old_state_en_MASK 0x00002000 +#define VGT_DEBUG_REG16_prev_last_bit_q_MASK 0x00004000 +#define VGT_DEBUG_REG16_dbl_last_bit_q_MASK 0x00008000 +#define VGT_DEBUG_REG16_last_bit_block_q_MASK 0x00010000 +#define VGT_DEBUG_REG16_ast_bit_block2_q_MASK 0x00020000 +#define VGT_DEBUG_REG16_load_empty_reg_MASK 0x00040000 +#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK 0x07f80000 +#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK 0x18000000 +#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK 0x20000000 +#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK 0x40000000 +#define VGT_DEBUG_REG16_bgrp_trigger_MASK 0x80000000 + +#define VGT_DEBUG_REG16_MASK \ + (VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK | \ + VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK | \ + VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK | \ + VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK | \ + VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK | \ + VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK | \ + VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK | \ + VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK | \ + VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK | \ + VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK | \ + VGT_DEBUG_REG16_rst_last_bit_MASK | \ + VGT_DEBUG_REG16_current_state_q_MASK | \ + VGT_DEBUG_REG16_old_state_q_MASK | \ + VGT_DEBUG_REG16_old_state_en_MASK | \ + VGT_DEBUG_REG16_prev_last_bit_q_MASK | \ + VGT_DEBUG_REG16_dbl_last_bit_q_MASK | \ + VGT_DEBUG_REG16_last_bit_block_q_MASK | \ + VGT_DEBUG_REG16_ast_bit_block2_q_MASK | \ + VGT_DEBUG_REG16_load_empty_reg_MASK | \ + VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK | \ + VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK | \ + VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK | \ + VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK | \ + VGT_DEBUG_REG16_bgrp_trigger_MASK) + +#define VGT_DEBUG_REG16(bgrp_cull_fetch_fifo_full, bgrp_cull_fetch_fifo_empty, dma_bgrp_cull_fetch_read, bgrp_cull_fetch_fifo_we, bgrp_byte_mask_fifo_full, bgrp_byte_mask_fifo_empty, bgrp_byte_mask_fifo_re_q, bgrp_byte_mask_fifo_we, bgrp_dma_mask_kill, bgrp_grp_bin_valid, rst_last_bit, current_state_q, old_state_q, old_state_en, prev_last_bit_q, dbl_last_bit_q, last_bit_block_q, ast_bit_block2_q, load_empty_reg, bgrp_grp_byte_mask_rdata, dma_bgrp_dma_data_fifo_rptr, top_di_pre_fetch_cull_enable, top_di_grp_cull_enable_q, bgrp_trigger) \ + ((bgrp_cull_fetch_fifo_full << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT) | \ + (bgrp_cull_fetch_fifo_empty << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT) | \ + (dma_bgrp_cull_fetch_read << VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT) | \ + (bgrp_cull_fetch_fifo_we << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT) | \ + (bgrp_byte_mask_fifo_full << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT) | \ + (bgrp_byte_mask_fifo_empty << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT) | \ + (bgrp_byte_mask_fifo_re_q << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT) | \ + (bgrp_byte_mask_fifo_we << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT) | \ + (bgrp_dma_mask_kill << VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT) | \ + (bgrp_grp_bin_valid << VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT) | \ + (rst_last_bit << VGT_DEBUG_REG16_rst_last_bit_SHIFT) | \ + (current_state_q << VGT_DEBUG_REG16_current_state_q_SHIFT) | \ + (old_state_q << VGT_DEBUG_REG16_old_state_q_SHIFT) | \ + (old_state_en << VGT_DEBUG_REG16_old_state_en_SHIFT) | \ + (prev_last_bit_q << VGT_DEBUG_REG16_prev_last_bit_q_SHIFT) | \ + (dbl_last_bit_q << VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT) | \ + (last_bit_block_q << VGT_DEBUG_REG16_last_bit_block_q_SHIFT) | \ + (ast_bit_block2_q << VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT) | \ + (load_empty_reg << VGT_DEBUG_REG16_load_empty_reg_SHIFT) | \ + (bgrp_grp_byte_mask_rdata << VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT) | \ + (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT) | \ + (top_di_pre_fetch_cull_enable << VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT) | \ + (top_di_grp_cull_enable_q << VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT) | \ + (bgrp_trigger << VGT_DEBUG_REG16_bgrp_trigger_SHIFT)) + +#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_full(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_empty(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT) +#define VGT_DEBUG_REG16_GET_dma_bgrp_cull_fetch_read(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK) >> VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_we(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_full(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_empty(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_re_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_we(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_dma_mask_kill(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK) >> VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_grp_bin_valid(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK) >> VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT) +#define VGT_DEBUG_REG16_GET_rst_last_bit(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_rst_last_bit_MASK) >> VGT_DEBUG_REG16_rst_last_bit_SHIFT) +#define VGT_DEBUG_REG16_GET_current_state_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_current_state_q_MASK) >> VGT_DEBUG_REG16_current_state_q_SHIFT) +#define VGT_DEBUG_REG16_GET_old_state_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_old_state_q_MASK) >> VGT_DEBUG_REG16_old_state_q_SHIFT) +#define VGT_DEBUG_REG16_GET_old_state_en(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_old_state_en_MASK) >> VGT_DEBUG_REG16_old_state_en_SHIFT) +#define VGT_DEBUG_REG16_GET_prev_last_bit_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_prev_last_bit_q_MASK) >> VGT_DEBUG_REG16_prev_last_bit_q_SHIFT) +#define VGT_DEBUG_REG16_GET_dbl_last_bit_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_dbl_last_bit_q_MASK) >> VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT) +#define VGT_DEBUG_REG16_GET_last_bit_block_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_last_bit_block_q_MASK) >> VGT_DEBUG_REG16_last_bit_block_q_SHIFT) +#define VGT_DEBUG_REG16_GET_ast_bit_block2_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_ast_bit_block2_q_MASK) >> VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT) +#define VGT_DEBUG_REG16_GET_load_empty_reg(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_load_empty_reg_MASK) >> VGT_DEBUG_REG16_load_empty_reg_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_grp_byte_mask_rdata(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK) >> VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT) +#define VGT_DEBUG_REG16_GET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK) >> VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT) +#define VGT_DEBUG_REG16_GET_top_di_pre_fetch_cull_enable(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK) >> VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT) +#define VGT_DEBUG_REG16_GET_top_di_grp_cull_enable_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK) >> VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_trigger(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_trigger_MASK) >> VGT_DEBUG_REG16_bgrp_trigger_SHIFT) + +#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_full(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_full) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK) | (bgrp_cull_fetch_fifo_full << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_empty(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_empty) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK) | (bgrp_cull_fetch_fifo_empty << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT) +#define VGT_DEBUG_REG16_SET_dma_bgrp_cull_fetch_read(vgt_debug_reg16_reg, dma_bgrp_cull_fetch_read) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK) | (dma_bgrp_cull_fetch_read << VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_we(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_we) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK) | (bgrp_cull_fetch_fifo_we << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_full(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_full) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK) | (bgrp_byte_mask_fifo_full << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_empty(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_empty) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK) | (bgrp_byte_mask_fifo_empty << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_re_q(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_re_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK) | (bgrp_byte_mask_fifo_re_q << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_we(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_we) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK) | (bgrp_byte_mask_fifo_we << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_dma_mask_kill(vgt_debug_reg16_reg, bgrp_dma_mask_kill) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK) | (bgrp_dma_mask_kill << VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_grp_bin_valid(vgt_debug_reg16_reg, bgrp_grp_bin_valid) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK) | (bgrp_grp_bin_valid << VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT) +#define VGT_DEBUG_REG16_SET_rst_last_bit(vgt_debug_reg16_reg, rst_last_bit) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_rst_last_bit_MASK) | (rst_last_bit << VGT_DEBUG_REG16_rst_last_bit_SHIFT) +#define VGT_DEBUG_REG16_SET_current_state_q(vgt_debug_reg16_reg, current_state_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_current_state_q_MASK) | (current_state_q << VGT_DEBUG_REG16_current_state_q_SHIFT) +#define VGT_DEBUG_REG16_SET_old_state_q(vgt_debug_reg16_reg, old_state_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_old_state_q_MASK) | (old_state_q << VGT_DEBUG_REG16_old_state_q_SHIFT) +#define VGT_DEBUG_REG16_SET_old_state_en(vgt_debug_reg16_reg, old_state_en) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_old_state_en_MASK) | (old_state_en << VGT_DEBUG_REG16_old_state_en_SHIFT) +#define VGT_DEBUG_REG16_SET_prev_last_bit_q(vgt_debug_reg16_reg, prev_last_bit_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_prev_last_bit_q_MASK) | (prev_last_bit_q << VGT_DEBUG_REG16_prev_last_bit_q_SHIFT) +#define VGT_DEBUG_REG16_SET_dbl_last_bit_q(vgt_debug_reg16_reg, dbl_last_bit_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dbl_last_bit_q_MASK) | (dbl_last_bit_q << VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT) +#define VGT_DEBUG_REG16_SET_last_bit_block_q(vgt_debug_reg16_reg, last_bit_block_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_last_bit_block_q_MASK) | (last_bit_block_q << VGT_DEBUG_REG16_last_bit_block_q_SHIFT) +#define VGT_DEBUG_REG16_SET_ast_bit_block2_q(vgt_debug_reg16_reg, ast_bit_block2_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_ast_bit_block2_q_MASK) | (ast_bit_block2_q << VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT) +#define VGT_DEBUG_REG16_SET_load_empty_reg(vgt_debug_reg16_reg, load_empty_reg) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_load_empty_reg_MASK) | (load_empty_reg << VGT_DEBUG_REG16_load_empty_reg_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_grp_byte_mask_rdata(vgt_debug_reg16_reg, bgrp_grp_byte_mask_rdata) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK) | (bgrp_grp_byte_mask_rdata << VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT) +#define VGT_DEBUG_REG16_SET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg16_reg, dma_bgrp_dma_data_fifo_rptr) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK) | (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT) +#define VGT_DEBUG_REG16_SET_top_di_pre_fetch_cull_enable(vgt_debug_reg16_reg, top_di_pre_fetch_cull_enable) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK) | (top_di_pre_fetch_cull_enable << VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT) +#define VGT_DEBUG_REG16_SET_top_di_grp_cull_enable_q(vgt_debug_reg16_reg, top_di_grp_cull_enable_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK) | (top_di_grp_cull_enable_q << VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_trigger(vgt_debug_reg16_reg, bgrp_trigger) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG16_bgrp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg16_t { + unsigned int bgrp_cull_fetch_fifo_full : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE; + unsigned int bgrp_cull_fetch_fifo_empty : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE; + unsigned int dma_bgrp_cull_fetch_read : VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE; + unsigned int bgrp_cull_fetch_fifo_we : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE; + unsigned int bgrp_byte_mask_fifo_full : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE; + unsigned int bgrp_byte_mask_fifo_empty : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE; + unsigned int bgrp_byte_mask_fifo_re_q : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE; + unsigned int bgrp_byte_mask_fifo_we : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE; + unsigned int bgrp_dma_mask_kill : VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE; + unsigned int bgrp_grp_bin_valid : VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE; + unsigned int rst_last_bit : VGT_DEBUG_REG16_rst_last_bit_SIZE; + unsigned int current_state_q : VGT_DEBUG_REG16_current_state_q_SIZE; + unsigned int old_state_q : VGT_DEBUG_REG16_old_state_q_SIZE; + unsigned int old_state_en : VGT_DEBUG_REG16_old_state_en_SIZE; + unsigned int prev_last_bit_q : VGT_DEBUG_REG16_prev_last_bit_q_SIZE; + unsigned int dbl_last_bit_q : VGT_DEBUG_REG16_dbl_last_bit_q_SIZE; + unsigned int last_bit_block_q : VGT_DEBUG_REG16_last_bit_block_q_SIZE; + unsigned int ast_bit_block2_q : VGT_DEBUG_REG16_ast_bit_block2_q_SIZE; + unsigned int load_empty_reg : VGT_DEBUG_REG16_load_empty_reg_SIZE; + unsigned int bgrp_grp_byte_mask_rdata : VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE; + unsigned int dma_bgrp_dma_data_fifo_rptr : VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE; + unsigned int top_di_pre_fetch_cull_enable : VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE; + unsigned int top_di_grp_cull_enable_q : VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE; + unsigned int bgrp_trigger : VGT_DEBUG_REG16_bgrp_trigger_SIZE; + } vgt_debug_reg16_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg16_t { + unsigned int bgrp_trigger : VGT_DEBUG_REG16_bgrp_trigger_SIZE; + unsigned int top_di_grp_cull_enable_q : VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE; + unsigned int top_di_pre_fetch_cull_enable : VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE; + unsigned int dma_bgrp_dma_data_fifo_rptr : VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE; + unsigned int bgrp_grp_byte_mask_rdata : VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE; + unsigned int load_empty_reg : VGT_DEBUG_REG16_load_empty_reg_SIZE; + unsigned int ast_bit_block2_q : VGT_DEBUG_REG16_ast_bit_block2_q_SIZE; + unsigned int last_bit_block_q : VGT_DEBUG_REG16_last_bit_block_q_SIZE; + unsigned int dbl_last_bit_q : VGT_DEBUG_REG16_dbl_last_bit_q_SIZE; + unsigned int prev_last_bit_q : VGT_DEBUG_REG16_prev_last_bit_q_SIZE; + unsigned int old_state_en : VGT_DEBUG_REG16_old_state_en_SIZE; + unsigned int old_state_q : VGT_DEBUG_REG16_old_state_q_SIZE; + unsigned int current_state_q : VGT_DEBUG_REG16_current_state_q_SIZE; + unsigned int rst_last_bit : VGT_DEBUG_REG16_rst_last_bit_SIZE; + unsigned int bgrp_grp_bin_valid : VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE; + unsigned int bgrp_dma_mask_kill : VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE; + unsigned int bgrp_byte_mask_fifo_we : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE; + unsigned int bgrp_byte_mask_fifo_re_q : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE; + unsigned int bgrp_byte_mask_fifo_empty : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE; + unsigned int bgrp_byte_mask_fifo_full : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE; + unsigned int bgrp_cull_fetch_fifo_we : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE; + unsigned int dma_bgrp_cull_fetch_read : VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE; + unsigned int bgrp_cull_fetch_fifo_empty : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE; + unsigned int bgrp_cull_fetch_fifo_full : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE; + } vgt_debug_reg16_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg16_t f; +} vgt_debug_reg16_u; + + +/* + * VGT_DEBUG_REG17 struct + */ + +#define VGT_DEBUG_REG17_save_read_q_SIZE 1 +#define VGT_DEBUG_REG17_extend_read_q_SIZE 1 +#define VGT_DEBUG_REG17_grp_indx_size_SIZE 2 +#define VGT_DEBUG_REG17_cull_prim_true_SIZE 1 +#define VGT_DEBUG_REG17_reset_bit2_q_SIZE 1 +#define VGT_DEBUG_REG17_reset_bit1_q_SIZE 1 +#define VGT_DEBUG_REG17_first_reg_first_q_SIZE 1 +#define VGT_DEBUG_REG17_check_second_reg_SIZE 1 +#define VGT_DEBUG_REG17_check_first_reg_SIZE 1 +#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE 1 +#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE 1 +#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE 1 +#define VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE 1 +#define VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE 1 +#define VGT_DEBUG_REG17_to_second_reg_q_SIZE 1 +#define VGT_DEBUG_REG17_roll_over_msk_q_SIZE 1 +#define VGT_DEBUG_REG17_max_msk_ptr_q_SIZE 7 +#define VGT_DEBUG_REG17_min_msk_ptr_q_SIZE 7 +#define VGT_DEBUG_REG17_bgrp_trigger_SIZE 1 + +#define VGT_DEBUG_REG17_save_read_q_SHIFT 0 +#define VGT_DEBUG_REG17_extend_read_q_SHIFT 1 +#define VGT_DEBUG_REG17_grp_indx_size_SHIFT 2 +#define VGT_DEBUG_REG17_cull_prim_true_SHIFT 4 +#define VGT_DEBUG_REG17_reset_bit2_q_SHIFT 5 +#define VGT_DEBUG_REG17_reset_bit1_q_SHIFT 6 +#define VGT_DEBUG_REG17_first_reg_first_q_SHIFT 7 +#define VGT_DEBUG_REG17_check_second_reg_SHIFT 8 +#define VGT_DEBUG_REG17_check_first_reg_SHIFT 9 +#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT 10 +#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT 11 +#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT 12 +#define VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT 13 +#define VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT 14 +#define VGT_DEBUG_REG17_to_second_reg_q_SHIFT 15 +#define VGT_DEBUG_REG17_roll_over_msk_q_SHIFT 16 +#define VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT 17 +#define VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT 24 +#define VGT_DEBUG_REG17_bgrp_trigger_SHIFT 31 + +#define VGT_DEBUG_REG17_save_read_q_MASK 0x00000001 +#define VGT_DEBUG_REG17_extend_read_q_MASK 0x00000002 +#define VGT_DEBUG_REG17_grp_indx_size_MASK 0x0000000c +#define VGT_DEBUG_REG17_cull_prim_true_MASK 0x00000010 +#define VGT_DEBUG_REG17_reset_bit2_q_MASK 0x00000020 +#define VGT_DEBUG_REG17_reset_bit1_q_MASK 0x00000040 +#define VGT_DEBUG_REG17_first_reg_first_q_MASK 0x00000080 +#define VGT_DEBUG_REG17_check_second_reg_MASK 0x00000100 +#define VGT_DEBUG_REG17_check_first_reg_MASK 0x00000200 +#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK 0x00000400 +#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK 0x00000800 +#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK 0x00001000 +#define VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK 0x00002000 +#define VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK 0x00004000 +#define VGT_DEBUG_REG17_to_second_reg_q_MASK 0x00008000 +#define VGT_DEBUG_REG17_roll_over_msk_q_MASK 0x00010000 +#define VGT_DEBUG_REG17_max_msk_ptr_q_MASK 0x00fe0000 +#define VGT_DEBUG_REG17_min_msk_ptr_q_MASK 0x7f000000 +#define VGT_DEBUG_REG17_bgrp_trigger_MASK 0x80000000 + +#define VGT_DEBUG_REG17_MASK \ + (VGT_DEBUG_REG17_save_read_q_MASK | \ + VGT_DEBUG_REG17_extend_read_q_MASK | \ + VGT_DEBUG_REG17_grp_indx_size_MASK | \ + VGT_DEBUG_REG17_cull_prim_true_MASK | \ + VGT_DEBUG_REG17_reset_bit2_q_MASK | \ + VGT_DEBUG_REG17_reset_bit1_q_MASK | \ + VGT_DEBUG_REG17_first_reg_first_q_MASK | \ + VGT_DEBUG_REG17_check_second_reg_MASK | \ + VGT_DEBUG_REG17_check_first_reg_MASK | \ + VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK | \ + VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK | \ + VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK | \ + VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK | \ + VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK | \ + VGT_DEBUG_REG17_to_second_reg_q_MASK | \ + VGT_DEBUG_REG17_roll_over_msk_q_MASK | \ + VGT_DEBUG_REG17_max_msk_ptr_q_MASK | \ + VGT_DEBUG_REG17_min_msk_ptr_q_MASK | \ + VGT_DEBUG_REG17_bgrp_trigger_MASK) + +#define VGT_DEBUG_REG17(save_read_q, extend_read_q, grp_indx_size, cull_prim_true, reset_bit2_q, reset_bit1_q, first_reg_first_q, check_second_reg, check_first_reg, bgrp_cull_fetch_fifo_wdata, save_cull_fetch_data2_q, save_cull_fetch_data1_q, save_byte_mask_data2_q, save_byte_mask_data1_q, to_second_reg_q, roll_over_msk_q, max_msk_ptr_q, min_msk_ptr_q, bgrp_trigger) \ + ((save_read_q << VGT_DEBUG_REG17_save_read_q_SHIFT) | \ + (extend_read_q << VGT_DEBUG_REG17_extend_read_q_SHIFT) | \ + (grp_indx_size << VGT_DEBUG_REG17_grp_indx_size_SHIFT) | \ + (cull_prim_true << VGT_DEBUG_REG17_cull_prim_true_SHIFT) | \ + (reset_bit2_q << VGT_DEBUG_REG17_reset_bit2_q_SHIFT) | \ + (reset_bit1_q << VGT_DEBUG_REG17_reset_bit1_q_SHIFT) | \ + (first_reg_first_q << VGT_DEBUG_REG17_first_reg_first_q_SHIFT) | \ + (check_second_reg << VGT_DEBUG_REG17_check_second_reg_SHIFT) | \ + (check_first_reg << VGT_DEBUG_REG17_check_first_reg_SHIFT) | \ + (bgrp_cull_fetch_fifo_wdata << VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT) | \ + (save_cull_fetch_data2_q << VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT) | \ + (save_cull_fetch_data1_q << VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT) | \ + (save_byte_mask_data2_q << VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT) | \ + (save_byte_mask_data1_q << VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT) | \ + (to_second_reg_q << VGT_DEBUG_REG17_to_second_reg_q_SHIFT) | \ + (roll_over_msk_q << VGT_DEBUG_REG17_roll_over_msk_q_SHIFT) | \ + (max_msk_ptr_q << VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT) | \ + (min_msk_ptr_q << VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT) | \ + (bgrp_trigger << VGT_DEBUG_REG17_bgrp_trigger_SHIFT)) + +#define VGT_DEBUG_REG17_GET_save_read_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_read_q_MASK) >> VGT_DEBUG_REG17_save_read_q_SHIFT) +#define VGT_DEBUG_REG17_GET_extend_read_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_extend_read_q_MASK) >> VGT_DEBUG_REG17_extend_read_q_SHIFT) +#define VGT_DEBUG_REG17_GET_grp_indx_size(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_grp_indx_size_MASK) >> VGT_DEBUG_REG17_grp_indx_size_SHIFT) +#define VGT_DEBUG_REG17_GET_cull_prim_true(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_cull_prim_true_MASK) >> VGT_DEBUG_REG17_cull_prim_true_SHIFT) +#define VGT_DEBUG_REG17_GET_reset_bit2_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_reset_bit2_q_MASK) >> VGT_DEBUG_REG17_reset_bit2_q_SHIFT) +#define VGT_DEBUG_REG17_GET_reset_bit1_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_reset_bit1_q_MASK) >> VGT_DEBUG_REG17_reset_bit1_q_SHIFT) +#define VGT_DEBUG_REG17_GET_first_reg_first_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_first_reg_first_q_MASK) >> VGT_DEBUG_REG17_first_reg_first_q_SHIFT) +#define VGT_DEBUG_REG17_GET_check_second_reg(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_check_second_reg_MASK) >> VGT_DEBUG_REG17_check_second_reg_SHIFT) +#define VGT_DEBUG_REG17_GET_check_first_reg(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_check_first_reg_MASK) >> VGT_DEBUG_REG17_check_first_reg_SHIFT) +#define VGT_DEBUG_REG17_GET_bgrp_cull_fetch_fifo_wdata(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK) >> VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT) +#define VGT_DEBUG_REG17_GET_save_cull_fetch_data2_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK) >> VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT) +#define VGT_DEBUG_REG17_GET_save_cull_fetch_data1_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK) >> VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT) +#define VGT_DEBUG_REG17_GET_save_byte_mask_data2_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK) >> VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT) +#define VGT_DEBUG_REG17_GET_save_byte_mask_data1_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK) >> VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT) +#define VGT_DEBUG_REG17_GET_to_second_reg_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_to_second_reg_q_MASK) >> VGT_DEBUG_REG17_to_second_reg_q_SHIFT) +#define VGT_DEBUG_REG17_GET_roll_over_msk_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_roll_over_msk_q_MASK) >> VGT_DEBUG_REG17_roll_over_msk_q_SHIFT) +#define VGT_DEBUG_REG17_GET_max_msk_ptr_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_max_msk_ptr_q_MASK) >> VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT) +#define VGT_DEBUG_REG17_GET_min_msk_ptr_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_min_msk_ptr_q_MASK) >> VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT) +#define VGT_DEBUG_REG17_GET_bgrp_trigger(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_bgrp_trigger_MASK) >> VGT_DEBUG_REG17_bgrp_trigger_SHIFT) + +#define VGT_DEBUG_REG17_SET_save_read_q(vgt_debug_reg17_reg, save_read_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_read_q_MASK) | (save_read_q << VGT_DEBUG_REG17_save_read_q_SHIFT) +#define VGT_DEBUG_REG17_SET_extend_read_q(vgt_debug_reg17_reg, extend_read_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_extend_read_q_MASK) | (extend_read_q << VGT_DEBUG_REG17_extend_read_q_SHIFT) +#define VGT_DEBUG_REG17_SET_grp_indx_size(vgt_debug_reg17_reg, grp_indx_size) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_grp_indx_size_MASK) | (grp_indx_size << VGT_DEBUG_REG17_grp_indx_size_SHIFT) +#define VGT_DEBUG_REG17_SET_cull_prim_true(vgt_debug_reg17_reg, cull_prim_true) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_cull_prim_true_MASK) | (cull_prim_true << VGT_DEBUG_REG17_cull_prim_true_SHIFT) +#define VGT_DEBUG_REG17_SET_reset_bit2_q(vgt_debug_reg17_reg, reset_bit2_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_reset_bit2_q_MASK) | (reset_bit2_q << VGT_DEBUG_REG17_reset_bit2_q_SHIFT) +#define VGT_DEBUG_REG17_SET_reset_bit1_q(vgt_debug_reg17_reg, reset_bit1_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_reset_bit1_q_MASK) | (reset_bit1_q << VGT_DEBUG_REG17_reset_bit1_q_SHIFT) +#define VGT_DEBUG_REG17_SET_first_reg_first_q(vgt_debug_reg17_reg, first_reg_first_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_first_reg_first_q_MASK) | (first_reg_first_q << VGT_DEBUG_REG17_first_reg_first_q_SHIFT) +#define VGT_DEBUG_REG17_SET_check_second_reg(vgt_debug_reg17_reg, check_second_reg) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_check_second_reg_MASK) | (check_second_reg << VGT_DEBUG_REG17_check_second_reg_SHIFT) +#define VGT_DEBUG_REG17_SET_check_first_reg(vgt_debug_reg17_reg, check_first_reg) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_check_first_reg_MASK) | (check_first_reg << VGT_DEBUG_REG17_check_first_reg_SHIFT) +#define VGT_DEBUG_REG17_SET_bgrp_cull_fetch_fifo_wdata(vgt_debug_reg17_reg, bgrp_cull_fetch_fifo_wdata) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK) | (bgrp_cull_fetch_fifo_wdata << VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT) +#define VGT_DEBUG_REG17_SET_save_cull_fetch_data2_q(vgt_debug_reg17_reg, save_cull_fetch_data2_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK) | (save_cull_fetch_data2_q << VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT) +#define VGT_DEBUG_REG17_SET_save_cull_fetch_data1_q(vgt_debug_reg17_reg, save_cull_fetch_data1_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK) | (save_cull_fetch_data1_q << VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT) +#define VGT_DEBUG_REG17_SET_save_byte_mask_data2_q(vgt_debug_reg17_reg, save_byte_mask_data2_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK) | (save_byte_mask_data2_q << VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT) +#define VGT_DEBUG_REG17_SET_save_byte_mask_data1_q(vgt_debug_reg17_reg, save_byte_mask_data1_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK) | (save_byte_mask_data1_q << VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT) +#define VGT_DEBUG_REG17_SET_to_second_reg_q(vgt_debug_reg17_reg, to_second_reg_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_to_second_reg_q_MASK) | (to_second_reg_q << VGT_DEBUG_REG17_to_second_reg_q_SHIFT) +#define VGT_DEBUG_REG17_SET_roll_over_msk_q(vgt_debug_reg17_reg, roll_over_msk_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_roll_over_msk_q_MASK) | (roll_over_msk_q << VGT_DEBUG_REG17_roll_over_msk_q_SHIFT) +#define VGT_DEBUG_REG17_SET_max_msk_ptr_q(vgt_debug_reg17_reg, max_msk_ptr_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_max_msk_ptr_q_MASK) | (max_msk_ptr_q << VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT) +#define VGT_DEBUG_REG17_SET_min_msk_ptr_q(vgt_debug_reg17_reg, min_msk_ptr_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_min_msk_ptr_q_MASK) | (min_msk_ptr_q << VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT) +#define VGT_DEBUG_REG17_SET_bgrp_trigger(vgt_debug_reg17_reg, bgrp_trigger) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG17_bgrp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg17_t { + unsigned int save_read_q : VGT_DEBUG_REG17_save_read_q_SIZE; + unsigned int extend_read_q : VGT_DEBUG_REG17_extend_read_q_SIZE; + unsigned int grp_indx_size : VGT_DEBUG_REG17_grp_indx_size_SIZE; + unsigned int cull_prim_true : VGT_DEBUG_REG17_cull_prim_true_SIZE; + unsigned int reset_bit2_q : VGT_DEBUG_REG17_reset_bit2_q_SIZE; + unsigned int reset_bit1_q : VGT_DEBUG_REG17_reset_bit1_q_SIZE; + unsigned int first_reg_first_q : VGT_DEBUG_REG17_first_reg_first_q_SIZE; + unsigned int check_second_reg : VGT_DEBUG_REG17_check_second_reg_SIZE; + unsigned int check_first_reg : VGT_DEBUG_REG17_check_first_reg_SIZE; + unsigned int bgrp_cull_fetch_fifo_wdata : VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE; + unsigned int save_cull_fetch_data2_q : VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE; + unsigned int save_cull_fetch_data1_q : VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE; + unsigned int save_byte_mask_data2_q : VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE; + unsigned int save_byte_mask_data1_q : VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE; + unsigned int to_second_reg_q : VGT_DEBUG_REG17_to_second_reg_q_SIZE; + unsigned int roll_over_msk_q : VGT_DEBUG_REG17_roll_over_msk_q_SIZE; + unsigned int max_msk_ptr_q : VGT_DEBUG_REG17_max_msk_ptr_q_SIZE; + unsigned int min_msk_ptr_q : VGT_DEBUG_REG17_min_msk_ptr_q_SIZE; + unsigned int bgrp_trigger : VGT_DEBUG_REG17_bgrp_trigger_SIZE; + } vgt_debug_reg17_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg17_t { + unsigned int bgrp_trigger : VGT_DEBUG_REG17_bgrp_trigger_SIZE; + unsigned int min_msk_ptr_q : VGT_DEBUG_REG17_min_msk_ptr_q_SIZE; + unsigned int max_msk_ptr_q : VGT_DEBUG_REG17_max_msk_ptr_q_SIZE; + unsigned int roll_over_msk_q : VGT_DEBUG_REG17_roll_over_msk_q_SIZE; + unsigned int to_second_reg_q : VGT_DEBUG_REG17_to_second_reg_q_SIZE; + unsigned int save_byte_mask_data1_q : VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE; + unsigned int save_byte_mask_data2_q : VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE; + unsigned int save_cull_fetch_data1_q : VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE; + unsigned int save_cull_fetch_data2_q : VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE; + unsigned int bgrp_cull_fetch_fifo_wdata : VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE; + unsigned int check_first_reg : VGT_DEBUG_REG17_check_first_reg_SIZE; + unsigned int check_second_reg : VGT_DEBUG_REG17_check_second_reg_SIZE; + unsigned int first_reg_first_q : VGT_DEBUG_REG17_first_reg_first_q_SIZE; + unsigned int reset_bit1_q : VGT_DEBUG_REG17_reset_bit1_q_SIZE; + unsigned int reset_bit2_q : VGT_DEBUG_REG17_reset_bit2_q_SIZE; + unsigned int cull_prim_true : VGT_DEBUG_REG17_cull_prim_true_SIZE; + unsigned int grp_indx_size : VGT_DEBUG_REG17_grp_indx_size_SIZE; + unsigned int extend_read_q : VGT_DEBUG_REG17_extend_read_q_SIZE; + unsigned int save_read_q : VGT_DEBUG_REG17_save_read_q_SIZE; + } vgt_debug_reg17_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg17_t f; +} vgt_debug_reg17_u; + + +/* + * VGT_DEBUG_REG18 struct + */ + +#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE 6 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE 6 +#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE 1 +#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE 2 +#define VGT_DEBUG_REG18_dma_mem_full_SIZE 1 +#define VGT_DEBUG_REG18_dma_ram_re_SIZE 1 +#define VGT_DEBUG_REG18_dma_ram_we_SIZE 1 +#define VGT_DEBUG_REG18_dma_mem_empty_SIZE 1 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE 1 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE 1 +#define VGT_DEBUG_REG18_bin_mem_full_SIZE 1 +#define VGT_DEBUG_REG18_bin_ram_we_SIZE 1 +#define VGT_DEBUG_REG18_bin_ram_re_SIZE 1 +#define VGT_DEBUG_REG18_bin_mem_empty_SIZE 1 +#define VGT_DEBUG_REG18_start_bin_req_SIZE 1 +#define VGT_DEBUG_REG18_fetch_cull_not_used_SIZE 1 +#define VGT_DEBUG_REG18_dma_req_xfer_SIZE 1 +#define VGT_DEBUG_REG18_have_valid_bin_req_SIZE 1 +#define VGT_DEBUG_REG18_have_valid_dma_req_SIZE 1 +#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE 1 +#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE 1 + +#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT 0 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT 6 +#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT 12 +#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT 13 +#define VGT_DEBUG_REG18_dma_mem_full_SHIFT 15 +#define VGT_DEBUG_REG18_dma_ram_re_SHIFT 16 +#define VGT_DEBUG_REG18_dma_ram_we_SHIFT 17 +#define VGT_DEBUG_REG18_dma_mem_empty_SHIFT 18 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT 19 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT 20 +#define VGT_DEBUG_REG18_bin_mem_full_SHIFT 21 +#define VGT_DEBUG_REG18_bin_ram_we_SHIFT 22 +#define VGT_DEBUG_REG18_bin_ram_re_SHIFT 23 +#define VGT_DEBUG_REG18_bin_mem_empty_SHIFT 24 +#define VGT_DEBUG_REG18_start_bin_req_SHIFT 25 +#define VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT 26 +#define VGT_DEBUG_REG18_dma_req_xfer_SHIFT 27 +#define VGT_DEBUG_REG18_have_valid_bin_req_SHIFT 28 +#define VGT_DEBUG_REG18_have_valid_dma_req_SHIFT 29 +#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT 30 +#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT 31 + +#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK 0x0000003f +#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK 0x00000fc0 +#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK 0x00001000 +#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK 0x00006000 +#define VGT_DEBUG_REG18_dma_mem_full_MASK 0x00008000 +#define VGT_DEBUG_REG18_dma_ram_re_MASK 0x00010000 +#define VGT_DEBUG_REG18_dma_ram_we_MASK 0x00020000 +#define VGT_DEBUG_REG18_dma_mem_empty_MASK 0x00040000 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK 0x00080000 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK 0x00100000 +#define VGT_DEBUG_REG18_bin_mem_full_MASK 0x00200000 +#define VGT_DEBUG_REG18_bin_ram_we_MASK 0x00400000 +#define VGT_DEBUG_REG18_bin_ram_re_MASK 0x00800000 +#define VGT_DEBUG_REG18_bin_mem_empty_MASK 0x01000000 +#define VGT_DEBUG_REG18_start_bin_req_MASK 0x02000000 +#define VGT_DEBUG_REG18_fetch_cull_not_used_MASK 0x04000000 +#define VGT_DEBUG_REG18_dma_req_xfer_MASK 0x08000000 +#define VGT_DEBUG_REG18_have_valid_bin_req_MASK 0x10000000 +#define VGT_DEBUG_REG18_have_valid_dma_req_MASK 0x20000000 +#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK 0x40000000 +#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK 0x80000000 + +#define VGT_DEBUG_REG18_MASK \ + (VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK | \ + VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK | \ + VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK | \ + VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK | \ + VGT_DEBUG_REG18_dma_mem_full_MASK | \ + VGT_DEBUG_REG18_dma_ram_re_MASK | \ + VGT_DEBUG_REG18_dma_ram_we_MASK | \ + VGT_DEBUG_REG18_dma_mem_empty_MASK | \ + VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK | \ + VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK | \ + VGT_DEBUG_REG18_bin_mem_full_MASK | \ + VGT_DEBUG_REG18_bin_ram_we_MASK | \ + VGT_DEBUG_REG18_bin_ram_re_MASK | \ + VGT_DEBUG_REG18_bin_mem_empty_MASK | \ + VGT_DEBUG_REG18_start_bin_req_MASK | \ + VGT_DEBUG_REG18_fetch_cull_not_used_MASK | \ + VGT_DEBUG_REG18_dma_req_xfer_MASK | \ + VGT_DEBUG_REG18_have_valid_bin_req_MASK | \ + VGT_DEBUG_REG18_have_valid_dma_req_MASK | \ + VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK | \ + VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) + +#define VGT_DEBUG_REG18(dma_data_fifo_mem_raddr, dma_data_fifo_mem_waddr, dma_bgrp_byte_mask_fifo_re, dma_bgrp_dma_data_fifo_rptr, dma_mem_full, dma_ram_re, dma_ram_we, dma_mem_empty, dma_data_fifo_mem_re, dma_data_fifo_mem_we, bin_mem_full, bin_ram_we, bin_ram_re, bin_mem_empty, start_bin_req, fetch_cull_not_used, dma_req_xfer, have_valid_bin_req, have_valid_dma_req, bgrp_dma_di_grp_cull_enable, bgrp_dma_di_pre_fetch_cull_enable) \ + ((dma_data_fifo_mem_raddr << VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT) | \ + (dma_data_fifo_mem_waddr << VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT) | \ + (dma_bgrp_byte_mask_fifo_re << VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT) | \ + (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT) | \ + (dma_mem_full << VGT_DEBUG_REG18_dma_mem_full_SHIFT) | \ + (dma_ram_re << VGT_DEBUG_REG18_dma_ram_re_SHIFT) | \ + (dma_ram_we << VGT_DEBUG_REG18_dma_ram_we_SHIFT) | \ + (dma_mem_empty << VGT_DEBUG_REG18_dma_mem_empty_SHIFT) | \ + (dma_data_fifo_mem_re << VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT) | \ + (dma_data_fifo_mem_we << VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT) | \ + (bin_mem_full << VGT_DEBUG_REG18_bin_mem_full_SHIFT) | \ + (bin_ram_we << VGT_DEBUG_REG18_bin_ram_we_SHIFT) | \ + (bin_ram_re << VGT_DEBUG_REG18_bin_ram_re_SHIFT) | \ + (bin_mem_empty << VGT_DEBUG_REG18_bin_mem_empty_SHIFT) | \ + (start_bin_req << VGT_DEBUG_REG18_start_bin_req_SHIFT) | \ + (fetch_cull_not_used << VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT) | \ + (dma_req_xfer << VGT_DEBUG_REG18_dma_req_xfer_SHIFT) | \ + (have_valid_bin_req << VGT_DEBUG_REG18_have_valid_bin_req_SHIFT) | \ + (have_valid_dma_req << VGT_DEBUG_REG18_have_valid_dma_req_SHIFT) | \ + (bgrp_dma_di_grp_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT) | \ + (bgrp_dma_di_pre_fetch_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT)) + +#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_raddr(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_waddr(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_bgrp_byte_mask_fifo_re(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK) >> VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK) >> VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_mem_full(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_mem_full_MASK) >> VGT_DEBUG_REG18_dma_mem_full_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_ram_re(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_ram_re_MASK) >> VGT_DEBUG_REG18_dma_ram_re_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_ram_we(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_ram_we_MASK) >> VGT_DEBUG_REG18_dma_ram_we_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_mem_empty(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_mem_empty_MASK) >> VGT_DEBUG_REG18_dma_mem_empty_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_re(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_we(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT) +#define VGT_DEBUG_REG18_GET_bin_mem_full(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_mem_full_MASK) >> VGT_DEBUG_REG18_bin_mem_full_SHIFT) +#define VGT_DEBUG_REG18_GET_bin_ram_we(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_ram_we_MASK) >> VGT_DEBUG_REG18_bin_ram_we_SHIFT) +#define VGT_DEBUG_REG18_GET_bin_ram_re(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_ram_re_MASK) >> VGT_DEBUG_REG18_bin_ram_re_SHIFT) +#define VGT_DEBUG_REG18_GET_bin_mem_empty(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_mem_empty_MASK) >> VGT_DEBUG_REG18_bin_mem_empty_SHIFT) +#define VGT_DEBUG_REG18_GET_start_bin_req(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_start_bin_req_MASK) >> VGT_DEBUG_REG18_start_bin_req_SHIFT) +#define VGT_DEBUG_REG18_GET_fetch_cull_not_used(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_fetch_cull_not_used_MASK) >> VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_req_xfer(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_req_xfer_MASK) >> VGT_DEBUG_REG18_dma_req_xfer_SHIFT) +#define VGT_DEBUG_REG18_GET_have_valid_bin_req(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_have_valid_bin_req_MASK) >> VGT_DEBUG_REG18_have_valid_bin_req_SHIFT) +#define VGT_DEBUG_REG18_GET_have_valid_dma_req(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_have_valid_dma_req_MASK) >> VGT_DEBUG_REG18_have_valid_dma_req_SHIFT) +#define VGT_DEBUG_REG18_GET_bgrp_dma_di_grp_cull_enable(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK) >> VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT) +#define VGT_DEBUG_REG18_GET_bgrp_dma_di_pre_fetch_cull_enable(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) >> VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT) + +#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_raddr(vgt_debug_reg18_reg, dma_data_fifo_mem_raddr) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK) | (dma_data_fifo_mem_raddr << VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_waddr(vgt_debug_reg18_reg, dma_data_fifo_mem_waddr) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK) | (dma_data_fifo_mem_waddr << VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_bgrp_byte_mask_fifo_re(vgt_debug_reg18_reg, dma_bgrp_byte_mask_fifo_re) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK) | (dma_bgrp_byte_mask_fifo_re << VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg18_reg, dma_bgrp_dma_data_fifo_rptr) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK) | (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_mem_full(vgt_debug_reg18_reg, dma_mem_full) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_mem_full_MASK) | (dma_mem_full << VGT_DEBUG_REG18_dma_mem_full_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_ram_re(vgt_debug_reg18_reg, dma_ram_re) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_ram_re_MASK) | (dma_ram_re << VGT_DEBUG_REG18_dma_ram_re_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_ram_we(vgt_debug_reg18_reg, dma_ram_we) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_ram_we_MASK) | (dma_ram_we << VGT_DEBUG_REG18_dma_ram_we_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_mem_empty(vgt_debug_reg18_reg, dma_mem_empty) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_mem_empty_MASK) | (dma_mem_empty << VGT_DEBUG_REG18_dma_mem_empty_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_re(vgt_debug_reg18_reg, dma_data_fifo_mem_re) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK) | (dma_data_fifo_mem_re << VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_we(vgt_debug_reg18_reg, dma_data_fifo_mem_we) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK) | (dma_data_fifo_mem_we << VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT) +#define VGT_DEBUG_REG18_SET_bin_mem_full(vgt_debug_reg18_reg, bin_mem_full) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_mem_full_MASK) | (bin_mem_full << VGT_DEBUG_REG18_bin_mem_full_SHIFT) +#define VGT_DEBUG_REG18_SET_bin_ram_we(vgt_debug_reg18_reg, bin_ram_we) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_ram_we_MASK) | (bin_ram_we << VGT_DEBUG_REG18_bin_ram_we_SHIFT) +#define VGT_DEBUG_REG18_SET_bin_ram_re(vgt_debug_reg18_reg, bin_ram_re) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_ram_re_MASK) | (bin_ram_re << VGT_DEBUG_REG18_bin_ram_re_SHIFT) +#define VGT_DEBUG_REG18_SET_bin_mem_empty(vgt_debug_reg18_reg, bin_mem_empty) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_mem_empty_MASK) | (bin_mem_empty << VGT_DEBUG_REG18_bin_mem_empty_SHIFT) +#define VGT_DEBUG_REG18_SET_start_bin_req(vgt_debug_reg18_reg, start_bin_req) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_start_bin_req_MASK) | (start_bin_req << VGT_DEBUG_REG18_start_bin_req_SHIFT) +#define VGT_DEBUG_REG18_SET_fetch_cull_not_used(vgt_debug_reg18_reg, fetch_cull_not_used) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_fetch_cull_not_used_MASK) | (fetch_cull_not_used << VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_req_xfer(vgt_debug_reg18_reg, dma_req_xfer) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_req_xfer_MASK) | (dma_req_xfer << VGT_DEBUG_REG18_dma_req_xfer_SHIFT) +#define VGT_DEBUG_REG18_SET_have_valid_bin_req(vgt_debug_reg18_reg, have_valid_bin_req) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_have_valid_bin_req_MASK) | (have_valid_bin_req << VGT_DEBUG_REG18_have_valid_bin_req_SHIFT) +#define VGT_DEBUG_REG18_SET_have_valid_dma_req(vgt_debug_reg18_reg, have_valid_dma_req) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_have_valid_dma_req_MASK) | (have_valid_dma_req << VGT_DEBUG_REG18_have_valid_dma_req_SHIFT) +#define VGT_DEBUG_REG18_SET_bgrp_dma_di_grp_cull_enable(vgt_debug_reg18_reg, bgrp_dma_di_grp_cull_enable) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK) | (bgrp_dma_di_grp_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT) +#define VGT_DEBUG_REG18_SET_bgrp_dma_di_pre_fetch_cull_enable(vgt_debug_reg18_reg, bgrp_dma_di_pre_fetch_cull_enable) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) | (bgrp_dma_di_pre_fetch_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg18_t { + unsigned int dma_data_fifo_mem_raddr : VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE; + unsigned int dma_data_fifo_mem_waddr : VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE; + unsigned int dma_bgrp_byte_mask_fifo_re : VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE; + unsigned int dma_bgrp_dma_data_fifo_rptr : VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE; + unsigned int dma_mem_full : VGT_DEBUG_REG18_dma_mem_full_SIZE; + unsigned int dma_ram_re : VGT_DEBUG_REG18_dma_ram_re_SIZE; + unsigned int dma_ram_we : VGT_DEBUG_REG18_dma_ram_we_SIZE; + unsigned int dma_mem_empty : VGT_DEBUG_REG18_dma_mem_empty_SIZE; + unsigned int dma_data_fifo_mem_re : VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE; + unsigned int dma_data_fifo_mem_we : VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE; + unsigned int bin_mem_full : VGT_DEBUG_REG18_bin_mem_full_SIZE; + unsigned int bin_ram_we : VGT_DEBUG_REG18_bin_ram_we_SIZE; + unsigned int bin_ram_re : VGT_DEBUG_REG18_bin_ram_re_SIZE; + unsigned int bin_mem_empty : VGT_DEBUG_REG18_bin_mem_empty_SIZE; + unsigned int start_bin_req : VGT_DEBUG_REG18_start_bin_req_SIZE; + unsigned int fetch_cull_not_used : VGT_DEBUG_REG18_fetch_cull_not_used_SIZE; + unsigned int dma_req_xfer : VGT_DEBUG_REG18_dma_req_xfer_SIZE; + unsigned int have_valid_bin_req : VGT_DEBUG_REG18_have_valid_bin_req_SIZE; + unsigned int have_valid_dma_req : VGT_DEBUG_REG18_have_valid_dma_req_SIZE; + unsigned int bgrp_dma_di_grp_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE; + unsigned int bgrp_dma_di_pre_fetch_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE; + } vgt_debug_reg18_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg18_t { + unsigned int bgrp_dma_di_pre_fetch_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE; + unsigned int bgrp_dma_di_grp_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE; + unsigned int have_valid_dma_req : VGT_DEBUG_REG18_have_valid_dma_req_SIZE; + unsigned int have_valid_bin_req : VGT_DEBUG_REG18_have_valid_bin_req_SIZE; + unsigned int dma_req_xfer : VGT_DEBUG_REG18_dma_req_xfer_SIZE; + unsigned int fetch_cull_not_used : VGT_DEBUG_REG18_fetch_cull_not_used_SIZE; + unsigned int start_bin_req : VGT_DEBUG_REG18_start_bin_req_SIZE; + unsigned int bin_mem_empty : VGT_DEBUG_REG18_bin_mem_empty_SIZE; + unsigned int bin_ram_re : VGT_DEBUG_REG18_bin_ram_re_SIZE; + unsigned int bin_ram_we : VGT_DEBUG_REG18_bin_ram_we_SIZE; + unsigned int bin_mem_full : VGT_DEBUG_REG18_bin_mem_full_SIZE; + unsigned int dma_data_fifo_mem_we : VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE; + unsigned int dma_data_fifo_mem_re : VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE; + unsigned int dma_mem_empty : VGT_DEBUG_REG18_dma_mem_empty_SIZE; + unsigned int dma_ram_we : VGT_DEBUG_REG18_dma_ram_we_SIZE; + unsigned int dma_ram_re : VGT_DEBUG_REG18_dma_ram_re_SIZE; + unsigned int dma_mem_full : VGT_DEBUG_REG18_dma_mem_full_SIZE; + unsigned int dma_bgrp_dma_data_fifo_rptr : VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE; + unsigned int dma_bgrp_byte_mask_fifo_re : VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE; + unsigned int dma_data_fifo_mem_waddr : VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE; + unsigned int dma_data_fifo_mem_raddr : VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE; + } vgt_debug_reg18_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg18_t f; +} vgt_debug_reg18_u; + + +/* + * VGT_DEBUG_REG20 struct + */ + +#define VGT_DEBUG_REG20_prim_side_indx_valid_SIZE 1 +#define VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE 1 +#define VGT_DEBUG_REG20_indx_side_fifo_re_SIZE 1 +#define VGT_DEBUG_REG20_indx_side_fifo_we_SIZE 1 +#define VGT_DEBUG_REG20_indx_side_fifo_full_SIZE 1 +#define VGT_DEBUG_REG20_prim_buffer_empty_SIZE 1 +#define VGT_DEBUG_REG20_prim_buffer_re_SIZE 1 +#define VGT_DEBUG_REG20_prim_buffer_we_SIZE 1 +#define VGT_DEBUG_REG20_prim_buffer_full_SIZE 1 +#define VGT_DEBUG_REG20_indx_buffer_empty_SIZE 1 +#define VGT_DEBUG_REG20_indx_buffer_re_SIZE 1 +#define VGT_DEBUG_REG20_indx_buffer_we_SIZE 1 +#define VGT_DEBUG_REG20_indx_buffer_full_SIZE 1 +#define VGT_DEBUG_REG20_hold_prim_SIZE 1 +#define VGT_DEBUG_REG20_sent_cnt_SIZE 4 +#define VGT_DEBUG_REG20_start_of_vtx_vector_SIZE 1 +#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE 1 +#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE 1 +#define VGT_DEBUG_REG20_buffered_prim_type_event_SIZE 5 +#define VGT_DEBUG_REG20_out_trigger_SIZE 1 + +#define VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT 0 +#define VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT 1 +#define VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT 2 +#define VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT 3 +#define VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT 4 +#define VGT_DEBUG_REG20_prim_buffer_empty_SHIFT 5 +#define VGT_DEBUG_REG20_prim_buffer_re_SHIFT 6 +#define VGT_DEBUG_REG20_prim_buffer_we_SHIFT 7 +#define VGT_DEBUG_REG20_prim_buffer_full_SHIFT 8 +#define VGT_DEBUG_REG20_indx_buffer_empty_SHIFT 9 +#define VGT_DEBUG_REG20_indx_buffer_re_SHIFT 10 +#define VGT_DEBUG_REG20_indx_buffer_we_SHIFT 11 +#define VGT_DEBUG_REG20_indx_buffer_full_SHIFT 12 +#define VGT_DEBUG_REG20_hold_prim_SHIFT 13 +#define VGT_DEBUG_REG20_sent_cnt_SHIFT 14 +#define VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT 18 +#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT 19 +#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT 20 +#define VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT 21 +#define VGT_DEBUG_REG20_out_trigger_SHIFT 26 + +#define VGT_DEBUG_REG20_prim_side_indx_valid_MASK 0x00000001 +#define VGT_DEBUG_REG20_indx_side_fifo_empty_MASK 0x00000002 +#define VGT_DEBUG_REG20_indx_side_fifo_re_MASK 0x00000004 +#define VGT_DEBUG_REG20_indx_side_fifo_we_MASK 0x00000008 +#define VGT_DEBUG_REG20_indx_side_fifo_full_MASK 0x00000010 +#define VGT_DEBUG_REG20_prim_buffer_empty_MASK 0x00000020 +#define VGT_DEBUG_REG20_prim_buffer_re_MASK 0x00000040 +#define VGT_DEBUG_REG20_prim_buffer_we_MASK 0x00000080 +#define VGT_DEBUG_REG20_prim_buffer_full_MASK 0x00000100 +#define VGT_DEBUG_REG20_indx_buffer_empty_MASK 0x00000200 +#define VGT_DEBUG_REG20_indx_buffer_re_MASK 0x00000400 +#define VGT_DEBUG_REG20_indx_buffer_we_MASK 0x00000800 +#define VGT_DEBUG_REG20_indx_buffer_full_MASK 0x00001000 +#define VGT_DEBUG_REG20_hold_prim_MASK 0x00002000 +#define VGT_DEBUG_REG20_sent_cnt_MASK 0x0003c000 +#define VGT_DEBUG_REG20_start_of_vtx_vector_MASK 0x00040000 +#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK 0x00080000 +#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK 0x00100000 +#define VGT_DEBUG_REG20_buffered_prim_type_event_MASK 0x03e00000 +#define VGT_DEBUG_REG20_out_trigger_MASK 0x04000000 + +#define VGT_DEBUG_REG20_MASK \ + (VGT_DEBUG_REG20_prim_side_indx_valid_MASK | \ + VGT_DEBUG_REG20_indx_side_fifo_empty_MASK | \ + VGT_DEBUG_REG20_indx_side_fifo_re_MASK | \ + VGT_DEBUG_REG20_indx_side_fifo_we_MASK | \ + VGT_DEBUG_REG20_indx_side_fifo_full_MASK | \ + VGT_DEBUG_REG20_prim_buffer_empty_MASK | \ + VGT_DEBUG_REG20_prim_buffer_re_MASK | \ + VGT_DEBUG_REG20_prim_buffer_we_MASK | \ + VGT_DEBUG_REG20_prim_buffer_full_MASK | \ + VGT_DEBUG_REG20_indx_buffer_empty_MASK | \ + VGT_DEBUG_REG20_indx_buffer_re_MASK | \ + VGT_DEBUG_REG20_indx_buffer_we_MASK | \ + VGT_DEBUG_REG20_indx_buffer_full_MASK | \ + VGT_DEBUG_REG20_hold_prim_MASK | \ + VGT_DEBUG_REG20_sent_cnt_MASK | \ + VGT_DEBUG_REG20_start_of_vtx_vector_MASK | \ + VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK | \ + VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK | \ + VGT_DEBUG_REG20_buffered_prim_type_event_MASK | \ + VGT_DEBUG_REG20_out_trigger_MASK) + +#define VGT_DEBUG_REG20(prim_side_indx_valid, indx_side_fifo_empty, indx_side_fifo_re, indx_side_fifo_we, indx_side_fifo_full, prim_buffer_empty, prim_buffer_re, prim_buffer_we, prim_buffer_full, indx_buffer_empty, indx_buffer_re, indx_buffer_we, indx_buffer_full, hold_prim, sent_cnt, start_of_vtx_vector, clip_s_pre_hold_prim, clip_p_pre_hold_prim, buffered_prim_type_event, out_trigger) \ + ((prim_side_indx_valid << VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT) | \ + (indx_side_fifo_empty << VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT) | \ + (indx_side_fifo_re << VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT) | \ + (indx_side_fifo_we << VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT) | \ + (indx_side_fifo_full << VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT) | \ + (prim_buffer_empty << VGT_DEBUG_REG20_prim_buffer_empty_SHIFT) | \ + (prim_buffer_re << VGT_DEBUG_REG20_prim_buffer_re_SHIFT) | \ + (prim_buffer_we << VGT_DEBUG_REG20_prim_buffer_we_SHIFT) | \ + (prim_buffer_full << VGT_DEBUG_REG20_prim_buffer_full_SHIFT) | \ + (indx_buffer_empty << VGT_DEBUG_REG20_indx_buffer_empty_SHIFT) | \ + (indx_buffer_re << VGT_DEBUG_REG20_indx_buffer_re_SHIFT) | \ + (indx_buffer_we << VGT_DEBUG_REG20_indx_buffer_we_SHIFT) | \ + (indx_buffer_full << VGT_DEBUG_REG20_indx_buffer_full_SHIFT) | \ + (hold_prim << VGT_DEBUG_REG20_hold_prim_SHIFT) | \ + (sent_cnt << VGT_DEBUG_REG20_sent_cnt_SHIFT) | \ + (start_of_vtx_vector << VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT) | \ + (clip_s_pre_hold_prim << VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT) | \ + (clip_p_pre_hold_prim << VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT) | \ + (buffered_prim_type_event << VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT) | \ + (out_trigger << VGT_DEBUG_REG20_out_trigger_SHIFT)) + +#define VGT_DEBUG_REG20_GET_prim_side_indx_valid(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_side_indx_valid_MASK) >> VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_side_fifo_empty(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_empty_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_side_fifo_re(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_re_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_side_fifo_we(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_we_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_side_fifo_full(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_full_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT) +#define VGT_DEBUG_REG20_GET_prim_buffer_empty(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_empty_MASK) >> VGT_DEBUG_REG20_prim_buffer_empty_SHIFT) +#define VGT_DEBUG_REG20_GET_prim_buffer_re(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_re_MASK) >> VGT_DEBUG_REG20_prim_buffer_re_SHIFT) +#define VGT_DEBUG_REG20_GET_prim_buffer_we(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_we_MASK) >> VGT_DEBUG_REG20_prim_buffer_we_SHIFT) +#define VGT_DEBUG_REG20_GET_prim_buffer_full(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_full_MASK) >> VGT_DEBUG_REG20_prim_buffer_full_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_buffer_empty(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_empty_MASK) >> VGT_DEBUG_REG20_indx_buffer_empty_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_buffer_re(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_re_MASK) >> VGT_DEBUG_REG20_indx_buffer_re_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_buffer_we(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_we_MASK) >> VGT_DEBUG_REG20_indx_buffer_we_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_buffer_full(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_full_MASK) >> VGT_DEBUG_REG20_indx_buffer_full_SHIFT) +#define VGT_DEBUG_REG20_GET_hold_prim(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_hold_prim_MASK) >> VGT_DEBUG_REG20_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_GET_sent_cnt(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_sent_cnt_MASK) >> VGT_DEBUG_REG20_sent_cnt_SHIFT) +#define VGT_DEBUG_REG20_GET_start_of_vtx_vector(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_start_of_vtx_vector_MASK) >> VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT) +#define VGT_DEBUG_REG20_GET_clip_s_pre_hold_prim(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK) >> VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_GET_clip_p_pre_hold_prim(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK) >> VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_GET_buffered_prim_type_event(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_buffered_prim_type_event_MASK) >> VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT) +#define VGT_DEBUG_REG20_GET_out_trigger(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_out_trigger_MASK) >> VGT_DEBUG_REG20_out_trigger_SHIFT) + +#define VGT_DEBUG_REG20_SET_prim_side_indx_valid(vgt_debug_reg20_reg, prim_side_indx_valid) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_side_indx_valid_MASK) | (prim_side_indx_valid << VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_side_fifo_empty(vgt_debug_reg20_reg, indx_side_fifo_empty) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_empty_MASK) | (indx_side_fifo_empty << VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_side_fifo_re(vgt_debug_reg20_reg, indx_side_fifo_re) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_re_MASK) | (indx_side_fifo_re << VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_side_fifo_we(vgt_debug_reg20_reg, indx_side_fifo_we) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_we_MASK) | (indx_side_fifo_we << VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_side_fifo_full(vgt_debug_reg20_reg, indx_side_fifo_full) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_full_MASK) | (indx_side_fifo_full << VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT) +#define VGT_DEBUG_REG20_SET_prim_buffer_empty(vgt_debug_reg20_reg, prim_buffer_empty) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_empty_MASK) | (prim_buffer_empty << VGT_DEBUG_REG20_prim_buffer_empty_SHIFT) +#define VGT_DEBUG_REG20_SET_prim_buffer_re(vgt_debug_reg20_reg, prim_buffer_re) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_re_MASK) | (prim_buffer_re << VGT_DEBUG_REG20_prim_buffer_re_SHIFT) +#define VGT_DEBUG_REG20_SET_prim_buffer_we(vgt_debug_reg20_reg, prim_buffer_we) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_we_MASK) | (prim_buffer_we << VGT_DEBUG_REG20_prim_buffer_we_SHIFT) +#define VGT_DEBUG_REG20_SET_prim_buffer_full(vgt_debug_reg20_reg, prim_buffer_full) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_full_MASK) | (prim_buffer_full << VGT_DEBUG_REG20_prim_buffer_full_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_buffer_empty(vgt_debug_reg20_reg, indx_buffer_empty) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_empty_MASK) | (indx_buffer_empty << VGT_DEBUG_REG20_indx_buffer_empty_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_buffer_re(vgt_debug_reg20_reg, indx_buffer_re) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_re_MASK) | (indx_buffer_re << VGT_DEBUG_REG20_indx_buffer_re_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_buffer_we(vgt_debug_reg20_reg, indx_buffer_we) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_we_MASK) | (indx_buffer_we << VGT_DEBUG_REG20_indx_buffer_we_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_buffer_full(vgt_debug_reg20_reg, indx_buffer_full) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_full_MASK) | (indx_buffer_full << VGT_DEBUG_REG20_indx_buffer_full_SHIFT) +#define VGT_DEBUG_REG20_SET_hold_prim(vgt_debug_reg20_reg, hold_prim) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_hold_prim_MASK) | (hold_prim << VGT_DEBUG_REG20_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_SET_sent_cnt(vgt_debug_reg20_reg, sent_cnt) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_sent_cnt_MASK) | (sent_cnt << VGT_DEBUG_REG20_sent_cnt_SHIFT) +#define VGT_DEBUG_REG20_SET_start_of_vtx_vector(vgt_debug_reg20_reg, start_of_vtx_vector) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_start_of_vtx_vector_MASK) | (start_of_vtx_vector << VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT) +#define VGT_DEBUG_REG20_SET_clip_s_pre_hold_prim(vgt_debug_reg20_reg, clip_s_pre_hold_prim) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK) | (clip_s_pre_hold_prim << VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_SET_clip_p_pre_hold_prim(vgt_debug_reg20_reg, clip_p_pre_hold_prim) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK) | (clip_p_pre_hold_prim << VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_SET_buffered_prim_type_event(vgt_debug_reg20_reg, buffered_prim_type_event) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_buffered_prim_type_event_MASK) | (buffered_prim_type_event << VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT) +#define VGT_DEBUG_REG20_SET_out_trigger(vgt_debug_reg20_reg, out_trigger) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_out_trigger_MASK) | (out_trigger << VGT_DEBUG_REG20_out_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg20_t { + unsigned int prim_side_indx_valid : VGT_DEBUG_REG20_prim_side_indx_valid_SIZE; + unsigned int indx_side_fifo_empty : VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE; + unsigned int indx_side_fifo_re : VGT_DEBUG_REG20_indx_side_fifo_re_SIZE; + unsigned int indx_side_fifo_we : VGT_DEBUG_REG20_indx_side_fifo_we_SIZE; + unsigned int indx_side_fifo_full : VGT_DEBUG_REG20_indx_side_fifo_full_SIZE; + unsigned int prim_buffer_empty : VGT_DEBUG_REG20_prim_buffer_empty_SIZE; + unsigned int prim_buffer_re : VGT_DEBUG_REG20_prim_buffer_re_SIZE; + unsigned int prim_buffer_we : VGT_DEBUG_REG20_prim_buffer_we_SIZE; + unsigned int prim_buffer_full : VGT_DEBUG_REG20_prim_buffer_full_SIZE; + unsigned int indx_buffer_empty : VGT_DEBUG_REG20_indx_buffer_empty_SIZE; + unsigned int indx_buffer_re : VGT_DEBUG_REG20_indx_buffer_re_SIZE; + unsigned int indx_buffer_we : VGT_DEBUG_REG20_indx_buffer_we_SIZE; + unsigned int indx_buffer_full : VGT_DEBUG_REG20_indx_buffer_full_SIZE; + unsigned int hold_prim : VGT_DEBUG_REG20_hold_prim_SIZE; + unsigned int sent_cnt : VGT_DEBUG_REG20_sent_cnt_SIZE; + unsigned int start_of_vtx_vector : VGT_DEBUG_REG20_start_of_vtx_vector_SIZE; + unsigned int clip_s_pre_hold_prim : VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE; + unsigned int clip_p_pre_hold_prim : VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE; + unsigned int buffered_prim_type_event : VGT_DEBUG_REG20_buffered_prim_type_event_SIZE; + unsigned int out_trigger : VGT_DEBUG_REG20_out_trigger_SIZE; + unsigned int : 5; + } vgt_debug_reg20_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg20_t { + unsigned int : 5; + unsigned int out_trigger : VGT_DEBUG_REG20_out_trigger_SIZE; + unsigned int buffered_prim_type_event : VGT_DEBUG_REG20_buffered_prim_type_event_SIZE; + unsigned int clip_p_pre_hold_prim : VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE; + unsigned int clip_s_pre_hold_prim : VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE; + unsigned int start_of_vtx_vector : VGT_DEBUG_REG20_start_of_vtx_vector_SIZE; + unsigned int sent_cnt : VGT_DEBUG_REG20_sent_cnt_SIZE; + unsigned int hold_prim : VGT_DEBUG_REG20_hold_prim_SIZE; + unsigned int indx_buffer_full : VGT_DEBUG_REG20_indx_buffer_full_SIZE; + unsigned int indx_buffer_we : VGT_DEBUG_REG20_indx_buffer_we_SIZE; + unsigned int indx_buffer_re : VGT_DEBUG_REG20_indx_buffer_re_SIZE; + unsigned int indx_buffer_empty : VGT_DEBUG_REG20_indx_buffer_empty_SIZE; + unsigned int prim_buffer_full : VGT_DEBUG_REG20_prim_buffer_full_SIZE; + unsigned int prim_buffer_we : VGT_DEBUG_REG20_prim_buffer_we_SIZE; + unsigned int prim_buffer_re : VGT_DEBUG_REG20_prim_buffer_re_SIZE; + unsigned int prim_buffer_empty : VGT_DEBUG_REG20_prim_buffer_empty_SIZE; + unsigned int indx_side_fifo_full : VGT_DEBUG_REG20_indx_side_fifo_full_SIZE; + unsigned int indx_side_fifo_we : VGT_DEBUG_REG20_indx_side_fifo_we_SIZE; + unsigned int indx_side_fifo_re : VGT_DEBUG_REG20_indx_side_fifo_re_SIZE; + unsigned int indx_side_fifo_empty : VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE; + unsigned int prim_side_indx_valid : VGT_DEBUG_REG20_prim_side_indx_valid_SIZE; + } vgt_debug_reg20_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg20_t f; +} vgt_debug_reg20_u; + + +/* + * VGT_DEBUG_REG21 struct + */ + +#define VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE 1 +#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE 3 +#define VGT_DEBUG_REG21_alloc_counter_q_SIZE 3 +#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE 3 +#define VGT_DEBUG_REG21_int_vtx_counter_q_SIZE 4 +#define VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE 4 +#define VGT_DEBUG_REG21_new_packet_q_SIZE 1 +#define VGT_DEBUG_REG21_new_allocate_q_SIZE 1 +#define VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE 2 +#define VGT_DEBUG_REG21_inserted_null_prim_q_SIZE 1 +#define VGT_DEBUG_REG21_insert_null_prim_SIZE 1 +#define VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE 1 +#define VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE 1 +#define VGT_DEBUG_REG21_buffered_thread_size_SIZE 1 +#define VGT_DEBUG_REG21_out_trigger_SIZE 1 + +#define VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT 0 +#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT 1 +#define VGT_DEBUG_REG21_alloc_counter_q_SHIFT 4 +#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT 7 +#define VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT 10 +#define VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT 14 +#define VGT_DEBUG_REG21_new_packet_q_SHIFT 18 +#define VGT_DEBUG_REG21_new_allocate_q_SHIFT 19 +#define VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT 20 +#define VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT 22 +#define VGT_DEBUG_REG21_insert_null_prim_SHIFT 23 +#define VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT 24 +#define VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT 25 +#define VGT_DEBUG_REG21_buffered_thread_size_SHIFT 26 +#define VGT_DEBUG_REG21_out_trigger_SHIFT 31 + +#define VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK 0x00000001 +#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK 0x0000000e +#define VGT_DEBUG_REG21_alloc_counter_q_MASK 0x00000070 +#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK 0x00000380 +#define VGT_DEBUG_REG21_int_vtx_counter_q_MASK 0x00003c00 +#define VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK 0x0003c000 +#define VGT_DEBUG_REG21_new_packet_q_MASK 0x00040000 +#define VGT_DEBUG_REG21_new_allocate_q_MASK 0x00080000 +#define VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK 0x00300000 +#define VGT_DEBUG_REG21_inserted_null_prim_q_MASK 0x00400000 +#define VGT_DEBUG_REG21_insert_null_prim_MASK 0x00800000 +#define VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK 0x01000000 +#define VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK 0x02000000 +#define VGT_DEBUG_REG21_buffered_thread_size_MASK 0x04000000 +#define VGT_DEBUG_REG21_out_trigger_MASK 0x80000000 + +#define VGT_DEBUG_REG21_MASK \ + (VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK | \ + VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK | \ + VGT_DEBUG_REG21_alloc_counter_q_MASK | \ + VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK | \ + VGT_DEBUG_REG21_int_vtx_counter_q_MASK | \ + VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK | \ + VGT_DEBUG_REG21_new_packet_q_MASK | \ + VGT_DEBUG_REG21_new_allocate_q_MASK | \ + VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK | \ + VGT_DEBUG_REG21_inserted_null_prim_q_MASK | \ + VGT_DEBUG_REG21_insert_null_prim_MASK | \ + VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK | \ + VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK | \ + VGT_DEBUG_REG21_buffered_thread_size_MASK | \ + VGT_DEBUG_REG21_out_trigger_MASK) + +#define VGT_DEBUG_REG21(null_terminate_vtx_vector, prim_end_of_vtx_vect_flags, alloc_counter_q, curr_slot_in_vtx_vect_q, int_vtx_counter_q, curr_dealloc_distance_q, new_packet_q, new_allocate_q, num_new_unique_rel_indx, inserted_null_prim_q, insert_null_prim, buffered_prim_eop_mux, prim_buffer_empty_mux, buffered_thread_size, out_trigger) \ + ((null_terminate_vtx_vector << VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT) | \ + (prim_end_of_vtx_vect_flags << VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT) | \ + (alloc_counter_q << VGT_DEBUG_REG21_alloc_counter_q_SHIFT) | \ + (curr_slot_in_vtx_vect_q << VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT) | \ + (int_vtx_counter_q << VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT) | \ + (curr_dealloc_distance_q << VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT) | \ + (new_packet_q << VGT_DEBUG_REG21_new_packet_q_SHIFT) | \ + (new_allocate_q << VGT_DEBUG_REG21_new_allocate_q_SHIFT) | \ + (num_new_unique_rel_indx << VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT) | \ + (inserted_null_prim_q << VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT) | \ + (insert_null_prim << VGT_DEBUG_REG21_insert_null_prim_SHIFT) | \ + (buffered_prim_eop_mux << VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT) | \ + (prim_buffer_empty_mux << VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT) | \ + (buffered_thread_size << VGT_DEBUG_REG21_buffered_thread_size_SHIFT) | \ + (out_trigger << VGT_DEBUG_REG21_out_trigger_SHIFT)) + +#define VGT_DEBUG_REG21_GET_null_terminate_vtx_vector(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK) >> VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT) +#define VGT_DEBUG_REG21_GET_prim_end_of_vtx_vect_flags(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK) >> VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT) +#define VGT_DEBUG_REG21_GET_alloc_counter_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_alloc_counter_q_MASK) >> VGT_DEBUG_REG21_alloc_counter_q_SHIFT) +#define VGT_DEBUG_REG21_GET_curr_slot_in_vtx_vect_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK) >> VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT) +#define VGT_DEBUG_REG21_GET_int_vtx_counter_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_int_vtx_counter_q_MASK) >> VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT) +#define VGT_DEBUG_REG21_GET_curr_dealloc_distance_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK) >> VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT) +#define VGT_DEBUG_REG21_GET_new_packet_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_new_packet_q_MASK) >> VGT_DEBUG_REG21_new_packet_q_SHIFT) +#define VGT_DEBUG_REG21_GET_new_allocate_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_new_allocate_q_MASK) >> VGT_DEBUG_REG21_new_allocate_q_SHIFT) +#define VGT_DEBUG_REG21_GET_num_new_unique_rel_indx(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK) >> VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT) +#define VGT_DEBUG_REG21_GET_inserted_null_prim_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_inserted_null_prim_q_MASK) >> VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT) +#define VGT_DEBUG_REG21_GET_insert_null_prim(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_insert_null_prim_MASK) >> VGT_DEBUG_REG21_insert_null_prim_SHIFT) +#define VGT_DEBUG_REG21_GET_buffered_prim_eop_mux(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK) >> VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT) +#define VGT_DEBUG_REG21_GET_prim_buffer_empty_mux(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK) >> VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT) +#define VGT_DEBUG_REG21_GET_buffered_thread_size(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_buffered_thread_size_MASK) >> VGT_DEBUG_REG21_buffered_thread_size_SHIFT) +#define VGT_DEBUG_REG21_GET_out_trigger(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_out_trigger_MASK) >> VGT_DEBUG_REG21_out_trigger_SHIFT) + +#define VGT_DEBUG_REG21_SET_null_terminate_vtx_vector(vgt_debug_reg21_reg, null_terminate_vtx_vector) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK) | (null_terminate_vtx_vector << VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT) +#define VGT_DEBUG_REG21_SET_prim_end_of_vtx_vect_flags(vgt_debug_reg21_reg, prim_end_of_vtx_vect_flags) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK) | (prim_end_of_vtx_vect_flags << VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT) +#define VGT_DEBUG_REG21_SET_alloc_counter_q(vgt_debug_reg21_reg, alloc_counter_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_alloc_counter_q_MASK) | (alloc_counter_q << VGT_DEBUG_REG21_alloc_counter_q_SHIFT) +#define VGT_DEBUG_REG21_SET_curr_slot_in_vtx_vect_q(vgt_debug_reg21_reg, curr_slot_in_vtx_vect_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK) | (curr_slot_in_vtx_vect_q << VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT) +#define VGT_DEBUG_REG21_SET_int_vtx_counter_q(vgt_debug_reg21_reg, int_vtx_counter_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_int_vtx_counter_q_MASK) | (int_vtx_counter_q << VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT) +#define VGT_DEBUG_REG21_SET_curr_dealloc_distance_q(vgt_debug_reg21_reg, curr_dealloc_distance_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK) | (curr_dealloc_distance_q << VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT) +#define VGT_DEBUG_REG21_SET_new_packet_q(vgt_debug_reg21_reg, new_packet_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_new_packet_q_MASK) | (new_packet_q << VGT_DEBUG_REG21_new_packet_q_SHIFT) +#define VGT_DEBUG_REG21_SET_new_allocate_q(vgt_debug_reg21_reg, new_allocate_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_new_allocate_q_MASK) | (new_allocate_q << VGT_DEBUG_REG21_new_allocate_q_SHIFT) +#define VGT_DEBUG_REG21_SET_num_new_unique_rel_indx(vgt_debug_reg21_reg, num_new_unique_rel_indx) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK) | (num_new_unique_rel_indx << VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT) +#define VGT_DEBUG_REG21_SET_inserted_null_prim_q(vgt_debug_reg21_reg, inserted_null_prim_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_inserted_null_prim_q_MASK) | (inserted_null_prim_q << VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT) +#define VGT_DEBUG_REG21_SET_insert_null_prim(vgt_debug_reg21_reg, insert_null_prim) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_insert_null_prim_MASK) | (insert_null_prim << VGT_DEBUG_REG21_insert_null_prim_SHIFT) +#define VGT_DEBUG_REG21_SET_buffered_prim_eop_mux(vgt_debug_reg21_reg, buffered_prim_eop_mux) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK) | (buffered_prim_eop_mux << VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT) +#define VGT_DEBUG_REG21_SET_prim_buffer_empty_mux(vgt_debug_reg21_reg, prim_buffer_empty_mux) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK) | (prim_buffer_empty_mux << VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT) +#define VGT_DEBUG_REG21_SET_buffered_thread_size(vgt_debug_reg21_reg, buffered_thread_size) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_buffered_thread_size_MASK) | (buffered_thread_size << VGT_DEBUG_REG21_buffered_thread_size_SHIFT) +#define VGT_DEBUG_REG21_SET_out_trigger(vgt_debug_reg21_reg, out_trigger) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_out_trigger_MASK) | (out_trigger << VGT_DEBUG_REG21_out_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg21_t { + unsigned int null_terminate_vtx_vector : VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE; + unsigned int prim_end_of_vtx_vect_flags : VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE; + unsigned int alloc_counter_q : VGT_DEBUG_REG21_alloc_counter_q_SIZE; + unsigned int curr_slot_in_vtx_vect_q : VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE; + unsigned int int_vtx_counter_q : VGT_DEBUG_REG21_int_vtx_counter_q_SIZE; + unsigned int curr_dealloc_distance_q : VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE; + unsigned int new_packet_q : VGT_DEBUG_REG21_new_packet_q_SIZE; + unsigned int new_allocate_q : VGT_DEBUG_REG21_new_allocate_q_SIZE; + unsigned int num_new_unique_rel_indx : VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE; + unsigned int inserted_null_prim_q : VGT_DEBUG_REG21_inserted_null_prim_q_SIZE; + unsigned int insert_null_prim : VGT_DEBUG_REG21_insert_null_prim_SIZE; + unsigned int buffered_prim_eop_mux : VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE; + unsigned int prim_buffer_empty_mux : VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE; + unsigned int buffered_thread_size : VGT_DEBUG_REG21_buffered_thread_size_SIZE; + unsigned int : 4; + unsigned int out_trigger : VGT_DEBUG_REG21_out_trigger_SIZE; + } vgt_debug_reg21_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg21_t { + unsigned int out_trigger : VGT_DEBUG_REG21_out_trigger_SIZE; + unsigned int : 4; + unsigned int buffered_thread_size : VGT_DEBUG_REG21_buffered_thread_size_SIZE; + unsigned int prim_buffer_empty_mux : VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE; + unsigned int buffered_prim_eop_mux : VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE; + unsigned int insert_null_prim : VGT_DEBUG_REG21_insert_null_prim_SIZE; + unsigned int inserted_null_prim_q : VGT_DEBUG_REG21_inserted_null_prim_q_SIZE; + unsigned int num_new_unique_rel_indx : VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE; + unsigned int new_allocate_q : VGT_DEBUG_REG21_new_allocate_q_SIZE; + unsigned int new_packet_q : VGT_DEBUG_REG21_new_packet_q_SIZE; + unsigned int curr_dealloc_distance_q : VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE; + unsigned int int_vtx_counter_q : VGT_DEBUG_REG21_int_vtx_counter_q_SIZE; + unsigned int curr_slot_in_vtx_vect_q : VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE; + unsigned int alloc_counter_q : VGT_DEBUG_REG21_alloc_counter_q_SIZE; + unsigned int prim_end_of_vtx_vect_flags : VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE; + unsigned int null_terminate_vtx_vector : VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE; + } vgt_debug_reg21_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg21_t f; +} vgt_debug_reg21_u; + + +/* + * VGT_CRC_SQ_DATA struct + */ + +#define VGT_CRC_SQ_DATA_CRC_SIZE 32 + +#define VGT_CRC_SQ_DATA_CRC_SHIFT 0 + +#define VGT_CRC_SQ_DATA_CRC_MASK 0xffffffff + +#define VGT_CRC_SQ_DATA_MASK \ + (VGT_CRC_SQ_DATA_CRC_MASK) + +#define VGT_CRC_SQ_DATA(crc) \ + ((crc << VGT_CRC_SQ_DATA_CRC_SHIFT)) + +#define VGT_CRC_SQ_DATA_GET_CRC(vgt_crc_sq_data) \ + ((vgt_crc_sq_data & VGT_CRC_SQ_DATA_CRC_MASK) >> VGT_CRC_SQ_DATA_CRC_SHIFT) + +#define VGT_CRC_SQ_DATA_SET_CRC(vgt_crc_sq_data_reg, crc) \ + vgt_crc_sq_data_reg = (vgt_crc_sq_data_reg & ~VGT_CRC_SQ_DATA_CRC_MASK) | (crc << VGT_CRC_SQ_DATA_CRC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_crc_sq_data_t { + unsigned int crc : VGT_CRC_SQ_DATA_CRC_SIZE; + } vgt_crc_sq_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_crc_sq_data_t { + unsigned int crc : VGT_CRC_SQ_DATA_CRC_SIZE; + } vgt_crc_sq_data_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_crc_sq_data_t f; +} vgt_crc_sq_data_u; + + +/* + * VGT_CRC_SQ_CTRL struct + */ + +#define VGT_CRC_SQ_CTRL_CRC_SIZE 32 + +#define VGT_CRC_SQ_CTRL_CRC_SHIFT 0 + +#define VGT_CRC_SQ_CTRL_CRC_MASK 0xffffffff + +#define VGT_CRC_SQ_CTRL_MASK \ + (VGT_CRC_SQ_CTRL_CRC_MASK) + +#define VGT_CRC_SQ_CTRL(crc) \ + ((crc << VGT_CRC_SQ_CTRL_CRC_SHIFT)) + +#define VGT_CRC_SQ_CTRL_GET_CRC(vgt_crc_sq_ctrl) \ + ((vgt_crc_sq_ctrl & VGT_CRC_SQ_CTRL_CRC_MASK) >> VGT_CRC_SQ_CTRL_CRC_SHIFT) + +#define VGT_CRC_SQ_CTRL_SET_CRC(vgt_crc_sq_ctrl_reg, crc) \ + vgt_crc_sq_ctrl_reg = (vgt_crc_sq_ctrl_reg & ~VGT_CRC_SQ_CTRL_CRC_MASK) | (crc << VGT_CRC_SQ_CTRL_CRC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_crc_sq_ctrl_t { + unsigned int crc : VGT_CRC_SQ_CTRL_CRC_SIZE; + } vgt_crc_sq_ctrl_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_crc_sq_ctrl_t { + unsigned int crc : VGT_CRC_SQ_CTRL_CRC_SIZE; + } vgt_crc_sq_ctrl_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_crc_sq_ctrl_t f; +} vgt_crc_sq_ctrl_u; + + +/* + * VGT_PERFCOUNTER0_SELECT struct + */ + +#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define VGT_PERFCOUNTER0_SELECT_MASK \ + (VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define VGT_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define VGT_PERFCOUNTER0_SELECT_GET_PERF_SEL(vgt_perfcounter0_select) \ + ((vgt_perfcounter0_select & VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define VGT_PERFCOUNTER0_SELECT_SET_PERF_SEL(vgt_perfcounter0_select_reg, perf_sel) \ + vgt_perfcounter0_select_reg = (vgt_perfcounter0_select_reg & ~VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_select_t { + unsigned int perf_sel : VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } vgt_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } vgt_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter0_select_t f; +} vgt_perfcounter0_select_u; + + +/* + * VGT_PERFCOUNTER1_SELECT struct + */ + +#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8 + +#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0 + +#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff + +#define VGT_PERFCOUNTER1_SELECT_MASK \ + (VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) + +#define VGT_PERFCOUNTER1_SELECT(perf_sel) \ + ((perf_sel << VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)) + +#define VGT_PERFCOUNTER1_SELECT_GET_PERF_SEL(vgt_perfcounter1_select) \ + ((vgt_perfcounter1_select & VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#define VGT_PERFCOUNTER1_SELECT_SET_PERF_SEL(vgt_perfcounter1_select_reg, perf_sel) \ + vgt_perfcounter1_select_reg = (vgt_perfcounter1_select_reg & ~VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_select_t { + unsigned int perf_sel : VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } vgt_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_select_t { + unsigned int : 24; + unsigned int perf_sel : VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + } vgt_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter1_select_t f; +} vgt_perfcounter1_select_u; + + +/* + * VGT_PERFCOUNTER2_SELECT struct + */ + +#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8 + +#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0 + +#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff + +#define VGT_PERFCOUNTER2_SELECT_MASK \ + (VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) + +#define VGT_PERFCOUNTER2_SELECT(perf_sel) \ + ((perf_sel << VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)) + +#define VGT_PERFCOUNTER2_SELECT_GET_PERF_SEL(vgt_perfcounter2_select) \ + ((vgt_perfcounter2_select & VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#define VGT_PERFCOUNTER2_SELECT_SET_PERF_SEL(vgt_perfcounter2_select_reg, perf_sel) \ + vgt_perfcounter2_select_reg = (vgt_perfcounter2_select_reg & ~VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_select_t { + unsigned int perf_sel : VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } vgt_perfcounter2_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_select_t { + unsigned int : 24; + unsigned int perf_sel : VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + } vgt_perfcounter2_select_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter2_select_t f; +} vgt_perfcounter2_select_u; + + +/* + * VGT_PERFCOUNTER3_SELECT struct + */ + +#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8 + +#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0 + +#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff + +#define VGT_PERFCOUNTER3_SELECT_MASK \ + (VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) + +#define VGT_PERFCOUNTER3_SELECT(perf_sel) \ + ((perf_sel << VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)) + +#define VGT_PERFCOUNTER3_SELECT_GET_PERF_SEL(vgt_perfcounter3_select) \ + ((vgt_perfcounter3_select & VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#define VGT_PERFCOUNTER3_SELECT_SET_PERF_SEL(vgt_perfcounter3_select_reg, perf_sel) \ + vgt_perfcounter3_select_reg = (vgt_perfcounter3_select_reg & ~VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_select_t { + unsigned int perf_sel : VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } vgt_perfcounter3_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_select_t { + unsigned int : 24; + unsigned int perf_sel : VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + } vgt_perfcounter3_select_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter3_select_t f; +} vgt_perfcounter3_select_u; + + +/* + * VGT_PERFCOUNTER0_LOW struct + */ + +#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define VGT_PERFCOUNTER0_LOW_MASK \ + (VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER0_LOW_GET_PERF_COUNT(vgt_perfcounter0_low) \ + ((vgt_perfcounter0_low & VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER0_LOW_SET_PERF_COUNT(vgt_perfcounter0_low_reg, perf_count) \ + vgt_perfcounter0_low_reg = (vgt_perfcounter0_low_reg & ~VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_low_t { + unsigned int perf_count : VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_low_t { + unsigned int perf_count : VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter0_low_t f; +} vgt_perfcounter0_low_u; + + +/* + * VGT_PERFCOUNTER1_LOW struct + */ + +#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32 + +#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff + +#define VGT_PERFCOUNTER1_LOW_MASK \ + (VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER1_LOW(perf_count) \ + ((perf_count << VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER1_LOW_GET_PERF_COUNT(vgt_perfcounter1_low) \ + ((vgt_perfcounter1_low & VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER1_LOW_SET_PERF_COUNT(vgt_perfcounter1_low_reg, perf_count) \ + vgt_perfcounter1_low_reg = (vgt_perfcounter1_low_reg & ~VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_low_t { + unsigned int perf_count : VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_low_t { + unsigned int perf_count : VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter1_low_t f; +} vgt_perfcounter1_low_u; + + +/* + * VGT_PERFCOUNTER2_LOW struct + */ + +#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32 + +#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff + +#define VGT_PERFCOUNTER2_LOW_MASK \ + (VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER2_LOW(perf_count) \ + ((perf_count << VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER2_LOW_GET_PERF_COUNT(vgt_perfcounter2_low) \ + ((vgt_perfcounter2_low & VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER2_LOW_SET_PERF_COUNT(vgt_perfcounter2_low_reg, perf_count) \ + vgt_perfcounter2_low_reg = (vgt_perfcounter2_low_reg & ~VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_low_t { + unsigned int perf_count : VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter2_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_low_t { + unsigned int perf_count : VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter2_low_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter2_low_t f; +} vgt_perfcounter2_low_u; + + +/* + * VGT_PERFCOUNTER3_LOW struct + */ + +#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32 + +#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff + +#define VGT_PERFCOUNTER3_LOW_MASK \ + (VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER3_LOW(perf_count) \ + ((perf_count << VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER3_LOW_GET_PERF_COUNT(vgt_perfcounter3_low) \ + ((vgt_perfcounter3_low & VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER3_LOW_SET_PERF_COUNT(vgt_perfcounter3_low_reg, perf_count) \ + vgt_perfcounter3_low_reg = (vgt_perfcounter3_low_reg & ~VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_low_t { + unsigned int perf_count : VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter3_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_low_t { + unsigned int perf_count : VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter3_low_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter3_low_t f; +} vgt_perfcounter3_low_u; + + +/* + * VGT_PERFCOUNTER0_HI struct + */ + +#define VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define VGT_PERFCOUNTER0_HI_MASK \ + (VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER0_HI_GET_PERF_COUNT(vgt_perfcounter0_hi) \ + ((vgt_perfcounter0_hi & VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER0_HI_SET_PERF_COUNT(vgt_perfcounter0_hi_reg, perf_count) \ + vgt_perfcounter0_hi_reg = (vgt_perfcounter0_hi_reg & ~VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_hi_t { + unsigned int perf_count : VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } vgt_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } vgt_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter0_hi_t f; +} vgt_perfcounter0_hi_u; + + +/* + * VGT_PERFCOUNTER1_HI struct + */ + +#define VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16 + +#define VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff + +#define VGT_PERFCOUNTER1_HI_MASK \ + (VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER1_HI(perf_count) \ + ((perf_count << VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER1_HI_GET_PERF_COUNT(vgt_perfcounter1_hi) \ + ((vgt_perfcounter1_hi & VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER1_HI_SET_PERF_COUNT(vgt_perfcounter1_hi_reg, perf_count) \ + vgt_perfcounter1_hi_reg = (vgt_perfcounter1_hi_reg & ~VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_hi_t { + unsigned int perf_count : VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } vgt_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_count : VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + } vgt_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter1_hi_t f; +} vgt_perfcounter1_hi_u; + + +/* + * VGT_PERFCOUNTER2_HI struct + */ + +#define VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16 + +#define VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff + +#define VGT_PERFCOUNTER2_HI_MASK \ + (VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER2_HI(perf_count) \ + ((perf_count << VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER2_HI_GET_PERF_COUNT(vgt_perfcounter2_hi) \ + ((vgt_perfcounter2_hi & VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER2_HI_SET_PERF_COUNT(vgt_perfcounter2_hi_reg, perf_count) \ + vgt_perfcounter2_hi_reg = (vgt_perfcounter2_hi_reg & ~VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_hi_t { + unsigned int perf_count : VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } vgt_perfcounter2_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_hi_t { + unsigned int : 16; + unsigned int perf_count : VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + } vgt_perfcounter2_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter2_hi_t f; +} vgt_perfcounter2_hi_u; + + +/* + * VGT_PERFCOUNTER3_HI struct + */ + +#define VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16 + +#define VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff + +#define VGT_PERFCOUNTER3_HI_MASK \ + (VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER3_HI(perf_count) \ + ((perf_count << VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER3_HI_GET_PERF_COUNT(vgt_perfcounter3_hi) \ + ((vgt_perfcounter3_hi & VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER3_HI_SET_PERF_COUNT(vgt_perfcounter3_hi_reg, perf_count) \ + vgt_perfcounter3_hi_reg = (vgt_perfcounter3_hi_reg & ~VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_hi_t { + unsigned int perf_count : VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } vgt_perfcounter3_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_hi_t { + unsigned int : 16; + unsigned int perf_count : VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + } vgt_perfcounter3_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter3_hi_t f; +} vgt_perfcounter3_hi_u; + + +#endif + + +#if !defined (_SQ_FIDDLE_H) +#define _SQ_FIDDLE_H + +/***************************************************************************************************************** + * + * sq_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * SQ_GPR_MANAGEMENT struct + */ + +#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE 1 +#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE 7 +#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE 7 + +#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT 0 +#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT 4 +#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT 12 + +#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK 0x00000001 +#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK 0x000007f0 +#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK 0x0007f000 + +#define SQ_GPR_MANAGEMENT_MASK \ + (SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK | \ + SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK | \ + SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) + +#define SQ_GPR_MANAGEMENT(reg_dynamic, reg_size_pix, reg_size_vtx) \ + ((reg_dynamic << SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT) | \ + (reg_size_pix << SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT) | \ + (reg_size_vtx << SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT)) + +#define SQ_GPR_MANAGEMENT_GET_REG_DYNAMIC(sq_gpr_management) \ + ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK) >> SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT) +#define SQ_GPR_MANAGEMENT_GET_REG_SIZE_PIX(sq_gpr_management) \ + ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK) >> SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT) +#define SQ_GPR_MANAGEMENT_GET_REG_SIZE_VTX(sq_gpr_management) \ + ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) >> SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT) + +#define SQ_GPR_MANAGEMENT_SET_REG_DYNAMIC(sq_gpr_management_reg, reg_dynamic) \ + sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK) | (reg_dynamic << SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT) +#define SQ_GPR_MANAGEMENT_SET_REG_SIZE_PIX(sq_gpr_management_reg, reg_size_pix) \ + sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK) | (reg_size_pix << SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT) +#define SQ_GPR_MANAGEMENT_SET_REG_SIZE_VTX(sq_gpr_management_reg, reg_size_vtx) \ + sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) | (reg_size_vtx << SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_gpr_management_t { + unsigned int reg_dynamic : SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE; + unsigned int : 3; + unsigned int reg_size_pix : SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE; + unsigned int : 1; + unsigned int reg_size_vtx : SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE; + unsigned int : 13; + } sq_gpr_management_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_gpr_management_t { + unsigned int : 13; + unsigned int reg_size_vtx : SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE; + unsigned int : 1; + unsigned int reg_size_pix : SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE; + unsigned int : 3; + unsigned int reg_dynamic : SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE; + } sq_gpr_management_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_gpr_management_t f; +} sq_gpr_management_u; + + +/* + * SQ_FLOW_CONTROL struct + */ + +#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE 2 +#define SQ_FLOW_CONTROL_ONE_THREAD_SIZE 1 +#define SQ_FLOW_CONTROL_ONE_ALU_SIZE 1 +#define SQ_FLOW_CONTROL_CF_WR_BASE_SIZE 4 +#define SQ_FLOW_CONTROL_NO_PV_PS_SIZE 1 +#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE 1 +#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE 1 +#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE 2 +#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE 1 +#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE 1 +#define SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE 1 +#define SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE 1 +#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE 1 +#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE 1 +#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE 1 + +#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT 0 +#define SQ_FLOW_CONTROL_ONE_THREAD_SHIFT 4 +#define SQ_FLOW_CONTROL_ONE_ALU_SHIFT 8 +#define SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT 12 +#define SQ_FLOW_CONTROL_NO_PV_PS_SHIFT 16 +#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT 17 +#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT 18 +#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT 19 +#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT 21 +#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT 22 +#define SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT 23 +#define SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT 24 +#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT 25 +#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT 26 +#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT 27 + +#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK 0x00000003 +#define SQ_FLOW_CONTROL_ONE_THREAD_MASK 0x00000010 +#define SQ_FLOW_CONTROL_ONE_ALU_MASK 0x00000100 +#define SQ_FLOW_CONTROL_CF_WR_BASE_MASK 0x0000f000 +#define SQ_FLOW_CONTROL_NO_PV_PS_MASK 0x00010000 +#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK 0x00020000 +#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK 0x00040000 +#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK 0x00180000 +#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK 0x00200000 +#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK 0x00400000 +#define SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK 0x00800000 +#define SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK 0x01000000 +#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK 0x02000000 +#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK 0x04000000 +#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK 0x08000000 + +#define SQ_FLOW_CONTROL_MASK \ + (SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK | \ + SQ_FLOW_CONTROL_ONE_THREAD_MASK | \ + SQ_FLOW_CONTROL_ONE_ALU_MASK | \ + SQ_FLOW_CONTROL_CF_WR_BASE_MASK | \ + SQ_FLOW_CONTROL_NO_PV_PS_MASK | \ + SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK | \ + SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK | \ + SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK | \ + SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK | \ + SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK | \ + SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK | \ + SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK | \ + SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK | \ + SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK | \ + SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) + +#define SQ_FLOW_CONTROL(input_arbitration_policy, one_thread, one_alu, cf_wr_base, no_pv_ps, no_loop_exit, no_cexec_optimize, texture_arbitration_policy, vc_arbitration_policy, alu_arbitration_policy, no_arb_eject, no_cfs_eject, pos_exp_priority, no_early_thread_termination, ps_prefetch_color_alloc) \ + ((input_arbitration_policy << SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT) | \ + (one_thread << SQ_FLOW_CONTROL_ONE_THREAD_SHIFT) | \ + (one_alu << SQ_FLOW_CONTROL_ONE_ALU_SHIFT) | \ + (cf_wr_base << SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT) | \ + (no_pv_ps << SQ_FLOW_CONTROL_NO_PV_PS_SHIFT) | \ + (no_loop_exit << SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT) | \ + (no_cexec_optimize << SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT) | \ + (texture_arbitration_policy << SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT) | \ + (vc_arbitration_policy << SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT) | \ + (alu_arbitration_policy << SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT) | \ + (no_arb_eject << SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT) | \ + (no_cfs_eject << SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT) | \ + (pos_exp_priority << SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT) | \ + (no_early_thread_termination << SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT) | \ + (ps_prefetch_color_alloc << SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT)) + +#define SQ_FLOW_CONTROL_GET_INPUT_ARBITRATION_POLICY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_GET_ONE_THREAD(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_ONE_THREAD_MASK) >> SQ_FLOW_CONTROL_ONE_THREAD_SHIFT) +#define SQ_FLOW_CONTROL_GET_ONE_ALU(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_ONE_ALU_MASK) >> SQ_FLOW_CONTROL_ONE_ALU_SHIFT) +#define SQ_FLOW_CONTROL_GET_CF_WR_BASE(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_CF_WR_BASE_MASK) >> SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_PV_PS(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_PV_PS_MASK) >> SQ_FLOW_CONTROL_NO_PV_PS_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_LOOP_EXIT(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK) >> SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_CEXEC_OPTIMIZE(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK) >> SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT) +#define SQ_FLOW_CONTROL_GET_TEXTURE_ARBITRATION_POLICY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_GET_VC_ARBITRATION_POLICY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_GET_ALU_ARBITRATION_POLICY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_ARB_EJECT(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK) >> SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_CFS_EJECT(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK) >> SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT) +#define SQ_FLOW_CONTROL_GET_POS_EXP_PRIORITY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK) >> SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_EARLY_THREAD_TERMINATION(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK) >> SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT) +#define SQ_FLOW_CONTROL_GET_PS_PREFETCH_COLOR_ALLOC(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) >> SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT) + +#define SQ_FLOW_CONTROL_SET_INPUT_ARBITRATION_POLICY(sq_flow_control_reg, input_arbitration_policy) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK) | (input_arbitration_policy << SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_SET_ONE_THREAD(sq_flow_control_reg, one_thread) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ONE_THREAD_MASK) | (one_thread << SQ_FLOW_CONTROL_ONE_THREAD_SHIFT) +#define SQ_FLOW_CONTROL_SET_ONE_ALU(sq_flow_control_reg, one_alu) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ONE_ALU_MASK) | (one_alu << SQ_FLOW_CONTROL_ONE_ALU_SHIFT) +#define SQ_FLOW_CONTROL_SET_CF_WR_BASE(sq_flow_control_reg, cf_wr_base) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_CF_WR_BASE_MASK) | (cf_wr_base << SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_PV_PS(sq_flow_control_reg, no_pv_ps) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_PV_PS_MASK) | (no_pv_ps << SQ_FLOW_CONTROL_NO_PV_PS_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_LOOP_EXIT(sq_flow_control_reg, no_loop_exit) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK) | (no_loop_exit << SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_CEXEC_OPTIMIZE(sq_flow_control_reg, no_cexec_optimize) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK) | (no_cexec_optimize << SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT) +#define SQ_FLOW_CONTROL_SET_TEXTURE_ARBITRATION_POLICY(sq_flow_control_reg, texture_arbitration_policy) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK) | (texture_arbitration_policy << SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_SET_VC_ARBITRATION_POLICY(sq_flow_control_reg, vc_arbitration_policy) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK) | (vc_arbitration_policy << SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_SET_ALU_ARBITRATION_POLICY(sq_flow_control_reg, alu_arbitration_policy) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK) | (alu_arbitration_policy << SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_ARB_EJECT(sq_flow_control_reg, no_arb_eject) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK) | (no_arb_eject << SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_CFS_EJECT(sq_flow_control_reg, no_cfs_eject) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK) | (no_cfs_eject << SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT) +#define SQ_FLOW_CONTROL_SET_POS_EXP_PRIORITY(sq_flow_control_reg, pos_exp_priority) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK) | (pos_exp_priority << SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_EARLY_THREAD_TERMINATION(sq_flow_control_reg, no_early_thread_termination) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK) | (no_early_thread_termination << SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT) +#define SQ_FLOW_CONTROL_SET_PS_PREFETCH_COLOR_ALLOC(sq_flow_control_reg, ps_prefetch_color_alloc) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) | (ps_prefetch_color_alloc << SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_flow_control_t { + unsigned int input_arbitration_policy : SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE; + unsigned int : 2; + unsigned int one_thread : SQ_FLOW_CONTROL_ONE_THREAD_SIZE; + unsigned int : 3; + unsigned int one_alu : SQ_FLOW_CONTROL_ONE_ALU_SIZE; + unsigned int : 3; + unsigned int cf_wr_base : SQ_FLOW_CONTROL_CF_WR_BASE_SIZE; + unsigned int no_pv_ps : SQ_FLOW_CONTROL_NO_PV_PS_SIZE; + unsigned int no_loop_exit : SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE; + unsigned int no_cexec_optimize : SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE; + unsigned int texture_arbitration_policy : SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE; + unsigned int vc_arbitration_policy : SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE; + unsigned int alu_arbitration_policy : SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE; + unsigned int no_arb_eject : SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE; + unsigned int no_cfs_eject : SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE; + unsigned int pos_exp_priority : SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE; + unsigned int no_early_thread_termination : SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE; + unsigned int ps_prefetch_color_alloc : SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE; + unsigned int : 4; + } sq_flow_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_flow_control_t { + unsigned int : 4; + unsigned int ps_prefetch_color_alloc : SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE; + unsigned int no_early_thread_termination : SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE; + unsigned int pos_exp_priority : SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE; + unsigned int no_cfs_eject : SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE; + unsigned int no_arb_eject : SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE; + unsigned int alu_arbitration_policy : SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE; + unsigned int vc_arbitration_policy : SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE; + unsigned int texture_arbitration_policy : SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE; + unsigned int no_cexec_optimize : SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE; + unsigned int no_loop_exit : SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE; + unsigned int no_pv_ps : SQ_FLOW_CONTROL_NO_PV_PS_SIZE; + unsigned int cf_wr_base : SQ_FLOW_CONTROL_CF_WR_BASE_SIZE; + unsigned int : 3; + unsigned int one_alu : SQ_FLOW_CONTROL_ONE_ALU_SIZE; + unsigned int : 3; + unsigned int one_thread : SQ_FLOW_CONTROL_ONE_THREAD_SIZE; + unsigned int : 2; + unsigned int input_arbitration_policy : SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE; + } sq_flow_control_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_flow_control_t f; +} sq_flow_control_u; + + +/* + * SQ_INST_STORE_MANAGMENT struct + */ + +#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE 12 +#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE 12 + +#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT 0 +#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT 16 + +#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK 0x00000fff +#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK 0x0fff0000 + +#define SQ_INST_STORE_MANAGMENT_MASK \ + (SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK | \ + SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) + +#define SQ_INST_STORE_MANAGMENT(inst_base_pix, inst_base_vtx) \ + ((inst_base_pix << SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT) | \ + (inst_base_vtx << SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT)) + +#define SQ_INST_STORE_MANAGMENT_GET_INST_BASE_PIX(sq_inst_store_managment) \ + ((sq_inst_store_managment & SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK) >> SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT) +#define SQ_INST_STORE_MANAGMENT_GET_INST_BASE_VTX(sq_inst_store_managment) \ + ((sq_inst_store_managment & SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) >> SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT) + +#define SQ_INST_STORE_MANAGMENT_SET_INST_BASE_PIX(sq_inst_store_managment_reg, inst_base_pix) \ + sq_inst_store_managment_reg = (sq_inst_store_managment_reg & ~SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK) | (inst_base_pix << SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT) +#define SQ_INST_STORE_MANAGMENT_SET_INST_BASE_VTX(sq_inst_store_managment_reg, inst_base_vtx) \ + sq_inst_store_managment_reg = (sq_inst_store_managment_reg & ~SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) | (inst_base_vtx << SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_inst_store_managment_t { + unsigned int inst_base_pix : SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE; + unsigned int : 4; + unsigned int inst_base_vtx : SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE; + unsigned int : 4; + } sq_inst_store_managment_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_inst_store_managment_t { + unsigned int : 4; + unsigned int inst_base_vtx : SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE; + unsigned int : 4; + unsigned int inst_base_pix : SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE; + } sq_inst_store_managment_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_inst_store_managment_t f; +} sq_inst_store_managment_u; + + +/* + * SQ_RESOURCE_MANAGMENT struct + */ + +#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE 8 +#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE 8 +#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE 9 + +#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT 0 +#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT 8 +#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT 16 + +#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK 0x000000ff +#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK 0x0000ff00 +#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK 0x01ff0000 + +#define SQ_RESOURCE_MANAGMENT_MASK \ + (SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK | \ + SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK | \ + SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) + +#define SQ_RESOURCE_MANAGMENT(vtx_thread_buf_entries, pix_thread_buf_entries, export_buf_entries) \ + ((vtx_thread_buf_entries << SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT) | \ + (pix_thread_buf_entries << SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT) | \ + (export_buf_entries << SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT)) + +#define SQ_RESOURCE_MANAGMENT_GET_VTX_THREAD_BUF_ENTRIES(sq_resource_managment) \ + ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT) +#define SQ_RESOURCE_MANAGMENT_GET_PIX_THREAD_BUF_ENTRIES(sq_resource_managment) \ + ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT) +#define SQ_RESOURCE_MANAGMENT_GET_EXPORT_BUF_ENTRIES(sq_resource_managment) \ + ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT) + +#define SQ_RESOURCE_MANAGMENT_SET_VTX_THREAD_BUF_ENTRIES(sq_resource_managment_reg, vtx_thread_buf_entries) \ + sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK) | (vtx_thread_buf_entries << SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT) +#define SQ_RESOURCE_MANAGMENT_SET_PIX_THREAD_BUF_ENTRIES(sq_resource_managment_reg, pix_thread_buf_entries) \ + sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK) | (pix_thread_buf_entries << SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT) +#define SQ_RESOURCE_MANAGMENT_SET_EXPORT_BUF_ENTRIES(sq_resource_managment_reg, export_buf_entries) \ + sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) | (export_buf_entries << SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_resource_managment_t { + unsigned int vtx_thread_buf_entries : SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE; + unsigned int pix_thread_buf_entries : SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE; + unsigned int export_buf_entries : SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE; + unsigned int : 7; + } sq_resource_managment_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_resource_managment_t { + unsigned int : 7; + unsigned int export_buf_entries : SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE; + unsigned int pix_thread_buf_entries : SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE; + unsigned int vtx_thread_buf_entries : SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE; + } sq_resource_managment_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_resource_managment_t f; +} sq_resource_managment_u; + + +/* + * SQ_EO_RT struct + */ + +#define SQ_EO_RT_EO_CONSTANTS_RT_SIZE 8 +#define SQ_EO_RT_EO_TSTATE_RT_SIZE 8 + +#define SQ_EO_RT_EO_CONSTANTS_RT_SHIFT 0 +#define SQ_EO_RT_EO_TSTATE_RT_SHIFT 16 + +#define SQ_EO_RT_EO_CONSTANTS_RT_MASK 0x000000ff +#define SQ_EO_RT_EO_TSTATE_RT_MASK 0x00ff0000 + +#define SQ_EO_RT_MASK \ + (SQ_EO_RT_EO_CONSTANTS_RT_MASK | \ + SQ_EO_RT_EO_TSTATE_RT_MASK) + +#define SQ_EO_RT(eo_constants_rt, eo_tstate_rt) \ + ((eo_constants_rt << SQ_EO_RT_EO_CONSTANTS_RT_SHIFT) | \ + (eo_tstate_rt << SQ_EO_RT_EO_TSTATE_RT_SHIFT)) + +#define SQ_EO_RT_GET_EO_CONSTANTS_RT(sq_eo_rt) \ + ((sq_eo_rt & SQ_EO_RT_EO_CONSTANTS_RT_MASK) >> SQ_EO_RT_EO_CONSTANTS_RT_SHIFT) +#define SQ_EO_RT_GET_EO_TSTATE_RT(sq_eo_rt) \ + ((sq_eo_rt & SQ_EO_RT_EO_TSTATE_RT_MASK) >> SQ_EO_RT_EO_TSTATE_RT_SHIFT) + +#define SQ_EO_RT_SET_EO_CONSTANTS_RT(sq_eo_rt_reg, eo_constants_rt) \ + sq_eo_rt_reg = (sq_eo_rt_reg & ~SQ_EO_RT_EO_CONSTANTS_RT_MASK) | (eo_constants_rt << SQ_EO_RT_EO_CONSTANTS_RT_SHIFT) +#define SQ_EO_RT_SET_EO_TSTATE_RT(sq_eo_rt_reg, eo_tstate_rt) \ + sq_eo_rt_reg = (sq_eo_rt_reg & ~SQ_EO_RT_EO_TSTATE_RT_MASK) | (eo_tstate_rt << SQ_EO_RT_EO_TSTATE_RT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_eo_rt_t { + unsigned int eo_constants_rt : SQ_EO_RT_EO_CONSTANTS_RT_SIZE; + unsigned int : 8; + unsigned int eo_tstate_rt : SQ_EO_RT_EO_TSTATE_RT_SIZE; + unsigned int : 8; + } sq_eo_rt_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_eo_rt_t { + unsigned int : 8; + unsigned int eo_tstate_rt : SQ_EO_RT_EO_TSTATE_RT_SIZE; + unsigned int : 8; + unsigned int eo_constants_rt : SQ_EO_RT_EO_CONSTANTS_RT_SIZE; + } sq_eo_rt_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_eo_rt_t f; +} sq_eo_rt_u; + + +/* + * SQ_DEBUG_MISC struct + */ + +#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE 11 +#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE 8 +#define SQ_DEBUG_MISC_DB_READ_CTX_SIZE 1 +#define SQ_DEBUG_MISC_RESERVED_SIZE 2 +#define SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE 2 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE 1 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE 1 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE 1 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE 1 + +#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT 0 +#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT 12 +#define SQ_DEBUG_MISC_DB_READ_CTX_SHIFT 20 +#define SQ_DEBUG_MISC_RESERVED_SHIFT 21 +#define SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT 23 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT 25 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT 26 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT 27 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT 28 + +#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK 0x000007ff +#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK 0x000ff000 +#define SQ_DEBUG_MISC_DB_READ_CTX_MASK 0x00100000 +#define SQ_DEBUG_MISC_RESERVED_MASK 0x00600000 +#define SQ_DEBUG_MISC_DB_READ_MEMORY_MASK 0x01800000 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK 0x02000000 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK 0x04000000 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK 0x08000000 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK 0x10000000 + +#define SQ_DEBUG_MISC_MASK \ + (SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK | \ + SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK | \ + SQ_DEBUG_MISC_DB_READ_CTX_MASK | \ + SQ_DEBUG_MISC_RESERVED_MASK | \ + SQ_DEBUG_MISC_DB_READ_MEMORY_MASK | \ + SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK | \ + SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK | \ + SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK | \ + SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) + +#define SQ_DEBUG_MISC(db_alucst_size, db_tstate_size, db_read_ctx, reserved, db_read_memory, db_wen_memory_0, db_wen_memory_1, db_wen_memory_2, db_wen_memory_3) \ + ((db_alucst_size << SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT) | \ + (db_tstate_size << SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT) | \ + (db_read_ctx << SQ_DEBUG_MISC_DB_READ_CTX_SHIFT) | \ + (reserved << SQ_DEBUG_MISC_RESERVED_SHIFT) | \ + (db_read_memory << SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT) | \ + (db_wen_memory_0 << SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT) | \ + (db_wen_memory_1 << SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT) | \ + (db_wen_memory_2 << SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT) | \ + (db_wen_memory_3 << SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT)) + +#define SQ_DEBUG_MISC_GET_DB_ALUCST_SIZE(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK) >> SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_TSTATE_SIZE(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK) >> SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_READ_CTX(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_READ_CTX_MASK) >> SQ_DEBUG_MISC_DB_READ_CTX_SHIFT) +#define SQ_DEBUG_MISC_GET_RESERVED(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_RESERVED_MASK) >> SQ_DEBUG_MISC_RESERVED_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_READ_MEMORY(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_READ_MEMORY_MASK) >> SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_0(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_1(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_2(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_3(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT) + +#define SQ_DEBUG_MISC_SET_DB_ALUCST_SIZE(sq_debug_misc_reg, db_alucst_size) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK) | (db_alucst_size << SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_TSTATE_SIZE(sq_debug_misc_reg, db_tstate_size) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK) | (db_tstate_size << SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_READ_CTX(sq_debug_misc_reg, db_read_ctx) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_READ_CTX_MASK) | (db_read_ctx << SQ_DEBUG_MISC_DB_READ_CTX_SHIFT) +#define SQ_DEBUG_MISC_SET_RESERVED(sq_debug_misc_reg, reserved) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_RESERVED_MASK) | (reserved << SQ_DEBUG_MISC_RESERVED_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_READ_MEMORY(sq_debug_misc_reg, db_read_memory) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_READ_MEMORY_MASK) | (db_read_memory << SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_0(sq_debug_misc_reg, db_wen_memory_0) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK) | (db_wen_memory_0 << SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_1(sq_debug_misc_reg, db_wen_memory_1) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK) | (db_wen_memory_1 << SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_2(sq_debug_misc_reg, db_wen_memory_2) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK) | (db_wen_memory_2 << SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_3(sq_debug_misc_reg, db_wen_memory_3) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) | (db_wen_memory_3 << SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_misc_t { + unsigned int db_alucst_size : SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE; + unsigned int : 1; + unsigned int db_tstate_size : SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE; + unsigned int db_read_ctx : SQ_DEBUG_MISC_DB_READ_CTX_SIZE; + unsigned int reserved : SQ_DEBUG_MISC_RESERVED_SIZE; + unsigned int db_read_memory : SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE; + unsigned int db_wen_memory_0 : SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE; + unsigned int db_wen_memory_1 : SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE; + unsigned int db_wen_memory_2 : SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE; + unsigned int db_wen_memory_3 : SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE; + unsigned int : 3; + } sq_debug_misc_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_misc_t { + unsigned int : 3; + unsigned int db_wen_memory_3 : SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE; + unsigned int db_wen_memory_2 : SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE; + unsigned int db_wen_memory_1 : SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE; + unsigned int db_wen_memory_0 : SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE; + unsigned int db_read_memory : SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE; + unsigned int reserved : SQ_DEBUG_MISC_RESERVED_SIZE; + unsigned int db_read_ctx : SQ_DEBUG_MISC_DB_READ_CTX_SIZE; + unsigned int db_tstate_size : SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE; + unsigned int : 1; + unsigned int db_alucst_size : SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE; + } sq_debug_misc_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_misc_t f; +} sq_debug_misc_u; + + +/* + * SQ_ACTIVITY_METER_CNTL struct + */ + +#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE 8 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE 8 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE 8 +#define SQ_ACTIVITY_METER_CNTL_SPARE_SIZE 8 + +#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT 0 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT 8 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT 16 +#define SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT 24 + +#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK 0x000000ff +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK 0x0000ff00 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK 0x00ff0000 +#define SQ_ACTIVITY_METER_CNTL_SPARE_MASK 0xff000000 + +#define SQ_ACTIVITY_METER_CNTL_MASK \ + (SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK | \ + SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK | \ + SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK | \ + SQ_ACTIVITY_METER_CNTL_SPARE_MASK) + +#define SQ_ACTIVITY_METER_CNTL(timebase, threshold_low, threshold_high, spare) \ + ((timebase << SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT) | \ + (threshold_low << SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT) | \ + (threshold_high << SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT) | \ + (spare << SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT)) + +#define SQ_ACTIVITY_METER_CNTL_GET_TIMEBASE(sq_activity_meter_cntl) \ + ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK) >> SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_GET_THRESHOLD_LOW(sq_activity_meter_cntl) \ + ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK) >> SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_GET_THRESHOLD_HIGH(sq_activity_meter_cntl) \ + ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK) >> SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_GET_SPARE(sq_activity_meter_cntl) \ + ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_SPARE_MASK) >> SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT) + +#define SQ_ACTIVITY_METER_CNTL_SET_TIMEBASE(sq_activity_meter_cntl_reg, timebase) \ + sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK) | (timebase << SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_SET_THRESHOLD_LOW(sq_activity_meter_cntl_reg, threshold_low) \ + sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK) | (threshold_low << SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_SET_THRESHOLD_HIGH(sq_activity_meter_cntl_reg, threshold_high) \ + sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK) | (threshold_high << SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_SET_SPARE(sq_activity_meter_cntl_reg, spare) \ + sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_SPARE_MASK) | (spare << SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_activity_meter_cntl_t { + unsigned int timebase : SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE; + unsigned int threshold_low : SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE; + unsigned int threshold_high : SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE; + unsigned int spare : SQ_ACTIVITY_METER_CNTL_SPARE_SIZE; + } sq_activity_meter_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_activity_meter_cntl_t { + unsigned int spare : SQ_ACTIVITY_METER_CNTL_SPARE_SIZE; + unsigned int threshold_high : SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE; + unsigned int threshold_low : SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE; + unsigned int timebase : SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE; + } sq_activity_meter_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_activity_meter_cntl_t f; +} sq_activity_meter_cntl_u; + + +/* + * SQ_ACTIVITY_METER_STATUS struct + */ + +#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE 8 + +#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT 0 + +#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK 0x000000ff + +#define SQ_ACTIVITY_METER_STATUS_MASK \ + (SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) + +#define SQ_ACTIVITY_METER_STATUS(percent_busy) \ + ((percent_busy << SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT)) + +#define SQ_ACTIVITY_METER_STATUS_GET_PERCENT_BUSY(sq_activity_meter_status) \ + ((sq_activity_meter_status & SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) >> SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT) + +#define SQ_ACTIVITY_METER_STATUS_SET_PERCENT_BUSY(sq_activity_meter_status_reg, percent_busy) \ + sq_activity_meter_status_reg = (sq_activity_meter_status_reg & ~SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) | (percent_busy << SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_activity_meter_status_t { + unsigned int percent_busy : SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE; + unsigned int : 24; + } sq_activity_meter_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_activity_meter_status_t { + unsigned int : 24; + unsigned int percent_busy : SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE; + } sq_activity_meter_status_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_activity_meter_status_t f; +} sq_activity_meter_status_u; + + +/* + * SQ_INPUT_ARB_PRIORITY struct + */ + +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE 3 +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE 1 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE 3 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE 1 +#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE 10 + +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT 0 +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT 3 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT 4 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT 7 +#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT 8 + +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK 0x00000007 +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK 0x00000008 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK 0x00000070 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK 0x00000080 +#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK 0x0003ff00 + +#define SQ_INPUT_ARB_PRIORITY_MASK \ + (SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK | \ + SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK | \ + SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK | \ + SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK | \ + SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) + +#define SQ_INPUT_ARB_PRIORITY(pc_avail_weight, pc_avail_sign, sx_avail_weight, sx_avail_sign, threshold) \ + ((pc_avail_weight << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) | \ + (pc_avail_sign << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) | \ + (sx_avail_weight << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) | \ + (sx_avail_sign << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) | \ + (threshold << SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT)) + +#define SQ_INPUT_ARB_PRIORITY_GET_PC_AVAIL_WEIGHT(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) >> SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_GET_PC_AVAIL_SIGN(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) >> SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_GET_SX_AVAIL_WEIGHT(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) >> SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_GET_SX_AVAIL_SIGN(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) >> SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_GET_THRESHOLD(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) >> SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT) + +#define SQ_INPUT_ARB_PRIORITY_SET_PC_AVAIL_WEIGHT(sq_input_arb_priority_reg, pc_avail_weight) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) | (pc_avail_weight << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_SET_PC_AVAIL_SIGN(sq_input_arb_priority_reg, pc_avail_sign) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) | (pc_avail_sign << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_SET_SX_AVAIL_WEIGHT(sq_input_arb_priority_reg, sx_avail_weight) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) | (sx_avail_weight << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_SET_SX_AVAIL_SIGN(sq_input_arb_priority_reg, sx_avail_sign) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) | (sx_avail_sign << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_SET_THRESHOLD(sq_input_arb_priority_reg, threshold) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) | (threshold << SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_input_arb_priority_t { + unsigned int pc_avail_weight : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE; + unsigned int pc_avail_sign : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE; + unsigned int sx_avail_weight : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE; + unsigned int sx_avail_sign : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE; + unsigned int threshold : SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE; + unsigned int : 14; + } sq_input_arb_priority_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_input_arb_priority_t { + unsigned int : 14; + unsigned int threshold : SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE; + unsigned int sx_avail_sign : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE; + unsigned int sx_avail_weight : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE; + unsigned int pc_avail_sign : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE; + unsigned int pc_avail_weight : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE; + } sq_input_arb_priority_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_input_arb_priority_t f; +} sq_input_arb_priority_u; + + +/* + * SQ_THREAD_ARB_PRIORITY struct + */ + +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE 3 +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE 1 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE 3 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE 1 +#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE 10 +#define SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE 2 +#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE 1 +#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE 1 +#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE 1 + +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT 0 +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT 3 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT 4 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT 7 +#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT 8 +#define SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT 18 +#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT 20 +#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT 21 +#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT 22 + +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK 0x00000007 +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK 0x00000008 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK 0x00000070 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK 0x00000080 +#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK 0x0003ff00 +#define SQ_THREAD_ARB_PRIORITY_RESERVED_MASK 0x000c0000 +#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK 0x00100000 +#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK 0x00200000 +#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK 0x00400000 + +#define SQ_THREAD_ARB_PRIORITY_MASK \ + (SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK | \ + SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK | \ + SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK | \ + SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK | \ + SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK | \ + SQ_THREAD_ARB_PRIORITY_RESERVED_MASK | \ + SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK | \ + SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK | \ + SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) + +#define SQ_THREAD_ARB_PRIORITY(pc_avail_weight, pc_avail_sign, sx_avail_weight, sx_avail_sign, threshold, reserved, vs_prioritize_serial, ps_prioritize_serial, use_serial_count_threshold) \ + ((pc_avail_weight << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) | \ + (pc_avail_sign << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) | \ + (sx_avail_weight << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) | \ + (sx_avail_sign << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) | \ + (threshold << SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT) | \ + (reserved << SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT) | \ + (vs_prioritize_serial << SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT) | \ + (ps_prioritize_serial << SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT) | \ + (use_serial_count_threshold << SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT)) + +#define SQ_THREAD_ARB_PRIORITY_GET_PC_AVAIL_WEIGHT(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) >> SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_PC_AVAIL_SIGN(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) >> SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_SX_AVAIL_WEIGHT(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) >> SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_SX_AVAIL_SIGN(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) >> SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_THRESHOLD(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK) >> SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_RESERVED(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_RESERVED_MASK) >> SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_VS_PRIORITIZE_SERIAL(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK) >> SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_PS_PRIORITIZE_SERIAL(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK) >> SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_USE_SERIAL_COUNT_THRESHOLD(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) >> SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT) + +#define SQ_THREAD_ARB_PRIORITY_SET_PC_AVAIL_WEIGHT(sq_thread_arb_priority_reg, pc_avail_weight) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) | (pc_avail_weight << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_PC_AVAIL_SIGN(sq_thread_arb_priority_reg, pc_avail_sign) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) | (pc_avail_sign << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_SX_AVAIL_WEIGHT(sq_thread_arb_priority_reg, sx_avail_weight) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) | (sx_avail_weight << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_SX_AVAIL_SIGN(sq_thread_arb_priority_reg, sx_avail_sign) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) | (sx_avail_sign << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_THRESHOLD(sq_thread_arb_priority_reg, threshold) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK) | (threshold << SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_RESERVED(sq_thread_arb_priority_reg, reserved) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_RESERVED_MASK) | (reserved << SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_VS_PRIORITIZE_SERIAL(sq_thread_arb_priority_reg, vs_prioritize_serial) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK) | (vs_prioritize_serial << SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_PS_PRIORITIZE_SERIAL(sq_thread_arb_priority_reg, ps_prioritize_serial) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK) | (ps_prioritize_serial << SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_USE_SERIAL_COUNT_THRESHOLD(sq_thread_arb_priority_reg, use_serial_count_threshold) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) | (use_serial_count_threshold << SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_thread_arb_priority_t { + unsigned int pc_avail_weight : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE; + unsigned int pc_avail_sign : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE; + unsigned int sx_avail_weight : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE; + unsigned int sx_avail_sign : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE; + unsigned int threshold : SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE; + unsigned int reserved : SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE; + unsigned int vs_prioritize_serial : SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE; + unsigned int ps_prioritize_serial : SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE; + unsigned int use_serial_count_threshold : SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE; + unsigned int : 9; + } sq_thread_arb_priority_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_thread_arb_priority_t { + unsigned int : 9; + unsigned int use_serial_count_threshold : SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE; + unsigned int ps_prioritize_serial : SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE; + unsigned int vs_prioritize_serial : SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE; + unsigned int reserved : SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE; + unsigned int threshold : SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE; + unsigned int sx_avail_sign : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE; + unsigned int sx_avail_weight : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE; + unsigned int pc_avail_sign : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE; + unsigned int pc_avail_weight : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE; + } sq_thread_arb_priority_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_thread_arb_priority_t f; +} sq_thread_arb_priority_u; + + +/* + * SQ_VS_WATCHDOG_TIMER struct + */ + +#define SQ_VS_WATCHDOG_TIMER_ENABLE_SIZE 1 +#define SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE 31 + +#define SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT 0 +#define SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT 1 + +#define SQ_VS_WATCHDOG_TIMER_ENABLE_MASK 0x00000001 +#define SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK 0xfffffffe + +#define SQ_VS_WATCHDOG_TIMER_MASK \ + (SQ_VS_WATCHDOG_TIMER_ENABLE_MASK | \ + SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) + +#define SQ_VS_WATCHDOG_TIMER(enable, timeout_count) \ + ((enable << SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT) | \ + (timeout_count << SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT)) + +#define SQ_VS_WATCHDOG_TIMER_GET_ENABLE(sq_vs_watchdog_timer) \ + ((sq_vs_watchdog_timer & SQ_VS_WATCHDOG_TIMER_ENABLE_MASK) >> SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT) +#define SQ_VS_WATCHDOG_TIMER_GET_TIMEOUT_COUNT(sq_vs_watchdog_timer) \ + ((sq_vs_watchdog_timer & SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) >> SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT) + +#define SQ_VS_WATCHDOG_TIMER_SET_ENABLE(sq_vs_watchdog_timer_reg, enable) \ + sq_vs_watchdog_timer_reg = (sq_vs_watchdog_timer_reg & ~SQ_VS_WATCHDOG_TIMER_ENABLE_MASK) | (enable << SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT) +#define SQ_VS_WATCHDOG_TIMER_SET_TIMEOUT_COUNT(sq_vs_watchdog_timer_reg, timeout_count) \ + sq_vs_watchdog_timer_reg = (sq_vs_watchdog_timer_reg & ~SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) | (timeout_count << SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_vs_watchdog_timer_t { + unsigned int enable : SQ_VS_WATCHDOG_TIMER_ENABLE_SIZE; + unsigned int timeout_count : SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE; + } sq_vs_watchdog_timer_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_vs_watchdog_timer_t { + unsigned int timeout_count : SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE; + unsigned int enable : SQ_VS_WATCHDOG_TIMER_ENABLE_SIZE; + } sq_vs_watchdog_timer_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_vs_watchdog_timer_t f; +} sq_vs_watchdog_timer_u; + + +/* + * SQ_PS_WATCHDOG_TIMER struct + */ + +#define SQ_PS_WATCHDOG_TIMER_ENABLE_SIZE 1 +#define SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE 31 + +#define SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT 0 +#define SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT 1 + +#define SQ_PS_WATCHDOG_TIMER_ENABLE_MASK 0x00000001 +#define SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK 0xfffffffe + +#define SQ_PS_WATCHDOG_TIMER_MASK \ + (SQ_PS_WATCHDOG_TIMER_ENABLE_MASK | \ + SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) + +#define SQ_PS_WATCHDOG_TIMER(enable, timeout_count) \ + ((enable << SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT) | \ + (timeout_count << SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT)) + +#define SQ_PS_WATCHDOG_TIMER_GET_ENABLE(sq_ps_watchdog_timer) \ + ((sq_ps_watchdog_timer & SQ_PS_WATCHDOG_TIMER_ENABLE_MASK) >> SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT) +#define SQ_PS_WATCHDOG_TIMER_GET_TIMEOUT_COUNT(sq_ps_watchdog_timer) \ + ((sq_ps_watchdog_timer & SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) >> SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT) + +#define SQ_PS_WATCHDOG_TIMER_SET_ENABLE(sq_ps_watchdog_timer_reg, enable) \ + sq_ps_watchdog_timer_reg = (sq_ps_watchdog_timer_reg & ~SQ_PS_WATCHDOG_TIMER_ENABLE_MASK) | (enable << SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT) +#define SQ_PS_WATCHDOG_TIMER_SET_TIMEOUT_COUNT(sq_ps_watchdog_timer_reg, timeout_count) \ + sq_ps_watchdog_timer_reg = (sq_ps_watchdog_timer_reg & ~SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) | (timeout_count << SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_ps_watchdog_timer_t { + unsigned int enable : SQ_PS_WATCHDOG_TIMER_ENABLE_SIZE; + unsigned int timeout_count : SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE; + } sq_ps_watchdog_timer_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_ps_watchdog_timer_t { + unsigned int timeout_count : SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE; + unsigned int enable : SQ_PS_WATCHDOG_TIMER_ENABLE_SIZE; + } sq_ps_watchdog_timer_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_ps_watchdog_timer_t f; +} sq_ps_watchdog_timer_u; + + +/* + * SQ_INT_CNTL struct + */ + +#define SQ_INT_CNTL_PS_WATCHDOG_MASK_SIZE 1 +#define SQ_INT_CNTL_VS_WATCHDOG_MASK_SIZE 1 + +#define SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT 0 +#define SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT 1 + +#define SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK 0x00000001 +#define SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK 0x00000002 + +#define SQ_INT_CNTL_MASK \ + (SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK | \ + SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK) + +#define SQ_INT_CNTL(ps_watchdog_mask, vs_watchdog_mask) \ + ((ps_watchdog_mask << SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT) | \ + (vs_watchdog_mask << SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT)) + +#define SQ_INT_CNTL_GET_PS_WATCHDOG_MASK(sq_int_cntl) \ + ((sq_int_cntl & SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK) >> SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT) +#define SQ_INT_CNTL_GET_VS_WATCHDOG_MASK(sq_int_cntl) \ + ((sq_int_cntl & SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK) >> SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT) + +#define SQ_INT_CNTL_SET_PS_WATCHDOG_MASK(sq_int_cntl_reg, ps_watchdog_mask) \ + sq_int_cntl_reg = (sq_int_cntl_reg & ~SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK) | (ps_watchdog_mask << SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT) +#define SQ_INT_CNTL_SET_VS_WATCHDOG_MASK(sq_int_cntl_reg, vs_watchdog_mask) \ + sq_int_cntl_reg = (sq_int_cntl_reg & ~SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK) | (vs_watchdog_mask << SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_int_cntl_t { + unsigned int ps_watchdog_mask : SQ_INT_CNTL_PS_WATCHDOG_MASK_SIZE; + unsigned int vs_watchdog_mask : SQ_INT_CNTL_VS_WATCHDOG_MASK_SIZE; + unsigned int : 30; + } sq_int_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_int_cntl_t { + unsigned int : 30; + unsigned int vs_watchdog_mask : SQ_INT_CNTL_VS_WATCHDOG_MASK_SIZE; + unsigned int ps_watchdog_mask : SQ_INT_CNTL_PS_WATCHDOG_MASK_SIZE; + } sq_int_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_int_cntl_t f; +} sq_int_cntl_u; + + +/* + * SQ_INT_STATUS struct + */ + +#define SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SIZE 1 +#define SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SIZE 1 + +#define SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT 0 +#define SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT 1 + +#define SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK 0x00000001 +#define SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK 0x00000002 + +#define SQ_INT_STATUS_MASK \ + (SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK | \ + SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK) + +#define SQ_INT_STATUS(ps_watchdog_timeout, vs_watchdog_timeout) \ + ((ps_watchdog_timeout << SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT) | \ + (vs_watchdog_timeout << SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT)) + +#define SQ_INT_STATUS_GET_PS_WATCHDOG_TIMEOUT(sq_int_status) \ + ((sq_int_status & SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK) >> SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT) +#define SQ_INT_STATUS_GET_VS_WATCHDOG_TIMEOUT(sq_int_status) \ + ((sq_int_status & SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK) >> SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT) + +#define SQ_INT_STATUS_SET_PS_WATCHDOG_TIMEOUT(sq_int_status_reg, ps_watchdog_timeout) \ + sq_int_status_reg = (sq_int_status_reg & ~SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK) | (ps_watchdog_timeout << SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT) +#define SQ_INT_STATUS_SET_VS_WATCHDOG_TIMEOUT(sq_int_status_reg, vs_watchdog_timeout) \ + sq_int_status_reg = (sq_int_status_reg & ~SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK) | (vs_watchdog_timeout << SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_int_status_t { + unsigned int ps_watchdog_timeout : SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SIZE; + unsigned int vs_watchdog_timeout : SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SIZE; + unsigned int : 30; + } sq_int_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_int_status_t { + unsigned int : 30; + unsigned int vs_watchdog_timeout : SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SIZE; + unsigned int ps_watchdog_timeout : SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SIZE; + } sq_int_status_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_int_status_t f; +} sq_int_status_u; + + +/* + * SQ_INT_ACK struct + */ + +#define SQ_INT_ACK_PS_WATCHDOG_ACK_SIZE 1 +#define SQ_INT_ACK_VS_WATCHDOG_ACK_SIZE 1 + +#define SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT 0 +#define SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT 1 + +#define SQ_INT_ACK_PS_WATCHDOG_ACK_MASK 0x00000001 +#define SQ_INT_ACK_VS_WATCHDOG_ACK_MASK 0x00000002 + +#define SQ_INT_ACK_MASK \ + (SQ_INT_ACK_PS_WATCHDOG_ACK_MASK | \ + SQ_INT_ACK_VS_WATCHDOG_ACK_MASK) + +#define SQ_INT_ACK(ps_watchdog_ack, vs_watchdog_ack) \ + ((ps_watchdog_ack << SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT) | \ + (vs_watchdog_ack << SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT)) + +#define SQ_INT_ACK_GET_PS_WATCHDOG_ACK(sq_int_ack) \ + ((sq_int_ack & SQ_INT_ACK_PS_WATCHDOG_ACK_MASK) >> SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT) +#define SQ_INT_ACK_GET_VS_WATCHDOG_ACK(sq_int_ack) \ + ((sq_int_ack & SQ_INT_ACK_VS_WATCHDOG_ACK_MASK) >> SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT) + +#define SQ_INT_ACK_SET_PS_WATCHDOG_ACK(sq_int_ack_reg, ps_watchdog_ack) \ + sq_int_ack_reg = (sq_int_ack_reg & ~SQ_INT_ACK_PS_WATCHDOG_ACK_MASK) | (ps_watchdog_ack << SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT) +#define SQ_INT_ACK_SET_VS_WATCHDOG_ACK(sq_int_ack_reg, vs_watchdog_ack) \ + sq_int_ack_reg = (sq_int_ack_reg & ~SQ_INT_ACK_VS_WATCHDOG_ACK_MASK) | (vs_watchdog_ack << SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_int_ack_t { + unsigned int ps_watchdog_ack : SQ_INT_ACK_PS_WATCHDOG_ACK_SIZE; + unsigned int vs_watchdog_ack : SQ_INT_ACK_VS_WATCHDOG_ACK_SIZE; + unsigned int : 30; + } sq_int_ack_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_int_ack_t { + unsigned int : 30; + unsigned int vs_watchdog_ack : SQ_INT_ACK_VS_WATCHDOG_ACK_SIZE; + unsigned int ps_watchdog_ack : SQ_INT_ACK_PS_WATCHDOG_ACK_SIZE; + } sq_int_ack_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_int_ack_t f; +} sq_int_ack_u; + + +/* + * SQ_DEBUG_INPUT_FSM struct + */ + +#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE 3 +#define SQ_DEBUG_INPUT_FSM_RESERVED_SIZE 1 +#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE 4 +#define SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE 3 +#define SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE 1 +#define SQ_DEBUG_INPUT_FSM_PC_AS_SIZE 3 +#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE 5 +#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE 8 + +#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT 0 +#define SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT 3 +#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT 4 +#define SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT 8 +#define SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT 11 +#define SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT 12 +#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT 15 +#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT 20 + +#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK 0x00000007 +#define SQ_DEBUG_INPUT_FSM_RESERVED_MASK 0x00000008 +#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK 0x000000f0 +#define SQ_DEBUG_INPUT_FSM_PC_PISM_MASK 0x00000700 +#define SQ_DEBUG_INPUT_FSM_RESERVED1_MASK 0x00000800 +#define SQ_DEBUG_INPUT_FSM_PC_AS_MASK 0x00007000 +#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK 0x000f8000 +#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK 0x0ff00000 + +#define SQ_DEBUG_INPUT_FSM_MASK \ + (SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK | \ + SQ_DEBUG_INPUT_FSM_RESERVED_MASK | \ + SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK | \ + SQ_DEBUG_INPUT_FSM_PC_PISM_MASK | \ + SQ_DEBUG_INPUT_FSM_RESERVED1_MASK | \ + SQ_DEBUG_INPUT_FSM_PC_AS_MASK | \ + SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK | \ + SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) + +#define SQ_DEBUG_INPUT_FSM(vc_vsr_ld, reserved, vc_gpr_ld, pc_pism, reserved1, pc_as, pc_interp_cnt, pc_gpr_size) \ + ((vc_vsr_ld << SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT) | \ + (reserved << SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT) | \ + (vc_gpr_ld << SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT) | \ + (pc_pism << SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT) | \ + (reserved1 << SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT) | \ + (pc_as << SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT) | \ + (pc_interp_cnt << SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT) | \ + (pc_gpr_size << SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT)) + +#define SQ_DEBUG_INPUT_FSM_GET_VC_VSR_LD(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK) >> SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_RESERVED(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_RESERVED_MASK) >> SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_VC_GPR_LD(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK) >> SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_PC_PISM(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_PISM_MASK) >> SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_RESERVED1(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_RESERVED1_MASK) >> SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_PC_AS(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_AS_MASK) >> SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_PC_INTERP_CNT(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK) >> SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_PC_GPR_SIZE(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) >> SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT) + +#define SQ_DEBUG_INPUT_FSM_SET_VC_VSR_LD(sq_debug_input_fsm_reg, vc_vsr_ld) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK) | (vc_vsr_ld << SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_RESERVED(sq_debug_input_fsm_reg, reserved) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_RESERVED_MASK) | (reserved << SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_VC_GPR_LD(sq_debug_input_fsm_reg, vc_gpr_ld) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK) | (vc_gpr_ld << SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_PC_PISM(sq_debug_input_fsm_reg, pc_pism) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_PISM_MASK) | (pc_pism << SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_RESERVED1(sq_debug_input_fsm_reg, reserved1) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_PC_AS(sq_debug_input_fsm_reg, pc_as) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_AS_MASK) | (pc_as << SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_PC_INTERP_CNT(sq_debug_input_fsm_reg, pc_interp_cnt) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK) | (pc_interp_cnt << SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_PC_GPR_SIZE(sq_debug_input_fsm_reg, pc_gpr_size) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) | (pc_gpr_size << SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_input_fsm_t { + unsigned int vc_vsr_ld : SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE; + unsigned int reserved : SQ_DEBUG_INPUT_FSM_RESERVED_SIZE; + unsigned int vc_gpr_ld : SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE; + unsigned int pc_pism : SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE; + unsigned int reserved1 : SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE; + unsigned int pc_as : SQ_DEBUG_INPUT_FSM_PC_AS_SIZE; + unsigned int pc_interp_cnt : SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE; + unsigned int pc_gpr_size : SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE; + unsigned int : 4; + } sq_debug_input_fsm_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_input_fsm_t { + unsigned int : 4; + unsigned int pc_gpr_size : SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE; + unsigned int pc_interp_cnt : SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE; + unsigned int pc_as : SQ_DEBUG_INPUT_FSM_PC_AS_SIZE; + unsigned int reserved1 : SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE; + unsigned int pc_pism : SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE; + unsigned int vc_gpr_ld : SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE; + unsigned int reserved : SQ_DEBUG_INPUT_FSM_RESERVED_SIZE; + unsigned int vc_vsr_ld : SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE; + } sq_debug_input_fsm_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_input_fsm_t f; +} sq_debug_input_fsm_u; + + +/* + * SQ_DEBUG_CONST_MGR_FSM struct + */ + +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE 5 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE 3 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE 5 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE 3 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE 2 +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE 2 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE 1 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE 1 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE 1 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE 1 + +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT 0 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT 5 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT 8 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT 13 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT 16 +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT 18 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT 20 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT 21 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT 22 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT 23 + +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK 0x0000001f +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK 0x000000e0 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK 0x00001f00 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK 0x0000e000 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK 0x00030000 +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK 0x000c0000 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK 0x00100000 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK 0x00200000 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK 0x00400000 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK 0x00800000 + +#define SQ_DEBUG_CONST_MGR_FSM_MASK \ + (SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) + +#define SQ_DEBUG_CONST_MGR_FSM(tex_const_event_state, reserved1, alu_const_event_state, reserved2, alu_const_cntx_valid, tex_const_cntx_valid, cntx0_vtx_event_done, cntx0_pix_event_done, cntx1_vtx_event_done, cntx1_pix_event_done) \ + ((tex_const_event_state << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT) | \ + (reserved1 << SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT) | \ + (alu_const_event_state << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT) | \ + (reserved2 << SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT) | \ + (alu_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT) | \ + (tex_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT) | \ + (cntx0_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT) | \ + (cntx0_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT) | \ + (cntx1_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT) | \ + (cntx1_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT)) + +#define SQ_DEBUG_CONST_MGR_FSM_GET_TEX_CONST_EVENT_STATE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_RESERVED1(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK) >> SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_ALU_CONST_EVENT_STATE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_RESERVED2(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK) >> SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_ALU_CONST_CNTX_VALID(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK) >> SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_TEX_CONST_CNTX_VALID(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK) >> SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX0_VTX_EVENT_DONE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX0_PIX_EVENT_DONE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX1_VTX_EVENT_DONE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX1_PIX_EVENT_DONE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT) + +#define SQ_DEBUG_CONST_MGR_FSM_SET_TEX_CONST_EVENT_STATE(sq_debug_const_mgr_fsm_reg, tex_const_event_state) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK) | (tex_const_event_state << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_RESERVED1(sq_debug_const_mgr_fsm_reg, reserved1) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_ALU_CONST_EVENT_STATE(sq_debug_const_mgr_fsm_reg, alu_const_event_state) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK) | (alu_const_event_state << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_RESERVED2(sq_debug_const_mgr_fsm_reg, reserved2) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_ALU_CONST_CNTX_VALID(sq_debug_const_mgr_fsm_reg, alu_const_cntx_valid) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK) | (alu_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_TEX_CONST_CNTX_VALID(sq_debug_const_mgr_fsm_reg, tex_const_cntx_valid) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK) | (tex_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX0_VTX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx0_vtx_event_done) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK) | (cntx0_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX0_PIX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx0_pix_event_done) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK) | (cntx0_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX1_VTX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx1_vtx_event_done) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK) | (cntx1_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX1_PIX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx1_pix_event_done) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) | (cntx1_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_const_mgr_fsm_t { + unsigned int tex_const_event_state : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE; + unsigned int reserved1 : SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE; + unsigned int alu_const_event_state : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE; + unsigned int reserved2 : SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE; + unsigned int alu_const_cntx_valid : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE; + unsigned int tex_const_cntx_valid : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE; + unsigned int cntx0_vtx_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE; + unsigned int cntx0_pix_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE; + unsigned int cntx1_vtx_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE; + unsigned int cntx1_pix_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE; + unsigned int : 8; + } sq_debug_const_mgr_fsm_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_const_mgr_fsm_t { + unsigned int : 8; + unsigned int cntx1_pix_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE; + unsigned int cntx1_vtx_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE; + unsigned int cntx0_pix_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE; + unsigned int cntx0_vtx_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE; + unsigned int tex_const_cntx_valid : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE; + unsigned int alu_const_cntx_valid : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE; + unsigned int reserved2 : SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE; + unsigned int alu_const_event_state : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE; + unsigned int reserved1 : SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE; + unsigned int tex_const_event_state : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE; + } sq_debug_const_mgr_fsm_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_const_mgr_fsm_t f; +} sq_debug_const_mgr_fsm_u; + + +/* + * SQ_DEBUG_TP_FSM struct + */ + +#define SQ_DEBUG_TP_FSM_EX_TP_SIZE 3 +#define SQ_DEBUG_TP_FSM_RESERVED0_SIZE 1 +#define SQ_DEBUG_TP_FSM_CF_TP_SIZE 4 +#define SQ_DEBUG_TP_FSM_IF_TP_SIZE 3 +#define SQ_DEBUG_TP_FSM_RESERVED1_SIZE 1 +#define SQ_DEBUG_TP_FSM_TIS_TP_SIZE 2 +#define SQ_DEBUG_TP_FSM_RESERVED2_SIZE 2 +#define SQ_DEBUG_TP_FSM_GS_TP_SIZE 2 +#define SQ_DEBUG_TP_FSM_RESERVED3_SIZE 2 +#define SQ_DEBUG_TP_FSM_FCR_TP_SIZE 2 +#define SQ_DEBUG_TP_FSM_RESERVED4_SIZE 2 +#define SQ_DEBUG_TP_FSM_FCS_TP_SIZE 2 +#define SQ_DEBUG_TP_FSM_RESERVED5_SIZE 2 +#define SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE 3 + +#define SQ_DEBUG_TP_FSM_EX_TP_SHIFT 0 +#define SQ_DEBUG_TP_FSM_RESERVED0_SHIFT 3 +#define SQ_DEBUG_TP_FSM_CF_TP_SHIFT 4 +#define SQ_DEBUG_TP_FSM_IF_TP_SHIFT 8 +#define SQ_DEBUG_TP_FSM_RESERVED1_SHIFT 11 +#define SQ_DEBUG_TP_FSM_TIS_TP_SHIFT 12 +#define SQ_DEBUG_TP_FSM_RESERVED2_SHIFT 14 +#define SQ_DEBUG_TP_FSM_GS_TP_SHIFT 16 +#define SQ_DEBUG_TP_FSM_RESERVED3_SHIFT 18 +#define SQ_DEBUG_TP_FSM_FCR_TP_SHIFT 20 +#define SQ_DEBUG_TP_FSM_RESERVED4_SHIFT 22 +#define SQ_DEBUG_TP_FSM_FCS_TP_SHIFT 24 +#define SQ_DEBUG_TP_FSM_RESERVED5_SHIFT 26 +#define SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT 28 + +#define SQ_DEBUG_TP_FSM_EX_TP_MASK 0x00000007 +#define SQ_DEBUG_TP_FSM_RESERVED0_MASK 0x00000008 +#define SQ_DEBUG_TP_FSM_CF_TP_MASK 0x000000f0 +#define SQ_DEBUG_TP_FSM_IF_TP_MASK 0x00000700 +#define SQ_DEBUG_TP_FSM_RESERVED1_MASK 0x00000800 +#define SQ_DEBUG_TP_FSM_TIS_TP_MASK 0x00003000 +#define SQ_DEBUG_TP_FSM_RESERVED2_MASK 0x0000c000 +#define SQ_DEBUG_TP_FSM_GS_TP_MASK 0x00030000 +#define SQ_DEBUG_TP_FSM_RESERVED3_MASK 0x000c0000 +#define SQ_DEBUG_TP_FSM_FCR_TP_MASK 0x00300000 +#define SQ_DEBUG_TP_FSM_RESERVED4_MASK 0x00c00000 +#define SQ_DEBUG_TP_FSM_FCS_TP_MASK 0x03000000 +#define SQ_DEBUG_TP_FSM_RESERVED5_MASK 0x0c000000 +#define SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK 0x70000000 + +#define SQ_DEBUG_TP_FSM_MASK \ + (SQ_DEBUG_TP_FSM_EX_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED0_MASK | \ + SQ_DEBUG_TP_FSM_CF_TP_MASK | \ + SQ_DEBUG_TP_FSM_IF_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED1_MASK | \ + SQ_DEBUG_TP_FSM_TIS_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED2_MASK | \ + SQ_DEBUG_TP_FSM_GS_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED3_MASK | \ + SQ_DEBUG_TP_FSM_FCR_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED4_MASK | \ + SQ_DEBUG_TP_FSM_FCS_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED5_MASK | \ + SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) + +#define SQ_DEBUG_TP_FSM(ex_tp, reserved0, cf_tp, if_tp, reserved1, tis_tp, reserved2, gs_tp, reserved3, fcr_tp, reserved4, fcs_tp, reserved5, arb_tr_tp) \ + ((ex_tp << SQ_DEBUG_TP_FSM_EX_TP_SHIFT) | \ + (reserved0 << SQ_DEBUG_TP_FSM_RESERVED0_SHIFT) | \ + (cf_tp << SQ_DEBUG_TP_FSM_CF_TP_SHIFT) | \ + (if_tp << SQ_DEBUG_TP_FSM_IF_TP_SHIFT) | \ + (reserved1 << SQ_DEBUG_TP_FSM_RESERVED1_SHIFT) | \ + (tis_tp << SQ_DEBUG_TP_FSM_TIS_TP_SHIFT) | \ + (reserved2 << SQ_DEBUG_TP_FSM_RESERVED2_SHIFT) | \ + (gs_tp << SQ_DEBUG_TP_FSM_GS_TP_SHIFT) | \ + (reserved3 << SQ_DEBUG_TP_FSM_RESERVED3_SHIFT) | \ + (fcr_tp << SQ_DEBUG_TP_FSM_FCR_TP_SHIFT) | \ + (reserved4 << SQ_DEBUG_TP_FSM_RESERVED4_SHIFT) | \ + (fcs_tp << SQ_DEBUG_TP_FSM_FCS_TP_SHIFT) | \ + (reserved5 << SQ_DEBUG_TP_FSM_RESERVED5_SHIFT) | \ + (arb_tr_tp << SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT)) + +#define SQ_DEBUG_TP_FSM_GET_EX_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_EX_TP_MASK) >> SQ_DEBUG_TP_FSM_EX_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED0(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED0_MASK) >> SQ_DEBUG_TP_FSM_RESERVED0_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_CF_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_CF_TP_MASK) >> SQ_DEBUG_TP_FSM_CF_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_IF_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_IF_TP_MASK) >> SQ_DEBUG_TP_FSM_IF_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED1(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED1_MASK) >> SQ_DEBUG_TP_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_TIS_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_TIS_TP_MASK) >> SQ_DEBUG_TP_FSM_TIS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED2(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED2_MASK) >> SQ_DEBUG_TP_FSM_RESERVED2_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_GS_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_GS_TP_MASK) >> SQ_DEBUG_TP_FSM_GS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED3(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED3_MASK) >> SQ_DEBUG_TP_FSM_RESERVED3_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_FCR_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_FCR_TP_MASK) >> SQ_DEBUG_TP_FSM_FCR_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED4(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED4_MASK) >> SQ_DEBUG_TP_FSM_RESERVED4_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_FCS_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_FCS_TP_MASK) >> SQ_DEBUG_TP_FSM_FCS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED5(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED5_MASK) >> SQ_DEBUG_TP_FSM_RESERVED5_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_ARB_TR_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) >> SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT) + +#define SQ_DEBUG_TP_FSM_SET_EX_TP(sq_debug_tp_fsm_reg, ex_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_EX_TP_MASK) | (ex_tp << SQ_DEBUG_TP_FSM_EX_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED0(sq_debug_tp_fsm_reg, reserved0) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_TP_FSM_RESERVED0_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_CF_TP(sq_debug_tp_fsm_reg, cf_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_CF_TP_MASK) | (cf_tp << SQ_DEBUG_TP_FSM_CF_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_IF_TP(sq_debug_tp_fsm_reg, if_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_IF_TP_MASK) | (if_tp << SQ_DEBUG_TP_FSM_IF_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED1(sq_debug_tp_fsm_reg, reserved1) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_TP_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_TIS_TP(sq_debug_tp_fsm_reg, tis_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_TIS_TP_MASK) | (tis_tp << SQ_DEBUG_TP_FSM_TIS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED2(sq_debug_tp_fsm_reg, reserved2) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_TP_FSM_RESERVED2_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_GS_TP(sq_debug_tp_fsm_reg, gs_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_GS_TP_MASK) | (gs_tp << SQ_DEBUG_TP_FSM_GS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED3(sq_debug_tp_fsm_reg, reserved3) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_TP_FSM_RESERVED3_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_FCR_TP(sq_debug_tp_fsm_reg, fcr_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_FCR_TP_MASK) | (fcr_tp << SQ_DEBUG_TP_FSM_FCR_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED4(sq_debug_tp_fsm_reg, reserved4) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_TP_FSM_RESERVED4_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_FCS_TP(sq_debug_tp_fsm_reg, fcs_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_FCS_TP_MASK) | (fcs_tp << SQ_DEBUG_TP_FSM_FCS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED5(sq_debug_tp_fsm_reg, reserved5) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_TP_FSM_RESERVED5_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_ARB_TR_TP(sq_debug_tp_fsm_reg, arb_tr_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) | (arb_tr_tp << SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_tp_fsm_t { + unsigned int ex_tp : SQ_DEBUG_TP_FSM_EX_TP_SIZE; + unsigned int reserved0 : SQ_DEBUG_TP_FSM_RESERVED0_SIZE; + unsigned int cf_tp : SQ_DEBUG_TP_FSM_CF_TP_SIZE; + unsigned int if_tp : SQ_DEBUG_TP_FSM_IF_TP_SIZE; + unsigned int reserved1 : SQ_DEBUG_TP_FSM_RESERVED1_SIZE; + unsigned int tis_tp : SQ_DEBUG_TP_FSM_TIS_TP_SIZE; + unsigned int reserved2 : SQ_DEBUG_TP_FSM_RESERVED2_SIZE; + unsigned int gs_tp : SQ_DEBUG_TP_FSM_GS_TP_SIZE; + unsigned int reserved3 : SQ_DEBUG_TP_FSM_RESERVED3_SIZE; + unsigned int fcr_tp : SQ_DEBUG_TP_FSM_FCR_TP_SIZE; + unsigned int reserved4 : SQ_DEBUG_TP_FSM_RESERVED4_SIZE; + unsigned int fcs_tp : SQ_DEBUG_TP_FSM_FCS_TP_SIZE; + unsigned int reserved5 : SQ_DEBUG_TP_FSM_RESERVED5_SIZE; + unsigned int arb_tr_tp : SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE; + unsigned int : 1; + } sq_debug_tp_fsm_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_tp_fsm_t { + unsigned int : 1; + unsigned int arb_tr_tp : SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE; + unsigned int reserved5 : SQ_DEBUG_TP_FSM_RESERVED5_SIZE; + unsigned int fcs_tp : SQ_DEBUG_TP_FSM_FCS_TP_SIZE; + unsigned int reserved4 : SQ_DEBUG_TP_FSM_RESERVED4_SIZE; + unsigned int fcr_tp : SQ_DEBUG_TP_FSM_FCR_TP_SIZE; + unsigned int reserved3 : SQ_DEBUG_TP_FSM_RESERVED3_SIZE; + unsigned int gs_tp : SQ_DEBUG_TP_FSM_GS_TP_SIZE; + unsigned int reserved2 : SQ_DEBUG_TP_FSM_RESERVED2_SIZE; + unsigned int tis_tp : SQ_DEBUG_TP_FSM_TIS_TP_SIZE; + unsigned int reserved1 : SQ_DEBUG_TP_FSM_RESERVED1_SIZE; + unsigned int if_tp : SQ_DEBUG_TP_FSM_IF_TP_SIZE; + unsigned int cf_tp : SQ_DEBUG_TP_FSM_CF_TP_SIZE; + unsigned int reserved0 : SQ_DEBUG_TP_FSM_RESERVED0_SIZE; + unsigned int ex_tp : SQ_DEBUG_TP_FSM_EX_TP_SIZE; + } sq_debug_tp_fsm_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_tp_fsm_t f; +} sq_debug_tp_fsm_u; + + +/* + * SQ_DEBUG_FSM_ALU_0 struct + */ + +#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE 4 +#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE 3 + +#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT 0 +#define SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT 3 +#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT 4 +#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT 8 +#define SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT 11 +#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT 12 +#define SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT 15 +#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT 16 +#define SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT 19 +#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT 20 +#define SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT 23 +#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT 24 +#define SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT 27 +#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT 28 + +#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK 0x00000007 +#define SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK 0x00000008 +#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK 0x000000f0 +#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK 0x00000700 +#define SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK 0x00000800 +#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK 0x00007000 +#define SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK 0x00008000 +#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK 0x00070000 +#define SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK 0x00080000 +#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK 0x00700000 +#define SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK 0x00800000 +#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK 0x07000000 +#define SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK 0x08000000 +#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK 0x70000000 + +#define SQ_DEBUG_FSM_ALU_0_MASK \ + (SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK | \ + SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK | \ + SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK | \ + SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK | \ + SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK | \ + SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK | \ + SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) + +#define SQ_DEBUG_FSM_ALU_0(ex_alu_0, reserved0, cf_alu_0, if_alu_0, reserved1, du1_alu_0, reserved2, du0_alu_0, reserved3, ais_alu_0, reserved4, acs_alu_0, reserved5, arb_tr_alu) \ + ((ex_alu_0 << SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT) | \ + (reserved0 << SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT) | \ + (cf_alu_0 << SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT) | \ + (if_alu_0 << SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT) | \ + (reserved1 << SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT) | \ + (du1_alu_0 << SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT) | \ + (reserved2 << SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT) | \ + (du0_alu_0 << SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT) | \ + (reserved3 << SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT) | \ + (ais_alu_0 << SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT) | \ + (reserved4 << SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT) | \ + (acs_alu_0 << SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT) | \ + (reserved5 << SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT) | \ + (arb_tr_alu << SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT)) + +#define SQ_DEBUG_FSM_ALU_0_GET_EX_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_CF_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_IF_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED1(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_DU1_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED2(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_DU0_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED3(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_AIS_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED4(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_ACS_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED5(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_ARB_TR_ALU(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) >> SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT) + +#define SQ_DEBUG_FSM_ALU_0_SET_EX_ALU_0(sq_debug_fsm_alu_0_reg, ex_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK) | (ex_alu_0 << SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED0(sq_debug_fsm_alu_0_reg, reserved0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_CF_ALU_0(sq_debug_fsm_alu_0_reg, cf_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK) | (cf_alu_0 << SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_IF_ALU_0(sq_debug_fsm_alu_0_reg, if_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK) | (if_alu_0 << SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED1(sq_debug_fsm_alu_0_reg, reserved1) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_DU1_ALU_0(sq_debug_fsm_alu_0_reg, du1_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK) | (du1_alu_0 << SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED2(sq_debug_fsm_alu_0_reg, reserved2) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_DU0_ALU_0(sq_debug_fsm_alu_0_reg, du0_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK) | (du0_alu_0 << SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED3(sq_debug_fsm_alu_0_reg, reserved3) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_AIS_ALU_0(sq_debug_fsm_alu_0_reg, ais_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK) | (ais_alu_0 << SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED4(sq_debug_fsm_alu_0_reg, reserved4) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_ACS_ALU_0(sq_debug_fsm_alu_0_reg, acs_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK) | (acs_alu_0 << SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED5(sq_debug_fsm_alu_0_reg, reserved5) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_ARB_TR_ALU(sq_debug_fsm_alu_0_reg, arb_tr_alu) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) | (arb_tr_alu << SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_fsm_alu_0_t { + unsigned int ex_alu_0 : SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE; + unsigned int reserved0 : SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE; + unsigned int cf_alu_0 : SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE; + unsigned int if_alu_0 : SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE; + unsigned int reserved1 : SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE; + unsigned int du1_alu_0 : SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE; + unsigned int reserved2 : SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE; + unsigned int du0_alu_0 : SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE; + unsigned int reserved3 : SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE; + unsigned int ais_alu_0 : SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE; + unsigned int reserved4 : SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE; + unsigned int acs_alu_0 : SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE; + unsigned int reserved5 : SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE; + unsigned int arb_tr_alu : SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE; + unsigned int : 1; + } sq_debug_fsm_alu_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_fsm_alu_0_t { + unsigned int : 1; + unsigned int arb_tr_alu : SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE; + unsigned int reserved5 : SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE; + unsigned int acs_alu_0 : SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE; + unsigned int reserved4 : SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE; + unsigned int ais_alu_0 : SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE; + unsigned int reserved3 : SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE; + unsigned int du0_alu_0 : SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE; + unsigned int reserved2 : SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE; + unsigned int du1_alu_0 : SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE; + unsigned int reserved1 : SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE; + unsigned int if_alu_0 : SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE; + unsigned int cf_alu_0 : SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE; + unsigned int reserved0 : SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE; + unsigned int ex_alu_0 : SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE; + } sq_debug_fsm_alu_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_fsm_alu_0_t f; +} sq_debug_fsm_alu_0_u; + + +/* + * SQ_DEBUG_FSM_ALU_1 struct + */ + +#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE 4 +#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE 3 + +#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT 0 +#define SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT 3 +#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT 4 +#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT 8 +#define SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT 11 +#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT 12 +#define SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT 15 +#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT 16 +#define SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT 19 +#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT 20 +#define SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT 23 +#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT 24 +#define SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT 27 +#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT 28 + +#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK 0x00000007 +#define SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK 0x00000008 +#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK 0x000000f0 +#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK 0x00000700 +#define SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK 0x00000800 +#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK 0x00007000 +#define SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK 0x00008000 +#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK 0x00070000 +#define SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK 0x00080000 +#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK 0x00700000 +#define SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK 0x00800000 +#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK 0x07000000 +#define SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK 0x08000000 +#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK 0x70000000 + +#define SQ_DEBUG_FSM_ALU_1_MASK \ + (SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK | \ + SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK | \ + SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK | \ + SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK | \ + SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK | \ + SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK | \ + SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) + +#define SQ_DEBUG_FSM_ALU_1(ex_alu_0, reserved0, cf_alu_0, if_alu_0, reserved1, du1_alu_0, reserved2, du0_alu_0, reserved3, ais_alu_0, reserved4, acs_alu_0, reserved5, arb_tr_alu) \ + ((ex_alu_0 << SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT) | \ + (reserved0 << SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT) | \ + (cf_alu_0 << SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT) | \ + (if_alu_0 << SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT) | \ + (reserved1 << SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT) | \ + (du1_alu_0 << SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT) | \ + (reserved2 << SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT) | \ + (du0_alu_0 << SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT) | \ + (reserved3 << SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT) | \ + (ais_alu_0 << SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT) | \ + (reserved4 << SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT) | \ + (acs_alu_0 << SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT) | \ + (reserved5 << SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT) | \ + (arb_tr_alu << SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT)) + +#define SQ_DEBUG_FSM_ALU_1_GET_EX_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_CF_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_IF_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED1(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_DU1_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED2(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_DU0_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED3(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_AIS_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED4(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_ACS_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED5(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_ARB_TR_ALU(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) >> SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT) + +#define SQ_DEBUG_FSM_ALU_1_SET_EX_ALU_0(sq_debug_fsm_alu_1_reg, ex_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK) | (ex_alu_0 << SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED0(sq_debug_fsm_alu_1_reg, reserved0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_CF_ALU_0(sq_debug_fsm_alu_1_reg, cf_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK) | (cf_alu_0 << SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_IF_ALU_0(sq_debug_fsm_alu_1_reg, if_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK) | (if_alu_0 << SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED1(sq_debug_fsm_alu_1_reg, reserved1) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_DU1_ALU_0(sq_debug_fsm_alu_1_reg, du1_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK) | (du1_alu_0 << SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED2(sq_debug_fsm_alu_1_reg, reserved2) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_DU0_ALU_0(sq_debug_fsm_alu_1_reg, du0_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK) | (du0_alu_0 << SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED3(sq_debug_fsm_alu_1_reg, reserved3) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_AIS_ALU_0(sq_debug_fsm_alu_1_reg, ais_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK) | (ais_alu_0 << SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED4(sq_debug_fsm_alu_1_reg, reserved4) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_ACS_ALU_0(sq_debug_fsm_alu_1_reg, acs_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK) | (acs_alu_0 << SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED5(sq_debug_fsm_alu_1_reg, reserved5) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_ARB_TR_ALU(sq_debug_fsm_alu_1_reg, arb_tr_alu) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) | (arb_tr_alu << SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_fsm_alu_1_t { + unsigned int ex_alu_0 : SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE; + unsigned int reserved0 : SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE; + unsigned int cf_alu_0 : SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE; + unsigned int if_alu_0 : SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE; + unsigned int reserved1 : SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE; + unsigned int du1_alu_0 : SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE; + unsigned int reserved2 : SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE; + unsigned int du0_alu_0 : SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE; + unsigned int reserved3 : SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE; + unsigned int ais_alu_0 : SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE; + unsigned int reserved4 : SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE; + unsigned int acs_alu_0 : SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE; + unsigned int reserved5 : SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE; + unsigned int arb_tr_alu : SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE; + unsigned int : 1; + } sq_debug_fsm_alu_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_fsm_alu_1_t { + unsigned int : 1; + unsigned int arb_tr_alu : SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE; + unsigned int reserved5 : SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE; + unsigned int acs_alu_0 : SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE; + unsigned int reserved4 : SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE; + unsigned int ais_alu_0 : SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE; + unsigned int reserved3 : SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE; + unsigned int du0_alu_0 : SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE; + unsigned int reserved2 : SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE; + unsigned int du1_alu_0 : SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE; + unsigned int reserved1 : SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE; + unsigned int if_alu_0 : SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE; + unsigned int cf_alu_0 : SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE; + unsigned int reserved0 : SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE; + unsigned int ex_alu_0 : SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE; + } sq_debug_fsm_alu_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_fsm_alu_1_t f; +} sq_debug_fsm_alu_1_u; + + +/* + * SQ_DEBUG_EXP_ALLOC struct + */ + +#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE 4 +#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE 8 +#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE 3 +#define SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE 1 +#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE 6 + +#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT 0 +#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT 4 +#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT 12 +#define SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT 15 +#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT 16 + +#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK 0x0000000f +#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK 0x00000ff0 +#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK 0x00007000 +#define SQ_DEBUG_EXP_ALLOC_RESERVED_MASK 0x00008000 +#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK 0x003f0000 + +#define SQ_DEBUG_EXP_ALLOC_MASK \ + (SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK | \ + SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK | \ + SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK | \ + SQ_DEBUG_EXP_ALLOC_RESERVED_MASK | \ + SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) + +#define SQ_DEBUG_EXP_ALLOC(pos_buf_avail, color_buf_avail, ea_buf_avail, reserved, alloc_tbl_buf_avail) \ + ((pos_buf_avail << SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT) | \ + (color_buf_avail << SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT) | \ + (ea_buf_avail << SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT) | \ + (reserved << SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT) | \ + (alloc_tbl_buf_avail << SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT)) + +#define SQ_DEBUG_EXP_ALLOC_GET_POS_BUF_AVAIL(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_GET_COLOR_BUF_AVAIL(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_GET_EA_BUF_AVAIL(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_GET_RESERVED(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_RESERVED_MASK) >> SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_GET_ALLOC_TBL_BUF_AVAIL(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT) + +#define SQ_DEBUG_EXP_ALLOC_SET_POS_BUF_AVAIL(sq_debug_exp_alloc_reg, pos_buf_avail) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK) | (pos_buf_avail << SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_SET_COLOR_BUF_AVAIL(sq_debug_exp_alloc_reg, color_buf_avail) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK) | (color_buf_avail << SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_SET_EA_BUF_AVAIL(sq_debug_exp_alloc_reg, ea_buf_avail) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK) | (ea_buf_avail << SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_SET_RESERVED(sq_debug_exp_alloc_reg, reserved) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_RESERVED_MASK) | (reserved << SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_SET_ALLOC_TBL_BUF_AVAIL(sq_debug_exp_alloc_reg, alloc_tbl_buf_avail) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) | (alloc_tbl_buf_avail << SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_exp_alloc_t { + unsigned int pos_buf_avail : SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE; + unsigned int color_buf_avail : SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE; + unsigned int ea_buf_avail : SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE; + unsigned int reserved : SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE; + unsigned int alloc_tbl_buf_avail : SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE; + unsigned int : 10; + } sq_debug_exp_alloc_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_exp_alloc_t { + unsigned int : 10; + unsigned int alloc_tbl_buf_avail : SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE; + unsigned int reserved : SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE; + unsigned int ea_buf_avail : SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE; + unsigned int color_buf_avail : SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE; + unsigned int pos_buf_avail : SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE; + } sq_debug_exp_alloc_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_exp_alloc_t f; +} sq_debug_exp_alloc_u; + + +/* + * SQ_DEBUG_PTR_BUFF struct + */ + +#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE 4 +#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE 3 +#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE 5 +#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE 11 + +#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT 0 +#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT 1 +#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT 5 +#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT 6 +#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT 9 +#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT 14 +#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT 15 +#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT 16 +#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT 17 + +#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK 0x00000001 +#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK 0x0000001e +#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK 0x00000020 +#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK 0x000001c0 +#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK 0x00003e00 +#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK 0x00004000 +#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK 0x00008000 +#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK 0x00010000 +#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK 0x0ffe0000 + +#define SQ_DEBUG_PTR_BUFF_MASK \ + (SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK | \ + SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK | \ + SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK | \ + SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK | \ + SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK | \ + SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK | \ + SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK | \ + SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK | \ + SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) + +#define SQ_DEBUG_PTR_BUFF(end_of_buffer, dealloc_cnt, qual_new_vector, event_context_id, sc_event_id, qual_event, prim_type_polygon, ef_empty, vtx_sync_cnt) \ + ((end_of_buffer << SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT) | \ + (dealloc_cnt << SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT) | \ + (qual_new_vector << SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT) | \ + (event_context_id << SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT) | \ + (sc_event_id << SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT) | \ + (qual_event << SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT) | \ + (prim_type_polygon << SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT) | \ + (ef_empty << SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT) | \ + (vtx_sync_cnt << SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT)) + +#define SQ_DEBUG_PTR_BUFF_GET_END_OF_BUFFER(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK) >> SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_DEALLOC_CNT(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK) >> SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_QUAL_NEW_VECTOR(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK) >> SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_EVENT_CONTEXT_ID(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK) >> SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_SC_EVENT_ID(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK) >> SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_QUAL_EVENT(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK) >> SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_PRIM_TYPE_POLYGON(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK) >> SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_EF_EMPTY(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK) >> SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_VTX_SYNC_CNT(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) >> SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT) + +#define SQ_DEBUG_PTR_BUFF_SET_END_OF_BUFFER(sq_debug_ptr_buff_reg, end_of_buffer) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK) | (end_of_buffer << SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_DEALLOC_CNT(sq_debug_ptr_buff_reg, dealloc_cnt) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK) | (dealloc_cnt << SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_QUAL_NEW_VECTOR(sq_debug_ptr_buff_reg, qual_new_vector) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK) | (qual_new_vector << SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_EVENT_CONTEXT_ID(sq_debug_ptr_buff_reg, event_context_id) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK) | (event_context_id << SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_SC_EVENT_ID(sq_debug_ptr_buff_reg, sc_event_id) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK) | (sc_event_id << SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_QUAL_EVENT(sq_debug_ptr_buff_reg, qual_event) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK) | (qual_event << SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_PRIM_TYPE_POLYGON(sq_debug_ptr_buff_reg, prim_type_polygon) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK) | (prim_type_polygon << SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_EF_EMPTY(sq_debug_ptr_buff_reg, ef_empty) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK) | (ef_empty << SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_VTX_SYNC_CNT(sq_debug_ptr_buff_reg, vtx_sync_cnt) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) | (vtx_sync_cnt << SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_ptr_buff_t { + unsigned int end_of_buffer : SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE; + unsigned int dealloc_cnt : SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE; + unsigned int qual_new_vector : SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE; + unsigned int event_context_id : SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE; + unsigned int sc_event_id : SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE; + unsigned int qual_event : SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE; + unsigned int prim_type_polygon : SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE; + unsigned int ef_empty : SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE; + unsigned int vtx_sync_cnt : SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE; + unsigned int : 4; + } sq_debug_ptr_buff_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_ptr_buff_t { + unsigned int : 4; + unsigned int vtx_sync_cnt : SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE; + unsigned int ef_empty : SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE; + unsigned int prim_type_polygon : SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE; + unsigned int qual_event : SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE; + unsigned int sc_event_id : SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE; + unsigned int event_context_id : SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE; + unsigned int qual_new_vector : SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE; + unsigned int dealloc_cnt : SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE; + unsigned int end_of_buffer : SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE; + } sq_debug_ptr_buff_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_ptr_buff_t f; +} sq_debug_ptr_buff_u; + + +/* + * SQ_DEBUG_GPR_VTX struct + */ + +#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE 7 +#define SQ_DEBUG_GPR_VTX_RESERVED_SIZE 1 +#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE 7 +#define SQ_DEBUG_GPR_VTX_RESERVED1_SIZE 1 +#define SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE 7 +#define SQ_DEBUG_GPR_VTX_RESERVED2_SIZE 1 +#define SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE 7 + +#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT 0 +#define SQ_DEBUG_GPR_VTX_RESERVED_SHIFT 7 +#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT 8 +#define SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT 15 +#define SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT 16 +#define SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT 23 +#define SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT 24 + +#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK 0x0000007f +#define SQ_DEBUG_GPR_VTX_RESERVED_MASK 0x00000080 +#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK 0x00007f00 +#define SQ_DEBUG_GPR_VTX_RESERVED1_MASK 0x00008000 +#define SQ_DEBUG_GPR_VTX_VTX_MAX_MASK 0x007f0000 +#define SQ_DEBUG_GPR_VTX_RESERVED2_MASK 0x00800000 +#define SQ_DEBUG_GPR_VTX_VTX_FREE_MASK 0x7f000000 + +#define SQ_DEBUG_GPR_VTX_MASK \ + (SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK | \ + SQ_DEBUG_GPR_VTX_RESERVED_MASK | \ + SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK | \ + SQ_DEBUG_GPR_VTX_RESERVED1_MASK | \ + SQ_DEBUG_GPR_VTX_VTX_MAX_MASK | \ + SQ_DEBUG_GPR_VTX_RESERVED2_MASK | \ + SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) + +#define SQ_DEBUG_GPR_VTX(vtx_tail_ptr, reserved, vtx_head_ptr, reserved1, vtx_max, reserved2, vtx_free) \ + ((vtx_tail_ptr << SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT) | \ + (reserved << SQ_DEBUG_GPR_VTX_RESERVED_SHIFT) | \ + (vtx_head_ptr << SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT) | \ + (reserved1 << SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT) | \ + (vtx_max << SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT) | \ + (reserved2 << SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT) | \ + (vtx_free << SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT)) + +#define SQ_DEBUG_GPR_VTX_GET_VTX_TAIL_PTR(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK) >> SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_RESERVED(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_VTX_HEAD_PTR(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK) >> SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_RESERVED1(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED1_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_VTX_MAX(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_MAX_MASK) >> SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_RESERVED2(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED2_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_VTX_FREE(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) >> SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT) + +#define SQ_DEBUG_GPR_VTX_SET_VTX_TAIL_PTR(sq_debug_gpr_vtx_reg, vtx_tail_ptr) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK) | (vtx_tail_ptr << SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_RESERVED(sq_debug_gpr_vtx_reg, reserved) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED_MASK) | (reserved << SQ_DEBUG_GPR_VTX_RESERVED_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_VTX_HEAD_PTR(sq_debug_gpr_vtx_reg, vtx_head_ptr) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK) | (vtx_head_ptr << SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_RESERVED1(sq_debug_gpr_vtx_reg, reserved1) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_VTX_MAX(sq_debug_gpr_vtx_reg, vtx_max) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_MAX_MASK) | (vtx_max << SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_RESERVED2(sq_debug_gpr_vtx_reg, reserved2) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_VTX_FREE(sq_debug_gpr_vtx_reg, vtx_free) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) | (vtx_free << SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_gpr_vtx_t { + unsigned int vtx_tail_ptr : SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE; + unsigned int reserved : SQ_DEBUG_GPR_VTX_RESERVED_SIZE; + unsigned int vtx_head_ptr : SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE; + unsigned int reserved1 : SQ_DEBUG_GPR_VTX_RESERVED1_SIZE; + unsigned int vtx_max : SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE; + unsigned int reserved2 : SQ_DEBUG_GPR_VTX_RESERVED2_SIZE; + unsigned int vtx_free : SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE; + unsigned int : 1; + } sq_debug_gpr_vtx_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_gpr_vtx_t { + unsigned int : 1; + unsigned int vtx_free : SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE; + unsigned int reserved2 : SQ_DEBUG_GPR_VTX_RESERVED2_SIZE; + unsigned int vtx_max : SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE; + unsigned int reserved1 : SQ_DEBUG_GPR_VTX_RESERVED1_SIZE; + unsigned int vtx_head_ptr : SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE; + unsigned int reserved : SQ_DEBUG_GPR_VTX_RESERVED_SIZE; + unsigned int vtx_tail_ptr : SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE; + } sq_debug_gpr_vtx_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_gpr_vtx_t f; +} sq_debug_gpr_vtx_u; + + +/* + * SQ_DEBUG_GPR_PIX struct + */ + +#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE 7 +#define SQ_DEBUG_GPR_PIX_RESERVED_SIZE 1 +#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE 7 +#define SQ_DEBUG_GPR_PIX_RESERVED1_SIZE 1 +#define SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE 7 +#define SQ_DEBUG_GPR_PIX_RESERVED2_SIZE 1 +#define SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE 7 + +#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT 0 +#define SQ_DEBUG_GPR_PIX_RESERVED_SHIFT 7 +#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT 8 +#define SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT 15 +#define SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT 16 +#define SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT 23 +#define SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT 24 + +#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK 0x0000007f +#define SQ_DEBUG_GPR_PIX_RESERVED_MASK 0x00000080 +#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK 0x00007f00 +#define SQ_DEBUG_GPR_PIX_RESERVED1_MASK 0x00008000 +#define SQ_DEBUG_GPR_PIX_PIX_MAX_MASK 0x007f0000 +#define SQ_DEBUG_GPR_PIX_RESERVED2_MASK 0x00800000 +#define SQ_DEBUG_GPR_PIX_PIX_FREE_MASK 0x7f000000 + +#define SQ_DEBUG_GPR_PIX_MASK \ + (SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK | \ + SQ_DEBUG_GPR_PIX_RESERVED_MASK | \ + SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK | \ + SQ_DEBUG_GPR_PIX_RESERVED1_MASK | \ + SQ_DEBUG_GPR_PIX_PIX_MAX_MASK | \ + SQ_DEBUG_GPR_PIX_RESERVED2_MASK | \ + SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) + +#define SQ_DEBUG_GPR_PIX(pix_tail_ptr, reserved, pix_head_ptr, reserved1, pix_max, reserved2, pix_free) \ + ((pix_tail_ptr << SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT) | \ + (reserved << SQ_DEBUG_GPR_PIX_RESERVED_SHIFT) | \ + (pix_head_ptr << SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT) | \ + (reserved1 << SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT) | \ + (pix_max << SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT) | \ + (reserved2 << SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT) | \ + (pix_free << SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT)) + +#define SQ_DEBUG_GPR_PIX_GET_PIX_TAIL_PTR(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK) >> SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_RESERVED(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_PIX_HEAD_PTR(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK) >> SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_RESERVED1(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED1_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_PIX_MAX(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_MAX_MASK) >> SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_RESERVED2(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED2_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_PIX_FREE(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) >> SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT) + +#define SQ_DEBUG_GPR_PIX_SET_PIX_TAIL_PTR(sq_debug_gpr_pix_reg, pix_tail_ptr) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK) | (pix_tail_ptr << SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_RESERVED(sq_debug_gpr_pix_reg, reserved) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED_MASK) | (reserved << SQ_DEBUG_GPR_PIX_RESERVED_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_PIX_HEAD_PTR(sq_debug_gpr_pix_reg, pix_head_ptr) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK) | (pix_head_ptr << SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_RESERVED1(sq_debug_gpr_pix_reg, reserved1) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_PIX_MAX(sq_debug_gpr_pix_reg, pix_max) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_MAX_MASK) | (pix_max << SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_RESERVED2(sq_debug_gpr_pix_reg, reserved2) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_PIX_FREE(sq_debug_gpr_pix_reg, pix_free) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) | (pix_free << SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_gpr_pix_t { + unsigned int pix_tail_ptr : SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE; + unsigned int reserved : SQ_DEBUG_GPR_PIX_RESERVED_SIZE; + unsigned int pix_head_ptr : SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE; + unsigned int reserved1 : SQ_DEBUG_GPR_PIX_RESERVED1_SIZE; + unsigned int pix_max : SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE; + unsigned int reserved2 : SQ_DEBUG_GPR_PIX_RESERVED2_SIZE; + unsigned int pix_free : SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE; + unsigned int : 1; + } sq_debug_gpr_pix_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_gpr_pix_t { + unsigned int : 1; + unsigned int pix_free : SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE; + unsigned int reserved2 : SQ_DEBUG_GPR_PIX_RESERVED2_SIZE; + unsigned int pix_max : SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE; + unsigned int reserved1 : SQ_DEBUG_GPR_PIX_RESERVED1_SIZE; + unsigned int pix_head_ptr : SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE; + unsigned int reserved : SQ_DEBUG_GPR_PIX_RESERVED_SIZE; + unsigned int pix_tail_ptr : SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE; + } sq_debug_gpr_pix_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_gpr_pix_t f; +} sq_debug_gpr_pix_u; + + +/* + * SQ_DEBUG_TB_STATUS_SEL struct + */ + +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE 4 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE 3 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE 4 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE 1 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE 1 +#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE 2 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE 4 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE 3 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE 6 +#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE 2 +#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE 1 + +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT 0 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT 4 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT 7 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT 11 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT 12 +#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT 14 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT 16 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT 20 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT 23 +#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT 29 +#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT 31 + +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK 0x0000000f +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK 0x00000070 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK 0x00000780 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK 0x00000800 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK 0x00001000 +#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK 0x0000c000 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK 0x000f0000 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK 0x00700000 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK 0x1f800000 +#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK 0x60000000 +#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK 0x80000000 + +#define SQ_DEBUG_TB_STATUS_SEL_MASK \ + (SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) + +#define SQ_DEBUG_TB_STATUS_SEL(vtx_tb_status_reg_sel, vtx_tb_state_mem_dw_sel, vtx_tb_state_mem_rd_addr, vtx_tb_state_mem_rd_en, pix_tb_state_mem_rd_en, debug_bus_trigger_sel, pix_tb_status_reg_sel, pix_tb_state_mem_dw_sel, pix_tb_state_mem_rd_addr, vc_thread_buf_dly, disable_strict_ctx_sync) \ + ((vtx_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT) | \ + (vtx_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT) | \ + (vtx_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT) | \ + (vtx_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT) | \ + (pix_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT) | \ + (debug_bus_trigger_sel << SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT) | \ + (pix_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT) | \ + (pix_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT) | \ + (pix_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT) | \ + (vc_thread_buf_dly << SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT) | \ + (disable_strict_ctx_sync << SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT)) + +#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_DEBUG_BUS_TRIGGER_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_VC_THREAD_BUF_DLY(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_DISABLE_STRICT_CTX_SYNC(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) >> SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT) + +#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel_reg, vtx_tb_status_reg_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK) | (vtx_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_dw_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK) | (vtx_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_rd_addr) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK) | (vtx_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_rd_en) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK) | (vtx_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel_reg, pix_tb_state_mem_rd_en) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK) | (pix_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_DEBUG_BUS_TRIGGER_SEL(sq_debug_tb_status_sel_reg, debug_bus_trigger_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK) | (debug_bus_trigger_sel << SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel_reg, pix_tb_status_reg_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK) | (pix_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel_reg, pix_tb_state_mem_dw_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK) | (pix_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel_reg, pix_tb_state_mem_rd_addr) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK) | (pix_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_VC_THREAD_BUF_DLY(sq_debug_tb_status_sel_reg, vc_thread_buf_dly) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK) | (vc_thread_buf_dly << SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_DISABLE_STRICT_CTX_SYNC(sq_debug_tb_status_sel_reg, disable_strict_ctx_sync) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) | (disable_strict_ctx_sync << SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_tb_status_sel_t { + unsigned int vtx_tb_status_reg_sel : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE; + unsigned int vtx_tb_state_mem_dw_sel : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE; + unsigned int vtx_tb_state_mem_rd_addr : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE; + unsigned int vtx_tb_state_mem_rd_en : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE; + unsigned int pix_tb_state_mem_rd_en : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE; + unsigned int : 1; + unsigned int debug_bus_trigger_sel : SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE; + unsigned int pix_tb_status_reg_sel : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE; + unsigned int pix_tb_state_mem_dw_sel : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE; + unsigned int pix_tb_state_mem_rd_addr : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE; + unsigned int vc_thread_buf_dly : SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE; + unsigned int disable_strict_ctx_sync : SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE; + } sq_debug_tb_status_sel_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_tb_status_sel_t { + unsigned int disable_strict_ctx_sync : SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE; + unsigned int vc_thread_buf_dly : SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE; + unsigned int pix_tb_state_mem_rd_addr : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE; + unsigned int pix_tb_state_mem_dw_sel : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE; + unsigned int pix_tb_status_reg_sel : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE; + unsigned int debug_bus_trigger_sel : SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE; + unsigned int : 1; + unsigned int pix_tb_state_mem_rd_en : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE; + unsigned int vtx_tb_state_mem_rd_en : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE; + unsigned int vtx_tb_state_mem_rd_addr : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE; + unsigned int vtx_tb_state_mem_dw_sel : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE; + unsigned int vtx_tb_status_reg_sel : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE; + } sq_debug_tb_status_sel_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_tb_status_sel_t f; +} sq_debug_tb_status_sel_u; + + +/* + * SQ_DEBUG_VTX_TB_0 struct + */ + +#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE 1 +#define SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE 1 + +#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT 0 +#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT 4 +#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT 8 +#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT 12 +#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT 16 +#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT 20 +#define SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT 21 + +#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK 0x0000000f +#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK 0x000000f0 +#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK 0x00000f00 +#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK 0x0000f000 +#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK 0x000f0000 +#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK 0x00100000 +#define SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK 0x00200000 + +#define SQ_DEBUG_VTX_TB_0_MASK \ + (SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK | \ + SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK | \ + SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK | \ + SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK | \ + SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK | \ + SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK | \ + SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) + +#define SQ_DEBUG_VTX_TB_0(vtx_head_ptr_q, tail_ptr_q, full_cnt_q, nxt_pos_alloc_cnt, nxt_pc_alloc_cnt, sx_event_full, busy_q) \ + ((vtx_head_ptr_q << SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT) | \ + (tail_ptr_q << SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT) | \ + (full_cnt_q << SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT) | \ + (nxt_pos_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT) | \ + (nxt_pc_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT) | \ + (sx_event_full << SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT) | \ + (busy_q << SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT)) + +#define SQ_DEBUG_VTX_TB_0_GET_VTX_HEAD_PTR_Q(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK) >> SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_TAIL_PTR_Q(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK) >> SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_FULL_CNT_Q(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK) >> SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_NXT_POS_ALLOC_CNT(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK) >> SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_NXT_PC_ALLOC_CNT(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK) >> SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_SX_EVENT_FULL(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK) >> SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_BUSY_Q(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) >> SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT) + +#define SQ_DEBUG_VTX_TB_0_SET_VTX_HEAD_PTR_Q(sq_debug_vtx_tb_0_reg, vtx_head_ptr_q) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK) | (vtx_head_ptr_q << SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_TAIL_PTR_Q(sq_debug_vtx_tb_0_reg, tail_ptr_q) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK) | (tail_ptr_q << SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_FULL_CNT_Q(sq_debug_vtx_tb_0_reg, full_cnt_q) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK) | (full_cnt_q << SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_NXT_POS_ALLOC_CNT(sq_debug_vtx_tb_0_reg, nxt_pos_alloc_cnt) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK) | (nxt_pos_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_NXT_PC_ALLOC_CNT(sq_debug_vtx_tb_0_reg, nxt_pc_alloc_cnt) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK) | (nxt_pc_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_SX_EVENT_FULL(sq_debug_vtx_tb_0_reg, sx_event_full) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK) | (sx_event_full << SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_BUSY_Q(sq_debug_vtx_tb_0_reg, busy_q) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) | (busy_q << SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_0_t { + unsigned int vtx_head_ptr_q : SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE; + unsigned int tail_ptr_q : SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE; + unsigned int full_cnt_q : SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE; + unsigned int nxt_pos_alloc_cnt : SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE; + unsigned int nxt_pc_alloc_cnt : SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE; + unsigned int sx_event_full : SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE; + unsigned int busy_q : SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE; + unsigned int : 10; + } sq_debug_vtx_tb_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_0_t { + unsigned int : 10; + unsigned int busy_q : SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE; + unsigned int sx_event_full : SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE; + unsigned int nxt_pc_alloc_cnt : SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE; + unsigned int nxt_pos_alloc_cnt : SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE; + unsigned int full_cnt_q : SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE; + unsigned int tail_ptr_q : SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE; + unsigned int vtx_head_ptr_q : SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE; + } sq_debug_vtx_tb_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_vtx_tb_0_t f; +} sq_debug_vtx_tb_0_u; + + +/* + * SQ_DEBUG_VTX_TB_1 struct + */ + +#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE 16 + +#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT 0 + +#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK 0x0000ffff + +#define SQ_DEBUG_VTX_TB_1_MASK \ + (SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) + +#define SQ_DEBUG_VTX_TB_1(vs_done_ptr) \ + ((vs_done_ptr << SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT)) + +#define SQ_DEBUG_VTX_TB_1_GET_VS_DONE_PTR(sq_debug_vtx_tb_1) \ + ((sq_debug_vtx_tb_1 & SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) >> SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT) + +#define SQ_DEBUG_VTX_TB_1_SET_VS_DONE_PTR(sq_debug_vtx_tb_1_reg, vs_done_ptr) \ + sq_debug_vtx_tb_1_reg = (sq_debug_vtx_tb_1_reg & ~SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) | (vs_done_ptr << SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_1_t { + unsigned int vs_done_ptr : SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE; + unsigned int : 16; + } sq_debug_vtx_tb_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_1_t { + unsigned int : 16; + unsigned int vs_done_ptr : SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE; + } sq_debug_vtx_tb_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_vtx_tb_1_t f; +} sq_debug_vtx_tb_1_u; + + +/* + * SQ_DEBUG_VTX_TB_STATUS_REG struct + */ + +#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE 32 + +#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT 0 + +#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK 0xffffffff + +#define SQ_DEBUG_VTX_TB_STATUS_REG_MASK \ + (SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) + +#define SQ_DEBUG_VTX_TB_STATUS_REG(vs_status_reg) \ + ((vs_status_reg << SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT)) + +#define SQ_DEBUG_VTX_TB_STATUS_REG_GET_VS_STATUS_REG(sq_debug_vtx_tb_status_reg) \ + ((sq_debug_vtx_tb_status_reg & SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) >> SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT) + +#define SQ_DEBUG_VTX_TB_STATUS_REG_SET_VS_STATUS_REG(sq_debug_vtx_tb_status_reg_reg, vs_status_reg) \ + sq_debug_vtx_tb_status_reg_reg = (sq_debug_vtx_tb_status_reg_reg & ~SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) | (vs_status_reg << SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_status_reg_t { + unsigned int vs_status_reg : SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE; + } sq_debug_vtx_tb_status_reg_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_status_reg_t { + unsigned int vs_status_reg : SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE; + } sq_debug_vtx_tb_status_reg_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_vtx_tb_status_reg_t f; +} sq_debug_vtx_tb_status_reg_u; + + +/* + * SQ_DEBUG_VTX_TB_STATE_MEM struct + */ + +#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE 32 + +#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT 0 + +#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK 0xffffffff + +#define SQ_DEBUG_VTX_TB_STATE_MEM_MASK \ + (SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) + +#define SQ_DEBUG_VTX_TB_STATE_MEM(vs_state_mem) \ + ((vs_state_mem << SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT)) + +#define SQ_DEBUG_VTX_TB_STATE_MEM_GET_VS_STATE_MEM(sq_debug_vtx_tb_state_mem) \ + ((sq_debug_vtx_tb_state_mem & SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) >> SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT) + +#define SQ_DEBUG_VTX_TB_STATE_MEM_SET_VS_STATE_MEM(sq_debug_vtx_tb_state_mem_reg, vs_state_mem) \ + sq_debug_vtx_tb_state_mem_reg = (sq_debug_vtx_tb_state_mem_reg & ~SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) | (vs_state_mem << SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_state_mem_t { + unsigned int vs_state_mem : SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE; + } sq_debug_vtx_tb_state_mem_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_state_mem_t { + unsigned int vs_state_mem : SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE; + } sq_debug_vtx_tb_state_mem_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_vtx_tb_state_mem_t f; +} sq_debug_vtx_tb_state_mem_u; + + +/* + * SQ_DEBUG_PIX_TB_0 struct + */ + +#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE 6 +#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE 6 +#define SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE 7 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE 6 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE 6 +#define SQ_DEBUG_PIX_TB_0_BUSY_SIZE 1 + +#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT 0 +#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT 6 +#define SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT 12 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT 19 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT 25 +#define SQ_DEBUG_PIX_TB_0_BUSY_SHIFT 31 + +#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK 0x0000003f +#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK 0x00000fc0 +#define SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK 0x0007f000 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK 0x01f80000 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK 0x7e000000 +#define SQ_DEBUG_PIX_TB_0_BUSY_MASK 0x80000000 + +#define SQ_DEBUG_PIX_TB_0_MASK \ + (SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK | \ + SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK | \ + SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK | \ + SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK | \ + SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK | \ + SQ_DEBUG_PIX_TB_0_BUSY_MASK) + +#define SQ_DEBUG_PIX_TB_0(pix_head_ptr, tail_ptr, full_cnt, nxt_pix_alloc_cnt, nxt_pix_exp_cnt, busy) \ + ((pix_head_ptr << SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT) | \ + (tail_ptr << SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT) | \ + (full_cnt << SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT) | \ + (nxt_pix_alloc_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT) | \ + (nxt_pix_exp_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT) | \ + (busy << SQ_DEBUG_PIX_TB_0_BUSY_SHIFT)) + +#define SQ_DEBUG_PIX_TB_0_GET_PIX_HEAD_PTR(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK) >> SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_TAIL_PTR(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK) >> SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_FULL_CNT(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_NXT_PIX_ALLOC_CNT(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_NXT_PIX_EXP_CNT(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_BUSY(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_BUSY_MASK) >> SQ_DEBUG_PIX_TB_0_BUSY_SHIFT) + +#define SQ_DEBUG_PIX_TB_0_SET_PIX_HEAD_PTR(sq_debug_pix_tb_0_reg, pix_head_ptr) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK) | (pix_head_ptr << SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_TAIL_PTR(sq_debug_pix_tb_0_reg, tail_ptr) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK) | (tail_ptr << SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_FULL_CNT(sq_debug_pix_tb_0_reg, full_cnt) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK) | (full_cnt << SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_NXT_PIX_ALLOC_CNT(sq_debug_pix_tb_0_reg, nxt_pix_alloc_cnt) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK) | (nxt_pix_alloc_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_NXT_PIX_EXP_CNT(sq_debug_pix_tb_0_reg, nxt_pix_exp_cnt) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK) | (nxt_pix_exp_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_BUSY(sq_debug_pix_tb_0_reg, busy) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_BUSY_MASK) | (busy << SQ_DEBUG_PIX_TB_0_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_0_t { + unsigned int pix_head_ptr : SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE; + unsigned int tail_ptr : SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE; + unsigned int full_cnt : SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE; + unsigned int nxt_pix_alloc_cnt : SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE; + unsigned int nxt_pix_exp_cnt : SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE; + unsigned int busy : SQ_DEBUG_PIX_TB_0_BUSY_SIZE; + } sq_debug_pix_tb_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_0_t { + unsigned int busy : SQ_DEBUG_PIX_TB_0_BUSY_SIZE; + unsigned int nxt_pix_exp_cnt : SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE; + unsigned int nxt_pix_alloc_cnt : SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE; + unsigned int full_cnt : SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE; + unsigned int tail_ptr : SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE; + unsigned int pix_head_ptr : SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE; + } sq_debug_pix_tb_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_0_t f; +} sq_debug_pix_tb_0_u; + + +/* + * SQ_DEBUG_PIX_TB_STATUS_REG_0 struct + */ + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_MASK \ + (SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0(pix_tb_status_reg_0) \ + ((pix_tb_status_reg_0 << SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_GET_PIX_TB_STATUS_REG_0(sq_debug_pix_tb_status_reg_0) \ + ((sq_debug_pix_tb_status_reg_0 & SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_SET_PIX_TB_STATUS_REG_0(sq_debug_pix_tb_status_reg_0_reg, pix_tb_status_reg_0) \ + sq_debug_pix_tb_status_reg_0_reg = (sq_debug_pix_tb_status_reg_0_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) | (pix_tb_status_reg_0 << SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_0_t { + unsigned int pix_tb_status_reg_0 : SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE; + } sq_debug_pix_tb_status_reg_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_0_t { + unsigned int pix_tb_status_reg_0 : SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE; + } sq_debug_pix_tb_status_reg_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_status_reg_0_t f; +} sq_debug_pix_tb_status_reg_0_u; + + +/* + * SQ_DEBUG_PIX_TB_STATUS_REG_1 struct + */ + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_MASK \ + (SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1(pix_tb_status_reg_1) \ + ((pix_tb_status_reg_1 << SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_GET_PIX_TB_STATUS_REG_1(sq_debug_pix_tb_status_reg_1) \ + ((sq_debug_pix_tb_status_reg_1 & SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_SET_PIX_TB_STATUS_REG_1(sq_debug_pix_tb_status_reg_1_reg, pix_tb_status_reg_1) \ + sq_debug_pix_tb_status_reg_1_reg = (sq_debug_pix_tb_status_reg_1_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) | (pix_tb_status_reg_1 << SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_1_t { + unsigned int pix_tb_status_reg_1 : SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE; + } sq_debug_pix_tb_status_reg_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_1_t { + unsigned int pix_tb_status_reg_1 : SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE; + } sq_debug_pix_tb_status_reg_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_status_reg_1_t f; +} sq_debug_pix_tb_status_reg_1_u; + + +/* + * SQ_DEBUG_PIX_TB_STATUS_REG_2 struct + */ + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_MASK \ + (SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2(pix_tb_status_reg_2) \ + ((pix_tb_status_reg_2 << SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_GET_PIX_TB_STATUS_REG_2(sq_debug_pix_tb_status_reg_2) \ + ((sq_debug_pix_tb_status_reg_2 & SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_SET_PIX_TB_STATUS_REG_2(sq_debug_pix_tb_status_reg_2_reg, pix_tb_status_reg_2) \ + sq_debug_pix_tb_status_reg_2_reg = (sq_debug_pix_tb_status_reg_2_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) | (pix_tb_status_reg_2 << SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_2_t { + unsigned int pix_tb_status_reg_2 : SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE; + } sq_debug_pix_tb_status_reg_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_2_t { + unsigned int pix_tb_status_reg_2 : SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE; + } sq_debug_pix_tb_status_reg_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_status_reg_2_t f; +} sq_debug_pix_tb_status_reg_2_u; + + +/* + * SQ_DEBUG_PIX_TB_STATUS_REG_3 struct + */ + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_MASK \ + (SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3(pix_tb_status_reg_3) \ + ((pix_tb_status_reg_3 << SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_GET_PIX_TB_STATUS_REG_3(sq_debug_pix_tb_status_reg_3) \ + ((sq_debug_pix_tb_status_reg_3 & SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_SET_PIX_TB_STATUS_REG_3(sq_debug_pix_tb_status_reg_3_reg, pix_tb_status_reg_3) \ + sq_debug_pix_tb_status_reg_3_reg = (sq_debug_pix_tb_status_reg_3_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) | (pix_tb_status_reg_3 << SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_3_t { + unsigned int pix_tb_status_reg_3 : SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE; + } sq_debug_pix_tb_status_reg_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_3_t { + unsigned int pix_tb_status_reg_3 : SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE; + } sq_debug_pix_tb_status_reg_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_status_reg_3_t f; +} sq_debug_pix_tb_status_reg_3_u; + + +/* + * SQ_DEBUG_PIX_TB_STATE_MEM struct + */ + +#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATE_MEM_MASK \ + (SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) + +#define SQ_DEBUG_PIX_TB_STATE_MEM(pix_tb_state_mem) \ + ((pix_tb_state_mem << SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATE_MEM_GET_PIX_TB_STATE_MEM(sq_debug_pix_tb_state_mem) \ + ((sq_debug_pix_tb_state_mem & SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) >> SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATE_MEM_SET_PIX_TB_STATE_MEM(sq_debug_pix_tb_state_mem_reg, pix_tb_state_mem) \ + sq_debug_pix_tb_state_mem_reg = (sq_debug_pix_tb_state_mem_reg & ~SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) | (pix_tb_state_mem << SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_state_mem_t { + unsigned int pix_tb_state_mem : SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE; + } sq_debug_pix_tb_state_mem_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_state_mem_t { + unsigned int pix_tb_state_mem : SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE; + } sq_debug_pix_tb_state_mem_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_state_mem_t f; +} sq_debug_pix_tb_state_mem_u; + + +/* + * SQ_PERFCOUNTER0_SELECT struct + */ + +#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define SQ_PERFCOUNTER0_SELECT_MASK \ + (SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define SQ_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define SQ_PERFCOUNTER0_SELECT_GET_PERF_SEL(sq_perfcounter0_select) \ + ((sq_perfcounter0_select & SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define SQ_PERFCOUNTER0_SELECT_SET_PERF_SEL(sq_perfcounter0_select_reg, perf_sel) \ + sq_perfcounter0_select_reg = (sq_perfcounter0_select_reg & ~SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter0_select_t { + unsigned int perf_sel : SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sq_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } sq_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter0_select_t f; +} sq_perfcounter0_select_u; + + +/* + * SQ_PERFCOUNTER1_SELECT struct + */ + +#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8 + +#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0 + +#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff + +#define SQ_PERFCOUNTER1_SELECT_MASK \ + (SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) + +#define SQ_PERFCOUNTER1_SELECT(perf_sel) \ + ((perf_sel << SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)) + +#define SQ_PERFCOUNTER1_SELECT_GET_PERF_SEL(sq_perfcounter1_select) \ + ((sq_perfcounter1_select & SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#define SQ_PERFCOUNTER1_SELECT_SET_PERF_SEL(sq_perfcounter1_select_reg, perf_sel) \ + sq_perfcounter1_select_reg = (sq_perfcounter1_select_reg & ~SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter1_select_t { + unsigned int perf_sel : SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sq_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter1_select_t { + unsigned int : 24; + unsigned int perf_sel : SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + } sq_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter1_select_t f; +} sq_perfcounter1_select_u; + + +/* + * SQ_PERFCOUNTER2_SELECT struct + */ + +#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8 + +#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0 + +#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff + +#define SQ_PERFCOUNTER2_SELECT_MASK \ + (SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) + +#define SQ_PERFCOUNTER2_SELECT(perf_sel) \ + ((perf_sel << SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)) + +#define SQ_PERFCOUNTER2_SELECT_GET_PERF_SEL(sq_perfcounter2_select) \ + ((sq_perfcounter2_select & SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#define SQ_PERFCOUNTER2_SELECT_SET_PERF_SEL(sq_perfcounter2_select_reg, perf_sel) \ + sq_perfcounter2_select_reg = (sq_perfcounter2_select_reg & ~SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter2_select_t { + unsigned int perf_sel : SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sq_perfcounter2_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter2_select_t { + unsigned int : 24; + unsigned int perf_sel : SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + } sq_perfcounter2_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter2_select_t f; +} sq_perfcounter2_select_u; + + +/* + * SQ_PERFCOUNTER3_SELECT struct + */ + +#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8 + +#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0 + +#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff + +#define SQ_PERFCOUNTER3_SELECT_MASK \ + (SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) + +#define SQ_PERFCOUNTER3_SELECT(perf_sel) \ + ((perf_sel << SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)) + +#define SQ_PERFCOUNTER3_SELECT_GET_PERF_SEL(sq_perfcounter3_select) \ + ((sq_perfcounter3_select & SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#define SQ_PERFCOUNTER3_SELECT_SET_PERF_SEL(sq_perfcounter3_select_reg, perf_sel) \ + sq_perfcounter3_select_reg = (sq_perfcounter3_select_reg & ~SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter3_select_t { + unsigned int perf_sel : SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sq_perfcounter3_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter3_select_t { + unsigned int : 24; + unsigned int perf_sel : SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + } sq_perfcounter3_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter3_select_t f; +} sq_perfcounter3_select_u; + + +/* + * SQ_PERFCOUNTER0_LOW struct + */ + +#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define SQ_PERFCOUNTER0_LOW_MASK \ + (SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER0_LOW_GET_PERF_COUNT(sq_perfcounter0_low) \ + ((sq_perfcounter0_low & SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER0_LOW_SET_PERF_COUNT(sq_perfcounter0_low_reg, perf_count) \ + sq_perfcounter0_low_reg = (sq_perfcounter0_low_reg & ~SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter0_low_t { + unsigned int perf_count : SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } sq_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter0_low_t { + unsigned int perf_count : SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } sq_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter0_low_t f; +} sq_perfcounter0_low_u; + + +/* + * SQ_PERFCOUNTER0_HI struct + */ + +#define SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define SQ_PERFCOUNTER0_HI_MASK \ + (SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER0_HI_GET_PERF_COUNT(sq_perfcounter0_hi) \ + ((sq_perfcounter0_hi & SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER0_HI_SET_PERF_COUNT(sq_perfcounter0_hi_reg, perf_count) \ + sq_perfcounter0_hi_reg = (sq_perfcounter0_hi_reg & ~SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter0_hi_t { + unsigned int perf_count : SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sq_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } sq_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter0_hi_t f; +} sq_perfcounter0_hi_u; + + +/* + * SQ_PERFCOUNTER1_LOW struct + */ + +#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32 + +#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff + +#define SQ_PERFCOUNTER1_LOW_MASK \ + (SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER1_LOW(perf_count) \ + ((perf_count << SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER1_LOW_GET_PERF_COUNT(sq_perfcounter1_low) \ + ((sq_perfcounter1_low & SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER1_LOW_SET_PERF_COUNT(sq_perfcounter1_low_reg, perf_count) \ + sq_perfcounter1_low_reg = (sq_perfcounter1_low_reg & ~SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter1_low_t { + unsigned int perf_count : SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } sq_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter1_low_t { + unsigned int perf_count : SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } sq_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter1_low_t f; +} sq_perfcounter1_low_u; + + +/* + * SQ_PERFCOUNTER1_HI struct + */ + +#define SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16 + +#define SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff + +#define SQ_PERFCOUNTER1_HI_MASK \ + (SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER1_HI(perf_count) \ + ((perf_count << SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER1_HI_GET_PERF_COUNT(sq_perfcounter1_hi) \ + ((sq_perfcounter1_hi & SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER1_HI_SET_PERF_COUNT(sq_perfcounter1_hi_reg, perf_count) \ + sq_perfcounter1_hi_reg = (sq_perfcounter1_hi_reg & ~SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter1_hi_t { + unsigned int perf_count : SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sq_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_count : SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + } sq_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter1_hi_t f; +} sq_perfcounter1_hi_u; + + +/* + * SQ_PERFCOUNTER2_LOW struct + */ + +#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32 + +#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff + +#define SQ_PERFCOUNTER2_LOW_MASK \ + (SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER2_LOW(perf_count) \ + ((perf_count << SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER2_LOW_GET_PERF_COUNT(sq_perfcounter2_low) \ + ((sq_perfcounter2_low & SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER2_LOW_SET_PERF_COUNT(sq_perfcounter2_low_reg, perf_count) \ + sq_perfcounter2_low_reg = (sq_perfcounter2_low_reg & ~SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter2_low_t { + unsigned int perf_count : SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } sq_perfcounter2_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter2_low_t { + unsigned int perf_count : SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } sq_perfcounter2_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter2_low_t f; +} sq_perfcounter2_low_u; + + +/* + * SQ_PERFCOUNTER2_HI struct + */ + +#define SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16 + +#define SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff + +#define SQ_PERFCOUNTER2_HI_MASK \ + (SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER2_HI(perf_count) \ + ((perf_count << SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER2_HI_GET_PERF_COUNT(sq_perfcounter2_hi) \ + ((sq_perfcounter2_hi & SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER2_HI_SET_PERF_COUNT(sq_perfcounter2_hi_reg, perf_count) \ + sq_perfcounter2_hi_reg = (sq_perfcounter2_hi_reg & ~SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter2_hi_t { + unsigned int perf_count : SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sq_perfcounter2_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter2_hi_t { + unsigned int : 16; + unsigned int perf_count : SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + } sq_perfcounter2_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter2_hi_t f; +} sq_perfcounter2_hi_u; + + +/* + * SQ_PERFCOUNTER3_LOW struct + */ + +#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32 + +#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff + +#define SQ_PERFCOUNTER3_LOW_MASK \ + (SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER3_LOW(perf_count) \ + ((perf_count << SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER3_LOW_GET_PERF_COUNT(sq_perfcounter3_low) \ + ((sq_perfcounter3_low & SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER3_LOW_SET_PERF_COUNT(sq_perfcounter3_low_reg, perf_count) \ + sq_perfcounter3_low_reg = (sq_perfcounter3_low_reg & ~SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter3_low_t { + unsigned int perf_count : SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } sq_perfcounter3_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter3_low_t { + unsigned int perf_count : SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } sq_perfcounter3_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter3_low_t f; +} sq_perfcounter3_low_u; + + +/* + * SQ_PERFCOUNTER3_HI struct + */ + +#define SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16 + +#define SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff + +#define SQ_PERFCOUNTER3_HI_MASK \ + (SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER3_HI(perf_count) \ + ((perf_count << SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER3_HI_GET_PERF_COUNT(sq_perfcounter3_hi) \ + ((sq_perfcounter3_hi & SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER3_HI_SET_PERF_COUNT(sq_perfcounter3_hi_reg, perf_count) \ + sq_perfcounter3_hi_reg = (sq_perfcounter3_hi_reg & ~SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter3_hi_t { + unsigned int perf_count : SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sq_perfcounter3_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter3_hi_t { + unsigned int : 16; + unsigned int perf_count : SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + } sq_perfcounter3_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter3_hi_t f; +} sq_perfcounter3_hi_u; + + +/* + * SX_PERFCOUNTER0_SELECT struct + */ + +#define SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define SX_PERFCOUNTER0_SELECT_MASK \ + (SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define SX_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define SX_PERFCOUNTER0_SELECT_GET_PERF_SEL(sx_perfcounter0_select) \ + ((sx_perfcounter0_select & SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define SX_PERFCOUNTER0_SELECT_SET_PERF_SEL(sx_perfcounter0_select_reg, perf_sel) \ + sx_perfcounter0_select_reg = (sx_perfcounter0_select_reg & ~SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sx_perfcounter0_select_t { + unsigned int perf_sel : SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sx_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sx_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } sx_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sx_perfcounter0_select_t f; +} sx_perfcounter0_select_u; + + +/* + * SX_PERFCOUNTER0_LOW struct + */ + +#define SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define SX_PERFCOUNTER0_LOW_MASK \ + (SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define SX_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define SX_PERFCOUNTER0_LOW_GET_PERF_COUNT(sx_perfcounter0_low) \ + ((sx_perfcounter0_low & SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define SX_PERFCOUNTER0_LOW_SET_PERF_COUNT(sx_perfcounter0_low_reg, perf_count) \ + sx_perfcounter0_low_reg = (sx_perfcounter0_low_reg & ~SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sx_perfcounter0_low_t { + unsigned int perf_count : SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } sx_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sx_perfcounter0_low_t { + unsigned int perf_count : SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } sx_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sx_perfcounter0_low_t f; +} sx_perfcounter0_low_u; + + +/* + * SX_PERFCOUNTER0_HI struct + */ + +#define SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define SX_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define SX_PERFCOUNTER0_HI_MASK \ + (SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define SX_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define SX_PERFCOUNTER0_HI_GET_PERF_COUNT(sx_perfcounter0_hi) \ + ((sx_perfcounter0_hi & SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define SX_PERFCOUNTER0_HI_SET_PERF_COUNT(sx_perfcounter0_hi_reg, perf_count) \ + sx_perfcounter0_hi_reg = (sx_perfcounter0_hi_reg & ~SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sx_perfcounter0_hi_t { + unsigned int perf_count : SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sx_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sx_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } sx_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sx_perfcounter0_hi_t f; +} sx_perfcounter0_hi_u; + + +/* + * SQ_INSTRUCTION_ALU_0 struct + */ + +#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE 6 +#define SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE 6 +#define SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE 4 +#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE 4 +#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE 6 + +#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT 0 +#define SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT 6 +#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT 7 +#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT 8 +#define SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT 14 +#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT 15 +#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT 16 +#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT 20 +#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT 24 +#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT 25 +#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT 26 + +#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK 0x0000003f +#define SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK 0x00000040 +#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK 0x00000080 +#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK 0x00003f00 +#define SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK 0x00004000 +#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK 0x00008000 +#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK 0x000f0000 +#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK 0x00f00000 +#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK 0x01000000 +#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK 0x02000000 +#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK 0xfc000000 + +#define SQ_INSTRUCTION_ALU_0_MASK \ + (SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK | \ + SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK | \ + SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK | \ + SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK | \ + SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK | \ + SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK | \ + SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK | \ + SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK | \ + SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK | \ + SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK | \ + SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) + +#define SQ_INSTRUCTION_ALU_0(vector_result, vector_dst_rel, low_precision_16b_fp, scalar_result, scalar_dst_rel, export_data, vector_wrt_msk, scalar_wrt_msk, vector_clamp, scalar_clamp, scalar_opcode) \ + ((vector_result << SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT) | \ + (vector_dst_rel << SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT) | \ + (low_precision_16b_fp << SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT) | \ + (scalar_result << SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT) | \ + (scalar_dst_rel << SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT) | \ + (export_data << SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT) | \ + (vector_wrt_msk << SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT) | \ + (scalar_wrt_msk << SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT) | \ + (vector_clamp << SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT) | \ + (scalar_clamp << SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT) | \ + (scalar_opcode << SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_RESULT(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_DST_REL(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_LOW_PRECISION_16B_FP(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK) >> SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_RESULT(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_DST_REL(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_EXPORT_DATA(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK) >> SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_WRT_MSK(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_WRT_MSK(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_CLAMP(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_CLAMP(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_OPCODE(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_RESULT(sq_instruction_alu_0_reg, vector_result) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK) | (vector_result << SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_DST_REL(sq_instruction_alu_0_reg, vector_dst_rel) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK) | (vector_dst_rel << SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_LOW_PRECISION_16B_FP(sq_instruction_alu_0_reg, low_precision_16b_fp) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK) | (low_precision_16b_fp << SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_RESULT(sq_instruction_alu_0_reg, scalar_result) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK) | (scalar_result << SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_DST_REL(sq_instruction_alu_0_reg, scalar_dst_rel) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK) | (scalar_dst_rel << SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_EXPORT_DATA(sq_instruction_alu_0_reg, export_data) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK) | (export_data << SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_WRT_MSK(sq_instruction_alu_0_reg, vector_wrt_msk) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK) | (vector_wrt_msk << SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_WRT_MSK(sq_instruction_alu_0_reg, scalar_wrt_msk) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK) | (scalar_wrt_msk << SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_CLAMP(sq_instruction_alu_0_reg, vector_clamp) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK) | (vector_clamp << SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_CLAMP(sq_instruction_alu_0_reg, scalar_clamp) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK) | (scalar_clamp << SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_OPCODE(sq_instruction_alu_0_reg, scalar_opcode) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) | (scalar_opcode << SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_alu_0_t { + unsigned int vector_result : SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE; + unsigned int vector_dst_rel : SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SIZE; + unsigned int low_precision_16b_fp : SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE; + unsigned int scalar_result : SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE; + unsigned int scalar_dst_rel : SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SIZE; + unsigned int export_data : SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE; + unsigned int vector_wrt_msk : SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE; + unsigned int scalar_wrt_msk : SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE; + unsigned int vector_clamp : SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE; + unsigned int scalar_clamp : SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE; + unsigned int scalar_opcode : SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE; + } sq_instruction_alu_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_alu_0_t { + unsigned int scalar_opcode : SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE; + unsigned int scalar_clamp : SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE; + unsigned int vector_clamp : SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE; + unsigned int scalar_wrt_msk : SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE; + unsigned int vector_wrt_msk : SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE; + unsigned int export_data : SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE; + unsigned int scalar_dst_rel : SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SIZE; + unsigned int scalar_result : SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE; + unsigned int low_precision_16b_fp : SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE; + unsigned int vector_dst_rel : SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SIZE; + unsigned int vector_result : SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE; + } sq_instruction_alu_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_alu_0_t f; +} sq_instruction_alu_0_u; + + +/* + * SQ_INSTRUCTION_ALU_1 struct + */ + +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE 1 + +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT 0 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT 4 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT 6 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT 8 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT 10 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT 12 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT 14 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT 16 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT 18 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT 20 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT 22 +#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT 24 +#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT 25 +#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT 26 +#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT 27 +#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT 29 +#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT 30 +#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT 31 + +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK 0x00000003 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK 0x0000000c +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK 0x00000030 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK 0x000000c0 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK 0x00000300 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK 0x00000c00 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK 0x00003000 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK 0x0000c000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK 0x00030000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK 0x000c0000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK 0x00300000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK 0x00c00000 +#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK 0x01000000 +#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK 0x02000000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK 0x04000000 +#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK 0x18000000 +#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK 0x20000000 +#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK 0x40000000 +#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK 0x80000000 + +#define SQ_INSTRUCTION_ALU_1_MASK \ + (SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK | \ + SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK | \ + SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK | \ + SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK | \ + SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) + +#define SQ_INSTRUCTION_ALU_1(src_c_swizzle_r, src_c_swizzle_g, src_c_swizzle_b, src_c_swizzle_a, src_b_swizzle_r, src_b_swizzle_g, src_b_swizzle_b, src_b_swizzle_a, src_a_swizzle_r, src_a_swizzle_g, src_a_swizzle_b, src_a_swizzle_a, src_c_arg_mod, src_b_arg_mod, src_a_arg_mod, pred_select, relative_addr, const_1_rel_abs, const_0_rel_abs) \ + ((src_c_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT) | \ + (src_c_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT) | \ + (src_c_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT) | \ + (src_c_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT) | \ + (src_b_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT) | \ + (src_b_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT) | \ + (src_b_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT) | \ + (src_b_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT) | \ + (src_a_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT) | \ + (src_a_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT) | \ + (src_a_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT) | \ + (src_a_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT) | \ + (src_c_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT) | \ + (src_b_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT) | \ + (src_a_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT) | \ + (pred_select << SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT) | \ + (relative_addr << SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT) | \ + (const_1_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT) | \ + (const_0_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT)) + +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_R(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_G(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_B(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_A(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_R(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_G(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_B(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_A(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_R(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_G(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_B(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_A(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_ARG_MOD(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_ARG_MOD(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_ARG_MOD(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_PRED_SELECT(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_RELATIVE_ADDR(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK) >> SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_CONST_1_REL_ABS(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK) >> SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_CONST_0_REL_ABS(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) >> SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT) + +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_R(sq_instruction_alu_1_reg, src_c_swizzle_r) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK) | (src_c_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_G(sq_instruction_alu_1_reg, src_c_swizzle_g) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK) | (src_c_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_B(sq_instruction_alu_1_reg, src_c_swizzle_b) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK) | (src_c_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_A(sq_instruction_alu_1_reg, src_c_swizzle_a) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK) | (src_c_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_R(sq_instruction_alu_1_reg, src_b_swizzle_r) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK) | (src_b_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_G(sq_instruction_alu_1_reg, src_b_swizzle_g) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK) | (src_b_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_B(sq_instruction_alu_1_reg, src_b_swizzle_b) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK) | (src_b_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_A(sq_instruction_alu_1_reg, src_b_swizzle_a) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK) | (src_b_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_R(sq_instruction_alu_1_reg, src_a_swizzle_r) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK) | (src_a_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_G(sq_instruction_alu_1_reg, src_a_swizzle_g) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK) | (src_a_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_B(sq_instruction_alu_1_reg, src_a_swizzle_b) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK) | (src_a_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_A(sq_instruction_alu_1_reg, src_a_swizzle_a) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK) | (src_a_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_ARG_MOD(sq_instruction_alu_1_reg, src_c_arg_mod) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK) | (src_c_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_ARG_MOD(sq_instruction_alu_1_reg, src_b_arg_mod) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK) | (src_b_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_ARG_MOD(sq_instruction_alu_1_reg, src_a_arg_mod) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK) | (src_a_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_PRED_SELECT(sq_instruction_alu_1_reg, pred_select) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_RELATIVE_ADDR(sq_instruction_alu_1_reg, relative_addr) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK) | (relative_addr << SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_CONST_1_REL_ABS(sq_instruction_alu_1_reg, const_1_rel_abs) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK) | (const_1_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_CONST_0_REL_ABS(sq_instruction_alu_1_reg, const_0_rel_abs) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) | (const_0_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_alu_1_t { + unsigned int src_c_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE; + unsigned int src_c_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE; + unsigned int src_c_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE; + unsigned int src_c_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE; + unsigned int src_b_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE; + unsigned int src_b_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE; + unsigned int src_b_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE; + unsigned int src_b_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE; + unsigned int src_a_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE; + unsigned int src_a_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE; + unsigned int src_a_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE; + unsigned int src_a_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE; + unsigned int src_c_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE; + unsigned int src_b_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE; + unsigned int src_a_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE; + unsigned int pred_select : SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE; + unsigned int relative_addr : SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE; + unsigned int const_1_rel_abs : SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE; + unsigned int const_0_rel_abs : SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE; + } sq_instruction_alu_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_alu_1_t { + unsigned int const_0_rel_abs : SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE; + unsigned int const_1_rel_abs : SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE; + unsigned int relative_addr : SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE; + unsigned int pred_select : SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE; + unsigned int src_a_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE; + unsigned int src_b_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE; + unsigned int src_c_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE; + unsigned int src_a_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE; + unsigned int src_a_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE; + unsigned int src_a_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE; + unsigned int src_a_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE; + unsigned int src_b_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE; + unsigned int src_b_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE; + unsigned int src_b_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE; + unsigned int src_b_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE; + unsigned int src_c_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE; + unsigned int src_c_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE; + unsigned int src_c_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE; + unsigned int src_c_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE; + } sq_instruction_alu_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_alu_1_t f; +} sq_instruction_alu_1_u; + + +/* + * SQ_INSTRUCTION_ALU_2 struct + */ + +#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE 6 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE 6 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE 6 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE 5 +#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE 1 + +#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT 0 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT 6 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT 7 +#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT 8 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT 14 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT 15 +#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT 16 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT 22 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT 23 +#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT 24 +#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT 29 +#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT 30 +#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT 31 + +#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK 0x0000003f +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK 0x00000040 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK 0x00000080 +#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK 0x00003f00 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK 0x00004000 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK 0x00008000 +#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK 0x003f0000 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK 0x00400000 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK 0x00800000 +#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK 0x1f000000 +#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK 0x20000000 +#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK 0x40000000 +#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK 0x80000000 + +#define SQ_INSTRUCTION_ALU_2_MASK \ + (SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK | \ + SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) + +#define SQ_INSTRUCTION_ALU_2(src_c_reg_ptr, reg_select_c, reg_abs_mod_c, src_b_reg_ptr, reg_select_b, reg_abs_mod_b, src_a_reg_ptr, reg_select_a, reg_abs_mod_a, vector_opcode, src_c_sel, src_b_sel, src_a_sel) \ + ((src_c_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT) | \ + (reg_select_c << SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT) | \ + (reg_abs_mod_c << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT) | \ + (src_b_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT) | \ + (reg_select_b << SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT) | \ + (reg_abs_mod_b << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT) | \ + (src_a_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT) | \ + (reg_select_a << SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT) | \ + (reg_abs_mod_a << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT) | \ + (vector_opcode << SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT) | \ + (src_c_sel << SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT) | \ + (src_b_sel << SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT) | \ + (src_a_sel << SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT)) + +#define SQ_INSTRUCTION_ALU_2_GET_SRC_C_REG_PTR(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_C(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_C(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_B_REG_PTR(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_B(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_B(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_A_REG_PTR(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_A(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_A(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_VECTOR_OPCODE(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK) >> SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_C_SEL(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_B_SEL(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_A_SEL(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT) + +#define SQ_INSTRUCTION_ALU_2_SET_SRC_C_REG_PTR(sq_instruction_alu_2_reg, src_c_reg_ptr) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK) | (src_c_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_C(sq_instruction_alu_2_reg, reg_select_c) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK) | (reg_select_c << SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_C(sq_instruction_alu_2_reg, reg_abs_mod_c) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK) | (reg_abs_mod_c << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_B_REG_PTR(sq_instruction_alu_2_reg, src_b_reg_ptr) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK) | (src_b_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_B(sq_instruction_alu_2_reg, reg_select_b) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK) | (reg_select_b << SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_B(sq_instruction_alu_2_reg, reg_abs_mod_b) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK) | (reg_abs_mod_b << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_A_REG_PTR(sq_instruction_alu_2_reg, src_a_reg_ptr) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK) | (src_a_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_A(sq_instruction_alu_2_reg, reg_select_a) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK) | (reg_select_a << SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_A(sq_instruction_alu_2_reg, reg_abs_mod_a) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK) | (reg_abs_mod_a << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_VECTOR_OPCODE(sq_instruction_alu_2_reg, vector_opcode) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK) | (vector_opcode << SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_C_SEL(sq_instruction_alu_2_reg, src_c_sel) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK) | (src_c_sel << SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_B_SEL(sq_instruction_alu_2_reg, src_b_sel) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK) | (src_b_sel << SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_A_SEL(sq_instruction_alu_2_reg, src_a_sel) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) | (src_a_sel << SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_alu_2_t { + unsigned int src_c_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE; + unsigned int reg_select_c : SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE; + unsigned int reg_abs_mod_c : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE; + unsigned int src_b_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE; + unsigned int reg_select_b : SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE; + unsigned int reg_abs_mod_b : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE; + unsigned int src_a_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE; + unsigned int reg_select_a : SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE; + unsigned int reg_abs_mod_a : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE; + unsigned int vector_opcode : SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE; + unsigned int src_c_sel : SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE; + unsigned int src_b_sel : SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE; + unsigned int src_a_sel : SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE; + } sq_instruction_alu_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_alu_2_t { + unsigned int src_a_sel : SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE; + unsigned int src_b_sel : SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE; + unsigned int src_c_sel : SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE; + unsigned int vector_opcode : SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE; + unsigned int reg_abs_mod_a : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE; + unsigned int reg_select_a : SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE; + unsigned int src_a_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE; + unsigned int reg_abs_mod_b : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE; + unsigned int reg_select_b : SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE; + unsigned int src_b_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE; + unsigned int reg_abs_mod_c : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE; + unsigned int reg_select_c : SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE; + unsigned int src_c_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE; + } sq_instruction_alu_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_alu_2_t f; +} sq_instruction_alu_2_u; + + +/* + * SQ_INSTRUCTION_CF_EXEC_0 struct + */ + +#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE 9 +#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE 3 +#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE 3 +#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE 1 + +#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT 0 +#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT 9 +#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT 12 +#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT 15 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT 16 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT 17 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT 18 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT 19 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT 20 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT 21 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT 22 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT 23 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT 24 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT 25 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT 26 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT 27 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT 28 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT 29 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT 30 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT 31 + +#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK 0x000001ff +#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK 0x00000e00 +#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK 0x00007000 +#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK 0x00008000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK 0x00010000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK 0x00020000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK 0x00040000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK 0x00080000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK 0x00100000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK 0x00200000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK 0x00400000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK 0x00800000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK 0x01000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK 0x02000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK 0x04000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK 0x10000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK 0x20000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK 0x40000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK 0x80000000 + +#define SQ_INSTRUCTION_CF_EXEC_0_MASK \ + (SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) + +#define SQ_INSTRUCTION_CF_EXEC_0(address, reserved, count, yield, inst_type_0, inst_serial_0, inst_type_1, inst_serial_1, inst_type_2, inst_serial_2, inst_type_3, inst_serial_3, inst_type_4, inst_serial_4, inst_type_5, inst_serial_5, inst_vc_0, inst_vc_1, inst_vc_2, inst_vc_3) \ + ((address << SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT) | \ + (reserved << SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT) | \ + (count << SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT) | \ + (yield << SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT) | \ + (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT) | \ + (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT) | \ + (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT) | \ + (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT) | \ + (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT) | \ + (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT) | \ + (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT) | \ + (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT) | \ + (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT) | \ + (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT) | \ + (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT) | \ + (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT) | \ + (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT) | \ + (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT) | \ + (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT) | \ + (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT)) + +#define SQ_INSTRUCTION_CF_EXEC_0_GET_ADDRESS(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_RESERVED(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_COUNT(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_YIELD(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_0(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_0(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_1(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_1(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_2(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_2(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_3(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_3(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_4(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_4(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_5(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_5(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_0(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_1(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_2(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_3(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT) + +#define SQ_INSTRUCTION_CF_EXEC_0_SET_ADDRESS(sq_instruction_cf_exec_0_reg, address) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_RESERVED(sq_instruction_cf_exec_0_reg, reserved) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_COUNT(sq_instruction_cf_exec_0_reg, count) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK) | (count << SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_YIELD(sq_instruction_cf_exec_0_reg, yield) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK) | (yield << SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_0(sq_instruction_cf_exec_0_reg, inst_type_0) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK) | (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_0(sq_instruction_cf_exec_0_reg, inst_serial_0) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK) | (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_1(sq_instruction_cf_exec_0_reg, inst_type_1) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK) | (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_1(sq_instruction_cf_exec_0_reg, inst_serial_1) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK) | (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_2(sq_instruction_cf_exec_0_reg, inst_type_2) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK) | (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_2(sq_instruction_cf_exec_0_reg, inst_serial_2) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK) | (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_3(sq_instruction_cf_exec_0_reg, inst_type_3) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK) | (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_3(sq_instruction_cf_exec_0_reg, inst_serial_3) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK) | (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_4(sq_instruction_cf_exec_0_reg, inst_type_4) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK) | (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_4(sq_instruction_cf_exec_0_reg, inst_serial_4) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK) | (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_5(sq_instruction_cf_exec_0_reg, inst_type_5) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK) | (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_5(sq_instruction_cf_exec_0_reg, inst_serial_5) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK) | (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_0(sq_instruction_cf_exec_0_reg, inst_vc_0) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK) | (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_1(sq_instruction_cf_exec_0_reg, inst_vc_1) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK) | (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_2(sq_instruction_cf_exec_0_reg, inst_vc_2) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK) | (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_3(sq_instruction_cf_exec_0_reg, inst_vc_3) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) | (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_0_t { + unsigned int address : SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE; + unsigned int count : SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE; + unsigned int yield : SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE; + unsigned int inst_type_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE; + unsigned int inst_serial_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE; + unsigned int inst_type_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE; + unsigned int inst_serial_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE; + unsigned int inst_type_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE; + unsigned int inst_serial_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE; + unsigned int inst_type_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE; + unsigned int inst_serial_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE; + unsigned int inst_type_4 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE; + unsigned int inst_serial_4 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE; + unsigned int inst_type_5 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE; + unsigned int inst_serial_5 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE; + unsigned int inst_vc_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE; + unsigned int inst_vc_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE; + unsigned int inst_vc_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE; + unsigned int inst_vc_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE; + } sq_instruction_cf_exec_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_0_t { + unsigned int inst_vc_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE; + unsigned int inst_vc_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE; + unsigned int inst_vc_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE; + unsigned int inst_vc_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE; + unsigned int inst_serial_5 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE; + unsigned int inst_type_5 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE; + unsigned int inst_serial_4 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE; + unsigned int inst_type_4 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE; + unsigned int inst_serial_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE; + unsigned int inst_type_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE; + unsigned int inst_serial_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE; + unsigned int inst_type_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE; + unsigned int inst_serial_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE; + unsigned int inst_type_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE; + unsigned int inst_serial_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE; + unsigned int inst_type_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE; + unsigned int yield : SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE; + unsigned int count : SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE; + } sq_instruction_cf_exec_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_exec_0_t f; +} sq_instruction_cf_exec_0_u; + + +/* + * SQ_INSTRUCTION_CF_EXEC_1 struct + */ + +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE 8 +#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE 4 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE 9 +#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE 3 +#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE 3 +#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE 1 + +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT 0 +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT 1 +#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT 2 +#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT 10 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT 11 +#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT 12 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT 16 +#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT 25 +#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT 28 +#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT 31 + +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK 0x00000001 +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK 0x00000002 +#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK 0x000003fc +#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK 0x00000400 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK 0x0000f000 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK 0x01ff0000 +#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK 0x0e000000 +#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK 0x70000000 +#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK 0x80000000 + +#define SQ_INSTRUCTION_CF_EXEC_1_MASK \ + (SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) + +#define SQ_INSTRUCTION_CF_EXEC_1(inst_vc_4, inst_vc_5, bool_addr, condition, address_mode, opcode, address, reserved, count, yield) \ + ((inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT) | \ + (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT) | \ + (bool_addr << SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT) | \ + (condition << SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT) | \ + (address << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT) | \ + (reserved << SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT) | \ + (count << SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT) | \ + (yield << SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT)) + +#define SQ_INSTRUCTION_CF_EXEC_1_GET_INST_VC_4(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_INST_VC_5(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_BOOL_ADDR(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_CONDITION(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_ADDRESS_MODE(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_OPCODE(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_ADDRESS(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_RESERVED(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_COUNT(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_YIELD(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT) + +#define SQ_INSTRUCTION_CF_EXEC_1_SET_INST_VC_4(sq_instruction_cf_exec_1_reg, inst_vc_4) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK) | (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_INST_VC_5(sq_instruction_cf_exec_1_reg, inst_vc_5) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK) | (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_BOOL_ADDR(sq_instruction_cf_exec_1_reg, bool_addr) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_CONDITION(sq_instruction_cf_exec_1_reg, condition) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_ADDRESS_MODE(sq_instruction_cf_exec_1_reg, address_mode) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_OPCODE(sq_instruction_cf_exec_1_reg, opcode) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_ADDRESS(sq_instruction_cf_exec_1_reg, address) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_RESERVED(sq_instruction_cf_exec_1_reg, reserved) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_COUNT(sq_instruction_cf_exec_1_reg, count) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK) | (count << SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_YIELD(sq_instruction_cf_exec_1_reg, yield) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) | (yield << SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_1_t { + unsigned int inst_vc_4 : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE; + unsigned int inst_vc_5 : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE; + unsigned int count : SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE; + unsigned int yield : SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE; + } sq_instruction_cf_exec_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_1_t { + unsigned int yield : SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE; + unsigned int count : SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE; + unsigned int inst_vc_5 : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE; + unsigned int inst_vc_4 : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE; + } sq_instruction_cf_exec_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_exec_1_t f; +} sq_instruction_cf_exec_1_u; + + +/* + * SQ_INSTRUCTION_CF_EXEC_2 struct + */ + +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE 8 +#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE 4 + +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT 0 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT 2 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT 3 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT 4 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT 5 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT 6 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT 7 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT 8 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT 9 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT 10 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT 11 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT 12 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT 13 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT 14 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT 15 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT 16 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT 17 +#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT 18 +#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT 26 +#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT 27 +#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT 28 + +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK 0x00000001 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK 0x00000002 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK 0x00000004 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK 0x00000008 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK 0x00000010 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK 0x00000020 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK 0x00000040 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK 0x00000080 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK 0x00000100 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK 0x00000200 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK 0x00000400 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK 0x00001000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK 0x00002000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK 0x00004000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK 0x00008000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK 0x00010000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK 0x00020000 +#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK 0x03fc0000 +#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK 0x04000000 +#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK 0xf0000000 + +#define SQ_INSTRUCTION_CF_EXEC_2_MASK \ + (SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) + +#define SQ_INSTRUCTION_CF_EXEC_2(inst_type_0, inst_serial_0, inst_type_1, inst_serial_1, inst_type_2, inst_serial_2, inst_type_3, inst_serial_3, inst_type_4, inst_serial_4, inst_type_5, inst_serial_5, inst_vc_0, inst_vc_1, inst_vc_2, inst_vc_3, inst_vc_4, inst_vc_5, bool_addr, condition, address_mode, opcode) \ + ((inst_type_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT) | \ + (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT) | \ + (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT) | \ + (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT) | \ + (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT) | \ + (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT) | \ + (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT) | \ + (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT) | \ + (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT) | \ + (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT) | \ + (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT) | \ + (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT) | \ + (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT) | \ + (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT) | \ + (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT) | \ + (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT) | \ + (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT) | \ + (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT) | \ + (bool_addr << SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT) | \ + (condition << SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_0(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_0(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_1(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_1(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_2(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_2(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_3(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_3(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_4(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_4(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_5(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_5(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_0(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_1(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_2(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_3(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_4(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_5(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_BOOL_ADDR(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_CONDITION(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_ADDRESS_MODE(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_OPCODE(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_0(sq_instruction_cf_exec_2_reg, inst_type_0) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK) | (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_0(sq_instruction_cf_exec_2_reg, inst_serial_0) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK) | (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_1(sq_instruction_cf_exec_2_reg, inst_type_1) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK) | (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_1(sq_instruction_cf_exec_2_reg, inst_serial_1) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK) | (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_2(sq_instruction_cf_exec_2_reg, inst_type_2) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK) | (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_2(sq_instruction_cf_exec_2_reg, inst_serial_2) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK) | (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_3(sq_instruction_cf_exec_2_reg, inst_type_3) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK) | (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_3(sq_instruction_cf_exec_2_reg, inst_serial_3) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK) | (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_4(sq_instruction_cf_exec_2_reg, inst_type_4) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK) | (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_4(sq_instruction_cf_exec_2_reg, inst_serial_4) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK) | (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_5(sq_instruction_cf_exec_2_reg, inst_type_5) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK) | (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_5(sq_instruction_cf_exec_2_reg, inst_serial_5) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK) | (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_0(sq_instruction_cf_exec_2_reg, inst_vc_0) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK) | (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_1(sq_instruction_cf_exec_2_reg, inst_vc_1) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK) | (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_2(sq_instruction_cf_exec_2_reg, inst_vc_2) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK) | (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_3(sq_instruction_cf_exec_2_reg, inst_vc_3) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK) | (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_4(sq_instruction_cf_exec_2_reg, inst_vc_4) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK) | (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_5(sq_instruction_cf_exec_2_reg, inst_vc_5) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK) | (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_BOOL_ADDR(sq_instruction_cf_exec_2_reg, bool_addr) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_CONDITION(sq_instruction_cf_exec_2_reg, condition) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_ADDRESS_MODE(sq_instruction_cf_exec_2_reg, address_mode) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_OPCODE(sq_instruction_cf_exec_2_reg, opcode) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_2_t { + unsigned int inst_type_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE; + unsigned int inst_serial_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE; + unsigned int inst_type_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE; + unsigned int inst_serial_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE; + unsigned int inst_type_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE; + unsigned int inst_serial_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE; + unsigned int inst_type_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE; + unsigned int inst_serial_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE; + unsigned int inst_type_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE; + unsigned int inst_serial_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE; + unsigned int inst_type_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE; + unsigned int inst_serial_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE; + unsigned int inst_vc_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE; + unsigned int inst_vc_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE; + unsigned int inst_vc_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE; + unsigned int inst_vc_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE; + unsigned int inst_vc_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE; + unsigned int inst_vc_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE; + } sq_instruction_cf_exec_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_2_t { + unsigned int opcode : SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE; + unsigned int inst_vc_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE; + unsigned int inst_vc_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE; + unsigned int inst_vc_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE; + unsigned int inst_vc_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE; + unsigned int inst_vc_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE; + unsigned int inst_vc_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE; + unsigned int inst_serial_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE; + unsigned int inst_type_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE; + unsigned int inst_serial_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE; + unsigned int inst_type_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE; + unsigned int inst_serial_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE; + unsigned int inst_type_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE; + unsigned int inst_serial_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE; + unsigned int inst_type_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE; + unsigned int inst_serial_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE; + unsigned int inst_type_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE; + unsigned int inst_serial_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE; + unsigned int inst_type_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE; + } sq_instruction_cf_exec_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_exec_2_t f; +} sq_instruction_cf_exec_2_u; + + +/* + * SQ_INSTRUCTION_CF_LOOP_0 struct + */ + +#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE 10 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE 6 +#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE 5 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE 11 + +#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT 0 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT 10 +#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT 16 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT 21 + +#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK 0x000003ff +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK 0x0000fc00 +#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK 0x001f0000 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK 0xffe00000 + +#define SQ_INSTRUCTION_CF_LOOP_0_MASK \ + (SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK | \ + SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) + +#define SQ_INSTRUCTION_CF_LOOP_0(address, reserved_0, loop_id, reserved_1) \ + ((address << SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT) | \ + (reserved_0 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT) | \ + (loop_id << SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT)) + +#define SQ_INSTRUCTION_CF_LOOP_0_GET_ADDRESS(sq_instruction_cf_loop_0) \ + ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_GET_RESERVED_0(sq_instruction_cf_loop_0) \ + ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_GET_LOOP_ID(sq_instruction_cf_loop_0) \ + ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_GET_RESERVED_1(sq_instruction_cf_loop_0) \ + ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT) + +#define SQ_INSTRUCTION_CF_LOOP_0_SET_ADDRESS(sq_instruction_cf_loop_0_reg, address) \ + sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_SET_RESERVED_0(sq_instruction_cf_loop_0_reg, reserved_0) \ + sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_SET_LOOP_ID(sq_instruction_cf_loop_0_reg, loop_id) \ + sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK) | (loop_id << SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_SET_RESERVED_1(sq_instruction_cf_loop_0_reg, reserved_1) \ + sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_0_t { + unsigned int address : SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE; + unsigned int loop_id : SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE; + } sq_instruction_cf_loop_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_0_t { + unsigned int reserved_1 : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE; + unsigned int loop_id : SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE; + } sq_instruction_cf_loop_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_loop_0_t f; +} sq_instruction_cf_loop_0_u; + + +/* + * SQ_INSTRUCTION_CF_LOOP_1 struct + */ + +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE 11 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE 4 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE 10 +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE 6 + +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT 0 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT 11 +#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT 12 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT 16 +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT 26 + +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK 0x000007ff +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK 0x0000f000 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK 0x03ff0000 +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK 0xfc000000 + +#define SQ_INSTRUCTION_CF_LOOP_1_MASK \ + (SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK | \ + SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) + +#define SQ_INSTRUCTION_CF_LOOP_1(reserved_0, address_mode, opcode, address, reserved_1) \ + ((reserved_0 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT) | \ + (address << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT)) + +#define SQ_INSTRUCTION_CF_LOOP_1_GET_RESERVED_0(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_GET_ADDRESS_MODE(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_GET_OPCODE(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_GET_ADDRESS(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_GET_RESERVED_1(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT) + +#define SQ_INSTRUCTION_CF_LOOP_1_SET_RESERVED_0(sq_instruction_cf_loop_1_reg, reserved_0) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_SET_ADDRESS_MODE(sq_instruction_cf_loop_1_reg, address_mode) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_SET_OPCODE(sq_instruction_cf_loop_1_reg, opcode) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_SET_ADDRESS(sq_instruction_cf_loop_1_reg, address) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_SET_RESERVED_1(sq_instruction_cf_loop_1_reg, reserved_1) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_1_t { + unsigned int reserved_0 : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE; + } sq_instruction_cf_loop_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_1_t { + unsigned int reserved_1 : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE; + } sq_instruction_cf_loop_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_loop_1_t f; +} sq_instruction_cf_loop_1_u; + + +/* + * SQ_INSTRUCTION_CF_LOOP_2 struct + */ + +#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE 5 +#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE 22 +#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE 4 + +#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT 0 +#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT 5 +#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT 27 +#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT 28 + +#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK 0x0000001f +#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK 0x07ffffe0 +#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK 0xf0000000 + +#define SQ_INSTRUCTION_CF_LOOP_2_MASK \ + (SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK | \ + SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) + +#define SQ_INSTRUCTION_CF_LOOP_2(loop_id, reserved, address_mode, opcode) \ + ((loop_id << SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT) | \ + (reserved << SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_CF_LOOP_2_GET_LOOP_ID(sq_instruction_cf_loop_2) \ + ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_GET_RESERVED(sq_instruction_cf_loop_2) \ + ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_GET_ADDRESS_MODE(sq_instruction_cf_loop_2) \ + ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_GET_OPCODE(sq_instruction_cf_loop_2) \ + ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_CF_LOOP_2_SET_LOOP_ID(sq_instruction_cf_loop_2_reg, loop_id) \ + sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK) | (loop_id << SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_SET_RESERVED(sq_instruction_cf_loop_2_reg, reserved) \ + sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_SET_ADDRESS_MODE(sq_instruction_cf_loop_2_reg, address_mode) \ + sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_SET_OPCODE(sq_instruction_cf_loop_2_reg, opcode) \ + sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_2_t { + unsigned int loop_id : SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE; + } sq_instruction_cf_loop_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_2_t { + unsigned int opcode : SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE; + unsigned int loop_id : SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE; + } sq_instruction_cf_loop_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_loop_2_t f; +} sq_instruction_cf_loop_2_u; + + +/* + * SQ_INSTRUCTION_CF_JMP_CALL_0 struct + */ + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE 10 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE 3 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE 17 + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT 0 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT 10 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT 13 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT 14 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT 15 + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK 0x000003ff +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK 0x00001c00 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK 0x00002000 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK 0x00004000 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK 0xffff8000 + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_MASK \ + (SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) + +#define SQ_INSTRUCTION_CF_JMP_CALL_0(address, reserved_0, force_call, predicated_jmp, reserved_1) \ + ((address << SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT) | \ + (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT) | \ + (force_call << SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT) | \ + (predicated_jmp << SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT)) + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_ADDRESS(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_RESERVED_0(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_FORCE_CALL(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_PREDICATED_JMP(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_RESERVED_1(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT) + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_ADDRESS(sq_instruction_cf_jmp_call_0_reg, address) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_RESERVED_0(sq_instruction_cf_jmp_call_0_reg, reserved_0) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_FORCE_CALL(sq_instruction_cf_jmp_call_0_reg, force_call) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK) | (force_call << SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_PREDICATED_JMP(sq_instruction_cf_jmp_call_0_reg, predicated_jmp) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK) | (predicated_jmp << SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_RESERVED_1(sq_instruction_cf_jmp_call_0_reg, reserved_1) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_0_t { + unsigned int address : SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE; + unsigned int force_call : SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE; + unsigned int predicated_jmp : SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE; + } sq_instruction_cf_jmp_call_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_0_t { + unsigned int reserved_1 : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE; + unsigned int predicated_jmp : SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE; + unsigned int force_call : SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE; + } sq_instruction_cf_jmp_call_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_jmp_call_0_t f; +} sq_instruction_cf_jmp_call_0_u; + + +/* + * SQ_INSTRUCTION_CF_JMP_CALL_1 struct + */ + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE 8 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE 4 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE 10 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE 3 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE 2 + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT 0 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT 2 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT 10 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT 11 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT 12 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT 16 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT 26 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT 29 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT 30 + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK 0x00000001 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK 0x00000002 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK 0x000003fc +#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK 0x00000400 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK 0x0000f000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK 0x03ff0000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK 0x1c000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK 0x20000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK 0xc0000000 + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_MASK \ + (SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) + +#define SQ_INSTRUCTION_CF_JMP_CALL_1(reserved_0, direction, bool_addr, condition, address_mode, opcode, address, reserved_1, force_call, reserved_2) \ + ((reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT) | \ + (direction << SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT) | \ + (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT) | \ + (condition << SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT) | \ + (address << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT) | \ + (force_call << SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT) | \ + (reserved_2 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT)) + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_0(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_DIRECTION(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_BOOL_ADDR(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_CONDITION(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_ADDRESS_MODE(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_OPCODE(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_ADDRESS(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_1(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_FORCE_CALL(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_2(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT) + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_0(sq_instruction_cf_jmp_call_1_reg, reserved_0) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_DIRECTION(sq_instruction_cf_jmp_call_1_reg, direction) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK) | (direction << SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_BOOL_ADDR(sq_instruction_cf_jmp_call_1_reg, bool_addr) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_CONDITION(sq_instruction_cf_jmp_call_1_reg, condition) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_ADDRESS_MODE(sq_instruction_cf_jmp_call_1_reg, address_mode) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_OPCODE(sq_instruction_cf_jmp_call_1_reg, opcode) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_ADDRESS(sq_instruction_cf_jmp_call_1_reg, address) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_1(sq_instruction_cf_jmp_call_1_reg, reserved_1) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_FORCE_CALL(sq_instruction_cf_jmp_call_1_reg, force_call) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK) | (force_call << SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_2(sq_instruction_cf_jmp_call_1_reg, reserved_2) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) | (reserved_2 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_1_t { + unsigned int reserved_0 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE; + unsigned int direction : SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE; + unsigned int force_call : SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE; + unsigned int reserved_2 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE; + } sq_instruction_cf_jmp_call_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_1_t { + unsigned int reserved_2 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE; + unsigned int force_call : SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE; + unsigned int direction : SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE; + } sq_instruction_cf_jmp_call_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_jmp_call_1_t f; +} sq_instruction_cf_jmp_call_1_u; + + +/* + * SQ_INSTRUCTION_CF_JMP_CALL_2 struct + */ + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE 17 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE 8 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE 4 + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT 0 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT 17 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT 18 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT 26 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT 27 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT 28 + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK 0x0001ffff +#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK 0x00020000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK 0x03fc0000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK 0x04000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK 0xf0000000 + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_MASK \ + (SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) + +#define SQ_INSTRUCTION_CF_JMP_CALL_2(reserved, direction, bool_addr, condition, address_mode, opcode) \ + ((reserved << SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT) | \ + (direction << SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT) | \ + (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT) | \ + (condition << SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_RESERVED(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_DIRECTION(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_BOOL_ADDR(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_CONDITION(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_ADDRESS_MODE(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_OPCODE(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_RESERVED(sq_instruction_cf_jmp_call_2_reg, reserved) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_DIRECTION(sq_instruction_cf_jmp_call_2_reg, direction) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK) | (direction << SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_BOOL_ADDR(sq_instruction_cf_jmp_call_2_reg, bool_addr) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_CONDITION(sq_instruction_cf_jmp_call_2_reg, condition) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_ADDRESS_MODE(sq_instruction_cf_jmp_call_2_reg, address_mode) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_OPCODE(sq_instruction_cf_jmp_call_2_reg, opcode) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_2_t { + unsigned int reserved : SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE; + unsigned int direction : SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE; + } sq_instruction_cf_jmp_call_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_2_t { + unsigned int opcode : SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE; + unsigned int direction : SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE; + } sq_instruction_cf_jmp_call_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_jmp_call_2_t f; +} sq_instruction_cf_jmp_call_2_u; + + +/* + * SQ_INSTRUCTION_CF_ALLOC_0 struct + */ + +#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE 4 +#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE 28 + +#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT 0 +#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT 4 + +#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK 0x0000000f +#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK 0xfffffff0 + +#define SQ_INSTRUCTION_CF_ALLOC_0_MASK \ + (SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) + +#define SQ_INSTRUCTION_CF_ALLOC_0(size, reserved) \ + ((size << SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT) | \ + (reserved << SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT)) + +#define SQ_INSTRUCTION_CF_ALLOC_0_GET_SIZE(sq_instruction_cf_alloc_0) \ + ((sq_instruction_cf_alloc_0 & SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_0_GET_RESERVED(sq_instruction_cf_alloc_0) \ + ((sq_instruction_cf_alloc_0 & SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) >> SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT) + +#define SQ_INSTRUCTION_CF_ALLOC_0_SET_SIZE(sq_instruction_cf_alloc_0_reg, size) \ + sq_instruction_cf_alloc_0_reg = (sq_instruction_cf_alloc_0_reg & ~SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK) | (size << SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_0_SET_RESERVED(sq_instruction_cf_alloc_0_reg, reserved) \ + sq_instruction_cf_alloc_0_reg = (sq_instruction_cf_alloc_0_reg & ~SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_0_t { + unsigned int size : SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE; + } sq_instruction_cf_alloc_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_0_t { + unsigned int reserved : SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE; + unsigned int size : SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE; + } sq_instruction_cf_alloc_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_alloc_0_t f; +} sq_instruction_cf_alloc_0_u; + + +/* + * SQ_INSTRUCTION_CF_ALLOC_1 struct + */ + +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE 8 +#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE 1 +#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE 2 +#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE 4 +#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE 4 +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE 12 + +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT 0 +#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT 8 +#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT 9 +#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT 11 +#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT 12 +#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT 16 +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT 20 + +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK 0x000000ff +#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK 0x00000100 +#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK 0x00000600 +#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK 0x0000f000 +#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK 0x000f0000 +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK 0xfff00000 + +#define SQ_INSTRUCTION_CF_ALLOC_1_MASK \ + (SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) + +#define SQ_INSTRUCTION_CF_ALLOC_1(reserved_0, no_serial, buffer_select, alloc_mode, opcode, size, reserved_1) \ + ((reserved_0 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT) | \ + (no_serial << SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT) | \ + (buffer_select << SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT) | \ + (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT) | \ + (size << SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT)) + +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_RESERVED_0(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_NO_SERIAL(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_BUFFER_SELECT(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_ALLOC_MODE(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_OPCODE(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_SIZE(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_RESERVED_1(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT) + +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_RESERVED_0(sq_instruction_cf_alloc_1_reg, reserved_0) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_NO_SERIAL(sq_instruction_cf_alloc_1_reg, no_serial) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK) | (no_serial << SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_BUFFER_SELECT(sq_instruction_cf_alloc_1_reg, buffer_select) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK) | (buffer_select << SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_ALLOC_MODE(sq_instruction_cf_alloc_1_reg, alloc_mode) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK) | (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_OPCODE(sq_instruction_cf_alloc_1_reg, opcode) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_SIZE(sq_instruction_cf_alloc_1_reg, size) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK) | (size << SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_RESERVED_1(sq_instruction_cf_alloc_1_reg, reserved_1) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_1_t { + unsigned int reserved_0 : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE; + unsigned int no_serial : SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE; + unsigned int buffer_select : SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE; + unsigned int alloc_mode : SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE; + unsigned int size : SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE; + } sq_instruction_cf_alloc_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_1_t { + unsigned int reserved_1 : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE; + unsigned int size : SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE; + unsigned int alloc_mode : SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE; + unsigned int buffer_select : SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE; + unsigned int no_serial : SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE; + } sq_instruction_cf_alloc_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_alloc_1_t f; +} sq_instruction_cf_alloc_1_u; + + +/* + * SQ_INSTRUCTION_CF_ALLOC_2 struct + */ + +#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE 24 +#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE 1 +#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE 2 +#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE 4 + +#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT 0 +#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT 24 +#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT 25 +#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT 27 +#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT 28 + +#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK 0x00ffffff +#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK 0x01000000 +#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK 0x06000000 +#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK 0xf0000000 + +#define SQ_INSTRUCTION_CF_ALLOC_2_MASK \ + (SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) + +#define SQ_INSTRUCTION_CF_ALLOC_2(reserved, no_serial, buffer_select, alloc_mode, opcode) \ + ((reserved << SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT) | \ + (no_serial << SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT) | \ + (buffer_select << SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT) | \ + (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_RESERVED(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_NO_SERIAL(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_BUFFER_SELECT(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_ALLOC_MODE(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_OPCODE(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_RESERVED(sq_instruction_cf_alloc_2_reg, reserved) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_NO_SERIAL(sq_instruction_cf_alloc_2_reg, no_serial) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK) | (no_serial << SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_BUFFER_SELECT(sq_instruction_cf_alloc_2_reg, buffer_select) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK) | (buffer_select << SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_ALLOC_MODE(sq_instruction_cf_alloc_2_reg, alloc_mode) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK) | (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_OPCODE(sq_instruction_cf_alloc_2_reg, opcode) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_2_t { + unsigned int reserved : SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE; + unsigned int no_serial : SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE; + unsigned int buffer_select : SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE; + unsigned int alloc_mode : SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE; + } sq_instruction_cf_alloc_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_2_t { + unsigned int opcode : SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE; + unsigned int alloc_mode : SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE; + unsigned int buffer_select : SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE; + unsigned int no_serial : SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE; + } sq_instruction_cf_alloc_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_alloc_2_t f; +} sq_instruction_cf_alloc_2_u; + + +/* + * SQ_INSTRUCTION_TFETCH_0 struct + */ + +#define SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE 6 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE 6 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE 2 + +#define SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT 0 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT 5 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT 11 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT 12 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT 18 +#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT 19 +#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT 20 +#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT 25 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT 26 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT 28 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT 30 + +#define SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK 0x0000001f +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK 0x000007e0 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK 0x00000800 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK 0x0003f000 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK 0x00040000 +#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK 0x00080000 +#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK 0x01f00000 +#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK 0x02000000 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK 0x0c000000 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK 0x30000000 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK 0xc0000000 + +#define SQ_INSTRUCTION_TFETCH_0_MASK \ + (SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK | \ + SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK | \ + SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK | \ + SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK | \ + SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK | \ + SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) + +#define SQ_INSTRUCTION_TFETCH_0(opcode, src_gpr, src_gpr_am, dst_gpr, dst_gpr_am, fetch_valid_only, const_index, tx_coord_denorm, src_sel_x, src_sel_y, src_sel_z) \ + ((opcode << SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT) | \ + (src_gpr << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT) | \ + (src_gpr_am << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT) | \ + (dst_gpr << SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT) | \ + (dst_gpr_am << SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT) | \ + (fetch_valid_only << SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT) | \ + (const_index << SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT) | \ + (tx_coord_denorm << SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT) | \ + (src_sel_x << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT) | \ + (src_sel_y << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT) | \ + (src_sel_z << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT)) + +#define SQ_INSTRUCTION_TFETCH_0_GET_OPCODE(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK) >> SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_GPR(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_GPR_AM(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_DST_GPR(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK) >> SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_DST_GPR_AM(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK) >> SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_FETCH_VALID_ONLY(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK) >> SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_CONST_INDEX(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK) >> SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_TX_COORD_DENORM(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK) >> SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_X(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_Y(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_Z(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT) + +#define SQ_INSTRUCTION_TFETCH_0_SET_OPCODE(sq_instruction_tfetch_0_reg, opcode) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_GPR(sq_instruction_tfetch_0_reg, src_gpr) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK) | (src_gpr << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_GPR_AM(sq_instruction_tfetch_0_reg, src_gpr_am) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK) | (src_gpr_am << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_DST_GPR(sq_instruction_tfetch_0_reg, dst_gpr) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK) | (dst_gpr << SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_DST_GPR_AM(sq_instruction_tfetch_0_reg, dst_gpr_am) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK) | (dst_gpr_am << SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_FETCH_VALID_ONLY(sq_instruction_tfetch_0_reg, fetch_valid_only) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK) | (fetch_valid_only << SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_CONST_INDEX(sq_instruction_tfetch_0_reg, const_index) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK) | (const_index << SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_TX_COORD_DENORM(sq_instruction_tfetch_0_reg, tx_coord_denorm) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK) | (tx_coord_denorm << SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_X(sq_instruction_tfetch_0_reg, src_sel_x) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK) | (src_sel_x << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_Y(sq_instruction_tfetch_0_reg, src_sel_y) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK) | (src_sel_y << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_Z(sq_instruction_tfetch_0_reg, src_sel_z) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) | (src_sel_z << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_0_t { + unsigned int opcode : SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE; + unsigned int src_gpr : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE; + unsigned int src_gpr_am : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE; + unsigned int dst_gpr : SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE; + unsigned int dst_gpr_am : SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE; + unsigned int fetch_valid_only : SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE; + unsigned int const_index : SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE; + unsigned int tx_coord_denorm : SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE; + unsigned int src_sel_x : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE; + unsigned int src_sel_y : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE; + unsigned int src_sel_z : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE; + } sq_instruction_tfetch_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_0_t { + unsigned int src_sel_z : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE; + unsigned int src_sel_y : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE; + unsigned int src_sel_x : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE; + unsigned int tx_coord_denorm : SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE; + unsigned int const_index : SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE; + unsigned int fetch_valid_only : SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE; + unsigned int dst_gpr_am : SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE; + unsigned int dst_gpr : SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE; + unsigned int src_gpr_am : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE; + unsigned int src_gpr : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE; + unsigned int opcode : SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE; + } sq_instruction_tfetch_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_tfetch_0_t f; +} sq_instruction_tfetch_0_u; + + +/* + * SQ_INSTRUCTION_TFETCH_1 struct + */ + +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE 1 + +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT 0 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT 3 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT 6 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT 9 +#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT 12 +#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT 14 +#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT 16 +#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT 18 +#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT 21 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT 24 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT 26 +#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT 28 +#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT 29 +#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT 31 + +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK 0x00000007 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK 0x00000038 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK 0x000001c0 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK 0x00000e00 +#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK 0x00003000 +#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK 0x0000c000 +#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK 0x00030000 +#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK 0x001c0000 +#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK 0x00e00000 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK 0x03000000 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK 0x0c000000 +#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK 0x10000000 +#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK 0x60000000 +#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK 0x80000000 + +#define SQ_INSTRUCTION_TFETCH_1_MASK \ + (SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK | \ + SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK | \ + SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK | \ + SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK | \ + SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK | \ + SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK | \ + SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) + +#define SQ_INSTRUCTION_TFETCH_1(dst_sel_x, dst_sel_y, dst_sel_z, dst_sel_w, mag_filter, min_filter, mip_filter, aniso_filter, arbitrary_filter, vol_mag_filter, vol_min_filter, use_comp_lod, use_reg_lod, pred_select) \ + ((dst_sel_x << SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT) | \ + (dst_sel_y << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT) | \ + (dst_sel_z << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT) | \ + (dst_sel_w << SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT) | \ + (mag_filter << SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT) | \ + (min_filter << SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT) | \ + (mip_filter << SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT) | \ + (aniso_filter << SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT) | \ + (arbitrary_filter << SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT) | \ + (vol_mag_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT) | \ + (vol_min_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT) | \ + (use_comp_lod << SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT) | \ + (use_reg_lod << SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT) | \ + (pred_select << SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT)) + +#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_X(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_Y(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_Z(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_W(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_MAG_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_MIN_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_MIP_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_ANISO_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_ARBITRARY_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_VOL_MAG_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_VOL_MIN_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_USE_COMP_LOD(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK) >> SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_USE_REG_LOD(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK) >> SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_PRED_SELECT(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT) + +#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_X(sq_instruction_tfetch_1_reg, dst_sel_x) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK) | (dst_sel_x << SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_Y(sq_instruction_tfetch_1_reg, dst_sel_y) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK) | (dst_sel_y << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_Z(sq_instruction_tfetch_1_reg, dst_sel_z) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK) | (dst_sel_z << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_W(sq_instruction_tfetch_1_reg, dst_sel_w) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK) | (dst_sel_w << SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_MAG_FILTER(sq_instruction_tfetch_1_reg, mag_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK) | (mag_filter << SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_MIN_FILTER(sq_instruction_tfetch_1_reg, min_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK) | (min_filter << SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_MIP_FILTER(sq_instruction_tfetch_1_reg, mip_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK) | (mip_filter << SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_ANISO_FILTER(sq_instruction_tfetch_1_reg, aniso_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK) | (aniso_filter << SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_ARBITRARY_FILTER(sq_instruction_tfetch_1_reg, arbitrary_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK) | (arbitrary_filter << SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_VOL_MAG_FILTER(sq_instruction_tfetch_1_reg, vol_mag_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK) | (vol_mag_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_VOL_MIN_FILTER(sq_instruction_tfetch_1_reg, vol_min_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK) | (vol_min_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_USE_COMP_LOD(sq_instruction_tfetch_1_reg, use_comp_lod) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK) | (use_comp_lod << SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_USE_REG_LOD(sq_instruction_tfetch_1_reg, use_reg_lod) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK) | (use_reg_lod << SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_PRED_SELECT(sq_instruction_tfetch_1_reg, pred_select) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_1_t { + unsigned int dst_sel_x : SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE; + unsigned int dst_sel_y : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE; + unsigned int dst_sel_z : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE; + unsigned int dst_sel_w : SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE; + unsigned int mag_filter : SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE; + unsigned int min_filter : SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE; + unsigned int mip_filter : SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE; + unsigned int aniso_filter : SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE; + unsigned int arbitrary_filter : SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE; + unsigned int vol_mag_filter : SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE; + unsigned int vol_min_filter : SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE; + unsigned int use_comp_lod : SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE; + unsigned int use_reg_lod : SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE; + unsigned int pred_select : SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE; + } sq_instruction_tfetch_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_1_t { + unsigned int pred_select : SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE; + unsigned int use_reg_lod : SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE; + unsigned int use_comp_lod : SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE; + unsigned int vol_min_filter : SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE; + unsigned int vol_mag_filter : SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE; + unsigned int arbitrary_filter : SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE; + unsigned int aniso_filter : SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE; + unsigned int mip_filter : SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE; + unsigned int min_filter : SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE; + unsigned int mag_filter : SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE; + unsigned int dst_sel_w : SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE; + unsigned int dst_sel_z : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE; + unsigned int dst_sel_y : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE; + unsigned int dst_sel_x : SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE; + } sq_instruction_tfetch_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_tfetch_1_t f; +} sq_instruction_tfetch_1_u; + + +/* + * SQ_INSTRUCTION_TFETCH_2 struct + */ + +#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE 7 +#define SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE 7 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE 1 + +#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT 0 +#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT 1 +#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT 2 +#define SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT 9 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT 16 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT 21 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT 26 +#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT 31 + +#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK 0x00000001 +#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK 0x00000002 +#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK 0x000001fc +#define SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK 0x0000fe00 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK 0x001f0000 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK 0x03e00000 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK 0x7c000000 +#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK 0x80000000 + +#define SQ_INSTRUCTION_TFETCH_2_MASK \ + (SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK | \ + SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK | \ + SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK | \ + SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK | \ + SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK | \ + SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK | \ + SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK | \ + SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) + +#define SQ_INSTRUCTION_TFETCH_2(use_reg_gradients, sample_location, lod_bias, unused, offset_x, offset_y, offset_z, pred_condition) \ + ((use_reg_gradients << SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT) | \ + (sample_location << SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT) | \ + (lod_bias << SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT) | \ + (unused << SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT) | \ + (offset_x << SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT) | \ + (offset_y << SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT) | \ + (offset_z << SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT) | \ + (pred_condition << SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT)) + +#define SQ_INSTRUCTION_TFETCH_2_GET_USE_REG_GRADIENTS(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK) >> SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_SAMPLE_LOCATION(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK) >> SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_LOD_BIAS(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK) >> SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_UNUSED(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK) >> SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_X(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_Y(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_Z(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_PRED_CONDITION(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) >> SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT) + +#define SQ_INSTRUCTION_TFETCH_2_SET_USE_REG_GRADIENTS(sq_instruction_tfetch_2_reg, use_reg_gradients) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK) | (use_reg_gradients << SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_SAMPLE_LOCATION(sq_instruction_tfetch_2_reg, sample_location) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK) | (sample_location << SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_LOD_BIAS(sq_instruction_tfetch_2_reg, lod_bias) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK) | (lod_bias << SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_UNUSED(sq_instruction_tfetch_2_reg, unused) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK) | (unused << SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_X(sq_instruction_tfetch_2_reg, offset_x) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK) | (offset_x << SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_Y(sq_instruction_tfetch_2_reg, offset_y) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK) | (offset_y << SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_Z(sq_instruction_tfetch_2_reg, offset_z) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK) | (offset_z << SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_PRED_CONDITION(sq_instruction_tfetch_2_reg, pred_condition) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) | (pred_condition << SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_2_t { + unsigned int use_reg_gradients : SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE; + unsigned int sample_location : SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE; + unsigned int lod_bias : SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE; + unsigned int unused : SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE; + unsigned int offset_x : SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE; + unsigned int offset_y : SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE; + unsigned int offset_z : SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE; + unsigned int pred_condition : SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE; + } sq_instruction_tfetch_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_2_t { + unsigned int pred_condition : SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE; + unsigned int offset_z : SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE; + unsigned int offset_y : SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE; + unsigned int offset_x : SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE; + unsigned int unused : SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE; + unsigned int lod_bias : SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE; + unsigned int sample_location : SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE; + unsigned int use_reg_gradients : SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE; + } sq_instruction_tfetch_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_tfetch_2_t f; +} sq_instruction_tfetch_2_u; + + +/* + * SQ_INSTRUCTION_VFETCH_0 struct + */ + +#define SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE 5 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE 6 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE 6 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE 5 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE 2 +#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE 2 + +#define SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT 0 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT 5 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT 11 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT 12 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT 18 +#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT 19 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT 20 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT 25 +#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT 30 + +#define SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK 0x0000001f +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK 0x000007e0 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK 0x00000800 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK 0x0003f000 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK 0x00040000 +#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK 0x00080000 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK 0x01f00000 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK 0x06000000 +#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK 0xc0000000 + +#define SQ_INSTRUCTION_VFETCH_0_MASK \ + (SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK | \ + SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK | \ + SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK | \ + SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK | \ + SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK | \ + SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK | \ + SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK | \ + SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK | \ + SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) + +#define SQ_INSTRUCTION_VFETCH_0(opcode, src_gpr, src_gpr_am, dst_gpr, dst_gpr_am, must_be_one, const_index, const_index_sel, src_sel) \ + ((opcode << SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT) | \ + (src_gpr << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT) | \ + (src_gpr_am << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT) | \ + (dst_gpr << SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT) | \ + (dst_gpr_am << SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT) | \ + (must_be_one << SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT) | \ + (const_index << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT) | \ + (const_index_sel << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT) | \ + (src_sel << SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT)) + +#define SQ_INSTRUCTION_VFETCH_0_GET_OPCODE(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK) >> SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_GPR(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_GPR_AM(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_DST_GPR(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK) >> SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_DST_GPR_AM(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK) >> SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_MUST_BE_ONE(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK) >> SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_CONST_INDEX(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK) >> SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_CONST_INDEX_SEL(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK) >> SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_SEL(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT) + +#define SQ_INSTRUCTION_VFETCH_0_SET_OPCODE(sq_instruction_vfetch_0_reg, opcode) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_GPR(sq_instruction_vfetch_0_reg, src_gpr) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK) | (src_gpr << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_GPR_AM(sq_instruction_vfetch_0_reg, src_gpr_am) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK) | (src_gpr_am << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_DST_GPR(sq_instruction_vfetch_0_reg, dst_gpr) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK) | (dst_gpr << SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_DST_GPR_AM(sq_instruction_vfetch_0_reg, dst_gpr_am) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK) | (dst_gpr_am << SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_MUST_BE_ONE(sq_instruction_vfetch_0_reg, must_be_one) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK) | (must_be_one << SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_CONST_INDEX(sq_instruction_vfetch_0_reg, const_index) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK) | (const_index << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_CONST_INDEX_SEL(sq_instruction_vfetch_0_reg, const_index_sel) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK) | (const_index_sel << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_SEL(sq_instruction_vfetch_0_reg, src_sel) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) | (src_sel << SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_0_t { + unsigned int opcode : SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE; + unsigned int src_gpr : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE; + unsigned int src_gpr_am : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE; + unsigned int dst_gpr : SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE; + unsigned int dst_gpr_am : SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE; + unsigned int must_be_one : SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE; + unsigned int const_index : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE; + unsigned int const_index_sel : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE; + unsigned int : 3; + unsigned int src_sel : SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE; + } sq_instruction_vfetch_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_0_t { + unsigned int src_sel : SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE; + unsigned int : 3; + unsigned int const_index_sel : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE; + unsigned int const_index : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE; + unsigned int must_be_one : SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE; + unsigned int dst_gpr_am : SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE; + unsigned int dst_gpr : SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE; + unsigned int src_gpr_am : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE; + unsigned int src_gpr : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE; + unsigned int opcode : SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE; + } sq_instruction_vfetch_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_vfetch_0_t f; +} sq_instruction_vfetch_0_u; + + +/* + * SQ_INSTRUCTION_VFETCH_1 struct + */ + +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE 3 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE 3 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE 3 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE 3 +#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE 6 +#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE 7 +#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE 1 + +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT 0 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT 3 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT 6 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT 9 +#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT 12 +#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT 13 +#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT 14 +#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT 16 +#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT 23 +#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT 31 + +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK 0x00000007 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK 0x00000038 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK 0x000001c0 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK 0x00000e00 +#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK 0x00001000 +#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK 0x00002000 +#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK 0x00004000 +#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK 0x003f0000 +#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK 0x3f800000 +#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK 0x80000000 + +#define SQ_INSTRUCTION_VFETCH_1_MASK \ + (SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK | \ + SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK | \ + SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK | \ + SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK | \ + SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK | \ + SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK | \ + SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK | \ + SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK | \ + SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK | \ + SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) + +#define SQ_INSTRUCTION_VFETCH_1(dst_sel_x, dst_sel_y, dst_sel_z, dst_sel_w, format_comp_all, num_format_all, signed_rf_mode_all, data_format, exp_adjust_all, pred_select) \ + ((dst_sel_x << SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT) | \ + (dst_sel_y << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT) | \ + (dst_sel_z << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT) | \ + (dst_sel_w << SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT) | \ + (format_comp_all << SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT) | \ + (num_format_all << SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT) | \ + (signed_rf_mode_all << SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT) | \ + (data_format << SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT) | \ + (exp_adjust_all << SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT) | \ + (pred_select << SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT)) + +#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_X(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_Y(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_Z(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_W(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_FORMAT_COMP_ALL(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_NUM_FORMAT_ALL(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_SIGNED_RF_MODE_ALL(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_DATA_FORMAT(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK) >> SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_EXP_ADJUST_ALL(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_PRED_SELECT(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT) + +#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_X(sq_instruction_vfetch_1_reg, dst_sel_x) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK) | (dst_sel_x << SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_Y(sq_instruction_vfetch_1_reg, dst_sel_y) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK) | (dst_sel_y << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_Z(sq_instruction_vfetch_1_reg, dst_sel_z) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK) | (dst_sel_z << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_W(sq_instruction_vfetch_1_reg, dst_sel_w) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK) | (dst_sel_w << SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_FORMAT_COMP_ALL(sq_instruction_vfetch_1_reg, format_comp_all) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK) | (format_comp_all << SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_NUM_FORMAT_ALL(sq_instruction_vfetch_1_reg, num_format_all) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK) | (num_format_all << SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_SIGNED_RF_MODE_ALL(sq_instruction_vfetch_1_reg, signed_rf_mode_all) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK) | (signed_rf_mode_all << SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_DATA_FORMAT(sq_instruction_vfetch_1_reg, data_format) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK) | (data_format << SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_EXP_ADJUST_ALL(sq_instruction_vfetch_1_reg, exp_adjust_all) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK) | (exp_adjust_all << SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_PRED_SELECT(sq_instruction_vfetch_1_reg, pred_select) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_1_t { + unsigned int dst_sel_x : SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE; + unsigned int dst_sel_y : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE; + unsigned int dst_sel_z : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE; + unsigned int dst_sel_w : SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE; + unsigned int format_comp_all : SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE; + unsigned int num_format_all : SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE; + unsigned int signed_rf_mode_all : SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE; + unsigned int : 1; + unsigned int data_format : SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE; + unsigned int : 1; + unsigned int exp_adjust_all : SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE; + unsigned int : 1; + unsigned int pred_select : SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE; + } sq_instruction_vfetch_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_1_t { + unsigned int pred_select : SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE; + unsigned int : 1; + unsigned int exp_adjust_all : SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE; + unsigned int : 1; + unsigned int data_format : SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE; + unsigned int : 1; + unsigned int signed_rf_mode_all : SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE; + unsigned int num_format_all : SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE; + unsigned int format_comp_all : SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE; + unsigned int dst_sel_w : SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE; + unsigned int dst_sel_z : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE; + unsigned int dst_sel_y : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE; + unsigned int dst_sel_x : SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE; + } sq_instruction_vfetch_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_vfetch_1_t f; +} sq_instruction_vfetch_1_u; + + +/* + * SQ_INSTRUCTION_VFETCH_2 struct + */ + +#define SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE 8 +#define SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE 8 +#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE 1 + +#define SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT 0 +#define SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT 16 +#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT 31 + +#define SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK 0x000000ff +#define SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK 0x00ff0000 +#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK 0x80000000 + +#define SQ_INSTRUCTION_VFETCH_2_MASK \ + (SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK | \ + SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK | \ + SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) + +#define SQ_INSTRUCTION_VFETCH_2(stride, offset, pred_condition) \ + ((stride << SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT) | \ + (offset << SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT) | \ + (pred_condition << SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT)) + +#define SQ_INSTRUCTION_VFETCH_2_GET_STRIDE(sq_instruction_vfetch_2) \ + ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK) >> SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_2_GET_OFFSET(sq_instruction_vfetch_2) \ + ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK) >> SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT) +#define SQ_INSTRUCTION_VFETCH_2_GET_PRED_CONDITION(sq_instruction_vfetch_2) \ + ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) >> SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT) + +#define SQ_INSTRUCTION_VFETCH_2_SET_STRIDE(sq_instruction_vfetch_2_reg, stride) \ + sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK) | (stride << SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_2_SET_OFFSET(sq_instruction_vfetch_2_reg, offset) \ + sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK) | (offset << SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT) +#define SQ_INSTRUCTION_VFETCH_2_SET_PRED_CONDITION(sq_instruction_vfetch_2_reg, pred_condition) \ + sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) | (pred_condition << SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_2_t { + unsigned int stride : SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE; + unsigned int : 8; + unsigned int offset : SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE; + unsigned int : 7; + unsigned int pred_condition : SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE; + } sq_instruction_vfetch_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_2_t { + unsigned int pred_condition : SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE; + unsigned int : 7; + unsigned int offset : SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE; + unsigned int : 8; + unsigned int stride : SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE; + } sq_instruction_vfetch_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_vfetch_2_t f; +} sq_instruction_vfetch_2_u; + + +/* + * SQ_CONSTANT_0 struct + */ + +#define SQ_CONSTANT_0_RED_SIZE 32 + +#define SQ_CONSTANT_0_RED_SHIFT 0 + +#define SQ_CONSTANT_0_RED_MASK 0xffffffff + +#define SQ_CONSTANT_0_MASK \ + (SQ_CONSTANT_0_RED_MASK) + +#define SQ_CONSTANT_0(red) \ + ((red << SQ_CONSTANT_0_RED_SHIFT)) + +#define SQ_CONSTANT_0_GET_RED(sq_constant_0) \ + ((sq_constant_0 & SQ_CONSTANT_0_RED_MASK) >> SQ_CONSTANT_0_RED_SHIFT) + +#define SQ_CONSTANT_0_SET_RED(sq_constant_0_reg, red) \ + sq_constant_0_reg = (sq_constant_0_reg & ~SQ_CONSTANT_0_RED_MASK) | (red << SQ_CONSTANT_0_RED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_0_t { + unsigned int red : SQ_CONSTANT_0_RED_SIZE; + } sq_constant_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_0_t { + unsigned int red : SQ_CONSTANT_0_RED_SIZE; + } sq_constant_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_0_t f; +} sq_constant_0_u; + + +/* + * SQ_CONSTANT_1 struct + */ + +#define SQ_CONSTANT_1_GREEN_SIZE 32 + +#define SQ_CONSTANT_1_GREEN_SHIFT 0 + +#define SQ_CONSTANT_1_GREEN_MASK 0xffffffff + +#define SQ_CONSTANT_1_MASK \ + (SQ_CONSTANT_1_GREEN_MASK) + +#define SQ_CONSTANT_1(green) \ + ((green << SQ_CONSTANT_1_GREEN_SHIFT)) + +#define SQ_CONSTANT_1_GET_GREEN(sq_constant_1) \ + ((sq_constant_1 & SQ_CONSTANT_1_GREEN_MASK) >> SQ_CONSTANT_1_GREEN_SHIFT) + +#define SQ_CONSTANT_1_SET_GREEN(sq_constant_1_reg, green) \ + sq_constant_1_reg = (sq_constant_1_reg & ~SQ_CONSTANT_1_GREEN_MASK) | (green << SQ_CONSTANT_1_GREEN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_1_t { + unsigned int green : SQ_CONSTANT_1_GREEN_SIZE; + } sq_constant_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_1_t { + unsigned int green : SQ_CONSTANT_1_GREEN_SIZE; + } sq_constant_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_1_t f; +} sq_constant_1_u; + + +/* + * SQ_CONSTANT_2 struct + */ + +#define SQ_CONSTANT_2_BLUE_SIZE 32 + +#define SQ_CONSTANT_2_BLUE_SHIFT 0 + +#define SQ_CONSTANT_2_BLUE_MASK 0xffffffff + +#define SQ_CONSTANT_2_MASK \ + (SQ_CONSTANT_2_BLUE_MASK) + +#define SQ_CONSTANT_2(blue) \ + ((blue << SQ_CONSTANT_2_BLUE_SHIFT)) + +#define SQ_CONSTANT_2_GET_BLUE(sq_constant_2) \ + ((sq_constant_2 & SQ_CONSTANT_2_BLUE_MASK) >> SQ_CONSTANT_2_BLUE_SHIFT) + +#define SQ_CONSTANT_2_SET_BLUE(sq_constant_2_reg, blue) \ + sq_constant_2_reg = (sq_constant_2_reg & ~SQ_CONSTANT_2_BLUE_MASK) | (blue << SQ_CONSTANT_2_BLUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_2_t { + unsigned int blue : SQ_CONSTANT_2_BLUE_SIZE; + } sq_constant_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_2_t { + unsigned int blue : SQ_CONSTANT_2_BLUE_SIZE; + } sq_constant_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_2_t f; +} sq_constant_2_u; + + +/* + * SQ_CONSTANT_3 struct + */ + +#define SQ_CONSTANT_3_ALPHA_SIZE 32 + +#define SQ_CONSTANT_3_ALPHA_SHIFT 0 + +#define SQ_CONSTANT_3_ALPHA_MASK 0xffffffff + +#define SQ_CONSTANT_3_MASK \ + (SQ_CONSTANT_3_ALPHA_MASK) + +#define SQ_CONSTANT_3(alpha) \ + ((alpha << SQ_CONSTANT_3_ALPHA_SHIFT)) + +#define SQ_CONSTANT_3_GET_ALPHA(sq_constant_3) \ + ((sq_constant_3 & SQ_CONSTANT_3_ALPHA_MASK) >> SQ_CONSTANT_3_ALPHA_SHIFT) + +#define SQ_CONSTANT_3_SET_ALPHA(sq_constant_3_reg, alpha) \ + sq_constant_3_reg = (sq_constant_3_reg & ~SQ_CONSTANT_3_ALPHA_MASK) | (alpha << SQ_CONSTANT_3_ALPHA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_3_t { + unsigned int alpha : SQ_CONSTANT_3_ALPHA_SIZE; + } sq_constant_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_3_t { + unsigned int alpha : SQ_CONSTANT_3_ALPHA_SIZE; + } sq_constant_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_3_t f; +} sq_constant_3_u; + + +/* + * SQ_FETCH_0 struct + */ + +#define SQ_FETCH_0_VALUE_SIZE 32 + +#define SQ_FETCH_0_VALUE_SHIFT 0 + +#define SQ_FETCH_0_VALUE_MASK 0xffffffff + +#define SQ_FETCH_0_MASK \ + (SQ_FETCH_0_VALUE_MASK) + +#define SQ_FETCH_0(value) \ + ((value << SQ_FETCH_0_VALUE_SHIFT)) + +#define SQ_FETCH_0_GET_VALUE(sq_fetch_0) \ + ((sq_fetch_0 & SQ_FETCH_0_VALUE_MASK) >> SQ_FETCH_0_VALUE_SHIFT) + +#define SQ_FETCH_0_SET_VALUE(sq_fetch_0_reg, value) \ + sq_fetch_0_reg = (sq_fetch_0_reg & ~SQ_FETCH_0_VALUE_MASK) | (value << SQ_FETCH_0_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_0_t { + unsigned int value : SQ_FETCH_0_VALUE_SIZE; + } sq_fetch_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_0_t { + unsigned int value : SQ_FETCH_0_VALUE_SIZE; + } sq_fetch_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_0_t f; +} sq_fetch_0_u; + + +/* + * SQ_FETCH_1 struct + */ + +#define SQ_FETCH_1_VALUE_SIZE 32 + +#define SQ_FETCH_1_VALUE_SHIFT 0 + +#define SQ_FETCH_1_VALUE_MASK 0xffffffff + +#define SQ_FETCH_1_MASK \ + (SQ_FETCH_1_VALUE_MASK) + +#define SQ_FETCH_1(value) \ + ((value << SQ_FETCH_1_VALUE_SHIFT)) + +#define SQ_FETCH_1_GET_VALUE(sq_fetch_1) \ + ((sq_fetch_1 & SQ_FETCH_1_VALUE_MASK) >> SQ_FETCH_1_VALUE_SHIFT) + +#define SQ_FETCH_1_SET_VALUE(sq_fetch_1_reg, value) \ + sq_fetch_1_reg = (sq_fetch_1_reg & ~SQ_FETCH_1_VALUE_MASK) | (value << SQ_FETCH_1_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_1_t { + unsigned int value : SQ_FETCH_1_VALUE_SIZE; + } sq_fetch_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_1_t { + unsigned int value : SQ_FETCH_1_VALUE_SIZE; + } sq_fetch_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_1_t f; +} sq_fetch_1_u; + + +/* + * SQ_FETCH_2 struct + */ + +#define SQ_FETCH_2_VALUE_SIZE 32 + +#define SQ_FETCH_2_VALUE_SHIFT 0 + +#define SQ_FETCH_2_VALUE_MASK 0xffffffff + +#define SQ_FETCH_2_MASK \ + (SQ_FETCH_2_VALUE_MASK) + +#define SQ_FETCH_2(value) \ + ((value << SQ_FETCH_2_VALUE_SHIFT)) + +#define SQ_FETCH_2_GET_VALUE(sq_fetch_2) \ + ((sq_fetch_2 & SQ_FETCH_2_VALUE_MASK) >> SQ_FETCH_2_VALUE_SHIFT) + +#define SQ_FETCH_2_SET_VALUE(sq_fetch_2_reg, value) \ + sq_fetch_2_reg = (sq_fetch_2_reg & ~SQ_FETCH_2_VALUE_MASK) | (value << SQ_FETCH_2_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_2_t { + unsigned int value : SQ_FETCH_2_VALUE_SIZE; + } sq_fetch_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_2_t { + unsigned int value : SQ_FETCH_2_VALUE_SIZE; + } sq_fetch_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_2_t f; +} sq_fetch_2_u; + + +/* + * SQ_FETCH_3 struct + */ + +#define SQ_FETCH_3_VALUE_SIZE 32 + +#define SQ_FETCH_3_VALUE_SHIFT 0 + +#define SQ_FETCH_3_VALUE_MASK 0xffffffff + +#define SQ_FETCH_3_MASK \ + (SQ_FETCH_3_VALUE_MASK) + +#define SQ_FETCH_3(value) \ + ((value << SQ_FETCH_3_VALUE_SHIFT)) + +#define SQ_FETCH_3_GET_VALUE(sq_fetch_3) \ + ((sq_fetch_3 & SQ_FETCH_3_VALUE_MASK) >> SQ_FETCH_3_VALUE_SHIFT) + +#define SQ_FETCH_3_SET_VALUE(sq_fetch_3_reg, value) \ + sq_fetch_3_reg = (sq_fetch_3_reg & ~SQ_FETCH_3_VALUE_MASK) | (value << SQ_FETCH_3_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_3_t { + unsigned int value : SQ_FETCH_3_VALUE_SIZE; + } sq_fetch_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_3_t { + unsigned int value : SQ_FETCH_3_VALUE_SIZE; + } sq_fetch_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_3_t f; +} sq_fetch_3_u; + + +/* + * SQ_FETCH_4 struct + */ + +#define SQ_FETCH_4_VALUE_SIZE 32 + +#define SQ_FETCH_4_VALUE_SHIFT 0 + +#define SQ_FETCH_4_VALUE_MASK 0xffffffff + +#define SQ_FETCH_4_MASK \ + (SQ_FETCH_4_VALUE_MASK) + +#define SQ_FETCH_4(value) \ + ((value << SQ_FETCH_4_VALUE_SHIFT)) + +#define SQ_FETCH_4_GET_VALUE(sq_fetch_4) \ + ((sq_fetch_4 & SQ_FETCH_4_VALUE_MASK) >> SQ_FETCH_4_VALUE_SHIFT) + +#define SQ_FETCH_4_SET_VALUE(sq_fetch_4_reg, value) \ + sq_fetch_4_reg = (sq_fetch_4_reg & ~SQ_FETCH_4_VALUE_MASK) | (value << SQ_FETCH_4_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_4_t { + unsigned int value : SQ_FETCH_4_VALUE_SIZE; + } sq_fetch_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_4_t { + unsigned int value : SQ_FETCH_4_VALUE_SIZE; + } sq_fetch_4_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_4_t f; +} sq_fetch_4_u; + + +/* + * SQ_FETCH_5 struct + */ + +#define SQ_FETCH_5_VALUE_SIZE 32 + +#define SQ_FETCH_5_VALUE_SHIFT 0 + +#define SQ_FETCH_5_VALUE_MASK 0xffffffff + +#define SQ_FETCH_5_MASK \ + (SQ_FETCH_5_VALUE_MASK) + +#define SQ_FETCH_5(value) \ + ((value << SQ_FETCH_5_VALUE_SHIFT)) + +#define SQ_FETCH_5_GET_VALUE(sq_fetch_5) \ + ((sq_fetch_5 & SQ_FETCH_5_VALUE_MASK) >> SQ_FETCH_5_VALUE_SHIFT) + +#define SQ_FETCH_5_SET_VALUE(sq_fetch_5_reg, value) \ + sq_fetch_5_reg = (sq_fetch_5_reg & ~SQ_FETCH_5_VALUE_MASK) | (value << SQ_FETCH_5_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_5_t { + unsigned int value : SQ_FETCH_5_VALUE_SIZE; + } sq_fetch_5_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_5_t { + unsigned int value : SQ_FETCH_5_VALUE_SIZE; + } sq_fetch_5_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_5_t f; +} sq_fetch_5_u; + + +/* + * SQ_CONSTANT_VFETCH_0 struct + */ + +#define SQ_CONSTANT_VFETCH_0_TYPE_SIZE 1 +#define SQ_CONSTANT_VFETCH_0_STATE_SIZE 1 +#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE 30 + +#define SQ_CONSTANT_VFETCH_0_TYPE_SHIFT 0 +#define SQ_CONSTANT_VFETCH_0_STATE_SHIFT 1 +#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT 2 + +#define SQ_CONSTANT_VFETCH_0_TYPE_MASK 0x00000001 +#define SQ_CONSTANT_VFETCH_0_STATE_MASK 0x00000002 +#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK 0xfffffffc + +#define SQ_CONSTANT_VFETCH_0_MASK \ + (SQ_CONSTANT_VFETCH_0_TYPE_MASK | \ + SQ_CONSTANT_VFETCH_0_STATE_MASK | \ + SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) + +#define SQ_CONSTANT_VFETCH_0(type, state, base_address) \ + ((type << SQ_CONSTANT_VFETCH_0_TYPE_SHIFT) | \ + (state << SQ_CONSTANT_VFETCH_0_STATE_SHIFT) | \ + (base_address << SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT)) + +#define SQ_CONSTANT_VFETCH_0_GET_TYPE(sq_constant_vfetch_0) \ + ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_TYPE_MASK) >> SQ_CONSTANT_VFETCH_0_TYPE_SHIFT) +#define SQ_CONSTANT_VFETCH_0_GET_STATE(sq_constant_vfetch_0) \ + ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_STATE_MASK) >> SQ_CONSTANT_VFETCH_0_STATE_SHIFT) +#define SQ_CONSTANT_VFETCH_0_GET_BASE_ADDRESS(sq_constant_vfetch_0) \ + ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) >> SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT) + +#define SQ_CONSTANT_VFETCH_0_SET_TYPE(sq_constant_vfetch_0_reg, type) \ + sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_TYPE_MASK) | (type << SQ_CONSTANT_VFETCH_0_TYPE_SHIFT) +#define SQ_CONSTANT_VFETCH_0_SET_STATE(sq_constant_vfetch_0_reg, state) \ + sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_STATE_MASK) | (state << SQ_CONSTANT_VFETCH_0_STATE_SHIFT) +#define SQ_CONSTANT_VFETCH_0_SET_BASE_ADDRESS(sq_constant_vfetch_0_reg, base_address) \ + sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) | (base_address << SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_vfetch_0_t { + unsigned int type : SQ_CONSTANT_VFETCH_0_TYPE_SIZE; + unsigned int state : SQ_CONSTANT_VFETCH_0_STATE_SIZE; + unsigned int base_address : SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE; + } sq_constant_vfetch_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_vfetch_0_t { + unsigned int base_address : SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE; + unsigned int state : SQ_CONSTANT_VFETCH_0_STATE_SIZE; + unsigned int type : SQ_CONSTANT_VFETCH_0_TYPE_SIZE; + } sq_constant_vfetch_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_vfetch_0_t f; +} sq_constant_vfetch_0_u; + + +/* + * SQ_CONSTANT_VFETCH_1 struct + */ + +#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE 2 +#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE 30 + +#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT 0 +#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT 2 + +#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK 0x00000003 +#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK 0xfffffffc + +#define SQ_CONSTANT_VFETCH_1_MASK \ + (SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK | \ + SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) + +#define SQ_CONSTANT_VFETCH_1(endian_swap, limit_address) \ + ((endian_swap << SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT) | \ + (limit_address << SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT)) + +#define SQ_CONSTANT_VFETCH_1_GET_ENDIAN_SWAP(sq_constant_vfetch_1) \ + ((sq_constant_vfetch_1 & SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK) >> SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT) +#define SQ_CONSTANT_VFETCH_1_GET_LIMIT_ADDRESS(sq_constant_vfetch_1) \ + ((sq_constant_vfetch_1 & SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) >> SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT) + +#define SQ_CONSTANT_VFETCH_1_SET_ENDIAN_SWAP(sq_constant_vfetch_1_reg, endian_swap) \ + sq_constant_vfetch_1_reg = (sq_constant_vfetch_1_reg & ~SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK) | (endian_swap << SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT) +#define SQ_CONSTANT_VFETCH_1_SET_LIMIT_ADDRESS(sq_constant_vfetch_1_reg, limit_address) \ + sq_constant_vfetch_1_reg = (sq_constant_vfetch_1_reg & ~SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) | (limit_address << SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_vfetch_1_t { + unsigned int endian_swap : SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE; + unsigned int limit_address : SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE; + } sq_constant_vfetch_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_vfetch_1_t { + unsigned int limit_address : SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE; + unsigned int endian_swap : SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE; + } sq_constant_vfetch_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_vfetch_1_t f; +} sq_constant_vfetch_1_u; + + +/* + * SQ_CONSTANT_T2 struct + */ + +#define SQ_CONSTANT_T2_VALUE_SIZE 32 + +#define SQ_CONSTANT_T2_VALUE_SHIFT 0 + +#define SQ_CONSTANT_T2_VALUE_MASK 0xffffffff + +#define SQ_CONSTANT_T2_MASK \ + (SQ_CONSTANT_T2_VALUE_MASK) + +#define SQ_CONSTANT_T2(value) \ + ((value << SQ_CONSTANT_T2_VALUE_SHIFT)) + +#define SQ_CONSTANT_T2_GET_VALUE(sq_constant_t2) \ + ((sq_constant_t2 & SQ_CONSTANT_T2_VALUE_MASK) >> SQ_CONSTANT_T2_VALUE_SHIFT) + +#define SQ_CONSTANT_T2_SET_VALUE(sq_constant_t2_reg, value) \ + sq_constant_t2_reg = (sq_constant_t2_reg & ~SQ_CONSTANT_T2_VALUE_MASK) | (value << SQ_CONSTANT_T2_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_t2_t { + unsigned int value : SQ_CONSTANT_T2_VALUE_SIZE; + } sq_constant_t2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_t2_t { + unsigned int value : SQ_CONSTANT_T2_VALUE_SIZE; + } sq_constant_t2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_t2_t f; +} sq_constant_t2_u; + + +/* + * SQ_CONSTANT_T3 struct + */ + +#define SQ_CONSTANT_T3_VALUE_SIZE 32 + +#define SQ_CONSTANT_T3_VALUE_SHIFT 0 + +#define SQ_CONSTANT_T3_VALUE_MASK 0xffffffff + +#define SQ_CONSTANT_T3_MASK \ + (SQ_CONSTANT_T3_VALUE_MASK) + +#define SQ_CONSTANT_T3(value) \ + ((value << SQ_CONSTANT_T3_VALUE_SHIFT)) + +#define SQ_CONSTANT_T3_GET_VALUE(sq_constant_t3) \ + ((sq_constant_t3 & SQ_CONSTANT_T3_VALUE_MASK) >> SQ_CONSTANT_T3_VALUE_SHIFT) + +#define SQ_CONSTANT_T3_SET_VALUE(sq_constant_t3_reg, value) \ + sq_constant_t3_reg = (sq_constant_t3_reg & ~SQ_CONSTANT_T3_VALUE_MASK) | (value << SQ_CONSTANT_T3_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_t3_t { + unsigned int value : SQ_CONSTANT_T3_VALUE_SIZE; + } sq_constant_t3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_t3_t { + unsigned int value : SQ_CONSTANT_T3_VALUE_SIZE; + } sq_constant_t3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_t3_t f; +} sq_constant_t3_u; + + +/* + * SQ_CF_BOOLEANS struct + */ + +#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE 8 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE 8 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE 8 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE 8 + +#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT 0 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT 8 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT 16 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT 24 + +#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK 0x000000ff +#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK 0x0000ff00 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK 0x00ff0000 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK 0xff000000 + +#define SQ_CF_BOOLEANS_MASK \ + (SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK | \ + SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK | \ + SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK | \ + SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) + +#define SQ_CF_BOOLEANS(cf_booleans_0, cf_booleans_1, cf_booleans_2, cf_booleans_3) \ + ((cf_booleans_0 << SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT) | \ + (cf_booleans_1 << SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT) | \ + (cf_booleans_2 << SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT) | \ + (cf_booleans_3 << SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT)) + +#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_0(sq_cf_booleans) \ + ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT) +#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_1(sq_cf_booleans) \ + ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT) +#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_2(sq_cf_booleans) \ + ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT) +#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_3(sq_cf_booleans) \ + ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT) + +#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_0(sq_cf_booleans_reg, cf_booleans_0) \ + sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK) | (cf_booleans_0 << SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT) +#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_1(sq_cf_booleans_reg, cf_booleans_1) \ + sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK) | (cf_booleans_1 << SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT) +#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_2(sq_cf_booleans_reg, cf_booleans_2) \ + sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK) | (cf_booleans_2 << SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT) +#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_3(sq_cf_booleans_reg, cf_booleans_3) \ + sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) | (cf_booleans_3 << SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_booleans_t { + unsigned int cf_booleans_0 : SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE; + unsigned int cf_booleans_1 : SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE; + unsigned int cf_booleans_2 : SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE; + unsigned int cf_booleans_3 : SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE; + } sq_cf_booleans_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_booleans_t { + unsigned int cf_booleans_3 : SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE; + unsigned int cf_booleans_2 : SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE; + unsigned int cf_booleans_1 : SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE; + unsigned int cf_booleans_0 : SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE; + } sq_cf_booleans_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_booleans_t f; +} sq_cf_booleans_u; + + +/* + * SQ_CF_LOOP struct + */ + +#define SQ_CF_LOOP_CF_LOOP_COUNT_SIZE 8 +#define SQ_CF_LOOP_CF_LOOP_START_SIZE 8 +#define SQ_CF_LOOP_CF_LOOP_STEP_SIZE 8 + +#define SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT 0 +#define SQ_CF_LOOP_CF_LOOP_START_SHIFT 8 +#define SQ_CF_LOOP_CF_LOOP_STEP_SHIFT 16 + +#define SQ_CF_LOOP_CF_LOOP_COUNT_MASK 0x000000ff +#define SQ_CF_LOOP_CF_LOOP_START_MASK 0x0000ff00 +#define SQ_CF_LOOP_CF_LOOP_STEP_MASK 0x00ff0000 + +#define SQ_CF_LOOP_MASK \ + (SQ_CF_LOOP_CF_LOOP_COUNT_MASK | \ + SQ_CF_LOOP_CF_LOOP_START_MASK | \ + SQ_CF_LOOP_CF_LOOP_STEP_MASK) + +#define SQ_CF_LOOP(cf_loop_count, cf_loop_start, cf_loop_step) \ + ((cf_loop_count << SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT) | \ + (cf_loop_start << SQ_CF_LOOP_CF_LOOP_START_SHIFT) | \ + (cf_loop_step << SQ_CF_LOOP_CF_LOOP_STEP_SHIFT)) + +#define SQ_CF_LOOP_GET_CF_LOOP_COUNT(sq_cf_loop) \ + ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_COUNT_MASK) >> SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT) +#define SQ_CF_LOOP_GET_CF_LOOP_START(sq_cf_loop) \ + ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_START_MASK) >> SQ_CF_LOOP_CF_LOOP_START_SHIFT) +#define SQ_CF_LOOP_GET_CF_LOOP_STEP(sq_cf_loop) \ + ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_STEP_MASK) >> SQ_CF_LOOP_CF_LOOP_STEP_SHIFT) + +#define SQ_CF_LOOP_SET_CF_LOOP_COUNT(sq_cf_loop_reg, cf_loop_count) \ + sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_COUNT_MASK) | (cf_loop_count << SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT) +#define SQ_CF_LOOP_SET_CF_LOOP_START(sq_cf_loop_reg, cf_loop_start) \ + sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_START_MASK) | (cf_loop_start << SQ_CF_LOOP_CF_LOOP_START_SHIFT) +#define SQ_CF_LOOP_SET_CF_LOOP_STEP(sq_cf_loop_reg, cf_loop_step) \ + sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_STEP_MASK) | (cf_loop_step << SQ_CF_LOOP_CF_LOOP_STEP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_loop_t { + unsigned int cf_loop_count : SQ_CF_LOOP_CF_LOOP_COUNT_SIZE; + unsigned int cf_loop_start : SQ_CF_LOOP_CF_LOOP_START_SIZE; + unsigned int cf_loop_step : SQ_CF_LOOP_CF_LOOP_STEP_SIZE; + unsigned int : 8; + } sq_cf_loop_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_loop_t { + unsigned int : 8; + unsigned int cf_loop_step : SQ_CF_LOOP_CF_LOOP_STEP_SIZE; + unsigned int cf_loop_start : SQ_CF_LOOP_CF_LOOP_START_SIZE; + unsigned int cf_loop_count : SQ_CF_LOOP_CF_LOOP_COUNT_SIZE; + } sq_cf_loop_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_loop_t f; +} sq_cf_loop_u; + + +/* + * SQ_CONSTANT_RT_0 struct + */ + +#define SQ_CONSTANT_RT_0_RED_SIZE 32 + +#define SQ_CONSTANT_RT_0_RED_SHIFT 0 + +#define SQ_CONSTANT_RT_0_RED_MASK 0xffffffff + +#define SQ_CONSTANT_RT_0_MASK \ + (SQ_CONSTANT_RT_0_RED_MASK) + +#define SQ_CONSTANT_RT_0(red) \ + ((red << SQ_CONSTANT_RT_0_RED_SHIFT)) + +#define SQ_CONSTANT_RT_0_GET_RED(sq_constant_rt_0) \ + ((sq_constant_rt_0 & SQ_CONSTANT_RT_0_RED_MASK) >> SQ_CONSTANT_RT_0_RED_SHIFT) + +#define SQ_CONSTANT_RT_0_SET_RED(sq_constant_rt_0_reg, red) \ + sq_constant_rt_0_reg = (sq_constant_rt_0_reg & ~SQ_CONSTANT_RT_0_RED_MASK) | (red << SQ_CONSTANT_RT_0_RED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_rt_0_t { + unsigned int red : SQ_CONSTANT_RT_0_RED_SIZE; + } sq_constant_rt_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_rt_0_t { + unsigned int red : SQ_CONSTANT_RT_0_RED_SIZE; + } sq_constant_rt_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_rt_0_t f; +} sq_constant_rt_0_u; + + +/* + * SQ_CONSTANT_RT_1 struct + */ + +#define SQ_CONSTANT_RT_1_GREEN_SIZE 32 + +#define SQ_CONSTANT_RT_1_GREEN_SHIFT 0 + +#define SQ_CONSTANT_RT_1_GREEN_MASK 0xffffffff + +#define SQ_CONSTANT_RT_1_MASK \ + (SQ_CONSTANT_RT_1_GREEN_MASK) + +#define SQ_CONSTANT_RT_1(green) \ + ((green << SQ_CONSTANT_RT_1_GREEN_SHIFT)) + +#define SQ_CONSTANT_RT_1_GET_GREEN(sq_constant_rt_1) \ + ((sq_constant_rt_1 & SQ_CONSTANT_RT_1_GREEN_MASK) >> SQ_CONSTANT_RT_1_GREEN_SHIFT) + +#define SQ_CONSTANT_RT_1_SET_GREEN(sq_constant_rt_1_reg, green) \ + sq_constant_rt_1_reg = (sq_constant_rt_1_reg & ~SQ_CONSTANT_RT_1_GREEN_MASK) | (green << SQ_CONSTANT_RT_1_GREEN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_rt_1_t { + unsigned int green : SQ_CONSTANT_RT_1_GREEN_SIZE; + } sq_constant_rt_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_rt_1_t { + unsigned int green : SQ_CONSTANT_RT_1_GREEN_SIZE; + } sq_constant_rt_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_rt_1_t f; +} sq_constant_rt_1_u; + + +/* + * SQ_CONSTANT_RT_2 struct + */ + +#define SQ_CONSTANT_RT_2_BLUE_SIZE 32 + +#define SQ_CONSTANT_RT_2_BLUE_SHIFT 0 + +#define SQ_CONSTANT_RT_2_BLUE_MASK 0xffffffff + +#define SQ_CONSTANT_RT_2_MASK \ + (SQ_CONSTANT_RT_2_BLUE_MASK) + +#define SQ_CONSTANT_RT_2(blue) \ + ((blue << SQ_CONSTANT_RT_2_BLUE_SHIFT)) + +#define SQ_CONSTANT_RT_2_GET_BLUE(sq_constant_rt_2) \ + ((sq_constant_rt_2 & SQ_CONSTANT_RT_2_BLUE_MASK) >> SQ_CONSTANT_RT_2_BLUE_SHIFT) + +#define SQ_CONSTANT_RT_2_SET_BLUE(sq_constant_rt_2_reg, blue) \ + sq_constant_rt_2_reg = (sq_constant_rt_2_reg & ~SQ_CONSTANT_RT_2_BLUE_MASK) | (blue << SQ_CONSTANT_RT_2_BLUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_rt_2_t { + unsigned int blue : SQ_CONSTANT_RT_2_BLUE_SIZE; + } sq_constant_rt_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_rt_2_t { + unsigned int blue : SQ_CONSTANT_RT_2_BLUE_SIZE; + } sq_constant_rt_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_rt_2_t f; +} sq_constant_rt_2_u; + + +/* + * SQ_CONSTANT_RT_3 struct + */ + +#define SQ_CONSTANT_RT_3_ALPHA_SIZE 32 + +#define SQ_CONSTANT_RT_3_ALPHA_SHIFT 0 + +#define SQ_CONSTANT_RT_3_ALPHA_MASK 0xffffffff + +#define SQ_CONSTANT_RT_3_MASK \ + (SQ_CONSTANT_RT_3_ALPHA_MASK) + +#define SQ_CONSTANT_RT_3(alpha) \ + ((alpha << SQ_CONSTANT_RT_3_ALPHA_SHIFT)) + +#define SQ_CONSTANT_RT_3_GET_ALPHA(sq_constant_rt_3) \ + ((sq_constant_rt_3 & SQ_CONSTANT_RT_3_ALPHA_MASK) >> SQ_CONSTANT_RT_3_ALPHA_SHIFT) + +#define SQ_CONSTANT_RT_3_SET_ALPHA(sq_constant_rt_3_reg, alpha) \ + sq_constant_rt_3_reg = (sq_constant_rt_3_reg & ~SQ_CONSTANT_RT_3_ALPHA_MASK) | (alpha << SQ_CONSTANT_RT_3_ALPHA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_rt_3_t { + unsigned int alpha : SQ_CONSTANT_RT_3_ALPHA_SIZE; + } sq_constant_rt_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_rt_3_t { + unsigned int alpha : SQ_CONSTANT_RT_3_ALPHA_SIZE; + } sq_constant_rt_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_rt_3_t f; +} sq_constant_rt_3_u; + + +/* + * SQ_FETCH_RT_0 struct + */ + +#define SQ_FETCH_RT_0_VALUE_SIZE 32 + +#define SQ_FETCH_RT_0_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_0_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_0_MASK \ + (SQ_FETCH_RT_0_VALUE_MASK) + +#define SQ_FETCH_RT_0(value) \ + ((value << SQ_FETCH_RT_0_VALUE_SHIFT)) + +#define SQ_FETCH_RT_0_GET_VALUE(sq_fetch_rt_0) \ + ((sq_fetch_rt_0 & SQ_FETCH_RT_0_VALUE_MASK) >> SQ_FETCH_RT_0_VALUE_SHIFT) + +#define SQ_FETCH_RT_0_SET_VALUE(sq_fetch_rt_0_reg, value) \ + sq_fetch_rt_0_reg = (sq_fetch_rt_0_reg & ~SQ_FETCH_RT_0_VALUE_MASK) | (value << SQ_FETCH_RT_0_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_0_t { + unsigned int value : SQ_FETCH_RT_0_VALUE_SIZE; + } sq_fetch_rt_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_0_t { + unsigned int value : SQ_FETCH_RT_0_VALUE_SIZE; + } sq_fetch_rt_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_0_t f; +} sq_fetch_rt_0_u; + + +/* + * SQ_FETCH_RT_1 struct + */ + +#define SQ_FETCH_RT_1_VALUE_SIZE 32 + +#define SQ_FETCH_RT_1_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_1_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_1_MASK \ + (SQ_FETCH_RT_1_VALUE_MASK) + +#define SQ_FETCH_RT_1(value) \ + ((value << SQ_FETCH_RT_1_VALUE_SHIFT)) + +#define SQ_FETCH_RT_1_GET_VALUE(sq_fetch_rt_1) \ + ((sq_fetch_rt_1 & SQ_FETCH_RT_1_VALUE_MASK) >> SQ_FETCH_RT_1_VALUE_SHIFT) + +#define SQ_FETCH_RT_1_SET_VALUE(sq_fetch_rt_1_reg, value) \ + sq_fetch_rt_1_reg = (sq_fetch_rt_1_reg & ~SQ_FETCH_RT_1_VALUE_MASK) | (value << SQ_FETCH_RT_1_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_1_t { + unsigned int value : SQ_FETCH_RT_1_VALUE_SIZE; + } sq_fetch_rt_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_1_t { + unsigned int value : SQ_FETCH_RT_1_VALUE_SIZE; + } sq_fetch_rt_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_1_t f; +} sq_fetch_rt_1_u; + + +/* + * SQ_FETCH_RT_2 struct + */ + +#define SQ_FETCH_RT_2_VALUE_SIZE 32 + +#define SQ_FETCH_RT_2_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_2_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_2_MASK \ + (SQ_FETCH_RT_2_VALUE_MASK) + +#define SQ_FETCH_RT_2(value) \ + ((value << SQ_FETCH_RT_2_VALUE_SHIFT)) + +#define SQ_FETCH_RT_2_GET_VALUE(sq_fetch_rt_2) \ + ((sq_fetch_rt_2 & SQ_FETCH_RT_2_VALUE_MASK) >> SQ_FETCH_RT_2_VALUE_SHIFT) + +#define SQ_FETCH_RT_2_SET_VALUE(sq_fetch_rt_2_reg, value) \ + sq_fetch_rt_2_reg = (sq_fetch_rt_2_reg & ~SQ_FETCH_RT_2_VALUE_MASK) | (value << SQ_FETCH_RT_2_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_2_t { + unsigned int value : SQ_FETCH_RT_2_VALUE_SIZE; + } sq_fetch_rt_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_2_t { + unsigned int value : SQ_FETCH_RT_2_VALUE_SIZE; + } sq_fetch_rt_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_2_t f; +} sq_fetch_rt_2_u; + + +/* + * SQ_FETCH_RT_3 struct + */ + +#define SQ_FETCH_RT_3_VALUE_SIZE 32 + +#define SQ_FETCH_RT_3_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_3_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_3_MASK \ + (SQ_FETCH_RT_3_VALUE_MASK) + +#define SQ_FETCH_RT_3(value) \ + ((value << SQ_FETCH_RT_3_VALUE_SHIFT)) + +#define SQ_FETCH_RT_3_GET_VALUE(sq_fetch_rt_3) \ + ((sq_fetch_rt_3 & SQ_FETCH_RT_3_VALUE_MASK) >> SQ_FETCH_RT_3_VALUE_SHIFT) + +#define SQ_FETCH_RT_3_SET_VALUE(sq_fetch_rt_3_reg, value) \ + sq_fetch_rt_3_reg = (sq_fetch_rt_3_reg & ~SQ_FETCH_RT_3_VALUE_MASK) | (value << SQ_FETCH_RT_3_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_3_t { + unsigned int value : SQ_FETCH_RT_3_VALUE_SIZE; + } sq_fetch_rt_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_3_t { + unsigned int value : SQ_FETCH_RT_3_VALUE_SIZE; + } sq_fetch_rt_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_3_t f; +} sq_fetch_rt_3_u; + + +/* + * SQ_FETCH_RT_4 struct + */ + +#define SQ_FETCH_RT_4_VALUE_SIZE 32 + +#define SQ_FETCH_RT_4_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_4_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_4_MASK \ + (SQ_FETCH_RT_4_VALUE_MASK) + +#define SQ_FETCH_RT_4(value) \ + ((value << SQ_FETCH_RT_4_VALUE_SHIFT)) + +#define SQ_FETCH_RT_4_GET_VALUE(sq_fetch_rt_4) \ + ((sq_fetch_rt_4 & SQ_FETCH_RT_4_VALUE_MASK) >> SQ_FETCH_RT_4_VALUE_SHIFT) + +#define SQ_FETCH_RT_4_SET_VALUE(sq_fetch_rt_4_reg, value) \ + sq_fetch_rt_4_reg = (sq_fetch_rt_4_reg & ~SQ_FETCH_RT_4_VALUE_MASK) | (value << SQ_FETCH_RT_4_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_4_t { + unsigned int value : SQ_FETCH_RT_4_VALUE_SIZE; + } sq_fetch_rt_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_4_t { + unsigned int value : SQ_FETCH_RT_4_VALUE_SIZE; + } sq_fetch_rt_4_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_4_t f; +} sq_fetch_rt_4_u; + + +/* + * SQ_FETCH_RT_5 struct + */ + +#define SQ_FETCH_RT_5_VALUE_SIZE 32 + +#define SQ_FETCH_RT_5_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_5_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_5_MASK \ + (SQ_FETCH_RT_5_VALUE_MASK) + +#define SQ_FETCH_RT_5(value) \ + ((value << SQ_FETCH_RT_5_VALUE_SHIFT)) + +#define SQ_FETCH_RT_5_GET_VALUE(sq_fetch_rt_5) \ + ((sq_fetch_rt_5 & SQ_FETCH_RT_5_VALUE_MASK) >> SQ_FETCH_RT_5_VALUE_SHIFT) + +#define SQ_FETCH_RT_5_SET_VALUE(sq_fetch_rt_5_reg, value) \ + sq_fetch_rt_5_reg = (sq_fetch_rt_5_reg & ~SQ_FETCH_RT_5_VALUE_MASK) | (value << SQ_FETCH_RT_5_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_5_t { + unsigned int value : SQ_FETCH_RT_5_VALUE_SIZE; + } sq_fetch_rt_5_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_5_t { + unsigned int value : SQ_FETCH_RT_5_VALUE_SIZE; + } sq_fetch_rt_5_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_5_t f; +} sq_fetch_rt_5_u; + + +/* + * SQ_CF_RT_BOOLEANS struct + */ + +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE 8 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE 8 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE 8 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE 8 + +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT 0 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT 8 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT 16 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT 24 + +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK 0x000000ff +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK 0x0000ff00 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK 0x00ff0000 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK 0xff000000 + +#define SQ_CF_RT_BOOLEANS_MASK \ + (SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK | \ + SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK | \ + SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK | \ + SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) + +#define SQ_CF_RT_BOOLEANS(cf_booleans_0, cf_booleans_1, cf_booleans_2, cf_booleans_3) \ + ((cf_booleans_0 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT) | \ + (cf_booleans_1 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT) | \ + (cf_booleans_2 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT) | \ + (cf_booleans_3 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT)) + +#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_0(sq_cf_rt_booleans) \ + ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT) +#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_1(sq_cf_rt_booleans) \ + ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT) +#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_2(sq_cf_rt_booleans) \ + ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT) +#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_3(sq_cf_rt_booleans) \ + ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT) + +#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_0(sq_cf_rt_booleans_reg, cf_booleans_0) \ + sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK) | (cf_booleans_0 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT) +#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_1(sq_cf_rt_booleans_reg, cf_booleans_1) \ + sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK) | (cf_booleans_1 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT) +#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_2(sq_cf_rt_booleans_reg, cf_booleans_2) \ + sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK) | (cf_booleans_2 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT) +#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_3(sq_cf_rt_booleans_reg, cf_booleans_3) \ + sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) | (cf_booleans_3 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_rt_booleans_t { + unsigned int cf_booleans_0 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE; + unsigned int cf_booleans_1 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE; + unsigned int cf_booleans_2 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE; + unsigned int cf_booleans_3 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE; + } sq_cf_rt_booleans_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_rt_booleans_t { + unsigned int cf_booleans_3 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE; + unsigned int cf_booleans_2 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE; + unsigned int cf_booleans_1 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE; + unsigned int cf_booleans_0 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE; + } sq_cf_rt_booleans_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_rt_booleans_t f; +} sq_cf_rt_booleans_u; + + +/* + * SQ_CF_RT_LOOP struct + */ + +#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE 8 +#define SQ_CF_RT_LOOP_CF_LOOP_START_SIZE 8 +#define SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE 8 + +#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT 0 +#define SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT 8 +#define SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT 16 + +#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK 0x000000ff +#define SQ_CF_RT_LOOP_CF_LOOP_START_MASK 0x0000ff00 +#define SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK 0x00ff0000 + +#define SQ_CF_RT_LOOP_MASK \ + (SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK | \ + SQ_CF_RT_LOOP_CF_LOOP_START_MASK | \ + SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) + +#define SQ_CF_RT_LOOP(cf_loop_count, cf_loop_start, cf_loop_step) \ + ((cf_loop_count << SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT) | \ + (cf_loop_start << SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT) | \ + (cf_loop_step << SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT)) + +#define SQ_CF_RT_LOOP_GET_CF_LOOP_COUNT(sq_cf_rt_loop) \ + ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT) +#define SQ_CF_RT_LOOP_GET_CF_LOOP_START(sq_cf_rt_loop) \ + ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_START_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT) +#define SQ_CF_RT_LOOP_GET_CF_LOOP_STEP(sq_cf_rt_loop) \ + ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT) + +#define SQ_CF_RT_LOOP_SET_CF_LOOP_COUNT(sq_cf_rt_loop_reg, cf_loop_count) \ + sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK) | (cf_loop_count << SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT) +#define SQ_CF_RT_LOOP_SET_CF_LOOP_START(sq_cf_rt_loop_reg, cf_loop_start) \ + sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_START_MASK) | (cf_loop_start << SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT) +#define SQ_CF_RT_LOOP_SET_CF_LOOP_STEP(sq_cf_rt_loop_reg, cf_loop_step) \ + sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) | (cf_loop_step << SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_rt_loop_t { + unsigned int cf_loop_count : SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE; + unsigned int cf_loop_start : SQ_CF_RT_LOOP_CF_LOOP_START_SIZE; + unsigned int cf_loop_step : SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE; + unsigned int : 8; + } sq_cf_rt_loop_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_rt_loop_t { + unsigned int : 8; + unsigned int cf_loop_step : SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE; + unsigned int cf_loop_start : SQ_CF_RT_LOOP_CF_LOOP_START_SIZE; + unsigned int cf_loop_count : SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE; + } sq_cf_rt_loop_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_rt_loop_t f; +} sq_cf_rt_loop_u; + + +/* + * SQ_VS_PROGRAM struct + */ + +#define SQ_VS_PROGRAM_BASE_SIZE 12 +#define SQ_VS_PROGRAM_SIZE_SIZE 12 + +#define SQ_VS_PROGRAM_BASE_SHIFT 0 +#define SQ_VS_PROGRAM_SIZE_SHIFT 12 + +#define SQ_VS_PROGRAM_BASE_MASK 0x00000fff +#define SQ_VS_PROGRAM_SIZE_MASK 0x00fff000 + +#define SQ_VS_PROGRAM_MASK \ + (SQ_VS_PROGRAM_BASE_MASK | \ + SQ_VS_PROGRAM_SIZE_MASK) + +#define SQ_VS_PROGRAM(base, size) \ + ((base << SQ_VS_PROGRAM_BASE_SHIFT) | \ + (size << SQ_VS_PROGRAM_SIZE_SHIFT)) + +#define SQ_VS_PROGRAM_GET_BASE(sq_vs_program) \ + ((sq_vs_program & SQ_VS_PROGRAM_BASE_MASK) >> SQ_VS_PROGRAM_BASE_SHIFT) +#define SQ_VS_PROGRAM_GET_SIZE(sq_vs_program) \ + ((sq_vs_program & SQ_VS_PROGRAM_SIZE_MASK) >> SQ_VS_PROGRAM_SIZE_SHIFT) + +#define SQ_VS_PROGRAM_SET_BASE(sq_vs_program_reg, base) \ + sq_vs_program_reg = (sq_vs_program_reg & ~SQ_VS_PROGRAM_BASE_MASK) | (base << SQ_VS_PROGRAM_BASE_SHIFT) +#define SQ_VS_PROGRAM_SET_SIZE(sq_vs_program_reg, size) \ + sq_vs_program_reg = (sq_vs_program_reg & ~SQ_VS_PROGRAM_SIZE_MASK) | (size << SQ_VS_PROGRAM_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_vs_program_t { + unsigned int base : SQ_VS_PROGRAM_BASE_SIZE; + unsigned int size : SQ_VS_PROGRAM_SIZE_SIZE; + unsigned int : 8; + } sq_vs_program_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_vs_program_t { + unsigned int : 8; + unsigned int size : SQ_VS_PROGRAM_SIZE_SIZE; + unsigned int base : SQ_VS_PROGRAM_BASE_SIZE; + } sq_vs_program_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_vs_program_t f; +} sq_vs_program_u; + + +/* + * SQ_PS_PROGRAM struct + */ + +#define SQ_PS_PROGRAM_BASE_SIZE 12 +#define SQ_PS_PROGRAM_SIZE_SIZE 12 + +#define SQ_PS_PROGRAM_BASE_SHIFT 0 +#define SQ_PS_PROGRAM_SIZE_SHIFT 12 + +#define SQ_PS_PROGRAM_BASE_MASK 0x00000fff +#define SQ_PS_PROGRAM_SIZE_MASK 0x00fff000 + +#define SQ_PS_PROGRAM_MASK \ + (SQ_PS_PROGRAM_BASE_MASK | \ + SQ_PS_PROGRAM_SIZE_MASK) + +#define SQ_PS_PROGRAM(base, size) \ + ((base << SQ_PS_PROGRAM_BASE_SHIFT) | \ + (size << SQ_PS_PROGRAM_SIZE_SHIFT)) + +#define SQ_PS_PROGRAM_GET_BASE(sq_ps_program) \ + ((sq_ps_program & SQ_PS_PROGRAM_BASE_MASK) >> SQ_PS_PROGRAM_BASE_SHIFT) +#define SQ_PS_PROGRAM_GET_SIZE(sq_ps_program) \ + ((sq_ps_program & SQ_PS_PROGRAM_SIZE_MASK) >> SQ_PS_PROGRAM_SIZE_SHIFT) + +#define SQ_PS_PROGRAM_SET_BASE(sq_ps_program_reg, base) \ + sq_ps_program_reg = (sq_ps_program_reg & ~SQ_PS_PROGRAM_BASE_MASK) | (base << SQ_PS_PROGRAM_BASE_SHIFT) +#define SQ_PS_PROGRAM_SET_SIZE(sq_ps_program_reg, size) \ + sq_ps_program_reg = (sq_ps_program_reg & ~SQ_PS_PROGRAM_SIZE_MASK) | (size << SQ_PS_PROGRAM_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_ps_program_t { + unsigned int base : SQ_PS_PROGRAM_BASE_SIZE; + unsigned int size : SQ_PS_PROGRAM_SIZE_SIZE; + unsigned int : 8; + } sq_ps_program_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_ps_program_t { + unsigned int : 8; + unsigned int size : SQ_PS_PROGRAM_SIZE_SIZE; + unsigned int base : SQ_PS_PROGRAM_BASE_SIZE; + } sq_ps_program_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_ps_program_t f; +} sq_ps_program_u; + + +/* + * SQ_CF_PROGRAM_SIZE struct + */ + +#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE 11 +#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE 11 + +#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT 0 +#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT 12 + +#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK 0x000007ff +#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK 0x007ff000 + +#define SQ_CF_PROGRAM_SIZE_MASK \ + (SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK | \ + SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) + +#define SQ_CF_PROGRAM_SIZE(vs_cf_size, ps_cf_size) \ + ((vs_cf_size << SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT) | \ + (ps_cf_size << SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT)) + +#define SQ_CF_PROGRAM_SIZE_GET_VS_CF_SIZE(sq_cf_program_size) \ + ((sq_cf_program_size & SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK) >> SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT) +#define SQ_CF_PROGRAM_SIZE_GET_PS_CF_SIZE(sq_cf_program_size) \ + ((sq_cf_program_size & SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) >> SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT) + +#define SQ_CF_PROGRAM_SIZE_SET_VS_CF_SIZE(sq_cf_program_size_reg, vs_cf_size) \ + sq_cf_program_size_reg = (sq_cf_program_size_reg & ~SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK) | (vs_cf_size << SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT) +#define SQ_CF_PROGRAM_SIZE_SET_PS_CF_SIZE(sq_cf_program_size_reg, ps_cf_size) \ + sq_cf_program_size_reg = (sq_cf_program_size_reg & ~SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) | (ps_cf_size << SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_program_size_t { + unsigned int vs_cf_size : SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE; + unsigned int : 1; + unsigned int ps_cf_size : SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE; + unsigned int : 9; + } sq_cf_program_size_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_program_size_t { + unsigned int : 9; + unsigned int ps_cf_size : SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE; + unsigned int : 1; + unsigned int vs_cf_size : SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE; + } sq_cf_program_size_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_program_size_t f; +} sq_cf_program_size_u; + + +/* + * SQ_INTERPOLATOR_CNTL struct + */ + +#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE 16 +#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE 16 + +#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT 0 +#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT 16 + +#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK 0x0000ffff +#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK 0xffff0000 + +#define SQ_INTERPOLATOR_CNTL_MASK \ + (SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK | \ + SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) + +#define SQ_INTERPOLATOR_CNTL(param_shade, sampling_pattern) \ + ((param_shade << SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT) | \ + (sampling_pattern << SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT)) + +#define SQ_INTERPOLATOR_CNTL_GET_PARAM_SHADE(sq_interpolator_cntl) \ + ((sq_interpolator_cntl & SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK) >> SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT) +#define SQ_INTERPOLATOR_CNTL_GET_SAMPLING_PATTERN(sq_interpolator_cntl) \ + ((sq_interpolator_cntl & SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) >> SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT) + +#define SQ_INTERPOLATOR_CNTL_SET_PARAM_SHADE(sq_interpolator_cntl_reg, param_shade) \ + sq_interpolator_cntl_reg = (sq_interpolator_cntl_reg & ~SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK) | (param_shade << SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT) +#define SQ_INTERPOLATOR_CNTL_SET_SAMPLING_PATTERN(sq_interpolator_cntl_reg, sampling_pattern) \ + sq_interpolator_cntl_reg = (sq_interpolator_cntl_reg & ~SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) | (sampling_pattern << SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_interpolator_cntl_t { + unsigned int param_shade : SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE; + unsigned int sampling_pattern : SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE; + } sq_interpolator_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_interpolator_cntl_t { + unsigned int sampling_pattern : SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE; + unsigned int param_shade : SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE; + } sq_interpolator_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_interpolator_cntl_t f; +} sq_interpolator_cntl_u; + + +/* + * SQ_PROGRAM_CNTL struct + */ + +#define SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE 6 +#define SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE 6 +#define SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE 1 +#define SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE 1 +#define SQ_PROGRAM_CNTL_PARAM_GEN_SIZE 1 +#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE 1 +#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE 4 +#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE 3 +#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE 4 +#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE 1 + +#define SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT 0 +#define SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT 8 +#define SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT 16 +#define SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT 17 +#define SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT 18 +#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT 19 +#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT 20 +#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT 24 +#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT 27 +#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT 31 + +#define SQ_PROGRAM_CNTL_VS_NUM_REG_MASK 0x0000003f +#define SQ_PROGRAM_CNTL_PS_NUM_REG_MASK 0x00003f00 +#define SQ_PROGRAM_CNTL_VS_RESOURCE_MASK 0x00010000 +#define SQ_PROGRAM_CNTL_PS_RESOURCE_MASK 0x00020000 +#define SQ_PROGRAM_CNTL_PARAM_GEN_MASK 0x00040000 +#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK 0x00080000 +#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK 0x00f00000 +#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK 0x07000000 +#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK 0x78000000 +#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK 0x80000000 + +#define SQ_PROGRAM_CNTL_MASK \ + (SQ_PROGRAM_CNTL_VS_NUM_REG_MASK | \ + SQ_PROGRAM_CNTL_PS_NUM_REG_MASK | \ + SQ_PROGRAM_CNTL_VS_RESOURCE_MASK | \ + SQ_PROGRAM_CNTL_PS_RESOURCE_MASK | \ + SQ_PROGRAM_CNTL_PARAM_GEN_MASK | \ + SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK | \ + SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK | \ + SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK | \ + SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK | \ + SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) + +#define SQ_PROGRAM_CNTL(vs_num_reg, ps_num_reg, vs_resource, ps_resource, param_gen, gen_index_pix, vs_export_count, vs_export_mode, ps_export_mode, gen_index_vtx) \ + ((vs_num_reg << SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT) | \ + (ps_num_reg << SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT) | \ + (vs_resource << SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT) | \ + (ps_resource << SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT) | \ + (param_gen << SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT) | \ + (gen_index_pix << SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT) | \ + (vs_export_count << SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT) | \ + (vs_export_mode << SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT) | \ + (ps_export_mode << SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT) | \ + (gen_index_vtx << SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT)) + +#define SQ_PROGRAM_CNTL_GET_VS_NUM_REG(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_NUM_REG_MASK) >> SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT) +#define SQ_PROGRAM_CNTL_GET_PS_NUM_REG(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_NUM_REG_MASK) >> SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT) +#define SQ_PROGRAM_CNTL_GET_VS_RESOURCE(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_RESOURCE_MASK) >> SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT) +#define SQ_PROGRAM_CNTL_GET_PS_RESOURCE(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_RESOURCE_MASK) >> SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT) +#define SQ_PROGRAM_CNTL_GET_PARAM_GEN(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_PARAM_GEN_MASK) >> SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT) +#define SQ_PROGRAM_CNTL_GET_GEN_INDEX_PIX(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK) >> SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT) +#define SQ_PROGRAM_CNTL_GET_VS_EXPORT_COUNT(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK) >> SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT) +#define SQ_PROGRAM_CNTL_GET_VS_EXPORT_MODE(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK) >> SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT) +#define SQ_PROGRAM_CNTL_GET_PS_EXPORT_MODE(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK) >> SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT) +#define SQ_PROGRAM_CNTL_GET_GEN_INDEX_VTX(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) >> SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT) + +#define SQ_PROGRAM_CNTL_SET_VS_NUM_REG(sq_program_cntl_reg, vs_num_reg) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_NUM_REG_MASK) | (vs_num_reg << SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT) +#define SQ_PROGRAM_CNTL_SET_PS_NUM_REG(sq_program_cntl_reg, ps_num_reg) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_NUM_REG_MASK) | (ps_num_reg << SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT) +#define SQ_PROGRAM_CNTL_SET_VS_RESOURCE(sq_program_cntl_reg, vs_resource) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_RESOURCE_MASK) | (vs_resource << SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT) +#define SQ_PROGRAM_CNTL_SET_PS_RESOURCE(sq_program_cntl_reg, ps_resource) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_RESOURCE_MASK) | (ps_resource << SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT) +#define SQ_PROGRAM_CNTL_SET_PARAM_GEN(sq_program_cntl_reg, param_gen) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PARAM_GEN_MASK) | (param_gen << SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT) +#define SQ_PROGRAM_CNTL_SET_GEN_INDEX_PIX(sq_program_cntl_reg, gen_index_pix) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK) | (gen_index_pix << SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT) +#define SQ_PROGRAM_CNTL_SET_VS_EXPORT_COUNT(sq_program_cntl_reg, vs_export_count) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK) | (vs_export_count << SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT) +#define SQ_PROGRAM_CNTL_SET_VS_EXPORT_MODE(sq_program_cntl_reg, vs_export_mode) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK) | (vs_export_mode << SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT) +#define SQ_PROGRAM_CNTL_SET_PS_EXPORT_MODE(sq_program_cntl_reg, ps_export_mode) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK) | (ps_export_mode << SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT) +#define SQ_PROGRAM_CNTL_SET_GEN_INDEX_VTX(sq_program_cntl_reg, gen_index_vtx) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) | (gen_index_vtx << SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_program_cntl_t { + unsigned int vs_num_reg : SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE; + unsigned int : 2; + unsigned int ps_num_reg : SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE; + unsigned int : 2; + unsigned int vs_resource : SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE; + unsigned int ps_resource : SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE; + unsigned int param_gen : SQ_PROGRAM_CNTL_PARAM_GEN_SIZE; + unsigned int gen_index_pix : SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE; + unsigned int vs_export_count : SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE; + unsigned int vs_export_mode : SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE; + unsigned int ps_export_mode : SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE; + unsigned int gen_index_vtx : SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE; + } sq_program_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_program_cntl_t { + unsigned int gen_index_vtx : SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE; + unsigned int ps_export_mode : SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE; + unsigned int vs_export_mode : SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE; + unsigned int vs_export_count : SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE; + unsigned int gen_index_pix : SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE; + unsigned int param_gen : SQ_PROGRAM_CNTL_PARAM_GEN_SIZE; + unsigned int ps_resource : SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE; + unsigned int vs_resource : SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE; + unsigned int : 2; + unsigned int ps_num_reg : SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE; + unsigned int : 2; + unsigned int vs_num_reg : SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE; + } sq_program_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_program_cntl_t f; +} sq_program_cntl_u; + + +/* + * SQ_WRAPPING_0 struct + */ + +#define SQ_WRAPPING_0_PARAM_WRAP_0_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_1_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_2_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_3_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_4_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_5_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_6_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_7_SIZE 4 + +#define SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT 0 +#define SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT 4 +#define SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT 8 +#define SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT 12 +#define SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT 16 +#define SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT 20 +#define SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT 24 +#define SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT 28 + +#define SQ_WRAPPING_0_PARAM_WRAP_0_MASK 0x0000000f +#define SQ_WRAPPING_0_PARAM_WRAP_1_MASK 0x000000f0 +#define SQ_WRAPPING_0_PARAM_WRAP_2_MASK 0x00000f00 +#define SQ_WRAPPING_0_PARAM_WRAP_3_MASK 0x0000f000 +#define SQ_WRAPPING_0_PARAM_WRAP_4_MASK 0x000f0000 +#define SQ_WRAPPING_0_PARAM_WRAP_5_MASK 0x00f00000 +#define SQ_WRAPPING_0_PARAM_WRAP_6_MASK 0x0f000000 +#define SQ_WRAPPING_0_PARAM_WRAP_7_MASK 0xf0000000 + +#define SQ_WRAPPING_0_MASK \ + (SQ_WRAPPING_0_PARAM_WRAP_0_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_1_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_2_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_3_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_4_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_5_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_6_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_7_MASK) + +#define SQ_WRAPPING_0(param_wrap_0, param_wrap_1, param_wrap_2, param_wrap_3, param_wrap_4, param_wrap_5, param_wrap_6, param_wrap_7) \ + ((param_wrap_0 << SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT) | \ + (param_wrap_1 << SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT) | \ + (param_wrap_2 << SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT) | \ + (param_wrap_3 << SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT) | \ + (param_wrap_4 << SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT) | \ + (param_wrap_5 << SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT) | \ + (param_wrap_6 << SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT) | \ + (param_wrap_7 << SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT)) + +#define SQ_WRAPPING_0_GET_PARAM_WRAP_0(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_0_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_1(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_1_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_2(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_2_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_3(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_3_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_4(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_4_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_5(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_5_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_6(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_6_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_7(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_7_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT) + +#define SQ_WRAPPING_0_SET_PARAM_WRAP_0(sq_wrapping_0_reg, param_wrap_0) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_0_MASK) | (param_wrap_0 << SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_1(sq_wrapping_0_reg, param_wrap_1) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_1_MASK) | (param_wrap_1 << SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_2(sq_wrapping_0_reg, param_wrap_2) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_2_MASK) | (param_wrap_2 << SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_3(sq_wrapping_0_reg, param_wrap_3) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_3_MASK) | (param_wrap_3 << SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_4(sq_wrapping_0_reg, param_wrap_4) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_4_MASK) | (param_wrap_4 << SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_5(sq_wrapping_0_reg, param_wrap_5) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_5_MASK) | (param_wrap_5 << SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_6(sq_wrapping_0_reg, param_wrap_6) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_6_MASK) | (param_wrap_6 << SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_7(sq_wrapping_0_reg, param_wrap_7) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_7_MASK) | (param_wrap_7 << SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_wrapping_0_t { + unsigned int param_wrap_0 : SQ_WRAPPING_0_PARAM_WRAP_0_SIZE; + unsigned int param_wrap_1 : SQ_WRAPPING_0_PARAM_WRAP_1_SIZE; + unsigned int param_wrap_2 : SQ_WRAPPING_0_PARAM_WRAP_2_SIZE; + unsigned int param_wrap_3 : SQ_WRAPPING_0_PARAM_WRAP_3_SIZE; + unsigned int param_wrap_4 : SQ_WRAPPING_0_PARAM_WRAP_4_SIZE; + unsigned int param_wrap_5 : SQ_WRAPPING_0_PARAM_WRAP_5_SIZE; + unsigned int param_wrap_6 : SQ_WRAPPING_0_PARAM_WRAP_6_SIZE; + unsigned int param_wrap_7 : SQ_WRAPPING_0_PARAM_WRAP_7_SIZE; + } sq_wrapping_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_wrapping_0_t { + unsigned int param_wrap_7 : SQ_WRAPPING_0_PARAM_WRAP_7_SIZE; + unsigned int param_wrap_6 : SQ_WRAPPING_0_PARAM_WRAP_6_SIZE; + unsigned int param_wrap_5 : SQ_WRAPPING_0_PARAM_WRAP_5_SIZE; + unsigned int param_wrap_4 : SQ_WRAPPING_0_PARAM_WRAP_4_SIZE; + unsigned int param_wrap_3 : SQ_WRAPPING_0_PARAM_WRAP_3_SIZE; + unsigned int param_wrap_2 : SQ_WRAPPING_0_PARAM_WRAP_2_SIZE; + unsigned int param_wrap_1 : SQ_WRAPPING_0_PARAM_WRAP_1_SIZE; + unsigned int param_wrap_0 : SQ_WRAPPING_0_PARAM_WRAP_0_SIZE; + } sq_wrapping_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_wrapping_0_t f; +} sq_wrapping_0_u; + + +/* + * SQ_WRAPPING_1 struct + */ + +#define SQ_WRAPPING_1_PARAM_WRAP_8_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_9_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_10_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_11_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_12_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_13_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_14_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_15_SIZE 4 + +#define SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT 0 +#define SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT 4 +#define SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT 8 +#define SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT 12 +#define SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT 16 +#define SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT 20 +#define SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT 24 +#define SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT 28 + +#define SQ_WRAPPING_1_PARAM_WRAP_8_MASK 0x0000000f +#define SQ_WRAPPING_1_PARAM_WRAP_9_MASK 0x000000f0 +#define SQ_WRAPPING_1_PARAM_WRAP_10_MASK 0x00000f00 +#define SQ_WRAPPING_1_PARAM_WRAP_11_MASK 0x0000f000 +#define SQ_WRAPPING_1_PARAM_WRAP_12_MASK 0x000f0000 +#define SQ_WRAPPING_1_PARAM_WRAP_13_MASK 0x00f00000 +#define SQ_WRAPPING_1_PARAM_WRAP_14_MASK 0x0f000000 +#define SQ_WRAPPING_1_PARAM_WRAP_15_MASK 0xf0000000 + +#define SQ_WRAPPING_1_MASK \ + (SQ_WRAPPING_1_PARAM_WRAP_8_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_9_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_10_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_11_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_12_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_13_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_14_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_15_MASK) + +#define SQ_WRAPPING_1(param_wrap_8, param_wrap_9, param_wrap_10, param_wrap_11, param_wrap_12, param_wrap_13, param_wrap_14, param_wrap_15) \ + ((param_wrap_8 << SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT) | \ + (param_wrap_9 << SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT) | \ + (param_wrap_10 << SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT) | \ + (param_wrap_11 << SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT) | \ + (param_wrap_12 << SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT) | \ + (param_wrap_13 << SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT) | \ + (param_wrap_14 << SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT) | \ + (param_wrap_15 << SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT)) + +#define SQ_WRAPPING_1_GET_PARAM_WRAP_8(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_8_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_9(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_9_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_10(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_10_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_11(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_11_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_12(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_12_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_13(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_13_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_14(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_14_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_15(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_15_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT) + +#define SQ_WRAPPING_1_SET_PARAM_WRAP_8(sq_wrapping_1_reg, param_wrap_8) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_8_MASK) | (param_wrap_8 << SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_9(sq_wrapping_1_reg, param_wrap_9) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_9_MASK) | (param_wrap_9 << SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_10(sq_wrapping_1_reg, param_wrap_10) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_10_MASK) | (param_wrap_10 << SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_11(sq_wrapping_1_reg, param_wrap_11) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_11_MASK) | (param_wrap_11 << SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_12(sq_wrapping_1_reg, param_wrap_12) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_12_MASK) | (param_wrap_12 << SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_13(sq_wrapping_1_reg, param_wrap_13) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_13_MASK) | (param_wrap_13 << SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_14(sq_wrapping_1_reg, param_wrap_14) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_14_MASK) | (param_wrap_14 << SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_15(sq_wrapping_1_reg, param_wrap_15) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_15_MASK) | (param_wrap_15 << SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_wrapping_1_t { + unsigned int param_wrap_8 : SQ_WRAPPING_1_PARAM_WRAP_8_SIZE; + unsigned int param_wrap_9 : SQ_WRAPPING_1_PARAM_WRAP_9_SIZE; + unsigned int param_wrap_10 : SQ_WRAPPING_1_PARAM_WRAP_10_SIZE; + unsigned int param_wrap_11 : SQ_WRAPPING_1_PARAM_WRAP_11_SIZE; + unsigned int param_wrap_12 : SQ_WRAPPING_1_PARAM_WRAP_12_SIZE; + unsigned int param_wrap_13 : SQ_WRAPPING_1_PARAM_WRAP_13_SIZE; + unsigned int param_wrap_14 : SQ_WRAPPING_1_PARAM_WRAP_14_SIZE; + unsigned int param_wrap_15 : SQ_WRAPPING_1_PARAM_WRAP_15_SIZE; + } sq_wrapping_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_wrapping_1_t { + unsigned int param_wrap_15 : SQ_WRAPPING_1_PARAM_WRAP_15_SIZE; + unsigned int param_wrap_14 : SQ_WRAPPING_1_PARAM_WRAP_14_SIZE; + unsigned int param_wrap_13 : SQ_WRAPPING_1_PARAM_WRAP_13_SIZE; + unsigned int param_wrap_12 : SQ_WRAPPING_1_PARAM_WRAP_12_SIZE; + unsigned int param_wrap_11 : SQ_WRAPPING_1_PARAM_WRAP_11_SIZE; + unsigned int param_wrap_10 : SQ_WRAPPING_1_PARAM_WRAP_10_SIZE; + unsigned int param_wrap_9 : SQ_WRAPPING_1_PARAM_WRAP_9_SIZE; + unsigned int param_wrap_8 : SQ_WRAPPING_1_PARAM_WRAP_8_SIZE; + } sq_wrapping_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_wrapping_1_t f; +} sq_wrapping_1_u; + + +/* + * SQ_VS_CONST struct + */ + +#define SQ_VS_CONST_BASE_SIZE 9 +#define SQ_VS_CONST_SIZE_SIZE 9 + +#define SQ_VS_CONST_BASE_SHIFT 0 +#define SQ_VS_CONST_SIZE_SHIFT 12 + +#define SQ_VS_CONST_BASE_MASK 0x000001ff +#define SQ_VS_CONST_SIZE_MASK 0x001ff000 + +#define SQ_VS_CONST_MASK \ + (SQ_VS_CONST_BASE_MASK | \ + SQ_VS_CONST_SIZE_MASK) + +#define SQ_VS_CONST(base, size) \ + ((base << SQ_VS_CONST_BASE_SHIFT) | \ + (size << SQ_VS_CONST_SIZE_SHIFT)) + +#define SQ_VS_CONST_GET_BASE(sq_vs_const) \ + ((sq_vs_const & SQ_VS_CONST_BASE_MASK) >> SQ_VS_CONST_BASE_SHIFT) +#define SQ_VS_CONST_GET_SIZE(sq_vs_const) \ + ((sq_vs_const & SQ_VS_CONST_SIZE_MASK) >> SQ_VS_CONST_SIZE_SHIFT) + +#define SQ_VS_CONST_SET_BASE(sq_vs_const_reg, base) \ + sq_vs_const_reg = (sq_vs_const_reg & ~SQ_VS_CONST_BASE_MASK) | (base << SQ_VS_CONST_BASE_SHIFT) +#define SQ_VS_CONST_SET_SIZE(sq_vs_const_reg, size) \ + sq_vs_const_reg = (sq_vs_const_reg & ~SQ_VS_CONST_SIZE_MASK) | (size << SQ_VS_CONST_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_vs_const_t { + unsigned int base : SQ_VS_CONST_BASE_SIZE; + unsigned int : 3; + unsigned int size : SQ_VS_CONST_SIZE_SIZE; + unsigned int : 11; + } sq_vs_const_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_vs_const_t { + unsigned int : 11; + unsigned int size : SQ_VS_CONST_SIZE_SIZE; + unsigned int : 3; + unsigned int base : SQ_VS_CONST_BASE_SIZE; + } sq_vs_const_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_vs_const_t f; +} sq_vs_const_u; + + +/* + * SQ_PS_CONST struct + */ + +#define SQ_PS_CONST_BASE_SIZE 9 +#define SQ_PS_CONST_SIZE_SIZE 9 + +#define SQ_PS_CONST_BASE_SHIFT 0 +#define SQ_PS_CONST_SIZE_SHIFT 12 + +#define SQ_PS_CONST_BASE_MASK 0x000001ff +#define SQ_PS_CONST_SIZE_MASK 0x001ff000 + +#define SQ_PS_CONST_MASK \ + (SQ_PS_CONST_BASE_MASK | \ + SQ_PS_CONST_SIZE_MASK) + +#define SQ_PS_CONST(base, size) \ + ((base << SQ_PS_CONST_BASE_SHIFT) | \ + (size << SQ_PS_CONST_SIZE_SHIFT)) + +#define SQ_PS_CONST_GET_BASE(sq_ps_const) \ + ((sq_ps_const & SQ_PS_CONST_BASE_MASK) >> SQ_PS_CONST_BASE_SHIFT) +#define SQ_PS_CONST_GET_SIZE(sq_ps_const) \ + ((sq_ps_const & SQ_PS_CONST_SIZE_MASK) >> SQ_PS_CONST_SIZE_SHIFT) + +#define SQ_PS_CONST_SET_BASE(sq_ps_const_reg, base) \ + sq_ps_const_reg = (sq_ps_const_reg & ~SQ_PS_CONST_BASE_MASK) | (base << SQ_PS_CONST_BASE_SHIFT) +#define SQ_PS_CONST_SET_SIZE(sq_ps_const_reg, size) \ + sq_ps_const_reg = (sq_ps_const_reg & ~SQ_PS_CONST_SIZE_MASK) | (size << SQ_PS_CONST_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_ps_const_t { + unsigned int base : SQ_PS_CONST_BASE_SIZE; + unsigned int : 3; + unsigned int size : SQ_PS_CONST_SIZE_SIZE; + unsigned int : 11; + } sq_ps_const_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_ps_const_t { + unsigned int : 11; + unsigned int size : SQ_PS_CONST_SIZE_SIZE; + unsigned int : 3; + unsigned int base : SQ_PS_CONST_BASE_SIZE; + } sq_ps_const_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_ps_const_t f; +} sq_ps_const_u; + + +/* + * SQ_CONTEXT_MISC struct + */ + +#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE 1 +#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE 1 +#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE 2 +#define SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE 8 +#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE 1 +#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE 1 +#define SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE 1 + +#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT 0 +#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT 1 +#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT 2 +#define SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT 8 +#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT 16 +#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT 17 +#define SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT 18 + +#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK 0x00000001 +#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK 0x00000002 +#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK 0x0000000c +#define SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK 0x0000ff00 +#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK 0x00010000 +#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK 0x00020000 +#define SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK 0x00040000 + +#define SQ_CONTEXT_MISC_MASK \ + (SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK | \ + SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK | \ + SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK | \ + SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK | \ + SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK | \ + SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK | \ + SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) + +#define SQ_CONTEXT_MISC(inst_pred_optimize, sc_output_screen_xy, sc_sample_cntl, param_gen_pos, perfcounter_ref, yeild_optimize, tx_cache_sel) \ + ((inst_pred_optimize << SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT) | \ + (sc_output_screen_xy << SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT) | \ + (sc_sample_cntl << SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT) | \ + (param_gen_pos << SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT) | \ + (perfcounter_ref << SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT) | \ + (yeild_optimize << SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT) | \ + (tx_cache_sel << SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT)) + +#define SQ_CONTEXT_MISC_GET_INST_PRED_OPTIMIZE(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK) >> SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT) +#define SQ_CONTEXT_MISC_GET_SC_OUTPUT_SCREEN_XY(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK) >> SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT) +#define SQ_CONTEXT_MISC_GET_SC_SAMPLE_CNTL(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK) >> SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT) +#define SQ_CONTEXT_MISC_GET_PARAM_GEN_POS(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK) >> SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT) +#define SQ_CONTEXT_MISC_GET_PERFCOUNTER_REF(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK) >> SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT) +#define SQ_CONTEXT_MISC_GET_YEILD_OPTIMIZE(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK) >> SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT) +#define SQ_CONTEXT_MISC_GET_TX_CACHE_SEL(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) >> SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT) + +#define SQ_CONTEXT_MISC_SET_INST_PRED_OPTIMIZE(sq_context_misc_reg, inst_pred_optimize) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK) | (inst_pred_optimize << SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT) +#define SQ_CONTEXT_MISC_SET_SC_OUTPUT_SCREEN_XY(sq_context_misc_reg, sc_output_screen_xy) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK) | (sc_output_screen_xy << SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT) +#define SQ_CONTEXT_MISC_SET_SC_SAMPLE_CNTL(sq_context_misc_reg, sc_sample_cntl) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK) | (sc_sample_cntl << SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT) +#define SQ_CONTEXT_MISC_SET_PARAM_GEN_POS(sq_context_misc_reg, param_gen_pos) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK) | (param_gen_pos << SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT) +#define SQ_CONTEXT_MISC_SET_PERFCOUNTER_REF(sq_context_misc_reg, perfcounter_ref) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK) | (perfcounter_ref << SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT) +#define SQ_CONTEXT_MISC_SET_YEILD_OPTIMIZE(sq_context_misc_reg, yeild_optimize) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK) | (yeild_optimize << SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT) +#define SQ_CONTEXT_MISC_SET_TX_CACHE_SEL(sq_context_misc_reg, tx_cache_sel) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) | (tx_cache_sel << SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_context_misc_t { + unsigned int inst_pred_optimize : SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE; + unsigned int sc_output_screen_xy : SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE; + unsigned int sc_sample_cntl : SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE; + unsigned int : 4; + unsigned int param_gen_pos : SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE; + unsigned int perfcounter_ref : SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE; + unsigned int yeild_optimize : SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE; + unsigned int tx_cache_sel : SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE; + unsigned int : 13; + } sq_context_misc_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_context_misc_t { + unsigned int : 13; + unsigned int tx_cache_sel : SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE; + unsigned int yeild_optimize : SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE; + unsigned int perfcounter_ref : SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE; + unsigned int param_gen_pos : SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE; + unsigned int : 4; + unsigned int sc_sample_cntl : SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE; + unsigned int sc_output_screen_xy : SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE; + unsigned int inst_pred_optimize : SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE; + } sq_context_misc_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_context_misc_t f; +} sq_context_misc_u; + + +/* + * SQ_CF_RD_BASE struct + */ + +#define SQ_CF_RD_BASE_RD_BASE_SIZE 3 + +#define SQ_CF_RD_BASE_RD_BASE_SHIFT 0 + +#define SQ_CF_RD_BASE_RD_BASE_MASK 0x00000007 + +#define SQ_CF_RD_BASE_MASK \ + (SQ_CF_RD_BASE_RD_BASE_MASK) + +#define SQ_CF_RD_BASE(rd_base) \ + ((rd_base << SQ_CF_RD_BASE_RD_BASE_SHIFT)) + +#define SQ_CF_RD_BASE_GET_RD_BASE(sq_cf_rd_base) \ + ((sq_cf_rd_base & SQ_CF_RD_BASE_RD_BASE_MASK) >> SQ_CF_RD_BASE_RD_BASE_SHIFT) + +#define SQ_CF_RD_BASE_SET_RD_BASE(sq_cf_rd_base_reg, rd_base) \ + sq_cf_rd_base_reg = (sq_cf_rd_base_reg & ~SQ_CF_RD_BASE_RD_BASE_MASK) | (rd_base << SQ_CF_RD_BASE_RD_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_rd_base_t { + unsigned int rd_base : SQ_CF_RD_BASE_RD_BASE_SIZE; + unsigned int : 29; + } sq_cf_rd_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_rd_base_t { + unsigned int : 29; + unsigned int rd_base : SQ_CF_RD_BASE_RD_BASE_SIZE; + } sq_cf_rd_base_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_rd_base_t f; +} sq_cf_rd_base_u; + + +/* + * SQ_DEBUG_MISC_0 struct + */ + +#define SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE 1 +#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE 1 +#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE 11 +#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE 8 + +#define SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT 0 +#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT 4 +#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT 8 +#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT 24 + +#define SQ_DEBUG_MISC_0_DB_PROB_ON_MASK 0x00000001 +#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK 0x00000010 +#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK 0x0007ff00 +#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK 0xff000000 + +#define SQ_DEBUG_MISC_0_MASK \ + (SQ_DEBUG_MISC_0_DB_PROB_ON_MASK | \ + SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK | \ + SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK | \ + SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) + +#define SQ_DEBUG_MISC_0(db_prob_on, db_prob_break, db_prob_addr, db_prob_count) \ + ((db_prob_on << SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT) | \ + (db_prob_break << SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT) | \ + (db_prob_addr << SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT) | \ + (db_prob_count << SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT)) + +#define SQ_DEBUG_MISC_0_GET_DB_PROB_ON(sq_debug_misc_0) \ + ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_ON_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT) +#define SQ_DEBUG_MISC_0_GET_DB_PROB_BREAK(sq_debug_misc_0) \ + ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT) +#define SQ_DEBUG_MISC_0_GET_DB_PROB_ADDR(sq_debug_misc_0) \ + ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT) +#define SQ_DEBUG_MISC_0_GET_DB_PROB_COUNT(sq_debug_misc_0) \ + ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT) + +#define SQ_DEBUG_MISC_0_SET_DB_PROB_ON(sq_debug_misc_0_reg, db_prob_on) \ + sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_ON_MASK) | (db_prob_on << SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT) +#define SQ_DEBUG_MISC_0_SET_DB_PROB_BREAK(sq_debug_misc_0_reg, db_prob_break) \ + sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK) | (db_prob_break << SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT) +#define SQ_DEBUG_MISC_0_SET_DB_PROB_ADDR(sq_debug_misc_0_reg, db_prob_addr) \ + sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK) | (db_prob_addr << SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT) +#define SQ_DEBUG_MISC_0_SET_DB_PROB_COUNT(sq_debug_misc_0_reg, db_prob_count) \ + sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) | (db_prob_count << SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_misc_0_t { + unsigned int db_prob_on : SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE; + unsigned int : 3; + unsigned int db_prob_break : SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE; + unsigned int : 3; + unsigned int db_prob_addr : SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE; + unsigned int : 5; + unsigned int db_prob_count : SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE; + } sq_debug_misc_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_misc_0_t { + unsigned int db_prob_count : SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE; + unsigned int : 5; + unsigned int db_prob_addr : SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE; + unsigned int : 3; + unsigned int db_prob_break : SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE; + unsigned int : 3; + unsigned int db_prob_on : SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE; + } sq_debug_misc_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_misc_0_t f; +} sq_debug_misc_0_u; + + +/* + * SQ_DEBUG_MISC_1 struct + */ + +#define SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE 1 +#define SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE 1 +#define SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE 8 +#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE 11 + +#define SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT 0 +#define SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT 1 +#define SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT 8 +#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT 16 + +#define SQ_DEBUG_MISC_1_DB_ON_PIX_MASK 0x00000001 +#define SQ_DEBUG_MISC_1_DB_ON_VTX_MASK 0x00000002 +#define SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK 0x0000ff00 +#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK 0x07ff0000 + +#define SQ_DEBUG_MISC_1_MASK \ + (SQ_DEBUG_MISC_1_DB_ON_PIX_MASK | \ + SQ_DEBUG_MISC_1_DB_ON_VTX_MASK | \ + SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK | \ + SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) + +#define SQ_DEBUG_MISC_1(db_on_pix, db_on_vtx, db_inst_count, db_break_addr) \ + ((db_on_pix << SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT) | \ + (db_on_vtx << SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT) | \ + (db_inst_count << SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT) | \ + (db_break_addr << SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT)) + +#define SQ_DEBUG_MISC_1_GET_DB_ON_PIX(sq_debug_misc_1) \ + ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_ON_PIX_MASK) >> SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT) +#define SQ_DEBUG_MISC_1_GET_DB_ON_VTX(sq_debug_misc_1) \ + ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_ON_VTX_MASK) >> SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT) +#define SQ_DEBUG_MISC_1_GET_DB_INST_COUNT(sq_debug_misc_1) \ + ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK) >> SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT) +#define SQ_DEBUG_MISC_1_GET_DB_BREAK_ADDR(sq_debug_misc_1) \ + ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) >> SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT) + +#define SQ_DEBUG_MISC_1_SET_DB_ON_PIX(sq_debug_misc_1_reg, db_on_pix) \ + sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_ON_PIX_MASK) | (db_on_pix << SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT) +#define SQ_DEBUG_MISC_1_SET_DB_ON_VTX(sq_debug_misc_1_reg, db_on_vtx) \ + sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_ON_VTX_MASK) | (db_on_vtx << SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT) +#define SQ_DEBUG_MISC_1_SET_DB_INST_COUNT(sq_debug_misc_1_reg, db_inst_count) \ + sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK) | (db_inst_count << SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT) +#define SQ_DEBUG_MISC_1_SET_DB_BREAK_ADDR(sq_debug_misc_1_reg, db_break_addr) \ + sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) | (db_break_addr << SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_misc_1_t { + unsigned int db_on_pix : SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE; + unsigned int db_on_vtx : SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE; + unsigned int : 6; + unsigned int db_inst_count : SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE; + unsigned int db_break_addr : SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE; + unsigned int : 5; + } sq_debug_misc_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_misc_1_t { + unsigned int : 5; + unsigned int db_break_addr : SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE; + unsigned int db_inst_count : SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE; + unsigned int : 6; + unsigned int db_on_vtx : SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE; + unsigned int db_on_pix : SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE; + } sq_debug_misc_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_misc_1_t f; +} sq_debug_misc_1_u; + + +#endif + + +#if !defined (_SX_FIDDLE_H) +#define _SX_FIDDLE_H + +/***************************************************************************************************************** + * + * sx_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +#endif + + +#if !defined (_TP_FIDDLE_H) +#define _TP_FIDDLE_H + +/***************************************************************************************************************** + * + * tp_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * TC_CNTL_STATUS struct + */ + +#define TC_CNTL_STATUS_L2_INVALIDATE_SIZE 1 +#define TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE 2 +#define TC_CNTL_STATUS_TC_BUSY_SIZE 1 + +#define TC_CNTL_STATUS_L2_INVALIDATE_SHIFT 0 +#define TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT 18 +#define TC_CNTL_STATUS_TC_BUSY_SHIFT 31 + +#define TC_CNTL_STATUS_L2_INVALIDATE_MASK 0x00000001 +#define TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK 0x000c0000 +#define TC_CNTL_STATUS_TC_BUSY_MASK 0x80000000 + +#define TC_CNTL_STATUS_MASK \ + (TC_CNTL_STATUS_L2_INVALIDATE_MASK | \ + TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK | \ + TC_CNTL_STATUS_TC_BUSY_MASK) + +#define TC_CNTL_STATUS(l2_invalidate, tc_l2_hit_miss, tc_busy) \ + ((l2_invalidate << TC_CNTL_STATUS_L2_INVALIDATE_SHIFT) | \ + (tc_l2_hit_miss << TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT) | \ + (tc_busy << TC_CNTL_STATUS_TC_BUSY_SHIFT)) + +#define TC_CNTL_STATUS_GET_L2_INVALIDATE(tc_cntl_status) \ + ((tc_cntl_status & TC_CNTL_STATUS_L2_INVALIDATE_MASK) >> TC_CNTL_STATUS_L2_INVALIDATE_SHIFT) +#define TC_CNTL_STATUS_GET_TC_L2_HIT_MISS(tc_cntl_status) \ + ((tc_cntl_status & TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK) >> TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT) +#define TC_CNTL_STATUS_GET_TC_BUSY(tc_cntl_status) \ + ((tc_cntl_status & TC_CNTL_STATUS_TC_BUSY_MASK) >> TC_CNTL_STATUS_TC_BUSY_SHIFT) + +#define TC_CNTL_STATUS_SET_L2_INVALIDATE(tc_cntl_status_reg, l2_invalidate) \ + tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_L2_INVALIDATE_MASK) | (l2_invalidate << TC_CNTL_STATUS_L2_INVALIDATE_SHIFT) +#define TC_CNTL_STATUS_SET_TC_L2_HIT_MISS(tc_cntl_status_reg, tc_l2_hit_miss) \ + tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK) | (tc_l2_hit_miss << TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT) +#define TC_CNTL_STATUS_SET_TC_BUSY(tc_cntl_status_reg, tc_busy) \ + tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_TC_BUSY_MASK) | (tc_busy << TC_CNTL_STATUS_TC_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tc_cntl_status_t { + unsigned int l2_invalidate : TC_CNTL_STATUS_L2_INVALIDATE_SIZE; + unsigned int : 17; + unsigned int tc_l2_hit_miss : TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE; + unsigned int : 11; + unsigned int tc_busy : TC_CNTL_STATUS_TC_BUSY_SIZE; + } tc_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _tc_cntl_status_t { + unsigned int tc_busy : TC_CNTL_STATUS_TC_BUSY_SIZE; + unsigned int : 11; + unsigned int tc_l2_hit_miss : TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE; + unsigned int : 17; + unsigned int l2_invalidate : TC_CNTL_STATUS_L2_INVALIDATE_SIZE; + } tc_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + tc_cntl_status_t f; +} tc_cntl_status_u; + + +/* + * TCR_CHICKEN struct + */ + +#define TCR_CHICKEN_SPARE_SIZE 32 + +#define TCR_CHICKEN_SPARE_SHIFT 0 + +#define TCR_CHICKEN_SPARE_MASK 0xffffffff + +#define TCR_CHICKEN_MASK \ + (TCR_CHICKEN_SPARE_MASK) + +#define TCR_CHICKEN(spare) \ + ((spare << TCR_CHICKEN_SPARE_SHIFT)) + +#define TCR_CHICKEN_GET_SPARE(tcr_chicken) \ + ((tcr_chicken & TCR_CHICKEN_SPARE_MASK) >> TCR_CHICKEN_SPARE_SHIFT) + +#define TCR_CHICKEN_SET_SPARE(tcr_chicken_reg, spare) \ + tcr_chicken_reg = (tcr_chicken_reg & ~TCR_CHICKEN_SPARE_MASK) | (spare << TCR_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_chicken_t { + unsigned int spare : TCR_CHICKEN_SPARE_SIZE; + } tcr_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_chicken_t { + unsigned int spare : TCR_CHICKEN_SPARE_SIZE; + } tcr_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_chicken_t f; +} tcr_chicken_u; + + +/* + * TCF_CHICKEN struct + */ + +#define TCF_CHICKEN_SPARE_SIZE 32 + +#define TCF_CHICKEN_SPARE_SHIFT 0 + +#define TCF_CHICKEN_SPARE_MASK 0xffffffff + +#define TCF_CHICKEN_MASK \ + (TCF_CHICKEN_SPARE_MASK) + +#define TCF_CHICKEN(spare) \ + ((spare << TCF_CHICKEN_SPARE_SHIFT)) + +#define TCF_CHICKEN_GET_SPARE(tcf_chicken) \ + ((tcf_chicken & TCF_CHICKEN_SPARE_MASK) >> TCF_CHICKEN_SPARE_SHIFT) + +#define TCF_CHICKEN_SET_SPARE(tcf_chicken_reg, spare) \ + tcf_chicken_reg = (tcf_chicken_reg & ~TCF_CHICKEN_SPARE_MASK) | (spare << TCF_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_chicken_t { + unsigned int spare : TCF_CHICKEN_SPARE_SIZE; + } tcf_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_chicken_t { + unsigned int spare : TCF_CHICKEN_SPARE_SIZE; + } tcf_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_chicken_t f; +} tcf_chicken_u; + + +/* + * TCM_CHICKEN struct + */ + +#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE 8 +#define TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE 1 +#define TCM_CHICKEN_SPARE_SIZE 23 + +#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT 0 +#define TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT 8 +#define TCM_CHICKEN_SPARE_SHIFT 9 + +#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK 0x000000ff +#define TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK 0x00000100 +#define TCM_CHICKEN_SPARE_MASK 0xfffffe00 + +#define TCM_CHICKEN_MASK \ + (TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK | \ + TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK | \ + TCM_CHICKEN_SPARE_MASK) + +#define TCM_CHICKEN(tco_read_latency_fifo_prog_depth, etc_color_endian, spare) \ + ((tco_read_latency_fifo_prog_depth << TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT) | \ + (etc_color_endian << TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT) | \ + (spare << TCM_CHICKEN_SPARE_SHIFT)) + +#define TCM_CHICKEN_GET_TCO_READ_LATENCY_FIFO_PROG_DEPTH(tcm_chicken) \ + ((tcm_chicken & TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK) >> TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT) +#define TCM_CHICKEN_GET_ETC_COLOR_ENDIAN(tcm_chicken) \ + ((tcm_chicken & TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK) >> TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT) +#define TCM_CHICKEN_GET_SPARE(tcm_chicken) \ + ((tcm_chicken & TCM_CHICKEN_SPARE_MASK) >> TCM_CHICKEN_SPARE_SHIFT) + +#define TCM_CHICKEN_SET_TCO_READ_LATENCY_FIFO_PROG_DEPTH(tcm_chicken_reg, tco_read_latency_fifo_prog_depth) \ + tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK) | (tco_read_latency_fifo_prog_depth << TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT) +#define TCM_CHICKEN_SET_ETC_COLOR_ENDIAN(tcm_chicken_reg, etc_color_endian) \ + tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK) | (etc_color_endian << TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT) +#define TCM_CHICKEN_SET_SPARE(tcm_chicken_reg, spare) \ + tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_SPARE_MASK) | (spare << TCM_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_chicken_t { + unsigned int tco_read_latency_fifo_prog_depth : TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE; + unsigned int etc_color_endian : TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE; + unsigned int spare : TCM_CHICKEN_SPARE_SIZE; + } tcm_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_chicken_t { + unsigned int spare : TCM_CHICKEN_SPARE_SIZE; + unsigned int etc_color_endian : TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE; + unsigned int tco_read_latency_fifo_prog_depth : TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE; + } tcm_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_chicken_t f; +} tcm_chicken_u; + + +/* + * TCR_PERFCOUNTER0_SELECT struct + */ + +#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCR_PERFCOUNTER0_SELECT_MASK \ + (TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCR_PERFCOUNTER0_SELECT(perfcounter_select) \ + ((perfcounter_select << TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCR_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcr_perfcounter0_select) \ + ((tcr_perfcounter0_select & TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCR_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcr_perfcounter0_select_reg, perfcounter_select) \ + tcr_perfcounter0_select_reg = (tcr_perfcounter0_select_reg & ~TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_select_t { + unsigned int perfcounter_select : TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcr_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcr_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter0_select_t f; +} tcr_perfcounter0_select_u; + + +/* + * TCR_PERFCOUNTER1_SELECT struct + */ + +#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCR_PERFCOUNTER1_SELECT_MASK \ + (TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCR_PERFCOUNTER1_SELECT(perfcounter_select) \ + ((perfcounter_select << TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCR_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcr_perfcounter1_select) \ + ((tcr_perfcounter1_select & TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCR_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcr_perfcounter1_select_reg, perfcounter_select) \ + tcr_perfcounter1_select_reg = (tcr_perfcounter1_select_reg & ~TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_select_t { + unsigned int perfcounter_select : TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcr_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcr_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter1_select_t f; +} tcr_perfcounter1_select_u; + + +/* + * TCR_PERFCOUNTER0_HI struct + */ + +#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCR_PERFCOUNTER0_HI_MASK \ + (TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) + +#define TCR_PERFCOUNTER0_HI(perfcounter_hi) \ + ((perfcounter_hi << TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCR_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcr_perfcounter0_hi) \ + ((tcr_perfcounter0_hi & TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#define TCR_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcr_perfcounter0_hi_reg, perfcounter_hi) \ + tcr_perfcounter0_hi_reg = (tcr_perfcounter0_hi_reg & ~TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_hi_t { + unsigned int perfcounter_hi : TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcr_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + } tcr_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter0_hi_t f; +} tcr_perfcounter0_hi_u; + + +/* + * TCR_PERFCOUNTER1_HI struct + */ + +#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCR_PERFCOUNTER1_HI_MASK \ + (TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) + +#define TCR_PERFCOUNTER1_HI(perfcounter_hi) \ + ((perfcounter_hi << TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCR_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcr_perfcounter1_hi) \ + ((tcr_perfcounter1_hi & TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#define TCR_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcr_perfcounter1_hi_reg, perfcounter_hi) \ + tcr_perfcounter1_hi_reg = (tcr_perfcounter1_hi_reg & ~TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_hi_t { + unsigned int perfcounter_hi : TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcr_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + } tcr_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter1_hi_t f; +} tcr_perfcounter1_hi_u; + + +/* + * TCR_PERFCOUNTER0_LOW struct + */ + +#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCR_PERFCOUNTER0_LOW_MASK \ + (TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) + +#define TCR_PERFCOUNTER0_LOW(perfcounter_low) \ + ((perfcounter_low << TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCR_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcr_perfcounter0_low) \ + ((tcr_perfcounter0_low & TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCR_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcr_perfcounter0_low_reg, perfcounter_low) \ + tcr_perfcounter0_low_reg = (tcr_perfcounter0_low_reg & ~TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_low_t { + unsigned int perfcounter_low : TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcr_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_low_t { + unsigned int perfcounter_low : TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcr_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter0_low_t f; +} tcr_perfcounter0_low_u; + + +/* + * TCR_PERFCOUNTER1_LOW struct + */ + +#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCR_PERFCOUNTER1_LOW_MASK \ + (TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) + +#define TCR_PERFCOUNTER1_LOW(perfcounter_low) \ + ((perfcounter_low << TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCR_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcr_perfcounter1_low) \ + ((tcr_perfcounter1_low & TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCR_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcr_perfcounter1_low_reg, perfcounter_low) \ + tcr_perfcounter1_low_reg = (tcr_perfcounter1_low_reg & ~TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_low_t { + unsigned int perfcounter_low : TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcr_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_low_t { + unsigned int perfcounter_low : TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcr_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter1_low_t f; +} tcr_perfcounter1_low_u; + + +/* + * TP_TC_CLKGATE_CNTL struct + */ + +#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE 3 +#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE 3 + +#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT 0 +#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT 3 + +#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK 0x00000007 +#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK 0x00000038 + +#define TP_TC_CLKGATE_CNTL_MASK \ + (TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK | \ + TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) + +#define TP_TC_CLKGATE_CNTL(tp_busy_extend, tc_busy_extend) \ + ((tp_busy_extend << TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT) | \ + (tc_busy_extend << TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT)) + +#define TP_TC_CLKGATE_CNTL_GET_TP_BUSY_EXTEND(tp_tc_clkgate_cntl) \ + ((tp_tc_clkgate_cntl & TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK) >> TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT) +#define TP_TC_CLKGATE_CNTL_GET_TC_BUSY_EXTEND(tp_tc_clkgate_cntl) \ + ((tp_tc_clkgate_cntl & TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) >> TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT) + +#define TP_TC_CLKGATE_CNTL_SET_TP_BUSY_EXTEND(tp_tc_clkgate_cntl_reg, tp_busy_extend) \ + tp_tc_clkgate_cntl_reg = (tp_tc_clkgate_cntl_reg & ~TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK) | (tp_busy_extend << TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT) +#define TP_TC_CLKGATE_CNTL_SET_TC_BUSY_EXTEND(tp_tc_clkgate_cntl_reg, tc_busy_extend) \ + tp_tc_clkgate_cntl_reg = (tp_tc_clkgate_cntl_reg & ~TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) | (tc_busy_extend << TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp_tc_clkgate_cntl_t { + unsigned int tp_busy_extend : TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE; + unsigned int tc_busy_extend : TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE; + unsigned int : 26; + } tp_tc_clkgate_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp_tc_clkgate_cntl_t { + unsigned int : 26; + unsigned int tc_busy_extend : TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE; + unsigned int tp_busy_extend : TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE; + } tp_tc_clkgate_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + tp_tc_clkgate_cntl_t f; +} tp_tc_clkgate_cntl_u; + + +/* + * TPC_CNTL_STATUS struct + */ + +#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TF_TW_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TF_TW_RTR_SIZE 1 +#define TPC_CNTL_STATUS_TW_TA_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TW_TA_RTR_SIZE 1 +#define TPC_CNTL_STATUS_TA_TB_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TA_TB_RTR_SIZE 1 +#define TPC_CNTL_STATUS_TA_TF_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE 1 +#define TPC_CNTL_STATUS_TP_SQ_DEC_SIZE 1 +#define TPC_CNTL_STATUS_TPC_BUSY_SIZE 1 + +#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT 0 +#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT 1 +#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT 2 +#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT 3 +#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT 4 +#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT 5 +#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT 6 +#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT 8 +#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT 9 +#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT 10 +#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT 12 +#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT 13 +#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT 14 +#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT 15 +#define TPC_CNTL_STATUS_TF_TW_RTS_SHIFT 16 +#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT 17 +#define TPC_CNTL_STATUS_TF_TW_RTR_SHIFT 19 +#define TPC_CNTL_STATUS_TW_TA_RTS_SHIFT 20 +#define TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT 21 +#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT 22 +#define TPC_CNTL_STATUS_TW_TA_RTR_SHIFT 23 +#define TPC_CNTL_STATUS_TA_TB_RTS_SHIFT 24 +#define TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT 25 +#define TPC_CNTL_STATUS_TA_TB_RTR_SHIFT 27 +#define TPC_CNTL_STATUS_TA_TF_RTS_SHIFT 28 +#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT 29 +#define TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT 30 +#define TPC_CNTL_STATUS_TPC_BUSY_SHIFT 31 + +#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK 0x00000001 +#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK 0x00000002 +#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK 0x00000004 +#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK 0x00000008 +#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK 0x00000010 +#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK 0x00000020 +#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK 0x00000040 +#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK 0x00000100 +#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK 0x00000200 +#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK 0x00000400 +#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK 0x00001000 +#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK 0x00002000 +#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK 0x00004000 +#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK 0x00008000 +#define TPC_CNTL_STATUS_TF_TW_RTS_MASK 0x00010000 +#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK 0x00020000 +#define TPC_CNTL_STATUS_TF_TW_RTR_MASK 0x00080000 +#define TPC_CNTL_STATUS_TW_TA_RTS_MASK 0x00100000 +#define TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK 0x00200000 +#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK 0x00400000 +#define TPC_CNTL_STATUS_TW_TA_RTR_MASK 0x00800000 +#define TPC_CNTL_STATUS_TA_TB_RTS_MASK 0x01000000 +#define TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK 0x02000000 +#define TPC_CNTL_STATUS_TA_TB_RTR_MASK 0x08000000 +#define TPC_CNTL_STATUS_TA_TF_RTS_MASK 0x10000000 +#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK 0x20000000 +#define TPC_CNTL_STATUS_TP_SQ_DEC_MASK 0x40000000 +#define TPC_CNTL_STATUS_TPC_BUSY_MASK 0x80000000 + +#define TPC_CNTL_STATUS_MASK \ + (TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK | \ + TPC_CNTL_STATUS_TF_TW_RTS_MASK | \ + TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK | \ + TPC_CNTL_STATUS_TF_TW_RTR_MASK | \ + TPC_CNTL_STATUS_TW_TA_RTS_MASK | \ + TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK | \ + TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK | \ + TPC_CNTL_STATUS_TW_TA_RTR_MASK | \ + TPC_CNTL_STATUS_TA_TB_RTS_MASK | \ + TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK | \ + TPC_CNTL_STATUS_TA_TB_RTR_MASK | \ + TPC_CNTL_STATUS_TA_TF_RTS_MASK | \ + TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK | \ + TPC_CNTL_STATUS_TP_SQ_DEC_MASK | \ + TPC_CNTL_STATUS_TPC_BUSY_MASK) + +#define TPC_CNTL_STATUS(tpc_input_busy, tpc_tc_fifo_busy, tpc_state_fifo_busy, tpc_fetch_fifo_busy, tpc_walker_pipe_busy, tpc_walk_fifo_busy, tpc_walker_busy, tpc_aligner_pipe_busy, tpc_align_fifo_busy, tpc_aligner_busy, tpc_rr_fifo_busy, tpc_blend_pipe_busy, tpc_out_fifo_busy, tpc_blend_busy, tf_tw_rts, tf_tw_state_rts, tf_tw_rtr, tw_ta_rts, tw_ta_tt_rts, tw_ta_last_rts, tw_ta_rtr, ta_tb_rts, ta_tb_tt_rts, ta_tb_rtr, ta_tf_rts, ta_tf_tc_fifo_ren, tp_sq_dec, tpc_busy) \ + ((tpc_input_busy << TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT) | \ + (tpc_tc_fifo_busy << TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT) | \ + (tpc_state_fifo_busy << TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT) | \ + (tpc_fetch_fifo_busy << TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT) | \ + (tpc_walker_pipe_busy << TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT) | \ + (tpc_walk_fifo_busy << TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT) | \ + (tpc_walker_busy << TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT) | \ + (tpc_aligner_pipe_busy << TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT) | \ + (tpc_align_fifo_busy << TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT) | \ + (tpc_aligner_busy << TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT) | \ + (tpc_rr_fifo_busy << TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT) | \ + (tpc_blend_pipe_busy << TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT) | \ + (tpc_out_fifo_busy << TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT) | \ + (tpc_blend_busy << TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT) | \ + (tf_tw_rts << TPC_CNTL_STATUS_TF_TW_RTS_SHIFT) | \ + (tf_tw_state_rts << TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT) | \ + (tf_tw_rtr << TPC_CNTL_STATUS_TF_TW_RTR_SHIFT) | \ + (tw_ta_rts << TPC_CNTL_STATUS_TW_TA_RTS_SHIFT) | \ + (tw_ta_tt_rts << TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT) | \ + (tw_ta_last_rts << TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT) | \ + (tw_ta_rtr << TPC_CNTL_STATUS_TW_TA_RTR_SHIFT) | \ + (ta_tb_rts << TPC_CNTL_STATUS_TA_TB_RTS_SHIFT) | \ + (ta_tb_tt_rts << TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT) | \ + (ta_tb_rtr << TPC_CNTL_STATUS_TA_TB_RTR_SHIFT) | \ + (ta_tf_rts << TPC_CNTL_STATUS_TA_TF_RTS_SHIFT) | \ + (ta_tf_tc_fifo_ren << TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT) | \ + (tp_sq_dec << TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT) | \ + (tpc_busy << TPC_CNTL_STATUS_TPC_BUSY_SHIFT)) + +#define TPC_CNTL_STATUS_GET_TPC_INPUT_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_TC_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_STATE_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_FETCH_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_WALKER_PIPE_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_WALK_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_WALKER_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_ALIGNER_PIPE_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_ALIGN_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_ALIGNER_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_RR_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_BLEND_PIPE_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_OUT_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_BLEND_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TF_TW_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_RTS_MASK) >> TPC_CNTL_STATUS_TF_TW_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TF_TW_STATE_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK) >> TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TF_TW_RTR(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_RTR_MASK) >> TPC_CNTL_STATUS_TF_TW_RTR_SHIFT) +#define TPC_CNTL_STATUS_GET_TW_TA_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TW_TA_TT_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TW_TA_LAST_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TW_TA_RTR(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_RTR_MASK) >> TPC_CNTL_STATUS_TW_TA_RTR_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TB_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_RTS_MASK) >> TPC_CNTL_STATUS_TA_TB_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TB_TT_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK) >> TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TB_RTR(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_RTR_MASK) >> TPC_CNTL_STATUS_TA_TB_RTR_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TF_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TF_RTS_MASK) >> TPC_CNTL_STATUS_TA_TF_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TF_TC_FIFO_REN(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK) >> TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT) +#define TPC_CNTL_STATUS_GET_TP_SQ_DEC(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TP_SQ_DEC_MASK) >> TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BUSY_SHIFT) + +#define TPC_CNTL_STATUS_SET_TPC_INPUT_BUSY(tpc_cntl_status_reg, tpc_input_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK) | (tpc_input_busy << TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_TC_FIFO_BUSY(tpc_cntl_status_reg, tpc_tc_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK) | (tpc_tc_fifo_busy << TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_STATE_FIFO_BUSY(tpc_cntl_status_reg, tpc_state_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK) | (tpc_state_fifo_busy << TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_FETCH_FIFO_BUSY(tpc_cntl_status_reg, tpc_fetch_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK) | (tpc_fetch_fifo_busy << TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_WALKER_PIPE_BUSY(tpc_cntl_status_reg, tpc_walker_pipe_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK) | (tpc_walker_pipe_busy << TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_WALK_FIFO_BUSY(tpc_cntl_status_reg, tpc_walk_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK) | (tpc_walk_fifo_busy << TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_WALKER_BUSY(tpc_cntl_status_reg, tpc_walker_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK) | (tpc_walker_busy << TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_ALIGNER_PIPE_BUSY(tpc_cntl_status_reg, tpc_aligner_pipe_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK) | (tpc_aligner_pipe_busy << TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_ALIGN_FIFO_BUSY(tpc_cntl_status_reg, tpc_align_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK) | (tpc_align_fifo_busy << TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_ALIGNER_BUSY(tpc_cntl_status_reg, tpc_aligner_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK) | (tpc_aligner_busy << TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_RR_FIFO_BUSY(tpc_cntl_status_reg, tpc_rr_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK) | (tpc_rr_fifo_busy << TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_BLEND_PIPE_BUSY(tpc_cntl_status_reg, tpc_blend_pipe_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK) | (tpc_blend_pipe_busy << TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_OUT_FIFO_BUSY(tpc_cntl_status_reg, tpc_out_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK) | (tpc_out_fifo_busy << TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_BLEND_BUSY(tpc_cntl_status_reg, tpc_blend_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK) | (tpc_blend_busy << TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TF_TW_RTS(tpc_cntl_status_reg, tf_tw_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_RTS_MASK) | (tf_tw_rts << TPC_CNTL_STATUS_TF_TW_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TF_TW_STATE_RTS(tpc_cntl_status_reg, tf_tw_state_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK) | (tf_tw_state_rts << TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TF_TW_RTR(tpc_cntl_status_reg, tf_tw_rtr) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_RTR_MASK) | (tf_tw_rtr << TPC_CNTL_STATUS_TF_TW_RTR_SHIFT) +#define TPC_CNTL_STATUS_SET_TW_TA_RTS(tpc_cntl_status_reg, tw_ta_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_RTS_MASK) | (tw_ta_rts << TPC_CNTL_STATUS_TW_TA_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TW_TA_TT_RTS(tpc_cntl_status_reg, tw_ta_tt_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK) | (tw_ta_tt_rts << TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TW_TA_LAST_RTS(tpc_cntl_status_reg, tw_ta_last_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK) | (tw_ta_last_rts << TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TW_TA_RTR(tpc_cntl_status_reg, tw_ta_rtr) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_RTR_MASK) | (tw_ta_rtr << TPC_CNTL_STATUS_TW_TA_RTR_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TB_RTS(tpc_cntl_status_reg, ta_tb_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_RTS_MASK) | (ta_tb_rts << TPC_CNTL_STATUS_TA_TB_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TB_TT_RTS(tpc_cntl_status_reg, ta_tb_tt_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK) | (ta_tb_tt_rts << TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TB_RTR(tpc_cntl_status_reg, ta_tb_rtr) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_RTR_MASK) | (ta_tb_rtr << TPC_CNTL_STATUS_TA_TB_RTR_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TF_RTS(tpc_cntl_status_reg, ta_tf_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TF_RTS_MASK) | (ta_tf_rts << TPC_CNTL_STATUS_TA_TF_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TF_TC_FIFO_REN(tpc_cntl_status_reg, ta_tf_tc_fifo_ren) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK) | (ta_tf_tc_fifo_ren << TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT) +#define TPC_CNTL_STATUS_SET_TP_SQ_DEC(tpc_cntl_status_reg, tp_sq_dec) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TP_SQ_DEC_MASK) | (tp_sq_dec << TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_BUSY(tpc_cntl_status_reg, tpc_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BUSY_MASK) | (tpc_busy << TPC_CNTL_STATUS_TPC_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tpc_cntl_status_t { + unsigned int tpc_input_busy : TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE; + unsigned int tpc_tc_fifo_busy : TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE; + unsigned int tpc_state_fifo_busy : TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE; + unsigned int tpc_fetch_fifo_busy : TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE; + unsigned int tpc_walker_pipe_busy : TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE; + unsigned int tpc_walk_fifo_busy : TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE; + unsigned int tpc_walker_busy : TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_aligner_pipe_busy : TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE; + unsigned int tpc_align_fifo_busy : TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE; + unsigned int tpc_aligner_busy : TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_rr_fifo_busy : TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE; + unsigned int tpc_blend_pipe_busy : TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE; + unsigned int tpc_out_fifo_busy : TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE; + unsigned int tpc_blend_busy : TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE; + unsigned int tf_tw_rts : TPC_CNTL_STATUS_TF_TW_RTS_SIZE; + unsigned int tf_tw_state_rts : TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE; + unsigned int : 1; + unsigned int tf_tw_rtr : TPC_CNTL_STATUS_TF_TW_RTR_SIZE; + unsigned int tw_ta_rts : TPC_CNTL_STATUS_TW_TA_RTS_SIZE; + unsigned int tw_ta_tt_rts : TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE; + unsigned int tw_ta_last_rts : TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE; + unsigned int tw_ta_rtr : TPC_CNTL_STATUS_TW_TA_RTR_SIZE; + unsigned int ta_tb_rts : TPC_CNTL_STATUS_TA_TB_RTS_SIZE; + unsigned int ta_tb_tt_rts : TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE; + unsigned int : 1; + unsigned int ta_tb_rtr : TPC_CNTL_STATUS_TA_TB_RTR_SIZE; + unsigned int ta_tf_rts : TPC_CNTL_STATUS_TA_TF_RTS_SIZE; + unsigned int ta_tf_tc_fifo_ren : TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE; + unsigned int tp_sq_dec : TPC_CNTL_STATUS_TP_SQ_DEC_SIZE; + unsigned int tpc_busy : TPC_CNTL_STATUS_TPC_BUSY_SIZE; + } tpc_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _tpc_cntl_status_t { + unsigned int tpc_busy : TPC_CNTL_STATUS_TPC_BUSY_SIZE; + unsigned int tp_sq_dec : TPC_CNTL_STATUS_TP_SQ_DEC_SIZE; + unsigned int ta_tf_tc_fifo_ren : TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE; + unsigned int ta_tf_rts : TPC_CNTL_STATUS_TA_TF_RTS_SIZE; + unsigned int ta_tb_rtr : TPC_CNTL_STATUS_TA_TB_RTR_SIZE; + unsigned int : 1; + unsigned int ta_tb_tt_rts : TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE; + unsigned int ta_tb_rts : TPC_CNTL_STATUS_TA_TB_RTS_SIZE; + unsigned int tw_ta_rtr : TPC_CNTL_STATUS_TW_TA_RTR_SIZE; + unsigned int tw_ta_last_rts : TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE; + unsigned int tw_ta_tt_rts : TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE; + unsigned int tw_ta_rts : TPC_CNTL_STATUS_TW_TA_RTS_SIZE; + unsigned int tf_tw_rtr : TPC_CNTL_STATUS_TF_TW_RTR_SIZE; + unsigned int : 1; + unsigned int tf_tw_state_rts : TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE; + unsigned int tf_tw_rts : TPC_CNTL_STATUS_TF_TW_RTS_SIZE; + unsigned int tpc_blend_busy : TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE; + unsigned int tpc_out_fifo_busy : TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE; + unsigned int tpc_blend_pipe_busy : TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE; + unsigned int tpc_rr_fifo_busy : TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_aligner_busy : TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE; + unsigned int tpc_align_fifo_busy : TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE; + unsigned int tpc_aligner_pipe_busy : TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_walker_busy : TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE; + unsigned int tpc_walk_fifo_busy : TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE; + unsigned int tpc_walker_pipe_busy : TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE; + unsigned int tpc_fetch_fifo_busy : TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE; + unsigned int tpc_state_fifo_busy : TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE; + unsigned int tpc_tc_fifo_busy : TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE; + unsigned int tpc_input_busy : TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE; + } tpc_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + tpc_cntl_status_t f; +} tpc_cntl_status_u; + + +/* + * TPC_DEBUG0 struct + */ + +#define TPC_DEBUG0_LOD_CNTL_SIZE 2 +#define TPC_DEBUG0_IC_CTR_SIZE 2 +#define TPC_DEBUG0_WALKER_CNTL_SIZE 4 +#define TPC_DEBUG0_ALIGNER_CNTL_SIZE 3 +#define TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE 1 +#define TPC_DEBUG0_WALKER_STATE_SIZE 10 +#define TPC_DEBUG0_ALIGNER_STATE_SIZE 2 +#define TPC_DEBUG0_REG_CLK_EN_SIZE 1 +#define TPC_DEBUG0_TPC_CLK_EN_SIZE 1 +#define TPC_DEBUG0_SQ_TP_WAKEUP_SIZE 1 + +#define TPC_DEBUG0_LOD_CNTL_SHIFT 0 +#define TPC_DEBUG0_IC_CTR_SHIFT 2 +#define TPC_DEBUG0_WALKER_CNTL_SHIFT 4 +#define TPC_DEBUG0_ALIGNER_CNTL_SHIFT 8 +#define TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT 12 +#define TPC_DEBUG0_WALKER_STATE_SHIFT 16 +#define TPC_DEBUG0_ALIGNER_STATE_SHIFT 26 +#define TPC_DEBUG0_REG_CLK_EN_SHIFT 29 +#define TPC_DEBUG0_TPC_CLK_EN_SHIFT 30 +#define TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT 31 + +#define TPC_DEBUG0_LOD_CNTL_MASK 0x00000003 +#define TPC_DEBUG0_IC_CTR_MASK 0x0000000c +#define TPC_DEBUG0_WALKER_CNTL_MASK 0x000000f0 +#define TPC_DEBUG0_ALIGNER_CNTL_MASK 0x00000700 +#define TPC_DEBUG0_PREV_TC_STATE_VALID_MASK 0x00001000 +#define TPC_DEBUG0_WALKER_STATE_MASK 0x03ff0000 +#define TPC_DEBUG0_ALIGNER_STATE_MASK 0x0c000000 +#define TPC_DEBUG0_REG_CLK_EN_MASK 0x20000000 +#define TPC_DEBUG0_TPC_CLK_EN_MASK 0x40000000 +#define TPC_DEBUG0_SQ_TP_WAKEUP_MASK 0x80000000 + +#define TPC_DEBUG0_MASK \ + (TPC_DEBUG0_LOD_CNTL_MASK | \ + TPC_DEBUG0_IC_CTR_MASK | \ + TPC_DEBUG0_WALKER_CNTL_MASK | \ + TPC_DEBUG0_ALIGNER_CNTL_MASK | \ + TPC_DEBUG0_PREV_TC_STATE_VALID_MASK | \ + TPC_DEBUG0_WALKER_STATE_MASK | \ + TPC_DEBUG0_ALIGNER_STATE_MASK | \ + TPC_DEBUG0_REG_CLK_EN_MASK | \ + TPC_DEBUG0_TPC_CLK_EN_MASK | \ + TPC_DEBUG0_SQ_TP_WAKEUP_MASK) + +#define TPC_DEBUG0(lod_cntl, ic_ctr, walker_cntl, aligner_cntl, prev_tc_state_valid, walker_state, aligner_state, reg_clk_en, tpc_clk_en, sq_tp_wakeup) \ + ((lod_cntl << TPC_DEBUG0_LOD_CNTL_SHIFT) | \ + (ic_ctr << TPC_DEBUG0_IC_CTR_SHIFT) | \ + (walker_cntl << TPC_DEBUG0_WALKER_CNTL_SHIFT) | \ + (aligner_cntl << TPC_DEBUG0_ALIGNER_CNTL_SHIFT) | \ + (prev_tc_state_valid << TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT) | \ + (walker_state << TPC_DEBUG0_WALKER_STATE_SHIFT) | \ + (aligner_state << TPC_DEBUG0_ALIGNER_STATE_SHIFT) | \ + (reg_clk_en << TPC_DEBUG0_REG_CLK_EN_SHIFT) | \ + (tpc_clk_en << TPC_DEBUG0_TPC_CLK_EN_SHIFT) | \ + (sq_tp_wakeup << TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT)) + +#define TPC_DEBUG0_GET_LOD_CNTL(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_LOD_CNTL_MASK) >> TPC_DEBUG0_LOD_CNTL_SHIFT) +#define TPC_DEBUG0_GET_IC_CTR(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_IC_CTR_MASK) >> TPC_DEBUG0_IC_CTR_SHIFT) +#define TPC_DEBUG0_GET_WALKER_CNTL(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_WALKER_CNTL_MASK) >> TPC_DEBUG0_WALKER_CNTL_SHIFT) +#define TPC_DEBUG0_GET_ALIGNER_CNTL(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_ALIGNER_CNTL_MASK) >> TPC_DEBUG0_ALIGNER_CNTL_SHIFT) +#define TPC_DEBUG0_GET_PREV_TC_STATE_VALID(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_PREV_TC_STATE_VALID_MASK) >> TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT) +#define TPC_DEBUG0_GET_WALKER_STATE(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_WALKER_STATE_MASK) >> TPC_DEBUG0_WALKER_STATE_SHIFT) +#define TPC_DEBUG0_GET_ALIGNER_STATE(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_ALIGNER_STATE_MASK) >> TPC_DEBUG0_ALIGNER_STATE_SHIFT) +#define TPC_DEBUG0_GET_REG_CLK_EN(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_REG_CLK_EN_MASK) >> TPC_DEBUG0_REG_CLK_EN_SHIFT) +#define TPC_DEBUG0_GET_TPC_CLK_EN(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_TPC_CLK_EN_MASK) >> TPC_DEBUG0_TPC_CLK_EN_SHIFT) +#define TPC_DEBUG0_GET_SQ_TP_WAKEUP(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_SQ_TP_WAKEUP_MASK) >> TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT) + +#define TPC_DEBUG0_SET_LOD_CNTL(tpc_debug0_reg, lod_cntl) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_LOD_CNTL_MASK) | (lod_cntl << TPC_DEBUG0_LOD_CNTL_SHIFT) +#define TPC_DEBUG0_SET_IC_CTR(tpc_debug0_reg, ic_ctr) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_IC_CTR_MASK) | (ic_ctr << TPC_DEBUG0_IC_CTR_SHIFT) +#define TPC_DEBUG0_SET_WALKER_CNTL(tpc_debug0_reg, walker_cntl) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_WALKER_CNTL_MASK) | (walker_cntl << TPC_DEBUG0_WALKER_CNTL_SHIFT) +#define TPC_DEBUG0_SET_ALIGNER_CNTL(tpc_debug0_reg, aligner_cntl) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_ALIGNER_CNTL_MASK) | (aligner_cntl << TPC_DEBUG0_ALIGNER_CNTL_SHIFT) +#define TPC_DEBUG0_SET_PREV_TC_STATE_VALID(tpc_debug0_reg, prev_tc_state_valid) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_PREV_TC_STATE_VALID_MASK) | (prev_tc_state_valid << TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT) +#define TPC_DEBUG0_SET_WALKER_STATE(tpc_debug0_reg, walker_state) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_WALKER_STATE_MASK) | (walker_state << TPC_DEBUG0_WALKER_STATE_SHIFT) +#define TPC_DEBUG0_SET_ALIGNER_STATE(tpc_debug0_reg, aligner_state) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_ALIGNER_STATE_MASK) | (aligner_state << TPC_DEBUG0_ALIGNER_STATE_SHIFT) +#define TPC_DEBUG0_SET_REG_CLK_EN(tpc_debug0_reg, reg_clk_en) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_REG_CLK_EN_MASK) | (reg_clk_en << TPC_DEBUG0_REG_CLK_EN_SHIFT) +#define TPC_DEBUG0_SET_TPC_CLK_EN(tpc_debug0_reg, tpc_clk_en) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_TPC_CLK_EN_MASK) | (tpc_clk_en << TPC_DEBUG0_TPC_CLK_EN_SHIFT) +#define TPC_DEBUG0_SET_SQ_TP_WAKEUP(tpc_debug0_reg, sq_tp_wakeup) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_SQ_TP_WAKEUP_MASK) | (sq_tp_wakeup << TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tpc_debug0_t { + unsigned int lod_cntl : TPC_DEBUG0_LOD_CNTL_SIZE; + unsigned int ic_ctr : TPC_DEBUG0_IC_CTR_SIZE; + unsigned int walker_cntl : TPC_DEBUG0_WALKER_CNTL_SIZE; + unsigned int aligner_cntl : TPC_DEBUG0_ALIGNER_CNTL_SIZE; + unsigned int : 1; + unsigned int prev_tc_state_valid : TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE; + unsigned int : 3; + unsigned int walker_state : TPC_DEBUG0_WALKER_STATE_SIZE; + unsigned int aligner_state : TPC_DEBUG0_ALIGNER_STATE_SIZE; + unsigned int : 1; + unsigned int reg_clk_en : TPC_DEBUG0_REG_CLK_EN_SIZE; + unsigned int tpc_clk_en : TPC_DEBUG0_TPC_CLK_EN_SIZE; + unsigned int sq_tp_wakeup : TPC_DEBUG0_SQ_TP_WAKEUP_SIZE; + } tpc_debug0_t; + +#else // !BIGENDIAN_OS + + typedef struct _tpc_debug0_t { + unsigned int sq_tp_wakeup : TPC_DEBUG0_SQ_TP_WAKEUP_SIZE; + unsigned int tpc_clk_en : TPC_DEBUG0_TPC_CLK_EN_SIZE; + unsigned int reg_clk_en : TPC_DEBUG0_REG_CLK_EN_SIZE; + unsigned int : 1; + unsigned int aligner_state : TPC_DEBUG0_ALIGNER_STATE_SIZE; + unsigned int walker_state : TPC_DEBUG0_WALKER_STATE_SIZE; + unsigned int : 3; + unsigned int prev_tc_state_valid : TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE; + unsigned int : 1; + unsigned int aligner_cntl : TPC_DEBUG0_ALIGNER_CNTL_SIZE; + unsigned int walker_cntl : TPC_DEBUG0_WALKER_CNTL_SIZE; + unsigned int ic_ctr : TPC_DEBUG0_IC_CTR_SIZE; + unsigned int lod_cntl : TPC_DEBUG0_LOD_CNTL_SIZE; + } tpc_debug0_t; + +#endif + +typedef union { + unsigned int val : 32; + tpc_debug0_t f; +} tpc_debug0_u; + + +/* + * TPC_DEBUG1 struct + */ + +#define TPC_DEBUG1_UNUSED_SIZE 1 + +#define TPC_DEBUG1_UNUSED_SHIFT 0 + +#define TPC_DEBUG1_UNUSED_MASK 0x00000001 + +#define TPC_DEBUG1_MASK \ + (TPC_DEBUG1_UNUSED_MASK) + +#define TPC_DEBUG1(unused) \ + ((unused << TPC_DEBUG1_UNUSED_SHIFT)) + +#define TPC_DEBUG1_GET_UNUSED(tpc_debug1) \ + ((tpc_debug1 & TPC_DEBUG1_UNUSED_MASK) >> TPC_DEBUG1_UNUSED_SHIFT) + +#define TPC_DEBUG1_SET_UNUSED(tpc_debug1_reg, unused) \ + tpc_debug1_reg = (tpc_debug1_reg & ~TPC_DEBUG1_UNUSED_MASK) | (unused << TPC_DEBUG1_UNUSED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tpc_debug1_t { + unsigned int unused : TPC_DEBUG1_UNUSED_SIZE; + unsigned int : 31; + } tpc_debug1_t; + +#else // !BIGENDIAN_OS + + typedef struct _tpc_debug1_t { + unsigned int : 31; + unsigned int unused : TPC_DEBUG1_UNUSED_SIZE; + } tpc_debug1_t; + +#endif + +typedef union { + unsigned int val : 32; + tpc_debug1_t f; +} tpc_debug1_u; + + +/* + * TPC_CHICKEN struct + */ + +#define TPC_CHICKEN_BLEND_PRECISION_SIZE 1 +#define TPC_CHICKEN_SPARE_SIZE 31 + +#define TPC_CHICKEN_BLEND_PRECISION_SHIFT 0 +#define TPC_CHICKEN_SPARE_SHIFT 1 + +#define TPC_CHICKEN_BLEND_PRECISION_MASK 0x00000001 +#define TPC_CHICKEN_SPARE_MASK 0xfffffffe + +#define TPC_CHICKEN_MASK \ + (TPC_CHICKEN_BLEND_PRECISION_MASK | \ + TPC_CHICKEN_SPARE_MASK) + +#define TPC_CHICKEN(blend_precision, spare) \ + ((blend_precision << TPC_CHICKEN_BLEND_PRECISION_SHIFT) | \ + (spare << TPC_CHICKEN_SPARE_SHIFT)) + +#define TPC_CHICKEN_GET_BLEND_PRECISION(tpc_chicken) \ + ((tpc_chicken & TPC_CHICKEN_BLEND_PRECISION_MASK) >> TPC_CHICKEN_BLEND_PRECISION_SHIFT) +#define TPC_CHICKEN_GET_SPARE(tpc_chicken) \ + ((tpc_chicken & TPC_CHICKEN_SPARE_MASK) >> TPC_CHICKEN_SPARE_SHIFT) + +#define TPC_CHICKEN_SET_BLEND_PRECISION(tpc_chicken_reg, blend_precision) \ + tpc_chicken_reg = (tpc_chicken_reg & ~TPC_CHICKEN_BLEND_PRECISION_MASK) | (blend_precision << TPC_CHICKEN_BLEND_PRECISION_SHIFT) +#define TPC_CHICKEN_SET_SPARE(tpc_chicken_reg, spare) \ + tpc_chicken_reg = (tpc_chicken_reg & ~TPC_CHICKEN_SPARE_MASK) | (spare << TPC_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tpc_chicken_t { + unsigned int blend_precision : TPC_CHICKEN_BLEND_PRECISION_SIZE; + unsigned int spare : TPC_CHICKEN_SPARE_SIZE; + } tpc_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tpc_chicken_t { + unsigned int spare : TPC_CHICKEN_SPARE_SIZE; + unsigned int blend_precision : TPC_CHICKEN_BLEND_PRECISION_SIZE; + } tpc_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tpc_chicken_t f; +} tpc_chicken_u; + + +/* + * TP0_CNTL_STATUS struct + */ + +#define TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_TT_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_IN_LC_RTS_SIZE 1 +#define TP0_CNTL_STATUS_LC_LA_RTS_SIZE 1 +#define TP0_CNTL_STATUS_LA_FL_RTS_SIZE 1 +#define TP0_CNTL_STATUS_FL_TA_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TA_FA_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_FA_AL_RTS_SIZE 1 +#define TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_AL_TF_RTS_SIZE 1 +#define TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TF_TB_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TB_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE 1 +#define TP0_CNTL_STATUS_TB_TO_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TP_BUSY_SIZE 1 + +#define TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT 0 +#define TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT 1 +#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT 2 +#define TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT 3 +#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT 4 +#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT 5 +#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT 6 +#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT 7 +#define TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT 8 +#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT 9 +#define TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT 10 +#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT 11 +#define TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT 12 +#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT 13 +#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT 14 +#define TP0_CNTL_STATUS_IN_LC_RTS_SHIFT 16 +#define TP0_CNTL_STATUS_LC_LA_RTS_SHIFT 17 +#define TP0_CNTL_STATUS_LA_FL_RTS_SHIFT 18 +#define TP0_CNTL_STATUS_FL_TA_RTS_SHIFT 19 +#define TP0_CNTL_STATUS_TA_FA_RTS_SHIFT 20 +#define TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT 21 +#define TP0_CNTL_STATUS_FA_AL_RTS_SHIFT 22 +#define TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT 23 +#define TP0_CNTL_STATUS_AL_TF_RTS_SHIFT 24 +#define TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT 25 +#define TP0_CNTL_STATUS_TF_TB_RTS_SHIFT 26 +#define TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT 27 +#define TP0_CNTL_STATUS_TB_TT_RTS_SHIFT 28 +#define TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT 29 +#define TP0_CNTL_STATUS_TB_TO_RTS_SHIFT 30 +#define TP0_CNTL_STATUS_TP_BUSY_SHIFT 31 + +#define TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK 0x00000001 +#define TP0_CNTL_STATUS_TP_LOD_BUSY_MASK 0x00000002 +#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK 0x00000004 +#define TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK 0x00000008 +#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK 0x00000010 +#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK 0x00000020 +#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK 0x00000040 +#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK 0x00000080 +#define TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK 0x00000100 +#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK 0x00000200 +#define TP0_CNTL_STATUS_TP_TT_BUSY_MASK 0x00000400 +#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK 0x00000800 +#define TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK 0x00001000 +#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK 0x00002000 +#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK 0x00004000 +#define TP0_CNTL_STATUS_IN_LC_RTS_MASK 0x00010000 +#define TP0_CNTL_STATUS_LC_LA_RTS_MASK 0x00020000 +#define TP0_CNTL_STATUS_LA_FL_RTS_MASK 0x00040000 +#define TP0_CNTL_STATUS_FL_TA_RTS_MASK 0x00080000 +#define TP0_CNTL_STATUS_TA_FA_RTS_MASK 0x00100000 +#define TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK 0x00200000 +#define TP0_CNTL_STATUS_FA_AL_RTS_MASK 0x00400000 +#define TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK 0x00800000 +#define TP0_CNTL_STATUS_AL_TF_RTS_MASK 0x01000000 +#define TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK 0x02000000 +#define TP0_CNTL_STATUS_TF_TB_RTS_MASK 0x04000000 +#define TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK 0x08000000 +#define TP0_CNTL_STATUS_TB_TT_RTS_MASK 0x10000000 +#define TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK 0x20000000 +#define TP0_CNTL_STATUS_TB_TO_RTS_MASK 0x40000000 +#define TP0_CNTL_STATUS_TP_BUSY_MASK 0x80000000 + +#define TP0_CNTL_STATUS_MASK \ + (TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_LOD_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_TT_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK | \ + TP0_CNTL_STATUS_IN_LC_RTS_MASK | \ + TP0_CNTL_STATUS_LC_LA_RTS_MASK | \ + TP0_CNTL_STATUS_LA_FL_RTS_MASK | \ + TP0_CNTL_STATUS_FL_TA_RTS_MASK | \ + TP0_CNTL_STATUS_TA_FA_RTS_MASK | \ + TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK | \ + TP0_CNTL_STATUS_FA_AL_RTS_MASK | \ + TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK | \ + TP0_CNTL_STATUS_AL_TF_RTS_MASK | \ + TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK | \ + TP0_CNTL_STATUS_TF_TB_RTS_MASK | \ + TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK | \ + TP0_CNTL_STATUS_TB_TT_RTS_MASK | \ + TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK | \ + TP0_CNTL_STATUS_TB_TO_RTS_MASK | \ + TP0_CNTL_STATUS_TP_BUSY_MASK) + +#define TP0_CNTL_STATUS(tp_input_busy, tp_lod_busy, tp_lod_fifo_busy, tp_addr_busy, tp_align_fifo_busy, tp_aligner_busy, tp_tc_fifo_busy, tp_rr_fifo_busy, tp_fetch_busy, tp_ch_blend_busy, tp_tt_busy, tp_hicolor_busy, tp_blend_busy, tp_out_fifo_busy, tp_output_busy, in_lc_rts, lc_la_rts, la_fl_rts, fl_ta_rts, ta_fa_rts, ta_fa_tt_rts, fa_al_rts, fa_al_tt_rts, al_tf_rts, al_tf_tt_rts, tf_tb_rts, tf_tb_tt_rts, tb_tt_rts, tb_tt_tt_reset, tb_to_rts, tp_busy) \ + ((tp_input_busy << TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT) | \ + (tp_lod_busy << TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT) | \ + (tp_lod_fifo_busy << TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT) | \ + (tp_addr_busy << TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT) | \ + (tp_align_fifo_busy << TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT) | \ + (tp_aligner_busy << TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT) | \ + (tp_tc_fifo_busy << TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT) | \ + (tp_rr_fifo_busy << TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT) | \ + (tp_fetch_busy << TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT) | \ + (tp_ch_blend_busy << TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT) | \ + (tp_tt_busy << TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT) | \ + (tp_hicolor_busy << TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT) | \ + (tp_blend_busy << TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT) | \ + (tp_out_fifo_busy << TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT) | \ + (tp_output_busy << TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT) | \ + (in_lc_rts << TP0_CNTL_STATUS_IN_LC_RTS_SHIFT) | \ + (lc_la_rts << TP0_CNTL_STATUS_LC_LA_RTS_SHIFT) | \ + (la_fl_rts << TP0_CNTL_STATUS_LA_FL_RTS_SHIFT) | \ + (fl_ta_rts << TP0_CNTL_STATUS_FL_TA_RTS_SHIFT) | \ + (ta_fa_rts << TP0_CNTL_STATUS_TA_FA_RTS_SHIFT) | \ + (ta_fa_tt_rts << TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT) | \ + (fa_al_rts << TP0_CNTL_STATUS_FA_AL_RTS_SHIFT) | \ + (fa_al_tt_rts << TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT) | \ + (al_tf_rts << TP0_CNTL_STATUS_AL_TF_RTS_SHIFT) | \ + (al_tf_tt_rts << TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT) | \ + (tf_tb_rts << TP0_CNTL_STATUS_TF_TB_RTS_SHIFT) | \ + (tf_tb_tt_rts << TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT) | \ + (tb_tt_rts << TP0_CNTL_STATUS_TB_TT_RTS_SHIFT) | \ + (tb_tt_tt_reset << TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT) | \ + (tb_to_rts << TP0_CNTL_STATUS_TB_TO_RTS_SHIFT) | \ + (tp_busy << TP0_CNTL_STATUS_TP_BUSY_SHIFT)) + +#define TP0_CNTL_STATUS_GET_TP_INPUT_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_LOD_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_LOD_BUSY_MASK) >> TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_LOD_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_ADDR_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_ALIGN_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_ALIGNER_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_TC_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_RR_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_FETCH_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK) >> TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_CH_BLEND_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK) >> TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_TT_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_TT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_HICOLOR_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK) >> TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_BLEND_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK) >> TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_OUT_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_OUTPUT_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_IN_LC_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_IN_LC_RTS_MASK) >> TP0_CNTL_STATUS_IN_LC_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_LC_LA_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_LC_LA_RTS_MASK) >> TP0_CNTL_STATUS_LC_LA_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_LA_FL_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_LA_FL_RTS_MASK) >> TP0_CNTL_STATUS_LA_FL_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_FL_TA_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_FL_TA_RTS_MASK) >> TP0_CNTL_STATUS_FL_TA_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TA_FA_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TA_FA_RTS_MASK) >> TP0_CNTL_STATUS_TA_FA_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TA_FA_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK) >> TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_FA_AL_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_FA_AL_RTS_MASK) >> TP0_CNTL_STATUS_FA_AL_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_FA_AL_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK) >> TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_AL_TF_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_AL_TF_RTS_MASK) >> TP0_CNTL_STATUS_AL_TF_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_AL_TF_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK) >> TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TF_TB_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TF_TB_RTS_MASK) >> TP0_CNTL_STATUS_TF_TB_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TF_TB_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK) >> TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TB_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TT_RTS_MASK) >> TP0_CNTL_STATUS_TB_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TB_TT_TT_RESET(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK) >> TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT) +#define TP0_CNTL_STATUS_GET_TB_TO_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TO_RTS_MASK) >> TP0_CNTL_STATUS_TB_TO_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_BUSY_MASK) >> TP0_CNTL_STATUS_TP_BUSY_SHIFT) + +#define TP0_CNTL_STATUS_SET_TP_INPUT_BUSY(tp0_cntl_status_reg, tp_input_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK) | (tp_input_busy << TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_LOD_BUSY(tp0_cntl_status_reg, tp_lod_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_LOD_BUSY_MASK) | (tp_lod_busy << TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_LOD_FIFO_BUSY(tp0_cntl_status_reg, tp_lod_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK) | (tp_lod_fifo_busy << TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_ADDR_BUSY(tp0_cntl_status_reg, tp_addr_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK) | (tp_addr_busy << TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_ALIGN_FIFO_BUSY(tp0_cntl_status_reg, tp_align_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK) | (tp_align_fifo_busy << TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_ALIGNER_BUSY(tp0_cntl_status_reg, tp_aligner_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK) | (tp_aligner_busy << TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_TC_FIFO_BUSY(tp0_cntl_status_reg, tp_tc_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK) | (tp_tc_fifo_busy << TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_RR_FIFO_BUSY(tp0_cntl_status_reg, tp_rr_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK) | (tp_rr_fifo_busy << TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_FETCH_BUSY(tp0_cntl_status_reg, tp_fetch_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK) | (tp_fetch_busy << TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_CH_BLEND_BUSY(tp0_cntl_status_reg, tp_ch_blend_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK) | (tp_ch_blend_busy << TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_TT_BUSY(tp0_cntl_status_reg, tp_tt_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_TT_BUSY_MASK) | (tp_tt_busy << TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_HICOLOR_BUSY(tp0_cntl_status_reg, tp_hicolor_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK) | (tp_hicolor_busy << TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_BLEND_BUSY(tp0_cntl_status_reg, tp_blend_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK) | (tp_blend_busy << TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_OUT_FIFO_BUSY(tp0_cntl_status_reg, tp_out_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK) | (tp_out_fifo_busy << TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_OUTPUT_BUSY(tp0_cntl_status_reg, tp_output_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK) | (tp_output_busy << TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_IN_LC_RTS(tp0_cntl_status_reg, in_lc_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_IN_LC_RTS_MASK) | (in_lc_rts << TP0_CNTL_STATUS_IN_LC_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_LC_LA_RTS(tp0_cntl_status_reg, lc_la_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_LC_LA_RTS_MASK) | (lc_la_rts << TP0_CNTL_STATUS_LC_LA_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_LA_FL_RTS(tp0_cntl_status_reg, la_fl_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_LA_FL_RTS_MASK) | (la_fl_rts << TP0_CNTL_STATUS_LA_FL_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_FL_TA_RTS(tp0_cntl_status_reg, fl_ta_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FL_TA_RTS_MASK) | (fl_ta_rts << TP0_CNTL_STATUS_FL_TA_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TA_FA_RTS(tp0_cntl_status_reg, ta_fa_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TA_FA_RTS_MASK) | (ta_fa_rts << TP0_CNTL_STATUS_TA_FA_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TA_FA_TT_RTS(tp0_cntl_status_reg, ta_fa_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK) | (ta_fa_tt_rts << TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_FA_AL_RTS(tp0_cntl_status_reg, fa_al_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FA_AL_RTS_MASK) | (fa_al_rts << TP0_CNTL_STATUS_FA_AL_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_FA_AL_TT_RTS(tp0_cntl_status_reg, fa_al_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK) | (fa_al_tt_rts << TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_AL_TF_RTS(tp0_cntl_status_reg, al_tf_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_AL_TF_RTS_MASK) | (al_tf_rts << TP0_CNTL_STATUS_AL_TF_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_AL_TF_TT_RTS(tp0_cntl_status_reg, al_tf_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK) | (al_tf_tt_rts << TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TF_TB_RTS(tp0_cntl_status_reg, tf_tb_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TF_TB_RTS_MASK) | (tf_tb_rts << TP0_CNTL_STATUS_TF_TB_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TF_TB_TT_RTS(tp0_cntl_status_reg, tf_tb_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK) | (tf_tb_tt_rts << TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TB_TT_RTS(tp0_cntl_status_reg, tb_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TT_RTS_MASK) | (tb_tt_rts << TP0_CNTL_STATUS_TB_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TB_TT_TT_RESET(tp0_cntl_status_reg, tb_tt_tt_reset) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK) | (tb_tt_tt_reset << TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT) +#define TP0_CNTL_STATUS_SET_TB_TO_RTS(tp0_cntl_status_reg, tb_to_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TO_RTS_MASK) | (tb_to_rts << TP0_CNTL_STATUS_TB_TO_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_BUSY(tp0_cntl_status_reg, tp_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_BUSY_MASK) | (tp_busy << TP0_CNTL_STATUS_TP_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_cntl_status_t { + unsigned int tp_input_busy : TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE; + unsigned int tp_lod_busy : TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE; + unsigned int tp_lod_fifo_busy : TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE; + unsigned int tp_addr_busy : TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE; + unsigned int tp_align_fifo_busy : TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE; + unsigned int tp_aligner_busy : TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE; + unsigned int tp_tc_fifo_busy : TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE; + unsigned int tp_rr_fifo_busy : TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE; + unsigned int tp_fetch_busy : TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE; + unsigned int tp_ch_blend_busy : TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE; + unsigned int tp_tt_busy : TP0_CNTL_STATUS_TP_TT_BUSY_SIZE; + unsigned int tp_hicolor_busy : TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE; + unsigned int tp_blend_busy : TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE; + unsigned int tp_out_fifo_busy : TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE; + unsigned int tp_output_busy : TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE; + unsigned int : 1; + unsigned int in_lc_rts : TP0_CNTL_STATUS_IN_LC_RTS_SIZE; + unsigned int lc_la_rts : TP0_CNTL_STATUS_LC_LA_RTS_SIZE; + unsigned int la_fl_rts : TP0_CNTL_STATUS_LA_FL_RTS_SIZE; + unsigned int fl_ta_rts : TP0_CNTL_STATUS_FL_TA_RTS_SIZE; + unsigned int ta_fa_rts : TP0_CNTL_STATUS_TA_FA_RTS_SIZE; + unsigned int ta_fa_tt_rts : TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE; + unsigned int fa_al_rts : TP0_CNTL_STATUS_FA_AL_RTS_SIZE; + unsigned int fa_al_tt_rts : TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE; + unsigned int al_tf_rts : TP0_CNTL_STATUS_AL_TF_RTS_SIZE; + unsigned int al_tf_tt_rts : TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE; + unsigned int tf_tb_rts : TP0_CNTL_STATUS_TF_TB_RTS_SIZE; + unsigned int tf_tb_tt_rts : TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE; + unsigned int tb_tt_rts : TP0_CNTL_STATUS_TB_TT_RTS_SIZE; + unsigned int tb_tt_tt_reset : TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE; + unsigned int tb_to_rts : TP0_CNTL_STATUS_TB_TO_RTS_SIZE; + unsigned int tp_busy : TP0_CNTL_STATUS_TP_BUSY_SIZE; + } tp0_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_cntl_status_t { + unsigned int tp_busy : TP0_CNTL_STATUS_TP_BUSY_SIZE; + unsigned int tb_to_rts : TP0_CNTL_STATUS_TB_TO_RTS_SIZE; + unsigned int tb_tt_tt_reset : TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE; + unsigned int tb_tt_rts : TP0_CNTL_STATUS_TB_TT_RTS_SIZE; + unsigned int tf_tb_tt_rts : TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE; + unsigned int tf_tb_rts : TP0_CNTL_STATUS_TF_TB_RTS_SIZE; + unsigned int al_tf_tt_rts : TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE; + unsigned int al_tf_rts : TP0_CNTL_STATUS_AL_TF_RTS_SIZE; + unsigned int fa_al_tt_rts : TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE; + unsigned int fa_al_rts : TP0_CNTL_STATUS_FA_AL_RTS_SIZE; + unsigned int ta_fa_tt_rts : TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE; + unsigned int ta_fa_rts : TP0_CNTL_STATUS_TA_FA_RTS_SIZE; + unsigned int fl_ta_rts : TP0_CNTL_STATUS_FL_TA_RTS_SIZE; + unsigned int la_fl_rts : TP0_CNTL_STATUS_LA_FL_RTS_SIZE; + unsigned int lc_la_rts : TP0_CNTL_STATUS_LC_LA_RTS_SIZE; + unsigned int in_lc_rts : TP0_CNTL_STATUS_IN_LC_RTS_SIZE; + unsigned int : 1; + unsigned int tp_output_busy : TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE; + unsigned int tp_out_fifo_busy : TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE; + unsigned int tp_blend_busy : TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE; + unsigned int tp_hicolor_busy : TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE; + unsigned int tp_tt_busy : TP0_CNTL_STATUS_TP_TT_BUSY_SIZE; + unsigned int tp_ch_blend_busy : TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE; + unsigned int tp_fetch_busy : TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE; + unsigned int tp_rr_fifo_busy : TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE; + unsigned int tp_tc_fifo_busy : TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE; + unsigned int tp_aligner_busy : TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE; + unsigned int tp_align_fifo_busy : TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE; + unsigned int tp_addr_busy : TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE; + unsigned int tp_lod_fifo_busy : TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE; + unsigned int tp_lod_busy : TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE; + unsigned int tp_input_busy : TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE; + } tp0_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_cntl_status_t f; +} tp0_cntl_status_u; + + +/* + * TP0_DEBUG struct + */ + +#define TP0_DEBUG_Q_LOD_CNTL_SIZE 2 +#define TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE 1 +#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE 17 +#define TP0_DEBUG_REG_CLK_EN_SIZE 1 +#define TP0_DEBUG_PERF_CLK_EN_SIZE 1 +#define TP0_DEBUG_TP_CLK_EN_SIZE 1 +#define TP0_DEBUG_Q_WALKER_CNTL_SIZE 4 +#define TP0_DEBUG_Q_ALIGNER_CNTL_SIZE 3 + +#define TP0_DEBUG_Q_LOD_CNTL_SHIFT 0 +#define TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT 3 +#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT 4 +#define TP0_DEBUG_REG_CLK_EN_SHIFT 21 +#define TP0_DEBUG_PERF_CLK_EN_SHIFT 22 +#define TP0_DEBUG_TP_CLK_EN_SHIFT 23 +#define TP0_DEBUG_Q_WALKER_CNTL_SHIFT 24 +#define TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT 28 + +#define TP0_DEBUG_Q_LOD_CNTL_MASK 0x00000003 +#define TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK 0x00000008 +#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK 0x001ffff0 +#define TP0_DEBUG_REG_CLK_EN_MASK 0x00200000 +#define TP0_DEBUG_PERF_CLK_EN_MASK 0x00400000 +#define TP0_DEBUG_TP_CLK_EN_MASK 0x00800000 +#define TP0_DEBUG_Q_WALKER_CNTL_MASK 0x0f000000 +#define TP0_DEBUG_Q_ALIGNER_CNTL_MASK 0x70000000 + +#define TP0_DEBUG_MASK \ + (TP0_DEBUG_Q_LOD_CNTL_MASK | \ + TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK | \ + TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK | \ + TP0_DEBUG_REG_CLK_EN_MASK | \ + TP0_DEBUG_PERF_CLK_EN_MASK | \ + TP0_DEBUG_TP_CLK_EN_MASK | \ + TP0_DEBUG_Q_WALKER_CNTL_MASK | \ + TP0_DEBUG_Q_ALIGNER_CNTL_MASK) + +#define TP0_DEBUG(q_lod_cntl, q_sq_tp_wakeup, fl_ta_addresser_cntl, reg_clk_en, perf_clk_en, tp_clk_en, q_walker_cntl, q_aligner_cntl) \ + ((q_lod_cntl << TP0_DEBUG_Q_LOD_CNTL_SHIFT) | \ + (q_sq_tp_wakeup << TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT) | \ + (fl_ta_addresser_cntl << TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT) | \ + (reg_clk_en << TP0_DEBUG_REG_CLK_EN_SHIFT) | \ + (perf_clk_en << TP0_DEBUG_PERF_CLK_EN_SHIFT) | \ + (tp_clk_en << TP0_DEBUG_TP_CLK_EN_SHIFT) | \ + (q_walker_cntl << TP0_DEBUG_Q_WALKER_CNTL_SHIFT) | \ + (q_aligner_cntl << TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT)) + +#define TP0_DEBUG_GET_Q_LOD_CNTL(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_Q_LOD_CNTL_MASK) >> TP0_DEBUG_Q_LOD_CNTL_SHIFT) +#define TP0_DEBUG_GET_Q_SQ_TP_WAKEUP(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK) >> TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT) +#define TP0_DEBUG_GET_FL_TA_ADDRESSER_CNTL(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK) >> TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT) +#define TP0_DEBUG_GET_REG_CLK_EN(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_REG_CLK_EN_MASK) >> TP0_DEBUG_REG_CLK_EN_SHIFT) +#define TP0_DEBUG_GET_PERF_CLK_EN(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_PERF_CLK_EN_MASK) >> TP0_DEBUG_PERF_CLK_EN_SHIFT) +#define TP0_DEBUG_GET_TP_CLK_EN(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_TP_CLK_EN_MASK) >> TP0_DEBUG_TP_CLK_EN_SHIFT) +#define TP0_DEBUG_GET_Q_WALKER_CNTL(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_Q_WALKER_CNTL_MASK) >> TP0_DEBUG_Q_WALKER_CNTL_SHIFT) +#define TP0_DEBUG_GET_Q_ALIGNER_CNTL(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_Q_ALIGNER_CNTL_MASK) >> TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT) + +#define TP0_DEBUG_SET_Q_LOD_CNTL(tp0_debug_reg, q_lod_cntl) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_LOD_CNTL_MASK) | (q_lod_cntl << TP0_DEBUG_Q_LOD_CNTL_SHIFT) +#define TP0_DEBUG_SET_Q_SQ_TP_WAKEUP(tp0_debug_reg, q_sq_tp_wakeup) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK) | (q_sq_tp_wakeup << TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT) +#define TP0_DEBUG_SET_FL_TA_ADDRESSER_CNTL(tp0_debug_reg, fl_ta_addresser_cntl) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK) | (fl_ta_addresser_cntl << TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT) +#define TP0_DEBUG_SET_REG_CLK_EN(tp0_debug_reg, reg_clk_en) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_REG_CLK_EN_MASK) | (reg_clk_en << TP0_DEBUG_REG_CLK_EN_SHIFT) +#define TP0_DEBUG_SET_PERF_CLK_EN(tp0_debug_reg, perf_clk_en) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_PERF_CLK_EN_MASK) | (perf_clk_en << TP0_DEBUG_PERF_CLK_EN_SHIFT) +#define TP0_DEBUG_SET_TP_CLK_EN(tp0_debug_reg, tp_clk_en) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_TP_CLK_EN_MASK) | (tp_clk_en << TP0_DEBUG_TP_CLK_EN_SHIFT) +#define TP0_DEBUG_SET_Q_WALKER_CNTL(tp0_debug_reg, q_walker_cntl) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_WALKER_CNTL_MASK) | (q_walker_cntl << TP0_DEBUG_Q_WALKER_CNTL_SHIFT) +#define TP0_DEBUG_SET_Q_ALIGNER_CNTL(tp0_debug_reg, q_aligner_cntl) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_ALIGNER_CNTL_MASK) | (q_aligner_cntl << TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_debug_t { + unsigned int q_lod_cntl : TP0_DEBUG_Q_LOD_CNTL_SIZE; + unsigned int : 1; + unsigned int q_sq_tp_wakeup : TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE; + unsigned int fl_ta_addresser_cntl : TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE; + unsigned int reg_clk_en : TP0_DEBUG_REG_CLK_EN_SIZE; + unsigned int perf_clk_en : TP0_DEBUG_PERF_CLK_EN_SIZE; + unsigned int tp_clk_en : TP0_DEBUG_TP_CLK_EN_SIZE; + unsigned int q_walker_cntl : TP0_DEBUG_Q_WALKER_CNTL_SIZE; + unsigned int q_aligner_cntl : TP0_DEBUG_Q_ALIGNER_CNTL_SIZE; + unsigned int : 1; + } tp0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_debug_t { + unsigned int : 1; + unsigned int q_aligner_cntl : TP0_DEBUG_Q_ALIGNER_CNTL_SIZE; + unsigned int q_walker_cntl : TP0_DEBUG_Q_WALKER_CNTL_SIZE; + unsigned int tp_clk_en : TP0_DEBUG_TP_CLK_EN_SIZE; + unsigned int perf_clk_en : TP0_DEBUG_PERF_CLK_EN_SIZE; + unsigned int reg_clk_en : TP0_DEBUG_REG_CLK_EN_SIZE; + unsigned int fl_ta_addresser_cntl : TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE; + unsigned int q_sq_tp_wakeup : TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE; + unsigned int : 1; + unsigned int q_lod_cntl : TP0_DEBUG_Q_LOD_CNTL_SIZE; + } tp0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_debug_t f; +} tp0_debug_u; + + +/* + * TP0_CHICKEN struct + */ + +#define TP0_CHICKEN_TT_MODE_SIZE 1 +#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE 1 +#define TP0_CHICKEN_SPARE_SIZE 30 + +#define TP0_CHICKEN_TT_MODE_SHIFT 0 +#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT 1 +#define TP0_CHICKEN_SPARE_SHIFT 2 + +#define TP0_CHICKEN_TT_MODE_MASK 0x00000001 +#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK 0x00000002 +#define TP0_CHICKEN_SPARE_MASK 0xfffffffc + +#define TP0_CHICKEN_MASK \ + (TP0_CHICKEN_TT_MODE_MASK | \ + TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK | \ + TP0_CHICKEN_SPARE_MASK) + +#define TP0_CHICKEN(tt_mode, vfetch_address_mode, spare) \ + ((tt_mode << TP0_CHICKEN_TT_MODE_SHIFT) | \ + (vfetch_address_mode << TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT) | \ + (spare << TP0_CHICKEN_SPARE_SHIFT)) + +#define TP0_CHICKEN_GET_TT_MODE(tp0_chicken) \ + ((tp0_chicken & TP0_CHICKEN_TT_MODE_MASK) >> TP0_CHICKEN_TT_MODE_SHIFT) +#define TP0_CHICKEN_GET_VFETCH_ADDRESS_MODE(tp0_chicken) \ + ((tp0_chicken & TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK) >> TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT) +#define TP0_CHICKEN_GET_SPARE(tp0_chicken) \ + ((tp0_chicken & TP0_CHICKEN_SPARE_MASK) >> TP0_CHICKEN_SPARE_SHIFT) + +#define TP0_CHICKEN_SET_TT_MODE(tp0_chicken_reg, tt_mode) \ + tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_TT_MODE_MASK) | (tt_mode << TP0_CHICKEN_TT_MODE_SHIFT) +#define TP0_CHICKEN_SET_VFETCH_ADDRESS_MODE(tp0_chicken_reg, vfetch_address_mode) \ + tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK) | (vfetch_address_mode << TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT) +#define TP0_CHICKEN_SET_SPARE(tp0_chicken_reg, spare) \ + tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_SPARE_MASK) | (spare << TP0_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_chicken_t { + unsigned int tt_mode : TP0_CHICKEN_TT_MODE_SIZE; + unsigned int vfetch_address_mode : TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE; + unsigned int spare : TP0_CHICKEN_SPARE_SIZE; + } tp0_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_chicken_t { + unsigned int spare : TP0_CHICKEN_SPARE_SIZE; + unsigned int vfetch_address_mode : TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE; + unsigned int tt_mode : TP0_CHICKEN_TT_MODE_SIZE; + } tp0_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_chicken_t f; +} tp0_chicken_u; + + +/* + * TP0_PERFCOUNTER0_SELECT struct + */ + +#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TP0_PERFCOUNTER0_SELECT_MASK \ + (TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TP0_PERFCOUNTER0_SELECT(perfcounter_select) \ + ((perfcounter_select << TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TP0_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tp0_perfcounter0_select) \ + ((tp0_perfcounter0_select & TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TP0_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tp0_perfcounter0_select_reg, perfcounter_select) \ + tp0_perfcounter0_select_reg = (tp0_perfcounter0_select_reg & ~TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_select_t { + unsigned int perfcounter_select : TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tp0_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + } tp0_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter0_select_t f; +} tp0_perfcounter0_select_u; + + +/* + * TP0_PERFCOUNTER0_HI struct + */ + +#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16 + +#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TP0_PERFCOUNTER0_HI_MASK \ + (TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) + +#define TP0_PERFCOUNTER0_HI(perfcounter_hi) \ + ((perfcounter_hi << TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)) + +#define TP0_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tp0_perfcounter0_hi) \ + ((tp0_perfcounter0_hi & TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#define TP0_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tp0_perfcounter0_hi_reg, perfcounter_hi) \ + tp0_perfcounter0_hi_reg = (tp0_perfcounter0_hi_reg & ~TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_hi_t { + unsigned int perfcounter_hi : TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tp0_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + } tp0_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter0_hi_t f; +} tp0_perfcounter0_hi_u; + + +/* + * TP0_PERFCOUNTER0_LOW struct + */ + +#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TP0_PERFCOUNTER0_LOW_MASK \ + (TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) + +#define TP0_PERFCOUNTER0_LOW(perfcounter_low) \ + ((perfcounter_low << TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TP0_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tp0_perfcounter0_low) \ + ((tp0_perfcounter0_low & TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TP0_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tp0_perfcounter0_low_reg, perfcounter_low) \ + tp0_perfcounter0_low_reg = (tp0_perfcounter0_low_reg & ~TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_low_t { + unsigned int perfcounter_low : TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tp0_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_low_t { + unsigned int perfcounter_low : TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tp0_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter0_low_t f; +} tp0_perfcounter0_low_u; + + +/* + * TP0_PERFCOUNTER1_SELECT struct + */ + +#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TP0_PERFCOUNTER1_SELECT_MASK \ + (TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TP0_PERFCOUNTER1_SELECT(perfcounter_select) \ + ((perfcounter_select << TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TP0_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tp0_perfcounter1_select) \ + ((tp0_perfcounter1_select & TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TP0_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tp0_perfcounter1_select_reg, perfcounter_select) \ + tp0_perfcounter1_select_reg = (tp0_perfcounter1_select_reg & ~TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_select_t { + unsigned int perfcounter_select : TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tp0_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + } tp0_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter1_select_t f; +} tp0_perfcounter1_select_u; + + +/* + * TP0_PERFCOUNTER1_HI struct + */ + +#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16 + +#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TP0_PERFCOUNTER1_HI_MASK \ + (TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) + +#define TP0_PERFCOUNTER1_HI(perfcounter_hi) \ + ((perfcounter_hi << TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)) + +#define TP0_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tp0_perfcounter1_hi) \ + ((tp0_perfcounter1_hi & TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#define TP0_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tp0_perfcounter1_hi_reg, perfcounter_hi) \ + tp0_perfcounter1_hi_reg = (tp0_perfcounter1_hi_reg & ~TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_hi_t { + unsigned int perfcounter_hi : TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tp0_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + } tp0_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter1_hi_t f; +} tp0_perfcounter1_hi_u; + + +/* + * TP0_PERFCOUNTER1_LOW struct + */ + +#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TP0_PERFCOUNTER1_LOW_MASK \ + (TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) + +#define TP0_PERFCOUNTER1_LOW(perfcounter_low) \ + ((perfcounter_low << TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TP0_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tp0_perfcounter1_low) \ + ((tp0_perfcounter1_low & TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TP0_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tp0_perfcounter1_low_reg, perfcounter_low) \ + tp0_perfcounter1_low_reg = (tp0_perfcounter1_low_reg & ~TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_low_t { + unsigned int perfcounter_low : TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tp0_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_low_t { + unsigned int perfcounter_low : TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tp0_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter1_low_t f; +} tp0_perfcounter1_low_u; + + +/* + * TCM_PERFCOUNTER0_SELECT struct + */ + +#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCM_PERFCOUNTER0_SELECT_MASK \ + (TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCM_PERFCOUNTER0_SELECT(perfcounter_select) \ + ((perfcounter_select << TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCM_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcm_perfcounter0_select) \ + ((tcm_perfcounter0_select & TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCM_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcm_perfcounter0_select_reg, perfcounter_select) \ + tcm_perfcounter0_select_reg = (tcm_perfcounter0_select_reg & ~TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_select_t { + unsigned int perfcounter_select : TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcm_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcm_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter0_select_t f; +} tcm_perfcounter0_select_u; + + +/* + * TCM_PERFCOUNTER1_SELECT struct + */ + +#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCM_PERFCOUNTER1_SELECT_MASK \ + (TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCM_PERFCOUNTER1_SELECT(perfcounter_select) \ + ((perfcounter_select << TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCM_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcm_perfcounter1_select) \ + ((tcm_perfcounter1_select & TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCM_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcm_perfcounter1_select_reg, perfcounter_select) \ + tcm_perfcounter1_select_reg = (tcm_perfcounter1_select_reg & ~TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_select_t { + unsigned int perfcounter_select : TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcm_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcm_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter1_select_t f; +} tcm_perfcounter1_select_u; + + +/* + * TCM_PERFCOUNTER0_HI struct + */ + +#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCM_PERFCOUNTER0_HI_MASK \ + (TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) + +#define TCM_PERFCOUNTER0_HI(perfcounter_hi) \ + ((perfcounter_hi << TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCM_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcm_perfcounter0_hi) \ + ((tcm_perfcounter0_hi & TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#define TCM_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcm_perfcounter0_hi_reg, perfcounter_hi) \ + tcm_perfcounter0_hi_reg = (tcm_perfcounter0_hi_reg & ~TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_hi_t { + unsigned int perfcounter_hi : TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcm_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + } tcm_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter0_hi_t f; +} tcm_perfcounter0_hi_u; + + +/* + * TCM_PERFCOUNTER1_HI struct + */ + +#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCM_PERFCOUNTER1_HI_MASK \ + (TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) + +#define TCM_PERFCOUNTER1_HI(perfcounter_hi) \ + ((perfcounter_hi << TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCM_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcm_perfcounter1_hi) \ + ((tcm_perfcounter1_hi & TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#define TCM_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcm_perfcounter1_hi_reg, perfcounter_hi) \ + tcm_perfcounter1_hi_reg = (tcm_perfcounter1_hi_reg & ~TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_hi_t { + unsigned int perfcounter_hi : TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcm_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + } tcm_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter1_hi_t f; +} tcm_perfcounter1_hi_u; + + +/* + * TCM_PERFCOUNTER0_LOW struct + */ + +#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCM_PERFCOUNTER0_LOW_MASK \ + (TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) + +#define TCM_PERFCOUNTER0_LOW(perfcounter_low) \ + ((perfcounter_low << TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCM_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcm_perfcounter0_low) \ + ((tcm_perfcounter0_low & TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCM_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcm_perfcounter0_low_reg, perfcounter_low) \ + tcm_perfcounter0_low_reg = (tcm_perfcounter0_low_reg & ~TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_low_t { + unsigned int perfcounter_low : TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcm_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_low_t { + unsigned int perfcounter_low : TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcm_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter0_low_t f; +} tcm_perfcounter0_low_u; + + +/* + * TCM_PERFCOUNTER1_LOW struct + */ + +#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCM_PERFCOUNTER1_LOW_MASK \ + (TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) + +#define TCM_PERFCOUNTER1_LOW(perfcounter_low) \ + ((perfcounter_low << TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCM_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcm_perfcounter1_low) \ + ((tcm_perfcounter1_low & TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCM_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcm_perfcounter1_low_reg, perfcounter_low) \ + tcm_perfcounter1_low_reg = (tcm_perfcounter1_low_reg & ~TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_low_t { + unsigned int perfcounter_low : TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcm_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_low_t { + unsigned int perfcounter_low : TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcm_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter1_low_t f; +} tcm_perfcounter1_low_u; + + +/* + * TCF_PERFCOUNTER0_SELECT struct + */ + +#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER0_SELECT_MASK \ + (TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER0_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter0_select) \ + ((tcf_perfcounter0_select & TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter0_select_reg, perfcounter_select) \ + tcf_perfcounter0_select_reg = (tcf_perfcounter0_select_reg & ~TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter0_select_t f; +} tcf_perfcounter0_select_u; + + +/* + * TCF_PERFCOUNTER1_SELECT struct + */ + +#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER1_SELECT_MASK \ + (TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER1_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter1_select) \ + ((tcf_perfcounter1_select & TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter1_select_reg, perfcounter_select) \ + tcf_perfcounter1_select_reg = (tcf_perfcounter1_select_reg & ~TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter1_select_t f; +} tcf_perfcounter1_select_u; + + +/* + * TCF_PERFCOUNTER2_SELECT struct + */ + +#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER2_SELECT_MASK \ + (TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER2_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER2_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter2_select) \ + ((tcf_perfcounter2_select & TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER2_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter2_select_reg, perfcounter_select) \ + tcf_perfcounter2_select_reg = (tcf_perfcounter2_select_reg & ~TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter2_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter2_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter2_select_t f; +} tcf_perfcounter2_select_u; + + +/* + * TCF_PERFCOUNTER3_SELECT struct + */ + +#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER3_SELECT_MASK \ + (TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER3_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER3_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter3_select) \ + ((tcf_perfcounter3_select & TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER3_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter3_select_reg, perfcounter_select) \ + tcf_perfcounter3_select_reg = (tcf_perfcounter3_select_reg & ~TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter3_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter3_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter3_select_t f; +} tcf_perfcounter3_select_u; + + +/* + * TCF_PERFCOUNTER4_SELECT struct + */ + +#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER4_SELECT_MASK \ + (TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER4_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER4_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter4_select) \ + ((tcf_perfcounter4_select & TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER4_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter4_select_reg, perfcounter_select) \ + tcf_perfcounter4_select_reg = (tcf_perfcounter4_select_reg & ~TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter4_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter4_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter4_select_t f; +} tcf_perfcounter4_select_u; + + +/* + * TCF_PERFCOUNTER5_SELECT struct + */ + +#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER5_SELECT_MASK \ + (TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER5_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER5_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter5_select) \ + ((tcf_perfcounter5_select & TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER5_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter5_select_reg, perfcounter_select) \ + tcf_perfcounter5_select_reg = (tcf_perfcounter5_select_reg & ~TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter5_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter5_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter5_select_t f; +} tcf_perfcounter5_select_u; + + +/* + * TCF_PERFCOUNTER6_SELECT struct + */ + +#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER6_SELECT_MASK \ + (TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER6_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER6_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter6_select) \ + ((tcf_perfcounter6_select & TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER6_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter6_select_reg, perfcounter_select) \ + tcf_perfcounter6_select_reg = (tcf_perfcounter6_select_reg & ~TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter6_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter6_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter6_select_t f; +} tcf_perfcounter6_select_u; + + +/* + * TCF_PERFCOUNTER7_SELECT struct + */ + +#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER7_SELECT_MASK \ + (TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER7_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER7_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter7_select) \ + ((tcf_perfcounter7_select & TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER7_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter7_select_reg, perfcounter_select) \ + tcf_perfcounter7_select_reg = (tcf_perfcounter7_select_reg & ~TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter7_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter7_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter7_select_t f; +} tcf_perfcounter7_select_u; + + +/* + * TCF_PERFCOUNTER8_SELECT struct + */ + +#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER8_SELECT_MASK \ + (TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER8_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER8_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter8_select) \ + ((tcf_perfcounter8_select & TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER8_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter8_select_reg, perfcounter_select) \ + tcf_perfcounter8_select_reg = (tcf_perfcounter8_select_reg & ~TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter8_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter8_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter8_select_t f; +} tcf_perfcounter8_select_u; + + +/* + * TCF_PERFCOUNTER9_SELECT struct + */ + +#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER9_SELECT_MASK \ + (TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER9_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER9_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter9_select) \ + ((tcf_perfcounter9_select & TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER9_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter9_select_reg, perfcounter_select) \ + tcf_perfcounter9_select_reg = (tcf_perfcounter9_select_reg & ~TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter9_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter9_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter9_select_t f; +} tcf_perfcounter9_select_u; + + +/* + * TCF_PERFCOUNTER10_SELECT struct + */ + +#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER10_SELECT_MASK \ + (TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER10_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER10_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter10_select) \ + ((tcf_perfcounter10_select & TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER10_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter10_select_reg, perfcounter_select) \ + tcf_perfcounter10_select_reg = (tcf_perfcounter10_select_reg & ~TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter10_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter10_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter10_select_t f; +} tcf_perfcounter10_select_u; + + +/* + * TCF_PERFCOUNTER11_SELECT struct + */ + +#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER11_SELECT_MASK \ + (TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER11_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER11_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter11_select) \ + ((tcf_perfcounter11_select & TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER11_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter11_select_reg, perfcounter_select) \ + tcf_perfcounter11_select_reg = (tcf_perfcounter11_select_reg & ~TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter11_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter11_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter11_select_t f; +} tcf_perfcounter11_select_u; + + +/* + * TCF_PERFCOUNTER0_HI struct + */ + +#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER0_HI_MASK \ + (TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER0_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcf_perfcounter0_hi) \ + ((tcf_perfcounter0_hi & TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcf_perfcounter0_hi_reg, perfcounter_hi) \ + tcf_perfcounter0_hi_reg = (tcf_perfcounter0_hi_reg & ~TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter0_hi_t f; +} tcf_perfcounter0_hi_u; + + +/* + * TCF_PERFCOUNTER1_HI struct + */ + +#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER1_HI_MASK \ + (TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER1_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcf_perfcounter1_hi) \ + ((tcf_perfcounter1_hi & TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcf_perfcounter1_hi_reg, perfcounter_hi) \ + tcf_perfcounter1_hi_reg = (tcf_perfcounter1_hi_reg & ~TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter1_hi_t f; +} tcf_perfcounter1_hi_u; + + +/* + * TCF_PERFCOUNTER2_HI struct + */ + +#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER2_HI_MASK \ + (TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER2_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER2_HI_GET_PERFCOUNTER_HI(tcf_perfcounter2_hi) \ + ((tcf_perfcounter2_hi & TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER2_HI_SET_PERFCOUNTER_HI(tcf_perfcounter2_hi_reg, perfcounter_hi) \ + tcf_perfcounter2_hi_reg = (tcf_perfcounter2_hi_reg & ~TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter2_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter2_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter2_hi_t f; +} tcf_perfcounter2_hi_u; + + +/* + * TCF_PERFCOUNTER3_HI struct + */ + +#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER3_HI_MASK \ + (TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER3_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER3_HI_GET_PERFCOUNTER_HI(tcf_perfcounter3_hi) \ + ((tcf_perfcounter3_hi & TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER3_HI_SET_PERFCOUNTER_HI(tcf_perfcounter3_hi_reg, perfcounter_hi) \ + tcf_perfcounter3_hi_reg = (tcf_perfcounter3_hi_reg & ~TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter3_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter3_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter3_hi_t f; +} tcf_perfcounter3_hi_u; + + +/* + * TCF_PERFCOUNTER4_HI struct + */ + +#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER4_HI_MASK \ + (TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER4_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER4_HI_GET_PERFCOUNTER_HI(tcf_perfcounter4_hi) \ + ((tcf_perfcounter4_hi & TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER4_HI_SET_PERFCOUNTER_HI(tcf_perfcounter4_hi_reg, perfcounter_hi) \ + tcf_perfcounter4_hi_reg = (tcf_perfcounter4_hi_reg & ~TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter4_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter4_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter4_hi_t f; +} tcf_perfcounter4_hi_u; + + +/* + * TCF_PERFCOUNTER5_HI struct + */ + +#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER5_HI_MASK \ + (TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER5_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER5_HI_GET_PERFCOUNTER_HI(tcf_perfcounter5_hi) \ + ((tcf_perfcounter5_hi & TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER5_HI_SET_PERFCOUNTER_HI(tcf_perfcounter5_hi_reg, perfcounter_hi) \ + tcf_perfcounter5_hi_reg = (tcf_perfcounter5_hi_reg & ~TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter5_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter5_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter5_hi_t f; +} tcf_perfcounter5_hi_u; + + +/* + * TCF_PERFCOUNTER6_HI struct + */ + +#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER6_HI_MASK \ + (TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER6_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER6_HI_GET_PERFCOUNTER_HI(tcf_perfcounter6_hi) \ + ((tcf_perfcounter6_hi & TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER6_HI_SET_PERFCOUNTER_HI(tcf_perfcounter6_hi_reg, perfcounter_hi) \ + tcf_perfcounter6_hi_reg = (tcf_perfcounter6_hi_reg & ~TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter6_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter6_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter6_hi_t f; +} tcf_perfcounter6_hi_u; + + +/* + * TCF_PERFCOUNTER7_HI struct + */ + +#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER7_HI_MASK \ + (TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER7_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER7_HI_GET_PERFCOUNTER_HI(tcf_perfcounter7_hi) \ + ((tcf_perfcounter7_hi & TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER7_HI_SET_PERFCOUNTER_HI(tcf_perfcounter7_hi_reg, perfcounter_hi) \ + tcf_perfcounter7_hi_reg = (tcf_perfcounter7_hi_reg & ~TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter7_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter7_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter7_hi_t f; +} tcf_perfcounter7_hi_u; + + +/* + * TCF_PERFCOUNTER8_HI struct + */ + +#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER8_HI_MASK \ + (TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER8_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER8_HI_GET_PERFCOUNTER_HI(tcf_perfcounter8_hi) \ + ((tcf_perfcounter8_hi & TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER8_HI_SET_PERFCOUNTER_HI(tcf_perfcounter8_hi_reg, perfcounter_hi) \ + tcf_perfcounter8_hi_reg = (tcf_perfcounter8_hi_reg & ~TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter8_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter8_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter8_hi_t f; +} tcf_perfcounter8_hi_u; + + +/* + * TCF_PERFCOUNTER9_HI struct + */ + +#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER9_HI_MASK \ + (TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER9_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER9_HI_GET_PERFCOUNTER_HI(tcf_perfcounter9_hi) \ + ((tcf_perfcounter9_hi & TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER9_HI_SET_PERFCOUNTER_HI(tcf_perfcounter9_hi_reg, perfcounter_hi) \ + tcf_perfcounter9_hi_reg = (tcf_perfcounter9_hi_reg & ~TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter9_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter9_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter9_hi_t f; +} tcf_perfcounter9_hi_u; + + +/* + * TCF_PERFCOUNTER10_HI struct + */ + +#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER10_HI_MASK \ + (TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER10_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER10_HI_GET_PERFCOUNTER_HI(tcf_perfcounter10_hi) \ + ((tcf_perfcounter10_hi & TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER10_HI_SET_PERFCOUNTER_HI(tcf_perfcounter10_hi_reg, perfcounter_hi) \ + tcf_perfcounter10_hi_reg = (tcf_perfcounter10_hi_reg & ~TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter10_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter10_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter10_hi_t f; +} tcf_perfcounter10_hi_u; + + +/* + * TCF_PERFCOUNTER11_HI struct + */ + +#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER11_HI_MASK \ + (TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER11_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER11_HI_GET_PERFCOUNTER_HI(tcf_perfcounter11_hi) \ + ((tcf_perfcounter11_hi & TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER11_HI_SET_PERFCOUNTER_HI(tcf_perfcounter11_hi_reg, perfcounter_hi) \ + tcf_perfcounter11_hi_reg = (tcf_perfcounter11_hi_reg & ~TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter11_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter11_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter11_hi_t f; +} tcf_perfcounter11_hi_u; + + +/* + * TCF_PERFCOUNTER0_LOW struct + */ + +#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER0_LOW_MASK \ + (TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER0_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter0_low) \ + ((tcf_perfcounter0_low & TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter0_low_reg, perfcounter_low) \ + tcf_perfcounter0_low_reg = (tcf_perfcounter0_low_reg & ~TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter0_low_t f; +} tcf_perfcounter0_low_u; + + +/* + * TCF_PERFCOUNTER1_LOW struct + */ + +#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER1_LOW_MASK \ + (TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER1_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter1_low) \ + ((tcf_perfcounter1_low & TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter1_low_reg, perfcounter_low) \ + tcf_perfcounter1_low_reg = (tcf_perfcounter1_low_reg & ~TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter1_low_t f; +} tcf_perfcounter1_low_u; + + +/* + * TCF_PERFCOUNTER2_LOW struct + */ + +#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER2_LOW_MASK \ + (TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER2_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER2_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter2_low) \ + ((tcf_perfcounter2_low & TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER2_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter2_low_reg, perfcounter_low) \ + tcf_perfcounter2_low_reg = (tcf_perfcounter2_low_reg & ~TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter2_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter2_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter2_low_t f; +} tcf_perfcounter2_low_u; + + +/* + * TCF_PERFCOUNTER3_LOW struct + */ + +#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER3_LOW_MASK \ + (TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER3_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER3_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter3_low) \ + ((tcf_perfcounter3_low & TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER3_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter3_low_reg, perfcounter_low) \ + tcf_perfcounter3_low_reg = (tcf_perfcounter3_low_reg & ~TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter3_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter3_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter3_low_t f; +} tcf_perfcounter3_low_u; + + +/* + * TCF_PERFCOUNTER4_LOW struct + */ + +#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER4_LOW_MASK \ + (TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER4_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER4_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter4_low) \ + ((tcf_perfcounter4_low & TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER4_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter4_low_reg, perfcounter_low) \ + tcf_perfcounter4_low_reg = (tcf_perfcounter4_low_reg & ~TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter4_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter4_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter4_low_t f; +} tcf_perfcounter4_low_u; + + +/* + * TCF_PERFCOUNTER5_LOW struct + */ + +#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER5_LOW_MASK \ + (TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER5_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER5_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter5_low) \ + ((tcf_perfcounter5_low & TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER5_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter5_low_reg, perfcounter_low) \ + tcf_perfcounter5_low_reg = (tcf_perfcounter5_low_reg & ~TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter5_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter5_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter5_low_t f; +} tcf_perfcounter5_low_u; + + +/* + * TCF_PERFCOUNTER6_LOW struct + */ + +#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER6_LOW_MASK \ + (TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER6_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER6_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter6_low) \ + ((tcf_perfcounter6_low & TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER6_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter6_low_reg, perfcounter_low) \ + tcf_perfcounter6_low_reg = (tcf_perfcounter6_low_reg & ~TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter6_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter6_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter6_low_t f; +} tcf_perfcounter6_low_u; + + +/* + * TCF_PERFCOUNTER7_LOW struct + */ + +#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER7_LOW_MASK \ + (TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER7_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER7_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter7_low) \ + ((tcf_perfcounter7_low & TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER7_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter7_low_reg, perfcounter_low) \ + tcf_perfcounter7_low_reg = (tcf_perfcounter7_low_reg & ~TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter7_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter7_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter7_low_t f; +} tcf_perfcounter7_low_u; + + +/* + * TCF_PERFCOUNTER8_LOW struct + */ + +#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER8_LOW_MASK \ + (TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER8_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER8_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter8_low) \ + ((tcf_perfcounter8_low & TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER8_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter8_low_reg, perfcounter_low) \ + tcf_perfcounter8_low_reg = (tcf_perfcounter8_low_reg & ~TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter8_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter8_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter8_low_t f; +} tcf_perfcounter8_low_u; + + +/* + * TCF_PERFCOUNTER9_LOW struct + */ + +#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER9_LOW_MASK \ + (TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER9_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER9_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter9_low) \ + ((tcf_perfcounter9_low & TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER9_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter9_low_reg, perfcounter_low) \ + tcf_perfcounter9_low_reg = (tcf_perfcounter9_low_reg & ~TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter9_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter9_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter9_low_t f; +} tcf_perfcounter9_low_u; + + +/* + * TCF_PERFCOUNTER10_LOW struct + */ + +#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER10_LOW_MASK \ + (TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER10_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER10_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter10_low) \ + ((tcf_perfcounter10_low & TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER10_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter10_low_reg, perfcounter_low) \ + tcf_perfcounter10_low_reg = (tcf_perfcounter10_low_reg & ~TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter10_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter10_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter10_low_t f; +} tcf_perfcounter10_low_u; + + +/* + * TCF_PERFCOUNTER11_LOW struct + */ + +#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER11_LOW_MASK \ + (TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER11_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER11_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter11_low) \ + ((tcf_perfcounter11_low & TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER11_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter11_low_reg, perfcounter_low) \ + tcf_perfcounter11_low_reg = (tcf_perfcounter11_low_reg & ~TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter11_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter11_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter11_low_t f; +} tcf_perfcounter11_low_u; + + +/* + * TCF_DEBUG struct + */ + +#define TCF_DEBUG_not_MH_TC_rtr_SIZE 1 +#define TCF_DEBUG_TC_MH_send_SIZE 1 +#define TCF_DEBUG_not_FG0_rtr_SIZE 1 +#define TCF_DEBUG_not_TCB_TCO_rtr_SIZE 1 +#define TCF_DEBUG_TCB_ff_stall_SIZE 1 +#define TCF_DEBUG_TCB_miss_stall_SIZE 1 +#define TCF_DEBUG_TCA_TCB_stall_SIZE 1 +#define TCF_DEBUG_PF0_stall_SIZE 1 +#define TCF_DEBUG_TP0_full_SIZE 1 +#define TCF_DEBUG_TPC_full_SIZE 1 +#define TCF_DEBUG_not_TPC_rtr_SIZE 1 +#define TCF_DEBUG_tca_state_rts_SIZE 1 +#define TCF_DEBUG_tca_rts_SIZE 1 + +#define TCF_DEBUG_not_MH_TC_rtr_SHIFT 6 +#define TCF_DEBUG_TC_MH_send_SHIFT 7 +#define TCF_DEBUG_not_FG0_rtr_SHIFT 8 +#define TCF_DEBUG_not_TCB_TCO_rtr_SHIFT 12 +#define TCF_DEBUG_TCB_ff_stall_SHIFT 13 +#define TCF_DEBUG_TCB_miss_stall_SHIFT 14 +#define TCF_DEBUG_TCA_TCB_stall_SHIFT 15 +#define TCF_DEBUG_PF0_stall_SHIFT 16 +#define TCF_DEBUG_TP0_full_SHIFT 20 +#define TCF_DEBUG_TPC_full_SHIFT 24 +#define TCF_DEBUG_not_TPC_rtr_SHIFT 25 +#define TCF_DEBUG_tca_state_rts_SHIFT 26 +#define TCF_DEBUG_tca_rts_SHIFT 27 + +#define TCF_DEBUG_not_MH_TC_rtr_MASK 0x00000040 +#define TCF_DEBUG_TC_MH_send_MASK 0x00000080 +#define TCF_DEBUG_not_FG0_rtr_MASK 0x00000100 +#define TCF_DEBUG_not_TCB_TCO_rtr_MASK 0x00001000 +#define TCF_DEBUG_TCB_ff_stall_MASK 0x00002000 +#define TCF_DEBUG_TCB_miss_stall_MASK 0x00004000 +#define TCF_DEBUG_TCA_TCB_stall_MASK 0x00008000 +#define TCF_DEBUG_PF0_stall_MASK 0x00010000 +#define TCF_DEBUG_TP0_full_MASK 0x00100000 +#define TCF_DEBUG_TPC_full_MASK 0x01000000 +#define TCF_DEBUG_not_TPC_rtr_MASK 0x02000000 +#define TCF_DEBUG_tca_state_rts_MASK 0x04000000 +#define TCF_DEBUG_tca_rts_MASK 0x08000000 + +#define TCF_DEBUG_MASK \ + (TCF_DEBUG_not_MH_TC_rtr_MASK | \ + TCF_DEBUG_TC_MH_send_MASK | \ + TCF_DEBUG_not_FG0_rtr_MASK | \ + TCF_DEBUG_not_TCB_TCO_rtr_MASK | \ + TCF_DEBUG_TCB_ff_stall_MASK | \ + TCF_DEBUG_TCB_miss_stall_MASK | \ + TCF_DEBUG_TCA_TCB_stall_MASK | \ + TCF_DEBUG_PF0_stall_MASK | \ + TCF_DEBUG_TP0_full_MASK | \ + TCF_DEBUG_TPC_full_MASK | \ + TCF_DEBUG_not_TPC_rtr_MASK | \ + TCF_DEBUG_tca_state_rts_MASK | \ + TCF_DEBUG_tca_rts_MASK) + +#define TCF_DEBUG(not_mh_tc_rtr, tc_mh_send, not_fg0_rtr, not_tcb_tco_rtr, tcb_ff_stall, tcb_miss_stall, tca_tcb_stall, pf0_stall, tp0_full, tpc_full, not_tpc_rtr, tca_state_rts, tca_rts) \ + ((not_mh_tc_rtr << TCF_DEBUG_not_MH_TC_rtr_SHIFT) | \ + (tc_mh_send << TCF_DEBUG_TC_MH_send_SHIFT) | \ + (not_fg0_rtr << TCF_DEBUG_not_FG0_rtr_SHIFT) | \ + (not_tcb_tco_rtr << TCF_DEBUG_not_TCB_TCO_rtr_SHIFT) | \ + (tcb_ff_stall << TCF_DEBUG_TCB_ff_stall_SHIFT) | \ + (tcb_miss_stall << TCF_DEBUG_TCB_miss_stall_SHIFT) | \ + (tca_tcb_stall << TCF_DEBUG_TCA_TCB_stall_SHIFT) | \ + (pf0_stall << TCF_DEBUG_PF0_stall_SHIFT) | \ + (tp0_full << TCF_DEBUG_TP0_full_SHIFT) | \ + (tpc_full << TCF_DEBUG_TPC_full_SHIFT) | \ + (not_tpc_rtr << TCF_DEBUG_not_TPC_rtr_SHIFT) | \ + (tca_state_rts << TCF_DEBUG_tca_state_rts_SHIFT) | \ + (tca_rts << TCF_DEBUG_tca_rts_SHIFT)) + +#define TCF_DEBUG_GET_not_MH_TC_rtr(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_not_MH_TC_rtr_MASK) >> TCF_DEBUG_not_MH_TC_rtr_SHIFT) +#define TCF_DEBUG_GET_TC_MH_send(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TC_MH_send_MASK) >> TCF_DEBUG_TC_MH_send_SHIFT) +#define TCF_DEBUG_GET_not_FG0_rtr(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_not_FG0_rtr_MASK) >> TCF_DEBUG_not_FG0_rtr_SHIFT) +#define TCF_DEBUG_GET_not_TCB_TCO_rtr(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_not_TCB_TCO_rtr_MASK) >> TCF_DEBUG_not_TCB_TCO_rtr_SHIFT) +#define TCF_DEBUG_GET_TCB_ff_stall(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TCB_ff_stall_MASK) >> TCF_DEBUG_TCB_ff_stall_SHIFT) +#define TCF_DEBUG_GET_TCB_miss_stall(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TCB_miss_stall_MASK) >> TCF_DEBUG_TCB_miss_stall_SHIFT) +#define TCF_DEBUG_GET_TCA_TCB_stall(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TCA_TCB_stall_MASK) >> TCF_DEBUG_TCA_TCB_stall_SHIFT) +#define TCF_DEBUG_GET_PF0_stall(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_PF0_stall_MASK) >> TCF_DEBUG_PF0_stall_SHIFT) +#define TCF_DEBUG_GET_TP0_full(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TP0_full_MASK) >> TCF_DEBUG_TP0_full_SHIFT) +#define TCF_DEBUG_GET_TPC_full(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TPC_full_MASK) >> TCF_DEBUG_TPC_full_SHIFT) +#define TCF_DEBUG_GET_not_TPC_rtr(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_not_TPC_rtr_MASK) >> TCF_DEBUG_not_TPC_rtr_SHIFT) +#define TCF_DEBUG_GET_tca_state_rts(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_tca_state_rts_MASK) >> TCF_DEBUG_tca_state_rts_SHIFT) +#define TCF_DEBUG_GET_tca_rts(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_tca_rts_MASK) >> TCF_DEBUG_tca_rts_SHIFT) + +#define TCF_DEBUG_SET_not_MH_TC_rtr(tcf_debug_reg, not_mh_tc_rtr) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_MH_TC_rtr_MASK) | (not_mh_tc_rtr << TCF_DEBUG_not_MH_TC_rtr_SHIFT) +#define TCF_DEBUG_SET_TC_MH_send(tcf_debug_reg, tc_mh_send) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TC_MH_send_MASK) | (tc_mh_send << TCF_DEBUG_TC_MH_send_SHIFT) +#define TCF_DEBUG_SET_not_FG0_rtr(tcf_debug_reg, not_fg0_rtr) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_FG0_rtr_MASK) | (not_fg0_rtr << TCF_DEBUG_not_FG0_rtr_SHIFT) +#define TCF_DEBUG_SET_not_TCB_TCO_rtr(tcf_debug_reg, not_tcb_tco_rtr) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_TCB_TCO_rtr_MASK) | (not_tcb_tco_rtr << TCF_DEBUG_not_TCB_TCO_rtr_SHIFT) +#define TCF_DEBUG_SET_TCB_ff_stall(tcf_debug_reg, tcb_ff_stall) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCB_ff_stall_MASK) | (tcb_ff_stall << TCF_DEBUG_TCB_ff_stall_SHIFT) +#define TCF_DEBUG_SET_TCB_miss_stall(tcf_debug_reg, tcb_miss_stall) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCB_miss_stall_MASK) | (tcb_miss_stall << TCF_DEBUG_TCB_miss_stall_SHIFT) +#define TCF_DEBUG_SET_TCA_TCB_stall(tcf_debug_reg, tca_tcb_stall) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCA_TCB_stall_MASK) | (tca_tcb_stall << TCF_DEBUG_TCA_TCB_stall_SHIFT) +#define TCF_DEBUG_SET_PF0_stall(tcf_debug_reg, pf0_stall) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_PF0_stall_MASK) | (pf0_stall << TCF_DEBUG_PF0_stall_SHIFT) +#define TCF_DEBUG_SET_TP0_full(tcf_debug_reg, tp0_full) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TP0_full_MASK) | (tp0_full << TCF_DEBUG_TP0_full_SHIFT) +#define TCF_DEBUG_SET_TPC_full(tcf_debug_reg, tpc_full) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TPC_full_MASK) | (tpc_full << TCF_DEBUG_TPC_full_SHIFT) +#define TCF_DEBUG_SET_not_TPC_rtr(tcf_debug_reg, not_tpc_rtr) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_TPC_rtr_MASK) | (not_tpc_rtr << TCF_DEBUG_not_TPC_rtr_SHIFT) +#define TCF_DEBUG_SET_tca_state_rts(tcf_debug_reg, tca_state_rts) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_tca_state_rts_MASK) | (tca_state_rts << TCF_DEBUG_tca_state_rts_SHIFT) +#define TCF_DEBUG_SET_tca_rts(tcf_debug_reg, tca_rts) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_tca_rts_MASK) | (tca_rts << TCF_DEBUG_tca_rts_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_debug_t { + unsigned int : 6; + unsigned int not_mh_tc_rtr : TCF_DEBUG_not_MH_TC_rtr_SIZE; + unsigned int tc_mh_send : TCF_DEBUG_TC_MH_send_SIZE; + unsigned int not_fg0_rtr : TCF_DEBUG_not_FG0_rtr_SIZE; + unsigned int : 3; + unsigned int not_tcb_tco_rtr : TCF_DEBUG_not_TCB_TCO_rtr_SIZE; + unsigned int tcb_ff_stall : TCF_DEBUG_TCB_ff_stall_SIZE; + unsigned int tcb_miss_stall : TCF_DEBUG_TCB_miss_stall_SIZE; + unsigned int tca_tcb_stall : TCF_DEBUG_TCA_TCB_stall_SIZE; + unsigned int pf0_stall : TCF_DEBUG_PF0_stall_SIZE; + unsigned int : 3; + unsigned int tp0_full : TCF_DEBUG_TP0_full_SIZE; + unsigned int : 3; + unsigned int tpc_full : TCF_DEBUG_TPC_full_SIZE; + unsigned int not_tpc_rtr : TCF_DEBUG_not_TPC_rtr_SIZE; + unsigned int tca_state_rts : TCF_DEBUG_tca_state_rts_SIZE; + unsigned int tca_rts : TCF_DEBUG_tca_rts_SIZE; + unsigned int : 4; + } tcf_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_debug_t { + unsigned int : 4; + unsigned int tca_rts : TCF_DEBUG_tca_rts_SIZE; + unsigned int tca_state_rts : TCF_DEBUG_tca_state_rts_SIZE; + unsigned int not_tpc_rtr : TCF_DEBUG_not_TPC_rtr_SIZE; + unsigned int tpc_full : TCF_DEBUG_TPC_full_SIZE; + unsigned int : 3; + unsigned int tp0_full : TCF_DEBUG_TP0_full_SIZE; + unsigned int : 3; + unsigned int pf0_stall : TCF_DEBUG_PF0_stall_SIZE; + unsigned int tca_tcb_stall : TCF_DEBUG_TCA_TCB_stall_SIZE; + unsigned int tcb_miss_stall : TCF_DEBUG_TCB_miss_stall_SIZE; + unsigned int tcb_ff_stall : TCF_DEBUG_TCB_ff_stall_SIZE; + unsigned int not_tcb_tco_rtr : TCF_DEBUG_not_TCB_TCO_rtr_SIZE; + unsigned int : 3; + unsigned int not_fg0_rtr : TCF_DEBUG_not_FG0_rtr_SIZE; + unsigned int tc_mh_send : TCF_DEBUG_TC_MH_send_SIZE; + unsigned int not_mh_tc_rtr : TCF_DEBUG_not_MH_TC_rtr_SIZE; + unsigned int : 6; + } tcf_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_debug_t f; +} tcf_debug_u; + + +/* + * TCA_FIFO_DEBUG struct + */ + +#define TCA_FIFO_DEBUG_tp0_full_SIZE 1 +#define TCA_FIFO_DEBUG_tpc_full_SIZE 1 +#define TCA_FIFO_DEBUG_load_tpc_fifo_SIZE 1 +#define TCA_FIFO_DEBUG_load_tp_fifos_SIZE 1 +#define TCA_FIFO_DEBUG_FW_full_SIZE 1 +#define TCA_FIFO_DEBUG_not_FW_rtr0_SIZE 1 +#define TCA_FIFO_DEBUG_FW_rts0_SIZE 1 +#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE 1 +#define TCA_FIFO_DEBUG_FW_tpc_rts_SIZE 1 + +#define TCA_FIFO_DEBUG_tp0_full_SHIFT 0 +#define TCA_FIFO_DEBUG_tpc_full_SHIFT 4 +#define TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT 5 +#define TCA_FIFO_DEBUG_load_tp_fifos_SHIFT 6 +#define TCA_FIFO_DEBUG_FW_full_SHIFT 7 +#define TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT 8 +#define TCA_FIFO_DEBUG_FW_rts0_SHIFT 12 +#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT 16 +#define TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT 17 + +#define TCA_FIFO_DEBUG_tp0_full_MASK 0x00000001 +#define TCA_FIFO_DEBUG_tpc_full_MASK 0x00000010 +#define TCA_FIFO_DEBUG_load_tpc_fifo_MASK 0x00000020 +#define TCA_FIFO_DEBUG_load_tp_fifos_MASK 0x00000040 +#define TCA_FIFO_DEBUG_FW_full_MASK 0x00000080 +#define TCA_FIFO_DEBUG_not_FW_rtr0_MASK 0x00000100 +#define TCA_FIFO_DEBUG_FW_rts0_MASK 0x00001000 +#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK 0x00010000 +#define TCA_FIFO_DEBUG_FW_tpc_rts_MASK 0x00020000 + +#define TCA_FIFO_DEBUG_MASK \ + (TCA_FIFO_DEBUG_tp0_full_MASK | \ + TCA_FIFO_DEBUG_tpc_full_MASK | \ + TCA_FIFO_DEBUG_load_tpc_fifo_MASK | \ + TCA_FIFO_DEBUG_load_tp_fifos_MASK | \ + TCA_FIFO_DEBUG_FW_full_MASK | \ + TCA_FIFO_DEBUG_not_FW_rtr0_MASK | \ + TCA_FIFO_DEBUG_FW_rts0_MASK | \ + TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK | \ + TCA_FIFO_DEBUG_FW_tpc_rts_MASK) + +#define TCA_FIFO_DEBUG(tp0_full, tpc_full, load_tpc_fifo, load_tp_fifos, fw_full, not_fw_rtr0, fw_rts0, not_fw_tpc_rtr, fw_tpc_rts) \ + ((tp0_full << TCA_FIFO_DEBUG_tp0_full_SHIFT) | \ + (tpc_full << TCA_FIFO_DEBUG_tpc_full_SHIFT) | \ + (load_tpc_fifo << TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT) | \ + (load_tp_fifos << TCA_FIFO_DEBUG_load_tp_fifos_SHIFT) | \ + (fw_full << TCA_FIFO_DEBUG_FW_full_SHIFT) | \ + (not_fw_rtr0 << TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT) | \ + (fw_rts0 << TCA_FIFO_DEBUG_FW_rts0_SHIFT) | \ + (not_fw_tpc_rtr << TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT) | \ + (fw_tpc_rts << TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT)) + +#define TCA_FIFO_DEBUG_GET_tp0_full(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_tp0_full_MASK) >> TCA_FIFO_DEBUG_tp0_full_SHIFT) +#define TCA_FIFO_DEBUG_GET_tpc_full(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_tpc_full_MASK) >> TCA_FIFO_DEBUG_tpc_full_SHIFT) +#define TCA_FIFO_DEBUG_GET_load_tpc_fifo(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_load_tpc_fifo_MASK) >> TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT) +#define TCA_FIFO_DEBUG_GET_load_tp_fifos(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_load_tp_fifos_MASK) >> TCA_FIFO_DEBUG_load_tp_fifos_SHIFT) +#define TCA_FIFO_DEBUG_GET_FW_full(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_full_MASK) >> TCA_FIFO_DEBUG_FW_full_SHIFT) +#define TCA_FIFO_DEBUG_GET_not_FW_rtr0(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_not_FW_rtr0_MASK) >> TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT) +#define TCA_FIFO_DEBUG_GET_FW_rts0(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_rts0_MASK) >> TCA_FIFO_DEBUG_FW_rts0_SHIFT) +#define TCA_FIFO_DEBUG_GET_not_FW_tpc_rtr(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK) >> TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT) +#define TCA_FIFO_DEBUG_GET_FW_tpc_rts(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_tpc_rts_MASK) >> TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT) + +#define TCA_FIFO_DEBUG_SET_tp0_full(tca_fifo_debug_reg, tp0_full) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_tp0_full_MASK) | (tp0_full << TCA_FIFO_DEBUG_tp0_full_SHIFT) +#define TCA_FIFO_DEBUG_SET_tpc_full(tca_fifo_debug_reg, tpc_full) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_tpc_full_MASK) | (tpc_full << TCA_FIFO_DEBUG_tpc_full_SHIFT) +#define TCA_FIFO_DEBUG_SET_load_tpc_fifo(tca_fifo_debug_reg, load_tpc_fifo) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_load_tpc_fifo_MASK) | (load_tpc_fifo << TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT) +#define TCA_FIFO_DEBUG_SET_load_tp_fifos(tca_fifo_debug_reg, load_tp_fifos) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_load_tp_fifos_MASK) | (load_tp_fifos << TCA_FIFO_DEBUG_load_tp_fifos_SHIFT) +#define TCA_FIFO_DEBUG_SET_FW_full(tca_fifo_debug_reg, fw_full) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_full_MASK) | (fw_full << TCA_FIFO_DEBUG_FW_full_SHIFT) +#define TCA_FIFO_DEBUG_SET_not_FW_rtr0(tca_fifo_debug_reg, not_fw_rtr0) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_not_FW_rtr0_MASK) | (not_fw_rtr0 << TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT) +#define TCA_FIFO_DEBUG_SET_FW_rts0(tca_fifo_debug_reg, fw_rts0) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_rts0_MASK) | (fw_rts0 << TCA_FIFO_DEBUG_FW_rts0_SHIFT) +#define TCA_FIFO_DEBUG_SET_not_FW_tpc_rtr(tca_fifo_debug_reg, not_fw_tpc_rtr) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK) | (not_fw_tpc_rtr << TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT) +#define TCA_FIFO_DEBUG_SET_FW_tpc_rts(tca_fifo_debug_reg, fw_tpc_rts) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_tpc_rts_MASK) | (fw_tpc_rts << TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tca_fifo_debug_t { + unsigned int tp0_full : TCA_FIFO_DEBUG_tp0_full_SIZE; + unsigned int : 3; + unsigned int tpc_full : TCA_FIFO_DEBUG_tpc_full_SIZE; + unsigned int load_tpc_fifo : TCA_FIFO_DEBUG_load_tpc_fifo_SIZE; + unsigned int load_tp_fifos : TCA_FIFO_DEBUG_load_tp_fifos_SIZE; + unsigned int fw_full : TCA_FIFO_DEBUG_FW_full_SIZE; + unsigned int not_fw_rtr0 : TCA_FIFO_DEBUG_not_FW_rtr0_SIZE; + unsigned int : 3; + unsigned int fw_rts0 : TCA_FIFO_DEBUG_FW_rts0_SIZE; + unsigned int : 3; + unsigned int not_fw_tpc_rtr : TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE; + unsigned int fw_tpc_rts : TCA_FIFO_DEBUG_FW_tpc_rts_SIZE; + unsigned int : 14; + } tca_fifo_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tca_fifo_debug_t { + unsigned int : 14; + unsigned int fw_tpc_rts : TCA_FIFO_DEBUG_FW_tpc_rts_SIZE; + unsigned int not_fw_tpc_rtr : TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE; + unsigned int : 3; + unsigned int fw_rts0 : TCA_FIFO_DEBUG_FW_rts0_SIZE; + unsigned int : 3; + unsigned int not_fw_rtr0 : TCA_FIFO_DEBUG_not_FW_rtr0_SIZE; + unsigned int fw_full : TCA_FIFO_DEBUG_FW_full_SIZE; + unsigned int load_tp_fifos : TCA_FIFO_DEBUG_load_tp_fifos_SIZE; + unsigned int load_tpc_fifo : TCA_FIFO_DEBUG_load_tpc_fifo_SIZE; + unsigned int tpc_full : TCA_FIFO_DEBUG_tpc_full_SIZE; + unsigned int : 3; + unsigned int tp0_full : TCA_FIFO_DEBUG_tp0_full_SIZE; + } tca_fifo_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tca_fifo_debug_t f; +} tca_fifo_debug_u; + + +/* + * TCA_PROBE_DEBUG struct + */ + +#define TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE 1 + +#define TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT 0 + +#define TCA_PROBE_DEBUG_ProbeFilter_stall_MASK 0x00000001 + +#define TCA_PROBE_DEBUG_MASK \ + (TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) + +#define TCA_PROBE_DEBUG(probefilter_stall) \ + ((probefilter_stall << TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT)) + +#define TCA_PROBE_DEBUG_GET_ProbeFilter_stall(tca_probe_debug) \ + ((tca_probe_debug & TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) >> TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT) + +#define TCA_PROBE_DEBUG_SET_ProbeFilter_stall(tca_probe_debug_reg, probefilter_stall) \ + tca_probe_debug_reg = (tca_probe_debug_reg & ~TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) | (probefilter_stall << TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tca_probe_debug_t { + unsigned int probefilter_stall : TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE; + unsigned int : 31; + } tca_probe_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tca_probe_debug_t { + unsigned int : 31; + unsigned int probefilter_stall : TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE; + } tca_probe_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tca_probe_debug_t f; +} tca_probe_debug_u; + + +/* + * TCA_TPC_DEBUG struct + */ + +#define TCA_TPC_DEBUG_captue_state_rts_SIZE 1 +#define TCA_TPC_DEBUG_capture_tca_rts_SIZE 1 + +#define TCA_TPC_DEBUG_captue_state_rts_SHIFT 12 +#define TCA_TPC_DEBUG_capture_tca_rts_SHIFT 13 + +#define TCA_TPC_DEBUG_captue_state_rts_MASK 0x00001000 +#define TCA_TPC_DEBUG_capture_tca_rts_MASK 0x00002000 + +#define TCA_TPC_DEBUG_MASK \ + (TCA_TPC_DEBUG_captue_state_rts_MASK | \ + TCA_TPC_DEBUG_capture_tca_rts_MASK) + +#define TCA_TPC_DEBUG(captue_state_rts, capture_tca_rts) \ + ((captue_state_rts << TCA_TPC_DEBUG_captue_state_rts_SHIFT) | \ + (capture_tca_rts << TCA_TPC_DEBUG_capture_tca_rts_SHIFT)) + +#define TCA_TPC_DEBUG_GET_captue_state_rts(tca_tpc_debug) \ + ((tca_tpc_debug & TCA_TPC_DEBUG_captue_state_rts_MASK) >> TCA_TPC_DEBUG_captue_state_rts_SHIFT) +#define TCA_TPC_DEBUG_GET_capture_tca_rts(tca_tpc_debug) \ + ((tca_tpc_debug & TCA_TPC_DEBUG_capture_tca_rts_MASK) >> TCA_TPC_DEBUG_capture_tca_rts_SHIFT) + +#define TCA_TPC_DEBUG_SET_captue_state_rts(tca_tpc_debug_reg, captue_state_rts) \ + tca_tpc_debug_reg = (tca_tpc_debug_reg & ~TCA_TPC_DEBUG_captue_state_rts_MASK) | (captue_state_rts << TCA_TPC_DEBUG_captue_state_rts_SHIFT) +#define TCA_TPC_DEBUG_SET_capture_tca_rts(tca_tpc_debug_reg, capture_tca_rts) \ + tca_tpc_debug_reg = (tca_tpc_debug_reg & ~TCA_TPC_DEBUG_capture_tca_rts_MASK) | (capture_tca_rts << TCA_TPC_DEBUG_capture_tca_rts_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tca_tpc_debug_t { + unsigned int : 12; + unsigned int captue_state_rts : TCA_TPC_DEBUG_captue_state_rts_SIZE; + unsigned int capture_tca_rts : TCA_TPC_DEBUG_capture_tca_rts_SIZE; + unsigned int : 18; + } tca_tpc_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tca_tpc_debug_t { + unsigned int : 18; + unsigned int capture_tca_rts : TCA_TPC_DEBUG_capture_tca_rts_SIZE; + unsigned int captue_state_rts : TCA_TPC_DEBUG_captue_state_rts_SIZE; + unsigned int : 12; + } tca_tpc_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tca_tpc_debug_t f; +} tca_tpc_debug_u; + + +/* + * TCB_CORE_DEBUG struct + */ + +#define TCB_CORE_DEBUG_access512_SIZE 1 +#define TCB_CORE_DEBUG_tiled_SIZE 1 +#define TCB_CORE_DEBUG_opcode_SIZE 3 +#define TCB_CORE_DEBUG_format_SIZE 6 +#define TCB_CORE_DEBUG_sector_format_SIZE 5 +#define TCB_CORE_DEBUG_sector_format512_SIZE 3 + +#define TCB_CORE_DEBUG_access512_SHIFT 0 +#define TCB_CORE_DEBUG_tiled_SHIFT 1 +#define TCB_CORE_DEBUG_opcode_SHIFT 4 +#define TCB_CORE_DEBUG_format_SHIFT 8 +#define TCB_CORE_DEBUG_sector_format_SHIFT 16 +#define TCB_CORE_DEBUG_sector_format512_SHIFT 24 + +#define TCB_CORE_DEBUG_access512_MASK 0x00000001 +#define TCB_CORE_DEBUG_tiled_MASK 0x00000002 +#define TCB_CORE_DEBUG_opcode_MASK 0x00000070 +#define TCB_CORE_DEBUG_format_MASK 0x00003f00 +#define TCB_CORE_DEBUG_sector_format_MASK 0x001f0000 +#define TCB_CORE_DEBUG_sector_format512_MASK 0x07000000 + +#define TCB_CORE_DEBUG_MASK \ + (TCB_CORE_DEBUG_access512_MASK | \ + TCB_CORE_DEBUG_tiled_MASK | \ + TCB_CORE_DEBUG_opcode_MASK | \ + TCB_CORE_DEBUG_format_MASK | \ + TCB_CORE_DEBUG_sector_format_MASK | \ + TCB_CORE_DEBUG_sector_format512_MASK) + +#define TCB_CORE_DEBUG(access512, tiled, opcode, format, sector_format, sector_format512) \ + ((access512 << TCB_CORE_DEBUG_access512_SHIFT) | \ + (tiled << TCB_CORE_DEBUG_tiled_SHIFT) | \ + (opcode << TCB_CORE_DEBUG_opcode_SHIFT) | \ + (format << TCB_CORE_DEBUG_format_SHIFT) | \ + (sector_format << TCB_CORE_DEBUG_sector_format_SHIFT) | \ + (sector_format512 << TCB_CORE_DEBUG_sector_format512_SHIFT)) + +#define TCB_CORE_DEBUG_GET_access512(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_access512_MASK) >> TCB_CORE_DEBUG_access512_SHIFT) +#define TCB_CORE_DEBUG_GET_tiled(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_tiled_MASK) >> TCB_CORE_DEBUG_tiled_SHIFT) +#define TCB_CORE_DEBUG_GET_opcode(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_opcode_MASK) >> TCB_CORE_DEBUG_opcode_SHIFT) +#define TCB_CORE_DEBUG_GET_format(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_format_MASK) >> TCB_CORE_DEBUG_format_SHIFT) +#define TCB_CORE_DEBUG_GET_sector_format(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_sector_format_MASK) >> TCB_CORE_DEBUG_sector_format_SHIFT) +#define TCB_CORE_DEBUG_GET_sector_format512(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_sector_format512_MASK) >> TCB_CORE_DEBUG_sector_format512_SHIFT) + +#define TCB_CORE_DEBUG_SET_access512(tcb_core_debug_reg, access512) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_access512_MASK) | (access512 << TCB_CORE_DEBUG_access512_SHIFT) +#define TCB_CORE_DEBUG_SET_tiled(tcb_core_debug_reg, tiled) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_tiled_MASK) | (tiled << TCB_CORE_DEBUG_tiled_SHIFT) +#define TCB_CORE_DEBUG_SET_opcode(tcb_core_debug_reg, opcode) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_opcode_MASK) | (opcode << TCB_CORE_DEBUG_opcode_SHIFT) +#define TCB_CORE_DEBUG_SET_format(tcb_core_debug_reg, format) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_format_MASK) | (format << TCB_CORE_DEBUG_format_SHIFT) +#define TCB_CORE_DEBUG_SET_sector_format(tcb_core_debug_reg, sector_format) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_sector_format_MASK) | (sector_format << TCB_CORE_DEBUG_sector_format_SHIFT) +#define TCB_CORE_DEBUG_SET_sector_format512(tcb_core_debug_reg, sector_format512) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_sector_format512_MASK) | (sector_format512 << TCB_CORE_DEBUG_sector_format512_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_core_debug_t { + unsigned int access512 : TCB_CORE_DEBUG_access512_SIZE; + unsigned int tiled : TCB_CORE_DEBUG_tiled_SIZE; + unsigned int : 2; + unsigned int opcode : TCB_CORE_DEBUG_opcode_SIZE; + unsigned int : 1; + unsigned int format : TCB_CORE_DEBUG_format_SIZE; + unsigned int : 2; + unsigned int sector_format : TCB_CORE_DEBUG_sector_format_SIZE; + unsigned int : 3; + unsigned int sector_format512 : TCB_CORE_DEBUG_sector_format512_SIZE; + unsigned int : 5; + } tcb_core_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_core_debug_t { + unsigned int : 5; + unsigned int sector_format512 : TCB_CORE_DEBUG_sector_format512_SIZE; + unsigned int : 3; + unsigned int sector_format : TCB_CORE_DEBUG_sector_format_SIZE; + unsigned int : 2; + unsigned int format : TCB_CORE_DEBUG_format_SIZE; + unsigned int : 1; + unsigned int opcode : TCB_CORE_DEBUG_opcode_SIZE; + unsigned int : 2; + unsigned int tiled : TCB_CORE_DEBUG_tiled_SIZE; + unsigned int access512 : TCB_CORE_DEBUG_access512_SIZE; + } tcb_core_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_core_debug_t f; +} tcb_core_debug_u; + + +/* + * TCB_TAG0_DEBUG struct + */ + +#define TCB_TAG0_DEBUG_mem_read_cycle_SIZE 10 +#define TCB_TAG0_DEBUG_tag_access_cycle_SIZE 9 +#define TCB_TAG0_DEBUG_miss_stall_SIZE 1 +#define TCB_TAG0_DEBUG_num_feee_lines_SIZE 5 +#define TCB_TAG0_DEBUG_max_misses_SIZE 3 + +#define TCB_TAG0_DEBUG_mem_read_cycle_SHIFT 0 +#define TCB_TAG0_DEBUG_tag_access_cycle_SHIFT 12 +#define TCB_TAG0_DEBUG_miss_stall_SHIFT 23 +#define TCB_TAG0_DEBUG_num_feee_lines_SHIFT 24 +#define TCB_TAG0_DEBUG_max_misses_SHIFT 29 + +#define TCB_TAG0_DEBUG_mem_read_cycle_MASK 0x000003ff +#define TCB_TAG0_DEBUG_tag_access_cycle_MASK 0x001ff000 +#define TCB_TAG0_DEBUG_miss_stall_MASK 0x00800000 +#define TCB_TAG0_DEBUG_num_feee_lines_MASK 0x1f000000 +#define TCB_TAG0_DEBUG_max_misses_MASK 0xe0000000 + +#define TCB_TAG0_DEBUG_MASK \ + (TCB_TAG0_DEBUG_mem_read_cycle_MASK | \ + TCB_TAG0_DEBUG_tag_access_cycle_MASK | \ + TCB_TAG0_DEBUG_miss_stall_MASK | \ + TCB_TAG0_DEBUG_num_feee_lines_MASK | \ + TCB_TAG0_DEBUG_max_misses_MASK) + +#define TCB_TAG0_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \ + ((mem_read_cycle << TCB_TAG0_DEBUG_mem_read_cycle_SHIFT) | \ + (tag_access_cycle << TCB_TAG0_DEBUG_tag_access_cycle_SHIFT) | \ + (miss_stall << TCB_TAG0_DEBUG_miss_stall_SHIFT) | \ + (num_feee_lines << TCB_TAG0_DEBUG_num_feee_lines_SHIFT) | \ + (max_misses << TCB_TAG0_DEBUG_max_misses_SHIFT)) + +#define TCB_TAG0_DEBUG_GET_mem_read_cycle(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_mem_read_cycle_MASK) >> TCB_TAG0_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG0_DEBUG_GET_tag_access_cycle(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_tag_access_cycle_MASK) >> TCB_TAG0_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG0_DEBUG_GET_miss_stall(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_miss_stall_MASK) >> TCB_TAG0_DEBUG_miss_stall_SHIFT) +#define TCB_TAG0_DEBUG_GET_num_feee_lines(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_num_feee_lines_MASK) >> TCB_TAG0_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG0_DEBUG_GET_max_misses(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_max_misses_MASK) >> TCB_TAG0_DEBUG_max_misses_SHIFT) + +#define TCB_TAG0_DEBUG_SET_mem_read_cycle(tcb_tag0_debug_reg, mem_read_cycle) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG0_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG0_DEBUG_SET_tag_access_cycle(tcb_tag0_debug_reg, tag_access_cycle) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG0_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG0_DEBUG_SET_miss_stall(tcb_tag0_debug_reg, miss_stall) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG0_DEBUG_miss_stall_SHIFT) +#define TCB_TAG0_DEBUG_SET_num_feee_lines(tcb_tag0_debug_reg, num_feee_lines) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG0_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG0_DEBUG_SET_max_misses(tcb_tag0_debug_reg, max_misses) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG0_DEBUG_max_misses_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_tag0_debug_t { + unsigned int mem_read_cycle : TCB_TAG0_DEBUG_mem_read_cycle_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG0_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int miss_stall : TCB_TAG0_DEBUG_miss_stall_SIZE; + unsigned int num_feee_lines : TCB_TAG0_DEBUG_num_feee_lines_SIZE; + unsigned int max_misses : TCB_TAG0_DEBUG_max_misses_SIZE; + } tcb_tag0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_tag0_debug_t { + unsigned int max_misses : TCB_TAG0_DEBUG_max_misses_SIZE; + unsigned int num_feee_lines : TCB_TAG0_DEBUG_num_feee_lines_SIZE; + unsigned int miss_stall : TCB_TAG0_DEBUG_miss_stall_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG0_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int mem_read_cycle : TCB_TAG0_DEBUG_mem_read_cycle_SIZE; + } tcb_tag0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_tag0_debug_t f; +} tcb_tag0_debug_u; + + +/* + * TCB_TAG1_DEBUG struct + */ + +#define TCB_TAG1_DEBUG_mem_read_cycle_SIZE 10 +#define TCB_TAG1_DEBUG_tag_access_cycle_SIZE 9 +#define TCB_TAG1_DEBUG_miss_stall_SIZE 1 +#define TCB_TAG1_DEBUG_num_feee_lines_SIZE 5 +#define TCB_TAG1_DEBUG_max_misses_SIZE 3 + +#define TCB_TAG1_DEBUG_mem_read_cycle_SHIFT 0 +#define TCB_TAG1_DEBUG_tag_access_cycle_SHIFT 12 +#define TCB_TAG1_DEBUG_miss_stall_SHIFT 23 +#define TCB_TAG1_DEBUG_num_feee_lines_SHIFT 24 +#define TCB_TAG1_DEBUG_max_misses_SHIFT 29 + +#define TCB_TAG1_DEBUG_mem_read_cycle_MASK 0x000003ff +#define TCB_TAG1_DEBUG_tag_access_cycle_MASK 0x001ff000 +#define TCB_TAG1_DEBUG_miss_stall_MASK 0x00800000 +#define TCB_TAG1_DEBUG_num_feee_lines_MASK 0x1f000000 +#define TCB_TAG1_DEBUG_max_misses_MASK 0xe0000000 + +#define TCB_TAG1_DEBUG_MASK \ + (TCB_TAG1_DEBUG_mem_read_cycle_MASK | \ + TCB_TAG1_DEBUG_tag_access_cycle_MASK | \ + TCB_TAG1_DEBUG_miss_stall_MASK | \ + TCB_TAG1_DEBUG_num_feee_lines_MASK | \ + TCB_TAG1_DEBUG_max_misses_MASK) + +#define TCB_TAG1_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \ + ((mem_read_cycle << TCB_TAG1_DEBUG_mem_read_cycle_SHIFT) | \ + (tag_access_cycle << TCB_TAG1_DEBUG_tag_access_cycle_SHIFT) | \ + (miss_stall << TCB_TAG1_DEBUG_miss_stall_SHIFT) | \ + (num_feee_lines << TCB_TAG1_DEBUG_num_feee_lines_SHIFT) | \ + (max_misses << TCB_TAG1_DEBUG_max_misses_SHIFT)) + +#define TCB_TAG1_DEBUG_GET_mem_read_cycle(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_mem_read_cycle_MASK) >> TCB_TAG1_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG1_DEBUG_GET_tag_access_cycle(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_tag_access_cycle_MASK) >> TCB_TAG1_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG1_DEBUG_GET_miss_stall(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_miss_stall_MASK) >> TCB_TAG1_DEBUG_miss_stall_SHIFT) +#define TCB_TAG1_DEBUG_GET_num_feee_lines(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_num_feee_lines_MASK) >> TCB_TAG1_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG1_DEBUG_GET_max_misses(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_max_misses_MASK) >> TCB_TAG1_DEBUG_max_misses_SHIFT) + +#define TCB_TAG1_DEBUG_SET_mem_read_cycle(tcb_tag1_debug_reg, mem_read_cycle) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG1_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG1_DEBUG_SET_tag_access_cycle(tcb_tag1_debug_reg, tag_access_cycle) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG1_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG1_DEBUG_SET_miss_stall(tcb_tag1_debug_reg, miss_stall) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG1_DEBUG_miss_stall_SHIFT) +#define TCB_TAG1_DEBUG_SET_num_feee_lines(tcb_tag1_debug_reg, num_feee_lines) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG1_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG1_DEBUG_SET_max_misses(tcb_tag1_debug_reg, max_misses) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG1_DEBUG_max_misses_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_tag1_debug_t { + unsigned int mem_read_cycle : TCB_TAG1_DEBUG_mem_read_cycle_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG1_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int miss_stall : TCB_TAG1_DEBUG_miss_stall_SIZE; + unsigned int num_feee_lines : TCB_TAG1_DEBUG_num_feee_lines_SIZE; + unsigned int max_misses : TCB_TAG1_DEBUG_max_misses_SIZE; + } tcb_tag1_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_tag1_debug_t { + unsigned int max_misses : TCB_TAG1_DEBUG_max_misses_SIZE; + unsigned int num_feee_lines : TCB_TAG1_DEBUG_num_feee_lines_SIZE; + unsigned int miss_stall : TCB_TAG1_DEBUG_miss_stall_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG1_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int mem_read_cycle : TCB_TAG1_DEBUG_mem_read_cycle_SIZE; + } tcb_tag1_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_tag1_debug_t f; +} tcb_tag1_debug_u; + + +/* + * TCB_TAG2_DEBUG struct + */ + +#define TCB_TAG2_DEBUG_mem_read_cycle_SIZE 10 +#define TCB_TAG2_DEBUG_tag_access_cycle_SIZE 9 +#define TCB_TAG2_DEBUG_miss_stall_SIZE 1 +#define TCB_TAG2_DEBUG_num_feee_lines_SIZE 5 +#define TCB_TAG2_DEBUG_max_misses_SIZE 3 + +#define TCB_TAG2_DEBUG_mem_read_cycle_SHIFT 0 +#define TCB_TAG2_DEBUG_tag_access_cycle_SHIFT 12 +#define TCB_TAG2_DEBUG_miss_stall_SHIFT 23 +#define TCB_TAG2_DEBUG_num_feee_lines_SHIFT 24 +#define TCB_TAG2_DEBUG_max_misses_SHIFT 29 + +#define TCB_TAG2_DEBUG_mem_read_cycle_MASK 0x000003ff +#define TCB_TAG2_DEBUG_tag_access_cycle_MASK 0x001ff000 +#define TCB_TAG2_DEBUG_miss_stall_MASK 0x00800000 +#define TCB_TAG2_DEBUG_num_feee_lines_MASK 0x1f000000 +#define TCB_TAG2_DEBUG_max_misses_MASK 0xe0000000 + +#define TCB_TAG2_DEBUG_MASK \ + (TCB_TAG2_DEBUG_mem_read_cycle_MASK | \ + TCB_TAG2_DEBUG_tag_access_cycle_MASK | \ + TCB_TAG2_DEBUG_miss_stall_MASK | \ + TCB_TAG2_DEBUG_num_feee_lines_MASK | \ + TCB_TAG2_DEBUG_max_misses_MASK) + +#define TCB_TAG2_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \ + ((mem_read_cycle << TCB_TAG2_DEBUG_mem_read_cycle_SHIFT) | \ + (tag_access_cycle << TCB_TAG2_DEBUG_tag_access_cycle_SHIFT) | \ + (miss_stall << TCB_TAG2_DEBUG_miss_stall_SHIFT) | \ + (num_feee_lines << TCB_TAG2_DEBUG_num_feee_lines_SHIFT) | \ + (max_misses << TCB_TAG2_DEBUG_max_misses_SHIFT)) + +#define TCB_TAG2_DEBUG_GET_mem_read_cycle(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_mem_read_cycle_MASK) >> TCB_TAG2_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG2_DEBUG_GET_tag_access_cycle(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_tag_access_cycle_MASK) >> TCB_TAG2_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG2_DEBUG_GET_miss_stall(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_miss_stall_MASK) >> TCB_TAG2_DEBUG_miss_stall_SHIFT) +#define TCB_TAG2_DEBUG_GET_num_feee_lines(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_num_feee_lines_MASK) >> TCB_TAG2_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG2_DEBUG_GET_max_misses(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_max_misses_MASK) >> TCB_TAG2_DEBUG_max_misses_SHIFT) + +#define TCB_TAG2_DEBUG_SET_mem_read_cycle(tcb_tag2_debug_reg, mem_read_cycle) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG2_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG2_DEBUG_SET_tag_access_cycle(tcb_tag2_debug_reg, tag_access_cycle) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG2_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG2_DEBUG_SET_miss_stall(tcb_tag2_debug_reg, miss_stall) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG2_DEBUG_miss_stall_SHIFT) +#define TCB_TAG2_DEBUG_SET_num_feee_lines(tcb_tag2_debug_reg, num_feee_lines) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG2_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG2_DEBUG_SET_max_misses(tcb_tag2_debug_reg, max_misses) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG2_DEBUG_max_misses_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_tag2_debug_t { + unsigned int mem_read_cycle : TCB_TAG2_DEBUG_mem_read_cycle_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG2_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int miss_stall : TCB_TAG2_DEBUG_miss_stall_SIZE; + unsigned int num_feee_lines : TCB_TAG2_DEBUG_num_feee_lines_SIZE; + unsigned int max_misses : TCB_TAG2_DEBUG_max_misses_SIZE; + } tcb_tag2_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_tag2_debug_t { + unsigned int max_misses : TCB_TAG2_DEBUG_max_misses_SIZE; + unsigned int num_feee_lines : TCB_TAG2_DEBUG_num_feee_lines_SIZE; + unsigned int miss_stall : TCB_TAG2_DEBUG_miss_stall_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG2_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int mem_read_cycle : TCB_TAG2_DEBUG_mem_read_cycle_SIZE; + } tcb_tag2_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_tag2_debug_t f; +} tcb_tag2_debug_u; + + +/* + * TCB_TAG3_DEBUG struct + */ + +#define TCB_TAG3_DEBUG_mem_read_cycle_SIZE 10 +#define TCB_TAG3_DEBUG_tag_access_cycle_SIZE 9 +#define TCB_TAG3_DEBUG_miss_stall_SIZE 1 +#define TCB_TAG3_DEBUG_num_feee_lines_SIZE 5 +#define TCB_TAG3_DEBUG_max_misses_SIZE 3 + +#define TCB_TAG3_DEBUG_mem_read_cycle_SHIFT 0 +#define TCB_TAG3_DEBUG_tag_access_cycle_SHIFT 12 +#define TCB_TAG3_DEBUG_miss_stall_SHIFT 23 +#define TCB_TAG3_DEBUG_num_feee_lines_SHIFT 24 +#define TCB_TAG3_DEBUG_max_misses_SHIFT 29 + +#define TCB_TAG3_DEBUG_mem_read_cycle_MASK 0x000003ff +#define TCB_TAG3_DEBUG_tag_access_cycle_MASK 0x001ff000 +#define TCB_TAG3_DEBUG_miss_stall_MASK 0x00800000 +#define TCB_TAG3_DEBUG_num_feee_lines_MASK 0x1f000000 +#define TCB_TAG3_DEBUG_max_misses_MASK 0xe0000000 + +#define TCB_TAG3_DEBUG_MASK \ + (TCB_TAG3_DEBUG_mem_read_cycle_MASK | \ + TCB_TAG3_DEBUG_tag_access_cycle_MASK | \ + TCB_TAG3_DEBUG_miss_stall_MASK | \ + TCB_TAG3_DEBUG_num_feee_lines_MASK | \ + TCB_TAG3_DEBUG_max_misses_MASK) + +#define TCB_TAG3_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \ + ((mem_read_cycle << TCB_TAG3_DEBUG_mem_read_cycle_SHIFT) | \ + (tag_access_cycle << TCB_TAG3_DEBUG_tag_access_cycle_SHIFT) | \ + (miss_stall << TCB_TAG3_DEBUG_miss_stall_SHIFT) | \ + (num_feee_lines << TCB_TAG3_DEBUG_num_feee_lines_SHIFT) | \ + (max_misses << TCB_TAG3_DEBUG_max_misses_SHIFT)) + +#define TCB_TAG3_DEBUG_GET_mem_read_cycle(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_mem_read_cycle_MASK) >> TCB_TAG3_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG3_DEBUG_GET_tag_access_cycle(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_tag_access_cycle_MASK) >> TCB_TAG3_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG3_DEBUG_GET_miss_stall(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_miss_stall_MASK) >> TCB_TAG3_DEBUG_miss_stall_SHIFT) +#define TCB_TAG3_DEBUG_GET_num_feee_lines(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_num_feee_lines_MASK) >> TCB_TAG3_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG3_DEBUG_GET_max_misses(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_max_misses_MASK) >> TCB_TAG3_DEBUG_max_misses_SHIFT) + +#define TCB_TAG3_DEBUG_SET_mem_read_cycle(tcb_tag3_debug_reg, mem_read_cycle) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG3_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG3_DEBUG_SET_tag_access_cycle(tcb_tag3_debug_reg, tag_access_cycle) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG3_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG3_DEBUG_SET_miss_stall(tcb_tag3_debug_reg, miss_stall) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG3_DEBUG_miss_stall_SHIFT) +#define TCB_TAG3_DEBUG_SET_num_feee_lines(tcb_tag3_debug_reg, num_feee_lines) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG3_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG3_DEBUG_SET_max_misses(tcb_tag3_debug_reg, max_misses) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG3_DEBUG_max_misses_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_tag3_debug_t { + unsigned int mem_read_cycle : TCB_TAG3_DEBUG_mem_read_cycle_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG3_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int miss_stall : TCB_TAG3_DEBUG_miss_stall_SIZE; + unsigned int num_feee_lines : TCB_TAG3_DEBUG_num_feee_lines_SIZE; + unsigned int max_misses : TCB_TAG3_DEBUG_max_misses_SIZE; + } tcb_tag3_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_tag3_debug_t { + unsigned int max_misses : TCB_TAG3_DEBUG_max_misses_SIZE; + unsigned int num_feee_lines : TCB_TAG3_DEBUG_num_feee_lines_SIZE; + unsigned int miss_stall : TCB_TAG3_DEBUG_miss_stall_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG3_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int mem_read_cycle : TCB_TAG3_DEBUG_mem_read_cycle_SIZE; + } tcb_tag3_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_tag3_debug_t f; +} tcb_tag3_debug_u; + + +/* + * TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG struct + */ + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE 5 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE 16 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE 1 + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT 0 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT 2 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT 4 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT 5 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT 6 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT 7 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT 12 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT 28 + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK 0x00000001 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK 0x00000004 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK 0x00000010 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK 0x00000020 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK 0x00000040 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK 0x00000f80 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK 0x0ffff000 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK 0x10000000 + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_MASK \ + (TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG(left_done, fg0_sends_left, one_sector_to_go_left_q, no_sectors_to_go, update_left, sector_mask_left_count_q, sector_mask_left_q, valid_left_q) \ + ((left_done << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT) | \ + (fg0_sends_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT) | \ + (one_sector_to_go_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT) | \ + (no_sectors_to_go << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT) | \ + (update_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT) | \ + (sector_mask_left_count_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT) | \ + (sector_mask_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT) | \ + (valid_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT)) + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_left_done(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_fg0_sends_left(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_one_sector_to_go_left_q(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_no_sectors_to_go(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_update_left(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_sector_mask_left_count_q(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_sector_mask_left_q(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_valid_left_q(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT) + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_left_done(tcb_fetch_gen_sector_walker0_debug_reg, left_done) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK) | (left_done << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_fg0_sends_left(tcb_fetch_gen_sector_walker0_debug_reg, fg0_sends_left) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK) | (fg0_sends_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_one_sector_to_go_left_q(tcb_fetch_gen_sector_walker0_debug_reg, one_sector_to_go_left_q) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK) | (one_sector_to_go_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_no_sectors_to_go(tcb_fetch_gen_sector_walker0_debug_reg, no_sectors_to_go) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK) | (no_sectors_to_go << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_update_left(tcb_fetch_gen_sector_walker0_debug_reg, update_left) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK) | (update_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_sector_mask_left_count_q(tcb_fetch_gen_sector_walker0_debug_reg, sector_mask_left_count_q) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK) | (sector_mask_left_count_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_sector_mask_left_q(tcb_fetch_gen_sector_walker0_debug_reg, sector_mask_left_q) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK) | (sector_mask_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_valid_left_q(tcb_fetch_gen_sector_walker0_debug_reg, valid_left_q) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) | (valid_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_sector_walker0_debug_t { + unsigned int left_done : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE; + unsigned int : 1; + unsigned int fg0_sends_left : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE; + unsigned int : 1; + unsigned int one_sector_to_go_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE; + unsigned int no_sectors_to_go : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE; + unsigned int update_left : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE; + unsigned int sector_mask_left_count_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE; + unsigned int sector_mask_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE; + unsigned int valid_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE; + unsigned int : 3; + } tcb_fetch_gen_sector_walker0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_sector_walker0_debug_t { + unsigned int : 3; + unsigned int valid_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE; + unsigned int sector_mask_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE; + unsigned int sector_mask_left_count_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE; + unsigned int update_left : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE; + unsigned int no_sectors_to_go : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE; + unsigned int one_sector_to_go_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE; + unsigned int : 1; + unsigned int fg0_sends_left : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE; + unsigned int : 1; + unsigned int left_done : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE; + } tcb_fetch_gen_sector_walker0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_fetch_gen_sector_walker0_debug_t f; +} tcb_fetch_gen_sector_walker0_debug_u; + + +/* + * TCB_FETCH_GEN_WALKER_DEBUG struct + */ + +#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE 2 +#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE 2 +#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE 1 +#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE 3 +#define TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE 1 +#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE 4 + +#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT 4 +#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT 6 +#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT 11 +#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT 12 +#define TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT 15 +#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT 16 + +#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK 0x00000030 +#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK 0x000000c0 +#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK 0x00000800 +#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK 0x00007000 +#define TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK 0x00008000 +#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK 0x000f0000 + +#define TCB_FETCH_GEN_WALKER_DEBUG_MASK \ + (TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) + +#define TCB_FETCH_GEN_WALKER_DEBUG(quad_sel_left, set_sel_left, right_eq_left, ff_fg_type512, busy, setquads_to_send) \ + ((quad_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT) | \ + (set_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT) | \ + (right_eq_left << TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT) | \ + (ff_fg_type512 << TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT) | \ + (busy << TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT) | \ + (setquads_to_send << TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT)) + +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_quad_sel_left(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_set_sel_left(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_right_eq_left(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_ff_fg_type512(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_busy(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_setquads_to_send(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT) + +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_quad_sel_left(tcb_fetch_gen_walker_debug_reg, quad_sel_left) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK) | (quad_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_set_sel_left(tcb_fetch_gen_walker_debug_reg, set_sel_left) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK) | (set_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_right_eq_left(tcb_fetch_gen_walker_debug_reg, right_eq_left) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK) | (right_eq_left << TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_ff_fg_type512(tcb_fetch_gen_walker_debug_reg, ff_fg_type512) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK) | (ff_fg_type512 << TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_busy(tcb_fetch_gen_walker_debug_reg, busy) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK) | (busy << TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_setquads_to_send(tcb_fetch_gen_walker_debug_reg, setquads_to_send) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) | (setquads_to_send << TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_walker_debug_t { + unsigned int : 4; + unsigned int quad_sel_left : TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE; + unsigned int set_sel_left : TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE; + unsigned int : 3; + unsigned int right_eq_left : TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE; + unsigned int ff_fg_type512 : TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE; + unsigned int busy : TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE; + unsigned int setquads_to_send : TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE; + unsigned int : 12; + } tcb_fetch_gen_walker_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_walker_debug_t { + unsigned int : 12; + unsigned int setquads_to_send : TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE; + unsigned int busy : TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE; + unsigned int ff_fg_type512 : TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE; + unsigned int right_eq_left : TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE; + unsigned int : 3; + unsigned int set_sel_left : TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE; + unsigned int quad_sel_left : TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE; + unsigned int : 4; + } tcb_fetch_gen_walker_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_fetch_gen_walker_debug_t f; +} tcb_fetch_gen_walker_debug_u; + + +/* + * TCB_FETCH_GEN_PIPE0_DEBUG struct + */ + +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE 12 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE 5 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE 2 +#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE 2 +#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE 1 + +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT 0 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT 2 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT 4 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT 16 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT 21 +#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT 23 +#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT 24 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT 25 +#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT 26 +#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT 28 +#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT 30 + +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK 0x00000001 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK 0x00000004 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK 0x0000fff0 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK 0x001f0000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK 0x00600000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK 0x00800000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK 0x01000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK 0x02000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK 0x0c000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK 0x10000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK 0x40000000 + +#define TCB_FETCH_GEN_PIPE0_DEBUG_MASK \ + (TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) + +#define TCB_FETCH_GEN_PIPE0_DEBUG(tc0_arb_rts, ga_out_rts, tc_arb_format, tc_arb_fmsopcode, tc_arb_request_type, busy, fgo_busy, ga_busy, mc_sel_q, valid_q, arb_rtr) \ + ((tc0_arb_rts << TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT) | \ + (ga_out_rts << TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT) | \ + (tc_arb_format << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT) | \ + (tc_arb_fmsopcode << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT) | \ + (tc_arb_request_type << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT) | \ + (busy << TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT) | \ + (fgo_busy << TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT) | \ + (ga_busy << TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT) | \ + (mc_sel_q << TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT) | \ + (valid_q << TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT) | \ + (arb_rtr << TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT)) + +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc0_arb_rts(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_ga_out_rts(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_format(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_fmsopcode(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_request_type(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_busy(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_fgo_busy(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_ga_busy(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_mc_sel_q(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_valid_q(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_arb_RTR(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT) + +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc0_arb_rts(tcb_fetch_gen_pipe0_debug_reg, tc0_arb_rts) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK) | (tc0_arb_rts << TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_ga_out_rts(tcb_fetch_gen_pipe0_debug_reg, ga_out_rts) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK) | (ga_out_rts << TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_format(tcb_fetch_gen_pipe0_debug_reg, tc_arb_format) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK) | (tc_arb_format << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_fmsopcode(tcb_fetch_gen_pipe0_debug_reg, tc_arb_fmsopcode) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK) | (tc_arb_fmsopcode << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_request_type(tcb_fetch_gen_pipe0_debug_reg, tc_arb_request_type) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK) | (tc_arb_request_type << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_busy(tcb_fetch_gen_pipe0_debug_reg, busy) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK) | (busy << TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_fgo_busy(tcb_fetch_gen_pipe0_debug_reg, fgo_busy) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK) | (fgo_busy << TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_ga_busy(tcb_fetch_gen_pipe0_debug_reg, ga_busy) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK) | (ga_busy << TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_mc_sel_q(tcb_fetch_gen_pipe0_debug_reg, mc_sel_q) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK) | (mc_sel_q << TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_valid_q(tcb_fetch_gen_pipe0_debug_reg, valid_q) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK) | (valid_q << TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_arb_RTR(tcb_fetch_gen_pipe0_debug_reg, arb_rtr) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) | (arb_rtr << TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_pipe0_debug_t { + unsigned int tc0_arb_rts : TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE; + unsigned int : 1; + unsigned int ga_out_rts : TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE; + unsigned int : 1; + unsigned int tc_arb_format : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE; + unsigned int tc_arb_fmsopcode : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE; + unsigned int tc_arb_request_type : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE; + unsigned int busy : TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE; + unsigned int fgo_busy : TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE; + unsigned int ga_busy : TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE; + unsigned int mc_sel_q : TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE; + unsigned int valid_q : TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE; + unsigned int : 1; + unsigned int arb_rtr : TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE; + unsigned int : 1; + } tcb_fetch_gen_pipe0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_pipe0_debug_t { + unsigned int : 1; + unsigned int arb_rtr : TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE; + unsigned int : 1; + unsigned int valid_q : TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE; + unsigned int mc_sel_q : TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE; + unsigned int ga_busy : TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE; + unsigned int fgo_busy : TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE; + unsigned int busy : TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE; + unsigned int tc_arb_request_type : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE; + unsigned int tc_arb_fmsopcode : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE; + unsigned int tc_arb_format : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE; + unsigned int : 1; + unsigned int ga_out_rts : TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE; + unsigned int : 1; + unsigned int tc0_arb_rts : TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE; + } tcb_fetch_gen_pipe0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_fetch_gen_pipe0_debug_t f; +} tcb_fetch_gen_pipe0_debug_u; + + +/* + * TCD_INPUT0_DEBUG struct + */ + +#define TCD_INPUT0_DEBUG_empty_SIZE 1 +#define TCD_INPUT0_DEBUG_full_SIZE 1 +#define TCD_INPUT0_DEBUG_valid_q1_SIZE 1 +#define TCD_INPUT0_DEBUG_cnt_q1_SIZE 2 +#define TCD_INPUT0_DEBUG_last_send_q1_SIZE 1 +#define TCD_INPUT0_DEBUG_ip_send_SIZE 1 +#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE 1 +#define TCD_INPUT0_DEBUG_ipbuf_busy_SIZE 1 + +#define TCD_INPUT0_DEBUG_empty_SHIFT 16 +#define TCD_INPUT0_DEBUG_full_SHIFT 17 +#define TCD_INPUT0_DEBUG_valid_q1_SHIFT 20 +#define TCD_INPUT0_DEBUG_cnt_q1_SHIFT 21 +#define TCD_INPUT0_DEBUG_last_send_q1_SHIFT 23 +#define TCD_INPUT0_DEBUG_ip_send_SHIFT 24 +#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT 25 +#define TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT 26 + +#define TCD_INPUT0_DEBUG_empty_MASK 0x00010000 +#define TCD_INPUT0_DEBUG_full_MASK 0x00020000 +#define TCD_INPUT0_DEBUG_valid_q1_MASK 0x00100000 +#define TCD_INPUT0_DEBUG_cnt_q1_MASK 0x00600000 +#define TCD_INPUT0_DEBUG_last_send_q1_MASK 0x00800000 +#define TCD_INPUT0_DEBUG_ip_send_MASK 0x01000000 +#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK 0x02000000 +#define TCD_INPUT0_DEBUG_ipbuf_busy_MASK 0x04000000 + +#define TCD_INPUT0_DEBUG_MASK \ + (TCD_INPUT0_DEBUG_empty_MASK | \ + TCD_INPUT0_DEBUG_full_MASK | \ + TCD_INPUT0_DEBUG_valid_q1_MASK | \ + TCD_INPUT0_DEBUG_cnt_q1_MASK | \ + TCD_INPUT0_DEBUG_last_send_q1_MASK | \ + TCD_INPUT0_DEBUG_ip_send_MASK | \ + TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK | \ + TCD_INPUT0_DEBUG_ipbuf_busy_MASK) + +#define TCD_INPUT0_DEBUG(empty, full, valid_q1, cnt_q1, last_send_q1, ip_send, ipbuf_dxt_send, ipbuf_busy) \ + ((empty << TCD_INPUT0_DEBUG_empty_SHIFT) | \ + (full << TCD_INPUT0_DEBUG_full_SHIFT) | \ + (valid_q1 << TCD_INPUT0_DEBUG_valid_q1_SHIFT) | \ + (cnt_q1 << TCD_INPUT0_DEBUG_cnt_q1_SHIFT) | \ + (last_send_q1 << TCD_INPUT0_DEBUG_last_send_q1_SHIFT) | \ + (ip_send << TCD_INPUT0_DEBUG_ip_send_SHIFT) | \ + (ipbuf_dxt_send << TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT) | \ + (ipbuf_busy << TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT)) + +#define TCD_INPUT0_DEBUG_GET_empty(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_empty_MASK) >> TCD_INPUT0_DEBUG_empty_SHIFT) +#define TCD_INPUT0_DEBUG_GET_full(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_full_MASK) >> TCD_INPUT0_DEBUG_full_SHIFT) +#define TCD_INPUT0_DEBUG_GET_valid_q1(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_valid_q1_MASK) >> TCD_INPUT0_DEBUG_valid_q1_SHIFT) +#define TCD_INPUT0_DEBUG_GET_cnt_q1(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_cnt_q1_MASK) >> TCD_INPUT0_DEBUG_cnt_q1_SHIFT) +#define TCD_INPUT0_DEBUG_GET_last_send_q1(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_last_send_q1_MASK) >> TCD_INPUT0_DEBUG_last_send_q1_SHIFT) +#define TCD_INPUT0_DEBUG_GET_ip_send(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_ip_send_MASK) >> TCD_INPUT0_DEBUG_ip_send_SHIFT) +#define TCD_INPUT0_DEBUG_GET_ipbuf_dxt_send(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK) >> TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT) +#define TCD_INPUT0_DEBUG_GET_ipbuf_busy(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_ipbuf_busy_MASK) >> TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT) + +#define TCD_INPUT0_DEBUG_SET_empty(tcd_input0_debug_reg, empty) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_empty_MASK) | (empty << TCD_INPUT0_DEBUG_empty_SHIFT) +#define TCD_INPUT0_DEBUG_SET_full(tcd_input0_debug_reg, full) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_full_MASK) | (full << TCD_INPUT0_DEBUG_full_SHIFT) +#define TCD_INPUT0_DEBUG_SET_valid_q1(tcd_input0_debug_reg, valid_q1) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_valid_q1_MASK) | (valid_q1 << TCD_INPUT0_DEBUG_valid_q1_SHIFT) +#define TCD_INPUT0_DEBUG_SET_cnt_q1(tcd_input0_debug_reg, cnt_q1) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_cnt_q1_MASK) | (cnt_q1 << TCD_INPUT0_DEBUG_cnt_q1_SHIFT) +#define TCD_INPUT0_DEBUG_SET_last_send_q1(tcd_input0_debug_reg, last_send_q1) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_last_send_q1_MASK) | (last_send_q1 << TCD_INPUT0_DEBUG_last_send_q1_SHIFT) +#define TCD_INPUT0_DEBUG_SET_ip_send(tcd_input0_debug_reg, ip_send) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ip_send_MASK) | (ip_send << TCD_INPUT0_DEBUG_ip_send_SHIFT) +#define TCD_INPUT0_DEBUG_SET_ipbuf_dxt_send(tcd_input0_debug_reg, ipbuf_dxt_send) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK) | (ipbuf_dxt_send << TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT) +#define TCD_INPUT0_DEBUG_SET_ipbuf_busy(tcd_input0_debug_reg, ipbuf_busy) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ipbuf_busy_MASK) | (ipbuf_busy << TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_input0_debug_t { + unsigned int : 16; + unsigned int empty : TCD_INPUT0_DEBUG_empty_SIZE; + unsigned int full : TCD_INPUT0_DEBUG_full_SIZE; + unsigned int : 2; + unsigned int valid_q1 : TCD_INPUT0_DEBUG_valid_q1_SIZE; + unsigned int cnt_q1 : TCD_INPUT0_DEBUG_cnt_q1_SIZE; + unsigned int last_send_q1 : TCD_INPUT0_DEBUG_last_send_q1_SIZE; + unsigned int ip_send : TCD_INPUT0_DEBUG_ip_send_SIZE; + unsigned int ipbuf_dxt_send : TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE; + unsigned int ipbuf_busy : TCD_INPUT0_DEBUG_ipbuf_busy_SIZE; + unsigned int : 5; + } tcd_input0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_input0_debug_t { + unsigned int : 5; + unsigned int ipbuf_busy : TCD_INPUT0_DEBUG_ipbuf_busy_SIZE; + unsigned int ipbuf_dxt_send : TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE; + unsigned int ip_send : TCD_INPUT0_DEBUG_ip_send_SIZE; + unsigned int last_send_q1 : TCD_INPUT0_DEBUG_last_send_q1_SIZE; + unsigned int cnt_q1 : TCD_INPUT0_DEBUG_cnt_q1_SIZE; + unsigned int valid_q1 : TCD_INPUT0_DEBUG_valid_q1_SIZE; + unsigned int : 2; + unsigned int full : TCD_INPUT0_DEBUG_full_SIZE; + unsigned int empty : TCD_INPUT0_DEBUG_empty_SIZE; + unsigned int : 16; + } tcd_input0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_input0_debug_t f; +} tcd_input0_debug_u; + + +/* + * TCD_DEGAMMA_DEBUG struct + */ + +#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE 2 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE 1 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE 1 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE 1 +#define TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE 1 +#define TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE 1 + +#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT 0 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT 2 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT 3 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT 4 +#define TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT 5 +#define TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT 6 + +#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK 0x00000003 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK 0x00000004 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK 0x00000008 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK 0x00000010 +#define TCD_DEGAMMA_DEBUG_dgmm_stall_MASK 0x00000020 +#define TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK 0x00000040 + +#define TCD_DEGAMMA_DEBUG_MASK \ + (TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_stall_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) + +#define TCD_DEGAMMA_DEBUG(dgmm_ftfconv_dgmmen, dgmm_ctrl_dgmm8, dgmm_ctrl_last_send, dgmm_ctrl_send, dgmm_stall, dgmm_pstate) \ + ((dgmm_ftfconv_dgmmen << TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT) | \ + (dgmm_ctrl_dgmm8 << TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT) | \ + (dgmm_ctrl_last_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT) | \ + (dgmm_ctrl_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT) | \ + (dgmm_stall << TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT) | \ + (dgmm_pstate << TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT)) + +#define TCD_DEGAMMA_DEBUG_GET_dgmm_ftfconv_dgmmen(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_dgmm8(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_last_send(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_send(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_stall(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_stall_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_pstate(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT) + +#define TCD_DEGAMMA_DEBUG_SET_dgmm_ftfconv_dgmmen(tcd_degamma_debug_reg, dgmm_ftfconv_dgmmen) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK) | (dgmm_ftfconv_dgmmen << TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_dgmm8(tcd_degamma_debug_reg, dgmm_ctrl_dgmm8) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK) | (dgmm_ctrl_dgmm8 << TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_last_send(tcd_degamma_debug_reg, dgmm_ctrl_last_send) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK) | (dgmm_ctrl_last_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_send(tcd_degamma_debug_reg, dgmm_ctrl_send) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK) | (dgmm_ctrl_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_stall(tcd_degamma_debug_reg, dgmm_stall) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_stall_MASK) | (dgmm_stall << TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_pstate(tcd_degamma_debug_reg, dgmm_pstate) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) | (dgmm_pstate << TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_degamma_debug_t { + unsigned int dgmm_ftfconv_dgmmen : TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE; + unsigned int dgmm_ctrl_dgmm8 : TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE; + unsigned int dgmm_ctrl_last_send : TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE; + unsigned int dgmm_ctrl_send : TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE; + unsigned int dgmm_stall : TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE; + unsigned int dgmm_pstate : TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE; + unsigned int : 25; + } tcd_degamma_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_degamma_debug_t { + unsigned int : 25; + unsigned int dgmm_pstate : TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE; + unsigned int dgmm_stall : TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE; + unsigned int dgmm_ctrl_send : TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE; + unsigned int dgmm_ctrl_last_send : TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE; + unsigned int dgmm_ctrl_dgmm8 : TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE; + unsigned int dgmm_ftfconv_dgmmen : TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE; + } tcd_degamma_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_degamma_debug_t f; +} tcd_degamma_debug_u; + + +/* + * TCD_DXTMUX_SCTARB_DEBUG struct + */ + +#define TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE 1 + +#define TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT 9 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT 10 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT 11 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT 15 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT 16 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT 20 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT 27 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT 28 +#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT 29 + +#define TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK 0x00000200 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK 0x00000400 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK 0x00000800 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK 0x00008000 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK 0x00010000 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK 0x00100000 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK 0x08000000 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK 0x10000000 +#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK 0x20000000 + +#define TCD_DXTMUX_SCTARB_DEBUG_MASK \ + (TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) + +#define TCD_DXTMUX_SCTARB_DEBUG(pstate, sctrmx_rtr, dxtc_rtr, sctrarb_multcyl_send, sctrmx0_sctrarb_rts, dxtc_sctrarb_send, dxtc_dgmmpd_last_send, dxtc_dgmmpd_send, dcmp_mux_send) \ + ((pstate << TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT) | \ + (sctrmx_rtr << TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT) | \ + (dxtc_rtr << TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT) | \ + (sctrarb_multcyl_send << TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT) | \ + (sctrmx0_sctrarb_rts << TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT) | \ + (dxtc_sctrarb_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT) | \ + (dxtc_dgmmpd_last_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT) | \ + (dxtc_dgmmpd_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT) | \ + (dcmp_mux_send << TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT)) + +#define TCD_DXTMUX_SCTARB_DEBUG_GET_pstate(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrmx_rtr(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_rtr(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrarb_multcyl_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrmx0_sctrarb_rts(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_sctrarb_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_dgmmpd_last_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_dgmmpd_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dcmp_mux_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT) + +#define TCD_DXTMUX_SCTARB_DEBUG_SET_pstate(tcd_dxtmux_sctarb_debug_reg, pstate) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK) | (pstate << TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrmx_rtr(tcd_dxtmux_sctarb_debug_reg, sctrmx_rtr) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK) | (sctrmx_rtr << TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_rtr(tcd_dxtmux_sctarb_debug_reg, dxtc_rtr) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK) | (dxtc_rtr << TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrarb_multcyl_send(tcd_dxtmux_sctarb_debug_reg, sctrarb_multcyl_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK) | (sctrarb_multcyl_send << TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrmx0_sctrarb_rts(tcd_dxtmux_sctarb_debug_reg, sctrmx0_sctrarb_rts) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK) | (sctrmx0_sctrarb_rts << TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_sctrarb_send(tcd_dxtmux_sctarb_debug_reg, dxtc_sctrarb_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK) | (dxtc_sctrarb_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_dgmmpd_last_send(tcd_dxtmux_sctarb_debug_reg, dxtc_dgmmpd_last_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK) | (dxtc_dgmmpd_last_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_dgmmpd_send(tcd_dxtmux_sctarb_debug_reg, dxtc_dgmmpd_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK) | (dxtc_dgmmpd_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dcmp_mux_send(tcd_dxtmux_sctarb_debug_reg, dcmp_mux_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) | (dcmp_mux_send << TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_dxtmux_sctarb_debug_t { + unsigned int : 9; + unsigned int pstate : TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE; + unsigned int sctrmx_rtr : TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE; + unsigned int dxtc_rtr : TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE; + unsigned int : 3; + unsigned int sctrarb_multcyl_send : TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE; + unsigned int sctrmx0_sctrarb_rts : TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE; + unsigned int : 3; + unsigned int dxtc_sctrarb_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE; + unsigned int : 6; + unsigned int dxtc_dgmmpd_last_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE; + unsigned int dxtc_dgmmpd_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE; + unsigned int dcmp_mux_send : TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE; + unsigned int : 2; + } tcd_dxtmux_sctarb_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_dxtmux_sctarb_debug_t { + unsigned int : 2; + unsigned int dcmp_mux_send : TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE; + unsigned int dxtc_dgmmpd_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE; + unsigned int dxtc_dgmmpd_last_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE; + unsigned int : 6; + unsigned int dxtc_sctrarb_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE; + unsigned int : 3; + unsigned int sctrmx0_sctrarb_rts : TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE; + unsigned int sctrarb_multcyl_send : TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE; + unsigned int : 3; + unsigned int dxtc_rtr : TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE; + unsigned int sctrmx_rtr : TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE; + unsigned int pstate : TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE; + unsigned int : 9; + } tcd_dxtmux_sctarb_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_dxtmux_sctarb_debug_t f; +} tcd_dxtmux_sctarb_debug_u; + + +/* + * TCD_DXTC_ARB_DEBUG struct + */ + +#define TCD_DXTC_ARB_DEBUG_n0_stall_SIZE 1 +#define TCD_DXTC_ARB_DEBUG_pstate_SIZE 1 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE 1 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE 2 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE 3 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE 6 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE 12 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE 1 +#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE 1 + +#define TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT 4 +#define TCD_DXTC_ARB_DEBUG_pstate_SHIFT 5 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT 6 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT 7 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT 9 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT 12 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT 18 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT 30 +#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT 31 + +#define TCD_DXTC_ARB_DEBUG_n0_stall_MASK 0x00000010 +#define TCD_DXTC_ARB_DEBUG_pstate_MASK 0x00000020 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK 0x00000040 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK 0x00000180 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK 0x00000e00 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK 0x0003f000 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK 0x3ffc0000 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK 0x40000000 +#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK 0x80000000 + +#define TCD_DXTC_ARB_DEBUG_MASK \ + (TCD_DXTC_ARB_DEBUG_n0_stall_MASK | \ + TCD_DXTC_ARB_DEBUG_pstate_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK | \ + TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) + +#define TCD_DXTC_ARB_DEBUG(n0_stall, pstate, arb_dcmp01_last_send, arb_dcmp01_cnt, arb_dcmp01_sector, arb_dcmp01_cacheline, arb_dcmp01_format, arb_dcmp01_send, n0_dxt2_4_types) \ + ((n0_stall << TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT) | \ + (pstate << TCD_DXTC_ARB_DEBUG_pstate_SHIFT) | \ + (arb_dcmp01_last_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT) | \ + (arb_dcmp01_cnt << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT) | \ + (arb_dcmp01_sector << TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT) | \ + (arb_dcmp01_cacheline << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT) | \ + (arb_dcmp01_format << TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT) | \ + (arb_dcmp01_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT) | \ + (n0_dxt2_4_types << TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT)) + +#define TCD_DXTC_ARB_DEBUG_GET_n0_stall(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_n0_stall_MASK) >> TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_pstate(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_pstate_MASK) >> TCD_DXTC_ARB_DEBUG_pstate_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_last_send(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_cnt(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_sector(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_cacheline(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_format(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_send(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_n0_dxt2_4_types(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) >> TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT) + +#define TCD_DXTC_ARB_DEBUG_SET_n0_stall(tcd_dxtc_arb_debug_reg, n0_stall) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_n0_stall_MASK) | (n0_stall << TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_pstate(tcd_dxtc_arb_debug_reg, pstate) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_pstate_MASK) | (pstate << TCD_DXTC_ARB_DEBUG_pstate_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_last_send(tcd_dxtc_arb_debug_reg, arb_dcmp01_last_send) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK) | (arb_dcmp01_last_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_cnt(tcd_dxtc_arb_debug_reg, arb_dcmp01_cnt) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK) | (arb_dcmp01_cnt << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_sector(tcd_dxtc_arb_debug_reg, arb_dcmp01_sector) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK) | (arb_dcmp01_sector << TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_cacheline(tcd_dxtc_arb_debug_reg, arb_dcmp01_cacheline) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK) | (arb_dcmp01_cacheline << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_format(tcd_dxtc_arb_debug_reg, arb_dcmp01_format) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK) | (arb_dcmp01_format << TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_send(tcd_dxtc_arb_debug_reg, arb_dcmp01_send) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK) | (arb_dcmp01_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_n0_dxt2_4_types(tcd_dxtc_arb_debug_reg, n0_dxt2_4_types) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) | (n0_dxt2_4_types << TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_dxtc_arb_debug_t { + unsigned int : 4; + unsigned int n0_stall : TCD_DXTC_ARB_DEBUG_n0_stall_SIZE; + unsigned int pstate : TCD_DXTC_ARB_DEBUG_pstate_SIZE; + unsigned int arb_dcmp01_last_send : TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE; + unsigned int arb_dcmp01_cnt : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE; + unsigned int arb_dcmp01_sector : TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE; + unsigned int arb_dcmp01_cacheline : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE; + unsigned int arb_dcmp01_format : TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE; + unsigned int arb_dcmp01_send : TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE; + unsigned int n0_dxt2_4_types : TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE; + } tcd_dxtc_arb_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_dxtc_arb_debug_t { + unsigned int n0_dxt2_4_types : TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE; + unsigned int arb_dcmp01_send : TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE; + unsigned int arb_dcmp01_format : TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE; + unsigned int arb_dcmp01_cacheline : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE; + unsigned int arb_dcmp01_sector : TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE; + unsigned int arb_dcmp01_cnt : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE; + unsigned int arb_dcmp01_last_send : TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE; + unsigned int pstate : TCD_DXTC_ARB_DEBUG_pstate_SIZE; + unsigned int n0_stall : TCD_DXTC_ARB_DEBUG_n0_stall_SIZE; + unsigned int : 4; + } tcd_dxtc_arb_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_dxtc_arb_debug_t f; +} tcd_dxtc_arb_debug_u; + + +/* + * TCD_STALLS_DEBUG struct + */ + +#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_incoming_rtr_SIZE 1 + +#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT 10 +#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT 11 +#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT 17 +#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT 18 +#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT 19 +#define TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT 31 + +#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK 0x00000400 +#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK 0x00000800 +#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK 0x00020000 +#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK 0x00040000 +#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK 0x00080000 +#define TCD_STALLS_DEBUG_not_incoming_rtr_MASK 0x80000000 + +#define TCD_STALLS_DEBUG_MASK \ + (TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK | \ + TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK | \ + TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK | \ + TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK | \ + TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK | \ + TCD_STALLS_DEBUG_not_incoming_rtr_MASK) + +#define TCD_STALLS_DEBUG(not_multcyl_sctrarb_rtr, not_sctrmx0_sctrarb_rtr, not_dcmp0_arb_rtr, not_dgmmpd_dxtc_rtr, not_mux_dcmp_rtr, not_incoming_rtr) \ + ((not_multcyl_sctrarb_rtr << TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT) | \ + (not_sctrmx0_sctrarb_rtr << TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT) | \ + (not_dcmp0_arb_rtr << TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT) | \ + (not_dgmmpd_dxtc_rtr << TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT) | \ + (not_mux_dcmp_rtr << TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT) | \ + (not_incoming_rtr << TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT)) + +#define TCD_STALLS_DEBUG_GET_not_multcyl_sctrarb_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK) >> TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_sctrmx0_sctrarb_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK) >> TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_dcmp0_arb_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK) >> TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_dgmmpd_dxtc_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK) >> TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_mux_dcmp_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK) >> TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_incoming_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_incoming_rtr_MASK) >> TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT) + +#define TCD_STALLS_DEBUG_SET_not_multcyl_sctrarb_rtr(tcd_stalls_debug_reg, not_multcyl_sctrarb_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK) | (not_multcyl_sctrarb_rtr << TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_sctrmx0_sctrarb_rtr(tcd_stalls_debug_reg, not_sctrmx0_sctrarb_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK) | (not_sctrmx0_sctrarb_rtr << TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_dcmp0_arb_rtr(tcd_stalls_debug_reg, not_dcmp0_arb_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK) | (not_dcmp0_arb_rtr << TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_dgmmpd_dxtc_rtr(tcd_stalls_debug_reg, not_dgmmpd_dxtc_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK) | (not_dgmmpd_dxtc_rtr << TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_mux_dcmp_rtr(tcd_stalls_debug_reg, not_mux_dcmp_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK) | (not_mux_dcmp_rtr << TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_incoming_rtr(tcd_stalls_debug_reg, not_incoming_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_incoming_rtr_MASK) | (not_incoming_rtr << TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_stalls_debug_t { + unsigned int : 10; + unsigned int not_multcyl_sctrarb_rtr : TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE; + unsigned int not_sctrmx0_sctrarb_rtr : TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE; + unsigned int : 5; + unsigned int not_dcmp0_arb_rtr : TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE; + unsigned int not_dgmmpd_dxtc_rtr : TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE; + unsigned int not_mux_dcmp_rtr : TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE; + unsigned int : 11; + unsigned int not_incoming_rtr : TCD_STALLS_DEBUG_not_incoming_rtr_SIZE; + } tcd_stalls_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_stalls_debug_t { + unsigned int not_incoming_rtr : TCD_STALLS_DEBUG_not_incoming_rtr_SIZE; + unsigned int : 11; + unsigned int not_mux_dcmp_rtr : TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE; + unsigned int not_dgmmpd_dxtc_rtr : TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE; + unsigned int not_dcmp0_arb_rtr : TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE; + unsigned int : 5; + unsigned int not_sctrmx0_sctrarb_rtr : TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE; + unsigned int not_multcyl_sctrarb_rtr : TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE; + unsigned int : 10; + } tcd_stalls_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_stalls_debug_t f; +} tcd_stalls_debug_u; + + +/* + * TCO_STALLS_DEBUG struct + */ + +#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE 1 +#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE 1 +#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE 1 + +#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT 5 +#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT 6 +#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT 7 + +#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK 0x00000020 +#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK 0x00000040 +#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK 0x00000080 + +#define TCO_STALLS_DEBUG_MASK \ + (TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK | \ + TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK | \ + TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) + +#define TCO_STALLS_DEBUG(quad0_sg_crd_rtr, quad0_rl_sg_rtr, quad0_tco_tcb_rtr_d) \ + ((quad0_sg_crd_rtr << TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT) | \ + (quad0_rl_sg_rtr << TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT) | \ + (quad0_tco_tcb_rtr_d << TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT)) + +#define TCO_STALLS_DEBUG_GET_quad0_sg_crd_RTR(tco_stalls_debug) \ + ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK) >> TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT) +#define TCO_STALLS_DEBUG_GET_quad0_rl_sg_RTR(tco_stalls_debug) \ + ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK) >> TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT) +#define TCO_STALLS_DEBUG_GET_quad0_TCO_TCB_rtr_d(tco_stalls_debug) \ + ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) >> TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT) + +#define TCO_STALLS_DEBUG_SET_quad0_sg_crd_RTR(tco_stalls_debug_reg, quad0_sg_crd_rtr) \ + tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK) | (quad0_sg_crd_rtr << TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT) +#define TCO_STALLS_DEBUG_SET_quad0_rl_sg_RTR(tco_stalls_debug_reg, quad0_rl_sg_rtr) \ + tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK) | (quad0_rl_sg_rtr << TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT) +#define TCO_STALLS_DEBUG_SET_quad0_TCO_TCB_rtr_d(tco_stalls_debug_reg, quad0_tco_tcb_rtr_d) \ + tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) | (quad0_tco_tcb_rtr_d << TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tco_stalls_debug_t { + unsigned int : 5; + unsigned int quad0_sg_crd_rtr : TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE; + unsigned int quad0_rl_sg_rtr : TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE; + unsigned int quad0_tco_tcb_rtr_d : TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE; + unsigned int : 24; + } tco_stalls_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tco_stalls_debug_t { + unsigned int : 24; + unsigned int quad0_tco_tcb_rtr_d : TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE; + unsigned int quad0_rl_sg_rtr : TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE; + unsigned int quad0_sg_crd_rtr : TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE; + unsigned int : 5; + } tco_stalls_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tco_stalls_debug_t f; +} tco_stalls_debug_u; + + +/* + * TCO_QUAD0_DEBUG0 struct + */ + +#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE 8 +#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE 1 +#define TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE 1 +#define TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE 1 +#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE 1 +#define TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE 1 +#define TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE 1 +#define TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE 1 +#define TCO_QUAD0_DEBUG0_read_cache_q_SIZE 1 +#define TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE 1 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE 1 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE 1 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE 1 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE 1 +#define TCO_QUAD0_DEBUG0_busy_SIZE 1 + +#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT 0 +#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT 8 +#define TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT 9 +#define TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT 10 +#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT 11 +#define TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT 12 +#define TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT 13 +#define TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT 16 +#define TCO_QUAD0_DEBUG0_read_cache_q_SHIFT 24 +#define TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT 25 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT 26 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT 27 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT 28 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT 29 +#define TCO_QUAD0_DEBUG0_busy_SHIFT 30 + +#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK 0x000000ff +#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK 0x00000100 +#define TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK 0x00000200 +#define TCO_QUAD0_DEBUG0_rl_sg_rts_MASK 0x00000400 +#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK 0x00000800 +#define TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK 0x00001000 +#define TCO_QUAD0_DEBUG0_sg_crd_rts_MASK 0x00002000 +#define TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK 0x00010000 +#define TCO_QUAD0_DEBUG0_read_cache_q_MASK 0x01000000 +#define TCO_QUAD0_DEBUG0_cache_read_RTR_MASK 0x02000000 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK 0x04000000 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK 0x08000000 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK 0x10000000 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK 0x20000000 +#define TCO_QUAD0_DEBUG0_busy_MASK 0x40000000 + +#define TCO_QUAD0_DEBUG0_MASK \ + (TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK | \ + TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK | \ + TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK | \ + TCO_QUAD0_DEBUG0_rl_sg_rts_MASK | \ + TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK | \ + TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK | \ + TCO_QUAD0_DEBUG0_sg_crd_rts_MASK | \ + TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK | \ + TCO_QUAD0_DEBUG0_read_cache_q_MASK | \ + TCO_QUAD0_DEBUG0_cache_read_RTR_MASK | \ + TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK | \ + TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK | \ + TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK | \ + TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK | \ + TCO_QUAD0_DEBUG0_busy_MASK) + +#define TCO_QUAD0_DEBUG0(rl_sg_sector_format, rl_sg_end_of_sample, rl_sg_rtr, rl_sg_rts, sg_crd_end_of_sample, sg_crd_rtr, sg_crd_rts, stagen1_valid_q, read_cache_q, cache_read_rtr, all_sectors_written_set3, all_sectors_written_set2, all_sectors_written_set1, all_sectors_written_set0, busy) \ + ((rl_sg_sector_format << TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT) | \ + (rl_sg_end_of_sample << TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT) | \ + (rl_sg_rtr << TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT) | \ + (rl_sg_rts << TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT) | \ + (sg_crd_end_of_sample << TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT) | \ + (sg_crd_rtr << TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT) | \ + (sg_crd_rts << TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT) | \ + (stagen1_valid_q << TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT) | \ + (read_cache_q << TCO_QUAD0_DEBUG0_read_cache_q_SHIFT) | \ + (cache_read_rtr << TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT) | \ + (all_sectors_written_set3 << TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT) | \ + (all_sectors_written_set2 << TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT) | \ + (all_sectors_written_set1 << TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT) | \ + (all_sectors_written_set0 << TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT) | \ + (busy << TCO_QUAD0_DEBUG0_busy_SHIFT)) + +#define TCO_QUAD0_DEBUG0_GET_rl_sg_sector_format(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_rl_sg_end_of_sample(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_rl_sg_rtr(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_rl_sg_rts(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_rts_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_sg_crd_end_of_sample(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_sg_crd_rtr(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_sg_crd_rts(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_rts_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_stageN1_valid_q(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK) >> TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_read_cache_q(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_read_cache_q_MASK) >> TCO_QUAD0_DEBUG0_read_cache_q_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_cache_read_RTR(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_cache_read_RTR_MASK) >> TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set3(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set2(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set1(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set0(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_busy(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_busy_MASK) >> TCO_QUAD0_DEBUG0_busy_SHIFT) + +#define TCO_QUAD0_DEBUG0_SET_rl_sg_sector_format(tco_quad0_debug0_reg, rl_sg_sector_format) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK) | (rl_sg_sector_format << TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_rl_sg_end_of_sample(tco_quad0_debug0_reg, rl_sg_end_of_sample) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK) | (rl_sg_end_of_sample << TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_rl_sg_rtr(tco_quad0_debug0_reg, rl_sg_rtr) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK) | (rl_sg_rtr << TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_rl_sg_rts(tco_quad0_debug0_reg, rl_sg_rts) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_rts_MASK) | (rl_sg_rts << TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_sg_crd_end_of_sample(tco_quad0_debug0_reg, sg_crd_end_of_sample) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK) | (sg_crd_end_of_sample << TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_sg_crd_rtr(tco_quad0_debug0_reg, sg_crd_rtr) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK) | (sg_crd_rtr << TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_sg_crd_rts(tco_quad0_debug0_reg, sg_crd_rts) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_rts_MASK) | (sg_crd_rts << TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_stageN1_valid_q(tco_quad0_debug0_reg, stagen1_valid_q) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK) | (stagen1_valid_q << TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_read_cache_q(tco_quad0_debug0_reg, read_cache_q) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_read_cache_q_MASK) | (read_cache_q << TCO_QUAD0_DEBUG0_read_cache_q_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_cache_read_RTR(tco_quad0_debug0_reg, cache_read_rtr) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_cache_read_RTR_MASK) | (cache_read_rtr << TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set3(tco_quad0_debug0_reg, all_sectors_written_set3) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK) | (all_sectors_written_set3 << TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set2(tco_quad0_debug0_reg, all_sectors_written_set2) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK) | (all_sectors_written_set2 << TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set1(tco_quad0_debug0_reg, all_sectors_written_set1) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK) | (all_sectors_written_set1 << TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set0(tco_quad0_debug0_reg, all_sectors_written_set0) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK) | (all_sectors_written_set0 << TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_busy(tco_quad0_debug0_reg, busy) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_busy_MASK) | (busy << TCO_QUAD0_DEBUG0_busy_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tco_quad0_debug0_t { + unsigned int rl_sg_sector_format : TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE; + unsigned int rl_sg_end_of_sample : TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE; + unsigned int rl_sg_rtr : TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE; + unsigned int rl_sg_rts : TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE; + unsigned int sg_crd_end_of_sample : TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE; + unsigned int sg_crd_rtr : TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE; + unsigned int sg_crd_rts : TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE; + unsigned int : 2; + unsigned int stagen1_valid_q : TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE; + unsigned int : 7; + unsigned int read_cache_q : TCO_QUAD0_DEBUG0_read_cache_q_SIZE; + unsigned int cache_read_rtr : TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE; + unsigned int all_sectors_written_set3 : TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE; + unsigned int all_sectors_written_set2 : TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE; + unsigned int all_sectors_written_set1 : TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE; + unsigned int all_sectors_written_set0 : TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE; + unsigned int busy : TCO_QUAD0_DEBUG0_busy_SIZE; + unsigned int : 1; + } tco_quad0_debug0_t; + +#else // !BIGENDIAN_OS + + typedef struct _tco_quad0_debug0_t { + unsigned int : 1; + unsigned int busy : TCO_QUAD0_DEBUG0_busy_SIZE; + unsigned int all_sectors_written_set0 : TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE; + unsigned int all_sectors_written_set1 : TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE; + unsigned int all_sectors_written_set2 : TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE; + unsigned int all_sectors_written_set3 : TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE; + unsigned int cache_read_rtr : TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE; + unsigned int read_cache_q : TCO_QUAD0_DEBUG0_read_cache_q_SIZE; + unsigned int : 7; + unsigned int stagen1_valid_q : TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE; + unsigned int : 2; + unsigned int sg_crd_rts : TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE; + unsigned int sg_crd_rtr : TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE; + unsigned int sg_crd_end_of_sample : TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE; + unsigned int rl_sg_rts : TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE; + unsigned int rl_sg_rtr : TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE; + unsigned int rl_sg_end_of_sample : TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE; + unsigned int rl_sg_sector_format : TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE; + } tco_quad0_debug0_t; + +#endif + +typedef union { + unsigned int val : 32; + tco_quad0_debug0_t f; +} tco_quad0_debug0_u; + + +/* + * TCO_QUAD0_DEBUG1 struct + */ + +#define TCO_QUAD0_DEBUG1_fifo_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_empty_SIZE 1 +#define TCO_QUAD0_DEBUG1_full_SIZE 1 +#define TCO_QUAD0_DEBUG1_write_enable_SIZE 1 +#define TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE 7 +#define TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE 7 +#define TCO_QUAD0_DEBUG1_cache_read_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_input_quad_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE 1 +#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE 1 +#define TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE 1 +#define TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE 1 +#define TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE 1 +#define TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE 1 +#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE 1 + +#define TCO_QUAD0_DEBUG1_fifo_busy_SHIFT 0 +#define TCO_QUAD0_DEBUG1_empty_SHIFT 1 +#define TCO_QUAD0_DEBUG1_full_SHIFT 2 +#define TCO_QUAD0_DEBUG1_write_enable_SHIFT 3 +#define TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT 4 +#define TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT 11 +#define TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT 20 +#define TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT 21 +#define TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT 22 +#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT 23 +#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT 24 +#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT 25 +#define TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT 26 +#define TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT 27 +#define TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT 28 +#define TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT 29 +#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT 30 + +#define TCO_QUAD0_DEBUG1_fifo_busy_MASK 0x00000001 +#define TCO_QUAD0_DEBUG1_empty_MASK 0x00000002 +#define TCO_QUAD0_DEBUG1_full_MASK 0x00000004 +#define TCO_QUAD0_DEBUG1_write_enable_MASK 0x00000008 +#define TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK 0x000007f0 +#define TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK 0x0003f800 +#define TCO_QUAD0_DEBUG1_cache_read_busy_MASK 0x00100000 +#define TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK 0x00200000 +#define TCO_QUAD0_DEBUG1_input_quad_busy_MASK 0x00400000 +#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK 0x00800000 +#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK 0x01000000 +#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK 0x02000000 +#define TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK 0x04000000 +#define TCO_QUAD0_DEBUG1_rl_sg_rts_MASK 0x08000000 +#define TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK 0x10000000 +#define TCO_QUAD0_DEBUG1_sg_crd_rts_MASK 0x20000000 +#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK 0x40000000 + +#define TCO_QUAD0_DEBUG1_MASK \ + (TCO_QUAD0_DEBUG1_fifo_busy_MASK | \ + TCO_QUAD0_DEBUG1_empty_MASK | \ + TCO_QUAD0_DEBUG1_full_MASK | \ + TCO_QUAD0_DEBUG1_write_enable_MASK | \ + TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK | \ + TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK | \ + TCO_QUAD0_DEBUG1_cache_read_busy_MASK | \ + TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK | \ + TCO_QUAD0_DEBUG1_input_quad_busy_MASK | \ + TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK | \ + TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK | \ + TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK | \ + TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK | \ + TCO_QUAD0_DEBUG1_rl_sg_rts_MASK | \ + TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK | \ + TCO_QUAD0_DEBUG1_sg_crd_rts_MASK | \ + TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) + +#define TCO_QUAD0_DEBUG1(fifo_busy, empty, full, write_enable, fifo_write_ptr, fifo_read_ptr, cache_read_busy, latency_fifo_busy, input_quad_busy, tco_quad_pipe_busy, tcb_tco_rtr_d, tcb_tco_xfc_q, rl_sg_rtr, rl_sg_rts, sg_crd_rtr, sg_crd_rts, tco_tcb_read_xfc) \ + ((fifo_busy << TCO_QUAD0_DEBUG1_fifo_busy_SHIFT) | \ + (empty << TCO_QUAD0_DEBUG1_empty_SHIFT) | \ + (full << TCO_QUAD0_DEBUG1_full_SHIFT) | \ + (write_enable << TCO_QUAD0_DEBUG1_write_enable_SHIFT) | \ + (fifo_write_ptr << TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT) | \ + (fifo_read_ptr << TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT) | \ + (cache_read_busy << TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT) | \ + (latency_fifo_busy << TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT) | \ + (input_quad_busy << TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT) | \ + (tco_quad_pipe_busy << TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT) | \ + (tcb_tco_rtr_d << TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT) | \ + (tcb_tco_xfc_q << TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT) | \ + (rl_sg_rtr << TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT) | \ + (rl_sg_rts << TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT) | \ + (sg_crd_rtr << TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT) | \ + (sg_crd_rts << TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT) | \ + (tco_tcb_read_xfc << TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT)) + +#define TCO_QUAD0_DEBUG1_GET_fifo_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_busy_MASK) >> TCO_QUAD0_DEBUG1_fifo_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_empty(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_empty_MASK) >> TCO_QUAD0_DEBUG1_empty_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_full(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_full_MASK) >> TCO_QUAD0_DEBUG1_full_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_write_enable(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_write_enable_MASK) >> TCO_QUAD0_DEBUG1_write_enable_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_fifo_write_ptr(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK) >> TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_fifo_read_ptr(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK) >> TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_cache_read_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_cache_read_busy_MASK) >> TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_latency_fifo_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK) >> TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_input_quad_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_input_quad_busy_MASK) >> TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_tco_quad_pipe_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK) >> TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_TCB_TCO_rtr_d(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK) >> TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_TCB_TCO_xfc_q(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK) >> TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_rl_sg_rtr(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK) >> TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_rl_sg_rts(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_rl_sg_rts_MASK) >> TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_sg_crd_rtr(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK) >> TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_sg_crd_rts(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_sg_crd_rts_MASK) >> TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_TCO_TCB_read_xfc(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) >> TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT) + +#define TCO_QUAD0_DEBUG1_SET_fifo_busy(tco_quad0_debug1_reg, fifo_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_busy_MASK) | (fifo_busy << TCO_QUAD0_DEBUG1_fifo_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_empty(tco_quad0_debug1_reg, empty) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_empty_MASK) | (empty << TCO_QUAD0_DEBUG1_empty_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_full(tco_quad0_debug1_reg, full) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_full_MASK) | (full << TCO_QUAD0_DEBUG1_full_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_write_enable(tco_quad0_debug1_reg, write_enable) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_write_enable_MASK) | (write_enable << TCO_QUAD0_DEBUG1_write_enable_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_fifo_write_ptr(tco_quad0_debug1_reg, fifo_write_ptr) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK) | (fifo_write_ptr << TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_fifo_read_ptr(tco_quad0_debug1_reg, fifo_read_ptr) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK) | (fifo_read_ptr << TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_cache_read_busy(tco_quad0_debug1_reg, cache_read_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_cache_read_busy_MASK) | (cache_read_busy << TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_latency_fifo_busy(tco_quad0_debug1_reg, latency_fifo_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK) | (latency_fifo_busy << TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_input_quad_busy(tco_quad0_debug1_reg, input_quad_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_input_quad_busy_MASK) | (input_quad_busy << TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_tco_quad_pipe_busy(tco_quad0_debug1_reg, tco_quad_pipe_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK) | (tco_quad_pipe_busy << TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_TCB_TCO_rtr_d(tco_quad0_debug1_reg, tcb_tco_rtr_d) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK) | (tcb_tco_rtr_d << TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_TCB_TCO_xfc_q(tco_quad0_debug1_reg, tcb_tco_xfc_q) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK) | (tcb_tco_xfc_q << TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_rl_sg_rtr(tco_quad0_debug1_reg, rl_sg_rtr) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK) | (rl_sg_rtr << TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_rl_sg_rts(tco_quad0_debug1_reg, rl_sg_rts) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_rl_sg_rts_MASK) | (rl_sg_rts << TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_sg_crd_rtr(tco_quad0_debug1_reg, sg_crd_rtr) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK) | (sg_crd_rtr << TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_sg_crd_rts(tco_quad0_debug1_reg, sg_crd_rts) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_sg_crd_rts_MASK) | (sg_crd_rts << TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_TCO_TCB_read_xfc(tco_quad0_debug1_reg, tco_tcb_read_xfc) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) | (tco_tcb_read_xfc << TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tco_quad0_debug1_t { + unsigned int fifo_busy : TCO_QUAD0_DEBUG1_fifo_busy_SIZE; + unsigned int empty : TCO_QUAD0_DEBUG1_empty_SIZE; + unsigned int full : TCO_QUAD0_DEBUG1_full_SIZE; + unsigned int write_enable : TCO_QUAD0_DEBUG1_write_enable_SIZE; + unsigned int fifo_write_ptr : TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE; + unsigned int fifo_read_ptr : TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE; + unsigned int : 2; + unsigned int cache_read_busy : TCO_QUAD0_DEBUG1_cache_read_busy_SIZE; + unsigned int latency_fifo_busy : TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE; + unsigned int input_quad_busy : TCO_QUAD0_DEBUG1_input_quad_busy_SIZE; + unsigned int tco_quad_pipe_busy : TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE; + unsigned int tcb_tco_rtr_d : TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE; + unsigned int tcb_tco_xfc_q : TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE; + unsigned int rl_sg_rtr : TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE; + unsigned int rl_sg_rts : TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE; + unsigned int sg_crd_rtr : TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE; + unsigned int sg_crd_rts : TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE; + unsigned int tco_tcb_read_xfc : TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE; + unsigned int : 1; + } tco_quad0_debug1_t; + +#else // !BIGENDIAN_OS + + typedef struct _tco_quad0_debug1_t { + unsigned int : 1; + unsigned int tco_tcb_read_xfc : TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE; + unsigned int sg_crd_rts : TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE; + unsigned int sg_crd_rtr : TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE; + unsigned int rl_sg_rts : TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE; + unsigned int rl_sg_rtr : TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE; + unsigned int tcb_tco_xfc_q : TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE; + unsigned int tcb_tco_rtr_d : TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE; + unsigned int tco_quad_pipe_busy : TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE; + unsigned int input_quad_busy : TCO_QUAD0_DEBUG1_input_quad_busy_SIZE; + unsigned int latency_fifo_busy : TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE; + unsigned int cache_read_busy : TCO_QUAD0_DEBUG1_cache_read_busy_SIZE; + unsigned int : 2; + unsigned int fifo_read_ptr : TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE; + unsigned int fifo_write_ptr : TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE; + unsigned int write_enable : TCO_QUAD0_DEBUG1_write_enable_SIZE; + unsigned int full : TCO_QUAD0_DEBUG1_full_SIZE; + unsigned int empty : TCO_QUAD0_DEBUG1_empty_SIZE; + unsigned int fifo_busy : TCO_QUAD0_DEBUG1_fifo_busy_SIZE; + } tco_quad0_debug1_t; + +#endif + +typedef union { + unsigned int val : 32; + tco_quad0_debug1_t f; +} tco_quad0_debug1_u; + + +#endif + + +#if !defined (_TC_FIDDLE_H) +#define _TC_FIDDLE_H + +/***************************************************************************************************************** + * + * tc_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +#endif + + +#if !defined (_SC_FIDDLE_H) +#define _SC_FIDDLE_H + +/***************************************************************************************************************** + * + * sc_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +#endif + + +#if !defined (_BC_FIDDLE_H) +#define _BC_FIDDLE_H + +/***************************************************************************************************************** + * + * bc_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * RB_SURFACE_INFO struct + */ + +#define RB_SURFACE_INFO_SURFACE_PITCH_SIZE 14 +#define RB_SURFACE_INFO_MSAA_SAMPLES_SIZE 2 + +#define RB_SURFACE_INFO_SURFACE_PITCH_SHIFT 0 +#define RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT 14 + +#define RB_SURFACE_INFO_SURFACE_PITCH_MASK 0x00003fff +#define RB_SURFACE_INFO_MSAA_SAMPLES_MASK 0x0000c000 + +#define RB_SURFACE_INFO_MASK \ + (RB_SURFACE_INFO_SURFACE_PITCH_MASK | \ + RB_SURFACE_INFO_MSAA_SAMPLES_MASK) + +#define RB_SURFACE_INFO(surface_pitch, msaa_samples) \ + ((surface_pitch << RB_SURFACE_INFO_SURFACE_PITCH_SHIFT) | \ + (msaa_samples << RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT)) + +#define RB_SURFACE_INFO_GET_SURFACE_PITCH(rb_surface_info) \ + ((rb_surface_info & RB_SURFACE_INFO_SURFACE_PITCH_MASK) >> RB_SURFACE_INFO_SURFACE_PITCH_SHIFT) +#define RB_SURFACE_INFO_GET_MSAA_SAMPLES(rb_surface_info) \ + ((rb_surface_info & RB_SURFACE_INFO_MSAA_SAMPLES_MASK) >> RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT) + +#define RB_SURFACE_INFO_SET_SURFACE_PITCH(rb_surface_info_reg, surface_pitch) \ + rb_surface_info_reg = (rb_surface_info_reg & ~RB_SURFACE_INFO_SURFACE_PITCH_MASK) | (surface_pitch << RB_SURFACE_INFO_SURFACE_PITCH_SHIFT) +#define RB_SURFACE_INFO_SET_MSAA_SAMPLES(rb_surface_info_reg, msaa_samples) \ + rb_surface_info_reg = (rb_surface_info_reg & ~RB_SURFACE_INFO_MSAA_SAMPLES_MASK) | (msaa_samples << RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_surface_info_t { + unsigned int surface_pitch : RB_SURFACE_INFO_SURFACE_PITCH_SIZE; + unsigned int msaa_samples : RB_SURFACE_INFO_MSAA_SAMPLES_SIZE; + unsigned int : 16; + } rb_surface_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_surface_info_t { + unsigned int : 16; + unsigned int msaa_samples : RB_SURFACE_INFO_MSAA_SAMPLES_SIZE; + unsigned int surface_pitch : RB_SURFACE_INFO_SURFACE_PITCH_SIZE; + } rb_surface_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_surface_info_t f; +} rb_surface_info_u; + + +/* + * RB_COLOR_INFO struct + */ + +#define RB_COLOR_INFO_COLOR_FORMAT_SIZE 4 +#define RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE 2 +#define RB_COLOR_INFO_COLOR_LINEAR_SIZE 1 +#define RB_COLOR_INFO_COLOR_ENDIAN_SIZE 2 +#define RB_COLOR_INFO_COLOR_SWAP_SIZE 2 +#define RB_COLOR_INFO_COLOR_BASE_SIZE 20 + +#define RB_COLOR_INFO_COLOR_FORMAT_SHIFT 0 +#define RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT 4 +#define RB_COLOR_INFO_COLOR_LINEAR_SHIFT 6 +#define RB_COLOR_INFO_COLOR_ENDIAN_SHIFT 7 +#define RB_COLOR_INFO_COLOR_SWAP_SHIFT 9 +#define RB_COLOR_INFO_COLOR_BASE_SHIFT 12 + +#define RB_COLOR_INFO_COLOR_FORMAT_MASK 0x0000000f +#define RB_COLOR_INFO_COLOR_ROUND_MODE_MASK 0x00000030 +#define RB_COLOR_INFO_COLOR_LINEAR_MASK 0x00000040 +#define RB_COLOR_INFO_COLOR_ENDIAN_MASK 0x00000180 +#define RB_COLOR_INFO_COLOR_SWAP_MASK 0x00000600 +#define RB_COLOR_INFO_COLOR_BASE_MASK 0xfffff000 + +#define RB_COLOR_INFO_MASK \ + (RB_COLOR_INFO_COLOR_FORMAT_MASK | \ + RB_COLOR_INFO_COLOR_ROUND_MODE_MASK | \ + RB_COLOR_INFO_COLOR_LINEAR_MASK | \ + RB_COLOR_INFO_COLOR_ENDIAN_MASK | \ + RB_COLOR_INFO_COLOR_SWAP_MASK | \ + RB_COLOR_INFO_COLOR_BASE_MASK) + +#define RB_COLOR_INFO(color_format, color_round_mode, color_linear, color_endian, color_swap, color_base) \ + ((color_format << RB_COLOR_INFO_COLOR_FORMAT_SHIFT) | \ + (color_round_mode << RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT) | \ + (color_linear << RB_COLOR_INFO_COLOR_LINEAR_SHIFT) | \ + (color_endian << RB_COLOR_INFO_COLOR_ENDIAN_SHIFT) | \ + (color_swap << RB_COLOR_INFO_COLOR_SWAP_SHIFT) | \ + (color_base << RB_COLOR_INFO_COLOR_BASE_SHIFT)) + +#define RB_COLOR_INFO_GET_COLOR_FORMAT(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_FORMAT_MASK) >> RB_COLOR_INFO_COLOR_FORMAT_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_ROUND_MODE(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_ROUND_MODE_MASK) >> RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_LINEAR(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_LINEAR_MASK) >> RB_COLOR_INFO_COLOR_LINEAR_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_ENDIAN(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_ENDIAN_MASK) >> RB_COLOR_INFO_COLOR_ENDIAN_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_SWAP(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_SWAP_MASK) >> RB_COLOR_INFO_COLOR_SWAP_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_BASE(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_BASE_MASK) >> RB_COLOR_INFO_COLOR_BASE_SHIFT) + +#define RB_COLOR_INFO_SET_COLOR_FORMAT(rb_color_info_reg, color_format) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_FORMAT_MASK) | (color_format << RB_COLOR_INFO_COLOR_FORMAT_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_ROUND_MODE(rb_color_info_reg, color_round_mode) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_ROUND_MODE_MASK) | (color_round_mode << RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_LINEAR(rb_color_info_reg, color_linear) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_LINEAR_MASK) | (color_linear << RB_COLOR_INFO_COLOR_LINEAR_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_ENDIAN(rb_color_info_reg, color_endian) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_ENDIAN_MASK) | (color_endian << RB_COLOR_INFO_COLOR_ENDIAN_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_SWAP(rb_color_info_reg, color_swap) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_SWAP_MASK) | (color_swap << RB_COLOR_INFO_COLOR_SWAP_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_BASE(rb_color_info_reg, color_base) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_BASE_MASK) | (color_base << RB_COLOR_INFO_COLOR_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_color_info_t { + unsigned int color_format : RB_COLOR_INFO_COLOR_FORMAT_SIZE; + unsigned int color_round_mode : RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE; + unsigned int color_linear : RB_COLOR_INFO_COLOR_LINEAR_SIZE; + unsigned int color_endian : RB_COLOR_INFO_COLOR_ENDIAN_SIZE; + unsigned int color_swap : RB_COLOR_INFO_COLOR_SWAP_SIZE; + unsigned int : 1; + unsigned int color_base : RB_COLOR_INFO_COLOR_BASE_SIZE; + } rb_color_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_color_info_t { + unsigned int color_base : RB_COLOR_INFO_COLOR_BASE_SIZE; + unsigned int : 1; + unsigned int color_swap : RB_COLOR_INFO_COLOR_SWAP_SIZE; + unsigned int color_endian : RB_COLOR_INFO_COLOR_ENDIAN_SIZE; + unsigned int color_linear : RB_COLOR_INFO_COLOR_LINEAR_SIZE; + unsigned int color_round_mode : RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE; + unsigned int color_format : RB_COLOR_INFO_COLOR_FORMAT_SIZE; + } rb_color_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_color_info_t f; +} rb_color_info_u; + + +/* + * RB_DEPTH_INFO struct + */ + +#define RB_DEPTH_INFO_DEPTH_FORMAT_SIZE 1 +#define RB_DEPTH_INFO_DEPTH_BASE_SIZE 20 + +#define RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT 0 +#define RB_DEPTH_INFO_DEPTH_BASE_SHIFT 12 + +#define RB_DEPTH_INFO_DEPTH_FORMAT_MASK 0x00000001 +#define RB_DEPTH_INFO_DEPTH_BASE_MASK 0xfffff000 + +#define RB_DEPTH_INFO_MASK \ + (RB_DEPTH_INFO_DEPTH_FORMAT_MASK | \ + RB_DEPTH_INFO_DEPTH_BASE_MASK) + +#define RB_DEPTH_INFO(depth_format, depth_base) \ + ((depth_format << RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT) | \ + (depth_base << RB_DEPTH_INFO_DEPTH_BASE_SHIFT)) + +#define RB_DEPTH_INFO_GET_DEPTH_FORMAT(rb_depth_info) \ + ((rb_depth_info & RB_DEPTH_INFO_DEPTH_FORMAT_MASK) >> RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT) +#define RB_DEPTH_INFO_GET_DEPTH_BASE(rb_depth_info) \ + ((rb_depth_info & RB_DEPTH_INFO_DEPTH_BASE_MASK) >> RB_DEPTH_INFO_DEPTH_BASE_SHIFT) + +#define RB_DEPTH_INFO_SET_DEPTH_FORMAT(rb_depth_info_reg, depth_format) \ + rb_depth_info_reg = (rb_depth_info_reg & ~RB_DEPTH_INFO_DEPTH_FORMAT_MASK) | (depth_format << RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT) +#define RB_DEPTH_INFO_SET_DEPTH_BASE(rb_depth_info_reg, depth_base) \ + rb_depth_info_reg = (rb_depth_info_reg & ~RB_DEPTH_INFO_DEPTH_BASE_MASK) | (depth_base << RB_DEPTH_INFO_DEPTH_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_depth_info_t { + unsigned int depth_format : RB_DEPTH_INFO_DEPTH_FORMAT_SIZE; + unsigned int : 11; + unsigned int depth_base : RB_DEPTH_INFO_DEPTH_BASE_SIZE; + } rb_depth_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_depth_info_t { + unsigned int depth_base : RB_DEPTH_INFO_DEPTH_BASE_SIZE; + unsigned int : 11; + unsigned int depth_format : RB_DEPTH_INFO_DEPTH_FORMAT_SIZE; + } rb_depth_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_depth_info_t f; +} rb_depth_info_u; + + +/* + * RB_STENCILREFMASK struct + */ + +#define RB_STENCILREFMASK_STENCILREF_SIZE 8 +#define RB_STENCILREFMASK_STENCILMASK_SIZE 8 +#define RB_STENCILREFMASK_STENCILWRITEMASK_SIZE 8 +#define RB_STENCILREFMASK_RESERVED0_SIZE 1 +#define RB_STENCILREFMASK_RESERVED1_SIZE 1 + +#define RB_STENCILREFMASK_STENCILREF_SHIFT 0 +#define RB_STENCILREFMASK_STENCILMASK_SHIFT 8 +#define RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT 16 +#define RB_STENCILREFMASK_RESERVED0_SHIFT 24 +#define RB_STENCILREFMASK_RESERVED1_SHIFT 25 + +#define RB_STENCILREFMASK_STENCILREF_MASK 0x000000ff +#define RB_STENCILREFMASK_STENCILMASK_MASK 0x0000ff00 +#define RB_STENCILREFMASK_STENCILWRITEMASK_MASK 0x00ff0000 +#define RB_STENCILREFMASK_RESERVED0_MASK 0x01000000 +#define RB_STENCILREFMASK_RESERVED1_MASK 0x02000000 + +#define RB_STENCILREFMASK_MASK \ + (RB_STENCILREFMASK_STENCILREF_MASK | \ + RB_STENCILREFMASK_STENCILMASK_MASK | \ + RB_STENCILREFMASK_STENCILWRITEMASK_MASK | \ + RB_STENCILREFMASK_RESERVED0_MASK | \ + RB_STENCILREFMASK_RESERVED1_MASK) + +#define RB_STENCILREFMASK(stencilref, stencilmask, stencilwritemask, reserved0, reserved1) \ + ((stencilref << RB_STENCILREFMASK_STENCILREF_SHIFT) | \ + (stencilmask << RB_STENCILREFMASK_STENCILMASK_SHIFT) | \ + (stencilwritemask << RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT) | \ + (reserved0 << RB_STENCILREFMASK_RESERVED0_SHIFT) | \ + (reserved1 << RB_STENCILREFMASK_RESERVED1_SHIFT)) + +#define RB_STENCILREFMASK_GET_STENCILREF(rb_stencilrefmask) \ + ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILREF_MASK) >> RB_STENCILREFMASK_STENCILREF_SHIFT) +#define RB_STENCILREFMASK_GET_STENCILMASK(rb_stencilrefmask) \ + ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILMASK_MASK) >> RB_STENCILREFMASK_STENCILMASK_SHIFT) +#define RB_STENCILREFMASK_GET_STENCILWRITEMASK(rb_stencilrefmask) \ + ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILWRITEMASK_MASK) >> RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT) +#define RB_STENCILREFMASK_GET_RESERVED0(rb_stencilrefmask) \ + ((rb_stencilrefmask & RB_STENCILREFMASK_RESERVED0_MASK) >> RB_STENCILREFMASK_RESERVED0_SHIFT) +#define RB_STENCILREFMASK_GET_RESERVED1(rb_stencilrefmask) \ + ((rb_stencilrefmask & RB_STENCILREFMASK_RESERVED1_MASK) >> RB_STENCILREFMASK_RESERVED1_SHIFT) + +#define RB_STENCILREFMASK_SET_STENCILREF(rb_stencilrefmask_reg, stencilref) \ + rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILREF_MASK) | (stencilref << RB_STENCILREFMASK_STENCILREF_SHIFT) +#define RB_STENCILREFMASK_SET_STENCILMASK(rb_stencilrefmask_reg, stencilmask) \ + rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILMASK_MASK) | (stencilmask << RB_STENCILREFMASK_STENCILMASK_SHIFT) +#define RB_STENCILREFMASK_SET_STENCILWRITEMASK(rb_stencilrefmask_reg, stencilwritemask) \ + rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILWRITEMASK_MASK) | (stencilwritemask << RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT) +#define RB_STENCILREFMASK_SET_RESERVED0(rb_stencilrefmask_reg, reserved0) \ + rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_RESERVED0_MASK) | (reserved0 << RB_STENCILREFMASK_RESERVED0_SHIFT) +#define RB_STENCILREFMASK_SET_RESERVED1(rb_stencilrefmask_reg, reserved1) \ + rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_RESERVED1_MASK) | (reserved1 << RB_STENCILREFMASK_RESERVED1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_stencilrefmask_t { + unsigned int stencilref : RB_STENCILREFMASK_STENCILREF_SIZE; + unsigned int stencilmask : RB_STENCILREFMASK_STENCILMASK_SIZE; + unsigned int stencilwritemask : RB_STENCILREFMASK_STENCILWRITEMASK_SIZE; + unsigned int reserved0 : RB_STENCILREFMASK_RESERVED0_SIZE; + unsigned int reserved1 : RB_STENCILREFMASK_RESERVED1_SIZE; + unsigned int : 6; + } rb_stencilrefmask_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_stencilrefmask_t { + unsigned int : 6; + unsigned int reserved1 : RB_STENCILREFMASK_RESERVED1_SIZE; + unsigned int reserved0 : RB_STENCILREFMASK_RESERVED0_SIZE; + unsigned int stencilwritemask : RB_STENCILREFMASK_STENCILWRITEMASK_SIZE; + unsigned int stencilmask : RB_STENCILREFMASK_STENCILMASK_SIZE; + unsigned int stencilref : RB_STENCILREFMASK_STENCILREF_SIZE; + } rb_stencilrefmask_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_stencilrefmask_t f; +} rb_stencilrefmask_u; + + +/* + * RB_ALPHA_REF struct + */ + +#define RB_ALPHA_REF_ALPHA_REF_SIZE 32 + +#define RB_ALPHA_REF_ALPHA_REF_SHIFT 0 + +#define RB_ALPHA_REF_ALPHA_REF_MASK 0xffffffff + +#define RB_ALPHA_REF_MASK \ + (RB_ALPHA_REF_ALPHA_REF_MASK) + +#define RB_ALPHA_REF(alpha_ref) \ + ((alpha_ref << RB_ALPHA_REF_ALPHA_REF_SHIFT)) + +#define RB_ALPHA_REF_GET_ALPHA_REF(rb_alpha_ref) \ + ((rb_alpha_ref & RB_ALPHA_REF_ALPHA_REF_MASK) >> RB_ALPHA_REF_ALPHA_REF_SHIFT) + +#define RB_ALPHA_REF_SET_ALPHA_REF(rb_alpha_ref_reg, alpha_ref) \ + rb_alpha_ref_reg = (rb_alpha_ref_reg & ~RB_ALPHA_REF_ALPHA_REF_MASK) | (alpha_ref << RB_ALPHA_REF_ALPHA_REF_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_alpha_ref_t { + unsigned int alpha_ref : RB_ALPHA_REF_ALPHA_REF_SIZE; + } rb_alpha_ref_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_alpha_ref_t { + unsigned int alpha_ref : RB_ALPHA_REF_ALPHA_REF_SIZE; + } rb_alpha_ref_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_alpha_ref_t f; +} rb_alpha_ref_u; + + +/* + * RB_COLOR_MASK struct + */ + +#define RB_COLOR_MASK_WRITE_RED_SIZE 1 +#define RB_COLOR_MASK_WRITE_GREEN_SIZE 1 +#define RB_COLOR_MASK_WRITE_BLUE_SIZE 1 +#define RB_COLOR_MASK_WRITE_ALPHA_SIZE 1 +#define RB_COLOR_MASK_RESERVED2_SIZE 1 +#define RB_COLOR_MASK_RESERVED3_SIZE 1 + +#define RB_COLOR_MASK_WRITE_RED_SHIFT 0 +#define RB_COLOR_MASK_WRITE_GREEN_SHIFT 1 +#define RB_COLOR_MASK_WRITE_BLUE_SHIFT 2 +#define RB_COLOR_MASK_WRITE_ALPHA_SHIFT 3 +#define RB_COLOR_MASK_RESERVED2_SHIFT 4 +#define RB_COLOR_MASK_RESERVED3_SHIFT 5 + +#define RB_COLOR_MASK_WRITE_RED_MASK 0x00000001 +#define RB_COLOR_MASK_WRITE_GREEN_MASK 0x00000002 +#define RB_COLOR_MASK_WRITE_BLUE_MASK 0x00000004 +#define RB_COLOR_MASK_WRITE_ALPHA_MASK 0x00000008 +#define RB_COLOR_MASK_RESERVED2_MASK 0x00000010 +#define RB_COLOR_MASK_RESERVED3_MASK 0x00000020 + +#define RB_COLOR_MASK_MASK \ + (RB_COLOR_MASK_WRITE_RED_MASK | \ + RB_COLOR_MASK_WRITE_GREEN_MASK | \ + RB_COLOR_MASK_WRITE_BLUE_MASK | \ + RB_COLOR_MASK_WRITE_ALPHA_MASK | \ + RB_COLOR_MASK_RESERVED2_MASK | \ + RB_COLOR_MASK_RESERVED3_MASK) + +#define RB_COLOR_MASK(write_red, write_green, write_blue, write_alpha, reserved2, reserved3) \ + ((write_red << RB_COLOR_MASK_WRITE_RED_SHIFT) | \ + (write_green << RB_COLOR_MASK_WRITE_GREEN_SHIFT) | \ + (write_blue << RB_COLOR_MASK_WRITE_BLUE_SHIFT) | \ + (write_alpha << RB_COLOR_MASK_WRITE_ALPHA_SHIFT) | \ + (reserved2 << RB_COLOR_MASK_RESERVED2_SHIFT) | \ + (reserved3 << RB_COLOR_MASK_RESERVED3_SHIFT)) + +#define RB_COLOR_MASK_GET_WRITE_RED(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_WRITE_RED_MASK) >> RB_COLOR_MASK_WRITE_RED_SHIFT) +#define RB_COLOR_MASK_GET_WRITE_GREEN(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_WRITE_GREEN_MASK) >> RB_COLOR_MASK_WRITE_GREEN_SHIFT) +#define RB_COLOR_MASK_GET_WRITE_BLUE(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_WRITE_BLUE_MASK) >> RB_COLOR_MASK_WRITE_BLUE_SHIFT) +#define RB_COLOR_MASK_GET_WRITE_ALPHA(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_WRITE_ALPHA_MASK) >> RB_COLOR_MASK_WRITE_ALPHA_SHIFT) +#define RB_COLOR_MASK_GET_RESERVED2(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_RESERVED2_MASK) >> RB_COLOR_MASK_RESERVED2_SHIFT) +#define RB_COLOR_MASK_GET_RESERVED3(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_RESERVED3_MASK) >> RB_COLOR_MASK_RESERVED3_SHIFT) + +#define RB_COLOR_MASK_SET_WRITE_RED(rb_color_mask_reg, write_red) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_RED_MASK) | (write_red << RB_COLOR_MASK_WRITE_RED_SHIFT) +#define RB_COLOR_MASK_SET_WRITE_GREEN(rb_color_mask_reg, write_green) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_GREEN_MASK) | (write_green << RB_COLOR_MASK_WRITE_GREEN_SHIFT) +#define RB_COLOR_MASK_SET_WRITE_BLUE(rb_color_mask_reg, write_blue) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_BLUE_MASK) | (write_blue << RB_COLOR_MASK_WRITE_BLUE_SHIFT) +#define RB_COLOR_MASK_SET_WRITE_ALPHA(rb_color_mask_reg, write_alpha) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_ALPHA_MASK) | (write_alpha << RB_COLOR_MASK_WRITE_ALPHA_SHIFT) +#define RB_COLOR_MASK_SET_RESERVED2(rb_color_mask_reg, reserved2) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_RESERVED2_MASK) | (reserved2 << RB_COLOR_MASK_RESERVED2_SHIFT) +#define RB_COLOR_MASK_SET_RESERVED3(rb_color_mask_reg, reserved3) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_RESERVED3_MASK) | (reserved3 << RB_COLOR_MASK_RESERVED3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_color_mask_t { + unsigned int write_red : RB_COLOR_MASK_WRITE_RED_SIZE; + unsigned int write_green : RB_COLOR_MASK_WRITE_GREEN_SIZE; + unsigned int write_blue : RB_COLOR_MASK_WRITE_BLUE_SIZE; + unsigned int write_alpha : RB_COLOR_MASK_WRITE_ALPHA_SIZE; + unsigned int reserved2 : RB_COLOR_MASK_RESERVED2_SIZE; + unsigned int reserved3 : RB_COLOR_MASK_RESERVED3_SIZE; + unsigned int : 26; + } rb_color_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_color_mask_t { + unsigned int : 26; + unsigned int reserved3 : RB_COLOR_MASK_RESERVED3_SIZE; + unsigned int reserved2 : RB_COLOR_MASK_RESERVED2_SIZE; + unsigned int write_alpha : RB_COLOR_MASK_WRITE_ALPHA_SIZE; + unsigned int write_blue : RB_COLOR_MASK_WRITE_BLUE_SIZE; + unsigned int write_green : RB_COLOR_MASK_WRITE_GREEN_SIZE; + unsigned int write_red : RB_COLOR_MASK_WRITE_RED_SIZE; + } rb_color_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_color_mask_t f; +} rb_color_mask_u; + + +/* + * RB_BLEND_RED struct + */ + +#define RB_BLEND_RED_BLEND_RED_SIZE 8 + +#define RB_BLEND_RED_BLEND_RED_SHIFT 0 + +#define RB_BLEND_RED_BLEND_RED_MASK 0x000000ff + +#define RB_BLEND_RED_MASK \ + (RB_BLEND_RED_BLEND_RED_MASK) + +#define RB_BLEND_RED(blend_red) \ + ((blend_red << RB_BLEND_RED_BLEND_RED_SHIFT)) + +#define RB_BLEND_RED_GET_BLEND_RED(rb_blend_red) \ + ((rb_blend_red & RB_BLEND_RED_BLEND_RED_MASK) >> RB_BLEND_RED_BLEND_RED_SHIFT) + +#define RB_BLEND_RED_SET_BLEND_RED(rb_blend_red_reg, blend_red) \ + rb_blend_red_reg = (rb_blend_red_reg & ~RB_BLEND_RED_BLEND_RED_MASK) | (blend_red << RB_BLEND_RED_BLEND_RED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blend_red_t { + unsigned int blend_red : RB_BLEND_RED_BLEND_RED_SIZE; + unsigned int : 24; + } rb_blend_red_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blend_red_t { + unsigned int : 24; + unsigned int blend_red : RB_BLEND_RED_BLEND_RED_SIZE; + } rb_blend_red_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blend_red_t f; +} rb_blend_red_u; + + +/* + * RB_BLEND_GREEN struct + */ + +#define RB_BLEND_GREEN_BLEND_GREEN_SIZE 8 + +#define RB_BLEND_GREEN_BLEND_GREEN_SHIFT 0 + +#define RB_BLEND_GREEN_BLEND_GREEN_MASK 0x000000ff + +#define RB_BLEND_GREEN_MASK \ + (RB_BLEND_GREEN_BLEND_GREEN_MASK) + +#define RB_BLEND_GREEN(blend_green) \ + ((blend_green << RB_BLEND_GREEN_BLEND_GREEN_SHIFT)) + +#define RB_BLEND_GREEN_GET_BLEND_GREEN(rb_blend_green) \ + ((rb_blend_green & RB_BLEND_GREEN_BLEND_GREEN_MASK) >> RB_BLEND_GREEN_BLEND_GREEN_SHIFT) + +#define RB_BLEND_GREEN_SET_BLEND_GREEN(rb_blend_green_reg, blend_green) \ + rb_blend_green_reg = (rb_blend_green_reg & ~RB_BLEND_GREEN_BLEND_GREEN_MASK) | (blend_green << RB_BLEND_GREEN_BLEND_GREEN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blend_green_t { + unsigned int blend_green : RB_BLEND_GREEN_BLEND_GREEN_SIZE; + unsigned int : 24; + } rb_blend_green_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blend_green_t { + unsigned int : 24; + unsigned int blend_green : RB_BLEND_GREEN_BLEND_GREEN_SIZE; + } rb_blend_green_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blend_green_t f; +} rb_blend_green_u; + + +/* + * RB_BLEND_BLUE struct + */ + +#define RB_BLEND_BLUE_BLEND_BLUE_SIZE 8 + +#define RB_BLEND_BLUE_BLEND_BLUE_SHIFT 0 + +#define RB_BLEND_BLUE_BLEND_BLUE_MASK 0x000000ff + +#define RB_BLEND_BLUE_MASK \ + (RB_BLEND_BLUE_BLEND_BLUE_MASK) + +#define RB_BLEND_BLUE(blend_blue) \ + ((blend_blue << RB_BLEND_BLUE_BLEND_BLUE_SHIFT)) + +#define RB_BLEND_BLUE_GET_BLEND_BLUE(rb_blend_blue) \ + ((rb_blend_blue & RB_BLEND_BLUE_BLEND_BLUE_MASK) >> RB_BLEND_BLUE_BLEND_BLUE_SHIFT) + +#define RB_BLEND_BLUE_SET_BLEND_BLUE(rb_blend_blue_reg, blend_blue) \ + rb_blend_blue_reg = (rb_blend_blue_reg & ~RB_BLEND_BLUE_BLEND_BLUE_MASK) | (blend_blue << RB_BLEND_BLUE_BLEND_BLUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blend_blue_t { + unsigned int blend_blue : RB_BLEND_BLUE_BLEND_BLUE_SIZE; + unsigned int : 24; + } rb_blend_blue_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blend_blue_t { + unsigned int : 24; + unsigned int blend_blue : RB_BLEND_BLUE_BLEND_BLUE_SIZE; + } rb_blend_blue_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blend_blue_t f; +} rb_blend_blue_u; + + +/* + * RB_BLEND_ALPHA struct + */ + +#define RB_BLEND_ALPHA_BLEND_ALPHA_SIZE 8 + +#define RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT 0 + +#define RB_BLEND_ALPHA_BLEND_ALPHA_MASK 0x000000ff + +#define RB_BLEND_ALPHA_MASK \ + (RB_BLEND_ALPHA_BLEND_ALPHA_MASK) + +#define RB_BLEND_ALPHA(blend_alpha) \ + ((blend_alpha << RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT)) + +#define RB_BLEND_ALPHA_GET_BLEND_ALPHA(rb_blend_alpha) \ + ((rb_blend_alpha & RB_BLEND_ALPHA_BLEND_ALPHA_MASK) >> RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT) + +#define RB_BLEND_ALPHA_SET_BLEND_ALPHA(rb_blend_alpha_reg, blend_alpha) \ + rb_blend_alpha_reg = (rb_blend_alpha_reg & ~RB_BLEND_ALPHA_BLEND_ALPHA_MASK) | (blend_alpha << RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blend_alpha_t { + unsigned int blend_alpha : RB_BLEND_ALPHA_BLEND_ALPHA_SIZE; + unsigned int : 24; + } rb_blend_alpha_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blend_alpha_t { + unsigned int : 24; + unsigned int blend_alpha : RB_BLEND_ALPHA_BLEND_ALPHA_SIZE; + } rb_blend_alpha_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blend_alpha_t f; +} rb_blend_alpha_u; + + +/* + * RB_FOG_COLOR struct + */ + +#define RB_FOG_COLOR_FOG_RED_SIZE 8 +#define RB_FOG_COLOR_FOG_GREEN_SIZE 8 +#define RB_FOG_COLOR_FOG_BLUE_SIZE 8 + +#define RB_FOG_COLOR_FOG_RED_SHIFT 0 +#define RB_FOG_COLOR_FOG_GREEN_SHIFT 8 +#define RB_FOG_COLOR_FOG_BLUE_SHIFT 16 + +#define RB_FOG_COLOR_FOG_RED_MASK 0x000000ff +#define RB_FOG_COLOR_FOG_GREEN_MASK 0x0000ff00 +#define RB_FOG_COLOR_FOG_BLUE_MASK 0x00ff0000 + +#define RB_FOG_COLOR_MASK \ + (RB_FOG_COLOR_FOG_RED_MASK | \ + RB_FOG_COLOR_FOG_GREEN_MASK | \ + RB_FOG_COLOR_FOG_BLUE_MASK) + +#define RB_FOG_COLOR(fog_red, fog_green, fog_blue) \ + ((fog_red << RB_FOG_COLOR_FOG_RED_SHIFT) | \ + (fog_green << RB_FOG_COLOR_FOG_GREEN_SHIFT) | \ + (fog_blue << RB_FOG_COLOR_FOG_BLUE_SHIFT)) + +#define RB_FOG_COLOR_GET_FOG_RED(rb_fog_color) \ + ((rb_fog_color & RB_FOG_COLOR_FOG_RED_MASK) >> RB_FOG_COLOR_FOG_RED_SHIFT) +#define RB_FOG_COLOR_GET_FOG_GREEN(rb_fog_color) \ + ((rb_fog_color & RB_FOG_COLOR_FOG_GREEN_MASK) >> RB_FOG_COLOR_FOG_GREEN_SHIFT) +#define RB_FOG_COLOR_GET_FOG_BLUE(rb_fog_color) \ + ((rb_fog_color & RB_FOG_COLOR_FOG_BLUE_MASK) >> RB_FOG_COLOR_FOG_BLUE_SHIFT) + +#define RB_FOG_COLOR_SET_FOG_RED(rb_fog_color_reg, fog_red) \ + rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_RED_MASK) | (fog_red << RB_FOG_COLOR_FOG_RED_SHIFT) +#define RB_FOG_COLOR_SET_FOG_GREEN(rb_fog_color_reg, fog_green) \ + rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_GREEN_MASK) | (fog_green << RB_FOG_COLOR_FOG_GREEN_SHIFT) +#define RB_FOG_COLOR_SET_FOG_BLUE(rb_fog_color_reg, fog_blue) \ + rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_BLUE_MASK) | (fog_blue << RB_FOG_COLOR_FOG_BLUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_fog_color_t { + unsigned int fog_red : RB_FOG_COLOR_FOG_RED_SIZE; + unsigned int fog_green : RB_FOG_COLOR_FOG_GREEN_SIZE; + unsigned int fog_blue : RB_FOG_COLOR_FOG_BLUE_SIZE; + unsigned int : 8; + } rb_fog_color_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_fog_color_t { + unsigned int : 8; + unsigned int fog_blue : RB_FOG_COLOR_FOG_BLUE_SIZE; + unsigned int fog_green : RB_FOG_COLOR_FOG_GREEN_SIZE; + unsigned int fog_red : RB_FOG_COLOR_FOG_RED_SIZE; + } rb_fog_color_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_fog_color_t f; +} rb_fog_color_u; + + +/* + * RB_STENCILREFMASK_BF struct + */ + +#define RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE 8 +#define RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE 8 +#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE 8 +#define RB_STENCILREFMASK_BF_RESERVED4_SIZE 1 +#define RB_STENCILREFMASK_BF_RESERVED5_SIZE 1 + +#define RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT 0 +#define RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT 8 +#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT 16 +#define RB_STENCILREFMASK_BF_RESERVED4_SHIFT 24 +#define RB_STENCILREFMASK_BF_RESERVED5_SHIFT 25 + +#define RB_STENCILREFMASK_BF_STENCILREF_BF_MASK 0x000000ff +#define RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK 0x0000ff00 +#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK 0x00ff0000 +#define RB_STENCILREFMASK_BF_RESERVED4_MASK 0x01000000 +#define RB_STENCILREFMASK_BF_RESERVED5_MASK 0x02000000 + +#define RB_STENCILREFMASK_BF_MASK \ + (RB_STENCILREFMASK_BF_STENCILREF_BF_MASK | \ + RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK | \ + RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK | \ + RB_STENCILREFMASK_BF_RESERVED4_MASK | \ + RB_STENCILREFMASK_BF_RESERVED5_MASK) + +#define RB_STENCILREFMASK_BF(stencilref_bf, stencilmask_bf, stencilwritemask_bf, reserved4, reserved5) \ + ((stencilref_bf << RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT) | \ + (stencilmask_bf << RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT) | \ + (stencilwritemask_bf << RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT) | \ + (reserved4 << RB_STENCILREFMASK_BF_RESERVED4_SHIFT) | \ + (reserved5 << RB_STENCILREFMASK_BF_RESERVED5_SHIFT)) + +#define RB_STENCILREFMASK_BF_GET_STENCILREF_BF(rb_stencilrefmask_bf) \ + ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILREF_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT) +#define RB_STENCILREFMASK_BF_GET_STENCILMASK_BF(rb_stencilrefmask_bf) \ + ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT) +#define RB_STENCILREFMASK_BF_GET_STENCILWRITEMASK_BF(rb_stencilrefmask_bf) \ + ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT) +#define RB_STENCILREFMASK_BF_GET_RESERVED4(rb_stencilrefmask_bf) \ + ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_RESERVED4_MASK) >> RB_STENCILREFMASK_BF_RESERVED4_SHIFT) +#define RB_STENCILREFMASK_BF_GET_RESERVED5(rb_stencilrefmask_bf) \ + ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_RESERVED5_MASK) >> RB_STENCILREFMASK_BF_RESERVED5_SHIFT) + +#define RB_STENCILREFMASK_BF_SET_STENCILREF_BF(rb_stencilrefmask_bf_reg, stencilref_bf) \ + rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILREF_BF_MASK) | (stencilref_bf << RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT) +#define RB_STENCILREFMASK_BF_SET_STENCILMASK_BF(rb_stencilrefmask_bf_reg, stencilmask_bf) \ + rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK) | (stencilmask_bf << RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT) +#define RB_STENCILREFMASK_BF_SET_STENCILWRITEMASK_BF(rb_stencilrefmask_bf_reg, stencilwritemask_bf) \ + rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK) | (stencilwritemask_bf << RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT) +#define RB_STENCILREFMASK_BF_SET_RESERVED4(rb_stencilrefmask_bf_reg, reserved4) \ + rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_RESERVED4_MASK) | (reserved4 << RB_STENCILREFMASK_BF_RESERVED4_SHIFT) +#define RB_STENCILREFMASK_BF_SET_RESERVED5(rb_stencilrefmask_bf_reg, reserved5) \ + rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_RESERVED5_MASK) | (reserved5 << RB_STENCILREFMASK_BF_RESERVED5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_stencilrefmask_bf_t { + unsigned int stencilref_bf : RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE; + unsigned int stencilmask_bf : RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE; + unsigned int stencilwritemask_bf : RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE; + unsigned int reserved4 : RB_STENCILREFMASK_BF_RESERVED4_SIZE; + unsigned int reserved5 : RB_STENCILREFMASK_BF_RESERVED5_SIZE; + unsigned int : 6; + } rb_stencilrefmask_bf_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_stencilrefmask_bf_t { + unsigned int : 6; + unsigned int reserved5 : RB_STENCILREFMASK_BF_RESERVED5_SIZE; + unsigned int reserved4 : RB_STENCILREFMASK_BF_RESERVED4_SIZE; + unsigned int stencilwritemask_bf : RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE; + unsigned int stencilmask_bf : RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE; + unsigned int stencilref_bf : RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE; + } rb_stencilrefmask_bf_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_stencilrefmask_bf_t f; +} rb_stencilrefmask_bf_u; + + +/* + * RB_DEPTHCONTROL struct + */ + +#define RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_Z_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_ZFUNC_SIZE 3 +#define RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_STENCILFUNC_SIZE 3 +#define RB_DEPTHCONTROL_STENCILFAIL_SIZE 3 +#define RB_DEPTHCONTROL_STENCILZPASS_SIZE 3 +#define RB_DEPTHCONTROL_STENCILZFAIL_SIZE 3 +#define RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE 3 +#define RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE 3 +#define RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE 3 +#define RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE 3 + +#define RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT 0 +#define RB_DEPTHCONTROL_Z_ENABLE_SHIFT 1 +#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT 2 +#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT 3 +#define RB_DEPTHCONTROL_ZFUNC_SHIFT 4 +#define RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT 7 +#define RB_DEPTHCONTROL_STENCILFUNC_SHIFT 8 +#define RB_DEPTHCONTROL_STENCILFAIL_SHIFT 11 +#define RB_DEPTHCONTROL_STENCILZPASS_SHIFT 14 +#define RB_DEPTHCONTROL_STENCILZFAIL_SHIFT 17 +#define RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT 20 +#define RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT 23 +#define RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT 26 +#define RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT 29 + +#define RB_DEPTHCONTROL_STENCIL_ENABLE_MASK 0x00000001 +#define RB_DEPTHCONTROL_Z_ENABLE_MASK 0x00000002 +#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK 0x00000004 +#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK 0x00000008 +#define RB_DEPTHCONTROL_ZFUNC_MASK 0x00000070 +#define RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK 0x00000080 +#define RB_DEPTHCONTROL_STENCILFUNC_MASK 0x00000700 +#define RB_DEPTHCONTROL_STENCILFAIL_MASK 0x00003800 +#define RB_DEPTHCONTROL_STENCILZPASS_MASK 0x0001c000 +#define RB_DEPTHCONTROL_STENCILZFAIL_MASK 0x000e0000 +#define RB_DEPTHCONTROL_STENCILFUNC_BF_MASK 0x00700000 +#define RB_DEPTHCONTROL_STENCILFAIL_BF_MASK 0x03800000 +#define RB_DEPTHCONTROL_STENCILZPASS_BF_MASK 0x1c000000 +#define RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK 0xe0000000 + +#define RB_DEPTHCONTROL_MASK \ + (RB_DEPTHCONTROL_STENCIL_ENABLE_MASK | \ + RB_DEPTHCONTROL_Z_ENABLE_MASK | \ + RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK | \ + RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK | \ + RB_DEPTHCONTROL_ZFUNC_MASK | \ + RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK | \ + RB_DEPTHCONTROL_STENCILFUNC_MASK | \ + RB_DEPTHCONTROL_STENCILFAIL_MASK | \ + RB_DEPTHCONTROL_STENCILZPASS_MASK | \ + RB_DEPTHCONTROL_STENCILZFAIL_MASK | \ + RB_DEPTHCONTROL_STENCILFUNC_BF_MASK | \ + RB_DEPTHCONTROL_STENCILFAIL_BF_MASK | \ + RB_DEPTHCONTROL_STENCILZPASS_BF_MASK | \ + RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) + +#define RB_DEPTHCONTROL(stencil_enable, z_enable, z_write_enable, early_z_enable, zfunc, backface_enable, stencilfunc, stencilfail, stencilzpass, stencilzfail, stencilfunc_bf, stencilfail_bf, stencilzpass_bf, stencilzfail_bf) \ + ((stencil_enable << RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT) | \ + (z_enable << RB_DEPTHCONTROL_Z_ENABLE_SHIFT) | \ + (z_write_enable << RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT) | \ + (early_z_enable << RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT) | \ + (zfunc << RB_DEPTHCONTROL_ZFUNC_SHIFT) | \ + (backface_enable << RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT) | \ + (stencilfunc << RB_DEPTHCONTROL_STENCILFUNC_SHIFT) | \ + (stencilfail << RB_DEPTHCONTROL_STENCILFAIL_SHIFT) | \ + (stencilzpass << RB_DEPTHCONTROL_STENCILZPASS_SHIFT) | \ + (stencilzfail << RB_DEPTHCONTROL_STENCILZFAIL_SHIFT) | \ + (stencilfunc_bf << RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT) | \ + (stencilfail_bf << RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT) | \ + (stencilzpass_bf << RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT) | \ + (stencilzfail_bf << RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT)) + +#define RB_DEPTHCONTROL_GET_STENCIL_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCIL_ENABLE_MASK) >> RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_Z_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_Z_ENABLE_MASK) >> RB_DEPTHCONTROL_Z_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_Z_WRITE_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK) >> RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_EARLY_Z_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK) >> RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_ZFUNC(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_ZFUNC_MASK) >> RB_DEPTHCONTROL_ZFUNC_SHIFT) +#define RB_DEPTHCONTROL_GET_BACKFACE_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK) >> RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILFUNC(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFUNC_MASK) >> RB_DEPTHCONTROL_STENCILFUNC_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILFAIL(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFAIL_MASK) >> RB_DEPTHCONTROL_STENCILFAIL_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILZPASS(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZPASS_MASK) >> RB_DEPTHCONTROL_STENCILZPASS_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILZFAIL(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZFAIL_MASK) >> RB_DEPTHCONTROL_STENCILZFAIL_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILFUNC_BF(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFUNC_BF_MASK) >> RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILFAIL_BF(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFAIL_BF_MASK) >> RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILZPASS_BF(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZPASS_BF_MASK) >> RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILZFAIL_BF(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) >> RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT) + +#define RB_DEPTHCONTROL_SET_STENCIL_ENABLE(rb_depthcontrol_reg, stencil_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCIL_ENABLE_MASK) | (stencil_enable << RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_Z_ENABLE(rb_depthcontrol_reg, z_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_Z_ENABLE_MASK) | (z_enable << RB_DEPTHCONTROL_Z_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_Z_WRITE_ENABLE(rb_depthcontrol_reg, z_write_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK) | (z_write_enable << RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_EARLY_Z_ENABLE(rb_depthcontrol_reg, early_z_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK) | (early_z_enable << RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_ZFUNC(rb_depthcontrol_reg, zfunc) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_ZFUNC_MASK) | (zfunc << RB_DEPTHCONTROL_ZFUNC_SHIFT) +#define RB_DEPTHCONTROL_SET_BACKFACE_ENABLE(rb_depthcontrol_reg, backface_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK) | (backface_enable << RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILFUNC(rb_depthcontrol_reg, stencilfunc) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFUNC_MASK) | (stencilfunc << RB_DEPTHCONTROL_STENCILFUNC_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILFAIL(rb_depthcontrol_reg, stencilfail) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFAIL_MASK) | (stencilfail << RB_DEPTHCONTROL_STENCILFAIL_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILZPASS(rb_depthcontrol_reg, stencilzpass) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZPASS_MASK) | (stencilzpass << RB_DEPTHCONTROL_STENCILZPASS_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILZFAIL(rb_depthcontrol_reg, stencilzfail) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZFAIL_MASK) | (stencilzfail << RB_DEPTHCONTROL_STENCILZFAIL_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILFUNC_BF(rb_depthcontrol_reg, stencilfunc_bf) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFUNC_BF_MASK) | (stencilfunc_bf << RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILFAIL_BF(rb_depthcontrol_reg, stencilfail_bf) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFAIL_BF_MASK) | (stencilfail_bf << RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILZPASS_BF(rb_depthcontrol_reg, stencilzpass_bf) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZPASS_BF_MASK) | (stencilzpass_bf << RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILZFAIL_BF(rb_depthcontrol_reg, stencilzfail_bf) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) | (stencilzfail_bf << RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_depthcontrol_t { + unsigned int stencil_enable : RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE; + unsigned int z_enable : RB_DEPTHCONTROL_Z_ENABLE_SIZE; + unsigned int z_write_enable : RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE; + unsigned int early_z_enable : RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE; + unsigned int zfunc : RB_DEPTHCONTROL_ZFUNC_SIZE; + unsigned int backface_enable : RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE; + unsigned int stencilfunc : RB_DEPTHCONTROL_STENCILFUNC_SIZE; + unsigned int stencilfail : RB_DEPTHCONTROL_STENCILFAIL_SIZE; + unsigned int stencilzpass : RB_DEPTHCONTROL_STENCILZPASS_SIZE; + unsigned int stencilzfail : RB_DEPTHCONTROL_STENCILZFAIL_SIZE; + unsigned int stencilfunc_bf : RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE; + unsigned int stencilfail_bf : RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE; + unsigned int stencilzpass_bf : RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE; + unsigned int stencilzfail_bf : RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE; + } rb_depthcontrol_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_depthcontrol_t { + unsigned int stencilzfail_bf : RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE; + unsigned int stencilzpass_bf : RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE; + unsigned int stencilfail_bf : RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE; + unsigned int stencilfunc_bf : RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE; + unsigned int stencilzfail : RB_DEPTHCONTROL_STENCILZFAIL_SIZE; + unsigned int stencilzpass : RB_DEPTHCONTROL_STENCILZPASS_SIZE; + unsigned int stencilfail : RB_DEPTHCONTROL_STENCILFAIL_SIZE; + unsigned int stencilfunc : RB_DEPTHCONTROL_STENCILFUNC_SIZE; + unsigned int backface_enable : RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE; + unsigned int zfunc : RB_DEPTHCONTROL_ZFUNC_SIZE; + unsigned int early_z_enable : RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE; + unsigned int z_write_enable : RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE; + unsigned int z_enable : RB_DEPTHCONTROL_Z_ENABLE_SIZE; + unsigned int stencil_enable : RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE; + } rb_depthcontrol_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_depthcontrol_t f; +} rb_depthcontrol_u; + + +/* + * RB_BLENDCONTROL struct + */ + +#define RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE 5 +#define RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE 3 +#define RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE 5 +#define RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE 5 +#define RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE 3 +#define RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE 5 +#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE 1 +#define RB_BLENDCONTROL_BLEND_FORCE_SIZE 1 + +#define RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT 0 +#define RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT 5 +#define RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT 8 +#define RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT 16 +#define RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT 21 +#define RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT 24 +#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT 29 +#define RB_BLENDCONTROL_BLEND_FORCE_SHIFT 30 + +#define RB_BLENDCONTROL_COLOR_SRCBLEND_MASK 0x0000001f +#define RB_BLENDCONTROL_COLOR_COMB_FCN_MASK 0x000000e0 +#define RB_BLENDCONTROL_COLOR_DESTBLEND_MASK 0x00001f00 +#define RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK 0x001f0000 +#define RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK 0x00e00000 +#define RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK 0x1f000000 +#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK 0x20000000 +#define RB_BLENDCONTROL_BLEND_FORCE_MASK 0x40000000 + +#define RB_BLENDCONTROL_MASK \ + (RB_BLENDCONTROL_COLOR_SRCBLEND_MASK | \ + RB_BLENDCONTROL_COLOR_COMB_FCN_MASK | \ + RB_BLENDCONTROL_COLOR_DESTBLEND_MASK | \ + RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK | \ + RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK | \ + RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK | \ + RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK | \ + RB_BLENDCONTROL_BLEND_FORCE_MASK) + +#define RB_BLENDCONTROL(color_srcblend, color_comb_fcn, color_destblend, alpha_srcblend, alpha_comb_fcn, alpha_destblend, blend_force_enable, blend_force) \ + ((color_srcblend << RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT) | \ + (color_comb_fcn << RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT) | \ + (color_destblend << RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT) | \ + (alpha_srcblend << RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT) | \ + (alpha_comb_fcn << RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT) | \ + (alpha_destblend << RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT) | \ + (blend_force_enable << RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT) | \ + (blend_force << RB_BLENDCONTROL_BLEND_FORCE_SHIFT)) + +#define RB_BLENDCONTROL_GET_COLOR_SRCBLEND(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_SRCBLEND_MASK) >> RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT) +#define RB_BLENDCONTROL_GET_COLOR_COMB_FCN(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_COMB_FCN_MASK) >> RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT) +#define RB_BLENDCONTROL_GET_COLOR_DESTBLEND(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_DESTBLEND_MASK) >> RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT) +#define RB_BLENDCONTROL_GET_ALPHA_SRCBLEND(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK) >> RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT) +#define RB_BLENDCONTROL_GET_ALPHA_COMB_FCN(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK) >> RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT) +#define RB_BLENDCONTROL_GET_ALPHA_DESTBLEND(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK) >> RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT) +#define RB_BLENDCONTROL_GET_BLEND_FORCE_ENABLE(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK) >> RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT) +#define RB_BLENDCONTROL_GET_BLEND_FORCE(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_BLEND_FORCE_MASK) >> RB_BLENDCONTROL_BLEND_FORCE_SHIFT) + +#define RB_BLENDCONTROL_SET_COLOR_SRCBLEND(rb_blendcontrol_reg, color_srcblend) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_SRCBLEND_MASK) | (color_srcblend << RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT) +#define RB_BLENDCONTROL_SET_COLOR_COMB_FCN(rb_blendcontrol_reg, color_comb_fcn) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_COMB_FCN_MASK) | (color_comb_fcn << RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT) +#define RB_BLENDCONTROL_SET_COLOR_DESTBLEND(rb_blendcontrol_reg, color_destblend) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_DESTBLEND_MASK) | (color_destblend << RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT) +#define RB_BLENDCONTROL_SET_ALPHA_SRCBLEND(rb_blendcontrol_reg, alpha_srcblend) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK) | (alpha_srcblend << RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT) +#define RB_BLENDCONTROL_SET_ALPHA_COMB_FCN(rb_blendcontrol_reg, alpha_comb_fcn) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK) | (alpha_comb_fcn << RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT) +#define RB_BLENDCONTROL_SET_ALPHA_DESTBLEND(rb_blendcontrol_reg, alpha_destblend) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK) | (alpha_destblend << RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT) +#define RB_BLENDCONTROL_SET_BLEND_FORCE_ENABLE(rb_blendcontrol_reg, blend_force_enable) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK) | (blend_force_enable << RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT) +#define RB_BLENDCONTROL_SET_BLEND_FORCE(rb_blendcontrol_reg, blend_force) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_BLEND_FORCE_MASK) | (blend_force << RB_BLENDCONTROL_BLEND_FORCE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blendcontrol_t { + unsigned int color_srcblend : RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE; + unsigned int color_comb_fcn : RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE; + unsigned int color_destblend : RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE; + unsigned int : 3; + unsigned int alpha_srcblend : RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE; + unsigned int alpha_comb_fcn : RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE; + unsigned int alpha_destblend : RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE; + unsigned int blend_force_enable : RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE; + unsigned int blend_force : RB_BLENDCONTROL_BLEND_FORCE_SIZE; + unsigned int : 1; + } rb_blendcontrol_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blendcontrol_t { + unsigned int : 1; + unsigned int blend_force : RB_BLENDCONTROL_BLEND_FORCE_SIZE; + unsigned int blend_force_enable : RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE; + unsigned int alpha_destblend : RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE; + unsigned int alpha_comb_fcn : RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE; + unsigned int alpha_srcblend : RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE; + unsigned int : 3; + unsigned int color_destblend : RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE; + unsigned int color_comb_fcn : RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE; + unsigned int color_srcblend : RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE; + } rb_blendcontrol_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blendcontrol_t f; +} rb_blendcontrol_u; + + +/* + * RB_COLORCONTROL struct + */ + +#define RB_COLORCONTROL_ALPHA_FUNC_SIZE 3 +#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE 1 +#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE 1 +#define RB_COLORCONTROL_BLEND_DISABLE_SIZE 1 +#define RB_COLORCONTROL_FOG_ENABLE_SIZE 1 +#define RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE 1 +#define RB_COLORCONTROL_ROP_CODE_SIZE 4 +#define RB_COLORCONTROL_DITHER_MODE_SIZE 2 +#define RB_COLORCONTROL_DITHER_TYPE_SIZE 2 +#define RB_COLORCONTROL_PIXEL_FOG_SIZE 1 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE 2 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE 2 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE 2 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE 2 + +#define RB_COLORCONTROL_ALPHA_FUNC_SHIFT 0 +#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT 3 +#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT 4 +#define RB_COLORCONTROL_BLEND_DISABLE_SHIFT 5 +#define RB_COLORCONTROL_FOG_ENABLE_SHIFT 6 +#define RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT 7 +#define RB_COLORCONTROL_ROP_CODE_SHIFT 8 +#define RB_COLORCONTROL_DITHER_MODE_SHIFT 12 +#define RB_COLORCONTROL_DITHER_TYPE_SHIFT 14 +#define RB_COLORCONTROL_PIXEL_FOG_SHIFT 16 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT 24 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT 26 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT 28 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT 30 + +#define RB_COLORCONTROL_ALPHA_FUNC_MASK 0x00000007 +#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK 0x00000008 +#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK 0x00000010 +#define RB_COLORCONTROL_BLEND_DISABLE_MASK 0x00000020 +#define RB_COLORCONTROL_FOG_ENABLE_MASK 0x00000040 +#define RB_COLORCONTROL_VS_EXPORTS_FOG_MASK 0x00000080 +#define RB_COLORCONTROL_ROP_CODE_MASK 0x00000f00 +#define RB_COLORCONTROL_DITHER_MODE_MASK 0x00003000 +#define RB_COLORCONTROL_DITHER_TYPE_MASK 0x0000c000 +#define RB_COLORCONTROL_PIXEL_FOG_MASK 0x00010000 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK 0x03000000 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK 0x0c000000 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK 0x30000000 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK 0xc0000000 + +#define RB_COLORCONTROL_MASK \ + (RB_COLORCONTROL_ALPHA_FUNC_MASK | \ + RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK | \ + RB_COLORCONTROL_BLEND_DISABLE_MASK | \ + RB_COLORCONTROL_FOG_ENABLE_MASK | \ + RB_COLORCONTROL_VS_EXPORTS_FOG_MASK | \ + RB_COLORCONTROL_ROP_CODE_MASK | \ + RB_COLORCONTROL_DITHER_MODE_MASK | \ + RB_COLORCONTROL_DITHER_TYPE_MASK | \ + RB_COLORCONTROL_PIXEL_FOG_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) + +#define RB_COLORCONTROL(alpha_func, alpha_test_enable, alpha_to_mask_enable, blend_disable, fog_enable, vs_exports_fog, rop_code, dither_mode, dither_type, pixel_fog, alpha_to_mask_offset0, alpha_to_mask_offset1, alpha_to_mask_offset2, alpha_to_mask_offset3) \ + ((alpha_func << RB_COLORCONTROL_ALPHA_FUNC_SHIFT) | \ + (alpha_test_enable << RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT) | \ + (alpha_to_mask_enable << RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT) | \ + (blend_disable << RB_COLORCONTROL_BLEND_DISABLE_SHIFT) | \ + (fog_enable << RB_COLORCONTROL_FOG_ENABLE_SHIFT) | \ + (vs_exports_fog << RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT) | \ + (rop_code << RB_COLORCONTROL_ROP_CODE_SHIFT) | \ + (dither_mode << RB_COLORCONTROL_DITHER_MODE_SHIFT) | \ + (dither_type << RB_COLORCONTROL_DITHER_TYPE_SHIFT) | \ + (pixel_fog << RB_COLORCONTROL_PIXEL_FOG_SHIFT) | \ + (alpha_to_mask_offset0 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT) | \ + (alpha_to_mask_offset1 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT) | \ + (alpha_to_mask_offset2 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT) | \ + (alpha_to_mask_offset3 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT)) + +#define RB_COLORCONTROL_GET_ALPHA_FUNC(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_FUNC_MASK) >> RB_COLORCONTROL_ALPHA_FUNC_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TEST_ENABLE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK) >> RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_ENABLE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT) +#define RB_COLORCONTROL_GET_BLEND_DISABLE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_BLEND_DISABLE_MASK) >> RB_COLORCONTROL_BLEND_DISABLE_SHIFT) +#define RB_COLORCONTROL_GET_FOG_ENABLE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_FOG_ENABLE_MASK) >> RB_COLORCONTROL_FOG_ENABLE_SHIFT) +#define RB_COLORCONTROL_GET_VS_EXPORTS_FOG(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_VS_EXPORTS_FOG_MASK) >> RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT) +#define RB_COLORCONTROL_GET_ROP_CODE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ROP_CODE_MASK) >> RB_COLORCONTROL_ROP_CODE_SHIFT) +#define RB_COLORCONTROL_GET_DITHER_MODE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_DITHER_MODE_MASK) >> RB_COLORCONTROL_DITHER_MODE_SHIFT) +#define RB_COLORCONTROL_GET_DITHER_TYPE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_DITHER_TYPE_MASK) >> RB_COLORCONTROL_DITHER_TYPE_SHIFT) +#define RB_COLORCONTROL_GET_PIXEL_FOG(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_PIXEL_FOG_MASK) >> RB_COLORCONTROL_PIXEL_FOG_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET0(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET1(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET2(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET3(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT) + +#define RB_COLORCONTROL_SET_ALPHA_FUNC(rb_colorcontrol_reg, alpha_func) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_FUNC_MASK) | (alpha_func << RB_COLORCONTROL_ALPHA_FUNC_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TEST_ENABLE(rb_colorcontrol_reg, alpha_test_enable) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK) | (alpha_test_enable << RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_ENABLE(rb_colorcontrol_reg, alpha_to_mask_enable) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK) | (alpha_to_mask_enable << RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT) +#define RB_COLORCONTROL_SET_BLEND_DISABLE(rb_colorcontrol_reg, blend_disable) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_BLEND_DISABLE_MASK) | (blend_disable << RB_COLORCONTROL_BLEND_DISABLE_SHIFT) +#define RB_COLORCONTROL_SET_FOG_ENABLE(rb_colorcontrol_reg, fog_enable) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_FOG_ENABLE_MASK) | (fog_enable << RB_COLORCONTROL_FOG_ENABLE_SHIFT) +#define RB_COLORCONTROL_SET_VS_EXPORTS_FOG(rb_colorcontrol_reg, vs_exports_fog) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_VS_EXPORTS_FOG_MASK) | (vs_exports_fog << RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT) +#define RB_COLORCONTROL_SET_ROP_CODE(rb_colorcontrol_reg, rop_code) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ROP_CODE_MASK) | (rop_code << RB_COLORCONTROL_ROP_CODE_SHIFT) +#define RB_COLORCONTROL_SET_DITHER_MODE(rb_colorcontrol_reg, dither_mode) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_DITHER_MODE_MASK) | (dither_mode << RB_COLORCONTROL_DITHER_MODE_SHIFT) +#define RB_COLORCONTROL_SET_DITHER_TYPE(rb_colorcontrol_reg, dither_type) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_DITHER_TYPE_MASK) | (dither_type << RB_COLORCONTROL_DITHER_TYPE_SHIFT) +#define RB_COLORCONTROL_SET_PIXEL_FOG(rb_colorcontrol_reg, pixel_fog) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_PIXEL_FOG_MASK) | (pixel_fog << RB_COLORCONTROL_PIXEL_FOG_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET0(rb_colorcontrol_reg, alpha_to_mask_offset0) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK) | (alpha_to_mask_offset0 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET1(rb_colorcontrol_reg, alpha_to_mask_offset1) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK) | (alpha_to_mask_offset1 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET2(rb_colorcontrol_reg, alpha_to_mask_offset2) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK) | (alpha_to_mask_offset2 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET3(rb_colorcontrol_reg, alpha_to_mask_offset3) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) | (alpha_to_mask_offset3 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_colorcontrol_t { + unsigned int alpha_func : RB_COLORCONTROL_ALPHA_FUNC_SIZE; + unsigned int alpha_test_enable : RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE; + unsigned int alpha_to_mask_enable : RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE; + unsigned int blend_disable : RB_COLORCONTROL_BLEND_DISABLE_SIZE; + unsigned int fog_enable : RB_COLORCONTROL_FOG_ENABLE_SIZE; + unsigned int vs_exports_fog : RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE; + unsigned int rop_code : RB_COLORCONTROL_ROP_CODE_SIZE; + unsigned int dither_mode : RB_COLORCONTROL_DITHER_MODE_SIZE; + unsigned int dither_type : RB_COLORCONTROL_DITHER_TYPE_SIZE; + unsigned int pixel_fog : RB_COLORCONTROL_PIXEL_FOG_SIZE; + unsigned int : 7; + unsigned int alpha_to_mask_offset0 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE; + unsigned int alpha_to_mask_offset1 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE; + unsigned int alpha_to_mask_offset2 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE; + unsigned int alpha_to_mask_offset3 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE; + } rb_colorcontrol_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_colorcontrol_t { + unsigned int alpha_to_mask_offset3 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE; + unsigned int alpha_to_mask_offset2 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE; + unsigned int alpha_to_mask_offset1 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE; + unsigned int alpha_to_mask_offset0 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE; + unsigned int : 7; + unsigned int pixel_fog : RB_COLORCONTROL_PIXEL_FOG_SIZE; + unsigned int dither_type : RB_COLORCONTROL_DITHER_TYPE_SIZE; + unsigned int dither_mode : RB_COLORCONTROL_DITHER_MODE_SIZE; + unsigned int rop_code : RB_COLORCONTROL_ROP_CODE_SIZE; + unsigned int vs_exports_fog : RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE; + unsigned int fog_enable : RB_COLORCONTROL_FOG_ENABLE_SIZE; + unsigned int blend_disable : RB_COLORCONTROL_BLEND_DISABLE_SIZE; + unsigned int alpha_to_mask_enable : RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE; + unsigned int alpha_test_enable : RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE; + unsigned int alpha_func : RB_COLORCONTROL_ALPHA_FUNC_SIZE; + } rb_colorcontrol_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_colorcontrol_t f; +} rb_colorcontrol_u; + + +/* + * RB_MODECONTROL struct + */ + +#define RB_MODECONTROL_EDRAM_MODE_SIZE 3 + +#define RB_MODECONTROL_EDRAM_MODE_SHIFT 0 + +#define RB_MODECONTROL_EDRAM_MODE_MASK 0x00000007 + +#define RB_MODECONTROL_MASK \ + (RB_MODECONTROL_EDRAM_MODE_MASK) + +#define RB_MODECONTROL(edram_mode) \ + ((edram_mode << RB_MODECONTROL_EDRAM_MODE_SHIFT)) + +#define RB_MODECONTROL_GET_EDRAM_MODE(rb_modecontrol) \ + ((rb_modecontrol & RB_MODECONTROL_EDRAM_MODE_MASK) >> RB_MODECONTROL_EDRAM_MODE_SHIFT) + +#define RB_MODECONTROL_SET_EDRAM_MODE(rb_modecontrol_reg, edram_mode) \ + rb_modecontrol_reg = (rb_modecontrol_reg & ~RB_MODECONTROL_EDRAM_MODE_MASK) | (edram_mode << RB_MODECONTROL_EDRAM_MODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_modecontrol_t { + unsigned int edram_mode : RB_MODECONTROL_EDRAM_MODE_SIZE; + unsigned int : 29; + } rb_modecontrol_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_modecontrol_t { + unsigned int : 29; + unsigned int edram_mode : RB_MODECONTROL_EDRAM_MODE_SIZE; + } rb_modecontrol_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_modecontrol_t f; +} rb_modecontrol_u; + + +/* + * RB_COLOR_DEST_MASK struct + */ + +#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE 32 + +#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT 0 + +#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK 0xffffffff + +#define RB_COLOR_DEST_MASK_MASK \ + (RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) + +#define RB_COLOR_DEST_MASK(color_dest_mask) \ + ((color_dest_mask << RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT)) + +#define RB_COLOR_DEST_MASK_GET_COLOR_DEST_MASK(rb_color_dest_mask) \ + ((rb_color_dest_mask & RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) >> RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT) + +#define RB_COLOR_DEST_MASK_SET_COLOR_DEST_MASK(rb_color_dest_mask_reg, color_dest_mask) \ + rb_color_dest_mask_reg = (rb_color_dest_mask_reg & ~RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) | (color_dest_mask << RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_color_dest_mask_t { + unsigned int color_dest_mask : RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE; + } rb_color_dest_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_color_dest_mask_t { + unsigned int color_dest_mask : RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE; + } rb_color_dest_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_color_dest_mask_t f; +} rb_color_dest_mask_u; + + +/* + * RB_COPY_CONTROL struct + */ + +#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE 3 +#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE 1 +#define RB_COPY_CONTROL_CLEAR_MASK_SIZE 4 + +#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT 0 +#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT 3 +#define RB_COPY_CONTROL_CLEAR_MASK_SHIFT 4 + +#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK 0x00000007 +#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK 0x00000008 +#define RB_COPY_CONTROL_CLEAR_MASK_MASK 0x000000f0 + +#define RB_COPY_CONTROL_MASK \ + (RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK | \ + RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK | \ + RB_COPY_CONTROL_CLEAR_MASK_MASK) + +#define RB_COPY_CONTROL(copy_sample_select, depth_clear_enable, clear_mask) \ + ((copy_sample_select << RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT) | \ + (depth_clear_enable << RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT) | \ + (clear_mask << RB_COPY_CONTROL_CLEAR_MASK_SHIFT)) + +#define RB_COPY_CONTROL_GET_COPY_SAMPLE_SELECT(rb_copy_control) \ + ((rb_copy_control & RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK) >> RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT) +#define RB_COPY_CONTROL_GET_DEPTH_CLEAR_ENABLE(rb_copy_control) \ + ((rb_copy_control & RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK) >> RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT) +#define RB_COPY_CONTROL_GET_CLEAR_MASK(rb_copy_control) \ + ((rb_copy_control & RB_COPY_CONTROL_CLEAR_MASK_MASK) >> RB_COPY_CONTROL_CLEAR_MASK_SHIFT) + +#define RB_COPY_CONTROL_SET_COPY_SAMPLE_SELECT(rb_copy_control_reg, copy_sample_select) \ + rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK) | (copy_sample_select << RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT) +#define RB_COPY_CONTROL_SET_DEPTH_CLEAR_ENABLE(rb_copy_control_reg, depth_clear_enable) \ + rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK) | (depth_clear_enable << RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT) +#define RB_COPY_CONTROL_SET_CLEAR_MASK(rb_copy_control_reg, clear_mask) \ + rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_CLEAR_MASK_MASK) | (clear_mask << RB_COPY_CONTROL_CLEAR_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_control_t { + unsigned int copy_sample_select : RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE; + unsigned int depth_clear_enable : RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE; + unsigned int clear_mask : RB_COPY_CONTROL_CLEAR_MASK_SIZE; + unsigned int : 24; + } rb_copy_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_control_t { + unsigned int : 24; + unsigned int clear_mask : RB_COPY_CONTROL_CLEAR_MASK_SIZE; + unsigned int depth_clear_enable : RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE; + unsigned int copy_sample_select : RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE; + } rb_copy_control_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_control_t f; +} rb_copy_control_u; + + +/* + * RB_COPY_DEST_BASE struct + */ + +#define RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE 20 + +#define RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT 12 + +#define RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK 0xfffff000 + +#define RB_COPY_DEST_BASE_MASK \ + (RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) + +#define RB_COPY_DEST_BASE(copy_dest_base) \ + ((copy_dest_base << RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT)) + +#define RB_COPY_DEST_BASE_GET_COPY_DEST_BASE(rb_copy_dest_base) \ + ((rb_copy_dest_base & RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) >> RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT) + +#define RB_COPY_DEST_BASE_SET_COPY_DEST_BASE(rb_copy_dest_base_reg, copy_dest_base) \ + rb_copy_dest_base_reg = (rb_copy_dest_base_reg & ~RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) | (copy_dest_base << RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_dest_base_t { + unsigned int : 12; + unsigned int copy_dest_base : RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE; + } rb_copy_dest_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_dest_base_t { + unsigned int copy_dest_base : RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE; + unsigned int : 12; + } rb_copy_dest_base_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_dest_base_t f; +} rb_copy_dest_base_u; + + +/* + * RB_COPY_DEST_PITCH struct + */ + +#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE 9 + +#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT 0 + +#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK 0x000001ff + +#define RB_COPY_DEST_PITCH_MASK \ + (RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) + +#define RB_COPY_DEST_PITCH(copy_dest_pitch) \ + ((copy_dest_pitch << RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT)) + +#define RB_COPY_DEST_PITCH_GET_COPY_DEST_PITCH(rb_copy_dest_pitch) \ + ((rb_copy_dest_pitch & RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) >> RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT) + +#define RB_COPY_DEST_PITCH_SET_COPY_DEST_PITCH(rb_copy_dest_pitch_reg, copy_dest_pitch) \ + rb_copy_dest_pitch_reg = (rb_copy_dest_pitch_reg & ~RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) | (copy_dest_pitch << RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_dest_pitch_t { + unsigned int copy_dest_pitch : RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE; + unsigned int : 23; + } rb_copy_dest_pitch_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_dest_pitch_t { + unsigned int : 23; + unsigned int copy_dest_pitch : RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE; + } rb_copy_dest_pitch_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_dest_pitch_t f; +} rb_copy_dest_pitch_u; + + +/* + * RB_COPY_DEST_INFO struct + */ + +#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE 3 +#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE 1 +#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE 4 +#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE 2 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE 2 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE 2 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE 1 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE 1 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE 1 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE 1 + +#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT 0 +#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT 3 +#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT 4 +#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT 8 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT 10 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT 12 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT 14 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT 15 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT 16 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT 17 + +#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK 0x00000007 +#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK 0x00000008 +#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK 0x000000f0 +#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK 0x00000300 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK 0x00000c00 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK 0x00003000 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK 0x00004000 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK 0x00008000 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK 0x00010000 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK 0x00020000 + +#define RB_COPY_DEST_INFO_MASK \ + (RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK | \ + RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK | \ + RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK | \ + RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK | \ + RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) + +#define RB_COPY_DEST_INFO(copy_dest_endian, copy_dest_linear, copy_dest_format, copy_dest_swap, copy_dest_dither_mode, copy_dest_dither_type, copy_mask_write_red, copy_mask_write_green, copy_mask_write_blue, copy_mask_write_alpha) \ + ((copy_dest_endian << RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT) | \ + (copy_dest_linear << RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT) | \ + (copy_dest_format << RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT) | \ + (copy_dest_swap << RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT) | \ + (copy_dest_dither_mode << RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT) | \ + (copy_dest_dither_type << RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT) | \ + (copy_mask_write_red << RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT) | \ + (copy_mask_write_green << RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT) | \ + (copy_mask_write_blue << RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT) | \ + (copy_mask_write_alpha << RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT)) + +#define RB_COPY_DEST_INFO_GET_COPY_DEST_ENDIAN(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_LINEAR(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_FORMAT(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_SWAP(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_DITHER_MODE(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_DITHER_TYPE(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_RED(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_GREEN(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_BLUE(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_ALPHA(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT) + +#define RB_COPY_DEST_INFO_SET_COPY_DEST_ENDIAN(rb_copy_dest_info_reg, copy_dest_endian) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK) | (copy_dest_endian << RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_LINEAR(rb_copy_dest_info_reg, copy_dest_linear) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK) | (copy_dest_linear << RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_FORMAT(rb_copy_dest_info_reg, copy_dest_format) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK) | (copy_dest_format << RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_SWAP(rb_copy_dest_info_reg, copy_dest_swap) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK) | (copy_dest_swap << RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_DITHER_MODE(rb_copy_dest_info_reg, copy_dest_dither_mode) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK) | (copy_dest_dither_mode << RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_DITHER_TYPE(rb_copy_dest_info_reg, copy_dest_dither_type) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK) | (copy_dest_dither_type << RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_RED(rb_copy_dest_info_reg, copy_mask_write_red) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK) | (copy_mask_write_red << RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_GREEN(rb_copy_dest_info_reg, copy_mask_write_green) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK) | (copy_mask_write_green << RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_BLUE(rb_copy_dest_info_reg, copy_mask_write_blue) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK) | (copy_mask_write_blue << RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_ALPHA(rb_copy_dest_info_reg, copy_mask_write_alpha) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) | (copy_mask_write_alpha << RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_dest_info_t { + unsigned int copy_dest_endian : RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE; + unsigned int copy_dest_linear : RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE; + unsigned int copy_dest_format : RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE; + unsigned int copy_dest_swap : RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE; + unsigned int copy_dest_dither_mode : RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE; + unsigned int copy_dest_dither_type : RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE; + unsigned int copy_mask_write_red : RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE; + unsigned int copy_mask_write_green : RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE; + unsigned int copy_mask_write_blue : RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE; + unsigned int copy_mask_write_alpha : RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE; + unsigned int : 14; + } rb_copy_dest_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_dest_info_t { + unsigned int : 14; + unsigned int copy_mask_write_alpha : RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE; + unsigned int copy_mask_write_blue : RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE; + unsigned int copy_mask_write_green : RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE; + unsigned int copy_mask_write_red : RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE; + unsigned int copy_dest_dither_type : RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE; + unsigned int copy_dest_dither_mode : RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE; + unsigned int copy_dest_swap : RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE; + unsigned int copy_dest_format : RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE; + unsigned int copy_dest_linear : RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE; + unsigned int copy_dest_endian : RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE; + } rb_copy_dest_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_dest_info_t f; +} rb_copy_dest_info_u; + + +/* + * RB_COPY_DEST_PIXEL_OFFSET struct + */ + +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE 13 +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE 13 + +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT 0 +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT 13 + +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK 0x00001fff +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK 0x03ffe000 + +#define RB_COPY_DEST_PIXEL_OFFSET_MASK \ + (RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK | \ + RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) + +#define RB_COPY_DEST_PIXEL_OFFSET(offset_x, offset_y) \ + ((offset_x << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT) | \ + (offset_y << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT)) + +#define RB_COPY_DEST_PIXEL_OFFSET_GET_OFFSET_X(rb_copy_dest_pixel_offset) \ + ((rb_copy_dest_pixel_offset & RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK) >> RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT) +#define RB_COPY_DEST_PIXEL_OFFSET_GET_OFFSET_Y(rb_copy_dest_pixel_offset) \ + ((rb_copy_dest_pixel_offset & RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) >> RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT) + +#define RB_COPY_DEST_PIXEL_OFFSET_SET_OFFSET_X(rb_copy_dest_pixel_offset_reg, offset_x) \ + rb_copy_dest_pixel_offset_reg = (rb_copy_dest_pixel_offset_reg & ~RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK) | (offset_x << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT) +#define RB_COPY_DEST_PIXEL_OFFSET_SET_OFFSET_Y(rb_copy_dest_pixel_offset_reg, offset_y) \ + rb_copy_dest_pixel_offset_reg = (rb_copy_dest_pixel_offset_reg & ~RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) | (offset_y << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_dest_pixel_offset_t { + unsigned int offset_x : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE; + unsigned int offset_y : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE; + unsigned int : 6; + } rb_copy_dest_pixel_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_dest_pixel_offset_t { + unsigned int : 6; + unsigned int offset_y : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE; + unsigned int offset_x : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE; + } rb_copy_dest_pixel_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_dest_pixel_offset_t f; +} rb_copy_dest_pixel_offset_u; + + +/* + * RB_DEPTH_CLEAR struct + */ + +#define RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE 32 + +#define RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT 0 + +#define RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK 0xffffffff + +#define RB_DEPTH_CLEAR_MASK \ + (RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) + +#define RB_DEPTH_CLEAR(depth_clear) \ + ((depth_clear << RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT)) + +#define RB_DEPTH_CLEAR_GET_DEPTH_CLEAR(rb_depth_clear) \ + ((rb_depth_clear & RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) >> RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT) + +#define RB_DEPTH_CLEAR_SET_DEPTH_CLEAR(rb_depth_clear_reg, depth_clear) \ + rb_depth_clear_reg = (rb_depth_clear_reg & ~RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) | (depth_clear << RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_depth_clear_t { + unsigned int depth_clear : RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE; + } rb_depth_clear_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_depth_clear_t { + unsigned int depth_clear : RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE; + } rb_depth_clear_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_depth_clear_t f; +} rb_depth_clear_u; + + +/* + * RB_SAMPLE_COUNT_CTL struct + */ + +#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE 1 +#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE 1 + +#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT 0 +#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT 1 + +#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK 0x00000001 +#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK 0x00000002 + +#define RB_SAMPLE_COUNT_CTL_MASK \ + (RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK | \ + RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) + +#define RB_SAMPLE_COUNT_CTL(reset_sample_count, copy_sample_count) \ + ((reset_sample_count << RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT) | \ + (copy_sample_count << RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT)) + +#define RB_SAMPLE_COUNT_CTL_GET_RESET_SAMPLE_COUNT(rb_sample_count_ctl) \ + ((rb_sample_count_ctl & RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK) >> RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT) +#define RB_SAMPLE_COUNT_CTL_GET_COPY_SAMPLE_COUNT(rb_sample_count_ctl) \ + ((rb_sample_count_ctl & RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) >> RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT) + +#define RB_SAMPLE_COUNT_CTL_SET_RESET_SAMPLE_COUNT(rb_sample_count_ctl_reg, reset_sample_count) \ + rb_sample_count_ctl_reg = (rb_sample_count_ctl_reg & ~RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK) | (reset_sample_count << RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT) +#define RB_SAMPLE_COUNT_CTL_SET_COPY_SAMPLE_COUNT(rb_sample_count_ctl_reg, copy_sample_count) \ + rb_sample_count_ctl_reg = (rb_sample_count_ctl_reg & ~RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) | (copy_sample_count << RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_sample_count_ctl_t { + unsigned int reset_sample_count : RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE; + unsigned int copy_sample_count : RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE; + unsigned int : 30; + } rb_sample_count_ctl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_sample_count_ctl_t { + unsigned int : 30; + unsigned int copy_sample_count : RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE; + unsigned int reset_sample_count : RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE; + } rb_sample_count_ctl_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_sample_count_ctl_t f; +} rb_sample_count_ctl_u; + + +/* + * RB_SAMPLE_COUNT_ADDR struct + */ + +#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE 32 + +#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT 0 + +#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK 0xffffffff + +#define RB_SAMPLE_COUNT_ADDR_MASK \ + (RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) + +#define RB_SAMPLE_COUNT_ADDR(sample_count_addr) \ + ((sample_count_addr << RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT)) + +#define RB_SAMPLE_COUNT_ADDR_GET_SAMPLE_COUNT_ADDR(rb_sample_count_addr) \ + ((rb_sample_count_addr & RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) >> RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT) + +#define RB_SAMPLE_COUNT_ADDR_SET_SAMPLE_COUNT_ADDR(rb_sample_count_addr_reg, sample_count_addr) \ + rb_sample_count_addr_reg = (rb_sample_count_addr_reg & ~RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) | (sample_count_addr << RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_sample_count_addr_t { + unsigned int sample_count_addr : RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE; + } rb_sample_count_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_sample_count_addr_t { + unsigned int sample_count_addr : RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE; + } rb_sample_count_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_sample_count_addr_t f; +} rb_sample_count_addr_u; + + +/* + * RB_BC_CONTROL struct + */ + +#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE 1 +#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE 2 +#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE 1 +#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE 1 +#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE 1 +#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE 1 +#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE 1 +#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE 5 +#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE 1 +#define RB_BC_CONTROL_CRC_MODE_SIZE 1 +#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE 1 +#define RB_BC_CONTROL_DISABLE_ACCUM_SIZE 1 +#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE 4 +#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE 1 +#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE 4 +#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE 2 +#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE 1 +#define RB_BC_CONTROL_CRC_SYSTEM_SIZE 1 +#define RB_BC_CONTROL_RESERVED6_SIZE 1 + +#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT 0 +#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT 1 +#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT 3 +#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT 4 +#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT 5 +#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT 6 +#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT 7 +#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT 8 +#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT 14 +#define RB_BC_CONTROL_CRC_MODE_SHIFT 15 +#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT 16 +#define RB_BC_CONTROL_DISABLE_ACCUM_SHIFT 17 +#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT 18 +#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT 22 +#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT 23 +#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT 27 +#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT 29 +#define RB_BC_CONTROL_CRC_SYSTEM_SHIFT 30 +#define RB_BC_CONTROL_RESERVED6_SHIFT 31 + +#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK 0x00000001 +#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK 0x00000006 +#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK 0x00000008 +#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK 0x00000010 +#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK 0x00000020 +#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK 0x00000040 +#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK 0x00000080 +#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK 0x00001f00 +#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK 0x00004000 +#define RB_BC_CONTROL_CRC_MODE_MASK 0x00008000 +#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK 0x00010000 +#define RB_BC_CONTROL_DISABLE_ACCUM_MASK 0x00020000 +#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK 0x003c0000 +#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK 0x00400000 +#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK 0x07800000 +#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK 0x18000000 +#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK 0x20000000 +#define RB_BC_CONTROL_CRC_SYSTEM_MASK 0x40000000 +#define RB_BC_CONTROL_RESERVED6_MASK 0x80000000 + +#define RB_BC_CONTROL_MASK \ + (RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK | \ + RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK | \ + RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK | \ + RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK | \ + RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK | \ + RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK | \ + RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK | \ + RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK | \ + RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK | \ + RB_BC_CONTROL_CRC_MODE_MASK | \ + RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK | \ + RB_BC_CONTROL_DISABLE_ACCUM_MASK | \ + RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK | \ + RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK | \ + RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK | \ + RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK | \ + RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK | \ + RB_BC_CONTROL_CRC_SYSTEM_MASK | \ + RB_BC_CONTROL_RESERVED6_MASK) + +#define RB_BC_CONTROL(accum_linear_mode_enable, accum_timeout_select, disable_edram_cam, disable_ez_fast_context_switch, disable_ez_null_zcmd_drop, disable_lz_null_zcmd_drop, enable_az_throttle, az_throttle_count, enable_crc_update, crc_mode, disable_sample_counters, disable_accum, accum_alloc_mask, linear_performance_enable, accum_data_fifo_limit, mem_export_timeout_select, mem_export_linear_mode_enable, crc_system, reserved6) \ + ((accum_linear_mode_enable << RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT) | \ + (accum_timeout_select << RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT) | \ + (disable_edram_cam << RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT) | \ + (disable_ez_fast_context_switch << RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT) | \ + (disable_ez_null_zcmd_drop << RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT) | \ + (disable_lz_null_zcmd_drop << RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT) | \ + (enable_az_throttle << RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT) | \ + (az_throttle_count << RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT) | \ + (enable_crc_update << RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT) | \ + (crc_mode << RB_BC_CONTROL_CRC_MODE_SHIFT) | \ + (disable_sample_counters << RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT) | \ + (disable_accum << RB_BC_CONTROL_DISABLE_ACCUM_SHIFT) | \ + (accum_alloc_mask << RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT) | \ + (linear_performance_enable << RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT) | \ + (accum_data_fifo_limit << RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT) | \ + (mem_export_timeout_select << RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT) | \ + (mem_export_linear_mode_enable << RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT) | \ + (crc_system << RB_BC_CONTROL_CRC_SYSTEM_SHIFT) | \ + (reserved6 << RB_BC_CONTROL_RESERVED6_SHIFT)) + +#define RB_BC_CONTROL_GET_ACCUM_LINEAR_MODE_ENABLE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK) >> RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT) +#define RB_BC_CONTROL_GET_ACCUM_TIMEOUT_SELECT(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK) >> RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_EDRAM_CAM(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK) >> RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_EZ_FAST_CONTEXT_SWITCH(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK) >> RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_EZ_NULL_ZCMD_DROP(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK) >> RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_LZ_NULL_ZCMD_DROP(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK) >> RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT) +#define RB_BC_CONTROL_GET_ENABLE_AZ_THROTTLE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK) >> RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT) +#define RB_BC_CONTROL_GET_AZ_THROTTLE_COUNT(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK) >> RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT) +#define RB_BC_CONTROL_GET_ENABLE_CRC_UPDATE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK) >> RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT) +#define RB_BC_CONTROL_GET_CRC_MODE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_CRC_MODE_MASK) >> RB_BC_CONTROL_CRC_MODE_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_SAMPLE_COUNTERS(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK) >> RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_ACCUM(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_ACCUM_MASK) >> RB_BC_CONTROL_DISABLE_ACCUM_SHIFT) +#define RB_BC_CONTROL_GET_ACCUM_ALLOC_MASK(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK) >> RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT) +#define RB_BC_CONTROL_GET_LINEAR_PERFORMANCE_ENABLE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK) >> RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT) +#define RB_BC_CONTROL_GET_ACCUM_DATA_FIFO_LIMIT(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK) >> RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT) +#define RB_BC_CONTROL_GET_MEM_EXPORT_TIMEOUT_SELECT(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK) >> RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT) +#define RB_BC_CONTROL_GET_MEM_EXPORT_LINEAR_MODE_ENABLE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK) >> RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT) +#define RB_BC_CONTROL_GET_CRC_SYSTEM(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_CRC_SYSTEM_MASK) >> RB_BC_CONTROL_CRC_SYSTEM_SHIFT) +#define RB_BC_CONTROL_GET_RESERVED6(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_RESERVED6_MASK) >> RB_BC_CONTROL_RESERVED6_SHIFT) + +#define RB_BC_CONTROL_SET_ACCUM_LINEAR_MODE_ENABLE(rb_bc_control_reg, accum_linear_mode_enable) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK) | (accum_linear_mode_enable << RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT) +#define RB_BC_CONTROL_SET_ACCUM_TIMEOUT_SELECT(rb_bc_control_reg, accum_timeout_select) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK) | (accum_timeout_select << RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_EDRAM_CAM(rb_bc_control_reg, disable_edram_cam) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK) | (disable_edram_cam << RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_EZ_FAST_CONTEXT_SWITCH(rb_bc_control_reg, disable_ez_fast_context_switch) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK) | (disable_ez_fast_context_switch << RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_EZ_NULL_ZCMD_DROP(rb_bc_control_reg, disable_ez_null_zcmd_drop) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK) | (disable_ez_null_zcmd_drop << RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_LZ_NULL_ZCMD_DROP(rb_bc_control_reg, disable_lz_null_zcmd_drop) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK) | (disable_lz_null_zcmd_drop << RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT) +#define RB_BC_CONTROL_SET_ENABLE_AZ_THROTTLE(rb_bc_control_reg, enable_az_throttle) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK) | (enable_az_throttle << RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT) +#define RB_BC_CONTROL_SET_AZ_THROTTLE_COUNT(rb_bc_control_reg, az_throttle_count) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK) | (az_throttle_count << RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT) +#define RB_BC_CONTROL_SET_ENABLE_CRC_UPDATE(rb_bc_control_reg, enable_crc_update) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK) | (enable_crc_update << RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT) +#define RB_BC_CONTROL_SET_CRC_MODE(rb_bc_control_reg, crc_mode) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_CRC_MODE_MASK) | (crc_mode << RB_BC_CONTROL_CRC_MODE_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_SAMPLE_COUNTERS(rb_bc_control_reg, disable_sample_counters) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK) | (disable_sample_counters << RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_ACCUM(rb_bc_control_reg, disable_accum) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_ACCUM_MASK) | (disable_accum << RB_BC_CONTROL_DISABLE_ACCUM_SHIFT) +#define RB_BC_CONTROL_SET_ACCUM_ALLOC_MASK(rb_bc_control_reg, accum_alloc_mask) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK) | (accum_alloc_mask << RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT) +#define RB_BC_CONTROL_SET_LINEAR_PERFORMANCE_ENABLE(rb_bc_control_reg, linear_performance_enable) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK) | (linear_performance_enable << RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT) +#define RB_BC_CONTROL_SET_ACCUM_DATA_FIFO_LIMIT(rb_bc_control_reg, accum_data_fifo_limit) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK) | (accum_data_fifo_limit << RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT) +#define RB_BC_CONTROL_SET_MEM_EXPORT_TIMEOUT_SELECT(rb_bc_control_reg, mem_export_timeout_select) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK) | (mem_export_timeout_select << RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT) +#define RB_BC_CONTROL_SET_MEM_EXPORT_LINEAR_MODE_ENABLE(rb_bc_control_reg, mem_export_linear_mode_enable) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK) | (mem_export_linear_mode_enable << RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT) +#define RB_BC_CONTROL_SET_CRC_SYSTEM(rb_bc_control_reg, crc_system) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_CRC_SYSTEM_MASK) | (crc_system << RB_BC_CONTROL_CRC_SYSTEM_SHIFT) +#define RB_BC_CONTROL_SET_RESERVED6(rb_bc_control_reg, reserved6) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_RESERVED6_MASK) | (reserved6 << RB_BC_CONTROL_RESERVED6_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_bc_control_t { + unsigned int accum_linear_mode_enable : RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE; + unsigned int accum_timeout_select : RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE; + unsigned int disable_edram_cam : RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE; + unsigned int disable_ez_fast_context_switch : RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE; + unsigned int disable_ez_null_zcmd_drop : RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE; + unsigned int disable_lz_null_zcmd_drop : RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE; + unsigned int enable_az_throttle : RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE; + unsigned int az_throttle_count : RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE; + unsigned int : 1; + unsigned int enable_crc_update : RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE; + unsigned int crc_mode : RB_BC_CONTROL_CRC_MODE_SIZE; + unsigned int disable_sample_counters : RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE; + unsigned int disable_accum : RB_BC_CONTROL_DISABLE_ACCUM_SIZE; + unsigned int accum_alloc_mask : RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE; + unsigned int linear_performance_enable : RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE; + unsigned int accum_data_fifo_limit : RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE; + unsigned int mem_export_timeout_select : RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE; + unsigned int mem_export_linear_mode_enable : RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE; + unsigned int crc_system : RB_BC_CONTROL_CRC_SYSTEM_SIZE; + unsigned int reserved6 : RB_BC_CONTROL_RESERVED6_SIZE; + } rb_bc_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_bc_control_t { + unsigned int reserved6 : RB_BC_CONTROL_RESERVED6_SIZE; + unsigned int crc_system : RB_BC_CONTROL_CRC_SYSTEM_SIZE; + unsigned int mem_export_linear_mode_enable : RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE; + unsigned int mem_export_timeout_select : RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE; + unsigned int accum_data_fifo_limit : RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE; + unsigned int linear_performance_enable : RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE; + unsigned int accum_alloc_mask : RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE; + unsigned int disable_accum : RB_BC_CONTROL_DISABLE_ACCUM_SIZE; + unsigned int disable_sample_counters : RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE; + unsigned int crc_mode : RB_BC_CONTROL_CRC_MODE_SIZE; + unsigned int enable_crc_update : RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE; + unsigned int : 1; + unsigned int az_throttle_count : RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE; + unsigned int enable_az_throttle : RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE; + unsigned int disable_lz_null_zcmd_drop : RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE; + unsigned int disable_ez_null_zcmd_drop : RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE; + unsigned int disable_ez_fast_context_switch : RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE; + unsigned int disable_edram_cam : RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE; + unsigned int accum_timeout_select : RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE; + unsigned int accum_linear_mode_enable : RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE; + } rb_bc_control_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_bc_control_t f; +} rb_bc_control_u; + + +/* + * RB_EDRAM_INFO struct + */ + +#define RB_EDRAM_INFO_EDRAM_SIZE_SIZE 4 +#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE 2 +#define RB_EDRAM_INFO_EDRAM_RANGE_SIZE 18 + +#define RB_EDRAM_INFO_EDRAM_SIZE_SHIFT 0 +#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT 4 +#define RB_EDRAM_INFO_EDRAM_RANGE_SHIFT 14 + +#define RB_EDRAM_INFO_EDRAM_SIZE_MASK 0x0000000f +#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK 0x00000030 +#define RB_EDRAM_INFO_EDRAM_RANGE_MASK 0xffffc000 + +#define RB_EDRAM_INFO_MASK \ + (RB_EDRAM_INFO_EDRAM_SIZE_MASK | \ + RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK | \ + RB_EDRAM_INFO_EDRAM_RANGE_MASK) + +#define RB_EDRAM_INFO(edram_size, edram_mapping_mode, edram_range) \ + ((edram_size << RB_EDRAM_INFO_EDRAM_SIZE_SHIFT) | \ + (edram_mapping_mode << RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT) | \ + (edram_range << RB_EDRAM_INFO_EDRAM_RANGE_SHIFT)) + +#define RB_EDRAM_INFO_GET_EDRAM_SIZE(rb_edram_info) \ + ((rb_edram_info & RB_EDRAM_INFO_EDRAM_SIZE_MASK) >> RB_EDRAM_INFO_EDRAM_SIZE_SHIFT) +#define RB_EDRAM_INFO_GET_EDRAM_MAPPING_MODE(rb_edram_info) \ + ((rb_edram_info & RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK) >> RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT) +#define RB_EDRAM_INFO_GET_EDRAM_RANGE(rb_edram_info) \ + ((rb_edram_info & RB_EDRAM_INFO_EDRAM_RANGE_MASK) >> RB_EDRAM_INFO_EDRAM_RANGE_SHIFT) + +#define RB_EDRAM_INFO_SET_EDRAM_SIZE(rb_edram_info_reg, edram_size) \ + rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_SIZE_MASK) | (edram_size << RB_EDRAM_INFO_EDRAM_SIZE_SHIFT) +#define RB_EDRAM_INFO_SET_EDRAM_MAPPING_MODE(rb_edram_info_reg, edram_mapping_mode) \ + rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK) | (edram_mapping_mode << RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT) +#define RB_EDRAM_INFO_SET_EDRAM_RANGE(rb_edram_info_reg, edram_range) \ + rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_RANGE_MASK) | (edram_range << RB_EDRAM_INFO_EDRAM_RANGE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_edram_info_t { + unsigned int edram_size : RB_EDRAM_INFO_EDRAM_SIZE_SIZE; + unsigned int edram_mapping_mode : RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE; + unsigned int : 8; + unsigned int edram_range : RB_EDRAM_INFO_EDRAM_RANGE_SIZE; + } rb_edram_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_edram_info_t { + unsigned int edram_range : RB_EDRAM_INFO_EDRAM_RANGE_SIZE; + unsigned int : 8; + unsigned int edram_mapping_mode : RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE; + unsigned int edram_size : RB_EDRAM_INFO_EDRAM_SIZE_SIZE; + } rb_edram_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_edram_info_t f; +} rb_edram_info_u; + + +/* + * RB_CRC_RD_PORT struct + */ + +#define RB_CRC_RD_PORT_CRC_DATA_SIZE 32 + +#define RB_CRC_RD_PORT_CRC_DATA_SHIFT 0 + +#define RB_CRC_RD_PORT_CRC_DATA_MASK 0xffffffff + +#define RB_CRC_RD_PORT_MASK \ + (RB_CRC_RD_PORT_CRC_DATA_MASK) + +#define RB_CRC_RD_PORT(crc_data) \ + ((crc_data << RB_CRC_RD_PORT_CRC_DATA_SHIFT)) + +#define RB_CRC_RD_PORT_GET_CRC_DATA(rb_crc_rd_port) \ + ((rb_crc_rd_port & RB_CRC_RD_PORT_CRC_DATA_MASK) >> RB_CRC_RD_PORT_CRC_DATA_SHIFT) + +#define RB_CRC_RD_PORT_SET_CRC_DATA(rb_crc_rd_port_reg, crc_data) \ + rb_crc_rd_port_reg = (rb_crc_rd_port_reg & ~RB_CRC_RD_PORT_CRC_DATA_MASK) | (crc_data << RB_CRC_RD_PORT_CRC_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_crc_rd_port_t { + unsigned int crc_data : RB_CRC_RD_PORT_CRC_DATA_SIZE; + } rb_crc_rd_port_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_crc_rd_port_t { + unsigned int crc_data : RB_CRC_RD_PORT_CRC_DATA_SIZE; + } rb_crc_rd_port_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_crc_rd_port_t f; +} rb_crc_rd_port_u; + + +/* + * RB_CRC_CONTROL struct + */ + +#define RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE 1 + +#define RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT 0 + +#define RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK 0x00000001 + +#define RB_CRC_CONTROL_MASK \ + (RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) + +#define RB_CRC_CONTROL(crc_rd_advance) \ + ((crc_rd_advance << RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT)) + +#define RB_CRC_CONTROL_GET_CRC_RD_ADVANCE(rb_crc_control) \ + ((rb_crc_control & RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) >> RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT) + +#define RB_CRC_CONTROL_SET_CRC_RD_ADVANCE(rb_crc_control_reg, crc_rd_advance) \ + rb_crc_control_reg = (rb_crc_control_reg & ~RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) | (crc_rd_advance << RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_crc_control_t { + unsigned int crc_rd_advance : RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE; + unsigned int : 31; + } rb_crc_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_crc_control_t { + unsigned int : 31; + unsigned int crc_rd_advance : RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE; + } rb_crc_control_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_crc_control_t f; +} rb_crc_control_u; + + +/* + * RB_CRC_MASK struct + */ + +#define RB_CRC_MASK_CRC_MASK_SIZE 32 + +#define RB_CRC_MASK_CRC_MASK_SHIFT 0 + +#define RB_CRC_MASK_CRC_MASK_MASK 0xffffffff + +#define RB_CRC_MASK_MASK \ + (RB_CRC_MASK_CRC_MASK_MASK) + +#define RB_CRC_MASK(crc_mask) \ + ((crc_mask << RB_CRC_MASK_CRC_MASK_SHIFT)) + +#define RB_CRC_MASK_GET_CRC_MASK(rb_crc_mask) \ + ((rb_crc_mask & RB_CRC_MASK_CRC_MASK_MASK) >> RB_CRC_MASK_CRC_MASK_SHIFT) + +#define RB_CRC_MASK_SET_CRC_MASK(rb_crc_mask_reg, crc_mask) \ + rb_crc_mask_reg = (rb_crc_mask_reg & ~RB_CRC_MASK_CRC_MASK_MASK) | (crc_mask << RB_CRC_MASK_CRC_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_crc_mask_t { + unsigned int crc_mask : RB_CRC_MASK_CRC_MASK_SIZE; + } rb_crc_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_crc_mask_t { + unsigned int crc_mask : RB_CRC_MASK_CRC_MASK_SIZE; + } rb_crc_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_crc_mask_t f; +} rb_crc_mask_u; + + +/* + * RB_PERFCOUNTER0_SELECT struct + */ + +#define RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define RB_PERFCOUNTER0_SELECT_MASK \ + (RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define RB_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define RB_PERFCOUNTER0_SELECT_GET_PERF_SEL(rb_perfcounter0_select) \ + ((rb_perfcounter0_select & RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define RB_PERFCOUNTER0_SELECT_SET_PERF_SEL(rb_perfcounter0_select_reg, perf_sel) \ + rb_perfcounter0_select_reg = (rb_perfcounter0_select_reg & ~RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_perfcounter0_select_t { + unsigned int perf_sel : RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } rb_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } rb_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_perfcounter0_select_t f; +} rb_perfcounter0_select_u; + + +/* + * RB_PERFCOUNTER0_LOW struct + */ + +#define RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define RB_PERFCOUNTER0_LOW_MASK \ + (RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define RB_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define RB_PERFCOUNTER0_LOW_GET_PERF_COUNT(rb_perfcounter0_low) \ + ((rb_perfcounter0_low & RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define RB_PERFCOUNTER0_LOW_SET_PERF_COUNT(rb_perfcounter0_low_reg, perf_count) \ + rb_perfcounter0_low_reg = (rb_perfcounter0_low_reg & ~RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_perfcounter0_low_t { + unsigned int perf_count : RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } rb_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_perfcounter0_low_t { + unsigned int perf_count : RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } rb_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_perfcounter0_low_t f; +} rb_perfcounter0_low_u; + + +/* + * RB_PERFCOUNTER0_HI struct + */ + +#define RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define RB_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define RB_PERFCOUNTER0_HI_MASK \ + (RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define RB_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define RB_PERFCOUNTER0_HI_GET_PERF_COUNT(rb_perfcounter0_hi) \ + ((rb_perfcounter0_hi & RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define RB_PERFCOUNTER0_HI_SET_PERF_COUNT(rb_perfcounter0_hi_reg, perf_count) \ + rb_perfcounter0_hi_reg = (rb_perfcounter0_hi_reg & ~RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_perfcounter0_hi_t { + unsigned int perf_count : RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } rb_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } rb_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_perfcounter0_hi_t f; +} rb_perfcounter0_hi_u; + + +/* + * RB_TOTAL_SAMPLES struct + */ + +#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE 32 + +#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT 0 + +#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK 0xffffffff + +#define RB_TOTAL_SAMPLES_MASK \ + (RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) + +#define RB_TOTAL_SAMPLES(total_samples) \ + ((total_samples << RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT)) + +#define RB_TOTAL_SAMPLES_GET_TOTAL_SAMPLES(rb_total_samples) \ + ((rb_total_samples & RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) >> RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT) + +#define RB_TOTAL_SAMPLES_SET_TOTAL_SAMPLES(rb_total_samples_reg, total_samples) \ + rb_total_samples_reg = (rb_total_samples_reg & ~RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) | (total_samples << RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_total_samples_t { + unsigned int total_samples : RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE; + } rb_total_samples_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_total_samples_t { + unsigned int total_samples : RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE; + } rb_total_samples_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_total_samples_t f; +} rb_total_samples_u; + + +/* + * RB_ZPASS_SAMPLES struct + */ + +#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE 32 + +#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT 0 + +#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK 0xffffffff + +#define RB_ZPASS_SAMPLES_MASK \ + (RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) + +#define RB_ZPASS_SAMPLES(zpass_samples) \ + ((zpass_samples << RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT)) + +#define RB_ZPASS_SAMPLES_GET_ZPASS_SAMPLES(rb_zpass_samples) \ + ((rb_zpass_samples & RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) >> RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT) + +#define RB_ZPASS_SAMPLES_SET_ZPASS_SAMPLES(rb_zpass_samples_reg, zpass_samples) \ + rb_zpass_samples_reg = (rb_zpass_samples_reg & ~RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) | (zpass_samples << RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_zpass_samples_t { + unsigned int zpass_samples : RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE; + } rb_zpass_samples_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_zpass_samples_t { + unsigned int zpass_samples : RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE; + } rb_zpass_samples_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_zpass_samples_t f; +} rb_zpass_samples_u; + + +/* + * RB_ZFAIL_SAMPLES struct + */ + +#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE 32 + +#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT 0 + +#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK 0xffffffff + +#define RB_ZFAIL_SAMPLES_MASK \ + (RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) + +#define RB_ZFAIL_SAMPLES(zfail_samples) \ + ((zfail_samples << RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT)) + +#define RB_ZFAIL_SAMPLES_GET_ZFAIL_SAMPLES(rb_zfail_samples) \ + ((rb_zfail_samples & RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) >> RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT) + +#define RB_ZFAIL_SAMPLES_SET_ZFAIL_SAMPLES(rb_zfail_samples_reg, zfail_samples) \ + rb_zfail_samples_reg = (rb_zfail_samples_reg & ~RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) | (zfail_samples << RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_zfail_samples_t { + unsigned int zfail_samples : RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE; + } rb_zfail_samples_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_zfail_samples_t { + unsigned int zfail_samples : RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE; + } rb_zfail_samples_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_zfail_samples_t f; +} rb_zfail_samples_u; + + +/* + * RB_SFAIL_SAMPLES struct + */ + +#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE 32 + +#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT 0 + +#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK 0xffffffff + +#define RB_SFAIL_SAMPLES_MASK \ + (RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) + +#define RB_SFAIL_SAMPLES(sfail_samples) \ + ((sfail_samples << RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT)) + +#define RB_SFAIL_SAMPLES_GET_SFAIL_SAMPLES(rb_sfail_samples) \ + ((rb_sfail_samples & RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) >> RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT) + +#define RB_SFAIL_SAMPLES_SET_SFAIL_SAMPLES(rb_sfail_samples_reg, sfail_samples) \ + rb_sfail_samples_reg = (rb_sfail_samples_reg & ~RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) | (sfail_samples << RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_sfail_samples_t { + unsigned int sfail_samples : RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE; + } rb_sfail_samples_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_sfail_samples_t { + unsigned int sfail_samples : RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE; + } rb_sfail_samples_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_sfail_samples_t f; +} rb_sfail_samples_u; + + +/* + * RB_DEBUG_0 struct + */ + +#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_Z1_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_Z0_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_C1_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_C0_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_Z1_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_Z0_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_C1_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_C0_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE 1 +#define RB_DEBUG_0_C_SX_LAT_FULL_SIZE 1 +#define RB_DEBUG_0_C_SX_CMD_FULL_SIZE 1 +#define RB_DEBUG_0_C_EZ_TILE_FULL_SIZE 1 +#define RB_DEBUG_0_C_REQ_FULL_SIZE 1 +#define RB_DEBUG_0_C_MASK_FULL_SIZE 1 +#define RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE 1 + +#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT 0 +#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT 1 +#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT 2 +#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT 3 +#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT 4 +#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT 5 +#define RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT 6 +#define RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT 7 +#define RB_DEBUG_0_RDREQ_C1_FULL_SHIFT 8 +#define RB_DEBUG_0_RDREQ_C0_FULL_SHIFT 9 +#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT 10 +#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT 11 +#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT 12 +#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT 13 +#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT 14 +#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT 15 +#define RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT 16 +#define RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT 17 +#define RB_DEBUG_0_WRREQ_C1_FULL_SHIFT 18 +#define RB_DEBUG_0_WRREQ_C0_FULL_SHIFT 19 +#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT 20 +#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT 21 +#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT 22 +#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT 23 +#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT 24 +#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT 25 +#define RB_DEBUG_0_C_SX_LAT_FULL_SHIFT 26 +#define RB_DEBUG_0_C_SX_CMD_FULL_SHIFT 27 +#define RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT 28 +#define RB_DEBUG_0_C_REQ_FULL_SHIFT 29 +#define RB_DEBUG_0_C_MASK_FULL_SHIFT 30 +#define RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT 31 + +#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK 0x00000001 +#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK 0x00000002 +#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK 0x00000004 +#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK 0x00000008 +#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK 0x00000010 +#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK 0x00000020 +#define RB_DEBUG_0_RDREQ_Z1_FULL_MASK 0x00000040 +#define RB_DEBUG_0_RDREQ_Z0_FULL_MASK 0x00000080 +#define RB_DEBUG_0_RDREQ_C1_FULL_MASK 0x00000100 +#define RB_DEBUG_0_RDREQ_C0_FULL_MASK 0x00000200 +#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK 0x00000400 +#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK 0x00000800 +#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK 0x00001000 +#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK 0x00002000 +#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK 0x00004000 +#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK 0x00008000 +#define RB_DEBUG_0_WRREQ_Z1_FULL_MASK 0x00010000 +#define RB_DEBUG_0_WRREQ_Z0_FULL_MASK 0x00020000 +#define RB_DEBUG_0_WRREQ_C1_FULL_MASK 0x00040000 +#define RB_DEBUG_0_WRREQ_C0_FULL_MASK 0x00080000 +#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK 0x00100000 +#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK 0x00200000 +#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK 0x00400000 +#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK 0x00800000 +#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK 0x01000000 +#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK 0x02000000 +#define RB_DEBUG_0_C_SX_LAT_FULL_MASK 0x04000000 +#define RB_DEBUG_0_C_SX_CMD_FULL_MASK 0x08000000 +#define RB_DEBUG_0_C_EZ_TILE_FULL_MASK 0x10000000 +#define RB_DEBUG_0_C_REQ_FULL_MASK 0x20000000 +#define RB_DEBUG_0_C_MASK_FULL_MASK 0x40000000 +#define RB_DEBUG_0_EZ_INFSAMP_FULL_MASK 0x80000000 + +#define RB_DEBUG_0_MASK \ + (RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK | \ + RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK | \ + RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK | \ + RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK | \ + RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK | \ + RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK | \ + RB_DEBUG_0_RDREQ_Z1_FULL_MASK | \ + RB_DEBUG_0_RDREQ_Z0_FULL_MASK | \ + RB_DEBUG_0_RDREQ_C1_FULL_MASK | \ + RB_DEBUG_0_RDREQ_C0_FULL_MASK | \ + RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK | \ + RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK | \ + RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK | \ + RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK | \ + RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK | \ + RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK | \ + RB_DEBUG_0_WRREQ_Z1_FULL_MASK | \ + RB_DEBUG_0_WRREQ_Z0_FULL_MASK | \ + RB_DEBUG_0_WRREQ_C1_FULL_MASK | \ + RB_DEBUG_0_WRREQ_C0_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK | \ + RB_DEBUG_0_C_SX_LAT_FULL_MASK | \ + RB_DEBUG_0_C_SX_CMD_FULL_MASK | \ + RB_DEBUG_0_C_EZ_TILE_FULL_MASK | \ + RB_DEBUG_0_C_REQ_FULL_MASK | \ + RB_DEBUG_0_C_MASK_FULL_MASK | \ + RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) + +#define RB_DEBUG_0(rdreq_ctl_z1_pre_full, rdreq_ctl_z0_pre_full, rdreq_ctl_c1_pre_full, rdreq_ctl_c0_pre_full, rdreq_e1_ordering_full, rdreq_e0_ordering_full, rdreq_z1_full, rdreq_z0_full, rdreq_c1_full, rdreq_c0_full, wrreq_e1_macro_hi_full, wrreq_e1_macro_lo_full, wrreq_e0_macro_hi_full, wrreq_e0_macro_lo_full, wrreq_c_we_hi_full, wrreq_c_we_lo_full, wrreq_z1_full, wrreq_z0_full, wrreq_c1_full, wrreq_c0_full, cmdfifo_z1_hold_full, cmdfifo_z0_hold_full, cmdfifo_c1_hold_full, cmdfifo_c0_hold_full, cmdfifo_z_ordering_full, cmdfifo_c_ordering_full, c_sx_lat_full, c_sx_cmd_full, c_ez_tile_full, c_req_full, c_mask_full, ez_infsamp_full) \ + ((rdreq_ctl_z1_pre_full << RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT) | \ + (rdreq_ctl_z0_pre_full << RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT) | \ + (rdreq_ctl_c1_pre_full << RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT) | \ + (rdreq_ctl_c0_pre_full << RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT) | \ + (rdreq_e1_ordering_full << RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT) | \ + (rdreq_e0_ordering_full << RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT) | \ + (rdreq_z1_full << RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT) | \ + (rdreq_z0_full << RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT) | \ + (rdreq_c1_full << RB_DEBUG_0_RDREQ_C1_FULL_SHIFT) | \ + (rdreq_c0_full << RB_DEBUG_0_RDREQ_C0_FULL_SHIFT) | \ + (wrreq_e1_macro_hi_full << RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT) | \ + (wrreq_e1_macro_lo_full << RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT) | \ + (wrreq_e0_macro_hi_full << RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT) | \ + (wrreq_e0_macro_lo_full << RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT) | \ + (wrreq_c_we_hi_full << RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT) | \ + (wrreq_c_we_lo_full << RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT) | \ + (wrreq_z1_full << RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT) | \ + (wrreq_z0_full << RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT) | \ + (wrreq_c1_full << RB_DEBUG_0_WRREQ_C1_FULL_SHIFT) | \ + (wrreq_c0_full << RB_DEBUG_0_WRREQ_C0_FULL_SHIFT) | \ + (cmdfifo_z1_hold_full << RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT) | \ + (cmdfifo_z0_hold_full << RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT) | \ + (cmdfifo_c1_hold_full << RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT) | \ + (cmdfifo_c0_hold_full << RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT) | \ + (cmdfifo_z_ordering_full << RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT) | \ + (cmdfifo_c_ordering_full << RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT) | \ + (c_sx_lat_full << RB_DEBUG_0_C_SX_LAT_FULL_SHIFT) | \ + (c_sx_cmd_full << RB_DEBUG_0_C_SX_CMD_FULL_SHIFT) | \ + (c_ez_tile_full << RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT) | \ + (c_req_full << RB_DEBUG_0_C_REQ_FULL_SHIFT) | \ + (c_mask_full << RB_DEBUG_0_C_MASK_FULL_SHIFT) | \ + (ez_infsamp_full << RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT)) + +#define RB_DEBUG_0_GET_RDREQ_CTL_Z1_PRE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_CTL_Z0_PRE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_CTL_C1_PRE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_CTL_C0_PRE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_E1_ORDERING_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK) >> RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_E0_ORDERING_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK) >> RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_Z1_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_Z1_FULL_MASK) >> RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_Z0_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_Z0_FULL_MASK) >> RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_C1_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_C1_FULL_MASK) >> RB_DEBUG_0_RDREQ_C1_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_C0_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_C0_FULL_MASK) >> RB_DEBUG_0_RDREQ_C0_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_E1_MACRO_HI_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_E1_MACRO_LO_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_E0_MACRO_HI_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_E0_MACRO_LO_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_C_WE_HI_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_C_WE_LO_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_Z1_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_Z1_FULL_MASK) >> RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_Z0_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_Z0_FULL_MASK) >> RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_C1_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_C1_FULL_MASK) >> RB_DEBUG_0_WRREQ_C1_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_C0_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_C0_FULL_MASK) >> RB_DEBUG_0_WRREQ_C0_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_Z1_HOLD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_Z0_HOLD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_C1_HOLD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_C0_HOLD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_Z_ORDERING_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_C_ORDERING_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_SX_LAT_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_SX_LAT_FULL_MASK) >> RB_DEBUG_0_C_SX_LAT_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_SX_CMD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_SX_CMD_FULL_MASK) >> RB_DEBUG_0_C_SX_CMD_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_EZ_TILE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_EZ_TILE_FULL_MASK) >> RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_REQ_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_REQ_FULL_MASK) >> RB_DEBUG_0_C_REQ_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_MASK_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_MASK_FULL_MASK) >> RB_DEBUG_0_C_MASK_FULL_SHIFT) +#define RB_DEBUG_0_GET_EZ_INFSAMP_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) >> RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT) + +#define RB_DEBUG_0_SET_RDREQ_CTL_Z1_PRE_FULL(rb_debug_0_reg, rdreq_ctl_z1_pre_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK) | (rdreq_ctl_z1_pre_full << RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_CTL_Z0_PRE_FULL(rb_debug_0_reg, rdreq_ctl_z0_pre_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK) | (rdreq_ctl_z0_pre_full << RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_CTL_C1_PRE_FULL(rb_debug_0_reg, rdreq_ctl_c1_pre_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK) | (rdreq_ctl_c1_pre_full << RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_CTL_C0_PRE_FULL(rb_debug_0_reg, rdreq_ctl_c0_pre_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK) | (rdreq_ctl_c0_pre_full << RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_E1_ORDERING_FULL(rb_debug_0_reg, rdreq_e1_ordering_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK) | (rdreq_e1_ordering_full << RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_E0_ORDERING_FULL(rb_debug_0_reg, rdreq_e0_ordering_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK) | (rdreq_e0_ordering_full << RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_Z1_FULL(rb_debug_0_reg, rdreq_z1_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_Z1_FULL_MASK) | (rdreq_z1_full << RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_Z0_FULL(rb_debug_0_reg, rdreq_z0_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_Z0_FULL_MASK) | (rdreq_z0_full << RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_C1_FULL(rb_debug_0_reg, rdreq_c1_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_C1_FULL_MASK) | (rdreq_c1_full << RB_DEBUG_0_RDREQ_C1_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_C0_FULL(rb_debug_0_reg, rdreq_c0_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_C0_FULL_MASK) | (rdreq_c0_full << RB_DEBUG_0_RDREQ_C0_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_E1_MACRO_HI_FULL(rb_debug_0_reg, wrreq_e1_macro_hi_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK) | (wrreq_e1_macro_hi_full << RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_E1_MACRO_LO_FULL(rb_debug_0_reg, wrreq_e1_macro_lo_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK) | (wrreq_e1_macro_lo_full << RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_E0_MACRO_HI_FULL(rb_debug_0_reg, wrreq_e0_macro_hi_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK) | (wrreq_e0_macro_hi_full << RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_E0_MACRO_LO_FULL(rb_debug_0_reg, wrreq_e0_macro_lo_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK) | (wrreq_e0_macro_lo_full << RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_C_WE_HI_FULL(rb_debug_0_reg, wrreq_c_we_hi_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK) | (wrreq_c_we_hi_full << RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_C_WE_LO_FULL(rb_debug_0_reg, wrreq_c_we_lo_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK) | (wrreq_c_we_lo_full << RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_Z1_FULL(rb_debug_0_reg, wrreq_z1_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_Z1_FULL_MASK) | (wrreq_z1_full << RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_Z0_FULL(rb_debug_0_reg, wrreq_z0_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_Z0_FULL_MASK) | (wrreq_z0_full << RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_C1_FULL(rb_debug_0_reg, wrreq_c1_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C1_FULL_MASK) | (wrreq_c1_full << RB_DEBUG_0_WRREQ_C1_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_C0_FULL(rb_debug_0_reg, wrreq_c0_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C0_FULL_MASK) | (wrreq_c0_full << RB_DEBUG_0_WRREQ_C0_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_Z1_HOLD_FULL(rb_debug_0_reg, cmdfifo_z1_hold_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK) | (cmdfifo_z1_hold_full << RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_Z0_HOLD_FULL(rb_debug_0_reg, cmdfifo_z0_hold_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK) | (cmdfifo_z0_hold_full << RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_C1_HOLD_FULL(rb_debug_0_reg, cmdfifo_c1_hold_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK) | (cmdfifo_c1_hold_full << RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_C0_HOLD_FULL(rb_debug_0_reg, cmdfifo_c0_hold_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK) | (cmdfifo_c0_hold_full << RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_Z_ORDERING_FULL(rb_debug_0_reg, cmdfifo_z_ordering_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK) | (cmdfifo_z_ordering_full << RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_C_ORDERING_FULL(rb_debug_0_reg, cmdfifo_c_ordering_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK) | (cmdfifo_c_ordering_full << RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_SX_LAT_FULL(rb_debug_0_reg, c_sx_lat_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_SX_LAT_FULL_MASK) | (c_sx_lat_full << RB_DEBUG_0_C_SX_LAT_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_SX_CMD_FULL(rb_debug_0_reg, c_sx_cmd_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_SX_CMD_FULL_MASK) | (c_sx_cmd_full << RB_DEBUG_0_C_SX_CMD_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_EZ_TILE_FULL(rb_debug_0_reg, c_ez_tile_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_EZ_TILE_FULL_MASK) | (c_ez_tile_full << RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_REQ_FULL(rb_debug_0_reg, c_req_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_REQ_FULL_MASK) | (c_req_full << RB_DEBUG_0_C_REQ_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_MASK_FULL(rb_debug_0_reg, c_mask_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_MASK_FULL_MASK) | (c_mask_full << RB_DEBUG_0_C_MASK_FULL_SHIFT) +#define RB_DEBUG_0_SET_EZ_INFSAMP_FULL(rb_debug_0_reg, ez_infsamp_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) | (ez_infsamp_full << RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_0_t { + unsigned int rdreq_ctl_z1_pre_full : RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE; + unsigned int rdreq_ctl_z0_pre_full : RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE; + unsigned int rdreq_ctl_c1_pre_full : RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE; + unsigned int rdreq_ctl_c0_pre_full : RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE; + unsigned int rdreq_e1_ordering_full : RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE; + unsigned int rdreq_e0_ordering_full : RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE; + unsigned int rdreq_z1_full : RB_DEBUG_0_RDREQ_Z1_FULL_SIZE; + unsigned int rdreq_z0_full : RB_DEBUG_0_RDREQ_Z0_FULL_SIZE; + unsigned int rdreq_c1_full : RB_DEBUG_0_RDREQ_C1_FULL_SIZE; + unsigned int rdreq_c0_full : RB_DEBUG_0_RDREQ_C0_FULL_SIZE; + unsigned int wrreq_e1_macro_hi_full : RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE; + unsigned int wrreq_e1_macro_lo_full : RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE; + unsigned int wrreq_e0_macro_hi_full : RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE; + unsigned int wrreq_e0_macro_lo_full : RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE; + unsigned int wrreq_c_we_hi_full : RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE; + unsigned int wrreq_c_we_lo_full : RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE; + unsigned int wrreq_z1_full : RB_DEBUG_0_WRREQ_Z1_FULL_SIZE; + unsigned int wrreq_z0_full : RB_DEBUG_0_WRREQ_Z0_FULL_SIZE; + unsigned int wrreq_c1_full : RB_DEBUG_0_WRREQ_C1_FULL_SIZE; + unsigned int wrreq_c0_full : RB_DEBUG_0_WRREQ_C0_FULL_SIZE; + unsigned int cmdfifo_z1_hold_full : RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE; + unsigned int cmdfifo_z0_hold_full : RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE; + unsigned int cmdfifo_c1_hold_full : RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE; + unsigned int cmdfifo_c0_hold_full : RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE; + unsigned int cmdfifo_z_ordering_full : RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE; + unsigned int cmdfifo_c_ordering_full : RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE; + unsigned int c_sx_lat_full : RB_DEBUG_0_C_SX_LAT_FULL_SIZE; + unsigned int c_sx_cmd_full : RB_DEBUG_0_C_SX_CMD_FULL_SIZE; + unsigned int c_ez_tile_full : RB_DEBUG_0_C_EZ_TILE_FULL_SIZE; + unsigned int c_req_full : RB_DEBUG_0_C_REQ_FULL_SIZE; + unsigned int c_mask_full : RB_DEBUG_0_C_MASK_FULL_SIZE; + unsigned int ez_infsamp_full : RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE; + } rb_debug_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_0_t { + unsigned int ez_infsamp_full : RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE; + unsigned int c_mask_full : RB_DEBUG_0_C_MASK_FULL_SIZE; + unsigned int c_req_full : RB_DEBUG_0_C_REQ_FULL_SIZE; + unsigned int c_ez_tile_full : RB_DEBUG_0_C_EZ_TILE_FULL_SIZE; + unsigned int c_sx_cmd_full : RB_DEBUG_0_C_SX_CMD_FULL_SIZE; + unsigned int c_sx_lat_full : RB_DEBUG_0_C_SX_LAT_FULL_SIZE; + unsigned int cmdfifo_c_ordering_full : RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE; + unsigned int cmdfifo_z_ordering_full : RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE; + unsigned int cmdfifo_c0_hold_full : RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE; + unsigned int cmdfifo_c1_hold_full : RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE; + unsigned int cmdfifo_z0_hold_full : RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE; + unsigned int cmdfifo_z1_hold_full : RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE; + unsigned int wrreq_c0_full : RB_DEBUG_0_WRREQ_C0_FULL_SIZE; + unsigned int wrreq_c1_full : RB_DEBUG_0_WRREQ_C1_FULL_SIZE; + unsigned int wrreq_z0_full : RB_DEBUG_0_WRREQ_Z0_FULL_SIZE; + unsigned int wrreq_z1_full : RB_DEBUG_0_WRREQ_Z1_FULL_SIZE; + unsigned int wrreq_c_we_lo_full : RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE; + unsigned int wrreq_c_we_hi_full : RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE; + unsigned int wrreq_e0_macro_lo_full : RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE; + unsigned int wrreq_e0_macro_hi_full : RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE; + unsigned int wrreq_e1_macro_lo_full : RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE; + unsigned int wrreq_e1_macro_hi_full : RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE; + unsigned int rdreq_c0_full : RB_DEBUG_0_RDREQ_C0_FULL_SIZE; + unsigned int rdreq_c1_full : RB_DEBUG_0_RDREQ_C1_FULL_SIZE; + unsigned int rdreq_z0_full : RB_DEBUG_0_RDREQ_Z0_FULL_SIZE; + unsigned int rdreq_z1_full : RB_DEBUG_0_RDREQ_Z1_FULL_SIZE; + unsigned int rdreq_e0_ordering_full : RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE; + unsigned int rdreq_e1_ordering_full : RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE; + unsigned int rdreq_ctl_c0_pre_full : RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE; + unsigned int rdreq_ctl_c1_pre_full : RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE; + unsigned int rdreq_ctl_z0_pre_full : RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE; + unsigned int rdreq_ctl_z1_pre_full : RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE; + } rb_debug_0_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_0_t f; +} rb_debug_0_u; + + +/* + * RB_DEBUG_1 struct + */ + +#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_REQ_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_MASK_EMPTY_SIZE 1 +#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE 1 + +#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT 0 +#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT 1 +#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT 2 +#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT 3 +#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT 4 +#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT 5 +#define RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT 6 +#define RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT 7 +#define RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT 8 +#define RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT 9 +#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT 10 +#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT 11 +#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT 12 +#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT 13 +#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT 14 +#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT 15 +#define RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT 16 +#define RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT 17 +#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT 18 +#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT 19 +#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT 20 +#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT 21 +#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT 22 +#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT 23 +#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT 24 +#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT 25 +#define RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT 26 +#define RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT 27 +#define RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT 28 +#define RB_DEBUG_1_C_REQ_EMPTY_SHIFT 29 +#define RB_DEBUG_1_C_MASK_EMPTY_SHIFT 30 +#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT 31 + +#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK 0x00000001 +#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK 0x00000002 +#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK 0x00000004 +#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK 0x00000008 +#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK 0x00000010 +#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK 0x00000020 +#define RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK 0x00000040 +#define RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK 0x00000080 +#define RB_DEBUG_1_RDREQ_C1_EMPTY_MASK 0x00000100 +#define RB_DEBUG_1_RDREQ_C0_EMPTY_MASK 0x00000200 +#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK 0x00000400 +#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK 0x00000800 +#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK 0x00001000 +#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK 0x00002000 +#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK 0x00004000 +#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK 0x00008000 +#define RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK 0x00010000 +#define RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK 0x00020000 +#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK 0x00040000 +#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK 0x00080000 +#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK 0x00100000 +#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK 0x00200000 +#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK 0x00400000 +#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK 0x00800000 +#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK 0x01000000 +#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK 0x02000000 +#define RB_DEBUG_1_C_SX_LAT_EMPTY_MASK 0x04000000 +#define RB_DEBUG_1_C_SX_CMD_EMPTY_MASK 0x08000000 +#define RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK 0x10000000 +#define RB_DEBUG_1_C_REQ_EMPTY_MASK 0x20000000 +#define RB_DEBUG_1_C_MASK_EMPTY_MASK 0x40000000 +#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK 0x80000000 + +#define RB_DEBUG_1_MASK \ + (RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_C1_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_C0_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK | \ + RB_DEBUG_1_C_SX_LAT_EMPTY_MASK | \ + RB_DEBUG_1_C_SX_CMD_EMPTY_MASK | \ + RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK | \ + RB_DEBUG_1_C_REQ_EMPTY_MASK | \ + RB_DEBUG_1_C_MASK_EMPTY_MASK | \ + RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) + +#define RB_DEBUG_1(rdreq_z1_cmd_empty, rdreq_z0_cmd_empty, rdreq_c1_cmd_empty, rdreq_c0_cmd_empty, rdreq_e1_ordering_empty, rdreq_e0_ordering_empty, rdreq_z1_empty, rdreq_z0_empty, rdreq_c1_empty, rdreq_c0_empty, wrreq_e1_macro_hi_empty, wrreq_e1_macro_lo_empty, wrreq_e0_macro_hi_empty, wrreq_e0_macro_lo_empty, wrreq_c_we_hi_empty, wrreq_c_we_lo_empty, wrreq_z1_empty, wrreq_z0_empty, wrreq_c1_pre_empty, wrreq_c0_pre_empty, cmdfifo_z1_hold_empty, cmdfifo_z0_hold_empty, cmdfifo_c1_hold_empty, cmdfifo_c0_hold_empty, cmdfifo_z_ordering_empty, cmdfifo_c_ordering_empty, c_sx_lat_empty, c_sx_cmd_empty, c_ez_tile_empty, c_req_empty, c_mask_empty, ez_infsamp_empty) \ + ((rdreq_z1_cmd_empty << RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT) | \ + (rdreq_z0_cmd_empty << RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT) | \ + (rdreq_c1_cmd_empty << RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT) | \ + (rdreq_c0_cmd_empty << RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT) | \ + (rdreq_e1_ordering_empty << RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT) | \ + (rdreq_e0_ordering_empty << RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT) | \ + (rdreq_z1_empty << RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT) | \ + (rdreq_z0_empty << RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT) | \ + (rdreq_c1_empty << RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT) | \ + (rdreq_c0_empty << RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT) | \ + (wrreq_e1_macro_hi_empty << RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT) | \ + (wrreq_e1_macro_lo_empty << RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT) | \ + (wrreq_e0_macro_hi_empty << RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT) | \ + (wrreq_e0_macro_lo_empty << RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT) | \ + (wrreq_c_we_hi_empty << RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT) | \ + (wrreq_c_we_lo_empty << RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT) | \ + (wrreq_z1_empty << RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT) | \ + (wrreq_z0_empty << RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT) | \ + (wrreq_c1_pre_empty << RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT) | \ + (wrreq_c0_pre_empty << RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT) | \ + (cmdfifo_z1_hold_empty << RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT) | \ + (cmdfifo_z0_hold_empty << RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT) | \ + (cmdfifo_c1_hold_empty << RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT) | \ + (cmdfifo_c0_hold_empty << RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT) | \ + (cmdfifo_z_ordering_empty << RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT) | \ + (cmdfifo_c_ordering_empty << RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT) | \ + (c_sx_lat_empty << RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT) | \ + (c_sx_cmd_empty << RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT) | \ + (c_ez_tile_empty << RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT) | \ + (c_req_empty << RB_DEBUG_1_C_REQ_EMPTY_SHIFT) | \ + (c_mask_empty << RB_DEBUG_1_C_MASK_EMPTY_SHIFT) | \ + (ez_infsamp_empty << RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT)) + +#define RB_DEBUG_1_GET_RDREQ_Z1_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_Z0_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_C1_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_C0_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_E1_ORDERING_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_E0_ORDERING_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_Z1_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_Z0_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_C1_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_C1_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_C0_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_C0_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_E1_MACRO_HI_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_E1_MACRO_LO_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_E0_MACRO_HI_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_E0_MACRO_LO_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_C_WE_HI_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_C_WE_LO_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_Z1_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_Z0_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_C1_PRE_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_C0_PRE_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_Z1_HOLD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_Z0_HOLD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_C1_HOLD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_C0_HOLD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_Z_ORDERING_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_C_ORDERING_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_SX_LAT_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_SX_LAT_EMPTY_MASK) >> RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_SX_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_SX_CMD_EMPTY_MASK) >> RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_EZ_TILE_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK) >> RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_REQ_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_REQ_EMPTY_MASK) >> RB_DEBUG_1_C_REQ_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_MASK_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_MASK_EMPTY_MASK) >> RB_DEBUG_1_C_MASK_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_EZ_INFSAMP_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) >> RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT) + +#define RB_DEBUG_1_SET_RDREQ_Z1_CMD_EMPTY(rb_debug_1_reg, rdreq_z1_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK) | (rdreq_z1_cmd_empty << RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_Z0_CMD_EMPTY(rb_debug_1_reg, rdreq_z0_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK) | (rdreq_z0_cmd_empty << RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_C1_CMD_EMPTY(rb_debug_1_reg, rdreq_c1_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK) | (rdreq_c1_cmd_empty << RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_C0_CMD_EMPTY(rb_debug_1_reg, rdreq_c0_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK) | (rdreq_c0_cmd_empty << RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_E1_ORDERING_EMPTY(rb_debug_1_reg, rdreq_e1_ordering_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK) | (rdreq_e1_ordering_empty << RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_E0_ORDERING_EMPTY(rb_debug_1_reg, rdreq_e0_ordering_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK) | (rdreq_e0_ordering_empty << RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_Z1_EMPTY(rb_debug_1_reg, rdreq_z1_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK) | (rdreq_z1_empty << RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_Z0_EMPTY(rb_debug_1_reg, rdreq_z0_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK) | (rdreq_z0_empty << RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_C1_EMPTY(rb_debug_1_reg, rdreq_c1_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C1_EMPTY_MASK) | (rdreq_c1_empty << RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_C0_EMPTY(rb_debug_1_reg, rdreq_c0_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C0_EMPTY_MASK) | (rdreq_c0_empty << RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_E1_MACRO_HI_EMPTY(rb_debug_1_reg, wrreq_e1_macro_hi_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK) | (wrreq_e1_macro_hi_empty << RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_E1_MACRO_LO_EMPTY(rb_debug_1_reg, wrreq_e1_macro_lo_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK) | (wrreq_e1_macro_lo_empty << RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_E0_MACRO_HI_EMPTY(rb_debug_1_reg, wrreq_e0_macro_hi_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK) | (wrreq_e0_macro_hi_empty << RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_E0_MACRO_LO_EMPTY(rb_debug_1_reg, wrreq_e0_macro_lo_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK) | (wrreq_e0_macro_lo_empty << RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_C_WE_HI_EMPTY(rb_debug_1_reg, wrreq_c_we_hi_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK) | (wrreq_c_we_hi_empty << RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_C_WE_LO_EMPTY(rb_debug_1_reg, wrreq_c_we_lo_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK) | (wrreq_c_we_lo_empty << RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_Z1_EMPTY(rb_debug_1_reg, wrreq_z1_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK) | (wrreq_z1_empty << RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_Z0_EMPTY(rb_debug_1_reg, wrreq_z0_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK) | (wrreq_z0_empty << RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_C1_PRE_EMPTY(rb_debug_1_reg, wrreq_c1_pre_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK) | (wrreq_c1_pre_empty << RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_C0_PRE_EMPTY(rb_debug_1_reg, wrreq_c0_pre_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK) | (wrreq_c0_pre_empty << RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_Z1_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_z1_hold_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK) | (cmdfifo_z1_hold_empty << RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_Z0_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_z0_hold_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK) | (cmdfifo_z0_hold_empty << RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_C1_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_c1_hold_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK) | (cmdfifo_c1_hold_empty << RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_C0_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_c0_hold_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK) | (cmdfifo_c0_hold_empty << RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_Z_ORDERING_EMPTY(rb_debug_1_reg, cmdfifo_z_ordering_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK) | (cmdfifo_z_ordering_empty << RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_C_ORDERING_EMPTY(rb_debug_1_reg, cmdfifo_c_ordering_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK) | (cmdfifo_c_ordering_empty << RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_SX_LAT_EMPTY(rb_debug_1_reg, c_sx_lat_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_SX_LAT_EMPTY_MASK) | (c_sx_lat_empty << RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_SX_CMD_EMPTY(rb_debug_1_reg, c_sx_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_SX_CMD_EMPTY_MASK) | (c_sx_cmd_empty << RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_EZ_TILE_EMPTY(rb_debug_1_reg, c_ez_tile_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK) | (c_ez_tile_empty << RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_REQ_EMPTY(rb_debug_1_reg, c_req_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_REQ_EMPTY_MASK) | (c_req_empty << RB_DEBUG_1_C_REQ_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_MASK_EMPTY(rb_debug_1_reg, c_mask_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_MASK_EMPTY_MASK) | (c_mask_empty << RB_DEBUG_1_C_MASK_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_EZ_INFSAMP_EMPTY(rb_debug_1_reg, ez_infsamp_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) | (ez_infsamp_empty << RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_1_t { + unsigned int rdreq_z1_cmd_empty : RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE; + unsigned int rdreq_z0_cmd_empty : RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE; + unsigned int rdreq_c1_cmd_empty : RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE; + unsigned int rdreq_c0_cmd_empty : RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE; + unsigned int rdreq_e1_ordering_empty : RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE; + unsigned int rdreq_e0_ordering_empty : RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE; + unsigned int rdreq_z1_empty : RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE; + unsigned int rdreq_z0_empty : RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE; + unsigned int rdreq_c1_empty : RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE; + unsigned int rdreq_c0_empty : RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE; + unsigned int wrreq_e1_macro_hi_empty : RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE; + unsigned int wrreq_e1_macro_lo_empty : RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE; + unsigned int wrreq_e0_macro_hi_empty : RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE; + unsigned int wrreq_e0_macro_lo_empty : RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE; + unsigned int wrreq_c_we_hi_empty : RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE; + unsigned int wrreq_c_we_lo_empty : RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE; + unsigned int wrreq_z1_empty : RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE; + unsigned int wrreq_z0_empty : RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE; + unsigned int wrreq_c1_pre_empty : RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE; + unsigned int wrreq_c0_pre_empty : RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE; + unsigned int cmdfifo_z1_hold_empty : RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_z0_hold_empty : RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_c1_hold_empty : RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_c0_hold_empty : RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_z_ordering_empty : RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE; + unsigned int cmdfifo_c_ordering_empty : RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE; + unsigned int c_sx_lat_empty : RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE; + unsigned int c_sx_cmd_empty : RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE; + unsigned int c_ez_tile_empty : RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE; + unsigned int c_req_empty : RB_DEBUG_1_C_REQ_EMPTY_SIZE; + unsigned int c_mask_empty : RB_DEBUG_1_C_MASK_EMPTY_SIZE; + unsigned int ez_infsamp_empty : RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE; + } rb_debug_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_1_t { + unsigned int ez_infsamp_empty : RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE; + unsigned int c_mask_empty : RB_DEBUG_1_C_MASK_EMPTY_SIZE; + unsigned int c_req_empty : RB_DEBUG_1_C_REQ_EMPTY_SIZE; + unsigned int c_ez_tile_empty : RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE; + unsigned int c_sx_cmd_empty : RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE; + unsigned int c_sx_lat_empty : RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE; + unsigned int cmdfifo_c_ordering_empty : RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE; + unsigned int cmdfifo_z_ordering_empty : RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE; + unsigned int cmdfifo_c0_hold_empty : RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_c1_hold_empty : RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_z0_hold_empty : RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_z1_hold_empty : RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE; + unsigned int wrreq_c0_pre_empty : RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE; + unsigned int wrreq_c1_pre_empty : RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE; + unsigned int wrreq_z0_empty : RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE; + unsigned int wrreq_z1_empty : RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE; + unsigned int wrreq_c_we_lo_empty : RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE; + unsigned int wrreq_c_we_hi_empty : RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE; + unsigned int wrreq_e0_macro_lo_empty : RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE; + unsigned int wrreq_e0_macro_hi_empty : RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE; + unsigned int wrreq_e1_macro_lo_empty : RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE; + unsigned int wrreq_e1_macro_hi_empty : RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE; + unsigned int rdreq_c0_empty : RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE; + unsigned int rdreq_c1_empty : RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE; + unsigned int rdreq_z0_empty : RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE; + unsigned int rdreq_z1_empty : RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE; + unsigned int rdreq_e0_ordering_empty : RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE; + unsigned int rdreq_e1_ordering_empty : RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE; + unsigned int rdreq_c0_cmd_empty : RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE; + unsigned int rdreq_c1_cmd_empty : RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE; + unsigned int rdreq_z0_cmd_empty : RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE; + unsigned int rdreq_z1_cmd_empty : RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE; + } rb_debug_1_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_1_t f; +} rb_debug_1_u; + + +/* + * RB_DEBUG_2 struct + */ + +#define RB_DEBUG_2_TILE_FIFO_COUNT_SIZE 4 +#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE 7 +#define RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE 1 +#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE 1 +#define RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE 1 +#define RB_DEBUG_2_EZ_INFTILE_FULL_SIZE 1 +#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE 1 +#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE 1 +#define RB_DEBUG_2_Z0_MASK_FULL_SIZE 1 +#define RB_DEBUG_2_Z1_MASK_FULL_SIZE 1 +#define RB_DEBUG_2_Z0_REQ_FULL_SIZE 1 +#define RB_DEBUG_2_Z1_REQ_FULL_SIZE 1 +#define RB_DEBUG_2_Z_SAMP_FULL_SIZE 1 +#define RB_DEBUG_2_Z_TILE_FULL_SIZE 1 +#define RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE 1 +#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE 1 +#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z0_MASK_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z1_MASK_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z0_REQ_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z1_REQ_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z_SAMP_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z_TILE_EMPTY_SIZE 1 + +#define RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT 0 +#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT 4 +#define RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT 11 +#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT 12 +#define RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT 13 +#define RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT 14 +#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT 15 +#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT 16 +#define RB_DEBUG_2_Z0_MASK_FULL_SHIFT 17 +#define RB_DEBUG_2_Z1_MASK_FULL_SHIFT 18 +#define RB_DEBUG_2_Z0_REQ_FULL_SHIFT 19 +#define RB_DEBUG_2_Z1_REQ_FULL_SHIFT 20 +#define RB_DEBUG_2_Z_SAMP_FULL_SHIFT 21 +#define RB_DEBUG_2_Z_TILE_FULL_SHIFT 22 +#define RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT 23 +#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT 24 +#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT 25 +#define RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT 26 +#define RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT 27 +#define RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT 28 +#define RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT 29 +#define RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT 30 +#define RB_DEBUG_2_Z_TILE_EMPTY_SHIFT 31 + +#define RB_DEBUG_2_TILE_FIFO_COUNT_MASK 0x0000000f +#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK 0x000007f0 +#define RB_DEBUG_2_MEM_EXPORT_FLAG_MASK 0x00000800 +#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK 0x00001000 +#define RB_DEBUG_2_CURRENT_TILE_EVENT_MASK 0x00002000 +#define RB_DEBUG_2_EZ_INFTILE_FULL_MASK 0x00004000 +#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK 0x00008000 +#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK 0x00010000 +#define RB_DEBUG_2_Z0_MASK_FULL_MASK 0x00020000 +#define RB_DEBUG_2_Z1_MASK_FULL_MASK 0x00040000 +#define RB_DEBUG_2_Z0_REQ_FULL_MASK 0x00080000 +#define RB_DEBUG_2_Z1_REQ_FULL_MASK 0x00100000 +#define RB_DEBUG_2_Z_SAMP_FULL_MASK 0x00200000 +#define RB_DEBUG_2_Z_TILE_FULL_MASK 0x00400000 +#define RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK 0x00800000 +#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK 0x01000000 +#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK 0x02000000 +#define RB_DEBUG_2_Z0_MASK_EMPTY_MASK 0x04000000 +#define RB_DEBUG_2_Z1_MASK_EMPTY_MASK 0x08000000 +#define RB_DEBUG_2_Z0_REQ_EMPTY_MASK 0x10000000 +#define RB_DEBUG_2_Z1_REQ_EMPTY_MASK 0x20000000 +#define RB_DEBUG_2_Z_SAMP_EMPTY_MASK 0x40000000 +#define RB_DEBUG_2_Z_TILE_EMPTY_MASK 0x80000000 + +#define RB_DEBUG_2_MASK \ + (RB_DEBUG_2_TILE_FIFO_COUNT_MASK | \ + RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK | \ + RB_DEBUG_2_MEM_EXPORT_FLAG_MASK | \ + RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK | \ + RB_DEBUG_2_CURRENT_TILE_EVENT_MASK | \ + RB_DEBUG_2_EZ_INFTILE_FULL_MASK | \ + RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK | \ + RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK | \ + RB_DEBUG_2_Z0_MASK_FULL_MASK | \ + RB_DEBUG_2_Z1_MASK_FULL_MASK | \ + RB_DEBUG_2_Z0_REQ_FULL_MASK | \ + RB_DEBUG_2_Z1_REQ_FULL_MASK | \ + RB_DEBUG_2_Z_SAMP_FULL_MASK | \ + RB_DEBUG_2_Z_TILE_FULL_MASK | \ + RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK | \ + RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK | \ + RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK | \ + RB_DEBUG_2_Z0_MASK_EMPTY_MASK | \ + RB_DEBUG_2_Z1_MASK_EMPTY_MASK | \ + RB_DEBUG_2_Z0_REQ_EMPTY_MASK | \ + RB_DEBUG_2_Z1_REQ_EMPTY_MASK | \ + RB_DEBUG_2_Z_SAMP_EMPTY_MASK | \ + RB_DEBUG_2_Z_TILE_EMPTY_MASK) + +#define RB_DEBUG_2(tile_fifo_count, sx_lat_fifo_count, mem_export_flag, sysmem_blend_flag, current_tile_event, ez_inftile_full, ez_mask_lower_full, ez_mask_upper_full, z0_mask_full, z1_mask_full, z0_req_full, z1_req_full, z_samp_full, z_tile_full, ez_inftile_empty, ez_mask_lower_empty, ez_mask_upper_empty, z0_mask_empty, z1_mask_empty, z0_req_empty, z1_req_empty, z_samp_empty, z_tile_empty) \ + ((tile_fifo_count << RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT) | \ + (sx_lat_fifo_count << RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT) | \ + (mem_export_flag << RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT) | \ + (sysmem_blend_flag << RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT) | \ + (current_tile_event << RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT) | \ + (ez_inftile_full << RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT) | \ + (ez_mask_lower_full << RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT) | \ + (ez_mask_upper_full << RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT) | \ + (z0_mask_full << RB_DEBUG_2_Z0_MASK_FULL_SHIFT) | \ + (z1_mask_full << RB_DEBUG_2_Z1_MASK_FULL_SHIFT) | \ + (z0_req_full << RB_DEBUG_2_Z0_REQ_FULL_SHIFT) | \ + (z1_req_full << RB_DEBUG_2_Z1_REQ_FULL_SHIFT) | \ + (z_samp_full << RB_DEBUG_2_Z_SAMP_FULL_SHIFT) | \ + (z_tile_full << RB_DEBUG_2_Z_TILE_FULL_SHIFT) | \ + (ez_inftile_empty << RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT) | \ + (ez_mask_lower_empty << RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT) | \ + (ez_mask_upper_empty << RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT) | \ + (z0_mask_empty << RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT) | \ + (z1_mask_empty << RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT) | \ + (z0_req_empty << RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT) | \ + (z1_req_empty << RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT) | \ + (z_samp_empty << RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT) | \ + (z_tile_empty << RB_DEBUG_2_Z_TILE_EMPTY_SHIFT)) + +#define RB_DEBUG_2_GET_TILE_FIFO_COUNT(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_TILE_FIFO_COUNT_MASK) >> RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT) +#define RB_DEBUG_2_GET_SX_LAT_FIFO_COUNT(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK) >> RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT) +#define RB_DEBUG_2_GET_MEM_EXPORT_FLAG(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_MEM_EXPORT_FLAG_MASK) >> RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT) +#define RB_DEBUG_2_GET_SYSMEM_BLEND_FLAG(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK) >> RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT) +#define RB_DEBUG_2_GET_CURRENT_TILE_EVENT(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_CURRENT_TILE_EVENT_MASK) >> RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT) +#define RB_DEBUG_2_GET_EZ_INFTILE_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_INFTILE_FULL_MASK) >> RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT) +#define RB_DEBUG_2_GET_EZ_MASK_LOWER_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK) >> RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT) +#define RB_DEBUG_2_GET_EZ_MASK_UPPER_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK) >> RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z0_MASK_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z0_MASK_FULL_MASK) >> RB_DEBUG_2_Z0_MASK_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z1_MASK_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z1_MASK_FULL_MASK) >> RB_DEBUG_2_Z1_MASK_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z0_REQ_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z0_REQ_FULL_MASK) >> RB_DEBUG_2_Z0_REQ_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z1_REQ_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z1_REQ_FULL_MASK) >> RB_DEBUG_2_Z1_REQ_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z_SAMP_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z_SAMP_FULL_MASK) >> RB_DEBUG_2_Z_SAMP_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z_TILE_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z_TILE_FULL_MASK) >> RB_DEBUG_2_Z_TILE_FULL_SHIFT) +#define RB_DEBUG_2_GET_EZ_INFTILE_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK) >> RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_EZ_MASK_LOWER_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK) >> RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_EZ_MASK_UPPER_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK) >> RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z0_MASK_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z0_MASK_EMPTY_MASK) >> RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z1_MASK_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z1_MASK_EMPTY_MASK) >> RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z0_REQ_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z0_REQ_EMPTY_MASK) >> RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z1_REQ_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z1_REQ_EMPTY_MASK) >> RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z_SAMP_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z_SAMP_EMPTY_MASK) >> RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z_TILE_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z_TILE_EMPTY_MASK) >> RB_DEBUG_2_Z_TILE_EMPTY_SHIFT) + +#define RB_DEBUG_2_SET_TILE_FIFO_COUNT(rb_debug_2_reg, tile_fifo_count) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_TILE_FIFO_COUNT_MASK) | (tile_fifo_count << RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT) +#define RB_DEBUG_2_SET_SX_LAT_FIFO_COUNT(rb_debug_2_reg, sx_lat_fifo_count) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK) | (sx_lat_fifo_count << RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT) +#define RB_DEBUG_2_SET_MEM_EXPORT_FLAG(rb_debug_2_reg, mem_export_flag) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_MEM_EXPORT_FLAG_MASK) | (mem_export_flag << RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT) +#define RB_DEBUG_2_SET_SYSMEM_BLEND_FLAG(rb_debug_2_reg, sysmem_blend_flag) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK) | (sysmem_blend_flag << RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT) +#define RB_DEBUG_2_SET_CURRENT_TILE_EVENT(rb_debug_2_reg, current_tile_event) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_CURRENT_TILE_EVENT_MASK) | (current_tile_event << RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT) +#define RB_DEBUG_2_SET_EZ_INFTILE_FULL(rb_debug_2_reg, ez_inftile_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_INFTILE_FULL_MASK) | (ez_inftile_full << RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT) +#define RB_DEBUG_2_SET_EZ_MASK_LOWER_FULL(rb_debug_2_reg, ez_mask_lower_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK) | (ez_mask_lower_full << RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT) +#define RB_DEBUG_2_SET_EZ_MASK_UPPER_FULL(rb_debug_2_reg, ez_mask_upper_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK) | (ez_mask_upper_full << RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z0_MASK_FULL(rb_debug_2_reg, z0_mask_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_MASK_FULL_MASK) | (z0_mask_full << RB_DEBUG_2_Z0_MASK_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z1_MASK_FULL(rb_debug_2_reg, z1_mask_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_MASK_FULL_MASK) | (z1_mask_full << RB_DEBUG_2_Z1_MASK_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z0_REQ_FULL(rb_debug_2_reg, z0_req_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_REQ_FULL_MASK) | (z0_req_full << RB_DEBUG_2_Z0_REQ_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z1_REQ_FULL(rb_debug_2_reg, z1_req_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_REQ_FULL_MASK) | (z1_req_full << RB_DEBUG_2_Z1_REQ_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z_SAMP_FULL(rb_debug_2_reg, z_samp_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_SAMP_FULL_MASK) | (z_samp_full << RB_DEBUG_2_Z_SAMP_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z_TILE_FULL(rb_debug_2_reg, z_tile_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_TILE_FULL_MASK) | (z_tile_full << RB_DEBUG_2_Z_TILE_FULL_SHIFT) +#define RB_DEBUG_2_SET_EZ_INFTILE_EMPTY(rb_debug_2_reg, ez_inftile_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK) | (ez_inftile_empty << RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_EZ_MASK_LOWER_EMPTY(rb_debug_2_reg, ez_mask_lower_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK) | (ez_mask_lower_empty << RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_EZ_MASK_UPPER_EMPTY(rb_debug_2_reg, ez_mask_upper_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK) | (ez_mask_upper_empty << RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z0_MASK_EMPTY(rb_debug_2_reg, z0_mask_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_MASK_EMPTY_MASK) | (z0_mask_empty << RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z1_MASK_EMPTY(rb_debug_2_reg, z1_mask_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_MASK_EMPTY_MASK) | (z1_mask_empty << RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z0_REQ_EMPTY(rb_debug_2_reg, z0_req_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_REQ_EMPTY_MASK) | (z0_req_empty << RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z1_REQ_EMPTY(rb_debug_2_reg, z1_req_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_REQ_EMPTY_MASK) | (z1_req_empty << RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z_SAMP_EMPTY(rb_debug_2_reg, z_samp_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_SAMP_EMPTY_MASK) | (z_samp_empty << RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z_TILE_EMPTY(rb_debug_2_reg, z_tile_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_TILE_EMPTY_MASK) | (z_tile_empty << RB_DEBUG_2_Z_TILE_EMPTY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_2_t { + unsigned int tile_fifo_count : RB_DEBUG_2_TILE_FIFO_COUNT_SIZE; + unsigned int sx_lat_fifo_count : RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE; + unsigned int mem_export_flag : RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE; + unsigned int sysmem_blend_flag : RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE; + unsigned int current_tile_event : RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE; + unsigned int ez_inftile_full : RB_DEBUG_2_EZ_INFTILE_FULL_SIZE; + unsigned int ez_mask_lower_full : RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE; + unsigned int ez_mask_upper_full : RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE; + unsigned int z0_mask_full : RB_DEBUG_2_Z0_MASK_FULL_SIZE; + unsigned int z1_mask_full : RB_DEBUG_2_Z1_MASK_FULL_SIZE; + unsigned int z0_req_full : RB_DEBUG_2_Z0_REQ_FULL_SIZE; + unsigned int z1_req_full : RB_DEBUG_2_Z1_REQ_FULL_SIZE; + unsigned int z_samp_full : RB_DEBUG_2_Z_SAMP_FULL_SIZE; + unsigned int z_tile_full : RB_DEBUG_2_Z_TILE_FULL_SIZE; + unsigned int ez_inftile_empty : RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE; + unsigned int ez_mask_lower_empty : RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE; + unsigned int ez_mask_upper_empty : RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE; + unsigned int z0_mask_empty : RB_DEBUG_2_Z0_MASK_EMPTY_SIZE; + unsigned int z1_mask_empty : RB_DEBUG_2_Z1_MASK_EMPTY_SIZE; + unsigned int z0_req_empty : RB_DEBUG_2_Z0_REQ_EMPTY_SIZE; + unsigned int z1_req_empty : RB_DEBUG_2_Z1_REQ_EMPTY_SIZE; + unsigned int z_samp_empty : RB_DEBUG_2_Z_SAMP_EMPTY_SIZE; + unsigned int z_tile_empty : RB_DEBUG_2_Z_TILE_EMPTY_SIZE; + } rb_debug_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_2_t { + unsigned int z_tile_empty : RB_DEBUG_2_Z_TILE_EMPTY_SIZE; + unsigned int z_samp_empty : RB_DEBUG_2_Z_SAMP_EMPTY_SIZE; + unsigned int z1_req_empty : RB_DEBUG_2_Z1_REQ_EMPTY_SIZE; + unsigned int z0_req_empty : RB_DEBUG_2_Z0_REQ_EMPTY_SIZE; + unsigned int z1_mask_empty : RB_DEBUG_2_Z1_MASK_EMPTY_SIZE; + unsigned int z0_mask_empty : RB_DEBUG_2_Z0_MASK_EMPTY_SIZE; + unsigned int ez_mask_upper_empty : RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE; + unsigned int ez_mask_lower_empty : RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE; + unsigned int ez_inftile_empty : RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE; + unsigned int z_tile_full : RB_DEBUG_2_Z_TILE_FULL_SIZE; + unsigned int z_samp_full : RB_DEBUG_2_Z_SAMP_FULL_SIZE; + unsigned int z1_req_full : RB_DEBUG_2_Z1_REQ_FULL_SIZE; + unsigned int z0_req_full : RB_DEBUG_2_Z0_REQ_FULL_SIZE; + unsigned int z1_mask_full : RB_DEBUG_2_Z1_MASK_FULL_SIZE; + unsigned int z0_mask_full : RB_DEBUG_2_Z0_MASK_FULL_SIZE; + unsigned int ez_mask_upper_full : RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE; + unsigned int ez_mask_lower_full : RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE; + unsigned int ez_inftile_full : RB_DEBUG_2_EZ_INFTILE_FULL_SIZE; + unsigned int current_tile_event : RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE; + unsigned int sysmem_blend_flag : RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE; + unsigned int mem_export_flag : RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE; + unsigned int sx_lat_fifo_count : RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE; + unsigned int tile_fifo_count : RB_DEBUG_2_TILE_FIFO_COUNT_SIZE; + } rb_debug_2_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_2_t f; +} rb_debug_2_u; + + +/* + * RB_DEBUG_3 struct + */ + +#define RB_DEBUG_3_ACCUM_VALID_SIZE 4 +#define RB_DEBUG_3_ACCUM_FLUSHING_SIZE 4 +#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE 6 +#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE 1 +#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE 4 +#define RB_DEBUG_3_SHD_FULL_SIZE 1 +#define RB_DEBUG_3_SHD_EMPTY_SIZE 1 +#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE 1 +#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE 1 +#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE 1 +#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE 1 +#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE 1 +#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE 1 +#define RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE 1 +#define RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE 1 + +#define RB_DEBUG_3_ACCUM_VALID_SHIFT 0 +#define RB_DEBUG_3_ACCUM_FLUSHING_SHIFT 4 +#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT 8 +#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT 14 +#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT 15 +#define RB_DEBUG_3_SHD_FULL_SHIFT 19 +#define RB_DEBUG_3_SHD_EMPTY_SHIFT 20 +#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT 21 +#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT 22 +#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT 23 +#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT 24 +#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT 25 +#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT 26 +#define RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT 27 +#define RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT 28 + +#define RB_DEBUG_3_ACCUM_VALID_MASK 0x0000000f +#define RB_DEBUG_3_ACCUM_FLUSHING_MASK 0x000000f0 +#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK 0x00003f00 +#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK 0x00004000 +#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK 0x00078000 +#define RB_DEBUG_3_SHD_FULL_MASK 0x00080000 +#define RB_DEBUG_3_SHD_EMPTY_MASK 0x00100000 +#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK 0x00200000 +#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK 0x00400000 +#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK 0x00800000 +#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK 0x01000000 +#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK 0x02000000 +#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK 0x04000000 +#define RB_DEBUG_3_ZEXP_LOWER_FULL_MASK 0x08000000 +#define RB_DEBUG_3_ZEXP_UPPER_FULL_MASK 0x10000000 + +#define RB_DEBUG_3_MASK \ + (RB_DEBUG_3_ACCUM_VALID_MASK | \ + RB_DEBUG_3_ACCUM_FLUSHING_MASK | \ + RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK | \ + RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK | \ + RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK | \ + RB_DEBUG_3_SHD_FULL_MASK | \ + RB_DEBUG_3_SHD_EMPTY_MASK | \ + RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK | \ + RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK | \ + RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK | \ + RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK | \ + RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK | \ + RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK | \ + RB_DEBUG_3_ZEXP_LOWER_FULL_MASK | \ + RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) + +#define RB_DEBUG_3(accum_valid, accum_flushing, accum_write_clean_count, accum_input_reg_valid, accum_data_fifo_cnt, shd_full, shd_empty, ez_return_lower_empty, ez_return_upper_empty, ez_return_lower_full, ez_return_upper_full, zexp_lower_empty, zexp_upper_empty, zexp_lower_full, zexp_upper_full) \ + ((accum_valid << RB_DEBUG_3_ACCUM_VALID_SHIFT) | \ + (accum_flushing << RB_DEBUG_3_ACCUM_FLUSHING_SHIFT) | \ + (accum_write_clean_count << RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT) | \ + (accum_input_reg_valid << RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT) | \ + (accum_data_fifo_cnt << RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT) | \ + (shd_full << RB_DEBUG_3_SHD_FULL_SHIFT) | \ + (shd_empty << RB_DEBUG_3_SHD_EMPTY_SHIFT) | \ + (ez_return_lower_empty << RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT) | \ + (ez_return_upper_empty << RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT) | \ + (ez_return_lower_full << RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT) | \ + (ez_return_upper_full << RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT) | \ + (zexp_lower_empty << RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT) | \ + (zexp_upper_empty << RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT) | \ + (zexp_lower_full << RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT) | \ + (zexp_upper_full << RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT)) + +#define RB_DEBUG_3_GET_ACCUM_VALID(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_VALID_MASK) >> RB_DEBUG_3_ACCUM_VALID_SHIFT) +#define RB_DEBUG_3_GET_ACCUM_FLUSHING(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_FLUSHING_MASK) >> RB_DEBUG_3_ACCUM_FLUSHING_SHIFT) +#define RB_DEBUG_3_GET_ACCUM_WRITE_CLEAN_COUNT(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK) >> RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT) +#define RB_DEBUG_3_GET_ACCUM_INPUT_REG_VALID(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK) >> RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT) +#define RB_DEBUG_3_GET_ACCUM_DATA_FIFO_CNT(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK) >> RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT) +#define RB_DEBUG_3_GET_SHD_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_SHD_FULL_MASK) >> RB_DEBUG_3_SHD_FULL_SHIFT) +#define RB_DEBUG_3_GET_SHD_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_SHD_EMPTY_MASK) >> RB_DEBUG_3_SHD_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_EZ_RETURN_LOWER_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK) >> RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_EZ_RETURN_UPPER_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK) >> RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_EZ_RETURN_LOWER_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK) >> RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT) +#define RB_DEBUG_3_GET_EZ_RETURN_UPPER_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK) >> RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT) +#define RB_DEBUG_3_GET_ZEXP_LOWER_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK) >> RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_ZEXP_UPPER_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK) >> RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_ZEXP_LOWER_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ZEXP_LOWER_FULL_MASK) >> RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT) +#define RB_DEBUG_3_GET_ZEXP_UPPER_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) >> RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT) + +#define RB_DEBUG_3_SET_ACCUM_VALID(rb_debug_3_reg, accum_valid) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_VALID_MASK) | (accum_valid << RB_DEBUG_3_ACCUM_VALID_SHIFT) +#define RB_DEBUG_3_SET_ACCUM_FLUSHING(rb_debug_3_reg, accum_flushing) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_FLUSHING_MASK) | (accum_flushing << RB_DEBUG_3_ACCUM_FLUSHING_SHIFT) +#define RB_DEBUG_3_SET_ACCUM_WRITE_CLEAN_COUNT(rb_debug_3_reg, accum_write_clean_count) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK) | (accum_write_clean_count << RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT) +#define RB_DEBUG_3_SET_ACCUM_INPUT_REG_VALID(rb_debug_3_reg, accum_input_reg_valid) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK) | (accum_input_reg_valid << RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT) +#define RB_DEBUG_3_SET_ACCUM_DATA_FIFO_CNT(rb_debug_3_reg, accum_data_fifo_cnt) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK) | (accum_data_fifo_cnt << RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT) +#define RB_DEBUG_3_SET_SHD_FULL(rb_debug_3_reg, shd_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_SHD_FULL_MASK) | (shd_full << RB_DEBUG_3_SHD_FULL_SHIFT) +#define RB_DEBUG_3_SET_SHD_EMPTY(rb_debug_3_reg, shd_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_SHD_EMPTY_MASK) | (shd_empty << RB_DEBUG_3_SHD_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_EZ_RETURN_LOWER_EMPTY(rb_debug_3_reg, ez_return_lower_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK) | (ez_return_lower_empty << RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_EZ_RETURN_UPPER_EMPTY(rb_debug_3_reg, ez_return_upper_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK) | (ez_return_upper_empty << RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_EZ_RETURN_LOWER_FULL(rb_debug_3_reg, ez_return_lower_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK) | (ez_return_lower_full << RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT) +#define RB_DEBUG_3_SET_EZ_RETURN_UPPER_FULL(rb_debug_3_reg, ez_return_upper_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK) | (ez_return_upper_full << RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT) +#define RB_DEBUG_3_SET_ZEXP_LOWER_EMPTY(rb_debug_3_reg, zexp_lower_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK) | (zexp_lower_empty << RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_ZEXP_UPPER_EMPTY(rb_debug_3_reg, zexp_upper_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK) | (zexp_upper_empty << RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_ZEXP_LOWER_FULL(rb_debug_3_reg, zexp_lower_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_LOWER_FULL_MASK) | (zexp_lower_full << RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT) +#define RB_DEBUG_3_SET_ZEXP_UPPER_FULL(rb_debug_3_reg, zexp_upper_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) | (zexp_upper_full << RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_3_t { + unsigned int accum_valid : RB_DEBUG_3_ACCUM_VALID_SIZE; + unsigned int accum_flushing : RB_DEBUG_3_ACCUM_FLUSHING_SIZE; + unsigned int accum_write_clean_count : RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE; + unsigned int accum_input_reg_valid : RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE; + unsigned int accum_data_fifo_cnt : RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE; + unsigned int shd_full : RB_DEBUG_3_SHD_FULL_SIZE; + unsigned int shd_empty : RB_DEBUG_3_SHD_EMPTY_SIZE; + unsigned int ez_return_lower_empty : RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE; + unsigned int ez_return_upper_empty : RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE; + unsigned int ez_return_lower_full : RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE; + unsigned int ez_return_upper_full : RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE; + unsigned int zexp_lower_empty : RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE; + unsigned int zexp_upper_empty : RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE; + unsigned int zexp_lower_full : RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE; + unsigned int zexp_upper_full : RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE; + unsigned int : 3; + } rb_debug_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_3_t { + unsigned int : 3; + unsigned int zexp_upper_full : RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE; + unsigned int zexp_lower_full : RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE; + unsigned int zexp_upper_empty : RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE; + unsigned int zexp_lower_empty : RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE; + unsigned int ez_return_upper_full : RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE; + unsigned int ez_return_lower_full : RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE; + unsigned int ez_return_upper_empty : RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE; + unsigned int ez_return_lower_empty : RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE; + unsigned int shd_empty : RB_DEBUG_3_SHD_EMPTY_SIZE; + unsigned int shd_full : RB_DEBUG_3_SHD_FULL_SIZE; + unsigned int accum_data_fifo_cnt : RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE; + unsigned int accum_input_reg_valid : RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE; + unsigned int accum_write_clean_count : RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE; + unsigned int accum_flushing : RB_DEBUG_3_ACCUM_FLUSHING_SIZE; + unsigned int accum_valid : RB_DEBUG_3_ACCUM_VALID_SIZE; + } rb_debug_3_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_3_t f; +} rb_debug_3_u; + + +/* + * RB_DEBUG_4 struct + */ + +#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE 1 +#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE 1 +#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE 1 +#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE 1 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE 1 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE 1 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE 1 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE 1 +#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE 1 +#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE 4 + +#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT 0 +#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT 1 +#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT 2 +#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT 3 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT 4 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT 5 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT 6 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT 7 +#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT 8 +#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT 9 + +#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK 0x00000001 +#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK 0x00000002 +#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK 0x00000004 +#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK 0x00000008 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK 0x00000010 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK 0x00000020 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK 0x00000040 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK 0x00000080 +#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK 0x00000100 +#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK 0x00001e00 + +#define RB_DEBUG_4_MASK \ + (RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK | \ + RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK | \ + RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK | \ + RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK | \ + RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK | \ + RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK | \ + RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK | \ + RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK | \ + RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK | \ + RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) + +#define RB_DEBUG_4(gmem_rd_access_flag, gmem_wr_access_flag, sysmem_rd_access_flag, sysmem_wr_access_flag, accum_data_fifo_empty, accum_order_fifo_empty, accum_data_fifo_full, accum_order_fifo_full, sysmem_write_count_overflow, context_count_debug) \ + ((gmem_rd_access_flag << RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT) | \ + (gmem_wr_access_flag << RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT) | \ + (sysmem_rd_access_flag << RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT) | \ + (sysmem_wr_access_flag << RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT) | \ + (accum_data_fifo_empty << RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT) | \ + (accum_order_fifo_empty << RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT) | \ + (accum_data_fifo_full << RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT) | \ + (accum_order_fifo_full << RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT) | \ + (sysmem_write_count_overflow << RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT) | \ + (context_count_debug << RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT)) + +#define RB_DEBUG_4_GET_GMEM_RD_ACCESS_FLAG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK) >> RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_GET_GMEM_WR_ACCESS_FLAG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK) >> RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_GET_SYSMEM_RD_ACCESS_FLAG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK) >> RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_GET_SYSMEM_WR_ACCESS_FLAG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK) >> RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_GET_ACCUM_DATA_FIFO_EMPTY(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK) >> RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT) +#define RB_DEBUG_4_GET_ACCUM_ORDER_FIFO_EMPTY(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK) >> RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT) +#define RB_DEBUG_4_GET_ACCUM_DATA_FIFO_FULL(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK) >> RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT) +#define RB_DEBUG_4_GET_ACCUM_ORDER_FIFO_FULL(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK) >> RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT) +#define RB_DEBUG_4_GET_SYSMEM_WRITE_COUNT_OVERFLOW(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK) >> RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT) +#define RB_DEBUG_4_GET_CONTEXT_COUNT_DEBUG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) >> RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT) + +#define RB_DEBUG_4_SET_GMEM_RD_ACCESS_FLAG(rb_debug_4_reg, gmem_rd_access_flag) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK) | (gmem_rd_access_flag << RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_SET_GMEM_WR_ACCESS_FLAG(rb_debug_4_reg, gmem_wr_access_flag) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK) | (gmem_wr_access_flag << RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_SET_SYSMEM_RD_ACCESS_FLAG(rb_debug_4_reg, sysmem_rd_access_flag) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK) | (sysmem_rd_access_flag << RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_SET_SYSMEM_WR_ACCESS_FLAG(rb_debug_4_reg, sysmem_wr_access_flag) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK) | (sysmem_wr_access_flag << RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_SET_ACCUM_DATA_FIFO_EMPTY(rb_debug_4_reg, accum_data_fifo_empty) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK) | (accum_data_fifo_empty << RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT) +#define RB_DEBUG_4_SET_ACCUM_ORDER_FIFO_EMPTY(rb_debug_4_reg, accum_order_fifo_empty) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK) | (accum_order_fifo_empty << RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT) +#define RB_DEBUG_4_SET_ACCUM_DATA_FIFO_FULL(rb_debug_4_reg, accum_data_fifo_full) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK) | (accum_data_fifo_full << RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT) +#define RB_DEBUG_4_SET_ACCUM_ORDER_FIFO_FULL(rb_debug_4_reg, accum_order_fifo_full) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK) | (accum_order_fifo_full << RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT) +#define RB_DEBUG_4_SET_SYSMEM_WRITE_COUNT_OVERFLOW(rb_debug_4_reg, sysmem_write_count_overflow) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK) | (sysmem_write_count_overflow << RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT) +#define RB_DEBUG_4_SET_CONTEXT_COUNT_DEBUG(rb_debug_4_reg, context_count_debug) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) | (context_count_debug << RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_4_t { + unsigned int gmem_rd_access_flag : RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE; + unsigned int gmem_wr_access_flag : RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE; + unsigned int sysmem_rd_access_flag : RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE; + unsigned int sysmem_wr_access_flag : RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE; + unsigned int accum_data_fifo_empty : RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE; + unsigned int accum_order_fifo_empty : RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE; + unsigned int accum_data_fifo_full : RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE; + unsigned int accum_order_fifo_full : RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE; + unsigned int sysmem_write_count_overflow : RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE; + unsigned int context_count_debug : RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE; + unsigned int : 19; + } rb_debug_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_4_t { + unsigned int : 19; + unsigned int context_count_debug : RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE; + unsigned int sysmem_write_count_overflow : RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE; + unsigned int accum_order_fifo_full : RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE; + unsigned int accum_data_fifo_full : RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE; + unsigned int accum_order_fifo_empty : RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE; + unsigned int accum_data_fifo_empty : RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE; + unsigned int sysmem_wr_access_flag : RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE; + unsigned int sysmem_rd_access_flag : RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE; + unsigned int gmem_wr_access_flag : RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE; + unsigned int gmem_rd_access_flag : RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE; + } rb_debug_4_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_4_t f; +} rb_debug_4_u; + + +/* + * RB_FLAG_CONTROL struct + */ + +#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE 1 + +#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT 0 + +#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK 0x00000001 + +#define RB_FLAG_CONTROL_MASK \ + (RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) + +#define RB_FLAG_CONTROL(debug_flag_clear) \ + ((debug_flag_clear << RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT)) + +#define RB_FLAG_CONTROL_GET_DEBUG_FLAG_CLEAR(rb_flag_control) \ + ((rb_flag_control & RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) >> RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT) + +#define RB_FLAG_CONTROL_SET_DEBUG_FLAG_CLEAR(rb_flag_control_reg, debug_flag_clear) \ + rb_flag_control_reg = (rb_flag_control_reg & ~RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) | (debug_flag_clear << RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_flag_control_t { + unsigned int debug_flag_clear : RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE; + unsigned int : 31; + } rb_flag_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_flag_control_t { + unsigned int : 31; + unsigned int debug_flag_clear : RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE; + } rb_flag_control_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_flag_control_t f; +} rb_flag_control_u; + + +/* + * RB_BC_SPARES struct + */ + +#define RB_BC_SPARES_RESERVED_SIZE 32 + +#define RB_BC_SPARES_RESERVED_SHIFT 0 + +#define RB_BC_SPARES_RESERVED_MASK 0xffffffff + +#define RB_BC_SPARES_MASK \ + (RB_BC_SPARES_RESERVED_MASK) + +#define RB_BC_SPARES(reserved) \ + ((reserved << RB_BC_SPARES_RESERVED_SHIFT)) + +#define RB_BC_SPARES_GET_RESERVED(rb_bc_spares) \ + ((rb_bc_spares & RB_BC_SPARES_RESERVED_MASK) >> RB_BC_SPARES_RESERVED_SHIFT) + +#define RB_BC_SPARES_SET_RESERVED(rb_bc_spares_reg, reserved) \ + rb_bc_spares_reg = (rb_bc_spares_reg & ~RB_BC_SPARES_RESERVED_MASK) | (reserved << RB_BC_SPARES_RESERVED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_bc_spares_t { + unsigned int reserved : RB_BC_SPARES_RESERVED_SIZE; + } rb_bc_spares_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_bc_spares_t { + unsigned int reserved : RB_BC_SPARES_RESERVED_SIZE; + } rb_bc_spares_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_bc_spares_t f; +} rb_bc_spares_u; + + +/* + * BC_DUMMY_CRAYRB_ENUMS struct + */ + +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE 6 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE 1 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE 2 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE 2 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE 6 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE 3 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE 6 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE 1 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE 2 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE 3 + +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT 0 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT 6 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT 7 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT 9 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT 11 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT 17 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT 20 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT 26 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT 27 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT 29 + +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK 0x0000003f +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK 0x00000040 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK 0x00000180 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK 0x00000600 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK 0x0001f800 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK 0x000e0000 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK 0x03f00000 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK 0x04000000 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK 0x18000000 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK 0xe0000000 + +#define BC_DUMMY_CRAYRB_ENUMS_MASK \ + (BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) + +#define BC_DUMMY_CRAYRB_ENUMS(dummy_crayrb_depth_format, dummy_crayrb_surface_swap, dummy_crayrb_depth_array, dummy_crayrb_array, dummy_crayrb_color_format, dummy_crayrb_surface_number, dummy_crayrb_surface_format, dummy_crayrb_surface_tiling, dummy_crayrb_surface_array, dummy_rb_copy_dest_info_number) \ + ((dummy_crayrb_depth_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT) | \ + (dummy_crayrb_surface_swap << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT) | \ + (dummy_crayrb_depth_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT) | \ + (dummy_crayrb_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT) | \ + (dummy_crayrb_color_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT) | \ + (dummy_crayrb_surface_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT) | \ + (dummy_crayrb_surface_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT) | \ + (dummy_crayrb_surface_tiling << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT) | \ + (dummy_crayrb_surface_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT) | \ + (dummy_rb_copy_dest_info_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT)) + +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_DEPTH_FORMAT(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_SWAP(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_DEPTH_ARRAY(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_ARRAY(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_COLOR_FORMAT(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_NUMBER(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_FORMAT(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_TILING(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_ARRAY(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_RB_COPY_DEST_INFO_NUMBER(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT) + +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_DEPTH_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_depth_format) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK) | (dummy_crayrb_depth_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_SWAP(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_swap) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK) | (dummy_crayrb_surface_swap << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_DEPTH_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_depth_array) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK) | (dummy_crayrb_depth_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_array) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK) | (dummy_crayrb_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_COLOR_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_color_format) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK) | (dummy_crayrb_color_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_NUMBER(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_number) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK) | (dummy_crayrb_surface_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_format) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK) | (dummy_crayrb_surface_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_TILING(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_tiling) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK) | (dummy_crayrb_surface_tiling << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_array) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK) | (dummy_crayrb_surface_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_RB_COPY_DEST_INFO_NUMBER(bc_dummy_crayrb_enums_reg, dummy_rb_copy_dest_info_number) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) | (dummy_rb_copy_dest_info_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bc_dummy_crayrb_enums_t { + unsigned int dummy_crayrb_depth_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE; + unsigned int dummy_crayrb_surface_swap : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE; + unsigned int dummy_crayrb_depth_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE; + unsigned int dummy_crayrb_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE; + unsigned int dummy_crayrb_color_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE; + unsigned int dummy_crayrb_surface_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE; + unsigned int dummy_crayrb_surface_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE; + unsigned int dummy_crayrb_surface_tiling : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE; + unsigned int dummy_crayrb_surface_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE; + unsigned int dummy_rb_copy_dest_info_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE; + } bc_dummy_crayrb_enums_t; + +#else // !BIGENDIAN_OS + + typedef struct _bc_dummy_crayrb_enums_t { + unsigned int dummy_rb_copy_dest_info_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE; + unsigned int dummy_crayrb_surface_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE; + unsigned int dummy_crayrb_surface_tiling : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE; + unsigned int dummy_crayrb_surface_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE; + unsigned int dummy_crayrb_surface_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE; + unsigned int dummy_crayrb_color_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE; + unsigned int dummy_crayrb_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE; + unsigned int dummy_crayrb_depth_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE; + unsigned int dummy_crayrb_surface_swap : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE; + unsigned int dummy_crayrb_depth_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE; + } bc_dummy_crayrb_enums_t; + +#endif + +typedef union { + unsigned int val : 32; + bc_dummy_crayrb_enums_t f; +} bc_dummy_crayrb_enums_u; + + +/* + * BC_DUMMY_CRAYRB_MOREENUMS struct + */ + +#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE 2 + +#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT 0 + +#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK 0x00000003 + +#define BC_DUMMY_CRAYRB_MOREENUMS_MASK \ + (BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) + +#define BC_DUMMY_CRAYRB_MOREENUMS(dummy_crayrb_colorarrayx) \ + ((dummy_crayrb_colorarrayx << BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT)) + +#define BC_DUMMY_CRAYRB_MOREENUMS_GET_DUMMY_CRAYRB_COLORARRAYX(bc_dummy_crayrb_moreenums) \ + ((bc_dummy_crayrb_moreenums & BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) >> BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT) + +#define BC_DUMMY_CRAYRB_MOREENUMS_SET_DUMMY_CRAYRB_COLORARRAYX(bc_dummy_crayrb_moreenums_reg, dummy_crayrb_colorarrayx) \ + bc_dummy_crayrb_moreenums_reg = (bc_dummy_crayrb_moreenums_reg & ~BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) | (dummy_crayrb_colorarrayx << BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bc_dummy_crayrb_moreenums_t { + unsigned int dummy_crayrb_colorarrayx : BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE; + unsigned int : 30; + } bc_dummy_crayrb_moreenums_t; + +#else // !BIGENDIAN_OS + + typedef struct _bc_dummy_crayrb_moreenums_t { + unsigned int : 30; + unsigned int dummy_crayrb_colorarrayx : BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE; + } bc_dummy_crayrb_moreenums_t; + +#endif + +typedef union { + unsigned int val : 32; + bc_dummy_crayrb_moreenums_t f; +} bc_dummy_crayrb_moreenums_u; + + +#endif + + diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_typedef.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_typedef.h new file mode 100644 index 000000000000..6968abb48bd7 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamato_typedef.h @@ -0,0 +1,550 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_TYPEDEF_HEADER) +#define _yamato_TYPEDEF_HEADER + +#include "yamato_registers.h" + +typedef union PA_CL_VPORT_XSCALE regPA_CL_VPORT_XSCALE; +typedef union PA_CL_VPORT_XOFFSET regPA_CL_VPORT_XOFFSET; +typedef union PA_CL_VPORT_YSCALE regPA_CL_VPORT_YSCALE; +typedef union PA_CL_VPORT_YOFFSET regPA_CL_VPORT_YOFFSET; +typedef union PA_CL_VPORT_ZSCALE regPA_CL_VPORT_ZSCALE; +typedef union PA_CL_VPORT_ZOFFSET regPA_CL_VPORT_ZOFFSET; +typedef union PA_CL_VTE_CNTL regPA_CL_VTE_CNTL; +typedef union PA_CL_CLIP_CNTL regPA_CL_CLIP_CNTL; +typedef union PA_CL_GB_VERT_CLIP_ADJ regPA_CL_GB_VERT_CLIP_ADJ; +typedef union PA_CL_GB_VERT_DISC_ADJ regPA_CL_GB_VERT_DISC_ADJ; +typedef union PA_CL_GB_HORZ_CLIP_ADJ regPA_CL_GB_HORZ_CLIP_ADJ; +typedef union PA_CL_GB_HORZ_DISC_ADJ regPA_CL_GB_HORZ_DISC_ADJ; +typedef union PA_CL_ENHANCE regPA_CL_ENHANCE; +typedef union PA_SC_ENHANCE regPA_SC_ENHANCE; +typedef union PA_SU_VTX_CNTL regPA_SU_VTX_CNTL; +typedef union PA_SU_POINT_SIZE regPA_SU_POINT_SIZE; +typedef union PA_SU_POINT_MINMAX regPA_SU_POINT_MINMAX; +typedef union PA_SU_LINE_CNTL regPA_SU_LINE_CNTL; +typedef union PA_SU_FACE_DATA regPA_SU_FACE_DATA; +typedef union PA_SU_SC_MODE_CNTL regPA_SU_SC_MODE_CNTL; +typedef union PA_SU_POLY_OFFSET_FRONT_SCALE regPA_SU_POLY_OFFSET_FRONT_SCALE; +typedef union PA_SU_POLY_OFFSET_FRONT_OFFSET regPA_SU_POLY_OFFSET_FRONT_OFFSET; +typedef union PA_SU_POLY_OFFSET_BACK_SCALE regPA_SU_POLY_OFFSET_BACK_SCALE; +typedef union PA_SU_POLY_OFFSET_BACK_OFFSET regPA_SU_POLY_OFFSET_BACK_OFFSET; +typedef union PA_SU_PERFCOUNTER0_SELECT regPA_SU_PERFCOUNTER0_SELECT; +typedef union PA_SU_PERFCOUNTER1_SELECT regPA_SU_PERFCOUNTER1_SELECT; +typedef union PA_SU_PERFCOUNTER2_SELECT regPA_SU_PERFCOUNTER2_SELECT; +typedef union PA_SU_PERFCOUNTER3_SELECT regPA_SU_PERFCOUNTER3_SELECT; +typedef union PA_SU_PERFCOUNTER0_LOW regPA_SU_PERFCOUNTER0_LOW; +typedef union PA_SU_PERFCOUNTER0_HI regPA_SU_PERFCOUNTER0_HI; +typedef union PA_SU_PERFCOUNTER1_LOW regPA_SU_PERFCOUNTER1_LOW; +typedef union PA_SU_PERFCOUNTER1_HI regPA_SU_PERFCOUNTER1_HI; +typedef union PA_SU_PERFCOUNTER2_LOW regPA_SU_PERFCOUNTER2_LOW; +typedef union PA_SU_PERFCOUNTER2_HI regPA_SU_PERFCOUNTER2_HI; +typedef union PA_SU_PERFCOUNTER3_LOW regPA_SU_PERFCOUNTER3_LOW; +typedef union PA_SU_PERFCOUNTER3_HI regPA_SU_PERFCOUNTER3_HI; +typedef union PA_SC_WINDOW_OFFSET regPA_SC_WINDOW_OFFSET; +typedef union PA_SC_AA_CONFIG regPA_SC_AA_CONFIG; +typedef union PA_SC_AA_MASK regPA_SC_AA_MASK; +typedef union PA_SC_LINE_STIPPLE regPA_SC_LINE_STIPPLE; +typedef union PA_SC_LINE_CNTL regPA_SC_LINE_CNTL; +typedef union PA_SC_WINDOW_SCISSOR_TL regPA_SC_WINDOW_SCISSOR_TL; +typedef union PA_SC_WINDOW_SCISSOR_BR regPA_SC_WINDOW_SCISSOR_BR; +typedef union PA_SC_SCREEN_SCISSOR_TL regPA_SC_SCREEN_SCISSOR_TL; +typedef union PA_SC_SCREEN_SCISSOR_BR regPA_SC_SCREEN_SCISSOR_BR; +typedef union PA_SC_VIZ_QUERY regPA_SC_VIZ_QUERY; +typedef union PA_SC_VIZ_QUERY_STATUS regPA_SC_VIZ_QUERY_STATUS; +typedef union PA_SC_LINE_STIPPLE_STATE regPA_SC_LINE_STIPPLE_STATE; +typedef union PA_SC_PERFCOUNTER0_SELECT regPA_SC_PERFCOUNTER0_SELECT; +typedef union PA_SC_PERFCOUNTER0_LOW regPA_SC_PERFCOUNTER0_LOW; +typedef union PA_SC_PERFCOUNTER0_HI regPA_SC_PERFCOUNTER0_HI; +typedef union PA_CL_CNTL_STATUS regPA_CL_CNTL_STATUS; +typedef union PA_SU_CNTL_STATUS regPA_SU_CNTL_STATUS; +typedef union PA_SC_CNTL_STATUS regPA_SC_CNTL_STATUS; +typedef union PA_SU_DEBUG_CNTL regPA_SU_DEBUG_CNTL; +typedef union PA_SU_DEBUG_DATA regPA_SU_DEBUG_DATA; +typedef union PA_SC_DEBUG_CNTL regPA_SC_DEBUG_CNTL; +typedef union PA_SC_DEBUG_DATA regPA_SC_DEBUG_DATA; +typedef union GFX_COPY_STATE regGFX_COPY_STATE; +typedef union VGT_DRAW_INITIATOR regVGT_DRAW_INITIATOR; +typedef union VGT_EVENT_INITIATOR regVGT_EVENT_INITIATOR; +typedef union VGT_DMA_BASE regVGT_DMA_BASE; +typedef union VGT_DMA_SIZE regVGT_DMA_SIZE; +typedef union VGT_BIN_BASE regVGT_BIN_BASE; +typedef union VGT_BIN_SIZE regVGT_BIN_SIZE; +typedef union VGT_CURRENT_BIN_ID_MIN regVGT_CURRENT_BIN_ID_MIN; +typedef union VGT_CURRENT_BIN_ID_MAX regVGT_CURRENT_BIN_ID_MAX; +typedef union VGT_IMMED_DATA regVGT_IMMED_DATA; +typedef union VGT_MAX_VTX_INDX regVGT_MAX_VTX_INDX; +typedef union VGT_MIN_VTX_INDX regVGT_MIN_VTX_INDX; +typedef union VGT_INDX_OFFSET regVGT_INDX_OFFSET; +typedef union VGT_VERTEX_REUSE_BLOCK_CNTL regVGT_VERTEX_REUSE_BLOCK_CNTL; +typedef union VGT_OUT_DEALLOC_CNTL regVGT_OUT_DEALLOC_CNTL; +typedef union VGT_MULTI_PRIM_IB_RESET_INDX regVGT_MULTI_PRIM_IB_RESET_INDX; +typedef union VGT_ENHANCE regVGT_ENHANCE; +typedef union VGT_VTX_VECT_EJECT_REG regVGT_VTX_VECT_EJECT_REG; +typedef union VGT_LAST_COPY_STATE regVGT_LAST_COPY_STATE; +typedef union VGT_DEBUG_CNTL regVGT_DEBUG_CNTL; +typedef union VGT_DEBUG_DATA regVGT_DEBUG_DATA; +typedef union VGT_CNTL_STATUS regVGT_CNTL_STATUS; +typedef union VGT_CRC_SQ_DATA regVGT_CRC_SQ_DATA; +typedef union VGT_CRC_SQ_CTRL regVGT_CRC_SQ_CTRL; +typedef union VGT_PERFCOUNTER0_SELECT regVGT_PERFCOUNTER0_SELECT; +typedef union VGT_PERFCOUNTER1_SELECT regVGT_PERFCOUNTER1_SELECT; +typedef union VGT_PERFCOUNTER2_SELECT regVGT_PERFCOUNTER2_SELECT; +typedef union VGT_PERFCOUNTER3_SELECT regVGT_PERFCOUNTER3_SELECT; +typedef union VGT_PERFCOUNTER0_LOW regVGT_PERFCOUNTER0_LOW; +typedef union VGT_PERFCOUNTER1_LOW regVGT_PERFCOUNTER1_LOW; +typedef union VGT_PERFCOUNTER2_LOW regVGT_PERFCOUNTER2_LOW; +typedef union VGT_PERFCOUNTER3_LOW regVGT_PERFCOUNTER3_LOW; +typedef union VGT_PERFCOUNTER0_HI regVGT_PERFCOUNTER0_HI; +typedef union VGT_PERFCOUNTER1_HI regVGT_PERFCOUNTER1_HI; +typedef union VGT_PERFCOUNTER2_HI regVGT_PERFCOUNTER2_HI; +typedef union VGT_PERFCOUNTER3_HI regVGT_PERFCOUNTER3_HI; +typedef union TC_CNTL_STATUS regTC_CNTL_STATUS; +typedef union TCR_CHICKEN regTCR_CHICKEN; +typedef union TCF_CHICKEN regTCF_CHICKEN; +typedef union TCM_CHICKEN regTCM_CHICKEN; +typedef union TCR_PERFCOUNTER0_SELECT regTCR_PERFCOUNTER0_SELECT; +typedef union TCR_PERFCOUNTER1_SELECT regTCR_PERFCOUNTER1_SELECT; +typedef union TCR_PERFCOUNTER0_HI regTCR_PERFCOUNTER0_HI; +typedef union TCR_PERFCOUNTER1_HI regTCR_PERFCOUNTER1_HI; +typedef union TCR_PERFCOUNTER0_LOW regTCR_PERFCOUNTER0_LOW; +typedef union TCR_PERFCOUNTER1_LOW regTCR_PERFCOUNTER1_LOW; +typedef union TP_TC_CLKGATE_CNTL regTP_TC_CLKGATE_CNTL; +typedef union TPC_CNTL_STATUS regTPC_CNTL_STATUS; +typedef union TPC_DEBUG0 regTPC_DEBUG0; +typedef union TPC_DEBUG1 regTPC_DEBUG1; +typedef union TPC_CHICKEN regTPC_CHICKEN; +typedef union TP0_CNTL_STATUS regTP0_CNTL_STATUS; +typedef union TP0_DEBUG regTP0_DEBUG; +typedef union TP0_CHICKEN regTP0_CHICKEN; +typedef union TP0_PERFCOUNTER0_SELECT regTP0_PERFCOUNTER0_SELECT; +typedef union TP0_PERFCOUNTER0_HI regTP0_PERFCOUNTER0_HI; +typedef union TP0_PERFCOUNTER0_LOW regTP0_PERFCOUNTER0_LOW; +typedef union TP0_PERFCOUNTER1_SELECT regTP0_PERFCOUNTER1_SELECT; +typedef union TP0_PERFCOUNTER1_HI regTP0_PERFCOUNTER1_HI; +typedef union TP0_PERFCOUNTER1_LOW regTP0_PERFCOUNTER1_LOW; +typedef union TCM_PERFCOUNTER0_SELECT regTCM_PERFCOUNTER0_SELECT; +typedef union TCM_PERFCOUNTER1_SELECT regTCM_PERFCOUNTER1_SELECT; +typedef union TCM_PERFCOUNTER0_HI regTCM_PERFCOUNTER0_HI; +typedef union TCM_PERFCOUNTER1_HI regTCM_PERFCOUNTER1_HI; +typedef union TCM_PERFCOUNTER0_LOW regTCM_PERFCOUNTER0_LOW; +typedef union TCM_PERFCOUNTER1_LOW regTCM_PERFCOUNTER1_LOW; +typedef union TCF_PERFCOUNTER0_SELECT regTCF_PERFCOUNTER0_SELECT; +typedef union TCF_PERFCOUNTER1_SELECT regTCF_PERFCOUNTER1_SELECT; +typedef union TCF_PERFCOUNTER2_SELECT regTCF_PERFCOUNTER2_SELECT; +typedef union TCF_PERFCOUNTER3_SELECT regTCF_PERFCOUNTER3_SELECT; +typedef union TCF_PERFCOUNTER4_SELECT regTCF_PERFCOUNTER4_SELECT; +typedef union TCF_PERFCOUNTER5_SELECT regTCF_PERFCOUNTER5_SELECT; +typedef union TCF_PERFCOUNTER6_SELECT regTCF_PERFCOUNTER6_SELECT; +typedef union TCF_PERFCOUNTER7_SELECT regTCF_PERFCOUNTER7_SELECT; +typedef union TCF_PERFCOUNTER8_SELECT regTCF_PERFCOUNTER8_SELECT; +typedef union TCF_PERFCOUNTER9_SELECT regTCF_PERFCOUNTER9_SELECT; +typedef union TCF_PERFCOUNTER10_SELECT regTCF_PERFCOUNTER10_SELECT; +typedef union TCF_PERFCOUNTER11_SELECT regTCF_PERFCOUNTER11_SELECT; +typedef union TCF_PERFCOUNTER0_HI regTCF_PERFCOUNTER0_HI; +typedef union TCF_PERFCOUNTER1_HI regTCF_PERFCOUNTER1_HI; +typedef union TCF_PERFCOUNTER2_HI regTCF_PERFCOUNTER2_HI; +typedef union TCF_PERFCOUNTER3_HI regTCF_PERFCOUNTER3_HI; +typedef union TCF_PERFCOUNTER4_HI regTCF_PERFCOUNTER4_HI; +typedef union TCF_PERFCOUNTER5_HI regTCF_PERFCOUNTER5_HI; +typedef union TCF_PERFCOUNTER6_HI regTCF_PERFCOUNTER6_HI; +typedef union TCF_PERFCOUNTER7_HI regTCF_PERFCOUNTER7_HI; +typedef union TCF_PERFCOUNTER8_HI regTCF_PERFCOUNTER8_HI; +typedef union TCF_PERFCOUNTER9_HI regTCF_PERFCOUNTER9_HI; +typedef union TCF_PERFCOUNTER10_HI regTCF_PERFCOUNTER10_HI; +typedef union TCF_PERFCOUNTER11_HI regTCF_PERFCOUNTER11_HI; +typedef union TCF_PERFCOUNTER0_LOW regTCF_PERFCOUNTER0_LOW; +typedef union TCF_PERFCOUNTER1_LOW regTCF_PERFCOUNTER1_LOW; +typedef union TCF_PERFCOUNTER2_LOW regTCF_PERFCOUNTER2_LOW; +typedef union TCF_PERFCOUNTER3_LOW regTCF_PERFCOUNTER3_LOW; +typedef union TCF_PERFCOUNTER4_LOW regTCF_PERFCOUNTER4_LOW; +typedef union TCF_PERFCOUNTER5_LOW regTCF_PERFCOUNTER5_LOW; +typedef union TCF_PERFCOUNTER6_LOW regTCF_PERFCOUNTER6_LOW; +typedef union TCF_PERFCOUNTER7_LOW regTCF_PERFCOUNTER7_LOW; +typedef union TCF_PERFCOUNTER8_LOW regTCF_PERFCOUNTER8_LOW; +typedef union TCF_PERFCOUNTER9_LOW regTCF_PERFCOUNTER9_LOW; +typedef union TCF_PERFCOUNTER10_LOW regTCF_PERFCOUNTER10_LOW; +typedef union TCF_PERFCOUNTER11_LOW regTCF_PERFCOUNTER11_LOW; +typedef union TCF_DEBUG regTCF_DEBUG; +typedef union TCA_FIFO_DEBUG regTCA_FIFO_DEBUG; +typedef union TCA_PROBE_DEBUG regTCA_PROBE_DEBUG; +typedef union TCA_TPC_DEBUG regTCA_TPC_DEBUG; +typedef union TCB_CORE_DEBUG regTCB_CORE_DEBUG; +typedef union TCB_TAG0_DEBUG regTCB_TAG0_DEBUG; +typedef union TCB_TAG1_DEBUG regTCB_TAG1_DEBUG; +typedef union TCB_TAG2_DEBUG regTCB_TAG2_DEBUG; +typedef union TCB_TAG3_DEBUG regTCB_TAG3_DEBUG; +typedef union TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG regTCB_FETCH_GEN_SECTOR_WALKER0_DEBUG; +typedef union TCB_FETCH_GEN_WALKER_DEBUG regTCB_FETCH_GEN_WALKER_DEBUG; +typedef union TCB_FETCH_GEN_PIPE0_DEBUG regTCB_FETCH_GEN_PIPE0_DEBUG; +typedef union TCD_INPUT0_DEBUG regTCD_INPUT0_DEBUG; +typedef union TCD_DEGAMMA_DEBUG regTCD_DEGAMMA_DEBUG; +typedef union TCD_DXTMUX_SCTARB_DEBUG regTCD_DXTMUX_SCTARB_DEBUG; +typedef union TCD_DXTC_ARB_DEBUG regTCD_DXTC_ARB_DEBUG; +typedef union TCD_STALLS_DEBUG regTCD_STALLS_DEBUG; +typedef union TCO_STALLS_DEBUG regTCO_STALLS_DEBUG; +typedef union TCO_QUAD0_DEBUG0 regTCO_QUAD0_DEBUG0; +typedef union TCO_QUAD0_DEBUG1 regTCO_QUAD0_DEBUG1; +typedef union SQ_GPR_MANAGEMENT regSQ_GPR_MANAGEMENT; +typedef union SQ_FLOW_CONTROL regSQ_FLOW_CONTROL; +typedef union SQ_INST_STORE_MANAGMENT regSQ_INST_STORE_MANAGMENT; +typedef union SQ_RESOURCE_MANAGMENT regSQ_RESOURCE_MANAGMENT; +typedef union SQ_EO_RT regSQ_EO_RT; +typedef union SQ_DEBUG_MISC regSQ_DEBUG_MISC; +typedef union SQ_ACTIVITY_METER_CNTL regSQ_ACTIVITY_METER_CNTL; +typedef union SQ_ACTIVITY_METER_STATUS regSQ_ACTIVITY_METER_STATUS; +typedef union SQ_INPUT_ARB_PRIORITY regSQ_INPUT_ARB_PRIORITY; +typedef union SQ_THREAD_ARB_PRIORITY regSQ_THREAD_ARB_PRIORITY; +typedef union SQ_VS_WATCHDOG_TIMER regSQ_VS_WATCHDOG_TIMER; +typedef union SQ_PS_WATCHDOG_TIMER regSQ_PS_WATCHDOG_TIMER; +typedef union SQ_INT_CNTL regSQ_INT_CNTL; +typedef union SQ_INT_STATUS regSQ_INT_STATUS; +typedef union SQ_INT_ACK regSQ_INT_ACK; +typedef union SQ_DEBUG_INPUT_FSM regSQ_DEBUG_INPUT_FSM; +typedef union SQ_DEBUG_CONST_MGR_FSM regSQ_DEBUG_CONST_MGR_FSM; +typedef union SQ_DEBUG_TP_FSM regSQ_DEBUG_TP_FSM; +typedef union SQ_DEBUG_FSM_ALU_0 regSQ_DEBUG_FSM_ALU_0; +typedef union SQ_DEBUG_FSM_ALU_1 regSQ_DEBUG_FSM_ALU_1; +typedef union SQ_DEBUG_EXP_ALLOC regSQ_DEBUG_EXP_ALLOC; +typedef union SQ_DEBUG_PTR_BUFF regSQ_DEBUG_PTR_BUFF; +typedef union SQ_DEBUG_GPR_VTX regSQ_DEBUG_GPR_VTX; +typedef union SQ_DEBUG_GPR_PIX regSQ_DEBUG_GPR_PIX; +typedef union SQ_DEBUG_TB_STATUS_SEL regSQ_DEBUG_TB_STATUS_SEL; +typedef union SQ_DEBUG_VTX_TB_0 regSQ_DEBUG_VTX_TB_0; +typedef union SQ_DEBUG_VTX_TB_1 regSQ_DEBUG_VTX_TB_1; +typedef union SQ_DEBUG_VTX_TB_STATUS_REG regSQ_DEBUG_VTX_TB_STATUS_REG; +typedef union SQ_DEBUG_VTX_TB_STATE_MEM regSQ_DEBUG_VTX_TB_STATE_MEM; +typedef union SQ_DEBUG_PIX_TB_0 regSQ_DEBUG_PIX_TB_0; +typedef union SQ_DEBUG_PIX_TB_STATUS_REG_0 regSQ_DEBUG_PIX_TB_STATUS_REG_0; +typedef union SQ_DEBUG_PIX_TB_STATUS_REG_1 regSQ_DEBUG_PIX_TB_STATUS_REG_1; +typedef union SQ_DEBUG_PIX_TB_STATUS_REG_2 regSQ_DEBUG_PIX_TB_STATUS_REG_2; +typedef union SQ_DEBUG_PIX_TB_STATUS_REG_3 regSQ_DEBUG_PIX_TB_STATUS_REG_3; +typedef union SQ_DEBUG_PIX_TB_STATE_MEM regSQ_DEBUG_PIX_TB_STATE_MEM; +typedef union SQ_PERFCOUNTER0_SELECT regSQ_PERFCOUNTER0_SELECT; +typedef union SQ_PERFCOUNTER1_SELECT regSQ_PERFCOUNTER1_SELECT; +typedef union SQ_PERFCOUNTER2_SELECT regSQ_PERFCOUNTER2_SELECT; +typedef union SQ_PERFCOUNTER3_SELECT regSQ_PERFCOUNTER3_SELECT; +typedef union SQ_PERFCOUNTER0_LOW regSQ_PERFCOUNTER0_LOW; +typedef union SQ_PERFCOUNTER0_HI regSQ_PERFCOUNTER0_HI; +typedef union SQ_PERFCOUNTER1_LOW regSQ_PERFCOUNTER1_LOW; +typedef union SQ_PERFCOUNTER1_HI regSQ_PERFCOUNTER1_HI; +typedef union SQ_PERFCOUNTER2_LOW regSQ_PERFCOUNTER2_LOW; +typedef union SQ_PERFCOUNTER2_HI regSQ_PERFCOUNTER2_HI; +typedef union SQ_PERFCOUNTER3_LOW regSQ_PERFCOUNTER3_LOW; +typedef union SQ_PERFCOUNTER3_HI regSQ_PERFCOUNTER3_HI; +typedef union SX_PERFCOUNTER0_SELECT regSX_PERFCOUNTER0_SELECT; +typedef union SX_PERFCOUNTER0_LOW regSX_PERFCOUNTER0_LOW; +typedef union SX_PERFCOUNTER0_HI regSX_PERFCOUNTER0_HI; +typedef union SQ_INSTRUCTION_ALU_0 regSQ_INSTRUCTION_ALU_0; +typedef union SQ_INSTRUCTION_ALU_1 regSQ_INSTRUCTION_ALU_1; +typedef union SQ_INSTRUCTION_ALU_2 regSQ_INSTRUCTION_ALU_2; +typedef union SQ_INSTRUCTION_CF_EXEC_0 regSQ_INSTRUCTION_CF_EXEC_0; +typedef union SQ_INSTRUCTION_CF_EXEC_1 regSQ_INSTRUCTION_CF_EXEC_1; +typedef union SQ_INSTRUCTION_CF_EXEC_2 regSQ_INSTRUCTION_CF_EXEC_2; +typedef union SQ_INSTRUCTION_CF_LOOP_0 regSQ_INSTRUCTION_CF_LOOP_0; +typedef union SQ_INSTRUCTION_CF_LOOP_1 regSQ_INSTRUCTION_CF_LOOP_1; +typedef union SQ_INSTRUCTION_CF_LOOP_2 regSQ_INSTRUCTION_CF_LOOP_2; +typedef union SQ_INSTRUCTION_CF_JMP_CALL_0 regSQ_INSTRUCTION_CF_JMP_CALL_0; +typedef union SQ_INSTRUCTION_CF_JMP_CALL_1 regSQ_INSTRUCTION_CF_JMP_CALL_1; +typedef union SQ_INSTRUCTION_CF_JMP_CALL_2 regSQ_INSTRUCTION_CF_JMP_CALL_2; +typedef union SQ_INSTRUCTION_CF_ALLOC_0 regSQ_INSTRUCTION_CF_ALLOC_0; +typedef union SQ_INSTRUCTION_CF_ALLOC_1 regSQ_INSTRUCTION_CF_ALLOC_1; +typedef union SQ_INSTRUCTION_CF_ALLOC_2 regSQ_INSTRUCTION_CF_ALLOC_2; +typedef union SQ_INSTRUCTION_TFETCH_0 regSQ_INSTRUCTION_TFETCH_0; +typedef union SQ_INSTRUCTION_TFETCH_1 regSQ_INSTRUCTION_TFETCH_1; +typedef union SQ_INSTRUCTION_TFETCH_2 regSQ_INSTRUCTION_TFETCH_2; +typedef union SQ_INSTRUCTION_VFETCH_0 regSQ_INSTRUCTION_VFETCH_0; +typedef union SQ_INSTRUCTION_VFETCH_1 regSQ_INSTRUCTION_VFETCH_1; +typedef union SQ_INSTRUCTION_VFETCH_2 regSQ_INSTRUCTION_VFETCH_2; +typedef union SQ_CONSTANT_0 regSQ_CONSTANT_0; +typedef union SQ_CONSTANT_1 regSQ_CONSTANT_1; +typedef union SQ_CONSTANT_2 regSQ_CONSTANT_2; +typedef union SQ_CONSTANT_3 regSQ_CONSTANT_3; +typedef union SQ_FETCH_0 regSQ_FETCH_0; +typedef union SQ_FETCH_1 regSQ_FETCH_1; +typedef union SQ_FETCH_2 regSQ_FETCH_2; +typedef union SQ_FETCH_3 regSQ_FETCH_3; +typedef union SQ_FETCH_4 regSQ_FETCH_4; +typedef union SQ_FETCH_5 regSQ_FETCH_5; +typedef union SQ_CONSTANT_VFETCH_0 regSQ_CONSTANT_VFETCH_0; +typedef union SQ_CONSTANT_VFETCH_1 regSQ_CONSTANT_VFETCH_1; +typedef union SQ_CONSTANT_T2 regSQ_CONSTANT_T2; +typedef union SQ_CONSTANT_T3 regSQ_CONSTANT_T3; +typedef union SQ_CF_BOOLEANS regSQ_CF_BOOLEANS; +typedef union SQ_CF_LOOP regSQ_CF_LOOP; +typedef union SQ_CONSTANT_RT_0 regSQ_CONSTANT_RT_0; +typedef union SQ_CONSTANT_RT_1 regSQ_CONSTANT_RT_1; +typedef union SQ_CONSTANT_RT_2 regSQ_CONSTANT_RT_2; +typedef union SQ_CONSTANT_RT_3 regSQ_CONSTANT_RT_3; +typedef union SQ_FETCH_RT_0 regSQ_FETCH_RT_0; +typedef union SQ_FETCH_RT_1 regSQ_FETCH_RT_1; +typedef union SQ_FETCH_RT_2 regSQ_FETCH_RT_2; +typedef union SQ_FETCH_RT_3 regSQ_FETCH_RT_3; +typedef union SQ_FETCH_RT_4 regSQ_FETCH_RT_4; +typedef union SQ_FETCH_RT_5 regSQ_FETCH_RT_5; +typedef union SQ_CF_RT_BOOLEANS regSQ_CF_RT_BOOLEANS; +typedef union SQ_CF_RT_LOOP regSQ_CF_RT_LOOP; +typedef union SQ_VS_PROGRAM regSQ_VS_PROGRAM; +typedef union SQ_PS_PROGRAM regSQ_PS_PROGRAM; +typedef union SQ_CF_PROGRAM_SIZE regSQ_CF_PROGRAM_SIZE; +typedef union SQ_INTERPOLATOR_CNTL regSQ_INTERPOLATOR_CNTL; +typedef union SQ_PROGRAM_CNTL regSQ_PROGRAM_CNTL; +typedef union SQ_WRAPPING_0 regSQ_WRAPPING_0; +typedef union SQ_WRAPPING_1 regSQ_WRAPPING_1; +typedef union SQ_VS_CONST regSQ_VS_CONST; +typedef union SQ_PS_CONST regSQ_PS_CONST; +typedef union SQ_CONTEXT_MISC regSQ_CONTEXT_MISC; +typedef union SQ_CF_RD_BASE regSQ_CF_RD_BASE; +typedef union SQ_DEBUG_MISC_0 regSQ_DEBUG_MISC_0; +typedef union SQ_DEBUG_MISC_1 regSQ_DEBUG_MISC_1; +typedef union MH_ARBITER_CONFIG regMH_ARBITER_CONFIG; +typedef union MH_CLNT_AXI_ID_REUSE regMH_CLNT_AXI_ID_REUSE; +typedef union MH_INTERRUPT_MASK regMH_INTERRUPT_MASK; +typedef union MH_INTERRUPT_STATUS regMH_INTERRUPT_STATUS; +typedef union MH_INTERRUPT_CLEAR regMH_INTERRUPT_CLEAR; +typedef union MH_AXI_ERROR regMH_AXI_ERROR; +typedef union MH_PERFCOUNTER0_SELECT regMH_PERFCOUNTER0_SELECT; +typedef union MH_PERFCOUNTER1_SELECT regMH_PERFCOUNTER1_SELECT; +typedef union MH_PERFCOUNTER0_CONFIG regMH_PERFCOUNTER0_CONFIG; +typedef union MH_PERFCOUNTER1_CONFIG regMH_PERFCOUNTER1_CONFIG; +typedef union MH_PERFCOUNTER0_LOW regMH_PERFCOUNTER0_LOW; +typedef union MH_PERFCOUNTER1_LOW regMH_PERFCOUNTER1_LOW; +typedef union MH_PERFCOUNTER0_HI regMH_PERFCOUNTER0_HI; +typedef union MH_PERFCOUNTER1_HI regMH_PERFCOUNTER1_HI; +typedef union MH_DEBUG_CTRL regMH_DEBUG_CTRL; +typedef union MH_DEBUG_DATA regMH_DEBUG_DATA; +typedef union MH_AXI_HALT_CONTROL regMH_AXI_HALT_CONTROL; +typedef union MH_MMU_CONFIG regMH_MMU_CONFIG; +typedef union MH_MMU_VA_RANGE regMH_MMU_VA_RANGE; +typedef union MH_MMU_PT_BASE regMH_MMU_PT_BASE; +typedef union MH_MMU_PAGE_FAULT regMH_MMU_PAGE_FAULT; +typedef union MH_MMU_TRAN_ERROR regMH_MMU_TRAN_ERROR; +typedef union MH_MMU_INVALIDATE regMH_MMU_INVALIDATE; +typedef union MH_MMU_MPU_BASE regMH_MMU_MPU_BASE; +typedef union MH_MMU_MPU_END regMH_MMU_MPU_END; +typedef union WAIT_UNTIL regWAIT_UNTIL; +typedef union RBBM_ISYNC_CNTL regRBBM_ISYNC_CNTL; +typedef union RBBM_STATUS regRBBM_STATUS; +typedef union RBBM_DSPLY regRBBM_DSPLY; +typedef union RBBM_RENDER_LATEST regRBBM_RENDER_LATEST; +typedef union RBBM_RTL_RELEASE regRBBM_RTL_RELEASE; +typedef union RBBM_PATCH_RELEASE regRBBM_PATCH_RELEASE; +typedef union RBBM_AUXILIARY_CONFIG regRBBM_AUXILIARY_CONFIG; +typedef union RBBM_PERIPHID0 regRBBM_PERIPHID0; +typedef union RBBM_PERIPHID1 regRBBM_PERIPHID1; +typedef union RBBM_PERIPHID2 regRBBM_PERIPHID2; +typedef union RBBM_PERIPHID3 regRBBM_PERIPHID3; +typedef union RBBM_CNTL regRBBM_CNTL; +typedef union RBBM_SKEW_CNTL regRBBM_SKEW_CNTL; +typedef union RBBM_SOFT_RESET regRBBM_SOFT_RESET; +typedef union RBBM_PM_OVERRIDE1 regRBBM_PM_OVERRIDE1; +typedef union RBBM_PM_OVERRIDE2 regRBBM_PM_OVERRIDE2; +typedef union GC_SYS_IDLE regGC_SYS_IDLE; +typedef union NQWAIT_UNTIL regNQWAIT_UNTIL; +typedef union RBBM_DEBUG_OUT regRBBM_DEBUG_OUT; +typedef union RBBM_DEBUG_CNTL regRBBM_DEBUG_CNTL; +typedef union RBBM_DEBUG regRBBM_DEBUG; +typedef union RBBM_READ_ERROR regRBBM_READ_ERROR; +typedef union RBBM_WAIT_IDLE_CLOCKS regRBBM_WAIT_IDLE_CLOCKS; +typedef union RBBM_INT_CNTL regRBBM_INT_CNTL; +typedef union RBBM_INT_STATUS regRBBM_INT_STATUS; +typedef union RBBM_INT_ACK regRBBM_INT_ACK; +typedef union MASTER_INT_SIGNAL regMASTER_INT_SIGNAL; +typedef union RBBM_PERFCOUNTER1_SELECT regRBBM_PERFCOUNTER1_SELECT; +typedef union RBBM_PERFCOUNTER1_LO regRBBM_PERFCOUNTER1_LO; +typedef union RBBM_PERFCOUNTER1_HI regRBBM_PERFCOUNTER1_HI; +typedef union CP_RB_BASE regCP_RB_BASE; +typedef union CP_RB_CNTL regCP_RB_CNTL; +typedef union CP_RB_RPTR_ADDR regCP_RB_RPTR_ADDR; +typedef union CP_RB_RPTR regCP_RB_RPTR; +typedef union CP_RB_RPTR_WR regCP_RB_RPTR_WR; +typedef union CP_RB_WPTR regCP_RB_WPTR; +typedef union CP_RB_WPTR_DELAY regCP_RB_WPTR_DELAY; +typedef union CP_RB_WPTR_BASE regCP_RB_WPTR_BASE; +typedef union CP_IB1_BASE regCP_IB1_BASE; +typedef union CP_IB1_BUFSZ regCP_IB1_BUFSZ; +typedef union CP_IB2_BASE regCP_IB2_BASE; +typedef union CP_IB2_BUFSZ regCP_IB2_BUFSZ; +typedef union CP_ST_BASE regCP_ST_BASE; +typedef union CP_ST_BUFSZ regCP_ST_BUFSZ; +typedef union CP_QUEUE_THRESHOLDS regCP_QUEUE_THRESHOLDS; +typedef union CP_MEQ_THRESHOLDS regCP_MEQ_THRESHOLDS; +typedef union CP_CSQ_AVAIL regCP_CSQ_AVAIL; +typedef union CP_STQ_AVAIL regCP_STQ_AVAIL; +typedef union CP_MEQ_AVAIL regCP_MEQ_AVAIL; +typedef union CP_CSQ_RB_STAT regCP_CSQ_RB_STAT; +typedef union CP_CSQ_IB1_STAT regCP_CSQ_IB1_STAT; +typedef union CP_CSQ_IB2_STAT regCP_CSQ_IB2_STAT; +typedef union CP_NON_PREFETCH_CNTRS regCP_NON_PREFETCH_CNTRS; +typedef union CP_STQ_ST_STAT regCP_STQ_ST_STAT; +typedef union CP_MEQ_STAT regCP_MEQ_STAT; +typedef union CP_MIU_TAG_STAT regCP_MIU_TAG_STAT; +typedef union CP_CMD_INDEX regCP_CMD_INDEX; +typedef union CP_CMD_DATA regCP_CMD_DATA; +typedef union CP_ME_CNTL regCP_ME_CNTL; +typedef union CP_ME_STATUS regCP_ME_STATUS; +typedef union CP_ME_RAM_WADDR regCP_ME_RAM_WADDR; +typedef union CP_ME_RAM_RADDR regCP_ME_RAM_RADDR; +typedef union CP_ME_RAM_DATA regCP_ME_RAM_DATA; +typedef union CP_ME_RDADDR regCP_ME_RDADDR; +typedef union CP_DEBUG regCP_DEBUG; +typedef union SCRATCH_REG0 regSCRATCH_REG0; +typedef union GUI_SCRATCH_REG0 regGUI_SCRATCH_REG0; +typedef union SCRATCH_REG1 regSCRATCH_REG1; +typedef union GUI_SCRATCH_REG1 regGUI_SCRATCH_REG1; +typedef union SCRATCH_REG2 regSCRATCH_REG2; +typedef union GUI_SCRATCH_REG2 regGUI_SCRATCH_REG2; +typedef union SCRATCH_REG3 regSCRATCH_REG3; +typedef union GUI_SCRATCH_REG3 regGUI_SCRATCH_REG3; +typedef union SCRATCH_REG4 regSCRATCH_REG4; +typedef union GUI_SCRATCH_REG4 regGUI_SCRATCH_REG4; +typedef union SCRATCH_REG5 regSCRATCH_REG5; +typedef union GUI_SCRATCH_REG5 regGUI_SCRATCH_REG5; +typedef union SCRATCH_REG6 regSCRATCH_REG6; +typedef union GUI_SCRATCH_REG6 regGUI_SCRATCH_REG6; +typedef union SCRATCH_REG7 regSCRATCH_REG7; +typedef union GUI_SCRATCH_REG7 regGUI_SCRATCH_REG7; +typedef union SCRATCH_UMSK regSCRATCH_UMSK; +typedef union SCRATCH_ADDR regSCRATCH_ADDR; +typedef union CP_ME_VS_EVENT_SRC regCP_ME_VS_EVENT_SRC; +typedef union CP_ME_VS_EVENT_ADDR regCP_ME_VS_EVENT_ADDR; +typedef union CP_ME_VS_EVENT_DATA regCP_ME_VS_EVENT_DATA; +typedef union CP_ME_VS_EVENT_ADDR_SWM regCP_ME_VS_EVENT_ADDR_SWM; +typedef union CP_ME_VS_EVENT_DATA_SWM regCP_ME_VS_EVENT_DATA_SWM; +typedef union CP_ME_PS_EVENT_SRC regCP_ME_PS_EVENT_SRC; +typedef union CP_ME_PS_EVENT_ADDR regCP_ME_PS_EVENT_ADDR; +typedef union CP_ME_PS_EVENT_DATA regCP_ME_PS_EVENT_DATA; +typedef union CP_ME_PS_EVENT_ADDR_SWM regCP_ME_PS_EVENT_ADDR_SWM; +typedef union CP_ME_PS_EVENT_DATA_SWM regCP_ME_PS_EVENT_DATA_SWM; +typedef union CP_ME_CF_EVENT_SRC regCP_ME_CF_EVENT_SRC; +typedef union CP_ME_CF_EVENT_ADDR regCP_ME_CF_EVENT_ADDR; +typedef union CP_ME_CF_EVENT_DATA regCP_ME_CF_EVENT_DATA; +typedef union CP_ME_NRT_ADDR regCP_ME_NRT_ADDR; +typedef union CP_ME_NRT_DATA regCP_ME_NRT_DATA; +typedef union CP_ME_VS_FETCH_DONE_SRC regCP_ME_VS_FETCH_DONE_SRC; +typedef union CP_ME_VS_FETCH_DONE_ADDR regCP_ME_VS_FETCH_DONE_ADDR; +typedef union CP_ME_VS_FETCH_DONE_DATA regCP_ME_VS_FETCH_DONE_DATA; +typedef union CP_INT_CNTL regCP_INT_CNTL; +typedef union CP_INT_STATUS regCP_INT_STATUS; +typedef union CP_INT_ACK regCP_INT_ACK; +typedef union CP_PFP_UCODE_ADDR regCP_PFP_UCODE_ADDR; +typedef union CP_PFP_UCODE_DATA regCP_PFP_UCODE_DATA; +typedef union CP_PERFMON_CNTL regCP_PERFMON_CNTL; +typedef union CP_PERFCOUNTER_SELECT regCP_PERFCOUNTER_SELECT; +typedef union CP_PERFCOUNTER_LO regCP_PERFCOUNTER_LO; +typedef union CP_PERFCOUNTER_HI regCP_PERFCOUNTER_HI; +typedef union CP_BIN_MASK_LO regCP_BIN_MASK_LO; +typedef union CP_BIN_MASK_HI regCP_BIN_MASK_HI; +typedef union CP_BIN_SELECT_LO regCP_BIN_SELECT_LO; +typedef union CP_BIN_SELECT_HI regCP_BIN_SELECT_HI; +typedef union CP_NV_FLAGS_0 regCP_NV_FLAGS_0; +typedef union CP_NV_FLAGS_1 regCP_NV_FLAGS_1; +typedef union CP_NV_FLAGS_2 regCP_NV_FLAGS_2; +typedef union CP_NV_FLAGS_3 regCP_NV_FLAGS_3; +typedef union CP_STATE_DEBUG_INDEX regCP_STATE_DEBUG_INDEX; +typedef union CP_STATE_DEBUG_DATA regCP_STATE_DEBUG_DATA; +typedef union CP_PROG_COUNTER regCP_PROG_COUNTER; +typedef union CP_STAT regCP_STAT; +typedef union BIOS_0_SCRATCH regBIOS_0_SCRATCH; +typedef union BIOS_1_SCRATCH regBIOS_1_SCRATCH; +typedef union BIOS_2_SCRATCH regBIOS_2_SCRATCH; +typedef union BIOS_3_SCRATCH regBIOS_3_SCRATCH; +typedef union BIOS_4_SCRATCH regBIOS_4_SCRATCH; +typedef union BIOS_5_SCRATCH regBIOS_5_SCRATCH; +typedef union BIOS_6_SCRATCH regBIOS_6_SCRATCH; +typedef union BIOS_7_SCRATCH regBIOS_7_SCRATCH; +typedef union BIOS_8_SCRATCH regBIOS_8_SCRATCH; +typedef union BIOS_9_SCRATCH regBIOS_9_SCRATCH; +typedef union BIOS_10_SCRATCH regBIOS_10_SCRATCH; +typedef union BIOS_11_SCRATCH regBIOS_11_SCRATCH; +typedef union BIOS_12_SCRATCH regBIOS_12_SCRATCH; +typedef union BIOS_13_SCRATCH regBIOS_13_SCRATCH; +typedef union BIOS_14_SCRATCH regBIOS_14_SCRATCH; +typedef union BIOS_15_SCRATCH regBIOS_15_SCRATCH; +typedef union COHER_SIZE_PM4 regCOHER_SIZE_PM4; +typedef union COHER_BASE_PM4 regCOHER_BASE_PM4; +typedef union COHER_STATUS_PM4 regCOHER_STATUS_PM4; +typedef union COHER_SIZE_HOST regCOHER_SIZE_HOST; +typedef union COHER_BASE_HOST regCOHER_BASE_HOST; +typedef union COHER_STATUS_HOST regCOHER_STATUS_HOST; +typedef union COHER_DEST_BASE_0 regCOHER_DEST_BASE_0; +typedef union COHER_DEST_BASE_1 regCOHER_DEST_BASE_1; +typedef union COHER_DEST_BASE_2 regCOHER_DEST_BASE_2; +typedef union COHER_DEST_BASE_3 regCOHER_DEST_BASE_3; +typedef union COHER_DEST_BASE_4 regCOHER_DEST_BASE_4; +typedef union COHER_DEST_BASE_5 regCOHER_DEST_BASE_5; +typedef union COHER_DEST_BASE_6 regCOHER_DEST_BASE_6; +typedef union COHER_DEST_BASE_7 regCOHER_DEST_BASE_7; +typedef union RB_SURFACE_INFO regRB_SURFACE_INFO; +typedef union RB_COLOR_INFO regRB_COLOR_INFO; +typedef union RB_DEPTH_INFO regRB_DEPTH_INFO; +typedef union RB_STENCILREFMASK regRB_STENCILREFMASK; +typedef union RB_ALPHA_REF regRB_ALPHA_REF; +typedef union RB_COLOR_MASK regRB_COLOR_MASK; +typedef union RB_BLEND_RED regRB_BLEND_RED; +typedef union RB_BLEND_GREEN regRB_BLEND_GREEN; +typedef union RB_BLEND_BLUE regRB_BLEND_BLUE; +typedef union RB_BLEND_ALPHA regRB_BLEND_ALPHA; +typedef union RB_FOG_COLOR regRB_FOG_COLOR; +typedef union RB_STENCILREFMASK_BF regRB_STENCILREFMASK_BF; +typedef union RB_DEPTHCONTROL regRB_DEPTHCONTROL; +typedef union RB_BLENDCONTROL regRB_BLENDCONTROL; +typedef union RB_COLORCONTROL regRB_COLORCONTROL; +typedef union RB_MODECONTROL regRB_MODECONTROL; +typedef union RB_COLOR_DEST_MASK regRB_COLOR_DEST_MASK; +typedef union RB_COPY_CONTROL regRB_COPY_CONTROL; +typedef union RB_COPY_DEST_BASE regRB_COPY_DEST_BASE; +typedef union RB_COPY_DEST_PITCH regRB_COPY_DEST_PITCH; +typedef union RB_COPY_DEST_INFO regRB_COPY_DEST_INFO; +typedef union RB_COPY_DEST_PIXEL_OFFSET regRB_COPY_DEST_PIXEL_OFFSET; +typedef union RB_DEPTH_CLEAR regRB_DEPTH_CLEAR; +typedef union RB_SAMPLE_COUNT_CTL regRB_SAMPLE_COUNT_CTL; +typedef union RB_SAMPLE_COUNT_ADDR regRB_SAMPLE_COUNT_ADDR; +typedef union RB_BC_CONTROL regRB_BC_CONTROL; +typedef union RB_EDRAM_INFO regRB_EDRAM_INFO; +typedef union RB_CRC_RD_PORT regRB_CRC_RD_PORT; +typedef union RB_CRC_CONTROL regRB_CRC_CONTROL; +typedef union RB_CRC_MASK regRB_CRC_MASK; +typedef union RB_PERFCOUNTER0_SELECT regRB_PERFCOUNTER0_SELECT; +typedef union RB_PERFCOUNTER0_LOW regRB_PERFCOUNTER0_LOW; +typedef union RB_PERFCOUNTER0_HI regRB_PERFCOUNTER0_HI; +typedef union RB_TOTAL_SAMPLES regRB_TOTAL_SAMPLES; +typedef union RB_ZPASS_SAMPLES regRB_ZPASS_SAMPLES; +typedef union RB_ZFAIL_SAMPLES regRB_ZFAIL_SAMPLES; +typedef union RB_SFAIL_SAMPLES regRB_SFAIL_SAMPLES; +typedef union RB_DEBUG_0 regRB_DEBUG_0; +typedef union RB_DEBUG_1 regRB_DEBUG_1; +typedef union RB_DEBUG_2 regRB_DEBUG_2; +typedef union RB_DEBUG_3 regRB_DEBUG_3; +typedef union RB_DEBUG_4 regRB_DEBUG_4; +typedef union RB_FLAG_CONTROL regRB_FLAG_CONTROL; +typedef union RB_BC_SPARES regRB_BC_SPARES; +typedef union BC_DUMMY_CRAYRB_ENUMS regBC_DUMMY_CRAYRB_ENUMS; +typedef union BC_DUMMY_CRAYRB_MOREENUMS regBC_DUMMY_CRAYRB_MOREENUMS; +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/10/yamatoix.h b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamatoix.h new file mode 100644 index 000000000000..ba259a6c9d5f --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/10/yamatoix.h @@ -0,0 +1,169 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _yamatoix_h +#define _yamatoix_h + +#ifdef __cplusplus +extern "C" { +#endif // __cplusplus + +// [SUDEBUGIND] : Indirect Registers + +#define ixCLIPPER_DEBUG_REG00 0x0000 +#define ixCLIPPER_DEBUG_REG01 0x0001 +#define ixCLIPPER_DEBUG_REG02 0x0002 +#define ixCLIPPER_DEBUG_REG03 0x0003 +#define ixCLIPPER_DEBUG_REG04 0x0004 +#define ixCLIPPER_DEBUG_REG05 0x0005 +#define ixCLIPPER_DEBUG_REG09 0x0009 +#define ixCLIPPER_DEBUG_REG10 0x000A +#define ixCLIPPER_DEBUG_REG11 0x000B +#define ixCLIPPER_DEBUG_REG12 0x000C +#define ixCLIPPER_DEBUG_REG13 0x000D +#define ixSXIFCCG_DEBUG_REG0 0x0011 +#define ixSXIFCCG_DEBUG_REG1 0x0012 +#define ixSXIFCCG_DEBUG_REG2 0x0013 +#define ixSXIFCCG_DEBUG_REG3 0x0014 +#define ixSETUP_DEBUG_REG0 0x0015 +#define ixSETUP_DEBUG_REG1 0x0016 +#define ixSETUP_DEBUG_REG2 0x0017 +#define ixSETUP_DEBUG_REG3 0x0018 +#define ixSETUP_DEBUG_REG4 0x0019 +#define ixSETUP_DEBUG_REG5 0x001A + +// [SCDEBUGIND] : Indirect Registers + +#define ixSC_DEBUG_0 0x0000 +#define ixSC_DEBUG_1 0x0001 +#define ixSC_DEBUG_2 0x0002 +#define ixSC_DEBUG_3 0x0003 +#define ixSC_DEBUG_4 0x0004 +#define ixSC_DEBUG_5 0x0005 +#define ixSC_DEBUG_6 0x0006 +#define ixSC_DEBUG_7 0x0007 +#define ixSC_DEBUG_8 0x0008 +#define ixSC_DEBUG_9 0x0009 +#define ixSC_DEBUG_10 0x000A +#define ixSC_DEBUG_11 0x000B +#define ixSC_DEBUG_12 0x000C + +// [VGTDEBUGIND] : Indirect Registers + +#define ixVGT_DEBUG_REG0 0x0000 +#define ixVGT_DEBUG_REG1 0x0001 +#define ixVGT_DEBUG_REG3 0x0003 +#define ixVGT_DEBUG_REG6 0x0006 +#define ixVGT_DEBUG_REG7 0x0007 +#define ixVGT_DEBUG_REG8 0x0008 +#define ixVGT_DEBUG_REG9 0x0009 +#define ixVGT_DEBUG_REG10 0x000A +#define ixVGT_DEBUG_REG12 0x000C +#define ixVGT_DEBUG_REG13 0x000D +#define ixVGT_DEBUG_REG14 0x000E +#define ixVGT_DEBUG_REG15 0x000F +#define ixVGT_DEBUG_REG16 0x0010 +#define ixVGT_DEBUG_REG17 0x0011 +#define ixVGT_DEBUG_REG18 0x0012 +#define ixVGT_DEBUG_REG20 0x0014 +#define ixVGT_DEBUG_REG21 0x0015 + +// [MHDEBUGIND] : Indirect Registers + +#define ixMH_DEBUG_REG00 0x0000 +#define ixMH_DEBUG_REG01 0x0001 +#define ixMH_DEBUG_REG02 0x0002 +#define ixMH_DEBUG_REG03 0x0003 +#define ixMH_DEBUG_REG04 0x0004 +#define ixMH_DEBUG_REG05 0x0005 +#define ixMH_DEBUG_REG06 0x0006 +#define ixMH_DEBUG_REG07 0x0007 +#define ixMH_DEBUG_REG08 0x0008 +#define ixMH_DEBUG_REG09 0x0009 +#define ixMH_DEBUG_REG10 0x000A +#define ixMH_DEBUG_REG11 0x000B +#define ixMH_DEBUG_REG12 0x000C +#define ixMH_DEBUG_REG13 0x000D +#define ixMH_DEBUG_REG14 0x000E +#define ixMH_DEBUG_REG15 0x000F +#define ixMH_DEBUG_REG16 0x0010 +#define ixMH_DEBUG_REG17 0x0011 +#define ixMH_DEBUG_REG18 0x0012 +#define ixMH_DEBUG_REG19 0x0013 +#define ixMH_DEBUG_REG20 0x0014 +#define ixMH_DEBUG_REG21 0x0015 +#define ixMH_DEBUG_REG22 0x0016 +#define ixMH_DEBUG_REG23 0x0017 +#define ixMH_DEBUG_REG24 0x0018 +#define ixMH_DEBUG_REG25 0x0019 +#define ixMH_DEBUG_REG26 0x001A +#define ixMH_DEBUG_REG27 0x001B +#define ixMH_DEBUG_REG28 0x001C +#define ixMH_DEBUG_REG29 0x001D +#define ixMH_DEBUG_REG30 0x001E +#define ixMH_DEBUG_REG31 0x001F +#define ixMH_DEBUG_REG32 0x0020 +#define ixMH_DEBUG_REG33 0x0021 +#define ixMH_DEBUG_REG34 0x0022 +#define ixMH_DEBUG_REG35 0x0023 +#define ixMH_DEBUG_REG36 0x0024 +#define ixMH_DEBUG_REG37 0x0025 +#define ixMH_DEBUG_REG38 0x0026 +#define ixMH_DEBUG_REG39 0x0027 +#define ixMH_DEBUG_REG40 0x0028 +#define ixMH_DEBUG_REG41 0x0029 +#define ixMH_DEBUG_REG42 0x002A +#define ixMH_DEBUG_REG43 0x002B +#define ixMH_DEBUG_REG44 0x002C +#define ixMH_DEBUG_REG45 0x002D +#define ixMH_DEBUG_REG46 0x002E +#define ixMH_DEBUG_REG47 0x002F +#define ixMH_DEBUG_REG48 0x0030 +#define ixMH_DEBUG_REG49 0x0031 +#define ixMH_DEBUG_REG50 0x0032 +#define ixMH_DEBUG_REG51 0x0033 +#define ixMH_DEBUG_REG52 0x0034 +#define ixMH_DEBUG_REG53 0x0035 +#define ixMH_DEBUG_REG54 0x0036 +#define ixMH_DEBUG_REG55 0x0037 +#define ixMH_DEBUG_REG56 0x0038 +#define ixMH_DEBUG_REG57 0x0039 +#define ixMH_DEBUG_REG58 0x003A +#define ixMH_DEBUG_REG59 0x003B +#define ixMH_DEBUG_REG60 0x003C +#define ixMH_DEBUG_REG61 0x003D +#define ixMH_DEBUG_REG62 0x003E +#define ixMH_DEBUG_REG63 0x003F + + +#ifdef __cplusplus +} +#endif // __cplusplus + +#endif // _yamatob_h + diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_enum.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_enum.h new file mode 100644 index 000000000000..ab11205f1092 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_enum.h @@ -0,0 +1,1867 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_ENUM_HEADER) +#define _yamato_ENUM_HEADER + + + +#ifndef _DRIVER_BUILD +#ifndef GL_ZERO +#define GL__ZERO BLEND_ZERO +#define GL__ONE BLEND_ONE +#define GL__SRC_COLOR BLEND_SRC_COLOR +#define GL__ONE_MINUS_SRC_COLOR BLEND_ONE_MINUS_SRC_COLOR +#define GL__DST_COLOR BLEND_DST_COLOR +#define GL__ONE_MINUS_DST_COLOR BLEND_ONE_MINUS_DST_COLOR +#define GL__SRC_ALPHA BLEND_SRC_ALPHA +#define GL__ONE_MINUS_SRC_ALPHA BLEND_ONE_MINUS_SRC_ALPHA +#define GL__DST_ALPHA BLEND_DST_ALPHA +#define GL__ONE_MINUS_DST_ALPHA BLEND_ONE_MINUS_DST_ALPHA +#define GL__SRC_ALPHA_SATURATE BLEND_SRC_ALPHA_SATURATE +#define GL__CONSTANT_COLOR BLEND_CONSTANT_COLOR +#define GL__ONE_MINUS_CONSTANT_COLOR BLEND_ONE_MINUS_CONSTANT_COLOR +#define GL__CONSTANT_ALPHA BLEND_CONSTANT_ALPHA +#define GL__ONE_MINUS_CONSTANT_ALPHA BLEND_ONE_MINUS_CONSTANT_ALPHA +#endif +#endif + +/******************************************************* + * PA Enums + *******************************************************/ +#ifndef ENUMS_SU_PERFCNT_SELECT_H +#define ENUMS_SU_PERFCNT_SELECT_H +typedef enum SU_PERFCNT_SELECT { + PERF_PAPC_PASX_REQ = 0, + UNUSED1 = 1, + PERF_PAPC_PASX_FIRST_VECTOR = 2, + PERF_PAPC_PASX_SECOND_VECTOR = 3, + PERF_PAPC_PASX_FIRST_DEAD = 4, + PERF_PAPC_PASX_SECOND_DEAD = 5, + PERF_PAPC_PASX_VTX_KILL_DISCARD = 6, + PERF_PAPC_PASX_VTX_NAN_DISCARD = 7, + PERF_PAPC_PA_INPUT_PRIM = 8, + PERF_PAPC_PA_INPUT_NULL_PRIM = 9, + PERF_PAPC_PA_INPUT_EVENT_FLAG = 10, + PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11, + PERF_PAPC_PA_INPUT_END_OF_PACKET = 12, + PERF_PAPC_CLPR_CULL_PRIM = 13, + UNUSED2 = 14, + PERF_PAPC_CLPR_VV_CULL_PRIM = 15, + UNUSED3 = 16, + PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 17, + PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 18, + PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 19, + UNUSED4 = 20, + PERF_PAPC_CLPR_VV_CLIP_PRIM = 21, + UNUSED5 = 22, + PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 23, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 24, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 25, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 26, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 27, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_5 = 28, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_6 = 29, + PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 30, + PERF_PAPC_CLPR_CLIP_PLANE_FAR = 31, + PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 32, + PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 33, + PERF_PAPC_CLPR_CLIP_PLANE_TOP = 34, + PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 35, + PERF_PAPC_CLSM_NULL_PRIM = 36, + PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 37, + PERF_PAPC_CLSM_CLIP_PRIM = 38, + PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 39, + PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 40, + PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 41, + PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 42, + PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 43, + PERF_PAPC_CLSM_OUT_PRIM_CNT_5 = 44, + PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7 = 45, + PERF_PAPC_CLSM_NON_TRIVIAL_CULL = 46, + PERF_PAPC_SU_INPUT_PRIM = 47, + PERF_PAPC_SU_INPUT_CLIP_PRIM = 48, + PERF_PAPC_SU_INPUT_NULL_PRIM = 49, + PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 50, + PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 51, + PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 52, + PERF_PAPC_SU_POLYMODE_FACE_CULL = 53, + PERF_PAPC_SU_POLYMODE_BACK_CULL = 54, + PERF_PAPC_SU_POLYMODE_FRONT_CULL = 55, + PERF_PAPC_SU_POLYMODE_INVALID_FILL = 56, + PERF_PAPC_SU_OUTPUT_PRIM = 57, + PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 58, + PERF_PAPC_SU_OUTPUT_NULL_PRIM = 59, + PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 60, + PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 61, + PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 62, + PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 63, + PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 64, + PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 65, + PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 66, + PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 67, + PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 68, + PERF_PAPC_PASX_REQ_IDLE = 69, + PERF_PAPC_PASX_REQ_BUSY = 70, + PERF_PAPC_PASX_REQ_STALLED = 71, + PERF_PAPC_PASX_REC_IDLE = 72, + PERF_PAPC_PASX_REC_BUSY = 73, + PERF_PAPC_PASX_REC_STARVED_SX = 74, + PERF_PAPC_PASX_REC_STALLED = 75, + PERF_PAPC_PASX_REC_STALLED_POS_MEM = 76, + PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 77, + PERF_PAPC_CCGSM_IDLE = 78, + PERF_PAPC_CCGSM_BUSY = 79, + PERF_PAPC_CCGSM_STALLED = 80, + PERF_PAPC_CLPRIM_IDLE = 81, + PERF_PAPC_CLPRIM_BUSY = 82, + PERF_PAPC_CLPRIM_STALLED = 83, + PERF_PAPC_CLPRIM_STARVED_CCGSM = 84, + PERF_PAPC_CLIPSM_IDLE = 85, + PERF_PAPC_CLIPSM_BUSY = 86, + PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 87, + PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 88, + PERF_PAPC_CLIPSM_WAIT_CLIPGA = 89, + PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 90, + PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 91, + PERF_PAPC_CLIPGA_IDLE = 92, + PERF_PAPC_CLIPGA_BUSY = 93, + PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 94, + PERF_PAPC_CLIPGA_STALLED = 95, + PERF_PAPC_CLIP_IDLE = 96, + PERF_PAPC_CLIP_BUSY = 97, + PERF_PAPC_SU_IDLE = 98, + PERF_PAPC_SU_BUSY = 99, + PERF_PAPC_SU_STARVED_CLIP = 100, + PERF_PAPC_SU_STALLED_SC = 101, +} SU_PERFCNT_SELECT; +#endif /*ENUMS_SU_PERFCNT_SELECT_H*/ + +#ifndef ENUMS_SC_PERFCNT_SELECT_H +#define ENUMS_SC_PERFCNT_SELECT_H +typedef enum SC_PERFCNT_SELECT { + SC_SR_WINDOW_VALID = 0, + SC_CW_WINDOW_VALID = 1, + SC_QM_WINDOW_VALID = 2, + SC_FW_WINDOW_VALID = 3, + SC_EZ_WINDOW_VALID = 4, + SC_IT_WINDOW_VALID = 5, + SC_STARVED_BY_PA = 6, + SC_STALLED_BY_RB_TILE = 7, + SC_STALLED_BY_RB_SAMP = 8, + SC_STARVED_BY_RB_EZ = 9, + SC_STALLED_BY_SAMPLE_FF = 10, + SC_STALLED_BY_SQ = 11, + SC_STALLED_BY_SP = 12, + SC_TOTAL_NO_PRIMS = 13, + SC_NON_EMPTY_PRIMS = 14, + SC_NO_TILES_PASSING_QM = 15, + SC_NO_PIXELS_PRE_EZ = 16, + SC_NO_PIXELS_POST_EZ = 17, +} SC_PERFCNT_SELECT; +#endif /*ENUMS_SC_PERFCNT_SELECT_H*/ + +/******************************************************* + * VGT Enums + *******************************************************/ +#ifndef ENUMS_VGT_DI_PRIM_TYPE_H +#define ENUMS_VGT_DI_PRIM_TYPE_H +typedef enum VGT_DI_PRIM_TYPE { + DI_PT_NONE = 0, + DI_PT_POINTLIST = 1, + DI_PT_LINELIST = 2, + DI_PT_LINESTRIP = 3, + DI_PT_TRILIST = 4, + DI_PT_TRIFAN = 5, + DI_PT_TRISTRIP = 6, + DI_PT_UNUSED_1 = 7, + DI_PT_RECTLIST = 8, + DI_PT_UNUSED_2 = 9, + DI_PT_UNUSED_3 = 10, + DI_PT_UNUSED_4 = 11, + DI_PT_UNUSED_5 = 12, + DI_PT_QUADLIST = 13, + DI_PT_QUADSTRIP = 14, + DI_PT_POLYGON = 15, + DI_PT_2D_COPY_RECT_LIST_V0 = 16, + DI_PT_2D_COPY_RECT_LIST_V1 = 17, + DI_PT_2D_COPY_RECT_LIST_V2 = 18, + DI_PT_2D_COPY_RECT_LIST_V3 = 19, + DI_PT_2D_FILL_RECT_LIST = 20, + DI_PT_2D_LINE_STRIP = 21, + DI_PT_2D_TRI_STRIP = 22, +} VGT_DI_PRIM_TYPE; +#endif /*ENUMS_VGT_DI_PRIM_TYPE_H*/ + +#ifndef ENUMS_VGT_DI_SOURCE_SELECT_H +#define ENUMS_VGT_DI_SOURCE_SELECT_H +typedef enum VGT_DI_SOURCE_SELECT { + DI_SRC_SEL_DMA = 0, + DI_SRC_SEL_IMMEDIATE = 1, + DI_SRC_SEL_AUTO_INDEX = 2, + DI_SRC_SEL_RESERVED = 3 +} VGT_DI_SOURCE_SELECT; +#endif /*ENUMS_VGT_DI_SOURCE_SELECT_H*/ + +#ifndef ENUMS_VGT_DI_INDEX_SIZE_H +#define ENUMS_VGT_DI_INDEX_SIZE_H +typedef enum VGT_DI_INDEX_SIZE { + DI_INDEX_SIZE_16_BIT = 0, + DI_INDEX_SIZE_32_BIT = 1 +} VGT_DI_INDEX_SIZE; +#endif /*ENUMS_VGT_DI_INDEX_SIZE_H*/ + +#ifndef ENUMS_VGT_DI_SMALL_INDEX_H +#define ENUMS_VGT_DI_SMALL_INDEX_H +typedef enum VGT_DI_SMALL_INDEX { + DI_USE_INDEX_SIZE = 0, + DI_INDEX_SIZE_8_BIT = 1 +} VGT_DI_SMALL_INDEX; +#endif /*ENUMS_VGT_DI_SMALL_INDEX_H*/ + +#ifndef ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H +#define ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H +typedef enum VGT_DI_PRE_FETCH_CULL_ENABLE { + DISABLE_PRE_FETCH_CULL_ENABLE = 0, + PRE_FETCH_CULL_ENABLE = 1 +} VGT_DI_PRE_FETCH_CULL_ENABLE; +#endif /*ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H*/ + +#ifndef ENUMS_VGT_DI_GRP_CULL_ENABLE_H +#define ENUMS_VGT_DI_GRP_CULL_ENABLE_H +typedef enum VGT_DI_GRP_CULL_ENABLE { + DISABLE_GRP_CULL_ENABLE = 0, + GRP_CULL_ENABLE = 1 +} VGT_DI_GRP_CULL_ENABLE; +#endif /*ENUMS_VGT_DI_GRP_CULL_ENABLE_H*/ + +#ifndef ENUMS_VGT_EVENT_TYPE_H +#define ENUMS_VGT_EVENT_TYPE_H +typedef enum VGT_EVENT_TYPE { + VS_DEALLOC = 0, + PS_DEALLOC = 1, + VS_DONE_TS = 2, + PS_DONE_TS = 3, + CACHE_FLUSH_TS = 4, + CONTEXT_DONE = 5, + CACHE_FLUSH = 6, + VIZQUERY_START = 7, + VIZQUERY_END = 8, + SC_WAIT_WC = 9, + RST_PIX_CNT = 13, + RST_VTX_CNT = 14, + TILE_FLUSH = 15, + CACHE_FLUSH_AND_INV_TS_EVENT = 20, + ZPASS_DONE = 21, + CACHE_FLUSH_AND_INV_EVENT = 22, + PERFCOUNTER_START = 23, + PERFCOUNTER_STOP = 24, + VS_FETCH_DONE = 27, +} VGT_EVENT_TYPE; +#endif /*ENUMS_VGT_EVENT_TYPE_H*/ + +#ifndef ENUMS_VGT_DMA_SWAP_MODE_H +#define ENUMS_VGT_DMA_SWAP_MODE_H +typedef enum VGT_DMA_SWAP_MODE { + VGT_DMA_SWAP_NONE = 0, + VGT_DMA_SWAP_16_BIT = 1, + VGT_DMA_SWAP_32_BIT = 2, + VGT_DMA_SWAP_WORD = 3 +} VGT_DMA_SWAP_MODE; +#endif /*ENUMS_VGT_DMA_SWAP_MODE_H*/ + +#ifndef ENUMS_VGT_PERFCOUNT_SELECT_H +#define ENUMS_VGT_PERFCOUNT_SELECT_H +typedef enum VGT_PERFCOUNT_SELECT { + VGT_SQ_EVENT_WINDOW_ACTIVE = 0, + VGT_SQ_SEND = 1, + VGT_SQ_STALLED = 2, + VGT_SQ_STARVED_BUSY = 3, + VGT_SQ_STARVED_IDLE = 4, + VGT_SQ_STATIC = 5, + VGT_PA_EVENT_WINDOW_ACTIVE = 6, + VGT_PA_CLIP_V_SEND = 7, + VGT_PA_CLIP_V_STALLED = 8, + VGT_PA_CLIP_V_STARVED_BUSY = 9, + VGT_PA_CLIP_V_STARVED_IDLE = 10, + VGT_PA_CLIP_V_STATIC = 11, + VGT_PA_CLIP_P_SEND = 12, + VGT_PA_CLIP_P_STALLED = 13, + VGT_PA_CLIP_P_STARVED_BUSY = 14, + VGT_PA_CLIP_P_STARVED_IDLE = 15, + VGT_PA_CLIP_P_STATIC = 16, + VGT_PA_CLIP_S_SEND = 17, + VGT_PA_CLIP_S_STALLED = 18, + VGT_PA_CLIP_S_STARVED_BUSY = 19, + VGT_PA_CLIP_S_STARVED_IDLE = 20, + VGT_PA_CLIP_S_STATIC = 21, + RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 22, + RBIU_IMMED_DATA_FIFO_STARVED = 23, + RBIU_IMMED_DATA_FIFO_STALLED = 24, + RBIU_DMA_REQUEST_FIFO_STARVED = 25, + RBIU_DMA_REQUEST_FIFO_STALLED = 26, + RBIU_DRAW_INITIATOR_FIFO_STARVED = 27, + RBIU_DRAW_INITIATOR_FIFO_STALLED = 28, + BIN_PRIM_NEAR_CULL = 29, + BIN_PRIM_ZERO_CULL = 30, + BIN_PRIM_FAR_CULL = 31, + BIN_PRIM_BIN_CULL = 32, + SPARE33 = 33, + SPARE34 = 34, + SPARE35 = 35, + SPARE36 = 36, + SPARE37 = 37, + SPARE38 = 38, + SPARE39 = 39, + TE_SU_IN_VALID = 40, + TE_SU_IN_READ = 41, + TE_SU_IN_PRIM = 42, + TE_SU_IN_EOP = 43, + TE_SU_IN_NULL_PRIM = 44, + TE_WK_IN_VALID = 45, + TE_WK_IN_READ = 46, + TE_OUT_PRIM_VALID = 47, + TE_OUT_PRIM_READ = 48, +} VGT_PERFCOUNT_SELECT; +#endif /*ENUMS_VGT_PERFCOUNT_SELECT_H*/ + +/******************************************************* + * TP Enums + *******************************************************/ +#ifndef ENUMS_TCR_PERFCOUNT_SELECT_H +#define ENUMS_TCR_PERFCOUNT_SELECT_H +typedef enum TCR_PERFCOUNT_SELECT { + DGMMPD_IPMUX0_STALL = 0, + reserved_46 = 1, + reserved_47 = 2, + reserved_48 = 3, + DGMMPD_IPMUX_ALL_STALL = 4, + OPMUX0_L2_WRITES = 5, + reserved_49 = 6, + reserved_50 = 7, + reserved_51 = 8, +} TCR_PERFCOUNT_SELECT; +#endif /*ENUMS_TCR_PERFCOUNT_SELECT_H*/ + +#ifndef ENUMS_TP_PERFCOUNT_SELECT_H +#define ENUMS_TP_PERFCOUNT_SELECT_H +typedef enum TP_PERFCOUNT_SELECT { + POINT_QUADS = 0, + BILIN_QUADS = 1, + ANISO_QUADS = 2, + MIP_QUADS = 3, + VOL_QUADS = 4, + MIP_VOL_QUADS = 5, + MIP_ANISO_QUADS = 6, + VOL_ANISO_QUADS = 7, + ANISO_2_1_QUADS = 8, + ANISO_4_1_QUADS = 9, + ANISO_6_1_QUADS = 10, + ANISO_8_1_QUADS = 11, + ANISO_10_1_QUADS = 12, + ANISO_12_1_QUADS = 13, + ANISO_14_1_QUADS = 14, + ANISO_16_1_QUADS = 15, + MIP_VOL_ANISO_QUADS = 16, + ALIGN_2_QUADS = 17, + ALIGN_4_QUADS = 18, + PIX_0_QUAD = 19, + PIX_1_QUAD = 20, + PIX_2_QUAD = 21, + PIX_3_QUAD = 22, + PIX_4_QUAD = 23, + TP_MIPMAP_LOD0 = 24, + TP_MIPMAP_LOD1 = 25, + TP_MIPMAP_LOD2 = 26, + TP_MIPMAP_LOD3 = 27, + TP_MIPMAP_LOD4 = 28, + TP_MIPMAP_LOD5 = 29, + TP_MIPMAP_LOD6 = 30, + TP_MIPMAP_LOD7 = 31, + TP_MIPMAP_LOD8 = 32, + TP_MIPMAP_LOD9 = 33, + TP_MIPMAP_LOD10 = 34, + TP_MIPMAP_LOD11 = 35, + TP_MIPMAP_LOD12 = 36, + TP_MIPMAP_LOD13 = 37, + TP_MIPMAP_LOD14 = 38, +} TP_PERFCOUNT_SELECT; +#endif /*ENUMS_TP_PERFCOUNT_SELECT_H*/ + +#ifndef ENUMS_TCM_PERFCOUNT_SELECT_H +#define ENUMS_TCM_PERFCOUNT_SELECT_H +typedef enum TCM_PERFCOUNT_SELECT { + QUAD0_RD_LAT_FIFO_EMPTY = 0, + reserved_01 = 1, + reserved_02 = 2, + QUAD0_RD_LAT_FIFO_4TH_FULL = 3, + QUAD0_RD_LAT_FIFO_HALF_FULL = 4, + QUAD0_RD_LAT_FIFO_FULL = 5, + QUAD0_RD_LAT_FIFO_LT_4TH_FULL = 6, + reserved_07 = 7, + reserved_08 = 8, + reserved_09 = 9, + reserved_10 = 10, + reserved_11 = 11, + reserved_12 = 12, + reserved_13 = 13, + reserved_14 = 14, + reserved_15 = 15, + reserved_16 = 16, + reserved_17 = 17, + reserved_18 = 18, + reserved_19 = 19, + reserved_20 = 20, + reserved_21 = 21, + reserved_22 = 22, + reserved_23 = 23, + reserved_24 = 24, + reserved_25 = 25, + reserved_26 = 26, + reserved_27 = 27, + READ_STARVED_QUAD0 = 28, + reserved_29 = 29, + reserved_30 = 30, + reserved_31 = 31, + READ_STARVED = 32, + READ_STALLED_QUAD0 = 33, + reserved_34 = 34, + reserved_35 = 35, + reserved_36 = 36, + READ_STALLED = 37, + VALID_READ_QUAD0 = 38, + reserved_39 = 39, + reserved_40 = 40, + reserved_41 = 41, + TC_TP_STARVED_QUAD0 = 42, + reserved_43 = 43, + reserved_44 = 44, + reserved_45 = 45, + TC_TP_STARVED = 46, +} TCM_PERFCOUNT_SELECT; +#endif /*ENUMS_TCM_PERFCOUNT_SELECT_H*/ + +#ifndef ENUMS_TCF_PERFCOUNT_SELECT_H +#define ENUMS_TCF_PERFCOUNT_SELECT_H +typedef enum TCF_PERFCOUNT_SELECT { + VALID_CYCLES = 0, + SINGLE_PHASES = 1, + ANISO_PHASES = 2, + MIP_PHASES = 3, + VOL_PHASES = 4, + MIP_VOL_PHASES = 5, + MIP_ANISO_PHASES = 6, + VOL_ANISO_PHASES = 7, + ANISO_2_1_PHASES = 8, + ANISO_4_1_PHASES = 9, + ANISO_6_1_PHASES = 10, + ANISO_8_1_PHASES = 11, + ANISO_10_1_PHASES = 12, + ANISO_12_1_PHASES = 13, + ANISO_14_1_PHASES = 14, + ANISO_16_1_PHASES = 15, + MIP_VOL_ANISO_PHASES = 16, + ALIGN_2_PHASES = 17, + ALIGN_4_PHASES = 18, + TPC_BUSY = 19, + TPC_STALLED = 20, + TPC_STARVED = 21, + TPC_WORKING = 22, + TPC_WALKER_BUSY = 23, + TPC_WALKER_STALLED = 24, + TPC_WALKER_WORKING = 25, + TPC_ALIGNER_BUSY = 26, + TPC_ALIGNER_STALLED = 27, + TPC_ALIGNER_STALLED_BY_BLEND = 28, + TPC_ALIGNER_STALLED_BY_CACHE = 29, + TPC_ALIGNER_WORKING = 30, + TPC_BLEND_BUSY = 31, + TPC_BLEND_SYNC = 32, + TPC_BLEND_STARVED = 33, + TPC_BLEND_WORKING = 34, + OPCODE_0x00 = 35, + OPCODE_0x01 = 36, + OPCODE_0x04 = 37, + OPCODE_0x10 = 38, + OPCODE_0x11 = 39, + OPCODE_0x12 = 40, + OPCODE_0x13 = 41, + OPCODE_0x18 = 42, + OPCODE_0x19 = 43, + OPCODE_0x1A = 44, + OPCODE_OTHER = 45, + IN_FIFO_0_EMPTY = 56, + IN_FIFO_0_LT_HALF_FULL = 57, + IN_FIFO_0_HALF_FULL = 58, + IN_FIFO_0_FULL = 59, + IN_FIFO_TPC_EMPTY = 72, + IN_FIFO_TPC_LT_HALF_FULL = 73, + IN_FIFO_TPC_HALF_FULL = 74, + IN_FIFO_TPC_FULL = 75, + TPC_TC_XFC = 76, + TPC_TC_STATE = 77, + TC_STALL = 78, + QUAD0_TAPS = 79, + QUADS = 83, + TCA_SYNC_STALL = 84, + TAG_STALL = 85, + TCB_SYNC_STALL = 88, + TCA_VALID = 89, + PROBES_VALID = 90, + MISS_STALL = 91, + FETCH_FIFO_STALL = 92, + TCO_STALL = 93, + ANY_STALL = 94, + TAG_MISSES = 95, + TAG_HITS = 96, + SUB_TAG_MISSES = 97, + SET0_INVALIDATES = 98, + SET1_INVALIDATES = 99, + SET2_INVALIDATES = 100, + SET3_INVALIDATES = 101, + SET0_TAG_MISSES = 102, + SET1_TAG_MISSES = 103, + SET2_TAG_MISSES = 104, + SET3_TAG_MISSES = 105, + SET0_TAG_HITS = 106, + SET1_TAG_HITS = 107, + SET2_TAG_HITS = 108, + SET3_TAG_HITS = 109, + SET0_SUB_TAG_MISSES = 110, + SET1_SUB_TAG_MISSES = 111, + SET2_SUB_TAG_MISSES = 112, + SET3_SUB_TAG_MISSES = 113, + SET0_EVICT1 = 114, + SET0_EVICT2 = 115, + SET0_EVICT3 = 116, + SET0_EVICT4 = 117, + SET0_EVICT5 = 118, + SET0_EVICT6 = 119, + SET0_EVICT7 = 120, + SET0_EVICT8 = 121, + SET1_EVICT1 = 130, + SET1_EVICT2 = 131, + SET1_EVICT3 = 132, + SET1_EVICT4 = 133, + SET1_EVICT5 = 134, + SET1_EVICT6 = 135, + SET1_EVICT7 = 136, + SET1_EVICT8 = 137, + SET2_EVICT1 = 146, + SET2_EVICT2 = 147, + SET2_EVICT3 = 148, + SET2_EVICT4 = 149, + SET2_EVICT5 = 150, + SET2_EVICT6 = 151, + SET2_EVICT7 = 152, + SET2_EVICT8 = 153, + SET3_EVICT1 = 162, + SET3_EVICT2 = 163, + SET3_EVICT3 = 164, + SET3_EVICT4 = 165, + SET3_EVICT5 = 166, + SET3_EVICT6 = 167, + SET3_EVICT7 = 168, + SET3_EVICT8 = 169, + FF_EMPTY = 178, + FF_LT_HALF_FULL = 179, + FF_HALF_FULL = 180, + FF_FULL = 181, + FF_XFC = 182, + FF_STALLED = 183, + FG_MASKS = 184, + FG_LEFT_MASKS = 185, + FG_LEFT_MASK_STALLED = 186, + FG_LEFT_NOT_DONE_STALL = 187, + FG_LEFT_FG_STALL = 188, + FG_LEFT_SECTORS = 189, + FG0_REQUESTS = 195, + FG0_STALLED = 196, + MEM_REQ512 = 199, + MEM_REQ_SENT = 200, + MEM_LOCAL_READ_REQ = 202, + TC0_MH_STALLED = 203, +} TCF_PERFCOUNT_SELECT; +#endif /*ENUMS_TCF_PERFCOUNT_SELECT_H*/ + +/******************************************************* + * TC Enums + *******************************************************/ +/******************************************************* + * SQ Enums + *******************************************************/ +#ifndef ENUMS_SQ_PERFCNT_SELECT_H +#define ENUMS_SQ_PERFCNT_SELECT_H +typedef enum SQ_PERFCNT_SELECT { + SQ_PIXEL_VECTORS_SUB = 0, + SQ_VERTEX_VECTORS_SUB = 1, + SQ_ALU0_ACTIVE_VTX_SIMD0 = 2, + SQ_ALU1_ACTIVE_VTX_SIMD0 = 3, + SQ_ALU0_ACTIVE_PIX_SIMD0 = 4, + SQ_ALU1_ACTIVE_PIX_SIMD0 = 5, + SQ_ALU0_ACTIVE_VTX_SIMD1 = 6, + SQ_ALU1_ACTIVE_VTX_SIMD1 = 7, + SQ_ALU0_ACTIVE_PIX_SIMD1 = 8, + SQ_ALU1_ACTIVE_PIX_SIMD1 = 9, + SQ_EXPORT_CYCLES = 10, + SQ_ALU_CST_WRITTEN = 11, + SQ_TEX_CST_WRITTEN = 12, + SQ_ALU_CST_STALL = 13, + SQ_ALU_TEX_STALL = 14, + SQ_INST_WRITTEN = 15, + SQ_BOOLEAN_WRITTEN = 16, + SQ_LOOPS_WRITTEN = 17, + SQ_PIXEL_SWAP_IN = 18, + SQ_PIXEL_SWAP_OUT = 19, + SQ_VERTEX_SWAP_IN = 20, + SQ_VERTEX_SWAP_OUT = 21, + SQ_ALU_VTX_INST_ISSUED = 22, + SQ_TEX_VTX_INST_ISSUED = 23, + SQ_VC_VTX_INST_ISSUED = 24, + SQ_CF_VTX_INST_ISSUED = 25, + SQ_ALU_PIX_INST_ISSUED = 26, + SQ_TEX_PIX_INST_ISSUED = 27, + SQ_VC_PIX_INST_ISSUED = 28, + SQ_CF_PIX_INST_ISSUED = 29, + SQ_ALU0_FIFO_EMPTY_SIMD0 = 30, + SQ_ALU1_FIFO_EMPTY_SIMD0 = 31, + SQ_ALU0_FIFO_EMPTY_SIMD1 = 32, + SQ_ALU1_FIFO_EMPTY_SIMD1 = 33, + SQ_ALU_NOPS = 34, + SQ_PRED_SKIP = 35, + SQ_SYNC_ALU_STALL_SIMD0_VTX = 36, + SQ_SYNC_ALU_STALL_SIMD1_VTX = 37, + SQ_SYNC_TEX_STALL_VTX = 38, + SQ_SYNC_VC_STALL_VTX = 39, + SQ_CONSTANTS_USED_SIMD0 = 40, + SQ_CONSTANTS_SENT_SP_SIMD0 = 41, + SQ_GPR_STALL_VTX = 42, + SQ_GPR_STALL_PIX = 43, + SQ_VTX_RS_STALL = 44, + SQ_PIX_RS_STALL = 45, + SQ_SX_PC_FULL = 46, + SQ_SX_EXP_BUFF_FULL = 47, + SQ_SX_POS_BUFF_FULL = 48, + SQ_INTERP_QUADS = 49, + SQ_INTERP_ACTIVE = 50, + SQ_IN_PIXEL_STALL = 51, + SQ_IN_VTX_STALL = 52, + SQ_VTX_CNT = 53, + SQ_VTX_VECTOR2 = 54, + SQ_VTX_VECTOR3 = 55, + SQ_VTX_VECTOR4 = 56, + SQ_PIXEL_VECTOR1 = 57, + SQ_PIXEL_VECTOR23 = 58, + SQ_PIXEL_VECTOR4 = 59, + SQ_CONSTANTS_USED_SIMD1 = 60, + SQ_CONSTANTS_SENT_SP_SIMD1 = 61, + SQ_SX_MEM_EXP_FULL = 62, + SQ_ALU0_ACTIVE_VTX_SIMD2 = 63, + SQ_ALU1_ACTIVE_VTX_SIMD2 = 64, + SQ_ALU0_ACTIVE_PIX_SIMD2 = 65, + SQ_ALU1_ACTIVE_PIX_SIMD2 = 66, + SQ_ALU0_ACTIVE_VTX_SIMD3 = 67, + SQ_ALU1_ACTIVE_VTX_SIMD3 = 68, + SQ_ALU0_ACTIVE_PIX_SIMD3 = 69, + SQ_ALU1_ACTIVE_PIX_SIMD3 = 70, + SQ_ALU0_FIFO_EMPTY_SIMD2 = 71, + SQ_ALU1_FIFO_EMPTY_SIMD2 = 72, + SQ_ALU0_FIFO_EMPTY_SIMD3 = 73, + SQ_ALU1_FIFO_EMPTY_SIMD3 = 74, + SQ_SYNC_ALU_STALL_SIMD2_VTX = 75, + SQ_SYNC_ALU_STALL_SIMD3_VTX = 76, + SQ_SYNC_ALU_STALL_SIMD0_PIX = 77, + SQ_SYNC_ALU_STALL_SIMD1_PIX = 78, + SQ_SYNC_ALU_STALL_SIMD2_PIX = 79, + SQ_SYNC_ALU_STALL_SIMD3_PIX = 80, + SQ_SYNC_TEX_STALL_PIX = 81, + SQ_SYNC_VC_STALL_PIX = 82, + SQ_CONSTANTS_USED_SIMD2 = 83, + SQ_CONSTANTS_SENT_SP_SIMD2 = 84, + SQ_CONSTANTS_USED_SIMD3 = 85, + SQ_CONSTANTS_SENT_SP_SIMD3 = 86, + SQ_ALU0_FIFO_FULL_SIMD0 = 87, + SQ_ALU1_FIFO_FULL_SIMD0 = 88, + SQ_ALU0_FIFO_FULL_SIMD1 = 89, + SQ_ALU1_FIFO_FULL_SIMD1 = 90, + SQ_ALU0_FIFO_FULL_SIMD2 = 91, + SQ_ALU1_FIFO_FULL_SIMD2 = 92, + SQ_ALU0_FIFO_FULL_SIMD3 = 93, + SQ_ALU1_FIFO_FULL_SIMD3 = 94, + VC_PERF_STATIC = 95, + VC_PERF_STALLED = 96, + VC_PERF_STARVED = 97, + VC_PERF_SEND = 98, + VC_PERF_ACTUAL_STARVED = 99, + PIXEL_THREAD_0_ACTIVE = 100, + VERTEX_THREAD_0_ACTIVE = 101, + PIXEL_THREAD_0_NUMBER = 102, + VERTEX_THREAD_0_NUMBER = 103, + VERTEX_EVENT_NUMBER = 104, + PIXEL_EVENT_NUMBER = 105, + PTRBUFF_EF_PUSH = 106, + PTRBUFF_EF_POP_EVENT = 107, + PTRBUFF_EF_POP_NEW_VTX = 108, + PTRBUFF_EF_POP_DEALLOC = 109, + PTRBUFF_EF_POP_PVECTOR = 110, + PTRBUFF_EF_POP_PVECTOR_X = 111, + PTRBUFF_EF_POP_PVECTOR_VNZ = 112, + PTRBUFF_PB_DEALLOC = 113, + PTRBUFF_PI_STATE_PPB_POP = 114, + PTRBUFF_PI_RTR = 115, + PTRBUFF_PI_READ_EN = 116, + PTRBUFF_PI_BUFF_SWAP = 117, + PTRBUFF_SQ_FREE_BUFF = 118, + PTRBUFF_SQ_DEC = 119, + PTRBUFF_SC_VALID_CNTL_EVENT = 120, + PTRBUFF_SC_VALID_IJ_XFER = 121, + PTRBUFF_SC_NEW_VECTOR_1_Q = 122, + PTRBUFF_QUAL_NEW_VECTOR = 123, + PTRBUFF_QUAL_EVENT = 124, + PTRBUFF_END_BUFFER = 125, + PTRBUFF_FILL_QUAD = 126, + VERTS_WRITTEN_SPI = 127, + TP_FETCH_INSTR_EXEC = 128, + TP_FETCH_INSTR_REQ = 129, + TP_DATA_RETURN = 130, + SPI_WRITE_CYCLES_SP = 131, + SPI_WRITES_SP = 132, + SP_ALU_INSTR_EXEC = 133, + SP_CONST_ADDR_TO_SQ = 134, + SP_PRED_KILLS_TO_SQ = 135, + SP_EXPORT_CYCLES_TO_SX = 136, + SP_EXPORTS_TO_SX = 137, + SQ_CYCLES_ELAPSED = 138, + SQ_TCFS_OPT_ALLOC_EXEC = 139, + SQ_TCFS_NO_OPT_ALLOC = 140, + SQ_ALU0_NO_OPT_ALLOC = 141, + SQ_ALU1_NO_OPT_ALLOC = 142, + SQ_TCFS_ARB_XFC_CNT = 143, + SQ_ALU0_ARB_XFC_CNT = 144, + SQ_ALU1_ARB_XFC_CNT = 145, + SQ_TCFS_CFS_UPDATE_CNT = 146, + SQ_ALU0_CFS_UPDATE_CNT = 147, + SQ_ALU1_CFS_UPDATE_CNT = 148, + SQ_VTX_PUSH_THREAD_CNT = 149, + SQ_VTX_POP_THREAD_CNT = 150, + SQ_PIX_PUSH_THREAD_CNT = 151, + SQ_PIX_POP_THREAD_CNT = 152, + SQ_PIX_TOTAL = 153, + SQ_PIX_KILLED = 154, +} SQ_PERFCNT_SELECT; +#endif /*ENUMS_SQ_PERFCNT_SELECT_H*/ + +#ifndef ENUMS_SX_PERFCNT_SELECT_H +#define ENUMS_SX_PERFCNT_SELECT_H +typedef enum SX_PERFCNT_SELECT { + SX_EXPORT_VECTORS = 0, + SX_DUMMY_QUADS = 1, + SX_ALPHA_FAIL = 2, + SX_RB_QUAD_BUSY = 3, + SX_RB_COLOR_BUSY = 4, + SX_RB_QUAD_STALL = 5, + SX_RB_COLOR_STALL = 6, +} SX_PERFCNT_SELECT; +#endif /*ENUMS_SX_PERFCNT_SELECT_H*/ + +#ifndef ENUMS_Abs_modifier_H +#define ENUMS_Abs_modifier_H +typedef enum Abs_modifier { + NO_ABS_MOD = 0, + ABS_MOD = 1 +} Abs_modifier; +#endif /*ENUMS_Abs_modifier_H*/ + +#ifndef ENUMS_Exporting_H +#define ENUMS_Exporting_H +typedef enum Exporting { + NOT_EXPORTING = 0, + EXPORTING = 1 +} Exporting; +#endif /*ENUMS_Exporting_H*/ + +#ifndef ENUMS_ScalarOpcode_H +#define ENUMS_ScalarOpcode_H +typedef enum ScalarOpcode { + ADDs = 0, + ADD_PREVs = 1, + MULs = 2, + MUL_PREVs = 3, + MUL_PREV2s = 4, + MAXs = 5, + MINs = 6, + SETEs = 7, + SETGTs = 8, + SETGTEs = 9, + SETNEs = 10, + FRACs = 11, + TRUNCs = 12, + FLOORs = 13, + EXP_IEEE = 14, + LOG_CLAMP = 15, + LOG_IEEE = 16, + RECIP_CLAMP = 17, + RECIP_FF = 18, + RECIP_IEEE = 19, + RECIPSQ_CLAMP = 20, + RECIPSQ_FF = 21, + RECIPSQ_IEEE = 22, + MOVAs = 23, + MOVA_FLOORs = 24, + SUBs = 25, + SUB_PREVs = 26, + PRED_SETEs = 27, + PRED_SETNEs = 28, + PRED_SETGTs = 29, + PRED_SETGTEs = 30, + PRED_SET_INVs = 31, + PRED_SET_POPs = 32, + PRED_SET_CLRs = 33, + PRED_SET_RESTOREs = 34, + KILLEs = 35, + KILLGTs = 36, + KILLGTEs = 37, + KILLNEs = 38, + KILLONEs = 39, + SQRT_IEEE = 40, + MUL_CONST_0 = 42, + MUL_CONST_1 = 43, + ADD_CONST_0 = 44, + ADD_CONST_1 = 45, + SUB_CONST_0 = 46, + SUB_CONST_1 = 47, + SIN = 48, + COS = 49, + RETAIN_PREV = 50, +} ScalarOpcode; +#endif /*ENUMS_ScalarOpcode_H*/ + +#ifndef ENUMS_SwizzleType_H +#define ENUMS_SwizzleType_H +typedef enum SwizzleType { + NO_SWIZZLE = 0, + SHIFT_RIGHT_1 = 1, + SHIFT_RIGHT_2 = 2, + SHIFT_RIGHT_3 = 3 +} SwizzleType; +#endif /*ENUMS_SwizzleType_H*/ + +#ifndef ENUMS_InputModifier_H +#define ENUMS_InputModifier_H +typedef enum InputModifier { + NIL = 0, + NEGATE = 1 +} InputModifier; +#endif /*ENUMS_InputModifier_H*/ + +#ifndef ENUMS_PredicateSelect_H +#define ENUMS_PredicateSelect_H +typedef enum PredicateSelect { + NO_PREDICATION = 0, + PREDICATE_QUAD = 1, + PREDICATED_2 = 2, + PREDICATED_3 = 3 +} PredicateSelect; +#endif /*ENUMS_PredicateSelect_H*/ + +#ifndef ENUMS_OperandSelect1_H +#define ENUMS_OperandSelect1_H +typedef enum OperandSelect1 { + ABSOLUTE_REG = 0, + RELATIVE_REG = 1 +} OperandSelect1; +#endif /*ENUMS_OperandSelect1_H*/ + +#ifndef ENUMS_VectorOpcode_H +#define ENUMS_VectorOpcode_H +typedef enum VectorOpcode { + ADDv = 0, + MULv = 1, + MAXv = 2, + MINv = 3, + SETEv = 4, + SETGTv = 5, + SETGTEv = 6, + SETNEv = 7, + FRACv = 8, + TRUNCv = 9, + FLOORv = 10, + MULADDv = 11, + CNDEv = 12, + CNDGTEv = 13, + CNDGTv = 14, + DOT4v = 15, + DOT3v = 16, + DOT2ADDv = 17, + CUBEv = 18, + MAX4v = 19, + PRED_SETE_PUSHv = 20, + PRED_SETNE_PUSHv = 21, + PRED_SETGT_PUSHv = 22, + PRED_SETGTE_PUSHv = 23, + KILLEv = 24, + KILLGTv = 25, + KILLGTEv = 26, + KILLNEv = 27, + DSTv = 28, + MOVAv = 29, +} VectorOpcode; +#endif /*ENUMS_VectorOpcode_H*/ + +#ifndef ENUMS_OperandSelect0_H +#define ENUMS_OperandSelect0_H +typedef enum OperandSelect0 { + CONSTANT = 0, + NON_CONSTANT = 1 +} OperandSelect0; +#endif /*ENUMS_OperandSelect0_H*/ + +#ifndef ENUMS_Ressource_type_H +#define ENUMS_Ressource_type_H +typedef enum Ressource_type { + ALU = 0, + TEXTURE = 1 +} Ressource_type; +#endif /*ENUMS_Ressource_type_H*/ + +#ifndef ENUMS_Instruction_serial_H +#define ENUMS_Instruction_serial_H +typedef enum Instruction_serial { + NOT_SERIAL = 0, + SERIAL = 1 +} Instruction_serial; +#endif /*ENUMS_Instruction_serial_H*/ + +#ifndef ENUMS_VC_type_H +#define ENUMS_VC_type_H +typedef enum VC_type { + ALU_TP_REQUEST = 0, + VC_REQUEST = 1 +} VC_type; +#endif /*ENUMS_VC_type_H*/ + +#ifndef ENUMS_Addressing_H +#define ENUMS_Addressing_H +typedef enum Addressing { + RELATIVE_ADDR = 0, + ABSOLUTE_ADDR = 1 +} Addressing; +#endif /*ENUMS_Addressing_H*/ + +#ifndef ENUMS_CFOpcode_H +#define ENUMS_CFOpcode_H +typedef enum CFOpcode { + NOP = 0, + EXECUTE = 1, + EXECUTE_END = 2, + COND_EXECUTE = 3, + COND_EXECUTE_END = 4, + COND_PRED_EXECUTE = 5, + COND_PRED_EXECUTE_END = 6, + LOOP_START = 7, + LOOP_END = 8, + COND_CALL = 9, + RETURN = 10, + COND_JMP = 11, + ALLOCATE = 12, + COND_EXECUTE_PRED_CLEAN = 13, + COND_EXECUTE_PRED_CLEAN_END = 14, + MARK_VS_FETCH_DONE = 15 +} CFOpcode; +#endif /*ENUMS_CFOpcode_H*/ + +#ifndef ENUMS_Allocation_type_H +#define ENUMS_Allocation_type_H +typedef enum Allocation_type { + SQ_NO_ALLOC = 0, + SQ_POSITION = 1, + SQ_PARAMETER_PIXEL = 2, + SQ_MEMORY = 3 +} Allocation_type; +#endif /*ENUMS_Allocation_type_H*/ + +#ifndef ENUMS_TexInstOpcode_H +#define ENUMS_TexInstOpcode_H +typedef enum TexInstOpcode { + TEX_INST_FETCH = 1, + TEX_INST_RESERVED_1 = 2, + TEX_INST_RESERVED_2 = 3, + TEX_INST_RESERVED_3 = 4, + TEX_INST_GET_BORDER_COLOR_FRAC = 16, + TEX_INST_GET_COMP_TEX_LOD = 17, + TEX_INST_GET_GRADIENTS = 18, + TEX_INST_GET_WEIGHTS = 19, + TEX_INST_SET_TEX_LOD = 24, + TEX_INST_SET_GRADIENTS_H = 25, + TEX_INST_SET_GRADIENTS_V = 26, + TEX_INST_RESERVED_4 = 27, +} TexInstOpcode; +#endif /*ENUMS_TexInstOpcode_H*/ + +#ifndef ENUMS_Addressmode_H +#define ENUMS_Addressmode_H +typedef enum Addressmode { + LOGICAL = 0, + LOOP_RELATIVE = 1 +} Addressmode; +#endif /*ENUMS_Addressmode_H*/ + +#ifndef ENUMS_TexCoordDenorm_H +#define ENUMS_TexCoordDenorm_H +typedef enum TexCoordDenorm { + TEX_COORD_NORMALIZED = 0, + TEX_COORD_UNNORMALIZED = 1 +} TexCoordDenorm; +#endif /*ENUMS_TexCoordDenorm_H*/ + +#ifndef ENUMS_SrcSel_H +#define ENUMS_SrcSel_H +typedef enum SrcSel { + SRC_SEL_X = 0, + SRC_SEL_Y = 1, + SRC_SEL_Z = 2, + SRC_SEL_W = 3 +} SrcSel; +#endif /*ENUMS_SrcSel_H*/ + +#ifndef ENUMS_DstSel_H +#define ENUMS_DstSel_H +typedef enum DstSel { + DST_SEL_X = 0, + DST_SEL_Y = 1, + DST_SEL_Z = 2, + DST_SEL_W = 3, + DST_SEL_0 = 4, + DST_SEL_1 = 5, + DST_SEL_RSVD = 6, + DST_SEL_MASK = 7 +} DstSel; +#endif /*ENUMS_DstSel_H*/ + +#ifndef ENUMS_MagFilter_H +#define ENUMS_MagFilter_H +typedef enum MagFilter { + MAG_FILTER_POINT = 0, + MAG_FILTER_LINEAR = 1, + MAG_FILTER_RESERVED_0 = 2, + MAG_FILTER_USE_FETCH_CONST = 3 +} MagFilter; +#endif /*ENUMS_MagFilter_H*/ + +#ifndef ENUMS_MinFilter_H +#define ENUMS_MinFilter_H +typedef enum MinFilter { + MIN_FILTER_POINT = 0, + MIN_FILTER_LINEAR = 1, + MIN_FILTER_RESERVED_0 = 2, + MIN_FILTER_USE_FETCH_CONST = 3 +} MinFilter; +#endif /*ENUMS_MinFilter_H*/ + +#ifndef ENUMS_MipFilter_H +#define ENUMS_MipFilter_H +typedef enum MipFilter { + MIP_FILTER_POINT = 0, + MIP_FILTER_LINEAR = 1, + MIP_FILTER_BASEMAP = 2, + MIP_FILTER_USE_FETCH_CONST = 3 +} MipFilter; +#endif /*ENUMS_MipFilter_H*/ + +#ifndef ENUMS_AnisoFilter_H +#define ENUMS_AnisoFilter_H +typedef enum AnisoFilter { + ANISO_FILTER_DISABLED = 0, + ANISO_FILTER_MAX_1_1 = 1, + ANISO_FILTER_MAX_2_1 = 2, + ANISO_FILTER_MAX_4_1 = 3, + ANISO_FILTER_MAX_8_1 = 4, + ANISO_FILTER_MAX_16_1 = 5, + ANISO_FILTER_USE_FETCH_CONST = 7 +} AnisoFilter; +#endif /*ENUMS_AnisoFilter_H*/ + +#ifndef ENUMS_ArbitraryFilter_H +#define ENUMS_ArbitraryFilter_H +typedef enum ArbitraryFilter { + ARBITRARY_FILTER_2X4_SYM = 0, + ARBITRARY_FILTER_2X4_ASYM = 1, + ARBITRARY_FILTER_4X2_SYM = 2, + ARBITRARY_FILTER_4X2_ASYM = 3, + ARBITRARY_FILTER_4X4_SYM = 4, + ARBITRARY_FILTER_4X4_ASYM = 5, + ARBITRARY_FILTER_USE_FETCH_CONST = 7 +} ArbitraryFilter; +#endif /*ENUMS_ArbitraryFilter_H*/ + +#ifndef ENUMS_VolMagFilter_H +#define ENUMS_VolMagFilter_H +typedef enum VolMagFilter { + VOL_MAG_FILTER_POINT = 0, + VOL_MAG_FILTER_LINEAR = 1, + VOL_MAG_FILTER_USE_FETCH_CONST = 3 +} VolMagFilter; +#endif /*ENUMS_VolMagFilter_H*/ + +#ifndef ENUMS_VolMinFilter_H +#define ENUMS_VolMinFilter_H +typedef enum VolMinFilter { + VOL_MIN_FILTER_POINT = 0, + VOL_MIN_FILTER_LINEAR = 1, + VOL_MIN_FILTER_USE_FETCH_CONST = 3 +} VolMinFilter; +#endif /*ENUMS_VolMinFilter_H*/ + +#ifndef ENUMS_PredSelect_H +#define ENUMS_PredSelect_H +typedef enum PredSelect { + NOT_PREDICATED = 0, + PREDICATED = 1 +} PredSelect; +#endif /*ENUMS_PredSelect_H*/ + +#ifndef ENUMS_SampleLocation_H +#define ENUMS_SampleLocation_H +typedef enum SampleLocation { + SAMPLE_CENTROID = 0, + SAMPLE_CENTER = 1 +} SampleLocation; +#endif /*ENUMS_SampleLocation_H*/ + +#ifndef ENUMS_VertexMode_H +#define ENUMS_VertexMode_H +typedef enum VertexMode { + POSITION_1_VECTOR = 0, + POSITION_2_VECTORS_UNUSED = 1, + POSITION_2_VECTORS_SPRITE = 2, + POSITION_2_VECTORS_EDGE = 3, + POSITION_2_VECTORS_KILL = 4, + POSITION_2_VECTORS_SPRITE_KILL = 5, + POSITION_2_VECTORS_EDGE_KILL = 6, + MULTIPASS = 7 +} VertexMode; +#endif /*ENUMS_VertexMode_H*/ + +#ifndef ENUMS_Sample_Cntl_H +#define ENUMS_Sample_Cntl_H +typedef enum Sample_Cntl { + CENTROIDS_ONLY = 0, + CENTERS_ONLY = 1, + CENTROIDS_AND_CENTERS = 2, + UNDEF = 3 +} Sample_Cntl; +#endif /*ENUMS_Sample_Cntl_H*/ + +/******************************************************* + * SX Enums + *******************************************************/ +/******************************************************* + * MH Enums + *******************************************************/ +#ifndef ENUMS_MhPerfEncode_H +#define ENUMS_MhPerfEncode_H +typedef enum MhPerfEncode { + CP_R0_REQUESTS = 0, + CP_R1_REQUESTS = 1, + CP_R2_REQUESTS = 2, + CP_R3_REQUESTS = 3, + CP_R4_REQUESTS = 4, + CP_TOTAL_READ_REQUESTS = 5, + CP_W_REQUESTS = 6, + CP_TOTAL_REQUESTS = 7, + CP_DATA_BYTES_WRITTEN = 8, + CP_WRITE_CLEAN_RESPONSES = 9, + CP_R0_READ_BURSTS_RECEIVED = 10, + CP_R1_READ_BURSTS_RECEIVED = 11, + CP_R2_READ_BURSTS_RECEIVED = 12, + CP_R3_READ_BURSTS_RECEIVED = 13, + CP_R4_READ_BURSTS_RECEIVED = 14, + CP_TOTAL_READ_BURSTS_RECEIVED = 15, + CP_R0_DATA_BEATS_READ = 16, + CP_R1_DATA_BEATS_READ = 17, + CP_R2_DATA_BEATS_READ = 18, + CP_R3_DATA_BEATS_READ = 19, + CP_R4_DATA_BEATS_READ = 20, + CP_TOTAL_DATA_BEATS_READ = 21, + VGT_R0_REQUESTS = 22, + VGT_R1_REQUESTS = 23, + VGT_TOTAL_REQUESTS = 24, + VGT_R0_READ_BURSTS_RECEIVED = 25, + VGT_R1_READ_BURSTS_RECEIVED = 26, + VGT_TOTAL_READ_BURSTS_RECEIVED = 27, + VGT_R0_DATA_BEATS_READ = 28, + VGT_R1_DATA_BEATS_READ = 29, + VGT_TOTAL_DATA_BEATS_READ = 30, + TC_REQUESTS = 31, + TC_ROQ_REQUESTS = 32, + TC_INFO_SENT = 33, + TC_READ_BURSTS_RECEIVED = 34, + TC_DATA_BEATS_READ = 35, + TCD_BURSTS_READ = 36, + RB_REQUESTS = 37, + RB_DATA_BYTES_WRITTEN = 38, + RB_WRITE_CLEAN_RESPONSES = 39, + AXI_READ_REQUESTS_ID_0 = 40, + AXI_READ_REQUESTS_ID_1 = 41, + AXI_READ_REQUESTS_ID_2 = 42, + AXI_READ_REQUESTS_ID_3 = 43, + AXI_READ_REQUESTS_ID_4 = 44, + AXI_READ_REQUESTS_ID_5 = 45, + AXI_READ_REQUESTS_ID_6 = 46, + AXI_READ_REQUESTS_ID_7 = 47, + AXI_TOTAL_READ_REQUESTS = 48, + AXI_WRITE_REQUESTS_ID_0 = 49, + AXI_WRITE_REQUESTS_ID_1 = 50, + AXI_WRITE_REQUESTS_ID_2 = 51, + AXI_WRITE_REQUESTS_ID_3 = 52, + AXI_WRITE_REQUESTS_ID_4 = 53, + AXI_WRITE_REQUESTS_ID_5 = 54, + AXI_WRITE_REQUESTS_ID_6 = 55, + AXI_WRITE_REQUESTS_ID_7 = 56, + AXI_TOTAL_WRITE_REQUESTS = 57, + AXI_TOTAL_REQUESTS_ID_0 = 58, + AXI_TOTAL_REQUESTS_ID_1 = 59, + AXI_TOTAL_REQUESTS_ID_2 = 60, + AXI_TOTAL_REQUESTS_ID_3 = 61, + AXI_TOTAL_REQUESTS_ID_4 = 62, + AXI_TOTAL_REQUESTS_ID_5 = 63, + AXI_TOTAL_REQUESTS_ID_6 = 64, + AXI_TOTAL_REQUESTS_ID_7 = 65, + AXI_TOTAL_REQUESTS = 66, + AXI_READ_CHANNEL_BURSTS_ID_0 = 67, + AXI_READ_CHANNEL_BURSTS_ID_1 = 68, + AXI_READ_CHANNEL_BURSTS_ID_2 = 69, + AXI_READ_CHANNEL_BURSTS_ID_3 = 70, + AXI_READ_CHANNEL_BURSTS_ID_4 = 71, + AXI_READ_CHANNEL_BURSTS_ID_5 = 72, + AXI_READ_CHANNEL_BURSTS_ID_6 = 73, + AXI_READ_CHANNEL_BURSTS_ID_7 = 74, + AXI_READ_CHANNEL_TOTAL_BURSTS = 75, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0 = 76, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1 = 77, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2 = 78, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3 = 79, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4 = 80, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5 = 81, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6 = 82, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7 = 83, + AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ = 84, + AXI_WRITE_CHANNEL_BURSTS_ID_0 = 85, + AXI_WRITE_CHANNEL_BURSTS_ID_1 = 86, + AXI_WRITE_CHANNEL_BURSTS_ID_2 = 87, + AXI_WRITE_CHANNEL_BURSTS_ID_3 = 88, + AXI_WRITE_CHANNEL_BURSTS_ID_4 = 89, + AXI_WRITE_CHANNEL_BURSTS_ID_5 = 90, + AXI_WRITE_CHANNEL_BURSTS_ID_6 = 91, + AXI_WRITE_CHANNEL_BURSTS_ID_7 = 92, + AXI_WRITE_CHANNEL_TOTAL_BURSTS = 93, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0 = 94, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1 = 95, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2 = 96, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3 = 97, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4 = 98, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5 = 99, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6 = 100, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7 = 101, + AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN = 102, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0 = 103, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1 = 104, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2 = 105, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3 = 106, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4 = 107, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5 = 108, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6 = 109, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7 = 110, + AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES = 111, + TOTAL_MMU_MISSES = 112, + MMU_READ_MISSES = 113, + MMU_WRITE_MISSES = 114, + TOTAL_MMU_HITS = 115, + MMU_READ_HITS = 116, + MMU_WRITE_HITS = 117, + SPLIT_MODE_TC_HITS = 118, + SPLIT_MODE_TC_MISSES = 119, + SPLIT_MODE_NON_TC_HITS = 120, + SPLIT_MODE_NON_TC_MISSES = 121, + STALL_AWAITING_TLB_MISS_FETCH = 122, + MMU_TLB_MISS_READ_BURSTS_RECEIVED = 123, + MMU_TLB_MISS_DATA_BEATS_READ = 124, + CP_CYCLES_HELD_OFF = 125, + VGT_CYCLES_HELD_OFF = 126, + TC_CYCLES_HELD_OFF = 127, + TC_ROQ_CYCLES_HELD_OFF = 128, + TC_CYCLES_HELD_OFF_TCD_FULL = 129, + RB_CYCLES_HELD_OFF = 130, + TOTAL_CYCLES_ANY_CLNT_HELD_OFF = 131, + TLB_MISS_CYCLES_HELD_OFF = 132, + AXI_READ_REQUEST_HELD_OFF = 133, + AXI_WRITE_REQUEST_HELD_OFF = 134, + AXI_REQUEST_HELD_OFF = 135, + AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT = 136, + AXI_WRITE_DATA_HELD_OFF = 137, + CP_SAME_PAGE_BANK_REQUESTS = 138, + VGT_SAME_PAGE_BANK_REQUESTS = 139, + TC_SAME_PAGE_BANK_REQUESTS = 140, + TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS = 141, + RB_SAME_PAGE_BANK_REQUESTS = 142, + TOTAL_SAME_PAGE_BANK_REQUESTS = 143, + CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 144, + VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 145, + TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 146, + RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 147, + TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT = 148, + TOTAL_MH_READ_REQUESTS = 149, + TOTAL_MH_WRITE_REQUESTS = 150, + TOTAL_MH_REQUESTS = 151, + MH_BUSY = 152, + CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 153, + VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 154, + TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 155, + RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 156, + TC_ROQ_N_VALID_ENTRIES = 157, + ARQ_N_ENTRIES = 158, + WDB_N_ENTRIES = 159, + MH_READ_LATENCY_OUTST_REQ_SUM = 160, + MC_READ_LATENCY_OUTST_REQ_SUM = 161, + MC_TOTAL_READ_REQUESTS = 162, + ELAPSED_CYCLES_MH_GATED_CLK = 163, +} MhPerfEncode; +#endif /*ENUMS_MhPerfEncode_H*/ + +#ifndef ENUMS_MmuClntBeh_H +#define ENUMS_MmuClntBeh_H +typedef enum MmuClntBeh { + BEH_NEVR = 0, + BEH_TRAN_RNG = 1, + BEH_TRAN_FLT = 2, +} MmuClntBeh; +#endif /*ENUMS_MmuClntBeh_H*/ + +/******************************************************* + * RBBM Enums + *******************************************************/ +#ifndef ENUMS_RBBM_PERFCOUNT1_SEL_H +#define ENUMS_RBBM_PERFCOUNT1_SEL_H +typedef enum RBBM_PERFCOUNT1_SEL { + RBBM1_COUNT = 0, + RBBM1_NRT_BUSY = 1, + RBBM1_RB_BUSY = 2, + RBBM1_SQ_CNTX0_BUSY = 3, + RBBM1_SQ_CNTX17_BUSY = 4, + RBBM1_VGT_BUSY = 5, + RBBM1_VGT_NODMA_BUSY = 6, + RBBM1_PA_BUSY = 7, + RBBM1_SC_CNTX_BUSY = 8, + RBBM1_TPC_BUSY = 9, + RBBM1_TC_BUSY = 10, + RBBM1_SX_BUSY = 11, + RBBM1_CP_COHER_BUSY = 12, + RBBM1_CP_NRT_BUSY = 13, + RBBM1_GFX_IDLE_STALL = 14, + RBBM1_INTERRUPT = 15, +} RBBM_PERFCOUNT1_SEL; +#endif /*ENUMS_RBBM_PERFCOUNT1_SEL_H*/ + +/******************************************************* + * CP Enums + *******************************************************/ +#ifndef ENUMS_CP_PERFCOUNT_SEL_H +#define ENUMS_CP_PERFCOUNT_SEL_H +typedef enum CP_PERFCOUNT_SEL { + ALWAYS_COUNT = 0, + TRANS_FIFO_FULL = 1, + TRANS_FIFO_AF = 2, + RCIU_PFPTRANS_WAIT = 3, + Reserved_04 = 4, + Reserved_05 = 5, + RCIU_NRTTRANS_WAIT = 6, + Reserved_07 = 7, + CSF_NRT_READ_WAIT = 8, + CSF_I1_FIFO_FULL = 9, + CSF_I2_FIFO_FULL = 10, + CSF_ST_FIFO_FULL = 11, + Reserved_12 = 12, + CSF_RING_ROQ_FULL = 13, + CSF_I1_ROQ_FULL = 14, + CSF_I2_ROQ_FULL = 15, + CSF_ST_ROQ_FULL = 16, + Reserved_17 = 17, + MIU_TAG_MEM_FULL = 18, + MIU_WRITECLEAN = 19, + Reserved_20 = 20, + Reserved_21 = 21, + MIU_NRT_WRITE_STALLED = 22, + MIU_NRT_READ_STALLED = 23, + ME_WRITE_CONFIRM_FIFO_FULL = 24, + ME_VS_DEALLOC_FIFO_FULL = 25, + ME_PS_DEALLOC_FIFO_FULL = 26, + ME_REGS_VS_EVENT_FIFO_FULL = 27, + ME_REGS_PS_EVENT_FIFO_FULL = 28, + ME_REGS_CF_EVENT_FIFO_FULL = 29, + ME_MICRO_RB_STARVED = 30, + ME_MICRO_I1_STARVED = 31, + ME_MICRO_I2_STARVED = 32, + ME_MICRO_ST_STARVED = 33, + Reserved_34 = 34, + Reserved_35 = 35, + Reserved_36 = 36, + Reserved_37 = 37, + Reserved_38 = 38, + Reserved_39 = 39, + RCIU_RBBM_DWORD_SENT = 40, + ME_BUSY_CLOCKS = 41, + ME_WAIT_CONTEXT_AVAIL = 42, + PFP_TYPE0_PACKET = 43, + PFP_TYPE3_PACKET = 44, + CSF_RB_WPTR_NEQ_RPTR = 45, + CSF_I1_SIZE_NEQ_ZERO = 46, + CSF_I2_SIZE_NEQ_ZERO = 47, + CSF_RBI1I2_FETCHING = 48, + Reserved_49 = 49, + Reserved_50 = 50, + Reserved_51 = 51, + Reserved_52 = 52, + Reserved_53 = 53, + Reserved_54 = 54, + Reserved_55 = 55, + Reserved_56 = 56, + Reserved_57 = 57, + Reserved_58 = 58, + Reserved_59 = 59, + Reserved_60 = 60, + Reserved_61 = 61, + Reserved_62 = 62, + Reserved_63 = 63 +} CP_PERFCOUNT_SEL; +#endif /*ENUMS_CP_PERFCOUNT_SEL_H*/ + +/******************************************************* + * SC Enums + *******************************************************/ +/******************************************************* + * BC Enums + *******************************************************/ +#ifndef ENUMS_ColorformatX_H +#define ENUMS_ColorformatX_H +typedef enum ColorformatX { + COLORX_4_4_4_4 = 0, + COLORX_1_5_5_5 = 1, + COLORX_5_6_5 = 2, + COLORX_8 = 3, + COLORX_8_8 = 4, + COLORX_8_8_8_8 = 5, + COLORX_S8_8_8_8 = 6, + COLORX_16_FLOAT = 7, + COLORX_16_16_FLOAT = 8, + COLORX_16_16_16_16_FLOAT = 9, + COLORX_32_FLOAT = 10, + COLORX_32_32_FLOAT = 11, + COLORX_32_32_32_32_FLOAT = 12, + COLORX_2_3_3 = 13, + COLORX_8_8_8 = 14, +} ColorformatX; +#endif /*ENUMS_ColorformatX_H*/ + +#ifndef ENUMS_DepthformatX_H +#define ENUMS_DepthformatX_H +typedef enum DepthformatX { + DEPTHX_16 = 0, + DEPTHX_24_8 = 1 +} DepthformatX; +#endif /*ENUMS_DepthformatX_H*/ + +#ifndef ENUMS_CompareFrag_H +#define ENUMS_CompareFrag_H +typedef enum CompareFrag { + FRAG_NEVER = 0, + FRAG_LESS = 1, + FRAG_EQUAL = 2, + FRAG_LEQUAL = 3, + FRAG_GREATER = 4, + FRAG_NOTEQUAL = 5, + FRAG_GEQUAL = 6, + FRAG_ALWAYS = 7 +} CompareFrag; +#endif /*ENUMS_CompareFrag_H*/ + +#ifndef ENUMS_CompareRef_H +#define ENUMS_CompareRef_H +typedef enum CompareRef { + REF_NEVER = 0, + REF_LESS = 1, + REF_EQUAL = 2, + REF_LEQUAL = 3, + REF_GREATER = 4, + REF_NOTEQUAL = 5, + REF_GEQUAL = 6, + REF_ALWAYS = 7 +} CompareRef; +#endif /*ENUMS_CompareRef_H*/ + +#ifndef ENUMS_StencilOp_H +#define ENUMS_StencilOp_H +typedef enum StencilOp { + STENCIL_KEEP = 0, + STENCIL_ZERO = 1, + STENCIL_REPLACE = 2, + STENCIL_INCR_CLAMP = 3, + STENCIL_DECR_CLAMP = 4, + STENCIL_INVERT = 5, + STENCIL_INCR_WRAP = 6, + STENCIL_DECR_WRAP = 7 +} StencilOp; +#endif /*ENUMS_StencilOp_H*/ + +#ifndef ENUMS_BlendOpX_H +#define ENUMS_BlendOpX_H +typedef enum BlendOpX { + BLENDX_ZERO = 0, + BLENDX_ONE = 1, + BLENDX_SRC_COLOR = 4, + BLENDX_ONE_MINUS_SRC_COLOR = 5, + BLENDX_SRC_ALPHA = 6, + BLENDX_ONE_MINUS_SRC_ALPHA = 7, + BLENDX_DST_COLOR = 8, + BLENDX_ONE_MINUS_DST_COLOR = 9, + BLENDX_DST_ALPHA = 10, + BLENDX_ONE_MINUS_DST_ALPHA = 11, + BLENDX_CONSTANT_COLOR = 12, + BLENDX_ONE_MINUS_CONSTANT_COLOR = 13, + BLENDX_CONSTANT_ALPHA = 14, + BLENDX_ONE_MINUS_CONSTANT_ALPHA = 15, + BLENDX_SRC_ALPHA_SATURATE = 16, +} BlendOpX; +#endif /*ENUMS_BlendOpX_H*/ + +#ifndef ENUMS_CombFuncX_H +#define ENUMS_CombFuncX_H +typedef enum CombFuncX { + COMB_DST_PLUS_SRC = 0, + COMB_SRC_MINUS_DST = 1, + COMB_MIN_DST_SRC = 2, + COMB_MAX_DST_SRC = 3, + COMB_DST_MINUS_SRC = 4, + COMB_DST_PLUS_SRC_BIAS = 5, +} CombFuncX; +#endif /*ENUMS_CombFuncX_H*/ + +#ifndef ENUMS_DitherModeX_H +#define ENUMS_DitherModeX_H +typedef enum DitherModeX { + DITHER_DISABLE = 0, + DITHER_ALWAYS = 1, + DITHER_IF_ALPHA_OFF = 2, +} DitherModeX; +#endif /*ENUMS_DitherModeX_H*/ + +#ifndef ENUMS_DitherTypeX_H +#define ENUMS_DitherTypeX_H +typedef enum DitherTypeX { + DITHER_PIXEL = 0, + DITHER_SUBPIXEL = 1, +} DitherTypeX; +#endif /*ENUMS_DitherTypeX_H*/ + +#ifndef ENUMS_EdramMode_H +#define ENUMS_EdramMode_H +typedef enum EdramMode { + EDRAM_NOP = 0, + COLOR_DEPTH = 4, + DEPTH_ONLY = 5, + EDRAM_COPY = 6, +} EdramMode; +#endif /*ENUMS_EdramMode_H*/ + +#ifndef ENUMS_SurfaceEndian_H +#define ENUMS_SurfaceEndian_H +typedef enum SurfaceEndian { + ENDIAN_NONE = 0, + ENDIAN_8IN16 = 1, + ENDIAN_8IN32 = 2, + ENDIAN_16IN32 = 3, + ENDIAN_8IN64 = 4, + ENDIAN_8IN128 = 5, +} SurfaceEndian; +#endif /*ENUMS_SurfaceEndian_H*/ + +#ifndef ENUMS_EdramSizeX_H +#define ENUMS_EdramSizeX_H +typedef enum EdramSizeX { + EDRAMSIZE_16KB = 0, + EDRAMSIZE_32KB = 1, + EDRAMSIZE_64KB = 2, + EDRAMSIZE_128KB = 3, + EDRAMSIZE_256KB = 4, + EDRAMSIZE_512KB = 5, + EDRAMSIZE_1MB = 6, + EDRAMSIZE_2MB = 7, + EDRAMSIZE_4MB = 8, + EDRAMSIZE_8MB = 9, + EDRAMSIZE_16MB = 10, +} EdramSizeX; +#endif /*ENUMS_EdramSizeX_H*/ + +#ifndef ENUMS_RB_PERFCNT_SELECT_H +#define ENUMS_RB_PERFCNT_SELECT_H +typedef enum RB_PERFCNT_SELECT { + RBPERF_CNTX_BUSY = 0, + RBPERF_CNTX_BUSY_MAX = 1, + RBPERF_SX_QUAD_STARVED = 2, + RBPERF_SX_QUAD_STARVED_MAX = 3, + RBPERF_GA_GC_CH0_SYS_REQ = 4, + RBPERF_GA_GC_CH0_SYS_REQ_MAX = 5, + RBPERF_GA_GC_CH1_SYS_REQ = 6, + RBPERF_GA_GC_CH1_SYS_REQ_MAX = 7, + RBPERF_MH_STARVED = 8, + RBPERF_MH_STARVED_MAX = 9, + RBPERF_AZ_BC_COLOR_BUSY = 10, + RBPERF_AZ_BC_COLOR_BUSY_MAX = 11, + RBPERF_AZ_BC_Z_BUSY = 12, + RBPERF_AZ_BC_Z_BUSY_MAX = 13, + RBPERF_RB_SC_TILE_RTR_N = 14, + RBPERF_RB_SC_TILE_RTR_N_MAX = 15, + RBPERF_RB_SC_SAMP_RTR_N = 16, + RBPERF_RB_SC_SAMP_RTR_N_MAX = 17, + RBPERF_RB_SX_QUAD_RTR_N = 18, + RBPERF_RB_SX_QUAD_RTR_N_MAX = 19, + RBPERF_RB_SX_COLOR_RTR_N = 20, + RBPERF_RB_SX_COLOR_RTR_N_MAX = 21, + RBPERF_RB_SC_SAMP_LZ_BUSY = 22, + RBPERF_RB_SC_SAMP_LZ_BUSY_MAX = 23, + RBPERF_ZXP_STALL = 24, + RBPERF_ZXP_STALL_MAX = 25, + RBPERF_EVENT_PENDING = 26, + RBPERF_EVENT_PENDING_MAX = 27, + RBPERF_RB_MH_VALID = 28, + RBPERF_RB_MH_VALID_MAX = 29, + RBPERF_SX_RB_QUAD_SEND = 30, + RBPERF_SX_RB_COLOR_SEND = 31, + RBPERF_SC_RB_TILE_SEND = 32, + RBPERF_SC_RB_SAMPLE_SEND = 33, + RBPERF_SX_RB_MEM_EXPORT = 34, + RBPERF_SX_RB_QUAD_EVENT = 35, + RBPERF_SC_RB_TILE_EVENT_FILTERED = 36, + RBPERF_SC_RB_TILE_EVENT_ALL = 37, + RBPERF_RB_SC_EZ_SEND = 38, + RBPERF_RB_SX_INDEX_SEND = 39, + RBPERF_GMEM_INTFO_RD = 40, + RBPERF_GMEM_INTF1_RD = 41, + RBPERF_GMEM_INTFO_WR = 42, + RBPERF_GMEM_INTF1_WR = 43, + RBPERF_RB_CP_CONTEXT_DONE = 44, + RBPERF_RB_CP_CACHE_FLUSH = 45, + RBPERF_ZPASS_DONE = 46, + RBPERF_ZCMD_VALID = 47, + RBPERF_CCMD_VALID = 48, + RBPERF_ACCUM_GRANT = 49, + RBPERF_ACCUM_C0_GRANT = 50, + RBPERF_ACCUM_C1_GRANT = 51, + RBPERF_ACCUM_FULL_BE_WR = 52, + RBPERF_ACCUM_REQUEST_NO_GRANT = 53, + RBPERF_ACCUM_TIMEOUT_PULSE = 54, + RBPERF_ACCUM_LIN_TIMEOUT_PULSE = 55, + RBPERF_ACCUM_CAM_HIT_FLUSHING = 56, +} RB_PERFCNT_SELECT; +#endif /*ENUMS_RB_PERFCNT_SELECT_H*/ + +#ifndef ENUMS_DepthFormat_H +#define ENUMS_DepthFormat_H +typedef enum DepthFormat { + DEPTH_24_8 = 22, + DEPTH_24_8_FLOAT = 23, + DEPTH_16 = 24, +} DepthFormat; +#endif /*ENUMS_DepthFormat_H*/ + +#ifndef ENUMS_SurfaceSwap_H +#define ENUMS_SurfaceSwap_H +typedef enum SurfaceSwap { + SWAP_LOWRED = 0, + SWAP_LOWBLUE = 1 +} SurfaceSwap; +#endif /*ENUMS_SurfaceSwap_H*/ + +#ifndef ENUMS_DepthArray_H +#define ENUMS_DepthArray_H +typedef enum DepthArray { + ARRAY_2D_ALT_DEPTH = 0, + ARRAY_2D_DEPTH = 1, +} DepthArray; +#endif /*ENUMS_DepthArray_H*/ + +#ifndef ENUMS_ColorArray_H +#define ENUMS_ColorArray_H +typedef enum ColorArray { + ARRAY_2D_ALT_COLOR = 0, + ARRAY_2D_COLOR = 1, + ARRAY_3D_SLICE_COLOR = 3 +} ColorArray; +#endif /*ENUMS_ColorArray_H*/ + +#ifndef ENUMS_ColorFormat_H +#define ENUMS_ColorFormat_H +typedef enum ColorFormat { + COLOR_8 = 2, + COLOR_1_5_5_5 = 3, + COLOR_5_6_5 = 4, + COLOR_6_5_5 = 5, + COLOR_8_8_8_8 = 6, + COLOR_2_10_10_10 = 7, + COLOR_8_A = 8, + COLOR_8_B = 9, + COLOR_8_8 = 10, + COLOR_8_8_8 = 11, + COLOR_8_8_8_8_A = 14, + COLOR_4_4_4_4 = 15, + COLOR_10_11_11 = 16, + COLOR_11_11_10 = 17, + COLOR_16 = 24, + COLOR_16_16 = 25, + COLOR_16_16_16_16 = 26, + COLOR_16_FLOAT = 30, + COLOR_16_16_FLOAT = 31, + COLOR_16_16_16_16_FLOAT = 32, + COLOR_32_FLOAT = 36, + COLOR_32_32_FLOAT = 37, + COLOR_32_32_32_32_FLOAT = 38, + COLOR_2_3_3 = 39, +} ColorFormat; +#endif /*ENUMS_ColorFormat_H*/ + +#ifndef ENUMS_SurfaceNumber_H +#define ENUMS_SurfaceNumber_H +typedef enum SurfaceNumber { + NUMBER_UREPEAT = 0, + NUMBER_SREPEAT = 1, + NUMBER_UINTEGER = 2, + NUMBER_SINTEGER = 3, + NUMBER_GAMMA = 4, + NUMBER_FIXED = 5, + NUMBER_FLOAT = 7 +} SurfaceNumber; +#endif /*ENUMS_SurfaceNumber_H*/ + +#ifndef ENUMS_SurfaceFormat_H +#define ENUMS_SurfaceFormat_H +typedef enum SurfaceFormat { + FMT_1_REVERSE = 0, + FMT_1 = 1, + FMT_8 = 2, + FMT_1_5_5_5 = 3, + FMT_5_6_5 = 4, + FMT_6_5_5 = 5, + FMT_8_8_8_8 = 6, + FMT_2_10_10_10 = 7, + FMT_8_A = 8, + FMT_8_B = 9, + FMT_8_8 = 10, + FMT_Cr_Y1_Cb_Y0 = 11, + FMT_Y1_Cr_Y0_Cb = 12, + FMT_5_5_5_1 = 13, + FMT_8_8_8_8_A = 14, + FMT_4_4_4_4 = 15, + FMT_8_8_8 = 16, + FMT_DXT1 = 18, + FMT_DXT2_3 = 19, + FMT_DXT4_5 = 20, + FMT_10_10_10_2 = 21, + FMT_24_8 = 22, + FMT_16 = 24, + FMT_16_16 = 25, + FMT_16_16_16_16 = 26, + FMT_16_EXPAND = 27, + FMT_16_16_EXPAND = 28, + FMT_16_16_16_16_EXPAND = 29, + FMT_16_FLOAT = 30, + FMT_16_16_FLOAT = 31, + FMT_16_16_16_16_FLOAT = 32, + FMT_32 = 33, + FMT_32_32 = 34, + FMT_32_32_32_32 = 35, + FMT_32_FLOAT = 36, + FMT_32_32_FLOAT = 37, + FMT_32_32_32_32_FLOAT = 38, + FMT_ATI_TC_RGB = 39, + FMT_ATI_TC_RGBA = 40, + FMT_ATI_TC_555_565_RGB = 41, + FMT_ATI_TC_555_565_RGBA = 42, + FMT_ATI_TC_RGBA_INTERP = 43, + FMT_ATI_TC_555_565_RGBA_INTERP = 44, + FMT_ETC1_RGBA_INTERP = 46, + FMT_ETC1_RGB = 47, + FMT_ETC1_RGBA = 48, + FMT_DXN = 49, + FMT_2_3_3 = 51, + FMT_2_10_10_10_AS_16_16_16_16 = 54, + FMT_10_10_10_2_AS_16_16_16_16 = 55, + FMT_32_32_32_FLOAT = 57, + FMT_DXT3A = 58, + FMT_DXT5A = 59, + FMT_CTX1 = 60, +} SurfaceFormat; +#endif /*ENUMS_SurfaceFormat_H*/ + +#ifndef ENUMS_SurfaceTiling_H +#define ENUMS_SurfaceTiling_H +typedef enum SurfaceTiling { + ARRAY_LINEAR = 0, + ARRAY_TILED = 1 +} SurfaceTiling; +#endif /*ENUMS_SurfaceTiling_H*/ + +#ifndef ENUMS_SurfaceArray_H +#define ENUMS_SurfaceArray_H +typedef enum SurfaceArray { + ARRAY_1D = 0, + ARRAY_2D = 1, + ARRAY_3D = 2, + ARRAY_3D_SLICE = 3 +} SurfaceArray; +#endif /*ENUMS_SurfaceArray_H*/ + +#ifndef ENUMS_SurfaceNumberX_H +#define ENUMS_SurfaceNumberX_H +typedef enum SurfaceNumberX { + NUMBERX_UREPEAT = 0, + NUMBERX_SREPEAT = 1, + NUMBERX_UINTEGER = 2, + NUMBERX_SINTEGER = 3, + NUMBERX_FLOAT = 7 +} SurfaceNumberX; +#endif /*ENUMS_SurfaceNumberX_H*/ + +#ifndef ENUMS_ColorArrayX_H +#define ENUMS_ColorArrayX_H +typedef enum ColorArrayX { + ARRAYX_2D_COLOR = 0, + ARRAYX_3D_SLICE_COLOR = 1, +} ColorArrayX; +#endif /*ENUMS_ColorArrayX_H*/ + +#endif /*_yamato_ENUM_HEADER*/ + diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_genenum.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_genenum.h new file mode 100644 index 000000000000..f2f4dec63daa --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_genenum.h @@ -0,0 +1,1674 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +START_ENUMTYPE(SU_PERFCNT_SELECT) + GENERATE_ENUM(PERF_PAPC_PASX_REQ, 0) + GENERATE_ENUM(UNUSED1, 1) + GENERATE_ENUM(PERF_PAPC_PASX_FIRST_VECTOR, 2) + GENERATE_ENUM(PERF_PAPC_PASX_SECOND_VECTOR, 3) + GENERATE_ENUM(PERF_PAPC_PASX_FIRST_DEAD, 4) + GENERATE_ENUM(PERF_PAPC_PASX_SECOND_DEAD, 5) + GENERATE_ENUM(PERF_PAPC_PASX_VTX_KILL_DISCARD, 6) + GENERATE_ENUM(PERF_PAPC_PASX_VTX_NAN_DISCARD, 7) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_PRIM, 8) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_NULL_PRIM, 9) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_EVENT_FLAG, 10) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT, 11) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_END_OF_PACKET, 12) + GENERATE_ENUM(PERF_PAPC_CLPR_CULL_PRIM, 13) + GENERATE_ENUM(UNUSED2, 14) + GENERATE_ENUM(PERF_PAPC_CLPR_VV_CULL_PRIM, 15) + GENERATE_ENUM(UNUSED3, 16) + GENERATE_ENUM(PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM, 17) + GENERATE_ENUM(PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM, 18) + GENERATE_ENUM(PERF_PAPC_CLPR_CULL_TO_NULL_PRIM, 19) + GENERATE_ENUM(UNUSED4, 20) + GENERATE_ENUM(PERF_PAPC_CLPR_VV_CLIP_PRIM, 21) + GENERATE_ENUM(UNUSED5, 22) + GENERATE_ENUM(PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE, 23) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_1, 24) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_2, 25) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_3, 26) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_4, 27) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_5, 28) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_6, 29) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_NEAR, 30) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_FAR, 31) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_LEFT, 32) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_RIGHT, 33) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_TOP, 34) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM, 35) + GENERATE_ENUM(PERF_PAPC_CLSM_NULL_PRIM, 36) + GENERATE_ENUM(PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM, 37) + GENERATE_ENUM(PERF_PAPC_CLSM_CLIP_PRIM, 38) + GENERATE_ENUM(PERF_PAPC_CLSM_CULL_TO_NULL_PRIM, 39) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_1, 40) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_2, 41) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_3, 42) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_4, 43) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_5, 44) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7, 45) + GENERATE_ENUM(PERF_PAPC_CLSM_NON_TRIVIAL_CULL, 46) + GENERATE_ENUM(PERF_PAPC_SU_INPUT_PRIM, 47) + GENERATE_ENUM(PERF_PAPC_SU_INPUT_CLIP_PRIM, 48) + GENERATE_ENUM(PERF_PAPC_SU_INPUT_NULL_PRIM, 49) + GENERATE_ENUM(PERF_PAPC_SU_ZERO_AREA_CULL_PRIM, 50) + GENERATE_ENUM(PERF_PAPC_SU_BACK_FACE_CULL_PRIM, 51) + GENERATE_ENUM(PERF_PAPC_SU_FRONT_FACE_CULL_PRIM, 52) + GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_FACE_CULL, 53) + GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_BACK_CULL, 54) + GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_FRONT_CULL, 55) + GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_INVALID_FILL, 56) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_PRIM, 57) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_CLIP_PRIM, 58) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_NULL_PRIM, 59) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_EVENT_FLAG, 60) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT, 61) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_END_OF_PACKET, 62) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_FACE, 63) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_BACK, 64) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT, 65) + GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE, 66) + GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK, 67) + GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT, 68) + GENERATE_ENUM(PERF_PAPC_PASX_REQ_IDLE, 69) + GENERATE_ENUM(PERF_PAPC_PASX_REQ_BUSY, 70) + GENERATE_ENUM(PERF_PAPC_PASX_REQ_STALLED, 71) + GENERATE_ENUM(PERF_PAPC_PASX_REC_IDLE, 72) + GENERATE_ENUM(PERF_PAPC_PASX_REC_BUSY, 73) + GENERATE_ENUM(PERF_PAPC_PASX_REC_STARVED_SX, 74) + GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED, 75) + GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED_POS_MEM, 76) + GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED_CCGSM_IN, 77) + GENERATE_ENUM(PERF_PAPC_CCGSM_IDLE, 78) + GENERATE_ENUM(PERF_PAPC_CCGSM_BUSY, 79) + GENERATE_ENUM(PERF_PAPC_CCGSM_STALLED, 80) + GENERATE_ENUM(PERF_PAPC_CLPRIM_IDLE, 81) + GENERATE_ENUM(PERF_PAPC_CLPRIM_BUSY, 82) + GENERATE_ENUM(PERF_PAPC_CLPRIM_STALLED, 83) + GENERATE_ENUM(PERF_PAPC_CLPRIM_STARVED_CCGSM, 84) + GENERATE_ENUM(PERF_PAPC_CLIPSM_IDLE, 85) + GENERATE_ENUM(PERF_PAPC_CLIPSM_BUSY, 86) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH, 87) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ, 88) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIPGA, 89) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP, 90) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM, 91) + GENERATE_ENUM(PERF_PAPC_CLIPGA_IDLE, 92) + GENERATE_ENUM(PERF_PAPC_CLIPGA_BUSY, 93) + GENERATE_ENUM(PERF_PAPC_CLIPGA_STARVED_VTE_CLIP, 94) + GENERATE_ENUM(PERF_PAPC_CLIPGA_STALLED, 95) + GENERATE_ENUM(PERF_PAPC_CLIP_IDLE, 96) + GENERATE_ENUM(PERF_PAPC_CLIP_BUSY, 97) + GENERATE_ENUM(PERF_PAPC_SU_IDLE, 98) + GENERATE_ENUM(PERF_PAPC_SU_BUSY, 99) + GENERATE_ENUM(PERF_PAPC_SU_STARVED_CLIP, 100) + GENERATE_ENUM(PERF_PAPC_SU_STALLED_SC, 101) +END_ENUMTYPE(SU_PERFCNT_SELECT) + +START_ENUMTYPE(SC_PERFCNT_SELECT) + GENERATE_ENUM(SC_SR_WINDOW_VALID, 0) + GENERATE_ENUM(SC_CW_WINDOW_VALID, 1) + GENERATE_ENUM(SC_QM_WINDOW_VALID, 2) + GENERATE_ENUM(SC_FW_WINDOW_VALID, 3) + GENERATE_ENUM(SC_EZ_WINDOW_VALID, 4) + GENERATE_ENUM(SC_IT_WINDOW_VALID, 5) + GENERATE_ENUM(SC_STARVED_BY_PA, 6) + GENERATE_ENUM(SC_STALLED_BY_RB_TILE, 7) + GENERATE_ENUM(SC_STALLED_BY_RB_SAMP, 8) + GENERATE_ENUM(SC_STARVED_BY_RB_EZ, 9) + GENERATE_ENUM(SC_STALLED_BY_SAMPLE_FF, 10) + GENERATE_ENUM(SC_STALLED_BY_SQ, 11) + GENERATE_ENUM(SC_STALLED_BY_SP, 12) + GENERATE_ENUM(SC_TOTAL_NO_PRIMS, 13) + GENERATE_ENUM(SC_NON_EMPTY_PRIMS, 14) + GENERATE_ENUM(SC_NO_TILES_PASSING_QM, 15) + GENERATE_ENUM(SC_NO_PIXELS_PRE_EZ, 16) + GENERATE_ENUM(SC_NO_PIXELS_POST_EZ, 17) +END_ENUMTYPE(SC_PERFCNT_SELECT) + +START_ENUMTYPE(VGT_DI_PRIM_TYPE) + GENERATE_ENUM(DI_PT_NONE, 0) + GENERATE_ENUM(DI_PT_POINTLIST, 1) + GENERATE_ENUM(DI_PT_LINELIST, 2) + GENERATE_ENUM(DI_PT_LINESTRIP, 3) + GENERATE_ENUM(DI_PT_TRILIST, 4) + GENERATE_ENUM(DI_PT_TRIFAN, 5) + GENERATE_ENUM(DI_PT_TRISTRIP, 6) + GENERATE_ENUM(DI_PT_UNUSED_1, 7) + GENERATE_ENUM(DI_PT_RECTLIST, 8) + GENERATE_ENUM(DI_PT_UNUSED_2, 9) + GENERATE_ENUM(DI_PT_UNUSED_3, 10) + GENERATE_ENUM(DI_PT_UNUSED_4, 11) + GENERATE_ENUM(DI_PT_UNUSED_5, 12) + GENERATE_ENUM(DI_PT_QUADLIST, 13) + GENERATE_ENUM(DI_PT_QUADSTRIP, 14) + GENERATE_ENUM(DI_PT_POLYGON, 15) + GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V0, 16) + GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V1, 17) + GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V2, 18) + GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V3, 19) + GENERATE_ENUM(DI_PT_2D_FILL_RECT_LIST, 20) + GENERATE_ENUM(DI_PT_2D_LINE_STRIP, 21) + GENERATE_ENUM(DI_PT_2D_TRI_STRIP, 22) +END_ENUMTYPE(VGT_DI_PRIM_TYPE) + +START_ENUMTYPE(VGT_DI_SOURCE_SELECT) + GENERATE_ENUM(DI_SRC_SEL_DMA, 0) + GENERATE_ENUM(DI_SRC_SEL_IMMEDIATE, 1) + GENERATE_ENUM(DI_SRC_SEL_AUTO_INDEX, 2) + GENERATE_ENUM(DI_SRC_SEL_RESERVED, 3) +END_ENUMTYPE(VGT_DI_SOURCE_SELECT) + +START_ENUMTYPE(VGT_DI_INDEX_SIZE) + GENERATE_ENUM(DI_INDEX_SIZE_16_BIT, 0) + GENERATE_ENUM(DI_INDEX_SIZE_32_BIT, 1) +END_ENUMTYPE(VGT_DI_INDEX_SIZE) + +START_ENUMTYPE(VGT_DI_SMALL_INDEX) + GENERATE_ENUM(DI_USE_INDEX_SIZE, 0) + GENERATE_ENUM(DI_INDEX_SIZE_8_BIT, 1) +END_ENUMTYPE(VGT_DI_SMALL_INDEX) + +START_ENUMTYPE(VGT_DI_PRE_FETCH_CULL_ENABLE) + GENERATE_ENUM(DISABLE_PRE_FETCH_CULL_ENABLE, 0) + GENERATE_ENUM(PRE_FETCH_CULL_ENABLE, 1) +END_ENUMTYPE(VGT_DI_PRE_FETCH_CULL_ENABLE) + +START_ENUMTYPE(VGT_DI_GRP_CULL_ENABLE) + GENERATE_ENUM(DISABLE_GRP_CULL_ENABLE, 0) + GENERATE_ENUM(GRP_CULL_ENABLE, 1) +END_ENUMTYPE(VGT_DI_GRP_CULL_ENABLE) + +START_ENUMTYPE(VGT_EVENT_TYPE) + GENERATE_ENUM(VS_DEALLOC, 0) + GENERATE_ENUM(PS_DEALLOC, 1) + GENERATE_ENUM(VS_DONE_TS, 2) + GENERATE_ENUM(PS_DONE_TS, 3) + GENERATE_ENUM(CACHE_FLUSH_TS, 4) + GENERATE_ENUM(CONTEXT_DONE, 5) + GENERATE_ENUM(CACHE_FLUSH, 6) + GENERATE_ENUM(VIZQUERY_START, 7) + GENERATE_ENUM(VIZQUERY_END, 8) + GENERATE_ENUM(SC_WAIT_WC, 9) + GENERATE_ENUM(RST_PIX_CNT, 13) + GENERATE_ENUM(RST_VTX_CNT, 14) + GENERATE_ENUM(TILE_FLUSH, 15) + GENERATE_ENUM(CACHE_FLUSH_AND_INV_TS_EVENT, 20) + GENERATE_ENUM(ZPASS_DONE, 21) + GENERATE_ENUM(CACHE_FLUSH_AND_INV_EVENT, 22) + GENERATE_ENUM(PERFCOUNTER_START, 23) + GENERATE_ENUM(PERFCOUNTER_STOP, 24) + GENERATE_ENUM(VS_FETCH_DONE, 27) +END_ENUMTYPE(VGT_EVENT_TYPE) + +START_ENUMTYPE(VGT_DMA_SWAP_MODE) + GENERATE_ENUM(VGT_DMA_SWAP_NONE, 0) + GENERATE_ENUM(VGT_DMA_SWAP_16_BIT, 1) + GENERATE_ENUM(VGT_DMA_SWAP_32_BIT, 2) + GENERATE_ENUM(VGT_DMA_SWAP_WORD, 3) +END_ENUMTYPE(VGT_DMA_SWAP_MODE) + +START_ENUMTYPE(VGT_PERFCOUNT_SELECT) + GENERATE_ENUM(VGT_SQ_EVENT_WINDOW_ACTIVE, 0) + GENERATE_ENUM(VGT_SQ_SEND, 1) + GENERATE_ENUM(VGT_SQ_STALLED, 2) + GENERATE_ENUM(VGT_SQ_STARVED_BUSY, 3) + GENERATE_ENUM(VGT_SQ_STARVED_IDLE, 4) + GENERATE_ENUM(VGT_SQ_STATIC, 5) + GENERATE_ENUM(VGT_PA_EVENT_WINDOW_ACTIVE, 6) + GENERATE_ENUM(VGT_PA_CLIP_V_SEND, 7) + GENERATE_ENUM(VGT_PA_CLIP_V_STALLED, 8) + GENERATE_ENUM(VGT_PA_CLIP_V_STARVED_BUSY, 9) + GENERATE_ENUM(VGT_PA_CLIP_V_STARVED_IDLE, 10) + GENERATE_ENUM(VGT_PA_CLIP_V_STATIC, 11) + GENERATE_ENUM(VGT_PA_CLIP_P_SEND, 12) + GENERATE_ENUM(VGT_PA_CLIP_P_STALLED, 13) + GENERATE_ENUM(VGT_PA_CLIP_P_STARVED_BUSY, 14) + GENERATE_ENUM(VGT_PA_CLIP_P_STARVED_IDLE, 15) + GENERATE_ENUM(VGT_PA_CLIP_P_STATIC, 16) + GENERATE_ENUM(VGT_PA_CLIP_S_SEND, 17) + GENERATE_ENUM(VGT_PA_CLIP_S_STALLED, 18) + GENERATE_ENUM(VGT_PA_CLIP_S_STARVED_BUSY, 19) + GENERATE_ENUM(VGT_PA_CLIP_S_STARVED_IDLE, 20) + GENERATE_ENUM(VGT_PA_CLIP_S_STATIC, 21) + GENERATE_ENUM(RBIU_FIFOS_EVENT_WINDOW_ACTIVE, 22) + GENERATE_ENUM(RBIU_IMMED_DATA_FIFO_STARVED, 23) + GENERATE_ENUM(RBIU_IMMED_DATA_FIFO_STALLED, 24) + GENERATE_ENUM(RBIU_DMA_REQUEST_FIFO_STARVED, 25) + GENERATE_ENUM(RBIU_DMA_REQUEST_FIFO_STALLED, 26) + GENERATE_ENUM(RBIU_DRAW_INITIATOR_FIFO_STARVED, 27) + GENERATE_ENUM(RBIU_DRAW_INITIATOR_FIFO_STALLED, 28) + GENERATE_ENUM(BIN_PRIM_NEAR_CULL, 29) + GENERATE_ENUM(BIN_PRIM_ZERO_CULL, 30) + GENERATE_ENUM(BIN_PRIM_FAR_CULL, 31) + GENERATE_ENUM(BIN_PRIM_BIN_CULL, 32) + GENERATE_ENUM(SPARE33, 33) + GENERATE_ENUM(SPARE34, 34) + GENERATE_ENUM(SPARE35, 35) + GENERATE_ENUM(SPARE36, 36) + GENERATE_ENUM(SPARE37, 37) + GENERATE_ENUM(SPARE38, 38) + GENERATE_ENUM(SPARE39, 39) + GENERATE_ENUM(TE_SU_IN_VALID, 40) + GENERATE_ENUM(TE_SU_IN_READ, 41) + GENERATE_ENUM(TE_SU_IN_PRIM, 42) + GENERATE_ENUM(TE_SU_IN_EOP, 43) + GENERATE_ENUM(TE_SU_IN_NULL_PRIM, 44) + GENERATE_ENUM(TE_WK_IN_VALID, 45) + GENERATE_ENUM(TE_WK_IN_READ, 46) + GENERATE_ENUM(TE_OUT_PRIM_VALID, 47) + GENERATE_ENUM(TE_OUT_PRIM_READ, 48) +END_ENUMTYPE(VGT_PERFCOUNT_SELECT) + +START_ENUMTYPE(TCR_PERFCOUNT_SELECT) + GENERATE_ENUM(DGMMPD_IPMUX0_STALL, 0) + GENERATE_ENUM(reserved_46, 1) + GENERATE_ENUM(reserved_47, 2) + GENERATE_ENUM(reserved_48, 3) + GENERATE_ENUM(DGMMPD_IPMUX_ALL_STALL, 4) + GENERATE_ENUM(OPMUX0_L2_WRITES, 5) + GENERATE_ENUM(reserved_49, 6) + GENERATE_ENUM(reserved_50, 7) + GENERATE_ENUM(reserved_51, 8) +END_ENUMTYPE(TCR_PERFCOUNT_SELECT) + +START_ENUMTYPE(TP_PERFCOUNT_SELECT) + GENERATE_ENUM(POINT_QUADS, 0) + GENERATE_ENUM(BILIN_QUADS, 1) + GENERATE_ENUM(ANISO_QUADS, 2) + GENERATE_ENUM(MIP_QUADS, 3) + GENERATE_ENUM(VOL_QUADS, 4) + GENERATE_ENUM(MIP_VOL_QUADS, 5) + GENERATE_ENUM(MIP_ANISO_QUADS, 6) + GENERATE_ENUM(VOL_ANISO_QUADS, 7) + GENERATE_ENUM(ANISO_2_1_QUADS, 8) + GENERATE_ENUM(ANISO_4_1_QUADS, 9) + GENERATE_ENUM(ANISO_6_1_QUADS, 10) + GENERATE_ENUM(ANISO_8_1_QUADS, 11) + GENERATE_ENUM(ANISO_10_1_QUADS, 12) + GENERATE_ENUM(ANISO_12_1_QUADS, 13) + GENERATE_ENUM(ANISO_14_1_QUADS, 14) + GENERATE_ENUM(ANISO_16_1_QUADS, 15) + GENERATE_ENUM(MIP_VOL_ANISO_QUADS, 16) + GENERATE_ENUM(ALIGN_2_QUADS, 17) + GENERATE_ENUM(ALIGN_4_QUADS, 18) + GENERATE_ENUM(PIX_0_QUAD, 19) + GENERATE_ENUM(PIX_1_QUAD, 20) + GENERATE_ENUM(PIX_2_QUAD, 21) + GENERATE_ENUM(PIX_3_QUAD, 22) + GENERATE_ENUM(PIX_4_QUAD, 23) + GENERATE_ENUM(TP_MIPMAP_LOD0, 24) + GENERATE_ENUM(TP_MIPMAP_LOD1, 25) + GENERATE_ENUM(TP_MIPMAP_LOD2, 26) + GENERATE_ENUM(TP_MIPMAP_LOD3, 27) + GENERATE_ENUM(TP_MIPMAP_LOD4, 28) + GENERATE_ENUM(TP_MIPMAP_LOD5, 29) + GENERATE_ENUM(TP_MIPMAP_LOD6, 30) + GENERATE_ENUM(TP_MIPMAP_LOD7, 31) + GENERATE_ENUM(TP_MIPMAP_LOD8, 32) + GENERATE_ENUM(TP_MIPMAP_LOD9, 33) + GENERATE_ENUM(TP_MIPMAP_LOD10, 34) + GENERATE_ENUM(TP_MIPMAP_LOD11, 35) + GENERATE_ENUM(TP_MIPMAP_LOD12, 36) + GENERATE_ENUM(TP_MIPMAP_LOD13, 37) + GENERATE_ENUM(TP_MIPMAP_LOD14, 38) +END_ENUMTYPE(TP_PERFCOUNT_SELECT) + +START_ENUMTYPE(TCM_PERFCOUNT_SELECT) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_EMPTY, 0) + GENERATE_ENUM(reserved_01, 1) + GENERATE_ENUM(reserved_02, 2) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_4TH_FULL, 3) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_HALF_FULL, 4) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_FULL, 5) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_LT_4TH_FULL, 6) + GENERATE_ENUM(reserved_07, 7) + GENERATE_ENUM(reserved_08, 8) + GENERATE_ENUM(reserved_09, 9) + GENERATE_ENUM(reserved_10, 10) + GENERATE_ENUM(reserved_11, 11) + GENERATE_ENUM(reserved_12, 12) + GENERATE_ENUM(reserved_13, 13) + GENERATE_ENUM(reserved_14, 14) + GENERATE_ENUM(reserved_15, 15) + GENERATE_ENUM(reserved_16, 16) + GENERATE_ENUM(reserved_17, 17) + GENERATE_ENUM(reserved_18, 18) + GENERATE_ENUM(reserved_19, 19) + GENERATE_ENUM(reserved_20, 20) + GENERATE_ENUM(reserved_21, 21) + GENERATE_ENUM(reserved_22, 22) + GENERATE_ENUM(reserved_23, 23) + GENERATE_ENUM(reserved_24, 24) + GENERATE_ENUM(reserved_25, 25) + GENERATE_ENUM(reserved_26, 26) + GENERATE_ENUM(reserved_27, 27) + GENERATE_ENUM(READ_STARVED_QUAD0, 28) + GENERATE_ENUM(reserved_29, 29) + GENERATE_ENUM(reserved_30, 30) + GENERATE_ENUM(reserved_31, 31) + GENERATE_ENUM(READ_STARVED, 32) + GENERATE_ENUM(READ_STALLED_QUAD0, 33) + GENERATE_ENUM(reserved_34, 34) + GENERATE_ENUM(reserved_35, 35) + GENERATE_ENUM(reserved_36, 36) + GENERATE_ENUM(READ_STALLED, 37) + GENERATE_ENUM(VALID_READ_QUAD0, 38) + GENERATE_ENUM(reserved_39, 39) + GENERATE_ENUM(reserved_40, 40) + GENERATE_ENUM(reserved_41, 41) + GENERATE_ENUM(TC_TP_STARVED_QUAD0, 42) + GENERATE_ENUM(reserved_43, 43) + GENERATE_ENUM(reserved_44, 44) + GENERATE_ENUM(reserved_45, 45) + GENERATE_ENUM(TC_TP_STARVED, 46) +END_ENUMTYPE(TCM_PERFCOUNT_SELECT) + +START_ENUMTYPE(TCF_PERFCOUNT_SELECT) + GENERATE_ENUM(VALID_CYCLES, 0) + GENERATE_ENUM(SINGLE_PHASES, 1) + GENERATE_ENUM(ANISO_PHASES, 2) + GENERATE_ENUM(MIP_PHASES, 3) + GENERATE_ENUM(VOL_PHASES, 4) + GENERATE_ENUM(MIP_VOL_PHASES, 5) + GENERATE_ENUM(MIP_ANISO_PHASES, 6) + GENERATE_ENUM(VOL_ANISO_PHASES, 7) + GENERATE_ENUM(ANISO_2_1_PHASES, 8) + GENERATE_ENUM(ANISO_4_1_PHASES, 9) + GENERATE_ENUM(ANISO_6_1_PHASES, 10) + GENERATE_ENUM(ANISO_8_1_PHASES, 11) + GENERATE_ENUM(ANISO_10_1_PHASES, 12) + GENERATE_ENUM(ANISO_12_1_PHASES, 13) + GENERATE_ENUM(ANISO_14_1_PHASES, 14) + GENERATE_ENUM(ANISO_16_1_PHASES, 15) + GENERATE_ENUM(MIP_VOL_ANISO_PHASES, 16) + GENERATE_ENUM(ALIGN_2_PHASES, 17) + GENERATE_ENUM(ALIGN_4_PHASES, 18) + GENERATE_ENUM(TPC_BUSY, 19) + GENERATE_ENUM(TPC_STALLED, 20) + GENERATE_ENUM(TPC_STARVED, 21) + GENERATE_ENUM(TPC_WORKING, 22) + GENERATE_ENUM(TPC_WALKER_BUSY, 23) + GENERATE_ENUM(TPC_WALKER_STALLED, 24) + GENERATE_ENUM(TPC_WALKER_WORKING, 25) + GENERATE_ENUM(TPC_ALIGNER_BUSY, 26) + GENERATE_ENUM(TPC_ALIGNER_STALLED, 27) + GENERATE_ENUM(TPC_ALIGNER_STALLED_BY_BLEND, 28) + GENERATE_ENUM(TPC_ALIGNER_STALLED_BY_CACHE, 29) + GENERATE_ENUM(TPC_ALIGNER_WORKING, 30) + GENERATE_ENUM(TPC_BLEND_BUSY, 31) + GENERATE_ENUM(TPC_BLEND_SYNC, 32) + GENERATE_ENUM(TPC_BLEND_STARVED, 33) + GENERATE_ENUM(TPC_BLEND_WORKING, 34) + GENERATE_ENUM(OPCODE_0x00, 35) + GENERATE_ENUM(OPCODE_0x01, 36) + GENERATE_ENUM(OPCODE_0x04, 37) + GENERATE_ENUM(OPCODE_0x10, 38) + GENERATE_ENUM(OPCODE_0x11, 39) + GENERATE_ENUM(OPCODE_0x12, 40) + GENERATE_ENUM(OPCODE_0x13, 41) + GENERATE_ENUM(OPCODE_0x18, 42) + GENERATE_ENUM(OPCODE_0x19, 43) + GENERATE_ENUM(OPCODE_0x1A, 44) + GENERATE_ENUM(OPCODE_OTHER, 45) + GENERATE_ENUM(IN_FIFO_0_EMPTY, 56) + GENERATE_ENUM(IN_FIFO_0_LT_HALF_FULL, 57) + GENERATE_ENUM(IN_FIFO_0_HALF_FULL, 58) + GENERATE_ENUM(IN_FIFO_0_FULL, 59) + GENERATE_ENUM(IN_FIFO_TPC_EMPTY, 72) + GENERATE_ENUM(IN_FIFO_TPC_LT_HALF_FULL, 73) + GENERATE_ENUM(IN_FIFO_TPC_HALF_FULL, 74) + GENERATE_ENUM(IN_FIFO_TPC_FULL, 75) + GENERATE_ENUM(TPC_TC_XFC, 76) + GENERATE_ENUM(TPC_TC_STATE, 77) + GENERATE_ENUM(TC_STALL, 78) + GENERATE_ENUM(QUAD0_TAPS, 79) + GENERATE_ENUM(QUADS, 83) + GENERATE_ENUM(TCA_SYNC_STALL, 84) + GENERATE_ENUM(TAG_STALL, 85) + GENERATE_ENUM(TCB_SYNC_STALL, 88) + GENERATE_ENUM(TCA_VALID, 89) + GENERATE_ENUM(PROBES_VALID, 90) + GENERATE_ENUM(MISS_STALL, 91) + GENERATE_ENUM(FETCH_FIFO_STALL, 92) + GENERATE_ENUM(TCO_STALL, 93) + GENERATE_ENUM(ANY_STALL, 94) + GENERATE_ENUM(TAG_MISSES, 95) + GENERATE_ENUM(TAG_HITS, 96) + GENERATE_ENUM(SUB_TAG_MISSES, 97) + GENERATE_ENUM(SET0_INVALIDATES, 98) + GENERATE_ENUM(SET1_INVALIDATES, 99) + GENERATE_ENUM(SET2_INVALIDATES, 100) + GENERATE_ENUM(SET3_INVALIDATES, 101) + GENERATE_ENUM(SET0_TAG_MISSES, 102) + GENERATE_ENUM(SET1_TAG_MISSES, 103) + GENERATE_ENUM(SET2_TAG_MISSES, 104) + GENERATE_ENUM(SET3_TAG_MISSES, 105) + GENERATE_ENUM(SET0_TAG_HITS, 106) + GENERATE_ENUM(SET1_TAG_HITS, 107) + GENERATE_ENUM(SET2_TAG_HITS, 108) + GENERATE_ENUM(SET3_TAG_HITS, 109) + GENERATE_ENUM(SET0_SUB_TAG_MISSES, 110) + GENERATE_ENUM(SET1_SUB_TAG_MISSES, 111) + GENERATE_ENUM(SET2_SUB_TAG_MISSES, 112) + GENERATE_ENUM(SET3_SUB_TAG_MISSES, 113) + GENERATE_ENUM(SET0_EVICT1, 114) + GENERATE_ENUM(SET0_EVICT2, 115) + GENERATE_ENUM(SET0_EVICT3, 116) + GENERATE_ENUM(SET0_EVICT4, 117) + GENERATE_ENUM(SET0_EVICT5, 118) + GENERATE_ENUM(SET0_EVICT6, 119) + GENERATE_ENUM(SET0_EVICT7, 120) + GENERATE_ENUM(SET0_EVICT8, 121) + GENERATE_ENUM(SET1_EVICT1, 130) + GENERATE_ENUM(SET1_EVICT2, 131) + GENERATE_ENUM(SET1_EVICT3, 132) + GENERATE_ENUM(SET1_EVICT4, 133) + GENERATE_ENUM(SET1_EVICT5, 134) + GENERATE_ENUM(SET1_EVICT6, 135) + GENERATE_ENUM(SET1_EVICT7, 136) + GENERATE_ENUM(SET1_EVICT8, 137) + GENERATE_ENUM(SET2_EVICT1, 146) + GENERATE_ENUM(SET2_EVICT2, 147) + GENERATE_ENUM(SET2_EVICT3, 148) + GENERATE_ENUM(SET2_EVICT4, 149) + GENERATE_ENUM(SET2_EVICT5, 150) + GENERATE_ENUM(SET2_EVICT6, 151) + GENERATE_ENUM(SET2_EVICT7, 152) + GENERATE_ENUM(SET2_EVICT8, 153) + GENERATE_ENUM(SET3_EVICT1, 162) + GENERATE_ENUM(SET3_EVICT2, 163) + GENERATE_ENUM(SET3_EVICT3, 164) + GENERATE_ENUM(SET3_EVICT4, 165) + GENERATE_ENUM(SET3_EVICT5, 166) + GENERATE_ENUM(SET3_EVICT6, 167) + GENERATE_ENUM(SET3_EVICT7, 168) + GENERATE_ENUM(SET3_EVICT8, 169) + GENERATE_ENUM(FF_EMPTY, 178) + GENERATE_ENUM(FF_LT_HALF_FULL, 179) + GENERATE_ENUM(FF_HALF_FULL, 180) + GENERATE_ENUM(FF_FULL, 181) + GENERATE_ENUM(FF_XFC, 182) + GENERATE_ENUM(FF_STALLED, 183) + GENERATE_ENUM(FG_MASKS, 184) + GENERATE_ENUM(FG_LEFT_MASKS, 185) + GENERATE_ENUM(FG_LEFT_MASK_STALLED, 186) + GENERATE_ENUM(FG_LEFT_NOT_DONE_STALL, 187) + GENERATE_ENUM(FG_LEFT_FG_STALL, 188) + GENERATE_ENUM(FG_LEFT_SECTORS, 189) + GENERATE_ENUM(FG0_REQUESTS, 195) + GENERATE_ENUM(FG0_STALLED, 196) + GENERATE_ENUM(MEM_REQ512, 199) + GENERATE_ENUM(MEM_REQ_SENT, 200) + GENERATE_ENUM(MEM_LOCAL_READ_REQ, 202) + GENERATE_ENUM(TC0_MH_STALLED, 203) +END_ENUMTYPE(TCF_PERFCOUNT_SELECT) + +START_ENUMTYPE(SQ_PERFCNT_SELECT) + GENERATE_ENUM(SQ_PIXEL_VECTORS_SUB, 0) + GENERATE_ENUM(SQ_VERTEX_VECTORS_SUB, 1) + GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD0, 2) + GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD0, 3) + GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD0, 4) + GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD0, 5) + GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD1, 6) + GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD1, 7) + GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD1, 8) + GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD1, 9) + GENERATE_ENUM(SQ_EXPORT_CYCLES, 10) + GENERATE_ENUM(SQ_ALU_CST_WRITTEN, 11) + GENERATE_ENUM(SQ_TEX_CST_WRITTEN, 12) + GENERATE_ENUM(SQ_ALU_CST_STALL, 13) + GENERATE_ENUM(SQ_ALU_TEX_STALL, 14) + GENERATE_ENUM(SQ_INST_WRITTEN, 15) + GENERATE_ENUM(SQ_BOOLEAN_WRITTEN, 16) + GENERATE_ENUM(SQ_LOOPS_WRITTEN, 17) + GENERATE_ENUM(SQ_PIXEL_SWAP_IN, 18) + GENERATE_ENUM(SQ_PIXEL_SWAP_OUT, 19) + GENERATE_ENUM(SQ_VERTEX_SWAP_IN, 20) + GENERATE_ENUM(SQ_VERTEX_SWAP_OUT, 21) + GENERATE_ENUM(SQ_ALU_VTX_INST_ISSUED, 22) + GENERATE_ENUM(SQ_TEX_VTX_INST_ISSUED, 23) + GENERATE_ENUM(SQ_VC_VTX_INST_ISSUED, 24) + GENERATE_ENUM(SQ_CF_VTX_INST_ISSUED, 25) + GENERATE_ENUM(SQ_ALU_PIX_INST_ISSUED, 26) + GENERATE_ENUM(SQ_TEX_PIX_INST_ISSUED, 27) + GENERATE_ENUM(SQ_VC_PIX_INST_ISSUED, 28) + GENERATE_ENUM(SQ_CF_PIX_INST_ISSUED, 29) + GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD0, 30) + GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD0, 31) + GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD1, 32) + GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD1, 33) + GENERATE_ENUM(SQ_ALU_NOPS, 34) + GENERATE_ENUM(SQ_PRED_SKIP, 35) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD0_VTX, 36) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD1_VTX, 37) + GENERATE_ENUM(SQ_SYNC_TEX_STALL_VTX, 38) + GENERATE_ENUM(SQ_SYNC_VC_STALL_VTX, 39) + GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD0, 40) + GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD0, 41) + GENERATE_ENUM(SQ_GPR_STALL_VTX, 42) + GENERATE_ENUM(SQ_GPR_STALL_PIX, 43) + GENERATE_ENUM(SQ_VTX_RS_STALL, 44) + GENERATE_ENUM(SQ_PIX_RS_STALL, 45) + GENERATE_ENUM(SQ_SX_PC_FULL, 46) + GENERATE_ENUM(SQ_SX_EXP_BUFF_FULL, 47) + GENERATE_ENUM(SQ_SX_POS_BUFF_FULL, 48) + GENERATE_ENUM(SQ_INTERP_QUADS, 49) + GENERATE_ENUM(SQ_INTERP_ACTIVE, 50) + GENERATE_ENUM(SQ_IN_PIXEL_STALL, 51) + GENERATE_ENUM(SQ_IN_VTX_STALL, 52) + GENERATE_ENUM(SQ_VTX_CNT, 53) + GENERATE_ENUM(SQ_VTX_VECTOR2, 54) + GENERATE_ENUM(SQ_VTX_VECTOR3, 55) + GENERATE_ENUM(SQ_VTX_VECTOR4, 56) + GENERATE_ENUM(SQ_PIXEL_VECTOR1, 57) + GENERATE_ENUM(SQ_PIXEL_VECTOR23, 58) + GENERATE_ENUM(SQ_PIXEL_VECTOR4, 59) + GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD1, 60) + GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD1, 61) + GENERATE_ENUM(SQ_SX_MEM_EXP_FULL, 62) + GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD2, 63) + GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD2, 64) + GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD2, 65) + GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD2, 66) + GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD3, 67) + GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD3, 68) + GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD3, 69) + GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD3, 70) + GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD2, 71) + GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD2, 72) + GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD3, 73) + GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD3, 74) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD2_VTX, 75) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD3_VTX, 76) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD0_PIX, 77) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD1_PIX, 78) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD2_PIX, 79) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD3_PIX, 80) + GENERATE_ENUM(SQ_SYNC_TEX_STALL_PIX, 81) + GENERATE_ENUM(SQ_SYNC_VC_STALL_PIX, 82) + GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD2, 83) + GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD2, 84) + GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD3, 85) + GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD3, 86) + GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD0, 87) + GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD0, 88) + GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD1, 89) + GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD1, 90) + GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD2, 91) + GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD2, 92) + GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD3, 93) + GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD3, 94) + GENERATE_ENUM(VC_PERF_STATIC, 95) + GENERATE_ENUM(VC_PERF_STALLED, 96) + GENERATE_ENUM(VC_PERF_STARVED, 97) + GENERATE_ENUM(VC_PERF_SEND, 98) + GENERATE_ENUM(VC_PERF_ACTUAL_STARVED, 99) + GENERATE_ENUM(PIXEL_THREAD_0_ACTIVE, 100) + GENERATE_ENUM(VERTEX_THREAD_0_ACTIVE, 101) + GENERATE_ENUM(PIXEL_THREAD_0_NUMBER, 102) + GENERATE_ENUM(VERTEX_THREAD_0_NUMBER, 103) + GENERATE_ENUM(VERTEX_EVENT_NUMBER, 104) + GENERATE_ENUM(PIXEL_EVENT_NUMBER, 105) + GENERATE_ENUM(PTRBUFF_EF_PUSH, 106) + GENERATE_ENUM(PTRBUFF_EF_POP_EVENT, 107) + GENERATE_ENUM(PTRBUFF_EF_POP_NEW_VTX, 108) + GENERATE_ENUM(PTRBUFF_EF_POP_DEALLOC, 109) + GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR, 110) + GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR_X, 111) + GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR_VNZ, 112) + GENERATE_ENUM(PTRBUFF_PB_DEALLOC, 113) + GENERATE_ENUM(PTRBUFF_PI_STATE_PPB_POP, 114) + GENERATE_ENUM(PTRBUFF_PI_RTR, 115) + GENERATE_ENUM(PTRBUFF_PI_READ_EN, 116) + GENERATE_ENUM(PTRBUFF_PI_BUFF_SWAP, 117) + GENERATE_ENUM(PTRBUFF_SQ_FREE_BUFF, 118) + GENERATE_ENUM(PTRBUFF_SQ_DEC, 119) + GENERATE_ENUM(PTRBUFF_SC_VALID_CNTL_EVENT, 120) + GENERATE_ENUM(PTRBUFF_SC_VALID_IJ_XFER, 121) + GENERATE_ENUM(PTRBUFF_SC_NEW_VECTOR_1_Q, 122) + GENERATE_ENUM(PTRBUFF_QUAL_NEW_VECTOR, 123) + GENERATE_ENUM(PTRBUFF_QUAL_EVENT, 124) + GENERATE_ENUM(PTRBUFF_END_BUFFER, 125) + GENERATE_ENUM(PTRBUFF_FILL_QUAD, 126) + GENERATE_ENUM(VERTS_WRITTEN_SPI, 127) + GENERATE_ENUM(TP_FETCH_INSTR_EXEC, 128) + GENERATE_ENUM(TP_FETCH_INSTR_REQ, 129) + GENERATE_ENUM(TP_DATA_RETURN, 130) + GENERATE_ENUM(SPI_WRITE_CYCLES_SP, 131) + GENERATE_ENUM(SPI_WRITES_SP, 132) + GENERATE_ENUM(SP_ALU_INSTR_EXEC, 133) + GENERATE_ENUM(SP_CONST_ADDR_TO_SQ, 134) + GENERATE_ENUM(SP_PRED_KILLS_TO_SQ, 135) + GENERATE_ENUM(SP_EXPORT_CYCLES_TO_SX, 136) + GENERATE_ENUM(SP_EXPORTS_TO_SX, 137) + GENERATE_ENUM(SQ_CYCLES_ELAPSED, 138) + GENERATE_ENUM(SQ_TCFS_OPT_ALLOC_EXEC, 139) + GENERATE_ENUM(SQ_TCFS_NO_OPT_ALLOC, 140) + GENERATE_ENUM(SQ_ALU0_NO_OPT_ALLOC, 141) + GENERATE_ENUM(SQ_ALU1_NO_OPT_ALLOC, 142) + GENERATE_ENUM(SQ_TCFS_ARB_XFC_CNT, 143) + GENERATE_ENUM(SQ_ALU0_ARB_XFC_CNT, 144) + GENERATE_ENUM(SQ_ALU1_ARB_XFC_CNT, 145) + GENERATE_ENUM(SQ_TCFS_CFS_UPDATE_CNT, 146) + GENERATE_ENUM(SQ_ALU0_CFS_UPDATE_CNT, 147) + GENERATE_ENUM(SQ_ALU1_CFS_UPDATE_CNT, 148) + GENERATE_ENUM(SQ_VTX_PUSH_THREAD_CNT, 149) + GENERATE_ENUM(SQ_VTX_POP_THREAD_CNT, 150) + GENERATE_ENUM(SQ_PIX_PUSH_THREAD_CNT, 151) + GENERATE_ENUM(SQ_PIX_POP_THREAD_CNT, 152) + GENERATE_ENUM(SQ_PIX_TOTAL, 153) + GENERATE_ENUM(SQ_PIX_KILLED, 154) +END_ENUMTYPE(SQ_PERFCNT_SELECT) + +START_ENUMTYPE(SX_PERFCNT_SELECT) + GENERATE_ENUM(SX_EXPORT_VECTORS, 0) + GENERATE_ENUM(SX_DUMMY_QUADS, 1) + GENERATE_ENUM(SX_ALPHA_FAIL, 2) + GENERATE_ENUM(SX_RB_QUAD_BUSY, 3) + GENERATE_ENUM(SX_RB_COLOR_BUSY, 4) + GENERATE_ENUM(SX_RB_QUAD_STALL, 5) + GENERATE_ENUM(SX_RB_COLOR_STALL, 6) +END_ENUMTYPE(SX_PERFCNT_SELECT) + +START_ENUMTYPE(Abs_modifier) + GENERATE_ENUM(NO_ABS_MOD, 0) + GENERATE_ENUM(ABS_MOD, 1) +END_ENUMTYPE(Abs_modifier) + +START_ENUMTYPE(Exporting) + GENERATE_ENUM(NOT_EXPORTING, 0) + GENERATE_ENUM(EXPORTING, 1) +END_ENUMTYPE(Exporting) + +START_ENUMTYPE(ScalarOpcode) + GENERATE_ENUM(ADDs, 0) + GENERATE_ENUM(ADD_PREVs, 1) + GENERATE_ENUM(MULs, 2) + GENERATE_ENUM(MUL_PREVs, 3) + GENERATE_ENUM(MUL_PREV2s, 4) + GENERATE_ENUM(MAXs, 5) + GENERATE_ENUM(MINs, 6) + GENERATE_ENUM(SETEs, 7) + GENERATE_ENUM(SETGTs, 8) + GENERATE_ENUM(SETGTEs, 9) + GENERATE_ENUM(SETNEs, 10) + GENERATE_ENUM(FRACs, 11) + GENERATE_ENUM(TRUNCs, 12) + GENERATE_ENUM(FLOORs, 13) + GENERATE_ENUM(EXP_IEEE, 14) + GENERATE_ENUM(LOG_CLAMP, 15) + GENERATE_ENUM(LOG_IEEE, 16) + GENERATE_ENUM(RECIP_CLAMP, 17) + GENERATE_ENUM(RECIP_FF, 18) + GENERATE_ENUM(RECIP_IEEE, 19) + GENERATE_ENUM(RECIPSQ_CLAMP, 20) + GENERATE_ENUM(RECIPSQ_FF, 21) + GENERATE_ENUM(RECIPSQ_IEEE, 22) + GENERATE_ENUM(MOVAs, 23) + GENERATE_ENUM(MOVA_FLOORs, 24) + GENERATE_ENUM(SUBs, 25) + GENERATE_ENUM(SUB_PREVs, 26) + GENERATE_ENUM(PRED_SETEs, 27) + GENERATE_ENUM(PRED_SETNEs, 28) + GENERATE_ENUM(PRED_SETGTs, 29) + GENERATE_ENUM(PRED_SETGTEs, 30) + GENERATE_ENUM(PRED_SET_INVs, 31) + GENERATE_ENUM(PRED_SET_POPs, 32) + GENERATE_ENUM(PRED_SET_CLRs, 33) + GENERATE_ENUM(PRED_SET_RESTOREs, 34) + GENERATE_ENUM(KILLEs, 35) + GENERATE_ENUM(KILLGTs, 36) + GENERATE_ENUM(KILLGTEs, 37) + GENERATE_ENUM(KILLNEs, 38) + GENERATE_ENUM(KILLONEs, 39) + GENERATE_ENUM(SQRT_IEEE, 40) + GENERATE_ENUM(MUL_CONST_0, 42) + GENERATE_ENUM(MUL_CONST_1, 43) + GENERATE_ENUM(ADD_CONST_0, 44) + GENERATE_ENUM(ADD_CONST_1, 45) + GENERATE_ENUM(SUB_CONST_0, 46) + GENERATE_ENUM(SUB_CONST_1, 47) + GENERATE_ENUM(SIN, 48) + GENERATE_ENUM(COS, 49) + GENERATE_ENUM(RETAIN_PREV, 50) +END_ENUMTYPE(ScalarOpcode) + +START_ENUMTYPE(SwizzleType) + GENERATE_ENUM(NO_SWIZZLE, 0) + GENERATE_ENUM(SHIFT_RIGHT_1, 1) + GENERATE_ENUM(SHIFT_RIGHT_2, 2) + GENERATE_ENUM(SHIFT_RIGHT_3, 3) +END_ENUMTYPE(SwizzleType) + +START_ENUMTYPE(InputModifier) + GENERATE_ENUM(NIL, 0) + GENERATE_ENUM(NEGATE, 1) +END_ENUMTYPE(InputModifier) + +START_ENUMTYPE(PredicateSelect) + GENERATE_ENUM(NO_PREDICATION, 0) + GENERATE_ENUM(PREDICATE_QUAD, 1) + GENERATE_ENUM(PREDICATED_2, 2) + GENERATE_ENUM(PREDICATED_3, 3) +END_ENUMTYPE(PredicateSelect) + +START_ENUMTYPE(OperandSelect1) + GENERATE_ENUM(ABSOLUTE_REG, 0) + GENERATE_ENUM(RELATIVE_REG, 1) +END_ENUMTYPE(OperandSelect1) + +START_ENUMTYPE(VectorOpcode) + GENERATE_ENUM(ADDv, 0) + GENERATE_ENUM(MULv, 1) + GENERATE_ENUM(MAXv, 2) + GENERATE_ENUM(MINv, 3) + GENERATE_ENUM(SETEv, 4) + GENERATE_ENUM(SETGTv, 5) + GENERATE_ENUM(SETGTEv, 6) + GENERATE_ENUM(SETNEv, 7) + GENERATE_ENUM(FRACv, 8) + GENERATE_ENUM(TRUNCv, 9) + GENERATE_ENUM(FLOORv, 10) + GENERATE_ENUM(MULADDv, 11) + GENERATE_ENUM(CNDEv, 12) + GENERATE_ENUM(CNDGTEv, 13) + GENERATE_ENUM(CNDGTv, 14) + GENERATE_ENUM(DOT4v, 15) + GENERATE_ENUM(DOT3v, 16) + GENERATE_ENUM(DOT2ADDv, 17) + GENERATE_ENUM(CUBEv, 18) + GENERATE_ENUM(MAX4v, 19) + GENERATE_ENUM(PRED_SETE_PUSHv, 20) + GENERATE_ENUM(PRED_SETNE_PUSHv, 21) + GENERATE_ENUM(PRED_SETGT_PUSHv, 22) + GENERATE_ENUM(PRED_SETGTE_PUSHv, 23) + GENERATE_ENUM(KILLEv, 24) + GENERATE_ENUM(KILLGTv, 25) + GENERATE_ENUM(KILLGTEv, 26) + GENERATE_ENUM(KILLNEv, 27) + GENERATE_ENUM(DSTv, 28) + GENERATE_ENUM(MOVAv, 29) +END_ENUMTYPE(VectorOpcode) + +START_ENUMTYPE(OperandSelect0) + GENERATE_ENUM(CONSTANT, 0) + GENERATE_ENUM(NON_CONSTANT, 1) +END_ENUMTYPE(OperandSelect0) + +START_ENUMTYPE(Ressource_type) + GENERATE_ENUM(ALU, 0) + GENERATE_ENUM(TEXTURE, 1) +END_ENUMTYPE(Ressource_type) + +START_ENUMTYPE(Instruction_serial) + GENERATE_ENUM(NOT_SERIAL, 0) + GENERATE_ENUM(SERIAL, 1) +END_ENUMTYPE(Instruction_serial) + +START_ENUMTYPE(VC_type) + GENERATE_ENUM(ALU_TP_REQUEST, 0) + GENERATE_ENUM(VC_REQUEST, 1) +END_ENUMTYPE(VC_type) + +START_ENUMTYPE(Addressing) + GENERATE_ENUM(RELATIVE_ADDR, 0) + GENERATE_ENUM(ABSOLUTE_ADDR, 1) +END_ENUMTYPE(Addressing) + +START_ENUMTYPE(CFOpcode) + GENERATE_ENUM(NOP, 0) + GENERATE_ENUM(EXECUTE, 1) + GENERATE_ENUM(EXECUTE_END, 2) + GENERATE_ENUM(COND_EXECUTE, 3) + GENERATE_ENUM(COND_EXECUTE_END, 4) + GENERATE_ENUM(COND_PRED_EXECUTE, 5) + GENERATE_ENUM(COND_PRED_EXECUTE_END, 6) + GENERATE_ENUM(LOOP_START, 7) + GENERATE_ENUM(LOOP_END, 8) + GENERATE_ENUM(COND_CALL, 9) + GENERATE_ENUM(RETURN, 10) + GENERATE_ENUM(COND_JMP, 11) + GENERATE_ENUM(ALLOCATE, 12) + GENERATE_ENUM(COND_EXECUTE_PRED_CLEAN, 13) + GENERATE_ENUM(COND_EXECUTE_PRED_CLEAN_END, 14) + GENERATE_ENUM(MARK_VS_FETCH_DONE, 15) +END_ENUMTYPE(CFOpcode) + +START_ENUMTYPE(Allocation_type) + GENERATE_ENUM(SQ_NO_ALLOC, 0) + GENERATE_ENUM(SQ_POSITION, 1) + GENERATE_ENUM(SQ_PARAMETER_PIXEL, 2) + GENERATE_ENUM(SQ_MEMORY, 3) +END_ENUMTYPE(Allocation_type) + +START_ENUMTYPE(TexInstOpcode) + GENERATE_ENUM(TEX_INST_FETCH, 1) + GENERATE_ENUM(TEX_INST_RESERVED_1, 2) + GENERATE_ENUM(TEX_INST_RESERVED_2, 3) + GENERATE_ENUM(TEX_INST_RESERVED_3, 4) + GENERATE_ENUM(TEX_INST_GET_BORDER_COLOR_FRAC, 16) + GENERATE_ENUM(TEX_INST_GET_COMP_TEX_LOD, 17) + GENERATE_ENUM(TEX_INST_GET_GRADIENTS, 18) + GENERATE_ENUM(TEX_INST_GET_WEIGHTS, 19) + GENERATE_ENUM(TEX_INST_SET_TEX_LOD, 24) + GENERATE_ENUM(TEX_INST_SET_GRADIENTS_H, 25) + GENERATE_ENUM(TEX_INST_SET_GRADIENTS_V, 26) + GENERATE_ENUM(TEX_INST_RESERVED_4, 27) +END_ENUMTYPE(TexInstOpcode) + +START_ENUMTYPE(Addressmode) + GENERATE_ENUM(LOGICAL, 0) + GENERATE_ENUM(LOOP_RELATIVE, 1) +END_ENUMTYPE(Addressmode) + +START_ENUMTYPE(TexCoordDenorm) + GENERATE_ENUM(TEX_COORD_NORMALIZED, 0) + GENERATE_ENUM(TEX_COORD_UNNORMALIZED, 1) +END_ENUMTYPE(TexCoordDenorm) + +START_ENUMTYPE(SrcSel) + GENERATE_ENUM(SRC_SEL_X, 0) + GENERATE_ENUM(SRC_SEL_Y, 1) + GENERATE_ENUM(SRC_SEL_Z, 2) + GENERATE_ENUM(SRC_SEL_W, 3) +END_ENUMTYPE(SrcSel) + +START_ENUMTYPE(DstSel) + GENERATE_ENUM(DST_SEL_X, 0) + GENERATE_ENUM(DST_SEL_Y, 1) + GENERATE_ENUM(DST_SEL_Z, 2) + GENERATE_ENUM(DST_SEL_W, 3) + GENERATE_ENUM(DST_SEL_0, 4) + GENERATE_ENUM(DST_SEL_1, 5) + GENERATE_ENUM(DST_SEL_RSVD, 6) + GENERATE_ENUM(DST_SEL_MASK, 7) +END_ENUMTYPE(DstSel) + +START_ENUMTYPE(MagFilter) + GENERATE_ENUM(MAG_FILTER_POINT, 0) + GENERATE_ENUM(MAG_FILTER_LINEAR, 1) + GENERATE_ENUM(MAG_FILTER_RESERVED_0, 2) + GENERATE_ENUM(MAG_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(MagFilter) + +START_ENUMTYPE(MinFilter) + GENERATE_ENUM(MIN_FILTER_POINT, 0) + GENERATE_ENUM(MIN_FILTER_LINEAR, 1) + GENERATE_ENUM(MIN_FILTER_RESERVED_0, 2) + GENERATE_ENUM(MIN_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(MinFilter) + +START_ENUMTYPE(MipFilter) + GENERATE_ENUM(MIP_FILTER_POINT, 0) + GENERATE_ENUM(MIP_FILTER_LINEAR, 1) + GENERATE_ENUM(MIP_FILTER_BASEMAP, 2) + GENERATE_ENUM(MIP_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(MipFilter) + +START_ENUMTYPE(AnisoFilter) + GENERATE_ENUM(ANISO_FILTER_DISABLED, 0) + GENERATE_ENUM(ANISO_FILTER_MAX_1_1, 1) + GENERATE_ENUM(ANISO_FILTER_MAX_2_1, 2) + GENERATE_ENUM(ANISO_FILTER_MAX_4_1, 3) + GENERATE_ENUM(ANISO_FILTER_MAX_8_1, 4) + GENERATE_ENUM(ANISO_FILTER_MAX_16_1, 5) + GENERATE_ENUM(ANISO_FILTER_USE_FETCH_CONST, 7) +END_ENUMTYPE(AnisoFilter) + +START_ENUMTYPE(ArbitraryFilter) + GENERATE_ENUM(ARBITRARY_FILTER_2X4_SYM, 0) + GENERATE_ENUM(ARBITRARY_FILTER_2X4_ASYM, 1) + GENERATE_ENUM(ARBITRARY_FILTER_4X2_SYM, 2) + GENERATE_ENUM(ARBITRARY_FILTER_4X2_ASYM, 3) + GENERATE_ENUM(ARBITRARY_FILTER_4X4_SYM, 4) + GENERATE_ENUM(ARBITRARY_FILTER_4X4_ASYM, 5) + GENERATE_ENUM(ARBITRARY_FILTER_USE_FETCH_CONST, 7) +END_ENUMTYPE(ArbitraryFilter) + +START_ENUMTYPE(VolMagFilter) + GENERATE_ENUM(VOL_MAG_FILTER_POINT, 0) + GENERATE_ENUM(VOL_MAG_FILTER_LINEAR, 1) + GENERATE_ENUM(VOL_MAG_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(VolMagFilter) + +START_ENUMTYPE(VolMinFilter) + GENERATE_ENUM(VOL_MIN_FILTER_POINT, 0) + GENERATE_ENUM(VOL_MIN_FILTER_LINEAR, 1) + GENERATE_ENUM(VOL_MIN_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(VolMinFilter) + +START_ENUMTYPE(PredSelect) + GENERATE_ENUM(NOT_PREDICATED, 0) + GENERATE_ENUM(PREDICATED, 1) +END_ENUMTYPE(PredSelect) + +START_ENUMTYPE(SampleLocation) + GENERATE_ENUM(SAMPLE_CENTROID, 0) + GENERATE_ENUM(SAMPLE_CENTER, 1) +END_ENUMTYPE(SampleLocation) + +START_ENUMTYPE(VertexMode) + GENERATE_ENUM(POSITION_1_VECTOR, 0) + GENERATE_ENUM(POSITION_2_VECTORS_UNUSED, 1) + GENERATE_ENUM(POSITION_2_VECTORS_SPRITE, 2) + GENERATE_ENUM(POSITION_2_VECTORS_EDGE, 3) + GENERATE_ENUM(POSITION_2_VECTORS_KILL, 4) + GENERATE_ENUM(POSITION_2_VECTORS_SPRITE_KILL, 5) + GENERATE_ENUM(POSITION_2_VECTORS_EDGE_KILL, 6) + GENERATE_ENUM(MULTIPASS, 7) +END_ENUMTYPE(VertexMode) + +START_ENUMTYPE(Sample_Cntl) + GENERATE_ENUM(CENTROIDS_ONLY, 0) + GENERATE_ENUM(CENTERS_ONLY, 1) + GENERATE_ENUM(CENTROIDS_AND_CENTERS, 2) + GENERATE_ENUM(UNDEF, 3) +END_ENUMTYPE(Sample_Cntl) + +START_ENUMTYPE(MhPerfEncode) + GENERATE_ENUM(CP_R0_REQUESTS, 0) + GENERATE_ENUM(CP_R1_REQUESTS, 1) + GENERATE_ENUM(CP_R2_REQUESTS, 2) + GENERATE_ENUM(CP_R3_REQUESTS, 3) + GENERATE_ENUM(CP_R4_REQUESTS, 4) + GENERATE_ENUM(CP_TOTAL_READ_REQUESTS, 5) + GENERATE_ENUM(CP_W_REQUESTS, 6) + GENERATE_ENUM(CP_TOTAL_REQUESTS, 7) + GENERATE_ENUM(CP_DATA_BYTES_WRITTEN, 8) + GENERATE_ENUM(CP_WRITE_CLEAN_RESPONSES, 9) + GENERATE_ENUM(CP_R0_READ_BURSTS_RECEIVED, 10) + GENERATE_ENUM(CP_R1_READ_BURSTS_RECEIVED, 11) + GENERATE_ENUM(CP_R2_READ_BURSTS_RECEIVED, 12) + GENERATE_ENUM(CP_R3_READ_BURSTS_RECEIVED, 13) + GENERATE_ENUM(CP_R4_READ_BURSTS_RECEIVED, 14) + GENERATE_ENUM(CP_TOTAL_READ_BURSTS_RECEIVED, 15) + GENERATE_ENUM(CP_R0_DATA_BEATS_READ, 16) + GENERATE_ENUM(CP_R1_DATA_BEATS_READ, 17) + GENERATE_ENUM(CP_R2_DATA_BEATS_READ, 18) + GENERATE_ENUM(CP_R3_DATA_BEATS_READ, 19) + GENERATE_ENUM(CP_R4_DATA_BEATS_READ, 20) + GENERATE_ENUM(CP_TOTAL_DATA_BEATS_READ, 21) + GENERATE_ENUM(VGT_R0_REQUESTS, 22) + GENERATE_ENUM(VGT_R1_REQUESTS, 23) + GENERATE_ENUM(VGT_TOTAL_REQUESTS, 24) + GENERATE_ENUM(VGT_R0_READ_BURSTS_RECEIVED, 25) + GENERATE_ENUM(VGT_R1_READ_BURSTS_RECEIVED, 26) + GENERATE_ENUM(VGT_TOTAL_READ_BURSTS_RECEIVED, 27) + GENERATE_ENUM(VGT_R0_DATA_BEATS_READ, 28) + GENERATE_ENUM(VGT_R1_DATA_BEATS_READ, 29) + GENERATE_ENUM(VGT_TOTAL_DATA_BEATS_READ, 30) + GENERATE_ENUM(TC_REQUESTS, 31) + GENERATE_ENUM(TC_ROQ_REQUESTS, 32) + GENERATE_ENUM(TC_INFO_SENT, 33) + GENERATE_ENUM(TC_READ_BURSTS_RECEIVED, 34) + GENERATE_ENUM(TC_DATA_BEATS_READ, 35) + GENERATE_ENUM(TCD_BURSTS_READ, 36) + GENERATE_ENUM(RB_REQUESTS, 37) + GENERATE_ENUM(RB_DATA_BYTES_WRITTEN, 38) + GENERATE_ENUM(RB_WRITE_CLEAN_RESPONSES, 39) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_0, 40) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_1, 41) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_2, 42) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_3, 43) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_4, 44) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_5, 45) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_6, 46) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_7, 47) + GENERATE_ENUM(AXI_TOTAL_READ_REQUESTS, 48) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_0, 49) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_1, 50) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_2, 51) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_3, 52) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_4, 53) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_5, 54) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_6, 55) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_7, 56) + GENERATE_ENUM(AXI_TOTAL_WRITE_REQUESTS, 57) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_0, 58) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_1, 59) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_2, 60) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_3, 61) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_4, 62) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_5, 63) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_6, 64) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_7, 65) + GENERATE_ENUM(AXI_TOTAL_REQUESTS, 66) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_0, 67) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_1, 68) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_2, 69) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_3, 70) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_4, 71) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_5, 72) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_6, 73) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_7, 74) + GENERATE_ENUM(AXI_READ_CHANNEL_TOTAL_BURSTS, 75) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0, 76) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1, 77) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2, 78) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3, 79) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4, 80) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5, 81) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6, 82) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7, 83) + GENERATE_ENUM(AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ, 84) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_0, 85) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_1, 86) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_2, 87) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_3, 88) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_4, 89) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_5, 90) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_6, 91) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_7, 92) + GENERATE_ENUM(AXI_WRITE_CHANNEL_TOTAL_BURSTS, 93) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0, 94) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1, 95) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2, 96) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3, 97) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4, 98) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5, 99) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6, 100) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7, 101) + GENERATE_ENUM(AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN, 102) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0, 103) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1, 104) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2, 105) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3, 106) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4, 107) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5, 108) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6, 109) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7, 110) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES, 111) + GENERATE_ENUM(TOTAL_MMU_MISSES, 112) + GENERATE_ENUM(MMU_READ_MISSES, 113) + GENERATE_ENUM(MMU_WRITE_MISSES, 114) + GENERATE_ENUM(TOTAL_MMU_HITS, 115) + GENERATE_ENUM(MMU_READ_HITS, 116) + GENERATE_ENUM(MMU_WRITE_HITS, 117) + GENERATE_ENUM(SPLIT_MODE_TC_HITS, 118) + GENERATE_ENUM(SPLIT_MODE_TC_MISSES, 119) + GENERATE_ENUM(SPLIT_MODE_NON_TC_HITS, 120) + GENERATE_ENUM(SPLIT_MODE_NON_TC_MISSES, 121) + GENERATE_ENUM(STALL_AWAITING_TLB_MISS_FETCH, 122) + GENERATE_ENUM(MMU_TLB_MISS_READ_BURSTS_RECEIVED, 123) + GENERATE_ENUM(MMU_TLB_MISS_DATA_BEATS_READ, 124) + GENERATE_ENUM(CP_CYCLES_HELD_OFF, 125) + GENERATE_ENUM(VGT_CYCLES_HELD_OFF, 126) + GENERATE_ENUM(TC_CYCLES_HELD_OFF, 127) + GENERATE_ENUM(TC_ROQ_CYCLES_HELD_OFF, 128) + GENERATE_ENUM(TC_CYCLES_HELD_OFF_TCD_FULL, 129) + GENERATE_ENUM(RB_CYCLES_HELD_OFF, 130) + GENERATE_ENUM(TOTAL_CYCLES_ANY_CLNT_HELD_OFF, 131) + GENERATE_ENUM(TLB_MISS_CYCLES_HELD_OFF, 132) + GENERATE_ENUM(AXI_READ_REQUEST_HELD_OFF, 133) + GENERATE_ENUM(AXI_WRITE_REQUEST_HELD_OFF, 134) + GENERATE_ENUM(AXI_REQUEST_HELD_OFF, 135) + GENERATE_ENUM(AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT, 136) + GENERATE_ENUM(AXI_WRITE_DATA_HELD_OFF, 137) + GENERATE_ENUM(CP_SAME_PAGE_BANK_REQUESTS, 138) + GENERATE_ENUM(VGT_SAME_PAGE_BANK_REQUESTS, 139) + GENERATE_ENUM(TC_SAME_PAGE_BANK_REQUESTS, 140) + GENERATE_ENUM(TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS, 141) + GENERATE_ENUM(RB_SAME_PAGE_BANK_REQUESTS, 142) + GENERATE_ENUM(TOTAL_SAME_PAGE_BANK_REQUESTS, 143) + GENERATE_ENUM(CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 144) + GENERATE_ENUM(VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 145) + GENERATE_ENUM(TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 146) + GENERATE_ENUM(RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 147) + GENERATE_ENUM(TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT, 148) + GENERATE_ENUM(TOTAL_MH_READ_REQUESTS, 149) + GENERATE_ENUM(TOTAL_MH_WRITE_REQUESTS, 150) + GENERATE_ENUM(TOTAL_MH_REQUESTS, 151) + GENERATE_ENUM(MH_BUSY, 152) + GENERATE_ENUM(CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 153) + GENERATE_ENUM(VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 154) + GENERATE_ENUM(TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 155) + GENERATE_ENUM(RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 156) + GENERATE_ENUM(TC_ROQ_N_VALID_ENTRIES, 157) + GENERATE_ENUM(ARQ_N_ENTRIES, 158) + GENERATE_ENUM(WDB_N_ENTRIES, 159) + GENERATE_ENUM(MH_READ_LATENCY_OUTST_REQ_SUM, 160) + GENERATE_ENUM(MC_READ_LATENCY_OUTST_REQ_SUM, 161) + GENERATE_ENUM(MC_TOTAL_READ_REQUESTS, 162) + GENERATE_ENUM(ELAPSED_CYCLES_MH_GATED_CLK, 163) +END_ENUMTYPE(MhPerfEncode) + +START_ENUMTYPE(MmuClntBeh) + GENERATE_ENUM(BEH_NEVR, 0) + GENERATE_ENUM(BEH_TRAN_RNG, 1) + GENERATE_ENUM(BEH_TRAN_FLT, 2) +END_ENUMTYPE(MmuClntBeh) + +START_ENUMTYPE(RBBM_PERFCOUNT1_SEL) + GENERATE_ENUM(RBBM1_COUNT, 0) + GENERATE_ENUM(RBBM1_NRT_BUSY, 1) + GENERATE_ENUM(RBBM1_RB_BUSY, 2) + GENERATE_ENUM(RBBM1_SQ_CNTX0_BUSY, 3) + GENERATE_ENUM(RBBM1_SQ_CNTX17_BUSY, 4) + GENERATE_ENUM(RBBM1_VGT_BUSY, 5) + GENERATE_ENUM(RBBM1_VGT_NODMA_BUSY, 6) + GENERATE_ENUM(RBBM1_PA_BUSY, 7) + GENERATE_ENUM(RBBM1_SC_CNTX_BUSY, 8) + GENERATE_ENUM(RBBM1_TPC_BUSY, 9) + GENERATE_ENUM(RBBM1_TC_BUSY, 10) + GENERATE_ENUM(RBBM1_SX_BUSY, 11) + GENERATE_ENUM(RBBM1_CP_COHER_BUSY, 12) + GENERATE_ENUM(RBBM1_CP_NRT_BUSY, 13) + GENERATE_ENUM(RBBM1_GFX_IDLE_STALL, 14) + GENERATE_ENUM(RBBM1_INTERRUPT, 15) +END_ENUMTYPE(RBBM_PERFCOUNT1_SEL) + +START_ENUMTYPE(CP_PERFCOUNT_SEL) + GENERATE_ENUM(ALWAYS_COUNT, 0) + GENERATE_ENUM(TRANS_FIFO_FULL, 1) + GENERATE_ENUM(TRANS_FIFO_AF, 2) + GENERATE_ENUM(RCIU_PFPTRANS_WAIT, 3) + GENERATE_ENUM(Reserved_04, 4) + GENERATE_ENUM(Reserved_05, 5) + GENERATE_ENUM(RCIU_NRTTRANS_WAIT, 6) + GENERATE_ENUM(Reserved_07, 7) + GENERATE_ENUM(CSF_NRT_READ_WAIT, 8) + GENERATE_ENUM(CSF_I1_FIFO_FULL, 9) + GENERATE_ENUM(CSF_I2_FIFO_FULL, 10) + GENERATE_ENUM(CSF_ST_FIFO_FULL, 11) + GENERATE_ENUM(Reserved_12, 12) + GENERATE_ENUM(CSF_RING_ROQ_FULL, 13) + GENERATE_ENUM(CSF_I1_ROQ_FULL, 14) + GENERATE_ENUM(CSF_I2_ROQ_FULL, 15) + GENERATE_ENUM(CSF_ST_ROQ_FULL, 16) + GENERATE_ENUM(Reserved_17, 17) + GENERATE_ENUM(MIU_TAG_MEM_FULL, 18) + GENERATE_ENUM(MIU_WRITECLEAN, 19) + GENERATE_ENUM(Reserved_20, 20) + GENERATE_ENUM(Reserved_21, 21) + GENERATE_ENUM(MIU_NRT_WRITE_STALLED, 22) + GENERATE_ENUM(MIU_NRT_READ_STALLED, 23) + GENERATE_ENUM(ME_WRITE_CONFIRM_FIFO_FULL, 24) + GENERATE_ENUM(ME_VS_DEALLOC_FIFO_FULL, 25) + GENERATE_ENUM(ME_PS_DEALLOC_FIFO_FULL, 26) + GENERATE_ENUM(ME_REGS_VS_EVENT_FIFO_FULL, 27) + GENERATE_ENUM(ME_REGS_PS_EVENT_FIFO_FULL, 28) + GENERATE_ENUM(ME_REGS_CF_EVENT_FIFO_FULL, 29) + GENERATE_ENUM(ME_MICRO_RB_STARVED, 30) + GENERATE_ENUM(ME_MICRO_I1_STARVED, 31) + GENERATE_ENUM(ME_MICRO_I2_STARVED, 32) + GENERATE_ENUM(ME_MICRO_ST_STARVED, 33) + GENERATE_ENUM(Reserved_34, 34) + GENERATE_ENUM(Reserved_35, 35) + GENERATE_ENUM(Reserved_36, 36) + GENERATE_ENUM(Reserved_37, 37) + GENERATE_ENUM(Reserved_38, 38) + GENERATE_ENUM(Reserved_39, 39) + GENERATE_ENUM(RCIU_RBBM_DWORD_SENT, 40) + GENERATE_ENUM(ME_BUSY_CLOCKS, 41) + GENERATE_ENUM(ME_WAIT_CONTEXT_AVAIL, 42) + GENERATE_ENUM(PFP_TYPE0_PACKET, 43) + GENERATE_ENUM(PFP_TYPE3_PACKET, 44) + GENERATE_ENUM(CSF_RB_WPTR_NEQ_RPTR, 45) + GENERATE_ENUM(CSF_I1_SIZE_NEQ_ZERO, 46) + GENERATE_ENUM(CSF_I2_SIZE_NEQ_ZERO, 47) + GENERATE_ENUM(CSF_RBI1I2_FETCHING, 48) + GENERATE_ENUM(Reserved_49, 49) + GENERATE_ENUM(Reserved_50, 50) + GENERATE_ENUM(Reserved_51, 51) + GENERATE_ENUM(Reserved_52, 52) + GENERATE_ENUM(Reserved_53, 53) + GENERATE_ENUM(Reserved_54, 54) + GENERATE_ENUM(Reserved_55, 55) + GENERATE_ENUM(Reserved_56, 56) + GENERATE_ENUM(Reserved_57, 57) + GENERATE_ENUM(Reserved_58, 58) + GENERATE_ENUM(Reserved_59, 59) + GENERATE_ENUM(Reserved_60, 60) + GENERATE_ENUM(Reserved_61, 61) + GENERATE_ENUM(Reserved_62, 62) + GENERATE_ENUM(Reserved_63, 63) +END_ENUMTYPE(CP_PERFCOUNT_SEL) + +START_ENUMTYPE(ColorformatX) + GENERATE_ENUM(COLORX_4_4_4_4, 0) + GENERATE_ENUM(COLORX_1_5_5_5, 1) + GENERATE_ENUM(COLORX_5_6_5, 2) + GENERATE_ENUM(COLORX_8, 3) + GENERATE_ENUM(COLORX_8_8, 4) + GENERATE_ENUM(COLORX_8_8_8_8, 5) + GENERATE_ENUM(COLORX_S8_8_8_8, 6) + GENERATE_ENUM(COLORX_16_FLOAT, 7) + GENERATE_ENUM(COLORX_16_16_FLOAT, 8) + GENERATE_ENUM(COLORX_16_16_16_16_FLOAT, 9) + GENERATE_ENUM(COLORX_32_FLOAT, 10) + GENERATE_ENUM(COLORX_32_32_FLOAT, 11) + GENERATE_ENUM(COLORX_32_32_32_32_FLOAT, 12) + GENERATE_ENUM(COLORX_2_3_3, 13) + GENERATE_ENUM(COLORX_8_8_8, 14) +END_ENUMTYPE(ColorformatX) + +START_ENUMTYPE(DepthformatX) + GENERATE_ENUM(DEPTHX_16, 0) + GENERATE_ENUM(DEPTHX_24_8, 1) +END_ENUMTYPE(DepthformatX) + +START_ENUMTYPE(CompareFrag) + GENERATE_ENUM(FRAG_NEVER, 0) + GENERATE_ENUM(FRAG_LESS, 1) + GENERATE_ENUM(FRAG_EQUAL, 2) + GENERATE_ENUM(FRAG_LEQUAL, 3) + GENERATE_ENUM(FRAG_GREATER, 4) + GENERATE_ENUM(FRAG_NOTEQUAL, 5) + GENERATE_ENUM(FRAG_GEQUAL, 6) + GENERATE_ENUM(FRAG_ALWAYS, 7) +END_ENUMTYPE(CompareFrag) + +START_ENUMTYPE(CompareRef) + GENERATE_ENUM(REF_NEVER, 0) + GENERATE_ENUM(REF_LESS, 1) + GENERATE_ENUM(REF_EQUAL, 2) + GENERATE_ENUM(REF_LEQUAL, 3) + GENERATE_ENUM(REF_GREATER, 4) + GENERATE_ENUM(REF_NOTEQUAL, 5) + GENERATE_ENUM(REF_GEQUAL, 6) + GENERATE_ENUM(REF_ALWAYS, 7) +END_ENUMTYPE(CompareRef) + +START_ENUMTYPE(StencilOp) + GENERATE_ENUM(STENCIL_KEEP, 0) + GENERATE_ENUM(STENCIL_ZERO, 1) + GENERATE_ENUM(STENCIL_REPLACE, 2) + GENERATE_ENUM(STENCIL_INCR_CLAMP, 3) + GENERATE_ENUM(STENCIL_DECR_CLAMP, 4) + GENERATE_ENUM(STENCIL_INVERT, 5) + GENERATE_ENUM(STENCIL_INCR_WRAP, 6) + GENERATE_ENUM(STENCIL_DECR_WRAP, 7) +END_ENUMTYPE(StencilOp) + +START_ENUMTYPE(BlendOpX) + GENERATE_ENUM(BLENDX_ZERO, 0) + GENERATE_ENUM(BLENDX_ONE, 1) + GENERATE_ENUM(BLENDX_SRC_COLOR, 4) + GENERATE_ENUM(BLENDX_ONE_MINUS_SRC_COLOR, 5) + GENERATE_ENUM(BLENDX_SRC_ALPHA, 6) + GENERATE_ENUM(BLENDX_ONE_MINUS_SRC_ALPHA, 7) + GENERATE_ENUM(BLENDX_DST_COLOR, 8) + GENERATE_ENUM(BLENDX_ONE_MINUS_DST_COLOR, 9) + GENERATE_ENUM(BLENDX_DST_ALPHA, 10) + GENERATE_ENUM(BLENDX_ONE_MINUS_DST_ALPHA, 11) + GENERATE_ENUM(BLENDX_CONSTANT_COLOR, 12) + GENERATE_ENUM(BLENDX_ONE_MINUS_CONSTANT_COLOR, 13) + GENERATE_ENUM(BLENDX_CONSTANT_ALPHA, 14) + GENERATE_ENUM(BLENDX_ONE_MINUS_CONSTANT_ALPHA, 15) + GENERATE_ENUM(BLENDX_SRC_ALPHA_SATURATE, 16) +END_ENUMTYPE(BlendOpX) + +START_ENUMTYPE(CombFuncX) + GENERATE_ENUM(COMB_DST_PLUS_SRC, 0) + GENERATE_ENUM(COMB_SRC_MINUS_DST, 1) + GENERATE_ENUM(COMB_MIN_DST_SRC, 2) + GENERATE_ENUM(COMB_MAX_DST_SRC, 3) + GENERATE_ENUM(COMB_DST_MINUS_SRC, 4) + GENERATE_ENUM(COMB_DST_PLUS_SRC_BIAS, 5) +END_ENUMTYPE(CombFuncX) + +START_ENUMTYPE(DitherModeX) + GENERATE_ENUM(DITHER_DISABLE, 0) + GENERATE_ENUM(DITHER_ALWAYS, 1) + GENERATE_ENUM(DITHER_IF_ALPHA_OFF, 2) +END_ENUMTYPE(DitherModeX) + +START_ENUMTYPE(DitherTypeX) + GENERATE_ENUM(DITHER_PIXEL, 0) + GENERATE_ENUM(DITHER_SUBPIXEL, 1) +END_ENUMTYPE(DitherTypeX) + +START_ENUMTYPE(EdramMode) + GENERATE_ENUM(EDRAM_NOP, 0) + GENERATE_ENUM(COLOR_DEPTH, 4) + GENERATE_ENUM(DEPTH_ONLY, 5) + GENERATE_ENUM(EDRAM_COPY, 6) +END_ENUMTYPE(EdramMode) + +START_ENUMTYPE(SurfaceEndian) + GENERATE_ENUM(ENDIAN_NONE, 0) + GENERATE_ENUM(ENDIAN_8IN16, 1) + GENERATE_ENUM(ENDIAN_8IN32, 2) + GENERATE_ENUM(ENDIAN_16IN32, 3) + GENERATE_ENUM(ENDIAN_8IN64, 4) + GENERATE_ENUM(ENDIAN_8IN128, 5) +END_ENUMTYPE(SurfaceEndian) + +START_ENUMTYPE(EdramSizeX) + GENERATE_ENUM(EDRAMSIZE_16KB, 0) + GENERATE_ENUM(EDRAMSIZE_32KB, 1) + GENERATE_ENUM(EDRAMSIZE_64KB, 2) + GENERATE_ENUM(EDRAMSIZE_128KB, 3) + GENERATE_ENUM(EDRAMSIZE_256KB, 4) + GENERATE_ENUM(EDRAMSIZE_512KB, 5) + GENERATE_ENUM(EDRAMSIZE_1MB, 6) + GENERATE_ENUM(EDRAMSIZE_2MB, 7) + GENERATE_ENUM(EDRAMSIZE_4MB, 8) + GENERATE_ENUM(EDRAMSIZE_8MB, 9) + GENERATE_ENUM(EDRAMSIZE_16MB, 10) +END_ENUMTYPE(EdramSizeX) + +START_ENUMTYPE(RB_PERFCNT_SELECT) + GENERATE_ENUM(RBPERF_CNTX_BUSY, 0) + GENERATE_ENUM(RBPERF_CNTX_BUSY_MAX, 1) + GENERATE_ENUM(RBPERF_SX_QUAD_STARVED, 2) + GENERATE_ENUM(RBPERF_SX_QUAD_STARVED_MAX, 3) + GENERATE_ENUM(RBPERF_GA_GC_CH0_SYS_REQ, 4) + GENERATE_ENUM(RBPERF_GA_GC_CH0_SYS_REQ_MAX, 5) + GENERATE_ENUM(RBPERF_GA_GC_CH1_SYS_REQ, 6) + GENERATE_ENUM(RBPERF_GA_GC_CH1_SYS_REQ_MAX, 7) + GENERATE_ENUM(RBPERF_MH_STARVED, 8) + GENERATE_ENUM(RBPERF_MH_STARVED_MAX, 9) + GENERATE_ENUM(RBPERF_AZ_BC_COLOR_BUSY, 10) + GENERATE_ENUM(RBPERF_AZ_BC_COLOR_BUSY_MAX, 11) + GENERATE_ENUM(RBPERF_AZ_BC_Z_BUSY, 12) + GENERATE_ENUM(RBPERF_AZ_BC_Z_BUSY_MAX, 13) + GENERATE_ENUM(RBPERF_RB_SC_TILE_RTR_N, 14) + GENERATE_ENUM(RBPERF_RB_SC_TILE_RTR_N_MAX, 15) + GENERATE_ENUM(RBPERF_RB_SC_SAMP_RTR_N, 16) + GENERATE_ENUM(RBPERF_RB_SC_SAMP_RTR_N_MAX, 17) + GENERATE_ENUM(RBPERF_RB_SX_QUAD_RTR_N, 18) + GENERATE_ENUM(RBPERF_RB_SX_QUAD_RTR_N_MAX, 19) + GENERATE_ENUM(RBPERF_RB_SX_COLOR_RTR_N, 20) + GENERATE_ENUM(RBPERF_RB_SX_COLOR_RTR_N_MAX, 21) + GENERATE_ENUM(RBPERF_RB_SC_SAMP_LZ_BUSY, 22) + GENERATE_ENUM(RBPERF_RB_SC_SAMP_LZ_BUSY_MAX, 23) + GENERATE_ENUM(RBPERF_ZXP_STALL, 24) + GENERATE_ENUM(RBPERF_ZXP_STALL_MAX, 25) + GENERATE_ENUM(RBPERF_EVENT_PENDING, 26) + GENERATE_ENUM(RBPERF_EVENT_PENDING_MAX, 27) + GENERATE_ENUM(RBPERF_RB_MH_VALID, 28) + GENERATE_ENUM(RBPERF_RB_MH_VALID_MAX, 29) + GENERATE_ENUM(RBPERF_SX_RB_QUAD_SEND, 30) + GENERATE_ENUM(RBPERF_SX_RB_COLOR_SEND, 31) + GENERATE_ENUM(RBPERF_SC_RB_TILE_SEND, 32) + GENERATE_ENUM(RBPERF_SC_RB_SAMPLE_SEND, 33) + GENERATE_ENUM(RBPERF_SX_RB_MEM_EXPORT, 34) + GENERATE_ENUM(RBPERF_SX_RB_QUAD_EVENT, 35) + GENERATE_ENUM(RBPERF_SC_RB_TILE_EVENT_FILTERED, 36) + GENERATE_ENUM(RBPERF_SC_RB_TILE_EVENT_ALL, 37) + GENERATE_ENUM(RBPERF_RB_SC_EZ_SEND, 38) + GENERATE_ENUM(RBPERF_RB_SX_INDEX_SEND, 39) + GENERATE_ENUM(RBPERF_GMEM_INTFO_RD, 40) + GENERATE_ENUM(RBPERF_GMEM_INTF1_RD, 41) + GENERATE_ENUM(RBPERF_GMEM_INTFO_WR, 42) + GENERATE_ENUM(RBPERF_GMEM_INTF1_WR, 43) + GENERATE_ENUM(RBPERF_RB_CP_CONTEXT_DONE, 44) + GENERATE_ENUM(RBPERF_RB_CP_CACHE_FLUSH, 45) + GENERATE_ENUM(RBPERF_ZPASS_DONE, 46) + GENERATE_ENUM(RBPERF_ZCMD_VALID, 47) + GENERATE_ENUM(RBPERF_CCMD_VALID, 48) + GENERATE_ENUM(RBPERF_ACCUM_GRANT, 49) + GENERATE_ENUM(RBPERF_ACCUM_C0_GRANT, 50) + GENERATE_ENUM(RBPERF_ACCUM_C1_GRANT, 51) + GENERATE_ENUM(RBPERF_ACCUM_FULL_BE_WR, 52) + GENERATE_ENUM(RBPERF_ACCUM_REQUEST_NO_GRANT, 53) + GENERATE_ENUM(RBPERF_ACCUM_TIMEOUT_PULSE, 54) + GENERATE_ENUM(RBPERF_ACCUM_LIN_TIMEOUT_PULSE, 55) + GENERATE_ENUM(RBPERF_ACCUM_CAM_HIT_FLUSHING, 56) +END_ENUMTYPE(RB_PERFCNT_SELECT) + +START_ENUMTYPE(DepthFormat) + GENERATE_ENUM(DEPTH_24_8, 22) + GENERATE_ENUM(DEPTH_24_8_FLOAT, 23) + GENERATE_ENUM(DEPTH_16, 24) +END_ENUMTYPE(DepthFormat) + +START_ENUMTYPE(SurfaceSwap) + GENERATE_ENUM(SWAP_LOWRED, 0) + GENERATE_ENUM(SWAP_LOWBLUE, 1) +END_ENUMTYPE(SurfaceSwap) + +START_ENUMTYPE(DepthArray) + GENERATE_ENUM(ARRAY_2D_ALT_DEPTH, 0) + GENERATE_ENUM(ARRAY_2D_DEPTH, 1) +END_ENUMTYPE(DepthArray) + +START_ENUMTYPE(ColorArray) + GENERATE_ENUM(ARRAY_2D_ALT_COLOR, 0) + GENERATE_ENUM(ARRAY_2D_COLOR, 1) + GENERATE_ENUM(ARRAY_3D_SLICE_COLOR, 3) +END_ENUMTYPE(ColorArray) + +START_ENUMTYPE(ColorFormat) + GENERATE_ENUM(COLOR_8, 2) + GENERATE_ENUM(COLOR_1_5_5_5, 3) + GENERATE_ENUM(COLOR_5_6_5, 4) + GENERATE_ENUM(COLOR_6_5_5, 5) + GENERATE_ENUM(COLOR_8_8_8_8, 6) + GENERATE_ENUM(COLOR_2_10_10_10, 7) + GENERATE_ENUM(COLOR_8_A, 8) + GENERATE_ENUM(COLOR_8_B, 9) + GENERATE_ENUM(COLOR_8_8, 10) + GENERATE_ENUM(COLOR_8_8_8, 11) + GENERATE_ENUM(COLOR_8_8_8_8_A, 14) + GENERATE_ENUM(COLOR_4_4_4_4, 15) + GENERATE_ENUM(COLOR_10_11_11, 16) + GENERATE_ENUM(COLOR_11_11_10, 17) + GENERATE_ENUM(COLOR_16, 24) + GENERATE_ENUM(COLOR_16_16, 25) + GENERATE_ENUM(COLOR_16_16_16_16, 26) + GENERATE_ENUM(COLOR_16_FLOAT, 30) + GENERATE_ENUM(COLOR_16_16_FLOAT, 31) + GENERATE_ENUM(COLOR_16_16_16_16_FLOAT, 32) + GENERATE_ENUM(COLOR_32_FLOAT, 36) + GENERATE_ENUM(COLOR_32_32_FLOAT, 37) + GENERATE_ENUM(COLOR_32_32_32_32_FLOAT, 38) + GENERATE_ENUM(COLOR_2_3_3, 39) +END_ENUMTYPE(ColorFormat) + +START_ENUMTYPE(SurfaceNumber) + GENERATE_ENUM(NUMBER_UREPEAT, 0) + GENERATE_ENUM(NUMBER_SREPEAT, 1) + GENERATE_ENUM(NUMBER_UINTEGER, 2) + GENERATE_ENUM(NUMBER_SINTEGER, 3) + GENERATE_ENUM(NUMBER_GAMMA, 4) + GENERATE_ENUM(NUMBER_FIXED, 5) + GENERATE_ENUM(NUMBER_FLOAT, 7) +END_ENUMTYPE(SurfaceNumber) + +START_ENUMTYPE(SurfaceFormat) + GENERATE_ENUM(FMT_1_REVERSE, 0) + GENERATE_ENUM(FMT_1, 1) + GENERATE_ENUM(FMT_8, 2) + GENERATE_ENUM(FMT_1_5_5_5, 3) + GENERATE_ENUM(FMT_5_6_5, 4) + GENERATE_ENUM(FMT_6_5_5, 5) + GENERATE_ENUM(FMT_8_8_8_8, 6) + GENERATE_ENUM(FMT_2_10_10_10, 7) + GENERATE_ENUM(FMT_8_A, 8) + GENERATE_ENUM(FMT_8_B, 9) + GENERATE_ENUM(FMT_8_8, 10) + GENERATE_ENUM(FMT_Cr_Y1_Cb_Y0, 11) + GENERATE_ENUM(FMT_Y1_Cr_Y0_Cb, 12) + GENERATE_ENUM(FMT_5_5_5_1, 13) + GENERATE_ENUM(FMT_8_8_8_8_A, 14) + GENERATE_ENUM(FMT_4_4_4_4, 15) + GENERATE_ENUM(FMT_8_8_8, 16) + GENERATE_ENUM(FMT_DXT1, 18) + GENERATE_ENUM(FMT_DXT2_3, 19) + GENERATE_ENUM(FMT_DXT4_5, 20) + GENERATE_ENUM(FMT_10_10_10_2, 21) + GENERATE_ENUM(FMT_24_8, 22) + GENERATE_ENUM(FMT_16, 24) + GENERATE_ENUM(FMT_16_16, 25) + GENERATE_ENUM(FMT_16_16_16_16, 26) + GENERATE_ENUM(FMT_16_EXPAND, 27) + GENERATE_ENUM(FMT_16_16_EXPAND, 28) + GENERATE_ENUM(FMT_16_16_16_16_EXPAND, 29) + GENERATE_ENUM(FMT_16_FLOAT, 30) + GENERATE_ENUM(FMT_16_16_FLOAT, 31) + GENERATE_ENUM(FMT_16_16_16_16_FLOAT, 32) + GENERATE_ENUM(FMT_32, 33) + GENERATE_ENUM(FMT_32_32, 34) + GENERATE_ENUM(FMT_32_32_32_32, 35) + GENERATE_ENUM(FMT_32_FLOAT, 36) + GENERATE_ENUM(FMT_32_32_FLOAT, 37) + GENERATE_ENUM(FMT_32_32_32_32_FLOAT, 38) + GENERATE_ENUM(FMT_ATI_TC_RGB, 39) + GENERATE_ENUM(FMT_ATI_TC_RGBA, 40) + GENERATE_ENUM(FMT_ATI_TC_555_565_RGB, 41) + GENERATE_ENUM(FMT_ATI_TC_555_565_RGBA, 42) + GENERATE_ENUM(FMT_ATI_TC_RGBA_INTERP, 43) + GENERATE_ENUM(FMT_ATI_TC_555_565_RGBA_INTERP, 44) + GENERATE_ENUM(FMT_ETC1_RGBA_INTERP, 46) + GENERATE_ENUM(FMT_ETC1_RGB, 47) + GENERATE_ENUM(FMT_ETC1_RGBA, 48) + GENERATE_ENUM(FMT_DXN, 49) + GENERATE_ENUM(FMT_2_3_3, 51) + GENERATE_ENUM(FMT_2_10_10_10_AS_16_16_16_16, 54) + GENERATE_ENUM(FMT_10_10_10_2_AS_16_16_16_16, 55) + GENERATE_ENUM(FMT_32_32_32_FLOAT, 57) + GENERATE_ENUM(FMT_DXT3A, 58) + GENERATE_ENUM(FMT_DXT5A, 59) + GENERATE_ENUM(FMT_CTX1, 60) +END_ENUMTYPE(SurfaceFormat) + +START_ENUMTYPE(SurfaceTiling) + GENERATE_ENUM(ARRAY_LINEAR, 0) + GENERATE_ENUM(ARRAY_TILED, 1) +END_ENUMTYPE(SurfaceTiling) + +START_ENUMTYPE(SurfaceArray) + GENERATE_ENUM(ARRAY_1D, 0) + GENERATE_ENUM(ARRAY_2D, 1) + GENERATE_ENUM(ARRAY_3D, 2) + GENERATE_ENUM(ARRAY_3D_SLICE, 3) +END_ENUMTYPE(SurfaceArray) + +START_ENUMTYPE(SurfaceNumberX) + GENERATE_ENUM(NUMBERX_UREPEAT, 0) + GENERATE_ENUM(NUMBERX_SREPEAT, 1) + GENERATE_ENUM(NUMBERX_UINTEGER, 2) + GENERATE_ENUM(NUMBERX_SINTEGER, 3) + GENERATE_ENUM(NUMBERX_FLOAT, 7) +END_ENUMTYPE(SurfaceNumberX) + +START_ENUMTYPE(ColorArrayX) + GENERATE_ENUM(ARRAYX_2D_COLOR, 0) + GENERATE_ENUM(ARRAYX_3D_SLICE_COLOR, 1) +END_ENUMTYPE(ColorArrayX) + + + + +// ************************************************************************** +// These are ones that had to be added in addition to what's generated +// by the autoreg (in CSIM) +// ************************************************************************** +START_ENUMTYPE(DXClipSpaceDef) + GENERATE_ENUM(DXCLIP_OPENGL, 0) + GENERATE_ENUM(DXCLIP_DIRECTX, 1) +END_ENUMTYPE(DXClipSpaceDef) + +START_ENUMTYPE(PixCenter) + GENERATE_ENUM(PIXCENTER_D3D, 0) + GENERATE_ENUM(PIXCENTER_OGL, 1) +END_ENUMTYPE(PixCenter) + +START_ENUMTYPE(RoundMode) + GENERATE_ENUM(TRUNCATE, 0) + GENERATE_ENUM(ROUND, 1) + GENERATE_ENUM(ROUNDTOEVEN, 2) + GENERATE_ENUM(ROUNDTOODD, 3) +END_ENUMTYPE(RoundMode) + +START_ENUMTYPE(QuantMode) + GENERATE_ENUM(ONE_SIXTEENTH, 0) + GENERATE_ENUM(ONE_EIGHTH, 1) + GENERATE_ENUM(ONE_QUARTER, 2) + GENERATE_ENUM(ONE_HALF, 3) + GENERATE_ENUM(ONE, 4) +END_ENUMTYPE(QuantMode) + +START_ENUMTYPE(FrontFace) + GENERATE_ENUM(FRONT_CCW, 0) + GENERATE_ENUM(FRONT_CW, 1) +END_ENUMTYPE(FrontFace) + +START_ENUMTYPE(PolyMode) + GENERATE_ENUM(DISABLED, 0) + GENERATE_ENUM(DUALMODE, 1) +END_ENUMTYPE(PolyMode) + +START_ENUMTYPE(PType) + GENERATE_ENUM(DRAW_POINTS, 0) + GENERATE_ENUM(DRAW_LINES, 1) + GENERATE_ENUM(DRAW_TRIANGLES, 2) +END_ENUMTYPE(PType) + +START_ENUMTYPE(MSAANumSamples) + GENERATE_ENUM(ONE, 0) + GENERATE_ENUM(TWO, 1) + GENERATE_ENUM(FOUR, 3) +END_ENUMTYPE(MSAANumSamples) + +START_ENUMTYPE(PatternBitOrder) + GENERATE_ENUM(LITTLE, 0) + GENERATE_ENUM(BIG, 1) +END_ENUMTYPE(PatternBitOrder) + +START_ENUMTYPE(AutoResetCntl) + GENERATE_ENUM(NEVER, 0) + GENERATE_ENUM(EACHPRIMITIVE, 1) + GENERATE_ENUM(EACHPACKET, 2) +END_ENUMTYPE(AutoResetCntl) + +START_ENUMTYPE(ParamShade) + GENERATE_ENUM(FLAT, 0) + GENERATE_ENUM(GOURAUD, 1) +END_ENUMTYPE(ParamShade) + +START_ENUMTYPE(SamplingPattern) + GENERATE_ENUM(CENTROID, 0) + GENERATE_ENUM(PIXCENTER, 1) +END_ENUMTYPE(SamplingPattern) + +START_ENUMTYPE(MSAASamples) + GENERATE_ENUM(ONE, 0) + GENERATE_ENUM(TWO, 1) + GENERATE_ENUM(FOUR, 2) +END_ENUMTYPE(MSAASamples) + +START_ENUMTYPE(CopySampleSelect) + GENERATE_ENUM(SAMPLE_0, 0) + GENERATE_ENUM(SAMPLE_1, 1) + GENERATE_ENUM(SAMPLE_2, 2) + GENERATE_ENUM(SAMPLE_3, 3) + GENERATE_ENUM(SAMPLE_01, 4) + GENERATE_ENUM(SAMPLE_23, 5) + GENERATE_ENUM(SAMPLE_0123, 6) +END_ENUMTYPE(CopySampleSelect) + + +#undef START_ENUMTYPE +#undef GENERATE_ENUM +#undef END_ENUMTYPE diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_genreg.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_genreg.h new file mode 100644 index 000000000000..d44be483e953 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_genreg.h @@ -0,0 +1,3310 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +START_REGISTER(PA_CL_VPORT_XSCALE) + GENERATE_FIELD(VPORT_XSCALE, float) +END_REGISTER(PA_CL_VPORT_XSCALE) + +START_REGISTER(PA_CL_VPORT_XOFFSET) + GENERATE_FIELD(VPORT_XOFFSET, float) +END_REGISTER(PA_CL_VPORT_XOFFSET) + +START_REGISTER(PA_CL_VPORT_YSCALE) + GENERATE_FIELD(VPORT_YSCALE, float) +END_REGISTER(PA_CL_VPORT_YSCALE) + +START_REGISTER(PA_CL_VPORT_YOFFSET) + GENERATE_FIELD(VPORT_YOFFSET, float) +END_REGISTER(PA_CL_VPORT_YOFFSET) + +START_REGISTER(PA_CL_VPORT_ZSCALE) + GENERATE_FIELD(VPORT_ZSCALE, float) +END_REGISTER(PA_CL_VPORT_ZSCALE) + +START_REGISTER(PA_CL_VPORT_ZOFFSET) + GENERATE_FIELD(VPORT_ZOFFSET, float) +END_REGISTER(PA_CL_VPORT_ZOFFSET) + +START_REGISTER(PA_CL_VTE_CNTL) + GENERATE_FIELD(VPORT_X_SCALE_ENA, bool) + GENERATE_FIELD(VPORT_X_OFFSET_ENA, bool) + GENERATE_FIELD(VPORT_Y_SCALE_ENA, bool) + GENERATE_FIELD(VPORT_Y_OFFSET_ENA, bool) + GENERATE_FIELD(VPORT_Z_SCALE_ENA, bool) + GENERATE_FIELD(VPORT_Z_OFFSET_ENA, bool) + GENERATE_FIELD(VTX_XY_FMT, bool) + GENERATE_FIELD(VTX_Z_FMT, bool) + GENERATE_FIELD(VTX_W0_FMT, bool) + GENERATE_FIELD(PERFCOUNTER_REF, bool) +END_REGISTER(PA_CL_VTE_CNTL) + +START_REGISTER(PA_CL_CLIP_CNTL) + GENERATE_FIELD(CLIP_DISABLE, bool) + GENERATE_FIELD(BOUNDARY_EDGE_FLAG_ENA, bool) + GENERATE_FIELD(DX_CLIP_SPACE_DEF, DXClipSpaceDef) + GENERATE_FIELD(DIS_CLIP_ERR_DETECT, bool) + GENERATE_FIELD(VTX_KILL_OR, bool) + GENERATE_FIELD(XY_NAN_RETAIN, bool) + GENERATE_FIELD(Z_NAN_RETAIN, bool) + GENERATE_FIELD(W_NAN_RETAIN, bool) +END_REGISTER(PA_CL_CLIP_CNTL) + +START_REGISTER(PA_CL_GB_VERT_CLIP_ADJ) + GENERATE_FIELD(DATA_REGISTER, float) +END_REGISTER(PA_CL_GB_VERT_CLIP_ADJ) + +START_REGISTER(PA_CL_GB_VERT_DISC_ADJ) + GENERATE_FIELD(DATA_REGISTER, float) +END_REGISTER(PA_CL_GB_VERT_DISC_ADJ) + +START_REGISTER(PA_CL_GB_HORZ_CLIP_ADJ) + GENERATE_FIELD(DATA_REGISTER, float) +END_REGISTER(PA_CL_GB_HORZ_CLIP_ADJ) + +START_REGISTER(PA_CL_GB_HORZ_DISC_ADJ) + GENERATE_FIELD(DATA_REGISTER, float) +END_REGISTER(PA_CL_GB_HORZ_DISC_ADJ) + +START_REGISTER(PA_CL_ENHANCE) + GENERATE_FIELD(CLIP_VTX_REORDER_ENA, bool) + GENERATE_FIELD(ECO_SPARE3, int) + GENERATE_FIELD(ECO_SPARE2, int) + GENERATE_FIELD(ECO_SPARE1, int) + GENERATE_FIELD(ECO_SPARE0, int) +END_REGISTER(PA_CL_ENHANCE) + +START_REGISTER(PA_SC_ENHANCE) + GENERATE_FIELD(ECO_SPARE3, int) + GENERATE_FIELD(ECO_SPARE2, int) + GENERATE_FIELD(ECO_SPARE1, int) + GENERATE_FIELD(ECO_SPARE0, int) +END_REGISTER(PA_SC_ENHANCE) + +START_REGISTER(PA_SU_VTX_CNTL) + GENERATE_FIELD(PIX_CENTER, PixCenter) + GENERATE_FIELD(ROUND_MODE, RoundMode) + GENERATE_FIELD(QUANT_MODE, QuantMode) +END_REGISTER(PA_SU_VTX_CNTL) + +START_REGISTER(PA_SU_POINT_SIZE) + GENERATE_FIELD(HEIGHT, fixed12_4) + GENERATE_FIELD(WIDTH, fixed12_4) +END_REGISTER(PA_SU_POINT_SIZE) + +START_REGISTER(PA_SU_POINT_MINMAX) + GENERATE_FIELD(MIN_SIZE, fixed12_4) + GENERATE_FIELD(MAX_SIZE, fixed12_4) +END_REGISTER(PA_SU_POINT_MINMAX) + +START_REGISTER(PA_SU_LINE_CNTL) + GENERATE_FIELD(WIDTH, fixed12_4) +END_REGISTER(PA_SU_LINE_CNTL) + +START_REGISTER(PA_SU_SC_MODE_CNTL) + GENERATE_FIELD(CULL_FRONT, bool) + GENERATE_FIELD(CULL_BACK, bool) + GENERATE_FIELD(FACE, FrontFace) + GENERATE_FIELD(POLY_MODE, PolyMode) + GENERATE_FIELD(POLYMODE_FRONT_PTYPE, PType) + GENERATE_FIELD(POLYMODE_BACK_PTYPE, PType) + GENERATE_FIELD(POLY_OFFSET_FRONT_ENABLE, bool) + GENERATE_FIELD(POLY_OFFSET_BACK_ENABLE, bool) + GENERATE_FIELD(POLY_OFFSET_PARA_ENABLE, bool) + GENERATE_FIELD(MSAA_ENABLE, bool) + GENERATE_FIELD(VTX_WINDOW_OFFSET_ENABLE, bool) + GENERATE_FIELD(LINE_STIPPLE_ENABLE, bool) + GENERATE_FIELD(PROVOKING_VTX_LAST, bool) + GENERATE_FIELD(PERSP_CORR_DIS, bool) + GENERATE_FIELD(MULTI_PRIM_IB_ENA, bool) + GENERATE_FIELD(QUAD_ORDER_ENABLE, bool) + GENERATE_FIELD(WAIT_RB_IDLE_ALL_TRI, bool) + GENERATE_FIELD(WAIT_RB_IDLE_FIRST_TRI_NEW_STATE, bool) +END_REGISTER(PA_SU_SC_MODE_CNTL) + +START_REGISTER(PA_SU_POLY_OFFSET_FRONT_SCALE) + GENERATE_FIELD(SCALE, float) +END_REGISTER(PA_SU_POLY_OFFSET_FRONT_SCALE) + +START_REGISTER(PA_SU_POLY_OFFSET_FRONT_OFFSET) + GENERATE_FIELD(OFFSET, float) +END_REGISTER(PA_SU_POLY_OFFSET_FRONT_OFFSET) + +START_REGISTER(PA_SU_POLY_OFFSET_BACK_SCALE) + GENERATE_FIELD(SCALE, float) +END_REGISTER(PA_SU_POLY_OFFSET_BACK_SCALE) + +START_REGISTER(PA_SU_POLY_OFFSET_BACK_OFFSET) + GENERATE_FIELD(OFFSET, float) +END_REGISTER(PA_SU_POLY_OFFSET_BACK_OFFSET) + +START_REGISTER(PA_SU_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, SU_PERFCNT_SELECT) +END_REGISTER(PA_SU_PERFCOUNTER0_SELECT) + +START_REGISTER(PA_SU_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(PA_SU_PERFCOUNTER1_SELECT) + +START_REGISTER(PA_SU_PERFCOUNTER2_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(PA_SU_PERFCOUNTER2_SELECT) + +START_REGISTER(PA_SU_PERFCOUNTER3_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(PA_SU_PERFCOUNTER3_SELECT) + +START_REGISTER(PA_SU_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER0_LOW) + +START_REGISTER(PA_SU_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER0_HI) + +START_REGISTER(PA_SU_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER1_LOW) + +START_REGISTER(PA_SU_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER1_HI) + +START_REGISTER(PA_SU_PERFCOUNTER2_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER2_LOW) + +START_REGISTER(PA_SU_PERFCOUNTER2_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER2_HI) + +START_REGISTER(PA_SU_PERFCOUNTER3_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER3_LOW) + +START_REGISTER(PA_SU_PERFCOUNTER3_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER3_HI) + +START_REGISTER(PA_SC_WINDOW_OFFSET) + GENERATE_FIELD(WINDOW_X_OFFSET, signedint15) + GENERATE_FIELD(WINDOW_Y_OFFSET, signedint15) +END_REGISTER(PA_SC_WINDOW_OFFSET) + +START_REGISTER(PA_SC_AA_CONFIG) + GENERATE_FIELD(MSAA_NUM_SAMPLES, MSAANumSamples) + GENERATE_FIELD(MAX_SAMPLE_DIST, int) +END_REGISTER(PA_SC_AA_CONFIG) + +START_REGISTER(PA_SC_AA_MASK) + GENERATE_FIELD(AA_MASK, hex) +END_REGISTER(PA_SC_AA_MASK) + +START_REGISTER(PA_SC_LINE_STIPPLE) + GENERATE_FIELD(LINE_PATTERN, hex) + GENERATE_FIELD(REPEAT_COUNT, intMinusOne) + GENERATE_FIELD(PATTERN_BIT_ORDER, PatternBitOrder) + GENERATE_FIELD(AUTO_RESET_CNTL, AutoResetCntl) +END_REGISTER(PA_SC_LINE_STIPPLE) + +START_REGISTER(PA_SC_LINE_CNTL) + GENERATE_FIELD(BRES_CNTL, int) + GENERATE_FIELD(USE_BRES_CNTL, bool) + GENERATE_FIELD(EXPAND_LINE_WIDTH, bool) + GENERATE_FIELD(LAST_PIXEL, bool) +END_REGISTER(PA_SC_LINE_CNTL) + +START_REGISTER(PA_SC_WINDOW_SCISSOR_TL) + GENERATE_FIELD(TL_X, int) + GENERATE_FIELD(TL_Y, int) + GENERATE_FIELD(WINDOW_OFFSET_DISABLE, bool) +END_REGISTER(PA_SC_WINDOW_SCISSOR_TL) + +START_REGISTER(PA_SC_WINDOW_SCISSOR_BR) + GENERATE_FIELD(BR_X, int) + GENERATE_FIELD(BR_Y, int) +END_REGISTER(PA_SC_WINDOW_SCISSOR_BR) + +START_REGISTER(PA_SC_SCREEN_SCISSOR_TL) + GENERATE_FIELD(TL_X, int) + GENERATE_FIELD(TL_Y, int) +END_REGISTER(PA_SC_SCREEN_SCISSOR_TL) + +START_REGISTER(PA_SC_SCREEN_SCISSOR_BR) + GENERATE_FIELD(BR_X, int) + GENERATE_FIELD(BR_Y, int) +END_REGISTER(PA_SC_SCREEN_SCISSOR_BR) + +START_REGISTER(PA_SC_VIZ_QUERY) + GENERATE_FIELD(VIZ_QUERY_ENA, bool) + GENERATE_FIELD(VIZ_QUERY_ID, int) + GENERATE_FIELD(KILL_PIX_POST_EARLY_Z, bool) +END_REGISTER(PA_SC_VIZ_QUERY) + +START_REGISTER(PA_SC_VIZ_QUERY_STATUS) + GENERATE_FIELD(STATUS_BITS, hex) +END_REGISTER(PA_SC_VIZ_QUERY_STATUS) + +START_REGISTER(PA_SC_LINE_STIPPLE_STATE) + GENERATE_FIELD(CURRENT_PTR, int) + GENERATE_FIELD(CURRENT_COUNT, int) +END_REGISTER(PA_SC_LINE_STIPPLE_STATE) + +START_REGISTER(PA_SC_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, SC_PERFCNT_SELECT) +END_REGISTER(PA_SC_PERFCOUNTER0_SELECT) + +START_REGISTER(PA_SC_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SC_PERFCOUNTER0_LOW) + +START_REGISTER(PA_SC_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SC_PERFCOUNTER0_HI) + +START_REGISTER(PA_CL_CNTL_STATUS) + GENERATE_FIELD(CL_BUSY, int) +END_REGISTER(PA_CL_CNTL_STATUS) + +START_REGISTER(PA_SU_CNTL_STATUS) + GENERATE_FIELD(SU_BUSY, int) +END_REGISTER(PA_SU_CNTL_STATUS) + +START_REGISTER(PA_SC_CNTL_STATUS) + GENERATE_FIELD(SC_BUSY, int) +END_REGISTER(PA_SC_CNTL_STATUS) + +START_REGISTER(PA_SU_DEBUG_CNTL) + GENERATE_FIELD(SU_DEBUG_INDX, int) +END_REGISTER(PA_SU_DEBUG_CNTL) + +START_REGISTER(PA_SU_DEBUG_DATA) + GENERATE_FIELD(DATA, hex) +END_REGISTER(PA_SU_DEBUG_DATA) + +START_REGISTER(PA_SC_DEBUG_CNTL) + GENERATE_FIELD(SC_DEBUG_INDX, int) +END_REGISTER(PA_SC_DEBUG_CNTL) + +START_REGISTER(PA_SC_DEBUG_DATA) + GENERATE_FIELD(DATA, int) +END_REGISTER(PA_SC_DEBUG_DATA) + +START_REGISTER(GFX_COPY_STATE) + GENERATE_FIELD(SRC_STATE_ID, int) +END_REGISTER(GFX_COPY_STATE) + +START_REGISTER(VGT_DRAW_INITIATOR) + GENERATE_FIELD(PRIM_TYPE, VGT_DI_PRIM_TYPE) + GENERATE_FIELD(SOURCE_SELECT, VGT_DI_SOURCE_SELECT) + GENERATE_FIELD(INDEX_SIZE, VGT_DI_INDEX_SIZE) + GENERATE_FIELD(NOT_EOP, bool) + GENERATE_FIELD(SMALL_INDEX, VGT_DI_SMALL_INDEX) + GENERATE_FIELD(PRE_FETCH_CULL_ENABLE, VGT_DI_PRE_FETCH_CULL_ENABLE) + GENERATE_FIELD(GRP_CULL_ENABLE, VGT_DI_GRP_CULL_ENABLE) + GENERATE_FIELD(NUM_INDICES, uint) +END_REGISTER(VGT_DRAW_INITIATOR) + +START_REGISTER(VGT_EVENT_INITIATOR) + GENERATE_FIELD(EVENT_TYPE, VGT_EVENT_TYPE) +END_REGISTER(VGT_EVENT_INITIATOR) + +START_REGISTER(VGT_DMA_BASE) + GENERATE_FIELD(BASE_ADDR, uint) +END_REGISTER(VGT_DMA_BASE) + +START_REGISTER(VGT_DMA_SIZE) + GENERATE_FIELD(NUM_WORDS, uint) + GENERATE_FIELD(SWAP_MODE, VGT_DMA_SWAP_MODE) +END_REGISTER(VGT_DMA_SIZE) + +START_REGISTER(VGT_BIN_BASE) + GENERATE_FIELD(BIN_BASE_ADDR, uint) +END_REGISTER(VGT_BIN_BASE) + +START_REGISTER(VGT_BIN_SIZE) + GENERATE_FIELD(NUM_WORDS, uint) +END_REGISTER(VGT_BIN_SIZE) + +START_REGISTER(VGT_CURRENT_BIN_ID_MIN) + GENERATE_FIELD(COLUMN, int) + GENERATE_FIELD(ROW, int) + GENERATE_FIELD(GUARD_BAND, int) +END_REGISTER(VGT_CURRENT_BIN_ID_MIN) + +START_REGISTER(VGT_CURRENT_BIN_ID_MAX) + GENERATE_FIELD(COLUMN, int) + GENERATE_FIELD(ROW, int) + GENERATE_FIELD(GUARD_BAND, int) +END_REGISTER(VGT_CURRENT_BIN_ID_MAX) + +START_REGISTER(VGT_IMMED_DATA) + GENERATE_FIELD(DATA, hex) +END_REGISTER(VGT_IMMED_DATA) + +START_REGISTER(VGT_MAX_VTX_INDX) + GENERATE_FIELD(MAX_INDX, int) +END_REGISTER(VGT_MAX_VTX_INDX) + +START_REGISTER(VGT_MIN_VTX_INDX) + GENERATE_FIELD(MIN_INDX, int) +END_REGISTER(VGT_MIN_VTX_INDX) + +START_REGISTER(VGT_INDX_OFFSET) + GENERATE_FIELD(INDX_OFFSET, int) +END_REGISTER(VGT_INDX_OFFSET) + +START_REGISTER(VGT_VERTEX_REUSE_BLOCK_CNTL) + GENERATE_FIELD(VTX_REUSE_DEPTH, int) +END_REGISTER(VGT_VERTEX_REUSE_BLOCK_CNTL) + +START_REGISTER(VGT_OUT_DEALLOC_CNTL) + GENERATE_FIELD(DEALLOC_DIST, int) +END_REGISTER(VGT_OUT_DEALLOC_CNTL) + +START_REGISTER(VGT_MULTI_PRIM_IB_RESET_INDX) + GENERATE_FIELD(RESET_INDX, int) +END_REGISTER(VGT_MULTI_PRIM_IB_RESET_INDX) + +START_REGISTER(VGT_ENHANCE) + GENERATE_FIELD(MISC, hex) +END_REGISTER(VGT_ENHANCE) + +START_REGISTER(VGT_VTX_VECT_EJECT_REG) + GENERATE_FIELD(PRIM_COUNT, int) +END_REGISTER(VGT_VTX_VECT_EJECT_REG) + +START_REGISTER(VGT_LAST_COPY_STATE) + GENERATE_FIELD(SRC_STATE_ID, int) + GENERATE_FIELD(DST_STATE_ID, int) +END_REGISTER(VGT_LAST_COPY_STATE) + +START_REGISTER(VGT_DEBUG_CNTL) + GENERATE_FIELD(VGT_DEBUG_INDX, int) +END_REGISTER(VGT_DEBUG_CNTL) + +START_REGISTER(VGT_DEBUG_DATA) + GENERATE_FIELD(DATA, hex) +END_REGISTER(VGT_DEBUG_DATA) + +START_REGISTER(VGT_CNTL_STATUS) + GENERATE_FIELD(VGT_BUSY, int) + GENERATE_FIELD(VGT_DMA_BUSY, int) + GENERATE_FIELD(VGT_DMA_REQ_BUSY, int) + GENERATE_FIELD(VGT_GRP_BUSY, int) + GENERATE_FIELD(VGT_VR_BUSY, int) + GENERATE_FIELD(VGT_BIN_BUSY, int) + GENERATE_FIELD(VGT_PT_BUSY, int) + GENERATE_FIELD(VGT_OUT_BUSY, int) + GENERATE_FIELD(VGT_OUT_INDX_BUSY, int) +END_REGISTER(VGT_CNTL_STATUS) + +START_REGISTER(VGT_CRC_SQ_DATA) + GENERATE_FIELD(CRC, hex) +END_REGISTER(VGT_CRC_SQ_DATA) + +START_REGISTER(VGT_CRC_SQ_CTRL) + GENERATE_FIELD(CRC, hex) +END_REGISTER(VGT_CRC_SQ_CTRL) + +START_REGISTER(VGT_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT) +END_REGISTER(VGT_PERFCOUNTER0_SELECT) + +START_REGISTER(VGT_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT) +END_REGISTER(VGT_PERFCOUNTER1_SELECT) + +START_REGISTER(VGT_PERFCOUNTER2_SELECT) + GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT) +END_REGISTER(VGT_PERFCOUNTER2_SELECT) + +START_REGISTER(VGT_PERFCOUNTER3_SELECT) + GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT) +END_REGISTER(VGT_PERFCOUNTER3_SELECT) + +START_REGISTER(VGT_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER0_LOW) + +START_REGISTER(VGT_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER1_LOW) + +START_REGISTER(VGT_PERFCOUNTER2_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER2_LOW) + +START_REGISTER(VGT_PERFCOUNTER3_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER3_LOW) + +START_REGISTER(VGT_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER0_HI) + +START_REGISTER(VGT_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER1_HI) + +START_REGISTER(VGT_PERFCOUNTER2_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER2_HI) + +START_REGISTER(VGT_PERFCOUNTER3_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER3_HI) + +START_REGISTER(TC_CNTL_STATUS) + GENERATE_FIELD(L2_INVALIDATE, int) + GENERATE_FIELD(TC_L2_HIT_MISS, int) + GENERATE_FIELD(TC_BUSY, int) +END_REGISTER(TC_CNTL_STATUS) + +START_REGISTER(TCR_CHICKEN) + GENERATE_FIELD(SPARE, hex) +END_REGISTER(TCR_CHICKEN) + +START_REGISTER(TCF_CHICKEN) + GENERATE_FIELD(SPARE, hex) +END_REGISTER(TCF_CHICKEN) + +START_REGISTER(TCM_CHICKEN) + GENERATE_FIELD(TCO_READ_LATENCY_FIFO_PROG_DEPTH, int) + GENERATE_FIELD(ETC_COLOR_ENDIAN, int) + GENERATE_FIELD(SPARE, hex) +END_REGISTER(TCM_CHICKEN) + +START_REGISTER(TCR_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCR_PERFCOUNT_SELECT) +END_REGISTER(TCR_PERFCOUNTER0_SELECT) + +START_REGISTER(TCR_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCR_PERFCOUNT_SELECT) +END_REGISTER(TCR_PERFCOUNTER1_SELECT) + +START_REGISTER(TCR_PERFCOUNTER0_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCR_PERFCOUNTER0_HI) + +START_REGISTER(TCR_PERFCOUNTER1_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCR_PERFCOUNTER1_HI) + +START_REGISTER(TCR_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCR_PERFCOUNTER0_LOW) + +START_REGISTER(TCR_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCR_PERFCOUNTER1_LOW) + +START_REGISTER(TP_TC_CLKGATE_CNTL) + GENERATE_FIELD(TP_BUSY_EXTEND, int) + GENERATE_FIELD(TC_BUSY_EXTEND, int) +END_REGISTER(TP_TC_CLKGATE_CNTL) + +START_REGISTER(TPC_CNTL_STATUS) + GENERATE_FIELD(TPC_INPUT_BUSY, int) + GENERATE_FIELD(TPC_TC_FIFO_BUSY, int) + GENERATE_FIELD(TPC_STATE_FIFO_BUSY, int) + GENERATE_FIELD(TPC_FETCH_FIFO_BUSY, int) + GENERATE_FIELD(TPC_WALKER_PIPE_BUSY, int) + GENERATE_FIELD(TPC_WALK_FIFO_BUSY, int) + GENERATE_FIELD(TPC_WALKER_BUSY, int) + GENERATE_FIELD(TPC_ALIGNER_PIPE_BUSY, int) + GENERATE_FIELD(TPC_ALIGN_FIFO_BUSY, int) + GENERATE_FIELD(TPC_ALIGNER_BUSY, int) + GENERATE_FIELD(TPC_RR_FIFO_BUSY, int) + GENERATE_FIELD(TPC_BLEND_PIPE_BUSY, int) + GENERATE_FIELD(TPC_OUT_FIFO_BUSY, int) + GENERATE_FIELD(TPC_BLEND_BUSY, int) + GENERATE_FIELD(TF_TW_RTS, int) + GENERATE_FIELD(TF_TW_STATE_RTS, int) + GENERATE_FIELD(TF_TW_RTR, int) + GENERATE_FIELD(TW_TA_RTS, int) + GENERATE_FIELD(TW_TA_TT_RTS, int) + GENERATE_FIELD(TW_TA_LAST_RTS, int) + GENERATE_FIELD(TW_TA_RTR, int) + GENERATE_FIELD(TA_TB_RTS, int) + GENERATE_FIELD(TA_TB_TT_RTS, int) + GENERATE_FIELD(TA_TB_RTR, int) + GENERATE_FIELD(TA_TF_RTS, int) + GENERATE_FIELD(TA_TF_TC_FIFO_REN, int) + GENERATE_FIELD(TP_SQ_DEC, int) + GENERATE_FIELD(TPC_BUSY, int) +END_REGISTER(TPC_CNTL_STATUS) + +START_REGISTER(TPC_DEBUG0) + GENERATE_FIELD(LOD_CNTL, int) + GENERATE_FIELD(IC_CTR, int) + GENERATE_FIELD(WALKER_CNTL, int) + GENERATE_FIELD(ALIGNER_CNTL, int) + GENERATE_FIELD(PREV_TC_STATE_VALID, int) + GENERATE_FIELD(WALKER_STATE, int) + GENERATE_FIELD(ALIGNER_STATE, int) + GENERATE_FIELD(REG_CLK_EN, int) + GENERATE_FIELD(TPC_CLK_EN, int) + GENERATE_FIELD(SQ_TP_WAKEUP, int) +END_REGISTER(TPC_DEBUG0) + +START_REGISTER(TPC_DEBUG1) + GENERATE_FIELD(UNUSED, int) +END_REGISTER(TPC_DEBUG1) + +START_REGISTER(TPC_CHICKEN) + GENERATE_FIELD(BLEND_PRECISION, int) + GENERATE_FIELD(SPARE, int) +END_REGISTER(TPC_CHICKEN) + +START_REGISTER(TP0_CNTL_STATUS) + GENERATE_FIELD(TP_INPUT_BUSY, int) + GENERATE_FIELD(TP_LOD_BUSY, int) + GENERATE_FIELD(TP_LOD_FIFO_BUSY, int) + GENERATE_FIELD(TP_ADDR_BUSY, int) + GENERATE_FIELD(TP_ALIGN_FIFO_BUSY, int) + GENERATE_FIELD(TP_ALIGNER_BUSY, int) + GENERATE_FIELD(TP_TC_FIFO_BUSY, int) + GENERATE_FIELD(TP_RR_FIFO_BUSY, int) + GENERATE_FIELD(TP_FETCH_BUSY, int) + GENERATE_FIELD(TP_CH_BLEND_BUSY, int) + GENERATE_FIELD(TP_TT_BUSY, int) + GENERATE_FIELD(TP_HICOLOR_BUSY, int) + GENERATE_FIELD(TP_BLEND_BUSY, int) + GENERATE_FIELD(TP_OUT_FIFO_BUSY, int) + GENERATE_FIELD(TP_OUTPUT_BUSY, int) + GENERATE_FIELD(IN_LC_RTS, int) + GENERATE_FIELD(LC_LA_RTS, int) + GENERATE_FIELD(LA_FL_RTS, int) + GENERATE_FIELD(FL_TA_RTS, int) + GENERATE_FIELD(TA_FA_RTS, int) + GENERATE_FIELD(TA_FA_TT_RTS, int) + GENERATE_FIELD(FA_AL_RTS, int) + GENERATE_FIELD(FA_AL_TT_RTS, int) + GENERATE_FIELD(AL_TF_RTS, int) + GENERATE_FIELD(AL_TF_TT_RTS, int) + GENERATE_FIELD(TF_TB_RTS, int) + GENERATE_FIELD(TF_TB_TT_RTS, int) + GENERATE_FIELD(TB_TT_RTS, int) + GENERATE_FIELD(TB_TT_TT_RESET, int) + GENERATE_FIELD(TB_TO_RTS, int) + GENERATE_FIELD(TP_BUSY, int) +END_REGISTER(TP0_CNTL_STATUS) + +START_REGISTER(TP0_DEBUG) + GENERATE_FIELD(Q_LOD_CNTL, int) + GENERATE_FIELD(Q_SQ_TP_WAKEUP, int) + GENERATE_FIELD(FL_TA_ADDRESSER_CNTL, int) + GENERATE_FIELD(REG_CLK_EN, int) + GENERATE_FIELD(PERF_CLK_EN, int) + GENERATE_FIELD(TP_CLK_EN, int) + GENERATE_FIELD(Q_WALKER_CNTL, int) + GENERATE_FIELD(Q_ALIGNER_CNTL, int) +END_REGISTER(TP0_DEBUG) + +START_REGISTER(TP0_CHICKEN) + GENERATE_FIELD(TT_MODE, int) + GENERATE_FIELD(VFETCH_ADDRESS_MODE, int) + GENERATE_FIELD(SPARE, int) +END_REGISTER(TP0_CHICKEN) + +START_REGISTER(TP0_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TP_PERFCOUNT_SELECT) +END_REGISTER(TP0_PERFCOUNTER0_SELECT) + +START_REGISTER(TP0_PERFCOUNTER0_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TP0_PERFCOUNTER0_HI) + +START_REGISTER(TP0_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TP0_PERFCOUNTER0_LOW) + +START_REGISTER(TP0_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, int) +END_REGISTER(TP0_PERFCOUNTER1_SELECT) + +START_REGISTER(TP0_PERFCOUNTER1_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TP0_PERFCOUNTER1_HI) + +START_REGISTER(TP0_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TP0_PERFCOUNTER1_LOW) + +START_REGISTER(TCM_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCM_PERFCOUNT_SELECT) +END_REGISTER(TCM_PERFCOUNTER0_SELECT) + +START_REGISTER(TCM_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCM_PERFCOUNT_SELECT) +END_REGISTER(TCM_PERFCOUNTER1_SELECT) + +START_REGISTER(TCM_PERFCOUNTER0_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCM_PERFCOUNTER0_HI) + +START_REGISTER(TCM_PERFCOUNTER1_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCM_PERFCOUNTER1_HI) + +START_REGISTER(TCM_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCM_PERFCOUNTER0_LOW) + +START_REGISTER(TCM_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCM_PERFCOUNTER1_LOW) + +START_REGISTER(TCF_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER0_SELECT) + +START_REGISTER(TCF_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER1_SELECT) + +START_REGISTER(TCF_PERFCOUNTER2_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER2_SELECT) + +START_REGISTER(TCF_PERFCOUNTER3_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER3_SELECT) + +START_REGISTER(TCF_PERFCOUNTER4_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER4_SELECT) + +START_REGISTER(TCF_PERFCOUNTER5_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER5_SELECT) + +START_REGISTER(TCF_PERFCOUNTER6_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER6_SELECT) + +START_REGISTER(TCF_PERFCOUNTER7_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER7_SELECT) + +START_REGISTER(TCF_PERFCOUNTER8_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER8_SELECT) + +START_REGISTER(TCF_PERFCOUNTER9_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER9_SELECT) + +START_REGISTER(TCF_PERFCOUNTER10_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER10_SELECT) + +START_REGISTER(TCF_PERFCOUNTER11_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER11_SELECT) + +START_REGISTER(TCF_PERFCOUNTER0_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER0_HI) + +START_REGISTER(TCF_PERFCOUNTER1_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER1_HI) + +START_REGISTER(TCF_PERFCOUNTER2_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER2_HI) + +START_REGISTER(TCF_PERFCOUNTER3_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER3_HI) + +START_REGISTER(TCF_PERFCOUNTER4_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER4_HI) + +START_REGISTER(TCF_PERFCOUNTER5_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER5_HI) + +START_REGISTER(TCF_PERFCOUNTER6_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER6_HI) + +START_REGISTER(TCF_PERFCOUNTER7_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER7_HI) + +START_REGISTER(TCF_PERFCOUNTER8_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER8_HI) + +START_REGISTER(TCF_PERFCOUNTER9_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER9_HI) + +START_REGISTER(TCF_PERFCOUNTER10_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER10_HI) + +START_REGISTER(TCF_PERFCOUNTER11_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER11_HI) + +START_REGISTER(TCF_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER0_LOW) + +START_REGISTER(TCF_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER1_LOW) + +START_REGISTER(TCF_PERFCOUNTER2_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER2_LOW) + +START_REGISTER(TCF_PERFCOUNTER3_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER3_LOW) + +START_REGISTER(TCF_PERFCOUNTER4_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER4_LOW) + +START_REGISTER(TCF_PERFCOUNTER5_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER5_LOW) + +START_REGISTER(TCF_PERFCOUNTER6_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER6_LOW) + +START_REGISTER(TCF_PERFCOUNTER7_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER7_LOW) + +START_REGISTER(TCF_PERFCOUNTER8_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER8_LOW) + +START_REGISTER(TCF_PERFCOUNTER9_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER9_LOW) + +START_REGISTER(TCF_PERFCOUNTER10_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER10_LOW) + +START_REGISTER(TCF_PERFCOUNTER11_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER11_LOW) + +START_REGISTER(TCF_DEBUG) + GENERATE_FIELD(not_MH_TC_rtr, int) + GENERATE_FIELD(TC_MH_send, int) + GENERATE_FIELD(not_FG0_rtr, int) + GENERATE_FIELD(not_TCB_TCO_rtr, int) + GENERATE_FIELD(TCB_ff_stall, int) + GENERATE_FIELD(TCB_miss_stall, int) + GENERATE_FIELD(TCA_TCB_stall, int) + GENERATE_FIELD(PF0_stall, int) + GENERATE_FIELD(TP0_full, int) + GENERATE_FIELD(TPC_full, int) + GENERATE_FIELD(not_TPC_rtr, int) + GENERATE_FIELD(tca_state_rts, int) + GENERATE_FIELD(tca_rts, int) +END_REGISTER(TCF_DEBUG) + +START_REGISTER(TCA_FIFO_DEBUG) + GENERATE_FIELD(tp0_full, int) + GENERATE_FIELD(tpc_full, int) + GENERATE_FIELD(load_tpc_fifo, int) + GENERATE_FIELD(load_tp_fifos, int) + GENERATE_FIELD(FW_full, int) + GENERATE_FIELD(not_FW_rtr0, int) + GENERATE_FIELD(FW_rts0, int) + GENERATE_FIELD(not_FW_tpc_rtr, int) + GENERATE_FIELD(FW_tpc_rts, int) +END_REGISTER(TCA_FIFO_DEBUG) + +START_REGISTER(TCA_PROBE_DEBUG) + GENERATE_FIELD(ProbeFilter_stall, int) +END_REGISTER(TCA_PROBE_DEBUG) + +START_REGISTER(TCA_TPC_DEBUG) + GENERATE_FIELD(captue_state_rts, int) + GENERATE_FIELD(capture_tca_rts, int) +END_REGISTER(TCA_TPC_DEBUG) + +START_REGISTER(TCB_CORE_DEBUG) + GENERATE_FIELD(access512, int) + GENERATE_FIELD(tiled, int) + GENERATE_FIELD(opcode, int) + GENERATE_FIELD(format, int) + GENERATE_FIELD(sector_format, int) + GENERATE_FIELD(sector_format512, int) +END_REGISTER(TCB_CORE_DEBUG) + +START_REGISTER(TCB_TAG0_DEBUG) + GENERATE_FIELD(mem_read_cycle, int) + GENERATE_FIELD(tag_access_cycle, int) + GENERATE_FIELD(miss_stall, int) + GENERATE_FIELD(num_feee_lines, int) + GENERATE_FIELD(max_misses, int) +END_REGISTER(TCB_TAG0_DEBUG) + +START_REGISTER(TCB_TAG1_DEBUG) + GENERATE_FIELD(mem_read_cycle, int) + GENERATE_FIELD(tag_access_cycle, int) + GENERATE_FIELD(miss_stall, int) + GENERATE_FIELD(num_feee_lines, int) + GENERATE_FIELD(max_misses, int) +END_REGISTER(TCB_TAG1_DEBUG) + +START_REGISTER(TCB_TAG2_DEBUG) + GENERATE_FIELD(mem_read_cycle, int) + GENERATE_FIELD(tag_access_cycle, int) + GENERATE_FIELD(miss_stall, int) + GENERATE_FIELD(num_feee_lines, int) + GENERATE_FIELD(max_misses, int) +END_REGISTER(TCB_TAG2_DEBUG) + +START_REGISTER(TCB_TAG3_DEBUG) + GENERATE_FIELD(mem_read_cycle, int) + GENERATE_FIELD(tag_access_cycle, int) + GENERATE_FIELD(miss_stall, int) + GENERATE_FIELD(num_feee_lines, int) + GENERATE_FIELD(max_misses, int) +END_REGISTER(TCB_TAG3_DEBUG) + +START_REGISTER(TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG) + GENERATE_FIELD(left_done, int) + GENERATE_FIELD(fg0_sends_left, int) + GENERATE_FIELD(one_sector_to_go_left_q, int) + GENERATE_FIELD(no_sectors_to_go, int) + GENERATE_FIELD(update_left, int) + GENERATE_FIELD(sector_mask_left_count_q, int) + GENERATE_FIELD(sector_mask_left_q, int) + GENERATE_FIELD(valid_left_q, int) +END_REGISTER(TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG) + +START_REGISTER(TCB_FETCH_GEN_WALKER_DEBUG) + GENERATE_FIELD(quad_sel_left, int) + GENERATE_FIELD(set_sel_left, int) + GENERATE_FIELD(right_eq_left, int) + GENERATE_FIELD(ff_fg_type512, int) + GENERATE_FIELD(busy, int) + GENERATE_FIELD(setquads_to_send, int) +END_REGISTER(TCB_FETCH_GEN_WALKER_DEBUG) + +START_REGISTER(TCB_FETCH_GEN_PIPE0_DEBUG) + GENERATE_FIELD(tc0_arb_rts, int) + GENERATE_FIELD(ga_out_rts, int) + GENERATE_FIELD(tc_arb_format, int) + GENERATE_FIELD(tc_arb_fmsopcode, int) + GENERATE_FIELD(tc_arb_request_type, int) + GENERATE_FIELD(busy, int) + GENERATE_FIELD(fgo_busy, int) + GENERATE_FIELD(ga_busy, int) + GENERATE_FIELD(mc_sel_q, int) + GENERATE_FIELD(valid_q, int) + GENERATE_FIELD(arb_RTR, int) +END_REGISTER(TCB_FETCH_GEN_PIPE0_DEBUG) + +START_REGISTER(TCD_INPUT0_DEBUG) + GENERATE_FIELD(empty, int) + GENERATE_FIELD(full, int) + GENERATE_FIELD(valid_q1, int) + GENERATE_FIELD(cnt_q1, int) + GENERATE_FIELD(last_send_q1, int) + GENERATE_FIELD(ip_send, int) + GENERATE_FIELD(ipbuf_dxt_send, int) + GENERATE_FIELD(ipbuf_busy, int) +END_REGISTER(TCD_INPUT0_DEBUG) + +START_REGISTER(TCD_DEGAMMA_DEBUG) + GENERATE_FIELD(dgmm_ftfconv_dgmmen, int) + GENERATE_FIELD(dgmm_ctrl_dgmm8, int) + GENERATE_FIELD(dgmm_ctrl_last_send, int) + GENERATE_FIELD(dgmm_ctrl_send, int) + GENERATE_FIELD(dgmm_stall, int) + GENERATE_FIELD(dgmm_pstate, int) +END_REGISTER(TCD_DEGAMMA_DEBUG) + +START_REGISTER(TCD_DXTMUX_SCTARB_DEBUG) + GENERATE_FIELD(pstate, int) + GENERATE_FIELD(sctrmx_rtr, int) + GENERATE_FIELD(dxtc_rtr, int) + GENERATE_FIELD(sctrarb_multcyl_send, int) + GENERATE_FIELD(sctrmx0_sctrarb_rts, int) + GENERATE_FIELD(dxtc_sctrarb_send, int) + GENERATE_FIELD(dxtc_dgmmpd_last_send, int) + GENERATE_FIELD(dxtc_dgmmpd_send, int) + GENERATE_FIELD(dcmp_mux_send, int) +END_REGISTER(TCD_DXTMUX_SCTARB_DEBUG) + +START_REGISTER(TCD_DXTC_ARB_DEBUG) + GENERATE_FIELD(n0_stall, int) + GENERATE_FIELD(pstate, int) + GENERATE_FIELD(arb_dcmp01_last_send, int) + GENERATE_FIELD(arb_dcmp01_cnt, int) + GENERATE_FIELD(arb_dcmp01_sector, int) + GENERATE_FIELD(arb_dcmp01_cacheline, int) + GENERATE_FIELD(arb_dcmp01_format, int) + GENERATE_FIELD(arb_dcmp01_send, int) + GENERATE_FIELD(n0_dxt2_4_types, int) +END_REGISTER(TCD_DXTC_ARB_DEBUG) + +START_REGISTER(TCD_STALLS_DEBUG) + GENERATE_FIELD(not_multcyl_sctrarb_rtr, int) + GENERATE_FIELD(not_sctrmx0_sctrarb_rtr, int) + GENERATE_FIELD(not_dcmp0_arb_rtr, int) + GENERATE_FIELD(not_dgmmpd_dxtc_rtr, int) + GENERATE_FIELD(not_mux_dcmp_rtr, int) + GENERATE_FIELD(not_incoming_rtr, int) +END_REGISTER(TCD_STALLS_DEBUG) + +START_REGISTER(TCO_STALLS_DEBUG) + GENERATE_FIELD(quad0_sg_crd_RTR, int) + GENERATE_FIELD(quad0_rl_sg_RTR, int) + GENERATE_FIELD(quad0_TCO_TCB_rtr_d, int) +END_REGISTER(TCO_STALLS_DEBUG) + +START_REGISTER(TCO_QUAD0_DEBUG0) + GENERATE_FIELD(rl_sg_sector_format, int) + GENERATE_FIELD(rl_sg_end_of_sample, int) + GENERATE_FIELD(rl_sg_rtr, int) + GENERATE_FIELD(rl_sg_rts, int) + GENERATE_FIELD(sg_crd_end_of_sample, int) + GENERATE_FIELD(sg_crd_rtr, int) + GENERATE_FIELD(sg_crd_rts, int) + GENERATE_FIELD(stageN1_valid_q, int) + GENERATE_FIELD(read_cache_q, int) + GENERATE_FIELD(cache_read_RTR, int) + GENERATE_FIELD(all_sectors_written_set3, int) + GENERATE_FIELD(all_sectors_written_set2, int) + GENERATE_FIELD(all_sectors_written_set1, int) + GENERATE_FIELD(all_sectors_written_set0, int) + GENERATE_FIELD(busy, int) +END_REGISTER(TCO_QUAD0_DEBUG0) + +START_REGISTER(TCO_QUAD0_DEBUG1) + GENERATE_FIELD(fifo_busy, int) + GENERATE_FIELD(empty, int) + GENERATE_FIELD(full, int) + GENERATE_FIELD(write_enable, int) + GENERATE_FIELD(fifo_write_ptr, int) + GENERATE_FIELD(fifo_read_ptr, int) + GENERATE_FIELD(cache_read_busy, int) + GENERATE_FIELD(latency_fifo_busy, int) + GENERATE_FIELD(input_quad_busy, int) + GENERATE_FIELD(tco_quad_pipe_busy, int) + GENERATE_FIELD(TCB_TCO_rtr_d, int) + GENERATE_FIELD(TCB_TCO_xfc_q, int) + GENERATE_FIELD(rl_sg_rtr, int) + GENERATE_FIELD(rl_sg_rts, int) + GENERATE_FIELD(sg_crd_rtr, int) + GENERATE_FIELD(sg_crd_rts, int) + GENERATE_FIELD(TCO_TCB_read_xfc, int) +END_REGISTER(TCO_QUAD0_DEBUG1) + +START_REGISTER(SQ_GPR_MANAGEMENT) + GENERATE_FIELD(REG_DYNAMIC, int) + GENERATE_FIELD(REG_SIZE_PIX, int) + GENERATE_FIELD(REG_SIZE_VTX, int) +END_REGISTER(SQ_GPR_MANAGEMENT) + +START_REGISTER(SQ_FLOW_CONTROL) + GENERATE_FIELD(INPUT_ARBITRATION_POLICY, int) + GENERATE_FIELD(ONE_THREAD, int) + GENERATE_FIELD(ONE_ALU, int) + GENERATE_FIELD(CF_WR_BASE, hex) + GENERATE_FIELD(NO_PV_PS, int) + GENERATE_FIELD(NO_LOOP_EXIT, int) + GENERATE_FIELD(NO_CEXEC_OPTIMIZE, int) + GENERATE_FIELD(TEXTURE_ARBITRATION_POLICY, int) + GENERATE_FIELD(VC_ARBITRATION_POLICY, int) + GENERATE_FIELD(ALU_ARBITRATION_POLICY, int) + GENERATE_FIELD(NO_ARB_EJECT, int) + GENERATE_FIELD(NO_CFS_EJECT, int) + GENERATE_FIELD(POS_EXP_PRIORITY, int) + GENERATE_FIELD(NO_EARLY_THREAD_TERMINATION, int) + GENERATE_FIELD(PS_PREFETCH_COLOR_ALLOC, int) +END_REGISTER(SQ_FLOW_CONTROL) + +START_REGISTER(SQ_INST_STORE_MANAGMENT) + GENERATE_FIELD(INST_BASE_PIX, int) + GENERATE_FIELD(INST_BASE_VTX, int) +END_REGISTER(SQ_INST_STORE_MANAGMENT) + +START_REGISTER(SQ_RESOURCE_MANAGMENT) + GENERATE_FIELD(VTX_THREAD_BUF_ENTRIES, int) + GENERATE_FIELD(PIX_THREAD_BUF_ENTRIES, int) + GENERATE_FIELD(EXPORT_BUF_ENTRIES, int) +END_REGISTER(SQ_RESOURCE_MANAGMENT) + +START_REGISTER(SQ_EO_RT) + GENERATE_FIELD(EO_CONSTANTS_RT, int) + GENERATE_FIELD(EO_TSTATE_RT, int) +END_REGISTER(SQ_EO_RT) + +START_REGISTER(SQ_DEBUG_MISC) + GENERATE_FIELD(DB_ALUCST_SIZE, int) + GENERATE_FIELD(DB_TSTATE_SIZE, int) + GENERATE_FIELD(DB_READ_CTX, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(DB_READ_MEMORY, int) + GENERATE_FIELD(DB_WEN_MEMORY_0, int) + GENERATE_FIELD(DB_WEN_MEMORY_1, int) + GENERATE_FIELD(DB_WEN_MEMORY_2, int) + GENERATE_FIELD(DB_WEN_MEMORY_3, int) +END_REGISTER(SQ_DEBUG_MISC) + +START_REGISTER(SQ_ACTIVITY_METER_CNTL) + GENERATE_FIELD(TIMEBASE, int) + GENERATE_FIELD(THRESHOLD_LOW, int) + GENERATE_FIELD(THRESHOLD_HIGH, int) + GENERATE_FIELD(SPARE, int) +END_REGISTER(SQ_ACTIVITY_METER_CNTL) + +START_REGISTER(SQ_ACTIVITY_METER_STATUS) + GENERATE_FIELD(PERCENT_BUSY, int) +END_REGISTER(SQ_ACTIVITY_METER_STATUS) + +START_REGISTER(SQ_INPUT_ARB_PRIORITY) + GENERATE_FIELD(PC_AVAIL_WEIGHT, int) + GENERATE_FIELD(PC_AVAIL_SIGN, int) + GENERATE_FIELD(SX_AVAIL_WEIGHT, int) + GENERATE_FIELD(SX_AVAIL_SIGN, int) + GENERATE_FIELD(THRESHOLD, int) +END_REGISTER(SQ_INPUT_ARB_PRIORITY) + +START_REGISTER(SQ_THREAD_ARB_PRIORITY) + GENERATE_FIELD(PC_AVAIL_WEIGHT, int) + GENERATE_FIELD(PC_AVAIL_SIGN, int) + GENERATE_FIELD(SX_AVAIL_WEIGHT, int) + GENERATE_FIELD(SX_AVAIL_SIGN, int) + GENERATE_FIELD(THRESHOLD, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(VS_PRIORITIZE_SERIAL, int) + GENERATE_FIELD(PS_PRIORITIZE_SERIAL, int) + GENERATE_FIELD(USE_SERIAL_COUNT_THRESHOLD, int) +END_REGISTER(SQ_THREAD_ARB_PRIORITY) + +START_REGISTER(SQ_DEBUG_INPUT_FSM) + GENERATE_FIELD(VC_VSR_LD, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(VC_GPR_LD, int) + GENERATE_FIELD(PC_PISM, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(PC_AS, int) + GENERATE_FIELD(PC_INTERP_CNT, int) + GENERATE_FIELD(PC_GPR_SIZE, int) +END_REGISTER(SQ_DEBUG_INPUT_FSM) + +START_REGISTER(SQ_DEBUG_CONST_MGR_FSM) + GENERATE_FIELD(TEX_CONST_EVENT_STATE, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(ALU_CONST_EVENT_STATE, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(ALU_CONST_CNTX_VALID, int) + GENERATE_FIELD(TEX_CONST_CNTX_VALID, int) + GENERATE_FIELD(CNTX0_VTX_EVENT_DONE, int) + GENERATE_FIELD(CNTX0_PIX_EVENT_DONE, int) + GENERATE_FIELD(CNTX1_VTX_EVENT_DONE, int) + GENERATE_FIELD(CNTX1_PIX_EVENT_DONE, int) +END_REGISTER(SQ_DEBUG_CONST_MGR_FSM) + +START_REGISTER(SQ_DEBUG_TP_FSM) + GENERATE_FIELD(EX_TP, int) + GENERATE_FIELD(RESERVED0, int) + GENERATE_FIELD(CF_TP, int) + GENERATE_FIELD(IF_TP, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(TIS_TP, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(GS_TP, int) + GENERATE_FIELD(RESERVED3, int) + GENERATE_FIELD(FCR_TP, int) + GENERATE_FIELD(RESERVED4, int) + GENERATE_FIELD(FCS_TP, int) + GENERATE_FIELD(RESERVED5, int) + GENERATE_FIELD(ARB_TR_TP, int) +END_REGISTER(SQ_DEBUG_TP_FSM) + +START_REGISTER(SQ_DEBUG_FSM_ALU_0) + GENERATE_FIELD(EX_ALU_0, int) + GENERATE_FIELD(RESERVED0, int) + GENERATE_FIELD(CF_ALU_0, int) + GENERATE_FIELD(IF_ALU_0, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(DU1_ALU_0, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(DU0_ALU_0, int) + GENERATE_FIELD(RESERVED3, int) + GENERATE_FIELD(AIS_ALU_0, int) + GENERATE_FIELD(RESERVED4, int) + GENERATE_FIELD(ACS_ALU_0, int) + GENERATE_FIELD(RESERVED5, int) + GENERATE_FIELD(ARB_TR_ALU, int) +END_REGISTER(SQ_DEBUG_FSM_ALU_0) + +START_REGISTER(SQ_DEBUG_FSM_ALU_1) + GENERATE_FIELD(EX_ALU_0, int) + GENERATE_FIELD(RESERVED0, int) + GENERATE_FIELD(CF_ALU_0, int) + GENERATE_FIELD(IF_ALU_0, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(DU1_ALU_0, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(DU0_ALU_0, int) + GENERATE_FIELD(RESERVED3, int) + GENERATE_FIELD(AIS_ALU_0, int) + GENERATE_FIELD(RESERVED4, int) + GENERATE_FIELD(ACS_ALU_0, int) + GENERATE_FIELD(RESERVED5, int) + GENERATE_FIELD(ARB_TR_ALU, int) +END_REGISTER(SQ_DEBUG_FSM_ALU_1) + +START_REGISTER(SQ_DEBUG_EXP_ALLOC) + GENERATE_FIELD(POS_BUF_AVAIL, int) + GENERATE_FIELD(COLOR_BUF_AVAIL, int) + GENERATE_FIELD(EA_BUF_AVAIL, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(ALLOC_TBL_BUF_AVAIL, int) +END_REGISTER(SQ_DEBUG_EXP_ALLOC) + +START_REGISTER(SQ_DEBUG_PTR_BUFF) + GENERATE_FIELD(END_OF_BUFFER, int) + GENERATE_FIELD(DEALLOC_CNT, int) + GENERATE_FIELD(QUAL_NEW_VECTOR, int) + GENERATE_FIELD(EVENT_CONTEXT_ID, int) + GENERATE_FIELD(SC_EVENT_ID, int) + GENERATE_FIELD(QUAL_EVENT, int) + GENERATE_FIELD(PRIM_TYPE_POLYGON, int) + GENERATE_FIELD(EF_EMPTY, int) + GENERATE_FIELD(VTX_SYNC_CNT, int) +END_REGISTER(SQ_DEBUG_PTR_BUFF) + +START_REGISTER(SQ_DEBUG_GPR_VTX) + GENERATE_FIELD(VTX_TAIL_PTR, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(VTX_HEAD_PTR, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(VTX_MAX, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(VTX_FREE, int) +END_REGISTER(SQ_DEBUG_GPR_VTX) + +START_REGISTER(SQ_DEBUG_GPR_PIX) + GENERATE_FIELD(PIX_TAIL_PTR, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(PIX_HEAD_PTR, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(PIX_MAX, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(PIX_FREE, int) +END_REGISTER(SQ_DEBUG_GPR_PIX) + +START_REGISTER(SQ_DEBUG_TB_STATUS_SEL) + GENERATE_FIELD(VTX_TB_STATUS_REG_SEL, int) + GENERATE_FIELD(VTX_TB_STATE_MEM_DW_SEL, int) + GENERATE_FIELD(VTX_TB_STATE_MEM_RD_ADDR, int) + GENERATE_FIELD(VTX_TB_STATE_MEM_RD_EN, int) + GENERATE_FIELD(PIX_TB_STATE_MEM_RD_EN, int) + GENERATE_FIELD(DEBUG_BUS_TRIGGER_SEL, int) + GENERATE_FIELD(PIX_TB_STATUS_REG_SEL, int) + GENERATE_FIELD(PIX_TB_STATE_MEM_DW_SEL, int) + GENERATE_FIELD(PIX_TB_STATE_MEM_RD_ADDR, int) + GENERATE_FIELD(VC_THREAD_BUF_DLY, int) + GENERATE_FIELD(DISABLE_STRICT_CTX_SYNC, int) +END_REGISTER(SQ_DEBUG_TB_STATUS_SEL) + +START_REGISTER(SQ_DEBUG_VTX_TB_0) + GENERATE_FIELD(VTX_HEAD_PTR_Q, int) + GENERATE_FIELD(TAIL_PTR_Q, int) + GENERATE_FIELD(FULL_CNT_Q, int) + GENERATE_FIELD(NXT_POS_ALLOC_CNT, int) + GENERATE_FIELD(NXT_PC_ALLOC_CNT, int) + GENERATE_FIELD(SX_EVENT_FULL, int) + GENERATE_FIELD(BUSY_Q, int) +END_REGISTER(SQ_DEBUG_VTX_TB_0) + +START_REGISTER(SQ_DEBUG_VTX_TB_1) + GENERATE_FIELD(VS_DONE_PTR, int) +END_REGISTER(SQ_DEBUG_VTX_TB_1) + +START_REGISTER(SQ_DEBUG_VTX_TB_STATUS_REG) + GENERATE_FIELD(VS_STATUS_REG, int) +END_REGISTER(SQ_DEBUG_VTX_TB_STATUS_REG) + +START_REGISTER(SQ_DEBUG_VTX_TB_STATE_MEM) + GENERATE_FIELD(VS_STATE_MEM, int) +END_REGISTER(SQ_DEBUG_VTX_TB_STATE_MEM) + +START_REGISTER(SQ_DEBUG_PIX_TB_0) + GENERATE_FIELD(PIX_HEAD_PTR, int) + GENERATE_FIELD(TAIL_PTR, int) + GENERATE_FIELD(FULL_CNT, int) + GENERATE_FIELD(NXT_PIX_ALLOC_CNT, int) + GENERATE_FIELD(NXT_PIX_EXP_CNT, int) + GENERATE_FIELD(BUSY, int) +END_REGISTER(SQ_DEBUG_PIX_TB_0) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_0) + GENERATE_FIELD(PIX_TB_STATUS_REG_0, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_0) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_1) + GENERATE_FIELD(PIX_TB_STATUS_REG_1, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_1) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_2) + GENERATE_FIELD(PIX_TB_STATUS_REG_2, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_2) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_3) + GENERATE_FIELD(PIX_TB_STATUS_REG_3, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_3) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATE_MEM) + GENERATE_FIELD(PIX_TB_STATE_MEM, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATE_MEM) + +START_REGISTER(SQ_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, SQ_PERFCNT_SELECT) +END_REGISTER(SQ_PERFCOUNTER0_SELECT) + +START_REGISTER(SQ_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(SQ_PERFCOUNTER1_SELECT) + +START_REGISTER(SQ_PERFCOUNTER2_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(SQ_PERFCOUNTER2_SELECT) + +START_REGISTER(SQ_PERFCOUNTER3_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(SQ_PERFCOUNTER3_SELECT) + +START_REGISTER(SQ_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER0_LOW) + +START_REGISTER(SQ_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER0_HI) + +START_REGISTER(SQ_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER1_LOW) + +START_REGISTER(SQ_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER1_HI) + +START_REGISTER(SQ_PERFCOUNTER2_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER2_LOW) + +START_REGISTER(SQ_PERFCOUNTER2_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER2_HI) + +START_REGISTER(SQ_PERFCOUNTER3_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER3_LOW) + +START_REGISTER(SQ_PERFCOUNTER3_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER3_HI) + +START_REGISTER(SX_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, SX_PERFCNT_SELECT) +END_REGISTER(SX_PERFCOUNTER0_SELECT) + +START_REGISTER(SX_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SX_PERFCOUNTER0_LOW) + +START_REGISTER(SX_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SX_PERFCOUNTER0_HI) + +START_REGISTER(SQ_INSTRUCTION_ALU_0) + GENERATE_FIELD(VECTOR_RESULT, int) + GENERATE_FIELD(CST_0_ABS_MOD, Abs_modifier) + GENERATE_FIELD(LOW_PRECISION_16B_FP, int) + GENERATE_FIELD(SCALAR_RESULT, int) + GENERATE_FIELD(SST_0_ABS_MOD, int) + GENERATE_FIELD(EXPORT_DATA, Exporting) + GENERATE_FIELD(VECTOR_WRT_MSK, int) + GENERATE_FIELD(SCALAR_WRT_MSK, int) + GENERATE_FIELD(VECTOR_CLAMP, int) + GENERATE_FIELD(SCALAR_CLAMP, int) + GENERATE_FIELD(SCALAR_OPCODE, ScalarOpcode) +END_REGISTER(SQ_INSTRUCTION_ALU_0) + +START_REGISTER(SQ_INSTRUCTION_ALU_1) + GENERATE_FIELD(SRC_C_SWIZZLE_R, SwizzleType) + GENERATE_FIELD(SRC_C_SWIZZLE_G, SwizzleType) + GENERATE_FIELD(SRC_C_SWIZZLE_B, SwizzleType) + GENERATE_FIELD(SRC_C_SWIZZLE_A, SwizzleType) + GENERATE_FIELD(SRC_B_SWIZZLE_R, SwizzleType) + GENERATE_FIELD(SRC_B_SWIZZLE_G, SwizzleType) + GENERATE_FIELD(SRC_B_SWIZZLE_B, SwizzleType) + GENERATE_FIELD(SRC_B_SWIZZLE_A, SwizzleType) + GENERATE_FIELD(SRC_A_SWIZZLE_R, SwizzleType) + GENERATE_FIELD(SRC_A_SWIZZLE_G, SwizzleType) + GENERATE_FIELD(SRC_A_SWIZZLE_B, SwizzleType) + GENERATE_FIELD(SRC_A_SWIZZLE_A, SwizzleType) + GENERATE_FIELD(SRC_C_ARG_MOD, InputModifier) + GENERATE_FIELD(SRC_B_ARG_MOD, InputModifier) + GENERATE_FIELD(SRC_A_ARG_MOD, InputModifier) + GENERATE_FIELD(PRED_SELECT, PredicateSelect) + GENERATE_FIELD(RELATIVE_ADDR, int) + GENERATE_FIELD(CONST_1_REL_ABS, int) + GENERATE_FIELD(CONST_0_REL_ABS, int) +END_REGISTER(SQ_INSTRUCTION_ALU_1) + +START_REGISTER(SQ_INSTRUCTION_ALU_2) + GENERATE_FIELD(SRC_C_REG_PTR, int) + GENERATE_FIELD(REG_SELECT_C, OperandSelect1) + GENERATE_FIELD(REG_ABS_MOD_C, Abs_modifier) + GENERATE_FIELD(SRC_B_REG_PTR, int) + GENERATE_FIELD(REG_SELECT_B, OperandSelect1) + GENERATE_FIELD(REG_ABS_MOD_B, Abs_modifier) + GENERATE_FIELD(SRC_A_REG_PTR, int) + GENERATE_FIELD(REG_SELECT_A, OperandSelect1) + GENERATE_FIELD(REG_ABS_MOD_A, Abs_modifier) + GENERATE_FIELD(VECTOR_OPCODE, VectorOpcode) + GENERATE_FIELD(SRC_C_SEL, OperandSelect0) + GENERATE_FIELD(SRC_B_SEL, OperandSelect0) + GENERATE_FIELD(SRC_A_SEL, OperandSelect0) +END_REGISTER(SQ_INSTRUCTION_ALU_2) + +START_REGISTER(SQ_INSTRUCTION_CF_EXEC_0) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(COUNT, int) + GENERATE_FIELD(YIELD, int) + GENERATE_FIELD(INST_TYPE_0, Ressource_type) + GENERATE_FIELD(INST_SERIAL_0, Instruction_serial) + GENERATE_FIELD(INST_TYPE_1, Ressource_type) + GENERATE_FIELD(INST_SERIAL_1, Instruction_serial) + GENERATE_FIELD(INST_TYPE_2, Ressource_type) + GENERATE_FIELD(INST_SERIAL_2, Instruction_serial) + GENERATE_FIELD(INST_TYPE_3, Ressource_type) + GENERATE_FIELD(INST_SERIAL_3, Instruction_serial) + GENERATE_FIELD(INST_TYPE_4, Ressource_type) + GENERATE_FIELD(INST_SERIAL_4, Instruction_serial) + GENERATE_FIELD(INST_TYPE_5, Ressource_type) + GENERATE_FIELD(INST_SERIAL_5, Instruction_serial) + GENERATE_FIELD(INST_VC_0, VC_type) + GENERATE_FIELD(INST_VC_1, VC_type) + GENERATE_FIELD(INST_VC_2, VC_type) + GENERATE_FIELD(INST_VC_3, VC_type) +END_REGISTER(SQ_INSTRUCTION_CF_EXEC_0) + +START_REGISTER(SQ_INSTRUCTION_CF_EXEC_1) + GENERATE_FIELD(INST_VC_4, VC_type) + GENERATE_FIELD(INST_VC_5, VC_type) + GENERATE_FIELD(BOOL_ADDR, int) + GENERATE_FIELD(CONDITION, int) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(COUNT, int) + GENERATE_FIELD(YIELD, int) +END_REGISTER(SQ_INSTRUCTION_CF_EXEC_1) + +START_REGISTER(SQ_INSTRUCTION_CF_EXEC_2) + GENERATE_FIELD(INST_TYPE_0, Ressource_type) + GENERATE_FIELD(INST_SERIAL_0, Instruction_serial) + GENERATE_FIELD(INST_TYPE_1, Ressource_type) + GENERATE_FIELD(INST_SERIAL_1, Instruction_serial) + GENERATE_FIELD(INST_TYPE_2, Ressource_type) + GENERATE_FIELD(INST_SERIAL_2, Instruction_serial) + GENERATE_FIELD(INST_TYPE_3, Ressource_type) + GENERATE_FIELD(INST_SERIAL_3, Instruction_serial) + GENERATE_FIELD(INST_TYPE_4, Ressource_type) + GENERATE_FIELD(INST_SERIAL_4, Instruction_serial) + GENERATE_FIELD(INST_TYPE_5, Ressource_type) + GENERATE_FIELD(INST_SERIAL_5, Instruction_serial) + GENERATE_FIELD(INST_VC_0, VC_type) + GENERATE_FIELD(INST_VC_1, VC_type) + GENERATE_FIELD(INST_VC_2, VC_type) + GENERATE_FIELD(INST_VC_3, VC_type) + GENERATE_FIELD(INST_VC_4, VC_type) + GENERATE_FIELD(INST_VC_5, VC_type) + GENERATE_FIELD(BOOL_ADDR, int) + GENERATE_FIELD(CONDITION, int) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(OPCODE, CFOpcode) +END_REGISTER(SQ_INSTRUCTION_CF_EXEC_2) + +START_REGISTER(SQ_INSTRUCTION_CF_LOOP_0) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(RESERVED_0, int) + GENERATE_FIELD(LOOP_ID, int) + GENERATE_FIELD(RESERVED_1, int) +END_REGISTER(SQ_INSTRUCTION_CF_LOOP_0) + +START_REGISTER(SQ_INSTRUCTION_CF_LOOP_1) + GENERATE_FIELD(RESERVED_0, int) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(RESERVED_1, int) +END_REGISTER(SQ_INSTRUCTION_CF_LOOP_1) + +START_REGISTER(SQ_INSTRUCTION_CF_LOOP_2) + GENERATE_FIELD(LOOP_ID, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(OPCODE, CFOpcode) +END_REGISTER(SQ_INSTRUCTION_CF_LOOP_2) + +START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_0) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(RESERVED_0, int) + GENERATE_FIELD(FORCE_CALL, int) + GENERATE_FIELD(PREDICATED_JMP, int) + GENERATE_FIELD(RESERVED_1, int) +END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_0) + +START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_1) + GENERATE_FIELD(RESERVED_0, int) + GENERATE_FIELD(DIRECTION, int) + GENERATE_FIELD(BOOL_ADDR, int) + GENERATE_FIELD(CONDITION, int) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(RESERVED_1, int) + GENERATE_FIELD(FORCE_CALL, int) + GENERATE_FIELD(RESERVED_2, int) +END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_1) + +START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_2) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(DIRECTION, int) + GENERATE_FIELD(BOOL_ADDR, int) + GENERATE_FIELD(CONDITION, int) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(OPCODE, CFOpcode) +END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_2) + +START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_0) + GENERATE_FIELD(SIZE, int) + GENERATE_FIELD(RESERVED, int) +END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_0) + +START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_1) + GENERATE_FIELD(RESERVED_0, int) + GENERATE_FIELD(NO_SERIAL, int) + GENERATE_FIELD(BUFFER_SELECT, Allocation_type) + GENERATE_FIELD(ALLOC_MODE, int) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(SIZE, int) + GENERATE_FIELD(RESERVED_1, int) +END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_1) + +START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_2) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(NO_SERIAL, int) + GENERATE_FIELD(BUFFER_SELECT, Allocation_type) + GENERATE_FIELD(ALLOC_MODE, int) + GENERATE_FIELD(OPCODE, CFOpcode) +END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_2) + +START_REGISTER(SQ_INSTRUCTION_TFETCH_0) + GENERATE_FIELD(OPCODE, TexInstOpcode) + GENERATE_FIELD(SRC_GPR, int) + GENERATE_FIELD(SRC_GPR_AM, Addressmode) + GENERATE_FIELD(DST_GPR, int) + GENERATE_FIELD(DST_GPR_AM, Addressmode) + GENERATE_FIELD(FETCH_VALID_ONLY, int) + GENERATE_FIELD(CONST_INDEX, int) + GENERATE_FIELD(TX_COORD_DENORM, TexCoordDenorm) + GENERATE_FIELD(SRC_SEL_X, SrcSel) + GENERATE_FIELD(SRC_SEL_Y, SrcSel) + GENERATE_FIELD(SRC_SEL_Z, SrcSel) +END_REGISTER(SQ_INSTRUCTION_TFETCH_0) + +START_REGISTER(SQ_INSTRUCTION_TFETCH_1) + GENERATE_FIELD(DST_SEL_X, DstSel) + GENERATE_FIELD(DST_SEL_Y, DstSel) + GENERATE_FIELD(DST_SEL_Z, DstSel) + GENERATE_FIELD(DST_SEL_W, DstSel) + GENERATE_FIELD(MAG_FILTER, MagFilter) + GENERATE_FIELD(MIN_FILTER, MinFilter) + GENERATE_FIELD(MIP_FILTER, MipFilter) + GENERATE_FIELD(ANISO_FILTER, AnisoFilter) + GENERATE_FIELD(ARBITRARY_FILTER, ArbitraryFilter) + GENERATE_FIELD(VOL_MAG_FILTER, VolMagFilter) + GENERATE_FIELD(VOL_MIN_FILTER, VolMinFilter) + GENERATE_FIELD(USE_COMP_LOD, int) + GENERATE_FIELD(USE_REG_LOD, int) + GENERATE_FIELD(PRED_SELECT, PredSelect) +END_REGISTER(SQ_INSTRUCTION_TFETCH_1) + +START_REGISTER(SQ_INSTRUCTION_TFETCH_2) + GENERATE_FIELD(USE_REG_GRADIENTS, int) + GENERATE_FIELD(SAMPLE_LOCATION, SampleLocation) + GENERATE_FIELD(LOD_BIAS, int) + GENERATE_FIELD(UNUSED, int) + GENERATE_FIELD(OFFSET_X, int) + GENERATE_FIELD(OFFSET_Y, int) + GENERATE_FIELD(OFFSET_Z, int) + GENERATE_FIELD(PRED_CONDITION, int) +END_REGISTER(SQ_INSTRUCTION_TFETCH_2) + +START_REGISTER(SQ_INSTRUCTION_VFETCH_0) + GENERATE_FIELD(OPCODE, int) + GENERATE_FIELD(SRC_GPR, int) + GENERATE_FIELD(SRC_GPR_AM, int) + GENERATE_FIELD(DST_GPR, int) + GENERATE_FIELD(DST_GPR_AM, int) + GENERATE_FIELD(MUST_BE_ONE, int) + GENERATE_FIELD(CONST_INDEX, int) + GENERATE_FIELD(CONST_INDEX_SEL, int) + GENERATE_FIELD(SRC_SEL, int) +END_REGISTER(SQ_INSTRUCTION_VFETCH_0) + +START_REGISTER(SQ_INSTRUCTION_VFETCH_1) + GENERATE_FIELD(DST_SEL_X, int) + GENERATE_FIELD(DST_SEL_Y, int) + GENERATE_FIELD(DST_SEL_Z, int) + GENERATE_FIELD(DST_SEL_W, int) + GENERATE_FIELD(FORMAT_COMP_ALL, int) + GENERATE_FIELD(NUM_FORMAT_ALL, int) + GENERATE_FIELD(SIGNED_RF_MODE_ALL, int) + GENERATE_FIELD(DATA_FORMAT, int) + GENERATE_FIELD(EXP_ADJUST_ALL, int) + GENERATE_FIELD(PRED_SELECT, int) +END_REGISTER(SQ_INSTRUCTION_VFETCH_1) + +START_REGISTER(SQ_INSTRUCTION_VFETCH_2) + GENERATE_FIELD(STRIDE, int) + GENERATE_FIELD(OFFSET, int) + GENERATE_FIELD(PRED_CONDITION, int) +END_REGISTER(SQ_INSTRUCTION_VFETCH_2) + +START_REGISTER(SQ_CONSTANT_0) + GENERATE_FIELD(RED, float) +END_REGISTER(SQ_CONSTANT_0) + +START_REGISTER(SQ_CONSTANT_1) + GENERATE_FIELD(GREEN, float) +END_REGISTER(SQ_CONSTANT_1) + +START_REGISTER(SQ_CONSTANT_2) + GENERATE_FIELD(BLUE, float) +END_REGISTER(SQ_CONSTANT_2) + +START_REGISTER(SQ_CONSTANT_3) + GENERATE_FIELD(ALPHA, float) +END_REGISTER(SQ_CONSTANT_3) + +START_REGISTER(SQ_FETCH_0) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_0) + +START_REGISTER(SQ_FETCH_1) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_1) + +START_REGISTER(SQ_FETCH_2) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_2) + +START_REGISTER(SQ_FETCH_3) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_3) + +START_REGISTER(SQ_FETCH_4) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_4) + +START_REGISTER(SQ_FETCH_5) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_5) + +START_REGISTER(SQ_CONSTANT_VFETCH_0) + GENERATE_FIELD(TYPE, int) + GENERATE_FIELD(STATE, int) + GENERATE_FIELD(BASE_ADDRESS, hex) +END_REGISTER(SQ_CONSTANT_VFETCH_0) + +START_REGISTER(SQ_CONSTANT_VFETCH_1) + GENERATE_FIELD(ENDIAN_SWAP, int) + GENERATE_FIELD(LIMIT_ADDRESS, hex) +END_REGISTER(SQ_CONSTANT_VFETCH_1) + +START_REGISTER(SQ_CONSTANT_T2) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_CONSTANT_T2) + +START_REGISTER(SQ_CONSTANT_T3) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_CONSTANT_T3) + +START_REGISTER(SQ_CF_BOOLEANS) + GENERATE_FIELD(CF_BOOLEANS_0, int) + GENERATE_FIELD(CF_BOOLEANS_1, int) + GENERATE_FIELD(CF_BOOLEANS_2, int) + GENERATE_FIELD(CF_BOOLEANS_3, int) +END_REGISTER(SQ_CF_BOOLEANS) + +START_REGISTER(SQ_CF_LOOP) + GENERATE_FIELD(CF_LOOP_COUNT, int) + GENERATE_FIELD(CF_LOOP_START, int) + GENERATE_FIELD(CF_LOOP_STEP, int) +END_REGISTER(SQ_CF_LOOP) + +START_REGISTER(SQ_CONSTANT_RT_0) + GENERATE_FIELD(RED, float) +END_REGISTER(SQ_CONSTANT_RT_0) + +START_REGISTER(SQ_CONSTANT_RT_1) + GENERATE_FIELD(GREEN, float) +END_REGISTER(SQ_CONSTANT_RT_1) + +START_REGISTER(SQ_CONSTANT_RT_2) + GENERATE_FIELD(BLUE, float) +END_REGISTER(SQ_CONSTANT_RT_2) + +START_REGISTER(SQ_CONSTANT_RT_3) + GENERATE_FIELD(ALPHA, float) +END_REGISTER(SQ_CONSTANT_RT_3) + +START_REGISTER(SQ_FETCH_RT_0) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_0) + +START_REGISTER(SQ_FETCH_RT_1) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_1) + +START_REGISTER(SQ_FETCH_RT_2) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_2) + +START_REGISTER(SQ_FETCH_RT_3) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_3) + +START_REGISTER(SQ_FETCH_RT_4) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_4) + +START_REGISTER(SQ_FETCH_RT_5) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_5) + +START_REGISTER(SQ_CF_RT_BOOLEANS) + GENERATE_FIELD(CF_BOOLEANS_0, int) + GENERATE_FIELD(CF_BOOLEANS_1, int) + GENERATE_FIELD(CF_BOOLEANS_2, int) + GENERATE_FIELD(CF_BOOLEANS_3, int) +END_REGISTER(SQ_CF_RT_BOOLEANS) + +START_REGISTER(SQ_CF_RT_LOOP) + GENERATE_FIELD(CF_LOOP_COUNT, int) + GENERATE_FIELD(CF_LOOP_START, int) + GENERATE_FIELD(CF_LOOP_STEP, int) +END_REGISTER(SQ_CF_RT_LOOP) + +START_REGISTER(SQ_VS_PROGRAM) + GENERATE_FIELD(BASE, int) + GENERATE_FIELD(SIZE, int) +END_REGISTER(SQ_VS_PROGRAM) + +START_REGISTER(SQ_PS_PROGRAM) + GENERATE_FIELD(BASE, int) + GENERATE_FIELD(SIZE, int) +END_REGISTER(SQ_PS_PROGRAM) + +START_REGISTER(SQ_CF_PROGRAM_SIZE) + GENERATE_FIELD(VS_CF_SIZE, int) + GENERATE_FIELD(PS_CF_SIZE, int) +END_REGISTER(SQ_CF_PROGRAM_SIZE) + +START_REGISTER(SQ_INTERPOLATOR_CNTL) + GENERATE_FIELD(PARAM_SHADE, ParamShade) + GENERATE_FIELD(SAMPLING_PATTERN, SamplingPattern) +END_REGISTER(SQ_INTERPOLATOR_CNTL) + +START_REGISTER(SQ_PROGRAM_CNTL) + GENERATE_FIELD(VS_NUM_REG, intMinusOne) + GENERATE_FIELD(PS_NUM_REG, intMinusOne) + GENERATE_FIELD(VS_RESOURCE, int) + GENERATE_FIELD(PS_RESOURCE, int) + GENERATE_FIELD(PARAM_GEN, int) + GENERATE_FIELD(GEN_INDEX_PIX, int) + GENERATE_FIELD(VS_EXPORT_COUNT, intMinusOne) + GENERATE_FIELD(VS_EXPORT_MODE, VertexMode) + GENERATE_FIELD(PS_EXPORT_MODE, int) + GENERATE_FIELD(GEN_INDEX_VTX, int) +END_REGISTER(SQ_PROGRAM_CNTL) + +START_REGISTER(SQ_WRAPPING_0) + GENERATE_FIELD(PARAM_WRAP_0, hex) + GENERATE_FIELD(PARAM_WRAP_1, hex) + GENERATE_FIELD(PARAM_WRAP_2, hex) + GENERATE_FIELD(PARAM_WRAP_3, hex) + GENERATE_FIELD(PARAM_WRAP_4, hex) + GENERATE_FIELD(PARAM_WRAP_5, hex) + GENERATE_FIELD(PARAM_WRAP_6, hex) + GENERATE_FIELD(PARAM_WRAP_7, hex) +END_REGISTER(SQ_WRAPPING_0) + +START_REGISTER(SQ_WRAPPING_1) + GENERATE_FIELD(PARAM_WRAP_8, hex) + GENERATE_FIELD(PARAM_WRAP_9, hex) + GENERATE_FIELD(PARAM_WRAP_10, hex) + GENERATE_FIELD(PARAM_WRAP_11, hex) + GENERATE_FIELD(PARAM_WRAP_12, hex) + GENERATE_FIELD(PARAM_WRAP_13, hex) + GENERATE_FIELD(PARAM_WRAP_14, hex) + GENERATE_FIELD(PARAM_WRAP_15, hex) +END_REGISTER(SQ_WRAPPING_1) + +START_REGISTER(SQ_VS_CONST) + GENERATE_FIELD(BASE, int) + GENERATE_FIELD(SIZE, int) +END_REGISTER(SQ_VS_CONST) + +START_REGISTER(SQ_PS_CONST) + GENERATE_FIELD(BASE, int) + GENERATE_FIELD(SIZE, int) +END_REGISTER(SQ_PS_CONST) + +START_REGISTER(SQ_CONTEXT_MISC) + GENERATE_FIELD(INST_PRED_OPTIMIZE, int) + GENERATE_FIELD(SC_OUTPUT_SCREEN_XY, int) + GENERATE_FIELD(SC_SAMPLE_CNTL, Sample_Cntl) + GENERATE_FIELD(PARAM_GEN_POS, int) + GENERATE_FIELD(PERFCOUNTER_REF, int) + GENERATE_FIELD(YEILD_OPTIMIZE, int) + GENERATE_FIELD(TX_CACHE_SEL, int) +END_REGISTER(SQ_CONTEXT_MISC) + +START_REGISTER(SQ_CF_RD_BASE) + GENERATE_FIELD(RD_BASE, hex) +END_REGISTER(SQ_CF_RD_BASE) + +START_REGISTER(SQ_DEBUG_MISC_0) + GENERATE_FIELD(DB_PROB_ON, int) + GENERATE_FIELD(DB_PROB_BREAK, int) + GENERATE_FIELD(DB_PROB_ADDR, int) + GENERATE_FIELD(DB_PROB_COUNT, int) +END_REGISTER(SQ_DEBUG_MISC_0) + +START_REGISTER(SQ_DEBUG_MISC_1) + GENERATE_FIELD(DB_ON_PIX, int) + GENERATE_FIELD(DB_ON_VTX, int) + GENERATE_FIELD(DB_INST_COUNT, int) + GENERATE_FIELD(DB_BREAK_ADDR, int) +END_REGISTER(SQ_DEBUG_MISC_1) + +START_REGISTER(MH_ARBITER_CONFIG) + GENERATE_FIELD(SAME_PAGE_LIMIT, int) + GENERATE_FIELD(SAME_PAGE_GRANULARITY, int) + GENERATE_FIELD(L1_ARB_ENABLE, bool) + GENERATE_FIELD(L1_ARB_HOLD_ENABLE, int) + GENERATE_FIELD(L2_ARB_CONTROL, int) + GENERATE_FIELD(PAGE_SIZE, int) + GENERATE_FIELD(TC_REORDER_ENABLE, bool) + GENERATE_FIELD(TC_ARB_HOLD_ENABLE, bool) + GENERATE_FIELD(IN_FLIGHT_LIMIT_ENABLE, bool) + GENERATE_FIELD(IN_FLIGHT_LIMIT, int) + GENERATE_FIELD(CP_CLNT_ENABLE, bool) + GENERATE_FIELD(VGT_CLNT_ENABLE, bool) + GENERATE_FIELD(TC_CLNT_ENABLE, bool) + GENERATE_FIELD(RB_CLNT_ENABLE, bool) +END_REGISTER(MH_ARBITER_CONFIG) + +START_REGISTER(MH_CLNT_AXI_ID_REUSE) + GENERATE_FIELD(CPw_ID, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(RBw_ID, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(MMUr_ID, int) +END_REGISTER(MH_CLNT_AXI_ID_REUSE) + +START_REGISTER(MH_INTERRUPT_MASK) + GENERATE_FIELD(AXI_READ_ERROR, bool) + GENERATE_FIELD(AXI_WRITE_ERROR, bool) + GENERATE_FIELD(MMU_PAGE_FAULT, bool) +END_REGISTER(MH_INTERRUPT_MASK) + +START_REGISTER(MH_INTERRUPT_STATUS) + GENERATE_FIELD(AXI_READ_ERROR, int) + GENERATE_FIELD(AXI_WRITE_ERROR, int) + GENERATE_FIELD(MMU_PAGE_FAULT, int) +END_REGISTER(MH_INTERRUPT_STATUS) + +START_REGISTER(MH_INTERRUPT_CLEAR) + GENERATE_FIELD(AXI_READ_ERROR, int) + GENERATE_FIELD(AXI_WRITE_ERROR, int) + GENERATE_FIELD(MMU_PAGE_FAULT, int) +END_REGISTER(MH_INTERRUPT_CLEAR) + +START_REGISTER(MH_AXI_ERROR) + GENERATE_FIELD(AXI_READ_ID, int) + GENERATE_FIELD(AXI_READ_ERROR, int) + GENERATE_FIELD(AXI_WRITE_ID, int) + GENERATE_FIELD(AXI_WRITE_ERROR, int) +END_REGISTER(MH_AXI_ERROR) + +START_REGISTER(MH_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, MhPerfEncode) +END_REGISTER(MH_PERFCOUNTER0_SELECT) + +START_REGISTER(MH_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_SEL, MhPerfEncode) +END_REGISTER(MH_PERFCOUNTER1_SELECT) + +START_REGISTER(MH_PERFCOUNTER0_CONFIG) + GENERATE_FIELD(N_VALUE, int) +END_REGISTER(MH_PERFCOUNTER0_CONFIG) + +START_REGISTER(MH_PERFCOUNTER1_CONFIG) + GENERATE_FIELD(N_VALUE, int) +END_REGISTER(MH_PERFCOUNTER1_CONFIG) + +START_REGISTER(MH_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNTER_LOW, int) +END_REGISTER(MH_PERFCOUNTER0_LOW) + +START_REGISTER(MH_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERF_COUNTER_LOW, int) +END_REGISTER(MH_PERFCOUNTER1_LOW) + +START_REGISTER(MH_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNTER_HI, int) +END_REGISTER(MH_PERFCOUNTER0_HI) + +START_REGISTER(MH_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNTER_HI, int) +END_REGISTER(MH_PERFCOUNTER1_HI) + +START_REGISTER(MH_DEBUG_CTRL) + GENERATE_FIELD(INDEX, int) +END_REGISTER(MH_DEBUG_CTRL) + +START_REGISTER(MH_DEBUG_DATA) + GENERATE_FIELD(DATA, int) +END_REGISTER(MH_DEBUG_DATA) + +START_REGISTER(MH_MMU_CONFIG) + GENERATE_FIELD(MMU_ENABLE, bool) + GENERATE_FIELD(SPLIT_MODE_ENABLE, bool) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(RB_W_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_W_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R0_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R1_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R2_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R3_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R4_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(VGT_R0_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(VGT_R1_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(TC_R_CLNT_BEHAVIOR, MmuClntBeh) +END_REGISTER(MH_MMU_CONFIG) + +START_REGISTER(MH_MMU_VA_RANGE) + GENERATE_FIELD(NUM_64KB_REGIONS, int) + GENERATE_FIELD(VA_BASE, int) +END_REGISTER(MH_MMU_VA_RANGE) + +START_REGISTER(MH_MMU_PT_BASE) + GENERATE_FIELD(PT_BASE, int) +END_REGISTER(MH_MMU_PT_BASE) + +START_REGISTER(MH_MMU_PAGE_FAULT) + GENERATE_FIELD(PAGE_FAULT, int) + GENERATE_FIELD(OP_TYPE, int) + GENERATE_FIELD(CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(AXI_ID, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(MPU_ADDRESS_OUT_OF_RANGE, int) + GENERATE_FIELD(ADDRESS_OUT_OF_RANGE, int) + GENERATE_FIELD(READ_PROTECTION_ERROR, int) + GENERATE_FIELD(WRITE_PROTECTION_ERROR, int) + GENERATE_FIELD(REQ_VA, int) +END_REGISTER(MH_MMU_PAGE_FAULT) + +START_REGISTER(MH_MMU_TRAN_ERROR) + GENERATE_FIELD(TRAN_ERROR, int) +END_REGISTER(MH_MMU_TRAN_ERROR) + +START_REGISTER(MH_MMU_INVALIDATE) + GENERATE_FIELD(INVALIDATE_ALL, int) + GENERATE_FIELD(INVALIDATE_TC, int) +END_REGISTER(MH_MMU_INVALIDATE) + +START_REGISTER(MH_MMU_MPU_BASE) + GENERATE_FIELD(MPU_BASE, int) +END_REGISTER(MH_MMU_MPU_BASE) + +START_REGISTER(MH_MMU_MPU_END) + GENERATE_FIELD(MPU_END, int) +END_REGISTER(MH_MMU_MPU_END) + +START_REGISTER(WAIT_UNTIL) + GENERATE_FIELD(WAIT_RE_VSYNC, int) + GENERATE_FIELD(WAIT_FE_VSYNC, int) + GENERATE_FIELD(WAIT_VSYNC, int) + GENERATE_FIELD(WAIT_DSPLY_ID0, int) + GENERATE_FIELD(WAIT_DSPLY_ID1, int) + GENERATE_FIELD(WAIT_DSPLY_ID2, int) + GENERATE_FIELD(WAIT_CMDFIFO, int) + GENERATE_FIELD(WAIT_2D_IDLE, int) + GENERATE_FIELD(WAIT_3D_IDLE, int) + GENERATE_FIELD(WAIT_2D_IDLECLEAN, int) + GENERATE_FIELD(WAIT_3D_IDLECLEAN, int) + GENERATE_FIELD(CMDFIFO_ENTRIES, int) +END_REGISTER(WAIT_UNTIL) + +START_REGISTER(RBBM_ISYNC_CNTL) + GENERATE_FIELD(ISYNC_WAIT_IDLEGUI, int) + GENERATE_FIELD(ISYNC_CPSCRATCH_IDLEGUI, int) +END_REGISTER(RBBM_ISYNC_CNTL) + +START_REGISTER(RBBM_STATUS) + GENERATE_FIELD(CMDFIFO_AVAIL, int) + GENERATE_FIELD(TC_BUSY, int) + GENERATE_FIELD(HIRQ_PENDING, int) + GENERATE_FIELD(CPRQ_PENDING, int) + GENERATE_FIELD(CFRQ_PENDING, int) + GENERATE_FIELD(PFRQ_PENDING, int) + GENERATE_FIELD(VGT_BUSY_NO_DMA, int) + GENERATE_FIELD(RBBM_WU_BUSY, int) + GENERATE_FIELD(CP_NRT_BUSY, int) + GENERATE_FIELD(MH_BUSY, int) + GENERATE_FIELD(MH_COHERENCY_BUSY, int) + GENERATE_FIELD(SX_BUSY, int) + GENERATE_FIELD(TPC_BUSY, int) + GENERATE_FIELD(SC_CNTX_BUSY, int) + GENERATE_FIELD(PA_BUSY, int) + GENERATE_FIELD(VGT_BUSY, int) + GENERATE_FIELD(SQ_CNTX17_BUSY, int) + GENERATE_FIELD(SQ_CNTX0_BUSY, int) + GENERATE_FIELD(RB_CNTX_BUSY, int) + GENERATE_FIELD(GUI_ACTIVE, int) +END_REGISTER(RBBM_STATUS) + +START_REGISTER(RBBM_DSPLY) + GENERATE_FIELD(DISPLAY_ID0_ACTIVE, int) + GENERATE_FIELD(DISPLAY_ID1_ACTIVE, int) + GENERATE_FIELD(DISPLAY_ID2_ACTIVE, int) + GENERATE_FIELD(VSYNC_ACTIVE, int) + GENERATE_FIELD(USE_DISPLAY_ID0, int) + GENERATE_FIELD(USE_DISPLAY_ID1, int) + GENERATE_FIELD(USE_DISPLAY_ID2, int) + GENERATE_FIELD(SW_CNTL, int) + GENERATE_FIELD(NUM_BUFS, int) +END_REGISTER(RBBM_DSPLY) + +START_REGISTER(RBBM_RENDER_LATEST) + GENERATE_FIELD(BUFFER_ID, int) +END_REGISTER(RBBM_RENDER_LATEST) + +START_REGISTER(RBBM_RTL_RELEASE) + GENERATE_FIELD(CHANGELIST, int) +END_REGISTER(RBBM_RTL_RELEASE) + +START_REGISTER(RBBM_PATCH_RELEASE) + GENERATE_FIELD(PATCH_REVISION, int) + GENERATE_FIELD(PATCH_SELECTION, int) + GENERATE_FIELD(CUSTOMER_ID, int) +END_REGISTER(RBBM_PATCH_RELEASE) + +START_REGISTER(RBBM_AUXILIARY_CONFIG) + GENERATE_FIELD(RESERVED, int) +END_REGISTER(RBBM_AUXILIARY_CONFIG) + +START_REGISTER(RBBM_PERIPHID0) + GENERATE_FIELD(PARTNUMBER0, int) +END_REGISTER(RBBM_PERIPHID0) + +START_REGISTER(RBBM_PERIPHID1) + GENERATE_FIELD(PARTNUMBER1, int) + GENERATE_FIELD(DESIGNER0, int) +END_REGISTER(RBBM_PERIPHID1) + +START_REGISTER(RBBM_PERIPHID2) + GENERATE_FIELD(DESIGNER1, int) + GENERATE_FIELD(REVISION, int) +END_REGISTER(RBBM_PERIPHID2) + +START_REGISTER(RBBM_PERIPHID3) + GENERATE_FIELD(RBBM_HOST_INTERFACE, int) + GENERATE_FIELD(GARB_SLAVE_INTERFACE, int) + GENERATE_FIELD(MH_INTERFACE, int) + GENERATE_FIELD(CONTINUATION, int) +END_REGISTER(RBBM_PERIPHID3) + +START_REGISTER(RBBM_CNTL) + GENERATE_FIELD(READ_TIMEOUT, int) + GENERATE_FIELD(REGCLK_DEASSERT_TIME, int) +END_REGISTER(RBBM_CNTL) + +START_REGISTER(RBBM_SKEW_CNTL) + GENERATE_FIELD(SKEW_TOP_THRESHOLD, int) + GENERATE_FIELD(SKEW_COUNT, int) +END_REGISTER(RBBM_SKEW_CNTL) + +START_REGISTER(RBBM_SOFT_RESET) + GENERATE_FIELD(SOFT_RESET_CP, int) + GENERATE_FIELD(SOFT_RESET_PA, int) + GENERATE_FIELD(SOFT_RESET_MH, int) + GENERATE_FIELD(SOFT_RESET_BC, int) + GENERATE_FIELD(SOFT_RESET_SQ, int) + GENERATE_FIELD(SOFT_RESET_SX, int) + GENERATE_FIELD(SOFT_RESET_CIB, int) + GENERATE_FIELD(SOFT_RESET_SC, int) + GENERATE_FIELD(SOFT_RESET_VGT, int) +END_REGISTER(RBBM_SOFT_RESET) + +START_REGISTER(RBBM_PM_OVERRIDE1) + GENERATE_FIELD(RBBM_AHBCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SC_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SC_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SP_TOP_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SP_V0_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SQ_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SQ_REG_FIFOS_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SQ_CONST_MEM_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SQ_SQ_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SX_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SX_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCM_TCO_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCM_TCM_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCM_TCD_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCM_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TPC_TPC_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TPC_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCF_TCA_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCF_TCB_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCF_TCB_READ_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TP_TP_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TP_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(CP_G_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(CP_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(CP_G_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SPI_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(RB_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(RB_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(MH_MH_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(MH_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(MH_MMU_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(MH_TCROQ_SCLK_PM_OVERRIDE, int) +END_REGISTER(RBBM_PM_OVERRIDE1) + +START_REGISTER(RBBM_PM_OVERRIDE2) + GENERATE_FIELD(PA_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(PA_PA_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(PA_AG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(VGT_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(VGT_FIFOS_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(VGT_VGT_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(DEBUG_PERF_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(PERM_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(GC_GA_GMEM0_PM_OVERRIDE, int) + GENERATE_FIELD(GC_GA_GMEM1_PM_OVERRIDE, int) + GENERATE_FIELD(GC_GA_GMEM2_PM_OVERRIDE, int) + GENERATE_FIELD(GC_GA_GMEM3_PM_OVERRIDE, int) +END_REGISTER(RBBM_PM_OVERRIDE2) + +START_REGISTER(GC_SYS_IDLE) + GENERATE_FIELD(GC_SYS_IDLE_DELAY, int) + GENERATE_FIELD(GC_SYS_IDLE_OVERRIDE, int) +END_REGISTER(GC_SYS_IDLE) + +START_REGISTER(NQWAIT_UNTIL) + GENERATE_FIELD(WAIT_GUI_IDLE, int) +END_REGISTER(NQWAIT_UNTIL) + +START_REGISTER(RBBM_DEBUG) + GENERATE_FIELD(IGNORE_RTR, int) + GENERATE_FIELD(IGNORE_CP_SCHED_WU, int) + GENERATE_FIELD(IGNORE_CP_SCHED_ISYNC, int) + GENERATE_FIELD(IGNORE_CP_SCHED_NQ_HI, int) + GENERATE_FIELD(HYSTERESIS_NRT_GUI_ACTIVE, int) + GENERATE_FIELD(IGNORE_RTR_FOR_HI, int) + GENERATE_FIELD(IGNORE_CP_RBBM_NRTRTR_FOR_HI, int) + GENERATE_FIELD(IGNORE_VGT_RBBM_NRTRTR_FOR_HI, int) + GENERATE_FIELD(IGNORE_SQ_RBBM_NRTRTR_FOR_HI, int) + GENERATE_FIELD(CP_RBBM_NRTRTR, int) + GENERATE_FIELD(VGT_RBBM_NRTRTR, int) + GENERATE_FIELD(SQ_RBBM_NRTRTR, int) + GENERATE_FIELD(CLIENTS_FOR_NRT_RTR_FOR_HI, int) + GENERATE_FIELD(CLIENTS_FOR_NRT_RTR, int) + GENERATE_FIELD(IGNORE_SX_RBBM_BUSY, int) +END_REGISTER(RBBM_DEBUG) + +START_REGISTER(RBBM_READ_ERROR) + GENERATE_FIELD(READ_ADDRESS, int) + GENERATE_FIELD(READ_REQUESTER, int) + GENERATE_FIELD(READ_ERROR, int) +END_REGISTER(RBBM_READ_ERROR) + +START_REGISTER(RBBM_WAIT_IDLE_CLOCKS) + GENERATE_FIELD(WAIT_IDLE_CLOCKS_NRT, int) +END_REGISTER(RBBM_WAIT_IDLE_CLOCKS) + +START_REGISTER(RBBM_INT_CNTL) + GENERATE_FIELD(RDERR_INT_MASK, int) + GENERATE_FIELD(DISPLAY_UPDATE_INT_MASK, int) + GENERATE_FIELD(GUI_IDLE_INT_MASK, int) +END_REGISTER(RBBM_INT_CNTL) + +START_REGISTER(RBBM_INT_STATUS) + GENERATE_FIELD(RDERR_INT_STAT, int) + GENERATE_FIELD(DISPLAY_UPDATE_INT_STAT, int) + GENERATE_FIELD(GUI_IDLE_INT_STAT, int) +END_REGISTER(RBBM_INT_STATUS) + +START_REGISTER(RBBM_INT_ACK) + GENERATE_FIELD(RDERR_INT_ACK, int) + GENERATE_FIELD(DISPLAY_UPDATE_INT_ACK, int) + GENERATE_FIELD(GUI_IDLE_INT_ACK, int) +END_REGISTER(RBBM_INT_ACK) + +START_REGISTER(MASTER_INT_SIGNAL) + GENERATE_FIELD(MH_INT_STAT, int) + GENERATE_FIELD(CP_INT_STAT, int) + GENERATE_FIELD(RBBM_INT_STAT, int) +END_REGISTER(MASTER_INT_SIGNAL) + +START_REGISTER(RBBM_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_COUNT1_SEL, RBBM_PERFCOUNT1_SEL) +END_REGISTER(RBBM_PERFCOUNTER1_SELECT) + +START_REGISTER(RBBM_PERFCOUNTER1_LO) + GENERATE_FIELD(PERF_COUNT1_LO, int) +END_REGISTER(RBBM_PERFCOUNTER1_LO) + +START_REGISTER(RBBM_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNT1_HI, int) +END_REGISTER(RBBM_PERFCOUNTER1_HI) + +START_REGISTER(CP_RB_BASE) + GENERATE_FIELD(RB_BASE, int) +END_REGISTER(CP_RB_BASE) + +START_REGISTER(CP_RB_CNTL) + GENERATE_FIELD(RB_BUFSZ, int) + GENERATE_FIELD(RB_BLKSZ, int) + GENERATE_FIELD(BUF_SWAP, int) + GENERATE_FIELD(RB_POLL_EN, int) + GENERATE_FIELD(RB_NO_UPDATE, int) + GENERATE_FIELD(RB_RPTR_WR_ENA, int) +END_REGISTER(CP_RB_CNTL) + +START_REGISTER(CP_RB_RPTR_ADDR) + GENERATE_FIELD(RB_RPTR_SWAP, int) + GENERATE_FIELD(RB_RPTR_ADDR, int) +END_REGISTER(CP_RB_RPTR_ADDR) + +START_REGISTER(CP_RB_RPTR) + GENERATE_FIELD(RB_RPTR, int) +END_REGISTER(CP_RB_RPTR) + +START_REGISTER(CP_RB_RPTR_WR) + GENERATE_FIELD(RB_RPTR_WR, int) +END_REGISTER(CP_RB_RPTR_WR) + +START_REGISTER(CP_RB_WPTR) + GENERATE_FIELD(RB_WPTR, int) +END_REGISTER(CP_RB_WPTR) + +START_REGISTER(CP_RB_WPTR_DELAY) + GENERATE_FIELD(PRE_WRITE_TIMER, int) + GENERATE_FIELD(PRE_WRITE_LIMIT, int) +END_REGISTER(CP_RB_WPTR_DELAY) + +START_REGISTER(CP_RB_WPTR_BASE) + GENERATE_FIELD(RB_WPTR_SWAP, int) + GENERATE_FIELD(RB_WPTR_BASE, int) +END_REGISTER(CP_RB_WPTR_BASE) + +START_REGISTER(CP_IB1_BASE) + GENERATE_FIELD(IB1_BASE, int) +END_REGISTER(CP_IB1_BASE) + +START_REGISTER(CP_IB1_BUFSZ) + GENERATE_FIELD(IB1_BUFSZ, int) +END_REGISTER(CP_IB1_BUFSZ) + +START_REGISTER(CP_IB2_BASE) + GENERATE_FIELD(IB2_BASE, int) +END_REGISTER(CP_IB2_BASE) + +START_REGISTER(CP_IB2_BUFSZ) + GENERATE_FIELD(IB2_BUFSZ, int) +END_REGISTER(CP_IB2_BUFSZ) + +START_REGISTER(CP_ST_BASE) + GENERATE_FIELD(ST_BASE, int) +END_REGISTER(CP_ST_BASE) + +START_REGISTER(CP_ST_BUFSZ) + GENERATE_FIELD(ST_BUFSZ, int) +END_REGISTER(CP_ST_BUFSZ) + +START_REGISTER(CP_QUEUE_THRESHOLDS) + GENERATE_FIELD(CSQ_IB1_START, int) + GENERATE_FIELD(CSQ_IB2_START, int) + GENERATE_FIELD(CSQ_ST_START, int) +END_REGISTER(CP_QUEUE_THRESHOLDS) + +START_REGISTER(CP_MEQ_THRESHOLDS) + GENERATE_FIELD(MEQ_END, int) + GENERATE_FIELD(ROQ_END, int) +END_REGISTER(CP_MEQ_THRESHOLDS) + +START_REGISTER(CP_CSQ_AVAIL) + GENERATE_FIELD(CSQ_CNT_RING, int) + GENERATE_FIELD(CSQ_CNT_IB1, int) + GENERATE_FIELD(CSQ_CNT_IB2, int) +END_REGISTER(CP_CSQ_AVAIL) + +START_REGISTER(CP_STQ_AVAIL) + GENERATE_FIELD(STQ_CNT_ST, int) +END_REGISTER(CP_STQ_AVAIL) + +START_REGISTER(CP_MEQ_AVAIL) + GENERATE_FIELD(MEQ_CNT, int) +END_REGISTER(CP_MEQ_AVAIL) + +START_REGISTER(CP_CSQ_RB_STAT) + GENERATE_FIELD(CSQ_RPTR_PRIMARY, int) + GENERATE_FIELD(CSQ_WPTR_PRIMARY, int) +END_REGISTER(CP_CSQ_RB_STAT) + +START_REGISTER(CP_CSQ_IB1_STAT) + GENERATE_FIELD(CSQ_RPTR_INDIRECT1, int) + GENERATE_FIELD(CSQ_WPTR_INDIRECT1, int) +END_REGISTER(CP_CSQ_IB1_STAT) + +START_REGISTER(CP_CSQ_IB2_STAT) + GENERATE_FIELD(CSQ_RPTR_INDIRECT2, int) + GENERATE_FIELD(CSQ_WPTR_INDIRECT2, int) +END_REGISTER(CP_CSQ_IB2_STAT) + +START_REGISTER(CP_NON_PREFETCH_CNTRS) + GENERATE_FIELD(IB1_COUNTER, int) + GENERATE_FIELD(IB2_COUNTER, int) +END_REGISTER(CP_NON_PREFETCH_CNTRS) + +START_REGISTER(CP_STQ_ST_STAT) + GENERATE_FIELD(STQ_RPTR_ST, int) + GENERATE_FIELD(STQ_WPTR_ST, int) +END_REGISTER(CP_STQ_ST_STAT) + +START_REGISTER(CP_MEQ_STAT) + GENERATE_FIELD(MEQ_RPTR, int) + GENERATE_FIELD(MEQ_WPTR, int) +END_REGISTER(CP_MEQ_STAT) + +START_REGISTER(CP_MIU_TAG_STAT) + GENERATE_FIELD(TAG_0_STAT, int) + GENERATE_FIELD(TAG_1_STAT, int) + GENERATE_FIELD(TAG_2_STAT, int) + GENERATE_FIELD(TAG_3_STAT, int) + GENERATE_FIELD(TAG_4_STAT, int) + GENERATE_FIELD(TAG_5_STAT, int) + GENERATE_FIELD(TAG_6_STAT, int) + GENERATE_FIELD(TAG_7_STAT, int) + GENERATE_FIELD(TAG_8_STAT, int) + GENERATE_FIELD(TAG_9_STAT, int) + GENERATE_FIELD(TAG_10_STAT, int) + GENERATE_FIELD(TAG_11_STAT, int) + GENERATE_FIELD(TAG_12_STAT, int) + GENERATE_FIELD(TAG_13_STAT, int) + GENERATE_FIELD(TAG_14_STAT, int) + GENERATE_FIELD(TAG_15_STAT, int) + GENERATE_FIELD(TAG_16_STAT, int) + GENERATE_FIELD(TAG_17_STAT, int) + GENERATE_FIELD(INVALID_RETURN_TAG, int) +END_REGISTER(CP_MIU_TAG_STAT) + +START_REGISTER(CP_CMD_INDEX) + GENERATE_FIELD(CMD_INDEX, int) + GENERATE_FIELD(CMD_QUEUE_SEL, int) +END_REGISTER(CP_CMD_INDEX) + +START_REGISTER(CP_CMD_DATA) + GENERATE_FIELD(CMD_DATA, int) +END_REGISTER(CP_CMD_DATA) + +START_REGISTER(CP_ME_CNTL) + GENERATE_FIELD(ME_STATMUX, int) + GENERATE_FIELD(VTX_DEALLOC_FIFO_EMPTY, int) + GENERATE_FIELD(PIX_DEALLOC_FIFO_EMPTY, int) + GENERATE_FIELD(ME_HALT, int) + GENERATE_FIELD(ME_BUSY, int) + GENERATE_FIELD(PROG_CNT_SIZE, int) +END_REGISTER(CP_ME_CNTL) + +START_REGISTER(CP_ME_STATUS) + GENERATE_FIELD(ME_DEBUG_DATA, int) +END_REGISTER(CP_ME_STATUS) + +START_REGISTER(CP_ME_RAM_WADDR) + GENERATE_FIELD(ME_RAM_WADDR, int) +END_REGISTER(CP_ME_RAM_WADDR) + +START_REGISTER(CP_ME_RAM_RADDR) + GENERATE_FIELD(ME_RAM_RADDR, int) +END_REGISTER(CP_ME_RAM_RADDR) + +START_REGISTER(CP_ME_RAM_DATA) + GENERATE_FIELD(ME_RAM_DATA, int) +END_REGISTER(CP_ME_RAM_DATA) + +START_REGISTER(CP_ME_RDADDR) + GENERATE_FIELD(ME_RDADDR, int) +END_REGISTER(CP_ME_RDADDR) + +START_REGISTER(CP_DEBUG) + GENERATE_FIELD(CP_DEBUG_UNUSED_22_to_0, int) + GENERATE_FIELD(PREDICATE_DISABLE, int) + GENERATE_FIELD(PROG_END_PTR_ENABLE, int) + GENERATE_FIELD(MIU_128BIT_WRITE_ENABLE, int) + GENERATE_FIELD(PREFETCH_PASS_NOPS, int) + GENERATE_FIELD(DYNAMIC_CLK_DISABLE, int) + GENERATE_FIELD(PREFETCH_MATCH_DISABLE, int) + GENERATE_FIELD(SIMPLE_ME_FLOW_CONTROL, int) + GENERATE_FIELD(MIU_WRITE_PACK_DISABLE, int) +END_REGISTER(CP_DEBUG) + +START_REGISTER(SCRATCH_REG0) + GENERATE_FIELD(SCRATCH_REG0, int) +END_REGISTER(SCRATCH_REG0) + +START_REGISTER(SCRATCH_REG1) + GENERATE_FIELD(SCRATCH_REG1, int) +END_REGISTER(SCRATCH_REG1) + +START_REGISTER(SCRATCH_REG2) + GENERATE_FIELD(SCRATCH_REG2, int) +END_REGISTER(SCRATCH_REG2) + +START_REGISTER(SCRATCH_REG3) + GENERATE_FIELD(SCRATCH_REG3, int) +END_REGISTER(SCRATCH_REG3) + +START_REGISTER(SCRATCH_REG4) + GENERATE_FIELD(SCRATCH_REG4, int) +END_REGISTER(SCRATCH_REG4) + +START_REGISTER(SCRATCH_REG5) + GENERATE_FIELD(SCRATCH_REG5, int) +END_REGISTER(SCRATCH_REG5) + +START_REGISTER(SCRATCH_REG6) + GENERATE_FIELD(SCRATCH_REG6, int) +END_REGISTER(SCRATCH_REG6) + +START_REGISTER(SCRATCH_REG7) + GENERATE_FIELD(SCRATCH_REG7, int) +END_REGISTER(SCRATCH_REG7) + +START_REGISTER(SCRATCH_UMSK) + GENERATE_FIELD(SCRATCH_UMSK, int) + GENERATE_FIELD(SCRATCH_SWAP, int) +END_REGISTER(SCRATCH_UMSK) + +START_REGISTER(SCRATCH_ADDR) + GENERATE_FIELD(SCRATCH_ADDR, hex) +END_REGISTER(SCRATCH_ADDR) + +START_REGISTER(CP_ME_VS_EVENT_SRC) + GENERATE_FIELD(VS_DONE_SWM, int) + GENERATE_FIELD(VS_DONE_CNTR, int) +END_REGISTER(CP_ME_VS_EVENT_SRC) + +START_REGISTER(CP_ME_VS_EVENT_ADDR) + GENERATE_FIELD(VS_DONE_SWAP, int) + GENERATE_FIELD(VS_DONE_ADDR, int) +END_REGISTER(CP_ME_VS_EVENT_ADDR) + +START_REGISTER(CP_ME_VS_EVENT_DATA) + GENERATE_FIELD(VS_DONE_DATA, int) +END_REGISTER(CP_ME_VS_EVENT_DATA) + +START_REGISTER(CP_ME_VS_EVENT_ADDR_SWM) + GENERATE_FIELD(VS_DONE_SWAP_SWM, int) + GENERATE_FIELD(VS_DONE_ADDR_SWM, int) +END_REGISTER(CP_ME_VS_EVENT_ADDR_SWM) + +START_REGISTER(CP_ME_VS_EVENT_DATA_SWM) + GENERATE_FIELD(VS_DONE_DATA_SWM, int) +END_REGISTER(CP_ME_VS_EVENT_DATA_SWM) + +START_REGISTER(CP_ME_PS_EVENT_SRC) + GENERATE_FIELD(PS_DONE_SWM, int) + GENERATE_FIELD(PS_DONE_CNTR, int) +END_REGISTER(CP_ME_PS_EVENT_SRC) + +START_REGISTER(CP_ME_PS_EVENT_ADDR) + GENERATE_FIELD(PS_DONE_SWAP, int) + GENERATE_FIELD(PS_DONE_ADDR, int) +END_REGISTER(CP_ME_PS_EVENT_ADDR) + +START_REGISTER(CP_ME_PS_EVENT_DATA) + GENERATE_FIELD(PS_DONE_DATA, int) +END_REGISTER(CP_ME_PS_EVENT_DATA) + +START_REGISTER(CP_ME_PS_EVENT_ADDR_SWM) + GENERATE_FIELD(PS_DONE_SWAP_SWM, int) + GENERATE_FIELD(PS_DONE_ADDR_SWM, int) +END_REGISTER(CP_ME_PS_EVENT_ADDR_SWM) + +START_REGISTER(CP_ME_PS_EVENT_DATA_SWM) + GENERATE_FIELD(PS_DONE_DATA_SWM, int) +END_REGISTER(CP_ME_PS_EVENT_DATA_SWM) + +START_REGISTER(CP_ME_CF_EVENT_SRC) + GENERATE_FIELD(CF_DONE_SRC, int) +END_REGISTER(CP_ME_CF_EVENT_SRC) + +START_REGISTER(CP_ME_CF_EVENT_ADDR) + GENERATE_FIELD(CF_DONE_SWAP, int) + GENERATE_FIELD(CF_DONE_ADDR, int) +END_REGISTER(CP_ME_CF_EVENT_ADDR) + +START_REGISTER(CP_ME_CF_EVENT_DATA) + GENERATE_FIELD(CF_DONE_DATA, int) +END_REGISTER(CP_ME_CF_EVENT_DATA) + +START_REGISTER(CP_ME_NRT_ADDR) + GENERATE_FIELD(NRT_WRITE_SWAP, int) + GENERATE_FIELD(NRT_WRITE_ADDR, int) +END_REGISTER(CP_ME_NRT_ADDR) + +START_REGISTER(CP_ME_NRT_DATA) + GENERATE_FIELD(NRT_WRITE_DATA, int) +END_REGISTER(CP_ME_NRT_DATA) + +START_REGISTER(CP_ME_VS_FETCH_DONE_SRC) + GENERATE_FIELD(VS_FETCH_DONE_CNTR, int) +END_REGISTER(CP_ME_VS_FETCH_DONE_SRC) + +START_REGISTER(CP_ME_VS_FETCH_DONE_ADDR) + GENERATE_FIELD(VS_FETCH_DONE_SWAP, int) + GENERATE_FIELD(VS_FETCH_DONE_ADDR, int) +END_REGISTER(CP_ME_VS_FETCH_DONE_ADDR) + +START_REGISTER(CP_ME_VS_FETCH_DONE_DATA) + GENERATE_FIELD(VS_FETCH_DONE_DATA, int) +END_REGISTER(CP_ME_VS_FETCH_DONE_DATA) + +START_REGISTER(CP_INT_CNTL) + GENERATE_FIELD(SW_INT_MASK, int) + GENERATE_FIELD(T0_PACKET_IN_IB_MASK, int) + GENERATE_FIELD(OPCODE_ERROR_MASK, int) + GENERATE_FIELD(PROTECTED_MODE_ERROR_MASK, int) + GENERATE_FIELD(RESERVED_BIT_ERROR_MASK, int) + GENERATE_FIELD(IB_ERROR_MASK, int) + GENERATE_FIELD(IB2_INT_MASK, int) + GENERATE_FIELD(IB1_INT_MASK, int) + GENERATE_FIELD(RB_INT_MASK, int) +END_REGISTER(CP_INT_CNTL) + +START_REGISTER(CP_INT_STATUS) + GENERATE_FIELD(SW_INT_STAT, int) + GENERATE_FIELD(T0_PACKET_IN_IB_STAT, int) + GENERATE_FIELD(OPCODE_ERROR_STAT, int) + GENERATE_FIELD(PROTECTED_MODE_ERROR_STAT, int) + GENERATE_FIELD(RESERVED_BIT_ERROR_STAT, int) + GENERATE_FIELD(IB_ERROR_STAT, int) + GENERATE_FIELD(IB2_INT_STAT, int) + GENERATE_FIELD(IB1_INT_STAT, int) + GENERATE_FIELD(RB_INT_STAT, int) +END_REGISTER(CP_INT_STATUS) + +START_REGISTER(CP_INT_ACK) + GENERATE_FIELD(SW_INT_ACK, int) + GENERATE_FIELD(T0_PACKET_IN_IB_ACK, int) + GENERATE_FIELD(OPCODE_ERROR_ACK, int) + GENERATE_FIELD(PROTECTED_MODE_ERROR_ACK, int) + GENERATE_FIELD(RESERVED_BIT_ERROR_ACK, int) + GENERATE_FIELD(IB_ERROR_ACK, int) + GENERATE_FIELD(IB2_INT_ACK, int) + GENERATE_FIELD(IB1_INT_ACK, int) + GENERATE_FIELD(RB_INT_ACK, int) +END_REGISTER(CP_INT_ACK) + +START_REGISTER(CP_PFP_UCODE_ADDR) + GENERATE_FIELD(UCODE_ADDR, hex) +END_REGISTER(CP_PFP_UCODE_ADDR) + +START_REGISTER(CP_PFP_UCODE_DATA) + GENERATE_FIELD(UCODE_DATA, hex) +END_REGISTER(CP_PFP_UCODE_DATA) + +START_REGISTER(CP_PERFMON_CNTL) + GENERATE_FIELD(PERFMON_STATE, int) + GENERATE_FIELD(PERFMON_ENABLE_MODE, int) +END_REGISTER(CP_PERFMON_CNTL) + +START_REGISTER(CP_PERFCOUNTER_SELECT) + GENERATE_FIELD(PERFCOUNT_SEL, CP_PERFCOUNT_SEL) +END_REGISTER(CP_PERFCOUNTER_SELECT) + +START_REGISTER(CP_PERFCOUNTER_LO) + GENERATE_FIELD(PERFCOUNT_LO, int) +END_REGISTER(CP_PERFCOUNTER_LO) + +START_REGISTER(CP_PERFCOUNTER_HI) + GENERATE_FIELD(PERFCOUNT_HI, int) +END_REGISTER(CP_PERFCOUNTER_HI) + +START_REGISTER(CP_BIN_MASK_LO) + GENERATE_FIELD(BIN_MASK_LO, int) +END_REGISTER(CP_BIN_MASK_LO) + +START_REGISTER(CP_BIN_MASK_HI) + GENERATE_FIELD(BIN_MASK_HI, int) +END_REGISTER(CP_BIN_MASK_HI) + +START_REGISTER(CP_BIN_SELECT_LO) + GENERATE_FIELD(BIN_SELECT_LO, int) +END_REGISTER(CP_BIN_SELECT_LO) + +START_REGISTER(CP_BIN_SELECT_HI) + GENERATE_FIELD(BIN_SELECT_HI, int) +END_REGISTER(CP_BIN_SELECT_HI) + +START_REGISTER(CP_NV_FLAGS_0) + GENERATE_FIELD(DISCARD_0, int) + GENERATE_FIELD(END_RCVD_0, int) + GENERATE_FIELD(DISCARD_1, int) + GENERATE_FIELD(END_RCVD_1, int) + GENERATE_FIELD(DISCARD_2, int) + GENERATE_FIELD(END_RCVD_2, int) + GENERATE_FIELD(DISCARD_3, int) + GENERATE_FIELD(END_RCVD_3, int) + GENERATE_FIELD(DISCARD_4, int) + GENERATE_FIELD(END_RCVD_4, int) + GENERATE_FIELD(DISCARD_5, int) + GENERATE_FIELD(END_RCVD_5, int) + GENERATE_FIELD(DISCARD_6, int) + GENERATE_FIELD(END_RCVD_6, int) + GENERATE_FIELD(DISCARD_7, int) + GENERATE_FIELD(END_RCVD_7, int) + GENERATE_FIELD(DISCARD_8, int) + GENERATE_FIELD(END_RCVD_8, int) + GENERATE_FIELD(DISCARD_9, int) + GENERATE_FIELD(END_RCVD_9, int) + GENERATE_FIELD(DISCARD_10, int) + GENERATE_FIELD(END_RCVD_10, int) + GENERATE_FIELD(DISCARD_11, int) + GENERATE_FIELD(END_RCVD_11, int) + GENERATE_FIELD(DISCARD_12, int) + GENERATE_FIELD(END_RCVD_12, int) + GENERATE_FIELD(DISCARD_13, int) + GENERATE_FIELD(END_RCVD_13, int) + GENERATE_FIELD(DISCARD_14, int) + GENERATE_FIELD(END_RCVD_14, int) + GENERATE_FIELD(DISCARD_15, int) + GENERATE_FIELD(END_RCVD_15, int) +END_REGISTER(CP_NV_FLAGS_0) + +START_REGISTER(CP_NV_FLAGS_1) + GENERATE_FIELD(DISCARD_16, int) + GENERATE_FIELD(END_RCVD_16, int) + GENERATE_FIELD(DISCARD_17, int) + GENERATE_FIELD(END_RCVD_17, int) + GENERATE_FIELD(DISCARD_18, int) + GENERATE_FIELD(END_RCVD_18, int) + GENERATE_FIELD(DISCARD_19, int) + GENERATE_FIELD(END_RCVD_19, int) + GENERATE_FIELD(DISCARD_20, int) + GENERATE_FIELD(END_RCVD_20, int) + GENERATE_FIELD(DISCARD_21, int) + GENERATE_FIELD(END_RCVD_21, int) + GENERATE_FIELD(DISCARD_22, int) + GENERATE_FIELD(END_RCVD_22, int) + GENERATE_FIELD(DISCARD_23, int) + GENERATE_FIELD(END_RCVD_23, int) + GENERATE_FIELD(DISCARD_24, int) + GENERATE_FIELD(END_RCVD_24, int) + GENERATE_FIELD(DISCARD_25, int) + GENERATE_FIELD(END_RCVD_25, int) + GENERATE_FIELD(DISCARD_26, int) + GENERATE_FIELD(END_RCVD_26, int) + GENERATE_FIELD(DISCARD_27, int) + GENERATE_FIELD(END_RCVD_27, int) + GENERATE_FIELD(DISCARD_28, int) + GENERATE_FIELD(END_RCVD_28, int) + GENERATE_FIELD(DISCARD_29, int) + GENERATE_FIELD(END_RCVD_29, int) + GENERATE_FIELD(DISCARD_30, int) + GENERATE_FIELD(END_RCVD_30, int) + GENERATE_FIELD(DISCARD_31, int) + GENERATE_FIELD(END_RCVD_31, int) +END_REGISTER(CP_NV_FLAGS_1) + +START_REGISTER(CP_NV_FLAGS_2) + GENERATE_FIELD(DISCARD_32, int) + GENERATE_FIELD(END_RCVD_32, int) + GENERATE_FIELD(DISCARD_33, int) + GENERATE_FIELD(END_RCVD_33, int) + GENERATE_FIELD(DISCARD_34, int) + GENERATE_FIELD(END_RCVD_34, int) + GENERATE_FIELD(DISCARD_35, int) + GENERATE_FIELD(END_RCVD_35, int) + GENERATE_FIELD(DISCARD_36, int) + GENERATE_FIELD(END_RCVD_36, int) + GENERATE_FIELD(DISCARD_37, int) + GENERATE_FIELD(END_RCVD_37, int) + GENERATE_FIELD(DISCARD_38, int) + GENERATE_FIELD(END_RCVD_38, int) + GENERATE_FIELD(DISCARD_39, int) + GENERATE_FIELD(END_RCVD_39, int) + GENERATE_FIELD(DISCARD_40, int) + GENERATE_FIELD(END_RCVD_40, int) + GENERATE_FIELD(DISCARD_41, int) + GENERATE_FIELD(END_RCVD_41, int) + GENERATE_FIELD(DISCARD_42, int) + GENERATE_FIELD(END_RCVD_42, int) + GENERATE_FIELD(DISCARD_43, int) + GENERATE_FIELD(END_RCVD_43, int) + GENERATE_FIELD(DISCARD_44, int) + GENERATE_FIELD(END_RCVD_44, int) + GENERATE_FIELD(DISCARD_45, int) + GENERATE_FIELD(END_RCVD_45, int) + GENERATE_FIELD(DISCARD_46, int) + GENERATE_FIELD(END_RCVD_46, int) + GENERATE_FIELD(DISCARD_47, int) + GENERATE_FIELD(END_RCVD_47, int) +END_REGISTER(CP_NV_FLAGS_2) + +START_REGISTER(CP_NV_FLAGS_3) + GENERATE_FIELD(DISCARD_48, int) + GENERATE_FIELD(END_RCVD_48, int) + GENERATE_FIELD(DISCARD_49, int) + GENERATE_FIELD(END_RCVD_49, int) + GENERATE_FIELD(DISCARD_50, int) + GENERATE_FIELD(END_RCVD_50, int) + GENERATE_FIELD(DISCARD_51, int) + GENERATE_FIELD(END_RCVD_51, int) + GENERATE_FIELD(DISCARD_52, int) + GENERATE_FIELD(END_RCVD_52, int) + GENERATE_FIELD(DISCARD_53, int) + GENERATE_FIELD(END_RCVD_53, int) + GENERATE_FIELD(DISCARD_54, int) + GENERATE_FIELD(END_RCVD_54, int) + GENERATE_FIELD(DISCARD_55, int) + GENERATE_FIELD(END_RCVD_55, int) + GENERATE_FIELD(DISCARD_56, int) + GENERATE_FIELD(END_RCVD_56, int) + GENERATE_FIELD(DISCARD_57, int) + GENERATE_FIELD(END_RCVD_57, int) + GENERATE_FIELD(DISCARD_58, int) + GENERATE_FIELD(END_RCVD_58, int) + GENERATE_FIELD(DISCARD_59, int) + GENERATE_FIELD(END_RCVD_59, int) + GENERATE_FIELD(DISCARD_60, int) + GENERATE_FIELD(END_RCVD_60, int) + GENERATE_FIELD(DISCARD_61, int) + GENERATE_FIELD(END_RCVD_61, int) + GENERATE_FIELD(DISCARD_62, int) + GENERATE_FIELD(END_RCVD_62, int) + GENERATE_FIELD(DISCARD_63, int) + GENERATE_FIELD(END_RCVD_63, int) +END_REGISTER(CP_NV_FLAGS_3) + +START_REGISTER(CP_STATE_DEBUG_INDEX) + GENERATE_FIELD(STATE_DEBUG_INDEX, int) +END_REGISTER(CP_STATE_DEBUG_INDEX) + +START_REGISTER(CP_STATE_DEBUG_DATA) + GENERATE_FIELD(STATE_DEBUG_DATA, int) +END_REGISTER(CP_STATE_DEBUG_DATA) + +START_REGISTER(CP_PROG_COUNTER) + GENERATE_FIELD(COUNTER, int) +END_REGISTER(CP_PROG_COUNTER) + +START_REGISTER(CP_STAT) + GENERATE_FIELD(MIU_WR_BUSY, int) + GENERATE_FIELD(MIU_RD_REQ_BUSY, int) + GENERATE_FIELD(MIU_RD_RETURN_BUSY, int) + GENERATE_FIELD(RBIU_BUSY, int) + GENERATE_FIELD(RCIU_BUSY, int) + GENERATE_FIELD(CSF_RING_BUSY, int) + GENERATE_FIELD(CSF_INDIRECTS_BUSY, int) + GENERATE_FIELD(CSF_INDIRECT2_BUSY, int) + GENERATE_FIELD(CSF_ST_BUSY, int) + GENERATE_FIELD(CSF_BUSY, int) + GENERATE_FIELD(RING_QUEUE_BUSY, int) + GENERATE_FIELD(INDIRECTS_QUEUE_BUSY, int) + GENERATE_FIELD(INDIRECT2_QUEUE_BUSY, int) + GENERATE_FIELD(ST_QUEUE_BUSY, int) + GENERATE_FIELD(PFP_BUSY, int) + GENERATE_FIELD(MEQ_RING_BUSY, int) + GENERATE_FIELD(MEQ_INDIRECTS_BUSY, int) + GENERATE_FIELD(MEQ_INDIRECT2_BUSY, int) + GENERATE_FIELD(MIU_WC_STALL, int) + GENERATE_FIELD(CP_NRT_BUSY, int) + GENERATE_FIELD(_3D_BUSY, int) + GENERATE_FIELD(ME_BUSY, int) + GENERATE_FIELD(ME_WC_BUSY, int) + GENERATE_FIELD(MIU_WC_TRACK_FIFO_EMPTY, int) + GENERATE_FIELD(CP_BUSY, int) +END_REGISTER(CP_STAT) + +START_REGISTER(BIOS_0_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_0_SCRATCH) + +START_REGISTER(BIOS_1_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_1_SCRATCH) + +START_REGISTER(BIOS_2_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_2_SCRATCH) + +START_REGISTER(BIOS_3_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_3_SCRATCH) + +START_REGISTER(BIOS_4_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_4_SCRATCH) + +START_REGISTER(BIOS_5_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_5_SCRATCH) + +START_REGISTER(BIOS_6_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_6_SCRATCH) + +START_REGISTER(BIOS_7_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_7_SCRATCH) + +START_REGISTER(BIOS_8_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_8_SCRATCH) + +START_REGISTER(BIOS_9_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_9_SCRATCH) + +START_REGISTER(BIOS_10_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_10_SCRATCH) + +START_REGISTER(BIOS_11_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_11_SCRATCH) + +START_REGISTER(BIOS_12_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_12_SCRATCH) + +START_REGISTER(BIOS_13_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_13_SCRATCH) + +START_REGISTER(BIOS_14_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_14_SCRATCH) + +START_REGISTER(BIOS_15_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_15_SCRATCH) + +START_REGISTER(COHER_SIZE_PM4) + GENERATE_FIELD(SIZE, int) +END_REGISTER(COHER_SIZE_PM4) + +START_REGISTER(COHER_BASE_PM4) + GENERATE_FIELD(BASE, int) +END_REGISTER(COHER_BASE_PM4) + +START_REGISTER(COHER_STATUS_PM4) + GENERATE_FIELD(MATCHING_CONTEXTS, int) + GENERATE_FIELD(RB_COPY_DEST_BASE_ENA, int) + GENERATE_FIELD(DEST_BASE_0_ENA, int) + GENERATE_FIELD(DEST_BASE_1_ENA, int) + GENERATE_FIELD(DEST_BASE_2_ENA, int) + GENERATE_FIELD(DEST_BASE_3_ENA, int) + GENERATE_FIELD(DEST_BASE_4_ENA, int) + GENERATE_FIELD(DEST_BASE_5_ENA, int) + GENERATE_FIELD(DEST_BASE_6_ENA, int) + GENERATE_FIELD(DEST_BASE_7_ENA, int) + GENERATE_FIELD(TC_ACTION_ENA, int) + GENERATE_FIELD(STATUS, int) +END_REGISTER(COHER_STATUS_PM4) + +START_REGISTER(COHER_SIZE_HOST) + GENERATE_FIELD(SIZE, int) +END_REGISTER(COHER_SIZE_HOST) + +START_REGISTER(COHER_BASE_HOST) + GENERATE_FIELD(BASE, hex) +END_REGISTER(COHER_BASE_HOST) + +START_REGISTER(COHER_STATUS_HOST) + GENERATE_FIELD(MATCHING_CONTEXTS, int) + GENERATE_FIELD(RB_COPY_DEST_BASE_ENA, int) + GENERATE_FIELD(DEST_BASE_0_ENA, int) + GENERATE_FIELD(DEST_BASE_1_ENA, int) + GENERATE_FIELD(DEST_BASE_2_ENA, int) + GENERATE_FIELD(DEST_BASE_3_ENA, int) + GENERATE_FIELD(DEST_BASE_4_ENA, int) + GENERATE_FIELD(DEST_BASE_5_ENA, int) + GENERATE_FIELD(DEST_BASE_6_ENA, int) + GENERATE_FIELD(DEST_BASE_7_ENA, int) + GENERATE_FIELD(TC_ACTION_ENA, int) + GENERATE_FIELD(STATUS, int) +END_REGISTER(COHER_STATUS_HOST) + +START_REGISTER(COHER_DEST_BASE_0) + GENERATE_FIELD(DEST_BASE_0, hex) +END_REGISTER(COHER_DEST_BASE_0) + +START_REGISTER(COHER_DEST_BASE_1) + GENERATE_FIELD(DEST_BASE_1, hex) +END_REGISTER(COHER_DEST_BASE_1) + +START_REGISTER(COHER_DEST_BASE_2) + GENERATE_FIELD(DEST_BASE_2, hex) +END_REGISTER(COHER_DEST_BASE_2) + +START_REGISTER(COHER_DEST_BASE_3) + GENERATE_FIELD(DEST_BASE_3, hex) +END_REGISTER(COHER_DEST_BASE_3) + +START_REGISTER(COHER_DEST_BASE_4) + GENERATE_FIELD(DEST_BASE_4, hex) +END_REGISTER(COHER_DEST_BASE_4) + +START_REGISTER(COHER_DEST_BASE_5) + GENERATE_FIELD(DEST_BASE_5, hex) +END_REGISTER(COHER_DEST_BASE_5) + +START_REGISTER(COHER_DEST_BASE_6) + GENERATE_FIELD(DEST_BASE_6, hex) +END_REGISTER(COHER_DEST_BASE_6) + +START_REGISTER(COHER_DEST_BASE_7) + GENERATE_FIELD(DEST_BASE_7, hex) +END_REGISTER(COHER_DEST_BASE_7) + +START_REGISTER(RB_SURFACE_INFO) + GENERATE_FIELD(SURFACE_PITCH, uint) + GENERATE_FIELD(MSAA_SAMPLES, MSAASamples) +END_REGISTER(RB_SURFACE_INFO) + +START_REGISTER(RB_COLOR_INFO) + GENERATE_FIELD(COLOR_FORMAT, ColorformatX) + GENERATE_FIELD(COLOR_ROUND_MODE, uint) + GENERATE_FIELD(COLOR_LINEAR, bool) + GENERATE_FIELD(COLOR_ENDIAN, uint) + GENERATE_FIELD(COLOR_SWAP, uint) + GENERATE_FIELD(COLOR_BASE, uint) +END_REGISTER(RB_COLOR_INFO) + +START_REGISTER(RB_DEPTH_INFO) + GENERATE_FIELD(DEPTH_FORMAT, DepthformatX) + GENERATE_FIELD(DEPTH_BASE, uint) +END_REGISTER(RB_DEPTH_INFO) + +START_REGISTER(RB_STENCILREFMASK) + GENERATE_FIELD(STENCILREF, hex) + GENERATE_FIELD(STENCILMASK, hex) + GENERATE_FIELD(STENCILWRITEMASK, hex) +END_REGISTER(RB_STENCILREFMASK) + +START_REGISTER(RB_ALPHA_REF) + GENERATE_FIELD(ALPHA_REF, float) +END_REGISTER(RB_ALPHA_REF) + +START_REGISTER(RB_COLOR_MASK) + GENERATE_FIELD(WRITE_RED, bool) + GENERATE_FIELD(WRITE_GREEN, bool) + GENERATE_FIELD(WRITE_BLUE, bool) + GENERATE_FIELD(WRITE_ALPHA, bool) +END_REGISTER(RB_COLOR_MASK) + +START_REGISTER(RB_BLEND_RED) + GENERATE_FIELD(BLEND_RED, uint) +END_REGISTER(RB_BLEND_RED) + +START_REGISTER(RB_BLEND_GREEN) + GENERATE_FIELD(BLEND_GREEN, uint) +END_REGISTER(RB_BLEND_GREEN) + +START_REGISTER(RB_BLEND_BLUE) + GENERATE_FIELD(BLEND_BLUE, uint) +END_REGISTER(RB_BLEND_BLUE) + +START_REGISTER(RB_BLEND_ALPHA) + GENERATE_FIELD(BLEND_ALPHA, uint) +END_REGISTER(RB_BLEND_ALPHA) + +START_REGISTER(RB_FOG_COLOR) + GENERATE_FIELD(FOG_RED, uint) + GENERATE_FIELD(FOG_GREEN, uint) + GENERATE_FIELD(FOG_BLUE, uint) +END_REGISTER(RB_FOG_COLOR) + +START_REGISTER(RB_STENCILREFMASK_BF) + GENERATE_FIELD(STENCILREF_BF, hex) + GENERATE_FIELD(STENCILMASK_BF, hex) + GENERATE_FIELD(STENCILWRITEMASK_BF, hex) +END_REGISTER(RB_STENCILREFMASK_BF) + +START_REGISTER(RB_DEPTHCONTROL) + GENERATE_FIELD(STENCIL_ENABLE, bool) + GENERATE_FIELD(Z_ENABLE, bool) + GENERATE_FIELD(Z_WRITE_ENABLE, bool) + GENERATE_FIELD(EARLY_Z_ENABLE, bool) + GENERATE_FIELD(ZFUNC, CompareFrag) + GENERATE_FIELD(BACKFACE_ENABLE, bool) + GENERATE_FIELD(STENCILFUNC, CompareRef) + GENERATE_FIELD(STENCILFAIL, StencilOp) + GENERATE_FIELD(STENCILZPASS, StencilOp) + GENERATE_FIELD(STENCILZFAIL, StencilOp) + GENERATE_FIELD(STENCILFUNC_BF, CompareRef) + GENERATE_FIELD(STENCILFAIL_BF, StencilOp) + GENERATE_FIELD(STENCILZPASS_BF, StencilOp) + GENERATE_FIELD(STENCILZFAIL_BF, StencilOp) +END_REGISTER(RB_DEPTHCONTROL) + +START_REGISTER(RB_BLENDCONTROL) + GENERATE_FIELD(COLOR_SRCBLEND, BlendOpX) + GENERATE_FIELD(COLOR_COMB_FCN, CombFuncX) + GENERATE_FIELD(COLOR_DESTBLEND, BlendOpX) + GENERATE_FIELD(ALPHA_SRCBLEND, BlendOpX) + GENERATE_FIELD(ALPHA_COMB_FCN, CombFuncX) + GENERATE_FIELD(ALPHA_DESTBLEND, BlendOpX) + GENERATE_FIELD(BLEND_FORCE_ENABLE, bool) + GENERATE_FIELD(BLEND_FORCE, bool) +END_REGISTER(RB_BLENDCONTROL) + +START_REGISTER(RB_COLORCONTROL) + GENERATE_FIELD(ALPHA_FUNC, CompareRef) + GENERATE_FIELD(ALPHA_TEST_ENABLE, bool) + GENERATE_FIELD(ALPHA_TO_MASK_ENABLE, bool) + GENERATE_FIELD(BLEND_DISABLE, bool) + GENERATE_FIELD(FOG_ENABLE, bool) + GENERATE_FIELD(VS_EXPORTS_FOG, bool) + GENERATE_FIELD(ROP_CODE, uint) + GENERATE_FIELD(DITHER_MODE, DitherModeX) + GENERATE_FIELD(DITHER_TYPE, DitherTypeX) + GENERATE_FIELD(PIXEL_FOG, bool) + GENERATE_FIELD(ALPHA_TO_MASK_OFFSET0, hex) + GENERATE_FIELD(ALPHA_TO_MASK_OFFSET1, hex) + GENERATE_FIELD(ALPHA_TO_MASK_OFFSET2, hex) + GENERATE_FIELD(ALPHA_TO_MASK_OFFSET3, hex) +END_REGISTER(RB_COLORCONTROL) + +START_REGISTER(RB_MODECONTROL) + GENERATE_FIELD(EDRAM_MODE, EdramMode) +END_REGISTER(RB_MODECONTROL) + +START_REGISTER(RB_COLOR_DEST_MASK) + GENERATE_FIELD(COLOR_DEST_MASK, uint) +END_REGISTER(RB_COLOR_DEST_MASK) + +START_REGISTER(RB_COPY_CONTROL) + GENERATE_FIELD(COPY_SAMPLE_SELECT, CopySampleSelect) + GENERATE_FIELD(DEPTH_CLEAR_ENABLE, bool) + GENERATE_FIELD(CLEAR_MASK, uint) +END_REGISTER(RB_COPY_CONTROL) + +START_REGISTER(RB_COPY_DEST_BASE) + GENERATE_FIELD(COPY_DEST_BASE, uint) +END_REGISTER(RB_COPY_DEST_BASE) + +START_REGISTER(RB_COPY_DEST_PITCH) + GENERATE_FIELD(COPY_DEST_PITCH, uint) +END_REGISTER(RB_COPY_DEST_PITCH) + +START_REGISTER(RB_COPY_DEST_INFO) + GENERATE_FIELD(COPY_DEST_ENDIAN, SurfaceEndian) + GENERATE_FIELD(COPY_DEST_LINEAR, uint) + GENERATE_FIELD(COPY_DEST_FORMAT, ColorformatX) + GENERATE_FIELD(COPY_DEST_SWAP, uint) + GENERATE_FIELD(COPY_DEST_DITHER_MODE, DitherModeX) + GENERATE_FIELD(COPY_DEST_DITHER_TYPE, DitherTypeX) + GENERATE_FIELD(COPY_MASK_WRITE_RED, hex) + GENERATE_FIELD(COPY_MASK_WRITE_GREEN, hex) + GENERATE_FIELD(COPY_MASK_WRITE_BLUE, hex) + GENERATE_FIELD(COPY_MASK_WRITE_ALPHA, hex) +END_REGISTER(RB_COPY_DEST_INFO) + +START_REGISTER(RB_COPY_DEST_PIXEL_OFFSET) + GENERATE_FIELD(OFFSET_X, uint) + GENERATE_FIELD(OFFSET_Y, uint) +END_REGISTER(RB_COPY_DEST_PIXEL_OFFSET) + +START_REGISTER(RB_DEPTH_CLEAR) + GENERATE_FIELD(DEPTH_CLEAR, uint) +END_REGISTER(RB_DEPTH_CLEAR) + +START_REGISTER(RB_SAMPLE_COUNT_CTL) + GENERATE_FIELD(RESET_SAMPLE_COUNT, bool) + GENERATE_FIELD(COPY_SAMPLE_COUNT, bool) +END_REGISTER(RB_SAMPLE_COUNT_CTL) + +START_REGISTER(RB_SAMPLE_COUNT_ADDR) + GENERATE_FIELD(SAMPLE_COUNT_ADDR, uint) +END_REGISTER(RB_SAMPLE_COUNT_ADDR) + +START_REGISTER(RB_BC_CONTROL) + GENERATE_FIELD(ACCUM_LINEAR_MODE_ENABLE, bool) + GENERATE_FIELD(ACCUM_TIMEOUT_SELECT, uint) + GENERATE_FIELD(DISABLE_EDRAM_CAM, bool) + GENERATE_FIELD(DISABLE_EZ_FAST_CONTEXT_SWITCH, bool) + GENERATE_FIELD(DISABLE_EZ_NULL_ZCMD_DROP, bool) + GENERATE_FIELD(DISABLE_LZ_NULL_ZCMD_DROP, bool) + GENERATE_FIELD(ENABLE_AZ_THROTTLE, bool) + GENERATE_FIELD(AZ_THROTTLE_COUNT, uint) + GENERATE_FIELD(ENABLE_CRC_UPDATE, bool) + GENERATE_FIELD(CRC_MODE, bool) + GENERATE_FIELD(DISABLE_SAMPLE_COUNTERS, bool) + GENERATE_FIELD(DISABLE_ACCUM, bool) + GENERATE_FIELD(ACCUM_ALLOC_MASK, uint) + GENERATE_FIELD(LINEAR_PERFORMANCE_ENABLE, bool) + GENERATE_FIELD(ACCUM_DATA_FIFO_LIMIT, bool) + GENERATE_FIELD(MEM_EXPORT_TIMEOUT_SELECT, int) + GENERATE_FIELD(MEM_EXPORT_LINEAR_MODE_ENABLE, bool) + GENERATE_FIELD(RESERVED9, bool) + GENERATE_FIELD(RESERVED10, bool) +END_REGISTER(RB_BC_CONTROL) + +START_REGISTER(RB_EDRAM_INFO) + GENERATE_FIELD(EDRAM_SIZE, EdramSizeX) + GENERATE_FIELD(EDRAM_MAPPING_MODE, uint) + GENERATE_FIELD(EDRAM_RANGE, hex) +END_REGISTER(RB_EDRAM_INFO) + +START_REGISTER(RB_CRC_RD_PORT) + GENERATE_FIELD(CRC_DATA, hex) +END_REGISTER(RB_CRC_RD_PORT) + +START_REGISTER(RB_CRC_CONTROL) + GENERATE_FIELD(CRC_RD_ADVANCE, bool) +END_REGISTER(RB_CRC_CONTROL) + +START_REGISTER(RB_CRC_MASK) + GENERATE_FIELD(CRC_MASK, hex) +END_REGISTER(RB_CRC_MASK) + +START_REGISTER(RB_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, RB_PERFCNT_SELECT) +END_REGISTER(RB_PERFCOUNTER0_SELECT) + +START_REGISTER(RB_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(RB_PERFCOUNTER0_LOW) + +START_REGISTER(RB_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(RB_PERFCOUNTER0_HI) + +START_REGISTER(RB_TOTAL_SAMPLES) + GENERATE_FIELD(TOTAL_SAMPLES, int) +END_REGISTER(RB_TOTAL_SAMPLES) + +START_REGISTER(RB_ZPASS_SAMPLES) + GENERATE_FIELD(ZPASS_SAMPLES, int) +END_REGISTER(RB_ZPASS_SAMPLES) + +START_REGISTER(RB_ZFAIL_SAMPLES) + GENERATE_FIELD(ZFAIL_SAMPLES, int) +END_REGISTER(RB_ZFAIL_SAMPLES) + +START_REGISTER(RB_SFAIL_SAMPLES) + GENERATE_FIELD(SFAIL_SAMPLES, int) +END_REGISTER(RB_SFAIL_SAMPLES) + +START_REGISTER(RB_DEBUG_0) + GENERATE_FIELD(RDREQ_CTL_Z1_PRE_FULL, bool) + GENERATE_FIELD(RDREQ_CTL_Z0_PRE_FULL, bool) + GENERATE_FIELD(RDREQ_CTL_C1_PRE_FULL, bool) + GENERATE_FIELD(RDREQ_CTL_C0_PRE_FULL, bool) + GENERATE_FIELD(RDREQ_E1_ORDERING_FULL, bool) + GENERATE_FIELD(RDREQ_E0_ORDERING_FULL, bool) + GENERATE_FIELD(RDREQ_Z1_FULL, bool) + GENERATE_FIELD(RDREQ_Z0_FULL, bool) + GENERATE_FIELD(RDREQ_C1_FULL, bool) + GENERATE_FIELD(RDREQ_C0_FULL, bool) + GENERATE_FIELD(WRREQ_E1_MACRO_HI_FULL, bool) + GENERATE_FIELD(WRREQ_E1_MACRO_LO_FULL, bool) + GENERATE_FIELD(WRREQ_E0_MACRO_HI_FULL, bool) + GENERATE_FIELD(WRREQ_E0_MACRO_LO_FULL, bool) + GENERATE_FIELD(WRREQ_C_WE_HI_FULL, bool) + GENERATE_FIELD(WRREQ_C_WE_LO_FULL, bool) + GENERATE_FIELD(WRREQ_Z1_FULL, bool) + GENERATE_FIELD(WRREQ_Z0_FULL, bool) + GENERATE_FIELD(WRREQ_C1_FULL, bool) + GENERATE_FIELD(WRREQ_C0_FULL, bool) + GENERATE_FIELD(CMDFIFO_Z1_HOLD_FULL, bool) + GENERATE_FIELD(CMDFIFO_Z0_HOLD_FULL, bool) + GENERATE_FIELD(CMDFIFO_C1_HOLD_FULL, bool) + GENERATE_FIELD(CMDFIFO_C0_HOLD_FULL, bool) + GENERATE_FIELD(CMDFIFO_Z_ORDERING_FULL, bool) + GENERATE_FIELD(CMDFIFO_C_ORDERING_FULL, bool) + GENERATE_FIELD(C_SX_LAT_FULL, bool) + GENERATE_FIELD(C_SX_CMD_FULL, bool) + GENERATE_FIELD(C_EZ_TILE_FULL, bool) + GENERATE_FIELD(C_REQ_FULL, bool) + GENERATE_FIELD(C_MASK_FULL, bool) + GENERATE_FIELD(EZ_INFSAMP_FULL, bool) +END_REGISTER(RB_DEBUG_0) + +START_REGISTER(RB_DEBUG_1) + GENERATE_FIELD(RDREQ_Z1_CMD_EMPTY, bool) + GENERATE_FIELD(RDREQ_Z0_CMD_EMPTY, bool) + GENERATE_FIELD(RDREQ_C1_CMD_EMPTY, bool) + GENERATE_FIELD(RDREQ_C0_CMD_EMPTY, bool) + GENERATE_FIELD(RDREQ_E1_ORDERING_EMPTY, bool) + GENERATE_FIELD(RDREQ_E0_ORDERING_EMPTY, bool) + GENERATE_FIELD(RDREQ_Z1_EMPTY, bool) + GENERATE_FIELD(RDREQ_Z0_EMPTY, bool) + GENERATE_FIELD(RDREQ_C1_EMPTY, bool) + GENERATE_FIELD(RDREQ_C0_EMPTY, bool) + GENERATE_FIELD(WRREQ_E1_MACRO_HI_EMPTY, bool) + GENERATE_FIELD(WRREQ_E1_MACRO_LO_EMPTY, bool) + GENERATE_FIELD(WRREQ_E0_MACRO_HI_EMPTY, bool) + GENERATE_FIELD(WRREQ_E0_MACRO_LO_EMPTY, bool) + GENERATE_FIELD(WRREQ_C_WE_HI_EMPTY, bool) + GENERATE_FIELD(WRREQ_C_WE_LO_EMPTY, bool) + GENERATE_FIELD(WRREQ_Z1_EMPTY, bool) + GENERATE_FIELD(WRREQ_Z0_EMPTY, bool) + GENERATE_FIELD(WRREQ_C1_PRE_EMPTY, bool) + GENERATE_FIELD(WRREQ_C0_PRE_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_Z1_HOLD_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_Z0_HOLD_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_C1_HOLD_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_C0_HOLD_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_Z_ORDERING_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_C_ORDERING_EMPTY, bool) + GENERATE_FIELD(C_SX_LAT_EMPTY, bool) + GENERATE_FIELD(C_SX_CMD_EMPTY, bool) + GENERATE_FIELD(C_EZ_TILE_EMPTY, bool) + GENERATE_FIELD(C_REQ_EMPTY, bool) + GENERATE_FIELD(C_MASK_EMPTY, bool) + GENERATE_FIELD(EZ_INFSAMP_EMPTY, bool) +END_REGISTER(RB_DEBUG_1) + +START_REGISTER(RB_DEBUG_2) + GENERATE_FIELD(TILE_FIFO_COUNT, bool) + GENERATE_FIELD(SX_LAT_FIFO_COUNT, bool) + GENERATE_FIELD(MEM_EXPORT_FLAG, bool) + GENERATE_FIELD(SYSMEM_BLEND_FLAG, bool) + GENERATE_FIELD(CURRENT_TILE_EVENT, bool) + GENERATE_FIELD(EZ_INFTILE_FULL, bool) + GENERATE_FIELD(EZ_MASK_LOWER_FULL, bool) + GENERATE_FIELD(EZ_MASK_UPPER_FULL, bool) + GENERATE_FIELD(Z0_MASK_FULL, bool) + GENERATE_FIELD(Z1_MASK_FULL, bool) + GENERATE_FIELD(Z0_REQ_FULL, bool) + GENERATE_FIELD(Z1_REQ_FULL, bool) + GENERATE_FIELD(Z_SAMP_FULL, bool) + GENERATE_FIELD(Z_TILE_FULL, bool) + GENERATE_FIELD(EZ_INFTILE_EMPTY, bool) + GENERATE_FIELD(EZ_MASK_LOWER_EMPTY, bool) + GENERATE_FIELD(EZ_MASK_UPPER_EMPTY, bool) + GENERATE_FIELD(Z0_MASK_EMPTY, bool) + GENERATE_FIELD(Z1_MASK_EMPTY, bool) + GENERATE_FIELD(Z0_REQ_EMPTY, bool) + GENERATE_FIELD(Z1_REQ_EMPTY, bool) + GENERATE_FIELD(Z_SAMP_EMPTY, bool) + GENERATE_FIELD(Z_TILE_EMPTY, bool) +END_REGISTER(RB_DEBUG_2) + +START_REGISTER(RB_DEBUG_3) + GENERATE_FIELD(ACCUM_VALID, bool) + GENERATE_FIELD(ACCUM_FLUSHING, bool) + GENERATE_FIELD(ACCUM_WRITE_CLEAN_COUNT, bool) + GENERATE_FIELD(ACCUM_INPUT_REG_VALID, bool) + GENERATE_FIELD(ACCUM_DATA_FIFO_CNT, bool) + GENERATE_FIELD(SHD_FULL, bool) + GENERATE_FIELD(SHD_EMPTY, bool) + GENERATE_FIELD(EZ_RETURN_LOWER_EMPTY, bool) + GENERATE_FIELD(EZ_RETURN_UPPER_EMPTY, bool) + GENERATE_FIELD(EZ_RETURN_LOWER_FULL, bool) + GENERATE_FIELD(EZ_RETURN_UPPER_FULL, bool) + GENERATE_FIELD(ZEXP_LOWER_EMPTY, bool) + GENERATE_FIELD(ZEXP_UPPER_EMPTY, bool) + GENERATE_FIELD(ZEXP_LOWER_FULL, bool) + GENERATE_FIELD(ZEXP_UPPER_FULL, bool) +END_REGISTER(RB_DEBUG_3) + +START_REGISTER(RB_DEBUG_4) + GENERATE_FIELD(GMEM_RD_ACCESS_FLAG, bool) + GENERATE_FIELD(GMEM_WR_ACCESS_FLAG, bool) + GENERATE_FIELD(SYSMEM_RD_ACCESS_FLAG, bool) + GENERATE_FIELD(SYSMEM_WR_ACCESS_FLAG, bool) + GENERATE_FIELD(ACCUM_DATA_FIFO_EMPTY, bool) + GENERATE_FIELD(ACCUM_ORDER_FIFO_EMPTY, bool) + GENERATE_FIELD(ACCUM_DATA_FIFO_FULL, bool) + GENERATE_FIELD(ACCUM_ORDER_FIFO_FULL, bool) + GENERATE_FIELD(SYSMEM_WRITE_COUNT_OVERFLOW, bool) + GENERATE_FIELD(CONTEXT_COUNT_DEBUG, bool) +END_REGISTER(RB_DEBUG_4) + +START_REGISTER(RB_FLAG_CONTROL) + GENERATE_FIELD(DEBUG_FLAG_CLEAR, bool) +END_REGISTER(RB_FLAG_CONTROL) + +START_REGISTER(BC_DUMMY_CRAYRB_ENUMS) + GENERATE_FIELD(DUMMY_CRAYRB_DEPTH_FORMAT, DepthFormat) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_SWAP, SurfaceSwap) + GENERATE_FIELD(DUMMY_CRAYRB_DEPTH_ARRAY, DepthArray) + GENERATE_FIELD(DUMMY_CRAYRB_ARRAY, ColorArray) + GENERATE_FIELD(DUMMY_CRAYRB_COLOR_FORMAT, ColorFormat) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_NUMBER, SurfaceNumber) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_FORMAT, SurfaceFormat) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_TILING, SurfaceTiling) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_ARRAY, SurfaceArray) + GENERATE_FIELD(DUMMY_RB_COPY_DEST_INFO_NUMBER, SurfaceNumberX) +END_REGISTER(BC_DUMMY_CRAYRB_ENUMS) + +START_REGISTER(BC_DUMMY_CRAYRB_MOREENUMS) + GENERATE_FIELD(DUMMY_CRAYRB_COLORARRAYX, ColorArrayX) +END_REGISTER(BC_DUMMY_CRAYRB_MOREENUMS) diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_ipt.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_ipt.h new file mode 100644 index 000000000000..0e32e421d0a3 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_ipt.h @@ -0,0 +1,95 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _R400IPT_H_ +#define _R400IPT_H_ + +// Hand-generated list from Yamato_PM4_Spec.doc + +#define PM4_PACKET0_NOP 0x00000000 // Empty type-0 packet header +#define PM4_PACKET1_NOP 0x40000000 // Empty type-1 packet header +#define PM4_PACKET2_NOP 0x80000000 // Empty type-2 packet header (reserved) + +#define PM4_COUNT_SHIFT 16 +#define PM4_COUNT_MASK +#define PM4_PACKET_COUNT(__x) ((((__x)-1) << PM4_COUNT_SHIFT) & 0x3fff0000) +// Type 3 packet headers + +#define PM4_PACKET3_NOP 0xC0001000 // Do nothing. +#define PM4_PACKET3_IB_PREFETCH_END 0xC0001700 // Internal Packet Used Only by CP +#define PM4_PACKET3_SUBBLK_PREFETCH 0xC0001F00 // Internal Packet Used Only by CP + +#define PM4_PACKET3_INSTR_PREFETCH 0xC0002000 // Internal Packet Used Only by CP +#define PM4_PACKET3_REG_RMW 0xC0002100 // Register Read-Modify-Write New for R400 +#define PM4_PACKET3_DRAW_INDX 0xC0002200 // Initiate fetch of index buffer New for R400 +#define PM4_PACKET3_VIZ_QUERY 0xC0002300 // Begin/End initiator for Viz Query extent processing New for R400 +#define PM4_PACKET3_SET_STATE 0xC0002500 // Fetch State Sub-Blocks and Initiate Shader Code DMAs New for R400 +#define PM4_PACKET3_WAIT_FOR_IDLE 0xC0002600 // Wait for the engine to be idle. +#define PM4_PACKET3_IM_LOAD 0xC0002700 // Load Sequencer Instruction Memory for a Specific Shader New for R400 +#define PM4_PACKET3_IM_LOAD_IMMEDIATE 0xC0002B00 // Load Sequencer Instruction Memory for a Specific Shader New for R400 +#define PM4_PACKET3_SET_CONSTANT 0xC0002D00 // Load Constant Into Chip & Shadow to Memory New for R400 +#define PM4_PACKET3_LOAD_CONSTANT_CONTEXT 0xC0002E00 // Load All Constants from a Location in Memory New for R400 +#define PM4_PACKET3_LOAD_ALU_CONSTANT 0xC0002F00 // Load ALu constants from a location in memory - similar to SET_CONSTANT but tuned for performance when loading only ALU constants + +#define PM4_PACKET3_DRAW_INDX_BIN 0xC0003400 // Initiate fetch of index buffer and BIN info used for visibility test +#define PM4_PACKET3_3D_DRAW_INDX_2_BIN 0xC0003500 // Draw using supplied indices and initiate fetch of BIN info for visibility test +#define PM4_PACKET3_3D_DRAW_INDX_2 0xC0003600 // Draw primitives using vertex buf and Indices in this packet. Pkt does NOT contain vtx fmt +#define PM4_PACKET3_INDIRECT_BUFFER_PFD 0xC0003700 +#define PM4_PACKET3_INVALIDATE_STATE 0xC0003B00 // Selective Invalidation of State Pointers New for R400 +#define PM4_PACKET3_WAIT_REG_MEM 0xC0003C00 // Wait Until a Register or Memory Location is a Specific Value. New for R400 +#define PM4_PACKET3_MEM_WRITE 0xC0003D00 // Write DWORD to Memory For Synchronization New for R400 +#define PM4_PACKET3_REG_TO_MEM 0xC0003E00 // Reads Register in Chip and Writes to Memory New for R400 +#define PM4_PACKET3_INDIRECT_BUFFER 0xC0003F00 // Indirect Buffer Dispatch - Pre-fetch parser uses this packet type in determining to pre-fetch the indirect buffer. Supported + +#define PM4_PACKET3_CP_INTERRUPT 0xC0004000 // Generate Interrupt from the Command Stream New for R400 +#define PM4_PACKET3_COND_EXEC 0xC0004400 // Conditional execution of a sequence of packets +#define PM4_PACKET3_COND_WRITE 0xC0004500 // Conditional Write to Memory New for R400 +#define PM4_PACKET3_EVENT_WRITE 0xC0004600 // Generate An Event that Creates a Write to Memory when Completed New for R400 +#define PM4_PACKET3_INSTR_MATCH 0xC0004700 // Internal Packet Used Only by CP +#define PM4_PACKET3_ME_INIT 0xC0004800 // Initialize CP's Micro Engine New for R400 +#define PM4_PACKET3_CONST_PREFETCH 0xC0004900 // Internal packet used only by CP +#define PM4_PACKET3_MEM_WRITE_CNTR 0xC0004F00 + +#define PM4_PACKET3_SET_BIN_MASK 0xC0005000 // Sets the 64-bit BIN_MASK register in the PFP +#define PM4_PACKET3_SET_BIN_SELECT 0xC0005100 // Sets the 64-bit BIN_SELECT register in the PFP +#define PM4_PACKET3_WAIT_REG_EQ 0xC0005200 // Wait until a register location is equal to a specific value +#define PM4_PACKET3_WAIT_REG_GTE 0xC0005300 // Wait until a register location is greater than or equal to a specific value +#define PM4_PACKET3_INCR_UPDT_STATE 0xC0005500 // Internal Packet Used Only by CP +#define PM4_PACKET3_INCR_UPDT_CONST 0xC0005600 // Internal Packet Used Only by CP +#define PM4_PACKET3_INCR_UPDT_INSTR 0xC0005700 // Internal Packet Used Only by CP +#define PM4_PACKET3_EVENT_WRITE_SHD 0xC0005800 // Generate a VS|PS_Done Event. +#define PM4_PACKET3_EVENT_WRITE_CFL 0xC0005900 // Generate a Cach Flush Done Event +#define PM4_PACKET3_EVENT_WRITE_ZPD 0xC0005B00 // Generate a Cach Flush Done Event +#define PM4_PACKET3_WAIT_UNTIL_READ 0xC0005C00 // Wait Until a Read completes. +#define PM4_PACKET3_WAIT_IB_PFD_COMPLETE 0xC0005D00 // Wait Until all Base/Size writes from an IB_PFD packet have completed. +#define PM4_PACKET3_CONTEXT_UPDATE 0xC0005E00 // Updates the current context if needed. + + /****** New Opcodes For R400 (all decode values are TBD) ******/ + + +#endif // _R400IPT_H_ diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_mask.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_mask.h new file mode 100644 index 000000000000..ad3d829bc94e --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_mask.h @@ -0,0 +1,5739 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_MASK_HEADER) +#define _yamato_MASK_HEADER + +// PA_CL_VPORT_XSCALE +#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xffffffffL + +// PA_CL_VPORT_XOFFSET +#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xffffffffL + +// PA_CL_VPORT_YSCALE +#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xffffffffL + +// PA_CL_VPORT_YOFFSET +#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xffffffffL + +// PA_CL_VPORT_ZSCALE +#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xffffffffL + +// PA_CL_VPORT_ZOFFSET +#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xffffffffL + +// PA_CL_VTE_CNTL +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x00000001L +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA 0x00000001L +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x00000002L +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA 0x00000002L +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x00000004L +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA 0x00000004L +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x00000008L +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA 0x00000008L +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x00000010L +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA 0x00000010L +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x00000020L +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA 0x00000020L +#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100L +#define PA_CL_VTE_CNTL__VTX_XY_FMT 0x00000100L +#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200L +#define PA_CL_VTE_CNTL__VTX_Z_FMT 0x00000200L +#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x00000400L +#define PA_CL_VTE_CNTL__VTX_W0_FMT 0x00000400L +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x00000800L +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF 0x00000800L + +// PA_CL_CLIP_CNTL +#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x00010000L +#define PA_CL_CLIP_CNTL__CLIP_DISABLE 0x00010000L +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000L +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA 0x00040000L +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x00080000L +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF 0x00080000L +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x00100000L +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT 0x00100000L +#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x00200000L +#define PA_CL_CLIP_CNTL__VTX_KILL_OR 0x00200000L +#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN_MASK 0x00400000L +#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN 0x00400000L +#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN_MASK 0x00800000L +#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN 0x00800000L +#define PA_CL_CLIP_CNTL__W_NAN_RETAIN_MASK 0x01000000L +#define PA_CL_CLIP_CNTL__W_NAN_RETAIN 0x01000000L + +// PA_CL_GB_VERT_CLIP_ADJ +#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffffL + +// PA_CL_GB_VERT_DISC_ADJ +#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xffffffffL + +// PA_CL_GB_HORZ_CLIP_ADJ +#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffffL + +// PA_CL_GB_HORZ_DISC_ADJ +#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xffffffffL + +// PA_CL_ENHANCE +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x00000001L +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA 0x00000001L +#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000L +#define PA_CL_ENHANCE__ECO_SPARE3 0x10000000L +#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000L +#define PA_CL_ENHANCE__ECO_SPARE2 0x20000000L +#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000L +#define PA_CL_ENHANCE__ECO_SPARE1 0x40000000L +#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000L +#define PA_CL_ENHANCE__ECO_SPARE0 0x80000000L + +// PA_SC_ENHANCE +#define PA_SC_ENHANCE__ECO_SPARE3_MASK 0x10000000L +#define PA_SC_ENHANCE__ECO_SPARE3 0x10000000L +#define PA_SC_ENHANCE__ECO_SPARE2_MASK 0x20000000L +#define PA_SC_ENHANCE__ECO_SPARE2 0x20000000L +#define PA_SC_ENHANCE__ECO_SPARE1_MASK 0x40000000L +#define PA_SC_ENHANCE__ECO_SPARE1 0x40000000L +#define PA_SC_ENHANCE__ECO_SPARE0_MASK 0x80000000L +#define PA_SC_ENHANCE__ECO_SPARE0 0x80000000L + +// PA_SU_VTX_CNTL +#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x00000001L +#define PA_SU_VTX_CNTL__PIX_CENTER 0x00000001L +#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x00000006L +#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x00000038L + +// PA_SU_POINT_SIZE +#define PA_SU_POINT_SIZE__HEIGHT_MASK 0x0000ffffL +#define PA_SU_POINT_SIZE__WIDTH_MASK 0xffff0000L + +// PA_SU_POINT_MINMAX +#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0x0000ffffL +#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xffff0000L + +// PA_SU_LINE_CNTL +#define PA_SU_LINE_CNTL__WIDTH_MASK 0x0000ffffL + +// PA_SU_SC_MODE_CNTL +#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x00000001L +#define PA_SU_SC_MODE_CNTL__CULL_FRONT 0x00000001L +#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x00000002L +#define PA_SU_SC_MODE_CNTL__CULL_BACK 0x00000002L +#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x00000004L +#define PA_SU_SC_MODE_CNTL__FACE 0x00000004L +#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x00000018L +#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0x000000e0L +#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x00000700L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE 0x00000800L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x00001000L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE 0x00001000L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x00002000L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE 0x00002000L +#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE_MASK 0x00008000L +#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE 0x00008000L +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000L +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE 0x00010000L +#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE_MASK 0x00040000L +#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE 0x00040000L +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x00080000L +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST 0x00080000L +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x00100000L +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS 0x00100000L +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x00200000L +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA 0x00200000L +#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE_MASK 0x00800000L +#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE 0x00800000L +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI_MASK 0x02000000L +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI 0x02000000L +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK 0x04000000L +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE 0x04000000L + +// PA_SU_POLY_OFFSET_FRONT_SCALE +#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xffffffffL + +// PA_SU_POLY_OFFSET_FRONT_OFFSET +#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xffffffffL + +// PA_SU_POLY_OFFSET_BACK_SCALE +#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xffffffffL + +// PA_SU_POLY_OFFSET_BACK_OFFSET +#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER0_SELECT +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SU_PERFCOUNTER1_SELECT +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SU_PERFCOUNTER2_SELECT +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SU_PERFCOUNTER3_SELECT +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SU_PERFCOUNTER0_LOW +#define PA_SU_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER0_HI +#define PA_SU_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_SU_PERFCOUNTER1_LOW +#define PA_SU_PERFCOUNTER1_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER1_HI +#define PA_SU_PERFCOUNTER1_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_SU_PERFCOUNTER2_LOW +#define PA_SU_PERFCOUNTER2_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER2_HI +#define PA_SU_PERFCOUNTER2_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_SU_PERFCOUNTER3_LOW +#define PA_SU_PERFCOUNTER3_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER3_HI +#define PA_SU_PERFCOUNTER3_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_SC_WINDOW_OFFSET +#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0x00007fffL +#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0x7fff0000L + +// PA_SC_AA_CONFIG +#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x00000007L +#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x0001e000L + +// PA_SC_AA_MASK +#define PA_SC_AA_MASK__AA_MASK_MASK 0x0000ffffL + +// PA_SC_LINE_STIPPLE +#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0x0000ffffL +#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0x00ff0000L +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000L +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER 0x10000000L +#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000L + +// PA_SC_LINE_CNTL +#define PA_SC_LINE_CNTL__BRES_CNTL_MASK 0x000000ffL +#define PA_SC_LINE_CNTL__USE_BRES_CNTL_MASK 0x00000100L +#define PA_SC_LINE_CNTL__USE_BRES_CNTL 0x00000100L +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x00000200L +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH 0x00000200L +#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x00000400L +#define PA_SC_LINE_CNTL__LAST_PIXEL 0x00000400L + +// PA_SC_WINDOW_SCISSOR_TL +#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x00003fffL +#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x3fff0000L +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE 0x80000000L + +// PA_SC_WINDOW_SCISSOR_BR +#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x00003fffL +#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x3fff0000L + +// PA_SC_SCREEN_SCISSOR_TL +#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0x00007fffL +#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0x7fff0000L + +// PA_SC_SCREEN_SCISSOR_BR +#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0x00007fffL +#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0x7fff0000L + +// PA_SC_VIZ_QUERY +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA_MASK 0x00000001L +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA 0x00000001L +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ID_MASK 0x0000003eL +#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z_MASK 0x00000080L +#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z 0x00000080L + +// PA_SC_VIZ_QUERY_STATUS +#define PA_SC_VIZ_QUERY_STATUS__STATUS_BITS_MASK 0xffffffffL + +// PA_SC_LINE_STIPPLE_STATE +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0x0000000fL +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0x0000ff00L + +// PA_SC_PERFCOUNTER0_SELECT +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SC_PERFCOUNTER0_LOW +#define PA_SC_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SC_PERFCOUNTER0_HI +#define PA_SC_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_CL_CNTL_STATUS +#define PA_CL_CNTL_STATUS__CL_BUSY_MASK 0x80000000L +#define PA_CL_CNTL_STATUS__CL_BUSY 0x80000000L + +// PA_SU_CNTL_STATUS +#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000L +#define PA_SU_CNTL_STATUS__SU_BUSY 0x80000000L + +// PA_SC_CNTL_STATUS +#define PA_SC_CNTL_STATUS__SC_BUSY_MASK 0x80000000L +#define PA_SC_CNTL_STATUS__SC_BUSY 0x80000000L + +// PA_SU_DEBUG_CNTL +#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK 0x0000001fL + +// PA_SU_DEBUG_DATA +#define PA_SU_DEBUG_DATA__DATA_MASK 0xffffffffL + +// CLIPPER_DEBUG_REG00 +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK 0x00000001L +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write 0x00000001L +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full_MASK 0x00000002L +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full 0x00000002L +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK 0x00000004L +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write 0x00000004L +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK 0x00000008L +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full 0x00000008L +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x00000010L +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty 0x00000010L +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x00000020L +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full 0x00000020L +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x00000040L +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty 0x00000040L +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK 0x00000080L +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full 0x00000080L +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK 0x00000100L +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty 0x00000100L +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK 0x00000200L +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full 0x00000200L +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK 0x00000400L +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty 0x00000400L +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK 0x00000800L +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full 0x00000800L +#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x00001000L +#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty 0x00001000L +#define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK 0x00002000L +#define CLIPPER_DEBUG_REG00__clipcode_fifo_full 0x00002000L +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x00004000L +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty 0x00004000L +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x00008000L +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full 0x00008000L +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x00010000L +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty 0x00010000L +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x00020000L +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full 0x00020000L +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x00040000L +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty 0x00040000L +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x00080000L +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full 0x00080000L +#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK 0xfff00000L + +// CLIPPER_DEBUG_REG01 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet_MASK 0x00000001L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet 0x00000001L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot_MASK 0x00000002L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot 0x00000002L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0x0000001cL +#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim_MASK 0x00000020L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim 0x00000020L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x00000040L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive 0x00000040L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_2_MASK 0x00000780L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_1_MASK 0x00007800L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_0_MASK 0x00078000L +#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK 0x00380000L +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0x00c00000L +#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK 0xff000000L + +// CLIPPER_DEBUG_REG02 +#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO1_MASK 0x001fffffL +#define CLIPPER_DEBUG_REG02__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00e00000L +#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO0_MASK 0x7f000000L +#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000L +#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid 0x80000000L + +// CLIPPER_DEBUG_REG03 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO3_MASK 0x00000007L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x00000008L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive 0x00000008L +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO2_MASK 0x00000070L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x00000080L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive 0x00000080L +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO1_MASK 0x000fff00L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x03f00000L +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO0_MASK 0xfc000000L + +// CLIPPER_DEBUG_REG04 +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO2_MASK 0x00000007L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x00000008L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot 0x00000008L +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO1_MASK 0x00000070L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x00000080L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event 0x00000080L +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO0_MASK 0xffffff00L + +// CLIPPER_DEBUG_REG05 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx_MASK 0x00000001L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx 0x00000001L +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO3_MASK 0x00000006L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x00000038L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_event_id_MASK 0x00000fc0L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0000f000L +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO2_MASK 0x00030000L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x003c0000L +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO1_MASK 0x00c00000L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x0f000000L +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO0_MASK 0xf0000000L + +// CLIPPER_DEBUG_REG09 +#define CLIPPER_DEBUG_REG09__clprim_in_back_event_MASK 0x00000001L +#define CLIPPER_DEBUG_REG09__clprim_in_back_event 0x00000001L +#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive_MASK 0x00000002L +#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive 0x00000002L +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_2_MASK 0x0000003cL +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO2_MASK 0x000000c0L +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_1_MASK 0x00000f00L +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO1_MASK 0x00003000L +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_0_MASK 0x0003c000L +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO0_MASK 0x000c0000L +#define CLIPPER_DEBUG_REG09__prim_back_valid_MASK 0x00100000L +#define CLIPPER_DEBUG_REG09__prim_back_valid 0x00100000L +#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_out_cnt_MASK 0x01e00000L +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_orig_vertices_MASK 0x06000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait_MASK 0x08000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait 0x08000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty_MASK 0x10000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty 0x10000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full_MASK 0x20000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full 0x20000000L +#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_load_MASK 0xc0000000L + +// CLIPPER_DEBUG_REG10 +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x0000000fL +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO3_MASK 0x00000030L +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x000003c0L +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO2_MASK 0x00000c00L +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x0000f000L +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO1_MASK 0x00030000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx_MASK 0x00040000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx 0x00040000L +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO0_MASK 0x00180000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet_MASK 0x00200000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet 0x00200000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot_MASK 0x00400000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot 0x00400000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_deallocate_slot_MASK 0x03800000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_event_id_MASK 0xfc000000L + +// CLIPPER_DEBUG_REG11 +#define CLIPPER_DEBUG_REG11__vertval_bits_vertex_vertex_store_msb_MASK 0x0000000fL +#define CLIPPER_DEBUG_REG11__ALWAYS_ZERO_MASK 0xfffffff0L + +// CLIPPER_DEBUG_REG12 +#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x00000003L +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO2_MASK 0x0000001cL +#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty_MASK 0x00000020L +#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty 0x00000020L +#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x000007c0L +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO1_MASK 0x00007800L +#define CLIPPER_DEBUG_REG12__vertval_bits_vertex_cc_next_valid_MASK 0x00078000L +#define CLIPPER_DEBUG_REG12__clipcc_vertex_store_indx_MASK 0x00180000L +#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid_MASK 0x00200000L +#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid 0x00200000L +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO0_MASK 0xffc00000L + +// CLIPPER_DEBUG_REG13 +#define CLIPPER_DEBUG_REG13__sm0_clip_vert_cnt_MASK 0x0000000fL +#define CLIPPER_DEBUG_REG13__sm0_prim_end_state_MASK 0x000007f0L +#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO1_MASK 0x00003800L +#define CLIPPER_DEBUG_REG13__sm0_vertex_clip_cnt_MASK 0x0003c000L +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1_MASK 0x00040000L +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1 0x00040000L +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0_MASK 0x00080000L +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0 0x00080000L +#define CLIPPER_DEBUG_REG13__sm0_current_state_MASK 0x07f00000L +#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO0_MASK 0xf8000000L + +// SXIFCCG_DEBUG_REG0 +#define SXIFCCG_DEBUG_REG0__nan_kill_flag_MASK 0x0000000fL +#define SXIFCCG_DEBUG_REG0__position_address_MASK 0x00000070L +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO2_MASK 0x00000380L +#define SXIFCCG_DEBUG_REG0__point_address_MASK 0x00001c00L +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO1_MASK 0x0000e000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx_MASK 0x00010000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx 0x00010000L +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO0_MASK 0x00060000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask_MASK 0x00780000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci_MASK 0x3f800000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc_MASK 0x40000000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc 0x40000000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel_MASK 0x80000000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel 0x80000000L + +// SXIFCCG_DEBUG_REG1 +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO3_MASK 0x00000003L +#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_MASK 0x0000000cL +#define SXIFCCG_DEBUG_REG1__available_positions_MASK 0x00000070L +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO2_MASK 0x00000780L +#define SXIFCCG_DEBUG_REG1__sx_pending_advance_MASK 0x00000800L +#define SXIFCCG_DEBUG_REG1__sx_pending_advance 0x00000800L +#define SXIFCCG_DEBUG_REG1__sx_receive_indx_MASK 0x00007000L +#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector_MASK 0x00008000L +#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector 0x00008000L +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO1_MASK 0x000f0000L +#define SXIFCCG_DEBUG_REG1__aux_sel_MASK 0x00100000L +#define SXIFCCG_DEBUG_REG1__aux_sel 0x00100000L +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO0_MASK 0x00600000L +#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_MASK 0x01800000L +#define SXIFCCG_DEBUG_REG1__param_cache_base_MASK 0xfe000000L + +// SXIFCCG_DEBUG_REG2 +#define SXIFCCG_DEBUG_REG2__sx_sent_MASK 0x00000001L +#define SXIFCCG_DEBUG_REG2__sx_sent 0x00000001L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3_MASK 0x00000002L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3 0x00000002L +#define SXIFCCG_DEBUG_REG2__sx_aux_MASK 0x00000004L +#define SXIFCCG_DEBUG_REG2__sx_aux 0x00000004L +#define SXIFCCG_DEBUG_REG2__sx_request_indx_MASK 0x000001f8L +#define SXIFCCG_DEBUG_REG2__req_active_verts_MASK 0x0000fe00L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2_MASK 0x00010000L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2 0x00010000L +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx_MASK 0x00020000L +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx 0x00020000L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO1_MASK 0x000c0000L +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts_MASK 0x00300000L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO0_MASK 0x03c00000L +#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded_MASK 0x04000000L +#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded 0x04000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty_MASK 0x08000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty 0x08000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full_MASK 0x10000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full 0x10000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_contents_MASK 0xe0000000L + +// SXIFCCG_DEBUG_REG3 +#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable_MASK 0x0000000fL +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3_MASK 0x00000010L +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3 0x00000010L +#define SXIFCCG_DEBUG_REG3__available_positions_MASK 0x000000e0L +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO2_MASK 0x00000f00L +#define SXIFCCG_DEBUG_REG3__current_state_MASK 0x00003000L +#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty_MASK 0x00004000L +#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty 0x00004000L +#define SXIFCCG_DEBUG_REG3__vertex_fifo_full_MASK 0x00008000L +#define SXIFCCG_DEBUG_REG3__vertex_fifo_full 0x00008000L +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO1_MASK 0x00030000L +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty_MASK 0x00040000L +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty 0x00040000L +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full_MASK 0x00080000L +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full 0x00080000L +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty_MASK 0x00100000L +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty 0x00100000L +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full_MASK 0x00200000L +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full 0x00200000L +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO0_MASK 0xffc00000L + +// SETUP_DEBUG_REG0 +#define SETUP_DEBUG_REG0__su_cntl_state_MASK 0x0000001fL +#define SETUP_DEBUG_REG0__pmode_state_MASK 0x000007e0L +#define SETUP_DEBUG_REG0__ge_stallb_MASK 0x00000800L +#define SETUP_DEBUG_REG0__ge_stallb 0x00000800L +#define SETUP_DEBUG_REG0__geom_enable_MASK 0x00001000L +#define SETUP_DEBUG_REG0__geom_enable 0x00001000L +#define SETUP_DEBUG_REG0__su_clip_baryc_rtr_MASK 0x00002000L +#define SETUP_DEBUG_REG0__su_clip_baryc_rtr 0x00002000L +#define SETUP_DEBUG_REG0__su_clip_rtr_MASK 0x00004000L +#define SETUP_DEBUG_REG0__su_clip_rtr 0x00004000L +#define SETUP_DEBUG_REG0__pfifo_busy_MASK 0x00008000L +#define SETUP_DEBUG_REG0__pfifo_busy 0x00008000L +#define SETUP_DEBUG_REG0__su_cntl_busy_MASK 0x00010000L +#define SETUP_DEBUG_REG0__su_cntl_busy 0x00010000L +#define SETUP_DEBUG_REG0__geom_busy_MASK 0x00020000L +#define SETUP_DEBUG_REG0__geom_busy 0x00020000L + +// SETUP_DEBUG_REG1 +#define SETUP_DEBUG_REG1__y_sort0_gated_17_4_MASK 0x00003fffL +#define SETUP_DEBUG_REG1__x_sort0_gated_17_4_MASK 0x0fffc000L + +// SETUP_DEBUG_REG2 +#define SETUP_DEBUG_REG2__y_sort1_gated_17_4_MASK 0x00003fffL +#define SETUP_DEBUG_REG2__x_sort1_gated_17_4_MASK 0x0fffc000L + +// SETUP_DEBUG_REG3 +#define SETUP_DEBUG_REG3__y_sort2_gated_17_4_MASK 0x00003fffL +#define SETUP_DEBUG_REG3__x_sort2_gated_17_4_MASK 0x0fffc000L + +// SETUP_DEBUG_REG4 +#define SETUP_DEBUG_REG4__attr_indx_sort0_gated_MASK 0x000007ffL +#define SETUP_DEBUG_REG4__null_prim_gated_MASK 0x00000800L +#define SETUP_DEBUG_REG4__null_prim_gated 0x00000800L +#define SETUP_DEBUG_REG4__backfacing_gated_MASK 0x00001000L +#define SETUP_DEBUG_REG4__backfacing_gated 0x00001000L +#define SETUP_DEBUG_REG4__st_indx_gated_MASK 0x0000e000L +#define SETUP_DEBUG_REG4__clipped_gated_MASK 0x00010000L +#define SETUP_DEBUG_REG4__clipped_gated 0x00010000L +#define SETUP_DEBUG_REG4__dealloc_slot_gated_MASK 0x000e0000L +#define SETUP_DEBUG_REG4__xmajor_gated_MASK 0x00100000L +#define SETUP_DEBUG_REG4__xmajor_gated 0x00100000L +#define SETUP_DEBUG_REG4__diamond_rule_gated_MASK 0x00600000L +#define SETUP_DEBUG_REG4__type_gated_MASK 0x03800000L +#define SETUP_DEBUG_REG4__fpov_gated_MASK 0x04000000L +#define SETUP_DEBUG_REG4__fpov_gated 0x04000000L +#define SETUP_DEBUG_REG4__pmode_prim_gated_MASK 0x08000000L +#define SETUP_DEBUG_REG4__pmode_prim_gated 0x08000000L +#define SETUP_DEBUG_REG4__event_gated_MASK 0x10000000L +#define SETUP_DEBUG_REG4__event_gated 0x10000000L +#define SETUP_DEBUG_REG4__eop_gated_MASK 0x20000000L +#define SETUP_DEBUG_REG4__eop_gated 0x20000000L + +// SETUP_DEBUG_REG5 +#define SETUP_DEBUG_REG5__attr_indx_sort2_gated_MASK 0x000007ffL +#define SETUP_DEBUG_REG5__attr_indx_sort1_gated_MASK 0x003ff800L +#define SETUP_DEBUG_REG5__provoking_vtx_gated_MASK 0x00c00000L +#define SETUP_DEBUG_REG5__event_id_gated_MASK 0x1f000000L + +// PA_SC_DEBUG_CNTL +#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK 0x0000001fL + +// PA_SC_DEBUG_DATA +#define PA_SC_DEBUG_DATA__DATA_MASK 0xffffffffL + +// SC_DEBUG_0 +#define SC_DEBUG_0__pa_freeze_b1_MASK 0x00000001L +#define SC_DEBUG_0__pa_freeze_b1 0x00000001L +#define SC_DEBUG_0__pa_sc_valid_MASK 0x00000002L +#define SC_DEBUG_0__pa_sc_valid 0x00000002L +#define SC_DEBUG_0__pa_sc_phase_MASK 0x0000001cL +#define SC_DEBUG_0__cntx_cnt_MASK 0x00000fe0L +#define SC_DEBUG_0__decr_cntx_cnt_MASK 0x00001000L +#define SC_DEBUG_0__decr_cntx_cnt 0x00001000L +#define SC_DEBUG_0__incr_cntx_cnt_MASK 0x00002000L +#define SC_DEBUG_0__incr_cntx_cnt 0x00002000L +#define SC_DEBUG_0__trigger_MASK 0x80000000L +#define SC_DEBUG_0__trigger 0x80000000L + +// SC_DEBUG_1 +#define SC_DEBUG_1__em_state_MASK 0x00000007L +#define SC_DEBUG_1__em1_data_ready_MASK 0x00000008L +#define SC_DEBUG_1__em1_data_ready 0x00000008L +#define SC_DEBUG_1__em2_data_ready_MASK 0x00000010L +#define SC_DEBUG_1__em2_data_ready 0x00000010L +#define SC_DEBUG_1__move_em1_to_em2_MASK 0x00000020L +#define SC_DEBUG_1__move_em1_to_em2 0x00000020L +#define SC_DEBUG_1__ef_data_ready_MASK 0x00000040L +#define SC_DEBUG_1__ef_data_ready 0x00000040L +#define SC_DEBUG_1__ef_state_MASK 0x00000180L +#define SC_DEBUG_1__pipe_valid_MASK 0x00000200L +#define SC_DEBUG_1__pipe_valid 0x00000200L +#define SC_DEBUG_1__trigger_MASK 0x80000000L +#define SC_DEBUG_1__trigger 0x80000000L + +// SC_DEBUG_2 +#define SC_DEBUG_2__rc_rtr_dly_MASK 0x00000001L +#define SC_DEBUG_2__rc_rtr_dly 0x00000001L +#define SC_DEBUG_2__qmask_ff_alm_full_d1_MASK 0x00000002L +#define SC_DEBUG_2__qmask_ff_alm_full_d1 0x00000002L +#define SC_DEBUG_2__pipe_freeze_b_MASK 0x00000008L +#define SC_DEBUG_2__pipe_freeze_b 0x00000008L +#define SC_DEBUG_2__prim_rts_MASK 0x00000010L +#define SC_DEBUG_2__prim_rts 0x00000010L +#define SC_DEBUG_2__next_prim_rts_dly_MASK 0x00000020L +#define SC_DEBUG_2__next_prim_rts_dly 0x00000020L +#define SC_DEBUG_2__next_prim_rtr_dly_MASK 0x00000040L +#define SC_DEBUG_2__next_prim_rtr_dly 0x00000040L +#define SC_DEBUG_2__pre_stage1_rts_d1_MASK 0x00000080L +#define SC_DEBUG_2__pre_stage1_rts_d1 0x00000080L +#define SC_DEBUG_2__stage0_rts_MASK 0x00000100L +#define SC_DEBUG_2__stage0_rts 0x00000100L +#define SC_DEBUG_2__phase_rts_dly_MASK 0x00000200L +#define SC_DEBUG_2__phase_rts_dly 0x00000200L +#define SC_DEBUG_2__end_of_prim_s1_dly_MASK 0x00008000L +#define SC_DEBUG_2__end_of_prim_s1_dly 0x00008000L +#define SC_DEBUG_2__pass_empty_prim_s1_MASK 0x00010000L +#define SC_DEBUG_2__pass_empty_prim_s1 0x00010000L +#define SC_DEBUG_2__event_id_s1_MASK 0x003e0000L +#define SC_DEBUG_2__event_s1_MASK 0x00400000L +#define SC_DEBUG_2__event_s1 0x00400000L +#define SC_DEBUG_2__trigger_MASK 0x80000000L +#define SC_DEBUG_2__trigger 0x80000000L + +// SC_DEBUG_3 +#define SC_DEBUG_3__x_curr_s1_MASK 0x000007ffL +#define SC_DEBUG_3__y_curr_s1_MASK 0x003ff800L +#define SC_DEBUG_3__trigger_MASK 0x80000000L +#define SC_DEBUG_3__trigger 0x80000000L + +// SC_DEBUG_4 +#define SC_DEBUG_4__y_end_s1_MASK 0x00003fffL +#define SC_DEBUG_4__y_start_s1_MASK 0x0fffc000L +#define SC_DEBUG_4__y_dir_s1_MASK 0x10000000L +#define SC_DEBUG_4__y_dir_s1 0x10000000L +#define SC_DEBUG_4__trigger_MASK 0x80000000L +#define SC_DEBUG_4__trigger 0x80000000L + +// SC_DEBUG_5 +#define SC_DEBUG_5__x_end_s1_MASK 0x00003fffL +#define SC_DEBUG_5__x_start_s1_MASK 0x0fffc000L +#define SC_DEBUG_5__x_dir_s1_MASK 0x10000000L +#define SC_DEBUG_5__x_dir_s1 0x10000000L +#define SC_DEBUG_5__trigger_MASK 0x80000000L +#define SC_DEBUG_5__trigger 0x80000000L + +// SC_DEBUG_6 +#define SC_DEBUG_6__z_ff_empty_MASK 0x00000001L +#define SC_DEBUG_6__z_ff_empty 0x00000001L +#define SC_DEBUG_6__qmcntl_ff_empty_MASK 0x00000002L +#define SC_DEBUG_6__qmcntl_ff_empty 0x00000002L +#define SC_DEBUG_6__xy_ff_empty_MASK 0x00000004L +#define SC_DEBUG_6__xy_ff_empty 0x00000004L +#define SC_DEBUG_6__event_flag_MASK 0x00000008L +#define SC_DEBUG_6__event_flag 0x00000008L +#define SC_DEBUG_6__z_mask_needed_MASK 0x00000010L +#define SC_DEBUG_6__z_mask_needed 0x00000010L +#define SC_DEBUG_6__state_MASK 0x000000e0L +#define SC_DEBUG_6__state_delayed_MASK 0x00000700L +#define SC_DEBUG_6__data_valid_MASK 0x00000800L +#define SC_DEBUG_6__data_valid 0x00000800L +#define SC_DEBUG_6__data_valid_d_MASK 0x00001000L +#define SC_DEBUG_6__data_valid_d 0x00001000L +#define SC_DEBUG_6__tilex_delayed_MASK 0x003fe000L +#define SC_DEBUG_6__tiley_delayed_MASK 0x7fc00000L +#define SC_DEBUG_6__trigger_MASK 0x80000000L +#define SC_DEBUG_6__trigger 0x80000000L + +// SC_DEBUG_7 +#define SC_DEBUG_7__event_flag_MASK 0x00000001L +#define SC_DEBUG_7__event_flag 0x00000001L +#define SC_DEBUG_7__deallocate_MASK 0x0000000eL +#define SC_DEBUG_7__fpos_MASK 0x00000010L +#define SC_DEBUG_7__fpos 0x00000010L +#define SC_DEBUG_7__sr_prim_we_MASK 0x00000020L +#define SC_DEBUG_7__sr_prim_we 0x00000020L +#define SC_DEBUG_7__last_tile_MASK 0x00000040L +#define SC_DEBUG_7__last_tile 0x00000040L +#define SC_DEBUG_7__tile_ff_we_MASK 0x00000080L +#define SC_DEBUG_7__tile_ff_we 0x00000080L +#define SC_DEBUG_7__qs_data_valid_MASK 0x00000100L +#define SC_DEBUG_7__qs_data_valid 0x00000100L +#define SC_DEBUG_7__qs_q0_y_MASK 0x00000600L +#define SC_DEBUG_7__qs_q0_x_MASK 0x00001800L +#define SC_DEBUG_7__qs_q0_valid_MASK 0x00002000L +#define SC_DEBUG_7__qs_q0_valid 0x00002000L +#define SC_DEBUG_7__prim_ff_we_MASK 0x00004000L +#define SC_DEBUG_7__prim_ff_we 0x00004000L +#define SC_DEBUG_7__tile_ff_re_MASK 0x00008000L +#define SC_DEBUG_7__tile_ff_re 0x00008000L +#define SC_DEBUG_7__fw_prim_data_valid_MASK 0x00010000L +#define SC_DEBUG_7__fw_prim_data_valid 0x00010000L +#define SC_DEBUG_7__last_quad_of_tile_MASK 0x00020000L +#define SC_DEBUG_7__last_quad_of_tile 0x00020000L +#define SC_DEBUG_7__first_quad_of_tile_MASK 0x00040000L +#define SC_DEBUG_7__first_quad_of_tile 0x00040000L +#define SC_DEBUG_7__first_quad_of_prim_MASK 0x00080000L +#define SC_DEBUG_7__first_quad_of_prim 0x00080000L +#define SC_DEBUG_7__new_prim_MASK 0x00100000L +#define SC_DEBUG_7__new_prim 0x00100000L +#define SC_DEBUG_7__load_new_tile_data_MASK 0x00200000L +#define SC_DEBUG_7__load_new_tile_data 0x00200000L +#define SC_DEBUG_7__state_MASK 0x00c00000L +#define SC_DEBUG_7__fifos_ready_MASK 0x01000000L +#define SC_DEBUG_7__fifos_ready 0x01000000L +#define SC_DEBUG_7__trigger_MASK 0x80000000L +#define SC_DEBUG_7__trigger 0x80000000L + +// SC_DEBUG_8 +#define SC_DEBUG_8__sample_last_MASK 0x00000001L +#define SC_DEBUG_8__sample_last 0x00000001L +#define SC_DEBUG_8__sample_mask_MASK 0x0000001eL +#define SC_DEBUG_8__sample_y_MASK 0x00000060L +#define SC_DEBUG_8__sample_x_MASK 0x00000180L +#define SC_DEBUG_8__sample_send_MASK 0x00000200L +#define SC_DEBUG_8__sample_send 0x00000200L +#define SC_DEBUG_8__next_cycle_MASK 0x00000c00L +#define SC_DEBUG_8__ez_sample_ff_full_MASK 0x00001000L +#define SC_DEBUG_8__ez_sample_ff_full 0x00001000L +#define SC_DEBUG_8__rb_sc_samp_rtr_MASK 0x00002000L +#define SC_DEBUG_8__rb_sc_samp_rtr 0x00002000L +#define SC_DEBUG_8__num_samples_MASK 0x0000c000L +#define SC_DEBUG_8__last_quad_of_tile_MASK 0x00010000L +#define SC_DEBUG_8__last_quad_of_tile 0x00010000L +#define SC_DEBUG_8__last_quad_of_prim_MASK 0x00020000L +#define SC_DEBUG_8__last_quad_of_prim 0x00020000L +#define SC_DEBUG_8__first_quad_of_prim_MASK 0x00040000L +#define SC_DEBUG_8__first_quad_of_prim 0x00040000L +#define SC_DEBUG_8__sample_we_MASK 0x00080000L +#define SC_DEBUG_8__sample_we 0x00080000L +#define SC_DEBUG_8__fpos_MASK 0x00100000L +#define SC_DEBUG_8__fpos 0x00100000L +#define SC_DEBUG_8__event_id_MASK 0x03e00000L +#define SC_DEBUG_8__event_flag_MASK 0x04000000L +#define SC_DEBUG_8__event_flag 0x04000000L +#define SC_DEBUG_8__fw_prim_data_valid_MASK 0x08000000L +#define SC_DEBUG_8__fw_prim_data_valid 0x08000000L +#define SC_DEBUG_8__trigger_MASK 0x80000000L +#define SC_DEBUG_8__trigger 0x80000000L + +// SC_DEBUG_9 +#define SC_DEBUG_9__rb_sc_send_MASK 0x00000001L +#define SC_DEBUG_9__rb_sc_send 0x00000001L +#define SC_DEBUG_9__rb_sc_ez_mask_MASK 0x0000001eL +#define SC_DEBUG_9__fifo_data_ready_MASK 0x00000020L +#define SC_DEBUG_9__fifo_data_ready 0x00000020L +#define SC_DEBUG_9__early_z_enable_MASK 0x00000040L +#define SC_DEBUG_9__early_z_enable 0x00000040L +#define SC_DEBUG_9__mask_state_MASK 0x00000180L +#define SC_DEBUG_9__next_ez_mask_MASK 0x01fffe00L +#define SC_DEBUG_9__mask_ready_MASK 0x02000000L +#define SC_DEBUG_9__mask_ready 0x02000000L +#define SC_DEBUG_9__drop_sample_MASK 0x04000000L +#define SC_DEBUG_9__drop_sample 0x04000000L +#define SC_DEBUG_9__fetch_new_sample_data_MASK 0x08000000L +#define SC_DEBUG_9__fetch_new_sample_data 0x08000000L +#define SC_DEBUG_9__fetch_new_ez_sample_mask_MASK 0x10000000L +#define SC_DEBUG_9__fetch_new_ez_sample_mask 0x10000000L +#define SC_DEBUG_9__pkr_fetch_new_sample_data_MASK 0x20000000L +#define SC_DEBUG_9__pkr_fetch_new_sample_data 0x20000000L +#define SC_DEBUG_9__pkr_fetch_new_prim_data_MASK 0x40000000L +#define SC_DEBUG_9__pkr_fetch_new_prim_data 0x40000000L +#define SC_DEBUG_9__trigger_MASK 0x80000000L +#define SC_DEBUG_9__trigger 0x80000000L + +// SC_DEBUG_10 +#define SC_DEBUG_10__combined_sample_mask_MASK 0x0000ffffL +#define SC_DEBUG_10__trigger_MASK 0x80000000L +#define SC_DEBUG_10__trigger 0x80000000L + +// SC_DEBUG_11 +#define SC_DEBUG_11__ez_sample_data_ready_MASK 0x00000001L +#define SC_DEBUG_11__ez_sample_data_ready 0x00000001L +#define SC_DEBUG_11__pkr_fetch_new_sample_data_MASK 0x00000002L +#define SC_DEBUG_11__pkr_fetch_new_sample_data 0x00000002L +#define SC_DEBUG_11__ez_prim_data_ready_MASK 0x00000004L +#define SC_DEBUG_11__ez_prim_data_ready 0x00000004L +#define SC_DEBUG_11__pkr_fetch_new_prim_data_MASK 0x00000008L +#define SC_DEBUG_11__pkr_fetch_new_prim_data 0x00000008L +#define SC_DEBUG_11__iterator_input_fz_MASK 0x00000010L +#define SC_DEBUG_11__iterator_input_fz 0x00000010L +#define SC_DEBUG_11__packer_send_quads_MASK 0x00000020L +#define SC_DEBUG_11__packer_send_quads 0x00000020L +#define SC_DEBUG_11__packer_send_cmd_MASK 0x00000040L +#define SC_DEBUG_11__packer_send_cmd 0x00000040L +#define SC_DEBUG_11__packer_send_event_MASK 0x00000080L +#define SC_DEBUG_11__packer_send_event 0x00000080L +#define SC_DEBUG_11__next_state_MASK 0x00000700L +#define SC_DEBUG_11__state_MASK 0x00003800L +#define SC_DEBUG_11__stall_MASK 0x00004000L +#define SC_DEBUG_11__stall 0x00004000L +#define SC_DEBUG_11__trigger_MASK 0x80000000L +#define SC_DEBUG_11__trigger 0x80000000L + +// SC_DEBUG_12 +#define SC_DEBUG_12__SQ_iterator_free_buff_MASK 0x00000001L +#define SC_DEBUG_12__SQ_iterator_free_buff 0x00000001L +#define SC_DEBUG_12__event_id_MASK 0x0000003eL +#define SC_DEBUG_12__event_flag_MASK 0x00000040L +#define SC_DEBUG_12__event_flag 0x00000040L +#define SC_DEBUG_12__itercmdfifo_busy_nc_dly_MASK 0x00000080L +#define SC_DEBUG_12__itercmdfifo_busy_nc_dly 0x00000080L +#define SC_DEBUG_12__itercmdfifo_full_MASK 0x00000100L +#define SC_DEBUG_12__itercmdfifo_full 0x00000100L +#define SC_DEBUG_12__itercmdfifo_empty_MASK 0x00000200L +#define SC_DEBUG_12__itercmdfifo_empty 0x00000200L +#define SC_DEBUG_12__iter_ds_one_clk_command_MASK 0x00000400L +#define SC_DEBUG_12__iter_ds_one_clk_command 0x00000400L +#define SC_DEBUG_12__iter_ds_end_of_prim0_MASK 0x00000800L +#define SC_DEBUG_12__iter_ds_end_of_prim0 0x00000800L +#define SC_DEBUG_12__iter_ds_end_of_vector_MASK 0x00001000L +#define SC_DEBUG_12__iter_ds_end_of_vector 0x00001000L +#define SC_DEBUG_12__iter_qdhit0_MASK 0x00002000L +#define SC_DEBUG_12__iter_qdhit0 0x00002000L +#define SC_DEBUG_12__bc_use_centers_reg_MASK 0x00004000L +#define SC_DEBUG_12__bc_use_centers_reg 0x00004000L +#define SC_DEBUG_12__bc_output_xy_reg_MASK 0x00008000L +#define SC_DEBUG_12__bc_output_xy_reg 0x00008000L +#define SC_DEBUG_12__iter_phase_out_MASK 0x00030000L +#define SC_DEBUG_12__iter_phase_reg_MASK 0x000c0000L +#define SC_DEBUG_12__iterator_SP_valid_MASK 0x00100000L +#define SC_DEBUG_12__iterator_SP_valid 0x00100000L +#define SC_DEBUG_12__eopv_reg_MASK 0x00200000L +#define SC_DEBUG_12__eopv_reg 0x00200000L +#define SC_DEBUG_12__one_clk_cmd_reg_MASK 0x00400000L +#define SC_DEBUG_12__one_clk_cmd_reg 0x00400000L +#define SC_DEBUG_12__iter_dx_end_of_prim_MASK 0x00800000L +#define SC_DEBUG_12__iter_dx_end_of_prim 0x00800000L +#define SC_DEBUG_12__trigger_MASK 0x80000000L +#define SC_DEBUG_12__trigger 0x80000000L + +// GFX_COPY_STATE +#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x00000001L +#define GFX_COPY_STATE__SRC_STATE_ID 0x00000001L + +// VGT_DRAW_INITIATOR +#define VGT_DRAW_INITIATOR__PRIM_TYPE_MASK 0x0000003fL +#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x000000c0L +#define VGT_DRAW_INITIATOR__INDEX_SIZE_MASK 0x00000800L +#define VGT_DRAW_INITIATOR__INDEX_SIZE 0x00000800L +#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x00001000L +#define VGT_DRAW_INITIATOR__NOT_EOP 0x00001000L +#define VGT_DRAW_INITIATOR__SMALL_INDEX_MASK 0x00002000L +#define VGT_DRAW_INITIATOR__SMALL_INDEX 0x00002000L +#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE_MASK 0x00004000L +#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE 0x00004000L +#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE_MASK 0x00008000L +#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE 0x00008000L +#define VGT_DRAW_INITIATOR__NUM_INDICES_MASK 0xffff0000L + +// VGT_EVENT_INITIATOR +#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003fL + +// VGT_DMA_BASE +#define VGT_DMA_BASE__BASE_ADDR_MASK 0xffffffffL + +// VGT_DMA_SIZE +#define VGT_DMA_SIZE__NUM_WORDS_MASK 0x00ffffffL +#define VGT_DMA_SIZE__SWAP_MODE_MASK 0xc0000000L + +// VGT_BIN_BASE +#define VGT_BIN_BASE__BIN_BASE_ADDR_MASK 0xffffffffL + +// VGT_BIN_SIZE +#define VGT_BIN_SIZE__NUM_WORDS_MASK 0x00ffffffL + +// VGT_CURRENT_BIN_ID_MIN +#define VGT_CURRENT_BIN_ID_MIN__COLUMN_MASK 0x00000007L +#define VGT_CURRENT_BIN_ID_MIN__ROW_MASK 0x00000038L +#define VGT_CURRENT_BIN_ID_MIN__GUARD_BAND_MASK 0x000001c0L + +// VGT_CURRENT_BIN_ID_MAX +#define VGT_CURRENT_BIN_ID_MAX__COLUMN_MASK 0x00000007L +#define VGT_CURRENT_BIN_ID_MAX__ROW_MASK 0x00000038L +#define VGT_CURRENT_BIN_ID_MAX__GUARD_BAND_MASK 0x000001c0L + +// VGT_IMMED_DATA +#define VGT_IMMED_DATA__DATA_MASK 0xffffffffL + +// VGT_MAX_VTX_INDX +#define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0x00ffffffL + +// VGT_MIN_VTX_INDX +#define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0x00ffffffL + +// VGT_INDX_OFFSET +#define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0x00ffffffL + +// VGT_VERTEX_REUSE_BLOCK_CNTL +#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0x00000007L + +// VGT_OUT_DEALLOC_CNTL +#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x00000003L + +// VGT_MULTI_PRIM_IB_RESET_INDX +#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0x00ffffffL + +// VGT_ENHANCE +#define VGT_ENHANCE__MISC_MASK 0x0000ffffL + +// VGT_VTX_VECT_EJECT_REG +#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x0000001fL + +// VGT_LAST_COPY_STATE +#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x00000001L +#define VGT_LAST_COPY_STATE__SRC_STATE_ID 0x00000001L +#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x00010000L +#define VGT_LAST_COPY_STATE__DST_STATE_ID 0x00010000L + +// VGT_DEBUG_CNTL +#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX_MASK 0x0000001fL + +// VGT_DEBUG_DATA +#define VGT_DEBUG_DATA__DATA_MASK 0xffffffffL + +// VGT_CNTL_STATUS +#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x00000001L +#define VGT_CNTL_STATUS__VGT_BUSY 0x00000001L +#define VGT_CNTL_STATUS__VGT_DMA_BUSY_MASK 0x00000002L +#define VGT_CNTL_STATUS__VGT_DMA_BUSY 0x00000002L +#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY_MASK 0x00000004L +#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY 0x00000004L +#define VGT_CNTL_STATUS__VGT_GRP_BUSY_MASK 0x00000008L +#define VGT_CNTL_STATUS__VGT_GRP_BUSY 0x00000008L +#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x00000010L +#define VGT_CNTL_STATUS__VGT_VR_BUSY 0x00000010L +#define VGT_CNTL_STATUS__VGT_BIN_BUSY_MASK 0x00000020L +#define VGT_CNTL_STATUS__VGT_BIN_BUSY 0x00000020L +#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x00000040L +#define VGT_CNTL_STATUS__VGT_PT_BUSY 0x00000040L +#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x00000080L +#define VGT_CNTL_STATUS__VGT_OUT_BUSY 0x00000080L +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x00000100L +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY 0x00000100L + +// VGT_DEBUG_REG0 +#define VGT_DEBUG_REG0__te_grp_busy_MASK 0x00000001L +#define VGT_DEBUG_REG0__te_grp_busy 0x00000001L +#define VGT_DEBUG_REG0__pt_grp_busy_MASK 0x00000002L +#define VGT_DEBUG_REG0__pt_grp_busy 0x00000002L +#define VGT_DEBUG_REG0__vr_grp_busy_MASK 0x00000004L +#define VGT_DEBUG_REG0__vr_grp_busy 0x00000004L +#define VGT_DEBUG_REG0__dma_request_busy_MASK 0x00000008L +#define VGT_DEBUG_REG0__dma_request_busy 0x00000008L +#define VGT_DEBUG_REG0__out_busy_MASK 0x00000010L +#define VGT_DEBUG_REG0__out_busy 0x00000010L +#define VGT_DEBUG_REG0__grp_backend_busy_MASK 0x00000020L +#define VGT_DEBUG_REG0__grp_backend_busy 0x00000020L +#define VGT_DEBUG_REG0__grp_busy_MASK 0x00000040L +#define VGT_DEBUG_REG0__grp_busy 0x00000040L +#define VGT_DEBUG_REG0__dma_busy_MASK 0x00000080L +#define VGT_DEBUG_REG0__dma_busy 0x00000080L +#define VGT_DEBUG_REG0__rbiu_dma_request_busy_MASK 0x00000100L +#define VGT_DEBUG_REG0__rbiu_dma_request_busy 0x00000100L +#define VGT_DEBUG_REG0__rbiu_busy_MASK 0x00000200L +#define VGT_DEBUG_REG0__rbiu_busy 0x00000200L +#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended_MASK 0x00000400L +#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended 0x00000400L +#define VGT_DEBUG_REG0__vgt_no_dma_busy_MASK 0x00000800L +#define VGT_DEBUG_REG0__vgt_no_dma_busy 0x00000800L +#define VGT_DEBUG_REG0__vgt_busy_extended_MASK 0x00001000L +#define VGT_DEBUG_REG0__vgt_busy_extended 0x00001000L +#define VGT_DEBUG_REG0__vgt_busy_MASK 0x00002000L +#define VGT_DEBUG_REG0__vgt_busy 0x00002000L +#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out_MASK 0x00004000L +#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out 0x00004000L +#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy_MASK 0x00008000L +#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy 0x00008000L +#define VGT_DEBUG_REG0__VGT_RBBM_busy_MASK 0x00010000L +#define VGT_DEBUG_REG0__VGT_RBBM_busy 0x00010000L + +// VGT_DEBUG_REG1 +#define VGT_DEBUG_REG1__out_te_data_read_MASK 0x00000001L +#define VGT_DEBUG_REG1__out_te_data_read 0x00000001L +#define VGT_DEBUG_REG1__te_out_data_valid_MASK 0x00000002L +#define VGT_DEBUG_REG1__te_out_data_valid 0x00000002L +#define VGT_DEBUG_REG1__out_pt_prim_read_MASK 0x00000004L +#define VGT_DEBUG_REG1__out_pt_prim_read 0x00000004L +#define VGT_DEBUG_REG1__pt_out_prim_valid_MASK 0x00000008L +#define VGT_DEBUG_REG1__pt_out_prim_valid 0x00000008L +#define VGT_DEBUG_REG1__out_pt_data_read_MASK 0x00000010L +#define VGT_DEBUG_REG1__out_pt_data_read 0x00000010L +#define VGT_DEBUG_REG1__pt_out_indx_valid_MASK 0x00000020L +#define VGT_DEBUG_REG1__pt_out_indx_valid 0x00000020L +#define VGT_DEBUG_REG1__out_vr_prim_read_MASK 0x00000040L +#define VGT_DEBUG_REG1__out_vr_prim_read 0x00000040L +#define VGT_DEBUG_REG1__vr_out_prim_valid_MASK 0x00000080L +#define VGT_DEBUG_REG1__vr_out_prim_valid 0x00000080L +#define VGT_DEBUG_REG1__out_vr_indx_read_MASK 0x00000100L +#define VGT_DEBUG_REG1__out_vr_indx_read 0x00000100L +#define VGT_DEBUG_REG1__vr_out_indx_valid_MASK 0x00000200L +#define VGT_DEBUG_REG1__vr_out_indx_valid 0x00000200L +#define VGT_DEBUG_REG1__te_grp_read_MASK 0x00000400L +#define VGT_DEBUG_REG1__te_grp_read 0x00000400L +#define VGT_DEBUG_REG1__grp_te_valid_MASK 0x00000800L +#define VGT_DEBUG_REG1__grp_te_valid 0x00000800L +#define VGT_DEBUG_REG1__pt_grp_read_MASK 0x00001000L +#define VGT_DEBUG_REG1__pt_grp_read 0x00001000L +#define VGT_DEBUG_REG1__grp_pt_valid_MASK 0x00002000L +#define VGT_DEBUG_REG1__grp_pt_valid 0x00002000L +#define VGT_DEBUG_REG1__vr_grp_read_MASK 0x00004000L +#define VGT_DEBUG_REG1__vr_grp_read 0x00004000L +#define VGT_DEBUG_REG1__grp_vr_valid_MASK 0x00008000L +#define VGT_DEBUG_REG1__grp_vr_valid 0x00008000L +#define VGT_DEBUG_REG1__grp_dma_read_MASK 0x00010000L +#define VGT_DEBUG_REG1__grp_dma_read 0x00010000L +#define VGT_DEBUG_REG1__dma_grp_valid_MASK 0x00020000L +#define VGT_DEBUG_REG1__dma_grp_valid 0x00020000L +#define VGT_DEBUG_REG1__grp_rbiu_di_read_MASK 0x00040000L +#define VGT_DEBUG_REG1__grp_rbiu_di_read 0x00040000L +#define VGT_DEBUG_REG1__rbiu_grp_di_valid_MASK 0x00080000L +#define VGT_DEBUG_REG1__rbiu_grp_di_valid 0x00080000L +#define VGT_DEBUG_REG1__MH_VGT_rtr_MASK 0x00100000L +#define VGT_DEBUG_REG1__MH_VGT_rtr 0x00100000L +#define VGT_DEBUG_REG1__VGT_MH_send_MASK 0x00200000L +#define VGT_DEBUG_REG1__VGT_MH_send 0x00200000L +#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr_MASK 0x00400000L +#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr 0x00400000L +#define VGT_DEBUG_REG1__VGT_PA_clip_s_send_MASK 0x00800000L +#define VGT_DEBUG_REG1__VGT_PA_clip_s_send 0x00800000L +#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr_MASK 0x01000000L +#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr 0x01000000L +#define VGT_DEBUG_REG1__VGT_PA_clip_p_send_MASK 0x02000000L +#define VGT_DEBUG_REG1__VGT_PA_clip_p_send 0x02000000L +#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr_MASK 0x04000000L +#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr 0x04000000L +#define VGT_DEBUG_REG1__VGT_PA_clip_v_send_MASK 0x08000000L +#define VGT_DEBUG_REG1__VGT_PA_clip_v_send 0x08000000L +#define VGT_DEBUG_REG1__SQ_VGT_rtr_MASK 0x10000000L +#define VGT_DEBUG_REG1__SQ_VGT_rtr 0x10000000L +#define VGT_DEBUG_REG1__VGT_SQ_send_MASK 0x20000000L +#define VGT_DEBUG_REG1__VGT_SQ_send 0x20000000L +#define VGT_DEBUG_REG1__mh_vgt_tag_7_q_MASK 0x40000000L +#define VGT_DEBUG_REG1__mh_vgt_tag_7_q 0x40000000L + +// VGT_DEBUG_REG3 +#define VGT_DEBUG_REG3__vgt_clk_en_MASK 0x00000001L +#define VGT_DEBUG_REG3__vgt_clk_en 0x00000001L +#define VGT_DEBUG_REG3__reg_fifos_clk_en_MASK 0x00000002L +#define VGT_DEBUG_REG3__reg_fifos_clk_en 0x00000002L + +// VGT_DEBUG_REG6 +#define VGT_DEBUG_REG6__shifter_byte_count_q_MASK 0x0000001fL +#define VGT_DEBUG_REG6__right_word_indx_q_MASK 0x000003e0L +#define VGT_DEBUG_REG6__input_data_valid_MASK 0x00000400L +#define VGT_DEBUG_REG6__input_data_valid 0x00000400L +#define VGT_DEBUG_REG6__input_data_xfer_MASK 0x00000800L +#define VGT_DEBUG_REG6__input_data_xfer 0x00000800L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_q_MASK 0x00001000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_q 0x00001000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_d_MASK 0x00002000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_d 0x00002000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d_MASK 0x00004000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d 0x00004000L +#define VGT_DEBUG_REG6__space_avail_from_shift_MASK 0x00008000L +#define VGT_DEBUG_REG6__space_avail_from_shift 0x00008000L +#define VGT_DEBUG_REG6__shifter_first_load_MASK 0x00010000L +#define VGT_DEBUG_REG6__shifter_first_load 0x00010000L +#define VGT_DEBUG_REG6__di_state_sel_q_MASK 0x00020000L +#define VGT_DEBUG_REG6__di_state_sel_q 0x00020000L +#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q_MASK 0x00040000L +#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q 0x00040000L +#define VGT_DEBUG_REG6__di_first_group_flag_q_MASK 0x00080000L +#define VGT_DEBUG_REG6__di_first_group_flag_q 0x00080000L +#define VGT_DEBUG_REG6__di_event_flag_q_MASK 0x00100000L +#define VGT_DEBUG_REG6__di_event_flag_q 0x00100000L +#define VGT_DEBUG_REG6__read_draw_initiator_MASK 0x00200000L +#define VGT_DEBUG_REG6__read_draw_initiator 0x00200000L +#define VGT_DEBUG_REG6__loading_di_requires_shifter_MASK 0x00400000L +#define VGT_DEBUG_REG6__loading_di_requires_shifter 0x00400000L +#define VGT_DEBUG_REG6__last_shift_of_packet_MASK 0x00800000L +#define VGT_DEBUG_REG6__last_shift_of_packet 0x00800000L +#define VGT_DEBUG_REG6__last_decr_of_packet_MASK 0x01000000L +#define VGT_DEBUG_REG6__last_decr_of_packet 0x01000000L +#define VGT_DEBUG_REG6__extract_vector_MASK 0x02000000L +#define VGT_DEBUG_REG6__extract_vector 0x02000000L +#define VGT_DEBUG_REG6__shift_vect_rtr_MASK 0x04000000L +#define VGT_DEBUG_REG6__shift_vect_rtr 0x04000000L +#define VGT_DEBUG_REG6__destination_rtr_MASK 0x08000000L +#define VGT_DEBUG_REG6__destination_rtr 0x08000000L +#define VGT_DEBUG_REG6__grp_trigger_MASK 0x10000000L +#define VGT_DEBUG_REG6__grp_trigger 0x10000000L + +// VGT_DEBUG_REG7 +#define VGT_DEBUG_REG7__di_index_counter_q_MASK 0x0000ffffL +#define VGT_DEBUG_REG7__shift_amount_no_extract_MASK 0x000f0000L +#define VGT_DEBUG_REG7__shift_amount_extract_MASK 0x00f00000L +#define VGT_DEBUG_REG7__di_prim_type_q_MASK 0x3f000000L +#define VGT_DEBUG_REG7__current_source_sel_MASK 0xc0000000L + +// VGT_DEBUG_REG8 +#define VGT_DEBUG_REG8__current_source_sel_MASK 0x00000003L +#define VGT_DEBUG_REG8__left_word_indx_q_MASK 0x0000007cL +#define VGT_DEBUG_REG8__input_data_cnt_MASK 0x00000f80L +#define VGT_DEBUG_REG8__input_data_lsw_MASK 0x0001f000L +#define VGT_DEBUG_REG8__input_data_msw_MASK 0x003e0000L +#define VGT_DEBUG_REG8__next_small_stride_shift_limit_q_MASK 0x07c00000L +#define VGT_DEBUG_REG8__current_small_stride_shift_limit_q_MASK 0xf8000000L + +// VGT_DEBUG_REG9 +#define VGT_DEBUG_REG9__next_stride_q_MASK 0x0000001fL +#define VGT_DEBUG_REG9__next_stride_d_MASK 0x000003e0L +#define VGT_DEBUG_REG9__current_shift_q_MASK 0x00007c00L +#define VGT_DEBUG_REG9__current_shift_d_MASK 0x000f8000L +#define VGT_DEBUG_REG9__current_stride_q_MASK 0x01f00000L +#define VGT_DEBUG_REG9__current_stride_d_MASK 0x3e000000L +#define VGT_DEBUG_REG9__grp_trigger_MASK 0x40000000L +#define VGT_DEBUG_REG9__grp_trigger 0x40000000L + +// VGT_DEBUG_REG10 +#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0_MASK 0x00000001L +#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0 0x00000001L +#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0_MASK 0x00000002L +#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0 0x00000002L +#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0_MASK 0x00000004L +#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0 0x00000004L +#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0_MASK 0x00000008L +#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0 0x00000008L +#define VGT_DEBUG_REG10__di_state_sel_q_MASK 0x00000010L +#define VGT_DEBUG_REG10__di_state_sel_q 0x00000010L +#define VGT_DEBUG_REG10__last_decr_of_packet_MASK 0x00000020L +#define VGT_DEBUG_REG10__last_decr_of_packet 0x00000020L +#define VGT_DEBUG_REG10__bin_valid_MASK 0x00000040L +#define VGT_DEBUG_REG10__bin_valid 0x00000040L +#define VGT_DEBUG_REG10__read_block_MASK 0x00000080L +#define VGT_DEBUG_REG10__read_block 0x00000080L +#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read_MASK 0x00000100L +#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read 0x00000100L +#define VGT_DEBUG_REG10__last_bit_enable_q_MASK 0x00000200L +#define VGT_DEBUG_REG10__last_bit_enable_q 0x00000200L +#define VGT_DEBUG_REG10__last_bit_end_di_q_MASK 0x00000400L +#define VGT_DEBUG_REG10__last_bit_end_di_q 0x00000400L +#define VGT_DEBUG_REG10__selected_data_MASK 0x0007f800L +#define VGT_DEBUG_REG10__mask_input_data_MASK 0x07f80000L +#define VGT_DEBUG_REG10__gap_q_MASK 0x08000000L +#define VGT_DEBUG_REG10__gap_q 0x08000000L +#define VGT_DEBUG_REG10__temp_mini_reset_z_MASK 0x10000000L +#define VGT_DEBUG_REG10__temp_mini_reset_z 0x10000000L +#define VGT_DEBUG_REG10__temp_mini_reset_y_MASK 0x20000000L +#define VGT_DEBUG_REG10__temp_mini_reset_y 0x20000000L +#define VGT_DEBUG_REG10__temp_mini_reset_x_MASK 0x40000000L +#define VGT_DEBUG_REG10__temp_mini_reset_x 0x40000000L +#define VGT_DEBUG_REG10__grp_trigger_MASK 0x80000000L +#define VGT_DEBUG_REG10__grp_trigger 0x80000000L + +// VGT_DEBUG_REG12 +#define VGT_DEBUG_REG12__shifter_byte_count_q_MASK 0x0000001fL +#define VGT_DEBUG_REG12__right_word_indx_q_MASK 0x000003e0L +#define VGT_DEBUG_REG12__input_data_valid_MASK 0x00000400L +#define VGT_DEBUG_REG12__input_data_valid 0x00000400L +#define VGT_DEBUG_REG12__input_data_xfer_MASK 0x00000800L +#define VGT_DEBUG_REG12__input_data_xfer 0x00000800L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_q_MASK 0x00001000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_q 0x00001000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_d_MASK 0x00002000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_d 0x00002000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d_MASK 0x00004000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d 0x00004000L +#define VGT_DEBUG_REG12__space_avail_from_shift_MASK 0x00008000L +#define VGT_DEBUG_REG12__space_avail_from_shift 0x00008000L +#define VGT_DEBUG_REG12__shifter_first_load_MASK 0x00010000L +#define VGT_DEBUG_REG12__shifter_first_load 0x00010000L +#define VGT_DEBUG_REG12__di_state_sel_q_MASK 0x00020000L +#define VGT_DEBUG_REG12__di_state_sel_q 0x00020000L +#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q_MASK 0x00040000L +#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q 0x00040000L +#define VGT_DEBUG_REG12__di_first_group_flag_q_MASK 0x00080000L +#define VGT_DEBUG_REG12__di_first_group_flag_q 0x00080000L +#define VGT_DEBUG_REG12__di_event_flag_q_MASK 0x00100000L +#define VGT_DEBUG_REG12__di_event_flag_q 0x00100000L +#define VGT_DEBUG_REG12__read_draw_initiator_MASK 0x00200000L +#define VGT_DEBUG_REG12__read_draw_initiator 0x00200000L +#define VGT_DEBUG_REG12__loading_di_requires_shifter_MASK 0x00400000L +#define VGT_DEBUG_REG12__loading_di_requires_shifter 0x00400000L +#define VGT_DEBUG_REG12__last_shift_of_packet_MASK 0x00800000L +#define VGT_DEBUG_REG12__last_shift_of_packet 0x00800000L +#define VGT_DEBUG_REG12__last_decr_of_packet_MASK 0x01000000L +#define VGT_DEBUG_REG12__last_decr_of_packet 0x01000000L +#define VGT_DEBUG_REG12__extract_vector_MASK 0x02000000L +#define VGT_DEBUG_REG12__extract_vector 0x02000000L +#define VGT_DEBUG_REG12__shift_vect_rtr_MASK 0x04000000L +#define VGT_DEBUG_REG12__shift_vect_rtr 0x04000000L +#define VGT_DEBUG_REG12__destination_rtr_MASK 0x08000000L +#define VGT_DEBUG_REG12__destination_rtr 0x08000000L +#define VGT_DEBUG_REG12__bgrp_trigger_MASK 0x10000000L +#define VGT_DEBUG_REG12__bgrp_trigger 0x10000000L + +// VGT_DEBUG_REG13 +#define VGT_DEBUG_REG13__di_index_counter_q_MASK 0x0000ffffL +#define VGT_DEBUG_REG13__shift_amount_no_extract_MASK 0x000f0000L +#define VGT_DEBUG_REG13__shift_amount_extract_MASK 0x00f00000L +#define VGT_DEBUG_REG13__di_prim_type_q_MASK 0x3f000000L +#define VGT_DEBUG_REG13__current_source_sel_MASK 0xc0000000L + +// VGT_DEBUG_REG14 +#define VGT_DEBUG_REG14__current_source_sel_MASK 0x00000003L +#define VGT_DEBUG_REG14__left_word_indx_q_MASK 0x0000007cL +#define VGT_DEBUG_REG14__input_data_cnt_MASK 0x00000f80L +#define VGT_DEBUG_REG14__input_data_lsw_MASK 0x0001f000L +#define VGT_DEBUG_REG14__input_data_msw_MASK 0x003e0000L +#define VGT_DEBUG_REG14__next_small_stride_shift_limit_q_MASK 0x07c00000L +#define VGT_DEBUG_REG14__current_small_stride_shift_limit_q_MASK 0xf8000000L + +// VGT_DEBUG_REG15 +#define VGT_DEBUG_REG15__next_stride_q_MASK 0x0000001fL +#define VGT_DEBUG_REG15__next_stride_d_MASK 0x000003e0L +#define VGT_DEBUG_REG15__current_shift_q_MASK 0x00007c00L +#define VGT_DEBUG_REG15__current_shift_d_MASK 0x000f8000L +#define VGT_DEBUG_REG15__current_stride_q_MASK 0x01f00000L +#define VGT_DEBUG_REG15__current_stride_d_MASK 0x3e000000L +#define VGT_DEBUG_REG15__bgrp_trigger_MASK 0x40000000L +#define VGT_DEBUG_REG15__bgrp_trigger 0x40000000L + +// VGT_DEBUG_REG16 +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full_MASK 0x00000001L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full 0x00000001L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty_MASK 0x00000002L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty 0x00000002L +#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read_MASK 0x00000004L +#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read 0x00000004L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we_MASK 0x00000008L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we 0x00000008L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full_MASK 0x00000010L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full 0x00000010L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty_MASK 0x00000020L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty 0x00000020L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q_MASK 0x00000040L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q 0x00000040L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we_MASK 0x00000080L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we 0x00000080L +#define VGT_DEBUG_REG16__bgrp_dma_mask_kill_MASK 0x00000100L +#define VGT_DEBUG_REG16__bgrp_dma_mask_kill 0x00000100L +#define VGT_DEBUG_REG16__bgrp_grp_bin_valid_MASK 0x00000200L +#define VGT_DEBUG_REG16__bgrp_grp_bin_valid 0x00000200L +#define VGT_DEBUG_REG16__rst_last_bit_MASK 0x00000400L +#define VGT_DEBUG_REG16__rst_last_bit 0x00000400L +#define VGT_DEBUG_REG16__current_state_q_MASK 0x00000800L +#define VGT_DEBUG_REG16__current_state_q 0x00000800L +#define VGT_DEBUG_REG16__old_state_q_MASK 0x00001000L +#define VGT_DEBUG_REG16__old_state_q 0x00001000L +#define VGT_DEBUG_REG16__old_state_en_MASK 0x00002000L +#define VGT_DEBUG_REG16__old_state_en 0x00002000L +#define VGT_DEBUG_REG16__prev_last_bit_q_MASK 0x00004000L +#define VGT_DEBUG_REG16__prev_last_bit_q 0x00004000L +#define VGT_DEBUG_REG16__dbl_last_bit_q_MASK 0x00008000L +#define VGT_DEBUG_REG16__dbl_last_bit_q 0x00008000L +#define VGT_DEBUG_REG16__last_bit_block_q_MASK 0x00010000L +#define VGT_DEBUG_REG16__last_bit_block_q 0x00010000L +#define VGT_DEBUG_REG16__ast_bit_block2_q_MASK 0x00020000L +#define VGT_DEBUG_REG16__ast_bit_block2_q 0x00020000L +#define VGT_DEBUG_REG16__load_empty_reg_MASK 0x00040000L +#define VGT_DEBUG_REG16__load_empty_reg 0x00040000L +#define VGT_DEBUG_REG16__bgrp_grp_byte_mask_rdata_MASK 0x07f80000L +#define VGT_DEBUG_REG16__dma_bgrp_dma_data_fifo_rptr_MASK 0x18000000L +#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable_MASK 0x20000000L +#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable 0x20000000L +#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q_MASK 0x40000000L +#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q 0x40000000L +#define VGT_DEBUG_REG16__bgrp_trigger_MASK 0x80000000L +#define VGT_DEBUG_REG16__bgrp_trigger 0x80000000L + +// VGT_DEBUG_REG17 +#define VGT_DEBUG_REG17__save_read_q_MASK 0x00000001L +#define VGT_DEBUG_REG17__save_read_q 0x00000001L +#define VGT_DEBUG_REG17__extend_read_q_MASK 0x00000002L +#define VGT_DEBUG_REG17__extend_read_q 0x00000002L +#define VGT_DEBUG_REG17__grp_indx_size_MASK 0x0000000cL +#define VGT_DEBUG_REG17__cull_prim_true_MASK 0x00000010L +#define VGT_DEBUG_REG17__cull_prim_true 0x00000010L +#define VGT_DEBUG_REG17__reset_bit2_q_MASK 0x00000020L +#define VGT_DEBUG_REG17__reset_bit2_q 0x00000020L +#define VGT_DEBUG_REG17__reset_bit1_q_MASK 0x00000040L +#define VGT_DEBUG_REG17__reset_bit1_q 0x00000040L +#define VGT_DEBUG_REG17__first_reg_first_q_MASK 0x00000080L +#define VGT_DEBUG_REG17__first_reg_first_q 0x00000080L +#define VGT_DEBUG_REG17__check_second_reg_MASK 0x00000100L +#define VGT_DEBUG_REG17__check_second_reg 0x00000100L +#define VGT_DEBUG_REG17__check_first_reg_MASK 0x00000200L +#define VGT_DEBUG_REG17__check_first_reg 0x00000200L +#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata_MASK 0x00000400L +#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata 0x00000400L +#define VGT_DEBUG_REG17__save_cull_fetch_data2_q_MASK 0x00000800L +#define VGT_DEBUG_REG17__save_cull_fetch_data2_q 0x00000800L +#define VGT_DEBUG_REG17__save_cull_fetch_data1_q_MASK 0x00001000L +#define VGT_DEBUG_REG17__save_cull_fetch_data1_q 0x00001000L +#define VGT_DEBUG_REG17__save_byte_mask_data2_q_MASK 0x00002000L +#define VGT_DEBUG_REG17__save_byte_mask_data2_q 0x00002000L +#define VGT_DEBUG_REG17__save_byte_mask_data1_q_MASK 0x00004000L +#define VGT_DEBUG_REG17__save_byte_mask_data1_q 0x00004000L +#define VGT_DEBUG_REG17__to_second_reg_q_MASK 0x00008000L +#define VGT_DEBUG_REG17__to_second_reg_q 0x00008000L +#define VGT_DEBUG_REG17__roll_over_msk_q_MASK 0x00010000L +#define VGT_DEBUG_REG17__roll_over_msk_q 0x00010000L +#define VGT_DEBUG_REG17__max_msk_ptr_q_MASK 0x00fe0000L +#define VGT_DEBUG_REG17__min_msk_ptr_q_MASK 0x7f000000L +#define VGT_DEBUG_REG17__bgrp_trigger_MASK 0x80000000L +#define VGT_DEBUG_REG17__bgrp_trigger 0x80000000L + +// VGT_DEBUG_REG18 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_raddr_MASK 0x0000003fL +#define VGT_DEBUG_REG18__dma_data_fifo_mem_waddr_MASK 0x00000fc0L +#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re_MASK 0x00001000L +#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re 0x00001000L +#define VGT_DEBUG_REG18__dma_bgrp_dma_data_fifo_rptr_MASK 0x00006000L +#define VGT_DEBUG_REG18__dma_mem_full_MASK 0x00008000L +#define VGT_DEBUG_REG18__dma_mem_full 0x00008000L +#define VGT_DEBUG_REG18__dma_ram_re_MASK 0x00010000L +#define VGT_DEBUG_REG18__dma_ram_re 0x00010000L +#define VGT_DEBUG_REG18__dma_ram_we_MASK 0x00020000L +#define VGT_DEBUG_REG18__dma_ram_we 0x00020000L +#define VGT_DEBUG_REG18__dma_mem_empty_MASK 0x00040000L +#define VGT_DEBUG_REG18__dma_mem_empty 0x00040000L +#define VGT_DEBUG_REG18__dma_data_fifo_mem_re_MASK 0x00080000L +#define VGT_DEBUG_REG18__dma_data_fifo_mem_re 0x00080000L +#define VGT_DEBUG_REG18__dma_data_fifo_mem_we_MASK 0x00100000L +#define VGT_DEBUG_REG18__dma_data_fifo_mem_we 0x00100000L +#define VGT_DEBUG_REG18__bin_mem_full_MASK 0x00200000L +#define VGT_DEBUG_REG18__bin_mem_full 0x00200000L +#define VGT_DEBUG_REG18__bin_ram_we_MASK 0x00400000L +#define VGT_DEBUG_REG18__bin_ram_we 0x00400000L +#define VGT_DEBUG_REG18__bin_ram_re_MASK 0x00800000L +#define VGT_DEBUG_REG18__bin_ram_re 0x00800000L +#define VGT_DEBUG_REG18__bin_mem_empty_MASK 0x01000000L +#define VGT_DEBUG_REG18__bin_mem_empty 0x01000000L +#define VGT_DEBUG_REG18__start_bin_req_MASK 0x02000000L +#define VGT_DEBUG_REG18__start_bin_req 0x02000000L +#define VGT_DEBUG_REG18__fetch_cull_not_used_MASK 0x04000000L +#define VGT_DEBUG_REG18__fetch_cull_not_used 0x04000000L +#define VGT_DEBUG_REG18__dma_req_xfer_MASK 0x08000000L +#define VGT_DEBUG_REG18__dma_req_xfer 0x08000000L +#define VGT_DEBUG_REG18__have_valid_bin_req_MASK 0x10000000L +#define VGT_DEBUG_REG18__have_valid_bin_req 0x10000000L +#define VGT_DEBUG_REG18__have_valid_dma_req_MASK 0x20000000L +#define VGT_DEBUG_REG18__have_valid_dma_req 0x20000000L +#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable_MASK 0x40000000L +#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable 0x40000000L +#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable_MASK 0x80000000L +#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable 0x80000000L + +// VGT_DEBUG_REG20 +#define VGT_DEBUG_REG20__prim_side_indx_valid_MASK 0x00000001L +#define VGT_DEBUG_REG20__prim_side_indx_valid 0x00000001L +#define VGT_DEBUG_REG20__indx_side_fifo_empty_MASK 0x00000002L +#define VGT_DEBUG_REG20__indx_side_fifo_empty 0x00000002L +#define VGT_DEBUG_REG20__indx_side_fifo_re_MASK 0x00000004L +#define VGT_DEBUG_REG20__indx_side_fifo_re 0x00000004L +#define VGT_DEBUG_REG20__indx_side_fifo_we_MASK 0x00000008L +#define VGT_DEBUG_REG20__indx_side_fifo_we 0x00000008L +#define VGT_DEBUG_REG20__indx_side_fifo_full_MASK 0x00000010L +#define VGT_DEBUG_REG20__indx_side_fifo_full 0x00000010L +#define VGT_DEBUG_REG20__prim_buffer_empty_MASK 0x00000020L +#define VGT_DEBUG_REG20__prim_buffer_empty 0x00000020L +#define VGT_DEBUG_REG20__prim_buffer_re_MASK 0x00000040L +#define VGT_DEBUG_REG20__prim_buffer_re 0x00000040L +#define VGT_DEBUG_REG20__prim_buffer_we_MASK 0x00000080L +#define VGT_DEBUG_REG20__prim_buffer_we 0x00000080L +#define VGT_DEBUG_REG20__prim_buffer_full_MASK 0x00000100L +#define VGT_DEBUG_REG20__prim_buffer_full 0x00000100L +#define VGT_DEBUG_REG20__indx_buffer_empty_MASK 0x00000200L +#define VGT_DEBUG_REG20__indx_buffer_empty 0x00000200L +#define VGT_DEBUG_REG20__indx_buffer_re_MASK 0x00000400L +#define VGT_DEBUG_REG20__indx_buffer_re 0x00000400L +#define VGT_DEBUG_REG20__indx_buffer_we_MASK 0x00000800L +#define VGT_DEBUG_REG20__indx_buffer_we 0x00000800L +#define VGT_DEBUG_REG20__indx_buffer_full_MASK 0x00001000L +#define VGT_DEBUG_REG20__indx_buffer_full 0x00001000L +#define VGT_DEBUG_REG20__hold_prim_MASK 0x00002000L +#define VGT_DEBUG_REG20__hold_prim 0x00002000L +#define VGT_DEBUG_REG20__sent_cnt_MASK 0x0003c000L +#define VGT_DEBUG_REG20__start_of_vtx_vector_MASK 0x00040000L +#define VGT_DEBUG_REG20__start_of_vtx_vector 0x00040000L +#define VGT_DEBUG_REG20__clip_s_pre_hold_prim_MASK 0x00080000L +#define VGT_DEBUG_REG20__clip_s_pre_hold_prim 0x00080000L +#define VGT_DEBUG_REG20__clip_p_pre_hold_prim_MASK 0x00100000L +#define VGT_DEBUG_REG20__clip_p_pre_hold_prim 0x00100000L +#define VGT_DEBUG_REG20__buffered_prim_type_event_MASK 0x03e00000L +#define VGT_DEBUG_REG20__out_trigger_MASK 0x04000000L +#define VGT_DEBUG_REG20__out_trigger 0x04000000L + +// VGT_DEBUG_REG21 +#define VGT_DEBUG_REG21__null_terminate_vtx_vector_MASK 0x00000001L +#define VGT_DEBUG_REG21__null_terminate_vtx_vector 0x00000001L +#define VGT_DEBUG_REG21__prim_end_of_vtx_vect_flags_MASK 0x0000000eL +#define VGT_DEBUG_REG21__alloc_counter_q_MASK 0x00000070L +#define VGT_DEBUG_REG21__curr_slot_in_vtx_vect_q_MASK 0x00000380L +#define VGT_DEBUG_REG21__int_vtx_counter_q_MASK 0x00003c00L +#define VGT_DEBUG_REG21__curr_dealloc_distance_q_MASK 0x0003c000L +#define VGT_DEBUG_REG21__new_packet_q_MASK 0x00040000L +#define VGT_DEBUG_REG21__new_packet_q 0x00040000L +#define VGT_DEBUG_REG21__new_allocate_q_MASK 0x00080000L +#define VGT_DEBUG_REG21__new_allocate_q 0x00080000L +#define VGT_DEBUG_REG21__num_new_unique_rel_indx_MASK 0x00300000L +#define VGT_DEBUG_REG21__inserted_null_prim_q_MASK 0x00400000L +#define VGT_DEBUG_REG21__inserted_null_prim_q 0x00400000L +#define VGT_DEBUG_REG21__insert_null_prim_MASK 0x00800000L +#define VGT_DEBUG_REG21__insert_null_prim 0x00800000L +#define VGT_DEBUG_REG21__buffered_prim_eop_mux_MASK 0x01000000L +#define VGT_DEBUG_REG21__buffered_prim_eop_mux 0x01000000L +#define VGT_DEBUG_REG21__prim_buffer_empty_mux_MASK 0x02000000L +#define VGT_DEBUG_REG21__prim_buffer_empty_mux 0x02000000L +#define VGT_DEBUG_REG21__buffered_thread_size_MASK 0x04000000L +#define VGT_DEBUG_REG21__buffered_thread_size 0x04000000L +#define VGT_DEBUG_REG21__out_trigger_MASK 0x80000000L +#define VGT_DEBUG_REG21__out_trigger 0x80000000L + +// VGT_CRC_SQ_DATA +#define VGT_CRC_SQ_DATA__CRC_MASK 0xffffffffL + +// VGT_CRC_SQ_CTRL +#define VGT_CRC_SQ_CTRL__CRC_MASK 0xffffffffL + +// VGT_PERFCOUNTER0_SELECT +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// VGT_PERFCOUNTER1_SELECT +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL + +// VGT_PERFCOUNTER2_SELECT +#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL + +// VGT_PERFCOUNTER3_SELECT +#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL + +// VGT_PERFCOUNTER0_LOW +#define VGT_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// VGT_PERFCOUNTER1_LOW +#define VGT_PERFCOUNTER1_LOW__PERF_COUNT_MASK 0xffffffffL + +// VGT_PERFCOUNTER2_LOW +#define VGT_PERFCOUNTER2_LOW__PERF_COUNT_MASK 0xffffffffL + +// VGT_PERFCOUNTER3_LOW +#define VGT_PERFCOUNTER3_LOW__PERF_COUNT_MASK 0xffffffffL + +// VGT_PERFCOUNTER0_HI +#define VGT_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// VGT_PERFCOUNTER1_HI +#define VGT_PERFCOUNTER1_HI__PERF_COUNT_MASK 0x0000ffffL + +// VGT_PERFCOUNTER2_HI +#define VGT_PERFCOUNTER2_HI__PERF_COUNT_MASK 0x0000ffffL + +// VGT_PERFCOUNTER3_HI +#define VGT_PERFCOUNTER3_HI__PERF_COUNT_MASK 0x0000ffffL + +// TC_CNTL_STATUS +#define TC_CNTL_STATUS__L2_INVALIDATE_MASK 0x00000001L +#define TC_CNTL_STATUS__L2_INVALIDATE 0x00000001L +#define TC_CNTL_STATUS__TC_L2_HIT_MISS_MASK 0x000c0000L +#define TC_CNTL_STATUS__TC_BUSY_MASK 0x80000000L +#define TC_CNTL_STATUS__TC_BUSY 0x80000000L + +// TCR_CHICKEN +#define TCR_CHICKEN__SPARE_MASK 0xffffffffL + +// TCF_CHICKEN +#define TCF_CHICKEN__SPARE_MASK 0xffffffffL + +// TCM_CHICKEN +#define TCM_CHICKEN__TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK 0x000000ffL +#define TCM_CHICKEN__ETC_COLOR_ENDIAN_MASK 0x00000100L +#define TCM_CHICKEN__ETC_COLOR_ENDIAN 0x00000100L +#define TCM_CHICKEN__SPARE_MASK 0xfffffe00L + +// TCR_PERFCOUNTER0_SELECT +#define TCR_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCR_PERFCOUNTER1_SELECT +#define TCR_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCR_PERFCOUNTER0_HI +#define TCR_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCR_PERFCOUNTER1_HI +#define TCR_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCR_PERFCOUNTER0_LOW +#define TCR_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCR_PERFCOUNTER1_LOW +#define TCR_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TP_TC_CLKGATE_CNTL +#define TP_TC_CLKGATE_CNTL__TP_BUSY_EXTEND_MASK 0x00000007L +#define TP_TC_CLKGATE_CNTL__TC_BUSY_EXTEND_MASK 0x00000038L + +// TPC_CNTL_STATUS +#define TPC_CNTL_STATUS__TPC_INPUT_BUSY_MASK 0x00000001L +#define TPC_CNTL_STATUS__TPC_INPUT_BUSY 0x00000001L +#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY_MASK 0x00000002L +#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY 0x00000002L +#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY_MASK 0x00000004L +#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY 0x00000004L +#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY_MASK 0x00000008L +#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY 0x00000008L +#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY_MASK 0x00000010L +#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY 0x00000010L +#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY_MASK 0x00000020L +#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY 0x00000020L +#define TPC_CNTL_STATUS__TPC_WALKER_BUSY_MASK 0x00000040L +#define TPC_CNTL_STATUS__TPC_WALKER_BUSY 0x00000040L +#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY_MASK 0x00000100L +#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY 0x00000100L +#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY_MASK 0x00000200L +#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY 0x00000200L +#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY_MASK 0x00000400L +#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY 0x00000400L +#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY_MASK 0x00001000L +#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY 0x00001000L +#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY_MASK 0x00002000L +#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY 0x00002000L +#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY_MASK 0x00004000L +#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY 0x00004000L +#define TPC_CNTL_STATUS__TPC_BLEND_BUSY_MASK 0x00008000L +#define TPC_CNTL_STATUS__TPC_BLEND_BUSY 0x00008000L +#define TPC_CNTL_STATUS__TF_TW_RTS_MASK 0x00010000L +#define TPC_CNTL_STATUS__TF_TW_RTS 0x00010000L +#define TPC_CNTL_STATUS__TF_TW_STATE_RTS_MASK 0x00020000L +#define TPC_CNTL_STATUS__TF_TW_STATE_RTS 0x00020000L +#define TPC_CNTL_STATUS__TF_TW_RTR_MASK 0x00080000L +#define TPC_CNTL_STATUS__TF_TW_RTR 0x00080000L +#define TPC_CNTL_STATUS__TW_TA_RTS_MASK 0x00100000L +#define TPC_CNTL_STATUS__TW_TA_RTS 0x00100000L +#define TPC_CNTL_STATUS__TW_TA_TT_RTS_MASK 0x00200000L +#define TPC_CNTL_STATUS__TW_TA_TT_RTS 0x00200000L +#define TPC_CNTL_STATUS__TW_TA_LAST_RTS_MASK 0x00400000L +#define TPC_CNTL_STATUS__TW_TA_LAST_RTS 0x00400000L +#define TPC_CNTL_STATUS__TW_TA_RTR_MASK 0x00800000L +#define TPC_CNTL_STATUS__TW_TA_RTR 0x00800000L +#define TPC_CNTL_STATUS__TA_TB_RTS_MASK 0x01000000L +#define TPC_CNTL_STATUS__TA_TB_RTS 0x01000000L +#define TPC_CNTL_STATUS__TA_TB_TT_RTS_MASK 0x02000000L +#define TPC_CNTL_STATUS__TA_TB_TT_RTS 0x02000000L +#define TPC_CNTL_STATUS__TA_TB_RTR_MASK 0x08000000L +#define TPC_CNTL_STATUS__TA_TB_RTR 0x08000000L +#define TPC_CNTL_STATUS__TA_TF_RTS_MASK 0x10000000L +#define TPC_CNTL_STATUS__TA_TF_RTS 0x10000000L +#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN_MASK 0x20000000L +#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN 0x20000000L +#define TPC_CNTL_STATUS__TP_SQ_DEC_MASK 0x40000000L +#define TPC_CNTL_STATUS__TP_SQ_DEC 0x40000000L +#define TPC_CNTL_STATUS__TPC_BUSY_MASK 0x80000000L +#define TPC_CNTL_STATUS__TPC_BUSY 0x80000000L + +// TPC_DEBUG0 +#define TPC_DEBUG0__LOD_CNTL_MASK 0x00000003L +#define TPC_DEBUG0__IC_CTR_MASK 0x0000000cL +#define TPC_DEBUG0__WALKER_CNTL_MASK 0x000000f0L +#define TPC_DEBUG0__ALIGNER_CNTL_MASK 0x00000700L +#define TPC_DEBUG0__PREV_TC_STATE_VALID_MASK 0x00001000L +#define TPC_DEBUG0__PREV_TC_STATE_VALID 0x00001000L +#define TPC_DEBUG0__WALKER_STATE_MASK 0x03ff0000L +#define TPC_DEBUG0__ALIGNER_STATE_MASK 0x0c000000L +#define TPC_DEBUG0__REG_CLK_EN_MASK 0x20000000L +#define TPC_DEBUG0__REG_CLK_EN 0x20000000L +#define TPC_DEBUG0__TPC_CLK_EN_MASK 0x40000000L +#define TPC_DEBUG0__TPC_CLK_EN 0x40000000L +#define TPC_DEBUG0__SQ_TP_WAKEUP_MASK 0x80000000L +#define TPC_DEBUG0__SQ_TP_WAKEUP 0x80000000L + +// TPC_DEBUG1 +#define TPC_DEBUG1__UNUSED_MASK 0x00000001L +#define TPC_DEBUG1__UNUSED 0x00000001L + +// TPC_CHICKEN +#define TPC_CHICKEN__BLEND_PRECISION_MASK 0x00000001L +#define TPC_CHICKEN__BLEND_PRECISION 0x00000001L +#define TPC_CHICKEN__SPARE_MASK 0xfffffffeL + +// TP0_CNTL_STATUS +#define TP0_CNTL_STATUS__TP_INPUT_BUSY_MASK 0x00000001L +#define TP0_CNTL_STATUS__TP_INPUT_BUSY 0x00000001L +#define TP0_CNTL_STATUS__TP_LOD_BUSY_MASK 0x00000002L +#define TP0_CNTL_STATUS__TP_LOD_BUSY 0x00000002L +#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY_MASK 0x00000004L +#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY 0x00000004L +#define TP0_CNTL_STATUS__TP_ADDR_BUSY_MASK 0x00000008L +#define TP0_CNTL_STATUS__TP_ADDR_BUSY 0x00000008L +#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY_MASK 0x00000010L +#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY 0x00000010L +#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY_MASK 0x00000020L +#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY 0x00000020L +#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY_MASK 0x00000040L +#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY 0x00000040L +#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY_MASK 0x00000080L +#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY 0x00000080L +#define TP0_CNTL_STATUS__TP_FETCH_BUSY_MASK 0x00000100L +#define TP0_CNTL_STATUS__TP_FETCH_BUSY 0x00000100L +#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY_MASK 0x00000200L +#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY 0x00000200L +#define TP0_CNTL_STATUS__TP_TT_BUSY_MASK 0x00000400L +#define TP0_CNTL_STATUS__TP_TT_BUSY 0x00000400L +#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY_MASK 0x00000800L +#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY 0x00000800L +#define TP0_CNTL_STATUS__TP_BLEND_BUSY_MASK 0x00001000L +#define TP0_CNTL_STATUS__TP_BLEND_BUSY 0x00001000L +#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY_MASK 0x00002000L +#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY 0x00002000L +#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY_MASK 0x00004000L +#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY 0x00004000L +#define TP0_CNTL_STATUS__IN_LC_RTS_MASK 0x00010000L +#define TP0_CNTL_STATUS__IN_LC_RTS 0x00010000L +#define TP0_CNTL_STATUS__LC_LA_RTS_MASK 0x00020000L +#define TP0_CNTL_STATUS__LC_LA_RTS 0x00020000L +#define TP0_CNTL_STATUS__LA_FL_RTS_MASK 0x00040000L +#define TP0_CNTL_STATUS__LA_FL_RTS 0x00040000L +#define TP0_CNTL_STATUS__FL_TA_RTS_MASK 0x00080000L +#define TP0_CNTL_STATUS__FL_TA_RTS 0x00080000L +#define TP0_CNTL_STATUS__TA_FA_RTS_MASK 0x00100000L +#define TP0_CNTL_STATUS__TA_FA_RTS 0x00100000L +#define TP0_CNTL_STATUS__TA_FA_TT_RTS_MASK 0x00200000L +#define TP0_CNTL_STATUS__TA_FA_TT_RTS 0x00200000L +#define TP0_CNTL_STATUS__FA_AL_RTS_MASK 0x00400000L +#define TP0_CNTL_STATUS__FA_AL_RTS 0x00400000L +#define TP0_CNTL_STATUS__FA_AL_TT_RTS_MASK 0x00800000L +#define TP0_CNTL_STATUS__FA_AL_TT_RTS 0x00800000L +#define TP0_CNTL_STATUS__AL_TF_RTS_MASK 0x01000000L +#define TP0_CNTL_STATUS__AL_TF_RTS 0x01000000L +#define TP0_CNTL_STATUS__AL_TF_TT_RTS_MASK 0x02000000L +#define TP0_CNTL_STATUS__AL_TF_TT_RTS 0x02000000L +#define TP0_CNTL_STATUS__TF_TB_RTS_MASK 0x04000000L +#define TP0_CNTL_STATUS__TF_TB_RTS 0x04000000L +#define TP0_CNTL_STATUS__TF_TB_TT_RTS_MASK 0x08000000L +#define TP0_CNTL_STATUS__TF_TB_TT_RTS 0x08000000L +#define TP0_CNTL_STATUS__TB_TT_RTS_MASK 0x10000000L +#define TP0_CNTL_STATUS__TB_TT_RTS 0x10000000L +#define TP0_CNTL_STATUS__TB_TT_TT_RESET_MASK 0x20000000L +#define TP0_CNTL_STATUS__TB_TT_TT_RESET 0x20000000L +#define TP0_CNTL_STATUS__TB_TO_RTS_MASK 0x40000000L +#define TP0_CNTL_STATUS__TB_TO_RTS 0x40000000L +#define TP0_CNTL_STATUS__TP_BUSY_MASK 0x80000000L +#define TP0_CNTL_STATUS__TP_BUSY 0x80000000L + +// TP0_DEBUG +#define TP0_DEBUG__Q_LOD_CNTL_MASK 0x00000003L +#define TP0_DEBUG__Q_SQ_TP_WAKEUP_MASK 0x00000008L +#define TP0_DEBUG__Q_SQ_TP_WAKEUP 0x00000008L +#define TP0_DEBUG__FL_TA_ADDRESSER_CNTL_MASK 0x001ffff0L +#define TP0_DEBUG__REG_CLK_EN_MASK 0x00200000L +#define TP0_DEBUG__REG_CLK_EN 0x00200000L +#define TP0_DEBUG__PERF_CLK_EN_MASK 0x00400000L +#define TP0_DEBUG__PERF_CLK_EN 0x00400000L +#define TP0_DEBUG__TP_CLK_EN_MASK 0x00800000L +#define TP0_DEBUG__TP_CLK_EN 0x00800000L +#define TP0_DEBUG__Q_WALKER_CNTL_MASK 0x0f000000L +#define TP0_DEBUG__Q_ALIGNER_CNTL_MASK 0x70000000L + +// TP0_CHICKEN +#define TP0_CHICKEN__TT_MODE_MASK 0x00000001L +#define TP0_CHICKEN__TT_MODE 0x00000001L +#define TP0_CHICKEN__VFETCH_ADDRESS_MODE_MASK 0x00000002L +#define TP0_CHICKEN__VFETCH_ADDRESS_MODE 0x00000002L +#define TP0_CHICKEN__SPARE_MASK 0xfffffffcL + +// TP0_PERFCOUNTER0_SELECT +#define TP0_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TP0_PERFCOUNTER0_HI +#define TP0_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TP0_PERFCOUNTER0_LOW +#define TP0_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TP0_PERFCOUNTER1_SELECT +#define TP0_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TP0_PERFCOUNTER1_HI +#define TP0_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TP0_PERFCOUNTER1_LOW +#define TP0_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCM_PERFCOUNTER0_SELECT +#define TCM_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCM_PERFCOUNTER1_SELECT +#define TCM_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCM_PERFCOUNTER0_HI +#define TCM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCM_PERFCOUNTER1_HI +#define TCM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCM_PERFCOUNTER0_LOW +#define TCM_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCM_PERFCOUNTER1_LOW +#define TCM_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER0_SELECT +#define TCF_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER1_SELECT +#define TCF_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER2_SELECT +#define TCF_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER3_SELECT +#define TCF_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER4_SELECT +#define TCF_PERFCOUNTER4_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER5_SELECT +#define TCF_PERFCOUNTER5_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER6_SELECT +#define TCF_PERFCOUNTER6_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER7_SELECT +#define TCF_PERFCOUNTER7_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER8_SELECT +#define TCF_PERFCOUNTER8_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER9_SELECT +#define TCF_PERFCOUNTER9_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER10_SELECT +#define TCF_PERFCOUNTER10_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER11_SELECT +#define TCF_PERFCOUNTER11_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER0_HI +#define TCF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER1_HI +#define TCF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER2_HI +#define TCF_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER3_HI +#define TCF_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER4_HI +#define TCF_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER5_HI +#define TCF_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER6_HI +#define TCF_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER7_HI +#define TCF_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER8_HI +#define TCF_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER9_HI +#define TCF_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER10_HI +#define TCF_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER11_HI +#define TCF_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER0_LOW +#define TCF_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER1_LOW +#define TCF_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER2_LOW +#define TCF_PERFCOUNTER2_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER3_LOW +#define TCF_PERFCOUNTER3_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER4_LOW +#define TCF_PERFCOUNTER4_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER5_LOW +#define TCF_PERFCOUNTER5_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER6_LOW +#define TCF_PERFCOUNTER6_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER7_LOW +#define TCF_PERFCOUNTER7_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER8_LOW +#define TCF_PERFCOUNTER8_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER9_LOW +#define TCF_PERFCOUNTER9_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER10_LOW +#define TCF_PERFCOUNTER10_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER11_LOW +#define TCF_PERFCOUNTER11_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_DEBUG +#define TCF_DEBUG__not_MH_TC_rtr_MASK 0x00000040L +#define TCF_DEBUG__not_MH_TC_rtr 0x00000040L +#define TCF_DEBUG__TC_MH_send_MASK 0x00000080L +#define TCF_DEBUG__TC_MH_send 0x00000080L +#define TCF_DEBUG__not_FG0_rtr_MASK 0x00000100L +#define TCF_DEBUG__not_FG0_rtr 0x00000100L +#define TCF_DEBUG__not_TCB_TCO_rtr_MASK 0x00001000L +#define TCF_DEBUG__not_TCB_TCO_rtr 0x00001000L +#define TCF_DEBUG__TCB_ff_stall_MASK 0x00002000L +#define TCF_DEBUG__TCB_ff_stall 0x00002000L +#define TCF_DEBUG__TCB_miss_stall_MASK 0x00004000L +#define TCF_DEBUG__TCB_miss_stall 0x00004000L +#define TCF_DEBUG__TCA_TCB_stall_MASK 0x00008000L +#define TCF_DEBUG__TCA_TCB_stall 0x00008000L +#define TCF_DEBUG__PF0_stall_MASK 0x00010000L +#define TCF_DEBUG__PF0_stall 0x00010000L +#define TCF_DEBUG__TP0_full_MASK 0x00100000L +#define TCF_DEBUG__TP0_full 0x00100000L +#define TCF_DEBUG__TPC_full_MASK 0x01000000L +#define TCF_DEBUG__TPC_full 0x01000000L +#define TCF_DEBUG__not_TPC_rtr_MASK 0x02000000L +#define TCF_DEBUG__not_TPC_rtr 0x02000000L +#define TCF_DEBUG__tca_state_rts_MASK 0x04000000L +#define TCF_DEBUG__tca_state_rts 0x04000000L +#define TCF_DEBUG__tca_rts_MASK 0x08000000L +#define TCF_DEBUG__tca_rts 0x08000000L + +// TCA_FIFO_DEBUG +#define TCA_FIFO_DEBUG__tp0_full_MASK 0x00000001L +#define TCA_FIFO_DEBUG__tp0_full 0x00000001L +#define TCA_FIFO_DEBUG__tpc_full_MASK 0x00000010L +#define TCA_FIFO_DEBUG__tpc_full 0x00000010L +#define TCA_FIFO_DEBUG__load_tpc_fifo_MASK 0x00000020L +#define TCA_FIFO_DEBUG__load_tpc_fifo 0x00000020L +#define TCA_FIFO_DEBUG__load_tp_fifos_MASK 0x00000040L +#define TCA_FIFO_DEBUG__load_tp_fifos 0x00000040L +#define TCA_FIFO_DEBUG__FW_full_MASK 0x00000080L +#define TCA_FIFO_DEBUG__FW_full 0x00000080L +#define TCA_FIFO_DEBUG__not_FW_rtr0_MASK 0x00000100L +#define TCA_FIFO_DEBUG__not_FW_rtr0 0x00000100L +#define TCA_FIFO_DEBUG__FW_rts0_MASK 0x00001000L +#define TCA_FIFO_DEBUG__FW_rts0 0x00001000L +#define TCA_FIFO_DEBUG__not_FW_tpc_rtr_MASK 0x00010000L +#define TCA_FIFO_DEBUG__not_FW_tpc_rtr 0x00010000L +#define TCA_FIFO_DEBUG__FW_tpc_rts_MASK 0x00020000L +#define TCA_FIFO_DEBUG__FW_tpc_rts 0x00020000L + +// TCA_PROBE_DEBUG +#define TCA_PROBE_DEBUG__ProbeFilter_stall_MASK 0x00000001L +#define TCA_PROBE_DEBUG__ProbeFilter_stall 0x00000001L + +// TCA_TPC_DEBUG +#define TCA_TPC_DEBUG__captue_state_rts_MASK 0x00001000L +#define TCA_TPC_DEBUG__captue_state_rts 0x00001000L +#define TCA_TPC_DEBUG__capture_tca_rts_MASK 0x00002000L +#define TCA_TPC_DEBUG__capture_tca_rts 0x00002000L + +// TCB_CORE_DEBUG +#define TCB_CORE_DEBUG__access512_MASK 0x00000001L +#define TCB_CORE_DEBUG__access512 0x00000001L +#define TCB_CORE_DEBUG__tiled_MASK 0x00000002L +#define TCB_CORE_DEBUG__tiled 0x00000002L +#define TCB_CORE_DEBUG__opcode_MASK 0x00000070L +#define TCB_CORE_DEBUG__format_MASK 0x00003f00L +#define TCB_CORE_DEBUG__sector_format_MASK 0x001f0000L +#define TCB_CORE_DEBUG__sector_format512_MASK 0x07000000L + +// TCB_TAG0_DEBUG +#define TCB_TAG0_DEBUG__mem_read_cycle_MASK 0x000003ffL +#define TCB_TAG0_DEBUG__tag_access_cycle_MASK 0x001ff000L +#define TCB_TAG0_DEBUG__miss_stall_MASK 0x00800000L +#define TCB_TAG0_DEBUG__miss_stall 0x00800000L +#define TCB_TAG0_DEBUG__num_feee_lines_MASK 0x1f000000L +#define TCB_TAG0_DEBUG__max_misses_MASK 0xe0000000L + +// TCB_TAG1_DEBUG +#define TCB_TAG1_DEBUG__mem_read_cycle_MASK 0x000003ffL +#define TCB_TAG1_DEBUG__tag_access_cycle_MASK 0x001ff000L +#define TCB_TAG1_DEBUG__miss_stall_MASK 0x00800000L +#define TCB_TAG1_DEBUG__miss_stall 0x00800000L +#define TCB_TAG1_DEBUG__num_feee_lines_MASK 0x1f000000L +#define TCB_TAG1_DEBUG__max_misses_MASK 0xe0000000L + +// TCB_TAG2_DEBUG +#define TCB_TAG2_DEBUG__mem_read_cycle_MASK 0x000003ffL +#define TCB_TAG2_DEBUG__tag_access_cycle_MASK 0x001ff000L +#define TCB_TAG2_DEBUG__miss_stall_MASK 0x00800000L +#define TCB_TAG2_DEBUG__miss_stall 0x00800000L +#define TCB_TAG2_DEBUG__num_feee_lines_MASK 0x1f000000L +#define TCB_TAG2_DEBUG__max_misses_MASK 0xe0000000L + +// TCB_TAG3_DEBUG +#define TCB_TAG3_DEBUG__mem_read_cycle_MASK 0x000003ffL +#define TCB_TAG3_DEBUG__tag_access_cycle_MASK 0x001ff000L +#define TCB_TAG3_DEBUG__miss_stall_MASK 0x00800000L +#define TCB_TAG3_DEBUG__miss_stall 0x00800000L +#define TCB_TAG3_DEBUG__num_feee_lines_MASK 0x1f000000L +#define TCB_TAG3_DEBUG__max_misses_MASK 0xe0000000L + +// TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done_MASK 0x00000001L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done 0x00000001L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left_MASK 0x00000004L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left 0x00000004L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q_MASK 0x00000010L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q 0x00000010L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go_MASK 0x00000020L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go 0x00000020L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left_MASK 0x00000040L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left 0x00000040L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_count_q_MASK 0x00000f80L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_q_MASK 0x0ffff000L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q_MASK 0x10000000L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q 0x10000000L + +// TCB_FETCH_GEN_WALKER_DEBUG +#define TCB_FETCH_GEN_WALKER_DEBUG__quad_sel_left_MASK 0x00000030L +#define TCB_FETCH_GEN_WALKER_DEBUG__set_sel_left_MASK 0x000000c0L +#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left_MASK 0x00000800L +#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left 0x00000800L +#define TCB_FETCH_GEN_WALKER_DEBUG__ff_fg_type512_MASK 0x00007000L +#define TCB_FETCH_GEN_WALKER_DEBUG__busy_MASK 0x00008000L +#define TCB_FETCH_GEN_WALKER_DEBUG__busy 0x00008000L +#define TCB_FETCH_GEN_WALKER_DEBUG__setquads_to_send_MASK 0x000f0000L + +// TCB_FETCH_GEN_PIPE0_DEBUG +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts_MASK 0x00000001L +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts 0x00000001L +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts_MASK 0x00000004L +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts 0x00000004L +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_format_MASK 0x0000fff0L +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_fmsopcode_MASK 0x001f0000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_request_type_MASK 0x00600000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__busy_MASK 0x00800000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__busy 0x00800000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy_MASK 0x01000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy 0x01000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy_MASK 0x02000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy 0x02000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__mc_sel_q_MASK 0x0c000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q_MASK 0x10000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q 0x10000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR_MASK 0x40000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR 0x40000000L + +// TCD_INPUT0_DEBUG +#define TCD_INPUT0_DEBUG__empty_MASK 0x00010000L +#define TCD_INPUT0_DEBUG__empty 0x00010000L +#define TCD_INPUT0_DEBUG__full_MASK 0x00020000L +#define TCD_INPUT0_DEBUG__full 0x00020000L +#define TCD_INPUT0_DEBUG__valid_q1_MASK 0x00100000L +#define TCD_INPUT0_DEBUG__valid_q1 0x00100000L +#define TCD_INPUT0_DEBUG__cnt_q1_MASK 0x00600000L +#define TCD_INPUT0_DEBUG__last_send_q1_MASK 0x00800000L +#define TCD_INPUT0_DEBUG__last_send_q1 0x00800000L +#define TCD_INPUT0_DEBUG__ip_send_MASK 0x01000000L +#define TCD_INPUT0_DEBUG__ip_send 0x01000000L +#define TCD_INPUT0_DEBUG__ipbuf_dxt_send_MASK 0x02000000L +#define TCD_INPUT0_DEBUG__ipbuf_dxt_send 0x02000000L +#define TCD_INPUT0_DEBUG__ipbuf_busy_MASK 0x04000000L +#define TCD_INPUT0_DEBUG__ipbuf_busy 0x04000000L + +// TCD_DEGAMMA_DEBUG +#define TCD_DEGAMMA_DEBUG__dgmm_ftfconv_dgmmen_MASK 0x00000003L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8_MASK 0x00000004L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8 0x00000004L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send_MASK 0x00000008L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send 0x00000008L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send_MASK 0x00000010L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send 0x00000010L +#define TCD_DEGAMMA_DEBUG__dgmm_stall_MASK 0x00000020L +#define TCD_DEGAMMA_DEBUG__dgmm_stall 0x00000020L +#define TCD_DEGAMMA_DEBUG__dgmm_pstate_MASK 0x00000040L +#define TCD_DEGAMMA_DEBUG__dgmm_pstate 0x00000040L + +// TCD_DXTMUX_SCTARB_DEBUG +#define TCD_DXTMUX_SCTARB_DEBUG__pstate_MASK 0x00000200L +#define TCD_DXTMUX_SCTARB_DEBUG__pstate 0x00000200L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr_MASK 0x00000400L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr 0x00000400L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr_MASK 0x00000800L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr 0x00000800L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send_MASK 0x00008000L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send 0x00008000L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts_MASK 0x00010000L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts 0x00010000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send_MASK 0x00100000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send 0x00100000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send_MASK 0x08000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send 0x08000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send_MASK 0x10000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send 0x10000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send_MASK 0x20000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send 0x20000000L + +// TCD_DXTC_ARB_DEBUG +#define TCD_DXTC_ARB_DEBUG__n0_stall_MASK 0x00000010L +#define TCD_DXTC_ARB_DEBUG__n0_stall 0x00000010L +#define TCD_DXTC_ARB_DEBUG__pstate_MASK 0x00000020L +#define TCD_DXTC_ARB_DEBUG__pstate 0x00000020L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send_MASK 0x00000040L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send 0x00000040L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cnt_MASK 0x00000180L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_sector_MASK 0x00000e00L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cacheline_MASK 0x0003f000L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_format_MASK 0x3ffc0000L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send_MASK 0x40000000L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send 0x40000000L +#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types_MASK 0x80000000L +#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types 0x80000000L + +// TCD_STALLS_DEBUG +#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr_MASK 0x00000400L +#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr 0x00000400L +#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr_MASK 0x00000800L +#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr 0x00000800L +#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr_MASK 0x00020000L +#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr 0x00020000L +#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr_MASK 0x00040000L +#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr 0x00040000L +#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr_MASK 0x00080000L +#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr 0x00080000L +#define TCD_STALLS_DEBUG__not_incoming_rtr_MASK 0x80000000L +#define TCD_STALLS_DEBUG__not_incoming_rtr 0x80000000L + +// TCO_STALLS_DEBUG +#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR_MASK 0x00000020L +#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR 0x00000020L +#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR_MASK 0x00000040L +#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR 0x00000040L +#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d_MASK 0x00000080L +#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d 0x00000080L + +// TCO_QUAD0_DEBUG0 +#define TCO_QUAD0_DEBUG0__rl_sg_sector_format_MASK 0x000000ffL +#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample_MASK 0x00000100L +#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample 0x00000100L +#define TCO_QUAD0_DEBUG0__rl_sg_rtr_MASK 0x00000200L +#define TCO_QUAD0_DEBUG0__rl_sg_rtr 0x00000200L +#define TCO_QUAD0_DEBUG0__rl_sg_rts_MASK 0x00000400L +#define TCO_QUAD0_DEBUG0__rl_sg_rts 0x00000400L +#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample_MASK 0x00000800L +#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample 0x00000800L +#define TCO_QUAD0_DEBUG0__sg_crd_rtr_MASK 0x00001000L +#define TCO_QUAD0_DEBUG0__sg_crd_rtr 0x00001000L +#define TCO_QUAD0_DEBUG0__sg_crd_rts_MASK 0x00002000L +#define TCO_QUAD0_DEBUG0__sg_crd_rts 0x00002000L +#define TCO_QUAD0_DEBUG0__stageN1_valid_q_MASK 0x00010000L +#define TCO_QUAD0_DEBUG0__stageN1_valid_q 0x00010000L +#define TCO_QUAD0_DEBUG0__read_cache_q_MASK 0x01000000L +#define TCO_QUAD0_DEBUG0__read_cache_q 0x01000000L +#define TCO_QUAD0_DEBUG0__cache_read_RTR_MASK 0x02000000L +#define TCO_QUAD0_DEBUG0__cache_read_RTR 0x02000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set3_MASK 0x04000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set3 0x04000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set2_MASK 0x08000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set2 0x08000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set1_MASK 0x10000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set1 0x10000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set0_MASK 0x20000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set0 0x20000000L +#define TCO_QUAD0_DEBUG0__busy_MASK 0x40000000L +#define TCO_QUAD0_DEBUG0__busy 0x40000000L + +// TCO_QUAD0_DEBUG1 +#define TCO_QUAD0_DEBUG1__fifo_busy_MASK 0x00000001L +#define TCO_QUAD0_DEBUG1__fifo_busy 0x00000001L +#define TCO_QUAD0_DEBUG1__empty_MASK 0x00000002L +#define TCO_QUAD0_DEBUG1__empty 0x00000002L +#define TCO_QUAD0_DEBUG1__full_MASK 0x00000004L +#define TCO_QUAD0_DEBUG1__full 0x00000004L +#define TCO_QUAD0_DEBUG1__write_enable_MASK 0x00000008L +#define TCO_QUAD0_DEBUG1__write_enable 0x00000008L +#define TCO_QUAD0_DEBUG1__fifo_write_ptr_MASK 0x000007f0L +#define TCO_QUAD0_DEBUG1__fifo_read_ptr_MASK 0x0003f800L +#define TCO_QUAD0_DEBUG1__cache_read_busy_MASK 0x00100000L +#define TCO_QUAD0_DEBUG1__cache_read_busy 0x00100000L +#define TCO_QUAD0_DEBUG1__latency_fifo_busy_MASK 0x00200000L +#define TCO_QUAD0_DEBUG1__latency_fifo_busy 0x00200000L +#define TCO_QUAD0_DEBUG1__input_quad_busy_MASK 0x00400000L +#define TCO_QUAD0_DEBUG1__input_quad_busy 0x00400000L +#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy_MASK 0x00800000L +#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy 0x00800000L +#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d_MASK 0x01000000L +#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d 0x01000000L +#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q_MASK 0x02000000L +#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q 0x02000000L +#define TCO_QUAD0_DEBUG1__rl_sg_rtr_MASK 0x04000000L +#define TCO_QUAD0_DEBUG1__rl_sg_rtr 0x04000000L +#define TCO_QUAD0_DEBUG1__rl_sg_rts_MASK 0x08000000L +#define TCO_QUAD0_DEBUG1__rl_sg_rts 0x08000000L +#define TCO_QUAD0_DEBUG1__sg_crd_rtr_MASK 0x10000000L +#define TCO_QUAD0_DEBUG1__sg_crd_rtr 0x10000000L +#define TCO_QUAD0_DEBUG1__sg_crd_rts_MASK 0x20000000L +#define TCO_QUAD0_DEBUG1__sg_crd_rts 0x20000000L +#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc_MASK 0x40000000L +#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc 0x40000000L + +// SQ_GPR_MANAGEMENT +#define SQ_GPR_MANAGEMENT__REG_DYNAMIC_MASK 0x00000001L +#define SQ_GPR_MANAGEMENT__REG_DYNAMIC 0x00000001L +#define SQ_GPR_MANAGEMENT__REG_SIZE_PIX_MASK 0x000007f0L +#define SQ_GPR_MANAGEMENT__REG_SIZE_VTX_MASK 0x0007f000L + +// SQ_FLOW_CONTROL +#define SQ_FLOW_CONTROL__INPUT_ARBITRATION_POLICY_MASK 0x00000003L +#define SQ_FLOW_CONTROL__ONE_THREAD_MASK 0x00000010L +#define SQ_FLOW_CONTROL__ONE_THREAD 0x00000010L +#define SQ_FLOW_CONTROL__ONE_ALU_MASK 0x00000100L +#define SQ_FLOW_CONTROL__ONE_ALU 0x00000100L +#define SQ_FLOW_CONTROL__CF_WR_BASE_MASK 0x0000f000L +#define SQ_FLOW_CONTROL__NO_PV_PS_MASK 0x00010000L +#define SQ_FLOW_CONTROL__NO_PV_PS 0x00010000L +#define SQ_FLOW_CONTROL__NO_LOOP_EXIT_MASK 0x00020000L +#define SQ_FLOW_CONTROL__NO_LOOP_EXIT 0x00020000L +#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE_MASK 0x00040000L +#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE 0x00040000L +#define SQ_FLOW_CONTROL__TEXTURE_ARBITRATION_POLICY_MASK 0x00180000L +#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY_MASK 0x00200000L +#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY 0x00200000L +#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY_MASK 0x00400000L +#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY 0x00400000L +#define SQ_FLOW_CONTROL__NO_ARB_EJECT_MASK 0x00800000L +#define SQ_FLOW_CONTROL__NO_ARB_EJECT 0x00800000L +#define SQ_FLOW_CONTROL__NO_CFS_EJECT_MASK 0x01000000L +#define SQ_FLOW_CONTROL__NO_CFS_EJECT 0x01000000L +#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY_MASK 0x02000000L +#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY 0x02000000L +#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION_MASK 0x04000000L +#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION 0x04000000L +#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC_MASK 0x08000000L +#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC 0x08000000L + +// SQ_INST_STORE_MANAGMENT +#define SQ_INST_STORE_MANAGMENT__INST_BASE_PIX_MASK 0x00000fffL +#define SQ_INST_STORE_MANAGMENT__INST_BASE_VTX_MASK 0x0fff0000L + +// SQ_RESOURCE_MANAGMENT +#define SQ_RESOURCE_MANAGMENT__VTX_THREAD_BUF_ENTRIES_MASK 0x000000ffL +#define SQ_RESOURCE_MANAGMENT__PIX_THREAD_BUF_ENTRIES_MASK 0x0000ff00L +#define SQ_RESOURCE_MANAGMENT__EXPORT_BUF_ENTRIES_MASK 0x01ff0000L + +// SQ_EO_RT +#define SQ_EO_RT__EO_CONSTANTS_RT_MASK 0x000000ffL +#define SQ_EO_RT__EO_TSTATE_RT_MASK 0x00ff0000L + +// SQ_DEBUG_MISC +#define SQ_DEBUG_MISC__DB_ALUCST_SIZE_MASK 0x000007ffL +#define SQ_DEBUG_MISC__DB_TSTATE_SIZE_MASK 0x000ff000L +#define SQ_DEBUG_MISC__DB_READ_CTX_MASK 0x00100000L +#define SQ_DEBUG_MISC__DB_READ_CTX 0x00100000L +#define SQ_DEBUG_MISC__RESERVED_MASK 0x00600000L +#define SQ_DEBUG_MISC__DB_READ_MEMORY_MASK 0x01800000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0_MASK 0x02000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0 0x02000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1_MASK 0x04000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1 0x04000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2_MASK 0x08000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2 0x08000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3_MASK 0x10000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3 0x10000000L + +// SQ_ACTIVITY_METER_CNTL +#define SQ_ACTIVITY_METER_CNTL__TIMEBASE_MASK 0x000000ffL +#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_LOW_MASK 0x0000ff00L +#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_HIGH_MASK 0x00ff0000L +#define SQ_ACTIVITY_METER_CNTL__SPARE_MASK 0xff000000L + +// SQ_ACTIVITY_METER_STATUS +#define SQ_ACTIVITY_METER_STATUS__PERCENT_BUSY_MASK 0x000000ffL + +// SQ_INPUT_ARB_PRIORITY +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_WEIGHT_MASK 0x00000007L +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN_MASK 0x00000008L +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN 0x00000008L +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_WEIGHT_MASK 0x00000070L +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN_MASK 0x00000080L +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN 0x00000080L +#define SQ_INPUT_ARB_PRIORITY__THRESHOLD_MASK 0x0003ff00L + +// SQ_THREAD_ARB_PRIORITY +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_WEIGHT_MASK 0x00000007L +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN_MASK 0x00000008L +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN 0x00000008L +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_WEIGHT_MASK 0x00000070L +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN_MASK 0x00000080L +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN 0x00000080L +#define SQ_THREAD_ARB_PRIORITY__THRESHOLD_MASK 0x0003ff00L +#define SQ_THREAD_ARB_PRIORITY__RESERVED_MASK 0x000c0000L +#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL_MASK 0x00100000L +#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL 0x00100000L +#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL_MASK 0x00200000L +#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL 0x00200000L +#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD_MASK 0x00400000L +#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD 0x00400000L + +// SQ_DEBUG_INPUT_FSM +#define SQ_DEBUG_INPUT_FSM__VC_VSR_LD_MASK 0x00000007L +#define SQ_DEBUG_INPUT_FSM__RESERVED_MASK 0x00000008L +#define SQ_DEBUG_INPUT_FSM__RESERVED 0x00000008L +#define SQ_DEBUG_INPUT_FSM__VC_GPR_LD_MASK 0x000000f0L +#define SQ_DEBUG_INPUT_FSM__PC_PISM_MASK 0x00000700L +#define SQ_DEBUG_INPUT_FSM__RESERVED1_MASK 0x00000800L +#define SQ_DEBUG_INPUT_FSM__RESERVED1 0x00000800L +#define SQ_DEBUG_INPUT_FSM__PC_AS_MASK 0x00007000L +#define SQ_DEBUG_INPUT_FSM__PC_INTERP_CNT_MASK 0x000f8000L +#define SQ_DEBUG_INPUT_FSM__PC_GPR_SIZE_MASK 0x0ff00000L + +// SQ_DEBUG_CONST_MGR_FSM +#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_EVENT_STATE_MASK 0x0000001fL +#define SQ_DEBUG_CONST_MGR_FSM__RESERVED1_MASK 0x000000e0L +#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_EVENT_STATE_MASK 0x00001f00L +#define SQ_DEBUG_CONST_MGR_FSM__RESERVED2_MASK 0x0000e000L +#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_CNTX_VALID_MASK 0x00030000L +#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_CNTX_VALID_MASK 0x000c0000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE_MASK 0x00100000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE 0x00100000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE_MASK 0x00200000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE 0x00200000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE_MASK 0x00400000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE 0x00400000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE_MASK 0x00800000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE 0x00800000L + +// SQ_DEBUG_TP_FSM +#define SQ_DEBUG_TP_FSM__EX_TP_MASK 0x00000007L +#define SQ_DEBUG_TP_FSM__RESERVED0_MASK 0x00000008L +#define SQ_DEBUG_TP_FSM__RESERVED0 0x00000008L +#define SQ_DEBUG_TP_FSM__CF_TP_MASK 0x000000f0L +#define SQ_DEBUG_TP_FSM__IF_TP_MASK 0x00000700L +#define SQ_DEBUG_TP_FSM__RESERVED1_MASK 0x00000800L +#define SQ_DEBUG_TP_FSM__RESERVED1 0x00000800L +#define SQ_DEBUG_TP_FSM__TIS_TP_MASK 0x00003000L +#define SQ_DEBUG_TP_FSM__RESERVED2_MASK 0x0000c000L +#define SQ_DEBUG_TP_FSM__GS_TP_MASK 0x00030000L +#define SQ_DEBUG_TP_FSM__RESERVED3_MASK 0x000c0000L +#define SQ_DEBUG_TP_FSM__FCR_TP_MASK 0x00300000L +#define SQ_DEBUG_TP_FSM__RESERVED4_MASK 0x00c00000L +#define SQ_DEBUG_TP_FSM__FCS_TP_MASK 0x03000000L +#define SQ_DEBUG_TP_FSM__RESERVED5_MASK 0x0c000000L +#define SQ_DEBUG_TP_FSM__ARB_TR_TP_MASK 0x70000000L + +// SQ_DEBUG_FSM_ALU_0 +#define SQ_DEBUG_FSM_ALU_0__EX_ALU_0_MASK 0x00000007L +#define SQ_DEBUG_FSM_ALU_0__RESERVED0_MASK 0x00000008L +#define SQ_DEBUG_FSM_ALU_0__RESERVED0 0x00000008L +#define SQ_DEBUG_FSM_ALU_0__CF_ALU_0_MASK 0x000000f0L +#define SQ_DEBUG_FSM_ALU_0__IF_ALU_0_MASK 0x00000700L +#define SQ_DEBUG_FSM_ALU_0__RESERVED1_MASK 0x00000800L +#define SQ_DEBUG_FSM_ALU_0__RESERVED1 0x00000800L +#define SQ_DEBUG_FSM_ALU_0__DU1_ALU_0_MASK 0x00007000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED2_MASK 0x00008000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED2 0x00008000L +#define SQ_DEBUG_FSM_ALU_0__DU0_ALU_0_MASK 0x00070000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED3_MASK 0x00080000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED3 0x00080000L +#define SQ_DEBUG_FSM_ALU_0__AIS_ALU_0_MASK 0x00700000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED4_MASK 0x00800000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED4 0x00800000L +#define SQ_DEBUG_FSM_ALU_0__ACS_ALU_0_MASK 0x07000000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED5_MASK 0x08000000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED5 0x08000000L +#define SQ_DEBUG_FSM_ALU_0__ARB_TR_ALU_MASK 0x70000000L + +// SQ_DEBUG_FSM_ALU_1 +#define SQ_DEBUG_FSM_ALU_1__EX_ALU_0_MASK 0x00000007L +#define SQ_DEBUG_FSM_ALU_1__RESERVED0_MASK 0x00000008L +#define SQ_DEBUG_FSM_ALU_1__RESERVED0 0x00000008L +#define SQ_DEBUG_FSM_ALU_1__CF_ALU_0_MASK 0x000000f0L +#define SQ_DEBUG_FSM_ALU_1__IF_ALU_0_MASK 0x00000700L +#define SQ_DEBUG_FSM_ALU_1__RESERVED1_MASK 0x00000800L +#define SQ_DEBUG_FSM_ALU_1__RESERVED1 0x00000800L +#define SQ_DEBUG_FSM_ALU_1__DU1_ALU_0_MASK 0x00007000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED2_MASK 0x00008000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED2 0x00008000L +#define SQ_DEBUG_FSM_ALU_1__DU0_ALU_0_MASK 0x00070000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED3_MASK 0x00080000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED3 0x00080000L +#define SQ_DEBUG_FSM_ALU_1__AIS_ALU_0_MASK 0x00700000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED4_MASK 0x00800000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED4 0x00800000L +#define SQ_DEBUG_FSM_ALU_1__ACS_ALU_0_MASK 0x07000000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED5_MASK 0x08000000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED5 0x08000000L +#define SQ_DEBUG_FSM_ALU_1__ARB_TR_ALU_MASK 0x70000000L + +// SQ_DEBUG_EXP_ALLOC +#define SQ_DEBUG_EXP_ALLOC__POS_BUF_AVAIL_MASK 0x0000000fL +#define SQ_DEBUG_EXP_ALLOC__COLOR_BUF_AVAIL_MASK 0x00000ff0L +#define SQ_DEBUG_EXP_ALLOC__EA_BUF_AVAIL_MASK 0x00007000L +#define SQ_DEBUG_EXP_ALLOC__RESERVED_MASK 0x00008000L +#define SQ_DEBUG_EXP_ALLOC__RESERVED 0x00008000L +#define SQ_DEBUG_EXP_ALLOC__ALLOC_TBL_BUF_AVAIL_MASK 0x003f0000L + +// SQ_DEBUG_PTR_BUFF +#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER_MASK 0x00000001L +#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER 0x00000001L +#define SQ_DEBUG_PTR_BUFF__DEALLOC_CNT_MASK 0x0000001eL +#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR_MASK 0x00000020L +#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR 0x00000020L +#define SQ_DEBUG_PTR_BUFF__EVENT_CONTEXT_ID_MASK 0x000001c0L +#define SQ_DEBUG_PTR_BUFF__SC_EVENT_ID_MASK 0x00003e00L +#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT_MASK 0x00004000L +#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT 0x00004000L +#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON_MASK 0x00008000L +#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON 0x00008000L +#define SQ_DEBUG_PTR_BUFF__EF_EMPTY_MASK 0x00010000L +#define SQ_DEBUG_PTR_BUFF__EF_EMPTY 0x00010000L +#define SQ_DEBUG_PTR_BUFF__VTX_SYNC_CNT_MASK 0x0ffe0000L + +// SQ_DEBUG_GPR_VTX +#define SQ_DEBUG_GPR_VTX__VTX_TAIL_PTR_MASK 0x0000007fL +#define SQ_DEBUG_GPR_VTX__RESERVED_MASK 0x00000080L +#define SQ_DEBUG_GPR_VTX__RESERVED 0x00000080L +#define SQ_DEBUG_GPR_VTX__VTX_HEAD_PTR_MASK 0x00007f00L +#define SQ_DEBUG_GPR_VTX__RESERVED1_MASK 0x00008000L +#define SQ_DEBUG_GPR_VTX__RESERVED1 0x00008000L +#define SQ_DEBUG_GPR_VTX__VTX_MAX_MASK 0x007f0000L +#define SQ_DEBUG_GPR_VTX__RESERVED2_MASK 0x00800000L +#define SQ_DEBUG_GPR_VTX__RESERVED2 0x00800000L +#define SQ_DEBUG_GPR_VTX__VTX_FREE_MASK 0x7f000000L + +// SQ_DEBUG_GPR_PIX +#define SQ_DEBUG_GPR_PIX__PIX_TAIL_PTR_MASK 0x0000007fL +#define SQ_DEBUG_GPR_PIX__RESERVED_MASK 0x00000080L +#define SQ_DEBUG_GPR_PIX__RESERVED 0x00000080L +#define SQ_DEBUG_GPR_PIX__PIX_HEAD_PTR_MASK 0x00007f00L +#define SQ_DEBUG_GPR_PIX__RESERVED1_MASK 0x00008000L +#define SQ_DEBUG_GPR_PIX__RESERVED1 0x00008000L +#define SQ_DEBUG_GPR_PIX__PIX_MAX_MASK 0x007f0000L +#define SQ_DEBUG_GPR_PIX__RESERVED2_MASK 0x00800000L +#define SQ_DEBUG_GPR_PIX__RESERVED2 0x00800000L +#define SQ_DEBUG_GPR_PIX__PIX_FREE_MASK 0x7f000000L + +// SQ_DEBUG_TB_STATUS_SEL +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATUS_REG_SEL_MASK 0x0000000fL +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_DW_SEL_MASK 0x00000070L +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_ADDR_MASK 0x00000780L +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN_MASK 0x00000800L +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN 0x00000800L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN_MASK 0x00001000L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN 0x00001000L +#define SQ_DEBUG_TB_STATUS_SEL__DEBUG_BUS_TRIGGER_SEL_MASK 0x0000c000L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATUS_REG_SEL_MASK 0x000f0000L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_DW_SEL_MASK 0x00700000L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_ADDR_MASK 0x1f800000L +#define SQ_DEBUG_TB_STATUS_SEL__VC_THREAD_BUF_DLY_MASK 0x60000000L +#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC_MASK 0x80000000L +#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC 0x80000000L + +// SQ_DEBUG_VTX_TB_0 +#define SQ_DEBUG_VTX_TB_0__VTX_HEAD_PTR_Q_MASK 0x0000000fL +#define SQ_DEBUG_VTX_TB_0__TAIL_PTR_Q_MASK 0x000000f0L +#define SQ_DEBUG_VTX_TB_0__FULL_CNT_Q_MASK 0x00000f00L +#define SQ_DEBUG_VTX_TB_0__NXT_POS_ALLOC_CNT_MASK 0x0000f000L +#define SQ_DEBUG_VTX_TB_0__NXT_PC_ALLOC_CNT_MASK 0x000f0000L +#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL_MASK 0x00100000L +#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL 0x00100000L +#define SQ_DEBUG_VTX_TB_0__BUSY_Q_MASK 0x00200000L +#define SQ_DEBUG_VTX_TB_0__BUSY_Q 0x00200000L + +// SQ_DEBUG_VTX_TB_1 +#define SQ_DEBUG_VTX_TB_1__VS_DONE_PTR_MASK 0x0000ffffL + +// SQ_DEBUG_VTX_TB_STATUS_REG +#define SQ_DEBUG_VTX_TB_STATUS_REG__VS_STATUS_REG_MASK 0xffffffffL + +// SQ_DEBUG_VTX_TB_STATE_MEM +#define SQ_DEBUG_VTX_TB_STATE_MEM__VS_STATE_MEM_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_0 +#define SQ_DEBUG_PIX_TB_0__PIX_HEAD_PTR_MASK 0x0000003fL +#define SQ_DEBUG_PIX_TB_0__TAIL_PTR_MASK 0x00000fc0L +#define SQ_DEBUG_PIX_TB_0__FULL_CNT_MASK 0x0007f000L +#define SQ_DEBUG_PIX_TB_0__NXT_PIX_ALLOC_CNT_MASK 0x01f80000L +#define SQ_DEBUG_PIX_TB_0__NXT_PIX_EXP_CNT_MASK 0x7e000000L +#define SQ_DEBUG_PIX_TB_0__BUSY_MASK 0x80000000L +#define SQ_DEBUG_PIX_TB_0__BUSY 0x80000000L + +// SQ_DEBUG_PIX_TB_STATUS_REG_0 +#define SQ_DEBUG_PIX_TB_STATUS_REG_0__PIX_TB_STATUS_REG_0_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_STATUS_REG_1 +#define SQ_DEBUG_PIX_TB_STATUS_REG_1__PIX_TB_STATUS_REG_1_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_STATUS_REG_2 +#define SQ_DEBUG_PIX_TB_STATUS_REG_2__PIX_TB_STATUS_REG_2_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_STATUS_REG_3 +#define SQ_DEBUG_PIX_TB_STATUS_REG_3__PIX_TB_STATUS_REG_3_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_STATE_MEM +#define SQ_DEBUG_PIX_TB_STATE_MEM__PIX_TB_STATE_MEM_MASK 0xffffffffL + +// SQ_PERFCOUNTER0_SELECT +#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// SQ_PERFCOUNTER1_SELECT +#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL + +// SQ_PERFCOUNTER2_SELECT +#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL + +// SQ_PERFCOUNTER3_SELECT +#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL + +// SQ_PERFCOUNTER0_LOW +#define SQ_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// SQ_PERFCOUNTER0_HI +#define SQ_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// SQ_PERFCOUNTER1_LOW +#define SQ_PERFCOUNTER1_LOW__PERF_COUNT_MASK 0xffffffffL + +// SQ_PERFCOUNTER1_HI +#define SQ_PERFCOUNTER1_HI__PERF_COUNT_MASK 0x0000ffffL + +// SQ_PERFCOUNTER2_LOW +#define SQ_PERFCOUNTER2_LOW__PERF_COUNT_MASK 0xffffffffL + +// SQ_PERFCOUNTER2_HI +#define SQ_PERFCOUNTER2_HI__PERF_COUNT_MASK 0x0000ffffL + +// SQ_PERFCOUNTER3_LOW +#define SQ_PERFCOUNTER3_LOW__PERF_COUNT_MASK 0xffffffffL + +// SQ_PERFCOUNTER3_HI +#define SQ_PERFCOUNTER3_HI__PERF_COUNT_MASK 0x0000ffffL + +// SX_PERFCOUNTER0_SELECT +#define SX_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// SX_PERFCOUNTER0_LOW +#define SX_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// SX_PERFCOUNTER0_HI +#define SX_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// SQ_INSTRUCTION_ALU_0 +#define SQ_INSTRUCTION_ALU_0__VECTOR_RESULT_MASK 0x0000003fL +#define SQ_INSTRUCTION_ALU_0__CST_0_ABS_MOD_MASK 0x00000040L +#define SQ_INSTRUCTION_ALU_0__CST_0_ABS_MOD 0x00000040L +#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP_MASK 0x00000080L +#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP 0x00000080L +#define SQ_INSTRUCTION_ALU_0__SCALAR_RESULT_MASK 0x00003f00L +#define SQ_INSTRUCTION_ALU_0__SST_0_ABS_MOD_MASK 0x00004000L +#define SQ_INSTRUCTION_ALU_0__SST_0_ABS_MOD 0x00004000L +#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA_MASK 0x00008000L +#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA 0x00008000L +#define SQ_INSTRUCTION_ALU_0__VECTOR_WRT_MSK_MASK 0x000f0000L +#define SQ_INSTRUCTION_ALU_0__SCALAR_WRT_MSK_MASK 0x00f00000L +#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP_MASK 0x01000000L +#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP 0x01000000L +#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP_MASK 0x02000000L +#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP 0x02000000L +#define SQ_INSTRUCTION_ALU_0__SCALAR_OPCODE_MASK 0xfc000000L + +// SQ_INSTRUCTION_ALU_1 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_R_MASK 0x00000003L +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_G_MASK 0x0000000cL +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_B_MASK 0x00000030L +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_A_MASK 0x000000c0L +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_R_MASK 0x00000300L +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_G_MASK 0x00000c00L +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_B_MASK 0x00003000L +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_A_MASK 0x0000c000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_R_MASK 0x00030000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_G_MASK 0x000c0000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_B_MASK 0x00300000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_A_MASK 0x00c00000L +#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD_MASK 0x01000000L +#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD 0x01000000L +#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD_MASK 0x02000000L +#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD 0x02000000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD_MASK 0x04000000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD 0x04000000L +#define SQ_INSTRUCTION_ALU_1__PRED_SELECT_MASK 0x18000000L +#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR_MASK 0x20000000L +#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR 0x20000000L +#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS_MASK 0x40000000L +#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS 0x40000000L +#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS_MASK 0x80000000L +#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS 0x80000000L + +// SQ_INSTRUCTION_ALU_2 +#define SQ_INSTRUCTION_ALU_2__SRC_C_REG_PTR_MASK 0x0000003fL +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C_MASK 0x00000040L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C 0x00000040L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C_MASK 0x00000080L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C 0x00000080L +#define SQ_INSTRUCTION_ALU_2__SRC_B_REG_PTR_MASK 0x00003f00L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B_MASK 0x00004000L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B 0x00004000L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B_MASK 0x00008000L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B 0x00008000L +#define SQ_INSTRUCTION_ALU_2__SRC_A_REG_PTR_MASK 0x003f0000L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A_MASK 0x00400000L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A 0x00400000L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A_MASK 0x00800000L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A 0x00800000L +#define SQ_INSTRUCTION_ALU_2__VECTOR_OPCODE_MASK 0x1f000000L +#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL_MASK 0x20000000L +#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL 0x20000000L +#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL_MASK 0x40000000L +#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL 0x40000000L +#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL_MASK 0x80000000L +#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL 0x80000000L + +// SQ_INSTRUCTION_CF_EXEC_0 +#define SQ_INSTRUCTION_CF_EXEC_0__ADDRESS_MASK 0x000001ffL +#define SQ_INSTRUCTION_CF_EXEC_0__RESERVED_MASK 0x00000e00L +#define SQ_INSTRUCTION_CF_EXEC_0__COUNT_MASK 0x00007000L +#define SQ_INSTRUCTION_CF_EXEC_0__YIELD_MASK 0x00008000L +#define SQ_INSTRUCTION_CF_EXEC_0__YIELD 0x00008000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0_MASK 0x00010000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0 0x00010000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0_MASK 0x00020000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0 0x00020000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1_MASK 0x00040000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1 0x00040000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1_MASK 0x00080000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1 0x00080000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2_MASK 0x00100000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2 0x00100000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2_MASK 0x00200000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2 0x00200000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3_MASK 0x00400000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3 0x00400000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3_MASK 0x00800000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3 0x00800000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4_MASK 0x01000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4 0x01000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4_MASK 0x02000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4 0x02000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5_MASK 0x04000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5 0x04000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5 0x08000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0_MASK 0x10000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0 0x10000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1_MASK 0x20000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1 0x20000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2_MASK 0x40000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2 0x40000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3_MASK 0x80000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3 0x80000000L + +// SQ_INSTRUCTION_CF_EXEC_1 +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4_MASK 0x00000001L +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4 0x00000001L +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5_MASK 0x00000002L +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5 0x00000002L +#define SQ_INSTRUCTION_CF_EXEC_1__BOOL_ADDR_MASK 0x000003fcL +#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION_MASK 0x00000400L +#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION 0x00000400L +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE 0x00000800L +#define SQ_INSTRUCTION_CF_EXEC_1__OPCODE_MASK 0x0000f000L +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MASK 0x01ff0000L +#define SQ_INSTRUCTION_CF_EXEC_1__RESERVED_MASK 0x0e000000L +#define SQ_INSTRUCTION_CF_EXEC_1__COUNT_MASK 0x70000000L +#define SQ_INSTRUCTION_CF_EXEC_1__YIELD_MASK 0x80000000L +#define SQ_INSTRUCTION_CF_EXEC_1__YIELD 0x80000000L + +// SQ_INSTRUCTION_CF_EXEC_2 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0_MASK 0x00000001L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0 0x00000001L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0_MASK 0x00000002L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0 0x00000002L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1_MASK 0x00000004L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1 0x00000004L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1_MASK 0x00000008L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1 0x00000008L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2_MASK 0x00000010L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2 0x00000010L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2_MASK 0x00000020L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2 0x00000020L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3_MASK 0x00000040L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3 0x00000040L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3_MASK 0x00000080L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3 0x00000080L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4_MASK 0x00000100L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4 0x00000100L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4_MASK 0x00000200L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4 0x00000200L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5_MASK 0x00000400L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5 0x00000400L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5 0x00000800L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0_MASK 0x00001000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0 0x00001000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1_MASK 0x00002000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1 0x00002000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2_MASK 0x00004000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2 0x00004000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3_MASK 0x00008000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3 0x00008000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4_MASK 0x00010000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4 0x00010000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5_MASK 0x00020000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5 0x00020000L +#define SQ_INSTRUCTION_CF_EXEC_2__BOOL_ADDR_MASK 0x03fc0000L +#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION_MASK 0x04000000L +#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION 0x04000000L +#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE 0x08000000L +#define SQ_INSTRUCTION_CF_EXEC_2__OPCODE_MASK 0xf0000000L + +// SQ_INSTRUCTION_CF_LOOP_0 +#define SQ_INSTRUCTION_CF_LOOP_0__ADDRESS_MASK 0x000003ffL +#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_0_MASK 0x0000fc00L +#define SQ_INSTRUCTION_CF_LOOP_0__LOOP_ID_MASK 0x001f0000L +#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_1_MASK 0xffe00000L + +// SQ_INSTRUCTION_CF_LOOP_1 +#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_0_MASK 0x000007ffL +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE 0x00000800L +#define SQ_INSTRUCTION_CF_LOOP_1__OPCODE_MASK 0x0000f000L +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MASK 0x03ff0000L +#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_1_MASK 0xfc000000L + +// SQ_INSTRUCTION_CF_LOOP_2 +#define SQ_INSTRUCTION_CF_LOOP_2__LOOP_ID_MASK 0x0000001fL +#define SQ_INSTRUCTION_CF_LOOP_2__RESERVED_MASK 0x07ffffe0L +#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE 0x08000000L +#define SQ_INSTRUCTION_CF_LOOP_2__OPCODE_MASK 0xf0000000L + +// SQ_INSTRUCTION_CF_JMP_CALL_0 +#define SQ_INSTRUCTION_CF_JMP_CALL_0__ADDRESS_MASK 0x000003ffL +#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_0_MASK 0x00001c00L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL_MASK 0x00002000L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL 0x00002000L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP_MASK 0x00004000L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP 0x00004000L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_1_MASK 0xffff8000L + +// SQ_INSTRUCTION_CF_JMP_CALL_1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0_MASK 0x00000001L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0 0x00000001L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION_MASK 0x00000002L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION 0x00000002L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__BOOL_ADDR_MASK 0x000003fcL +#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION_MASK 0x00000400L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION 0x00000400L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE 0x00000800L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__OPCODE_MASK 0x0000f000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MASK 0x03ff0000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_1_MASK 0x1c000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL_MASK 0x20000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL 0x20000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_2_MASK 0xc0000000L + +// SQ_INSTRUCTION_CF_JMP_CALL_2 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__RESERVED_MASK 0x0001ffffL +#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION_MASK 0x00020000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION 0x00020000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__BOOL_ADDR_MASK 0x03fc0000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION_MASK 0x04000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION 0x04000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE 0x08000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__OPCODE_MASK 0xf0000000L + +// SQ_INSTRUCTION_CF_ALLOC_0 +#define SQ_INSTRUCTION_CF_ALLOC_0__SIZE_MASK 0x0000000fL +#define SQ_INSTRUCTION_CF_ALLOC_0__RESERVED_MASK 0xfffffff0L + +// SQ_INSTRUCTION_CF_ALLOC_1 +#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_0_MASK 0x000000ffL +#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL_MASK 0x00000100L +#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL 0x00000100L +#define SQ_INSTRUCTION_CF_ALLOC_1__BUFFER_SELECT_MASK 0x00000600L +#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE 0x00000800L +#define SQ_INSTRUCTION_CF_ALLOC_1__OPCODE_MASK 0x0000f000L +#define SQ_INSTRUCTION_CF_ALLOC_1__SIZE_MASK 0x000f0000L +#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_1_MASK 0xfff00000L + +// SQ_INSTRUCTION_CF_ALLOC_2 +#define SQ_INSTRUCTION_CF_ALLOC_2__RESERVED_MASK 0x00ffffffL +#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL_MASK 0x01000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL 0x01000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__BUFFER_SELECT_MASK 0x06000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE 0x08000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__OPCODE_MASK 0xf0000000L + +// SQ_INSTRUCTION_TFETCH_0 +#define SQ_INSTRUCTION_TFETCH_0__OPCODE_MASK 0x0000001fL +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_MASK 0x000007e0L +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM_MASK 0x00000800L +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM 0x00000800L +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_MASK 0x0003f000L +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM_MASK 0x00040000L +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM 0x00040000L +#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY_MASK 0x00080000L +#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY 0x00080000L +#define SQ_INSTRUCTION_TFETCH_0__CONST_INDEX_MASK 0x01f00000L +#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM_MASK 0x02000000L +#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM 0x02000000L +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_X_MASK 0x0c000000L +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Y_MASK 0x30000000L +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Z_MASK 0xc0000000L + +// SQ_INSTRUCTION_TFETCH_1 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_X_MASK 0x00000007L +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Y_MASK 0x00000038L +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Z_MASK 0x000001c0L +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_W_MASK 0x00000e00L +#define SQ_INSTRUCTION_TFETCH_1__MAG_FILTER_MASK 0x00003000L +#define SQ_INSTRUCTION_TFETCH_1__MIN_FILTER_MASK 0x0000c000L +#define SQ_INSTRUCTION_TFETCH_1__MIP_FILTER_MASK 0x00030000L +#define SQ_INSTRUCTION_TFETCH_1__ANISO_FILTER_MASK 0x001c0000L +#define SQ_INSTRUCTION_TFETCH_1__ARBITRARY_FILTER_MASK 0x00e00000L +#define SQ_INSTRUCTION_TFETCH_1__VOL_MAG_FILTER_MASK 0x03000000L +#define SQ_INSTRUCTION_TFETCH_1__VOL_MIN_FILTER_MASK 0x0c000000L +#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD_MASK 0x10000000L +#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD 0x10000000L +#define SQ_INSTRUCTION_TFETCH_1__USE_REG_LOD_MASK 0x60000000L +#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT_MASK 0x80000000L +#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT 0x80000000L + +// SQ_INSTRUCTION_TFETCH_2 +#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS_MASK 0x00000001L +#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS 0x00000001L +#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION_MASK 0x00000002L +#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION 0x00000002L +#define SQ_INSTRUCTION_TFETCH_2__LOD_BIAS_MASK 0x000001fcL +#define SQ_INSTRUCTION_TFETCH_2__UNUSED_MASK 0x0000fe00L +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_X_MASK 0x001f0000L +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Y_MASK 0x03e00000L +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Z_MASK 0x7c000000L +#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION_MASK 0x80000000L +#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION 0x80000000L + +// SQ_INSTRUCTION_VFETCH_0 +#define SQ_INSTRUCTION_VFETCH_0__OPCODE_MASK 0x0000001fL +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_MASK 0x000007e0L +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM_MASK 0x00000800L +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM 0x00000800L +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_MASK 0x0003f000L +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM_MASK 0x00040000L +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM 0x00040000L +#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE_MASK 0x00080000L +#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE 0x00080000L +#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_MASK 0x01f00000L +#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_SEL_MASK 0x06000000L +#define SQ_INSTRUCTION_VFETCH_0__SRC_SEL_MASK 0xc0000000L + +// SQ_INSTRUCTION_VFETCH_1 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_X_MASK 0x00000007L +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Y_MASK 0x00000038L +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Z_MASK 0x000001c0L +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_W_MASK 0x00000e00L +#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL_MASK 0x00001000L +#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL 0x00001000L +#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL_MASK 0x00002000L +#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL 0x00002000L +#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL_MASK 0x00004000L +#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL 0x00004000L +#define SQ_INSTRUCTION_VFETCH_1__DATA_FORMAT_MASK 0x003f0000L +#define SQ_INSTRUCTION_VFETCH_1__EXP_ADJUST_ALL_MASK 0x3f800000L +#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT_MASK 0x80000000L +#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT 0x80000000L + +// SQ_INSTRUCTION_VFETCH_2 +#define SQ_INSTRUCTION_VFETCH_2__STRIDE_MASK 0x000000ffL +#define SQ_INSTRUCTION_VFETCH_2__OFFSET_MASK 0x00ff0000L +#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION_MASK 0x80000000L +#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION 0x80000000L + +// SQ_CONSTANT_0 +#define SQ_CONSTANT_0__RED_MASK 0xffffffffL + +// SQ_CONSTANT_1 +#define SQ_CONSTANT_1__GREEN_MASK 0xffffffffL + +// SQ_CONSTANT_2 +#define SQ_CONSTANT_2__BLUE_MASK 0xffffffffL + +// SQ_CONSTANT_3 +#define SQ_CONSTANT_3__ALPHA_MASK 0xffffffffL + +// SQ_FETCH_0 +#define SQ_FETCH_0__VALUE_MASK 0xffffffffL + +// SQ_FETCH_1 +#define SQ_FETCH_1__VALUE_MASK 0xffffffffL + +// SQ_FETCH_2 +#define SQ_FETCH_2__VALUE_MASK 0xffffffffL + +// SQ_FETCH_3 +#define SQ_FETCH_3__VALUE_MASK 0xffffffffL + +// SQ_FETCH_4 +#define SQ_FETCH_4__VALUE_MASK 0xffffffffL + +// SQ_FETCH_5 +#define SQ_FETCH_5__VALUE_MASK 0xffffffffL + +// SQ_CONSTANT_VFETCH_0 +#define SQ_CONSTANT_VFETCH_0__TYPE_MASK 0x00000001L +#define SQ_CONSTANT_VFETCH_0__TYPE 0x00000001L +#define SQ_CONSTANT_VFETCH_0__STATE_MASK 0x00000002L +#define SQ_CONSTANT_VFETCH_0__STATE 0x00000002L +#define SQ_CONSTANT_VFETCH_0__BASE_ADDRESS_MASK 0xfffffffcL + +// SQ_CONSTANT_VFETCH_1 +#define SQ_CONSTANT_VFETCH_1__ENDIAN_SWAP_MASK 0x00000003L +#define SQ_CONSTANT_VFETCH_1__LIMIT_ADDRESS_MASK 0xfffffffcL + +// SQ_CONSTANT_T2 +#define SQ_CONSTANT_T2__VALUE_MASK 0xffffffffL + +// SQ_CONSTANT_T3 +#define SQ_CONSTANT_T3__VALUE_MASK 0xffffffffL + +// SQ_CF_BOOLEANS +#define SQ_CF_BOOLEANS__CF_BOOLEANS_0_MASK 0x000000ffL +#define SQ_CF_BOOLEANS__CF_BOOLEANS_1_MASK 0x0000ff00L +#define SQ_CF_BOOLEANS__CF_BOOLEANS_2_MASK 0x00ff0000L +#define SQ_CF_BOOLEANS__CF_BOOLEANS_3_MASK 0xff000000L + +// SQ_CF_LOOP +#define SQ_CF_LOOP__CF_LOOP_COUNT_MASK 0x000000ffL +#define SQ_CF_LOOP__CF_LOOP_START_MASK 0x0000ff00L +#define SQ_CF_LOOP__CF_LOOP_STEP_MASK 0x00ff0000L + +// SQ_CONSTANT_RT_0 +#define SQ_CONSTANT_RT_0__RED_MASK 0xffffffffL + +// SQ_CONSTANT_RT_1 +#define SQ_CONSTANT_RT_1__GREEN_MASK 0xffffffffL + +// SQ_CONSTANT_RT_2 +#define SQ_CONSTANT_RT_2__BLUE_MASK 0xffffffffL + +// SQ_CONSTANT_RT_3 +#define SQ_CONSTANT_RT_3__ALPHA_MASK 0xffffffffL + +// SQ_FETCH_RT_0 +#define SQ_FETCH_RT_0__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_1 +#define SQ_FETCH_RT_1__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_2 +#define SQ_FETCH_RT_2__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_3 +#define SQ_FETCH_RT_3__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_4 +#define SQ_FETCH_RT_4__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_5 +#define SQ_FETCH_RT_5__VALUE_MASK 0xffffffffL + +// SQ_CF_RT_BOOLEANS +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_0_MASK 0x000000ffL +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_1_MASK 0x0000ff00L +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_2_MASK 0x00ff0000L +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_3_MASK 0xff000000L + +// SQ_CF_RT_LOOP +#define SQ_CF_RT_LOOP__CF_LOOP_COUNT_MASK 0x000000ffL +#define SQ_CF_RT_LOOP__CF_LOOP_START_MASK 0x0000ff00L +#define SQ_CF_RT_LOOP__CF_LOOP_STEP_MASK 0x00ff0000L + +// SQ_VS_PROGRAM +#define SQ_VS_PROGRAM__BASE_MASK 0x00000fffL +#define SQ_VS_PROGRAM__SIZE_MASK 0x00fff000L + +// SQ_PS_PROGRAM +#define SQ_PS_PROGRAM__BASE_MASK 0x00000fffL +#define SQ_PS_PROGRAM__SIZE_MASK 0x00fff000L + +// SQ_CF_PROGRAM_SIZE +#define SQ_CF_PROGRAM_SIZE__VS_CF_SIZE_MASK 0x000007ffL +#define SQ_CF_PROGRAM_SIZE__PS_CF_SIZE_MASK 0x007ff000L + +// SQ_INTERPOLATOR_CNTL +#define SQ_INTERPOLATOR_CNTL__PARAM_SHADE_MASK 0x0000ffffL +#define SQ_INTERPOLATOR_CNTL__SAMPLING_PATTERN_MASK 0xffff0000L + +// SQ_PROGRAM_CNTL +#define SQ_PROGRAM_CNTL__VS_NUM_REG_MASK 0x0000003fL +#define SQ_PROGRAM_CNTL__PS_NUM_REG_MASK 0x00003f00L +#define SQ_PROGRAM_CNTL__VS_RESOURCE_MASK 0x00010000L +#define SQ_PROGRAM_CNTL__VS_RESOURCE 0x00010000L +#define SQ_PROGRAM_CNTL__PS_RESOURCE_MASK 0x00020000L +#define SQ_PROGRAM_CNTL__PS_RESOURCE 0x00020000L +#define SQ_PROGRAM_CNTL__PARAM_GEN_MASK 0x00040000L +#define SQ_PROGRAM_CNTL__PARAM_GEN 0x00040000L +#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX_MASK 0x00080000L +#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX 0x00080000L +#define SQ_PROGRAM_CNTL__VS_EXPORT_COUNT_MASK 0x00f00000L +#define SQ_PROGRAM_CNTL__VS_EXPORT_MODE_MASK 0x07000000L +#define SQ_PROGRAM_CNTL__PS_EXPORT_MODE_MASK 0x78000000L +#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX_MASK 0x80000000L +#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX 0x80000000L + +// SQ_WRAPPING_0 +#define SQ_WRAPPING_0__PARAM_WRAP_0_MASK 0x0000000fL +#define SQ_WRAPPING_0__PARAM_WRAP_1_MASK 0x000000f0L +#define SQ_WRAPPING_0__PARAM_WRAP_2_MASK 0x00000f00L +#define SQ_WRAPPING_0__PARAM_WRAP_3_MASK 0x0000f000L +#define SQ_WRAPPING_0__PARAM_WRAP_4_MASK 0x000f0000L +#define SQ_WRAPPING_0__PARAM_WRAP_5_MASK 0x00f00000L +#define SQ_WRAPPING_0__PARAM_WRAP_6_MASK 0x0f000000L +#define SQ_WRAPPING_0__PARAM_WRAP_7_MASK 0xf0000000L + +// SQ_WRAPPING_1 +#define SQ_WRAPPING_1__PARAM_WRAP_8_MASK 0x0000000fL +#define SQ_WRAPPING_1__PARAM_WRAP_9_MASK 0x000000f0L +#define SQ_WRAPPING_1__PARAM_WRAP_10_MASK 0x00000f00L +#define SQ_WRAPPING_1__PARAM_WRAP_11_MASK 0x0000f000L +#define SQ_WRAPPING_1__PARAM_WRAP_12_MASK 0x000f0000L +#define SQ_WRAPPING_1__PARAM_WRAP_13_MASK 0x00f00000L +#define SQ_WRAPPING_1__PARAM_WRAP_14_MASK 0x0f000000L +#define SQ_WRAPPING_1__PARAM_WRAP_15_MASK 0xf0000000L + +// SQ_VS_CONST +#define SQ_VS_CONST__BASE_MASK 0x000001ffL +#define SQ_VS_CONST__SIZE_MASK 0x001ff000L + +// SQ_PS_CONST +#define SQ_PS_CONST__BASE_MASK 0x000001ffL +#define SQ_PS_CONST__SIZE_MASK 0x001ff000L + +// SQ_CONTEXT_MISC +#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE_MASK 0x00000001L +#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE 0x00000001L +#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY_MASK 0x00000002L +#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY 0x00000002L +#define SQ_CONTEXT_MISC__SC_SAMPLE_CNTL_MASK 0x0000000cL +#define SQ_CONTEXT_MISC__PARAM_GEN_POS_MASK 0x0000ff00L +#define SQ_CONTEXT_MISC__PERFCOUNTER_REF_MASK 0x00010000L +#define SQ_CONTEXT_MISC__PERFCOUNTER_REF 0x00010000L +#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE_MASK 0x00020000L +#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE 0x00020000L +#define SQ_CONTEXT_MISC__TX_CACHE_SEL_MASK 0x00040000L +#define SQ_CONTEXT_MISC__TX_CACHE_SEL 0x00040000L + +// SQ_CF_RD_BASE +#define SQ_CF_RD_BASE__RD_BASE_MASK 0x00000007L + +// SQ_DEBUG_MISC_0 +#define SQ_DEBUG_MISC_0__DB_PROB_ON_MASK 0x00000001L +#define SQ_DEBUG_MISC_0__DB_PROB_ON 0x00000001L +#define SQ_DEBUG_MISC_0__DB_PROB_BREAK_MASK 0x00000010L +#define SQ_DEBUG_MISC_0__DB_PROB_BREAK 0x00000010L +#define SQ_DEBUG_MISC_0__DB_PROB_ADDR_MASK 0x0007ff00L +#define SQ_DEBUG_MISC_0__DB_PROB_COUNT_MASK 0xff000000L + +// SQ_DEBUG_MISC_1 +#define SQ_DEBUG_MISC_1__DB_ON_PIX_MASK 0x00000001L +#define SQ_DEBUG_MISC_1__DB_ON_PIX 0x00000001L +#define SQ_DEBUG_MISC_1__DB_ON_VTX_MASK 0x00000002L +#define SQ_DEBUG_MISC_1__DB_ON_VTX 0x00000002L +#define SQ_DEBUG_MISC_1__DB_INST_COUNT_MASK 0x0000ff00L +#define SQ_DEBUG_MISC_1__DB_BREAK_ADDR_MASK 0x07ff0000L + +// MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG__SAME_PAGE_LIMIT_MASK 0x0000003fL +#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY_MASK 0x00000040L +#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY 0x00000040L +#define MH_ARBITER_CONFIG__L1_ARB_ENABLE_MASK 0x00000080L +#define MH_ARBITER_CONFIG__L1_ARB_ENABLE 0x00000080L +#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE_MASK 0x00000100L +#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE 0x00000100L +#define MH_ARBITER_CONFIG__L2_ARB_CONTROL_MASK 0x00000200L +#define MH_ARBITER_CONFIG__L2_ARB_CONTROL 0x00000200L +#define MH_ARBITER_CONFIG__PAGE_SIZE_MASK 0x00001c00L +#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE_MASK 0x00002000L +#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE 0x00002000L +#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE_MASK 0x00004000L +#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE 0x00004000L +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE_MASK 0x00008000L +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE 0x00008000L +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_MASK 0x003f0000L +#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE_MASK 0x00400000L +#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE 0x00400000L +#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE_MASK 0x00800000L +#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE 0x00800000L +#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE_MASK 0x01000000L +#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE 0x01000000L +#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE_MASK 0x02000000L +#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE 0x02000000L + +// MH_CLNT_AXI_ID_REUSE +#define MH_CLNT_AXI_ID_REUSE__CPw_ID_MASK 0x00000007L +#define MH_CLNT_AXI_ID_REUSE__RESERVED1_MASK 0x00000008L +#define MH_CLNT_AXI_ID_REUSE__RESERVED1 0x00000008L +#define MH_CLNT_AXI_ID_REUSE__RBw_ID_MASK 0x00000070L +#define MH_CLNT_AXI_ID_REUSE__RESERVED2_MASK 0x00000080L +#define MH_CLNT_AXI_ID_REUSE__RESERVED2 0x00000080L +#define MH_CLNT_AXI_ID_REUSE__MMUr_ID_MASK 0x00000700L + +// MH_INTERRUPT_MASK +#define MH_INTERRUPT_MASK__AXI_READ_ERROR_MASK 0x00000001L +#define MH_INTERRUPT_MASK__AXI_READ_ERROR 0x00000001L +#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR_MASK 0x00000002L +#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR 0x00000002L +#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT_MASK 0x00000004L +#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT 0x00000004L + +// MH_INTERRUPT_STATUS +#define MH_INTERRUPT_STATUS__AXI_READ_ERROR_MASK 0x00000001L +#define MH_INTERRUPT_STATUS__AXI_READ_ERROR 0x00000001L +#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR_MASK 0x00000002L +#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR 0x00000002L +#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT_MASK 0x00000004L +#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT 0x00000004L + +// MH_INTERRUPT_CLEAR +#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR_MASK 0x00000001L +#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR 0x00000001L +#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR_MASK 0x00000002L +#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR 0x00000002L +#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT_MASK 0x00000004L +#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT 0x00000004L + +// MH_AXI_ERROR +#define MH_AXI_ERROR__AXI_READ_ID_MASK 0x00000007L +#define MH_AXI_ERROR__AXI_READ_ERROR_MASK 0x00000008L +#define MH_AXI_ERROR__AXI_READ_ERROR 0x00000008L +#define MH_AXI_ERROR__AXI_WRITE_ID_MASK 0x00000070L +#define MH_AXI_ERROR__AXI_WRITE_ERROR_MASK 0x00000080L +#define MH_AXI_ERROR__AXI_WRITE_ERROR 0x00000080L + +// MH_PERFCOUNTER0_SELECT +#define MH_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// MH_PERFCOUNTER1_SELECT +#define MH_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL + +// MH_PERFCOUNTER0_CONFIG +#define MH_PERFCOUNTER0_CONFIG__N_VALUE_MASK 0x000000ffL + +// MH_PERFCOUNTER1_CONFIG +#define MH_PERFCOUNTER1_CONFIG__N_VALUE_MASK 0x000000ffL + +// MH_PERFCOUNTER0_LOW +#define MH_PERFCOUNTER0_LOW__PERF_COUNTER_LOW_MASK 0xffffffffL + +// MH_PERFCOUNTER1_LOW +#define MH_PERFCOUNTER1_LOW__PERF_COUNTER_LOW_MASK 0xffffffffL + +// MH_PERFCOUNTER0_HI +#define MH_PERFCOUNTER0_HI__PERF_COUNTER_HI_MASK 0x0000ffffL + +// MH_PERFCOUNTER1_HI +#define MH_PERFCOUNTER1_HI__PERF_COUNTER_HI_MASK 0x0000ffffL + +// MH_DEBUG_CTRL +#define MH_DEBUG_CTRL__INDEX_MASK 0x0000003fL + +// MH_DEBUG_DATA +#define MH_DEBUG_DATA__DATA_MASK 0xffffffffL + +// MH_DEBUG_REG00 +#define MH_DEBUG_REG00__MH_BUSY_MASK 0x00000001L +#define MH_DEBUG_REG00__MH_BUSY 0x00000001L +#define MH_DEBUG_REG00__TRANS_OUTSTANDING_MASK 0x00000002L +#define MH_DEBUG_REG00__TRANS_OUTSTANDING 0x00000002L +#define MH_DEBUG_REG00__CP_REQUEST_MASK 0x00000004L +#define MH_DEBUG_REG00__CP_REQUEST 0x00000004L +#define MH_DEBUG_REG00__VGT_REQUEST_MASK 0x00000008L +#define MH_DEBUG_REG00__VGT_REQUEST 0x00000008L +#define MH_DEBUG_REG00__TC_REQUEST_MASK 0x00000010L +#define MH_DEBUG_REG00__TC_REQUEST 0x00000010L +#define MH_DEBUG_REG00__TC_CAM_EMPTY_MASK 0x00000020L +#define MH_DEBUG_REG00__TC_CAM_EMPTY 0x00000020L +#define MH_DEBUG_REG00__TC_CAM_FULL_MASK 0x00000040L +#define MH_DEBUG_REG00__TC_CAM_FULL 0x00000040L +#define MH_DEBUG_REG00__TCD_EMPTY_MASK 0x00000080L +#define MH_DEBUG_REG00__TCD_EMPTY 0x00000080L +#define MH_DEBUG_REG00__TCD_FULL_MASK 0x00000100L +#define MH_DEBUG_REG00__TCD_FULL 0x00000100L +#define MH_DEBUG_REG00__RB_REQUEST_MASK 0x00000200L +#define MH_DEBUG_REG00__RB_REQUEST 0x00000200L +#define MH_DEBUG_REG00__MH_CLK_EN_STATE_MASK 0x00000400L +#define MH_DEBUG_REG00__MH_CLK_EN_STATE 0x00000400L +#define MH_DEBUG_REG00__ARQ_EMPTY_MASK 0x00000800L +#define MH_DEBUG_REG00__ARQ_EMPTY 0x00000800L +#define MH_DEBUG_REG00__ARQ_FULL_MASK 0x00001000L +#define MH_DEBUG_REG00__ARQ_FULL 0x00001000L +#define MH_DEBUG_REG00__WDB_EMPTY_MASK 0x00002000L +#define MH_DEBUG_REG00__WDB_EMPTY 0x00002000L +#define MH_DEBUG_REG00__WDB_FULL_MASK 0x00004000L +#define MH_DEBUG_REG00__WDB_FULL 0x00004000L +#define MH_DEBUG_REG00__AXI_AVALID_MASK 0x00008000L +#define MH_DEBUG_REG00__AXI_AVALID 0x00008000L +#define MH_DEBUG_REG00__AXI_AREADY_MASK 0x00010000L +#define MH_DEBUG_REG00__AXI_AREADY 0x00010000L +#define MH_DEBUG_REG00__AXI_ARVALID_MASK 0x00020000L +#define MH_DEBUG_REG00__AXI_ARVALID 0x00020000L +#define MH_DEBUG_REG00__AXI_ARREADY_MASK 0x00040000L +#define MH_DEBUG_REG00__AXI_ARREADY 0x00040000L +#define MH_DEBUG_REG00__AXI_WVALID_MASK 0x00080000L +#define MH_DEBUG_REG00__AXI_WVALID 0x00080000L +#define MH_DEBUG_REG00__AXI_WREADY_MASK 0x00100000L +#define MH_DEBUG_REG00__AXI_WREADY 0x00100000L +#define MH_DEBUG_REG00__AXI_RVALID_MASK 0x00200000L +#define MH_DEBUG_REG00__AXI_RVALID 0x00200000L +#define MH_DEBUG_REG00__AXI_RREADY_MASK 0x00400000L +#define MH_DEBUG_REG00__AXI_RREADY 0x00400000L +#define MH_DEBUG_REG00__AXI_BVALID_MASK 0x00800000L +#define MH_DEBUG_REG00__AXI_BVALID 0x00800000L +#define MH_DEBUG_REG00__AXI_BREADY_MASK 0x01000000L +#define MH_DEBUG_REG00__AXI_BREADY 0x01000000L +#define MH_DEBUG_REG00__AXI_HALT_REQ_MASK 0x02000000L +#define MH_DEBUG_REG00__AXI_HALT_REQ 0x02000000L +#define MH_DEBUG_REG00__AXI_HALT_ACK_MASK 0x04000000L +#define MH_DEBUG_REG00__AXI_HALT_ACK 0x04000000L + +// MH_DEBUG_REG01 +#define MH_DEBUG_REG01__CP_SEND_q_MASK 0x00000001L +#define MH_DEBUG_REG01__CP_SEND_q 0x00000001L +#define MH_DEBUG_REG01__CP_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG01__CP_RTR_q 0x00000002L +#define MH_DEBUG_REG01__CP_WRITE_q_MASK 0x00000004L +#define MH_DEBUG_REG01__CP_WRITE_q 0x00000004L +#define MH_DEBUG_REG01__CP_TAG_q_MASK 0x00000038L +#define MH_DEBUG_REG01__CP_BE_q_MASK 0x00003fc0L +#define MH_DEBUG_REG01__VGT_SEND_q_MASK 0x00004000L +#define MH_DEBUG_REG01__VGT_SEND_q 0x00004000L +#define MH_DEBUG_REG01__VGT_RTR_q_MASK 0x00008000L +#define MH_DEBUG_REG01__VGT_RTR_q 0x00008000L +#define MH_DEBUG_REG01__VGT_TAG_q_MASK 0x00010000L +#define MH_DEBUG_REG01__VGT_TAG_q 0x00010000L +#define MH_DEBUG_REG01__TC_SEND_q_MASK 0x00020000L +#define MH_DEBUG_REG01__TC_SEND_q 0x00020000L +#define MH_DEBUG_REG01__TC_RTR_q_MASK 0x00040000L +#define MH_DEBUG_REG01__TC_RTR_q 0x00040000L +#define MH_DEBUG_REG01__TC_ROQ_SEND_q_MASK 0x00080000L +#define MH_DEBUG_REG01__TC_ROQ_SEND_q 0x00080000L +#define MH_DEBUG_REG01__TC_ROQ_RTR_q_MASK 0x00100000L +#define MH_DEBUG_REG01__TC_ROQ_RTR_q 0x00100000L +#define MH_DEBUG_REG01__TC_MH_written_MASK 0x00200000L +#define MH_DEBUG_REG01__TC_MH_written 0x00200000L +#define MH_DEBUG_REG01__RB_SEND_q_MASK 0x00400000L +#define MH_DEBUG_REG01__RB_SEND_q 0x00400000L +#define MH_DEBUG_REG01__RB_RTR_q_MASK 0x00800000L +#define MH_DEBUG_REG01__RB_RTR_q 0x00800000L +#define MH_DEBUG_REG01__RB_BE_q_MASK 0xff000000L + +// MH_DEBUG_REG02 +#define MH_DEBUG_REG02__MH_CP_grb_send_MASK 0x00000001L +#define MH_DEBUG_REG02__MH_CP_grb_send 0x00000001L +#define MH_DEBUG_REG02__MH_VGT_grb_send_MASK 0x00000002L +#define MH_DEBUG_REG02__MH_VGT_grb_send 0x00000002L +#define MH_DEBUG_REG02__MH_TC_mcsend_MASK 0x00000004L +#define MH_DEBUG_REG02__MH_TC_mcsend 0x00000004L +#define MH_DEBUG_REG02__MH_CLNT_rlast_MASK 0x00000008L +#define MH_DEBUG_REG02__MH_CLNT_rlast 0x00000008L +#define MH_DEBUG_REG02__MH_CLNT_tag_MASK 0x00000070L +#define MH_DEBUG_REG02__RDC_RID_MASK 0x00000380L +#define MH_DEBUG_REG02__RDC_RRESP_MASK 0x00000c00L +#define MH_DEBUG_REG02__MH_CP_writeclean_MASK 0x00001000L +#define MH_DEBUG_REG02__MH_CP_writeclean 0x00001000L +#define MH_DEBUG_REG02__MH_RB_writeclean_MASK 0x00002000L +#define MH_DEBUG_REG02__MH_RB_writeclean 0x00002000L +#define MH_DEBUG_REG02__BRC_BID_MASK 0x0001c000L +#define MH_DEBUG_REG02__BRC_BRESP_MASK 0x00060000L + +// MH_DEBUG_REG03 +#define MH_DEBUG_REG03__MH_CLNT_data_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG04 +#define MH_DEBUG_REG04__MH_CLNT_data_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG05 +#define MH_DEBUG_REG05__CP_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG05__CP_MH_send 0x00000001L +#define MH_DEBUG_REG05__CP_MH_write_MASK 0x00000002L +#define MH_DEBUG_REG05__CP_MH_write 0x00000002L +#define MH_DEBUG_REG05__CP_MH_tag_MASK 0x0000001cL +#define MH_DEBUG_REG05__CP_MH_ad_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG06 +#define MH_DEBUG_REG06__CP_MH_data_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG07 +#define MH_DEBUG_REG07__CP_MH_data_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG08 +#define MH_DEBUG_REG08__ALWAYS_ZERO_MASK 0x00000007L +#define MH_DEBUG_REG08__VGT_MH_send_MASK 0x00000008L +#define MH_DEBUG_REG08__VGT_MH_send 0x00000008L +#define MH_DEBUG_REG08__VGT_MH_tagbe_MASK 0x00000010L +#define MH_DEBUG_REG08__VGT_MH_tagbe 0x00000010L +#define MH_DEBUG_REG08__VGT_MH_ad_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG09 +#define MH_DEBUG_REG09__ALWAYS_ZERO_MASK 0x00000003L +#define MH_DEBUG_REG09__TC_MH_send_MASK 0x00000004L +#define MH_DEBUG_REG09__TC_MH_send 0x00000004L +#define MH_DEBUG_REG09__TC_MH_mask_MASK 0x00000018L +#define MH_DEBUG_REG09__TC_MH_addr_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG10 +#define MH_DEBUG_REG10__TC_MH_info_MASK 0x01ffffffL +#define MH_DEBUG_REG10__TC_MH_send_MASK 0x02000000L +#define MH_DEBUG_REG10__TC_MH_send 0x02000000L + +// MH_DEBUG_REG11 +#define MH_DEBUG_REG11__MH_TC_mcinfo_MASK 0x01ffffffL +#define MH_DEBUG_REG11__MH_TC_mcinfo_send_MASK 0x02000000L +#define MH_DEBUG_REG11__MH_TC_mcinfo_send 0x02000000L +#define MH_DEBUG_REG11__TC_MH_written_MASK 0x04000000L +#define MH_DEBUG_REG11__TC_MH_written 0x04000000L + +// MH_DEBUG_REG12 +#define MH_DEBUG_REG12__ALWAYS_ZERO_MASK 0x00000003L +#define MH_DEBUG_REG12__TC_ROQ_SEND_MASK 0x00000004L +#define MH_DEBUG_REG12__TC_ROQ_SEND 0x00000004L +#define MH_DEBUG_REG12__TC_ROQ_MASK_MASK 0x00000018L +#define MH_DEBUG_REG12__TC_ROQ_ADDR_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG13 +#define MH_DEBUG_REG13__TC_ROQ_INFO_MASK 0x01ffffffL +#define MH_DEBUG_REG13__TC_ROQ_SEND_MASK 0x02000000L +#define MH_DEBUG_REG13__TC_ROQ_SEND 0x02000000L + +// MH_DEBUG_REG14 +#define MH_DEBUG_REG14__ALWAYS_ZERO_MASK 0x0000000fL +#define MH_DEBUG_REG14__RB_MH_send_MASK 0x00000010L +#define MH_DEBUG_REG14__RB_MH_send 0x00000010L +#define MH_DEBUG_REG14__RB_MH_addr_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG15 +#define MH_DEBUG_REG15__RB_MH_data_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG16 +#define MH_DEBUG_REG16__RB_MH_data_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG17 +#define MH_DEBUG_REG17__AVALID_q_MASK 0x00000001L +#define MH_DEBUG_REG17__AVALID_q 0x00000001L +#define MH_DEBUG_REG17__AREADY_q_MASK 0x00000002L +#define MH_DEBUG_REG17__AREADY_q 0x00000002L +#define MH_DEBUG_REG17__AID_q_MASK 0x0000001cL +#define MH_DEBUG_REG17__ALEN_q_2_0_MASK 0x000000e0L +#define MH_DEBUG_REG17__ARVALID_q_MASK 0x00000100L +#define MH_DEBUG_REG17__ARVALID_q 0x00000100L +#define MH_DEBUG_REG17__ARREADY_q_MASK 0x00000200L +#define MH_DEBUG_REG17__ARREADY_q 0x00000200L +#define MH_DEBUG_REG17__ARID_q_MASK 0x00001c00L +#define MH_DEBUG_REG17__ARLEN_q_1_0_MASK 0x00006000L +#define MH_DEBUG_REG17__RVALID_q_MASK 0x00008000L +#define MH_DEBUG_REG17__RVALID_q 0x00008000L +#define MH_DEBUG_REG17__RREADY_q_MASK 0x00010000L +#define MH_DEBUG_REG17__RREADY_q 0x00010000L +#define MH_DEBUG_REG17__RLAST_q_MASK 0x00020000L +#define MH_DEBUG_REG17__RLAST_q 0x00020000L +#define MH_DEBUG_REG17__RID_q_MASK 0x001c0000L +#define MH_DEBUG_REG17__WVALID_q_MASK 0x00200000L +#define MH_DEBUG_REG17__WVALID_q 0x00200000L +#define MH_DEBUG_REG17__WREADY_q_MASK 0x00400000L +#define MH_DEBUG_REG17__WREADY_q 0x00400000L +#define MH_DEBUG_REG17__WLAST_q_MASK 0x00800000L +#define MH_DEBUG_REG17__WLAST_q 0x00800000L +#define MH_DEBUG_REG17__WID_q_MASK 0x07000000L +#define MH_DEBUG_REG17__BVALID_q_MASK 0x08000000L +#define MH_DEBUG_REG17__BVALID_q 0x08000000L +#define MH_DEBUG_REG17__BREADY_q_MASK 0x10000000L +#define MH_DEBUG_REG17__BREADY_q 0x10000000L +#define MH_DEBUG_REG17__BID_q_MASK 0xe0000000L + +// MH_DEBUG_REG18 +#define MH_DEBUG_REG18__AVALID_q_MASK 0x00000001L +#define MH_DEBUG_REG18__AVALID_q 0x00000001L +#define MH_DEBUG_REG18__AREADY_q_MASK 0x00000002L +#define MH_DEBUG_REG18__AREADY_q 0x00000002L +#define MH_DEBUG_REG18__AID_q_MASK 0x0000001cL +#define MH_DEBUG_REG18__ALEN_q_1_0_MASK 0x00000060L +#define MH_DEBUG_REG18__ARVALID_q_MASK 0x00000080L +#define MH_DEBUG_REG18__ARVALID_q 0x00000080L +#define MH_DEBUG_REG18__ARREADY_q_MASK 0x00000100L +#define MH_DEBUG_REG18__ARREADY_q 0x00000100L +#define MH_DEBUG_REG18__ARID_q_MASK 0x00000e00L +#define MH_DEBUG_REG18__ARLEN_q_1_1_MASK 0x00001000L +#define MH_DEBUG_REG18__ARLEN_q_1_1 0x00001000L +#define MH_DEBUG_REG18__WVALID_q_MASK 0x00002000L +#define MH_DEBUG_REG18__WVALID_q 0x00002000L +#define MH_DEBUG_REG18__WREADY_q_MASK 0x00004000L +#define MH_DEBUG_REG18__WREADY_q 0x00004000L +#define MH_DEBUG_REG18__WLAST_q_MASK 0x00008000L +#define MH_DEBUG_REG18__WLAST_q 0x00008000L +#define MH_DEBUG_REG18__WID_q_MASK 0x00070000L +#define MH_DEBUG_REG18__WSTRB_q_MASK 0x07f80000L +#define MH_DEBUG_REG18__BVALID_q_MASK 0x08000000L +#define MH_DEBUG_REG18__BVALID_q 0x08000000L +#define MH_DEBUG_REG18__BREADY_q_MASK 0x10000000L +#define MH_DEBUG_REG18__BREADY_q 0x10000000L +#define MH_DEBUG_REG18__BID_q_MASK 0xe0000000L + +// MH_DEBUG_REG19 +#define MH_DEBUG_REG19__ARC_CTRL_RE_q_MASK 0x00000001L +#define MH_DEBUG_REG19__ARC_CTRL_RE_q 0x00000001L +#define MH_DEBUG_REG19__CTRL_ARC_ID_MASK 0x0000000eL +#define MH_DEBUG_REG19__CTRL_ARC_PAD_MASK 0xfffffff0L + +// MH_DEBUG_REG20 +#define MH_DEBUG_REG20__ALWAYS_ZERO_MASK 0x00000003L +#define MH_DEBUG_REG20__REG_A_MASK 0x0000fffcL +#define MH_DEBUG_REG20__REG_RE_MASK 0x00010000L +#define MH_DEBUG_REG20__REG_RE 0x00010000L +#define MH_DEBUG_REG20__REG_WE_MASK 0x00020000L +#define MH_DEBUG_REG20__REG_WE 0x00020000L +#define MH_DEBUG_REG20__BLOCK_RS_MASK 0x00040000L +#define MH_DEBUG_REG20__BLOCK_RS 0x00040000L + +// MH_DEBUG_REG21 +#define MH_DEBUG_REG21__REG_WD_MASK 0xffffffffL + +// MH_DEBUG_REG22 +#define MH_DEBUG_REG22__CIB_MH_axi_halt_req_MASK 0x00000001L +#define MH_DEBUG_REG22__CIB_MH_axi_halt_req 0x00000001L +#define MH_DEBUG_REG22__MH_CIB_axi_halt_ack_MASK 0x00000002L +#define MH_DEBUG_REG22__MH_CIB_axi_halt_ack 0x00000002L +#define MH_DEBUG_REG22__MH_RBBM_busy_MASK 0x00000004L +#define MH_DEBUG_REG22__MH_RBBM_busy 0x00000004L +#define MH_DEBUG_REG22__MH_CIB_mh_clk_en_int_MASK 0x00000008L +#define MH_DEBUG_REG22__MH_CIB_mh_clk_en_int 0x00000008L +#define MH_DEBUG_REG22__MH_CIB_mmu_clk_en_int_MASK 0x00000010L +#define MH_DEBUG_REG22__MH_CIB_mmu_clk_en_int 0x00000010L +#define MH_DEBUG_REG22__MH_CIB_tcroq_clk_en_int_MASK 0x00000020L +#define MH_DEBUG_REG22__MH_CIB_tcroq_clk_en_int 0x00000020L +#define MH_DEBUG_REG22__GAT_CLK_ENA_MASK 0x00000040L +#define MH_DEBUG_REG22__GAT_CLK_ENA 0x00000040L +#define MH_DEBUG_REG22__AXI_RDY_ENA_MASK 0x00000080L +#define MH_DEBUG_REG22__AXI_RDY_ENA 0x00000080L +#define MH_DEBUG_REG22__RBBM_MH_clk_en_override_MASK 0x00000100L +#define MH_DEBUG_REG22__RBBM_MH_clk_en_override 0x00000100L +#define MH_DEBUG_REG22__CNT_q_MASK 0x00007e00L +#define MH_DEBUG_REG22__TCD_EMPTY_q_MASK 0x00008000L +#define MH_DEBUG_REG22__TCD_EMPTY_q 0x00008000L +#define MH_DEBUG_REG22__TC_ROQ_EMPTY_MASK 0x00010000L +#define MH_DEBUG_REG22__TC_ROQ_EMPTY 0x00010000L +#define MH_DEBUG_REG22__MH_BUSY_d_MASK 0x00020000L +#define MH_DEBUG_REG22__MH_BUSY_d 0x00020000L +#define MH_DEBUG_REG22__ANY_CLNT_BUSY_MASK 0x00040000L +#define MH_DEBUG_REG22__ANY_CLNT_BUSY 0x00040000L +#define MH_DEBUG_REG22__MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00080000L +#define MH_DEBUG_REG22__MH_MMU_INVALIDATE_INVALIDATE_ALL 0x00080000L +#define MH_DEBUG_REG22__CP_SEND_q_MASK 0x00100000L +#define MH_DEBUG_REG22__CP_SEND_q 0x00100000L +#define MH_DEBUG_REG22__CP_RTR_q_MASK 0x00200000L +#define MH_DEBUG_REG22__CP_RTR_q 0x00200000L +#define MH_DEBUG_REG22__VGT_SEND_q_MASK 0x00400000L +#define MH_DEBUG_REG22__VGT_SEND_q 0x00400000L +#define MH_DEBUG_REG22__VGT_RTR_q_MASK 0x00800000L +#define MH_DEBUG_REG22__VGT_RTR_q 0x00800000L +#define MH_DEBUG_REG22__TC_ROQ_SEND_q_MASK 0x01000000L +#define MH_DEBUG_REG22__TC_ROQ_SEND_q 0x01000000L +#define MH_DEBUG_REG22__TC_ROQ_RTR_q_MASK 0x02000000L +#define MH_DEBUG_REG22__TC_ROQ_RTR_q 0x02000000L +#define MH_DEBUG_REG22__RB_SEND_q_MASK 0x04000000L +#define MH_DEBUG_REG22__RB_SEND_q 0x04000000L +#define MH_DEBUG_REG22__RB_RTR_q_MASK 0x08000000L +#define MH_DEBUG_REG22__RB_RTR_q 0x08000000L +#define MH_DEBUG_REG22__RDC_VALID_MASK 0x10000000L +#define MH_DEBUG_REG22__RDC_VALID 0x10000000L +#define MH_DEBUG_REG22__RDC_RLAST_MASK 0x20000000L +#define MH_DEBUG_REG22__RDC_RLAST 0x20000000L +#define MH_DEBUG_REG22__TLBMISS_VALID_MASK 0x40000000L +#define MH_DEBUG_REG22__TLBMISS_VALID 0x40000000L +#define MH_DEBUG_REG22__BRC_VALID_MASK 0x80000000L +#define MH_DEBUG_REG22__BRC_VALID 0x80000000L + +// MH_DEBUG_REG23 +#define MH_DEBUG_REG23__EFF2_FP_WINNER_MASK 0x00000007L +#define MH_DEBUG_REG23__EFF2_LRU_WINNER_out_MASK 0x00000038L +#define MH_DEBUG_REG23__EFF1_WINNER_MASK 0x000001c0L +#define MH_DEBUG_REG23__ARB_WINNER_MASK 0x00000e00L +#define MH_DEBUG_REG23__ARB_WINNER_q_MASK 0x00007000L +#define MH_DEBUG_REG23__EFF1_WIN_MASK 0x00008000L +#define MH_DEBUG_REG23__EFF1_WIN 0x00008000L +#define MH_DEBUG_REG23__KILL_EFF1_MASK 0x00010000L +#define MH_DEBUG_REG23__KILL_EFF1 0x00010000L +#define MH_DEBUG_REG23__ARB_HOLD_MASK 0x00020000L +#define MH_DEBUG_REG23__ARB_HOLD 0x00020000L +#define MH_DEBUG_REG23__ARB_RTR_q_MASK 0x00040000L +#define MH_DEBUG_REG23__ARB_RTR_q 0x00040000L +#define MH_DEBUG_REG23__CP_SEND_QUAL_MASK 0x00080000L +#define MH_DEBUG_REG23__CP_SEND_QUAL 0x00080000L +#define MH_DEBUG_REG23__VGT_SEND_QUAL_MASK 0x00100000L +#define MH_DEBUG_REG23__VGT_SEND_QUAL 0x00100000L +#define MH_DEBUG_REG23__TC_SEND_QUAL_MASK 0x00200000L +#define MH_DEBUG_REG23__TC_SEND_QUAL 0x00200000L +#define MH_DEBUG_REG23__TC_SEND_EFF1_QUAL_MASK 0x00400000L +#define MH_DEBUG_REG23__TC_SEND_EFF1_QUAL 0x00400000L +#define MH_DEBUG_REG23__RB_SEND_QUAL_MASK 0x00800000L +#define MH_DEBUG_REG23__RB_SEND_QUAL 0x00800000L +#define MH_DEBUG_REG23__ARB_QUAL_MASK 0x01000000L +#define MH_DEBUG_REG23__ARB_QUAL 0x01000000L +#define MH_DEBUG_REG23__CP_EFF1_REQ_MASK 0x02000000L +#define MH_DEBUG_REG23__CP_EFF1_REQ 0x02000000L +#define MH_DEBUG_REG23__VGT_EFF1_REQ_MASK 0x04000000L +#define MH_DEBUG_REG23__VGT_EFF1_REQ 0x04000000L +#define MH_DEBUG_REG23__TC_EFF1_REQ_MASK 0x08000000L +#define MH_DEBUG_REG23__TC_EFF1_REQ 0x08000000L +#define MH_DEBUG_REG23__RB_EFF1_REQ_MASK 0x10000000L +#define MH_DEBUG_REG23__RB_EFF1_REQ 0x10000000L +#define MH_DEBUG_REG23__ANY_SAME_ROW_BANK_MASK 0x20000000L +#define MH_DEBUG_REG23__ANY_SAME_ROW_BANK 0x20000000L +#define MH_DEBUG_REG23__TCD_NEARFULL_q_MASK 0x40000000L +#define MH_DEBUG_REG23__TCD_NEARFULL_q 0x40000000L +#define MH_DEBUG_REG23__TCHOLD_IP_q_MASK 0x80000000L +#define MH_DEBUG_REG23__TCHOLD_IP_q 0x80000000L + +// MH_DEBUG_REG24 +#define MH_DEBUG_REG24__EFF1_WINNER_MASK 0x00000007L +#define MH_DEBUG_REG24__ARB_WINNER_MASK 0x00000038L +#define MH_DEBUG_REG24__CP_SEND_QUAL_MASK 0x00000040L +#define MH_DEBUG_REG24__CP_SEND_QUAL 0x00000040L +#define MH_DEBUG_REG24__VGT_SEND_QUAL_MASK 0x00000080L +#define MH_DEBUG_REG24__VGT_SEND_QUAL 0x00000080L +#define MH_DEBUG_REG24__TC_SEND_QUAL_MASK 0x00000100L +#define MH_DEBUG_REG24__TC_SEND_QUAL 0x00000100L +#define MH_DEBUG_REG24__TC_SEND_EFF1_QUAL_MASK 0x00000200L +#define MH_DEBUG_REG24__TC_SEND_EFF1_QUAL 0x00000200L +#define MH_DEBUG_REG24__RB_SEND_QUAL_MASK 0x00000400L +#define MH_DEBUG_REG24__RB_SEND_QUAL 0x00000400L +#define MH_DEBUG_REG24__ARB_QUAL_MASK 0x00000800L +#define MH_DEBUG_REG24__ARB_QUAL 0x00000800L +#define MH_DEBUG_REG24__CP_EFF1_REQ_MASK 0x00001000L +#define MH_DEBUG_REG24__CP_EFF1_REQ 0x00001000L +#define MH_DEBUG_REG24__VGT_EFF1_REQ_MASK 0x00002000L +#define MH_DEBUG_REG24__VGT_EFF1_REQ 0x00002000L +#define MH_DEBUG_REG24__TC_EFF1_REQ_MASK 0x00004000L +#define MH_DEBUG_REG24__TC_EFF1_REQ 0x00004000L +#define MH_DEBUG_REG24__RB_EFF1_REQ_MASK 0x00008000L +#define MH_DEBUG_REG24__RB_EFF1_REQ 0x00008000L +#define MH_DEBUG_REG24__EFF1_WIN_MASK 0x00010000L +#define MH_DEBUG_REG24__EFF1_WIN 0x00010000L +#define MH_DEBUG_REG24__KILL_EFF1_MASK 0x00020000L +#define MH_DEBUG_REG24__KILL_EFF1 0x00020000L +#define MH_DEBUG_REG24__TCD_NEARFULL_q_MASK 0x00040000L +#define MH_DEBUG_REG24__TCD_NEARFULL_q 0x00040000L +#define MH_DEBUG_REG24__TC_ARB_HOLD_MASK 0x00080000L +#define MH_DEBUG_REG24__TC_ARB_HOLD 0x00080000L +#define MH_DEBUG_REG24__ARB_HOLD_MASK 0x00100000L +#define MH_DEBUG_REG24__ARB_HOLD 0x00100000L +#define MH_DEBUG_REG24__ARB_RTR_q_MASK 0x00200000L +#define MH_DEBUG_REG24__ARB_RTR_q 0x00200000L +#define MH_DEBUG_REG24__SAME_PAGE_LIMIT_COUNT_q_MASK 0xffc00000L + +// MH_DEBUG_REG25 +#define MH_DEBUG_REG25__EFF2_LRU_WINNER_out_MASK 0x00000007L +#define MH_DEBUG_REG25__ARB_WINNER_MASK 0x00000038L +#define MH_DEBUG_REG25__LEAST_RECENT_INDEX_d_MASK 0x000001c0L +#define MH_DEBUG_REG25__LEAST_RECENT_d_MASK 0x00000e00L +#define MH_DEBUG_REG25__UPDATE_RECENT_STACK_d_MASK 0x00001000L +#define MH_DEBUG_REG25__UPDATE_RECENT_STACK_d 0x00001000L +#define MH_DEBUG_REG25__ARB_HOLD_MASK 0x00002000L +#define MH_DEBUG_REG25__ARB_HOLD 0x00002000L +#define MH_DEBUG_REG25__ARB_RTR_q_MASK 0x00004000L +#define MH_DEBUG_REG25__ARB_RTR_q 0x00004000L +#define MH_DEBUG_REG25__EFF1_WIN_MASK 0x00008000L +#define MH_DEBUG_REG25__EFF1_WIN 0x00008000L +#define MH_DEBUG_REG25__CLNT_REQ_MASK 0x000f0000L +#define MH_DEBUG_REG25__RECENT_d_0_MASK 0x00700000L +#define MH_DEBUG_REG25__RECENT_d_1_MASK 0x03800000L +#define MH_DEBUG_REG25__RECENT_d_2_MASK 0x1c000000L +#define MH_DEBUG_REG25__RECENT_d_3_MASK 0xe0000000L + +// MH_DEBUG_REG26 +#define MH_DEBUG_REG26__TC_ARB_HOLD_MASK 0x00000001L +#define MH_DEBUG_REG26__TC_ARB_HOLD 0x00000001L +#define MH_DEBUG_REG26__TC_NOROQ_SAME_ROW_BANK_MASK 0x00000002L +#define MH_DEBUG_REG26__TC_NOROQ_SAME_ROW_BANK 0x00000002L +#define MH_DEBUG_REG26__TC_ROQ_SAME_ROW_BANK_MASK 0x00000004L +#define MH_DEBUG_REG26__TC_ROQ_SAME_ROW_BANK 0x00000004L +#define MH_DEBUG_REG26__TCD_NEARFULL_q_MASK 0x00000008L +#define MH_DEBUG_REG26__TCD_NEARFULL_q 0x00000008L +#define MH_DEBUG_REG26__TCHOLD_IP_q_MASK 0x00000010L +#define MH_DEBUG_REG26__TCHOLD_IP_q 0x00000010L +#define MH_DEBUG_REG26__TCHOLD_CNT_q_MASK 0x000000e0L +#define MH_DEBUG_REG26__MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00000100L +#define MH_DEBUG_REG26__MH_ARBITER_CONFIG_TC_REORDER_ENABLE 0x00000100L +#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q_MASK 0x00000200L +#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q 0x00000200L +#define MH_DEBUG_REG26__TC_ROQ_SEND_q_MASK 0x00000400L +#define MH_DEBUG_REG26__TC_ROQ_SEND_q 0x00000400L +#define MH_DEBUG_REG26__TC_MH_written_MASK 0x00000800L +#define MH_DEBUG_REG26__TC_MH_written 0x00000800L +#define MH_DEBUG_REG26__TCD_FULLNESS_CNT_q_MASK 0x0007f000L +#define MH_DEBUG_REG26__WBURST_ACTIVE_MASK 0x00080000L +#define MH_DEBUG_REG26__WBURST_ACTIVE 0x00080000L +#define MH_DEBUG_REG26__WLAST_q_MASK 0x00100000L +#define MH_DEBUG_REG26__WLAST_q 0x00100000L +#define MH_DEBUG_REG26__WBURST_IP_q_MASK 0x00200000L +#define MH_DEBUG_REG26__WBURST_IP_q 0x00200000L +#define MH_DEBUG_REG26__WBURST_CNT_q_MASK 0x01c00000L +#define MH_DEBUG_REG26__CP_SEND_QUAL_MASK 0x02000000L +#define MH_DEBUG_REG26__CP_SEND_QUAL 0x02000000L +#define MH_DEBUG_REG26__CP_MH_write_MASK 0x04000000L +#define MH_DEBUG_REG26__CP_MH_write 0x04000000L +#define MH_DEBUG_REG26__RB_SEND_QUAL_MASK 0x08000000L +#define MH_DEBUG_REG26__RB_SEND_QUAL 0x08000000L +#define MH_DEBUG_REG26__ARB_WINNER_MASK 0x70000000L + +// MH_DEBUG_REG27 +#define MH_DEBUG_REG27__RF_ARBITER_CONFIG_q_MASK 0x03ffffffL +#define MH_DEBUG_REG27__MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x1c000000L + +// MH_DEBUG_REG28 +#define MH_DEBUG_REG28__SAME_ROW_BANK_q_MASK 0x000000ffL +#define MH_DEBUG_REG28__ROQ_MARK_q_MASK 0x0000ff00L +#define MH_DEBUG_REG28__ROQ_VALID_q_MASK 0x00ff0000L +#define MH_DEBUG_REG28__TC_MH_send_MASK 0x01000000L +#define MH_DEBUG_REG28__TC_MH_send 0x01000000L +#define MH_DEBUG_REG28__TC_ROQ_RTR_q_MASK 0x02000000L +#define MH_DEBUG_REG28__TC_ROQ_RTR_q 0x02000000L +#define MH_DEBUG_REG28__KILL_EFF1_MASK 0x04000000L +#define MH_DEBUG_REG28__KILL_EFF1 0x04000000L +#define MH_DEBUG_REG28__TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000L +#define MH_DEBUG_REG28__TC_ROQ_SAME_ROW_BANK_SEL 0x08000000L +#define MH_DEBUG_REG28__ANY_SAME_ROW_BANK_MASK 0x10000000L +#define MH_DEBUG_REG28__ANY_SAME_ROW_BANK 0x10000000L +#define MH_DEBUG_REG28__TC_EFF1_QUAL_MASK 0x20000000L +#define MH_DEBUG_REG28__TC_EFF1_QUAL 0x20000000L +#define MH_DEBUG_REG28__TC_ROQ_EMPTY_MASK 0x40000000L +#define MH_DEBUG_REG28__TC_ROQ_EMPTY 0x40000000L +#define MH_DEBUG_REG28__TC_ROQ_FULL_MASK 0x80000000L +#define MH_DEBUG_REG28__TC_ROQ_FULL 0x80000000L + +// MH_DEBUG_REG29 +#define MH_DEBUG_REG29__SAME_ROW_BANK_q_MASK 0x000000ffL +#define MH_DEBUG_REG29__ROQ_MARK_d_MASK 0x0000ff00L +#define MH_DEBUG_REG29__ROQ_VALID_d_MASK 0x00ff0000L +#define MH_DEBUG_REG29__TC_MH_send_MASK 0x01000000L +#define MH_DEBUG_REG29__TC_MH_send 0x01000000L +#define MH_DEBUG_REG29__TC_ROQ_RTR_q_MASK 0x02000000L +#define MH_DEBUG_REG29__TC_ROQ_RTR_q 0x02000000L +#define MH_DEBUG_REG29__KILL_EFF1_MASK 0x04000000L +#define MH_DEBUG_REG29__KILL_EFF1 0x04000000L +#define MH_DEBUG_REG29__TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000L +#define MH_DEBUG_REG29__TC_ROQ_SAME_ROW_BANK_SEL 0x08000000L +#define MH_DEBUG_REG29__ANY_SAME_ROW_BANK_MASK 0x10000000L +#define MH_DEBUG_REG29__ANY_SAME_ROW_BANK 0x10000000L +#define MH_DEBUG_REG29__TC_EFF1_QUAL_MASK 0x20000000L +#define MH_DEBUG_REG29__TC_EFF1_QUAL 0x20000000L +#define MH_DEBUG_REG29__TC_ROQ_EMPTY_MASK 0x40000000L +#define MH_DEBUG_REG29__TC_ROQ_EMPTY 0x40000000L +#define MH_DEBUG_REG29__TC_ROQ_FULL_MASK 0x80000000L +#define MH_DEBUG_REG29__TC_ROQ_FULL 0x80000000L + +// MH_DEBUG_REG30 +#define MH_DEBUG_REG30__SAME_ROW_BANK_WIN_MASK 0x000000ffL +#define MH_DEBUG_REG30__SAME_ROW_BANK_REQ_MASK 0x0000ff00L +#define MH_DEBUG_REG30__NON_SAME_ROW_BANK_WIN_MASK 0x00ff0000L +#define MH_DEBUG_REG30__NON_SAME_ROW_BANK_REQ_MASK 0xff000000L + +// MH_DEBUG_REG31 +#define MH_DEBUG_REG31__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG31__TC_MH_send 0x00000001L +#define MH_DEBUG_REG31__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG31__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG31__ROQ_MARK_q_0_MASK 0x00000004L +#define MH_DEBUG_REG31__ROQ_MARK_q_0 0x00000004L +#define MH_DEBUG_REG31__ROQ_VALID_q_0_MASK 0x00000008L +#define MH_DEBUG_REG31__ROQ_VALID_q_0 0x00000008L +#define MH_DEBUG_REG31__SAME_ROW_BANK_q_0_MASK 0x00000010L +#define MH_DEBUG_REG31__SAME_ROW_BANK_q_0 0x00000010L +#define MH_DEBUG_REG31__ROQ_ADDR_0_MASK 0xffffffe0L + +// MH_DEBUG_REG32 +#define MH_DEBUG_REG32__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG32__TC_MH_send 0x00000001L +#define MH_DEBUG_REG32__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG32__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG32__ROQ_MARK_q_1_MASK 0x00000004L +#define MH_DEBUG_REG32__ROQ_MARK_q_1 0x00000004L +#define MH_DEBUG_REG32__ROQ_VALID_q_1_MASK 0x00000008L +#define MH_DEBUG_REG32__ROQ_VALID_q_1 0x00000008L +#define MH_DEBUG_REG32__SAME_ROW_BANK_q_1_MASK 0x00000010L +#define MH_DEBUG_REG32__SAME_ROW_BANK_q_1 0x00000010L +#define MH_DEBUG_REG32__ROQ_ADDR_1_MASK 0xffffffe0L + +// MH_DEBUG_REG33 +#define MH_DEBUG_REG33__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG33__TC_MH_send 0x00000001L +#define MH_DEBUG_REG33__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG33__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG33__ROQ_MARK_q_2_MASK 0x00000004L +#define MH_DEBUG_REG33__ROQ_MARK_q_2 0x00000004L +#define MH_DEBUG_REG33__ROQ_VALID_q_2_MASK 0x00000008L +#define MH_DEBUG_REG33__ROQ_VALID_q_2 0x00000008L +#define MH_DEBUG_REG33__SAME_ROW_BANK_q_2_MASK 0x00000010L +#define MH_DEBUG_REG33__SAME_ROW_BANK_q_2 0x00000010L +#define MH_DEBUG_REG33__ROQ_ADDR_2_MASK 0xffffffe0L + +// MH_DEBUG_REG34 +#define MH_DEBUG_REG34__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG34__TC_MH_send 0x00000001L +#define MH_DEBUG_REG34__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG34__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG34__ROQ_MARK_q_3_MASK 0x00000004L +#define MH_DEBUG_REG34__ROQ_MARK_q_3 0x00000004L +#define MH_DEBUG_REG34__ROQ_VALID_q_3_MASK 0x00000008L +#define MH_DEBUG_REG34__ROQ_VALID_q_3 0x00000008L +#define MH_DEBUG_REG34__SAME_ROW_BANK_q_3_MASK 0x00000010L +#define MH_DEBUG_REG34__SAME_ROW_BANK_q_3 0x00000010L +#define MH_DEBUG_REG34__ROQ_ADDR_3_MASK 0xffffffe0L + +// MH_DEBUG_REG35 +#define MH_DEBUG_REG35__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG35__TC_MH_send 0x00000001L +#define MH_DEBUG_REG35__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG35__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG35__ROQ_MARK_q_4_MASK 0x00000004L +#define MH_DEBUG_REG35__ROQ_MARK_q_4 0x00000004L +#define MH_DEBUG_REG35__ROQ_VALID_q_4_MASK 0x00000008L +#define MH_DEBUG_REG35__ROQ_VALID_q_4 0x00000008L +#define MH_DEBUG_REG35__SAME_ROW_BANK_q_4_MASK 0x00000010L +#define MH_DEBUG_REG35__SAME_ROW_BANK_q_4 0x00000010L +#define MH_DEBUG_REG35__ROQ_ADDR_4_MASK 0xffffffe0L + +// MH_DEBUG_REG36 +#define MH_DEBUG_REG36__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG36__TC_MH_send 0x00000001L +#define MH_DEBUG_REG36__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG36__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG36__ROQ_MARK_q_5_MASK 0x00000004L +#define MH_DEBUG_REG36__ROQ_MARK_q_5 0x00000004L +#define MH_DEBUG_REG36__ROQ_VALID_q_5_MASK 0x00000008L +#define MH_DEBUG_REG36__ROQ_VALID_q_5 0x00000008L +#define MH_DEBUG_REG36__SAME_ROW_BANK_q_5_MASK 0x00000010L +#define MH_DEBUG_REG36__SAME_ROW_BANK_q_5 0x00000010L +#define MH_DEBUG_REG36__ROQ_ADDR_5_MASK 0xffffffe0L + +// MH_DEBUG_REG37 +#define MH_DEBUG_REG37__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG37__TC_MH_send 0x00000001L +#define MH_DEBUG_REG37__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG37__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG37__ROQ_MARK_q_6_MASK 0x00000004L +#define MH_DEBUG_REG37__ROQ_MARK_q_6 0x00000004L +#define MH_DEBUG_REG37__ROQ_VALID_q_6_MASK 0x00000008L +#define MH_DEBUG_REG37__ROQ_VALID_q_6 0x00000008L +#define MH_DEBUG_REG37__SAME_ROW_BANK_q_6_MASK 0x00000010L +#define MH_DEBUG_REG37__SAME_ROW_BANK_q_6 0x00000010L +#define MH_DEBUG_REG37__ROQ_ADDR_6_MASK 0xffffffe0L + +// MH_DEBUG_REG38 +#define MH_DEBUG_REG38__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG38__TC_MH_send 0x00000001L +#define MH_DEBUG_REG38__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG38__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG38__ROQ_MARK_q_7_MASK 0x00000004L +#define MH_DEBUG_REG38__ROQ_MARK_q_7 0x00000004L +#define MH_DEBUG_REG38__ROQ_VALID_q_7_MASK 0x00000008L +#define MH_DEBUG_REG38__ROQ_VALID_q_7 0x00000008L +#define MH_DEBUG_REG38__SAME_ROW_BANK_q_7_MASK 0x00000010L +#define MH_DEBUG_REG38__SAME_ROW_BANK_q_7 0x00000010L +#define MH_DEBUG_REG38__ROQ_ADDR_7_MASK 0xffffffe0L + +// MH_DEBUG_REG39 +#define MH_DEBUG_REG39__ARB_WE_MASK 0x00000001L +#define MH_DEBUG_REG39__ARB_WE 0x00000001L +#define MH_DEBUG_REG39__MMU_RTR_MASK 0x00000002L +#define MH_DEBUG_REG39__MMU_RTR 0x00000002L +#define MH_DEBUG_REG39__ARB_ID_q_MASK 0x0000001cL +#define MH_DEBUG_REG39__ARB_WRITE_q_MASK 0x00000020L +#define MH_DEBUG_REG39__ARB_WRITE_q 0x00000020L +#define MH_DEBUG_REG39__ARB_BLEN_q_MASK 0x00000040L +#define MH_DEBUG_REG39__ARB_BLEN_q 0x00000040L +#define MH_DEBUG_REG39__ARQ_CTRL_EMPTY_MASK 0x00000080L +#define MH_DEBUG_REG39__ARQ_CTRL_EMPTY 0x00000080L +#define MH_DEBUG_REG39__ARQ_FIFO_CNT_q_MASK 0x00000700L +#define MH_DEBUG_REG39__MMU_WE_MASK 0x00000800L +#define MH_DEBUG_REG39__MMU_WE 0x00000800L +#define MH_DEBUG_REG39__ARQ_RTR_MASK 0x00001000L +#define MH_DEBUG_REG39__ARQ_RTR 0x00001000L +#define MH_DEBUG_REG39__MMU_ID_MASK 0x0000e000L +#define MH_DEBUG_REG39__MMU_WRITE_MASK 0x00010000L +#define MH_DEBUG_REG39__MMU_WRITE 0x00010000L +#define MH_DEBUG_REG39__MMU_BLEN_MASK 0x00020000L +#define MH_DEBUG_REG39__MMU_BLEN 0x00020000L + +// MH_DEBUG_REG40 +#define MH_DEBUG_REG40__ARB_WE_MASK 0x00000001L +#define MH_DEBUG_REG40__ARB_WE 0x00000001L +#define MH_DEBUG_REG40__ARB_ID_q_MASK 0x0000000eL +#define MH_DEBUG_REG40__ARB_VAD_q_MASK 0xfffffff0L + +// MH_DEBUG_REG41 +#define MH_DEBUG_REG41__MMU_WE_MASK 0x00000001L +#define MH_DEBUG_REG41__MMU_WE 0x00000001L +#define MH_DEBUG_REG41__MMU_ID_MASK 0x0000000eL +#define MH_DEBUG_REG41__MMU_PAD_MASK 0xfffffff0L + +// MH_DEBUG_REG42 +#define MH_DEBUG_REG42__WDB_WE_MASK 0x00000001L +#define MH_DEBUG_REG42__WDB_WE 0x00000001L +#define MH_DEBUG_REG42__WDB_RTR_SKID_MASK 0x00000002L +#define MH_DEBUG_REG42__WDB_RTR_SKID 0x00000002L +#define MH_DEBUG_REG42__ARB_WSTRB_q_MASK 0x000003fcL +#define MH_DEBUG_REG42__ARB_WLAST_MASK 0x00000400L +#define MH_DEBUG_REG42__ARB_WLAST 0x00000400L +#define MH_DEBUG_REG42__WDB_CTRL_EMPTY_MASK 0x00000800L +#define MH_DEBUG_REG42__WDB_CTRL_EMPTY 0x00000800L +#define MH_DEBUG_REG42__WDB_FIFO_CNT_q_MASK 0x0001f000L +#define MH_DEBUG_REG42__WDC_WDB_RE_q_MASK 0x00020000L +#define MH_DEBUG_REG42__WDC_WDB_RE_q 0x00020000L +#define MH_DEBUG_REG42__WDB_WDC_WID_MASK 0x001c0000L +#define MH_DEBUG_REG42__WDB_WDC_WLAST_MASK 0x00200000L +#define MH_DEBUG_REG42__WDB_WDC_WLAST 0x00200000L +#define MH_DEBUG_REG42__WDB_WDC_WSTRB_MASK 0x3fc00000L + +// MH_DEBUG_REG43 +#define MH_DEBUG_REG43__ARB_WDATA_q_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG44 +#define MH_DEBUG_REG44__ARB_WDATA_q_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG45 +#define MH_DEBUG_REG45__WDB_WDC_WDATA_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG46 +#define MH_DEBUG_REG46__WDB_WDC_WDATA_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG47 +#define MH_DEBUG_REG47__CTRL_ARC_EMPTY_MASK 0x00000001L +#define MH_DEBUG_REG47__CTRL_ARC_EMPTY 0x00000001L +#define MH_DEBUG_REG47__CTRL_RARC_EMPTY_MASK 0x00000002L +#define MH_DEBUG_REG47__CTRL_RARC_EMPTY 0x00000002L +#define MH_DEBUG_REG47__ARQ_CTRL_EMPTY_MASK 0x00000004L +#define MH_DEBUG_REG47__ARQ_CTRL_EMPTY 0x00000004L +#define MH_DEBUG_REG47__ARQ_CTRL_WRITE_MASK 0x00000008L +#define MH_DEBUG_REG47__ARQ_CTRL_WRITE 0x00000008L +#define MH_DEBUG_REG47__TLBMISS_CTRL_RTS_MASK 0x00000010L +#define MH_DEBUG_REG47__TLBMISS_CTRL_RTS 0x00000010L +#define MH_DEBUG_REG47__CTRL_TLBMISS_RE_q_MASK 0x00000020L +#define MH_DEBUG_REG47__CTRL_TLBMISS_RE_q 0x00000020L +#define MH_DEBUG_REG47__INFLT_LIMIT_q_MASK 0x00000040L +#define MH_DEBUG_REG47__INFLT_LIMIT_q 0x00000040L +#define MH_DEBUG_REG47__INFLT_LIMIT_CNT_q_MASK 0x00001f80L +#define MH_DEBUG_REG47__ARC_CTRL_RE_q_MASK 0x00002000L +#define MH_DEBUG_REG47__ARC_CTRL_RE_q 0x00002000L +#define MH_DEBUG_REG47__RARC_CTRL_RE_q_MASK 0x00004000L +#define MH_DEBUG_REG47__RARC_CTRL_RE_q 0x00004000L +#define MH_DEBUG_REG47__RVALID_q_MASK 0x00008000L +#define MH_DEBUG_REG47__RVALID_q 0x00008000L +#define MH_DEBUG_REG47__RREADY_q_MASK 0x00010000L +#define MH_DEBUG_REG47__RREADY_q 0x00010000L +#define MH_DEBUG_REG47__RLAST_q_MASK 0x00020000L +#define MH_DEBUG_REG47__RLAST_q 0x00020000L +#define MH_DEBUG_REG47__BVALID_q_MASK 0x00040000L +#define MH_DEBUG_REG47__BVALID_q 0x00040000L +#define MH_DEBUG_REG47__BREADY_q_MASK 0x00080000L +#define MH_DEBUG_REG47__BREADY_q 0x00080000L + +// MH_DEBUG_REG48 +#define MH_DEBUG_REG48__MH_CP_grb_send_MASK 0x00000001L +#define MH_DEBUG_REG48__MH_CP_grb_send 0x00000001L +#define MH_DEBUG_REG48__MH_VGT_grb_send_MASK 0x00000002L +#define MH_DEBUG_REG48__MH_VGT_grb_send 0x00000002L +#define MH_DEBUG_REG48__MH_TC_mcsend_MASK 0x00000004L +#define MH_DEBUG_REG48__MH_TC_mcsend 0x00000004L +#define MH_DEBUG_REG48__MH_TLBMISS_SEND_MASK 0x00000008L +#define MH_DEBUG_REG48__MH_TLBMISS_SEND 0x00000008L +#define MH_DEBUG_REG48__TLBMISS_VALID_MASK 0x00000010L +#define MH_DEBUG_REG48__TLBMISS_VALID 0x00000010L +#define MH_DEBUG_REG48__RDC_VALID_MASK 0x00000020L +#define MH_DEBUG_REG48__RDC_VALID 0x00000020L +#define MH_DEBUG_REG48__RDC_RID_MASK 0x000001c0L +#define MH_DEBUG_REG48__RDC_RLAST_MASK 0x00000200L +#define MH_DEBUG_REG48__RDC_RLAST 0x00000200L +#define MH_DEBUG_REG48__RDC_RRESP_MASK 0x00000c00L +#define MH_DEBUG_REG48__TLBMISS_CTRL_RTS_MASK 0x00001000L +#define MH_DEBUG_REG48__TLBMISS_CTRL_RTS 0x00001000L +#define MH_DEBUG_REG48__CTRL_TLBMISS_RE_q_MASK 0x00002000L +#define MH_DEBUG_REG48__CTRL_TLBMISS_RE_q 0x00002000L +#define MH_DEBUG_REG48__MMU_ID_REQUEST_q_MASK 0x00004000L +#define MH_DEBUG_REG48__MMU_ID_REQUEST_q 0x00004000L +#define MH_DEBUG_REG48__OUTSTANDING_MMUID_CNT_q_MASK 0x001f8000L +#define MH_DEBUG_REG48__MMU_ID_RESPONSE_MASK 0x00200000L +#define MH_DEBUG_REG48__MMU_ID_RESPONSE 0x00200000L +#define MH_DEBUG_REG48__TLBMISS_RETURN_CNT_q_MASK 0x0fc00000L +#define MH_DEBUG_REG48__CNT_HOLD_q1_MASK 0x10000000L +#define MH_DEBUG_REG48__CNT_HOLD_q1 0x10000000L +#define MH_DEBUG_REG48__MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0xe0000000L + +// MH_DEBUG_REG49 +#define MH_DEBUG_REG49__RF_MMU_PAGE_FAULT_MASK 0xffffffffL + +// MH_DEBUG_REG50 +#define MH_DEBUG_REG50__RF_MMU_CONFIG_q_MASK 0x00ffffffL +#define MH_DEBUG_REG50__ARB_ID_q_MASK 0x07000000L +#define MH_DEBUG_REG50__ARB_WRITE_q_MASK 0x08000000L +#define MH_DEBUG_REG50__ARB_WRITE_q 0x08000000L +#define MH_DEBUG_REG50__client_behavior_q_MASK 0x30000000L +#define MH_DEBUG_REG50__ARB_WE_MASK 0x40000000L +#define MH_DEBUG_REG50__ARB_WE 0x40000000L +#define MH_DEBUG_REG50__MMU_RTR_MASK 0x80000000L +#define MH_DEBUG_REG50__MMU_RTR 0x80000000L + +// MH_DEBUG_REG51 +#define MH_DEBUG_REG51__stage1_valid_MASK 0x00000001L +#define MH_DEBUG_REG51__stage1_valid 0x00000001L +#define MH_DEBUG_REG51__IGNORE_TAG_MISS_q_MASK 0x00000002L +#define MH_DEBUG_REG51__IGNORE_TAG_MISS_q 0x00000002L +#define MH_DEBUG_REG51__pa_in_mpu_range_MASK 0x00000004L +#define MH_DEBUG_REG51__pa_in_mpu_range 0x00000004L +#define MH_DEBUG_REG51__tag_match_q_MASK 0x00000008L +#define MH_DEBUG_REG51__tag_match_q 0x00000008L +#define MH_DEBUG_REG51__tag_miss_q_MASK 0x00000010L +#define MH_DEBUG_REG51__tag_miss_q 0x00000010L +#define MH_DEBUG_REG51__va_in_range_q_MASK 0x00000020L +#define MH_DEBUG_REG51__va_in_range_q 0x00000020L +#define MH_DEBUG_REG51__MMU_MISS_MASK 0x00000040L +#define MH_DEBUG_REG51__MMU_MISS 0x00000040L +#define MH_DEBUG_REG51__MMU_READ_MISS_MASK 0x00000080L +#define MH_DEBUG_REG51__MMU_READ_MISS 0x00000080L +#define MH_DEBUG_REG51__MMU_WRITE_MISS_MASK 0x00000100L +#define MH_DEBUG_REG51__MMU_WRITE_MISS 0x00000100L +#define MH_DEBUG_REG51__MMU_HIT_MASK 0x00000200L +#define MH_DEBUG_REG51__MMU_HIT 0x00000200L +#define MH_DEBUG_REG51__MMU_READ_HIT_MASK 0x00000400L +#define MH_DEBUG_REG51__MMU_READ_HIT 0x00000400L +#define MH_DEBUG_REG51__MMU_WRITE_HIT_MASK 0x00000800L +#define MH_DEBUG_REG51__MMU_WRITE_HIT 0x00000800L +#define MH_DEBUG_REG51__MMU_SPLIT_MODE_TC_MISS_MASK 0x00001000L +#define MH_DEBUG_REG51__MMU_SPLIT_MODE_TC_MISS 0x00001000L +#define MH_DEBUG_REG51__MMU_SPLIT_MODE_TC_HIT_MASK 0x00002000L +#define MH_DEBUG_REG51__MMU_SPLIT_MODE_TC_HIT 0x00002000L +#define MH_DEBUG_REG51__MMU_SPLIT_MODE_nonTC_MISS_MASK 0x00004000L +#define MH_DEBUG_REG51__MMU_SPLIT_MODE_nonTC_MISS 0x00004000L +#define MH_DEBUG_REG51__MMU_SPLIT_MODE_nonTC_HIT_MASK 0x00008000L +#define MH_DEBUG_REG51__MMU_SPLIT_MODE_nonTC_HIT 0x00008000L +#define MH_DEBUG_REG51__REQ_VA_OFFSET_q_MASK 0xffff0000L + +// MH_DEBUG_REG52 +#define MH_DEBUG_REG52__ARQ_RTR_MASK 0x00000001L +#define MH_DEBUG_REG52__ARQ_RTR 0x00000001L +#define MH_DEBUG_REG52__MMU_WE_MASK 0x00000002L +#define MH_DEBUG_REG52__MMU_WE 0x00000002L +#define MH_DEBUG_REG52__CTRL_TLBMISS_RE_q_MASK 0x00000004L +#define MH_DEBUG_REG52__CTRL_TLBMISS_RE_q 0x00000004L +#define MH_DEBUG_REG52__TLBMISS_CTRL_RTS_MASK 0x00000008L +#define MH_DEBUG_REG52__TLBMISS_CTRL_RTS 0x00000008L +#define MH_DEBUG_REG52__MH_TLBMISS_SEND_MASK 0x00000010L +#define MH_DEBUG_REG52__MH_TLBMISS_SEND 0x00000010L +#define MH_DEBUG_REG52__MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK 0x00000020L +#define MH_DEBUG_REG52__MMU_STALL_AWAITING_TLB_MISS_FETCH 0x00000020L +#define MH_DEBUG_REG52__pa_in_mpu_range_MASK 0x00000040L +#define MH_DEBUG_REG52__pa_in_mpu_range 0x00000040L +#define MH_DEBUG_REG52__stage1_valid_MASK 0x00000080L +#define MH_DEBUG_REG52__stage1_valid 0x00000080L +#define MH_DEBUG_REG52__stage2_valid_MASK 0x00000100L +#define MH_DEBUG_REG52__stage2_valid 0x00000100L +#define MH_DEBUG_REG52__client_behavior_q_MASK 0x00000600L +#define MH_DEBUG_REG52__IGNORE_TAG_MISS_q_MASK 0x00000800L +#define MH_DEBUG_REG52__IGNORE_TAG_MISS_q 0x00000800L +#define MH_DEBUG_REG52__tag_match_q_MASK 0x00001000L +#define MH_DEBUG_REG52__tag_match_q 0x00001000L +#define MH_DEBUG_REG52__tag_miss_q_MASK 0x00002000L +#define MH_DEBUG_REG52__tag_miss_q 0x00002000L +#define MH_DEBUG_REG52__va_in_range_q_MASK 0x00004000L +#define MH_DEBUG_REG52__va_in_range_q 0x00004000L +#define MH_DEBUG_REG52__PTE_FETCH_COMPLETE_q_MASK 0x00008000L +#define MH_DEBUG_REG52__PTE_FETCH_COMPLETE_q 0x00008000L +#define MH_DEBUG_REG52__TAG_valid_q_MASK 0xffff0000L + +// MH_DEBUG_REG53 +#define MH_DEBUG_REG53__TAG0_VA_MASK 0x00001fffL +#define MH_DEBUG_REG53__TAG_valid_q_0_MASK 0x00002000L +#define MH_DEBUG_REG53__TAG_valid_q_0 0x00002000L +#define MH_DEBUG_REG53__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG53__TAG1_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG53__TAG_valid_q_1_MASK 0x20000000L +#define MH_DEBUG_REG53__TAG_valid_q_1 0x20000000L + +// MH_DEBUG_REG54 +#define MH_DEBUG_REG54__TAG2_VA_MASK 0x00001fffL +#define MH_DEBUG_REG54__TAG_valid_q_2_MASK 0x00002000L +#define MH_DEBUG_REG54__TAG_valid_q_2 0x00002000L +#define MH_DEBUG_REG54__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG54__TAG3_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG54__TAG_valid_q_3_MASK 0x20000000L +#define MH_DEBUG_REG54__TAG_valid_q_3 0x20000000L + +// MH_DEBUG_REG55 +#define MH_DEBUG_REG55__TAG4_VA_MASK 0x00001fffL +#define MH_DEBUG_REG55__TAG_valid_q_4_MASK 0x00002000L +#define MH_DEBUG_REG55__TAG_valid_q_4 0x00002000L +#define MH_DEBUG_REG55__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG55__TAG5_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG55__TAG_valid_q_5_MASK 0x20000000L +#define MH_DEBUG_REG55__TAG_valid_q_5 0x20000000L + +// MH_DEBUG_REG56 +#define MH_DEBUG_REG56__TAG6_VA_MASK 0x00001fffL +#define MH_DEBUG_REG56__TAG_valid_q_6_MASK 0x00002000L +#define MH_DEBUG_REG56__TAG_valid_q_6 0x00002000L +#define MH_DEBUG_REG56__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG56__TAG7_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG56__TAG_valid_q_7_MASK 0x20000000L +#define MH_DEBUG_REG56__TAG_valid_q_7 0x20000000L + +// MH_DEBUG_REG57 +#define MH_DEBUG_REG57__TAG8_VA_MASK 0x00001fffL +#define MH_DEBUG_REG57__TAG_valid_q_8_MASK 0x00002000L +#define MH_DEBUG_REG57__TAG_valid_q_8 0x00002000L +#define MH_DEBUG_REG57__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG57__TAG9_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG57__TAG_valid_q_9_MASK 0x20000000L +#define MH_DEBUG_REG57__TAG_valid_q_9 0x20000000L + +// MH_DEBUG_REG58 +#define MH_DEBUG_REG58__TAG10_VA_MASK 0x00001fffL +#define MH_DEBUG_REG58__TAG_valid_q_10_MASK 0x00002000L +#define MH_DEBUG_REG58__TAG_valid_q_10 0x00002000L +#define MH_DEBUG_REG58__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG58__TAG11_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG58__TAG_valid_q_11_MASK 0x20000000L +#define MH_DEBUG_REG58__TAG_valid_q_11 0x20000000L + +// MH_DEBUG_REG59 +#define MH_DEBUG_REG59__TAG12_VA_MASK 0x00001fffL +#define MH_DEBUG_REG59__TAG_valid_q_12_MASK 0x00002000L +#define MH_DEBUG_REG59__TAG_valid_q_12 0x00002000L +#define MH_DEBUG_REG59__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG59__TAG13_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG59__TAG_valid_q_13_MASK 0x20000000L +#define MH_DEBUG_REG59__TAG_valid_q_13 0x20000000L + +// MH_DEBUG_REG60 +#define MH_DEBUG_REG60__TAG14_VA_MASK 0x00001fffL +#define MH_DEBUG_REG60__TAG_valid_q_14_MASK 0x00002000L +#define MH_DEBUG_REG60__TAG_valid_q_14 0x00002000L +#define MH_DEBUG_REG60__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG60__TAG15_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG60__TAG_valid_q_15_MASK 0x20000000L +#define MH_DEBUG_REG60__TAG_valid_q_15 0x20000000L + +// MH_DEBUG_REG61 +#define MH_DEBUG_REG61__MH_DBG_DEFAULT_MASK 0xffffffffL + +// MH_DEBUG_REG62 +#define MH_DEBUG_REG62__MH_DBG_DEFAULT_MASK 0xffffffffL + +// MH_DEBUG_REG63 +#define MH_DEBUG_REG63__MH_DBG_DEFAULT_MASK 0xffffffffL + +// MH_MMU_CONFIG +#define MH_MMU_CONFIG__MMU_ENABLE_MASK 0x00000001L +#define MH_MMU_CONFIG__MMU_ENABLE 0x00000001L +#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE_MASK 0x00000002L +#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE 0x00000002L +#define MH_MMU_CONFIG__RESERVED1_MASK 0x0000000cL +#define MH_MMU_CONFIG__RB_W_CLNT_BEHAVIOR_MASK 0x00000030L +#define MH_MMU_CONFIG__CP_W_CLNT_BEHAVIOR_MASK 0x000000c0L +#define MH_MMU_CONFIG__CP_R0_CLNT_BEHAVIOR_MASK 0x00000300L +#define MH_MMU_CONFIG__CP_R1_CLNT_BEHAVIOR_MASK 0x00000c00L +#define MH_MMU_CONFIG__CP_R2_CLNT_BEHAVIOR_MASK 0x00003000L +#define MH_MMU_CONFIG__CP_R3_CLNT_BEHAVIOR_MASK 0x0000c000L +#define MH_MMU_CONFIG__CP_R4_CLNT_BEHAVIOR_MASK 0x00030000L +#define MH_MMU_CONFIG__VGT_R0_CLNT_BEHAVIOR_MASK 0x000c0000L +#define MH_MMU_CONFIG__VGT_R1_CLNT_BEHAVIOR_MASK 0x00300000L +#define MH_MMU_CONFIG__TC_R_CLNT_BEHAVIOR_MASK 0x00c00000L + +// MH_MMU_VA_RANGE +#define MH_MMU_VA_RANGE__NUM_64KB_REGIONS_MASK 0x00000fffL +#define MH_MMU_VA_RANGE__VA_BASE_MASK 0xfffff000L + +// MH_MMU_PT_BASE +#define MH_MMU_PT_BASE__PT_BASE_MASK 0xfffff000L + +// MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT__PAGE_FAULT_MASK 0x00000001L +#define MH_MMU_PAGE_FAULT__PAGE_FAULT 0x00000001L +#define MH_MMU_PAGE_FAULT__OP_TYPE_MASK 0x00000002L +#define MH_MMU_PAGE_FAULT__OP_TYPE 0x00000002L +#define MH_MMU_PAGE_FAULT__CLNT_BEHAVIOR_MASK 0x0000000cL +#define MH_MMU_PAGE_FAULT__AXI_ID_MASK 0x00000070L +#define MH_MMU_PAGE_FAULT__RESERVED1_MASK 0x00000080L +#define MH_MMU_PAGE_FAULT__RESERVED1 0x00000080L +#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE_MASK 0x00000100L +#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE 0x00000100L +#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE_MASK 0x00000200L +#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE 0x00000200L +#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR_MASK 0x00000400L +#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR 0x00000400L +#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR_MASK 0x00000800L +#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR 0x00000800L +#define MH_MMU_PAGE_FAULT__REQ_VA_MASK 0xfffff000L + +// MH_MMU_TRAN_ERROR +#define MH_MMU_TRAN_ERROR__TRAN_ERROR_MASK 0xffffffe0L + +// MH_MMU_INVALIDATE +#define MH_MMU_INVALIDATE__INVALIDATE_ALL_MASK 0x00000001L +#define MH_MMU_INVALIDATE__INVALIDATE_ALL 0x00000001L +#define MH_MMU_INVALIDATE__INVALIDATE_TC_MASK 0x00000002L +#define MH_MMU_INVALIDATE__INVALIDATE_TC 0x00000002L + +// MH_MMU_MPU_BASE +#define MH_MMU_MPU_BASE__MPU_BASE_MASK 0xfffff000L + +// MH_MMU_MPU_END +#define MH_MMU_MPU_END__MPU_END_MASK 0xfffff000L + +// WAIT_UNTIL +#define WAIT_UNTIL__WAIT_RE_VSYNC_MASK 0x00000002L +#define WAIT_UNTIL__WAIT_RE_VSYNC 0x00000002L +#define WAIT_UNTIL__WAIT_FE_VSYNC_MASK 0x00000004L +#define WAIT_UNTIL__WAIT_FE_VSYNC 0x00000004L +#define WAIT_UNTIL__WAIT_VSYNC_MASK 0x00000008L +#define WAIT_UNTIL__WAIT_VSYNC 0x00000008L +#define WAIT_UNTIL__WAIT_DSPLY_ID0_MASK 0x00000010L +#define WAIT_UNTIL__WAIT_DSPLY_ID0 0x00000010L +#define WAIT_UNTIL__WAIT_DSPLY_ID1_MASK 0x00000020L +#define WAIT_UNTIL__WAIT_DSPLY_ID1 0x00000020L +#define WAIT_UNTIL__WAIT_DSPLY_ID2_MASK 0x00000040L +#define WAIT_UNTIL__WAIT_DSPLY_ID2 0x00000040L +#define WAIT_UNTIL__WAIT_CMDFIFO_MASK 0x00000400L +#define WAIT_UNTIL__WAIT_CMDFIFO 0x00000400L +#define WAIT_UNTIL__WAIT_2D_IDLE_MASK 0x00004000L +#define WAIT_UNTIL__WAIT_2D_IDLE 0x00004000L +#define WAIT_UNTIL__WAIT_3D_IDLE_MASK 0x00008000L +#define WAIT_UNTIL__WAIT_3D_IDLE 0x00008000L +#define WAIT_UNTIL__WAIT_2D_IDLECLEAN_MASK 0x00010000L +#define WAIT_UNTIL__WAIT_2D_IDLECLEAN 0x00010000L +#define WAIT_UNTIL__WAIT_3D_IDLECLEAN_MASK 0x00020000L +#define WAIT_UNTIL__WAIT_3D_IDLECLEAN 0x00020000L +#define WAIT_UNTIL__CMDFIFO_ENTRIES_MASK 0x00f00000L + +// RBBM_ISYNC_CNTL +#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI_MASK 0x00000010L +#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI 0x00000010L +#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI_MASK 0x00000020L +#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI 0x00000020L + +// RBBM_STATUS +#define RBBM_STATUS__CMDFIFO_AVAIL_MASK 0x0000001fL +#define RBBM_STATUS__TC_BUSY_MASK 0x00000020L +#define RBBM_STATUS__TC_BUSY 0x00000020L +#define RBBM_STATUS__HIRQ_PENDING_MASK 0x00000100L +#define RBBM_STATUS__HIRQ_PENDING 0x00000100L +#define RBBM_STATUS__CPRQ_PENDING_MASK 0x00000200L +#define RBBM_STATUS__CPRQ_PENDING 0x00000200L +#define RBBM_STATUS__CFRQ_PENDING_MASK 0x00000400L +#define RBBM_STATUS__CFRQ_PENDING 0x00000400L +#define RBBM_STATUS__PFRQ_PENDING_MASK 0x00000800L +#define RBBM_STATUS__PFRQ_PENDING 0x00000800L +#define RBBM_STATUS__VGT_BUSY_NO_DMA_MASK 0x00001000L +#define RBBM_STATUS__VGT_BUSY_NO_DMA 0x00001000L +#define RBBM_STATUS__RBBM_WU_BUSY_MASK 0x00004000L +#define RBBM_STATUS__RBBM_WU_BUSY 0x00004000L +#define RBBM_STATUS__CP_NRT_BUSY_MASK 0x00010000L +#define RBBM_STATUS__CP_NRT_BUSY 0x00010000L +#define RBBM_STATUS__MH_BUSY_MASK 0x00040000L +#define RBBM_STATUS__MH_BUSY 0x00040000L +#define RBBM_STATUS__MH_COHERENCY_BUSY_MASK 0x00080000L +#define RBBM_STATUS__MH_COHERENCY_BUSY 0x00080000L +#define RBBM_STATUS__SX_BUSY_MASK 0x00200000L +#define RBBM_STATUS__SX_BUSY 0x00200000L +#define RBBM_STATUS__TPC_BUSY_MASK 0x00400000L +#define RBBM_STATUS__TPC_BUSY 0x00400000L +#define RBBM_STATUS__SC_CNTX_BUSY_MASK 0x01000000L +#define RBBM_STATUS__SC_CNTX_BUSY 0x01000000L +#define RBBM_STATUS__PA_BUSY_MASK 0x02000000L +#define RBBM_STATUS__PA_BUSY 0x02000000L +#define RBBM_STATUS__VGT_BUSY_MASK 0x04000000L +#define RBBM_STATUS__VGT_BUSY 0x04000000L +#define RBBM_STATUS__SQ_CNTX17_BUSY_MASK 0x08000000L +#define RBBM_STATUS__SQ_CNTX17_BUSY 0x08000000L +#define RBBM_STATUS__SQ_CNTX0_BUSY_MASK 0x10000000L +#define RBBM_STATUS__SQ_CNTX0_BUSY 0x10000000L +#define RBBM_STATUS__RB_CNTX_BUSY_MASK 0x40000000L +#define RBBM_STATUS__RB_CNTX_BUSY 0x40000000L +#define RBBM_STATUS__GUI_ACTIVE_MASK 0x80000000L +#define RBBM_STATUS__GUI_ACTIVE 0x80000000L + +// RBBM_DSPLY +#define RBBM_DSPLY__DISPLAY_ID0_ACTIVE_MASK 0x00000001L +#define RBBM_DSPLY__DISPLAY_ID0_ACTIVE 0x00000001L +#define RBBM_DSPLY__DISPLAY_ID1_ACTIVE_MASK 0x00000002L +#define RBBM_DSPLY__DISPLAY_ID1_ACTIVE 0x00000002L +#define RBBM_DSPLY__DISPLAY_ID2_ACTIVE_MASK 0x00000004L +#define RBBM_DSPLY__DISPLAY_ID2_ACTIVE 0x00000004L +#define RBBM_DSPLY__VSYNC_ACTIVE_MASK 0x00000008L +#define RBBM_DSPLY__VSYNC_ACTIVE 0x00000008L +#define RBBM_DSPLY__USE_DISPLAY_ID0_MASK 0x00000010L +#define RBBM_DSPLY__USE_DISPLAY_ID0 0x00000010L +#define RBBM_DSPLY__USE_DISPLAY_ID1_MASK 0x00000020L +#define RBBM_DSPLY__USE_DISPLAY_ID1 0x00000020L +#define RBBM_DSPLY__USE_DISPLAY_ID2_MASK 0x00000040L +#define RBBM_DSPLY__USE_DISPLAY_ID2 0x00000040L +#define RBBM_DSPLY__SW_CNTL_MASK 0x00000080L +#define RBBM_DSPLY__SW_CNTL 0x00000080L +#define RBBM_DSPLY__NUM_BUFS_MASK 0x00000300L + +// RBBM_RENDER_LATEST +#define RBBM_RENDER_LATEST__BUFFER_ID_MASK 0x00000003L + +// RBBM_RTL_RELEASE +#define RBBM_RTL_RELEASE__CHANGELIST_MASK 0xffffffffL + +// RBBM_PATCH_RELEASE +#define RBBM_PATCH_RELEASE__PATCH_REVISION_MASK 0x0000ffffL +#define RBBM_PATCH_RELEASE__PATCH_SELECTION_MASK 0x00ff0000L +#define RBBM_PATCH_RELEASE__CUSTOMER_ID_MASK 0xff000000L + +// RBBM_AUXILIARY_CONFIG +#define RBBM_AUXILIARY_CONFIG__RESERVED_MASK 0xffffffffL + +// RBBM_PERIPHID0 +#define RBBM_PERIPHID0__PARTNUMBER0_MASK 0x000000ffL + +// RBBM_PERIPHID1 +#define RBBM_PERIPHID1__PARTNUMBER1_MASK 0x0000000fL +#define RBBM_PERIPHID1__DESIGNER0_MASK 0x000000f0L + +// RBBM_PERIPHID2 +#define RBBM_PERIPHID2__DESIGNER1_MASK 0x0000000fL +#define RBBM_PERIPHID2__REVISION_MASK 0x000000f0L + +// RBBM_PERIPHID3 +#define RBBM_PERIPHID3__RBBM_HOST_INTERFACE_MASK 0x00000003L +#define RBBM_PERIPHID3__GARB_SLAVE_INTERFACE_MASK 0x0000000cL +#define RBBM_PERIPHID3__MH_INTERFACE_MASK 0x00000030L +#define RBBM_PERIPHID3__CONTINUATION_MASK 0x00000080L +#define RBBM_PERIPHID3__CONTINUATION 0x00000080L + +// RBBM_CNTL +#define RBBM_CNTL__READ_TIMEOUT_MASK 0x000000ffL +#define RBBM_CNTL__REGCLK_DEASSERT_TIME_MASK 0x0001ff00L + +// RBBM_SKEW_CNTL +#define RBBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x0000001fL +#define RBBM_SKEW_CNTL__SKEW_COUNT_MASK 0x000003e0L + +// RBBM_SOFT_RESET +#define RBBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L +#define RBBM_SOFT_RESET__SOFT_RESET_CP 0x00000001L +#define RBBM_SOFT_RESET__SOFT_RESET_PA_MASK 0x00000004L +#define RBBM_SOFT_RESET__SOFT_RESET_PA 0x00000004L +#define RBBM_SOFT_RESET__SOFT_RESET_MH_MASK 0x00000008L +#define RBBM_SOFT_RESET__SOFT_RESET_MH 0x00000008L +#define RBBM_SOFT_RESET__SOFT_RESET_BC_MASK 0x00000010L +#define RBBM_SOFT_RESET__SOFT_RESET_BC 0x00000010L +#define RBBM_SOFT_RESET__SOFT_RESET_SQ_MASK 0x00000020L +#define RBBM_SOFT_RESET__SOFT_RESET_SQ 0x00000020L +#define RBBM_SOFT_RESET__SOFT_RESET_SX_MASK 0x00000040L +#define RBBM_SOFT_RESET__SOFT_RESET_SX 0x00000040L +#define RBBM_SOFT_RESET__SOFT_RESET_CIB_MASK 0x00001000L +#define RBBM_SOFT_RESET__SOFT_RESET_CIB 0x00001000L +#define RBBM_SOFT_RESET__SOFT_RESET_SC_MASK 0x00008000L +#define RBBM_SOFT_RESET__SOFT_RESET_SC 0x00008000L +#define RBBM_SOFT_RESET__SOFT_RESET_VGT_MASK 0x00010000L +#define RBBM_SOFT_RESET__SOFT_RESET_VGT 0x00010000L + +// RBBM_PM_OVERRIDE1 +#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE_MASK 0x00000001L +#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE 0x00000001L +#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE_MASK 0x00000002L +#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE 0x00000002L +#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE_MASK 0x00000004L +#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE 0x00000004L +#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE_MASK 0x00000008L +#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE 0x00000008L +#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE_MASK 0x00000010L +#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE 0x00000010L +#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE_MASK 0x00000020L +#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE 0x00000020L +#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000040L +#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE 0x00000040L +#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK 0x00000080L +#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE 0x00000080L +#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE_MASK 0x00000100L +#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE 0x00000100L +#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE_MASK 0x00000200L +#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE 0x00000200L +#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE_MASK 0x00000400L +#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE 0x00000400L +#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE_MASK 0x00000800L +#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE 0x00000800L +#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE_MASK 0x00001000L +#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE 0x00001000L +#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE_MASK 0x00002000L +#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE 0x00002000L +#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE_MASK 0x00004000L +#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE 0x00004000L +#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE_MASK 0x00008000L +#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE 0x00008000L +#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE_MASK 0x00010000L +#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE 0x00010000L +#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE_MASK 0x00020000L +#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE 0x00020000L +#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE_MASK 0x00040000L +#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE 0x00040000L +#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK 0x00080000L +#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE 0x00080000L +#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE_MASK 0x00100000L +#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE 0x00100000L +#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE_MASK 0x00200000L +#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE 0x00200000L +#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE_MASK 0x00400000L +#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE 0x00400000L +#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE_MASK 0x00800000L +#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE 0x00800000L +#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE_MASK 0x01000000L +#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE 0x01000000L +#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE_MASK 0x02000000L +#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE 0x02000000L +#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE_MASK 0x04000000L +#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE 0x04000000L +#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE_MASK 0x08000000L +#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE 0x08000000L +#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE_MASK 0x10000000L +#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE 0x10000000L +#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE_MASK 0x20000000L +#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE 0x20000000L +#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE_MASK 0x40000000L +#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE 0x40000000L +#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE_MASK 0x80000000L +#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE 0x80000000L + +// RBBM_PM_OVERRIDE2 +#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE_MASK 0x00000001L +#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE 0x00000001L +#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE_MASK 0x00000002L +#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE 0x00000002L +#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE_MASK 0x00000004L +#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE 0x00000004L +#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE_MASK 0x00000008L +#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE 0x00000008L +#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000010L +#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE 0x00000010L +#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE_MASK 0x00000020L +#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE 0x00000020L +#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE_MASK 0x00000040L +#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE 0x00000040L +#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE_MASK 0x00000080L +#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE 0x00000080L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE_MASK 0x00000100L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE 0x00000100L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE_MASK 0x00000200L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE 0x00000200L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE_MASK 0x00000400L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE 0x00000400L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE_MASK 0x00000800L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE 0x00000800L + +// GC_SYS_IDLE +#define GC_SYS_IDLE__GC_SYS_IDLE_DELAY_MASK 0x0000ffffL +#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE_MASK 0x80000000L +#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE 0x80000000L + +// NQWAIT_UNTIL +#define NQWAIT_UNTIL__WAIT_GUI_IDLE_MASK 0x00000001L +#define NQWAIT_UNTIL__WAIT_GUI_IDLE 0x00000001L + +// RBBM_DEBUG +#define RBBM_DEBUG__IGNORE_RTR_MASK 0x00000002L +#define RBBM_DEBUG__IGNORE_RTR 0x00000002L +#define RBBM_DEBUG__IGNORE_CP_SCHED_WU_MASK 0x00000004L +#define RBBM_DEBUG__IGNORE_CP_SCHED_WU 0x00000004L +#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC_MASK 0x00000008L +#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC 0x00000008L +#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI_MASK 0x00000010L +#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI 0x00000010L +#define RBBM_DEBUG__HYSTERESIS_NRT_GUI_ACTIVE_MASK 0x00000f00L +#define RBBM_DEBUG__IGNORE_RTR_FOR_HI_MASK 0x00010000L +#define RBBM_DEBUG__IGNORE_RTR_FOR_HI 0x00010000L +#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK 0x00020000L +#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI 0x00020000L +#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK 0x00040000L +#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI 0x00040000L +#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK 0x00080000L +#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI 0x00080000L +#define RBBM_DEBUG__CP_RBBM_NRTRTR_MASK 0x00100000L +#define RBBM_DEBUG__CP_RBBM_NRTRTR 0x00100000L +#define RBBM_DEBUG__VGT_RBBM_NRTRTR_MASK 0x00200000L +#define RBBM_DEBUG__VGT_RBBM_NRTRTR 0x00200000L +#define RBBM_DEBUG__SQ_RBBM_NRTRTR_MASK 0x00400000L +#define RBBM_DEBUG__SQ_RBBM_NRTRTR 0x00400000L +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI_MASK 0x00800000L +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI 0x00800000L +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_MASK 0x01000000L +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR 0x01000000L +#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY_MASK 0x80000000L +#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY 0x80000000L + +// RBBM_READ_ERROR +#define RBBM_READ_ERROR__READ_ADDRESS_MASK 0x0001fffcL +#define RBBM_READ_ERROR__READ_REQUESTER_MASK 0x40000000L +#define RBBM_READ_ERROR__READ_REQUESTER 0x40000000L +#define RBBM_READ_ERROR__READ_ERROR_MASK 0x80000000L +#define RBBM_READ_ERROR__READ_ERROR 0x80000000L + +// RBBM_WAIT_IDLE_CLOCKS +#define RBBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_NRT_MASK 0x000000ffL + +// RBBM_INT_CNTL +#define RBBM_INT_CNTL__RDERR_INT_MASK_MASK 0x00000001L +#define RBBM_INT_CNTL__RDERR_INT_MASK 0x00000001L +#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK_MASK 0x00000002L +#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK 0x00000002L +#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK_MASK 0x00080000L +#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK 0x00080000L + +// RBBM_INT_STATUS +#define RBBM_INT_STATUS__RDERR_INT_STAT_MASK 0x00000001L +#define RBBM_INT_STATUS__RDERR_INT_STAT 0x00000001L +#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT_MASK 0x00000002L +#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT 0x00000002L +#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT_MASK 0x00080000L +#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT 0x00080000L + +// RBBM_INT_ACK +#define RBBM_INT_ACK__RDERR_INT_ACK_MASK 0x00000001L +#define RBBM_INT_ACK__RDERR_INT_ACK 0x00000001L +#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK_MASK 0x00000002L +#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK 0x00000002L +#define RBBM_INT_ACK__GUI_IDLE_INT_ACK_MASK 0x00080000L +#define RBBM_INT_ACK__GUI_IDLE_INT_ACK 0x00080000L + +// MASTER_INT_SIGNAL +#define MASTER_INT_SIGNAL__MH_INT_STAT_MASK 0x00000020L +#define MASTER_INT_SIGNAL__MH_INT_STAT 0x00000020L +#define MASTER_INT_SIGNAL__CP_INT_STAT_MASK 0x40000000L +#define MASTER_INT_SIGNAL__CP_INT_STAT 0x40000000L +#define MASTER_INT_SIGNAL__RBBM_INT_STAT_MASK 0x80000000L +#define MASTER_INT_SIGNAL__RBBM_INT_STAT 0x80000000L + +// RBBM_PERFCOUNTER1_SELECT +#define RBBM_PERFCOUNTER1_SELECT__PERF_COUNT1_SEL_MASK 0x0000003fL + +// RBBM_PERFCOUNTER1_LO +#define RBBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK 0xffffffffL + +// RBBM_PERFCOUNTER1_HI +#define RBBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK 0x0000ffffL + +// CP_RB_BASE +#define CP_RB_BASE__RB_BASE_MASK 0xffffffe0L + +// CP_RB_CNTL +#define CP_RB_CNTL__RB_BUFSZ_MASK 0x0000003fL +#define CP_RB_CNTL__RB_BLKSZ_MASK 0x00003f00L +#define CP_RB_CNTL__BUF_SWAP_MASK 0x00030000L +#define CP_RB_CNTL__RB_POLL_EN_MASK 0x00100000L +#define CP_RB_CNTL__RB_POLL_EN 0x00100000L +#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x08000000L +#define CP_RB_CNTL__RB_NO_UPDATE 0x08000000L +#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L +#define CP_RB_CNTL__RB_RPTR_WR_ENA 0x80000000L + +// CP_RB_RPTR_ADDR +#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x00000003L +#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffcL + +// CP_RB_RPTR +#define CP_RB_RPTR__RB_RPTR_MASK 0x000fffffL + +// CP_RB_RPTR_WR +#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0x000fffffL + +// CP_RB_WPTR +#define CP_RB_WPTR__RB_WPTR_MASK 0x000fffffL + +// CP_RB_WPTR_DELAY +#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0x0fffffffL +#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xf0000000L + +// CP_RB_WPTR_BASE +#define CP_RB_WPTR_BASE__RB_WPTR_SWAP_MASK 0x00000003L +#define CP_RB_WPTR_BASE__RB_WPTR_BASE_MASK 0xfffffffcL + +// CP_IB1_BASE +#define CP_IB1_BASE__IB1_BASE_MASK 0xfffffffcL + +// CP_IB1_BUFSZ +#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000fffffL + +// CP_IB2_BASE +#define CP_IB2_BASE__IB2_BASE_MASK 0xfffffffcL + +// CP_IB2_BUFSZ +#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000fffffL + +// CP_ST_BASE +#define CP_ST_BASE__ST_BASE_MASK 0xfffffffcL + +// CP_ST_BUFSZ +#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0x000fffffL + +// CP_QUEUE_THRESHOLDS +#define CP_QUEUE_THRESHOLDS__CSQ_IB1_START_MASK 0x0000000fL +#define CP_QUEUE_THRESHOLDS__CSQ_IB2_START_MASK 0x00000f00L +#define CP_QUEUE_THRESHOLDS__CSQ_ST_START_MASK 0x000f0000L + +// CP_MEQ_THRESHOLDS +#define CP_MEQ_THRESHOLDS__MEQ_END_MASK 0x001f0000L +#define CP_MEQ_THRESHOLDS__ROQ_END_MASK 0x1f000000L + +// CP_CSQ_AVAIL +#define CP_CSQ_AVAIL__CSQ_CNT_RING_MASK 0x0000007fL +#define CP_CSQ_AVAIL__CSQ_CNT_IB1_MASK 0x00007f00L +#define CP_CSQ_AVAIL__CSQ_CNT_IB2_MASK 0x007f0000L + +// CP_STQ_AVAIL +#define CP_STQ_AVAIL__STQ_CNT_ST_MASK 0x0000007fL + +// CP_MEQ_AVAIL +#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x0000001fL + +// CP_CSQ_RB_STAT +#define CP_CSQ_RB_STAT__CSQ_RPTR_PRIMARY_MASK 0x0000007fL +#define CP_CSQ_RB_STAT__CSQ_WPTR_PRIMARY_MASK 0x007f0000L + +// CP_CSQ_IB1_STAT +#define CP_CSQ_IB1_STAT__CSQ_RPTR_INDIRECT1_MASK 0x0000007fL +#define CP_CSQ_IB1_STAT__CSQ_WPTR_INDIRECT1_MASK 0x007f0000L + +// CP_CSQ_IB2_STAT +#define CP_CSQ_IB2_STAT__CSQ_RPTR_INDIRECT2_MASK 0x0000007fL +#define CP_CSQ_IB2_STAT__CSQ_WPTR_INDIRECT2_MASK 0x007f0000L + +// CP_NON_PREFETCH_CNTRS +#define CP_NON_PREFETCH_CNTRS__IB1_COUNTER_MASK 0x00000007L +#define CP_NON_PREFETCH_CNTRS__IB2_COUNTER_MASK 0x00000700L + +// CP_STQ_ST_STAT +#define CP_STQ_ST_STAT__STQ_RPTR_ST_MASK 0x0000007fL +#define CP_STQ_ST_STAT__STQ_WPTR_ST_MASK 0x007f0000L + +// CP_MEQ_STAT +#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x000003ffL +#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x03ff0000L + +// CP_MIU_TAG_STAT +#define CP_MIU_TAG_STAT__TAG_0_STAT_MASK 0x00000001L +#define CP_MIU_TAG_STAT__TAG_0_STAT 0x00000001L +#define CP_MIU_TAG_STAT__TAG_1_STAT_MASK 0x00000002L +#define CP_MIU_TAG_STAT__TAG_1_STAT 0x00000002L +#define CP_MIU_TAG_STAT__TAG_2_STAT_MASK 0x00000004L +#define CP_MIU_TAG_STAT__TAG_2_STAT 0x00000004L +#define CP_MIU_TAG_STAT__TAG_3_STAT_MASK 0x00000008L +#define CP_MIU_TAG_STAT__TAG_3_STAT 0x00000008L +#define CP_MIU_TAG_STAT__TAG_4_STAT_MASK 0x00000010L +#define CP_MIU_TAG_STAT__TAG_4_STAT 0x00000010L +#define CP_MIU_TAG_STAT__TAG_5_STAT_MASK 0x00000020L +#define CP_MIU_TAG_STAT__TAG_5_STAT 0x00000020L +#define CP_MIU_TAG_STAT__TAG_6_STAT_MASK 0x00000040L +#define CP_MIU_TAG_STAT__TAG_6_STAT 0x00000040L +#define CP_MIU_TAG_STAT__TAG_7_STAT_MASK 0x00000080L +#define CP_MIU_TAG_STAT__TAG_7_STAT 0x00000080L +#define CP_MIU_TAG_STAT__TAG_8_STAT_MASK 0x00000100L +#define CP_MIU_TAG_STAT__TAG_8_STAT 0x00000100L +#define CP_MIU_TAG_STAT__TAG_9_STAT_MASK 0x00000200L +#define CP_MIU_TAG_STAT__TAG_9_STAT 0x00000200L +#define CP_MIU_TAG_STAT__TAG_10_STAT_MASK 0x00000400L +#define CP_MIU_TAG_STAT__TAG_10_STAT 0x00000400L +#define CP_MIU_TAG_STAT__TAG_11_STAT_MASK 0x00000800L +#define CP_MIU_TAG_STAT__TAG_11_STAT 0x00000800L +#define CP_MIU_TAG_STAT__TAG_12_STAT_MASK 0x00001000L +#define CP_MIU_TAG_STAT__TAG_12_STAT 0x00001000L +#define CP_MIU_TAG_STAT__TAG_13_STAT_MASK 0x00002000L +#define CP_MIU_TAG_STAT__TAG_13_STAT 0x00002000L +#define CP_MIU_TAG_STAT__TAG_14_STAT_MASK 0x00004000L +#define CP_MIU_TAG_STAT__TAG_14_STAT 0x00004000L +#define CP_MIU_TAG_STAT__TAG_15_STAT_MASK 0x00008000L +#define CP_MIU_TAG_STAT__TAG_15_STAT 0x00008000L +#define CP_MIU_TAG_STAT__TAG_16_STAT_MASK 0x00010000L +#define CP_MIU_TAG_STAT__TAG_16_STAT 0x00010000L +#define CP_MIU_TAG_STAT__TAG_17_STAT_MASK 0x00020000L +#define CP_MIU_TAG_STAT__TAG_17_STAT 0x00020000L +#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG_MASK 0x80000000L +#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG 0x80000000L + +// CP_CMD_INDEX +#define CP_CMD_INDEX__CMD_INDEX_MASK 0x0000007fL +#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x00030000L + +// CP_CMD_DATA +#define CP_CMD_DATA__CMD_DATA_MASK 0xffffffffL + +// CP_ME_CNTL +#define CP_ME_CNTL__ME_STATMUX_MASK 0x0000ffffL +#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY_MASK 0x02000000L +#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY 0x02000000L +#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY_MASK 0x04000000L +#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY 0x04000000L +#define CP_ME_CNTL__ME_HALT_MASK 0x10000000L +#define CP_ME_CNTL__ME_HALT 0x10000000L +#define CP_ME_CNTL__ME_BUSY_MASK 0x20000000L +#define CP_ME_CNTL__ME_BUSY 0x20000000L +#define CP_ME_CNTL__PROG_CNT_SIZE_MASK 0x80000000L +#define CP_ME_CNTL__PROG_CNT_SIZE 0x80000000L + +// CP_ME_STATUS +#define CP_ME_STATUS__ME_DEBUG_DATA_MASK 0xffffffffL + +// CP_ME_RAM_WADDR +#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x000003ffL + +// CP_ME_RAM_RADDR +#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x000003ffL + +// CP_ME_RAM_DATA +#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xffffffffL + +// CP_ME_RDADDR +#define CP_ME_RDADDR__ME_RDADDR_MASK 0xffffffffL + +// CP_DEBUG +#define CP_DEBUG__CP_DEBUG_UNUSED_22_to_0_MASK 0x007fffffL +#define CP_DEBUG__PREDICATE_DISABLE_MASK 0x00800000L +#define CP_DEBUG__PREDICATE_DISABLE 0x00800000L +#define CP_DEBUG__PROG_END_PTR_ENABLE_MASK 0x01000000L +#define CP_DEBUG__PROG_END_PTR_ENABLE 0x01000000L +#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE_MASK 0x02000000L +#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE 0x02000000L +#define CP_DEBUG__PREFETCH_PASS_NOPS_MASK 0x04000000L +#define CP_DEBUG__PREFETCH_PASS_NOPS 0x04000000L +#define CP_DEBUG__DYNAMIC_CLK_DISABLE_MASK 0x08000000L +#define CP_DEBUG__DYNAMIC_CLK_DISABLE 0x08000000L +#define CP_DEBUG__PREFETCH_MATCH_DISABLE_MASK 0x10000000L +#define CP_DEBUG__PREFETCH_MATCH_DISABLE 0x10000000L +#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL_MASK 0x40000000L +#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL 0x40000000L +#define CP_DEBUG__MIU_WRITE_PACK_DISABLE_MASK 0x80000000L +#define CP_DEBUG__MIU_WRITE_PACK_DISABLE 0x80000000L + +// SCRATCH_REG0 +#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffffL +#define GUI_SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffffL + +// SCRATCH_REG1 +#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffffL +#define GUI_SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffffL + +// SCRATCH_REG2 +#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffffL +#define GUI_SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffffL + +// SCRATCH_REG3 +#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffffL +#define GUI_SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffffL + +// SCRATCH_REG4 +#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffffL +#define GUI_SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffffL + +// SCRATCH_REG5 +#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffffL +#define GUI_SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffffL + +// SCRATCH_REG6 +#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffffL +#define GUI_SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffffL + +// SCRATCH_REG7 +#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffffL +#define GUI_SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffffL + +// SCRATCH_UMSK +#define SCRATCH_UMSK__SCRATCH_UMSK_MASK 0x000000ffL +#define SCRATCH_UMSK__SCRATCH_SWAP_MASK 0x00030000L + +// SCRATCH_ADDR +#define SCRATCH_ADDR__SCRATCH_ADDR_MASK 0xffffffe0L + +// CP_ME_VS_EVENT_SRC +#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM_MASK 0x00000001L +#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM 0x00000001L +#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR_MASK 0x00000002L +#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR 0x00000002L + +// CP_ME_VS_EVENT_ADDR +#define CP_ME_VS_EVENT_ADDR__VS_DONE_SWAP_MASK 0x00000003L +#define CP_ME_VS_EVENT_ADDR__VS_DONE_ADDR_MASK 0xfffffffcL + +// CP_ME_VS_EVENT_DATA +#define CP_ME_VS_EVENT_DATA__VS_DONE_DATA_MASK 0xffffffffL + +// CP_ME_VS_EVENT_ADDR_SWM +#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_SWAP_SWM_MASK 0x00000003L +#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_ADDR_SWM_MASK 0xfffffffcL + +// CP_ME_VS_EVENT_DATA_SWM +#define CP_ME_VS_EVENT_DATA_SWM__VS_DONE_DATA_SWM_MASK 0xffffffffL + +// CP_ME_PS_EVENT_SRC +#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM_MASK 0x00000001L +#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM 0x00000001L +#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR_MASK 0x00000002L +#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR 0x00000002L + +// CP_ME_PS_EVENT_ADDR +#define CP_ME_PS_EVENT_ADDR__PS_DONE_SWAP_MASK 0x00000003L +#define CP_ME_PS_EVENT_ADDR__PS_DONE_ADDR_MASK 0xfffffffcL + +// CP_ME_PS_EVENT_DATA +#define CP_ME_PS_EVENT_DATA__PS_DONE_DATA_MASK 0xffffffffL + +// CP_ME_PS_EVENT_ADDR_SWM +#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_SWAP_SWM_MASK 0x00000003L +#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_ADDR_SWM_MASK 0xfffffffcL + +// CP_ME_PS_EVENT_DATA_SWM +#define CP_ME_PS_EVENT_DATA_SWM__PS_DONE_DATA_SWM_MASK 0xffffffffL + +// CP_ME_CF_EVENT_SRC +#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC_MASK 0x00000001L +#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC 0x00000001L + +// CP_ME_CF_EVENT_ADDR +#define CP_ME_CF_EVENT_ADDR__CF_DONE_SWAP_MASK 0x00000003L +#define CP_ME_CF_EVENT_ADDR__CF_DONE_ADDR_MASK 0xfffffffcL + +// CP_ME_CF_EVENT_DATA +#define CP_ME_CF_EVENT_DATA__CF_DONE_DATA_MASK 0xffffffffL + +// CP_ME_NRT_ADDR +#define CP_ME_NRT_ADDR__NRT_WRITE_SWAP_MASK 0x00000003L +#define CP_ME_NRT_ADDR__NRT_WRITE_ADDR_MASK 0xfffffffcL + +// CP_ME_NRT_DATA +#define CP_ME_NRT_DATA__NRT_WRITE_DATA_MASK 0xffffffffL + +// CP_ME_VS_FETCH_DONE_SRC +#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR_MASK 0x00000001L +#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR 0x00000001L + +// CP_ME_VS_FETCH_DONE_ADDR +#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_SWAP_MASK 0x00000003L +#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_ADDR_MASK 0xfffffffcL + +// CP_ME_VS_FETCH_DONE_DATA +#define CP_ME_VS_FETCH_DONE_DATA__VS_FETCH_DONE_DATA_MASK 0xffffffffL + +// CP_INT_CNTL +#define CP_INT_CNTL__SW_INT_MASK_MASK 0x00080000L +#define CP_INT_CNTL__SW_INT_MASK 0x00080000L +#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK_MASK 0x00800000L +#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK 0x00800000L +#define CP_INT_CNTL__OPCODE_ERROR_MASK_MASK 0x01000000L +#define CP_INT_CNTL__OPCODE_ERROR_MASK 0x01000000L +#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK_MASK 0x02000000L +#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK 0x02000000L +#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK_MASK 0x04000000L +#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK 0x04000000L +#define CP_INT_CNTL__IB_ERROR_MASK_MASK 0x08000000L +#define CP_INT_CNTL__IB_ERROR_MASK 0x08000000L +#define CP_INT_CNTL__IB2_INT_MASK_MASK 0x20000000L +#define CP_INT_CNTL__IB2_INT_MASK 0x20000000L +#define CP_INT_CNTL__IB1_INT_MASK_MASK 0x40000000L +#define CP_INT_CNTL__IB1_INT_MASK 0x40000000L +#define CP_INT_CNTL__RB_INT_MASK_MASK 0x80000000L +#define CP_INT_CNTL__RB_INT_MASK 0x80000000L + +// CP_INT_STATUS +#define CP_INT_STATUS__SW_INT_STAT_MASK 0x00080000L +#define CP_INT_STATUS__SW_INT_STAT 0x00080000L +#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT_MASK 0x00800000L +#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT 0x00800000L +#define CP_INT_STATUS__OPCODE_ERROR_STAT_MASK 0x01000000L +#define CP_INT_STATUS__OPCODE_ERROR_STAT 0x01000000L +#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT_MASK 0x02000000L +#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT 0x02000000L +#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT_MASK 0x04000000L +#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT 0x04000000L +#define CP_INT_STATUS__IB_ERROR_STAT_MASK 0x08000000L +#define CP_INT_STATUS__IB_ERROR_STAT 0x08000000L +#define CP_INT_STATUS__IB2_INT_STAT_MASK 0x20000000L +#define CP_INT_STATUS__IB2_INT_STAT 0x20000000L +#define CP_INT_STATUS__IB1_INT_STAT_MASK 0x40000000L +#define CP_INT_STATUS__IB1_INT_STAT 0x40000000L +#define CP_INT_STATUS__RB_INT_STAT_MASK 0x80000000L +#define CP_INT_STATUS__RB_INT_STAT 0x80000000L + +// CP_INT_ACK +#define CP_INT_ACK__SW_INT_ACK_MASK 0x00080000L +#define CP_INT_ACK__SW_INT_ACK 0x00080000L +#define CP_INT_ACK__T0_PACKET_IN_IB_ACK_MASK 0x00800000L +#define CP_INT_ACK__T0_PACKET_IN_IB_ACK 0x00800000L +#define CP_INT_ACK__OPCODE_ERROR_ACK_MASK 0x01000000L +#define CP_INT_ACK__OPCODE_ERROR_ACK 0x01000000L +#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK_MASK 0x02000000L +#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK 0x02000000L +#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK_MASK 0x04000000L +#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK 0x04000000L +#define CP_INT_ACK__IB_ERROR_ACK_MASK 0x08000000L +#define CP_INT_ACK__IB_ERROR_ACK 0x08000000L +#define CP_INT_ACK__IB2_INT_ACK_MASK 0x20000000L +#define CP_INT_ACK__IB2_INT_ACK 0x20000000L +#define CP_INT_ACK__IB1_INT_ACK_MASK 0x40000000L +#define CP_INT_ACK__IB1_INT_ACK 0x40000000L +#define CP_INT_ACK__RB_INT_ACK_MASK 0x80000000L +#define CP_INT_ACK__RB_INT_ACK 0x80000000L + +// CP_PFP_UCODE_ADDR +#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x000001ffL + +// CP_PFP_UCODE_DATA +#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0x00ffffffL + +// CP_PERFMON_CNTL +#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000fL +#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L + +// CP_PERFCOUNTER_SELECT +#define CP_PERFCOUNTER_SELECT__PERFCOUNT_SEL_MASK 0x0000003fL + +// CP_PERFCOUNTER_LO +#define CP_PERFCOUNTER_LO__PERFCOUNT_LO_MASK 0xffffffffL + +// CP_PERFCOUNTER_HI +#define CP_PERFCOUNTER_HI__PERFCOUNT_HI_MASK 0x0000ffffL + +// CP_BIN_MASK_LO +#define CP_BIN_MASK_LO__BIN_MASK_LO_MASK 0xffffffffL + +// CP_BIN_MASK_HI +#define CP_BIN_MASK_HI__BIN_MASK_HI_MASK 0xffffffffL + +// CP_BIN_SELECT_LO +#define CP_BIN_SELECT_LO__BIN_SELECT_LO_MASK 0xffffffffL + +// CP_BIN_SELECT_HI +#define CP_BIN_SELECT_HI__BIN_SELECT_HI_MASK 0xffffffffL + +// CP_NV_FLAGS_0 +#define CP_NV_FLAGS_0__DISCARD_0_MASK 0x00000001L +#define CP_NV_FLAGS_0__DISCARD_0 0x00000001L +#define CP_NV_FLAGS_0__END_RCVD_0_MASK 0x00000002L +#define CP_NV_FLAGS_0__END_RCVD_0 0x00000002L +#define CP_NV_FLAGS_0__DISCARD_1_MASK 0x00000004L +#define CP_NV_FLAGS_0__DISCARD_1 0x00000004L +#define CP_NV_FLAGS_0__END_RCVD_1_MASK 0x00000008L +#define CP_NV_FLAGS_0__END_RCVD_1 0x00000008L +#define CP_NV_FLAGS_0__DISCARD_2_MASK 0x00000010L +#define CP_NV_FLAGS_0__DISCARD_2 0x00000010L +#define CP_NV_FLAGS_0__END_RCVD_2_MASK 0x00000020L +#define CP_NV_FLAGS_0__END_RCVD_2 0x00000020L +#define CP_NV_FLAGS_0__DISCARD_3_MASK 0x00000040L +#define CP_NV_FLAGS_0__DISCARD_3 0x00000040L +#define CP_NV_FLAGS_0__END_RCVD_3_MASK 0x00000080L +#define CP_NV_FLAGS_0__END_RCVD_3 0x00000080L +#define CP_NV_FLAGS_0__DISCARD_4_MASK 0x00000100L +#define CP_NV_FLAGS_0__DISCARD_4 0x00000100L +#define CP_NV_FLAGS_0__END_RCVD_4_MASK 0x00000200L +#define CP_NV_FLAGS_0__END_RCVD_4 0x00000200L +#define CP_NV_FLAGS_0__DISCARD_5_MASK 0x00000400L +#define CP_NV_FLAGS_0__DISCARD_5 0x00000400L +#define CP_NV_FLAGS_0__END_RCVD_5_MASK 0x00000800L +#define CP_NV_FLAGS_0__END_RCVD_5 0x00000800L +#define CP_NV_FLAGS_0__DISCARD_6_MASK 0x00001000L +#define CP_NV_FLAGS_0__DISCARD_6 0x00001000L +#define CP_NV_FLAGS_0__END_RCVD_6_MASK 0x00002000L +#define CP_NV_FLAGS_0__END_RCVD_6 0x00002000L +#define CP_NV_FLAGS_0__DISCARD_7_MASK 0x00004000L +#define CP_NV_FLAGS_0__DISCARD_7 0x00004000L +#define CP_NV_FLAGS_0__END_RCVD_7_MASK 0x00008000L +#define CP_NV_FLAGS_0__END_RCVD_7 0x00008000L +#define CP_NV_FLAGS_0__DISCARD_8_MASK 0x00010000L +#define CP_NV_FLAGS_0__DISCARD_8 0x00010000L +#define CP_NV_FLAGS_0__END_RCVD_8_MASK 0x00020000L +#define CP_NV_FLAGS_0__END_RCVD_8 0x00020000L +#define CP_NV_FLAGS_0__DISCARD_9_MASK 0x00040000L +#define CP_NV_FLAGS_0__DISCARD_9 0x00040000L +#define CP_NV_FLAGS_0__END_RCVD_9_MASK 0x00080000L +#define CP_NV_FLAGS_0__END_RCVD_9 0x00080000L +#define CP_NV_FLAGS_0__DISCARD_10_MASK 0x00100000L +#define CP_NV_FLAGS_0__DISCARD_10 0x00100000L +#define CP_NV_FLAGS_0__END_RCVD_10_MASK 0x00200000L +#define CP_NV_FLAGS_0__END_RCVD_10 0x00200000L +#define CP_NV_FLAGS_0__DISCARD_11_MASK 0x00400000L +#define CP_NV_FLAGS_0__DISCARD_11 0x00400000L +#define CP_NV_FLAGS_0__END_RCVD_11_MASK 0x00800000L +#define CP_NV_FLAGS_0__END_RCVD_11 0x00800000L +#define CP_NV_FLAGS_0__DISCARD_12_MASK 0x01000000L +#define CP_NV_FLAGS_0__DISCARD_12 0x01000000L +#define CP_NV_FLAGS_0__END_RCVD_12_MASK 0x02000000L +#define CP_NV_FLAGS_0__END_RCVD_12 0x02000000L +#define CP_NV_FLAGS_0__DISCARD_13_MASK 0x04000000L +#define CP_NV_FLAGS_0__DISCARD_13 0x04000000L +#define CP_NV_FLAGS_0__END_RCVD_13_MASK 0x08000000L +#define CP_NV_FLAGS_0__END_RCVD_13 0x08000000L +#define CP_NV_FLAGS_0__DISCARD_14_MASK 0x10000000L +#define CP_NV_FLAGS_0__DISCARD_14 0x10000000L +#define CP_NV_FLAGS_0__END_RCVD_14_MASK 0x20000000L +#define CP_NV_FLAGS_0__END_RCVD_14 0x20000000L +#define CP_NV_FLAGS_0__DISCARD_15_MASK 0x40000000L +#define CP_NV_FLAGS_0__DISCARD_15 0x40000000L +#define CP_NV_FLAGS_0__END_RCVD_15_MASK 0x80000000L +#define CP_NV_FLAGS_0__END_RCVD_15 0x80000000L + +// CP_NV_FLAGS_1 +#define CP_NV_FLAGS_1__DISCARD_16_MASK 0x00000001L +#define CP_NV_FLAGS_1__DISCARD_16 0x00000001L +#define CP_NV_FLAGS_1__END_RCVD_16_MASK 0x00000002L +#define CP_NV_FLAGS_1__END_RCVD_16 0x00000002L +#define CP_NV_FLAGS_1__DISCARD_17_MASK 0x00000004L +#define CP_NV_FLAGS_1__DISCARD_17 0x00000004L +#define CP_NV_FLAGS_1__END_RCVD_17_MASK 0x00000008L +#define CP_NV_FLAGS_1__END_RCVD_17 0x00000008L +#define CP_NV_FLAGS_1__DISCARD_18_MASK 0x00000010L +#define CP_NV_FLAGS_1__DISCARD_18 0x00000010L +#define CP_NV_FLAGS_1__END_RCVD_18_MASK 0x00000020L +#define CP_NV_FLAGS_1__END_RCVD_18 0x00000020L +#define CP_NV_FLAGS_1__DISCARD_19_MASK 0x00000040L +#define CP_NV_FLAGS_1__DISCARD_19 0x00000040L +#define CP_NV_FLAGS_1__END_RCVD_19_MASK 0x00000080L +#define CP_NV_FLAGS_1__END_RCVD_19 0x00000080L +#define CP_NV_FLAGS_1__DISCARD_20_MASK 0x00000100L +#define CP_NV_FLAGS_1__DISCARD_20 0x00000100L +#define CP_NV_FLAGS_1__END_RCVD_20_MASK 0x00000200L +#define CP_NV_FLAGS_1__END_RCVD_20 0x00000200L +#define CP_NV_FLAGS_1__DISCARD_21_MASK 0x00000400L +#define CP_NV_FLAGS_1__DISCARD_21 0x00000400L +#define CP_NV_FLAGS_1__END_RCVD_21_MASK 0x00000800L +#define CP_NV_FLAGS_1__END_RCVD_21 0x00000800L +#define CP_NV_FLAGS_1__DISCARD_22_MASK 0x00001000L +#define CP_NV_FLAGS_1__DISCARD_22 0x00001000L +#define CP_NV_FLAGS_1__END_RCVD_22_MASK 0x00002000L +#define CP_NV_FLAGS_1__END_RCVD_22 0x00002000L +#define CP_NV_FLAGS_1__DISCARD_23_MASK 0x00004000L +#define CP_NV_FLAGS_1__DISCARD_23 0x00004000L +#define CP_NV_FLAGS_1__END_RCVD_23_MASK 0x00008000L +#define CP_NV_FLAGS_1__END_RCVD_23 0x00008000L +#define CP_NV_FLAGS_1__DISCARD_24_MASK 0x00010000L +#define CP_NV_FLAGS_1__DISCARD_24 0x00010000L +#define CP_NV_FLAGS_1__END_RCVD_24_MASK 0x00020000L +#define CP_NV_FLAGS_1__END_RCVD_24 0x00020000L +#define CP_NV_FLAGS_1__DISCARD_25_MASK 0x00040000L +#define CP_NV_FLAGS_1__DISCARD_25 0x00040000L +#define CP_NV_FLAGS_1__END_RCVD_25_MASK 0x00080000L +#define CP_NV_FLAGS_1__END_RCVD_25 0x00080000L +#define CP_NV_FLAGS_1__DISCARD_26_MASK 0x00100000L +#define CP_NV_FLAGS_1__DISCARD_26 0x00100000L +#define CP_NV_FLAGS_1__END_RCVD_26_MASK 0x00200000L +#define CP_NV_FLAGS_1__END_RCVD_26 0x00200000L +#define CP_NV_FLAGS_1__DISCARD_27_MASK 0x00400000L +#define CP_NV_FLAGS_1__DISCARD_27 0x00400000L +#define CP_NV_FLAGS_1__END_RCVD_27_MASK 0x00800000L +#define CP_NV_FLAGS_1__END_RCVD_27 0x00800000L +#define CP_NV_FLAGS_1__DISCARD_28_MASK 0x01000000L +#define CP_NV_FLAGS_1__DISCARD_28 0x01000000L +#define CP_NV_FLAGS_1__END_RCVD_28_MASK 0x02000000L +#define CP_NV_FLAGS_1__END_RCVD_28 0x02000000L +#define CP_NV_FLAGS_1__DISCARD_29_MASK 0x04000000L +#define CP_NV_FLAGS_1__DISCARD_29 0x04000000L +#define CP_NV_FLAGS_1__END_RCVD_29_MASK 0x08000000L +#define CP_NV_FLAGS_1__END_RCVD_29 0x08000000L +#define CP_NV_FLAGS_1__DISCARD_30_MASK 0x10000000L +#define CP_NV_FLAGS_1__DISCARD_30 0x10000000L +#define CP_NV_FLAGS_1__END_RCVD_30_MASK 0x20000000L +#define CP_NV_FLAGS_1__END_RCVD_30 0x20000000L +#define CP_NV_FLAGS_1__DISCARD_31_MASK 0x40000000L +#define CP_NV_FLAGS_1__DISCARD_31 0x40000000L +#define CP_NV_FLAGS_1__END_RCVD_31_MASK 0x80000000L +#define CP_NV_FLAGS_1__END_RCVD_31 0x80000000L + +// CP_NV_FLAGS_2 +#define CP_NV_FLAGS_2__DISCARD_32_MASK 0x00000001L +#define CP_NV_FLAGS_2__DISCARD_32 0x00000001L +#define CP_NV_FLAGS_2__END_RCVD_32_MASK 0x00000002L +#define CP_NV_FLAGS_2__END_RCVD_32 0x00000002L +#define CP_NV_FLAGS_2__DISCARD_33_MASK 0x00000004L +#define CP_NV_FLAGS_2__DISCARD_33 0x00000004L +#define CP_NV_FLAGS_2__END_RCVD_33_MASK 0x00000008L +#define CP_NV_FLAGS_2__END_RCVD_33 0x00000008L +#define CP_NV_FLAGS_2__DISCARD_34_MASK 0x00000010L +#define CP_NV_FLAGS_2__DISCARD_34 0x00000010L +#define CP_NV_FLAGS_2__END_RCVD_34_MASK 0x00000020L +#define CP_NV_FLAGS_2__END_RCVD_34 0x00000020L +#define CP_NV_FLAGS_2__DISCARD_35_MASK 0x00000040L +#define CP_NV_FLAGS_2__DISCARD_35 0x00000040L +#define CP_NV_FLAGS_2__END_RCVD_35_MASK 0x00000080L +#define CP_NV_FLAGS_2__END_RCVD_35 0x00000080L +#define CP_NV_FLAGS_2__DISCARD_36_MASK 0x00000100L +#define CP_NV_FLAGS_2__DISCARD_36 0x00000100L +#define CP_NV_FLAGS_2__END_RCVD_36_MASK 0x00000200L +#define CP_NV_FLAGS_2__END_RCVD_36 0x00000200L +#define CP_NV_FLAGS_2__DISCARD_37_MASK 0x00000400L +#define CP_NV_FLAGS_2__DISCARD_37 0x00000400L +#define CP_NV_FLAGS_2__END_RCVD_37_MASK 0x00000800L +#define CP_NV_FLAGS_2__END_RCVD_37 0x00000800L +#define CP_NV_FLAGS_2__DISCARD_38_MASK 0x00001000L +#define CP_NV_FLAGS_2__DISCARD_38 0x00001000L +#define CP_NV_FLAGS_2__END_RCVD_38_MASK 0x00002000L +#define CP_NV_FLAGS_2__END_RCVD_38 0x00002000L +#define CP_NV_FLAGS_2__DISCARD_39_MASK 0x00004000L +#define CP_NV_FLAGS_2__DISCARD_39 0x00004000L +#define CP_NV_FLAGS_2__END_RCVD_39_MASK 0x00008000L +#define CP_NV_FLAGS_2__END_RCVD_39 0x00008000L +#define CP_NV_FLAGS_2__DISCARD_40_MASK 0x00010000L +#define CP_NV_FLAGS_2__DISCARD_40 0x00010000L +#define CP_NV_FLAGS_2__END_RCVD_40_MASK 0x00020000L +#define CP_NV_FLAGS_2__END_RCVD_40 0x00020000L +#define CP_NV_FLAGS_2__DISCARD_41_MASK 0x00040000L +#define CP_NV_FLAGS_2__DISCARD_41 0x00040000L +#define CP_NV_FLAGS_2__END_RCVD_41_MASK 0x00080000L +#define CP_NV_FLAGS_2__END_RCVD_41 0x00080000L +#define CP_NV_FLAGS_2__DISCARD_42_MASK 0x00100000L +#define CP_NV_FLAGS_2__DISCARD_42 0x00100000L +#define CP_NV_FLAGS_2__END_RCVD_42_MASK 0x00200000L +#define CP_NV_FLAGS_2__END_RCVD_42 0x00200000L +#define CP_NV_FLAGS_2__DISCARD_43_MASK 0x00400000L +#define CP_NV_FLAGS_2__DISCARD_43 0x00400000L +#define CP_NV_FLAGS_2__END_RCVD_43_MASK 0x00800000L +#define CP_NV_FLAGS_2__END_RCVD_43 0x00800000L +#define CP_NV_FLAGS_2__DISCARD_44_MASK 0x01000000L +#define CP_NV_FLAGS_2__DISCARD_44 0x01000000L +#define CP_NV_FLAGS_2__END_RCVD_44_MASK 0x02000000L +#define CP_NV_FLAGS_2__END_RCVD_44 0x02000000L +#define CP_NV_FLAGS_2__DISCARD_45_MASK 0x04000000L +#define CP_NV_FLAGS_2__DISCARD_45 0x04000000L +#define CP_NV_FLAGS_2__END_RCVD_45_MASK 0x08000000L +#define CP_NV_FLAGS_2__END_RCVD_45 0x08000000L +#define CP_NV_FLAGS_2__DISCARD_46_MASK 0x10000000L +#define CP_NV_FLAGS_2__DISCARD_46 0x10000000L +#define CP_NV_FLAGS_2__END_RCVD_46_MASK 0x20000000L +#define CP_NV_FLAGS_2__END_RCVD_46 0x20000000L +#define CP_NV_FLAGS_2__DISCARD_47_MASK 0x40000000L +#define CP_NV_FLAGS_2__DISCARD_47 0x40000000L +#define CP_NV_FLAGS_2__END_RCVD_47_MASK 0x80000000L +#define CP_NV_FLAGS_2__END_RCVD_47 0x80000000L + +// CP_NV_FLAGS_3 +#define CP_NV_FLAGS_3__DISCARD_48_MASK 0x00000001L +#define CP_NV_FLAGS_3__DISCARD_48 0x00000001L +#define CP_NV_FLAGS_3__END_RCVD_48_MASK 0x00000002L +#define CP_NV_FLAGS_3__END_RCVD_48 0x00000002L +#define CP_NV_FLAGS_3__DISCARD_49_MASK 0x00000004L +#define CP_NV_FLAGS_3__DISCARD_49 0x00000004L +#define CP_NV_FLAGS_3__END_RCVD_49_MASK 0x00000008L +#define CP_NV_FLAGS_3__END_RCVD_49 0x00000008L +#define CP_NV_FLAGS_3__DISCARD_50_MASK 0x00000010L +#define CP_NV_FLAGS_3__DISCARD_50 0x00000010L +#define CP_NV_FLAGS_3__END_RCVD_50_MASK 0x00000020L +#define CP_NV_FLAGS_3__END_RCVD_50 0x00000020L +#define CP_NV_FLAGS_3__DISCARD_51_MASK 0x00000040L +#define CP_NV_FLAGS_3__DISCARD_51 0x00000040L +#define CP_NV_FLAGS_3__END_RCVD_51_MASK 0x00000080L +#define CP_NV_FLAGS_3__END_RCVD_51 0x00000080L +#define CP_NV_FLAGS_3__DISCARD_52_MASK 0x00000100L +#define CP_NV_FLAGS_3__DISCARD_52 0x00000100L +#define CP_NV_FLAGS_3__END_RCVD_52_MASK 0x00000200L +#define CP_NV_FLAGS_3__END_RCVD_52 0x00000200L +#define CP_NV_FLAGS_3__DISCARD_53_MASK 0x00000400L +#define CP_NV_FLAGS_3__DISCARD_53 0x00000400L +#define CP_NV_FLAGS_3__END_RCVD_53_MASK 0x00000800L +#define CP_NV_FLAGS_3__END_RCVD_53 0x00000800L +#define CP_NV_FLAGS_3__DISCARD_54_MASK 0x00001000L +#define CP_NV_FLAGS_3__DISCARD_54 0x00001000L +#define CP_NV_FLAGS_3__END_RCVD_54_MASK 0x00002000L +#define CP_NV_FLAGS_3__END_RCVD_54 0x00002000L +#define CP_NV_FLAGS_3__DISCARD_55_MASK 0x00004000L +#define CP_NV_FLAGS_3__DISCARD_55 0x00004000L +#define CP_NV_FLAGS_3__END_RCVD_55_MASK 0x00008000L +#define CP_NV_FLAGS_3__END_RCVD_55 0x00008000L +#define CP_NV_FLAGS_3__DISCARD_56_MASK 0x00010000L +#define CP_NV_FLAGS_3__DISCARD_56 0x00010000L +#define CP_NV_FLAGS_3__END_RCVD_56_MASK 0x00020000L +#define CP_NV_FLAGS_3__END_RCVD_56 0x00020000L +#define CP_NV_FLAGS_3__DISCARD_57_MASK 0x00040000L +#define CP_NV_FLAGS_3__DISCARD_57 0x00040000L +#define CP_NV_FLAGS_3__END_RCVD_57_MASK 0x00080000L +#define CP_NV_FLAGS_3__END_RCVD_57 0x00080000L +#define CP_NV_FLAGS_3__DISCARD_58_MASK 0x00100000L +#define CP_NV_FLAGS_3__DISCARD_58 0x00100000L +#define CP_NV_FLAGS_3__END_RCVD_58_MASK 0x00200000L +#define CP_NV_FLAGS_3__END_RCVD_58 0x00200000L +#define CP_NV_FLAGS_3__DISCARD_59_MASK 0x00400000L +#define CP_NV_FLAGS_3__DISCARD_59 0x00400000L +#define CP_NV_FLAGS_3__END_RCVD_59_MASK 0x00800000L +#define CP_NV_FLAGS_3__END_RCVD_59 0x00800000L +#define CP_NV_FLAGS_3__DISCARD_60_MASK 0x01000000L +#define CP_NV_FLAGS_3__DISCARD_60 0x01000000L +#define CP_NV_FLAGS_3__END_RCVD_60_MASK 0x02000000L +#define CP_NV_FLAGS_3__END_RCVD_60 0x02000000L +#define CP_NV_FLAGS_3__DISCARD_61_MASK 0x04000000L +#define CP_NV_FLAGS_3__DISCARD_61 0x04000000L +#define CP_NV_FLAGS_3__END_RCVD_61_MASK 0x08000000L +#define CP_NV_FLAGS_3__END_RCVD_61 0x08000000L +#define CP_NV_FLAGS_3__DISCARD_62_MASK 0x10000000L +#define CP_NV_FLAGS_3__DISCARD_62 0x10000000L +#define CP_NV_FLAGS_3__END_RCVD_62_MASK 0x20000000L +#define CP_NV_FLAGS_3__END_RCVD_62 0x20000000L +#define CP_NV_FLAGS_3__DISCARD_63_MASK 0x40000000L +#define CP_NV_FLAGS_3__DISCARD_63 0x40000000L +#define CP_NV_FLAGS_3__END_RCVD_63_MASK 0x80000000L +#define CP_NV_FLAGS_3__END_RCVD_63 0x80000000L + +// CP_STATE_DEBUG_INDEX +#define CP_STATE_DEBUG_INDEX__STATE_DEBUG_INDEX_MASK 0x0000001fL + +// CP_STATE_DEBUG_DATA +#define CP_STATE_DEBUG_DATA__STATE_DEBUG_DATA_MASK 0xffffffffL + +// CP_PROG_COUNTER +#define CP_PROG_COUNTER__COUNTER_MASK 0xffffffffL + +// CP_STAT +#define CP_STAT__MIU_WR_BUSY_MASK 0x00000001L +#define CP_STAT__MIU_WR_BUSY 0x00000001L +#define CP_STAT__MIU_RD_REQ_BUSY_MASK 0x00000002L +#define CP_STAT__MIU_RD_REQ_BUSY 0x00000002L +#define CP_STAT__MIU_RD_RETURN_BUSY_MASK 0x00000004L +#define CP_STAT__MIU_RD_RETURN_BUSY 0x00000004L +#define CP_STAT__RBIU_BUSY_MASK 0x00000008L +#define CP_STAT__RBIU_BUSY 0x00000008L +#define CP_STAT__RCIU_BUSY_MASK 0x00000010L +#define CP_STAT__RCIU_BUSY 0x00000010L +#define CP_STAT__CSF_RING_BUSY_MASK 0x00000020L +#define CP_STAT__CSF_RING_BUSY 0x00000020L +#define CP_STAT__CSF_INDIRECTS_BUSY_MASK 0x00000040L +#define CP_STAT__CSF_INDIRECTS_BUSY 0x00000040L +#define CP_STAT__CSF_INDIRECT2_BUSY_MASK 0x00000080L +#define CP_STAT__CSF_INDIRECT2_BUSY 0x00000080L +#define CP_STAT__CSF_ST_BUSY_MASK 0x00000200L +#define CP_STAT__CSF_ST_BUSY 0x00000200L +#define CP_STAT__CSF_BUSY_MASK 0x00000400L +#define CP_STAT__CSF_BUSY 0x00000400L +#define CP_STAT__RING_QUEUE_BUSY_MASK 0x00000800L +#define CP_STAT__RING_QUEUE_BUSY 0x00000800L +#define CP_STAT__INDIRECTS_QUEUE_BUSY_MASK 0x00001000L +#define CP_STAT__INDIRECTS_QUEUE_BUSY 0x00001000L +#define CP_STAT__INDIRECT2_QUEUE_BUSY_MASK 0x00002000L +#define CP_STAT__INDIRECT2_QUEUE_BUSY 0x00002000L +#define CP_STAT__ST_QUEUE_BUSY_MASK 0x00010000L +#define CP_STAT__ST_QUEUE_BUSY 0x00010000L +#define CP_STAT__PFP_BUSY_MASK 0x00020000L +#define CP_STAT__PFP_BUSY 0x00020000L +#define CP_STAT__MEQ_RING_BUSY_MASK 0x00040000L +#define CP_STAT__MEQ_RING_BUSY 0x00040000L +#define CP_STAT__MEQ_INDIRECTS_BUSY_MASK 0x00080000L +#define CP_STAT__MEQ_INDIRECTS_BUSY 0x00080000L +#define CP_STAT__MEQ_INDIRECT2_BUSY_MASK 0x00100000L +#define CP_STAT__MEQ_INDIRECT2_BUSY 0x00100000L +#define CP_STAT__MIU_WC_STALL_MASK 0x00200000L +#define CP_STAT__MIU_WC_STALL 0x00200000L +#define CP_STAT__CP_NRT_BUSY_MASK 0x00400000L +#define CP_STAT__CP_NRT_BUSY 0x00400000L +#define CP_STAT___3D_BUSY_MASK 0x00800000L +#define CP_STAT___3D_BUSY 0x00800000L +#define CP_STAT__ME_BUSY_MASK 0x04000000L +#define CP_STAT__ME_BUSY 0x04000000L +#define CP_STAT__ME_WC_BUSY_MASK 0x20000000L +#define CP_STAT__ME_WC_BUSY 0x20000000L +#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY_MASK 0x40000000L +#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY 0x40000000L +#define CP_STAT__CP_BUSY_MASK 0x80000000L +#define CP_STAT__CP_BUSY 0x80000000L + +// BIOS_0_SCRATCH +#define BIOS_0_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_1_SCRATCH +#define BIOS_1_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_2_SCRATCH +#define BIOS_2_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_3_SCRATCH +#define BIOS_3_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_4_SCRATCH +#define BIOS_4_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_5_SCRATCH +#define BIOS_5_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_6_SCRATCH +#define BIOS_6_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_7_SCRATCH +#define BIOS_7_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_8_SCRATCH +#define BIOS_8_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_9_SCRATCH +#define BIOS_9_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_10_SCRATCH +#define BIOS_10_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_11_SCRATCH +#define BIOS_11_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_12_SCRATCH +#define BIOS_12_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_13_SCRATCH +#define BIOS_13_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_14_SCRATCH +#define BIOS_14_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_15_SCRATCH +#define BIOS_15_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// COHER_SIZE_PM4 +#define COHER_SIZE_PM4__SIZE_MASK 0xffffffffL + +// COHER_BASE_PM4 +#define COHER_BASE_PM4__BASE_MASK 0xffffffffL + +// COHER_STATUS_PM4 +#define COHER_STATUS_PM4__MATCHING_CONTEXTS_MASK 0x000000ffL +#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA_MASK 0x00000100L +#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA 0x00000100L +#define COHER_STATUS_PM4__DEST_BASE_0_ENA_MASK 0x00000200L +#define COHER_STATUS_PM4__DEST_BASE_0_ENA 0x00000200L +#define COHER_STATUS_PM4__DEST_BASE_1_ENA_MASK 0x00000400L +#define COHER_STATUS_PM4__DEST_BASE_1_ENA 0x00000400L +#define COHER_STATUS_PM4__DEST_BASE_2_ENA_MASK 0x00000800L +#define COHER_STATUS_PM4__DEST_BASE_2_ENA 0x00000800L +#define COHER_STATUS_PM4__DEST_BASE_3_ENA_MASK 0x00001000L +#define COHER_STATUS_PM4__DEST_BASE_3_ENA 0x00001000L +#define COHER_STATUS_PM4__DEST_BASE_4_ENA_MASK 0x00002000L +#define COHER_STATUS_PM4__DEST_BASE_4_ENA 0x00002000L +#define COHER_STATUS_PM4__DEST_BASE_5_ENA_MASK 0x00004000L +#define COHER_STATUS_PM4__DEST_BASE_5_ENA 0x00004000L +#define COHER_STATUS_PM4__DEST_BASE_6_ENA_MASK 0x00008000L +#define COHER_STATUS_PM4__DEST_BASE_6_ENA 0x00008000L +#define COHER_STATUS_PM4__DEST_BASE_7_ENA_MASK 0x00010000L +#define COHER_STATUS_PM4__DEST_BASE_7_ENA 0x00010000L +#define COHER_STATUS_PM4__TC_ACTION_ENA_MASK 0x02000000L +#define COHER_STATUS_PM4__TC_ACTION_ENA 0x02000000L +#define COHER_STATUS_PM4__STATUS_MASK 0x80000000L +#define COHER_STATUS_PM4__STATUS 0x80000000L + +// COHER_SIZE_HOST +#define COHER_SIZE_HOST__SIZE_MASK 0xffffffffL + +// COHER_BASE_HOST +#define COHER_BASE_HOST__BASE_MASK 0xffffffffL + +// COHER_STATUS_HOST +#define COHER_STATUS_HOST__MATCHING_CONTEXTS_MASK 0x000000ffL +#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA_MASK 0x00000100L +#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA 0x00000100L +#define COHER_STATUS_HOST__DEST_BASE_0_ENA_MASK 0x00000200L +#define COHER_STATUS_HOST__DEST_BASE_0_ENA 0x00000200L +#define COHER_STATUS_HOST__DEST_BASE_1_ENA_MASK 0x00000400L +#define COHER_STATUS_HOST__DEST_BASE_1_ENA 0x00000400L +#define COHER_STATUS_HOST__DEST_BASE_2_ENA_MASK 0x00000800L +#define COHER_STATUS_HOST__DEST_BASE_2_ENA 0x00000800L +#define COHER_STATUS_HOST__DEST_BASE_3_ENA_MASK 0x00001000L +#define COHER_STATUS_HOST__DEST_BASE_3_ENA 0x00001000L +#define COHER_STATUS_HOST__DEST_BASE_4_ENA_MASK 0x00002000L +#define COHER_STATUS_HOST__DEST_BASE_4_ENA 0x00002000L +#define COHER_STATUS_HOST__DEST_BASE_5_ENA_MASK 0x00004000L +#define COHER_STATUS_HOST__DEST_BASE_5_ENA 0x00004000L +#define COHER_STATUS_HOST__DEST_BASE_6_ENA_MASK 0x00008000L +#define COHER_STATUS_HOST__DEST_BASE_6_ENA 0x00008000L +#define COHER_STATUS_HOST__DEST_BASE_7_ENA_MASK 0x00010000L +#define COHER_STATUS_HOST__DEST_BASE_7_ENA 0x00010000L +#define COHER_STATUS_HOST__TC_ACTION_ENA_MASK 0x02000000L +#define COHER_STATUS_HOST__TC_ACTION_ENA 0x02000000L +#define COHER_STATUS_HOST__STATUS_MASK 0x80000000L +#define COHER_STATUS_HOST__STATUS 0x80000000L + +// COHER_DEST_BASE_0 +#define COHER_DEST_BASE_0__DEST_BASE_0_MASK 0xfffff000L + +// COHER_DEST_BASE_1 +#define COHER_DEST_BASE_1__DEST_BASE_1_MASK 0xfffff000L + +// COHER_DEST_BASE_2 +#define COHER_DEST_BASE_2__DEST_BASE_2_MASK 0xfffff000L + +// COHER_DEST_BASE_3 +#define COHER_DEST_BASE_3__DEST_BASE_3_MASK 0xfffff000L + +// COHER_DEST_BASE_4 +#define COHER_DEST_BASE_4__DEST_BASE_4_MASK 0xfffff000L + +// COHER_DEST_BASE_5 +#define COHER_DEST_BASE_5__DEST_BASE_5_MASK 0xfffff000L + +// COHER_DEST_BASE_6 +#define COHER_DEST_BASE_6__DEST_BASE_6_MASK 0xfffff000L + +// COHER_DEST_BASE_7 +#define COHER_DEST_BASE_7__DEST_BASE_7_MASK 0xfffff000L + +// RB_SURFACE_INFO +#define RB_SURFACE_INFO__SURFACE_PITCH_MASK 0x00003fffL +#define RB_SURFACE_INFO__MSAA_SAMPLES_MASK 0x0000c000L + +// RB_COLOR_INFO +#define RB_COLOR_INFO__COLOR_FORMAT_MASK 0x0000000fL +#define RB_COLOR_INFO__COLOR_ROUND_MODE_MASK 0x00000030L +#define RB_COLOR_INFO__COLOR_LINEAR_MASK 0x00000040L +#define RB_COLOR_INFO__COLOR_LINEAR 0x00000040L +#define RB_COLOR_INFO__COLOR_ENDIAN_MASK 0x00000180L +#define RB_COLOR_INFO__COLOR_SWAP_MASK 0x00000600L +#define RB_COLOR_INFO__COLOR_BASE_MASK 0xfffff000L + +// RB_DEPTH_INFO +#define RB_DEPTH_INFO__DEPTH_FORMAT_MASK 0x00000001L +#define RB_DEPTH_INFO__DEPTH_FORMAT 0x00000001L +#define RB_DEPTH_INFO__DEPTH_BASE_MASK 0xfffff000L + +// RB_STENCILREFMASK +#define RB_STENCILREFMASK__STENCILREF_MASK 0x000000ffL +#define RB_STENCILREFMASK__STENCILMASK_MASK 0x0000ff00L +#define RB_STENCILREFMASK__STENCILWRITEMASK_MASK 0x00ff0000L + +// RB_ALPHA_REF +#define RB_ALPHA_REF__ALPHA_REF_MASK 0xffffffffL + +// RB_COLOR_MASK +#define RB_COLOR_MASK__WRITE_RED_MASK 0x00000001L +#define RB_COLOR_MASK__WRITE_RED 0x00000001L +#define RB_COLOR_MASK__WRITE_GREEN_MASK 0x00000002L +#define RB_COLOR_MASK__WRITE_GREEN 0x00000002L +#define RB_COLOR_MASK__WRITE_BLUE_MASK 0x00000004L +#define RB_COLOR_MASK__WRITE_BLUE 0x00000004L +#define RB_COLOR_MASK__WRITE_ALPHA_MASK 0x00000008L +#define RB_COLOR_MASK__WRITE_ALPHA 0x00000008L + +// RB_BLEND_RED +#define RB_BLEND_RED__BLEND_RED_MASK 0x000000ffL + +// RB_BLEND_GREEN +#define RB_BLEND_GREEN__BLEND_GREEN_MASK 0x000000ffL + +// RB_BLEND_BLUE +#define RB_BLEND_BLUE__BLEND_BLUE_MASK 0x000000ffL + +// RB_BLEND_ALPHA +#define RB_BLEND_ALPHA__BLEND_ALPHA_MASK 0x000000ffL + +// RB_FOG_COLOR +#define RB_FOG_COLOR__FOG_RED_MASK 0x000000ffL +#define RB_FOG_COLOR__FOG_GREEN_MASK 0x0000ff00L +#define RB_FOG_COLOR__FOG_BLUE_MASK 0x00ff0000L + +// RB_STENCILREFMASK_BF +#define RB_STENCILREFMASK_BF__STENCILREF_BF_MASK 0x000000ffL +#define RB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0x0000ff00L +#define RB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0x00ff0000L + +// RB_DEPTHCONTROL +#define RB_DEPTHCONTROL__STENCIL_ENABLE_MASK 0x00000001L +#define RB_DEPTHCONTROL__STENCIL_ENABLE 0x00000001L +#define RB_DEPTHCONTROL__Z_ENABLE_MASK 0x00000002L +#define RB_DEPTHCONTROL__Z_ENABLE 0x00000002L +#define RB_DEPTHCONTROL__Z_WRITE_ENABLE_MASK 0x00000004L +#define RB_DEPTHCONTROL__Z_WRITE_ENABLE 0x00000004L +#define RB_DEPTHCONTROL__EARLY_Z_ENABLE_MASK 0x00000008L +#define RB_DEPTHCONTROL__EARLY_Z_ENABLE 0x00000008L +#define RB_DEPTHCONTROL__ZFUNC_MASK 0x00000070L +#define RB_DEPTHCONTROL__BACKFACE_ENABLE_MASK 0x00000080L +#define RB_DEPTHCONTROL__BACKFACE_ENABLE 0x00000080L +#define RB_DEPTHCONTROL__STENCILFUNC_MASK 0x00000700L +#define RB_DEPTHCONTROL__STENCILFAIL_MASK 0x00003800L +#define RB_DEPTHCONTROL__STENCILZPASS_MASK 0x0001c000L +#define RB_DEPTHCONTROL__STENCILZFAIL_MASK 0x000e0000L +#define RB_DEPTHCONTROL__STENCILFUNC_BF_MASK 0x00700000L +#define RB_DEPTHCONTROL__STENCILFAIL_BF_MASK 0x03800000L +#define RB_DEPTHCONTROL__STENCILZPASS_BF_MASK 0x1c000000L +#define RB_DEPTHCONTROL__STENCILZFAIL_BF_MASK 0xe0000000L + +// RB_BLENDCONTROL +#define RB_BLENDCONTROL__COLOR_SRCBLEND_MASK 0x0000001fL +#define RB_BLENDCONTROL__COLOR_COMB_FCN_MASK 0x000000e0L +#define RB_BLENDCONTROL__COLOR_DESTBLEND_MASK 0x00001f00L +#define RB_BLENDCONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L +#define RB_BLENDCONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L +#define RB_BLENDCONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L +#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE_MASK 0x20000000L +#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE 0x20000000L +#define RB_BLENDCONTROL__BLEND_FORCE_MASK 0x40000000L +#define RB_BLENDCONTROL__BLEND_FORCE 0x40000000L + +// RB_COLORCONTROL +#define RB_COLORCONTROL__ALPHA_FUNC_MASK 0x00000007L +#define RB_COLORCONTROL__ALPHA_TEST_ENABLE_MASK 0x00000008L +#define RB_COLORCONTROL__ALPHA_TEST_ENABLE 0x00000008L +#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE_MASK 0x00000010L +#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE 0x00000010L +#define RB_COLORCONTROL__BLEND_DISABLE_MASK 0x00000020L +#define RB_COLORCONTROL__BLEND_DISABLE 0x00000020L +#define RB_COLORCONTROL__FOG_ENABLE_MASK 0x00000040L +#define RB_COLORCONTROL__FOG_ENABLE 0x00000040L +#define RB_COLORCONTROL__VS_EXPORTS_FOG_MASK 0x00000080L +#define RB_COLORCONTROL__VS_EXPORTS_FOG 0x00000080L +#define RB_COLORCONTROL__ROP_CODE_MASK 0x00000f00L +#define RB_COLORCONTROL__DITHER_MODE_MASK 0x00003000L +#define RB_COLORCONTROL__DITHER_TYPE_MASK 0x0000c000L +#define RB_COLORCONTROL__PIXEL_FOG_MASK 0x00010000L +#define RB_COLORCONTROL__PIXEL_FOG 0x00010000L +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET0_MASK 0x03000000L +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET1_MASK 0x0c000000L +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET2_MASK 0x30000000L +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET3_MASK 0xc0000000L + +// RB_MODECONTROL +#define RB_MODECONTROL__EDRAM_MODE_MASK 0x00000007L + +// RB_COLOR_DEST_MASK +#define RB_COLOR_DEST_MASK__COLOR_DEST_MASK_MASK 0xffffffffL + +// RB_COPY_CONTROL +#define RB_COPY_CONTROL__COPY_SAMPLE_SELECT_MASK 0x00000007L +#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x00000008L +#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE 0x00000008L +#define RB_COPY_CONTROL__CLEAR_MASK_MASK 0x000000f0L + +// RB_COPY_DEST_BASE +#define RB_COPY_DEST_BASE__COPY_DEST_BASE_MASK 0xfffff000L + +// RB_COPY_DEST_PITCH +#define RB_COPY_DEST_PITCH__COPY_DEST_PITCH_MASK 0x000001ffL + +// RB_COPY_DEST_INFO +#define RB_COPY_DEST_INFO__COPY_DEST_ENDIAN_MASK 0x00000007L +#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR_MASK 0x00000008L +#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR 0x00000008L +#define RB_COPY_DEST_INFO__COPY_DEST_FORMAT_MASK 0x000000f0L +#define RB_COPY_DEST_INFO__COPY_DEST_SWAP_MASK 0x00000300L +#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_MODE_MASK 0x00000c00L +#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_TYPE_MASK 0x00003000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED_MASK 0x00004000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED 0x00004000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN_MASK 0x00008000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN 0x00008000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE_MASK 0x00010000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE 0x00010000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA_MASK 0x00020000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA 0x00020000L + +// RB_COPY_DEST_PIXEL_OFFSET +#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_X_MASK 0x00001fffL +#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_Y_MASK 0x03ffe000L + +// RB_DEPTH_CLEAR +#define RB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xffffffffL + +// RB_SAMPLE_COUNT_CTL +#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT_MASK 0x00000001L +#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT 0x00000001L +#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT_MASK 0x00000002L +#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT 0x00000002L + +// RB_SAMPLE_COUNT_ADDR +#define RB_SAMPLE_COUNT_ADDR__SAMPLE_COUNT_ADDR_MASK 0xffffffffL + +// RB_BC_CONTROL +#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE_MASK 0x00000001L +#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE 0x00000001L +#define RB_BC_CONTROL__ACCUM_TIMEOUT_SELECT_MASK 0x00000006L +#define RB_BC_CONTROL__DISABLE_EDRAM_CAM_MASK 0x00000008L +#define RB_BC_CONTROL__DISABLE_EDRAM_CAM 0x00000008L +#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK 0x00000010L +#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH 0x00000010L +#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP_MASK 0x00000020L +#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP 0x00000020L +#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP_MASK 0x00000040L +#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP 0x00000040L +#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE_MASK 0x00000080L +#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE 0x00000080L +#define RB_BC_CONTROL__AZ_THROTTLE_COUNT_MASK 0x00001f00L +#define RB_BC_CONTROL__ENABLE_CRC_UPDATE_MASK 0x00004000L +#define RB_BC_CONTROL__ENABLE_CRC_UPDATE 0x00004000L +#define RB_BC_CONTROL__CRC_MODE_MASK 0x00008000L +#define RB_BC_CONTROL__CRC_MODE 0x00008000L +#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS_MASK 0x00010000L +#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS 0x00010000L +#define RB_BC_CONTROL__DISABLE_ACCUM_MASK 0x00020000L +#define RB_BC_CONTROL__DISABLE_ACCUM 0x00020000L +#define RB_BC_CONTROL__ACCUM_ALLOC_MASK_MASK 0x003c0000L +#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE_MASK 0x00400000L +#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE 0x00400000L +#define RB_BC_CONTROL__ACCUM_DATA_FIFO_LIMIT_MASK 0x07800000L +#define RB_BC_CONTROL__MEM_EXPORT_TIMEOUT_SELECT_MASK 0x18000000L +#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE_MASK 0x20000000L +#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE 0x20000000L +#define RB_BC_CONTROL__RESERVED9_MASK 0x40000000L +#define RB_BC_CONTROL__RESERVED9 0x40000000L +#define RB_BC_CONTROL__RESERVED10_MASK 0x80000000L +#define RB_BC_CONTROL__RESERVED10 0x80000000L + +// RB_EDRAM_INFO +#define RB_EDRAM_INFO__EDRAM_SIZE_MASK 0x0000000fL +#define RB_EDRAM_INFO__EDRAM_MAPPING_MODE_MASK 0x00000030L +#define RB_EDRAM_INFO__EDRAM_RANGE_MASK 0xffffc000L + +// RB_CRC_RD_PORT +#define RB_CRC_RD_PORT__CRC_DATA_MASK 0xffffffffL + +// RB_CRC_CONTROL +#define RB_CRC_CONTROL__CRC_RD_ADVANCE_MASK 0x00000001L +#define RB_CRC_CONTROL__CRC_RD_ADVANCE 0x00000001L + +// RB_CRC_MASK +#define RB_CRC_MASK__CRC_MASK_MASK 0xffffffffL + +// RB_PERFCOUNTER0_SELECT +#define RB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// RB_PERFCOUNTER0_LOW +#define RB_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// RB_PERFCOUNTER0_HI +#define RB_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// RB_TOTAL_SAMPLES +#define RB_TOTAL_SAMPLES__TOTAL_SAMPLES_MASK 0xffffffffL + +// RB_ZPASS_SAMPLES +#define RB_ZPASS_SAMPLES__ZPASS_SAMPLES_MASK 0xffffffffL + +// RB_ZFAIL_SAMPLES +#define RB_ZFAIL_SAMPLES__ZFAIL_SAMPLES_MASK 0xffffffffL + +// RB_SFAIL_SAMPLES +#define RB_SFAIL_SAMPLES__SFAIL_SAMPLES_MASK 0xffffffffL + +// RB_DEBUG_0 +#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL_MASK 0x00000001L +#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL 0x00000001L +#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL_MASK 0x00000002L +#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL 0x00000002L +#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL_MASK 0x00000004L +#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL 0x00000004L +#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL_MASK 0x00000008L +#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL 0x00000008L +#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL_MASK 0x00000010L +#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL 0x00000010L +#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL_MASK 0x00000020L +#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL 0x00000020L +#define RB_DEBUG_0__RDREQ_Z1_FULL_MASK 0x00000040L +#define RB_DEBUG_0__RDREQ_Z1_FULL 0x00000040L +#define RB_DEBUG_0__RDREQ_Z0_FULL_MASK 0x00000080L +#define RB_DEBUG_0__RDREQ_Z0_FULL 0x00000080L +#define RB_DEBUG_0__RDREQ_C1_FULL_MASK 0x00000100L +#define RB_DEBUG_0__RDREQ_C1_FULL 0x00000100L +#define RB_DEBUG_0__RDREQ_C0_FULL_MASK 0x00000200L +#define RB_DEBUG_0__RDREQ_C0_FULL 0x00000200L +#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL_MASK 0x00000400L +#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL 0x00000400L +#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL_MASK 0x00000800L +#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL 0x00000800L +#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL_MASK 0x00001000L +#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL 0x00001000L +#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL_MASK 0x00002000L +#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL 0x00002000L +#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL_MASK 0x00004000L +#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL 0x00004000L +#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL_MASK 0x00008000L +#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL 0x00008000L +#define RB_DEBUG_0__WRREQ_Z1_FULL_MASK 0x00010000L +#define RB_DEBUG_0__WRREQ_Z1_FULL 0x00010000L +#define RB_DEBUG_0__WRREQ_Z0_FULL_MASK 0x00020000L +#define RB_DEBUG_0__WRREQ_Z0_FULL 0x00020000L +#define RB_DEBUG_0__WRREQ_C1_FULL_MASK 0x00040000L +#define RB_DEBUG_0__WRREQ_C1_FULL 0x00040000L +#define RB_DEBUG_0__WRREQ_C0_FULL_MASK 0x00080000L +#define RB_DEBUG_0__WRREQ_C0_FULL 0x00080000L +#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL_MASK 0x00100000L +#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL 0x00100000L +#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL_MASK 0x00200000L +#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL 0x00200000L +#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL_MASK 0x00400000L +#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL 0x00400000L +#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL_MASK 0x00800000L +#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL 0x00800000L +#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL_MASK 0x01000000L +#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL 0x01000000L +#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL_MASK 0x02000000L +#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL 0x02000000L +#define RB_DEBUG_0__C_SX_LAT_FULL_MASK 0x04000000L +#define RB_DEBUG_0__C_SX_LAT_FULL 0x04000000L +#define RB_DEBUG_0__C_SX_CMD_FULL_MASK 0x08000000L +#define RB_DEBUG_0__C_SX_CMD_FULL 0x08000000L +#define RB_DEBUG_0__C_EZ_TILE_FULL_MASK 0x10000000L +#define RB_DEBUG_0__C_EZ_TILE_FULL 0x10000000L +#define RB_DEBUG_0__C_REQ_FULL_MASK 0x20000000L +#define RB_DEBUG_0__C_REQ_FULL 0x20000000L +#define RB_DEBUG_0__C_MASK_FULL_MASK 0x40000000L +#define RB_DEBUG_0__C_MASK_FULL 0x40000000L +#define RB_DEBUG_0__EZ_INFSAMP_FULL_MASK 0x80000000L +#define RB_DEBUG_0__EZ_INFSAMP_FULL 0x80000000L + +// RB_DEBUG_1 +#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY_MASK 0x00000001L +#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY 0x00000001L +#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY_MASK 0x00000002L +#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY 0x00000002L +#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY_MASK 0x00000004L +#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY 0x00000004L +#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY_MASK 0x00000008L +#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY 0x00000008L +#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY_MASK 0x00000010L +#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY 0x00000010L +#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY_MASK 0x00000020L +#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY 0x00000020L +#define RB_DEBUG_1__RDREQ_Z1_EMPTY_MASK 0x00000040L +#define RB_DEBUG_1__RDREQ_Z1_EMPTY 0x00000040L +#define RB_DEBUG_1__RDREQ_Z0_EMPTY_MASK 0x00000080L +#define RB_DEBUG_1__RDREQ_Z0_EMPTY 0x00000080L +#define RB_DEBUG_1__RDREQ_C1_EMPTY_MASK 0x00000100L +#define RB_DEBUG_1__RDREQ_C1_EMPTY 0x00000100L +#define RB_DEBUG_1__RDREQ_C0_EMPTY_MASK 0x00000200L +#define RB_DEBUG_1__RDREQ_C0_EMPTY 0x00000200L +#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY_MASK 0x00000400L +#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY 0x00000400L +#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY_MASK 0x00000800L +#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY 0x00000800L +#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY_MASK 0x00001000L +#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY 0x00001000L +#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY_MASK 0x00002000L +#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY 0x00002000L +#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY_MASK 0x00004000L +#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY 0x00004000L +#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY_MASK 0x00008000L +#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY 0x00008000L +#define RB_DEBUG_1__WRREQ_Z1_EMPTY_MASK 0x00010000L +#define RB_DEBUG_1__WRREQ_Z1_EMPTY 0x00010000L +#define RB_DEBUG_1__WRREQ_Z0_EMPTY_MASK 0x00020000L +#define RB_DEBUG_1__WRREQ_Z0_EMPTY 0x00020000L +#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY_MASK 0x00040000L +#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY 0x00040000L +#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY_MASK 0x00080000L +#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY 0x00080000L +#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY_MASK 0x00100000L +#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY 0x00100000L +#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY_MASK 0x00200000L +#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY 0x00200000L +#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY_MASK 0x00400000L +#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY 0x00400000L +#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY_MASK 0x00800000L +#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY 0x00800000L +#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY_MASK 0x01000000L +#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY 0x01000000L +#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY_MASK 0x02000000L +#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY 0x02000000L +#define RB_DEBUG_1__C_SX_LAT_EMPTY_MASK 0x04000000L +#define RB_DEBUG_1__C_SX_LAT_EMPTY 0x04000000L +#define RB_DEBUG_1__C_SX_CMD_EMPTY_MASK 0x08000000L +#define RB_DEBUG_1__C_SX_CMD_EMPTY 0x08000000L +#define RB_DEBUG_1__C_EZ_TILE_EMPTY_MASK 0x10000000L +#define RB_DEBUG_1__C_EZ_TILE_EMPTY 0x10000000L +#define RB_DEBUG_1__C_REQ_EMPTY_MASK 0x20000000L +#define RB_DEBUG_1__C_REQ_EMPTY 0x20000000L +#define RB_DEBUG_1__C_MASK_EMPTY_MASK 0x40000000L +#define RB_DEBUG_1__C_MASK_EMPTY 0x40000000L +#define RB_DEBUG_1__EZ_INFSAMP_EMPTY_MASK 0x80000000L +#define RB_DEBUG_1__EZ_INFSAMP_EMPTY 0x80000000L + +// RB_DEBUG_2 +#define RB_DEBUG_2__TILE_FIFO_COUNT_MASK 0x0000000fL +#define RB_DEBUG_2__SX_LAT_FIFO_COUNT_MASK 0x000007f0L +#define RB_DEBUG_2__MEM_EXPORT_FLAG_MASK 0x00000800L +#define RB_DEBUG_2__MEM_EXPORT_FLAG 0x00000800L +#define RB_DEBUG_2__SYSMEM_BLEND_FLAG_MASK 0x00001000L +#define RB_DEBUG_2__SYSMEM_BLEND_FLAG 0x00001000L +#define RB_DEBUG_2__CURRENT_TILE_EVENT_MASK 0x00002000L +#define RB_DEBUG_2__CURRENT_TILE_EVENT 0x00002000L +#define RB_DEBUG_2__EZ_INFTILE_FULL_MASK 0x00004000L +#define RB_DEBUG_2__EZ_INFTILE_FULL 0x00004000L +#define RB_DEBUG_2__EZ_MASK_LOWER_FULL_MASK 0x00008000L +#define RB_DEBUG_2__EZ_MASK_LOWER_FULL 0x00008000L +#define RB_DEBUG_2__EZ_MASK_UPPER_FULL_MASK 0x00010000L +#define RB_DEBUG_2__EZ_MASK_UPPER_FULL 0x00010000L +#define RB_DEBUG_2__Z0_MASK_FULL_MASK 0x00020000L +#define RB_DEBUG_2__Z0_MASK_FULL 0x00020000L +#define RB_DEBUG_2__Z1_MASK_FULL_MASK 0x00040000L +#define RB_DEBUG_2__Z1_MASK_FULL 0x00040000L +#define RB_DEBUG_2__Z0_REQ_FULL_MASK 0x00080000L +#define RB_DEBUG_2__Z0_REQ_FULL 0x00080000L +#define RB_DEBUG_2__Z1_REQ_FULL_MASK 0x00100000L +#define RB_DEBUG_2__Z1_REQ_FULL 0x00100000L +#define RB_DEBUG_2__Z_SAMP_FULL_MASK 0x00200000L +#define RB_DEBUG_2__Z_SAMP_FULL 0x00200000L +#define RB_DEBUG_2__Z_TILE_FULL_MASK 0x00400000L +#define RB_DEBUG_2__Z_TILE_FULL 0x00400000L +#define RB_DEBUG_2__EZ_INFTILE_EMPTY_MASK 0x00800000L +#define RB_DEBUG_2__EZ_INFTILE_EMPTY 0x00800000L +#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY_MASK 0x01000000L +#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY 0x01000000L +#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY_MASK 0x02000000L +#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY 0x02000000L +#define RB_DEBUG_2__Z0_MASK_EMPTY_MASK 0x04000000L +#define RB_DEBUG_2__Z0_MASK_EMPTY 0x04000000L +#define RB_DEBUG_2__Z1_MASK_EMPTY_MASK 0x08000000L +#define RB_DEBUG_2__Z1_MASK_EMPTY 0x08000000L +#define RB_DEBUG_2__Z0_REQ_EMPTY_MASK 0x10000000L +#define RB_DEBUG_2__Z0_REQ_EMPTY 0x10000000L +#define RB_DEBUG_2__Z1_REQ_EMPTY_MASK 0x20000000L +#define RB_DEBUG_2__Z1_REQ_EMPTY 0x20000000L +#define RB_DEBUG_2__Z_SAMP_EMPTY_MASK 0x40000000L +#define RB_DEBUG_2__Z_SAMP_EMPTY 0x40000000L +#define RB_DEBUG_2__Z_TILE_EMPTY_MASK 0x80000000L +#define RB_DEBUG_2__Z_TILE_EMPTY 0x80000000L + +// RB_DEBUG_3 +#define RB_DEBUG_3__ACCUM_VALID_MASK 0x0000000fL +#define RB_DEBUG_3__ACCUM_FLUSHING_MASK 0x000000f0L +#define RB_DEBUG_3__ACCUM_WRITE_CLEAN_COUNT_MASK 0x00003f00L +#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID_MASK 0x00004000L +#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID 0x00004000L +#define RB_DEBUG_3__ACCUM_DATA_FIFO_CNT_MASK 0x00078000L +#define RB_DEBUG_3__SHD_FULL_MASK 0x00080000L +#define RB_DEBUG_3__SHD_FULL 0x00080000L +#define RB_DEBUG_3__SHD_EMPTY_MASK 0x00100000L +#define RB_DEBUG_3__SHD_EMPTY 0x00100000L +#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY_MASK 0x00200000L +#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY 0x00200000L +#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY_MASK 0x00400000L +#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY 0x00400000L +#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL_MASK 0x00800000L +#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL 0x00800000L +#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL_MASK 0x01000000L +#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL 0x01000000L +#define RB_DEBUG_3__ZEXP_LOWER_EMPTY_MASK 0x02000000L +#define RB_DEBUG_3__ZEXP_LOWER_EMPTY 0x02000000L +#define RB_DEBUG_3__ZEXP_UPPER_EMPTY_MASK 0x04000000L +#define RB_DEBUG_3__ZEXP_UPPER_EMPTY 0x04000000L +#define RB_DEBUG_3__ZEXP_LOWER_FULL_MASK 0x08000000L +#define RB_DEBUG_3__ZEXP_LOWER_FULL 0x08000000L +#define RB_DEBUG_3__ZEXP_UPPER_FULL_MASK 0x10000000L +#define RB_DEBUG_3__ZEXP_UPPER_FULL 0x10000000L + +// RB_DEBUG_4 +#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG_MASK 0x00000001L +#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG 0x00000001L +#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG_MASK 0x00000002L +#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG 0x00000002L +#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG_MASK 0x00000004L +#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG 0x00000004L +#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG_MASK 0x00000008L +#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG 0x00000008L +#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY_MASK 0x00000010L +#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY 0x00000010L +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY_MASK 0x00000020L +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY 0x00000020L +#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL_MASK 0x00000040L +#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL 0x00000040L +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL_MASK 0x00000080L +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL 0x00000080L +#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW_MASK 0x00000100L +#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW 0x00000100L +#define RB_DEBUG_4__CONTEXT_COUNT_DEBUG_MASK 0x00001e00L + +// RB_FLAG_CONTROL +#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR_MASK 0x00000001L +#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR 0x00000001L + +// BC_DUMMY_CRAYRB_ENUMS +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_FORMAT_MASK 0x0000003fL +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP_MASK 0x00000040L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP 0x00000040L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_ARRAY_MASK 0x00000180L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_ARRAY_MASK 0x00000600L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_COLOR_FORMAT_MASK 0x0001f800L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_NUMBER_MASK 0x000e0000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_FORMAT_MASK 0x03f00000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING_MASK 0x04000000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING 0x04000000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_ARRAY_MASK 0x18000000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK 0xe0000000L + +// BC_DUMMY_CRAYRB_MOREENUMS +#define BC_DUMMY_CRAYRB_MOREENUMS__DUMMY_CRAYRB_COLORARRAYX_MASK 0x00000003L + +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_offset.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_offset.h new file mode 100644 index 000000000000..6a229a8e79e2 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_offset.h @@ -0,0 +1,581 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _yamato_OFFSET_HEADER +#define _yamato_OFFSET_HEADER + + +// Registers from PA block + +#define mmPA_CL_VPORT_XSCALE 0x210F +#define mmPA_CL_VPORT_XOFFSET 0x2110 +#define mmPA_CL_VPORT_YSCALE 0x2111 +#define mmPA_CL_VPORT_YOFFSET 0x2112 +#define mmPA_CL_VPORT_ZSCALE 0x2113 +#define mmPA_CL_VPORT_ZOFFSET 0x2114 +#define mmPA_CL_VTE_CNTL 0x2206 +#define mmPA_CL_CLIP_CNTL 0x2204 +#define mmPA_CL_GB_VERT_CLIP_ADJ 0x2303 +#define mmPA_CL_GB_VERT_DISC_ADJ 0x2304 +#define mmPA_CL_GB_HORZ_CLIP_ADJ 0x2305 +#define mmPA_CL_GB_HORZ_DISC_ADJ 0x2306 +#define mmPA_CL_ENHANCE 0x0C85 +#define mmPA_SC_ENHANCE 0x0CA5 +#define mmPA_SU_VTX_CNTL 0x2302 +#define mmPA_SU_POINT_SIZE 0x2280 +#define mmPA_SU_POINT_MINMAX 0x2281 +#define mmPA_SU_LINE_CNTL 0x2282 +#define mmPA_SU_SC_MODE_CNTL 0x2205 +#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0x2380 +#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0x2381 +#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0x2382 +#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0x2383 +#define mmPA_SU_PERFCOUNTER0_SELECT 0x0C88 +#define mmPA_SU_PERFCOUNTER1_SELECT 0x0C89 +#define mmPA_SU_PERFCOUNTER2_SELECT 0x0C8A +#define mmPA_SU_PERFCOUNTER3_SELECT 0x0C8B +#define mmPA_SU_PERFCOUNTER0_LOW 0x0C8C +#define mmPA_SU_PERFCOUNTER0_HI 0x0C8D +#define mmPA_SU_PERFCOUNTER1_LOW 0x0C8E +#define mmPA_SU_PERFCOUNTER1_HI 0x0C8F +#define mmPA_SU_PERFCOUNTER2_LOW 0x0C90 +#define mmPA_SU_PERFCOUNTER2_HI 0x0C91 +#define mmPA_SU_PERFCOUNTER3_LOW 0x0C92 +#define mmPA_SU_PERFCOUNTER3_HI 0x0C93 +#define mmPA_SC_WINDOW_OFFSET 0x2080 +#define mmPA_SC_AA_CONFIG 0x2301 +#define mmPA_SC_AA_MASK 0x2312 +#define mmPA_SC_LINE_STIPPLE 0x2283 +#define mmPA_SC_LINE_CNTL 0x2300 +#define mmPA_SC_WINDOW_SCISSOR_TL 0x2081 +#define mmPA_SC_WINDOW_SCISSOR_BR 0x2082 +#define mmPA_SC_SCREEN_SCISSOR_TL 0x200E +#define mmPA_SC_SCREEN_SCISSOR_BR 0x200F +#define mmPA_SC_VIZ_QUERY 0x2293 +#define mmPA_SC_VIZ_QUERY_STATUS 0x0C44 +#define mmPA_SC_LINE_STIPPLE_STATE 0x0C40 +#define mmPA_SC_PERFCOUNTER0_SELECT 0x0C98 +#define mmPA_SC_PERFCOUNTER0_LOW 0x0C99 +#define mmPA_SC_PERFCOUNTER0_HI 0x0C9A +#define mmPA_CL_CNTL_STATUS 0x0C84 +#define mmPA_SU_CNTL_STATUS 0x0C94 +#define mmPA_SC_CNTL_STATUS 0x0CA4 +#define mmPA_SU_DEBUG_CNTL 0x0C80 +#define mmPA_SU_DEBUG_DATA 0x0C81 +#define mmPA_SC_DEBUG_CNTL 0x0C82 +#define mmPA_SC_DEBUG_DATA 0x0C83 + + +// Registers from VGT block + +#define mmGFX_COPY_STATE 0x21F4 +#define mmVGT_DRAW_INITIATOR 0x21FC +#define mmVGT_EVENT_INITIATOR 0x21F9 +#define mmVGT_DMA_BASE 0x21FA +#define mmVGT_DMA_SIZE 0x21FB +#define mmVGT_BIN_BASE 0x21FE +#define mmVGT_BIN_SIZE 0x21FF +#define mmVGT_CURRENT_BIN_ID_MIN 0x2207 +#define mmVGT_CURRENT_BIN_ID_MAX 0x2203 +#define mmVGT_IMMED_DATA 0x21FD +#define mmVGT_MAX_VTX_INDX 0x2100 +#define mmVGT_MIN_VTX_INDX 0x2101 +#define mmVGT_INDX_OFFSET 0x2102 +#define mmVGT_VERTEX_REUSE_BLOCK_CNTL 0x2316 +#define mmVGT_OUT_DEALLOC_CNTL 0x2317 +#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0x2103 +#define mmVGT_ENHANCE 0x2294 +#define mmVGT_VTX_VECT_EJECT_REG 0x0C2C +#define mmVGT_LAST_COPY_STATE 0x0C30 +#define mmVGT_DEBUG_CNTL 0x0C38 +#define mmVGT_DEBUG_DATA 0x0C39 +#define mmVGT_CNTL_STATUS 0x0C3C +#define mmVGT_CRC_SQ_DATA 0x0C3A +#define mmVGT_CRC_SQ_CTRL 0x0C3B +#define mmVGT_PERFCOUNTER0_SELECT 0x0C48 +#define mmVGT_PERFCOUNTER1_SELECT 0x0C49 +#define mmVGT_PERFCOUNTER2_SELECT 0x0C4A +#define mmVGT_PERFCOUNTER3_SELECT 0x0C4B +#define mmVGT_PERFCOUNTER0_LOW 0x0C4C +#define mmVGT_PERFCOUNTER1_LOW 0x0C4E +#define mmVGT_PERFCOUNTER2_LOW 0x0C50 +#define mmVGT_PERFCOUNTER3_LOW 0x0C52 +#define mmVGT_PERFCOUNTER0_HI 0x0C4D +#define mmVGT_PERFCOUNTER1_HI 0x0C4F +#define mmVGT_PERFCOUNTER2_HI 0x0C51 +#define mmVGT_PERFCOUNTER3_HI 0x0C53 + + +// Registers from TP block + +#define mmTC_CNTL_STATUS 0x0E00 +#define mmTCR_CHICKEN 0x0E02 +#define mmTCF_CHICKEN 0x0E03 +#define mmTCM_CHICKEN 0x0E04 +#define mmTCR_PERFCOUNTER0_SELECT 0x0E05 +#define mmTCR_PERFCOUNTER1_SELECT 0x0E08 +#define mmTCR_PERFCOUNTER0_HI 0x0E06 +#define mmTCR_PERFCOUNTER1_HI 0x0E09 +#define mmTCR_PERFCOUNTER0_LOW 0x0E07 +#define mmTCR_PERFCOUNTER1_LOW 0x0E0A +#define mmTP_TC_CLKGATE_CNTL 0x0E17 +#define mmTPC_CNTL_STATUS 0x0E18 +#define mmTPC_DEBUG0 0x0E19 +#define mmTPC_DEBUG1 0x0E1A +#define mmTPC_CHICKEN 0x0E1B +#define mmTP0_CNTL_STATUS 0x0E1C +#define mmTP0_DEBUG 0x0E1D +#define mmTP0_CHICKEN 0x0E1E +#define mmTP0_PERFCOUNTER0_SELECT 0x0E1F +#define mmTP0_PERFCOUNTER0_HI 0x0E20 +#define mmTP0_PERFCOUNTER0_LOW 0x0E21 +#define mmTP0_PERFCOUNTER1_SELECT 0x0E22 +#define mmTP0_PERFCOUNTER1_HI 0x0E23 +#define mmTP0_PERFCOUNTER1_LOW 0x0E24 +#define mmTCM_PERFCOUNTER0_SELECT 0x0E54 +#define mmTCM_PERFCOUNTER1_SELECT 0x0E57 +#define mmTCM_PERFCOUNTER0_HI 0x0E55 +#define mmTCM_PERFCOUNTER1_HI 0x0E58 +#define mmTCM_PERFCOUNTER0_LOW 0x0E56 +#define mmTCM_PERFCOUNTER1_LOW 0x0E59 +#define mmTCF_PERFCOUNTER0_SELECT 0x0E5A +#define mmTCF_PERFCOUNTER1_SELECT 0x0E5D +#define mmTCF_PERFCOUNTER2_SELECT 0x0E60 +#define mmTCF_PERFCOUNTER3_SELECT 0x0E63 +#define mmTCF_PERFCOUNTER4_SELECT 0x0E66 +#define mmTCF_PERFCOUNTER5_SELECT 0x0E69 +#define mmTCF_PERFCOUNTER6_SELECT 0x0E6C +#define mmTCF_PERFCOUNTER7_SELECT 0x0E6F +#define mmTCF_PERFCOUNTER8_SELECT 0x0E72 +#define mmTCF_PERFCOUNTER9_SELECT 0x0E75 +#define mmTCF_PERFCOUNTER10_SELECT 0x0E78 +#define mmTCF_PERFCOUNTER11_SELECT 0x0E7B +#define mmTCF_PERFCOUNTER0_HI 0x0E5B +#define mmTCF_PERFCOUNTER1_HI 0x0E5E +#define mmTCF_PERFCOUNTER2_HI 0x0E61 +#define mmTCF_PERFCOUNTER3_HI 0x0E64 +#define mmTCF_PERFCOUNTER4_HI 0x0E67 +#define mmTCF_PERFCOUNTER5_HI 0x0E6A +#define mmTCF_PERFCOUNTER6_HI 0x0E6D +#define mmTCF_PERFCOUNTER7_HI 0x0E70 +#define mmTCF_PERFCOUNTER8_HI 0x0E73 +#define mmTCF_PERFCOUNTER9_HI 0x0E76 +#define mmTCF_PERFCOUNTER10_HI 0x0E79 +#define mmTCF_PERFCOUNTER11_HI 0x0E7C +#define mmTCF_PERFCOUNTER0_LOW 0x0E5C +#define mmTCF_PERFCOUNTER1_LOW 0x0E5F +#define mmTCF_PERFCOUNTER2_LOW 0x0E62 +#define mmTCF_PERFCOUNTER3_LOW 0x0E65 +#define mmTCF_PERFCOUNTER4_LOW 0x0E68 +#define mmTCF_PERFCOUNTER5_LOW 0x0E6B +#define mmTCF_PERFCOUNTER6_LOW 0x0E6E +#define mmTCF_PERFCOUNTER7_LOW 0x0E71 +#define mmTCF_PERFCOUNTER8_LOW 0x0E74 +#define mmTCF_PERFCOUNTER9_LOW 0x0E77 +#define mmTCF_PERFCOUNTER10_LOW 0x0E7A +#define mmTCF_PERFCOUNTER11_LOW 0x0E7D +#define mmTCF_DEBUG 0x0EC0 +#define mmTCA_FIFO_DEBUG 0x0EC1 +#define mmTCA_PROBE_DEBUG 0x0EC2 +#define mmTCA_TPC_DEBUG 0x0EC3 +#define mmTCB_CORE_DEBUG 0x0EC4 +#define mmTCB_TAG0_DEBUG 0x0EC5 +#define mmTCB_TAG1_DEBUG 0x0EC6 +#define mmTCB_TAG2_DEBUG 0x0EC7 +#define mmTCB_TAG3_DEBUG 0x0EC8 +#define mmTCB_FETCH_GEN_SECTOR_WALKER0_DEBUG 0x0EC9 +#define mmTCB_FETCH_GEN_WALKER_DEBUG 0x0ECB +#define mmTCB_FETCH_GEN_PIPE0_DEBUG 0x0ECC +#define mmTCD_INPUT0_DEBUG 0x0ED0 +#define mmTCD_DEGAMMA_DEBUG 0x0ED4 +#define mmTCD_DXTMUX_SCTARB_DEBUG 0x0ED5 +#define mmTCD_DXTC_ARB_DEBUG 0x0ED6 +#define mmTCD_STALLS_DEBUG 0x0ED7 +#define mmTCO_STALLS_DEBUG 0x0EE0 +#define mmTCO_QUAD0_DEBUG0 0x0EE1 +#define mmTCO_QUAD0_DEBUG1 0x0EE2 + + +// Registers from TC block + + + +// Registers from SQ block + +#define mmSQ_GPR_MANAGEMENT 0x0D00 +#define mmSQ_FLOW_CONTROL 0x0D01 +#define mmSQ_INST_STORE_MANAGMENT 0x0D02 +#define mmSQ_RESOURCE_MANAGMENT 0x0D03 +#define mmSQ_EO_RT 0x0D04 +#define mmSQ_DEBUG_MISC 0x0D05 +#define mmSQ_ACTIVITY_METER_CNTL 0x0D06 +#define mmSQ_ACTIVITY_METER_STATUS 0x0D07 +#define mmSQ_INPUT_ARB_PRIORITY 0x0D08 +#define mmSQ_THREAD_ARB_PRIORITY 0x0D09 +#define mmSQ_DEBUG_INPUT_FSM 0x0DAE +#define mmSQ_DEBUG_CONST_MGR_FSM 0x0DAF +#define mmSQ_DEBUG_TP_FSM 0x0DB0 +#define mmSQ_DEBUG_FSM_ALU_0 0x0DB1 +#define mmSQ_DEBUG_FSM_ALU_1 0x0DB2 +#define mmSQ_DEBUG_EXP_ALLOC 0x0DB3 +#define mmSQ_DEBUG_PTR_BUFF 0x0DB4 +#define mmSQ_DEBUG_GPR_VTX 0x0DB5 +#define mmSQ_DEBUG_GPR_PIX 0x0DB6 +#define mmSQ_DEBUG_TB_STATUS_SEL 0x0DB7 +#define mmSQ_DEBUG_VTX_TB_0 0x0DB8 +#define mmSQ_DEBUG_VTX_TB_1 0x0DB9 +#define mmSQ_DEBUG_VTX_TB_STATUS_REG 0x0DBA +#define mmSQ_DEBUG_VTX_TB_STATE_MEM 0x0DBB +#define mmSQ_DEBUG_PIX_TB_0 0x0DBC +#define mmSQ_DEBUG_PIX_TB_STATUS_REG_0 0x0DBD +#define mmSQ_DEBUG_PIX_TB_STATUS_REG_1 0x0DBE +#define mmSQ_DEBUG_PIX_TB_STATUS_REG_2 0x0DBF +#define mmSQ_DEBUG_PIX_TB_STATUS_REG_3 0x0DC0 +#define mmSQ_DEBUG_PIX_TB_STATE_MEM 0x0DC1 +#define mmSQ_PERFCOUNTER0_SELECT 0x0DC8 +#define mmSQ_PERFCOUNTER1_SELECT 0x0DC9 +#define mmSQ_PERFCOUNTER2_SELECT 0x0DCA +#define mmSQ_PERFCOUNTER3_SELECT 0x0DCB +#define mmSQ_PERFCOUNTER0_LOW 0x0DCC +#define mmSQ_PERFCOUNTER0_HI 0x0DCD +#define mmSQ_PERFCOUNTER1_LOW 0x0DCE +#define mmSQ_PERFCOUNTER1_HI 0x0DCF +#define mmSQ_PERFCOUNTER2_LOW 0x0DD0 +#define mmSQ_PERFCOUNTER2_HI 0x0DD1 +#define mmSQ_PERFCOUNTER3_LOW 0x0DD2 +#define mmSQ_PERFCOUNTER3_HI 0x0DD3 +#define mmSX_PERFCOUNTER0_SELECT 0x0DD4 +#define mmSX_PERFCOUNTER0_LOW 0x0DD8 +#define mmSX_PERFCOUNTER0_HI 0x0DD9 +#define mmSQ_INSTRUCTION_ALU_0 0x5000 +#define mmSQ_INSTRUCTION_ALU_1 0x5001 +#define mmSQ_INSTRUCTION_ALU_2 0x5002 +#define mmSQ_INSTRUCTION_CF_EXEC_0 0x5080 +#define mmSQ_INSTRUCTION_CF_EXEC_1 0x5081 +#define mmSQ_INSTRUCTION_CF_EXEC_2 0x5082 +#define mmSQ_INSTRUCTION_CF_LOOP_0 0x5083 +#define mmSQ_INSTRUCTION_CF_LOOP_1 0x5084 +#define mmSQ_INSTRUCTION_CF_LOOP_2 0x5085 +#define mmSQ_INSTRUCTION_CF_JMP_CALL_0 0x5086 +#define mmSQ_INSTRUCTION_CF_JMP_CALL_1 0x5087 +#define mmSQ_INSTRUCTION_CF_JMP_CALL_2 0x5088 +#define mmSQ_INSTRUCTION_CF_ALLOC_0 0x5089 +#define mmSQ_INSTRUCTION_CF_ALLOC_1 0x508A +#define mmSQ_INSTRUCTION_CF_ALLOC_2 0x508B +#define mmSQ_INSTRUCTION_TFETCH_0 0x5043 +#define mmSQ_INSTRUCTION_TFETCH_1 0x5044 +#define mmSQ_INSTRUCTION_TFETCH_2 0x5045 +#define mmSQ_INSTRUCTION_VFETCH_0 0x5040 +#define mmSQ_INSTRUCTION_VFETCH_1 0x5041 +#define mmSQ_INSTRUCTION_VFETCH_2 0x5042 +#define mmSQ_CONSTANT_0 0x4000 +#define mmSQ_CONSTANT_1 0x4001 +#define mmSQ_CONSTANT_2 0x4002 +#define mmSQ_CONSTANT_3 0x4003 +#define mmSQ_FETCH_0 0x4800 +#define mmSQ_FETCH_1 0x4801 +#define mmSQ_FETCH_2 0x4802 +#define mmSQ_FETCH_3 0x4803 +#define mmSQ_FETCH_4 0x4804 +#define mmSQ_FETCH_5 0x4805 +#define mmSQ_CONSTANT_VFETCH_0 0x4806 +#define mmSQ_CONSTANT_VFETCH_1 0x4808 +#define mmSQ_CONSTANT_T2 0x480C +#define mmSQ_CONSTANT_T3 0x4812 +#define mmSQ_CF_BOOLEANS 0x4900 +#define mmSQ_CF_LOOP 0x4908 +#define mmSQ_CONSTANT_RT_0 0x4940 +#define mmSQ_CONSTANT_RT_1 0x4941 +#define mmSQ_CONSTANT_RT_2 0x4942 +#define mmSQ_CONSTANT_RT_3 0x4943 +#define mmSQ_FETCH_RT_0 0x4D40 +#define mmSQ_FETCH_RT_1 0x4D41 +#define mmSQ_FETCH_RT_2 0x4D42 +#define mmSQ_FETCH_RT_3 0x4D43 +#define mmSQ_FETCH_RT_4 0x4D44 +#define mmSQ_FETCH_RT_5 0x4D45 +#define mmSQ_CF_RT_BOOLEANS 0x4E00 +#define mmSQ_CF_RT_LOOP 0x4E14 +#define mmSQ_VS_PROGRAM 0x21F7 +#define mmSQ_PS_PROGRAM 0x21F6 +#define mmSQ_CF_PROGRAM_SIZE 0x2315 +#define mmSQ_INTERPOLATOR_CNTL 0x2182 +#define mmSQ_PROGRAM_CNTL 0x2180 +#define mmSQ_WRAPPING_0 0x2183 +#define mmSQ_WRAPPING_1 0x2184 +#define mmSQ_VS_CONST 0x2307 +#define mmSQ_PS_CONST 0x2308 +#define mmSQ_CONTEXT_MISC 0x2181 +#define mmSQ_CF_RD_BASE 0x21F5 +#define mmSQ_DEBUG_MISC_0 0x2309 +#define mmSQ_DEBUG_MISC_1 0x230A + + +// Registers from SX block + + + +// Registers from MH block + +#define mmMH_ARBITER_CONFIG 0x0A40 +#define mmMH_CLNT_AXI_ID_REUSE 0x0A41 +#define mmMH_INTERRUPT_MASK 0x0A42 +#define mmMH_INTERRUPT_STATUS 0x0A43 +#define mmMH_INTERRUPT_CLEAR 0x0A44 +#define mmMH_AXI_ERROR 0x0A45 +#define mmMH_PERFCOUNTER0_SELECT 0x0A46 +#define mmMH_PERFCOUNTER1_SELECT 0x0A4A +#define mmMH_PERFCOUNTER0_CONFIG 0x0A47 +#define mmMH_PERFCOUNTER1_CONFIG 0x0A4B +#define mmMH_PERFCOUNTER0_LOW 0x0A48 +#define mmMH_PERFCOUNTER1_LOW 0x0A4C +#define mmMH_PERFCOUNTER0_HI 0x0A49 +#define mmMH_PERFCOUNTER1_HI 0x0A4D +#define mmMH_DEBUG_CTRL 0x0A4E +#define mmMH_DEBUG_DATA 0x0A4F +#define mmMH_MMU_CONFIG 0x0040 +#define mmMH_MMU_VA_RANGE 0x0041 +#define mmMH_MMU_PT_BASE 0x0042 +#define mmMH_MMU_PAGE_FAULT 0x0043 +#define mmMH_MMU_TRAN_ERROR 0x0044 +#define mmMH_MMU_INVALIDATE 0x0045 +#define mmMH_MMU_MPU_BASE 0x0046 +#define mmMH_MMU_MPU_END 0x0047 + + +// Registers from RBBM block + +#define mmWAIT_UNTIL 0x05C8 +#define mmRBBM_ISYNC_CNTL 0x05C9 +#define mmRBBM_STATUS 0x05D0 +#define mmRBBM_DSPLY 0x0391 +#define mmRBBM_RENDER_LATEST 0x0392 +#define mmRBBM_RTL_RELEASE 0x0000 +#define mmRBBM_PATCH_RELEASE 0x0001 +#define mmRBBM_AUXILIARY_CONFIG 0x0002 +#define mmRBBM_PERIPHID0 0x03F8 +#define mmRBBM_PERIPHID1 0x03F9 +#define mmRBBM_PERIPHID2 0x03FA +#define mmRBBM_PERIPHID3 0x03FB +#define mmRBBM_CNTL 0x003B +#define mmRBBM_SKEW_CNTL 0x003D +#define mmRBBM_SOFT_RESET 0x003C +#define mmRBBM_PM_OVERRIDE1 0x039C +#define mmRBBM_PM_OVERRIDE2 0x039D +#define mmGC_SYS_IDLE 0x039E +#define mmNQWAIT_UNTIL 0x0394 +#define mmRBBM_DEBUG 0x039B +#define mmRBBM_READ_ERROR 0x03B3 +#define mmRBBM_WAIT_IDLE_CLOCKS 0x03B2 +#define mmRBBM_INT_CNTL 0x03B4 +#define mmRBBM_INT_STATUS 0x03B5 +#define mmRBBM_INT_ACK 0x03B6 +#define mmMASTER_INT_SIGNAL 0x03B7 +#define mmRBBM_PERFCOUNTER1_SELECT 0x0395 +#define mmRBBM_PERFCOUNTER1_LO 0x0397 +#define mmRBBM_PERFCOUNTER1_HI 0x0398 + + +// Registers from CP block + +#define mmCP_RB_BASE 0x01C0 +#define mmCP_RB_CNTL 0x01C1 +#define mmCP_RB_RPTR_ADDR 0x01C3 +#define mmCP_RB_RPTR 0x01C4 +#define mmCP_RB_RPTR_WR 0x01C7 +#define mmCP_RB_WPTR 0x01C5 +#define mmCP_RB_WPTR_DELAY 0x01C6 +#define mmCP_RB_WPTR_BASE 0x01C8 +#define mmCP_IB1_BASE 0x01CC +#define mmCP_IB1_BUFSZ 0x01CD +#define mmCP_IB2_BASE 0x01CE +#define mmCP_IB2_BUFSZ 0x01CF +#define mmCP_ST_BASE 0x044D +#define mmCP_ST_BUFSZ 0x044E +#define mmCP_QUEUE_THRESHOLDS 0x01D5 +#define mmCP_MEQ_THRESHOLDS 0x01D6 +#define mmCP_CSQ_AVAIL 0x01D7 +#define mmCP_STQ_AVAIL 0x01D8 +#define mmCP_MEQ_AVAIL 0x01D9 +#define mmCP_CSQ_RB_STAT 0x01FD +#define mmCP_CSQ_IB1_STAT 0x01FE +#define mmCP_CSQ_IB2_STAT 0x01FF +#define mmCP_NON_PREFETCH_CNTRS 0x0440 +#define mmCP_STQ_ST_STAT 0x0443 +#define mmCP_MEQ_STAT 0x044F +#define mmCP_MIU_TAG_STAT 0x0452 +#define mmCP_CMD_INDEX 0x01DA +#define mmCP_CMD_DATA 0x01DB +#define mmCP_ME_CNTL 0x01F6 +#define mmCP_ME_STATUS 0x01F7 +#define mmCP_ME_RAM_WADDR 0x01F8 +#define mmCP_ME_RAM_RADDR 0x01F9 +#define mmCP_ME_RAM_DATA 0x01FA +#define mmCP_ME_RDADDR 0x01EA +#define mmCP_DEBUG 0x01FC +#define mmSCRATCH_REG0 0x0578 +#define mmGUI_SCRATCH_REG0 0x0578 +#define mmSCRATCH_REG1 0x0579 +#define mmGUI_SCRATCH_REG1 0x0579 +#define mmSCRATCH_REG2 0x057A +#define mmGUI_SCRATCH_REG2 0x057A +#define mmSCRATCH_REG3 0x057B +#define mmGUI_SCRATCH_REG3 0x057B +#define mmSCRATCH_REG4 0x057C +#define mmGUI_SCRATCH_REG4 0x057C +#define mmSCRATCH_REG5 0x057D +#define mmGUI_SCRATCH_REG5 0x057D +#define mmSCRATCH_REG6 0x057E +#define mmGUI_SCRATCH_REG6 0x057E +#define mmSCRATCH_REG7 0x057F +#define mmGUI_SCRATCH_REG7 0x057F +#define mmSCRATCH_UMSK 0x01DC +#define mmSCRATCH_ADDR 0x01DD +#define mmCP_ME_VS_EVENT_SRC 0x0600 +#define mmCP_ME_VS_EVENT_ADDR 0x0601 +#define mmCP_ME_VS_EVENT_DATA 0x0602 +#define mmCP_ME_VS_EVENT_ADDR_SWM 0x0603 +#define mmCP_ME_VS_EVENT_DATA_SWM 0x0604 +#define mmCP_ME_PS_EVENT_SRC 0x0605 +#define mmCP_ME_PS_EVENT_ADDR 0x0606 +#define mmCP_ME_PS_EVENT_DATA 0x0607 +#define mmCP_ME_PS_EVENT_ADDR_SWM 0x0608 +#define mmCP_ME_PS_EVENT_DATA_SWM 0x0609 +#define mmCP_ME_CF_EVENT_SRC 0x060A +#define mmCP_ME_CF_EVENT_ADDR 0x060B +#define mmCP_ME_CF_EVENT_DATA 0x060C +#define mmCP_ME_NRT_ADDR 0x060D +#define mmCP_ME_NRT_DATA 0x060E +#define mmCP_ME_VS_FETCH_DONE_SRC 0x0612 +#define mmCP_ME_VS_FETCH_DONE_ADDR 0x0613 +#define mmCP_ME_VS_FETCH_DONE_DATA 0x0614 +#define mmCP_INT_CNTL 0x01F2 +#define mmCP_INT_STATUS 0x01F3 +#define mmCP_INT_ACK 0x01F4 +#define mmCP_PFP_UCODE_ADDR 0x045F +#define mmCP_PFP_UCODE_DATA 0x0460 +#define mmCP_PERFMON_CNTL 0x01F5 +#define mmCP_PERFCOUNTER_SELECT 0x01E6 +#define mmCP_PERFCOUNTER_LO 0x01E7 +#define mmCP_PERFCOUNTER_HI 0x01E8 +#define mmCP_BIN_MASK_LO 0x0454 +#define mmCP_BIN_MASK_HI 0x0455 +#define mmCP_BIN_SELECT_LO 0x0456 +#define mmCP_BIN_SELECT_HI 0x0457 +#define mmCP_NV_FLAGS_0 0x01EE +#define mmCP_NV_FLAGS_1 0x01EF +#define mmCP_NV_FLAGS_2 0x01F0 +#define mmCP_NV_FLAGS_3 0x01F1 +#define mmCP_STATE_DEBUG_INDEX 0x01EC +#define mmCP_STATE_DEBUG_DATA 0x01ED +#define mmCP_PROG_COUNTER 0x044B +#define mmCP_STAT 0x047F +#define mmBIOS_0_SCRATCH 0x0004 +#define mmBIOS_1_SCRATCH 0x0005 +#define mmBIOS_2_SCRATCH 0x0006 +#define mmBIOS_3_SCRATCH 0x0007 +#define mmBIOS_4_SCRATCH 0x0008 +#define mmBIOS_5_SCRATCH 0x0009 +#define mmBIOS_6_SCRATCH 0x000A +#define mmBIOS_7_SCRATCH 0x000B +#define mmBIOS_8_SCRATCH 0x0580 +#define mmBIOS_9_SCRATCH 0x0581 +#define mmBIOS_10_SCRATCH 0x0582 +#define mmBIOS_11_SCRATCH 0x0583 +#define mmBIOS_12_SCRATCH 0x0584 +#define mmBIOS_13_SCRATCH 0x0585 +#define mmBIOS_14_SCRATCH 0x0586 +#define mmBIOS_15_SCRATCH 0x0587 +#define mmCOHER_SIZE_PM4 0x0A29 +#define mmCOHER_BASE_PM4 0x0A2A +#define mmCOHER_STATUS_PM4 0x0A2B +#define mmCOHER_SIZE_HOST 0x0A2F +#define mmCOHER_BASE_HOST 0x0A30 +#define mmCOHER_STATUS_HOST 0x0A31 +#define mmCOHER_DEST_BASE_0 0x2006 +#define mmCOHER_DEST_BASE_1 0x2007 +#define mmCOHER_DEST_BASE_2 0x2008 +#define mmCOHER_DEST_BASE_3 0x2009 +#define mmCOHER_DEST_BASE_4 0x200A +#define mmCOHER_DEST_BASE_5 0x200B +#define mmCOHER_DEST_BASE_6 0x200C +#define mmCOHER_DEST_BASE_7 0x200D + + +// Registers from SC block + + + +// Registers from BC block + +#define mmRB_SURFACE_INFO 0x2000 +#define mmRB_COLOR_INFO 0x2001 +#define mmRB_DEPTH_INFO 0x2002 +#define mmRB_STENCILREFMASK 0x210D +#define mmRB_ALPHA_REF 0x210E +#define mmRB_COLOR_MASK 0x2104 +#define mmRB_BLEND_RED 0x2105 +#define mmRB_BLEND_GREEN 0x2106 +#define mmRB_BLEND_BLUE 0x2107 +#define mmRB_BLEND_ALPHA 0x2108 +#define mmRB_FOG_COLOR 0x2109 +#define mmRB_STENCILREFMASK_BF 0x210C +#define mmRB_DEPTHCONTROL 0x2200 +#define mmRB_BLENDCONTROL 0x2201 +#define mmRB_COLORCONTROL 0x2202 +#define mmRB_MODECONTROL 0x2208 +#define mmRB_COLOR_DEST_MASK 0x2326 +#define mmRB_COPY_CONTROL 0x2318 +#define mmRB_COPY_DEST_BASE 0x2319 +#define mmRB_COPY_DEST_PITCH 0x231A +#define mmRB_COPY_DEST_INFO 0x231B +#define mmRB_COPY_DEST_PIXEL_OFFSET 0x231C +#define mmRB_DEPTH_CLEAR 0x231D +#define mmRB_SAMPLE_COUNT_CTL 0x2324 +#define mmRB_SAMPLE_COUNT_ADDR 0x2325 +#define mmRB_BC_CONTROL 0x0F01 +#define mmRB_EDRAM_INFO 0x0F02 +#define mmRB_CRC_RD_PORT 0x0F0C +#define mmRB_CRC_CONTROL 0x0F0D +#define mmRB_CRC_MASK 0x0F0E +#define mmRB_PERFCOUNTER0_SELECT 0x0F04 +#define mmRB_PERFCOUNTER0_LOW 0x0F08 +#define mmRB_PERFCOUNTER0_HI 0x0F09 +#define mmRB_TOTAL_SAMPLES 0x0F0F +#define mmRB_ZPASS_SAMPLES 0x0F10 +#define mmRB_ZFAIL_SAMPLES 0x0F11 +#define mmRB_SFAIL_SAMPLES 0x0F12 +#define mmRB_DEBUG_0 0x0F26 +#define mmRB_DEBUG_1 0x0F27 +#define mmRB_DEBUG_2 0x0F28 +#define mmRB_DEBUG_3 0x0F29 +#define mmRB_DEBUG_4 0x0F2A +#define mmRB_FLAG_CONTROL 0x0F2B +#define mmBC_DUMMY_CRAYRB_ENUMS 0x0F15 +#define mmBC_DUMMY_CRAYRB_MOREENUMS 0x0F16 +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_random.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_random.h new file mode 100644 index 000000000000..7e293b371bcd --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_random.h @@ -0,0 +1,221 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_RANDOM_HEADER) +#define _yamato_RANDOM_HEADER + +/************************************************************* + * THIS FILE IS AUTOMATICALLY CREATED. DO NOT EDIT THIS FILE. + *************************************************************/ +/******************************************************* + * PA Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * VGT Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * TP Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * TC Enums + *******************************************************/ +/******************************************************* + * SQ Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * SX Enums + *******************************************************/ +/******************************************************* + * MH Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * RBBM Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * CP Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * SC Enums + *******************************************************/ +/******************************************************* + * BC Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +#endif /*_yamato_RANDOM_HEADER*/ + diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_registers.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_registers.h new file mode 100644 index 000000000000..b021d446a229 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_registers.h @@ -0,0 +1,13962 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_REG_HEADER) +#define _yamato_REG_HEADER + + union PA_CL_VPORT_XSCALE { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_XSCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_XSCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_XOFFSET { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_XOFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_XOFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_YSCALE { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_YSCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_YSCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_YOFFSET { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_YOFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_YOFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_ZSCALE { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_ZSCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_ZSCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_ZOFFSET { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_ZOFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_ZOFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VTE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_X_SCALE_ENA : 1; + unsigned int VPORT_X_OFFSET_ENA : 1; + unsigned int VPORT_Y_SCALE_ENA : 1; + unsigned int VPORT_Y_OFFSET_ENA : 1; + unsigned int VPORT_Z_SCALE_ENA : 1; + unsigned int VPORT_Z_OFFSET_ENA : 1; + unsigned int : 2; + unsigned int VTX_XY_FMT : 1; + unsigned int VTX_Z_FMT : 1; + unsigned int VTX_W0_FMT : 1; + unsigned int PERFCOUNTER_REF : 1; + unsigned int : 20; +#else /* !defined(qLittleEndian) */ + unsigned int : 20; + unsigned int PERFCOUNTER_REF : 1; + unsigned int VTX_W0_FMT : 1; + unsigned int VTX_Z_FMT : 1; + unsigned int VTX_XY_FMT : 1; + unsigned int : 2; + unsigned int VPORT_Z_OFFSET_ENA : 1; + unsigned int VPORT_Z_SCALE_ENA : 1; + unsigned int VPORT_Y_OFFSET_ENA : 1; + unsigned int VPORT_Y_SCALE_ENA : 1; + unsigned int VPORT_X_OFFSET_ENA : 1; + unsigned int VPORT_X_SCALE_ENA : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_CLIP_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int : 16; + unsigned int CLIP_DISABLE : 1; + unsigned int : 1; + unsigned int BOUNDARY_EDGE_FLAG_ENA : 1; + unsigned int DX_CLIP_SPACE_DEF : 1; + unsigned int DIS_CLIP_ERR_DETECT : 1; + unsigned int VTX_KILL_OR : 1; + unsigned int XY_NAN_RETAIN : 1; + unsigned int Z_NAN_RETAIN : 1; + unsigned int W_NAN_RETAIN : 1; + unsigned int : 7; +#else /* !defined(qLittleEndian) */ + unsigned int : 7; + unsigned int W_NAN_RETAIN : 1; + unsigned int Z_NAN_RETAIN : 1; + unsigned int XY_NAN_RETAIN : 1; + unsigned int VTX_KILL_OR : 1; + unsigned int DIS_CLIP_ERR_DETECT : 1; + unsigned int DX_CLIP_SPACE_DEF : 1; + unsigned int BOUNDARY_EDGE_FLAG_ENA : 1; + unsigned int : 1; + unsigned int CLIP_DISABLE : 1; + unsigned int : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_GB_VERT_CLIP_ADJ { + struct { +#if defined(qLittleEndian) + unsigned int DATA_REGISTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA_REGISTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_GB_VERT_DISC_ADJ { + struct { +#if defined(qLittleEndian) + unsigned int DATA_REGISTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA_REGISTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_GB_HORZ_CLIP_ADJ { + struct { +#if defined(qLittleEndian) + unsigned int DATA_REGISTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA_REGISTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_GB_HORZ_DISC_ADJ { + struct { +#if defined(qLittleEndian) + unsigned int DATA_REGISTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA_REGISTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_ENHANCE { + struct { +#if defined(qLittleEndian) + unsigned int CLIP_VTX_REORDER_ENA : 1; + unsigned int : 27; + unsigned int ECO_SPARE3 : 1; + unsigned int ECO_SPARE2 : 1; + unsigned int ECO_SPARE1 : 1; + unsigned int ECO_SPARE0 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int ECO_SPARE0 : 1; + unsigned int ECO_SPARE1 : 1; + unsigned int ECO_SPARE2 : 1; + unsigned int ECO_SPARE3 : 1; + unsigned int : 27; + unsigned int CLIP_VTX_REORDER_ENA : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_ENHANCE { + struct { +#if defined(qLittleEndian) + unsigned int : 28; + unsigned int ECO_SPARE3 : 1; + unsigned int ECO_SPARE2 : 1; + unsigned int ECO_SPARE1 : 1; + unsigned int ECO_SPARE0 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int ECO_SPARE0 : 1; + unsigned int ECO_SPARE1 : 1; + unsigned int ECO_SPARE2 : 1; + unsigned int ECO_SPARE3 : 1; + unsigned int : 28; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_VTX_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int PIX_CENTER : 1; + unsigned int ROUND_MODE : 2; + unsigned int QUANT_MODE : 3; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int QUANT_MODE : 3; + unsigned int ROUND_MODE : 2; + unsigned int PIX_CENTER : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POINT_SIZE { + struct { +#if defined(qLittleEndian) + unsigned int HEIGHT : 16; + unsigned int WIDTH : 16; +#else /* !defined(qLittleEndian) */ + unsigned int WIDTH : 16; + unsigned int HEIGHT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POINT_MINMAX { + struct { +#if defined(qLittleEndian) + unsigned int MIN_SIZE : 16; + unsigned int MAX_SIZE : 16; +#else /* !defined(qLittleEndian) */ + unsigned int MAX_SIZE : 16; + unsigned int MIN_SIZE : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_LINE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int WIDTH : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int WIDTH : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_SC_MODE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int CULL_FRONT : 1; + unsigned int CULL_BACK : 1; + unsigned int FACE : 1; + unsigned int POLY_MODE : 2; + unsigned int POLYMODE_FRONT_PTYPE : 3; + unsigned int POLYMODE_BACK_PTYPE : 3; + unsigned int POLY_OFFSET_FRONT_ENABLE : 1; + unsigned int POLY_OFFSET_BACK_ENABLE : 1; + unsigned int POLY_OFFSET_PARA_ENABLE : 1; + unsigned int : 1; + unsigned int MSAA_ENABLE : 1; + unsigned int VTX_WINDOW_OFFSET_ENABLE : 1; + unsigned int : 1; + unsigned int LINE_STIPPLE_ENABLE : 1; + unsigned int PROVOKING_VTX_LAST : 1; + unsigned int PERSP_CORR_DIS : 1; + unsigned int MULTI_PRIM_IB_ENA : 1; + unsigned int : 1; + unsigned int QUAD_ORDER_ENABLE : 1; + unsigned int : 1; + unsigned int WAIT_RB_IDLE_ALL_TRI : 1; + unsigned int WAIT_RB_IDLE_FIRST_TRI_NEW_STATE : 1; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int WAIT_RB_IDLE_FIRST_TRI_NEW_STATE : 1; + unsigned int WAIT_RB_IDLE_ALL_TRI : 1; + unsigned int : 1; + unsigned int QUAD_ORDER_ENABLE : 1; + unsigned int : 1; + unsigned int MULTI_PRIM_IB_ENA : 1; + unsigned int PERSP_CORR_DIS : 1; + unsigned int PROVOKING_VTX_LAST : 1; + unsigned int LINE_STIPPLE_ENABLE : 1; + unsigned int : 1; + unsigned int VTX_WINDOW_OFFSET_ENABLE : 1; + unsigned int MSAA_ENABLE : 1; + unsigned int : 1; + unsigned int POLY_OFFSET_PARA_ENABLE : 1; + unsigned int POLY_OFFSET_BACK_ENABLE : 1; + unsigned int POLY_OFFSET_FRONT_ENABLE : 1; + unsigned int POLYMODE_BACK_PTYPE : 3; + unsigned int POLYMODE_FRONT_PTYPE : 3; + unsigned int POLY_MODE : 2; + unsigned int FACE : 1; + unsigned int CULL_BACK : 1; + unsigned int CULL_FRONT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POLY_OFFSET_FRONT_SCALE { + struct { +#if defined(qLittleEndian) + unsigned int SCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POLY_OFFSET_FRONT_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int OFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int OFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POLY_OFFSET_BACK_SCALE { + struct { +#if defined(qLittleEndian) + unsigned int SCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POLY_OFFSET_BACK_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int OFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int OFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER2_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER3_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER2_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER2_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER3_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER3_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_WINDOW_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int WINDOW_X_OFFSET : 15; + unsigned int : 1; + unsigned int WINDOW_Y_OFFSET : 15; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int WINDOW_Y_OFFSET : 15; + unsigned int : 1; + unsigned int WINDOW_X_OFFSET : 15; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_AA_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int MSAA_NUM_SAMPLES : 3; + unsigned int : 10; + unsigned int MAX_SAMPLE_DIST : 4; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int MAX_SAMPLE_DIST : 4; + unsigned int : 10; + unsigned int MSAA_NUM_SAMPLES : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_AA_MASK { + struct { +#if defined(qLittleEndian) + unsigned int AA_MASK : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int AA_MASK : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_LINE_STIPPLE { + struct { +#if defined(qLittleEndian) + unsigned int LINE_PATTERN : 16; + unsigned int REPEAT_COUNT : 8; + unsigned int : 4; + unsigned int PATTERN_BIT_ORDER : 1; + unsigned int AUTO_RESET_CNTL : 2; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int AUTO_RESET_CNTL : 2; + unsigned int PATTERN_BIT_ORDER : 1; + unsigned int : 4; + unsigned int REPEAT_COUNT : 8; + unsigned int LINE_PATTERN : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_LINE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int BRES_CNTL : 8; + unsigned int USE_BRES_CNTL : 1; + unsigned int EXPAND_LINE_WIDTH : 1; + unsigned int LAST_PIXEL : 1; + unsigned int : 21; +#else /* !defined(qLittleEndian) */ + unsigned int : 21; + unsigned int LAST_PIXEL : 1; + unsigned int EXPAND_LINE_WIDTH : 1; + unsigned int USE_BRES_CNTL : 1; + unsigned int BRES_CNTL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_WINDOW_SCISSOR_TL { + struct { +#if defined(qLittleEndian) + unsigned int TL_X : 14; + unsigned int : 2; + unsigned int TL_Y : 14; + unsigned int : 1; + unsigned int WINDOW_OFFSET_DISABLE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int WINDOW_OFFSET_DISABLE : 1; + unsigned int : 1; + unsigned int TL_Y : 14; + unsigned int : 2; + unsigned int TL_X : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_WINDOW_SCISSOR_BR { + struct { +#if defined(qLittleEndian) + unsigned int BR_X : 14; + unsigned int : 2; + unsigned int BR_Y : 14; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int BR_Y : 14; + unsigned int : 2; + unsigned int BR_X : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_SCREEN_SCISSOR_TL { + struct { +#if defined(qLittleEndian) + unsigned int TL_X : 15; + unsigned int : 1; + unsigned int TL_Y : 15; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int TL_Y : 15; + unsigned int : 1; + unsigned int TL_X : 15; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_SCREEN_SCISSOR_BR { + struct { +#if defined(qLittleEndian) + unsigned int BR_X : 15; + unsigned int : 1; + unsigned int BR_Y : 15; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int BR_Y : 15; + unsigned int : 1; + unsigned int BR_X : 15; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_VIZ_QUERY { + struct { +#if defined(qLittleEndian) + unsigned int VIZ_QUERY_ENA : 1; + unsigned int VIZ_QUERY_ID : 5; + unsigned int : 1; + unsigned int KILL_PIX_POST_EARLY_Z : 1; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int KILL_PIX_POST_EARLY_Z : 1; + unsigned int : 1; + unsigned int VIZ_QUERY_ID : 5; + unsigned int VIZ_QUERY_ENA : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_VIZ_QUERY_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int STATUS_BITS : 32; +#else /* !defined(qLittleEndian) */ + unsigned int STATUS_BITS : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_LINE_STIPPLE_STATE { + struct { +#if defined(qLittleEndian) + unsigned int CURRENT_PTR : 4; + unsigned int : 4; + unsigned int CURRENT_COUNT : 8; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int CURRENT_COUNT : 8; + unsigned int : 4; + unsigned int CURRENT_PTR : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int : 31; + unsigned int CL_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int CL_BUSY : 1; + unsigned int : 31; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int : 31; + unsigned int SU_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int SU_BUSY : 1; + unsigned int : 31; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int : 31; + unsigned int SC_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int SC_BUSY : 1; + unsigned int : 31; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_DEBUG_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int SU_DEBUG_INDX : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int SU_DEBUG_INDX : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG00 { + struct { +#if defined(qLittleEndian) + unsigned int clip_ga_bc_fifo_write : 1; + unsigned int clip_ga_bc_fifo_full : 1; + unsigned int clip_to_ga_fifo_write : 1; + unsigned int clip_to_ga_fifo_full : 1; + unsigned int primic_to_clprim_fifo_empty : 1; + unsigned int primic_to_clprim_fifo_full : 1; + unsigned int clip_to_outsm_fifo_empty : 1; + unsigned int clip_to_outsm_fifo_full : 1; + unsigned int vgt_to_clipp_fifo_empty : 1; + unsigned int vgt_to_clipp_fifo_full : 1; + unsigned int vgt_to_clips_fifo_empty : 1; + unsigned int vgt_to_clips_fifo_full : 1; + unsigned int clipcode_fifo_fifo_empty : 1; + unsigned int clipcode_fifo_full : 1; + unsigned int vte_out_clip_fifo_fifo_empty : 1; + unsigned int vte_out_clip_fifo_fifo_full : 1; + unsigned int vte_out_orig_fifo_fifo_empty : 1; + unsigned int vte_out_orig_fifo_fifo_full : 1; + unsigned int ccgen_to_clipcc_fifo_empty : 1; + unsigned int ccgen_to_clipcc_fifo_full : 1; + unsigned int ALWAYS_ZERO : 12; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO : 12; + unsigned int ccgen_to_clipcc_fifo_full : 1; + unsigned int ccgen_to_clipcc_fifo_empty : 1; + unsigned int vte_out_orig_fifo_fifo_full : 1; + unsigned int vte_out_orig_fifo_fifo_empty : 1; + unsigned int vte_out_clip_fifo_fifo_full : 1; + unsigned int vte_out_clip_fifo_fifo_empty : 1; + unsigned int clipcode_fifo_full : 1; + unsigned int clipcode_fifo_fifo_empty : 1; + unsigned int vgt_to_clips_fifo_full : 1; + unsigned int vgt_to_clips_fifo_empty : 1; + unsigned int vgt_to_clipp_fifo_full : 1; + unsigned int vgt_to_clipp_fifo_empty : 1; + unsigned int clip_to_outsm_fifo_full : 1; + unsigned int clip_to_outsm_fifo_empty : 1; + unsigned int primic_to_clprim_fifo_full : 1; + unsigned int primic_to_clprim_fifo_empty : 1; + unsigned int clip_to_ga_fifo_full : 1; + unsigned int clip_to_ga_fifo_write : 1; + unsigned int clip_ga_bc_fifo_full : 1; + unsigned int clip_ga_bc_fifo_write : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG01 { + struct { +#if defined(qLittleEndian) + unsigned int clip_to_outsm_end_of_packet : 1; + unsigned int clip_to_outsm_first_prim_of_slot : 1; + unsigned int clip_to_outsm_deallocate_slot : 3; + unsigned int clip_to_outsm_clipped_prim : 1; + unsigned int clip_to_outsm_null_primitive : 1; + unsigned int clip_to_outsm_vertex_store_indx_2 : 4; + unsigned int clip_to_outsm_vertex_store_indx_1 : 4; + unsigned int clip_to_outsm_vertex_store_indx_0 : 4; + unsigned int clip_vert_vte_valid : 3; + unsigned int vte_out_clip_rd_vertex_store_indx : 2; + unsigned int ALWAYS_ZERO : 8; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO : 8; + unsigned int vte_out_clip_rd_vertex_store_indx : 2; + unsigned int clip_vert_vte_valid : 3; + unsigned int clip_to_outsm_vertex_store_indx_0 : 4; + unsigned int clip_to_outsm_vertex_store_indx_1 : 4; + unsigned int clip_to_outsm_vertex_store_indx_2 : 4; + unsigned int clip_to_outsm_null_primitive : 1; + unsigned int clip_to_outsm_clipped_prim : 1; + unsigned int clip_to_outsm_deallocate_slot : 3; + unsigned int clip_to_outsm_first_prim_of_slot : 1; + unsigned int clip_to_outsm_end_of_packet : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG02 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO1 : 21; + unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : 3; + unsigned int ALWAYS_ZERO0 : 7; + unsigned int clipsm0_clprim_to_clip_prim_valid : 1; +#else /* !defined(qLittleEndian) */ + unsigned int clipsm0_clprim_to_clip_prim_valid : 1; + unsigned int ALWAYS_ZERO0 : 7; + unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : 3; + unsigned int ALWAYS_ZERO1 : 21; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG03 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO3 : 3; + unsigned int clipsm0_clprim_to_clip_clip_primitive : 1; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clipsm0_clprim_to_clip_null_primitive : 1; + unsigned int ALWAYS_ZERO1 : 12; + unsigned int clipsm0_clprim_to_clip_clip_code_or : 6; + unsigned int ALWAYS_ZERO0 : 6; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 6; + unsigned int clipsm0_clprim_to_clip_clip_code_or : 6; + unsigned int ALWAYS_ZERO1 : 12; + unsigned int clipsm0_clprim_to_clip_null_primitive : 1; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clipsm0_clprim_to_clip_clip_primitive : 1; + unsigned int ALWAYS_ZERO3 : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG04 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : 1; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int clipsm0_clprim_to_clip_event : 1; + unsigned int ALWAYS_ZERO0 : 24; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 24; + unsigned int clipsm0_clprim_to_clip_event : 1; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : 1; + unsigned int ALWAYS_ZERO2 : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG05 { + struct { +#if defined(qLittleEndian) + unsigned int clipsm0_clprim_to_clip_state_var_indx : 1; + unsigned int ALWAYS_ZERO3 : 2; + unsigned int clipsm0_clprim_to_clip_deallocate_slot : 3; + unsigned int clipsm0_clprim_to_clip_event_id : 6; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO0 : 4; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 4; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : 4; + unsigned int clipsm0_clprim_to_clip_event_id : 6; + unsigned int clipsm0_clprim_to_clip_deallocate_slot : 3; + unsigned int ALWAYS_ZERO3 : 2; + unsigned int clipsm0_clprim_to_clip_state_var_indx : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG09 { + struct { +#if defined(qLittleEndian) + unsigned int clprim_in_back_event : 1; + unsigned int outputclprimtoclip_null_primitive : 1; + unsigned int clprim_in_back_vertex_store_indx_2 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int clprim_in_back_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clprim_in_back_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int prim_back_valid : 1; + unsigned int clip_priority_seq_indx_out_cnt : 4; + unsigned int outsm_clr_rd_orig_vertices : 2; + unsigned int outsm_clr_rd_clipsm_wait : 1; + unsigned int outsm_clr_fifo_empty : 1; + unsigned int outsm_clr_fifo_full : 1; + unsigned int clip_priority_seq_indx_load : 2; +#else /* !defined(qLittleEndian) */ + unsigned int clip_priority_seq_indx_load : 2; + unsigned int outsm_clr_fifo_full : 1; + unsigned int outsm_clr_fifo_empty : 1; + unsigned int outsm_clr_rd_clipsm_wait : 1; + unsigned int outsm_clr_rd_orig_vertices : 2; + unsigned int clip_priority_seq_indx_out_cnt : 4; + unsigned int prim_back_valid : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int clprim_in_back_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clprim_in_back_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int clprim_in_back_vertex_store_indx_2 : 4; + unsigned int outputclprimtoclip_null_primitive : 1; + unsigned int clprim_in_back_event : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG10 { + struct { +#if defined(qLittleEndian) + unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : 4; + unsigned int ALWAYS_ZERO3 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clprim_in_back_state_var_indx : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int clprim_in_back_end_of_packet : 1; + unsigned int clprim_in_back_first_prim_of_slot : 1; + unsigned int clprim_in_back_deallocate_slot : 3; + unsigned int clprim_in_back_event_id : 6; +#else /* !defined(qLittleEndian) */ + unsigned int clprim_in_back_event_id : 6; + unsigned int clprim_in_back_deallocate_slot : 3; + unsigned int clprim_in_back_first_prim_of_slot : 1; + unsigned int clprim_in_back_end_of_packet : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int clprim_in_back_state_var_indx : 1; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO3 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG11 { + struct { +#if defined(qLittleEndian) + unsigned int vertval_bits_vertex_vertex_store_msb : 4; + unsigned int ALWAYS_ZERO : 28; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO : 28; + unsigned int vertval_bits_vertex_vertex_store_msb : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG12 { + struct { +#if defined(qLittleEndian) + unsigned int clip_priority_available_vte_out_clip : 2; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clip_vertex_fifo_empty : 1; + unsigned int clip_priority_available_clip_verts : 5; + unsigned int ALWAYS_ZERO1 : 4; + unsigned int vertval_bits_vertex_cc_next_valid : 4; + unsigned int clipcc_vertex_store_indx : 2; + unsigned int primic_to_clprim_valid : 1; + unsigned int ALWAYS_ZERO0 : 10; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 10; + unsigned int primic_to_clprim_valid : 1; + unsigned int clipcc_vertex_store_indx : 2; + unsigned int vertval_bits_vertex_cc_next_valid : 4; + unsigned int ALWAYS_ZERO1 : 4; + unsigned int clip_priority_available_clip_verts : 5; + unsigned int clip_vertex_fifo_empty : 1; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clip_priority_available_vte_out_clip : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG13 { + struct { +#if defined(qLittleEndian) + unsigned int sm0_clip_vert_cnt : 4; + unsigned int sm0_prim_end_state : 7; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int sm0_vertex_clip_cnt : 4; + unsigned int sm0_inv_to_clip_data_valid_1 : 1; + unsigned int sm0_inv_to_clip_data_valid_0 : 1; + unsigned int sm0_current_state : 7; + unsigned int ALWAYS_ZERO0 : 5; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 5; + unsigned int sm0_current_state : 7; + unsigned int sm0_inv_to_clip_data_valid_0 : 1; + unsigned int sm0_inv_to_clip_data_valid_1 : 1; + unsigned int sm0_vertex_clip_cnt : 4; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int sm0_prim_end_state : 7; + unsigned int sm0_clip_vert_cnt : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SXIFCCG_DEBUG_REG0 { + struct { +#if defined(qLittleEndian) + unsigned int nan_kill_flag : 4; + unsigned int position_address : 3; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int point_address : 3; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int sx_pending_rd_state_var_indx : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int sx_pending_rd_req_mask : 4; + unsigned int sx_pending_rd_pci : 7; + unsigned int sx_pending_rd_aux_inc : 1; + unsigned int sx_pending_rd_aux_sel : 1; +#else /* !defined(qLittleEndian) */ + unsigned int sx_pending_rd_aux_sel : 1; + unsigned int sx_pending_rd_aux_inc : 1; + unsigned int sx_pending_rd_pci : 7; + unsigned int sx_pending_rd_req_mask : 4; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int sx_pending_rd_state_var_indx : 1; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int point_address : 3; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int position_address : 3; + unsigned int nan_kill_flag : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SXIFCCG_DEBUG_REG1 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO3 : 2; + unsigned int sx_to_pa_empty : 2; + unsigned int available_positions : 3; + unsigned int ALWAYS_ZERO2 : 4; + unsigned int sx_pending_advance : 1; + unsigned int sx_receive_indx : 3; + unsigned int statevar_bits_sxpa_aux_vector : 1; + unsigned int ALWAYS_ZERO1 : 4; + unsigned int aux_sel : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int pasx_req_cnt : 2; + unsigned int param_cache_base : 7; +#else /* !defined(qLittleEndian) */ + unsigned int param_cache_base : 7; + unsigned int pasx_req_cnt : 2; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int aux_sel : 1; + unsigned int ALWAYS_ZERO1 : 4; + unsigned int statevar_bits_sxpa_aux_vector : 1; + unsigned int sx_receive_indx : 3; + unsigned int sx_pending_advance : 1; + unsigned int ALWAYS_ZERO2 : 4; + unsigned int available_positions : 3; + unsigned int sx_to_pa_empty : 2; + unsigned int ALWAYS_ZERO3 : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SXIFCCG_DEBUG_REG2 { + struct { +#if defined(qLittleEndian) + unsigned int sx_sent : 1; + unsigned int ALWAYS_ZERO3 : 1; + unsigned int sx_aux : 1; + unsigned int sx_request_indx : 6; + unsigned int req_active_verts : 7; + unsigned int ALWAYS_ZERO2 : 1; + unsigned int vgt_to_ccgen_state_var_indx : 1; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int vgt_to_ccgen_active_verts : 2; + unsigned int ALWAYS_ZERO0 : 4; + unsigned int req_active_verts_loaded : 1; + unsigned int sx_pending_fifo_empty : 1; + unsigned int sx_pending_fifo_full : 1; + unsigned int sx_pending_fifo_contents : 3; +#else /* !defined(qLittleEndian) */ + unsigned int sx_pending_fifo_contents : 3; + unsigned int sx_pending_fifo_full : 1; + unsigned int sx_pending_fifo_empty : 1; + unsigned int req_active_verts_loaded : 1; + unsigned int ALWAYS_ZERO0 : 4; + unsigned int vgt_to_ccgen_active_verts : 2; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int vgt_to_ccgen_state_var_indx : 1; + unsigned int ALWAYS_ZERO2 : 1; + unsigned int req_active_verts : 7; + unsigned int sx_request_indx : 6; + unsigned int sx_aux : 1; + unsigned int ALWAYS_ZERO3 : 1; + unsigned int sx_sent : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SXIFCCG_DEBUG_REG3 { + struct { +#if defined(qLittleEndian) + unsigned int vertex_fifo_entriesavailable : 4; + unsigned int ALWAYS_ZERO3 : 1; + unsigned int available_positions : 3; + unsigned int ALWAYS_ZERO2 : 4; + unsigned int current_state : 2; + unsigned int vertex_fifo_empty : 1; + unsigned int vertex_fifo_full : 1; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int sx0_receive_fifo_empty : 1; + unsigned int sx0_receive_fifo_full : 1; + unsigned int vgt_to_ccgen_fifo_empty : 1; + unsigned int vgt_to_ccgen_fifo_full : 1; + unsigned int ALWAYS_ZERO0 : 10; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 10; + unsigned int vgt_to_ccgen_fifo_full : 1; + unsigned int vgt_to_ccgen_fifo_empty : 1; + unsigned int sx0_receive_fifo_full : 1; + unsigned int sx0_receive_fifo_empty : 1; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int vertex_fifo_full : 1; + unsigned int vertex_fifo_empty : 1; + unsigned int current_state : 2; + unsigned int ALWAYS_ZERO2 : 4; + unsigned int available_positions : 3; + unsigned int ALWAYS_ZERO3 : 1; + unsigned int vertex_fifo_entriesavailable : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG0 { + struct { +#if defined(qLittleEndian) + unsigned int su_cntl_state : 5; + unsigned int pmode_state : 6; + unsigned int ge_stallb : 1; + unsigned int geom_enable : 1; + unsigned int su_clip_baryc_rtr : 1; + unsigned int su_clip_rtr : 1; + unsigned int pfifo_busy : 1; + unsigned int su_cntl_busy : 1; + unsigned int geom_busy : 1; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int geom_busy : 1; + unsigned int su_cntl_busy : 1; + unsigned int pfifo_busy : 1; + unsigned int su_clip_rtr : 1; + unsigned int su_clip_baryc_rtr : 1; + unsigned int geom_enable : 1; + unsigned int ge_stallb : 1; + unsigned int pmode_state : 6; + unsigned int su_cntl_state : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG1 { + struct { +#if defined(qLittleEndian) + unsigned int y_sort0_gated_17_4 : 14; + unsigned int x_sort0_gated_17_4 : 14; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int x_sort0_gated_17_4 : 14; + unsigned int y_sort0_gated_17_4 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG2 { + struct { +#if defined(qLittleEndian) + unsigned int y_sort1_gated_17_4 : 14; + unsigned int x_sort1_gated_17_4 : 14; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int x_sort1_gated_17_4 : 14; + unsigned int y_sort1_gated_17_4 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG3 { + struct { +#if defined(qLittleEndian) + unsigned int y_sort2_gated_17_4 : 14; + unsigned int x_sort2_gated_17_4 : 14; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int x_sort2_gated_17_4 : 14; + unsigned int y_sort2_gated_17_4 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG4 { + struct { +#if defined(qLittleEndian) + unsigned int attr_indx_sort0_gated : 11; + unsigned int null_prim_gated : 1; + unsigned int backfacing_gated : 1; + unsigned int st_indx_gated : 3; + unsigned int clipped_gated : 1; + unsigned int dealloc_slot_gated : 3; + unsigned int xmajor_gated : 1; + unsigned int diamond_rule_gated : 2; + unsigned int type_gated : 3; + unsigned int fpov_gated : 1; + unsigned int pmode_prim_gated : 1; + unsigned int event_gated : 1; + unsigned int eop_gated : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int eop_gated : 1; + unsigned int event_gated : 1; + unsigned int pmode_prim_gated : 1; + unsigned int fpov_gated : 1; + unsigned int type_gated : 3; + unsigned int diamond_rule_gated : 2; + unsigned int xmajor_gated : 1; + unsigned int dealloc_slot_gated : 3; + unsigned int clipped_gated : 1; + unsigned int st_indx_gated : 3; + unsigned int backfacing_gated : 1; + unsigned int null_prim_gated : 1; + unsigned int attr_indx_sort0_gated : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG5 { + struct { +#if defined(qLittleEndian) + unsigned int attr_indx_sort2_gated : 11; + unsigned int attr_indx_sort1_gated : 11; + unsigned int provoking_vtx_gated : 2; + unsigned int event_id_gated : 5; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int event_id_gated : 5; + unsigned int provoking_vtx_gated : 2; + unsigned int attr_indx_sort1_gated : 11; + unsigned int attr_indx_sort2_gated : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_DEBUG_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int SC_DEBUG_INDX : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int SC_DEBUG_INDX : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_0 { + struct { +#if defined(qLittleEndian) + unsigned int pa_freeze_b1 : 1; + unsigned int pa_sc_valid : 1; + unsigned int pa_sc_phase : 3; + unsigned int cntx_cnt : 7; + unsigned int decr_cntx_cnt : 1; + unsigned int incr_cntx_cnt : 1; + unsigned int : 17; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 17; + unsigned int incr_cntx_cnt : 1; + unsigned int decr_cntx_cnt : 1; + unsigned int cntx_cnt : 7; + unsigned int pa_sc_phase : 3; + unsigned int pa_sc_valid : 1; + unsigned int pa_freeze_b1 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_1 { + struct { +#if defined(qLittleEndian) + unsigned int em_state : 3; + unsigned int em1_data_ready : 1; + unsigned int em2_data_ready : 1; + unsigned int move_em1_to_em2 : 1; + unsigned int ef_data_ready : 1; + unsigned int ef_state : 2; + unsigned int pipe_valid : 1; + unsigned int : 21; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 21; + unsigned int pipe_valid : 1; + unsigned int ef_state : 2; + unsigned int ef_data_ready : 1; + unsigned int move_em1_to_em2 : 1; + unsigned int em2_data_ready : 1; + unsigned int em1_data_ready : 1; + unsigned int em_state : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_2 { + struct { +#if defined(qLittleEndian) + unsigned int rc_rtr_dly : 1; + unsigned int qmask_ff_alm_full_d1 : 1; + unsigned int : 1; + unsigned int pipe_freeze_b : 1; + unsigned int prim_rts : 1; + unsigned int next_prim_rts_dly : 1; + unsigned int next_prim_rtr_dly : 1; + unsigned int pre_stage1_rts_d1 : 1; + unsigned int stage0_rts : 1; + unsigned int phase_rts_dly : 1; + unsigned int : 5; + unsigned int end_of_prim_s1_dly : 1; + unsigned int pass_empty_prim_s1 : 1; + unsigned int event_id_s1 : 5; + unsigned int event_s1 : 1; + unsigned int : 8; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 8; + unsigned int event_s1 : 1; + unsigned int event_id_s1 : 5; + unsigned int pass_empty_prim_s1 : 1; + unsigned int end_of_prim_s1_dly : 1; + unsigned int : 5; + unsigned int phase_rts_dly : 1; + unsigned int stage0_rts : 1; + unsigned int pre_stage1_rts_d1 : 1; + unsigned int next_prim_rtr_dly : 1; + unsigned int next_prim_rts_dly : 1; + unsigned int prim_rts : 1; + unsigned int pipe_freeze_b : 1; + unsigned int : 1; + unsigned int qmask_ff_alm_full_d1 : 1; + unsigned int rc_rtr_dly : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_3 { + struct { +#if defined(qLittleEndian) + unsigned int x_curr_s1 : 11; + unsigned int y_curr_s1 : 11; + unsigned int : 9; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 9; + unsigned int y_curr_s1 : 11; + unsigned int x_curr_s1 : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_4 { + struct { +#if defined(qLittleEndian) + unsigned int y_end_s1 : 14; + unsigned int y_start_s1 : 14; + unsigned int y_dir_s1 : 1; + unsigned int : 2; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 2; + unsigned int y_dir_s1 : 1; + unsigned int y_start_s1 : 14; + unsigned int y_end_s1 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_5 { + struct { +#if defined(qLittleEndian) + unsigned int x_end_s1 : 14; + unsigned int x_start_s1 : 14; + unsigned int x_dir_s1 : 1; + unsigned int : 2; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 2; + unsigned int x_dir_s1 : 1; + unsigned int x_start_s1 : 14; + unsigned int x_end_s1 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_6 { + struct { +#if defined(qLittleEndian) + unsigned int z_ff_empty : 1; + unsigned int qmcntl_ff_empty : 1; + unsigned int xy_ff_empty : 1; + unsigned int event_flag : 1; + unsigned int z_mask_needed : 1; + unsigned int state : 3; + unsigned int state_delayed : 3; + unsigned int data_valid : 1; + unsigned int data_valid_d : 1; + unsigned int tilex_delayed : 9; + unsigned int tiley_delayed : 9; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int tiley_delayed : 9; + unsigned int tilex_delayed : 9; + unsigned int data_valid_d : 1; + unsigned int data_valid : 1; + unsigned int state_delayed : 3; + unsigned int state : 3; + unsigned int z_mask_needed : 1; + unsigned int event_flag : 1; + unsigned int xy_ff_empty : 1; + unsigned int qmcntl_ff_empty : 1; + unsigned int z_ff_empty : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_7 { + struct { +#if defined(qLittleEndian) + unsigned int event_flag : 1; + unsigned int deallocate : 3; + unsigned int fpos : 1; + unsigned int sr_prim_we : 1; + unsigned int last_tile : 1; + unsigned int tile_ff_we : 1; + unsigned int qs_data_valid : 1; + unsigned int qs_q0_y : 2; + unsigned int qs_q0_x : 2; + unsigned int qs_q0_valid : 1; + unsigned int prim_ff_we : 1; + unsigned int tile_ff_re : 1; + unsigned int fw_prim_data_valid : 1; + unsigned int last_quad_of_tile : 1; + unsigned int first_quad_of_tile : 1; + unsigned int first_quad_of_prim : 1; + unsigned int new_prim : 1; + unsigned int load_new_tile_data : 1; + unsigned int state : 2; + unsigned int fifos_ready : 1; + unsigned int : 6; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 6; + unsigned int fifos_ready : 1; + unsigned int state : 2; + unsigned int load_new_tile_data : 1; + unsigned int new_prim : 1; + unsigned int first_quad_of_prim : 1; + unsigned int first_quad_of_tile : 1; + unsigned int last_quad_of_tile : 1; + unsigned int fw_prim_data_valid : 1; + unsigned int tile_ff_re : 1; + unsigned int prim_ff_we : 1; + unsigned int qs_q0_valid : 1; + unsigned int qs_q0_x : 2; + unsigned int qs_q0_y : 2; + unsigned int qs_data_valid : 1; + unsigned int tile_ff_we : 1; + unsigned int last_tile : 1; + unsigned int sr_prim_we : 1; + unsigned int fpos : 1; + unsigned int deallocate : 3; + unsigned int event_flag : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_8 { + struct { +#if defined(qLittleEndian) + unsigned int sample_last : 1; + unsigned int sample_mask : 4; + unsigned int sample_y : 2; + unsigned int sample_x : 2; + unsigned int sample_send : 1; + unsigned int next_cycle : 2; + unsigned int ez_sample_ff_full : 1; + unsigned int rb_sc_samp_rtr : 1; + unsigned int num_samples : 2; + unsigned int last_quad_of_tile : 1; + unsigned int last_quad_of_prim : 1; + unsigned int first_quad_of_prim : 1; + unsigned int sample_we : 1; + unsigned int fpos : 1; + unsigned int event_id : 5; + unsigned int event_flag : 1; + unsigned int fw_prim_data_valid : 1; + unsigned int : 3; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 3; + unsigned int fw_prim_data_valid : 1; + unsigned int event_flag : 1; + unsigned int event_id : 5; + unsigned int fpos : 1; + unsigned int sample_we : 1; + unsigned int first_quad_of_prim : 1; + unsigned int last_quad_of_prim : 1; + unsigned int last_quad_of_tile : 1; + unsigned int num_samples : 2; + unsigned int rb_sc_samp_rtr : 1; + unsigned int ez_sample_ff_full : 1; + unsigned int next_cycle : 2; + unsigned int sample_send : 1; + unsigned int sample_x : 2; + unsigned int sample_y : 2; + unsigned int sample_mask : 4; + unsigned int sample_last : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_9 { + struct { +#if defined(qLittleEndian) + unsigned int rb_sc_send : 1; + unsigned int rb_sc_ez_mask : 4; + unsigned int fifo_data_ready : 1; + unsigned int early_z_enable : 1; + unsigned int mask_state : 2; + unsigned int next_ez_mask : 16; + unsigned int mask_ready : 1; + unsigned int drop_sample : 1; + unsigned int fetch_new_sample_data : 1; + unsigned int fetch_new_ez_sample_mask : 1; + unsigned int pkr_fetch_new_sample_data : 1; + unsigned int pkr_fetch_new_prim_data : 1; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int pkr_fetch_new_prim_data : 1; + unsigned int pkr_fetch_new_sample_data : 1; + unsigned int fetch_new_ez_sample_mask : 1; + unsigned int fetch_new_sample_data : 1; + unsigned int drop_sample : 1; + unsigned int mask_ready : 1; + unsigned int next_ez_mask : 16; + unsigned int mask_state : 2; + unsigned int early_z_enable : 1; + unsigned int fifo_data_ready : 1; + unsigned int rb_sc_ez_mask : 4; + unsigned int rb_sc_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_10 { + struct { +#if defined(qLittleEndian) + unsigned int combined_sample_mask : 16; + unsigned int : 15; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 15; + unsigned int combined_sample_mask : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_11 { + struct { +#if defined(qLittleEndian) + unsigned int ez_sample_data_ready : 1; + unsigned int pkr_fetch_new_sample_data : 1; + unsigned int ez_prim_data_ready : 1; + unsigned int pkr_fetch_new_prim_data : 1; + unsigned int iterator_input_fz : 1; + unsigned int packer_send_quads : 1; + unsigned int packer_send_cmd : 1; + unsigned int packer_send_event : 1; + unsigned int next_state : 3; + unsigned int state : 3; + unsigned int stall : 1; + unsigned int : 16; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 16; + unsigned int stall : 1; + unsigned int state : 3; + unsigned int next_state : 3; + unsigned int packer_send_event : 1; + unsigned int packer_send_cmd : 1; + unsigned int packer_send_quads : 1; + unsigned int iterator_input_fz : 1; + unsigned int pkr_fetch_new_prim_data : 1; + unsigned int ez_prim_data_ready : 1; + unsigned int pkr_fetch_new_sample_data : 1; + unsigned int ez_sample_data_ready : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_12 { + struct { +#if defined(qLittleEndian) + unsigned int SQ_iterator_free_buff : 1; + unsigned int event_id : 5; + unsigned int event_flag : 1; + unsigned int itercmdfifo_busy_nc_dly : 1; + unsigned int itercmdfifo_full : 1; + unsigned int itercmdfifo_empty : 1; + unsigned int iter_ds_one_clk_command : 1; + unsigned int iter_ds_end_of_prim0 : 1; + unsigned int iter_ds_end_of_vector : 1; + unsigned int iter_qdhit0 : 1; + unsigned int bc_use_centers_reg : 1; + unsigned int bc_output_xy_reg : 1; + unsigned int iter_phase_out : 2; + unsigned int iter_phase_reg : 2; + unsigned int iterator_SP_valid : 1; + unsigned int eopv_reg : 1; + unsigned int one_clk_cmd_reg : 1; + unsigned int iter_dx_end_of_prim : 1; + unsigned int : 7; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 7; + unsigned int iter_dx_end_of_prim : 1; + unsigned int one_clk_cmd_reg : 1; + unsigned int eopv_reg : 1; + unsigned int iterator_SP_valid : 1; + unsigned int iter_phase_reg : 2; + unsigned int iter_phase_out : 2; + unsigned int bc_output_xy_reg : 1; + unsigned int bc_use_centers_reg : 1; + unsigned int iter_qdhit0 : 1; + unsigned int iter_ds_end_of_vector : 1; + unsigned int iter_ds_end_of_prim0 : 1; + unsigned int iter_ds_one_clk_command : 1; + unsigned int itercmdfifo_empty : 1; + unsigned int itercmdfifo_full : 1; + unsigned int itercmdfifo_busy_nc_dly : 1; + unsigned int event_flag : 1; + unsigned int event_id : 5; + unsigned int SQ_iterator_free_buff : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union GFX_COPY_STATE { + struct { +#if defined(qLittleEndian) + unsigned int SRC_STATE_ID : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int SRC_STATE_ID : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DRAW_INITIATOR { + struct { +#if defined(qLittleEndian) + unsigned int PRIM_TYPE : 6; + unsigned int SOURCE_SELECT : 2; + unsigned int : 3; + unsigned int INDEX_SIZE : 1; + unsigned int NOT_EOP : 1; + unsigned int SMALL_INDEX : 1; + unsigned int PRE_FETCH_CULL_ENABLE : 1; + unsigned int GRP_CULL_ENABLE : 1; + unsigned int NUM_INDICES : 16; +#else /* !defined(qLittleEndian) */ + unsigned int NUM_INDICES : 16; + unsigned int GRP_CULL_ENABLE : 1; + unsigned int PRE_FETCH_CULL_ENABLE : 1; + unsigned int SMALL_INDEX : 1; + unsigned int NOT_EOP : 1; + unsigned int INDEX_SIZE : 1; + unsigned int : 3; + unsigned int SOURCE_SELECT : 2; + unsigned int PRIM_TYPE : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_EVENT_INITIATOR { + struct { +#if defined(qLittleEndian) + unsigned int EVENT_TYPE : 6; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int EVENT_TYPE : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DMA_BASE { + struct { +#if defined(qLittleEndian) + unsigned int BASE_ADDR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BASE_ADDR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DMA_SIZE { + struct { +#if defined(qLittleEndian) + unsigned int NUM_WORDS : 24; + unsigned int : 6; + unsigned int SWAP_MODE : 2; +#else /* !defined(qLittleEndian) */ + unsigned int SWAP_MODE : 2; + unsigned int : 6; + unsigned int NUM_WORDS : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_BIN_BASE { + struct { +#if defined(qLittleEndian) + unsigned int BIN_BASE_ADDR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_BASE_ADDR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_BIN_SIZE { + struct { +#if defined(qLittleEndian) + unsigned int NUM_WORDS : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int NUM_WORDS : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CURRENT_BIN_ID_MIN { + struct { +#if defined(qLittleEndian) + unsigned int COLUMN : 3; + unsigned int ROW : 3; + unsigned int GUARD_BAND : 3; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int GUARD_BAND : 3; + unsigned int ROW : 3; + unsigned int COLUMN : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CURRENT_BIN_ID_MAX { + struct { +#if defined(qLittleEndian) + unsigned int COLUMN : 3; + unsigned int ROW : 3; + unsigned int GUARD_BAND : 3; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int GUARD_BAND : 3; + unsigned int ROW : 3; + unsigned int COLUMN : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_IMMED_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_MAX_VTX_INDX { + struct { +#if defined(qLittleEndian) + unsigned int MAX_INDX : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int MAX_INDX : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_MIN_VTX_INDX { + struct { +#if defined(qLittleEndian) + unsigned int MIN_INDX : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int MIN_INDX : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_INDX_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int INDX_OFFSET : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int INDX_OFFSET : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_VERTEX_REUSE_BLOCK_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int VTX_REUSE_DEPTH : 3; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int VTX_REUSE_DEPTH : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_OUT_DEALLOC_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int DEALLOC_DIST : 2; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int DEALLOC_DIST : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_MULTI_PRIM_IB_RESET_INDX { + struct { +#if defined(qLittleEndian) + unsigned int RESET_INDX : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int RESET_INDX : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_ENHANCE { + struct { +#if defined(qLittleEndian) + unsigned int MISC : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int MISC : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_VTX_VECT_EJECT_REG { + struct { +#if defined(qLittleEndian) + unsigned int PRIM_COUNT : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int PRIM_COUNT : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_LAST_COPY_STATE { + struct { +#if defined(qLittleEndian) + unsigned int SRC_STATE_ID : 1; + unsigned int : 15; + unsigned int DST_STATE_ID : 1; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int DST_STATE_ID : 1; + unsigned int : 15; + unsigned int SRC_STATE_ID : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int VGT_DEBUG_INDX : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int VGT_DEBUG_INDX : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int VGT_BUSY : 1; + unsigned int VGT_DMA_BUSY : 1; + unsigned int VGT_DMA_REQ_BUSY : 1; + unsigned int VGT_GRP_BUSY : 1; + unsigned int VGT_VR_BUSY : 1; + unsigned int VGT_BIN_BUSY : 1; + unsigned int VGT_PT_BUSY : 1; + unsigned int VGT_OUT_BUSY : 1; + unsigned int VGT_OUT_INDX_BUSY : 1; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int VGT_OUT_INDX_BUSY : 1; + unsigned int VGT_OUT_BUSY : 1; + unsigned int VGT_PT_BUSY : 1; + unsigned int VGT_BIN_BUSY : 1; + unsigned int VGT_VR_BUSY : 1; + unsigned int VGT_GRP_BUSY : 1; + unsigned int VGT_DMA_REQ_BUSY : 1; + unsigned int VGT_DMA_BUSY : 1; + unsigned int VGT_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG0 { + struct { +#if defined(qLittleEndian) + unsigned int te_grp_busy : 1; + unsigned int pt_grp_busy : 1; + unsigned int vr_grp_busy : 1; + unsigned int dma_request_busy : 1; + unsigned int out_busy : 1; + unsigned int grp_backend_busy : 1; + unsigned int grp_busy : 1; + unsigned int dma_busy : 1; + unsigned int rbiu_dma_request_busy : 1; + unsigned int rbiu_busy : 1; + unsigned int vgt_no_dma_busy_extended : 1; + unsigned int vgt_no_dma_busy : 1; + unsigned int vgt_busy_extended : 1; + unsigned int vgt_busy : 1; + unsigned int rbbm_skid_fifo_busy_out : 1; + unsigned int VGT_RBBM_no_dma_busy : 1; + unsigned int VGT_RBBM_busy : 1; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int VGT_RBBM_busy : 1; + unsigned int VGT_RBBM_no_dma_busy : 1; + unsigned int rbbm_skid_fifo_busy_out : 1; + unsigned int vgt_busy : 1; + unsigned int vgt_busy_extended : 1; + unsigned int vgt_no_dma_busy : 1; + unsigned int vgt_no_dma_busy_extended : 1; + unsigned int rbiu_busy : 1; + unsigned int rbiu_dma_request_busy : 1; + unsigned int dma_busy : 1; + unsigned int grp_busy : 1; + unsigned int grp_backend_busy : 1; + unsigned int out_busy : 1; + unsigned int dma_request_busy : 1; + unsigned int vr_grp_busy : 1; + unsigned int pt_grp_busy : 1; + unsigned int te_grp_busy : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG1 { + struct { +#if defined(qLittleEndian) + unsigned int out_te_data_read : 1; + unsigned int te_out_data_valid : 1; + unsigned int out_pt_prim_read : 1; + unsigned int pt_out_prim_valid : 1; + unsigned int out_pt_data_read : 1; + unsigned int pt_out_indx_valid : 1; + unsigned int out_vr_prim_read : 1; + unsigned int vr_out_prim_valid : 1; + unsigned int out_vr_indx_read : 1; + unsigned int vr_out_indx_valid : 1; + unsigned int te_grp_read : 1; + unsigned int grp_te_valid : 1; + unsigned int pt_grp_read : 1; + unsigned int grp_pt_valid : 1; + unsigned int vr_grp_read : 1; + unsigned int grp_vr_valid : 1; + unsigned int grp_dma_read : 1; + unsigned int dma_grp_valid : 1; + unsigned int grp_rbiu_di_read : 1; + unsigned int rbiu_grp_di_valid : 1; + unsigned int MH_VGT_rtr : 1; + unsigned int VGT_MH_send : 1; + unsigned int PA_VGT_clip_s_rtr : 1; + unsigned int VGT_PA_clip_s_send : 1; + unsigned int PA_VGT_clip_p_rtr : 1; + unsigned int VGT_PA_clip_p_send : 1; + unsigned int PA_VGT_clip_v_rtr : 1; + unsigned int VGT_PA_clip_v_send : 1; + unsigned int SQ_VGT_rtr : 1; + unsigned int VGT_SQ_send : 1; + unsigned int mh_vgt_tag_7_q : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int mh_vgt_tag_7_q : 1; + unsigned int VGT_SQ_send : 1; + unsigned int SQ_VGT_rtr : 1; + unsigned int VGT_PA_clip_v_send : 1; + unsigned int PA_VGT_clip_v_rtr : 1; + unsigned int VGT_PA_clip_p_send : 1; + unsigned int PA_VGT_clip_p_rtr : 1; + unsigned int VGT_PA_clip_s_send : 1; + unsigned int PA_VGT_clip_s_rtr : 1; + unsigned int VGT_MH_send : 1; + unsigned int MH_VGT_rtr : 1; + unsigned int rbiu_grp_di_valid : 1; + unsigned int grp_rbiu_di_read : 1; + unsigned int dma_grp_valid : 1; + unsigned int grp_dma_read : 1; + unsigned int grp_vr_valid : 1; + unsigned int vr_grp_read : 1; + unsigned int grp_pt_valid : 1; + unsigned int pt_grp_read : 1; + unsigned int grp_te_valid : 1; + unsigned int te_grp_read : 1; + unsigned int vr_out_indx_valid : 1; + unsigned int out_vr_indx_read : 1; + unsigned int vr_out_prim_valid : 1; + unsigned int out_vr_prim_read : 1; + unsigned int pt_out_indx_valid : 1; + unsigned int out_pt_data_read : 1; + unsigned int pt_out_prim_valid : 1; + unsigned int out_pt_prim_read : 1; + unsigned int te_out_data_valid : 1; + unsigned int out_te_data_read : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG3 { + struct { +#if defined(qLittleEndian) + unsigned int vgt_clk_en : 1; + unsigned int reg_fifos_clk_en : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int reg_fifos_clk_en : 1; + unsigned int vgt_clk_en : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG6 { + struct { +#if defined(qLittleEndian) + unsigned int shifter_byte_count_q : 5; + unsigned int right_word_indx_q : 5; + unsigned int input_data_valid : 1; + unsigned int input_data_xfer : 1; + unsigned int next_shift_is_vect_1_q : 1; + unsigned int next_shift_is_vect_1_d : 1; + unsigned int next_shift_is_vect_1_pre_d : 1; + unsigned int space_avail_from_shift : 1; + unsigned int shifter_first_load : 1; + unsigned int di_state_sel_q : 1; + unsigned int shifter_waiting_for_first_load_q : 1; + unsigned int di_first_group_flag_q : 1; + unsigned int di_event_flag_q : 1; + unsigned int read_draw_initiator : 1; + unsigned int loading_di_requires_shifter : 1; + unsigned int last_shift_of_packet : 1; + unsigned int last_decr_of_packet : 1; + unsigned int extract_vector : 1; + unsigned int shift_vect_rtr : 1; + unsigned int destination_rtr : 1; + unsigned int grp_trigger : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int grp_trigger : 1; + unsigned int destination_rtr : 1; + unsigned int shift_vect_rtr : 1; + unsigned int extract_vector : 1; + unsigned int last_decr_of_packet : 1; + unsigned int last_shift_of_packet : 1; + unsigned int loading_di_requires_shifter : 1; + unsigned int read_draw_initiator : 1; + unsigned int di_event_flag_q : 1; + unsigned int di_first_group_flag_q : 1; + unsigned int shifter_waiting_for_first_load_q : 1; + unsigned int di_state_sel_q : 1; + unsigned int shifter_first_load : 1; + unsigned int space_avail_from_shift : 1; + unsigned int next_shift_is_vect_1_pre_d : 1; + unsigned int next_shift_is_vect_1_d : 1; + unsigned int next_shift_is_vect_1_q : 1; + unsigned int input_data_xfer : 1; + unsigned int input_data_valid : 1; + unsigned int right_word_indx_q : 5; + unsigned int shifter_byte_count_q : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG7 { + struct { +#if defined(qLittleEndian) + unsigned int di_index_counter_q : 16; + unsigned int shift_amount_no_extract : 4; + unsigned int shift_amount_extract : 4; + unsigned int di_prim_type_q : 6; + unsigned int current_source_sel : 2; +#else /* !defined(qLittleEndian) */ + unsigned int current_source_sel : 2; + unsigned int di_prim_type_q : 6; + unsigned int shift_amount_extract : 4; + unsigned int shift_amount_no_extract : 4; + unsigned int di_index_counter_q : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG8 { + struct { +#if defined(qLittleEndian) + unsigned int current_source_sel : 2; + unsigned int left_word_indx_q : 5; + unsigned int input_data_cnt : 5; + unsigned int input_data_lsw : 5; + unsigned int input_data_msw : 5; + unsigned int next_small_stride_shift_limit_q : 5; + unsigned int current_small_stride_shift_limit_q : 5; +#else /* !defined(qLittleEndian) */ + unsigned int current_small_stride_shift_limit_q : 5; + unsigned int next_small_stride_shift_limit_q : 5; + unsigned int input_data_msw : 5; + unsigned int input_data_lsw : 5; + unsigned int input_data_cnt : 5; + unsigned int left_word_indx_q : 5; + unsigned int current_source_sel : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG9 { + struct { +#if defined(qLittleEndian) + unsigned int next_stride_q : 5; + unsigned int next_stride_d : 5; + unsigned int current_shift_q : 5; + unsigned int current_shift_d : 5; + unsigned int current_stride_q : 5; + unsigned int current_stride_d : 5; + unsigned int grp_trigger : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int grp_trigger : 1; + unsigned int current_stride_d : 5; + unsigned int current_stride_q : 5; + unsigned int current_shift_d : 5; + unsigned int current_shift_q : 5; + unsigned int next_stride_d : 5; + unsigned int next_stride_q : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG10 { + struct { +#if defined(qLittleEndian) + unsigned int temp_derived_di_prim_type_t0 : 1; + unsigned int temp_derived_di_small_index_t0 : 1; + unsigned int temp_derived_di_cull_enable_t0 : 1; + unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : 1; + unsigned int di_state_sel_q : 1; + unsigned int last_decr_of_packet : 1; + unsigned int bin_valid : 1; + unsigned int read_block : 1; + unsigned int grp_bgrp_last_bit_read : 1; + unsigned int last_bit_enable_q : 1; + unsigned int last_bit_end_di_q : 1; + unsigned int selected_data : 8; + unsigned int mask_input_data : 8; + unsigned int gap_q : 1; + unsigned int temp_mini_reset_z : 1; + unsigned int temp_mini_reset_y : 1; + unsigned int temp_mini_reset_x : 1; + unsigned int grp_trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int grp_trigger : 1; + unsigned int temp_mini_reset_x : 1; + unsigned int temp_mini_reset_y : 1; + unsigned int temp_mini_reset_z : 1; + unsigned int gap_q : 1; + unsigned int mask_input_data : 8; + unsigned int selected_data : 8; + unsigned int last_bit_end_di_q : 1; + unsigned int last_bit_enable_q : 1; + unsigned int grp_bgrp_last_bit_read : 1; + unsigned int read_block : 1; + unsigned int bin_valid : 1; + unsigned int last_decr_of_packet : 1; + unsigned int di_state_sel_q : 1; + unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : 1; + unsigned int temp_derived_di_cull_enable_t0 : 1; + unsigned int temp_derived_di_small_index_t0 : 1; + unsigned int temp_derived_di_prim_type_t0 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG12 { + struct { +#if defined(qLittleEndian) + unsigned int shifter_byte_count_q : 5; + unsigned int right_word_indx_q : 5; + unsigned int input_data_valid : 1; + unsigned int input_data_xfer : 1; + unsigned int next_shift_is_vect_1_q : 1; + unsigned int next_shift_is_vect_1_d : 1; + unsigned int next_shift_is_vect_1_pre_d : 1; + unsigned int space_avail_from_shift : 1; + unsigned int shifter_first_load : 1; + unsigned int di_state_sel_q : 1; + unsigned int shifter_waiting_for_first_load_q : 1; + unsigned int di_first_group_flag_q : 1; + unsigned int di_event_flag_q : 1; + unsigned int read_draw_initiator : 1; + unsigned int loading_di_requires_shifter : 1; + unsigned int last_shift_of_packet : 1; + unsigned int last_decr_of_packet : 1; + unsigned int extract_vector : 1; + unsigned int shift_vect_rtr : 1; + unsigned int destination_rtr : 1; + unsigned int bgrp_trigger : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int bgrp_trigger : 1; + unsigned int destination_rtr : 1; + unsigned int shift_vect_rtr : 1; + unsigned int extract_vector : 1; + unsigned int last_decr_of_packet : 1; + unsigned int last_shift_of_packet : 1; + unsigned int loading_di_requires_shifter : 1; + unsigned int read_draw_initiator : 1; + unsigned int di_event_flag_q : 1; + unsigned int di_first_group_flag_q : 1; + unsigned int shifter_waiting_for_first_load_q : 1; + unsigned int di_state_sel_q : 1; + unsigned int shifter_first_load : 1; + unsigned int space_avail_from_shift : 1; + unsigned int next_shift_is_vect_1_pre_d : 1; + unsigned int next_shift_is_vect_1_d : 1; + unsigned int next_shift_is_vect_1_q : 1; + unsigned int input_data_xfer : 1; + unsigned int input_data_valid : 1; + unsigned int right_word_indx_q : 5; + unsigned int shifter_byte_count_q : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG13 { + struct { +#if defined(qLittleEndian) + unsigned int di_index_counter_q : 16; + unsigned int shift_amount_no_extract : 4; + unsigned int shift_amount_extract : 4; + unsigned int di_prim_type_q : 6; + unsigned int current_source_sel : 2; +#else /* !defined(qLittleEndian) */ + unsigned int current_source_sel : 2; + unsigned int di_prim_type_q : 6; + unsigned int shift_amount_extract : 4; + unsigned int shift_amount_no_extract : 4; + unsigned int di_index_counter_q : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG14 { + struct { +#if defined(qLittleEndian) + unsigned int current_source_sel : 2; + unsigned int left_word_indx_q : 5; + unsigned int input_data_cnt : 5; + unsigned int input_data_lsw : 5; + unsigned int input_data_msw : 5; + unsigned int next_small_stride_shift_limit_q : 5; + unsigned int current_small_stride_shift_limit_q : 5; +#else /* !defined(qLittleEndian) */ + unsigned int current_small_stride_shift_limit_q : 5; + unsigned int next_small_stride_shift_limit_q : 5; + unsigned int input_data_msw : 5; + unsigned int input_data_lsw : 5; + unsigned int input_data_cnt : 5; + unsigned int left_word_indx_q : 5; + unsigned int current_source_sel : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG15 { + struct { +#if defined(qLittleEndian) + unsigned int next_stride_q : 5; + unsigned int next_stride_d : 5; + unsigned int current_shift_q : 5; + unsigned int current_shift_d : 5; + unsigned int current_stride_q : 5; + unsigned int current_stride_d : 5; + unsigned int bgrp_trigger : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int bgrp_trigger : 1; + unsigned int current_stride_d : 5; + unsigned int current_stride_q : 5; + unsigned int current_shift_d : 5; + unsigned int current_shift_q : 5; + unsigned int next_stride_d : 5; + unsigned int next_stride_q : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG16 { + struct { +#if defined(qLittleEndian) + unsigned int bgrp_cull_fetch_fifo_full : 1; + unsigned int bgrp_cull_fetch_fifo_empty : 1; + unsigned int dma_bgrp_cull_fetch_read : 1; + unsigned int bgrp_cull_fetch_fifo_we : 1; + unsigned int bgrp_byte_mask_fifo_full : 1; + unsigned int bgrp_byte_mask_fifo_empty : 1; + unsigned int bgrp_byte_mask_fifo_re_q : 1; + unsigned int bgrp_byte_mask_fifo_we : 1; + unsigned int bgrp_dma_mask_kill : 1; + unsigned int bgrp_grp_bin_valid : 1; + unsigned int rst_last_bit : 1; + unsigned int current_state_q : 1; + unsigned int old_state_q : 1; + unsigned int old_state_en : 1; + unsigned int prev_last_bit_q : 1; + unsigned int dbl_last_bit_q : 1; + unsigned int last_bit_block_q : 1; + unsigned int ast_bit_block2_q : 1; + unsigned int load_empty_reg : 1; + unsigned int bgrp_grp_byte_mask_rdata : 8; + unsigned int dma_bgrp_dma_data_fifo_rptr : 2; + unsigned int top_di_pre_fetch_cull_enable : 1; + unsigned int top_di_grp_cull_enable_q : 1; + unsigned int bgrp_trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int bgrp_trigger : 1; + unsigned int top_di_grp_cull_enable_q : 1; + unsigned int top_di_pre_fetch_cull_enable : 1; + unsigned int dma_bgrp_dma_data_fifo_rptr : 2; + unsigned int bgrp_grp_byte_mask_rdata : 8; + unsigned int load_empty_reg : 1; + unsigned int ast_bit_block2_q : 1; + unsigned int last_bit_block_q : 1; + unsigned int dbl_last_bit_q : 1; + unsigned int prev_last_bit_q : 1; + unsigned int old_state_en : 1; + unsigned int old_state_q : 1; + unsigned int current_state_q : 1; + unsigned int rst_last_bit : 1; + unsigned int bgrp_grp_bin_valid : 1; + unsigned int bgrp_dma_mask_kill : 1; + unsigned int bgrp_byte_mask_fifo_we : 1; + unsigned int bgrp_byte_mask_fifo_re_q : 1; + unsigned int bgrp_byte_mask_fifo_empty : 1; + unsigned int bgrp_byte_mask_fifo_full : 1; + unsigned int bgrp_cull_fetch_fifo_we : 1; + unsigned int dma_bgrp_cull_fetch_read : 1; + unsigned int bgrp_cull_fetch_fifo_empty : 1; + unsigned int bgrp_cull_fetch_fifo_full : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG17 { + struct { +#if defined(qLittleEndian) + unsigned int save_read_q : 1; + unsigned int extend_read_q : 1; + unsigned int grp_indx_size : 2; + unsigned int cull_prim_true : 1; + unsigned int reset_bit2_q : 1; + unsigned int reset_bit1_q : 1; + unsigned int first_reg_first_q : 1; + unsigned int check_second_reg : 1; + unsigned int check_first_reg : 1; + unsigned int bgrp_cull_fetch_fifo_wdata : 1; + unsigned int save_cull_fetch_data2_q : 1; + unsigned int save_cull_fetch_data1_q : 1; + unsigned int save_byte_mask_data2_q : 1; + unsigned int save_byte_mask_data1_q : 1; + unsigned int to_second_reg_q : 1; + unsigned int roll_over_msk_q : 1; + unsigned int max_msk_ptr_q : 7; + unsigned int min_msk_ptr_q : 7; + unsigned int bgrp_trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int bgrp_trigger : 1; + unsigned int min_msk_ptr_q : 7; + unsigned int max_msk_ptr_q : 7; + unsigned int roll_over_msk_q : 1; + unsigned int to_second_reg_q : 1; + unsigned int save_byte_mask_data1_q : 1; + unsigned int save_byte_mask_data2_q : 1; + unsigned int save_cull_fetch_data1_q : 1; + unsigned int save_cull_fetch_data2_q : 1; + unsigned int bgrp_cull_fetch_fifo_wdata : 1; + unsigned int check_first_reg : 1; + unsigned int check_second_reg : 1; + unsigned int first_reg_first_q : 1; + unsigned int reset_bit1_q : 1; + unsigned int reset_bit2_q : 1; + unsigned int cull_prim_true : 1; + unsigned int grp_indx_size : 2; + unsigned int extend_read_q : 1; + unsigned int save_read_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG18 { + struct { +#if defined(qLittleEndian) + unsigned int dma_data_fifo_mem_raddr : 6; + unsigned int dma_data_fifo_mem_waddr : 6; + unsigned int dma_bgrp_byte_mask_fifo_re : 1; + unsigned int dma_bgrp_dma_data_fifo_rptr : 2; + unsigned int dma_mem_full : 1; + unsigned int dma_ram_re : 1; + unsigned int dma_ram_we : 1; + unsigned int dma_mem_empty : 1; + unsigned int dma_data_fifo_mem_re : 1; + unsigned int dma_data_fifo_mem_we : 1; + unsigned int bin_mem_full : 1; + unsigned int bin_ram_we : 1; + unsigned int bin_ram_re : 1; + unsigned int bin_mem_empty : 1; + unsigned int start_bin_req : 1; + unsigned int fetch_cull_not_used : 1; + unsigned int dma_req_xfer : 1; + unsigned int have_valid_bin_req : 1; + unsigned int have_valid_dma_req : 1; + unsigned int bgrp_dma_di_grp_cull_enable : 1; + unsigned int bgrp_dma_di_pre_fetch_cull_enable : 1; +#else /* !defined(qLittleEndian) */ + unsigned int bgrp_dma_di_pre_fetch_cull_enable : 1; + unsigned int bgrp_dma_di_grp_cull_enable : 1; + unsigned int have_valid_dma_req : 1; + unsigned int have_valid_bin_req : 1; + unsigned int dma_req_xfer : 1; + unsigned int fetch_cull_not_used : 1; + unsigned int start_bin_req : 1; + unsigned int bin_mem_empty : 1; + unsigned int bin_ram_re : 1; + unsigned int bin_ram_we : 1; + unsigned int bin_mem_full : 1; + unsigned int dma_data_fifo_mem_we : 1; + unsigned int dma_data_fifo_mem_re : 1; + unsigned int dma_mem_empty : 1; + unsigned int dma_ram_we : 1; + unsigned int dma_ram_re : 1; + unsigned int dma_mem_full : 1; + unsigned int dma_bgrp_dma_data_fifo_rptr : 2; + unsigned int dma_bgrp_byte_mask_fifo_re : 1; + unsigned int dma_data_fifo_mem_waddr : 6; + unsigned int dma_data_fifo_mem_raddr : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG20 { + struct { +#if defined(qLittleEndian) + unsigned int prim_side_indx_valid : 1; + unsigned int indx_side_fifo_empty : 1; + unsigned int indx_side_fifo_re : 1; + unsigned int indx_side_fifo_we : 1; + unsigned int indx_side_fifo_full : 1; + unsigned int prim_buffer_empty : 1; + unsigned int prim_buffer_re : 1; + unsigned int prim_buffer_we : 1; + unsigned int prim_buffer_full : 1; + unsigned int indx_buffer_empty : 1; + unsigned int indx_buffer_re : 1; + unsigned int indx_buffer_we : 1; + unsigned int indx_buffer_full : 1; + unsigned int hold_prim : 1; + unsigned int sent_cnt : 4; + unsigned int start_of_vtx_vector : 1; + unsigned int clip_s_pre_hold_prim : 1; + unsigned int clip_p_pre_hold_prim : 1; + unsigned int buffered_prim_type_event : 5; + unsigned int out_trigger : 1; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int out_trigger : 1; + unsigned int buffered_prim_type_event : 5; + unsigned int clip_p_pre_hold_prim : 1; + unsigned int clip_s_pre_hold_prim : 1; + unsigned int start_of_vtx_vector : 1; + unsigned int sent_cnt : 4; + unsigned int hold_prim : 1; + unsigned int indx_buffer_full : 1; + unsigned int indx_buffer_we : 1; + unsigned int indx_buffer_re : 1; + unsigned int indx_buffer_empty : 1; + unsigned int prim_buffer_full : 1; + unsigned int prim_buffer_we : 1; + unsigned int prim_buffer_re : 1; + unsigned int prim_buffer_empty : 1; + unsigned int indx_side_fifo_full : 1; + unsigned int indx_side_fifo_we : 1; + unsigned int indx_side_fifo_re : 1; + unsigned int indx_side_fifo_empty : 1; + unsigned int prim_side_indx_valid : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG21 { + struct { +#if defined(qLittleEndian) + unsigned int null_terminate_vtx_vector : 1; + unsigned int prim_end_of_vtx_vect_flags : 3; + unsigned int alloc_counter_q : 3; + unsigned int curr_slot_in_vtx_vect_q : 3; + unsigned int int_vtx_counter_q : 4; + unsigned int curr_dealloc_distance_q : 4; + unsigned int new_packet_q : 1; + unsigned int new_allocate_q : 1; + unsigned int num_new_unique_rel_indx : 2; + unsigned int inserted_null_prim_q : 1; + unsigned int insert_null_prim : 1; + unsigned int buffered_prim_eop_mux : 1; + unsigned int prim_buffer_empty_mux : 1; + unsigned int buffered_thread_size : 1; + unsigned int : 4; + unsigned int out_trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int out_trigger : 1; + unsigned int : 4; + unsigned int buffered_thread_size : 1; + unsigned int prim_buffer_empty_mux : 1; + unsigned int buffered_prim_eop_mux : 1; + unsigned int insert_null_prim : 1; + unsigned int inserted_null_prim_q : 1; + unsigned int num_new_unique_rel_indx : 2; + unsigned int new_allocate_q : 1; + unsigned int new_packet_q : 1; + unsigned int curr_dealloc_distance_q : 4; + unsigned int int_vtx_counter_q : 4; + unsigned int curr_slot_in_vtx_vect_q : 3; + unsigned int alloc_counter_q : 3; + unsigned int prim_end_of_vtx_vect_flags : 3; + unsigned int null_terminate_vtx_vector : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CRC_SQ_DATA { + struct { +#if defined(qLittleEndian) + unsigned int CRC : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CRC : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CRC_SQ_CTRL { + struct { +#if defined(qLittleEndian) + unsigned int CRC : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CRC : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER2_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER3_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER2_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER3_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER2_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER3_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TC_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int L2_INVALIDATE : 1; + unsigned int : 17; + unsigned int TC_L2_HIT_MISS : 2; + unsigned int : 11; + unsigned int TC_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TC_BUSY : 1; + unsigned int : 11; + unsigned int TC_L2_HIT_MISS : 2; + unsigned int : 17; + unsigned int L2_INVALIDATE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int SPARE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int SPARE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int TCO_READ_LATENCY_FIFO_PROG_DEPTH : 8; + unsigned int ETC_COLOR_ENDIAN : 1; + unsigned int SPARE : 23; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 23; + unsigned int ETC_COLOR_ENDIAN : 1; + unsigned int TCO_READ_LATENCY_FIFO_PROG_DEPTH : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP_TC_CLKGATE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int TP_BUSY_EXTEND : 3; + unsigned int TC_BUSY_EXTEND : 3; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int TC_BUSY_EXTEND : 3; + unsigned int TP_BUSY_EXTEND : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TPC_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int TPC_INPUT_BUSY : 1; + unsigned int TPC_TC_FIFO_BUSY : 1; + unsigned int TPC_STATE_FIFO_BUSY : 1; + unsigned int TPC_FETCH_FIFO_BUSY : 1; + unsigned int TPC_WALKER_PIPE_BUSY : 1; + unsigned int TPC_WALK_FIFO_BUSY : 1; + unsigned int TPC_WALKER_BUSY : 1; + unsigned int : 1; + unsigned int TPC_ALIGNER_PIPE_BUSY : 1; + unsigned int TPC_ALIGN_FIFO_BUSY : 1; + unsigned int TPC_ALIGNER_BUSY : 1; + unsigned int : 1; + unsigned int TPC_RR_FIFO_BUSY : 1; + unsigned int TPC_BLEND_PIPE_BUSY : 1; + unsigned int TPC_OUT_FIFO_BUSY : 1; + unsigned int TPC_BLEND_BUSY : 1; + unsigned int TF_TW_RTS : 1; + unsigned int TF_TW_STATE_RTS : 1; + unsigned int : 1; + unsigned int TF_TW_RTR : 1; + unsigned int TW_TA_RTS : 1; + unsigned int TW_TA_TT_RTS : 1; + unsigned int TW_TA_LAST_RTS : 1; + unsigned int TW_TA_RTR : 1; + unsigned int TA_TB_RTS : 1; + unsigned int TA_TB_TT_RTS : 1; + unsigned int : 1; + unsigned int TA_TB_RTR : 1; + unsigned int TA_TF_RTS : 1; + unsigned int TA_TF_TC_FIFO_REN : 1; + unsigned int TP_SQ_DEC : 1; + unsigned int TPC_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TPC_BUSY : 1; + unsigned int TP_SQ_DEC : 1; + unsigned int TA_TF_TC_FIFO_REN : 1; + unsigned int TA_TF_RTS : 1; + unsigned int TA_TB_RTR : 1; + unsigned int : 1; + unsigned int TA_TB_TT_RTS : 1; + unsigned int TA_TB_RTS : 1; + unsigned int TW_TA_RTR : 1; + unsigned int TW_TA_LAST_RTS : 1; + unsigned int TW_TA_TT_RTS : 1; + unsigned int TW_TA_RTS : 1; + unsigned int TF_TW_RTR : 1; + unsigned int : 1; + unsigned int TF_TW_STATE_RTS : 1; + unsigned int TF_TW_RTS : 1; + unsigned int TPC_BLEND_BUSY : 1; + unsigned int TPC_OUT_FIFO_BUSY : 1; + unsigned int TPC_BLEND_PIPE_BUSY : 1; + unsigned int TPC_RR_FIFO_BUSY : 1; + unsigned int : 1; + unsigned int TPC_ALIGNER_BUSY : 1; + unsigned int TPC_ALIGN_FIFO_BUSY : 1; + unsigned int TPC_ALIGNER_PIPE_BUSY : 1; + unsigned int : 1; + unsigned int TPC_WALKER_BUSY : 1; + unsigned int TPC_WALK_FIFO_BUSY : 1; + unsigned int TPC_WALKER_PIPE_BUSY : 1; + unsigned int TPC_FETCH_FIFO_BUSY : 1; + unsigned int TPC_STATE_FIFO_BUSY : 1; + unsigned int TPC_TC_FIFO_BUSY : 1; + unsigned int TPC_INPUT_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TPC_DEBUG0 { + struct { +#if defined(qLittleEndian) + unsigned int LOD_CNTL : 2; + unsigned int IC_CTR : 2; + unsigned int WALKER_CNTL : 4; + unsigned int ALIGNER_CNTL : 3; + unsigned int : 1; + unsigned int PREV_TC_STATE_VALID : 1; + unsigned int : 3; + unsigned int WALKER_STATE : 10; + unsigned int ALIGNER_STATE : 2; + unsigned int : 1; + unsigned int REG_CLK_EN : 1; + unsigned int TPC_CLK_EN : 1; + unsigned int SQ_TP_WAKEUP : 1; +#else /* !defined(qLittleEndian) */ + unsigned int SQ_TP_WAKEUP : 1; + unsigned int TPC_CLK_EN : 1; + unsigned int REG_CLK_EN : 1; + unsigned int : 1; + unsigned int ALIGNER_STATE : 2; + unsigned int WALKER_STATE : 10; + unsigned int : 3; + unsigned int PREV_TC_STATE_VALID : 1; + unsigned int : 1; + unsigned int ALIGNER_CNTL : 3; + unsigned int WALKER_CNTL : 4; + unsigned int IC_CTR : 2; + unsigned int LOD_CNTL : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TPC_DEBUG1 { + struct { +#if defined(qLittleEndian) + unsigned int UNUSED : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int UNUSED : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TPC_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_PRECISION : 1; + unsigned int SPARE : 31; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 31; + unsigned int BLEND_PRECISION : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int TP_INPUT_BUSY : 1; + unsigned int TP_LOD_BUSY : 1; + unsigned int TP_LOD_FIFO_BUSY : 1; + unsigned int TP_ADDR_BUSY : 1; + unsigned int TP_ALIGN_FIFO_BUSY : 1; + unsigned int TP_ALIGNER_BUSY : 1; + unsigned int TP_TC_FIFO_BUSY : 1; + unsigned int TP_RR_FIFO_BUSY : 1; + unsigned int TP_FETCH_BUSY : 1; + unsigned int TP_CH_BLEND_BUSY : 1; + unsigned int TP_TT_BUSY : 1; + unsigned int TP_HICOLOR_BUSY : 1; + unsigned int TP_BLEND_BUSY : 1; + unsigned int TP_OUT_FIFO_BUSY : 1; + unsigned int TP_OUTPUT_BUSY : 1; + unsigned int : 1; + unsigned int IN_LC_RTS : 1; + unsigned int LC_LA_RTS : 1; + unsigned int LA_FL_RTS : 1; + unsigned int FL_TA_RTS : 1; + unsigned int TA_FA_RTS : 1; + unsigned int TA_FA_TT_RTS : 1; + unsigned int FA_AL_RTS : 1; + unsigned int FA_AL_TT_RTS : 1; + unsigned int AL_TF_RTS : 1; + unsigned int AL_TF_TT_RTS : 1; + unsigned int TF_TB_RTS : 1; + unsigned int TF_TB_TT_RTS : 1; + unsigned int TB_TT_RTS : 1; + unsigned int TB_TT_TT_RESET : 1; + unsigned int TB_TO_RTS : 1; + unsigned int TP_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TP_BUSY : 1; + unsigned int TB_TO_RTS : 1; + unsigned int TB_TT_TT_RESET : 1; + unsigned int TB_TT_RTS : 1; + unsigned int TF_TB_TT_RTS : 1; + unsigned int TF_TB_RTS : 1; + unsigned int AL_TF_TT_RTS : 1; + unsigned int AL_TF_RTS : 1; + unsigned int FA_AL_TT_RTS : 1; + unsigned int FA_AL_RTS : 1; + unsigned int TA_FA_TT_RTS : 1; + unsigned int TA_FA_RTS : 1; + unsigned int FL_TA_RTS : 1; + unsigned int LA_FL_RTS : 1; + unsigned int LC_LA_RTS : 1; + unsigned int IN_LC_RTS : 1; + unsigned int : 1; + unsigned int TP_OUTPUT_BUSY : 1; + unsigned int TP_OUT_FIFO_BUSY : 1; + unsigned int TP_BLEND_BUSY : 1; + unsigned int TP_HICOLOR_BUSY : 1; + unsigned int TP_TT_BUSY : 1; + unsigned int TP_CH_BLEND_BUSY : 1; + unsigned int TP_FETCH_BUSY : 1; + unsigned int TP_RR_FIFO_BUSY : 1; + unsigned int TP_TC_FIFO_BUSY : 1; + unsigned int TP_ALIGNER_BUSY : 1; + unsigned int TP_ALIGN_FIFO_BUSY : 1; + unsigned int TP_ADDR_BUSY : 1; + unsigned int TP_LOD_FIFO_BUSY : 1; + unsigned int TP_LOD_BUSY : 1; + unsigned int TP_INPUT_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int Q_LOD_CNTL : 2; + unsigned int : 1; + unsigned int Q_SQ_TP_WAKEUP : 1; + unsigned int FL_TA_ADDRESSER_CNTL : 17; + unsigned int REG_CLK_EN : 1; + unsigned int PERF_CLK_EN : 1; + unsigned int TP_CLK_EN : 1; + unsigned int Q_WALKER_CNTL : 4; + unsigned int Q_ALIGNER_CNTL : 3; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int Q_ALIGNER_CNTL : 3; + unsigned int Q_WALKER_CNTL : 4; + unsigned int TP_CLK_EN : 1; + unsigned int PERF_CLK_EN : 1; + unsigned int REG_CLK_EN : 1; + unsigned int FL_TA_ADDRESSER_CNTL : 17; + unsigned int Q_SQ_TP_WAKEUP : 1; + unsigned int : 1; + unsigned int Q_LOD_CNTL : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int TT_MODE : 1; + unsigned int VFETCH_ADDRESS_MODE : 1; + unsigned int SPARE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 30; + unsigned int VFETCH_ADDRESS_MODE : 1; + unsigned int TT_MODE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER2_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER3_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER4_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER5_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER6_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER7_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER8_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER9_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER10_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER11_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER2_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER3_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER4_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER5_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER6_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER7_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER8_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER9_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER10_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER11_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER2_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER3_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER4_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER5_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER6_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER7_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER8_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER9_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER10_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER11_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 6; + unsigned int not_MH_TC_rtr : 1; + unsigned int TC_MH_send : 1; + unsigned int not_FG0_rtr : 1; + unsigned int : 3; + unsigned int not_TCB_TCO_rtr : 1; + unsigned int TCB_ff_stall : 1; + unsigned int TCB_miss_stall : 1; + unsigned int TCA_TCB_stall : 1; + unsigned int PF0_stall : 1; + unsigned int : 3; + unsigned int TP0_full : 1; + unsigned int : 3; + unsigned int TPC_full : 1; + unsigned int not_TPC_rtr : 1; + unsigned int tca_state_rts : 1; + unsigned int tca_rts : 1; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int tca_rts : 1; + unsigned int tca_state_rts : 1; + unsigned int not_TPC_rtr : 1; + unsigned int TPC_full : 1; + unsigned int : 3; + unsigned int TP0_full : 1; + unsigned int : 3; + unsigned int PF0_stall : 1; + unsigned int TCA_TCB_stall : 1; + unsigned int TCB_miss_stall : 1; + unsigned int TCB_ff_stall : 1; + unsigned int not_TCB_TCO_rtr : 1; + unsigned int : 3; + unsigned int not_FG0_rtr : 1; + unsigned int TC_MH_send : 1; + unsigned int not_MH_TC_rtr : 1; + unsigned int : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCA_FIFO_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int tp0_full : 1; + unsigned int : 3; + unsigned int tpc_full : 1; + unsigned int load_tpc_fifo : 1; + unsigned int load_tp_fifos : 1; + unsigned int FW_full : 1; + unsigned int not_FW_rtr0 : 1; + unsigned int : 3; + unsigned int FW_rts0 : 1; + unsigned int : 3; + unsigned int not_FW_tpc_rtr : 1; + unsigned int FW_tpc_rts : 1; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int FW_tpc_rts : 1; + unsigned int not_FW_tpc_rtr : 1; + unsigned int : 3; + unsigned int FW_rts0 : 1; + unsigned int : 3; + unsigned int not_FW_rtr0 : 1; + unsigned int FW_full : 1; + unsigned int load_tp_fifos : 1; + unsigned int load_tpc_fifo : 1; + unsigned int tpc_full : 1; + unsigned int : 3; + unsigned int tp0_full : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCA_PROBE_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int ProbeFilter_stall : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int ProbeFilter_stall : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCA_TPC_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int captue_state_rts : 1; + unsigned int capture_tca_rts : 1; + unsigned int : 18; +#else /* !defined(qLittleEndian) */ + unsigned int : 18; + unsigned int capture_tca_rts : 1; + unsigned int captue_state_rts : 1; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_CORE_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int access512 : 1; + unsigned int tiled : 1; + unsigned int : 2; + unsigned int opcode : 3; + unsigned int : 1; + unsigned int format : 6; + unsigned int : 2; + unsigned int sector_format : 5; + unsigned int : 3; + unsigned int sector_format512 : 3; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int sector_format512 : 3; + unsigned int : 3; + unsigned int sector_format : 5; + unsigned int : 2; + unsigned int format : 6; + unsigned int : 1; + unsigned int opcode : 3; + unsigned int : 2; + unsigned int tiled : 1; + unsigned int access512 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_TAG0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int mem_read_cycle : 10; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int miss_stall : 1; + unsigned int num_feee_lines : 5; + unsigned int max_misses : 3; +#else /* !defined(qLittleEndian) */ + unsigned int max_misses : 3; + unsigned int num_feee_lines : 5; + unsigned int miss_stall : 1; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int mem_read_cycle : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_TAG1_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int mem_read_cycle : 10; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int miss_stall : 1; + unsigned int num_feee_lines : 5; + unsigned int max_misses : 3; +#else /* !defined(qLittleEndian) */ + unsigned int max_misses : 3; + unsigned int num_feee_lines : 5; + unsigned int miss_stall : 1; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int mem_read_cycle : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_TAG2_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int mem_read_cycle : 10; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int miss_stall : 1; + unsigned int num_feee_lines : 5; + unsigned int max_misses : 3; +#else /* !defined(qLittleEndian) */ + unsigned int max_misses : 3; + unsigned int num_feee_lines : 5; + unsigned int miss_stall : 1; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int mem_read_cycle : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_TAG3_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int mem_read_cycle : 10; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int miss_stall : 1; + unsigned int num_feee_lines : 5; + unsigned int max_misses : 3; +#else /* !defined(qLittleEndian) */ + unsigned int max_misses : 3; + unsigned int num_feee_lines : 5; + unsigned int miss_stall : 1; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int mem_read_cycle : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int left_done : 1; + unsigned int : 1; + unsigned int fg0_sends_left : 1; + unsigned int : 1; + unsigned int one_sector_to_go_left_q : 1; + unsigned int no_sectors_to_go : 1; + unsigned int update_left : 1; + unsigned int sector_mask_left_count_q : 5; + unsigned int sector_mask_left_q : 16; + unsigned int valid_left_q : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int valid_left_q : 1; + unsigned int sector_mask_left_q : 16; + unsigned int sector_mask_left_count_q : 5; + unsigned int update_left : 1; + unsigned int no_sectors_to_go : 1; + unsigned int one_sector_to_go_left_q : 1; + unsigned int : 1; + unsigned int fg0_sends_left : 1; + unsigned int : 1; + unsigned int left_done : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_FETCH_GEN_WALKER_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 4; + unsigned int quad_sel_left : 2; + unsigned int set_sel_left : 2; + unsigned int : 3; + unsigned int right_eq_left : 1; + unsigned int ff_fg_type512 : 3; + unsigned int busy : 1; + unsigned int setquads_to_send : 4; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int setquads_to_send : 4; + unsigned int busy : 1; + unsigned int ff_fg_type512 : 3; + unsigned int right_eq_left : 1; + unsigned int : 3; + unsigned int set_sel_left : 2; + unsigned int quad_sel_left : 2; + unsigned int : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_FETCH_GEN_PIPE0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int tc0_arb_rts : 1; + unsigned int : 1; + unsigned int ga_out_rts : 1; + unsigned int : 1; + unsigned int tc_arb_format : 12; + unsigned int tc_arb_fmsopcode : 5; + unsigned int tc_arb_request_type : 2; + unsigned int busy : 1; + unsigned int fgo_busy : 1; + unsigned int ga_busy : 1; + unsigned int mc_sel_q : 2; + unsigned int valid_q : 1; + unsigned int : 1; + unsigned int arb_RTR : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int arb_RTR : 1; + unsigned int : 1; + unsigned int valid_q : 1; + unsigned int mc_sel_q : 2; + unsigned int ga_busy : 1; + unsigned int fgo_busy : 1; + unsigned int busy : 1; + unsigned int tc_arb_request_type : 2; + unsigned int tc_arb_fmsopcode : 5; + unsigned int tc_arb_format : 12; + unsigned int : 1; + unsigned int ga_out_rts : 1; + unsigned int : 1; + unsigned int tc0_arb_rts : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_INPUT0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 16; + unsigned int empty : 1; + unsigned int full : 1; + unsigned int : 2; + unsigned int valid_q1 : 1; + unsigned int cnt_q1 : 2; + unsigned int last_send_q1 : 1; + unsigned int ip_send : 1; + unsigned int ipbuf_dxt_send : 1; + unsigned int ipbuf_busy : 1; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int ipbuf_busy : 1; + unsigned int ipbuf_dxt_send : 1; + unsigned int ip_send : 1; + unsigned int last_send_q1 : 1; + unsigned int cnt_q1 : 2; + unsigned int valid_q1 : 1; + unsigned int : 2; + unsigned int full : 1; + unsigned int empty : 1; + unsigned int : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_DEGAMMA_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int dgmm_ftfconv_dgmmen : 2; + unsigned int dgmm_ctrl_dgmm8 : 1; + unsigned int dgmm_ctrl_last_send : 1; + unsigned int dgmm_ctrl_send : 1; + unsigned int dgmm_stall : 1; + unsigned int dgmm_pstate : 1; + unsigned int : 25; +#else /* !defined(qLittleEndian) */ + unsigned int : 25; + unsigned int dgmm_pstate : 1; + unsigned int dgmm_stall : 1; + unsigned int dgmm_ctrl_send : 1; + unsigned int dgmm_ctrl_last_send : 1; + unsigned int dgmm_ctrl_dgmm8 : 1; + unsigned int dgmm_ftfconv_dgmmen : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_DXTMUX_SCTARB_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 9; + unsigned int pstate : 1; + unsigned int sctrmx_rtr : 1; + unsigned int dxtc_rtr : 1; + unsigned int : 3; + unsigned int sctrarb_multcyl_send : 1; + unsigned int sctrmx0_sctrarb_rts : 1; + unsigned int : 3; + unsigned int dxtc_sctrarb_send : 1; + unsigned int : 6; + unsigned int dxtc_dgmmpd_last_send : 1; + unsigned int dxtc_dgmmpd_send : 1; + unsigned int dcmp_mux_send : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int dcmp_mux_send : 1; + unsigned int dxtc_dgmmpd_send : 1; + unsigned int dxtc_dgmmpd_last_send : 1; + unsigned int : 6; + unsigned int dxtc_sctrarb_send : 1; + unsigned int : 3; + unsigned int sctrmx0_sctrarb_rts : 1; + unsigned int sctrarb_multcyl_send : 1; + unsigned int : 3; + unsigned int dxtc_rtr : 1; + unsigned int sctrmx_rtr : 1; + unsigned int pstate : 1; + unsigned int : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_DXTC_ARB_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 4; + unsigned int n0_stall : 1; + unsigned int pstate : 1; + unsigned int arb_dcmp01_last_send : 1; + unsigned int arb_dcmp01_cnt : 2; + unsigned int arb_dcmp01_sector : 3; + unsigned int arb_dcmp01_cacheline : 6; + unsigned int arb_dcmp01_format : 12; + unsigned int arb_dcmp01_send : 1; + unsigned int n0_dxt2_4_types : 1; +#else /* !defined(qLittleEndian) */ + unsigned int n0_dxt2_4_types : 1; + unsigned int arb_dcmp01_send : 1; + unsigned int arb_dcmp01_format : 12; + unsigned int arb_dcmp01_cacheline : 6; + unsigned int arb_dcmp01_sector : 3; + unsigned int arb_dcmp01_cnt : 2; + unsigned int arb_dcmp01_last_send : 1; + unsigned int pstate : 1; + unsigned int n0_stall : 1; + unsigned int : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_STALLS_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 10; + unsigned int not_multcyl_sctrarb_rtr : 1; + unsigned int not_sctrmx0_sctrarb_rtr : 1; + unsigned int : 5; + unsigned int not_dcmp0_arb_rtr : 1; + unsigned int not_dgmmpd_dxtc_rtr : 1; + unsigned int not_mux_dcmp_rtr : 1; + unsigned int : 11; + unsigned int not_incoming_rtr : 1; +#else /* !defined(qLittleEndian) */ + unsigned int not_incoming_rtr : 1; + unsigned int : 11; + unsigned int not_mux_dcmp_rtr : 1; + unsigned int not_dgmmpd_dxtc_rtr : 1; + unsigned int not_dcmp0_arb_rtr : 1; + unsigned int : 5; + unsigned int not_sctrmx0_sctrarb_rtr : 1; + unsigned int not_multcyl_sctrarb_rtr : 1; + unsigned int : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCO_STALLS_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int quad0_sg_crd_RTR : 1; + unsigned int quad0_rl_sg_RTR : 1; + unsigned int quad0_TCO_TCB_rtr_d : 1; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int quad0_TCO_TCB_rtr_d : 1; + unsigned int quad0_rl_sg_RTR : 1; + unsigned int quad0_sg_crd_RTR : 1; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCO_QUAD0_DEBUG0 { + struct { +#if defined(qLittleEndian) + unsigned int rl_sg_sector_format : 8; + unsigned int rl_sg_end_of_sample : 1; + unsigned int rl_sg_rtr : 1; + unsigned int rl_sg_rts : 1; + unsigned int sg_crd_end_of_sample : 1; + unsigned int sg_crd_rtr : 1; + unsigned int sg_crd_rts : 1; + unsigned int : 2; + unsigned int stageN1_valid_q : 1; + unsigned int : 7; + unsigned int read_cache_q : 1; + unsigned int cache_read_RTR : 1; + unsigned int all_sectors_written_set3 : 1; + unsigned int all_sectors_written_set2 : 1; + unsigned int all_sectors_written_set1 : 1; + unsigned int all_sectors_written_set0 : 1; + unsigned int busy : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int busy : 1; + unsigned int all_sectors_written_set0 : 1; + unsigned int all_sectors_written_set1 : 1; + unsigned int all_sectors_written_set2 : 1; + unsigned int all_sectors_written_set3 : 1; + unsigned int cache_read_RTR : 1; + unsigned int read_cache_q : 1; + unsigned int : 7; + unsigned int stageN1_valid_q : 1; + unsigned int : 2; + unsigned int sg_crd_rts : 1; + unsigned int sg_crd_rtr : 1; + unsigned int sg_crd_end_of_sample : 1; + unsigned int rl_sg_rts : 1; + unsigned int rl_sg_rtr : 1; + unsigned int rl_sg_end_of_sample : 1; + unsigned int rl_sg_sector_format : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCO_QUAD0_DEBUG1 { + struct { +#if defined(qLittleEndian) + unsigned int fifo_busy : 1; + unsigned int empty : 1; + unsigned int full : 1; + unsigned int write_enable : 1; + unsigned int fifo_write_ptr : 7; + unsigned int fifo_read_ptr : 7; + unsigned int : 2; + unsigned int cache_read_busy : 1; + unsigned int latency_fifo_busy : 1; + unsigned int input_quad_busy : 1; + unsigned int tco_quad_pipe_busy : 1; + unsigned int TCB_TCO_rtr_d : 1; + unsigned int TCB_TCO_xfc_q : 1; + unsigned int rl_sg_rtr : 1; + unsigned int rl_sg_rts : 1; + unsigned int sg_crd_rtr : 1; + unsigned int sg_crd_rts : 1; + unsigned int TCO_TCB_read_xfc : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int TCO_TCB_read_xfc : 1; + unsigned int sg_crd_rts : 1; + unsigned int sg_crd_rtr : 1; + unsigned int rl_sg_rts : 1; + unsigned int rl_sg_rtr : 1; + unsigned int TCB_TCO_xfc_q : 1; + unsigned int TCB_TCO_rtr_d : 1; + unsigned int tco_quad_pipe_busy : 1; + unsigned int input_quad_busy : 1; + unsigned int latency_fifo_busy : 1; + unsigned int cache_read_busy : 1; + unsigned int : 2; + unsigned int fifo_read_ptr : 7; + unsigned int fifo_write_ptr : 7; + unsigned int write_enable : 1; + unsigned int full : 1; + unsigned int empty : 1; + unsigned int fifo_busy : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_GPR_MANAGEMENT { + struct { +#if defined(qLittleEndian) + unsigned int REG_DYNAMIC : 1; + unsigned int : 3; + unsigned int REG_SIZE_PIX : 7; + unsigned int : 1; + unsigned int REG_SIZE_VTX : 7; + unsigned int : 13; +#else /* !defined(qLittleEndian) */ + unsigned int : 13; + unsigned int REG_SIZE_VTX : 7; + unsigned int : 1; + unsigned int REG_SIZE_PIX : 7; + unsigned int : 3; + unsigned int REG_DYNAMIC : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FLOW_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int INPUT_ARBITRATION_POLICY : 2; + unsigned int : 2; + unsigned int ONE_THREAD : 1; + unsigned int : 3; + unsigned int ONE_ALU : 1; + unsigned int : 3; + unsigned int CF_WR_BASE : 4; + unsigned int NO_PV_PS : 1; + unsigned int NO_LOOP_EXIT : 1; + unsigned int NO_CEXEC_OPTIMIZE : 1; + unsigned int TEXTURE_ARBITRATION_POLICY : 2; + unsigned int VC_ARBITRATION_POLICY : 1; + unsigned int ALU_ARBITRATION_POLICY : 1; + unsigned int NO_ARB_EJECT : 1; + unsigned int NO_CFS_EJECT : 1; + unsigned int POS_EXP_PRIORITY : 1; + unsigned int NO_EARLY_THREAD_TERMINATION : 1; + unsigned int PS_PREFETCH_COLOR_ALLOC : 1; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int PS_PREFETCH_COLOR_ALLOC : 1; + unsigned int NO_EARLY_THREAD_TERMINATION : 1; + unsigned int POS_EXP_PRIORITY : 1; + unsigned int NO_CFS_EJECT : 1; + unsigned int NO_ARB_EJECT : 1; + unsigned int ALU_ARBITRATION_POLICY : 1; + unsigned int VC_ARBITRATION_POLICY : 1; + unsigned int TEXTURE_ARBITRATION_POLICY : 2; + unsigned int NO_CEXEC_OPTIMIZE : 1; + unsigned int NO_LOOP_EXIT : 1; + unsigned int NO_PV_PS : 1; + unsigned int CF_WR_BASE : 4; + unsigned int : 3; + unsigned int ONE_ALU : 1; + unsigned int : 3; + unsigned int ONE_THREAD : 1; + unsigned int : 2; + unsigned int INPUT_ARBITRATION_POLICY : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INST_STORE_MANAGMENT { + struct { +#if defined(qLittleEndian) + unsigned int INST_BASE_PIX : 12; + unsigned int : 4; + unsigned int INST_BASE_VTX : 12; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int INST_BASE_VTX : 12; + unsigned int : 4; + unsigned int INST_BASE_PIX : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_RESOURCE_MANAGMENT { + struct { +#if defined(qLittleEndian) + unsigned int VTX_THREAD_BUF_ENTRIES : 8; + unsigned int PIX_THREAD_BUF_ENTRIES : 8; + unsigned int EXPORT_BUF_ENTRIES : 9; + unsigned int : 7; +#else /* !defined(qLittleEndian) */ + unsigned int : 7; + unsigned int EXPORT_BUF_ENTRIES : 9; + unsigned int PIX_THREAD_BUF_ENTRIES : 8; + unsigned int VTX_THREAD_BUF_ENTRIES : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_EO_RT { + struct { +#if defined(qLittleEndian) + unsigned int EO_CONSTANTS_RT : 8; + unsigned int : 8; + unsigned int EO_TSTATE_RT : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int EO_TSTATE_RT : 8; + unsigned int : 8; + unsigned int EO_CONSTANTS_RT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_MISC { + struct { +#if defined(qLittleEndian) + unsigned int DB_ALUCST_SIZE : 11; + unsigned int : 1; + unsigned int DB_TSTATE_SIZE : 8; + unsigned int DB_READ_CTX : 1; + unsigned int RESERVED : 2; + unsigned int DB_READ_MEMORY : 2; + unsigned int DB_WEN_MEMORY_0 : 1; + unsigned int DB_WEN_MEMORY_1 : 1; + unsigned int DB_WEN_MEMORY_2 : 1; + unsigned int DB_WEN_MEMORY_3 : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int DB_WEN_MEMORY_3 : 1; + unsigned int DB_WEN_MEMORY_2 : 1; + unsigned int DB_WEN_MEMORY_1 : 1; + unsigned int DB_WEN_MEMORY_0 : 1; + unsigned int DB_READ_MEMORY : 2; + unsigned int RESERVED : 2; + unsigned int DB_READ_CTX : 1; + unsigned int DB_TSTATE_SIZE : 8; + unsigned int : 1; + unsigned int DB_ALUCST_SIZE : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_ACTIVITY_METER_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int TIMEBASE : 8; + unsigned int THRESHOLD_LOW : 8; + unsigned int THRESHOLD_HIGH : 8; + unsigned int SPARE : 8; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 8; + unsigned int THRESHOLD_HIGH : 8; + unsigned int THRESHOLD_LOW : 8; + unsigned int TIMEBASE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_ACTIVITY_METER_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int PERCENT_BUSY : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERCENT_BUSY : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INPUT_ARB_PRIORITY { + struct { +#if defined(qLittleEndian) + unsigned int PC_AVAIL_WEIGHT : 3; + unsigned int PC_AVAIL_SIGN : 1; + unsigned int SX_AVAIL_WEIGHT : 3; + unsigned int SX_AVAIL_SIGN : 1; + unsigned int THRESHOLD : 10; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int THRESHOLD : 10; + unsigned int SX_AVAIL_SIGN : 1; + unsigned int SX_AVAIL_WEIGHT : 3; + unsigned int PC_AVAIL_SIGN : 1; + unsigned int PC_AVAIL_WEIGHT : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_THREAD_ARB_PRIORITY { + struct { +#if defined(qLittleEndian) + unsigned int PC_AVAIL_WEIGHT : 3; + unsigned int PC_AVAIL_SIGN : 1; + unsigned int SX_AVAIL_WEIGHT : 3; + unsigned int SX_AVAIL_SIGN : 1; + unsigned int THRESHOLD : 10; + unsigned int RESERVED : 2; + unsigned int VS_PRIORITIZE_SERIAL : 1; + unsigned int PS_PRIORITIZE_SERIAL : 1; + unsigned int USE_SERIAL_COUNT_THRESHOLD : 1; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int USE_SERIAL_COUNT_THRESHOLD : 1; + unsigned int PS_PRIORITIZE_SERIAL : 1; + unsigned int VS_PRIORITIZE_SERIAL : 1; + unsigned int RESERVED : 2; + unsigned int THRESHOLD : 10; + unsigned int SX_AVAIL_SIGN : 1; + unsigned int SX_AVAIL_WEIGHT : 3; + unsigned int PC_AVAIL_SIGN : 1; + unsigned int PC_AVAIL_WEIGHT : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_INPUT_FSM { + struct { +#if defined(qLittleEndian) + unsigned int VC_VSR_LD : 3; + unsigned int RESERVED : 1; + unsigned int VC_GPR_LD : 4; + unsigned int PC_PISM : 3; + unsigned int RESERVED1 : 1; + unsigned int PC_AS : 3; + unsigned int PC_INTERP_CNT : 5; + unsigned int PC_GPR_SIZE : 8; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int PC_GPR_SIZE : 8; + unsigned int PC_INTERP_CNT : 5; + unsigned int PC_AS : 3; + unsigned int RESERVED1 : 1; + unsigned int PC_PISM : 3; + unsigned int VC_GPR_LD : 4; + unsigned int RESERVED : 1; + unsigned int VC_VSR_LD : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_CONST_MGR_FSM { + struct { +#if defined(qLittleEndian) + unsigned int TEX_CONST_EVENT_STATE : 5; + unsigned int RESERVED1 : 3; + unsigned int ALU_CONST_EVENT_STATE : 5; + unsigned int RESERVED2 : 3; + unsigned int ALU_CONST_CNTX_VALID : 2; + unsigned int TEX_CONST_CNTX_VALID : 2; + unsigned int CNTX0_VTX_EVENT_DONE : 1; + unsigned int CNTX0_PIX_EVENT_DONE : 1; + unsigned int CNTX1_VTX_EVENT_DONE : 1; + unsigned int CNTX1_PIX_EVENT_DONE : 1; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int CNTX1_PIX_EVENT_DONE : 1; + unsigned int CNTX1_VTX_EVENT_DONE : 1; + unsigned int CNTX0_PIX_EVENT_DONE : 1; + unsigned int CNTX0_VTX_EVENT_DONE : 1; + unsigned int TEX_CONST_CNTX_VALID : 2; + unsigned int ALU_CONST_CNTX_VALID : 2; + unsigned int RESERVED2 : 3; + unsigned int ALU_CONST_EVENT_STATE : 5; + unsigned int RESERVED1 : 3; + unsigned int TEX_CONST_EVENT_STATE : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_TP_FSM { + struct { +#if defined(qLittleEndian) + unsigned int EX_TP : 3; + unsigned int RESERVED0 : 1; + unsigned int CF_TP : 4; + unsigned int IF_TP : 3; + unsigned int RESERVED1 : 1; + unsigned int TIS_TP : 2; + unsigned int RESERVED2 : 2; + unsigned int GS_TP : 2; + unsigned int RESERVED3 : 2; + unsigned int FCR_TP : 2; + unsigned int RESERVED4 : 2; + unsigned int FCS_TP : 2; + unsigned int RESERVED5 : 2; + unsigned int ARB_TR_TP : 3; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int ARB_TR_TP : 3; + unsigned int RESERVED5 : 2; + unsigned int FCS_TP : 2; + unsigned int RESERVED4 : 2; + unsigned int FCR_TP : 2; + unsigned int RESERVED3 : 2; + unsigned int GS_TP : 2; + unsigned int RESERVED2 : 2; + unsigned int TIS_TP : 2; + unsigned int RESERVED1 : 1; + unsigned int IF_TP : 3; + unsigned int CF_TP : 4; + unsigned int RESERVED0 : 1; + unsigned int EX_TP : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_FSM_ALU_0 { + struct { +#if defined(qLittleEndian) + unsigned int EX_ALU_0 : 3; + unsigned int RESERVED0 : 1; + unsigned int CF_ALU_0 : 4; + unsigned int IF_ALU_0 : 3; + unsigned int RESERVED1 : 1; + unsigned int DU1_ALU_0 : 3; + unsigned int RESERVED2 : 1; + unsigned int DU0_ALU_0 : 3; + unsigned int RESERVED3 : 1; + unsigned int AIS_ALU_0 : 3; + unsigned int RESERVED4 : 1; + unsigned int ACS_ALU_0 : 3; + unsigned int RESERVED5 : 1; + unsigned int ARB_TR_ALU : 3; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int ARB_TR_ALU : 3; + unsigned int RESERVED5 : 1; + unsigned int ACS_ALU_0 : 3; + unsigned int RESERVED4 : 1; + unsigned int AIS_ALU_0 : 3; + unsigned int RESERVED3 : 1; + unsigned int DU0_ALU_0 : 3; + unsigned int RESERVED2 : 1; + unsigned int DU1_ALU_0 : 3; + unsigned int RESERVED1 : 1; + unsigned int IF_ALU_0 : 3; + unsigned int CF_ALU_0 : 4; + unsigned int RESERVED0 : 1; + unsigned int EX_ALU_0 : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_FSM_ALU_1 { + struct { +#if defined(qLittleEndian) + unsigned int EX_ALU_0 : 3; + unsigned int RESERVED0 : 1; + unsigned int CF_ALU_0 : 4; + unsigned int IF_ALU_0 : 3; + unsigned int RESERVED1 : 1; + unsigned int DU1_ALU_0 : 3; + unsigned int RESERVED2 : 1; + unsigned int DU0_ALU_0 : 3; + unsigned int RESERVED3 : 1; + unsigned int AIS_ALU_0 : 3; + unsigned int RESERVED4 : 1; + unsigned int ACS_ALU_0 : 3; + unsigned int RESERVED5 : 1; + unsigned int ARB_TR_ALU : 3; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int ARB_TR_ALU : 3; + unsigned int RESERVED5 : 1; + unsigned int ACS_ALU_0 : 3; + unsigned int RESERVED4 : 1; + unsigned int AIS_ALU_0 : 3; + unsigned int RESERVED3 : 1; + unsigned int DU0_ALU_0 : 3; + unsigned int RESERVED2 : 1; + unsigned int DU1_ALU_0 : 3; + unsigned int RESERVED1 : 1; + unsigned int IF_ALU_0 : 3; + unsigned int CF_ALU_0 : 4; + unsigned int RESERVED0 : 1; + unsigned int EX_ALU_0 : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_EXP_ALLOC { + struct { +#if defined(qLittleEndian) + unsigned int POS_BUF_AVAIL : 4; + unsigned int COLOR_BUF_AVAIL : 8; + unsigned int EA_BUF_AVAIL : 3; + unsigned int RESERVED : 1; + unsigned int ALLOC_TBL_BUF_AVAIL : 6; + unsigned int : 10; +#else /* !defined(qLittleEndian) */ + unsigned int : 10; + unsigned int ALLOC_TBL_BUF_AVAIL : 6; + unsigned int RESERVED : 1; + unsigned int EA_BUF_AVAIL : 3; + unsigned int COLOR_BUF_AVAIL : 8; + unsigned int POS_BUF_AVAIL : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PTR_BUFF { + struct { +#if defined(qLittleEndian) + unsigned int END_OF_BUFFER : 1; + unsigned int DEALLOC_CNT : 4; + unsigned int QUAL_NEW_VECTOR : 1; + unsigned int EVENT_CONTEXT_ID : 3; + unsigned int SC_EVENT_ID : 5; + unsigned int QUAL_EVENT : 1; + unsigned int PRIM_TYPE_POLYGON : 1; + unsigned int EF_EMPTY : 1; + unsigned int VTX_SYNC_CNT : 11; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int VTX_SYNC_CNT : 11; + unsigned int EF_EMPTY : 1; + unsigned int PRIM_TYPE_POLYGON : 1; + unsigned int QUAL_EVENT : 1; + unsigned int SC_EVENT_ID : 5; + unsigned int EVENT_CONTEXT_ID : 3; + unsigned int QUAL_NEW_VECTOR : 1; + unsigned int DEALLOC_CNT : 4; + unsigned int END_OF_BUFFER : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_GPR_VTX { + struct { +#if defined(qLittleEndian) + unsigned int VTX_TAIL_PTR : 7; + unsigned int RESERVED : 1; + unsigned int VTX_HEAD_PTR : 7; + unsigned int RESERVED1 : 1; + unsigned int VTX_MAX : 7; + unsigned int RESERVED2 : 1; + unsigned int VTX_FREE : 7; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int VTX_FREE : 7; + unsigned int RESERVED2 : 1; + unsigned int VTX_MAX : 7; + unsigned int RESERVED1 : 1; + unsigned int VTX_HEAD_PTR : 7; + unsigned int RESERVED : 1; + unsigned int VTX_TAIL_PTR : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_GPR_PIX { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TAIL_PTR : 7; + unsigned int RESERVED : 1; + unsigned int PIX_HEAD_PTR : 7; + unsigned int RESERVED1 : 1; + unsigned int PIX_MAX : 7; + unsigned int RESERVED2 : 1; + unsigned int PIX_FREE : 7; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int PIX_FREE : 7; + unsigned int RESERVED2 : 1; + unsigned int PIX_MAX : 7; + unsigned int RESERVED1 : 1; + unsigned int PIX_HEAD_PTR : 7; + unsigned int RESERVED : 1; + unsigned int PIX_TAIL_PTR : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_TB_STATUS_SEL { + struct { +#if defined(qLittleEndian) + unsigned int VTX_TB_STATUS_REG_SEL : 4; + unsigned int VTX_TB_STATE_MEM_DW_SEL : 3; + unsigned int VTX_TB_STATE_MEM_RD_ADDR : 4; + unsigned int VTX_TB_STATE_MEM_RD_EN : 1; + unsigned int PIX_TB_STATE_MEM_RD_EN : 1; + unsigned int : 1; + unsigned int DEBUG_BUS_TRIGGER_SEL : 2; + unsigned int PIX_TB_STATUS_REG_SEL : 4; + unsigned int PIX_TB_STATE_MEM_DW_SEL : 3; + unsigned int PIX_TB_STATE_MEM_RD_ADDR : 6; + unsigned int VC_THREAD_BUF_DLY : 2; + unsigned int DISABLE_STRICT_CTX_SYNC : 1; +#else /* !defined(qLittleEndian) */ + unsigned int DISABLE_STRICT_CTX_SYNC : 1; + unsigned int VC_THREAD_BUF_DLY : 2; + unsigned int PIX_TB_STATE_MEM_RD_ADDR : 6; + unsigned int PIX_TB_STATE_MEM_DW_SEL : 3; + unsigned int PIX_TB_STATUS_REG_SEL : 4; + unsigned int DEBUG_BUS_TRIGGER_SEL : 2; + unsigned int : 1; + unsigned int PIX_TB_STATE_MEM_RD_EN : 1; + unsigned int VTX_TB_STATE_MEM_RD_EN : 1; + unsigned int VTX_TB_STATE_MEM_RD_ADDR : 4; + unsigned int VTX_TB_STATE_MEM_DW_SEL : 3; + unsigned int VTX_TB_STATUS_REG_SEL : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_VTX_TB_0 { + struct { +#if defined(qLittleEndian) + unsigned int VTX_HEAD_PTR_Q : 4; + unsigned int TAIL_PTR_Q : 4; + unsigned int FULL_CNT_Q : 4; + unsigned int NXT_POS_ALLOC_CNT : 4; + unsigned int NXT_PC_ALLOC_CNT : 4; + unsigned int SX_EVENT_FULL : 1; + unsigned int BUSY_Q : 1; + unsigned int : 10; +#else /* !defined(qLittleEndian) */ + unsigned int : 10; + unsigned int BUSY_Q : 1; + unsigned int SX_EVENT_FULL : 1; + unsigned int NXT_PC_ALLOC_CNT : 4; + unsigned int NXT_POS_ALLOC_CNT : 4; + unsigned int FULL_CNT_Q : 4; + unsigned int TAIL_PTR_Q : 4; + unsigned int VTX_HEAD_PTR_Q : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_VTX_TB_1 { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_PTR : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int VS_DONE_PTR : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_VTX_TB_STATUS_REG { + struct { +#if defined(qLittleEndian) + unsigned int VS_STATUS_REG : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_STATUS_REG : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_VTX_TB_STATE_MEM { + struct { +#if defined(qLittleEndian) + unsigned int VS_STATE_MEM : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_STATE_MEM : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_0 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_HEAD_PTR : 6; + unsigned int TAIL_PTR : 6; + unsigned int FULL_CNT : 7; + unsigned int NXT_PIX_ALLOC_CNT : 6; + unsigned int NXT_PIX_EXP_CNT : 6; + unsigned int BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int BUSY : 1; + unsigned int NXT_PIX_EXP_CNT : 6; + unsigned int NXT_PIX_ALLOC_CNT : 6; + unsigned int FULL_CNT : 7; + unsigned int TAIL_PTR : 6; + unsigned int PIX_HEAD_PTR : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATUS_REG_0 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATUS_REG_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATUS_REG_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATUS_REG_1 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATUS_REG_1 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATUS_REG_1 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATUS_REG_2 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATUS_REG_2 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATUS_REG_2 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATUS_REG_3 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATUS_REG_3 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATUS_REG_3 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATE_MEM { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATE_MEM : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATE_MEM : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER2_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER3_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER2_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER2_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER3_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER3_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SX_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SX_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SX_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_ALU_0 { + struct { +#if defined(qLittleEndian) + unsigned int VECTOR_RESULT : 6; + unsigned int CST_0_ABS_MOD : 1; + unsigned int LOW_PRECISION_16B_FP : 1; + unsigned int SCALAR_RESULT : 6; + unsigned int SST_0_ABS_MOD : 1; + unsigned int EXPORT_DATA : 1; + unsigned int VECTOR_WRT_MSK : 4; + unsigned int SCALAR_WRT_MSK : 4; + unsigned int VECTOR_CLAMP : 1; + unsigned int SCALAR_CLAMP : 1; + unsigned int SCALAR_OPCODE : 6; +#else /* !defined(qLittleEndian) */ + unsigned int SCALAR_OPCODE : 6; + unsigned int SCALAR_CLAMP : 1; + unsigned int VECTOR_CLAMP : 1; + unsigned int SCALAR_WRT_MSK : 4; + unsigned int VECTOR_WRT_MSK : 4; + unsigned int EXPORT_DATA : 1; + unsigned int SST_0_ABS_MOD : 1; + unsigned int SCALAR_RESULT : 6; + unsigned int LOW_PRECISION_16B_FP : 1; + unsigned int CST_0_ABS_MOD : 1; + unsigned int VECTOR_RESULT : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_ALU_1 { + struct { +#if defined(qLittleEndian) + unsigned int SRC_C_SWIZZLE_R : 2; + unsigned int SRC_C_SWIZZLE_G : 2; + unsigned int SRC_C_SWIZZLE_B : 2; + unsigned int SRC_C_SWIZZLE_A : 2; + unsigned int SRC_B_SWIZZLE_R : 2; + unsigned int SRC_B_SWIZZLE_G : 2; + unsigned int SRC_B_SWIZZLE_B : 2; + unsigned int SRC_B_SWIZZLE_A : 2; + unsigned int SRC_A_SWIZZLE_R : 2; + unsigned int SRC_A_SWIZZLE_G : 2; + unsigned int SRC_A_SWIZZLE_B : 2; + unsigned int SRC_A_SWIZZLE_A : 2; + unsigned int SRC_C_ARG_MOD : 1; + unsigned int SRC_B_ARG_MOD : 1; + unsigned int SRC_A_ARG_MOD : 1; + unsigned int PRED_SELECT : 2; + unsigned int RELATIVE_ADDR : 1; + unsigned int CONST_1_REL_ABS : 1; + unsigned int CONST_0_REL_ABS : 1; +#else /* !defined(qLittleEndian) */ + unsigned int CONST_0_REL_ABS : 1; + unsigned int CONST_1_REL_ABS : 1; + unsigned int RELATIVE_ADDR : 1; + unsigned int PRED_SELECT : 2; + unsigned int SRC_A_ARG_MOD : 1; + unsigned int SRC_B_ARG_MOD : 1; + unsigned int SRC_C_ARG_MOD : 1; + unsigned int SRC_A_SWIZZLE_A : 2; + unsigned int SRC_A_SWIZZLE_B : 2; + unsigned int SRC_A_SWIZZLE_G : 2; + unsigned int SRC_A_SWIZZLE_R : 2; + unsigned int SRC_B_SWIZZLE_A : 2; + unsigned int SRC_B_SWIZZLE_B : 2; + unsigned int SRC_B_SWIZZLE_G : 2; + unsigned int SRC_B_SWIZZLE_R : 2; + unsigned int SRC_C_SWIZZLE_A : 2; + unsigned int SRC_C_SWIZZLE_B : 2; + unsigned int SRC_C_SWIZZLE_G : 2; + unsigned int SRC_C_SWIZZLE_R : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_ALU_2 { + struct { +#if defined(qLittleEndian) + unsigned int SRC_C_REG_PTR : 6; + unsigned int REG_SELECT_C : 1; + unsigned int REG_ABS_MOD_C : 1; + unsigned int SRC_B_REG_PTR : 6; + unsigned int REG_SELECT_B : 1; + unsigned int REG_ABS_MOD_B : 1; + unsigned int SRC_A_REG_PTR : 6; + unsigned int REG_SELECT_A : 1; + unsigned int REG_ABS_MOD_A : 1; + unsigned int VECTOR_OPCODE : 5; + unsigned int SRC_C_SEL : 1; + unsigned int SRC_B_SEL : 1; + unsigned int SRC_A_SEL : 1; +#else /* !defined(qLittleEndian) */ + unsigned int SRC_A_SEL : 1; + unsigned int SRC_B_SEL : 1; + unsigned int SRC_C_SEL : 1; + unsigned int VECTOR_OPCODE : 5; + unsigned int REG_ABS_MOD_A : 1; + unsigned int REG_SELECT_A : 1; + unsigned int SRC_A_REG_PTR : 6; + unsigned int REG_ABS_MOD_B : 1; + unsigned int REG_SELECT_B : 1; + unsigned int SRC_B_REG_PTR : 6; + unsigned int REG_ABS_MOD_C : 1; + unsigned int REG_SELECT_C : 1; + unsigned int SRC_C_REG_PTR : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_EXEC_0 { + struct { +#if defined(qLittleEndian) + unsigned int ADDRESS : 9; + unsigned int RESERVED : 3; + unsigned int COUNT : 3; + unsigned int YIELD : 1; + unsigned int INST_TYPE_0 : 1; + unsigned int INST_SERIAL_0 : 1; + unsigned int INST_TYPE_1 : 1; + unsigned int INST_SERIAL_1 : 1; + unsigned int INST_TYPE_2 : 1; + unsigned int INST_SERIAL_2 : 1; + unsigned int INST_TYPE_3 : 1; + unsigned int INST_SERIAL_3 : 1; + unsigned int INST_TYPE_4 : 1; + unsigned int INST_SERIAL_4 : 1; + unsigned int INST_TYPE_5 : 1; + unsigned int INST_SERIAL_5 : 1; + unsigned int INST_VC_0 : 1; + unsigned int INST_VC_1 : 1; + unsigned int INST_VC_2 : 1; + unsigned int INST_VC_3 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int INST_VC_3 : 1; + unsigned int INST_VC_2 : 1; + unsigned int INST_VC_1 : 1; + unsigned int INST_VC_0 : 1; + unsigned int INST_SERIAL_5 : 1; + unsigned int INST_TYPE_5 : 1; + unsigned int INST_SERIAL_4 : 1; + unsigned int INST_TYPE_4 : 1; + unsigned int INST_SERIAL_3 : 1; + unsigned int INST_TYPE_3 : 1; + unsigned int INST_SERIAL_2 : 1; + unsigned int INST_TYPE_2 : 1; + unsigned int INST_SERIAL_1 : 1; + unsigned int INST_TYPE_1 : 1; + unsigned int INST_SERIAL_0 : 1; + unsigned int INST_TYPE_0 : 1; + unsigned int YIELD : 1; + unsigned int COUNT : 3; + unsigned int RESERVED : 3; + unsigned int ADDRESS : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_EXEC_1 { + struct { +#if defined(qLittleEndian) + unsigned int INST_VC_4 : 1; + unsigned int INST_VC_5 : 1; + unsigned int BOOL_ADDR : 8; + unsigned int CONDITION : 1; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; + unsigned int ADDRESS : 9; + unsigned int RESERVED : 3; + unsigned int COUNT : 3; + unsigned int YIELD : 1; +#else /* !defined(qLittleEndian) */ + unsigned int YIELD : 1; + unsigned int COUNT : 3; + unsigned int RESERVED : 3; + unsigned int ADDRESS : 9; + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int CONDITION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int INST_VC_5 : 1; + unsigned int INST_VC_4 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_EXEC_2 { + struct { +#if defined(qLittleEndian) + unsigned int INST_TYPE_0 : 1; + unsigned int INST_SERIAL_0 : 1; + unsigned int INST_TYPE_1 : 1; + unsigned int INST_SERIAL_1 : 1; + unsigned int INST_TYPE_2 : 1; + unsigned int INST_SERIAL_2 : 1; + unsigned int INST_TYPE_3 : 1; + unsigned int INST_SERIAL_3 : 1; + unsigned int INST_TYPE_4 : 1; + unsigned int INST_SERIAL_4 : 1; + unsigned int INST_TYPE_5 : 1; + unsigned int INST_SERIAL_5 : 1; + unsigned int INST_VC_0 : 1; + unsigned int INST_VC_1 : 1; + unsigned int INST_VC_2 : 1; + unsigned int INST_VC_3 : 1; + unsigned int INST_VC_4 : 1; + unsigned int INST_VC_5 : 1; + unsigned int BOOL_ADDR : 8; + unsigned int CONDITION : 1; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; +#else /* !defined(qLittleEndian) */ + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int CONDITION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int INST_VC_5 : 1; + unsigned int INST_VC_4 : 1; + unsigned int INST_VC_3 : 1; + unsigned int INST_VC_2 : 1; + unsigned int INST_VC_1 : 1; + unsigned int INST_VC_0 : 1; + unsigned int INST_SERIAL_5 : 1; + unsigned int INST_TYPE_5 : 1; + unsigned int INST_SERIAL_4 : 1; + unsigned int INST_TYPE_4 : 1; + unsigned int INST_SERIAL_3 : 1; + unsigned int INST_TYPE_3 : 1; + unsigned int INST_SERIAL_2 : 1; + unsigned int INST_TYPE_2 : 1; + unsigned int INST_SERIAL_1 : 1; + unsigned int INST_TYPE_1 : 1; + unsigned int INST_SERIAL_0 : 1; + unsigned int INST_TYPE_0 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_LOOP_0 { + struct { +#if defined(qLittleEndian) + unsigned int ADDRESS : 10; + unsigned int RESERVED_0 : 6; + unsigned int LOOP_ID : 5; + unsigned int RESERVED_1 : 11; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_1 : 11; + unsigned int LOOP_ID : 5; + unsigned int RESERVED_0 : 6; + unsigned int ADDRESS : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_LOOP_1 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED_0 : 11; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; + unsigned int ADDRESS : 10; + unsigned int RESERVED_1 : 6; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_1 : 6; + unsigned int ADDRESS : 10; + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int RESERVED_0 : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_LOOP_2 { + struct { +#if defined(qLittleEndian) + unsigned int LOOP_ID : 5; + unsigned int RESERVED : 22; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; +#else /* !defined(qLittleEndian) */ + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int RESERVED : 22; + unsigned int LOOP_ID : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_JMP_CALL_0 { + struct { +#if defined(qLittleEndian) + unsigned int ADDRESS : 10; + unsigned int RESERVED_0 : 3; + unsigned int FORCE_CALL : 1; + unsigned int PREDICATED_JMP : 1; + unsigned int RESERVED_1 : 17; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_1 : 17; + unsigned int PREDICATED_JMP : 1; + unsigned int FORCE_CALL : 1; + unsigned int RESERVED_0 : 3; + unsigned int ADDRESS : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_JMP_CALL_1 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED_0 : 1; + unsigned int DIRECTION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int CONDITION : 1; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; + unsigned int ADDRESS : 10; + unsigned int RESERVED_1 : 3; + unsigned int FORCE_CALL : 1; + unsigned int RESERVED_2 : 2; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_2 : 2; + unsigned int FORCE_CALL : 1; + unsigned int RESERVED_1 : 3; + unsigned int ADDRESS : 10; + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int CONDITION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int DIRECTION : 1; + unsigned int RESERVED_0 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_JMP_CALL_2 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED : 17; + unsigned int DIRECTION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int CONDITION : 1; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; +#else /* !defined(qLittleEndian) */ + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int CONDITION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int DIRECTION : 1; + unsigned int RESERVED : 17; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_ALLOC_0 { + struct { +#if defined(qLittleEndian) + unsigned int SIZE : 4; + unsigned int RESERVED : 28; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED : 28; + unsigned int SIZE : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_ALLOC_1 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED_0 : 8; + unsigned int NO_SERIAL : 1; + unsigned int BUFFER_SELECT : 2; + unsigned int ALLOC_MODE : 1; + unsigned int OPCODE : 4; + unsigned int SIZE : 4; + unsigned int RESERVED_1 : 12; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_1 : 12; + unsigned int SIZE : 4; + unsigned int OPCODE : 4; + unsigned int ALLOC_MODE : 1; + unsigned int BUFFER_SELECT : 2; + unsigned int NO_SERIAL : 1; + unsigned int RESERVED_0 : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_ALLOC_2 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED : 24; + unsigned int NO_SERIAL : 1; + unsigned int BUFFER_SELECT : 2; + unsigned int ALLOC_MODE : 1; + unsigned int OPCODE : 4; +#else /* !defined(qLittleEndian) */ + unsigned int OPCODE : 4; + unsigned int ALLOC_MODE : 1; + unsigned int BUFFER_SELECT : 2; + unsigned int NO_SERIAL : 1; + unsigned int RESERVED : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_TFETCH_0 { + struct { +#if defined(qLittleEndian) + unsigned int OPCODE : 5; + unsigned int SRC_GPR : 6; + unsigned int SRC_GPR_AM : 1; + unsigned int DST_GPR : 6; + unsigned int DST_GPR_AM : 1; + unsigned int FETCH_VALID_ONLY : 1; + unsigned int CONST_INDEX : 5; + unsigned int TX_COORD_DENORM : 1; + unsigned int SRC_SEL_X : 2; + unsigned int SRC_SEL_Y : 2; + unsigned int SRC_SEL_Z : 2; +#else /* !defined(qLittleEndian) */ + unsigned int SRC_SEL_Z : 2; + unsigned int SRC_SEL_Y : 2; + unsigned int SRC_SEL_X : 2; + unsigned int TX_COORD_DENORM : 1; + unsigned int CONST_INDEX : 5; + unsigned int FETCH_VALID_ONLY : 1; + unsigned int DST_GPR_AM : 1; + unsigned int DST_GPR : 6; + unsigned int SRC_GPR_AM : 1; + unsigned int SRC_GPR : 6; + unsigned int OPCODE : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_TFETCH_1 { + struct { +#if defined(qLittleEndian) + unsigned int DST_SEL_X : 3; + unsigned int DST_SEL_Y : 3; + unsigned int DST_SEL_Z : 3; + unsigned int DST_SEL_W : 3; + unsigned int MAG_FILTER : 2; + unsigned int MIN_FILTER : 2; + unsigned int MIP_FILTER : 2; + unsigned int ANISO_FILTER : 3; + unsigned int ARBITRARY_FILTER : 3; + unsigned int VOL_MAG_FILTER : 2; + unsigned int VOL_MIN_FILTER : 2; + unsigned int USE_COMP_LOD : 1; + unsigned int USE_REG_LOD : 2; + unsigned int PRED_SELECT : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PRED_SELECT : 1; + unsigned int USE_REG_LOD : 2; + unsigned int USE_COMP_LOD : 1; + unsigned int VOL_MIN_FILTER : 2; + unsigned int VOL_MAG_FILTER : 2; + unsigned int ARBITRARY_FILTER : 3; + unsigned int ANISO_FILTER : 3; + unsigned int MIP_FILTER : 2; + unsigned int MIN_FILTER : 2; + unsigned int MAG_FILTER : 2; + unsigned int DST_SEL_W : 3; + unsigned int DST_SEL_Z : 3; + unsigned int DST_SEL_Y : 3; + unsigned int DST_SEL_X : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_TFETCH_2 { + struct { +#if defined(qLittleEndian) + unsigned int USE_REG_GRADIENTS : 1; + unsigned int SAMPLE_LOCATION : 1; + unsigned int LOD_BIAS : 7; + unsigned int UNUSED : 7; + unsigned int OFFSET_X : 5; + unsigned int OFFSET_Y : 5; + unsigned int OFFSET_Z : 5; + unsigned int PRED_CONDITION : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PRED_CONDITION : 1; + unsigned int OFFSET_Z : 5; + unsigned int OFFSET_Y : 5; + unsigned int OFFSET_X : 5; + unsigned int UNUSED : 7; + unsigned int LOD_BIAS : 7; + unsigned int SAMPLE_LOCATION : 1; + unsigned int USE_REG_GRADIENTS : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_VFETCH_0 { + struct { +#if defined(qLittleEndian) + unsigned int OPCODE : 5; + unsigned int SRC_GPR : 6; + unsigned int SRC_GPR_AM : 1; + unsigned int DST_GPR : 6; + unsigned int DST_GPR_AM : 1; + unsigned int MUST_BE_ONE : 1; + unsigned int CONST_INDEX : 5; + unsigned int CONST_INDEX_SEL : 2; + unsigned int : 3; + unsigned int SRC_SEL : 2; +#else /* !defined(qLittleEndian) */ + unsigned int SRC_SEL : 2; + unsigned int : 3; + unsigned int CONST_INDEX_SEL : 2; + unsigned int CONST_INDEX : 5; + unsigned int MUST_BE_ONE : 1; + unsigned int DST_GPR_AM : 1; + unsigned int DST_GPR : 6; + unsigned int SRC_GPR_AM : 1; + unsigned int SRC_GPR : 6; + unsigned int OPCODE : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_VFETCH_1 { + struct { +#if defined(qLittleEndian) + unsigned int DST_SEL_X : 3; + unsigned int DST_SEL_Y : 3; + unsigned int DST_SEL_Z : 3; + unsigned int DST_SEL_W : 3; + unsigned int FORMAT_COMP_ALL : 1; + unsigned int NUM_FORMAT_ALL : 1; + unsigned int SIGNED_RF_MODE_ALL : 1; + unsigned int : 1; + unsigned int DATA_FORMAT : 6; + unsigned int : 1; + unsigned int EXP_ADJUST_ALL : 7; + unsigned int : 1; + unsigned int PRED_SELECT : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PRED_SELECT : 1; + unsigned int : 1; + unsigned int EXP_ADJUST_ALL : 7; + unsigned int : 1; + unsigned int DATA_FORMAT : 6; + unsigned int : 1; + unsigned int SIGNED_RF_MODE_ALL : 1; + unsigned int NUM_FORMAT_ALL : 1; + unsigned int FORMAT_COMP_ALL : 1; + unsigned int DST_SEL_W : 3; + unsigned int DST_SEL_Z : 3; + unsigned int DST_SEL_Y : 3; + unsigned int DST_SEL_X : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_VFETCH_2 { + struct { +#if defined(qLittleEndian) + unsigned int STRIDE : 8; + unsigned int : 8; + unsigned int OFFSET : 8; + unsigned int : 7; + unsigned int PRED_CONDITION : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PRED_CONDITION : 1; + unsigned int : 7; + unsigned int OFFSET : 8; + unsigned int : 8; + unsigned int STRIDE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_0 { + struct { +#if defined(qLittleEndian) + unsigned int RED : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RED : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_1 { + struct { +#if defined(qLittleEndian) + unsigned int GREEN : 32; +#else /* !defined(qLittleEndian) */ + unsigned int GREEN : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_2 { + struct { +#if defined(qLittleEndian) + unsigned int BLUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BLUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_3 { + struct { +#if defined(qLittleEndian) + unsigned int ALPHA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ALPHA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_0 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_1 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_2 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_3 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_4 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_5 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_VFETCH_0 { + struct { +#if defined(qLittleEndian) + unsigned int TYPE : 1; + unsigned int STATE : 1; + unsigned int BASE_ADDRESS : 30; +#else /* !defined(qLittleEndian) */ + unsigned int BASE_ADDRESS : 30; + unsigned int STATE : 1; + unsigned int TYPE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_VFETCH_1 { + struct { +#if defined(qLittleEndian) + unsigned int ENDIAN_SWAP : 2; + unsigned int LIMIT_ADDRESS : 30; +#else /* !defined(qLittleEndian) */ + unsigned int LIMIT_ADDRESS : 30; + unsigned int ENDIAN_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_T2 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_T3 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_BOOLEANS { + struct { +#if defined(qLittleEndian) + unsigned int CF_BOOLEANS_0 : 8; + unsigned int CF_BOOLEANS_1 : 8; + unsigned int CF_BOOLEANS_2 : 8; + unsigned int CF_BOOLEANS_3 : 8; +#else /* !defined(qLittleEndian) */ + unsigned int CF_BOOLEANS_3 : 8; + unsigned int CF_BOOLEANS_2 : 8; + unsigned int CF_BOOLEANS_1 : 8; + unsigned int CF_BOOLEANS_0 : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_LOOP { + struct { +#if defined(qLittleEndian) + unsigned int CF_LOOP_COUNT : 8; + unsigned int CF_LOOP_START : 8; + unsigned int CF_LOOP_STEP : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int CF_LOOP_STEP : 8; + unsigned int CF_LOOP_START : 8; + unsigned int CF_LOOP_COUNT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_RT_0 { + struct { +#if defined(qLittleEndian) + unsigned int RED : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RED : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_RT_1 { + struct { +#if defined(qLittleEndian) + unsigned int GREEN : 32; +#else /* !defined(qLittleEndian) */ + unsigned int GREEN : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_RT_2 { + struct { +#if defined(qLittleEndian) + unsigned int BLUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BLUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_RT_3 { + struct { +#if defined(qLittleEndian) + unsigned int ALPHA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ALPHA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_0 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_1 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_2 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_3 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_4 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_5 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_RT_BOOLEANS { + struct { +#if defined(qLittleEndian) + unsigned int CF_BOOLEANS_0 : 8; + unsigned int CF_BOOLEANS_1 : 8; + unsigned int CF_BOOLEANS_2 : 8; + unsigned int CF_BOOLEANS_3 : 8; +#else /* !defined(qLittleEndian) */ + unsigned int CF_BOOLEANS_3 : 8; + unsigned int CF_BOOLEANS_2 : 8; + unsigned int CF_BOOLEANS_1 : 8; + unsigned int CF_BOOLEANS_0 : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_RT_LOOP { + struct { +#if defined(qLittleEndian) + unsigned int CF_LOOP_COUNT : 8; + unsigned int CF_LOOP_START : 8; + unsigned int CF_LOOP_STEP : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int CF_LOOP_STEP : 8; + unsigned int CF_LOOP_START : 8; + unsigned int CF_LOOP_COUNT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_VS_PROGRAM { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 12; + unsigned int SIZE : 12; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int SIZE : 12; + unsigned int BASE : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PS_PROGRAM { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 12; + unsigned int SIZE : 12; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int SIZE : 12; + unsigned int BASE : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_PROGRAM_SIZE { + struct { +#if defined(qLittleEndian) + unsigned int VS_CF_SIZE : 11; + unsigned int : 1; + unsigned int PS_CF_SIZE : 11; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int PS_CF_SIZE : 11; + unsigned int : 1; + unsigned int VS_CF_SIZE : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INTERPOLATOR_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int PARAM_SHADE : 16; + unsigned int SAMPLING_PATTERN : 16; +#else /* !defined(qLittleEndian) */ + unsigned int SAMPLING_PATTERN : 16; + unsigned int PARAM_SHADE : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PROGRAM_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int VS_NUM_REG : 6; + unsigned int : 2; + unsigned int PS_NUM_REG : 6; + unsigned int : 2; + unsigned int VS_RESOURCE : 1; + unsigned int PS_RESOURCE : 1; + unsigned int PARAM_GEN : 1; + unsigned int GEN_INDEX_PIX : 1; + unsigned int VS_EXPORT_COUNT : 4; + unsigned int VS_EXPORT_MODE : 3; + unsigned int PS_EXPORT_MODE : 4; + unsigned int GEN_INDEX_VTX : 1; +#else /* !defined(qLittleEndian) */ + unsigned int GEN_INDEX_VTX : 1; + unsigned int PS_EXPORT_MODE : 4; + unsigned int VS_EXPORT_MODE : 3; + unsigned int VS_EXPORT_COUNT : 4; + unsigned int GEN_INDEX_PIX : 1; + unsigned int PARAM_GEN : 1; + unsigned int PS_RESOURCE : 1; + unsigned int VS_RESOURCE : 1; + unsigned int : 2; + unsigned int PS_NUM_REG : 6; + unsigned int : 2; + unsigned int VS_NUM_REG : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_WRAPPING_0 { + struct { +#if defined(qLittleEndian) + unsigned int PARAM_WRAP_0 : 4; + unsigned int PARAM_WRAP_1 : 4; + unsigned int PARAM_WRAP_2 : 4; + unsigned int PARAM_WRAP_3 : 4; + unsigned int PARAM_WRAP_4 : 4; + unsigned int PARAM_WRAP_5 : 4; + unsigned int PARAM_WRAP_6 : 4; + unsigned int PARAM_WRAP_7 : 4; +#else /* !defined(qLittleEndian) */ + unsigned int PARAM_WRAP_7 : 4; + unsigned int PARAM_WRAP_6 : 4; + unsigned int PARAM_WRAP_5 : 4; + unsigned int PARAM_WRAP_4 : 4; + unsigned int PARAM_WRAP_3 : 4; + unsigned int PARAM_WRAP_2 : 4; + unsigned int PARAM_WRAP_1 : 4; + unsigned int PARAM_WRAP_0 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_WRAPPING_1 { + struct { +#if defined(qLittleEndian) + unsigned int PARAM_WRAP_8 : 4; + unsigned int PARAM_WRAP_9 : 4; + unsigned int PARAM_WRAP_10 : 4; + unsigned int PARAM_WRAP_11 : 4; + unsigned int PARAM_WRAP_12 : 4; + unsigned int PARAM_WRAP_13 : 4; + unsigned int PARAM_WRAP_14 : 4; + unsigned int PARAM_WRAP_15 : 4; +#else /* !defined(qLittleEndian) */ + unsigned int PARAM_WRAP_15 : 4; + unsigned int PARAM_WRAP_14 : 4; + unsigned int PARAM_WRAP_13 : 4; + unsigned int PARAM_WRAP_12 : 4; + unsigned int PARAM_WRAP_11 : 4; + unsigned int PARAM_WRAP_10 : 4; + unsigned int PARAM_WRAP_9 : 4; + unsigned int PARAM_WRAP_8 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_VS_CONST { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 9; + unsigned int : 3; + unsigned int SIZE : 9; + unsigned int : 11; +#else /* !defined(qLittleEndian) */ + unsigned int : 11; + unsigned int SIZE : 9; + unsigned int : 3; + unsigned int BASE : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PS_CONST { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 9; + unsigned int : 3; + unsigned int SIZE : 9; + unsigned int : 11; +#else /* !defined(qLittleEndian) */ + unsigned int : 11; + unsigned int SIZE : 9; + unsigned int : 3; + unsigned int BASE : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONTEXT_MISC { + struct { +#if defined(qLittleEndian) + unsigned int INST_PRED_OPTIMIZE : 1; + unsigned int SC_OUTPUT_SCREEN_XY : 1; + unsigned int SC_SAMPLE_CNTL : 2; + unsigned int : 4; + unsigned int PARAM_GEN_POS : 8; + unsigned int PERFCOUNTER_REF : 1; + unsigned int YEILD_OPTIMIZE : 1; + unsigned int TX_CACHE_SEL : 1; + unsigned int : 13; +#else /* !defined(qLittleEndian) */ + unsigned int : 13; + unsigned int TX_CACHE_SEL : 1; + unsigned int YEILD_OPTIMIZE : 1; + unsigned int PERFCOUNTER_REF : 1; + unsigned int PARAM_GEN_POS : 8; + unsigned int : 4; + unsigned int SC_SAMPLE_CNTL : 2; + unsigned int SC_OUTPUT_SCREEN_XY : 1; + unsigned int INST_PRED_OPTIMIZE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_RD_BASE { + struct { +#if defined(qLittleEndian) + unsigned int RD_BASE : 3; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int RD_BASE : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_MISC_0 { + struct { +#if defined(qLittleEndian) + unsigned int DB_PROB_ON : 1; + unsigned int : 3; + unsigned int DB_PROB_BREAK : 1; + unsigned int : 3; + unsigned int DB_PROB_ADDR : 11; + unsigned int : 5; + unsigned int DB_PROB_COUNT : 8; +#else /* !defined(qLittleEndian) */ + unsigned int DB_PROB_COUNT : 8; + unsigned int : 5; + unsigned int DB_PROB_ADDR : 11; + unsigned int : 3; + unsigned int DB_PROB_BREAK : 1; + unsigned int : 3; + unsigned int DB_PROB_ON : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_MISC_1 { + struct { +#if defined(qLittleEndian) + unsigned int DB_ON_PIX : 1; + unsigned int DB_ON_VTX : 1; + unsigned int : 6; + unsigned int DB_INST_COUNT : 8; + unsigned int DB_BREAK_ADDR : 11; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int DB_BREAK_ADDR : 11; + unsigned int DB_INST_COUNT : 8; + unsigned int : 6; + unsigned int DB_ON_VTX : 1; + unsigned int DB_ON_PIX : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_ARBITER_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int SAME_PAGE_LIMIT : 6; + unsigned int SAME_PAGE_GRANULARITY : 1; + unsigned int L1_ARB_ENABLE : 1; + unsigned int L1_ARB_HOLD_ENABLE : 1; + unsigned int L2_ARB_CONTROL : 1; + unsigned int PAGE_SIZE : 3; + unsigned int TC_REORDER_ENABLE : 1; + unsigned int TC_ARB_HOLD_ENABLE : 1; + unsigned int IN_FLIGHT_LIMIT_ENABLE : 1; + unsigned int IN_FLIGHT_LIMIT : 6; + unsigned int CP_CLNT_ENABLE : 1; + unsigned int VGT_CLNT_ENABLE : 1; + unsigned int TC_CLNT_ENABLE : 1; + unsigned int RB_CLNT_ENABLE : 1; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int RB_CLNT_ENABLE : 1; + unsigned int TC_CLNT_ENABLE : 1; + unsigned int VGT_CLNT_ENABLE : 1; + unsigned int CP_CLNT_ENABLE : 1; + unsigned int IN_FLIGHT_LIMIT : 6; + unsigned int IN_FLIGHT_LIMIT_ENABLE : 1; + unsigned int TC_ARB_HOLD_ENABLE : 1; + unsigned int TC_REORDER_ENABLE : 1; + unsigned int PAGE_SIZE : 3; + unsigned int L2_ARB_CONTROL : 1; + unsigned int L1_ARB_HOLD_ENABLE : 1; + unsigned int L1_ARB_ENABLE : 1; + unsigned int SAME_PAGE_GRANULARITY : 1; + unsigned int SAME_PAGE_LIMIT : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_CLNT_AXI_ID_REUSE { + struct { +#if defined(qLittleEndian) + unsigned int CPw_ID : 3; + unsigned int RESERVED1 : 1; + unsigned int RBw_ID : 3; + unsigned int RESERVED2 : 1; + unsigned int MMUr_ID : 3; + unsigned int : 21; +#else /* !defined(qLittleEndian) */ + unsigned int : 21; + unsigned int MMUr_ID : 3; + unsigned int RESERVED2 : 1; + unsigned int RBw_ID : 3; + unsigned int RESERVED1 : 1; + unsigned int CPw_ID : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_INTERRUPT_MASK { + struct { +#if defined(qLittleEndian) + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int AXI_READ_ERROR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_INTERRUPT_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int AXI_READ_ERROR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_INTERRUPT_CLEAR { + struct { +#if defined(qLittleEndian) + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int AXI_READ_ERROR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_AXI_ERROR { + struct { +#if defined(qLittleEndian) + unsigned int AXI_READ_ID : 3; + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_WRITE_ID : 3; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int AXI_WRITE_ID : 3; + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_READ_ID : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER0_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int N_VALUE : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int N_VALUE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER1_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int N_VALUE : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int N_VALUE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_CTRL { + struct { +#if defined(qLittleEndian) + unsigned int INDEX : 6; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int INDEX : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG00 { + struct { +#if defined(qLittleEndian) + unsigned int MH_BUSY : 1; + unsigned int TRANS_OUTSTANDING : 1; + unsigned int CP_REQUEST : 1; + unsigned int VGT_REQUEST : 1; + unsigned int TC_REQUEST : 1; + unsigned int TC_CAM_EMPTY : 1; + unsigned int TC_CAM_FULL : 1; + unsigned int TCD_EMPTY : 1; + unsigned int TCD_FULL : 1; + unsigned int RB_REQUEST : 1; + unsigned int MH_CLK_EN_STATE : 1; + unsigned int ARQ_EMPTY : 1; + unsigned int ARQ_FULL : 1; + unsigned int WDB_EMPTY : 1; + unsigned int WDB_FULL : 1; + unsigned int AXI_AVALID : 1; + unsigned int AXI_AREADY : 1; + unsigned int AXI_ARVALID : 1; + unsigned int AXI_ARREADY : 1; + unsigned int AXI_WVALID : 1; + unsigned int AXI_WREADY : 1; + unsigned int AXI_RVALID : 1; + unsigned int AXI_RREADY : 1; + unsigned int AXI_BVALID : 1; + unsigned int AXI_BREADY : 1; + unsigned int AXI_HALT_REQ : 1; + unsigned int AXI_HALT_ACK : 1; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int AXI_HALT_ACK : 1; + unsigned int AXI_HALT_REQ : 1; + unsigned int AXI_BREADY : 1; + unsigned int AXI_BVALID : 1; + unsigned int AXI_RREADY : 1; + unsigned int AXI_RVALID : 1; + unsigned int AXI_WREADY : 1; + unsigned int AXI_WVALID : 1; + unsigned int AXI_ARREADY : 1; + unsigned int AXI_ARVALID : 1; + unsigned int AXI_AREADY : 1; + unsigned int AXI_AVALID : 1; + unsigned int WDB_FULL : 1; + unsigned int WDB_EMPTY : 1; + unsigned int ARQ_FULL : 1; + unsigned int ARQ_EMPTY : 1; + unsigned int MH_CLK_EN_STATE : 1; + unsigned int RB_REQUEST : 1; + unsigned int TCD_FULL : 1; + unsigned int TCD_EMPTY : 1; + unsigned int TC_CAM_FULL : 1; + unsigned int TC_CAM_EMPTY : 1; + unsigned int TC_REQUEST : 1; + unsigned int VGT_REQUEST : 1; + unsigned int CP_REQUEST : 1; + unsigned int TRANS_OUTSTANDING : 1; + unsigned int MH_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG01 { + struct { +#if defined(qLittleEndian) + unsigned int CP_SEND_q : 1; + unsigned int CP_RTR_q : 1; + unsigned int CP_WRITE_q : 1; + unsigned int CP_TAG_q : 3; + unsigned int CP_BE_q : 8; + unsigned int VGT_SEND_q : 1; + unsigned int VGT_RTR_q : 1; + unsigned int VGT_TAG_q : 1; + unsigned int TC_SEND_q : 1; + unsigned int TC_RTR_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_written : 1; + unsigned int RB_SEND_q : 1; + unsigned int RB_RTR_q : 1; + unsigned int RB_BE_q : 8; +#else /* !defined(qLittleEndian) */ + unsigned int RB_BE_q : 8; + unsigned int RB_RTR_q : 1; + unsigned int RB_SEND_q : 1; + unsigned int TC_MH_written : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_RTR_q : 1; + unsigned int TC_SEND_q : 1; + unsigned int VGT_TAG_q : 1; + unsigned int VGT_RTR_q : 1; + unsigned int VGT_SEND_q : 1; + unsigned int CP_BE_q : 8; + unsigned int CP_TAG_q : 3; + unsigned int CP_WRITE_q : 1; + unsigned int CP_RTR_q : 1; + unsigned int CP_SEND_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG02 { + struct { +#if defined(qLittleEndian) + unsigned int MH_CP_grb_send : 1; + unsigned int MH_VGT_grb_send : 1; + unsigned int MH_TC_mcsend : 1; + unsigned int MH_CLNT_rlast : 1; + unsigned int MH_CLNT_tag : 3; + unsigned int RDC_RID : 3; + unsigned int RDC_RRESP : 2; + unsigned int MH_CP_writeclean : 1; + unsigned int MH_RB_writeclean : 1; + unsigned int BRC_BID : 3; + unsigned int BRC_BRESP : 2; + unsigned int : 13; +#else /* !defined(qLittleEndian) */ + unsigned int : 13; + unsigned int BRC_BRESP : 2; + unsigned int BRC_BID : 3; + unsigned int MH_RB_writeclean : 1; + unsigned int MH_CP_writeclean : 1; + unsigned int RDC_RRESP : 2; + unsigned int RDC_RID : 3; + unsigned int MH_CLNT_tag : 3; + unsigned int MH_CLNT_rlast : 1; + unsigned int MH_TC_mcsend : 1; + unsigned int MH_VGT_grb_send : 1; + unsigned int MH_CP_grb_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG03 { + struct { +#if defined(qLittleEndian) + unsigned int MH_CLNT_data_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int MH_CLNT_data_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG04 { + struct { +#if defined(qLittleEndian) + unsigned int MH_CLNT_data_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int MH_CLNT_data_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG05 { + struct { +#if defined(qLittleEndian) + unsigned int CP_MH_send : 1; + unsigned int CP_MH_write : 1; + unsigned int CP_MH_tag : 3; + unsigned int CP_MH_ad_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int CP_MH_ad_31_5 : 27; + unsigned int CP_MH_tag : 3; + unsigned int CP_MH_write : 1; + unsigned int CP_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG06 { + struct { +#if defined(qLittleEndian) + unsigned int CP_MH_data_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CP_MH_data_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG07 { + struct { +#if defined(qLittleEndian) + unsigned int CP_MH_data_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CP_MH_data_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG08 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 3; + unsigned int VGT_MH_send : 1; + unsigned int VGT_MH_tagbe : 1; + unsigned int VGT_MH_ad_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int VGT_MH_ad_31_5 : 27; + unsigned int VGT_MH_tagbe : 1; + unsigned int VGT_MH_send : 1; + unsigned int ALWAYS_ZERO : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG09 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 2; + unsigned int TC_MH_send : 1; + unsigned int TC_MH_mask : 2; + unsigned int TC_MH_addr_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int TC_MH_addr_31_5 : 27; + unsigned int TC_MH_mask : 2; + unsigned int TC_MH_send : 1; + unsigned int ALWAYS_ZERO : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG10 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_info : 25; + unsigned int TC_MH_send : 1; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int TC_MH_send : 1; + unsigned int TC_MH_info : 25; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG11 { + struct { +#if defined(qLittleEndian) + unsigned int MH_TC_mcinfo : 25; + unsigned int MH_TC_mcinfo_send : 1; + unsigned int TC_MH_written : 1; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int TC_MH_written : 1; + unsigned int MH_TC_mcinfo_send : 1; + unsigned int MH_TC_mcinfo : 25; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG12 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 2; + unsigned int TC_ROQ_SEND : 1; + unsigned int TC_ROQ_MASK : 2; + unsigned int TC_ROQ_ADDR_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int TC_ROQ_ADDR_31_5 : 27; + unsigned int TC_ROQ_MASK : 2; + unsigned int TC_ROQ_SEND : 1; + unsigned int ALWAYS_ZERO : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG13 { + struct { +#if defined(qLittleEndian) + unsigned int TC_ROQ_INFO : 25; + unsigned int TC_ROQ_SEND : 1; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int TC_ROQ_SEND : 1; + unsigned int TC_ROQ_INFO : 25; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG14 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 4; + unsigned int RB_MH_send : 1; + unsigned int RB_MH_addr_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int RB_MH_addr_31_5 : 27; + unsigned int RB_MH_send : 1; + unsigned int ALWAYS_ZERO : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG15 { + struct { +#if defined(qLittleEndian) + unsigned int RB_MH_data_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RB_MH_data_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG16 { + struct { +#if defined(qLittleEndian) + unsigned int RB_MH_data_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RB_MH_data_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG17 { + struct { +#if defined(qLittleEndian) + unsigned int AVALID_q : 1; + unsigned int AREADY_q : 1; + unsigned int AID_q : 3; + unsigned int ALEN_q_2_0 : 3; + unsigned int ARVALID_q : 1; + unsigned int ARREADY_q : 1; + unsigned int ARID_q : 3; + unsigned int ARLEN_q_1_0 : 2; + unsigned int RVALID_q : 1; + unsigned int RREADY_q : 1; + unsigned int RLAST_q : 1; + unsigned int RID_q : 3; + unsigned int WVALID_q : 1; + unsigned int WREADY_q : 1; + unsigned int WLAST_q : 1; + unsigned int WID_q : 3; + unsigned int BVALID_q : 1; + unsigned int BREADY_q : 1; + unsigned int BID_q : 3; +#else /* !defined(qLittleEndian) */ + unsigned int BID_q : 3; + unsigned int BREADY_q : 1; + unsigned int BVALID_q : 1; + unsigned int WID_q : 3; + unsigned int WLAST_q : 1; + unsigned int WREADY_q : 1; + unsigned int WVALID_q : 1; + unsigned int RID_q : 3; + unsigned int RLAST_q : 1; + unsigned int RREADY_q : 1; + unsigned int RVALID_q : 1; + unsigned int ARLEN_q_1_0 : 2; + unsigned int ARID_q : 3; + unsigned int ARREADY_q : 1; + unsigned int ARVALID_q : 1; + unsigned int ALEN_q_2_0 : 3; + unsigned int AID_q : 3; + unsigned int AREADY_q : 1; + unsigned int AVALID_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG18 { + struct { +#if defined(qLittleEndian) + unsigned int AVALID_q : 1; + unsigned int AREADY_q : 1; + unsigned int AID_q : 3; + unsigned int ALEN_q_1_0 : 2; + unsigned int ARVALID_q : 1; + unsigned int ARREADY_q : 1; + unsigned int ARID_q : 3; + unsigned int ARLEN_q_1_1 : 1; + unsigned int WVALID_q : 1; + unsigned int WREADY_q : 1; + unsigned int WLAST_q : 1; + unsigned int WID_q : 3; + unsigned int WSTRB_q : 8; + unsigned int BVALID_q : 1; + unsigned int BREADY_q : 1; + unsigned int BID_q : 3; +#else /* !defined(qLittleEndian) */ + unsigned int BID_q : 3; + unsigned int BREADY_q : 1; + unsigned int BVALID_q : 1; + unsigned int WSTRB_q : 8; + unsigned int WID_q : 3; + unsigned int WLAST_q : 1; + unsigned int WREADY_q : 1; + unsigned int WVALID_q : 1; + unsigned int ARLEN_q_1_1 : 1; + unsigned int ARID_q : 3; + unsigned int ARREADY_q : 1; + unsigned int ARVALID_q : 1; + unsigned int ALEN_q_1_0 : 2; + unsigned int AID_q : 3; + unsigned int AREADY_q : 1; + unsigned int AVALID_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG19 { + struct { +#if defined(qLittleEndian) + unsigned int ARC_CTRL_RE_q : 1; + unsigned int CTRL_ARC_ID : 3; + unsigned int CTRL_ARC_PAD : 28; +#else /* !defined(qLittleEndian) */ + unsigned int CTRL_ARC_PAD : 28; + unsigned int CTRL_ARC_ID : 3; + unsigned int ARC_CTRL_RE_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG20 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 2; + unsigned int REG_A : 14; + unsigned int REG_RE : 1; + unsigned int REG_WE : 1; + unsigned int BLOCK_RS : 1; + unsigned int : 13; +#else /* !defined(qLittleEndian) */ + unsigned int : 13; + unsigned int BLOCK_RS : 1; + unsigned int REG_WE : 1; + unsigned int REG_RE : 1; + unsigned int REG_A : 14; + unsigned int ALWAYS_ZERO : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG21 { + struct { +#if defined(qLittleEndian) + unsigned int REG_WD : 32; +#else /* !defined(qLittleEndian) */ + unsigned int REG_WD : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG22 { + struct { +#if defined(qLittleEndian) + unsigned int CIB_MH_axi_halt_req : 1; + unsigned int MH_CIB_axi_halt_ack : 1; + unsigned int MH_RBBM_busy : 1; + unsigned int MH_CIB_mh_clk_en_int : 1; + unsigned int MH_CIB_mmu_clk_en_int : 1; + unsigned int MH_CIB_tcroq_clk_en_int : 1; + unsigned int GAT_CLK_ENA : 1; + unsigned int AXI_RDY_ENA : 1; + unsigned int RBBM_MH_clk_en_override : 1; + unsigned int CNT_q : 6; + unsigned int TCD_EMPTY_q : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int MH_BUSY_d : 1; + unsigned int ANY_CLNT_BUSY : 1; + unsigned int MH_MMU_INVALIDATE_INVALIDATE_ALL : 1; + unsigned int CP_SEND_q : 1; + unsigned int CP_RTR_q : 1; + unsigned int VGT_SEND_q : 1; + unsigned int VGT_RTR_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int RB_SEND_q : 1; + unsigned int RB_RTR_q : 1; + unsigned int RDC_VALID : 1; + unsigned int RDC_RLAST : 1; + unsigned int TLBMISS_VALID : 1; + unsigned int BRC_VALID : 1; +#else /* !defined(qLittleEndian) */ + unsigned int BRC_VALID : 1; + unsigned int TLBMISS_VALID : 1; + unsigned int RDC_RLAST : 1; + unsigned int RDC_VALID : 1; + unsigned int RB_RTR_q : 1; + unsigned int RB_SEND_q : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int VGT_RTR_q : 1; + unsigned int VGT_SEND_q : 1; + unsigned int CP_RTR_q : 1; + unsigned int CP_SEND_q : 1; + unsigned int MH_MMU_INVALIDATE_INVALIDATE_ALL : 1; + unsigned int ANY_CLNT_BUSY : 1; + unsigned int MH_BUSY_d : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TCD_EMPTY_q : 1; + unsigned int CNT_q : 6; + unsigned int RBBM_MH_clk_en_override : 1; + unsigned int AXI_RDY_ENA : 1; + unsigned int GAT_CLK_ENA : 1; + unsigned int MH_CIB_tcroq_clk_en_int : 1; + unsigned int MH_CIB_mmu_clk_en_int : 1; + unsigned int MH_CIB_mh_clk_en_int : 1; + unsigned int MH_RBBM_busy : 1; + unsigned int MH_CIB_axi_halt_ack : 1; + unsigned int CIB_MH_axi_halt_req : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG23 { + struct { +#if defined(qLittleEndian) + unsigned int EFF2_FP_WINNER : 3; + unsigned int EFF2_LRU_WINNER_out : 3; + unsigned int EFF1_WINNER : 3; + unsigned int ARB_WINNER : 3; + unsigned int ARB_WINNER_q : 3; + unsigned int EFF1_WIN : 1; + unsigned int KILL_EFF1 : 1; + unsigned int ARB_HOLD : 1; + unsigned int ARB_RTR_q : 1; + unsigned int CP_SEND_QUAL : 1; + unsigned int VGT_SEND_QUAL : 1; + unsigned int TC_SEND_QUAL : 1; + unsigned int TC_SEND_EFF1_QUAL : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int ARB_QUAL : 1; + unsigned int CP_EFF1_REQ : 1; + unsigned int VGT_EFF1_REQ : 1; + unsigned int TC_EFF1_REQ : 1; + unsigned int RB_EFF1_REQ : 1; + unsigned int ANY_SAME_ROW_BANK : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int TCHOLD_IP_q : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TCHOLD_IP_q : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int ANY_SAME_ROW_BANK : 1; + unsigned int RB_EFF1_REQ : 1; + unsigned int TC_EFF1_REQ : 1; + unsigned int VGT_EFF1_REQ : 1; + unsigned int CP_EFF1_REQ : 1; + unsigned int ARB_QUAL : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int TC_SEND_EFF1_QUAL : 1; + unsigned int TC_SEND_QUAL : 1; + unsigned int VGT_SEND_QUAL : 1; + unsigned int CP_SEND_QUAL : 1; + unsigned int ARB_RTR_q : 1; + unsigned int ARB_HOLD : 1; + unsigned int KILL_EFF1 : 1; + unsigned int EFF1_WIN : 1; + unsigned int ARB_WINNER_q : 3; + unsigned int ARB_WINNER : 3; + unsigned int EFF1_WINNER : 3; + unsigned int EFF2_LRU_WINNER_out : 3; + unsigned int EFF2_FP_WINNER : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG24 { + struct { +#if defined(qLittleEndian) + unsigned int EFF1_WINNER : 3; + unsigned int ARB_WINNER : 3; + unsigned int CP_SEND_QUAL : 1; + unsigned int VGT_SEND_QUAL : 1; + unsigned int TC_SEND_QUAL : 1; + unsigned int TC_SEND_EFF1_QUAL : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int ARB_QUAL : 1; + unsigned int CP_EFF1_REQ : 1; + unsigned int VGT_EFF1_REQ : 1; + unsigned int TC_EFF1_REQ : 1; + unsigned int RB_EFF1_REQ : 1; + unsigned int EFF1_WIN : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int TC_ARB_HOLD : 1; + unsigned int ARB_HOLD : 1; + unsigned int ARB_RTR_q : 1; + unsigned int SAME_PAGE_LIMIT_COUNT_q : 10; +#else /* !defined(qLittleEndian) */ + unsigned int SAME_PAGE_LIMIT_COUNT_q : 10; + unsigned int ARB_RTR_q : 1; + unsigned int ARB_HOLD : 1; + unsigned int TC_ARB_HOLD : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int KILL_EFF1 : 1; + unsigned int EFF1_WIN : 1; + unsigned int RB_EFF1_REQ : 1; + unsigned int TC_EFF1_REQ : 1; + unsigned int VGT_EFF1_REQ : 1; + unsigned int CP_EFF1_REQ : 1; + unsigned int ARB_QUAL : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int TC_SEND_EFF1_QUAL : 1; + unsigned int TC_SEND_QUAL : 1; + unsigned int VGT_SEND_QUAL : 1; + unsigned int CP_SEND_QUAL : 1; + unsigned int ARB_WINNER : 3; + unsigned int EFF1_WINNER : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG25 { + struct { +#if defined(qLittleEndian) + unsigned int EFF2_LRU_WINNER_out : 3; + unsigned int ARB_WINNER : 3; + unsigned int LEAST_RECENT_INDEX_d : 3; + unsigned int LEAST_RECENT_d : 3; + unsigned int UPDATE_RECENT_STACK_d : 1; + unsigned int ARB_HOLD : 1; + unsigned int ARB_RTR_q : 1; + unsigned int EFF1_WIN : 1; + unsigned int CLNT_REQ : 4; + unsigned int RECENT_d_0 : 3; + unsigned int RECENT_d_1 : 3; + unsigned int RECENT_d_2 : 3; + unsigned int RECENT_d_3 : 3; +#else /* !defined(qLittleEndian) */ + unsigned int RECENT_d_3 : 3; + unsigned int RECENT_d_2 : 3; + unsigned int RECENT_d_1 : 3; + unsigned int RECENT_d_0 : 3; + unsigned int CLNT_REQ : 4; + unsigned int EFF1_WIN : 1; + unsigned int ARB_RTR_q : 1; + unsigned int ARB_HOLD : 1; + unsigned int UPDATE_RECENT_STACK_d : 1; + unsigned int LEAST_RECENT_d : 3; + unsigned int LEAST_RECENT_INDEX_d : 3; + unsigned int ARB_WINNER : 3; + unsigned int EFF2_LRU_WINNER_out : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG26 { + struct { +#if defined(qLittleEndian) + unsigned int TC_ARB_HOLD : 1; + unsigned int TC_NOROQ_SAME_ROW_BANK : 1; + unsigned int TC_ROQ_SAME_ROW_BANK : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int TCHOLD_IP_q : 1; + unsigned int TCHOLD_CNT_q : 3; + unsigned int MH_ARBITER_CONFIG_TC_REORDER_ENABLE : 1; + unsigned int TC_ROQ_RTR_DBG_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_MH_written : 1; + unsigned int TCD_FULLNESS_CNT_q : 7; + unsigned int WBURST_ACTIVE : 1; + unsigned int WLAST_q : 1; + unsigned int WBURST_IP_q : 1; + unsigned int WBURST_CNT_q : 3; + unsigned int CP_SEND_QUAL : 1; + unsigned int CP_MH_write : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int ARB_WINNER : 3; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int ARB_WINNER : 3; + unsigned int RB_SEND_QUAL : 1; + unsigned int CP_MH_write : 1; + unsigned int CP_SEND_QUAL : 1; + unsigned int WBURST_CNT_q : 3; + unsigned int WBURST_IP_q : 1; + unsigned int WLAST_q : 1; + unsigned int WBURST_ACTIVE : 1; + unsigned int TCD_FULLNESS_CNT_q : 7; + unsigned int TC_MH_written : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_ROQ_RTR_DBG_q : 1; + unsigned int MH_ARBITER_CONFIG_TC_REORDER_ENABLE : 1; + unsigned int TCHOLD_CNT_q : 3; + unsigned int TCHOLD_IP_q : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int TC_ROQ_SAME_ROW_BANK : 1; + unsigned int TC_NOROQ_SAME_ROW_BANK : 1; + unsigned int TC_ARB_HOLD : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG27 { + struct { +#if defined(qLittleEndian) + unsigned int RF_ARBITER_CONFIG_q : 26; + unsigned int MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3; + unsigned int RF_ARBITER_CONFIG_q : 26; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG28 { + struct { +#if defined(qLittleEndian) + unsigned int SAME_ROW_BANK_q : 8; + unsigned int ROQ_MARK_q : 8; + unsigned int ROQ_VALID_q : 8; + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TC_ROQ_SAME_ROW_BANK_SEL : 1; + unsigned int ANY_SAME_ROW_BANK : 1; + unsigned int TC_EFF1_QUAL : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TC_ROQ_FULL : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TC_ROQ_FULL : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TC_EFF1_QUAL : 1; + unsigned int ANY_SAME_ROW_BANK : 1; + unsigned int TC_ROQ_SAME_ROW_BANK_SEL : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; + unsigned int ROQ_VALID_q : 8; + unsigned int ROQ_MARK_q : 8; + unsigned int SAME_ROW_BANK_q : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG29 { + struct { +#if defined(qLittleEndian) + unsigned int SAME_ROW_BANK_q : 8; + unsigned int ROQ_MARK_d : 8; + unsigned int ROQ_VALID_d : 8; + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TC_ROQ_SAME_ROW_BANK_SEL : 1; + unsigned int ANY_SAME_ROW_BANK : 1; + unsigned int TC_EFF1_QUAL : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TC_ROQ_FULL : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TC_ROQ_FULL : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TC_EFF1_QUAL : 1; + unsigned int ANY_SAME_ROW_BANK : 1; + unsigned int TC_ROQ_SAME_ROW_BANK_SEL : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; + unsigned int ROQ_VALID_d : 8; + unsigned int ROQ_MARK_d : 8; + unsigned int SAME_ROW_BANK_q : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG30 { + struct { +#if defined(qLittleEndian) + unsigned int SAME_ROW_BANK_WIN : 8; + unsigned int SAME_ROW_BANK_REQ : 8; + unsigned int NON_SAME_ROW_BANK_WIN : 8; + unsigned int NON_SAME_ROW_BANK_REQ : 8; +#else /* !defined(qLittleEndian) */ + unsigned int NON_SAME_ROW_BANK_REQ : 8; + unsigned int NON_SAME_ROW_BANK_WIN : 8; + unsigned int SAME_ROW_BANK_REQ : 8; + unsigned int SAME_ROW_BANK_WIN : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG31 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_0 : 1; + unsigned int ROQ_VALID_q_0 : 1; + unsigned int SAME_ROW_BANK_q_0 : 1; + unsigned int ROQ_ADDR_0 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_0 : 27; + unsigned int SAME_ROW_BANK_q_0 : 1; + unsigned int ROQ_VALID_q_0 : 1; + unsigned int ROQ_MARK_q_0 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG32 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_1 : 1; + unsigned int ROQ_VALID_q_1 : 1; + unsigned int SAME_ROW_BANK_q_1 : 1; + unsigned int ROQ_ADDR_1 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_1 : 27; + unsigned int SAME_ROW_BANK_q_1 : 1; + unsigned int ROQ_VALID_q_1 : 1; + unsigned int ROQ_MARK_q_1 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG33 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_2 : 1; + unsigned int ROQ_VALID_q_2 : 1; + unsigned int SAME_ROW_BANK_q_2 : 1; + unsigned int ROQ_ADDR_2 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_2 : 27; + unsigned int SAME_ROW_BANK_q_2 : 1; + unsigned int ROQ_VALID_q_2 : 1; + unsigned int ROQ_MARK_q_2 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG34 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_3 : 1; + unsigned int ROQ_VALID_q_3 : 1; + unsigned int SAME_ROW_BANK_q_3 : 1; + unsigned int ROQ_ADDR_3 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_3 : 27; + unsigned int SAME_ROW_BANK_q_3 : 1; + unsigned int ROQ_VALID_q_3 : 1; + unsigned int ROQ_MARK_q_3 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG35 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_4 : 1; + unsigned int ROQ_VALID_q_4 : 1; + unsigned int SAME_ROW_BANK_q_4 : 1; + unsigned int ROQ_ADDR_4 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_4 : 27; + unsigned int SAME_ROW_BANK_q_4 : 1; + unsigned int ROQ_VALID_q_4 : 1; + unsigned int ROQ_MARK_q_4 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG36 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_5 : 1; + unsigned int ROQ_VALID_q_5 : 1; + unsigned int SAME_ROW_BANK_q_5 : 1; + unsigned int ROQ_ADDR_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_5 : 27; + unsigned int SAME_ROW_BANK_q_5 : 1; + unsigned int ROQ_VALID_q_5 : 1; + unsigned int ROQ_MARK_q_5 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG37 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_6 : 1; + unsigned int ROQ_VALID_q_6 : 1; + unsigned int SAME_ROW_BANK_q_6 : 1; + unsigned int ROQ_ADDR_6 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_6 : 27; + unsigned int SAME_ROW_BANK_q_6 : 1; + unsigned int ROQ_VALID_q_6 : 1; + unsigned int ROQ_MARK_q_6 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG38 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_7 : 1; + unsigned int ROQ_VALID_q_7 : 1; + unsigned int SAME_ROW_BANK_q_7 : 1; + unsigned int ROQ_ADDR_7 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_7 : 27; + unsigned int SAME_ROW_BANK_q_7 : 1; + unsigned int ROQ_VALID_q_7 : 1; + unsigned int ROQ_MARK_q_7 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG39 { + struct { +#if defined(qLittleEndian) + unsigned int ARB_WE : 1; + unsigned int MMU_RTR : 1; + unsigned int ARB_ID_q : 3; + unsigned int ARB_WRITE_q : 1; + unsigned int ARB_BLEN_q : 1; + unsigned int ARQ_CTRL_EMPTY : 1; + unsigned int ARQ_FIFO_CNT_q : 3; + unsigned int MMU_WE : 1; + unsigned int ARQ_RTR : 1; + unsigned int MMU_ID : 3; + unsigned int MMU_WRITE : 1; + unsigned int MMU_BLEN : 1; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int MMU_BLEN : 1; + unsigned int MMU_WRITE : 1; + unsigned int MMU_ID : 3; + unsigned int ARQ_RTR : 1; + unsigned int MMU_WE : 1; + unsigned int ARQ_FIFO_CNT_q : 3; + unsigned int ARQ_CTRL_EMPTY : 1; + unsigned int ARB_BLEN_q : 1; + unsigned int ARB_WRITE_q : 1; + unsigned int ARB_ID_q : 3; + unsigned int MMU_RTR : 1; + unsigned int ARB_WE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG40 { + struct { +#if defined(qLittleEndian) + unsigned int ARB_WE : 1; + unsigned int ARB_ID_q : 3; + unsigned int ARB_VAD_q : 28; +#else /* !defined(qLittleEndian) */ + unsigned int ARB_VAD_q : 28; + unsigned int ARB_ID_q : 3; + unsigned int ARB_WE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG41 { + struct { +#if defined(qLittleEndian) + unsigned int MMU_WE : 1; + unsigned int MMU_ID : 3; + unsigned int MMU_PAD : 28; +#else /* !defined(qLittleEndian) */ + unsigned int MMU_PAD : 28; + unsigned int MMU_ID : 3; + unsigned int MMU_WE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG42 { + struct { +#if defined(qLittleEndian) + unsigned int WDB_WE : 1; + unsigned int WDB_RTR_SKID : 1; + unsigned int ARB_WSTRB_q : 8; + unsigned int ARB_WLAST : 1; + unsigned int WDB_CTRL_EMPTY : 1; + unsigned int WDB_FIFO_CNT_q : 5; + unsigned int WDC_WDB_RE_q : 1; + unsigned int WDB_WDC_WID : 3; + unsigned int WDB_WDC_WLAST : 1; + unsigned int WDB_WDC_WSTRB : 8; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int WDB_WDC_WSTRB : 8; + unsigned int WDB_WDC_WLAST : 1; + unsigned int WDB_WDC_WID : 3; + unsigned int WDC_WDB_RE_q : 1; + unsigned int WDB_FIFO_CNT_q : 5; + unsigned int WDB_CTRL_EMPTY : 1; + unsigned int ARB_WLAST : 1; + unsigned int ARB_WSTRB_q : 8; + unsigned int WDB_RTR_SKID : 1; + unsigned int WDB_WE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG43 { + struct { +#if defined(qLittleEndian) + unsigned int ARB_WDATA_q_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ARB_WDATA_q_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG44 { + struct { +#if defined(qLittleEndian) + unsigned int ARB_WDATA_q_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ARB_WDATA_q_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG45 { + struct { +#if defined(qLittleEndian) + unsigned int WDB_WDC_WDATA_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int WDB_WDC_WDATA_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG46 { + struct { +#if defined(qLittleEndian) + unsigned int WDB_WDC_WDATA_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int WDB_WDC_WDATA_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG47 { + struct { +#if defined(qLittleEndian) + unsigned int CTRL_ARC_EMPTY : 1; + unsigned int CTRL_RARC_EMPTY : 1; + unsigned int ARQ_CTRL_EMPTY : 1; + unsigned int ARQ_CTRL_WRITE : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int INFLT_LIMIT_q : 1; + unsigned int INFLT_LIMIT_CNT_q : 6; + unsigned int ARC_CTRL_RE_q : 1; + unsigned int RARC_CTRL_RE_q : 1; + unsigned int RVALID_q : 1; + unsigned int RREADY_q : 1; + unsigned int RLAST_q : 1; + unsigned int BVALID_q : 1; + unsigned int BREADY_q : 1; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int BREADY_q : 1; + unsigned int BVALID_q : 1; + unsigned int RLAST_q : 1; + unsigned int RREADY_q : 1; + unsigned int RVALID_q : 1; + unsigned int RARC_CTRL_RE_q : 1; + unsigned int ARC_CTRL_RE_q : 1; + unsigned int INFLT_LIMIT_CNT_q : 6; + unsigned int INFLT_LIMIT_q : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int ARQ_CTRL_WRITE : 1; + unsigned int ARQ_CTRL_EMPTY : 1; + unsigned int CTRL_RARC_EMPTY : 1; + unsigned int CTRL_ARC_EMPTY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG48 { + struct { +#if defined(qLittleEndian) + unsigned int MH_CP_grb_send : 1; + unsigned int MH_VGT_grb_send : 1; + unsigned int MH_TC_mcsend : 1; + unsigned int MH_TLBMISS_SEND : 1; + unsigned int TLBMISS_VALID : 1; + unsigned int RDC_VALID : 1; + unsigned int RDC_RID : 3; + unsigned int RDC_RLAST : 1; + unsigned int RDC_RRESP : 2; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int MMU_ID_REQUEST_q : 1; + unsigned int OUTSTANDING_MMUID_CNT_q : 6; + unsigned int MMU_ID_RESPONSE : 1; + unsigned int TLBMISS_RETURN_CNT_q : 6; + unsigned int CNT_HOLD_q1 : 1; + unsigned int MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3; +#else /* !defined(qLittleEndian) */ + unsigned int MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3; + unsigned int CNT_HOLD_q1 : 1; + unsigned int TLBMISS_RETURN_CNT_q : 6; + unsigned int MMU_ID_RESPONSE : 1; + unsigned int OUTSTANDING_MMUID_CNT_q : 6; + unsigned int MMU_ID_REQUEST_q : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int RDC_RRESP : 2; + unsigned int RDC_RLAST : 1; + unsigned int RDC_RID : 3; + unsigned int RDC_VALID : 1; + unsigned int TLBMISS_VALID : 1; + unsigned int MH_TLBMISS_SEND : 1; + unsigned int MH_TC_mcsend : 1; + unsigned int MH_VGT_grb_send : 1; + unsigned int MH_CP_grb_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG49 { + struct { +#if defined(qLittleEndian) + unsigned int RF_MMU_PAGE_FAULT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RF_MMU_PAGE_FAULT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG50 { + struct { +#if defined(qLittleEndian) + unsigned int RF_MMU_CONFIG_q : 24; + unsigned int ARB_ID_q : 3; + unsigned int ARB_WRITE_q : 1; + unsigned int client_behavior_q : 2; + unsigned int ARB_WE : 1; + unsigned int MMU_RTR : 1; +#else /* !defined(qLittleEndian) */ + unsigned int MMU_RTR : 1; + unsigned int ARB_WE : 1; + unsigned int client_behavior_q : 2; + unsigned int ARB_WRITE_q : 1; + unsigned int ARB_ID_q : 3; + unsigned int RF_MMU_CONFIG_q : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG51 { + struct { +#if defined(qLittleEndian) + unsigned int stage1_valid : 1; + unsigned int IGNORE_TAG_MISS_q : 1; + unsigned int pa_in_mpu_range : 1; + unsigned int tag_match_q : 1; + unsigned int tag_miss_q : 1; + unsigned int va_in_range_q : 1; + unsigned int MMU_MISS : 1; + unsigned int MMU_READ_MISS : 1; + unsigned int MMU_WRITE_MISS : 1; + unsigned int MMU_HIT : 1; + unsigned int MMU_READ_HIT : 1; + unsigned int MMU_WRITE_HIT : 1; + unsigned int MMU_SPLIT_MODE_TC_MISS : 1; + unsigned int MMU_SPLIT_MODE_TC_HIT : 1; + unsigned int MMU_SPLIT_MODE_nonTC_MISS : 1; + unsigned int MMU_SPLIT_MODE_nonTC_HIT : 1; + unsigned int REQ_VA_OFFSET_q : 16; +#else /* !defined(qLittleEndian) */ + unsigned int REQ_VA_OFFSET_q : 16; + unsigned int MMU_SPLIT_MODE_nonTC_HIT : 1; + unsigned int MMU_SPLIT_MODE_nonTC_MISS : 1; + unsigned int MMU_SPLIT_MODE_TC_HIT : 1; + unsigned int MMU_SPLIT_MODE_TC_MISS : 1; + unsigned int MMU_WRITE_HIT : 1; + unsigned int MMU_READ_HIT : 1; + unsigned int MMU_HIT : 1; + unsigned int MMU_WRITE_MISS : 1; + unsigned int MMU_READ_MISS : 1; + unsigned int MMU_MISS : 1; + unsigned int va_in_range_q : 1; + unsigned int tag_miss_q : 1; + unsigned int tag_match_q : 1; + unsigned int pa_in_mpu_range : 1; + unsigned int IGNORE_TAG_MISS_q : 1; + unsigned int stage1_valid : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG52 { + struct { +#if defined(qLittleEndian) + unsigned int ARQ_RTR : 1; + unsigned int MMU_WE : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int MH_TLBMISS_SEND : 1; + unsigned int MMU_STALL_AWAITING_TLB_MISS_FETCH : 1; + unsigned int pa_in_mpu_range : 1; + unsigned int stage1_valid : 1; + unsigned int stage2_valid : 1; + unsigned int client_behavior_q : 2; + unsigned int IGNORE_TAG_MISS_q : 1; + unsigned int tag_match_q : 1; + unsigned int tag_miss_q : 1; + unsigned int va_in_range_q : 1; + unsigned int PTE_FETCH_COMPLETE_q : 1; + unsigned int TAG_valid_q : 16; +#else /* !defined(qLittleEndian) */ + unsigned int TAG_valid_q : 16; + unsigned int PTE_FETCH_COMPLETE_q : 1; + unsigned int va_in_range_q : 1; + unsigned int tag_miss_q : 1; + unsigned int tag_match_q : 1; + unsigned int IGNORE_TAG_MISS_q : 1; + unsigned int client_behavior_q : 2; + unsigned int stage2_valid : 1; + unsigned int stage1_valid : 1; + unsigned int pa_in_mpu_range : 1; + unsigned int MMU_STALL_AWAITING_TLB_MISS_FETCH : 1; + unsigned int MH_TLBMISS_SEND : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int MMU_WE : 1; + unsigned int ARQ_RTR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG53 { + struct { +#if defined(qLittleEndian) + unsigned int TAG0_VA : 13; + unsigned int TAG_valid_q_0 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG1_VA : 13; + unsigned int TAG_valid_q_1 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_1 : 1; + unsigned int TAG1_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_0 : 1; + unsigned int TAG0_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG54 { + struct { +#if defined(qLittleEndian) + unsigned int TAG2_VA : 13; + unsigned int TAG_valid_q_2 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG3_VA : 13; + unsigned int TAG_valid_q_3 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_3 : 1; + unsigned int TAG3_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_2 : 1; + unsigned int TAG2_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG55 { + struct { +#if defined(qLittleEndian) + unsigned int TAG4_VA : 13; + unsigned int TAG_valid_q_4 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG5_VA : 13; + unsigned int TAG_valid_q_5 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_5 : 1; + unsigned int TAG5_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_4 : 1; + unsigned int TAG4_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG56 { + struct { +#if defined(qLittleEndian) + unsigned int TAG6_VA : 13; + unsigned int TAG_valid_q_6 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG7_VA : 13; + unsigned int TAG_valid_q_7 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_7 : 1; + unsigned int TAG7_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_6 : 1; + unsigned int TAG6_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG57 { + struct { +#if defined(qLittleEndian) + unsigned int TAG8_VA : 13; + unsigned int TAG_valid_q_8 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG9_VA : 13; + unsigned int TAG_valid_q_9 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_9 : 1; + unsigned int TAG9_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_8 : 1; + unsigned int TAG8_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG58 { + struct { +#if defined(qLittleEndian) + unsigned int TAG10_VA : 13; + unsigned int TAG_valid_q_10 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG11_VA : 13; + unsigned int TAG_valid_q_11 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_11 : 1; + unsigned int TAG11_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_10 : 1; + unsigned int TAG10_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG59 { + struct { +#if defined(qLittleEndian) + unsigned int TAG12_VA : 13; + unsigned int TAG_valid_q_12 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG13_VA : 13; + unsigned int TAG_valid_q_13 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_13 : 1; + unsigned int TAG13_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_12 : 1; + unsigned int TAG12_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG60 { + struct { +#if defined(qLittleEndian) + unsigned int TAG14_VA : 13; + unsigned int TAG_valid_q_14 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG15_VA : 13; + unsigned int TAG_valid_q_15 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_15 : 1; + unsigned int TAG15_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_14 : 1; + unsigned int TAG14_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG61 { + struct { +#if defined(qLittleEndian) + unsigned int MH_DBG_DEFAULT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int MH_DBG_DEFAULT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG62 { + struct { +#if defined(qLittleEndian) + unsigned int MH_DBG_DEFAULT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int MH_DBG_DEFAULT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG63 { + struct { +#if defined(qLittleEndian) + unsigned int MH_DBG_DEFAULT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int MH_DBG_DEFAULT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int MMU_ENABLE : 1; + unsigned int SPLIT_MODE_ENABLE : 1; + unsigned int RESERVED1 : 2; + unsigned int RB_W_CLNT_BEHAVIOR : 2; + unsigned int CP_W_CLNT_BEHAVIOR : 2; + unsigned int CP_R0_CLNT_BEHAVIOR : 2; + unsigned int CP_R1_CLNT_BEHAVIOR : 2; + unsigned int CP_R2_CLNT_BEHAVIOR : 2; + unsigned int CP_R3_CLNT_BEHAVIOR : 2; + unsigned int CP_R4_CLNT_BEHAVIOR : 2; + unsigned int VGT_R0_CLNT_BEHAVIOR : 2; + unsigned int VGT_R1_CLNT_BEHAVIOR : 2; + unsigned int TC_R_CLNT_BEHAVIOR : 2; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int TC_R_CLNT_BEHAVIOR : 2; + unsigned int VGT_R1_CLNT_BEHAVIOR : 2; + unsigned int VGT_R0_CLNT_BEHAVIOR : 2; + unsigned int CP_R4_CLNT_BEHAVIOR : 2; + unsigned int CP_R3_CLNT_BEHAVIOR : 2; + unsigned int CP_R2_CLNT_BEHAVIOR : 2; + unsigned int CP_R1_CLNT_BEHAVIOR : 2; + unsigned int CP_R0_CLNT_BEHAVIOR : 2; + unsigned int CP_W_CLNT_BEHAVIOR : 2; + unsigned int RB_W_CLNT_BEHAVIOR : 2; + unsigned int RESERVED1 : 2; + unsigned int SPLIT_MODE_ENABLE : 1; + unsigned int MMU_ENABLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_VA_RANGE { + struct { +#if defined(qLittleEndian) + unsigned int NUM_64KB_REGIONS : 12; + unsigned int VA_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int VA_BASE : 20; + unsigned int NUM_64KB_REGIONS : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_PT_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int PT_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int PT_BASE : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_PAGE_FAULT { + struct { +#if defined(qLittleEndian) + unsigned int PAGE_FAULT : 1; + unsigned int OP_TYPE : 1; + unsigned int CLNT_BEHAVIOR : 2; + unsigned int AXI_ID : 3; + unsigned int RESERVED1 : 1; + unsigned int MPU_ADDRESS_OUT_OF_RANGE : 1; + unsigned int ADDRESS_OUT_OF_RANGE : 1; + unsigned int READ_PROTECTION_ERROR : 1; + unsigned int WRITE_PROTECTION_ERROR : 1; + unsigned int REQ_VA : 20; +#else /* !defined(qLittleEndian) */ + unsigned int REQ_VA : 20; + unsigned int WRITE_PROTECTION_ERROR : 1; + unsigned int READ_PROTECTION_ERROR : 1; + unsigned int ADDRESS_OUT_OF_RANGE : 1; + unsigned int MPU_ADDRESS_OUT_OF_RANGE : 1; + unsigned int RESERVED1 : 1; + unsigned int AXI_ID : 3; + unsigned int CLNT_BEHAVIOR : 2; + unsigned int OP_TYPE : 1; + unsigned int PAGE_FAULT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_TRAN_ERROR { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int TRAN_ERROR : 27; +#else /* !defined(qLittleEndian) */ + unsigned int TRAN_ERROR : 27; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_INVALIDATE { + struct { +#if defined(qLittleEndian) + unsigned int INVALIDATE_ALL : 1; + unsigned int INVALIDATE_TC : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int INVALIDATE_TC : 1; + unsigned int INVALIDATE_ALL : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_MPU_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int MPU_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int MPU_BASE : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_MPU_END { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int MPU_END : 20; +#else /* !defined(qLittleEndian) */ + unsigned int MPU_END : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union WAIT_UNTIL { + struct { +#if defined(qLittleEndian) + unsigned int : 1; + unsigned int WAIT_RE_VSYNC : 1; + unsigned int WAIT_FE_VSYNC : 1; + unsigned int WAIT_VSYNC : 1; + unsigned int WAIT_DSPLY_ID0 : 1; + unsigned int WAIT_DSPLY_ID1 : 1; + unsigned int WAIT_DSPLY_ID2 : 1; + unsigned int : 3; + unsigned int WAIT_CMDFIFO : 1; + unsigned int : 3; + unsigned int WAIT_2D_IDLE : 1; + unsigned int WAIT_3D_IDLE : 1; + unsigned int WAIT_2D_IDLECLEAN : 1; + unsigned int WAIT_3D_IDLECLEAN : 1; + unsigned int : 2; + unsigned int CMDFIFO_ENTRIES : 4; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int CMDFIFO_ENTRIES : 4; + unsigned int : 2; + unsigned int WAIT_3D_IDLECLEAN : 1; + unsigned int WAIT_2D_IDLECLEAN : 1; + unsigned int WAIT_3D_IDLE : 1; + unsigned int WAIT_2D_IDLE : 1; + unsigned int : 3; + unsigned int WAIT_CMDFIFO : 1; + unsigned int : 3; + unsigned int WAIT_DSPLY_ID2 : 1; + unsigned int WAIT_DSPLY_ID1 : 1; + unsigned int WAIT_DSPLY_ID0 : 1; + unsigned int WAIT_VSYNC : 1; + unsigned int WAIT_FE_VSYNC : 1; + unsigned int WAIT_RE_VSYNC : 1; + unsigned int : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_ISYNC_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int : 4; + unsigned int ISYNC_WAIT_IDLEGUI : 1; + unsigned int ISYNC_CPSCRATCH_IDLEGUI : 1; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int ISYNC_CPSCRATCH_IDLEGUI : 1; + unsigned int ISYNC_WAIT_IDLEGUI : 1; + unsigned int : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int CMDFIFO_AVAIL : 5; + unsigned int TC_BUSY : 1; + unsigned int : 2; + unsigned int HIRQ_PENDING : 1; + unsigned int CPRQ_PENDING : 1; + unsigned int CFRQ_PENDING : 1; + unsigned int PFRQ_PENDING : 1; + unsigned int VGT_BUSY_NO_DMA : 1; + unsigned int : 1; + unsigned int RBBM_WU_BUSY : 1; + unsigned int : 1; + unsigned int CP_NRT_BUSY : 1; + unsigned int : 1; + unsigned int MH_BUSY : 1; + unsigned int MH_COHERENCY_BUSY : 1; + unsigned int : 1; + unsigned int SX_BUSY : 1; + unsigned int TPC_BUSY : 1; + unsigned int : 1; + unsigned int SC_CNTX_BUSY : 1; + unsigned int PA_BUSY : 1; + unsigned int VGT_BUSY : 1; + unsigned int SQ_CNTX17_BUSY : 1; + unsigned int SQ_CNTX0_BUSY : 1; + unsigned int : 1; + unsigned int RB_CNTX_BUSY : 1; + unsigned int GUI_ACTIVE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int GUI_ACTIVE : 1; + unsigned int RB_CNTX_BUSY : 1; + unsigned int : 1; + unsigned int SQ_CNTX0_BUSY : 1; + unsigned int SQ_CNTX17_BUSY : 1; + unsigned int VGT_BUSY : 1; + unsigned int PA_BUSY : 1; + unsigned int SC_CNTX_BUSY : 1; + unsigned int : 1; + unsigned int TPC_BUSY : 1; + unsigned int SX_BUSY : 1; + unsigned int : 1; + unsigned int MH_COHERENCY_BUSY : 1; + unsigned int MH_BUSY : 1; + unsigned int : 1; + unsigned int CP_NRT_BUSY : 1; + unsigned int : 1; + unsigned int RBBM_WU_BUSY : 1; + unsigned int : 1; + unsigned int VGT_BUSY_NO_DMA : 1; + unsigned int PFRQ_PENDING : 1; + unsigned int CFRQ_PENDING : 1; + unsigned int CPRQ_PENDING : 1; + unsigned int HIRQ_PENDING : 1; + unsigned int : 2; + unsigned int TC_BUSY : 1; + unsigned int CMDFIFO_AVAIL : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_DSPLY { + struct { +#if defined(qLittleEndian) + unsigned int DISPLAY_ID0_ACTIVE : 1; + unsigned int DISPLAY_ID1_ACTIVE : 1; + unsigned int DISPLAY_ID2_ACTIVE : 1; + unsigned int VSYNC_ACTIVE : 1; + unsigned int USE_DISPLAY_ID0 : 1; + unsigned int USE_DISPLAY_ID1 : 1; + unsigned int USE_DISPLAY_ID2 : 1; + unsigned int SW_CNTL : 1; + unsigned int NUM_BUFS : 2; + unsigned int : 22; +#else /* !defined(qLittleEndian) */ + unsigned int : 22; + unsigned int NUM_BUFS : 2; + unsigned int SW_CNTL : 1; + unsigned int USE_DISPLAY_ID2 : 1; + unsigned int USE_DISPLAY_ID1 : 1; + unsigned int USE_DISPLAY_ID0 : 1; + unsigned int VSYNC_ACTIVE : 1; + unsigned int DISPLAY_ID2_ACTIVE : 1; + unsigned int DISPLAY_ID1_ACTIVE : 1; + unsigned int DISPLAY_ID0_ACTIVE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_RENDER_LATEST { + struct { +#if defined(qLittleEndian) + unsigned int BUFFER_ID : 2; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int BUFFER_ID : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_RTL_RELEASE { + struct { +#if defined(qLittleEndian) + unsigned int CHANGELIST : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CHANGELIST : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PATCH_RELEASE { + struct { +#if defined(qLittleEndian) + unsigned int PATCH_REVISION : 16; + unsigned int PATCH_SELECTION : 8; + unsigned int CUSTOMER_ID : 8; +#else /* !defined(qLittleEndian) */ + unsigned int CUSTOMER_ID : 8; + unsigned int PATCH_SELECTION : 8; + unsigned int PATCH_REVISION : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_AUXILIARY_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERIPHID0 { + struct { +#if defined(qLittleEndian) + unsigned int PARTNUMBER0 : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PARTNUMBER0 : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERIPHID1 { + struct { +#if defined(qLittleEndian) + unsigned int PARTNUMBER1 : 4; + unsigned int DESIGNER0 : 4; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int DESIGNER0 : 4; + unsigned int PARTNUMBER1 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERIPHID2 { + struct { +#if defined(qLittleEndian) + unsigned int DESIGNER1 : 4; + unsigned int REVISION : 4; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int REVISION : 4; + unsigned int DESIGNER1 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERIPHID3 { + struct { +#if defined(qLittleEndian) + unsigned int RBBM_HOST_INTERFACE : 2; + unsigned int GARB_SLAVE_INTERFACE : 2; + unsigned int MH_INTERFACE : 2; + unsigned int : 1; + unsigned int CONTINUATION : 1; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int CONTINUATION : 1; + unsigned int : 1; + unsigned int MH_INTERFACE : 2; + unsigned int GARB_SLAVE_INTERFACE : 2; + unsigned int RBBM_HOST_INTERFACE : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int READ_TIMEOUT : 8; + unsigned int REGCLK_DEASSERT_TIME : 9; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int REGCLK_DEASSERT_TIME : 9; + unsigned int READ_TIMEOUT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_SKEW_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int SKEW_TOP_THRESHOLD : 5; + unsigned int SKEW_COUNT : 5; + unsigned int : 22; +#else /* !defined(qLittleEndian) */ + unsigned int : 22; + unsigned int SKEW_COUNT : 5; + unsigned int SKEW_TOP_THRESHOLD : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_SOFT_RESET { + struct { +#if defined(qLittleEndian) + unsigned int SOFT_RESET_CP : 1; + unsigned int : 1; + unsigned int SOFT_RESET_PA : 1; + unsigned int SOFT_RESET_MH : 1; + unsigned int SOFT_RESET_BC : 1; + unsigned int SOFT_RESET_SQ : 1; + unsigned int SOFT_RESET_SX : 1; + unsigned int : 5; + unsigned int SOFT_RESET_CIB : 1; + unsigned int : 2; + unsigned int SOFT_RESET_SC : 1; + unsigned int SOFT_RESET_VGT : 1; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int SOFT_RESET_VGT : 1; + unsigned int SOFT_RESET_SC : 1; + unsigned int : 2; + unsigned int SOFT_RESET_CIB : 1; + unsigned int : 5; + unsigned int SOFT_RESET_SX : 1; + unsigned int SOFT_RESET_SQ : 1; + unsigned int SOFT_RESET_BC : 1; + unsigned int SOFT_RESET_MH : 1; + unsigned int SOFT_RESET_PA : 1; + unsigned int : 1; + unsigned int SOFT_RESET_CP : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PM_OVERRIDE1 { + struct { +#if defined(qLittleEndian) + unsigned int RBBM_AHBCLK_PM_OVERRIDE : 1; + unsigned int SC_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SC_SCLK_PM_OVERRIDE : 1; + unsigned int SP_TOP_SCLK_PM_OVERRIDE : 1; + unsigned int SP_V0_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_REG_FIFOS_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_CONST_MEM_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_SQ_SCLK_PM_OVERRIDE : 1; + unsigned int SX_SCLK_PM_OVERRIDE : 1; + unsigned int SX_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCO_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCM_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCD_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TPC_TPC_SCLK_PM_OVERRIDE : 1; + unsigned int TPC_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCA_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCB_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCB_READ_SCLK_PM_OVERRIDE : 1; + unsigned int TP_TP_SCLK_PM_OVERRIDE : 1; + unsigned int TP_REG_SCLK_PM_OVERRIDE : 1; + unsigned int CP_G_SCLK_PM_OVERRIDE : 1; + unsigned int CP_REG_SCLK_PM_OVERRIDE : 1; + unsigned int CP_G_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SPI_SCLK_PM_OVERRIDE : 1; + unsigned int RB_REG_SCLK_PM_OVERRIDE : 1; + unsigned int RB_SCLK_PM_OVERRIDE : 1; + unsigned int MH_MH_SCLK_PM_OVERRIDE : 1; + unsigned int MH_REG_SCLK_PM_OVERRIDE : 1; + unsigned int MH_MMU_SCLK_PM_OVERRIDE : 1; + unsigned int MH_TCROQ_SCLK_PM_OVERRIDE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int MH_TCROQ_SCLK_PM_OVERRIDE : 1; + unsigned int MH_MMU_SCLK_PM_OVERRIDE : 1; + unsigned int MH_REG_SCLK_PM_OVERRIDE : 1; + unsigned int MH_MH_SCLK_PM_OVERRIDE : 1; + unsigned int RB_SCLK_PM_OVERRIDE : 1; + unsigned int RB_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SPI_SCLK_PM_OVERRIDE : 1; + unsigned int CP_G_REG_SCLK_PM_OVERRIDE : 1; + unsigned int CP_REG_SCLK_PM_OVERRIDE : 1; + unsigned int CP_G_SCLK_PM_OVERRIDE : 1; + unsigned int TP_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TP_TP_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCB_READ_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCB_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCA_SCLK_PM_OVERRIDE : 1; + unsigned int TPC_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TPC_TPC_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCD_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCM_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCO_SCLK_PM_OVERRIDE : 1; + unsigned int SX_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SX_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_SQ_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_CONST_MEM_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_REG_FIFOS_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SP_V0_SCLK_PM_OVERRIDE : 1; + unsigned int SP_TOP_SCLK_PM_OVERRIDE : 1; + unsigned int SC_SCLK_PM_OVERRIDE : 1; + unsigned int SC_REG_SCLK_PM_OVERRIDE : 1; + unsigned int RBBM_AHBCLK_PM_OVERRIDE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PM_OVERRIDE2 { + struct { +#if defined(qLittleEndian) + unsigned int PA_REG_SCLK_PM_OVERRIDE : 1; + unsigned int PA_PA_SCLK_PM_OVERRIDE : 1; + unsigned int PA_AG_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_REG_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_FIFOS_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_VGT_SCLK_PM_OVERRIDE : 1; + unsigned int DEBUG_PERF_SCLK_PM_OVERRIDE : 1; + unsigned int PERM_SCLK_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM0_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM1_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM2_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM3_PM_OVERRIDE : 1; + unsigned int : 20; +#else /* !defined(qLittleEndian) */ + unsigned int : 20; + unsigned int GC_GA_GMEM3_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM2_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM1_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM0_PM_OVERRIDE : 1; + unsigned int PERM_SCLK_PM_OVERRIDE : 1; + unsigned int DEBUG_PERF_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_VGT_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_FIFOS_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_REG_SCLK_PM_OVERRIDE : 1; + unsigned int PA_AG_SCLK_PM_OVERRIDE : 1; + unsigned int PA_PA_SCLK_PM_OVERRIDE : 1; + unsigned int PA_REG_SCLK_PM_OVERRIDE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union GC_SYS_IDLE { + struct { +#if defined(qLittleEndian) + unsigned int GC_SYS_IDLE_DELAY : 16; + unsigned int : 15; + unsigned int GC_SYS_IDLE_OVERRIDE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int GC_SYS_IDLE_OVERRIDE : 1; + unsigned int : 15; + unsigned int GC_SYS_IDLE_DELAY : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union NQWAIT_UNTIL { + struct { +#if defined(qLittleEndian) + unsigned int WAIT_GUI_IDLE : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int WAIT_GUI_IDLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 1; + unsigned int IGNORE_RTR : 1; + unsigned int IGNORE_CP_SCHED_WU : 1; + unsigned int IGNORE_CP_SCHED_ISYNC : 1; + unsigned int IGNORE_CP_SCHED_NQ_HI : 1; + unsigned int : 3; + unsigned int HYSTERESIS_NRT_GUI_ACTIVE : 4; + unsigned int : 4; + unsigned int IGNORE_RTR_FOR_HI : 1; + unsigned int IGNORE_CP_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_VGT_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_SQ_RBBM_NRTRTR_FOR_HI : 1; + unsigned int CP_RBBM_NRTRTR : 1; + unsigned int VGT_RBBM_NRTRTR : 1; + unsigned int SQ_RBBM_NRTRTR : 1; + unsigned int CLIENTS_FOR_NRT_RTR_FOR_HI : 1; + unsigned int CLIENTS_FOR_NRT_RTR : 1; + unsigned int : 6; + unsigned int IGNORE_SX_RBBM_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int IGNORE_SX_RBBM_BUSY : 1; + unsigned int : 6; + unsigned int CLIENTS_FOR_NRT_RTR : 1; + unsigned int CLIENTS_FOR_NRT_RTR_FOR_HI : 1; + unsigned int SQ_RBBM_NRTRTR : 1; + unsigned int VGT_RBBM_NRTRTR : 1; + unsigned int CP_RBBM_NRTRTR : 1; + unsigned int IGNORE_SQ_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_VGT_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_CP_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_RTR_FOR_HI : 1; + unsigned int : 4; + unsigned int HYSTERESIS_NRT_GUI_ACTIVE : 4; + unsigned int : 3; + unsigned int IGNORE_CP_SCHED_NQ_HI : 1; + unsigned int IGNORE_CP_SCHED_ISYNC : 1; + unsigned int IGNORE_CP_SCHED_WU : 1; + unsigned int IGNORE_RTR : 1; + unsigned int : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_READ_ERROR { + struct { +#if defined(qLittleEndian) + unsigned int : 2; + unsigned int READ_ADDRESS : 15; + unsigned int : 13; + unsigned int READ_REQUESTER : 1; + unsigned int READ_ERROR : 1; +#else /* !defined(qLittleEndian) */ + unsigned int READ_ERROR : 1; + unsigned int READ_REQUESTER : 1; + unsigned int : 13; + unsigned int READ_ADDRESS : 15; + unsigned int : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_WAIT_IDLE_CLOCKS { + struct { +#if defined(qLittleEndian) + unsigned int WAIT_IDLE_CLOCKS_NRT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int WAIT_IDLE_CLOCKS_NRT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_INT_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int RDERR_INT_MASK : 1; + unsigned int DISPLAY_UPDATE_INT_MASK : 1; + unsigned int : 17; + unsigned int GUI_IDLE_INT_MASK : 1; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int GUI_IDLE_INT_MASK : 1; + unsigned int : 17; + unsigned int DISPLAY_UPDATE_INT_MASK : 1; + unsigned int RDERR_INT_MASK : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_INT_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int RDERR_INT_STAT : 1; + unsigned int DISPLAY_UPDATE_INT_STAT : 1; + unsigned int : 17; + unsigned int GUI_IDLE_INT_STAT : 1; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int GUI_IDLE_INT_STAT : 1; + unsigned int : 17; + unsigned int DISPLAY_UPDATE_INT_STAT : 1; + unsigned int RDERR_INT_STAT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_INT_ACK { + struct { +#if defined(qLittleEndian) + unsigned int RDERR_INT_ACK : 1; + unsigned int DISPLAY_UPDATE_INT_ACK : 1; + unsigned int : 17; + unsigned int GUI_IDLE_INT_ACK : 1; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int GUI_IDLE_INT_ACK : 1; + unsigned int : 17; + unsigned int DISPLAY_UPDATE_INT_ACK : 1; + unsigned int RDERR_INT_ACK : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MASTER_INT_SIGNAL { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int MH_INT_STAT : 1; + unsigned int : 24; + unsigned int CP_INT_STAT : 1; + unsigned int RBBM_INT_STAT : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RBBM_INT_STAT : 1; + unsigned int CP_INT_STAT : 1; + unsigned int : 24; + unsigned int MH_INT_STAT : 1; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT1_SEL : 6; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int PERF_COUNT1_SEL : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERFCOUNTER1_LO { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT1_LO : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT1_LO : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT1_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT1_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int RB_BASE : 27; +#else /* !defined(qLittleEndian) */ + unsigned int RB_BASE : 27; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int RB_BUFSZ : 6; + unsigned int : 2; + unsigned int RB_BLKSZ : 6; + unsigned int : 2; + unsigned int BUF_SWAP : 2; + unsigned int : 2; + unsigned int RB_POLL_EN : 1; + unsigned int : 6; + unsigned int RB_NO_UPDATE : 1; + unsigned int : 3; + unsigned int RB_RPTR_WR_ENA : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RB_RPTR_WR_ENA : 1; + unsigned int : 3; + unsigned int RB_NO_UPDATE : 1; + unsigned int : 6; + unsigned int RB_POLL_EN : 1; + unsigned int : 2; + unsigned int BUF_SWAP : 2; + unsigned int : 2; + unsigned int RB_BLKSZ : 6; + unsigned int : 2; + unsigned int RB_BUFSZ : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_RPTR_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int RB_RPTR_SWAP : 2; + unsigned int RB_RPTR_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int RB_RPTR_ADDR : 30; + unsigned int RB_RPTR_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_RPTR { + struct { +#if defined(qLittleEndian) + unsigned int RB_RPTR : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int RB_RPTR : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_RPTR_WR { + struct { +#if defined(qLittleEndian) + unsigned int RB_RPTR_WR : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int RB_RPTR_WR : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_WPTR { + struct { +#if defined(qLittleEndian) + unsigned int RB_WPTR : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int RB_WPTR : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_WPTR_DELAY { + struct { +#if defined(qLittleEndian) + unsigned int PRE_WRITE_TIMER : 28; + unsigned int PRE_WRITE_LIMIT : 4; +#else /* !defined(qLittleEndian) */ + unsigned int PRE_WRITE_LIMIT : 4; + unsigned int PRE_WRITE_TIMER : 28; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_WPTR_BASE { + struct { +#if defined(qLittleEndian) + unsigned int RB_WPTR_SWAP : 2; + unsigned int RB_WPTR_BASE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int RB_WPTR_BASE : 30; + unsigned int RB_WPTR_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_IB1_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 2; + unsigned int IB1_BASE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int IB1_BASE : 30; + unsigned int : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_IB1_BUFSZ { + struct { +#if defined(qLittleEndian) + unsigned int IB1_BUFSZ : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int IB1_BUFSZ : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_IB2_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 2; + unsigned int IB2_BASE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int IB2_BASE : 30; + unsigned int : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_IB2_BUFSZ { + struct { +#if defined(qLittleEndian) + unsigned int IB2_BUFSZ : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int IB2_BUFSZ : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ST_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 2; + unsigned int ST_BASE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int ST_BASE : 30; + unsigned int : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ST_BUFSZ { + struct { +#if defined(qLittleEndian) + unsigned int ST_BUFSZ : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int ST_BUFSZ : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_QUEUE_THRESHOLDS { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_IB1_START : 4; + unsigned int : 4; + unsigned int CSQ_IB2_START : 4; + unsigned int : 4; + unsigned int CSQ_ST_START : 4; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int CSQ_ST_START : 4; + unsigned int : 4; + unsigned int CSQ_IB2_START : 4; + unsigned int : 4; + unsigned int CSQ_IB1_START : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_MEQ_THRESHOLDS { + struct { +#if defined(qLittleEndian) + unsigned int : 16; + unsigned int MEQ_END : 5; + unsigned int : 3; + unsigned int ROQ_END : 5; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int ROQ_END : 5; + unsigned int : 3; + unsigned int MEQ_END : 5; + unsigned int : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CSQ_AVAIL { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_CNT_RING : 7; + unsigned int : 1; + unsigned int CSQ_CNT_IB1 : 7; + unsigned int : 1; + unsigned int CSQ_CNT_IB2 : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int CSQ_CNT_IB2 : 7; + unsigned int : 1; + unsigned int CSQ_CNT_IB1 : 7; + unsigned int : 1; + unsigned int CSQ_CNT_RING : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STQ_AVAIL { + struct { +#if defined(qLittleEndian) + unsigned int STQ_CNT_ST : 7; + unsigned int : 25; +#else /* !defined(qLittleEndian) */ + unsigned int : 25; + unsigned int STQ_CNT_ST : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_MEQ_AVAIL { + struct { +#if defined(qLittleEndian) + unsigned int MEQ_CNT : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int MEQ_CNT : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CSQ_RB_STAT { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_RPTR_PRIMARY : 7; + unsigned int : 9; + unsigned int CSQ_WPTR_PRIMARY : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int CSQ_WPTR_PRIMARY : 7; + unsigned int : 9; + unsigned int CSQ_RPTR_PRIMARY : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CSQ_IB1_STAT { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_RPTR_INDIRECT1 : 7; + unsigned int : 9; + unsigned int CSQ_WPTR_INDIRECT1 : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int CSQ_WPTR_INDIRECT1 : 7; + unsigned int : 9; + unsigned int CSQ_RPTR_INDIRECT1 : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CSQ_IB2_STAT { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_RPTR_INDIRECT2 : 7; + unsigned int : 9; + unsigned int CSQ_WPTR_INDIRECT2 : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int CSQ_WPTR_INDIRECT2 : 7; + unsigned int : 9; + unsigned int CSQ_RPTR_INDIRECT2 : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NON_PREFETCH_CNTRS { + struct { +#if defined(qLittleEndian) + unsigned int IB1_COUNTER : 3; + unsigned int : 5; + unsigned int IB2_COUNTER : 3; + unsigned int : 21; +#else /* !defined(qLittleEndian) */ + unsigned int : 21; + unsigned int IB2_COUNTER : 3; + unsigned int : 5; + unsigned int IB1_COUNTER : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STQ_ST_STAT { + struct { +#if defined(qLittleEndian) + unsigned int STQ_RPTR_ST : 7; + unsigned int : 9; + unsigned int STQ_WPTR_ST : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int STQ_WPTR_ST : 7; + unsigned int : 9; + unsigned int STQ_RPTR_ST : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_MEQ_STAT { + struct { +#if defined(qLittleEndian) + unsigned int MEQ_RPTR : 10; + unsigned int : 6; + unsigned int MEQ_WPTR : 10; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int MEQ_WPTR : 10; + unsigned int : 6; + unsigned int MEQ_RPTR : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_MIU_TAG_STAT { + struct { +#if defined(qLittleEndian) + unsigned int TAG_0_STAT : 1; + unsigned int TAG_1_STAT : 1; + unsigned int TAG_2_STAT : 1; + unsigned int TAG_3_STAT : 1; + unsigned int TAG_4_STAT : 1; + unsigned int TAG_5_STAT : 1; + unsigned int TAG_6_STAT : 1; + unsigned int TAG_7_STAT : 1; + unsigned int TAG_8_STAT : 1; + unsigned int TAG_9_STAT : 1; + unsigned int TAG_10_STAT : 1; + unsigned int TAG_11_STAT : 1; + unsigned int TAG_12_STAT : 1; + unsigned int TAG_13_STAT : 1; + unsigned int TAG_14_STAT : 1; + unsigned int TAG_15_STAT : 1; + unsigned int TAG_16_STAT : 1; + unsigned int TAG_17_STAT : 1; + unsigned int : 13; + unsigned int INVALID_RETURN_TAG : 1; +#else /* !defined(qLittleEndian) */ + unsigned int INVALID_RETURN_TAG : 1; + unsigned int : 13; + unsigned int TAG_17_STAT : 1; + unsigned int TAG_16_STAT : 1; + unsigned int TAG_15_STAT : 1; + unsigned int TAG_14_STAT : 1; + unsigned int TAG_13_STAT : 1; + unsigned int TAG_12_STAT : 1; + unsigned int TAG_11_STAT : 1; + unsigned int TAG_10_STAT : 1; + unsigned int TAG_9_STAT : 1; + unsigned int TAG_8_STAT : 1; + unsigned int TAG_7_STAT : 1; + unsigned int TAG_6_STAT : 1; + unsigned int TAG_5_STAT : 1; + unsigned int TAG_4_STAT : 1; + unsigned int TAG_3_STAT : 1; + unsigned int TAG_2_STAT : 1; + unsigned int TAG_1_STAT : 1; + unsigned int TAG_0_STAT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CMD_INDEX { + struct { +#if defined(qLittleEndian) + unsigned int CMD_INDEX : 7; + unsigned int : 9; + unsigned int CMD_QUEUE_SEL : 2; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int CMD_QUEUE_SEL : 2; + unsigned int : 9; + unsigned int CMD_INDEX : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CMD_DATA { + struct { +#if defined(qLittleEndian) + unsigned int CMD_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CMD_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int ME_STATMUX : 16; + unsigned int : 9; + unsigned int VTX_DEALLOC_FIFO_EMPTY : 1; + unsigned int PIX_DEALLOC_FIFO_EMPTY : 1; + unsigned int : 1; + unsigned int ME_HALT : 1; + unsigned int ME_BUSY : 1; + unsigned int : 1; + unsigned int PROG_CNT_SIZE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PROG_CNT_SIZE : 1; + unsigned int : 1; + unsigned int ME_BUSY : 1; + unsigned int ME_HALT : 1; + unsigned int : 1; + unsigned int PIX_DEALLOC_FIFO_EMPTY : 1; + unsigned int VTX_DEALLOC_FIFO_EMPTY : 1; + unsigned int : 9; + unsigned int ME_STATMUX : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int ME_DEBUG_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ME_DEBUG_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_RAM_WADDR { + struct { +#if defined(qLittleEndian) + unsigned int ME_RAM_WADDR : 10; + unsigned int : 22; +#else /* !defined(qLittleEndian) */ + unsigned int : 22; + unsigned int ME_RAM_WADDR : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_RAM_RADDR { + struct { +#if defined(qLittleEndian) + unsigned int ME_RAM_RADDR : 10; + unsigned int : 22; +#else /* !defined(qLittleEndian) */ + unsigned int : 22; + unsigned int ME_RAM_RADDR : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_RAM_DATA { + struct { +#if defined(qLittleEndian) + unsigned int ME_RAM_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ME_RAM_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_RDADDR { + struct { +#if defined(qLittleEndian) + unsigned int ME_RDADDR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ME_RDADDR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int CP_DEBUG_UNUSED_22_to_0 : 23; + unsigned int PREDICATE_DISABLE : 1; + unsigned int PROG_END_PTR_ENABLE : 1; + unsigned int MIU_128BIT_WRITE_ENABLE : 1; + unsigned int PREFETCH_PASS_NOPS : 1; + unsigned int DYNAMIC_CLK_DISABLE : 1; + unsigned int PREFETCH_MATCH_DISABLE : 1; + unsigned int : 1; + unsigned int SIMPLE_ME_FLOW_CONTROL : 1; + unsigned int MIU_WRITE_PACK_DISABLE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int MIU_WRITE_PACK_DISABLE : 1; + unsigned int SIMPLE_ME_FLOW_CONTROL : 1; + unsigned int : 1; + unsigned int PREFETCH_MATCH_DISABLE : 1; + unsigned int DYNAMIC_CLK_DISABLE : 1; + unsigned int PREFETCH_PASS_NOPS : 1; + unsigned int MIU_128BIT_WRITE_ENABLE : 1; + unsigned int PROG_END_PTR_ENABLE : 1; + unsigned int PREDICATE_DISABLE : 1; + unsigned int CP_DEBUG_UNUSED_22_to_0 : 23; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG0 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG1 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG1 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG1 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG2 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG2 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG2 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG3 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG3 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG3 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG4 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG4 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG4 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG5 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG5 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG5 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG6 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG6 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG6 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG7 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG7 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG7 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_UMSK { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_UMSK : 8; + unsigned int : 8; + unsigned int SCRATCH_SWAP : 2; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int SCRATCH_SWAP : 2; + unsigned int : 8; + unsigned int SCRATCH_UMSK : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int SCRATCH_ADDR : 27; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_ADDR : 27; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_SRC { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_SWM : 1; + unsigned int VS_DONE_CNTR : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int VS_DONE_CNTR : 1; + unsigned int VS_DONE_SWM : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_SWAP : 2; + unsigned int VS_DONE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int VS_DONE_ADDR : 30; + unsigned int VS_DONE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_DATA { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_DONE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_ADDR_SWM { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_SWAP_SWM : 2; + unsigned int VS_DONE_ADDR_SWM : 30; +#else /* !defined(qLittleEndian) */ + unsigned int VS_DONE_ADDR_SWM : 30; + unsigned int VS_DONE_SWAP_SWM : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_DATA_SWM { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_DATA_SWM : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_DONE_DATA_SWM : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_SRC { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_SWM : 1; + unsigned int PS_DONE_CNTR : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int PS_DONE_CNTR : 1; + unsigned int PS_DONE_SWM : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_SWAP : 2; + unsigned int PS_DONE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int PS_DONE_ADDR : 30; + unsigned int PS_DONE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_DATA { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PS_DONE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_ADDR_SWM { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_SWAP_SWM : 2; + unsigned int PS_DONE_ADDR_SWM : 30; +#else /* !defined(qLittleEndian) */ + unsigned int PS_DONE_ADDR_SWM : 30; + unsigned int PS_DONE_SWAP_SWM : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_DATA_SWM { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_DATA_SWM : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PS_DONE_DATA_SWM : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_CF_EVENT_SRC { + struct { +#if defined(qLittleEndian) + unsigned int CF_DONE_SRC : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int CF_DONE_SRC : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_CF_EVENT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int CF_DONE_SWAP : 2; + unsigned int CF_DONE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int CF_DONE_ADDR : 30; + unsigned int CF_DONE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_CF_EVENT_DATA { + struct { +#if defined(qLittleEndian) + unsigned int CF_DONE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CF_DONE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_NRT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int NRT_WRITE_SWAP : 2; + unsigned int NRT_WRITE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int NRT_WRITE_ADDR : 30; + unsigned int NRT_WRITE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_NRT_DATA { + struct { +#if defined(qLittleEndian) + unsigned int NRT_WRITE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int NRT_WRITE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_FETCH_DONE_SRC { + struct { +#if defined(qLittleEndian) + unsigned int VS_FETCH_DONE_CNTR : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int VS_FETCH_DONE_CNTR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_FETCH_DONE_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int VS_FETCH_DONE_SWAP : 2; + unsigned int VS_FETCH_DONE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int VS_FETCH_DONE_ADDR : 30; + unsigned int VS_FETCH_DONE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_FETCH_DONE_DATA { + struct { +#if defined(qLittleEndian) + unsigned int VS_FETCH_DONE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_FETCH_DONE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_INT_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int : 19; + unsigned int SW_INT_MASK : 1; + unsigned int : 3; + unsigned int T0_PACKET_IN_IB_MASK : 1; + unsigned int OPCODE_ERROR_MASK : 1; + unsigned int PROTECTED_MODE_ERROR_MASK : 1; + unsigned int RESERVED_BIT_ERROR_MASK : 1; + unsigned int IB_ERROR_MASK : 1; + unsigned int : 1; + unsigned int IB2_INT_MASK : 1; + unsigned int IB1_INT_MASK : 1; + unsigned int RB_INT_MASK : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RB_INT_MASK : 1; + unsigned int IB1_INT_MASK : 1; + unsigned int IB2_INT_MASK : 1; + unsigned int : 1; + unsigned int IB_ERROR_MASK : 1; + unsigned int RESERVED_BIT_ERROR_MASK : 1; + unsigned int PROTECTED_MODE_ERROR_MASK : 1; + unsigned int OPCODE_ERROR_MASK : 1; + unsigned int T0_PACKET_IN_IB_MASK : 1; + unsigned int : 3; + unsigned int SW_INT_MASK : 1; + unsigned int : 19; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_INT_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int : 19; + unsigned int SW_INT_STAT : 1; + unsigned int : 3; + unsigned int T0_PACKET_IN_IB_STAT : 1; + unsigned int OPCODE_ERROR_STAT : 1; + unsigned int PROTECTED_MODE_ERROR_STAT : 1; + unsigned int RESERVED_BIT_ERROR_STAT : 1; + unsigned int IB_ERROR_STAT : 1; + unsigned int : 1; + unsigned int IB2_INT_STAT : 1; + unsigned int IB1_INT_STAT : 1; + unsigned int RB_INT_STAT : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RB_INT_STAT : 1; + unsigned int IB1_INT_STAT : 1; + unsigned int IB2_INT_STAT : 1; + unsigned int : 1; + unsigned int IB_ERROR_STAT : 1; + unsigned int RESERVED_BIT_ERROR_STAT : 1; + unsigned int PROTECTED_MODE_ERROR_STAT : 1; + unsigned int OPCODE_ERROR_STAT : 1; + unsigned int T0_PACKET_IN_IB_STAT : 1; + unsigned int : 3; + unsigned int SW_INT_STAT : 1; + unsigned int : 19; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_INT_ACK { + struct { +#if defined(qLittleEndian) + unsigned int : 19; + unsigned int SW_INT_ACK : 1; + unsigned int : 3; + unsigned int T0_PACKET_IN_IB_ACK : 1; + unsigned int OPCODE_ERROR_ACK : 1; + unsigned int PROTECTED_MODE_ERROR_ACK : 1; + unsigned int RESERVED_BIT_ERROR_ACK : 1; + unsigned int IB_ERROR_ACK : 1; + unsigned int : 1; + unsigned int IB2_INT_ACK : 1; + unsigned int IB1_INT_ACK : 1; + unsigned int RB_INT_ACK : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RB_INT_ACK : 1; + unsigned int IB1_INT_ACK : 1; + unsigned int IB2_INT_ACK : 1; + unsigned int : 1; + unsigned int IB_ERROR_ACK : 1; + unsigned int RESERVED_BIT_ERROR_ACK : 1; + unsigned int PROTECTED_MODE_ERROR_ACK : 1; + unsigned int OPCODE_ERROR_ACK : 1; + unsigned int T0_PACKET_IN_IB_ACK : 1; + unsigned int : 3; + unsigned int SW_INT_ACK : 1; + unsigned int : 19; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PFP_UCODE_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int UCODE_ADDR : 9; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int UCODE_ADDR : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PFP_UCODE_DATA { + struct { +#if defined(qLittleEndian) + unsigned int UCODE_DATA : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int UCODE_DATA : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PERFMON_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int PERFMON_STATE : 4; + unsigned int : 4; + unsigned int PERFMON_ENABLE_MODE : 2; + unsigned int : 22; +#else /* !defined(qLittleEndian) */ + unsigned int : 22; + unsigned int PERFMON_ENABLE_MODE : 2; + unsigned int : 4; + unsigned int PERFMON_STATE : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PERFCOUNTER_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNT_SEL : 6; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int PERFCOUNT_SEL : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PERFCOUNTER_LO { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNT_LO : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNT_LO : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PERFCOUNTER_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNT_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNT_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_BIN_MASK_LO { + struct { +#if defined(qLittleEndian) + unsigned int BIN_MASK_LO : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_MASK_LO : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_BIN_MASK_HI { + struct { +#if defined(qLittleEndian) + unsigned int BIN_MASK_HI : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_MASK_HI : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_BIN_SELECT_LO { + struct { +#if defined(qLittleEndian) + unsigned int BIN_SELECT_LO : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_SELECT_LO : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_BIN_SELECT_HI { + struct { +#if defined(qLittleEndian) + unsigned int BIN_SELECT_HI : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_SELECT_HI : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NV_FLAGS_0 { + struct { +#if defined(qLittleEndian) + unsigned int DISCARD_0 : 1; + unsigned int END_RCVD_0 : 1; + unsigned int DISCARD_1 : 1; + unsigned int END_RCVD_1 : 1; + unsigned int DISCARD_2 : 1; + unsigned int END_RCVD_2 : 1; + unsigned int DISCARD_3 : 1; + unsigned int END_RCVD_3 : 1; + unsigned int DISCARD_4 : 1; + unsigned int END_RCVD_4 : 1; + unsigned int DISCARD_5 : 1; + unsigned int END_RCVD_5 : 1; + unsigned int DISCARD_6 : 1; + unsigned int END_RCVD_6 : 1; + unsigned int DISCARD_7 : 1; + unsigned int END_RCVD_7 : 1; + unsigned int DISCARD_8 : 1; + unsigned int END_RCVD_8 : 1; + unsigned int DISCARD_9 : 1; + unsigned int END_RCVD_9 : 1; + unsigned int DISCARD_10 : 1; + unsigned int END_RCVD_10 : 1; + unsigned int DISCARD_11 : 1; + unsigned int END_RCVD_11 : 1; + unsigned int DISCARD_12 : 1; + unsigned int END_RCVD_12 : 1; + unsigned int DISCARD_13 : 1; + unsigned int END_RCVD_13 : 1; + unsigned int DISCARD_14 : 1; + unsigned int END_RCVD_14 : 1; + unsigned int DISCARD_15 : 1; + unsigned int END_RCVD_15 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int END_RCVD_15 : 1; + unsigned int DISCARD_15 : 1; + unsigned int END_RCVD_14 : 1; + unsigned int DISCARD_14 : 1; + unsigned int END_RCVD_13 : 1; + unsigned int DISCARD_13 : 1; + unsigned int END_RCVD_12 : 1; + unsigned int DISCARD_12 : 1; + unsigned int END_RCVD_11 : 1; + unsigned int DISCARD_11 : 1; + unsigned int END_RCVD_10 : 1; + unsigned int DISCARD_10 : 1; + unsigned int END_RCVD_9 : 1; + unsigned int DISCARD_9 : 1; + unsigned int END_RCVD_8 : 1; + unsigned int DISCARD_8 : 1; + unsigned int END_RCVD_7 : 1; + unsigned int DISCARD_7 : 1; + unsigned int END_RCVD_6 : 1; + unsigned int DISCARD_6 : 1; + unsigned int END_RCVD_5 : 1; + unsigned int DISCARD_5 : 1; + unsigned int END_RCVD_4 : 1; + unsigned int DISCARD_4 : 1; + unsigned int END_RCVD_3 : 1; + unsigned int DISCARD_3 : 1; + unsigned int END_RCVD_2 : 1; + unsigned int DISCARD_2 : 1; + unsigned int END_RCVD_1 : 1; + unsigned int DISCARD_1 : 1; + unsigned int END_RCVD_0 : 1; + unsigned int DISCARD_0 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NV_FLAGS_1 { + struct { +#if defined(qLittleEndian) + unsigned int DISCARD_16 : 1; + unsigned int END_RCVD_16 : 1; + unsigned int DISCARD_17 : 1; + unsigned int END_RCVD_17 : 1; + unsigned int DISCARD_18 : 1; + unsigned int END_RCVD_18 : 1; + unsigned int DISCARD_19 : 1; + unsigned int END_RCVD_19 : 1; + unsigned int DISCARD_20 : 1; + unsigned int END_RCVD_20 : 1; + unsigned int DISCARD_21 : 1; + unsigned int END_RCVD_21 : 1; + unsigned int DISCARD_22 : 1; + unsigned int END_RCVD_22 : 1; + unsigned int DISCARD_23 : 1; + unsigned int END_RCVD_23 : 1; + unsigned int DISCARD_24 : 1; + unsigned int END_RCVD_24 : 1; + unsigned int DISCARD_25 : 1; + unsigned int END_RCVD_25 : 1; + unsigned int DISCARD_26 : 1; + unsigned int END_RCVD_26 : 1; + unsigned int DISCARD_27 : 1; + unsigned int END_RCVD_27 : 1; + unsigned int DISCARD_28 : 1; + unsigned int END_RCVD_28 : 1; + unsigned int DISCARD_29 : 1; + unsigned int END_RCVD_29 : 1; + unsigned int DISCARD_30 : 1; + unsigned int END_RCVD_30 : 1; + unsigned int DISCARD_31 : 1; + unsigned int END_RCVD_31 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int END_RCVD_31 : 1; + unsigned int DISCARD_31 : 1; + unsigned int END_RCVD_30 : 1; + unsigned int DISCARD_30 : 1; + unsigned int END_RCVD_29 : 1; + unsigned int DISCARD_29 : 1; + unsigned int END_RCVD_28 : 1; + unsigned int DISCARD_28 : 1; + unsigned int END_RCVD_27 : 1; + unsigned int DISCARD_27 : 1; + unsigned int END_RCVD_26 : 1; + unsigned int DISCARD_26 : 1; + unsigned int END_RCVD_25 : 1; + unsigned int DISCARD_25 : 1; + unsigned int END_RCVD_24 : 1; + unsigned int DISCARD_24 : 1; + unsigned int END_RCVD_23 : 1; + unsigned int DISCARD_23 : 1; + unsigned int END_RCVD_22 : 1; + unsigned int DISCARD_22 : 1; + unsigned int END_RCVD_21 : 1; + unsigned int DISCARD_21 : 1; + unsigned int END_RCVD_20 : 1; + unsigned int DISCARD_20 : 1; + unsigned int END_RCVD_19 : 1; + unsigned int DISCARD_19 : 1; + unsigned int END_RCVD_18 : 1; + unsigned int DISCARD_18 : 1; + unsigned int END_RCVD_17 : 1; + unsigned int DISCARD_17 : 1; + unsigned int END_RCVD_16 : 1; + unsigned int DISCARD_16 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NV_FLAGS_2 { + struct { +#if defined(qLittleEndian) + unsigned int DISCARD_32 : 1; + unsigned int END_RCVD_32 : 1; + unsigned int DISCARD_33 : 1; + unsigned int END_RCVD_33 : 1; + unsigned int DISCARD_34 : 1; + unsigned int END_RCVD_34 : 1; + unsigned int DISCARD_35 : 1; + unsigned int END_RCVD_35 : 1; + unsigned int DISCARD_36 : 1; + unsigned int END_RCVD_36 : 1; + unsigned int DISCARD_37 : 1; + unsigned int END_RCVD_37 : 1; + unsigned int DISCARD_38 : 1; + unsigned int END_RCVD_38 : 1; + unsigned int DISCARD_39 : 1; + unsigned int END_RCVD_39 : 1; + unsigned int DISCARD_40 : 1; + unsigned int END_RCVD_40 : 1; + unsigned int DISCARD_41 : 1; + unsigned int END_RCVD_41 : 1; + unsigned int DISCARD_42 : 1; + unsigned int END_RCVD_42 : 1; + unsigned int DISCARD_43 : 1; + unsigned int END_RCVD_43 : 1; + unsigned int DISCARD_44 : 1; + unsigned int END_RCVD_44 : 1; + unsigned int DISCARD_45 : 1; + unsigned int END_RCVD_45 : 1; + unsigned int DISCARD_46 : 1; + unsigned int END_RCVD_46 : 1; + unsigned int DISCARD_47 : 1; + unsigned int END_RCVD_47 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int END_RCVD_47 : 1; + unsigned int DISCARD_47 : 1; + unsigned int END_RCVD_46 : 1; + unsigned int DISCARD_46 : 1; + unsigned int END_RCVD_45 : 1; + unsigned int DISCARD_45 : 1; + unsigned int END_RCVD_44 : 1; + unsigned int DISCARD_44 : 1; + unsigned int END_RCVD_43 : 1; + unsigned int DISCARD_43 : 1; + unsigned int END_RCVD_42 : 1; + unsigned int DISCARD_42 : 1; + unsigned int END_RCVD_41 : 1; + unsigned int DISCARD_41 : 1; + unsigned int END_RCVD_40 : 1; + unsigned int DISCARD_40 : 1; + unsigned int END_RCVD_39 : 1; + unsigned int DISCARD_39 : 1; + unsigned int END_RCVD_38 : 1; + unsigned int DISCARD_38 : 1; + unsigned int END_RCVD_37 : 1; + unsigned int DISCARD_37 : 1; + unsigned int END_RCVD_36 : 1; + unsigned int DISCARD_36 : 1; + unsigned int END_RCVD_35 : 1; + unsigned int DISCARD_35 : 1; + unsigned int END_RCVD_34 : 1; + unsigned int DISCARD_34 : 1; + unsigned int END_RCVD_33 : 1; + unsigned int DISCARD_33 : 1; + unsigned int END_RCVD_32 : 1; + unsigned int DISCARD_32 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NV_FLAGS_3 { + struct { +#if defined(qLittleEndian) + unsigned int DISCARD_48 : 1; + unsigned int END_RCVD_48 : 1; + unsigned int DISCARD_49 : 1; + unsigned int END_RCVD_49 : 1; + unsigned int DISCARD_50 : 1; + unsigned int END_RCVD_50 : 1; + unsigned int DISCARD_51 : 1; + unsigned int END_RCVD_51 : 1; + unsigned int DISCARD_52 : 1; + unsigned int END_RCVD_52 : 1; + unsigned int DISCARD_53 : 1; + unsigned int END_RCVD_53 : 1; + unsigned int DISCARD_54 : 1; + unsigned int END_RCVD_54 : 1; + unsigned int DISCARD_55 : 1; + unsigned int END_RCVD_55 : 1; + unsigned int DISCARD_56 : 1; + unsigned int END_RCVD_56 : 1; + unsigned int DISCARD_57 : 1; + unsigned int END_RCVD_57 : 1; + unsigned int DISCARD_58 : 1; + unsigned int END_RCVD_58 : 1; + unsigned int DISCARD_59 : 1; + unsigned int END_RCVD_59 : 1; + unsigned int DISCARD_60 : 1; + unsigned int END_RCVD_60 : 1; + unsigned int DISCARD_61 : 1; + unsigned int END_RCVD_61 : 1; + unsigned int DISCARD_62 : 1; + unsigned int END_RCVD_62 : 1; + unsigned int DISCARD_63 : 1; + unsigned int END_RCVD_63 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int END_RCVD_63 : 1; + unsigned int DISCARD_63 : 1; + unsigned int END_RCVD_62 : 1; + unsigned int DISCARD_62 : 1; + unsigned int END_RCVD_61 : 1; + unsigned int DISCARD_61 : 1; + unsigned int END_RCVD_60 : 1; + unsigned int DISCARD_60 : 1; + unsigned int END_RCVD_59 : 1; + unsigned int DISCARD_59 : 1; + unsigned int END_RCVD_58 : 1; + unsigned int DISCARD_58 : 1; + unsigned int END_RCVD_57 : 1; + unsigned int DISCARD_57 : 1; + unsigned int END_RCVD_56 : 1; + unsigned int DISCARD_56 : 1; + unsigned int END_RCVD_55 : 1; + unsigned int DISCARD_55 : 1; + unsigned int END_RCVD_54 : 1; + unsigned int DISCARD_54 : 1; + unsigned int END_RCVD_53 : 1; + unsigned int DISCARD_53 : 1; + unsigned int END_RCVD_52 : 1; + unsigned int DISCARD_52 : 1; + unsigned int END_RCVD_51 : 1; + unsigned int DISCARD_51 : 1; + unsigned int END_RCVD_50 : 1; + unsigned int DISCARD_50 : 1; + unsigned int END_RCVD_49 : 1; + unsigned int DISCARD_49 : 1; + unsigned int END_RCVD_48 : 1; + unsigned int DISCARD_48 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STATE_DEBUG_INDEX { + struct { +#if defined(qLittleEndian) + unsigned int STATE_DEBUG_INDEX : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int STATE_DEBUG_INDEX : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STATE_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int STATE_DEBUG_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int STATE_DEBUG_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PROG_COUNTER { + struct { +#if defined(qLittleEndian) + unsigned int COUNTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int COUNTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STAT { + struct { +#if defined(qLittleEndian) + unsigned int MIU_WR_BUSY : 1; + unsigned int MIU_RD_REQ_BUSY : 1; + unsigned int MIU_RD_RETURN_BUSY : 1; + unsigned int RBIU_BUSY : 1; + unsigned int RCIU_BUSY : 1; + unsigned int CSF_RING_BUSY : 1; + unsigned int CSF_INDIRECTS_BUSY : 1; + unsigned int CSF_INDIRECT2_BUSY : 1; + unsigned int : 1; + unsigned int CSF_ST_BUSY : 1; + unsigned int CSF_BUSY : 1; + unsigned int RING_QUEUE_BUSY : 1; + unsigned int INDIRECTS_QUEUE_BUSY : 1; + unsigned int INDIRECT2_QUEUE_BUSY : 1; + unsigned int : 2; + unsigned int ST_QUEUE_BUSY : 1; + unsigned int PFP_BUSY : 1; + unsigned int MEQ_RING_BUSY : 1; + unsigned int MEQ_INDIRECTS_BUSY : 1; + unsigned int MEQ_INDIRECT2_BUSY : 1; + unsigned int MIU_WC_STALL : 1; + unsigned int CP_NRT_BUSY : 1; + unsigned int _3D_BUSY : 1; + unsigned int : 2; + unsigned int ME_BUSY : 1; + unsigned int : 2; + unsigned int ME_WC_BUSY : 1; + unsigned int MIU_WC_TRACK_FIFO_EMPTY : 1; + unsigned int CP_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int CP_BUSY : 1; + unsigned int MIU_WC_TRACK_FIFO_EMPTY : 1; + unsigned int ME_WC_BUSY : 1; + unsigned int : 2; + unsigned int ME_BUSY : 1; + unsigned int : 2; + unsigned int _3D_BUSY : 1; + unsigned int CP_NRT_BUSY : 1; + unsigned int MIU_WC_STALL : 1; + unsigned int MEQ_INDIRECT2_BUSY : 1; + unsigned int MEQ_INDIRECTS_BUSY : 1; + unsigned int MEQ_RING_BUSY : 1; + unsigned int PFP_BUSY : 1; + unsigned int ST_QUEUE_BUSY : 1; + unsigned int : 2; + unsigned int INDIRECT2_QUEUE_BUSY : 1; + unsigned int INDIRECTS_QUEUE_BUSY : 1; + unsigned int RING_QUEUE_BUSY : 1; + unsigned int CSF_BUSY : 1; + unsigned int CSF_ST_BUSY : 1; + unsigned int : 1; + unsigned int CSF_INDIRECT2_BUSY : 1; + unsigned int CSF_INDIRECTS_BUSY : 1; + unsigned int CSF_RING_BUSY : 1; + unsigned int RCIU_BUSY : 1; + unsigned int RBIU_BUSY : 1; + unsigned int MIU_RD_RETURN_BUSY : 1; + unsigned int MIU_RD_REQ_BUSY : 1; + unsigned int MIU_WR_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_0_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_1_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_2_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_3_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_4_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_5_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_6_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_7_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_8_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_9_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_10_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_11_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_12_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_13_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_14_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_15_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_SIZE_PM4 { + struct { +#if defined(qLittleEndian) + unsigned int SIZE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SIZE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_BASE_PM4 { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BASE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_STATUS_PM4 { + struct { +#if defined(qLittleEndian) + unsigned int MATCHING_CONTEXTS : 8; + unsigned int RB_COPY_DEST_BASE_ENA : 1; + unsigned int DEST_BASE_0_ENA : 1; + unsigned int DEST_BASE_1_ENA : 1; + unsigned int DEST_BASE_2_ENA : 1; + unsigned int DEST_BASE_3_ENA : 1; + unsigned int DEST_BASE_4_ENA : 1; + unsigned int DEST_BASE_5_ENA : 1; + unsigned int DEST_BASE_6_ENA : 1; + unsigned int DEST_BASE_7_ENA : 1; + unsigned int : 8; + unsigned int TC_ACTION_ENA : 1; + unsigned int : 5; + unsigned int STATUS : 1; +#else /* !defined(qLittleEndian) */ + unsigned int STATUS : 1; + unsigned int : 5; + unsigned int TC_ACTION_ENA : 1; + unsigned int : 8; + unsigned int DEST_BASE_7_ENA : 1; + unsigned int DEST_BASE_6_ENA : 1; + unsigned int DEST_BASE_5_ENA : 1; + unsigned int DEST_BASE_4_ENA : 1; + unsigned int DEST_BASE_3_ENA : 1; + unsigned int DEST_BASE_2_ENA : 1; + unsigned int DEST_BASE_1_ENA : 1; + unsigned int DEST_BASE_0_ENA : 1; + unsigned int RB_COPY_DEST_BASE_ENA : 1; + unsigned int MATCHING_CONTEXTS : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_SIZE_HOST { + struct { +#if defined(qLittleEndian) + unsigned int SIZE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SIZE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_BASE_HOST { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BASE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_STATUS_HOST { + struct { +#if defined(qLittleEndian) + unsigned int MATCHING_CONTEXTS : 8; + unsigned int RB_COPY_DEST_BASE_ENA : 1; + unsigned int DEST_BASE_0_ENA : 1; + unsigned int DEST_BASE_1_ENA : 1; + unsigned int DEST_BASE_2_ENA : 1; + unsigned int DEST_BASE_3_ENA : 1; + unsigned int DEST_BASE_4_ENA : 1; + unsigned int DEST_BASE_5_ENA : 1; + unsigned int DEST_BASE_6_ENA : 1; + unsigned int DEST_BASE_7_ENA : 1; + unsigned int : 8; + unsigned int TC_ACTION_ENA : 1; + unsigned int : 5; + unsigned int STATUS : 1; +#else /* !defined(qLittleEndian) */ + unsigned int STATUS : 1; + unsigned int : 5; + unsigned int TC_ACTION_ENA : 1; + unsigned int : 8; + unsigned int DEST_BASE_7_ENA : 1; + unsigned int DEST_BASE_6_ENA : 1; + unsigned int DEST_BASE_5_ENA : 1; + unsigned int DEST_BASE_4_ENA : 1; + unsigned int DEST_BASE_3_ENA : 1; + unsigned int DEST_BASE_2_ENA : 1; + unsigned int DEST_BASE_1_ENA : 1; + unsigned int DEST_BASE_0_ENA : 1; + unsigned int RB_COPY_DEST_BASE_ENA : 1; + unsigned int MATCHING_CONTEXTS : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_0 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_0 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_0 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_1 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_1 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_1 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_2 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_2 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_2 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_3 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_3 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_3 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_4 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_4 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_4 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_5 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_5 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_5 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_6 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_6 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_6 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_7 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_7 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_7 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_SURFACE_INFO { + struct { +#if defined(qLittleEndian) + unsigned int SURFACE_PITCH : 14; + unsigned int MSAA_SAMPLES : 2; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int MSAA_SAMPLES : 2; + unsigned int SURFACE_PITCH : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COLOR_INFO { + struct { +#if defined(qLittleEndian) + unsigned int COLOR_FORMAT : 4; + unsigned int COLOR_ROUND_MODE : 2; + unsigned int COLOR_LINEAR : 1; + unsigned int COLOR_ENDIAN : 2; + unsigned int COLOR_SWAP : 2; + unsigned int : 1; + unsigned int COLOR_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int COLOR_BASE : 20; + unsigned int : 1; + unsigned int COLOR_SWAP : 2; + unsigned int COLOR_ENDIAN : 2; + unsigned int COLOR_LINEAR : 1; + unsigned int COLOR_ROUND_MODE : 2; + unsigned int COLOR_FORMAT : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEPTH_INFO { + struct { +#if defined(qLittleEndian) + unsigned int DEPTH_FORMAT : 1; + unsigned int : 11; + unsigned int DEPTH_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEPTH_BASE : 20; + unsigned int : 11; + unsigned int DEPTH_FORMAT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_STENCILREFMASK { + struct { +#if defined(qLittleEndian) + unsigned int STENCILREF : 8; + unsigned int STENCILMASK : 8; + unsigned int STENCILWRITEMASK : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int STENCILWRITEMASK : 8; + unsigned int STENCILMASK : 8; + unsigned int STENCILREF : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_ALPHA_REF { + struct { +#if defined(qLittleEndian) + unsigned int ALPHA_REF : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ALPHA_REF : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COLOR_MASK { + struct { +#if defined(qLittleEndian) + unsigned int WRITE_RED : 1; + unsigned int WRITE_GREEN : 1; + unsigned int WRITE_BLUE : 1; + unsigned int WRITE_ALPHA : 1; + unsigned int : 28; +#else /* !defined(qLittleEndian) */ + unsigned int : 28; + unsigned int WRITE_ALPHA : 1; + unsigned int WRITE_BLUE : 1; + unsigned int WRITE_GREEN : 1; + unsigned int WRITE_RED : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLEND_RED { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_RED : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int BLEND_RED : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLEND_GREEN { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_GREEN : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int BLEND_GREEN : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLEND_BLUE { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_BLUE : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int BLEND_BLUE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLEND_ALPHA { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_ALPHA : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int BLEND_ALPHA : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_FOG_COLOR { + struct { +#if defined(qLittleEndian) + unsigned int FOG_RED : 8; + unsigned int FOG_GREEN : 8; + unsigned int FOG_BLUE : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int FOG_BLUE : 8; + unsigned int FOG_GREEN : 8; + unsigned int FOG_RED : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_STENCILREFMASK_BF { + struct { +#if defined(qLittleEndian) + unsigned int STENCILREF_BF : 8; + unsigned int STENCILMASK_BF : 8; + unsigned int STENCILWRITEMASK_BF : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int STENCILWRITEMASK_BF : 8; + unsigned int STENCILMASK_BF : 8; + unsigned int STENCILREF_BF : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEPTHCONTROL { + struct { +#if defined(qLittleEndian) + unsigned int STENCIL_ENABLE : 1; + unsigned int Z_ENABLE : 1; + unsigned int Z_WRITE_ENABLE : 1; + unsigned int EARLY_Z_ENABLE : 1; + unsigned int ZFUNC : 3; + unsigned int BACKFACE_ENABLE : 1; + unsigned int STENCILFUNC : 3; + unsigned int STENCILFAIL : 3; + unsigned int STENCILZPASS : 3; + unsigned int STENCILZFAIL : 3; + unsigned int STENCILFUNC_BF : 3; + unsigned int STENCILFAIL_BF : 3; + unsigned int STENCILZPASS_BF : 3; + unsigned int STENCILZFAIL_BF : 3; +#else /* !defined(qLittleEndian) */ + unsigned int STENCILZFAIL_BF : 3; + unsigned int STENCILZPASS_BF : 3; + unsigned int STENCILFAIL_BF : 3; + unsigned int STENCILFUNC_BF : 3; + unsigned int STENCILZFAIL : 3; + unsigned int STENCILZPASS : 3; + unsigned int STENCILFAIL : 3; + unsigned int STENCILFUNC : 3; + unsigned int BACKFACE_ENABLE : 1; + unsigned int ZFUNC : 3; + unsigned int EARLY_Z_ENABLE : 1; + unsigned int Z_WRITE_ENABLE : 1; + unsigned int Z_ENABLE : 1; + unsigned int STENCIL_ENABLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLENDCONTROL { + struct { +#if defined(qLittleEndian) + unsigned int COLOR_SRCBLEND : 5; + unsigned int COLOR_COMB_FCN : 3; + unsigned int COLOR_DESTBLEND : 5; + unsigned int : 3; + unsigned int ALPHA_SRCBLEND : 5; + unsigned int ALPHA_COMB_FCN : 3; + unsigned int ALPHA_DESTBLEND : 5; + unsigned int BLEND_FORCE_ENABLE : 1; + unsigned int BLEND_FORCE : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int BLEND_FORCE : 1; + unsigned int BLEND_FORCE_ENABLE : 1; + unsigned int ALPHA_DESTBLEND : 5; + unsigned int ALPHA_COMB_FCN : 3; + unsigned int ALPHA_SRCBLEND : 5; + unsigned int : 3; + unsigned int COLOR_DESTBLEND : 5; + unsigned int COLOR_COMB_FCN : 3; + unsigned int COLOR_SRCBLEND : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COLORCONTROL { + struct { +#if defined(qLittleEndian) + unsigned int ALPHA_FUNC : 3; + unsigned int ALPHA_TEST_ENABLE : 1; + unsigned int ALPHA_TO_MASK_ENABLE : 1; + unsigned int BLEND_DISABLE : 1; + unsigned int FOG_ENABLE : 1; + unsigned int VS_EXPORTS_FOG : 1; + unsigned int ROP_CODE : 4; + unsigned int DITHER_MODE : 2; + unsigned int DITHER_TYPE : 2; + unsigned int PIXEL_FOG : 1; + unsigned int : 7; + unsigned int ALPHA_TO_MASK_OFFSET0 : 2; + unsigned int ALPHA_TO_MASK_OFFSET1 : 2; + unsigned int ALPHA_TO_MASK_OFFSET2 : 2; + unsigned int ALPHA_TO_MASK_OFFSET3 : 2; +#else /* !defined(qLittleEndian) */ + unsigned int ALPHA_TO_MASK_OFFSET3 : 2; + unsigned int ALPHA_TO_MASK_OFFSET2 : 2; + unsigned int ALPHA_TO_MASK_OFFSET1 : 2; + unsigned int ALPHA_TO_MASK_OFFSET0 : 2; + unsigned int : 7; + unsigned int PIXEL_FOG : 1; + unsigned int DITHER_TYPE : 2; + unsigned int DITHER_MODE : 2; + unsigned int ROP_CODE : 4; + unsigned int VS_EXPORTS_FOG : 1; + unsigned int FOG_ENABLE : 1; + unsigned int BLEND_DISABLE : 1; + unsigned int ALPHA_TO_MASK_ENABLE : 1; + unsigned int ALPHA_TEST_ENABLE : 1; + unsigned int ALPHA_FUNC : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_MODECONTROL { + struct { +#if defined(qLittleEndian) + unsigned int EDRAM_MODE : 3; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int EDRAM_MODE : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COLOR_DEST_MASK { + struct { +#if defined(qLittleEndian) + unsigned int COLOR_DEST_MASK : 32; +#else /* !defined(qLittleEndian) */ + unsigned int COLOR_DEST_MASK : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int COPY_SAMPLE_SELECT : 3; + unsigned int DEPTH_CLEAR_ENABLE : 1; + unsigned int CLEAR_MASK : 4; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int CLEAR_MASK : 4; + unsigned int DEPTH_CLEAR_ENABLE : 1; + unsigned int COPY_SAMPLE_SELECT : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_DEST_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int COPY_DEST_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int COPY_DEST_BASE : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_DEST_PITCH { + struct { +#if defined(qLittleEndian) + unsigned int COPY_DEST_PITCH : 9; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int COPY_DEST_PITCH : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_DEST_INFO { + struct { +#if defined(qLittleEndian) + unsigned int COPY_DEST_ENDIAN : 3; + unsigned int COPY_DEST_LINEAR : 1; + unsigned int COPY_DEST_FORMAT : 4; + unsigned int COPY_DEST_SWAP : 2; + unsigned int COPY_DEST_DITHER_MODE : 2; + unsigned int COPY_DEST_DITHER_TYPE : 2; + unsigned int COPY_MASK_WRITE_RED : 1; + unsigned int COPY_MASK_WRITE_GREEN : 1; + unsigned int COPY_MASK_WRITE_BLUE : 1; + unsigned int COPY_MASK_WRITE_ALPHA : 1; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int COPY_MASK_WRITE_ALPHA : 1; + unsigned int COPY_MASK_WRITE_BLUE : 1; + unsigned int COPY_MASK_WRITE_GREEN : 1; + unsigned int COPY_MASK_WRITE_RED : 1; + unsigned int COPY_DEST_DITHER_TYPE : 2; + unsigned int COPY_DEST_DITHER_MODE : 2; + unsigned int COPY_DEST_SWAP : 2; + unsigned int COPY_DEST_FORMAT : 4; + unsigned int COPY_DEST_LINEAR : 1; + unsigned int COPY_DEST_ENDIAN : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_DEST_PIXEL_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int OFFSET_X : 13; + unsigned int OFFSET_Y : 13; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int OFFSET_Y : 13; + unsigned int OFFSET_X : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEPTH_CLEAR { + struct { +#if defined(qLittleEndian) + unsigned int DEPTH_CLEAR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DEPTH_CLEAR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_SAMPLE_COUNT_CTL { + struct { +#if defined(qLittleEndian) + unsigned int RESET_SAMPLE_COUNT : 1; + unsigned int COPY_SAMPLE_COUNT : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int COPY_SAMPLE_COUNT : 1; + unsigned int RESET_SAMPLE_COUNT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_SAMPLE_COUNT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int SAMPLE_COUNT_ADDR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SAMPLE_COUNT_ADDR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BC_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int ACCUM_LINEAR_MODE_ENABLE : 1; + unsigned int ACCUM_TIMEOUT_SELECT : 2; + unsigned int DISABLE_EDRAM_CAM : 1; + unsigned int DISABLE_EZ_FAST_CONTEXT_SWITCH : 1; + unsigned int DISABLE_EZ_NULL_ZCMD_DROP : 1; + unsigned int DISABLE_LZ_NULL_ZCMD_DROP : 1; + unsigned int ENABLE_AZ_THROTTLE : 1; + unsigned int AZ_THROTTLE_COUNT : 5; + unsigned int : 1; + unsigned int ENABLE_CRC_UPDATE : 1; + unsigned int CRC_MODE : 1; + unsigned int DISABLE_SAMPLE_COUNTERS : 1; + unsigned int DISABLE_ACCUM : 1; + unsigned int ACCUM_ALLOC_MASK : 4; + unsigned int LINEAR_PERFORMANCE_ENABLE : 1; + unsigned int ACCUM_DATA_FIFO_LIMIT : 4; + unsigned int MEM_EXPORT_TIMEOUT_SELECT : 2; + unsigned int MEM_EXPORT_LINEAR_MODE_ENABLE : 1; + unsigned int RESERVED9 : 1; + unsigned int RESERVED10 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED10 : 1; + unsigned int RESERVED9 : 1; + unsigned int MEM_EXPORT_LINEAR_MODE_ENABLE : 1; + unsigned int MEM_EXPORT_TIMEOUT_SELECT : 2; + unsigned int ACCUM_DATA_FIFO_LIMIT : 4; + unsigned int LINEAR_PERFORMANCE_ENABLE : 1; + unsigned int ACCUM_ALLOC_MASK : 4; + unsigned int DISABLE_ACCUM : 1; + unsigned int DISABLE_SAMPLE_COUNTERS : 1; + unsigned int CRC_MODE : 1; + unsigned int ENABLE_CRC_UPDATE : 1; + unsigned int : 1; + unsigned int AZ_THROTTLE_COUNT : 5; + unsigned int ENABLE_AZ_THROTTLE : 1; + unsigned int DISABLE_LZ_NULL_ZCMD_DROP : 1; + unsigned int DISABLE_EZ_NULL_ZCMD_DROP : 1; + unsigned int DISABLE_EZ_FAST_CONTEXT_SWITCH : 1; + unsigned int DISABLE_EDRAM_CAM : 1; + unsigned int ACCUM_TIMEOUT_SELECT : 2; + unsigned int ACCUM_LINEAR_MODE_ENABLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_EDRAM_INFO { + struct { +#if defined(qLittleEndian) + unsigned int EDRAM_SIZE : 4; + unsigned int EDRAM_MAPPING_MODE : 2; + unsigned int : 8; + unsigned int EDRAM_RANGE : 18; +#else /* !defined(qLittleEndian) */ + unsigned int EDRAM_RANGE : 18; + unsigned int : 8; + unsigned int EDRAM_MAPPING_MODE : 2; + unsigned int EDRAM_SIZE : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_CRC_RD_PORT { + struct { +#if defined(qLittleEndian) + unsigned int CRC_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CRC_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_CRC_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int CRC_RD_ADVANCE : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int CRC_RD_ADVANCE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_CRC_MASK { + struct { +#if defined(qLittleEndian) + unsigned int CRC_MASK : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CRC_MASK : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_TOTAL_SAMPLES { + struct { +#if defined(qLittleEndian) + unsigned int TOTAL_SAMPLES : 32; +#else /* !defined(qLittleEndian) */ + unsigned int TOTAL_SAMPLES : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_ZPASS_SAMPLES { + struct { +#if defined(qLittleEndian) + unsigned int ZPASS_SAMPLES : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ZPASS_SAMPLES : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_ZFAIL_SAMPLES { + struct { +#if defined(qLittleEndian) + unsigned int ZFAIL_SAMPLES : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ZFAIL_SAMPLES : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_SFAIL_SAMPLES { + struct { +#if defined(qLittleEndian) + unsigned int SFAIL_SAMPLES : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SFAIL_SAMPLES : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_0 { + struct { +#if defined(qLittleEndian) + unsigned int RDREQ_CTL_Z1_PRE_FULL : 1; + unsigned int RDREQ_CTL_Z0_PRE_FULL : 1; + unsigned int RDREQ_CTL_C1_PRE_FULL : 1; + unsigned int RDREQ_CTL_C0_PRE_FULL : 1; + unsigned int RDREQ_E1_ORDERING_FULL : 1; + unsigned int RDREQ_E0_ORDERING_FULL : 1; + unsigned int RDREQ_Z1_FULL : 1; + unsigned int RDREQ_Z0_FULL : 1; + unsigned int RDREQ_C1_FULL : 1; + unsigned int RDREQ_C0_FULL : 1; + unsigned int WRREQ_E1_MACRO_HI_FULL : 1; + unsigned int WRREQ_E1_MACRO_LO_FULL : 1; + unsigned int WRREQ_E0_MACRO_HI_FULL : 1; + unsigned int WRREQ_E0_MACRO_LO_FULL : 1; + unsigned int WRREQ_C_WE_HI_FULL : 1; + unsigned int WRREQ_C_WE_LO_FULL : 1; + unsigned int WRREQ_Z1_FULL : 1; + unsigned int WRREQ_Z0_FULL : 1; + unsigned int WRREQ_C1_FULL : 1; + unsigned int WRREQ_C0_FULL : 1; + unsigned int CMDFIFO_Z1_HOLD_FULL : 1; + unsigned int CMDFIFO_Z0_HOLD_FULL : 1; + unsigned int CMDFIFO_C1_HOLD_FULL : 1; + unsigned int CMDFIFO_C0_HOLD_FULL : 1; + unsigned int CMDFIFO_Z_ORDERING_FULL : 1; + unsigned int CMDFIFO_C_ORDERING_FULL : 1; + unsigned int C_SX_LAT_FULL : 1; + unsigned int C_SX_CMD_FULL : 1; + unsigned int C_EZ_TILE_FULL : 1; + unsigned int C_REQ_FULL : 1; + unsigned int C_MASK_FULL : 1; + unsigned int EZ_INFSAMP_FULL : 1; +#else /* !defined(qLittleEndian) */ + unsigned int EZ_INFSAMP_FULL : 1; + unsigned int C_MASK_FULL : 1; + unsigned int C_REQ_FULL : 1; + unsigned int C_EZ_TILE_FULL : 1; + unsigned int C_SX_CMD_FULL : 1; + unsigned int C_SX_LAT_FULL : 1; + unsigned int CMDFIFO_C_ORDERING_FULL : 1; + unsigned int CMDFIFO_Z_ORDERING_FULL : 1; + unsigned int CMDFIFO_C0_HOLD_FULL : 1; + unsigned int CMDFIFO_C1_HOLD_FULL : 1; + unsigned int CMDFIFO_Z0_HOLD_FULL : 1; + unsigned int CMDFIFO_Z1_HOLD_FULL : 1; + unsigned int WRREQ_C0_FULL : 1; + unsigned int WRREQ_C1_FULL : 1; + unsigned int WRREQ_Z0_FULL : 1; + unsigned int WRREQ_Z1_FULL : 1; + unsigned int WRREQ_C_WE_LO_FULL : 1; + unsigned int WRREQ_C_WE_HI_FULL : 1; + unsigned int WRREQ_E0_MACRO_LO_FULL : 1; + unsigned int WRREQ_E0_MACRO_HI_FULL : 1; + unsigned int WRREQ_E1_MACRO_LO_FULL : 1; + unsigned int WRREQ_E1_MACRO_HI_FULL : 1; + unsigned int RDREQ_C0_FULL : 1; + unsigned int RDREQ_C1_FULL : 1; + unsigned int RDREQ_Z0_FULL : 1; + unsigned int RDREQ_Z1_FULL : 1; + unsigned int RDREQ_E0_ORDERING_FULL : 1; + unsigned int RDREQ_E1_ORDERING_FULL : 1; + unsigned int RDREQ_CTL_C0_PRE_FULL : 1; + unsigned int RDREQ_CTL_C1_PRE_FULL : 1; + unsigned int RDREQ_CTL_Z0_PRE_FULL : 1; + unsigned int RDREQ_CTL_Z1_PRE_FULL : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_1 { + struct { +#if defined(qLittleEndian) + unsigned int RDREQ_Z1_CMD_EMPTY : 1; + unsigned int RDREQ_Z0_CMD_EMPTY : 1; + unsigned int RDREQ_C1_CMD_EMPTY : 1; + unsigned int RDREQ_C0_CMD_EMPTY : 1; + unsigned int RDREQ_E1_ORDERING_EMPTY : 1; + unsigned int RDREQ_E0_ORDERING_EMPTY : 1; + unsigned int RDREQ_Z1_EMPTY : 1; + unsigned int RDREQ_Z0_EMPTY : 1; + unsigned int RDREQ_C1_EMPTY : 1; + unsigned int RDREQ_C0_EMPTY : 1; + unsigned int WRREQ_E1_MACRO_HI_EMPTY : 1; + unsigned int WRREQ_E1_MACRO_LO_EMPTY : 1; + unsigned int WRREQ_E0_MACRO_HI_EMPTY : 1; + unsigned int WRREQ_E0_MACRO_LO_EMPTY : 1; + unsigned int WRREQ_C_WE_HI_EMPTY : 1; + unsigned int WRREQ_C_WE_LO_EMPTY : 1; + unsigned int WRREQ_Z1_EMPTY : 1; + unsigned int WRREQ_Z0_EMPTY : 1; + unsigned int WRREQ_C1_PRE_EMPTY : 1; + unsigned int WRREQ_C0_PRE_EMPTY : 1; + unsigned int CMDFIFO_Z1_HOLD_EMPTY : 1; + unsigned int CMDFIFO_Z0_HOLD_EMPTY : 1; + unsigned int CMDFIFO_C1_HOLD_EMPTY : 1; + unsigned int CMDFIFO_C0_HOLD_EMPTY : 1; + unsigned int CMDFIFO_Z_ORDERING_EMPTY : 1; + unsigned int CMDFIFO_C_ORDERING_EMPTY : 1; + unsigned int C_SX_LAT_EMPTY : 1; + unsigned int C_SX_CMD_EMPTY : 1; + unsigned int C_EZ_TILE_EMPTY : 1; + unsigned int C_REQ_EMPTY : 1; + unsigned int C_MASK_EMPTY : 1; + unsigned int EZ_INFSAMP_EMPTY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int EZ_INFSAMP_EMPTY : 1; + unsigned int C_MASK_EMPTY : 1; + unsigned int C_REQ_EMPTY : 1; + unsigned int C_EZ_TILE_EMPTY : 1; + unsigned int C_SX_CMD_EMPTY : 1; + unsigned int C_SX_LAT_EMPTY : 1; + unsigned int CMDFIFO_C_ORDERING_EMPTY : 1; + unsigned int CMDFIFO_Z_ORDERING_EMPTY : 1; + unsigned int CMDFIFO_C0_HOLD_EMPTY : 1; + unsigned int CMDFIFO_C1_HOLD_EMPTY : 1; + unsigned int CMDFIFO_Z0_HOLD_EMPTY : 1; + unsigned int CMDFIFO_Z1_HOLD_EMPTY : 1; + unsigned int WRREQ_C0_PRE_EMPTY : 1; + unsigned int WRREQ_C1_PRE_EMPTY : 1; + unsigned int WRREQ_Z0_EMPTY : 1; + unsigned int WRREQ_Z1_EMPTY : 1; + unsigned int WRREQ_C_WE_LO_EMPTY : 1; + unsigned int WRREQ_C_WE_HI_EMPTY : 1; + unsigned int WRREQ_E0_MACRO_LO_EMPTY : 1; + unsigned int WRREQ_E0_MACRO_HI_EMPTY : 1; + unsigned int WRREQ_E1_MACRO_LO_EMPTY : 1; + unsigned int WRREQ_E1_MACRO_HI_EMPTY : 1; + unsigned int RDREQ_C0_EMPTY : 1; + unsigned int RDREQ_C1_EMPTY : 1; + unsigned int RDREQ_Z0_EMPTY : 1; + unsigned int RDREQ_Z1_EMPTY : 1; + unsigned int RDREQ_E0_ORDERING_EMPTY : 1; + unsigned int RDREQ_E1_ORDERING_EMPTY : 1; + unsigned int RDREQ_C0_CMD_EMPTY : 1; + unsigned int RDREQ_C1_CMD_EMPTY : 1; + unsigned int RDREQ_Z0_CMD_EMPTY : 1; + unsigned int RDREQ_Z1_CMD_EMPTY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_2 { + struct { +#if defined(qLittleEndian) + unsigned int TILE_FIFO_COUNT : 4; + unsigned int SX_LAT_FIFO_COUNT : 7; + unsigned int MEM_EXPORT_FLAG : 1; + unsigned int SYSMEM_BLEND_FLAG : 1; + unsigned int CURRENT_TILE_EVENT : 1; + unsigned int EZ_INFTILE_FULL : 1; + unsigned int EZ_MASK_LOWER_FULL : 1; + unsigned int EZ_MASK_UPPER_FULL : 1; + unsigned int Z0_MASK_FULL : 1; + unsigned int Z1_MASK_FULL : 1; + unsigned int Z0_REQ_FULL : 1; + unsigned int Z1_REQ_FULL : 1; + unsigned int Z_SAMP_FULL : 1; + unsigned int Z_TILE_FULL : 1; + unsigned int EZ_INFTILE_EMPTY : 1; + unsigned int EZ_MASK_LOWER_EMPTY : 1; + unsigned int EZ_MASK_UPPER_EMPTY : 1; + unsigned int Z0_MASK_EMPTY : 1; + unsigned int Z1_MASK_EMPTY : 1; + unsigned int Z0_REQ_EMPTY : 1; + unsigned int Z1_REQ_EMPTY : 1; + unsigned int Z_SAMP_EMPTY : 1; + unsigned int Z_TILE_EMPTY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int Z_TILE_EMPTY : 1; + unsigned int Z_SAMP_EMPTY : 1; + unsigned int Z1_REQ_EMPTY : 1; + unsigned int Z0_REQ_EMPTY : 1; + unsigned int Z1_MASK_EMPTY : 1; + unsigned int Z0_MASK_EMPTY : 1; + unsigned int EZ_MASK_UPPER_EMPTY : 1; + unsigned int EZ_MASK_LOWER_EMPTY : 1; + unsigned int EZ_INFTILE_EMPTY : 1; + unsigned int Z_TILE_FULL : 1; + unsigned int Z_SAMP_FULL : 1; + unsigned int Z1_REQ_FULL : 1; + unsigned int Z0_REQ_FULL : 1; + unsigned int Z1_MASK_FULL : 1; + unsigned int Z0_MASK_FULL : 1; + unsigned int EZ_MASK_UPPER_FULL : 1; + unsigned int EZ_MASK_LOWER_FULL : 1; + unsigned int EZ_INFTILE_FULL : 1; + unsigned int CURRENT_TILE_EVENT : 1; + unsigned int SYSMEM_BLEND_FLAG : 1; + unsigned int MEM_EXPORT_FLAG : 1; + unsigned int SX_LAT_FIFO_COUNT : 7; + unsigned int TILE_FIFO_COUNT : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_3 { + struct { +#if defined(qLittleEndian) + unsigned int ACCUM_VALID : 4; + unsigned int ACCUM_FLUSHING : 4; + unsigned int ACCUM_WRITE_CLEAN_COUNT : 6; + unsigned int ACCUM_INPUT_REG_VALID : 1; + unsigned int ACCUM_DATA_FIFO_CNT : 4; + unsigned int SHD_FULL : 1; + unsigned int SHD_EMPTY : 1; + unsigned int EZ_RETURN_LOWER_EMPTY : 1; + unsigned int EZ_RETURN_UPPER_EMPTY : 1; + unsigned int EZ_RETURN_LOWER_FULL : 1; + unsigned int EZ_RETURN_UPPER_FULL : 1; + unsigned int ZEXP_LOWER_EMPTY : 1; + unsigned int ZEXP_UPPER_EMPTY : 1; + unsigned int ZEXP_LOWER_FULL : 1; + unsigned int ZEXP_UPPER_FULL : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int ZEXP_UPPER_FULL : 1; + unsigned int ZEXP_LOWER_FULL : 1; + unsigned int ZEXP_UPPER_EMPTY : 1; + unsigned int ZEXP_LOWER_EMPTY : 1; + unsigned int EZ_RETURN_UPPER_FULL : 1; + unsigned int EZ_RETURN_LOWER_FULL : 1; + unsigned int EZ_RETURN_UPPER_EMPTY : 1; + unsigned int EZ_RETURN_LOWER_EMPTY : 1; + unsigned int SHD_EMPTY : 1; + unsigned int SHD_FULL : 1; + unsigned int ACCUM_DATA_FIFO_CNT : 4; + unsigned int ACCUM_INPUT_REG_VALID : 1; + unsigned int ACCUM_WRITE_CLEAN_COUNT : 6; + unsigned int ACCUM_FLUSHING : 4; + unsigned int ACCUM_VALID : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_4 { + struct { +#if defined(qLittleEndian) + unsigned int GMEM_RD_ACCESS_FLAG : 1; + unsigned int GMEM_WR_ACCESS_FLAG : 1; + unsigned int SYSMEM_RD_ACCESS_FLAG : 1; + unsigned int SYSMEM_WR_ACCESS_FLAG : 1; + unsigned int ACCUM_DATA_FIFO_EMPTY : 1; + unsigned int ACCUM_ORDER_FIFO_EMPTY : 1; + unsigned int ACCUM_DATA_FIFO_FULL : 1; + unsigned int ACCUM_ORDER_FIFO_FULL : 1; + unsigned int SYSMEM_WRITE_COUNT_OVERFLOW : 1; + unsigned int CONTEXT_COUNT_DEBUG : 4; + unsigned int : 19; +#else /* !defined(qLittleEndian) */ + unsigned int : 19; + unsigned int CONTEXT_COUNT_DEBUG : 4; + unsigned int SYSMEM_WRITE_COUNT_OVERFLOW : 1; + unsigned int ACCUM_ORDER_FIFO_FULL : 1; + unsigned int ACCUM_DATA_FIFO_FULL : 1; + unsigned int ACCUM_ORDER_FIFO_EMPTY : 1; + unsigned int ACCUM_DATA_FIFO_EMPTY : 1; + unsigned int SYSMEM_WR_ACCESS_FLAG : 1; + unsigned int SYSMEM_RD_ACCESS_FLAG : 1; + unsigned int GMEM_WR_ACCESS_FLAG : 1; + unsigned int GMEM_RD_ACCESS_FLAG : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_FLAG_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int DEBUG_FLAG_CLEAR : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int DEBUG_FLAG_CLEAR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BC_DUMMY_CRAYRB_ENUMS { + struct { +#if defined(qLittleEndian) + unsigned int DUMMY_CRAYRB_DEPTH_FORMAT : 6; + unsigned int DUMMY_CRAYRB_SURFACE_SWAP : 1; + unsigned int DUMMY_CRAYRB_DEPTH_ARRAY : 2; + unsigned int DUMMY_CRAYRB_ARRAY : 2; + unsigned int DUMMY_CRAYRB_COLOR_FORMAT : 6; + unsigned int DUMMY_CRAYRB_SURFACE_NUMBER : 3; + unsigned int DUMMY_CRAYRB_SURFACE_FORMAT : 6; + unsigned int DUMMY_CRAYRB_SURFACE_TILING : 1; + unsigned int DUMMY_CRAYRB_SURFACE_ARRAY : 2; + unsigned int DUMMY_RB_COPY_DEST_INFO_NUMBER : 3; +#else /* !defined(qLittleEndian) */ + unsigned int DUMMY_RB_COPY_DEST_INFO_NUMBER : 3; + unsigned int DUMMY_CRAYRB_SURFACE_ARRAY : 2; + unsigned int DUMMY_CRAYRB_SURFACE_TILING : 1; + unsigned int DUMMY_CRAYRB_SURFACE_FORMAT : 6; + unsigned int DUMMY_CRAYRB_SURFACE_NUMBER : 3; + unsigned int DUMMY_CRAYRB_COLOR_FORMAT : 6; + unsigned int DUMMY_CRAYRB_ARRAY : 2; + unsigned int DUMMY_CRAYRB_DEPTH_ARRAY : 2; + unsigned int DUMMY_CRAYRB_SURFACE_SWAP : 1; + unsigned int DUMMY_CRAYRB_DEPTH_FORMAT : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BC_DUMMY_CRAYRB_MOREENUMS { + struct { +#if defined(qLittleEndian) + unsigned int DUMMY_CRAYRB_COLORARRAYX : 2; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int DUMMY_CRAYRB_COLORARRAYX : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_shift.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_shift.h new file mode 100644 index 000000000000..2049d0f7bd14 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_shift.h @@ -0,0 +1,4078 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_SHIFT_HEADER) +#define _yamato_SHIFT_HEADER + +// PA_CL_VPORT_XSCALE +#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x00000000 + +// PA_CL_VPORT_XOFFSET +#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x00000000 + +// PA_CL_VPORT_YSCALE +#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x00000000 + +// PA_CL_VPORT_YOFFSET +#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x00000000 + +// PA_CL_VPORT_ZSCALE +#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x00000000 + +// PA_CL_VPORT_ZOFFSET +#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x00000000 + +// PA_CL_VTE_CNTL +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x00000000 +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x00000001 +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x00000002 +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x00000003 +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x00000004 +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x00000005 +#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x00000008 +#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x00000009 +#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0x0000000a +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0x0000000b + +// PA_CL_CLIP_CNTL +#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x00000010 +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x00000012 +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x00000013 +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x00000014 +#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x00000015 +#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN__SHIFT 0x00000016 +#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN__SHIFT 0x00000017 +#define PA_CL_CLIP_CNTL__W_NAN_RETAIN__SHIFT 0x00000018 + +// PA_CL_GB_VERT_CLIP_ADJ +#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x00000000 + +// PA_CL_GB_VERT_DISC_ADJ +#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x00000000 + +// PA_CL_GB_HORZ_CLIP_ADJ +#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x00000000 + +// PA_CL_GB_HORZ_DISC_ADJ +#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x00000000 + +// PA_CL_ENHANCE +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x00000000 +#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x0000001c +#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x0000001d +#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x0000001e +#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x0000001f + +// PA_SC_ENHANCE +#define PA_SC_ENHANCE__ECO_SPARE3__SHIFT 0x0000001c +#define PA_SC_ENHANCE__ECO_SPARE2__SHIFT 0x0000001d +#define PA_SC_ENHANCE__ECO_SPARE1__SHIFT 0x0000001e +#define PA_SC_ENHANCE__ECO_SPARE0__SHIFT 0x0000001f + +// PA_SU_VTX_CNTL +#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x00000000 +#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x00000001 +#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x00000003 + +// PA_SU_POINT_SIZE +#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x00000000 +#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x00000010 + +// PA_SU_POINT_MINMAX +#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x00000000 +#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x00000010 + +// PA_SU_LINE_CNTL +#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x00000000 + +// PA_SU_SC_MODE_CNTL +#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x00000000 +#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x00000001 +#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x00000002 +#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x00000003 +#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x00000005 +#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x00000008 +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0x0000000b +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0x0000000c +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0x0000000d +#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE__SHIFT 0x0000000f +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x00000010 +#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE__SHIFT 0x00000012 +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x00000013 +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x00000014 +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x00000015 +#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE__SHIFT 0x00000017 +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI__SHIFT 0x00000019 +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE__SHIFT 0x0000001a + +// PA_SU_POLY_OFFSET_FRONT_SCALE +#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x00000000 + +// PA_SU_POLY_OFFSET_FRONT_OFFSET +#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x00000000 + +// PA_SU_POLY_OFFSET_BACK_SCALE +#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x00000000 + +// PA_SU_POLY_OFFSET_BACK_OFFSET +#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER0_SELECT +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER1_SELECT +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER2_SELECT +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER3_SELECT +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER0_LOW +#define PA_SU_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER0_HI +#define PA_SU_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER1_LOW +#define PA_SU_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER1_HI +#define PA_SU_PERFCOUNTER1_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER2_LOW +#define PA_SU_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER2_HI +#define PA_SU_PERFCOUNTER2_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER3_LOW +#define PA_SU_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER3_HI +#define PA_SU_PERFCOUNTER3_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_SC_WINDOW_OFFSET +#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x00000000 +#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x00000010 + +// PA_SC_AA_CONFIG +#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x00000000 +#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0x0000000d + +// PA_SC_AA_MASK +#define PA_SC_AA_MASK__AA_MASK__SHIFT 0x00000000 + +// PA_SC_LINE_STIPPLE +#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x00000000 +#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x00000010 +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x0000001c +#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x0000001d + +// PA_SC_LINE_CNTL +#define PA_SC_LINE_CNTL__BRES_CNTL__SHIFT 0x00000000 +#define PA_SC_LINE_CNTL__USE_BRES_CNTL__SHIFT 0x00000008 +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x00000009 +#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0x0000000a + +// PA_SC_WINDOW_SCISSOR_TL +#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f + +// PA_SC_WINDOW_SCISSOR_BR +#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x00000010 + +// PA_SC_SCREEN_SCISSOR_TL +#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x00000010 + +// PA_SC_SCREEN_SCISSOR_BR +#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x00000010 + +// PA_SC_VIZ_QUERY +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA__SHIFT 0x00000000 +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ID__SHIFT 0x00000001 +#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z__SHIFT 0x00000007 + +// PA_SC_VIZ_QUERY_STATUS +#define PA_SC_VIZ_QUERY_STATUS__STATUS_BITS__SHIFT 0x00000000 + +// PA_SC_LINE_STIPPLE_STATE +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x00000000 +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x00000008 + +// PA_SC_PERFCOUNTER0_SELECT +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SC_PERFCOUNTER0_LOW +#define PA_SC_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SC_PERFCOUNTER0_HI +#define PA_SC_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_CL_CNTL_STATUS +#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT 0x0000001f + +// PA_SU_CNTL_STATUS +#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x0000001f + +// PA_SC_CNTL_STATUS +#define PA_SC_CNTL_STATUS__SC_BUSY__SHIFT 0x0000001f + +// PA_SU_DEBUG_CNTL +#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT 0x00000000 + +// PA_SU_DEBUG_DATA +#define PA_SU_DEBUG_DATA__DATA__SHIFT 0x00000000 + +// CLIPPER_DEBUG_REG00 +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT 0x00000002 +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT 0x00000003 +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0x00000005 +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x00000009 +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x0000000a +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT 0x0000000d +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x0000000e +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x0000000f +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x00000010 +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x00000011 +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT 0x00000014 + +// CLIPPER_DEBUG_REG01 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x00000002 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim__SHIFT 0x00000005 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_2__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_1__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_0__SHIFT 0x0000000f +#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x00000016 +#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT 0x00000018 + +// CLIPPER_DEBUG_REG02 +#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO1__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG02__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO0__SHIFT 0x00000018 +#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f + +// CLIPPER_DEBUG_REG03 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO3__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x00000003 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO2__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO1__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO0__SHIFT 0x0000001a + +// CLIPPER_DEBUG_REG04 +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO2__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x00000003 +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO1__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO0__SHIFT 0x00000008 + +// CLIPPER_DEBUG_REG05 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO3__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x00000003 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_event_id__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO2__SHIFT 0x00000010 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO1__SHIFT 0x00000016 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000018 +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO0__SHIFT 0x0000001c + +// CLIPPER_DEBUG_REG09 +#define CLIPPER_DEBUG_REG09__clprim_in_back_event__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_2__SHIFT 0x00000002 +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO2__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_1__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO1__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_0__SHIFT 0x0000000e +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO0__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG09__prim_back_valid__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_out_cnt__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_orig_vertices__SHIFT 0x00000019 +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait__SHIFT 0x0000001b +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty__SHIFT 0x0000001c +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_load__SHIFT 0x0000001e + +// CLIPPER_DEBUG_REG10 +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO3__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO2__SHIFT 0x0000000a +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO1__SHIFT 0x00000010 +#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO0__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot__SHIFT 0x00000016 +#define CLIPPER_DEBUG_REG10__clprim_in_back_deallocate_slot__SHIFT 0x00000017 +#define CLIPPER_DEBUG_REG10__clprim_in_back_event_id__SHIFT 0x0000001a + +// CLIPPER_DEBUG_REG11 +#define CLIPPER_DEBUG_REG11__vertval_bits_vertex_vertex_store_msb__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG11__ALWAYS_ZERO__SHIFT 0x00000004 + +// CLIPPER_DEBUG_REG12 +#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO2__SHIFT 0x00000002 +#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty__SHIFT 0x00000005 +#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO1__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG12__vertval_bits_vertex_cc_next_valid__SHIFT 0x0000000f +#define CLIPPER_DEBUG_REG12__clipcc_vertex_store_indx__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO0__SHIFT 0x00000016 + +// CLIPPER_DEBUG_REG13 +#define CLIPPER_DEBUG_REG13__sm0_clip_vert_cnt__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG13__sm0_prim_end_state__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO1__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG13__sm0_vertex_clip_cnt__SHIFT 0x0000000e +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG13__sm0_current_state__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO0__SHIFT 0x0000001b + +// SXIFCCG_DEBUG_REG0 +#define SXIFCCG_DEBUG_REG0__nan_kill_flag__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG0__position_address__SHIFT 0x00000004 +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO2__SHIFT 0x00000007 +#define SXIFCCG_DEBUG_REG0__point_address__SHIFT 0x0000000a +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO1__SHIFT 0x0000000d +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx__SHIFT 0x00000010 +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO0__SHIFT 0x00000011 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask__SHIFT 0x00000013 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci__SHIFT 0x00000017 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc__SHIFT 0x0000001e +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel__SHIFT 0x0000001f + +// SXIFCCG_DEBUG_REG1 +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO3__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty__SHIFT 0x00000002 +#define SXIFCCG_DEBUG_REG1__available_positions__SHIFT 0x00000004 +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO2__SHIFT 0x00000007 +#define SXIFCCG_DEBUG_REG1__sx_pending_advance__SHIFT 0x0000000b +#define SXIFCCG_DEBUG_REG1__sx_receive_indx__SHIFT 0x0000000c +#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector__SHIFT 0x0000000f +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO1__SHIFT 0x00000010 +#define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT 0x00000014 +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO0__SHIFT 0x00000015 +#define SXIFCCG_DEBUG_REG1__pasx_req_cnt__SHIFT 0x00000017 +#define SXIFCCG_DEBUG_REG1__param_cache_base__SHIFT 0x00000019 + +// SXIFCCG_DEBUG_REG2 +#define SXIFCCG_DEBUG_REG2__sx_sent__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3__SHIFT 0x00000001 +#define SXIFCCG_DEBUG_REG2__sx_aux__SHIFT 0x00000002 +#define SXIFCCG_DEBUG_REG2__sx_request_indx__SHIFT 0x00000003 +#define SXIFCCG_DEBUG_REG2__req_active_verts__SHIFT 0x00000009 +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2__SHIFT 0x00000010 +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx__SHIFT 0x00000011 +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO1__SHIFT 0x00000012 +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts__SHIFT 0x00000014 +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO0__SHIFT 0x00000016 +#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded__SHIFT 0x0000001a +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty__SHIFT 0x0000001b +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full__SHIFT 0x0000001c +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_contents__SHIFT 0x0000001d + +// SXIFCCG_DEBUG_REG3 +#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3__SHIFT 0x00000004 +#define SXIFCCG_DEBUG_REG3__available_positions__SHIFT 0x00000005 +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO2__SHIFT 0x00000008 +#define SXIFCCG_DEBUG_REG3__current_state__SHIFT 0x0000000c +#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty__SHIFT 0x0000000e +#define SXIFCCG_DEBUG_REG3__vertex_fifo_full__SHIFT 0x0000000f +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO1__SHIFT 0x00000010 +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty__SHIFT 0x00000012 +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full__SHIFT 0x00000013 +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty__SHIFT 0x00000014 +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full__SHIFT 0x00000015 +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO0__SHIFT 0x00000016 + +// SETUP_DEBUG_REG0 +#define SETUP_DEBUG_REG0__su_cntl_state__SHIFT 0x00000000 +#define SETUP_DEBUG_REG0__pmode_state__SHIFT 0x00000005 +#define SETUP_DEBUG_REG0__ge_stallb__SHIFT 0x0000000b +#define SETUP_DEBUG_REG0__geom_enable__SHIFT 0x0000000c +#define SETUP_DEBUG_REG0__su_clip_baryc_rtr__SHIFT 0x0000000d +#define SETUP_DEBUG_REG0__su_clip_rtr__SHIFT 0x0000000e +#define SETUP_DEBUG_REG0__pfifo_busy__SHIFT 0x0000000f +#define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT 0x00000010 +#define SETUP_DEBUG_REG0__geom_busy__SHIFT 0x00000011 + +// SETUP_DEBUG_REG1 +#define SETUP_DEBUG_REG1__y_sort0_gated_17_4__SHIFT 0x00000000 +#define SETUP_DEBUG_REG1__x_sort0_gated_17_4__SHIFT 0x0000000e + +// SETUP_DEBUG_REG2 +#define SETUP_DEBUG_REG2__y_sort1_gated_17_4__SHIFT 0x00000000 +#define SETUP_DEBUG_REG2__x_sort1_gated_17_4__SHIFT 0x0000000e + +// SETUP_DEBUG_REG3 +#define SETUP_DEBUG_REG3__y_sort2_gated_17_4__SHIFT 0x00000000 +#define SETUP_DEBUG_REG3__x_sort2_gated_17_4__SHIFT 0x0000000e + +// SETUP_DEBUG_REG4 +#define SETUP_DEBUG_REG4__attr_indx_sort0_gated__SHIFT 0x00000000 +#define SETUP_DEBUG_REG4__null_prim_gated__SHIFT 0x0000000b +#define SETUP_DEBUG_REG4__backfacing_gated__SHIFT 0x0000000c +#define SETUP_DEBUG_REG4__st_indx_gated__SHIFT 0x0000000d +#define SETUP_DEBUG_REG4__clipped_gated__SHIFT 0x00000010 +#define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT 0x00000011 +#define SETUP_DEBUG_REG4__xmajor_gated__SHIFT 0x00000014 +#define SETUP_DEBUG_REG4__diamond_rule_gated__SHIFT 0x00000015 +#define SETUP_DEBUG_REG4__type_gated__SHIFT 0x00000017 +#define SETUP_DEBUG_REG4__fpov_gated__SHIFT 0x0000001a +#define SETUP_DEBUG_REG4__pmode_prim_gated__SHIFT 0x0000001b +#define SETUP_DEBUG_REG4__event_gated__SHIFT 0x0000001c +#define SETUP_DEBUG_REG4__eop_gated__SHIFT 0x0000001d + +// SETUP_DEBUG_REG5 +#define SETUP_DEBUG_REG5__attr_indx_sort2_gated__SHIFT 0x00000000 +#define SETUP_DEBUG_REG5__attr_indx_sort1_gated__SHIFT 0x0000000b +#define SETUP_DEBUG_REG5__provoking_vtx_gated__SHIFT 0x00000016 +#define SETUP_DEBUG_REG5__event_id_gated__SHIFT 0x00000018 + +// PA_SC_DEBUG_CNTL +#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT 0x00000000 + +// PA_SC_DEBUG_DATA +#define PA_SC_DEBUG_DATA__DATA__SHIFT 0x00000000 + +// SC_DEBUG_0 +#define SC_DEBUG_0__pa_freeze_b1__SHIFT 0x00000000 +#define SC_DEBUG_0__pa_sc_valid__SHIFT 0x00000001 +#define SC_DEBUG_0__pa_sc_phase__SHIFT 0x00000002 +#define SC_DEBUG_0__cntx_cnt__SHIFT 0x00000005 +#define SC_DEBUG_0__decr_cntx_cnt__SHIFT 0x0000000c +#define SC_DEBUG_0__incr_cntx_cnt__SHIFT 0x0000000d +#define SC_DEBUG_0__trigger__SHIFT 0x0000001f + +// SC_DEBUG_1 +#define SC_DEBUG_1__em_state__SHIFT 0x00000000 +#define SC_DEBUG_1__em1_data_ready__SHIFT 0x00000003 +#define SC_DEBUG_1__em2_data_ready__SHIFT 0x00000004 +#define SC_DEBUG_1__move_em1_to_em2__SHIFT 0x00000005 +#define SC_DEBUG_1__ef_data_ready__SHIFT 0x00000006 +#define SC_DEBUG_1__ef_state__SHIFT 0x00000007 +#define SC_DEBUG_1__pipe_valid__SHIFT 0x00000009 +#define SC_DEBUG_1__trigger__SHIFT 0x0000001f + +// SC_DEBUG_2 +#define SC_DEBUG_2__rc_rtr_dly__SHIFT 0x00000000 +#define SC_DEBUG_2__qmask_ff_alm_full_d1__SHIFT 0x00000001 +#define SC_DEBUG_2__pipe_freeze_b__SHIFT 0x00000003 +#define SC_DEBUG_2__prim_rts__SHIFT 0x00000004 +#define SC_DEBUG_2__next_prim_rts_dly__SHIFT 0x00000005 +#define SC_DEBUG_2__next_prim_rtr_dly__SHIFT 0x00000006 +#define SC_DEBUG_2__pre_stage1_rts_d1__SHIFT 0x00000007 +#define SC_DEBUG_2__stage0_rts__SHIFT 0x00000008 +#define SC_DEBUG_2__phase_rts_dly__SHIFT 0x00000009 +#define SC_DEBUG_2__end_of_prim_s1_dly__SHIFT 0x0000000f +#define SC_DEBUG_2__pass_empty_prim_s1__SHIFT 0x00000010 +#define SC_DEBUG_2__event_id_s1__SHIFT 0x00000011 +#define SC_DEBUG_2__event_s1__SHIFT 0x00000016 +#define SC_DEBUG_2__trigger__SHIFT 0x0000001f + +// SC_DEBUG_3 +#define SC_DEBUG_3__x_curr_s1__SHIFT 0x00000000 +#define SC_DEBUG_3__y_curr_s1__SHIFT 0x0000000b +#define SC_DEBUG_3__trigger__SHIFT 0x0000001f + +// SC_DEBUG_4 +#define SC_DEBUG_4__y_end_s1__SHIFT 0x00000000 +#define SC_DEBUG_4__y_start_s1__SHIFT 0x0000000e +#define SC_DEBUG_4__y_dir_s1__SHIFT 0x0000001c +#define SC_DEBUG_4__trigger__SHIFT 0x0000001f + +// SC_DEBUG_5 +#define SC_DEBUG_5__x_end_s1__SHIFT 0x00000000 +#define SC_DEBUG_5__x_start_s1__SHIFT 0x0000000e +#define SC_DEBUG_5__x_dir_s1__SHIFT 0x0000001c +#define SC_DEBUG_5__trigger__SHIFT 0x0000001f + +// SC_DEBUG_6 +#define SC_DEBUG_6__z_ff_empty__SHIFT 0x00000000 +#define SC_DEBUG_6__qmcntl_ff_empty__SHIFT 0x00000001 +#define SC_DEBUG_6__xy_ff_empty__SHIFT 0x00000002 +#define SC_DEBUG_6__event_flag__SHIFT 0x00000003 +#define SC_DEBUG_6__z_mask_needed__SHIFT 0x00000004 +#define SC_DEBUG_6__state__SHIFT 0x00000005 +#define SC_DEBUG_6__state_delayed__SHIFT 0x00000008 +#define SC_DEBUG_6__data_valid__SHIFT 0x0000000b +#define SC_DEBUG_6__data_valid_d__SHIFT 0x0000000c +#define SC_DEBUG_6__tilex_delayed__SHIFT 0x0000000d +#define SC_DEBUG_6__tiley_delayed__SHIFT 0x00000016 +#define SC_DEBUG_6__trigger__SHIFT 0x0000001f + +// SC_DEBUG_7 +#define SC_DEBUG_7__event_flag__SHIFT 0x00000000 +#define SC_DEBUG_7__deallocate__SHIFT 0x00000001 +#define SC_DEBUG_7__fpos__SHIFT 0x00000004 +#define SC_DEBUG_7__sr_prim_we__SHIFT 0x00000005 +#define SC_DEBUG_7__last_tile__SHIFT 0x00000006 +#define SC_DEBUG_7__tile_ff_we__SHIFT 0x00000007 +#define SC_DEBUG_7__qs_data_valid__SHIFT 0x00000008 +#define SC_DEBUG_7__qs_q0_y__SHIFT 0x00000009 +#define SC_DEBUG_7__qs_q0_x__SHIFT 0x0000000b +#define SC_DEBUG_7__qs_q0_valid__SHIFT 0x0000000d +#define SC_DEBUG_7__prim_ff_we__SHIFT 0x0000000e +#define SC_DEBUG_7__tile_ff_re__SHIFT 0x0000000f +#define SC_DEBUG_7__fw_prim_data_valid__SHIFT 0x00000010 +#define SC_DEBUG_7__last_quad_of_tile__SHIFT 0x00000011 +#define SC_DEBUG_7__first_quad_of_tile__SHIFT 0x00000012 +#define SC_DEBUG_7__first_quad_of_prim__SHIFT 0x00000013 +#define SC_DEBUG_7__new_prim__SHIFT 0x00000014 +#define SC_DEBUG_7__load_new_tile_data__SHIFT 0x00000015 +#define SC_DEBUG_7__state__SHIFT 0x00000016 +#define SC_DEBUG_7__fifos_ready__SHIFT 0x00000018 +#define SC_DEBUG_7__trigger__SHIFT 0x0000001f + +// SC_DEBUG_8 +#define SC_DEBUG_8__sample_last__SHIFT 0x00000000 +#define SC_DEBUG_8__sample_mask__SHIFT 0x00000001 +#define SC_DEBUG_8__sample_y__SHIFT 0x00000005 +#define SC_DEBUG_8__sample_x__SHIFT 0x00000007 +#define SC_DEBUG_8__sample_send__SHIFT 0x00000009 +#define SC_DEBUG_8__next_cycle__SHIFT 0x0000000a +#define SC_DEBUG_8__ez_sample_ff_full__SHIFT 0x0000000c +#define SC_DEBUG_8__rb_sc_samp_rtr__SHIFT 0x0000000d +#define SC_DEBUG_8__num_samples__SHIFT 0x0000000e +#define SC_DEBUG_8__last_quad_of_tile__SHIFT 0x00000010 +#define SC_DEBUG_8__last_quad_of_prim__SHIFT 0x00000011 +#define SC_DEBUG_8__first_quad_of_prim__SHIFT 0x00000012 +#define SC_DEBUG_8__sample_we__SHIFT 0x00000013 +#define SC_DEBUG_8__fpos__SHIFT 0x00000014 +#define SC_DEBUG_8__event_id__SHIFT 0x00000015 +#define SC_DEBUG_8__event_flag__SHIFT 0x0000001a +#define SC_DEBUG_8__fw_prim_data_valid__SHIFT 0x0000001b +#define SC_DEBUG_8__trigger__SHIFT 0x0000001f + +// SC_DEBUG_9 +#define SC_DEBUG_9__rb_sc_send__SHIFT 0x00000000 +#define SC_DEBUG_9__rb_sc_ez_mask__SHIFT 0x00000001 +#define SC_DEBUG_9__fifo_data_ready__SHIFT 0x00000005 +#define SC_DEBUG_9__early_z_enable__SHIFT 0x00000006 +#define SC_DEBUG_9__mask_state__SHIFT 0x00000007 +#define SC_DEBUG_9__next_ez_mask__SHIFT 0x00000009 +#define SC_DEBUG_9__mask_ready__SHIFT 0x00000019 +#define SC_DEBUG_9__drop_sample__SHIFT 0x0000001a +#define SC_DEBUG_9__fetch_new_sample_data__SHIFT 0x0000001b +#define SC_DEBUG_9__fetch_new_ez_sample_mask__SHIFT 0x0000001c +#define SC_DEBUG_9__pkr_fetch_new_sample_data__SHIFT 0x0000001d +#define SC_DEBUG_9__pkr_fetch_new_prim_data__SHIFT 0x0000001e +#define SC_DEBUG_9__trigger__SHIFT 0x0000001f + +// SC_DEBUG_10 +#define SC_DEBUG_10__combined_sample_mask__SHIFT 0x00000000 +#define SC_DEBUG_10__trigger__SHIFT 0x0000001f + +// SC_DEBUG_11 +#define SC_DEBUG_11__ez_sample_data_ready__SHIFT 0x00000000 +#define SC_DEBUG_11__pkr_fetch_new_sample_data__SHIFT 0x00000001 +#define SC_DEBUG_11__ez_prim_data_ready__SHIFT 0x00000002 +#define SC_DEBUG_11__pkr_fetch_new_prim_data__SHIFT 0x00000003 +#define SC_DEBUG_11__iterator_input_fz__SHIFT 0x00000004 +#define SC_DEBUG_11__packer_send_quads__SHIFT 0x00000005 +#define SC_DEBUG_11__packer_send_cmd__SHIFT 0x00000006 +#define SC_DEBUG_11__packer_send_event__SHIFT 0x00000007 +#define SC_DEBUG_11__next_state__SHIFT 0x00000008 +#define SC_DEBUG_11__state__SHIFT 0x0000000b +#define SC_DEBUG_11__stall__SHIFT 0x0000000e +#define SC_DEBUG_11__trigger__SHIFT 0x0000001f + +// SC_DEBUG_12 +#define SC_DEBUG_12__SQ_iterator_free_buff__SHIFT 0x00000000 +#define SC_DEBUG_12__event_id__SHIFT 0x00000001 +#define SC_DEBUG_12__event_flag__SHIFT 0x00000006 +#define SC_DEBUG_12__itercmdfifo_busy_nc_dly__SHIFT 0x00000007 +#define SC_DEBUG_12__itercmdfifo_full__SHIFT 0x00000008 +#define SC_DEBUG_12__itercmdfifo_empty__SHIFT 0x00000009 +#define SC_DEBUG_12__iter_ds_one_clk_command__SHIFT 0x0000000a +#define SC_DEBUG_12__iter_ds_end_of_prim0__SHIFT 0x0000000b +#define SC_DEBUG_12__iter_ds_end_of_vector__SHIFT 0x0000000c +#define SC_DEBUG_12__iter_qdhit0__SHIFT 0x0000000d +#define SC_DEBUG_12__bc_use_centers_reg__SHIFT 0x0000000e +#define SC_DEBUG_12__bc_output_xy_reg__SHIFT 0x0000000f +#define SC_DEBUG_12__iter_phase_out__SHIFT 0x00000010 +#define SC_DEBUG_12__iter_phase_reg__SHIFT 0x00000012 +#define SC_DEBUG_12__iterator_SP_valid__SHIFT 0x00000014 +#define SC_DEBUG_12__eopv_reg__SHIFT 0x00000015 +#define SC_DEBUG_12__one_clk_cmd_reg__SHIFT 0x00000016 +#define SC_DEBUG_12__iter_dx_end_of_prim__SHIFT 0x00000017 +#define SC_DEBUG_12__trigger__SHIFT 0x0000001f + +// GFX_COPY_STATE +#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x00000000 + +// VGT_DRAW_INITIATOR +#define VGT_DRAW_INITIATOR__PRIM_TYPE__SHIFT 0x00000000 +#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x00000006 +#define VGT_DRAW_INITIATOR__INDEX_SIZE__SHIFT 0x0000000b +#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x0000000c +#define VGT_DRAW_INITIATOR__SMALL_INDEX__SHIFT 0x0000000d +#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE__SHIFT 0x0000000e +#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE__SHIFT 0x0000000f +#define VGT_DRAW_INITIATOR__NUM_INDICES__SHIFT 0x00000010 + +// VGT_EVENT_INITIATOR +#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x00000000 + +// VGT_DMA_BASE +#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x00000000 + +// VGT_DMA_SIZE +#define VGT_DMA_SIZE__NUM_WORDS__SHIFT 0x00000000 +#define VGT_DMA_SIZE__SWAP_MODE__SHIFT 0x0000001e + +// VGT_BIN_BASE +#define VGT_BIN_BASE__BIN_BASE_ADDR__SHIFT 0x00000000 + +// VGT_BIN_SIZE +#define VGT_BIN_SIZE__NUM_WORDS__SHIFT 0x00000000 + +// VGT_CURRENT_BIN_ID_MIN +#define VGT_CURRENT_BIN_ID_MIN__COLUMN__SHIFT 0x00000000 +#define VGT_CURRENT_BIN_ID_MIN__ROW__SHIFT 0x00000003 +#define VGT_CURRENT_BIN_ID_MIN__GUARD_BAND__SHIFT 0x00000006 + +// VGT_CURRENT_BIN_ID_MAX +#define VGT_CURRENT_BIN_ID_MAX__COLUMN__SHIFT 0x00000000 +#define VGT_CURRENT_BIN_ID_MAX__ROW__SHIFT 0x00000003 +#define VGT_CURRENT_BIN_ID_MAX__GUARD_BAND__SHIFT 0x00000006 + +// VGT_IMMED_DATA +#define VGT_IMMED_DATA__DATA__SHIFT 0x00000000 + +// VGT_MAX_VTX_INDX +#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x00000000 + +// VGT_MIN_VTX_INDX +#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x00000000 + +// VGT_INDX_OFFSET +#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x00000000 + +// VGT_VERTEX_REUSE_BLOCK_CNTL +#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x00000000 + +// VGT_OUT_DEALLOC_CNTL +#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x00000000 + +// VGT_MULTI_PRIM_IB_RESET_INDX +#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x00000000 + +// VGT_ENHANCE +#define VGT_ENHANCE__MISC__SHIFT 0x00000000 + +// VGT_VTX_VECT_EJECT_REG +#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x00000000 + +// VGT_LAST_COPY_STATE +#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x00000000 +#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x00000010 + +// VGT_DEBUG_CNTL +#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX__SHIFT 0x00000000 + +// VGT_DEBUG_DATA +#define VGT_DEBUG_DATA__DATA__SHIFT 0x00000000 + +// VGT_CNTL_STATUS +#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x00000000 +#define VGT_CNTL_STATUS__VGT_DMA_BUSY__SHIFT 0x00000001 +#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY__SHIFT 0x00000002 +#define VGT_CNTL_STATUS__VGT_GRP_BUSY__SHIFT 0x00000003 +#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x00000004 +#define VGT_CNTL_STATUS__VGT_BIN_BUSY__SHIFT 0x00000005 +#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x00000006 +#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x00000007 +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x00000008 + +// VGT_DEBUG_REG0 +#define VGT_DEBUG_REG0__te_grp_busy__SHIFT 0x00000000 +#define VGT_DEBUG_REG0__pt_grp_busy__SHIFT 0x00000001 +#define VGT_DEBUG_REG0__vr_grp_busy__SHIFT 0x00000002 +#define VGT_DEBUG_REG0__dma_request_busy__SHIFT 0x00000003 +#define VGT_DEBUG_REG0__out_busy__SHIFT 0x00000004 +#define VGT_DEBUG_REG0__grp_backend_busy__SHIFT 0x00000005 +#define VGT_DEBUG_REG0__grp_busy__SHIFT 0x00000006 +#define VGT_DEBUG_REG0__dma_busy__SHIFT 0x00000007 +#define VGT_DEBUG_REG0__rbiu_dma_request_busy__SHIFT 0x00000008 +#define VGT_DEBUG_REG0__rbiu_busy__SHIFT 0x00000009 +#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended__SHIFT 0x0000000a +#define VGT_DEBUG_REG0__vgt_no_dma_busy__SHIFT 0x0000000b +#define VGT_DEBUG_REG0__vgt_busy_extended__SHIFT 0x0000000c +#define VGT_DEBUG_REG0__vgt_busy__SHIFT 0x0000000d +#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out__SHIFT 0x0000000e +#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy__SHIFT 0x0000000f +#define VGT_DEBUG_REG0__VGT_RBBM_busy__SHIFT 0x00000010 + +// VGT_DEBUG_REG1 +#define VGT_DEBUG_REG1__out_te_data_read__SHIFT 0x00000000 +#define VGT_DEBUG_REG1__te_out_data_valid__SHIFT 0x00000001 +#define VGT_DEBUG_REG1__out_pt_prim_read__SHIFT 0x00000002 +#define VGT_DEBUG_REG1__pt_out_prim_valid__SHIFT 0x00000003 +#define VGT_DEBUG_REG1__out_pt_data_read__SHIFT 0x00000004 +#define VGT_DEBUG_REG1__pt_out_indx_valid__SHIFT 0x00000005 +#define VGT_DEBUG_REG1__out_vr_prim_read__SHIFT 0x00000006 +#define VGT_DEBUG_REG1__vr_out_prim_valid__SHIFT 0x00000007 +#define VGT_DEBUG_REG1__out_vr_indx_read__SHIFT 0x00000008 +#define VGT_DEBUG_REG1__vr_out_indx_valid__SHIFT 0x00000009 +#define VGT_DEBUG_REG1__te_grp_read__SHIFT 0x0000000a +#define VGT_DEBUG_REG1__grp_te_valid__SHIFT 0x0000000b +#define VGT_DEBUG_REG1__pt_grp_read__SHIFT 0x0000000c +#define VGT_DEBUG_REG1__grp_pt_valid__SHIFT 0x0000000d +#define VGT_DEBUG_REG1__vr_grp_read__SHIFT 0x0000000e +#define VGT_DEBUG_REG1__grp_vr_valid__SHIFT 0x0000000f +#define VGT_DEBUG_REG1__grp_dma_read__SHIFT 0x00000010 +#define VGT_DEBUG_REG1__dma_grp_valid__SHIFT 0x00000011 +#define VGT_DEBUG_REG1__grp_rbiu_di_read__SHIFT 0x00000012 +#define VGT_DEBUG_REG1__rbiu_grp_di_valid__SHIFT 0x00000013 +#define VGT_DEBUG_REG1__MH_VGT_rtr__SHIFT 0x00000014 +#define VGT_DEBUG_REG1__VGT_MH_send__SHIFT 0x00000015 +#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr__SHIFT 0x00000016 +#define VGT_DEBUG_REG1__VGT_PA_clip_s_send__SHIFT 0x00000017 +#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr__SHIFT 0x00000018 +#define VGT_DEBUG_REG1__VGT_PA_clip_p_send__SHIFT 0x00000019 +#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr__SHIFT 0x0000001a +#define VGT_DEBUG_REG1__VGT_PA_clip_v_send__SHIFT 0x0000001b +#define VGT_DEBUG_REG1__SQ_VGT_rtr__SHIFT 0x0000001c +#define VGT_DEBUG_REG1__VGT_SQ_send__SHIFT 0x0000001d +#define VGT_DEBUG_REG1__mh_vgt_tag_7_q__SHIFT 0x0000001e + +// VGT_DEBUG_REG3 +#define VGT_DEBUG_REG3__vgt_clk_en__SHIFT 0x00000000 +#define VGT_DEBUG_REG3__reg_fifos_clk_en__SHIFT 0x00000001 + +// VGT_DEBUG_REG6 +#define VGT_DEBUG_REG6__shifter_byte_count_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG6__right_word_indx_q__SHIFT 0x00000005 +#define VGT_DEBUG_REG6__input_data_valid__SHIFT 0x0000000a +#define VGT_DEBUG_REG6__input_data_xfer__SHIFT 0x0000000b +#define VGT_DEBUG_REG6__next_shift_is_vect_1_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG6__next_shift_is_vect_1_d__SHIFT 0x0000000d +#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d__SHIFT 0x0000000e +#define VGT_DEBUG_REG6__space_avail_from_shift__SHIFT 0x0000000f +#define VGT_DEBUG_REG6__shifter_first_load__SHIFT 0x00000010 +#define VGT_DEBUG_REG6__di_state_sel_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q__SHIFT 0x00000012 +#define VGT_DEBUG_REG6__di_first_group_flag_q__SHIFT 0x00000013 +#define VGT_DEBUG_REG6__di_event_flag_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG6__read_draw_initiator__SHIFT 0x00000015 +#define VGT_DEBUG_REG6__loading_di_requires_shifter__SHIFT 0x00000016 +#define VGT_DEBUG_REG6__last_shift_of_packet__SHIFT 0x00000017 +#define VGT_DEBUG_REG6__last_decr_of_packet__SHIFT 0x00000018 +#define VGT_DEBUG_REG6__extract_vector__SHIFT 0x00000019 +#define VGT_DEBUG_REG6__shift_vect_rtr__SHIFT 0x0000001a +#define VGT_DEBUG_REG6__destination_rtr__SHIFT 0x0000001b +#define VGT_DEBUG_REG6__grp_trigger__SHIFT 0x0000001c + +// VGT_DEBUG_REG7 +#define VGT_DEBUG_REG7__di_index_counter_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG7__shift_amount_no_extract__SHIFT 0x00000010 +#define VGT_DEBUG_REG7__shift_amount_extract__SHIFT 0x00000014 +#define VGT_DEBUG_REG7__di_prim_type_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG7__current_source_sel__SHIFT 0x0000001e + +// VGT_DEBUG_REG8 +#define VGT_DEBUG_REG8__current_source_sel__SHIFT 0x00000000 +#define VGT_DEBUG_REG8__left_word_indx_q__SHIFT 0x00000002 +#define VGT_DEBUG_REG8__input_data_cnt__SHIFT 0x00000007 +#define VGT_DEBUG_REG8__input_data_lsw__SHIFT 0x0000000c +#define VGT_DEBUG_REG8__input_data_msw__SHIFT 0x00000011 +#define VGT_DEBUG_REG8__next_small_stride_shift_limit_q__SHIFT 0x00000016 +#define VGT_DEBUG_REG8__current_small_stride_shift_limit_q__SHIFT 0x0000001b + +// VGT_DEBUG_REG9 +#define VGT_DEBUG_REG9__next_stride_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG9__next_stride_d__SHIFT 0x00000005 +#define VGT_DEBUG_REG9__current_shift_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG9__current_shift_d__SHIFT 0x0000000f +#define VGT_DEBUG_REG9__current_stride_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG9__current_stride_d__SHIFT 0x00000019 +#define VGT_DEBUG_REG9__grp_trigger__SHIFT 0x0000001e + +// VGT_DEBUG_REG10 +#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0__SHIFT 0x00000000 +#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0__SHIFT 0x00000001 +#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0__SHIFT 0x00000002 +#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0__SHIFT 0x00000003 +#define VGT_DEBUG_REG10__di_state_sel_q__SHIFT 0x00000004 +#define VGT_DEBUG_REG10__last_decr_of_packet__SHIFT 0x00000005 +#define VGT_DEBUG_REG10__bin_valid__SHIFT 0x00000006 +#define VGT_DEBUG_REG10__read_block__SHIFT 0x00000007 +#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read__SHIFT 0x00000008 +#define VGT_DEBUG_REG10__last_bit_enable_q__SHIFT 0x00000009 +#define VGT_DEBUG_REG10__last_bit_end_di_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG10__selected_data__SHIFT 0x0000000b +#define VGT_DEBUG_REG10__mask_input_data__SHIFT 0x00000013 +#define VGT_DEBUG_REG10__gap_q__SHIFT 0x0000001b +#define VGT_DEBUG_REG10__temp_mini_reset_z__SHIFT 0x0000001c +#define VGT_DEBUG_REG10__temp_mini_reset_y__SHIFT 0x0000001d +#define VGT_DEBUG_REG10__temp_mini_reset_x__SHIFT 0x0000001e +#define VGT_DEBUG_REG10__grp_trigger__SHIFT 0x0000001f + +// VGT_DEBUG_REG12 +#define VGT_DEBUG_REG12__shifter_byte_count_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG12__right_word_indx_q__SHIFT 0x00000005 +#define VGT_DEBUG_REG12__input_data_valid__SHIFT 0x0000000a +#define VGT_DEBUG_REG12__input_data_xfer__SHIFT 0x0000000b +#define VGT_DEBUG_REG12__next_shift_is_vect_1_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG12__next_shift_is_vect_1_d__SHIFT 0x0000000d +#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d__SHIFT 0x0000000e +#define VGT_DEBUG_REG12__space_avail_from_shift__SHIFT 0x0000000f +#define VGT_DEBUG_REG12__shifter_first_load__SHIFT 0x00000010 +#define VGT_DEBUG_REG12__di_state_sel_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q__SHIFT 0x00000012 +#define VGT_DEBUG_REG12__di_first_group_flag_q__SHIFT 0x00000013 +#define VGT_DEBUG_REG12__di_event_flag_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG12__read_draw_initiator__SHIFT 0x00000015 +#define VGT_DEBUG_REG12__loading_di_requires_shifter__SHIFT 0x00000016 +#define VGT_DEBUG_REG12__last_shift_of_packet__SHIFT 0x00000017 +#define VGT_DEBUG_REG12__last_decr_of_packet__SHIFT 0x00000018 +#define VGT_DEBUG_REG12__extract_vector__SHIFT 0x00000019 +#define VGT_DEBUG_REG12__shift_vect_rtr__SHIFT 0x0000001a +#define VGT_DEBUG_REG12__destination_rtr__SHIFT 0x0000001b +#define VGT_DEBUG_REG12__bgrp_trigger__SHIFT 0x0000001c + +// VGT_DEBUG_REG13 +#define VGT_DEBUG_REG13__di_index_counter_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG13__shift_amount_no_extract__SHIFT 0x00000010 +#define VGT_DEBUG_REG13__shift_amount_extract__SHIFT 0x00000014 +#define VGT_DEBUG_REG13__di_prim_type_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG13__current_source_sel__SHIFT 0x0000001e + +// VGT_DEBUG_REG14 +#define VGT_DEBUG_REG14__current_source_sel__SHIFT 0x00000000 +#define VGT_DEBUG_REG14__left_word_indx_q__SHIFT 0x00000002 +#define VGT_DEBUG_REG14__input_data_cnt__SHIFT 0x00000007 +#define VGT_DEBUG_REG14__input_data_lsw__SHIFT 0x0000000c +#define VGT_DEBUG_REG14__input_data_msw__SHIFT 0x00000011 +#define VGT_DEBUG_REG14__next_small_stride_shift_limit_q__SHIFT 0x00000016 +#define VGT_DEBUG_REG14__current_small_stride_shift_limit_q__SHIFT 0x0000001b + +// VGT_DEBUG_REG15 +#define VGT_DEBUG_REG15__next_stride_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG15__next_stride_d__SHIFT 0x00000005 +#define VGT_DEBUG_REG15__current_shift_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG15__current_shift_d__SHIFT 0x0000000f +#define VGT_DEBUG_REG15__current_stride_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG15__current_stride_d__SHIFT 0x00000019 +#define VGT_DEBUG_REG15__bgrp_trigger__SHIFT 0x0000001e + +// VGT_DEBUG_REG16 +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full__SHIFT 0x00000000 +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty__SHIFT 0x00000001 +#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read__SHIFT 0x00000002 +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we__SHIFT 0x00000003 +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full__SHIFT 0x00000004 +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty__SHIFT 0x00000005 +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q__SHIFT 0x00000006 +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we__SHIFT 0x00000007 +#define VGT_DEBUG_REG16__bgrp_dma_mask_kill__SHIFT 0x00000008 +#define VGT_DEBUG_REG16__bgrp_grp_bin_valid__SHIFT 0x00000009 +#define VGT_DEBUG_REG16__rst_last_bit__SHIFT 0x0000000a +#define VGT_DEBUG_REG16__current_state_q__SHIFT 0x0000000b +#define VGT_DEBUG_REG16__old_state_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG16__old_state_en__SHIFT 0x0000000d +#define VGT_DEBUG_REG16__prev_last_bit_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG16__dbl_last_bit_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG16__last_bit_block_q__SHIFT 0x00000010 +#define VGT_DEBUG_REG16__ast_bit_block2_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG16__load_empty_reg__SHIFT 0x00000012 +#define VGT_DEBUG_REG16__bgrp_grp_byte_mask_rdata__SHIFT 0x00000013 +#define VGT_DEBUG_REG16__dma_bgrp_dma_data_fifo_rptr__SHIFT 0x0000001b +#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable__SHIFT 0x0000001d +#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q__SHIFT 0x0000001e +#define VGT_DEBUG_REG16__bgrp_trigger__SHIFT 0x0000001f + +// VGT_DEBUG_REG17 +#define VGT_DEBUG_REG17__save_read_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG17__extend_read_q__SHIFT 0x00000001 +#define VGT_DEBUG_REG17__grp_indx_size__SHIFT 0x00000002 +#define VGT_DEBUG_REG17__cull_prim_true__SHIFT 0x00000004 +#define VGT_DEBUG_REG17__reset_bit2_q__SHIFT 0x00000005 +#define VGT_DEBUG_REG17__reset_bit1_q__SHIFT 0x00000006 +#define VGT_DEBUG_REG17__first_reg_first_q__SHIFT 0x00000007 +#define VGT_DEBUG_REG17__check_second_reg__SHIFT 0x00000008 +#define VGT_DEBUG_REG17__check_first_reg__SHIFT 0x00000009 +#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata__SHIFT 0x0000000a +#define VGT_DEBUG_REG17__save_cull_fetch_data2_q__SHIFT 0x0000000b +#define VGT_DEBUG_REG17__save_cull_fetch_data1_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG17__save_byte_mask_data2_q__SHIFT 0x0000000d +#define VGT_DEBUG_REG17__save_byte_mask_data1_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG17__to_second_reg_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG17__roll_over_msk_q__SHIFT 0x00000010 +#define VGT_DEBUG_REG17__max_msk_ptr_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG17__min_msk_ptr_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG17__bgrp_trigger__SHIFT 0x0000001f + +// VGT_DEBUG_REG18 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_raddr__SHIFT 0x00000000 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_waddr__SHIFT 0x00000006 +#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re__SHIFT 0x0000000c +#define VGT_DEBUG_REG18__dma_bgrp_dma_data_fifo_rptr__SHIFT 0x0000000d +#define VGT_DEBUG_REG18__dma_mem_full__SHIFT 0x0000000f +#define VGT_DEBUG_REG18__dma_ram_re__SHIFT 0x00000010 +#define VGT_DEBUG_REG18__dma_ram_we__SHIFT 0x00000011 +#define VGT_DEBUG_REG18__dma_mem_empty__SHIFT 0x00000012 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_re__SHIFT 0x00000013 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_we__SHIFT 0x00000014 +#define VGT_DEBUG_REG18__bin_mem_full__SHIFT 0x00000015 +#define VGT_DEBUG_REG18__bin_ram_we__SHIFT 0x00000016 +#define VGT_DEBUG_REG18__bin_ram_re__SHIFT 0x00000017 +#define VGT_DEBUG_REG18__bin_mem_empty__SHIFT 0x00000018 +#define VGT_DEBUG_REG18__start_bin_req__SHIFT 0x00000019 +#define VGT_DEBUG_REG18__fetch_cull_not_used__SHIFT 0x0000001a +#define VGT_DEBUG_REG18__dma_req_xfer__SHIFT 0x0000001b +#define VGT_DEBUG_REG18__have_valid_bin_req__SHIFT 0x0000001c +#define VGT_DEBUG_REG18__have_valid_dma_req__SHIFT 0x0000001d +#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable__SHIFT 0x0000001e +#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable__SHIFT 0x0000001f + +// VGT_DEBUG_REG20 +#define VGT_DEBUG_REG20__prim_side_indx_valid__SHIFT 0x00000000 +#define VGT_DEBUG_REG20__indx_side_fifo_empty__SHIFT 0x00000001 +#define VGT_DEBUG_REG20__indx_side_fifo_re__SHIFT 0x00000002 +#define VGT_DEBUG_REG20__indx_side_fifo_we__SHIFT 0x00000003 +#define VGT_DEBUG_REG20__indx_side_fifo_full__SHIFT 0x00000004 +#define VGT_DEBUG_REG20__prim_buffer_empty__SHIFT 0x00000005 +#define VGT_DEBUG_REG20__prim_buffer_re__SHIFT 0x00000006 +#define VGT_DEBUG_REG20__prim_buffer_we__SHIFT 0x00000007 +#define VGT_DEBUG_REG20__prim_buffer_full__SHIFT 0x00000008 +#define VGT_DEBUG_REG20__indx_buffer_empty__SHIFT 0x00000009 +#define VGT_DEBUG_REG20__indx_buffer_re__SHIFT 0x0000000a +#define VGT_DEBUG_REG20__indx_buffer_we__SHIFT 0x0000000b +#define VGT_DEBUG_REG20__indx_buffer_full__SHIFT 0x0000000c +#define VGT_DEBUG_REG20__hold_prim__SHIFT 0x0000000d +#define VGT_DEBUG_REG20__sent_cnt__SHIFT 0x0000000e +#define VGT_DEBUG_REG20__start_of_vtx_vector__SHIFT 0x00000012 +#define VGT_DEBUG_REG20__clip_s_pre_hold_prim__SHIFT 0x00000013 +#define VGT_DEBUG_REG20__clip_p_pre_hold_prim__SHIFT 0x00000014 +#define VGT_DEBUG_REG20__buffered_prim_type_event__SHIFT 0x00000015 +#define VGT_DEBUG_REG20__out_trigger__SHIFT 0x0000001a + +// VGT_DEBUG_REG21 +#define VGT_DEBUG_REG21__null_terminate_vtx_vector__SHIFT 0x00000000 +#define VGT_DEBUG_REG21__prim_end_of_vtx_vect_flags__SHIFT 0x00000001 +#define VGT_DEBUG_REG21__alloc_counter_q__SHIFT 0x00000004 +#define VGT_DEBUG_REG21__curr_slot_in_vtx_vect_q__SHIFT 0x00000007 +#define VGT_DEBUG_REG21__int_vtx_counter_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG21__curr_dealloc_distance_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG21__new_packet_q__SHIFT 0x00000012 +#define VGT_DEBUG_REG21__new_allocate_q__SHIFT 0x00000013 +#define VGT_DEBUG_REG21__num_new_unique_rel_indx__SHIFT 0x00000014 +#define VGT_DEBUG_REG21__inserted_null_prim_q__SHIFT 0x00000016 +#define VGT_DEBUG_REG21__insert_null_prim__SHIFT 0x00000017 +#define VGT_DEBUG_REG21__buffered_prim_eop_mux__SHIFT 0x00000018 +#define VGT_DEBUG_REG21__prim_buffer_empty_mux__SHIFT 0x00000019 +#define VGT_DEBUG_REG21__buffered_thread_size__SHIFT 0x0000001a +#define VGT_DEBUG_REG21__out_trigger__SHIFT 0x0000001f + +// VGT_CRC_SQ_DATA +#define VGT_CRC_SQ_DATA__CRC__SHIFT 0x00000000 + +// VGT_CRC_SQ_CTRL +#define VGT_CRC_SQ_CTRL__CRC__SHIFT 0x00000000 + +// VGT_PERFCOUNTER0_SELECT +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// VGT_PERFCOUNTER1_SELECT +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 + +// VGT_PERFCOUNTER2_SELECT +#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 + +// VGT_PERFCOUNTER3_SELECT +#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 + +// VGT_PERFCOUNTER0_LOW +#define VGT_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER1_LOW +#define VGT_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER2_LOW +#define VGT_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER3_LOW +#define VGT_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER0_HI +#define VGT_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER1_HI +#define VGT_PERFCOUNTER1_HI__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER2_HI +#define VGT_PERFCOUNTER2_HI__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER3_HI +#define VGT_PERFCOUNTER3_HI__PERF_COUNT__SHIFT 0x00000000 + +// TC_CNTL_STATUS +#define TC_CNTL_STATUS__L2_INVALIDATE__SHIFT 0x00000000 +#define TC_CNTL_STATUS__TC_L2_HIT_MISS__SHIFT 0x00000012 +#define TC_CNTL_STATUS__TC_BUSY__SHIFT 0x0000001f + +// TCR_CHICKEN +#define TCR_CHICKEN__SPARE__SHIFT 0x00000000 + +// TCF_CHICKEN +#define TCF_CHICKEN__SPARE__SHIFT 0x00000000 + +// TCM_CHICKEN +#define TCM_CHICKEN__TCO_READ_LATENCY_FIFO_PROG_DEPTH__SHIFT 0x00000000 +#define TCM_CHICKEN__ETC_COLOR_ENDIAN__SHIFT 0x00000008 +#define TCM_CHICKEN__SPARE__SHIFT 0x00000009 + +// TCR_PERFCOUNTER0_SELECT +#define TCR_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCR_PERFCOUNTER1_SELECT +#define TCR_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCR_PERFCOUNTER0_HI +#define TCR_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCR_PERFCOUNTER1_HI +#define TCR_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCR_PERFCOUNTER0_LOW +#define TCR_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCR_PERFCOUNTER1_LOW +#define TCR_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TP_TC_CLKGATE_CNTL +#define TP_TC_CLKGATE_CNTL__TP_BUSY_EXTEND__SHIFT 0x00000000 +#define TP_TC_CLKGATE_CNTL__TC_BUSY_EXTEND__SHIFT 0x00000003 + +// TPC_CNTL_STATUS +#define TPC_CNTL_STATUS__TPC_INPUT_BUSY__SHIFT 0x00000000 +#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY__SHIFT 0x00000001 +#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY__SHIFT 0x00000002 +#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY__SHIFT 0x00000003 +#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY__SHIFT 0x00000004 +#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY__SHIFT 0x00000005 +#define TPC_CNTL_STATUS__TPC_WALKER_BUSY__SHIFT 0x00000006 +#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY__SHIFT 0x00000008 +#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY__SHIFT 0x00000009 +#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY__SHIFT 0x0000000a +#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY__SHIFT 0x0000000c +#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY__SHIFT 0x0000000d +#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY__SHIFT 0x0000000e +#define TPC_CNTL_STATUS__TPC_BLEND_BUSY__SHIFT 0x0000000f +#define TPC_CNTL_STATUS__TF_TW_RTS__SHIFT 0x00000010 +#define TPC_CNTL_STATUS__TF_TW_STATE_RTS__SHIFT 0x00000011 +#define TPC_CNTL_STATUS__TF_TW_RTR__SHIFT 0x00000013 +#define TPC_CNTL_STATUS__TW_TA_RTS__SHIFT 0x00000014 +#define TPC_CNTL_STATUS__TW_TA_TT_RTS__SHIFT 0x00000015 +#define TPC_CNTL_STATUS__TW_TA_LAST_RTS__SHIFT 0x00000016 +#define TPC_CNTL_STATUS__TW_TA_RTR__SHIFT 0x00000017 +#define TPC_CNTL_STATUS__TA_TB_RTS__SHIFT 0x00000018 +#define TPC_CNTL_STATUS__TA_TB_TT_RTS__SHIFT 0x00000019 +#define TPC_CNTL_STATUS__TA_TB_RTR__SHIFT 0x0000001b +#define TPC_CNTL_STATUS__TA_TF_RTS__SHIFT 0x0000001c +#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN__SHIFT 0x0000001d +#define TPC_CNTL_STATUS__TP_SQ_DEC__SHIFT 0x0000001e +#define TPC_CNTL_STATUS__TPC_BUSY__SHIFT 0x0000001f + +// TPC_DEBUG0 +#define TPC_DEBUG0__LOD_CNTL__SHIFT 0x00000000 +#define TPC_DEBUG0__IC_CTR__SHIFT 0x00000002 +#define TPC_DEBUG0__WALKER_CNTL__SHIFT 0x00000004 +#define TPC_DEBUG0__ALIGNER_CNTL__SHIFT 0x00000008 +#define TPC_DEBUG0__PREV_TC_STATE_VALID__SHIFT 0x0000000c +#define TPC_DEBUG0__WALKER_STATE__SHIFT 0x00000010 +#define TPC_DEBUG0__ALIGNER_STATE__SHIFT 0x0000001a +#define TPC_DEBUG0__REG_CLK_EN__SHIFT 0x0000001d +#define TPC_DEBUG0__TPC_CLK_EN__SHIFT 0x0000001e +#define TPC_DEBUG0__SQ_TP_WAKEUP__SHIFT 0x0000001f + +// TPC_DEBUG1 +#define TPC_DEBUG1__UNUSED__SHIFT 0x00000000 + +// TPC_CHICKEN +#define TPC_CHICKEN__BLEND_PRECISION__SHIFT 0x00000000 +#define TPC_CHICKEN__SPARE__SHIFT 0x00000001 + +// TP0_CNTL_STATUS +#define TP0_CNTL_STATUS__TP_INPUT_BUSY__SHIFT 0x00000000 +#define TP0_CNTL_STATUS__TP_LOD_BUSY__SHIFT 0x00000001 +#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY__SHIFT 0x00000002 +#define TP0_CNTL_STATUS__TP_ADDR_BUSY__SHIFT 0x00000003 +#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY__SHIFT 0x00000004 +#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY__SHIFT 0x00000005 +#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY__SHIFT 0x00000006 +#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY__SHIFT 0x00000007 +#define TP0_CNTL_STATUS__TP_FETCH_BUSY__SHIFT 0x00000008 +#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY__SHIFT 0x00000009 +#define TP0_CNTL_STATUS__TP_TT_BUSY__SHIFT 0x0000000a +#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY__SHIFT 0x0000000b +#define TP0_CNTL_STATUS__TP_BLEND_BUSY__SHIFT 0x0000000c +#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY__SHIFT 0x0000000d +#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY__SHIFT 0x0000000e +#define TP0_CNTL_STATUS__IN_LC_RTS__SHIFT 0x00000010 +#define TP0_CNTL_STATUS__LC_LA_RTS__SHIFT 0x00000011 +#define TP0_CNTL_STATUS__LA_FL_RTS__SHIFT 0x00000012 +#define TP0_CNTL_STATUS__FL_TA_RTS__SHIFT 0x00000013 +#define TP0_CNTL_STATUS__TA_FA_RTS__SHIFT 0x00000014 +#define TP0_CNTL_STATUS__TA_FA_TT_RTS__SHIFT 0x00000015 +#define TP0_CNTL_STATUS__FA_AL_RTS__SHIFT 0x00000016 +#define TP0_CNTL_STATUS__FA_AL_TT_RTS__SHIFT 0x00000017 +#define TP0_CNTL_STATUS__AL_TF_RTS__SHIFT 0x00000018 +#define TP0_CNTL_STATUS__AL_TF_TT_RTS__SHIFT 0x00000019 +#define TP0_CNTL_STATUS__TF_TB_RTS__SHIFT 0x0000001a +#define TP0_CNTL_STATUS__TF_TB_TT_RTS__SHIFT 0x0000001b +#define TP0_CNTL_STATUS__TB_TT_RTS__SHIFT 0x0000001c +#define TP0_CNTL_STATUS__TB_TT_TT_RESET__SHIFT 0x0000001d +#define TP0_CNTL_STATUS__TB_TO_RTS__SHIFT 0x0000001e +#define TP0_CNTL_STATUS__TP_BUSY__SHIFT 0x0000001f + +// TP0_DEBUG +#define TP0_DEBUG__Q_LOD_CNTL__SHIFT 0x00000000 +#define TP0_DEBUG__Q_SQ_TP_WAKEUP__SHIFT 0x00000003 +#define TP0_DEBUG__FL_TA_ADDRESSER_CNTL__SHIFT 0x00000004 +#define TP0_DEBUG__REG_CLK_EN__SHIFT 0x00000015 +#define TP0_DEBUG__PERF_CLK_EN__SHIFT 0x00000016 +#define TP0_DEBUG__TP_CLK_EN__SHIFT 0x00000017 +#define TP0_DEBUG__Q_WALKER_CNTL__SHIFT 0x00000018 +#define TP0_DEBUG__Q_ALIGNER_CNTL__SHIFT 0x0000001c + +// TP0_CHICKEN +#define TP0_CHICKEN__TT_MODE__SHIFT 0x00000000 +#define TP0_CHICKEN__VFETCH_ADDRESS_MODE__SHIFT 0x00000001 +#define TP0_CHICKEN__SPARE__SHIFT 0x00000002 + +// TP0_PERFCOUNTER0_SELECT +#define TP0_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TP0_PERFCOUNTER0_HI +#define TP0_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TP0_PERFCOUNTER0_LOW +#define TP0_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TP0_PERFCOUNTER1_SELECT +#define TP0_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TP0_PERFCOUNTER1_HI +#define TP0_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TP0_PERFCOUNTER1_LOW +#define TP0_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCM_PERFCOUNTER0_SELECT +#define TCM_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCM_PERFCOUNTER1_SELECT +#define TCM_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCM_PERFCOUNTER0_HI +#define TCM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCM_PERFCOUNTER1_HI +#define TCM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCM_PERFCOUNTER0_LOW +#define TCM_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCM_PERFCOUNTER1_LOW +#define TCM_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER0_SELECT +#define TCF_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER1_SELECT +#define TCF_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER2_SELECT +#define TCF_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER3_SELECT +#define TCF_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER4_SELECT +#define TCF_PERFCOUNTER4_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER5_SELECT +#define TCF_PERFCOUNTER5_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER6_SELECT +#define TCF_PERFCOUNTER6_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER7_SELECT +#define TCF_PERFCOUNTER7_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER8_SELECT +#define TCF_PERFCOUNTER8_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER9_SELECT +#define TCF_PERFCOUNTER9_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER10_SELECT +#define TCF_PERFCOUNTER10_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER11_SELECT +#define TCF_PERFCOUNTER11_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER0_HI +#define TCF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER1_HI +#define TCF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER2_HI +#define TCF_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER3_HI +#define TCF_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER4_HI +#define TCF_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER5_HI +#define TCF_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER6_HI +#define TCF_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER7_HI +#define TCF_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER8_HI +#define TCF_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER9_HI +#define TCF_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER10_HI +#define TCF_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER11_HI +#define TCF_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER0_LOW +#define TCF_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER1_LOW +#define TCF_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER2_LOW +#define TCF_PERFCOUNTER2_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER3_LOW +#define TCF_PERFCOUNTER3_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER4_LOW +#define TCF_PERFCOUNTER4_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER5_LOW +#define TCF_PERFCOUNTER5_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER6_LOW +#define TCF_PERFCOUNTER6_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER7_LOW +#define TCF_PERFCOUNTER7_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER8_LOW +#define TCF_PERFCOUNTER8_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER9_LOW +#define TCF_PERFCOUNTER9_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER10_LOW +#define TCF_PERFCOUNTER10_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER11_LOW +#define TCF_PERFCOUNTER11_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_DEBUG +#define TCF_DEBUG__not_MH_TC_rtr__SHIFT 0x00000006 +#define TCF_DEBUG__TC_MH_send__SHIFT 0x00000007 +#define TCF_DEBUG__not_FG0_rtr__SHIFT 0x00000008 +#define TCF_DEBUG__not_TCB_TCO_rtr__SHIFT 0x0000000c +#define TCF_DEBUG__TCB_ff_stall__SHIFT 0x0000000d +#define TCF_DEBUG__TCB_miss_stall__SHIFT 0x0000000e +#define TCF_DEBUG__TCA_TCB_stall__SHIFT 0x0000000f +#define TCF_DEBUG__PF0_stall__SHIFT 0x00000010 +#define TCF_DEBUG__TP0_full__SHIFT 0x00000014 +#define TCF_DEBUG__TPC_full__SHIFT 0x00000018 +#define TCF_DEBUG__not_TPC_rtr__SHIFT 0x00000019 +#define TCF_DEBUG__tca_state_rts__SHIFT 0x0000001a +#define TCF_DEBUG__tca_rts__SHIFT 0x0000001b + +// TCA_FIFO_DEBUG +#define TCA_FIFO_DEBUG__tp0_full__SHIFT 0x00000000 +#define TCA_FIFO_DEBUG__tpc_full__SHIFT 0x00000004 +#define TCA_FIFO_DEBUG__load_tpc_fifo__SHIFT 0x00000005 +#define TCA_FIFO_DEBUG__load_tp_fifos__SHIFT 0x00000006 +#define TCA_FIFO_DEBUG__FW_full__SHIFT 0x00000007 +#define TCA_FIFO_DEBUG__not_FW_rtr0__SHIFT 0x00000008 +#define TCA_FIFO_DEBUG__FW_rts0__SHIFT 0x0000000c +#define TCA_FIFO_DEBUG__not_FW_tpc_rtr__SHIFT 0x00000010 +#define TCA_FIFO_DEBUG__FW_tpc_rts__SHIFT 0x00000011 + +// TCA_PROBE_DEBUG +#define TCA_PROBE_DEBUG__ProbeFilter_stall__SHIFT 0x00000000 + +// TCA_TPC_DEBUG +#define TCA_TPC_DEBUG__captue_state_rts__SHIFT 0x0000000c +#define TCA_TPC_DEBUG__capture_tca_rts__SHIFT 0x0000000d + +// TCB_CORE_DEBUG +#define TCB_CORE_DEBUG__access512__SHIFT 0x00000000 +#define TCB_CORE_DEBUG__tiled__SHIFT 0x00000001 +#define TCB_CORE_DEBUG__opcode__SHIFT 0x00000004 +#define TCB_CORE_DEBUG__format__SHIFT 0x00000008 +#define TCB_CORE_DEBUG__sector_format__SHIFT 0x00000010 +#define TCB_CORE_DEBUG__sector_format512__SHIFT 0x00000018 + +// TCB_TAG0_DEBUG +#define TCB_TAG0_DEBUG__mem_read_cycle__SHIFT 0x00000000 +#define TCB_TAG0_DEBUG__tag_access_cycle__SHIFT 0x0000000c +#define TCB_TAG0_DEBUG__miss_stall__SHIFT 0x00000017 +#define TCB_TAG0_DEBUG__num_feee_lines__SHIFT 0x00000018 +#define TCB_TAG0_DEBUG__max_misses__SHIFT 0x0000001d + +// TCB_TAG1_DEBUG +#define TCB_TAG1_DEBUG__mem_read_cycle__SHIFT 0x00000000 +#define TCB_TAG1_DEBUG__tag_access_cycle__SHIFT 0x0000000c +#define TCB_TAG1_DEBUG__miss_stall__SHIFT 0x00000017 +#define TCB_TAG1_DEBUG__num_feee_lines__SHIFT 0x00000018 +#define TCB_TAG1_DEBUG__max_misses__SHIFT 0x0000001d + +// TCB_TAG2_DEBUG +#define TCB_TAG2_DEBUG__mem_read_cycle__SHIFT 0x00000000 +#define TCB_TAG2_DEBUG__tag_access_cycle__SHIFT 0x0000000c +#define TCB_TAG2_DEBUG__miss_stall__SHIFT 0x00000017 +#define TCB_TAG2_DEBUG__num_feee_lines__SHIFT 0x00000018 +#define TCB_TAG2_DEBUG__max_misses__SHIFT 0x0000001d + +// TCB_TAG3_DEBUG +#define TCB_TAG3_DEBUG__mem_read_cycle__SHIFT 0x00000000 +#define TCB_TAG3_DEBUG__tag_access_cycle__SHIFT 0x0000000c +#define TCB_TAG3_DEBUG__miss_stall__SHIFT 0x00000017 +#define TCB_TAG3_DEBUG__num_feee_lines__SHIFT 0x00000018 +#define TCB_TAG3_DEBUG__max_misses__SHIFT 0x0000001d + +// TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done__SHIFT 0x00000000 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left__SHIFT 0x00000002 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q__SHIFT 0x00000004 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go__SHIFT 0x00000005 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left__SHIFT 0x00000006 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_count_q__SHIFT 0x00000007 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_q__SHIFT 0x0000000c +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q__SHIFT 0x0000001c + +// TCB_FETCH_GEN_WALKER_DEBUG +#define TCB_FETCH_GEN_WALKER_DEBUG__quad_sel_left__SHIFT 0x00000004 +#define TCB_FETCH_GEN_WALKER_DEBUG__set_sel_left__SHIFT 0x00000006 +#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left__SHIFT 0x0000000b +#define TCB_FETCH_GEN_WALKER_DEBUG__ff_fg_type512__SHIFT 0x0000000c +#define TCB_FETCH_GEN_WALKER_DEBUG__busy__SHIFT 0x0000000f +#define TCB_FETCH_GEN_WALKER_DEBUG__setquads_to_send__SHIFT 0x00000010 + +// TCB_FETCH_GEN_PIPE0_DEBUG +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts__SHIFT 0x00000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts__SHIFT 0x00000002 +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_format__SHIFT 0x00000004 +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_fmsopcode__SHIFT 0x00000010 +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_request_type__SHIFT 0x00000015 +#define TCB_FETCH_GEN_PIPE0_DEBUG__busy__SHIFT 0x00000017 +#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy__SHIFT 0x00000018 +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy__SHIFT 0x00000019 +#define TCB_FETCH_GEN_PIPE0_DEBUG__mc_sel_q__SHIFT 0x0000001a +#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q__SHIFT 0x0000001c +#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR__SHIFT 0x0000001e + +// TCD_INPUT0_DEBUG +#define TCD_INPUT0_DEBUG__empty__SHIFT 0x00000010 +#define TCD_INPUT0_DEBUG__full__SHIFT 0x00000011 +#define TCD_INPUT0_DEBUG__valid_q1__SHIFT 0x00000014 +#define TCD_INPUT0_DEBUG__cnt_q1__SHIFT 0x00000015 +#define TCD_INPUT0_DEBUG__last_send_q1__SHIFT 0x00000017 +#define TCD_INPUT0_DEBUG__ip_send__SHIFT 0x00000018 +#define TCD_INPUT0_DEBUG__ipbuf_dxt_send__SHIFT 0x00000019 +#define TCD_INPUT0_DEBUG__ipbuf_busy__SHIFT 0x0000001a + +// TCD_DEGAMMA_DEBUG +#define TCD_DEGAMMA_DEBUG__dgmm_ftfconv_dgmmen__SHIFT 0x00000000 +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8__SHIFT 0x00000002 +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send__SHIFT 0x00000003 +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send__SHIFT 0x00000004 +#define TCD_DEGAMMA_DEBUG__dgmm_stall__SHIFT 0x00000005 +#define TCD_DEGAMMA_DEBUG__dgmm_pstate__SHIFT 0x00000006 + +// TCD_DXTMUX_SCTARB_DEBUG +#define TCD_DXTMUX_SCTARB_DEBUG__pstate__SHIFT 0x00000009 +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr__SHIFT 0x0000000a +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr__SHIFT 0x0000000b +#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send__SHIFT 0x0000000f +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts__SHIFT 0x00000010 +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send__SHIFT 0x00000014 +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send__SHIFT 0x0000001b +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send__SHIFT 0x0000001c +#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send__SHIFT 0x0000001d + +// TCD_DXTC_ARB_DEBUG +#define TCD_DXTC_ARB_DEBUG__n0_stall__SHIFT 0x00000004 +#define TCD_DXTC_ARB_DEBUG__pstate__SHIFT 0x00000005 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send__SHIFT 0x00000006 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cnt__SHIFT 0x00000007 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_sector__SHIFT 0x00000009 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cacheline__SHIFT 0x0000000c +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_format__SHIFT 0x00000012 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send__SHIFT 0x0000001e +#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types__SHIFT 0x0000001f + +// TCD_STALLS_DEBUG +#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr__SHIFT 0x0000000a +#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr__SHIFT 0x0000000b +#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr__SHIFT 0x00000011 +#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr__SHIFT 0x00000012 +#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr__SHIFT 0x00000013 +#define TCD_STALLS_DEBUG__not_incoming_rtr__SHIFT 0x0000001f + +// TCO_STALLS_DEBUG +#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR__SHIFT 0x00000005 +#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR__SHIFT 0x00000006 +#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d__SHIFT 0x00000007 + +// TCO_QUAD0_DEBUG0 +#define TCO_QUAD0_DEBUG0__rl_sg_sector_format__SHIFT 0x00000000 +#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample__SHIFT 0x00000008 +#define TCO_QUAD0_DEBUG0__rl_sg_rtr__SHIFT 0x00000009 +#define TCO_QUAD0_DEBUG0__rl_sg_rts__SHIFT 0x0000000a +#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample__SHIFT 0x0000000b +#define TCO_QUAD0_DEBUG0__sg_crd_rtr__SHIFT 0x0000000c +#define TCO_QUAD0_DEBUG0__sg_crd_rts__SHIFT 0x0000000d +#define TCO_QUAD0_DEBUG0__stageN1_valid_q__SHIFT 0x00000010 +#define TCO_QUAD0_DEBUG0__read_cache_q__SHIFT 0x00000018 +#define TCO_QUAD0_DEBUG0__cache_read_RTR__SHIFT 0x00000019 +#define TCO_QUAD0_DEBUG0__all_sectors_written_set3__SHIFT 0x0000001a +#define TCO_QUAD0_DEBUG0__all_sectors_written_set2__SHIFT 0x0000001b +#define TCO_QUAD0_DEBUG0__all_sectors_written_set1__SHIFT 0x0000001c +#define TCO_QUAD0_DEBUG0__all_sectors_written_set0__SHIFT 0x0000001d +#define TCO_QUAD0_DEBUG0__busy__SHIFT 0x0000001e + +// TCO_QUAD0_DEBUG1 +#define TCO_QUAD0_DEBUG1__fifo_busy__SHIFT 0x00000000 +#define TCO_QUAD0_DEBUG1__empty__SHIFT 0x00000001 +#define TCO_QUAD0_DEBUG1__full__SHIFT 0x00000002 +#define TCO_QUAD0_DEBUG1__write_enable__SHIFT 0x00000003 +#define TCO_QUAD0_DEBUG1__fifo_write_ptr__SHIFT 0x00000004 +#define TCO_QUAD0_DEBUG1__fifo_read_ptr__SHIFT 0x0000000b +#define TCO_QUAD0_DEBUG1__cache_read_busy__SHIFT 0x00000014 +#define TCO_QUAD0_DEBUG1__latency_fifo_busy__SHIFT 0x00000015 +#define TCO_QUAD0_DEBUG1__input_quad_busy__SHIFT 0x00000016 +#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy__SHIFT 0x00000017 +#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d__SHIFT 0x00000018 +#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q__SHIFT 0x00000019 +#define TCO_QUAD0_DEBUG1__rl_sg_rtr__SHIFT 0x0000001a +#define TCO_QUAD0_DEBUG1__rl_sg_rts__SHIFT 0x0000001b +#define TCO_QUAD0_DEBUG1__sg_crd_rtr__SHIFT 0x0000001c +#define TCO_QUAD0_DEBUG1__sg_crd_rts__SHIFT 0x0000001d +#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc__SHIFT 0x0000001e + +// SQ_GPR_MANAGEMENT +#define SQ_GPR_MANAGEMENT__REG_DYNAMIC__SHIFT 0x00000000 +#define SQ_GPR_MANAGEMENT__REG_SIZE_PIX__SHIFT 0x00000004 +#define SQ_GPR_MANAGEMENT__REG_SIZE_VTX__SHIFT 0x0000000c + +// SQ_FLOW_CONTROL +#define SQ_FLOW_CONTROL__INPUT_ARBITRATION_POLICY__SHIFT 0x00000000 +#define SQ_FLOW_CONTROL__ONE_THREAD__SHIFT 0x00000004 +#define SQ_FLOW_CONTROL__ONE_ALU__SHIFT 0x00000008 +#define SQ_FLOW_CONTROL__CF_WR_BASE__SHIFT 0x0000000c +#define SQ_FLOW_CONTROL__NO_PV_PS__SHIFT 0x00000010 +#define SQ_FLOW_CONTROL__NO_LOOP_EXIT__SHIFT 0x00000011 +#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE__SHIFT 0x00000012 +#define SQ_FLOW_CONTROL__TEXTURE_ARBITRATION_POLICY__SHIFT 0x00000013 +#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY__SHIFT 0x00000015 +#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY__SHIFT 0x00000016 +#define SQ_FLOW_CONTROL__NO_ARB_EJECT__SHIFT 0x00000017 +#define SQ_FLOW_CONTROL__NO_CFS_EJECT__SHIFT 0x00000018 +#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY__SHIFT 0x00000019 +#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION__SHIFT 0x0000001a +#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC__SHIFT 0x0000001b + +// SQ_INST_STORE_MANAGMENT +#define SQ_INST_STORE_MANAGMENT__INST_BASE_PIX__SHIFT 0x00000000 +#define SQ_INST_STORE_MANAGMENT__INST_BASE_VTX__SHIFT 0x00000010 + +// SQ_RESOURCE_MANAGMENT +#define SQ_RESOURCE_MANAGMENT__VTX_THREAD_BUF_ENTRIES__SHIFT 0x00000000 +#define SQ_RESOURCE_MANAGMENT__PIX_THREAD_BUF_ENTRIES__SHIFT 0x00000008 +#define SQ_RESOURCE_MANAGMENT__EXPORT_BUF_ENTRIES__SHIFT 0x00000010 + +// SQ_EO_RT +#define SQ_EO_RT__EO_CONSTANTS_RT__SHIFT 0x00000000 +#define SQ_EO_RT__EO_TSTATE_RT__SHIFT 0x00000010 + +// SQ_DEBUG_MISC +#define SQ_DEBUG_MISC__DB_ALUCST_SIZE__SHIFT 0x00000000 +#define SQ_DEBUG_MISC__DB_TSTATE_SIZE__SHIFT 0x0000000c +#define SQ_DEBUG_MISC__DB_READ_CTX__SHIFT 0x00000014 +#define SQ_DEBUG_MISC__RESERVED__SHIFT 0x00000015 +#define SQ_DEBUG_MISC__DB_READ_MEMORY__SHIFT 0x00000017 +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0__SHIFT 0x00000019 +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1__SHIFT 0x0000001a +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2__SHIFT 0x0000001b +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3__SHIFT 0x0000001c + +// SQ_ACTIVITY_METER_CNTL +#define SQ_ACTIVITY_METER_CNTL__TIMEBASE__SHIFT 0x00000000 +#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_LOW__SHIFT 0x00000008 +#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_HIGH__SHIFT 0x00000010 +#define SQ_ACTIVITY_METER_CNTL__SPARE__SHIFT 0x00000018 + +// SQ_ACTIVITY_METER_STATUS +#define SQ_ACTIVITY_METER_STATUS__PERCENT_BUSY__SHIFT 0x00000000 + +// SQ_INPUT_ARB_PRIORITY +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_WEIGHT__SHIFT 0x00000000 +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN__SHIFT 0x00000003 +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_WEIGHT__SHIFT 0x00000004 +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN__SHIFT 0x00000007 +#define SQ_INPUT_ARB_PRIORITY__THRESHOLD__SHIFT 0x00000008 + +// SQ_THREAD_ARB_PRIORITY +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_WEIGHT__SHIFT 0x00000000 +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN__SHIFT 0x00000003 +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_WEIGHT__SHIFT 0x00000004 +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN__SHIFT 0x00000007 +#define SQ_THREAD_ARB_PRIORITY__THRESHOLD__SHIFT 0x00000008 +#define SQ_THREAD_ARB_PRIORITY__RESERVED__SHIFT 0x00000012 +#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL__SHIFT 0x00000014 +#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL__SHIFT 0x00000015 +#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD__SHIFT 0x00000016 + +// SQ_DEBUG_INPUT_FSM +#define SQ_DEBUG_INPUT_FSM__VC_VSR_LD__SHIFT 0x00000000 +#define SQ_DEBUG_INPUT_FSM__RESERVED__SHIFT 0x00000003 +#define SQ_DEBUG_INPUT_FSM__VC_GPR_LD__SHIFT 0x00000004 +#define SQ_DEBUG_INPUT_FSM__PC_PISM__SHIFT 0x00000008 +#define SQ_DEBUG_INPUT_FSM__RESERVED1__SHIFT 0x0000000b +#define SQ_DEBUG_INPUT_FSM__PC_AS__SHIFT 0x0000000c +#define SQ_DEBUG_INPUT_FSM__PC_INTERP_CNT__SHIFT 0x0000000f +#define SQ_DEBUG_INPUT_FSM__PC_GPR_SIZE__SHIFT 0x00000014 + +// SQ_DEBUG_CONST_MGR_FSM +#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_EVENT_STATE__SHIFT 0x00000000 +#define SQ_DEBUG_CONST_MGR_FSM__RESERVED1__SHIFT 0x00000005 +#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_EVENT_STATE__SHIFT 0x00000008 +#define SQ_DEBUG_CONST_MGR_FSM__RESERVED2__SHIFT 0x0000000d +#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_CNTX_VALID__SHIFT 0x00000010 +#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_CNTX_VALID__SHIFT 0x00000012 +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE__SHIFT 0x00000014 +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE__SHIFT 0x00000015 +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE__SHIFT 0x00000016 +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE__SHIFT 0x00000017 + +// SQ_DEBUG_TP_FSM +#define SQ_DEBUG_TP_FSM__EX_TP__SHIFT 0x00000000 +#define SQ_DEBUG_TP_FSM__RESERVED0__SHIFT 0x00000003 +#define SQ_DEBUG_TP_FSM__CF_TP__SHIFT 0x00000004 +#define SQ_DEBUG_TP_FSM__IF_TP__SHIFT 0x00000008 +#define SQ_DEBUG_TP_FSM__RESERVED1__SHIFT 0x0000000b +#define SQ_DEBUG_TP_FSM__TIS_TP__SHIFT 0x0000000c +#define SQ_DEBUG_TP_FSM__RESERVED2__SHIFT 0x0000000e +#define SQ_DEBUG_TP_FSM__GS_TP__SHIFT 0x00000010 +#define SQ_DEBUG_TP_FSM__RESERVED3__SHIFT 0x00000012 +#define SQ_DEBUG_TP_FSM__FCR_TP__SHIFT 0x00000014 +#define SQ_DEBUG_TP_FSM__RESERVED4__SHIFT 0x00000016 +#define SQ_DEBUG_TP_FSM__FCS_TP__SHIFT 0x00000018 +#define SQ_DEBUG_TP_FSM__RESERVED5__SHIFT 0x0000001a +#define SQ_DEBUG_TP_FSM__ARB_TR_TP__SHIFT 0x0000001c + +// SQ_DEBUG_FSM_ALU_0 +#define SQ_DEBUG_FSM_ALU_0__EX_ALU_0__SHIFT 0x00000000 +#define SQ_DEBUG_FSM_ALU_0__RESERVED0__SHIFT 0x00000003 +#define SQ_DEBUG_FSM_ALU_0__CF_ALU_0__SHIFT 0x00000004 +#define SQ_DEBUG_FSM_ALU_0__IF_ALU_0__SHIFT 0x00000008 +#define SQ_DEBUG_FSM_ALU_0__RESERVED1__SHIFT 0x0000000b +#define SQ_DEBUG_FSM_ALU_0__DU1_ALU_0__SHIFT 0x0000000c +#define SQ_DEBUG_FSM_ALU_0__RESERVED2__SHIFT 0x0000000f +#define SQ_DEBUG_FSM_ALU_0__DU0_ALU_0__SHIFT 0x00000010 +#define SQ_DEBUG_FSM_ALU_0__RESERVED3__SHIFT 0x00000013 +#define SQ_DEBUG_FSM_ALU_0__AIS_ALU_0__SHIFT 0x00000014 +#define SQ_DEBUG_FSM_ALU_0__RESERVED4__SHIFT 0x00000017 +#define SQ_DEBUG_FSM_ALU_0__ACS_ALU_0__SHIFT 0x00000018 +#define SQ_DEBUG_FSM_ALU_0__RESERVED5__SHIFT 0x0000001b +#define SQ_DEBUG_FSM_ALU_0__ARB_TR_ALU__SHIFT 0x0000001c + +// SQ_DEBUG_FSM_ALU_1 +#define SQ_DEBUG_FSM_ALU_1__EX_ALU_0__SHIFT 0x00000000 +#define SQ_DEBUG_FSM_ALU_1__RESERVED0__SHIFT 0x00000003 +#define SQ_DEBUG_FSM_ALU_1__CF_ALU_0__SHIFT 0x00000004 +#define SQ_DEBUG_FSM_ALU_1__IF_ALU_0__SHIFT 0x00000008 +#define SQ_DEBUG_FSM_ALU_1__RESERVED1__SHIFT 0x0000000b +#define SQ_DEBUG_FSM_ALU_1__DU1_ALU_0__SHIFT 0x0000000c +#define SQ_DEBUG_FSM_ALU_1__RESERVED2__SHIFT 0x0000000f +#define SQ_DEBUG_FSM_ALU_1__DU0_ALU_0__SHIFT 0x00000010 +#define SQ_DEBUG_FSM_ALU_1__RESERVED3__SHIFT 0x00000013 +#define SQ_DEBUG_FSM_ALU_1__AIS_ALU_0__SHIFT 0x00000014 +#define SQ_DEBUG_FSM_ALU_1__RESERVED4__SHIFT 0x00000017 +#define SQ_DEBUG_FSM_ALU_1__ACS_ALU_0__SHIFT 0x00000018 +#define SQ_DEBUG_FSM_ALU_1__RESERVED5__SHIFT 0x0000001b +#define SQ_DEBUG_FSM_ALU_1__ARB_TR_ALU__SHIFT 0x0000001c + +// SQ_DEBUG_EXP_ALLOC +#define SQ_DEBUG_EXP_ALLOC__POS_BUF_AVAIL__SHIFT 0x00000000 +#define SQ_DEBUG_EXP_ALLOC__COLOR_BUF_AVAIL__SHIFT 0x00000004 +#define SQ_DEBUG_EXP_ALLOC__EA_BUF_AVAIL__SHIFT 0x0000000c +#define SQ_DEBUG_EXP_ALLOC__RESERVED__SHIFT 0x0000000f +#define SQ_DEBUG_EXP_ALLOC__ALLOC_TBL_BUF_AVAIL__SHIFT 0x00000010 + +// SQ_DEBUG_PTR_BUFF +#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER__SHIFT 0x00000000 +#define SQ_DEBUG_PTR_BUFF__DEALLOC_CNT__SHIFT 0x00000001 +#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR__SHIFT 0x00000005 +#define SQ_DEBUG_PTR_BUFF__EVENT_CONTEXT_ID__SHIFT 0x00000006 +#define SQ_DEBUG_PTR_BUFF__SC_EVENT_ID__SHIFT 0x00000009 +#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT__SHIFT 0x0000000e +#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON__SHIFT 0x0000000f +#define SQ_DEBUG_PTR_BUFF__EF_EMPTY__SHIFT 0x00000010 +#define SQ_DEBUG_PTR_BUFF__VTX_SYNC_CNT__SHIFT 0x00000011 + +// SQ_DEBUG_GPR_VTX +#define SQ_DEBUG_GPR_VTX__VTX_TAIL_PTR__SHIFT 0x00000000 +#define SQ_DEBUG_GPR_VTX__RESERVED__SHIFT 0x00000007 +#define SQ_DEBUG_GPR_VTX__VTX_HEAD_PTR__SHIFT 0x00000008 +#define SQ_DEBUG_GPR_VTX__RESERVED1__SHIFT 0x0000000f +#define SQ_DEBUG_GPR_VTX__VTX_MAX__SHIFT 0x00000010 +#define SQ_DEBUG_GPR_VTX__RESERVED2__SHIFT 0x00000017 +#define SQ_DEBUG_GPR_VTX__VTX_FREE__SHIFT 0x00000018 + +// SQ_DEBUG_GPR_PIX +#define SQ_DEBUG_GPR_PIX__PIX_TAIL_PTR__SHIFT 0x00000000 +#define SQ_DEBUG_GPR_PIX__RESERVED__SHIFT 0x00000007 +#define SQ_DEBUG_GPR_PIX__PIX_HEAD_PTR__SHIFT 0x00000008 +#define SQ_DEBUG_GPR_PIX__RESERVED1__SHIFT 0x0000000f +#define SQ_DEBUG_GPR_PIX__PIX_MAX__SHIFT 0x00000010 +#define SQ_DEBUG_GPR_PIX__RESERVED2__SHIFT 0x00000017 +#define SQ_DEBUG_GPR_PIX__PIX_FREE__SHIFT 0x00000018 + +// SQ_DEBUG_TB_STATUS_SEL +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATUS_REG_SEL__SHIFT 0x00000000 +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_DW_SEL__SHIFT 0x00000004 +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_ADDR__SHIFT 0x00000007 +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN__SHIFT 0x0000000b +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN__SHIFT 0x0000000c +#define SQ_DEBUG_TB_STATUS_SEL__DEBUG_BUS_TRIGGER_SEL__SHIFT 0x0000000e +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATUS_REG_SEL__SHIFT 0x00000010 +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_DW_SEL__SHIFT 0x00000014 +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_ADDR__SHIFT 0x00000017 +#define SQ_DEBUG_TB_STATUS_SEL__VC_THREAD_BUF_DLY__SHIFT 0x0000001d +#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC__SHIFT 0x0000001f + +// SQ_DEBUG_VTX_TB_0 +#define SQ_DEBUG_VTX_TB_0__VTX_HEAD_PTR_Q__SHIFT 0x00000000 +#define SQ_DEBUG_VTX_TB_0__TAIL_PTR_Q__SHIFT 0x00000004 +#define SQ_DEBUG_VTX_TB_0__FULL_CNT_Q__SHIFT 0x00000008 +#define SQ_DEBUG_VTX_TB_0__NXT_POS_ALLOC_CNT__SHIFT 0x0000000c +#define SQ_DEBUG_VTX_TB_0__NXT_PC_ALLOC_CNT__SHIFT 0x00000010 +#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL__SHIFT 0x00000014 +#define SQ_DEBUG_VTX_TB_0__BUSY_Q__SHIFT 0x00000015 + +// SQ_DEBUG_VTX_TB_1 +#define SQ_DEBUG_VTX_TB_1__VS_DONE_PTR__SHIFT 0x00000000 + +// SQ_DEBUG_VTX_TB_STATUS_REG +#define SQ_DEBUG_VTX_TB_STATUS_REG__VS_STATUS_REG__SHIFT 0x00000000 + +// SQ_DEBUG_VTX_TB_STATE_MEM +#define SQ_DEBUG_VTX_TB_STATE_MEM__VS_STATE_MEM__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_0 +#define SQ_DEBUG_PIX_TB_0__PIX_HEAD_PTR__SHIFT 0x00000000 +#define SQ_DEBUG_PIX_TB_0__TAIL_PTR__SHIFT 0x00000006 +#define SQ_DEBUG_PIX_TB_0__FULL_CNT__SHIFT 0x0000000c +#define SQ_DEBUG_PIX_TB_0__NXT_PIX_ALLOC_CNT__SHIFT 0x00000013 +#define SQ_DEBUG_PIX_TB_0__NXT_PIX_EXP_CNT__SHIFT 0x00000019 +#define SQ_DEBUG_PIX_TB_0__BUSY__SHIFT 0x0000001f + +// SQ_DEBUG_PIX_TB_STATUS_REG_0 +#define SQ_DEBUG_PIX_TB_STATUS_REG_0__PIX_TB_STATUS_REG_0__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_STATUS_REG_1 +#define SQ_DEBUG_PIX_TB_STATUS_REG_1__PIX_TB_STATUS_REG_1__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_STATUS_REG_2 +#define SQ_DEBUG_PIX_TB_STATUS_REG_2__PIX_TB_STATUS_REG_2__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_STATUS_REG_3 +#define SQ_DEBUG_PIX_TB_STATUS_REG_3__PIX_TB_STATUS_REG_3__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_STATE_MEM +#define SQ_DEBUG_PIX_TB_STATE_MEM__PIX_TB_STATE_MEM__SHIFT 0x00000000 + +// SQ_PERFCOUNTER0_SELECT +#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SQ_PERFCOUNTER1_SELECT +#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SQ_PERFCOUNTER2_SELECT +#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SQ_PERFCOUNTER3_SELECT +#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SQ_PERFCOUNTER0_LOW +#define SQ_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER0_HI +#define SQ_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER1_LOW +#define SQ_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER1_HI +#define SQ_PERFCOUNTER1_HI__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER2_LOW +#define SQ_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER2_HI +#define SQ_PERFCOUNTER2_HI__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER3_LOW +#define SQ_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER3_HI +#define SQ_PERFCOUNTER3_HI__PERF_COUNT__SHIFT 0x00000000 + +// SX_PERFCOUNTER0_SELECT +#define SX_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SX_PERFCOUNTER0_LOW +#define SX_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SX_PERFCOUNTER0_HI +#define SX_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// SQ_INSTRUCTION_ALU_0 +#define SQ_INSTRUCTION_ALU_0__VECTOR_RESULT__SHIFT 0x00000000 +#define SQ_INSTRUCTION_ALU_0__CST_0_ABS_MOD__SHIFT 0x00000006 +#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP__SHIFT 0x00000007 +#define SQ_INSTRUCTION_ALU_0__SCALAR_RESULT__SHIFT 0x00000008 +#define SQ_INSTRUCTION_ALU_0__SST_0_ABS_MOD__SHIFT 0x0000000e +#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA__SHIFT 0x0000000f +#define SQ_INSTRUCTION_ALU_0__VECTOR_WRT_MSK__SHIFT 0x00000010 +#define SQ_INSTRUCTION_ALU_0__SCALAR_WRT_MSK__SHIFT 0x00000014 +#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP__SHIFT 0x00000018 +#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP__SHIFT 0x00000019 +#define SQ_INSTRUCTION_ALU_0__SCALAR_OPCODE__SHIFT 0x0000001a + +// SQ_INSTRUCTION_ALU_1 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_R__SHIFT 0x00000000 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_G__SHIFT 0x00000002 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_B__SHIFT 0x00000004 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_A__SHIFT 0x00000006 +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_R__SHIFT 0x00000008 +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_G__SHIFT 0x0000000a +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_B__SHIFT 0x0000000c +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_A__SHIFT 0x0000000e +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_R__SHIFT 0x00000010 +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_G__SHIFT 0x00000012 +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_B__SHIFT 0x00000014 +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_A__SHIFT 0x00000016 +#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD__SHIFT 0x00000018 +#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD__SHIFT 0x00000019 +#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD__SHIFT 0x0000001a +#define SQ_INSTRUCTION_ALU_1__PRED_SELECT__SHIFT 0x0000001b +#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR__SHIFT 0x0000001d +#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS__SHIFT 0x0000001e +#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS__SHIFT 0x0000001f + +// SQ_INSTRUCTION_ALU_2 +#define SQ_INSTRUCTION_ALU_2__SRC_C_REG_PTR__SHIFT 0x00000000 +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C__SHIFT 0x00000006 +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C__SHIFT 0x00000007 +#define SQ_INSTRUCTION_ALU_2__SRC_B_REG_PTR__SHIFT 0x00000008 +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B__SHIFT 0x0000000e +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B__SHIFT 0x0000000f +#define SQ_INSTRUCTION_ALU_2__SRC_A_REG_PTR__SHIFT 0x00000010 +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A__SHIFT 0x00000016 +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A__SHIFT 0x00000017 +#define SQ_INSTRUCTION_ALU_2__VECTOR_OPCODE__SHIFT 0x00000018 +#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL__SHIFT 0x0000001d +#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL__SHIFT 0x0000001e +#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL__SHIFT 0x0000001f + +// SQ_INSTRUCTION_CF_EXEC_0 +#define SQ_INSTRUCTION_CF_EXEC_0__ADDRESS__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_EXEC_0__RESERVED__SHIFT 0x00000009 +#define SQ_INSTRUCTION_CF_EXEC_0__COUNT__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_EXEC_0__YIELD__SHIFT 0x0000000f +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0__SHIFT 0x00000011 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1__SHIFT 0x00000012 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1__SHIFT 0x00000013 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2__SHIFT 0x00000014 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2__SHIFT 0x00000015 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3__SHIFT 0x00000016 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3__SHIFT 0x00000017 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4__SHIFT 0x00000018 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4__SHIFT 0x00000019 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5__SHIFT 0x0000001a +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0__SHIFT 0x0000001c +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1__SHIFT 0x0000001d +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2__SHIFT 0x0000001e +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3__SHIFT 0x0000001f + +// SQ_INSTRUCTION_CF_EXEC_1 +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5__SHIFT 0x00000001 +#define SQ_INSTRUCTION_CF_EXEC_1__BOOL_ADDR__SHIFT 0x00000002 +#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_EXEC_1__OPCODE__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_EXEC_1__RESERVED__SHIFT 0x00000019 +#define SQ_INSTRUCTION_CF_EXEC_1__COUNT__SHIFT 0x0000001c +#define SQ_INSTRUCTION_CF_EXEC_1__YIELD__SHIFT 0x0000001f + +// SQ_INSTRUCTION_CF_EXEC_2 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0__SHIFT 0x00000001 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1__SHIFT 0x00000002 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1__SHIFT 0x00000003 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2__SHIFT 0x00000004 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2__SHIFT 0x00000005 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3__SHIFT 0x00000006 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3__SHIFT 0x00000007 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4__SHIFT 0x00000008 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4__SHIFT 0x00000009 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1__SHIFT 0x0000000d +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2__SHIFT 0x0000000e +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3__SHIFT 0x0000000f +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5__SHIFT 0x00000011 +#define SQ_INSTRUCTION_CF_EXEC_2__BOOL_ADDR__SHIFT 0x00000012 +#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION__SHIFT 0x0000001a +#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_EXEC_2__OPCODE__SHIFT 0x0000001c + +// SQ_INSTRUCTION_CF_LOOP_0 +#define SQ_INSTRUCTION_CF_LOOP_0__ADDRESS__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_0__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_LOOP_0__LOOP_ID__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_1__SHIFT 0x00000015 + +// SQ_INSTRUCTION_CF_LOOP_1 +#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_0__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_LOOP_1__OPCODE__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_1__SHIFT 0x0000001a + +// SQ_INSTRUCTION_CF_LOOP_2 +#define SQ_INSTRUCTION_CF_LOOP_2__LOOP_ID__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_LOOP_2__RESERVED__SHIFT 0x00000005 +#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_LOOP_2__OPCODE__SHIFT 0x0000001c + +// SQ_INSTRUCTION_CF_JMP_CALL_0 +#define SQ_INSTRUCTION_CF_JMP_CALL_0__ADDRESS__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_0__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL__SHIFT 0x0000000d +#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP__SHIFT 0x0000000e +#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_1__SHIFT 0x0000000f + +// SQ_INSTRUCTION_CF_JMP_CALL_1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION__SHIFT 0x00000001 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__BOOL_ADDR__SHIFT 0x00000002 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_JMP_CALL_1__OPCODE__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_1__SHIFT 0x0000001a +#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL__SHIFT 0x0000001d +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_2__SHIFT 0x0000001e + +// SQ_INSTRUCTION_CF_JMP_CALL_2 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__RESERVED__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION__SHIFT 0x00000011 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__BOOL_ADDR__SHIFT 0x00000012 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION__SHIFT 0x0000001a +#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_JMP_CALL_2__OPCODE__SHIFT 0x0000001c + +// SQ_INSTRUCTION_CF_ALLOC_0 +#define SQ_INSTRUCTION_CF_ALLOC_0__SIZE__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_ALLOC_0__RESERVED__SHIFT 0x00000004 + +// SQ_INSTRUCTION_CF_ALLOC_1 +#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_0__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL__SHIFT 0x00000008 +#define SQ_INSTRUCTION_CF_ALLOC_1__BUFFER_SELECT__SHIFT 0x00000009 +#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_ALLOC_1__OPCODE__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_ALLOC_1__SIZE__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_1__SHIFT 0x00000014 + +// SQ_INSTRUCTION_CF_ALLOC_2 +#define SQ_INSTRUCTION_CF_ALLOC_2__RESERVED__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL__SHIFT 0x00000018 +#define SQ_INSTRUCTION_CF_ALLOC_2__BUFFER_SELECT__SHIFT 0x00000019 +#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_ALLOC_2__OPCODE__SHIFT 0x0000001c + +// SQ_INSTRUCTION_TFETCH_0 +#define SQ_INSTRUCTION_TFETCH_0__OPCODE__SHIFT 0x00000000 +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR__SHIFT 0x00000005 +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM__SHIFT 0x0000000b +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR__SHIFT 0x0000000c +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM__SHIFT 0x00000012 +#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY__SHIFT 0x00000013 +#define SQ_INSTRUCTION_TFETCH_0__CONST_INDEX__SHIFT 0x00000014 +#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM__SHIFT 0x00000019 +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_X__SHIFT 0x0000001a +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Y__SHIFT 0x0000001c +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Z__SHIFT 0x0000001e + +// SQ_INSTRUCTION_TFETCH_1 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_X__SHIFT 0x00000000 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Y__SHIFT 0x00000003 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Z__SHIFT 0x00000006 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_W__SHIFT 0x00000009 +#define SQ_INSTRUCTION_TFETCH_1__MAG_FILTER__SHIFT 0x0000000c +#define SQ_INSTRUCTION_TFETCH_1__MIN_FILTER__SHIFT 0x0000000e +#define SQ_INSTRUCTION_TFETCH_1__MIP_FILTER__SHIFT 0x00000010 +#define SQ_INSTRUCTION_TFETCH_1__ANISO_FILTER__SHIFT 0x00000012 +#define SQ_INSTRUCTION_TFETCH_1__ARBITRARY_FILTER__SHIFT 0x00000015 +#define SQ_INSTRUCTION_TFETCH_1__VOL_MAG_FILTER__SHIFT 0x00000018 +#define SQ_INSTRUCTION_TFETCH_1__VOL_MIN_FILTER__SHIFT 0x0000001a +#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD__SHIFT 0x0000001c +#define SQ_INSTRUCTION_TFETCH_1__USE_REG_LOD__SHIFT 0x0000001d +#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT__SHIFT 0x0000001f + +// SQ_INSTRUCTION_TFETCH_2 +#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS__SHIFT 0x00000000 +#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION__SHIFT 0x00000001 +#define SQ_INSTRUCTION_TFETCH_2__LOD_BIAS__SHIFT 0x00000002 +#define SQ_INSTRUCTION_TFETCH_2__UNUSED__SHIFT 0x00000009 +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_X__SHIFT 0x00000010 +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Y__SHIFT 0x00000015 +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Z__SHIFT 0x0000001a +#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION__SHIFT 0x0000001f + +// SQ_INSTRUCTION_VFETCH_0 +#define SQ_INSTRUCTION_VFETCH_0__OPCODE__SHIFT 0x00000000 +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR__SHIFT 0x00000005 +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM__SHIFT 0x0000000b +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR__SHIFT 0x0000000c +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM__SHIFT 0x00000012 +#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE__SHIFT 0x00000013 +#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX__SHIFT 0x00000014 +#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_SEL__SHIFT 0x00000019 +#define SQ_INSTRUCTION_VFETCH_0__SRC_SEL__SHIFT 0x0000001e + +// SQ_INSTRUCTION_VFETCH_1 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_X__SHIFT 0x00000000 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Y__SHIFT 0x00000003 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Z__SHIFT 0x00000006 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_W__SHIFT 0x00000009 +#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL__SHIFT 0x0000000c +#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL__SHIFT 0x0000000d +#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL__SHIFT 0x0000000e +#define SQ_INSTRUCTION_VFETCH_1__DATA_FORMAT__SHIFT 0x00000010 +#define SQ_INSTRUCTION_VFETCH_1__EXP_ADJUST_ALL__SHIFT 0x00000017 +#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT__SHIFT 0x0000001f + +// SQ_INSTRUCTION_VFETCH_2 +#define SQ_INSTRUCTION_VFETCH_2__STRIDE__SHIFT 0x00000000 +#define SQ_INSTRUCTION_VFETCH_2__OFFSET__SHIFT 0x00000010 +#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION__SHIFT 0x0000001f + +// SQ_CONSTANT_0 +#define SQ_CONSTANT_0__RED__SHIFT 0x00000000 + +// SQ_CONSTANT_1 +#define SQ_CONSTANT_1__GREEN__SHIFT 0x00000000 + +// SQ_CONSTANT_2 +#define SQ_CONSTANT_2__BLUE__SHIFT 0x00000000 + +// SQ_CONSTANT_3 +#define SQ_CONSTANT_3__ALPHA__SHIFT 0x00000000 + +// SQ_FETCH_0 +#define SQ_FETCH_0__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_1 +#define SQ_FETCH_1__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_2 +#define SQ_FETCH_2__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_3 +#define SQ_FETCH_3__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_4 +#define SQ_FETCH_4__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_5 +#define SQ_FETCH_5__VALUE__SHIFT 0x00000000 + +// SQ_CONSTANT_VFETCH_0 +#define SQ_CONSTANT_VFETCH_0__TYPE__SHIFT 0x00000000 +#define SQ_CONSTANT_VFETCH_0__STATE__SHIFT 0x00000001 +#define SQ_CONSTANT_VFETCH_0__BASE_ADDRESS__SHIFT 0x00000002 + +// SQ_CONSTANT_VFETCH_1 +#define SQ_CONSTANT_VFETCH_1__ENDIAN_SWAP__SHIFT 0x00000000 +#define SQ_CONSTANT_VFETCH_1__LIMIT_ADDRESS__SHIFT 0x00000002 + +// SQ_CONSTANT_T2 +#define SQ_CONSTANT_T2__VALUE__SHIFT 0x00000000 + +// SQ_CONSTANT_T3 +#define SQ_CONSTANT_T3__VALUE__SHIFT 0x00000000 + +// SQ_CF_BOOLEANS +#define SQ_CF_BOOLEANS__CF_BOOLEANS_0__SHIFT 0x00000000 +#define SQ_CF_BOOLEANS__CF_BOOLEANS_1__SHIFT 0x00000008 +#define SQ_CF_BOOLEANS__CF_BOOLEANS_2__SHIFT 0x00000010 +#define SQ_CF_BOOLEANS__CF_BOOLEANS_3__SHIFT 0x00000018 + +// SQ_CF_LOOP +#define SQ_CF_LOOP__CF_LOOP_COUNT__SHIFT 0x00000000 +#define SQ_CF_LOOP__CF_LOOP_START__SHIFT 0x00000008 +#define SQ_CF_LOOP__CF_LOOP_STEP__SHIFT 0x00000010 + +// SQ_CONSTANT_RT_0 +#define SQ_CONSTANT_RT_0__RED__SHIFT 0x00000000 + +// SQ_CONSTANT_RT_1 +#define SQ_CONSTANT_RT_1__GREEN__SHIFT 0x00000000 + +// SQ_CONSTANT_RT_2 +#define SQ_CONSTANT_RT_2__BLUE__SHIFT 0x00000000 + +// SQ_CONSTANT_RT_3 +#define SQ_CONSTANT_RT_3__ALPHA__SHIFT 0x00000000 + +// SQ_FETCH_RT_0 +#define SQ_FETCH_RT_0__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_1 +#define SQ_FETCH_RT_1__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_2 +#define SQ_FETCH_RT_2__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_3 +#define SQ_FETCH_RT_3__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_4 +#define SQ_FETCH_RT_4__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_5 +#define SQ_FETCH_RT_5__VALUE__SHIFT 0x00000000 + +// SQ_CF_RT_BOOLEANS +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_0__SHIFT 0x00000000 +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_1__SHIFT 0x00000008 +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_2__SHIFT 0x00000010 +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_3__SHIFT 0x00000018 + +// SQ_CF_RT_LOOP +#define SQ_CF_RT_LOOP__CF_LOOP_COUNT__SHIFT 0x00000000 +#define SQ_CF_RT_LOOP__CF_LOOP_START__SHIFT 0x00000008 +#define SQ_CF_RT_LOOP__CF_LOOP_STEP__SHIFT 0x00000010 + +// SQ_VS_PROGRAM +#define SQ_VS_PROGRAM__BASE__SHIFT 0x00000000 +#define SQ_VS_PROGRAM__SIZE__SHIFT 0x0000000c + +// SQ_PS_PROGRAM +#define SQ_PS_PROGRAM__BASE__SHIFT 0x00000000 +#define SQ_PS_PROGRAM__SIZE__SHIFT 0x0000000c + +// SQ_CF_PROGRAM_SIZE +#define SQ_CF_PROGRAM_SIZE__VS_CF_SIZE__SHIFT 0x00000000 +#define SQ_CF_PROGRAM_SIZE__PS_CF_SIZE__SHIFT 0x0000000c + +// SQ_INTERPOLATOR_CNTL +#define SQ_INTERPOLATOR_CNTL__PARAM_SHADE__SHIFT 0x00000000 +#define SQ_INTERPOLATOR_CNTL__SAMPLING_PATTERN__SHIFT 0x00000010 + +// SQ_PROGRAM_CNTL +#define SQ_PROGRAM_CNTL__VS_NUM_REG__SHIFT 0x00000000 +#define SQ_PROGRAM_CNTL__PS_NUM_REG__SHIFT 0x00000008 +#define SQ_PROGRAM_CNTL__VS_RESOURCE__SHIFT 0x00000010 +#define SQ_PROGRAM_CNTL__PS_RESOURCE__SHIFT 0x00000011 +#define SQ_PROGRAM_CNTL__PARAM_GEN__SHIFT 0x00000012 +#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX__SHIFT 0x00000013 +#define SQ_PROGRAM_CNTL__VS_EXPORT_COUNT__SHIFT 0x00000014 +#define SQ_PROGRAM_CNTL__VS_EXPORT_MODE__SHIFT 0x00000018 +#define SQ_PROGRAM_CNTL__PS_EXPORT_MODE__SHIFT 0x0000001b +#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX__SHIFT 0x0000001f + +// SQ_WRAPPING_0 +#define SQ_WRAPPING_0__PARAM_WRAP_0__SHIFT 0x00000000 +#define SQ_WRAPPING_0__PARAM_WRAP_1__SHIFT 0x00000004 +#define SQ_WRAPPING_0__PARAM_WRAP_2__SHIFT 0x00000008 +#define SQ_WRAPPING_0__PARAM_WRAP_3__SHIFT 0x0000000c +#define SQ_WRAPPING_0__PARAM_WRAP_4__SHIFT 0x00000010 +#define SQ_WRAPPING_0__PARAM_WRAP_5__SHIFT 0x00000014 +#define SQ_WRAPPING_0__PARAM_WRAP_6__SHIFT 0x00000018 +#define SQ_WRAPPING_0__PARAM_WRAP_7__SHIFT 0x0000001c + +// SQ_WRAPPING_1 +#define SQ_WRAPPING_1__PARAM_WRAP_8__SHIFT 0x00000000 +#define SQ_WRAPPING_1__PARAM_WRAP_9__SHIFT 0x00000004 +#define SQ_WRAPPING_1__PARAM_WRAP_10__SHIFT 0x00000008 +#define SQ_WRAPPING_1__PARAM_WRAP_11__SHIFT 0x0000000c +#define SQ_WRAPPING_1__PARAM_WRAP_12__SHIFT 0x00000010 +#define SQ_WRAPPING_1__PARAM_WRAP_13__SHIFT 0x00000014 +#define SQ_WRAPPING_1__PARAM_WRAP_14__SHIFT 0x00000018 +#define SQ_WRAPPING_1__PARAM_WRAP_15__SHIFT 0x0000001c + +// SQ_VS_CONST +#define SQ_VS_CONST__BASE__SHIFT 0x00000000 +#define SQ_VS_CONST__SIZE__SHIFT 0x0000000c + +// SQ_PS_CONST +#define SQ_PS_CONST__BASE__SHIFT 0x00000000 +#define SQ_PS_CONST__SIZE__SHIFT 0x0000000c + +// SQ_CONTEXT_MISC +#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE__SHIFT 0x00000000 +#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY__SHIFT 0x00000001 +#define SQ_CONTEXT_MISC__SC_SAMPLE_CNTL__SHIFT 0x00000002 +#define SQ_CONTEXT_MISC__PARAM_GEN_POS__SHIFT 0x00000008 +#define SQ_CONTEXT_MISC__PERFCOUNTER_REF__SHIFT 0x00000010 +#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE__SHIFT 0x00000011 +#define SQ_CONTEXT_MISC__TX_CACHE_SEL__SHIFT 0x00000012 + +// SQ_CF_RD_BASE +#define SQ_CF_RD_BASE__RD_BASE__SHIFT 0x00000000 + +// SQ_DEBUG_MISC_0 +#define SQ_DEBUG_MISC_0__DB_PROB_ON__SHIFT 0x00000000 +#define SQ_DEBUG_MISC_0__DB_PROB_BREAK__SHIFT 0x00000004 +#define SQ_DEBUG_MISC_0__DB_PROB_ADDR__SHIFT 0x00000008 +#define SQ_DEBUG_MISC_0__DB_PROB_COUNT__SHIFT 0x00000018 + +// SQ_DEBUG_MISC_1 +#define SQ_DEBUG_MISC_1__DB_ON_PIX__SHIFT 0x00000000 +#define SQ_DEBUG_MISC_1__DB_ON_VTX__SHIFT 0x00000001 +#define SQ_DEBUG_MISC_1__DB_INST_COUNT__SHIFT 0x00000008 +#define SQ_DEBUG_MISC_1__DB_BREAK_ADDR__SHIFT 0x00000010 + +// MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG__SAME_PAGE_LIMIT__SHIFT 0x00000000 +#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY__SHIFT 0x00000006 +#define MH_ARBITER_CONFIG__L1_ARB_ENABLE__SHIFT 0x00000007 +#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE__SHIFT 0x00000008 +#define MH_ARBITER_CONFIG__L2_ARB_CONTROL__SHIFT 0x00000009 +#define MH_ARBITER_CONFIG__PAGE_SIZE__SHIFT 0x0000000a +#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE__SHIFT 0x0000000d +#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE__SHIFT 0x0000000e +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE__SHIFT 0x0000000f +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT__SHIFT 0x00000010 +#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE__SHIFT 0x00000016 +#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE__SHIFT 0x00000017 +#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE__SHIFT 0x00000018 +#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE__SHIFT 0x00000019 + +// MH_CLNT_AXI_ID_REUSE +#define MH_CLNT_AXI_ID_REUSE__CPw_ID__SHIFT 0x00000000 +#define MH_CLNT_AXI_ID_REUSE__RESERVED1__SHIFT 0x00000003 +#define MH_CLNT_AXI_ID_REUSE__RBw_ID__SHIFT 0x00000004 +#define MH_CLNT_AXI_ID_REUSE__RESERVED2__SHIFT 0x00000007 +#define MH_CLNT_AXI_ID_REUSE__MMUr_ID__SHIFT 0x00000008 + +// MH_INTERRUPT_MASK +#define MH_INTERRUPT_MASK__AXI_READ_ERROR__SHIFT 0x00000000 +#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR__SHIFT 0x00000001 +#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT__SHIFT 0x00000002 + +// MH_INTERRUPT_STATUS +#define MH_INTERRUPT_STATUS__AXI_READ_ERROR__SHIFT 0x00000000 +#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR__SHIFT 0x00000001 +#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT__SHIFT 0x00000002 + +// MH_INTERRUPT_CLEAR +#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR__SHIFT 0x00000000 +#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR__SHIFT 0x00000001 +#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT__SHIFT 0x00000002 + +// MH_AXI_ERROR +#define MH_AXI_ERROR__AXI_READ_ID__SHIFT 0x00000000 +#define MH_AXI_ERROR__AXI_READ_ERROR__SHIFT 0x00000003 +#define MH_AXI_ERROR__AXI_WRITE_ID__SHIFT 0x00000004 +#define MH_AXI_ERROR__AXI_WRITE_ERROR__SHIFT 0x00000007 + +// MH_PERFCOUNTER0_SELECT +#define MH_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// MH_PERFCOUNTER1_SELECT +#define MH_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 + +// MH_PERFCOUNTER0_CONFIG +#define MH_PERFCOUNTER0_CONFIG__N_VALUE__SHIFT 0x00000000 + +// MH_PERFCOUNTER1_CONFIG +#define MH_PERFCOUNTER1_CONFIG__N_VALUE__SHIFT 0x00000000 + +// MH_PERFCOUNTER0_LOW +#define MH_PERFCOUNTER0_LOW__PERF_COUNTER_LOW__SHIFT 0x00000000 + +// MH_PERFCOUNTER1_LOW +#define MH_PERFCOUNTER1_LOW__PERF_COUNTER_LOW__SHIFT 0x00000000 + +// MH_PERFCOUNTER0_HI +#define MH_PERFCOUNTER0_HI__PERF_COUNTER_HI__SHIFT 0x00000000 + +// MH_PERFCOUNTER1_HI +#define MH_PERFCOUNTER1_HI__PERF_COUNTER_HI__SHIFT 0x00000000 + +// MH_DEBUG_CTRL +#define MH_DEBUG_CTRL__INDEX__SHIFT 0x00000000 + +// MH_DEBUG_DATA +#define MH_DEBUG_DATA__DATA__SHIFT 0x00000000 + +// MH_DEBUG_REG00 +#define MH_DEBUG_REG00__MH_BUSY__SHIFT 0x00000000 +#define MH_DEBUG_REG00__TRANS_OUTSTANDING__SHIFT 0x00000001 +#define MH_DEBUG_REG00__CP_REQUEST__SHIFT 0x00000002 +#define MH_DEBUG_REG00__VGT_REQUEST__SHIFT 0x00000003 +#define MH_DEBUG_REG00__TC_REQUEST__SHIFT 0x00000004 +#define MH_DEBUG_REG00__TC_CAM_EMPTY__SHIFT 0x00000005 +#define MH_DEBUG_REG00__TC_CAM_FULL__SHIFT 0x00000006 +#define MH_DEBUG_REG00__TCD_EMPTY__SHIFT 0x00000007 +#define MH_DEBUG_REG00__TCD_FULL__SHIFT 0x00000008 +#define MH_DEBUG_REG00__RB_REQUEST__SHIFT 0x00000009 +#define MH_DEBUG_REG00__MH_CLK_EN_STATE__SHIFT 0x0000000a +#define MH_DEBUG_REG00__ARQ_EMPTY__SHIFT 0x0000000b +#define MH_DEBUG_REG00__ARQ_FULL__SHIFT 0x0000000c +#define MH_DEBUG_REG00__WDB_EMPTY__SHIFT 0x0000000d +#define MH_DEBUG_REG00__WDB_FULL__SHIFT 0x0000000e +#define MH_DEBUG_REG00__AXI_AVALID__SHIFT 0x0000000f +#define MH_DEBUG_REG00__AXI_AREADY__SHIFT 0x00000010 +#define MH_DEBUG_REG00__AXI_ARVALID__SHIFT 0x00000011 +#define MH_DEBUG_REG00__AXI_ARREADY__SHIFT 0x00000012 +#define MH_DEBUG_REG00__AXI_WVALID__SHIFT 0x00000013 +#define MH_DEBUG_REG00__AXI_WREADY__SHIFT 0x00000014 +#define MH_DEBUG_REG00__AXI_RVALID__SHIFT 0x00000015 +#define MH_DEBUG_REG00__AXI_RREADY__SHIFT 0x00000016 +#define MH_DEBUG_REG00__AXI_BVALID__SHIFT 0x00000017 +#define MH_DEBUG_REG00__AXI_BREADY__SHIFT 0x00000018 +#define MH_DEBUG_REG00__AXI_HALT_REQ__SHIFT 0x00000019 +#define MH_DEBUG_REG00__AXI_HALT_ACK__SHIFT 0x0000001a + +// MH_DEBUG_REG01 +#define MH_DEBUG_REG01__CP_SEND_q__SHIFT 0x00000000 +#define MH_DEBUG_REG01__CP_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG01__CP_WRITE_q__SHIFT 0x00000002 +#define MH_DEBUG_REG01__CP_TAG_q__SHIFT 0x00000003 +#define MH_DEBUG_REG01__CP_BE_q__SHIFT 0x00000006 +#define MH_DEBUG_REG01__VGT_SEND_q__SHIFT 0x0000000e +#define MH_DEBUG_REG01__VGT_RTR_q__SHIFT 0x0000000f +#define MH_DEBUG_REG01__VGT_TAG_q__SHIFT 0x00000010 +#define MH_DEBUG_REG01__TC_SEND_q__SHIFT 0x00000011 +#define MH_DEBUG_REG01__TC_RTR_q__SHIFT 0x00000012 +#define MH_DEBUG_REG01__TC_ROQ_SEND_q__SHIFT 0x00000013 +#define MH_DEBUG_REG01__TC_ROQ_RTR_q__SHIFT 0x00000014 +#define MH_DEBUG_REG01__TC_MH_written__SHIFT 0x00000015 +#define MH_DEBUG_REG01__RB_SEND_q__SHIFT 0x00000016 +#define MH_DEBUG_REG01__RB_RTR_q__SHIFT 0x00000017 +#define MH_DEBUG_REG01__RB_BE_q__SHIFT 0x00000018 + +// MH_DEBUG_REG02 +#define MH_DEBUG_REG02__MH_CP_grb_send__SHIFT 0x00000000 +#define MH_DEBUG_REG02__MH_VGT_grb_send__SHIFT 0x00000001 +#define MH_DEBUG_REG02__MH_TC_mcsend__SHIFT 0x00000002 +#define MH_DEBUG_REG02__MH_CLNT_rlast__SHIFT 0x00000003 +#define MH_DEBUG_REG02__MH_CLNT_tag__SHIFT 0x00000004 +#define MH_DEBUG_REG02__RDC_RID__SHIFT 0x00000007 +#define MH_DEBUG_REG02__RDC_RRESP__SHIFT 0x0000000a +#define MH_DEBUG_REG02__MH_CP_writeclean__SHIFT 0x0000000c +#define MH_DEBUG_REG02__MH_RB_writeclean__SHIFT 0x0000000d +#define MH_DEBUG_REG02__BRC_BID__SHIFT 0x0000000e +#define MH_DEBUG_REG02__BRC_BRESP__SHIFT 0x00000011 + +// MH_DEBUG_REG03 +#define MH_DEBUG_REG03__MH_CLNT_data_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG04 +#define MH_DEBUG_REG04__MH_CLNT_data_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG05 +#define MH_DEBUG_REG05__CP_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG05__CP_MH_write__SHIFT 0x00000001 +#define MH_DEBUG_REG05__CP_MH_tag__SHIFT 0x00000002 +#define MH_DEBUG_REG05__CP_MH_ad_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG06 +#define MH_DEBUG_REG06__CP_MH_data_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG07 +#define MH_DEBUG_REG07__CP_MH_data_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG08 +#define MH_DEBUG_REG08__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG08__VGT_MH_send__SHIFT 0x00000003 +#define MH_DEBUG_REG08__VGT_MH_tagbe__SHIFT 0x00000004 +#define MH_DEBUG_REG08__VGT_MH_ad_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG09 +#define MH_DEBUG_REG09__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG09__TC_MH_send__SHIFT 0x00000002 +#define MH_DEBUG_REG09__TC_MH_mask__SHIFT 0x00000003 +#define MH_DEBUG_REG09__TC_MH_addr_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG10 +#define MH_DEBUG_REG10__TC_MH_info__SHIFT 0x00000000 +#define MH_DEBUG_REG10__TC_MH_send__SHIFT 0x00000019 + +// MH_DEBUG_REG11 +#define MH_DEBUG_REG11__MH_TC_mcinfo__SHIFT 0x00000000 +#define MH_DEBUG_REG11__MH_TC_mcinfo_send__SHIFT 0x00000019 +#define MH_DEBUG_REG11__TC_MH_written__SHIFT 0x0000001a + +// MH_DEBUG_REG12 +#define MH_DEBUG_REG12__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG12__TC_ROQ_SEND__SHIFT 0x00000002 +#define MH_DEBUG_REG12__TC_ROQ_MASK__SHIFT 0x00000003 +#define MH_DEBUG_REG12__TC_ROQ_ADDR_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG13 +#define MH_DEBUG_REG13__TC_ROQ_INFO__SHIFT 0x00000000 +#define MH_DEBUG_REG13__TC_ROQ_SEND__SHIFT 0x00000019 + +// MH_DEBUG_REG14 +#define MH_DEBUG_REG14__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG14__RB_MH_send__SHIFT 0x00000004 +#define MH_DEBUG_REG14__RB_MH_addr_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG15 +#define MH_DEBUG_REG15__RB_MH_data_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG16 +#define MH_DEBUG_REG16__RB_MH_data_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG17 +#define MH_DEBUG_REG17__AVALID_q__SHIFT 0x00000000 +#define MH_DEBUG_REG17__AREADY_q__SHIFT 0x00000001 +#define MH_DEBUG_REG17__AID_q__SHIFT 0x00000002 +#define MH_DEBUG_REG17__ALEN_q_2_0__SHIFT 0x00000005 +#define MH_DEBUG_REG17__ARVALID_q__SHIFT 0x00000008 +#define MH_DEBUG_REG17__ARREADY_q__SHIFT 0x00000009 +#define MH_DEBUG_REG17__ARID_q__SHIFT 0x0000000a +#define MH_DEBUG_REG17__ARLEN_q_1_0__SHIFT 0x0000000d +#define MH_DEBUG_REG17__RVALID_q__SHIFT 0x0000000f +#define MH_DEBUG_REG17__RREADY_q__SHIFT 0x00000010 +#define MH_DEBUG_REG17__RLAST_q__SHIFT 0x00000011 +#define MH_DEBUG_REG17__RID_q__SHIFT 0x00000012 +#define MH_DEBUG_REG17__WVALID_q__SHIFT 0x00000015 +#define MH_DEBUG_REG17__WREADY_q__SHIFT 0x00000016 +#define MH_DEBUG_REG17__WLAST_q__SHIFT 0x00000017 +#define MH_DEBUG_REG17__WID_q__SHIFT 0x00000018 +#define MH_DEBUG_REG17__BVALID_q__SHIFT 0x0000001b +#define MH_DEBUG_REG17__BREADY_q__SHIFT 0x0000001c +#define MH_DEBUG_REG17__BID_q__SHIFT 0x0000001d + +// MH_DEBUG_REG18 +#define MH_DEBUG_REG18__AVALID_q__SHIFT 0x00000000 +#define MH_DEBUG_REG18__AREADY_q__SHIFT 0x00000001 +#define MH_DEBUG_REG18__AID_q__SHIFT 0x00000002 +#define MH_DEBUG_REG18__ALEN_q_1_0__SHIFT 0x00000005 +#define MH_DEBUG_REG18__ARVALID_q__SHIFT 0x00000007 +#define MH_DEBUG_REG18__ARREADY_q__SHIFT 0x00000008 +#define MH_DEBUG_REG18__ARID_q__SHIFT 0x00000009 +#define MH_DEBUG_REG18__ARLEN_q_1_1__SHIFT 0x0000000c +#define MH_DEBUG_REG18__WVALID_q__SHIFT 0x0000000d +#define MH_DEBUG_REG18__WREADY_q__SHIFT 0x0000000e +#define MH_DEBUG_REG18__WLAST_q__SHIFT 0x0000000f +#define MH_DEBUG_REG18__WID_q__SHIFT 0x00000010 +#define MH_DEBUG_REG18__WSTRB_q__SHIFT 0x00000013 +#define MH_DEBUG_REG18__BVALID_q__SHIFT 0x0000001b +#define MH_DEBUG_REG18__BREADY_q__SHIFT 0x0000001c +#define MH_DEBUG_REG18__BID_q__SHIFT 0x0000001d + +// MH_DEBUG_REG19 +#define MH_DEBUG_REG19__ARC_CTRL_RE_q__SHIFT 0x00000000 +#define MH_DEBUG_REG19__CTRL_ARC_ID__SHIFT 0x00000001 +#define MH_DEBUG_REG19__CTRL_ARC_PAD__SHIFT 0x00000004 + +// MH_DEBUG_REG20 +#define MH_DEBUG_REG20__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG20__REG_A__SHIFT 0x00000002 +#define MH_DEBUG_REG20__REG_RE__SHIFT 0x00000010 +#define MH_DEBUG_REG20__REG_WE__SHIFT 0x00000011 +#define MH_DEBUG_REG20__BLOCK_RS__SHIFT 0x00000012 + +// MH_DEBUG_REG21 +#define MH_DEBUG_REG21__REG_WD__SHIFT 0x00000000 + +// MH_DEBUG_REG22 +#define MH_DEBUG_REG22__CIB_MH_axi_halt_req__SHIFT 0x00000000 +#define MH_DEBUG_REG22__MH_CIB_axi_halt_ack__SHIFT 0x00000001 +#define MH_DEBUG_REG22__MH_RBBM_busy__SHIFT 0x00000002 +#define MH_DEBUG_REG22__MH_CIB_mh_clk_en_int__SHIFT 0x00000003 +#define MH_DEBUG_REG22__MH_CIB_mmu_clk_en_int__SHIFT 0x00000004 +#define MH_DEBUG_REG22__MH_CIB_tcroq_clk_en_int__SHIFT 0x00000005 +#define MH_DEBUG_REG22__GAT_CLK_ENA__SHIFT 0x00000006 +#define MH_DEBUG_REG22__AXI_RDY_ENA__SHIFT 0x00000007 +#define MH_DEBUG_REG22__RBBM_MH_clk_en_override__SHIFT 0x00000008 +#define MH_DEBUG_REG22__CNT_q__SHIFT 0x00000009 +#define MH_DEBUG_REG22__TCD_EMPTY_q__SHIFT 0x0000000f +#define MH_DEBUG_REG22__TC_ROQ_EMPTY__SHIFT 0x00000010 +#define MH_DEBUG_REG22__MH_BUSY_d__SHIFT 0x00000011 +#define MH_DEBUG_REG22__ANY_CLNT_BUSY__SHIFT 0x00000012 +#define MH_DEBUG_REG22__MH_MMU_INVALIDATE_INVALIDATE_ALL__SHIFT 0x00000013 +#define MH_DEBUG_REG22__CP_SEND_q__SHIFT 0x00000014 +#define MH_DEBUG_REG22__CP_RTR_q__SHIFT 0x00000015 +#define MH_DEBUG_REG22__VGT_SEND_q__SHIFT 0x00000016 +#define MH_DEBUG_REG22__VGT_RTR_q__SHIFT 0x00000017 +#define MH_DEBUG_REG22__TC_ROQ_SEND_q__SHIFT 0x00000018 +#define MH_DEBUG_REG22__TC_ROQ_RTR_q__SHIFT 0x00000019 +#define MH_DEBUG_REG22__RB_SEND_q__SHIFT 0x0000001a +#define MH_DEBUG_REG22__RB_RTR_q__SHIFT 0x0000001b +#define MH_DEBUG_REG22__RDC_VALID__SHIFT 0x0000001c +#define MH_DEBUG_REG22__RDC_RLAST__SHIFT 0x0000001d +#define MH_DEBUG_REG22__TLBMISS_VALID__SHIFT 0x0000001e +#define MH_DEBUG_REG22__BRC_VALID__SHIFT 0x0000001f + +// MH_DEBUG_REG23 +#define MH_DEBUG_REG23__EFF2_FP_WINNER__SHIFT 0x00000000 +#define MH_DEBUG_REG23__EFF2_LRU_WINNER_out__SHIFT 0x00000003 +#define MH_DEBUG_REG23__EFF1_WINNER__SHIFT 0x00000006 +#define MH_DEBUG_REG23__ARB_WINNER__SHIFT 0x00000009 +#define MH_DEBUG_REG23__ARB_WINNER_q__SHIFT 0x0000000c +#define MH_DEBUG_REG23__EFF1_WIN__SHIFT 0x0000000f +#define MH_DEBUG_REG23__KILL_EFF1__SHIFT 0x00000010 +#define MH_DEBUG_REG23__ARB_HOLD__SHIFT 0x00000011 +#define MH_DEBUG_REG23__ARB_RTR_q__SHIFT 0x00000012 +#define MH_DEBUG_REG23__CP_SEND_QUAL__SHIFT 0x00000013 +#define MH_DEBUG_REG23__VGT_SEND_QUAL__SHIFT 0x00000014 +#define MH_DEBUG_REG23__TC_SEND_QUAL__SHIFT 0x00000015 +#define MH_DEBUG_REG23__TC_SEND_EFF1_QUAL__SHIFT 0x00000016 +#define MH_DEBUG_REG23__RB_SEND_QUAL__SHIFT 0x00000017 +#define MH_DEBUG_REG23__ARB_QUAL__SHIFT 0x00000018 +#define MH_DEBUG_REG23__CP_EFF1_REQ__SHIFT 0x00000019 +#define MH_DEBUG_REG23__VGT_EFF1_REQ__SHIFT 0x0000001a +#define MH_DEBUG_REG23__TC_EFF1_REQ__SHIFT 0x0000001b +#define MH_DEBUG_REG23__RB_EFF1_REQ__SHIFT 0x0000001c +#define MH_DEBUG_REG23__ANY_SAME_ROW_BANK__SHIFT 0x0000001d +#define MH_DEBUG_REG23__TCD_NEARFULL_q__SHIFT 0x0000001e +#define MH_DEBUG_REG23__TCHOLD_IP_q__SHIFT 0x0000001f + +// MH_DEBUG_REG24 +#define MH_DEBUG_REG24__EFF1_WINNER__SHIFT 0x00000000 +#define MH_DEBUG_REG24__ARB_WINNER__SHIFT 0x00000003 +#define MH_DEBUG_REG24__CP_SEND_QUAL__SHIFT 0x00000006 +#define MH_DEBUG_REG24__VGT_SEND_QUAL__SHIFT 0x00000007 +#define MH_DEBUG_REG24__TC_SEND_QUAL__SHIFT 0x00000008 +#define MH_DEBUG_REG24__TC_SEND_EFF1_QUAL__SHIFT 0x00000009 +#define MH_DEBUG_REG24__RB_SEND_QUAL__SHIFT 0x0000000a +#define MH_DEBUG_REG24__ARB_QUAL__SHIFT 0x0000000b +#define MH_DEBUG_REG24__CP_EFF1_REQ__SHIFT 0x0000000c +#define MH_DEBUG_REG24__VGT_EFF1_REQ__SHIFT 0x0000000d +#define MH_DEBUG_REG24__TC_EFF1_REQ__SHIFT 0x0000000e +#define MH_DEBUG_REG24__RB_EFF1_REQ__SHIFT 0x0000000f +#define MH_DEBUG_REG24__EFF1_WIN__SHIFT 0x00000010 +#define MH_DEBUG_REG24__KILL_EFF1__SHIFT 0x00000011 +#define MH_DEBUG_REG24__TCD_NEARFULL_q__SHIFT 0x00000012 +#define MH_DEBUG_REG24__TC_ARB_HOLD__SHIFT 0x00000013 +#define MH_DEBUG_REG24__ARB_HOLD__SHIFT 0x00000014 +#define MH_DEBUG_REG24__ARB_RTR_q__SHIFT 0x00000015 +#define MH_DEBUG_REG24__SAME_PAGE_LIMIT_COUNT_q__SHIFT 0x00000016 + +// MH_DEBUG_REG25 +#define MH_DEBUG_REG25__EFF2_LRU_WINNER_out__SHIFT 0x00000000 +#define MH_DEBUG_REG25__ARB_WINNER__SHIFT 0x00000003 +#define MH_DEBUG_REG25__LEAST_RECENT_INDEX_d__SHIFT 0x00000006 +#define MH_DEBUG_REG25__LEAST_RECENT_d__SHIFT 0x00000009 +#define MH_DEBUG_REG25__UPDATE_RECENT_STACK_d__SHIFT 0x0000000c +#define MH_DEBUG_REG25__ARB_HOLD__SHIFT 0x0000000d +#define MH_DEBUG_REG25__ARB_RTR_q__SHIFT 0x0000000e +#define MH_DEBUG_REG25__EFF1_WIN__SHIFT 0x0000000f +#define MH_DEBUG_REG25__CLNT_REQ__SHIFT 0x00000010 +#define MH_DEBUG_REG25__RECENT_d_0__SHIFT 0x00000014 +#define MH_DEBUG_REG25__RECENT_d_1__SHIFT 0x00000017 +#define MH_DEBUG_REG25__RECENT_d_2__SHIFT 0x0000001a +#define MH_DEBUG_REG25__RECENT_d_3__SHIFT 0x0000001d + +// MH_DEBUG_REG26 +#define MH_DEBUG_REG26__TC_ARB_HOLD__SHIFT 0x00000000 +#define MH_DEBUG_REG26__TC_NOROQ_SAME_ROW_BANK__SHIFT 0x00000001 +#define MH_DEBUG_REG26__TC_ROQ_SAME_ROW_BANK__SHIFT 0x00000002 +#define MH_DEBUG_REG26__TCD_NEARFULL_q__SHIFT 0x00000003 +#define MH_DEBUG_REG26__TCHOLD_IP_q__SHIFT 0x00000004 +#define MH_DEBUG_REG26__TCHOLD_CNT_q__SHIFT 0x00000005 +#define MH_DEBUG_REG26__MH_ARBITER_CONFIG_TC_REORDER_ENABLE__SHIFT 0x00000008 +#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q__SHIFT 0x00000009 +#define MH_DEBUG_REG26__TC_ROQ_SEND_q__SHIFT 0x0000000a +#define MH_DEBUG_REG26__TC_MH_written__SHIFT 0x0000000b +#define MH_DEBUG_REG26__TCD_FULLNESS_CNT_q__SHIFT 0x0000000c +#define MH_DEBUG_REG26__WBURST_ACTIVE__SHIFT 0x00000013 +#define MH_DEBUG_REG26__WLAST_q__SHIFT 0x00000014 +#define MH_DEBUG_REG26__WBURST_IP_q__SHIFT 0x00000015 +#define MH_DEBUG_REG26__WBURST_CNT_q__SHIFT 0x00000016 +#define MH_DEBUG_REG26__CP_SEND_QUAL__SHIFT 0x00000019 +#define MH_DEBUG_REG26__CP_MH_write__SHIFT 0x0000001a +#define MH_DEBUG_REG26__RB_SEND_QUAL__SHIFT 0x0000001b +#define MH_DEBUG_REG26__ARB_WINNER__SHIFT 0x0000001c + +// MH_DEBUG_REG27 +#define MH_DEBUG_REG27__RF_ARBITER_CONFIG_q__SHIFT 0x00000000 +#define MH_DEBUG_REG27__MH_CLNT_AXI_ID_REUSE_MMUr_ID__SHIFT 0x0000001a + +// MH_DEBUG_REG28 +#define MH_DEBUG_REG28__SAME_ROW_BANK_q__SHIFT 0x00000000 +#define MH_DEBUG_REG28__ROQ_MARK_q__SHIFT 0x00000008 +#define MH_DEBUG_REG28__ROQ_VALID_q__SHIFT 0x00000010 +#define MH_DEBUG_REG28__TC_MH_send__SHIFT 0x00000018 +#define MH_DEBUG_REG28__TC_ROQ_RTR_q__SHIFT 0x00000019 +#define MH_DEBUG_REG28__KILL_EFF1__SHIFT 0x0000001a +#define MH_DEBUG_REG28__TC_ROQ_SAME_ROW_BANK_SEL__SHIFT 0x0000001b +#define MH_DEBUG_REG28__ANY_SAME_ROW_BANK__SHIFT 0x0000001c +#define MH_DEBUG_REG28__TC_EFF1_QUAL__SHIFT 0x0000001d +#define MH_DEBUG_REG28__TC_ROQ_EMPTY__SHIFT 0x0000001e +#define MH_DEBUG_REG28__TC_ROQ_FULL__SHIFT 0x0000001f + +// MH_DEBUG_REG29 +#define MH_DEBUG_REG29__SAME_ROW_BANK_q__SHIFT 0x00000000 +#define MH_DEBUG_REG29__ROQ_MARK_d__SHIFT 0x00000008 +#define MH_DEBUG_REG29__ROQ_VALID_d__SHIFT 0x00000010 +#define MH_DEBUG_REG29__TC_MH_send__SHIFT 0x00000018 +#define MH_DEBUG_REG29__TC_ROQ_RTR_q__SHIFT 0x00000019 +#define MH_DEBUG_REG29__KILL_EFF1__SHIFT 0x0000001a +#define MH_DEBUG_REG29__TC_ROQ_SAME_ROW_BANK_SEL__SHIFT 0x0000001b +#define MH_DEBUG_REG29__ANY_SAME_ROW_BANK__SHIFT 0x0000001c +#define MH_DEBUG_REG29__TC_EFF1_QUAL__SHIFT 0x0000001d +#define MH_DEBUG_REG29__TC_ROQ_EMPTY__SHIFT 0x0000001e +#define MH_DEBUG_REG29__TC_ROQ_FULL__SHIFT 0x0000001f + +// MH_DEBUG_REG30 +#define MH_DEBUG_REG30__SAME_ROW_BANK_WIN__SHIFT 0x00000000 +#define MH_DEBUG_REG30__SAME_ROW_BANK_REQ__SHIFT 0x00000008 +#define MH_DEBUG_REG30__NON_SAME_ROW_BANK_WIN__SHIFT 0x00000010 +#define MH_DEBUG_REG30__NON_SAME_ROW_BANK_REQ__SHIFT 0x00000018 + +// MH_DEBUG_REG31 +#define MH_DEBUG_REG31__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG31__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG31__ROQ_MARK_q_0__SHIFT 0x00000002 +#define MH_DEBUG_REG31__ROQ_VALID_q_0__SHIFT 0x00000003 +#define MH_DEBUG_REG31__SAME_ROW_BANK_q_0__SHIFT 0x00000004 +#define MH_DEBUG_REG31__ROQ_ADDR_0__SHIFT 0x00000005 + +// MH_DEBUG_REG32 +#define MH_DEBUG_REG32__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG32__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG32__ROQ_MARK_q_1__SHIFT 0x00000002 +#define MH_DEBUG_REG32__ROQ_VALID_q_1__SHIFT 0x00000003 +#define MH_DEBUG_REG32__SAME_ROW_BANK_q_1__SHIFT 0x00000004 +#define MH_DEBUG_REG32__ROQ_ADDR_1__SHIFT 0x00000005 + +// MH_DEBUG_REG33 +#define MH_DEBUG_REG33__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG33__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG33__ROQ_MARK_q_2__SHIFT 0x00000002 +#define MH_DEBUG_REG33__ROQ_VALID_q_2__SHIFT 0x00000003 +#define MH_DEBUG_REG33__SAME_ROW_BANK_q_2__SHIFT 0x00000004 +#define MH_DEBUG_REG33__ROQ_ADDR_2__SHIFT 0x00000005 + +// MH_DEBUG_REG34 +#define MH_DEBUG_REG34__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG34__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG34__ROQ_MARK_q_3__SHIFT 0x00000002 +#define MH_DEBUG_REG34__ROQ_VALID_q_3__SHIFT 0x00000003 +#define MH_DEBUG_REG34__SAME_ROW_BANK_q_3__SHIFT 0x00000004 +#define MH_DEBUG_REG34__ROQ_ADDR_3__SHIFT 0x00000005 + +// MH_DEBUG_REG35 +#define MH_DEBUG_REG35__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG35__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG35__ROQ_MARK_q_4__SHIFT 0x00000002 +#define MH_DEBUG_REG35__ROQ_VALID_q_4__SHIFT 0x00000003 +#define MH_DEBUG_REG35__SAME_ROW_BANK_q_4__SHIFT 0x00000004 +#define MH_DEBUG_REG35__ROQ_ADDR_4__SHIFT 0x00000005 + +// MH_DEBUG_REG36 +#define MH_DEBUG_REG36__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG36__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG36__ROQ_MARK_q_5__SHIFT 0x00000002 +#define MH_DEBUG_REG36__ROQ_VALID_q_5__SHIFT 0x00000003 +#define MH_DEBUG_REG36__SAME_ROW_BANK_q_5__SHIFT 0x00000004 +#define MH_DEBUG_REG36__ROQ_ADDR_5__SHIFT 0x00000005 + +// MH_DEBUG_REG37 +#define MH_DEBUG_REG37__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG37__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG37__ROQ_MARK_q_6__SHIFT 0x00000002 +#define MH_DEBUG_REG37__ROQ_VALID_q_6__SHIFT 0x00000003 +#define MH_DEBUG_REG37__SAME_ROW_BANK_q_6__SHIFT 0x00000004 +#define MH_DEBUG_REG37__ROQ_ADDR_6__SHIFT 0x00000005 + +// MH_DEBUG_REG38 +#define MH_DEBUG_REG38__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG38__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG38__ROQ_MARK_q_7__SHIFT 0x00000002 +#define MH_DEBUG_REG38__ROQ_VALID_q_7__SHIFT 0x00000003 +#define MH_DEBUG_REG38__SAME_ROW_BANK_q_7__SHIFT 0x00000004 +#define MH_DEBUG_REG38__ROQ_ADDR_7__SHIFT 0x00000005 + +// MH_DEBUG_REG39 +#define MH_DEBUG_REG39__ARB_WE__SHIFT 0x00000000 +#define MH_DEBUG_REG39__MMU_RTR__SHIFT 0x00000001 +#define MH_DEBUG_REG39__ARB_ID_q__SHIFT 0x00000002 +#define MH_DEBUG_REG39__ARB_WRITE_q__SHIFT 0x00000005 +#define MH_DEBUG_REG39__ARB_BLEN_q__SHIFT 0x00000006 +#define MH_DEBUG_REG39__ARQ_CTRL_EMPTY__SHIFT 0x00000007 +#define MH_DEBUG_REG39__ARQ_FIFO_CNT_q__SHIFT 0x00000008 +#define MH_DEBUG_REG39__MMU_WE__SHIFT 0x0000000b +#define MH_DEBUG_REG39__ARQ_RTR__SHIFT 0x0000000c +#define MH_DEBUG_REG39__MMU_ID__SHIFT 0x0000000d +#define MH_DEBUG_REG39__MMU_WRITE__SHIFT 0x00000010 +#define MH_DEBUG_REG39__MMU_BLEN__SHIFT 0x00000011 + +// MH_DEBUG_REG40 +#define MH_DEBUG_REG40__ARB_WE__SHIFT 0x00000000 +#define MH_DEBUG_REG40__ARB_ID_q__SHIFT 0x00000001 +#define MH_DEBUG_REG40__ARB_VAD_q__SHIFT 0x00000004 + +// MH_DEBUG_REG41 +#define MH_DEBUG_REG41__MMU_WE__SHIFT 0x00000000 +#define MH_DEBUG_REG41__MMU_ID__SHIFT 0x00000001 +#define MH_DEBUG_REG41__MMU_PAD__SHIFT 0x00000004 + +// MH_DEBUG_REG42 +#define MH_DEBUG_REG42__WDB_WE__SHIFT 0x00000000 +#define MH_DEBUG_REG42__WDB_RTR_SKID__SHIFT 0x00000001 +#define MH_DEBUG_REG42__ARB_WSTRB_q__SHIFT 0x00000002 +#define MH_DEBUG_REG42__ARB_WLAST__SHIFT 0x0000000a +#define MH_DEBUG_REG42__WDB_CTRL_EMPTY__SHIFT 0x0000000b +#define MH_DEBUG_REG42__WDB_FIFO_CNT_q__SHIFT 0x0000000c +#define MH_DEBUG_REG42__WDC_WDB_RE_q__SHIFT 0x00000011 +#define MH_DEBUG_REG42__WDB_WDC_WID__SHIFT 0x00000012 +#define MH_DEBUG_REG42__WDB_WDC_WLAST__SHIFT 0x00000015 +#define MH_DEBUG_REG42__WDB_WDC_WSTRB__SHIFT 0x00000016 + +// MH_DEBUG_REG43 +#define MH_DEBUG_REG43__ARB_WDATA_q_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG44 +#define MH_DEBUG_REG44__ARB_WDATA_q_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG45 +#define MH_DEBUG_REG45__WDB_WDC_WDATA_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG46 +#define MH_DEBUG_REG46__WDB_WDC_WDATA_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG47 +#define MH_DEBUG_REG47__CTRL_ARC_EMPTY__SHIFT 0x00000000 +#define MH_DEBUG_REG47__CTRL_RARC_EMPTY__SHIFT 0x00000001 +#define MH_DEBUG_REG47__ARQ_CTRL_EMPTY__SHIFT 0x00000002 +#define MH_DEBUG_REG47__ARQ_CTRL_WRITE__SHIFT 0x00000003 +#define MH_DEBUG_REG47__TLBMISS_CTRL_RTS__SHIFT 0x00000004 +#define MH_DEBUG_REG47__CTRL_TLBMISS_RE_q__SHIFT 0x00000005 +#define MH_DEBUG_REG47__INFLT_LIMIT_q__SHIFT 0x00000006 +#define MH_DEBUG_REG47__INFLT_LIMIT_CNT_q__SHIFT 0x00000007 +#define MH_DEBUG_REG47__ARC_CTRL_RE_q__SHIFT 0x0000000d +#define MH_DEBUG_REG47__RARC_CTRL_RE_q__SHIFT 0x0000000e +#define MH_DEBUG_REG47__RVALID_q__SHIFT 0x0000000f +#define MH_DEBUG_REG47__RREADY_q__SHIFT 0x00000010 +#define MH_DEBUG_REG47__RLAST_q__SHIFT 0x00000011 +#define MH_DEBUG_REG47__BVALID_q__SHIFT 0x00000012 +#define MH_DEBUG_REG47__BREADY_q__SHIFT 0x00000013 + +// MH_DEBUG_REG48 +#define MH_DEBUG_REG48__MH_CP_grb_send__SHIFT 0x00000000 +#define MH_DEBUG_REG48__MH_VGT_grb_send__SHIFT 0x00000001 +#define MH_DEBUG_REG48__MH_TC_mcsend__SHIFT 0x00000002 +#define MH_DEBUG_REG48__MH_TLBMISS_SEND__SHIFT 0x00000003 +#define MH_DEBUG_REG48__TLBMISS_VALID__SHIFT 0x00000004 +#define MH_DEBUG_REG48__RDC_VALID__SHIFT 0x00000005 +#define MH_DEBUG_REG48__RDC_RID__SHIFT 0x00000006 +#define MH_DEBUG_REG48__RDC_RLAST__SHIFT 0x00000009 +#define MH_DEBUG_REG48__RDC_RRESP__SHIFT 0x0000000a +#define MH_DEBUG_REG48__TLBMISS_CTRL_RTS__SHIFT 0x0000000c +#define MH_DEBUG_REG48__CTRL_TLBMISS_RE_q__SHIFT 0x0000000d +#define MH_DEBUG_REG48__MMU_ID_REQUEST_q__SHIFT 0x0000000e +#define MH_DEBUG_REG48__OUTSTANDING_MMUID_CNT_q__SHIFT 0x0000000f +#define MH_DEBUG_REG48__MMU_ID_RESPONSE__SHIFT 0x00000015 +#define MH_DEBUG_REG48__TLBMISS_RETURN_CNT_q__SHIFT 0x00000016 +#define MH_DEBUG_REG48__CNT_HOLD_q1__SHIFT 0x0000001c +#define MH_DEBUG_REG48__MH_CLNT_AXI_ID_REUSE_MMUr_ID__SHIFT 0x0000001d + +// MH_DEBUG_REG49 +#define MH_DEBUG_REG49__RF_MMU_PAGE_FAULT__SHIFT 0x00000000 + +// MH_DEBUG_REG50 +#define MH_DEBUG_REG50__RF_MMU_CONFIG_q__SHIFT 0x00000000 +#define MH_DEBUG_REG50__ARB_ID_q__SHIFT 0x00000018 +#define MH_DEBUG_REG50__ARB_WRITE_q__SHIFT 0x0000001b +#define MH_DEBUG_REG50__client_behavior_q__SHIFT 0x0000001c +#define MH_DEBUG_REG50__ARB_WE__SHIFT 0x0000001e +#define MH_DEBUG_REG50__MMU_RTR__SHIFT 0x0000001f + +// MH_DEBUG_REG51 +#define MH_DEBUG_REG51__stage1_valid__SHIFT 0x00000000 +#define MH_DEBUG_REG51__IGNORE_TAG_MISS_q__SHIFT 0x00000001 +#define MH_DEBUG_REG51__pa_in_mpu_range__SHIFT 0x00000002 +#define MH_DEBUG_REG51__tag_match_q__SHIFT 0x00000003 +#define MH_DEBUG_REG51__tag_miss_q__SHIFT 0x00000004 +#define MH_DEBUG_REG51__va_in_range_q__SHIFT 0x00000005 +#define MH_DEBUG_REG51__MMU_MISS__SHIFT 0x00000006 +#define MH_DEBUG_REG51__MMU_READ_MISS__SHIFT 0x00000007 +#define MH_DEBUG_REG51__MMU_WRITE_MISS__SHIFT 0x00000008 +#define MH_DEBUG_REG51__MMU_HIT__SHIFT 0x00000009 +#define MH_DEBUG_REG51__MMU_READ_HIT__SHIFT 0x0000000a +#define MH_DEBUG_REG51__MMU_WRITE_HIT__SHIFT 0x0000000b +#define MH_DEBUG_REG51__MMU_SPLIT_MODE_TC_MISS__SHIFT 0x0000000c +#define MH_DEBUG_REG51__MMU_SPLIT_MODE_TC_HIT__SHIFT 0x0000000d +#define MH_DEBUG_REG51__MMU_SPLIT_MODE_nonTC_MISS__SHIFT 0x0000000e +#define MH_DEBUG_REG51__MMU_SPLIT_MODE_nonTC_HIT__SHIFT 0x0000000f +#define MH_DEBUG_REG51__REQ_VA_OFFSET_q__SHIFT 0x00000010 + +// MH_DEBUG_REG52 +#define MH_DEBUG_REG52__ARQ_RTR__SHIFT 0x00000000 +#define MH_DEBUG_REG52__MMU_WE__SHIFT 0x00000001 +#define MH_DEBUG_REG52__CTRL_TLBMISS_RE_q__SHIFT 0x00000002 +#define MH_DEBUG_REG52__TLBMISS_CTRL_RTS__SHIFT 0x00000003 +#define MH_DEBUG_REG52__MH_TLBMISS_SEND__SHIFT 0x00000004 +#define MH_DEBUG_REG52__MMU_STALL_AWAITING_TLB_MISS_FETCH__SHIFT 0x00000005 +#define MH_DEBUG_REG52__pa_in_mpu_range__SHIFT 0x00000006 +#define MH_DEBUG_REG52__stage1_valid__SHIFT 0x00000007 +#define MH_DEBUG_REG52__stage2_valid__SHIFT 0x00000008 +#define MH_DEBUG_REG52__client_behavior_q__SHIFT 0x00000009 +#define MH_DEBUG_REG52__IGNORE_TAG_MISS_q__SHIFT 0x0000000b +#define MH_DEBUG_REG52__tag_match_q__SHIFT 0x0000000c +#define MH_DEBUG_REG52__tag_miss_q__SHIFT 0x0000000d +#define MH_DEBUG_REG52__va_in_range_q__SHIFT 0x0000000e +#define MH_DEBUG_REG52__PTE_FETCH_COMPLETE_q__SHIFT 0x0000000f +#define MH_DEBUG_REG52__TAG_valid_q__SHIFT 0x00000010 + +// MH_DEBUG_REG53 +#define MH_DEBUG_REG53__TAG0_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG53__TAG_valid_q_0__SHIFT 0x0000000d +#define MH_DEBUG_REG53__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG53__TAG1_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG53__TAG_valid_q_1__SHIFT 0x0000001d + +// MH_DEBUG_REG54 +#define MH_DEBUG_REG54__TAG2_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG54__TAG_valid_q_2__SHIFT 0x0000000d +#define MH_DEBUG_REG54__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG54__TAG3_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG54__TAG_valid_q_3__SHIFT 0x0000001d + +// MH_DEBUG_REG55 +#define MH_DEBUG_REG55__TAG4_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG55__TAG_valid_q_4__SHIFT 0x0000000d +#define MH_DEBUG_REG55__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG55__TAG5_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG55__TAG_valid_q_5__SHIFT 0x0000001d + +// MH_DEBUG_REG56 +#define MH_DEBUG_REG56__TAG6_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG56__TAG_valid_q_6__SHIFT 0x0000000d +#define MH_DEBUG_REG56__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG56__TAG7_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG56__TAG_valid_q_7__SHIFT 0x0000001d + +// MH_DEBUG_REG57 +#define MH_DEBUG_REG57__TAG8_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG57__TAG_valid_q_8__SHIFT 0x0000000d +#define MH_DEBUG_REG57__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG57__TAG9_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG57__TAG_valid_q_9__SHIFT 0x0000001d + +// MH_DEBUG_REG58 +#define MH_DEBUG_REG58__TAG10_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG58__TAG_valid_q_10__SHIFT 0x0000000d +#define MH_DEBUG_REG58__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG58__TAG11_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG58__TAG_valid_q_11__SHIFT 0x0000001d + +// MH_DEBUG_REG59 +#define MH_DEBUG_REG59__TAG12_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG59__TAG_valid_q_12__SHIFT 0x0000000d +#define MH_DEBUG_REG59__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG59__TAG13_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG59__TAG_valid_q_13__SHIFT 0x0000001d + +// MH_DEBUG_REG60 +#define MH_DEBUG_REG60__TAG14_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG60__TAG_valid_q_14__SHIFT 0x0000000d +#define MH_DEBUG_REG60__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG60__TAG15_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG60__TAG_valid_q_15__SHIFT 0x0000001d + +// MH_DEBUG_REG61 +#define MH_DEBUG_REG61__MH_DBG_DEFAULT__SHIFT 0x00000000 + +// MH_DEBUG_REG62 +#define MH_DEBUG_REG62__MH_DBG_DEFAULT__SHIFT 0x00000000 + +// MH_DEBUG_REG63 +#define MH_DEBUG_REG63__MH_DBG_DEFAULT__SHIFT 0x00000000 + +// MH_MMU_CONFIG +#define MH_MMU_CONFIG__MMU_ENABLE__SHIFT 0x00000000 +#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE__SHIFT 0x00000001 +#define MH_MMU_CONFIG__RESERVED1__SHIFT 0x00000002 +#define MH_MMU_CONFIG__RB_W_CLNT_BEHAVIOR__SHIFT 0x00000004 +#define MH_MMU_CONFIG__CP_W_CLNT_BEHAVIOR__SHIFT 0x00000006 +#define MH_MMU_CONFIG__CP_R0_CLNT_BEHAVIOR__SHIFT 0x00000008 +#define MH_MMU_CONFIG__CP_R1_CLNT_BEHAVIOR__SHIFT 0x0000000a +#define MH_MMU_CONFIG__CP_R2_CLNT_BEHAVIOR__SHIFT 0x0000000c +#define MH_MMU_CONFIG__CP_R3_CLNT_BEHAVIOR__SHIFT 0x0000000e +#define MH_MMU_CONFIG__CP_R4_CLNT_BEHAVIOR__SHIFT 0x00000010 +#define MH_MMU_CONFIG__VGT_R0_CLNT_BEHAVIOR__SHIFT 0x00000012 +#define MH_MMU_CONFIG__VGT_R1_CLNT_BEHAVIOR__SHIFT 0x00000014 +#define MH_MMU_CONFIG__TC_R_CLNT_BEHAVIOR__SHIFT 0x00000016 + +// MH_MMU_VA_RANGE +#define MH_MMU_VA_RANGE__NUM_64KB_REGIONS__SHIFT 0x00000000 +#define MH_MMU_VA_RANGE__VA_BASE__SHIFT 0x0000000c + +// MH_MMU_PT_BASE +#define MH_MMU_PT_BASE__PT_BASE__SHIFT 0x0000000c + +// MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT__PAGE_FAULT__SHIFT 0x00000000 +#define MH_MMU_PAGE_FAULT__OP_TYPE__SHIFT 0x00000001 +#define MH_MMU_PAGE_FAULT__CLNT_BEHAVIOR__SHIFT 0x00000002 +#define MH_MMU_PAGE_FAULT__AXI_ID__SHIFT 0x00000004 +#define MH_MMU_PAGE_FAULT__RESERVED1__SHIFT 0x00000007 +#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE__SHIFT 0x00000008 +#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE__SHIFT 0x00000009 +#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR__SHIFT 0x0000000a +#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR__SHIFT 0x0000000b +#define MH_MMU_PAGE_FAULT__REQ_VA__SHIFT 0x0000000c + +// MH_MMU_TRAN_ERROR +#define MH_MMU_TRAN_ERROR__TRAN_ERROR__SHIFT 0x00000005 + +// MH_MMU_INVALIDATE +#define MH_MMU_INVALIDATE__INVALIDATE_ALL__SHIFT 0x00000000 +#define MH_MMU_INVALIDATE__INVALIDATE_TC__SHIFT 0x00000001 + +// MH_MMU_MPU_BASE +#define MH_MMU_MPU_BASE__MPU_BASE__SHIFT 0x0000000c + +// MH_MMU_MPU_END +#define MH_MMU_MPU_END__MPU_END__SHIFT 0x0000000c + +// WAIT_UNTIL +#define WAIT_UNTIL__WAIT_RE_VSYNC__SHIFT 0x00000001 +#define WAIT_UNTIL__WAIT_FE_VSYNC__SHIFT 0x00000002 +#define WAIT_UNTIL__WAIT_VSYNC__SHIFT 0x00000003 +#define WAIT_UNTIL__WAIT_DSPLY_ID0__SHIFT 0x00000004 +#define WAIT_UNTIL__WAIT_DSPLY_ID1__SHIFT 0x00000005 +#define WAIT_UNTIL__WAIT_DSPLY_ID2__SHIFT 0x00000006 +#define WAIT_UNTIL__WAIT_CMDFIFO__SHIFT 0x0000000a +#define WAIT_UNTIL__WAIT_2D_IDLE__SHIFT 0x0000000e +#define WAIT_UNTIL__WAIT_3D_IDLE__SHIFT 0x0000000f +#define WAIT_UNTIL__WAIT_2D_IDLECLEAN__SHIFT 0x00000010 +#define WAIT_UNTIL__WAIT_3D_IDLECLEAN__SHIFT 0x00000011 +#define WAIT_UNTIL__CMDFIFO_ENTRIES__SHIFT 0x00000014 + +// RBBM_ISYNC_CNTL +#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI__SHIFT 0x00000004 +#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI__SHIFT 0x00000005 + +// RBBM_STATUS +#define RBBM_STATUS__CMDFIFO_AVAIL__SHIFT 0x00000000 +#define RBBM_STATUS__TC_BUSY__SHIFT 0x00000005 +#define RBBM_STATUS__HIRQ_PENDING__SHIFT 0x00000008 +#define RBBM_STATUS__CPRQ_PENDING__SHIFT 0x00000009 +#define RBBM_STATUS__CFRQ_PENDING__SHIFT 0x0000000a +#define RBBM_STATUS__PFRQ_PENDING__SHIFT 0x0000000b +#define RBBM_STATUS__VGT_BUSY_NO_DMA__SHIFT 0x0000000c +#define RBBM_STATUS__RBBM_WU_BUSY__SHIFT 0x0000000e +#define RBBM_STATUS__CP_NRT_BUSY__SHIFT 0x00000010 +#define RBBM_STATUS__MH_BUSY__SHIFT 0x00000012 +#define RBBM_STATUS__MH_COHERENCY_BUSY__SHIFT 0x00000013 +#define RBBM_STATUS__SX_BUSY__SHIFT 0x00000015 +#define RBBM_STATUS__TPC_BUSY__SHIFT 0x00000016 +#define RBBM_STATUS__SC_CNTX_BUSY__SHIFT 0x00000018 +#define RBBM_STATUS__PA_BUSY__SHIFT 0x00000019 +#define RBBM_STATUS__VGT_BUSY__SHIFT 0x0000001a +#define RBBM_STATUS__SQ_CNTX17_BUSY__SHIFT 0x0000001b +#define RBBM_STATUS__SQ_CNTX0_BUSY__SHIFT 0x0000001c +#define RBBM_STATUS__RB_CNTX_BUSY__SHIFT 0x0000001e +#define RBBM_STATUS__GUI_ACTIVE__SHIFT 0x0000001f + +// RBBM_DSPLY +#define RBBM_DSPLY__DISPLAY_ID0_ACTIVE__SHIFT 0x00000000 +#define RBBM_DSPLY__DISPLAY_ID1_ACTIVE__SHIFT 0x00000001 +#define RBBM_DSPLY__DISPLAY_ID2_ACTIVE__SHIFT 0x00000002 +#define RBBM_DSPLY__VSYNC_ACTIVE__SHIFT 0x00000003 +#define RBBM_DSPLY__USE_DISPLAY_ID0__SHIFT 0x00000004 +#define RBBM_DSPLY__USE_DISPLAY_ID1__SHIFT 0x00000005 +#define RBBM_DSPLY__USE_DISPLAY_ID2__SHIFT 0x00000006 +#define RBBM_DSPLY__SW_CNTL__SHIFT 0x00000007 +#define RBBM_DSPLY__NUM_BUFS__SHIFT 0x00000008 + +// RBBM_RENDER_LATEST +#define RBBM_RENDER_LATEST__BUFFER_ID__SHIFT 0x00000000 + +// RBBM_RTL_RELEASE +#define RBBM_RTL_RELEASE__CHANGELIST__SHIFT 0x00000000 + +// RBBM_PATCH_RELEASE +#define RBBM_PATCH_RELEASE__PATCH_REVISION__SHIFT 0x00000000 +#define RBBM_PATCH_RELEASE__PATCH_SELECTION__SHIFT 0x00000010 +#define RBBM_PATCH_RELEASE__CUSTOMER_ID__SHIFT 0x00000018 + +// RBBM_AUXILIARY_CONFIG +#define RBBM_AUXILIARY_CONFIG__RESERVED__SHIFT 0x00000000 + +// RBBM_PERIPHID0 +#define RBBM_PERIPHID0__PARTNUMBER0__SHIFT 0x00000000 + +// RBBM_PERIPHID1 +#define RBBM_PERIPHID1__PARTNUMBER1__SHIFT 0x00000000 +#define RBBM_PERIPHID1__DESIGNER0__SHIFT 0x00000004 + +// RBBM_PERIPHID2 +#define RBBM_PERIPHID2__DESIGNER1__SHIFT 0x00000000 +#define RBBM_PERIPHID2__REVISION__SHIFT 0x00000004 + +// RBBM_PERIPHID3 +#define RBBM_PERIPHID3__RBBM_HOST_INTERFACE__SHIFT 0x00000000 +#define RBBM_PERIPHID3__GARB_SLAVE_INTERFACE__SHIFT 0x00000002 +#define RBBM_PERIPHID3__MH_INTERFACE__SHIFT 0x00000004 +#define RBBM_PERIPHID3__CONTINUATION__SHIFT 0x00000007 + +// RBBM_CNTL +#define RBBM_CNTL__READ_TIMEOUT__SHIFT 0x00000000 +#define RBBM_CNTL__REGCLK_DEASSERT_TIME__SHIFT 0x00000008 + +// RBBM_SKEW_CNTL +#define RBBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x00000000 +#define RBBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x00000005 + +// RBBM_SOFT_RESET +#define RBBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x00000000 +#define RBBM_SOFT_RESET__SOFT_RESET_PA__SHIFT 0x00000002 +#define RBBM_SOFT_RESET__SOFT_RESET_MH__SHIFT 0x00000003 +#define RBBM_SOFT_RESET__SOFT_RESET_BC__SHIFT 0x00000004 +#define RBBM_SOFT_RESET__SOFT_RESET_SQ__SHIFT 0x00000005 +#define RBBM_SOFT_RESET__SOFT_RESET_SX__SHIFT 0x00000006 +#define RBBM_SOFT_RESET__SOFT_RESET_CIB__SHIFT 0x0000000c +#define RBBM_SOFT_RESET__SOFT_RESET_SC__SHIFT 0x0000000f +#define RBBM_SOFT_RESET__SOFT_RESET_VGT__SHIFT 0x00000010 + +// RBBM_PM_OVERRIDE1 +#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE__SHIFT 0x00000000 +#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000001 +#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE__SHIFT 0x00000002 +#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE__SHIFT 0x00000003 +#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE__SHIFT 0x00000004 +#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000005 +#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE__SHIFT 0x00000006 +#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE__SHIFT 0x00000007 +#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE__SHIFT 0x00000008 +#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE__SHIFT 0x00000009 +#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000000a +#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE__SHIFT 0x0000000b +#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE__SHIFT 0x0000000c +#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE__SHIFT 0x0000000d +#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000000e +#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE__SHIFT 0x0000000f +#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000010 +#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE__SHIFT 0x00000011 +#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE__SHIFT 0x00000012 +#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE__SHIFT 0x00000013 +#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE__SHIFT 0x00000014 +#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000015 +#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE__SHIFT 0x00000016 +#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000017 +#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000018 +#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE__SHIFT 0x00000019 +#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000001a +#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE__SHIFT 0x0000001b +#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE__SHIFT 0x0000001c +#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000001d +#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE__SHIFT 0x0000001e +#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE__SHIFT 0x0000001f + +// RBBM_PM_OVERRIDE2 +#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000000 +#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE__SHIFT 0x00000001 +#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE__SHIFT 0x00000002 +#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000003 +#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE__SHIFT 0x00000004 +#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE__SHIFT 0x00000005 +#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE__SHIFT 0x00000006 +#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE__SHIFT 0x00000007 +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE__SHIFT 0x00000008 +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE__SHIFT 0x00000009 +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE__SHIFT 0x0000000a +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE__SHIFT 0x0000000b + +// GC_SYS_IDLE +#define GC_SYS_IDLE__GC_SYS_IDLE_DELAY__SHIFT 0x00000000 +#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE__SHIFT 0x0000001f + +// NQWAIT_UNTIL +#define NQWAIT_UNTIL__WAIT_GUI_IDLE__SHIFT 0x00000000 + +// RBBM_DEBUG +#define RBBM_DEBUG__IGNORE_RTR__SHIFT 0x00000001 +#define RBBM_DEBUG__IGNORE_CP_SCHED_WU__SHIFT 0x00000002 +#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC__SHIFT 0x00000003 +#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI__SHIFT 0x00000004 +#define RBBM_DEBUG__HYSTERESIS_NRT_GUI_ACTIVE__SHIFT 0x00000008 +#define RBBM_DEBUG__IGNORE_RTR_FOR_HI__SHIFT 0x00000010 +#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI__SHIFT 0x00000011 +#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI__SHIFT 0x00000012 +#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI__SHIFT 0x00000013 +#define RBBM_DEBUG__CP_RBBM_NRTRTR__SHIFT 0x00000014 +#define RBBM_DEBUG__VGT_RBBM_NRTRTR__SHIFT 0x00000015 +#define RBBM_DEBUG__SQ_RBBM_NRTRTR__SHIFT 0x00000016 +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI__SHIFT 0x00000017 +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR__SHIFT 0x00000018 +#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY__SHIFT 0x0000001f + +// RBBM_READ_ERROR +#define RBBM_READ_ERROR__READ_ADDRESS__SHIFT 0x00000002 +#define RBBM_READ_ERROR__READ_REQUESTER__SHIFT 0x0000001e +#define RBBM_READ_ERROR__READ_ERROR__SHIFT 0x0000001f + +// RBBM_WAIT_IDLE_CLOCKS +#define RBBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_NRT__SHIFT 0x00000000 + +// RBBM_INT_CNTL +#define RBBM_INT_CNTL__RDERR_INT_MASK__SHIFT 0x00000000 +#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK__SHIFT 0x00000001 +#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK__SHIFT 0x00000013 + +// RBBM_INT_STATUS +#define RBBM_INT_STATUS__RDERR_INT_STAT__SHIFT 0x00000000 +#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT__SHIFT 0x00000001 +#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT__SHIFT 0x00000013 + +// RBBM_INT_ACK +#define RBBM_INT_ACK__RDERR_INT_ACK__SHIFT 0x00000000 +#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK__SHIFT 0x00000001 +#define RBBM_INT_ACK__GUI_IDLE_INT_ACK__SHIFT 0x00000013 + +// MASTER_INT_SIGNAL +#define MASTER_INT_SIGNAL__MH_INT_STAT__SHIFT 0x00000005 +#define MASTER_INT_SIGNAL__CP_INT_STAT__SHIFT 0x0000001e +#define MASTER_INT_SIGNAL__RBBM_INT_STAT__SHIFT 0x0000001f + +// RBBM_PERFCOUNTER1_SELECT +#define RBBM_PERFCOUNTER1_SELECT__PERF_COUNT1_SEL__SHIFT 0x00000000 + +// RBBM_PERFCOUNTER1_LO +#define RBBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT 0x00000000 + +// RBBM_PERFCOUNTER1_HI +#define RBBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT 0x00000000 + +// CP_RB_BASE +#define CP_RB_BASE__RB_BASE__SHIFT 0x00000005 + +// CP_RB_CNTL +#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x00000000 +#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x00000008 +#define CP_RB_CNTL__BUF_SWAP__SHIFT 0x00000010 +#define CP_RB_CNTL__RB_POLL_EN__SHIFT 0x00000014 +#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b +#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x0000001f + +// CP_RB_RPTR_ADDR +#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x00000000 +#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000002 + +// CP_RB_RPTR +#define CP_RB_RPTR__RB_RPTR__SHIFT 0x00000000 + +// CP_RB_RPTR_WR +#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x00000000 + +// CP_RB_WPTR +#define CP_RB_WPTR__RB_WPTR__SHIFT 0x00000000 + +// CP_RB_WPTR_DELAY +#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x00000000 +#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x0000001c + +// CP_RB_WPTR_BASE +#define CP_RB_WPTR_BASE__RB_WPTR_SWAP__SHIFT 0x00000000 +#define CP_RB_WPTR_BASE__RB_WPTR_BASE__SHIFT 0x00000002 + +// CP_IB1_BASE +#define CP_IB1_BASE__IB1_BASE__SHIFT 0x00000002 + +// CP_IB1_BUFSZ +#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x00000000 + +// CP_IB2_BASE +#define CP_IB2_BASE__IB2_BASE__SHIFT 0x00000002 + +// CP_IB2_BUFSZ +#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x00000000 + +// CP_ST_BASE +#define CP_ST_BASE__ST_BASE__SHIFT 0x00000002 + +// CP_ST_BUFSZ +#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x00000000 + +// CP_QUEUE_THRESHOLDS +#define CP_QUEUE_THRESHOLDS__CSQ_IB1_START__SHIFT 0x00000000 +#define CP_QUEUE_THRESHOLDS__CSQ_IB2_START__SHIFT 0x00000008 +#define CP_QUEUE_THRESHOLDS__CSQ_ST_START__SHIFT 0x00000010 + +// CP_MEQ_THRESHOLDS +#define CP_MEQ_THRESHOLDS__MEQ_END__SHIFT 0x00000010 +#define CP_MEQ_THRESHOLDS__ROQ_END__SHIFT 0x00000018 + +// CP_CSQ_AVAIL +#define CP_CSQ_AVAIL__CSQ_CNT_RING__SHIFT 0x00000000 +#define CP_CSQ_AVAIL__CSQ_CNT_IB1__SHIFT 0x00000008 +#define CP_CSQ_AVAIL__CSQ_CNT_IB2__SHIFT 0x00000010 + +// CP_STQ_AVAIL +#define CP_STQ_AVAIL__STQ_CNT_ST__SHIFT 0x00000000 + +// CP_MEQ_AVAIL +#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x00000000 + +// CP_CSQ_RB_STAT +#define CP_CSQ_RB_STAT__CSQ_RPTR_PRIMARY__SHIFT 0x00000000 +#define CP_CSQ_RB_STAT__CSQ_WPTR_PRIMARY__SHIFT 0x00000010 + +// CP_CSQ_IB1_STAT +#define CP_CSQ_IB1_STAT__CSQ_RPTR_INDIRECT1__SHIFT 0x00000000 +#define CP_CSQ_IB1_STAT__CSQ_WPTR_INDIRECT1__SHIFT 0x00000010 + +// CP_CSQ_IB2_STAT +#define CP_CSQ_IB2_STAT__CSQ_RPTR_INDIRECT2__SHIFT 0x00000000 +#define CP_CSQ_IB2_STAT__CSQ_WPTR_INDIRECT2__SHIFT 0x00000010 + +// CP_NON_PREFETCH_CNTRS +#define CP_NON_PREFETCH_CNTRS__IB1_COUNTER__SHIFT 0x00000000 +#define CP_NON_PREFETCH_CNTRS__IB2_COUNTER__SHIFT 0x00000008 + +// CP_STQ_ST_STAT +#define CP_STQ_ST_STAT__STQ_RPTR_ST__SHIFT 0x00000000 +#define CP_STQ_ST_STAT__STQ_WPTR_ST__SHIFT 0x00000010 + +// CP_MEQ_STAT +#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x00000000 +#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x00000010 + +// CP_MIU_TAG_STAT +#define CP_MIU_TAG_STAT__TAG_0_STAT__SHIFT 0x00000000 +#define CP_MIU_TAG_STAT__TAG_1_STAT__SHIFT 0x00000001 +#define CP_MIU_TAG_STAT__TAG_2_STAT__SHIFT 0x00000002 +#define CP_MIU_TAG_STAT__TAG_3_STAT__SHIFT 0x00000003 +#define CP_MIU_TAG_STAT__TAG_4_STAT__SHIFT 0x00000004 +#define CP_MIU_TAG_STAT__TAG_5_STAT__SHIFT 0x00000005 +#define CP_MIU_TAG_STAT__TAG_6_STAT__SHIFT 0x00000006 +#define CP_MIU_TAG_STAT__TAG_7_STAT__SHIFT 0x00000007 +#define CP_MIU_TAG_STAT__TAG_8_STAT__SHIFT 0x00000008 +#define CP_MIU_TAG_STAT__TAG_9_STAT__SHIFT 0x00000009 +#define CP_MIU_TAG_STAT__TAG_10_STAT__SHIFT 0x0000000a +#define CP_MIU_TAG_STAT__TAG_11_STAT__SHIFT 0x0000000b +#define CP_MIU_TAG_STAT__TAG_12_STAT__SHIFT 0x0000000c +#define CP_MIU_TAG_STAT__TAG_13_STAT__SHIFT 0x0000000d +#define CP_MIU_TAG_STAT__TAG_14_STAT__SHIFT 0x0000000e +#define CP_MIU_TAG_STAT__TAG_15_STAT__SHIFT 0x0000000f +#define CP_MIU_TAG_STAT__TAG_16_STAT__SHIFT 0x00000010 +#define CP_MIU_TAG_STAT__TAG_17_STAT__SHIFT 0x00000011 +#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG__SHIFT 0x0000001f + +// CP_CMD_INDEX +#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x00000000 +#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x00000010 + +// CP_CMD_DATA +#define CP_CMD_DATA__CMD_DATA__SHIFT 0x00000000 + +// CP_ME_CNTL +#define CP_ME_CNTL__ME_STATMUX__SHIFT 0x00000000 +#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY__SHIFT 0x00000019 +#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY__SHIFT 0x0000001a +#define CP_ME_CNTL__ME_HALT__SHIFT 0x0000001c +#define CP_ME_CNTL__ME_BUSY__SHIFT 0x0000001d +#define CP_ME_CNTL__PROG_CNT_SIZE__SHIFT 0x0000001f + +// CP_ME_STATUS +#define CP_ME_STATUS__ME_DEBUG_DATA__SHIFT 0x00000000 + +// CP_ME_RAM_WADDR +#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x00000000 + +// CP_ME_RAM_RADDR +#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x00000000 + +// CP_ME_RAM_DATA +#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x00000000 + +// CP_ME_RDADDR +#define CP_ME_RDADDR__ME_RDADDR__SHIFT 0x00000000 + +// CP_DEBUG +#define CP_DEBUG__CP_DEBUG_UNUSED_22_to_0__SHIFT 0x00000000 +#define CP_DEBUG__PREDICATE_DISABLE__SHIFT 0x00000017 +#define CP_DEBUG__PROG_END_PTR_ENABLE__SHIFT 0x00000018 +#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE__SHIFT 0x00000019 +#define CP_DEBUG__PREFETCH_PASS_NOPS__SHIFT 0x0000001a +#define CP_DEBUG__DYNAMIC_CLK_DISABLE__SHIFT 0x0000001b +#define CP_DEBUG__PREFETCH_MATCH_DISABLE__SHIFT 0x0000001c +#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL__SHIFT 0x0000001e +#define CP_DEBUG__MIU_WRITE_PACK_DISABLE__SHIFT 0x0000001f + +// SCRATCH_REG0 +#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x00000000 +#define GUI_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x00000000 + +// SCRATCH_REG1 +#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x00000000 +#define GUI_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x00000000 + +// SCRATCH_REG2 +#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x00000000 +#define GUI_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x00000000 + +// SCRATCH_REG3 +#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x00000000 +#define GUI_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x00000000 + +// SCRATCH_REG4 +#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x00000000 +#define GUI_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x00000000 + +// SCRATCH_REG5 +#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x00000000 +#define GUI_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x00000000 + +// SCRATCH_REG6 +#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x00000000 +#define GUI_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x00000000 + +// SCRATCH_REG7 +#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x00000000 +#define GUI_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x00000000 + +// SCRATCH_UMSK +#define SCRATCH_UMSK__SCRATCH_UMSK__SHIFT 0x00000000 +#define SCRATCH_UMSK__SCRATCH_SWAP__SHIFT 0x00000010 + +// SCRATCH_ADDR +#define SCRATCH_ADDR__SCRATCH_ADDR__SHIFT 0x00000005 + +// CP_ME_VS_EVENT_SRC +#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM__SHIFT 0x00000000 +#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR__SHIFT 0x00000001 + +// CP_ME_VS_EVENT_ADDR +#define CP_ME_VS_EVENT_ADDR__VS_DONE_SWAP__SHIFT 0x00000000 +#define CP_ME_VS_EVENT_ADDR__VS_DONE_ADDR__SHIFT 0x00000002 + +// CP_ME_VS_EVENT_DATA +#define CP_ME_VS_EVENT_DATA__VS_DONE_DATA__SHIFT 0x00000000 + +// CP_ME_VS_EVENT_ADDR_SWM +#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_SWAP_SWM__SHIFT 0x00000000 +#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_ADDR_SWM__SHIFT 0x00000002 + +// CP_ME_VS_EVENT_DATA_SWM +#define CP_ME_VS_EVENT_DATA_SWM__VS_DONE_DATA_SWM__SHIFT 0x00000000 + +// CP_ME_PS_EVENT_SRC +#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM__SHIFT 0x00000000 +#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR__SHIFT 0x00000001 + +// CP_ME_PS_EVENT_ADDR +#define CP_ME_PS_EVENT_ADDR__PS_DONE_SWAP__SHIFT 0x00000000 +#define CP_ME_PS_EVENT_ADDR__PS_DONE_ADDR__SHIFT 0x00000002 + +// CP_ME_PS_EVENT_DATA +#define CP_ME_PS_EVENT_DATA__PS_DONE_DATA__SHIFT 0x00000000 + +// CP_ME_PS_EVENT_ADDR_SWM +#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_SWAP_SWM__SHIFT 0x00000000 +#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_ADDR_SWM__SHIFT 0x00000002 + +// CP_ME_PS_EVENT_DATA_SWM +#define CP_ME_PS_EVENT_DATA_SWM__PS_DONE_DATA_SWM__SHIFT 0x00000000 + +// CP_ME_CF_EVENT_SRC +#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC__SHIFT 0x00000000 + +// CP_ME_CF_EVENT_ADDR +#define CP_ME_CF_EVENT_ADDR__CF_DONE_SWAP__SHIFT 0x00000000 +#define CP_ME_CF_EVENT_ADDR__CF_DONE_ADDR__SHIFT 0x00000002 + +// CP_ME_CF_EVENT_DATA +#define CP_ME_CF_EVENT_DATA__CF_DONE_DATA__SHIFT 0x00000000 + +// CP_ME_NRT_ADDR +#define CP_ME_NRT_ADDR__NRT_WRITE_SWAP__SHIFT 0x00000000 +#define CP_ME_NRT_ADDR__NRT_WRITE_ADDR__SHIFT 0x00000002 + +// CP_ME_NRT_DATA +#define CP_ME_NRT_DATA__NRT_WRITE_DATA__SHIFT 0x00000000 + +// CP_ME_VS_FETCH_DONE_SRC +#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR__SHIFT 0x00000000 + +// CP_ME_VS_FETCH_DONE_ADDR +#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_SWAP__SHIFT 0x00000000 +#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_ADDR__SHIFT 0x00000002 + +// CP_ME_VS_FETCH_DONE_DATA +#define CP_ME_VS_FETCH_DONE_DATA__VS_FETCH_DONE_DATA__SHIFT 0x00000000 + +// CP_INT_CNTL +#define CP_INT_CNTL__SW_INT_MASK__SHIFT 0x00000013 +#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK__SHIFT 0x00000017 +#define CP_INT_CNTL__OPCODE_ERROR_MASK__SHIFT 0x00000018 +#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK__SHIFT 0x00000019 +#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK__SHIFT 0x0000001a +#define CP_INT_CNTL__IB_ERROR_MASK__SHIFT 0x0000001b +#define CP_INT_CNTL__IB2_INT_MASK__SHIFT 0x0000001d +#define CP_INT_CNTL__IB1_INT_MASK__SHIFT 0x0000001e +#define CP_INT_CNTL__RB_INT_MASK__SHIFT 0x0000001f + +// CP_INT_STATUS +#define CP_INT_STATUS__SW_INT_STAT__SHIFT 0x00000013 +#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT__SHIFT 0x00000017 +#define CP_INT_STATUS__OPCODE_ERROR_STAT__SHIFT 0x00000018 +#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT__SHIFT 0x00000019 +#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT__SHIFT 0x0000001a +#define CP_INT_STATUS__IB_ERROR_STAT__SHIFT 0x0000001b +#define CP_INT_STATUS__IB2_INT_STAT__SHIFT 0x0000001d +#define CP_INT_STATUS__IB1_INT_STAT__SHIFT 0x0000001e +#define CP_INT_STATUS__RB_INT_STAT__SHIFT 0x0000001f + +// CP_INT_ACK +#define CP_INT_ACK__SW_INT_ACK__SHIFT 0x00000013 +#define CP_INT_ACK__T0_PACKET_IN_IB_ACK__SHIFT 0x00000017 +#define CP_INT_ACK__OPCODE_ERROR_ACK__SHIFT 0x00000018 +#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK__SHIFT 0x00000019 +#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK__SHIFT 0x0000001a +#define CP_INT_ACK__IB_ERROR_ACK__SHIFT 0x0000001b +#define CP_INT_ACK__IB2_INT_ACK__SHIFT 0x0000001d +#define CP_INT_ACK__IB1_INT_ACK__SHIFT 0x0000001e +#define CP_INT_ACK__RB_INT_ACK__SHIFT 0x0000001f + +// CP_PFP_UCODE_ADDR +#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x00000000 + +// CP_PFP_UCODE_DATA +#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x00000000 + +// CP_PERFMON_CNTL +#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x00000000 +#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x00000008 + +// CP_PERFCOUNTER_SELECT +#define CP_PERFCOUNTER_SELECT__PERFCOUNT_SEL__SHIFT 0x00000000 + +// CP_PERFCOUNTER_LO +#define CP_PERFCOUNTER_LO__PERFCOUNT_LO__SHIFT 0x00000000 + +// CP_PERFCOUNTER_HI +#define CP_PERFCOUNTER_HI__PERFCOUNT_HI__SHIFT 0x00000000 + +// CP_BIN_MASK_LO +#define CP_BIN_MASK_LO__BIN_MASK_LO__SHIFT 0x00000000 + +// CP_BIN_MASK_HI +#define CP_BIN_MASK_HI__BIN_MASK_HI__SHIFT 0x00000000 + +// CP_BIN_SELECT_LO +#define CP_BIN_SELECT_LO__BIN_SELECT_LO__SHIFT 0x00000000 + +// CP_BIN_SELECT_HI +#define CP_BIN_SELECT_HI__BIN_SELECT_HI__SHIFT 0x00000000 + +// CP_NV_FLAGS_0 +#define CP_NV_FLAGS_0__DISCARD_0__SHIFT 0x00000000 +#define CP_NV_FLAGS_0__END_RCVD_0__SHIFT 0x00000001 +#define CP_NV_FLAGS_0__DISCARD_1__SHIFT 0x00000002 +#define CP_NV_FLAGS_0__END_RCVD_1__SHIFT 0x00000003 +#define CP_NV_FLAGS_0__DISCARD_2__SHIFT 0x00000004 +#define CP_NV_FLAGS_0__END_RCVD_2__SHIFT 0x00000005 +#define CP_NV_FLAGS_0__DISCARD_3__SHIFT 0x00000006 +#define CP_NV_FLAGS_0__END_RCVD_3__SHIFT 0x00000007 +#define CP_NV_FLAGS_0__DISCARD_4__SHIFT 0x00000008 +#define CP_NV_FLAGS_0__END_RCVD_4__SHIFT 0x00000009 +#define CP_NV_FLAGS_0__DISCARD_5__SHIFT 0x0000000a +#define CP_NV_FLAGS_0__END_RCVD_5__SHIFT 0x0000000b +#define CP_NV_FLAGS_0__DISCARD_6__SHIFT 0x0000000c +#define CP_NV_FLAGS_0__END_RCVD_6__SHIFT 0x0000000d +#define CP_NV_FLAGS_0__DISCARD_7__SHIFT 0x0000000e +#define CP_NV_FLAGS_0__END_RCVD_7__SHIFT 0x0000000f +#define CP_NV_FLAGS_0__DISCARD_8__SHIFT 0x00000010 +#define CP_NV_FLAGS_0__END_RCVD_8__SHIFT 0x00000011 +#define CP_NV_FLAGS_0__DISCARD_9__SHIFT 0x00000012 +#define CP_NV_FLAGS_0__END_RCVD_9__SHIFT 0x00000013 +#define CP_NV_FLAGS_0__DISCARD_10__SHIFT 0x00000014 +#define CP_NV_FLAGS_0__END_RCVD_10__SHIFT 0x00000015 +#define CP_NV_FLAGS_0__DISCARD_11__SHIFT 0x00000016 +#define CP_NV_FLAGS_0__END_RCVD_11__SHIFT 0x00000017 +#define CP_NV_FLAGS_0__DISCARD_12__SHIFT 0x00000018 +#define CP_NV_FLAGS_0__END_RCVD_12__SHIFT 0x00000019 +#define CP_NV_FLAGS_0__DISCARD_13__SHIFT 0x0000001a +#define CP_NV_FLAGS_0__END_RCVD_13__SHIFT 0x0000001b +#define CP_NV_FLAGS_0__DISCARD_14__SHIFT 0x0000001c +#define CP_NV_FLAGS_0__END_RCVD_14__SHIFT 0x0000001d +#define CP_NV_FLAGS_0__DISCARD_15__SHIFT 0x0000001e +#define CP_NV_FLAGS_0__END_RCVD_15__SHIFT 0x0000001f + +// CP_NV_FLAGS_1 +#define CP_NV_FLAGS_1__DISCARD_16__SHIFT 0x00000000 +#define CP_NV_FLAGS_1__END_RCVD_16__SHIFT 0x00000001 +#define CP_NV_FLAGS_1__DISCARD_17__SHIFT 0x00000002 +#define CP_NV_FLAGS_1__END_RCVD_17__SHIFT 0x00000003 +#define CP_NV_FLAGS_1__DISCARD_18__SHIFT 0x00000004 +#define CP_NV_FLAGS_1__END_RCVD_18__SHIFT 0x00000005 +#define CP_NV_FLAGS_1__DISCARD_19__SHIFT 0x00000006 +#define CP_NV_FLAGS_1__END_RCVD_19__SHIFT 0x00000007 +#define CP_NV_FLAGS_1__DISCARD_20__SHIFT 0x00000008 +#define CP_NV_FLAGS_1__END_RCVD_20__SHIFT 0x00000009 +#define CP_NV_FLAGS_1__DISCARD_21__SHIFT 0x0000000a +#define CP_NV_FLAGS_1__END_RCVD_21__SHIFT 0x0000000b +#define CP_NV_FLAGS_1__DISCARD_22__SHIFT 0x0000000c +#define CP_NV_FLAGS_1__END_RCVD_22__SHIFT 0x0000000d +#define CP_NV_FLAGS_1__DISCARD_23__SHIFT 0x0000000e +#define CP_NV_FLAGS_1__END_RCVD_23__SHIFT 0x0000000f +#define CP_NV_FLAGS_1__DISCARD_24__SHIFT 0x00000010 +#define CP_NV_FLAGS_1__END_RCVD_24__SHIFT 0x00000011 +#define CP_NV_FLAGS_1__DISCARD_25__SHIFT 0x00000012 +#define CP_NV_FLAGS_1__END_RCVD_25__SHIFT 0x00000013 +#define CP_NV_FLAGS_1__DISCARD_26__SHIFT 0x00000014 +#define CP_NV_FLAGS_1__END_RCVD_26__SHIFT 0x00000015 +#define CP_NV_FLAGS_1__DISCARD_27__SHIFT 0x00000016 +#define CP_NV_FLAGS_1__END_RCVD_27__SHIFT 0x00000017 +#define CP_NV_FLAGS_1__DISCARD_28__SHIFT 0x00000018 +#define CP_NV_FLAGS_1__END_RCVD_28__SHIFT 0x00000019 +#define CP_NV_FLAGS_1__DISCARD_29__SHIFT 0x0000001a +#define CP_NV_FLAGS_1__END_RCVD_29__SHIFT 0x0000001b +#define CP_NV_FLAGS_1__DISCARD_30__SHIFT 0x0000001c +#define CP_NV_FLAGS_1__END_RCVD_30__SHIFT 0x0000001d +#define CP_NV_FLAGS_1__DISCARD_31__SHIFT 0x0000001e +#define CP_NV_FLAGS_1__END_RCVD_31__SHIFT 0x0000001f + +// CP_NV_FLAGS_2 +#define CP_NV_FLAGS_2__DISCARD_32__SHIFT 0x00000000 +#define CP_NV_FLAGS_2__END_RCVD_32__SHIFT 0x00000001 +#define CP_NV_FLAGS_2__DISCARD_33__SHIFT 0x00000002 +#define CP_NV_FLAGS_2__END_RCVD_33__SHIFT 0x00000003 +#define CP_NV_FLAGS_2__DISCARD_34__SHIFT 0x00000004 +#define CP_NV_FLAGS_2__END_RCVD_34__SHIFT 0x00000005 +#define CP_NV_FLAGS_2__DISCARD_35__SHIFT 0x00000006 +#define CP_NV_FLAGS_2__END_RCVD_35__SHIFT 0x00000007 +#define CP_NV_FLAGS_2__DISCARD_36__SHIFT 0x00000008 +#define CP_NV_FLAGS_2__END_RCVD_36__SHIFT 0x00000009 +#define CP_NV_FLAGS_2__DISCARD_37__SHIFT 0x0000000a +#define CP_NV_FLAGS_2__END_RCVD_37__SHIFT 0x0000000b +#define CP_NV_FLAGS_2__DISCARD_38__SHIFT 0x0000000c +#define CP_NV_FLAGS_2__END_RCVD_38__SHIFT 0x0000000d +#define CP_NV_FLAGS_2__DISCARD_39__SHIFT 0x0000000e +#define CP_NV_FLAGS_2__END_RCVD_39__SHIFT 0x0000000f +#define CP_NV_FLAGS_2__DISCARD_40__SHIFT 0x00000010 +#define CP_NV_FLAGS_2__END_RCVD_40__SHIFT 0x00000011 +#define CP_NV_FLAGS_2__DISCARD_41__SHIFT 0x00000012 +#define CP_NV_FLAGS_2__END_RCVD_41__SHIFT 0x00000013 +#define CP_NV_FLAGS_2__DISCARD_42__SHIFT 0x00000014 +#define CP_NV_FLAGS_2__END_RCVD_42__SHIFT 0x00000015 +#define CP_NV_FLAGS_2__DISCARD_43__SHIFT 0x00000016 +#define CP_NV_FLAGS_2__END_RCVD_43__SHIFT 0x00000017 +#define CP_NV_FLAGS_2__DISCARD_44__SHIFT 0x00000018 +#define CP_NV_FLAGS_2__END_RCVD_44__SHIFT 0x00000019 +#define CP_NV_FLAGS_2__DISCARD_45__SHIFT 0x0000001a +#define CP_NV_FLAGS_2__END_RCVD_45__SHIFT 0x0000001b +#define CP_NV_FLAGS_2__DISCARD_46__SHIFT 0x0000001c +#define CP_NV_FLAGS_2__END_RCVD_46__SHIFT 0x0000001d +#define CP_NV_FLAGS_2__DISCARD_47__SHIFT 0x0000001e +#define CP_NV_FLAGS_2__END_RCVD_47__SHIFT 0x0000001f + +// CP_NV_FLAGS_3 +#define CP_NV_FLAGS_3__DISCARD_48__SHIFT 0x00000000 +#define CP_NV_FLAGS_3__END_RCVD_48__SHIFT 0x00000001 +#define CP_NV_FLAGS_3__DISCARD_49__SHIFT 0x00000002 +#define CP_NV_FLAGS_3__END_RCVD_49__SHIFT 0x00000003 +#define CP_NV_FLAGS_3__DISCARD_50__SHIFT 0x00000004 +#define CP_NV_FLAGS_3__END_RCVD_50__SHIFT 0x00000005 +#define CP_NV_FLAGS_3__DISCARD_51__SHIFT 0x00000006 +#define CP_NV_FLAGS_3__END_RCVD_51__SHIFT 0x00000007 +#define CP_NV_FLAGS_3__DISCARD_52__SHIFT 0x00000008 +#define CP_NV_FLAGS_3__END_RCVD_52__SHIFT 0x00000009 +#define CP_NV_FLAGS_3__DISCARD_53__SHIFT 0x0000000a +#define CP_NV_FLAGS_3__END_RCVD_53__SHIFT 0x0000000b +#define CP_NV_FLAGS_3__DISCARD_54__SHIFT 0x0000000c +#define CP_NV_FLAGS_3__END_RCVD_54__SHIFT 0x0000000d +#define CP_NV_FLAGS_3__DISCARD_55__SHIFT 0x0000000e +#define CP_NV_FLAGS_3__END_RCVD_55__SHIFT 0x0000000f +#define CP_NV_FLAGS_3__DISCARD_56__SHIFT 0x00000010 +#define CP_NV_FLAGS_3__END_RCVD_56__SHIFT 0x00000011 +#define CP_NV_FLAGS_3__DISCARD_57__SHIFT 0x00000012 +#define CP_NV_FLAGS_3__END_RCVD_57__SHIFT 0x00000013 +#define CP_NV_FLAGS_3__DISCARD_58__SHIFT 0x00000014 +#define CP_NV_FLAGS_3__END_RCVD_58__SHIFT 0x00000015 +#define CP_NV_FLAGS_3__DISCARD_59__SHIFT 0x00000016 +#define CP_NV_FLAGS_3__END_RCVD_59__SHIFT 0x00000017 +#define CP_NV_FLAGS_3__DISCARD_60__SHIFT 0x00000018 +#define CP_NV_FLAGS_3__END_RCVD_60__SHIFT 0x00000019 +#define CP_NV_FLAGS_3__DISCARD_61__SHIFT 0x0000001a +#define CP_NV_FLAGS_3__END_RCVD_61__SHIFT 0x0000001b +#define CP_NV_FLAGS_3__DISCARD_62__SHIFT 0x0000001c +#define CP_NV_FLAGS_3__END_RCVD_62__SHIFT 0x0000001d +#define CP_NV_FLAGS_3__DISCARD_63__SHIFT 0x0000001e +#define CP_NV_FLAGS_3__END_RCVD_63__SHIFT 0x0000001f + +// CP_STATE_DEBUG_INDEX +#define CP_STATE_DEBUG_INDEX__STATE_DEBUG_INDEX__SHIFT 0x00000000 + +// CP_STATE_DEBUG_DATA +#define CP_STATE_DEBUG_DATA__STATE_DEBUG_DATA__SHIFT 0x00000000 + +// CP_PROG_COUNTER +#define CP_PROG_COUNTER__COUNTER__SHIFT 0x00000000 + +// CP_STAT +#define CP_STAT__MIU_WR_BUSY__SHIFT 0x00000000 +#define CP_STAT__MIU_RD_REQ_BUSY__SHIFT 0x00000001 +#define CP_STAT__MIU_RD_RETURN_BUSY__SHIFT 0x00000002 +#define CP_STAT__RBIU_BUSY__SHIFT 0x00000003 +#define CP_STAT__RCIU_BUSY__SHIFT 0x00000004 +#define CP_STAT__CSF_RING_BUSY__SHIFT 0x00000005 +#define CP_STAT__CSF_INDIRECTS_BUSY__SHIFT 0x00000006 +#define CP_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x00000007 +#define CP_STAT__CSF_ST_BUSY__SHIFT 0x00000009 +#define CP_STAT__CSF_BUSY__SHIFT 0x0000000a +#define CP_STAT__RING_QUEUE_BUSY__SHIFT 0x0000000b +#define CP_STAT__INDIRECTS_QUEUE_BUSY__SHIFT 0x0000000c +#define CP_STAT__INDIRECT2_QUEUE_BUSY__SHIFT 0x0000000d +#define CP_STAT__ST_QUEUE_BUSY__SHIFT 0x00000010 +#define CP_STAT__PFP_BUSY__SHIFT 0x00000011 +#define CP_STAT__MEQ_RING_BUSY__SHIFT 0x00000012 +#define CP_STAT__MEQ_INDIRECTS_BUSY__SHIFT 0x00000013 +#define CP_STAT__MEQ_INDIRECT2_BUSY__SHIFT 0x00000014 +#define CP_STAT__MIU_WC_STALL__SHIFT 0x00000015 +#define CP_STAT__CP_NRT_BUSY__SHIFT 0x00000016 +#define CP_STAT___3D_BUSY__SHIFT 0x00000017 +#define CP_STAT__ME_BUSY__SHIFT 0x0000001a +#define CP_STAT__ME_WC_BUSY__SHIFT 0x0000001d +#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY__SHIFT 0x0000001e +#define CP_STAT__CP_BUSY__SHIFT 0x0000001f + +// BIOS_0_SCRATCH +#define BIOS_0_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_1_SCRATCH +#define BIOS_1_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_2_SCRATCH +#define BIOS_2_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_3_SCRATCH +#define BIOS_3_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_4_SCRATCH +#define BIOS_4_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_5_SCRATCH +#define BIOS_5_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_6_SCRATCH +#define BIOS_6_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_7_SCRATCH +#define BIOS_7_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_8_SCRATCH +#define BIOS_8_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_9_SCRATCH +#define BIOS_9_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_10_SCRATCH +#define BIOS_10_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_11_SCRATCH +#define BIOS_11_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_12_SCRATCH +#define BIOS_12_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_13_SCRATCH +#define BIOS_13_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_14_SCRATCH +#define BIOS_14_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_15_SCRATCH +#define BIOS_15_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// COHER_SIZE_PM4 +#define COHER_SIZE_PM4__SIZE__SHIFT 0x00000000 + +// COHER_BASE_PM4 +#define COHER_BASE_PM4__BASE__SHIFT 0x00000000 + +// COHER_STATUS_PM4 +#define COHER_STATUS_PM4__MATCHING_CONTEXTS__SHIFT 0x00000000 +#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA__SHIFT 0x00000008 +#define COHER_STATUS_PM4__DEST_BASE_0_ENA__SHIFT 0x00000009 +#define COHER_STATUS_PM4__DEST_BASE_1_ENA__SHIFT 0x0000000a +#define COHER_STATUS_PM4__DEST_BASE_2_ENA__SHIFT 0x0000000b +#define COHER_STATUS_PM4__DEST_BASE_3_ENA__SHIFT 0x0000000c +#define COHER_STATUS_PM4__DEST_BASE_4_ENA__SHIFT 0x0000000d +#define COHER_STATUS_PM4__DEST_BASE_5_ENA__SHIFT 0x0000000e +#define COHER_STATUS_PM4__DEST_BASE_6_ENA__SHIFT 0x0000000f +#define COHER_STATUS_PM4__DEST_BASE_7_ENA__SHIFT 0x00000010 +#define COHER_STATUS_PM4__TC_ACTION_ENA__SHIFT 0x00000019 +#define COHER_STATUS_PM4__STATUS__SHIFT 0x0000001f + +// COHER_SIZE_HOST +#define COHER_SIZE_HOST__SIZE__SHIFT 0x00000000 + +// COHER_BASE_HOST +#define COHER_BASE_HOST__BASE__SHIFT 0x00000000 + +// COHER_STATUS_HOST +#define COHER_STATUS_HOST__MATCHING_CONTEXTS__SHIFT 0x00000000 +#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA__SHIFT 0x00000008 +#define COHER_STATUS_HOST__DEST_BASE_0_ENA__SHIFT 0x00000009 +#define COHER_STATUS_HOST__DEST_BASE_1_ENA__SHIFT 0x0000000a +#define COHER_STATUS_HOST__DEST_BASE_2_ENA__SHIFT 0x0000000b +#define COHER_STATUS_HOST__DEST_BASE_3_ENA__SHIFT 0x0000000c +#define COHER_STATUS_HOST__DEST_BASE_4_ENA__SHIFT 0x0000000d +#define COHER_STATUS_HOST__DEST_BASE_5_ENA__SHIFT 0x0000000e +#define COHER_STATUS_HOST__DEST_BASE_6_ENA__SHIFT 0x0000000f +#define COHER_STATUS_HOST__DEST_BASE_7_ENA__SHIFT 0x00000010 +#define COHER_STATUS_HOST__TC_ACTION_ENA__SHIFT 0x00000019 +#define COHER_STATUS_HOST__STATUS__SHIFT 0x0000001f + +// COHER_DEST_BASE_0 +#define COHER_DEST_BASE_0__DEST_BASE_0__SHIFT 0x0000000c + +// COHER_DEST_BASE_1 +#define COHER_DEST_BASE_1__DEST_BASE_1__SHIFT 0x0000000c + +// COHER_DEST_BASE_2 +#define COHER_DEST_BASE_2__DEST_BASE_2__SHIFT 0x0000000c + +// COHER_DEST_BASE_3 +#define COHER_DEST_BASE_3__DEST_BASE_3__SHIFT 0x0000000c + +// COHER_DEST_BASE_4 +#define COHER_DEST_BASE_4__DEST_BASE_4__SHIFT 0x0000000c + +// COHER_DEST_BASE_5 +#define COHER_DEST_BASE_5__DEST_BASE_5__SHIFT 0x0000000c + +// COHER_DEST_BASE_6 +#define COHER_DEST_BASE_6__DEST_BASE_6__SHIFT 0x0000000c + +// COHER_DEST_BASE_7 +#define COHER_DEST_BASE_7__DEST_BASE_7__SHIFT 0x0000000c + +// RB_SURFACE_INFO +#define RB_SURFACE_INFO__SURFACE_PITCH__SHIFT 0x00000000 +#define RB_SURFACE_INFO__MSAA_SAMPLES__SHIFT 0x0000000e + +// RB_COLOR_INFO +#define RB_COLOR_INFO__COLOR_FORMAT__SHIFT 0x00000000 +#define RB_COLOR_INFO__COLOR_ROUND_MODE__SHIFT 0x00000004 +#define RB_COLOR_INFO__COLOR_LINEAR__SHIFT 0x00000006 +#define RB_COLOR_INFO__COLOR_ENDIAN__SHIFT 0x00000007 +#define RB_COLOR_INFO__COLOR_SWAP__SHIFT 0x00000009 +#define RB_COLOR_INFO__COLOR_BASE__SHIFT 0x0000000c + +// RB_DEPTH_INFO +#define RB_DEPTH_INFO__DEPTH_FORMAT__SHIFT 0x00000000 +#define RB_DEPTH_INFO__DEPTH_BASE__SHIFT 0x0000000c + +// RB_STENCILREFMASK +#define RB_STENCILREFMASK__STENCILREF__SHIFT 0x00000000 +#define RB_STENCILREFMASK__STENCILMASK__SHIFT 0x00000008 +#define RB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x00000010 + +// RB_ALPHA_REF +#define RB_ALPHA_REF__ALPHA_REF__SHIFT 0x00000000 + +// RB_COLOR_MASK +#define RB_COLOR_MASK__WRITE_RED__SHIFT 0x00000000 +#define RB_COLOR_MASK__WRITE_GREEN__SHIFT 0x00000001 +#define RB_COLOR_MASK__WRITE_BLUE__SHIFT 0x00000002 +#define RB_COLOR_MASK__WRITE_ALPHA__SHIFT 0x00000003 + +// RB_BLEND_RED +#define RB_BLEND_RED__BLEND_RED__SHIFT 0x00000000 + +// RB_BLEND_GREEN +#define RB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x00000000 + +// RB_BLEND_BLUE +#define RB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x00000000 + +// RB_BLEND_ALPHA +#define RB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x00000000 + +// RB_FOG_COLOR +#define RB_FOG_COLOR__FOG_RED__SHIFT 0x00000000 +#define RB_FOG_COLOR__FOG_GREEN__SHIFT 0x00000008 +#define RB_FOG_COLOR__FOG_BLUE__SHIFT 0x00000010 + +// RB_STENCILREFMASK_BF +#define RB_STENCILREFMASK_BF__STENCILREF_BF__SHIFT 0x00000000 +#define RB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x00000008 +#define RB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x00000010 + +// RB_DEPTHCONTROL +#define RB_DEPTHCONTROL__STENCIL_ENABLE__SHIFT 0x00000000 +#define RB_DEPTHCONTROL__Z_ENABLE__SHIFT 0x00000001 +#define RB_DEPTHCONTROL__Z_WRITE_ENABLE__SHIFT 0x00000002 +#define RB_DEPTHCONTROL__EARLY_Z_ENABLE__SHIFT 0x00000003 +#define RB_DEPTHCONTROL__ZFUNC__SHIFT 0x00000004 +#define RB_DEPTHCONTROL__BACKFACE_ENABLE__SHIFT 0x00000007 +#define RB_DEPTHCONTROL__STENCILFUNC__SHIFT 0x00000008 +#define RB_DEPTHCONTROL__STENCILFAIL__SHIFT 0x0000000b +#define RB_DEPTHCONTROL__STENCILZPASS__SHIFT 0x0000000e +#define RB_DEPTHCONTROL__STENCILZFAIL__SHIFT 0x00000011 +#define RB_DEPTHCONTROL__STENCILFUNC_BF__SHIFT 0x00000014 +#define RB_DEPTHCONTROL__STENCILFAIL_BF__SHIFT 0x00000017 +#define RB_DEPTHCONTROL__STENCILZPASS_BF__SHIFT 0x0000001a +#define RB_DEPTHCONTROL__STENCILZFAIL_BF__SHIFT 0x0000001d + +// RB_BLENDCONTROL +#define RB_BLENDCONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 +#define RB_BLENDCONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 +#define RB_BLENDCONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 +#define RB_BLENDCONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 +#define RB_BLENDCONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 +#define RB_BLENDCONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 +#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE__SHIFT 0x0000001d +#define RB_BLENDCONTROL__BLEND_FORCE__SHIFT 0x0000001e + +// RB_COLORCONTROL +#define RB_COLORCONTROL__ALPHA_FUNC__SHIFT 0x00000000 +#define RB_COLORCONTROL__ALPHA_TEST_ENABLE__SHIFT 0x00000003 +#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE__SHIFT 0x00000004 +#define RB_COLORCONTROL__BLEND_DISABLE__SHIFT 0x00000005 +#define RB_COLORCONTROL__FOG_ENABLE__SHIFT 0x00000006 +#define RB_COLORCONTROL__VS_EXPORTS_FOG__SHIFT 0x00000007 +#define RB_COLORCONTROL__ROP_CODE__SHIFT 0x00000008 +#define RB_COLORCONTROL__DITHER_MODE__SHIFT 0x0000000c +#define RB_COLORCONTROL__DITHER_TYPE__SHIFT 0x0000000e +#define RB_COLORCONTROL__PIXEL_FOG__SHIFT 0x00000010 +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET0__SHIFT 0x00000018 +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET1__SHIFT 0x0000001a +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET2__SHIFT 0x0000001c +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET3__SHIFT 0x0000001e + +// RB_MODECONTROL +#define RB_MODECONTROL__EDRAM_MODE__SHIFT 0x00000000 + +// RB_COLOR_DEST_MASK +#define RB_COLOR_DEST_MASK__COLOR_DEST_MASK__SHIFT 0x00000000 + +// RB_COPY_CONTROL +#define RB_COPY_CONTROL__COPY_SAMPLE_SELECT__SHIFT 0x00000000 +#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x00000003 +#define RB_COPY_CONTROL__CLEAR_MASK__SHIFT 0x00000004 + +// RB_COPY_DEST_BASE +#define RB_COPY_DEST_BASE__COPY_DEST_BASE__SHIFT 0x0000000c + +// RB_COPY_DEST_PITCH +#define RB_COPY_DEST_PITCH__COPY_DEST_PITCH__SHIFT 0x00000000 + +// RB_COPY_DEST_INFO +#define RB_COPY_DEST_INFO__COPY_DEST_ENDIAN__SHIFT 0x00000000 +#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR__SHIFT 0x00000003 +#define RB_COPY_DEST_INFO__COPY_DEST_FORMAT__SHIFT 0x00000004 +#define RB_COPY_DEST_INFO__COPY_DEST_SWAP__SHIFT 0x00000008 +#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_MODE__SHIFT 0x0000000a +#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_TYPE__SHIFT 0x0000000c +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED__SHIFT 0x0000000e +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN__SHIFT 0x0000000f +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE__SHIFT 0x00000010 +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA__SHIFT 0x00000011 + +// RB_COPY_DEST_PIXEL_OFFSET +#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_X__SHIFT 0x00000000 +#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_Y__SHIFT 0x0000000d + +// RB_DEPTH_CLEAR +#define RB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x00000000 + +// RB_SAMPLE_COUNT_CTL +#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT__SHIFT 0x00000000 +#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT__SHIFT 0x00000001 + +// RB_SAMPLE_COUNT_ADDR +#define RB_SAMPLE_COUNT_ADDR__SAMPLE_COUNT_ADDR__SHIFT 0x00000000 + +// RB_BC_CONTROL +#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE__SHIFT 0x00000000 +#define RB_BC_CONTROL__ACCUM_TIMEOUT_SELECT__SHIFT 0x00000001 +#define RB_BC_CONTROL__DISABLE_EDRAM_CAM__SHIFT 0x00000003 +#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH__SHIFT 0x00000004 +#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP__SHIFT 0x00000005 +#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP__SHIFT 0x00000006 +#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE__SHIFT 0x00000007 +#define RB_BC_CONTROL__AZ_THROTTLE_COUNT__SHIFT 0x00000008 +#define RB_BC_CONTROL__ENABLE_CRC_UPDATE__SHIFT 0x0000000e +#define RB_BC_CONTROL__CRC_MODE__SHIFT 0x0000000f +#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS__SHIFT 0x00000010 +#define RB_BC_CONTROL__DISABLE_ACCUM__SHIFT 0x00000011 +#define RB_BC_CONTROL__ACCUM_ALLOC_MASK__SHIFT 0x00000012 +#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE__SHIFT 0x00000016 +#define RB_BC_CONTROL__ACCUM_DATA_FIFO_LIMIT__SHIFT 0x00000017 +#define RB_BC_CONTROL__MEM_EXPORT_TIMEOUT_SELECT__SHIFT 0x0000001b +#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE__SHIFT 0x0000001d +#define RB_BC_CONTROL__RESERVED9__SHIFT 0x0000001e +#define RB_BC_CONTROL__RESERVED10__SHIFT 0x0000001f + +// RB_EDRAM_INFO +#define RB_EDRAM_INFO__EDRAM_SIZE__SHIFT 0x00000000 +#define RB_EDRAM_INFO__EDRAM_MAPPING_MODE__SHIFT 0x00000004 +#define RB_EDRAM_INFO__EDRAM_RANGE__SHIFT 0x0000000e + +// RB_CRC_RD_PORT +#define RB_CRC_RD_PORT__CRC_DATA__SHIFT 0x00000000 + +// RB_CRC_CONTROL +#define RB_CRC_CONTROL__CRC_RD_ADVANCE__SHIFT 0x00000000 + +// RB_CRC_MASK +#define RB_CRC_MASK__CRC_MASK__SHIFT 0x00000000 + +// RB_PERFCOUNTER0_SELECT +#define RB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// RB_PERFCOUNTER0_LOW +#define RB_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// RB_PERFCOUNTER0_HI +#define RB_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// RB_TOTAL_SAMPLES +#define RB_TOTAL_SAMPLES__TOTAL_SAMPLES__SHIFT 0x00000000 + +// RB_ZPASS_SAMPLES +#define RB_ZPASS_SAMPLES__ZPASS_SAMPLES__SHIFT 0x00000000 + +// RB_ZFAIL_SAMPLES +#define RB_ZFAIL_SAMPLES__ZFAIL_SAMPLES__SHIFT 0x00000000 + +// RB_SFAIL_SAMPLES +#define RB_SFAIL_SAMPLES__SFAIL_SAMPLES__SHIFT 0x00000000 + +// RB_DEBUG_0 +#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL__SHIFT 0x00000000 +#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL__SHIFT 0x00000001 +#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL__SHIFT 0x00000002 +#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL__SHIFT 0x00000003 +#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL__SHIFT 0x00000004 +#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL__SHIFT 0x00000005 +#define RB_DEBUG_0__RDREQ_Z1_FULL__SHIFT 0x00000006 +#define RB_DEBUG_0__RDREQ_Z0_FULL__SHIFT 0x00000007 +#define RB_DEBUG_0__RDREQ_C1_FULL__SHIFT 0x00000008 +#define RB_DEBUG_0__RDREQ_C0_FULL__SHIFT 0x00000009 +#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL__SHIFT 0x0000000a +#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL__SHIFT 0x0000000b +#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL__SHIFT 0x0000000c +#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL__SHIFT 0x0000000d +#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL__SHIFT 0x0000000e +#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL__SHIFT 0x0000000f +#define RB_DEBUG_0__WRREQ_Z1_FULL__SHIFT 0x00000010 +#define RB_DEBUG_0__WRREQ_Z0_FULL__SHIFT 0x00000011 +#define RB_DEBUG_0__WRREQ_C1_FULL__SHIFT 0x00000012 +#define RB_DEBUG_0__WRREQ_C0_FULL__SHIFT 0x00000013 +#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL__SHIFT 0x00000014 +#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL__SHIFT 0x00000015 +#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL__SHIFT 0x00000016 +#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL__SHIFT 0x00000017 +#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL__SHIFT 0x00000018 +#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL__SHIFT 0x00000019 +#define RB_DEBUG_0__C_SX_LAT_FULL__SHIFT 0x0000001a +#define RB_DEBUG_0__C_SX_CMD_FULL__SHIFT 0x0000001b +#define RB_DEBUG_0__C_EZ_TILE_FULL__SHIFT 0x0000001c +#define RB_DEBUG_0__C_REQ_FULL__SHIFT 0x0000001d +#define RB_DEBUG_0__C_MASK_FULL__SHIFT 0x0000001e +#define RB_DEBUG_0__EZ_INFSAMP_FULL__SHIFT 0x0000001f + +// RB_DEBUG_1 +#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY__SHIFT 0x00000000 +#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY__SHIFT 0x00000001 +#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY__SHIFT 0x00000002 +#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY__SHIFT 0x00000003 +#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY__SHIFT 0x00000004 +#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY__SHIFT 0x00000005 +#define RB_DEBUG_1__RDREQ_Z1_EMPTY__SHIFT 0x00000006 +#define RB_DEBUG_1__RDREQ_Z0_EMPTY__SHIFT 0x00000007 +#define RB_DEBUG_1__RDREQ_C1_EMPTY__SHIFT 0x00000008 +#define RB_DEBUG_1__RDREQ_C0_EMPTY__SHIFT 0x00000009 +#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY__SHIFT 0x0000000a +#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY__SHIFT 0x0000000b +#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY__SHIFT 0x0000000c +#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY__SHIFT 0x0000000d +#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY__SHIFT 0x0000000e +#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY__SHIFT 0x0000000f +#define RB_DEBUG_1__WRREQ_Z1_EMPTY__SHIFT 0x00000010 +#define RB_DEBUG_1__WRREQ_Z0_EMPTY__SHIFT 0x00000011 +#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY__SHIFT 0x00000012 +#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY__SHIFT 0x00000013 +#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY__SHIFT 0x00000014 +#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY__SHIFT 0x00000015 +#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY__SHIFT 0x00000016 +#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY__SHIFT 0x00000017 +#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY__SHIFT 0x00000018 +#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY__SHIFT 0x00000019 +#define RB_DEBUG_1__C_SX_LAT_EMPTY__SHIFT 0x0000001a +#define RB_DEBUG_1__C_SX_CMD_EMPTY__SHIFT 0x0000001b +#define RB_DEBUG_1__C_EZ_TILE_EMPTY__SHIFT 0x0000001c +#define RB_DEBUG_1__C_REQ_EMPTY__SHIFT 0x0000001d +#define RB_DEBUG_1__C_MASK_EMPTY__SHIFT 0x0000001e +#define RB_DEBUG_1__EZ_INFSAMP_EMPTY__SHIFT 0x0000001f + +// RB_DEBUG_2 +#define RB_DEBUG_2__TILE_FIFO_COUNT__SHIFT 0x00000000 +#define RB_DEBUG_2__SX_LAT_FIFO_COUNT__SHIFT 0x00000004 +#define RB_DEBUG_2__MEM_EXPORT_FLAG__SHIFT 0x0000000b +#define RB_DEBUG_2__SYSMEM_BLEND_FLAG__SHIFT 0x0000000c +#define RB_DEBUG_2__CURRENT_TILE_EVENT__SHIFT 0x0000000d +#define RB_DEBUG_2__EZ_INFTILE_FULL__SHIFT 0x0000000e +#define RB_DEBUG_2__EZ_MASK_LOWER_FULL__SHIFT 0x0000000f +#define RB_DEBUG_2__EZ_MASK_UPPER_FULL__SHIFT 0x00000010 +#define RB_DEBUG_2__Z0_MASK_FULL__SHIFT 0x00000011 +#define RB_DEBUG_2__Z1_MASK_FULL__SHIFT 0x00000012 +#define RB_DEBUG_2__Z0_REQ_FULL__SHIFT 0x00000013 +#define RB_DEBUG_2__Z1_REQ_FULL__SHIFT 0x00000014 +#define RB_DEBUG_2__Z_SAMP_FULL__SHIFT 0x00000015 +#define RB_DEBUG_2__Z_TILE_FULL__SHIFT 0x00000016 +#define RB_DEBUG_2__EZ_INFTILE_EMPTY__SHIFT 0x00000017 +#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY__SHIFT 0x00000018 +#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY__SHIFT 0x00000019 +#define RB_DEBUG_2__Z0_MASK_EMPTY__SHIFT 0x0000001a +#define RB_DEBUG_2__Z1_MASK_EMPTY__SHIFT 0x0000001b +#define RB_DEBUG_2__Z0_REQ_EMPTY__SHIFT 0x0000001c +#define RB_DEBUG_2__Z1_REQ_EMPTY__SHIFT 0x0000001d +#define RB_DEBUG_2__Z_SAMP_EMPTY__SHIFT 0x0000001e +#define RB_DEBUG_2__Z_TILE_EMPTY__SHIFT 0x0000001f + +// RB_DEBUG_3 +#define RB_DEBUG_3__ACCUM_VALID__SHIFT 0x00000000 +#define RB_DEBUG_3__ACCUM_FLUSHING__SHIFT 0x00000004 +#define RB_DEBUG_3__ACCUM_WRITE_CLEAN_COUNT__SHIFT 0x00000008 +#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID__SHIFT 0x0000000e +#define RB_DEBUG_3__ACCUM_DATA_FIFO_CNT__SHIFT 0x0000000f +#define RB_DEBUG_3__SHD_FULL__SHIFT 0x00000013 +#define RB_DEBUG_3__SHD_EMPTY__SHIFT 0x00000014 +#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY__SHIFT 0x00000015 +#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY__SHIFT 0x00000016 +#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL__SHIFT 0x00000017 +#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL__SHIFT 0x00000018 +#define RB_DEBUG_3__ZEXP_LOWER_EMPTY__SHIFT 0x00000019 +#define RB_DEBUG_3__ZEXP_UPPER_EMPTY__SHIFT 0x0000001a +#define RB_DEBUG_3__ZEXP_LOWER_FULL__SHIFT 0x0000001b +#define RB_DEBUG_3__ZEXP_UPPER_FULL__SHIFT 0x0000001c + +// RB_DEBUG_4 +#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG__SHIFT 0x00000000 +#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG__SHIFT 0x00000001 +#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG__SHIFT 0x00000002 +#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG__SHIFT 0x00000003 +#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY__SHIFT 0x00000004 +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY__SHIFT 0x00000005 +#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL__SHIFT 0x00000006 +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL__SHIFT 0x00000007 +#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW__SHIFT 0x00000008 +#define RB_DEBUG_4__CONTEXT_COUNT_DEBUG__SHIFT 0x00000009 + +// RB_FLAG_CONTROL +#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR__SHIFT 0x00000000 + +// BC_DUMMY_CRAYRB_ENUMS +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_FORMAT__SHIFT 0x00000000 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP__SHIFT 0x00000006 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_ARRAY__SHIFT 0x00000007 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_ARRAY__SHIFT 0x00000009 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_COLOR_FORMAT__SHIFT 0x0000000b +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_NUMBER__SHIFT 0x00000011 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_FORMAT__SHIFT 0x00000014 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING__SHIFT 0x0000001a +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_ARRAY__SHIFT 0x0000001b +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_RB_COPY_DEST_INFO_NUMBER__SHIFT 0x0000001d + +// BC_DUMMY_CRAYRB_MOREENUMS +#define BC_DUMMY_CRAYRB_MOREENUMS__DUMMY_CRAYRB_COLORARRAYX__SHIFT 0x00000000 + +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_struct.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_struct.h new file mode 100644 index 000000000000..80b9106759e3 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_struct.h @@ -0,0 +1,51301 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_CP_FIDDLE_H) +#define _CP_FIDDLE_H + + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * CP_RB_BASE struct + */ + +#define CP_RB_BASE_RB_BASE_SIZE 27 + +#define CP_RB_BASE_RB_BASE_SHIFT 5 + +#define CP_RB_BASE_RB_BASE_MASK 0xffffffe0 + +#define CP_RB_BASE_MASK \ + (CP_RB_BASE_RB_BASE_MASK) + +#define CP_RB_BASE(rb_base) \ + ((rb_base << CP_RB_BASE_RB_BASE_SHIFT)) + +#define CP_RB_BASE_GET_RB_BASE(cp_rb_base) \ + ((cp_rb_base & CP_RB_BASE_RB_BASE_MASK) >> CP_RB_BASE_RB_BASE_SHIFT) + +#define CP_RB_BASE_SET_RB_BASE(cp_rb_base_reg, rb_base) \ + cp_rb_base_reg = (cp_rb_base_reg & ~CP_RB_BASE_RB_BASE_MASK) | (rb_base << CP_RB_BASE_RB_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_base_t { + unsigned int : 5; + unsigned int rb_base : CP_RB_BASE_RB_BASE_SIZE; + } cp_rb_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_base_t { + unsigned int rb_base : CP_RB_BASE_RB_BASE_SIZE; + unsigned int : 5; + } cp_rb_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_base_t f; +} cp_rb_base_u; + + +/* + * CP_RB_CNTL struct + */ + +#define CP_RB_CNTL_RB_BUFSZ_SIZE 6 +#define CP_RB_CNTL_RB_BLKSZ_SIZE 6 +#define CP_RB_CNTL_BUF_SWAP_SIZE 2 +#define CP_RB_CNTL_RB_POLL_EN_SIZE 1 +#define CP_RB_CNTL_RB_NO_UPDATE_SIZE 1 +#define CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE 1 + +#define CP_RB_CNTL_RB_BUFSZ_SHIFT 0 +#define CP_RB_CNTL_RB_BLKSZ_SHIFT 8 +#define CP_RB_CNTL_BUF_SWAP_SHIFT 16 +#define CP_RB_CNTL_RB_POLL_EN_SHIFT 20 +#define CP_RB_CNTL_RB_NO_UPDATE_SHIFT 27 +#define CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT 31 + +#define CP_RB_CNTL_RB_BUFSZ_MASK 0x0000003f +#define CP_RB_CNTL_RB_BLKSZ_MASK 0x00003f00 +#define CP_RB_CNTL_BUF_SWAP_MASK 0x00030000 +#define CP_RB_CNTL_RB_POLL_EN_MASK 0x00100000 +#define CP_RB_CNTL_RB_NO_UPDATE_MASK 0x08000000 +#define CP_RB_CNTL_RB_RPTR_WR_ENA_MASK 0x80000000 + +#define CP_RB_CNTL_MASK \ + (CP_RB_CNTL_RB_BUFSZ_MASK | \ + CP_RB_CNTL_RB_BLKSZ_MASK | \ + CP_RB_CNTL_BUF_SWAP_MASK | \ + CP_RB_CNTL_RB_POLL_EN_MASK | \ + CP_RB_CNTL_RB_NO_UPDATE_MASK | \ + CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) + +#define CP_RB_CNTL(rb_bufsz, rb_blksz, buf_swap, rb_poll_en, rb_no_update, rb_rptr_wr_ena) \ + ((rb_bufsz << CP_RB_CNTL_RB_BUFSZ_SHIFT) | \ + (rb_blksz << CP_RB_CNTL_RB_BLKSZ_SHIFT) | \ + (buf_swap << CP_RB_CNTL_BUF_SWAP_SHIFT) | \ + (rb_poll_en << CP_RB_CNTL_RB_POLL_EN_SHIFT) | \ + (rb_no_update << CP_RB_CNTL_RB_NO_UPDATE_SHIFT) | \ + (rb_rptr_wr_ena << CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT)) + +#define CP_RB_CNTL_GET_RB_BUFSZ(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_BUFSZ_MASK) >> CP_RB_CNTL_RB_BUFSZ_SHIFT) +#define CP_RB_CNTL_GET_RB_BLKSZ(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_BLKSZ_MASK) >> CP_RB_CNTL_RB_BLKSZ_SHIFT) +#define CP_RB_CNTL_GET_BUF_SWAP(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_BUF_SWAP_MASK) >> CP_RB_CNTL_BUF_SWAP_SHIFT) +#define CP_RB_CNTL_GET_RB_POLL_EN(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_POLL_EN_MASK) >> CP_RB_CNTL_RB_POLL_EN_SHIFT) +#define CP_RB_CNTL_GET_RB_NO_UPDATE(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_NO_UPDATE_MASK) >> CP_RB_CNTL_RB_NO_UPDATE_SHIFT) +#define CP_RB_CNTL_GET_RB_RPTR_WR_ENA(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) >> CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT) + +#define CP_RB_CNTL_SET_RB_BUFSZ(cp_rb_cntl_reg, rb_bufsz) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_BUFSZ_MASK) | (rb_bufsz << CP_RB_CNTL_RB_BUFSZ_SHIFT) +#define CP_RB_CNTL_SET_RB_BLKSZ(cp_rb_cntl_reg, rb_blksz) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_BLKSZ_MASK) | (rb_blksz << CP_RB_CNTL_RB_BLKSZ_SHIFT) +#define CP_RB_CNTL_SET_BUF_SWAP(cp_rb_cntl_reg, buf_swap) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_BUF_SWAP_MASK) | (buf_swap << CP_RB_CNTL_BUF_SWAP_SHIFT) +#define CP_RB_CNTL_SET_RB_POLL_EN(cp_rb_cntl_reg, rb_poll_en) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_POLL_EN_MASK) | (rb_poll_en << CP_RB_CNTL_RB_POLL_EN_SHIFT) +#define CP_RB_CNTL_SET_RB_NO_UPDATE(cp_rb_cntl_reg, rb_no_update) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_NO_UPDATE_MASK) | (rb_no_update << CP_RB_CNTL_RB_NO_UPDATE_SHIFT) +#define CP_RB_CNTL_SET_RB_RPTR_WR_ENA(cp_rb_cntl_reg, rb_rptr_wr_ena) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) | (rb_rptr_wr_ena << CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_cntl_t { + unsigned int rb_bufsz : CP_RB_CNTL_RB_BUFSZ_SIZE; + unsigned int : 2; + unsigned int rb_blksz : CP_RB_CNTL_RB_BLKSZ_SIZE; + unsigned int : 2; + unsigned int buf_swap : CP_RB_CNTL_BUF_SWAP_SIZE; + unsigned int : 2; + unsigned int rb_poll_en : CP_RB_CNTL_RB_POLL_EN_SIZE; + unsigned int : 6; + unsigned int rb_no_update : CP_RB_CNTL_RB_NO_UPDATE_SIZE; + unsigned int : 3; + unsigned int rb_rptr_wr_ena : CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE; + } cp_rb_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_cntl_t { + unsigned int rb_rptr_wr_ena : CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE; + unsigned int : 3; + unsigned int rb_no_update : CP_RB_CNTL_RB_NO_UPDATE_SIZE; + unsigned int : 6; + unsigned int rb_poll_en : CP_RB_CNTL_RB_POLL_EN_SIZE; + unsigned int : 2; + unsigned int buf_swap : CP_RB_CNTL_BUF_SWAP_SIZE; + unsigned int : 2; + unsigned int rb_blksz : CP_RB_CNTL_RB_BLKSZ_SIZE; + unsigned int : 2; + unsigned int rb_bufsz : CP_RB_CNTL_RB_BUFSZ_SIZE; + } cp_rb_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_cntl_t f; +} cp_rb_cntl_u; + + +/* + * CP_RB_RPTR_ADDR struct + */ + +#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE 2 +#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE 30 + +#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT 0 +#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT 2 + +#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK 0x00000003 +#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK 0xfffffffc + +#define CP_RB_RPTR_ADDR_MASK \ + (CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK | \ + CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) + +#define CP_RB_RPTR_ADDR(rb_rptr_swap, rb_rptr_addr) \ + ((rb_rptr_swap << CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT) | \ + (rb_rptr_addr << CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT)) + +#define CP_RB_RPTR_ADDR_GET_RB_RPTR_SWAP(cp_rb_rptr_addr) \ + ((cp_rb_rptr_addr & CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK) >> CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT) +#define CP_RB_RPTR_ADDR_GET_RB_RPTR_ADDR(cp_rb_rptr_addr) \ + ((cp_rb_rptr_addr & CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) >> CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT) + +#define CP_RB_RPTR_ADDR_SET_RB_RPTR_SWAP(cp_rb_rptr_addr_reg, rb_rptr_swap) \ + cp_rb_rptr_addr_reg = (cp_rb_rptr_addr_reg & ~CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK) | (rb_rptr_swap << CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT) +#define CP_RB_RPTR_ADDR_SET_RB_RPTR_ADDR(cp_rb_rptr_addr_reg, rb_rptr_addr) \ + cp_rb_rptr_addr_reg = (cp_rb_rptr_addr_reg & ~CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) | (rb_rptr_addr << CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_rptr_addr_t { + unsigned int rb_rptr_swap : CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE; + unsigned int rb_rptr_addr : CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE; + } cp_rb_rptr_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_rptr_addr_t { + unsigned int rb_rptr_addr : CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE; + unsigned int rb_rptr_swap : CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE; + } cp_rb_rptr_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_rptr_addr_t f; +} cp_rb_rptr_addr_u; + + +/* + * CP_RB_RPTR struct + */ + +#define CP_RB_RPTR_RB_RPTR_SIZE 20 + +#define CP_RB_RPTR_RB_RPTR_SHIFT 0 + +#define CP_RB_RPTR_RB_RPTR_MASK 0x000fffff + +#define CP_RB_RPTR_MASK \ + (CP_RB_RPTR_RB_RPTR_MASK) + +#define CP_RB_RPTR(rb_rptr) \ + ((rb_rptr << CP_RB_RPTR_RB_RPTR_SHIFT)) + +#define CP_RB_RPTR_GET_RB_RPTR(cp_rb_rptr) \ + ((cp_rb_rptr & CP_RB_RPTR_RB_RPTR_MASK) >> CP_RB_RPTR_RB_RPTR_SHIFT) + +#define CP_RB_RPTR_SET_RB_RPTR(cp_rb_rptr_reg, rb_rptr) \ + cp_rb_rptr_reg = (cp_rb_rptr_reg & ~CP_RB_RPTR_RB_RPTR_MASK) | (rb_rptr << CP_RB_RPTR_RB_RPTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_rptr_t { + unsigned int rb_rptr : CP_RB_RPTR_RB_RPTR_SIZE; + unsigned int : 12; + } cp_rb_rptr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_rptr_t { + unsigned int : 12; + unsigned int rb_rptr : CP_RB_RPTR_RB_RPTR_SIZE; + } cp_rb_rptr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_rptr_t f; +} cp_rb_rptr_u; + + +/* + * CP_RB_RPTR_WR struct + */ + +#define CP_RB_RPTR_WR_RB_RPTR_WR_SIZE 20 + +#define CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT 0 + +#define CP_RB_RPTR_WR_RB_RPTR_WR_MASK 0x000fffff + +#define CP_RB_RPTR_WR_MASK \ + (CP_RB_RPTR_WR_RB_RPTR_WR_MASK) + +#define CP_RB_RPTR_WR(rb_rptr_wr) \ + ((rb_rptr_wr << CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT)) + +#define CP_RB_RPTR_WR_GET_RB_RPTR_WR(cp_rb_rptr_wr) \ + ((cp_rb_rptr_wr & CP_RB_RPTR_WR_RB_RPTR_WR_MASK) >> CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT) + +#define CP_RB_RPTR_WR_SET_RB_RPTR_WR(cp_rb_rptr_wr_reg, rb_rptr_wr) \ + cp_rb_rptr_wr_reg = (cp_rb_rptr_wr_reg & ~CP_RB_RPTR_WR_RB_RPTR_WR_MASK) | (rb_rptr_wr << CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_rptr_wr_t { + unsigned int rb_rptr_wr : CP_RB_RPTR_WR_RB_RPTR_WR_SIZE; + unsigned int : 12; + } cp_rb_rptr_wr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_rptr_wr_t { + unsigned int : 12; + unsigned int rb_rptr_wr : CP_RB_RPTR_WR_RB_RPTR_WR_SIZE; + } cp_rb_rptr_wr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_rptr_wr_t f; +} cp_rb_rptr_wr_u; + + +/* + * CP_RB_WPTR struct + */ + +#define CP_RB_WPTR_RB_WPTR_SIZE 20 + +#define CP_RB_WPTR_RB_WPTR_SHIFT 0 + +#define CP_RB_WPTR_RB_WPTR_MASK 0x000fffff + +#define CP_RB_WPTR_MASK \ + (CP_RB_WPTR_RB_WPTR_MASK) + +#define CP_RB_WPTR(rb_wptr) \ + ((rb_wptr << CP_RB_WPTR_RB_WPTR_SHIFT)) + +#define CP_RB_WPTR_GET_RB_WPTR(cp_rb_wptr) \ + ((cp_rb_wptr & CP_RB_WPTR_RB_WPTR_MASK) >> CP_RB_WPTR_RB_WPTR_SHIFT) + +#define CP_RB_WPTR_SET_RB_WPTR(cp_rb_wptr_reg, rb_wptr) \ + cp_rb_wptr_reg = (cp_rb_wptr_reg & ~CP_RB_WPTR_RB_WPTR_MASK) | (rb_wptr << CP_RB_WPTR_RB_WPTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_wptr_t { + unsigned int rb_wptr : CP_RB_WPTR_RB_WPTR_SIZE; + unsigned int : 12; + } cp_rb_wptr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_wptr_t { + unsigned int : 12; + unsigned int rb_wptr : CP_RB_WPTR_RB_WPTR_SIZE; + } cp_rb_wptr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_wptr_t f; +} cp_rb_wptr_u; + + +/* + * CP_RB_WPTR_DELAY struct + */ + +#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE 28 +#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE 4 + +#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT 0 +#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT 28 + +#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK 0x0fffffff +#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK 0xf0000000 + +#define CP_RB_WPTR_DELAY_MASK \ + (CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK | \ + CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) + +#define CP_RB_WPTR_DELAY(pre_write_timer, pre_write_limit) \ + ((pre_write_timer << CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT) | \ + (pre_write_limit << CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT)) + +#define CP_RB_WPTR_DELAY_GET_PRE_WRITE_TIMER(cp_rb_wptr_delay) \ + ((cp_rb_wptr_delay & CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK) >> CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT) +#define CP_RB_WPTR_DELAY_GET_PRE_WRITE_LIMIT(cp_rb_wptr_delay) \ + ((cp_rb_wptr_delay & CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) >> CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT) + +#define CP_RB_WPTR_DELAY_SET_PRE_WRITE_TIMER(cp_rb_wptr_delay_reg, pre_write_timer) \ + cp_rb_wptr_delay_reg = (cp_rb_wptr_delay_reg & ~CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK) | (pre_write_timer << CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT) +#define CP_RB_WPTR_DELAY_SET_PRE_WRITE_LIMIT(cp_rb_wptr_delay_reg, pre_write_limit) \ + cp_rb_wptr_delay_reg = (cp_rb_wptr_delay_reg & ~CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) | (pre_write_limit << CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_wptr_delay_t { + unsigned int pre_write_timer : CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE; + unsigned int pre_write_limit : CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE; + } cp_rb_wptr_delay_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_wptr_delay_t { + unsigned int pre_write_limit : CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE; + unsigned int pre_write_timer : CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE; + } cp_rb_wptr_delay_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_wptr_delay_t f; +} cp_rb_wptr_delay_u; + + +/* + * CP_RB_WPTR_BASE struct + */ + +#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE 2 +#define CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE 30 + +#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT 0 +#define CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT 2 + +#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK 0x00000003 +#define CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK 0xfffffffc + +#define CP_RB_WPTR_BASE_MASK \ + (CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK | \ + CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) + +#define CP_RB_WPTR_BASE(rb_wptr_swap, rb_wptr_base) \ + ((rb_wptr_swap << CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT) | \ + (rb_wptr_base << CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT)) + +#define CP_RB_WPTR_BASE_GET_RB_WPTR_SWAP(cp_rb_wptr_base) \ + ((cp_rb_wptr_base & CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK) >> CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT) +#define CP_RB_WPTR_BASE_GET_RB_WPTR_BASE(cp_rb_wptr_base) \ + ((cp_rb_wptr_base & CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) >> CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT) + +#define CP_RB_WPTR_BASE_SET_RB_WPTR_SWAP(cp_rb_wptr_base_reg, rb_wptr_swap) \ + cp_rb_wptr_base_reg = (cp_rb_wptr_base_reg & ~CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK) | (rb_wptr_swap << CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT) +#define CP_RB_WPTR_BASE_SET_RB_WPTR_BASE(cp_rb_wptr_base_reg, rb_wptr_base) \ + cp_rb_wptr_base_reg = (cp_rb_wptr_base_reg & ~CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) | (rb_wptr_base << CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_wptr_base_t { + unsigned int rb_wptr_swap : CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE; + unsigned int rb_wptr_base : CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE; + } cp_rb_wptr_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_wptr_base_t { + unsigned int rb_wptr_base : CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE; + unsigned int rb_wptr_swap : CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE; + } cp_rb_wptr_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_wptr_base_t f; +} cp_rb_wptr_base_u; + + +/* + * CP_IB1_BASE struct + */ + +#define CP_IB1_BASE_IB1_BASE_SIZE 30 + +#define CP_IB1_BASE_IB1_BASE_SHIFT 2 + +#define CP_IB1_BASE_IB1_BASE_MASK 0xfffffffc + +#define CP_IB1_BASE_MASK \ + (CP_IB1_BASE_IB1_BASE_MASK) + +#define CP_IB1_BASE(ib1_base) \ + ((ib1_base << CP_IB1_BASE_IB1_BASE_SHIFT)) + +#define CP_IB1_BASE_GET_IB1_BASE(cp_ib1_base) \ + ((cp_ib1_base & CP_IB1_BASE_IB1_BASE_MASK) >> CP_IB1_BASE_IB1_BASE_SHIFT) + +#define CP_IB1_BASE_SET_IB1_BASE(cp_ib1_base_reg, ib1_base) \ + cp_ib1_base_reg = (cp_ib1_base_reg & ~CP_IB1_BASE_IB1_BASE_MASK) | (ib1_base << CP_IB1_BASE_IB1_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_ib1_base_t { + unsigned int : 2; + unsigned int ib1_base : CP_IB1_BASE_IB1_BASE_SIZE; + } cp_ib1_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_ib1_base_t { + unsigned int ib1_base : CP_IB1_BASE_IB1_BASE_SIZE; + unsigned int : 2; + } cp_ib1_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_ib1_base_t f; +} cp_ib1_base_u; + + +/* + * CP_IB1_BUFSZ struct + */ + +#define CP_IB1_BUFSZ_IB1_BUFSZ_SIZE 20 + +#define CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT 0 + +#define CP_IB1_BUFSZ_IB1_BUFSZ_MASK 0x000fffff + +#define CP_IB1_BUFSZ_MASK \ + (CP_IB1_BUFSZ_IB1_BUFSZ_MASK) + +#define CP_IB1_BUFSZ(ib1_bufsz) \ + ((ib1_bufsz << CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT)) + +#define CP_IB1_BUFSZ_GET_IB1_BUFSZ(cp_ib1_bufsz) \ + ((cp_ib1_bufsz & CP_IB1_BUFSZ_IB1_BUFSZ_MASK) >> CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT) + +#define CP_IB1_BUFSZ_SET_IB1_BUFSZ(cp_ib1_bufsz_reg, ib1_bufsz) \ + cp_ib1_bufsz_reg = (cp_ib1_bufsz_reg & ~CP_IB1_BUFSZ_IB1_BUFSZ_MASK) | (ib1_bufsz << CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_ib1_bufsz_t { + unsigned int ib1_bufsz : CP_IB1_BUFSZ_IB1_BUFSZ_SIZE; + unsigned int : 12; + } cp_ib1_bufsz_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_ib1_bufsz_t { + unsigned int : 12; + unsigned int ib1_bufsz : CP_IB1_BUFSZ_IB1_BUFSZ_SIZE; + } cp_ib1_bufsz_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_ib1_bufsz_t f; +} cp_ib1_bufsz_u; + + +/* + * CP_IB2_BASE struct + */ + +#define CP_IB2_BASE_IB2_BASE_SIZE 30 + +#define CP_IB2_BASE_IB2_BASE_SHIFT 2 + +#define CP_IB2_BASE_IB2_BASE_MASK 0xfffffffc + +#define CP_IB2_BASE_MASK \ + (CP_IB2_BASE_IB2_BASE_MASK) + +#define CP_IB2_BASE(ib2_base) \ + ((ib2_base << CP_IB2_BASE_IB2_BASE_SHIFT)) + +#define CP_IB2_BASE_GET_IB2_BASE(cp_ib2_base) \ + ((cp_ib2_base & CP_IB2_BASE_IB2_BASE_MASK) >> CP_IB2_BASE_IB2_BASE_SHIFT) + +#define CP_IB2_BASE_SET_IB2_BASE(cp_ib2_base_reg, ib2_base) \ + cp_ib2_base_reg = (cp_ib2_base_reg & ~CP_IB2_BASE_IB2_BASE_MASK) | (ib2_base << CP_IB2_BASE_IB2_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_ib2_base_t { + unsigned int : 2; + unsigned int ib2_base : CP_IB2_BASE_IB2_BASE_SIZE; + } cp_ib2_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_ib2_base_t { + unsigned int ib2_base : CP_IB2_BASE_IB2_BASE_SIZE; + unsigned int : 2; + } cp_ib2_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_ib2_base_t f; +} cp_ib2_base_u; + + +/* + * CP_IB2_BUFSZ struct + */ + +#define CP_IB2_BUFSZ_IB2_BUFSZ_SIZE 20 + +#define CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT 0 + +#define CP_IB2_BUFSZ_IB2_BUFSZ_MASK 0x000fffff + +#define CP_IB2_BUFSZ_MASK \ + (CP_IB2_BUFSZ_IB2_BUFSZ_MASK) + +#define CP_IB2_BUFSZ(ib2_bufsz) \ + ((ib2_bufsz << CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT)) + +#define CP_IB2_BUFSZ_GET_IB2_BUFSZ(cp_ib2_bufsz) \ + ((cp_ib2_bufsz & CP_IB2_BUFSZ_IB2_BUFSZ_MASK) >> CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT) + +#define CP_IB2_BUFSZ_SET_IB2_BUFSZ(cp_ib2_bufsz_reg, ib2_bufsz) \ + cp_ib2_bufsz_reg = (cp_ib2_bufsz_reg & ~CP_IB2_BUFSZ_IB2_BUFSZ_MASK) | (ib2_bufsz << CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_ib2_bufsz_t { + unsigned int ib2_bufsz : CP_IB2_BUFSZ_IB2_BUFSZ_SIZE; + unsigned int : 12; + } cp_ib2_bufsz_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_ib2_bufsz_t { + unsigned int : 12; + unsigned int ib2_bufsz : CP_IB2_BUFSZ_IB2_BUFSZ_SIZE; + } cp_ib2_bufsz_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_ib2_bufsz_t f; +} cp_ib2_bufsz_u; + + +/* + * CP_ST_BASE struct + */ + +#define CP_ST_BASE_ST_BASE_SIZE 30 + +#define CP_ST_BASE_ST_BASE_SHIFT 2 + +#define CP_ST_BASE_ST_BASE_MASK 0xfffffffc + +#define CP_ST_BASE_MASK \ + (CP_ST_BASE_ST_BASE_MASK) + +#define CP_ST_BASE(st_base) \ + ((st_base << CP_ST_BASE_ST_BASE_SHIFT)) + +#define CP_ST_BASE_GET_ST_BASE(cp_st_base) \ + ((cp_st_base & CP_ST_BASE_ST_BASE_MASK) >> CP_ST_BASE_ST_BASE_SHIFT) + +#define CP_ST_BASE_SET_ST_BASE(cp_st_base_reg, st_base) \ + cp_st_base_reg = (cp_st_base_reg & ~CP_ST_BASE_ST_BASE_MASK) | (st_base << CP_ST_BASE_ST_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_st_base_t { + unsigned int : 2; + unsigned int st_base : CP_ST_BASE_ST_BASE_SIZE; + } cp_st_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_st_base_t { + unsigned int st_base : CP_ST_BASE_ST_BASE_SIZE; + unsigned int : 2; + } cp_st_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_st_base_t f; +} cp_st_base_u; + + +/* + * CP_ST_BUFSZ struct + */ + +#define CP_ST_BUFSZ_ST_BUFSZ_SIZE 20 + +#define CP_ST_BUFSZ_ST_BUFSZ_SHIFT 0 + +#define CP_ST_BUFSZ_ST_BUFSZ_MASK 0x000fffff + +#define CP_ST_BUFSZ_MASK \ + (CP_ST_BUFSZ_ST_BUFSZ_MASK) + +#define CP_ST_BUFSZ(st_bufsz) \ + ((st_bufsz << CP_ST_BUFSZ_ST_BUFSZ_SHIFT)) + +#define CP_ST_BUFSZ_GET_ST_BUFSZ(cp_st_bufsz) \ + ((cp_st_bufsz & CP_ST_BUFSZ_ST_BUFSZ_MASK) >> CP_ST_BUFSZ_ST_BUFSZ_SHIFT) + +#define CP_ST_BUFSZ_SET_ST_BUFSZ(cp_st_bufsz_reg, st_bufsz) \ + cp_st_bufsz_reg = (cp_st_bufsz_reg & ~CP_ST_BUFSZ_ST_BUFSZ_MASK) | (st_bufsz << CP_ST_BUFSZ_ST_BUFSZ_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_st_bufsz_t { + unsigned int st_bufsz : CP_ST_BUFSZ_ST_BUFSZ_SIZE; + unsigned int : 12; + } cp_st_bufsz_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_st_bufsz_t { + unsigned int : 12; + unsigned int st_bufsz : CP_ST_BUFSZ_ST_BUFSZ_SIZE; + } cp_st_bufsz_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_st_bufsz_t f; +} cp_st_bufsz_u; + + +/* + * CP_QUEUE_THRESHOLDS struct + */ + +#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE 4 +#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE 4 +#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE 4 + +#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT 0 +#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT 8 +#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT 16 + +#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK 0x0000000f +#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK 0x00000f00 +#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK 0x000f0000 + +#define CP_QUEUE_THRESHOLDS_MASK \ + (CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK | \ + CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK | \ + CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) + +#define CP_QUEUE_THRESHOLDS(csq_ib1_start, csq_ib2_start, csq_st_start) \ + ((csq_ib1_start << CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT) | \ + (csq_ib2_start << CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT) | \ + (csq_st_start << CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT)) + +#define CP_QUEUE_THRESHOLDS_GET_CSQ_IB1_START(cp_queue_thresholds) \ + ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT) +#define CP_QUEUE_THRESHOLDS_GET_CSQ_IB2_START(cp_queue_thresholds) \ + ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT) +#define CP_QUEUE_THRESHOLDS_GET_CSQ_ST_START(cp_queue_thresholds) \ + ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT) + +#define CP_QUEUE_THRESHOLDS_SET_CSQ_IB1_START(cp_queue_thresholds_reg, csq_ib1_start) \ + cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK) | (csq_ib1_start << CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT) +#define CP_QUEUE_THRESHOLDS_SET_CSQ_IB2_START(cp_queue_thresholds_reg, csq_ib2_start) \ + cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK) | (csq_ib2_start << CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT) +#define CP_QUEUE_THRESHOLDS_SET_CSQ_ST_START(cp_queue_thresholds_reg, csq_st_start) \ + cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) | (csq_st_start << CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_queue_thresholds_t { + unsigned int csq_ib1_start : CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE; + unsigned int : 4; + unsigned int csq_ib2_start : CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE; + unsigned int : 4; + unsigned int csq_st_start : CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE; + unsigned int : 12; + } cp_queue_thresholds_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_queue_thresholds_t { + unsigned int : 12; + unsigned int csq_st_start : CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE; + unsigned int : 4; + unsigned int csq_ib2_start : CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE; + unsigned int : 4; + unsigned int csq_ib1_start : CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE; + } cp_queue_thresholds_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_queue_thresholds_t f; +} cp_queue_thresholds_u; + + +/* + * CP_MEQ_THRESHOLDS struct + */ + +#define CP_MEQ_THRESHOLDS_MEQ_END_SIZE 5 +#define CP_MEQ_THRESHOLDS_ROQ_END_SIZE 5 + +#define CP_MEQ_THRESHOLDS_MEQ_END_SHIFT 16 +#define CP_MEQ_THRESHOLDS_ROQ_END_SHIFT 24 + +#define CP_MEQ_THRESHOLDS_MEQ_END_MASK 0x001f0000 +#define CP_MEQ_THRESHOLDS_ROQ_END_MASK 0x1f000000 + +#define CP_MEQ_THRESHOLDS_MASK \ + (CP_MEQ_THRESHOLDS_MEQ_END_MASK | \ + CP_MEQ_THRESHOLDS_ROQ_END_MASK) + +#define CP_MEQ_THRESHOLDS(meq_end, roq_end) \ + ((meq_end << CP_MEQ_THRESHOLDS_MEQ_END_SHIFT) | \ + (roq_end << CP_MEQ_THRESHOLDS_ROQ_END_SHIFT)) + +#define CP_MEQ_THRESHOLDS_GET_MEQ_END(cp_meq_thresholds) \ + ((cp_meq_thresholds & CP_MEQ_THRESHOLDS_MEQ_END_MASK) >> CP_MEQ_THRESHOLDS_MEQ_END_SHIFT) +#define CP_MEQ_THRESHOLDS_GET_ROQ_END(cp_meq_thresholds) \ + ((cp_meq_thresholds & CP_MEQ_THRESHOLDS_ROQ_END_MASK) >> CP_MEQ_THRESHOLDS_ROQ_END_SHIFT) + +#define CP_MEQ_THRESHOLDS_SET_MEQ_END(cp_meq_thresholds_reg, meq_end) \ + cp_meq_thresholds_reg = (cp_meq_thresholds_reg & ~CP_MEQ_THRESHOLDS_MEQ_END_MASK) | (meq_end << CP_MEQ_THRESHOLDS_MEQ_END_SHIFT) +#define CP_MEQ_THRESHOLDS_SET_ROQ_END(cp_meq_thresholds_reg, roq_end) \ + cp_meq_thresholds_reg = (cp_meq_thresholds_reg & ~CP_MEQ_THRESHOLDS_ROQ_END_MASK) | (roq_end << CP_MEQ_THRESHOLDS_ROQ_END_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_meq_thresholds_t { + unsigned int : 16; + unsigned int meq_end : CP_MEQ_THRESHOLDS_MEQ_END_SIZE; + unsigned int : 3; + unsigned int roq_end : CP_MEQ_THRESHOLDS_ROQ_END_SIZE; + unsigned int : 3; + } cp_meq_thresholds_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_meq_thresholds_t { + unsigned int : 3; + unsigned int roq_end : CP_MEQ_THRESHOLDS_ROQ_END_SIZE; + unsigned int : 3; + unsigned int meq_end : CP_MEQ_THRESHOLDS_MEQ_END_SIZE; + unsigned int : 16; + } cp_meq_thresholds_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_meq_thresholds_t f; +} cp_meq_thresholds_u; + + +/* + * CP_CSQ_AVAIL struct + */ + +#define CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE 7 +#define CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE 7 +#define CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE 7 + +#define CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT 0 +#define CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT 8 +#define CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT 16 + +#define CP_CSQ_AVAIL_CSQ_CNT_RING_MASK 0x0000007f +#define CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK 0x00007f00 +#define CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK 0x007f0000 + +#define CP_CSQ_AVAIL_MASK \ + (CP_CSQ_AVAIL_CSQ_CNT_RING_MASK | \ + CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK | \ + CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) + +#define CP_CSQ_AVAIL(csq_cnt_ring, csq_cnt_ib1, csq_cnt_ib2) \ + ((csq_cnt_ring << CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT) | \ + (csq_cnt_ib1 << CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT) | \ + (csq_cnt_ib2 << CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT)) + +#define CP_CSQ_AVAIL_GET_CSQ_CNT_RING(cp_csq_avail) \ + ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_RING_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT) +#define CP_CSQ_AVAIL_GET_CSQ_CNT_IB1(cp_csq_avail) \ + ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT) +#define CP_CSQ_AVAIL_GET_CSQ_CNT_IB2(cp_csq_avail) \ + ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT) + +#define CP_CSQ_AVAIL_SET_CSQ_CNT_RING(cp_csq_avail_reg, csq_cnt_ring) \ + cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_RING_MASK) | (csq_cnt_ring << CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT) +#define CP_CSQ_AVAIL_SET_CSQ_CNT_IB1(cp_csq_avail_reg, csq_cnt_ib1) \ + cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK) | (csq_cnt_ib1 << CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT) +#define CP_CSQ_AVAIL_SET_CSQ_CNT_IB2(cp_csq_avail_reg, csq_cnt_ib2) \ + cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) | (csq_cnt_ib2 << CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_csq_avail_t { + unsigned int csq_cnt_ring : CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE; + unsigned int : 1; + unsigned int csq_cnt_ib1 : CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE; + unsigned int : 1; + unsigned int csq_cnt_ib2 : CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE; + unsigned int : 9; + } cp_csq_avail_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_csq_avail_t { + unsigned int : 9; + unsigned int csq_cnt_ib2 : CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE; + unsigned int : 1; + unsigned int csq_cnt_ib1 : CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE; + unsigned int : 1; + unsigned int csq_cnt_ring : CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE; + } cp_csq_avail_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_csq_avail_t f; +} cp_csq_avail_u; + + +/* + * CP_STQ_AVAIL struct + */ + +#define CP_STQ_AVAIL_STQ_CNT_ST_SIZE 7 + +#define CP_STQ_AVAIL_STQ_CNT_ST_SHIFT 0 + +#define CP_STQ_AVAIL_STQ_CNT_ST_MASK 0x0000007f + +#define CP_STQ_AVAIL_MASK \ + (CP_STQ_AVAIL_STQ_CNT_ST_MASK) + +#define CP_STQ_AVAIL(stq_cnt_st) \ + ((stq_cnt_st << CP_STQ_AVAIL_STQ_CNT_ST_SHIFT)) + +#define CP_STQ_AVAIL_GET_STQ_CNT_ST(cp_stq_avail) \ + ((cp_stq_avail & CP_STQ_AVAIL_STQ_CNT_ST_MASK) >> CP_STQ_AVAIL_STQ_CNT_ST_SHIFT) + +#define CP_STQ_AVAIL_SET_STQ_CNT_ST(cp_stq_avail_reg, stq_cnt_st) \ + cp_stq_avail_reg = (cp_stq_avail_reg & ~CP_STQ_AVAIL_STQ_CNT_ST_MASK) | (stq_cnt_st << CP_STQ_AVAIL_STQ_CNT_ST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_stq_avail_t { + unsigned int stq_cnt_st : CP_STQ_AVAIL_STQ_CNT_ST_SIZE; + unsigned int : 25; + } cp_stq_avail_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_stq_avail_t { + unsigned int : 25; + unsigned int stq_cnt_st : CP_STQ_AVAIL_STQ_CNT_ST_SIZE; + } cp_stq_avail_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_stq_avail_t f; +} cp_stq_avail_u; + + +/* + * CP_MEQ_AVAIL struct + */ + +#define CP_MEQ_AVAIL_MEQ_CNT_SIZE 5 + +#define CP_MEQ_AVAIL_MEQ_CNT_SHIFT 0 + +#define CP_MEQ_AVAIL_MEQ_CNT_MASK 0x0000001f + +#define CP_MEQ_AVAIL_MASK \ + (CP_MEQ_AVAIL_MEQ_CNT_MASK) + +#define CP_MEQ_AVAIL(meq_cnt) \ + ((meq_cnt << CP_MEQ_AVAIL_MEQ_CNT_SHIFT)) + +#define CP_MEQ_AVAIL_GET_MEQ_CNT(cp_meq_avail) \ + ((cp_meq_avail & CP_MEQ_AVAIL_MEQ_CNT_MASK) >> CP_MEQ_AVAIL_MEQ_CNT_SHIFT) + +#define CP_MEQ_AVAIL_SET_MEQ_CNT(cp_meq_avail_reg, meq_cnt) \ + cp_meq_avail_reg = (cp_meq_avail_reg & ~CP_MEQ_AVAIL_MEQ_CNT_MASK) | (meq_cnt << CP_MEQ_AVAIL_MEQ_CNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_meq_avail_t { + unsigned int meq_cnt : CP_MEQ_AVAIL_MEQ_CNT_SIZE; + unsigned int : 27; + } cp_meq_avail_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_meq_avail_t { + unsigned int : 27; + unsigned int meq_cnt : CP_MEQ_AVAIL_MEQ_CNT_SIZE; + } cp_meq_avail_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_meq_avail_t f; +} cp_meq_avail_u; + + +/* + * CP_CSQ_RB_STAT struct + */ + +#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE 7 +#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE 7 + +#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT 0 +#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT 16 + +#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK 0x0000007f +#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK 0x007f0000 + +#define CP_CSQ_RB_STAT_MASK \ + (CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK | \ + CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) + +#define CP_CSQ_RB_STAT(csq_rptr_primary, csq_wptr_primary) \ + ((csq_rptr_primary << CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT) | \ + (csq_wptr_primary << CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT)) + +#define CP_CSQ_RB_STAT_GET_CSQ_RPTR_PRIMARY(cp_csq_rb_stat) \ + ((cp_csq_rb_stat & CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK) >> CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT) +#define CP_CSQ_RB_STAT_GET_CSQ_WPTR_PRIMARY(cp_csq_rb_stat) \ + ((cp_csq_rb_stat & CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) >> CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT) + +#define CP_CSQ_RB_STAT_SET_CSQ_RPTR_PRIMARY(cp_csq_rb_stat_reg, csq_rptr_primary) \ + cp_csq_rb_stat_reg = (cp_csq_rb_stat_reg & ~CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK) | (csq_rptr_primary << CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT) +#define CP_CSQ_RB_STAT_SET_CSQ_WPTR_PRIMARY(cp_csq_rb_stat_reg, csq_wptr_primary) \ + cp_csq_rb_stat_reg = (cp_csq_rb_stat_reg & ~CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) | (csq_wptr_primary << CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_csq_rb_stat_t { + unsigned int csq_rptr_primary : CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE; + unsigned int : 9; + unsigned int csq_wptr_primary : CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE; + unsigned int : 9; + } cp_csq_rb_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_csq_rb_stat_t { + unsigned int : 9; + unsigned int csq_wptr_primary : CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE; + unsigned int : 9; + unsigned int csq_rptr_primary : CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE; + } cp_csq_rb_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_csq_rb_stat_t f; +} cp_csq_rb_stat_u; + + +/* + * CP_CSQ_IB1_STAT struct + */ + +#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE 7 +#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE 7 + +#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT 0 +#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT 16 + +#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK 0x0000007f +#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK 0x007f0000 + +#define CP_CSQ_IB1_STAT_MASK \ + (CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK | \ + CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) + +#define CP_CSQ_IB1_STAT(csq_rptr_indirect1, csq_wptr_indirect1) \ + ((csq_rptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT) | \ + (csq_wptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT)) + +#define CP_CSQ_IB1_STAT_GET_CSQ_RPTR_INDIRECT1(cp_csq_ib1_stat) \ + ((cp_csq_ib1_stat & CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK) >> CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT) +#define CP_CSQ_IB1_STAT_GET_CSQ_WPTR_INDIRECT1(cp_csq_ib1_stat) \ + ((cp_csq_ib1_stat & CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) >> CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT) + +#define CP_CSQ_IB1_STAT_SET_CSQ_RPTR_INDIRECT1(cp_csq_ib1_stat_reg, csq_rptr_indirect1) \ + cp_csq_ib1_stat_reg = (cp_csq_ib1_stat_reg & ~CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK) | (csq_rptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT) +#define CP_CSQ_IB1_STAT_SET_CSQ_WPTR_INDIRECT1(cp_csq_ib1_stat_reg, csq_wptr_indirect1) \ + cp_csq_ib1_stat_reg = (cp_csq_ib1_stat_reg & ~CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) | (csq_wptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_csq_ib1_stat_t { + unsigned int csq_rptr_indirect1 : CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE; + unsigned int : 9; + unsigned int csq_wptr_indirect1 : CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE; + unsigned int : 9; + } cp_csq_ib1_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_csq_ib1_stat_t { + unsigned int : 9; + unsigned int csq_wptr_indirect1 : CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE; + unsigned int : 9; + unsigned int csq_rptr_indirect1 : CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE; + } cp_csq_ib1_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_csq_ib1_stat_t f; +} cp_csq_ib1_stat_u; + + +/* + * CP_CSQ_IB2_STAT struct + */ + +#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE 7 +#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE 7 + +#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT 0 +#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT 16 + +#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK 0x0000007f +#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK 0x007f0000 + +#define CP_CSQ_IB2_STAT_MASK \ + (CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK | \ + CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) + +#define CP_CSQ_IB2_STAT(csq_rptr_indirect2, csq_wptr_indirect2) \ + ((csq_rptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT) | \ + (csq_wptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT)) + +#define CP_CSQ_IB2_STAT_GET_CSQ_RPTR_INDIRECT2(cp_csq_ib2_stat) \ + ((cp_csq_ib2_stat & CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK) >> CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT) +#define CP_CSQ_IB2_STAT_GET_CSQ_WPTR_INDIRECT2(cp_csq_ib2_stat) \ + ((cp_csq_ib2_stat & CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) >> CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT) + +#define CP_CSQ_IB2_STAT_SET_CSQ_RPTR_INDIRECT2(cp_csq_ib2_stat_reg, csq_rptr_indirect2) \ + cp_csq_ib2_stat_reg = (cp_csq_ib2_stat_reg & ~CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK) | (csq_rptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT) +#define CP_CSQ_IB2_STAT_SET_CSQ_WPTR_INDIRECT2(cp_csq_ib2_stat_reg, csq_wptr_indirect2) \ + cp_csq_ib2_stat_reg = (cp_csq_ib2_stat_reg & ~CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) | (csq_wptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_csq_ib2_stat_t { + unsigned int csq_rptr_indirect2 : CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE; + unsigned int : 9; + unsigned int csq_wptr_indirect2 : CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE; + unsigned int : 9; + } cp_csq_ib2_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_csq_ib2_stat_t { + unsigned int : 9; + unsigned int csq_wptr_indirect2 : CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE; + unsigned int : 9; + unsigned int csq_rptr_indirect2 : CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE; + } cp_csq_ib2_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_csq_ib2_stat_t f; +} cp_csq_ib2_stat_u; + + +/* + * CP_NON_PREFETCH_CNTRS struct + */ + +#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE 3 +#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE 3 + +#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT 0 +#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT 8 + +#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK 0x00000007 +#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK 0x00000700 + +#define CP_NON_PREFETCH_CNTRS_MASK \ + (CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK | \ + CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) + +#define CP_NON_PREFETCH_CNTRS(ib1_counter, ib2_counter) \ + ((ib1_counter << CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT) | \ + (ib2_counter << CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT)) + +#define CP_NON_PREFETCH_CNTRS_GET_IB1_COUNTER(cp_non_prefetch_cntrs) \ + ((cp_non_prefetch_cntrs & CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK) >> CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT) +#define CP_NON_PREFETCH_CNTRS_GET_IB2_COUNTER(cp_non_prefetch_cntrs) \ + ((cp_non_prefetch_cntrs & CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) >> CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT) + +#define CP_NON_PREFETCH_CNTRS_SET_IB1_COUNTER(cp_non_prefetch_cntrs_reg, ib1_counter) \ + cp_non_prefetch_cntrs_reg = (cp_non_prefetch_cntrs_reg & ~CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK) | (ib1_counter << CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT) +#define CP_NON_PREFETCH_CNTRS_SET_IB2_COUNTER(cp_non_prefetch_cntrs_reg, ib2_counter) \ + cp_non_prefetch_cntrs_reg = (cp_non_prefetch_cntrs_reg & ~CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) | (ib2_counter << CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_non_prefetch_cntrs_t { + unsigned int ib1_counter : CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE; + unsigned int : 5; + unsigned int ib2_counter : CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE; + unsigned int : 21; + } cp_non_prefetch_cntrs_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_non_prefetch_cntrs_t { + unsigned int : 21; + unsigned int ib2_counter : CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE; + unsigned int : 5; + unsigned int ib1_counter : CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE; + } cp_non_prefetch_cntrs_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_non_prefetch_cntrs_t f; +} cp_non_prefetch_cntrs_u; + + +/* + * CP_STQ_ST_STAT struct + */ + +#define CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE 7 +#define CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE 7 + +#define CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT 0 +#define CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT 16 + +#define CP_STQ_ST_STAT_STQ_RPTR_ST_MASK 0x0000007f +#define CP_STQ_ST_STAT_STQ_WPTR_ST_MASK 0x007f0000 + +#define CP_STQ_ST_STAT_MASK \ + (CP_STQ_ST_STAT_STQ_RPTR_ST_MASK | \ + CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) + +#define CP_STQ_ST_STAT(stq_rptr_st, stq_wptr_st) \ + ((stq_rptr_st << CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT) | \ + (stq_wptr_st << CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT)) + +#define CP_STQ_ST_STAT_GET_STQ_RPTR_ST(cp_stq_st_stat) \ + ((cp_stq_st_stat & CP_STQ_ST_STAT_STQ_RPTR_ST_MASK) >> CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT) +#define CP_STQ_ST_STAT_GET_STQ_WPTR_ST(cp_stq_st_stat) \ + ((cp_stq_st_stat & CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) >> CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT) + +#define CP_STQ_ST_STAT_SET_STQ_RPTR_ST(cp_stq_st_stat_reg, stq_rptr_st) \ + cp_stq_st_stat_reg = (cp_stq_st_stat_reg & ~CP_STQ_ST_STAT_STQ_RPTR_ST_MASK) | (stq_rptr_st << CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT) +#define CP_STQ_ST_STAT_SET_STQ_WPTR_ST(cp_stq_st_stat_reg, stq_wptr_st) \ + cp_stq_st_stat_reg = (cp_stq_st_stat_reg & ~CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) | (stq_wptr_st << CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_stq_st_stat_t { + unsigned int stq_rptr_st : CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE; + unsigned int : 9; + unsigned int stq_wptr_st : CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE; + unsigned int : 9; + } cp_stq_st_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_stq_st_stat_t { + unsigned int : 9; + unsigned int stq_wptr_st : CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE; + unsigned int : 9; + unsigned int stq_rptr_st : CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE; + } cp_stq_st_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_stq_st_stat_t f; +} cp_stq_st_stat_u; + + +/* + * CP_MEQ_STAT struct + */ + +#define CP_MEQ_STAT_MEQ_RPTR_SIZE 10 +#define CP_MEQ_STAT_MEQ_WPTR_SIZE 10 + +#define CP_MEQ_STAT_MEQ_RPTR_SHIFT 0 +#define CP_MEQ_STAT_MEQ_WPTR_SHIFT 16 + +#define CP_MEQ_STAT_MEQ_RPTR_MASK 0x000003ff +#define CP_MEQ_STAT_MEQ_WPTR_MASK 0x03ff0000 + +#define CP_MEQ_STAT_MASK \ + (CP_MEQ_STAT_MEQ_RPTR_MASK | \ + CP_MEQ_STAT_MEQ_WPTR_MASK) + +#define CP_MEQ_STAT(meq_rptr, meq_wptr) \ + ((meq_rptr << CP_MEQ_STAT_MEQ_RPTR_SHIFT) | \ + (meq_wptr << CP_MEQ_STAT_MEQ_WPTR_SHIFT)) + +#define CP_MEQ_STAT_GET_MEQ_RPTR(cp_meq_stat) \ + ((cp_meq_stat & CP_MEQ_STAT_MEQ_RPTR_MASK) >> CP_MEQ_STAT_MEQ_RPTR_SHIFT) +#define CP_MEQ_STAT_GET_MEQ_WPTR(cp_meq_stat) \ + ((cp_meq_stat & CP_MEQ_STAT_MEQ_WPTR_MASK) >> CP_MEQ_STAT_MEQ_WPTR_SHIFT) + +#define CP_MEQ_STAT_SET_MEQ_RPTR(cp_meq_stat_reg, meq_rptr) \ + cp_meq_stat_reg = (cp_meq_stat_reg & ~CP_MEQ_STAT_MEQ_RPTR_MASK) | (meq_rptr << CP_MEQ_STAT_MEQ_RPTR_SHIFT) +#define CP_MEQ_STAT_SET_MEQ_WPTR(cp_meq_stat_reg, meq_wptr) \ + cp_meq_stat_reg = (cp_meq_stat_reg & ~CP_MEQ_STAT_MEQ_WPTR_MASK) | (meq_wptr << CP_MEQ_STAT_MEQ_WPTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_meq_stat_t { + unsigned int meq_rptr : CP_MEQ_STAT_MEQ_RPTR_SIZE; + unsigned int : 6; + unsigned int meq_wptr : CP_MEQ_STAT_MEQ_WPTR_SIZE; + unsigned int : 6; + } cp_meq_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_meq_stat_t { + unsigned int : 6; + unsigned int meq_wptr : CP_MEQ_STAT_MEQ_WPTR_SIZE; + unsigned int : 6; + unsigned int meq_rptr : CP_MEQ_STAT_MEQ_RPTR_SIZE; + } cp_meq_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_meq_stat_t f; +} cp_meq_stat_u; + + +/* + * CP_MIU_TAG_STAT struct + */ + +#define CP_MIU_TAG_STAT_TAG_0_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_1_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_2_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_3_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_4_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_5_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_6_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_7_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_8_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_9_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_10_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_11_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_12_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_13_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_14_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_15_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_16_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_17_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE 1 + +#define CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT 0 +#define CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT 1 +#define CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT 2 +#define CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT 3 +#define CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT 4 +#define CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT 5 +#define CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT 6 +#define CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT 7 +#define CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT 8 +#define CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT 9 +#define CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT 10 +#define CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT 11 +#define CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT 12 +#define CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT 13 +#define CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT 14 +#define CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT 15 +#define CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT 16 +#define CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT 17 +#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT 31 + +#define CP_MIU_TAG_STAT_TAG_0_STAT_MASK 0x00000001 +#define CP_MIU_TAG_STAT_TAG_1_STAT_MASK 0x00000002 +#define CP_MIU_TAG_STAT_TAG_2_STAT_MASK 0x00000004 +#define CP_MIU_TAG_STAT_TAG_3_STAT_MASK 0x00000008 +#define CP_MIU_TAG_STAT_TAG_4_STAT_MASK 0x00000010 +#define CP_MIU_TAG_STAT_TAG_5_STAT_MASK 0x00000020 +#define CP_MIU_TAG_STAT_TAG_6_STAT_MASK 0x00000040 +#define CP_MIU_TAG_STAT_TAG_7_STAT_MASK 0x00000080 +#define CP_MIU_TAG_STAT_TAG_8_STAT_MASK 0x00000100 +#define CP_MIU_TAG_STAT_TAG_9_STAT_MASK 0x00000200 +#define CP_MIU_TAG_STAT_TAG_10_STAT_MASK 0x00000400 +#define CP_MIU_TAG_STAT_TAG_11_STAT_MASK 0x00000800 +#define CP_MIU_TAG_STAT_TAG_12_STAT_MASK 0x00001000 +#define CP_MIU_TAG_STAT_TAG_13_STAT_MASK 0x00002000 +#define CP_MIU_TAG_STAT_TAG_14_STAT_MASK 0x00004000 +#define CP_MIU_TAG_STAT_TAG_15_STAT_MASK 0x00008000 +#define CP_MIU_TAG_STAT_TAG_16_STAT_MASK 0x00010000 +#define CP_MIU_TAG_STAT_TAG_17_STAT_MASK 0x00020000 +#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK 0x80000000 + +#define CP_MIU_TAG_STAT_MASK \ + (CP_MIU_TAG_STAT_TAG_0_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_1_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_2_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_3_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_4_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_5_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_6_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_7_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_8_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_9_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_10_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_11_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_12_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_13_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_14_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_15_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_16_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_17_STAT_MASK | \ + CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) + +#define CP_MIU_TAG_STAT(tag_0_stat, tag_1_stat, tag_2_stat, tag_3_stat, tag_4_stat, tag_5_stat, tag_6_stat, tag_7_stat, tag_8_stat, tag_9_stat, tag_10_stat, tag_11_stat, tag_12_stat, tag_13_stat, tag_14_stat, tag_15_stat, tag_16_stat, tag_17_stat, invalid_return_tag) \ + ((tag_0_stat << CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT) | \ + (tag_1_stat << CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT) | \ + (tag_2_stat << CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT) | \ + (tag_3_stat << CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT) | \ + (tag_4_stat << CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT) | \ + (tag_5_stat << CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT) | \ + (tag_6_stat << CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT) | \ + (tag_7_stat << CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT) | \ + (tag_8_stat << CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT) | \ + (tag_9_stat << CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT) | \ + (tag_10_stat << CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT) | \ + (tag_11_stat << CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT) | \ + (tag_12_stat << CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT) | \ + (tag_13_stat << CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT) | \ + (tag_14_stat << CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT) | \ + (tag_15_stat << CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT) | \ + (tag_16_stat << CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT) | \ + (tag_17_stat << CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT) | \ + (invalid_return_tag << CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT)) + +#define CP_MIU_TAG_STAT_GET_TAG_0_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_0_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_1_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_1_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_2_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_2_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_3_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_3_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_4_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_4_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_5_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_5_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_6_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_6_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_7_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_7_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_8_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_8_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_9_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_9_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_10_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_10_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_11_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_11_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_12_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_12_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_13_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_13_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_14_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_14_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_15_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_15_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_16_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_16_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_17_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_17_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_INVALID_RETURN_TAG(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) >> CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT) + +#define CP_MIU_TAG_STAT_SET_TAG_0_STAT(cp_miu_tag_stat_reg, tag_0_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_0_STAT_MASK) | (tag_0_stat << CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_1_STAT(cp_miu_tag_stat_reg, tag_1_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_1_STAT_MASK) | (tag_1_stat << CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_2_STAT(cp_miu_tag_stat_reg, tag_2_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_2_STAT_MASK) | (tag_2_stat << CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_3_STAT(cp_miu_tag_stat_reg, tag_3_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_3_STAT_MASK) | (tag_3_stat << CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_4_STAT(cp_miu_tag_stat_reg, tag_4_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_4_STAT_MASK) | (tag_4_stat << CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_5_STAT(cp_miu_tag_stat_reg, tag_5_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_5_STAT_MASK) | (tag_5_stat << CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_6_STAT(cp_miu_tag_stat_reg, tag_6_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_6_STAT_MASK) | (tag_6_stat << CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_7_STAT(cp_miu_tag_stat_reg, tag_7_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_7_STAT_MASK) | (tag_7_stat << CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_8_STAT(cp_miu_tag_stat_reg, tag_8_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_8_STAT_MASK) | (tag_8_stat << CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_9_STAT(cp_miu_tag_stat_reg, tag_9_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_9_STAT_MASK) | (tag_9_stat << CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_10_STAT(cp_miu_tag_stat_reg, tag_10_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_10_STAT_MASK) | (tag_10_stat << CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_11_STAT(cp_miu_tag_stat_reg, tag_11_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_11_STAT_MASK) | (tag_11_stat << CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_12_STAT(cp_miu_tag_stat_reg, tag_12_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_12_STAT_MASK) | (tag_12_stat << CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_13_STAT(cp_miu_tag_stat_reg, tag_13_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_13_STAT_MASK) | (tag_13_stat << CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_14_STAT(cp_miu_tag_stat_reg, tag_14_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_14_STAT_MASK) | (tag_14_stat << CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_15_STAT(cp_miu_tag_stat_reg, tag_15_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_15_STAT_MASK) | (tag_15_stat << CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_16_STAT(cp_miu_tag_stat_reg, tag_16_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_16_STAT_MASK) | (tag_16_stat << CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_17_STAT(cp_miu_tag_stat_reg, tag_17_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_17_STAT_MASK) | (tag_17_stat << CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_INVALID_RETURN_TAG(cp_miu_tag_stat_reg, invalid_return_tag) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) | (invalid_return_tag << CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_miu_tag_stat_t { + unsigned int tag_0_stat : CP_MIU_TAG_STAT_TAG_0_STAT_SIZE; + unsigned int tag_1_stat : CP_MIU_TAG_STAT_TAG_1_STAT_SIZE; + unsigned int tag_2_stat : CP_MIU_TAG_STAT_TAG_2_STAT_SIZE; + unsigned int tag_3_stat : CP_MIU_TAG_STAT_TAG_3_STAT_SIZE; + unsigned int tag_4_stat : CP_MIU_TAG_STAT_TAG_4_STAT_SIZE; + unsigned int tag_5_stat : CP_MIU_TAG_STAT_TAG_5_STAT_SIZE; + unsigned int tag_6_stat : CP_MIU_TAG_STAT_TAG_6_STAT_SIZE; + unsigned int tag_7_stat : CP_MIU_TAG_STAT_TAG_7_STAT_SIZE; + unsigned int tag_8_stat : CP_MIU_TAG_STAT_TAG_8_STAT_SIZE; + unsigned int tag_9_stat : CP_MIU_TAG_STAT_TAG_9_STAT_SIZE; + unsigned int tag_10_stat : CP_MIU_TAG_STAT_TAG_10_STAT_SIZE; + unsigned int tag_11_stat : CP_MIU_TAG_STAT_TAG_11_STAT_SIZE; + unsigned int tag_12_stat : CP_MIU_TAG_STAT_TAG_12_STAT_SIZE; + unsigned int tag_13_stat : CP_MIU_TAG_STAT_TAG_13_STAT_SIZE; + unsigned int tag_14_stat : CP_MIU_TAG_STAT_TAG_14_STAT_SIZE; + unsigned int tag_15_stat : CP_MIU_TAG_STAT_TAG_15_STAT_SIZE; + unsigned int tag_16_stat : CP_MIU_TAG_STAT_TAG_16_STAT_SIZE; + unsigned int tag_17_stat : CP_MIU_TAG_STAT_TAG_17_STAT_SIZE; + unsigned int : 13; + unsigned int invalid_return_tag : CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE; + } cp_miu_tag_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_miu_tag_stat_t { + unsigned int invalid_return_tag : CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE; + unsigned int : 13; + unsigned int tag_17_stat : CP_MIU_TAG_STAT_TAG_17_STAT_SIZE; + unsigned int tag_16_stat : CP_MIU_TAG_STAT_TAG_16_STAT_SIZE; + unsigned int tag_15_stat : CP_MIU_TAG_STAT_TAG_15_STAT_SIZE; + unsigned int tag_14_stat : CP_MIU_TAG_STAT_TAG_14_STAT_SIZE; + unsigned int tag_13_stat : CP_MIU_TAG_STAT_TAG_13_STAT_SIZE; + unsigned int tag_12_stat : CP_MIU_TAG_STAT_TAG_12_STAT_SIZE; + unsigned int tag_11_stat : CP_MIU_TAG_STAT_TAG_11_STAT_SIZE; + unsigned int tag_10_stat : CP_MIU_TAG_STAT_TAG_10_STAT_SIZE; + unsigned int tag_9_stat : CP_MIU_TAG_STAT_TAG_9_STAT_SIZE; + unsigned int tag_8_stat : CP_MIU_TAG_STAT_TAG_8_STAT_SIZE; + unsigned int tag_7_stat : CP_MIU_TAG_STAT_TAG_7_STAT_SIZE; + unsigned int tag_6_stat : CP_MIU_TAG_STAT_TAG_6_STAT_SIZE; + unsigned int tag_5_stat : CP_MIU_TAG_STAT_TAG_5_STAT_SIZE; + unsigned int tag_4_stat : CP_MIU_TAG_STAT_TAG_4_STAT_SIZE; + unsigned int tag_3_stat : CP_MIU_TAG_STAT_TAG_3_STAT_SIZE; + unsigned int tag_2_stat : CP_MIU_TAG_STAT_TAG_2_STAT_SIZE; + unsigned int tag_1_stat : CP_MIU_TAG_STAT_TAG_1_STAT_SIZE; + unsigned int tag_0_stat : CP_MIU_TAG_STAT_TAG_0_STAT_SIZE; + } cp_miu_tag_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_miu_tag_stat_t f; +} cp_miu_tag_stat_u; + + +/* + * CP_CMD_INDEX struct + */ + +#define CP_CMD_INDEX_CMD_INDEX_SIZE 7 +#define CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE 2 + +#define CP_CMD_INDEX_CMD_INDEX_SHIFT 0 +#define CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT 16 + +#define CP_CMD_INDEX_CMD_INDEX_MASK 0x0000007f +#define CP_CMD_INDEX_CMD_QUEUE_SEL_MASK 0x00030000 + +#define CP_CMD_INDEX_MASK \ + (CP_CMD_INDEX_CMD_INDEX_MASK | \ + CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) + +#define CP_CMD_INDEX(cmd_index, cmd_queue_sel) \ + ((cmd_index << CP_CMD_INDEX_CMD_INDEX_SHIFT) | \ + (cmd_queue_sel << CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT)) + +#define CP_CMD_INDEX_GET_CMD_INDEX(cp_cmd_index) \ + ((cp_cmd_index & CP_CMD_INDEX_CMD_INDEX_MASK) >> CP_CMD_INDEX_CMD_INDEX_SHIFT) +#define CP_CMD_INDEX_GET_CMD_QUEUE_SEL(cp_cmd_index) \ + ((cp_cmd_index & CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) >> CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT) + +#define CP_CMD_INDEX_SET_CMD_INDEX(cp_cmd_index_reg, cmd_index) \ + cp_cmd_index_reg = (cp_cmd_index_reg & ~CP_CMD_INDEX_CMD_INDEX_MASK) | (cmd_index << CP_CMD_INDEX_CMD_INDEX_SHIFT) +#define CP_CMD_INDEX_SET_CMD_QUEUE_SEL(cp_cmd_index_reg, cmd_queue_sel) \ + cp_cmd_index_reg = (cp_cmd_index_reg & ~CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) | (cmd_queue_sel << CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_cmd_index_t { + unsigned int cmd_index : CP_CMD_INDEX_CMD_INDEX_SIZE; + unsigned int : 9; + unsigned int cmd_queue_sel : CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE; + unsigned int : 14; + } cp_cmd_index_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_cmd_index_t { + unsigned int : 14; + unsigned int cmd_queue_sel : CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE; + unsigned int : 9; + unsigned int cmd_index : CP_CMD_INDEX_CMD_INDEX_SIZE; + } cp_cmd_index_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_cmd_index_t f; +} cp_cmd_index_u; + + +/* + * CP_CMD_DATA struct + */ + +#define CP_CMD_DATA_CMD_DATA_SIZE 32 + +#define CP_CMD_DATA_CMD_DATA_SHIFT 0 + +#define CP_CMD_DATA_CMD_DATA_MASK 0xffffffff + +#define CP_CMD_DATA_MASK \ + (CP_CMD_DATA_CMD_DATA_MASK) + +#define CP_CMD_DATA(cmd_data) \ + ((cmd_data << CP_CMD_DATA_CMD_DATA_SHIFT)) + +#define CP_CMD_DATA_GET_CMD_DATA(cp_cmd_data) \ + ((cp_cmd_data & CP_CMD_DATA_CMD_DATA_MASK) >> CP_CMD_DATA_CMD_DATA_SHIFT) + +#define CP_CMD_DATA_SET_CMD_DATA(cp_cmd_data_reg, cmd_data) \ + cp_cmd_data_reg = (cp_cmd_data_reg & ~CP_CMD_DATA_CMD_DATA_MASK) | (cmd_data << CP_CMD_DATA_CMD_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_cmd_data_t { + unsigned int cmd_data : CP_CMD_DATA_CMD_DATA_SIZE; + } cp_cmd_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_cmd_data_t { + unsigned int cmd_data : CP_CMD_DATA_CMD_DATA_SIZE; + } cp_cmd_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_cmd_data_t f; +} cp_cmd_data_u; + + +/* + * CP_ME_CNTL struct + */ + +#define CP_ME_CNTL_ME_STATMUX_SIZE 16 +#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE 1 +#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE 1 +#define CP_ME_CNTL_ME_HALT_SIZE 1 +#define CP_ME_CNTL_ME_BUSY_SIZE 1 +#define CP_ME_CNTL_PROG_CNT_SIZE_SIZE 1 + +#define CP_ME_CNTL_ME_STATMUX_SHIFT 0 +#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT 25 +#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT 26 +#define CP_ME_CNTL_ME_HALT_SHIFT 28 +#define CP_ME_CNTL_ME_BUSY_SHIFT 29 +#define CP_ME_CNTL_PROG_CNT_SIZE_SHIFT 31 + +#define CP_ME_CNTL_ME_STATMUX_MASK 0x0000ffff +#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK 0x02000000 +#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK 0x04000000 +#define CP_ME_CNTL_ME_HALT_MASK 0x10000000 +#define CP_ME_CNTL_ME_BUSY_MASK 0x20000000 +#define CP_ME_CNTL_PROG_CNT_SIZE_MASK 0x80000000 + +#define CP_ME_CNTL_MASK \ + (CP_ME_CNTL_ME_STATMUX_MASK | \ + CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK | \ + CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK | \ + CP_ME_CNTL_ME_HALT_MASK | \ + CP_ME_CNTL_ME_BUSY_MASK | \ + CP_ME_CNTL_PROG_CNT_SIZE_MASK) + +#define CP_ME_CNTL(me_statmux, vtx_dealloc_fifo_empty, pix_dealloc_fifo_empty, me_halt, me_busy, prog_cnt_size) \ + ((me_statmux << CP_ME_CNTL_ME_STATMUX_SHIFT) | \ + (vtx_dealloc_fifo_empty << CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT) | \ + (pix_dealloc_fifo_empty << CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT) | \ + (me_halt << CP_ME_CNTL_ME_HALT_SHIFT) | \ + (me_busy << CP_ME_CNTL_ME_BUSY_SHIFT) | \ + (prog_cnt_size << CP_ME_CNTL_PROG_CNT_SIZE_SHIFT)) + +#define CP_ME_CNTL_GET_ME_STATMUX(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_ME_STATMUX_MASK) >> CP_ME_CNTL_ME_STATMUX_SHIFT) +#define CP_ME_CNTL_GET_VTX_DEALLOC_FIFO_EMPTY(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK) >> CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT) +#define CP_ME_CNTL_GET_PIX_DEALLOC_FIFO_EMPTY(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK) >> CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT) +#define CP_ME_CNTL_GET_ME_HALT(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_ME_HALT_MASK) >> CP_ME_CNTL_ME_HALT_SHIFT) +#define CP_ME_CNTL_GET_ME_BUSY(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_ME_BUSY_MASK) >> CP_ME_CNTL_ME_BUSY_SHIFT) +#define CP_ME_CNTL_GET_PROG_CNT_SIZE(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_PROG_CNT_SIZE_MASK) >> CP_ME_CNTL_PROG_CNT_SIZE_SHIFT) + +#define CP_ME_CNTL_SET_ME_STATMUX(cp_me_cntl_reg, me_statmux) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_STATMUX_MASK) | (me_statmux << CP_ME_CNTL_ME_STATMUX_SHIFT) +#define CP_ME_CNTL_SET_VTX_DEALLOC_FIFO_EMPTY(cp_me_cntl_reg, vtx_dealloc_fifo_empty) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK) | (vtx_dealloc_fifo_empty << CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT) +#define CP_ME_CNTL_SET_PIX_DEALLOC_FIFO_EMPTY(cp_me_cntl_reg, pix_dealloc_fifo_empty) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK) | (pix_dealloc_fifo_empty << CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT) +#define CP_ME_CNTL_SET_ME_HALT(cp_me_cntl_reg, me_halt) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_HALT_MASK) | (me_halt << CP_ME_CNTL_ME_HALT_SHIFT) +#define CP_ME_CNTL_SET_ME_BUSY(cp_me_cntl_reg, me_busy) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_BUSY_MASK) | (me_busy << CP_ME_CNTL_ME_BUSY_SHIFT) +#define CP_ME_CNTL_SET_PROG_CNT_SIZE(cp_me_cntl_reg, prog_cnt_size) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_PROG_CNT_SIZE_MASK) | (prog_cnt_size << CP_ME_CNTL_PROG_CNT_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_cntl_t { + unsigned int me_statmux : CP_ME_CNTL_ME_STATMUX_SIZE; + unsigned int : 9; + unsigned int vtx_dealloc_fifo_empty : CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE; + unsigned int pix_dealloc_fifo_empty : CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE; + unsigned int : 1; + unsigned int me_halt : CP_ME_CNTL_ME_HALT_SIZE; + unsigned int me_busy : CP_ME_CNTL_ME_BUSY_SIZE; + unsigned int : 1; + unsigned int prog_cnt_size : CP_ME_CNTL_PROG_CNT_SIZE_SIZE; + } cp_me_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_cntl_t { + unsigned int prog_cnt_size : CP_ME_CNTL_PROG_CNT_SIZE_SIZE; + unsigned int : 1; + unsigned int me_busy : CP_ME_CNTL_ME_BUSY_SIZE; + unsigned int me_halt : CP_ME_CNTL_ME_HALT_SIZE; + unsigned int : 1; + unsigned int pix_dealloc_fifo_empty : CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE; + unsigned int vtx_dealloc_fifo_empty : CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE; + unsigned int : 9; + unsigned int me_statmux : CP_ME_CNTL_ME_STATMUX_SIZE; + } cp_me_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_cntl_t f; +} cp_me_cntl_u; + + +/* + * CP_ME_STATUS struct + */ + +#define CP_ME_STATUS_ME_DEBUG_DATA_SIZE 32 + +#define CP_ME_STATUS_ME_DEBUG_DATA_SHIFT 0 + +#define CP_ME_STATUS_ME_DEBUG_DATA_MASK 0xffffffff + +#define CP_ME_STATUS_MASK \ + (CP_ME_STATUS_ME_DEBUG_DATA_MASK) + +#define CP_ME_STATUS(me_debug_data) \ + ((me_debug_data << CP_ME_STATUS_ME_DEBUG_DATA_SHIFT)) + +#define CP_ME_STATUS_GET_ME_DEBUG_DATA(cp_me_status) \ + ((cp_me_status & CP_ME_STATUS_ME_DEBUG_DATA_MASK) >> CP_ME_STATUS_ME_DEBUG_DATA_SHIFT) + +#define CP_ME_STATUS_SET_ME_DEBUG_DATA(cp_me_status_reg, me_debug_data) \ + cp_me_status_reg = (cp_me_status_reg & ~CP_ME_STATUS_ME_DEBUG_DATA_MASK) | (me_debug_data << CP_ME_STATUS_ME_DEBUG_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_status_t { + unsigned int me_debug_data : CP_ME_STATUS_ME_DEBUG_DATA_SIZE; + } cp_me_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_status_t { + unsigned int me_debug_data : CP_ME_STATUS_ME_DEBUG_DATA_SIZE; + } cp_me_status_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_status_t f; +} cp_me_status_u; + + +/* + * CP_ME_RAM_WADDR struct + */ + +#define CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE 10 + +#define CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT 0 + +#define CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK 0x000003ff + +#define CP_ME_RAM_WADDR_MASK \ + (CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) + +#define CP_ME_RAM_WADDR(me_ram_waddr) \ + ((me_ram_waddr << CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT)) + +#define CP_ME_RAM_WADDR_GET_ME_RAM_WADDR(cp_me_ram_waddr) \ + ((cp_me_ram_waddr & CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) >> CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT) + +#define CP_ME_RAM_WADDR_SET_ME_RAM_WADDR(cp_me_ram_waddr_reg, me_ram_waddr) \ + cp_me_ram_waddr_reg = (cp_me_ram_waddr_reg & ~CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) | (me_ram_waddr << CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ram_waddr_t { + unsigned int me_ram_waddr : CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE; + unsigned int : 22; + } cp_me_ram_waddr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ram_waddr_t { + unsigned int : 22; + unsigned int me_ram_waddr : CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE; + } cp_me_ram_waddr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ram_waddr_t f; +} cp_me_ram_waddr_u; + + +/* + * CP_ME_RAM_RADDR struct + */ + +#define CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE 10 + +#define CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT 0 + +#define CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK 0x000003ff + +#define CP_ME_RAM_RADDR_MASK \ + (CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) + +#define CP_ME_RAM_RADDR(me_ram_raddr) \ + ((me_ram_raddr << CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT)) + +#define CP_ME_RAM_RADDR_GET_ME_RAM_RADDR(cp_me_ram_raddr) \ + ((cp_me_ram_raddr & CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) >> CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT) + +#define CP_ME_RAM_RADDR_SET_ME_RAM_RADDR(cp_me_ram_raddr_reg, me_ram_raddr) \ + cp_me_ram_raddr_reg = (cp_me_ram_raddr_reg & ~CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) | (me_ram_raddr << CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ram_raddr_t { + unsigned int me_ram_raddr : CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE; + unsigned int : 22; + } cp_me_ram_raddr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ram_raddr_t { + unsigned int : 22; + unsigned int me_ram_raddr : CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE; + } cp_me_ram_raddr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ram_raddr_t f; +} cp_me_ram_raddr_u; + + +/* + * CP_ME_RAM_DATA struct + */ + +#define CP_ME_RAM_DATA_ME_RAM_DATA_SIZE 32 + +#define CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT 0 + +#define CP_ME_RAM_DATA_ME_RAM_DATA_MASK 0xffffffff + +#define CP_ME_RAM_DATA_MASK \ + (CP_ME_RAM_DATA_ME_RAM_DATA_MASK) + +#define CP_ME_RAM_DATA(me_ram_data) \ + ((me_ram_data << CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT)) + +#define CP_ME_RAM_DATA_GET_ME_RAM_DATA(cp_me_ram_data) \ + ((cp_me_ram_data & CP_ME_RAM_DATA_ME_RAM_DATA_MASK) >> CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT) + +#define CP_ME_RAM_DATA_SET_ME_RAM_DATA(cp_me_ram_data_reg, me_ram_data) \ + cp_me_ram_data_reg = (cp_me_ram_data_reg & ~CP_ME_RAM_DATA_ME_RAM_DATA_MASK) | (me_ram_data << CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ram_data_t { + unsigned int me_ram_data : CP_ME_RAM_DATA_ME_RAM_DATA_SIZE; + } cp_me_ram_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ram_data_t { + unsigned int me_ram_data : CP_ME_RAM_DATA_ME_RAM_DATA_SIZE; + } cp_me_ram_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ram_data_t f; +} cp_me_ram_data_u; + + +/* + * CP_ME_RDADDR struct + */ + +#define CP_ME_RDADDR_ME_RDADDR_SIZE 32 + +#define CP_ME_RDADDR_ME_RDADDR_SHIFT 0 + +#define CP_ME_RDADDR_ME_RDADDR_MASK 0xffffffff + +#define CP_ME_RDADDR_MASK \ + (CP_ME_RDADDR_ME_RDADDR_MASK) + +#define CP_ME_RDADDR(me_rdaddr) \ + ((me_rdaddr << CP_ME_RDADDR_ME_RDADDR_SHIFT)) + +#define CP_ME_RDADDR_GET_ME_RDADDR(cp_me_rdaddr) \ + ((cp_me_rdaddr & CP_ME_RDADDR_ME_RDADDR_MASK) >> CP_ME_RDADDR_ME_RDADDR_SHIFT) + +#define CP_ME_RDADDR_SET_ME_RDADDR(cp_me_rdaddr_reg, me_rdaddr) \ + cp_me_rdaddr_reg = (cp_me_rdaddr_reg & ~CP_ME_RDADDR_ME_RDADDR_MASK) | (me_rdaddr << CP_ME_RDADDR_ME_RDADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_rdaddr_t { + unsigned int me_rdaddr : CP_ME_RDADDR_ME_RDADDR_SIZE; + } cp_me_rdaddr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_rdaddr_t { + unsigned int me_rdaddr : CP_ME_RDADDR_ME_RDADDR_SIZE; + } cp_me_rdaddr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_rdaddr_t f; +} cp_me_rdaddr_u; + + +/* + * CP_DEBUG struct + */ + +#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE 23 +#define CP_DEBUG_PREDICATE_DISABLE_SIZE 1 +#define CP_DEBUG_PROG_END_PTR_ENABLE_SIZE 1 +#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE 1 +#define CP_DEBUG_PREFETCH_PASS_NOPS_SIZE 1 +#define CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE 1 +#define CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE 1 +#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE 1 +#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE 1 + +#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT 0 +#define CP_DEBUG_PREDICATE_DISABLE_SHIFT 23 +#define CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT 24 +#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT 25 +#define CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT 26 +#define CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT 27 +#define CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT 28 +#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT 30 +#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT 31 + +#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK 0x007fffff +#define CP_DEBUG_PREDICATE_DISABLE_MASK 0x00800000 +#define CP_DEBUG_PROG_END_PTR_ENABLE_MASK 0x01000000 +#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK 0x02000000 +#define CP_DEBUG_PREFETCH_PASS_NOPS_MASK 0x04000000 +#define CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK 0x08000000 +#define CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK 0x10000000 +#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK 0x40000000 +#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK 0x80000000 + +#define CP_DEBUG_MASK \ + (CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK | \ + CP_DEBUG_PREDICATE_DISABLE_MASK | \ + CP_DEBUG_PROG_END_PTR_ENABLE_MASK | \ + CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK | \ + CP_DEBUG_PREFETCH_PASS_NOPS_MASK | \ + CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK | \ + CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK | \ + CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK | \ + CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) + +#define CP_DEBUG(cp_debug_unused_22_to_0, predicate_disable, prog_end_ptr_enable, miu_128bit_write_enable, prefetch_pass_nops, dynamic_clk_disable, prefetch_match_disable, simple_me_flow_control, miu_write_pack_disable) \ + ((cp_debug_unused_22_to_0 << CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT) | \ + (predicate_disable << CP_DEBUG_PREDICATE_DISABLE_SHIFT) | \ + (prog_end_ptr_enable << CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT) | \ + (miu_128bit_write_enable << CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT) | \ + (prefetch_pass_nops << CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT) | \ + (dynamic_clk_disable << CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT) | \ + (prefetch_match_disable << CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT) | \ + (simple_me_flow_control << CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT) | \ + (miu_write_pack_disable << CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT)) + +#define CP_DEBUG_GET_CP_DEBUG_UNUSED_22_to_0(cp_debug) \ + ((cp_debug & CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK) >> CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT) +#define CP_DEBUG_GET_PREDICATE_DISABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_PREDICATE_DISABLE_MASK) >> CP_DEBUG_PREDICATE_DISABLE_SHIFT) +#define CP_DEBUG_GET_PROG_END_PTR_ENABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_PROG_END_PTR_ENABLE_MASK) >> CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT) +#define CP_DEBUG_GET_MIU_128BIT_WRITE_ENABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK) >> CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT) +#define CP_DEBUG_GET_PREFETCH_PASS_NOPS(cp_debug) \ + ((cp_debug & CP_DEBUG_PREFETCH_PASS_NOPS_MASK) >> CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT) +#define CP_DEBUG_GET_DYNAMIC_CLK_DISABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK) >> CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT) +#define CP_DEBUG_GET_PREFETCH_MATCH_DISABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK) >> CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT) +#define CP_DEBUG_GET_SIMPLE_ME_FLOW_CONTROL(cp_debug) \ + ((cp_debug & CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK) >> CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT) +#define CP_DEBUG_GET_MIU_WRITE_PACK_DISABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) >> CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT) + +#define CP_DEBUG_SET_CP_DEBUG_UNUSED_22_to_0(cp_debug_reg, cp_debug_unused_22_to_0) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK) | (cp_debug_unused_22_to_0 << CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT) +#define CP_DEBUG_SET_PREDICATE_DISABLE(cp_debug_reg, predicate_disable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREDICATE_DISABLE_MASK) | (predicate_disable << CP_DEBUG_PREDICATE_DISABLE_SHIFT) +#define CP_DEBUG_SET_PROG_END_PTR_ENABLE(cp_debug_reg, prog_end_ptr_enable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PROG_END_PTR_ENABLE_MASK) | (prog_end_ptr_enable << CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT) +#define CP_DEBUG_SET_MIU_128BIT_WRITE_ENABLE(cp_debug_reg, miu_128bit_write_enable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK) | (miu_128bit_write_enable << CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT) +#define CP_DEBUG_SET_PREFETCH_PASS_NOPS(cp_debug_reg, prefetch_pass_nops) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREFETCH_PASS_NOPS_MASK) | (prefetch_pass_nops << CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT) +#define CP_DEBUG_SET_DYNAMIC_CLK_DISABLE(cp_debug_reg, dynamic_clk_disable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK) | (dynamic_clk_disable << CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT) +#define CP_DEBUG_SET_PREFETCH_MATCH_DISABLE(cp_debug_reg, prefetch_match_disable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK) | (prefetch_match_disable << CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT) +#define CP_DEBUG_SET_SIMPLE_ME_FLOW_CONTROL(cp_debug_reg, simple_me_flow_control) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK) | (simple_me_flow_control << CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT) +#define CP_DEBUG_SET_MIU_WRITE_PACK_DISABLE(cp_debug_reg, miu_write_pack_disable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) | (miu_write_pack_disable << CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_debug_t { + unsigned int cp_debug_unused_22_to_0 : CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE; + unsigned int predicate_disable : CP_DEBUG_PREDICATE_DISABLE_SIZE; + unsigned int prog_end_ptr_enable : CP_DEBUG_PROG_END_PTR_ENABLE_SIZE; + unsigned int miu_128bit_write_enable : CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE; + unsigned int prefetch_pass_nops : CP_DEBUG_PREFETCH_PASS_NOPS_SIZE; + unsigned int dynamic_clk_disable : CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE; + unsigned int prefetch_match_disable : CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE; + unsigned int : 1; + unsigned int simple_me_flow_control : CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE; + unsigned int miu_write_pack_disable : CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE; + } cp_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_debug_t { + unsigned int miu_write_pack_disable : CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE; + unsigned int simple_me_flow_control : CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE; + unsigned int : 1; + unsigned int prefetch_match_disable : CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE; + unsigned int dynamic_clk_disable : CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE; + unsigned int prefetch_pass_nops : CP_DEBUG_PREFETCH_PASS_NOPS_SIZE; + unsigned int miu_128bit_write_enable : CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE; + unsigned int prog_end_ptr_enable : CP_DEBUG_PROG_END_PTR_ENABLE_SIZE; + unsigned int predicate_disable : CP_DEBUG_PREDICATE_DISABLE_SIZE; + unsigned int cp_debug_unused_22_to_0 : CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE; + } cp_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_debug_t f; +} cp_debug_u; + + +/* + * SCRATCH_REG0 struct + */ + +#define SCRATCH_REG0_SCRATCH_REG0_SIZE 32 + +#define SCRATCH_REG0_SCRATCH_REG0_SHIFT 0 + +#define SCRATCH_REG0_SCRATCH_REG0_MASK 0xffffffff + +#define SCRATCH_REG0_MASK \ + (SCRATCH_REG0_SCRATCH_REG0_MASK) + +#define SCRATCH_REG0(scratch_reg0) \ + ((scratch_reg0 << SCRATCH_REG0_SCRATCH_REG0_SHIFT)) + +#define SCRATCH_REG0_GET_SCRATCH_REG0(scratch_reg0) \ + ((scratch_reg0 & SCRATCH_REG0_SCRATCH_REG0_MASK) >> SCRATCH_REG0_SCRATCH_REG0_SHIFT) + +#define SCRATCH_REG0_SET_SCRATCH_REG0(scratch_reg0_reg, scratch_reg0) \ + scratch_reg0_reg = (scratch_reg0_reg & ~SCRATCH_REG0_SCRATCH_REG0_MASK) | (scratch_reg0 << SCRATCH_REG0_SCRATCH_REG0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg0_t { + unsigned int scratch_reg0 : SCRATCH_REG0_SCRATCH_REG0_SIZE; + } scratch_reg0_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg0_t { + unsigned int scratch_reg0 : SCRATCH_REG0_SCRATCH_REG0_SIZE; + } scratch_reg0_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg0_t f; +} scratch_reg0_u; + + +/* + * SCRATCH_REG1 struct + */ + +#define SCRATCH_REG1_SCRATCH_REG1_SIZE 32 + +#define SCRATCH_REG1_SCRATCH_REG1_SHIFT 0 + +#define SCRATCH_REG1_SCRATCH_REG1_MASK 0xffffffff + +#define SCRATCH_REG1_MASK \ + (SCRATCH_REG1_SCRATCH_REG1_MASK) + +#define SCRATCH_REG1(scratch_reg1) \ + ((scratch_reg1 << SCRATCH_REG1_SCRATCH_REG1_SHIFT)) + +#define SCRATCH_REG1_GET_SCRATCH_REG1(scratch_reg1) \ + ((scratch_reg1 & SCRATCH_REG1_SCRATCH_REG1_MASK) >> SCRATCH_REG1_SCRATCH_REG1_SHIFT) + +#define SCRATCH_REG1_SET_SCRATCH_REG1(scratch_reg1_reg, scratch_reg1) \ + scratch_reg1_reg = (scratch_reg1_reg & ~SCRATCH_REG1_SCRATCH_REG1_MASK) | (scratch_reg1 << SCRATCH_REG1_SCRATCH_REG1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg1_t { + unsigned int scratch_reg1 : SCRATCH_REG1_SCRATCH_REG1_SIZE; + } scratch_reg1_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg1_t { + unsigned int scratch_reg1 : SCRATCH_REG1_SCRATCH_REG1_SIZE; + } scratch_reg1_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg1_t f; +} scratch_reg1_u; + + +/* + * SCRATCH_REG2 struct + */ + +#define SCRATCH_REG2_SCRATCH_REG2_SIZE 32 + +#define SCRATCH_REG2_SCRATCH_REG2_SHIFT 0 + +#define SCRATCH_REG2_SCRATCH_REG2_MASK 0xffffffff + +#define SCRATCH_REG2_MASK \ + (SCRATCH_REG2_SCRATCH_REG2_MASK) + +#define SCRATCH_REG2(scratch_reg2) \ + ((scratch_reg2 << SCRATCH_REG2_SCRATCH_REG2_SHIFT)) + +#define SCRATCH_REG2_GET_SCRATCH_REG2(scratch_reg2) \ + ((scratch_reg2 & SCRATCH_REG2_SCRATCH_REG2_MASK) >> SCRATCH_REG2_SCRATCH_REG2_SHIFT) + +#define SCRATCH_REG2_SET_SCRATCH_REG2(scratch_reg2_reg, scratch_reg2) \ + scratch_reg2_reg = (scratch_reg2_reg & ~SCRATCH_REG2_SCRATCH_REG2_MASK) | (scratch_reg2 << SCRATCH_REG2_SCRATCH_REG2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg2_t { + unsigned int scratch_reg2 : SCRATCH_REG2_SCRATCH_REG2_SIZE; + } scratch_reg2_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg2_t { + unsigned int scratch_reg2 : SCRATCH_REG2_SCRATCH_REG2_SIZE; + } scratch_reg2_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg2_t f; +} scratch_reg2_u; + + +/* + * SCRATCH_REG3 struct + */ + +#define SCRATCH_REG3_SCRATCH_REG3_SIZE 32 + +#define SCRATCH_REG3_SCRATCH_REG3_SHIFT 0 + +#define SCRATCH_REG3_SCRATCH_REG3_MASK 0xffffffff + +#define SCRATCH_REG3_MASK \ + (SCRATCH_REG3_SCRATCH_REG3_MASK) + +#define SCRATCH_REG3(scratch_reg3) \ + ((scratch_reg3 << SCRATCH_REG3_SCRATCH_REG3_SHIFT)) + +#define SCRATCH_REG3_GET_SCRATCH_REG3(scratch_reg3) \ + ((scratch_reg3 & SCRATCH_REG3_SCRATCH_REG3_MASK) >> SCRATCH_REG3_SCRATCH_REG3_SHIFT) + +#define SCRATCH_REG3_SET_SCRATCH_REG3(scratch_reg3_reg, scratch_reg3) \ + scratch_reg3_reg = (scratch_reg3_reg & ~SCRATCH_REG3_SCRATCH_REG3_MASK) | (scratch_reg3 << SCRATCH_REG3_SCRATCH_REG3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg3_t { + unsigned int scratch_reg3 : SCRATCH_REG3_SCRATCH_REG3_SIZE; + } scratch_reg3_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg3_t { + unsigned int scratch_reg3 : SCRATCH_REG3_SCRATCH_REG3_SIZE; + } scratch_reg3_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg3_t f; +} scratch_reg3_u; + + +/* + * SCRATCH_REG4 struct + */ + +#define SCRATCH_REG4_SCRATCH_REG4_SIZE 32 + +#define SCRATCH_REG4_SCRATCH_REG4_SHIFT 0 + +#define SCRATCH_REG4_SCRATCH_REG4_MASK 0xffffffff + +#define SCRATCH_REG4_MASK \ + (SCRATCH_REG4_SCRATCH_REG4_MASK) + +#define SCRATCH_REG4(scratch_reg4) \ + ((scratch_reg4 << SCRATCH_REG4_SCRATCH_REG4_SHIFT)) + +#define SCRATCH_REG4_GET_SCRATCH_REG4(scratch_reg4) \ + ((scratch_reg4 & SCRATCH_REG4_SCRATCH_REG4_MASK) >> SCRATCH_REG4_SCRATCH_REG4_SHIFT) + +#define SCRATCH_REG4_SET_SCRATCH_REG4(scratch_reg4_reg, scratch_reg4) \ + scratch_reg4_reg = (scratch_reg4_reg & ~SCRATCH_REG4_SCRATCH_REG4_MASK) | (scratch_reg4 << SCRATCH_REG4_SCRATCH_REG4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg4_t { + unsigned int scratch_reg4 : SCRATCH_REG4_SCRATCH_REG4_SIZE; + } scratch_reg4_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg4_t { + unsigned int scratch_reg4 : SCRATCH_REG4_SCRATCH_REG4_SIZE; + } scratch_reg4_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg4_t f; +} scratch_reg4_u; + + +/* + * SCRATCH_REG5 struct + */ + +#define SCRATCH_REG5_SCRATCH_REG5_SIZE 32 + +#define SCRATCH_REG5_SCRATCH_REG5_SHIFT 0 + +#define SCRATCH_REG5_SCRATCH_REG5_MASK 0xffffffff + +#define SCRATCH_REG5_MASK \ + (SCRATCH_REG5_SCRATCH_REG5_MASK) + +#define SCRATCH_REG5(scratch_reg5) \ + ((scratch_reg5 << SCRATCH_REG5_SCRATCH_REG5_SHIFT)) + +#define SCRATCH_REG5_GET_SCRATCH_REG5(scratch_reg5) \ + ((scratch_reg5 & SCRATCH_REG5_SCRATCH_REG5_MASK) >> SCRATCH_REG5_SCRATCH_REG5_SHIFT) + +#define SCRATCH_REG5_SET_SCRATCH_REG5(scratch_reg5_reg, scratch_reg5) \ + scratch_reg5_reg = (scratch_reg5_reg & ~SCRATCH_REG5_SCRATCH_REG5_MASK) | (scratch_reg5 << SCRATCH_REG5_SCRATCH_REG5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg5_t { + unsigned int scratch_reg5 : SCRATCH_REG5_SCRATCH_REG5_SIZE; + } scratch_reg5_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg5_t { + unsigned int scratch_reg5 : SCRATCH_REG5_SCRATCH_REG5_SIZE; + } scratch_reg5_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg5_t f; +} scratch_reg5_u; + + +/* + * SCRATCH_REG6 struct + */ + +#define SCRATCH_REG6_SCRATCH_REG6_SIZE 32 + +#define SCRATCH_REG6_SCRATCH_REG6_SHIFT 0 + +#define SCRATCH_REG6_SCRATCH_REG6_MASK 0xffffffff + +#define SCRATCH_REG6_MASK \ + (SCRATCH_REG6_SCRATCH_REG6_MASK) + +#define SCRATCH_REG6(scratch_reg6) \ + ((scratch_reg6 << SCRATCH_REG6_SCRATCH_REG6_SHIFT)) + +#define SCRATCH_REG6_GET_SCRATCH_REG6(scratch_reg6) \ + ((scratch_reg6 & SCRATCH_REG6_SCRATCH_REG6_MASK) >> SCRATCH_REG6_SCRATCH_REG6_SHIFT) + +#define SCRATCH_REG6_SET_SCRATCH_REG6(scratch_reg6_reg, scratch_reg6) \ + scratch_reg6_reg = (scratch_reg6_reg & ~SCRATCH_REG6_SCRATCH_REG6_MASK) | (scratch_reg6 << SCRATCH_REG6_SCRATCH_REG6_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg6_t { + unsigned int scratch_reg6 : SCRATCH_REG6_SCRATCH_REG6_SIZE; + } scratch_reg6_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg6_t { + unsigned int scratch_reg6 : SCRATCH_REG6_SCRATCH_REG6_SIZE; + } scratch_reg6_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg6_t f; +} scratch_reg6_u; + + +/* + * SCRATCH_REG7 struct + */ + +#define SCRATCH_REG7_SCRATCH_REG7_SIZE 32 + +#define SCRATCH_REG7_SCRATCH_REG7_SHIFT 0 + +#define SCRATCH_REG7_SCRATCH_REG7_MASK 0xffffffff + +#define SCRATCH_REG7_MASK \ + (SCRATCH_REG7_SCRATCH_REG7_MASK) + +#define SCRATCH_REG7(scratch_reg7) \ + ((scratch_reg7 << SCRATCH_REG7_SCRATCH_REG7_SHIFT)) + +#define SCRATCH_REG7_GET_SCRATCH_REG7(scratch_reg7) \ + ((scratch_reg7 & SCRATCH_REG7_SCRATCH_REG7_MASK) >> SCRATCH_REG7_SCRATCH_REG7_SHIFT) + +#define SCRATCH_REG7_SET_SCRATCH_REG7(scratch_reg7_reg, scratch_reg7) \ + scratch_reg7_reg = (scratch_reg7_reg & ~SCRATCH_REG7_SCRATCH_REG7_MASK) | (scratch_reg7 << SCRATCH_REG7_SCRATCH_REG7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg7_t { + unsigned int scratch_reg7 : SCRATCH_REG7_SCRATCH_REG7_SIZE; + } scratch_reg7_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg7_t { + unsigned int scratch_reg7 : SCRATCH_REG7_SCRATCH_REG7_SIZE; + } scratch_reg7_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg7_t f; +} scratch_reg7_u; + + +/* + * SCRATCH_UMSK struct + */ + +#define SCRATCH_UMSK_SCRATCH_UMSK_SIZE 8 +#define SCRATCH_UMSK_SCRATCH_SWAP_SIZE 2 + +#define SCRATCH_UMSK_SCRATCH_UMSK_SHIFT 0 +#define SCRATCH_UMSK_SCRATCH_SWAP_SHIFT 16 + +#define SCRATCH_UMSK_SCRATCH_UMSK_MASK 0x000000ff +#define SCRATCH_UMSK_SCRATCH_SWAP_MASK 0x00030000 + +#define SCRATCH_UMSK_MASK \ + (SCRATCH_UMSK_SCRATCH_UMSK_MASK | \ + SCRATCH_UMSK_SCRATCH_SWAP_MASK) + +#define SCRATCH_UMSK(scratch_umsk, scratch_swap) \ + ((scratch_umsk << SCRATCH_UMSK_SCRATCH_UMSK_SHIFT) | \ + (scratch_swap << SCRATCH_UMSK_SCRATCH_SWAP_SHIFT)) + +#define SCRATCH_UMSK_GET_SCRATCH_UMSK(scratch_umsk) \ + ((scratch_umsk & SCRATCH_UMSK_SCRATCH_UMSK_MASK) >> SCRATCH_UMSK_SCRATCH_UMSK_SHIFT) +#define SCRATCH_UMSK_GET_SCRATCH_SWAP(scratch_umsk) \ + ((scratch_umsk & SCRATCH_UMSK_SCRATCH_SWAP_MASK) >> SCRATCH_UMSK_SCRATCH_SWAP_SHIFT) + +#define SCRATCH_UMSK_SET_SCRATCH_UMSK(scratch_umsk_reg, scratch_umsk) \ + scratch_umsk_reg = (scratch_umsk_reg & ~SCRATCH_UMSK_SCRATCH_UMSK_MASK) | (scratch_umsk << SCRATCH_UMSK_SCRATCH_UMSK_SHIFT) +#define SCRATCH_UMSK_SET_SCRATCH_SWAP(scratch_umsk_reg, scratch_swap) \ + scratch_umsk_reg = (scratch_umsk_reg & ~SCRATCH_UMSK_SCRATCH_SWAP_MASK) | (scratch_swap << SCRATCH_UMSK_SCRATCH_SWAP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_umsk_t { + unsigned int scratch_umsk : SCRATCH_UMSK_SCRATCH_UMSK_SIZE; + unsigned int : 8; + unsigned int scratch_swap : SCRATCH_UMSK_SCRATCH_SWAP_SIZE; + unsigned int : 14; + } scratch_umsk_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_umsk_t { + unsigned int : 14; + unsigned int scratch_swap : SCRATCH_UMSK_SCRATCH_SWAP_SIZE; + unsigned int : 8; + unsigned int scratch_umsk : SCRATCH_UMSK_SCRATCH_UMSK_SIZE; + } scratch_umsk_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_umsk_t f; +} scratch_umsk_u; + + +/* + * SCRATCH_ADDR struct + */ + +#define SCRATCH_ADDR_SCRATCH_ADDR_SIZE 27 + +#define SCRATCH_ADDR_SCRATCH_ADDR_SHIFT 5 + +#define SCRATCH_ADDR_SCRATCH_ADDR_MASK 0xffffffe0 + +#define SCRATCH_ADDR_MASK \ + (SCRATCH_ADDR_SCRATCH_ADDR_MASK) + +#define SCRATCH_ADDR(scratch_addr) \ + ((scratch_addr << SCRATCH_ADDR_SCRATCH_ADDR_SHIFT)) + +#define SCRATCH_ADDR_GET_SCRATCH_ADDR(scratch_addr) \ + ((scratch_addr & SCRATCH_ADDR_SCRATCH_ADDR_MASK) >> SCRATCH_ADDR_SCRATCH_ADDR_SHIFT) + +#define SCRATCH_ADDR_SET_SCRATCH_ADDR(scratch_addr_reg, scratch_addr) \ + scratch_addr_reg = (scratch_addr_reg & ~SCRATCH_ADDR_SCRATCH_ADDR_MASK) | (scratch_addr << SCRATCH_ADDR_SCRATCH_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_addr_t { + unsigned int : 5; + unsigned int scratch_addr : SCRATCH_ADDR_SCRATCH_ADDR_SIZE; + } scratch_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_addr_t { + unsigned int scratch_addr : SCRATCH_ADDR_SCRATCH_ADDR_SIZE; + unsigned int : 5; + } scratch_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_addr_t f; +} scratch_addr_u; + + +/* + * CP_ME_VS_EVENT_SRC struct + */ + +#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE 1 +#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE 1 + +#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT 0 +#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT 1 + +#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK 0x00000001 +#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK 0x00000002 + +#define CP_ME_VS_EVENT_SRC_MASK \ + (CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK | \ + CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) + +#define CP_ME_VS_EVENT_SRC(vs_done_swm, vs_done_cntr) \ + ((vs_done_swm << CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT) | \ + (vs_done_cntr << CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT)) + +#define CP_ME_VS_EVENT_SRC_GET_VS_DONE_SWM(cp_me_vs_event_src) \ + ((cp_me_vs_event_src & CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK) >> CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT) +#define CP_ME_VS_EVENT_SRC_GET_VS_DONE_CNTR(cp_me_vs_event_src) \ + ((cp_me_vs_event_src & CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) >> CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT) + +#define CP_ME_VS_EVENT_SRC_SET_VS_DONE_SWM(cp_me_vs_event_src_reg, vs_done_swm) \ + cp_me_vs_event_src_reg = (cp_me_vs_event_src_reg & ~CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK) | (vs_done_swm << CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT) +#define CP_ME_VS_EVENT_SRC_SET_VS_DONE_CNTR(cp_me_vs_event_src_reg, vs_done_cntr) \ + cp_me_vs_event_src_reg = (cp_me_vs_event_src_reg & ~CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) | (vs_done_cntr << CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_src_t { + unsigned int vs_done_swm : CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE; + unsigned int vs_done_cntr : CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE; + unsigned int : 30; + } cp_me_vs_event_src_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_src_t { + unsigned int : 30; + unsigned int vs_done_cntr : CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE; + unsigned int vs_done_swm : CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE; + } cp_me_vs_event_src_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_src_t f; +} cp_me_vs_event_src_u; + + +/* + * CP_ME_VS_EVENT_ADDR struct + */ + +#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE 2 +#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE 30 + +#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT 0 +#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT 2 + +#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK 0x00000003 +#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK 0xfffffffc + +#define CP_ME_VS_EVENT_ADDR_MASK \ + (CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK | \ + CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) + +#define CP_ME_VS_EVENT_ADDR(vs_done_swap, vs_done_addr) \ + ((vs_done_swap << CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT) | \ + (vs_done_addr << CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT)) + +#define CP_ME_VS_EVENT_ADDR_GET_VS_DONE_SWAP(cp_me_vs_event_addr) \ + ((cp_me_vs_event_addr & CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK) >> CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT) +#define CP_ME_VS_EVENT_ADDR_GET_VS_DONE_ADDR(cp_me_vs_event_addr) \ + ((cp_me_vs_event_addr & CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) >> CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT) + +#define CP_ME_VS_EVENT_ADDR_SET_VS_DONE_SWAP(cp_me_vs_event_addr_reg, vs_done_swap) \ + cp_me_vs_event_addr_reg = (cp_me_vs_event_addr_reg & ~CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK) | (vs_done_swap << CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT) +#define CP_ME_VS_EVENT_ADDR_SET_VS_DONE_ADDR(cp_me_vs_event_addr_reg, vs_done_addr) \ + cp_me_vs_event_addr_reg = (cp_me_vs_event_addr_reg & ~CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) | (vs_done_addr << CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_addr_t { + unsigned int vs_done_swap : CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE; + unsigned int vs_done_addr : CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE; + } cp_me_vs_event_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_addr_t { + unsigned int vs_done_addr : CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE; + unsigned int vs_done_swap : CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE; + } cp_me_vs_event_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_addr_t f; +} cp_me_vs_event_addr_u; + + +/* + * CP_ME_VS_EVENT_DATA struct + */ + +#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE 32 + +#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT 0 + +#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK 0xffffffff + +#define CP_ME_VS_EVENT_DATA_MASK \ + (CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) + +#define CP_ME_VS_EVENT_DATA(vs_done_data) \ + ((vs_done_data << CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT)) + +#define CP_ME_VS_EVENT_DATA_GET_VS_DONE_DATA(cp_me_vs_event_data) \ + ((cp_me_vs_event_data & CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) >> CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT) + +#define CP_ME_VS_EVENT_DATA_SET_VS_DONE_DATA(cp_me_vs_event_data_reg, vs_done_data) \ + cp_me_vs_event_data_reg = (cp_me_vs_event_data_reg & ~CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) | (vs_done_data << CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_data_t { + unsigned int vs_done_data : CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE; + } cp_me_vs_event_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_data_t { + unsigned int vs_done_data : CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE; + } cp_me_vs_event_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_data_t f; +} cp_me_vs_event_data_u; + + +/* + * CP_ME_VS_EVENT_ADDR_SWM struct + */ + +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE 2 +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE 30 + +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT 0 +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT 2 + +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK 0x00000003 +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK 0xfffffffc + +#define CP_ME_VS_EVENT_ADDR_SWM_MASK \ + (CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK | \ + CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) + +#define CP_ME_VS_EVENT_ADDR_SWM(vs_done_swap_swm, vs_done_addr_swm) \ + ((vs_done_swap_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT) | \ + (vs_done_addr_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT)) + +#define CP_ME_VS_EVENT_ADDR_SWM_GET_VS_DONE_SWAP_SWM(cp_me_vs_event_addr_swm) \ + ((cp_me_vs_event_addr_swm & CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK) >> CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT) +#define CP_ME_VS_EVENT_ADDR_SWM_GET_VS_DONE_ADDR_SWM(cp_me_vs_event_addr_swm) \ + ((cp_me_vs_event_addr_swm & CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) >> CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT) + +#define CP_ME_VS_EVENT_ADDR_SWM_SET_VS_DONE_SWAP_SWM(cp_me_vs_event_addr_swm_reg, vs_done_swap_swm) \ + cp_me_vs_event_addr_swm_reg = (cp_me_vs_event_addr_swm_reg & ~CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK) | (vs_done_swap_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT) +#define CP_ME_VS_EVENT_ADDR_SWM_SET_VS_DONE_ADDR_SWM(cp_me_vs_event_addr_swm_reg, vs_done_addr_swm) \ + cp_me_vs_event_addr_swm_reg = (cp_me_vs_event_addr_swm_reg & ~CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) | (vs_done_addr_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_addr_swm_t { + unsigned int vs_done_swap_swm : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE; + unsigned int vs_done_addr_swm : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE; + } cp_me_vs_event_addr_swm_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_addr_swm_t { + unsigned int vs_done_addr_swm : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE; + unsigned int vs_done_swap_swm : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE; + } cp_me_vs_event_addr_swm_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_addr_swm_t f; +} cp_me_vs_event_addr_swm_u; + + +/* + * CP_ME_VS_EVENT_DATA_SWM struct + */ + +#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE 32 + +#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT 0 + +#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK 0xffffffff + +#define CP_ME_VS_EVENT_DATA_SWM_MASK \ + (CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) + +#define CP_ME_VS_EVENT_DATA_SWM(vs_done_data_swm) \ + ((vs_done_data_swm << CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT)) + +#define CP_ME_VS_EVENT_DATA_SWM_GET_VS_DONE_DATA_SWM(cp_me_vs_event_data_swm) \ + ((cp_me_vs_event_data_swm & CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) >> CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT) + +#define CP_ME_VS_EVENT_DATA_SWM_SET_VS_DONE_DATA_SWM(cp_me_vs_event_data_swm_reg, vs_done_data_swm) \ + cp_me_vs_event_data_swm_reg = (cp_me_vs_event_data_swm_reg & ~CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) | (vs_done_data_swm << CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_data_swm_t { + unsigned int vs_done_data_swm : CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE; + } cp_me_vs_event_data_swm_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_data_swm_t { + unsigned int vs_done_data_swm : CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE; + } cp_me_vs_event_data_swm_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_data_swm_t f; +} cp_me_vs_event_data_swm_u; + + +/* + * CP_ME_PS_EVENT_SRC struct + */ + +#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE 1 +#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE 1 + +#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT 0 +#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT 1 + +#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK 0x00000001 +#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK 0x00000002 + +#define CP_ME_PS_EVENT_SRC_MASK \ + (CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK | \ + CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) + +#define CP_ME_PS_EVENT_SRC(ps_done_swm, ps_done_cntr) \ + ((ps_done_swm << CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT) | \ + (ps_done_cntr << CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT)) + +#define CP_ME_PS_EVENT_SRC_GET_PS_DONE_SWM(cp_me_ps_event_src) \ + ((cp_me_ps_event_src & CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK) >> CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT) +#define CP_ME_PS_EVENT_SRC_GET_PS_DONE_CNTR(cp_me_ps_event_src) \ + ((cp_me_ps_event_src & CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) >> CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT) + +#define CP_ME_PS_EVENT_SRC_SET_PS_DONE_SWM(cp_me_ps_event_src_reg, ps_done_swm) \ + cp_me_ps_event_src_reg = (cp_me_ps_event_src_reg & ~CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK) | (ps_done_swm << CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT) +#define CP_ME_PS_EVENT_SRC_SET_PS_DONE_CNTR(cp_me_ps_event_src_reg, ps_done_cntr) \ + cp_me_ps_event_src_reg = (cp_me_ps_event_src_reg & ~CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) | (ps_done_cntr << CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_src_t { + unsigned int ps_done_swm : CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE; + unsigned int ps_done_cntr : CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE; + unsigned int : 30; + } cp_me_ps_event_src_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_src_t { + unsigned int : 30; + unsigned int ps_done_cntr : CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE; + unsigned int ps_done_swm : CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE; + } cp_me_ps_event_src_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_src_t f; +} cp_me_ps_event_src_u; + + +/* + * CP_ME_PS_EVENT_ADDR struct + */ + +#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE 2 +#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE 30 + +#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT 0 +#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT 2 + +#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK 0x00000003 +#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK 0xfffffffc + +#define CP_ME_PS_EVENT_ADDR_MASK \ + (CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK | \ + CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) + +#define CP_ME_PS_EVENT_ADDR(ps_done_swap, ps_done_addr) \ + ((ps_done_swap << CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT) | \ + (ps_done_addr << CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT)) + +#define CP_ME_PS_EVENT_ADDR_GET_PS_DONE_SWAP(cp_me_ps_event_addr) \ + ((cp_me_ps_event_addr & CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK) >> CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT) +#define CP_ME_PS_EVENT_ADDR_GET_PS_DONE_ADDR(cp_me_ps_event_addr) \ + ((cp_me_ps_event_addr & CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) >> CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT) + +#define CP_ME_PS_EVENT_ADDR_SET_PS_DONE_SWAP(cp_me_ps_event_addr_reg, ps_done_swap) \ + cp_me_ps_event_addr_reg = (cp_me_ps_event_addr_reg & ~CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK) | (ps_done_swap << CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT) +#define CP_ME_PS_EVENT_ADDR_SET_PS_DONE_ADDR(cp_me_ps_event_addr_reg, ps_done_addr) \ + cp_me_ps_event_addr_reg = (cp_me_ps_event_addr_reg & ~CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) | (ps_done_addr << CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_addr_t { + unsigned int ps_done_swap : CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE; + unsigned int ps_done_addr : CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE; + } cp_me_ps_event_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_addr_t { + unsigned int ps_done_addr : CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE; + unsigned int ps_done_swap : CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE; + } cp_me_ps_event_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_addr_t f; +} cp_me_ps_event_addr_u; + + +/* + * CP_ME_PS_EVENT_DATA struct + */ + +#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE 32 + +#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT 0 + +#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK 0xffffffff + +#define CP_ME_PS_EVENT_DATA_MASK \ + (CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) + +#define CP_ME_PS_EVENT_DATA(ps_done_data) \ + ((ps_done_data << CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT)) + +#define CP_ME_PS_EVENT_DATA_GET_PS_DONE_DATA(cp_me_ps_event_data) \ + ((cp_me_ps_event_data & CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) >> CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT) + +#define CP_ME_PS_EVENT_DATA_SET_PS_DONE_DATA(cp_me_ps_event_data_reg, ps_done_data) \ + cp_me_ps_event_data_reg = (cp_me_ps_event_data_reg & ~CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) | (ps_done_data << CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_data_t { + unsigned int ps_done_data : CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE; + } cp_me_ps_event_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_data_t { + unsigned int ps_done_data : CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE; + } cp_me_ps_event_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_data_t f; +} cp_me_ps_event_data_u; + + +/* + * CP_ME_PS_EVENT_ADDR_SWM struct + */ + +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE 2 +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE 30 + +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT 0 +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT 2 + +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK 0x00000003 +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK 0xfffffffc + +#define CP_ME_PS_EVENT_ADDR_SWM_MASK \ + (CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK | \ + CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) + +#define CP_ME_PS_EVENT_ADDR_SWM(ps_done_swap_swm, ps_done_addr_swm) \ + ((ps_done_swap_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT) | \ + (ps_done_addr_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT)) + +#define CP_ME_PS_EVENT_ADDR_SWM_GET_PS_DONE_SWAP_SWM(cp_me_ps_event_addr_swm) \ + ((cp_me_ps_event_addr_swm & CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK) >> CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT) +#define CP_ME_PS_EVENT_ADDR_SWM_GET_PS_DONE_ADDR_SWM(cp_me_ps_event_addr_swm) \ + ((cp_me_ps_event_addr_swm & CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) >> CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT) + +#define CP_ME_PS_EVENT_ADDR_SWM_SET_PS_DONE_SWAP_SWM(cp_me_ps_event_addr_swm_reg, ps_done_swap_swm) \ + cp_me_ps_event_addr_swm_reg = (cp_me_ps_event_addr_swm_reg & ~CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK) | (ps_done_swap_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT) +#define CP_ME_PS_EVENT_ADDR_SWM_SET_PS_DONE_ADDR_SWM(cp_me_ps_event_addr_swm_reg, ps_done_addr_swm) \ + cp_me_ps_event_addr_swm_reg = (cp_me_ps_event_addr_swm_reg & ~CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) | (ps_done_addr_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_addr_swm_t { + unsigned int ps_done_swap_swm : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE; + unsigned int ps_done_addr_swm : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE; + } cp_me_ps_event_addr_swm_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_addr_swm_t { + unsigned int ps_done_addr_swm : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE; + unsigned int ps_done_swap_swm : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE; + } cp_me_ps_event_addr_swm_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_addr_swm_t f; +} cp_me_ps_event_addr_swm_u; + + +/* + * CP_ME_PS_EVENT_DATA_SWM struct + */ + +#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE 32 + +#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT 0 + +#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK 0xffffffff + +#define CP_ME_PS_EVENT_DATA_SWM_MASK \ + (CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) + +#define CP_ME_PS_EVENT_DATA_SWM(ps_done_data_swm) \ + ((ps_done_data_swm << CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT)) + +#define CP_ME_PS_EVENT_DATA_SWM_GET_PS_DONE_DATA_SWM(cp_me_ps_event_data_swm) \ + ((cp_me_ps_event_data_swm & CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) >> CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT) + +#define CP_ME_PS_EVENT_DATA_SWM_SET_PS_DONE_DATA_SWM(cp_me_ps_event_data_swm_reg, ps_done_data_swm) \ + cp_me_ps_event_data_swm_reg = (cp_me_ps_event_data_swm_reg & ~CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) | (ps_done_data_swm << CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_data_swm_t { + unsigned int ps_done_data_swm : CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE; + } cp_me_ps_event_data_swm_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_data_swm_t { + unsigned int ps_done_data_swm : CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE; + } cp_me_ps_event_data_swm_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_data_swm_t f; +} cp_me_ps_event_data_swm_u; + + +/* + * CP_ME_CF_EVENT_SRC struct + */ + +#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE 1 + +#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT 0 + +#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK 0x00000001 + +#define CP_ME_CF_EVENT_SRC_MASK \ + (CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) + +#define CP_ME_CF_EVENT_SRC(cf_done_src) \ + ((cf_done_src << CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT)) + +#define CP_ME_CF_EVENT_SRC_GET_CF_DONE_SRC(cp_me_cf_event_src) \ + ((cp_me_cf_event_src & CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) >> CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT) + +#define CP_ME_CF_EVENT_SRC_SET_CF_DONE_SRC(cp_me_cf_event_src_reg, cf_done_src) \ + cp_me_cf_event_src_reg = (cp_me_cf_event_src_reg & ~CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) | (cf_done_src << CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_cf_event_src_t { + unsigned int cf_done_src : CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE; + unsigned int : 31; + } cp_me_cf_event_src_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_cf_event_src_t { + unsigned int : 31; + unsigned int cf_done_src : CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE; + } cp_me_cf_event_src_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_cf_event_src_t f; +} cp_me_cf_event_src_u; + + +/* + * CP_ME_CF_EVENT_ADDR struct + */ + +#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE 2 +#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE 30 + +#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT 0 +#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT 2 + +#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK 0x00000003 +#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK 0xfffffffc + +#define CP_ME_CF_EVENT_ADDR_MASK \ + (CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK | \ + CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) + +#define CP_ME_CF_EVENT_ADDR(cf_done_swap, cf_done_addr) \ + ((cf_done_swap << CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT) | \ + (cf_done_addr << CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT)) + +#define CP_ME_CF_EVENT_ADDR_GET_CF_DONE_SWAP(cp_me_cf_event_addr) \ + ((cp_me_cf_event_addr & CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK) >> CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT) +#define CP_ME_CF_EVENT_ADDR_GET_CF_DONE_ADDR(cp_me_cf_event_addr) \ + ((cp_me_cf_event_addr & CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) >> CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT) + +#define CP_ME_CF_EVENT_ADDR_SET_CF_DONE_SWAP(cp_me_cf_event_addr_reg, cf_done_swap) \ + cp_me_cf_event_addr_reg = (cp_me_cf_event_addr_reg & ~CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK) | (cf_done_swap << CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT) +#define CP_ME_CF_EVENT_ADDR_SET_CF_DONE_ADDR(cp_me_cf_event_addr_reg, cf_done_addr) \ + cp_me_cf_event_addr_reg = (cp_me_cf_event_addr_reg & ~CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) | (cf_done_addr << CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_cf_event_addr_t { + unsigned int cf_done_swap : CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE; + unsigned int cf_done_addr : CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE; + } cp_me_cf_event_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_cf_event_addr_t { + unsigned int cf_done_addr : CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE; + unsigned int cf_done_swap : CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE; + } cp_me_cf_event_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_cf_event_addr_t f; +} cp_me_cf_event_addr_u; + + +/* + * CP_ME_CF_EVENT_DATA struct + */ + +#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE 32 + +#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT 0 + +#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK 0xffffffff + +#define CP_ME_CF_EVENT_DATA_MASK \ + (CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) + +#define CP_ME_CF_EVENT_DATA(cf_done_data) \ + ((cf_done_data << CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT)) + +#define CP_ME_CF_EVENT_DATA_GET_CF_DONE_DATA(cp_me_cf_event_data) \ + ((cp_me_cf_event_data & CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) >> CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT) + +#define CP_ME_CF_EVENT_DATA_SET_CF_DONE_DATA(cp_me_cf_event_data_reg, cf_done_data) \ + cp_me_cf_event_data_reg = (cp_me_cf_event_data_reg & ~CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) | (cf_done_data << CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_cf_event_data_t { + unsigned int cf_done_data : CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE; + } cp_me_cf_event_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_cf_event_data_t { + unsigned int cf_done_data : CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE; + } cp_me_cf_event_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_cf_event_data_t f; +} cp_me_cf_event_data_u; + + +/* + * CP_ME_NRT_ADDR struct + */ + +#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE 2 +#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE 30 + +#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT 0 +#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT 2 + +#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK 0x00000003 +#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK 0xfffffffc + +#define CP_ME_NRT_ADDR_MASK \ + (CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK | \ + CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) + +#define CP_ME_NRT_ADDR(nrt_write_swap, nrt_write_addr) \ + ((nrt_write_swap << CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT) | \ + (nrt_write_addr << CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT)) + +#define CP_ME_NRT_ADDR_GET_NRT_WRITE_SWAP(cp_me_nrt_addr) \ + ((cp_me_nrt_addr & CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK) >> CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT) +#define CP_ME_NRT_ADDR_GET_NRT_WRITE_ADDR(cp_me_nrt_addr) \ + ((cp_me_nrt_addr & CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) >> CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT) + +#define CP_ME_NRT_ADDR_SET_NRT_WRITE_SWAP(cp_me_nrt_addr_reg, nrt_write_swap) \ + cp_me_nrt_addr_reg = (cp_me_nrt_addr_reg & ~CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK) | (nrt_write_swap << CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT) +#define CP_ME_NRT_ADDR_SET_NRT_WRITE_ADDR(cp_me_nrt_addr_reg, nrt_write_addr) \ + cp_me_nrt_addr_reg = (cp_me_nrt_addr_reg & ~CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) | (nrt_write_addr << CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_nrt_addr_t { + unsigned int nrt_write_swap : CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE; + unsigned int nrt_write_addr : CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE; + } cp_me_nrt_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_nrt_addr_t { + unsigned int nrt_write_addr : CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE; + unsigned int nrt_write_swap : CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE; + } cp_me_nrt_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_nrt_addr_t f; +} cp_me_nrt_addr_u; + + +/* + * CP_ME_NRT_DATA struct + */ + +#define CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE 32 + +#define CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT 0 + +#define CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK 0xffffffff + +#define CP_ME_NRT_DATA_MASK \ + (CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) + +#define CP_ME_NRT_DATA(nrt_write_data) \ + ((nrt_write_data << CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT)) + +#define CP_ME_NRT_DATA_GET_NRT_WRITE_DATA(cp_me_nrt_data) \ + ((cp_me_nrt_data & CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) >> CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT) + +#define CP_ME_NRT_DATA_SET_NRT_WRITE_DATA(cp_me_nrt_data_reg, nrt_write_data) \ + cp_me_nrt_data_reg = (cp_me_nrt_data_reg & ~CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) | (nrt_write_data << CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_nrt_data_t { + unsigned int nrt_write_data : CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE; + } cp_me_nrt_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_nrt_data_t { + unsigned int nrt_write_data : CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE; + } cp_me_nrt_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_nrt_data_t f; +} cp_me_nrt_data_u; + + +/* + * CP_ME_VS_FETCH_DONE_SRC struct + */ + +#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE 1 + +#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT 0 + +#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK 0x00000001 + +#define CP_ME_VS_FETCH_DONE_SRC_MASK \ + (CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) + +#define CP_ME_VS_FETCH_DONE_SRC(vs_fetch_done_cntr) \ + ((vs_fetch_done_cntr << CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT)) + +#define CP_ME_VS_FETCH_DONE_SRC_GET_VS_FETCH_DONE_CNTR(cp_me_vs_fetch_done_src) \ + ((cp_me_vs_fetch_done_src & CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) >> CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT) + +#define CP_ME_VS_FETCH_DONE_SRC_SET_VS_FETCH_DONE_CNTR(cp_me_vs_fetch_done_src_reg, vs_fetch_done_cntr) \ + cp_me_vs_fetch_done_src_reg = (cp_me_vs_fetch_done_src_reg & ~CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) | (vs_fetch_done_cntr << CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_src_t { + unsigned int vs_fetch_done_cntr : CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE; + unsigned int : 31; + } cp_me_vs_fetch_done_src_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_src_t { + unsigned int : 31; + unsigned int vs_fetch_done_cntr : CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE; + } cp_me_vs_fetch_done_src_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_fetch_done_src_t f; +} cp_me_vs_fetch_done_src_u; + + +/* + * CP_ME_VS_FETCH_DONE_ADDR struct + */ + +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE 2 +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE 30 + +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT 0 +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT 2 + +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK 0x00000003 +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK 0xfffffffc + +#define CP_ME_VS_FETCH_DONE_ADDR_MASK \ + (CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK | \ + CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) + +#define CP_ME_VS_FETCH_DONE_ADDR(vs_fetch_done_swap, vs_fetch_done_addr) \ + ((vs_fetch_done_swap << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT) | \ + (vs_fetch_done_addr << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT)) + +#define CP_ME_VS_FETCH_DONE_ADDR_GET_VS_FETCH_DONE_SWAP(cp_me_vs_fetch_done_addr) \ + ((cp_me_vs_fetch_done_addr & CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK) >> CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT) +#define CP_ME_VS_FETCH_DONE_ADDR_GET_VS_FETCH_DONE_ADDR(cp_me_vs_fetch_done_addr) \ + ((cp_me_vs_fetch_done_addr & CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) >> CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT) + +#define CP_ME_VS_FETCH_DONE_ADDR_SET_VS_FETCH_DONE_SWAP(cp_me_vs_fetch_done_addr_reg, vs_fetch_done_swap) \ + cp_me_vs_fetch_done_addr_reg = (cp_me_vs_fetch_done_addr_reg & ~CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK) | (vs_fetch_done_swap << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT) +#define CP_ME_VS_FETCH_DONE_ADDR_SET_VS_FETCH_DONE_ADDR(cp_me_vs_fetch_done_addr_reg, vs_fetch_done_addr) \ + cp_me_vs_fetch_done_addr_reg = (cp_me_vs_fetch_done_addr_reg & ~CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) | (vs_fetch_done_addr << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_addr_t { + unsigned int vs_fetch_done_swap : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE; + unsigned int vs_fetch_done_addr : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE; + } cp_me_vs_fetch_done_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_addr_t { + unsigned int vs_fetch_done_addr : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE; + unsigned int vs_fetch_done_swap : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE; + } cp_me_vs_fetch_done_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_fetch_done_addr_t f; +} cp_me_vs_fetch_done_addr_u; + + +/* + * CP_ME_VS_FETCH_DONE_DATA struct + */ + +#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE 32 + +#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT 0 + +#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK 0xffffffff + +#define CP_ME_VS_FETCH_DONE_DATA_MASK \ + (CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) + +#define CP_ME_VS_FETCH_DONE_DATA(vs_fetch_done_data) \ + ((vs_fetch_done_data << CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT)) + +#define CP_ME_VS_FETCH_DONE_DATA_GET_VS_FETCH_DONE_DATA(cp_me_vs_fetch_done_data) \ + ((cp_me_vs_fetch_done_data & CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) >> CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT) + +#define CP_ME_VS_FETCH_DONE_DATA_SET_VS_FETCH_DONE_DATA(cp_me_vs_fetch_done_data_reg, vs_fetch_done_data) \ + cp_me_vs_fetch_done_data_reg = (cp_me_vs_fetch_done_data_reg & ~CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) | (vs_fetch_done_data << CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_data_t { + unsigned int vs_fetch_done_data : CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE; + } cp_me_vs_fetch_done_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_data_t { + unsigned int vs_fetch_done_data : CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE; + } cp_me_vs_fetch_done_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_fetch_done_data_t f; +} cp_me_vs_fetch_done_data_u; + + +/* + * CP_INT_CNTL struct + */ + +#define CP_INT_CNTL_SW_INT_MASK_SIZE 1 +#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE 1 +#define CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE 1 +#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE 1 +#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE 1 +#define CP_INT_CNTL_IB_ERROR_MASK_SIZE 1 +#define CP_INT_CNTL_IB2_INT_MASK_SIZE 1 +#define CP_INT_CNTL_IB1_INT_MASK_SIZE 1 +#define CP_INT_CNTL_RB_INT_MASK_SIZE 1 + +#define CP_INT_CNTL_SW_INT_MASK_SHIFT 19 +#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT 23 +#define CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT 24 +#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT 25 +#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT 26 +#define CP_INT_CNTL_IB_ERROR_MASK_SHIFT 27 +#define CP_INT_CNTL_IB2_INT_MASK_SHIFT 29 +#define CP_INT_CNTL_IB1_INT_MASK_SHIFT 30 +#define CP_INT_CNTL_RB_INT_MASK_SHIFT 31 + +#define CP_INT_CNTL_SW_INT_MASK_MASK 0x00080000 +#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK 0x00800000 +#define CP_INT_CNTL_OPCODE_ERROR_MASK_MASK 0x01000000 +#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK 0x02000000 +#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK 0x04000000 +#define CP_INT_CNTL_IB_ERROR_MASK_MASK 0x08000000 +#define CP_INT_CNTL_IB2_INT_MASK_MASK 0x20000000 +#define CP_INT_CNTL_IB1_INT_MASK_MASK 0x40000000 +#define CP_INT_CNTL_RB_INT_MASK_MASK 0x80000000 + +#define CP_INT_CNTL_MASK \ + (CP_INT_CNTL_SW_INT_MASK_MASK | \ + CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK | \ + CP_INT_CNTL_OPCODE_ERROR_MASK_MASK | \ + CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK | \ + CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK | \ + CP_INT_CNTL_IB_ERROR_MASK_MASK | \ + CP_INT_CNTL_IB2_INT_MASK_MASK | \ + CP_INT_CNTL_IB1_INT_MASK_MASK | \ + CP_INT_CNTL_RB_INT_MASK_MASK) + +#define CP_INT_CNTL(sw_int_mask, t0_packet_in_ib_mask, opcode_error_mask, protected_mode_error_mask, reserved_bit_error_mask, ib_error_mask, ib2_int_mask, ib1_int_mask, rb_int_mask) \ + ((sw_int_mask << CP_INT_CNTL_SW_INT_MASK_SHIFT) | \ + (t0_packet_in_ib_mask << CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT) | \ + (opcode_error_mask << CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT) | \ + (protected_mode_error_mask << CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT) | \ + (reserved_bit_error_mask << CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT) | \ + (ib_error_mask << CP_INT_CNTL_IB_ERROR_MASK_SHIFT) | \ + (ib2_int_mask << CP_INT_CNTL_IB2_INT_MASK_SHIFT) | \ + (ib1_int_mask << CP_INT_CNTL_IB1_INT_MASK_SHIFT) | \ + (rb_int_mask << CP_INT_CNTL_RB_INT_MASK_SHIFT)) + +#define CP_INT_CNTL_GET_SW_INT_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_SW_INT_MASK_MASK) >> CP_INT_CNTL_SW_INT_MASK_SHIFT) +#define CP_INT_CNTL_GET_T0_PACKET_IN_IB_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK) >> CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT) +#define CP_INT_CNTL_GET_OPCODE_ERROR_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_OPCODE_ERROR_MASK_MASK) >> CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_GET_PROTECTED_MODE_ERROR_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK) >> CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_GET_RESERVED_BIT_ERROR_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK) >> CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_GET_IB_ERROR_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_IB_ERROR_MASK_MASK) >> CP_INT_CNTL_IB_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_GET_IB2_INT_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_IB2_INT_MASK_MASK) >> CP_INT_CNTL_IB2_INT_MASK_SHIFT) +#define CP_INT_CNTL_GET_IB1_INT_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_IB1_INT_MASK_MASK) >> CP_INT_CNTL_IB1_INT_MASK_SHIFT) +#define CP_INT_CNTL_GET_RB_INT_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_RB_INT_MASK_MASK) >> CP_INT_CNTL_RB_INT_MASK_SHIFT) + +#define CP_INT_CNTL_SET_SW_INT_MASK(cp_int_cntl_reg, sw_int_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_SW_INT_MASK_MASK) | (sw_int_mask << CP_INT_CNTL_SW_INT_MASK_SHIFT) +#define CP_INT_CNTL_SET_T0_PACKET_IN_IB_MASK(cp_int_cntl_reg, t0_packet_in_ib_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK) | (t0_packet_in_ib_mask << CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT) +#define CP_INT_CNTL_SET_OPCODE_ERROR_MASK(cp_int_cntl_reg, opcode_error_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_OPCODE_ERROR_MASK_MASK) | (opcode_error_mask << CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_SET_PROTECTED_MODE_ERROR_MASK(cp_int_cntl_reg, protected_mode_error_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK) | (protected_mode_error_mask << CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_SET_RESERVED_BIT_ERROR_MASK(cp_int_cntl_reg, reserved_bit_error_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK) | (reserved_bit_error_mask << CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_SET_IB_ERROR_MASK(cp_int_cntl_reg, ib_error_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB_ERROR_MASK_MASK) | (ib_error_mask << CP_INT_CNTL_IB_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_SET_IB2_INT_MASK(cp_int_cntl_reg, ib2_int_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB2_INT_MASK_MASK) | (ib2_int_mask << CP_INT_CNTL_IB2_INT_MASK_SHIFT) +#define CP_INT_CNTL_SET_IB1_INT_MASK(cp_int_cntl_reg, ib1_int_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB1_INT_MASK_MASK) | (ib1_int_mask << CP_INT_CNTL_IB1_INT_MASK_SHIFT) +#define CP_INT_CNTL_SET_RB_INT_MASK(cp_int_cntl_reg, rb_int_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_RB_INT_MASK_MASK) | (rb_int_mask << CP_INT_CNTL_RB_INT_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_int_cntl_t { + unsigned int : 19; + unsigned int sw_int_mask : CP_INT_CNTL_SW_INT_MASK_SIZE; + unsigned int : 3; + unsigned int t0_packet_in_ib_mask : CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE; + unsigned int opcode_error_mask : CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE; + unsigned int protected_mode_error_mask : CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE; + unsigned int reserved_bit_error_mask : CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE; + unsigned int ib_error_mask : CP_INT_CNTL_IB_ERROR_MASK_SIZE; + unsigned int : 1; + unsigned int ib2_int_mask : CP_INT_CNTL_IB2_INT_MASK_SIZE; + unsigned int ib1_int_mask : CP_INT_CNTL_IB1_INT_MASK_SIZE; + unsigned int rb_int_mask : CP_INT_CNTL_RB_INT_MASK_SIZE; + } cp_int_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_int_cntl_t { + unsigned int rb_int_mask : CP_INT_CNTL_RB_INT_MASK_SIZE; + unsigned int ib1_int_mask : CP_INT_CNTL_IB1_INT_MASK_SIZE; + unsigned int ib2_int_mask : CP_INT_CNTL_IB2_INT_MASK_SIZE; + unsigned int : 1; + unsigned int ib_error_mask : CP_INT_CNTL_IB_ERROR_MASK_SIZE; + unsigned int reserved_bit_error_mask : CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE; + unsigned int protected_mode_error_mask : CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE; + unsigned int opcode_error_mask : CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE; + unsigned int t0_packet_in_ib_mask : CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE; + unsigned int : 3; + unsigned int sw_int_mask : CP_INT_CNTL_SW_INT_MASK_SIZE; + unsigned int : 19; + } cp_int_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_int_cntl_t f; +} cp_int_cntl_u; + + +/* + * CP_INT_STATUS struct + */ + +#define CP_INT_STATUS_SW_INT_STAT_SIZE 1 +#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE 1 +#define CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE 1 +#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE 1 +#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE 1 +#define CP_INT_STATUS_IB_ERROR_STAT_SIZE 1 +#define CP_INT_STATUS_IB2_INT_STAT_SIZE 1 +#define CP_INT_STATUS_IB1_INT_STAT_SIZE 1 +#define CP_INT_STATUS_RB_INT_STAT_SIZE 1 + +#define CP_INT_STATUS_SW_INT_STAT_SHIFT 19 +#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT 23 +#define CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT 24 +#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT 25 +#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT 26 +#define CP_INT_STATUS_IB_ERROR_STAT_SHIFT 27 +#define CP_INT_STATUS_IB2_INT_STAT_SHIFT 29 +#define CP_INT_STATUS_IB1_INT_STAT_SHIFT 30 +#define CP_INT_STATUS_RB_INT_STAT_SHIFT 31 + +#define CP_INT_STATUS_SW_INT_STAT_MASK 0x00080000 +#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK 0x00800000 +#define CP_INT_STATUS_OPCODE_ERROR_STAT_MASK 0x01000000 +#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK 0x02000000 +#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK 0x04000000 +#define CP_INT_STATUS_IB_ERROR_STAT_MASK 0x08000000 +#define CP_INT_STATUS_IB2_INT_STAT_MASK 0x20000000 +#define CP_INT_STATUS_IB1_INT_STAT_MASK 0x40000000 +#define CP_INT_STATUS_RB_INT_STAT_MASK 0x80000000 + +#define CP_INT_STATUS_MASK \ + (CP_INT_STATUS_SW_INT_STAT_MASK | \ + CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK | \ + CP_INT_STATUS_OPCODE_ERROR_STAT_MASK | \ + CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK | \ + CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK | \ + CP_INT_STATUS_IB_ERROR_STAT_MASK | \ + CP_INT_STATUS_IB2_INT_STAT_MASK | \ + CP_INT_STATUS_IB1_INT_STAT_MASK | \ + CP_INT_STATUS_RB_INT_STAT_MASK) + +#define CP_INT_STATUS(sw_int_stat, t0_packet_in_ib_stat, opcode_error_stat, protected_mode_error_stat, reserved_bit_error_stat, ib_error_stat, ib2_int_stat, ib1_int_stat, rb_int_stat) \ + ((sw_int_stat << CP_INT_STATUS_SW_INT_STAT_SHIFT) | \ + (t0_packet_in_ib_stat << CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT) | \ + (opcode_error_stat << CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT) | \ + (protected_mode_error_stat << CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT) | \ + (reserved_bit_error_stat << CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT) | \ + (ib_error_stat << CP_INT_STATUS_IB_ERROR_STAT_SHIFT) | \ + (ib2_int_stat << CP_INT_STATUS_IB2_INT_STAT_SHIFT) | \ + (ib1_int_stat << CP_INT_STATUS_IB1_INT_STAT_SHIFT) | \ + (rb_int_stat << CP_INT_STATUS_RB_INT_STAT_SHIFT)) + +#define CP_INT_STATUS_GET_SW_INT_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_SW_INT_STAT_MASK) >> CP_INT_STATUS_SW_INT_STAT_SHIFT) +#define CP_INT_STATUS_GET_T0_PACKET_IN_IB_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK) >> CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT) +#define CP_INT_STATUS_GET_OPCODE_ERROR_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_OPCODE_ERROR_STAT_MASK) >> CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_GET_PROTECTED_MODE_ERROR_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK) >> CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_GET_RESERVED_BIT_ERROR_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK) >> CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_GET_IB_ERROR_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_IB_ERROR_STAT_MASK) >> CP_INT_STATUS_IB_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_GET_IB2_INT_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_IB2_INT_STAT_MASK) >> CP_INT_STATUS_IB2_INT_STAT_SHIFT) +#define CP_INT_STATUS_GET_IB1_INT_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_IB1_INT_STAT_MASK) >> CP_INT_STATUS_IB1_INT_STAT_SHIFT) +#define CP_INT_STATUS_GET_RB_INT_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_RB_INT_STAT_MASK) >> CP_INT_STATUS_RB_INT_STAT_SHIFT) + +#define CP_INT_STATUS_SET_SW_INT_STAT(cp_int_status_reg, sw_int_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_SW_INT_STAT_MASK) | (sw_int_stat << CP_INT_STATUS_SW_INT_STAT_SHIFT) +#define CP_INT_STATUS_SET_T0_PACKET_IN_IB_STAT(cp_int_status_reg, t0_packet_in_ib_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK) | (t0_packet_in_ib_stat << CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT) +#define CP_INT_STATUS_SET_OPCODE_ERROR_STAT(cp_int_status_reg, opcode_error_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_OPCODE_ERROR_STAT_MASK) | (opcode_error_stat << CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_SET_PROTECTED_MODE_ERROR_STAT(cp_int_status_reg, protected_mode_error_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK) | (protected_mode_error_stat << CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_SET_RESERVED_BIT_ERROR_STAT(cp_int_status_reg, reserved_bit_error_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK) | (reserved_bit_error_stat << CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_SET_IB_ERROR_STAT(cp_int_status_reg, ib_error_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB_ERROR_STAT_MASK) | (ib_error_stat << CP_INT_STATUS_IB_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_SET_IB2_INT_STAT(cp_int_status_reg, ib2_int_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB2_INT_STAT_MASK) | (ib2_int_stat << CP_INT_STATUS_IB2_INT_STAT_SHIFT) +#define CP_INT_STATUS_SET_IB1_INT_STAT(cp_int_status_reg, ib1_int_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB1_INT_STAT_MASK) | (ib1_int_stat << CP_INT_STATUS_IB1_INT_STAT_SHIFT) +#define CP_INT_STATUS_SET_RB_INT_STAT(cp_int_status_reg, rb_int_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_RB_INT_STAT_MASK) | (rb_int_stat << CP_INT_STATUS_RB_INT_STAT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_int_status_t { + unsigned int : 19; + unsigned int sw_int_stat : CP_INT_STATUS_SW_INT_STAT_SIZE; + unsigned int : 3; + unsigned int t0_packet_in_ib_stat : CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE; + unsigned int opcode_error_stat : CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE; + unsigned int protected_mode_error_stat : CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE; + unsigned int reserved_bit_error_stat : CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE; + unsigned int ib_error_stat : CP_INT_STATUS_IB_ERROR_STAT_SIZE; + unsigned int : 1; + unsigned int ib2_int_stat : CP_INT_STATUS_IB2_INT_STAT_SIZE; + unsigned int ib1_int_stat : CP_INT_STATUS_IB1_INT_STAT_SIZE; + unsigned int rb_int_stat : CP_INT_STATUS_RB_INT_STAT_SIZE; + } cp_int_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_int_status_t { + unsigned int rb_int_stat : CP_INT_STATUS_RB_INT_STAT_SIZE; + unsigned int ib1_int_stat : CP_INT_STATUS_IB1_INT_STAT_SIZE; + unsigned int ib2_int_stat : CP_INT_STATUS_IB2_INT_STAT_SIZE; + unsigned int : 1; + unsigned int ib_error_stat : CP_INT_STATUS_IB_ERROR_STAT_SIZE; + unsigned int reserved_bit_error_stat : CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE; + unsigned int protected_mode_error_stat : CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE; + unsigned int opcode_error_stat : CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE; + unsigned int t0_packet_in_ib_stat : CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE; + unsigned int : 3; + unsigned int sw_int_stat : CP_INT_STATUS_SW_INT_STAT_SIZE; + unsigned int : 19; + } cp_int_status_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_int_status_t f; +} cp_int_status_u; + + +/* + * CP_INT_ACK struct + */ + +#define CP_INT_ACK_SW_INT_ACK_SIZE 1 +#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE 1 +#define CP_INT_ACK_OPCODE_ERROR_ACK_SIZE 1 +#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE 1 +#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE 1 +#define CP_INT_ACK_IB_ERROR_ACK_SIZE 1 +#define CP_INT_ACK_IB2_INT_ACK_SIZE 1 +#define CP_INT_ACK_IB1_INT_ACK_SIZE 1 +#define CP_INT_ACK_RB_INT_ACK_SIZE 1 + +#define CP_INT_ACK_SW_INT_ACK_SHIFT 19 +#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT 23 +#define CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT 24 +#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT 25 +#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT 26 +#define CP_INT_ACK_IB_ERROR_ACK_SHIFT 27 +#define CP_INT_ACK_IB2_INT_ACK_SHIFT 29 +#define CP_INT_ACK_IB1_INT_ACK_SHIFT 30 +#define CP_INT_ACK_RB_INT_ACK_SHIFT 31 + +#define CP_INT_ACK_SW_INT_ACK_MASK 0x00080000 +#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK 0x00800000 +#define CP_INT_ACK_OPCODE_ERROR_ACK_MASK 0x01000000 +#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK 0x02000000 +#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK 0x04000000 +#define CP_INT_ACK_IB_ERROR_ACK_MASK 0x08000000 +#define CP_INT_ACK_IB2_INT_ACK_MASK 0x20000000 +#define CP_INT_ACK_IB1_INT_ACK_MASK 0x40000000 +#define CP_INT_ACK_RB_INT_ACK_MASK 0x80000000 + +#define CP_INT_ACK_MASK \ + (CP_INT_ACK_SW_INT_ACK_MASK | \ + CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK | \ + CP_INT_ACK_OPCODE_ERROR_ACK_MASK | \ + CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK | \ + CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK | \ + CP_INT_ACK_IB_ERROR_ACK_MASK | \ + CP_INT_ACK_IB2_INT_ACK_MASK | \ + CP_INT_ACK_IB1_INT_ACK_MASK | \ + CP_INT_ACK_RB_INT_ACK_MASK) + +#define CP_INT_ACK(sw_int_ack, t0_packet_in_ib_ack, opcode_error_ack, protected_mode_error_ack, reserved_bit_error_ack, ib_error_ack, ib2_int_ack, ib1_int_ack, rb_int_ack) \ + ((sw_int_ack << CP_INT_ACK_SW_INT_ACK_SHIFT) | \ + (t0_packet_in_ib_ack << CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT) | \ + (opcode_error_ack << CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT) | \ + (protected_mode_error_ack << CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT) | \ + (reserved_bit_error_ack << CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT) | \ + (ib_error_ack << CP_INT_ACK_IB_ERROR_ACK_SHIFT) | \ + (ib2_int_ack << CP_INT_ACK_IB2_INT_ACK_SHIFT) | \ + (ib1_int_ack << CP_INT_ACK_IB1_INT_ACK_SHIFT) | \ + (rb_int_ack << CP_INT_ACK_RB_INT_ACK_SHIFT)) + +#define CP_INT_ACK_GET_SW_INT_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_SW_INT_ACK_MASK) >> CP_INT_ACK_SW_INT_ACK_SHIFT) +#define CP_INT_ACK_GET_T0_PACKET_IN_IB_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK) >> CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT) +#define CP_INT_ACK_GET_OPCODE_ERROR_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_OPCODE_ERROR_ACK_MASK) >> CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT) +#define CP_INT_ACK_GET_PROTECTED_MODE_ERROR_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK) >> CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT) +#define CP_INT_ACK_GET_RESERVED_BIT_ERROR_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK) >> CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT) +#define CP_INT_ACK_GET_IB_ERROR_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_IB_ERROR_ACK_MASK) >> CP_INT_ACK_IB_ERROR_ACK_SHIFT) +#define CP_INT_ACK_GET_IB2_INT_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_IB2_INT_ACK_MASK) >> CP_INT_ACK_IB2_INT_ACK_SHIFT) +#define CP_INT_ACK_GET_IB1_INT_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_IB1_INT_ACK_MASK) >> CP_INT_ACK_IB1_INT_ACK_SHIFT) +#define CP_INT_ACK_GET_RB_INT_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_RB_INT_ACK_MASK) >> CP_INT_ACK_RB_INT_ACK_SHIFT) + +#define CP_INT_ACK_SET_SW_INT_ACK(cp_int_ack_reg, sw_int_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_SW_INT_ACK_MASK) | (sw_int_ack << CP_INT_ACK_SW_INT_ACK_SHIFT) +#define CP_INT_ACK_SET_T0_PACKET_IN_IB_ACK(cp_int_ack_reg, t0_packet_in_ib_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK) | (t0_packet_in_ib_ack << CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT) +#define CP_INT_ACK_SET_OPCODE_ERROR_ACK(cp_int_ack_reg, opcode_error_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_OPCODE_ERROR_ACK_MASK) | (opcode_error_ack << CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT) +#define CP_INT_ACK_SET_PROTECTED_MODE_ERROR_ACK(cp_int_ack_reg, protected_mode_error_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK) | (protected_mode_error_ack << CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT) +#define CP_INT_ACK_SET_RESERVED_BIT_ERROR_ACK(cp_int_ack_reg, reserved_bit_error_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK) | (reserved_bit_error_ack << CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT) +#define CP_INT_ACK_SET_IB_ERROR_ACK(cp_int_ack_reg, ib_error_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB_ERROR_ACK_MASK) | (ib_error_ack << CP_INT_ACK_IB_ERROR_ACK_SHIFT) +#define CP_INT_ACK_SET_IB2_INT_ACK(cp_int_ack_reg, ib2_int_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB2_INT_ACK_MASK) | (ib2_int_ack << CP_INT_ACK_IB2_INT_ACK_SHIFT) +#define CP_INT_ACK_SET_IB1_INT_ACK(cp_int_ack_reg, ib1_int_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB1_INT_ACK_MASK) | (ib1_int_ack << CP_INT_ACK_IB1_INT_ACK_SHIFT) +#define CP_INT_ACK_SET_RB_INT_ACK(cp_int_ack_reg, rb_int_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_RB_INT_ACK_MASK) | (rb_int_ack << CP_INT_ACK_RB_INT_ACK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_int_ack_t { + unsigned int : 19; + unsigned int sw_int_ack : CP_INT_ACK_SW_INT_ACK_SIZE; + unsigned int : 3; + unsigned int t0_packet_in_ib_ack : CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE; + unsigned int opcode_error_ack : CP_INT_ACK_OPCODE_ERROR_ACK_SIZE; + unsigned int protected_mode_error_ack : CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE; + unsigned int reserved_bit_error_ack : CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE; + unsigned int ib_error_ack : CP_INT_ACK_IB_ERROR_ACK_SIZE; + unsigned int : 1; + unsigned int ib2_int_ack : CP_INT_ACK_IB2_INT_ACK_SIZE; + unsigned int ib1_int_ack : CP_INT_ACK_IB1_INT_ACK_SIZE; + unsigned int rb_int_ack : CP_INT_ACK_RB_INT_ACK_SIZE; + } cp_int_ack_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_int_ack_t { + unsigned int rb_int_ack : CP_INT_ACK_RB_INT_ACK_SIZE; + unsigned int ib1_int_ack : CP_INT_ACK_IB1_INT_ACK_SIZE; + unsigned int ib2_int_ack : CP_INT_ACK_IB2_INT_ACK_SIZE; + unsigned int : 1; + unsigned int ib_error_ack : CP_INT_ACK_IB_ERROR_ACK_SIZE; + unsigned int reserved_bit_error_ack : CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE; + unsigned int protected_mode_error_ack : CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE; + unsigned int opcode_error_ack : CP_INT_ACK_OPCODE_ERROR_ACK_SIZE; + unsigned int t0_packet_in_ib_ack : CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE; + unsigned int : 3; + unsigned int sw_int_ack : CP_INT_ACK_SW_INT_ACK_SIZE; + unsigned int : 19; + } cp_int_ack_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_int_ack_t f; +} cp_int_ack_u; + + +/* + * CP_PFP_UCODE_ADDR struct + */ + +#define CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE 9 + +#define CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT 0 + +#define CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK 0x000001ff + +#define CP_PFP_UCODE_ADDR_MASK \ + (CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) + +#define CP_PFP_UCODE_ADDR(ucode_addr) \ + ((ucode_addr << CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT)) + +#define CP_PFP_UCODE_ADDR_GET_UCODE_ADDR(cp_pfp_ucode_addr) \ + ((cp_pfp_ucode_addr & CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) >> CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT) + +#define CP_PFP_UCODE_ADDR_SET_UCODE_ADDR(cp_pfp_ucode_addr_reg, ucode_addr) \ + cp_pfp_ucode_addr_reg = (cp_pfp_ucode_addr_reg & ~CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) | (ucode_addr << CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_pfp_ucode_addr_t { + unsigned int ucode_addr : CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE; + unsigned int : 23; + } cp_pfp_ucode_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_pfp_ucode_addr_t { + unsigned int : 23; + unsigned int ucode_addr : CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE; + } cp_pfp_ucode_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_pfp_ucode_addr_t f; +} cp_pfp_ucode_addr_u; + + +/* + * CP_PFP_UCODE_DATA struct + */ + +#define CP_PFP_UCODE_DATA_UCODE_DATA_SIZE 24 + +#define CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT 0 + +#define CP_PFP_UCODE_DATA_UCODE_DATA_MASK 0x00ffffff + +#define CP_PFP_UCODE_DATA_MASK \ + (CP_PFP_UCODE_DATA_UCODE_DATA_MASK) + +#define CP_PFP_UCODE_DATA(ucode_data) \ + ((ucode_data << CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT)) + +#define CP_PFP_UCODE_DATA_GET_UCODE_DATA(cp_pfp_ucode_data) \ + ((cp_pfp_ucode_data & CP_PFP_UCODE_DATA_UCODE_DATA_MASK) >> CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT) + +#define CP_PFP_UCODE_DATA_SET_UCODE_DATA(cp_pfp_ucode_data_reg, ucode_data) \ + cp_pfp_ucode_data_reg = (cp_pfp_ucode_data_reg & ~CP_PFP_UCODE_DATA_UCODE_DATA_MASK) | (ucode_data << CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_pfp_ucode_data_t { + unsigned int ucode_data : CP_PFP_UCODE_DATA_UCODE_DATA_SIZE; + unsigned int : 8; + } cp_pfp_ucode_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_pfp_ucode_data_t { + unsigned int : 8; + unsigned int ucode_data : CP_PFP_UCODE_DATA_UCODE_DATA_SIZE; + } cp_pfp_ucode_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_pfp_ucode_data_t f; +} cp_pfp_ucode_data_u; + + +/* + * CP_PERFMON_CNTL struct + */ + +#define CP_PERFMON_CNTL_PERFMON_STATE_SIZE 4 +#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE 2 + +#define CP_PERFMON_CNTL_PERFMON_STATE_SHIFT 0 +#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT 8 + +#define CP_PERFMON_CNTL_PERFMON_STATE_MASK 0x0000000f +#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK 0x00000300 + +#define CP_PERFMON_CNTL_MASK \ + (CP_PERFMON_CNTL_PERFMON_STATE_MASK | \ + CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) + +#define CP_PERFMON_CNTL(perfmon_state, perfmon_enable_mode) \ + ((perfmon_state << CP_PERFMON_CNTL_PERFMON_STATE_SHIFT) | \ + (perfmon_enable_mode << CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT)) + +#define CP_PERFMON_CNTL_GET_PERFMON_STATE(cp_perfmon_cntl) \ + ((cp_perfmon_cntl & CP_PERFMON_CNTL_PERFMON_STATE_MASK) >> CP_PERFMON_CNTL_PERFMON_STATE_SHIFT) +#define CP_PERFMON_CNTL_GET_PERFMON_ENABLE_MODE(cp_perfmon_cntl) \ + ((cp_perfmon_cntl & CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) >> CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT) + +#define CP_PERFMON_CNTL_SET_PERFMON_STATE(cp_perfmon_cntl_reg, perfmon_state) \ + cp_perfmon_cntl_reg = (cp_perfmon_cntl_reg & ~CP_PERFMON_CNTL_PERFMON_STATE_MASK) | (perfmon_state << CP_PERFMON_CNTL_PERFMON_STATE_SHIFT) +#define CP_PERFMON_CNTL_SET_PERFMON_ENABLE_MODE(cp_perfmon_cntl_reg, perfmon_enable_mode) \ + cp_perfmon_cntl_reg = (cp_perfmon_cntl_reg & ~CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) | (perfmon_enable_mode << CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_perfmon_cntl_t { + unsigned int perfmon_state : CP_PERFMON_CNTL_PERFMON_STATE_SIZE; + unsigned int : 4; + unsigned int perfmon_enable_mode : CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE; + unsigned int : 22; + } cp_perfmon_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_perfmon_cntl_t { + unsigned int : 22; + unsigned int perfmon_enable_mode : CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE; + unsigned int : 4; + unsigned int perfmon_state : CP_PERFMON_CNTL_PERFMON_STATE_SIZE; + } cp_perfmon_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_perfmon_cntl_t f; +} cp_perfmon_cntl_u; + + +/* + * CP_PERFCOUNTER_SELECT struct + */ + +#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE 6 + +#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT 0 + +#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK 0x0000003f + +#define CP_PERFCOUNTER_SELECT_MASK \ + (CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) + +#define CP_PERFCOUNTER_SELECT(perfcount_sel) \ + ((perfcount_sel << CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT)) + +#define CP_PERFCOUNTER_SELECT_GET_PERFCOUNT_SEL(cp_perfcounter_select) \ + ((cp_perfcounter_select & CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) >> CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT) + +#define CP_PERFCOUNTER_SELECT_SET_PERFCOUNT_SEL(cp_perfcounter_select_reg, perfcount_sel) \ + cp_perfcounter_select_reg = (cp_perfcounter_select_reg & ~CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) | (perfcount_sel << CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_perfcounter_select_t { + unsigned int perfcount_sel : CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE; + unsigned int : 26; + } cp_perfcounter_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_perfcounter_select_t { + unsigned int : 26; + unsigned int perfcount_sel : CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE; + } cp_perfcounter_select_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_perfcounter_select_t f; +} cp_perfcounter_select_u; + + +/* + * CP_PERFCOUNTER_LO struct + */ + +#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE 32 + +#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT 0 + +#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK 0xffffffff + +#define CP_PERFCOUNTER_LO_MASK \ + (CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) + +#define CP_PERFCOUNTER_LO(perfcount_lo) \ + ((perfcount_lo << CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT)) + +#define CP_PERFCOUNTER_LO_GET_PERFCOUNT_LO(cp_perfcounter_lo) \ + ((cp_perfcounter_lo & CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) >> CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT) + +#define CP_PERFCOUNTER_LO_SET_PERFCOUNT_LO(cp_perfcounter_lo_reg, perfcount_lo) \ + cp_perfcounter_lo_reg = (cp_perfcounter_lo_reg & ~CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) | (perfcount_lo << CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_perfcounter_lo_t { + unsigned int perfcount_lo : CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE; + } cp_perfcounter_lo_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_perfcounter_lo_t { + unsigned int perfcount_lo : CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE; + } cp_perfcounter_lo_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_perfcounter_lo_t f; +} cp_perfcounter_lo_u; + + +/* + * CP_PERFCOUNTER_HI struct + */ + +#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE 16 + +#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT 0 + +#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK 0x0000ffff + +#define CP_PERFCOUNTER_HI_MASK \ + (CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) + +#define CP_PERFCOUNTER_HI(perfcount_hi) \ + ((perfcount_hi << CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT)) + +#define CP_PERFCOUNTER_HI_GET_PERFCOUNT_HI(cp_perfcounter_hi) \ + ((cp_perfcounter_hi & CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) >> CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT) + +#define CP_PERFCOUNTER_HI_SET_PERFCOUNT_HI(cp_perfcounter_hi_reg, perfcount_hi) \ + cp_perfcounter_hi_reg = (cp_perfcounter_hi_reg & ~CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) | (perfcount_hi << CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_perfcounter_hi_t { + unsigned int perfcount_hi : CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE; + unsigned int : 16; + } cp_perfcounter_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_perfcounter_hi_t { + unsigned int : 16; + unsigned int perfcount_hi : CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE; + } cp_perfcounter_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_perfcounter_hi_t f; +} cp_perfcounter_hi_u; + + +/* + * CP_BIN_MASK_LO struct + */ + +#define CP_BIN_MASK_LO_BIN_MASK_LO_SIZE 32 + +#define CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT 0 + +#define CP_BIN_MASK_LO_BIN_MASK_LO_MASK 0xffffffff + +#define CP_BIN_MASK_LO_MASK \ + (CP_BIN_MASK_LO_BIN_MASK_LO_MASK) + +#define CP_BIN_MASK_LO(bin_mask_lo) \ + ((bin_mask_lo << CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT)) + +#define CP_BIN_MASK_LO_GET_BIN_MASK_LO(cp_bin_mask_lo) \ + ((cp_bin_mask_lo & CP_BIN_MASK_LO_BIN_MASK_LO_MASK) >> CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT) + +#define CP_BIN_MASK_LO_SET_BIN_MASK_LO(cp_bin_mask_lo_reg, bin_mask_lo) \ + cp_bin_mask_lo_reg = (cp_bin_mask_lo_reg & ~CP_BIN_MASK_LO_BIN_MASK_LO_MASK) | (bin_mask_lo << CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_bin_mask_lo_t { + unsigned int bin_mask_lo : CP_BIN_MASK_LO_BIN_MASK_LO_SIZE; + } cp_bin_mask_lo_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_bin_mask_lo_t { + unsigned int bin_mask_lo : CP_BIN_MASK_LO_BIN_MASK_LO_SIZE; + } cp_bin_mask_lo_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_bin_mask_lo_t f; +} cp_bin_mask_lo_u; + + +/* + * CP_BIN_MASK_HI struct + */ + +#define CP_BIN_MASK_HI_BIN_MASK_HI_SIZE 32 + +#define CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT 0 + +#define CP_BIN_MASK_HI_BIN_MASK_HI_MASK 0xffffffff + +#define CP_BIN_MASK_HI_MASK \ + (CP_BIN_MASK_HI_BIN_MASK_HI_MASK) + +#define CP_BIN_MASK_HI(bin_mask_hi) \ + ((bin_mask_hi << CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT)) + +#define CP_BIN_MASK_HI_GET_BIN_MASK_HI(cp_bin_mask_hi) \ + ((cp_bin_mask_hi & CP_BIN_MASK_HI_BIN_MASK_HI_MASK) >> CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT) + +#define CP_BIN_MASK_HI_SET_BIN_MASK_HI(cp_bin_mask_hi_reg, bin_mask_hi) \ + cp_bin_mask_hi_reg = (cp_bin_mask_hi_reg & ~CP_BIN_MASK_HI_BIN_MASK_HI_MASK) | (bin_mask_hi << CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_bin_mask_hi_t { + unsigned int bin_mask_hi : CP_BIN_MASK_HI_BIN_MASK_HI_SIZE; + } cp_bin_mask_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_bin_mask_hi_t { + unsigned int bin_mask_hi : CP_BIN_MASK_HI_BIN_MASK_HI_SIZE; + } cp_bin_mask_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_bin_mask_hi_t f; +} cp_bin_mask_hi_u; + + +/* + * CP_BIN_SELECT_LO struct + */ + +#define CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE 32 + +#define CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT 0 + +#define CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK 0xffffffff + +#define CP_BIN_SELECT_LO_MASK \ + (CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) + +#define CP_BIN_SELECT_LO(bin_select_lo) \ + ((bin_select_lo << CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT)) + +#define CP_BIN_SELECT_LO_GET_BIN_SELECT_LO(cp_bin_select_lo) \ + ((cp_bin_select_lo & CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) >> CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT) + +#define CP_BIN_SELECT_LO_SET_BIN_SELECT_LO(cp_bin_select_lo_reg, bin_select_lo) \ + cp_bin_select_lo_reg = (cp_bin_select_lo_reg & ~CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) | (bin_select_lo << CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_bin_select_lo_t { + unsigned int bin_select_lo : CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE; + } cp_bin_select_lo_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_bin_select_lo_t { + unsigned int bin_select_lo : CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE; + } cp_bin_select_lo_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_bin_select_lo_t f; +} cp_bin_select_lo_u; + + +/* + * CP_BIN_SELECT_HI struct + */ + +#define CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE 32 + +#define CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT 0 + +#define CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK 0xffffffff + +#define CP_BIN_SELECT_HI_MASK \ + (CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) + +#define CP_BIN_SELECT_HI(bin_select_hi) \ + ((bin_select_hi << CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT)) + +#define CP_BIN_SELECT_HI_GET_BIN_SELECT_HI(cp_bin_select_hi) \ + ((cp_bin_select_hi & CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) >> CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT) + +#define CP_BIN_SELECT_HI_SET_BIN_SELECT_HI(cp_bin_select_hi_reg, bin_select_hi) \ + cp_bin_select_hi_reg = (cp_bin_select_hi_reg & ~CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) | (bin_select_hi << CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_bin_select_hi_t { + unsigned int bin_select_hi : CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE; + } cp_bin_select_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_bin_select_hi_t { + unsigned int bin_select_hi : CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE; + } cp_bin_select_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_bin_select_hi_t f; +} cp_bin_select_hi_u; + + +/* + * CP_NV_FLAGS_0 struct + */ + +#define CP_NV_FLAGS_0_DISCARD_0_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_0_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_1_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_1_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_2_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_2_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_3_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_3_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_4_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_4_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_5_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_5_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_6_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_6_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_7_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_7_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_8_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_8_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_9_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_9_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_10_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_10_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_11_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_11_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_12_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_12_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_13_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_13_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_14_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_14_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_15_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_15_SIZE 1 + +#define CP_NV_FLAGS_0_DISCARD_0_SHIFT 0 +#define CP_NV_FLAGS_0_END_RCVD_0_SHIFT 1 +#define CP_NV_FLAGS_0_DISCARD_1_SHIFT 2 +#define CP_NV_FLAGS_0_END_RCVD_1_SHIFT 3 +#define CP_NV_FLAGS_0_DISCARD_2_SHIFT 4 +#define CP_NV_FLAGS_0_END_RCVD_2_SHIFT 5 +#define CP_NV_FLAGS_0_DISCARD_3_SHIFT 6 +#define CP_NV_FLAGS_0_END_RCVD_3_SHIFT 7 +#define CP_NV_FLAGS_0_DISCARD_4_SHIFT 8 +#define CP_NV_FLAGS_0_END_RCVD_4_SHIFT 9 +#define CP_NV_FLAGS_0_DISCARD_5_SHIFT 10 +#define CP_NV_FLAGS_0_END_RCVD_5_SHIFT 11 +#define CP_NV_FLAGS_0_DISCARD_6_SHIFT 12 +#define CP_NV_FLAGS_0_END_RCVD_6_SHIFT 13 +#define CP_NV_FLAGS_0_DISCARD_7_SHIFT 14 +#define CP_NV_FLAGS_0_END_RCVD_7_SHIFT 15 +#define CP_NV_FLAGS_0_DISCARD_8_SHIFT 16 +#define CP_NV_FLAGS_0_END_RCVD_8_SHIFT 17 +#define CP_NV_FLAGS_0_DISCARD_9_SHIFT 18 +#define CP_NV_FLAGS_0_END_RCVD_9_SHIFT 19 +#define CP_NV_FLAGS_0_DISCARD_10_SHIFT 20 +#define CP_NV_FLAGS_0_END_RCVD_10_SHIFT 21 +#define CP_NV_FLAGS_0_DISCARD_11_SHIFT 22 +#define CP_NV_FLAGS_0_END_RCVD_11_SHIFT 23 +#define CP_NV_FLAGS_0_DISCARD_12_SHIFT 24 +#define CP_NV_FLAGS_0_END_RCVD_12_SHIFT 25 +#define CP_NV_FLAGS_0_DISCARD_13_SHIFT 26 +#define CP_NV_FLAGS_0_END_RCVD_13_SHIFT 27 +#define CP_NV_FLAGS_0_DISCARD_14_SHIFT 28 +#define CP_NV_FLAGS_0_END_RCVD_14_SHIFT 29 +#define CP_NV_FLAGS_0_DISCARD_15_SHIFT 30 +#define CP_NV_FLAGS_0_END_RCVD_15_SHIFT 31 + +#define CP_NV_FLAGS_0_DISCARD_0_MASK 0x00000001 +#define CP_NV_FLAGS_0_END_RCVD_0_MASK 0x00000002 +#define CP_NV_FLAGS_0_DISCARD_1_MASK 0x00000004 +#define CP_NV_FLAGS_0_END_RCVD_1_MASK 0x00000008 +#define CP_NV_FLAGS_0_DISCARD_2_MASK 0x00000010 +#define CP_NV_FLAGS_0_END_RCVD_2_MASK 0x00000020 +#define CP_NV_FLAGS_0_DISCARD_3_MASK 0x00000040 +#define CP_NV_FLAGS_0_END_RCVD_3_MASK 0x00000080 +#define CP_NV_FLAGS_0_DISCARD_4_MASK 0x00000100 +#define CP_NV_FLAGS_0_END_RCVD_4_MASK 0x00000200 +#define CP_NV_FLAGS_0_DISCARD_5_MASK 0x00000400 +#define CP_NV_FLAGS_0_END_RCVD_5_MASK 0x00000800 +#define CP_NV_FLAGS_0_DISCARD_6_MASK 0x00001000 +#define CP_NV_FLAGS_0_END_RCVD_6_MASK 0x00002000 +#define CP_NV_FLAGS_0_DISCARD_7_MASK 0x00004000 +#define CP_NV_FLAGS_0_END_RCVD_7_MASK 0x00008000 +#define CP_NV_FLAGS_0_DISCARD_8_MASK 0x00010000 +#define CP_NV_FLAGS_0_END_RCVD_8_MASK 0x00020000 +#define CP_NV_FLAGS_0_DISCARD_9_MASK 0x00040000 +#define CP_NV_FLAGS_0_END_RCVD_9_MASK 0x00080000 +#define CP_NV_FLAGS_0_DISCARD_10_MASK 0x00100000 +#define CP_NV_FLAGS_0_END_RCVD_10_MASK 0x00200000 +#define CP_NV_FLAGS_0_DISCARD_11_MASK 0x00400000 +#define CP_NV_FLAGS_0_END_RCVD_11_MASK 0x00800000 +#define CP_NV_FLAGS_0_DISCARD_12_MASK 0x01000000 +#define CP_NV_FLAGS_0_END_RCVD_12_MASK 0x02000000 +#define CP_NV_FLAGS_0_DISCARD_13_MASK 0x04000000 +#define CP_NV_FLAGS_0_END_RCVD_13_MASK 0x08000000 +#define CP_NV_FLAGS_0_DISCARD_14_MASK 0x10000000 +#define CP_NV_FLAGS_0_END_RCVD_14_MASK 0x20000000 +#define CP_NV_FLAGS_0_DISCARD_15_MASK 0x40000000 +#define CP_NV_FLAGS_0_END_RCVD_15_MASK 0x80000000 + +#define CP_NV_FLAGS_0_MASK \ + (CP_NV_FLAGS_0_DISCARD_0_MASK | \ + CP_NV_FLAGS_0_END_RCVD_0_MASK | \ + CP_NV_FLAGS_0_DISCARD_1_MASK | \ + CP_NV_FLAGS_0_END_RCVD_1_MASK | \ + CP_NV_FLAGS_0_DISCARD_2_MASK | \ + CP_NV_FLAGS_0_END_RCVD_2_MASK | \ + CP_NV_FLAGS_0_DISCARD_3_MASK | \ + CP_NV_FLAGS_0_END_RCVD_3_MASK | \ + CP_NV_FLAGS_0_DISCARD_4_MASK | \ + CP_NV_FLAGS_0_END_RCVD_4_MASK | \ + CP_NV_FLAGS_0_DISCARD_5_MASK | \ + CP_NV_FLAGS_0_END_RCVD_5_MASK | \ + CP_NV_FLAGS_0_DISCARD_6_MASK | \ + CP_NV_FLAGS_0_END_RCVD_6_MASK | \ + CP_NV_FLAGS_0_DISCARD_7_MASK | \ + CP_NV_FLAGS_0_END_RCVD_7_MASK | \ + CP_NV_FLAGS_0_DISCARD_8_MASK | \ + CP_NV_FLAGS_0_END_RCVD_8_MASK | \ + CP_NV_FLAGS_0_DISCARD_9_MASK | \ + CP_NV_FLAGS_0_END_RCVD_9_MASK | \ + CP_NV_FLAGS_0_DISCARD_10_MASK | \ + CP_NV_FLAGS_0_END_RCVD_10_MASK | \ + CP_NV_FLAGS_0_DISCARD_11_MASK | \ + CP_NV_FLAGS_0_END_RCVD_11_MASK | \ + CP_NV_FLAGS_0_DISCARD_12_MASK | \ + CP_NV_FLAGS_0_END_RCVD_12_MASK | \ + CP_NV_FLAGS_0_DISCARD_13_MASK | \ + CP_NV_FLAGS_0_END_RCVD_13_MASK | \ + CP_NV_FLAGS_0_DISCARD_14_MASK | \ + CP_NV_FLAGS_0_END_RCVD_14_MASK | \ + CP_NV_FLAGS_0_DISCARD_15_MASK | \ + CP_NV_FLAGS_0_END_RCVD_15_MASK) + +#define CP_NV_FLAGS_0(discard_0, end_rcvd_0, discard_1, end_rcvd_1, discard_2, end_rcvd_2, discard_3, end_rcvd_3, discard_4, end_rcvd_4, discard_5, end_rcvd_5, discard_6, end_rcvd_6, discard_7, end_rcvd_7, discard_8, end_rcvd_8, discard_9, end_rcvd_9, discard_10, end_rcvd_10, discard_11, end_rcvd_11, discard_12, end_rcvd_12, discard_13, end_rcvd_13, discard_14, end_rcvd_14, discard_15, end_rcvd_15) \ + ((discard_0 << CP_NV_FLAGS_0_DISCARD_0_SHIFT) | \ + (end_rcvd_0 << CP_NV_FLAGS_0_END_RCVD_0_SHIFT) | \ + (discard_1 << CP_NV_FLAGS_0_DISCARD_1_SHIFT) | \ + (end_rcvd_1 << CP_NV_FLAGS_0_END_RCVD_1_SHIFT) | \ + (discard_2 << CP_NV_FLAGS_0_DISCARD_2_SHIFT) | \ + (end_rcvd_2 << CP_NV_FLAGS_0_END_RCVD_2_SHIFT) | \ + (discard_3 << CP_NV_FLAGS_0_DISCARD_3_SHIFT) | \ + (end_rcvd_3 << CP_NV_FLAGS_0_END_RCVD_3_SHIFT) | \ + (discard_4 << CP_NV_FLAGS_0_DISCARD_4_SHIFT) | \ + (end_rcvd_4 << CP_NV_FLAGS_0_END_RCVD_4_SHIFT) | \ + (discard_5 << CP_NV_FLAGS_0_DISCARD_5_SHIFT) | \ + (end_rcvd_5 << CP_NV_FLAGS_0_END_RCVD_5_SHIFT) | \ + (discard_6 << CP_NV_FLAGS_0_DISCARD_6_SHIFT) | \ + (end_rcvd_6 << CP_NV_FLAGS_0_END_RCVD_6_SHIFT) | \ + (discard_7 << CP_NV_FLAGS_0_DISCARD_7_SHIFT) | \ + (end_rcvd_7 << CP_NV_FLAGS_0_END_RCVD_7_SHIFT) | \ + (discard_8 << CP_NV_FLAGS_0_DISCARD_8_SHIFT) | \ + (end_rcvd_8 << CP_NV_FLAGS_0_END_RCVD_8_SHIFT) | \ + (discard_9 << CP_NV_FLAGS_0_DISCARD_9_SHIFT) | \ + (end_rcvd_9 << CP_NV_FLAGS_0_END_RCVD_9_SHIFT) | \ + (discard_10 << CP_NV_FLAGS_0_DISCARD_10_SHIFT) | \ + (end_rcvd_10 << CP_NV_FLAGS_0_END_RCVD_10_SHIFT) | \ + (discard_11 << CP_NV_FLAGS_0_DISCARD_11_SHIFT) | \ + (end_rcvd_11 << CP_NV_FLAGS_0_END_RCVD_11_SHIFT) | \ + (discard_12 << CP_NV_FLAGS_0_DISCARD_12_SHIFT) | \ + (end_rcvd_12 << CP_NV_FLAGS_0_END_RCVD_12_SHIFT) | \ + (discard_13 << CP_NV_FLAGS_0_DISCARD_13_SHIFT) | \ + (end_rcvd_13 << CP_NV_FLAGS_0_END_RCVD_13_SHIFT) | \ + (discard_14 << CP_NV_FLAGS_0_DISCARD_14_SHIFT) | \ + (end_rcvd_14 << CP_NV_FLAGS_0_END_RCVD_14_SHIFT) | \ + (discard_15 << CP_NV_FLAGS_0_DISCARD_15_SHIFT) | \ + (end_rcvd_15 << CP_NV_FLAGS_0_END_RCVD_15_SHIFT)) + +#define CP_NV_FLAGS_0_GET_DISCARD_0(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_0_MASK) >> CP_NV_FLAGS_0_DISCARD_0_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_0(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_0_MASK) >> CP_NV_FLAGS_0_END_RCVD_0_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_1(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_1_MASK) >> CP_NV_FLAGS_0_DISCARD_1_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_1(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_1_MASK) >> CP_NV_FLAGS_0_END_RCVD_1_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_2(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_2_MASK) >> CP_NV_FLAGS_0_DISCARD_2_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_2(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_2_MASK) >> CP_NV_FLAGS_0_END_RCVD_2_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_3(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_3_MASK) >> CP_NV_FLAGS_0_DISCARD_3_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_3(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_3_MASK) >> CP_NV_FLAGS_0_END_RCVD_3_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_4(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_4_MASK) >> CP_NV_FLAGS_0_DISCARD_4_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_4(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_4_MASK) >> CP_NV_FLAGS_0_END_RCVD_4_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_5(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_5_MASK) >> CP_NV_FLAGS_0_DISCARD_5_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_5(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_5_MASK) >> CP_NV_FLAGS_0_END_RCVD_5_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_6(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_6_MASK) >> CP_NV_FLAGS_0_DISCARD_6_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_6(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_6_MASK) >> CP_NV_FLAGS_0_END_RCVD_6_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_7(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_7_MASK) >> CP_NV_FLAGS_0_DISCARD_7_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_7(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_7_MASK) >> CP_NV_FLAGS_0_END_RCVD_7_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_8(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_8_MASK) >> CP_NV_FLAGS_0_DISCARD_8_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_8(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_8_MASK) >> CP_NV_FLAGS_0_END_RCVD_8_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_9(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_9_MASK) >> CP_NV_FLAGS_0_DISCARD_9_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_9(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_9_MASK) >> CP_NV_FLAGS_0_END_RCVD_9_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_10(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_10_MASK) >> CP_NV_FLAGS_0_DISCARD_10_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_10(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_10_MASK) >> CP_NV_FLAGS_0_END_RCVD_10_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_11(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_11_MASK) >> CP_NV_FLAGS_0_DISCARD_11_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_11(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_11_MASK) >> CP_NV_FLAGS_0_END_RCVD_11_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_12(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_12_MASK) >> CP_NV_FLAGS_0_DISCARD_12_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_12(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_12_MASK) >> CP_NV_FLAGS_0_END_RCVD_12_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_13(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_13_MASK) >> CP_NV_FLAGS_0_DISCARD_13_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_13(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_13_MASK) >> CP_NV_FLAGS_0_END_RCVD_13_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_14(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_14_MASK) >> CP_NV_FLAGS_0_DISCARD_14_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_14(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_14_MASK) >> CP_NV_FLAGS_0_END_RCVD_14_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_15(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_15_MASK) >> CP_NV_FLAGS_0_DISCARD_15_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_15(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_15_MASK) >> CP_NV_FLAGS_0_END_RCVD_15_SHIFT) + +#define CP_NV_FLAGS_0_SET_DISCARD_0(cp_nv_flags_0_reg, discard_0) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_0_MASK) | (discard_0 << CP_NV_FLAGS_0_DISCARD_0_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_0(cp_nv_flags_0_reg, end_rcvd_0) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_0_MASK) | (end_rcvd_0 << CP_NV_FLAGS_0_END_RCVD_0_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_1(cp_nv_flags_0_reg, discard_1) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_1_MASK) | (discard_1 << CP_NV_FLAGS_0_DISCARD_1_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_1(cp_nv_flags_0_reg, end_rcvd_1) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_1_MASK) | (end_rcvd_1 << CP_NV_FLAGS_0_END_RCVD_1_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_2(cp_nv_flags_0_reg, discard_2) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_2_MASK) | (discard_2 << CP_NV_FLAGS_0_DISCARD_2_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_2(cp_nv_flags_0_reg, end_rcvd_2) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_2_MASK) | (end_rcvd_2 << CP_NV_FLAGS_0_END_RCVD_2_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_3(cp_nv_flags_0_reg, discard_3) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_3_MASK) | (discard_3 << CP_NV_FLAGS_0_DISCARD_3_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_3(cp_nv_flags_0_reg, end_rcvd_3) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_3_MASK) | (end_rcvd_3 << CP_NV_FLAGS_0_END_RCVD_3_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_4(cp_nv_flags_0_reg, discard_4) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_4_MASK) | (discard_4 << CP_NV_FLAGS_0_DISCARD_4_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_4(cp_nv_flags_0_reg, end_rcvd_4) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_4_MASK) | (end_rcvd_4 << CP_NV_FLAGS_0_END_RCVD_4_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_5(cp_nv_flags_0_reg, discard_5) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_5_MASK) | (discard_5 << CP_NV_FLAGS_0_DISCARD_5_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_5(cp_nv_flags_0_reg, end_rcvd_5) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_5_MASK) | (end_rcvd_5 << CP_NV_FLAGS_0_END_RCVD_5_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_6(cp_nv_flags_0_reg, discard_6) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_6_MASK) | (discard_6 << CP_NV_FLAGS_0_DISCARD_6_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_6(cp_nv_flags_0_reg, end_rcvd_6) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_6_MASK) | (end_rcvd_6 << CP_NV_FLAGS_0_END_RCVD_6_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_7(cp_nv_flags_0_reg, discard_7) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_7_MASK) | (discard_7 << CP_NV_FLAGS_0_DISCARD_7_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_7(cp_nv_flags_0_reg, end_rcvd_7) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_7_MASK) | (end_rcvd_7 << CP_NV_FLAGS_0_END_RCVD_7_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_8(cp_nv_flags_0_reg, discard_8) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_8_MASK) | (discard_8 << CP_NV_FLAGS_0_DISCARD_8_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_8(cp_nv_flags_0_reg, end_rcvd_8) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_8_MASK) | (end_rcvd_8 << CP_NV_FLAGS_0_END_RCVD_8_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_9(cp_nv_flags_0_reg, discard_9) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_9_MASK) | (discard_9 << CP_NV_FLAGS_0_DISCARD_9_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_9(cp_nv_flags_0_reg, end_rcvd_9) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_9_MASK) | (end_rcvd_9 << CP_NV_FLAGS_0_END_RCVD_9_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_10(cp_nv_flags_0_reg, discard_10) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_10_MASK) | (discard_10 << CP_NV_FLAGS_0_DISCARD_10_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_10(cp_nv_flags_0_reg, end_rcvd_10) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_10_MASK) | (end_rcvd_10 << CP_NV_FLAGS_0_END_RCVD_10_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_11(cp_nv_flags_0_reg, discard_11) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_11_MASK) | (discard_11 << CP_NV_FLAGS_0_DISCARD_11_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_11(cp_nv_flags_0_reg, end_rcvd_11) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_11_MASK) | (end_rcvd_11 << CP_NV_FLAGS_0_END_RCVD_11_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_12(cp_nv_flags_0_reg, discard_12) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_12_MASK) | (discard_12 << CP_NV_FLAGS_0_DISCARD_12_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_12(cp_nv_flags_0_reg, end_rcvd_12) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_12_MASK) | (end_rcvd_12 << CP_NV_FLAGS_0_END_RCVD_12_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_13(cp_nv_flags_0_reg, discard_13) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_13_MASK) | (discard_13 << CP_NV_FLAGS_0_DISCARD_13_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_13(cp_nv_flags_0_reg, end_rcvd_13) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_13_MASK) | (end_rcvd_13 << CP_NV_FLAGS_0_END_RCVD_13_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_14(cp_nv_flags_0_reg, discard_14) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_14_MASK) | (discard_14 << CP_NV_FLAGS_0_DISCARD_14_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_14(cp_nv_flags_0_reg, end_rcvd_14) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_14_MASK) | (end_rcvd_14 << CP_NV_FLAGS_0_END_RCVD_14_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_15(cp_nv_flags_0_reg, discard_15) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_15_MASK) | (discard_15 << CP_NV_FLAGS_0_DISCARD_15_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_15(cp_nv_flags_0_reg, end_rcvd_15) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_15_MASK) | (end_rcvd_15 << CP_NV_FLAGS_0_END_RCVD_15_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_nv_flags_0_t { + unsigned int discard_0 : CP_NV_FLAGS_0_DISCARD_0_SIZE; + unsigned int end_rcvd_0 : CP_NV_FLAGS_0_END_RCVD_0_SIZE; + unsigned int discard_1 : CP_NV_FLAGS_0_DISCARD_1_SIZE; + unsigned int end_rcvd_1 : CP_NV_FLAGS_0_END_RCVD_1_SIZE; + unsigned int discard_2 : CP_NV_FLAGS_0_DISCARD_2_SIZE; + unsigned int end_rcvd_2 : CP_NV_FLAGS_0_END_RCVD_2_SIZE; + unsigned int discard_3 : CP_NV_FLAGS_0_DISCARD_3_SIZE; + unsigned int end_rcvd_3 : CP_NV_FLAGS_0_END_RCVD_3_SIZE; + unsigned int discard_4 : CP_NV_FLAGS_0_DISCARD_4_SIZE; + unsigned int end_rcvd_4 : CP_NV_FLAGS_0_END_RCVD_4_SIZE; + unsigned int discard_5 : CP_NV_FLAGS_0_DISCARD_5_SIZE; + unsigned int end_rcvd_5 : CP_NV_FLAGS_0_END_RCVD_5_SIZE; + unsigned int discard_6 : CP_NV_FLAGS_0_DISCARD_6_SIZE; + unsigned int end_rcvd_6 : CP_NV_FLAGS_0_END_RCVD_6_SIZE; + unsigned int discard_7 : CP_NV_FLAGS_0_DISCARD_7_SIZE; + unsigned int end_rcvd_7 : CP_NV_FLAGS_0_END_RCVD_7_SIZE; + unsigned int discard_8 : CP_NV_FLAGS_0_DISCARD_8_SIZE; + unsigned int end_rcvd_8 : CP_NV_FLAGS_0_END_RCVD_8_SIZE; + unsigned int discard_9 : CP_NV_FLAGS_0_DISCARD_9_SIZE; + unsigned int end_rcvd_9 : CP_NV_FLAGS_0_END_RCVD_9_SIZE; + unsigned int discard_10 : CP_NV_FLAGS_0_DISCARD_10_SIZE; + unsigned int end_rcvd_10 : CP_NV_FLAGS_0_END_RCVD_10_SIZE; + unsigned int discard_11 : CP_NV_FLAGS_0_DISCARD_11_SIZE; + unsigned int end_rcvd_11 : CP_NV_FLAGS_0_END_RCVD_11_SIZE; + unsigned int discard_12 : CP_NV_FLAGS_0_DISCARD_12_SIZE; + unsigned int end_rcvd_12 : CP_NV_FLAGS_0_END_RCVD_12_SIZE; + unsigned int discard_13 : CP_NV_FLAGS_0_DISCARD_13_SIZE; + unsigned int end_rcvd_13 : CP_NV_FLAGS_0_END_RCVD_13_SIZE; + unsigned int discard_14 : CP_NV_FLAGS_0_DISCARD_14_SIZE; + unsigned int end_rcvd_14 : CP_NV_FLAGS_0_END_RCVD_14_SIZE; + unsigned int discard_15 : CP_NV_FLAGS_0_DISCARD_15_SIZE; + unsigned int end_rcvd_15 : CP_NV_FLAGS_0_END_RCVD_15_SIZE; + } cp_nv_flags_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_nv_flags_0_t { + unsigned int end_rcvd_15 : CP_NV_FLAGS_0_END_RCVD_15_SIZE; + unsigned int discard_15 : CP_NV_FLAGS_0_DISCARD_15_SIZE; + unsigned int end_rcvd_14 : CP_NV_FLAGS_0_END_RCVD_14_SIZE; + unsigned int discard_14 : CP_NV_FLAGS_0_DISCARD_14_SIZE; + unsigned int end_rcvd_13 : CP_NV_FLAGS_0_END_RCVD_13_SIZE; + unsigned int discard_13 : CP_NV_FLAGS_0_DISCARD_13_SIZE; + unsigned int end_rcvd_12 : CP_NV_FLAGS_0_END_RCVD_12_SIZE; + unsigned int discard_12 : CP_NV_FLAGS_0_DISCARD_12_SIZE; + unsigned int end_rcvd_11 : CP_NV_FLAGS_0_END_RCVD_11_SIZE; + unsigned int discard_11 : CP_NV_FLAGS_0_DISCARD_11_SIZE; + unsigned int end_rcvd_10 : CP_NV_FLAGS_0_END_RCVD_10_SIZE; + unsigned int discard_10 : CP_NV_FLAGS_0_DISCARD_10_SIZE; + unsigned int end_rcvd_9 : CP_NV_FLAGS_0_END_RCVD_9_SIZE; + unsigned int discard_9 : CP_NV_FLAGS_0_DISCARD_9_SIZE; + unsigned int end_rcvd_8 : CP_NV_FLAGS_0_END_RCVD_8_SIZE; + unsigned int discard_8 : CP_NV_FLAGS_0_DISCARD_8_SIZE; + unsigned int end_rcvd_7 : CP_NV_FLAGS_0_END_RCVD_7_SIZE; + unsigned int discard_7 : CP_NV_FLAGS_0_DISCARD_7_SIZE; + unsigned int end_rcvd_6 : CP_NV_FLAGS_0_END_RCVD_6_SIZE; + unsigned int discard_6 : CP_NV_FLAGS_0_DISCARD_6_SIZE; + unsigned int end_rcvd_5 : CP_NV_FLAGS_0_END_RCVD_5_SIZE; + unsigned int discard_5 : CP_NV_FLAGS_0_DISCARD_5_SIZE; + unsigned int end_rcvd_4 : CP_NV_FLAGS_0_END_RCVD_4_SIZE; + unsigned int discard_4 : CP_NV_FLAGS_0_DISCARD_4_SIZE; + unsigned int end_rcvd_3 : CP_NV_FLAGS_0_END_RCVD_3_SIZE; + unsigned int discard_3 : CP_NV_FLAGS_0_DISCARD_3_SIZE; + unsigned int end_rcvd_2 : CP_NV_FLAGS_0_END_RCVD_2_SIZE; + unsigned int discard_2 : CP_NV_FLAGS_0_DISCARD_2_SIZE; + unsigned int end_rcvd_1 : CP_NV_FLAGS_0_END_RCVD_1_SIZE; + unsigned int discard_1 : CP_NV_FLAGS_0_DISCARD_1_SIZE; + unsigned int end_rcvd_0 : CP_NV_FLAGS_0_END_RCVD_0_SIZE; + unsigned int discard_0 : CP_NV_FLAGS_0_DISCARD_0_SIZE; + } cp_nv_flags_0_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_nv_flags_0_t f; +} cp_nv_flags_0_u; + + +/* + * CP_NV_FLAGS_1 struct + */ + +#define CP_NV_FLAGS_1_DISCARD_16_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_16_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_17_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_17_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_18_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_18_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_19_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_19_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_20_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_20_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_21_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_21_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_22_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_22_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_23_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_23_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_24_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_24_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_25_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_25_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_26_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_26_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_27_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_27_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_28_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_28_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_29_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_29_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_30_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_30_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_31_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_31_SIZE 1 + +#define CP_NV_FLAGS_1_DISCARD_16_SHIFT 0 +#define CP_NV_FLAGS_1_END_RCVD_16_SHIFT 1 +#define CP_NV_FLAGS_1_DISCARD_17_SHIFT 2 +#define CP_NV_FLAGS_1_END_RCVD_17_SHIFT 3 +#define CP_NV_FLAGS_1_DISCARD_18_SHIFT 4 +#define CP_NV_FLAGS_1_END_RCVD_18_SHIFT 5 +#define CP_NV_FLAGS_1_DISCARD_19_SHIFT 6 +#define CP_NV_FLAGS_1_END_RCVD_19_SHIFT 7 +#define CP_NV_FLAGS_1_DISCARD_20_SHIFT 8 +#define CP_NV_FLAGS_1_END_RCVD_20_SHIFT 9 +#define CP_NV_FLAGS_1_DISCARD_21_SHIFT 10 +#define CP_NV_FLAGS_1_END_RCVD_21_SHIFT 11 +#define CP_NV_FLAGS_1_DISCARD_22_SHIFT 12 +#define CP_NV_FLAGS_1_END_RCVD_22_SHIFT 13 +#define CP_NV_FLAGS_1_DISCARD_23_SHIFT 14 +#define CP_NV_FLAGS_1_END_RCVD_23_SHIFT 15 +#define CP_NV_FLAGS_1_DISCARD_24_SHIFT 16 +#define CP_NV_FLAGS_1_END_RCVD_24_SHIFT 17 +#define CP_NV_FLAGS_1_DISCARD_25_SHIFT 18 +#define CP_NV_FLAGS_1_END_RCVD_25_SHIFT 19 +#define CP_NV_FLAGS_1_DISCARD_26_SHIFT 20 +#define CP_NV_FLAGS_1_END_RCVD_26_SHIFT 21 +#define CP_NV_FLAGS_1_DISCARD_27_SHIFT 22 +#define CP_NV_FLAGS_1_END_RCVD_27_SHIFT 23 +#define CP_NV_FLAGS_1_DISCARD_28_SHIFT 24 +#define CP_NV_FLAGS_1_END_RCVD_28_SHIFT 25 +#define CP_NV_FLAGS_1_DISCARD_29_SHIFT 26 +#define CP_NV_FLAGS_1_END_RCVD_29_SHIFT 27 +#define CP_NV_FLAGS_1_DISCARD_30_SHIFT 28 +#define CP_NV_FLAGS_1_END_RCVD_30_SHIFT 29 +#define CP_NV_FLAGS_1_DISCARD_31_SHIFT 30 +#define CP_NV_FLAGS_1_END_RCVD_31_SHIFT 31 + +#define CP_NV_FLAGS_1_DISCARD_16_MASK 0x00000001 +#define CP_NV_FLAGS_1_END_RCVD_16_MASK 0x00000002 +#define CP_NV_FLAGS_1_DISCARD_17_MASK 0x00000004 +#define CP_NV_FLAGS_1_END_RCVD_17_MASK 0x00000008 +#define CP_NV_FLAGS_1_DISCARD_18_MASK 0x00000010 +#define CP_NV_FLAGS_1_END_RCVD_18_MASK 0x00000020 +#define CP_NV_FLAGS_1_DISCARD_19_MASK 0x00000040 +#define CP_NV_FLAGS_1_END_RCVD_19_MASK 0x00000080 +#define CP_NV_FLAGS_1_DISCARD_20_MASK 0x00000100 +#define CP_NV_FLAGS_1_END_RCVD_20_MASK 0x00000200 +#define CP_NV_FLAGS_1_DISCARD_21_MASK 0x00000400 +#define CP_NV_FLAGS_1_END_RCVD_21_MASK 0x00000800 +#define CP_NV_FLAGS_1_DISCARD_22_MASK 0x00001000 +#define CP_NV_FLAGS_1_END_RCVD_22_MASK 0x00002000 +#define CP_NV_FLAGS_1_DISCARD_23_MASK 0x00004000 +#define CP_NV_FLAGS_1_END_RCVD_23_MASK 0x00008000 +#define CP_NV_FLAGS_1_DISCARD_24_MASK 0x00010000 +#define CP_NV_FLAGS_1_END_RCVD_24_MASK 0x00020000 +#define CP_NV_FLAGS_1_DISCARD_25_MASK 0x00040000 +#define CP_NV_FLAGS_1_END_RCVD_25_MASK 0x00080000 +#define CP_NV_FLAGS_1_DISCARD_26_MASK 0x00100000 +#define CP_NV_FLAGS_1_END_RCVD_26_MASK 0x00200000 +#define CP_NV_FLAGS_1_DISCARD_27_MASK 0x00400000 +#define CP_NV_FLAGS_1_END_RCVD_27_MASK 0x00800000 +#define CP_NV_FLAGS_1_DISCARD_28_MASK 0x01000000 +#define CP_NV_FLAGS_1_END_RCVD_28_MASK 0x02000000 +#define CP_NV_FLAGS_1_DISCARD_29_MASK 0x04000000 +#define CP_NV_FLAGS_1_END_RCVD_29_MASK 0x08000000 +#define CP_NV_FLAGS_1_DISCARD_30_MASK 0x10000000 +#define CP_NV_FLAGS_1_END_RCVD_30_MASK 0x20000000 +#define CP_NV_FLAGS_1_DISCARD_31_MASK 0x40000000 +#define CP_NV_FLAGS_1_END_RCVD_31_MASK 0x80000000 + +#define CP_NV_FLAGS_1_MASK \ + (CP_NV_FLAGS_1_DISCARD_16_MASK | \ + CP_NV_FLAGS_1_END_RCVD_16_MASK | \ + CP_NV_FLAGS_1_DISCARD_17_MASK | \ + CP_NV_FLAGS_1_END_RCVD_17_MASK | \ + CP_NV_FLAGS_1_DISCARD_18_MASK | \ + CP_NV_FLAGS_1_END_RCVD_18_MASK | \ + CP_NV_FLAGS_1_DISCARD_19_MASK | \ + CP_NV_FLAGS_1_END_RCVD_19_MASK | \ + CP_NV_FLAGS_1_DISCARD_20_MASK | \ + CP_NV_FLAGS_1_END_RCVD_20_MASK | \ + CP_NV_FLAGS_1_DISCARD_21_MASK | \ + CP_NV_FLAGS_1_END_RCVD_21_MASK | \ + CP_NV_FLAGS_1_DISCARD_22_MASK | \ + CP_NV_FLAGS_1_END_RCVD_22_MASK | \ + CP_NV_FLAGS_1_DISCARD_23_MASK | \ + CP_NV_FLAGS_1_END_RCVD_23_MASK | \ + CP_NV_FLAGS_1_DISCARD_24_MASK | \ + CP_NV_FLAGS_1_END_RCVD_24_MASK | \ + CP_NV_FLAGS_1_DISCARD_25_MASK | \ + CP_NV_FLAGS_1_END_RCVD_25_MASK | \ + CP_NV_FLAGS_1_DISCARD_26_MASK | \ + CP_NV_FLAGS_1_END_RCVD_26_MASK | \ + CP_NV_FLAGS_1_DISCARD_27_MASK | \ + CP_NV_FLAGS_1_END_RCVD_27_MASK | \ + CP_NV_FLAGS_1_DISCARD_28_MASK | \ + CP_NV_FLAGS_1_END_RCVD_28_MASK | \ + CP_NV_FLAGS_1_DISCARD_29_MASK | \ + CP_NV_FLAGS_1_END_RCVD_29_MASK | \ + CP_NV_FLAGS_1_DISCARD_30_MASK | \ + CP_NV_FLAGS_1_END_RCVD_30_MASK | \ + CP_NV_FLAGS_1_DISCARD_31_MASK | \ + CP_NV_FLAGS_1_END_RCVD_31_MASK) + +#define CP_NV_FLAGS_1(discard_16, end_rcvd_16, discard_17, end_rcvd_17, discard_18, end_rcvd_18, discard_19, end_rcvd_19, discard_20, end_rcvd_20, discard_21, end_rcvd_21, discard_22, end_rcvd_22, discard_23, end_rcvd_23, discard_24, end_rcvd_24, discard_25, end_rcvd_25, discard_26, end_rcvd_26, discard_27, end_rcvd_27, discard_28, end_rcvd_28, discard_29, end_rcvd_29, discard_30, end_rcvd_30, discard_31, end_rcvd_31) \ + ((discard_16 << CP_NV_FLAGS_1_DISCARD_16_SHIFT) | \ + (end_rcvd_16 << CP_NV_FLAGS_1_END_RCVD_16_SHIFT) | \ + (discard_17 << CP_NV_FLAGS_1_DISCARD_17_SHIFT) | \ + (end_rcvd_17 << CP_NV_FLAGS_1_END_RCVD_17_SHIFT) | \ + (discard_18 << CP_NV_FLAGS_1_DISCARD_18_SHIFT) | \ + (end_rcvd_18 << CP_NV_FLAGS_1_END_RCVD_18_SHIFT) | \ + (discard_19 << CP_NV_FLAGS_1_DISCARD_19_SHIFT) | \ + (end_rcvd_19 << CP_NV_FLAGS_1_END_RCVD_19_SHIFT) | \ + (discard_20 << CP_NV_FLAGS_1_DISCARD_20_SHIFT) | \ + (end_rcvd_20 << CP_NV_FLAGS_1_END_RCVD_20_SHIFT) | \ + (discard_21 << CP_NV_FLAGS_1_DISCARD_21_SHIFT) | \ + (end_rcvd_21 << CP_NV_FLAGS_1_END_RCVD_21_SHIFT) | \ + (discard_22 << CP_NV_FLAGS_1_DISCARD_22_SHIFT) | \ + (end_rcvd_22 << CP_NV_FLAGS_1_END_RCVD_22_SHIFT) | \ + (discard_23 << CP_NV_FLAGS_1_DISCARD_23_SHIFT) | \ + (end_rcvd_23 << CP_NV_FLAGS_1_END_RCVD_23_SHIFT) | \ + (discard_24 << CP_NV_FLAGS_1_DISCARD_24_SHIFT) | \ + (end_rcvd_24 << CP_NV_FLAGS_1_END_RCVD_24_SHIFT) | \ + (discard_25 << CP_NV_FLAGS_1_DISCARD_25_SHIFT) | \ + (end_rcvd_25 << CP_NV_FLAGS_1_END_RCVD_25_SHIFT) | \ + (discard_26 << CP_NV_FLAGS_1_DISCARD_26_SHIFT) | \ + (end_rcvd_26 << CP_NV_FLAGS_1_END_RCVD_26_SHIFT) | \ + (discard_27 << CP_NV_FLAGS_1_DISCARD_27_SHIFT) | \ + (end_rcvd_27 << CP_NV_FLAGS_1_END_RCVD_27_SHIFT) | \ + (discard_28 << CP_NV_FLAGS_1_DISCARD_28_SHIFT) | \ + (end_rcvd_28 << CP_NV_FLAGS_1_END_RCVD_28_SHIFT) | \ + (discard_29 << CP_NV_FLAGS_1_DISCARD_29_SHIFT) | \ + (end_rcvd_29 << CP_NV_FLAGS_1_END_RCVD_29_SHIFT) | \ + (discard_30 << CP_NV_FLAGS_1_DISCARD_30_SHIFT) | \ + (end_rcvd_30 << CP_NV_FLAGS_1_END_RCVD_30_SHIFT) | \ + (discard_31 << CP_NV_FLAGS_1_DISCARD_31_SHIFT) | \ + (end_rcvd_31 << CP_NV_FLAGS_1_END_RCVD_31_SHIFT)) + +#define CP_NV_FLAGS_1_GET_DISCARD_16(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_16_MASK) >> CP_NV_FLAGS_1_DISCARD_16_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_16(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_16_MASK) >> CP_NV_FLAGS_1_END_RCVD_16_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_17(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_17_MASK) >> CP_NV_FLAGS_1_DISCARD_17_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_17(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_17_MASK) >> CP_NV_FLAGS_1_END_RCVD_17_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_18(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_18_MASK) >> CP_NV_FLAGS_1_DISCARD_18_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_18(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_18_MASK) >> CP_NV_FLAGS_1_END_RCVD_18_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_19(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_19_MASK) >> CP_NV_FLAGS_1_DISCARD_19_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_19(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_19_MASK) >> CP_NV_FLAGS_1_END_RCVD_19_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_20(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_20_MASK) >> CP_NV_FLAGS_1_DISCARD_20_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_20(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_20_MASK) >> CP_NV_FLAGS_1_END_RCVD_20_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_21(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_21_MASK) >> CP_NV_FLAGS_1_DISCARD_21_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_21(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_21_MASK) >> CP_NV_FLAGS_1_END_RCVD_21_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_22(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_22_MASK) >> CP_NV_FLAGS_1_DISCARD_22_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_22(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_22_MASK) >> CP_NV_FLAGS_1_END_RCVD_22_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_23(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_23_MASK) >> CP_NV_FLAGS_1_DISCARD_23_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_23(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_23_MASK) >> CP_NV_FLAGS_1_END_RCVD_23_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_24(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_24_MASK) >> CP_NV_FLAGS_1_DISCARD_24_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_24(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_24_MASK) >> CP_NV_FLAGS_1_END_RCVD_24_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_25(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_25_MASK) >> CP_NV_FLAGS_1_DISCARD_25_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_25(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_25_MASK) >> CP_NV_FLAGS_1_END_RCVD_25_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_26(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_26_MASK) >> CP_NV_FLAGS_1_DISCARD_26_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_26(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_26_MASK) >> CP_NV_FLAGS_1_END_RCVD_26_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_27(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_27_MASK) >> CP_NV_FLAGS_1_DISCARD_27_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_27(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_27_MASK) >> CP_NV_FLAGS_1_END_RCVD_27_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_28(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_28_MASK) >> CP_NV_FLAGS_1_DISCARD_28_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_28(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_28_MASK) >> CP_NV_FLAGS_1_END_RCVD_28_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_29(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_29_MASK) >> CP_NV_FLAGS_1_DISCARD_29_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_29(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_29_MASK) >> CP_NV_FLAGS_1_END_RCVD_29_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_30(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_30_MASK) >> CP_NV_FLAGS_1_DISCARD_30_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_30(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_30_MASK) >> CP_NV_FLAGS_1_END_RCVD_30_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_31(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_31_MASK) >> CP_NV_FLAGS_1_DISCARD_31_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_31(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_31_MASK) >> CP_NV_FLAGS_1_END_RCVD_31_SHIFT) + +#define CP_NV_FLAGS_1_SET_DISCARD_16(cp_nv_flags_1_reg, discard_16) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_16_MASK) | (discard_16 << CP_NV_FLAGS_1_DISCARD_16_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_16(cp_nv_flags_1_reg, end_rcvd_16) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_16_MASK) | (end_rcvd_16 << CP_NV_FLAGS_1_END_RCVD_16_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_17(cp_nv_flags_1_reg, discard_17) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_17_MASK) | (discard_17 << CP_NV_FLAGS_1_DISCARD_17_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_17(cp_nv_flags_1_reg, end_rcvd_17) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_17_MASK) | (end_rcvd_17 << CP_NV_FLAGS_1_END_RCVD_17_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_18(cp_nv_flags_1_reg, discard_18) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_18_MASK) | (discard_18 << CP_NV_FLAGS_1_DISCARD_18_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_18(cp_nv_flags_1_reg, end_rcvd_18) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_18_MASK) | (end_rcvd_18 << CP_NV_FLAGS_1_END_RCVD_18_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_19(cp_nv_flags_1_reg, discard_19) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_19_MASK) | (discard_19 << CP_NV_FLAGS_1_DISCARD_19_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_19(cp_nv_flags_1_reg, end_rcvd_19) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_19_MASK) | (end_rcvd_19 << CP_NV_FLAGS_1_END_RCVD_19_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_20(cp_nv_flags_1_reg, discard_20) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_20_MASK) | (discard_20 << CP_NV_FLAGS_1_DISCARD_20_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_20(cp_nv_flags_1_reg, end_rcvd_20) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_20_MASK) | (end_rcvd_20 << CP_NV_FLAGS_1_END_RCVD_20_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_21(cp_nv_flags_1_reg, discard_21) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_21_MASK) | (discard_21 << CP_NV_FLAGS_1_DISCARD_21_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_21(cp_nv_flags_1_reg, end_rcvd_21) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_21_MASK) | (end_rcvd_21 << CP_NV_FLAGS_1_END_RCVD_21_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_22(cp_nv_flags_1_reg, discard_22) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_22_MASK) | (discard_22 << CP_NV_FLAGS_1_DISCARD_22_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_22(cp_nv_flags_1_reg, end_rcvd_22) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_22_MASK) | (end_rcvd_22 << CP_NV_FLAGS_1_END_RCVD_22_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_23(cp_nv_flags_1_reg, discard_23) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_23_MASK) | (discard_23 << CP_NV_FLAGS_1_DISCARD_23_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_23(cp_nv_flags_1_reg, end_rcvd_23) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_23_MASK) | (end_rcvd_23 << CP_NV_FLAGS_1_END_RCVD_23_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_24(cp_nv_flags_1_reg, discard_24) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_24_MASK) | (discard_24 << CP_NV_FLAGS_1_DISCARD_24_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_24(cp_nv_flags_1_reg, end_rcvd_24) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_24_MASK) | (end_rcvd_24 << CP_NV_FLAGS_1_END_RCVD_24_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_25(cp_nv_flags_1_reg, discard_25) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_25_MASK) | (discard_25 << CP_NV_FLAGS_1_DISCARD_25_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_25(cp_nv_flags_1_reg, end_rcvd_25) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_25_MASK) | (end_rcvd_25 << CP_NV_FLAGS_1_END_RCVD_25_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_26(cp_nv_flags_1_reg, discard_26) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_26_MASK) | (discard_26 << CP_NV_FLAGS_1_DISCARD_26_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_26(cp_nv_flags_1_reg, end_rcvd_26) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_26_MASK) | (end_rcvd_26 << CP_NV_FLAGS_1_END_RCVD_26_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_27(cp_nv_flags_1_reg, discard_27) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_27_MASK) | (discard_27 << CP_NV_FLAGS_1_DISCARD_27_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_27(cp_nv_flags_1_reg, end_rcvd_27) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_27_MASK) | (end_rcvd_27 << CP_NV_FLAGS_1_END_RCVD_27_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_28(cp_nv_flags_1_reg, discard_28) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_28_MASK) | (discard_28 << CP_NV_FLAGS_1_DISCARD_28_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_28(cp_nv_flags_1_reg, end_rcvd_28) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_28_MASK) | (end_rcvd_28 << CP_NV_FLAGS_1_END_RCVD_28_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_29(cp_nv_flags_1_reg, discard_29) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_29_MASK) | (discard_29 << CP_NV_FLAGS_1_DISCARD_29_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_29(cp_nv_flags_1_reg, end_rcvd_29) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_29_MASK) | (end_rcvd_29 << CP_NV_FLAGS_1_END_RCVD_29_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_30(cp_nv_flags_1_reg, discard_30) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_30_MASK) | (discard_30 << CP_NV_FLAGS_1_DISCARD_30_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_30(cp_nv_flags_1_reg, end_rcvd_30) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_30_MASK) | (end_rcvd_30 << CP_NV_FLAGS_1_END_RCVD_30_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_31(cp_nv_flags_1_reg, discard_31) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_31_MASK) | (discard_31 << CP_NV_FLAGS_1_DISCARD_31_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_31(cp_nv_flags_1_reg, end_rcvd_31) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_31_MASK) | (end_rcvd_31 << CP_NV_FLAGS_1_END_RCVD_31_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_nv_flags_1_t { + unsigned int discard_16 : CP_NV_FLAGS_1_DISCARD_16_SIZE; + unsigned int end_rcvd_16 : CP_NV_FLAGS_1_END_RCVD_16_SIZE; + unsigned int discard_17 : CP_NV_FLAGS_1_DISCARD_17_SIZE; + unsigned int end_rcvd_17 : CP_NV_FLAGS_1_END_RCVD_17_SIZE; + unsigned int discard_18 : CP_NV_FLAGS_1_DISCARD_18_SIZE; + unsigned int end_rcvd_18 : CP_NV_FLAGS_1_END_RCVD_18_SIZE; + unsigned int discard_19 : CP_NV_FLAGS_1_DISCARD_19_SIZE; + unsigned int end_rcvd_19 : CP_NV_FLAGS_1_END_RCVD_19_SIZE; + unsigned int discard_20 : CP_NV_FLAGS_1_DISCARD_20_SIZE; + unsigned int end_rcvd_20 : CP_NV_FLAGS_1_END_RCVD_20_SIZE; + unsigned int discard_21 : CP_NV_FLAGS_1_DISCARD_21_SIZE; + unsigned int end_rcvd_21 : CP_NV_FLAGS_1_END_RCVD_21_SIZE; + unsigned int discard_22 : CP_NV_FLAGS_1_DISCARD_22_SIZE; + unsigned int end_rcvd_22 : CP_NV_FLAGS_1_END_RCVD_22_SIZE; + unsigned int discard_23 : CP_NV_FLAGS_1_DISCARD_23_SIZE; + unsigned int end_rcvd_23 : CP_NV_FLAGS_1_END_RCVD_23_SIZE; + unsigned int discard_24 : CP_NV_FLAGS_1_DISCARD_24_SIZE; + unsigned int end_rcvd_24 : CP_NV_FLAGS_1_END_RCVD_24_SIZE; + unsigned int discard_25 : CP_NV_FLAGS_1_DISCARD_25_SIZE; + unsigned int end_rcvd_25 : CP_NV_FLAGS_1_END_RCVD_25_SIZE; + unsigned int discard_26 : CP_NV_FLAGS_1_DISCARD_26_SIZE; + unsigned int end_rcvd_26 : CP_NV_FLAGS_1_END_RCVD_26_SIZE; + unsigned int discard_27 : CP_NV_FLAGS_1_DISCARD_27_SIZE; + unsigned int end_rcvd_27 : CP_NV_FLAGS_1_END_RCVD_27_SIZE; + unsigned int discard_28 : CP_NV_FLAGS_1_DISCARD_28_SIZE; + unsigned int end_rcvd_28 : CP_NV_FLAGS_1_END_RCVD_28_SIZE; + unsigned int discard_29 : CP_NV_FLAGS_1_DISCARD_29_SIZE; + unsigned int end_rcvd_29 : CP_NV_FLAGS_1_END_RCVD_29_SIZE; + unsigned int discard_30 : CP_NV_FLAGS_1_DISCARD_30_SIZE; + unsigned int end_rcvd_30 : CP_NV_FLAGS_1_END_RCVD_30_SIZE; + unsigned int discard_31 : CP_NV_FLAGS_1_DISCARD_31_SIZE; + unsigned int end_rcvd_31 : CP_NV_FLAGS_1_END_RCVD_31_SIZE; + } cp_nv_flags_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_nv_flags_1_t { + unsigned int end_rcvd_31 : CP_NV_FLAGS_1_END_RCVD_31_SIZE; + unsigned int discard_31 : CP_NV_FLAGS_1_DISCARD_31_SIZE; + unsigned int end_rcvd_30 : CP_NV_FLAGS_1_END_RCVD_30_SIZE; + unsigned int discard_30 : CP_NV_FLAGS_1_DISCARD_30_SIZE; + unsigned int end_rcvd_29 : CP_NV_FLAGS_1_END_RCVD_29_SIZE; + unsigned int discard_29 : CP_NV_FLAGS_1_DISCARD_29_SIZE; + unsigned int end_rcvd_28 : CP_NV_FLAGS_1_END_RCVD_28_SIZE; + unsigned int discard_28 : CP_NV_FLAGS_1_DISCARD_28_SIZE; + unsigned int end_rcvd_27 : CP_NV_FLAGS_1_END_RCVD_27_SIZE; + unsigned int discard_27 : CP_NV_FLAGS_1_DISCARD_27_SIZE; + unsigned int end_rcvd_26 : CP_NV_FLAGS_1_END_RCVD_26_SIZE; + unsigned int discard_26 : CP_NV_FLAGS_1_DISCARD_26_SIZE; + unsigned int end_rcvd_25 : CP_NV_FLAGS_1_END_RCVD_25_SIZE; + unsigned int discard_25 : CP_NV_FLAGS_1_DISCARD_25_SIZE; + unsigned int end_rcvd_24 : CP_NV_FLAGS_1_END_RCVD_24_SIZE; + unsigned int discard_24 : CP_NV_FLAGS_1_DISCARD_24_SIZE; + unsigned int end_rcvd_23 : CP_NV_FLAGS_1_END_RCVD_23_SIZE; + unsigned int discard_23 : CP_NV_FLAGS_1_DISCARD_23_SIZE; + unsigned int end_rcvd_22 : CP_NV_FLAGS_1_END_RCVD_22_SIZE; + unsigned int discard_22 : CP_NV_FLAGS_1_DISCARD_22_SIZE; + unsigned int end_rcvd_21 : CP_NV_FLAGS_1_END_RCVD_21_SIZE; + unsigned int discard_21 : CP_NV_FLAGS_1_DISCARD_21_SIZE; + unsigned int end_rcvd_20 : CP_NV_FLAGS_1_END_RCVD_20_SIZE; + unsigned int discard_20 : CP_NV_FLAGS_1_DISCARD_20_SIZE; + unsigned int end_rcvd_19 : CP_NV_FLAGS_1_END_RCVD_19_SIZE; + unsigned int discard_19 : CP_NV_FLAGS_1_DISCARD_19_SIZE; + unsigned int end_rcvd_18 : CP_NV_FLAGS_1_END_RCVD_18_SIZE; + unsigned int discard_18 : CP_NV_FLAGS_1_DISCARD_18_SIZE; + unsigned int end_rcvd_17 : CP_NV_FLAGS_1_END_RCVD_17_SIZE; + unsigned int discard_17 : CP_NV_FLAGS_1_DISCARD_17_SIZE; + unsigned int end_rcvd_16 : CP_NV_FLAGS_1_END_RCVD_16_SIZE; + unsigned int discard_16 : CP_NV_FLAGS_1_DISCARD_16_SIZE; + } cp_nv_flags_1_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_nv_flags_1_t f; +} cp_nv_flags_1_u; + + +/* + * CP_NV_FLAGS_2 struct + */ + +#define CP_NV_FLAGS_2_DISCARD_32_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_32_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_33_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_33_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_34_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_34_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_35_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_35_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_36_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_36_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_37_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_37_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_38_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_38_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_39_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_39_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_40_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_40_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_41_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_41_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_42_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_42_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_43_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_43_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_44_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_44_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_45_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_45_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_46_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_46_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_47_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_47_SIZE 1 + +#define CP_NV_FLAGS_2_DISCARD_32_SHIFT 0 +#define CP_NV_FLAGS_2_END_RCVD_32_SHIFT 1 +#define CP_NV_FLAGS_2_DISCARD_33_SHIFT 2 +#define CP_NV_FLAGS_2_END_RCVD_33_SHIFT 3 +#define CP_NV_FLAGS_2_DISCARD_34_SHIFT 4 +#define CP_NV_FLAGS_2_END_RCVD_34_SHIFT 5 +#define CP_NV_FLAGS_2_DISCARD_35_SHIFT 6 +#define CP_NV_FLAGS_2_END_RCVD_35_SHIFT 7 +#define CP_NV_FLAGS_2_DISCARD_36_SHIFT 8 +#define CP_NV_FLAGS_2_END_RCVD_36_SHIFT 9 +#define CP_NV_FLAGS_2_DISCARD_37_SHIFT 10 +#define CP_NV_FLAGS_2_END_RCVD_37_SHIFT 11 +#define CP_NV_FLAGS_2_DISCARD_38_SHIFT 12 +#define CP_NV_FLAGS_2_END_RCVD_38_SHIFT 13 +#define CP_NV_FLAGS_2_DISCARD_39_SHIFT 14 +#define CP_NV_FLAGS_2_END_RCVD_39_SHIFT 15 +#define CP_NV_FLAGS_2_DISCARD_40_SHIFT 16 +#define CP_NV_FLAGS_2_END_RCVD_40_SHIFT 17 +#define CP_NV_FLAGS_2_DISCARD_41_SHIFT 18 +#define CP_NV_FLAGS_2_END_RCVD_41_SHIFT 19 +#define CP_NV_FLAGS_2_DISCARD_42_SHIFT 20 +#define CP_NV_FLAGS_2_END_RCVD_42_SHIFT 21 +#define CP_NV_FLAGS_2_DISCARD_43_SHIFT 22 +#define CP_NV_FLAGS_2_END_RCVD_43_SHIFT 23 +#define CP_NV_FLAGS_2_DISCARD_44_SHIFT 24 +#define CP_NV_FLAGS_2_END_RCVD_44_SHIFT 25 +#define CP_NV_FLAGS_2_DISCARD_45_SHIFT 26 +#define CP_NV_FLAGS_2_END_RCVD_45_SHIFT 27 +#define CP_NV_FLAGS_2_DISCARD_46_SHIFT 28 +#define CP_NV_FLAGS_2_END_RCVD_46_SHIFT 29 +#define CP_NV_FLAGS_2_DISCARD_47_SHIFT 30 +#define CP_NV_FLAGS_2_END_RCVD_47_SHIFT 31 + +#define CP_NV_FLAGS_2_DISCARD_32_MASK 0x00000001 +#define CP_NV_FLAGS_2_END_RCVD_32_MASK 0x00000002 +#define CP_NV_FLAGS_2_DISCARD_33_MASK 0x00000004 +#define CP_NV_FLAGS_2_END_RCVD_33_MASK 0x00000008 +#define CP_NV_FLAGS_2_DISCARD_34_MASK 0x00000010 +#define CP_NV_FLAGS_2_END_RCVD_34_MASK 0x00000020 +#define CP_NV_FLAGS_2_DISCARD_35_MASK 0x00000040 +#define CP_NV_FLAGS_2_END_RCVD_35_MASK 0x00000080 +#define CP_NV_FLAGS_2_DISCARD_36_MASK 0x00000100 +#define CP_NV_FLAGS_2_END_RCVD_36_MASK 0x00000200 +#define CP_NV_FLAGS_2_DISCARD_37_MASK 0x00000400 +#define CP_NV_FLAGS_2_END_RCVD_37_MASK 0x00000800 +#define CP_NV_FLAGS_2_DISCARD_38_MASK 0x00001000 +#define CP_NV_FLAGS_2_END_RCVD_38_MASK 0x00002000 +#define CP_NV_FLAGS_2_DISCARD_39_MASK 0x00004000 +#define CP_NV_FLAGS_2_END_RCVD_39_MASK 0x00008000 +#define CP_NV_FLAGS_2_DISCARD_40_MASK 0x00010000 +#define CP_NV_FLAGS_2_END_RCVD_40_MASK 0x00020000 +#define CP_NV_FLAGS_2_DISCARD_41_MASK 0x00040000 +#define CP_NV_FLAGS_2_END_RCVD_41_MASK 0x00080000 +#define CP_NV_FLAGS_2_DISCARD_42_MASK 0x00100000 +#define CP_NV_FLAGS_2_END_RCVD_42_MASK 0x00200000 +#define CP_NV_FLAGS_2_DISCARD_43_MASK 0x00400000 +#define CP_NV_FLAGS_2_END_RCVD_43_MASK 0x00800000 +#define CP_NV_FLAGS_2_DISCARD_44_MASK 0x01000000 +#define CP_NV_FLAGS_2_END_RCVD_44_MASK 0x02000000 +#define CP_NV_FLAGS_2_DISCARD_45_MASK 0x04000000 +#define CP_NV_FLAGS_2_END_RCVD_45_MASK 0x08000000 +#define CP_NV_FLAGS_2_DISCARD_46_MASK 0x10000000 +#define CP_NV_FLAGS_2_END_RCVD_46_MASK 0x20000000 +#define CP_NV_FLAGS_2_DISCARD_47_MASK 0x40000000 +#define CP_NV_FLAGS_2_END_RCVD_47_MASK 0x80000000 + +#define CP_NV_FLAGS_2_MASK \ + (CP_NV_FLAGS_2_DISCARD_32_MASK | \ + CP_NV_FLAGS_2_END_RCVD_32_MASK | \ + CP_NV_FLAGS_2_DISCARD_33_MASK | \ + CP_NV_FLAGS_2_END_RCVD_33_MASK | \ + CP_NV_FLAGS_2_DISCARD_34_MASK | \ + CP_NV_FLAGS_2_END_RCVD_34_MASK | \ + CP_NV_FLAGS_2_DISCARD_35_MASK | \ + CP_NV_FLAGS_2_END_RCVD_35_MASK | \ + CP_NV_FLAGS_2_DISCARD_36_MASK | \ + CP_NV_FLAGS_2_END_RCVD_36_MASK | \ + CP_NV_FLAGS_2_DISCARD_37_MASK | \ + CP_NV_FLAGS_2_END_RCVD_37_MASK | \ + CP_NV_FLAGS_2_DISCARD_38_MASK | \ + CP_NV_FLAGS_2_END_RCVD_38_MASK | \ + CP_NV_FLAGS_2_DISCARD_39_MASK | \ + CP_NV_FLAGS_2_END_RCVD_39_MASK | \ + CP_NV_FLAGS_2_DISCARD_40_MASK | \ + CP_NV_FLAGS_2_END_RCVD_40_MASK | \ + CP_NV_FLAGS_2_DISCARD_41_MASK | \ + CP_NV_FLAGS_2_END_RCVD_41_MASK | \ + CP_NV_FLAGS_2_DISCARD_42_MASK | \ + CP_NV_FLAGS_2_END_RCVD_42_MASK | \ + CP_NV_FLAGS_2_DISCARD_43_MASK | \ + CP_NV_FLAGS_2_END_RCVD_43_MASK | \ + CP_NV_FLAGS_2_DISCARD_44_MASK | \ + CP_NV_FLAGS_2_END_RCVD_44_MASK | \ + CP_NV_FLAGS_2_DISCARD_45_MASK | \ + CP_NV_FLAGS_2_END_RCVD_45_MASK | \ + CP_NV_FLAGS_2_DISCARD_46_MASK | \ + CP_NV_FLAGS_2_END_RCVD_46_MASK | \ + CP_NV_FLAGS_2_DISCARD_47_MASK | \ + CP_NV_FLAGS_2_END_RCVD_47_MASK) + +#define CP_NV_FLAGS_2(discard_32, end_rcvd_32, discard_33, end_rcvd_33, discard_34, end_rcvd_34, discard_35, end_rcvd_35, discard_36, end_rcvd_36, discard_37, end_rcvd_37, discard_38, end_rcvd_38, discard_39, end_rcvd_39, discard_40, end_rcvd_40, discard_41, end_rcvd_41, discard_42, end_rcvd_42, discard_43, end_rcvd_43, discard_44, end_rcvd_44, discard_45, end_rcvd_45, discard_46, end_rcvd_46, discard_47, end_rcvd_47) \ + ((discard_32 << CP_NV_FLAGS_2_DISCARD_32_SHIFT) | \ + (end_rcvd_32 << CP_NV_FLAGS_2_END_RCVD_32_SHIFT) | \ + (discard_33 << CP_NV_FLAGS_2_DISCARD_33_SHIFT) | \ + (end_rcvd_33 << CP_NV_FLAGS_2_END_RCVD_33_SHIFT) | \ + (discard_34 << CP_NV_FLAGS_2_DISCARD_34_SHIFT) | \ + (end_rcvd_34 << CP_NV_FLAGS_2_END_RCVD_34_SHIFT) | \ + (discard_35 << CP_NV_FLAGS_2_DISCARD_35_SHIFT) | \ + (end_rcvd_35 << CP_NV_FLAGS_2_END_RCVD_35_SHIFT) | \ + (discard_36 << CP_NV_FLAGS_2_DISCARD_36_SHIFT) | \ + (end_rcvd_36 << CP_NV_FLAGS_2_END_RCVD_36_SHIFT) | \ + (discard_37 << CP_NV_FLAGS_2_DISCARD_37_SHIFT) | \ + (end_rcvd_37 << CP_NV_FLAGS_2_END_RCVD_37_SHIFT) | \ + (discard_38 << CP_NV_FLAGS_2_DISCARD_38_SHIFT) | \ + (end_rcvd_38 << CP_NV_FLAGS_2_END_RCVD_38_SHIFT) | \ + (discard_39 << CP_NV_FLAGS_2_DISCARD_39_SHIFT) | \ + (end_rcvd_39 << CP_NV_FLAGS_2_END_RCVD_39_SHIFT) | \ + (discard_40 << CP_NV_FLAGS_2_DISCARD_40_SHIFT) | \ + (end_rcvd_40 << CP_NV_FLAGS_2_END_RCVD_40_SHIFT) | \ + (discard_41 << CP_NV_FLAGS_2_DISCARD_41_SHIFT) | \ + (end_rcvd_41 << CP_NV_FLAGS_2_END_RCVD_41_SHIFT) | \ + (discard_42 << CP_NV_FLAGS_2_DISCARD_42_SHIFT) | \ + (end_rcvd_42 << CP_NV_FLAGS_2_END_RCVD_42_SHIFT) | \ + (discard_43 << CP_NV_FLAGS_2_DISCARD_43_SHIFT) | \ + (end_rcvd_43 << CP_NV_FLAGS_2_END_RCVD_43_SHIFT) | \ + (discard_44 << CP_NV_FLAGS_2_DISCARD_44_SHIFT) | \ + (end_rcvd_44 << CP_NV_FLAGS_2_END_RCVD_44_SHIFT) | \ + (discard_45 << CP_NV_FLAGS_2_DISCARD_45_SHIFT) | \ + (end_rcvd_45 << CP_NV_FLAGS_2_END_RCVD_45_SHIFT) | \ + (discard_46 << CP_NV_FLAGS_2_DISCARD_46_SHIFT) | \ + (end_rcvd_46 << CP_NV_FLAGS_2_END_RCVD_46_SHIFT) | \ + (discard_47 << CP_NV_FLAGS_2_DISCARD_47_SHIFT) | \ + (end_rcvd_47 << CP_NV_FLAGS_2_END_RCVD_47_SHIFT)) + +#define CP_NV_FLAGS_2_GET_DISCARD_32(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_32_MASK) >> CP_NV_FLAGS_2_DISCARD_32_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_32(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_32_MASK) >> CP_NV_FLAGS_2_END_RCVD_32_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_33(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_33_MASK) >> CP_NV_FLAGS_2_DISCARD_33_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_33(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_33_MASK) >> CP_NV_FLAGS_2_END_RCVD_33_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_34(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_34_MASK) >> CP_NV_FLAGS_2_DISCARD_34_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_34(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_34_MASK) >> CP_NV_FLAGS_2_END_RCVD_34_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_35(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_35_MASK) >> CP_NV_FLAGS_2_DISCARD_35_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_35(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_35_MASK) >> CP_NV_FLAGS_2_END_RCVD_35_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_36(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_36_MASK) >> CP_NV_FLAGS_2_DISCARD_36_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_36(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_36_MASK) >> CP_NV_FLAGS_2_END_RCVD_36_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_37(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_37_MASK) >> CP_NV_FLAGS_2_DISCARD_37_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_37(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_37_MASK) >> CP_NV_FLAGS_2_END_RCVD_37_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_38(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_38_MASK) >> CP_NV_FLAGS_2_DISCARD_38_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_38(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_38_MASK) >> CP_NV_FLAGS_2_END_RCVD_38_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_39(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_39_MASK) >> CP_NV_FLAGS_2_DISCARD_39_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_39(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_39_MASK) >> CP_NV_FLAGS_2_END_RCVD_39_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_40(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_40_MASK) >> CP_NV_FLAGS_2_DISCARD_40_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_40(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_40_MASK) >> CP_NV_FLAGS_2_END_RCVD_40_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_41(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_41_MASK) >> CP_NV_FLAGS_2_DISCARD_41_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_41(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_41_MASK) >> CP_NV_FLAGS_2_END_RCVD_41_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_42(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_42_MASK) >> CP_NV_FLAGS_2_DISCARD_42_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_42(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_42_MASK) >> CP_NV_FLAGS_2_END_RCVD_42_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_43(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_43_MASK) >> CP_NV_FLAGS_2_DISCARD_43_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_43(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_43_MASK) >> CP_NV_FLAGS_2_END_RCVD_43_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_44(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_44_MASK) >> CP_NV_FLAGS_2_DISCARD_44_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_44(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_44_MASK) >> CP_NV_FLAGS_2_END_RCVD_44_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_45(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_45_MASK) >> CP_NV_FLAGS_2_DISCARD_45_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_45(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_45_MASK) >> CP_NV_FLAGS_2_END_RCVD_45_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_46(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_46_MASK) >> CP_NV_FLAGS_2_DISCARD_46_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_46(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_46_MASK) >> CP_NV_FLAGS_2_END_RCVD_46_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_47(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_47_MASK) >> CP_NV_FLAGS_2_DISCARD_47_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_47(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_47_MASK) >> CP_NV_FLAGS_2_END_RCVD_47_SHIFT) + +#define CP_NV_FLAGS_2_SET_DISCARD_32(cp_nv_flags_2_reg, discard_32) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_32_MASK) | (discard_32 << CP_NV_FLAGS_2_DISCARD_32_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_32(cp_nv_flags_2_reg, end_rcvd_32) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_32_MASK) | (end_rcvd_32 << CP_NV_FLAGS_2_END_RCVD_32_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_33(cp_nv_flags_2_reg, discard_33) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_33_MASK) | (discard_33 << CP_NV_FLAGS_2_DISCARD_33_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_33(cp_nv_flags_2_reg, end_rcvd_33) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_33_MASK) | (end_rcvd_33 << CP_NV_FLAGS_2_END_RCVD_33_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_34(cp_nv_flags_2_reg, discard_34) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_34_MASK) | (discard_34 << CP_NV_FLAGS_2_DISCARD_34_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_34(cp_nv_flags_2_reg, end_rcvd_34) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_34_MASK) | (end_rcvd_34 << CP_NV_FLAGS_2_END_RCVD_34_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_35(cp_nv_flags_2_reg, discard_35) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_35_MASK) | (discard_35 << CP_NV_FLAGS_2_DISCARD_35_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_35(cp_nv_flags_2_reg, end_rcvd_35) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_35_MASK) | (end_rcvd_35 << CP_NV_FLAGS_2_END_RCVD_35_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_36(cp_nv_flags_2_reg, discard_36) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_36_MASK) | (discard_36 << CP_NV_FLAGS_2_DISCARD_36_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_36(cp_nv_flags_2_reg, end_rcvd_36) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_36_MASK) | (end_rcvd_36 << CP_NV_FLAGS_2_END_RCVD_36_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_37(cp_nv_flags_2_reg, discard_37) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_37_MASK) | (discard_37 << CP_NV_FLAGS_2_DISCARD_37_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_37(cp_nv_flags_2_reg, end_rcvd_37) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_37_MASK) | (end_rcvd_37 << CP_NV_FLAGS_2_END_RCVD_37_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_38(cp_nv_flags_2_reg, discard_38) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_38_MASK) | (discard_38 << CP_NV_FLAGS_2_DISCARD_38_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_38(cp_nv_flags_2_reg, end_rcvd_38) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_38_MASK) | (end_rcvd_38 << CP_NV_FLAGS_2_END_RCVD_38_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_39(cp_nv_flags_2_reg, discard_39) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_39_MASK) | (discard_39 << CP_NV_FLAGS_2_DISCARD_39_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_39(cp_nv_flags_2_reg, end_rcvd_39) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_39_MASK) | (end_rcvd_39 << CP_NV_FLAGS_2_END_RCVD_39_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_40(cp_nv_flags_2_reg, discard_40) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_40_MASK) | (discard_40 << CP_NV_FLAGS_2_DISCARD_40_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_40(cp_nv_flags_2_reg, end_rcvd_40) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_40_MASK) | (end_rcvd_40 << CP_NV_FLAGS_2_END_RCVD_40_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_41(cp_nv_flags_2_reg, discard_41) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_41_MASK) | (discard_41 << CP_NV_FLAGS_2_DISCARD_41_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_41(cp_nv_flags_2_reg, end_rcvd_41) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_41_MASK) | (end_rcvd_41 << CP_NV_FLAGS_2_END_RCVD_41_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_42(cp_nv_flags_2_reg, discard_42) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_42_MASK) | (discard_42 << CP_NV_FLAGS_2_DISCARD_42_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_42(cp_nv_flags_2_reg, end_rcvd_42) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_42_MASK) | (end_rcvd_42 << CP_NV_FLAGS_2_END_RCVD_42_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_43(cp_nv_flags_2_reg, discard_43) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_43_MASK) | (discard_43 << CP_NV_FLAGS_2_DISCARD_43_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_43(cp_nv_flags_2_reg, end_rcvd_43) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_43_MASK) | (end_rcvd_43 << CP_NV_FLAGS_2_END_RCVD_43_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_44(cp_nv_flags_2_reg, discard_44) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_44_MASK) | (discard_44 << CP_NV_FLAGS_2_DISCARD_44_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_44(cp_nv_flags_2_reg, end_rcvd_44) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_44_MASK) | (end_rcvd_44 << CP_NV_FLAGS_2_END_RCVD_44_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_45(cp_nv_flags_2_reg, discard_45) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_45_MASK) | (discard_45 << CP_NV_FLAGS_2_DISCARD_45_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_45(cp_nv_flags_2_reg, end_rcvd_45) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_45_MASK) | (end_rcvd_45 << CP_NV_FLAGS_2_END_RCVD_45_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_46(cp_nv_flags_2_reg, discard_46) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_46_MASK) | (discard_46 << CP_NV_FLAGS_2_DISCARD_46_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_46(cp_nv_flags_2_reg, end_rcvd_46) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_46_MASK) | (end_rcvd_46 << CP_NV_FLAGS_2_END_RCVD_46_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_47(cp_nv_flags_2_reg, discard_47) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_47_MASK) | (discard_47 << CP_NV_FLAGS_2_DISCARD_47_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_47(cp_nv_flags_2_reg, end_rcvd_47) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_47_MASK) | (end_rcvd_47 << CP_NV_FLAGS_2_END_RCVD_47_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_nv_flags_2_t { + unsigned int discard_32 : CP_NV_FLAGS_2_DISCARD_32_SIZE; + unsigned int end_rcvd_32 : CP_NV_FLAGS_2_END_RCVD_32_SIZE; + unsigned int discard_33 : CP_NV_FLAGS_2_DISCARD_33_SIZE; + unsigned int end_rcvd_33 : CP_NV_FLAGS_2_END_RCVD_33_SIZE; + unsigned int discard_34 : CP_NV_FLAGS_2_DISCARD_34_SIZE; + unsigned int end_rcvd_34 : CP_NV_FLAGS_2_END_RCVD_34_SIZE; + unsigned int discard_35 : CP_NV_FLAGS_2_DISCARD_35_SIZE; + unsigned int end_rcvd_35 : CP_NV_FLAGS_2_END_RCVD_35_SIZE; + unsigned int discard_36 : CP_NV_FLAGS_2_DISCARD_36_SIZE; + unsigned int end_rcvd_36 : CP_NV_FLAGS_2_END_RCVD_36_SIZE; + unsigned int discard_37 : CP_NV_FLAGS_2_DISCARD_37_SIZE; + unsigned int end_rcvd_37 : CP_NV_FLAGS_2_END_RCVD_37_SIZE; + unsigned int discard_38 : CP_NV_FLAGS_2_DISCARD_38_SIZE; + unsigned int end_rcvd_38 : CP_NV_FLAGS_2_END_RCVD_38_SIZE; + unsigned int discard_39 : CP_NV_FLAGS_2_DISCARD_39_SIZE; + unsigned int end_rcvd_39 : CP_NV_FLAGS_2_END_RCVD_39_SIZE; + unsigned int discard_40 : CP_NV_FLAGS_2_DISCARD_40_SIZE; + unsigned int end_rcvd_40 : CP_NV_FLAGS_2_END_RCVD_40_SIZE; + unsigned int discard_41 : CP_NV_FLAGS_2_DISCARD_41_SIZE; + unsigned int end_rcvd_41 : CP_NV_FLAGS_2_END_RCVD_41_SIZE; + unsigned int discard_42 : CP_NV_FLAGS_2_DISCARD_42_SIZE; + unsigned int end_rcvd_42 : CP_NV_FLAGS_2_END_RCVD_42_SIZE; + unsigned int discard_43 : CP_NV_FLAGS_2_DISCARD_43_SIZE; + unsigned int end_rcvd_43 : CP_NV_FLAGS_2_END_RCVD_43_SIZE; + unsigned int discard_44 : CP_NV_FLAGS_2_DISCARD_44_SIZE; + unsigned int end_rcvd_44 : CP_NV_FLAGS_2_END_RCVD_44_SIZE; + unsigned int discard_45 : CP_NV_FLAGS_2_DISCARD_45_SIZE; + unsigned int end_rcvd_45 : CP_NV_FLAGS_2_END_RCVD_45_SIZE; + unsigned int discard_46 : CP_NV_FLAGS_2_DISCARD_46_SIZE; + unsigned int end_rcvd_46 : CP_NV_FLAGS_2_END_RCVD_46_SIZE; + unsigned int discard_47 : CP_NV_FLAGS_2_DISCARD_47_SIZE; + unsigned int end_rcvd_47 : CP_NV_FLAGS_2_END_RCVD_47_SIZE; + } cp_nv_flags_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_nv_flags_2_t { + unsigned int end_rcvd_47 : CP_NV_FLAGS_2_END_RCVD_47_SIZE; + unsigned int discard_47 : CP_NV_FLAGS_2_DISCARD_47_SIZE; + unsigned int end_rcvd_46 : CP_NV_FLAGS_2_END_RCVD_46_SIZE; + unsigned int discard_46 : CP_NV_FLAGS_2_DISCARD_46_SIZE; + unsigned int end_rcvd_45 : CP_NV_FLAGS_2_END_RCVD_45_SIZE; + unsigned int discard_45 : CP_NV_FLAGS_2_DISCARD_45_SIZE; + unsigned int end_rcvd_44 : CP_NV_FLAGS_2_END_RCVD_44_SIZE; + unsigned int discard_44 : CP_NV_FLAGS_2_DISCARD_44_SIZE; + unsigned int end_rcvd_43 : CP_NV_FLAGS_2_END_RCVD_43_SIZE; + unsigned int discard_43 : CP_NV_FLAGS_2_DISCARD_43_SIZE; + unsigned int end_rcvd_42 : CP_NV_FLAGS_2_END_RCVD_42_SIZE; + unsigned int discard_42 : CP_NV_FLAGS_2_DISCARD_42_SIZE; + unsigned int end_rcvd_41 : CP_NV_FLAGS_2_END_RCVD_41_SIZE; + unsigned int discard_41 : CP_NV_FLAGS_2_DISCARD_41_SIZE; + unsigned int end_rcvd_40 : CP_NV_FLAGS_2_END_RCVD_40_SIZE; + unsigned int discard_40 : CP_NV_FLAGS_2_DISCARD_40_SIZE; + unsigned int end_rcvd_39 : CP_NV_FLAGS_2_END_RCVD_39_SIZE; + unsigned int discard_39 : CP_NV_FLAGS_2_DISCARD_39_SIZE; + unsigned int end_rcvd_38 : CP_NV_FLAGS_2_END_RCVD_38_SIZE; + unsigned int discard_38 : CP_NV_FLAGS_2_DISCARD_38_SIZE; + unsigned int end_rcvd_37 : CP_NV_FLAGS_2_END_RCVD_37_SIZE; + unsigned int discard_37 : CP_NV_FLAGS_2_DISCARD_37_SIZE; + unsigned int end_rcvd_36 : CP_NV_FLAGS_2_END_RCVD_36_SIZE; + unsigned int discard_36 : CP_NV_FLAGS_2_DISCARD_36_SIZE; + unsigned int end_rcvd_35 : CP_NV_FLAGS_2_END_RCVD_35_SIZE; + unsigned int discard_35 : CP_NV_FLAGS_2_DISCARD_35_SIZE; + unsigned int end_rcvd_34 : CP_NV_FLAGS_2_END_RCVD_34_SIZE; + unsigned int discard_34 : CP_NV_FLAGS_2_DISCARD_34_SIZE; + unsigned int end_rcvd_33 : CP_NV_FLAGS_2_END_RCVD_33_SIZE; + unsigned int discard_33 : CP_NV_FLAGS_2_DISCARD_33_SIZE; + unsigned int end_rcvd_32 : CP_NV_FLAGS_2_END_RCVD_32_SIZE; + unsigned int discard_32 : CP_NV_FLAGS_2_DISCARD_32_SIZE; + } cp_nv_flags_2_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_nv_flags_2_t f; +} cp_nv_flags_2_u; + + +/* + * CP_NV_FLAGS_3 struct + */ + +#define CP_NV_FLAGS_3_DISCARD_48_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_48_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_49_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_49_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_50_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_50_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_51_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_51_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_52_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_52_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_53_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_53_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_54_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_54_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_55_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_55_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_56_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_56_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_57_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_57_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_58_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_58_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_59_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_59_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_60_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_60_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_61_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_61_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_62_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_62_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_63_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_63_SIZE 1 + +#define CP_NV_FLAGS_3_DISCARD_48_SHIFT 0 +#define CP_NV_FLAGS_3_END_RCVD_48_SHIFT 1 +#define CP_NV_FLAGS_3_DISCARD_49_SHIFT 2 +#define CP_NV_FLAGS_3_END_RCVD_49_SHIFT 3 +#define CP_NV_FLAGS_3_DISCARD_50_SHIFT 4 +#define CP_NV_FLAGS_3_END_RCVD_50_SHIFT 5 +#define CP_NV_FLAGS_3_DISCARD_51_SHIFT 6 +#define CP_NV_FLAGS_3_END_RCVD_51_SHIFT 7 +#define CP_NV_FLAGS_3_DISCARD_52_SHIFT 8 +#define CP_NV_FLAGS_3_END_RCVD_52_SHIFT 9 +#define CP_NV_FLAGS_3_DISCARD_53_SHIFT 10 +#define CP_NV_FLAGS_3_END_RCVD_53_SHIFT 11 +#define CP_NV_FLAGS_3_DISCARD_54_SHIFT 12 +#define CP_NV_FLAGS_3_END_RCVD_54_SHIFT 13 +#define CP_NV_FLAGS_3_DISCARD_55_SHIFT 14 +#define CP_NV_FLAGS_3_END_RCVD_55_SHIFT 15 +#define CP_NV_FLAGS_3_DISCARD_56_SHIFT 16 +#define CP_NV_FLAGS_3_END_RCVD_56_SHIFT 17 +#define CP_NV_FLAGS_3_DISCARD_57_SHIFT 18 +#define CP_NV_FLAGS_3_END_RCVD_57_SHIFT 19 +#define CP_NV_FLAGS_3_DISCARD_58_SHIFT 20 +#define CP_NV_FLAGS_3_END_RCVD_58_SHIFT 21 +#define CP_NV_FLAGS_3_DISCARD_59_SHIFT 22 +#define CP_NV_FLAGS_3_END_RCVD_59_SHIFT 23 +#define CP_NV_FLAGS_3_DISCARD_60_SHIFT 24 +#define CP_NV_FLAGS_3_END_RCVD_60_SHIFT 25 +#define CP_NV_FLAGS_3_DISCARD_61_SHIFT 26 +#define CP_NV_FLAGS_3_END_RCVD_61_SHIFT 27 +#define CP_NV_FLAGS_3_DISCARD_62_SHIFT 28 +#define CP_NV_FLAGS_3_END_RCVD_62_SHIFT 29 +#define CP_NV_FLAGS_3_DISCARD_63_SHIFT 30 +#define CP_NV_FLAGS_3_END_RCVD_63_SHIFT 31 + +#define CP_NV_FLAGS_3_DISCARD_48_MASK 0x00000001 +#define CP_NV_FLAGS_3_END_RCVD_48_MASK 0x00000002 +#define CP_NV_FLAGS_3_DISCARD_49_MASK 0x00000004 +#define CP_NV_FLAGS_3_END_RCVD_49_MASK 0x00000008 +#define CP_NV_FLAGS_3_DISCARD_50_MASK 0x00000010 +#define CP_NV_FLAGS_3_END_RCVD_50_MASK 0x00000020 +#define CP_NV_FLAGS_3_DISCARD_51_MASK 0x00000040 +#define CP_NV_FLAGS_3_END_RCVD_51_MASK 0x00000080 +#define CP_NV_FLAGS_3_DISCARD_52_MASK 0x00000100 +#define CP_NV_FLAGS_3_END_RCVD_52_MASK 0x00000200 +#define CP_NV_FLAGS_3_DISCARD_53_MASK 0x00000400 +#define CP_NV_FLAGS_3_END_RCVD_53_MASK 0x00000800 +#define CP_NV_FLAGS_3_DISCARD_54_MASK 0x00001000 +#define CP_NV_FLAGS_3_END_RCVD_54_MASK 0x00002000 +#define CP_NV_FLAGS_3_DISCARD_55_MASK 0x00004000 +#define CP_NV_FLAGS_3_END_RCVD_55_MASK 0x00008000 +#define CP_NV_FLAGS_3_DISCARD_56_MASK 0x00010000 +#define CP_NV_FLAGS_3_END_RCVD_56_MASK 0x00020000 +#define CP_NV_FLAGS_3_DISCARD_57_MASK 0x00040000 +#define CP_NV_FLAGS_3_END_RCVD_57_MASK 0x00080000 +#define CP_NV_FLAGS_3_DISCARD_58_MASK 0x00100000 +#define CP_NV_FLAGS_3_END_RCVD_58_MASK 0x00200000 +#define CP_NV_FLAGS_3_DISCARD_59_MASK 0x00400000 +#define CP_NV_FLAGS_3_END_RCVD_59_MASK 0x00800000 +#define CP_NV_FLAGS_3_DISCARD_60_MASK 0x01000000 +#define CP_NV_FLAGS_3_END_RCVD_60_MASK 0x02000000 +#define CP_NV_FLAGS_3_DISCARD_61_MASK 0x04000000 +#define CP_NV_FLAGS_3_END_RCVD_61_MASK 0x08000000 +#define CP_NV_FLAGS_3_DISCARD_62_MASK 0x10000000 +#define CP_NV_FLAGS_3_END_RCVD_62_MASK 0x20000000 +#define CP_NV_FLAGS_3_DISCARD_63_MASK 0x40000000 +#define CP_NV_FLAGS_3_END_RCVD_63_MASK 0x80000000 + +#define CP_NV_FLAGS_3_MASK \ + (CP_NV_FLAGS_3_DISCARD_48_MASK | \ + CP_NV_FLAGS_3_END_RCVD_48_MASK | \ + CP_NV_FLAGS_3_DISCARD_49_MASK | \ + CP_NV_FLAGS_3_END_RCVD_49_MASK | \ + CP_NV_FLAGS_3_DISCARD_50_MASK | \ + CP_NV_FLAGS_3_END_RCVD_50_MASK | \ + CP_NV_FLAGS_3_DISCARD_51_MASK | \ + CP_NV_FLAGS_3_END_RCVD_51_MASK | \ + CP_NV_FLAGS_3_DISCARD_52_MASK | \ + CP_NV_FLAGS_3_END_RCVD_52_MASK | \ + CP_NV_FLAGS_3_DISCARD_53_MASK | \ + CP_NV_FLAGS_3_END_RCVD_53_MASK | \ + CP_NV_FLAGS_3_DISCARD_54_MASK | \ + CP_NV_FLAGS_3_END_RCVD_54_MASK | \ + CP_NV_FLAGS_3_DISCARD_55_MASK | \ + CP_NV_FLAGS_3_END_RCVD_55_MASK | \ + CP_NV_FLAGS_3_DISCARD_56_MASK | \ + CP_NV_FLAGS_3_END_RCVD_56_MASK | \ + CP_NV_FLAGS_3_DISCARD_57_MASK | \ + CP_NV_FLAGS_3_END_RCVD_57_MASK | \ + CP_NV_FLAGS_3_DISCARD_58_MASK | \ + CP_NV_FLAGS_3_END_RCVD_58_MASK | \ + CP_NV_FLAGS_3_DISCARD_59_MASK | \ + CP_NV_FLAGS_3_END_RCVD_59_MASK | \ + CP_NV_FLAGS_3_DISCARD_60_MASK | \ + CP_NV_FLAGS_3_END_RCVD_60_MASK | \ + CP_NV_FLAGS_3_DISCARD_61_MASK | \ + CP_NV_FLAGS_3_END_RCVD_61_MASK | \ + CP_NV_FLAGS_3_DISCARD_62_MASK | \ + CP_NV_FLAGS_3_END_RCVD_62_MASK | \ + CP_NV_FLAGS_3_DISCARD_63_MASK | \ + CP_NV_FLAGS_3_END_RCVD_63_MASK) + +#define CP_NV_FLAGS_3(discard_48, end_rcvd_48, discard_49, end_rcvd_49, discard_50, end_rcvd_50, discard_51, end_rcvd_51, discard_52, end_rcvd_52, discard_53, end_rcvd_53, discard_54, end_rcvd_54, discard_55, end_rcvd_55, discard_56, end_rcvd_56, discard_57, end_rcvd_57, discard_58, end_rcvd_58, discard_59, end_rcvd_59, discard_60, end_rcvd_60, discard_61, end_rcvd_61, discard_62, end_rcvd_62, discard_63, end_rcvd_63) \ + ((discard_48 << CP_NV_FLAGS_3_DISCARD_48_SHIFT) | \ + (end_rcvd_48 << CP_NV_FLAGS_3_END_RCVD_48_SHIFT) | \ + (discard_49 << CP_NV_FLAGS_3_DISCARD_49_SHIFT) | \ + (end_rcvd_49 << CP_NV_FLAGS_3_END_RCVD_49_SHIFT) | \ + (discard_50 << CP_NV_FLAGS_3_DISCARD_50_SHIFT) | \ + (end_rcvd_50 << CP_NV_FLAGS_3_END_RCVD_50_SHIFT) | \ + (discard_51 << CP_NV_FLAGS_3_DISCARD_51_SHIFT) | \ + (end_rcvd_51 << CP_NV_FLAGS_3_END_RCVD_51_SHIFT) | \ + (discard_52 << CP_NV_FLAGS_3_DISCARD_52_SHIFT) | \ + (end_rcvd_52 << CP_NV_FLAGS_3_END_RCVD_52_SHIFT) | \ + (discard_53 << CP_NV_FLAGS_3_DISCARD_53_SHIFT) | \ + (end_rcvd_53 << CP_NV_FLAGS_3_END_RCVD_53_SHIFT) | \ + (discard_54 << CP_NV_FLAGS_3_DISCARD_54_SHIFT) | \ + (end_rcvd_54 << CP_NV_FLAGS_3_END_RCVD_54_SHIFT) | \ + (discard_55 << CP_NV_FLAGS_3_DISCARD_55_SHIFT) | \ + (end_rcvd_55 << CP_NV_FLAGS_3_END_RCVD_55_SHIFT) | \ + (discard_56 << CP_NV_FLAGS_3_DISCARD_56_SHIFT) | \ + (end_rcvd_56 << CP_NV_FLAGS_3_END_RCVD_56_SHIFT) | \ + (discard_57 << CP_NV_FLAGS_3_DISCARD_57_SHIFT) | \ + (end_rcvd_57 << CP_NV_FLAGS_3_END_RCVD_57_SHIFT) | \ + (discard_58 << CP_NV_FLAGS_3_DISCARD_58_SHIFT) | \ + (end_rcvd_58 << CP_NV_FLAGS_3_END_RCVD_58_SHIFT) | \ + (discard_59 << CP_NV_FLAGS_3_DISCARD_59_SHIFT) | \ + (end_rcvd_59 << CP_NV_FLAGS_3_END_RCVD_59_SHIFT) | \ + (discard_60 << CP_NV_FLAGS_3_DISCARD_60_SHIFT) | \ + (end_rcvd_60 << CP_NV_FLAGS_3_END_RCVD_60_SHIFT) | \ + (discard_61 << CP_NV_FLAGS_3_DISCARD_61_SHIFT) | \ + (end_rcvd_61 << CP_NV_FLAGS_3_END_RCVD_61_SHIFT) | \ + (discard_62 << CP_NV_FLAGS_3_DISCARD_62_SHIFT) | \ + (end_rcvd_62 << CP_NV_FLAGS_3_END_RCVD_62_SHIFT) | \ + (discard_63 << CP_NV_FLAGS_3_DISCARD_63_SHIFT) | \ + (end_rcvd_63 << CP_NV_FLAGS_3_END_RCVD_63_SHIFT)) + +#define CP_NV_FLAGS_3_GET_DISCARD_48(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_48_MASK) >> CP_NV_FLAGS_3_DISCARD_48_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_48(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_48_MASK) >> CP_NV_FLAGS_3_END_RCVD_48_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_49(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_49_MASK) >> CP_NV_FLAGS_3_DISCARD_49_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_49(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_49_MASK) >> CP_NV_FLAGS_3_END_RCVD_49_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_50(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_50_MASK) >> CP_NV_FLAGS_3_DISCARD_50_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_50(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_50_MASK) >> CP_NV_FLAGS_3_END_RCVD_50_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_51(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_51_MASK) >> CP_NV_FLAGS_3_DISCARD_51_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_51(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_51_MASK) >> CP_NV_FLAGS_3_END_RCVD_51_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_52(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_52_MASK) >> CP_NV_FLAGS_3_DISCARD_52_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_52(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_52_MASK) >> CP_NV_FLAGS_3_END_RCVD_52_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_53(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_53_MASK) >> CP_NV_FLAGS_3_DISCARD_53_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_53(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_53_MASK) >> CP_NV_FLAGS_3_END_RCVD_53_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_54(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_54_MASK) >> CP_NV_FLAGS_3_DISCARD_54_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_54(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_54_MASK) >> CP_NV_FLAGS_3_END_RCVD_54_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_55(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_55_MASK) >> CP_NV_FLAGS_3_DISCARD_55_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_55(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_55_MASK) >> CP_NV_FLAGS_3_END_RCVD_55_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_56(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_56_MASK) >> CP_NV_FLAGS_3_DISCARD_56_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_56(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_56_MASK) >> CP_NV_FLAGS_3_END_RCVD_56_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_57(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_57_MASK) >> CP_NV_FLAGS_3_DISCARD_57_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_57(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_57_MASK) >> CP_NV_FLAGS_3_END_RCVD_57_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_58(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_58_MASK) >> CP_NV_FLAGS_3_DISCARD_58_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_58(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_58_MASK) >> CP_NV_FLAGS_3_END_RCVD_58_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_59(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_59_MASK) >> CP_NV_FLAGS_3_DISCARD_59_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_59(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_59_MASK) >> CP_NV_FLAGS_3_END_RCVD_59_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_60(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_60_MASK) >> CP_NV_FLAGS_3_DISCARD_60_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_60(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_60_MASK) >> CP_NV_FLAGS_3_END_RCVD_60_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_61(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_61_MASK) >> CP_NV_FLAGS_3_DISCARD_61_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_61(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_61_MASK) >> CP_NV_FLAGS_3_END_RCVD_61_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_62(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_62_MASK) >> CP_NV_FLAGS_3_DISCARD_62_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_62(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_62_MASK) >> CP_NV_FLAGS_3_END_RCVD_62_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_63(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_63_MASK) >> CP_NV_FLAGS_3_DISCARD_63_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_63(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_63_MASK) >> CP_NV_FLAGS_3_END_RCVD_63_SHIFT) + +#define CP_NV_FLAGS_3_SET_DISCARD_48(cp_nv_flags_3_reg, discard_48) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_48_MASK) | (discard_48 << CP_NV_FLAGS_3_DISCARD_48_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_48(cp_nv_flags_3_reg, end_rcvd_48) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_48_MASK) | (end_rcvd_48 << CP_NV_FLAGS_3_END_RCVD_48_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_49(cp_nv_flags_3_reg, discard_49) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_49_MASK) | (discard_49 << CP_NV_FLAGS_3_DISCARD_49_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_49(cp_nv_flags_3_reg, end_rcvd_49) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_49_MASK) | (end_rcvd_49 << CP_NV_FLAGS_3_END_RCVD_49_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_50(cp_nv_flags_3_reg, discard_50) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_50_MASK) | (discard_50 << CP_NV_FLAGS_3_DISCARD_50_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_50(cp_nv_flags_3_reg, end_rcvd_50) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_50_MASK) | (end_rcvd_50 << CP_NV_FLAGS_3_END_RCVD_50_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_51(cp_nv_flags_3_reg, discard_51) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_51_MASK) | (discard_51 << CP_NV_FLAGS_3_DISCARD_51_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_51(cp_nv_flags_3_reg, end_rcvd_51) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_51_MASK) | (end_rcvd_51 << CP_NV_FLAGS_3_END_RCVD_51_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_52(cp_nv_flags_3_reg, discard_52) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_52_MASK) | (discard_52 << CP_NV_FLAGS_3_DISCARD_52_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_52(cp_nv_flags_3_reg, end_rcvd_52) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_52_MASK) | (end_rcvd_52 << CP_NV_FLAGS_3_END_RCVD_52_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_53(cp_nv_flags_3_reg, discard_53) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_53_MASK) | (discard_53 << CP_NV_FLAGS_3_DISCARD_53_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_53(cp_nv_flags_3_reg, end_rcvd_53) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_53_MASK) | (end_rcvd_53 << CP_NV_FLAGS_3_END_RCVD_53_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_54(cp_nv_flags_3_reg, discard_54) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_54_MASK) | (discard_54 << CP_NV_FLAGS_3_DISCARD_54_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_54(cp_nv_flags_3_reg, end_rcvd_54) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_54_MASK) | (end_rcvd_54 << CP_NV_FLAGS_3_END_RCVD_54_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_55(cp_nv_flags_3_reg, discard_55) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_55_MASK) | (discard_55 << CP_NV_FLAGS_3_DISCARD_55_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_55(cp_nv_flags_3_reg, end_rcvd_55) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_55_MASK) | (end_rcvd_55 << CP_NV_FLAGS_3_END_RCVD_55_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_56(cp_nv_flags_3_reg, discard_56) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_56_MASK) | (discard_56 << CP_NV_FLAGS_3_DISCARD_56_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_56(cp_nv_flags_3_reg, end_rcvd_56) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_56_MASK) | (end_rcvd_56 << CP_NV_FLAGS_3_END_RCVD_56_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_57(cp_nv_flags_3_reg, discard_57) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_57_MASK) | (discard_57 << CP_NV_FLAGS_3_DISCARD_57_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_57(cp_nv_flags_3_reg, end_rcvd_57) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_57_MASK) | (end_rcvd_57 << CP_NV_FLAGS_3_END_RCVD_57_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_58(cp_nv_flags_3_reg, discard_58) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_58_MASK) | (discard_58 << CP_NV_FLAGS_3_DISCARD_58_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_58(cp_nv_flags_3_reg, end_rcvd_58) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_58_MASK) | (end_rcvd_58 << CP_NV_FLAGS_3_END_RCVD_58_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_59(cp_nv_flags_3_reg, discard_59) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_59_MASK) | (discard_59 << CP_NV_FLAGS_3_DISCARD_59_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_59(cp_nv_flags_3_reg, end_rcvd_59) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_59_MASK) | (end_rcvd_59 << CP_NV_FLAGS_3_END_RCVD_59_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_60(cp_nv_flags_3_reg, discard_60) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_60_MASK) | (discard_60 << CP_NV_FLAGS_3_DISCARD_60_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_60(cp_nv_flags_3_reg, end_rcvd_60) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_60_MASK) | (end_rcvd_60 << CP_NV_FLAGS_3_END_RCVD_60_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_61(cp_nv_flags_3_reg, discard_61) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_61_MASK) | (discard_61 << CP_NV_FLAGS_3_DISCARD_61_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_61(cp_nv_flags_3_reg, end_rcvd_61) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_61_MASK) | (end_rcvd_61 << CP_NV_FLAGS_3_END_RCVD_61_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_62(cp_nv_flags_3_reg, discard_62) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_62_MASK) | (discard_62 << CP_NV_FLAGS_3_DISCARD_62_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_62(cp_nv_flags_3_reg, end_rcvd_62) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_62_MASK) | (end_rcvd_62 << CP_NV_FLAGS_3_END_RCVD_62_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_63(cp_nv_flags_3_reg, discard_63) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_63_MASK) | (discard_63 << CP_NV_FLAGS_3_DISCARD_63_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_63(cp_nv_flags_3_reg, end_rcvd_63) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_63_MASK) | (end_rcvd_63 << CP_NV_FLAGS_3_END_RCVD_63_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_nv_flags_3_t { + unsigned int discard_48 : CP_NV_FLAGS_3_DISCARD_48_SIZE; + unsigned int end_rcvd_48 : CP_NV_FLAGS_3_END_RCVD_48_SIZE; + unsigned int discard_49 : CP_NV_FLAGS_3_DISCARD_49_SIZE; + unsigned int end_rcvd_49 : CP_NV_FLAGS_3_END_RCVD_49_SIZE; + unsigned int discard_50 : CP_NV_FLAGS_3_DISCARD_50_SIZE; + unsigned int end_rcvd_50 : CP_NV_FLAGS_3_END_RCVD_50_SIZE; + unsigned int discard_51 : CP_NV_FLAGS_3_DISCARD_51_SIZE; + unsigned int end_rcvd_51 : CP_NV_FLAGS_3_END_RCVD_51_SIZE; + unsigned int discard_52 : CP_NV_FLAGS_3_DISCARD_52_SIZE; + unsigned int end_rcvd_52 : CP_NV_FLAGS_3_END_RCVD_52_SIZE; + unsigned int discard_53 : CP_NV_FLAGS_3_DISCARD_53_SIZE; + unsigned int end_rcvd_53 : CP_NV_FLAGS_3_END_RCVD_53_SIZE; + unsigned int discard_54 : CP_NV_FLAGS_3_DISCARD_54_SIZE; + unsigned int end_rcvd_54 : CP_NV_FLAGS_3_END_RCVD_54_SIZE; + unsigned int discard_55 : CP_NV_FLAGS_3_DISCARD_55_SIZE; + unsigned int end_rcvd_55 : CP_NV_FLAGS_3_END_RCVD_55_SIZE; + unsigned int discard_56 : CP_NV_FLAGS_3_DISCARD_56_SIZE; + unsigned int end_rcvd_56 : CP_NV_FLAGS_3_END_RCVD_56_SIZE; + unsigned int discard_57 : CP_NV_FLAGS_3_DISCARD_57_SIZE; + unsigned int end_rcvd_57 : CP_NV_FLAGS_3_END_RCVD_57_SIZE; + unsigned int discard_58 : CP_NV_FLAGS_3_DISCARD_58_SIZE; + unsigned int end_rcvd_58 : CP_NV_FLAGS_3_END_RCVD_58_SIZE; + unsigned int discard_59 : CP_NV_FLAGS_3_DISCARD_59_SIZE; + unsigned int end_rcvd_59 : CP_NV_FLAGS_3_END_RCVD_59_SIZE; + unsigned int discard_60 : CP_NV_FLAGS_3_DISCARD_60_SIZE; + unsigned int end_rcvd_60 : CP_NV_FLAGS_3_END_RCVD_60_SIZE; + unsigned int discard_61 : CP_NV_FLAGS_3_DISCARD_61_SIZE; + unsigned int end_rcvd_61 : CP_NV_FLAGS_3_END_RCVD_61_SIZE; + unsigned int discard_62 : CP_NV_FLAGS_3_DISCARD_62_SIZE; + unsigned int end_rcvd_62 : CP_NV_FLAGS_3_END_RCVD_62_SIZE; + unsigned int discard_63 : CP_NV_FLAGS_3_DISCARD_63_SIZE; + unsigned int end_rcvd_63 : CP_NV_FLAGS_3_END_RCVD_63_SIZE; + } cp_nv_flags_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_nv_flags_3_t { + unsigned int end_rcvd_63 : CP_NV_FLAGS_3_END_RCVD_63_SIZE; + unsigned int discard_63 : CP_NV_FLAGS_3_DISCARD_63_SIZE; + unsigned int end_rcvd_62 : CP_NV_FLAGS_3_END_RCVD_62_SIZE; + unsigned int discard_62 : CP_NV_FLAGS_3_DISCARD_62_SIZE; + unsigned int end_rcvd_61 : CP_NV_FLAGS_3_END_RCVD_61_SIZE; + unsigned int discard_61 : CP_NV_FLAGS_3_DISCARD_61_SIZE; + unsigned int end_rcvd_60 : CP_NV_FLAGS_3_END_RCVD_60_SIZE; + unsigned int discard_60 : CP_NV_FLAGS_3_DISCARD_60_SIZE; + unsigned int end_rcvd_59 : CP_NV_FLAGS_3_END_RCVD_59_SIZE; + unsigned int discard_59 : CP_NV_FLAGS_3_DISCARD_59_SIZE; + unsigned int end_rcvd_58 : CP_NV_FLAGS_3_END_RCVD_58_SIZE; + unsigned int discard_58 : CP_NV_FLAGS_3_DISCARD_58_SIZE; + unsigned int end_rcvd_57 : CP_NV_FLAGS_3_END_RCVD_57_SIZE; + unsigned int discard_57 : CP_NV_FLAGS_3_DISCARD_57_SIZE; + unsigned int end_rcvd_56 : CP_NV_FLAGS_3_END_RCVD_56_SIZE; + unsigned int discard_56 : CP_NV_FLAGS_3_DISCARD_56_SIZE; + unsigned int end_rcvd_55 : CP_NV_FLAGS_3_END_RCVD_55_SIZE; + unsigned int discard_55 : CP_NV_FLAGS_3_DISCARD_55_SIZE; + unsigned int end_rcvd_54 : CP_NV_FLAGS_3_END_RCVD_54_SIZE; + unsigned int discard_54 : CP_NV_FLAGS_3_DISCARD_54_SIZE; + unsigned int end_rcvd_53 : CP_NV_FLAGS_3_END_RCVD_53_SIZE; + unsigned int discard_53 : CP_NV_FLAGS_3_DISCARD_53_SIZE; + unsigned int end_rcvd_52 : CP_NV_FLAGS_3_END_RCVD_52_SIZE; + unsigned int discard_52 : CP_NV_FLAGS_3_DISCARD_52_SIZE; + unsigned int end_rcvd_51 : CP_NV_FLAGS_3_END_RCVD_51_SIZE; + unsigned int discard_51 : CP_NV_FLAGS_3_DISCARD_51_SIZE; + unsigned int end_rcvd_50 : CP_NV_FLAGS_3_END_RCVD_50_SIZE; + unsigned int discard_50 : CP_NV_FLAGS_3_DISCARD_50_SIZE; + unsigned int end_rcvd_49 : CP_NV_FLAGS_3_END_RCVD_49_SIZE; + unsigned int discard_49 : CP_NV_FLAGS_3_DISCARD_49_SIZE; + unsigned int end_rcvd_48 : CP_NV_FLAGS_3_END_RCVD_48_SIZE; + unsigned int discard_48 : CP_NV_FLAGS_3_DISCARD_48_SIZE; + } cp_nv_flags_3_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_nv_flags_3_t f; +} cp_nv_flags_3_u; + + +/* + * CP_STATE_DEBUG_INDEX struct + */ + +#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE 5 + +#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT 0 + +#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK 0x0000001f + +#define CP_STATE_DEBUG_INDEX_MASK \ + (CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) + +#define CP_STATE_DEBUG_INDEX(state_debug_index) \ + ((state_debug_index << CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT)) + +#define CP_STATE_DEBUG_INDEX_GET_STATE_DEBUG_INDEX(cp_state_debug_index) \ + ((cp_state_debug_index & CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) >> CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT) + +#define CP_STATE_DEBUG_INDEX_SET_STATE_DEBUG_INDEX(cp_state_debug_index_reg, state_debug_index) \ + cp_state_debug_index_reg = (cp_state_debug_index_reg & ~CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) | (state_debug_index << CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_state_debug_index_t { + unsigned int state_debug_index : CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE; + unsigned int : 27; + } cp_state_debug_index_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_state_debug_index_t { + unsigned int : 27; + unsigned int state_debug_index : CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE; + } cp_state_debug_index_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_state_debug_index_t f; +} cp_state_debug_index_u; + + +/* + * CP_STATE_DEBUG_DATA struct + */ + +#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE 32 + +#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT 0 + +#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK 0xffffffff + +#define CP_STATE_DEBUG_DATA_MASK \ + (CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) + +#define CP_STATE_DEBUG_DATA(state_debug_data) \ + ((state_debug_data << CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT)) + +#define CP_STATE_DEBUG_DATA_GET_STATE_DEBUG_DATA(cp_state_debug_data) \ + ((cp_state_debug_data & CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) >> CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT) + +#define CP_STATE_DEBUG_DATA_SET_STATE_DEBUG_DATA(cp_state_debug_data_reg, state_debug_data) \ + cp_state_debug_data_reg = (cp_state_debug_data_reg & ~CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) | (state_debug_data << CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_state_debug_data_t { + unsigned int state_debug_data : CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE; + } cp_state_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_state_debug_data_t { + unsigned int state_debug_data : CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE; + } cp_state_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_state_debug_data_t f; +} cp_state_debug_data_u; + + +/* + * CP_PROG_COUNTER struct + */ + +#define CP_PROG_COUNTER_COUNTER_SIZE 32 + +#define CP_PROG_COUNTER_COUNTER_SHIFT 0 + +#define CP_PROG_COUNTER_COUNTER_MASK 0xffffffff + +#define CP_PROG_COUNTER_MASK \ + (CP_PROG_COUNTER_COUNTER_MASK) + +#define CP_PROG_COUNTER(counter) \ + ((counter << CP_PROG_COUNTER_COUNTER_SHIFT)) + +#define CP_PROG_COUNTER_GET_COUNTER(cp_prog_counter) \ + ((cp_prog_counter & CP_PROG_COUNTER_COUNTER_MASK) >> CP_PROG_COUNTER_COUNTER_SHIFT) + +#define CP_PROG_COUNTER_SET_COUNTER(cp_prog_counter_reg, counter) \ + cp_prog_counter_reg = (cp_prog_counter_reg & ~CP_PROG_COUNTER_COUNTER_MASK) | (counter << CP_PROG_COUNTER_COUNTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_prog_counter_t { + unsigned int counter : CP_PROG_COUNTER_COUNTER_SIZE; + } cp_prog_counter_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_prog_counter_t { + unsigned int counter : CP_PROG_COUNTER_COUNTER_SIZE; + } cp_prog_counter_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_prog_counter_t f; +} cp_prog_counter_u; + + +/* + * CP_STAT struct + */ + +#define CP_STAT_MIU_WR_BUSY_SIZE 1 +#define CP_STAT_MIU_RD_REQ_BUSY_SIZE 1 +#define CP_STAT_MIU_RD_RETURN_BUSY_SIZE 1 +#define CP_STAT_RBIU_BUSY_SIZE 1 +#define CP_STAT_RCIU_BUSY_SIZE 1 +#define CP_STAT_CSF_RING_BUSY_SIZE 1 +#define CP_STAT_CSF_INDIRECTS_BUSY_SIZE 1 +#define CP_STAT_CSF_INDIRECT2_BUSY_SIZE 1 +#define CP_STAT_CSF_ST_BUSY_SIZE 1 +#define CP_STAT_CSF_BUSY_SIZE 1 +#define CP_STAT_RING_QUEUE_BUSY_SIZE 1 +#define CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE 1 +#define CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE 1 +#define CP_STAT_ST_QUEUE_BUSY_SIZE 1 +#define CP_STAT_PFP_BUSY_SIZE 1 +#define CP_STAT_MEQ_RING_BUSY_SIZE 1 +#define CP_STAT_MEQ_INDIRECTS_BUSY_SIZE 1 +#define CP_STAT_MEQ_INDIRECT2_BUSY_SIZE 1 +#define CP_STAT_MIU_WC_STALL_SIZE 1 +#define CP_STAT_CP_NRT_BUSY_SIZE 1 +#define CP_STAT__3D_BUSY_SIZE 1 +#define CP_STAT_ME_BUSY_SIZE 1 +#define CP_STAT_ME_WC_BUSY_SIZE 1 +#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE 1 +#define CP_STAT_CP_BUSY_SIZE 1 + +#define CP_STAT_MIU_WR_BUSY_SHIFT 0 +#define CP_STAT_MIU_RD_REQ_BUSY_SHIFT 1 +#define CP_STAT_MIU_RD_RETURN_BUSY_SHIFT 2 +#define CP_STAT_RBIU_BUSY_SHIFT 3 +#define CP_STAT_RCIU_BUSY_SHIFT 4 +#define CP_STAT_CSF_RING_BUSY_SHIFT 5 +#define CP_STAT_CSF_INDIRECTS_BUSY_SHIFT 6 +#define CP_STAT_CSF_INDIRECT2_BUSY_SHIFT 7 +#define CP_STAT_CSF_ST_BUSY_SHIFT 9 +#define CP_STAT_CSF_BUSY_SHIFT 10 +#define CP_STAT_RING_QUEUE_BUSY_SHIFT 11 +#define CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT 12 +#define CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT 13 +#define CP_STAT_ST_QUEUE_BUSY_SHIFT 16 +#define CP_STAT_PFP_BUSY_SHIFT 17 +#define CP_STAT_MEQ_RING_BUSY_SHIFT 18 +#define CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT 19 +#define CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT 20 +#define CP_STAT_MIU_WC_STALL_SHIFT 21 +#define CP_STAT_CP_NRT_BUSY_SHIFT 22 +#define CP_STAT__3D_BUSY_SHIFT 23 +#define CP_STAT_ME_BUSY_SHIFT 26 +#define CP_STAT_ME_WC_BUSY_SHIFT 29 +#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT 30 +#define CP_STAT_CP_BUSY_SHIFT 31 + +#define CP_STAT_MIU_WR_BUSY_MASK 0x00000001 +#define CP_STAT_MIU_RD_REQ_BUSY_MASK 0x00000002 +#define CP_STAT_MIU_RD_RETURN_BUSY_MASK 0x00000004 +#define CP_STAT_RBIU_BUSY_MASK 0x00000008 +#define CP_STAT_RCIU_BUSY_MASK 0x00000010 +#define CP_STAT_CSF_RING_BUSY_MASK 0x00000020 +#define CP_STAT_CSF_INDIRECTS_BUSY_MASK 0x00000040 +#define CP_STAT_CSF_INDIRECT2_BUSY_MASK 0x00000080 +#define CP_STAT_CSF_ST_BUSY_MASK 0x00000200 +#define CP_STAT_CSF_BUSY_MASK 0x00000400 +#define CP_STAT_RING_QUEUE_BUSY_MASK 0x00000800 +#define CP_STAT_INDIRECTS_QUEUE_BUSY_MASK 0x00001000 +#define CP_STAT_INDIRECT2_QUEUE_BUSY_MASK 0x00002000 +#define CP_STAT_ST_QUEUE_BUSY_MASK 0x00010000 +#define CP_STAT_PFP_BUSY_MASK 0x00020000 +#define CP_STAT_MEQ_RING_BUSY_MASK 0x00040000 +#define CP_STAT_MEQ_INDIRECTS_BUSY_MASK 0x00080000 +#define CP_STAT_MEQ_INDIRECT2_BUSY_MASK 0x00100000 +#define CP_STAT_MIU_WC_STALL_MASK 0x00200000 +#define CP_STAT_CP_NRT_BUSY_MASK 0x00400000 +#define CP_STAT__3D_BUSY_MASK 0x00800000 +#define CP_STAT_ME_BUSY_MASK 0x04000000 +#define CP_STAT_ME_WC_BUSY_MASK 0x20000000 +#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK 0x40000000 +#define CP_STAT_CP_BUSY_MASK 0x80000000 + +#define CP_STAT_MASK \ + (CP_STAT_MIU_WR_BUSY_MASK | \ + CP_STAT_MIU_RD_REQ_BUSY_MASK | \ + CP_STAT_MIU_RD_RETURN_BUSY_MASK | \ + CP_STAT_RBIU_BUSY_MASK | \ + CP_STAT_RCIU_BUSY_MASK | \ + CP_STAT_CSF_RING_BUSY_MASK | \ + CP_STAT_CSF_INDIRECTS_BUSY_MASK | \ + CP_STAT_CSF_INDIRECT2_BUSY_MASK | \ + CP_STAT_CSF_ST_BUSY_MASK | \ + CP_STAT_CSF_BUSY_MASK | \ + CP_STAT_RING_QUEUE_BUSY_MASK | \ + CP_STAT_INDIRECTS_QUEUE_BUSY_MASK | \ + CP_STAT_INDIRECT2_QUEUE_BUSY_MASK | \ + CP_STAT_ST_QUEUE_BUSY_MASK | \ + CP_STAT_PFP_BUSY_MASK | \ + CP_STAT_MEQ_RING_BUSY_MASK | \ + CP_STAT_MEQ_INDIRECTS_BUSY_MASK | \ + CP_STAT_MEQ_INDIRECT2_BUSY_MASK | \ + CP_STAT_MIU_WC_STALL_MASK | \ + CP_STAT_CP_NRT_BUSY_MASK | \ + CP_STAT__3D_BUSY_MASK | \ + CP_STAT_ME_BUSY_MASK | \ + CP_STAT_ME_WC_BUSY_MASK | \ + CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK | \ + CP_STAT_CP_BUSY_MASK) + +#define CP_STAT(miu_wr_busy, miu_rd_req_busy, miu_rd_return_busy, rbiu_busy, rciu_busy, csf_ring_busy, csf_indirects_busy, csf_indirect2_busy, csf_st_busy, csf_busy, ring_queue_busy, indirects_queue_busy, indirect2_queue_busy, st_queue_busy, pfp_busy, meq_ring_busy, meq_indirects_busy, meq_indirect2_busy, miu_wc_stall, cp_nrt_busy, _3d_busy, me_busy, me_wc_busy, miu_wc_track_fifo_empty, cp_busy) \ + ((miu_wr_busy << CP_STAT_MIU_WR_BUSY_SHIFT) | \ + (miu_rd_req_busy << CP_STAT_MIU_RD_REQ_BUSY_SHIFT) | \ + (miu_rd_return_busy << CP_STAT_MIU_RD_RETURN_BUSY_SHIFT) | \ + (rbiu_busy << CP_STAT_RBIU_BUSY_SHIFT) | \ + (rciu_busy << CP_STAT_RCIU_BUSY_SHIFT) | \ + (csf_ring_busy << CP_STAT_CSF_RING_BUSY_SHIFT) | \ + (csf_indirects_busy << CP_STAT_CSF_INDIRECTS_BUSY_SHIFT) | \ + (csf_indirect2_busy << CP_STAT_CSF_INDIRECT2_BUSY_SHIFT) | \ + (csf_st_busy << CP_STAT_CSF_ST_BUSY_SHIFT) | \ + (csf_busy << CP_STAT_CSF_BUSY_SHIFT) | \ + (ring_queue_busy << CP_STAT_RING_QUEUE_BUSY_SHIFT) | \ + (indirects_queue_busy << CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT) | \ + (indirect2_queue_busy << CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT) | \ + (st_queue_busy << CP_STAT_ST_QUEUE_BUSY_SHIFT) | \ + (pfp_busy << CP_STAT_PFP_BUSY_SHIFT) | \ + (meq_ring_busy << CP_STAT_MEQ_RING_BUSY_SHIFT) | \ + (meq_indirects_busy << CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT) | \ + (meq_indirect2_busy << CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT) | \ + (miu_wc_stall << CP_STAT_MIU_WC_STALL_SHIFT) | \ + (cp_nrt_busy << CP_STAT_CP_NRT_BUSY_SHIFT) | \ + (_3d_busy << CP_STAT__3D_BUSY_SHIFT) | \ + (me_busy << CP_STAT_ME_BUSY_SHIFT) | \ + (me_wc_busy << CP_STAT_ME_WC_BUSY_SHIFT) | \ + (miu_wc_track_fifo_empty << CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT) | \ + (cp_busy << CP_STAT_CP_BUSY_SHIFT)) + +#define CP_STAT_GET_MIU_WR_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MIU_WR_BUSY_MASK) >> CP_STAT_MIU_WR_BUSY_SHIFT) +#define CP_STAT_GET_MIU_RD_REQ_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MIU_RD_REQ_BUSY_MASK) >> CP_STAT_MIU_RD_REQ_BUSY_SHIFT) +#define CP_STAT_GET_MIU_RD_RETURN_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MIU_RD_RETURN_BUSY_MASK) >> CP_STAT_MIU_RD_RETURN_BUSY_SHIFT) +#define CP_STAT_GET_RBIU_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_RBIU_BUSY_MASK) >> CP_STAT_RBIU_BUSY_SHIFT) +#define CP_STAT_GET_RCIU_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_RCIU_BUSY_MASK) >> CP_STAT_RCIU_BUSY_SHIFT) +#define CP_STAT_GET_CSF_RING_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_RING_BUSY_MASK) >> CP_STAT_CSF_RING_BUSY_SHIFT) +#define CP_STAT_GET_CSF_INDIRECTS_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_INDIRECTS_BUSY_MASK) >> CP_STAT_CSF_INDIRECTS_BUSY_SHIFT) +#define CP_STAT_GET_CSF_INDIRECT2_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_INDIRECT2_BUSY_MASK) >> CP_STAT_CSF_INDIRECT2_BUSY_SHIFT) +#define CP_STAT_GET_CSF_ST_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_ST_BUSY_MASK) >> CP_STAT_CSF_ST_BUSY_SHIFT) +#define CP_STAT_GET_CSF_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_BUSY_MASK) >> CP_STAT_CSF_BUSY_SHIFT) +#define CP_STAT_GET_RING_QUEUE_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_RING_QUEUE_BUSY_MASK) >> CP_STAT_RING_QUEUE_BUSY_SHIFT) +#define CP_STAT_GET_INDIRECTS_QUEUE_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_INDIRECTS_QUEUE_BUSY_MASK) >> CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT) +#define CP_STAT_GET_INDIRECT2_QUEUE_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_INDIRECT2_QUEUE_BUSY_MASK) >> CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT) +#define CP_STAT_GET_ST_QUEUE_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_ST_QUEUE_BUSY_MASK) >> CP_STAT_ST_QUEUE_BUSY_SHIFT) +#define CP_STAT_GET_PFP_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_PFP_BUSY_MASK) >> CP_STAT_PFP_BUSY_SHIFT) +#define CP_STAT_GET_MEQ_RING_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MEQ_RING_BUSY_MASK) >> CP_STAT_MEQ_RING_BUSY_SHIFT) +#define CP_STAT_GET_MEQ_INDIRECTS_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MEQ_INDIRECTS_BUSY_MASK) >> CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT) +#define CP_STAT_GET_MEQ_INDIRECT2_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MEQ_INDIRECT2_BUSY_MASK) >> CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT) +#define CP_STAT_GET_MIU_WC_STALL(cp_stat) \ + ((cp_stat & CP_STAT_MIU_WC_STALL_MASK) >> CP_STAT_MIU_WC_STALL_SHIFT) +#define CP_STAT_GET_CP_NRT_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CP_NRT_BUSY_MASK) >> CP_STAT_CP_NRT_BUSY_SHIFT) +#define CP_STAT_GET__3D_BUSY(cp_stat) \ + ((cp_stat & CP_STAT__3D_BUSY_MASK) >> CP_STAT__3D_BUSY_SHIFT) +#define CP_STAT_GET_ME_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_ME_BUSY_MASK) >> CP_STAT_ME_BUSY_SHIFT) +#define CP_STAT_GET_ME_WC_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_ME_WC_BUSY_MASK) >> CP_STAT_ME_WC_BUSY_SHIFT) +#define CP_STAT_GET_MIU_WC_TRACK_FIFO_EMPTY(cp_stat) \ + ((cp_stat & CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK) >> CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT) +#define CP_STAT_GET_CP_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CP_BUSY_MASK) >> CP_STAT_CP_BUSY_SHIFT) + +#define CP_STAT_SET_MIU_WR_BUSY(cp_stat_reg, miu_wr_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WR_BUSY_MASK) | (miu_wr_busy << CP_STAT_MIU_WR_BUSY_SHIFT) +#define CP_STAT_SET_MIU_RD_REQ_BUSY(cp_stat_reg, miu_rd_req_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_RD_REQ_BUSY_MASK) | (miu_rd_req_busy << CP_STAT_MIU_RD_REQ_BUSY_SHIFT) +#define CP_STAT_SET_MIU_RD_RETURN_BUSY(cp_stat_reg, miu_rd_return_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_RD_RETURN_BUSY_MASK) | (miu_rd_return_busy << CP_STAT_MIU_RD_RETURN_BUSY_SHIFT) +#define CP_STAT_SET_RBIU_BUSY(cp_stat_reg, rbiu_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_RBIU_BUSY_MASK) | (rbiu_busy << CP_STAT_RBIU_BUSY_SHIFT) +#define CP_STAT_SET_RCIU_BUSY(cp_stat_reg, rciu_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_RCIU_BUSY_MASK) | (rciu_busy << CP_STAT_RCIU_BUSY_SHIFT) +#define CP_STAT_SET_CSF_RING_BUSY(cp_stat_reg, csf_ring_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_RING_BUSY_MASK) | (csf_ring_busy << CP_STAT_CSF_RING_BUSY_SHIFT) +#define CP_STAT_SET_CSF_INDIRECTS_BUSY(cp_stat_reg, csf_indirects_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_INDIRECTS_BUSY_MASK) | (csf_indirects_busy << CP_STAT_CSF_INDIRECTS_BUSY_SHIFT) +#define CP_STAT_SET_CSF_INDIRECT2_BUSY(cp_stat_reg, csf_indirect2_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_INDIRECT2_BUSY_MASK) | (csf_indirect2_busy << CP_STAT_CSF_INDIRECT2_BUSY_SHIFT) +#define CP_STAT_SET_CSF_ST_BUSY(cp_stat_reg, csf_st_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_ST_BUSY_MASK) | (csf_st_busy << CP_STAT_CSF_ST_BUSY_SHIFT) +#define CP_STAT_SET_CSF_BUSY(cp_stat_reg, csf_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_BUSY_MASK) | (csf_busy << CP_STAT_CSF_BUSY_SHIFT) +#define CP_STAT_SET_RING_QUEUE_BUSY(cp_stat_reg, ring_queue_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_RING_QUEUE_BUSY_MASK) | (ring_queue_busy << CP_STAT_RING_QUEUE_BUSY_SHIFT) +#define CP_STAT_SET_INDIRECTS_QUEUE_BUSY(cp_stat_reg, indirects_queue_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_INDIRECTS_QUEUE_BUSY_MASK) | (indirects_queue_busy << CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT) +#define CP_STAT_SET_INDIRECT2_QUEUE_BUSY(cp_stat_reg, indirect2_queue_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_INDIRECT2_QUEUE_BUSY_MASK) | (indirect2_queue_busy << CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT) +#define CP_STAT_SET_ST_QUEUE_BUSY(cp_stat_reg, st_queue_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_ST_QUEUE_BUSY_MASK) | (st_queue_busy << CP_STAT_ST_QUEUE_BUSY_SHIFT) +#define CP_STAT_SET_PFP_BUSY(cp_stat_reg, pfp_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_PFP_BUSY_MASK) | (pfp_busy << CP_STAT_PFP_BUSY_SHIFT) +#define CP_STAT_SET_MEQ_RING_BUSY(cp_stat_reg, meq_ring_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_RING_BUSY_MASK) | (meq_ring_busy << CP_STAT_MEQ_RING_BUSY_SHIFT) +#define CP_STAT_SET_MEQ_INDIRECTS_BUSY(cp_stat_reg, meq_indirects_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_INDIRECTS_BUSY_MASK) | (meq_indirects_busy << CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT) +#define CP_STAT_SET_MEQ_INDIRECT2_BUSY(cp_stat_reg, meq_indirect2_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_INDIRECT2_BUSY_MASK) | (meq_indirect2_busy << CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT) +#define CP_STAT_SET_MIU_WC_STALL(cp_stat_reg, miu_wc_stall) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WC_STALL_MASK) | (miu_wc_stall << CP_STAT_MIU_WC_STALL_SHIFT) +#define CP_STAT_SET_CP_NRT_BUSY(cp_stat_reg, cp_nrt_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CP_NRT_BUSY_MASK) | (cp_nrt_busy << CP_STAT_CP_NRT_BUSY_SHIFT) +#define CP_STAT_SET__3D_BUSY(cp_stat_reg, _3d_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT__3D_BUSY_MASK) | (_3d_busy << CP_STAT__3D_BUSY_SHIFT) +#define CP_STAT_SET_ME_BUSY(cp_stat_reg, me_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_ME_BUSY_MASK) | (me_busy << CP_STAT_ME_BUSY_SHIFT) +#define CP_STAT_SET_ME_WC_BUSY(cp_stat_reg, me_wc_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_ME_WC_BUSY_MASK) | (me_wc_busy << CP_STAT_ME_WC_BUSY_SHIFT) +#define CP_STAT_SET_MIU_WC_TRACK_FIFO_EMPTY(cp_stat_reg, miu_wc_track_fifo_empty) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK) | (miu_wc_track_fifo_empty << CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT) +#define CP_STAT_SET_CP_BUSY(cp_stat_reg, cp_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CP_BUSY_MASK) | (cp_busy << CP_STAT_CP_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_stat_t { + unsigned int miu_wr_busy : CP_STAT_MIU_WR_BUSY_SIZE; + unsigned int miu_rd_req_busy : CP_STAT_MIU_RD_REQ_BUSY_SIZE; + unsigned int miu_rd_return_busy : CP_STAT_MIU_RD_RETURN_BUSY_SIZE; + unsigned int rbiu_busy : CP_STAT_RBIU_BUSY_SIZE; + unsigned int rciu_busy : CP_STAT_RCIU_BUSY_SIZE; + unsigned int csf_ring_busy : CP_STAT_CSF_RING_BUSY_SIZE; + unsigned int csf_indirects_busy : CP_STAT_CSF_INDIRECTS_BUSY_SIZE; + unsigned int csf_indirect2_busy : CP_STAT_CSF_INDIRECT2_BUSY_SIZE; + unsigned int : 1; + unsigned int csf_st_busy : CP_STAT_CSF_ST_BUSY_SIZE; + unsigned int csf_busy : CP_STAT_CSF_BUSY_SIZE; + unsigned int ring_queue_busy : CP_STAT_RING_QUEUE_BUSY_SIZE; + unsigned int indirects_queue_busy : CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE; + unsigned int indirect2_queue_busy : CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE; + unsigned int : 2; + unsigned int st_queue_busy : CP_STAT_ST_QUEUE_BUSY_SIZE; + unsigned int pfp_busy : CP_STAT_PFP_BUSY_SIZE; + unsigned int meq_ring_busy : CP_STAT_MEQ_RING_BUSY_SIZE; + unsigned int meq_indirects_busy : CP_STAT_MEQ_INDIRECTS_BUSY_SIZE; + unsigned int meq_indirect2_busy : CP_STAT_MEQ_INDIRECT2_BUSY_SIZE; + unsigned int miu_wc_stall : CP_STAT_MIU_WC_STALL_SIZE; + unsigned int cp_nrt_busy : CP_STAT_CP_NRT_BUSY_SIZE; + unsigned int _3d_busy : CP_STAT__3D_BUSY_SIZE; + unsigned int : 2; + unsigned int me_busy : CP_STAT_ME_BUSY_SIZE; + unsigned int : 2; + unsigned int me_wc_busy : CP_STAT_ME_WC_BUSY_SIZE; + unsigned int miu_wc_track_fifo_empty : CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE; + unsigned int cp_busy : CP_STAT_CP_BUSY_SIZE; + } cp_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_stat_t { + unsigned int cp_busy : CP_STAT_CP_BUSY_SIZE; + unsigned int miu_wc_track_fifo_empty : CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE; + unsigned int me_wc_busy : CP_STAT_ME_WC_BUSY_SIZE; + unsigned int : 2; + unsigned int me_busy : CP_STAT_ME_BUSY_SIZE; + unsigned int : 2; + unsigned int _3d_busy : CP_STAT__3D_BUSY_SIZE; + unsigned int cp_nrt_busy : CP_STAT_CP_NRT_BUSY_SIZE; + unsigned int miu_wc_stall : CP_STAT_MIU_WC_STALL_SIZE; + unsigned int meq_indirect2_busy : CP_STAT_MEQ_INDIRECT2_BUSY_SIZE; + unsigned int meq_indirects_busy : CP_STAT_MEQ_INDIRECTS_BUSY_SIZE; + unsigned int meq_ring_busy : CP_STAT_MEQ_RING_BUSY_SIZE; + unsigned int pfp_busy : CP_STAT_PFP_BUSY_SIZE; + unsigned int st_queue_busy : CP_STAT_ST_QUEUE_BUSY_SIZE; + unsigned int : 2; + unsigned int indirect2_queue_busy : CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE; + unsigned int indirects_queue_busy : CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE; + unsigned int ring_queue_busy : CP_STAT_RING_QUEUE_BUSY_SIZE; + unsigned int csf_busy : CP_STAT_CSF_BUSY_SIZE; + unsigned int csf_st_busy : CP_STAT_CSF_ST_BUSY_SIZE; + unsigned int : 1; + unsigned int csf_indirect2_busy : CP_STAT_CSF_INDIRECT2_BUSY_SIZE; + unsigned int csf_indirects_busy : CP_STAT_CSF_INDIRECTS_BUSY_SIZE; + unsigned int csf_ring_busy : CP_STAT_CSF_RING_BUSY_SIZE; + unsigned int rciu_busy : CP_STAT_RCIU_BUSY_SIZE; + unsigned int rbiu_busy : CP_STAT_RBIU_BUSY_SIZE; + unsigned int miu_rd_return_busy : CP_STAT_MIU_RD_RETURN_BUSY_SIZE; + unsigned int miu_rd_req_busy : CP_STAT_MIU_RD_REQ_BUSY_SIZE; + unsigned int miu_wr_busy : CP_STAT_MIU_WR_BUSY_SIZE; + } cp_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_stat_t f; +} cp_stat_u; + + +/* + * BIOS_0_SCRATCH struct + */ + +#define BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_0_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_0_SCRATCH_MASK \ + (BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_0_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_0_SCRATCH_GET_BIOS_SCRATCH(bios_0_scratch) \ + ((bios_0_scratch & BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_0_SCRATCH_SET_BIOS_SCRATCH(bios_0_scratch_reg, bios_scratch) \ + bios_0_scratch_reg = (bios_0_scratch_reg & ~BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_0_scratch_t { + unsigned int bios_scratch : BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_0_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_0_scratch_t { + unsigned int bios_scratch : BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_0_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_0_scratch_t f; +} bios_0_scratch_u; + + +/* + * BIOS_1_SCRATCH struct + */ + +#define BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_1_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_1_SCRATCH_MASK \ + (BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_1_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_1_SCRATCH_GET_BIOS_SCRATCH(bios_1_scratch) \ + ((bios_1_scratch & BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_1_SCRATCH_SET_BIOS_SCRATCH(bios_1_scratch_reg, bios_scratch) \ + bios_1_scratch_reg = (bios_1_scratch_reg & ~BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_1_scratch_t { + unsigned int bios_scratch : BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_1_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_1_scratch_t { + unsigned int bios_scratch : BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_1_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_1_scratch_t f; +} bios_1_scratch_u; + + +/* + * BIOS_2_SCRATCH struct + */ + +#define BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_2_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_2_SCRATCH_MASK \ + (BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_2_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_2_SCRATCH_GET_BIOS_SCRATCH(bios_2_scratch) \ + ((bios_2_scratch & BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_2_SCRATCH_SET_BIOS_SCRATCH(bios_2_scratch_reg, bios_scratch) \ + bios_2_scratch_reg = (bios_2_scratch_reg & ~BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_2_scratch_t { + unsigned int bios_scratch : BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_2_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_2_scratch_t { + unsigned int bios_scratch : BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_2_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_2_scratch_t f; +} bios_2_scratch_u; + + +/* + * BIOS_3_SCRATCH struct + */ + +#define BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_3_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_3_SCRATCH_MASK \ + (BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_3_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_3_SCRATCH_GET_BIOS_SCRATCH(bios_3_scratch) \ + ((bios_3_scratch & BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_3_SCRATCH_SET_BIOS_SCRATCH(bios_3_scratch_reg, bios_scratch) \ + bios_3_scratch_reg = (bios_3_scratch_reg & ~BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_3_scratch_t { + unsigned int bios_scratch : BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_3_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_3_scratch_t { + unsigned int bios_scratch : BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_3_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_3_scratch_t f; +} bios_3_scratch_u; + + +/* + * BIOS_4_SCRATCH struct + */ + +#define BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_4_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_4_SCRATCH_MASK \ + (BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_4_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_4_SCRATCH_GET_BIOS_SCRATCH(bios_4_scratch) \ + ((bios_4_scratch & BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_4_SCRATCH_SET_BIOS_SCRATCH(bios_4_scratch_reg, bios_scratch) \ + bios_4_scratch_reg = (bios_4_scratch_reg & ~BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_4_scratch_t { + unsigned int bios_scratch : BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_4_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_4_scratch_t { + unsigned int bios_scratch : BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_4_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_4_scratch_t f; +} bios_4_scratch_u; + + +/* + * BIOS_5_SCRATCH struct + */ + +#define BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_5_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_5_SCRATCH_MASK \ + (BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_5_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_5_SCRATCH_GET_BIOS_SCRATCH(bios_5_scratch) \ + ((bios_5_scratch & BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_5_SCRATCH_SET_BIOS_SCRATCH(bios_5_scratch_reg, bios_scratch) \ + bios_5_scratch_reg = (bios_5_scratch_reg & ~BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_5_scratch_t { + unsigned int bios_scratch : BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_5_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_5_scratch_t { + unsigned int bios_scratch : BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_5_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_5_scratch_t f; +} bios_5_scratch_u; + + +/* + * BIOS_6_SCRATCH struct + */ + +#define BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_6_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_6_SCRATCH_MASK \ + (BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_6_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_6_SCRATCH_GET_BIOS_SCRATCH(bios_6_scratch) \ + ((bios_6_scratch & BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_6_SCRATCH_SET_BIOS_SCRATCH(bios_6_scratch_reg, bios_scratch) \ + bios_6_scratch_reg = (bios_6_scratch_reg & ~BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_6_scratch_t { + unsigned int bios_scratch : BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_6_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_6_scratch_t { + unsigned int bios_scratch : BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_6_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_6_scratch_t f; +} bios_6_scratch_u; + + +/* + * BIOS_7_SCRATCH struct + */ + +#define BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_7_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_7_SCRATCH_MASK \ + (BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_7_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_7_SCRATCH_GET_BIOS_SCRATCH(bios_7_scratch) \ + ((bios_7_scratch & BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_7_SCRATCH_SET_BIOS_SCRATCH(bios_7_scratch_reg, bios_scratch) \ + bios_7_scratch_reg = (bios_7_scratch_reg & ~BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_7_scratch_t { + unsigned int bios_scratch : BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_7_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_7_scratch_t { + unsigned int bios_scratch : BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_7_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_7_scratch_t f; +} bios_7_scratch_u; + + +/* + * BIOS_8_SCRATCH struct + */ + +#define BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_8_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_8_SCRATCH_MASK \ + (BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_8_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_8_SCRATCH_GET_BIOS_SCRATCH(bios_8_scratch) \ + ((bios_8_scratch & BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_8_SCRATCH_SET_BIOS_SCRATCH(bios_8_scratch_reg, bios_scratch) \ + bios_8_scratch_reg = (bios_8_scratch_reg & ~BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_8_scratch_t { + unsigned int bios_scratch : BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_8_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_8_scratch_t { + unsigned int bios_scratch : BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_8_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_8_scratch_t f; +} bios_8_scratch_u; + + +/* + * BIOS_9_SCRATCH struct + */ + +#define BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_9_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_9_SCRATCH_MASK \ + (BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_9_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_9_SCRATCH_GET_BIOS_SCRATCH(bios_9_scratch) \ + ((bios_9_scratch & BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_9_SCRATCH_SET_BIOS_SCRATCH(bios_9_scratch_reg, bios_scratch) \ + bios_9_scratch_reg = (bios_9_scratch_reg & ~BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_9_scratch_t { + unsigned int bios_scratch : BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_9_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_9_scratch_t { + unsigned int bios_scratch : BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_9_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_9_scratch_t f; +} bios_9_scratch_u; + + +/* + * BIOS_10_SCRATCH struct + */ + +#define BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_10_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_10_SCRATCH_MASK \ + (BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_10_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_10_SCRATCH_GET_BIOS_SCRATCH(bios_10_scratch) \ + ((bios_10_scratch & BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_10_SCRATCH_SET_BIOS_SCRATCH(bios_10_scratch_reg, bios_scratch) \ + bios_10_scratch_reg = (bios_10_scratch_reg & ~BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_10_scratch_t { + unsigned int bios_scratch : BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_10_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_10_scratch_t { + unsigned int bios_scratch : BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_10_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_10_scratch_t f; +} bios_10_scratch_u; + + +/* + * BIOS_11_SCRATCH struct + */ + +#define BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_11_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_11_SCRATCH_MASK \ + (BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_11_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_11_SCRATCH_GET_BIOS_SCRATCH(bios_11_scratch) \ + ((bios_11_scratch & BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_11_SCRATCH_SET_BIOS_SCRATCH(bios_11_scratch_reg, bios_scratch) \ + bios_11_scratch_reg = (bios_11_scratch_reg & ~BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_11_scratch_t { + unsigned int bios_scratch : BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_11_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_11_scratch_t { + unsigned int bios_scratch : BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_11_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_11_scratch_t f; +} bios_11_scratch_u; + + +/* + * BIOS_12_SCRATCH struct + */ + +#define BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_12_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_12_SCRATCH_MASK \ + (BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_12_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_12_SCRATCH_GET_BIOS_SCRATCH(bios_12_scratch) \ + ((bios_12_scratch & BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_12_SCRATCH_SET_BIOS_SCRATCH(bios_12_scratch_reg, bios_scratch) \ + bios_12_scratch_reg = (bios_12_scratch_reg & ~BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_12_scratch_t { + unsigned int bios_scratch : BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_12_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_12_scratch_t { + unsigned int bios_scratch : BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_12_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_12_scratch_t f; +} bios_12_scratch_u; + + +/* + * BIOS_13_SCRATCH struct + */ + +#define BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_13_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_13_SCRATCH_MASK \ + (BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_13_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_13_SCRATCH_GET_BIOS_SCRATCH(bios_13_scratch) \ + ((bios_13_scratch & BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_13_SCRATCH_SET_BIOS_SCRATCH(bios_13_scratch_reg, bios_scratch) \ + bios_13_scratch_reg = (bios_13_scratch_reg & ~BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_13_scratch_t { + unsigned int bios_scratch : BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_13_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_13_scratch_t { + unsigned int bios_scratch : BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_13_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_13_scratch_t f; +} bios_13_scratch_u; + + +/* + * BIOS_14_SCRATCH struct + */ + +#define BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_14_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_14_SCRATCH_MASK \ + (BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_14_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_14_SCRATCH_GET_BIOS_SCRATCH(bios_14_scratch) \ + ((bios_14_scratch & BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_14_SCRATCH_SET_BIOS_SCRATCH(bios_14_scratch_reg, bios_scratch) \ + bios_14_scratch_reg = (bios_14_scratch_reg & ~BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_14_scratch_t { + unsigned int bios_scratch : BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_14_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_14_scratch_t { + unsigned int bios_scratch : BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_14_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_14_scratch_t f; +} bios_14_scratch_u; + + +/* + * BIOS_15_SCRATCH struct + */ + +#define BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_15_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_15_SCRATCH_MASK \ + (BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_15_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_15_SCRATCH_GET_BIOS_SCRATCH(bios_15_scratch) \ + ((bios_15_scratch & BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_15_SCRATCH_SET_BIOS_SCRATCH(bios_15_scratch_reg, bios_scratch) \ + bios_15_scratch_reg = (bios_15_scratch_reg & ~BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_15_scratch_t { + unsigned int bios_scratch : BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_15_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_15_scratch_t { + unsigned int bios_scratch : BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_15_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_15_scratch_t f; +} bios_15_scratch_u; + + +/* + * COHER_SIZE_PM4 struct + */ + +#define COHER_SIZE_PM4_SIZE_SIZE 32 + +#define COHER_SIZE_PM4_SIZE_SHIFT 0 + +#define COHER_SIZE_PM4_SIZE_MASK 0xffffffff + +#define COHER_SIZE_PM4_MASK \ + (COHER_SIZE_PM4_SIZE_MASK) + +#define COHER_SIZE_PM4(size) \ + ((size << COHER_SIZE_PM4_SIZE_SHIFT)) + +#define COHER_SIZE_PM4_GET_SIZE(coher_size_pm4) \ + ((coher_size_pm4 & COHER_SIZE_PM4_SIZE_MASK) >> COHER_SIZE_PM4_SIZE_SHIFT) + +#define COHER_SIZE_PM4_SET_SIZE(coher_size_pm4_reg, size) \ + coher_size_pm4_reg = (coher_size_pm4_reg & ~COHER_SIZE_PM4_SIZE_MASK) | (size << COHER_SIZE_PM4_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_size_pm4_t { + unsigned int size : COHER_SIZE_PM4_SIZE_SIZE; + } coher_size_pm4_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_size_pm4_t { + unsigned int size : COHER_SIZE_PM4_SIZE_SIZE; + } coher_size_pm4_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_size_pm4_t f; +} coher_size_pm4_u; + + +/* + * COHER_BASE_PM4 struct + */ + +#define COHER_BASE_PM4_BASE_SIZE 32 + +#define COHER_BASE_PM4_BASE_SHIFT 0 + +#define COHER_BASE_PM4_BASE_MASK 0xffffffff + +#define COHER_BASE_PM4_MASK \ + (COHER_BASE_PM4_BASE_MASK) + +#define COHER_BASE_PM4(base) \ + ((base << COHER_BASE_PM4_BASE_SHIFT)) + +#define COHER_BASE_PM4_GET_BASE(coher_base_pm4) \ + ((coher_base_pm4 & COHER_BASE_PM4_BASE_MASK) >> COHER_BASE_PM4_BASE_SHIFT) + +#define COHER_BASE_PM4_SET_BASE(coher_base_pm4_reg, base) \ + coher_base_pm4_reg = (coher_base_pm4_reg & ~COHER_BASE_PM4_BASE_MASK) | (base << COHER_BASE_PM4_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_base_pm4_t { + unsigned int base : COHER_BASE_PM4_BASE_SIZE; + } coher_base_pm4_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_base_pm4_t { + unsigned int base : COHER_BASE_PM4_BASE_SIZE; + } coher_base_pm4_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_base_pm4_t f; +} coher_base_pm4_u; + + +/* + * COHER_STATUS_PM4 struct + */ + +#define COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE 8 +#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE 1 +#define COHER_STATUS_PM4_TC_ACTION_ENA_SIZE 1 +#define COHER_STATUS_PM4_STATUS_SIZE 1 + +#define COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT 0 +#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT 8 +#define COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT 9 +#define COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT 10 +#define COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT 11 +#define COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT 12 +#define COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT 13 +#define COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT 14 +#define COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT 15 +#define COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT 16 +#define COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT 25 +#define COHER_STATUS_PM4_STATUS_SHIFT 31 + +#define COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK 0x000000ff +#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK 0x00000100 +#define COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK 0x00000200 +#define COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK 0x00000400 +#define COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK 0x00000800 +#define COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK 0x00001000 +#define COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK 0x00002000 +#define COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK 0x00004000 +#define COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK 0x00008000 +#define COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK 0x00010000 +#define COHER_STATUS_PM4_TC_ACTION_ENA_MASK 0x02000000 +#define COHER_STATUS_PM4_STATUS_MASK 0x80000000 + +#define COHER_STATUS_PM4_MASK \ + (COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK | \ + COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK | \ + COHER_STATUS_PM4_TC_ACTION_ENA_MASK | \ + COHER_STATUS_PM4_STATUS_MASK) + +#define COHER_STATUS_PM4(matching_contexts, rb_copy_dest_base_ena, dest_base_0_ena, dest_base_1_ena, dest_base_2_ena, dest_base_3_ena, dest_base_4_ena, dest_base_5_ena, dest_base_6_ena, dest_base_7_ena, tc_action_ena, status) \ + ((matching_contexts << COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT) | \ + (rb_copy_dest_base_ena << COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT) | \ + (dest_base_0_ena << COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT) | \ + (dest_base_1_ena << COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT) | \ + (dest_base_2_ena << COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT) | \ + (dest_base_3_ena << COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT) | \ + (dest_base_4_ena << COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT) | \ + (dest_base_5_ena << COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT) | \ + (dest_base_6_ena << COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT) | \ + (dest_base_7_ena << COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT) | \ + (tc_action_ena << COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT) | \ + (status << COHER_STATUS_PM4_STATUS_SHIFT)) + +#define COHER_STATUS_PM4_GET_MATCHING_CONTEXTS(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK) >> COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT) +#define COHER_STATUS_PM4_GET_RB_COPY_DEST_BASE_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK) >> COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_0_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_1_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_2_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_3_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_4_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_5_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_6_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_7_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_TC_ACTION_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_TC_ACTION_ENA_MASK) >> COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_STATUS(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_STATUS_MASK) >> COHER_STATUS_PM4_STATUS_SHIFT) + +#define COHER_STATUS_PM4_SET_MATCHING_CONTEXTS(coher_status_pm4_reg, matching_contexts) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK) | (matching_contexts << COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT) +#define COHER_STATUS_PM4_SET_RB_COPY_DEST_BASE_ENA(coher_status_pm4_reg, rb_copy_dest_base_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK) | (rb_copy_dest_base_ena << COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_0_ENA(coher_status_pm4_reg, dest_base_0_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK) | (dest_base_0_ena << COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_1_ENA(coher_status_pm4_reg, dest_base_1_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK) | (dest_base_1_ena << COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_2_ENA(coher_status_pm4_reg, dest_base_2_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK) | (dest_base_2_ena << COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_3_ENA(coher_status_pm4_reg, dest_base_3_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK) | (dest_base_3_ena << COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_4_ENA(coher_status_pm4_reg, dest_base_4_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK) | (dest_base_4_ena << COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_5_ENA(coher_status_pm4_reg, dest_base_5_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK) | (dest_base_5_ena << COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_6_ENA(coher_status_pm4_reg, dest_base_6_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK) | (dest_base_6_ena << COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_7_ENA(coher_status_pm4_reg, dest_base_7_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK) | (dest_base_7_ena << COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_TC_ACTION_ENA(coher_status_pm4_reg, tc_action_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_TC_ACTION_ENA_MASK) | (tc_action_ena << COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_STATUS(coher_status_pm4_reg, status) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_STATUS_MASK) | (status << COHER_STATUS_PM4_STATUS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_status_pm4_t { + unsigned int matching_contexts : COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE; + unsigned int rb_copy_dest_base_ena : COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE; + unsigned int dest_base_0_ena : COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE; + unsigned int dest_base_1_ena : COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE; + unsigned int dest_base_2_ena : COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE; + unsigned int dest_base_3_ena : COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE; + unsigned int dest_base_4_ena : COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE; + unsigned int dest_base_5_ena : COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE; + unsigned int dest_base_6_ena : COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE; + unsigned int dest_base_7_ena : COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE; + unsigned int : 8; + unsigned int tc_action_ena : COHER_STATUS_PM4_TC_ACTION_ENA_SIZE; + unsigned int : 5; + unsigned int status : COHER_STATUS_PM4_STATUS_SIZE; + } coher_status_pm4_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_status_pm4_t { + unsigned int status : COHER_STATUS_PM4_STATUS_SIZE; + unsigned int : 5; + unsigned int tc_action_ena : COHER_STATUS_PM4_TC_ACTION_ENA_SIZE; + unsigned int : 8; + unsigned int dest_base_7_ena : COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE; + unsigned int dest_base_6_ena : COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE; + unsigned int dest_base_5_ena : COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE; + unsigned int dest_base_4_ena : COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE; + unsigned int dest_base_3_ena : COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE; + unsigned int dest_base_2_ena : COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE; + unsigned int dest_base_1_ena : COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE; + unsigned int dest_base_0_ena : COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE; + unsigned int rb_copy_dest_base_ena : COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE; + unsigned int matching_contexts : COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE; + } coher_status_pm4_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_status_pm4_t f; +} coher_status_pm4_u; + + +/* + * COHER_SIZE_HOST struct + */ + +#define COHER_SIZE_HOST_SIZE_SIZE 32 + +#define COHER_SIZE_HOST_SIZE_SHIFT 0 + +#define COHER_SIZE_HOST_SIZE_MASK 0xffffffff + +#define COHER_SIZE_HOST_MASK \ + (COHER_SIZE_HOST_SIZE_MASK) + +#define COHER_SIZE_HOST(size) \ + ((size << COHER_SIZE_HOST_SIZE_SHIFT)) + +#define COHER_SIZE_HOST_GET_SIZE(coher_size_host) \ + ((coher_size_host & COHER_SIZE_HOST_SIZE_MASK) >> COHER_SIZE_HOST_SIZE_SHIFT) + +#define COHER_SIZE_HOST_SET_SIZE(coher_size_host_reg, size) \ + coher_size_host_reg = (coher_size_host_reg & ~COHER_SIZE_HOST_SIZE_MASK) | (size << COHER_SIZE_HOST_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_size_host_t { + unsigned int size : COHER_SIZE_HOST_SIZE_SIZE; + } coher_size_host_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_size_host_t { + unsigned int size : COHER_SIZE_HOST_SIZE_SIZE; + } coher_size_host_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_size_host_t f; +} coher_size_host_u; + + +/* + * COHER_BASE_HOST struct + */ + +#define COHER_BASE_HOST_BASE_SIZE 32 + +#define COHER_BASE_HOST_BASE_SHIFT 0 + +#define COHER_BASE_HOST_BASE_MASK 0xffffffff + +#define COHER_BASE_HOST_MASK \ + (COHER_BASE_HOST_BASE_MASK) + +#define COHER_BASE_HOST(base) \ + ((base << COHER_BASE_HOST_BASE_SHIFT)) + +#define COHER_BASE_HOST_GET_BASE(coher_base_host) \ + ((coher_base_host & COHER_BASE_HOST_BASE_MASK) >> COHER_BASE_HOST_BASE_SHIFT) + +#define COHER_BASE_HOST_SET_BASE(coher_base_host_reg, base) \ + coher_base_host_reg = (coher_base_host_reg & ~COHER_BASE_HOST_BASE_MASK) | (base << COHER_BASE_HOST_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_base_host_t { + unsigned int base : COHER_BASE_HOST_BASE_SIZE; + } coher_base_host_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_base_host_t { + unsigned int base : COHER_BASE_HOST_BASE_SIZE; + } coher_base_host_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_base_host_t f; +} coher_base_host_u; + + +/* + * COHER_STATUS_HOST struct + */ + +#define COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE 8 +#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE 1 +#define COHER_STATUS_HOST_TC_ACTION_ENA_SIZE 1 +#define COHER_STATUS_HOST_STATUS_SIZE 1 + +#define COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT 0 +#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT 8 +#define COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT 9 +#define COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT 10 +#define COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT 11 +#define COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT 12 +#define COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT 13 +#define COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT 14 +#define COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT 15 +#define COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT 16 +#define COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT 25 +#define COHER_STATUS_HOST_STATUS_SHIFT 31 + +#define COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK 0x000000ff +#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK 0x00000100 +#define COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK 0x00000200 +#define COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK 0x00000400 +#define COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK 0x00000800 +#define COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK 0x00001000 +#define COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK 0x00002000 +#define COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK 0x00004000 +#define COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK 0x00008000 +#define COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK 0x00010000 +#define COHER_STATUS_HOST_TC_ACTION_ENA_MASK 0x02000000 +#define COHER_STATUS_HOST_STATUS_MASK 0x80000000 + +#define COHER_STATUS_HOST_MASK \ + (COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK | \ + COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK | \ + COHER_STATUS_HOST_TC_ACTION_ENA_MASK | \ + COHER_STATUS_HOST_STATUS_MASK) + +#define COHER_STATUS_HOST(matching_contexts, rb_copy_dest_base_ena, dest_base_0_ena, dest_base_1_ena, dest_base_2_ena, dest_base_3_ena, dest_base_4_ena, dest_base_5_ena, dest_base_6_ena, dest_base_7_ena, tc_action_ena, status) \ + ((matching_contexts << COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT) | \ + (rb_copy_dest_base_ena << COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT) | \ + (dest_base_0_ena << COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT) | \ + (dest_base_1_ena << COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT) | \ + (dest_base_2_ena << COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT) | \ + (dest_base_3_ena << COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT) | \ + (dest_base_4_ena << COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT) | \ + (dest_base_5_ena << COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT) | \ + (dest_base_6_ena << COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT) | \ + (dest_base_7_ena << COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT) | \ + (tc_action_ena << COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT) | \ + (status << COHER_STATUS_HOST_STATUS_SHIFT)) + +#define COHER_STATUS_HOST_GET_MATCHING_CONTEXTS(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK) >> COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT) +#define COHER_STATUS_HOST_GET_RB_COPY_DEST_BASE_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK) >> COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_0_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_1_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_2_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_3_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_4_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_5_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_6_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_7_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_TC_ACTION_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_TC_ACTION_ENA_MASK) >> COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_STATUS(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_STATUS_MASK) >> COHER_STATUS_HOST_STATUS_SHIFT) + +#define COHER_STATUS_HOST_SET_MATCHING_CONTEXTS(coher_status_host_reg, matching_contexts) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK) | (matching_contexts << COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT) +#define COHER_STATUS_HOST_SET_RB_COPY_DEST_BASE_ENA(coher_status_host_reg, rb_copy_dest_base_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK) | (rb_copy_dest_base_ena << COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_0_ENA(coher_status_host_reg, dest_base_0_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK) | (dest_base_0_ena << COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_1_ENA(coher_status_host_reg, dest_base_1_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK) | (dest_base_1_ena << COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_2_ENA(coher_status_host_reg, dest_base_2_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK) | (dest_base_2_ena << COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_3_ENA(coher_status_host_reg, dest_base_3_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK) | (dest_base_3_ena << COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_4_ENA(coher_status_host_reg, dest_base_4_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK) | (dest_base_4_ena << COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_5_ENA(coher_status_host_reg, dest_base_5_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK) | (dest_base_5_ena << COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_6_ENA(coher_status_host_reg, dest_base_6_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK) | (dest_base_6_ena << COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_7_ENA(coher_status_host_reg, dest_base_7_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK) | (dest_base_7_ena << COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_TC_ACTION_ENA(coher_status_host_reg, tc_action_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_TC_ACTION_ENA_MASK) | (tc_action_ena << COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_STATUS(coher_status_host_reg, status) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_STATUS_MASK) | (status << COHER_STATUS_HOST_STATUS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_status_host_t { + unsigned int matching_contexts : COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE; + unsigned int rb_copy_dest_base_ena : COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE; + unsigned int dest_base_0_ena : COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE; + unsigned int dest_base_1_ena : COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE; + unsigned int dest_base_2_ena : COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE; + unsigned int dest_base_3_ena : COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE; + unsigned int dest_base_4_ena : COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE; + unsigned int dest_base_5_ena : COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE; + unsigned int dest_base_6_ena : COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE; + unsigned int dest_base_7_ena : COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE; + unsigned int : 8; + unsigned int tc_action_ena : COHER_STATUS_HOST_TC_ACTION_ENA_SIZE; + unsigned int : 5; + unsigned int status : COHER_STATUS_HOST_STATUS_SIZE; + } coher_status_host_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_status_host_t { + unsigned int status : COHER_STATUS_HOST_STATUS_SIZE; + unsigned int : 5; + unsigned int tc_action_ena : COHER_STATUS_HOST_TC_ACTION_ENA_SIZE; + unsigned int : 8; + unsigned int dest_base_7_ena : COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE; + unsigned int dest_base_6_ena : COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE; + unsigned int dest_base_5_ena : COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE; + unsigned int dest_base_4_ena : COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE; + unsigned int dest_base_3_ena : COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE; + unsigned int dest_base_2_ena : COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE; + unsigned int dest_base_1_ena : COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE; + unsigned int dest_base_0_ena : COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE; + unsigned int rb_copy_dest_base_ena : COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE; + unsigned int matching_contexts : COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE; + } coher_status_host_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_status_host_t f; +} coher_status_host_u; + + +/* + * COHER_DEST_BASE_0 struct + */ + +#define COHER_DEST_BASE_0_DEST_BASE_0_SIZE 20 + +#define COHER_DEST_BASE_0_DEST_BASE_0_SHIFT 12 + +#define COHER_DEST_BASE_0_DEST_BASE_0_MASK 0xfffff000 + +#define COHER_DEST_BASE_0_MASK \ + (COHER_DEST_BASE_0_DEST_BASE_0_MASK) + +#define COHER_DEST_BASE_0(dest_base_0) \ + ((dest_base_0 << COHER_DEST_BASE_0_DEST_BASE_0_SHIFT)) + +#define COHER_DEST_BASE_0_GET_DEST_BASE_0(coher_dest_base_0) \ + ((coher_dest_base_0 & COHER_DEST_BASE_0_DEST_BASE_0_MASK) >> COHER_DEST_BASE_0_DEST_BASE_0_SHIFT) + +#define COHER_DEST_BASE_0_SET_DEST_BASE_0(coher_dest_base_0_reg, dest_base_0) \ + coher_dest_base_0_reg = (coher_dest_base_0_reg & ~COHER_DEST_BASE_0_DEST_BASE_0_MASK) | (dest_base_0 << COHER_DEST_BASE_0_DEST_BASE_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_0_t { + unsigned int : 12; + unsigned int dest_base_0 : COHER_DEST_BASE_0_DEST_BASE_0_SIZE; + } coher_dest_base_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_0_t { + unsigned int dest_base_0 : COHER_DEST_BASE_0_DEST_BASE_0_SIZE; + unsigned int : 12; + } coher_dest_base_0_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_0_t f; +} coher_dest_base_0_u; + + +/* + * COHER_DEST_BASE_1 struct + */ + +#define COHER_DEST_BASE_1_DEST_BASE_1_SIZE 20 + +#define COHER_DEST_BASE_1_DEST_BASE_1_SHIFT 12 + +#define COHER_DEST_BASE_1_DEST_BASE_1_MASK 0xfffff000 + +#define COHER_DEST_BASE_1_MASK \ + (COHER_DEST_BASE_1_DEST_BASE_1_MASK) + +#define COHER_DEST_BASE_1(dest_base_1) \ + ((dest_base_1 << COHER_DEST_BASE_1_DEST_BASE_1_SHIFT)) + +#define COHER_DEST_BASE_1_GET_DEST_BASE_1(coher_dest_base_1) \ + ((coher_dest_base_1 & COHER_DEST_BASE_1_DEST_BASE_1_MASK) >> COHER_DEST_BASE_1_DEST_BASE_1_SHIFT) + +#define COHER_DEST_BASE_1_SET_DEST_BASE_1(coher_dest_base_1_reg, dest_base_1) \ + coher_dest_base_1_reg = (coher_dest_base_1_reg & ~COHER_DEST_BASE_1_DEST_BASE_1_MASK) | (dest_base_1 << COHER_DEST_BASE_1_DEST_BASE_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_1_t { + unsigned int : 12; + unsigned int dest_base_1 : COHER_DEST_BASE_1_DEST_BASE_1_SIZE; + } coher_dest_base_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_1_t { + unsigned int dest_base_1 : COHER_DEST_BASE_1_DEST_BASE_1_SIZE; + unsigned int : 12; + } coher_dest_base_1_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_1_t f; +} coher_dest_base_1_u; + + +/* + * COHER_DEST_BASE_2 struct + */ + +#define COHER_DEST_BASE_2_DEST_BASE_2_SIZE 20 + +#define COHER_DEST_BASE_2_DEST_BASE_2_SHIFT 12 + +#define COHER_DEST_BASE_2_DEST_BASE_2_MASK 0xfffff000 + +#define COHER_DEST_BASE_2_MASK \ + (COHER_DEST_BASE_2_DEST_BASE_2_MASK) + +#define COHER_DEST_BASE_2(dest_base_2) \ + ((dest_base_2 << COHER_DEST_BASE_2_DEST_BASE_2_SHIFT)) + +#define COHER_DEST_BASE_2_GET_DEST_BASE_2(coher_dest_base_2) \ + ((coher_dest_base_2 & COHER_DEST_BASE_2_DEST_BASE_2_MASK) >> COHER_DEST_BASE_2_DEST_BASE_2_SHIFT) + +#define COHER_DEST_BASE_2_SET_DEST_BASE_2(coher_dest_base_2_reg, dest_base_2) \ + coher_dest_base_2_reg = (coher_dest_base_2_reg & ~COHER_DEST_BASE_2_DEST_BASE_2_MASK) | (dest_base_2 << COHER_DEST_BASE_2_DEST_BASE_2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_2_t { + unsigned int : 12; + unsigned int dest_base_2 : COHER_DEST_BASE_2_DEST_BASE_2_SIZE; + } coher_dest_base_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_2_t { + unsigned int dest_base_2 : COHER_DEST_BASE_2_DEST_BASE_2_SIZE; + unsigned int : 12; + } coher_dest_base_2_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_2_t f; +} coher_dest_base_2_u; + + +/* + * COHER_DEST_BASE_3 struct + */ + +#define COHER_DEST_BASE_3_DEST_BASE_3_SIZE 20 + +#define COHER_DEST_BASE_3_DEST_BASE_3_SHIFT 12 + +#define COHER_DEST_BASE_3_DEST_BASE_3_MASK 0xfffff000 + +#define COHER_DEST_BASE_3_MASK \ + (COHER_DEST_BASE_3_DEST_BASE_3_MASK) + +#define COHER_DEST_BASE_3(dest_base_3) \ + ((dest_base_3 << COHER_DEST_BASE_3_DEST_BASE_3_SHIFT)) + +#define COHER_DEST_BASE_3_GET_DEST_BASE_3(coher_dest_base_3) \ + ((coher_dest_base_3 & COHER_DEST_BASE_3_DEST_BASE_3_MASK) >> COHER_DEST_BASE_3_DEST_BASE_3_SHIFT) + +#define COHER_DEST_BASE_3_SET_DEST_BASE_3(coher_dest_base_3_reg, dest_base_3) \ + coher_dest_base_3_reg = (coher_dest_base_3_reg & ~COHER_DEST_BASE_3_DEST_BASE_3_MASK) | (dest_base_3 << COHER_DEST_BASE_3_DEST_BASE_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_3_t { + unsigned int : 12; + unsigned int dest_base_3 : COHER_DEST_BASE_3_DEST_BASE_3_SIZE; + } coher_dest_base_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_3_t { + unsigned int dest_base_3 : COHER_DEST_BASE_3_DEST_BASE_3_SIZE; + unsigned int : 12; + } coher_dest_base_3_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_3_t f; +} coher_dest_base_3_u; + + +/* + * COHER_DEST_BASE_4 struct + */ + +#define COHER_DEST_BASE_4_DEST_BASE_4_SIZE 20 + +#define COHER_DEST_BASE_4_DEST_BASE_4_SHIFT 12 + +#define COHER_DEST_BASE_4_DEST_BASE_4_MASK 0xfffff000 + +#define COHER_DEST_BASE_4_MASK \ + (COHER_DEST_BASE_4_DEST_BASE_4_MASK) + +#define COHER_DEST_BASE_4(dest_base_4) \ + ((dest_base_4 << COHER_DEST_BASE_4_DEST_BASE_4_SHIFT)) + +#define COHER_DEST_BASE_4_GET_DEST_BASE_4(coher_dest_base_4) \ + ((coher_dest_base_4 & COHER_DEST_BASE_4_DEST_BASE_4_MASK) >> COHER_DEST_BASE_4_DEST_BASE_4_SHIFT) + +#define COHER_DEST_BASE_4_SET_DEST_BASE_4(coher_dest_base_4_reg, dest_base_4) \ + coher_dest_base_4_reg = (coher_dest_base_4_reg & ~COHER_DEST_BASE_4_DEST_BASE_4_MASK) | (dest_base_4 << COHER_DEST_BASE_4_DEST_BASE_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_4_t { + unsigned int : 12; + unsigned int dest_base_4 : COHER_DEST_BASE_4_DEST_BASE_4_SIZE; + } coher_dest_base_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_4_t { + unsigned int dest_base_4 : COHER_DEST_BASE_4_DEST_BASE_4_SIZE; + unsigned int : 12; + } coher_dest_base_4_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_4_t f; +} coher_dest_base_4_u; + + +/* + * COHER_DEST_BASE_5 struct + */ + +#define COHER_DEST_BASE_5_DEST_BASE_5_SIZE 20 + +#define COHER_DEST_BASE_5_DEST_BASE_5_SHIFT 12 + +#define COHER_DEST_BASE_5_DEST_BASE_5_MASK 0xfffff000 + +#define COHER_DEST_BASE_5_MASK \ + (COHER_DEST_BASE_5_DEST_BASE_5_MASK) + +#define COHER_DEST_BASE_5(dest_base_5) \ + ((dest_base_5 << COHER_DEST_BASE_5_DEST_BASE_5_SHIFT)) + +#define COHER_DEST_BASE_5_GET_DEST_BASE_5(coher_dest_base_5) \ + ((coher_dest_base_5 & COHER_DEST_BASE_5_DEST_BASE_5_MASK) >> COHER_DEST_BASE_5_DEST_BASE_5_SHIFT) + +#define COHER_DEST_BASE_5_SET_DEST_BASE_5(coher_dest_base_5_reg, dest_base_5) \ + coher_dest_base_5_reg = (coher_dest_base_5_reg & ~COHER_DEST_BASE_5_DEST_BASE_5_MASK) | (dest_base_5 << COHER_DEST_BASE_5_DEST_BASE_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_5_t { + unsigned int : 12; + unsigned int dest_base_5 : COHER_DEST_BASE_5_DEST_BASE_5_SIZE; + } coher_dest_base_5_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_5_t { + unsigned int dest_base_5 : COHER_DEST_BASE_5_DEST_BASE_5_SIZE; + unsigned int : 12; + } coher_dest_base_5_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_5_t f; +} coher_dest_base_5_u; + + +/* + * COHER_DEST_BASE_6 struct + */ + +#define COHER_DEST_BASE_6_DEST_BASE_6_SIZE 20 + +#define COHER_DEST_BASE_6_DEST_BASE_6_SHIFT 12 + +#define COHER_DEST_BASE_6_DEST_BASE_6_MASK 0xfffff000 + +#define COHER_DEST_BASE_6_MASK \ + (COHER_DEST_BASE_6_DEST_BASE_6_MASK) + +#define COHER_DEST_BASE_6(dest_base_6) \ + ((dest_base_6 << COHER_DEST_BASE_6_DEST_BASE_6_SHIFT)) + +#define COHER_DEST_BASE_6_GET_DEST_BASE_6(coher_dest_base_6) \ + ((coher_dest_base_6 & COHER_DEST_BASE_6_DEST_BASE_6_MASK) >> COHER_DEST_BASE_6_DEST_BASE_6_SHIFT) + +#define COHER_DEST_BASE_6_SET_DEST_BASE_6(coher_dest_base_6_reg, dest_base_6) \ + coher_dest_base_6_reg = (coher_dest_base_6_reg & ~COHER_DEST_BASE_6_DEST_BASE_6_MASK) | (dest_base_6 << COHER_DEST_BASE_6_DEST_BASE_6_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_6_t { + unsigned int : 12; + unsigned int dest_base_6 : COHER_DEST_BASE_6_DEST_BASE_6_SIZE; + } coher_dest_base_6_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_6_t { + unsigned int dest_base_6 : COHER_DEST_BASE_6_DEST_BASE_6_SIZE; + unsigned int : 12; + } coher_dest_base_6_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_6_t f; +} coher_dest_base_6_u; + + +/* + * COHER_DEST_BASE_7 struct + */ + +#define COHER_DEST_BASE_7_DEST_BASE_7_SIZE 20 + +#define COHER_DEST_BASE_7_DEST_BASE_7_SHIFT 12 + +#define COHER_DEST_BASE_7_DEST_BASE_7_MASK 0xfffff000 + +#define COHER_DEST_BASE_7_MASK \ + (COHER_DEST_BASE_7_DEST_BASE_7_MASK) + +#define COHER_DEST_BASE_7(dest_base_7) \ + ((dest_base_7 << COHER_DEST_BASE_7_DEST_BASE_7_SHIFT)) + +#define COHER_DEST_BASE_7_GET_DEST_BASE_7(coher_dest_base_7) \ + ((coher_dest_base_7 & COHER_DEST_BASE_7_DEST_BASE_7_MASK) >> COHER_DEST_BASE_7_DEST_BASE_7_SHIFT) + +#define COHER_DEST_BASE_7_SET_DEST_BASE_7(coher_dest_base_7_reg, dest_base_7) \ + coher_dest_base_7_reg = (coher_dest_base_7_reg & ~COHER_DEST_BASE_7_DEST_BASE_7_MASK) | (dest_base_7 << COHER_DEST_BASE_7_DEST_BASE_7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_7_t { + unsigned int : 12; + unsigned int dest_base_7 : COHER_DEST_BASE_7_DEST_BASE_7_SIZE; + } coher_dest_base_7_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_7_t { + unsigned int dest_base_7 : COHER_DEST_BASE_7_DEST_BASE_7_SIZE; + unsigned int : 12; + } coher_dest_base_7_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_7_t f; +} coher_dest_base_7_u; + + +#endif + + +#if !defined (_RBBM_FIDDLE_H) +#define _RBBM_FIDDLE_H + +/***************************************************************************************************************** + * + * rbbm_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * WAIT_UNTIL struct + */ + +#define WAIT_UNTIL_WAIT_RE_VSYNC_SIZE 1 +#define WAIT_UNTIL_WAIT_FE_VSYNC_SIZE 1 +#define WAIT_UNTIL_WAIT_VSYNC_SIZE 1 +#define WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE 1 +#define WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE 1 +#define WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE 1 +#define WAIT_UNTIL_WAIT_CMDFIFO_SIZE 1 +#define WAIT_UNTIL_WAIT_2D_IDLE_SIZE 1 +#define WAIT_UNTIL_WAIT_3D_IDLE_SIZE 1 +#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE 1 +#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE 1 +#define WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE 4 + +#define WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT 1 +#define WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT 2 +#define WAIT_UNTIL_WAIT_VSYNC_SHIFT 3 +#define WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT 4 +#define WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT 5 +#define WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT 6 +#define WAIT_UNTIL_WAIT_CMDFIFO_SHIFT 10 +#define WAIT_UNTIL_WAIT_2D_IDLE_SHIFT 14 +#define WAIT_UNTIL_WAIT_3D_IDLE_SHIFT 15 +#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT 16 +#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT 17 +#define WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT 20 + +#define WAIT_UNTIL_WAIT_RE_VSYNC_MASK 0x00000002 +#define WAIT_UNTIL_WAIT_FE_VSYNC_MASK 0x00000004 +#define WAIT_UNTIL_WAIT_VSYNC_MASK 0x00000008 +#define WAIT_UNTIL_WAIT_DSPLY_ID0_MASK 0x00000010 +#define WAIT_UNTIL_WAIT_DSPLY_ID1_MASK 0x00000020 +#define WAIT_UNTIL_WAIT_DSPLY_ID2_MASK 0x00000040 +#define WAIT_UNTIL_WAIT_CMDFIFO_MASK 0x00000400 +#define WAIT_UNTIL_WAIT_2D_IDLE_MASK 0x00004000 +#define WAIT_UNTIL_WAIT_3D_IDLE_MASK 0x00008000 +#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK 0x00010000 +#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK 0x00020000 +#define WAIT_UNTIL_CMDFIFO_ENTRIES_MASK 0x00f00000 + +#define WAIT_UNTIL_MASK \ + (WAIT_UNTIL_WAIT_RE_VSYNC_MASK | \ + WAIT_UNTIL_WAIT_FE_VSYNC_MASK | \ + WAIT_UNTIL_WAIT_VSYNC_MASK | \ + WAIT_UNTIL_WAIT_DSPLY_ID0_MASK | \ + WAIT_UNTIL_WAIT_DSPLY_ID1_MASK | \ + WAIT_UNTIL_WAIT_DSPLY_ID2_MASK | \ + WAIT_UNTIL_WAIT_CMDFIFO_MASK | \ + WAIT_UNTIL_WAIT_2D_IDLE_MASK | \ + WAIT_UNTIL_WAIT_3D_IDLE_MASK | \ + WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK | \ + WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK | \ + WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) + +#define WAIT_UNTIL(wait_re_vsync, wait_fe_vsync, wait_vsync, wait_dsply_id0, wait_dsply_id1, wait_dsply_id2, wait_cmdfifo, wait_2d_idle, wait_3d_idle, wait_2d_idleclean, wait_3d_idleclean, cmdfifo_entries) \ + ((wait_re_vsync << WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT) | \ + (wait_fe_vsync << WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT) | \ + (wait_vsync << WAIT_UNTIL_WAIT_VSYNC_SHIFT) | \ + (wait_dsply_id0 << WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT) | \ + (wait_dsply_id1 << WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT) | \ + (wait_dsply_id2 << WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT) | \ + (wait_cmdfifo << WAIT_UNTIL_WAIT_CMDFIFO_SHIFT) | \ + (wait_2d_idle << WAIT_UNTIL_WAIT_2D_IDLE_SHIFT) | \ + (wait_3d_idle << WAIT_UNTIL_WAIT_3D_IDLE_SHIFT) | \ + (wait_2d_idleclean << WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT) | \ + (wait_3d_idleclean << WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT) | \ + (cmdfifo_entries << WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT)) + +#define WAIT_UNTIL_GET_WAIT_RE_VSYNC(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_RE_VSYNC_MASK) >> WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT) +#define WAIT_UNTIL_GET_WAIT_FE_VSYNC(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_FE_VSYNC_MASK) >> WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT) +#define WAIT_UNTIL_GET_WAIT_VSYNC(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_VSYNC_MASK) >> WAIT_UNTIL_WAIT_VSYNC_SHIFT) +#define WAIT_UNTIL_GET_WAIT_DSPLY_ID0(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID0_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT) +#define WAIT_UNTIL_GET_WAIT_DSPLY_ID1(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID1_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT) +#define WAIT_UNTIL_GET_WAIT_DSPLY_ID2(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID2_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT) +#define WAIT_UNTIL_GET_WAIT_CMDFIFO(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_CMDFIFO_MASK) >> WAIT_UNTIL_WAIT_CMDFIFO_SHIFT) +#define WAIT_UNTIL_GET_WAIT_2D_IDLE(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_2D_IDLE_MASK) >> WAIT_UNTIL_WAIT_2D_IDLE_SHIFT) +#define WAIT_UNTIL_GET_WAIT_3D_IDLE(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_3D_IDLE_MASK) >> WAIT_UNTIL_WAIT_3D_IDLE_SHIFT) +#define WAIT_UNTIL_GET_WAIT_2D_IDLECLEAN(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK) >> WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT) +#define WAIT_UNTIL_GET_WAIT_3D_IDLECLEAN(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK) >> WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT) +#define WAIT_UNTIL_GET_CMDFIFO_ENTRIES(wait_until) \ + ((wait_until & WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) >> WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT) + +#define WAIT_UNTIL_SET_WAIT_RE_VSYNC(wait_until_reg, wait_re_vsync) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_RE_VSYNC_MASK) | (wait_re_vsync << WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT) +#define WAIT_UNTIL_SET_WAIT_FE_VSYNC(wait_until_reg, wait_fe_vsync) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_FE_VSYNC_MASK) | (wait_fe_vsync << WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT) +#define WAIT_UNTIL_SET_WAIT_VSYNC(wait_until_reg, wait_vsync) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_VSYNC_MASK) | (wait_vsync << WAIT_UNTIL_WAIT_VSYNC_SHIFT) +#define WAIT_UNTIL_SET_WAIT_DSPLY_ID0(wait_until_reg, wait_dsply_id0) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID0_MASK) | (wait_dsply_id0 << WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT) +#define WAIT_UNTIL_SET_WAIT_DSPLY_ID1(wait_until_reg, wait_dsply_id1) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID1_MASK) | (wait_dsply_id1 << WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT) +#define WAIT_UNTIL_SET_WAIT_DSPLY_ID2(wait_until_reg, wait_dsply_id2) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID2_MASK) | (wait_dsply_id2 << WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT) +#define WAIT_UNTIL_SET_WAIT_CMDFIFO(wait_until_reg, wait_cmdfifo) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_CMDFIFO_MASK) | (wait_cmdfifo << WAIT_UNTIL_WAIT_CMDFIFO_SHIFT) +#define WAIT_UNTIL_SET_WAIT_2D_IDLE(wait_until_reg, wait_2d_idle) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_2D_IDLE_MASK) | (wait_2d_idle << WAIT_UNTIL_WAIT_2D_IDLE_SHIFT) +#define WAIT_UNTIL_SET_WAIT_3D_IDLE(wait_until_reg, wait_3d_idle) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_3D_IDLE_MASK) | (wait_3d_idle << WAIT_UNTIL_WAIT_3D_IDLE_SHIFT) +#define WAIT_UNTIL_SET_WAIT_2D_IDLECLEAN(wait_until_reg, wait_2d_idleclean) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK) | (wait_2d_idleclean << WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT) +#define WAIT_UNTIL_SET_WAIT_3D_IDLECLEAN(wait_until_reg, wait_3d_idleclean) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK) | (wait_3d_idleclean << WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT) +#define WAIT_UNTIL_SET_CMDFIFO_ENTRIES(wait_until_reg, cmdfifo_entries) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) | (cmdfifo_entries << WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _wait_until_t { + unsigned int : 1; + unsigned int wait_re_vsync : WAIT_UNTIL_WAIT_RE_VSYNC_SIZE; + unsigned int wait_fe_vsync : WAIT_UNTIL_WAIT_FE_VSYNC_SIZE; + unsigned int wait_vsync : WAIT_UNTIL_WAIT_VSYNC_SIZE; + unsigned int wait_dsply_id0 : WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE; + unsigned int wait_dsply_id1 : WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE; + unsigned int wait_dsply_id2 : WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE; + unsigned int : 3; + unsigned int wait_cmdfifo : WAIT_UNTIL_WAIT_CMDFIFO_SIZE; + unsigned int : 3; + unsigned int wait_2d_idle : WAIT_UNTIL_WAIT_2D_IDLE_SIZE; + unsigned int wait_3d_idle : WAIT_UNTIL_WAIT_3D_IDLE_SIZE; + unsigned int wait_2d_idleclean : WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE; + unsigned int wait_3d_idleclean : WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE; + unsigned int : 2; + unsigned int cmdfifo_entries : WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE; + unsigned int : 8; + } wait_until_t; + +#else // !BIGENDIAN_OS + + typedef struct _wait_until_t { + unsigned int : 8; + unsigned int cmdfifo_entries : WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE; + unsigned int : 2; + unsigned int wait_3d_idleclean : WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE; + unsigned int wait_2d_idleclean : WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE; + unsigned int wait_3d_idle : WAIT_UNTIL_WAIT_3D_IDLE_SIZE; + unsigned int wait_2d_idle : WAIT_UNTIL_WAIT_2D_IDLE_SIZE; + unsigned int : 3; + unsigned int wait_cmdfifo : WAIT_UNTIL_WAIT_CMDFIFO_SIZE; + unsigned int : 3; + unsigned int wait_dsply_id2 : WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE; + unsigned int wait_dsply_id1 : WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE; + unsigned int wait_dsply_id0 : WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE; + unsigned int wait_vsync : WAIT_UNTIL_WAIT_VSYNC_SIZE; + unsigned int wait_fe_vsync : WAIT_UNTIL_WAIT_FE_VSYNC_SIZE; + unsigned int wait_re_vsync : WAIT_UNTIL_WAIT_RE_VSYNC_SIZE; + unsigned int : 1; + } wait_until_t; + +#endif + +typedef union { + unsigned int val : 32; + wait_until_t f; +} wait_until_u; + + +/* + * RBBM_ISYNC_CNTL struct + */ + +#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE 1 +#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE 1 + +#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT 4 +#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT 5 + +#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK 0x00000010 +#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK 0x00000020 + +#define RBBM_ISYNC_CNTL_MASK \ + (RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK | \ + RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) + +#define RBBM_ISYNC_CNTL(isync_wait_idlegui, isync_cpscratch_idlegui) \ + ((isync_wait_idlegui << RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT) | \ + (isync_cpscratch_idlegui << RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT)) + +#define RBBM_ISYNC_CNTL_GET_ISYNC_WAIT_IDLEGUI(rbbm_isync_cntl) \ + ((rbbm_isync_cntl & RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK) >> RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT) +#define RBBM_ISYNC_CNTL_GET_ISYNC_CPSCRATCH_IDLEGUI(rbbm_isync_cntl) \ + ((rbbm_isync_cntl & RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) >> RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT) + +#define RBBM_ISYNC_CNTL_SET_ISYNC_WAIT_IDLEGUI(rbbm_isync_cntl_reg, isync_wait_idlegui) \ + rbbm_isync_cntl_reg = (rbbm_isync_cntl_reg & ~RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK) | (isync_wait_idlegui << RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT) +#define RBBM_ISYNC_CNTL_SET_ISYNC_CPSCRATCH_IDLEGUI(rbbm_isync_cntl_reg, isync_cpscratch_idlegui) \ + rbbm_isync_cntl_reg = (rbbm_isync_cntl_reg & ~RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) | (isync_cpscratch_idlegui << RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_isync_cntl_t { + unsigned int : 4; + unsigned int isync_wait_idlegui : RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE; + unsigned int isync_cpscratch_idlegui : RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE; + unsigned int : 26; + } rbbm_isync_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_isync_cntl_t { + unsigned int : 26; + unsigned int isync_cpscratch_idlegui : RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE; + unsigned int isync_wait_idlegui : RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE; + unsigned int : 4; + } rbbm_isync_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_isync_cntl_t f; +} rbbm_isync_cntl_u; + + +/* + * RBBM_STATUS struct + */ + +#define RBBM_STATUS_CMDFIFO_AVAIL_SIZE 5 +#define RBBM_STATUS_TC_BUSY_SIZE 1 +#define RBBM_STATUS_HIRQ_PENDING_SIZE 1 +#define RBBM_STATUS_CPRQ_PENDING_SIZE 1 +#define RBBM_STATUS_CFRQ_PENDING_SIZE 1 +#define RBBM_STATUS_PFRQ_PENDING_SIZE 1 +#define RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE 1 +#define RBBM_STATUS_RBBM_WU_BUSY_SIZE 1 +#define RBBM_STATUS_CP_NRT_BUSY_SIZE 1 +#define RBBM_STATUS_MH_BUSY_SIZE 1 +#define RBBM_STATUS_MH_COHERENCY_BUSY_SIZE 1 +#define RBBM_STATUS_SX_BUSY_SIZE 1 +#define RBBM_STATUS_TPC_BUSY_SIZE 1 +#define RBBM_STATUS_SC_CNTX_BUSY_SIZE 1 +#define RBBM_STATUS_PA_BUSY_SIZE 1 +#define RBBM_STATUS_VGT_BUSY_SIZE 1 +#define RBBM_STATUS_SQ_CNTX17_BUSY_SIZE 1 +#define RBBM_STATUS_SQ_CNTX0_BUSY_SIZE 1 +#define RBBM_STATUS_RB_CNTX_BUSY_SIZE 1 +#define RBBM_STATUS_GUI_ACTIVE_SIZE 1 + +#define RBBM_STATUS_CMDFIFO_AVAIL_SHIFT 0 +#define RBBM_STATUS_TC_BUSY_SHIFT 5 +#define RBBM_STATUS_HIRQ_PENDING_SHIFT 8 +#define RBBM_STATUS_CPRQ_PENDING_SHIFT 9 +#define RBBM_STATUS_CFRQ_PENDING_SHIFT 10 +#define RBBM_STATUS_PFRQ_PENDING_SHIFT 11 +#define RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT 12 +#define RBBM_STATUS_RBBM_WU_BUSY_SHIFT 14 +#define RBBM_STATUS_CP_NRT_BUSY_SHIFT 16 +#define RBBM_STATUS_MH_BUSY_SHIFT 18 +#define RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT 19 +#define RBBM_STATUS_SX_BUSY_SHIFT 21 +#define RBBM_STATUS_TPC_BUSY_SHIFT 22 +#define RBBM_STATUS_SC_CNTX_BUSY_SHIFT 24 +#define RBBM_STATUS_PA_BUSY_SHIFT 25 +#define RBBM_STATUS_VGT_BUSY_SHIFT 26 +#define RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT 27 +#define RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT 28 +#define RBBM_STATUS_RB_CNTX_BUSY_SHIFT 30 +#define RBBM_STATUS_GUI_ACTIVE_SHIFT 31 + +#define RBBM_STATUS_CMDFIFO_AVAIL_MASK 0x0000001f +#define RBBM_STATUS_TC_BUSY_MASK 0x00000020 +#define RBBM_STATUS_HIRQ_PENDING_MASK 0x00000100 +#define RBBM_STATUS_CPRQ_PENDING_MASK 0x00000200 +#define RBBM_STATUS_CFRQ_PENDING_MASK 0x00000400 +#define RBBM_STATUS_PFRQ_PENDING_MASK 0x00000800 +#define RBBM_STATUS_VGT_BUSY_NO_DMA_MASK 0x00001000 +#define RBBM_STATUS_RBBM_WU_BUSY_MASK 0x00004000 +#define RBBM_STATUS_CP_NRT_BUSY_MASK 0x00010000 +#define RBBM_STATUS_MH_BUSY_MASK 0x00040000 +#define RBBM_STATUS_MH_COHERENCY_BUSY_MASK 0x00080000 +#define RBBM_STATUS_SX_BUSY_MASK 0x00200000 +#define RBBM_STATUS_TPC_BUSY_MASK 0x00400000 +#define RBBM_STATUS_SC_CNTX_BUSY_MASK 0x01000000 +#define RBBM_STATUS_PA_BUSY_MASK 0x02000000 +#define RBBM_STATUS_VGT_BUSY_MASK 0x04000000 +#define RBBM_STATUS_SQ_CNTX17_BUSY_MASK 0x08000000 +#define RBBM_STATUS_SQ_CNTX0_BUSY_MASK 0x10000000 +#define RBBM_STATUS_RB_CNTX_BUSY_MASK 0x40000000 +#define RBBM_STATUS_GUI_ACTIVE_MASK 0x80000000 + +#define RBBM_STATUS_MASK \ + (RBBM_STATUS_CMDFIFO_AVAIL_MASK | \ + RBBM_STATUS_TC_BUSY_MASK | \ + RBBM_STATUS_HIRQ_PENDING_MASK | \ + RBBM_STATUS_CPRQ_PENDING_MASK | \ + RBBM_STATUS_CFRQ_PENDING_MASK | \ + RBBM_STATUS_PFRQ_PENDING_MASK | \ + RBBM_STATUS_VGT_BUSY_NO_DMA_MASK | \ + RBBM_STATUS_RBBM_WU_BUSY_MASK | \ + RBBM_STATUS_CP_NRT_BUSY_MASK | \ + RBBM_STATUS_MH_BUSY_MASK | \ + RBBM_STATUS_MH_COHERENCY_BUSY_MASK | \ + RBBM_STATUS_SX_BUSY_MASK | \ + RBBM_STATUS_TPC_BUSY_MASK | \ + RBBM_STATUS_SC_CNTX_BUSY_MASK | \ + RBBM_STATUS_PA_BUSY_MASK | \ + RBBM_STATUS_VGT_BUSY_MASK | \ + RBBM_STATUS_SQ_CNTX17_BUSY_MASK | \ + RBBM_STATUS_SQ_CNTX0_BUSY_MASK | \ + RBBM_STATUS_RB_CNTX_BUSY_MASK | \ + RBBM_STATUS_GUI_ACTIVE_MASK) + +#define RBBM_STATUS(cmdfifo_avail, tc_busy, hirq_pending, cprq_pending, cfrq_pending, pfrq_pending, vgt_busy_no_dma, rbbm_wu_busy, cp_nrt_busy, mh_busy, mh_coherency_busy, sx_busy, tpc_busy, sc_cntx_busy, pa_busy, vgt_busy, sq_cntx17_busy, sq_cntx0_busy, rb_cntx_busy, gui_active) \ + ((cmdfifo_avail << RBBM_STATUS_CMDFIFO_AVAIL_SHIFT) | \ + (tc_busy << RBBM_STATUS_TC_BUSY_SHIFT) | \ + (hirq_pending << RBBM_STATUS_HIRQ_PENDING_SHIFT) | \ + (cprq_pending << RBBM_STATUS_CPRQ_PENDING_SHIFT) | \ + (cfrq_pending << RBBM_STATUS_CFRQ_PENDING_SHIFT) | \ + (pfrq_pending << RBBM_STATUS_PFRQ_PENDING_SHIFT) | \ + (vgt_busy_no_dma << RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT) | \ + (rbbm_wu_busy << RBBM_STATUS_RBBM_WU_BUSY_SHIFT) | \ + (cp_nrt_busy << RBBM_STATUS_CP_NRT_BUSY_SHIFT) | \ + (mh_busy << RBBM_STATUS_MH_BUSY_SHIFT) | \ + (mh_coherency_busy << RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT) | \ + (sx_busy << RBBM_STATUS_SX_BUSY_SHIFT) | \ + (tpc_busy << RBBM_STATUS_TPC_BUSY_SHIFT) | \ + (sc_cntx_busy << RBBM_STATUS_SC_CNTX_BUSY_SHIFT) | \ + (pa_busy << RBBM_STATUS_PA_BUSY_SHIFT) | \ + (vgt_busy << RBBM_STATUS_VGT_BUSY_SHIFT) | \ + (sq_cntx17_busy << RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT) | \ + (sq_cntx0_busy << RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT) | \ + (rb_cntx_busy << RBBM_STATUS_RB_CNTX_BUSY_SHIFT) | \ + (gui_active << RBBM_STATUS_GUI_ACTIVE_SHIFT)) + +#define RBBM_STATUS_GET_CMDFIFO_AVAIL(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_CMDFIFO_AVAIL_MASK) >> RBBM_STATUS_CMDFIFO_AVAIL_SHIFT) +#define RBBM_STATUS_GET_TC_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_TC_BUSY_MASK) >> RBBM_STATUS_TC_BUSY_SHIFT) +#define RBBM_STATUS_GET_HIRQ_PENDING(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_HIRQ_PENDING_MASK) >> RBBM_STATUS_HIRQ_PENDING_SHIFT) +#define RBBM_STATUS_GET_CPRQ_PENDING(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_CPRQ_PENDING_MASK) >> RBBM_STATUS_CPRQ_PENDING_SHIFT) +#define RBBM_STATUS_GET_CFRQ_PENDING(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_CFRQ_PENDING_MASK) >> RBBM_STATUS_CFRQ_PENDING_SHIFT) +#define RBBM_STATUS_GET_PFRQ_PENDING(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_PFRQ_PENDING_MASK) >> RBBM_STATUS_PFRQ_PENDING_SHIFT) +#define RBBM_STATUS_GET_VGT_BUSY_NO_DMA(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_VGT_BUSY_NO_DMA_MASK) >> RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT) +#define RBBM_STATUS_GET_RBBM_WU_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_RBBM_WU_BUSY_MASK) >> RBBM_STATUS_RBBM_WU_BUSY_SHIFT) +#define RBBM_STATUS_GET_CP_NRT_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_CP_NRT_BUSY_MASK) >> RBBM_STATUS_CP_NRT_BUSY_SHIFT) +#define RBBM_STATUS_GET_MH_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_MH_BUSY_MASK) >> RBBM_STATUS_MH_BUSY_SHIFT) +#define RBBM_STATUS_GET_MH_COHERENCY_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_MH_COHERENCY_BUSY_MASK) >> RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT) +#define RBBM_STATUS_GET_SX_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_SX_BUSY_MASK) >> RBBM_STATUS_SX_BUSY_SHIFT) +#define RBBM_STATUS_GET_TPC_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_TPC_BUSY_MASK) >> RBBM_STATUS_TPC_BUSY_SHIFT) +#define RBBM_STATUS_GET_SC_CNTX_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_SC_CNTX_BUSY_MASK) >> RBBM_STATUS_SC_CNTX_BUSY_SHIFT) +#define RBBM_STATUS_GET_PA_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_PA_BUSY_MASK) >> RBBM_STATUS_PA_BUSY_SHIFT) +#define RBBM_STATUS_GET_VGT_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_VGT_BUSY_MASK) >> RBBM_STATUS_VGT_BUSY_SHIFT) +#define RBBM_STATUS_GET_SQ_CNTX17_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_SQ_CNTX17_BUSY_MASK) >> RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT) +#define RBBM_STATUS_GET_SQ_CNTX0_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_SQ_CNTX0_BUSY_MASK) >> RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT) +#define RBBM_STATUS_GET_RB_CNTX_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_RB_CNTX_BUSY_MASK) >> RBBM_STATUS_RB_CNTX_BUSY_SHIFT) +#define RBBM_STATUS_GET_GUI_ACTIVE(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_GUI_ACTIVE_MASK) >> RBBM_STATUS_GUI_ACTIVE_SHIFT) + +#define RBBM_STATUS_SET_CMDFIFO_AVAIL(rbbm_status_reg, cmdfifo_avail) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CMDFIFO_AVAIL_MASK) | (cmdfifo_avail << RBBM_STATUS_CMDFIFO_AVAIL_SHIFT) +#define RBBM_STATUS_SET_TC_BUSY(rbbm_status_reg, tc_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_TC_BUSY_MASK) | (tc_busy << RBBM_STATUS_TC_BUSY_SHIFT) +#define RBBM_STATUS_SET_HIRQ_PENDING(rbbm_status_reg, hirq_pending) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_HIRQ_PENDING_MASK) | (hirq_pending << RBBM_STATUS_HIRQ_PENDING_SHIFT) +#define RBBM_STATUS_SET_CPRQ_PENDING(rbbm_status_reg, cprq_pending) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CPRQ_PENDING_MASK) | (cprq_pending << RBBM_STATUS_CPRQ_PENDING_SHIFT) +#define RBBM_STATUS_SET_CFRQ_PENDING(rbbm_status_reg, cfrq_pending) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CFRQ_PENDING_MASK) | (cfrq_pending << RBBM_STATUS_CFRQ_PENDING_SHIFT) +#define RBBM_STATUS_SET_PFRQ_PENDING(rbbm_status_reg, pfrq_pending) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_PFRQ_PENDING_MASK) | (pfrq_pending << RBBM_STATUS_PFRQ_PENDING_SHIFT) +#define RBBM_STATUS_SET_VGT_BUSY_NO_DMA(rbbm_status_reg, vgt_busy_no_dma) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_VGT_BUSY_NO_DMA_MASK) | (vgt_busy_no_dma << RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT) +#define RBBM_STATUS_SET_RBBM_WU_BUSY(rbbm_status_reg, rbbm_wu_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_RBBM_WU_BUSY_MASK) | (rbbm_wu_busy << RBBM_STATUS_RBBM_WU_BUSY_SHIFT) +#define RBBM_STATUS_SET_CP_NRT_BUSY(rbbm_status_reg, cp_nrt_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CP_NRT_BUSY_MASK) | (cp_nrt_busy << RBBM_STATUS_CP_NRT_BUSY_SHIFT) +#define RBBM_STATUS_SET_MH_BUSY(rbbm_status_reg, mh_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_MH_BUSY_MASK) | (mh_busy << RBBM_STATUS_MH_BUSY_SHIFT) +#define RBBM_STATUS_SET_MH_COHERENCY_BUSY(rbbm_status_reg, mh_coherency_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_MH_COHERENCY_BUSY_MASK) | (mh_coherency_busy << RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT) +#define RBBM_STATUS_SET_SX_BUSY(rbbm_status_reg, sx_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SX_BUSY_MASK) | (sx_busy << RBBM_STATUS_SX_BUSY_SHIFT) +#define RBBM_STATUS_SET_TPC_BUSY(rbbm_status_reg, tpc_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_TPC_BUSY_MASK) | (tpc_busy << RBBM_STATUS_TPC_BUSY_SHIFT) +#define RBBM_STATUS_SET_SC_CNTX_BUSY(rbbm_status_reg, sc_cntx_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SC_CNTX_BUSY_MASK) | (sc_cntx_busy << RBBM_STATUS_SC_CNTX_BUSY_SHIFT) +#define RBBM_STATUS_SET_PA_BUSY(rbbm_status_reg, pa_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_PA_BUSY_MASK) | (pa_busy << RBBM_STATUS_PA_BUSY_SHIFT) +#define RBBM_STATUS_SET_VGT_BUSY(rbbm_status_reg, vgt_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_VGT_BUSY_MASK) | (vgt_busy << RBBM_STATUS_VGT_BUSY_SHIFT) +#define RBBM_STATUS_SET_SQ_CNTX17_BUSY(rbbm_status_reg, sq_cntx17_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SQ_CNTX17_BUSY_MASK) | (sq_cntx17_busy << RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT) +#define RBBM_STATUS_SET_SQ_CNTX0_BUSY(rbbm_status_reg, sq_cntx0_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SQ_CNTX0_BUSY_MASK) | (sq_cntx0_busy << RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT) +#define RBBM_STATUS_SET_RB_CNTX_BUSY(rbbm_status_reg, rb_cntx_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_RB_CNTX_BUSY_MASK) | (rb_cntx_busy << RBBM_STATUS_RB_CNTX_BUSY_SHIFT) +#define RBBM_STATUS_SET_GUI_ACTIVE(rbbm_status_reg, gui_active) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_GUI_ACTIVE_MASK) | (gui_active << RBBM_STATUS_GUI_ACTIVE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_status_t { + unsigned int cmdfifo_avail : RBBM_STATUS_CMDFIFO_AVAIL_SIZE; + unsigned int tc_busy : RBBM_STATUS_TC_BUSY_SIZE; + unsigned int : 2; + unsigned int hirq_pending : RBBM_STATUS_HIRQ_PENDING_SIZE; + unsigned int cprq_pending : RBBM_STATUS_CPRQ_PENDING_SIZE; + unsigned int cfrq_pending : RBBM_STATUS_CFRQ_PENDING_SIZE; + unsigned int pfrq_pending : RBBM_STATUS_PFRQ_PENDING_SIZE; + unsigned int vgt_busy_no_dma : RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE; + unsigned int : 1; + unsigned int rbbm_wu_busy : RBBM_STATUS_RBBM_WU_BUSY_SIZE; + unsigned int : 1; + unsigned int cp_nrt_busy : RBBM_STATUS_CP_NRT_BUSY_SIZE; + unsigned int : 1; + unsigned int mh_busy : RBBM_STATUS_MH_BUSY_SIZE; + unsigned int mh_coherency_busy : RBBM_STATUS_MH_COHERENCY_BUSY_SIZE; + unsigned int : 1; + unsigned int sx_busy : RBBM_STATUS_SX_BUSY_SIZE; + unsigned int tpc_busy : RBBM_STATUS_TPC_BUSY_SIZE; + unsigned int : 1; + unsigned int sc_cntx_busy : RBBM_STATUS_SC_CNTX_BUSY_SIZE; + unsigned int pa_busy : RBBM_STATUS_PA_BUSY_SIZE; + unsigned int vgt_busy : RBBM_STATUS_VGT_BUSY_SIZE; + unsigned int sq_cntx17_busy : RBBM_STATUS_SQ_CNTX17_BUSY_SIZE; + unsigned int sq_cntx0_busy : RBBM_STATUS_SQ_CNTX0_BUSY_SIZE; + unsigned int : 1; + unsigned int rb_cntx_busy : RBBM_STATUS_RB_CNTX_BUSY_SIZE; + unsigned int gui_active : RBBM_STATUS_GUI_ACTIVE_SIZE; + } rbbm_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_status_t { + unsigned int gui_active : RBBM_STATUS_GUI_ACTIVE_SIZE; + unsigned int rb_cntx_busy : RBBM_STATUS_RB_CNTX_BUSY_SIZE; + unsigned int : 1; + unsigned int sq_cntx0_busy : RBBM_STATUS_SQ_CNTX0_BUSY_SIZE; + unsigned int sq_cntx17_busy : RBBM_STATUS_SQ_CNTX17_BUSY_SIZE; + unsigned int vgt_busy : RBBM_STATUS_VGT_BUSY_SIZE; + unsigned int pa_busy : RBBM_STATUS_PA_BUSY_SIZE; + unsigned int sc_cntx_busy : RBBM_STATUS_SC_CNTX_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_busy : RBBM_STATUS_TPC_BUSY_SIZE; + unsigned int sx_busy : RBBM_STATUS_SX_BUSY_SIZE; + unsigned int : 1; + unsigned int mh_coherency_busy : RBBM_STATUS_MH_COHERENCY_BUSY_SIZE; + unsigned int mh_busy : RBBM_STATUS_MH_BUSY_SIZE; + unsigned int : 1; + unsigned int cp_nrt_busy : RBBM_STATUS_CP_NRT_BUSY_SIZE; + unsigned int : 1; + unsigned int rbbm_wu_busy : RBBM_STATUS_RBBM_WU_BUSY_SIZE; + unsigned int : 1; + unsigned int vgt_busy_no_dma : RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE; + unsigned int pfrq_pending : RBBM_STATUS_PFRQ_PENDING_SIZE; + unsigned int cfrq_pending : RBBM_STATUS_CFRQ_PENDING_SIZE; + unsigned int cprq_pending : RBBM_STATUS_CPRQ_PENDING_SIZE; + unsigned int hirq_pending : RBBM_STATUS_HIRQ_PENDING_SIZE; + unsigned int : 2; + unsigned int tc_busy : RBBM_STATUS_TC_BUSY_SIZE; + unsigned int cmdfifo_avail : RBBM_STATUS_CMDFIFO_AVAIL_SIZE; + } rbbm_status_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_status_t f; +} rbbm_status_u; + + +/* + * RBBM_DSPLY struct + */ + +#define RBBM_DSPLY_DISPLAY_ID0_ACTIVE_SIZE 1 +#define RBBM_DSPLY_DISPLAY_ID1_ACTIVE_SIZE 1 +#define RBBM_DSPLY_DISPLAY_ID2_ACTIVE_SIZE 1 +#define RBBM_DSPLY_VSYNC_ACTIVE_SIZE 1 +#define RBBM_DSPLY_USE_DISPLAY_ID0_SIZE 1 +#define RBBM_DSPLY_USE_DISPLAY_ID1_SIZE 1 +#define RBBM_DSPLY_USE_DISPLAY_ID2_SIZE 1 +#define RBBM_DSPLY_SW_CNTL_SIZE 1 +#define RBBM_DSPLY_NUM_BUFS_SIZE 2 + +#define RBBM_DSPLY_DISPLAY_ID0_ACTIVE_SHIFT 0 +#define RBBM_DSPLY_DISPLAY_ID1_ACTIVE_SHIFT 1 +#define RBBM_DSPLY_DISPLAY_ID2_ACTIVE_SHIFT 2 +#define RBBM_DSPLY_VSYNC_ACTIVE_SHIFT 3 +#define RBBM_DSPLY_USE_DISPLAY_ID0_SHIFT 4 +#define RBBM_DSPLY_USE_DISPLAY_ID1_SHIFT 5 +#define RBBM_DSPLY_USE_DISPLAY_ID2_SHIFT 6 +#define RBBM_DSPLY_SW_CNTL_SHIFT 7 +#define RBBM_DSPLY_NUM_BUFS_SHIFT 8 + +#define RBBM_DSPLY_DISPLAY_ID0_ACTIVE_MASK 0x00000001 +#define RBBM_DSPLY_DISPLAY_ID1_ACTIVE_MASK 0x00000002 +#define RBBM_DSPLY_DISPLAY_ID2_ACTIVE_MASK 0x00000004 +#define RBBM_DSPLY_VSYNC_ACTIVE_MASK 0x00000008 +#define RBBM_DSPLY_USE_DISPLAY_ID0_MASK 0x00000010 +#define RBBM_DSPLY_USE_DISPLAY_ID1_MASK 0x00000020 +#define RBBM_DSPLY_USE_DISPLAY_ID2_MASK 0x00000040 +#define RBBM_DSPLY_SW_CNTL_MASK 0x00000080 +#define RBBM_DSPLY_NUM_BUFS_MASK 0x00000300 + +#define RBBM_DSPLY_MASK \ + (RBBM_DSPLY_DISPLAY_ID0_ACTIVE_MASK | \ + RBBM_DSPLY_DISPLAY_ID1_ACTIVE_MASK | \ + RBBM_DSPLY_DISPLAY_ID2_ACTIVE_MASK | \ + RBBM_DSPLY_VSYNC_ACTIVE_MASK | \ + RBBM_DSPLY_USE_DISPLAY_ID0_MASK | \ + RBBM_DSPLY_USE_DISPLAY_ID1_MASK | \ + RBBM_DSPLY_USE_DISPLAY_ID2_MASK | \ + RBBM_DSPLY_SW_CNTL_MASK | \ + RBBM_DSPLY_NUM_BUFS_MASK) + +#define RBBM_DSPLY(display_id0_active, display_id1_active, display_id2_active, vsync_active, use_display_id0, use_display_id1, use_display_id2, sw_cntl, num_bufs) \ + ((display_id0_active << RBBM_DSPLY_DISPLAY_ID0_ACTIVE_SHIFT) | \ + (display_id1_active << RBBM_DSPLY_DISPLAY_ID1_ACTIVE_SHIFT) | \ + (display_id2_active << RBBM_DSPLY_DISPLAY_ID2_ACTIVE_SHIFT) | \ + (vsync_active << RBBM_DSPLY_VSYNC_ACTIVE_SHIFT) | \ + (use_display_id0 << RBBM_DSPLY_USE_DISPLAY_ID0_SHIFT) | \ + (use_display_id1 << RBBM_DSPLY_USE_DISPLAY_ID1_SHIFT) | \ + (use_display_id2 << RBBM_DSPLY_USE_DISPLAY_ID2_SHIFT) | \ + (sw_cntl << RBBM_DSPLY_SW_CNTL_SHIFT) | \ + (num_bufs << RBBM_DSPLY_NUM_BUFS_SHIFT)) + +#define RBBM_DSPLY_GET_DISPLAY_ID0_ACTIVE(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DISPLAY_ID0_ACTIVE_MASK) >> RBBM_DSPLY_DISPLAY_ID0_ACTIVE_SHIFT) +#define RBBM_DSPLY_GET_DISPLAY_ID1_ACTIVE(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DISPLAY_ID1_ACTIVE_MASK) >> RBBM_DSPLY_DISPLAY_ID1_ACTIVE_SHIFT) +#define RBBM_DSPLY_GET_DISPLAY_ID2_ACTIVE(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DISPLAY_ID2_ACTIVE_MASK) >> RBBM_DSPLY_DISPLAY_ID2_ACTIVE_SHIFT) +#define RBBM_DSPLY_GET_VSYNC_ACTIVE(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_VSYNC_ACTIVE_MASK) >> RBBM_DSPLY_VSYNC_ACTIVE_SHIFT) +#define RBBM_DSPLY_GET_USE_DISPLAY_ID0(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_USE_DISPLAY_ID0_MASK) >> RBBM_DSPLY_USE_DISPLAY_ID0_SHIFT) +#define RBBM_DSPLY_GET_USE_DISPLAY_ID1(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_USE_DISPLAY_ID1_MASK) >> RBBM_DSPLY_USE_DISPLAY_ID1_SHIFT) +#define RBBM_DSPLY_GET_USE_DISPLAY_ID2(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_USE_DISPLAY_ID2_MASK) >> RBBM_DSPLY_USE_DISPLAY_ID2_SHIFT) +#define RBBM_DSPLY_GET_SW_CNTL(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_SW_CNTL_MASK) >> RBBM_DSPLY_SW_CNTL_SHIFT) +#define RBBM_DSPLY_GET_NUM_BUFS(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_NUM_BUFS_MASK) >> RBBM_DSPLY_NUM_BUFS_SHIFT) + +#define RBBM_DSPLY_SET_DISPLAY_ID0_ACTIVE(rbbm_dsply_reg, display_id0_active) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DISPLAY_ID0_ACTIVE_MASK) | (display_id0_active << RBBM_DSPLY_DISPLAY_ID0_ACTIVE_SHIFT) +#define RBBM_DSPLY_SET_DISPLAY_ID1_ACTIVE(rbbm_dsply_reg, display_id1_active) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DISPLAY_ID1_ACTIVE_MASK) | (display_id1_active << RBBM_DSPLY_DISPLAY_ID1_ACTIVE_SHIFT) +#define RBBM_DSPLY_SET_DISPLAY_ID2_ACTIVE(rbbm_dsply_reg, display_id2_active) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DISPLAY_ID2_ACTIVE_MASK) | (display_id2_active << RBBM_DSPLY_DISPLAY_ID2_ACTIVE_SHIFT) +#define RBBM_DSPLY_SET_VSYNC_ACTIVE(rbbm_dsply_reg, vsync_active) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_VSYNC_ACTIVE_MASK) | (vsync_active << RBBM_DSPLY_VSYNC_ACTIVE_SHIFT) +#define RBBM_DSPLY_SET_USE_DISPLAY_ID0(rbbm_dsply_reg, use_display_id0) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_USE_DISPLAY_ID0_MASK) | (use_display_id0 << RBBM_DSPLY_USE_DISPLAY_ID0_SHIFT) +#define RBBM_DSPLY_SET_USE_DISPLAY_ID1(rbbm_dsply_reg, use_display_id1) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_USE_DISPLAY_ID1_MASK) | (use_display_id1 << RBBM_DSPLY_USE_DISPLAY_ID1_SHIFT) +#define RBBM_DSPLY_SET_USE_DISPLAY_ID2(rbbm_dsply_reg, use_display_id2) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_USE_DISPLAY_ID2_MASK) | (use_display_id2 << RBBM_DSPLY_USE_DISPLAY_ID2_SHIFT) +#define RBBM_DSPLY_SET_SW_CNTL(rbbm_dsply_reg, sw_cntl) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SW_CNTL_MASK) | (sw_cntl << RBBM_DSPLY_SW_CNTL_SHIFT) +#define RBBM_DSPLY_SET_NUM_BUFS(rbbm_dsply_reg, num_bufs) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_NUM_BUFS_MASK) | (num_bufs << RBBM_DSPLY_NUM_BUFS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_dsply_t { + unsigned int display_id0_active : RBBM_DSPLY_DISPLAY_ID0_ACTIVE_SIZE; + unsigned int display_id1_active : RBBM_DSPLY_DISPLAY_ID1_ACTIVE_SIZE; + unsigned int display_id2_active : RBBM_DSPLY_DISPLAY_ID2_ACTIVE_SIZE; + unsigned int vsync_active : RBBM_DSPLY_VSYNC_ACTIVE_SIZE; + unsigned int use_display_id0 : RBBM_DSPLY_USE_DISPLAY_ID0_SIZE; + unsigned int use_display_id1 : RBBM_DSPLY_USE_DISPLAY_ID1_SIZE; + unsigned int use_display_id2 : RBBM_DSPLY_USE_DISPLAY_ID2_SIZE; + unsigned int sw_cntl : RBBM_DSPLY_SW_CNTL_SIZE; + unsigned int num_bufs : RBBM_DSPLY_NUM_BUFS_SIZE; + unsigned int : 22; + } rbbm_dsply_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_dsply_t { + unsigned int : 22; + unsigned int num_bufs : RBBM_DSPLY_NUM_BUFS_SIZE; + unsigned int sw_cntl : RBBM_DSPLY_SW_CNTL_SIZE; + unsigned int use_display_id2 : RBBM_DSPLY_USE_DISPLAY_ID2_SIZE; + unsigned int use_display_id1 : RBBM_DSPLY_USE_DISPLAY_ID1_SIZE; + unsigned int use_display_id0 : RBBM_DSPLY_USE_DISPLAY_ID0_SIZE; + unsigned int vsync_active : RBBM_DSPLY_VSYNC_ACTIVE_SIZE; + unsigned int display_id2_active : RBBM_DSPLY_DISPLAY_ID2_ACTIVE_SIZE; + unsigned int display_id1_active : RBBM_DSPLY_DISPLAY_ID1_ACTIVE_SIZE; + unsigned int display_id0_active : RBBM_DSPLY_DISPLAY_ID0_ACTIVE_SIZE; + } rbbm_dsply_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_dsply_t f; +} rbbm_dsply_u; + + +/* + * RBBM_RENDER_LATEST struct + */ + +#define RBBM_RENDER_LATEST_BUFFER_ID_SIZE 2 + +#define RBBM_RENDER_LATEST_BUFFER_ID_SHIFT 0 + +#define RBBM_RENDER_LATEST_BUFFER_ID_MASK 0x00000003 + +#define RBBM_RENDER_LATEST_MASK \ + (RBBM_RENDER_LATEST_BUFFER_ID_MASK) + +#define RBBM_RENDER_LATEST(buffer_id) \ + ((buffer_id << RBBM_RENDER_LATEST_BUFFER_ID_SHIFT)) + +#define RBBM_RENDER_LATEST_GET_BUFFER_ID(rbbm_render_latest) \ + ((rbbm_render_latest & RBBM_RENDER_LATEST_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_BUFFER_ID_SHIFT) + +#define RBBM_RENDER_LATEST_SET_BUFFER_ID(rbbm_render_latest_reg, buffer_id) \ + rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_BUFFER_ID_MASK) | (buffer_id << RBBM_RENDER_LATEST_BUFFER_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_render_latest_t { + unsigned int buffer_id : RBBM_RENDER_LATEST_BUFFER_ID_SIZE; + unsigned int : 30; + } rbbm_render_latest_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_render_latest_t { + unsigned int : 30; + unsigned int buffer_id : RBBM_RENDER_LATEST_BUFFER_ID_SIZE; + } rbbm_render_latest_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_render_latest_t f; +} rbbm_render_latest_u; + + +/* + * RBBM_RTL_RELEASE struct + */ + +#define RBBM_RTL_RELEASE_CHANGELIST_SIZE 32 + +#define RBBM_RTL_RELEASE_CHANGELIST_SHIFT 0 + +#define RBBM_RTL_RELEASE_CHANGELIST_MASK 0xffffffff + +#define RBBM_RTL_RELEASE_MASK \ + (RBBM_RTL_RELEASE_CHANGELIST_MASK) + +#define RBBM_RTL_RELEASE(changelist) \ + ((changelist << RBBM_RTL_RELEASE_CHANGELIST_SHIFT)) + +#define RBBM_RTL_RELEASE_GET_CHANGELIST(rbbm_rtl_release) \ + ((rbbm_rtl_release & RBBM_RTL_RELEASE_CHANGELIST_MASK) >> RBBM_RTL_RELEASE_CHANGELIST_SHIFT) + +#define RBBM_RTL_RELEASE_SET_CHANGELIST(rbbm_rtl_release_reg, changelist) \ + rbbm_rtl_release_reg = (rbbm_rtl_release_reg & ~RBBM_RTL_RELEASE_CHANGELIST_MASK) | (changelist << RBBM_RTL_RELEASE_CHANGELIST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_rtl_release_t { + unsigned int changelist : RBBM_RTL_RELEASE_CHANGELIST_SIZE; + } rbbm_rtl_release_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_rtl_release_t { + unsigned int changelist : RBBM_RTL_RELEASE_CHANGELIST_SIZE; + } rbbm_rtl_release_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_rtl_release_t f; +} rbbm_rtl_release_u; + + +/* + * RBBM_PATCH_RELEASE struct + */ + +#define RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE 16 +#define RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE 8 +#define RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE 8 + +#define RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT 0 +#define RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT 16 +#define RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT 24 + +#define RBBM_PATCH_RELEASE_PATCH_REVISION_MASK 0x0000ffff +#define RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK 0x00ff0000 +#define RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK 0xff000000 + +#define RBBM_PATCH_RELEASE_MASK \ + (RBBM_PATCH_RELEASE_PATCH_REVISION_MASK | \ + RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK | \ + RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) + +#define RBBM_PATCH_RELEASE(patch_revision, patch_selection, customer_id) \ + ((patch_revision << RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT) | \ + (patch_selection << RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT) | \ + (customer_id << RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT)) + +#define RBBM_PATCH_RELEASE_GET_PATCH_REVISION(rbbm_patch_release) \ + ((rbbm_patch_release & RBBM_PATCH_RELEASE_PATCH_REVISION_MASK) >> RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT) +#define RBBM_PATCH_RELEASE_GET_PATCH_SELECTION(rbbm_patch_release) \ + ((rbbm_patch_release & RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK) >> RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT) +#define RBBM_PATCH_RELEASE_GET_CUSTOMER_ID(rbbm_patch_release) \ + ((rbbm_patch_release & RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) >> RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT) + +#define RBBM_PATCH_RELEASE_SET_PATCH_REVISION(rbbm_patch_release_reg, patch_revision) \ + rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_PATCH_REVISION_MASK) | (patch_revision << RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT) +#define RBBM_PATCH_RELEASE_SET_PATCH_SELECTION(rbbm_patch_release_reg, patch_selection) \ + rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK) | (patch_selection << RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT) +#define RBBM_PATCH_RELEASE_SET_CUSTOMER_ID(rbbm_patch_release_reg, customer_id) \ + rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) | (customer_id << RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_patch_release_t { + unsigned int patch_revision : RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE; + unsigned int patch_selection : RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE; + unsigned int customer_id : RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE; + } rbbm_patch_release_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_patch_release_t { + unsigned int customer_id : RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE; + unsigned int patch_selection : RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE; + unsigned int patch_revision : RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE; + } rbbm_patch_release_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_patch_release_t f; +} rbbm_patch_release_u; + + +/* + * RBBM_AUXILIARY_CONFIG struct + */ + +#define RBBM_AUXILIARY_CONFIG_RESERVED_SIZE 32 + +#define RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT 0 + +#define RBBM_AUXILIARY_CONFIG_RESERVED_MASK 0xffffffff + +#define RBBM_AUXILIARY_CONFIG_MASK \ + (RBBM_AUXILIARY_CONFIG_RESERVED_MASK) + +#define RBBM_AUXILIARY_CONFIG(reserved) \ + ((reserved << RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT)) + +#define RBBM_AUXILIARY_CONFIG_GET_RESERVED(rbbm_auxiliary_config) \ + ((rbbm_auxiliary_config & RBBM_AUXILIARY_CONFIG_RESERVED_MASK) >> RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT) + +#define RBBM_AUXILIARY_CONFIG_SET_RESERVED(rbbm_auxiliary_config_reg, reserved) \ + rbbm_auxiliary_config_reg = (rbbm_auxiliary_config_reg & ~RBBM_AUXILIARY_CONFIG_RESERVED_MASK) | (reserved << RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_auxiliary_config_t { + unsigned int reserved : RBBM_AUXILIARY_CONFIG_RESERVED_SIZE; + } rbbm_auxiliary_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_auxiliary_config_t { + unsigned int reserved : RBBM_AUXILIARY_CONFIG_RESERVED_SIZE; + } rbbm_auxiliary_config_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_auxiliary_config_t f; +} rbbm_auxiliary_config_u; + + +/* + * RBBM_PERIPHID0 struct + */ + +#define RBBM_PERIPHID0_PARTNUMBER0_SIZE 8 + +#define RBBM_PERIPHID0_PARTNUMBER0_SHIFT 0 + +#define RBBM_PERIPHID0_PARTNUMBER0_MASK 0x000000ff + +#define RBBM_PERIPHID0_MASK \ + (RBBM_PERIPHID0_PARTNUMBER0_MASK) + +#define RBBM_PERIPHID0(partnumber0) \ + ((partnumber0 << RBBM_PERIPHID0_PARTNUMBER0_SHIFT)) + +#define RBBM_PERIPHID0_GET_PARTNUMBER0(rbbm_periphid0) \ + ((rbbm_periphid0 & RBBM_PERIPHID0_PARTNUMBER0_MASK) >> RBBM_PERIPHID0_PARTNUMBER0_SHIFT) + +#define RBBM_PERIPHID0_SET_PARTNUMBER0(rbbm_periphid0_reg, partnumber0) \ + rbbm_periphid0_reg = (rbbm_periphid0_reg & ~RBBM_PERIPHID0_PARTNUMBER0_MASK) | (partnumber0 << RBBM_PERIPHID0_PARTNUMBER0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_periphid0_t { + unsigned int partnumber0 : RBBM_PERIPHID0_PARTNUMBER0_SIZE; + unsigned int : 24; + } rbbm_periphid0_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_periphid0_t { + unsigned int : 24; + unsigned int partnumber0 : RBBM_PERIPHID0_PARTNUMBER0_SIZE; + } rbbm_periphid0_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_periphid0_t f; +} rbbm_periphid0_u; + + +/* + * RBBM_PERIPHID1 struct + */ + +#define RBBM_PERIPHID1_PARTNUMBER1_SIZE 4 +#define RBBM_PERIPHID1_DESIGNER0_SIZE 4 + +#define RBBM_PERIPHID1_PARTNUMBER1_SHIFT 0 +#define RBBM_PERIPHID1_DESIGNER0_SHIFT 4 + +#define RBBM_PERIPHID1_PARTNUMBER1_MASK 0x0000000f +#define RBBM_PERIPHID1_DESIGNER0_MASK 0x000000f0 + +#define RBBM_PERIPHID1_MASK \ + (RBBM_PERIPHID1_PARTNUMBER1_MASK | \ + RBBM_PERIPHID1_DESIGNER0_MASK) + +#define RBBM_PERIPHID1(partnumber1, designer0) \ + ((partnumber1 << RBBM_PERIPHID1_PARTNUMBER1_SHIFT) | \ + (designer0 << RBBM_PERIPHID1_DESIGNER0_SHIFT)) + +#define RBBM_PERIPHID1_GET_PARTNUMBER1(rbbm_periphid1) \ + ((rbbm_periphid1 & RBBM_PERIPHID1_PARTNUMBER1_MASK) >> RBBM_PERIPHID1_PARTNUMBER1_SHIFT) +#define RBBM_PERIPHID1_GET_DESIGNER0(rbbm_periphid1) \ + ((rbbm_periphid1 & RBBM_PERIPHID1_DESIGNER0_MASK) >> RBBM_PERIPHID1_DESIGNER0_SHIFT) + +#define RBBM_PERIPHID1_SET_PARTNUMBER1(rbbm_periphid1_reg, partnumber1) \ + rbbm_periphid1_reg = (rbbm_periphid1_reg & ~RBBM_PERIPHID1_PARTNUMBER1_MASK) | (partnumber1 << RBBM_PERIPHID1_PARTNUMBER1_SHIFT) +#define RBBM_PERIPHID1_SET_DESIGNER0(rbbm_periphid1_reg, designer0) \ + rbbm_periphid1_reg = (rbbm_periphid1_reg & ~RBBM_PERIPHID1_DESIGNER0_MASK) | (designer0 << RBBM_PERIPHID1_DESIGNER0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_periphid1_t { + unsigned int partnumber1 : RBBM_PERIPHID1_PARTNUMBER1_SIZE; + unsigned int designer0 : RBBM_PERIPHID1_DESIGNER0_SIZE; + unsigned int : 24; + } rbbm_periphid1_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_periphid1_t { + unsigned int : 24; + unsigned int designer0 : RBBM_PERIPHID1_DESIGNER0_SIZE; + unsigned int partnumber1 : RBBM_PERIPHID1_PARTNUMBER1_SIZE; + } rbbm_periphid1_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_periphid1_t f; +} rbbm_periphid1_u; + + +/* + * RBBM_PERIPHID2 struct + */ + +#define RBBM_PERIPHID2_DESIGNER1_SIZE 4 +#define RBBM_PERIPHID2_REVISION_SIZE 4 + +#define RBBM_PERIPHID2_DESIGNER1_SHIFT 0 +#define RBBM_PERIPHID2_REVISION_SHIFT 4 + +#define RBBM_PERIPHID2_DESIGNER1_MASK 0x0000000f +#define RBBM_PERIPHID2_REVISION_MASK 0x000000f0 + +#define RBBM_PERIPHID2_MASK \ + (RBBM_PERIPHID2_DESIGNER1_MASK | \ + RBBM_PERIPHID2_REVISION_MASK) + +#define RBBM_PERIPHID2(designer1, revision) \ + ((designer1 << RBBM_PERIPHID2_DESIGNER1_SHIFT) | \ + (revision << RBBM_PERIPHID2_REVISION_SHIFT)) + +#define RBBM_PERIPHID2_GET_DESIGNER1(rbbm_periphid2) \ + ((rbbm_periphid2 & RBBM_PERIPHID2_DESIGNER1_MASK) >> RBBM_PERIPHID2_DESIGNER1_SHIFT) +#define RBBM_PERIPHID2_GET_REVISION(rbbm_periphid2) \ + ((rbbm_periphid2 & RBBM_PERIPHID2_REVISION_MASK) >> RBBM_PERIPHID2_REVISION_SHIFT) + +#define RBBM_PERIPHID2_SET_DESIGNER1(rbbm_periphid2_reg, designer1) \ + rbbm_periphid2_reg = (rbbm_periphid2_reg & ~RBBM_PERIPHID2_DESIGNER1_MASK) | (designer1 << RBBM_PERIPHID2_DESIGNER1_SHIFT) +#define RBBM_PERIPHID2_SET_REVISION(rbbm_periphid2_reg, revision) \ + rbbm_periphid2_reg = (rbbm_periphid2_reg & ~RBBM_PERIPHID2_REVISION_MASK) | (revision << RBBM_PERIPHID2_REVISION_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_periphid2_t { + unsigned int designer1 : RBBM_PERIPHID2_DESIGNER1_SIZE; + unsigned int revision : RBBM_PERIPHID2_REVISION_SIZE; + unsigned int : 24; + } rbbm_periphid2_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_periphid2_t { + unsigned int : 24; + unsigned int revision : RBBM_PERIPHID2_REVISION_SIZE; + unsigned int designer1 : RBBM_PERIPHID2_DESIGNER1_SIZE; + } rbbm_periphid2_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_periphid2_t f; +} rbbm_periphid2_u; + + +/* + * RBBM_PERIPHID3 struct + */ + +#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE 2 +#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE 2 +#define RBBM_PERIPHID3_MH_INTERFACE_SIZE 2 +#define RBBM_PERIPHID3_CONTINUATION_SIZE 1 + +#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT 0 +#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT 2 +#define RBBM_PERIPHID3_MH_INTERFACE_SHIFT 4 +#define RBBM_PERIPHID3_CONTINUATION_SHIFT 7 + +#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK 0x00000003 +#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK 0x0000000c +#define RBBM_PERIPHID3_MH_INTERFACE_MASK 0x00000030 +#define RBBM_PERIPHID3_CONTINUATION_MASK 0x00000080 + +#define RBBM_PERIPHID3_MASK \ + (RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK | \ + RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK | \ + RBBM_PERIPHID3_MH_INTERFACE_MASK | \ + RBBM_PERIPHID3_CONTINUATION_MASK) + +#define RBBM_PERIPHID3(rbbm_host_interface, garb_slave_interface, mh_interface, continuation) \ + ((rbbm_host_interface << RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT) | \ + (garb_slave_interface << RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT) | \ + (mh_interface << RBBM_PERIPHID3_MH_INTERFACE_SHIFT) | \ + (continuation << RBBM_PERIPHID3_CONTINUATION_SHIFT)) + +#define RBBM_PERIPHID3_GET_RBBM_HOST_INTERFACE(rbbm_periphid3) \ + ((rbbm_periphid3 & RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK) >> RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_GET_GARB_SLAVE_INTERFACE(rbbm_periphid3) \ + ((rbbm_periphid3 & RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK) >> RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_GET_MH_INTERFACE(rbbm_periphid3) \ + ((rbbm_periphid3 & RBBM_PERIPHID3_MH_INTERFACE_MASK) >> RBBM_PERIPHID3_MH_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_GET_CONTINUATION(rbbm_periphid3) \ + ((rbbm_periphid3 & RBBM_PERIPHID3_CONTINUATION_MASK) >> RBBM_PERIPHID3_CONTINUATION_SHIFT) + +#define RBBM_PERIPHID3_SET_RBBM_HOST_INTERFACE(rbbm_periphid3_reg, rbbm_host_interface) \ + rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK) | (rbbm_host_interface << RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_SET_GARB_SLAVE_INTERFACE(rbbm_periphid3_reg, garb_slave_interface) \ + rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK) | (garb_slave_interface << RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_SET_MH_INTERFACE(rbbm_periphid3_reg, mh_interface) \ + rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_MH_INTERFACE_MASK) | (mh_interface << RBBM_PERIPHID3_MH_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_SET_CONTINUATION(rbbm_periphid3_reg, continuation) \ + rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_CONTINUATION_MASK) | (continuation << RBBM_PERIPHID3_CONTINUATION_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_periphid3_t { + unsigned int rbbm_host_interface : RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE; + unsigned int garb_slave_interface : RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE; + unsigned int mh_interface : RBBM_PERIPHID3_MH_INTERFACE_SIZE; + unsigned int : 1; + unsigned int continuation : RBBM_PERIPHID3_CONTINUATION_SIZE; + unsigned int : 24; + } rbbm_periphid3_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_periphid3_t { + unsigned int : 24; + unsigned int continuation : RBBM_PERIPHID3_CONTINUATION_SIZE; + unsigned int : 1; + unsigned int mh_interface : RBBM_PERIPHID3_MH_INTERFACE_SIZE; + unsigned int garb_slave_interface : RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE; + unsigned int rbbm_host_interface : RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE; + } rbbm_periphid3_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_periphid3_t f; +} rbbm_periphid3_u; + + +/* + * RBBM_CNTL struct + */ + +#define RBBM_CNTL_READ_TIMEOUT_SIZE 8 +#define RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE 9 + +#define RBBM_CNTL_READ_TIMEOUT_SHIFT 0 +#define RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT 8 + +#define RBBM_CNTL_READ_TIMEOUT_MASK 0x000000ff +#define RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK 0x0001ff00 + +#define RBBM_CNTL_MASK \ + (RBBM_CNTL_READ_TIMEOUT_MASK | \ + RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) + +#define RBBM_CNTL(read_timeout, regclk_deassert_time) \ + ((read_timeout << RBBM_CNTL_READ_TIMEOUT_SHIFT) | \ + (regclk_deassert_time << RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT)) + +#define RBBM_CNTL_GET_READ_TIMEOUT(rbbm_cntl) \ + ((rbbm_cntl & RBBM_CNTL_READ_TIMEOUT_MASK) >> RBBM_CNTL_READ_TIMEOUT_SHIFT) +#define RBBM_CNTL_GET_REGCLK_DEASSERT_TIME(rbbm_cntl) \ + ((rbbm_cntl & RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) >> RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT) + +#define RBBM_CNTL_SET_READ_TIMEOUT(rbbm_cntl_reg, read_timeout) \ + rbbm_cntl_reg = (rbbm_cntl_reg & ~RBBM_CNTL_READ_TIMEOUT_MASK) | (read_timeout << RBBM_CNTL_READ_TIMEOUT_SHIFT) +#define RBBM_CNTL_SET_REGCLK_DEASSERT_TIME(rbbm_cntl_reg, regclk_deassert_time) \ + rbbm_cntl_reg = (rbbm_cntl_reg & ~RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) | (regclk_deassert_time << RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_cntl_t { + unsigned int read_timeout : RBBM_CNTL_READ_TIMEOUT_SIZE; + unsigned int regclk_deassert_time : RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE; + unsigned int : 15; + } rbbm_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_cntl_t { + unsigned int : 15; + unsigned int regclk_deassert_time : RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE; + unsigned int read_timeout : RBBM_CNTL_READ_TIMEOUT_SIZE; + } rbbm_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_cntl_t f; +} rbbm_cntl_u; + + +/* + * RBBM_SKEW_CNTL struct + */ + +#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE 5 +#define RBBM_SKEW_CNTL_SKEW_COUNT_SIZE 5 + +#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT 0 +#define RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT 5 + +#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK 0x0000001f +#define RBBM_SKEW_CNTL_SKEW_COUNT_MASK 0x000003e0 + +#define RBBM_SKEW_CNTL_MASK \ + (RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK | \ + RBBM_SKEW_CNTL_SKEW_COUNT_MASK) + +#define RBBM_SKEW_CNTL(skew_top_threshold, skew_count) \ + ((skew_top_threshold << RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT) | \ + (skew_count << RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT)) + +#define RBBM_SKEW_CNTL_GET_SKEW_TOP_THRESHOLD(rbbm_skew_cntl) \ + ((rbbm_skew_cntl & RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK) >> RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT) +#define RBBM_SKEW_CNTL_GET_SKEW_COUNT(rbbm_skew_cntl) \ + ((rbbm_skew_cntl & RBBM_SKEW_CNTL_SKEW_COUNT_MASK) >> RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT) + +#define RBBM_SKEW_CNTL_SET_SKEW_TOP_THRESHOLD(rbbm_skew_cntl_reg, skew_top_threshold) \ + rbbm_skew_cntl_reg = (rbbm_skew_cntl_reg & ~RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK) | (skew_top_threshold << RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT) +#define RBBM_SKEW_CNTL_SET_SKEW_COUNT(rbbm_skew_cntl_reg, skew_count) \ + rbbm_skew_cntl_reg = (rbbm_skew_cntl_reg & ~RBBM_SKEW_CNTL_SKEW_COUNT_MASK) | (skew_count << RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_skew_cntl_t { + unsigned int skew_top_threshold : RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE; + unsigned int skew_count : RBBM_SKEW_CNTL_SKEW_COUNT_SIZE; + unsigned int : 22; + } rbbm_skew_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_skew_cntl_t { + unsigned int : 22; + unsigned int skew_count : RBBM_SKEW_CNTL_SKEW_COUNT_SIZE; + unsigned int skew_top_threshold : RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE; + } rbbm_skew_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_skew_cntl_t f; +} rbbm_skew_cntl_u; + + +/* + * RBBM_SOFT_RESET struct + */ + +#define RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE 1 + +#define RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT 0 +#define RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT 2 +#define RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT 3 +#define RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT 4 +#define RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT 5 +#define RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT 6 +#define RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT 12 +#define RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT 15 +#define RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT 16 + +#define RBBM_SOFT_RESET_SOFT_RESET_CP_MASK 0x00000001 +#define RBBM_SOFT_RESET_SOFT_RESET_PA_MASK 0x00000004 +#define RBBM_SOFT_RESET_SOFT_RESET_MH_MASK 0x00000008 +#define RBBM_SOFT_RESET_SOFT_RESET_BC_MASK 0x00000010 +#define RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK 0x00000020 +#define RBBM_SOFT_RESET_SOFT_RESET_SX_MASK 0x00000040 +#define RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK 0x00001000 +#define RBBM_SOFT_RESET_SOFT_RESET_SC_MASK 0x00008000 +#define RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK 0x00010000 + +#define RBBM_SOFT_RESET_MASK \ + (RBBM_SOFT_RESET_SOFT_RESET_CP_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_PA_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_MH_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_BC_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_SX_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_SC_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) + +#define RBBM_SOFT_RESET(soft_reset_cp, soft_reset_pa, soft_reset_mh, soft_reset_bc, soft_reset_sq, soft_reset_sx, soft_reset_cib, soft_reset_sc, soft_reset_vgt) \ + ((soft_reset_cp << RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT) | \ + (soft_reset_pa << RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT) | \ + (soft_reset_mh << RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT) | \ + (soft_reset_bc << RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT) | \ + (soft_reset_sq << RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT) | \ + (soft_reset_sx << RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT) | \ + (soft_reset_cib << RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT) | \ + (soft_reset_sc << RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT) | \ + (soft_reset_vgt << RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT)) + +#define RBBM_SOFT_RESET_GET_SOFT_RESET_CP(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_CP_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_PA(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_PA_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_MH(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_MH_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_BC(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_BC_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_SQ(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_SX(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SX_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_CIB(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_SC(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SC_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_VGT(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT) + +#define RBBM_SOFT_RESET_SET_SOFT_RESET_CP(rbbm_soft_reset_reg, soft_reset_cp) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_CP_MASK) | (soft_reset_cp << RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_PA(rbbm_soft_reset_reg, soft_reset_pa) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_PA_MASK) | (soft_reset_pa << RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_MH(rbbm_soft_reset_reg, soft_reset_mh) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_MH_MASK) | (soft_reset_mh << RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_BC(rbbm_soft_reset_reg, soft_reset_bc) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_BC_MASK) | (soft_reset_bc << RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_SQ(rbbm_soft_reset_reg, soft_reset_sq) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK) | (soft_reset_sq << RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_SX(rbbm_soft_reset_reg, soft_reset_sx) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SX_MASK) | (soft_reset_sx << RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_CIB(rbbm_soft_reset_reg, soft_reset_cib) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK) | (soft_reset_cib << RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_SC(rbbm_soft_reset_reg, soft_reset_sc) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SC_MASK) | (soft_reset_sc << RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_VGT(rbbm_soft_reset_reg, soft_reset_vgt) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) | (soft_reset_vgt << RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_soft_reset_t { + unsigned int soft_reset_cp : RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE; + unsigned int : 1; + unsigned int soft_reset_pa : RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE; + unsigned int soft_reset_mh : RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE; + unsigned int soft_reset_bc : RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE; + unsigned int soft_reset_sq : RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE; + unsigned int soft_reset_sx : RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE; + unsigned int : 5; + unsigned int soft_reset_cib : RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE; + unsigned int : 2; + unsigned int soft_reset_sc : RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE; + unsigned int soft_reset_vgt : RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE; + unsigned int : 15; + } rbbm_soft_reset_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_soft_reset_t { + unsigned int : 15; + unsigned int soft_reset_vgt : RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE; + unsigned int soft_reset_sc : RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE; + unsigned int : 2; + unsigned int soft_reset_cib : RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE; + unsigned int : 5; + unsigned int soft_reset_sx : RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE; + unsigned int soft_reset_sq : RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE; + unsigned int soft_reset_bc : RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE; + unsigned int soft_reset_mh : RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE; + unsigned int soft_reset_pa : RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE; + unsigned int : 1; + unsigned int soft_reset_cp : RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE; + } rbbm_soft_reset_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_soft_reset_t f; +} rbbm_soft_reset_u; + + +/* + * RBBM_PM_OVERRIDE1 struct + */ + +#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE 1 + +#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT 0 +#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT 1 +#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT 2 +#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT 3 +#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT 4 +#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT 5 +#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT 6 +#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT 7 +#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT 8 +#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT 9 +#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT 10 +#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT 11 +#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT 12 +#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT 13 +#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT 14 +#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT 15 +#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT 16 +#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT 17 +#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT 18 +#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT 19 +#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT 20 +#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT 21 +#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT 22 +#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT 23 +#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT 24 +#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT 25 +#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT 26 +#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT 27 +#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT 28 +#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT 29 +#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT 30 +#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT 31 + +#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK 0x00000001 +#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK 0x00000002 +#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK 0x00000004 +#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK 0x00000008 +#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK 0x00000010 +#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK 0x00000020 +#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000040 +#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK 0x00000080 +#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK 0x00000100 +#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK 0x00000200 +#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK 0x00000400 +#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK 0x00000800 +#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK 0x00001000 +#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK 0x00002000 +#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK 0x00004000 +#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK 0x00008000 +#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK 0x00010000 +#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK 0x00020000 +#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK 0x00040000 +#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK 0x00080000 +#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK 0x00100000 +#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK 0x00200000 +#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK 0x00400000 +#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK 0x00800000 +#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK 0x01000000 +#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK 0x02000000 +#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK 0x04000000 +#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK 0x08000000 +#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK 0x10000000 +#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK 0x20000000 +#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK 0x40000000 +#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK 0x80000000 + +#define RBBM_PM_OVERRIDE1_MASK \ + (RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) + +#define RBBM_PM_OVERRIDE1(rbbm_ahbclk_pm_override, sc_reg_sclk_pm_override, sc_sclk_pm_override, sp_top_sclk_pm_override, sp_v0_sclk_pm_override, sq_reg_sclk_pm_override, sq_reg_fifos_sclk_pm_override, sq_const_mem_sclk_pm_override, sq_sq_sclk_pm_override, sx_sclk_pm_override, sx_reg_sclk_pm_override, tcm_tco_sclk_pm_override, tcm_tcm_sclk_pm_override, tcm_tcd_sclk_pm_override, tcm_reg_sclk_pm_override, tpc_tpc_sclk_pm_override, tpc_reg_sclk_pm_override, tcf_tca_sclk_pm_override, tcf_tcb_sclk_pm_override, tcf_tcb_read_sclk_pm_override, tp_tp_sclk_pm_override, tp_reg_sclk_pm_override, cp_g_sclk_pm_override, cp_reg_sclk_pm_override, cp_g_reg_sclk_pm_override, spi_sclk_pm_override, rb_reg_sclk_pm_override, rb_sclk_pm_override, mh_mh_sclk_pm_override, mh_reg_sclk_pm_override, mh_mmu_sclk_pm_override, mh_tcroq_sclk_pm_override) \ + ((rbbm_ahbclk_pm_override << RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT) | \ + (sc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (sc_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT) | \ + (sp_top_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT) | \ + (sp_v0_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT) | \ + (sq_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (sq_reg_fifos_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT) | \ + (sq_const_mem_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT) | \ + (sq_sq_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT) | \ + (sx_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT) | \ + (sx_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcm_tco_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcm_tcm_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcm_tcd_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcm_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (tpc_tpc_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT) | \ + (tpc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcf_tca_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcf_tcb_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcf_tcb_read_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT) | \ + (tp_tp_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT) | \ + (tp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (cp_g_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT) | \ + (cp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (cp_g_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (spi_sclk_pm_override << RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT) | \ + (rb_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (rb_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT) | \ + (mh_mh_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT) | \ + (mh_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (mh_mmu_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT) | \ + (mh_tcroq_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT)) + +#define RBBM_PM_OVERRIDE1_GET_RBBM_AHBCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SC_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SP_TOP_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SP_V0_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SQ_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SQ_REG_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SQ_CONST_MEM_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SQ_SQ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SX_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SX_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCM_TCO_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCM_TCM_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCM_TCD_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCM_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TPC_TPC_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TPC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCF_TCA_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCF_TCB_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCF_TCB_READ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TP_TP_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_CP_G_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_CP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_CP_G_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SPI_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_RB_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_RB_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_MH_MH_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_MH_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_MH_MMU_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_MH_TCROQ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT) + +#define RBBM_PM_OVERRIDE1_SET_RBBM_AHBCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rbbm_ahbclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK) | (rbbm_ahbclk_pm_override << RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sc_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK) | (sc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SC_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sc_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK) | (sc_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SP_TOP_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sp_top_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK) | (sp_top_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SP_V0_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sp_v0_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK) | (sp_v0_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SQ_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK) | (sq_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SQ_REG_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_reg_fifos_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK) | (sq_reg_fifos_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SQ_CONST_MEM_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_const_mem_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK) | (sq_const_mem_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SQ_SQ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_sq_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK) | (sq_sq_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SX_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sx_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK) | (sx_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SX_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sx_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK) | (sx_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCM_TCO_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tco_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK) | (tcm_tco_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCM_TCM_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tcm_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK) | (tcm_tcm_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCM_TCD_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tcd_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK) | (tcm_tcd_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCM_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK) | (tcm_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TPC_TPC_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tpc_tpc_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK) | (tpc_tpc_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TPC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tpc_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK) | (tpc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCF_TCA_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tca_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK) | (tcf_tca_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCF_TCB_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tcb_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK) | (tcf_tcb_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCF_TCB_READ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tcb_read_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK) | (tcf_tcb_read_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TP_TP_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tp_tp_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK) | (tp_tp_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tp_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK) | (tp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_CP_G_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_g_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK) | (cp_g_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_CP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK) | (cp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_CP_G_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_g_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK) | (cp_g_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SPI_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, spi_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK) | (spi_sclk_pm_override << RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_RB_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rb_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK) | (rb_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_RB_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rb_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK) | (rb_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_MH_MH_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_mh_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK) | (mh_mh_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_MH_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK) | (mh_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_MH_MMU_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_mmu_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK) | (mh_mmu_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_MH_TCROQ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_tcroq_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) | (mh_tcroq_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_pm_override1_t { + unsigned int rbbm_ahbclk_pm_override : RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE; + unsigned int sc_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int sc_sclk_pm_override : RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE; + unsigned int sp_top_sclk_pm_override : RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE; + unsigned int sp_v0_sclk_pm_override : RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_reg_fifos_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_const_mem_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_sq_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE; + unsigned int sx_sclk_pm_override : RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE; + unsigned int sx_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tco_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tcm_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tcd_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tpc_tpc_sclk_pm_override : RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE; + unsigned int tpc_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tca_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tcb_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tcb_read_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE; + unsigned int tp_tp_sclk_pm_override : RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE; + unsigned int tp_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_g_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_g_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int spi_sclk_pm_override : RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE; + unsigned int rb_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int rb_sclk_pm_override : RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_mh_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_mmu_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_tcroq_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE; + } rbbm_pm_override1_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_pm_override1_t { + unsigned int mh_tcroq_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_mmu_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_mh_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE; + unsigned int rb_sclk_pm_override : RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE; + unsigned int rb_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int spi_sclk_pm_override : RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_g_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_g_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE; + unsigned int tp_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tp_tp_sclk_pm_override : RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tcb_read_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tcb_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tca_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE; + unsigned int tpc_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tpc_tpc_sclk_pm_override : RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tcd_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tcm_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tco_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE; + unsigned int sx_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int sx_sclk_pm_override : RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_sq_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_const_mem_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_reg_fifos_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int sp_v0_sclk_pm_override : RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE; + unsigned int sp_top_sclk_pm_override : RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE; + unsigned int sc_sclk_pm_override : RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE; + unsigned int sc_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int rbbm_ahbclk_pm_override : RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE; + } rbbm_pm_override1_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_pm_override1_t f; +} rbbm_pm_override1_u; + + +/* + * RBBM_PM_OVERRIDE2 struct + */ + +#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE 1 + +#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT 0 +#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT 1 +#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT 2 +#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT 3 +#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT 4 +#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT 5 +#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT 6 +#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT 7 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT 8 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT 9 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT 10 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT 11 + +#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK 0x00000001 +#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK 0x00000002 +#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK 0x00000004 +#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK 0x00000008 +#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000010 +#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK 0x00000020 +#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK 0x00000040 +#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK 0x00000080 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK 0x00000100 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK 0x00000200 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK 0x00000400 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK 0x00000800 + +#define RBBM_PM_OVERRIDE2_MASK \ + (RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) + +#define RBBM_PM_OVERRIDE2(pa_reg_sclk_pm_override, pa_pa_sclk_pm_override, pa_ag_sclk_pm_override, vgt_reg_sclk_pm_override, vgt_fifos_sclk_pm_override, vgt_vgt_sclk_pm_override, debug_perf_sclk_pm_override, perm_sclk_pm_override, gc_ga_gmem0_pm_override, gc_ga_gmem1_pm_override, gc_ga_gmem2_pm_override, gc_ga_gmem3_pm_override) \ + ((pa_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (pa_pa_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT) | \ + (pa_ag_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT) | \ + (vgt_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (vgt_fifos_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT) | \ + (vgt_vgt_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT) | \ + (debug_perf_sclk_pm_override << RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT) | \ + (perm_sclk_pm_override << RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT) | \ + (gc_ga_gmem0_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT) | \ + (gc_ga_gmem1_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT) | \ + (gc_ga_gmem2_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT) | \ + (gc_ga_gmem3_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT)) + +#define RBBM_PM_OVERRIDE2_GET_PA_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_PA_PA_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_PA_AG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_VGT_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_VGT_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_VGT_VGT_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_DEBUG_PERF_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_PERM_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM0_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM1_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM2_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM3_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT) + +#define RBBM_PM_OVERRIDE2_SET_PA_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_reg_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK) | (pa_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_PA_PA_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_pa_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK) | (pa_pa_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_PA_AG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_ag_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK) | (pa_ag_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_VGT_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_reg_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK) | (vgt_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_VGT_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_fifos_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK) | (vgt_fifos_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_VGT_VGT_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_vgt_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK) | (vgt_vgt_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_DEBUG_PERF_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, debug_perf_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK) | (debug_perf_sclk_pm_override << RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_PERM_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, perm_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK) | (perm_sclk_pm_override << RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM0_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem0_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK) | (gc_ga_gmem0_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM1_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem1_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK) | (gc_ga_gmem1_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM2_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem2_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK) | (gc_ga_gmem2_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM3_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem3_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) | (gc_ga_gmem3_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_pm_override2_t { + unsigned int pa_reg_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_pa_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_ag_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_reg_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_fifos_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_vgt_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE; + unsigned int debug_perf_sclk_pm_override : RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE; + unsigned int perm_sclk_pm_override : RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem0_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem1_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem2_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem3_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE; + unsigned int : 20; + } rbbm_pm_override2_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_pm_override2_t { + unsigned int : 20; + unsigned int gc_ga_gmem3_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem2_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem1_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem0_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE; + unsigned int perm_sclk_pm_override : RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE; + unsigned int debug_perf_sclk_pm_override : RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_vgt_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_fifos_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_reg_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_ag_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_pa_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_reg_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE; + } rbbm_pm_override2_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_pm_override2_t f; +} rbbm_pm_override2_u; + + +/* + * GC_SYS_IDLE struct + */ + +#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE 16 +#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE 1 + +#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT 0 +#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT 31 + +#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK 0x0000ffff +#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK 0x80000000 + +#define GC_SYS_IDLE_MASK \ + (GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK | \ + GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) + +#define GC_SYS_IDLE(gc_sys_idle_delay, gc_sys_idle_override) \ + ((gc_sys_idle_delay << GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT) | \ + (gc_sys_idle_override << GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT)) + +#define GC_SYS_IDLE_GET_GC_SYS_IDLE_DELAY(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK) >> GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT) +#define GC_SYS_IDLE_GET_GC_SYS_IDLE_OVERRIDE(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) >> GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT) + +#define GC_SYS_IDLE_SET_GC_SYS_IDLE_DELAY(gc_sys_idle_reg, gc_sys_idle_delay) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK) | (gc_sys_idle_delay << GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT) +#define GC_SYS_IDLE_SET_GC_SYS_IDLE_OVERRIDE(gc_sys_idle_reg, gc_sys_idle_override) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) | (gc_sys_idle_override << GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _gc_sys_idle_t { + unsigned int gc_sys_idle_delay : GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE; + unsigned int : 15; + unsigned int gc_sys_idle_override : GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE; + } gc_sys_idle_t; + +#else // !BIGENDIAN_OS + + typedef struct _gc_sys_idle_t { + unsigned int gc_sys_idle_override : GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE; + unsigned int : 15; + unsigned int gc_sys_idle_delay : GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE; + } gc_sys_idle_t; + +#endif + +typedef union { + unsigned int val : 32; + gc_sys_idle_t f; +} gc_sys_idle_u; + + +/* + * NQWAIT_UNTIL struct + */ + +#define NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE 1 + +#define NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT 0 + +#define NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK 0x00000001 + +#define NQWAIT_UNTIL_MASK \ + (NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) + +#define NQWAIT_UNTIL(wait_gui_idle) \ + ((wait_gui_idle << NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT)) + +#define NQWAIT_UNTIL_GET_WAIT_GUI_IDLE(nqwait_until) \ + ((nqwait_until & NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) >> NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT) + +#define NQWAIT_UNTIL_SET_WAIT_GUI_IDLE(nqwait_until_reg, wait_gui_idle) \ + nqwait_until_reg = (nqwait_until_reg & ~NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) | (wait_gui_idle << NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _nqwait_until_t { + unsigned int wait_gui_idle : NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE; + unsigned int : 31; + } nqwait_until_t; + +#else // !BIGENDIAN_OS + + typedef struct _nqwait_until_t { + unsigned int : 31; + unsigned int wait_gui_idle : NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE; + } nqwait_until_t; + +#endif + +typedef union { + unsigned int val : 32; + nqwait_until_t f; +} nqwait_until_u; + + +/* + * RBBM_DEBUG struct + */ + +#define RBBM_DEBUG_IGNORE_RTR_SIZE 1 +#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE 1 +#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE 1 +#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE 1 +#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE 4 +#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE 1 +#define RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE 1 +#define RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE 1 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE 1 +#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE 1 + +#define RBBM_DEBUG_IGNORE_RTR_SHIFT 1 +#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT 2 +#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT 3 +#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT 4 +#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT 8 +#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT 16 +#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT 17 +#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT 18 +#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT 19 +#define RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT 20 +#define RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT 21 +#define RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT 22 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT 23 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT 24 +#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT 31 + +#define RBBM_DEBUG_IGNORE_RTR_MASK 0x00000002 +#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK 0x00000004 +#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK 0x00000008 +#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK 0x00000010 +#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK 0x00000f00 +#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK 0x00010000 +#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK 0x00020000 +#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK 0x00040000 +#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK 0x00080000 +#define RBBM_DEBUG_CP_RBBM_NRTRTR_MASK 0x00100000 +#define RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK 0x00200000 +#define RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK 0x00400000 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK 0x00800000 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK 0x01000000 +#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK 0x80000000 + +#define RBBM_DEBUG_MASK \ + (RBBM_DEBUG_IGNORE_RTR_MASK | \ + RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK | \ + RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK | \ + RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK | \ + RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK | \ + RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK | \ + RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK | \ + RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK | \ + RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK | \ + RBBM_DEBUG_CP_RBBM_NRTRTR_MASK | \ + RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK | \ + RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK | \ + RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK | \ + RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK | \ + RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) + +#define RBBM_DEBUG(ignore_rtr, ignore_cp_sched_wu, ignore_cp_sched_isync, ignore_cp_sched_nq_hi, hysteresis_nrt_gui_active, ignore_rtr_for_hi, ignore_cp_rbbm_nrtrtr_for_hi, ignore_vgt_rbbm_nrtrtr_for_hi, ignore_sq_rbbm_nrtrtr_for_hi, cp_rbbm_nrtrtr, vgt_rbbm_nrtrtr, sq_rbbm_nrtrtr, clients_for_nrt_rtr_for_hi, clients_for_nrt_rtr, ignore_sx_rbbm_busy) \ + ((ignore_rtr << RBBM_DEBUG_IGNORE_RTR_SHIFT) | \ + (ignore_cp_sched_wu << RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT) | \ + (ignore_cp_sched_isync << RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT) | \ + (ignore_cp_sched_nq_hi << RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT) | \ + (hysteresis_nrt_gui_active << RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT) | \ + (ignore_rtr_for_hi << RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT) | \ + (ignore_cp_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT) | \ + (ignore_vgt_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT) | \ + (ignore_sq_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT) | \ + (cp_rbbm_nrtrtr << RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT) | \ + (vgt_rbbm_nrtrtr << RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT) | \ + (sq_rbbm_nrtrtr << RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT) | \ + (clients_for_nrt_rtr_for_hi << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT) | \ + (clients_for_nrt_rtr << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT) | \ + (ignore_sx_rbbm_busy << RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT)) + +#define RBBM_DEBUG_GET_IGNORE_RTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_RTR_MASK) >> RBBM_DEBUG_IGNORE_RTR_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_WU(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_ISYNC(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_NQ_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT) +#define RBBM_DEBUG_GET_HYSTERESIS_NRT_GUI_ACTIVE(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK) >> RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_RTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_CP_RBBM_NRTRTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_VGT_RBBM_NRTRTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_SQ_RBBM_NRTRTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_CP_RBBM_NRTRTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_CP_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_GET_VGT_RBBM_NRTRTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_GET_SQ_RBBM_NRTRTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_GET_CLIENTS_FOR_NRT_RTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK) >> RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_CLIENTS_FOR_NRT_RTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK) >> RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_SX_RBBM_BUSY(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) >> RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT) + +#define RBBM_DEBUG_SET_IGNORE_RTR(rbbm_debug_reg, ignore_rtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_RTR_MASK) | (ignore_rtr << RBBM_DEBUG_IGNORE_RTR_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_WU(rbbm_debug_reg, ignore_cp_sched_wu) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK) | (ignore_cp_sched_wu << RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_ISYNC(rbbm_debug_reg, ignore_cp_sched_isync) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK) | (ignore_cp_sched_isync << RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_NQ_HI(rbbm_debug_reg, ignore_cp_sched_nq_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK) | (ignore_cp_sched_nq_hi << RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT) +#define RBBM_DEBUG_SET_HYSTERESIS_NRT_GUI_ACTIVE(rbbm_debug_reg, hysteresis_nrt_gui_active) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK) | (hysteresis_nrt_gui_active << RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_RTR_FOR_HI(rbbm_debug_reg, ignore_rtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK) | (ignore_rtr_for_hi << RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_CP_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_cp_rbbm_nrtrtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_cp_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_VGT_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_vgt_rbbm_nrtrtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_vgt_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_SQ_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_sq_rbbm_nrtrtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_sq_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_CP_RBBM_NRTRTR(rbbm_debug_reg, cp_rbbm_nrtrtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CP_RBBM_NRTRTR_MASK) | (cp_rbbm_nrtrtr << RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_SET_VGT_RBBM_NRTRTR(rbbm_debug_reg, vgt_rbbm_nrtrtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK) | (vgt_rbbm_nrtrtr << RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_SET_SQ_RBBM_NRTRTR(rbbm_debug_reg, sq_rbbm_nrtrtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK) | (sq_rbbm_nrtrtr << RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_SET_CLIENTS_FOR_NRT_RTR_FOR_HI(rbbm_debug_reg, clients_for_nrt_rtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK) | (clients_for_nrt_rtr_for_hi << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_CLIENTS_FOR_NRT_RTR(rbbm_debug_reg, clients_for_nrt_rtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK) | (clients_for_nrt_rtr << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_SX_RBBM_BUSY(rbbm_debug_reg, ignore_sx_rbbm_busy) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) | (ignore_sx_rbbm_busy << RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_debug_t { + unsigned int : 1; + unsigned int ignore_rtr : RBBM_DEBUG_IGNORE_RTR_SIZE; + unsigned int ignore_cp_sched_wu : RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE; + unsigned int ignore_cp_sched_isync : RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE; + unsigned int ignore_cp_sched_nq_hi : RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE; + unsigned int : 3; + unsigned int hysteresis_nrt_gui_active : RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE; + unsigned int : 4; + unsigned int ignore_rtr_for_hi : RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE; + unsigned int ignore_cp_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_vgt_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_sq_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int cp_rbbm_nrtrtr : RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE; + unsigned int vgt_rbbm_nrtrtr : RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE; + unsigned int sq_rbbm_nrtrtr : RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE; + unsigned int clients_for_nrt_rtr_for_hi : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE; + unsigned int clients_for_nrt_rtr : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE; + unsigned int : 6; + unsigned int ignore_sx_rbbm_busy : RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE; + } rbbm_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_debug_t { + unsigned int ignore_sx_rbbm_busy : RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE; + unsigned int : 6; + unsigned int clients_for_nrt_rtr : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE; + unsigned int clients_for_nrt_rtr_for_hi : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE; + unsigned int sq_rbbm_nrtrtr : RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE; + unsigned int vgt_rbbm_nrtrtr : RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE; + unsigned int cp_rbbm_nrtrtr : RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE; + unsigned int ignore_sq_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_vgt_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_cp_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_rtr_for_hi : RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE; + unsigned int : 4; + unsigned int hysteresis_nrt_gui_active : RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE; + unsigned int : 3; + unsigned int ignore_cp_sched_nq_hi : RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE; + unsigned int ignore_cp_sched_isync : RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE; + unsigned int ignore_cp_sched_wu : RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE; + unsigned int ignore_rtr : RBBM_DEBUG_IGNORE_RTR_SIZE; + unsigned int : 1; + } rbbm_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_debug_t f; +} rbbm_debug_u; + + +/* + * RBBM_READ_ERROR struct + */ + +#define RBBM_READ_ERROR_READ_ADDRESS_SIZE 15 +#define RBBM_READ_ERROR_READ_REQUESTER_SIZE 1 +#define RBBM_READ_ERROR_READ_ERROR_SIZE 1 + +#define RBBM_READ_ERROR_READ_ADDRESS_SHIFT 2 +#define RBBM_READ_ERROR_READ_REQUESTER_SHIFT 30 +#define RBBM_READ_ERROR_READ_ERROR_SHIFT 31 + +#define RBBM_READ_ERROR_READ_ADDRESS_MASK 0x0001fffc +#define RBBM_READ_ERROR_READ_REQUESTER_MASK 0x40000000 +#define RBBM_READ_ERROR_READ_ERROR_MASK 0x80000000 + +#define RBBM_READ_ERROR_MASK \ + (RBBM_READ_ERROR_READ_ADDRESS_MASK | \ + RBBM_READ_ERROR_READ_REQUESTER_MASK | \ + RBBM_READ_ERROR_READ_ERROR_MASK) + +#define RBBM_READ_ERROR(read_address, read_requester, read_error) \ + ((read_address << RBBM_READ_ERROR_READ_ADDRESS_SHIFT) | \ + (read_requester << RBBM_READ_ERROR_READ_REQUESTER_SHIFT) | \ + (read_error << RBBM_READ_ERROR_READ_ERROR_SHIFT)) + +#define RBBM_READ_ERROR_GET_READ_ADDRESS(rbbm_read_error) \ + ((rbbm_read_error & RBBM_READ_ERROR_READ_ADDRESS_MASK) >> RBBM_READ_ERROR_READ_ADDRESS_SHIFT) +#define RBBM_READ_ERROR_GET_READ_REQUESTER(rbbm_read_error) \ + ((rbbm_read_error & RBBM_READ_ERROR_READ_REQUESTER_MASK) >> RBBM_READ_ERROR_READ_REQUESTER_SHIFT) +#define RBBM_READ_ERROR_GET_READ_ERROR(rbbm_read_error) \ + ((rbbm_read_error & RBBM_READ_ERROR_READ_ERROR_MASK) >> RBBM_READ_ERROR_READ_ERROR_SHIFT) + +#define RBBM_READ_ERROR_SET_READ_ADDRESS(rbbm_read_error_reg, read_address) \ + rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_ADDRESS_MASK) | (read_address << RBBM_READ_ERROR_READ_ADDRESS_SHIFT) +#define RBBM_READ_ERROR_SET_READ_REQUESTER(rbbm_read_error_reg, read_requester) \ + rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_REQUESTER_MASK) | (read_requester << RBBM_READ_ERROR_READ_REQUESTER_SHIFT) +#define RBBM_READ_ERROR_SET_READ_ERROR(rbbm_read_error_reg, read_error) \ + rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_ERROR_MASK) | (read_error << RBBM_READ_ERROR_READ_ERROR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_read_error_t { + unsigned int : 2; + unsigned int read_address : RBBM_READ_ERROR_READ_ADDRESS_SIZE; + unsigned int : 13; + unsigned int read_requester : RBBM_READ_ERROR_READ_REQUESTER_SIZE; + unsigned int read_error : RBBM_READ_ERROR_READ_ERROR_SIZE; + } rbbm_read_error_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_read_error_t { + unsigned int read_error : RBBM_READ_ERROR_READ_ERROR_SIZE; + unsigned int read_requester : RBBM_READ_ERROR_READ_REQUESTER_SIZE; + unsigned int : 13; + unsigned int read_address : RBBM_READ_ERROR_READ_ADDRESS_SIZE; + unsigned int : 2; + } rbbm_read_error_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_read_error_t f; +} rbbm_read_error_u; + + +/* + * RBBM_WAIT_IDLE_CLOCKS struct + */ + +#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE 8 + +#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT 0 + +#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK 0x000000ff + +#define RBBM_WAIT_IDLE_CLOCKS_MASK \ + (RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) + +#define RBBM_WAIT_IDLE_CLOCKS(wait_idle_clocks_nrt) \ + ((wait_idle_clocks_nrt << RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT)) + +#define RBBM_WAIT_IDLE_CLOCKS_GET_WAIT_IDLE_CLOCKS_NRT(rbbm_wait_idle_clocks) \ + ((rbbm_wait_idle_clocks & RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) >> RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT) + +#define RBBM_WAIT_IDLE_CLOCKS_SET_WAIT_IDLE_CLOCKS_NRT(rbbm_wait_idle_clocks_reg, wait_idle_clocks_nrt) \ + rbbm_wait_idle_clocks_reg = (rbbm_wait_idle_clocks_reg & ~RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) | (wait_idle_clocks_nrt << RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_wait_idle_clocks_t { + unsigned int wait_idle_clocks_nrt : RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE; + unsigned int : 24; + } rbbm_wait_idle_clocks_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_wait_idle_clocks_t { + unsigned int : 24; + unsigned int wait_idle_clocks_nrt : RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE; + } rbbm_wait_idle_clocks_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_wait_idle_clocks_t f; +} rbbm_wait_idle_clocks_u; + + +/* + * RBBM_INT_CNTL struct + */ + +#define RBBM_INT_CNTL_RDERR_INT_MASK_SIZE 1 +#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE 1 +#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE 1 + +#define RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT 0 +#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT 1 +#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT 19 + +#define RBBM_INT_CNTL_RDERR_INT_MASK_MASK 0x00000001 +#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK 0x00000002 +#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK 0x00080000 + +#define RBBM_INT_CNTL_MASK \ + (RBBM_INT_CNTL_RDERR_INT_MASK_MASK | \ + RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK | \ + RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) + +#define RBBM_INT_CNTL(rderr_int_mask, display_update_int_mask, gui_idle_int_mask) \ + ((rderr_int_mask << RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT) | \ + (display_update_int_mask << RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT) | \ + (gui_idle_int_mask << RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT)) + +#define RBBM_INT_CNTL_GET_RDERR_INT_MASK(rbbm_int_cntl) \ + ((rbbm_int_cntl & RBBM_INT_CNTL_RDERR_INT_MASK_MASK) >> RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT) +#define RBBM_INT_CNTL_GET_DISPLAY_UPDATE_INT_MASK(rbbm_int_cntl) \ + ((rbbm_int_cntl & RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK) >> RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT) +#define RBBM_INT_CNTL_GET_GUI_IDLE_INT_MASK(rbbm_int_cntl) \ + ((rbbm_int_cntl & RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) >> RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT) + +#define RBBM_INT_CNTL_SET_RDERR_INT_MASK(rbbm_int_cntl_reg, rderr_int_mask) \ + rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_RDERR_INT_MASK_MASK) | (rderr_int_mask << RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT) +#define RBBM_INT_CNTL_SET_DISPLAY_UPDATE_INT_MASK(rbbm_int_cntl_reg, display_update_int_mask) \ + rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK) | (display_update_int_mask << RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT) +#define RBBM_INT_CNTL_SET_GUI_IDLE_INT_MASK(rbbm_int_cntl_reg, gui_idle_int_mask) \ + rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) | (gui_idle_int_mask << RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_int_cntl_t { + unsigned int rderr_int_mask : RBBM_INT_CNTL_RDERR_INT_MASK_SIZE; + unsigned int display_update_int_mask : RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE; + unsigned int : 17; + unsigned int gui_idle_int_mask : RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE; + unsigned int : 12; + } rbbm_int_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_int_cntl_t { + unsigned int : 12; + unsigned int gui_idle_int_mask : RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE; + unsigned int : 17; + unsigned int display_update_int_mask : RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE; + unsigned int rderr_int_mask : RBBM_INT_CNTL_RDERR_INT_MASK_SIZE; + } rbbm_int_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_int_cntl_t f; +} rbbm_int_cntl_u; + + +/* + * RBBM_INT_STATUS struct + */ + +#define RBBM_INT_STATUS_RDERR_INT_STAT_SIZE 1 +#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE 1 +#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE 1 + +#define RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT 0 +#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT 1 +#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT 19 + +#define RBBM_INT_STATUS_RDERR_INT_STAT_MASK 0x00000001 +#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK 0x00000002 +#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK 0x00080000 + +#define RBBM_INT_STATUS_MASK \ + (RBBM_INT_STATUS_RDERR_INT_STAT_MASK | \ + RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK | \ + RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) + +#define RBBM_INT_STATUS(rderr_int_stat, display_update_int_stat, gui_idle_int_stat) \ + ((rderr_int_stat << RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT) | \ + (display_update_int_stat << RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT) | \ + (gui_idle_int_stat << RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT)) + +#define RBBM_INT_STATUS_GET_RDERR_INT_STAT(rbbm_int_status) \ + ((rbbm_int_status & RBBM_INT_STATUS_RDERR_INT_STAT_MASK) >> RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT) +#define RBBM_INT_STATUS_GET_DISPLAY_UPDATE_INT_STAT(rbbm_int_status) \ + ((rbbm_int_status & RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK) >> RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT) +#define RBBM_INT_STATUS_GET_GUI_IDLE_INT_STAT(rbbm_int_status) \ + ((rbbm_int_status & RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) >> RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT) + +#define RBBM_INT_STATUS_SET_RDERR_INT_STAT(rbbm_int_status_reg, rderr_int_stat) \ + rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_RDERR_INT_STAT_MASK) | (rderr_int_stat << RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT) +#define RBBM_INT_STATUS_SET_DISPLAY_UPDATE_INT_STAT(rbbm_int_status_reg, display_update_int_stat) \ + rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK) | (display_update_int_stat << RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT) +#define RBBM_INT_STATUS_SET_GUI_IDLE_INT_STAT(rbbm_int_status_reg, gui_idle_int_stat) \ + rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) | (gui_idle_int_stat << RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_int_status_t { + unsigned int rderr_int_stat : RBBM_INT_STATUS_RDERR_INT_STAT_SIZE; + unsigned int display_update_int_stat : RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE; + unsigned int : 17; + unsigned int gui_idle_int_stat : RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE; + unsigned int : 12; + } rbbm_int_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_int_status_t { + unsigned int : 12; + unsigned int gui_idle_int_stat : RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE; + unsigned int : 17; + unsigned int display_update_int_stat : RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE; + unsigned int rderr_int_stat : RBBM_INT_STATUS_RDERR_INT_STAT_SIZE; + } rbbm_int_status_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_int_status_t f; +} rbbm_int_status_u; + + +/* + * RBBM_INT_ACK struct + */ + +#define RBBM_INT_ACK_RDERR_INT_ACK_SIZE 1 +#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE 1 +#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE 1 + +#define RBBM_INT_ACK_RDERR_INT_ACK_SHIFT 0 +#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT 1 +#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT 19 + +#define RBBM_INT_ACK_RDERR_INT_ACK_MASK 0x00000001 +#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK 0x00000002 +#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK 0x00080000 + +#define RBBM_INT_ACK_MASK \ + (RBBM_INT_ACK_RDERR_INT_ACK_MASK | \ + RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK | \ + RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) + +#define RBBM_INT_ACK(rderr_int_ack, display_update_int_ack, gui_idle_int_ack) \ + ((rderr_int_ack << RBBM_INT_ACK_RDERR_INT_ACK_SHIFT) | \ + (display_update_int_ack << RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT) | \ + (gui_idle_int_ack << RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT)) + +#define RBBM_INT_ACK_GET_RDERR_INT_ACK(rbbm_int_ack) \ + ((rbbm_int_ack & RBBM_INT_ACK_RDERR_INT_ACK_MASK) >> RBBM_INT_ACK_RDERR_INT_ACK_SHIFT) +#define RBBM_INT_ACK_GET_DISPLAY_UPDATE_INT_ACK(rbbm_int_ack) \ + ((rbbm_int_ack & RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK) >> RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT) +#define RBBM_INT_ACK_GET_GUI_IDLE_INT_ACK(rbbm_int_ack) \ + ((rbbm_int_ack & RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) >> RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT) + +#define RBBM_INT_ACK_SET_RDERR_INT_ACK(rbbm_int_ack_reg, rderr_int_ack) \ + rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_RDERR_INT_ACK_MASK) | (rderr_int_ack << RBBM_INT_ACK_RDERR_INT_ACK_SHIFT) +#define RBBM_INT_ACK_SET_DISPLAY_UPDATE_INT_ACK(rbbm_int_ack_reg, display_update_int_ack) \ + rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK) | (display_update_int_ack << RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT) +#define RBBM_INT_ACK_SET_GUI_IDLE_INT_ACK(rbbm_int_ack_reg, gui_idle_int_ack) \ + rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) | (gui_idle_int_ack << RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_int_ack_t { + unsigned int rderr_int_ack : RBBM_INT_ACK_RDERR_INT_ACK_SIZE; + unsigned int display_update_int_ack : RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE; + unsigned int : 17; + unsigned int gui_idle_int_ack : RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE; + unsigned int : 12; + } rbbm_int_ack_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_int_ack_t { + unsigned int : 12; + unsigned int gui_idle_int_ack : RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE; + unsigned int : 17; + unsigned int display_update_int_ack : RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE; + unsigned int rderr_int_ack : RBBM_INT_ACK_RDERR_INT_ACK_SIZE; + } rbbm_int_ack_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_int_ack_t f; +} rbbm_int_ack_u; + + +/* + * MASTER_INT_SIGNAL struct + */ + +#define MASTER_INT_SIGNAL_MH_INT_STAT_SIZE 1 +#define MASTER_INT_SIGNAL_CP_INT_STAT_SIZE 1 +#define MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE 1 + +#define MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT 5 +#define MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT 30 +#define MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT 31 + +#define MASTER_INT_SIGNAL_MH_INT_STAT_MASK 0x00000020 +#define MASTER_INT_SIGNAL_CP_INT_STAT_MASK 0x40000000 +#define MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK 0x80000000 + +#define MASTER_INT_SIGNAL_MASK \ + (MASTER_INT_SIGNAL_MH_INT_STAT_MASK | \ + MASTER_INT_SIGNAL_CP_INT_STAT_MASK | \ + MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) + +#define MASTER_INT_SIGNAL(mh_int_stat, cp_int_stat, rbbm_int_stat) \ + ((mh_int_stat << MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT) | \ + (cp_int_stat << MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT) | \ + (rbbm_int_stat << MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT)) + +#define MASTER_INT_SIGNAL_GET_MH_INT_STAT(master_int_signal) \ + ((master_int_signal & MASTER_INT_SIGNAL_MH_INT_STAT_MASK) >> MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_GET_CP_INT_STAT(master_int_signal) \ + ((master_int_signal & MASTER_INT_SIGNAL_CP_INT_STAT_MASK) >> MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_GET_RBBM_INT_STAT(master_int_signal) \ + ((master_int_signal & MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) >> MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT) + +#define MASTER_INT_SIGNAL_SET_MH_INT_STAT(master_int_signal_reg, mh_int_stat) \ + master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_MH_INT_STAT_MASK) | (mh_int_stat << MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_SET_CP_INT_STAT(master_int_signal_reg, cp_int_stat) \ + master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_CP_INT_STAT_MASK) | (cp_int_stat << MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_SET_RBBM_INT_STAT(master_int_signal_reg, rbbm_int_stat) \ + master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) | (rbbm_int_stat << MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _master_int_signal_t { + unsigned int : 5; + unsigned int mh_int_stat : MASTER_INT_SIGNAL_MH_INT_STAT_SIZE; + unsigned int : 24; + unsigned int cp_int_stat : MASTER_INT_SIGNAL_CP_INT_STAT_SIZE; + unsigned int rbbm_int_stat : MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE; + } master_int_signal_t; + +#else // !BIGENDIAN_OS + + typedef struct _master_int_signal_t { + unsigned int rbbm_int_stat : MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE; + unsigned int cp_int_stat : MASTER_INT_SIGNAL_CP_INT_STAT_SIZE; + unsigned int : 24; + unsigned int mh_int_stat : MASTER_INT_SIGNAL_MH_INT_STAT_SIZE; + unsigned int : 5; + } master_int_signal_t; + +#endif + +typedef union { + unsigned int val : 32; + master_int_signal_t f; +} master_int_signal_u; + + +/* + * RBBM_PERFCOUNTER1_SELECT struct + */ + +#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE 6 + +#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT 0 + +#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK 0x0000003f + +#define RBBM_PERFCOUNTER1_SELECT_MASK \ + (RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) + +#define RBBM_PERFCOUNTER1_SELECT(perf_count1_sel) \ + ((perf_count1_sel << RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT)) + +#define RBBM_PERFCOUNTER1_SELECT_GET_PERF_COUNT1_SEL(rbbm_perfcounter1_select) \ + ((rbbm_perfcounter1_select & RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) >> RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT) + +#define RBBM_PERFCOUNTER1_SELECT_SET_PERF_COUNT1_SEL(rbbm_perfcounter1_select_reg, perf_count1_sel) \ + rbbm_perfcounter1_select_reg = (rbbm_perfcounter1_select_reg & ~RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) | (perf_count1_sel << RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_select_t { + unsigned int perf_count1_sel : RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE; + unsigned int : 26; + } rbbm_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_select_t { + unsigned int : 26; + unsigned int perf_count1_sel : RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE; + } rbbm_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_perfcounter1_select_t f; +} rbbm_perfcounter1_select_u; + + +/* + * RBBM_PERFCOUNTER1_LO struct + */ + +#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE 32 + +#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT 0 + +#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK 0xffffffff + +#define RBBM_PERFCOUNTER1_LO_MASK \ + (RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) + +#define RBBM_PERFCOUNTER1_LO(perf_count1_lo) \ + ((perf_count1_lo << RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT)) + +#define RBBM_PERFCOUNTER1_LO_GET_PERF_COUNT1_LO(rbbm_perfcounter1_lo) \ + ((rbbm_perfcounter1_lo & RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) >> RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT) + +#define RBBM_PERFCOUNTER1_LO_SET_PERF_COUNT1_LO(rbbm_perfcounter1_lo_reg, perf_count1_lo) \ + rbbm_perfcounter1_lo_reg = (rbbm_perfcounter1_lo_reg & ~RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) | (perf_count1_lo << RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_lo_t { + unsigned int perf_count1_lo : RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE; + } rbbm_perfcounter1_lo_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_lo_t { + unsigned int perf_count1_lo : RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE; + } rbbm_perfcounter1_lo_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_perfcounter1_lo_t f; +} rbbm_perfcounter1_lo_u; + + +/* + * RBBM_PERFCOUNTER1_HI struct + */ + +#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE 16 + +#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT 0 + +#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK 0x0000ffff + +#define RBBM_PERFCOUNTER1_HI_MASK \ + (RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) + +#define RBBM_PERFCOUNTER1_HI(perf_count1_hi) \ + ((perf_count1_hi << RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT)) + +#define RBBM_PERFCOUNTER1_HI_GET_PERF_COUNT1_HI(rbbm_perfcounter1_hi) \ + ((rbbm_perfcounter1_hi & RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) >> RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT) + +#define RBBM_PERFCOUNTER1_HI_SET_PERF_COUNT1_HI(rbbm_perfcounter1_hi_reg, perf_count1_hi) \ + rbbm_perfcounter1_hi_reg = (rbbm_perfcounter1_hi_reg & ~RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) | (perf_count1_hi << RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_hi_t { + unsigned int perf_count1_hi : RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE; + unsigned int : 16; + } rbbm_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_count1_hi : RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE; + } rbbm_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_perfcounter1_hi_t f; +} rbbm_perfcounter1_hi_u; + + +#endif + + +#if !defined (_MH_FIDDLE_H) +#define _MH_FIDDLE_H + +/***************************************************************************************************************** + * + * mh_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * MH_ARBITER_CONFIG struct + */ + +#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE 6 +#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE 1 +#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE 1 +#define MH_ARBITER_CONFIG_PAGE_SIZE_SIZE 3 +#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE 6 +#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE 1 + +#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT 0 +#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT 6 +#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT 7 +#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT 8 +#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT 9 +#define MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT 10 +#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT 13 +#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT 14 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT 15 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT 16 +#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT 22 +#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT 23 +#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT 24 +#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT 25 + +#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK 0x0000003f +#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK 0x00000040 +#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK 0x00000080 +#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK 0x00000100 +#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK 0x00000200 +#define MH_ARBITER_CONFIG_PAGE_SIZE_MASK 0x00001c00 +#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00002000 +#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK 0x00004000 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK 0x00008000 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK 0x003f0000 +#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK 0x00400000 +#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK 0x00800000 +#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK 0x01000000 +#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK 0x02000000 + +#define MH_ARBITER_CONFIG_MASK \ + (MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK | \ + MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK | \ + MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK | \ + MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK | \ + MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK | \ + MH_ARBITER_CONFIG_PAGE_SIZE_MASK | \ + MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK | \ + MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK | \ + MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK | \ + MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK | \ + MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK | \ + MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK | \ + MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK | \ + MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK) + +#define MH_ARBITER_CONFIG(same_page_limit, same_page_granularity, l1_arb_enable, l1_arb_hold_enable, l2_arb_control, page_size, tc_reorder_enable, tc_arb_hold_enable, in_flight_limit_enable, in_flight_limit, cp_clnt_enable, vgt_clnt_enable, tc_clnt_enable, rb_clnt_enable) \ + ((same_page_limit << MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT) | \ + (same_page_granularity << MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT) | \ + (l1_arb_enable << MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT) | \ + (l1_arb_hold_enable << MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT) | \ + (l2_arb_control << MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT) | \ + (page_size << MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT) | \ + (tc_reorder_enable << MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) | \ + (tc_arb_hold_enable << MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT) | \ + (in_flight_limit_enable << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT) | \ + (in_flight_limit << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT) | \ + (cp_clnt_enable << MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT) | \ + (vgt_clnt_enable << MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT) | \ + (tc_clnt_enable << MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT) | \ + (rb_clnt_enable << MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT)) + +#define MH_ARBITER_CONFIG_GET_SAME_PAGE_LIMIT(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK) >> MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT) +#define MH_ARBITER_CONFIG_GET_SAME_PAGE_GRANULARITY(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK) >> MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT) +#define MH_ARBITER_CONFIG_GET_L1_ARB_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK) >> MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_L1_ARB_HOLD_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK) >> MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_L2_ARB_CONTROL(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK) >> MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT) +#define MH_ARBITER_CONFIG_GET_PAGE_SIZE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_PAGE_SIZE_MASK) >> MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT) +#define MH_ARBITER_CONFIG_GET_TC_REORDER_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_TC_ARB_HOLD_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_IN_FLIGHT_LIMIT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK) >> MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_IN_FLIGHT_LIMIT(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK) >> MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT) +#define MH_ARBITER_CONFIG_GET_CP_CLNT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_VGT_CLNT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_TC_CLNT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_RB_CLNT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT) + +#define MH_ARBITER_CONFIG_SET_SAME_PAGE_LIMIT(mh_arbiter_config_reg, same_page_limit) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK) | (same_page_limit << MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT) +#define MH_ARBITER_CONFIG_SET_SAME_PAGE_GRANULARITY(mh_arbiter_config_reg, same_page_granularity) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK) | (same_page_granularity << MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT) +#define MH_ARBITER_CONFIG_SET_L1_ARB_ENABLE(mh_arbiter_config_reg, l1_arb_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK) | (l1_arb_enable << MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_L1_ARB_HOLD_ENABLE(mh_arbiter_config_reg, l1_arb_hold_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK) | (l1_arb_hold_enable << MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_L2_ARB_CONTROL(mh_arbiter_config_reg, l2_arb_control) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK) | (l2_arb_control << MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT) +#define MH_ARBITER_CONFIG_SET_PAGE_SIZE(mh_arbiter_config_reg, page_size) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_PAGE_SIZE_MASK) | (page_size << MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT) +#define MH_ARBITER_CONFIG_SET_TC_REORDER_ENABLE(mh_arbiter_config_reg, tc_reorder_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) | (tc_reorder_enable << MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_TC_ARB_HOLD_ENABLE(mh_arbiter_config_reg, tc_arb_hold_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK) | (tc_arb_hold_enable << MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_IN_FLIGHT_LIMIT_ENABLE(mh_arbiter_config_reg, in_flight_limit_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK) | (in_flight_limit_enable << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_IN_FLIGHT_LIMIT(mh_arbiter_config_reg, in_flight_limit) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK) | (in_flight_limit << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT) +#define MH_ARBITER_CONFIG_SET_CP_CLNT_ENABLE(mh_arbiter_config_reg, cp_clnt_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK) | (cp_clnt_enable << MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_VGT_CLNT_ENABLE(mh_arbiter_config_reg, vgt_clnt_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK) | (vgt_clnt_enable << MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_TC_CLNT_ENABLE(mh_arbiter_config_reg, tc_clnt_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK) | (tc_clnt_enable << MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_RB_CLNT_ENABLE(mh_arbiter_config_reg, rb_clnt_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK) | (rb_clnt_enable << MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_arbiter_config_t { + unsigned int same_page_limit : MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE; + unsigned int same_page_granularity : MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE; + unsigned int l1_arb_enable : MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE; + unsigned int l1_arb_hold_enable : MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE; + unsigned int l2_arb_control : MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE; + unsigned int page_size : MH_ARBITER_CONFIG_PAGE_SIZE_SIZE; + unsigned int tc_reorder_enable : MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE; + unsigned int tc_arb_hold_enable : MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE; + unsigned int in_flight_limit_enable : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE; + unsigned int in_flight_limit : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE; + unsigned int cp_clnt_enable : MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE; + unsigned int vgt_clnt_enable : MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE; + unsigned int tc_clnt_enable : MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE; + unsigned int rb_clnt_enable : MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE; + unsigned int : 6; + } mh_arbiter_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_arbiter_config_t { + unsigned int : 6; + unsigned int rb_clnt_enable : MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE; + unsigned int tc_clnt_enable : MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE; + unsigned int vgt_clnt_enable : MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE; + unsigned int cp_clnt_enable : MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE; + unsigned int in_flight_limit : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE; + unsigned int in_flight_limit_enable : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE; + unsigned int tc_arb_hold_enable : MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE; + unsigned int tc_reorder_enable : MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE; + unsigned int page_size : MH_ARBITER_CONFIG_PAGE_SIZE_SIZE; + unsigned int l2_arb_control : MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE; + unsigned int l1_arb_hold_enable : MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE; + unsigned int l1_arb_enable : MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE; + unsigned int same_page_granularity : MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE; + unsigned int same_page_limit : MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE; + } mh_arbiter_config_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_arbiter_config_t f; +} mh_arbiter_config_u; + + +/* + * MH_CLNT_AXI_ID_REUSE struct + */ + +#define MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE 3 +#define MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE 1 +#define MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE 3 +#define MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE 1 +#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3 + +#define MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT 0 +#define MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT 3 +#define MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT 4 +#define MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT 7 +#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 8 + +#define MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK 0x00000007 +#define MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK 0x00000008 +#define MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK 0x00000070 +#define MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK 0x00000080 +#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x00000700 + +#define MH_CLNT_AXI_ID_REUSE_MASK \ + (MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK | \ + MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK | \ + MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK | \ + MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK | \ + MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) + +#define MH_CLNT_AXI_ID_REUSE(cpw_id, reserved1, rbw_id, reserved2, mmur_id) \ + ((cpw_id << MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT) | \ + (reserved1 << MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT) | \ + (rbw_id << MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT) | \ + (reserved2 << MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT) | \ + (mmur_id << MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)) + +#define MH_CLNT_AXI_ID_REUSE_GET_CPw_ID(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED1(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_RBw_ID(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED2(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_MMUr_ID(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) + +#define MH_CLNT_AXI_ID_REUSE_SET_CPw_ID(mh_clnt_axi_id_reuse_reg, cpw_id) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK) | (cpw_id << MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED1(mh_clnt_axi_id_reuse_reg, reserved1) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK) | (reserved1 << MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_RBw_ID(mh_clnt_axi_id_reuse_reg, rbw_id) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK) | (rbw_id << MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED2(mh_clnt_axi_id_reuse_reg, reserved2) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK) | (reserved2 << MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_MMUr_ID(mh_clnt_axi_id_reuse_reg, mmur_id) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mmur_id << MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_clnt_axi_id_reuse_t { + unsigned int cpw_id : MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE; + unsigned int reserved1 : MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE; + unsigned int rbw_id : MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE; + unsigned int reserved2 : MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE; + unsigned int mmur_id : MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int : 21; + } mh_clnt_axi_id_reuse_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_clnt_axi_id_reuse_t { + unsigned int : 21; + unsigned int mmur_id : MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int reserved2 : MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE; + unsigned int rbw_id : MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE; + unsigned int reserved1 : MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE; + unsigned int cpw_id : MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE; + } mh_clnt_axi_id_reuse_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_clnt_axi_id_reuse_t f; +} mh_clnt_axi_id_reuse_u; + + +/* + * MH_INTERRUPT_MASK struct + */ + +#define MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE 1 +#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE 1 +#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE 1 + +#define MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT 0 +#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT 1 +#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT 2 + +#define MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK 0x00000001 +#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK 0x00000002 +#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK 0x00000004 + +#define MH_INTERRUPT_MASK_MASK \ + (MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK | \ + MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK | \ + MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) + +#define MH_INTERRUPT_MASK(axi_read_error, axi_write_error, mmu_page_fault) \ + ((axi_read_error << MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT) | \ + (axi_write_error << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT) | \ + (mmu_page_fault << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT)) + +#define MH_INTERRUPT_MASK_GET_AXI_READ_ERROR(mh_interrupt_mask) \ + ((mh_interrupt_mask & MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_MASK_GET_AXI_WRITE_ERROR(mh_interrupt_mask) \ + ((mh_interrupt_mask & MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_MASK_GET_MMU_PAGE_FAULT(mh_interrupt_mask) \ + ((mh_interrupt_mask & MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT) + +#define MH_INTERRUPT_MASK_SET_AXI_READ_ERROR(mh_interrupt_mask_reg, axi_read_error) \ + mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_MASK_SET_AXI_WRITE_ERROR(mh_interrupt_mask_reg, axi_write_error) \ + mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_MASK_SET_MMU_PAGE_FAULT(mh_interrupt_mask_reg, mmu_page_fault) \ + mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_interrupt_mask_t { + unsigned int axi_read_error : MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE; + unsigned int mmu_page_fault : MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE; + unsigned int : 29; + } mh_interrupt_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_interrupt_mask_t { + unsigned int : 29; + unsigned int mmu_page_fault : MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE; + unsigned int axi_read_error : MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE; + } mh_interrupt_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_interrupt_mask_t f; +} mh_interrupt_mask_u; + + +/* + * MH_INTERRUPT_STATUS struct + */ + +#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE 1 +#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE 1 +#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE 1 + +#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT 0 +#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT 1 +#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT 2 + +#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK 0x00000001 +#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK 0x00000002 +#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK 0x00000004 + +#define MH_INTERRUPT_STATUS_MASK \ + (MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK | \ + MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK | \ + MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) + +#define MH_INTERRUPT_STATUS(axi_read_error, axi_write_error, mmu_page_fault) \ + ((axi_read_error << MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT) | \ + (axi_write_error << MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT) | \ + (mmu_page_fault << MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT)) + +#define MH_INTERRUPT_STATUS_GET_AXI_READ_ERROR(mh_interrupt_status) \ + ((mh_interrupt_status & MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_STATUS_GET_AXI_WRITE_ERROR(mh_interrupt_status) \ + ((mh_interrupt_status & MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_STATUS_GET_MMU_PAGE_FAULT(mh_interrupt_status) \ + ((mh_interrupt_status & MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT) + +#define MH_INTERRUPT_STATUS_SET_AXI_READ_ERROR(mh_interrupt_status_reg, axi_read_error) \ + mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_STATUS_SET_AXI_WRITE_ERROR(mh_interrupt_status_reg, axi_write_error) \ + mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_STATUS_SET_MMU_PAGE_FAULT(mh_interrupt_status_reg, mmu_page_fault) \ + mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_interrupt_status_t { + unsigned int axi_read_error : MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE; + unsigned int mmu_page_fault : MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE; + unsigned int : 29; + } mh_interrupt_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_interrupt_status_t { + unsigned int : 29; + unsigned int mmu_page_fault : MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE; + unsigned int axi_read_error : MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE; + } mh_interrupt_status_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_interrupt_status_t f; +} mh_interrupt_status_u; + + +/* + * MH_INTERRUPT_CLEAR struct + */ + +#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE 1 +#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE 1 +#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE 1 + +#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT 0 +#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT 1 +#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT 2 + +#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK 0x00000001 +#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK 0x00000002 +#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK 0x00000004 + +#define MH_INTERRUPT_CLEAR_MASK \ + (MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK | \ + MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK | \ + MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) + +#define MH_INTERRUPT_CLEAR(axi_read_error, axi_write_error, mmu_page_fault) \ + ((axi_read_error << MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT) | \ + (axi_write_error << MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT) | \ + (mmu_page_fault << MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT)) + +#define MH_INTERRUPT_CLEAR_GET_AXI_READ_ERROR(mh_interrupt_clear) \ + ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_CLEAR_GET_AXI_WRITE_ERROR(mh_interrupt_clear) \ + ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_CLEAR_GET_MMU_PAGE_FAULT(mh_interrupt_clear) \ + ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT) + +#define MH_INTERRUPT_CLEAR_SET_AXI_READ_ERROR(mh_interrupt_clear_reg, axi_read_error) \ + mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_CLEAR_SET_AXI_WRITE_ERROR(mh_interrupt_clear_reg, axi_write_error) \ + mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_CLEAR_SET_MMU_PAGE_FAULT(mh_interrupt_clear_reg, mmu_page_fault) \ + mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_interrupt_clear_t { + unsigned int axi_read_error : MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE; + unsigned int mmu_page_fault : MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE; + unsigned int : 29; + } mh_interrupt_clear_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_interrupt_clear_t { + unsigned int : 29; + unsigned int mmu_page_fault : MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE; + unsigned int axi_read_error : MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE; + } mh_interrupt_clear_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_interrupt_clear_t f; +} mh_interrupt_clear_u; + + +/* + * MH_AXI_ERROR struct + */ + +#define MH_AXI_ERROR_AXI_READ_ID_SIZE 3 +#define MH_AXI_ERROR_AXI_READ_ERROR_SIZE 1 +#define MH_AXI_ERROR_AXI_WRITE_ID_SIZE 3 +#define MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE 1 + +#define MH_AXI_ERROR_AXI_READ_ID_SHIFT 0 +#define MH_AXI_ERROR_AXI_READ_ERROR_SHIFT 3 +#define MH_AXI_ERROR_AXI_WRITE_ID_SHIFT 4 +#define MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT 7 + +#define MH_AXI_ERROR_AXI_READ_ID_MASK 0x00000007 +#define MH_AXI_ERROR_AXI_READ_ERROR_MASK 0x00000008 +#define MH_AXI_ERROR_AXI_WRITE_ID_MASK 0x00000070 +#define MH_AXI_ERROR_AXI_WRITE_ERROR_MASK 0x00000080 + +#define MH_AXI_ERROR_MASK \ + (MH_AXI_ERROR_AXI_READ_ID_MASK | \ + MH_AXI_ERROR_AXI_READ_ERROR_MASK | \ + MH_AXI_ERROR_AXI_WRITE_ID_MASK | \ + MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) + +#define MH_AXI_ERROR(axi_read_id, axi_read_error, axi_write_id, axi_write_error) \ + ((axi_read_id << MH_AXI_ERROR_AXI_READ_ID_SHIFT) | \ + (axi_read_error << MH_AXI_ERROR_AXI_READ_ERROR_SHIFT) | \ + (axi_write_id << MH_AXI_ERROR_AXI_WRITE_ID_SHIFT) | \ + (axi_write_error << MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT)) + +#define MH_AXI_ERROR_GET_AXI_READ_ID(mh_axi_error) \ + ((mh_axi_error & MH_AXI_ERROR_AXI_READ_ID_MASK) >> MH_AXI_ERROR_AXI_READ_ID_SHIFT) +#define MH_AXI_ERROR_GET_AXI_READ_ERROR(mh_axi_error) \ + ((mh_axi_error & MH_AXI_ERROR_AXI_READ_ERROR_MASK) >> MH_AXI_ERROR_AXI_READ_ERROR_SHIFT) +#define MH_AXI_ERROR_GET_AXI_WRITE_ID(mh_axi_error) \ + ((mh_axi_error & MH_AXI_ERROR_AXI_WRITE_ID_MASK) >> MH_AXI_ERROR_AXI_WRITE_ID_SHIFT) +#define MH_AXI_ERROR_GET_AXI_WRITE_ERROR(mh_axi_error) \ + ((mh_axi_error & MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) >> MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT) + +#define MH_AXI_ERROR_SET_AXI_READ_ID(mh_axi_error_reg, axi_read_id) \ + mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_READ_ID_MASK) | (axi_read_id << MH_AXI_ERROR_AXI_READ_ID_SHIFT) +#define MH_AXI_ERROR_SET_AXI_READ_ERROR(mh_axi_error_reg, axi_read_error) \ + mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_READ_ERROR_MASK) | (axi_read_error << MH_AXI_ERROR_AXI_READ_ERROR_SHIFT) +#define MH_AXI_ERROR_SET_AXI_WRITE_ID(mh_axi_error_reg, axi_write_id) \ + mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_WRITE_ID_MASK) | (axi_write_id << MH_AXI_ERROR_AXI_WRITE_ID_SHIFT) +#define MH_AXI_ERROR_SET_AXI_WRITE_ERROR(mh_axi_error_reg, axi_write_error) \ + mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_axi_error_t { + unsigned int axi_read_id : MH_AXI_ERROR_AXI_READ_ID_SIZE; + unsigned int axi_read_error : MH_AXI_ERROR_AXI_READ_ERROR_SIZE; + unsigned int axi_write_id : MH_AXI_ERROR_AXI_WRITE_ID_SIZE; + unsigned int axi_write_error : MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE; + unsigned int : 24; + } mh_axi_error_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_axi_error_t { + unsigned int : 24; + unsigned int axi_write_error : MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE; + unsigned int axi_write_id : MH_AXI_ERROR_AXI_WRITE_ID_SIZE; + unsigned int axi_read_error : MH_AXI_ERROR_AXI_READ_ERROR_SIZE; + unsigned int axi_read_id : MH_AXI_ERROR_AXI_READ_ID_SIZE; + } mh_axi_error_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_axi_error_t f; +} mh_axi_error_u; + + +/* + * MH_PERFCOUNTER0_SELECT struct + */ + +#define MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define MH_PERFCOUNTER0_SELECT_MASK \ + (MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define MH_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define MH_PERFCOUNTER0_SELECT_GET_PERF_SEL(mh_perfcounter0_select) \ + ((mh_perfcounter0_select & MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define MH_PERFCOUNTER0_SELECT_SET_PERF_SEL(mh_perfcounter0_select_reg, perf_sel) \ + mh_perfcounter0_select_reg = (mh_perfcounter0_select_reg & ~MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter0_select_t { + unsigned int perf_sel : MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } mh_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } mh_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter0_select_t f; +} mh_perfcounter0_select_u; + + +/* + * MH_PERFCOUNTER1_SELECT struct + */ + +#define MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8 + +#define MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0 + +#define MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff + +#define MH_PERFCOUNTER1_SELECT_MASK \ + (MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) + +#define MH_PERFCOUNTER1_SELECT(perf_sel) \ + ((perf_sel << MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)) + +#define MH_PERFCOUNTER1_SELECT_GET_PERF_SEL(mh_perfcounter1_select) \ + ((mh_perfcounter1_select & MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#define MH_PERFCOUNTER1_SELECT_SET_PERF_SEL(mh_perfcounter1_select_reg, perf_sel) \ + mh_perfcounter1_select_reg = (mh_perfcounter1_select_reg & ~MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter1_select_t { + unsigned int perf_sel : MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } mh_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter1_select_t { + unsigned int : 24; + unsigned int perf_sel : MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + } mh_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter1_select_t f; +} mh_perfcounter1_select_u; + + +/* + * MH_PERFCOUNTER0_CONFIG struct + */ + +#define MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE 8 + +#define MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT 0 + +#define MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK 0x000000ff + +#define MH_PERFCOUNTER0_CONFIG_MASK \ + (MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) + +#define MH_PERFCOUNTER0_CONFIG(n_value) \ + ((n_value << MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT)) + +#define MH_PERFCOUNTER0_CONFIG_GET_N_VALUE(mh_perfcounter0_config) \ + ((mh_perfcounter0_config & MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) >> MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT) + +#define MH_PERFCOUNTER0_CONFIG_SET_N_VALUE(mh_perfcounter0_config_reg, n_value) \ + mh_perfcounter0_config_reg = (mh_perfcounter0_config_reg & ~MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) | (n_value << MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter0_config_t { + unsigned int n_value : MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE; + unsigned int : 24; + } mh_perfcounter0_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter0_config_t { + unsigned int : 24; + unsigned int n_value : MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE; + } mh_perfcounter0_config_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter0_config_t f; +} mh_perfcounter0_config_u; + + +/* + * MH_PERFCOUNTER1_CONFIG struct + */ + +#define MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE 8 + +#define MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT 0 + +#define MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK 0x000000ff + +#define MH_PERFCOUNTER1_CONFIG_MASK \ + (MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) + +#define MH_PERFCOUNTER1_CONFIG(n_value) \ + ((n_value << MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT)) + +#define MH_PERFCOUNTER1_CONFIG_GET_N_VALUE(mh_perfcounter1_config) \ + ((mh_perfcounter1_config & MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) >> MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT) + +#define MH_PERFCOUNTER1_CONFIG_SET_N_VALUE(mh_perfcounter1_config_reg, n_value) \ + mh_perfcounter1_config_reg = (mh_perfcounter1_config_reg & ~MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) | (n_value << MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter1_config_t { + unsigned int n_value : MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE; + unsigned int : 24; + } mh_perfcounter1_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter1_config_t { + unsigned int : 24; + unsigned int n_value : MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE; + } mh_perfcounter1_config_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter1_config_t f; +} mh_perfcounter1_config_u; + + +/* + * MH_PERFCOUNTER0_LOW struct + */ + +#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE 32 + +#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT 0 + +#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK 0xffffffff + +#define MH_PERFCOUNTER0_LOW_MASK \ + (MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) + +#define MH_PERFCOUNTER0_LOW(perf_counter_low) \ + ((perf_counter_low << MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT)) + +#define MH_PERFCOUNTER0_LOW_GET_PERF_COUNTER_LOW(mh_perfcounter0_low) \ + ((mh_perfcounter0_low & MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) >> MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT) + +#define MH_PERFCOUNTER0_LOW_SET_PERF_COUNTER_LOW(mh_perfcounter0_low_reg, perf_counter_low) \ + mh_perfcounter0_low_reg = (mh_perfcounter0_low_reg & ~MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) | (perf_counter_low << MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter0_low_t { + unsigned int perf_counter_low : MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE; + } mh_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter0_low_t { + unsigned int perf_counter_low : MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE; + } mh_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter0_low_t f; +} mh_perfcounter0_low_u; + + +/* + * MH_PERFCOUNTER1_LOW struct + */ + +#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE 32 + +#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT 0 + +#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK 0xffffffff + +#define MH_PERFCOUNTER1_LOW_MASK \ + (MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) + +#define MH_PERFCOUNTER1_LOW(perf_counter_low) \ + ((perf_counter_low << MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT)) + +#define MH_PERFCOUNTER1_LOW_GET_PERF_COUNTER_LOW(mh_perfcounter1_low) \ + ((mh_perfcounter1_low & MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) >> MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT) + +#define MH_PERFCOUNTER1_LOW_SET_PERF_COUNTER_LOW(mh_perfcounter1_low_reg, perf_counter_low) \ + mh_perfcounter1_low_reg = (mh_perfcounter1_low_reg & ~MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) | (perf_counter_low << MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter1_low_t { + unsigned int perf_counter_low : MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE; + } mh_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter1_low_t { + unsigned int perf_counter_low : MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE; + } mh_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter1_low_t f; +} mh_perfcounter1_low_u; + + +/* + * MH_PERFCOUNTER0_HI struct + */ + +#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE 16 + +#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT 0 + +#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK 0x0000ffff + +#define MH_PERFCOUNTER0_HI_MASK \ + (MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) + +#define MH_PERFCOUNTER0_HI(perf_counter_hi) \ + ((perf_counter_hi << MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT)) + +#define MH_PERFCOUNTER0_HI_GET_PERF_COUNTER_HI(mh_perfcounter0_hi) \ + ((mh_perfcounter0_hi & MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) >> MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT) + +#define MH_PERFCOUNTER0_HI_SET_PERF_COUNTER_HI(mh_perfcounter0_hi_reg, perf_counter_hi) \ + mh_perfcounter0_hi_reg = (mh_perfcounter0_hi_reg & ~MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) | (perf_counter_hi << MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter0_hi_t { + unsigned int perf_counter_hi : MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE; + unsigned int : 16; + } mh_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_counter_hi : MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE; + } mh_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter0_hi_t f; +} mh_perfcounter0_hi_u; + + +/* + * MH_PERFCOUNTER1_HI struct + */ + +#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE 16 + +#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT 0 + +#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK 0x0000ffff + +#define MH_PERFCOUNTER1_HI_MASK \ + (MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) + +#define MH_PERFCOUNTER1_HI(perf_counter_hi) \ + ((perf_counter_hi << MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT)) + +#define MH_PERFCOUNTER1_HI_GET_PERF_COUNTER_HI(mh_perfcounter1_hi) \ + ((mh_perfcounter1_hi & MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) >> MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT) + +#define MH_PERFCOUNTER1_HI_SET_PERF_COUNTER_HI(mh_perfcounter1_hi_reg, perf_counter_hi) \ + mh_perfcounter1_hi_reg = (mh_perfcounter1_hi_reg & ~MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) | (perf_counter_hi << MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter1_hi_t { + unsigned int perf_counter_hi : MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE; + unsigned int : 16; + } mh_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_counter_hi : MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE; + } mh_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter1_hi_t f; +} mh_perfcounter1_hi_u; + + +/* + * MH_DEBUG_CTRL struct + */ + +#define MH_DEBUG_CTRL_INDEX_SIZE 6 + +#define MH_DEBUG_CTRL_INDEX_SHIFT 0 + +#define MH_DEBUG_CTRL_INDEX_MASK 0x0000003f + +#define MH_DEBUG_CTRL_MASK \ + (MH_DEBUG_CTRL_INDEX_MASK) + +#define MH_DEBUG_CTRL(index) \ + ((index << MH_DEBUG_CTRL_INDEX_SHIFT)) + +#define MH_DEBUG_CTRL_GET_INDEX(mh_debug_ctrl) \ + ((mh_debug_ctrl & MH_DEBUG_CTRL_INDEX_MASK) >> MH_DEBUG_CTRL_INDEX_SHIFT) + +#define MH_DEBUG_CTRL_SET_INDEX(mh_debug_ctrl_reg, index) \ + mh_debug_ctrl_reg = (mh_debug_ctrl_reg & ~MH_DEBUG_CTRL_INDEX_MASK) | (index << MH_DEBUG_CTRL_INDEX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_ctrl_t { + unsigned int index : MH_DEBUG_CTRL_INDEX_SIZE; + unsigned int : 26; + } mh_debug_ctrl_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_ctrl_t { + unsigned int : 26; + unsigned int index : MH_DEBUG_CTRL_INDEX_SIZE; + } mh_debug_ctrl_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_ctrl_t f; +} mh_debug_ctrl_u; + + +/* + * MH_DEBUG_DATA struct + */ + +#define MH_DEBUG_DATA_DATA_SIZE 32 + +#define MH_DEBUG_DATA_DATA_SHIFT 0 + +#define MH_DEBUG_DATA_DATA_MASK 0xffffffff + +#define MH_DEBUG_DATA_MASK \ + (MH_DEBUG_DATA_DATA_MASK) + +#define MH_DEBUG_DATA(data) \ + ((data << MH_DEBUG_DATA_DATA_SHIFT)) + +#define MH_DEBUG_DATA_GET_DATA(mh_debug_data) \ + ((mh_debug_data & MH_DEBUG_DATA_DATA_MASK) >> MH_DEBUG_DATA_DATA_SHIFT) + +#define MH_DEBUG_DATA_SET_DATA(mh_debug_data_reg, data) \ + mh_debug_data_reg = (mh_debug_data_reg & ~MH_DEBUG_DATA_DATA_MASK) | (data << MH_DEBUG_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_data_t { + unsigned int data : MH_DEBUG_DATA_DATA_SIZE; + } mh_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_data_t { + unsigned int data : MH_DEBUG_DATA_DATA_SIZE; + } mh_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_data_t f; +} mh_debug_data_u; + + +/* + * MH_DEBUG_REG00 struct + */ + +#define MH_DEBUG_REG00_MH_BUSY_SIZE 1 +#define MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE 1 +#define MH_DEBUG_REG00_CP_REQUEST_SIZE 1 +#define MH_DEBUG_REG00_VGT_REQUEST_SIZE 1 +#define MH_DEBUG_REG00_TC_REQUEST_SIZE 1 +#define MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE 1 +#define MH_DEBUG_REG00_TC_CAM_FULL_SIZE 1 +#define MH_DEBUG_REG00_TCD_EMPTY_SIZE 1 +#define MH_DEBUG_REG00_TCD_FULL_SIZE 1 +#define MH_DEBUG_REG00_RB_REQUEST_SIZE 1 +#define MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE 1 +#define MH_DEBUG_REG00_ARQ_EMPTY_SIZE 1 +#define MH_DEBUG_REG00_ARQ_FULL_SIZE 1 +#define MH_DEBUG_REG00_WDB_EMPTY_SIZE 1 +#define MH_DEBUG_REG00_WDB_FULL_SIZE 1 +#define MH_DEBUG_REG00_AXI_AVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_AREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_ARVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_ARREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_WVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_WREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_RVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_RREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_BVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_BREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_HALT_REQ_SIZE 1 +#define MH_DEBUG_REG00_AXI_HALT_ACK_SIZE 1 + +#define MH_DEBUG_REG00_MH_BUSY_SHIFT 0 +#define MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT 1 +#define MH_DEBUG_REG00_CP_REQUEST_SHIFT 2 +#define MH_DEBUG_REG00_VGT_REQUEST_SHIFT 3 +#define MH_DEBUG_REG00_TC_REQUEST_SHIFT 4 +#define MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT 5 +#define MH_DEBUG_REG00_TC_CAM_FULL_SHIFT 6 +#define MH_DEBUG_REG00_TCD_EMPTY_SHIFT 7 +#define MH_DEBUG_REG00_TCD_FULL_SHIFT 8 +#define MH_DEBUG_REG00_RB_REQUEST_SHIFT 9 +#define MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT 10 +#define MH_DEBUG_REG00_ARQ_EMPTY_SHIFT 11 +#define MH_DEBUG_REG00_ARQ_FULL_SHIFT 12 +#define MH_DEBUG_REG00_WDB_EMPTY_SHIFT 13 +#define MH_DEBUG_REG00_WDB_FULL_SHIFT 14 +#define MH_DEBUG_REG00_AXI_AVALID_SHIFT 15 +#define MH_DEBUG_REG00_AXI_AREADY_SHIFT 16 +#define MH_DEBUG_REG00_AXI_ARVALID_SHIFT 17 +#define MH_DEBUG_REG00_AXI_ARREADY_SHIFT 18 +#define MH_DEBUG_REG00_AXI_WVALID_SHIFT 19 +#define MH_DEBUG_REG00_AXI_WREADY_SHIFT 20 +#define MH_DEBUG_REG00_AXI_RVALID_SHIFT 21 +#define MH_DEBUG_REG00_AXI_RREADY_SHIFT 22 +#define MH_DEBUG_REG00_AXI_BVALID_SHIFT 23 +#define MH_DEBUG_REG00_AXI_BREADY_SHIFT 24 +#define MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT 25 +#define MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT 26 + +#define MH_DEBUG_REG00_MH_BUSY_MASK 0x00000001 +#define MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK 0x00000002 +#define MH_DEBUG_REG00_CP_REQUEST_MASK 0x00000004 +#define MH_DEBUG_REG00_VGT_REQUEST_MASK 0x00000008 +#define MH_DEBUG_REG00_TC_REQUEST_MASK 0x00000010 +#define MH_DEBUG_REG00_TC_CAM_EMPTY_MASK 0x00000020 +#define MH_DEBUG_REG00_TC_CAM_FULL_MASK 0x00000040 +#define MH_DEBUG_REG00_TCD_EMPTY_MASK 0x00000080 +#define MH_DEBUG_REG00_TCD_FULL_MASK 0x00000100 +#define MH_DEBUG_REG00_RB_REQUEST_MASK 0x00000200 +#define MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK 0x00000400 +#define MH_DEBUG_REG00_ARQ_EMPTY_MASK 0x00000800 +#define MH_DEBUG_REG00_ARQ_FULL_MASK 0x00001000 +#define MH_DEBUG_REG00_WDB_EMPTY_MASK 0x00002000 +#define MH_DEBUG_REG00_WDB_FULL_MASK 0x00004000 +#define MH_DEBUG_REG00_AXI_AVALID_MASK 0x00008000 +#define MH_DEBUG_REG00_AXI_AREADY_MASK 0x00010000 +#define MH_DEBUG_REG00_AXI_ARVALID_MASK 0x00020000 +#define MH_DEBUG_REG00_AXI_ARREADY_MASK 0x00040000 +#define MH_DEBUG_REG00_AXI_WVALID_MASK 0x00080000 +#define MH_DEBUG_REG00_AXI_WREADY_MASK 0x00100000 +#define MH_DEBUG_REG00_AXI_RVALID_MASK 0x00200000 +#define MH_DEBUG_REG00_AXI_RREADY_MASK 0x00400000 +#define MH_DEBUG_REG00_AXI_BVALID_MASK 0x00800000 +#define MH_DEBUG_REG00_AXI_BREADY_MASK 0x01000000 +#define MH_DEBUG_REG00_AXI_HALT_REQ_MASK 0x02000000 +#define MH_DEBUG_REG00_AXI_HALT_ACK_MASK 0x04000000 + +#define MH_DEBUG_REG00_MASK \ + (MH_DEBUG_REG00_MH_BUSY_MASK | \ + MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK | \ + MH_DEBUG_REG00_CP_REQUEST_MASK | \ + MH_DEBUG_REG00_VGT_REQUEST_MASK | \ + MH_DEBUG_REG00_TC_REQUEST_MASK | \ + MH_DEBUG_REG00_TC_CAM_EMPTY_MASK | \ + MH_DEBUG_REG00_TC_CAM_FULL_MASK | \ + MH_DEBUG_REG00_TCD_EMPTY_MASK | \ + MH_DEBUG_REG00_TCD_FULL_MASK | \ + MH_DEBUG_REG00_RB_REQUEST_MASK | \ + MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK | \ + MH_DEBUG_REG00_ARQ_EMPTY_MASK | \ + MH_DEBUG_REG00_ARQ_FULL_MASK | \ + MH_DEBUG_REG00_WDB_EMPTY_MASK | \ + MH_DEBUG_REG00_WDB_FULL_MASK | \ + MH_DEBUG_REG00_AXI_AVALID_MASK | \ + MH_DEBUG_REG00_AXI_AREADY_MASK | \ + MH_DEBUG_REG00_AXI_ARVALID_MASK | \ + MH_DEBUG_REG00_AXI_ARREADY_MASK | \ + MH_DEBUG_REG00_AXI_WVALID_MASK | \ + MH_DEBUG_REG00_AXI_WREADY_MASK | \ + MH_DEBUG_REG00_AXI_RVALID_MASK | \ + MH_DEBUG_REG00_AXI_RREADY_MASK | \ + MH_DEBUG_REG00_AXI_BVALID_MASK | \ + MH_DEBUG_REG00_AXI_BREADY_MASK | \ + MH_DEBUG_REG00_AXI_HALT_REQ_MASK | \ + MH_DEBUG_REG00_AXI_HALT_ACK_MASK) + +#define MH_DEBUG_REG00(mh_busy, trans_outstanding, cp_request, vgt_request, tc_request, tc_cam_empty, tc_cam_full, tcd_empty, tcd_full, rb_request, mh_clk_en_state, arq_empty, arq_full, wdb_empty, wdb_full, axi_avalid, axi_aready, axi_arvalid, axi_arready, axi_wvalid, axi_wready, axi_rvalid, axi_rready, axi_bvalid, axi_bready, axi_halt_req, axi_halt_ack) \ + ((mh_busy << MH_DEBUG_REG00_MH_BUSY_SHIFT) | \ + (trans_outstanding << MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT) | \ + (cp_request << MH_DEBUG_REG00_CP_REQUEST_SHIFT) | \ + (vgt_request << MH_DEBUG_REG00_VGT_REQUEST_SHIFT) | \ + (tc_request << MH_DEBUG_REG00_TC_REQUEST_SHIFT) | \ + (tc_cam_empty << MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT) | \ + (tc_cam_full << MH_DEBUG_REG00_TC_CAM_FULL_SHIFT) | \ + (tcd_empty << MH_DEBUG_REG00_TCD_EMPTY_SHIFT) | \ + (tcd_full << MH_DEBUG_REG00_TCD_FULL_SHIFT) | \ + (rb_request << MH_DEBUG_REG00_RB_REQUEST_SHIFT) | \ + (mh_clk_en_state << MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT) | \ + (arq_empty << MH_DEBUG_REG00_ARQ_EMPTY_SHIFT) | \ + (arq_full << MH_DEBUG_REG00_ARQ_FULL_SHIFT) | \ + (wdb_empty << MH_DEBUG_REG00_WDB_EMPTY_SHIFT) | \ + (wdb_full << MH_DEBUG_REG00_WDB_FULL_SHIFT) | \ + (axi_avalid << MH_DEBUG_REG00_AXI_AVALID_SHIFT) | \ + (axi_aready << MH_DEBUG_REG00_AXI_AREADY_SHIFT) | \ + (axi_arvalid << MH_DEBUG_REG00_AXI_ARVALID_SHIFT) | \ + (axi_arready << MH_DEBUG_REG00_AXI_ARREADY_SHIFT) | \ + (axi_wvalid << MH_DEBUG_REG00_AXI_WVALID_SHIFT) | \ + (axi_wready << MH_DEBUG_REG00_AXI_WREADY_SHIFT) | \ + (axi_rvalid << MH_DEBUG_REG00_AXI_RVALID_SHIFT) | \ + (axi_rready << MH_DEBUG_REG00_AXI_RREADY_SHIFT) | \ + (axi_bvalid << MH_DEBUG_REG00_AXI_BVALID_SHIFT) | \ + (axi_bready << MH_DEBUG_REG00_AXI_BREADY_SHIFT) | \ + (axi_halt_req << MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT) | \ + (axi_halt_ack << MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT)) + +#define MH_DEBUG_REG00_GET_MH_BUSY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_MH_BUSY_MASK) >> MH_DEBUG_REG00_MH_BUSY_SHIFT) +#define MH_DEBUG_REG00_GET_TRANS_OUTSTANDING(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK) >> MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT) +#define MH_DEBUG_REG00_GET_CP_REQUEST(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_CP_REQUEST_MASK) >> MH_DEBUG_REG00_CP_REQUEST_SHIFT) +#define MH_DEBUG_REG00_GET_VGT_REQUEST(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_VGT_REQUEST_MASK) >> MH_DEBUG_REG00_VGT_REQUEST_SHIFT) +#define MH_DEBUG_REG00_GET_TC_REQUEST(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TC_REQUEST_MASK) >> MH_DEBUG_REG00_TC_REQUEST_SHIFT) +#define MH_DEBUG_REG00_GET_TC_CAM_EMPTY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TC_CAM_EMPTY_MASK) >> MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT) +#define MH_DEBUG_REG00_GET_TC_CAM_FULL(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TC_CAM_FULL_MASK) >> MH_DEBUG_REG00_TC_CAM_FULL_SHIFT) +#define MH_DEBUG_REG00_GET_TCD_EMPTY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TCD_EMPTY_MASK) >> MH_DEBUG_REG00_TCD_EMPTY_SHIFT) +#define MH_DEBUG_REG00_GET_TCD_FULL(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TCD_FULL_MASK) >> MH_DEBUG_REG00_TCD_FULL_SHIFT) +#define MH_DEBUG_REG00_GET_RB_REQUEST(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_RB_REQUEST_MASK) >> MH_DEBUG_REG00_RB_REQUEST_SHIFT) +#define MH_DEBUG_REG00_GET_MH_CLK_EN_STATE(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK) >> MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT) +#define MH_DEBUG_REG00_GET_ARQ_EMPTY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_ARQ_EMPTY_MASK) >> MH_DEBUG_REG00_ARQ_EMPTY_SHIFT) +#define MH_DEBUG_REG00_GET_ARQ_FULL(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_ARQ_FULL_MASK) >> MH_DEBUG_REG00_ARQ_FULL_SHIFT) +#define MH_DEBUG_REG00_GET_WDB_EMPTY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_WDB_EMPTY_MASK) >> MH_DEBUG_REG00_WDB_EMPTY_SHIFT) +#define MH_DEBUG_REG00_GET_WDB_FULL(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_WDB_FULL_MASK) >> MH_DEBUG_REG00_WDB_FULL_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_AVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_AVALID_MASK) >> MH_DEBUG_REG00_AXI_AVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_AREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_AREADY_MASK) >> MH_DEBUG_REG00_AXI_AREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_ARVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_ARVALID_MASK) >> MH_DEBUG_REG00_AXI_ARVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_ARREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_ARREADY_MASK) >> MH_DEBUG_REG00_AXI_ARREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_WVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_WVALID_MASK) >> MH_DEBUG_REG00_AXI_WVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_WREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_WREADY_MASK) >> MH_DEBUG_REG00_AXI_WREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_RVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RVALID_MASK) >> MH_DEBUG_REG00_AXI_RVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_RREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RREADY_MASK) >> MH_DEBUG_REG00_AXI_RREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_BVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_BVALID_MASK) >> MH_DEBUG_REG00_AXI_BVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_BREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_BREADY_MASK) >> MH_DEBUG_REG00_AXI_BREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_HALT_REQ(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_HALT_REQ_MASK) >> MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_HALT_ACK(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_HALT_ACK_MASK) >> MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT) + +#define MH_DEBUG_REG00_SET_MH_BUSY(mh_debug_reg00_reg, mh_busy) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_MH_BUSY_MASK) | (mh_busy << MH_DEBUG_REG00_MH_BUSY_SHIFT) +#define MH_DEBUG_REG00_SET_TRANS_OUTSTANDING(mh_debug_reg00_reg, trans_outstanding) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK) | (trans_outstanding << MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT) +#define MH_DEBUG_REG00_SET_CP_REQUEST(mh_debug_reg00_reg, cp_request) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_CP_REQUEST_MASK) | (cp_request << MH_DEBUG_REG00_CP_REQUEST_SHIFT) +#define MH_DEBUG_REG00_SET_VGT_REQUEST(mh_debug_reg00_reg, vgt_request) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_VGT_REQUEST_MASK) | (vgt_request << MH_DEBUG_REG00_VGT_REQUEST_SHIFT) +#define MH_DEBUG_REG00_SET_TC_REQUEST(mh_debug_reg00_reg, tc_request) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_REQUEST_MASK) | (tc_request << MH_DEBUG_REG00_TC_REQUEST_SHIFT) +#define MH_DEBUG_REG00_SET_TC_CAM_EMPTY(mh_debug_reg00_reg, tc_cam_empty) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_CAM_EMPTY_MASK) | (tc_cam_empty << MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT) +#define MH_DEBUG_REG00_SET_TC_CAM_FULL(mh_debug_reg00_reg, tc_cam_full) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_CAM_FULL_MASK) | (tc_cam_full << MH_DEBUG_REG00_TC_CAM_FULL_SHIFT) +#define MH_DEBUG_REG00_SET_TCD_EMPTY(mh_debug_reg00_reg, tcd_empty) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TCD_EMPTY_MASK) | (tcd_empty << MH_DEBUG_REG00_TCD_EMPTY_SHIFT) +#define MH_DEBUG_REG00_SET_TCD_FULL(mh_debug_reg00_reg, tcd_full) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TCD_FULL_MASK) | (tcd_full << MH_DEBUG_REG00_TCD_FULL_SHIFT) +#define MH_DEBUG_REG00_SET_RB_REQUEST(mh_debug_reg00_reg, rb_request) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_RB_REQUEST_MASK) | (rb_request << MH_DEBUG_REG00_RB_REQUEST_SHIFT) +#define MH_DEBUG_REG00_SET_MH_CLK_EN_STATE(mh_debug_reg00_reg, mh_clk_en_state) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK) | (mh_clk_en_state << MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT) +#define MH_DEBUG_REG00_SET_ARQ_EMPTY(mh_debug_reg00_reg, arq_empty) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_ARQ_EMPTY_MASK) | (arq_empty << MH_DEBUG_REG00_ARQ_EMPTY_SHIFT) +#define MH_DEBUG_REG00_SET_ARQ_FULL(mh_debug_reg00_reg, arq_full) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_ARQ_FULL_MASK) | (arq_full << MH_DEBUG_REG00_ARQ_FULL_SHIFT) +#define MH_DEBUG_REG00_SET_WDB_EMPTY(mh_debug_reg00_reg, wdb_empty) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_WDB_EMPTY_MASK) | (wdb_empty << MH_DEBUG_REG00_WDB_EMPTY_SHIFT) +#define MH_DEBUG_REG00_SET_WDB_FULL(mh_debug_reg00_reg, wdb_full) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_WDB_FULL_MASK) | (wdb_full << MH_DEBUG_REG00_WDB_FULL_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_AVALID(mh_debug_reg00_reg, axi_avalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_AVALID_MASK) | (axi_avalid << MH_DEBUG_REG00_AXI_AVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_AREADY(mh_debug_reg00_reg, axi_aready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_AREADY_MASK) | (axi_aready << MH_DEBUG_REG00_AXI_AREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_ARVALID(mh_debug_reg00_reg, axi_arvalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_ARVALID_MASK) | (axi_arvalid << MH_DEBUG_REG00_AXI_ARVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_ARREADY(mh_debug_reg00_reg, axi_arready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_ARREADY_MASK) | (axi_arready << MH_DEBUG_REG00_AXI_ARREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_WVALID(mh_debug_reg00_reg, axi_wvalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_WVALID_MASK) | (axi_wvalid << MH_DEBUG_REG00_AXI_WVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_WREADY(mh_debug_reg00_reg, axi_wready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_WREADY_MASK) | (axi_wready << MH_DEBUG_REG00_AXI_WREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_RVALID(mh_debug_reg00_reg, axi_rvalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RVALID_MASK) | (axi_rvalid << MH_DEBUG_REG00_AXI_RVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_RREADY(mh_debug_reg00_reg, axi_rready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RREADY_MASK) | (axi_rready << MH_DEBUG_REG00_AXI_RREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_BVALID(mh_debug_reg00_reg, axi_bvalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_BVALID_MASK) | (axi_bvalid << MH_DEBUG_REG00_AXI_BVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_BREADY(mh_debug_reg00_reg, axi_bready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_BREADY_MASK) | (axi_bready << MH_DEBUG_REG00_AXI_BREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_HALT_REQ(mh_debug_reg00_reg, axi_halt_req) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_HALT_REQ_MASK) | (axi_halt_req << MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_HALT_ACK(mh_debug_reg00_reg, axi_halt_ack) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_HALT_ACK_MASK) | (axi_halt_ack << MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg00_t { + unsigned int mh_busy : MH_DEBUG_REG00_MH_BUSY_SIZE; + unsigned int trans_outstanding : MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE; + unsigned int cp_request : MH_DEBUG_REG00_CP_REQUEST_SIZE; + unsigned int vgt_request : MH_DEBUG_REG00_VGT_REQUEST_SIZE; + unsigned int tc_request : MH_DEBUG_REG00_TC_REQUEST_SIZE; + unsigned int tc_cam_empty : MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE; + unsigned int tc_cam_full : MH_DEBUG_REG00_TC_CAM_FULL_SIZE; + unsigned int tcd_empty : MH_DEBUG_REG00_TCD_EMPTY_SIZE; + unsigned int tcd_full : MH_DEBUG_REG00_TCD_FULL_SIZE; + unsigned int rb_request : MH_DEBUG_REG00_RB_REQUEST_SIZE; + unsigned int mh_clk_en_state : MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE; + unsigned int arq_empty : MH_DEBUG_REG00_ARQ_EMPTY_SIZE; + unsigned int arq_full : MH_DEBUG_REG00_ARQ_FULL_SIZE; + unsigned int wdb_empty : MH_DEBUG_REG00_WDB_EMPTY_SIZE; + unsigned int wdb_full : MH_DEBUG_REG00_WDB_FULL_SIZE; + unsigned int axi_avalid : MH_DEBUG_REG00_AXI_AVALID_SIZE; + unsigned int axi_aready : MH_DEBUG_REG00_AXI_AREADY_SIZE; + unsigned int axi_arvalid : MH_DEBUG_REG00_AXI_ARVALID_SIZE; + unsigned int axi_arready : MH_DEBUG_REG00_AXI_ARREADY_SIZE; + unsigned int axi_wvalid : MH_DEBUG_REG00_AXI_WVALID_SIZE; + unsigned int axi_wready : MH_DEBUG_REG00_AXI_WREADY_SIZE; + unsigned int axi_rvalid : MH_DEBUG_REG00_AXI_RVALID_SIZE; + unsigned int axi_rready : MH_DEBUG_REG00_AXI_RREADY_SIZE; + unsigned int axi_bvalid : MH_DEBUG_REG00_AXI_BVALID_SIZE; + unsigned int axi_bready : MH_DEBUG_REG00_AXI_BREADY_SIZE; + unsigned int axi_halt_req : MH_DEBUG_REG00_AXI_HALT_REQ_SIZE; + unsigned int axi_halt_ack : MH_DEBUG_REG00_AXI_HALT_ACK_SIZE; + unsigned int : 5; + } mh_debug_reg00_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg00_t { + unsigned int : 5; + unsigned int axi_halt_ack : MH_DEBUG_REG00_AXI_HALT_ACK_SIZE; + unsigned int axi_halt_req : MH_DEBUG_REG00_AXI_HALT_REQ_SIZE; + unsigned int axi_bready : MH_DEBUG_REG00_AXI_BREADY_SIZE; + unsigned int axi_bvalid : MH_DEBUG_REG00_AXI_BVALID_SIZE; + unsigned int axi_rready : MH_DEBUG_REG00_AXI_RREADY_SIZE; + unsigned int axi_rvalid : MH_DEBUG_REG00_AXI_RVALID_SIZE; + unsigned int axi_wready : MH_DEBUG_REG00_AXI_WREADY_SIZE; + unsigned int axi_wvalid : MH_DEBUG_REG00_AXI_WVALID_SIZE; + unsigned int axi_arready : MH_DEBUG_REG00_AXI_ARREADY_SIZE; + unsigned int axi_arvalid : MH_DEBUG_REG00_AXI_ARVALID_SIZE; + unsigned int axi_aready : MH_DEBUG_REG00_AXI_AREADY_SIZE; + unsigned int axi_avalid : MH_DEBUG_REG00_AXI_AVALID_SIZE; + unsigned int wdb_full : MH_DEBUG_REG00_WDB_FULL_SIZE; + unsigned int wdb_empty : MH_DEBUG_REG00_WDB_EMPTY_SIZE; + unsigned int arq_full : MH_DEBUG_REG00_ARQ_FULL_SIZE; + unsigned int arq_empty : MH_DEBUG_REG00_ARQ_EMPTY_SIZE; + unsigned int mh_clk_en_state : MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE; + unsigned int rb_request : MH_DEBUG_REG00_RB_REQUEST_SIZE; + unsigned int tcd_full : MH_DEBUG_REG00_TCD_FULL_SIZE; + unsigned int tcd_empty : MH_DEBUG_REG00_TCD_EMPTY_SIZE; + unsigned int tc_cam_full : MH_DEBUG_REG00_TC_CAM_FULL_SIZE; + unsigned int tc_cam_empty : MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE; + unsigned int tc_request : MH_DEBUG_REG00_TC_REQUEST_SIZE; + unsigned int vgt_request : MH_DEBUG_REG00_VGT_REQUEST_SIZE; + unsigned int cp_request : MH_DEBUG_REG00_CP_REQUEST_SIZE; + unsigned int trans_outstanding : MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE; + unsigned int mh_busy : MH_DEBUG_REG00_MH_BUSY_SIZE; + } mh_debug_reg00_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg00_t f; +} mh_debug_reg00_u; + + +/* + * MH_DEBUG_REG01 struct + */ + +#define MH_DEBUG_REG01_CP_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_CP_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_CP_WRITE_q_SIZE 1 +#define MH_DEBUG_REG01_CP_TAG_q_SIZE 3 +#define MH_DEBUG_REG01_CP_BE_q_SIZE 8 +#define MH_DEBUG_REG01_VGT_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_VGT_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_VGT_TAG_q_SIZE 1 +#define MH_DEBUG_REG01_TC_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_TC_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_TC_MH_written_SIZE 1 +#define MH_DEBUG_REG01_RB_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_RB_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_RB_BE_q_SIZE 8 + +#define MH_DEBUG_REG01_CP_SEND_q_SHIFT 0 +#define MH_DEBUG_REG01_CP_RTR_q_SHIFT 1 +#define MH_DEBUG_REG01_CP_WRITE_q_SHIFT 2 +#define MH_DEBUG_REG01_CP_TAG_q_SHIFT 3 +#define MH_DEBUG_REG01_CP_BE_q_SHIFT 6 +#define MH_DEBUG_REG01_VGT_SEND_q_SHIFT 14 +#define MH_DEBUG_REG01_VGT_RTR_q_SHIFT 15 +#define MH_DEBUG_REG01_VGT_TAG_q_SHIFT 16 +#define MH_DEBUG_REG01_TC_SEND_q_SHIFT 17 +#define MH_DEBUG_REG01_TC_RTR_q_SHIFT 18 +#define MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT 19 +#define MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT 20 +#define MH_DEBUG_REG01_TC_MH_written_SHIFT 21 +#define MH_DEBUG_REG01_RB_SEND_q_SHIFT 22 +#define MH_DEBUG_REG01_RB_RTR_q_SHIFT 23 +#define MH_DEBUG_REG01_RB_BE_q_SHIFT 24 + +#define MH_DEBUG_REG01_CP_SEND_q_MASK 0x00000001 +#define MH_DEBUG_REG01_CP_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG01_CP_WRITE_q_MASK 0x00000004 +#define MH_DEBUG_REG01_CP_TAG_q_MASK 0x00000038 +#define MH_DEBUG_REG01_CP_BE_q_MASK 0x00003fc0 +#define MH_DEBUG_REG01_VGT_SEND_q_MASK 0x00004000 +#define MH_DEBUG_REG01_VGT_RTR_q_MASK 0x00008000 +#define MH_DEBUG_REG01_VGT_TAG_q_MASK 0x00010000 +#define MH_DEBUG_REG01_TC_SEND_q_MASK 0x00020000 +#define MH_DEBUG_REG01_TC_RTR_q_MASK 0x00040000 +#define MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK 0x00080000 +#define MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK 0x00100000 +#define MH_DEBUG_REG01_TC_MH_written_MASK 0x00200000 +#define MH_DEBUG_REG01_RB_SEND_q_MASK 0x00400000 +#define MH_DEBUG_REG01_RB_RTR_q_MASK 0x00800000 +#define MH_DEBUG_REG01_RB_BE_q_MASK 0xff000000 + +#define MH_DEBUG_REG01_MASK \ + (MH_DEBUG_REG01_CP_SEND_q_MASK | \ + MH_DEBUG_REG01_CP_RTR_q_MASK | \ + MH_DEBUG_REG01_CP_WRITE_q_MASK | \ + MH_DEBUG_REG01_CP_TAG_q_MASK | \ + MH_DEBUG_REG01_CP_BE_q_MASK | \ + MH_DEBUG_REG01_VGT_SEND_q_MASK | \ + MH_DEBUG_REG01_VGT_RTR_q_MASK | \ + MH_DEBUG_REG01_VGT_TAG_q_MASK | \ + MH_DEBUG_REG01_TC_SEND_q_MASK | \ + MH_DEBUG_REG01_TC_RTR_q_MASK | \ + MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK | \ + MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG01_TC_MH_written_MASK | \ + MH_DEBUG_REG01_RB_SEND_q_MASK | \ + MH_DEBUG_REG01_RB_RTR_q_MASK | \ + MH_DEBUG_REG01_RB_BE_q_MASK) + +#define MH_DEBUG_REG01(cp_send_q, cp_rtr_q, cp_write_q, cp_tag_q, cp_be_q, vgt_send_q, vgt_rtr_q, vgt_tag_q, tc_send_q, tc_rtr_q, tc_roq_send_q, tc_roq_rtr_q, tc_mh_written, rb_send_q, rb_rtr_q, rb_be_q) \ + ((cp_send_q << MH_DEBUG_REG01_CP_SEND_q_SHIFT) | \ + (cp_rtr_q << MH_DEBUG_REG01_CP_RTR_q_SHIFT) | \ + (cp_write_q << MH_DEBUG_REG01_CP_WRITE_q_SHIFT) | \ + (cp_tag_q << MH_DEBUG_REG01_CP_TAG_q_SHIFT) | \ + (cp_be_q << MH_DEBUG_REG01_CP_BE_q_SHIFT) | \ + (vgt_send_q << MH_DEBUG_REG01_VGT_SEND_q_SHIFT) | \ + (vgt_rtr_q << MH_DEBUG_REG01_VGT_RTR_q_SHIFT) | \ + (vgt_tag_q << MH_DEBUG_REG01_VGT_TAG_q_SHIFT) | \ + (tc_send_q << MH_DEBUG_REG01_TC_SEND_q_SHIFT) | \ + (tc_rtr_q << MH_DEBUG_REG01_TC_RTR_q_SHIFT) | \ + (tc_roq_send_q << MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT) | \ + (tc_mh_written << MH_DEBUG_REG01_TC_MH_written_SHIFT) | \ + (rb_send_q << MH_DEBUG_REG01_RB_SEND_q_SHIFT) | \ + (rb_rtr_q << MH_DEBUG_REG01_RB_RTR_q_SHIFT) | \ + (rb_be_q << MH_DEBUG_REG01_RB_BE_q_SHIFT)) + +#define MH_DEBUG_REG01_GET_CP_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_SEND_q_MASK) >> MH_DEBUG_REG01_CP_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_CP_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_RTR_q_MASK) >> MH_DEBUG_REG01_CP_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_CP_WRITE_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_WRITE_q_MASK) >> MH_DEBUG_REG01_CP_WRITE_q_SHIFT) +#define MH_DEBUG_REG01_GET_CP_TAG_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_TAG_q_MASK) >> MH_DEBUG_REG01_CP_TAG_q_SHIFT) +#define MH_DEBUG_REG01_GET_CP_BE_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_BE_q_MASK) >> MH_DEBUG_REG01_CP_BE_q_SHIFT) +#define MH_DEBUG_REG01_GET_VGT_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_SEND_q_MASK) >> MH_DEBUG_REG01_VGT_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_VGT_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_RTR_q_MASK) >> MH_DEBUG_REG01_VGT_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_VGT_TAG_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_TAG_q_MASK) >> MH_DEBUG_REG01_VGT_TAG_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_SEND_q_MASK) >> MH_DEBUG_REG01_TC_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_RTR_q_MASK) >> MH_DEBUG_REG01_TC_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_ROQ_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_ROQ_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_MH_written(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_MH_written_MASK) >> MH_DEBUG_REG01_TC_MH_written_SHIFT) +#define MH_DEBUG_REG01_GET_RB_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_RB_SEND_q_MASK) >> MH_DEBUG_REG01_RB_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_RB_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_RB_RTR_q_MASK) >> MH_DEBUG_REG01_RB_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_RB_BE_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_RB_BE_q_MASK) >> MH_DEBUG_REG01_RB_BE_q_SHIFT) + +#define MH_DEBUG_REG01_SET_CP_SEND_q(mh_debug_reg01_reg, cp_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_SEND_q_MASK) | (cp_send_q << MH_DEBUG_REG01_CP_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_CP_RTR_q(mh_debug_reg01_reg, cp_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_RTR_q_MASK) | (cp_rtr_q << MH_DEBUG_REG01_CP_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_CP_WRITE_q(mh_debug_reg01_reg, cp_write_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_WRITE_q_MASK) | (cp_write_q << MH_DEBUG_REG01_CP_WRITE_q_SHIFT) +#define MH_DEBUG_REG01_SET_CP_TAG_q(mh_debug_reg01_reg, cp_tag_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_TAG_q_MASK) | (cp_tag_q << MH_DEBUG_REG01_CP_TAG_q_SHIFT) +#define MH_DEBUG_REG01_SET_CP_BE_q(mh_debug_reg01_reg, cp_be_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_BE_q_MASK) | (cp_be_q << MH_DEBUG_REG01_CP_BE_q_SHIFT) +#define MH_DEBUG_REG01_SET_VGT_SEND_q(mh_debug_reg01_reg, vgt_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_SEND_q_MASK) | (vgt_send_q << MH_DEBUG_REG01_VGT_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_VGT_RTR_q(mh_debug_reg01_reg, vgt_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_RTR_q_MASK) | (vgt_rtr_q << MH_DEBUG_REG01_VGT_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_VGT_TAG_q(mh_debug_reg01_reg, vgt_tag_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_TAG_q_MASK) | (vgt_tag_q << MH_DEBUG_REG01_VGT_TAG_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_SEND_q(mh_debug_reg01_reg, tc_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_SEND_q_MASK) | (tc_send_q << MH_DEBUG_REG01_TC_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_RTR_q(mh_debug_reg01_reg, tc_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_RTR_q_MASK) | (tc_rtr_q << MH_DEBUG_REG01_TC_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_ROQ_SEND_q(mh_debug_reg01_reg, tc_roq_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_ROQ_RTR_q(mh_debug_reg01_reg, tc_roq_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_MH_written(mh_debug_reg01_reg, tc_mh_written) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG01_TC_MH_written_SHIFT) +#define MH_DEBUG_REG01_SET_RB_SEND_q(mh_debug_reg01_reg, rb_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_RB_SEND_q_MASK) | (rb_send_q << MH_DEBUG_REG01_RB_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_RB_RTR_q(mh_debug_reg01_reg, rb_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_RB_RTR_q_MASK) | (rb_rtr_q << MH_DEBUG_REG01_RB_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_RB_BE_q(mh_debug_reg01_reg, rb_be_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_RB_BE_q_MASK) | (rb_be_q << MH_DEBUG_REG01_RB_BE_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg01_t { + unsigned int cp_send_q : MH_DEBUG_REG01_CP_SEND_q_SIZE; + unsigned int cp_rtr_q : MH_DEBUG_REG01_CP_RTR_q_SIZE; + unsigned int cp_write_q : MH_DEBUG_REG01_CP_WRITE_q_SIZE; + unsigned int cp_tag_q : MH_DEBUG_REG01_CP_TAG_q_SIZE; + unsigned int cp_be_q : MH_DEBUG_REG01_CP_BE_q_SIZE; + unsigned int vgt_send_q : MH_DEBUG_REG01_VGT_SEND_q_SIZE; + unsigned int vgt_rtr_q : MH_DEBUG_REG01_VGT_RTR_q_SIZE; + unsigned int vgt_tag_q : MH_DEBUG_REG01_VGT_TAG_q_SIZE; + unsigned int tc_send_q : MH_DEBUG_REG01_TC_SEND_q_SIZE; + unsigned int tc_rtr_q : MH_DEBUG_REG01_TC_RTR_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG01_TC_MH_written_SIZE; + unsigned int rb_send_q : MH_DEBUG_REG01_RB_SEND_q_SIZE; + unsigned int rb_rtr_q : MH_DEBUG_REG01_RB_RTR_q_SIZE; + unsigned int rb_be_q : MH_DEBUG_REG01_RB_BE_q_SIZE; + } mh_debug_reg01_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg01_t { + unsigned int rb_be_q : MH_DEBUG_REG01_RB_BE_q_SIZE; + unsigned int rb_rtr_q : MH_DEBUG_REG01_RB_RTR_q_SIZE; + unsigned int rb_send_q : MH_DEBUG_REG01_RB_SEND_q_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG01_TC_MH_written_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE; + unsigned int tc_rtr_q : MH_DEBUG_REG01_TC_RTR_q_SIZE; + unsigned int tc_send_q : MH_DEBUG_REG01_TC_SEND_q_SIZE; + unsigned int vgt_tag_q : MH_DEBUG_REG01_VGT_TAG_q_SIZE; + unsigned int vgt_rtr_q : MH_DEBUG_REG01_VGT_RTR_q_SIZE; + unsigned int vgt_send_q : MH_DEBUG_REG01_VGT_SEND_q_SIZE; + unsigned int cp_be_q : MH_DEBUG_REG01_CP_BE_q_SIZE; + unsigned int cp_tag_q : MH_DEBUG_REG01_CP_TAG_q_SIZE; + unsigned int cp_write_q : MH_DEBUG_REG01_CP_WRITE_q_SIZE; + unsigned int cp_rtr_q : MH_DEBUG_REG01_CP_RTR_q_SIZE; + unsigned int cp_send_q : MH_DEBUG_REG01_CP_SEND_q_SIZE; + } mh_debug_reg01_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg01_t f; +} mh_debug_reg01_u; + + +/* + * MH_DEBUG_REG02 struct + */ + +#define MH_DEBUG_REG02_MH_CP_grb_send_SIZE 1 +#define MH_DEBUG_REG02_MH_VGT_grb_send_SIZE 1 +#define MH_DEBUG_REG02_MH_TC_mcsend_SIZE 1 +#define MH_DEBUG_REG02_MH_CLNT_rlast_SIZE 1 +#define MH_DEBUG_REG02_MH_CLNT_tag_SIZE 3 +#define MH_DEBUG_REG02_RDC_RID_SIZE 3 +#define MH_DEBUG_REG02_RDC_RRESP_SIZE 2 +#define MH_DEBUG_REG02_MH_CP_writeclean_SIZE 1 +#define MH_DEBUG_REG02_MH_RB_writeclean_SIZE 1 +#define MH_DEBUG_REG02_BRC_BID_SIZE 3 +#define MH_DEBUG_REG02_BRC_BRESP_SIZE 2 + +#define MH_DEBUG_REG02_MH_CP_grb_send_SHIFT 0 +#define MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT 1 +#define MH_DEBUG_REG02_MH_TC_mcsend_SHIFT 2 +#define MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT 3 +#define MH_DEBUG_REG02_MH_CLNT_tag_SHIFT 4 +#define MH_DEBUG_REG02_RDC_RID_SHIFT 7 +#define MH_DEBUG_REG02_RDC_RRESP_SHIFT 10 +#define MH_DEBUG_REG02_MH_CP_writeclean_SHIFT 12 +#define MH_DEBUG_REG02_MH_RB_writeclean_SHIFT 13 +#define MH_DEBUG_REG02_BRC_BID_SHIFT 14 +#define MH_DEBUG_REG02_BRC_BRESP_SHIFT 17 + +#define MH_DEBUG_REG02_MH_CP_grb_send_MASK 0x00000001 +#define MH_DEBUG_REG02_MH_VGT_grb_send_MASK 0x00000002 +#define MH_DEBUG_REG02_MH_TC_mcsend_MASK 0x00000004 +#define MH_DEBUG_REG02_MH_CLNT_rlast_MASK 0x00000008 +#define MH_DEBUG_REG02_MH_CLNT_tag_MASK 0x00000070 +#define MH_DEBUG_REG02_RDC_RID_MASK 0x00000380 +#define MH_DEBUG_REG02_RDC_RRESP_MASK 0x00000c00 +#define MH_DEBUG_REG02_MH_CP_writeclean_MASK 0x00001000 +#define MH_DEBUG_REG02_MH_RB_writeclean_MASK 0x00002000 +#define MH_DEBUG_REG02_BRC_BID_MASK 0x0001c000 +#define MH_DEBUG_REG02_BRC_BRESP_MASK 0x00060000 + +#define MH_DEBUG_REG02_MASK \ + (MH_DEBUG_REG02_MH_CP_grb_send_MASK | \ + MH_DEBUG_REG02_MH_VGT_grb_send_MASK | \ + MH_DEBUG_REG02_MH_TC_mcsend_MASK | \ + MH_DEBUG_REG02_MH_CLNT_rlast_MASK | \ + MH_DEBUG_REG02_MH_CLNT_tag_MASK | \ + MH_DEBUG_REG02_RDC_RID_MASK | \ + MH_DEBUG_REG02_RDC_RRESP_MASK | \ + MH_DEBUG_REG02_MH_CP_writeclean_MASK | \ + MH_DEBUG_REG02_MH_RB_writeclean_MASK | \ + MH_DEBUG_REG02_BRC_BID_MASK | \ + MH_DEBUG_REG02_BRC_BRESP_MASK) + +#define MH_DEBUG_REG02(mh_cp_grb_send, mh_vgt_grb_send, mh_tc_mcsend, mh_clnt_rlast, mh_clnt_tag, rdc_rid, rdc_rresp, mh_cp_writeclean, mh_rb_writeclean, brc_bid, brc_bresp) \ + ((mh_cp_grb_send << MH_DEBUG_REG02_MH_CP_grb_send_SHIFT) | \ + (mh_vgt_grb_send << MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT) | \ + (mh_tc_mcsend << MH_DEBUG_REG02_MH_TC_mcsend_SHIFT) | \ + (mh_clnt_rlast << MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT) | \ + (mh_clnt_tag << MH_DEBUG_REG02_MH_CLNT_tag_SHIFT) | \ + (rdc_rid << MH_DEBUG_REG02_RDC_RID_SHIFT) | \ + (rdc_rresp << MH_DEBUG_REG02_RDC_RRESP_SHIFT) | \ + (mh_cp_writeclean << MH_DEBUG_REG02_MH_CP_writeclean_SHIFT) | \ + (mh_rb_writeclean << MH_DEBUG_REG02_MH_RB_writeclean_SHIFT) | \ + (brc_bid << MH_DEBUG_REG02_BRC_BID_SHIFT) | \ + (brc_bresp << MH_DEBUG_REG02_BRC_BRESP_SHIFT)) + +#define MH_DEBUG_REG02_GET_MH_CP_grb_send(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CP_grb_send_MASK) >> MH_DEBUG_REG02_MH_CP_grb_send_SHIFT) +#define MH_DEBUG_REG02_GET_MH_VGT_grb_send(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_VGT_grb_send_MASK) >> MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT) +#define MH_DEBUG_REG02_GET_MH_TC_mcsend(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_TC_mcsend_MASK) >> MH_DEBUG_REG02_MH_TC_mcsend_SHIFT) +#define MH_DEBUG_REG02_GET_MH_CLNT_rlast(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CLNT_rlast_MASK) >> MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT) +#define MH_DEBUG_REG02_GET_MH_CLNT_tag(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CLNT_tag_MASK) >> MH_DEBUG_REG02_MH_CLNT_tag_SHIFT) +#define MH_DEBUG_REG02_GET_RDC_RID(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_RDC_RID_MASK) >> MH_DEBUG_REG02_RDC_RID_SHIFT) +#define MH_DEBUG_REG02_GET_RDC_RRESP(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_RDC_RRESP_MASK) >> MH_DEBUG_REG02_RDC_RRESP_SHIFT) +#define MH_DEBUG_REG02_GET_MH_CP_writeclean(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CP_writeclean_MASK) >> MH_DEBUG_REG02_MH_CP_writeclean_SHIFT) +#define MH_DEBUG_REG02_GET_MH_RB_writeclean(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_RB_writeclean_MASK) >> MH_DEBUG_REG02_MH_RB_writeclean_SHIFT) +#define MH_DEBUG_REG02_GET_BRC_BID(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_BRC_BID_MASK) >> MH_DEBUG_REG02_BRC_BID_SHIFT) +#define MH_DEBUG_REG02_GET_BRC_BRESP(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_BRC_BRESP_MASK) >> MH_DEBUG_REG02_BRC_BRESP_SHIFT) + +#define MH_DEBUG_REG02_SET_MH_CP_grb_send(mh_debug_reg02_reg, mh_cp_grb_send) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CP_grb_send_MASK) | (mh_cp_grb_send << MH_DEBUG_REG02_MH_CP_grb_send_SHIFT) +#define MH_DEBUG_REG02_SET_MH_VGT_grb_send(mh_debug_reg02_reg, mh_vgt_grb_send) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_VGT_grb_send_MASK) | (mh_vgt_grb_send << MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT) +#define MH_DEBUG_REG02_SET_MH_TC_mcsend(mh_debug_reg02_reg, mh_tc_mcsend) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_TC_mcsend_MASK) | (mh_tc_mcsend << MH_DEBUG_REG02_MH_TC_mcsend_SHIFT) +#define MH_DEBUG_REG02_SET_MH_CLNT_rlast(mh_debug_reg02_reg, mh_clnt_rlast) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CLNT_rlast_MASK) | (mh_clnt_rlast << MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT) +#define MH_DEBUG_REG02_SET_MH_CLNT_tag(mh_debug_reg02_reg, mh_clnt_tag) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CLNT_tag_MASK) | (mh_clnt_tag << MH_DEBUG_REG02_MH_CLNT_tag_SHIFT) +#define MH_DEBUG_REG02_SET_RDC_RID(mh_debug_reg02_reg, rdc_rid) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_RDC_RID_MASK) | (rdc_rid << MH_DEBUG_REG02_RDC_RID_SHIFT) +#define MH_DEBUG_REG02_SET_RDC_RRESP(mh_debug_reg02_reg, rdc_rresp) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_RDC_RRESP_MASK) | (rdc_rresp << MH_DEBUG_REG02_RDC_RRESP_SHIFT) +#define MH_DEBUG_REG02_SET_MH_CP_writeclean(mh_debug_reg02_reg, mh_cp_writeclean) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CP_writeclean_MASK) | (mh_cp_writeclean << MH_DEBUG_REG02_MH_CP_writeclean_SHIFT) +#define MH_DEBUG_REG02_SET_MH_RB_writeclean(mh_debug_reg02_reg, mh_rb_writeclean) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_RB_writeclean_MASK) | (mh_rb_writeclean << MH_DEBUG_REG02_MH_RB_writeclean_SHIFT) +#define MH_DEBUG_REG02_SET_BRC_BID(mh_debug_reg02_reg, brc_bid) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_BRC_BID_MASK) | (brc_bid << MH_DEBUG_REG02_BRC_BID_SHIFT) +#define MH_DEBUG_REG02_SET_BRC_BRESP(mh_debug_reg02_reg, brc_bresp) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_BRC_BRESP_MASK) | (brc_bresp << MH_DEBUG_REG02_BRC_BRESP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg02_t { + unsigned int mh_cp_grb_send : MH_DEBUG_REG02_MH_CP_grb_send_SIZE; + unsigned int mh_vgt_grb_send : MH_DEBUG_REG02_MH_VGT_grb_send_SIZE; + unsigned int mh_tc_mcsend : MH_DEBUG_REG02_MH_TC_mcsend_SIZE; + unsigned int mh_clnt_rlast : MH_DEBUG_REG02_MH_CLNT_rlast_SIZE; + unsigned int mh_clnt_tag : MH_DEBUG_REG02_MH_CLNT_tag_SIZE; + unsigned int rdc_rid : MH_DEBUG_REG02_RDC_RID_SIZE; + unsigned int rdc_rresp : MH_DEBUG_REG02_RDC_RRESP_SIZE; + unsigned int mh_cp_writeclean : MH_DEBUG_REG02_MH_CP_writeclean_SIZE; + unsigned int mh_rb_writeclean : MH_DEBUG_REG02_MH_RB_writeclean_SIZE; + unsigned int brc_bid : MH_DEBUG_REG02_BRC_BID_SIZE; + unsigned int brc_bresp : MH_DEBUG_REG02_BRC_BRESP_SIZE; + unsigned int : 13; + } mh_debug_reg02_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg02_t { + unsigned int : 13; + unsigned int brc_bresp : MH_DEBUG_REG02_BRC_BRESP_SIZE; + unsigned int brc_bid : MH_DEBUG_REG02_BRC_BID_SIZE; + unsigned int mh_rb_writeclean : MH_DEBUG_REG02_MH_RB_writeclean_SIZE; + unsigned int mh_cp_writeclean : MH_DEBUG_REG02_MH_CP_writeclean_SIZE; + unsigned int rdc_rresp : MH_DEBUG_REG02_RDC_RRESP_SIZE; + unsigned int rdc_rid : MH_DEBUG_REG02_RDC_RID_SIZE; + unsigned int mh_clnt_tag : MH_DEBUG_REG02_MH_CLNT_tag_SIZE; + unsigned int mh_clnt_rlast : MH_DEBUG_REG02_MH_CLNT_rlast_SIZE; + unsigned int mh_tc_mcsend : MH_DEBUG_REG02_MH_TC_mcsend_SIZE; + unsigned int mh_vgt_grb_send : MH_DEBUG_REG02_MH_VGT_grb_send_SIZE; + unsigned int mh_cp_grb_send : MH_DEBUG_REG02_MH_CP_grb_send_SIZE; + } mh_debug_reg02_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg02_t f; +} mh_debug_reg02_u; + + +/* + * MH_DEBUG_REG03 struct + */ + +#define MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE 32 + +#define MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT 0 + +#define MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG03_MASK \ + (MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) + +#define MH_DEBUG_REG03(mh_clnt_data_31_0) \ + ((mh_clnt_data_31_0 << MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT)) + +#define MH_DEBUG_REG03_GET_MH_CLNT_data_31_0(mh_debug_reg03) \ + ((mh_debug_reg03 & MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) >> MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT) + +#define MH_DEBUG_REG03_SET_MH_CLNT_data_31_0(mh_debug_reg03_reg, mh_clnt_data_31_0) \ + mh_debug_reg03_reg = (mh_debug_reg03_reg & ~MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) | (mh_clnt_data_31_0 << MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg03_t { + unsigned int mh_clnt_data_31_0 : MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE; + } mh_debug_reg03_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg03_t { + unsigned int mh_clnt_data_31_0 : MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE; + } mh_debug_reg03_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg03_t f; +} mh_debug_reg03_u; + + +/* + * MH_DEBUG_REG04 struct + */ + +#define MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE 32 + +#define MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT 0 + +#define MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG04_MASK \ + (MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) + +#define MH_DEBUG_REG04(mh_clnt_data_63_32) \ + ((mh_clnt_data_63_32 << MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT)) + +#define MH_DEBUG_REG04_GET_MH_CLNT_data_63_32(mh_debug_reg04) \ + ((mh_debug_reg04 & MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) >> MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT) + +#define MH_DEBUG_REG04_SET_MH_CLNT_data_63_32(mh_debug_reg04_reg, mh_clnt_data_63_32) \ + mh_debug_reg04_reg = (mh_debug_reg04_reg & ~MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) | (mh_clnt_data_63_32 << MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg04_t { + unsigned int mh_clnt_data_63_32 : MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE; + } mh_debug_reg04_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg04_t { + unsigned int mh_clnt_data_63_32 : MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE; + } mh_debug_reg04_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg04_t f; +} mh_debug_reg04_u; + + +/* + * MH_DEBUG_REG05 struct + */ + +#define MH_DEBUG_REG05_CP_MH_send_SIZE 1 +#define MH_DEBUG_REG05_CP_MH_write_SIZE 1 +#define MH_DEBUG_REG05_CP_MH_tag_SIZE 3 +#define MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE 27 + +#define MH_DEBUG_REG05_CP_MH_send_SHIFT 0 +#define MH_DEBUG_REG05_CP_MH_write_SHIFT 1 +#define MH_DEBUG_REG05_CP_MH_tag_SHIFT 2 +#define MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT 5 + +#define MH_DEBUG_REG05_CP_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG05_CP_MH_write_MASK 0x00000002 +#define MH_DEBUG_REG05_CP_MH_tag_MASK 0x0000001c +#define MH_DEBUG_REG05_CP_MH_ad_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG05_MASK \ + (MH_DEBUG_REG05_CP_MH_send_MASK | \ + MH_DEBUG_REG05_CP_MH_write_MASK | \ + MH_DEBUG_REG05_CP_MH_tag_MASK | \ + MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) + +#define MH_DEBUG_REG05(cp_mh_send, cp_mh_write, cp_mh_tag, cp_mh_ad_31_5) \ + ((cp_mh_send << MH_DEBUG_REG05_CP_MH_send_SHIFT) | \ + (cp_mh_write << MH_DEBUG_REG05_CP_MH_write_SHIFT) | \ + (cp_mh_tag << MH_DEBUG_REG05_CP_MH_tag_SHIFT) | \ + (cp_mh_ad_31_5 << MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT)) + +#define MH_DEBUG_REG05_GET_CP_MH_send(mh_debug_reg05) \ + ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_send_MASK) >> MH_DEBUG_REG05_CP_MH_send_SHIFT) +#define MH_DEBUG_REG05_GET_CP_MH_write(mh_debug_reg05) \ + ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_write_MASK) >> MH_DEBUG_REG05_CP_MH_write_SHIFT) +#define MH_DEBUG_REG05_GET_CP_MH_tag(mh_debug_reg05) \ + ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_tag_MASK) >> MH_DEBUG_REG05_CP_MH_tag_SHIFT) +#define MH_DEBUG_REG05_GET_CP_MH_ad_31_5(mh_debug_reg05) \ + ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) >> MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT) + +#define MH_DEBUG_REG05_SET_CP_MH_send(mh_debug_reg05_reg, cp_mh_send) \ + mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_send_MASK) | (cp_mh_send << MH_DEBUG_REG05_CP_MH_send_SHIFT) +#define MH_DEBUG_REG05_SET_CP_MH_write(mh_debug_reg05_reg, cp_mh_write) \ + mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_write_MASK) | (cp_mh_write << MH_DEBUG_REG05_CP_MH_write_SHIFT) +#define MH_DEBUG_REG05_SET_CP_MH_tag(mh_debug_reg05_reg, cp_mh_tag) \ + mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_tag_MASK) | (cp_mh_tag << MH_DEBUG_REG05_CP_MH_tag_SHIFT) +#define MH_DEBUG_REG05_SET_CP_MH_ad_31_5(mh_debug_reg05_reg, cp_mh_ad_31_5) \ + mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) | (cp_mh_ad_31_5 << MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg05_t { + unsigned int cp_mh_send : MH_DEBUG_REG05_CP_MH_send_SIZE; + unsigned int cp_mh_write : MH_DEBUG_REG05_CP_MH_write_SIZE; + unsigned int cp_mh_tag : MH_DEBUG_REG05_CP_MH_tag_SIZE; + unsigned int cp_mh_ad_31_5 : MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE; + } mh_debug_reg05_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg05_t { + unsigned int cp_mh_ad_31_5 : MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE; + unsigned int cp_mh_tag : MH_DEBUG_REG05_CP_MH_tag_SIZE; + unsigned int cp_mh_write : MH_DEBUG_REG05_CP_MH_write_SIZE; + unsigned int cp_mh_send : MH_DEBUG_REG05_CP_MH_send_SIZE; + } mh_debug_reg05_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg05_t f; +} mh_debug_reg05_u; + + +/* + * MH_DEBUG_REG06 struct + */ + +#define MH_DEBUG_REG06_CP_MH_data_31_0_SIZE 32 + +#define MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT 0 + +#define MH_DEBUG_REG06_CP_MH_data_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG06_MASK \ + (MH_DEBUG_REG06_CP_MH_data_31_0_MASK) + +#define MH_DEBUG_REG06(cp_mh_data_31_0) \ + ((cp_mh_data_31_0 << MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT)) + +#define MH_DEBUG_REG06_GET_CP_MH_data_31_0(mh_debug_reg06) \ + ((mh_debug_reg06 & MH_DEBUG_REG06_CP_MH_data_31_0_MASK) >> MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT) + +#define MH_DEBUG_REG06_SET_CP_MH_data_31_0(mh_debug_reg06_reg, cp_mh_data_31_0) \ + mh_debug_reg06_reg = (mh_debug_reg06_reg & ~MH_DEBUG_REG06_CP_MH_data_31_0_MASK) | (cp_mh_data_31_0 << MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg06_t { + unsigned int cp_mh_data_31_0 : MH_DEBUG_REG06_CP_MH_data_31_0_SIZE; + } mh_debug_reg06_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg06_t { + unsigned int cp_mh_data_31_0 : MH_DEBUG_REG06_CP_MH_data_31_0_SIZE; + } mh_debug_reg06_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg06_t f; +} mh_debug_reg06_u; + + +/* + * MH_DEBUG_REG07 struct + */ + +#define MH_DEBUG_REG07_CP_MH_data_63_32_SIZE 32 + +#define MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT 0 + +#define MH_DEBUG_REG07_CP_MH_data_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG07_MASK \ + (MH_DEBUG_REG07_CP_MH_data_63_32_MASK) + +#define MH_DEBUG_REG07(cp_mh_data_63_32) \ + ((cp_mh_data_63_32 << MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT)) + +#define MH_DEBUG_REG07_GET_CP_MH_data_63_32(mh_debug_reg07) \ + ((mh_debug_reg07 & MH_DEBUG_REG07_CP_MH_data_63_32_MASK) >> MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT) + +#define MH_DEBUG_REG07_SET_CP_MH_data_63_32(mh_debug_reg07_reg, cp_mh_data_63_32) \ + mh_debug_reg07_reg = (mh_debug_reg07_reg & ~MH_DEBUG_REG07_CP_MH_data_63_32_MASK) | (cp_mh_data_63_32 << MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg07_t { + unsigned int cp_mh_data_63_32 : MH_DEBUG_REG07_CP_MH_data_63_32_SIZE; + } mh_debug_reg07_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg07_t { + unsigned int cp_mh_data_63_32 : MH_DEBUG_REG07_CP_MH_data_63_32_SIZE; + } mh_debug_reg07_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg07_t f; +} mh_debug_reg07_u; + + +/* + * MH_DEBUG_REG08 struct + */ + +#define MH_DEBUG_REG08_ALWAYS_ZERO_SIZE 3 +#define MH_DEBUG_REG08_VGT_MH_send_SIZE 1 +#define MH_DEBUG_REG08_VGT_MH_tagbe_SIZE 1 +#define MH_DEBUG_REG08_VGT_MH_ad_31_5_SIZE 27 + +#define MH_DEBUG_REG08_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG08_VGT_MH_send_SHIFT 3 +#define MH_DEBUG_REG08_VGT_MH_tagbe_SHIFT 4 +#define MH_DEBUG_REG08_VGT_MH_ad_31_5_SHIFT 5 + +#define MH_DEBUG_REG08_ALWAYS_ZERO_MASK 0x00000007 +#define MH_DEBUG_REG08_VGT_MH_send_MASK 0x00000008 +#define MH_DEBUG_REG08_VGT_MH_tagbe_MASK 0x00000010 +#define MH_DEBUG_REG08_VGT_MH_ad_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG08_MASK \ + (MH_DEBUG_REG08_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG08_VGT_MH_send_MASK | \ + MH_DEBUG_REG08_VGT_MH_tagbe_MASK | \ + MH_DEBUG_REG08_VGT_MH_ad_31_5_MASK) + +#define MH_DEBUG_REG08(always_zero, vgt_mh_send, vgt_mh_tagbe, vgt_mh_ad_31_5) \ + ((always_zero << MH_DEBUG_REG08_ALWAYS_ZERO_SHIFT) | \ + (vgt_mh_send << MH_DEBUG_REG08_VGT_MH_send_SHIFT) | \ + (vgt_mh_tagbe << MH_DEBUG_REG08_VGT_MH_tagbe_SHIFT) | \ + (vgt_mh_ad_31_5 << MH_DEBUG_REG08_VGT_MH_ad_31_5_SHIFT)) + +#define MH_DEBUG_REG08_GET_ALWAYS_ZERO(mh_debug_reg08) \ + ((mh_debug_reg08 & MH_DEBUG_REG08_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG08_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG08_GET_VGT_MH_send(mh_debug_reg08) \ + ((mh_debug_reg08 & MH_DEBUG_REG08_VGT_MH_send_MASK) >> MH_DEBUG_REG08_VGT_MH_send_SHIFT) +#define MH_DEBUG_REG08_GET_VGT_MH_tagbe(mh_debug_reg08) \ + ((mh_debug_reg08 & MH_DEBUG_REG08_VGT_MH_tagbe_MASK) >> MH_DEBUG_REG08_VGT_MH_tagbe_SHIFT) +#define MH_DEBUG_REG08_GET_VGT_MH_ad_31_5(mh_debug_reg08) \ + ((mh_debug_reg08 & MH_DEBUG_REG08_VGT_MH_ad_31_5_MASK) >> MH_DEBUG_REG08_VGT_MH_ad_31_5_SHIFT) + +#define MH_DEBUG_REG08_SET_ALWAYS_ZERO(mh_debug_reg08_reg, always_zero) \ + mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG08_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG08_SET_VGT_MH_send(mh_debug_reg08_reg, vgt_mh_send) \ + mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_VGT_MH_send_MASK) | (vgt_mh_send << MH_DEBUG_REG08_VGT_MH_send_SHIFT) +#define MH_DEBUG_REG08_SET_VGT_MH_tagbe(mh_debug_reg08_reg, vgt_mh_tagbe) \ + mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_VGT_MH_tagbe_MASK) | (vgt_mh_tagbe << MH_DEBUG_REG08_VGT_MH_tagbe_SHIFT) +#define MH_DEBUG_REG08_SET_VGT_MH_ad_31_5(mh_debug_reg08_reg, vgt_mh_ad_31_5) \ + mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_VGT_MH_ad_31_5_MASK) | (vgt_mh_ad_31_5 << MH_DEBUG_REG08_VGT_MH_ad_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg08_t { + unsigned int always_zero : MH_DEBUG_REG08_ALWAYS_ZERO_SIZE; + unsigned int vgt_mh_send : MH_DEBUG_REG08_VGT_MH_send_SIZE; + unsigned int vgt_mh_tagbe : MH_DEBUG_REG08_VGT_MH_tagbe_SIZE; + unsigned int vgt_mh_ad_31_5 : MH_DEBUG_REG08_VGT_MH_ad_31_5_SIZE; + } mh_debug_reg08_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg08_t { + unsigned int vgt_mh_ad_31_5 : MH_DEBUG_REG08_VGT_MH_ad_31_5_SIZE; + unsigned int vgt_mh_tagbe : MH_DEBUG_REG08_VGT_MH_tagbe_SIZE; + unsigned int vgt_mh_send : MH_DEBUG_REG08_VGT_MH_send_SIZE; + unsigned int always_zero : MH_DEBUG_REG08_ALWAYS_ZERO_SIZE; + } mh_debug_reg08_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg08_t f; +} mh_debug_reg08_u; + + +/* + * MH_DEBUG_REG09 struct + */ + +#define MH_DEBUG_REG09_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG09_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG09_TC_MH_mask_SIZE 2 +#define MH_DEBUG_REG09_TC_MH_addr_31_5_SIZE 27 + +#define MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG09_TC_MH_send_SHIFT 2 +#define MH_DEBUG_REG09_TC_MH_mask_SHIFT 3 +#define MH_DEBUG_REG09_TC_MH_addr_31_5_SHIFT 5 + +#define MH_DEBUG_REG09_ALWAYS_ZERO_MASK 0x00000003 +#define MH_DEBUG_REG09_TC_MH_send_MASK 0x00000004 +#define MH_DEBUG_REG09_TC_MH_mask_MASK 0x00000018 +#define MH_DEBUG_REG09_TC_MH_addr_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG09_MASK \ + (MH_DEBUG_REG09_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG09_TC_MH_send_MASK | \ + MH_DEBUG_REG09_TC_MH_mask_MASK | \ + MH_DEBUG_REG09_TC_MH_addr_31_5_MASK) + +#define MH_DEBUG_REG09(always_zero, tc_mh_send, tc_mh_mask, tc_mh_addr_31_5) \ + ((always_zero << MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT) | \ + (tc_mh_send << MH_DEBUG_REG09_TC_MH_send_SHIFT) | \ + (tc_mh_mask << MH_DEBUG_REG09_TC_MH_mask_SHIFT) | \ + (tc_mh_addr_31_5 << MH_DEBUG_REG09_TC_MH_addr_31_5_SHIFT)) + +#define MH_DEBUG_REG09_GET_ALWAYS_ZERO(mh_debug_reg09) \ + ((mh_debug_reg09 & MH_DEBUG_REG09_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG09_GET_TC_MH_send(mh_debug_reg09) \ + ((mh_debug_reg09 & MH_DEBUG_REG09_TC_MH_send_MASK) >> MH_DEBUG_REG09_TC_MH_send_SHIFT) +#define MH_DEBUG_REG09_GET_TC_MH_mask(mh_debug_reg09) \ + ((mh_debug_reg09 & MH_DEBUG_REG09_TC_MH_mask_MASK) >> MH_DEBUG_REG09_TC_MH_mask_SHIFT) +#define MH_DEBUG_REG09_GET_TC_MH_addr_31_5(mh_debug_reg09) \ + ((mh_debug_reg09 & MH_DEBUG_REG09_TC_MH_addr_31_5_MASK) >> MH_DEBUG_REG09_TC_MH_addr_31_5_SHIFT) + +#define MH_DEBUG_REG09_SET_ALWAYS_ZERO(mh_debug_reg09_reg, always_zero) \ + mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG09_SET_TC_MH_send(mh_debug_reg09_reg, tc_mh_send) \ + mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG09_TC_MH_send_SHIFT) +#define MH_DEBUG_REG09_SET_TC_MH_mask(mh_debug_reg09_reg, tc_mh_mask) \ + mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_TC_MH_mask_MASK) | (tc_mh_mask << MH_DEBUG_REG09_TC_MH_mask_SHIFT) +#define MH_DEBUG_REG09_SET_TC_MH_addr_31_5(mh_debug_reg09_reg, tc_mh_addr_31_5) \ + mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_TC_MH_addr_31_5_MASK) | (tc_mh_addr_31_5 << MH_DEBUG_REG09_TC_MH_addr_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg09_t { + unsigned int always_zero : MH_DEBUG_REG09_ALWAYS_ZERO_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG09_TC_MH_send_SIZE; + unsigned int tc_mh_mask : MH_DEBUG_REG09_TC_MH_mask_SIZE; + unsigned int tc_mh_addr_31_5 : MH_DEBUG_REG09_TC_MH_addr_31_5_SIZE; + } mh_debug_reg09_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg09_t { + unsigned int tc_mh_addr_31_5 : MH_DEBUG_REG09_TC_MH_addr_31_5_SIZE; + unsigned int tc_mh_mask : MH_DEBUG_REG09_TC_MH_mask_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG09_TC_MH_send_SIZE; + unsigned int always_zero : MH_DEBUG_REG09_ALWAYS_ZERO_SIZE; + } mh_debug_reg09_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg09_t f; +} mh_debug_reg09_u; + + +/* + * MH_DEBUG_REG10 struct + */ + +#define MH_DEBUG_REG10_TC_MH_info_SIZE 25 +#define MH_DEBUG_REG10_TC_MH_send_SIZE 1 + +#define MH_DEBUG_REG10_TC_MH_info_SHIFT 0 +#define MH_DEBUG_REG10_TC_MH_send_SHIFT 25 + +#define MH_DEBUG_REG10_TC_MH_info_MASK 0x01ffffff +#define MH_DEBUG_REG10_TC_MH_send_MASK 0x02000000 + +#define MH_DEBUG_REG10_MASK \ + (MH_DEBUG_REG10_TC_MH_info_MASK | \ + MH_DEBUG_REG10_TC_MH_send_MASK) + +#define MH_DEBUG_REG10(tc_mh_info, tc_mh_send) \ + ((tc_mh_info << MH_DEBUG_REG10_TC_MH_info_SHIFT) | \ + (tc_mh_send << MH_DEBUG_REG10_TC_MH_send_SHIFT)) + +#define MH_DEBUG_REG10_GET_TC_MH_info(mh_debug_reg10) \ + ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_info_MASK) >> MH_DEBUG_REG10_TC_MH_info_SHIFT) +#define MH_DEBUG_REG10_GET_TC_MH_send(mh_debug_reg10) \ + ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_send_MASK) >> MH_DEBUG_REG10_TC_MH_send_SHIFT) + +#define MH_DEBUG_REG10_SET_TC_MH_info(mh_debug_reg10_reg, tc_mh_info) \ + mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_info_MASK) | (tc_mh_info << MH_DEBUG_REG10_TC_MH_info_SHIFT) +#define MH_DEBUG_REG10_SET_TC_MH_send(mh_debug_reg10_reg, tc_mh_send) \ + mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG10_TC_MH_send_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg10_t { + unsigned int tc_mh_info : MH_DEBUG_REG10_TC_MH_info_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG10_TC_MH_send_SIZE; + unsigned int : 6; + } mh_debug_reg10_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg10_t { + unsigned int : 6; + unsigned int tc_mh_send : MH_DEBUG_REG10_TC_MH_send_SIZE; + unsigned int tc_mh_info : MH_DEBUG_REG10_TC_MH_info_SIZE; + } mh_debug_reg10_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg10_t f; +} mh_debug_reg10_u; + + +/* + * MH_DEBUG_REG11 struct + */ + +#define MH_DEBUG_REG11_MH_TC_mcinfo_SIZE 25 +#define MH_DEBUG_REG11_MH_TC_mcinfo_send_SIZE 1 +#define MH_DEBUG_REG11_TC_MH_written_SIZE 1 + +#define MH_DEBUG_REG11_MH_TC_mcinfo_SHIFT 0 +#define MH_DEBUG_REG11_MH_TC_mcinfo_send_SHIFT 25 +#define MH_DEBUG_REG11_TC_MH_written_SHIFT 26 + +#define MH_DEBUG_REG11_MH_TC_mcinfo_MASK 0x01ffffff +#define MH_DEBUG_REG11_MH_TC_mcinfo_send_MASK 0x02000000 +#define MH_DEBUG_REG11_TC_MH_written_MASK 0x04000000 + +#define MH_DEBUG_REG11_MASK \ + (MH_DEBUG_REG11_MH_TC_mcinfo_MASK | \ + MH_DEBUG_REG11_MH_TC_mcinfo_send_MASK | \ + MH_DEBUG_REG11_TC_MH_written_MASK) + +#define MH_DEBUG_REG11(mh_tc_mcinfo, mh_tc_mcinfo_send, tc_mh_written) \ + ((mh_tc_mcinfo << MH_DEBUG_REG11_MH_TC_mcinfo_SHIFT) | \ + (mh_tc_mcinfo_send << MH_DEBUG_REG11_MH_TC_mcinfo_send_SHIFT) | \ + (tc_mh_written << MH_DEBUG_REG11_TC_MH_written_SHIFT)) + +#define MH_DEBUG_REG11_GET_MH_TC_mcinfo(mh_debug_reg11) \ + ((mh_debug_reg11 & MH_DEBUG_REG11_MH_TC_mcinfo_MASK) >> MH_DEBUG_REG11_MH_TC_mcinfo_SHIFT) +#define MH_DEBUG_REG11_GET_MH_TC_mcinfo_send(mh_debug_reg11) \ + ((mh_debug_reg11 & MH_DEBUG_REG11_MH_TC_mcinfo_send_MASK) >> MH_DEBUG_REG11_MH_TC_mcinfo_send_SHIFT) +#define MH_DEBUG_REG11_GET_TC_MH_written(mh_debug_reg11) \ + ((mh_debug_reg11 & MH_DEBUG_REG11_TC_MH_written_MASK) >> MH_DEBUG_REG11_TC_MH_written_SHIFT) + +#define MH_DEBUG_REG11_SET_MH_TC_mcinfo(mh_debug_reg11_reg, mh_tc_mcinfo) \ + mh_debug_reg11_reg = (mh_debug_reg11_reg & ~MH_DEBUG_REG11_MH_TC_mcinfo_MASK) | (mh_tc_mcinfo << MH_DEBUG_REG11_MH_TC_mcinfo_SHIFT) +#define MH_DEBUG_REG11_SET_MH_TC_mcinfo_send(mh_debug_reg11_reg, mh_tc_mcinfo_send) \ + mh_debug_reg11_reg = (mh_debug_reg11_reg & ~MH_DEBUG_REG11_MH_TC_mcinfo_send_MASK) | (mh_tc_mcinfo_send << MH_DEBUG_REG11_MH_TC_mcinfo_send_SHIFT) +#define MH_DEBUG_REG11_SET_TC_MH_written(mh_debug_reg11_reg, tc_mh_written) \ + mh_debug_reg11_reg = (mh_debug_reg11_reg & ~MH_DEBUG_REG11_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG11_TC_MH_written_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg11_t { + unsigned int mh_tc_mcinfo : MH_DEBUG_REG11_MH_TC_mcinfo_SIZE; + unsigned int mh_tc_mcinfo_send : MH_DEBUG_REG11_MH_TC_mcinfo_send_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG11_TC_MH_written_SIZE; + unsigned int : 5; + } mh_debug_reg11_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg11_t { + unsigned int : 5; + unsigned int tc_mh_written : MH_DEBUG_REG11_TC_MH_written_SIZE; + unsigned int mh_tc_mcinfo_send : MH_DEBUG_REG11_MH_TC_mcinfo_send_SIZE; + unsigned int mh_tc_mcinfo : MH_DEBUG_REG11_MH_TC_mcinfo_SIZE; + } mh_debug_reg11_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg11_t f; +} mh_debug_reg11_u; + + +/* + * MH_DEBUG_REG12 struct + */ + +#define MH_DEBUG_REG12_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG12_TC_ROQ_SEND_SIZE 1 +#define MH_DEBUG_REG12_TC_ROQ_MASK_SIZE 2 +#define MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_SIZE 27 + +#define MH_DEBUG_REG12_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG12_TC_ROQ_SEND_SHIFT 2 +#define MH_DEBUG_REG12_TC_ROQ_MASK_SHIFT 3 +#define MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_SHIFT 5 + +#define MH_DEBUG_REG12_ALWAYS_ZERO_MASK 0x00000003 +#define MH_DEBUG_REG12_TC_ROQ_SEND_MASK 0x00000004 +#define MH_DEBUG_REG12_TC_ROQ_MASK_MASK 0x00000018 +#define MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG12_MASK \ + (MH_DEBUG_REG12_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG12_TC_ROQ_SEND_MASK | \ + MH_DEBUG_REG12_TC_ROQ_MASK_MASK | \ + MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_MASK) + +#define MH_DEBUG_REG12(always_zero, tc_roq_send, tc_roq_mask, tc_roq_addr_31_5) \ + ((always_zero << MH_DEBUG_REG12_ALWAYS_ZERO_SHIFT) | \ + (tc_roq_send << MH_DEBUG_REG12_TC_ROQ_SEND_SHIFT) | \ + (tc_roq_mask << MH_DEBUG_REG12_TC_ROQ_MASK_SHIFT) | \ + (tc_roq_addr_31_5 << MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_SHIFT)) + +#define MH_DEBUG_REG12_GET_ALWAYS_ZERO(mh_debug_reg12) \ + ((mh_debug_reg12 & MH_DEBUG_REG12_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG12_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG12_GET_TC_ROQ_SEND(mh_debug_reg12) \ + ((mh_debug_reg12 & MH_DEBUG_REG12_TC_ROQ_SEND_MASK) >> MH_DEBUG_REG12_TC_ROQ_SEND_SHIFT) +#define MH_DEBUG_REG12_GET_TC_ROQ_MASK(mh_debug_reg12) \ + ((mh_debug_reg12 & MH_DEBUG_REG12_TC_ROQ_MASK_MASK) >> MH_DEBUG_REG12_TC_ROQ_MASK_SHIFT) +#define MH_DEBUG_REG12_GET_TC_ROQ_ADDR_31_5(mh_debug_reg12) \ + ((mh_debug_reg12 & MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_MASK) >> MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_SHIFT) + +#define MH_DEBUG_REG12_SET_ALWAYS_ZERO(mh_debug_reg12_reg, always_zero) \ + mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG12_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG12_SET_TC_ROQ_SEND(mh_debug_reg12_reg, tc_roq_send) \ + mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_TC_ROQ_SEND_MASK) | (tc_roq_send << MH_DEBUG_REG12_TC_ROQ_SEND_SHIFT) +#define MH_DEBUG_REG12_SET_TC_ROQ_MASK(mh_debug_reg12_reg, tc_roq_mask) \ + mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_TC_ROQ_MASK_MASK) | (tc_roq_mask << MH_DEBUG_REG12_TC_ROQ_MASK_SHIFT) +#define MH_DEBUG_REG12_SET_TC_ROQ_ADDR_31_5(mh_debug_reg12_reg, tc_roq_addr_31_5) \ + mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_MASK) | (tc_roq_addr_31_5 << MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg12_t { + unsigned int always_zero : MH_DEBUG_REG12_ALWAYS_ZERO_SIZE; + unsigned int tc_roq_send : MH_DEBUG_REG12_TC_ROQ_SEND_SIZE; + unsigned int tc_roq_mask : MH_DEBUG_REG12_TC_ROQ_MASK_SIZE; + unsigned int tc_roq_addr_31_5 : MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_SIZE; + } mh_debug_reg12_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg12_t { + unsigned int tc_roq_addr_31_5 : MH_DEBUG_REG12_TC_ROQ_ADDR_31_5_SIZE; + unsigned int tc_roq_mask : MH_DEBUG_REG12_TC_ROQ_MASK_SIZE; + unsigned int tc_roq_send : MH_DEBUG_REG12_TC_ROQ_SEND_SIZE; + unsigned int always_zero : MH_DEBUG_REG12_ALWAYS_ZERO_SIZE; + } mh_debug_reg12_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg12_t f; +} mh_debug_reg12_u; + + +/* + * MH_DEBUG_REG13 struct + */ + +#define MH_DEBUG_REG13_TC_ROQ_INFO_SIZE 25 +#define MH_DEBUG_REG13_TC_ROQ_SEND_SIZE 1 + +#define MH_DEBUG_REG13_TC_ROQ_INFO_SHIFT 0 +#define MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT 25 + +#define MH_DEBUG_REG13_TC_ROQ_INFO_MASK 0x01ffffff +#define MH_DEBUG_REG13_TC_ROQ_SEND_MASK 0x02000000 + +#define MH_DEBUG_REG13_MASK \ + (MH_DEBUG_REG13_TC_ROQ_INFO_MASK | \ + MH_DEBUG_REG13_TC_ROQ_SEND_MASK) + +#define MH_DEBUG_REG13(tc_roq_info, tc_roq_send) \ + ((tc_roq_info << MH_DEBUG_REG13_TC_ROQ_INFO_SHIFT) | \ + (tc_roq_send << MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT)) + +#define MH_DEBUG_REG13_GET_TC_ROQ_INFO(mh_debug_reg13) \ + ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_INFO_MASK) >> MH_DEBUG_REG13_TC_ROQ_INFO_SHIFT) +#define MH_DEBUG_REG13_GET_TC_ROQ_SEND(mh_debug_reg13) \ + ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_SEND_MASK) >> MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT) + +#define MH_DEBUG_REG13_SET_TC_ROQ_INFO(mh_debug_reg13_reg, tc_roq_info) \ + mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_INFO_MASK) | (tc_roq_info << MH_DEBUG_REG13_TC_ROQ_INFO_SHIFT) +#define MH_DEBUG_REG13_SET_TC_ROQ_SEND(mh_debug_reg13_reg, tc_roq_send) \ + mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_SEND_MASK) | (tc_roq_send << MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg13_t { + unsigned int tc_roq_info : MH_DEBUG_REG13_TC_ROQ_INFO_SIZE; + unsigned int tc_roq_send : MH_DEBUG_REG13_TC_ROQ_SEND_SIZE; + unsigned int : 6; + } mh_debug_reg13_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg13_t { + unsigned int : 6; + unsigned int tc_roq_send : MH_DEBUG_REG13_TC_ROQ_SEND_SIZE; + unsigned int tc_roq_info : MH_DEBUG_REG13_TC_ROQ_INFO_SIZE; + } mh_debug_reg13_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg13_t f; +} mh_debug_reg13_u; + + +/* + * MH_DEBUG_REG14 struct + */ + +#define MH_DEBUG_REG14_ALWAYS_ZERO_SIZE 4 +#define MH_DEBUG_REG14_RB_MH_send_SIZE 1 +#define MH_DEBUG_REG14_RB_MH_addr_31_5_SIZE 27 + +#define MH_DEBUG_REG14_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG14_RB_MH_send_SHIFT 4 +#define MH_DEBUG_REG14_RB_MH_addr_31_5_SHIFT 5 + +#define MH_DEBUG_REG14_ALWAYS_ZERO_MASK 0x0000000f +#define MH_DEBUG_REG14_RB_MH_send_MASK 0x00000010 +#define MH_DEBUG_REG14_RB_MH_addr_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG14_MASK \ + (MH_DEBUG_REG14_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG14_RB_MH_send_MASK | \ + MH_DEBUG_REG14_RB_MH_addr_31_5_MASK) + +#define MH_DEBUG_REG14(always_zero, rb_mh_send, rb_mh_addr_31_5) \ + ((always_zero << MH_DEBUG_REG14_ALWAYS_ZERO_SHIFT) | \ + (rb_mh_send << MH_DEBUG_REG14_RB_MH_send_SHIFT) | \ + (rb_mh_addr_31_5 << MH_DEBUG_REG14_RB_MH_addr_31_5_SHIFT)) + +#define MH_DEBUG_REG14_GET_ALWAYS_ZERO(mh_debug_reg14) \ + ((mh_debug_reg14 & MH_DEBUG_REG14_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG14_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG14_GET_RB_MH_send(mh_debug_reg14) \ + ((mh_debug_reg14 & MH_DEBUG_REG14_RB_MH_send_MASK) >> MH_DEBUG_REG14_RB_MH_send_SHIFT) +#define MH_DEBUG_REG14_GET_RB_MH_addr_31_5(mh_debug_reg14) \ + ((mh_debug_reg14 & MH_DEBUG_REG14_RB_MH_addr_31_5_MASK) >> MH_DEBUG_REG14_RB_MH_addr_31_5_SHIFT) + +#define MH_DEBUG_REG14_SET_ALWAYS_ZERO(mh_debug_reg14_reg, always_zero) \ + mh_debug_reg14_reg = (mh_debug_reg14_reg & ~MH_DEBUG_REG14_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG14_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG14_SET_RB_MH_send(mh_debug_reg14_reg, rb_mh_send) \ + mh_debug_reg14_reg = (mh_debug_reg14_reg & ~MH_DEBUG_REG14_RB_MH_send_MASK) | (rb_mh_send << MH_DEBUG_REG14_RB_MH_send_SHIFT) +#define MH_DEBUG_REG14_SET_RB_MH_addr_31_5(mh_debug_reg14_reg, rb_mh_addr_31_5) \ + mh_debug_reg14_reg = (mh_debug_reg14_reg & ~MH_DEBUG_REG14_RB_MH_addr_31_5_MASK) | (rb_mh_addr_31_5 << MH_DEBUG_REG14_RB_MH_addr_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg14_t { + unsigned int always_zero : MH_DEBUG_REG14_ALWAYS_ZERO_SIZE; + unsigned int rb_mh_send : MH_DEBUG_REG14_RB_MH_send_SIZE; + unsigned int rb_mh_addr_31_5 : MH_DEBUG_REG14_RB_MH_addr_31_5_SIZE; + } mh_debug_reg14_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg14_t { + unsigned int rb_mh_addr_31_5 : MH_DEBUG_REG14_RB_MH_addr_31_5_SIZE; + unsigned int rb_mh_send : MH_DEBUG_REG14_RB_MH_send_SIZE; + unsigned int always_zero : MH_DEBUG_REG14_ALWAYS_ZERO_SIZE; + } mh_debug_reg14_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg14_t f; +} mh_debug_reg14_u; + + +/* + * MH_DEBUG_REG15 struct + */ + +#define MH_DEBUG_REG15_RB_MH_data_31_0_SIZE 32 + +#define MH_DEBUG_REG15_RB_MH_data_31_0_SHIFT 0 + +#define MH_DEBUG_REG15_RB_MH_data_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG15_MASK \ + (MH_DEBUG_REG15_RB_MH_data_31_0_MASK) + +#define MH_DEBUG_REG15(rb_mh_data_31_0) \ + ((rb_mh_data_31_0 << MH_DEBUG_REG15_RB_MH_data_31_0_SHIFT)) + +#define MH_DEBUG_REG15_GET_RB_MH_data_31_0(mh_debug_reg15) \ + ((mh_debug_reg15 & MH_DEBUG_REG15_RB_MH_data_31_0_MASK) >> MH_DEBUG_REG15_RB_MH_data_31_0_SHIFT) + +#define MH_DEBUG_REG15_SET_RB_MH_data_31_0(mh_debug_reg15_reg, rb_mh_data_31_0) \ + mh_debug_reg15_reg = (mh_debug_reg15_reg & ~MH_DEBUG_REG15_RB_MH_data_31_0_MASK) | (rb_mh_data_31_0 << MH_DEBUG_REG15_RB_MH_data_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg15_t { + unsigned int rb_mh_data_31_0 : MH_DEBUG_REG15_RB_MH_data_31_0_SIZE; + } mh_debug_reg15_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg15_t { + unsigned int rb_mh_data_31_0 : MH_DEBUG_REG15_RB_MH_data_31_0_SIZE; + } mh_debug_reg15_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg15_t f; +} mh_debug_reg15_u; + + +/* + * MH_DEBUG_REG16 struct + */ + +#define MH_DEBUG_REG16_RB_MH_data_63_32_SIZE 32 + +#define MH_DEBUG_REG16_RB_MH_data_63_32_SHIFT 0 + +#define MH_DEBUG_REG16_RB_MH_data_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG16_MASK \ + (MH_DEBUG_REG16_RB_MH_data_63_32_MASK) + +#define MH_DEBUG_REG16(rb_mh_data_63_32) \ + ((rb_mh_data_63_32 << MH_DEBUG_REG16_RB_MH_data_63_32_SHIFT)) + +#define MH_DEBUG_REG16_GET_RB_MH_data_63_32(mh_debug_reg16) \ + ((mh_debug_reg16 & MH_DEBUG_REG16_RB_MH_data_63_32_MASK) >> MH_DEBUG_REG16_RB_MH_data_63_32_SHIFT) + +#define MH_DEBUG_REG16_SET_RB_MH_data_63_32(mh_debug_reg16_reg, rb_mh_data_63_32) \ + mh_debug_reg16_reg = (mh_debug_reg16_reg & ~MH_DEBUG_REG16_RB_MH_data_63_32_MASK) | (rb_mh_data_63_32 << MH_DEBUG_REG16_RB_MH_data_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg16_t { + unsigned int rb_mh_data_63_32 : MH_DEBUG_REG16_RB_MH_data_63_32_SIZE; + } mh_debug_reg16_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg16_t { + unsigned int rb_mh_data_63_32 : MH_DEBUG_REG16_RB_MH_data_63_32_SIZE; + } mh_debug_reg16_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg16_t f; +} mh_debug_reg16_u; + + +/* + * MH_DEBUG_REG17 struct + */ + +#define MH_DEBUG_REG17_AVALID_q_SIZE 1 +#define MH_DEBUG_REG17_AREADY_q_SIZE 1 +#define MH_DEBUG_REG17_AID_q_SIZE 3 +#define MH_DEBUG_REG17_ALEN_q_2_0_SIZE 3 +#define MH_DEBUG_REG17_ARVALID_q_SIZE 1 +#define MH_DEBUG_REG17_ARREADY_q_SIZE 1 +#define MH_DEBUG_REG17_ARID_q_SIZE 3 +#define MH_DEBUG_REG17_ARLEN_q_1_0_SIZE 2 +#define MH_DEBUG_REG17_RVALID_q_SIZE 1 +#define MH_DEBUG_REG17_RREADY_q_SIZE 1 +#define MH_DEBUG_REG17_RLAST_q_SIZE 1 +#define MH_DEBUG_REG17_RID_q_SIZE 3 +#define MH_DEBUG_REG17_WVALID_q_SIZE 1 +#define MH_DEBUG_REG17_WREADY_q_SIZE 1 +#define MH_DEBUG_REG17_WLAST_q_SIZE 1 +#define MH_DEBUG_REG17_WID_q_SIZE 3 +#define MH_DEBUG_REG17_BVALID_q_SIZE 1 +#define MH_DEBUG_REG17_BREADY_q_SIZE 1 +#define MH_DEBUG_REG17_BID_q_SIZE 3 + +#define MH_DEBUG_REG17_AVALID_q_SHIFT 0 +#define MH_DEBUG_REG17_AREADY_q_SHIFT 1 +#define MH_DEBUG_REG17_AID_q_SHIFT 2 +#define MH_DEBUG_REG17_ALEN_q_2_0_SHIFT 5 +#define MH_DEBUG_REG17_ARVALID_q_SHIFT 8 +#define MH_DEBUG_REG17_ARREADY_q_SHIFT 9 +#define MH_DEBUG_REG17_ARID_q_SHIFT 10 +#define MH_DEBUG_REG17_ARLEN_q_1_0_SHIFT 13 +#define MH_DEBUG_REG17_RVALID_q_SHIFT 15 +#define MH_DEBUG_REG17_RREADY_q_SHIFT 16 +#define MH_DEBUG_REG17_RLAST_q_SHIFT 17 +#define MH_DEBUG_REG17_RID_q_SHIFT 18 +#define MH_DEBUG_REG17_WVALID_q_SHIFT 21 +#define MH_DEBUG_REG17_WREADY_q_SHIFT 22 +#define MH_DEBUG_REG17_WLAST_q_SHIFT 23 +#define MH_DEBUG_REG17_WID_q_SHIFT 24 +#define MH_DEBUG_REG17_BVALID_q_SHIFT 27 +#define MH_DEBUG_REG17_BREADY_q_SHIFT 28 +#define MH_DEBUG_REG17_BID_q_SHIFT 29 + +#define MH_DEBUG_REG17_AVALID_q_MASK 0x00000001 +#define MH_DEBUG_REG17_AREADY_q_MASK 0x00000002 +#define MH_DEBUG_REG17_AID_q_MASK 0x0000001c +#define MH_DEBUG_REG17_ALEN_q_2_0_MASK 0x000000e0 +#define MH_DEBUG_REG17_ARVALID_q_MASK 0x00000100 +#define MH_DEBUG_REG17_ARREADY_q_MASK 0x00000200 +#define MH_DEBUG_REG17_ARID_q_MASK 0x00001c00 +#define MH_DEBUG_REG17_ARLEN_q_1_0_MASK 0x00006000 +#define MH_DEBUG_REG17_RVALID_q_MASK 0x00008000 +#define MH_DEBUG_REG17_RREADY_q_MASK 0x00010000 +#define MH_DEBUG_REG17_RLAST_q_MASK 0x00020000 +#define MH_DEBUG_REG17_RID_q_MASK 0x001c0000 +#define MH_DEBUG_REG17_WVALID_q_MASK 0x00200000 +#define MH_DEBUG_REG17_WREADY_q_MASK 0x00400000 +#define MH_DEBUG_REG17_WLAST_q_MASK 0x00800000 +#define MH_DEBUG_REG17_WID_q_MASK 0x07000000 +#define MH_DEBUG_REG17_BVALID_q_MASK 0x08000000 +#define MH_DEBUG_REG17_BREADY_q_MASK 0x10000000 +#define MH_DEBUG_REG17_BID_q_MASK 0xe0000000 + +#define MH_DEBUG_REG17_MASK \ + (MH_DEBUG_REG17_AVALID_q_MASK | \ + MH_DEBUG_REG17_AREADY_q_MASK | \ + MH_DEBUG_REG17_AID_q_MASK | \ + MH_DEBUG_REG17_ALEN_q_2_0_MASK | \ + MH_DEBUG_REG17_ARVALID_q_MASK | \ + MH_DEBUG_REG17_ARREADY_q_MASK | \ + MH_DEBUG_REG17_ARID_q_MASK | \ + MH_DEBUG_REG17_ARLEN_q_1_0_MASK | \ + MH_DEBUG_REG17_RVALID_q_MASK | \ + MH_DEBUG_REG17_RREADY_q_MASK | \ + MH_DEBUG_REG17_RLAST_q_MASK | \ + MH_DEBUG_REG17_RID_q_MASK | \ + MH_DEBUG_REG17_WVALID_q_MASK | \ + MH_DEBUG_REG17_WREADY_q_MASK | \ + MH_DEBUG_REG17_WLAST_q_MASK | \ + MH_DEBUG_REG17_WID_q_MASK | \ + MH_DEBUG_REG17_BVALID_q_MASK | \ + MH_DEBUG_REG17_BREADY_q_MASK | \ + MH_DEBUG_REG17_BID_q_MASK) + +#define MH_DEBUG_REG17(avalid_q, aready_q, aid_q, alen_q_2_0, arvalid_q, arready_q, arid_q, arlen_q_1_0, rvalid_q, rready_q, rlast_q, rid_q, wvalid_q, wready_q, wlast_q, wid_q, bvalid_q, bready_q, bid_q) \ + ((avalid_q << MH_DEBUG_REG17_AVALID_q_SHIFT) | \ + (aready_q << MH_DEBUG_REG17_AREADY_q_SHIFT) | \ + (aid_q << MH_DEBUG_REG17_AID_q_SHIFT) | \ + (alen_q_2_0 << MH_DEBUG_REG17_ALEN_q_2_0_SHIFT) | \ + (arvalid_q << MH_DEBUG_REG17_ARVALID_q_SHIFT) | \ + (arready_q << MH_DEBUG_REG17_ARREADY_q_SHIFT) | \ + (arid_q << MH_DEBUG_REG17_ARID_q_SHIFT) | \ + (arlen_q_1_0 << MH_DEBUG_REG17_ARLEN_q_1_0_SHIFT) | \ + (rvalid_q << MH_DEBUG_REG17_RVALID_q_SHIFT) | \ + (rready_q << MH_DEBUG_REG17_RREADY_q_SHIFT) | \ + (rlast_q << MH_DEBUG_REG17_RLAST_q_SHIFT) | \ + (rid_q << MH_DEBUG_REG17_RID_q_SHIFT) | \ + (wvalid_q << MH_DEBUG_REG17_WVALID_q_SHIFT) | \ + (wready_q << MH_DEBUG_REG17_WREADY_q_SHIFT) | \ + (wlast_q << MH_DEBUG_REG17_WLAST_q_SHIFT) | \ + (wid_q << MH_DEBUG_REG17_WID_q_SHIFT) | \ + (bvalid_q << MH_DEBUG_REG17_BVALID_q_SHIFT) | \ + (bready_q << MH_DEBUG_REG17_BREADY_q_SHIFT) | \ + (bid_q << MH_DEBUG_REG17_BID_q_SHIFT)) + +#define MH_DEBUG_REG17_GET_AVALID_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_AVALID_q_MASK) >> MH_DEBUG_REG17_AVALID_q_SHIFT) +#define MH_DEBUG_REG17_GET_AREADY_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_AREADY_q_MASK) >> MH_DEBUG_REG17_AREADY_q_SHIFT) +#define MH_DEBUG_REG17_GET_AID_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_AID_q_MASK) >> MH_DEBUG_REG17_AID_q_SHIFT) +#define MH_DEBUG_REG17_GET_ALEN_q_2_0(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_ALEN_q_2_0_MASK) >> MH_DEBUG_REG17_ALEN_q_2_0_SHIFT) +#define MH_DEBUG_REG17_GET_ARVALID_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_ARVALID_q_MASK) >> MH_DEBUG_REG17_ARVALID_q_SHIFT) +#define MH_DEBUG_REG17_GET_ARREADY_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_ARREADY_q_MASK) >> MH_DEBUG_REG17_ARREADY_q_SHIFT) +#define MH_DEBUG_REG17_GET_ARID_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_ARID_q_MASK) >> MH_DEBUG_REG17_ARID_q_SHIFT) +#define MH_DEBUG_REG17_GET_ARLEN_q_1_0(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_ARLEN_q_1_0_MASK) >> MH_DEBUG_REG17_ARLEN_q_1_0_SHIFT) +#define MH_DEBUG_REG17_GET_RVALID_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_RVALID_q_MASK) >> MH_DEBUG_REG17_RVALID_q_SHIFT) +#define MH_DEBUG_REG17_GET_RREADY_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_RREADY_q_MASK) >> MH_DEBUG_REG17_RREADY_q_SHIFT) +#define MH_DEBUG_REG17_GET_RLAST_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_RLAST_q_MASK) >> MH_DEBUG_REG17_RLAST_q_SHIFT) +#define MH_DEBUG_REG17_GET_RID_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_RID_q_MASK) >> MH_DEBUG_REG17_RID_q_SHIFT) +#define MH_DEBUG_REG17_GET_WVALID_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_WVALID_q_MASK) >> MH_DEBUG_REG17_WVALID_q_SHIFT) +#define MH_DEBUG_REG17_GET_WREADY_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_WREADY_q_MASK) >> MH_DEBUG_REG17_WREADY_q_SHIFT) +#define MH_DEBUG_REG17_GET_WLAST_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_WLAST_q_MASK) >> MH_DEBUG_REG17_WLAST_q_SHIFT) +#define MH_DEBUG_REG17_GET_WID_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_WID_q_MASK) >> MH_DEBUG_REG17_WID_q_SHIFT) +#define MH_DEBUG_REG17_GET_BVALID_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_BVALID_q_MASK) >> MH_DEBUG_REG17_BVALID_q_SHIFT) +#define MH_DEBUG_REG17_GET_BREADY_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_BREADY_q_MASK) >> MH_DEBUG_REG17_BREADY_q_SHIFT) +#define MH_DEBUG_REG17_GET_BID_q(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_BID_q_MASK) >> MH_DEBUG_REG17_BID_q_SHIFT) + +#define MH_DEBUG_REG17_SET_AVALID_q(mh_debug_reg17_reg, avalid_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_AVALID_q_MASK) | (avalid_q << MH_DEBUG_REG17_AVALID_q_SHIFT) +#define MH_DEBUG_REG17_SET_AREADY_q(mh_debug_reg17_reg, aready_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_AREADY_q_MASK) | (aready_q << MH_DEBUG_REG17_AREADY_q_SHIFT) +#define MH_DEBUG_REG17_SET_AID_q(mh_debug_reg17_reg, aid_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_AID_q_MASK) | (aid_q << MH_DEBUG_REG17_AID_q_SHIFT) +#define MH_DEBUG_REG17_SET_ALEN_q_2_0(mh_debug_reg17_reg, alen_q_2_0) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_ALEN_q_2_0_MASK) | (alen_q_2_0 << MH_DEBUG_REG17_ALEN_q_2_0_SHIFT) +#define MH_DEBUG_REG17_SET_ARVALID_q(mh_debug_reg17_reg, arvalid_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_ARVALID_q_MASK) | (arvalid_q << MH_DEBUG_REG17_ARVALID_q_SHIFT) +#define MH_DEBUG_REG17_SET_ARREADY_q(mh_debug_reg17_reg, arready_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_ARREADY_q_MASK) | (arready_q << MH_DEBUG_REG17_ARREADY_q_SHIFT) +#define MH_DEBUG_REG17_SET_ARID_q(mh_debug_reg17_reg, arid_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_ARID_q_MASK) | (arid_q << MH_DEBUG_REG17_ARID_q_SHIFT) +#define MH_DEBUG_REG17_SET_ARLEN_q_1_0(mh_debug_reg17_reg, arlen_q_1_0) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_ARLEN_q_1_0_MASK) | (arlen_q_1_0 << MH_DEBUG_REG17_ARLEN_q_1_0_SHIFT) +#define MH_DEBUG_REG17_SET_RVALID_q(mh_debug_reg17_reg, rvalid_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_RVALID_q_MASK) | (rvalid_q << MH_DEBUG_REG17_RVALID_q_SHIFT) +#define MH_DEBUG_REG17_SET_RREADY_q(mh_debug_reg17_reg, rready_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_RREADY_q_MASK) | (rready_q << MH_DEBUG_REG17_RREADY_q_SHIFT) +#define MH_DEBUG_REG17_SET_RLAST_q(mh_debug_reg17_reg, rlast_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_RLAST_q_MASK) | (rlast_q << MH_DEBUG_REG17_RLAST_q_SHIFT) +#define MH_DEBUG_REG17_SET_RID_q(mh_debug_reg17_reg, rid_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_RID_q_MASK) | (rid_q << MH_DEBUG_REG17_RID_q_SHIFT) +#define MH_DEBUG_REG17_SET_WVALID_q(mh_debug_reg17_reg, wvalid_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_WVALID_q_MASK) | (wvalid_q << MH_DEBUG_REG17_WVALID_q_SHIFT) +#define MH_DEBUG_REG17_SET_WREADY_q(mh_debug_reg17_reg, wready_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_WREADY_q_MASK) | (wready_q << MH_DEBUG_REG17_WREADY_q_SHIFT) +#define MH_DEBUG_REG17_SET_WLAST_q(mh_debug_reg17_reg, wlast_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG17_WLAST_q_SHIFT) +#define MH_DEBUG_REG17_SET_WID_q(mh_debug_reg17_reg, wid_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_WID_q_MASK) | (wid_q << MH_DEBUG_REG17_WID_q_SHIFT) +#define MH_DEBUG_REG17_SET_BVALID_q(mh_debug_reg17_reg, bvalid_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG17_BVALID_q_SHIFT) +#define MH_DEBUG_REG17_SET_BREADY_q(mh_debug_reg17_reg, bready_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG17_BREADY_q_SHIFT) +#define MH_DEBUG_REG17_SET_BID_q(mh_debug_reg17_reg, bid_q) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_BID_q_MASK) | (bid_q << MH_DEBUG_REG17_BID_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg17_t { + unsigned int avalid_q : MH_DEBUG_REG17_AVALID_q_SIZE; + unsigned int aready_q : MH_DEBUG_REG17_AREADY_q_SIZE; + unsigned int aid_q : MH_DEBUG_REG17_AID_q_SIZE; + unsigned int alen_q_2_0 : MH_DEBUG_REG17_ALEN_q_2_0_SIZE; + unsigned int arvalid_q : MH_DEBUG_REG17_ARVALID_q_SIZE; + unsigned int arready_q : MH_DEBUG_REG17_ARREADY_q_SIZE; + unsigned int arid_q : MH_DEBUG_REG17_ARID_q_SIZE; + unsigned int arlen_q_1_0 : MH_DEBUG_REG17_ARLEN_q_1_0_SIZE; + unsigned int rvalid_q : MH_DEBUG_REG17_RVALID_q_SIZE; + unsigned int rready_q : MH_DEBUG_REG17_RREADY_q_SIZE; + unsigned int rlast_q : MH_DEBUG_REG17_RLAST_q_SIZE; + unsigned int rid_q : MH_DEBUG_REG17_RID_q_SIZE; + unsigned int wvalid_q : MH_DEBUG_REG17_WVALID_q_SIZE; + unsigned int wready_q : MH_DEBUG_REG17_WREADY_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG17_WLAST_q_SIZE; + unsigned int wid_q : MH_DEBUG_REG17_WID_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG17_BVALID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG17_BREADY_q_SIZE; + unsigned int bid_q : MH_DEBUG_REG17_BID_q_SIZE; + } mh_debug_reg17_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg17_t { + unsigned int bid_q : MH_DEBUG_REG17_BID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG17_BREADY_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG17_BVALID_q_SIZE; + unsigned int wid_q : MH_DEBUG_REG17_WID_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG17_WLAST_q_SIZE; + unsigned int wready_q : MH_DEBUG_REG17_WREADY_q_SIZE; + unsigned int wvalid_q : MH_DEBUG_REG17_WVALID_q_SIZE; + unsigned int rid_q : MH_DEBUG_REG17_RID_q_SIZE; + unsigned int rlast_q : MH_DEBUG_REG17_RLAST_q_SIZE; + unsigned int rready_q : MH_DEBUG_REG17_RREADY_q_SIZE; + unsigned int rvalid_q : MH_DEBUG_REG17_RVALID_q_SIZE; + unsigned int arlen_q_1_0 : MH_DEBUG_REG17_ARLEN_q_1_0_SIZE; + unsigned int arid_q : MH_DEBUG_REG17_ARID_q_SIZE; + unsigned int arready_q : MH_DEBUG_REG17_ARREADY_q_SIZE; + unsigned int arvalid_q : MH_DEBUG_REG17_ARVALID_q_SIZE; + unsigned int alen_q_2_0 : MH_DEBUG_REG17_ALEN_q_2_0_SIZE; + unsigned int aid_q : MH_DEBUG_REG17_AID_q_SIZE; + unsigned int aready_q : MH_DEBUG_REG17_AREADY_q_SIZE; + unsigned int avalid_q : MH_DEBUG_REG17_AVALID_q_SIZE; + } mh_debug_reg17_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg17_t f; +} mh_debug_reg17_u; + + +/* + * MH_DEBUG_REG18 struct + */ + +#define MH_DEBUG_REG18_AVALID_q_SIZE 1 +#define MH_DEBUG_REG18_AREADY_q_SIZE 1 +#define MH_DEBUG_REG18_AID_q_SIZE 3 +#define MH_DEBUG_REG18_ALEN_q_1_0_SIZE 2 +#define MH_DEBUG_REG18_ARVALID_q_SIZE 1 +#define MH_DEBUG_REG18_ARREADY_q_SIZE 1 +#define MH_DEBUG_REG18_ARID_q_SIZE 3 +#define MH_DEBUG_REG18_ARLEN_q_1_1_SIZE 1 +#define MH_DEBUG_REG18_WVALID_q_SIZE 1 +#define MH_DEBUG_REG18_WREADY_q_SIZE 1 +#define MH_DEBUG_REG18_WLAST_q_SIZE 1 +#define MH_DEBUG_REG18_WID_q_SIZE 3 +#define MH_DEBUG_REG18_WSTRB_q_SIZE 8 +#define MH_DEBUG_REG18_BVALID_q_SIZE 1 +#define MH_DEBUG_REG18_BREADY_q_SIZE 1 +#define MH_DEBUG_REG18_BID_q_SIZE 3 + +#define MH_DEBUG_REG18_AVALID_q_SHIFT 0 +#define MH_DEBUG_REG18_AREADY_q_SHIFT 1 +#define MH_DEBUG_REG18_AID_q_SHIFT 2 +#define MH_DEBUG_REG18_ALEN_q_1_0_SHIFT 5 +#define MH_DEBUG_REG18_ARVALID_q_SHIFT 7 +#define MH_DEBUG_REG18_ARREADY_q_SHIFT 8 +#define MH_DEBUG_REG18_ARID_q_SHIFT 9 +#define MH_DEBUG_REG18_ARLEN_q_1_1_SHIFT 12 +#define MH_DEBUG_REG18_WVALID_q_SHIFT 13 +#define MH_DEBUG_REG18_WREADY_q_SHIFT 14 +#define MH_DEBUG_REG18_WLAST_q_SHIFT 15 +#define MH_DEBUG_REG18_WID_q_SHIFT 16 +#define MH_DEBUG_REG18_WSTRB_q_SHIFT 19 +#define MH_DEBUG_REG18_BVALID_q_SHIFT 27 +#define MH_DEBUG_REG18_BREADY_q_SHIFT 28 +#define MH_DEBUG_REG18_BID_q_SHIFT 29 + +#define MH_DEBUG_REG18_AVALID_q_MASK 0x00000001 +#define MH_DEBUG_REG18_AREADY_q_MASK 0x00000002 +#define MH_DEBUG_REG18_AID_q_MASK 0x0000001c +#define MH_DEBUG_REG18_ALEN_q_1_0_MASK 0x00000060 +#define MH_DEBUG_REG18_ARVALID_q_MASK 0x00000080 +#define MH_DEBUG_REG18_ARREADY_q_MASK 0x00000100 +#define MH_DEBUG_REG18_ARID_q_MASK 0x00000e00 +#define MH_DEBUG_REG18_ARLEN_q_1_1_MASK 0x00001000 +#define MH_DEBUG_REG18_WVALID_q_MASK 0x00002000 +#define MH_DEBUG_REG18_WREADY_q_MASK 0x00004000 +#define MH_DEBUG_REG18_WLAST_q_MASK 0x00008000 +#define MH_DEBUG_REG18_WID_q_MASK 0x00070000 +#define MH_DEBUG_REG18_WSTRB_q_MASK 0x07f80000 +#define MH_DEBUG_REG18_BVALID_q_MASK 0x08000000 +#define MH_DEBUG_REG18_BREADY_q_MASK 0x10000000 +#define MH_DEBUG_REG18_BID_q_MASK 0xe0000000 + +#define MH_DEBUG_REG18_MASK \ + (MH_DEBUG_REG18_AVALID_q_MASK | \ + MH_DEBUG_REG18_AREADY_q_MASK | \ + MH_DEBUG_REG18_AID_q_MASK | \ + MH_DEBUG_REG18_ALEN_q_1_0_MASK | \ + MH_DEBUG_REG18_ARVALID_q_MASK | \ + MH_DEBUG_REG18_ARREADY_q_MASK | \ + MH_DEBUG_REG18_ARID_q_MASK | \ + MH_DEBUG_REG18_ARLEN_q_1_1_MASK | \ + MH_DEBUG_REG18_WVALID_q_MASK | \ + MH_DEBUG_REG18_WREADY_q_MASK | \ + MH_DEBUG_REG18_WLAST_q_MASK | \ + MH_DEBUG_REG18_WID_q_MASK | \ + MH_DEBUG_REG18_WSTRB_q_MASK | \ + MH_DEBUG_REG18_BVALID_q_MASK | \ + MH_DEBUG_REG18_BREADY_q_MASK | \ + MH_DEBUG_REG18_BID_q_MASK) + +#define MH_DEBUG_REG18(avalid_q, aready_q, aid_q, alen_q_1_0, arvalid_q, arready_q, arid_q, arlen_q_1_1, wvalid_q, wready_q, wlast_q, wid_q, wstrb_q, bvalid_q, bready_q, bid_q) \ + ((avalid_q << MH_DEBUG_REG18_AVALID_q_SHIFT) | \ + (aready_q << MH_DEBUG_REG18_AREADY_q_SHIFT) | \ + (aid_q << MH_DEBUG_REG18_AID_q_SHIFT) | \ + (alen_q_1_0 << MH_DEBUG_REG18_ALEN_q_1_0_SHIFT) | \ + (arvalid_q << MH_DEBUG_REG18_ARVALID_q_SHIFT) | \ + (arready_q << MH_DEBUG_REG18_ARREADY_q_SHIFT) | \ + (arid_q << MH_DEBUG_REG18_ARID_q_SHIFT) | \ + (arlen_q_1_1 << MH_DEBUG_REG18_ARLEN_q_1_1_SHIFT) | \ + (wvalid_q << MH_DEBUG_REG18_WVALID_q_SHIFT) | \ + (wready_q << MH_DEBUG_REG18_WREADY_q_SHIFT) | \ + (wlast_q << MH_DEBUG_REG18_WLAST_q_SHIFT) | \ + (wid_q << MH_DEBUG_REG18_WID_q_SHIFT) | \ + (wstrb_q << MH_DEBUG_REG18_WSTRB_q_SHIFT) | \ + (bvalid_q << MH_DEBUG_REG18_BVALID_q_SHIFT) | \ + (bready_q << MH_DEBUG_REG18_BREADY_q_SHIFT) | \ + (bid_q << MH_DEBUG_REG18_BID_q_SHIFT)) + +#define MH_DEBUG_REG18_GET_AVALID_q(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_AVALID_q_MASK) >> MH_DEBUG_REG18_AVALID_q_SHIFT) +#define MH_DEBUG_REG18_GET_AREADY_q(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_AREADY_q_MASK) >> MH_DEBUG_REG18_AREADY_q_SHIFT) +#define MH_DEBUG_REG18_GET_AID_q(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_AID_q_MASK) >> MH_DEBUG_REG18_AID_q_SHIFT) +#define MH_DEBUG_REG18_GET_ALEN_q_1_0(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_ALEN_q_1_0_MASK) >> MH_DEBUG_REG18_ALEN_q_1_0_SHIFT) +#define MH_DEBUG_REG18_GET_ARVALID_q(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_ARVALID_q_MASK) >> MH_DEBUG_REG18_ARVALID_q_SHIFT) +#define MH_DEBUG_REG18_GET_ARREADY_q(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_ARREADY_q_MASK) >> MH_DEBUG_REG18_ARREADY_q_SHIFT) +#define MH_DEBUG_REG18_GET_ARID_q(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_ARID_q_MASK) >> MH_DEBUG_REG18_ARID_q_SHIFT) +#define MH_DEBUG_REG18_GET_ARLEN_q_1_1(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_ARLEN_q_1_1_MASK) >> MH_DEBUG_REG18_ARLEN_q_1_1_SHIFT) +#define MH_DEBUG_REG18_GET_WVALID_q(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_WVALID_q_MASK) >> MH_DEBUG_REG18_WVALID_q_SHIFT) +#define MH_DEBUG_REG18_GET_WREADY_q(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_WREADY_q_MASK) >> MH_DEBUG_REG18_WREADY_q_SHIFT) +#define MH_DEBUG_REG18_GET_WLAST_q(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_WLAST_q_MASK) >> MH_DEBUG_REG18_WLAST_q_SHIFT) +#define MH_DEBUG_REG18_GET_WID_q(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_WID_q_MASK) >> MH_DEBUG_REG18_WID_q_SHIFT) +#define MH_DEBUG_REG18_GET_WSTRB_q(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_WSTRB_q_MASK) >> MH_DEBUG_REG18_WSTRB_q_SHIFT) +#define MH_DEBUG_REG18_GET_BVALID_q(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_BVALID_q_MASK) >> MH_DEBUG_REG18_BVALID_q_SHIFT) +#define MH_DEBUG_REG18_GET_BREADY_q(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_BREADY_q_MASK) >> MH_DEBUG_REG18_BREADY_q_SHIFT) +#define MH_DEBUG_REG18_GET_BID_q(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_BID_q_MASK) >> MH_DEBUG_REG18_BID_q_SHIFT) + +#define MH_DEBUG_REG18_SET_AVALID_q(mh_debug_reg18_reg, avalid_q) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_AVALID_q_MASK) | (avalid_q << MH_DEBUG_REG18_AVALID_q_SHIFT) +#define MH_DEBUG_REG18_SET_AREADY_q(mh_debug_reg18_reg, aready_q) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_AREADY_q_MASK) | (aready_q << MH_DEBUG_REG18_AREADY_q_SHIFT) +#define MH_DEBUG_REG18_SET_AID_q(mh_debug_reg18_reg, aid_q) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_AID_q_MASK) | (aid_q << MH_DEBUG_REG18_AID_q_SHIFT) +#define MH_DEBUG_REG18_SET_ALEN_q_1_0(mh_debug_reg18_reg, alen_q_1_0) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_ALEN_q_1_0_MASK) | (alen_q_1_0 << MH_DEBUG_REG18_ALEN_q_1_0_SHIFT) +#define MH_DEBUG_REG18_SET_ARVALID_q(mh_debug_reg18_reg, arvalid_q) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_ARVALID_q_MASK) | (arvalid_q << MH_DEBUG_REG18_ARVALID_q_SHIFT) +#define MH_DEBUG_REG18_SET_ARREADY_q(mh_debug_reg18_reg, arready_q) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_ARREADY_q_MASK) | (arready_q << MH_DEBUG_REG18_ARREADY_q_SHIFT) +#define MH_DEBUG_REG18_SET_ARID_q(mh_debug_reg18_reg, arid_q) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_ARID_q_MASK) | (arid_q << MH_DEBUG_REG18_ARID_q_SHIFT) +#define MH_DEBUG_REG18_SET_ARLEN_q_1_1(mh_debug_reg18_reg, arlen_q_1_1) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_ARLEN_q_1_1_MASK) | (arlen_q_1_1 << MH_DEBUG_REG18_ARLEN_q_1_1_SHIFT) +#define MH_DEBUG_REG18_SET_WVALID_q(mh_debug_reg18_reg, wvalid_q) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_WVALID_q_MASK) | (wvalid_q << MH_DEBUG_REG18_WVALID_q_SHIFT) +#define MH_DEBUG_REG18_SET_WREADY_q(mh_debug_reg18_reg, wready_q) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_WREADY_q_MASK) | (wready_q << MH_DEBUG_REG18_WREADY_q_SHIFT) +#define MH_DEBUG_REG18_SET_WLAST_q(mh_debug_reg18_reg, wlast_q) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG18_WLAST_q_SHIFT) +#define MH_DEBUG_REG18_SET_WID_q(mh_debug_reg18_reg, wid_q) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_WID_q_MASK) | (wid_q << MH_DEBUG_REG18_WID_q_SHIFT) +#define MH_DEBUG_REG18_SET_WSTRB_q(mh_debug_reg18_reg, wstrb_q) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_WSTRB_q_MASK) | (wstrb_q << MH_DEBUG_REG18_WSTRB_q_SHIFT) +#define MH_DEBUG_REG18_SET_BVALID_q(mh_debug_reg18_reg, bvalid_q) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG18_BVALID_q_SHIFT) +#define MH_DEBUG_REG18_SET_BREADY_q(mh_debug_reg18_reg, bready_q) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG18_BREADY_q_SHIFT) +#define MH_DEBUG_REG18_SET_BID_q(mh_debug_reg18_reg, bid_q) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_BID_q_MASK) | (bid_q << MH_DEBUG_REG18_BID_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg18_t { + unsigned int avalid_q : MH_DEBUG_REG18_AVALID_q_SIZE; + unsigned int aready_q : MH_DEBUG_REG18_AREADY_q_SIZE; + unsigned int aid_q : MH_DEBUG_REG18_AID_q_SIZE; + unsigned int alen_q_1_0 : MH_DEBUG_REG18_ALEN_q_1_0_SIZE; + unsigned int arvalid_q : MH_DEBUG_REG18_ARVALID_q_SIZE; + unsigned int arready_q : MH_DEBUG_REG18_ARREADY_q_SIZE; + unsigned int arid_q : MH_DEBUG_REG18_ARID_q_SIZE; + unsigned int arlen_q_1_1 : MH_DEBUG_REG18_ARLEN_q_1_1_SIZE; + unsigned int wvalid_q : MH_DEBUG_REG18_WVALID_q_SIZE; + unsigned int wready_q : MH_DEBUG_REG18_WREADY_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG18_WLAST_q_SIZE; + unsigned int wid_q : MH_DEBUG_REG18_WID_q_SIZE; + unsigned int wstrb_q : MH_DEBUG_REG18_WSTRB_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG18_BVALID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG18_BREADY_q_SIZE; + unsigned int bid_q : MH_DEBUG_REG18_BID_q_SIZE; + } mh_debug_reg18_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg18_t { + unsigned int bid_q : MH_DEBUG_REG18_BID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG18_BREADY_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG18_BVALID_q_SIZE; + unsigned int wstrb_q : MH_DEBUG_REG18_WSTRB_q_SIZE; + unsigned int wid_q : MH_DEBUG_REG18_WID_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG18_WLAST_q_SIZE; + unsigned int wready_q : MH_DEBUG_REG18_WREADY_q_SIZE; + unsigned int wvalid_q : MH_DEBUG_REG18_WVALID_q_SIZE; + unsigned int arlen_q_1_1 : MH_DEBUG_REG18_ARLEN_q_1_1_SIZE; + unsigned int arid_q : MH_DEBUG_REG18_ARID_q_SIZE; + unsigned int arready_q : MH_DEBUG_REG18_ARREADY_q_SIZE; + unsigned int arvalid_q : MH_DEBUG_REG18_ARVALID_q_SIZE; + unsigned int alen_q_1_0 : MH_DEBUG_REG18_ALEN_q_1_0_SIZE; + unsigned int aid_q : MH_DEBUG_REG18_AID_q_SIZE; + unsigned int aready_q : MH_DEBUG_REG18_AREADY_q_SIZE; + unsigned int avalid_q : MH_DEBUG_REG18_AVALID_q_SIZE; + } mh_debug_reg18_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg18_t f; +} mh_debug_reg18_u; + + +/* + * MH_DEBUG_REG19 struct + */ + +#define MH_DEBUG_REG19_ARC_CTRL_RE_q_SIZE 1 +#define MH_DEBUG_REG19_CTRL_ARC_ID_SIZE 3 +#define MH_DEBUG_REG19_CTRL_ARC_PAD_SIZE 28 + +#define MH_DEBUG_REG19_ARC_CTRL_RE_q_SHIFT 0 +#define MH_DEBUG_REG19_CTRL_ARC_ID_SHIFT 1 +#define MH_DEBUG_REG19_CTRL_ARC_PAD_SHIFT 4 + +#define MH_DEBUG_REG19_ARC_CTRL_RE_q_MASK 0x00000001 +#define MH_DEBUG_REG19_CTRL_ARC_ID_MASK 0x0000000e +#define MH_DEBUG_REG19_CTRL_ARC_PAD_MASK 0xfffffff0 + +#define MH_DEBUG_REG19_MASK \ + (MH_DEBUG_REG19_ARC_CTRL_RE_q_MASK | \ + MH_DEBUG_REG19_CTRL_ARC_ID_MASK | \ + MH_DEBUG_REG19_CTRL_ARC_PAD_MASK) + +#define MH_DEBUG_REG19(arc_ctrl_re_q, ctrl_arc_id, ctrl_arc_pad) \ + ((arc_ctrl_re_q << MH_DEBUG_REG19_ARC_CTRL_RE_q_SHIFT) | \ + (ctrl_arc_id << MH_DEBUG_REG19_CTRL_ARC_ID_SHIFT) | \ + (ctrl_arc_pad << MH_DEBUG_REG19_CTRL_ARC_PAD_SHIFT)) + +#define MH_DEBUG_REG19_GET_ARC_CTRL_RE_q(mh_debug_reg19) \ + ((mh_debug_reg19 & MH_DEBUG_REG19_ARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG19_ARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG19_GET_CTRL_ARC_ID(mh_debug_reg19) \ + ((mh_debug_reg19 & MH_DEBUG_REG19_CTRL_ARC_ID_MASK) >> MH_DEBUG_REG19_CTRL_ARC_ID_SHIFT) +#define MH_DEBUG_REG19_GET_CTRL_ARC_PAD(mh_debug_reg19) \ + ((mh_debug_reg19 & MH_DEBUG_REG19_CTRL_ARC_PAD_MASK) >> MH_DEBUG_REG19_CTRL_ARC_PAD_SHIFT) + +#define MH_DEBUG_REG19_SET_ARC_CTRL_RE_q(mh_debug_reg19_reg, arc_ctrl_re_q) \ + mh_debug_reg19_reg = (mh_debug_reg19_reg & ~MH_DEBUG_REG19_ARC_CTRL_RE_q_MASK) | (arc_ctrl_re_q << MH_DEBUG_REG19_ARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG19_SET_CTRL_ARC_ID(mh_debug_reg19_reg, ctrl_arc_id) \ + mh_debug_reg19_reg = (mh_debug_reg19_reg & ~MH_DEBUG_REG19_CTRL_ARC_ID_MASK) | (ctrl_arc_id << MH_DEBUG_REG19_CTRL_ARC_ID_SHIFT) +#define MH_DEBUG_REG19_SET_CTRL_ARC_PAD(mh_debug_reg19_reg, ctrl_arc_pad) \ + mh_debug_reg19_reg = (mh_debug_reg19_reg & ~MH_DEBUG_REG19_CTRL_ARC_PAD_MASK) | (ctrl_arc_pad << MH_DEBUG_REG19_CTRL_ARC_PAD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg19_t { + unsigned int arc_ctrl_re_q : MH_DEBUG_REG19_ARC_CTRL_RE_q_SIZE; + unsigned int ctrl_arc_id : MH_DEBUG_REG19_CTRL_ARC_ID_SIZE; + unsigned int ctrl_arc_pad : MH_DEBUG_REG19_CTRL_ARC_PAD_SIZE; + } mh_debug_reg19_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg19_t { + unsigned int ctrl_arc_pad : MH_DEBUG_REG19_CTRL_ARC_PAD_SIZE; + unsigned int ctrl_arc_id : MH_DEBUG_REG19_CTRL_ARC_ID_SIZE; + unsigned int arc_ctrl_re_q : MH_DEBUG_REG19_ARC_CTRL_RE_q_SIZE; + } mh_debug_reg19_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg19_t f; +} mh_debug_reg19_u; + + +/* + * MH_DEBUG_REG20 struct + */ + +#define MH_DEBUG_REG20_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG20_REG_A_SIZE 14 +#define MH_DEBUG_REG20_REG_RE_SIZE 1 +#define MH_DEBUG_REG20_REG_WE_SIZE 1 +#define MH_DEBUG_REG20_BLOCK_RS_SIZE 1 + +#define MH_DEBUG_REG20_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG20_REG_A_SHIFT 2 +#define MH_DEBUG_REG20_REG_RE_SHIFT 16 +#define MH_DEBUG_REG20_REG_WE_SHIFT 17 +#define MH_DEBUG_REG20_BLOCK_RS_SHIFT 18 + +#define MH_DEBUG_REG20_ALWAYS_ZERO_MASK 0x00000003 +#define MH_DEBUG_REG20_REG_A_MASK 0x0000fffc +#define MH_DEBUG_REG20_REG_RE_MASK 0x00010000 +#define MH_DEBUG_REG20_REG_WE_MASK 0x00020000 +#define MH_DEBUG_REG20_BLOCK_RS_MASK 0x00040000 + +#define MH_DEBUG_REG20_MASK \ + (MH_DEBUG_REG20_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG20_REG_A_MASK | \ + MH_DEBUG_REG20_REG_RE_MASK | \ + MH_DEBUG_REG20_REG_WE_MASK | \ + MH_DEBUG_REG20_BLOCK_RS_MASK) + +#define MH_DEBUG_REG20(always_zero, reg_a, reg_re, reg_we, block_rs) \ + ((always_zero << MH_DEBUG_REG20_ALWAYS_ZERO_SHIFT) | \ + (reg_a << MH_DEBUG_REG20_REG_A_SHIFT) | \ + (reg_re << MH_DEBUG_REG20_REG_RE_SHIFT) | \ + (reg_we << MH_DEBUG_REG20_REG_WE_SHIFT) | \ + (block_rs << MH_DEBUG_REG20_BLOCK_RS_SHIFT)) + +#define MH_DEBUG_REG20_GET_ALWAYS_ZERO(mh_debug_reg20) \ + ((mh_debug_reg20 & MH_DEBUG_REG20_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG20_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG20_GET_REG_A(mh_debug_reg20) \ + ((mh_debug_reg20 & MH_DEBUG_REG20_REG_A_MASK) >> MH_DEBUG_REG20_REG_A_SHIFT) +#define MH_DEBUG_REG20_GET_REG_RE(mh_debug_reg20) \ + ((mh_debug_reg20 & MH_DEBUG_REG20_REG_RE_MASK) >> MH_DEBUG_REG20_REG_RE_SHIFT) +#define MH_DEBUG_REG20_GET_REG_WE(mh_debug_reg20) \ + ((mh_debug_reg20 & MH_DEBUG_REG20_REG_WE_MASK) >> MH_DEBUG_REG20_REG_WE_SHIFT) +#define MH_DEBUG_REG20_GET_BLOCK_RS(mh_debug_reg20) \ + ((mh_debug_reg20 & MH_DEBUG_REG20_BLOCK_RS_MASK) >> MH_DEBUG_REG20_BLOCK_RS_SHIFT) + +#define MH_DEBUG_REG20_SET_ALWAYS_ZERO(mh_debug_reg20_reg, always_zero) \ + mh_debug_reg20_reg = (mh_debug_reg20_reg & ~MH_DEBUG_REG20_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG20_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG20_SET_REG_A(mh_debug_reg20_reg, reg_a) \ + mh_debug_reg20_reg = (mh_debug_reg20_reg & ~MH_DEBUG_REG20_REG_A_MASK) | (reg_a << MH_DEBUG_REG20_REG_A_SHIFT) +#define MH_DEBUG_REG20_SET_REG_RE(mh_debug_reg20_reg, reg_re) \ + mh_debug_reg20_reg = (mh_debug_reg20_reg & ~MH_DEBUG_REG20_REG_RE_MASK) | (reg_re << MH_DEBUG_REG20_REG_RE_SHIFT) +#define MH_DEBUG_REG20_SET_REG_WE(mh_debug_reg20_reg, reg_we) \ + mh_debug_reg20_reg = (mh_debug_reg20_reg & ~MH_DEBUG_REG20_REG_WE_MASK) | (reg_we << MH_DEBUG_REG20_REG_WE_SHIFT) +#define MH_DEBUG_REG20_SET_BLOCK_RS(mh_debug_reg20_reg, block_rs) \ + mh_debug_reg20_reg = (mh_debug_reg20_reg & ~MH_DEBUG_REG20_BLOCK_RS_MASK) | (block_rs << MH_DEBUG_REG20_BLOCK_RS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg20_t { + unsigned int always_zero : MH_DEBUG_REG20_ALWAYS_ZERO_SIZE; + unsigned int reg_a : MH_DEBUG_REG20_REG_A_SIZE; + unsigned int reg_re : MH_DEBUG_REG20_REG_RE_SIZE; + unsigned int reg_we : MH_DEBUG_REG20_REG_WE_SIZE; + unsigned int block_rs : MH_DEBUG_REG20_BLOCK_RS_SIZE; + unsigned int : 13; + } mh_debug_reg20_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg20_t { + unsigned int : 13; + unsigned int block_rs : MH_DEBUG_REG20_BLOCK_RS_SIZE; + unsigned int reg_we : MH_DEBUG_REG20_REG_WE_SIZE; + unsigned int reg_re : MH_DEBUG_REG20_REG_RE_SIZE; + unsigned int reg_a : MH_DEBUG_REG20_REG_A_SIZE; + unsigned int always_zero : MH_DEBUG_REG20_ALWAYS_ZERO_SIZE; + } mh_debug_reg20_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg20_t f; +} mh_debug_reg20_u; + + +/* + * MH_DEBUG_REG21 struct + */ + +#define MH_DEBUG_REG21_REG_WD_SIZE 32 + +#define MH_DEBUG_REG21_REG_WD_SHIFT 0 + +#define MH_DEBUG_REG21_REG_WD_MASK 0xffffffff + +#define MH_DEBUG_REG21_MASK \ + (MH_DEBUG_REG21_REG_WD_MASK) + +#define MH_DEBUG_REG21(reg_wd) \ + ((reg_wd << MH_DEBUG_REG21_REG_WD_SHIFT)) + +#define MH_DEBUG_REG21_GET_REG_WD(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_REG_WD_MASK) >> MH_DEBUG_REG21_REG_WD_SHIFT) + +#define MH_DEBUG_REG21_SET_REG_WD(mh_debug_reg21_reg, reg_wd) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_REG_WD_MASK) | (reg_wd << MH_DEBUG_REG21_REG_WD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg21_t { + unsigned int reg_wd : MH_DEBUG_REG21_REG_WD_SIZE; + } mh_debug_reg21_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg21_t { + unsigned int reg_wd : MH_DEBUG_REG21_REG_WD_SIZE; + } mh_debug_reg21_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg21_t f; +} mh_debug_reg21_u; + + +/* + * MH_DEBUG_REG22 struct + */ + +#define MH_DEBUG_REG22_CIB_MH_axi_halt_req_SIZE 1 +#define MH_DEBUG_REG22_MH_CIB_axi_halt_ack_SIZE 1 +#define MH_DEBUG_REG22_MH_RBBM_busy_SIZE 1 +#define MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_SIZE 1 +#define MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_SIZE 1 +#define MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_SIZE 1 +#define MH_DEBUG_REG22_GAT_CLK_ENA_SIZE 1 +#define MH_DEBUG_REG22_AXI_RDY_ENA_SIZE 1 +#define MH_DEBUG_REG22_RBBM_MH_clk_en_override_SIZE 1 +#define MH_DEBUG_REG22_CNT_q_SIZE 6 +#define MH_DEBUG_REG22_TCD_EMPTY_q_SIZE 1 +#define MH_DEBUG_REG22_TC_ROQ_EMPTY_SIZE 1 +#define MH_DEBUG_REG22_MH_BUSY_d_SIZE 1 +#define MH_DEBUG_REG22_ANY_CLNT_BUSY_SIZE 1 +#define MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE 1 +#define MH_DEBUG_REG22_CP_SEND_q_SIZE 1 +#define MH_DEBUG_REG22_CP_RTR_q_SIZE 1 +#define MH_DEBUG_REG22_VGT_SEND_q_SIZE 1 +#define MH_DEBUG_REG22_VGT_RTR_q_SIZE 1 +#define MH_DEBUG_REG22_TC_ROQ_SEND_q_SIZE 1 +#define MH_DEBUG_REG22_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG22_RB_SEND_q_SIZE 1 +#define MH_DEBUG_REG22_RB_RTR_q_SIZE 1 +#define MH_DEBUG_REG22_RDC_VALID_SIZE 1 +#define MH_DEBUG_REG22_RDC_RLAST_SIZE 1 +#define MH_DEBUG_REG22_TLBMISS_VALID_SIZE 1 +#define MH_DEBUG_REG22_BRC_VALID_SIZE 1 + +#define MH_DEBUG_REG22_CIB_MH_axi_halt_req_SHIFT 0 +#define MH_DEBUG_REG22_MH_CIB_axi_halt_ack_SHIFT 1 +#define MH_DEBUG_REG22_MH_RBBM_busy_SHIFT 2 +#define MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_SHIFT 3 +#define MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_SHIFT 4 +#define MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_SHIFT 5 +#define MH_DEBUG_REG22_GAT_CLK_ENA_SHIFT 6 +#define MH_DEBUG_REG22_AXI_RDY_ENA_SHIFT 7 +#define MH_DEBUG_REG22_RBBM_MH_clk_en_override_SHIFT 8 +#define MH_DEBUG_REG22_CNT_q_SHIFT 9 +#define MH_DEBUG_REG22_TCD_EMPTY_q_SHIFT 15 +#define MH_DEBUG_REG22_TC_ROQ_EMPTY_SHIFT 16 +#define MH_DEBUG_REG22_MH_BUSY_d_SHIFT 17 +#define MH_DEBUG_REG22_ANY_CLNT_BUSY_SHIFT 18 +#define MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT 19 +#define MH_DEBUG_REG22_CP_SEND_q_SHIFT 20 +#define MH_DEBUG_REG22_CP_RTR_q_SHIFT 21 +#define MH_DEBUG_REG22_VGT_SEND_q_SHIFT 22 +#define MH_DEBUG_REG22_VGT_RTR_q_SHIFT 23 +#define MH_DEBUG_REG22_TC_ROQ_SEND_q_SHIFT 24 +#define MH_DEBUG_REG22_TC_ROQ_RTR_q_SHIFT 25 +#define MH_DEBUG_REG22_RB_SEND_q_SHIFT 26 +#define MH_DEBUG_REG22_RB_RTR_q_SHIFT 27 +#define MH_DEBUG_REG22_RDC_VALID_SHIFT 28 +#define MH_DEBUG_REG22_RDC_RLAST_SHIFT 29 +#define MH_DEBUG_REG22_TLBMISS_VALID_SHIFT 30 +#define MH_DEBUG_REG22_BRC_VALID_SHIFT 31 + +#define MH_DEBUG_REG22_CIB_MH_axi_halt_req_MASK 0x00000001 +#define MH_DEBUG_REG22_MH_CIB_axi_halt_ack_MASK 0x00000002 +#define MH_DEBUG_REG22_MH_RBBM_busy_MASK 0x00000004 +#define MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_MASK 0x00000008 +#define MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_MASK 0x00000010 +#define MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_MASK 0x00000020 +#define MH_DEBUG_REG22_GAT_CLK_ENA_MASK 0x00000040 +#define MH_DEBUG_REG22_AXI_RDY_ENA_MASK 0x00000080 +#define MH_DEBUG_REG22_RBBM_MH_clk_en_override_MASK 0x00000100 +#define MH_DEBUG_REG22_CNT_q_MASK 0x00007e00 +#define MH_DEBUG_REG22_TCD_EMPTY_q_MASK 0x00008000 +#define MH_DEBUG_REG22_TC_ROQ_EMPTY_MASK 0x00010000 +#define MH_DEBUG_REG22_MH_BUSY_d_MASK 0x00020000 +#define MH_DEBUG_REG22_ANY_CLNT_BUSY_MASK 0x00040000 +#define MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00080000 +#define MH_DEBUG_REG22_CP_SEND_q_MASK 0x00100000 +#define MH_DEBUG_REG22_CP_RTR_q_MASK 0x00200000 +#define MH_DEBUG_REG22_VGT_SEND_q_MASK 0x00400000 +#define MH_DEBUG_REG22_VGT_RTR_q_MASK 0x00800000 +#define MH_DEBUG_REG22_TC_ROQ_SEND_q_MASK 0x01000000 +#define MH_DEBUG_REG22_TC_ROQ_RTR_q_MASK 0x02000000 +#define MH_DEBUG_REG22_RB_SEND_q_MASK 0x04000000 +#define MH_DEBUG_REG22_RB_RTR_q_MASK 0x08000000 +#define MH_DEBUG_REG22_RDC_VALID_MASK 0x10000000 +#define MH_DEBUG_REG22_RDC_RLAST_MASK 0x20000000 +#define MH_DEBUG_REG22_TLBMISS_VALID_MASK 0x40000000 +#define MH_DEBUG_REG22_BRC_VALID_MASK 0x80000000 + +#define MH_DEBUG_REG22_MASK \ + (MH_DEBUG_REG22_CIB_MH_axi_halt_req_MASK | \ + MH_DEBUG_REG22_MH_CIB_axi_halt_ack_MASK | \ + MH_DEBUG_REG22_MH_RBBM_busy_MASK | \ + MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_MASK | \ + MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_MASK | \ + MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_MASK | \ + MH_DEBUG_REG22_GAT_CLK_ENA_MASK | \ + MH_DEBUG_REG22_AXI_RDY_ENA_MASK | \ + MH_DEBUG_REG22_RBBM_MH_clk_en_override_MASK | \ + MH_DEBUG_REG22_CNT_q_MASK | \ + MH_DEBUG_REG22_TCD_EMPTY_q_MASK | \ + MH_DEBUG_REG22_TC_ROQ_EMPTY_MASK | \ + MH_DEBUG_REG22_MH_BUSY_d_MASK | \ + MH_DEBUG_REG22_ANY_CLNT_BUSY_MASK | \ + MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK | \ + MH_DEBUG_REG22_CP_SEND_q_MASK | \ + MH_DEBUG_REG22_CP_RTR_q_MASK | \ + MH_DEBUG_REG22_VGT_SEND_q_MASK | \ + MH_DEBUG_REG22_VGT_RTR_q_MASK | \ + MH_DEBUG_REG22_TC_ROQ_SEND_q_MASK | \ + MH_DEBUG_REG22_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG22_RB_SEND_q_MASK | \ + MH_DEBUG_REG22_RB_RTR_q_MASK | \ + MH_DEBUG_REG22_RDC_VALID_MASK | \ + MH_DEBUG_REG22_RDC_RLAST_MASK | \ + MH_DEBUG_REG22_TLBMISS_VALID_MASK | \ + MH_DEBUG_REG22_BRC_VALID_MASK) + +#define MH_DEBUG_REG22(cib_mh_axi_halt_req, mh_cib_axi_halt_ack, mh_rbbm_busy, mh_cib_mh_clk_en_int, mh_cib_mmu_clk_en_int, mh_cib_tcroq_clk_en_int, gat_clk_ena, axi_rdy_ena, rbbm_mh_clk_en_override, cnt_q, tcd_empty_q, tc_roq_empty, mh_busy_d, any_clnt_busy, mh_mmu_invalidate_invalidate_all, cp_send_q, cp_rtr_q, vgt_send_q, vgt_rtr_q, tc_roq_send_q, tc_roq_rtr_q, rb_send_q, rb_rtr_q, rdc_valid, rdc_rlast, tlbmiss_valid, brc_valid) \ + ((cib_mh_axi_halt_req << MH_DEBUG_REG22_CIB_MH_axi_halt_req_SHIFT) | \ + (mh_cib_axi_halt_ack << MH_DEBUG_REG22_MH_CIB_axi_halt_ack_SHIFT) | \ + (mh_rbbm_busy << MH_DEBUG_REG22_MH_RBBM_busy_SHIFT) | \ + (mh_cib_mh_clk_en_int << MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_SHIFT) | \ + (mh_cib_mmu_clk_en_int << MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_SHIFT) | \ + (mh_cib_tcroq_clk_en_int << MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_SHIFT) | \ + (gat_clk_ena << MH_DEBUG_REG22_GAT_CLK_ENA_SHIFT) | \ + (axi_rdy_ena << MH_DEBUG_REG22_AXI_RDY_ENA_SHIFT) | \ + (rbbm_mh_clk_en_override << MH_DEBUG_REG22_RBBM_MH_clk_en_override_SHIFT) | \ + (cnt_q << MH_DEBUG_REG22_CNT_q_SHIFT) | \ + (tcd_empty_q << MH_DEBUG_REG22_TCD_EMPTY_q_SHIFT) | \ + (tc_roq_empty << MH_DEBUG_REG22_TC_ROQ_EMPTY_SHIFT) | \ + (mh_busy_d << MH_DEBUG_REG22_MH_BUSY_d_SHIFT) | \ + (any_clnt_busy << MH_DEBUG_REG22_ANY_CLNT_BUSY_SHIFT) | \ + (mh_mmu_invalidate_invalidate_all << MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) | \ + (cp_send_q << MH_DEBUG_REG22_CP_SEND_q_SHIFT) | \ + (cp_rtr_q << MH_DEBUG_REG22_CP_RTR_q_SHIFT) | \ + (vgt_send_q << MH_DEBUG_REG22_VGT_SEND_q_SHIFT) | \ + (vgt_rtr_q << MH_DEBUG_REG22_VGT_RTR_q_SHIFT) | \ + (tc_roq_send_q << MH_DEBUG_REG22_TC_ROQ_SEND_q_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG22_TC_ROQ_RTR_q_SHIFT) | \ + (rb_send_q << MH_DEBUG_REG22_RB_SEND_q_SHIFT) | \ + (rb_rtr_q << MH_DEBUG_REG22_RB_RTR_q_SHIFT) | \ + (rdc_valid << MH_DEBUG_REG22_RDC_VALID_SHIFT) | \ + (rdc_rlast << MH_DEBUG_REG22_RDC_RLAST_SHIFT) | \ + (tlbmiss_valid << MH_DEBUG_REG22_TLBMISS_VALID_SHIFT) | \ + (brc_valid << MH_DEBUG_REG22_BRC_VALID_SHIFT)) + +#define MH_DEBUG_REG22_GET_CIB_MH_axi_halt_req(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_CIB_MH_axi_halt_req_MASK) >> MH_DEBUG_REG22_CIB_MH_axi_halt_req_SHIFT) +#define MH_DEBUG_REG22_GET_MH_CIB_axi_halt_ack(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_MH_CIB_axi_halt_ack_MASK) >> MH_DEBUG_REG22_MH_CIB_axi_halt_ack_SHIFT) +#define MH_DEBUG_REG22_GET_MH_RBBM_busy(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_MH_RBBM_busy_MASK) >> MH_DEBUG_REG22_MH_RBBM_busy_SHIFT) +#define MH_DEBUG_REG22_GET_MH_CIB_mh_clk_en_int(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_MASK) >> MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_SHIFT) +#define MH_DEBUG_REG22_GET_MH_CIB_mmu_clk_en_int(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_MASK) >> MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_SHIFT) +#define MH_DEBUG_REG22_GET_MH_CIB_tcroq_clk_en_int(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_MASK) >> MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_SHIFT) +#define MH_DEBUG_REG22_GET_GAT_CLK_ENA(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_GAT_CLK_ENA_MASK) >> MH_DEBUG_REG22_GAT_CLK_ENA_SHIFT) +#define MH_DEBUG_REG22_GET_AXI_RDY_ENA(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_AXI_RDY_ENA_MASK) >> MH_DEBUG_REG22_AXI_RDY_ENA_SHIFT) +#define MH_DEBUG_REG22_GET_RBBM_MH_clk_en_override(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_RBBM_MH_clk_en_override_MASK) >> MH_DEBUG_REG22_RBBM_MH_clk_en_override_SHIFT) +#define MH_DEBUG_REG22_GET_CNT_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_CNT_q_MASK) >> MH_DEBUG_REG22_CNT_q_SHIFT) +#define MH_DEBUG_REG22_GET_TCD_EMPTY_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_TCD_EMPTY_q_MASK) >> MH_DEBUG_REG22_TCD_EMPTY_q_SHIFT) +#define MH_DEBUG_REG22_GET_TC_ROQ_EMPTY(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG22_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG22_GET_MH_BUSY_d(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_MH_BUSY_d_MASK) >> MH_DEBUG_REG22_MH_BUSY_d_SHIFT) +#define MH_DEBUG_REG22_GET_ANY_CLNT_BUSY(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_ANY_CLNT_BUSY_MASK) >> MH_DEBUG_REG22_ANY_CLNT_BUSY_SHIFT) +#define MH_DEBUG_REG22_GET_MH_MMU_INVALIDATE_INVALIDATE_ALL(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) >> MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) +#define MH_DEBUG_REG22_GET_CP_SEND_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_CP_SEND_q_MASK) >> MH_DEBUG_REG22_CP_SEND_q_SHIFT) +#define MH_DEBUG_REG22_GET_CP_RTR_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_CP_RTR_q_MASK) >> MH_DEBUG_REG22_CP_RTR_q_SHIFT) +#define MH_DEBUG_REG22_GET_VGT_SEND_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_VGT_SEND_q_MASK) >> MH_DEBUG_REG22_VGT_SEND_q_SHIFT) +#define MH_DEBUG_REG22_GET_VGT_RTR_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_VGT_RTR_q_MASK) >> MH_DEBUG_REG22_VGT_RTR_q_SHIFT) +#define MH_DEBUG_REG22_GET_TC_ROQ_SEND_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG22_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG22_GET_TC_ROQ_RTR_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG22_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG22_GET_RB_SEND_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_RB_SEND_q_MASK) >> MH_DEBUG_REG22_RB_SEND_q_SHIFT) +#define MH_DEBUG_REG22_GET_RB_RTR_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_RB_RTR_q_MASK) >> MH_DEBUG_REG22_RB_RTR_q_SHIFT) +#define MH_DEBUG_REG22_GET_RDC_VALID(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_RDC_VALID_MASK) >> MH_DEBUG_REG22_RDC_VALID_SHIFT) +#define MH_DEBUG_REG22_GET_RDC_RLAST(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_RDC_RLAST_MASK) >> MH_DEBUG_REG22_RDC_RLAST_SHIFT) +#define MH_DEBUG_REG22_GET_TLBMISS_VALID(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_TLBMISS_VALID_MASK) >> MH_DEBUG_REG22_TLBMISS_VALID_SHIFT) +#define MH_DEBUG_REG22_GET_BRC_VALID(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_BRC_VALID_MASK) >> MH_DEBUG_REG22_BRC_VALID_SHIFT) + +#define MH_DEBUG_REG22_SET_CIB_MH_axi_halt_req(mh_debug_reg22_reg, cib_mh_axi_halt_req) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_CIB_MH_axi_halt_req_MASK) | (cib_mh_axi_halt_req << MH_DEBUG_REG22_CIB_MH_axi_halt_req_SHIFT) +#define MH_DEBUG_REG22_SET_MH_CIB_axi_halt_ack(mh_debug_reg22_reg, mh_cib_axi_halt_ack) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_MH_CIB_axi_halt_ack_MASK) | (mh_cib_axi_halt_ack << MH_DEBUG_REG22_MH_CIB_axi_halt_ack_SHIFT) +#define MH_DEBUG_REG22_SET_MH_RBBM_busy(mh_debug_reg22_reg, mh_rbbm_busy) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_MH_RBBM_busy_MASK) | (mh_rbbm_busy << MH_DEBUG_REG22_MH_RBBM_busy_SHIFT) +#define MH_DEBUG_REG22_SET_MH_CIB_mh_clk_en_int(mh_debug_reg22_reg, mh_cib_mh_clk_en_int) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_MASK) | (mh_cib_mh_clk_en_int << MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_SHIFT) +#define MH_DEBUG_REG22_SET_MH_CIB_mmu_clk_en_int(mh_debug_reg22_reg, mh_cib_mmu_clk_en_int) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_MASK) | (mh_cib_mmu_clk_en_int << MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_SHIFT) +#define MH_DEBUG_REG22_SET_MH_CIB_tcroq_clk_en_int(mh_debug_reg22_reg, mh_cib_tcroq_clk_en_int) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_MASK) | (mh_cib_tcroq_clk_en_int << MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_SHIFT) +#define MH_DEBUG_REG22_SET_GAT_CLK_ENA(mh_debug_reg22_reg, gat_clk_ena) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_GAT_CLK_ENA_MASK) | (gat_clk_ena << MH_DEBUG_REG22_GAT_CLK_ENA_SHIFT) +#define MH_DEBUG_REG22_SET_AXI_RDY_ENA(mh_debug_reg22_reg, axi_rdy_ena) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_AXI_RDY_ENA_MASK) | (axi_rdy_ena << MH_DEBUG_REG22_AXI_RDY_ENA_SHIFT) +#define MH_DEBUG_REG22_SET_RBBM_MH_clk_en_override(mh_debug_reg22_reg, rbbm_mh_clk_en_override) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_RBBM_MH_clk_en_override_MASK) | (rbbm_mh_clk_en_override << MH_DEBUG_REG22_RBBM_MH_clk_en_override_SHIFT) +#define MH_DEBUG_REG22_SET_CNT_q(mh_debug_reg22_reg, cnt_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_CNT_q_MASK) | (cnt_q << MH_DEBUG_REG22_CNT_q_SHIFT) +#define MH_DEBUG_REG22_SET_TCD_EMPTY_q(mh_debug_reg22_reg, tcd_empty_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_TCD_EMPTY_q_MASK) | (tcd_empty_q << MH_DEBUG_REG22_TCD_EMPTY_q_SHIFT) +#define MH_DEBUG_REG22_SET_TC_ROQ_EMPTY(mh_debug_reg22_reg, tc_roq_empty) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG22_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG22_SET_MH_BUSY_d(mh_debug_reg22_reg, mh_busy_d) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_MH_BUSY_d_MASK) | (mh_busy_d << MH_DEBUG_REG22_MH_BUSY_d_SHIFT) +#define MH_DEBUG_REG22_SET_ANY_CLNT_BUSY(mh_debug_reg22_reg, any_clnt_busy) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ANY_CLNT_BUSY_MASK) | (any_clnt_busy << MH_DEBUG_REG22_ANY_CLNT_BUSY_SHIFT) +#define MH_DEBUG_REG22_SET_MH_MMU_INVALIDATE_INVALIDATE_ALL(mh_debug_reg22_reg, mh_mmu_invalidate_invalidate_all) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) | (mh_mmu_invalidate_invalidate_all << MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) +#define MH_DEBUG_REG22_SET_CP_SEND_q(mh_debug_reg22_reg, cp_send_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_CP_SEND_q_MASK) | (cp_send_q << MH_DEBUG_REG22_CP_SEND_q_SHIFT) +#define MH_DEBUG_REG22_SET_CP_RTR_q(mh_debug_reg22_reg, cp_rtr_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_CP_RTR_q_MASK) | (cp_rtr_q << MH_DEBUG_REG22_CP_RTR_q_SHIFT) +#define MH_DEBUG_REG22_SET_VGT_SEND_q(mh_debug_reg22_reg, vgt_send_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_VGT_SEND_q_MASK) | (vgt_send_q << MH_DEBUG_REG22_VGT_SEND_q_SHIFT) +#define MH_DEBUG_REG22_SET_VGT_RTR_q(mh_debug_reg22_reg, vgt_rtr_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_VGT_RTR_q_MASK) | (vgt_rtr_q << MH_DEBUG_REG22_VGT_RTR_q_SHIFT) +#define MH_DEBUG_REG22_SET_TC_ROQ_SEND_q(mh_debug_reg22_reg, tc_roq_send_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG22_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG22_SET_TC_ROQ_RTR_q(mh_debug_reg22_reg, tc_roq_rtr_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG22_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG22_SET_RB_SEND_q(mh_debug_reg22_reg, rb_send_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_RB_SEND_q_MASK) | (rb_send_q << MH_DEBUG_REG22_RB_SEND_q_SHIFT) +#define MH_DEBUG_REG22_SET_RB_RTR_q(mh_debug_reg22_reg, rb_rtr_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_RB_RTR_q_MASK) | (rb_rtr_q << MH_DEBUG_REG22_RB_RTR_q_SHIFT) +#define MH_DEBUG_REG22_SET_RDC_VALID(mh_debug_reg22_reg, rdc_valid) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_RDC_VALID_MASK) | (rdc_valid << MH_DEBUG_REG22_RDC_VALID_SHIFT) +#define MH_DEBUG_REG22_SET_RDC_RLAST(mh_debug_reg22_reg, rdc_rlast) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_RDC_RLAST_MASK) | (rdc_rlast << MH_DEBUG_REG22_RDC_RLAST_SHIFT) +#define MH_DEBUG_REG22_SET_TLBMISS_VALID(mh_debug_reg22_reg, tlbmiss_valid) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_TLBMISS_VALID_MASK) | (tlbmiss_valid << MH_DEBUG_REG22_TLBMISS_VALID_SHIFT) +#define MH_DEBUG_REG22_SET_BRC_VALID(mh_debug_reg22_reg, brc_valid) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_BRC_VALID_MASK) | (brc_valid << MH_DEBUG_REG22_BRC_VALID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg22_t { + unsigned int cib_mh_axi_halt_req : MH_DEBUG_REG22_CIB_MH_axi_halt_req_SIZE; + unsigned int mh_cib_axi_halt_ack : MH_DEBUG_REG22_MH_CIB_axi_halt_ack_SIZE; + unsigned int mh_rbbm_busy : MH_DEBUG_REG22_MH_RBBM_busy_SIZE; + unsigned int mh_cib_mh_clk_en_int : MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_SIZE; + unsigned int mh_cib_mmu_clk_en_int : MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_SIZE; + unsigned int mh_cib_tcroq_clk_en_int : MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_SIZE; + unsigned int gat_clk_ena : MH_DEBUG_REG22_GAT_CLK_ENA_SIZE; + unsigned int axi_rdy_ena : MH_DEBUG_REG22_AXI_RDY_ENA_SIZE; + unsigned int rbbm_mh_clk_en_override : MH_DEBUG_REG22_RBBM_MH_clk_en_override_SIZE; + unsigned int cnt_q : MH_DEBUG_REG22_CNT_q_SIZE; + unsigned int tcd_empty_q : MH_DEBUG_REG22_TCD_EMPTY_q_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG22_TC_ROQ_EMPTY_SIZE; + unsigned int mh_busy_d : MH_DEBUG_REG22_MH_BUSY_d_SIZE; + unsigned int any_clnt_busy : MH_DEBUG_REG22_ANY_CLNT_BUSY_SIZE; + unsigned int mh_mmu_invalidate_invalidate_all : MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE; + unsigned int cp_send_q : MH_DEBUG_REG22_CP_SEND_q_SIZE; + unsigned int cp_rtr_q : MH_DEBUG_REG22_CP_RTR_q_SIZE; + unsigned int vgt_send_q : MH_DEBUG_REG22_VGT_SEND_q_SIZE; + unsigned int vgt_rtr_q : MH_DEBUG_REG22_VGT_RTR_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG22_TC_ROQ_SEND_q_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG22_TC_ROQ_RTR_q_SIZE; + unsigned int rb_send_q : MH_DEBUG_REG22_RB_SEND_q_SIZE; + unsigned int rb_rtr_q : MH_DEBUG_REG22_RB_RTR_q_SIZE; + unsigned int rdc_valid : MH_DEBUG_REG22_RDC_VALID_SIZE; + unsigned int rdc_rlast : MH_DEBUG_REG22_RDC_RLAST_SIZE; + unsigned int tlbmiss_valid : MH_DEBUG_REG22_TLBMISS_VALID_SIZE; + unsigned int brc_valid : MH_DEBUG_REG22_BRC_VALID_SIZE; + } mh_debug_reg22_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg22_t { + unsigned int brc_valid : MH_DEBUG_REG22_BRC_VALID_SIZE; + unsigned int tlbmiss_valid : MH_DEBUG_REG22_TLBMISS_VALID_SIZE; + unsigned int rdc_rlast : MH_DEBUG_REG22_RDC_RLAST_SIZE; + unsigned int rdc_valid : MH_DEBUG_REG22_RDC_VALID_SIZE; + unsigned int rb_rtr_q : MH_DEBUG_REG22_RB_RTR_q_SIZE; + unsigned int rb_send_q : MH_DEBUG_REG22_RB_SEND_q_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG22_TC_ROQ_RTR_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG22_TC_ROQ_SEND_q_SIZE; + unsigned int vgt_rtr_q : MH_DEBUG_REG22_VGT_RTR_q_SIZE; + unsigned int vgt_send_q : MH_DEBUG_REG22_VGT_SEND_q_SIZE; + unsigned int cp_rtr_q : MH_DEBUG_REG22_CP_RTR_q_SIZE; + unsigned int cp_send_q : MH_DEBUG_REG22_CP_SEND_q_SIZE; + unsigned int mh_mmu_invalidate_invalidate_all : MH_DEBUG_REG22_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE; + unsigned int any_clnt_busy : MH_DEBUG_REG22_ANY_CLNT_BUSY_SIZE; + unsigned int mh_busy_d : MH_DEBUG_REG22_MH_BUSY_d_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG22_TC_ROQ_EMPTY_SIZE; + unsigned int tcd_empty_q : MH_DEBUG_REG22_TCD_EMPTY_q_SIZE; + unsigned int cnt_q : MH_DEBUG_REG22_CNT_q_SIZE; + unsigned int rbbm_mh_clk_en_override : MH_DEBUG_REG22_RBBM_MH_clk_en_override_SIZE; + unsigned int axi_rdy_ena : MH_DEBUG_REG22_AXI_RDY_ENA_SIZE; + unsigned int gat_clk_ena : MH_DEBUG_REG22_GAT_CLK_ENA_SIZE; + unsigned int mh_cib_tcroq_clk_en_int : MH_DEBUG_REG22_MH_CIB_tcroq_clk_en_int_SIZE; + unsigned int mh_cib_mmu_clk_en_int : MH_DEBUG_REG22_MH_CIB_mmu_clk_en_int_SIZE; + unsigned int mh_cib_mh_clk_en_int : MH_DEBUG_REG22_MH_CIB_mh_clk_en_int_SIZE; + unsigned int mh_rbbm_busy : MH_DEBUG_REG22_MH_RBBM_busy_SIZE; + unsigned int mh_cib_axi_halt_ack : MH_DEBUG_REG22_MH_CIB_axi_halt_ack_SIZE; + unsigned int cib_mh_axi_halt_req : MH_DEBUG_REG22_CIB_MH_axi_halt_req_SIZE; + } mh_debug_reg22_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg22_t f; +} mh_debug_reg22_u; + + +/* + * MH_DEBUG_REG23 struct + */ + +#define MH_DEBUG_REG23_EFF2_FP_WINNER_SIZE 3 +#define MH_DEBUG_REG23_EFF2_LRU_WINNER_out_SIZE 3 +#define MH_DEBUG_REG23_EFF1_WINNER_SIZE 3 +#define MH_DEBUG_REG23_ARB_WINNER_SIZE 3 +#define MH_DEBUG_REG23_ARB_WINNER_q_SIZE 3 +#define MH_DEBUG_REG23_EFF1_WIN_SIZE 1 +#define MH_DEBUG_REG23_KILL_EFF1_SIZE 1 +#define MH_DEBUG_REG23_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG23_ARB_RTR_q_SIZE 1 +#define MH_DEBUG_REG23_CP_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG23_VGT_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG23_TC_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_SIZE 1 +#define MH_DEBUG_REG23_RB_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG23_ARB_QUAL_SIZE 1 +#define MH_DEBUG_REG23_CP_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG23_VGT_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG23_TC_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG23_RB_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG23_ANY_SAME_ROW_BANK_SIZE 1 +#define MH_DEBUG_REG23_TCD_NEARFULL_q_SIZE 1 +#define MH_DEBUG_REG23_TCHOLD_IP_q_SIZE 1 + +#define MH_DEBUG_REG23_EFF2_FP_WINNER_SHIFT 0 +#define MH_DEBUG_REG23_EFF2_LRU_WINNER_out_SHIFT 3 +#define MH_DEBUG_REG23_EFF1_WINNER_SHIFT 6 +#define MH_DEBUG_REG23_ARB_WINNER_SHIFT 9 +#define MH_DEBUG_REG23_ARB_WINNER_q_SHIFT 12 +#define MH_DEBUG_REG23_EFF1_WIN_SHIFT 15 +#define MH_DEBUG_REG23_KILL_EFF1_SHIFT 16 +#define MH_DEBUG_REG23_ARB_HOLD_SHIFT 17 +#define MH_DEBUG_REG23_ARB_RTR_q_SHIFT 18 +#define MH_DEBUG_REG23_CP_SEND_QUAL_SHIFT 19 +#define MH_DEBUG_REG23_VGT_SEND_QUAL_SHIFT 20 +#define MH_DEBUG_REG23_TC_SEND_QUAL_SHIFT 21 +#define MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_SHIFT 22 +#define MH_DEBUG_REG23_RB_SEND_QUAL_SHIFT 23 +#define MH_DEBUG_REG23_ARB_QUAL_SHIFT 24 +#define MH_DEBUG_REG23_CP_EFF1_REQ_SHIFT 25 +#define MH_DEBUG_REG23_VGT_EFF1_REQ_SHIFT 26 +#define MH_DEBUG_REG23_TC_EFF1_REQ_SHIFT 27 +#define MH_DEBUG_REG23_RB_EFF1_REQ_SHIFT 28 +#define MH_DEBUG_REG23_ANY_SAME_ROW_BANK_SHIFT 29 +#define MH_DEBUG_REG23_TCD_NEARFULL_q_SHIFT 30 +#define MH_DEBUG_REG23_TCHOLD_IP_q_SHIFT 31 + +#define MH_DEBUG_REG23_EFF2_FP_WINNER_MASK 0x00000007 +#define MH_DEBUG_REG23_EFF2_LRU_WINNER_out_MASK 0x00000038 +#define MH_DEBUG_REG23_EFF1_WINNER_MASK 0x000001c0 +#define MH_DEBUG_REG23_ARB_WINNER_MASK 0x00000e00 +#define MH_DEBUG_REG23_ARB_WINNER_q_MASK 0x00007000 +#define MH_DEBUG_REG23_EFF1_WIN_MASK 0x00008000 +#define MH_DEBUG_REG23_KILL_EFF1_MASK 0x00010000 +#define MH_DEBUG_REG23_ARB_HOLD_MASK 0x00020000 +#define MH_DEBUG_REG23_ARB_RTR_q_MASK 0x00040000 +#define MH_DEBUG_REG23_CP_SEND_QUAL_MASK 0x00080000 +#define MH_DEBUG_REG23_VGT_SEND_QUAL_MASK 0x00100000 +#define MH_DEBUG_REG23_TC_SEND_QUAL_MASK 0x00200000 +#define MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_MASK 0x00400000 +#define MH_DEBUG_REG23_RB_SEND_QUAL_MASK 0x00800000 +#define MH_DEBUG_REG23_ARB_QUAL_MASK 0x01000000 +#define MH_DEBUG_REG23_CP_EFF1_REQ_MASK 0x02000000 +#define MH_DEBUG_REG23_VGT_EFF1_REQ_MASK 0x04000000 +#define MH_DEBUG_REG23_TC_EFF1_REQ_MASK 0x08000000 +#define MH_DEBUG_REG23_RB_EFF1_REQ_MASK 0x10000000 +#define MH_DEBUG_REG23_ANY_SAME_ROW_BANK_MASK 0x20000000 +#define MH_DEBUG_REG23_TCD_NEARFULL_q_MASK 0x40000000 +#define MH_DEBUG_REG23_TCHOLD_IP_q_MASK 0x80000000 + +#define MH_DEBUG_REG23_MASK \ + (MH_DEBUG_REG23_EFF2_FP_WINNER_MASK | \ + MH_DEBUG_REG23_EFF2_LRU_WINNER_out_MASK | \ + MH_DEBUG_REG23_EFF1_WINNER_MASK | \ + MH_DEBUG_REG23_ARB_WINNER_MASK | \ + MH_DEBUG_REG23_ARB_WINNER_q_MASK | \ + MH_DEBUG_REG23_EFF1_WIN_MASK | \ + MH_DEBUG_REG23_KILL_EFF1_MASK | \ + MH_DEBUG_REG23_ARB_HOLD_MASK | \ + MH_DEBUG_REG23_ARB_RTR_q_MASK | \ + MH_DEBUG_REG23_CP_SEND_QUAL_MASK | \ + MH_DEBUG_REG23_VGT_SEND_QUAL_MASK | \ + MH_DEBUG_REG23_TC_SEND_QUAL_MASK | \ + MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_MASK | \ + MH_DEBUG_REG23_RB_SEND_QUAL_MASK | \ + MH_DEBUG_REG23_ARB_QUAL_MASK | \ + MH_DEBUG_REG23_CP_EFF1_REQ_MASK | \ + MH_DEBUG_REG23_VGT_EFF1_REQ_MASK | \ + MH_DEBUG_REG23_TC_EFF1_REQ_MASK | \ + MH_DEBUG_REG23_RB_EFF1_REQ_MASK | \ + MH_DEBUG_REG23_ANY_SAME_ROW_BANK_MASK | \ + MH_DEBUG_REG23_TCD_NEARFULL_q_MASK | \ + MH_DEBUG_REG23_TCHOLD_IP_q_MASK) + +#define MH_DEBUG_REG23(eff2_fp_winner, eff2_lru_winner_out, eff1_winner, arb_winner, arb_winner_q, eff1_win, kill_eff1, arb_hold, arb_rtr_q, cp_send_qual, vgt_send_qual, tc_send_qual, tc_send_eff1_qual, rb_send_qual, arb_qual, cp_eff1_req, vgt_eff1_req, tc_eff1_req, rb_eff1_req, any_same_row_bank, tcd_nearfull_q, tchold_ip_q) \ + ((eff2_fp_winner << MH_DEBUG_REG23_EFF2_FP_WINNER_SHIFT) | \ + (eff2_lru_winner_out << MH_DEBUG_REG23_EFF2_LRU_WINNER_out_SHIFT) | \ + (eff1_winner << MH_DEBUG_REG23_EFF1_WINNER_SHIFT) | \ + (arb_winner << MH_DEBUG_REG23_ARB_WINNER_SHIFT) | \ + (arb_winner_q << MH_DEBUG_REG23_ARB_WINNER_q_SHIFT) | \ + (eff1_win << MH_DEBUG_REG23_EFF1_WIN_SHIFT) | \ + (kill_eff1 << MH_DEBUG_REG23_KILL_EFF1_SHIFT) | \ + (arb_hold << MH_DEBUG_REG23_ARB_HOLD_SHIFT) | \ + (arb_rtr_q << MH_DEBUG_REG23_ARB_RTR_q_SHIFT) | \ + (cp_send_qual << MH_DEBUG_REG23_CP_SEND_QUAL_SHIFT) | \ + (vgt_send_qual << MH_DEBUG_REG23_VGT_SEND_QUAL_SHIFT) | \ + (tc_send_qual << MH_DEBUG_REG23_TC_SEND_QUAL_SHIFT) | \ + (tc_send_eff1_qual << MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_SHIFT) | \ + (rb_send_qual << MH_DEBUG_REG23_RB_SEND_QUAL_SHIFT) | \ + (arb_qual << MH_DEBUG_REG23_ARB_QUAL_SHIFT) | \ + (cp_eff1_req << MH_DEBUG_REG23_CP_EFF1_REQ_SHIFT) | \ + (vgt_eff1_req << MH_DEBUG_REG23_VGT_EFF1_REQ_SHIFT) | \ + (tc_eff1_req << MH_DEBUG_REG23_TC_EFF1_REQ_SHIFT) | \ + (rb_eff1_req << MH_DEBUG_REG23_RB_EFF1_REQ_SHIFT) | \ + (any_same_row_bank << MH_DEBUG_REG23_ANY_SAME_ROW_BANK_SHIFT) | \ + (tcd_nearfull_q << MH_DEBUG_REG23_TCD_NEARFULL_q_SHIFT) | \ + (tchold_ip_q << MH_DEBUG_REG23_TCHOLD_IP_q_SHIFT)) + +#define MH_DEBUG_REG23_GET_EFF2_FP_WINNER(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_EFF2_FP_WINNER_MASK) >> MH_DEBUG_REG23_EFF2_FP_WINNER_SHIFT) +#define MH_DEBUG_REG23_GET_EFF2_LRU_WINNER_out(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_EFF2_LRU_WINNER_out_MASK) >> MH_DEBUG_REG23_EFF2_LRU_WINNER_out_SHIFT) +#define MH_DEBUG_REG23_GET_EFF1_WINNER(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_EFF1_WINNER_MASK) >> MH_DEBUG_REG23_EFF1_WINNER_SHIFT) +#define MH_DEBUG_REG23_GET_ARB_WINNER(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_ARB_WINNER_MASK) >> MH_DEBUG_REG23_ARB_WINNER_SHIFT) +#define MH_DEBUG_REG23_GET_ARB_WINNER_q(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_ARB_WINNER_q_MASK) >> MH_DEBUG_REG23_ARB_WINNER_q_SHIFT) +#define MH_DEBUG_REG23_GET_EFF1_WIN(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_EFF1_WIN_MASK) >> MH_DEBUG_REG23_EFF1_WIN_SHIFT) +#define MH_DEBUG_REG23_GET_KILL_EFF1(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_KILL_EFF1_MASK) >> MH_DEBUG_REG23_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG23_GET_ARB_HOLD(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_ARB_HOLD_MASK) >> MH_DEBUG_REG23_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG23_GET_ARB_RTR_q(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_ARB_RTR_q_MASK) >> MH_DEBUG_REG23_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG23_GET_CP_SEND_QUAL(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG23_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG23_GET_VGT_SEND_QUAL(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_VGT_SEND_QUAL_MASK) >> MH_DEBUG_REG23_VGT_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG23_GET_TC_SEND_QUAL(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_TC_SEND_QUAL_MASK) >> MH_DEBUG_REG23_TC_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG23_GET_TC_SEND_EFF1_QUAL(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_MASK) >> MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG23_GET_RB_SEND_QUAL(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG23_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG23_GET_ARB_QUAL(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_ARB_QUAL_MASK) >> MH_DEBUG_REG23_ARB_QUAL_SHIFT) +#define MH_DEBUG_REG23_GET_CP_EFF1_REQ(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_CP_EFF1_REQ_MASK) >> MH_DEBUG_REG23_CP_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG23_GET_VGT_EFF1_REQ(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_VGT_EFF1_REQ_MASK) >> MH_DEBUG_REG23_VGT_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG23_GET_TC_EFF1_REQ(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_TC_EFF1_REQ_MASK) >> MH_DEBUG_REG23_TC_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG23_GET_RB_EFF1_REQ(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_RB_EFF1_REQ_MASK) >> MH_DEBUG_REG23_RB_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG23_GET_ANY_SAME_ROW_BANK(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_ANY_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG23_ANY_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG23_GET_TCD_NEARFULL_q(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG23_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG23_GET_TCHOLD_IP_q(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_TCHOLD_IP_q_MASK) >> MH_DEBUG_REG23_TCHOLD_IP_q_SHIFT) + +#define MH_DEBUG_REG23_SET_EFF2_FP_WINNER(mh_debug_reg23_reg, eff2_fp_winner) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_EFF2_FP_WINNER_MASK) | (eff2_fp_winner << MH_DEBUG_REG23_EFF2_FP_WINNER_SHIFT) +#define MH_DEBUG_REG23_SET_EFF2_LRU_WINNER_out(mh_debug_reg23_reg, eff2_lru_winner_out) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_EFF2_LRU_WINNER_out_MASK) | (eff2_lru_winner_out << MH_DEBUG_REG23_EFF2_LRU_WINNER_out_SHIFT) +#define MH_DEBUG_REG23_SET_EFF1_WINNER(mh_debug_reg23_reg, eff1_winner) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_EFF1_WINNER_MASK) | (eff1_winner << MH_DEBUG_REG23_EFF1_WINNER_SHIFT) +#define MH_DEBUG_REG23_SET_ARB_WINNER(mh_debug_reg23_reg, arb_winner) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG23_ARB_WINNER_SHIFT) +#define MH_DEBUG_REG23_SET_ARB_WINNER_q(mh_debug_reg23_reg, arb_winner_q) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ARB_WINNER_q_MASK) | (arb_winner_q << MH_DEBUG_REG23_ARB_WINNER_q_SHIFT) +#define MH_DEBUG_REG23_SET_EFF1_WIN(mh_debug_reg23_reg, eff1_win) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_EFF1_WIN_MASK) | (eff1_win << MH_DEBUG_REG23_EFF1_WIN_SHIFT) +#define MH_DEBUG_REG23_SET_KILL_EFF1(mh_debug_reg23_reg, kill_eff1) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG23_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG23_SET_ARB_HOLD(mh_debug_reg23_reg, arb_hold) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG23_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG23_SET_ARB_RTR_q(mh_debug_reg23_reg, arb_rtr_q) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG23_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG23_SET_CP_SEND_QUAL(mh_debug_reg23_reg, cp_send_qual) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG23_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG23_SET_VGT_SEND_QUAL(mh_debug_reg23_reg, vgt_send_qual) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_VGT_SEND_QUAL_MASK) | (vgt_send_qual << MH_DEBUG_REG23_VGT_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG23_SET_TC_SEND_QUAL(mh_debug_reg23_reg, tc_send_qual) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_TC_SEND_QUAL_MASK) | (tc_send_qual << MH_DEBUG_REG23_TC_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG23_SET_TC_SEND_EFF1_QUAL(mh_debug_reg23_reg, tc_send_eff1_qual) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_MASK) | (tc_send_eff1_qual << MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG23_SET_RB_SEND_QUAL(mh_debug_reg23_reg, rb_send_qual) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG23_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG23_SET_ARB_QUAL(mh_debug_reg23_reg, arb_qual) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ARB_QUAL_MASK) | (arb_qual << MH_DEBUG_REG23_ARB_QUAL_SHIFT) +#define MH_DEBUG_REG23_SET_CP_EFF1_REQ(mh_debug_reg23_reg, cp_eff1_req) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_CP_EFF1_REQ_MASK) | (cp_eff1_req << MH_DEBUG_REG23_CP_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG23_SET_VGT_EFF1_REQ(mh_debug_reg23_reg, vgt_eff1_req) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_VGT_EFF1_REQ_MASK) | (vgt_eff1_req << MH_DEBUG_REG23_VGT_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG23_SET_TC_EFF1_REQ(mh_debug_reg23_reg, tc_eff1_req) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_TC_EFF1_REQ_MASK) | (tc_eff1_req << MH_DEBUG_REG23_TC_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG23_SET_RB_EFF1_REQ(mh_debug_reg23_reg, rb_eff1_req) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_RB_EFF1_REQ_MASK) | (rb_eff1_req << MH_DEBUG_REG23_RB_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG23_SET_ANY_SAME_ROW_BANK(mh_debug_reg23_reg, any_same_row_bank) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ANY_SAME_ROW_BANK_MASK) | (any_same_row_bank << MH_DEBUG_REG23_ANY_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG23_SET_TCD_NEARFULL_q(mh_debug_reg23_reg, tcd_nearfull_q) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG23_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG23_SET_TCHOLD_IP_q(mh_debug_reg23_reg, tchold_ip_q) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_TCHOLD_IP_q_MASK) | (tchold_ip_q << MH_DEBUG_REG23_TCHOLD_IP_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg23_t { + unsigned int eff2_fp_winner : MH_DEBUG_REG23_EFF2_FP_WINNER_SIZE; + unsigned int eff2_lru_winner_out : MH_DEBUG_REG23_EFF2_LRU_WINNER_out_SIZE; + unsigned int eff1_winner : MH_DEBUG_REG23_EFF1_WINNER_SIZE; + unsigned int arb_winner : MH_DEBUG_REG23_ARB_WINNER_SIZE; + unsigned int arb_winner_q : MH_DEBUG_REG23_ARB_WINNER_q_SIZE; + unsigned int eff1_win : MH_DEBUG_REG23_EFF1_WIN_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG23_KILL_EFF1_SIZE; + unsigned int arb_hold : MH_DEBUG_REG23_ARB_HOLD_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG23_ARB_RTR_q_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG23_CP_SEND_QUAL_SIZE; + unsigned int vgt_send_qual : MH_DEBUG_REG23_VGT_SEND_QUAL_SIZE; + unsigned int tc_send_qual : MH_DEBUG_REG23_TC_SEND_QUAL_SIZE; + unsigned int tc_send_eff1_qual : MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG23_RB_SEND_QUAL_SIZE; + unsigned int arb_qual : MH_DEBUG_REG23_ARB_QUAL_SIZE; + unsigned int cp_eff1_req : MH_DEBUG_REG23_CP_EFF1_REQ_SIZE; + unsigned int vgt_eff1_req : MH_DEBUG_REG23_VGT_EFF1_REQ_SIZE; + unsigned int tc_eff1_req : MH_DEBUG_REG23_TC_EFF1_REQ_SIZE; + unsigned int rb_eff1_req : MH_DEBUG_REG23_RB_EFF1_REQ_SIZE; + unsigned int any_same_row_bank : MH_DEBUG_REG23_ANY_SAME_ROW_BANK_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG23_TCD_NEARFULL_q_SIZE; + unsigned int tchold_ip_q : MH_DEBUG_REG23_TCHOLD_IP_q_SIZE; + } mh_debug_reg23_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg23_t { + unsigned int tchold_ip_q : MH_DEBUG_REG23_TCHOLD_IP_q_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG23_TCD_NEARFULL_q_SIZE; + unsigned int any_same_row_bank : MH_DEBUG_REG23_ANY_SAME_ROW_BANK_SIZE; + unsigned int rb_eff1_req : MH_DEBUG_REG23_RB_EFF1_REQ_SIZE; + unsigned int tc_eff1_req : MH_DEBUG_REG23_TC_EFF1_REQ_SIZE; + unsigned int vgt_eff1_req : MH_DEBUG_REG23_VGT_EFF1_REQ_SIZE; + unsigned int cp_eff1_req : MH_DEBUG_REG23_CP_EFF1_REQ_SIZE; + unsigned int arb_qual : MH_DEBUG_REG23_ARB_QUAL_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG23_RB_SEND_QUAL_SIZE; + unsigned int tc_send_eff1_qual : MH_DEBUG_REG23_TC_SEND_EFF1_QUAL_SIZE; + unsigned int tc_send_qual : MH_DEBUG_REG23_TC_SEND_QUAL_SIZE; + unsigned int vgt_send_qual : MH_DEBUG_REG23_VGT_SEND_QUAL_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG23_CP_SEND_QUAL_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG23_ARB_RTR_q_SIZE; + unsigned int arb_hold : MH_DEBUG_REG23_ARB_HOLD_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG23_KILL_EFF1_SIZE; + unsigned int eff1_win : MH_DEBUG_REG23_EFF1_WIN_SIZE; + unsigned int arb_winner_q : MH_DEBUG_REG23_ARB_WINNER_q_SIZE; + unsigned int arb_winner : MH_DEBUG_REG23_ARB_WINNER_SIZE; + unsigned int eff1_winner : MH_DEBUG_REG23_EFF1_WINNER_SIZE; + unsigned int eff2_lru_winner_out : MH_DEBUG_REG23_EFF2_LRU_WINNER_out_SIZE; + unsigned int eff2_fp_winner : MH_DEBUG_REG23_EFF2_FP_WINNER_SIZE; + } mh_debug_reg23_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg23_t f; +} mh_debug_reg23_u; + + +/* + * MH_DEBUG_REG24 struct + */ + +#define MH_DEBUG_REG24_EFF1_WINNER_SIZE 3 +#define MH_DEBUG_REG24_ARB_WINNER_SIZE 3 +#define MH_DEBUG_REG24_CP_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG24_VGT_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG24_TC_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_SIZE 1 +#define MH_DEBUG_REG24_RB_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG24_ARB_QUAL_SIZE 1 +#define MH_DEBUG_REG24_CP_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG24_VGT_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG24_TC_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG24_RB_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG24_EFF1_WIN_SIZE 1 +#define MH_DEBUG_REG24_KILL_EFF1_SIZE 1 +#define MH_DEBUG_REG24_TCD_NEARFULL_q_SIZE 1 +#define MH_DEBUG_REG24_TC_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG24_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG24_ARB_RTR_q_SIZE 1 +#define MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_SIZE 10 + +#define MH_DEBUG_REG24_EFF1_WINNER_SHIFT 0 +#define MH_DEBUG_REG24_ARB_WINNER_SHIFT 3 +#define MH_DEBUG_REG24_CP_SEND_QUAL_SHIFT 6 +#define MH_DEBUG_REG24_VGT_SEND_QUAL_SHIFT 7 +#define MH_DEBUG_REG24_TC_SEND_QUAL_SHIFT 8 +#define MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_SHIFT 9 +#define MH_DEBUG_REG24_RB_SEND_QUAL_SHIFT 10 +#define MH_DEBUG_REG24_ARB_QUAL_SHIFT 11 +#define MH_DEBUG_REG24_CP_EFF1_REQ_SHIFT 12 +#define MH_DEBUG_REG24_VGT_EFF1_REQ_SHIFT 13 +#define MH_DEBUG_REG24_TC_EFF1_REQ_SHIFT 14 +#define MH_DEBUG_REG24_RB_EFF1_REQ_SHIFT 15 +#define MH_DEBUG_REG24_EFF1_WIN_SHIFT 16 +#define MH_DEBUG_REG24_KILL_EFF1_SHIFT 17 +#define MH_DEBUG_REG24_TCD_NEARFULL_q_SHIFT 18 +#define MH_DEBUG_REG24_TC_ARB_HOLD_SHIFT 19 +#define MH_DEBUG_REG24_ARB_HOLD_SHIFT 20 +#define MH_DEBUG_REG24_ARB_RTR_q_SHIFT 21 +#define MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_SHIFT 22 + +#define MH_DEBUG_REG24_EFF1_WINNER_MASK 0x00000007 +#define MH_DEBUG_REG24_ARB_WINNER_MASK 0x00000038 +#define MH_DEBUG_REG24_CP_SEND_QUAL_MASK 0x00000040 +#define MH_DEBUG_REG24_VGT_SEND_QUAL_MASK 0x00000080 +#define MH_DEBUG_REG24_TC_SEND_QUAL_MASK 0x00000100 +#define MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_MASK 0x00000200 +#define MH_DEBUG_REG24_RB_SEND_QUAL_MASK 0x00000400 +#define MH_DEBUG_REG24_ARB_QUAL_MASK 0x00000800 +#define MH_DEBUG_REG24_CP_EFF1_REQ_MASK 0x00001000 +#define MH_DEBUG_REG24_VGT_EFF1_REQ_MASK 0x00002000 +#define MH_DEBUG_REG24_TC_EFF1_REQ_MASK 0x00004000 +#define MH_DEBUG_REG24_RB_EFF1_REQ_MASK 0x00008000 +#define MH_DEBUG_REG24_EFF1_WIN_MASK 0x00010000 +#define MH_DEBUG_REG24_KILL_EFF1_MASK 0x00020000 +#define MH_DEBUG_REG24_TCD_NEARFULL_q_MASK 0x00040000 +#define MH_DEBUG_REG24_TC_ARB_HOLD_MASK 0x00080000 +#define MH_DEBUG_REG24_ARB_HOLD_MASK 0x00100000 +#define MH_DEBUG_REG24_ARB_RTR_q_MASK 0x00200000 +#define MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_MASK 0xffc00000 + +#define MH_DEBUG_REG24_MASK \ + (MH_DEBUG_REG24_EFF1_WINNER_MASK | \ + MH_DEBUG_REG24_ARB_WINNER_MASK | \ + MH_DEBUG_REG24_CP_SEND_QUAL_MASK | \ + MH_DEBUG_REG24_VGT_SEND_QUAL_MASK | \ + MH_DEBUG_REG24_TC_SEND_QUAL_MASK | \ + MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_MASK | \ + MH_DEBUG_REG24_RB_SEND_QUAL_MASK | \ + MH_DEBUG_REG24_ARB_QUAL_MASK | \ + MH_DEBUG_REG24_CP_EFF1_REQ_MASK | \ + MH_DEBUG_REG24_VGT_EFF1_REQ_MASK | \ + MH_DEBUG_REG24_TC_EFF1_REQ_MASK | \ + MH_DEBUG_REG24_RB_EFF1_REQ_MASK | \ + MH_DEBUG_REG24_EFF1_WIN_MASK | \ + MH_DEBUG_REG24_KILL_EFF1_MASK | \ + MH_DEBUG_REG24_TCD_NEARFULL_q_MASK | \ + MH_DEBUG_REG24_TC_ARB_HOLD_MASK | \ + MH_DEBUG_REG24_ARB_HOLD_MASK | \ + MH_DEBUG_REG24_ARB_RTR_q_MASK | \ + MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_MASK) + +#define MH_DEBUG_REG24(eff1_winner, arb_winner, cp_send_qual, vgt_send_qual, tc_send_qual, tc_send_eff1_qual, rb_send_qual, arb_qual, cp_eff1_req, vgt_eff1_req, tc_eff1_req, rb_eff1_req, eff1_win, kill_eff1, tcd_nearfull_q, tc_arb_hold, arb_hold, arb_rtr_q, same_page_limit_count_q) \ + ((eff1_winner << MH_DEBUG_REG24_EFF1_WINNER_SHIFT) | \ + (arb_winner << MH_DEBUG_REG24_ARB_WINNER_SHIFT) | \ + (cp_send_qual << MH_DEBUG_REG24_CP_SEND_QUAL_SHIFT) | \ + (vgt_send_qual << MH_DEBUG_REG24_VGT_SEND_QUAL_SHIFT) | \ + (tc_send_qual << MH_DEBUG_REG24_TC_SEND_QUAL_SHIFT) | \ + (tc_send_eff1_qual << MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_SHIFT) | \ + (rb_send_qual << MH_DEBUG_REG24_RB_SEND_QUAL_SHIFT) | \ + (arb_qual << MH_DEBUG_REG24_ARB_QUAL_SHIFT) | \ + (cp_eff1_req << MH_DEBUG_REG24_CP_EFF1_REQ_SHIFT) | \ + (vgt_eff1_req << MH_DEBUG_REG24_VGT_EFF1_REQ_SHIFT) | \ + (tc_eff1_req << MH_DEBUG_REG24_TC_EFF1_REQ_SHIFT) | \ + (rb_eff1_req << MH_DEBUG_REG24_RB_EFF1_REQ_SHIFT) | \ + (eff1_win << MH_DEBUG_REG24_EFF1_WIN_SHIFT) | \ + (kill_eff1 << MH_DEBUG_REG24_KILL_EFF1_SHIFT) | \ + (tcd_nearfull_q << MH_DEBUG_REG24_TCD_NEARFULL_q_SHIFT) | \ + (tc_arb_hold << MH_DEBUG_REG24_TC_ARB_HOLD_SHIFT) | \ + (arb_hold << MH_DEBUG_REG24_ARB_HOLD_SHIFT) | \ + (arb_rtr_q << MH_DEBUG_REG24_ARB_RTR_q_SHIFT) | \ + (same_page_limit_count_q << MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_SHIFT)) + +#define MH_DEBUG_REG24_GET_EFF1_WINNER(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_EFF1_WINNER_MASK) >> MH_DEBUG_REG24_EFF1_WINNER_SHIFT) +#define MH_DEBUG_REG24_GET_ARB_WINNER(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_ARB_WINNER_MASK) >> MH_DEBUG_REG24_ARB_WINNER_SHIFT) +#define MH_DEBUG_REG24_GET_CP_SEND_QUAL(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG24_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG24_GET_VGT_SEND_QUAL(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_VGT_SEND_QUAL_MASK) >> MH_DEBUG_REG24_VGT_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG24_GET_TC_SEND_QUAL(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_TC_SEND_QUAL_MASK) >> MH_DEBUG_REG24_TC_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG24_GET_TC_SEND_EFF1_QUAL(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_MASK) >> MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG24_GET_RB_SEND_QUAL(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG24_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG24_GET_ARB_QUAL(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_ARB_QUAL_MASK) >> MH_DEBUG_REG24_ARB_QUAL_SHIFT) +#define MH_DEBUG_REG24_GET_CP_EFF1_REQ(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_CP_EFF1_REQ_MASK) >> MH_DEBUG_REG24_CP_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG24_GET_VGT_EFF1_REQ(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_VGT_EFF1_REQ_MASK) >> MH_DEBUG_REG24_VGT_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG24_GET_TC_EFF1_REQ(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_TC_EFF1_REQ_MASK) >> MH_DEBUG_REG24_TC_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG24_GET_RB_EFF1_REQ(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_RB_EFF1_REQ_MASK) >> MH_DEBUG_REG24_RB_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG24_GET_EFF1_WIN(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_EFF1_WIN_MASK) >> MH_DEBUG_REG24_EFF1_WIN_SHIFT) +#define MH_DEBUG_REG24_GET_KILL_EFF1(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_KILL_EFF1_MASK) >> MH_DEBUG_REG24_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG24_GET_TCD_NEARFULL_q(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG24_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG24_GET_TC_ARB_HOLD(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_TC_ARB_HOLD_MASK) >> MH_DEBUG_REG24_TC_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG24_GET_ARB_HOLD(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_ARB_HOLD_MASK) >> MH_DEBUG_REG24_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG24_GET_ARB_RTR_q(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_ARB_RTR_q_MASK) >> MH_DEBUG_REG24_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG24_GET_SAME_PAGE_LIMIT_COUNT_q(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_MASK) >> MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_SHIFT) + +#define MH_DEBUG_REG24_SET_EFF1_WINNER(mh_debug_reg24_reg, eff1_winner) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_EFF1_WINNER_MASK) | (eff1_winner << MH_DEBUG_REG24_EFF1_WINNER_SHIFT) +#define MH_DEBUG_REG24_SET_ARB_WINNER(mh_debug_reg24_reg, arb_winner) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG24_ARB_WINNER_SHIFT) +#define MH_DEBUG_REG24_SET_CP_SEND_QUAL(mh_debug_reg24_reg, cp_send_qual) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG24_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG24_SET_VGT_SEND_QUAL(mh_debug_reg24_reg, vgt_send_qual) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_VGT_SEND_QUAL_MASK) | (vgt_send_qual << MH_DEBUG_REG24_VGT_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG24_SET_TC_SEND_QUAL(mh_debug_reg24_reg, tc_send_qual) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_TC_SEND_QUAL_MASK) | (tc_send_qual << MH_DEBUG_REG24_TC_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG24_SET_TC_SEND_EFF1_QUAL(mh_debug_reg24_reg, tc_send_eff1_qual) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_MASK) | (tc_send_eff1_qual << MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG24_SET_RB_SEND_QUAL(mh_debug_reg24_reg, rb_send_qual) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG24_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG24_SET_ARB_QUAL(mh_debug_reg24_reg, arb_qual) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_ARB_QUAL_MASK) | (arb_qual << MH_DEBUG_REG24_ARB_QUAL_SHIFT) +#define MH_DEBUG_REG24_SET_CP_EFF1_REQ(mh_debug_reg24_reg, cp_eff1_req) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_CP_EFF1_REQ_MASK) | (cp_eff1_req << MH_DEBUG_REG24_CP_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG24_SET_VGT_EFF1_REQ(mh_debug_reg24_reg, vgt_eff1_req) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_VGT_EFF1_REQ_MASK) | (vgt_eff1_req << MH_DEBUG_REG24_VGT_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG24_SET_TC_EFF1_REQ(mh_debug_reg24_reg, tc_eff1_req) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_TC_EFF1_REQ_MASK) | (tc_eff1_req << MH_DEBUG_REG24_TC_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG24_SET_RB_EFF1_REQ(mh_debug_reg24_reg, rb_eff1_req) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_RB_EFF1_REQ_MASK) | (rb_eff1_req << MH_DEBUG_REG24_RB_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG24_SET_EFF1_WIN(mh_debug_reg24_reg, eff1_win) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_EFF1_WIN_MASK) | (eff1_win << MH_DEBUG_REG24_EFF1_WIN_SHIFT) +#define MH_DEBUG_REG24_SET_KILL_EFF1(mh_debug_reg24_reg, kill_eff1) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG24_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG24_SET_TCD_NEARFULL_q(mh_debug_reg24_reg, tcd_nearfull_q) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG24_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG24_SET_TC_ARB_HOLD(mh_debug_reg24_reg, tc_arb_hold) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_TC_ARB_HOLD_MASK) | (tc_arb_hold << MH_DEBUG_REG24_TC_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG24_SET_ARB_HOLD(mh_debug_reg24_reg, arb_hold) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG24_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG24_SET_ARB_RTR_q(mh_debug_reg24_reg, arb_rtr_q) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG24_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG24_SET_SAME_PAGE_LIMIT_COUNT_q(mh_debug_reg24_reg, same_page_limit_count_q) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_MASK) | (same_page_limit_count_q << MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg24_t { + unsigned int eff1_winner : MH_DEBUG_REG24_EFF1_WINNER_SIZE; + unsigned int arb_winner : MH_DEBUG_REG24_ARB_WINNER_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG24_CP_SEND_QUAL_SIZE; + unsigned int vgt_send_qual : MH_DEBUG_REG24_VGT_SEND_QUAL_SIZE; + unsigned int tc_send_qual : MH_DEBUG_REG24_TC_SEND_QUAL_SIZE; + unsigned int tc_send_eff1_qual : MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG24_RB_SEND_QUAL_SIZE; + unsigned int arb_qual : MH_DEBUG_REG24_ARB_QUAL_SIZE; + unsigned int cp_eff1_req : MH_DEBUG_REG24_CP_EFF1_REQ_SIZE; + unsigned int vgt_eff1_req : MH_DEBUG_REG24_VGT_EFF1_REQ_SIZE; + unsigned int tc_eff1_req : MH_DEBUG_REG24_TC_EFF1_REQ_SIZE; + unsigned int rb_eff1_req : MH_DEBUG_REG24_RB_EFF1_REQ_SIZE; + unsigned int eff1_win : MH_DEBUG_REG24_EFF1_WIN_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG24_KILL_EFF1_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG24_TCD_NEARFULL_q_SIZE; + unsigned int tc_arb_hold : MH_DEBUG_REG24_TC_ARB_HOLD_SIZE; + unsigned int arb_hold : MH_DEBUG_REG24_ARB_HOLD_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG24_ARB_RTR_q_SIZE; + unsigned int same_page_limit_count_q : MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_SIZE; + } mh_debug_reg24_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg24_t { + unsigned int same_page_limit_count_q : MH_DEBUG_REG24_SAME_PAGE_LIMIT_COUNT_q_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG24_ARB_RTR_q_SIZE; + unsigned int arb_hold : MH_DEBUG_REG24_ARB_HOLD_SIZE; + unsigned int tc_arb_hold : MH_DEBUG_REG24_TC_ARB_HOLD_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG24_TCD_NEARFULL_q_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG24_KILL_EFF1_SIZE; + unsigned int eff1_win : MH_DEBUG_REG24_EFF1_WIN_SIZE; + unsigned int rb_eff1_req : MH_DEBUG_REG24_RB_EFF1_REQ_SIZE; + unsigned int tc_eff1_req : MH_DEBUG_REG24_TC_EFF1_REQ_SIZE; + unsigned int vgt_eff1_req : MH_DEBUG_REG24_VGT_EFF1_REQ_SIZE; + unsigned int cp_eff1_req : MH_DEBUG_REG24_CP_EFF1_REQ_SIZE; + unsigned int arb_qual : MH_DEBUG_REG24_ARB_QUAL_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG24_RB_SEND_QUAL_SIZE; + unsigned int tc_send_eff1_qual : MH_DEBUG_REG24_TC_SEND_EFF1_QUAL_SIZE; + unsigned int tc_send_qual : MH_DEBUG_REG24_TC_SEND_QUAL_SIZE; + unsigned int vgt_send_qual : MH_DEBUG_REG24_VGT_SEND_QUAL_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG24_CP_SEND_QUAL_SIZE; + unsigned int arb_winner : MH_DEBUG_REG24_ARB_WINNER_SIZE; + unsigned int eff1_winner : MH_DEBUG_REG24_EFF1_WINNER_SIZE; + } mh_debug_reg24_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg24_t f; +} mh_debug_reg24_u; + + +/* + * MH_DEBUG_REG25 struct + */ + +#define MH_DEBUG_REG25_EFF2_LRU_WINNER_out_SIZE 3 +#define MH_DEBUG_REG25_ARB_WINNER_SIZE 3 +#define MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_SIZE 3 +#define MH_DEBUG_REG25_LEAST_RECENT_d_SIZE 3 +#define MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_SIZE 1 +#define MH_DEBUG_REG25_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG25_ARB_RTR_q_SIZE 1 +#define MH_DEBUG_REG25_EFF1_WIN_SIZE 1 +#define MH_DEBUG_REG25_CLNT_REQ_SIZE 4 +#define MH_DEBUG_REG25_RECENT_d_0_SIZE 3 +#define MH_DEBUG_REG25_RECENT_d_1_SIZE 3 +#define MH_DEBUG_REG25_RECENT_d_2_SIZE 3 +#define MH_DEBUG_REG25_RECENT_d_3_SIZE 3 + +#define MH_DEBUG_REG25_EFF2_LRU_WINNER_out_SHIFT 0 +#define MH_DEBUG_REG25_ARB_WINNER_SHIFT 3 +#define MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_SHIFT 6 +#define MH_DEBUG_REG25_LEAST_RECENT_d_SHIFT 9 +#define MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_SHIFT 12 +#define MH_DEBUG_REG25_ARB_HOLD_SHIFT 13 +#define MH_DEBUG_REG25_ARB_RTR_q_SHIFT 14 +#define MH_DEBUG_REG25_EFF1_WIN_SHIFT 15 +#define MH_DEBUG_REG25_CLNT_REQ_SHIFT 16 +#define MH_DEBUG_REG25_RECENT_d_0_SHIFT 20 +#define MH_DEBUG_REG25_RECENT_d_1_SHIFT 23 +#define MH_DEBUG_REG25_RECENT_d_2_SHIFT 26 +#define MH_DEBUG_REG25_RECENT_d_3_SHIFT 29 + +#define MH_DEBUG_REG25_EFF2_LRU_WINNER_out_MASK 0x00000007 +#define MH_DEBUG_REG25_ARB_WINNER_MASK 0x00000038 +#define MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_MASK 0x000001c0 +#define MH_DEBUG_REG25_LEAST_RECENT_d_MASK 0x00000e00 +#define MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_MASK 0x00001000 +#define MH_DEBUG_REG25_ARB_HOLD_MASK 0x00002000 +#define MH_DEBUG_REG25_ARB_RTR_q_MASK 0x00004000 +#define MH_DEBUG_REG25_EFF1_WIN_MASK 0x00008000 +#define MH_DEBUG_REG25_CLNT_REQ_MASK 0x000f0000 +#define MH_DEBUG_REG25_RECENT_d_0_MASK 0x00700000 +#define MH_DEBUG_REG25_RECENT_d_1_MASK 0x03800000 +#define MH_DEBUG_REG25_RECENT_d_2_MASK 0x1c000000 +#define MH_DEBUG_REG25_RECENT_d_3_MASK 0xe0000000 + +#define MH_DEBUG_REG25_MASK \ + (MH_DEBUG_REG25_EFF2_LRU_WINNER_out_MASK | \ + MH_DEBUG_REG25_ARB_WINNER_MASK | \ + MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_MASK | \ + MH_DEBUG_REG25_LEAST_RECENT_d_MASK | \ + MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_MASK | \ + MH_DEBUG_REG25_ARB_HOLD_MASK | \ + MH_DEBUG_REG25_ARB_RTR_q_MASK | \ + MH_DEBUG_REG25_EFF1_WIN_MASK | \ + MH_DEBUG_REG25_CLNT_REQ_MASK | \ + MH_DEBUG_REG25_RECENT_d_0_MASK | \ + MH_DEBUG_REG25_RECENT_d_1_MASK | \ + MH_DEBUG_REG25_RECENT_d_2_MASK | \ + MH_DEBUG_REG25_RECENT_d_3_MASK) + +#define MH_DEBUG_REG25(eff2_lru_winner_out, arb_winner, least_recent_index_d, least_recent_d, update_recent_stack_d, arb_hold, arb_rtr_q, eff1_win, clnt_req, recent_d_0, recent_d_1, recent_d_2, recent_d_3) \ + ((eff2_lru_winner_out << MH_DEBUG_REG25_EFF2_LRU_WINNER_out_SHIFT) | \ + (arb_winner << MH_DEBUG_REG25_ARB_WINNER_SHIFT) | \ + (least_recent_index_d << MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_SHIFT) | \ + (least_recent_d << MH_DEBUG_REG25_LEAST_RECENT_d_SHIFT) | \ + (update_recent_stack_d << MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_SHIFT) | \ + (arb_hold << MH_DEBUG_REG25_ARB_HOLD_SHIFT) | \ + (arb_rtr_q << MH_DEBUG_REG25_ARB_RTR_q_SHIFT) | \ + (eff1_win << MH_DEBUG_REG25_EFF1_WIN_SHIFT) | \ + (clnt_req << MH_DEBUG_REG25_CLNT_REQ_SHIFT) | \ + (recent_d_0 << MH_DEBUG_REG25_RECENT_d_0_SHIFT) | \ + (recent_d_1 << MH_DEBUG_REG25_RECENT_d_1_SHIFT) | \ + (recent_d_2 << MH_DEBUG_REG25_RECENT_d_2_SHIFT) | \ + (recent_d_3 << MH_DEBUG_REG25_RECENT_d_3_SHIFT)) + +#define MH_DEBUG_REG25_GET_EFF2_LRU_WINNER_out(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_EFF2_LRU_WINNER_out_MASK) >> MH_DEBUG_REG25_EFF2_LRU_WINNER_out_SHIFT) +#define MH_DEBUG_REG25_GET_ARB_WINNER(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_ARB_WINNER_MASK) >> MH_DEBUG_REG25_ARB_WINNER_SHIFT) +#define MH_DEBUG_REG25_GET_LEAST_RECENT_INDEX_d(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_MASK) >> MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_SHIFT) +#define MH_DEBUG_REG25_GET_LEAST_RECENT_d(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_LEAST_RECENT_d_MASK) >> MH_DEBUG_REG25_LEAST_RECENT_d_SHIFT) +#define MH_DEBUG_REG25_GET_UPDATE_RECENT_STACK_d(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_MASK) >> MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_SHIFT) +#define MH_DEBUG_REG25_GET_ARB_HOLD(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_ARB_HOLD_MASK) >> MH_DEBUG_REG25_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG25_GET_ARB_RTR_q(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_ARB_RTR_q_MASK) >> MH_DEBUG_REG25_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG25_GET_EFF1_WIN(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_EFF1_WIN_MASK) >> MH_DEBUG_REG25_EFF1_WIN_SHIFT) +#define MH_DEBUG_REG25_GET_CLNT_REQ(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_CLNT_REQ_MASK) >> MH_DEBUG_REG25_CLNT_REQ_SHIFT) +#define MH_DEBUG_REG25_GET_RECENT_d_0(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_RECENT_d_0_MASK) >> MH_DEBUG_REG25_RECENT_d_0_SHIFT) +#define MH_DEBUG_REG25_GET_RECENT_d_1(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_RECENT_d_1_MASK) >> MH_DEBUG_REG25_RECENT_d_1_SHIFT) +#define MH_DEBUG_REG25_GET_RECENT_d_2(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_RECENT_d_2_MASK) >> MH_DEBUG_REG25_RECENT_d_2_SHIFT) +#define MH_DEBUG_REG25_GET_RECENT_d_3(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_RECENT_d_3_MASK) >> MH_DEBUG_REG25_RECENT_d_3_SHIFT) + +#define MH_DEBUG_REG25_SET_EFF2_LRU_WINNER_out(mh_debug_reg25_reg, eff2_lru_winner_out) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_EFF2_LRU_WINNER_out_MASK) | (eff2_lru_winner_out << MH_DEBUG_REG25_EFF2_LRU_WINNER_out_SHIFT) +#define MH_DEBUG_REG25_SET_ARB_WINNER(mh_debug_reg25_reg, arb_winner) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG25_ARB_WINNER_SHIFT) +#define MH_DEBUG_REG25_SET_LEAST_RECENT_INDEX_d(mh_debug_reg25_reg, least_recent_index_d) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_MASK) | (least_recent_index_d << MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_SHIFT) +#define MH_DEBUG_REG25_SET_LEAST_RECENT_d(mh_debug_reg25_reg, least_recent_d) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_LEAST_RECENT_d_MASK) | (least_recent_d << MH_DEBUG_REG25_LEAST_RECENT_d_SHIFT) +#define MH_DEBUG_REG25_SET_UPDATE_RECENT_STACK_d(mh_debug_reg25_reg, update_recent_stack_d) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_MASK) | (update_recent_stack_d << MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_SHIFT) +#define MH_DEBUG_REG25_SET_ARB_HOLD(mh_debug_reg25_reg, arb_hold) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG25_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG25_SET_ARB_RTR_q(mh_debug_reg25_reg, arb_rtr_q) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG25_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG25_SET_EFF1_WIN(mh_debug_reg25_reg, eff1_win) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_EFF1_WIN_MASK) | (eff1_win << MH_DEBUG_REG25_EFF1_WIN_SHIFT) +#define MH_DEBUG_REG25_SET_CLNT_REQ(mh_debug_reg25_reg, clnt_req) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_CLNT_REQ_MASK) | (clnt_req << MH_DEBUG_REG25_CLNT_REQ_SHIFT) +#define MH_DEBUG_REG25_SET_RECENT_d_0(mh_debug_reg25_reg, recent_d_0) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_RECENT_d_0_MASK) | (recent_d_0 << MH_DEBUG_REG25_RECENT_d_0_SHIFT) +#define MH_DEBUG_REG25_SET_RECENT_d_1(mh_debug_reg25_reg, recent_d_1) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_RECENT_d_1_MASK) | (recent_d_1 << MH_DEBUG_REG25_RECENT_d_1_SHIFT) +#define MH_DEBUG_REG25_SET_RECENT_d_2(mh_debug_reg25_reg, recent_d_2) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_RECENT_d_2_MASK) | (recent_d_2 << MH_DEBUG_REG25_RECENT_d_2_SHIFT) +#define MH_DEBUG_REG25_SET_RECENT_d_3(mh_debug_reg25_reg, recent_d_3) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_RECENT_d_3_MASK) | (recent_d_3 << MH_DEBUG_REG25_RECENT_d_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg25_t { + unsigned int eff2_lru_winner_out : MH_DEBUG_REG25_EFF2_LRU_WINNER_out_SIZE; + unsigned int arb_winner : MH_DEBUG_REG25_ARB_WINNER_SIZE; + unsigned int least_recent_index_d : MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_SIZE; + unsigned int least_recent_d : MH_DEBUG_REG25_LEAST_RECENT_d_SIZE; + unsigned int update_recent_stack_d : MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_SIZE; + unsigned int arb_hold : MH_DEBUG_REG25_ARB_HOLD_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG25_ARB_RTR_q_SIZE; + unsigned int eff1_win : MH_DEBUG_REG25_EFF1_WIN_SIZE; + unsigned int clnt_req : MH_DEBUG_REG25_CLNT_REQ_SIZE; + unsigned int recent_d_0 : MH_DEBUG_REG25_RECENT_d_0_SIZE; + unsigned int recent_d_1 : MH_DEBUG_REG25_RECENT_d_1_SIZE; + unsigned int recent_d_2 : MH_DEBUG_REG25_RECENT_d_2_SIZE; + unsigned int recent_d_3 : MH_DEBUG_REG25_RECENT_d_3_SIZE; + } mh_debug_reg25_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg25_t { + unsigned int recent_d_3 : MH_DEBUG_REG25_RECENT_d_3_SIZE; + unsigned int recent_d_2 : MH_DEBUG_REG25_RECENT_d_2_SIZE; + unsigned int recent_d_1 : MH_DEBUG_REG25_RECENT_d_1_SIZE; + unsigned int recent_d_0 : MH_DEBUG_REG25_RECENT_d_0_SIZE; + unsigned int clnt_req : MH_DEBUG_REG25_CLNT_REQ_SIZE; + unsigned int eff1_win : MH_DEBUG_REG25_EFF1_WIN_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG25_ARB_RTR_q_SIZE; + unsigned int arb_hold : MH_DEBUG_REG25_ARB_HOLD_SIZE; + unsigned int update_recent_stack_d : MH_DEBUG_REG25_UPDATE_RECENT_STACK_d_SIZE; + unsigned int least_recent_d : MH_DEBUG_REG25_LEAST_RECENT_d_SIZE; + unsigned int least_recent_index_d : MH_DEBUG_REG25_LEAST_RECENT_INDEX_d_SIZE; + unsigned int arb_winner : MH_DEBUG_REG25_ARB_WINNER_SIZE; + unsigned int eff2_lru_winner_out : MH_DEBUG_REG25_EFF2_LRU_WINNER_out_SIZE; + } mh_debug_reg25_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg25_t f; +} mh_debug_reg25_u; + + +/* + * MH_DEBUG_REG26 struct + */ + +#define MH_DEBUG_REG26_TC_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_SIZE 1 +#define MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_SIZE 1 +#define MH_DEBUG_REG26_TCD_NEARFULL_q_SIZE 1 +#define MH_DEBUG_REG26_TCHOLD_IP_q_SIZE 1 +#define MH_DEBUG_REG26_TCHOLD_CNT_q_SIZE 3 +#define MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE 1 +#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE 1 +#define MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE 1 +#define MH_DEBUG_REG26_TC_MH_written_SIZE 1 +#define MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_SIZE 7 +#define MH_DEBUG_REG26_WBURST_ACTIVE_SIZE 1 +#define MH_DEBUG_REG26_WLAST_q_SIZE 1 +#define MH_DEBUG_REG26_WBURST_IP_q_SIZE 1 +#define MH_DEBUG_REG26_WBURST_CNT_q_SIZE 3 +#define MH_DEBUG_REG26_CP_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG26_CP_MH_write_SIZE 1 +#define MH_DEBUG_REG26_RB_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG26_ARB_WINNER_SIZE 3 + +#define MH_DEBUG_REG26_TC_ARB_HOLD_SHIFT 0 +#define MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_SHIFT 1 +#define MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_SHIFT 2 +#define MH_DEBUG_REG26_TCD_NEARFULL_q_SHIFT 3 +#define MH_DEBUG_REG26_TCHOLD_IP_q_SHIFT 4 +#define MH_DEBUG_REG26_TCHOLD_CNT_q_SHIFT 5 +#define MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT 8 +#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT 9 +#define MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT 10 +#define MH_DEBUG_REG26_TC_MH_written_SHIFT 11 +#define MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_SHIFT 12 +#define MH_DEBUG_REG26_WBURST_ACTIVE_SHIFT 19 +#define MH_DEBUG_REG26_WLAST_q_SHIFT 20 +#define MH_DEBUG_REG26_WBURST_IP_q_SHIFT 21 +#define MH_DEBUG_REG26_WBURST_CNT_q_SHIFT 22 +#define MH_DEBUG_REG26_CP_SEND_QUAL_SHIFT 25 +#define MH_DEBUG_REG26_CP_MH_write_SHIFT 26 +#define MH_DEBUG_REG26_RB_SEND_QUAL_SHIFT 27 +#define MH_DEBUG_REG26_ARB_WINNER_SHIFT 28 + +#define MH_DEBUG_REG26_TC_ARB_HOLD_MASK 0x00000001 +#define MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_MASK 0x00000002 +#define MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_MASK 0x00000004 +#define MH_DEBUG_REG26_TCD_NEARFULL_q_MASK 0x00000008 +#define MH_DEBUG_REG26_TCHOLD_IP_q_MASK 0x00000010 +#define MH_DEBUG_REG26_TCHOLD_CNT_q_MASK 0x000000e0 +#define MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00000100 +#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK 0x00000200 +#define MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK 0x00000400 +#define MH_DEBUG_REG26_TC_MH_written_MASK 0x00000800 +#define MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_MASK 0x0007f000 +#define MH_DEBUG_REG26_WBURST_ACTIVE_MASK 0x00080000 +#define MH_DEBUG_REG26_WLAST_q_MASK 0x00100000 +#define MH_DEBUG_REG26_WBURST_IP_q_MASK 0x00200000 +#define MH_DEBUG_REG26_WBURST_CNT_q_MASK 0x01c00000 +#define MH_DEBUG_REG26_CP_SEND_QUAL_MASK 0x02000000 +#define MH_DEBUG_REG26_CP_MH_write_MASK 0x04000000 +#define MH_DEBUG_REG26_RB_SEND_QUAL_MASK 0x08000000 +#define MH_DEBUG_REG26_ARB_WINNER_MASK 0x70000000 + +#define MH_DEBUG_REG26_MASK \ + (MH_DEBUG_REG26_TC_ARB_HOLD_MASK | \ + MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_MASK | \ + MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_MASK | \ + MH_DEBUG_REG26_TCD_NEARFULL_q_MASK | \ + MH_DEBUG_REG26_TCHOLD_IP_q_MASK | \ + MH_DEBUG_REG26_TCHOLD_CNT_q_MASK | \ + MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK | \ + MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK | \ + MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK | \ + MH_DEBUG_REG26_TC_MH_written_MASK | \ + MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_MASK | \ + MH_DEBUG_REG26_WBURST_ACTIVE_MASK | \ + MH_DEBUG_REG26_WLAST_q_MASK | \ + MH_DEBUG_REG26_WBURST_IP_q_MASK | \ + MH_DEBUG_REG26_WBURST_CNT_q_MASK | \ + MH_DEBUG_REG26_CP_SEND_QUAL_MASK | \ + MH_DEBUG_REG26_CP_MH_write_MASK | \ + MH_DEBUG_REG26_RB_SEND_QUAL_MASK | \ + MH_DEBUG_REG26_ARB_WINNER_MASK) + +#define MH_DEBUG_REG26(tc_arb_hold, tc_noroq_same_row_bank, tc_roq_same_row_bank, tcd_nearfull_q, tchold_ip_q, tchold_cnt_q, mh_arbiter_config_tc_reorder_enable, tc_roq_rtr_dbg_q, tc_roq_send_q, tc_mh_written, tcd_fullness_cnt_q, wburst_active, wlast_q, wburst_ip_q, wburst_cnt_q, cp_send_qual, cp_mh_write, rb_send_qual, arb_winner) \ + ((tc_arb_hold << MH_DEBUG_REG26_TC_ARB_HOLD_SHIFT) | \ + (tc_noroq_same_row_bank << MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_SHIFT) | \ + (tc_roq_same_row_bank << MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_SHIFT) | \ + (tcd_nearfull_q << MH_DEBUG_REG26_TCD_NEARFULL_q_SHIFT) | \ + (tchold_ip_q << MH_DEBUG_REG26_TCHOLD_IP_q_SHIFT) | \ + (tchold_cnt_q << MH_DEBUG_REG26_TCHOLD_CNT_q_SHIFT) | \ + (mh_arbiter_config_tc_reorder_enable << MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) | \ + (tc_roq_rtr_dbg_q << MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT) | \ + (tc_roq_send_q << MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT) | \ + (tc_mh_written << MH_DEBUG_REG26_TC_MH_written_SHIFT) | \ + (tcd_fullness_cnt_q << MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_SHIFT) | \ + (wburst_active << MH_DEBUG_REG26_WBURST_ACTIVE_SHIFT) | \ + (wlast_q << MH_DEBUG_REG26_WLAST_q_SHIFT) | \ + (wburst_ip_q << MH_DEBUG_REG26_WBURST_IP_q_SHIFT) | \ + (wburst_cnt_q << MH_DEBUG_REG26_WBURST_CNT_q_SHIFT) | \ + (cp_send_qual << MH_DEBUG_REG26_CP_SEND_QUAL_SHIFT) | \ + (cp_mh_write << MH_DEBUG_REG26_CP_MH_write_SHIFT) | \ + (rb_send_qual << MH_DEBUG_REG26_RB_SEND_QUAL_SHIFT) | \ + (arb_winner << MH_DEBUG_REG26_ARB_WINNER_SHIFT)) + +#define MH_DEBUG_REG26_GET_TC_ARB_HOLD(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ARB_HOLD_MASK) >> MH_DEBUG_REG26_TC_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG26_GET_TC_NOROQ_SAME_ROW_BANK(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG26_GET_TC_ROQ_SAME_ROW_BANK(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG26_GET_TCD_NEARFULL_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG26_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG26_GET_TCHOLD_IP_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TCHOLD_IP_q_MASK) >> MH_DEBUG_REG26_TCHOLD_IP_q_SHIFT) +#define MH_DEBUG_REG26_GET_TCHOLD_CNT_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TCHOLD_CNT_q_MASK) >> MH_DEBUG_REG26_TCHOLD_CNT_q_SHIFT) +#define MH_DEBUG_REG26_GET_MH_ARBITER_CONFIG_TC_REORDER_ENABLE(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) >> MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) +#define MH_DEBUG_REG26_GET_TC_ROQ_RTR_DBG_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK) >> MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT) +#define MH_DEBUG_REG26_GET_TC_ROQ_SEND_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG26_GET_TC_MH_written(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TC_MH_written_MASK) >> MH_DEBUG_REG26_TC_MH_written_SHIFT) +#define MH_DEBUG_REG26_GET_TCD_FULLNESS_CNT_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_MASK) >> MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_SHIFT) +#define MH_DEBUG_REG26_GET_WBURST_ACTIVE(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_WBURST_ACTIVE_MASK) >> MH_DEBUG_REG26_WBURST_ACTIVE_SHIFT) +#define MH_DEBUG_REG26_GET_WLAST_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_WLAST_q_MASK) >> MH_DEBUG_REG26_WLAST_q_SHIFT) +#define MH_DEBUG_REG26_GET_WBURST_IP_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_WBURST_IP_q_MASK) >> MH_DEBUG_REG26_WBURST_IP_q_SHIFT) +#define MH_DEBUG_REG26_GET_WBURST_CNT_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_WBURST_CNT_q_MASK) >> MH_DEBUG_REG26_WBURST_CNT_q_SHIFT) +#define MH_DEBUG_REG26_GET_CP_SEND_QUAL(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG26_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG26_GET_CP_MH_write(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_CP_MH_write_MASK) >> MH_DEBUG_REG26_CP_MH_write_SHIFT) +#define MH_DEBUG_REG26_GET_RB_SEND_QUAL(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG26_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG26_GET_ARB_WINNER(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_ARB_WINNER_MASK) >> MH_DEBUG_REG26_ARB_WINNER_SHIFT) + +#define MH_DEBUG_REG26_SET_TC_ARB_HOLD(mh_debug_reg26_reg, tc_arb_hold) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ARB_HOLD_MASK) | (tc_arb_hold << MH_DEBUG_REG26_TC_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG26_SET_TC_NOROQ_SAME_ROW_BANK(mh_debug_reg26_reg, tc_noroq_same_row_bank) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_MASK) | (tc_noroq_same_row_bank << MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG26_SET_TC_ROQ_SAME_ROW_BANK(mh_debug_reg26_reg, tc_roq_same_row_bank) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_MASK) | (tc_roq_same_row_bank << MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG26_SET_TCD_NEARFULL_q(mh_debug_reg26_reg, tcd_nearfull_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG26_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG26_SET_TCHOLD_IP_q(mh_debug_reg26_reg, tchold_ip_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TCHOLD_IP_q_MASK) | (tchold_ip_q << MH_DEBUG_REG26_TCHOLD_IP_q_SHIFT) +#define MH_DEBUG_REG26_SET_TCHOLD_CNT_q(mh_debug_reg26_reg, tchold_cnt_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TCHOLD_CNT_q_MASK) | (tchold_cnt_q << MH_DEBUG_REG26_TCHOLD_CNT_q_SHIFT) +#define MH_DEBUG_REG26_SET_MH_ARBITER_CONFIG_TC_REORDER_ENABLE(mh_debug_reg26_reg, mh_arbiter_config_tc_reorder_enable) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) | (mh_arbiter_config_tc_reorder_enable << MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) +#define MH_DEBUG_REG26_SET_TC_ROQ_RTR_DBG_q(mh_debug_reg26_reg, tc_roq_rtr_dbg_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK) | (tc_roq_rtr_dbg_q << MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT) +#define MH_DEBUG_REG26_SET_TC_ROQ_SEND_q(mh_debug_reg26_reg, tc_roq_send_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG26_SET_TC_MH_written(mh_debug_reg26_reg, tc_mh_written) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG26_TC_MH_written_SHIFT) +#define MH_DEBUG_REG26_SET_TCD_FULLNESS_CNT_q(mh_debug_reg26_reg, tcd_fullness_cnt_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_MASK) | (tcd_fullness_cnt_q << MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_SHIFT) +#define MH_DEBUG_REG26_SET_WBURST_ACTIVE(mh_debug_reg26_reg, wburst_active) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_WBURST_ACTIVE_MASK) | (wburst_active << MH_DEBUG_REG26_WBURST_ACTIVE_SHIFT) +#define MH_DEBUG_REG26_SET_WLAST_q(mh_debug_reg26_reg, wlast_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG26_WLAST_q_SHIFT) +#define MH_DEBUG_REG26_SET_WBURST_IP_q(mh_debug_reg26_reg, wburst_ip_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_WBURST_IP_q_MASK) | (wburst_ip_q << MH_DEBUG_REG26_WBURST_IP_q_SHIFT) +#define MH_DEBUG_REG26_SET_WBURST_CNT_q(mh_debug_reg26_reg, wburst_cnt_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_WBURST_CNT_q_MASK) | (wburst_cnt_q << MH_DEBUG_REG26_WBURST_CNT_q_SHIFT) +#define MH_DEBUG_REG26_SET_CP_SEND_QUAL(mh_debug_reg26_reg, cp_send_qual) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG26_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG26_SET_CP_MH_write(mh_debug_reg26_reg, cp_mh_write) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CP_MH_write_MASK) | (cp_mh_write << MH_DEBUG_REG26_CP_MH_write_SHIFT) +#define MH_DEBUG_REG26_SET_RB_SEND_QUAL(mh_debug_reg26_reg, rb_send_qual) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG26_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG26_SET_ARB_WINNER(mh_debug_reg26_reg, arb_winner) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG26_ARB_WINNER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg26_t { + unsigned int tc_arb_hold : MH_DEBUG_REG26_TC_ARB_HOLD_SIZE; + unsigned int tc_noroq_same_row_bank : MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_SIZE; + unsigned int tc_roq_same_row_bank : MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG26_TCD_NEARFULL_q_SIZE; + unsigned int tchold_ip_q : MH_DEBUG_REG26_TCHOLD_IP_q_SIZE; + unsigned int tchold_cnt_q : MH_DEBUG_REG26_TCHOLD_CNT_q_SIZE; + unsigned int mh_arbiter_config_tc_reorder_enable : MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE; + unsigned int tc_roq_rtr_dbg_q : MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG26_TC_MH_written_SIZE; + unsigned int tcd_fullness_cnt_q : MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_SIZE; + unsigned int wburst_active : MH_DEBUG_REG26_WBURST_ACTIVE_SIZE; + unsigned int wlast_q : MH_DEBUG_REG26_WLAST_q_SIZE; + unsigned int wburst_ip_q : MH_DEBUG_REG26_WBURST_IP_q_SIZE; + unsigned int wburst_cnt_q : MH_DEBUG_REG26_WBURST_CNT_q_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG26_CP_SEND_QUAL_SIZE; + unsigned int cp_mh_write : MH_DEBUG_REG26_CP_MH_write_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG26_RB_SEND_QUAL_SIZE; + unsigned int arb_winner : MH_DEBUG_REG26_ARB_WINNER_SIZE; + unsigned int : 1; + } mh_debug_reg26_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg26_t { + unsigned int : 1; + unsigned int arb_winner : MH_DEBUG_REG26_ARB_WINNER_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG26_RB_SEND_QUAL_SIZE; + unsigned int cp_mh_write : MH_DEBUG_REG26_CP_MH_write_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG26_CP_SEND_QUAL_SIZE; + unsigned int wburst_cnt_q : MH_DEBUG_REG26_WBURST_CNT_q_SIZE; + unsigned int wburst_ip_q : MH_DEBUG_REG26_WBURST_IP_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG26_WLAST_q_SIZE; + unsigned int wburst_active : MH_DEBUG_REG26_WBURST_ACTIVE_SIZE; + unsigned int tcd_fullness_cnt_q : MH_DEBUG_REG26_TCD_FULLNESS_CNT_q_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG26_TC_MH_written_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE; + unsigned int tc_roq_rtr_dbg_q : MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE; + unsigned int mh_arbiter_config_tc_reorder_enable : MH_DEBUG_REG26_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE; + unsigned int tchold_cnt_q : MH_DEBUG_REG26_TCHOLD_CNT_q_SIZE; + unsigned int tchold_ip_q : MH_DEBUG_REG26_TCHOLD_IP_q_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG26_TCD_NEARFULL_q_SIZE; + unsigned int tc_roq_same_row_bank : MH_DEBUG_REG26_TC_ROQ_SAME_ROW_BANK_SIZE; + unsigned int tc_noroq_same_row_bank : MH_DEBUG_REG26_TC_NOROQ_SAME_ROW_BANK_SIZE; + unsigned int tc_arb_hold : MH_DEBUG_REG26_TC_ARB_HOLD_SIZE; + } mh_debug_reg26_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg26_t f; +} mh_debug_reg26_u; + + +/* + * MH_DEBUG_REG27 struct + */ + +#define MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_SIZE 26 +#define MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3 + +#define MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_SHIFT 0 +#define MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 26 + +#define MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_MASK 0x03ffffff +#define MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x1c000000 + +#define MH_DEBUG_REG27_MASK \ + (MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_MASK | \ + MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) + +#define MH_DEBUG_REG27(rf_arbiter_config_q, mh_clnt_axi_id_reuse_mmur_id) \ + ((rf_arbiter_config_q << MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_SHIFT) | \ + (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)) + +#define MH_DEBUG_REG27_GET_RF_ARBITER_CONFIG_q(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_MASK) >> MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_SHIFT) +#define MH_DEBUG_REG27_GET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) + +#define MH_DEBUG_REG27_SET_RF_ARBITER_CONFIG_q(mh_debug_reg27_reg, rf_arbiter_config_q) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_MASK) | (rf_arbiter_config_q << MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_SHIFT) +#define MH_DEBUG_REG27_SET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg27_reg, mh_clnt_axi_id_reuse_mmur_id) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg27_t { + unsigned int rf_arbiter_config_q : MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_SIZE; + unsigned int mh_clnt_axi_id_reuse_mmur_id : MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int : 3; + } mh_debug_reg27_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg27_t { + unsigned int : 3; + unsigned int mh_clnt_axi_id_reuse_mmur_id : MH_DEBUG_REG27_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int rf_arbiter_config_q : MH_DEBUG_REG27_RF_ARBITER_CONFIG_q_SIZE; + } mh_debug_reg27_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg27_t f; +} mh_debug_reg27_u; + + +/* + * MH_DEBUG_REG28 struct + */ + +#define MH_DEBUG_REG28_SAME_ROW_BANK_q_SIZE 8 +#define MH_DEBUG_REG28_ROQ_MARK_q_SIZE 8 +#define MH_DEBUG_REG28_ROQ_VALID_q_SIZE 8 +#define MH_DEBUG_REG28_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG28_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG28_KILL_EFF1_SIZE 1 +#define MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_SIZE 1 +#define MH_DEBUG_REG28_ANY_SAME_ROW_BANK_SIZE 1 +#define MH_DEBUG_REG28_TC_EFF1_QUAL_SIZE 1 +#define MH_DEBUG_REG28_TC_ROQ_EMPTY_SIZE 1 +#define MH_DEBUG_REG28_TC_ROQ_FULL_SIZE 1 + +#define MH_DEBUG_REG28_SAME_ROW_BANK_q_SHIFT 0 +#define MH_DEBUG_REG28_ROQ_MARK_q_SHIFT 8 +#define MH_DEBUG_REG28_ROQ_VALID_q_SHIFT 16 +#define MH_DEBUG_REG28_TC_MH_send_SHIFT 24 +#define MH_DEBUG_REG28_TC_ROQ_RTR_q_SHIFT 25 +#define MH_DEBUG_REG28_KILL_EFF1_SHIFT 26 +#define MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT 27 +#define MH_DEBUG_REG28_ANY_SAME_ROW_BANK_SHIFT 28 +#define MH_DEBUG_REG28_TC_EFF1_QUAL_SHIFT 29 +#define MH_DEBUG_REG28_TC_ROQ_EMPTY_SHIFT 30 +#define MH_DEBUG_REG28_TC_ROQ_FULL_SHIFT 31 + +#define MH_DEBUG_REG28_SAME_ROW_BANK_q_MASK 0x000000ff +#define MH_DEBUG_REG28_ROQ_MARK_q_MASK 0x0000ff00 +#define MH_DEBUG_REG28_ROQ_VALID_q_MASK 0x00ff0000 +#define MH_DEBUG_REG28_TC_MH_send_MASK 0x01000000 +#define MH_DEBUG_REG28_TC_ROQ_RTR_q_MASK 0x02000000 +#define MH_DEBUG_REG28_KILL_EFF1_MASK 0x04000000 +#define MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000 +#define MH_DEBUG_REG28_ANY_SAME_ROW_BANK_MASK 0x10000000 +#define MH_DEBUG_REG28_TC_EFF1_QUAL_MASK 0x20000000 +#define MH_DEBUG_REG28_TC_ROQ_EMPTY_MASK 0x40000000 +#define MH_DEBUG_REG28_TC_ROQ_FULL_MASK 0x80000000 + +#define MH_DEBUG_REG28_MASK \ + (MH_DEBUG_REG28_SAME_ROW_BANK_q_MASK | \ + MH_DEBUG_REG28_ROQ_MARK_q_MASK | \ + MH_DEBUG_REG28_ROQ_VALID_q_MASK | \ + MH_DEBUG_REG28_TC_MH_send_MASK | \ + MH_DEBUG_REG28_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG28_KILL_EFF1_MASK | \ + MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_MASK | \ + MH_DEBUG_REG28_ANY_SAME_ROW_BANK_MASK | \ + MH_DEBUG_REG28_TC_EFF1_QUAL_MASK | \ + MH_DEBUG_REG28_TC_ROQ_EMPTY_MASK | \ + MH_DEBUG_REG28_TC_ROQ_FULL_MASK) + +#define MH_DEBUG_REG28(same_row_bank_q, roq_mark_q, roq_valid_q, tc_mh_send, tc_roq_rtr_q, kill_eff1, tc_roq_same_row_bank_sel, any_same_row_bank, tc_eff1_qual, tc_roq_empty, tc_roq_full) \ + ((same_row_bank_q << MH_DEBUG_REG28_SAME_ROW_BANK_q_SHIFT) | \ + (roq_mark_q << MH_DEBUG_REG28_ROQ_MARK_q_SHIFT) | \ + (roq_valid_q << MH_DEBUG_REG28_ROQ_VALID_q_SHIFT) | \ + (tc_mh_send << MH_DEBUG_REG28_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG28_TC_ROQ_RTR_q_SHIFT) | \ + (kill_eff1 << MH_DEBUG_REG28_KILL_EFF1_SHIFT) | \ + (tc_roq_same_row_bank_sel << MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) | \ + (any_same_row_bank << MH_DEBUG_REG28_ANY_SAME_ROW_BANK_SHIFT) | \ + (tc_eff1_qual << MH_DEBUG_REG28_TC_EFF1_QUAL_SHIFT) | \ + (tc_roq_empty << MH_DEBUG_REG28_TC_ROQ_EMPTY_SHIFT) | \ + (tc_roq_full << MH_DEBUG_REG28_TC_ROQ_FULL_SHIFT)) + +#define MH_DEBUG_REG28_GET_SAME_ROW_BANK_q(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_SAME_ROW_BANK_q_MASK) >> MH_DEBUG_REG28_SAME_ROW_BANK_q_SHIFT) +#define MH_DEBUG_REG28_GET_ROQ_MARK_q(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_ROQ_MARK_q_MASK) >> MH_DEBUG_REG28_ROQ_MARK_q_SHIFT) +#define MH_DEBUG_REG28_GET_ROQ_VALID_q(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_ROQ_VALID_q_MASK) >> MH_DEBUG_REG28_ROQ_VALID_q_SHIFT) +#define MH_DEBUG_REG28_GET_TC_MH_send(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TC_MH_send_MASK) >> MH_DEBUG_REG28_TC_MH_send_SHIFT) +#define MH_DEBUG_REG28_GET_TC_ROQ_RTR_q(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG28_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG28_GET_KILL_EFF1(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_KILL_EFF1_MASK) >> MH_DEBUG_REG28_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG28_GET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_MASK) >> MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) +#define MH_DEBUG_REG28_GET_ANY_SAME_ROW_BANK(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_ANY_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG28_ANY_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG28_GET_TC_EFF1_QUAL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TC_EFF1_QUAL_MASK) >> MH_DEBUG_REG28_TC_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG28_GET_TC_ROQ_EMPTY(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG28_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG28_GET_TC_ROQ_FULL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TC_ROQ_FULL_MASK) >> MH_DEBUG_REG28_TC_ROQ_FULL_SHIFT) + +#define MH_DEBUG_REG28_SET_SAME_ROW_BANK_q(mh_debug_reg28_reg, same_row_bank_q) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_SAME_ROW_BANK_q_MASK) | (same_row_bank_q << MH_DEBUG_REG28_SAME_ROW_BANK_q_SHIFT) +#define MH_DEBUG_REG28_SET_ROQ_MARK_q(mh_debug_reg28_reg, roq_mark_q) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ROQ_MARK_q_MASK) | (roq_mark_q << MH_DEBUG_REG28_ROQ_MARK_q_SHIFT) +#define MH_DEBUG_REG28_SET_ROQ_VALID_q(mh_debug_reg28_reg, roq_valid_q) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ROQ_VALID_q_MASK) | (roq_valid_q << MH_DEBUG_REG28_ROQ_VALID_q_SHIFT) +#define MH_DEBUG_REG28_SET_TC_MH_send(mh_debug_reg28_reg, tc_mh_send) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG28_TC_MH_send_SHIFT) +#define MH_DEBUG_REG28_SET_TC_ROQ_RTR_q(mh_debug_reg28_reg, tc_roq_rtr_q) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG28_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG28_SET_KILL_EFF1(mh_debug_reg28_reg, kill_eff1) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG28_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG28_SET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg28_reg, tc_roq_same_row_bank_sel) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_MASK) | (tc_roq_same_row_bank_sel << MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) +#define MH_DEBUG_REG28_SET_ANY_SAME_ROW_BANK(mh_debug_reg28_reg, any_same_row_bank) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ANY_SAME_ROW_BANK_MASK) | (any_same_row_bank << MH_DEBUG_REG28_ANY_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG28_SET_TC_EFF1_QUAL(mh_debug_reg28_reg, tc_eff1_qual) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_EFF1_QUAL_MASK) | (tc_eff1_qual << MH_DEBUG_REG28_TC_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG28_SET_TC_ROQ_EMPTY(mh_debug_reg28_reg, tc_roq_empty) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG28_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG28_SET_TC_ROQ_FULL(mh_debug_reg28_reg, tc_roq_full) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_ROQ_FULL_MASK) | (tc_roq_full << MH_DEBUG_REG28_TC_ROQ_FULL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg28_t { + unsigned int same_row_bank_q : MH_DEBUG_REG28_SAME_ROW_BANK_q_SIZE; + unsigned int roq_mark_q : MH_DEBUG_REG28_ROQ_MARK_q_SIZE; + unsigned int roq_valid_q : MH_DEBUG_REG28_ROQ_VALID_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG28_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG28_TC_ROQ_RTR_q_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG28_KILL_EFF1_SIZE; + unsigned int tc_roq_same_row_bank_sel : MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_SIZE; + unsigned int any_same_row_bank : MH_DEBUG_REG28_ANY_SAME_ROW_BANK_SIZE; + unsigned int tc_eff1_qual : MH_DEBUG_REG28_TC_EFF1_QUAL_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG28_TC_ROQ_EMPTY_SIZE; + unsigned int tc_roq_full : MH_DEBUG_REG28_TC_ROQ_FULL_SIZE; + } mh_debug_reg28_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg28_t { + unsigned int tc_roq_full : MH_DEBUG_REG28_TC_ROQ_FULL_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG28_TC_ROQ_EMPTY_SIZE; + unsigned int tc_eff1_qual : MH_DEBUG_REG28_TC_EFF1_QUAL_SIZE; + unsigned int any_same_row_bank : MH_DEBUG_REG28_ANY_SAME_ROW_BANK_SIZE; + unsigned int tc_roq_same_row_bank_sel : MH_DEBUG_REG28_TC_ROQ_SAME_ROW_BANK_SEL_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG28_KILL_EFF1_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG28_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG28_TC_MH_send_SIZE; + unsigned int roq_valid_q : MH_DEBUG_REG28_ROQ_VALID_q_SIZE; + unsigned int roq_mark_q : MH_DEBUG_REG28_ROQ_MARK_q_SIZE; + unsigned int same_row_bank_q : MH_DEBUG_REG28_SAME_ROW_BANK_q_SIZE; + } mh_debug_reg28_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg28_t f; +} mh_debug_reg28_u; + + +/* + * MH_DEBUG_REG29 struct + */ + +#define MH_DEBUG_REG29_SAME_ROW_BANK_q_SIZE 8 +#define MH_DEBUG_REG29_ROQ_MARK_d_SIZE 8 +#define MH_DEBUG_REG29_ROQ_VALID_d_SIZE 8 +#define MH_DEBUG_REG29_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG29_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG29_KILL_EFF1_SIZE 1 +#define MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_SIZE 1 +#define MH_DEBUG_REG29_ANY_SAME_ROW_BANK_SIZE 1 +#define MH_DEBUG_REG29_TC_EFF1_QUAL_SIZE 1 +#define MH_DEBUG_REG29_TC_ROQ_EMPTY_SIZE 1 +#define MH_DEBUG_REG29_TC_ROQ_FULL_SIZE 1 + +#define MH_DEBUG_REG29_SAME_ROW_BANK_q_SHIFT 0 +#define MH_DEBUG_REG29_ROQ_MARK_d_SHIFT 8 +#define MH_DEBUG_REG29_ROQ_VALID_d_SHIFT 16 +#define MH_DEBUG_REG29_TC_MH_send_SHIFT 24 +#define MH_DEBUG_REG29_TC_ROQ_RTR_q_SHIFT 25 +#define MH_DEBUG_REG29_KILL_EFF1_SHIFT 26 +#define MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT 27 +#define MH_DEBUG_REG29_ANY_SAME_ROW_BANK_SHIFT 28 +#define MH_DEBUG_REG29_TC_EFF1_QUAL_SHIFT 29 +#define MH_DEBUG_REG29_TC_ROQ_EMPTY_SHIFT 30 +#define MH_DEBUG_REG29_TC_ROQ_FULL_SHIFT 31 + +#define MH_DEBUG_REG29_SAME_ROW_BANK_q_MASK 0x000000ff +#define MH_DEBUG_REG29_ROQ_MARK_d_MASK 0x0000ff00 +#define MH_DEBUG_REG29_ROQ_VALID_d_MASK 0x00ff0000 +#define MH_DEBUG_REG29_TC_MH_send_MASK 0x01000000 +#define MH_DEBUG_REG29_TC_ROQ_RTR_q_MASK 0x02000000 +#define MH_DEBUG_REG29_KILL_EFF1_MASK 0x04000000 +#define MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000 +#define MH_DEBUG_REG29_ANY_SAME_ROW_BANK_MASK 0x10000000 +#define MH_DEBUG_REG29_TC_EFF1_QUAL_MASK 0x20000000 +#define MH_DEBUG_REG29_TC_ROQ_EMPTY_MASK 0x40000000 +#define MH_DEBUG_REG29_TC_ROQ_FULL_MASK 0x80000000 + +#define MH_DEBUG_REG29_MASK \ + (MH_DEBUG_REG29_SAME_ROW_BANK_q_MASK | \ + MH_DEBUG_REG29_ROQ_MARK_d_MASK | \ + MH_DEBUG_REG29_ROQ_VALID_d_MASK | \ + MH_DEBUG_REG29_TC_MH_send_MASK | \ + MH_DEBUG_REG29_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG29_KILL_EFF1_MASK | \ + MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_MASK | \ + MH_DEBUG_REG29_ANY_SAME_ROW_BANK_MASK | \ + MH_DEBUG_REG29_TC_EFF1_QUAL_MASK | \ + MH_DEBUG_REG29_TC_ROQ_EMPTY_MASK | \ + MH_DEBUG_REG29_TC_ROQ_FULL_MASK) + +#define MH_DEBUG_REG29(same_row_bank_q, roq_mark_d, roq_valid_d, tc_mh_send, tc_roq_rtr_q, kill_eff1, tc_roq_same_row_bank_sel, any_same_row_bank, tc_eff1_qual, tc_roq_empty, tc_roq_full) \ + ((same_row_bank_q << MH_DEBUG_REG29_SAME_ROW_BANK_q_SHIFT) | \ + (roq_mark_d << MH_DEBUG_REG29_ROQ_MARK_d_SHIFT) | \ + (roq_valid_d << MH_DEBUG_REG29_ROQ_VALID_d_SHIFT) | \ + (tc_mh_send << MH_DEBUG_REG29_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG29_TC_ROQ_RTR_q_SHIFT) | \ + (kill_eff1 << MH_DEBUG_REG29_KILL_EFF1_SHIFT) | \ + (tc_roq_same_row_bank_sel << MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) | \ + (any_same_row_bank << MH_DEBUG_REG29_ANY_SAME_ROW_BANK_SHIFT) | \ + (tc_eff1_qual << MH_DEBUG_REG29_TC_EFF1_QUAL_SHIFT) | \ + (tc_roq_empty << MH_DEBUG_REG29_TC_ROQ_EMPTY_SHIFT) | \ + (tc_roq_full << MH_DEBUG_REG29_TC_ROQ_FULL_SHIFT)) + +#define MH_DEBUG_REG29_GET_SAME_ROW_BANK_q(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_SAME_ROW_BANK_q_MASK) >> MH_DEBUG_REG29_SAME_ROW_BANK_q_SHIFT) +#define MH_DEBUG_REG29_GET_ROQ_MARK_d(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_ROQ_MARK_d_MASK) >> MH_DEBUG_REG29_ROQ_MARK_d_SHIFT) +#define MH_DEBUG_REG29_GET_ROQ_VALID_d(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_ROQ_VALID_d_MASK) >> MH_DEBUG_REG29_ROQ_VALID_d_SHIFT) +#define MH_DEBUG_REG29_GET_TC_MH_send(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_TC_MH_send_MASK) >> MH_DEBUG_REG29_TC_MH_send_SHIFT) +#define MH_DEBUG_REG29_GET_TC_ROQ_RTR_q(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG29_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG29_GET_KILL_EFF1(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_KILL_EFF1_MASK) >> MH_DEBUG_REG29_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG29_GET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_MASK) >> MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) +#define MH_DEBUG_REG29_GET_ANY_SAME_ROW_BANK(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_ANY_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG29_ANY_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG29_GET_TC_EFF1_QUAL(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_TC_EFF1_QUAL_MASK) >> MH_DEBUG_REG29_TC_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG29_GET_TC_ROQ_EMPTY(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG29_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG29_GET_TC_ROQ_FULL(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_TC_ROQ_FULL_MASK) >> MH_DEBUG_REG29_TC_ROQ_FULL_SHIFT) + +#define MH_DEBUG_REG29_SET_SAME_ROW_BANK_q(mh_debug_reg29_reg, same_row_bank_q) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_SAME_ROW_BANK_q_MASK) | (same_row_bank_q << MH_DEBUG_REG29_SAME_ROW_BANK_q_SHIFT) +#define MH_DEBUG_REG29_SET_ROQ_MARK_d(mh_debug_reg29_reg, roq_mark_d) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_ROQ_MARK_d_MASK) | (roq_mark_d << MH_DEBUG_REG29_ROQ_MARK_d_SHIFT) +#define MH_DEBUG_REG29_SET_ROQ_VALID_d(mh_debug_reg29_reg, roq_valid_d) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_ROQ_VALID_d_MASK) | (roq_valid_d << MH_DEBUG_REG29_ROQ_VALID_d_SHIFT) +#define MH_DEBUG_REG29_SET_TC_MH_send(mh_debug_reg29_reg, tc_mh_send) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG29_TC_MH_send_SHIFT) +#define MH_DEBUG_REG29_SET_TC_ROQ_RTR_q(mh_debug_reg29_reg, tc_roq_rtr_q) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG29_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG29_SET_KILL_EFF1(mh_debug_reg29_reg, kill_eff1) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG29_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG29_SET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg29_reg, tc_roq_same_row_bank_sel) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_MASK) | (tc_roq_same_row_bank_sel << MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) +#define MH_DEBUG_REG29_SET_ANY_SAME_ROW_BANK(mh_debug_reg29_reg, any_same_row_bank) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_ANY_SAME_ROW_BANK_MASK) | (any_same_row_bank << MH_DEBUG_REG29_ANY_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG29_SET_TC_EFF1_QUAL(mh_debug_reg29_reg, tc_eff1_qual) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_TC_EFF1_QUAL_MASK) | (tc_eff1_qual << MH_DEBUG_REG29_TC_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG29_SET_TC_ROQ_EMPTY(mh_debug_reg29_reg, tc_roq_empty) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG29_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG29_SET_TC_ROQ_FULL(mh_debug_reg29_reg, tc_roq_full) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_TC_ROQ_FULL_MASK) | (tc_roq_full << MH_DEBUG_REG29_TC_ROQ_FULL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg29_t { + unsigned int same_row_bank_q : MH_DEBUG_REG29_SAME_ROW_BANK_q_SIZE; + unsigned int roq_mark_d : MH_DEBUG_REG29_ROQ_MARK_d_SIZE; + unsigned int roq_valid_d : MH_DEBUG_REG29_ROQ_VALID_d_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG29_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG29_TC_ROQ_RTR_q_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG29_KILL_EFF1_SIZE; + unsigned int tc_roq_same_row_bank_sel : MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_SIZE; + unsigned int any_same_row_bank : MH_DEBUG_REG29_ANY_SAME_ROW_BANK_SIZE; + unsigned int tc_eff1_qual : MH_DEBUG_REG29_TC_EFF1_QUAL_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG29_TC_ROQ_EMPTY_SIZE; + unsigned int tc_roq_full : MH_DEBUG_REG29_TC_ROQ_FULL_SIZE; + } mh_debug_reg29_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg29_t { + unsigned int tc_roq_full : MH_DEBUG_REG29_TC_ROQ_FULL_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG29_TC_ROQ_EMPTY_SIZE; + unsigned int tc_eff1_qual : MH_DEBUG_REG29_TC_EFF1_QUAL_SIZE; + unsigned int any_same_row_bank : MH_DEBUG_REG29_ANY_SAME_ROW_BANK_SIZE; + unsigned int tc_roq_same_row_bank_sel : MH_DEBUG_REG29_TC_ROQ_SAME_ROW_BANK_SEL_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG29_KILL_EFF1_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG29_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG29_TC_MH_send_SIZE; + unsigned int roq_valid_d : MH_DEBUG_REG29_ROQ_VALID_d_SIZE; + unsigned int roq_mark_d : MH_DEBUG_REG29_ROQ_MARK_d_SIZE; + unsigned int same_row_bank_q : MH_DEBUG_REG29_SAME_ROW_BANK_q_SIZE; + } mh_debug_reg29_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg29_t f; +} mh_debug_reg29_u; + + +/* + * MH_DEBUG_REG30 struct + */ + +#define MH_DEBUG_REG30_SAME_ROW_BANK_WIN_SIZE 8 +#define MH_DEBUG_REG30_SAME_ROW_BANK_REQ_SIZE 8 +#define MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_SIZE 8 +#define MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_SIZE 8 + +#define MH_DEBUG_REG30_SAME_ROW_BANK_WIN_SHIFT 0 +#define MH_DEBUG_REG30_SAME_ROW_BANK_REQ_SHIFT 8 +#define MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_SHIFT 16 +#define MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_SHIFT 24 + +#define MH_DEBUG_REG30_SAME_ROW_BANK_WIN_MASK 0x000000ff +#define MH_DEBUG_REG30_SAME_ROW_BANK_REQ_MASK 0x0000ff00 +#define MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_MASK 0x00ff0000 +#define MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_MASK 0xff000000 + +#define MH_DEBUG_REG30_MASK \ + (MH_DEBUG_REG30_SAME_ROW_BANK_WIN_MASK | \ + MH_DEBUG_REG30_SAME_ROW_BANK_REQ_MASK | \ + MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_MASK | \ + MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_MASK) + +#define MH_DEBUG_REG30(same_row_bank_win, same_row_bank_req, non_same_row_bank_win, non_same_row_bank_req) \ + ((same_row_bank_win << MH_DEBUG_REG30_SAME_ROW_BANK_WIN_SHIFT) | \ + (same_row_bank_req << MH_DEBUG_REG30_SAME_ROW_BANK_REQ_SHIFT) | \ + (non_same_row_bank_win << MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_SHIFT) | \ + (non_same_row_bank_req << MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_SHIFT)) + +#define MH_DEBUG_REG30_GET_SAME_ROW_BANK_WIN(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_SAME_ROW_BANK_WIN_MASK) >> MH_DEBUG_REG30_SAME_ROW_BANK_WIN_SHIFT) +#define MH_DEBUG_REG30_GET_SAME_ROW_BANK_REQ(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_SAME_ROW_BANK_REQ_MASK) >> MH_DEBUG_REG30_SAME_ROW_BANK_REQ_SHIFT) +#define MH_DEBUG_REG30_GET_NON_SAME_ROW_BANK_WIN(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_MASK) >> MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_SHIFT) +#define MH_DEBUG_REG30_GET_NON_SAME_ROW_BANK_REQ(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_MASK) >> MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_SHIFT) + +#define MH_DEBUG_REG30_SET_SAME_ROW_BANK_WIN(mh_debug_reg30_reg, same_row_bank_win) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_SAME_ROW_BANK_WIN_MASK) | (same_row_bank_win << MH_DEBUG_REG30_SAME_ROW_BANK_WIN_SHIFT) +#define MH_DEBUG_REG30_SET_SAME_ROW_BANK_REQ(mh_debug_reg30_reg, same_row_bank_req) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_SAME_ROW_BANK_REQ_MASK) | (same_row_bank_req << MH_DEBUG_REG30_SAME_ROW_BANK_REQ_SHIFT) +#define MH_DEBUG_REG30_SET_NON_SAME_ROW_BANK_WIN(mh_debug_reg30_reg, non_same_row_bank_win) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_MASK) | (non_same_row_bank_win << MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_SHIFT) +#define MH_DEBUG_REG30_SET_NON_SAME_ROW_BANK_REQ(mh_debug_reg30_reg, non_same_row_bank_req) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_MASK) | (non_same_row_bank_req << MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg30_t { + unsigned int same_row_bank_win : MH_DEBUG_REG30_SAME_ROW_BANK_WIN_SIZE; + unsigned int same_row_bank_req : MH_DEBUG_REG30_SAME_ROW_BANK_REQ_SIZE; + unsigned int non_same_row_bank_win : MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_SIZE; + unsigned int non_same_row_bank_req : MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_SIZE; + } mh_debug_reg30_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg30_t { + unsigned int non_same_row_bank_req : MH_DEBUG_REG30_NON_SAME_ROW_BANK_REQ_SIZE; + unsigned int non_same_row_bank_win : MH_DEBUG_REG30_NON_SAME_ROW_BANK_WIN_SIZE; + unsigned int same_row_bank_req : MH_DEBUG_REG30_SAME_ROW_BANK_REQ_SIZE; + unsigned int same_row_bank_win : MH_DEBUG_REG30_SAME_ROW_BANK_WIN_SIZE; + } mh_debug_reg30_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg30_t f; +} mh_debug_reg30_u; + + +/* + * MH_DEBUG_REG31 struct + */ + +#define MH_DEBUG_REG31_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG31_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG31_ROQ_MARK_q_0_SIZE 1 +#define MH_DEBUG_REG31_ROQ_VALID_q_0_SIZE 1 +#define MH_DEBUG_REG31_SAME_ROW_BANK_q_0_SIZE 1 +#define MH_DEBUG_REG31_ROQ_ADDR_0_SIZE 27 + +#define MH_DEBUG_REG31_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG31_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG31_ROQ_MARK_q_0_SHIFT 2 +#define MH_DEBUG_REG31_ROQ_VALID_q_0_SHIFT 3 +#define MH_DEBUG_REG31_SAME_ROW_BANK_q_0_SHIFT 4 +#define MH_DEBUG_REG31_ROQ_ADDR_0_SHIFT 5 + +#define MH_DEBUG_REG31_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG31_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG31_ROQ_MARK_q_0_MASK 0x00000004 +#define MH_DEBUG_REG31_ROQ_VALID_q_0_MASK 0x00000008 +#define MH_DEBUG_REG31_SAME_ROW_BANK_q_0_MASK 0x00000010 +#define MH_DEBUG_REG31_ROQ_ADDR_0_MASK 0xffffffe0 + +#define MH_DEBUG_REG31_MASK \ + (MH_DEBUG_REG31_TC_MH_send_MASK | \ + MH_DEBUG_REG31_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG31_ROQ_MARK_q_0_MASK | \ + MH_DEBUG_REG31_ROQ_VALID_q_0_MASK | \ + MH_DEBUG_REG31_SAME_ROW_BANK_q_0_MASK | \ + MH_DEBUG_REG31_ROQ_ADDR_0_MASK) + +#define MH_DEBUG_REG31(tc_mh_send, tc_roq_rtr_q, roq_mark_q_0, roq_valid_q_0, same_row_bank_q_0, roq_addr_0) \ + ((tc_mh_send << MH_DEBUG_REG31_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG31_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_0 << MH_DEBUG_REG31_ROQ_MARK_q_0_SHIFT) | \ + (roq_valid_q_0 << MH_DEBUG_REG31_ROQ_VALID_q_0_SHIFT) | \ + (same_row_bank_q_0 << MH_DEBUG_REG31_SAME_ROW_BANK_q_0_SHIFT) | \ + (roq_addr_0 << MH_DEBUG_REG31_ROQ_ADDR_0_SHIFT)) + +#define MH_DEBUG_REG31_GET_TC_MH_send(mh_debug_reg31) \ + ((mh_debug_reg31 & MH_DEBUG_REG31_TC_MH_send_MASK) >> MH_DEBUG_REG31_TC_MH_send_SHIFT) +#define MH_DEBUG_REG31_GET_TC_ROQ_RTR_q(mh_debug_reg31) \ + ((mh_debug_reg31 & MH_DEBUG_REG31_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG31_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG31_GET_ROQ_MARK_q_0(mh_debug_reg31) \ + ((mh_debug_reg31 & MH_DEBUG_REG31_ROQ_MARK_q_0_MASK) >> MH_DEBUG_REG31_ROQ_MARK_q_0_SHIFT) +#define MH_DEBUG_REG31_GET_ROQ_VALID_q_0(mh_debug_reg31) \ + ((mh_debug_reg31 & MH_DEBUG_REG31_ROQ_VALID_q_0_MASK) >> MH_DEBUG_REG31_ROQ_VALID_q_0_SHIFT) +#define MH_DEBUG_REG31_GET_SAME_ROW_BANK_q_0(mh_debug_reg31) \ + ((mh_debug_reg31 & MH_DEBUG_REG31_SAME_ROW_BANK_q_0_MASK) >> MH_DEBUG_REG31_SAME_ROW_BANK_q_0_SHIFT) +#define MH_DEBUG_REG31_GET_ROQ_ADDR_0(mh_debug_reg31) \ + ((mh_debug_reg31 & MH_DEBUG_REG31_ROQ_ADDR_0_MASK) >> MH_DEBUG_REG31_ROQ_ADDR_0_SHIFT) + +#define MH_DEBUG_REG31_SET_TC_MH_send(mh_debug_reg31_reg, tc_mh_send) \ + mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG31_TC_MH_send_SHIFT) +#define MH_DEBUG_REG31_SET_TC_ROQ_RTR_q(mh_debug_reg31_reg, tc_roq_rtr_q) \ + mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG31_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG31_SET_ROQ_MARK_q_0(mh_debug_reg31_reg, roq_mark_q_0) \ + mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_ROQ_MARK_q_0_MASK) | (roq_mark_q_0 << MH_DEBUG_REG31_ROQ_MARK_q_0_SHIFT) +#define MH_DEBUG_REG31_SET_ROQ_VALID_q_0(mh_debug_reg31_reg, roq_valid_q_0) \ + mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_ROQ_VALID_q_0_MASK) | (roq_valid_q_0 << MH_DEBUG_REG31_ROQ_VALID_q_0_SHIFT) +#define MH_DEBUG_REG31_SET_SAME_ROW_BANK_q_0(mh_debug_reg31_reg, same_row_bank_q_0) \ + mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_SAME_ROW_BANK_q_0_MASK) | (same_row_bank_q_0 << MH_DEBUG_REG31_SAME_ROW_BANK_q_0_SHIFT) +#define MH_DEBUG_REG31_SET_ROQ_ADDR_0(mh_debug_reg31_reg, roq_addr_0) \ + mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_ROQ_ADDR_0_MASK) | (roq_addr_0 << MH_DEBUG_REG31_ROQ_ADDR_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg31_t { + unsigned int tc_mh_send : MH_DEBUG_REG31_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG31_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_0 : MH_DEBUG_REG31_ROQ_MARK_q_0_SIZE; + unsigned int roq_valid_q_0 : MH_DEBUG_REG31_ROQ_VALID_q_0_SIZE; + unsigned int same_row_bank_q_0 : MH_DEBUG_REG31_SAME_ROW_BANK_q_0_SIZE; + unsigned int roq_addr_0 : MH_DEBUG_REG31_ROQ_ADDR_0_SIZE; + } mh_debug_reg31_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg31_t { + unsigned int roq_addr_0 : MH_DEBUG_REG31_ROQ_ADDR_0_SIZE; + unsigned int same_row_bank_q_0 : MH_DEBUG_REG31_SAME_ROW_BANK_q_0_SIZE; + unsigned int roq_valid_q_0 : MH_DEBUG_REG31_ROQ_VALID_q_0_SIZE; + unsigned int roq_mark_q_0 : MH_DEBUG_REG31_ROQ_MARK_q_0_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG31_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG31_TC_MH_send_SIZE; + } mh_debug_reg31_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg31_t f; +} mh_debug_reg31_u; + + +/* + * MH_DEBUG_REG32 struct + */ + +#define MH_DEBUG_REG32_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG32_ROQ_MARK_q_1_SIZE 1 +#define MH_DEBUG_REG32_ROQ_VALID_q_1_SIZE 1 +#define MH_DEBUG_REG32_SAME_ROW_BANK_q_1_SIZE 1 +#define MH_DEBUG_REG32_ROQ_ADDR_1_SIZE 27 + +#define MH_DEBUG_REG32_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG32_ROQ_MARK_q_1_SHIFT 2 +#define MH_DEBUG_REG32_ROQ_VALID_q_1_SHIFT 3 +#define MH_DEBUG_REG32_SAME_ROW_BANK_q_1_SHIFT 4 +#define MH_DEBUG_REG32_ROQ_ADDR_1_SHIFT 5 + +#define MH_DEBUG_REG32_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG32_ROQ_MARK_q_1_MASK 0x00000004 +#define MH_DEBUG_REG32_ROQ_VALID_q_1_MASK 0x00000008 +#define MH_DEBUG_REG32_SAME_ROW_BANK_q_1_MASK 0x00000010 +#define MH_DEBUG_REG32_ROQ_ADDR_1_MASK 0xffffffe0 + +#define MH_DEBUG_REG32_MASK \ + (MH_DEBUG_REG32_TC_MH_send_MASK | \ + MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG32_ROQ_MARK_q_1_MASK | \ + MH_DEBUG_REG32_ROQ_VALID_q_1_MASK | \ + MH_DEBUG_REG32_SAME_ROW_BANK_q_1_MASK | \ + MH_DEBUG_REG32_ROQ_ADDR_1_MASK) + +#define MH_DEBUG_REG32(tc_mh_send, tc_roq_rtr_q, roq_mark_q_1, roq_valid_q_1, same_row_bank_q_1, roq_addr_1) \ + ((tc_mh_send << MH_DEBUG_REG32_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_1 << MH_DEBUG_REG32_ROQ_MARK_q_1_SHIFT) | \ + (roq_valid_q_1 << MH_DEBUG_REG32_ROQ_VALID_q_1_SHIFT) | \ + (same_row_bank_q_1 << MH_DEBUG_REG32_SAME_ROW_BANK_q_1_SHIFT) | \ + (roq_addr_1 << MH_DEBUG_REG32_ROQ_ADDR_1_SHIFT)) + +#define MH_DEBUG_REG32_GET_TC_MH_send(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_TC_MH_send_MASK) >> MH_DEBUG_REG32_TC_MH_send_SHIFT) +#define MH_DEBUG_REG32_GET_TC_ROQ_RTR_q(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG32_GET_ROQ_MARK_q_1(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_ROQ_MARK_q_1_MASK) >> MH_DEBUG_REG32_ROQ_MARK_q_1_SHIFT) +#define MH_DEBUG_REG32_GET_ROQ_VALID_q_1(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_ROQ_VALID_q_1_MASK) >> MH_DEBUG_REG32_ROQ_VALID_q_1_SHIFT) +#define MH_DEBUG_REG32_GET_SAME_ROW_BANK_q_1(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_SAME_ROW_BANK_q_1_MASK) >> MH_DEBUG_REG32_SAME_ROW_BANK_q_1_SHIFT) +#define MH_DEBUG_REG32_GET_ROQ_ADDR_1(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_ROQ_ADDR_1_MASK) >> MH_DEBUG_REG32_ROQ_ADDR_1_SHIFT) + +#define MH_DEBUG_REG32_SET_TC_MH_send(mh_debug_reg32_reg, tc_mh_send) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG32_TC_MH_send_SHIFT) +#define MH_DEBUG_REG32_SET_TC_ROQ_RTR_q(mh_debug_reg32_reg, tc_roq_rtr_q) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG32_SET_ROQ_MARK_q_1(mh_debug_reg32_reg, roq_mark_q_1) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ROQ_MARK_q_1_MASK) | (roq_mark_q_1 << MH_DEBUG_REG32_ROQ_MARK_q_1_SHIFT) +#define MH_DEBUG_REG32_SET_ROQ_VALID_q_1(mh_debug_reg32_reg, roq_valid_q_1) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ROQ_VALID_q_1_MASK) | (roq_valid_q_1 << MH_DEBUG_REG32_ROQ_VALID_q_1_SHIFT) +#define MH_DEBUG_REG32_SET_SAME_ROW_BANK_q_1(mh_debug_reg32_reg, same_row_bank_q_1) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_SAME_ROW_BANK_q_1_MASK) | (same_row_bank_q_1 << MH_DEBUG_REG32_SAME_ROW_BANK_q_1_SHIFT) +#define MH_DEBUG_REG32_SET_ROQ_ADDR_1(mh_debug_reg32_reg, roq_addr_1) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ROQ_ADDR_1_MASK) | (roq_addr_1 << MH_DEBUG_REG32_ROQ_ADDR_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg32_t { + unsigned int tc_mh_send : MH_DEBUG_REG32_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_1 : MH_DEBUG_REG32_ROQ_MARK_q_1_SIZE; + unsigned int roq_valid_q_1 : MH_DEBUG_REG32_ROQ_VALID_q_1_SIZE; + unsigned int same_row_bank_q_1 : MH_DEBUG_REG32_SAME_ROW_BANK_q_1_SIZE; + unsigned int roq_addr_1 : MH_DEBUG_REG32_ROQ_ADDR_1_SIZE; + } mh_debug_reg32_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg32_t { + unsigned int roq_addr_1 : MH_DEBUG_REG32_ROQ_ADDR_1_SIZE; + unsigned int same_row_bank_q_1 : MH_DEBUG_REG32_SAME_ROW_BANK_q_1_SIZE; + unsigned int roq_valid_q_1 : MH_DEBUG_REG32_ROQ_VALID_q_1_SIZE; + unsigned int roq_mark_q_1 : MH_DEBUG_REG32_ROQ_MARK_q_1_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG32_TC_MH_send_SIZE; + } mh_debug_reg32_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg32_t f; +} mh_debug_reg32_u; + + +/* + * MH_DEBUG_REG33 struct + */ + +#define MH_DEBUG_REG33_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG33_ROQ_MARK_q_2_SIZE 1 +#define MH_DEBUG_REG33_ROQ_VALID_q_2_SIZE 1 +#define MH_DEBUG_REG33_SAME_ROW_BANK_q_2_SIZE 1 +#define MH_DEBUG_REG33_ROQ_ADDR_2_SIZE 27 + +#define MH_DEBUG_REG33_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG33_ROQ_MARK_q_2_SHIFT 2 +#define MH_DEBUG_REG33_ROQ_VALID_q_2_SHIFT 3 +#define MH_DEBUG_REG33_SAME_ROW_BANK_q_2_SHIFT 4 +#define MH_DEBUG_REG33_ROQ_ADDR_2_SHIFT 5 + +#define MH_DEBUG_REG33_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG33_ROQ_MARK_q_2_MASK 0x00000004 +#define MH_DEBUG_REG33_ROQ_VALID_q_2_MASK 0x00000008 +#define MH_DEBUG_REG33_SAME_ROW_BANK_q_2_MASK 0x00000010 +#define MH_DEBUG_REG33_ROQ_ADDR_2_MASK 0xffffffe0 + +#define MH_DEBUG_REG33_MASK \ + (MH_DEBUG_REG33_TC_MH_send_MASK | \ + MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG33_ROQ_MARK_q_2_MASK | \ + MH_DEBUG_REG33_ROQ_VALID_q_2_MASK | \ + MH_DEBUG_REG33_SAME_ROW_BANK_q_2_MASK | \ + MH_DEBUG_REG33_ROQ_ADDR_2_MASK) + +#define MH_DEBUG_REG33(tc_mh_send, tc_roq_rtr_q, roq_mark_q_2, roq_valid_q_2, same_row_bank_q_2, roq_addr_2) \ + ((tc_mh_send << MH_DEBUG_REG33_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_2 << MH_DEBUG_REG33_ROQ_MARK_q_2_SHIFT) | \ + (roq_valid_q_2 << MH_DEBUG_REG33_ROQ_VALID_q_2_SHIFT) | \ + (same_row_bank_q_2 << MH_DEBUG_REG33_SAME_ROW_BANK_q_2_SHIFT) | \ + (roq_addr_2 << MH_DEBUG_REG33_ROQ_ADDR_2_SHIFT)) + +#define MH_DEBUG_REG33_GET_TC_MH_send(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_TC_MH_send_MASK) >> MH_DEBUG_REG33_TC_MH_send_SHIFT) +#define MH_DEBUG_REG33_GET_TC_ROQ_RTR_q(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG33_GET_ROQ_MARK_q_2(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_ROQ_MARK_q_2_MASK) >> MH_DEBUG_REG33_ROQ_MARK_q_2_SHIFT) +#define MH_DEBUG_REG33_GET_ROQ_VALID_q_2(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_ROQ_VALID_q_2_MASK) >> MH_DEBUG_REG33_ROQ_VALID_q_2_SHIFT) +#define MH_DEBUG_REG33_GET_SAME_ROW_BANK_q_2(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_SAME_ROW_BANK_q_2_MASK) >> MH_DEBUG_REG33_SAME_ROW_BANK_q_2_SHIFT) +#define MH_DEBUG_REG33_GET_ROQ_ADDR_2(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_ROQ_ADDR_2_MASK) >> MH_DEBUG_REG33_ROQ_ADDR_2_SHIFT) + +#define MH_DEBUG_REG33_SET_TC_MH_send(mh_debug_reg33_reg, tc_mh_send) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG33_TC_MH_send_SHIFT) +#define MH_DEBUG_REG33_SET_TC_ROQ_RTR_q(mh_debug_reg33_reg, tc_roq_rtr_q) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG33_SET_ROQ_MARK_q_2(mh_debug_reg33_reg, roq_mark_q_2) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ROQ_MARK_q_2_MASK) | (roq_mark_q_2 << MH_DEBUG_REG33_ROQ_MARK_q_2_SHIFT) +#define MH_DEBUG_REG33_SET_ROQ_VALID_q_2(mh_debug_reg33_reg, roq_valid_q_2) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ROQ_VALID_q_2_MASK) | (roq_valid_q_2 << MH_DEBUG_REG33_ROQ_VALID_q_2_SHIFT) +#define MH_DEBUG_REG33_SET_SAME_ROW_BANK_q_2(mh_debug_reg33_reg, same_row_bank_q_2) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_SAME_ROW_BANK_q_2_MASK) | (same_row_bank_q_2 << MH_DEBUG_REG33_SAME_ROW_BANK_q_2_SHIFT) +#define MH_DEBUG_REG33_SET_ROQ_ADDR_2(mh_debug_reg33_reg, roq_addr_2) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ROQ_ADDR_2_MASK) | (roq_addr_2 << MH_DEBUG_REG33_ROQ_ADDR_2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg33_t { + unsigned int tc_mh_send : MH_DEBUG_REG33_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_2 : MH_DEBUG_REG33_ROQ_MARK_q_2_SIZE; + unsigned int roq_valid_q_2 : MH_DEBUG_REG33_ROQ_VALID_q_2_SIZE; + unsigned int same_row_bank_q_2 : MH_DEBUG_REG33_SAME_ROW_BANK_q_2_SIZE; + unsigned int roq_addr_2 : MH_DEBUG_REG33_ROQ_ADDR_2_SIZE; + } mh_debug_reg33_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg33_t { + unsigned int roq_addr_2 : MH_DEBUG_REG33_ROQ_ADDR_2_SIZE; + unsigned int same_row_bank_q_2 : MH_DEBUG_REG33_SAME_ROW_BANK_q_2_SIZE; + unsigned int roq_valid_q_2 : MH_DEBUG_REG33_ROQ_VALID_q_2_SIZE; + unsigned int roq_mark_q_2 : MH_DEBUG_REG33_ROQ_MARK_q_2_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG33_TC_MH_send_SIZE; + } mh_debug_reg33_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg33_t f; +} mh_debug_reg33_u; + + +/* + * MH_DEBUG_REG34 struct + */ + +#define MH_DEBUG_REG34_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG34_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG34_ROQ_MARK_q_3_SIZE 1 +#define MH_DEBUG_REG34_ROQ_VALID_q_3_SIZE 1 +#define MH_DEBUG_REG34_SAME_ROW_BANK_q_3_SIZE 1 +#define MH_DEBUG_REG34_ROQ_ADDR_3_SIZE 27 + +#define MH_DEBUG_REG34_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG34_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG34_ROQ_MARK_q_3_SHIFT 2 +#define MH_DEBUG_REG34_ROQ_VALID_q_3_SHIFT 3 +#define MH_DEBUG_REG34_SAME_ROW_BANK_q_3_SHIFT 4 +#define MH_DEBUG_REG34_ROQ_ADDR_3_SHIFT 5 + +#define MH_DEBUG_REG34_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG34_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG34_ROQ_MARK_q_3_MASK 0x00000004 +#define MH_DEBUG_REG34_ROQ_VALID_q_3_MASK 0x00000008 +#define MH_DEBUG_REG34_SAME_ROW_BANK_q_3_MASK 0x00000010 +#define MH_DEBUG_REG34_ROQ_ADDR_3_MASK 0xffffffe0 + +#define MH_DEBUG_REG34_MASK \ + (MH_DEBUG_REG34_TC_MH_send_MASK | \ + MH_DEBUG_REG34_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG34_ROQ_MARK_q_3_MASK | \ + MH_DEBUG_REG34_ROQ_VALID_q_3_MASK | \ + MH_DEBUG_REG34_SAME_ROW_BANK_q_3_MASK | \ + MH_DEBUG_REG34_ROQ_ADDR_3_MASK) + +#define MH_DEBUG_REG34(tc_mh_send, tc_roq_rtr_q, roq_mark_q_3, roq_valid_q_3, same_row_bank_q_3, roq_addr_3) \ + ((tc_mh_send << MH_DEBUG_REG34_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG34_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_3 << MH_DEBUG_REG34_ROQ_MARK_q_3_SHIFT) | \ + (roq_valid_q_3 << MH_DEBUG_REG34_ROQ_VALID_q_3_SHIFT) | \ + (same_row_bank_q_3 << MH_DEBUG_REG34_SAME_ROW_BANK_q_3_SHIFT) | \ + (roq_addr_3 << MH_DEBUG_REG34_ROQ_ADDR_3_SHIFT)) + +#define MH_DEBUG_REG34_GET_TC_MH_send(mh_debug_reg34) \ + ((mh_debug_reg34 & MH_DEBUG_REG34_TC_MH_send_MASK) >> MH_DEBUG_REG34_TC_MH_send_SHIFT) +#define MH_DEBUG_REG34_GET_TC_ROQ_RTR_q(mh_debug_reg34) \ + ((mh_debug_reg34 & MH_DEBUG_REG34_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG34_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG34_GET_ROQ_MARK_q_3(mh_debug_reg34) \ + ((mh_debug_reg34 & MH_DEBUG_REG34_ROQ_MARK_q_3_MASK) >> MH_DEBUG_REG34_ROQ_MARK_q_3_SHIFT) +#define MH_DEBUG_REG34_GET_ROQ_VALID_q_3(mh_debug_reg34) \ + ((mh_debug_reg34 & MH_DEBUG_REG34_ROQ_VALID_q_3_MASK) >> MH_DEBUG_REG34_ROQ_VALID_q_3_SHIFT) +#define MH_DEBUG_REG34_GET_SAME_ROW_BANK_q_3(mh_debug_reg34) \ + ((mh_debug_reg34 & MH_DEBUG_REG34_SAME_ROW_BANK_q_3_MASK) >> MH_DEBUG_REG34_SAME_ROW_BANK_q_3_SHIFT) +#define MH_DEBUG_REG34_GET_ROQ_ADDR_3(mh_debug_reg34) \ + ((mh_debug_reg34 & MH_DEBUG_REG34_ROQ_ADDR_3_MASK) >> MH_DEBUG_REG34_ROQ_ADDR_3_SHIFT) + +#define MH_DEBUG_REG34_SET_TC_MH_send(mh_debug_reg34_reg, tc_mh_send) \ + mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG34_TC_MH_send_SHIFT) +#define MH_DEBUG_REG34_SET_TC_ROQ_RTR_q(mh_debug_reg34_reg, tc_roq_rtr_q) \ + mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG34_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG34_SET_ROQ_MARK_q_3(mh_debug_reg34_reg, roq_mark_q_3) \ + mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_ROQ_MARK_q_3_MASK) | (roq_mark_q_3 << MH_DEBUG_REG34_ROQ_MARK_q_3_SHIFT) +#define MH_DEBUG_REG34_SET_ROQ_VALID_q_3(mh_debug_reg34_reg, roq_valid_q_3) \ + mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_ROQ_VALID_q_3_MASK) | (roq_valid_q_3 << MH_DEBUG_REG34_ROQ_VALID_q_3_SHIFT) +#define MH_DEBUG_REG34_SET_SAME_ROW_BANK_q_3(mh_debug_reg34_reg, same_row_bank_q_3) \ + mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_SAME_ROW_BANK_q_3_MASK) | (same_row_bank_q_3 << MH_DEBUG_REG34_SAME_ROW_BANK_q_3_SHIFT) +#define MH_DEBUG_REG34_SET_ROQ_ADDR_3(mh_debug_reg34_reg, roq_addr_3) \ + mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_ROQ_ADDR_3_MASK) | (roq_addr_3 << MH_DEBUG_REG34_ROQ_ADDR_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg34_t { + unsigned int tc_mh_send : MH_DEBUG_REG34_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG34_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_3 : MH_DEBUG_REG34_ROQ_MARK_q_3_SIZE; + unsigned int roq_valid_q_3 : MH_DEBUG_REG34_ROQ_VALID_q_3_SIZE; + unsigned int same_row_bank_q_3 : MH_DEBUG_REG34_SAME_ROW_BANK_q_3_SIZE; + unsigned int roq_addr_3 : MH_DEBUG_REG34_ROQ_ADDR_3_SIZE; + } mh_debug_reg34_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg34_t { + unsigned int roq_addr_3 : MH_DEBUG_REG34_ROQ_ADDR_3_SIZE; + unsigned int same_row_bank_q_3 : MH_DEBUG_REG34_SAME_ROW_BANK_q_3_SIZE; + unsigned int roq_valid_q_3 : MH_DEBUG_REG34_ROQ_VALID_q_3_SIZE; + unsigned int roq_mark_q_3 : MH_DEBUG_REG34_ROQ_MARK_q_3_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG34_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG34_TC_MH_send_SIZE; + } mh_debug_reg34_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg34_t f; +} mh_debug_reg34_u; + + +/* + * MH_DEBUG_REG35 struct + */ + +#define MH_DEBUG_REG35_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG35_ROQ_MARK_q_4_SIZE 1 +#define MH_DEBUG_REG35_ROQ_VALID_q_4_SIZE 1 +#define MH_DEBUG_REG35_SAME_ROW_BANK_q_4_SIZE 1 +#define MH_DEBUG_REG35_ROQ_ADDR_4_SIZE 27 + +#define MH_DEBUG_REG35_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG35_ROQ_MARK_q_4_SHIFT 2 +#define MH_DEBUG_REG35_ROQ_VALID_q_4_SHIFT 3 +#define MH_DEBUG_REG35_SAME_ROW_BANK_q_4_SHIFT 4 +#define MH_DEBUG_REG35_ROQ_ADDR_4_SHIFT 5 + +#define MH_DEBUG_REG35_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG35_ROQ_MARK_q_4_MASK 0x00000004 +#define MH_DEBUG_REG35_ROQ_VALID_q_4_MASK 0x00000008 +#define MH_DEBUG_REG35_SAME_ROW_BANK_q_4_MASK 0x00000010 +#define MH_DEBUG_REG35_ROQ_ADDR_4_MASK 0xffffffe0 + +#define MH_DEBUG_REG35_MASK \ + (MH_DEBUG_REG35_TC_MH_send_MASK | \ + MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG35_ROQ_MARK_q_4_MASK | \ + MH_DEBUG_REG35_ROQ_VALID_q_4_MASK | \ + MH_DEBUG_REG35_SAME_ROW_BANK_q_4_MASK | \ + MH_DEBUG_REG35_ROQ_ADDR_4_MASK) + +#define MH_DEBUG_REG35(tc_mh_send, tc_roq_rtr_q, roq_mark_q_4, roq_valid_q_4, same_row_bank_q_4, roq_addr_4) \ + ((tc_mh_send << MH_DEBUG_REG35_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_4 << MH_DEBUG_REG35_ROQ_MARK_q_4_SHIFT) | \ + (roq_valid_q_4 << MH_DEBUG_REG35_ROQ_VALID_q_4_SHIFT) | \ + (same_row_bank_q_4 << MH_DEBUG_REG35_SAME_ROW_BANK_q_4_SHIFT) | \ + (roq_addr_4 << MH_DEBUG_REG35_ROQ_ADDR_4_SHIFT)) + +#define MH_DEBUG_REG35_GET_TC_MH_send(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_TC_MH_send_MASK) >> MH_DEBUG_REG35_TC_MH_send_SHIFT) +#define MH_DEBUG_REG35_GET_TC_ROQ_RTR_q(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG35_GET_ROQ_MARK_q_4(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_MARK_q_4_MASK) >> MH_DEBUG_REG35_ROQ_MARK_q_4_SHIFT) +#define MH_DEBUG_REG35_GET_ROQ_VALID_q_4(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_VALID_q_4_MASK) >> MH_DEBUG_REG35_ROQ_VALID_q_4_SHIFT) +#define MH_DEBUG_REG35_GET_SAME_ROW_BANK_q_4(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_SAME_ROW_BANK_q_4_MASK) >> MH_DEBUG_REG35_SAME_ROW_BANK_q_4_SHIFT) +#define MH_DEBUG_REG35_GET_ROQ_ADDR_4(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_ADDR_4_MASK) >> MH_DEBUG_REG35_ROQ_ADDR_4_SHIFT) + +#define MH_DEBUG_REG35_SET_TC_MH_send(mh_debug_reg35_reg, tc_mh_send) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG35_TC_MH_send_SHIFT) +#define MH_DEBUG_REG35_SET_TC_ROQ_RTR_q(mh_debug_reg35_reg, tc_roq_rtr_q) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG35_SET_ROQ_MARK_q_4(mh_debug_reg35_reg, roq_mark_q_4) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_MARK_q_4_MASK) | (roq_mark_q_4 << MH_DEBUG_REG35_ROQ_MARK_q_4_SHIFT) +#define MH_DEBUG_REG35_SET_ROQ_VALID_q_4(mh_debug_reg35_reg, roq_valid_q_4) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_VALID_q_4_MASK) | (roq_valid_q_4 << MH_DEBUG_REG35_ROQ_VALID_q_4_SHIFT) +#define MH_DEBUG_REG35_SET_SAME_ROW_BANK_q_4(mh_debug_reg35_reg, same_row_bank_q_4) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_SAME_ROW_BANK_q_4_MASK) | (same_row_bank_q_4 << MH_DEBUG_REG35_SAME_ROW_BANK_q_4_SHIFT) +#define MH_DEBUG_REG35_SET_ROQ_ADDR_4(mh_debug_reg35_reg, roq_addr_4) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_ADDR_4_MASK) | (roq_addr_4 << MH_DEBUG_REG35_ROQ_ADDR_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg35_t { + unsigned int tc_mh_send : MH_DEBUG_REG35_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_4 : MH_DEBUG_REG35_ROQ_MARK_q_4_SIZE; + unsigned int roq_valid_q_4 : MH_DEBUG_REG35_ROQ_VALID_q_4_SIZE; + unsigned int same_row_bank_q_4 : MH_DEBUG_REG35_SAME_ROW_BANK_q_4_SIZE; + unsigned int roq_addr_4 : MH_DEBUG_REG35_ROQ_ADDR_4_SIZE; + } mh_debug_reg35_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg35_t { + unsigned int roq_addr_4 : MH_DEBUG_REG35_ROQ_ADDR_4_SIZE; + unsigned int same_row_bank_q_4 : MH_DEBUG_REG35_SAME_ROW_BANK_q_4_SIZE; + unsigned int roq_valid_q_4 : MH_DEBUG_REG35_ROQ_VALID_q_4_SIZE; + unsigned int roq_mark_q_4 : MH_DEBUG_REG35_ROQ_MARK_q_4_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG35_TC_MH_send_SIZE; + } mh_debug_reg35_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg35_t f; +} mh_debug_reg35_u; + + +/* + * MH_DEBUG_REG36 struct + */ + +#define MH_DEBUG_REG36_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG36_ROQ_MARK_q_5_SIZE 1 +#define MH_DEBUG_REG36_ROQ_VALID_q_5_SIZE 1 +#define MH_DEBUG_REG36_SAME_ROW_BANK_q_5_SIZE 1 +#define MH_DEBUG_REG36_ROQ_ADDR_5_SIZE 27 + +#define MH_DEBUG_REG36_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG36_ROQ_MARK_q_5_SHIFT 2 +#define MH_DEBUG_REG36_ROQ_VALID_q_5_SHIFT 3 +#define MH_DEBUG_REG36_SAME_ROW_BANK_q_5_SHIFT 4 +#define MH_DEBUG_REG36_ROQ_ADDR_5_SHIFT 5 + +#define MH_DEBUG_REG36_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG36_ROQ_MARK_q_5_MASK 0x00000004 +#define MH_DEBUG_REG36_ROQ_VALID_q_5_MASK 0x00000008 +#define MH_DEBUG_REG36_SAME_ROW_BANK_q_5_MASK 0x00000010 +#define MH_DEBUG_REG36_ROQ_ADDR_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG36_MASK \ + (MH_DEBUG_REG36_TC_MH_send_MASK | \ + MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG36_ROQ_MARK_q_5_MASK | \ + MH_DEBUG_REG36_ROQ_VALID_q_5_MASK | \ + MH_DEBUG_REG36_SAME_ROW_BANK_q_5_MASK | \ + MH_DEBUG_REG36_ROQ_ADDR_5_MASK) + +#define MH_DEBUG_REG36(tc_mh_send, tc_roq_rtr_q, roq_mark_q_5, roq_valid_q_5, same_row_bank_q_5, roq_addr_5) \ + ((tc_mh_send << MH_DEBUG_REG36_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_5 << MH_DEBUG_REG36_ROQ_MARK_q_5_SHIFT) | \ + (roq_valid_q_5 << MH_DEBUG_REG36_ROQ_VALID_q_5_SHIFT) | \ + (same_row_bank_q_5 << MH_DEBUG_REG36_SAME_ROW_BANK_q_5_SHIFT) | \ + (roq_addr_5 << MH_DEBUG_REG36_ROQ_ADDR_5_SHIFT)) + +#define MH_DEBUG_REG36_GET_TC_MH_send(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_TC_MH_send_MASK) >> MH_DEBUG_REG36_TC_MH_send_SHIFT) +#define MH_DEBUG_REG36_GET_TC_ROQ_RTR_q(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG36_GET_ROQ_MARK_q_5(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_MARK_q_5_MASK) >> MH_DEBUG_REG36_ROQ_MARK_q_5_SHIFT) +#define MH_DEBUG_REG36_GET_ROQ_VALID_q_5(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_VALID_q_5_MASK) >> MH_DEBUG_REG36_ROQ_VALID_q_5_SHIFT) +#define MH_DEBUG_REG36_GET_SAME_ROW_BANK_q_5(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_SAME_ROW_BANK_q_5_MASK) >> MH_DEBUG_REG36_SAME_ROW_BANK_q_5_SHIFT) +#define MH_DEBUG_REG36_GET_ROQ_ADDR_5(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_ADDR_5_MASK) >> MH_DEBUG_REG36_ROQ_ADDR_5_SHIFT) + +#define MH_DEBUG_REG36_SET_TC_MH_send(mh_debug_reg36_reg, tc_mh_send) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG36_TC_MH_send_SHIFT) +#define MH_DEBUG_REG36_SET_TC_ROQ_RTR_q(mh_debug_reg36_reg, tc_roq_rtr_q) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG36_SET_ROQ_MARK_q_5(mh_debug_reg36_reg, roq_mark_q_5) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_MARK_q_5_MASK) | (roq_mark_q_5 << MH_DEBUG_REG36_ROQ_MARK_q_5_SHIFT) +#define MH_DEBUG_REG36_SET_ROQ_VALID_q_5(mh_debug_reg36_reg, roq_valid_q_5) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_VALID_q_5_MASK) | (roq_valid_q_5 << MH_DEBUG_REG36_ROQ_VALID_q_5_SHIFT) +#define MH_DEBUG_REG36_SET_SAME_ROW_BANK_q_5(mh_debug_reg36_reg, same_row_bank_q_5) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_SAME_ROW_BANK_q_5_MASK) | (same_row_bank_q_5 << MH_DEBUG_REG36_SAME_ROW_BANK_q_5_SHIFT) +#define MH_DEBUG_REG36_SET_ROQ_ADDR_5(mh_debug_reg36_reg, roq_addr_5) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_ADDR_5_MASK) | (roq_addr_5 << MH_DEBUG_REG36_ROQ_ADDR_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg36_t { + unsigned int tc_mh_send : MH_DEBUG_REG36_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_5 : MH_DEBUG_REG36_ROQ_MARK_q_5_SIZE; + unsigned int roq_valid_q_5 : MH_DEBUG_REG36_ROQ_VALID_q_5_SIZE; + unsigned int same_row_bank_q_5 : MH_DEBUG_REG36_SAME_ROW_BANK_q_5_SIZE; + unsigned int roq_addr_5 : MH_DEBUG_REG36_ROQ_ADDR_5_SIZE; + } mh_debug_reg36_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg36_t { + unsigned int roq_addr_5 : MH_DEBUG_REG36_ROQ_ADDR_5_SIZE; + unsigned int same_row_bank_q_5 : MH_DEBUG_REG36_SAME_ROW_BANK_q_5_SIZE; + unsigned int roq_valid_q_5 : MH_DEBUG_REG36_ROQ_VALID_q_5_SIZE; + unsigned int roq_mark_q_5 : MH_DEBUG_REG36_ROQ_MARK_q_5_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG36_TC_MH_send_SIZE; + } mh_debug_reg36_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg36_t f; +} mh_debug_reg36_u; + + +/* + * MH_DEBUG_REG37 struct + */ + +#define MH_DEBUG_REG37_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG37_ROQ_MARK_q_6_SIZE 1 +#define MH_DEBUG_REG37_ROQ_VALID_q_6_SIZE 1 +#define MH_DEBUG_REG37_SAME_ROW_BANK_q_6_SIZE 1 +#define MH_DEBUG_REG37_ROQ_ADDR_6_SIZE 27 + +#define MH_DEBUG_REG37_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG37_ROQ_MARK_q_6_SHIFT 2 +#define MH_DEBUG_REG37_ROQ_VALID_q_6_SHIFT 3 +#define MH_DEBUG_REG37_SAME_ROW_BANK_q_6_SHIFT 4 +#define MH_DEBUG_REG37_ROQ_ADDR_6_SHIFT 5 + +#define MH_DEBUG_REG37_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG37_ROQ_MARK_q_6_MASK 0x00000004 +#define MH_DEBUG_REG37_ROQ_VALID_q_6_MASK 0x00000008 +#define MH_DEBUG_REG37_SAME_ROW_BANK_q_6_MASK 0x00000010 +#define MH_DEBUG_REG37_ROQ_ADDR_6_MASK 0xffffffe0 + +#define MH_DEBUG_REG37_MASK \ + (MH_DEBUG_REG37_TC_MH_send_MASK | \ + MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG37_ROQ_MARK_q_6_MASK | \ + MH_DEBUG_REG37_ROQ_VALID_q_6_MASK | \ + MH_DEBUG_REG37_SAME_ROW_BANK_q_6_MASK | \ + MH_DEBUG_REG37_ROQ_ADDR_6_MASK) + +#define MH_DEBUG_REG37(tc_mh_send, tc_roq_rtr_q, roq_mark_q_6, roq_valid_q_6, same_row_bank_q_6, roq_addr_6) \ + ((tc_mh_send << MH_DEBUG_REG37_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_6 << MH_DEBUG_REG37_ROQ_MARK_q_6_SHIFT) | \ + (roq_valid_q_6 << MH_DEBUG_REG37_ROQ_VALID_q_6_SHIFT) | \ + (same_row_bank_q_6 << MH_DEBUG_REG37_SAME_ROW_BANK_q_6_SHIFT) | \ + (roq_addr_6 << MH_DEBUG_REG37_ROQ_ADDR_6_SHIFT)) + +#define MH_DEBUG_REG37_GET_TC_MH_send(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_TC_MH_send_MASK) >> MH_DEBUG_REG37_TC_MH_send_SHIFT) +#define MH_DEBUG_REG37_GET_TC_ROQ_RTR_q(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG37_GET_ROQ_MARK_q_6(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_MARK_q_6_MASK) >> MH_DEBUG_REG37_ROQ_MARK_q_6_SHIFT) +#define MH_DEBUG_REG37_GET_ROQ_VALID_q_6(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_VALID_q_6_MASK) >> MH_DEBUG_REG37_ROQ_VALID_q_6_SHIFT) +#define MH_DEBUG_REG37_GET_SAME_ROW_BANK_q_6(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_SAME_ROW_BANK_q_6_MASK) >> MH_DEBUG_REG37_SAME_ROW_BANK_q_6_SHIFT) +#define MH_DEBUG_REG37_GET_ROQ_ADDR_6(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_ADDR_6_MASK) >> MH_DEBUG_REG37_ROQ_ADDR_6_SHIFT) + +#define MH_DEBUG_REG37_SET_TC_MH_send(mh_debug_reg37_reg, tc_mh_send) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG37_TC_MH_send_SHIFT) +#define MH_DEBUG_REG37_SET_TC_ROQ_RTR_q(mh_debug_reg37_reg, tc_roq_rtr_q) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG37_SET_ROQ_MARK_q_6(mh_debug_reg37_reg, roq_mark_q_6) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_MARK_q_6_MASK) | (roq_mark_q_6 << MH_DEBUG_REG37_ROQ_MARK_q_6_SHIFT) +#define MH_DEBUG_REG37_SET_ROQ_VALID_q_6(mh_debug_reg37_reg, roq_valid_q_6) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_VALID_q_6_MASK) | (roq_valid_q_6 << MH_DEBUG_REG37_ROQ_VALID_q_6_SHIFT) +#define MH_DEBUG_REG37_SET_SAME_ROW_BANK_q_6(mh_debug_reg37_reg, same_row_bank_q_6) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_SAME_ROW_BANK_q_6_MASK) | (same_row_bank_q_6 << MH_DEBUG_REG37_SAME_ROW_BANK_q_6_SHIFT) +#define MH_DEBUG_REG37_SET_ROQ_ADDR_6(mh_debug_reg37_reg, roq_addr_6) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_ADDR_6_MASK) | (roq_addr_6 << MH_DEBUG_REG37_ROQ_ADDR_6_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg37_t { + unsigned int tc_mh_send : MH_DEBUG_REG37_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_6 : MH_DEBUG_REG37_ROQ_MARK_q_6_SIZE; + unsigned int roq_valid_q_6 : MH_DEBUG_REG37_ROQ_VALID_q_6_SIZE; + unsigned int same_row_bank_q_6 : MH_DEBUG_REG37_SAME_ROW_BANK_q_6_SIZE; + unsigned int roq_addr_6 : MH_DEBUG_REG37_ROQ_ADDR_6_SIZE; + } mh_debug_reg37_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg37_t { + unsigned int roq_addr_6 : MH_DEBUG_REG37_ROQ_ADDR_6_SIZE; + unsigned int same_row_bank_q_6 : MH_DEBUG_REG37_SAME_ROW_BANK_q_6_SIZE; + unsigned int roq_valid_q_6 : MH_DEBUG_REG37_ROQ_VALID_q_6_SIZE; + unsigned int roq_mark_q_6 : MH_DEBUG_REG37_ROQ_MARK_q_6_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG37_TC_MH_send_SIZE; + } mh_debug_reg37_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg37_t f; +} mh_debug_reg37_u; + + +/* + * MH_DEBUG_REG38 struct + */ + +#define MH_DEBUG_REG38_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG38_ROQ_MARK_q_7_SIZE 1 +#define MH_DEBUG_REG38_ROQ_VALID_q_7_SIZE 1 +#define MH_DEBUG_REG38_SAME_ROW_BANK_q_7_SIZE 1 +#define MH_DEBUG_REG38_ROQ_ADDR_7_SIZE 27 + +#define MH_DEBUG_REG38_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG38_ROQ_MARK_q_7_SHIFT 2 +#define MH_DEBUG_REG38_ROQ_VALID_q_7_SHIFT 3 +#define MH_DEBUG_REG38_SAME_ROW_BANK_q_7_SHIFT 4 +#define MH_DEBUG_REG38_ROQ_ADDR_7_SHIFT 5 + +#define MH_DEBUG_REG38_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG38_ROQ_MARK_q_7_MASK 0x00000004 +#define MH_DEBUG_REG38_ROQ_VALID_q_7_MASK 0x00000008 +#define MH_DEBUG_REG38_SAME_ROW_BANK_q_7_MASK 0x00000010 +#define MH_DEBUG_REG38_ROQ_ADDR_7_MASK 0xffffffe0 + +#define MH_DEBUG_REG38_MASK \ + (MH_DEBUG_REG38_TC_MH_send_MASK | \ + MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG38_ROQ_MARK_q_7_MASK | \ + MH_DEBUG_REG38_ROQ_VALID_q_7_MASK | \ + MH_DEBUG_REG38_SAME_ROW_BANK_q_7_MASK | \ + MH_DEBUG_REG38_ROQ_ADDR_7_MASK) + +#define MH_DEBUG_REG38(tc_mh_send, tc_roq_rtr_q, roq_mark_q_7, roq_valid_q_7, same_row_bank_q_7, roq_addr_7) \ + ((tc_mh_send << MH_DEBUG_REG38_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_7 << MH_DEBUG_REG38_ROQ_MARK_q_7_SHIFT) | \ + (roq_valid_q_7 << MH_DEBUG_REG38_ROQ_VALID_q_7_SHIFT) | \ + (same_row_bank_q_7 << MH_DEBUG_REG38_SAME_ROW_BANK_q_7_SHIFT) | \ + (roq_addr_7 << MH_DEBUG_REG38_ROQ_ADDR_7_SHIFT)) + +#define MH_DEBUG_REG38_GET_TC_MH_send(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_TC_MH_send_MASK) >> MH_DEBUG_REG38_TC_MH_send_SHIFT) +#define MH_DEBUG_REG38_GET_TC_ROQ_RTR_q(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG38_GET_ROQ_MARK_q_7(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_MARK_q_7_MASK) >> MH_DEBUG_REG38_ROQ_MARK_q_7_SHIFT) +#define MH_DEBUG_REG38_GET_ROQ_VALID_q_7(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_VALID_q_7_MASK) >> MH_DEBUG_REG38_ROQ_VALID_q_7_SHIFT) +#define MH_DEBUG_REG38_GET_SAME_ROW_BANK_q_7(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_SAME_ROW_BANK_q_7_MASK) >> MH_DEBUG_REG38_SAME_ROW_BANK_q_7_SHIFT) +#define MH_DEBUG_REG38_GET_ROQ_ADDR_7(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_ADDR_7_MASK) >> MH_DEBUG_REG38_ROQ_ADDR_7_SHIFT) + +#define MH_DEBUG_REG38_SET_TC_MH_send(mh_debug_reg38_reg, tc_mh_send) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG38_TC_MH_send_SHIFT) +#define MH_DEBUG_REG38_SET_TC_ROQ_RTR_q(mh_debug_reg38_reg, tc_roq_rtr_q) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG38_SET_ROQ_MARK_q_7(mh_debug_reg38_reg, roq_mark_q_7) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_MARK_q_7_MASK) | (roq_mark_q_7 << MH_DEBUG_REG38_ROQ_MARK_q_7_SHIFT) +#define MH_DEBUG_REG38_SET_ROQ_VALID_q_7(mh_debug_reg38_reg, roq_valid_q_7) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_VALID_q_7_MASK) | (roq_valid_q_7 << MH_DEBUG_REG38_ROQ_VALID_q_7_SHIFT) +#define MH_DEBUG_REG38_SET_SAME_ROW_BANK_q_7(mh_debug_reg38_reg, same_row_bank_q_7) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_SAME_ROW_BANK_q_7_MASK) | (same_row_bank_q_7 << MH_DEBUG_REG38_SAME_ROW_BANK_q_7_SHIFT) +#define MH_DEBUG_REG38_SET_ROQ_ADDR_7(mh_debug_reg38_reg, roq_addr_7) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_ADDR_7_MASK) | (roq_addr_7 << MH_DEBUG_REG38_ROQ_ADDR_7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg38_t { + unsigned int tc_mh_send : MH_DEBUG_REG38_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_7 : MH_DEBUG_REG38_ROQ_MARK_q_7_SIZE; + unsigned int roq_valid_q_7 : MH_DEBUG_REG38_ROQ_VALID_q_7_SIZE; + unsigned int same_row_bank_q_7 : MH_DEBUG_REG38_SAME_ROW_BANK_q_7_SIZE; + unsigned int roq_addr_7 : MH_DEBUG_REG38_ROQ_ADDR_7_SIZE; + } mh_debug_reg38_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg38_t { + unsigned int roq_addr_7 : MH_DEBUG_REG38_ROQ_ADDR_7_SIZE; + unsigned int same_row_bank_q_7 : MH_DEBUG_REG38_SAME_ROW_BANK_q_7_SIZE; + unsigned int roq_valid_q_7 : MH_DEBUG_REG38_ROQ_VALID_q_7_SIZE; + unsigned int roq_mark_q_7 : MH_DEBUG_REG38_ROQ_MARK_q_7_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG38_TC_MH_send_SIZE; + } mh_debug_reg38_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg38_t f; +} mh_debug_reg38_u; + + +/* + * MH_DEBUG_REG39 struct + */ + +#define MH_DEBUG_REG39_ARB_WE_SIZE 1 +#define MH_DEBUG_REG39_MMU_RTR_SIZE 1 +#define MH_DEBUG_REG39_ARB_ID_q_SIZE 3 +#define MH_DEBUG_REG39_ARB_WRITE_q_SIZE 1 +#define MH_DEBUG_REG39_ARB_BLEN_q_SIZE 1 +#define MH_DEBUG_REG39_ARQ_CTRL_EMPTY_SIZE 1 +#define MH_DEBUG_REG39_ARQ_FIFO_CNT_q_SIZE 3 +#define MH_DEBUG_REG39_MMU_WE_SIZE 1 +#define MH_DEBUG_REG39_ARQ_RTR_SIZE 1 +#define MH_DEBUG_REG39_MMU_ID_SIZE 3 +#define MH_DEBUG_REG39_MMU_WRITE_SIZE 1 +#define MH_DEBUG_REG39_MMU_BLEN_SIZE 1 + +#define MH_DEBUG_REG39_ARB_WE_SHIFT 0 +#define MH_DEBUG_REG39_MMU_RTR_SHIFT 1 +#define MH_DEBUG_REG39_ARB_ID_q_SHIFT 2 +#define MH_DEBUG_REG39_ARB_WRITE_q_SHIFT 5 +#define MH_DEBUG_REG39_ARB_BLEN_q_SHIFT 6 +#define MH_DEBUG_REG39_ARQ_CTRL_EMPTY_SHIFT 7 +#define MH_DEBUG_REG39_ARQ_FIFO_CNT_q_SHIFT 8 +#define MH_DEBUG_REG39_MMU_WE_SHIFT 11 +#define MH_DEBUG_REG39_ARQ_RTR_SHIFT 12 +#define MH_DEBUG_REG39_MMU_ID_SHIFT 13 +#define MH_DEBUG_REG39_MMU_WRITE_SHIFT 16 +#define MH_DEBUG_REG39_MMU_BLEN_SHIFT 17 + +#define MH_DEBUG_REG39_ARB_WE_MASK 0x00000001 +#define MH_DEBUG_REG39_MMU_RTR_MASK 0x00000002 +#define MH_DEBUG_REG39_ARB_ID_q_MASK 0x0000001c +#define MH_DEBUG_REG39_ARB_WRITE_q_MASK 0x00000020 +#define MH_DEBUG_REG39_ARB_BLEN_q_MASK 0x00000040 +#define MH_DEBUG_REG39_ARQ_CTRL_EMPTY_MASK 0x00000080 +#define MH_DEBUG_REG39_ARQ_FIFO_CNT_q_MASK 0x00000700 +#define MH_DEBUG_REG39_MMU_WE_MASK 0x00000800 +#define MH_DEBUG_REG39_ARQ_RTR_MASK 0x00001000 +#define MH_DEBUG_REG39_MMU_ID_MASK 0x0000e000 +#define MH_DEBUG_REG39_MMU_WRITE_MASK 0x00010000 +#define MH_DEBUG_REG39_MMU_BLEN_MASK 0x00020000 + +#define MH_DEBUG_REG39_MASK \ + (MH_DEBUG_REG39_ARB_WE_MASK | \ + MH_DEBUG_REG39_MMU_RTR_MASK | \ + MH_DEBUG_REG39_ARB_ID_q_MASK | \ + MH_DEBUG_REG39_ARB_WRITE_q_MASK | \ + MH_DEBUG_REG39_ARB_BLEN_q_MASK | \ + MH_DEBUG_REG39_ARQ_CTRL_EMPTY_MASK | \ + MH_DEBUG_REG39_ARQ_FIFO_CNT_q_MASK | \ + MH_DEBUG_REG39_MMU_WE_MASK | \ + MH_DEBUG_REG39_ARQ_RTR_MASK | \ + MH_DEBUG_REG39_MMU_ID_MASK | \ + MH_DEBUG_REG39_MMU_WRITE_MASK | \ + MH_DEBUG_REG39_MMU_BLEN_MASK) + +#define MH_DEBUG_REG39(arb_we, mmu_rtr, arb_id_q, arb_write_q, arb_blen_q, arq_ctrl_empty, arq_fifo_cnt_q, mmu_we, arq_rtr, mmu_id, mmu_write, mmu_blen) \ + ((arb_we << MH_DEBUG_REG39_ARB_WE_SHIFT) | \ + (mmu_rtr << MH_DEBUG_REG39_MMU_RTR_SHIFT) | \ + (arb_id_q << MH_DEBUG_REG39_ARB_ID_q_SHIFT) | \ + (arb_write_q << MH_DEBUG_REG39_ARB_WRITE_q_SHIFT) | \ + (arb_blen_q << MH_DEBUG_REG39_ARB_BLEN_q_SHIFT) | \ + (arq_ctrl_empty << MH_DEBUG_REG39_ARQ_CTRL_EMPTY_SHIFT) | \ + (arq_fifo_cnt_q << MH_DEBUG_REG39_ARQ_FIFO_CNT_q_SHIFT) | \ + (mmu_we << MH_DEBUG_REG39_MMU_WE_SHIFT) | \ + (arq_rtr << MH_DEBUG_REG39_ARQ_RTR_SHIFT) | \ + (mmu_id << MH_DEBUG_REG39_MMU_ID_SHIFT) | \ + (mmu_write << MH_DEBUG_REG39_MMU_WRITE_SHIFT) | \ + (mmu_blen << MH_DEBUG_REG39_MMU_BLEN_SHIFT)) + +#define MH_DEBUG_REG39_GET_ARB_WE(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_ARB_WE_MASK) >> MH_DEBUG_REG39_ARB_WE_SHIFT) +#define MH_DEBUG_REG39_GET_MMU_RTR(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_MMU_RTR_MASK) >> MH_DEBUG_REG39_MMU_RTR_SHIFT) +#define MH_DEBUG_REG39_GET_ARB_ID_q(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_ARB_ID_q_MASK) >> MH_DEBUG_REG39_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG39_GET_ARB_WRITE_q(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_ARB_WRITE_q_MASK) >> MH_DEBUG_REG39_ARB_WRITE_q_SHIFT) +#define MH_DEBUG_REG39_GET_ARB_BLEN_q(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_ARB_BLEN_q_MASK) >> MH_DEBUG_REG39_ARB_BLEN_q_SHIFT) +#define MH_DEBUG_REG39_GET_ARQ_CTRL_EMPTY(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_ARQ_CTRL_EMPTY_MASK) >> MH_DEBUG_REG39_ARQ_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG39_GET_ARQ_FIFO_CNT_q(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_ARQ_FIFO_CNT_q_MASK) >> MH_DEBUG_REG39_ARQ_FIFO_CNT_q_SHIFT) +#define MH_DEBUG_REG39_GET_MMU_WE(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_MMU_WE_MASK) >> MH_DEBUG_REG39_MMU_WE_SHIFT) +#define MH_DEBUG_REG39_GET_ARQ_RTR(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_ARQ_RTR_MASK) >> MH_DEBUG_REG39_ARQ_RTR_SHIFT) +#define MH_DEBUG_REG39_GET_MMU_ID(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_MMU_ID_MASK) >> MH_DEBUG_REG39_MMU_ID_SHIFT) +#define MH_DEBUG_REG39_GET_MMU_WRITE(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_MMU_WRITE_MASK) >> MH_DEBUG_REG39_MMU_WRITE_SHIFT) +#define MH_DEBUG_REG39_GET_MMU_BLEN(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_MMU_BLEN_MASK) >> MH_DEBUG_REG39_MMU_BLEN_SHIFT) + +#define MH_DEBUG_REG39_SET_ARB_WE(mh_debug_reg39_reg, arb_we) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG39_ARB_WE_SHIFT) +#define MH_DEBUG_REG39_SET_MMU_RTR(mh_debug_reg39_reg, mmu_rtr) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_MMU_RTR_MASK) | (mmu_rtr << MH_DEBUG_REG39_MMU_RTR_SHIFT) +#define MH_DEBUG_REG39_SET_ARB_ID_q(mh_debug_reg39_reg, arb_id_q) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG39_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG39_SET_ARB_WRITE_q(mh_debug_reg39_reg, arb_write_q) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ARB_WRITE_q_MASK) | (arb_write_q << MH_DEBUG_REG39_ARB_WRITE_q_SHIFT) +#define MH_DEBUG_REG39_SET_ARB_BLEN_q(mh_debug_reg39_reg, arb_blen_q) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ARB_BLEN_q_MASK) | (arb_blen_q << MH_DEBUG_REG39_ARB_BLEN_q_SHIFT) +#define MH_DEBUG_REG39_SET_ARQ_CTRL_EMPTY(mh_debug_reg39_reg, arq_ctrl_empty) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ARQ_CTRL_EMPTY_MASK) | (arq_ctrl_empty << MH_DEBUG_REG39_ARQ_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG39_SET_ARQ_FIFO_CNT_q(mh_debug_reg39_reg, arq_fifo_cnt_q) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ARQ_FIFO_CNT_q_MASK) | (arq_fifo_cnt_q << MH_DEBUG_REG39_ARQ_FIFO_CNT_q_SHIFT) +#define MH_DEBUG_REG39_SET_MMU_WE(mh_debug_reg39_reg, mmu_we) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG39_MMU_WE_SHIFT) +#define MH_DEBUG_REG39_SET_ARQ_RTR(mh_debug_reg39_reg, arq_rtr) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ARQ_RTR_MASK) | (arq_rtr << MH_DEBUG_REG39_ARQ_RTR_SHIFT) +#define MH_DEBUG_REG39_SET_MMU_ID(mh_debug_reg39_reg, mmu_id) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_MMU_ID_MASK) | (mmu_id << MH_DEBUG_REG39_MMU_ID_SHIFT) +#define MH_DEBUG_REG39_SET_MMU_WRITE(mh_debug_reg39_reg, mmu_write) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_MMU_WRITE_MASK) | (mmu_write << MH_DEBUG_REG39_MMU_WRITE_SHIFT) +#define MH_DEBUG_REG39_SET_MMU_BLEN(mh_debug_reg39_reg, mmu_blen) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_MMU_BLEN_MASK) | (mmu_blen << MH_DEBUG_REG39_MMU_BLEN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg39_t { + unsigned int arb_we : MH_DEBUG_REG39_ARB_WE_SIZE; + unsigned int mmu_rtr : MH_DEBUG_REG39_MMU_RTR_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG39_ARB_ID_q_SIZE; + unsigned int arb_write_q : MH_DEBUG_REG39_ARB_WRITE_q_SIZE; + unsigned int arb_blen_q : MH_DEBUG_REG39_ARB_BLEN_q_SIZE; + unsigned int arq_ctrl_empty : MH_DEBUG_REG39_ARQ_CTRL_EMPTY_SIZE; + unsigned int arq_fifo_cnt_q : MH_DEBUG_REG39_ARQ_FIFO_CNT_q_SIZE; + unsigned int mmu_we : MH_DEBUG_REG39_MMU_WE_SIZE; + unsigned int arq_rtr : MH_DEBUG_REG39_ARQ_RTR_SIZE; + unsigned int mmu_id : MH_DEBUG_REG39_MMU_ID_SIZE; + unsigned int mmu_write : MH_DEBUG_REG39_MMU_WRITE_SIZE; + unsigned int mmu_blen : MH_DEBUG_REG39_MMU_BLEN_SIZE; + unsigned int : 14; + } mh_debug_reg39_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg39_t { + unsigned int : 14; + unsigned int mmu_blen : MH_DEBUG_REG39_MMU_BLEN_SIZE; + unsigned int mmu_write : MH_DEBUG_REG39_MMU_WRITE_SIZE; + unsigned int mmu_id : MH_DEBUG_REG39_MMU_ID_SIZE; + unsigned int arq_rtr : MH_DEBUG_REG39_ARQ_RTR_SIZE; + unsigned int mmu_we : MH_DEBUG_REG39_MMU_WE_SIZE; + unsigned int arq_fifo_cnt_q : MH_DEBUG_REG39_ARQ_FIFO_CNT_q_SIZE; + unsigned int arq_ctrl_empty : MH_DEBUG_REG39_ARQ_CTRL_EMPTY_SIZE; + unsigned int arb_blen_q : MH_DEBUG_REG39_ARB_BLEN_q_SIZE; + unsigned int arb_write_q : MH_DEBUG_REG39_ARB_WRITE_q_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG39_ARB_ID_q_SIZE; + unsigned int mmu_rtr : MH_DEBUG_REG39_MMU_RTR_SIZE; + unsigned int arb_we : MH_DEBUG_REG39_ARB_WE_SIZE; + } mh_debug_reg39_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg39_t f; +} mh_debug_reg39_u; + + +/* + * MH_DEBUG_REG40 struct + */ + +#define MH_DEBUG_REG40_ARB_WE_SIZE 1 +#define MH_DEBUG_REG40_ARB_ID_q_SIZE 3 +#define MH_DEBUG_REG40_ARB_VAD_q_SIZE 28 + +#define MH_DEBUG_REG40_ARB_WE_SHIFT 0 +#define MH_DEBUG_REG40_ARB_ID_q_SHIFT 1 +#define MH_DEBUG_REG40_ARB_VAD_q_SHIFT 4 + +#define MH_DEBUG_REG40_ARB_WE_MASK 0x00000001 +#define MH_DEBUG_REG40_ARB_ID_q_MASK 0x0000000e +#define MH_DEBUG_REG40_ARB_VAD_q_MASK 0xfffffff0 + +#define MH_DEBUG_REG40_MASK \ + (MH_DEBUG_REG40_ARB_WE_MASK | \ + MH_DEBUG_REG40_ARB_ID_q_MASK | \ + MH_DEBUG_REG40_ARB_VAD_q_MASK) + +#define MH_DEBUG_REG40(arb_we, arb_id_q, arb_vad_q) \ + ((arb_we << MH_DEBUG_REG40_ARB_WE_SHIFT) | \ + (arb_id_q << MH_DEBUG_REG40_ARB_ID_q_SHIFT) | \ + (arb_vad_q << MH_DEBUG_REG40_ARB_VAD_q_SHIFT)) + +#define MH_DEBUG_REG40_GET_ARB_WE(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_ARB_WE_MASK) >> MH_DEBUG_REG40_ARB_WE_SHIFT) +#define MH_DEBUG_REG40_GET_ARB_ID_q(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_ARB_ID_q_MASK) >> MH_DEBUG_REG40_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG40_GET_ARB_VAD_q(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_ARB_VAD_q_MASK) >> MH_DEBUG_REG40_ARB_VAD_q_SHIFT) + +#define MH_DEBUG_REG40_SET_ARB_WE(mh_debug_reg40_reg, arb_we) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG40_ARB_WE_SHIFT) +#define MH_DEBUG_REG40_SET_ARB_ID_q(mh_debug_reg40_reg, arb_id_q) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG40_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG40_SET_ARB_VAD_q(mh_debug_reg40_reg, arb_vad_q) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ARB_VAD_q_MASK) | (arb_vad_q << MH_DEBUG_REG40_ARB_VAD_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg40_t { + unsigned int arb_we : MH_DEBUG_REG40_ARB_WE_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG40_ARB_ID_q_SIZE; + unsigned int arb_vad_q : MH_DEBUG_REG40_ARB_VAD_q_SIZE; + } mh_debug_reg40_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg40_t { + unsigned int arb_vad_q : MH_DEBUG_REG40_ARB_VAD_q_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG40_ARB_ID_q_SIZE; + unsigned int arb_we : MH_DEBUG_REG40_ARB_WE_SIZE; + } mh_debug_reg40_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg40_t f; +} mh_debug_reg40_u; + + +/* + * MH_DEBUG_REG41 struct + */ + +#define MH_DEBUG_REG41_MMU_WE_SIZE 1 +#define MH_DEBUG_REG41_MMU_ID_SIZE 3 +#define MH_DEBUG_REG41_MMU_PAD_SIZE 28 + +#define MH_DEBUG_REG41_MMU_WE_SHIFT 0 +#define MH_DEBUG_REG41_MMU_ID_SHIFT 1 +#define MH_DEBUG_REG41_MMU_PAD_SHIFT 4 + +#define MH_DEBUG_REG41_MMU_WE_MASK 0x00000001 +#define MH_DEBUG_REG41_MMU_ID_MASK 0x0000000e +#define MH_DEBUG_REG41_MMU_PAD_MASK 0xfffffff0 + +#define MH_DEBUG_REG41_MASK \ + (MH_DEBUG_REG41_MMU_WE_MASK | \ + MH_DEBUG_REG41_MMU_ID_MASK | \ + MH_DEBUG_REG41_MMU_PAD_MASK) + +#define MH_DEBUG_REG41(mmu_we, mmu_id, mmu_pad) \ + ((mmu_we << MH_DEBUG_REG41_MMU_WE_SHIFT) | \ + (mmu_id << MH_DEBUG_REG41_MMU_ID_SHIFT) | \ + (mmu_pad << MH_DEBUG_REG41_MMU_PAD_SHIFT)) + +#define MH_DEBUG_REG41_GET_MMU_WE(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_MMU_WE_MASK) >> MH_DEBUG_REG41_MMU_WE_SHIFT) +#define MH_DEBUG_REG41_GET_MMU_ID(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_MMU_ID_MASK) >> MH_DEBUG_REG41_MMU_ID_SHIFT) +#define MH_DEBUG_REG41_GET_MMU_PAD(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_MMU_PAD_MASK) >> MH_DEBUG_REG41_MMU_PAD_SHIFT) + +#define MH_DEBUG_REG41_SET_MMU_WE(mh_debug_reg41_reg, mmu_we) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG41_MMU_WE_SHIFT) +#define MH_DEBUG_REG41_SET_MMU_ID(mh_debug_reg41_reg, mmu_id) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_MMU_ID_MASK) | (mmu_id << MH_DEBUG_REG41_MMU_ID_SHIFT) +#define MH_DEBUG_REG41_SET_MMU_PAD(mh_debug_reg41_reg, mmu_pad) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_MMU_PAD_MASK) | (mmu_pad << MH_DEBUG_REG41_MMU_PAD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg41_t { + unsigned int mmu_we : MH_DEBUG_REG41_MMU_WE_SIZE; + unsigned int mmu_id : MH_DEBUG_REG41_MMU_ID_SIZE; + unsigned int mmu_pad : MH_DEBUG_REG41_MMU_PAD_SIZE; + } mh_debug_reg41_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg41_t { + unsigned int mmu_pad : MH_DEBUG_REG41_MMU_PAD_SIZE; + unsigned int mmu_id : MH_DEBUG_REG41_MMU_ID_SIZE; + unsigned int mmu_we : MH_DEBUG_REG41_MMU_WE_SIZE; + } mh_debug_reg41_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg41_t f; +} mh_debug_reg41_u; + + +/* + * MH_DEBUG_REG42 struct + */ + +#define MH_DEBUG_REG42_WDB_WE_SIZE 1 +#define MH_DEBUG_REG42_WDB_RTR_SKID_SIZE 1 +#define MH_DEBUG_REG42_ARB_WSTRB_q_SIZE 8 +#define MH_DEBUG_REG42_ARB_WLAST_SIZE 1 +#define MH_DEBUG_REG42_WDB_CTRL_EMPTY_SIZE 1 +#define MH_DEBUG_REG42_WDB_FIFO_CNT_q_SIZE 5 +#define MH_DEBUG_REG42_WDC_WDB_RE_q_SIZE 1 +#define MH_DEBUG_REG42_WDB_WDC_WID_SIZE 3 +#define MH_DEBUG_REG42_WDB_WDC_WLAST_SIZE 1 +#define MH_DEBUG_REG42_WDB_WDC_WSTRB_SIZE 8 + +#define MH_DEBUG_REG42_WDB_WE_SHIFT 0 +#define MH_DEBUG_REG42_WDB_RTR_SKID_SHIFT 1 +#define MH_DEBUG_REG42_ARB_WSTRB_q_SHIFT 2 +#define MH_DEBUG_REG42_ARB_WLAST_SHIFT 10 +#define MH_DEBUG_REG42_WDB_CTRL_EMPTY_SHIFT 11 +#define MH_DEBUG_REG42_WDB_FIFO_CNT_q_SHIFT 12 +#define MH_DEBUG_REG42_WDC_WDB_RE_q_SHIFT 17 +#define MH_DEBUG_REG42_WDB_WDC_WID_SHIFT 18 +#define MH_DEBUG_REG42_WDB_WDC_WLAST_SHIFT 21 +#define MH_DEBUG_REG42_WDB_WDC_WSTRB_SHIFT 22 + +#define MH_DEBUG_REG42_WDB_WE_MASK 0x00000001 +#define MH_DEBUG_REG42_WDB_RTR_SKID_MASK 0x00000002 +#define MH_DEBUG_REG42_ARB_WSTRB_q_MASK 0x000003fc +#define MH_DEBUG_REG42_ARB_WLAST_MASK 0x00000400 +#define MH_DEBUG_REG42_WDB_CTRL_EMPTY_MASK 0x00000800 +#define MH_DEBUG_REG42_WDB_FIFO_CNT_q_MASK 0x0001f000 +#define MH_DEBUG_REG42_WDC_WDB_RE_q_MASK 0x00020000 +#define MH_DEBUG_REG42_WDB_WDC_WID_MASK 0x001c0000 +#define MH_DEBUG_REG42_WDB_WDC_WLAST_MASK 0x00200000 +#define MH_DEBUG_REG42_WDB_WDC_WSTRB_MASK 0x3fc00000 + +#define MH_DEBUG_REG42_MASK \ + (MH_DEBUG_REG42_WDB_WE_MASK | \ + MH_DEBUG_REG42_WDB_RTR_SKID_MASK | \ + MH_DEBUG_REG42_ARB_WSTRB_q_MASK | \ + MH_DEBUG_REG42_ARB_WLAST_MASK | \ + MH_DEBUG_REG42_WDB_CTRL_EMPTY_MASK | \ + MH_DEBUG_REG42_WDB_FIFO_CNT_q_MASK | \ + MH_DEBUG_REG42_WDC_WDB_RE_q_MASK | \ + MH_DEBUG_REG42_WDB_WDC_WID_MASK | \ + MH_DEBUG_REG42_WDB_WDC_WLAST_MASK | \ + MH_DEBUG_REG42_WDB_WDC_WSTRB_MASK) + +#define MH_DEBUG_REG42(wdb_we, wdb_rtr_skid, arb_wstrb_q, arb_wlast, wdb_ctrl_empty, wdb_fifo_cnt_q, wdc_wdb_re_q, wdb_wdc_wid, wdb_wdc_wlast, wdb_wdc_wstrb) \ + ((wdb_we << MH_DEBUG_REG42_WDB_WE_SHIFT) | \ + (wdb_rtr_skid << MH_DEBUG_REG42_WDB_RTR_SKID_SHIFT) | \ + (arb_wstrb_q << MH_DEBUG_REG42_ARB_WSTRB_q_SHIFT) | \ + (arb_wlast << MH_DEBUG_REG42_ARB_WLAST_SHIFT) | \ + (wdb_ctrl_empty << MH_DEBUG_REG42_WDB_CTRL_EMPTY_SHIFT) | \ + (wdb_fifo_cnt_q << MH_DEBUG_REG42_WDB_FIFO_CNT_q_SHIFT) | \ + (wdc_wdb_re_q << MH_DEBUG_REG42_WDC_WDB_RE_q_SHIFT) | \ + (wdb_wdc_wid << MH_DEBUG_REG42_WDB_WDC_WID_SHIFT) | \ + (wdb_wdc_wlast << MH_DEBUG_REG42_WDB_WDC_WLAST_SHIFT) | \ + (wdb_wdc_wstrb << MH_DEBUG_REG42_WDB_WDC_WSTRB_SHIFT)) + +#define MH_DEBUG_REG42_GET_WDB_WE(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_WDB_WE_MASK) >> MH_DEBUG_REG42_WDB_WE_SHIFT) +#define MH_DEBUG_REG42_GET_WDB_RTR_SKID(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_WDB_RTR_SKID_MASK) >> MH_DEBUG_REG42_WDB_RTR_SKID_SHIFT) +#define MH_DEBUG_REG42_GET_ARB_WSTRB_q(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_ARB_WSTRB_q_MASK) >> MH_DEBUG_REG42_ARB_WSTRB_q_SHIFT) +#define MH_DEBUG_REG42_GET_ARB_WLAST(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_ARB_WLAST_MASK) >> MH_DEBUG_REG42_ARB_WLAST_SHIFT) +#define MH_DEBUG_REG42_GET_WDB_CTRL_EMPTY(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_WDB_CTRL_EMPTY_MASK) >> MH_DEBUG_REG42_WDB_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG42_GET_WDB_FIFO_CNT_q(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_WDB_FIFO_CNT_q_MASK) >> MH_DEBUG_REG42_WDB_FIFO_CNT_q_SHIFT) +#define MH_DEBUG_REG42_GET_WDC_WDB_RE_q(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_WDC_WDB_RE_q_MASK) >> MH_DEBUG_REG42_WDC_WDB_RE_q_SHIFT) +#define MH_DEBUG_REG42_GET_WDB_WDC_WID(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_WDB_WDC_WID_MASK) >> MH_DEBUG_REG42_WDB_WDC_WID_SHIFT) +#define MH_DEBUG_REG42_GET_WDB_WDC_WLAST(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_WDB_WDC_WLAST_MASK) >> MH_DEBUG_REG42_WDB_WDC_WLAST_SHIFT) +#define MH_DEBUG_REG42_GET_WDB_WDC_WSTRB(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_WDB_WDC_WSTRB_MASK) >> MH_DEBUG_REG42_WDB_WDC_WSTRB_SHIFT) + +#define MH_DEBUG_REG42_SET_WDB_WE(mh_debug_reg42_reg, wdb_we) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDB_WE_MASK) | (wdb_we << MH_DEBUG_REG42_WDB_WE_SHIFT) +#define MH_DEBUG_REG42_SET_WDB_RTR_SKID(mh_debug_reg42_reg, wdb_rtr_skid) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDB_RTR_SKID_MASK) | (wdb_rtr_skid << MH_DEBUG_REG42_WDB_RTR_SKID_SHIFT) +#define MH_DEBUG_REG42_SET_ARB_WSTRB_q(mh_debug_reg42_reg, arb_wstrb_q) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ARB_WSTRB_q_MASK) | (arb_wstrb_q << MH_DEBUG_REG42_ARB_WSTRB_q_SHIFT) +#define MH_DEBUG_REG42_SET_ARB_WLAST(mh_debug_reg42_reg, arb_wlast) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ARB_WLAST_MASK) | (arb_wlast << MH_DEBUG_REG42_ARB_WLAST_SHIFT) +#define MH_DEBUG_REG42_SET_WDB_CTRL_EMPTY(mh_debug_reg42_reg, wdb_ctrl_empty) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDB_CTRL_EMPTY_MASK) | (wdb_ctrl_empty << MH_DEBUG_REG42_WDB_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG42_SET_WDB_FIFO_CNT_q(mh_debug_reg42_reg, wdb_fifo_cnt_q) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDB_FIFO_CNT_q_MASK) | (wdb_fifo_cnt_q << MH_DEBUG_REG42_WDB_FIFO_CNT_q_SHIFT) +#define MH_DEBUG_REG42_SET_WDC_WDB_RE_q(mh_debug_reg42_reg, wdc_wdb_re_q) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDC_WDB_RE_q_MASK) | (wdc_wdb_re_q << MH_DEBUG_REG42_WDC_WDB_RE_q_SHIFT) +#define MH_DEBUG_REG42_SET_WDB_WDC_WID(mh_debug_reg42_reg, wdb_wdc_wid) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDB_WDC_WID_MASK) | (wdb_wdc_wid << MH_DEBUG_REG42_WDB_WDC_WID_SHIFT) +#define MH_DEBUG_REG42_SET_WDB_WDC_WLAST(mh_debug_reg42_reg, wdb_wdc_wlast) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDB_WDC_WLAST_MASK) | (wdb_wdc_wlast << MH_DEBUG_REG42_WDB_WDC_WLAST_SHIFT) +#define MH_DEBUG_REG42_SET_WDB_WDC_WSTRB(mh_debug_reg42_reg, wdb_wdc_wstrb) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_WDB_WDC_WSTRB_MASK) | (wdb_wdc_wstrb << MH_DEBUG_REG42_WDB_WDC_WSTRB_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg42_t { + unsigned int wdb_we : MH_DEBUG_REG42_WDB_WE_SIZE; + unsigned int wdb_rtr_skid : MH_DEBUG_REG42_WDB_RTR_SKID_SIZE; + unsigned int arb_wstrb_q : MH_DEBUG_REG42_ARB_WSTRB_q_SIZE; + unsigned int arb_wlast : MH_DEBUG_REG42_ARB_WLAST_SIZE; + unsigned int wdb_ctrl_empty : MH_DEBUG_REG42_WDB_CTRL_EMPTY_SIZE; + unsigned int wdb_fifo_cnt_q : MH_DEBUG_REG42_WDB_FIFO_CNT_q_SIZE; + unsigned int wdc_wdb_re_q : MH_DEBUG_REG42_WDC_WDB_RE_q_SIZE; + unsigned int wdb_wdc_wid : MH_DEBUG_REG42_WDB_WDC_WID_SIZE; + unsigned int wdb_wdc_wlast : MH_DEBUG_REG42_WDB_WDC_WLAST_SIZE; + unsigned int wdb_wdc_wstrb : MH_DEBUG_REG42_WDB_WDC_WSTRB_SIZE; + unsigned int : 2; + } mh_debug_reg42_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg42_t { + unsigned int : 2; + unsigned int wdb_wdc_wstrb : MH_DEBUG_REG42_WDB_WDC_WSTRB_SIZE; + unsigned int wdb_wdc_wlast : MH_DEBUG_REG42_WDB_WDC_WLAST_SIZE; + unsigned int wdb_wdc_wid : MH_DEBUG_REG42_WDB_WDC_WID_SIZE; + unsigned int wdc_wdb_re_q : MH_DEBUG_REG42_WDC_WDB_RE_q_SIZE; + unsigned int wdb_fifo_cnt_q : MH_DEBUG_REG42_WDB_FIFO_CNT_q_SIZE; + unsigned int wdb_ctrl_empty : MH_DEBUG_REG42_WDB_CTRL_EMPTY_SIZE; + unsigned int arb_wlast : MH_DEBUG_REG42_ARB_WLAST_SIZE; + unsigned int arb_wstrb_q : MH_DEBUG_REG42_ARB_WSTRB_q_SIZE; + unsigned int wdb_rtr_skid : MH_DEBUG_REG42_WDB_RTR_SKID_SIZE; + unsigned int wdb_we : MH_DEBUG_REG42_WDB_WE_SIZE; + } mh_debug_reg42_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg42_t f; +} mh_debug_reg42_u; + + +/* + * MH_DEBUG_REG43 struct + */ + +#define MH_DEBUG_REG43_ARB_WDATA_q_31_0_SIZE 32 + +#define MH_DEBUG_REG43_ARB_WDATA_q_31_0_SHIFT 0 + +#define MH_DEBUG_REG43_ARB_WDATA_q_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG43_MASK \ + (MH_DEBUG_REG43_ARB_WDATA_q_31_0_MASK) + +#define MH_DEBUG_REG43(arb_wdata_q_31_0) \ + ((arb_wdata_q_31_0 << MH_DEBUG_REG43_ARB_WDATA_q_31_0_SHIFT)) + +#define MH_DEBUG_REG43_GET_ARB_WDATA_q_31_0(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_WDATA_q_31_0_MASK) >> MH_DEBUG_REG43_ARB_WDATA_q_31_0_SHIFT) + +#define MH_DEBUG_REG43_SET_ARB_WDATA_q_31_0(mh_debug_reg43_reg, arb_wdata_q_31_0) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_WDATA_q_31_0_MASK) | (arb_wdata_q_31_0 << MH_DEBUG_REG43_ARB_WDATA_q_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg43_t { + unsigned int arb_wdata_q_31_0 : MH_DEBUG_REG43_ARB_WDATA_q_31_0_SIZE; + } mh_debug_reg43_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg43_t { + unsigned int arb_wdata_q_31_0 : MH_DEBUG_REG43_ARB_WDATA_q_31_0_SIZE; + } mh_debug_reg43_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg43_t f; +} mh_debug_reg43_u; + + +/* + * MH_DEBUG_REG44 struct + */ + +#define MH_DEBUG_REG44_ARB_WDATA_q_63_32_SIZE 32 + +#define MH_DEBUG_REG44_ARB_WDATA_q_63_32_SHIFT 0 + +#define MH_DEBUG_REG44_ARB_WDATA_q_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG44_MASK \ + (MH_DEBUG_REG44_ARB_WDATA_q_63_32_MASK) + +#define MH_DEBUG_REG44(arb_wdata_q_63_32) \ + ((arb_wdata_q_63_32 << MH_DEBUG_REG44_ARB_WDATA_q_63_32_SHIFT)) + +#define MH_DEBUG_REG44_GET_ARB_WDATA_q_63_32(mh_debug_reg44) \ + ((mh_debug_reg44 & MH_DEBUG_REG44_ARB_WDATA_q_63_32_MASK) >> MH_DEBUG_REG44_ARB_WDATA_q_63_32_SHIFT) + +#define MH_DEBUG_REG44_SET_ARB_WDATA_q_63_32(mh_debug_reg44_reg, arb_wdata_q_63_32) \ + mh_debug_reg44_reg = (mh_debug_reg44_reg & ~MH_DEBUG_REG44_ARB_WDATA_q_63_32_MASK) | (arb_wdata_q_63_32 << MH_DEBUG_REG44_ARB_WDATA_q_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg44_t { + unsigned int arb_wdata_q_63_32 : MH_DEBUG_REG44_ARB_WDATA_q_63_32_SIZE; + } mh_debug_reg44_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg44_t { + unsigned int arb_wdata_q_63_32 : MH_DEBUG_REG44_ARB_WDATA_q_63_32_SIZE; + } mh_debug_reg44_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg44_t f; +} mh_debug_reg44_u; + + +/* + * MH_DEBUG_REG45 struct + */ + +#define MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_SIZE 32 + +#define MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_SHIFT 0 + +#define MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG45_MASK \ + (MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_MASK) + +#define MH_DEBUG_REG45(wdb_wdc_wdata_31_0) \ + ((wdb_wdc_wdata_31_0 << MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_SHIFT)) + +#define MH_DEBUG_REG45_GET_WDB_WDC_WDATA_31_0(mh_debug_reg45) \ + ((mh_debug_reg45 & MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_MASK) >> MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_SHIFT) + +#define MH_DEBUG_REG45_SET_WDB_WDC_WDATA_31_0(mh_debug_reg45_reg, wdb_wdc_wdata_31_0) \ + mh_debug_reg45_reg = (mh_debug_reg45_reg & ~MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_MASK) | (wdb_wdc_wdata_31_0 << MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg45_t { + unsigned int wdb_wdc_wdata_31_0 : MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_SIZE; + } mh_debug_reg45_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg45_t { + unsigned int wdb_wdc_wdata_31_0 : MH_DEBUG_REG45_WDB_WDC_WDATA_31_0_SIZE; + } mh_debug_reg45_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg45_t f; +} mh_debug_reg45_u; + + +/* + * MH_DEBUG_REG46 struct + */ + +#define MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_SIZE 32 + +#define MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_SHIFT 0 + +#define MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG46_MASK \ + (MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_MASK) + +#define MH_DEBUG_REG46(wdb_wdc_wdata_63_32) \ + ((wdb_wdc_wdata_63_32 << MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_SHIFT)) + +#define MH_DEBUG_REG46_GET_WDB_WDC_WDATA_63_32(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_MASK) >> MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_SHIFT) + +#define MH_DEBUG_REG46_SET_WDB_WDC_WDATA_63_32(mh_debug_reg46_reg, wdb_wdc_wdata_63_32) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_MASK) | (wdb_wdc_wdata_63_32 << MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg46_t { + unsigned int wdb_wdc_wdata_63_32 : MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_SIZE; + } mh_debug_reg46_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg46_t { + unsigned int wdb_wdc_wdata_63_32 : MH_DEBUG_REG46_WDB_WDC_WDATA_63_32_SIZE; + } mh_debug_reg46_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg46_t f; +} mh_debug_reg46_u; + + +/* + * MH_DEBUG_REG47 struct + */ + +#define MH_DEBUG_REG47_CTRL_ARC_EMPTY_SIZE 1 +#define MH_DEBUG_REG47_CTRL_RARC_EMPTY_SIZE 1 +#define MH_DEBUG_REG47_ARQ_CTRL_EMPTY_SIZE 1 +#define MH_DEBUG_REG47_ARQ_CTRL_WRITE_SIZE 1 +#define MH_DEBUG_REG47_TLBMISS_CTRL_RTS_SIZE 1 +#define MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_SIZE 1 +#define MH_DEBUG_REG47_INFLT_LIMIT_q_SIZE 1 +#define MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_SIZE 6 +#define MH_DEBUG_REG47_ARC_CTRL_RE_q_SIZE 1 +#define MH_DEBUG_REG47_RARC_CTRL_RE_q_SIZE 1 +#define MH_DEBUG_REG47_RVALID_q_SIZE 1 +#define MH_DEBUG_REG47_RREADY_q_SIZE 1 +#define MH_DEBUG_REG47_RLAST_q_SIZE 1 +#define MH_DEBUG_REG47_BVALID_q_SIZE 1 +#define MH_DEBUG_REG47_BREADY_q_SIZE 1 + +#define MH_DEBUG_REG47_CTRL_ARC_EMPTY_SHIFT 0 +#define MH_DEBUG_REG47_CTRL_RARC_EMPTY_SHIFT 1 +#define MH_DEBUG_REG47_ARQ_CTRL_EMPTY_SHIFT 2 +#define MH_DEBUG_REG47_ARQ_CTRL_WRITE_SHIFT 3 +#define MH_DEBUG_REG47_TLBMISS_CTRL_RTS_SHIFT 4 +#define MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_SHIFT 5 +#define MH_DEBUG_REG47_INFLT_LIMIT_q_SHIFT 6 +#define MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_SHIFT 7 +#define MH_DEBUG_REG47_ARC_CTRL_RE_q_SHIFT 13 +#define MH_DEBUG_REG47_RARC_CTRL_RE_q_SHIFT 14 +#define MH_DEBUG_REG47_RVALID_q_SHIFT 15 +#define MH_DEBUG_REG47_RREADY_q_SHIFT 16 +#define MH_DEBUG_REG47_RLAST_q_SHIFT 17 +#define MH_DEBUG_REG47_BVALID_q_SHIFT 18 +#define MH_DEBUG_REG47_BREADY_q_SHIFT 19 + +#define MH_DEBUG_REG47_CTRL_ARC_EMPTY_MASK 0x00000001 +#define MH_DEBUG_REG47_CTRL_RARC_EMPTY_MASK 0x00000002 +#define MH_DEBUG_REG47_ARQ_CTRL_EMPTY_MASK 0x00000004 +#define MH_DEBUG_REG47_ARQ_CTRL_WRITE_MASK 0x00000008 +#define MH_DEBUG_REG47_TLBMISS_CTRL_RTS_MASK 0x00000010 +#define MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_MASK 0x00000020 +#define MH_DEBUG_REG47_INFLT_LIMIT_q_MASK 0x00000040 +#define MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_MASK 0x00001f80 +#define MH_DEBUG_REG47_ARC_CTRL_RE_q_MASK 0x00002000 +#define MH_DEBUG_REG47_RARC_CTRL_RE_q_MASK 0x00004000 +#define MH_DEBUG_REG47_RVALID_q_MASK 0x00008000 +#define MH_DEBUG_REG47_RREADY_q_MASK 0x00010000 +#define MH_DEBUG_REG47_RLAST_q_MASK 0x00020000 +#define MH_DEBUG_REG47_BVALID_q_MASK 0x00040000 +#define MH_DEBUG_REG47_BREADY_q_MASK 0x00080000 + +#define MH_DEBUG_REG47_MASK \ + (MH_DEBUG_REG47_CTRL_ARC_EMPTY_MASK | \ + MH_DEBUG_REG47_CTRL_RARC_EMPTY_MASK | \ + MH_DEBUG_REG47_ARQ_CTRL_EMPTY_MASK | \ + MH_DEBUG_REG47_ARQ_CTRL_WRITE_MASK | \ + MH_DEBUG_REG47_TLBMISS_CTRL_RTS_MASK | \ + MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_MASK | \ + MH_DEBUG_REG47_INFLT_LIMIT_q_MASK | \ + MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_MASK | \ + MH_DEBUG_REG47_ARC_CTRL_RE_q_MASK | \ + MH_DEBUG_REG47_RARC_CTRL_RE_q_MASK | \ + MH_DEBUG_REG47_RVALID_q_MASK | \ + MH_DEBUG_REG47_RREADY_q_MASK | \ + MH_DEBUG_REG47_RLAST_q_MASK | \ + MH_DEBUG_REG47_BVALID_q_MASK | \ + MH_DEBUG_REG47_BREADY_q_MASK) + +#define MH_DEBUG_REG47(ctrl_arc_empty, ctrl_rarc_empty, arq_ctrl_empty, arq_ctrl_write, tlbmiss_ctrl_rts, ctrl_tlbmiss_re_q, inflt_limit_q, inflt_limit_cnt_q, arc_ctrl_re_q, rarc_ctrl_re_q, rvalid_q, rready_q, rlast_q, bvalid_q, bready_q) \ + ((ctrl_arc_empty << MH_DEBUG_REG47_CTRL_ARC_EMPTY_SHIFT) | \ + (ctrl_rarc_empty << MH_DEBUG_REG47_CTRL_RARC_EMPTY_SHIFT) | \ + (arq_ctrl_empty << MH_DEBUG_REG47_ARQ_CTRL_EMPTY_SHIFT) | \ + (arq_ctrl_write << MH_DEBUG_REG47_ARQ_CTRL_WRITE_SHIFT) | \ + (tlbmiss_ctrl_rts << MH_DEBUG_REG47_TLBMISS_CTRL_RTS_SHIFT) | \ + (ctrl_tlbmiss_re_q << MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_SHIFT) | \ + (inflt_limit_q << MH_DEBUG_REG47_INFLT_LIMIT_q_SHIFT) | \ + (inflt_limit_cnt_q << MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_SHIFT) | \ + (arc_ctrl_re_q << MH_DEBUG_REG47_ARC_CTRL_RE_q_SHIFT) | \ + (rarc_ctrl_re_q << MH_DEBUG_REG47_RARC_CTRL_RE_q_SHIFT) | \ + (rvalid_q << MH_DEBUG_REG47_RVALID_q_SHIFT) | \ + (rready_q << MH_DEBUG_REG47_RREADY_q_SHIFT) | \ + (rlast_q << MH_DEBUG_REG47_RLAST_q_SHIFT) | \ + (bvalid_q << MH_DEBUG_REG47_BVALID_q_SHIFT) | \ + (bready_q << MH_DEBUG_REG47_BREADY_q_SHIFT)) + +#define MH_DEBUG_REG47_GET_CTRL_ARC_EMPTY(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_CTRL_ARC_EMPTY_MASK) >> MH_DEBUG_REG47_CTRL_ARC_EMPTY_SHIFT) +#define MH_DEBUG_REG47_GET_CTRL_RARC_EMPTY(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_CTRL_RARC_EMPTY_MASK) >> MH_DEBUG_REG47_CTRL_RARC_EMPTY_SHIFT) +#define MH_DEBUG_REG47_GET_ARQ_CTRL_EMPTY(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_ARQ_CTRL_EMPTY_MASK) >> MH_DEBUG_REG47_ARQ_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG47_GET_ARQ_CTRL_WRITE(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_ARQ_CTRL_WRITE_MASK) >> MH_DEBUG_REG47_ARQ_CTRL_WRITE_SHIFT) +#define MH_DEBUG_REG47_GET_TLBMISS_CTRL_RTS(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG47_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG47_GET_CTRL_TLBMISS_RE_q(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG47_GET_INFLT_LIMIT_q(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_INFLT_LIMIT_q_MASK) >> MH_DEBUG_REG47_INFLT_LIMIT_q_SHIFT) +#define MH_DEBUG_REG47_GET_INFLT_LIMIT_CNT_q(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_MASK) >> MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_SHIFT) +#define MH_DEBUG_REG47_GET_ARC_CTRL_RE_q(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_ARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG47_ARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG47_GET_RARC_CTRL_RE_q(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_RARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG47_RARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG47_GET_RVALID_q(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_RVALID_q_MASK) >> MH_DEBUG_REG47_RVALID_q_SHIFT) +#define MH_DEBUG_REG47_GET_RREADY_q(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_RREADY_q_MASK) >> MH_DEBUG_REG47_RREADY_q_SHIFT) +#define MH_DEBUG_REG47_GET_RLAST_q(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_RLAST_q_MASK) >> MH_DEBUG_REG47_RLAST_q_SHIFT) +#define MH_DEBUG_REG47_GET_BVALID_q(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_BVALID_q_MASK) >> MH_DEBUG_REG47_BVALID_q_SHIFT) +#define MH_DEBUG_REG47_GET_BREADY_q(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_BREADY_q_MASK) >> MH_DEBUG_REG47_BREADY_q_SHIFT) + +#define MH_DEBUG_REG47_SET_CTRL_ARC_EMPTY(mh_debug_reg47_reg, ctrl_arc_empty) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_CTRL_ARC_EMPTY_MASK) | (ctrl_arc_empty << MH_DEBUG_REG47_CTRL_ARC_EMPTY_SHIFT) +#define MH_DEBUG_REG47_SET_CTRL_RARC_EMPTY(mh_debug_reg47_reg, ctrl_rarc_empty) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_CTRL_RARC_EMPTY_MASK) | (ctrl_rarc_empty << MH_DEBUG_REG47_CTRL_RARC_EMPTY_SHIFT) +#define MH_DEBUG_REG47_SET_ARQ_CTRL_EMPTY(mh_debug_reg47_reg, arq_ctrl_empty) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_ARQ_CTRL_EMPTY_MASK) | (arq_ctrl_empty << MH_DEBUG_REG47_ARQ_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG47_SET_ARQ_CTRL_WRITE(mh_debug_reg47_reg, arq_ctrl_write) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_ARQ_CTRL_WRITE_MASK) | (arq_ctrl_write << MH_DEBUG_REG47_ARQ_CTRL_WRITE_SHIFT) +#define MH_DEBUG_REG47_SET_TLBMISS_CTRL_RTS(mh_debug_reg47_reg, tlbmiss_ctrl_rts) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG47_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG47_SET_CTRL_TLBMISS_RE_q(mh_debug_reg47_reg, ctrl_tlbmiss_re_q) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG47_SET_INFLT_LIMIT_q(mh_debug_reg47_reg, inflt_limit_q) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_INFLT_LIMIT_q_MASK) | (inflt_limit_q << MH_DEBUG_REG47_INFLT_LIMIT_q_SHIFT) +#define MH_DEBUG_REG47_SET_INFLT_LIMIT_CNT_q(mh_debug_reg47_reg, inflt_limit_cnt_q) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_MASK) | (inflt_limit_cnt_q << MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_SHIFT) +#define MH_DEBUG_REG47_SET_ARC_CTRL_RE_q(mh_debug_reg47_reg, arc_ctrl_re_q) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_ARC_CTRL_RE_q_MASK) | (arc_ctrl_re_q << MH_DEBUG_REG47_ARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG47_SET_RARC_CTRL_RE_q(mh_debug_reg47_reg, rarc_ctrl_re_q) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_RARC_CTRL_RE_q_MASK) | (rarc_ctrl_re_q << MH_DEBUG_REG47_RARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG47_SET_RVALID_q(mh_debug_reg47_reg, rvalid_q) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_RVALID_q_MASK) | (rvalid_q << MH_DEBUG_REG47_RVALID_q_SHIFT) +#define MH_DEBUG_REG47_SET_RREADY_q(mh_debug_reg47_reg, rready_q) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_RREADY_q_MASK) | (rready_q << MH_DEBUG_REG47_RREADY_q_SHIFT) +#define MH_DEBUG_REG47_SET_RLAST_q(mh_debug_reg47_reg, rlast_q) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_RLAST_q_MASK) | (rlast_q << MH_DEBUG_REG47_RLAST_q_SHIFT) +#define MH_DEBUG_REG47_SET_BVALID_q(mh_debug_reg47_reg, bvalid_q) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG47_BVALID_q_SHIFT) +#define MH_DEBUG_REG47_SET_BREADY_q(mh_debug_reg47_reg, bready_q) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG47_BREADY_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg47_t { + unsigned int ctrl_arc_empty : MH_DEBUG_REG47_CTRL_ARC_EMPTY_SIZE; + unsigned int ctrl_rarc_empty : MH_DEBUG_REG47_CTRL_RARC_EMPTY_SIZE; + unsigned int arq_ctrl_empty : MH_DEBUG_REG47_ARQ_CTRL_EMPTY_SIZE; + unsigned int arq_ctrl_write : MH_DEBUG_REG47_ARQ_CTRL_WRITE_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG47_TLBMISS_CTRL_RTS_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_SIZE; + unsigned int inflt_limit_q : MH_DEBUG_REG47_INFLT_LIMIT_q_SIZE; + unsigned int inflt_limit_cnt_q : MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_SIZE; + unsigned int arc_ctrl_re_q : MH_DEBUG_REG47_ARC_CTRL_RE_q_SIZE; + unsigned int rarc_ctrl_re_q : MH_DEBUG_REG47_RARC_CTRL_RE_q_SIZE; + unsigned int rvalid_q : MH_DEBUG_REG47_RVALID_q_SIZE; + unsigned int rready_q : MH_DEBUG_REG47_RREADY_q_SIZE; + unsigned int rlast_q : MH_DEBUG_REG47_RLAST_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG47_BVALID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG47_BREADY_q_SIZE; + unsigned int : 12; + } mh_debug_reg47_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg47_t { + unsigned int : 12; + unsigned int bready_q : MH_DEBUG_REG47_BREADY_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG47_BVALID_q_SIZE; + unsigned int rlast_q : MH_DEBUG_REG47_RLAST_q_SIZE; + unsigned int rready_q : MH_DEBUG_REG47_RREADY_q_SIZE; + unsigned int rvalid_q : MH_DEBUG_REG47_RVALID_q_SIZE; + unsigned int rarc_ctrl_re_q : MH_DEBUG_REG47_RARC_CTRL_RE_q_SIZE; + unsigned int arc_ctrl_re_q : MH_DEBUG_REG47_ARC_CTRL_RE_q_SIZE; + unsigned int inflt_limit_cnt_q : MH_DEBUG_REG47_INFLT_LIMIT_CNT_q_SIZE; + unsigned int inflt_limit_q : MH_DEBUG_REG47_INFLT_LIMIT_q_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG47_CTRL_TLBMISS_RE_q_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG47_TLBMISS_CTRL_RTS_SIZE; + unsigned int arq_ctrl_write : MH_DEBUG_REG47_ARQ_CTRL_WRITE_SIZE; + unsigned int arq_ctrl_empty : MH_DEBUG_REG47_ARQ_CTRL_EMPTY_SIZE; + unsigned int ctrl_rarc_empty : MH_DEBUG_REG47_CTRL_RARC_EMPTY_SIZE; + unsigned int ctrl_arc_empty : MH_DEBUG_REG47_CTRL_ARC_EMPTY_SIZE; + } mh_debug_reg47_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg47_t f; +} mh_debug_reg47_u; + + +/* + * MH_DEBUG_REG48 struct + */ + +#define MH_DEBUG_REG48_MH_CP_grb_send_SIZE 1 +#define MH_DEBUG_REG48_MH_VGT_grb_send_SIZE 1 +#define MH_DEBUG_REG48_MH_TC_mcsend_SIZE 1 +#define MH_DEBUG_REG48_MH_TLBMISS_SEND_SIZE 1 +#define MH_DEBUG_REG48_TLBMISS_VALID_SIZE 1 +#define MH_DEBUG_REG48_RDC_VALID_SIZE 1 +#define MH_DEBUG_REG48_RDC_RID_SIZE 3 +#define MH_DEBUG_REG48_RDC_RLAST_SIZE 1 +#define MH_DEBUG_REG48_RDC_RRESP_SIZE 2 +#define MH_DEBUG_REG48_TLBMISS_CTRL_RTS_SIZE 1 +#define MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_SIZE 1 +#define MH_DEBUG_REG48_MMU_ID_REQUEST_q_SIZE 1 +#define MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_SIZE 6 +#define MH_DEBUG_REG48_MMU_ID_RESPONSE_SIZE 1 +#define MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_SIZE 6 +#define MH_DEBUG_REG48_CNT_HOLD_q1_SIZE 1 +#define MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3 + +#define MH_DEBUG_REG48_MH_CP_grb_send_SHIFT 0 +#define MH_DEBUG_REG48_MH_VGT_grb_send_SHIFT 1 +#define MH_DEBUG_REG48_MH_TC_mcsend_SHIFT 2 +#define MH_DEBUG_REG48_MH_TLBMISS_SEND_SHIFT 3 +#define MH_DEBUG_REG48_TLBMISS_VALID_SHIFT 4 +#define MH_DEBUG_REG48_RDC_VALID_SHIFT 5 +#define MH_DEBUG_REG48_RDC_RID_SHIFT 6 +#define MH_DEBUG_REG48_RDC_RLAST_SHIFT 9 +#define MH_DEBUG_REG48_RDC_RRESP_SHIFT 10 +#define MH_DEBUG_REG48_TLBMISS_CTRL_RTS_SHIFT 12 +#define MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_SHIFT 13 +#define MH_DEBUG_REG48_MMU_ID_REQUEST_q_SHIFT 14 +#define MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_SHIFT 15 +#define MH_DEBUG_REG48_MMU_ID_RESPONSE_SHIFT 21 +#define MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_SHIFT 22 +#define MH_DEBUG_REG48_CNT_HOLD_q1_SHIFT 28 +#define MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 29 + +#define MH_DEBUG_REG48_MH_CP_grb_send_MASK 0x00000001 +#define MH_DEBUG_REG48_MH_VGT_grb_send_MASK 0x00000002 +#define MH_DEBUG_REG48_MH_TC_mcsend_MASK 0x00000004 +#define MH_DEBUG_REG48_MH_TLBMISS_SEND_MASK 0x00000008 +#define MH_DEBUG_REG48_TLBMISS_VALID_MASK 0x00000010 +#define MH_DEBUG_REG48_RDC_VALID_MASK 0x00000020 +#define MH_DEBUG_REG48_RDC_RID_MASK 0x000001c0 +#define MH_DEBUG_REG48_RDC_RLAST_MASK 0x00000200 +#define MH_DEBUG_REG48_RDC_RRESP_MASK 0x00000c00 +#define MH_DEBUG_REG48_TLBMISS_CTRL_RTS_MASK 0x00001000 +#define MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_MASK 0x00002000 +#define MH_DEBUG_REG48_MMU_ID_REQUEST_q_MASK 0x00004000 +#define MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_MASK 0x001f8000 +#define MH_DEBUG_REG48_MMU_ID_RESPONSE_MASK 0x00200000 +#define MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_MASK 0x0fc00000 +#define MH_DEBUG_REG48_CNT_HOLD_q1_MASK 0x10000000 +#define MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0xe0000000 + +#define MH_DEBUG_REG48_MASK \ + (MH_DEBUG_REG48_MH_CP_grb_send_MASK | \ + MH_DEBUG_REG48_MH_VGT_grb_send_MASK | \ + MH_DEBUG_REG48_MH_TC_mcsend_MASK | \ + MH_DEBUG_REG48_MH_TLBMISS_SEND_MASK | \ + MH_DEBUG_REG48_TLBMISS_VALID_MASK | \ + MH_DEBUG_REG48_RDC_VALID_MASK | \ + MH_DEBUG_REG48_RDC_RID_MASK | \ + MH_DEBUG_REG48_RDC_RLAST_MASK | \ + MH_DEBUG_REG48_RDC_RRESP_MASK | \ + MH_DEBUG_REG48_TLBMISS_CTRL_RTS_MASK | \ + MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_MASK | \ + MH_DEBUG_REG48_MMU_ID_REQUEST_q_MASK | \ + MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_MASK | \ + MH_DEBUG_REG48_MMU_ID_RESPONSE_MASK | \ + MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_MASK | \ + MH_DEBUG_REG48_CNT_HOLD_q1_MASK | \ + MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) + +#define MH_DEBUG_REG48(mh_cp_grb_send, mh_vgt_grb_send, mh_tc_mcsend, mh_tlbmiss_send, tlbmiss_valid, rdc_valid, rdc_rid, rdc_rlast, rdc_rresp, tlbmiss_ctrl_rts, ctrl_tlbmiss_re_q, mmu_id_request_q, outstanding_mmuid_cnt_q, mmu_id_response, tlbmiss_return_cnt_q, cnt_hold_q1, mh_clnt_axi_id_reuse_mmur_id) \ + ((mh_cp_grb_send << MH_DEBUG_REG48_MH_CP_grb_send_SHIFT) | \ + (mh_vgt_grb_send << MH_DEBUG_REG48_MH_VGT_grb_send_SHIFT) | \ + (mh_tc_mcsend << MH_DEBUG_REG48_MH_TC_mcsend_SHIFT) | \ + (mh_tlbmiss_send << MH_DEBUG_REG48_MH_TLBMISS_SEND_SHIFT) | \ + (tlbmiss_valid << MH_DEBUG_REG48_TLBMISS_VALID_SHIFT) | \ + (rdc_valid << MH_DEBUG_REG48_RDC_VALID_SHIFT) | \ + (rdc_rid << MH_DEBUG_REG48_RDC_RID_SHIFT) | \ + (rdc_rlast << MH_DEBUG_REG48_RDC_RLAST_SHIFT) | \ + (rdc_rresp << MH_DEBUG_REG48_RDC_RRESP_SHIFT) | \ + (tlbmiss_ctrl_rts << MH_DEBUG_REG48_TLBMISS_CTRL_RTS_SHIFT) | \ + (ctrl_tlbmiss_re_q << MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_SHIFT) | \ + (mmu_id_request_q << MH_DEBUG_REG48_MMU_ID_REQUEST_q_SHIFT) | \ + (outstanding_mmuid_cnt_q << MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_SHIFT) | \ + (mmu_id_response << MH_DEBUG_REG48_MMU_ID_RESPONSE_SHIFT) | \ + (tlbmiss_return_cnt_q << MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_SHIFT) | \ + (cnt_hold_q1 << MH_DEBUG_REG48_CNT_HOLD_q1_SHIFT) | \ + (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)) + +#define MH_DEBUG_REG48_GET_MH_CP_grb_send(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_MH_CP_grb_send_MASK) >> MH_DEBUG_REG48_MH_CP_grb_send_SHIFT) +#define MH_DEBUG_REG48_GET_MH_VGT_grb_send(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_MH_VGT_grb_send_MASK) >> MH_DEBUG_REG48_MH_VGT_grb_send_SHIFT) +#define MH_DEBUG_REG48_GET_MH_TC_mcsend(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_MH_TC_mcsend_MASK) >> MH_DEBUG_REG48_MH_TC_mcsend_SHIFT) +#define MH_DEBUG_REG48_GET_MH_TLBMISS_SEND(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_MH_TLBMISS_SEND_MASK) >> MH_DEBUG_REG48_MH_TLBMISS_SEND_SHIFT) +#define MH_DEBUG_REG48_GET_TLBMISS_VALID(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_TLBMISS_VALID_MASK) >> MH_DEBUG_REG48_TLBMISS_VALID_SHIFT) +#define MH_DEBUG_REG48_GET_RDC_VALID(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_RDC_VALID_MASK) >> MH_DEBUG_REG48_RDC_VALID_SHIFT) +#define MH_DEBUG_REG48_GET_RDC_RID(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_RDC_RID_MASK) >> MH_DEBUG_REG48_RDC_RID_SHIFT) +#define MH_DEBUG_REG48_GET_RDC_RLAST(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_RDC_RLAST_MASK) >> MH_DEBUG_REG48_RDC_RLAST_SHIFT) +#define MH_DEBUG_REG48_GET_RDC_RRESP(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_RDC_RRESP_MASK) >> MH_DEBUG_REG48_RDC_RRESP_SHIFT) +#define MH_DEBUG_REG48_GET_TLBMISS_CTRL_RTS(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG48_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG48_GET_CTRL_TLBMISS_RE_q(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG48_GET_MMU_ID_REQUEST_q(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_MMU_ID_REQUEST_q_MASK) >> MH_DEBUG_REG48_MMU_ID_REQUEST_q_SHIFT) +#define MH_DEBUG_REG48_GET_OUTSTANDING_MMUID_CNT_q(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_MASK) >> MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_SHIFT) +#define MH_DEBUG_REG48_GET_MMU_ID_RESPONSE(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_MMU_ID_RESPONSE_MASK) >> MH_DEBUG_REG48_MMU_ID_RESPONSE_SHIFT) +#define MH_DEBUG_REG48_GET_TLBMISS_RETURN_CNT_q(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_MASK) >> MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_SHIFT) +#define MH_DEBUG_REG48_GET_CNT_HOLD_q1(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_CNT_HOLD_q1_MASK) >> MH_DEBUG_REG48_CNT_HOLD_q1_SHIFT) +#define MH_DEBUG_REG48_GET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) + +#define MH_DEBUG_REG48_SET_MH_CP_grb_send(mh_debug_reg48_reg, mh_cp_grb_send) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_MH_CP_grb_send_MASK) | (mh_cp_grb_send << MH_DEBUG_REG48_MH_CP_grb_send_SHIFT) +#define MH_DEBUG_REG48_SET_MH_VGT_grb_send(mh_debug_reg48_reg, mh_vgt_grb_send) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_MH_VGT_grb_send_MASK) | (mh_vgt_grb_send << MH_DEBUG_REG48_MH_VGT_grb_send_SHIFT) +#define MH_DEBUG_REG48_SET_MH_TC_mcsend(mh_debug_reg48_reg, mh_tc_mcsend) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_MH_TC_mcsend_MASK) | (mh_tc_mcsend << MH_DEBUG_REG48_MH_TC_mcsend_SHIFT) +#define MH_DEBUG_REG48_SET_MH_TLBMISS_SEND(mh_debug_reg48_reg, mh_tlbmiss_send) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_MH_TLBMISS_SEND_MASK) | (mh_tlbmiss_send << MH_DEBUG_REG48_MH_TLBMISS_SEND_SHIFT) +#define MH_DEBUG_REG48_SET_TLBMISS_VALID(mh_debug_reg48_reg, tlbmiss_valid) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_TLBMISS_VALID_MASK) | (tlbmiss_valid << MH_DEBUG_REG48_TLBMISS_VALID_SHIFT) +#define MH_DEBUG_REG48_SET_RDC_VALID(mh_debug_reg48_reg, rdc_valid) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_RDC_VALID_MASK) | (rdc_valid << MH_DEBUG_REG48_RDC_VALID_SHIFT) +#define MH_DEBUG_REG48_SET_RDC_RID(mh_debug_reg48_reg, rdc_rid) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_RDC_RID_MASK) | (rdc_rid << MH_DEBUG_REG48_RDC_RID_SHIFT) +#define MH_DEBUG_REG48_SET_RDC_RLAST(mh_debug_reg48_reg, rdc_rlast) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_RDC_RLAST_MASK) | (rdc_rlast << MH_DEBUG_REG48_RDC_RLAST_SHIFT) +#define MH_DEBUG_REG48_SET_RDC_RRESP(mh_debug_reg48_reg, rdc_rresp) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_RDC_RRESP_MASK) | (rdc_rresp << MH_DEBUG_REG48_RDC_RRESP_SHIFT) +#define MH_DEBUG_REG48_SET_TLBMISS_CTRL_RTS(mh_debug_reg48_reg, tlbmiss_ctrl_rts) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG48_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG48_SET_CTRL_TLBMISS_RE_q(mh_debug_reg48_reg, ctrl_tlbmiss_re_q) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG48_SET_MMU_ID_REQUEST_q(mh_debug_reg48_reg, mmu_id_request_q) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_MMU_ID_REQUEST_q_MASK) | (mmu_id_request_q << MH_DEBUG_REG48_MMU_ID_REQUEST_q_SHIFT) +#define MH_DEBUG_REG48_SET_OUTSTANDING_MMUID_CNT_q(mh_debug_reg48_reg, outstanding_mmuid_cnt_q) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_MASK) | (outstanding_mmuid_cnt_q << MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_SHIFT) +#define MH_DEBUG_REG48_SET_MMU_ID_RESPONSE(mh_debug_reg48_reg, mmu_id_response) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_MMU_ID_RESPONSE_MASK) | (mmu_id_response << MH_DEBUG_REG48_MMU_ID_RESPONSE_SHIFT) +#define MH_DEBUG_REG48_SET_TLBMISS_RETURN_CNT_q(mh_debug_reg48_reg, tlbmiss_return_cnt_q) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_MASK) | (tlbmiss_return_cnt_q << MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_SHIFT) +#define MH_DEBUG_REG48_SET_CNT_HOLD_q1(mh_debug_reg48_reg, cnt_hold_q1) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_CNT_HOLD_q1_MASK) | (cnt_hold_q1 << MH_DEBUG_REG48_CNT_HOLD_q1_SHIFT) +#define MH_DEBUG_REG48_SET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg48_reg, mh_clnt_axi_id_reuse_mmur_id) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg48_t { + unsigned int mh_cp_grb_send : MH_DEBUG_REG48_MH_CP_grb_send_SIZE; + unsigned int mh_vgt_grb_send : MH_DEBUG_REG48_MH_VGT_grb_send_SIZE; + unsigned int mh_tc_mcsend : MH_DEBUG_REG48_MH_TC_mcsend_SIZE; + unsigned int mh_tlbmiss_send : MH_DEBUG_REG48_MH_TLBMISS_SEND_SIZE; + unsigned int tlbmiss_valid : MH_DEBUG_REG48_TLBMISS_VALID_SIZE; + unsigned int rdc_valid : MH_DEBUG_REG48_RDC_VALID_SIZE; + unsigned int rdc_rid : MH_DEBUG_REG48_RDC_RID_SIZE; + unsigned int rdc_rlast : MH_DEBUG_REG48_RDC_RLAST_SIZE; + unsigned int rdc_rresp : MH_DEBUG_REG48_RDC_RRESP_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG48_TLBMISS_CTRL_RTS_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_SIZE; + unsigned int mmu_id_request_q : MH_DEBUG_REG48_MMU_ID_REQUEST_q_SIZE; + unsigned int outstanding_mmuid_cnt_q : MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_SIZE; + unsigned int mmu_id_response : MH_DEBUG_REG48_MMU_ID_RESPONSE_SIZE; + unsigned int tlbmiss_return_cnt_q : MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_SIZE; + unsigned int cnt_hold_q1 : MH_DEBUG_REG48_CNT_HOLD_q1_SIZE; + unsigned int mh_clnt_axi_id_reuse_mmur_id : MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + } mh_debug_reg48_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg48_t { + unsigned int mh_clnt_axi_id_reuse_mmur_id : MH_DEBUG_REG48_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int cnt_hold_q1 : MH_DEBUG_REG48_CNT_HOLD_q1_SIZE; + unsigned int tlbmiss_return_cnt_q : MH_DEBUG_REG48_TLBMISS_RETURN_CNT_q_SIZE; + unsigned int mmu_id_response : MH_DEBUG_REG48_MMU_ID_RESPONSE_SIZE; + unsigned int outstanding_mmuid_cnt_q : MH_DEBUG_REG48_OUTSTANDING_MMUID_CNT_q_SIZE; + unsigned int mmu_id_request_q : MH_DEBUG_REG48_MMU_ID_REQUEST_q_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG48_CTRL_TLBMISS_RE_q_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG48_TLBMISS_CTRL_RTS_SIZE; + unsigned int rdc_rresp : MH_DEBUG_REG48_RDC_RRESP_SIZE; + unsigned int rdc_rlast : MH_DEBUG_REG48_RDC_RLAST_SIZE; + unsigned int rdc_rid : MH_DEBUG_REG48_RDC_RID_SIZE; + unsigned int rdc_valid : MH_DEBUG_REG48_RDC_VALID_SIZE; + unsigned int tlbmiss_valid : MH_DEBUG_REG48_TLBMISS_VALID_SIZE; + unsigned int mh_tlbmiss_send : MH_DEBUG_REG48_MH_TLBMISS_SEND_SIZE; + unsigned int mh_tc_mcsend : MH_DEBUG_REG48_MH_TC_mcsend_SIZE; + unsigned int mh_vgt_grb_send : MH_DEBUG_REG48_MH_VGT_grb_send_SIZE; + unsigned int mh_cp_grb_send : MH_DEBUG_REG48_MH_CP_grb_send_SIZE; + } mh_debug_reg48_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg48_t f; +} mh_debug_reg48_u; + + +/* + * MH_DEBUG_REG49 struct + */ + +#define MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_SIZE 32 + +#define MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_SHIFT 0 + +#define MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_MASK 0xffffffff + +#define MH_DEBUG_REG49_MASK \ + (MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_MASK) + +#define MH_DEBUG_REG49(rf_mmu_page_fault) \ + ((rf_mmu_page_fault << MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_SHIFT)) + +#define MH_DEBUG_REG49_GET_RF_MMU_PAGE_FAULT(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_MASK) >> MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_SHIFT) + +#define MH_DEBUG_REG49_SET_RF_MMU_PAGE_FAULT(mh_debug_reg49_reg, rf_mmu_page_fault) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_MASK) | (rf_mmu_page_fault << MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg49_t { + unsigned int rf_mmu_page_fault : MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_SIZE; + } mh_debug_reg49_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg49_t { + unsigned int rf_mmu_page_fault : MH_DEBUG_REG49_RF_MMU_PAGE_FAULT_SIZE; + } mh_debug_reg49_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg49_t f; +} mh_debug_reg49_u; + + +/* + * MH_DEBUG_REG50 struct + */ + +#define MH_DEBUG_REG50_RF_MMU_CONFIG_q_SIZE 24 +#define MH_DEBUG_REG50_ARB_ID_q_SIZE 3 +#define MH_DEBUG_REG50_ARB_WRITE_q_SIZE 1 +#define MH_DEBUG_REG50_client_behavior_q_SIZE 2 +#define MH_DEBUG_REG50_ARB_WE_SIZE 1 +#define MH_DEBUG_REG50_MMU_RTR_SIZE 1 + +#define MH_DEBUG_REG50_RF_MMU_CONFIG_q_SHIFT 0 +#define MH_DEBUG_REG50_ARB_ID_q_SHIFT 24 +#define MH_DEBUG_REG50_ARB_WRITE_q_SHIFT 27 +#define MH_DEBUG_REG50_client_behavior_q_SHIFT 28 +#define MH_DEBUG_REG50_ARB_WE_SHIFT 30 +#define MH_DEBUG_REG50_MMU_RTR_SHIFT 31 + +#define MH_DEBUG_REG50_RF_MMU_CONFIG_q_MASK 0x00ffffff +#define MH_DEBUG_REG50_ARB_ID_q_MASK 0x07000000 +#define MH_DEBUG_REG50_ARB_WRITE_q_MASK 0x08000000 +#define MH_DEBUG_REG50_client_behavior_q_MASK 0x30000000 +#define MH_DEBUG_REG50_ARB_WE_MASK 0x40000000 +#define MH_DEBUG_REG50_MMU_RTR_MASK 0x80000000 + +#define MH_DEBUG_REG50_MASK \ + (MH_DEBUG_REG50_RF_MMU_CONFIG_q_MASK | \ + MH_DEBUG_REG50_ARB_ID_q_MASK | \ + MH_DEBUG_REG50_ARB_WRITE_q_MASK | \ + MH_DEBUG_REG50_client_behavior_q_MASK | \ + MH_DEBUG_REG50_ARB_WE_MASK | \ + MH_DEBUG_REG50_MMU_RTR_MASK) + +#define MH_DEBUG_REG50(rf_mmu_config_q, arb_id_q, arb_write_q, client_behavior_q, arb_we, mmu_rtr) \ + ((rf_mmu_config_q << MH_DEBUG_REG50_RF_MMU_CONFIG_q_SHIFT) | \ + (arb_id_q << MH_DEBUG_REG50_ARB_ID_q_SHIFT) | \ + (arb_write_q << MH_DEBUG_REG50_ARB_WRITE_q_SHIFT) | \ + (client_behavior_q << MH_DEBUG_REG50_client_behavior_q_SHIFT) | \ + (arb_we << MH_DEBUG_REG50_ARB_WE_SHIFT) | \ + (mmu_rtr << MH_DEBUG_REG50_MMU_RTR_SHIFT)) + +#define MH_DEBUG_REG50_GET_RF_MMU_CONFIG_q(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_RF_MMU_CONFIG_q_MASK) >> MH_DEBUG_REG50_RF_MMU_CONFIG_q_SHIFT) +#define MH_DEBUG_REG50_GET_ARB_ID_q(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_ARB_ID_q_MASK) >> MH_DEBUG_REG50_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG50_GET_ARB_WRITE_q(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_ARB_WRITE_q_MASK) >> MH_DEBUG_REG50_ARB_WRITE_q_SHIFT) +#define MH_DEBUG_REG50_GET_client_behavior_q(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_client_behavior_q_MASK) >> MH_DEBUG_REG50_client_behavior_q_SHIFT) +#define MH_DEBUG_REG50_GET_ARB_WE(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_ARB_WE_MASK) >> MH_DEBUG_REG50_ARB_WE_SHIFT) +#define MH_DEBUG_REG50_GET_MMU_RTR(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MMU_RTR_MASK) >> MH_DEBUG_REG50_MMU_RTR_SHIFT) + +#define MH_DEBUG_REG50_SET_RF_MMU_CONFIG_q(mh_debug_reg50_reg, rf_mmu_config_q) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RF_MMU_CONFIG_q_MASK) | (rf_mmu_config_q << MH_DEBUG_REG50_RF_MMU_CONFIG_q_SHIFT) +#define MH_DEBUG_REG50_SET_ARB_ID_q(mh_debug_reg50_reg, arb_id_q) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG50_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG50_SET_ARB_WRITE_q(mh_debug_reg50_reg, arb_write_q) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_ARB_WRITE_q_MASK) | (arb_write_q << MH_DEBUG_REG50_ARB_WRITE_q_SHIFT) +#define MH_DEBUG_REG50_SET_client_behavior_q(mh_debug_reg50_reg, client_behavior_q) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_client_behavior_q_MASK) | (client_behavior_q << MH_DEBUG_REG50_client_behavior_q_SHIFT) +#define MH_DEBUG_REG50_SET_ARB_WE(mh_debug_reg50_reg, arb_we) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG50_ARB_WE_SHIFT) +#define MH_DEBUG_REG50_SET_MMU_RTR(mh_debug_reg50_reg, mmu_rtr) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MMU_RTR_MASK) | (mmu_rtr << MH_DEBUG_REG50_MMU_RTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg50_t { + unsigned int rf_mmu_config_q : MH_DEBUG_REG50_RF_MMU_CONFIG_q_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG50_ARB_ID_q_SIZE; + unsigned int arb_write_q : MH_DEBUG_REG50_ARB_WRITE_q_SIZE; + unsigned int client_behavior_q : MH_DEBUG_REG50_client_behavior_q_SIZE; + unsigned int arb_we : MH_DEBUG_REG50_ARB_WE_SIZE; + unsigned int mmu_rtr : MH_DEBUG_REG50_MMU_RTR_SIZE; + } mh_debug_reg50_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg50_t { + unsigned int mmu_rtr : MH_DEBUG_REG50_MMU_RTR_SIZE; + unsigned int arb_we : MH_DEBUG_REG50_ARB_WE_SIZE; + unsigned int client_behavior_q : MH_DEBUG_REG50_client_behavior_q_SIZE; + unsigned int arb_write_q : MH_DEBUG_REG50_ARB_WRITE_q_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG50_ARB_ID_q_SIZE; + unsigned int rf_mmu_config_q : MH_DEBUG_REG50_RF_MMU_CONFIG_q_SIZE; + } mh_debug_reg50_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg50_t f; +} mh_debug_reg50_u; + + +/* + * MH_DEBUG_REG51 struct + */ + +#define MH_DEBUG_REG51_stage1_valid_SIZE 1 +#define MH_DEBUG_REG51_IGNORE_TAG_MISS_q_SIZE 1 +#define MH_DEBUG_REG51_pa_in_mpu_range_SIZE 1 +#define MH_DEBUG_REG51_tag_match_q_SIZE 1 +#define MH_DEBUG_REG51_tag_miss_q_SIZE 1 +#define MH_DEBUG_REG51_va_in_range_q_SIZE 1 +#define MH_DEBUG_REG51_MMU_MISS_SIZE 1 +#define MH_DEBUG_REG51_MMU_READ_MISS_SIZE 1 +#define MH_DEBUG_REG51_MMU_WRITE_MISS_SIZE 1 +#define MH_DEBUG_REG51_MMU_HIT_SIZE 1 +#define MH_DEBUG_REG51_MMU_READ_HIT_SIZE 1 +#define MH_DEBUG_REG51_MMU_WRITE_HIT_SIZE 1 +#define MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_SIZE 1 +#define MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_SIZE 1 +#define MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_SIZE 1 +#define MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_SIZE 1 +#define MH_DEBUG_REG51_REQ_VA_OFFSET_q_SIZE 16 + +#define MH_DEBUG_REG51_stage1_valid_SHIFT 0 +#define MH_DEBUG_REG51_IGNORE_TAG_MISS_q_SHIFT 1 +#define MH_DEBUG_REG51_pa_in_mpu_range_SHIFT 2 +#define MH_DEBUG_REG51_tag_match_q_SHIFT 3 +#define MH_DEBUG_REG51_tag_miss_q_SHIFT 4 +#define MH_DEBUG_REG51_va_in_range_q_SHIFT 5 +#define MH_DEBUG_REG51_MMU_MISS_SHIFT 6 +#define MH_DEBUG_REG51_MMU_READ_MISS_SHIFT 7 +#define MH_DEBUG_REG51_MMU_WRITE_MISS_SHIFT 8 +#define MH_DEBUG_REG51_MMU_HIT_SHIFT 9 +#define MH_DEBUG_REG51_MMU_READ_HIT_SHIFT 10 +#define MH_DEBUG_REG51_MMU_WRITE_HIT_SHIFT 11 +#define MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_SHIFT 12 +#define MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_SHIFT 13 +#define MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_SHIFT 14 +#define MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_SHIFT 15 +#define MH_DEBUG_REG51_REQ_VA_OFFSET_q_SHIFT 16 + +#define MH_DEBUG_REG51_stage1_valid_MASK 0x00000001 +#define MH_DEBUG_REG51_IGNORE_TAG_MISS_q_MASK 0x00000002 +#define MH_DEBUG_REG51_pa_in_mpu_range_MASK 0x00000004 +#define MH_DEBUG_REG51_tag_match_q_MASK 0x00000008 +#define MH_DEBUG_REG51_tag_miss_q_MASK 0x00000010 +#define MH_DEBUG_REG51_va_in_range_q_MASK 0x00000020 +#define MH_DEBUG_REG51_MMU_MISS_MASK 0x00000040 +#define MH_DEBUG_REG51_MMU_READ_MISS_MASK 0x00000080 +#define MH_DEBUG_REG51_MMU_WRITE_MISS_MASK 0x00000100 +#define MH_DEBUG_REG51_MMU_HIT_MASK 0x00000200 +#define MH_DEBUG_REG51_MMU_READ_HIT_MASK 0x00000400 +#define MH_DEBUG_REG51_MMU_WRITE_HIT_MASK 0x00000800 +#define MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_MASK 0x00001000 +#define MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_MASK 0x00002000 +#define MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_MASK 0x00004000 +#define MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_MASK 0x00008000 +#define MH_DEBUG_REG51_REQ_VA_OFFSET_q_MASK 0xffff0000 + +#define MH_DEBUG_REG51_MASK \ + (MH_DEBUG_REG51_stage1_valid_MASK | \ + MH_DEBUG_REG51_IGNORE_TAG_MISS_q_MASK | \ + MH_DEBUG_REG51_pa_in_mpu_range_MASK | \ + MH_DEBUG_REG51_tag_match_q_MASK | \ + MH_DEBUG_REG51_tag_miss_q_MASK | \ + MH_DEBUG_REG51_va_in_range_q_MASK | \ + MH_DEBUG_REG51_MMU_MISS_MASK | \ + MH_DEBUG_REG51_MMU_READ_MISS_MASK | \ + MH_DEBUG_REG51_MMU_WRITE_MISS_MASK | \ + MH_DEBUG_REG51_MMU_HIT_MASK | \ + MH_DEBUG_REG51_MMU_READ_HIT_MASK | \ + MH_DEBUG_REG51_MMU_WRITE_HIT_MASK | \ + MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_MASK | \ + MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_MASK | \ + MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_MASK | \ + MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_MASK | \ + MH_DEBUG_REG51_REQ_VA_OFFSET_q_MASK) + +#define MH_DEBUG_REG51(stage1_valid, ignore_tag_miss_q, pa_in_mpu_range, tag_match_q, tag_miss_q, va_in_range_q, mmu_miss, mmu_read_miss, mmu_write_miss, mmu_hit, mmu_read_hit, mmu_write_hit, mmu_split_mode_tc_miss, mmu_split_mode_tc_hit, mmu_split_mode_nontc_miss, mmu_split_mode_nontc_hit, req_va_offset_q) \ + ((stage1_valid << MH_DEBUG_REG51_stage1_valid_SHIFT) | \ + (ignore_tag_miss_q << MH_DEBUG_REG51_IGNORE_TAG_MISS_q_SHIFT) | \ + (pa_in_mpu_range << MH_DEBUG_REG51_pa_in_mpu_range_SHIFT) | \ + (tag_match_q << MH_DEBUG_REG51_tag_match_q_SHIFT) | \ + (tag_miss_q << MH_DEBUG_REG51_tag_miss_q_SHIFT) | \ + (va_in_range_q << MH_DEBUG_REG51_va_in_range_q_SHIFT) | \ + (mmu_miss << MH_DEBUG_REG51_MMU_MISS_SHIFT) | \ + (mmu_read_miss << MH_DEBUG_REG51_MMU_READ_MISS_SHIFT) | \ + (mmu_write_miss << MH_DEBUG_REG51_MMU_WRITE_MISS_SHIFT) | \ + (mmu_hit << MH_DEBUG_REG51_MMU_HIT_SHIFT) | \ + (mmu_read_hit << MH_DEBUG_REG51_MMU_READ_HIT_SHIFT) | \ + (mmu_write_hit << MH_DEBUG_REG51_MMU_WRITE_HIT_SHIFT) | \ + (mmu_split_mode_tc_miss << MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_SHIFT) | \ + (mmu_split_mode_tc_hit << MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_SHIFT) | \ + (mmu_split_mode_nontc_miss << MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_SHIFT) | \ + (mmu_split_mode_nontc_hit << MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_SHIFT) | \ + (req_va_offset_q << MH_DEBUG_REG51_REQ_VA_OFFSET_q_SHIFT)) + +#define MH_DEBUG_REG51_GET_stage1_valid(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_stage1_valid_MASK) >> MH_DEBUG_REG51_stage1_valid_SHIFT) +#define MH_DEBUG_REG51_GET_IGNORE_TAG_MISS_q(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_IGNORE_TAG_MISS_q_MASK) >> MH_DEBUG_REG51_IGNORE_TAG_MISS_q_SHIFT) +#define MH_DEBUG_REG51_GET_pa_in_mpu_range(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_pa_in_mpu_range_MASK) >> MH_DEBUG_REG51_pa_in_mpu_range_SHIFT) +#define MH_DEBUG_REG51_GET_tag_match_q(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_tag_match_q_MASK) >> MH_DEBUG_REG51_tag_match_q_SHIFT) +#define MH_DEBUG_REG51_GET_tag_miss_q(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_tag_miss_q_MASK) >> MH_DEBUG_REG51_tag_miss_q_SHIFT) +#define MH_DEBUG_REG51_GET_va_in_range_q(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_va_in_range_q_MASK) >> MH_DEBUG_REG51_va_in_range_q_SHIFT) +#define MH_DEBUG_REG51_GET_MMU_MISS(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_MISS_MASK) >> MH_DEBUG_REG51_MMU_MISS_SHIFT) +#define MH_DEBUG_REG51_GET_MMU_READ_MISS(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_READ_MISS_MASK) >> MH_DEBUG_REG51_MMU_READ_MISS_SHIFT) +#define MH_DEBUG_REG51_GET_MMU_WRITE_MISS(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_WRITE_MISS_MASK) >> MH_DEBUG_REG51_MMU_WRITE_MISS_SHIFT) +#define MH_DEBUG_REG51_GET_MMU_HIT(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_HIT_MASK) >> MH_DEBUG_REG51_MMU_HIT_SHIFT) +#define MH_DEBUG_REG51_GET_MMU_READ_HIT(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_READ_HIT_MASK) >> MH_DEBUG_REG51_MMU_READ_HIT_SHIFT) +#define MH_DEBUG_REG51_GET_MMU_WRITE_HIT(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_WRITE_HIT_MASK) >> MH_DEBUG_REG51_MMU_WRITE_HIT_SHIFT) +#define MH_DEBUG_REG51_GET_MMU_SPLIT_MODE_TC_MISS(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_MASK) >> MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_SHIFT) +#define MH_DEBUG_REG51_GET_MMU_SPLIT_MODE_TC_HIT(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_MASK) >> MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_SHIFT) +#define MH_DEBUG_REG51_GET_MMU_SPLIT_MODE_nonTC_MISS(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_MASK) >> MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_SHIFT) +#define MH_DEBUG_REG51_GET_MMU_SPLIT_MODE_nonTC_HIT(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_MASK) >> MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_SHIFT) +#define MH_DEBUG_REG51_GET_REQ_VA_OFFSET_q(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_REQ_VA_OFFSET_q_MASK) >> MH_DEBUG_REG51_REQ_VA_OFFSET_q_SHIFT) + +#define MH_DEBUG_REG51_SET_stage1_valid(mh_debug_reg51_reg, stage1_valid) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_stage1_valid_MASK) | (stage1_valid << MH_DEBUG_REG51_stage1_valid_SHIFT) +#define MH_DEBUG_REG51_SET_IGNORE_TAG_MISS_q(mh_debug_reg51_reg, ignore_tag_miss_q) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_IGNORE_TAG_MISS_q_MASK) | (ignore_tag_miss_q << MH_DEBUG_REG51_IGNORE_TAG_MISS_q_SHIFT) +#define MH_DEBUG_REG51_SET_pa_in_mpu_range(mh_debug_reg51_reg, pa_in_mpu_range) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_pa_in_mpu_range_MASK) | (pa_in_mpu_range << MH_DEBUG_REG51_pa_in_mpu_range_SHIFT) +#define MH_DEBUG_REG51_SET_tag_match_q(mh_debug_reg51_reg, tag_match_q) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_tag_match_q_MASK) | (tag_match_q << MH_DEBUG_REG51_tag_match_q_SHIFT) +#define MH_DEBUG_REG51_SET_tag_miss_q(mh_debug_reg51_reg, tag_miss_q) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_tag_miss_q_MASK) | (tag_miss_q << MH_DEBUG_REG51_tag_miss_q_SHIFT) +#define MH_DEBUG_REG51_SET_va_in_range_q(mh_debug_reg51_reg, va_in_range_q) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_va_in_range_q_MASK) | (va_in_range_q << MH_DEBUG_REG51_va_in_range_q_SHIFT) +#define MH_DEBUG_REG51_SET_MMU_MISS(mh_debug_reg51_reg, mmu_miss) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_MISS_MASK) | (mmu_miss << MH_DEBUG_REG51_MMU_MISS_SHIFT) +#define MH_DEBUG_REG51_SET_MMU_READ_MISS(mh_debug_reg51_reg, mmu_read_miss) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_READ_MISS_MASK) | (mmu_read_miss << MH_DEBUG_REG51_MMU_READ_MISS_SHIFT) +#define MH_DEBUG_REG51_SET_MMU_WRITE_MISS(mh_debug_reg51_reg, mmu_write_miss) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_WRITE_MISS_MASK) | (mmu_write_miss << MH_DEBUG_REG51_MMU_WRITE_MISS_SHIFT) +#define MH_DEBUG_REG51_SET_MMU_HIT(mh_debug_reg51_reg, mmu_hit) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_HIT_MASK) | (mmu_hit << MH_DEBUG_REG51_MMU_HIT_SHIFT) +#define MH_DEBUG_REG51_SET_MMU_READ_HIT(mh_debug_reg51_reg, mmu_read_hit) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_READ_HIT_MASK) | (mmu_read_hit << MH_DEBUG_REG51_MMU_READ_HIT_SHIFT) +#define MH_DEBUG_REG51_SET_MMU_WRITE_HIT(mh_debug_reg51_reg, mmu_write_hit) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_WRITE_HIT_MASK) | (mmu_write_hit << MH_DEBUG_REG51_MMU_WRITE_HIT_SHIFT) +#define MH_DEBUG_REG51_SET_MMU_SPLIT_MODE_TC_MISS(mh_debug_reg51_reg, mmu_split_mode_tc_miss) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_MASK) | (mmu_split_mode_tc_miss << MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_SHIFT) +#define MH_DEBUG_REG51_SET_MMU_SPLIT_MODE_TC_HIT(mh_debug_reg51_reg, mmu_split_mode_tc_hit) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_MASK) | (mmu_split_mode_tc_hit << MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_SHIFT) +#define MH_DEBUG_REG51_SET_MMU_SPLIT_MODE_nonTC_MISS(mh_debug_reg51_reg, mmu_split_mode_nontc_miss) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_MASK) | (mmu_split_mode_nontc_miss << MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_SHIFT) +#define MH_DEBUG_REG51_SET_MMU_SPLIT_MODE_nonTC_HIT(mh_debug_reg51_reg, mmu_split_mode_nontc_hit) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_MASK) | (mmu_split_mode_nontc_hit << MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_SHIFT) +#define MH_DEBUG_REG51_SET_REQ_VA_OFFSET_q(mh_debug_reg51_reg, req_va_offset_q) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_REQ_VA_OFFSET_q_MASK) | (req_va_offset_q << MH_DEBUG_REG51_REQ_VA_OFFSET_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg51_t { + unsigned int stage1_valid : MH_DEBUG_REG51_stage1_valid_SIZE; + unsigned int ignore_tag_miss_q : MH_DEBUG_REG51_IGNORE_TAG_MISS_q_SIZE; + unsigned int pa_in_mpu_range : MH_DEBUG_REG51_pa_in_mpu_range_SIZE; + unsigned int tag_match_q : MH_DEBUG_REG51_tag_match_q_SIZE; + unsigned int tag_miss_q : MH_DEBUG_REG51_tag_miss_q_SIZE; + unsigned int va_in_range_q : MH_DEBUG_REG51_va_in_range_q_SIZE; + unsigned int mmu_miss : MH_DEBUG_REG51_MMU_MISS_SIZE; + unsigned int mmu_read_miss : MH_DEBUG_REG51_MMU_READ_MISS_SIZE; + unsigned int mmu_write_miss : MH_DEBUG_REG51_MMU_WRITE_MISS_SIZE; + unsigned int mmu_hit : MH_DEBUG_REG51_MMU_HIT_SIZE; + unsigned int mmu_read_hit : MH_DEBUG_REG51_MMU_READ_HIT_SIZE; + unsigned int mmu_write_hit : MH_DEBUG_REG51_MMU_WRITE_HIT_SIZE; + unsigned int mmu_split_mode_tc_miss : MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_SIZE; + unsigned int mmu_split_mode_tc_hit : MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_SIZE; + unsigned int mmu_split_mode_nontc_miss : MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_SIZE; + unsigned int mmu_split_mode_nontc_hit : MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_SIZE; + unsigned int req_va_offset_q : MH_DEBUG_REG51_REQ_VA_OFFSET_q_SIZE; + } mh_debug_reg51_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg51_t { + unsigned int req_va_offset_q : MH_DEBUG_REG51_REQ_VA_OFFSET_q_SIZE; + unsigned int mmu_split_mode_nontc_hit : MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_HIT_SIZE; + unsigned int mmu_split_mode_nontc_miss : MH_DEBUG_REG51_MMU_SPLIT_MODE_nonTC_MISS_SIZE; + unsigned int mmu_split_mode_tc_hit : MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_HIT_SIZE; + unsigned int mmu_split_mode_tc_miss : MH_DEBUG_REG51_MMU_SPLIT_MODE_TC_MISS_SIZE; + unsigned int mmu_write_hit : MH_DEBUG_REG51_MMU_WRITE_HIT_SIZE; + unsigned int mmu_read_hit : MH_DEBUG_REG51_MMU_READ_HIT_SIZE; + unsigned int mmu_hit : MH_DEBUG_REG51_MMU_HIT_SIZE; + unsigned int mmu_write_miss : MH_DEBUG_REG51_MMU_WRITE_MISS_SIZE; + unsigned int mmu_read_miss : MH_DEBUG_REG51_MMU_READ_MISS_SIZE; + unsigned int mmu_miss : MH_DEBUG_REG51_MMU_MISS_SIZE; + unsigned int va_in_range_q : MH_DEBUG_REG51_va_in_range_q_SIZE; + unsigned int tag_miss_q : MH_DEBUG_REG51_tag_miss_q_SIZE; + unsigned int tag_match_q : MH_DEBUG_REG51_tag_match_q_SIZE; + unsigned int pa_in_mpu_range : MH_DEBUG_REG51_pa_in_mpu_range_SIZE; + unsigned int ignore_tag_miss_q : MH_DEBUG_REG51_IGNORE_TAG_MISS_q_SIZE; + unsigned int stage1_valid : MH_DEBUG_REG51_stage1_valid_SIZE; + } mh_debug_reg51_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg51_t f; +} mh_debug_reg51_u; + + +/* + * MH_DEBUG_REG52 struct + */ + +#define MH_DEBUG_REG52_ARQ_RTR_SIZE 1 +#define MH_DEBUG_REG52_MMU_WE_SIZE 1 +#define MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_SIZE 1 +#define MH_DEBUG_REG52_TLBMISS_CTRL_RTS_SIZE 1 +#define MH_DEBUG_REG52_MH_TLBMISS_SEND_SIZE 1 +#define MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE 1 +#define MH_DEBUG_REG52_pa_in_mpu_range_SIZE 1 +#define MH_DEBUG_REG52_stage1_valid_SIZE 1 +#define MH_DEBUG_REG52_stage2_valid_SIZE 1 +#define MH_DEBUG_REG52_client_behavior_q_SIZE 2 +#define MH_DEBUG_REG52_IGNORE_TAG_MISS_q_SIZE 1 +#define MH_DEBUG_REG52_tag_match_q_SIZE 1 +#define MH_DEBUG_REG52_tag_miss_q_SIZE 1 +#define MH_DEBUG_REG52_va_in_range_q_SIZE 1 +#define MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_SIZE 1 +#define MH_DEBUG_REG52_TAG_valid_q_SIZE 16 + +#define MH_DEBUG_REG52_ARQ_RTR_SHIFT 0 +#define MH_DEBUG_REG52_MMU_WE_SHIFT 1 +#define MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_SHIFT 2 +#define MH_DEBUG_REG52_TLBMISS_CTRL_RTS_SHIFT 3 +#define MH_DEBUG_REG52_MH_TLBMISS_SEND_SHIFT 4 +#define MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT 5 +#define MH_DEBUG_REG52_pa_in_mpu_range_SHIFT 6 +#define MH_DEBUG_REG52_stage1_valid_SHIFT 7 +#define MH_DEBUG_REG52_stage2_valid_SHIFT 8 +#define MH_DEBUG_REG52_client_behavior_q_SHIFT 9 +#define MH_DEBUG_REG52_IGNORE_TAG_MISS_q_SHIFT 11 +#define MH_DEBUG_REG52_tag_match_q_SHIFT 12 +#define MH_DEBUG_REG52_tag_miss_q_SHIFT 13 +#define MH_DEBUG_REG52_va_in_range_q_SHIFT 14 +#define MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_SHIFT 15 +#define MH_DEBUG_REG52_TAG_valid_q_SHIFT 16 + +#define MH_DEBUG_REG52_ARQ_RTR_MASK 0x00000001 +#define MH_DEBUG_REG52_MMU_WE_MASK 0x00000002 +#define MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_MASK 0x00000004 +#define MH_DEBUG_REG52_TLBMISS_CTRL_RTS_MASK 0x00000008 +#define MH_DEBUG_REG52_MH_TLBMISS_SEND_MASK 0x00000010 +#define MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK 0x00000020 +#define MH_DEBUG_REG52_pa_in_mpu_range_MASK 0x00000040 +#define MH_DEBUG_REG52_stage1_valid_MASK 0x00000080 +#define MH_DEBUG_REG52_stage2_valid_MASK 0x00000100 +#define MH_DEBUG_REG52_client_behavior_q_MASK 0x00000600 +#define MH_DEBUG_REG52_IGNORE_TAG_MISS_q_MASK 0x00000800 +#define MH_DEBUG_REG52_tag_match_q_MASK 0x00001000 +#define MH_DEBUG_REG52_tag_miss_q_MASK 0x00002000 +#define MH_DEBUG_REG52_va_in_range_q_MASK 0x00004000 +#define MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_MASK 0x00008000 +#define MH_DEBUG_REG52_TAG_valid_q_MASK 0xffff0000 + +#define MH_DEBUG_REG52_MASK \ + (MH_DEBUG_REG52_ARQ_RTR_MASK | \ + MH_DEBUG_REG52_MMU_WE_MASK | \ + MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_MASK | \ + MH_DEBUG_REG52_TLBMISS_CTRL_RTS_MASK | \ + MH_DEBUG_REG52_MH_TLBMISS_SEND_MASK | \ + MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK | \ + MH_DEBUG_REG52_pa_in_mpu_range_MASK | \ + MH_DEBUG_REG52_stage1_valid_MASK | \ + MH_DEBUG_REG52_stage2_valid_MASK | \ + MH_DEBUG_REG52_client_behavior_q_MASK | \ + MH_DEBUG_REG52_IGNORE_TAG_MISS_q_MASK | \ + MH_DEBUG_REG52_tag_match_q_MASK | \ + MH_DEBUG_REG52_tag_miss_q_MASK | \ + MH_DEBUG_REG52_va_in_range_q_MASK | \ + MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_MASK | \ + MH_DEBUG_REG52_TAG_valid_q_MASK) + +#define MH_DEBUG_REG52(arq_rtr, mmu_we, ctrl_tlbmiss_re_q, tlbmiss_ctrl_rts, mh_tlbmiss_send, mmu_stall_awaiting_tlb_miss_fetch, pa_in_mpu_range, stage1_valid, stage2_valid, client_behavior_q, ignore_tag_miss_q, tag_match_q, tag_miss_q, va_in_range_q, pte_fetch_complete_q, tag_valid_q) \ + ((arq_rtr << MH_DEBUG_REG52_ARQ_RTR_SHIFT) | \ + (mmu_we << MH_DEBUG_REG52_MMU_WE_SHIFT) | \ + (ctrl_tlbmiss_re_q << MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_SHIFT) | \ + (tlbmiss_ctrl_rts << MH_DEBUG_REG52_TLBMISS_CTRL_RTS_SHIFT) | \ + (mh_tlbmiss_send << MH_DEBUG_REG52_MH_TLBMISS_SEND_SHIFT) | \ + (mmu_stall_awaiting_tlb_miss_fetch << MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT) | \ + (pa_in_mpu_range << MH_DEBUG_REG52_pa_in_mpu_range_SHIFT) | \ + (stage1_valid << MH_DEBUG_REG52_stage1_valid_SHIFT) | \ + (stage2_valid << MH_DEBUG_REG52_stage2_valid_SHIFT) | \ + (client_behavior_q << MH_DEBUG_REG52_client_behavior_q_SHIFT) | \ + (ignore_tag_miss_q << MH_DEBUG_REG52_IGNORE_TAG_MISS_q_SHIFT) | \ + (tag_match_q << MH_DEBUG_REG52_tag_match_q_SHIFT) | \ + (tag_miss_q << MH_DEBUG_REG52_tag_miss_q_SHIFT) | \ + (va_in_range_q << MH_DEBUG_REG52_va_in_range_q_SHIFT) | \ + (pte_fetch_complete_q << MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_SHIFT) | \ + (tag_valid_q << MH_DEBUG_REG52_TAG_valid_q_SHIFT)) + +#define MH_DEBUG_REG52_GET_ARQ_RTR(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_ARQ_RTR_MASK) >> MH_DEBUG_REG52_ARQ_RTR_SHIFT) +#define MH_DEBUG_REG52_GET_MMU_WE(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_MMU_WE_MASK) >> MH_DEBUG_REG52_MMU_WE_SHIFT) +#define MH_DEBUG_REG52_GET_CTRL_TLBMISS_RE_q(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG52_GET_TLBMISS_CTRL_RTS(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG52_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG52_GET_MH_TLBMISS_SEND(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_MH_TLBMISS_SEND_MASK) >> MH_DEBUG_REG52_MH_TLBMISS_SEND_SHIFT) +#define MH_DEBUG_REG52_GET_MMU_STALL_AWAITING_TLB_MISS_FETCH(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK) >> MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT) +#define MH_DEBUG_REG52_GET_pa_in_mpu_range(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_pa_in_mpu_range_MASK) >> MH_DEBUG_REG52_pa_in_mpu_range_SHIFT) +#define MH_DEBUG_REG52_GET_stage1_valid(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_stage1_valid_MASK) >> MH_DEBUG_REG52_stage1_valid_SHIFT) +#define MH_DEBUG_REG52_GET_stage2_valid(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_stage2_valid_MASK) >> MH_DEBUG_REG52_stage2_valid_SHIFT) +#define MH_DEBUG_REG52_GET_client_behavior_q(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_client_behavior_q_MASK) >> MH_DEBUG_REG52_client_behavior_q_SHIFT) +#define MH_DEBUG_REG52_GET_IGNORE_TAG_MISS_q(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_IGNORE_TAG_MISS_q_MASK) >> MH_DEBUG_REG52_IGNORE_TAG_MISS_q_SHIFT) +#define MH_DEBUG_REG52_GET_tag_match_q(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_tag_match_q_MASK) >> MH_DEBUG_REG52_tag_match_q_SHIFT) +#define MH_DEBUG_REG52_GET_tag_miss_q(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_tag_miss_q_MASK) >> MH_DEBUG_REG52_tag_miss_q_SHIFT) +#define MH_DEBUG_REG52_GET_va_in_range_q(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_va_in_range_q_MASK) >> MH_DEBUG_REG52_va_in_range_q_SHIFT) +#define MH_DEBUG_REG52_GET_PTE_FETCH_COMPLETE_q(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_MASK) >> MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_SHIFT) +#define MH_DEBUG_REG52_GET_TAG_valid_q(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_TAG_valid_q_MASK) >> MH_DEBUG_REG52_TAG_valid_q_SHIFT) + +#define MH_DEBUG_REG52_SET_ARQ_RTR(mh_debug_reg52_reg, arq_rtr) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_ARQ_RTR_MASK) | (arq_rtr << MH_DEBUG_REG52_ARQ_RTR_SHIFT) +#define MH_DEBUG_REG52_SET_MMU_WE(mh_debug_reg52_reg, mmu_we) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG52_MMU_WE_SHIFT) +#define MH_DEBUG_REG52_SET_CTRL_TLBMISS_RE_q(mh_debug_reg52_reg, ctrl_tlbmiss_re_q) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG52_SET_TLBMISS_CTRL_RTS(mh_debug_reg52_reg, tlbmiss_ctrl_rts) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG52_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG52_SET_MH_TLBMISS_SEND(mh_debug_reg52_reg, mh_tlbmiss_send) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_MH_TLBMISS_SEND_MASK) | (mh_tlbmiss_send << MH_DEBUG_REG52_MH_TLBMISS_SEND_SHIFT) +#define MH_DEBUG_REG52_SET_MMU_STALL_AWAITING_TLB_MISS_FETCH(mh_debug_reg52_reg, mmu_stall_awaiting_tlb_miss_fetch) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK) | (mmu_stall_awaiting_tlb_miss_fetch << MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT) +#define MH_DEBUG_REG52_SET_pa_in_mpu_range(mh_debug_reg52_reg, pa_in_mpu_range) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_pa_in_mpu_range_MASK) | (pa_in_mpu_range << MH_DEBUG_REG52_pa_in_mpu_range_SHIFT) +#define MH_DEBUG_REG52_SET_stage1_valid(mh_debug_reg52_reg, stage1_valid) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_stage1_valid_MASK) | (stage1_valid << MH_DEBUG_REG52_stage1_valid_SHIFT) +#define MH_DEBUG_REG52_SET_stage2_valid(mh_debug_reg52_reg, stage2_valid) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_stage2_valid_MASK) | (stage2_valid << MH_DEBUG_REG52_stage2_valid_SHIFT) +#define MH_DEBUG_REG52_SET_client_behavior_q(mh_debug_reg52_reg, client_behavior_q) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_client_behavior_q_MASK) | (client_behavior_q << MH_DEBUG_REG52_client_behavior_q_SHIFT) +#define MH_DEBUG_REG52_SET_IGNORE_TAG_MISS_q(mh_debug_reg52_reg, ignore_tag_miss_q) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_IGNORE_TAG_MISS_q_MASK) | (ignore_tag_miss_q << MH_DEBUG_REG52_IGNORE_TAG_MISS_q_SHIFT) +#define MH_DEBUG_REG52_SET_tag_match_q(mh_debug_reg52_reg, tag_match_q) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_tag_match_q_MASK) | (tag_match_q << MH_DEBUG_REG52_tag_match_q_SHIFT) +#define MH_DEBUG_REG52_SET_tag_miss_q(mh_debug_reg52_reg, tag_miss_q) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_tag_miss_q_MASK) | (tag_miss_q << MH_DEBUG_REG52_tag_miss_q_SHIFT) +#define MH_DEBUG_REG52_SET_va_in_range_q(mh_debug_reg52_reg, va_in_range_q) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_va_in_range_q_MASK) | (va_in_range_q << MH_DEBUG_REG52_va_in_range_q_SHIFT) +#define MH_DEBUG_REG52_SET_PTE_FETCH_COMPLETE_q(mh_debug_reg52_reg, pte_fetch_complete_q) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_MASK) | (pte_fetch_complete_q << MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_SHIFT) +#define MH_DEBUG_REG52_SET_TAG_valid_q(mh_debug_reg52_reg, tag_valid_q) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_TAG_valid_q_MASK) | (tag_valid_q << MH_DEBUG_REG52_TAG_valid_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg52_t { + unsigned int arq_rtr : MH_DEBUG_REG52_ARQ_RTR_SIZE; + unsigned int mmu_we : MH_DEBUG_REG52_MMU_WE_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG52_TLBMISS_CTRL_RTS_SIZE; + unsigned int mh_tlbmiss_send : MH_DEBUG_REG52_MH_TLBMISS_SEND_SIZE; + unsigned int mmu_stall_awaiting_tlb_miss_fetch : MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE; + unsigned int pa_in_mpu_range : MH_DEBUG_REG52_pa_in_mpu_range_SIZE; + unsigned int stage1_valid : MH_DEBUG_REG52_stage1_valid_SIZE; + unsigned int stage2_valid : MH_DEBUG_REG52_stage2_valid_SIZE; + unsigned int client_behavior_q : MH_DEBUG_REG52_client_behavior_q_SIZE; + unsigned int ignore_tag_miss_q : MH_DEBUG_REG52_IGNORE_TAG_MISS_q_SIZE; + unsigned int tag_match_q : MH_DEBUG_REG52_tag_match_q_SIZE; + unsigned int tag_miss_q : MH_DEBUG_REG52_tag_miss_q_SIZE; + unsigned int va_in_range_q : MH_DEBUG_REG52_va_in_range_q_SIZE; + unsigned int pte_fetch_complete_q : MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_SIZE; + unsigned int tag_valid_q : MH_DEBUG_REG52_TAG_valid_q_SIZE; + } mh_debug_reg52_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg52_t { + unsigned int tag_valid_q : MH_DEBUG_REG52_TAG_valid_q_SIZE; + unsigned int pte_fetch_complete_q : MH_DEBUG_REG52_PTE_FETCH_COMPLETE_q_SIZE; + unsigned int va_in_range_q : MH_DEBUG_REG52_va_in_range_q_SIZE; + unsigned int tag_miss_q : MH_DEBUG_REG52_tag_miss_q_SIZE; + unsigned int tag_match_q : MH_DEBUG_REG52_tag_match_q_SIZE; + unsigned int ignore_tag_miss_q : MH_DEBUG_REG52_IGNORE_TAG_MISS_q_SIZE; + unsigned int client_behavior_q : MH_DEBUG_REG52_client_behavior_q_SIZE; + unsigned int stage2_valid : MH_DEBUG_REG52_stage2_valid_SIZE; + unsigned int stage1_valid : MH_DEBUG_REG52_stage1_valid_SIZE; + unsigned int pa_in_mpu_range : MH_DEBUG_REG52_pa_in_mpu_range_SIZE; + unsigned int mmu_stall_awaiting_tlb_miss_fetch : MH_DEBUG_REG52_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE; + unsigned int mh_tlbmiss_send : MH_DEBUG_REG52_MH_TLBMISS_SEND_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG52_TLBMISS_CTRL_RTS_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG52_CTRL_TLBMISS_RE_q_SIZE; + unsigned int mmu_we : MH_DEBUG_REG52_MMU_WE_SIZE; + unsigned int arq_rtr : MH_DEBUG_REG52_ARQ_RTR_SIZE; + } mh_debug_reg52_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg52_t f; +} mh_debug_reg52_u; + + +/* + * MH_DEBUG_REG53 struct + */ + +#define MH_DEBUG_REG53_TAG0_VA_SIZE 13 +#define MH_DEBUG_REG53_TAG_valid_q_0_SIZE 1 +#define MH_DEBUG_REG53_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG53_TAG1_VA_SIZE 13 +#define MH_DEBUG_REG53_TAG_valid_q_1_SIZE 1 + +#define MH_DEBUG_REG53_TAG0_VA_SHIFT 0 +#define MH_DEBUG_REG53_TAG_valid_q_0_SHIFT 13 +#define MH_DEBUG_REG53_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG53_TAG1_VA_SHIFT 16 +#define MH_DEBUG_REG53_TAG_valid_q_1_SHIFT 29 + +#define MH_DEBUG_REG53_TAG0_VA_MASK 0x00001fff +#define MH_DEBUG_REG53_TAG_valid_q_0_MASK 0x00002000 +#define MH_DEBUG_REG53_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG53_TAG1_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG53_TAG_valid_q_1_MASK 0x20000000 + +#define MH_DEBUG_REG53_MASK \ + (MH_DEBUG_REG53_TAG0_VA_MASK | \ + MH_DEBUG_REG53_TAG_valid_q_0_MASK | \ + MH_DEBUG_REG53_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG53_TAG1_VA_MASK | \ + MH_DEBUG_REG53_TAG_valid_q_1_MASK) + +#define MH_DEBUG_REG53(tag0_va, tag_valid_q_0, always_zero, tag1_va, tag_valid_q_1) \ + ((tag0_va << MH_DEBUG_REG53_TAG0_VA_SHIFT) | \ + (tag_valid_q_0 << MH_DEBUG_REG53_TAG_valid_q_0_SHIFT) | \ + (always_zero << MH_DEBUG_REG53_ALWAYS_ZERO_SHIFT) | \ + (tag1_va << MH_DEBUG_REG53_TAG1_VA_SHIFT) | \ + (tag_valid_q_1 << MH_DEBUG_REG53_TAG_valid_q_1_SHIFT)) + +#define MH_DEBUG_REG53_GET_TAG0_VA(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_TAG0_VA_MASK) >> MH_DEBUG_REG53_TAG0_VA_SHIFT) +#define MH_DEBUG_REG53_GET_TAG_valid_q_0(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_TAG_valid_q_0_MASK) >> MH_DEBUG_REG53_TAG_valid_q_0_SHIFT) +#define MH_DEBUG_REG53_GET_ALWAYS_ZERO(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG53_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG53_GET_TAG1_VA(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_TAG1_VA_MASK) >> MH_DEBUG_REG53_TAG1_VA_SHIFT) +#define MH_DEBUG_REG53_GET_TAG_valid_q_1(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_TAG_valid_q_1_MASK) >> MH_DEBUG_REG53_TAG_valid_q_1_SHIFT) + +#define MH_DEBUG_REG53_SET_TAG0_VA(mh_debug_reg53_reg, tag0_va) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_TAG0_VA_MASK) | (tag0_va << MH_DEBUG_REG53_TAG0_VA_SHIFT) +#define MH_DEBUG_REG53_SET_TAG_valid_q_0(mh_debug_reg53_reg, tag_valid_q_0) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_TAG_valid_q_0_MASK) | (tag_valid_q_0 << MH_DEBUG_REG53_TAG_valid_q_0_SHIFT) +#define MH_DEBUG_REG53_SET_ALWAYS_ZERO(mh_debug_reg53_reg, always_zero) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG53_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG53_SET_TAG1_VA(mh_debug_reg53_reg, tag1_va) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_TAG1_VA_MASK) | (tag1_va << MH_DEBUG_REG53_TAG1_VA_SHIFT) +#define MH_DEBUG_REG53_SET_TAG_valid_q_1(mh_debug_reg53_reg, tag_valid_q_1) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_TAG_valid_q_1_MASK) | (tag_valid_q_1 << MH_DEBUG_REG53_TAG_valid_q_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg53_t { + unsigned int tag0_va : MH_DEBUG_REG53_TAG0_VA_SIZE; + unsigned int tag_valid_q_0 : MH_DEBUG_REG53_TAG_valid_q_0_SIZE; + unsigned int always_zero : MH_DEBUG_REG53_ALWAYS_ZERO_SIZE; + unsigned int tag1_va : MH_DEBUG_REG53_TAG1_VA_SIZE; + unsigned int tag_valid_q_1 : MH_DEBUG_REG53_TAG_valid_q_1_SIZE; + unsigned int : 2; + } mh_debug_reg53_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg53_t { + unsigned int : 2; + unsigned int tag_valid_q_1 : MH_DEBUG_REG53_TAG_valid_q_1_SIZE; + unsigned int tag1_va : MH_DEBUG_REG53_TAG1_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG53_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_0 : MH_DEBUG_REG53_TAG_valid_q_0_SIZE; + unsigned int tag0_va : MH_DEBUG_REG53_TAG0_VA_SIZE; + } mh_debug_reg53_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg53_t f; +} mh_debug_reg53_u; + + +/* + * MH_DEBUG_REG54 struct + */ + +#define MH_DEBUG_REG54_TAG2_VA_SIZE 13 +#define MH_DEBUG_REG54_TAG_valid_q_2_SIZE 1 +#define MH_DEBUG_REG54_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG54_TAG3_VA_SIZE 13 +#define MH_DEBUG_REG54_TAG_valid_q_3_SIZE 1 + +#define MH_DEBUG_REG54_TAG2_VA_SHIFT 0 +#define MH_DEBUG_REG54_TAG_valid_q_2_SHIFT 13 +#define MH_DEBUG_REG54_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG54_TAG3_VA_SHIFT 16 +#define MH_DEBUG_REG54_TAG_valid_q_3_SHIFT 29 + +#define MH_DEBUG_REG54_TAG2_VA_MASK 0x00001fff +#define MH_DEBUG_REG54_TAG_valid_q_2_MASK 0x00002000 +#define MH_DEBUG_REG54_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG54_TAG3_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG54_TAG_valid_q_3_MASK 0x20000000 + +#define MH_DEBUG_REG54_MASK \ + (MH_DEBUG_REG54_TAG2_VA_MASK | \ + MH_DEBUG_REG54_TAG_valid_q_2_MASK | \ + MH_DEBUG_REG54_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG54_TAG3_VA_MASK | \ + MH_DEBUG_REG54_TAG_valid_q_3_MASK) + +#define MH_DEBUG_REG54(tag2_va, tag_valid_q_2, always_zero, tag3_va, tag_valid_q_3) \ + ((tag2_va << MH_DEBUG_REG54_TAG2_VA_SHIFT) | \ + (tag_valid_q_2 << MH_DEBUG_REG54_TAG_valid_q_2_SHIFT) | \ + (always_zero << MH_DEBUG_REG54_ALWAYS_ZERO_SHIFT) | \ + (tag3_va << MH_DEBUG_REG54_TAG3_VA_SHIFT) | \ + (tag_valid_q_3 << MH_DEBUG_REG54_TAG_valid_q_3_SHIFT)) + +#define MH_DEBUG_REG54_GET_TAG2_VA(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_TAG2_VA_MASK) >> MH_DEBUG_REG54_TAG2_VA_SHIFT) +#define MH_DEBUG_REG54_GET_TAG_valid_q_2(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_TAG_valid_q_2_MASK) >> MH_DEBUG_REG54_TAG_valid_q_2_SHIFT) +#define MH_DEBUG_REG54_GET_ALWAYS_ZERO(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG54_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG54_GET_TAG3_VA(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_TAG3_VA_MASK) >> MH_DEBUG_REG54_TAG3_VA_SHIFT) +#define MH_DEBUG_REG54_GET_TAG_valid_q_3(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_TAG_valid_q_3_MASK) >> MH_DEBUG_REG54_TAG_valid_q_3_SHIFT) + +#define MH_DEBUG_REG54_SET_TAG2_VA(mh_debug_reg54_reg, tag2_va) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TAG2_VA_MASK) | (tag2_va << MH_DEBUG_REG54_TAG2_VA_SHIFT) +#define MH_DEBUG_REG54_SET_TAG_valid_q_2(mh_debug_reg54_reg, tag_valid_q_2) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TAG_valid_q_2_MASK) | (tag_valid_q_2 << MH_DEBUG_REG54_TAG_valid_q_2_SHIFT) +#define MH_DEBUG_REG54_SET_ALWAYS_ZERO(mh_debug_reg54_reg, always_zero) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG54_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG54_SET_TAG3_VA(mh_debug_reg54_reg, tag3_va) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TAG3_VA_MASK) | (tag3_va << MH_DEBUG_REG54_TAG3_VA_SHIFT) +#define MH_DEBUG_REG54_SET_TAG_valid_q_3(mh_debug_reg54_reg, tag_valid_q_3) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TAG_valid_q_3_MASK) | (tag_valid_q_3 << MH_DEBUG_REG54_TAG_valid_q_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg54_t { + unsigned int tag2_va : MH_DEBUG_REG54_TAG2_VA_SIZE; + unsigned int tag_valid_q_2 : MH_DEBUG_REG54_TAG_valid_q_2_SIZE; + unsigned int always_zero : MH_DEBUG_REG54_ALWAYS_ZERO_SIZE; + unsigned int tag3_va : MH_DEBUG_REG54_TAG3_VA_SIZE; + unsigned int tag_valid_q_3 : MH_DEBUG_REG54_TAG_valid_q_3_SIZE; + unsigned int : 2; + } mh_debug_reg54_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg54_t { + unsigned int : 2; + unsigned int tag_valid_q_3 : MH_DEBUG_REG54_TAG_valid_q_3_SIZE; + unsigned int tag3_va : MH_DEBUG_REG54_TAG3_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG54_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_2 : MH_DEBUG_REG54_TAG_valid_q_2_SIZE; + unsigned int tag2_va : MH_DEBUG_REG54_TAG2_VA_SIZE; + } mh_debug_reg54_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg54_t f; +} mh_debug_reg54_u; + + +/* + * MH_DEBUG_REG55 struct + */ + +#define MH_DEBUG_REG55_TAG4_VA_SIZE 13 +#define MH_DEBUG_REG55_TAG_valid_q_4_SIZE 1 +#define MH_DEBUG_REG55_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG55_TAG5_VA_SIZE 13 +#define MH_DEBUG_REG55_TAG_valid_q_5_SIZE 1 + +#define MH_DEBUG_REG55_TAG4_VA_SHIFT 0 +#define MH_DEBUG_REG55_TAG_valid_q_4_SHIFT 13 +#define MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG55_TAG5_VA_SHIFT 16 +#define MH_DEBUG_REG55_TAG_valid_q_5_SHIFT 29 + +#define MH_DEBUG_REG55_TAG4_VA_MASK 0x00001fff +#define MH_DEBUG_REG55_TAG_valid_q_4_MASK 0x00002000 +#define MH_DEBUG_REG55_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG55_TAG5_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG55_TAG_valid_q_5_MASK 0x20000000 + +#define MH_DEBUG_REG55_MASK \ + (MH_DEBUG_REG55_TAG4_VA_MASK | \ + MH_DEBUG_REG55_TAG_valid_q_4_MASK | \ + MH_DEBUG_REG55_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG55_TAG5_VA_MASK | \ + MH_DEBUG_REG55_TAG_valid_q_5_MASK) + +#define MH_DEBUG_REG55(tag4_va, tag_valid_q_4, always_zero, tag5_va, tag_valid_q_5) \ + ((tag4_va << MH_DEBUG_REG55_TAG4_VA_SHIFT) | \ + (tag_valid_q_4 << MH_DEBUG_REG55_TAG_valid_q_4_SHIFT) | \ + (always_zero << MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT) | \ + (tag5_va << MH_DEBUG_REG55_TAG5_VA_SHIFT) | \ + (tag_valid_q_5 << MH_DEBUG_REG55_TAG_valid_q_5_SHIFT)) + +#define MH_DEBUG_REG55_GET_TAG4_VA(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_TAG4_VA_MASK) >> MH_DEBUG_REG55_TAG4_VA_SHIFT) +#define MH_DEBUG_REG55_GET_TAG_valid_q_4(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_TAG_valid_q_4_MASK) >> MH_DEBUG_REG55_TAG_valid_q_4_SHIFT) +#define MH_DEBUG_REG55_GET_ALWAYS_ZERO(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG55_GET_TAG5_VA(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_TAG5_VA_MASK) >> MH_DEBUG_REG55_TAG5_VA_SHIFT) +#define MH_DEBUG_REG55_GET_TAG_valid_q_5(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_TAG_valid_q_5_MASK) >> MH_DEBUG_REG55_TAG_valid_q_5_SHIFT) + +#define MH_DEBUG_REG55_SET_TAG4_VA(mh_debug_reg55_reg, tag4_va) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG4_VA_MASK) | (tag4_va << MH_DEBUG_REG55_TAG4_VA_SHIFT) +#define MH_DEBUG_REG55_SET_TAG_valid_q_4(mh_debug_reg55_reg, tag_valid_q_4) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG_valid_q_4_MASK) | (tag_valid_q_4 << MH_DEBUG_REG55_TAG_valid_q_4_SHIFT) +#define MH_DEBUG_REG55_SET_ALWAYS_ZERO(mh_debug_reg55_reg, always_zero) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG55_SET_TAG5_VA(mh_debug_reg55_reg, tag5_va) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG5_VA_MASK) | (tag5_va << MH_DEBUG_REG55_TAG5_VA_SHIFT) +#define MH_DEBUG_REG55_SET_TAG_valid_q_5(mh_debug_reg55_reg, tag_valid_q_5) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG_valid_q_5_MASK) | (tag_valid_q_5 << MH_DEBUG_REG55_TAG_valid_q_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg55_t { + unsigned int tag4_va : MH_DEBUG_REG55_TAG4_VA_SIZE; + unsigned int tag_valid_q_4 : MH_DEBUG_REG55_TAG_valid_q_4_SIZE; + unsigned int always_zero : MH_DEBUG_REG55_ALWAYS_ZERO_SIZE; + unsigned int tag5_va : MH_DEBUG_REG55_TAG5_VA_SIZE; + unsigned int tag_valid_q_5 : MH_DEBUG_REG55_TAG_valid_q_5_SIZE; + unsigned int : 2; + } mh_debug_reg55_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg55_t { + unsigned int : 2; + unsigned int tag_valid_q_5 : MH_DEBUG_REG55_TAG_valid_q_5_SIZE; + unsigned int tag5_va : MH_DEBUG_REG55_TAG5_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG55_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_4 : MH_DEBUG_REG55_TAG_valid_q_4_SIZE; + unsigned int tag4_va : MH_DEBUG_REG55_TAG4_VA_SIZE; + } mh_debug_reg55_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg55_t f; +} mh_debug_reg55_u; + + +/* + * MH_DEBUG_REG56 struct + */ + +#define MH_DEBUG_REG56_TAG6_VA_SIZE 13 +#define MH_DEBUG_REG56_TAG_valid_q_6_SIZE 1 +#define MH_DEBUG_REG56_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG56_TAG7_VA_SIZE 13 +#define MH_DEBUG_REG56_TAG_valid_q_7_SIZE 1 + +#define MH_DEBUG_REG56_TAG6_VA_SHIFT 0 +#define MH_DEBUG_REG56_TAG_valid_q_6_SHIFT 13 +#define MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG56_TAG7_VA_SHIFT 16 +#define MH_DEBUG_REG56_TAG_valid_q_7_SHIFT 29 + +#define MH_DEBUG_REG56_TAG6_VA_MASK 0x00001fff +#define MH_DEBUG_REG56_TAG_valid_q_6_MASK 0x00002000 +#define MH_DEBUG_REG56_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG56_TAG7_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG56_TAG_valid_q_7_MASK 0x20000000 + +#define MH_DEBUG_REG56_MASK \ + (MH_DEBUG_REG56_TAG6_VA_MASK | \ + MH_DEBUG_REG56_TAG_valid_q_6_MASK | \ + MH_DEBUG_REG56_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG56_TAG7_VA_MASK | \ + MH_DEBUG_REG56_TAG_valid_q_7_MASK) + +#define MH_DEBUG_REG56(tag6_va, tag_valid_q_6, always_zero, tag7_va, tag_valid_q_7) \ + ((tag6_va << MH_DEBUG_REG56_TAG6_VA_SHIFT) | \ + (tag_valid_q_6 << MH_DEBUG_REG56_TAG_valid_q_6_SHIFT) | \ + (always_zero << MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT) | \ + (tag7_va << MH_DEBUG_REG56_TAG7_VA_SHIFT) | \ + (tag_valid_q_7 << MH_DEBUG_REG56_TAG_valid_q_7_SHIFT)) + +#define MH_DEBUG_REG56_GET_TAG6_VA(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_TAG6_VA_MASK) >> MH_DEBUG_REG56_TAG6_VA_SHIFT) +#define MH_DEBUG_REG56_GET_TAG_valid_q_6(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_TAG_valid_q_6_MASK) >> MH_DEBUG_REG56_TAG_valid_q_6_SHIFT) +#define MH_DEBUG_REG56_GET_ALWAYS_ZERO(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG56_GET_TAG7_VA(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_TAG7_VA_MASK) >> MH_DEBUG_REG56_TAG7_VA_SHIFT) +#define MH_DEBUG_REG56_GET_TAG_valid_q_7(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_TAG_valid_q_7_MASK) >> MH_DEBUG_REG56_TAG_valid_q_7_SHIFT) + +#define MH_DEBUG_REG56_SET_TAG6_VA(mh_debug_reg56_reg, tag6_va) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG6_VA_MASK) | (tag6_va << MH_DEBUG_REG56_TAG6_VA_SHIFT) +#define MH_DEBUG_REG56_SET_TAG_valid_q_6(mh_debug_reg56_reg, tag_valid_q_6) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG_valid_q_6_MASK) | (tag_valid_q_6 << MH_DEBUG_REG56_TAG_valid_q_6_SHIFT) +#define MH_DEBUG_REG56_SET_ALWAYS_ZERO(mh_debug_reg56_reg, always_zero) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG56_SET_TAG7_VA(mh_debug_reg56_reg, tag7_va) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG7_VA_MASK) | (tag7_va << MH_DEBUG_REG56_TAG7_VA_SHIFT) +#define MH_DEBUG_REG56_SET_TAG_valid_q_7(mh_debug_reg56_reg, tag_valid_q_7) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG_valid_q_7_MASK) | (tag_valid_q_7 << MH_DEBUG_REG56_TAG_valid_q_7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg56_t { + unsigned int tag6_va : MH_DEBUG_REG56_TAG6_VA_SIZE; + unsigned int tag_valid_q_6 : MH_DEBUG_REG56_TAG_valid_q_6_SIZE; + unsigned int always_zero : MH_DEBUG_REG56_ALWAYS_ZERO_SIZE; + unsigned int tag7_va : MH_DEBUG_REG56_TAG7_VA_SIZE; + unsigned int tag_valid_q_7 : MH_DEBUG_REG56_TAG_valid_q_7_SIZE; + unsigned int : 2; + } mh_debug_reg56_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg56_t { + unsigned int : 2; + unsigned int tag_valid_q_7 : MH_DEBUG_REG56_TAG_valid_q_7_SIZE; + unsigned int tag7_va : MH_DEBUG_REG56_TAG7_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG56_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_6 : MH_DEBUG_REG56_TAG_valid_q_6_SIZE; + unsigned int tag6_va : MH_DEBUG_REG56_TAG6_VA_SIZE; + } mh_debug_reg56_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg56_t f; +} mh_debug_reg56_u; + + +/* + * MH_DEBUG_REG57 struct + */ + +#define MH_DEBUG_REG57_TAG8_VA_SIZE 13 +#define MH_DEBUG_REG57_TAG_valid_q_8_SIZE 1 +#define MH_DEBUG_REG57_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG57_TAG9_VA_SIZE 13 +#define MH_DEBUG_REG57_TAG_valid_q_9_SIZE 1 + +#define MH_DEBUG_REG57_TAG8_VA_SHIFT 0 +#define MH_DEBUG_REG57_TAG_valid_q_8_SHIFT 13 +#define MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG57_TAG9_VA_SHIFT 16 +#define MH_DEBUG_REG57_TAG_valid_q_9_SHIFT 29 + +#define MH_DEBUG_REG57_TAG8_VA_MASK 0x00001fff +#define MH_DEBUG_REG57_TAG_valid_q_8_MASK 0x00002000 +#define MH_DEBUG_REG57_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG57_TAG9_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG57_TAG_valid_q_9_MASK 0x20000000 + +#define MH_DEBUG_REG57_MASK \ + (MH_DEBUG_REG57_TAG8_VA_MASK | \ + MH_DEBUG_REG57_TAG_valid_q_8_MASK | \ + MH_DEBUG_REG57_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG57_TAG9_VA_MASK | \ + MH_DEBUG_REG57_TAG_valid_q_9_MASK) + +#define MH_DEBUG_REG57(tag8_va, tag_valid_q_8, always_zero, tag9_va, tag_valid_q_9) \ + ((tag8_va << MH_DEBUG_REG57_TAG8_VA_SHIFT) | \ + (tag_valid_q_8 << MH_DEBUG_REG57_TAG_valid_q_8_SHIFT) | \ + (always_zero << MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT) | \ + (tag9_va << MH_DEBUG_REG57_TAG9_VA_SHIFT) | \ + (tag_valid_q_9 << MH_DEBUG_REG57_TAG_valid_q_9_SHIFT)) + +#define MH_DEBUG_REG57_GET_TAG8_VA(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_TAG8_VA_MASK) >> MH_DEBUG_REG57_TAG8_VA_SHIFT) +#define MH_DEBUG_REG57_GET_TAG_valid_q_8(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_TAG_valid_q_8_MASK) >> MH_DEBUG_REG57_TAG_valid_q_8_SHIFT) +#define MH_DEBUG_REG57_GET_ALWAYS_ZERO(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG57_GET_TAG9_VA(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_TAG9_VA_MASK) >> MH_DEBUG_REG57_TAG9_VA_SHIFT) +#define MH_DEBUG_REG57_GET_TAG_valid_q_9(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_TAG_valid_q_9_MASK) >> MH_DEBUG_REG57_TAG_valid_q_9_SHIFT) + +#define MH_DEBUG_REG57_SET_TAG8_VA(mh_debug_reg57_reg, tag8_va) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG8_VA_MASK) | (tag8_va << MH_DEBUG_REG57_TAG8_VA_SHIFT) +#define MH_DEBUG_REG57_SET_TAG_valid_q_8(mh_debug_reg57_reg, tag_valid_q_8) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG_valid_q_8_MASK) | (tag_valid_q_8 << MH_DEBUG_REG57_TAG_valid_q_8_SHIFT) +#define MH_DEBUG_REG57_SET_ALWAYS_ZERO(mh_debug_reg57_reg, always_zero) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG57_SET_TAG9_VA(mh_debug_reg57_reg, tag9_va) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG9_VA_MASK) | (tag9_va << MH_DEBUG_REG57_TAG9_VA_SHIFT) +#define MH_DEBUG_REG57_SET_TAG_valid_q_9(mh_debug_reg57_reg, tag_valid_q_9) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG_valid_q_9_MASK) | (tag_valid_q_9 << MH_DEBUG_REG57_TAG_valid_q_9_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg57_t { + unsigned int tag8_va : MH_DEBUG_REG57_TAG8_VA_SIZE; + unsigned int tag_valid_q_8 : MH_DEBUG_REG57_TAG_valid_q_8_SIZE; + unsigned int always_zero : MH_DEBUG_REG57_ALWAYS_ZERO_SIZE; + unsigned int tag9_va : MH_DEBUG_REG57_TAG9_VA_SIZE; + unsigned int tag_valid_q_9 : MH_DEBUG_REG57_TAG_valid_q_9_SIZE; + unsigned int : 2; + } mh_debug_reg57_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg57_t { + unsigned int : 2; + unsigned int tag_valid_q_9 : MH_DEBUG_REG57_TAG_valid_q_9_SIZE; + unsigned int tag9_va : MH_DEBUG_REG57_TAG9_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG57_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_8 : MH_DEBUG_REG57_TAG_valid_q_8_SIZE; + unsigned int tag8_va : MH_DEBUG_REG57_TAG8_VA_SIZE; + } mh_debug_reg57_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg57_t f; +} mh_debug_reg57_u; + + +/* + * MH_DEBUG_REG58 struct + */ + +#define MH_DEBUG_REG58_TAG10_VA_SIZE 13 +#define MH_DEBUG_REG58_TAG_valid_q_10_SIZE 1 +#define MH_DEBUG_REG58_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG58_TAG11_VA_SIZE 13 +#define MH_DEBUG_REG58_TAG_valid_q_11_SIZE 1 + +#define MH_DEBUG_REG58_TAG10_VA_SHIFT 0 +#define MH_DEBUG_REG58_TAG_valid_q_10_SHIFT 13 +#define MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG58_TAG11_VA_SHIFT 16 +#define MH_DEBUG_REG58_TAG_valid_q_11_SHIFT 29 + +#define MH_DEBUG_REG58_TAG10_VA_MASK 0x00001fff +#define MH_DEBUG_REG58_TAG_valid_q_10_MASK 0x00002000 +#define MH_DEBUG_REG58_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG58_TAG11_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG58_TAG_valid_q_11_MASK 0x20000000 + +#define MH_DEBUG_REG58_MASK \ + (MH_DEBUG_REG58_TAG10_VA_MASK | \ + MH_DEBUG_REG58_TAG_valid_q_10_MASK | \ + MH_DEBUG_REG58_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG58_TAG11_VA_MASK | \ + MH_DEBUG_REG58_TAG_valid_q_11_MASK) + +#define MH_DEBUG_REG58(tag10_va, tag_valid_q_10, always_zero, tag11_va, tag_valid_q_11) \ + ((tag10_va << MH_DEBUG_REG58_TAG10_VA_SHIFT) | \ + (tag_valid_q_10 << MH_DEBUG_REG58_TAG_valid_q_10_SHIFT) | \ + (always_zero << MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT) | \ + (tag11_va << MH_DEBUG_REG58_TAG11_VA_SHIFT) | \ + (tag_valid_q_11 << MH_DEBUG_REG58_TAG_valid_q_11_SHIFT)) + +#define MH_DEBUG_REG58_GET_TAG10_VA(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_TAG10_VA_MASK) >> MH_DEBUG_REG58_TAG10_VA_SHIFT) +#define MH_DEBUG_REG58_GET_TAG_valid_q_10(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_TAG_valid_q_10_MASK) >> MH_DEBUG_REG58_TAG_valid_q_10_SHIFT) +#define MH_DEBUG_REG58_GET_ALWAYS_ZERO(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG58_GET_TAG11_VA(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_TAG11_VA_MASK) >> MH_DEBUG_REG58_TAG11_VA_SHIFT) +#define MH_DEBUG_REG58_GET_TAG_valid_q_11(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_TAG_valid_q_11_MASK) >> MH_DEBUG_REG58_TAG_valid_q_11_SHIFT) + +#define MH_DEBUG_REG58_SET_TAG10_VA(mh_debug_reg58_reg, tag10_va) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG10_VA_MASK) | (tag10_va << MH_DEBUG_REG58_TAG10_VA_SHIFT) +#define MH_DEBUG_REG58_SET_TAG_valid_q_10(mh_debug_reg58_reg, tag_valid_q_10) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG_valid_q_10_MASK) | (tag_valid_q_10 << MH_DEBUG_REG58_TAG_valid_q_10_SHIFT) +#define MH_DEBUG_REG58_SET_ALWAYS_ZERO(mh_debug_reg58_reg, always_zero) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG58_SET_TAG11_VA(mh_debug_reg58_reg, tag11_va) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG11_VA_MASK) | (tag11_va << MH_DEBUG_REG58_TAG11_VA_SHIFT) +#define MH_DEBUG_REG58_SET_TAG_valid_q_11(mh_debug_reg58_reg, tag_valid_q_11) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG_valid_q_11_MASK) | (tag_valid_q_11 << MH_DEBUG_REG58_TAG_valid_q_11_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg58_t { + unsigned int tag10_va : MH_DEBUG_REG58_TAG10_VA_SIZE; + unsigned int tag_valid_q_10 : MH_DEBUG_REG58_TAG_valid_q_10_SIZE; + unsigned int always_zero : MH_DEBUG_REG58_ALWAYS_ZERO_SIZE; + unsigned int tag11_va : MH_DEBUG_REG58_TAG11_VA_SIZE; + unsigned int tag_valid_q_11 : MH_DEBUG_REG58_TAG_valid_q_11_SIZE; + unsigned int : 2; + } mh_debug_reg58_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg58_t { + unsigned int : 2; + unsigned int tag_valid_q_11 : MH_DEBUG_REG58_TAG_valid_q_11_SIZE; + unsigned int tag11_va : MH_DEBUG_REG58_TAG11_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG58_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_10 : MH_DEBUG_REG58_TAG_valid_q_10_SIZE; + unsigned int tag10_va : MH_DEBUG_REG58_TAG10_VA_SIZE; + } mh_debug_reg58_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg58_t f; +} mh_debug_reg58_u; + + +/* + * MH_DEBUG_REG59 struct + */ + +#define MH_DEBUG_REG59_TAG12_VA_SIZE 13 +#define MH_DEBUG_REG59_TAG_valid_q_12_SIZE 1 +#define MH_DEBUG_REG59_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG59_TAG13_VA_SIZE 13 +#define MH_DEBUG_REG59_TAG_valid_q_13_SIZE 1 + +#define MH_DEBUG_REG59_TAG12_VA_SHIFT 0 +#define MH_DEBUG_REG59_TAG_valid_q_12_SHIFT 13 +#define MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG59_TAG13_VA_SHIFT 16 +#define MH_DEBUG_REG59_TAG_valid_q_13_SHIFT 29 + +#define MH_DEBUG_REG59_TAG12_VA_MASK 0x00001fff +#define MH_DEBUG_REG59_TAG_valid_q_12_MASK 0x00002000 +#define MH_DEBUG_REG59_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG59_TAG13_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG59_TAG_valid_q_13_MASK 0x20000000 + +#define MH_DEBUG_REG59_MASK \ + (MH_DEBUG_REG59_TAG12_VA_MASK | \ + MH_DEBUG_REG59_TAG_valid_q_12_MASK | \ + MH_DEBUG_REG59_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG59_TAG13_VA_MASK | \ + MH_DEBUG_REG59_TAG_valid_q_13_MASK) + +#define MH_DEBUG_REG59(tag12_va, tag_valid_q_12, always_zero, tag13_va, tag_valid_q_13) \ + ((tag12_va << MH_DEBUG_REG59_TAG12_VA_SHIFT) | \ + (tag_valid_q_12 << MH_DEBUG_REG59_TAG_valid_q_12_SHIFT) | \ + (always_zero << MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT) | \ + (tag13_va << MH_DEBUG_REG59_TAG13_VA_SHIFT) | \ + (tag_valid_q_13 << MH_DEBUG_REG59_TAG_valid_q_13_SHIFT)) + +#define MH_DEBUG_REG59_GET_TAG12_VA(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_TAG12_VA_MASK) >> MH_DEBUG_REG59_TAG12_VA_SHIFT) +#define MH_DEBUG_REG59_GET_TAG_valid_q_12(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_TAG_valid_q_12_MASK) >> MH_DEBUG_REG59_TAG_valid_q_12_SHIFT) +#define MH_DEBUG_REG59_GET_ALWAYS_ZERO(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG59_GET_TAG13_VA(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_TAG13_VA_MASK) >> MH_DEBUG_REG59_TAG13_VA_SHIFT) +#define MH_DEBUG_REG59_GET_TAG_valid_q_13(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_TAG_valid_q_13_MASK) >> MH_DEBUG_REG59_TAG_valid_q_13_SHIFT) + +#define MH_DEBUG_REG59_SET_TAG12_VA(mh_debug_reg59_reg, tag12_va) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG12_VA_MASK) | (tag12_va << MH_DEBUG_REG59_TAG12_VA_SHIFT) +#define MH_DEBUG_REG59_SET_TAG_valid_q_12(mh_debug_reg59_reg, tag_valid_q_12) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG_valid_q_12_MASK) | (tag_valid_q_12 << MH_DEBUG_REG59_TAG_valid_q_12_SHIFT) +#define MH_DEBUG_REG59_SET_ALWAYS_ZERO(mh_debug_reg59_reg, always_zero) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG59_SET_TAG13_VA(mh_debug_reg59_reg, tag13_va) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG13_VA_MASK) | (tag13_va << MH_DEBUG_REG59_TAG13_VA_SHIFT) +#define MH_DEBUG_REG59_SET_TAG_valid_q_13(mh_debug_reg59_reg, tag_valid_q_13) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG_valid_q_13_MASK) | (tag_valid_q_13 << MH_DEBUG_REG59_TAG_valid_q_13_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg59_t { + unsigned int tag12_va : MH_DEBUG_REG59_TAG12_VA_SIZE; + unsigned int tag_valid_q_12 : MH_DEBUG_REG59_TAG_valid_q_12_SIZE; + unsigned int always_zero : MH_DEBUG_REG59_ALWAYS_ZERO_SIZE; + unsigned int tag13_va : MH_DEBUG_REG59_TAG13_VA_SIZE; + unsigned int tag_valid_q_13 : MH_DEBUG_REG59_TAG_valid_q_13_SIZE; + unsigned int : 2; + } mh_debug_reg59_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg59_t { + unsigned int : 2; + unsigned int tag_valid_q_13 : MH_DEBUG_REG59_TAG_valid_q_13_SIZE; + unsigned int tag13_va : MH_DEBUG_REG59_TAG13_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG59_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_12 : MH_DEBUG_REG59_TAG_valid_q_12_SIZE; + unsigned int tag12_va : MH_DEBUG_REG59_TAG12_VA_SIZE; + } mh_debug_reg59_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg59_t f; +} mh_debug_reg59_u; + + +/* + * MH_DEBUG_REG60 struct + */ + +#define MH_DEBUG_REG60_TAG14_VA_SIZE 13 +#define MH_DEBUG_REG60_TAG_valid_q_14_SIZE 1 +#define MH_DEBUG_REG60_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG60_TAG15_VA_SIZE 13 +#define MH_DEBUG_REG60_TAG_valid_q_15_SIZE 1 + +#define MH_DEBUG_REG60_TAG14_VA_SHIFT 0 +#define MH_DEBUG_REG60_TAG_valid_q_14_SHIFT 13 +#define MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG60_TAG15_VA_SHIFT 16 +#define MH_DEBUG_REG60_TAG_valid_q_15_SHIFT 29 + +#define MH_DEBUG_REG60_TAG14_VA_MASK 0x00001fff +#define MH_DEBUG_REG60_TAG_valid_q_14_MASK 0x00002000 +#define MH_DEBUG_REG60_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG60_TAG15_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG60_TAG_valid_q_15_MASK 0x20000000 + +#define MH_DEBUG_REG60_MASK \ + (MH_DEBUG_REG60_TAG14_VA_MASK | \ + MH_DEBUG_REG60_TAG_valid_q_14_MASK | \ + MH_DEBUG_REG60_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG60_TAG15_VA_MASK | \ + MH_DEBUG_REG60_TAG_valid_q_15_MASK) + +#define MH_DEBUG_REG60(tag14_va, tag_valid_q_14, always_zero, tag15_va, tag_valid_q_15) \ + ((tag14_va << MH_DEBUG_REG60_TAG14_VA_SHIFT) | \ + (tag_valid_q_14 << MH_DEBUG_REG60_TAG_valid_q_14_SHIFT) | \ + (always_zero << MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT) | \ + (tag15_va << MH_DEBUG_REG60_TAG15_VA_SHIFT) | \ + (tag_valid_q_15 << MH_DEBUG_REG60_TAG_valid_q_15_SHIFT)) + +#define MH_DEBUG_REG60_GET_TAG14_VA(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_TAG14_VA_MASK) >> MH_DEBUG_REG60_TAG14_VA_SHIFT) +#define MH_DEBUG_REG60_GET_TAG_valid_q_14(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_TAG_valid_q_14_MASK) >> MH_DEBUG_REG60_TAG_valid_q_14_SHIFT) +#define MH_DEBUG_REG60_GET_ALWAYS_ZERO(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG60_GET_TAG15_VA(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_TAG15_VA_MASK) >> MH_DEBUG_REG60_TAG15_VA_SHIFT) +#define MH_DEBUG_REG60_GET_TAG_valid_q_15(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_TAG_valid_q_15_MASK) >> MH_DEBUG_REG60_TAG_valid_q_15_SHIFT) + +#define MH_DEBUG_REG60_SET_TAG14_VA(mh_debug_reg60_reg, tag14_va) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG14_VA_MASK) | (tag14_va << MH_DEBUG_REG60_TAG14_VA_SHIFT) +#define MH_DEBUG_REG60_SET_TAG_valid_q_14(mh_debug_reg60_reg, tag_valid_q_14) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG_valid_q_14_MASK) | (tag_valid_q_14 << MH_DEBUG_REG60_TAG_valid_q_14_SHIFT) +#define MH_DEBUG_REG60_SET_ALWAYS_ZERO(mh_debug_reg60_reg, always_zero) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG60_SET_TAG15_VA(mh_debug_reg60_reg, tag15_va) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG15_VA_MASK) | (tag15_va << MH_DEBUG_REG60_TAG15_VA_SHIFT) +#define MH_DEBUG_REG60_SET_TAG_valid_q_15(mh_debug_reg60_reg, tag_valid_q_15) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG_valid_q_15_MASK) | (tag_valid_q_15 << MH_DEBUG_REG60_TAG_valid_q_15_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg60_t { + unsigned int tag14_va : MH_DEBUG_REG60_TAG14_VA_SIZE; + unsigned int tag_valid_q_14 : MH_DEBUG_REG60_TAG_valid_q_14_SIZE; + unsigned int always_zero : MH_DEBUG_REG60_ALWAYS_ZERO_SIZE; + unsigned int tag15_va : MH_DEBUG_REG60_TAG15_VA_SIZE; + unsigned int tag_valid_q_15 : MH_DEBUG_REG60_TAG_valid_q_15_SIZE; + unsigned int : 2; + } mh_debug_reg60_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg60_t { + unsigned int : 2; + unsigned int tag_valid_q_15 : MH_DEBUG_REG60_TAG_valid_q_15_SIZE; + unsigned int tag15_va : MH_DEBUG_REG60_TAG15_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG60_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_14 : MH_DEBUG_REG60_TAG_valid_q_14_SIZE; + unsigned int tag14_va : MH_DEBUG_REG60_TAG14_VA_SIZE; + } mh_debug_reg60_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg60_t f; +} mh_debug_reg60_u; + + +/* + * MH_DEBUG_REG61 struct + */ + +#define MH_DEBUG_REG61_MH_DBG_DEFAULT_SIZE 32 + +#define MH_DEBUG_REG61_MH_DBG_DEFAULT_SHIFT 0 + +#define MH_DEBUG_REG61_MH_DBG_DEFAULT_MASK 0xffffffff + +#define MH_DEBUG_REG61_MASK \ + (MH_DEBUG_REG61_MH_DBG_DEFAULT_MASK) + +#define MH_DEBUG_REG61(mh_dbg_default) \ + ((mh_dbg_default << MH_DEBUG_REG61_MH_DBG_DEFAULT_SHIFT)) + +#define MH_DEBUG_REG61_GET_MH_DBG_DEFAULT(mh_debug_reg61) \ + ((mh_debug_reg61 & MH_DEBUG_REG61_MH_DBG_DEFAULT_MASK) >> MH_DEBUG_REG61_MH_DBG_DEFAULT_SHIFT) + +#define MH_DEBUG_REG61_SET_MH_DBG_DEFAULT(mh_debug_reg61_reg, mh_dbg_default) \ + mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_MH_DBG_DEFAULT_MASK) | (mh_dbg_default << MH_DEBUG_REG61_MH_DBG_DEFAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg61_t { + unsigned int mh_dbg_default : MH_DEBUG_REG61_MH_DBG_DEFAULT_SIZE; + } mh_debug_reg61_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg61_t { + unsigned int mh_dbg_default : MH_DEBUG_REG61_MH_DBG_DEFAULT_SIZE; + } mh_debug_reg61_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg61_t f; +} mh_debug_reg61_u; + + +/* + * MH_DEBUG_REG62 struct + */ + +#define MH_DEBUG_REG62_MH_DBG_DEFAULT_SIZE 32 + +#define MH_DEBUG_REG62_MH_DBG_DEFAULT_SHIFT 0 + +#define MH_DEBUG_REG62_MH_DBG_DEFAULT_MASK 0xffffffff + +#define MH_DEBUG_REG62_MASK \ + (MH_DEBUG_REG62_MH_DBG_DEFAULT_MASK) + +#define MH_DEBUG_REG62(mh_dbg_default) \ + ((mh_dbg_default << MH_DEBUG_REG62_MH_DBG_DEFAULT_SHIFT)) + +#define MH_DEBUG_REG62_GET_MH_DBG_DEFAULT(mh_debug_reg62) \ + ((mh_debug_reg62 & MH_DEBUG_REG62_MH_DBG_DEFAULT_MASK) >> MH_DEBUG_REG62_MH_DBG_DEFAULT_SHIFT) + +#define MH_DEBUG_REG62_SET_MH_DBG_DEFAULT(mh_debug_reg62_reg, mh_dbg_default) \ + mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_MH_DBG_DEFAULT_MASK) | (mh_dbg_default << MH_DEBUG_REG62_MH_DBG_DEFAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg62_t { + unsigned int mh_dbg_default : MH_DEBUG_REG62_MH_DBG_DEFAULT_SIZE; + } mh_debug_reg62_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg62_t { + unsigned int mh_dbg_default : MH_DEBUG_REG62_MH_DBG_DEFAULT_SIZE; + } mh_debug_reg62_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg62_t f; +} mh_debug_reg62_u; + + +/* + * MH_DEBUG_REG63 struct + */ + +#define MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE 32 + +#define MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT 0 + +#define MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK 0xffffffff + +#define MH_DEBUG_REG63_MASK \ + (MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) + +#define MH_DEBUG_REG63(mh_dbg_default) \ + ((mh_dbg_default << MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT)) + +#define MH_DEBUG_REG63_GET_MH_DBG_DEFAULT(mh_debug_reg63) \ + ((mh_debug_reg63 & MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) >> MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT) + +#define MH_DEBUG_REG63_SET_MH_DBG_DEFAULT(mh_debug_reg63_reg, mh_dbg_default) \ + mh_debug_reg63_reg = (mh_debug_reg63_reg & ~MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) | (mh_dbg_default << MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg63_t { + unsigned int mh_dbg_default : MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE; + } mh_debug_reg63_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg63_t { + unsigned int mh_dbg_default : MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE; + } mh_debug_reg63_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg63_t f; +} mh_debug_reg63_u; + + +/* + * MH_MMU_CONFIG struct + */ + +#define MH_MMU_CONFIG_MMU_ENABLE_SIZE 1 +#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE 1 +#define MH_MMU_CONFIG_RESERVED1_SIZE 2 +#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE 2 + +#define MH_MMU_CONFIG_MMU_ENABLE_SHIFT 0 +#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT 1 +#define MH_MMU_CONFIG_RESERVED1_SHIFT 2 +#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT 4 +#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT 6 +#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT 8 +#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT 10 +#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT 12 +#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT 14 +#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT 16 +#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT 18 +#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT 20 +#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT 22 + +#define MH_MMU_CONFIG_MMU_ENABLE_MASK 0x00000001 +#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK 0x00000002 +#define MH_MMU_CONFIG_RESERVED1_MASK 0x0000000c +#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK 0x00000030 +#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK 0x000000c0 +#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK 0x00000300 +#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK 0x00000c00 +#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK 0x00003000 +#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK 0x0000c000 +#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK 0x00030000 +#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK 0x000c0000 +#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK 0x00300000 +#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK 0x00c00000 + +#define MH_MMU_CONFIG_MASK \ + (MH_MMU_CONFIG_MMU_ENABLE_MASK | \ + MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK | \ + MH_MMU_CONFIG_RESERVED1_MASK | \ + MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK) + +#define MH_MMU_CONFIG(mmu_enable, split_mode_enable, reserved1, rb_w_clnt_behavior, cp_w_clnt_behavior, cp_r0_clnt_behavior, cp_r1_clnt_behavior, cp_r2_clnt_behavior, cp_r3_clnt_behavior, cp_r4_clnt_behavior, vgt_r0_clnt_behavior, vgt_r1_clnt_behavior, tc_r_clnt_behavior) \ + ((mmu_enable << MH_MMU_CONFIG_MMU_ENABLE_SHIFT) | \ + (split_mode_enable << MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT) | \ + (reserved1 << MH_MMU_CONFIG_RESERVED1_SHIFT) | \ + (rb_w_clnt_behavior << MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT) | \ + (cp_w_clnt_behavior << MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r0_clnt_behavior << MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r1_clnt_behavior << MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r2_clnt_behavior << MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r3_clnt_behavior << MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r4_clnt_behavior << MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT) | \ + (vgt_r0_clnt_behavior << MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT) | \ + (vgt_r1_clnt_behavior << MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT) | \ + (tc_r_clnt_behavior << MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT)) + +#define MH_MMU_CONFIG_GET_MMU_ENABLE(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_MMU_ENABLE_MASK) >> MH_MMU_CONFIG_MMU_ENABLE_SHIFT) +#define MH_MMU_CONFIG_GET_SPLIT_MODE_ENABLE(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK) >> MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT) +#define MH_MMU_CONFIG_GET_RESERVED1(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_RESERVED1_MASK) >> MH_MMU_CONFIG_RESERVED1_SHIFT) +#define MH_MMU_CONFIG_GET_RB_W_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_W_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R0_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R1_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R2_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R3_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R4_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_VGT_R0_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_VGT_R1_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_TC_R_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT) + +#define MH_MMU_CONFIG_SET_MMU_ENABLE(mh_mmu_config_reg, mmu_enable) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_MMU_ENABLE_MASK) | (mmu_enable << MH_MMU_CONFIG_MMU_ENABLE_SHIFT) +#define MH_MMU_CONFIG_SET_SPLIT_MODE_ENABLE(mh_mmu_config_reg, split_mode_enable) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK) | (split_mode_enable << MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT) +#define MH_MMU_CONFIG_SET_RESERVED1(mh_mmu_config_reg, reserved1) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_RESERVED1_MASK) | (reserved1 << MH_MMU_CONFIG_RESERVED1_SHIFT) +#define MH_MMU_CONFIG_SET_RB_W_CLNT_BEHAVIOR(mh_mmu_config_reg, rb_w_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK) | (rb_w_clnt_behavior << MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_W_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_w_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK) | (cp_w_clnt_behavior << MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R0_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r0_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK) | (cp_r0_clnt_behavior << MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R1_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r1_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK) | (cp_r1_clnt_behavior << MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R2_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r2_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK) | (cp_r2_clnt_behavior << MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R3_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r3_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK) | (cp_r3_clnt_behavior << MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R4_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r4_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK) | (cp_r4_clnt_behavior << MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_VGT_R0_CLNT_BEHAVIOR(mh_mmu_config_reg, vgt_r0_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK) | (vgt_r0_clnt_behavior << MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_VGT_R1_CLNT_BEHAVIOR(mh_mmu_config_reg, vgt_r1_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK) | (vgt_r1_clnt_behavior << MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_TC_R_CLNT_BEHAVIOR(mh_mmu_config_reg, tc_r_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK) | (tc_r_clnt_behavior << MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_config_t { + unsigned int mmu_enable : MH_MMU_CONFIG_MMU_ENABLE_SIZE; + unsigned int split_mode_enable : MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE; + unsigned int reserved1 : MH_MMU_CONFIG_RESERVED1_SIZE; + unsigned int rb_w_clnt_behavior : MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE; + unsigned int cp_w_clnt_behavior : MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r0_clnt_behavior : MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r1_clnt_behavior : MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r2_clnt_behavior : MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r3_clnt_behavior : MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r4_clnt_behavior : MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE; + unsigned int vgt_r0_clnt_behavior : MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE; + unsigned int vgt_r1_clnt_behavior : MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE; + unsigned int tc_r_clnt_behavior : MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE; + unsigned int : 8; + } mh_mmu_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_config_t { + unsigned int : 8; + unsigned int tc_r_clnt_behavior : MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE; + unsigned int vgt_r1_clnt_behavior : MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE; + unsigned int vgt_r0_clnt_behavior : MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r4_clnt_behavior : MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r3_clnt_behavior : MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r2_clnt_behavior : MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r1_clnt_behavior : MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r0_clnt_behavior : MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE; + unsigned int cp_w_clnt_behavior : MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE; + unsigned int rb_w_clnt_behavior : MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE; + unsigned int reserved1 : MH_MMU_CONFIG_RESERVED1_SIZE; + unsigned int split_mode_enable : MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE; + unsigned int mmu_enable : MH_MMU_CONFIG_MMU_ENABLE_SIZE; + } mh_mmu_config_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_config_t f; +} mh_mmu_config_u; + + +/* + * MH_MMU_VA_RANGE struct + */ + +#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE 12 +#define MH_MMU_VA_RANGE_VA_BASE_SIZE 20 + +#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT 0 +#define MH_MMU_VA_RANGE_VA_BASE_SHIFT 12 + +#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK 0x00000fff +#define MH_MMU_VA_RANGE_VA_BASE_MASK 0xfffff000 + +#define MH_MMU_VA_RANGE_MASK \ + (MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK | \ + MH_MMU_VA_RANGE_VA_BASE_MASK) + +#define MH_MMU_VA_RANGE(num_64kb_regions, va_base) \ + ((num_64kb_regions << MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT) | \ + (va_base << MH_MMU_VA_RANGE_VA_BASE_SHIFT)) + +#define MH_MMU_VA_RANGE_GET_NUM_64KB_REGIONS(mh_mmu_va_range) \ + ((mh_mmu_va_range & MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK) >> MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT) +#define MH_MMU_VA_RANGE_GET_VA_BASE(mh_mmu_va_range) \ + ((mh_mmu_va_range & MH_MMU_VA_RANGE_VA_BASE_MASK) >> MH_MMU_VA_RANGE_VA_BASE_SHIFT) + +#define MH_MMU_VA_RANGE_SET_NUM_64KB_REGIONS(mh_mmu_va_range_reg, num_64kb_regions) \ + mh_mmu_va_range_reg = (mh_mmu_va_range_reg & ~MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK) | (num_64kb_regions << MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT) +#define MH_MMU_VA_RANGE_SET_VA_BASE(mh_mmu_va_range_reg, va_base) \ + mh_mmu_va_range_reg = (mh_mmu_va_range_reg & ~MH_MMU_VA_RANGE_VA_BASE_MASK) | (va_base << MH_MMU_VA_RANGE_VA_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_va_range_t { + unsigned int num_64kb_regions : MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE; + unsigned int va_base : MH_MMU_VA_RANGE_VA_BASE_SIZE; + } mh_mmu_va_range_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_va_range_t { + unsigned int va_base : MH_MMU_VA_RANGE_VA_BASE_SIZE; + unsigned int num_64kb_regions : MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE; + } mh_mmu_va_range_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_va_range_t f; +} mh_mmu_va_range_u; + + +/* + * MH_MMU_PT_BASE struct + */ + +#define MH_MMU_PT_BASE_PT_BASE_SIZE 20 + +#define MH_MMU_PT_BASE_PT_BASE_SHIFT 12 + +#define MH_MMU_PT_BASE_PT_BASE_MASK 0xfffff000 + +#define MH_MMU_PT_BASE_MASK \ + (MH_MMU_PT_BASE_PT_BASE_MASK) + +#define MH_MMU_PT_BASE(pt_base) \ + ((pt_base << MH_MMU_PT_BASE_PT_BASE_SHIFT)) + +#define MH_MMU_PT_BASE_GET_PT_BASE(mh_mmu_pt_base) \ + ((mh_mmu_pt_base & MH_MMU_PT_BASE_PT_BASE_MASK) >> MH_MMU_PT_BASE_PT_BASE_SHIFT) + +#define MH_MMU_PT_BASE_SET_PT_BASE(mh_mmu_pt_base_reg, pt_base) \ + mh_mmu_pt_base_reg = (mh_mmu_pt_base_reg & ~MH_MMU_PT_BASE_PT_BASE_MASK) | (pt_base << MH_MMU_PT_BASE_PT_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_pt_base_t { + unsigned int : 12; + unsigned int pt_base : MH_MMU_PT_BASE_PT_BASE_SIZE; + } mh_mmu_pt_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_pt_base_t { + unsigned int pt_base : MH_MMU_PT_BASE_PT_BASE_SIZE; + unsigned int : 12; + } mh_mmu_pt_base_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_pt_base_t f; +} mh_mmu_pt_base_u; + + +/* + * MH_MMU_PAGE_FAULT struct + */ + +#define MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE 1 +#define MH_MMU_PAGE_FAULT_OP_TYPE_SIZE 1 +#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_PAGE_FAULT_AXI_ID_SIZE 3 +#define MH_MMU_PAGE_FAULT_RESERVED1_SIZE 1 +#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE 1 +#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE 1 +#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE 1 +#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE 1 +#define MH_MMU_PAGE_FAULT_REQ_VA_SIZE 20 + +#define MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT 0 +#define MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT 1 +#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT 2 +#define MH_MMU_PAGE_FAULT_AXI_ID_SHIFT 4 +#define MH_MMU_PAGE_FAULT_RESERVED1_SHIFT 7 +#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT 8 +#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT 9 +#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT 10 +#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT 11 +#define MH_MMU_PAGE_FAULT_REQ_VA_SHIFT 12 + +#define MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK 0x00000001 +#define MH_MMU_PAGE_FAULT_OP_TYPE_MASK 0x00000002 +#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK 0x0000000c +#define MH_MMU_PAGE_FAULT_AXI_ID_MASK 0x00000070 +#define MH_MMU_PAGE_FAULT_RESERVED1_MASK 0x00000080 +#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK 0x00000100 +#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK 0x00000200 +#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK 0x00000400 +#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK 0x00000800 +#define MH_MMU_PAGE_FAULT_REQ_VA_MASK 0xfffff000 + +#define MH_MMU_PAGE_FAULT_MASK \ + (MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK | \ + MH_MMU_PAGE_FAULT_OP_TYPE_MASK | \ + MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK | \ + MH_MMU_PAGE_FAULT_AXI_ID_MASK | \ + MH_MMU_PAGE_FAULT_RESERVED1_MASK | \ + MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK | \ + MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK | \ + MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK | \ + MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK | \ + MH_MMU_PAGE_FAULT_REQ_VA_MASK) + +#define MH_MMU_PAGE_FAULT(page_fault, op_type, clnt_behavior, axi_id, reserved1, mpu_address_out_of_range, address_out_of_range, read_protection_error, write_protection_error, req_va) \ + ((page_fault << MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT) | \ + (op_type << MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT) | \ + (clnt_behavior << MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT) | \ + (axi_id << MH_MMU_PAGE_FAULT_AXI_ID_SHIFT) | \ + (reserved1 << MH_MMU_PAGE_FAULT_RESERVED1_SHIFT) | \ + (mpu_address_out_of_range << MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT) | \ + (address_out_of_range << MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT) | \ + (read_protection_error << MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT) | \ + (write_protection_error << MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT) | \ + (req_va << MH_MMU_PAGE_FAULT_REQ_VA_SHIFT)) + +#define MH_MMU_PAGE_FAULT_GET_PAGE_FAULT(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK) >> MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_OP_TYPE(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_OP_TYPE_MASK) >> MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_CLNT_BEHAVIOR(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK) >> MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_AXI_ID(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_AXI_ID_MASK) >> MH_MMU_PAGE_FAULT_AXI_ID_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_RESERVED1(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_RESERVED1_MASK) >> MH_MMU_PAGE_FAULT_RESERVED1_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_MPU_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK) >> MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK) >> MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_READ_PROTECTION_ERROR(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK) >> MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_WRITE_PROTECTION_ERROR(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK) >> MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_REQ_VA(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_REQ_VA_MASK) >> MH_MMU_PAGE_FAULT_REQ_VA_SHIFT) + +#define MH_MMU_PAGE_FAULT_SET_PAGE_FAULT(mh_mmu_page_fault_reg, page_fault) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK) | (page_fault << MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_OP_TYPE(mh_mmu_page_fault_reg, op_type) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_OP_TYPE_MASK) | (op_type << MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_CLNT_BEHAVIOR(mh_mmu_page_fault_reg, clnt_behavior) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK) | (clnt_behavior << MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_AXI_ID(mh_mmu_page_fault_reg, axi_id) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_AXI_ID_MASK) | (axi_id << MH_MMU_PAGE_FAULT_AXI_ID_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_RESERVED1(mh_mmu_page_fault_reg, reserved1) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_RESERVED1_MASK) | (reserved1 << MH_MMU_PAGE_FAULT_RESERVED1_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_MPU_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault_reg, mpu_address_out_of_range) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK) | (mpu_address_out_of_range << MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault_reg, address_out_of_range) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK) | (address_out_of_range << MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_READ_PROTECTION_ERROR(mh_mmu_page_fault_reg, read_protection_error) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK) | (read_protection_error << MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_WRITE_PROTECTION_ERROR(mh_mmu_page_fault_reg, write_protection_error) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK) | (write_protection_error << MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_REQ_VA(mh_mmu_page_fault_reg, req_va) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_REQ_VA_MASK) | (req_va << MH_MMU_PAGE_FAULT_REQ_VA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_page_fault_t { + unsigned int page_fault : MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE; + unsigned int op_type : MH_MMU_PAGE_FAULT_OP_TYPE_SIZE; + unsigned int clnt_behavior : MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE; + unsigned int axi_id : MH_MMU_PAGE_FAULT_AXI_ID_SIZE; + unsigned int reserved1 : MH_MMU_PAGE_FAULT_RESERVED1_SIZE; + unsigned int mpu_address_out_of_range : MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE; + unsigned int address_out_of_range : MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE; + unsigned int read_protection_error : MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE; + unsigned int write_protection_error : MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE; + unsigned int req_va : MH_MMU_PAGE_FAULT_REQ_VA_SIZE; + } mh_mmu_page_fault_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_page_fault_t { + unsigned int req_va : MH_MMU_PAGE_FAULT_REQ_VA_SIZE; + unsigned int write_protection_error : MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE; + unsigned int read_protection_error : MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE; + unsigned int address_out_of_range : MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE; + unsigned int mpu_address_out_of_range : MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE; + unsigned int reserved1 : MH_MMU_PAGE_FAULT_RESERVED1_SIZE; + unsigned int axi_id : MH_MMU_PAGE_FAULT_AXI_ID_SIZE; + unsigned int clnt_behavior : MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE; + unsigned int op_type : MH_MMU_PAGE_FAULT_OP_TYPE_SIZE; + unsigned int page_fault : MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE; + } mh_mmu_page_fault_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_page_fault_t f; +} mh_mmu_page_fault_u; + + +/* + * MH_MMU_TRAN_ERROR struct + */ + +#define MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE 27 + +#define MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT 5 + +#define MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK 0xffffffe0 + +#define MH_MMU_TRAN_ERROR_MASK \ + (MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) + +#define MH_MMU_TRAN_ERROR(tran_error) \ + ((tran_error << MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT)) + +#define MH_MMU_TRAN_ERROR_GET_TRAN_ERROR(mh_mmu_tran_error) \ + ((mh_mmu_tran_error & MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) >> MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT) + +#define MH_MMU_TRAN_ERROR_SET_TRAN_ERROR(mh_mmu_tran_error_reg, tran_error) \ + mh_mmu_tran_error_reg = (mh_mmu_tran_error_reg & ~MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) | (tran_error << MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_tran_error_t { + unsigned int : 5; + unsigned int tran_error : MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE; + } mh_mmu_tran_error_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_tran_error_t { + unsigned int tran_error : MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE; + unsigned int : 5; + } mh_mmu_tran_error_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_tran_error_t f; +} mh_mmu_tran_error_u; + + +/* + * MH_MMU_INVALIDATE struct + */ + +#define MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE 1 +#define MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE 1 + +#define MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT 0 +#define MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT 1 + +#define MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00000001 +#define MH_MMU_INVALIDATE_INVALIDATE_TC_MASK 0x00000002 + +#define MH_MMU_INVALIDATE_MASK \ + (MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK | \ + MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) + +#define MH_MMU_INVALIDATE(invalidate_all, invalidate_tc) \ + ((invalidate_all << MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) | \ + (invalidate_tc << MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT)) + +#define MH_MMU_INVALIDATE_GET_INVALIDATE_ALL(mh_mmu_invalidate) \ + ((mh_mmu_invalidate & MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) >> MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) +#define MH_MMU_INVALIDATE_GET_INVALIDATE_TC(mh_mmu_invalidate) \ + ((mh_mmu_invalidate & MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) >> MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT) + +#define MH_MMU_INVALIDATE_SET_INVALIDATE_ALL(mh_mmu_invalidate_reg, invalidate_all) \ + mh_mmu_invalidate_reg = (mh_mmu_invalidate_reg & ~MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) | (invalidate_all << MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) +#define MH_MMU_INVALIDATE_SET_INVALIDATE_TC(mh_mmu_invalidate_reg, invalidate_tc) \ + mh_mmu_invalidate_reg = (mh_mmu_invalidate_reg & ~MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) | (invalidate_tc << MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_invalidate_t { + unsigned int invalidate_all : MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE; + unsigned int invalidate_tc : MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE; + unsigned int : 30; + } mh_mmu_invalidate_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_invalidate_t { + unsigned int : 30; + unsigned int invalidate_tc : MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE; + unsigned int invalidate_all : MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE; + } mh_mmu_invalidate_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_invalidate_t f; +} mh_mmu_invalidate_u; + + +/* + * MH_MMU_MPU_BASE struct + */ + +#define MH_MMU_MPU_BASE_MPU_BASE_SIZE 20 + +#define MH_MMU_MPU_BASE_MPU_BASE_SHIFT 12 + +#define MH_MMU_MPU_BASE_MPU_BASE_MASK 0xfffff000 + +#define MH_MMU_MPU_BASE_MASK \ + (MH_MMU_MPU_BASE_MPU_BASE_MASK) + +#define MH_MMU_MPU_BASE(mpu_base) \ + ((mpu_base << MH_MMU_MPU_BASE_MPU_BASE_SHIFT)) + +#define MH_MMU_MPU_BASE_GET_MPU_BASE(mh_mmu_mpu_base) \ + ((mh_mmu_mpu_base & MH_MMU_MPU_BASE_MPU_BASE_MASK) >> MH_MMU_MPU_BASE_MPU_BASE_SHIFT) + +#define MH_MMU_MPU_BASE_SET_MPU_BASE(mh_mmu_mpu_base_reg, mpu_base) \ + mh_mmu_mpu_base_reg = (mh_mmu_mpu_base_reg & ~MH_MMU_MPU_BASE_MPU_BASE_MASK) | (mpu_base << MH_MMU_MPU_BASE_MPU_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_mpu_base_t { + unsigned int : 12; + unsigned int mpu_base : MH_MMU_MPU_BASE_MPU_BASE_SIZE; + } mh_mmu_mpu_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_mpu_base_t { + unsigned int mpu_base : MH_MMU_MPU_BASE_MPU_BASE_SIZE; + unsigned int : 12; + } mh_mmu_mpu_base_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_mpu_base_t f; +} mh_mmu_mpu_base_u; + + +/* + * MH_MMU_MPU_END struct + */ + +#define MH_MMU_MPU_END_MPU_END_SIZE 20 + +#define MH_MMU_MPU_END_MPU_END_SHIFT 12 + +#define MH_MMU_MPU_END_MPU_END_MASK 0xfffff000 + +#define MH_MMU_MPU_END_MASK \ + (MH_MMU_MPU_END_MPU_END_MASK) + +#define MH_MMU_MPU_END(mpu_end) \ + ((mpu_end << MH_MMU_MPU_END_MPU_END_SHIFT)) + +#define MH_MMU_MPU_END_GET_MPU_END(mh_mmu_mpu_end) \ + ((mh_mmu_mpu_end & MH_MMU_MPU_END_MPU_END_MASK) >> MH_MMU_MPU_END_MPU_END_SHIFT) + +#define MH_MMU_MPU_END_SET_MPU_END(mh_mmu_mpu_end_reg, mpu_end) \ + mh_mmu_mpu_end_reg = (mh_mmu_mpu_end_reg & ~MH_MMU_MPU_END_MPU_END_MASK) | (mpu_end << MH_MMU_MPU_END_MPU_END_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_mpu_end_t { + unsigned int : 12; + unsigned int mpu_end : MH_MMU_MPU_END_MPU_END_SIZE; + } mh_mmu_mpu_end_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_mpu_end_t { + unsigned int mpu_end : MH_MMU_MPU_END_MPU_END_SIZE; + unsigned int : 12; + } mh_mmu_mpu_end_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_mpu_end_t f; +} mh_mmu_mpu_end_u; + + +#endif + + +#if !defined (_PA_FIDDLE_H) +#define _PA_FIDDLE_H + +/***************************************************************************************************************** + * + * pa_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * PA_CL_VPORT_XSCALE struct + */ + +#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE 32 + +#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT 0 + +#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK 0xffffffff + +#define PA_CL_VPORT_XSCALE_MASK \ + (PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) + +#define PA_CL_VPORT_XSCALE(vport_xscale) \ + ((vport_xscale << PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT)) + +#define PA_CL_VPORT_XSCALE_GET_VPORT_XSCALE(pa_cl_vport_xscale) \ + ((pa_cl_vport_xscale & PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) >> PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT) + +#define PA_CL_VPORT_XSCALE_SET_VPORT_XSCALE(pa_cl_vport_xscale_reg, vport_xscale) \ + pa_cl_vport_xscale_reg = (pa_cl_vport_xscale_reg & ~PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) | (vport_xscale << PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_xscale_t { + unsigned int vport_xscale : PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE; + } pa_cl_vport_xscale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_xscale_t { + unsigned int vport_xscale : PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE; + } pa_cl_vport_xscale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_xscale_t f; +} pa_cl_vport_xscale_u; + + +/* + * PA_CL_VPORT_XOFFSET struct + */ + +#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE 32 + +#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT 0 + +#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK 0xffffffff + +#define PA_CL_VPORT_XOFFSET_MASK \ + (PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) + +#define PA_CL_VPORT_XOFFSET(vport_xoffset) \ + ((vport_xoffset << PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT)) + +#define PA_CL_VPORT_XOFFSET_GET_VPORT_XOFFSET(pa_cl_vport_xoffset) \ + ((pa_cl_vport_xoffset & PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) >> PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT) + +#define PA_CL_VPORT_XOFFSET_SET_VPORT_XOFFSET(pa_cl_vport_xoffset_reg, vport_xoffset) \ + pa_cl_vport_xoffset_reg = (pa_cl_vport_xoffset_reg & ~PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) | (vport_xoffset << PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_xoffset_t { + unsigned int vport_xoffset : PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE; + } pa_cl_vport_xoffset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_xoffset_t { + unsigned int vport_xoffset : PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE; + } pa_cl_vport_xoffset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_xoffset_t f; +} pa_cl_vport_xoffset_u; + + +/* + * PA_CL_VPORT_YSCALE struct + */ + +#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE 32 + +#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT 0 + +#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK 0xffffffff + +#define PA_CL_VPORT_YSCALE_MASK \ + (PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) + +#define PA_CL_VPORT_YSCALE(vport_yscale) \ + ((vport_yscale << PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT)) + +#define PA_CL_VPORT_YSCALE_GET_VPORT_YSCALE(pa_cl_vport_yscale) \ + ((pa_cl_vport_yscale & PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) >> PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT) + +#define PA_CL_VPORT_YSCALE_SET_VPORT_YSCALE(pa_cl_vport_yscale_reg, vport_yscale) \ + pa_cl_vport_yscale_reg = (pa_cl_vport_yscale_reg & ~PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) | (vport_yscale << PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_yscale_t { + unsigned int vport_yscale : PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE; + } pa_cl_vport_yscale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_yscale_t { + unsigned int vport_yscale : PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE; + } pa_cl_vport_yscale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_yscale_t f; +} pa_cl_vport_yscale_u; + + +/* + * PA_CL_VPORT_YOFFSET struct + */ + +#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE 32 + +#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT 0 + +#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK 0xffffffff + +#define PA_CL_VPORT_YOFFSET_MASK \ + (PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) + +#define PA_CL_VPORT_YOFFSET(vport_yoffset) \ + ((vport_yoffset << PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT)) + +#define PA_CL_VPORT_YOFFSET_GET_VPORT_YOFFSET(pa_cl_vport_yoffset) \ + ((pa_cl_vport_yoffset & PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) >> PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT) + +#define PA_CL_VPORT_YOFFSET_SET_VPORT_YOFFSET(pa_cl_vport_yoffset_reg, vport_yoffset) \ + pa_cl_vport_yoffset_reg = (pa_cl_vport_yoffset_reg & ~PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) | (vport_yoffset << PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_yoffset_t { + unsigned int vport_yoffset : PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE; + } pa_cl_vport_yoffset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_yoffset_t { + unsigned int vport_yoffset : PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE; + } pa_cl_vport_yoffset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_yoffset_t f; +} pa_cl_vport_yoffset_u; + + +/* + * PA_CL_VPORT_ZSCALE struct + */ + +#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE 32 + +#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT 0 + +#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK 0xffffffff + +#define PA_CL_VPORT_ZSCALE_MASK \ + (PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) + +#define PA_CL_VPORT_ZSCALE(vport_zscale) \ + ((vport_zscale << PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT)) + +#define PA_CL_VPORT_ZSCALE_GET_VPORT_ZSCALE(pa_cl_vport_zscale) \ + ((pa_cl_vport_zscale & PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) >> PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT) + +#define PA_CL_VPORT_ZSCALE_SET_VPORT_ZSCALE(pa_cl_vport_zscale_reg, vport_zscale) \ + pa_cl_vport_zscale_reg = (pa_cl_vport_zscale_reg & ~PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) | (vport_zscale << PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_zscale_t { + unsigned int vport_zscale : PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE; + } pa_cl_vport_zscale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_zscale_t { + unsigned int vport_zscale : PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE; + } pa_cl_vport_zscale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_zscale_t f; +} pa_cl_vport_zscale_u; + + +/* + * PA_CL_VPORT_ZOFFSET struct + */ + +#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE 32 + +#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT 0 + +#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK 0xffffffff + +#define PA_CL_VPORT_ZOFFSET_MASK \ + (PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) + +#define PA_CL_VPORT_ZOFFSET(vport_zoffset) \ + ((vport_zoffset << PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT)) + +#define PA_CL_VPORT_ZOFFSET_GET_VPORT_ZOFFSET(pa_cl_vport_zoffset) \ + ((pa_cl_vport_zoffset & PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) >> PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT) + +#define PA_CL_VPORT_ZOFFSET_SET_VPORT_ZOFFSET(pa_cl_vport_zoffset_reg, vport_zoffset) \ + pa_cl_vport_zoffset_reg = (pa_cl_vport_zoffset_reg & ~PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) | (vport_zoffset << PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_zoffset_t { + unsigned int vport_zoffset : PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE; + } pa_cl_vport_zoffset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_zoffset_t { + unsigned int vport_zoffset : PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE; + } pa_cl_vport_zoffset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_zoffset_t f; +} pa_cl_vport_zoffset_u; + + +/* + * PA_CL_VTE_CNTL struct + */ + +#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE 1 +#define PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE 1 +#define PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE 1 +#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE 1 + +#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT 0 +#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT 1 +#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT 2 +#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT 3 +#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT 4 +#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT 5 +#define PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT 8 +#define PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT 9 +#define PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT 10 +#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT 11 + +#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK 0x00000001 +#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK 0x00000002 +#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK 0x00000004 +#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK 0x00000008 +#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK 0x00000010 +#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK 0x00000020 +#define PA_CL_VTE_CNTL_VTX_XY_FMT_MASK 0x00000100 +#define PA_CL_VTE_CNTL_VTX_Z_FMT_MASK 0x00000200 +#define PA_CL_VTE_CNTL_VTX_W0_FMT_MASK 0x00000400 +#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK 0x00000800 + +#define PA_CL_VTE_CNTL_MASK \ + (PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK | \ + PA_CL_VTE_CNTL_VTX_XY_FMT_MASK | \ + PA_CL_VTE_CNTL_VTX_Z_FMT_MASK | \ + PA_CL_VTE_CNTL_VTX_W0_FMT_MASK | \ + PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) + +#define PA_CL_VTE_CNTL(vport_x_scale_ena, vport_x_offset_ena, vport_y_scale_ena, vport_y_offset_ena, vport_z_scale_ena, vport_z_offset_ena, vtx_xy_fmt, vtx_z_fmt, vtx_w0_fmt, perfcounter_ref) \ + ((vport_x_scale_ena << PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT) | \ + (vport_x_offset_ena << PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT) | \ + (vport_y_scale_ena << PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT) | \ + (vport_y_offset_ena << PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT) | \ + (vport_z_scale_ena << PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT) | \ + (vport_z_offset_ena << PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT) | \ + (vtx_xy_fmt << PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT) | \ + (vtx_z_fmt << PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT) | \ + (vtx_w0_fmt << PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT) | \ + (perfcounter_ref << PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT)) + +#define PA_CL_VTE_CNTL_GET_VPORT_X_SCALE_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_X_OFFSET_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_Y_SCALE_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_Y_OFFSET_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_Z_SCALE_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_Z_OFFSET_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VTX_XY_FMT(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_XY_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT) +#define PA_CL_VTE_CNTL_GET_VTX_Z_FMT(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_Z_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT) +#define PA_CL_VTE_CNTL_GET_VTX_W0_FMT(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_W0_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT) +#define PA_CL_VTE_CNTL_GET_PERFCOUNTER_REF(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) >> PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT) + +#define PA_CL_VTE_CNTL_SET_VPORT_X_SCALE_ENA(pa_cl_vte_cntl_reg, vport_x_scale_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK) | (vport_x_scale_ena << PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_X_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_x_offset_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK) | (vport_x_offset_ena << PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_Y_SCALE_ENA(pa_cl_vte_cntl_reg, vport_y_scale_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK) | (vport_y_scale_ena << PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_Y_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_y_offset_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK) | (vport_y_offset_ena << PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_Z_SCALE_ENA(pa_cl_vte_cntl_reg, vport_z_scale_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK) | (vport_z_scale_ena << PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_Z_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_z_offset_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK) | (vport_z_offset_ena << PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VTX_XY_FMT(pa_cl_vte_cntl_reg, vtx_xy_fmt) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_XY_FMT_MASK) | (vtx_xy_fmt << PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT) +#define PA_CL_VTE_CNTL_SET_VTX_Z_FMT(pa_cl_vte_cntl_reg, vtx_z_fmt) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_Z_FMT_MASK) | (vtx_z_fmt << PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT) +#define PA_CL_VTE_CNTL_SET_VTX_W0_FMT(pa_cl_vte_cntl_reg, vtx_w0_fmt) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_W0_FMT_MASK) | (vtx_w0_fmt << PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT) +#define PA_CL_VTE_CNTL_SET_PERFCOUNTER_REF(pa_cl_vte_cntl_reg, perfcounter_ref) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) | (perfcounter_ref << PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vte_cntl_t { + unsigned int vport_x_scale_ena : PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE; + unsigned int vport_x_offset_ena : PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE; + unsigned int vport_y_scale_ena : PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE; + unsigned int vport_y_offset_ena : PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE; + unsigned int vport_z_scale_ena : PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE; + unsigned int vport_z_offset_ena : PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE; + unsigned int : 2; + unsigned int vtx_xy_fmt : PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE; + unsigned int vtx_z_fmt : PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE; + unsigned int vtx_w0_fmt : PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE; + unsigned int perfcounter_ref : PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE; + unsigned int : 20; + } pa_cl_vte_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vte_cntl_t { + unsigned int : 20; + unsigned int perfcounter_ref : PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE; + unsigned int vtx_w0_fmt : PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE; + unsigned int vtx_z_fmt : PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE; + unsigned int vtx_xy_fmt : PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE; + unsigned int : 2; + unsigned int vport_z_offset_ena : PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE; + unsigned int vport_z_scale_ena : PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE; + unsigned int vport_y_offset_ena : PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE; + unsigned int vport_y_scale_ena : PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE; + unsigned int vport_x_offset_ena : PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE; + unsigned int vport_x_scale_ena : PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE; + } pa_cl_vte_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vte_cntl_t f; +} pa_cl_vte_cntl_u; + + +/* + * PA_CL_CLIP_CNTL struct + */ + +#define PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE 1 +#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE 1 +#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE 1 +#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE 1 +#define PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE 1 +#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE 1 +#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE 1 +#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE 1 + +#define PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT 16 +#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT 18 +#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT 19 +#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT 20 +#define PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT 21 +#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT 22 +#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT 23 +#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT 24 + +#define PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK 0x00010000 +#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000 +#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK 0x00080000 +#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK 0x00100000 +#define PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK 0x00200000 +#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK 0x00400000 +#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK 0x00800000 +#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK 0x01000000 + +#define PA_CL_CLIP_CNTL_MASK \ + (PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK | \ + PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK | \ + PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK | \ + PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK | \ + PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK | \ + PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK | \ + PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK | \ + PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) + +#define PA_CL_CLIP_CNTL(clip_disable, boundary_edge_flag_ena, dx_clip_space_def, dis_clip_err_detect, vtx_kill_or, xy_nan_retain, z_nan_retain, w_nan_retain) \ + ((clip_disable << PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT) | \ + (boundary_edge_flag_ena << PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT) | \ + (dx_clip_space_def << PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT) | \ + (dis_clip_err_detect << PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT) | \ + (vtx_kill_or << PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT) | \ + (xy_nan_retain << PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT) | \ + (z_nan_retain << PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT) | \ + (w_nan_retain << PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT)) + +#define PA_CL_CLIP_CNTL_GET_CLIP_DISABLE(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK) >> PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT) +#define PA_CL_CLIP_CNTL_GET_BOUNDARY_EDGE_FLAG_ENA(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK) >> PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT) +#define PA_CL_CLIP_CNTL_GET_DX_CLIP_SPACE_DEF(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK) >> PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT) +#define PA_CL_CLIP_CNTL_GET_DIS_CLIP_ERR_DETECT(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK) >> PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT) +#define PA_CL_CLIP_CNTL_GET_VTX_KILL_OR(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK) >> PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT) +#define PA_CL_CLIP_CNTL_GET_XY_NAN_RETAIN(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT) +#define PA_CL_CLIP_CNTL_GET_Z_NAN_RETAIN(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT) +#define PA_CL_CLIP_CNTL_GET_W_NAN_RETAIN(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT) + +#define PA_CL_CLIP_CNTL_SET_CLIP_DISABLE(pa_cl_clip_cntl_reg, clip_disable) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK) | (clip_disable << PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT) +#define PA_CL_CLIP_CNTL_SET_BOUNDARY_EDGE_FLAG_ENA(pa_cl_clip_cntl_reg, boundary_edge_flag_ena) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK) | (boundary_edge_flag_ena << PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT) +#define PA_CL_CLIP_CNTL_SET_DX_CLIP_SPACE_DEF(pa_cl_clip_cntl_reg, dx_clip_space_def) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK) | (dx_clip_space_def << PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT) +#define PA_CL_CLIP_CNTL_SET_DIS_CLIP_ERR_DETECT(pa_cl_clip_cntl_reg, dis_clip_err_detect) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK) | (dis_clip_err_detect << PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT) +#define PA_CL_CLIP_CNTL_SET_VTX_KILL_OR(pa_cl_clip_cntl_reg, vtx_kill_or) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK) | (vtx_kill_or << PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT) +#define PA_CL_CLIP_CNTL_SET_XY_NAN_RETAIN(pa_cl_clip_cntl_reg, xy_nan_retain) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK) | (xy_nan_retain << PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT) +#define PA_CL_CLIP_CNTL_SET_Z_NAN_RETAIN(pa_cl_clip_cntl_reg, z_nan_retain) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK) | (z_nan_retain << PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT) +#define PA_CL_CLIP_CNTL_SET_W_NAN_RETAIN(pa_cl_clip_cntl_reg, w_nan_retain) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) | (w_nan_retain << PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_clip_cntl_t { + unsigned int : 16; + unsigned int clip_disable : PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE; + unsigned int : 1; + unsigned int boundary_edge_flag_ena : PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE; + unsigned int dx_clip_space_def : PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE; + unsigned int dis_clip_err_detect : PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE; + unsigned int vtx_kill_or : PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE; + unsigned int xy_nan_retain : PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE; + unsigned int z_nan_retain : PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE; + unsigned int w_nan_retain : PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE; + unsigned int : 7; + } pa_cl_clip_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_clip_cntl_t { + unsigned int : 7; + unsigned int w_nan_retain : PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE; + unsigned int z_nan_retain : PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE; + unsigned int xy_nan_retain : PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE; + unsigned int vtx_kill_or : PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE; + unsigned int dis_clip_err_detect : PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE; + unsigned int dx_clip_space_def : PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE; + unsigned int boundary_edge_flag_ena : PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE; + unsigned int : 1; + unsigned int clip_disable : PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE; + unsigned int : 16; + } pa_cl_clip_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_clip_cntl_t f; +} pa_cl_clip_cntl_u; + + +/* + * PA_CL_GB_VERT_CLIP_ADJ struct + */ + +#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE 32 + +#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT 0 + +#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK 0xffffffff + +#define PA_CL_GB_VERT_CLIP_ADJ_MASK \ + (PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) + +#define PA_CL_GB_VERT_CLIP_ADJ(data_register) \ + ((data_register << PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT)) + +#define PA_CL_GB_VERT_CLIP_ADJ_GET_DATA_REGISTER(pa_cl_gb_vert_clip_adj) \ + ((pa_cl_gb_vert_clip_adj & PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT) + +#define PA_CL_GB_VERT_CLIP_ADJ_SET_DATA_REGISTER(pa_cl_gb_vert_clip_adj_reg, data_register) \ + pa_cl_gb_vert_clip_adj_reg = (pa_cl_gb_vert_clip_adj_reg & ~PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_gb_vert_clip_adj_t { + unsigned int data_register : PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_vert_clip_adj_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_gb_vert_clip_adj_t { + unsigned int data_register : PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_vert_clip_adj_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_gb_vert_clip_adj_t f; +} pa_cl_gb_vert_clip_adj_u; + + +/* + * PA_CL_GB_VERT_DISC_ADJ struct + */ + +#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE 32 + +#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT 0 + +#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK 0xffffffff + +#define PA_CL_GB_VERT_DISC_ADJ_MASK \ + (PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) + +#define PA_CL_GB_VERT_DISC_ADJ(data_register) \ + ((data_register << PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT)) + +#define PA_CL_GB_VERT_DISC_ADJ_GET_DATA_REGISTER(pa_cl_gb_vert_disc_adj) \ + ((pa_cl_gb_vert_disc_adj & PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT) + +#define PA_CL_GB_VERT_DISC_ADJ_SET_DATA_REGISTER(pa_cl_gb_vert_disc_adj_reg, data_register) \ + pa_cl_gb_vert_disc_adj_reg = (pa_cl_gb_vert_disc_adj_reg & ~PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_gb_vert_disc_adj_t { + unsigned int data_register : PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_vert_disc_adj_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_gb_vert_disc_adj_t { + unsigned int data_register : PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_vert_disc_adj_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_gb_vert_disc_adj_t f; +} pa_cl_gb_vert_disc_adj_u; + + +/* + * PA_CL_GB_HORZ_CLIP_ADJ struct + */ + +#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE 32 + +#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT 0 + +#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK 0xffffffff + +#define PA_CL_GB_HORZ_CLIP_ADJ_MASK \ + (PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) + +#define PA_CL_GB_HORZ_CLIP_ADJ(data_register) \ + ((data_register << PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT)) + +#define PA_CL_GB_HORZ_CLIP_ADJ_GET_DATA_REGISTER(pa_cl_gb_horz_clip_adj) \ + ((pa_cl_gb_horz_clip_adj & PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT) + +#define PA_CL_GB_HORZ_CLIP_ADJ_SET_DATA_REGISTER(pa_cl_gb_horz_clip_adj_reg, data_register) \ + pa_cl_gb_horz_clip_adj_reg = (pa_cl_gb_horz_clip_adj_reg & ~PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_gb_horz_clip_adj_t { + unsigned int data_register : PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_horz_clip_adj_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_gb_horz_clip_adj_t { + unsigned int data_register : PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_horz_clip_adj_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_gb_horz_clip_adj_t f; +} pa_cl_gb_horz_clip_adj_u; + + +/* + * PA_CL_GB_HORZ_DISC_ADJ struct + */ + +#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE 32 + +#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT 0 + +#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK 0xffffffff + +#define PA_CL_GB_HORZ_DISC_ADJ_MASK \ + (PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) + +#define PA_CL_GB_HORZ_DISC_ADJ(data_register) \ + ((data_register << PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT)) + +#define PA_CL_GB_HORZ_DISC_ADJ_GET_DATA_REGISTER(pa_cl_gb_horz_disc_adj) \ + ((pa_cl_gb_horz_disc_adj & PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT) + +#define PA_CL_GB_HORZ_DISC_ADJ_SET_DATA_REGISTER(pa_cl_gb_horz_disc_adj_reg, data_register) \ + pa_cl_gb_horz_disc_adj_reg = (pa_cl_gb_horz_disc_adj_reg & ~PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_gb_horz_disc_adj_t { + unsigned int data_register : PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_horz_disc_adj_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_gb_horz_disc_adj_t { + unsigned int data_register : PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_horz_disc_adj_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_gb_horz_disc_adj_t f; +} pa_cl_gb_horz_disc_adj_u; + + +/* + * PA_CL_ENHANCE struct + */ + +#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE 1 +#define PA_CL_ENHANCE_ECO_SPARE3_SIZE 1 +#define PA_CL_ENHANCE_ECO_SPARE2_SIZE 1 +#define PA_CL_ENHANCE_ECO_SPARE1_SIZE 1 +#define PA_CL_ENHANCE_ECO_SPARE0_SIZE 1 + +#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT 0 +#define PA_CL_ENHANCE_ECO_SPARE3_SHIFT 28 +#define PA_CL_ENHANCE_ECO_SPARE2_SHIFT 29 +#define PA_CL_ENHANCE_ECO_SPARE1_SHIFT 30 +#define PA_CL_ENHANCE_ECO_SPARE0_SHIFT 31 + +#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK 0x00000001 +#define PA_CL_ENHANCE_ECO_SPARE3_MASK 0x10000000 +#define PA_CL_ENHANCE_ECO_SPARE2_MASK 0x20000000 +#define PA_CL_ENHANCE_ECO_SPARE1_MASK 0x40000000 +#define PA_CL_ENHANCE_ECO_SPARE0_MASK 0x80000000 + +#define PA_CL_ENHANCE_MASK \ + (PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK | \ + PA_CL_ENHANCE_ECO_SPARE3_MASK | \ + PA_CL_ENHANCE_ECO_SPARE2_MASK | \ + PA_CL_ENHANCE_ECO_SPARE1_MASK | \ + PA_CL_ENHANCE_ECO_SPARE0_MASK) + +#define PA_CL_ENHANCE(clip_vtx_reorder_ena, eco_spare3, eco_spare2, eco_spare1, eco_spare0) \ + ((clip_vtx_reorder_ena << PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT) | \ + (eco_spare3 << PA_CL_ENHANCE_ECO_SPARE3_SHIFT) | \ + (eco_spare2 << PA_CL_ENHANCE_ECO_SPARE2_SHIFT) | \ + (eco_spare1 << PA_CL_ENHANCE_ECO_SPARE1_SHIFT) | \ + (eco_spare0 << PA_CL_ENHANCE_ECO_SPARE0_SHIFT)) + +#define PA_CL_ENHANCE_GET_CLIP_VTX_REORDER_ENA(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK) >> PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT) +#define PA_CL_ENHANCE_GET_ECO_SPARE3(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE3_MASK) >> PA_CL_ENHANCE_ECO_SPARE3_SHIFT) +#define PA_CL_ENHANCE_GET_ECO_SPARE2(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE2_MASK) >> PA_CL_ENHANCE_ECO_SPARE2_SHIFT) +#define PA_CL_ENHANCE_GET_ECO_SPARE1(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE1_MASK) >> PA_CL_ENHANCE_ECO_SPARE1_SHIFT) +#define PA_CL_ENHANCE_GET_ECO_SPARE0(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE0_MASK) >> PA_CL_ENHANCE_ECO_SPARE0_SHIFT) + +#define PA_CL_ENHANCE_SET_CLIP_VTX_REORDER_ENA(pa_cl_enhance_reg, clip_vtx_reorder_ena) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK) | (clip_vtx_reorder_ena << PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT) +#define PA_CL_ENHANCE_SET_ECO_SPARE3(pa_cl_enhance_reg, eco_spare3) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE3_MASK) | (eco_spare3 << PA_CL_ENHANCE_ECO_SPARE3_SHIFT) +#define PA_CL_ENHANCE_SET_ECO_SPARE2(pa_cl_enhance_reg, eco_spare2) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE2_MASK) | (eco_spare2 << PA_CL_ENHANCE_ECO_SPARE2_SHIFT) +#define PA_CL_ENHANCE_SET_ECO_SPARE1(pa_cl_enhance_reg, eco_spare1) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE1_MASK) | (eco_spare1 << PA_CL_ENHANCE_ECO_SPARE1_SHIFT) +#define PA_CL_ENHANCE_SET_ECO_SPARE0(pa_cl_enhance_reg, eco_spare0) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE0_MASK) | (eco_spare0 << PA_CL_ENHANCE_ECO_SPARE0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_enhance_t { + unsigned int clip_vtx_reorder_ena : PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE; + unsigned int : 27; + unsigned int eco_spare3 : PA_CL_ENHANCE_ECO_SPARE3_SIZE; + unsigned int eco_spare2 : PA_CL_ENHANCE_ECO_SPARE2_SIZE; + unsigned int eco_spare1 : PA_CL_ENHANCE_ECO_SPARE1_SIZE; + unsigned int eco_spare0 : PA_CL_ENHANCE_ECO_SPARE0_SIZE; + } pa_cl_enhance_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_enhance_t { + unsigned int eco_spare0 : PA_CL_ENHANCE_ECO_SPARE0_SIZE; + unsigned int eco_spare1 : PA_CL_ENHANCE_ECO_SPARE1_SIZE; + unsigned int eco_spare2 : PA_CL_ENHANCE_ECO_SPARE2_SIZE; + unsigned int eco_spare3 : PA_CL_ENHANCE_ECO_SPARE3_SIZE; + unsigned int : 27; + unsigned int clip_vtx_reorder_ena : PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE; + } pa_cl_enhance_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_enhance_t f; +} pa_cl_enhance_u; + + +/* + * PA_SC_ENHANCE struct + */ + +#define PA_SC_ENHANCE_ECO_SPARE3_SIZE 1 +#define PA_SC_ENHANCE_ECO_SPARE2_SIZE 1 +#define PA_SC_ENHANCE_ECO_SPARE1_SIZE 1 +#define PA_SC_ENHANCE_ECO_SPARE0_SIZE 1 + +#define PA_SC_ENHANCE_ECO_SPARE3_SHIFT 28 +#define PA_SC_ENHANCE_ECO_SPARE2_SHIFT 29 +#define PA_SC_ENHANCE_ECO_SPARE1_SHIFT 30 +#define PA_SC_ENHANCE_ECO_SPARE0_SHIFT 31 + +#define PA_SC_ENHANCE_ECO_SPARE3_MASK 0x10000000 +#define PA_SC_ENHANCE_ECO_SPARE2_MASK 0x20000000 +#define PA_SC_ENHANCE_ECO_SPARE1_MASK 0x40000000 +#define PA_SC_ENHANCE_ECO_SPARE0_MASK 0x80000000 + +#define PA_SC_ENHANCE_MASK \ + (PA_SC_ENHANCE_ECO_SPARE3_MASK | \ + PA_SC_ENHANCE_ECO_SPARE2_MASK | \ + PA_SC_ENHANCE_ECO_SPARE1_MASK | \ + PA_SC_ENHANCE_ECO_SPARE0_MASK) + +#define PA_SC_ENHANCE(eco_spare3, eco_spare2, eco_spare1, eco_spare0) \ + ((eco_spare3 << PA_SC_ENHANCE_ECO_SPARE3_SHIFT) | \ + (eco_spare2 << PA_SC_ENHANCE_ECO_SPARE2_SHIFT) | \ + (eco_spare1 << PA_SC_ENHANCE_ECO_SPARE1_SHIFT) | \ + (eco_spare0 << PA_SC_ENHANCE_ECO_SPARE0_SHIFT)) + +#define PA_SC_ENHANCE_GET_ECO_SPARE3(pa_sc_enhance) \ + ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE3_MASK) >> PA_SC_ENHANCE_ECO_SPARE3_SHIFT) +#define PA_SC_ENHANCE_GET_ECO_SPARE2(pa_sc_enhance) \ + ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE2_MASK) >> PA_SC_ENHANCE_ECO_SPARE2_SHIFT) +#define PA_SC_ENHANCE_GET_ECO_SPARE1(pa_sc_enhance) \ + ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE1_MASK) >> PA_SC_ENHANCE_ECO_SPARE1_SHIFT) +#define PA_SC_ENHANCE_GET_ECO_SPARE0(pa_sc_enhance) \ + ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE0_MASK) >> PA_SC_ENHANCE_ECO_SPARE0_SHIFT) + +#define PA_SC_ENHANCE_SET_ECO_SPARE3(pa_sc_enhance_reg, eco_spare3) \ + pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE3_MASK) | (eco_spare3 << PA_SC_ENHANCE_ECO_SPARE3_SHIFT) +#define PA_SC_ENHANCE_SET_ECO_SPARE2(pa_sc_enhance_reg, eco_spare2) \ + pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE2_MASK) | (eco_spare2 << PA_SC_ENHANCE_ECO_SPARE2_SHIFT) +#define PA_SC_ENHANCE_SET_ECO_SPARE1(pa_sc_enhance_reg, eco_spare1) \ + pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE1_MASK) | (eco_spare1 << PA_SC_ENHANCE_ECO_SPARE1_SHIFT) +#define PA_SC_ENHANCE_SET_ECO_SPARE0(pa_sc_enhance_reg, eco_spare0) \ + pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE0_MASK) | (eco_spare0 << PA_SC_ENHANCE_ECO_SPARE0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_enhance_t { + unsigned int : 28; + unsigned int eco_spare3 : PA_SC_ENHANCE_ECO_SPARE3_SIZE; + unsigned int eco_spare2 : PA_SC_ENHANCE_ECO_SPARE2_SIZE; + unsigned int eco_spare1 : PA_SC_ENHANCE_ECO_SPARE1_SIZE; + unsigned int eco_spare0 : PA_SC_ENHANCE_ECO_SPARE0_SIZE; + } pa_sc_enhance_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_enhance_t { + unsigned int eco_spare0 : PA_SC_ENHANCE_ECO_SPARE0_SIZE; + unsigned int eco_spare1 : PA_SC_ENHANCE_ECO_SPARE1_SIZE; + unsigned int eco_spare2 : PA_SC_ENHANCE_ECO_SPARE2_SIZE; + unsigned int eco_spare3 : PA_SC_ENHANCE_ECO_SPARE3_SIZE; + unsigned int : 28; + } pa_sc_enhance_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_enhance_t f; +} pa_sc_enhance_u; + + +/* + * PA_SU_VTX_CNTL struct + */ + +#define PA_SU_VTX_CNTL_PIX_CENTER_SIZE 1 +#define PA_SU_VTX_CNTL_ROUND_MODE_SIZE 2 +#define PA_SU_VTX_CNTL_QUANT_MODE_SIZE 3 + +#define PA_SU_VTX_CNTL_PIX_CENTER_SHIFT 0 +#define PA_SU_VTX_CNTL_ROUND_MODE_SHIFT 1 +#define PA_SU_VTX_CNTL_QUANT_MODE_SHIFT 3 + +#define PA_SU_VTX_CNTL_PIX_CENTER_MASK 0x00000001 +#define PA_SU_VTX_CNTL_ROUND_MODE_MASK 0x00000006 +#define PA_SU_VTX_CNTL_QUANT_MODE_MASK 0x00000038 + +#define PA_SU_VTX_CNTL_MASK \ + (PA_SU_VTX_CNTL_PIX_CENTER_MASK | \ + PA_SU_VTX_CNTL_ROUND_MODE_MASK | \ + PA_SU_VTX_CNTL_QUANT_MODE_MASK) + +#define PA_SU_VTX_CNTL(pix_center, round_mode, quant_mode) \ + ((pix_center << PA_SU_VTX_CNTL_PIX_CENTER_SHIFT) | \ + (round_mode << PA_SU_VTX_CNTL_ROUND_MODE_SHIFT) | \ + (quant_mode << PA_SU_VTX_CNTL_QUANT_MODE_SHIFT)) + +#define PA_SU_VTX_CNTL_GET_PIX_CENTER(pa_su_vtx_cntl) \ + ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_PIX_CENTER_MASK) >> PA_SU_VTX_CNTL_PIX_CENTER_SHIFT) +#define PA_SU_VTX_CNTL_GET_ROUND_MODE(pa_su_vtx_cntl) \ + ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_ROUND_MODE_MASK) >> PA_SU_VTX_CNTL_ROUND_MODE_SHIFT) +#define PA_SU_VTX_CNTL_GET_QUANT_MODE(pa_su_vtx_cntl) \ + ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_QUANT_MODE_MASK) >> PA_SU_VTX_CNTL_QUANT_MODE_SHIFT) + +#define PA_SU_VTX_CNTL_SET_PIX_CENTER(pa_su_vtx_cntl_reg, pix_center) \ + pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_PIX_CENTER_MASK) | (pix_center << PA_SU_VTX_CNTL_PIX_CENTER_SHIFT) +#define PA_SU_VTX_CNTL_SET_ROUND_MODE(pa_su_vtx_cntl_reg, round_mode) \ + pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_ROUND_MODE_MASK) | (round_mode << PA_SU_VTX_CNTL_ROUND_MODE_SHIFT) +#define PA_SU_VTX_CNTL_SET_QUANT_MODE(pa_su_vtx_cntl_reg, quant_mode) \ + pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_QUANT_MODE_MASK) | (quant_mode << PA_SU_VTX_CNTL_QUANT_MODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_vtx_cntl_t { + unsigned int pix_center : PA_SU_VTX_CNTL_PIX_CENTER_SIZE; + unsigned int round_mode : PA_SU_VTX_CNTL_ROUND_MODE_SIZE; + unsigned int quant_mode : PA_SU_VTX_CNTL_QUANT_MODE_SIZE; + unsigned int : 26; + } pa_su_vtx_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_vtx_cntl_t { + unsigned int : 26; + unsigned int quant_mode : PA_SU_VTX_CNTL_QUANT_MODE_SIZE; + unsigned int round_mode : PA_SU_VTX_CNTL_ROUND_MODE_SIZE; + unsigned int pix_center : PA_SU_VTX_CNTL_PIX_CENTER_SIZE; + } pa_su_vtx_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_vtx_cntl_t f; +} pa_su_vtx_cntl_u; + + +/* + * PA_SU_POINT_SIZE struct + */ + +#define PA_SU_POINT_SIZE_HEIGHT_SIZE 16 +#define PA_SU_POINT_SIZE_WIDTH_SIZE 16 + +#define PA_SU_POINT_SIZE_HEIGHT_SHIFT 0 +#define PA_SU_POINT_SIZE_WIDTH_SHIFT 16 + +#define PA_SU_POINT_SIZE_HEIGHT_MASK 0x0000ffff +#define PA_SU_POINT_SIZE_WIDTH_MASK 0xffff0000 + +#define PA_SU_POINT_SIZE_MASK \ + (PA_SU_POINT_SIZE_HEIGHT_MASK | \ + PA_SU_POINT_SIZE_WIDTH_MASK) + +#define PA_SU_POINT_SIZE(height, width) \ + ((height << PA_SU_POINT_SIZE_HEIGHT_SHIFT) | \ + (width << PA_SU_POINT_SIZE_WIDTH_SHIFT)) + +#define PA_SU_POINT_SIZE_GET_HEIGHT(pa_su_point_size) \ + ((pa_su_point_size & PA_SU_POINT_SIZE_HEIGHT_MASK) >> PA_SU_POINT_SIZE_HEIGHT_SHIFT) +#define PA_SU_POINT_SIZE_GET_WIDTH(pa_su_point_size) \ + ((pa_su_point_size & PA_SU_POINT_SIZE_WIDTH_MASK) >> PA_SU_POINT_SIZE_WIDTH_SHIFT) + +#define PA_SU_POINT_SIZE_SET_HEIGHT(pa_su_point_size_reg, height) \ + pa_su_point_size_reg = (pa_su_point_size_reg & ~PA_SU_POINT_SIZE_HEIGHT_MASK) | (height << PA_SU_POINT_SIZE_HEIGHT_SHIFT) +#define PA_SU_POINT_SIZE_SET_WIDTH(pa_su_point_size_reg, width) \ + pa_su_point_size_reg = (pa_su_point_size_reg & ~PA_SU_POINT_SIZE_WIDTH_MASK) | (width << PA_SU_POINT_SIZE_WIDTH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_point_size_t { + unsigned int height : PA_SU_POINT_SIZE_HEIGHT_SIZE; + unsigned int width : PA_SU_POINT_SIZE_WIDTH_SIZE; + } pa_su_point_size_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_point_size_t { + unsigned int width : PA_SU_POINT_SIZE_WIDTH_SIZE; + unsigned int height : PA_SU_POINT_SIZE_HEIGHT_SIZE; + } pa_su_point_size_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_point_size_t f; +} pa_su_point_size_u; + + +/* + * PA_SU_POINT_MINMAX struct + */ + +#define PA_SU_POINT_MINMAX_MIN_SIZE_SIZE 16 +#define PA_SU_POINT_MINMAX_MAX_SIZE_SIZE 16 + +#define PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT 0 +#define PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT 16 + +#define PA_SU_POINT_MINMAX_MIN_SIZE_MASK 0x0000ffff +#define PA_SU_POINT_MINMAX_MAX_SIZE_MASK 0xffff0000 + +#define PA_SU_POINT_MINMAX_MASK \ + (PA_SU_POINT_MINMAX_MIN_SIZE_MASK | \ + PA_SU_POINT_MINMAX_MAX_SIZE_MASK) + +#define PA_SU_POINT_MINMAX(min_size, max_size) \ + ((min_size << PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT) | \ + (max_size << PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT)) + +#define PA_SU_POINT_MINMAX_GET_MIN_SIZE(pa_su_point_minmax) \ + ((pa_su_point_minmax & PA_SU_POINT_MINMAX_MIN_SIZE_MASK) >> PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT) +#define PA_SU_POINT_MINMAX_GET_MAX_SIZE(pa_su_point_minmax) \ + ((pa_su_point_minmax & PA_SU_POINT_MINMAX_MAX_SIZE_MASK) >> PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT) + +#define PA_SU_POINT_MINMAX_SET_MIN_SIZE(pa_su_point_minmax_reg, min_size) \ + pa_su_point_minmax_reg = (pa_su_point_minmax_reg & ~PA_SU_POINT_MINMAX_MIN_SIZE_MASK) | (min_size << PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT) +#define PA_SU_POINT_MINMAX_SET_MAX_SIZE(pa_su_point_minmax_reg, max_size) \ + pa_su_point_minmax_reg = (pa_su_point_minmax_reg & ~PA_SU_POINT_MINMAX_MAX_SIZE_MASK) | (max_size << PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_point_minmax_t { + unsigned int min_size : PA_SU_POINT_MINMAX_MIN_SIZE_SIZE; + unsigned int max_size : PA_SU_POINT_MINMAX_MAX_SIZE_SIZE; + } pa_su_point_minmax_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_point_minmax_t { + unsigned int max_size : PA_SU_POINT_MINMAX_MAX_SIZE_SIZE; + unsigned int min_size : PA_SU_POINT_MINMAX_MIN_SIZE_SIZE; + } pa_su_point_minmax_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_point_minmax_t f; +} pa_su_point_minmax_u; + + +/* + * PA_SU_LINE_CNTL struct + */ + +#define PA_SU_LINE_CNTL_WIDTH_SIZE 16 + +#define PA_SU_LINE_CNTL_WIDTH_SHIFT 0 + +#define PA_SU_LINE_CNTL_WIDTH_MASK 0x0000ffff + +#define PA_SU_LINE_CNTL_MASK \ + (PA_SU_LINE_CNTL_WIDTH_MASK) + +#define PA_SU_LINE_CNTL(width) \ + ((width << PA_SU_LINE_CNTL_WIDTH_SHIFT)) + +#define PA_SU_LINE_CNTL_GET_WIDTH(pa_su_line_cntl) \ + ((pa_su_line_cntl & PA_SU_LINE_CNTL_WIDTH_MASK) >> PA_SU_LINE_CNTL_WIDTH_SHIFT) + +#define PA_SU_LINE_CNTL_SET_WIDTH(pa_su_line_cntl_reg, width) \ + pa_su_line_cntl_reg = (pa_su_line_cntl_reg & ~PA_SU_LINE_CNTL_WIDTH_MASK) | (width << PA_SU_LINE_CNTL_WIDTH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_line_cntl_t { + unsigned int width : PA_SU_LINE_CNTL_WIDTH_SIZE; + unsigned int : 16; + } pa_su_line_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_line_cntl_t { + unsigned int : 16; + unsigned int width : PA_SU_LINE_CNTL_WIDTH_SIZE; + } pa_su_line_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_line_cntl_t f; +} pa_su_line_cntl_u; + + +/* + * PA_SU_SC_MODE_CNTL struct + */ + +#define PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE 1 +#define PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE 1 +#define PA_SU_SC_MODE_CNTL_FACE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE 2 +#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE 3 +#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE 3 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE 1 +#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE 1 +#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE 1 +#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE 1 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE 1 + +#define PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT 0 +#define PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT 1 +#define PA_SU_SC_MODE_CNTL_FACE_SHIFT 2 +#define PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT 3 +#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT 5 +#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT 8 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT 11 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT 12 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT 13 +#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT 15 +#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT 16 +#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT 18 +#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT 19 +#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT 20 +#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT 21 +#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT 23 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT 25 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT 26 + +#define PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK 0x00000001 +#define PA_SU_SC_MODE_CNTL_CULL_BACK_MASK 0x00000002 +#define PA_SU_SC_MODE_CNTL_FACE_MASK 0x00000004 +#define PA_SU_SC_MODE_CNTL_POLY_MODE_MASK 0x00000018 +#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK 0x000000e0 +#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK 0x00000700 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK 0x00001000 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK 0x00002000 +#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK 0x00008000 +#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000 +#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK 0x00040000 +#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK 0x00080000 +#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK 0x00100000 +#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK 0x00200000 +#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK 0x00800000 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK 0x02000000 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK 0x04000000 + +#define PA_SU_SC_MODE_CNTL_MASK \ + (PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK | \ + PA_SU_SC_MODE_CNTL_CULL_BACK_MASK | \ + PA_SU_SC_MODE_CNTL_FACE_MASK | \ + PA_SU_SC_MODE_CNTL_POLY_MODE_MASK | \ + PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK | \ + PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK | \ + PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK | \ + PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK | \ + PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK | \ + PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK | \ + PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK) + +#define PA_SU_SC_MODE_CNTL(cull_front, cull_back, face, poly_mode, polymode_front_ptype, polymode_back_ptype, poly_offset_front_enable, poly_offset_back_enable, poly_offset_para_enable, msaa_enable, vtx_window_offset_enable, line_stipple_enable, provoking_vtx_last, persp_corr_dis, multi_prim_ib_ena, quad_order_enable, wait_rb_idle_all_tri, wait_rb_idle_first_tri_new_state) \ + ((cull_front << PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT) | \ + (cull_back << PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT) | \ + (face << PA_SU_SC_MODE_CNTL_FACE_SHIFT) | \ + (poly_mode << PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT) | \ + (polymode_front_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT) | \ + (polymode_back_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT) | \ + (poly_offset_front_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT) | \ + (poly_offset_back_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT) | \ + (poly_offset_para_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT) | \ + (msaa_enable << PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT) | \ + (vtx_window_offset_enable << PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT) | \ + (line_stipple_enable << PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT) | \ + (provoking_vtx_last << PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT) | \ + (persp_corr_dis << PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT) | \ + (multi_prim_ib_ena << PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT) | \ + (quad_order_enable << PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT) | \ + (wait_rb_idle_all_tri << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT) | \ + (wait_rb_idle_first_tri_new_state << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT)) + +#define PA_SU_SC_MODE_CNTL_GET_CULL_FRONT(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK) >> PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_CULL_BACK(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_CULL_BACK_MASK) >> PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_FACE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_FACE_MASK) >> PA_SU_SC_MODE_CNTL_FACE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLY_MODE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_MODE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLYMODE_FRONT_PTYPE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK) >> PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLYMODE_BACK_PTYPE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK) >> PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_FRONT_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_BACK_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_PARA_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_MSAA_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_VTX_WINDOW_OFFSET_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_LINE_STIPPLE_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_PROVOKING_VTX_LAST(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK) >> PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_PERSP_CORR_DIS(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK) >> PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_MULTI_PRIM_IB_ENA(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK) >> PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_QUAD_ORDER_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_WAIT_RB_IDLE_ALL_TRI(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK) >> PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK) >> PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT) + +#define PA_SU_SC_MODE_CNTL_SET_CULL_FRONT(pa_su_sc_mode_cntl_reg, cull_front) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK) | (cull_front << PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_CULL_BACK(pa_su_sc_mode_cntl_reg, cull_back) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_CULL_BACK_MASK) | (cull_back << PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_FACE(pa_su_sc_mode_cntl_reg, face) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_FACE_MASK) | (face << PA_SU_SC_MODE_CNTL_FACE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLY_MODE(pa_su_sc_mode_cntl_reg, poly_mode) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_MODE_MASK) | (poly_mode << PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLYMODE_FRONT_PTYPE(pa_su_sc_mode_cntl_reg, polymode_front_ptype) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK) | (polymode_front_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLYMODE_BACK_PTYPE(pa_su_sc_mode_cntl_reg, polymode_back_ptype) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK) | (polymode_back_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_FRONT_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_front_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK) | (poly_offset_front_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_BACK_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_back_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK) | (poly_offset_back_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_PARA_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_para_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK) | (poly_offset_para_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_MSAA_ENABLE(pa_su_sc_mode_cntl_reg, msaa_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK) | (msaa_enable << PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_VTX_WINDOW_OFFSET_ENABLE(pa_su_sc_mode_cntl_reg, vtx_window_offset_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK) | (vtx_window_offset_enable << PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_LINE_STIPPLE_ENABLE(pa_su_sc_mode_cntl_reg, line_stipple_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK) | (line_stipple_enable << PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_PROVOKING_VTX_LAST(pa_su_sc_mode_cntl_reg, provoking_vtx_last) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK) | (provoking_vtx_last << PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_PERSP_CORR_DIS(pa_su_sc_mode_cntl_reg, persp_corr_dis) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK) | (persp_corr_dis << PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_MULTI_PRIM_IB_ENA(pa_su_sc_mode_cntl_reg, multi_prim_ib_ena) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK) | (multi_prim_ib_ena << PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_QUAD_ORDER_ENABLE(pa_su_sc_mode_cntl_reg, quad_order_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK) | (quad_order_enable << PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_WAIT_RB_IDLE_ALL_TRI(pa_su_sc_mode_cntl_reg, wait_rb_idle_all_tri) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK) | (wait_rb_idle_all_tri << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE(pa_su_sc_mode_cntl_reg, wait_rb_idle_first_tri_new_state) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK) | (wait_rb_idle_first_tri_new_state << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_sc_mode_cntl_t { + unsigned int cull_front : PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE; + unsigned int cull_back : PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE; + unsigned int face : PA_SU_SC_MODE_CNTL_FACE_SIZE; + unsigned int poly_mode : PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE; + unsigned int polymode_front_ptype : PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE; + unsigned int polymode_back_ptype : PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE; + unsigned int poly_offset_front_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE; + unsigned int poly_offset_back_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE; + unsigned int poly_offset_para_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE; + unsigned int : 1; + unsigned int msaa_enable : PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE; + unsigned int vtx_window_offset_enable : PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE; + unsigned int : 1; + unsigned int line_stipple_enable : PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE; + unsigned int provoking_vtx_last : PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE; + unsigned int persp_corr_dis : PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE; + unsigned int multi_prim_ib_ena : PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE; + unsigned int : 1; + unsigned int quad_order_enable : PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE; + unsigned int : 1; + unsigned int wait_rb_idle_all_tri : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE; + unsigned int wait_rb_idle_first_tri_new_state : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE; + unsigned int : 5; + } pa_su_sc_mode_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_sc_mode_cntl_t { + unsigned int : 5; + unsigned int wait_rb_idle_first_tri_new_state : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE; + unsigned int wait_rb_idle_all_tri : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE; + unsigned int : 1; + unsigned int quad_order_enable : PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE; + unsigned int : 1; + unsigned int multi_prim_ib_ena : PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE; + unsigned int persp_corr_dis : PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE; + unsigned int provoking_vtx_last : PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE; + unsigned int line_stipple_enable : PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE; + unsigned int : 1; + unsigned int vtx_window_offset_enable : PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE; + unsigned int msaa_enable : PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE; + unsigned int : 1; + unsigned int poly_offset_para_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE; + unsigned int poly_offset_back_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE; + unsigned int poly_offset_front_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE; + unsigned int polymode_back_ptype : PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE; + unsigned int polymode_front_ptype : PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE; + unsigned int poly_mode : PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE; + unsigned int face : PA_SU_SC_MODE_CNTL_FACE_SIZE; + unsigned int cull_back : PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE; + unsigned int cull_front : PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE; + } pa_su_sc_mode_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_sc_mode_cntl_t f; +} pa_su_sc_mode_cntl_u; + + +/* + * PA_SU_POLY_OFFSET_FRONT_SCALE struct + */ + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE 32 + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT 0 + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK 0xffffffff + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_MASK \ + (PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) + +#define PA_SU_POLY_OFFSET_FRONT_SCALE(scale) \ + ((scale << PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT)) + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_GET_SCALE(pa_su_poly_offset_front_scale) \ + ((pa_su_poly_offset_front_scale & PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) >> PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT) + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_SET_SCALE(pa_su_poly_offset_front_scale_reg, scale) \ + pa_su_poly_offset_front_scale_reg = (pa_su_poly_offset_front_scale_reg & ~PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) | (scale << PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_front_scale_t { + unsigned int scale : PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE; + } pa_su_poly_offset_front_scale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_front_scale_t { + unsigned int scale : PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE; + } pa_su_poly_offset_front_scale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_poly_offset_front_scale_t f; +} pa_su_poly_offset_front_scale_u; + + +/* + * PA_SU_POLY_OFFSET_FRONT_OFFSET struct + */ + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE 32 + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT 0 + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK 0xffffffff + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_MASK \ + (PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET(offset) \ + ((offset << PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT)) + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_GET_OFFSET(pa_su_poly_offset_front_offset) \ + ((pa_su_poly_offset_front_offset & PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) >> PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT) + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_SET_OFFSET(pa_su_poly_offset_front_offset_reg, offset) \ + pa_su_poly_offset_front_offset_reg = (pa_su_poly_offset_front_offset_reg & ~PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) | (offset << PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_front_offset_t { + unsigned int offset : PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE; + } pa_su_poly_offset_front_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_front_offset_t { + unsigned int offset : PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE; + } pa_su_poly_offset_front_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_poly_offset_front_offset_t f; +} pa_su_poly_offset_front_offset_u; + + +/* + * PA_SU_POLY_OFFSET_BACK_SCALE struct + */ + +#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE 32 + +#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT 0 + +#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK 0xffffffff + +#define PA_SU_POLY_OFFSET_BACK_SCALE_MASK \ + (PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) + +#define PA_SU_POLY_OFFSET_BACK_SCALE(scale) \ + ((scale << PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT)) + +#define PA_SU_POLY_OFFSET_BACK_SCALE_GET_SCALE(pa_su_poly_offset_back_scale) \ + ((pa_su_poly_offset_back_scale & PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) >> PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT) + +#define PA_SU_POLY_OFFSET_BACK_SCALE_SET_SCALE(pa_su_poly_offset_back_scale_reg, scale) \ + pa_su_poly_offset_back_scale_reg = (pa_su_poly_offset_back_scale_reg & ~PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) | (scale << PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_back_scale_t { + unsigned int scale : PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE; + } pa_su_poly_offset_back_scale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_back_scale_t { + unsigned int scale : PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE; + } pa_su_poly_offset_back_scale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_poly_offset_back_scale_t f; +} pa_su_poly_offset_back_scale_u; + + +/* + * PA_SU_POLY_OFFSET_BACK_OFFSET struct + */ + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE 32 + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT 0 + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK 0xffffffff + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_MASK \ + (PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) + +#define PA_SU_POLY_OFFSET_BACK_OFFSET(offset) \ + ((offset << PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT)) + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_GET_OFFSET(pa_su_poly_offset_back_offset) \ + ((pa_su_poly_offset_back_offset & PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) >> PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT) + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_SET_OFFSET(pa_su_poly_offset_back_offset_reg, offset) \ + pa_su_poly_offset_back_offset_reg = (pa_su_poly_offset_back_offset_reg & ~PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) | (offset << PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_back_offset_t { + unsigned int offset : PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE; + } pa_su_poly_offset_back_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_back_offset_t { + unsigned int offset : PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE; + } pa_su_poly_offset_back_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_poly_offset_back_offset_t f; +} pa_su_poly_offset_back_offset_u; + + +/* + * PA_SU_PERFCOUNTER0_SELECT struct + */ + +#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SU_PERFCOUNTER0_SELECT_MASK \ + (PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define PA_SU_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define PA_SU_PERFCOUNTER0_SELECT_GET_PERF_SEL(pa_su_perfcounter0_select) \ + ((pa_su_perfcounter0_select & PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define PA_SU_PERFCOUNTER0_SELECT_SET_PERF_SEL(pa_su_perfcounter0_select_reg, perf_sel) \ + pa_su_perfcounter0_select_reg = (pa_su_perfcounter0_select_reg & ~PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_select_t { + unsigned int perf_sel : PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_su_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } pa_su_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter0_select_t f; +} pa_su_perfcounter0_select_u; + + +/* + * PA_SU_PERFCOUNTER1_SELECT struct + */ + +#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8 + +#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SU_PERFCOUNTER1_SELECT_MASK \ + (PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) + +#define PA_SU_PERFCOUNTER1_SELECT(perf_sel) \ + ((perf_sel << PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)) + +#define PA_SU_PERFCOUNTER1_SELECT_GET_PERF_SEL(pa_su_perfcounter1_select) \ + ((pa_su_perfcounter1_select & PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#define PA_SU_PERFCOUNTER1_SELECT_SET_PERF_SEL(pa_su_perfcounter1_select_reg, perf_sel) \ + pa_su_perfcounter1_select_reg = (pa_su_perfcounter1_select_reg & ~PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_select_t { + unsigned int perf_sel : PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_su_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + } pa_su_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter1_select_t f; +} pa_su_perfcounter1_select_u; + + +/* + * PA_SU_PERFCOUNTER2_SELECT struct + */ + +#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8 + +#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SU_PERFCOUNTER2_SELECT_MASK \ + (PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) + +#define PA_SU_PERFCOUNTER2_SELECT(perf_sel) \ + ((perf_sel << PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)) + +#define PA_SU_PERFCOUNTER2_SELECT_GET_PERF_SEL(pa_su_perfcounter2_select) \ + ((pa_su_perfcounter2_select & PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#define PA_SU_PERFCOUNTER2_SELECT_SET_PERF_SEL(pa_su_perfcounter2_select_reg, perf_sel) \ + pa_su_perfcounter2_select_reg = (pa_su_perfcounter2_select_reg & ~PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_select_t { + unsigned int perf_sel : PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_su_perfcounter2_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + } pa_su_perfcounter2_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter2_select_t f; +} pa_su_perfcounter2_select_u; + + +/* + * PA_SU_PERFCOUNTER3_SELECT struct + */ + +#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8 + +#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SU_PERFCOUNTER3_SELECT_MASK \ + (PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) + +#define PA_SU_PERFCOUNTER3_SELECT(perf_sel) \ + ((perf_sel << PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)) + +#define PA_SU_PERFCOUNTER3_SELECT_GET_PERF_SEL(pa_su_perfcounter3_select) \ + ((pa_su_perfcounter3_select & PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#define PA_SU_PERFCOUNTER3_SELECT_SET_PERF_SEL(pa_su_perfcounter3_select_reg, perf_sel) \ + pa_su_perfcounter3_select_reg = (pa_su_perfcounter3_select_reg & ~PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_select_t { + unsigned int perf_sel : PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_su_perfcounter3_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + } pa_su_perfcounter3_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter3_select_t f; +} pa_su_perfcounter3_select_u; + + +/* + * PA_SU_PERFCOUNTER0_LOW struct + */ + +#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SU_PERFCOUNTER0_LOW_MASK \ + (PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER0_LOW_GET_PERF_COUNT(pa_su_perfcounter0_low) \ + ((pa_su_perfcounter0_low & PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER0_LOW_SET_PERF_COUNT(pa_su_perfcounter0_low_reg, perf_count) \ + pa_su_perfcounter0_low_reg = (pa_su_perfcounter0_low_reg & ~PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter0_low_t f; +} pa_su_perfcounter0_low_u; + + +/* + * PA_SU_PERFCOUNTER0_HI struct + */ + +#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SU_PERFCOUNTER0_HI_MASK \ + (PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER0_HI_GET_PERF_COUNT(pa_su_perfcounter0_hi) \ + ((pa_su_perfcounter0_hi & PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER0_HI_SET_PERF_COUNT(pa_su_perfcounter0_hi_reg, perf_count) \ + pa_su_perfcounter0_hi_reg = (pa_su_perfcounter0_hi_reg & ~PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_hi_t { + unsigned int perf_count : PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_su_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } pa_su_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter0_hi_t f; +} pa_su_perfcounter0_hi_u; + + +/* + * PA_SU_PERFCOUNTER1_LOW struct + */ + +#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32 + +#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SU_PERFCOUNTER1_LOW_MASK \ + (PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER1_LOW(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER1_LOW_GET_PERF_COUNT(pa_su_perfcounter1_low) \ + ((pa_su_perfcounter1_low & PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER1_LOW_SET_PERF_COUNT(pa_su_perfcounter1_low_reg, perf_count) \ + pa_su_perfcounter1_low_reg = (pa_su_perfcounter1_low_reg & ~PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter1_low_t f; +} pa_su_perfcounter1_low_u; + + +/* + * PA_SU_PERFCOUNTER1_HI struct + */ + +#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16 + +#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SU_PERFCOUNTER1_HI_MASK \ + (PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER1_HI(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER1_HI_GET_PERF_COUNT(pa_su_perfcounter1_hi) \ + ((pa_su_perfcounter1_hi & PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER1_HI_SET_PERF_COUNT(pa_su_perfcounter1_hi_reg, perf_count) \ + pa_su_perfcounter1_hi_reg = (pa_su_perfcounter1_hi_reg & ~PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_hi_t { + unsigned int perf_count : PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_su_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + } pa_su_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter1_hi_t f; +} pa_su_perfcounter1_hi_u; + + +/* + * PA_SU_PERFCOUNTER2_LOW struct + */ + +#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32 + +#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SU_PERFCOUNTER2_LOW_MASK \ + (PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER2_LOW(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER2_LOW_GET_PERF_COUNT(pa_su_perfcounter2_low) \ + ((pa_su_perfcounter2_low & PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER2_LOW_SET_PERF_COUNT(pa_su_perfcounter2_low_reg, perf_count) \ + pa_su_perfcounter2_low_reg = (pa_su_perfcounter2_low_reg & ~PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter2_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter2_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter2_low_t f; +} pa_su_perfcounter2_low_u; + + +/* + * PA_SU_PERFCOUNTER2_HI struct + */ + +#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16 + +#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SU_PERFCOUNTER2_HI_MASK \ + (PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER2_HI(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER2_HI_GET_PERF_COUNT(pa_su_perfcounter2_hi) \ + ((pa_su_perfcounter2_hi & PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER2_HI_SET_PERF_COUNT(pa_su_perfcounter2_hi_reg, perf_count) \ + pa_su_perfcounter2_hi_reg = (pa_su_perfcounter2_hi_reg & ~PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_hi_t { + unsigned int perf_count : PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_su_perfcounter2_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + } pa_su_perfcounter2_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter2_hi_t f; +} pa_su_perfcounter2_hi_u; + + +/* + * PA_SU_PERFCOUNTER3_LOW struct + */ + +#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32 + +#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SU_PERFCOUNTER3_LOW_MASK \ + (PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER3_LOW(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER3_LOW_GET_PERF_COUNT(pa_su_perfcounter3_low) \ + ((pa_su_perfcounter3_low & PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER3_LOW_SET_PERF_COUNT(pa_su_perfcounter3_low_reg, perf_count) \ + pa_su_perfcounter3_low_reg = (pa_su_perfcounter3_low_reg & ~PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter3_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter3_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter3_low_t f; +} pa_su_perfcounter3_low_u; + + +/* + * PA_SU_PERFCOUNTER3_HI struct + */ + +#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16 + +#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SU_PERFCOUNTER3_HI_MASK \ + (PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER3_HI(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER3_HI_GET_PERF_COUNT(pa_su_perfcounter3_hi) \ + ((pa_su_perfcounter3_hi & PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER3_HI_SET_PERF_COUNT(pa_su_perfcounter3_hi_reg, perf_count) \ + pa_su_perfcounter3_hi_reg = (pa_su_perfcounter3_hi_reg & ~PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_hi_t { + unsigned int perf_count : PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_su_perfcounter3_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + } pa_su_perfcounter3_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter3_hi_t f; +} pa_su_perfcounter3_hi_u; + + +/* + * PA_SC_WINDOW_OFFSET struct + */ + +#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE 15 +#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE 15 + +#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT 0 +#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT 16 + +#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK 0x00007fff +#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK 0x7fff0000 + +#define PA_SC_WINDOW_OFFSET_MASK \ + (PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK | \ + PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) + +#define PA_SC_WINDOW_OFFSET(window_x_offset, window_y_offset) \ + ((window_x_offset << PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT) | \ + (window_y_offset << PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT)) + +#define PA_SC_WINDOW_OFFSET_GET_WINDOW_X_OFFSET(pa_sc_window_offset) \ + ((pa_sc_window_offset & PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK) >> PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT) +#define PA_SC_WINDOW_OFFSET_GET_WINDOW_Y_OFFSET(pa_sc_window_offset) \ + ((pa_sc_window_offset & PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) >> PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT) + +#define PA_SC_WINDOW_OFFSET_SET_WINDOW_X_OFFSET(pa_sc_window_offset_reg, window_x_offset) \ + pa_sc_window_offset_reg = (pa_sc_window_offset_reg & ~PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK) | (window_x_offset << PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT) +#define PA_SC_WINDOW_OFFSET_SET_WINDOW_Y_OFFSET(pa_sc_window_offset_reg, window_y_offset) \ + pa_sc_window_offset_reg = (pa_sc_window_offset_reg & ~PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) | (window_y_offset << PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_window_offset_t { + unsigned int window_x_offset : PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE; + unsigned int : 1; + unsigned int window_y_offset : PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE; + unsigned int : 1; + } pa_sc_window_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_window_offset_t { + unsigned int : 1; + unsigned int window_y_offset : PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE; + unsigned int : 1; + unsigned int window_x_offset : PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE; + } pa_sc_window_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_window_offset_t f; +} pa_sc_window_offset_u; + + +/* + * PA_SC_AA_CONFIG struct + */ + +#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE 3 +#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE 4 + +#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT 0 +#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT 13 + +#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK 0x00000007 +#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK 0x0001e000 + +#define PA_SC_AA_CONFIG_MASK \ + (PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK | \ + PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) + +#define PA_SC_AA_CONFIG(msaa_num_samples, max_sample_dist) \ + ((msaa_num_samples << PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT) | \ + (max_sample_dist << PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT)) + +#define PA_SC_AA_CONFIG_GET_MSAA_NUM_SAMPLES(pa_sc_aa_config) \ + ((pa_sc_aa_config & PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK) >> PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT) +#define PA_SC_AA_CONFIG_GET_MAX_SAMPLE_DIST(pa_sc_aa_config) \ + ((pa_sc_aa_config & PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) >> PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT) + +#define PA_SC_AA_CONFIG_SET_MSAA_NUM_SAMPLES(pa_sc_aa_config_reg, msaa_num_samples) \ + pa_sc_aa_config_reg = (pa_sc_aa_config_reg & ~PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK) | (msaa_num_samples << PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT) +#define PA_SC_AA_CONFIG_SET_MAX_SAMPLE_DIST(pa_sc_aa_config_reg, max_sample_dist) \ + pa_sc_aa_config_reg = (pa_sc_aa_config_reg & ~PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) | (max_sample_dist << PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_aa_config_t { + unsigned int msaa_num_samples : PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE; + unsigned int : 10; + unsigned int max_sample_dist : PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE; + unsigned int : 15; + } pa_sc_aa_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_aa_config_t { + unsigned int : 15; + unsigned int max_sample_dist : PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE; + unsigned int : 10; + unsigned int msaa_num_samples : PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE; + } pa_sc_aa_config_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_aa_config_t f; +} pa_sc_aa_config_u; + + +/* + * PA_SC_AA_MASK struct + */ + +#define PA_SC_AA_MASK_AA_MASK_SIZE 16 + +#define PA_SC_AA_MASK_AA_MASK_SHIFT 0 + +#define PA_SC_AA_MASK_AA_MASK_MASK 0x0000ffff + +#define PA_SC_AA_MASK_MASK \ + (PA_SC_AA_MASK_AA_MASK_MASK) + +#define PA_SC_AA_MASK(aa_mask) \ + ((aa_mask << PA_SC_AA_MASK_AA_MASK_SHIFT)) + +#define PA_SC_AA_MASK_GET_AA_MASK(pa_sc_aa_mask) \ + ((pa_sc_aa_mask & PA_SC_AA_MASK_AA_MASK_MASK) >> PA_SC_AA_MASK_AA_MASK_SHIFT) + +#define PA_SC_AA_MASK_SET_AA_MASK(pa_sc_aa_mask_reg, aa_mask) \ + pa_sc_aa_mask_reg = (pa_sc_aa_mask_reg & ~PA_SC_AA_MASK_AA_MASK_MASK) | (aa_mask << PA_SC_AA_MASK_AA_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_aa_mask_t { + unsigned int aa_mask : PA_SC_AA_MASK_AA_MASK_SIZE; + unsigned int : 16; + } pa_sc_aa_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_aa_mask_t { + unsigned int : 16; + unsigned int aa_mask : PA_SC_AA_MASK_AA_MASK_SIZE; + } pa_sc_aa_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_aa_mask_t f; +} pa_sc_aa_mask_u; + + +/* + * PA_SC_LINE_STIPPLE struct + */ + +#define PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE 16 +#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE 8 +#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE 1 +#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE 2 + +#define PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT 0 +#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT 16 +#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT 28 +#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT 29 + +#define PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK 0x0000ffff +#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK 0x00ff0000 +#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK 0x10000000 +#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK 0x60000000 + +#define PA_SC_LINE_STIPPLE_MASK \ + (PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK | \ + PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK | \ + PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK | \ + PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) + +#define PA_SC_LINE_STIPPLE(line_pattern, repeat_count, pattern_bit_order, auto_reset_cntl) \ + ((line_pattern << PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT) | \ + (repeat_count << PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT) | \ + (pattern_bit_order << PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT) | \ + (auto_reset_cntl << PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT)) + +#define PA_SC_LINE_STIPPLE_GET_LINE_PATTERN(pa_sc_line_stipple) \ + ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK) >> PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT) +#define PA_SC_LINE_STIPPLE_GET_REPEAT_COUNT(pa_sc_line_stipple) \ + ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK) >> PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT) +#define PA_SC_LINE_STIPPLE_GET_PATTERN_BIT_ORDER(pa_sc_line_stipple) \ + ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK) >> PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT) +#define PA_SC_LINE_STIPPLE_GET_AUTO_RESET_CNTL(pa_sc_line_stipple) \ + ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) >> PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT) + +#define PA_SC_LINE_STIPPLE_SET_LINE_PATTERN(pa_sc_line_stipple_reg, line_pattern) \ + pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK) | (line_pattern << PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT) +#define PA_SC_LINE_STIPPLE_SET_REPEAT_COUNT(pa_sc_line_stipple_reg, repeat_count) \ + pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK) | (repeat_count << PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT) +#define PA_SC_LINE_STIPPLE_SET_PATTERN_BIT_ORDER(pa_sc_line_stipple_reg, pattern_bit_order) \ + pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK) | (pattern_bit_order << PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT) +#define PA_SC_LINE_STIPPLE_SET_AUTO_RESET_CNTL(pa_sc_line_stipple_reg, auto_reset_cntl) \ + pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) | (auto_reset_cntl << PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_line_stipple_t { + unsigned int line_pattern : PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE; + unsigned int repeat_count : PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE; + unsigned int : 4; + unsigned int pattern_bit_order : PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE; + unsigned int auto_reset_cntl : PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE; + unsigned int : 1; + } pa_sc_line_stipple_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_line_stipple_t { + unsigned int : 1; + unsigned int auto_reset_cntl : PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE; + unsigned int pattern_bit_order : PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE; + unsigned int : 4; + unsigned int repeat_count : PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE; + unsigned int line_pattern : PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE; + } pa_sc_line_stipple_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_line_stipple_t f; +} pa_sc_line_stipple_u; + + +/* + * PA_SC_LINE_CNTL struct + */ + +#define PA_SC_LINE_CNTL_BRES_CNTL_SIZE 8 +#define PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE 1 +#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE 1 +#define PA_SC_LINE_CNTL_LAST_PIXEL_SIZE 1 + +#define PA_SC_LINE_CNTL_BRES_CNTL_SHIFT 0 +#define PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT 8 +#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT 9 +#define PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT 10 + +#define PA_SC_LINE_CNTL_BRES_CNTL_MASK 0x000000ff +#define PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK 0x00000100 +#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK 0x00000200 +#define PA_SC_LINE_CNTL_LAST_PIXEL_MASK 0x00000400 + +#define PA_SC_LINE_CNTL_MASK \ + (PA_SC_LINE_CNTL_BRES_CNTL_MASK | \ + PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK | \ + PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK | \ + PA_SC_LINE_CNTL_LAST_PIXEL_MASK) + +#define PA_SC_LINE_CNTL(bres_cntl, use_bres_cntl, expand_line_width, last_pixel) \ + ((bres_cntl << PA_SC_LINE_CNTL_BRES_CNTL_SHIFT) | \ + (use_bres_cntl << PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT) | \ + (expand_line_width << PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT) | \ + (last_pixel << PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT)) + +#define PA_SC_LINE_CNTL_GET_BRES_CNTL(pa_sc_line_cntl) \ + ((pa_sc_line_cntl & PA_SC_LINE_CNTL_BRES_CNTL_MASK) >> PA_SC_LINE_CNTL_BRES_CNTL_SHIFT) +#define PA_SC_LINE_CNTL_GET_USE_BRES_CNTL(pa_sc_line_cntl) \ + ((pa_sc_line_cntl & PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK) >> PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT) +#define PA_SC_LINE_CNTL_GET_EXPAND_LINE_WIDTH(pa_sc_line_cntl) \ + ((pa_sc_line_cntl & PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK) >> PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT) +#define PA_SC_LINE_CNTL_GET_LAST_PIXEL(pa_sc_line_cntl) \ + ((pa_sc_line_cntl & PA_SC_LINE_CNTL_LAST_PIXEL_MASK) >> PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT) + +#define PA_SC_LINE_CNTL_SET_BRES_CNTL(pa_sc_line_cntl_reg, bres_cntl) \ + pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_BRES_CNTL_MASK) | (bres_cntl << PA_SC_LINE_CNTL_BRES_CNTL_SHIFT) +#define PA_SC_LINE_CNTL_SET_USE_BRES_CNTL(pa_sc_line_cntl_reg, use_bres_cntl) \ + pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK) | (use_bres_cntl << PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT) +#define PA_SC_LINE_CNTL_SET_EXPAND_LINE_WIDTH(pa_sc_line_cntl_reg, expand_line_width) \ + pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK) | (expand_line_width << PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT) +#define PA_SC_LINE_CNTL_SET_LAST_PIXEL(pa_sc_line_cntl_reg, last_pixel) \ + pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_LAST_PIXEL_MASK) | (last_pixel << PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_line_cntl_t { + unsigned int bres_cntl : PA_SC_LINE_CNTL_BRES_CNTL_SIZE; + unsigned int use_bres_cntl : PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE; + unsigned int expand_line_width : PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE; + unsigned int last_pixel : PA_SC_LINE_CNTL_LAST_PIXEL_SIZE; + unsigned int : 21; + } pa_sc_line_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_line_cntl_t { + unsigned int : 21; + unsigned int last_pixel : PA_SC_LINE_CNTL_LAST_PIXEL_SIZE; + unsigned int expand_line_width : PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE; + unsigned int use_bres_cntl : PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE; + unsigned int bres_cntl : PA_SC_LINE_CNTL_BRES_CNTL_SIZE; + } pa_sc_line_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_line_cntl_t f; +} pa_sc_line_cntl_u; + + +/* + * PA_SC_WINDOW_SCISSOR_TL struct + */ + +#define PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE 14 +#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE 14 +#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE 1 + +#define PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT 0 +#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT 16 +#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT 31 + +#define PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK 0x00003fff +#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK 0x3fff0000 +#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK 0x80000000 + +#define PA_SC_WINDOW_SCISSOR_TL_MASK \ + (PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK | \ + PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK | \ + PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) + +#define PA_SC_WINDOW_SCISSOR_TL(tl_x, tl_y, window_offset_disable) \ + ((tl_x << PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT) | \ + (tl_y << PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT) | \ + (window_offset_disable << PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT)) + +#define PA_SC_WINDOW_SCISSOR_TL_GET_TL_X(pa_sc_window_scissor_tl) \ + ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK) >> PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT) +#define PA_SC_WINDOW_SCISSOR_TL_GET_TL_Y(pa_sc_window_scissor_tl) \ + ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK) >> PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT) +#define PA_SC_WINDOW_SCISSOR_TL_GET_WINDOW_OFFSET_DISABLE(pa_sc_window_scissor_tl) \ + ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) >> PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT) + +#define PA_SC_WINDOW_SCISSOR_TL_SET_TL_X(pa_sc_window_scissor_tl_reg, tl_x) \ + pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK) | (tl_x << PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT) +#define PA_SC_WINDOW_SCISSOR_TL_SET_TL_Y(pa_sc_window_scissor_tl_reg, tl_y) \ + pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK) | (tl_y << PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT) +#define PA_SC_WINDOW_SCISSOR_TL_SET_WINDOW_OFFSET_DISABLE(pa_sc_window_scissor_tl_reg, window_offset_disable) \ + pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) | (window_offset_disable << PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_window_scissor_tl_t { + unsigned int tl_x : PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE; + unsigned int : 2; + unsigned int tl_y : PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE; + unsigned int : 1; + unsigned int window_offset_disable : PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE; + } pa_sc_window_scissor_tl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_window_scissor_tl_t { + unsigned int window_offset_disable : PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE; + unsigned int : 1; + unsigned int tl_y : PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE; + unsigned int : 2; + unsigned int tl_x : PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE; + } pa_sc_window_scissor_tl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_window_scissor_tl_t f; +} pa_sc_window_scissor_tl_u; + + +/* + * PA_SC_WINDOW_SCISSOR_BR struct + */ + +#define PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE 14 +#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE 14 + +#define PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT 0 +#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT 16 + +#define PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK 0x00003fff +#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK 0x3fff0000 + +#define PA_SC_WINDOW_SCISSOR_BR_MASK \ + (PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK | \ + PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) + +#define PA_SC_WINDOW_SCISSOR_BR(br_x, br_y) \ + ((br_x << PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT) | \ + (br_y << PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT)) + +#define PA_SC_WINDOW_SCISSOR_BR_GET_BR_X(pa_sc_window_scissor_br) \ + ((pa_sc_window_scissor_br & PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK) >> PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT) +#define PA_SC_WINDOW_SCISSOR_BR_GET_BR_Y(pa_sc_window_scissor_br) \ + ((pa_sc_window_scissor_br & PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) >> PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT) + +#define PA_SC_WINDOW_SCISSOR_BR_SET_BR_X(pa_sc_window_scissor_br_reg, br_x) \ + pa_sc_window_scissor_br_reg = (pa_sc_window_scissor_br_reg & ~PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK) | (br_x << PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT) +#define PA_SC_WINDOW_SCISSOR_BR_SET_BR_Y(pa_sc_window_scissor_br_reg, br_y) \ + pa_sc_window_scissor_br_reg = (pa_sc_window_scissor_br_reg & ~PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) | (br_y << PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_window_scissor_br_t { + unsigned int br_x : PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE; + unsigned int : 2; + unsigned int br_y : PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE; + unsigned int : 2; + } pa_sc_window_scissor_br_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_window_scissor_br_t { + unsigned int : 2; + unsigned int br_y : PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE; + unsigned int : 2; + unsigned int br_x : PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE; + } pa_sc_window_scissor_br_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_window_scissor_br_t f; +} pa_sc_window_scissor_br_u; + + +/* + * PA_SC_SCREEN_SCISSOR_TL struct + */ + +#define PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE 15 +#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE 15 + +#define PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT 0 +#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT 16 + +#define PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK 0x00007fff +#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK 0x7fff0000 + +#define PA_SC_SCREEN_SCISSOR_TL_MASK \ + (PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK | \ + PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) + +#define PA_SC_SCREEN_SCISSOR_TL(tl_x, tl_y) \ + ((tl_x << PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT) | \ + (tl_y << PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT)) + +#define PA_SC_SCREEN_SCISSOR_TL_GET_TL_X(pa_sc_screen_scissor_tl) \ + ((pa_sc_screen_scissor_tl & PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK) >> PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT) +#define PA_SC_SCREEN_SCISSOR_TL_GET_TL_Y(pa_sc_screen_scissor_tl) \ + ((pa_sc_screen_scissor_tl & PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) >> PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT) + +#define PA_SC_SCREEN_SCISSOR_TL_SET_TL_X(pa_sc_screen_scissor_tl_reg, tl_x) \ + pa_sc_screen_scissor_tl_reg = (pa_sc_screen_scissor_tl_reg & ~PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK) | (tl_x << PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT) +#define PA_SC_SCREEN_SCISSOR_TL_SET_TL_Y(pa_sc_screen_scissor_tl_reg, tl_y) \ + pa_sc_screen_scissor_tl_reg = (pa_sc_screen_scissor_tl_reg & ~PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) | (tl_y << PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_screen_scissor_tl_t { + unsigned int tl_x : PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE; + unsigned int : 1; + unsigned int tl_y : PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE; + unsigned int : 1; + } pa_sc_screen_scissor_tl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_screen_scissor_tl_t { + unsigned int : 1; + unsigned int tl_y : PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE; + unsigned int : 1; + unsigned int tl_x : PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE; + } pa_sc_screen_scissor_tl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_screen_scissor_tl_t f; +} pa_sc_screen_scissor_tl_u; + + +/* + * PA_SC_SCREEN_SCISSOR_BR struct + */ + +#define PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE 15 +#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE 15 + +#define PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT 0 +#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT 16 + +#define PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK 0x00007fff +#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK 0x7fff0000 + +#define PA_SC_SCREEN_SCISSOR_BR_MASK \ + (PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK | \ + PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) + +#define PA_SC_SCREEN_SCISSOR_BR(br_x, br_y) \ + ((br_x << PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT) | \ + (br_y << PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT)) + +#define PA_SC_SCREEN_SCISSOR_BR_GET_BR_X(pa_sc_screen_scissor_br) \ + ((pa_sc_screen_scissor_br & PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK) >> PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT) +#define PA_SC_SCREEN_SCISSOR_BR_GET_BR_Y(pa_sc_screen_scissor_br) \ + ((pa_sc_screen_scissor_br & PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) >> PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT) + +#define PA_SC_SCREEN_SCISSOR_BR_SET_BR_X(pa_sc_screen_scissor_br_reg, br_x) \ + pa_sc_screen_scissor_br_reg = (pa_sc_screen_scissor_br_reg & ~PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK) | (br_x << PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT) +#define PA_SC_SCREEN_SCISSOR_BR_SET_BR_Y(pa_sc_screen_scissor_br_reg, br_y) \ + pa_sc_screen_scissor_br_reg = (pa_sc_screen_scissor_br_reg & ~PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) | (br_y << PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_screen_scissor_br_t { + unsigned int br_x : PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE; + unsigned int : 1; + unsigned int br_y : PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE; + unsigned int : 1; + } pa_sc_screen_scissor_br_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_screen_scissor_br_t { + unsigned int : 1; + unsigned int br_y : PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE; + unsigned int : 1; + unsigned int br_x : PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE; + } pa_sc_screen_scissor_br_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_screen_scissor_br_t f; +} pa_sc_screen_scissor_br_u; + + +/* + * PA_SC_VIZ_QUERY struct + */ + +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE 1 +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE 5 +#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE 1 + +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT 0 +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT 1 +#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT 7 + +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK 0x00000001 +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK 0x0000003e +#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK 0x00000080 + +#define PA_SC_VIZ_QUERY_MASK \ + (PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK | \ + PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK | \ + PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) + +#define PA_SC_VIZ_QUERY(viz_query_ena, viz_query_id, kill_pix_post_early_z) \ + ((viz_query_ena << PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT) | \ + (viz_query_id << PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT) | \ + (kill_pix_post_early_z << PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT)) + +#define PA_SC_VIZ_QUERY_GET_VIZ_QUERY_ENA(pa_sc_viz_query) \ + ((pa_sc_viz_query & PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK) >> PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT) +#define PA_SC_VIZ_QUERY_GET_VIZ_QUERY_ID(pa_sc_viz_query) \ + ((pa_sc_viz_query & PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK) >> PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT) +#define PA_SC_VIZ_QUERY_GET_KILL_PIX_POST_EARLY_Z(pa_sc_viz_query) \ + ((pa_sc_viz_query & PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) >> PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT) + +#define PA_SC_VIZ_QUERY_SET_VIZ_QUERY_ENA(pa_sc_viz_query_reg, viz_query_ena) \ + pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK) | (viz_query_ena << PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT) +#define PA_SC_VIZ_QUERY_SET_VIZ_QUERY_ID(pa_sc_viz_query_reg, viz_query_id) \ + pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK) | (viz_query_id << PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT) +#define PA_SC_VIZ_QUERY_SET_KILL_PIX_POST_EARLY_Z(pa_sc_viz_query_reg, kill_pix_post_early_z) \ + pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) | (kill_pix_post_early_z << PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_viz_query_t { + unsigned int viz_query_ena : PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE; + unsigned int viz_query_id : PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE; + unsigned int : 1; + unsigned int kill_pix_post_early_z : PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE; + unsigned int : 24; + } pa_sc_viz_query_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_viz_query_t { + unsigned int : 24; + unsigned int kill_pix_post_early_z : PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE; + unsigned int : 1; + unsigned int viz_query_id : PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE; + unsigned int viz_query_ena : PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE; + } pa_sc_viz_query_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_viz_query_t f; +} pa_sc_viz_query_u; + + +/* + * PA_SC_VIZ_QUERY_STATUS struct + */ + +#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE 32 + +#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT 0 + +#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK 0xffffffff + +#define PA_SC_VIZ_QUERY_STATUS_MASK \ + (PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) + +#define PA_SC_VIZ_QUERY_STATUS(status_bits) \ + ((status_bits << PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT)) + +#define PA_SC_VIZ_QUERY_STATUS_GET_STATUS_BITS(pa_sc_viz_query_status) \ + ((pa_sc_viz_query_status & PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) >> PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT) + +#define PA_SC_VIZ_QUERY_STATUS_SET_STATUS_BITS(pa_sc_viz_query_status_reg, status_bits) \ + pa_sc_viz_query_status_reg = (pa_sc_viz_query_status_reg & ~PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) | (status_bits << PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_viz_query_status_t { + unsigned int status_bits : PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE; + } pa_sc_viz_query_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_viz_query_status_t { + unsigned int status_bits : PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE; + } pa_sc_viz_query_status_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_viz_query_status_t f; +} pa_sc_viz_query_status_u; + + +/* + * PA_SC_LINE_STIPPLE_STATE struct + */ + +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE 4 +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE 8 + +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT 0 +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT 8 + +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK 0x0000000f +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK 0x0000ff00 + +#define PA_SC_LINE_STIPPLE_STATE_MASK \ + (PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK | \ + PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) + +#define PA_SC_LINE_STIPPLE_STATE(current_ptr, current_count) \ + ((current_ptr << PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT) | \ + (current_count << PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT)) + +#define PA_SC_LINE_STIPPLE_STATE_GET_CURRENT_PTR(pa_sc_line_stipple_state) \ + ((pa_sc_line_stipple_state & PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK) >> PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT) +#define PA_SC_LINE_STIPPLE_STATE_GET_CURRENT_COUNT(pa_sc_line_stipple_state) \ + ((pa_sc_line_stipple_state & PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) >> PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT) + +#define PA_SC_LINE_STIPPLE_STATE_SET_CURRENT_PTR(pa_sc_line_stipple_state_reg, current_ptr) \ + pa_sc_line_stipple_state_reg = (pa_sc_line_stipple_state_reg & ~PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK) | (current_ptr << PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT) +#define PA_SC_LINE_STIPPLE_STATE_SET_CURRENT_COUNT(pa_sc_line_stipple_state_reg, current_count) \ + pa_sc_line_stipple_state_reg = (pa_sc_line_stipple_state_reg & ~PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) | (current_count << PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_line_stipple_state_t { + unsigned int current_ptr : PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE; + unsigned int : 4; + unsigned int current_count : PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE; + unsigned int : 16; + } pa_sc_line_stipple_state_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_line_stipple_state_t { + unsigned int : 16; + unsigned int current_count : PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE; + unsigned int : 4; + unsigned int current_ptr : PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE; + } pa_sc_line_stipple_state_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_line_stipple_state_t f; +} pa_sc_line_stipple_state_u; + + +/* + * PA_SC_PERFCOUNTER0_SELECT struct + */ + +#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SC_PERFCOUNTER0_SELECT_MASK \ + (PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define PA_SC_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define PA_SC_PERFCOUNTER0_SELECT_GET_PERF_SEL(pa_sc_perfcounter0_select) \ + ((pa_sc_perfcounter0_select & PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define PA_SC_PERFCOUNTER0_SELECT_SET_PERF_SEL(pa_sc_perfcounter0_select_reg, perf_sel) \ + pa_sc_perfcounter0_select_reg = (pa_sc_perfcounter0_select_reg & ~PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_select_t { + unsigned int perf_sel : PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_sc_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } pa_sc_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_perfcounter0_select_t f; +} pa_sc_perfcounter0_select_u; + + +/* + * PA_SC_PERFCOUNTER0_LOW struct + */ + +#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SC_PERFCOUNTER0_LOW_MASK \ + (PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define PA_SC_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define PA_SC_PERFCOUNTER0_LOW_GET_PERF_COUNT(pa_sc_perfcounter0_low) \ + ((pa_sc_perfcounter0_low & PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define PA_SC_PERFCOUNTER0_LOW_SET_PERF_COUNT(pa_sc_perfcounter0_low_reg, perf_count) \ + pa_sc_perfcounter0_low_reg = (pa_sc_perfcounter0_low_reg & ~PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_low_t { + unsigned int perf_count : PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } pa_sc_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_low_t { + unsigned int perf_count : PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } pa_sc_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_perfcounter0_low_t f; +} pa_sc_perfcounter0_low_u; + + +/* + * PA_SC_PERFCOUNTER0_HI struct + */ + +#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SC_PERFCOUNTER0_HI_MASK \ + (PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define PA_SC_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define PA_SC_PERFCOUNTER0_HI_GET_PERF_COUNT(pa_sc_perfcounter0_hi) \ + ((pa_sc_perfcounter0_hi & PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define PA_SC_PERFCOUNTER0_HI_SET_PERF_COUNT(pa_sc_perfcounter0_hi_reg, perf_count) \ + pa_sc_perfcounter0_hi_reg = (pa_sc_perfcounter0_hi_reg & ~PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_hi_t { + unsigned int perf_count : PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_sc_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } pa_sc_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_perfcounter0_hi_t f; +} pa_sc_perfcounter0_hi_u; + + +/* + * PA_CL_CNTL_STATUS struct + */ + +#define PA_CL_CNTL_STATUS_CL_BUSY_SIZE 1 + +#define PA_CL_CNTL_STATUS_CL_BUSY_SHIFT 31 + +#define PA_CL_CNTL_STATUS_CL_BUSY_MASK 0x80000000 + +#define PA_CL_CNTL_STATUS_MASK \ + (PA_CL_CNTL_STATUS_CL_BUSY_MASK) + +#define PA_CL_CNTL_STATUS(cl_busy) \ + ((cl_busy << PA_CL_CNTL_STATUS_CL_BUSY_SHIFT)) + +#define PA_CL_CNTL_STATUS_GET_CL_BUSY(pa_cl_cntl_status) \ + ((pa_cl_cntl_status & PA_CL_CNTL_STATUS_CL_BUSY_MASK) >> PA_CL_CNTL_STATUS_CL_BUSY_SHIFT) + +#define PA_CL_CNTL_STATUS_SET_CL_BUSY(pa_cl_cntl_status_reg, cl_busy) \ + pa_cl_cntl_status_reg = (pa_cl_cntl_status_reg & ~PA_CL_CNTL_STATUS_CL_BUSY_MASK) | (cl_busy << PA_CL_CNTL_STATUS_CL_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_cntl_status_t { + unsigned int : 31; + unsigned int cl_busy : PA_CL_CNTL_STATUS_CL_BUSY_SIZE; + } pa_cl_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_cntl_status_t { + unsigned int cl_busy : PA_CL_CNTL_STATUS_CL_BUSY_SIZE; + unsigned int : 31; + } pa_cl_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_cntl_status_t f; +} pa_cl_cntl_status_u; + + +/* + * PA_SU_CNTL_STATUS struct + */ + +#define PA_SU_CNTL_STATUS_SU_BUSY_SIZE 1 + +#define PA_SU_CNTL_STATUS_SU_BUSY_SHIFT 31 + +#define PA_SU_CNTL_STATUS_SU_BUSY_MASK 0x80000000 + +#define PA_SU_CNTL_STATUS_MASK \ + (PA_SU_CNTL_STATUS_SU_BUSY_MASK) + +#define PA_SU_CNTL_STATUS(su_busy) \ + ((su_busy << PA_SU_CNTL_STATUS_SU_BUSY_SHIFT)) + +#define PA_SU_CNTL_STATUS_GET_SU_BUSY(pa_su_cntl_status) \ + ((pa_su_cntl_status & PA_SU_CNTL_STATUS_SU_BUSY_MASK) >> PA_SU_CNTL_STATUS_SU_BUSY_SHIFT) + +#define PA_SU_CNTL_STATUS_SET_SU_BUSY(pa_su_cntl_status_reg, su_busy) \ + pa_su_cntl_status_reg = (pa_su_cntl_status_reg & ~PA_SU_CNTL_STATUS_SU_BUSY_MASK) | (su_busy << PA_SU_CNTL_STATUS_SU_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_cntl_status_t { + unsigned int : 31; + unsigned int su_busy : PA_SU_CNTL_STATUS_SU_BUSY_SIZE; + } pa_su_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_cntl_status_t { + unsigned int su_busy : PA_SU_CNTL_STATUS_SU_BUSY_SIZE; + unsigned int : 31; + } pa_su_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_cntl_status_t f; +} pa_su_cntl_status_u; + + +/* + * PA_SC_CNTL_STATUS struct + */ + +#define PA_SC_CNTL_STATUS_SC_BUSY_SIZE 1 + +#define PA_SC_CNTL_STATUS_SC_BUSY_SHIFT 31 + +#define PA_SC_CNTL_STATUS_SC_BUSY_MASK 0x80000000 + +#define PA_SC_CNTL_STATUS_MASK \ + (PA_SC_CNTL_STATUS_SC_BUSY_MASK) + +#define PA_SC_CNTL_STATUS(sc_busy) \ + ((sc_busy << PA_SC_CNTL_STATUS_SC_BUSY_SHIFT)) + +#define PA_SC_CNTL_STATUS_GET_SC_BUSY(pa_sc_cntl_status) \ + ((pa_sc_cntl_status & PA_SC_CNTL_STATUS_SC_BUSY_MASK) >> PA_SC_CNTL_STATUS_SC_BUSY_SHIFT) + +#define PA_SC_CNTL_STATUS_SET_SC_BUSY(pa_sc_cntl_status_reg, sc_busy) \ + pa_sc_cntl_status_reg = (pa_sc_cntl_status_reg & ~PA_SC_CNTL_STATUS_SC_BUSY_MASK) | (sc_busy << PA_SC_CNTL_STATUS_SC_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_cntl_status_t { + unsigned int : 31; + unsigned int sc_busy : PA_SC_CNTL_STATUS_SC_BUSY_SIZE; + } pa_sc_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_cntl_status_t { + unsigned int sc_busy : PA_SC_CNTL_STATUS_SC_BUSY_SIZE; + unsigned int : 31; + } pa_sc_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_cntl_status_t f; +} pa_sc_cntl_status_u; + + +/* + * PA_SU_DEBUG_CNTL struct + */ + +#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE 5 + +#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT 0 + +#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK 0x0000001f + +#define PA_SU_DEBUG_CNTL_MASK \ + (PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) + +#define PA_SU_DEBUG_CNTL(su_debug_indx) \ + ((su_debug_indx << PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT)) + +#define PA_SU_DEBUG_CNTL_GET_SU_DEBUG_INDX(pa_su_debug_cntl) \ + ((pa_su_debug_cntl & PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) >> PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT) + +#define PA_SU_DEBUG_CNTL_SET_SU_DEBUG_INDX(pa_su_debug_cntl_reg, su_debug_indx) \ + pa_su_debug_cntl_reg = (pa_su_debug_cntl_reg & ~PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) | (su_debug_indx << PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_debug_cntl_t { + unsigned int su_debug_indx : PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE; + unsigned int : 27; + } pa_su_debug_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_debug_cntl_t { + unsigned int : 27; + unsigned int su_debug_indx : PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE; + } pa_su_debug_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_debug_cntl_t f; +} pa_su_debug_cntl_u; + + +/* + * PA_SU_DEBUG_DATA struct + */ + +#define PA_SU_DEBUG_DATA_DATA_SIZE 32 + +#define PA_SU_DEBUG_DATA_DATA_SHIFT 0 + +#define PA_SU_DEBUG_DATA_DATA_MASK 0xffffffff + +#define PA_SU_DEBUG_DATA_MASK \ + (PA_SU_DEBUG_DATA_DATA_MASK) + +#define PA_SU_DEBUG_DATA(data) \ + ((data << PA_SU_DEBUG_DATA_DATA_SHIFT)) + +#define PA_SU_DEBUG_DATA_GET_DATA(pa_su_debug_data) \ + ((pa_su_debug_data & PA_SU_DEBUG_DATA_DATA_MASK) >> PA_SU_DEBUG_DATA_DATA_SHIFT) + +#define PA_SU_DEBUG_DATA_SET_DATA(pa_su_debug_data_reg, data) \ + pa_su_debug_data_reg = (pa_su_debug_data_reg & ~PA_SU_DEBUG_DATA_DATA_MASK) | (data << PA_SU_DEBUG_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_debug_data_t { + unsigned int data : PA_SU_DEBUG_DATA_DATA_SIZE; + } pa_su_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_debug_data_t { + unsigned int data : PA_SU_DEBUG_DATA_DATA_SIZE; + } pa_su_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_debug_data_t f; +} pa_su_debug_data_u; + + +/* + * CLIPPER_DEBUG_REG00 struct + */ + +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE 12 + +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT 0 +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT 1 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT 2 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT 3 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT 4 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT 5 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT 6 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT 7 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT 8 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT 9 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT 10 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT 11 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT 12 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT 13 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT 14 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT 15 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT 16 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT 17 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT 18 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT 19 +#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT 20 + +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK 0x00000001 +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK 0x00000002 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK 0x00000004 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK 0x00000008 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK 0x00000010 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK 0x00000020 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK 0x00000040 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK 0x00000080 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK 0x00000100 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK 0x00000200 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK 0x00000400 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK 0x00000800 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK 0x00001000 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK 0x00002000 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK 0x00004000 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK 0x00008000 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK 0x00010000 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK 0x00020000 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK 0x00040000 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK 0x00080000 +#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK 0xfff00000 + +#define CLIPPER_DEBUG_REG00_MASK \ + (CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK | \ + CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK | \ + CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) + +#define CLIPPER_DEBUG_REG00(clip_ga_bc_fifo_write, clip_ga_bc_fifo_full, clip_to_ga_fifo_write, clip_to_ga_fifo_full, primic_to_clprim_fifo_empty, primic_to_clprim_fifo_full, clip_to_outsm_fifo_empty, clip_to_outsm_fifo_full, vgt_to_clipp_fifo_empty, vgt_to_clipp_fifo_full, vgt_to_clips_fifo_empty, vgt_to_clips_fifo_full, clipcode_fifo_fifo_empty, clipcode_fifo_full, vte_out_clip_fifo_fifo_empty, vte_out_clip_fifo_fifo_full, vte_out_orig_fifo_fifo_empty, vte_out_orig_fifo_fifo_full, ccgen_to_clipcc_fifo_empty, ccgen_to_clipcc_fifo_full, always_zero) \ + ((clip_ga_bc_fifo_write << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT) | \ + (clip_ga_bc_fifo_full << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT) | \ + (clip_to_ga_fifo_write << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT) | \ + (clip_to_ga_fifo_full << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT) | \ + (primic_to_clprim_fifo_empty << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT) | \ + (primic_to_clprim_fifo_full << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT) | \ + (clip_to_outsm_fifo_empty << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT) | \ + (clip_to_outsm_fifo_full << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT) | \ + (vgt_to_clipp_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT) | \ + (vgt_to_clipp_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT) | \ + (vgt_to_clips_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT) | \ + (vgt_to_clips_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT) | \ + (clipcode_fifo_fifo_empty << CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT) | \ + (clipcode_fifo_full << CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT) | \ + (vte_out_clip_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT) | \ + (vte_out_clip_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT) | \ + (vte_out_orig_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT) | \ + (vte_out_orig_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT) | \ + (ccgen_to_clipcc_fifo_empty << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT) | \ + (ccgen_to_clipcc_fifo_full << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT) | \ + (always_zero << CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT)) + +#define CLIPPER_DEBUG_REG00_GET_clip_ga_bc_fifo_write(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK) >> CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_ga_bc_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_to_ga_fifo_write(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK) >> CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_to_ga_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_primic_to_clprim_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_primic_to_clprim_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_to_outsm_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_to_outsm_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vgt_to_clipp_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vgt_to_clipp_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vgt_to_clips_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vgt_to_clips_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clipcode_fifo_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clipcode_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vte_out_clip_fifo_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vte_out_clip_fifo_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vte_out_orig_fifo_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vte_out_orig_fifo_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_ccgen_to_clipcc_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_ccgen_to_clipcc_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_ALWAYS_ZERO(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT) + +#define CLIPPER_DEBUG_REG00_SET_clip_ga_bc_fifo_write(clipper_debug_reg00_reg, clip_ga_bc_fifo_write) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK) | (clip_ga_bc_fifo_write << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_ga_bc_fifo_full(clipper_debug_reg00_reg, clip_ga_bc_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK) | (clip_ga_bc_fifo_full << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_to_ga_fifo_write(clipper_debug_reg00_reg, clip_to_ga_fifo_write) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK) | (clip_to_ga_fifo_write << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_to_ga_fifo_full(clipper_debug_reg00_reg, clip_to_ga_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK) | (clip_to_ga_fifo_full << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_primic_to_clprim_fifo_empty(clipper_debug_reg00_reg, primic_to_clprim_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK) | (primic_to_clprim_fifo_empty << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_primic_to_clprim_fifo_full(clipper_debug_reg00_reg, primic_to_clprim_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK) | (primic_to_clprim_fifo_full << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_to_outsm_fifo_empty(clipper_debug_reg00_reg, clip_to_outsm_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK) | (clip_to_outsm_fifo_empty << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_to_outsm_fifo_full(clipper_debug_reg00_reg, clip_to_outsm_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK) | (clip_to_outsm_fifo_full << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vgt_to_clipp_fifo_empty(clipper_debug_reg00_reg, vgt_to_clipp_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK) | (vgt_to_clipp_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vgt_to_clipp_fifo_full(clipper_debug_reg00_reg, vgt_to_clipp_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK) | (vgt_to_clipp_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vgt_to_clips_fifo_empty(clipper_debug_reg00_reg, vgt_to_clips_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK) | (vgt_to_clips_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vgt_to_clips_fifo_full(clipper_debug_reg00_reg, vgt_to_clips_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK) | (vgt_to_clips_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clipcode_fifo_fifo_empty(clipper_debug_reg00_reg, clipcode_fifo_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK) | (clipcode_fifo_fifo_empty << CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clipcode_fifo_full(clipper_debug_reg00_reg, clipcode_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK) | (clipcode_fifo_full << CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vte_out_clip_fifo_fifo_empty(clipper_debug_reg00_reg, vte_out_clip_fifo_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK) | (vte_out_clip_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vte_out_clip_fifo_fifo_full(clipper_debug_reg00_reg, vte_out_clip_fifo_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK) | (vte_out_clip_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vte_out_orig_fifo_fifo_empty(clipper_debug_reg00_reg, vte_out_orig_fifo_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK) | (vte_out_orig_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vte_out_orig_fifo_fifo_full(clipper_debug_reg00_reg, vte_out_orig_fifo_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK) | (vte_out_orig_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_ccgen_to_clipcc_fifo_empty(clipper_debug_reg00_reg, ccgen_to_clipcc_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK) | (ccgen_to_clipcc_fifo_empty << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_ccgen_to_clipcc_fifo_full(clipper_debug_reg00_reg, ccgen_to_clipcc_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK) | (ccgen_to_clipcc_fifo_full << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_ALWAYS_ZERO(clipper_debug_reg00_reg, always_zero) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg00_t { + unsigned int clip_ga_bc_fifo_write : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE; + unsigned int clip_ga_bc_fifo_full : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE; + unsigned int clip_to_ga_fifo_write : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE; + unsigned int clip_to_ga_fifo_full : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE; + unsigned int primic_to_clprim_fifo_empty : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE; + unsigned int primic_to_clprim_fifo_full : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE; + unsigned int clip_to_outsm_fifo_empty : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE; + unsigned int clip_to_outsm_fifo_full : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE; + unsigned int vgt_to_clipp_fifo_empty : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE; + unsigned int vgt_to_clipp_fifo_full : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE; + unsigned int vgt_to_clips_fifo_empty : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE; + unsigned int vgt_to_clips_fifo_full : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE; + unsigned int clipcode_fifo_fifo_empty : CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE; + unsigned int clipcode_fifo_full : CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE; + unsigned int vte_out_clip_fifo_fifo_empty : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE; + unsigned int vte_out_clip_fifo_fifo_full : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE; + unsigned int vte_out_orig_fifo_fifo_empty : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE; + unsigned int vte_out_orig_fifo_fifo_full : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE; + unsigned int ccgen_to_clipcc_fifo_empty : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE; + unsigned int ccgen_to_clipcc_fifo_full : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE; + unsigned int always_zero : CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE; + } clipper_debug_reg00_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg00_t { + unsigned int always_zero : CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE; + unsigned int ccgen_to_clipcc_fifo_full : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE; + unsigned int ccgen_to_clipcc_fifo_empty : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE; + unsigned int vte_out_orig_fifo_fifo_full : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE; + unsigned int vte_out_orig_fifo_fifo_empty : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE; + unsigned int vte_out_clip_fifo_fifo_full : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE; + unsigned int vte_out_clip_fifo_fifo_empty : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE; + unsigned int clipcode_fifo_full : CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE; + unsigned int clipcode_fifo_fifo_empty : CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE; + unsigned int vgt_to_clips_fifo_full : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE; + unsigned int vgt_to_clips_fifo_empty : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE; + unsigned int vgt_to_clipp_fifo_full : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE; + unsigned int vgt_to_clipp_fifo_empty : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE; + unsigned int clip_to_outsm_fifo_full : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE; + unsigned int clip_to_outsm_fifo_empty : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE; + unsigned int primic_to_clprim_fifo_full : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE; + unsigned int primic_to_clprim_fifo_empty : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE; + unsigned int clip_to_ga_fifo_full : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE; + unsigned int clip_to_ga_fifo_write : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE; + unsigned int clip_ga_bc_fifo_full : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE; + unsigned int clip_ga_bc_fifo_write : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE; + } clipper_debug_reg00_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg00_t f; +} clipper_debug_reg00_u; + + +/* + * CLIPPER_DEBUG_REG01 struct + */ + +#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE 3 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE 4 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE 4 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE 4 +#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE 3 +#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE 2 +#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE 8 + +#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT 0 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT 2 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT 5 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT 6 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT 7 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT 11 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT 15 +#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT 19 +#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT 22 +#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT 24 + +#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK 0x00000001 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK 0x00000002 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK 0x0000001c +#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK 0x00000020 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK 0x00000040 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK 0x00000780 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK 0x00007800 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK 0x00078000 +#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK 0x00380000 +#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK 0x00c00000 +#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK 0xff000000 + +#define CLIPPER_DEBUG_REG01_MASK \ + (CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK | \ + CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK | \ + CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK | \ + CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) + +#define CLIPPER_DEBUG_REG01(clip_to_outsm_end_of_packet, clip_to_outsm_first_prim_of_slot, clip_to_outsm_deallocate_slot, clip_to_outsm_clipped_prim, clip_to_outsm_null_primitive, clip_to_outsm_vertex_store_indx_2, clip_to_outsm_vertex_store_indx_1, clip_to_outsm_vertex_store_indx_0, clip_vert_vte_valid, vte_out_clip_rd_vertex_store_indx, always_zero) \ + ((clip_to_outsm_end_of_packet << CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT) | \ + (clip_to_outsm_first_prim_of_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT) | \ + (clip_to_outsm_deallocate_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT) | \ + (clip_to_outsm_clipped_prim << CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT) | \ + (clip_to_outsm_null_primitive << CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT) | \ + (clip_to_outsm_vertex_store_indx_2 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT) | \ + (clip_to_outsm_vertex_store_indx_1 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT) | \ + (clip_to_outsm_vertex_store_indx_0 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT) | \ + (clip_vert_vte_valid << CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT) | \ + (vte_out_clip_rd_vertex_store_indx << CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT) | \ + (always_zero << CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT)) + +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_end_of_packet(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_first_prim_of_slot(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_deallocate_slot(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_clipped_prim(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_null_primitive(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_2(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_1(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_0(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_vert_vte_valid(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK) >> CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_vte_out_clip_rd_vertex_store_indx(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK) >> CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_ALWAYS_ZERO(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT) + +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_end_of_packet(clipper_debug_reg01_reg, clip_to_outsm_end_of_packet) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK) | (clip_to_outsm_end_of_packet << CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_first_prim_of_slot(clipper_debug_reg01_reg, clip_to_outsm_first_prim_of_slot) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK) | (clip_to_outsm_first_prim_of_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_deallocate_slot(clipper_debug_reg01_reg, clip_to_outsm_deallocate_slot) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK) | (clip_to_outsm_deallocate_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_clipped_prim(clipper_debug_reg01_reg, clip_to_outsm_clipped_prim) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK) | (clip_to_outsm_clipped_prim << CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_null_primitive(clipper_debug_reg01_reg, clip_to_outsm_null_primitive) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK) | (clip_to_outsm_null_primitive << CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_2(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_2) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK) | (clip_to_outsm_vertex_store_indx_2 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_1(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_1) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK) | (clip_to_outsm_vertex_store_indx_1 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_0(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_0) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK) | (clip_to_outsm_vertex_store_indx_0 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_vert_vte_valid(clipper_debug_reg01_reg, clip_vert_vte_valid) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK) | (clip_vert_vte_valid << CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_vte_out_clip_rd_vertex_store_indx(clipper_debug_reg01_reg, vte_out_clip_rd_vertex_store_indx) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK) | (vte_out_clip_rd_vertex_store_indx << CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_ALWAYS_ZERO(clipper_debug_reg01_reg, always_zero) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg01_t { + unsigned int clip_to_outsm_end_of_packet : CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE; + unsigned int clip_to_outsm_first_prim_of_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE; + unsigned int clip_to_outsm_deallocate_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE; + unsigned int clip_to_outsm_clipped_prim : CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE; + unsigned int clip_to_outsm_null_primitive : CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_2 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_1 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_0 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE; + unsigned int clip_vert_vte_valid : CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE; + unsigned int vte_out_clip_rd_vertex_store_indx : CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE; + unsigned int always_zero : CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE; + } clipper_debug_reg01_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg01_t { + unsigned int always_zero : CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE; + unsigned int vte_out_clip_rd_vertex_store_indx : CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE; + unsigned int clip_vert_vte_valid : CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_0 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_1 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_2 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE; + unsigned int clip_to_outsm_null_primitive : CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE; + unsigned int clip_to_outsm_clipped_prim : CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE; + unsigned int clip_to_outsm_deallocate_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE; + unsigned int clip_to_outsm_first_prim_of_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE; + unsigned int clip_to_outsm_end_of_packet : CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE; + } clipper_debug_reg01_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg01_t f; +} clipper_debug_reg01_u; + + +/* + * CLIPPER_DEBUG_REG02 struct + */ + +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE 21 +#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE 3 +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE 7 +#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE 1 + +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT 0 +#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT 21 +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT 24 +#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT 31 + +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK 0x001fffff +#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00e00000 +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK 0x7f000000 +#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000 + +#define CLIPPER_DEBUG_REG02_MASK \ + (CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK | \ + CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK | \ + CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) + +#define CLIPPER_DEBUG_REG02(always_zero1, clipsm0_clip_to_clipga_clip_to_outsm_cnt, always_zero0, clipsm0_clprim_to_clip_prim_valid) \ + ((always_zero1 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT) | \ + (clipsm0_clip_to_clipga_clip_to_outsm_cnt << CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT) | \ + (clipsm0_clprim_to_clip_prim_valid << CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT)) + +#define CLIPPER_DEBUG_REG02_GET_ALWAYS_ZERO1(clipper_debug_reg02) \ + ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG02_GET_clipsm0_clip_to_clipga_clip_to_outsm_cnt(clipper_debug_reg02) \ + ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK) >> CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT) +#define CLIPPER_DEBUG_REG02_GET_ALWAYS_ZERO0(clipper_debug_reg02) \ + ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG02_GET_clipsm0_clprim_to_clip_prim_valid(clipper_debug_reg02) \ + ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) >> CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT) + +#define CLIPPER_DEBUG_REG02_SET_ALWAYS_ZERO1(clipper_debug_reg02_reg, always_zero1) \ + clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG02_SET_clipsm0_clip_to_clipga_clip_to_outsm_cnt(clipper_debug_reg02_reg, clipsm0_clip_to_clipga_clip_to_outsm_cnt) \ + clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK) | (clipsm0_clip_to_clipga_clip_to_outsm_cnt << CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT) +#define CLIPPER_DEBUG_REG02_SET_ALWAYS_ZERO0(clipper_debug_reg02_reg, always_zero0) \ + clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG02_SET_clipsm0_clprim_to_clip_prim_valid(clipper_debug_reg02_reg, clipsm0_clprim_to_clip_prim_valid) \ + clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) | (clipsm0_clprim_to_clip_prim_valid << CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg02_t { + unsigned int always_zero1 : CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clprim_to_clip_prim_valid : CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE; + } clipper_debug_reg02_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg02_t { + unsigned int clipsm0_clprim_to_clip_prim_valid : CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE; + } clipper_debug_reg02_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg02_t f; +} clipper_debug_reg02_u; + + +/* + * CLIPPER_DEBUG_REG03 struct + */ + +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE 3 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE 1 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE 3 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE 1 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE 12 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE 6 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE 6 + +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT 0 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT 3 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT 4 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT 7 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT 8 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT 20 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT 26 + +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK 0x00000007 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK 0x00000008 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK 0x00000070 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK 0x00000080 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK 0x000fff00 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK 0x03f00000 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK 0xfc000000 + +#define CLIPPER_DEBUG_REG03_MASK \ + (CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK | \ + CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK | \ + CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK | \ + CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK | \ + CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG03(always_zero3, clipsm0_clprim_to_clip_clip_primitive, always_zero2, clipsm0_clprim_to_clip_null_primitive, always_zero1, clipsm0_clprim_to_clip_clip_code_or, always_zero0) \ + ((always_zero3 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT) | \ + (clipsm0_clprim_to_clip_clip_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT) | \ + (clipsm0_clprim_to_clip_null_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT) | \ + (clipsm0_clprim_to_clip_clip_code_or << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO3(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_clip_primitive(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO2(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_null_primitive(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO1(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_clip_code_or(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO0(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO3(clipper_debug_reg03_reg, always_zero3) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_clip_primitive(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_clip_primitive) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK) | (clipsm0_clprim_to_clip_clip_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO2(clipper_debug_reg03_reg, always_zero2) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_null_primitive(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_null_primitive) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK) | (clipsm0_clprim_to_clip_null_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO1(clipper_debug_reg03_reg, always_zero1) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_clip_code_or(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_clip_code_or) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK) | (clipsm0_clprim_to_clip_clip_code_or << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO0(clipper_debug_reg03_reg, always_zero0) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg03_t { + unsigned int always_zero3 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE; + unsigned int clipsm0_clprim_to_clip_clip_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_null_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_clip_code_or : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg03_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg03_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clprim_to_clip_clip_code_or : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_null_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_clip_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE; + } clipper_debug_reg03_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg03_t f; +} clipper_debug_reg03_u; + + +/* + * CLIPPER_DEBUG_REG04 struct + */ + +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE 3 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE 1 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE 3 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE 1 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE 24 + +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT 0 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT 3 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT 4 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT 7 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT 8 + +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK 0x00000007 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x00000008 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK 0x00000070 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK 0x00000080 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK 0xffffff00 + +#define CLIPPER_DEBUG_REG04_MASK \ + (CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK | \ + CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK | \ + CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG04(always_zero2, clipsm0_clprim_to_clip_first_prim_of_slot, always_zero1, clipsm0_clprim_to_clip_event, always_zero0) \ + ((always_zero2 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT) | \ + (clipsm0_clprim_to_clip_first_prim_of_slot << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT) | \ + (clipsm0_clprim_to_clip_event << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO2(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG04_GET_clipsm0_clprim_to_clip_first_prim_of_slot(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO1(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG04_GET_clipsm0_clprim_to_clip_event(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK) >> CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT) +#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO0(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO2(clipper_debug_reg04_reg, always_zero2) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG04_SET_clipsm0_clprim_to_clip_first_prim_of_slot(clipper_debug_reg04_reg, clipsm0_clprim_to_clip_first_prim_of_slot) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK) | (clipsm0_clprim_to_clip_first_prim_of_slot << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO1(clipper_debug_reg04_reg, always_zero1) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG04_SET_clipsm0_clprim_to_clip_event(clipper_debug_reg04_reg, clipsm0_clprim_to_clip_event) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK) | (clipsm0_clprim_to_clip_event << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT) +#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO0(clipper_debug_reg04_reg, always_zero0) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg04_t { + unsigned int always_zero2 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_event : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg04_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg04_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clprim_to_clip_event : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE; + } clipper_debug_reg04_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg04_t f; +} clipper_debug_reg04_u; + + +/* + * CLIPPER_DEBUG_REG05 struct + */ + +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE 1 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE 2 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE 3 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE 6 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE 4 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE 2 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE 4 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE 2 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE 4 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE 4 + +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT 0 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT 1 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT 3 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT 6 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT 12 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT 16 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT 18 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT 22 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT 24 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT 28 + +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK 0x00000001 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK 0x00000006 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK 0x00000038 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK 0x00000fc0 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0000f000 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK 0x00030000 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x003c0000 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK 0x00c00000 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x0f000000 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK 0xf0000000 + +#define CLIPPER_DEBUG_REG05_MASK \ + (CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK | \ + CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK | \ + CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK | \ + CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK | \ + CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG05(clipsm0_clprim_to_clip_state_var_indx, always_zero3, clipsm0_clprim_to_clip_deallocate_slot, clipsm0_clprim_to_clip_event_id, clipsm0_clprim_to_clip_vertex_store_indx_2, always_zero2, clipsm0_clprim_to_clip_vertex_store_indx_1, always_zero1, clipsm0_clprim_to_clip_vertex_store_indx_0, always_zero0) \ + ((clipsm0_clprim_to_clip_state_var_indx << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT) | \ + (always_zero3 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT) | \ + (clipsm0_clprim_to_clip_deallocate_slot << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT) | \ + (clipsm0_clprim_to_clip_event_id << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT) | \ + (clipsm0_clprim_to_clip_vertex_store_indx_2 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT) | \ + (clipsm0_clprim_to_clip_vertex_store_indx_1 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT) | \ + (clipsm0_clprim_to_clip_vertex_store_indx_0 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_state_var_indx(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO3(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_deallocate_slot(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_event_id(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_2(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO2(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_1(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO1(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_0(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO0(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_state_var_indx(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_state_var_indx) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK) | (clipsm0_clprim_to_clip_state_var_indx << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO3(clipper_debug_reg05_reg, always_zero3) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_deallocate_slot(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_deallocate_slot) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK) | (clipsm0_clprim_to_clip_deallocate_slot << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_event_id(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_event_id) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK) | (clipsm0_clprim_to_clip_event_id << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_2(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_2) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_2 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO2(clipper_debug_reg05_reg, always_zero2) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_1(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_1) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_1 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO1(clipper_debug_reg05_reg, always_zero1) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_0(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_0) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_0 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO0(clipper_debug_reg05_reg, always_zero0) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg05_t { + unsigned int clipsm0_clprim_to_clip_state_var_indx : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE; + unsigned int clipsm0_clprim_to_clip_deallocate_slot : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE; + unsigned int clipsm0_clprim_to_clip_event_id : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg05_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg05_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE; + unsigned int clipsm0_clprim_to_clip_event_id : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE; + unsigned int clipsm0_clprim_to_clip_deallocate_slot : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE; + unsigned int clipsm0_clprim_to_clip_state_var_indx : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE; + } clipper_debug_reg05_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg05_t f; +} clipper_debug_reg05_u; + + +/* + * CLIPPER_DEBUG_REG09 struct + */ + +#define CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE 1 +#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE 1 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE 4 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE 2 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE 4 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE 2 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE 4 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE 2 +#define CLIPPER_DEBUG_REG09_prim_back_valid_SIZE 1 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE 4 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE 2 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE 1 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE 2 + +#define CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT 0 +#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT 1 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT 2 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT 6 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT 8 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT 12 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT 14 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT 18 +#define CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT 20 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT 21 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT 25 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT 27 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT 28 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT 29 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT 30 + +#define CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK 0x00000001 +#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK 0x00000002 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK 0x0000003c +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK 0x000000c0 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK 0x00000f00 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK 0x00003000 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK 0x0003c000 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK 0x000c0000 +#define CLIPPER_DEBUG_REG09_prim_back_valid_MASK 0x00100000 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK 0x01e00000 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK 0x06000000 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK 0x08000000 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK 0x10000000 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK 0x20000000 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK 0xc0000000 + +#define CLIPPER_DEBUG_REG09_MASK \ + (CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK | \ + CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK | \ + CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK | \ + CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK | \ + CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK | \ + CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK | \ + CLIPPER_DEBUG_REG09_prim_back_valid_MASK | \ + CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK | \ + CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK | \ + CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK | \ + CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK | \ + CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) + +#define CLIPPER_DEBUG_REG09(clprim_in_back_event, outputclprimtoclip_null_primitive, clprim_in_back_vertex_store_indx_2, always_zero2, clprim_in_back_vertex_store_indx_1, always_zero1, clprim_in_back_vertex_store_indx_0, always_zero0, prim_back_valid, clip_priority_seq_indx_out_cnt, outsm_clr_rd_orig_vertices, outsm_clr_rd_clipsm_wait, outsm_clr_fifo_empty, outsm_clr_fifo_full, clip_priority_seq_indx_load) \ + ((clprim_in_back_event << CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT) | \ + (outputclprimtoclip_null_primitive << CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT) | \ + (clprim_in_back_vertex_store_indx_2 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT) | \ + (clprim_in_back_vertex_store_indx_1 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT) | \ + (clprim_in_back_vertex_store_indx_0 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT) | \ + (prim_back_valid << CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT) | \ + (clip_priority_seq_indx_out_cnt << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT) | \ + (outsm_clr_rd_orig_vertices << CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT) | \ + (outsm_clr_rd_clipsm_wait << CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT) | \ + (outsm_clr_fifo_empty << CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT) | \ + (outsm_clr_fifo_full << CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT) | \ + (clip_priority_seq_indx_load << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT)) + +#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_event(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outputclprimtoclip_null_primitive(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK) >> CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_2(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO2(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_1(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO1(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_0(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO0(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_prim_back_valid(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_prim_back_valid_MASK) >> CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clip_priority_seq_indx_out_cnt(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK) >> CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outsm_clr_rd_orig_vertices(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outsm_clr_rd_clipsm_wait(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outsm_clr_fifo_empty(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outsm_clr_fifo_full(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clip_priority_seq_indx_load(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) >> CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT) + +#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_event(clipper_debug_reg09_reg, clprim_in_back_event) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK) | (clprim_in_back_event << CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outputclprimtoclip_null_primitive(clipper_debug_reg09_reg, outputclprimtoclip_null_primitive) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK) | (outputclprimtoclip_null_primitive << CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_2(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_2) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK) | (clprim_in_back_vertex_store_indx_2 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO2(clipper_debug_reg09_reg, always_zero2) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_1(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_1) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK) | (clprim_in_back_vertex_store_indx_1 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO1(clipper_debug_reg09_reg, always_zero1) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_0(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_0) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK) | (clprim_in_back_vertex_store_indx_0 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO0(clipper_debug_reg09_reg, always_zero0) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_prim_back_valid(clipper_debug_reg09_reg, prim_back_valid) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_prim_back_valid_MASK) | (prim_back_valid << CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clip_priority_seq_indx_out_cnt(clipper_debug_reg09_reg, clip_priority_seq_indx_out_cnt) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK) | (clip_priority_seq_indx_out_cnt << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outsm_clr_rd_orig_vertices(clipper_debug_reg09_reg, outsm_clr_rd_orig_vertices) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK) | (outsm_clr_rd_orig_vertices << CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outsm_clr_rd_clipsm_wait(clipper_debug_reg09_reg, outsm_clr_rd_clipsm_wait) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK) | (outsm_clr_rd_clipsm_wait << CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outsm_clr_fifo_empty(clipper_debug_reg09_reg, outsm_clr_fifo_empty) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK) | (outsm_clr_fifo_empty << CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outsm_clr_fifo_full(clipper_debug_reg09_reg, outsm_clr_fifo_full) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK) | (outsm_clr_fifo_full << CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clip_priority_seq_indx_load(clipper_debug_reg09_reg, clip_priority_seq_indx_load) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) | (clip_priority_seq_indx_load << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg09_t { + unsigned int clprim_in_back_event : CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE; + unsigned int outputclprimtoclip_null_primitive : CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE; + unsigned int clprim_in_back_vertex_store_indx_2 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE; + unsigned int clprim_in_back_vertex_store_indx_1 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE; + unsigned int clprim_in_back_vertex_store_indx_0 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE; + unsigned int prim_back_valid : CLIPPER_DEBUG_REG09_prim_back_valid_SIZE; + unsigned int clip_priority_seq_indx_out_cnt : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE; + unsigned int outsm_clr_rd_orig_vertices : CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE; + unsigned int outsm_clr_rd_clipsm_wait : CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE; + unsigned int outsm_clr_fifo_empty : CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE; + unsigned int outsm_clr_fifo_full : CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE; + unsigned int clip_priority_seq_indx_load : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE; + } clipper_debug_reg09_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg09_t { + unsigned int clip_priority_seq_indx_load : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE; + unsigned int outsm_clr_fifo_full : CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE; + unsigned int outsm_clr_fifo_empty : CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE; + unsigned int outsm_clr_rd_clipsm_wait : CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE; + unsigned int outsm_clr_rd_orig_vertices : CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE; + unsigned int clip_priority_seq_indx_out_cnt : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE; + unsigned int prim_back_valid : CLIPPER_DEBUG_REG09_prim_back_valid_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE; + unsigned int clprim_in_back_vertex_store_indx_0 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE; + unsigned int clprim_in_back_vertex_store_indx_1 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE; + unsigned int clprim_in_back_vertex_store_indx_2 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE; + unsigned int outputclprimtoclip_null_primitive : CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE; + unsigned int clprim_in_back_event : CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE; + } clipper_debug_reg09_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg09_t f; +} clipper_debug_reg09_u; + + +/* + * CLIPPER_DEBUG_REG10 struct + */ + +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE 4 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE 2 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE 4 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE 2 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE 4 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE 2 +#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE 1 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE 2 +#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE 1 +#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE 1 +#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE 3 +#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE 6 + +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT 0 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT 4 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT 6 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT 10 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT 12 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT 16 +#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT 18 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT 19 +#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT 21 +#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT 22 +#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT 23 +#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT 26 + +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x0000000f +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK 0x00000030 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x000003c0 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK 0x00000c00 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x0000f000 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK 0x00030000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK 0x00040000 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK 0x00180000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK 0x00200000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK 0x00400000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK 0x03800000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK 0xfc000000 + +#define CLIPPER_DEBUG_REG10_MASK \ + (CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK | \ + CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK | \ + CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK | \ + CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK | \ + CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK | \ + CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) + +#define CLIPPER_DEBUG_REG10(primic_to_clprim_fifo_vertex_store_indx_2, always_zero3, primic_to_clprim_fifo_vertex_store_indx_1, always_zero2, primic_to_clprim_fifo_vertex_store_indx_0, always_zero1, clprim_in_back_state_var_indx, always_zero0, clprim_in_back_end_of_packet, clprim_in_back_first_prim_of_slot, clprim_in_back_deallocate_slot, clprim_in_back_event_id) \ + ((primic_to_clprim_fifo_vertex_store_indx_2 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT) | \ + (always_zero3 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT) | \ + (primic_to_clprim_fifo_vertex_store_indx_1 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT) | \ + (primic_to_clprim_fifo_vertex_store_indx_0 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT) | \ + (clprim_in_back_state_var_indx << CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT) | \ + (clprim_in_back_end_of_packet << CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT) | \ + (clprim_in_back_first_prim_of_slot << CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT) | \ + (clprim_in_back_deallocate_slot << CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT) | \ + (clprim_in_back_event_id << CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT)) + +#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_2(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO3(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_1(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO2(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_0(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO1(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_state_var_indx(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO0(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_end_of_packet(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_first_prim_of_slot(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_deallocate_slot(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_event_id(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT) + +#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_2(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_2) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK) | (primic_to_clprim_fifo_vertex_store_indx_2 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO3(clipper_debug_reg10_reg, always_zero3) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_1(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_1) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK) | (primic_to_clprim_fifo_vertex_store_indx_1 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO2(clipper_debug_reg10_reg, always_zero2) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_0(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_0) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK) | (primic_to_clprim_fifo_vertex_store_indx_0 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO1(clipper_debug_reg10_reg, always_zero1) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_state_var_indx(clipper_debug_reg10_reg, clprim_in_back_state_var_indx) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK) | (clprim_in_back_state_var_indx << CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO0(clipper_debug_reg10_reg, always_zero0) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_end_of_packet(clipper_debug_reg10_reg, clprim_in_back_end_of_packet) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK) | (clprim_in_back_end_of_packet << CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_first_prim_of_slot(clipper_debug_reg10_reg, clprim_in_back_first_prim_of_slot) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK) | (clprim_in_back_first_prim_of_slot << CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_deallocate_slot(clipper_debug_reg10_reg, clprim_in_back_deallocate_slot) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK) | (clprim_in_back_deallocate_slot << CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_event_id(clipper_debug_reg10_reg, clprim_in_back_event_id) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) | (clprim_in_back_event_id << CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg10_t { + unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE; + unsigned int clprim_in_back_state_var_indx : CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE; + unsigned int clprim_in_back_end_of_packet : CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE; + unsigned int clprim_in_back_first_prim_of_slot : CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE; + unsigned int clprim_in_back_deallocate_slot : CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE; + unsigned int clprim_in_back_event_id : CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE; + } clipper_debug_reg10_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg10_t { + unsigned int clprim_in_back_event_id : CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE; + unsigned int clprim_in_back_deallocate_slot : CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE; + unsigned int clprim_in_back_first_prim_of_slot : CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE; + unsigned int clprim_in_back_end_of_packet : CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE; + unsigned int clprim_in_back_state_var_indx : CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE; + } clipper_debug_reg10_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg10_t f; +} clipper_debug_reg10_u; + + +/* + * CLIPPER_DEBUG_REG11 struct + */ + +#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE 4 +#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE 28 + +#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT 0 +#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT 4 + +#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK 0x0000000f +#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK 0xfffffff0 + +#define CLIPPER_DEBUG_REG11_MASK \ + (CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK | \ + CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) + +#define CLIPPER_DEBUG_REG11(vertval_bits_vertex_vertex_store_msb, always_zero) \ + ((vertval_bits_vertex_vertex_store_msb << CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT) | \ + (always_zero << CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT)) + +#define CLIPPER_DEBUG_REG11_GET_vertval_bits_vertex_vertex_store_msb(clipper_debug_reg11) \ + ((clipper_debug_reg11 & CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK) >> CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT) +#define CLIPPER_DEBUG_REG11_GET_ALWAYS_ZERO(clipper_debug_reg11) \ + ((clipper_debug_reg11 & CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT) + +#define CLIPPER_DEBUG_REG11_SET_vertval_bits_vertex_vertex_store_msb(clipper_debug_reg11_reg, vertval_bits_vertex_vertex_store_msb) \ + clipper_debug_reg11_reg = (clipper_debug_reg11_reg & ~CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK) | (vertval_bits_vertex_vertex_store_msb << CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT) +#define CLIPPER_DEBUG_REG11_SET_ALWAYS_ZERO(clipper_debug_reg11_reg, always_zero) \ + clipper_debug_reg11_reg = (clipper_debug_reg11_reg & ~CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg11_t { + unsigned int vertval_bits_vertex_vertex_store_msb : CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE; + unsigned int always_zero : CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE; + } clipper_debug_reg11_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg11_t { + unsigned int always_zero : CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE; + unsigned int vertval_bits_vertex_vertex_store_msb : CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE; + } clipper_debug_reg11_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg11_t f; +} clipper_debug_reg11_u; + + +/* + * CLIPPER_DEBUG_REG12 struct + */ + +#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE 2 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE 3 +#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE 5 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE 4 +#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE 4 +#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE 2 +#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE 1 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE 10 + +#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT 0 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT 2 +#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT 5 +#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT 6 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT 11 +#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT 15 +#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT 19 +#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT 21 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT 22 + +#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK 0x00000003 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK 0x0000001c +#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK 0x00000020 +#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK 0x000007c0 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK 0x00007800 +#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK 0x00078000 +#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK 0x00180000 +#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK 0x00200000 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK 0xffc00000 + +#define CLIPPER_DEBUG_REG12_MASK \ + (CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK | \ + CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK | \ + CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK | \ + CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK | \ + CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK | \ + CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG12(clip_priority_available_vte_out_clip, always_zero2, clip_vertex_fifo_empty, clip_priority_available_clip_verts, always_zero1, vertval_bits_vertex_cc_next_valid, clipcc_vertex_store_indx, primic_to_clprim_valid, always_zero0) \ + ((clip_priority_available_vte_out_clip << CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT) | \ + (clip_vertex_fifo_empty << CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT) | \ + (clip_priority_available_clip_verts << CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT) | \ + (vertval_bits_vertex_cc_next_valid << CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT) | \ + (clipcc_vertex_store_indx << CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT) | \ + (primic_to_clprim_valid << CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG12_GET_clip_priority_available_vte_out_clip(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK) >> CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO2(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_clip_vertex_fifo_empty(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK) >> CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_clip_priority_available_clip_verts(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK) >> CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO1(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_vertval_bits_vertex_cc_next_valid(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK) >> CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_clipcc_vertex_store_indx(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK) >> CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_primic_to_clprim_valid(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK) >> CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO0(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG12_SET_clip_priority_available_vte_out_clip(clipper_debug_reg12_reg, clip_priority_available_vte_out_clip) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK) | (clip_priority_available_vte_out_clip << CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO2(clipper_debug_reg12_reg, always_zero2) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_clip_vertex_fifo_empty(clipper_debug_reg12_reg, clip_vertex_fifo_empty) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK) | (clip_vertex_fifo_empty << CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_clip_priority_available_clip_verts(clipper_debug_reg12_reg, clip_priority_available_clip_verts) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK) | (clip_priority_available_clip_verts << CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO1(clipper_debug_reg12_reg, always_zero1) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_vertval_bits_vertex_cc_next_valid(clipper_debug_reg12_reg, vertval_bits_vertex_cc_next_valid) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK) | (vertval_bits_vertex_cc_next_valid << CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_clipcc_vertex_store_indx(clipper_debug_reg12_reg, clipcc_vertex_store_indx) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK) | (clipcc_vertex_store_indx << CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_primic_to_clprim_valid(clipper_debug_reg12_reg, primic_to_clprim_valid) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK) | (primic_to_clprim_valid << CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO0(clipper_debug_reg12_reg, always_zero0) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg12_t { + unsigned int clip_priority_available_vte_out_clip : CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE; + unsigned int clip_vertex_fifo_empty : CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE; + unsigned int clip_priority_available_clip_verts : CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE; + unsigned int vertval_bits_vertex_cc_next_valid : CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE; + unsigned int clipcc_vertex_store_indx : CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE; + unsigned int primic_to_clprim_valid : CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg12_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg12_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE; + unsigned int primic_to_clprim_valid : CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE; + unsigned int clipcc_vertex_store_indx : CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE; + unsigned int vertval_bits_vertex_cc_next_valid : CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE; + unsigned int clip_priority_available_clip_verts : CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE; + unsigned int clip_vertex_fifo_empty : CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE; + unsigned int clip_priority_available_vte_out_clip : CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE; + } clipper_debug_reg12_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg12_t f; +} clipper_debug_reg12_u; + + +/* + * CLIPPER_DEBUG_REG13 struct + */ + +#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE 4 +#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE 7 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE 3 +#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE 4 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE 1 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE 1 +#define CLIPPER_DEBUG_REG13_sm0_current_state_SIZE 7 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE 5 + +#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT 0 +#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT 4 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT 11 +#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT 14 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT 18 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT 19 +#define CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT 20 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT 27 + +#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK 0x0000000f +#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK 0x000007f0 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK 0x00003800 +#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK 0x0003c000 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK 0x00040000 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK 0x00080000 +#define CLIPPER_DEBUG_REG13_sm0_current_state_MASK 0x07f00000 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK 0xf8000000 + +#define CLIPPER_DEBUG_REG13_MASK \ + (CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK | \ + CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK | \ + CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK | \ + CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK | \ + CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK | \ + CLIPPER_DEBUG_REG13_sm0_current_state_MASK | \ + CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG13(sm0_clip_vert_cnt, sm0_prim_end_state, always_zero1, sm0_vertex_clip_cnt, sm0_inv_to_clip_data_valid_1, sm0_inv_to_clip_data_valid_0, sm0_current_state, always_zero0) \ + ((sm0_clip_vert_cnt << CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT) | \ + (sm0_prim_end_state << CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT) | \ + (sm0_vertex_clip_cnt << CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT) | \ + (sm0_inv_to_clip_data_valid_1 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT) | \ + (sm0_inv_to_clip_data_valid_0 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT) | \ + (sm0_current_state << CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG13_GET_sm0_clip_vert_cnt(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK) >> CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_prim_end_state(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK) >> CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_ALWAYS_ZERO1(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_vertex_clip_cnt(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK) >> CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_inv_to_clip_data_valid_1(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK) >> CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_inv_to_clip_data_valid_0(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK) >> CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_current_state(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_current_state_MASK) >> CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_ALWAYS_ZERO0(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG13_SET_sm0_clip_vert_cnt(clipper_debug_reg13_reg, sm0_clip_vert_cnt) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK) | (sm0_clip_vert_cnt << CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_prim_end_state(clipper_debug_reg13_reg, sm0_prim_end_state) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK) | (sm0_prim_end_state << CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_ALWAYS_ZERO1(clipper_debug_reg13_reg, always_zero1) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_vertex_clip_cnt(clipper_debug_reg13_reg, sm0_vertex_clip_cnt) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK) | (sm0_vertex_clip_cnt << CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_inv_to_clip_data_valid_1(clipper_debug_reg13_reg, sm0_inv_to_clip_data_valid_1) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK) | (sm0_inv_to_clip_data_valid_1 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_inv_to_clip_data_valid_0(clipper_debug_reg13_reg, sm0_inv_to_clip_data_valid_0) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK) | (sm0_inv_to_clip_data_valid_0 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_current_state(clipper_debug_reg13_reg, sm0_current_state) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_current_state_MASK) | (sm0_current_state << CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_ALWAYS_ZERO0(clipper_debug_reg13_reg, always_zero0) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg13_t { + unsigned int sm0_clip_vert_cnt : CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE; + unsigned int sm0_prim_end_state : CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE; + unsigned int sm0_vertex_clip_cnt : CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE; + unsigned int sm0_inv_to_clip_data_valid_1 : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE; + unsigned int sm0_inv_to_clip_data_valid_0 : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE; + unsigned int sm0_current_state : CLIPPER_DEBUG_REG13_sm0_current_state_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg13_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg13_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE; + unsigned int sm0_current_state : CLIPPER_DEBUG_REG13_sm0_current_state_SIZE; + unsigned int sm0_inv_to_clip_data_valid_0 : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE; + unsigned int sm0_inv_to_clip_data_valid_1 : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE; + unsigned int sm0_vertex_clip_cnt : CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE; + unsigned int sm0_prim_end_state : CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE; + unsigned int sm0_clip_vert_cnt : CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE; + } clipper_debug_reg13_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg13_t f; +} clipper_debug_reg13_u; + + +/* + * SXIFCCG_DEBUG_REG0 struct + */ + +#define SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE 4 +#define SXIFCCG_DEBUG_REG0_position_address_SIZE 3 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE 3 +#define SXIFCCG_DEBUG_REG0_point_address_SIZE 3 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE 3 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE 1 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE 2 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE 4 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE 7 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE 1 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE 1 + +#define SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT 0 +#define SXIFCCG_DEBUG_REG0_position_address_SHIFT 4 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT 7 +#define SXIFCCG_DEBUG_REG0_point_address_SHIFT 10 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT 13 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT 16 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT 17 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT 19 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT 23 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT 30 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT 31 + +#define SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK 0x0000000f +#define SXIFCCG_DEBUG_REG0_position_address_MASK 0x00000070 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK 0x00000380 +#define SXIFCCG_DEBUG_REG0_point_address_MASK 0x00001c00 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK 0x0000e000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK 0x00010000 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK 0x00060000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK 0x00780000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK 0x3f800000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK 0x40000000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK 0x80000000 + +#define SXIFCCG_DEBUG_REG0_MASK \ + (SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK | \ + SXIFCCG_DEBUG_REG0_position_address_MASK | \ + SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK | \ + SXIFCCG_DEBUG_REG0_point_address_MASK | \ + SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK | \ + SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) + +#define SXIFCCG_DEBUG_REG0(nan_kill_flag, position_address, always_zero2, point_address, always_zero1, sx_pending_rd_state_var_indx, always_zero0, sx_pending_rd_req_mask, sx_pending_rd_pci, sx_pending_rd_aux_inc, sx_pending_rd_aux_sel) \ + ((nan_kill_flag << SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT) | \ + (position_address << SXIFCCG_DEBUG_REG0_position_address_SHIFT) | \ + (always_zero2 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT) | \ + (point_address << SXIFCCG_DEBUG_REG0_point_address_SHIFT) | \ + (always_zero1 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT) | \ + (sx_pending_rd_state_var_indx << SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT) | \ + (always_zero0 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT) | \ + (sx_pending_rd_req_mask << SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT) | \ + (sx_pending_rd_pci << SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT) | \ + (sx_pending_rd_aux_inc << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT) | \ + (sx_pending_rd_aux_sel << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT)) + +#define SXIFCCG_DEBUG_REG0_GET_nan_kill_flag(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK) >> SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_position_address(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_position_address_MASK) >> SXIFCCG_DEBUG_REG0_position_address_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO2(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_point_address(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_point_address_MASK) >> SXIFCCG_DEBUG_REG0_point_address_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO1(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_state_var_indx(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO0(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_req_mask(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_pci(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_aux_inc(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_aux_sel(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT) + +#define SXIFCCG_DEBUG_REG0_SET_nan_kill_flag(sxifccg_debug_reg0_reg, nan_kill_flag) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK) | (nan_kill_flag << SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_position_address(sxifccg_debug_reg0_reg, position_address) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_position_address_MASK) | (position_address << SXIFCCG_DEBUG_REG0_position_address_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO2(sxifccg_debug_reg0_reg, always_zero2) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_point_address(sxifccg_debug_reg0_reg, point_address) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_point_address_MASK) | (point_address << SXIFCCG_DEBUG_REG0_point_address_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO1(sxifccg_debug_reg0_reg, always_zero1) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_state_var_indx(sxifccg_debug_reg0_reg, sx_pending_rd_state_var_indx) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK) | (sx_pending_rd_state_var_indx << SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO0(sxifccg_debug_reg0_reg, always_zero0) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_req_mask(sxifccg_debug_reg0_reg, sx_pending_rd_req_mask) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK) | (sx_pending_rd_req_mask << SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_pci(sxifccg_debug_reg0_reg, sx_pending_rd_pci) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK) | (sx_pending_rd_pci << SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_aux_inc(sxifccg_debug_reg0_reg, sx_pending_rd_aux_inc) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK) | (sx_pending_rd_aux_inc << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_aux_sel(sxifccg_debug_reg0_reg, sx_pending_rd_aux_sel) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) | (sx_pending_rd_aux_sel << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg0_t { + unsigned int nan_kill_flag : SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE; + unsigned int position_address : SXIFCCG_DEBUG_REG0_position_address_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE; + unsigned int point_address : SXIFCCG_DEBUG_REG0_point_address_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE; + unsigned int sx_pending_rd_state_var_indx : SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE; + unsigned int sx_pending_rd_req_mask : SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE; + unsigned int sx_pending_rd_pci : SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE; + unsigned int sx_pending_rd_aux_inc : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE; + unsigned int sx_pending_rd_aux_sel : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE; + } sxifccg_debug_reg0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg0_t { + unsigned int sx_pending_rd_aux_sel : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE; + unsigned int sx_pending_rd_aux_inc : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE; + unsigned int sx_pending_rd_pci : SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE; + unsigned int sx_pending_rd_req_mask : SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE; + unsigned int sx_pending_rd_state_var_indx : SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE; + unsigned int point_address : SXIFCCG_DEBUG_REG0_point_address_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE; + unsigned int position_address : SXIFCCG_DEBUG_REG0_position_address_SIZE; + unsigned int nan_kill_flag : SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE; + } sxifccg_debug_reg0_t; + +#endif + +typedef union { + unsigned int val : 32; + sxifccg_debug_reg0_t f; +} sxifccg_debug_reg0_u; + + +/* + * SXIFCCG_DEBUG_REG1 struct + */ + +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE 2 +#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE 2 +#define SXIFCCG_DEBUG_REG1_available_positions_SIZE 3 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE 4 +#define SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE 1 +#define SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE 3 +#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE 1 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE 4 +#define SXIFCCG_DEBUG_REG1_aux_sel_SIZE 1 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE 2 +#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE 2 +#define SXIFCCG_DEBUG_REG1_param_cache_base_SIZE 7 + +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT 0 +#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT 2 +#define SXIFCCG_DEBUG_REG1_available_positions_SHIFT 4 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT 7 +#define SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT 11 +#define SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT 12 +#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT 15 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT 16 +#define SXIFCCG_DEBUG_REG1_aux_sel_SHIFT 20 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT 21 +#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT 23 +#define SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT 25 + +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK 0x00000003 +#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK 0x0000000c +#define SXIFCCG_DEBUG_REG1_available_positions_MASK 0x00000070 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK 0x00000780 +#define SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK 0x00000800 +#define SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK 0x00007000 +#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK 0x00008000 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK 0x000f0000 +#define SXIFCCG_DEBUG_REG1_aux_sel_MASK 0x00100000 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK 0x00600000 +#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK 0x01800000 +#define SXIFCCG_DEBUG_REG1_param_cache_base_MASK 0xfe000000 + +#define SXIFCCG_DEBUG_REG1_MASK \ + (SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK | \ + SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK | \ + SXIFCCG_DEBUG_REG1_available_positions_MASK | \ + SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK | \ + SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK | \ + SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK | \ + SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK | \ + SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK | \ + SXIFCCG_DEBUG_REG1_aux_sel_MASK | \ + SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK | \ + SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK | \ + SXIFCCG_DEBUG_REG1_param_cache_base_MASK) + +#define SXIFCCG_DEBUG_REG1(always_zero3, sx_to_pa_empty, available_positions, always_zero2, sx_pending_advance, sx_receive_indx, statevar_bits_sxpa_aux_vector, always_zero1, aux_sel, always_zero0, pasx_req_cnt, param_cache_base) \ + ((always_zero3 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT) | \ + (sx_to_pa_empty << SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT) | \ + (available_positions << SXIFCCG_DEBUG_REG1_available_positions_SHIFT) | \ + (always_zero2 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT) | \ + (sx_pending_advance << SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT) | \ + (sx_receive_indx << SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT) | \ + (statevar_bits_sxpa_aux_vector << SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT) | \ + (always_zero1 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT) | \ + (aux_sel << SXIFCCG_DEBUG_REG1_aux_sel_SHIFT) | \ + (always_zero0 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT) | \ + (pasx_req_cnt << SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT) | \ + (param_cache_base << SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT)) + +#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO3(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_sx_to_pa_empty(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK) >> SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_available_positions(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_available_positions_MASK) >> SXIFCCG_DEBUG_REG1_available_positions_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO2(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_sx_pending_advance(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK) >> SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_sx_receive_indx(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK) >> SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_statevar_bits_sxpa_aux_vector(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK) >> SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO1(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_aux_sel(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_aux_sel_MASK) >> SXIFCCG_DEBUG_REG1_aux_sel_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO0(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_pasx_req_cnt(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK) >> SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_param_cache_base(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_param_cache_base_MASK) >> SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT) + +#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO3(sxifccg_debug_reg1_reg, always_zero3) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_sx_to_pa_empty(sxifccg_debug_reg1_reg, sx_to_pa_empty) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK) | (sx_to_pa_empty << SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_available_positions(sxifccg_debug_reg1_reg, available_positions) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_available_positions_MASK) | (available_positions << SXIFCCG_DEBUG_REG1_available_positions_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO2(sxifccg_debug_reg1_reg, always_zero2) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_sx_pending_advance(sxifccg_debug_reg1_reg, sx_pending_advance) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK) | (sx_pending_advance << SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_sx_receive_indx(sxifccg_debug_reg1_reg, sx_receive_indx) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK) | (sx_receive_indx << SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_statevar_bits_sxpa_aux_vector(sxifccg_debug_reg1_reg, statevar_bits_sxpa_aux_vector) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK) | (statevar_bits_sxpa_aux_vector << SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO1(sxifccg_debug_reg1_reg, always_zero1) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_aux_sel(sxifccg_debug_reg1_reg, aux_sel) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_aux_sel_MASK) | (aux_sel << SXIFCCG_DEBUG_REG1_aux_sel_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO0(sxifccg_debug_reg1_reg, always_zero0) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_pasx_req_cnt(sxifccg_debug_reg1_reg, pasx_req_cnt) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK) | (pasx_req_cnt << SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_param_cache_base(sxifccg_debug_reg1_reg, param_cache_base) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_param_cache_base_MASK) | (param_cache_base << SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg1_t { + unsigned int always_zero3 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE; + unsigned int sx_to_pa_empty : SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE; + unsigned int available_positions : SXIFCCG_DEBUG_REG1_available_positions_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE; + unsigned int sx_pending_advance : SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE; + unsigned int sx_receive_indx : SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE; + unsigned int statevar_bits_sxpa_aux_vector : SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE; + unsigned int aux_sel : SXIFCCG_DEBUG_REG1_aux_sel_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE; + unsigned int pasx_req_cnt : SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE; + unsigned int param_cache_base : SXIFCCG_DEBUG_REG1_param_cache_base_SIZE; + } sxifccg_debug_reg1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg1_t { + unsigned int param_cache_base : SXIFCCG_DEBUG_REG1_param_cache_base_SIZE; + unsigned int pasx_req_cnt : SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE; + unsigned int aux_sel : SXIFCCG_DEBUG_REG1_aux_sel_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE; + unsigned int statevar_bits_sxpa_aux_vector : SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE; + unsigned int sx_receive_indx : SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE; + unsigned int sx_pending_advance : SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE; + unsigned int available_positions : SXIFCCG_DEBUG_REG1_available_positions_SIZE; + unsigned int sx_to_pa_empty : SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE; + } sxifccg_debug_reg1_t; + +#endif + +typedef union { + unsigned int val : 32; + sxifccg_debug_reg1_t f; +} sxifccg_debug_reg1_u; + + +/* + * SXIFCCG_DEBUG_REG2 struct + */ + +#define SXIFCCG_DEBUG_REG2_sx_sent_SIZE 1 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_aux_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE 6 +#define SXIFCCG_DEBUG_REG2_req_active_verts_SIZE 7 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE 1 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE 1 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE 2 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE 2 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE 4 +#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE 3 + +#define SXIFCCG_DEBUG_REG2_sx_sent_SHIFT 0 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT 1 +#define SXIFCCG_DEBUG_REG2_sx_aux_SHIFT 2 +#define SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT 3 +#define SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT 9 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT 16 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT 17 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT 18 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT 20 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT 22 +#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT 26 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT 27 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT 28 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT 29 + +#define SXIFCCG_DEBUG_REG2_sx_sent_MASK 0x00000001 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK 0x00000002 +#define SXIFCCG_DEBUG_REG2_sx_aux_MASK 0x00000004 +#define SXIFCCG_DEBUG_REG2_sx_request_indx_MASK 0x000001f8 +#define SXIFCCG_DEBUG_REG2_req_active_verts_MASK 0x0000fe00 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK 0x00010000 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK 0x00020000 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK 0x000c0000 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK 0x00300000 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK 0x03c00000 +#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK 0x04000000 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK 0x08000000 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK 0x10000000 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK 0xe0000000 + +#define SXIFCCG_DEBUG_REG2_MASK \ + (SXIFCCG_DEBUG_REG2_sx_sent_MASK | \ + SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK | \ + SXIFCCG_DEBUG_REG2_sx_aux_MASK | \ + SXIFCCG_DEBUG_REG2_sx_request_indx_MASK | \ + SXIFCCG_DEBUG_REG2_req_active_verts_MASK | \ + SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK | \ + SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK | \ + SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK | \ + SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK | \ + SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK | \ + SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK | \ + SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK | \ + SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK | \ + SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) + +#define SXIFCCG_DEBUG_REG2(sx_sent, always_zero3, sx_aux, sx_request_indx, req_active_verts, always_zero2, vgt_to_ccgen_state_var_indx, always_zero1, vgt_to_ccgen_active_verts, always_zero0, req_active_verts_loaded, sx_pending_fifo_empty, sx_pending_fifo_full, sx_pending_fifo_contents) \ + ((sx_sent << SXIFCCG_DEBUG_REG2_sx_sent_SHIFT) | \ + (always_zero3 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT) | \ + (sx_aux << SXIFCCG_DEBUG_REG2_sx_aux_SHIFT) | \ + (sx_request_indx << SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT) | \ + (req_active_verts << SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT) | \ + (always_zero2 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT) | \ + (vgt_to_ccgen_state_var_indx << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT) | \ + (always_zero1 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT) | \ + (vgt_to_ccgen_active_verts << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT) | \ + (always_zero0 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT) | \ + (req_active_verts_loaded << SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT) | \ + (sx_pending_fifo_empty << SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT) | \ + (sx_pending_fifo_full << SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT) | \ + (sx_pending_fifo_contents << SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT)) + +#define SXIFCCG_DEBUG_REG2_GET_sx_sent(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_sent_MASK) >> SXIFCCG_DEBUG_REG2_sx_sent_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO3(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_aux(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_aux_MASK) >> SXIFCCG_DEBUG_REG2_sx_aux_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_request_indx(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_request_indx_MASK) >> SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_req_active_verts(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_req_active_verts_MASK) >> SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO2(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_vgt_to_ccgen_state_var_indx(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK) >> SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO1(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_vgt_to_ccgen_active_verts(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK) >> SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO0(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_req_active_verts_loaded(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK) >> SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_empty(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_full(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_contents(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT) + +#define SXIFCCG_DEBUG_REG2_SET_sx_sent(sxifccg_debug_reg2_reg, sx_sent) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_sent_MASK) | (sx_sent << SXIFCCG_DEBUG_REG2_sx_sent_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO3(sxifccg_debug_reg2_reg, always_zero3) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_aux(sxifccg_debug_reg2_reg, sx_aux) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_aux_MASK) | (sx_aux << SXIFCCG_DEBUG_REG2_sx_aux_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_request_indx(sxifccg_debug_reg2_reg, sx_request_indx) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_request_indx_MASK) | (sx_request_indx << SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_req_active_verts(sxifccg_debug_reg2_reg, req_active_verts) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_req_active_verts_MASK) | (req_active_verts << SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO2(sxifccg_debug_reg2_reg, always_zero2) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_vgt_to_ccgen_state_var_indx(sxifccg_debug_reg2_reg, vgt_to_ccgen_state_var_indx) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK) | (vgt_to_ccgen_state_var_indx << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO1(sxifccg_debug_reg2_reg, always_zero1) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_vgt_to_ccgen_active_verts(sxifccg_debug_reg2_reg, vgt_to_ccgen_active_verts) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK) | (vgt_to_ccgen_active_verts << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO0(sxifccg_debug_reg2_reg, always_zero0) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_req_active_verts_loaded(sxifccg_debug_reg2_reg, req_active_verts_loaded) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK) | (req_active_verts_loaded << SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_empty(sxifccg_debug_reg2_reg, sx_pending_fifo_empty) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK) | (sx_pending_fifo_empty << SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_full(sxifccg_debug_reg2_reg, sx_pending_fifo_full) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK) | (sx_pending_fifo_full << SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_contents(sxifccg_debug_reg2_reg, sx_pending_fifo_contents) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) | (sx_pending_fifo_contents << SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg2_t { + unsigned int sx_sent : SXIFCCG_DEBUG_REG2_sx_sent_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE; + unsigned int sx_aux : SXIFCCG_DEBUG_REG2_sx_aux_SIZE; + unsigned int sx_request_indx : SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE; + unsigned int req_active_verts : SXIFCCG_DEBUG_REG2_req_active_verts_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE; + unsigned int vgt_to_ccgen_state_var_indx : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE; + unsigned int vgt_to_ccgen_active_verts : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE; + unsigned int req_active_verts_loaded : SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE; + unsigned int sx_pending_fifo_empty : SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE; + unsigned int sx_pending_fifo_full : SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE; + unsigned int sx_pending_fifo_contents : SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE; + } sxifccg_debug_reg2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg2_t { + unsigned int sx_pending_fifo_contents : SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE; + unsigned int sx_pending_fifo_full : SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE; + unsigned int sx_pending_fifo_empty : SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE; + unsigned int req_active_verts_loaded : SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE; + unsigned int vgt_to_ccgen_active_verts : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE; + unsigned int vgt_to_ccgen_state_var_indx : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE; + unsigned int req_active_verts : SXIFCCG_DEBUG_REG2_req_active_verts_SIZE; + unsigned int sx_request_indx : SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE; + unsigned int sx_aux : SXIFCCG_DEBUG_REG2_sx_aux_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE; + unsigned int sx_sent : SXIFCCG_DEBUG_REG2_sx_sent_SIZE; + } sxifccg_debug_reg2_t; + +#endif + +typedef union { + unsigned int val : 32; + sxifccg_debug_reg2_t f; +} sxifccg_debug_reg2_u; + + +/* + * SXIFCCG_DEBUG_REG3 struct + */ + +#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE 4 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE 1 +#define SXIFCCG_DEBUG_REG3_available_positions_SIZE 3 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE 4 +#define SXIFCCG_DEBUG_REG3_current_state_SIZE 2 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE 1 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE 1 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE 2 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE 1 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE 1 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE 1 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE 1 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE 10 + +#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT 0 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT 4 +#define SXIFCCG_DEBUG_REG3_available_positions_SHIFT 5 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT 8 +#define SXIFCCG_DEBUG_REG3_current_state_SHIFT 12 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT 14 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT 15 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT 16 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT 18 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT 19 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT 20 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT 21 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT 22 + +#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK 0x0000000f +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK 0x00000010 +#define SXIFCCG_DEBUG_REG3_available_positions_MASK 0x000000e0 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK 0x00000f00 +#define SXIFCCG_DEBUG_REG3_current_state_MASK 0x00003000 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK 0x00004000 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK 0x00008000 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK 0x00030000 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK 0x00040000 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK 0x00080000 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK 0x00100000 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK 0x00200000 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK 0xffc00000 + +#define SXIFCCG_DEBUG_REG3_MASK \ + (SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK | \ + SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK | \ + SXIFCCG_DEBUG_REG3_available_positions_MASK | \ + SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK | \ + SXIFCCG_DEBUG_REG3_current_state_MASK | \ + SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK | \ + SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK | \ + SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK | \ + SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK | \ + SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK | \ + SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK | \ + SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK | \ + SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) + +#define SXIFCCG_DEBUG_REG3(vertex_fifo_entriesavailable, always_zero3, available_positions, always_zero2, current_state, vertex_fifo_empty, vertex_fifo_full, always_zero1, sx0_receive_fifo_empty, sx0_receive_fifo_full, vgt_to_ccgen_fifo_empty, vgt_to_ccgen_fifo_full, always_zero0) \ + ((vertex_fifo_entriesavailable << SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT) | \ + (always_zero3 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT) | \ + (available_positions << SXIFCCG_DEBUG_REG3_available_positions_SHIFT) | \ + (always_zero2 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT) | \ + (current_state << SXIFCCG_DEBUG_REG3_current_state_SHIFT) | \ + (vertex_fifo_empty << SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT) | \ + (vertex_fifo_full << SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT) | \ + (always_zero1 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT) | \ + (sx0_receive_fifo_empty << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT) | \ + (sx0_receive_fifo_full << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT) | \ + (vgt_to_ccgen_fifo_empty << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT) | \ + (vgt_to_ccgen_fifo_full << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT) | \ + (always_zero0 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT)) + +#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_entriesavailable(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO3(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_available_positions(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_available_positions_MASK) >> SXIFCCG_DEBUG_REG3_available_positions_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO2(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_current_state(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_current_state_MASK) >> SXIFCCG_DEBUG_REG3_current_state_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_empty(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_full(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO1(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_sx0_receive_fifo_empty(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_sx0_receive_fifo_full(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_vgt_to_ccgen_fifo_empty(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_vgt_to_ccgen_fifo_full(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO0(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT) + +#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_entriesavailable(sxifccg_debug_reg3_reg, vertex_fifo_entriesavailable) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK) | (vertex_fifo_entriesavailable << SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO3(sxifccg_debug_reg3_reg, always_zero3) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_available_positions(sxifccg_debug_reg3_reg, available_positions) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_available_positions_MASK) | (available_positions << SXIFCCG_DEBUG_REG3_available_positions_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO2(sxifccg_debug_reg3_reg, always_zero2) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_current_state(sxifccg_debug_reg3_reg, current_state) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_current_state_MASK) | (current_state << SXIFCCG_DEBUG_REG3_current_state_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_empty(sxifccg_debug_reg3_reg, vertex_fifo_empty) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK) | (vertex_fifo_empty << SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_full(sxifccg_debug_reg3_reg, vertex_fifo_full) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK) | (vertex_fifo_full << SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO1(sxifccg_debug_reg3_reg, always_zero1) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_sx0_receive_fifo_empty(sxifccg_debug_reg3_reg, sx0_receive_fifo_empty) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK) | (sx0_receive_fifo_empty << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_sx0_receive_fifo_full(sxifccg_debug_reg3_reg, sx0_receive_fifo_full) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK) | (sx0_receive_fifo_full << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_vgt_to_ccgen_fifo_empty(sxifccg_debug_reg3_reg, vgt_to_ccgen_fifo_empty) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK) | (vgt_to_ccgen_fifo_empty << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_vgt_to_ccgen_fifo_full(sxifccg_debug_reg3_reg, vgt_to_ccgen_fifo_full) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK) | (vgt_to_ccgen_fifo_full << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO0(sxifccg_debug_reg3_reg, always_zero0) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg3_t { + unsigned int vertex_fifo_entriesavailable : SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE; + unsigned int available_positions : SXIFCCG_DEBUG_REG3_available_positions_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE; + unsigned int current_state : SXIFCCG_DEBUG_REG3_current_state_SIZE; + unsigned int vertex_fifo_empty : SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE; + unsigned int vertex_fifo_full : SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE; + unsigned int sx0_receive_fifo_empty : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE; + unsigned int sx0_receive_fifo_full : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE; + unsigned int vgt_to_ccgen_fifo_empty : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE; + unsigned int vgt_to_ccgen_fifo_full : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE; + } sxifccg_debug_reg3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg3_t { + unsigned int always_zero0 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE; + unsigned int vgt_to_ccgen_fifo_full : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE; + unsigned int vgt_to_ccgen_fifo_empty : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE; + unsigned int sx0_receive_fifo_full : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE; + unsigned int sx0_receive_fifo_empty : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE; + unsigned int vertex_fifo_full : SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE; + unsigned int vertex_fifo_empty : SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE; + unsigned int current_state : SXIFCCG_DEBUG_REG3_current_state_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE; + unsigned int available_positions : SXIFCCG_DEBUG_REG3_available_positions_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE; + unsigned int vertex_fifo_entriesavailable : SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE; + } sxifccg_debug_reg3_t; + +#endif + +typedef union { + unsigned int val : 32; + sxifccg_debug_reg3_t f; +} sxifccg_debug_reg3_u; + + +/* + * SETUP_DEBUG_REG0 struct + */ + +#define SETUP_DEBUG_REG0_su_cntl_state_SIZE 5 +#define SETUP_DEBUG_REG0_pmode_state_SIZE 6 +#define SETUP_DEBUG_REG0_ge_stallb_SIZE 1 +#define SETUP_DEBUG_REG0_geom_enable_SIZE 1 +#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE 1 +#define SETUP_DEBUG_REG0_su_clip_rtr_SIZE 1 +#define SETUP_DEBUG_REG0_pfifo_busy_SIZE 1 +#define SETUP_DEBUG_REG0_su_cntl_busy_SIZE 1 +#define SETUP_DEBUG_REG0_geom_busy_SIZE 1 + +#define SETUP_DEBUG_REG0_su_cntl_state_SHIFT 0 +#define SETUP_DEBUG_REG0_pmode_state_SHIFT 5 +#define SETUP_DEBUG_REG0_ge_stallb_SHIFT 11 +#define SETUP_DEBUG_REG0_geom_enable_SHIFT 12 +#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT 13 +#define SETUP_DEBUG_REG0_su_clip_rtr_SHIFT 14 +#define SETUP_DEBUG_REG0_pfifo_busy_SHIFT 15 +#define SETUP_DEBUG_REG0_su_cntl_busy_SHIFT 16 +#define SETUP_DEBUG_REG0_geom_busy_SHIFT 17 + +#define SETUP_DEBUG_REG0_su_cntl_state_MASK 0x0000001f +#define SETUP_DEBUG_REG0_pmode_state_MASK 0x000007e0 +#define SETUP_DEBUG_REG0_ge_stallb_MASK 0x00000800 +#define SETUP_DEBUG_REG0_geom_enable_MASK 0x00001000 +#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK 0x00002000 +#define SETUP_DEBUG_REG0_su_clip_rtr_MASK 0x00004000 +#define SETUP_DEBUG_REG0_pfifo_busy_MASK 0x00008000 +#define SETUP_DEBUG_REG0_su_cntl_busy_MASK 0x00010000 +#define SETUP_DEBUG_REG0_geom_busy_MASK 0x00020000 + +#define SETUP_DEBUG_REG0_MASK \ + (SETUP_DEBUG_REG0_su_cntl_state_MASK | \ + SETUP_DEBUG_REG0_pmode_state_MASK | \ + SETUP_DEBUG_REG0_ge_stallb_MASK | \ + SETUP_DEBUG_REG0_geom_enable_MASK | \ + SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK | \ + SETUP_DEBUG_REG0_su_clip_rtr_MASK | \ + SETUP_DEBUG_REG0_pfifo_busy_MASK | \ + SETUP_DEBUG_REG0_su_cntl_busy_MASK | \ + SETUP_DEBUG_REG0_geom_busy_MASK) + +#define SETUP_DEBUG_REG0(su_cntl_state, pmode_state, ge_stallb, geom_enable, su_clip_baryc_rtr, su_clip_rtr, pfifo_busy, su_cntl_busy, geom_busy) \ + ((su_cntl_state << SETUP_DEBUG_REG0_su_cntl_state_SHIFT) | \ + (pmode_state << SETUP_DEBUG_REG0_pmode_state_SHIFT) | \ + (ge_stallb << SETUP_DEBUG_REG0_ge_stallb_SHIFT) | \ + (geom_enable << SETUP_DEBUG_REG0_geom_enable_SHIFT) | \ + (su_clip_baryc_rtr << SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT) | \ + (su_clip_rtr << SETUP_DEBUG_REG0_su_clip_rtr_SHIFT) | \ + (pfifo_busy << SETUP_DEBUG_REG0_pfifo_busy_SHIFT) | \ + (su_cntl_busy << SETUP_DEBUG_REG0_su_cntl_busy_SHIFT) | \ + (geom_busy << SETUP_DEBUG_REG0_geom_busy_SHIFT)) + +#define SETUP_DEBUG_REG0_GET_su_cntl_state(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_cntl_state_MASK) >> SETUP_DEBUG_REG0_su_cntl_state_SHIFT) +#define SETUP_DEBUG_REG0_GET_pmode_state(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_pmode_state_MASK) >> SETUP_DEBUG_REG0_pmode_state_SHIFT) +#define SETUP_DEBUG_REG0_GET_ge_stallb(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_ge_stallb_MASK) >> SETUP_DEBUG_REG0_ge_stallb_SHIFT) +#define SETUP_DEBUG_REG0_GET_geom_enable(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_geom_enable_MASK) >> SETUP_DEBUG_REG0_geom_enable_SHIFT) +#define SETUP_DEBUG_REG0_GET_su_clip_baryc_rtr(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK) >> SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT) +#define SETUP_DEBUG_REG0_GET_su_clip_rtr(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_clip_rtr_MASK) >> SETUP_DEBUG_REG0_su_clip_rtr_SHIFT) +#define SETUP_DEBUG_REG0_GET_pfifo_busy(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_pfifo_busy_MASK) >> SETUP_DEBUG_REG0_pfifo_busy_SHIFT) +#define SETUP_DEBUG_REG0_GET_su_cntl_busy(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_cntl_busy_MASK) >> SETUP_DEBUG_REG0_su_cntl_busy_SHIFT) +#define SETUP_DEBUG_REG0_GET_geom_busy(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_geom_busy_MASK) >> SETUP_DEBUG_REG0_geom_busy_SHIFT) + +#define SETUP_DEBUG_REG0_SET_su_cntl_state(setup_debug_reg0_reg, su_cntl_state) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_cntl_state_MASK) | (su_cntl_state << SETUP_DEBUG_REG0_su_cntl_state_SHIFT) +#define SETUP_DEBUG_REG0_SET_pmode_state(setup_debug_reg0_reg, pmode_state) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_pmode_state_MASK) | (pmode_state << SETUP_DEBUG_REG0_pmode_state_SHIFT) +#define SETUP_DEBUG_REG0_SET_ge_stallb(setup_debug_reg0_reg, ge_stallb) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_ge_stallb_MASK) | (ge_stallb << SETUP_DEBUG_REG0_ge_stallb_SHIFT) +#define SETUP_DEBUG_REG0_SET_geom_enable(setup_debug_reg0_reg, geom_enable) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_geom_enable_MASK) | (geom_enable << SETUP_DEBUG_REG0_geom_enable_SHIFT) +#define SETUP_DEBUG_REG0_SET_su_clip_baryc_rtr(setup_debug_reg0_reg, su_clip_baryc_rtr) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK) | (su_clip_baryc_rtr << SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT) +#define SETUP_DEBUG_REG0_SET_su_clip_rtr(setup_debug_reg0_reg, su_clip_rtr) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_clip_rtr_MASK) | (su_clip_rtr << SETUP_DEBUG_REG0_su_clip_rtr_SHIFT) +#define SETUP_DEBUG_REG0_SET_pfifo_busy(setup_debug_reg0_reg, pfifo_busy) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_pfifo_busy_MASK) | (pfifo_busy << SETUP_DEBUG_REG0_pfifo_busy_SHIFT) +#define SETUP_DEBUG_REG0_SET_su_cntl_busy(setup_debug_reg0_reg, su_cntl_busy) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_cntl_busy_MASK) | (su_cntl_busy << SETUP_DEBUG_REG0_su_cntl_busy_SHIFT) +#define SETUP_DEBUG_REG0_SET_geom_busy(setup_debug_reg0_reg, geom_busy) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_geom_busy_MASK) | (geom_busy << SETUP_DEBUG_REG0_geom_busy_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg0_t { + unsigned int su_cntl_state : SETUP_DEBUG_REG0_su_cntl_state_SIZE; + unsigned int pmode_state : SETUP_DEBUG_REG0_pmode_state_SIZE; + unsigned int ge_stallb : SETUP_DEBUG_REG0_ge_stallb_SIZE; + unsigned int geom_enable : SETUP_DEBUG_REG0_geom_enable_SIZE; + unsigned int su_clip_baryc_rtr : SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE; + unsigned int su_clip_rtr : SETUP_DEBUG_REG0_su_clip_rtr_SIZE; + unsigned int pfifo_busy : SETUP_DEBUG_REG0_pfifo_busy_SIZE; + unsigned int su_cntl_busy : SETUP_DEBUG_REG0_su_cntl_busy_SIZE; + unsigned int geom_busy : SETUP_DEBUG_REG0_geom_busy_SIZE; + unsigned int : 14; + } setup_debug_reg0_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg0_t { + unsigned int : 14; + unsigned int geom_busy : SETUP_DEBUG_REG0_geom_busy_SIZE; + unsigned int su_cntl_busy : SETUP_DEBUG_REG0_su_cntl_busy_SIZE; + unsigned int pfifo_busy : SETUP_DEBUG_REG0_pfifo_busy_SIZE; + unsigned int su_clip_rtr : SETUP_DEBUG_REG0_su_clip_rtr_SIZE; + unsigned int su_clip_baryc_rtr : SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE; + unsigned int geom_enable : SETUP_DEBUG_REG0_geom_enable_SIZE; + unsigned int ge_stallb : SETUP_DEBUG_REG0_ge_stallb_SIZE; + unsigned int pmode_state : SETUP_DEBUG_REG0_pmode_state_SIZE; + unsigned int su_cntl_state : SETUP_DEBUG_REG0_su_cntl_state_SIZE; + } setup_debug_reg0_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg0_t f; +} setup_debug_reg0_u; + + +/* + * SETUP_DEBUG_REG1 struct + */ + +#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE 14 +#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE 14 + +#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT 0 +#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT 14 + +#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK 0x00003fff +#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK 0x0fffc000 + +#define SETUP_DEBUG_REG1_MASK \ + (SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK | \ + SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) + +#define SETUP_DEBUG_REG1(y_sort0_gated_17_4, x_sort0_gated_17_4) \ + ((y_sort0_gated_17_4 << SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT) | \ + (x_sort0_gated_17_4 << SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT)) + +#define SETUP_DEBUG_REG1_GET_y_sort0_gated_17_4(setup_debug_reg1) \ + ((setup_debug_reg1 & SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK) >> SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG1_GET_x_sort0_gated_17_4(setup_debug_reg1) \ + ((setup_debug_reg1 & SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) >> SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT) + +#define SETUP_DEBUG_REG1_SET_y_sort0_gated_17_4(setup_debug_reg1_reg, y_sort0_gated_17_4) \ + setup_debug_reg1_reg = (setup_debug_reg1_reg & ~SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK) | (y_sort0_gated_17_4 << SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG1_SET_x_sort0_gated_17_4(setup_debug_reg1_reg, x_sort0_gated_17_4) \ + setup_debug_reg1_reg = (setup_debug_reg1_reg & ~SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) | (x_sort0_gated_17_4 << SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg1_t { + unsigned int y_sort0_gated_17_4 : SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE; + unsigned int x_sort0_gated_17_4 : SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE; + unsigned int : 4; + } setup_debug_reg1_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg1_t { + unsigned int : 4; + unsigned int x_sort0_gated_17_4 : SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE; + unsigned int y_sort0_gated_17_4 : SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE; + } setup_debug_reg1_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg1_t f; +} setup_debug_reg1_u; + + +/* + * SETUP_DEBUG_REG2 struct + */ + +#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE 14 +#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE 14 + +#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT 0 +#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT 14 + +#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK 0x00003fff +#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK 0x0fffc000 + +#define SETUP_DEBUG_REG2_MASK \ + (SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK | \ + SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) + +#define SETUP_DEBUG_REG2(y_sort1_gated_17_4, x_sort1_gated_17_4) \ + ((y_sort1_gated_17_4 << SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT) | \ + (x_sort1_gated_17_4 << SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT)) + +#define SETUP_DEBUG_REG2_GET_y_sort1_gated_17_4(setup_debug_reg2) \ + ((setup_debug_reg2 & SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK) >> SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG2_GET_x_sort1_gated_17_4(setup_debug_reg2) \ + ((setup_debug_reg2 & SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) >> SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT) + +#define SETUP_DEBUG_REG2_SET_y_sort1_gated_17_4(setup_debug_reg2_reg, y_sort1_gated_17_4) \ + setup_debug_reg2_reg = (setup_debug_reg2_reg & ~SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK) | (y_sort1_gated_17_4 << SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG2_SET_x_sort1_gated_17_4(setup_debug_reg2_reg, x_sort1_gated_17_4) \ + setup_debug_reg2_reg = (setup_debug_reg2_reg & ~SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) | (x_sort1_gated_17_4 << SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg2_t { + unsigned int y_sort1_gated_17_4 : SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE; + unsigned int x_sort1_gated_17_4 : SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE; + unsigned int : 4; + } setup_debug_reg2_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg2_t { + unsigned int : 4; + unsigned int x_sort1_gated_17_4 : SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE; + unsigned int y_sort1_gated_17_4 : SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE; + } setup_debug_reg2_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg2_t f; +} setup_debug_reg2_u; + + +/* + * SETUP_DEBUG_REG3 struct + */ + +#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE 14 +#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE 14 + +#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT 0 +#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT 14 + +#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK 0x00003fff +#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK 0x0fffc000 + +#define SETUP_DEBUG_REG3_MASK \ + (SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK | \ + SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) + +#define SETUP_DEBUG_REG3(y_sort2_gated_17_4, x_sort2_gated_17_4) \ + ((y_sort2_gated_17_4 << SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT) | \ + (x_sort2_gated_17_4 << SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT)) + +#define SETUP_DEBUG_REG3_GET_y_sort2_gated_17_4(setup_debug_reg3) \ + ((setup_debug_reg3 & SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK) >> SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG3_GET_x_sort2_gated_17_4(setup_debug_reg3) \ + ((setup_debug_reg3 & SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) >> SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT) + +#define SETUP_DEBUG_REG3_SET_y_sort2_gated_17_4(setup_debug_reg3_reg, y_sort2_gated_17_4) \ + setup_debug_reg3_reg = (setup_debug_reg3_reg & ~SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK) | (y_sort2_gated_17_4 << SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG3_SET_x_sort2_gated_17_4(setup_debug_reg3_reg, x_sort2_gated_17_4) \ + setup_debug_reg3_reg = (setup_debug_reg3_reg & ~SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) | (x_sort2_gated_17_4 << SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg3_t { + unsigned int y_sort2_gated_17_4 : SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE; + unsigned int x_sort2_gated_17_4 : SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE; + unsigned int : 4; + } setup_debug_reg3_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg3_t { + unsigned int : 4; + unsigned int x_sort2_gated_17_4 : SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE; + unsigned int y_sort2_gated_17_4 : SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE; + } setup_debug_reg3_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg3_t f; +} setup_debug_reg3_u; + + +/* + * SETUP_DEBUG_REG4 struct + */ + +#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE 11 +#define SETUP_DEBUG_REG4_null_prim_gated_SIZE 1 +#define SETUP_DEBUG_REG4_backfacing_gated_SIZE 1 +#define SETUP_DEBUG_REG4_st_indx_gated_SIZE 3 +#define SETUP_DEBUG_REG4_clipped_gated_SIZE 1 +#define SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE 3 +#define SETUP_DEBUG_REG4_xmajor_gated_SIZE 1 +#define SETUP_DEBUG_REG4_diamond_rule_gated_SIZE 2 +#define SETUP_DEBUG_REG4_type_gated_SIZE 3 +#define SETUP_DEBUG_REG4_fpov_gated_SIZE 1 +#define SETUP_DEBUG_REG4_pmode_prim_gated_SIZE 1 +#define SETUP_DEBUG_REG4_event_gated_SIZE 1 +#define SETUP_DEBUG_REG4_eop_gated_SIZE 1 + +#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT 0 +#define SETUP_DEBUG_REG4_null_prim_gated_SHIFT 11 +#define SETUP_DEBUG_REG4_backfacing_gated_SHIFT 12 +#define SETUP_DEBUG_REG4_st_indx_gated_SHIFT 13 +#define SETUP_DEBUG_REG4_clipped_gated_SHIFT 16 +#define SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT 17 +#define SETUP_DEBUG_REG4_xmajor_gated_SHIFT 20 +#define SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT 21 +#define SETUP_DEBUG_REG4_type_gated_SHIFT 23 +#define SETUP_DEBUG_REG4_fpov_gated_SHIFT 26 +#define SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT 27 +#define SETUP_DEBUG_REG4_event_gated_SHIFT 28 +#define SETUP_DEBUG_REG4_eop_gated_SHIFT 29 + +#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK 0x000007ff +#define SETUP_DEBUG_REG4_null_prim_gated_MASK 0x00000800 +#define SETUP_DEBUG_REG4_backfacing_gated_MASK 0x00001000 +#define SETUP_DEBUG_REG4_st_indx_gated_MASK 0x0000e000 +#define SETUP_DEBUG_REG4_clipped_gated_MASK 0x00010000 +#define SETUP_DEBUG_REG4_dealloc_slot_gated_MASK 0x000e0000 +#define SETUP_DEBUG_REG4_xmajor_gated_MASK 0x00100000 +#define SETUP_DEBUG_REG4_diamond_rule_gated_MASK 0x00600000 +#define SETUP_DEBUG_REG4_type_gated_MASK 0x03800000 +#define SETUP_DEBUG_REG4_fpov_gated_MASK 0x04000000 +#define SETUP_DEBUG_REG4_pmode_prim_gated_MASK 0x08000000 +#define SETUP_DEBUG_REG4_event_gated_MASK 0x10000000 +#define SETUP_DEBUG_REG4_eop_gated_MASK 0x20000000 + +#define SETUP_DEBUG_REG4_MASK \ + (SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK | \ + SETUP_DEBUG_REG4_null_prim_gated_MASK | \ + SETUP_DEBUG_REG4_backfacing_gated_MASK | \ + SETUP_DEBUG_REG4_st_indx_gated_MASK | \ + SETUP_DEBUG_REG4_clipped_gated_MASK | \ + SETUP_DEBUG_REG4_dealloc_slot_gated_MASK | \ + SETUP_DEBUG_REG4_xmajor_gated_MASK | \ + SETUP_DEBUG_REG4_diamond_rule_gated_MASK | \ + SETUP_DEBUG_REG4_type_gated_MASK | \ + SETUP_DEBUG_REG4_fpov_gated_MASK | \ + SETUP_DEBUG_REG4_pmode_prim_gated_MASK | \ + SETUP_DEBUG_REG4_event_gated_MASK | \ + SETUP_DEBUG_REG4_eop_gated_MASK) + +#define SETUP_DEBUG_REG4(attr_indx_sort0_gated, null_prim_gated, backfacing_gated, st_indx_gated, clipped_gated, dealloc_slot_gated, xmajor_gated, diamond_rule_gated, type_gated, fpov_gated, pmode_prim_gated, event_gated, eop_gated) \ + ((attr_indx_sort0_gated << SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT) | \ + (null_prim_gated << SETUP_DEBUG_REG4_null_prim_gated_SHIFT) | \ + (backfacing_gated << SETUP_DEBUG_REG4_backfacing_gated_SHIFT) | \ + (st_indx_gated << SETUP_DEBUG_REG4_st_indx_gated_SHIFT) | \ + (clipped_gated << SETUP_DEBUG_REG4_clipped_gated_SHIFT) | \ + (dealloc_slot_gated << SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT) | \ + (xmajor_gated << SETUP_DEBUG_REG4_xmajor_gated_SHIFT) | \ + (diamond_rule_gated << SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT) | \ + (type_gated << SETUP_DEBUG_REG4_type_gated_SHIFT) | \ + (fpov_gated << SETUP_DEBUG_REG4_fpov_gated_SHIFT) | \ + (pmode_prim_gated << SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT) | \ + (event_gated << SETUP_DEBUG_REG4_event_gated_SHIFT) | \ + (eop_gated << SETUP_DEBUG_REG4_eop_gated_SHIFT)) + +#define SETUP_DEBUG_REG4_GET_attr_indx_sort0_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK) >> SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_null_prim_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_null_prim_gated_MASK) >> SETUP_DEBUG_REG4_null_prim_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_backfacing_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_backfacing_gated_MASK) >> SETUP_DEBUG_REG4_backfacing_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_st_indx_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_st_indx_gated_MASK) >> SETUP_DEBUG_REG4_st_indx_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_clipped_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_clipped_gated_MASK) >> SETUP_DEBUG_REG4_clipped_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_dealloc_slot_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_dealloc_slot_gated_MASK) >> SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_xmajor_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_xmajor_gated_MASK) >> SETUP_DEBUG_REG4_xmajor_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_diamond_rule_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_diamond_rule_gated_MASK) >> SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_type_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_type_gated_MASK) >> SETUP_DEBUG_REG4_type_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_fpov_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_fpov_gated_MASK) >> SETUP_DEBUG_REG4_fpov_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_pmode_prim_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_pmode_prim_gated_MASK) >> SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_event_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_event_gated_MASK) >> SETUP_DEBUG_REG4_event_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_eop_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_eop_gated_MASK) >> SETUP_DEBUG_REG4_eop_gated_SHIFT) + +#define SETUP_DEBUG_REG4_SET_attr_indx_sort0_gated(setup_debug_reg4_reg, attr_indx_sort0_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK) | (attr_indx_sort0_gated << SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_null_prim_gated(setup_debug_reg4_reg, null_prim_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_null_prim_gated_MASK) | (null_prim_gated << SETUP_DEBUG_REG4_null_prim_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_backfacing_gated(setup_debug_reg4_reg, backfacing_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_backfacing_gated_MASK) | (backfacing_gated << SETUP_DEBUG_REG4_backfacing_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_st_indx_gated(setup_debug_reg4_reg, st_indx_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_st_indx_gated_MASK) | (st_indx_gated << SETUP_DEBUG_REG4_st_indx_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_clipped_gated(setup_debug_reg4_reg, clipped_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_clipped_gated_MASK) | (clipped_gated << SETUP_DEBUG_REG4_clipped_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_dealloc_slot_gated(setup_debug_reg4_reg, dealloc_slot_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_dealloc_slot_gated_MASK) | (dealloc_slot_gated << SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_xmajor_gated(setup_debug_reg4_reg, xmajor_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_xmajor_gated_MASK) | (xmajor_gated << SETUP_DEBUG_REG4_xmajor_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_diamond_rule_gated(setup_debug_reg4_reg, diamond_rule_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_diamond_rule_gated_MASK) | (diamond_rule_gated << SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_type_gated(setup_debug_reg4_reg, type_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_type_gated_MASK) | (type_gated << SETUP_DEBUG_REG4_type_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_fpov_gated(setup_debug_reg4_reg, fpov_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_fpov_gated_MASK) | (fpov_gated << SETUP_DEBUG_REG4_fpov_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_pmode_prim_gated(setup_debug_reg4_reg, pmode_prim_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_pmode_prim_gated_MASK) | (pmode_prim_gated << SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_event_gated(setup_debug_reg4_reg, event_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_event_gated_MASK) | (event_gated << SETUP_DEBUG_REG4_event_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_eop_gated(setup_debug_reg4_reg, eop_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_eop_gated_MASK) | (eop_gated << SETUP_DEBUG_REG4_eop_gated_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg4_t { + unsigned int attr_indx_sort0_gated : SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE; + unsigned int null_prim_gated : SETUP_DEBUG_REG4_null_prim_gated_SIZE; + unsigned int backfacing_gated : SETUP_DEBUG_REG4_backfacing_gated_SIZE; + unsigned int st_indx_gated : SETUP_DEBUG_REG4_st_indx_gated_SIZE; + unsigned int clipped_gated : SETUP_DEBUG_REG4_clipped_gated_SIZE; + unsigned int dealloc_slot_gated : SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE; + unsigned int xmajor_gated : SETUP_DEBUG_REG4_xmajor_gated_SIZE; + unsigned int diamond_rule_gated : SETUP_DEBUG_REG4_diamond_rule_gated_SIZE; + unsigned int type_gated : SETUP_DEBUG_REG4_type_gated_SIZE; + unsigned int fpov_gated : SETUP_DEBUG_REG4_fpov_gated_SIZE; + unsigned int pmode_prim_gated : SETUP_DEBUG_REG4_pmode_prim_gated_SIZE; + unsigned int event_gated : SETUP_DEBUG_REG4_event_gated_SIZE; + unsigned int eop_gated : SETUP_DEBUG_REG4_eop_gated_SIZE; + unsigned int : 2; + } setup_debug_reg4_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg4_t { + unsigned int : 2; + unsigned int eop_gated : SETUP_DEBUG_REG4_eop_gated_SIZE; + unsigned int event_gated : SETUP_DEBUG_REG4_event_gated_SIZE; + unsigned int pmode_prim_gated : SETUP_DEBUG_REG4_pmode_prim_gated_SIZE; + unsigned int fpov_gated : SETUP_DEBUG_REG4_fpov_gated_SIZE; + unsigned int type_gated : SETUP_DEBUG_REG4_type_gated_SIZE; + unsigned int diamond_rule_gated : SETUP_DEBUG_REG4_diamond_rule_gated_SIZE; + unsigned int xmajor_gated : SETUP_DEBUG_REG4_xmajor_gated_SIZE; + unsigned int dealloc_slot_gated : SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE; + unsigned int clipped_gated : SETUP_DEBUG_REG4_clipped_gated_SIZE; + unsigned int st_indx_gated : SETUP_DEBUG_REG4_st_indx_gated_SIZE; + unsigned int backfacing_gated : SETUP_DEBUG_REG4_backfacing_gated_SIZE; + unsigned int null_prim_gated : SETUP_DEBUG_REG4_null_prim_gated_SIZE; + unsigned int attr_indx_sort0_gated : SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE; + } setup_debug_reg4_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg4_t f; +} setup_debug_reg4_u; + + +/* + * SETUP_DEBUG_REG5 struct + */ + +#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE 11 +#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE 11 +#define SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE 2 +#define SETUP_DEBUG_REG5_event_id_gated_SIZE 5 + +#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT 0 +#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT 11 +#define SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT 22 +#define SETUP_DEBUG_REG5_event_id_gated_SHIFT 24 + +#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK 0x000007ff +#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK 0x003ff800 +#define SETUP_DEBUG_REG5_provoking_vtx_gated_MASK 0x00c00000 +#define SETUP_DEBUG_REG5_event_id_gated_MASK 0x1f000000 + +#define SETUP_DEBUG_REG5_MASK \ + (SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK | \ + SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK | \ + SETUP_DEBUG_REG5_provoking_vtx_gated_MASK | \ + SETUP_DEBUG_REG5_event_id_gated_MASK) + +#define SETUP_DEBUG_REG5(attr_indx_sort2_gated, attr_indx_sort1_gated, provoking_vtx_gated, event_id_gated) \ + ((attr_indx_sort2_gated << SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT) | \ + (attr_indx_sort1_gated << SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT) | \ + (provoking_vtx_gated << SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT) | \ + (event_id_gated << SETUP_DEBUG_REG5_event_id_gated_SHIFT)) + +#define SETUP_DEBUG_REG5_GET_attr_indx_sort2_gated(setup_debug_reg5) \ + ((setup_debug_reg5 & SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK) >> SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT) +#define SETUP_DEBUG_REG5_GET_attr_indx_sort1_gated(setup_debug_reg5) \ + ((setup_debug_reg5 & SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK) >> SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT) +#define SETUP_DEBUG_REG5_GET_provoking_vtx_gated(setup_debug_reg5) \ + ((setup_debug_reg5 & SETUP_DEBUG_REG5_provoking_vtx_gated_MASK) >> SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT) +#define SETUP_DEBUG_REG5_GET_event_id_gated(setup_debug_reg5) \ + ((setup_debug_reg5 & SETUP_DEBUG_REG5_event_id_gated_MASK) >> SETUP_DEBUG_REG5_event_id_gated_SHIFT) + +#define SETUP_DEBUG_REG5_SET_attr_indx_sort2_gated(setup_debug_reg5_reg, attr_indx_sort2_gated) \ + setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK) | (attr_indx_sort2_gated << SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT) +#define SETUP_DEBUG_REG5_SET_attr_indx_sort1_gated(setup_debug_reg5_reg, attr_indx_sort1_gated) \ + setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK) | (attr_indx_sort1_gated << SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT) +#define SETUP_DEBUG_REG5_SET_provoking_vtx_gated(setup_debug_reg5_reg, provoking_vtx_gated) \ + setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_provoking_vtx_gated_MASK) | (provoking_vtx_gated << SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT) +#define SETUP_DEBUG_REG5_SET_event_id_gated(setup_debug_reg5_reg, event_id_gated) \ + setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_event_id_gated_MASK) | (event_id_gated << SETUP_DEBUG_REG5_event_id_gated_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg5_t { + unsigned int attr_indx_sort2_gated : SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE; + unsigned int attr_indx_sort1_gated : SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE; + unsigned int provoking_vtx_gated : SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE; + unsigned int event_id_gated : SETUP_DEBUG_REG5_event_id_gated_SIZE; + unsigned int : 3; + } setup_debug_reg5_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg5_t { + unsigned int : 3; + unsigned int event_id_gated : SETUP_DEBUG_REG5_event_id_gated_SIZE; + unsigned int provoking_vtx_gated : SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE; + unsigned int attr_indx_sort1_gated : SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE; + unsigned int attr_indx_sort2_gated : SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE; + } setup_debug_reg5_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg5_t f; +} setup_debug_reg5_u; + + +/* + * PA_SC_DEBUG_CNTL struct + */ + +#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE 5 + +#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT 0 + +#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK 0x0000001f + +#define PA_SC_DEBUG_CNTL_MASK \ + (PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) + +#define PA_SC_DEBUG_CNTL(sc_debug_indx) \ + ((sc_debug_indx << PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT)) + +#define PA_SC_DEBUG_CNTL_GET_SC_DEBUG_INDX(pa_sc_debug_cntl) \ + ((pa_sc_debug_cntl & PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) >> PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT) + +#define PA_SC_DEBUG_CNTL_SET_SC_DEBUG_INDX(pa_sc_debug_cntl_reg, sc_debug_indx) \ + pa_sc_debug_cntl_reg = (pa_sc_debug_cntl_reg & ~PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) | (sc_debug_indx << PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_debug_cntl_t { + unsigned int sc_debug_indx : PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE; + unsigned int : 27; + } pa_sc_debug_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_debug_cntl_t { + unsigned int : 27; + unsigned int sc_debug_indx : PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE; + } pa_sc_debug_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_debug_cntl_t f; +} pa_sc_debug_cntl_u; + + +/* + * PA_SC_DEBUG_DATA struct + */ + +#define PA_SC_DEBUG_DATA_DATA_SIZE 32 + +#define PA_SC_DEBUG_DATA_DATA_SHIFT 0 + +#define PA_SC_DEBUG_DATA_DATA_MASK 0xffffffff + +#define PA_SC_DEBUG_DATA_MASK \ + (PA_SC_DEBUG_DATA_DATA_MASK) + +#define PA_SC_DEBUG_DATA(data) \ + ((data << PA_SC_DEBUG_DATA_DATA_SHIFT)) + +#define PA_SC_DEBUG_DATA_GET_DATA(pa_sc_debug_data) \ + ((pa_sc_debug_data & PA_SC_DEBUG_DATA_DATA_MASK) >> PA_SC_DEBUG_DATA_DATA_SHIFT) + +#define PA_SC_DEBUG_DATA_SET_DATA(pa_sc_debug_data_reg, data) \ + pa_sc_debug_data_reg = (pa_sc_debug_data_reg & ~PA_SC_DEBUG_DATA_DATA_MASK) | (data << PA_SC_DEBUG_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_debug_data_t { + unsigned int data : PA_SC_DEBUG_DATA_DATA_SIZE; + } pa_sc_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_debug_data_t { + unsigned int data : PA_SC_DEBUG_DATA_DATA_SIZE; + } pa_sc_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_debug_data_t f; +} pa_sc_debug_data_u; + + +/* + * SC_DEBUG_0 struct + */ + +#define SC_DEBUG_0_pa_freeze_b1_SIZE 1 +#define SC_DEBUG_0_pa_sc_valid_SIZE 1 +#define SC_DEBUG_0_pa_sc_phase_SIZE 3 +#define SC_DEBUG_0_cntx_cnt_SIZE 7 +#define SC_DEBUG_0_decr_cntx_cnt_SIZE 1 +#define SC_DEBUG_0_incr_cntx_cnt_SIZE 1 +#define SC_DEBUG_0_trigger_SIZE 1 + +#define SC_DEBUG_0_pa_freeze_b1_SHIFT 0 +#define SC_DEBUG_0_pa_sc_valid_SHIFT 1 +#define SC_DEBUG_0_pa_sc_phase_SHIFT 2 +#define SC_DEBUG_0_cntx_cnt_SHIFT 5 +#define SC_DEBUG_0_decr_cntx_cnt_SHIFT 12 +#define SC_DEBUG_0_incr_cntx_cnt_SHIFT 13 +#define SC_DEBUG_0_trigger_SHIFT 31 + +#define SC_DEBUG_0_pa_freeze_b1_MASK 0x00000001 +#define SC_DEBUG_0_pa_sc_valid_MASK 0x00000002 +#define SC_DEBUG_0_pa_sc_phase_MASK 0x0000001c +#define SC_DEBUG_0_cntx_cnt_MASK 0x00000fe0 +#define SC_DEBUG_0_decr_cntx_cnt_MASK 0x00001000 +#define SC_DEBUG_0_incr_cntx_cnt_MASK 0x00002000 +#define SC_DEBUG_0_trigger_MASK 0x80000000 + +#define SC_DEBUG_0_MASK \ + (SC_DEBUG_0_pa_freeze_b1_MASK | \ + SC_DEBUG_0_pa_sc_valid_MASK | \ + SC_DEBUG_0_pa_sc_phase_MASK | \ + SC_DEBUG_0_cntx_cnt_MASK | \ + SC_DEBUG_0_decr_cntx_cnt_MASK | \ + SC_DEBUG_0_incr_cntx_cnt_MASK | \ + SC_DEBUG_0_trigger_MASK) + +#define SC_DEBUG_0(pa_freeze_b1, pa_sc_valid, pa_sc_phase, cntx_cnt, decr_cntx_cnt, incr_cntx_cnt, trigger) \ + ((pa_freeze_b1 << SC_DEBUG_0_pa_freeze_b1_SHIFT) | \ + (pa_sc_valid << SC_DEBUG_0_pa_sc_valid_SHIFT) | \ + (pa_sc_phase << SC_DEBUG_0_pa_sc_phase_SHIFT) | \ + (cntx_cnt << SC_DEBUG_0_cntx_cnt_SHIFT) | \ + (decr_cntx_cnt << SC_DEBUG_0_decr_cntx_cnt_SHIFT) | \ + (incr_cntx_cnt << SC_DEBUG_0_incr_cntx_cnt_SHIFT) | \ + (trigger << SC_DEBUG_0_trigger_SHIFT)) + +#define SC_DEBUG_0_GET_pa_freeze_b1(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_pa_freeze_b1_MASK) >> SC_DEBUG_0_pa_freeze_b1_SHIFT) +#define SC_DEBUG_0_GET_pa_sc_valid(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_pa_sc_valid_MASK) >> SC_DEBUG_0_pa_sc_valid_SHIFT) +#define SC_DEBUG_0_GET_pa_sc_phase(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_pa_sc_phase_MASK) >> SC_DEBUG_0_pa_sc_phase_SHIFT) +#define SC_DEBUG_0_GET_cntx_cnt(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_cntx_cnt_MASK) >> SC_DEBUG_0_cntx_cnt_SHIFT) +#define SC_DEBUG_0_GET_decr_cntx_cnt(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_decr_cntx_cnt_MASK) >> SC_DEBUG_0_decr_cntx_cnt_SHIFT) +#define SC_DEBUG_0_GET_incr_cntx_cnt(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_incr_cntx_cnt_MASK) >> SC_DEBUG_0_incr_cntx_cnt_SHIFT) +#define SC_DEBUG_0_GET_trigger(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_trigger_MASK) >> SC_DEBUG_0_trigger_SHIFT) + +#define SC_DEBUG_0_SET_pa_freeze_b1(sc_debug_0_reg, pa_freeze_b1) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_freeze_b1_MASK) | (pa_freeze_b1 << SC_DEBUG_0_pa_freeze_b1_SHIFT) +#define SC_DEBUG_0_SET_pa_sc_valid(sc_debug_0_reg, pa_sc_valid) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_sc_valid_MASK) | (pa_sc_valid << SC_DEBUG_0_pa_sc_valid_SHIFT) +#define SC_DEBUG_0_SET_pa_sc_phase(sc_debug_0_reg, pa_sc_phase) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_sc_phase_MASK) | (pa_sc_phase << SC_DEBUG_0_pa_sc_phase_SHIFT) +#define SC_DEBUG_0_SET_cntx_cnt(sc_debug_0_reg, cntx_cnt) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_cntx_cnt_MASK) | (cntx_cnt << SC_DEBUG_0_cntx_cnt_SHIFT) +#define SC_DEBUG_0_SET_decr_cntx_cnt(sc_debug_0_reg, decr_cntx_cnt) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_decr_cntx_cnt_MASK) | (decr_cntx_cnt << SC_DEBUG_0_decr_cntx_cnt_SHIFT) +#define SC_DEBUG_0_SET_incr_cntx_cnt(sc_debug_0_reg, incr_cntx_cnt) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_incr_cntx_cnt_MASK) | (incr_cntx_cnt << SC_DEBUG_0_incr_cntx_cnt_SHIFT) +#define SC_DEBUG_0_SET_trigger(sc_debug_0_reg, trigger) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_trigger_MASK) | (trigger << SC_DEBUG_0_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_0_t { + unsigned int pa_freeze_b1 : SC_DEBUG_0_pa_freeze_b1_SIZE; + unsigned int pa_sc_valid : SC_DEBUG_0_pa_sc_valid_SIZE; + unsigned int pa_sc_phase : SC_DEBUG_0_pa_sc_phase_SIZE; + unsigned int cntx_cnt : SC_DEBUG_0_cntx_cnt_SIZE; + unsigned int decr_cntx_cnt : SC_DEBUG_0_decr_cntx_cnt_SIZE; + unsigned int incr_cntx_cnt : SC_DEBUG_0_incr_cntx_cnt_SIZE; + unsigned int : 17; + unsigned int trigger : SC_DEBUG_0_trigger_SIZE; + } sc_debug_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_0_t { + unsigned int trigger : SC_DEBUG_0_trigger_SIZE; + unsigned int : 17; + unsigned int incr_cntx_cnt : SC_DEBUG_0_incr_cntx_cnt_SIZE; + unsigned int decr_cntx_cnt : SC_DEBUG_0_decr_cntx_cnt_SIZE; + unsigned int cntx_cnt : SC_DEBUG_0_cntx_cnt_SIZE; + unsigned int pa_sc_phase : SC_DEBUG_0_pa_sc_phase_SIZE; + unsigned int pa_sc_valid : SC_DEBUG_0_pa_sc_valid_SIZE; + unsigned int pa_freeze_b1 : SC_DEBUG_0_pa_freeze_b1_SIZE; + } sc_debug_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_0_t f; +} sc_debug_0_u; + + +/* + * SC_DEBUG_1 struct + */ + +#define SC_DEBUG_1_em_state_SIZE 3 +#define SC_DEBUG_1_em1_data_ready_SIZE 1 +#define SC_DEBUG_1_em2_data_ready_SIZE 1 +#define SC_DEBUG_1_move_em1_to_em2_SIZE 1 +#define SC_DEBUG_1_ef_data_ready_SIZE 1 +#define SC_DEBUG_1_ef_state_SIZE 2 +#define SC_DEBUG_1_pipe_valid_SIZE 1 +#define SC_DEBUG_1_trigger_SIZE 1 + +#define SC_DEBUG_1_em_state_SHIFT 0 +#define SC_DEBUG_1_em1_data_ready_SHIFT 3 +#define SC_DEBUG_1_em2_data_ready_SHIFT 4 +#define SC_DEBUG_1_move_em1_to_em2_SHIFT 5 +#define SC_DEBUG_1_ef_data_ready_SHIFT 6 +#define SC_DEBUG_1_ef_state_SHIFT 7 +#define SC_DEBUG_1_pipe_valid_SHIFT 9 +#define SC_DEBUG_1_trigger_SHIFT 31 + +#define SC_DEBUG_1_em_state_MASK 0x00000007 +#define SC_DEBUG_1_em1_data_ready_MASK 0x00000008 +#define SC_DEBUG_1_em2_data_ready_MASK 0x00000010 +#define SC_DEBUG_1_move_em1_to_em2_MASK 0x00000020 +#define SC_DEBUG_1_ef_data_ready_MASK 0x00000040 +#define SC_DEBUG_1_ef_state_MASK 0x00000180 +#define SC_DEBUG_1_pipe_valid_MASK 0x00000200 +#define SC_DEBUG_1_trigger_MASK 0x80000000 + +#define SC_DEBUG_1_MASK \ + (SC_DEBUG_1_em_state_MASK | \ + SC_DEBUG_1_em1_data_ready_MASK | \ + SC_DEBUG_1_em2_data_ready_MASK | \ + SC_DEBUG_1_move_em1_to_em2_MASK | \ + SC_DEBUG_1_ef_data_ready_MASK | \ + SC_DEBUG_1_ef_state_MASK | \ + SC_DEBUG_1_pipe_valid_MASK | \ + SC_DEBUG_1_trigger_MASK) + +#define SC_DEBUG_1(em_state, em1_data_ready, em2_data_ready, move_em1_to_em2, ef_data_ready, ef_state, pipe_valid, trigger) \ + ((em_state << SC_DEBUG_1_em_state_SHIFT) | \ + (em1_data_ready << SC_DEBUG_1_em1_data_ready_SHIFT) | \ + (em2_data_ready << SC_DEBUG_1_em2_data_ready_SHIFT) | \ + (move_em1_to_em2 << SC_DEBUG_1_move_em1_to_em2_SHIFT) | \ + (ef_data_ready << SC_DEBUG_1_ef_data_ready_SHIFT) | \ + (ef_state << SC_DEBUG_1_ef_state_SHIFT) | \ + (pipe_valid << SC_DEBUG_1_pipe_valid_SHIFT) | \ + (trigger << SC_DEBUG_1_trigger_SHIFT)) + +#define SC_DEBUG_1_GET_em_state(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_em_state_MASK) >> SC_DEBUG_1_em_state_SHIFT) +#define SC_DEBUG_1_GET_em1_data_ready(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_em1_data_ready_MASK) >> SC_DEBUG_1_em1_data_ready_SHIFT) +#define SC_DEBUG_1_GET_em2_data_ready(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_em2_data_ready_MASK) >> SC_DEBUG_1_em2_data_ready_SHIFT) +#define SC_DEBUG_1_GET_move_em1_to_em2(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_move_em1_to_em2_MASK) >> SC_DEBUG_1_move_em1_to_em2_SHIFT) +#define SC_DEBUG_1_GET_ef_data_ready(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_ef_data_ready_MASK) >> SC_DEBUG_1_ef_data_ready_SHIFT) +#define SC_DEBUG_1_GET_ef_state(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_ef_state_MASK) >> SC_DEBUG_1_ef_state_SHIFT) +#define SC_DEBUG_1_GET_pipe_valid(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_pipe_valid_MASK) >> SC_DEBUG_1_pipe_valid_SHIFT) +#define SC_DEBUG_1_GET_trigger(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_trigger_MASK) >> SC_DEBUG_1_trigger_SHIFT) + +#define SC_DEBUG_1_SET_em_state(sc_debug_1_reg, em_state) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em_state_MASK) | (em_state << SC_DEBUG_1_em_state_SHIFT) +#define SC_DEBUG_1_SET_em1_data_ready(sc_debug_1_reg, em1_data_ready) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em1_data_ready_MASK) | (em1_data_ready << SC_DEBUG_1_em1_data_ready_SHIFT) +#define SC_DEBUG_1_SET_em2_data_ready(sc_debug_1_reg, em2_data_ready) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em2_data_ready_MASK) | (em2_data_ready << SC_DEBUG_1_em2_data_ready_SHIFT) +#define SC_DEBUG_1_SET_move_em1_to_em2(sc_debug_1_reg, move_em1_to_em2) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_move_em1_to_em2_MASK) | (move_em1_to_em2 << SC_DEBUG_1_move_em1_to_em2_SHIFT) +#define SC_DEBUG_1_SET_ef_data_ready(sc_debug_1_reg, ef_data_ready) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_ef_data_ready_MASK) | (ef_data_ready << SC_DEBUG_1_ef_data_ready_SHIFT) +#define SC_DEBUG_1_SET_ef_state(sc_debug_1_reg, ef_state) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_ef_state_MASK) | (ef_state << SC_DEBUG_1_ef_state_SHIFT) +#define SC_DEBUG_1_SET_pipe_valid(sc_debug_1_reg, pipe_valid) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_pipe_valid_MASK) | (pipe_valid << SC_DEBUG_1_pipe_valid_SHIFT) +#define SC_DEBUG_1_SET_trigger(sc_debug_1_reg, trigger) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_trigger_MASK) | (trigger << SC_DEBUG_1_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_1_t { + unsigned int em_state : SC_DEBUG_1_em_state_SIZE; + unsigned int em1_data_ready : SC_DEBUG_1_em1_data_ready_SIZE; + unsigned int em2_data_ready : SC_DEBUG_1_em2_data_ready_SIZE; + unsigned int move_em1_to_em2 : SC_DEBUG_1_move_em1_to_em2_SIZE; + unsigned int ef_data_ready : SC_DEBUG_1_ef_data_ready_SIZE; + unsigned int ef_state : SC_DEBUG_1_ef_state_SIZE; + unsigned int pipe_valid : SC_DEBUG_1_pipe_valid_SIZE; + unsigned int : 21; + unsigned int trigger : SC_DEBUG_1_trigger_SIZE; + } sc_debug_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_1_t { + unsigned int trigger : SC_DEBUG_1_trigger_SIZE; + unsigned int : 21; + unsigned int pipe_valid : SC_DEBUG_1_pipe_valid_SIZE; + unsigned int ef_state : SC_DEBUG_1_ef_state_SIZE; + unsigned int ef_data_ready : SC_DEBUG_1_ef_data_ready_SIZE; + unsigned int move_em1_to_em2 : SC_DEBUG_1_move_em1_to_em2_SIZE; + unsigned int em2_data_ready : SC_DEBUG_1_em2_data_ready_SIZE; + unsigned int em1_data_ready : SC_DEBUG_1_em1_data_ready_SIZE; + unsigned int em_state : SC_DEBUG_1_em_state_SIZE; + } sc_debug_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_1_t f; +} sc_debug_1_u; + + +/* + * SC_DEBUG_2 struct + */ + +#define SC_DEBUG_2_rc_rtr_dly_SIZE 1 +#define SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE 1 +#define SC_DEBUG_2_pipe_freeze_b_SIZE 1 +#define SC_DEBUG_2_prim_rts_SIZE 1 +#define SC_DEBUG_2_next_prim_rts_dly_SIZE 1 +#define SC_DEBUG_2_next_prim_rtr_dly_SIZE 1 +#define SC_DEBUG_2_pre_stage1_rts_d1_SIZE 1 +#define SC_DEBUG_2_stage0_rts_SIZE 1 +#define SC_DEBUG_2_phase_rts_dly_SIZE 1 +#define SC_DEBUG_2_end_of_prim_s1_dly_SIZE 1 +#define SC_DEBUG_2_pass_empty_prim_s1_SIZE 1 +#define SC_DEBUG_2_event_id_s1_SIZE 5 +#define SC_DEBUG_2_event_s1_SIZE 1 +#define SC_DEBUG_2_trigger_SIZE 1 + +#define SC_DEBUG_2_rc_rtr_dly_SHIFT 0 +#define SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT 1 +#define SC_DEBUG_2_pipe_freeze_b_SHIFT 3 +#define SC_DEBUG_2_prim_rts_SHIFT 4 +#define SC_DEBUG_2_next_prim_rts_dly_SHIFT 5 +#define SC_DEBUG_2_next_prim_rtr_dly_SHIFT 6 +#define SC_DEBUG_2_pre_stage1_rts_d1_SHIFT 7 +#define SC_DEBUG_2_stage0_rts_SHIFT 8 +#define SC_DEBUG_2_phase_rts_dly_SHIFT 9 +#define SC_DEBUG_2_end_of_prim_s1_dly_SHIFT 15 +#define SC_DEBUG_2_pass_empty_prim_s1_SHIFT 16 +#define SC_DEBUG_2_event_id_s1_SHIFT 17 +#define SC_DEBUG_2_event_s1_SHIFT 22 +#define SC_DEBUG_2_trigger_SHIFT 31 + +#define SC_DEBUG_2_rc_rtr_dly_MASK 0x00000001 +#define SC_DEBUG_2_qmask_ff_alm_full_d1_MASK 0x00000002 +#define SC_DEBUG_2_pipe_freeze_b_MASK 0x00000008 +#define SC_DEBUG_2_prim_rts_MASK 0x00000010 +#define SC_DEBUG_2_next_prim_rts_dly_MASK 0x00000020 +#define SC_DEBUG_2_next_prim_rtr_dly_MASK 0x00000040 +#define SC_DEBUG_2_pre_stage1_rts_d1_MASK 0x00000080 +#define SC_DEBUG_2_stage0_rts_MASK 0x00000100 +#define SC_DEBUG_2_phase_rts_dly_MASK 0x00000200 +#define SC_DEBUG_2_end_of_prim_s1_dly_MASK 0x00008000 +#define SC_DEBUG_2_pass_empty_prim_s1_MASK 0x00010000 +#define SC_DEBUG_2_event_id_s1_MASK 0x003e0000 +#define SC_DEBUG_2_event_s1_MASK 0x00400000 +#define SC_DEBUG_2_trigger_MASK 0x80000000 + +#define SC_DEBUG_2_MASK \ + (SC_DEBUG_2_rc_rtr_dly_MASK | \ + SC_DEBUG_2_qmask_ff_alm_full_d1_MASK | \ + SC_DEBUG_2_pipe_freeze_b_MASK | \ + SC_DEBUG_2_prim_rts_MASK | \ + SC_DEBUG_2_next_prim_rts_dly_MASK | \ + SC_DEBUG_2_next_prim_rtr_dly_MASK | \ + SC_DEBUG_2_pre_stage1_rts_d1_MASK | \ + SC_DEBUG_2_stage0_rts_MASK | \ + SC_DEBUG_2_phase_rts_dly_MASK | \ + SC_DEBUG_2_end_of_prim_s1_dly_MASK | \ + SC_DEBUG_2_pass_empty_prim_s1_MASK | \ + SC_DEBUG_2_event_id_s1_MASK | \ + SC_DEBUG_2_event_s1_MASK | \ + SC_DEBUG_2_trigger_MASK) + +#define SC_DEBUG_2(rc_rtr_dly, qmask_ff_alm_full_d1, pipe_freeze_b, prim_rts, next_prim_rts_dly, next_prim_rtr_dly, pre_stage1_rts_d1, stage0_rts, phase_rts_dly, end_of_prim_s1_dly, pass_empty_prim_s1, event_id_s1, event_s1, trigger) \ + ((rc_rtr_dly << SC_DEBUG_2_rc_rtr_dly_SHIFT) | \ + (qmask_ff_alm_full_d1 << SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT) | \ + (pipe_freeze_b << SC_DEBUG_2_pipe_freeze_b_SHIFT) | \ + (prim_rts << SC_DEBUG_2_prim_rts_SHIFT) | \ + (next_prim_rts_dly << SC_DEBUG_2_next_prim_rts_dly_SHIFT) | \ + (next_prim_rtr_dly << SC_DEBUG_2_next_prim_rtr_dly_SHIFT) | \ + (pre_stage1_rts_d1 << SC_DEBUG_2_pre_stage1_rts_d1_SHIFT) | \ + (stage0_rts << SC_DEBUG_2_stage0_rts_SHIFT) | \ + (phase_rts_dly << SC_DEBUG_2_phase_rts_dly_SHIFT) | \ + (end_of_prim_s1_dly << SC_DEBUG_2_end_of_prim_s1_dly_SHIFT) | \ + (pass_empty_prim_s1 << SC_DEBUG_2_pass_empty_prim_s1_SHIFT) | \ + (event_id_s1 << SC_DEBUG_2_event_id_s1_SHIFT) | \ + (event_s1 << SC_DEBUG_2_event_s1_SHIFT) | \ + (trigger << SC_DEBUG_2_trigger_SHIFT)) + +#define SC_DEBUG_2_GET_rc_rtr_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_rc_rtr_dly_MASK) >> SC_DEBUG_2_rc_rtr_dly_SHIFT) +#define SC_DEBUG_2_GET_qmask_ff_alm_full_d1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_qmask_ff_alm_full_d1_MASK) >> SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT) +#define SC_DEBUG_2_GET_pipe_freeze_b(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_pipe_freeze_b_MASK) >> SC_DEBUG_2_pipe_freeze_b_SHIFT) +#define SC_DEBUG_2_GET_prim_rts(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_prim_rts_MASK) >> SC_DEBUG_2_prim_rts_SHIFT) +#define SC_DEBUG_2_GET_next_prim_rts_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_next_prim_rts_dly_MASK) >> SC_DEBUG_2_next_prim_rts_dly_SHIFT) +#define SC_DEBUG_2_GET_next_prim_rtr_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_next_prim_rtr_dly_MASK) >> SC_DEBUG_2_next_prim_rtr_dly_SHIFT) +#define SC_DEBUG_2_GET_pre_stage1_rts_d1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_pre_stage1_rts_d1_MASK) >> SC_DEBUG_2_pre_stage1_rts_d1_SHIFT) +#define SC_DEBUG_2_GET_stage0_rts(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_stage0_rts_MASK) >> SC_DEBUG_2_stage0_rts_SHIFT) +#define SC_DEBUG_2_GET_phase_rts_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_phase_rts_dly_MASK) >> SC_DEBUG_2_phase_rts_dly_SHIFT) +#define SC_DEBUG_2_GET_end_of_prim_s1_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_end_of_prim_s1_dly_MASK) >> SC_DEBUG_2_end_of_prim_s1_dly_SHIFT) +#define SC_DEBUG_2_GET_pass_empty_prim_s1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_pass_empty_prim_s1_MASK) >> SC_DEBUG_2_pass_empty_prim_s1_SHIFT) +#define SC_DEBUG_2_GET_event_id_s1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_event_id_s1_MASK) >> SC_DEBUG_2_event_id_s1_SHIFT) +#define SC_DEBUG_2_GET_event_s1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_event_s1_MASK) >> SC_DEBUG_2_event_s1_SHIFT) +#define SC_DEBUG_2_GET_trigger(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_trigger_MASK) >> SC_DEBUG_2_trigger_SHIFT) + +#define SC_DEBUG_2_SET_rc_rtr_dly(sc_debug_2_reg, rc_rtr_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_rc_rtr_dly_MASK) | (rc_rtr_dly << SC_DEBUG_2_rc_rtr_dly_SHIFT) +#define SC_DEBUG_2_SET_qmask_ff_alm_full_d1(sc_debug_2_reg, qmask_ff_alm_full_d1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_qmask_ff_alm_full_d1_MASK) | (qmask_ff_alm_full_d1 << SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT) +#define SC_DEBUG_2_SET_pipe_freeze_b(sc_debug_2_reg, pipe_freeze_b) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pipe_freeze_b_MASK) | (pipe_freeze_b << SC_DEBUG_2_pipe_freeze_b_SHIFT) +#define SC_DEBUG_2_SET_prim_rts(sc_debug_2_reg, prim_rts) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_prim_rts_MASK) | (prim_rts << SC_DEBUG_2_prim_rts_SHIFT) +#define SC_DEBUG_2_SET_next_prim_rts_dly(sc_debug_2_reg, next_prim_rts_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_next_prim_rts_dly_MASK) | (next_prim_rts_dly << SC_DEBUG_2_next_prim_rts_dly_SHIFT) +#define SC_DEBUG_2_SET_next_prim_rtr_dly(sc_debug_2_reg, next_prim_rtr_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_next_prim_rtr_dly_MASK) | (next_prim_rtr_dly << SC_DEBUG_2_next_prim_rtr_dly_SHIFT) +#define SC_DEBUG_2_SET_pre_stage1_rts_d1(sc_debug_2_reg, pre_stage1_rts_d1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pre_stage1_rts_d1_MASK) | (pre_stage1_rts_d1 << SC_DEBUG_2_pre_stage1_rts_d1_SHIFT) +#define SC_DEBUG_2_SET_stage0_rts(sc_debug_2_reg, stage0_rts) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_stage0_rts_MASK) | (stage0_rts << SC_DEBUG_2_stage0_rts_SHIFT) +#define SC_DEBUG_2_SET_phase_rts_dly(sc_debug_2_reg, phase_rts_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_phase_rts_dly_MASK) | (phase_rts_dly << SC_DEBUG_2_phase_rts_dly_SHIFT) +#define SC_DEBUG_2_SET_end_of_prim_s1_dly(sc_debug_2_reg, end_of_prim_s1_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_end_of_prim_s1_dly_MASK) | (end_of_prim_s1_dly << SC_DEBUG_2_end_of_prim_s1_dly_SHIFT) +#define SC_DEBUG_2_SET_pass_empty_prim_s1(sc_debug_2_reg, pass_empty_prim_s1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pass_empty_prim_s1_MASK) | (pass_empty_prim_s1 << SC_DEBUG_2_pass_empty_prim_s1_SHIFT) +#define SC_DEBUG_2_SET_event_id_s1(sc_debug_2_reg, event_id_s1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_event_id_s1_MASK) | (event_id_s1 << SC_DEBUG_2_event_id_s1_SHIFT) +#define SC_DEBUG_2_SET_event_s1(sc_debug_2_reg, event_s1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_event_s1_MASK) | (event_s1 << SC_DEBUG_2_event_s1_SHIFT) +#define SC_DEBUG_2_SET_trigger(sc_debug_2_reg, trigger) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_trigger_MASK) | (trigger << SC_DEBUG_2_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_2_t { + unsigned int rc_rtr_dly : SC_DEBUG_2_rc_rtr_dly_SIZE; + unsigned int qmask_ff_alm_full_d1 : SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE; + unsigned int : 1; + unsigned int pipe_freeze_b : SC_DEBUG_2_pipe_freeze_b_SIZE; + unsigned int prim_rts : SC_DEBUG_2_prim_rts_SIZE; + unsigned int next_prim_rts_dly : SC_DEBUG_2_next_prim_rts_dly_SIZE; + unsigned int next_prim_rtr_dly : SC_DEBUG_2_next_prim_rtr_dly_SIZE; + unsigned int pre_stage1_rts_d1 : SC_DEBUG_2_pre_stage1_rts_d1_SIZE; + unsigned int stage0_rts : SC_DEBUG_2_stage0_rts_SIZE; + unsigned int phase_rts_dly : SC_DEBUG_2_phase_rts_dly_SIZE; + unsigned int : 5; + unsigned int end_of_prim_s1_dly : SC_DEBUG_2_end_of_prim_s1_dly_SIZE; + unsigned int pass_empty_prim_s1 : SC_DEBUG_2_pass_empty_prim_s1_SIZE; + unsigned int event_id_s1 : SC_DEBUG_2_event_id_s1_SIZE; + unsigned int event_s1 : SC_DEBUG_2_event_s1_SIZE; + unsigned int : 8; + unsigned int trigger : SC_DEBUG_2_trigger_SIZE; + } sc_debug_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_2_t { + unsigned int trigger : SC_DEBUG_2_trigger_SIZE; + unsigned int : 8; + unsigned int event_s1 : SC_DEBUG_2_event_s1_SIZE; + unsigned int event_id_s1 : SC_DEBUG_2_event_id_s1_SIZE; + unsigned int pass_empty_prim_s1 : SC_DEBUG_2_pass_empty_prim_s1_SIZE; + unsigned int end_of_prim_s1_dly : SC_DEBUG_2_end_of_prim_s1_dly_SIZE; + unsigned int : 5; + unsigned int phase_rts_dly : SC_DEBUG_2_phase_rts_dly_SIZE; + unsigned int stage0_rts : SC_DEBUG_2_stage0_rts_SIZE; + unsigned int pre_stage1_rts_d1 : SC_DEBUG_2_pre_stage1_rts_d1_SIZE; + unsigned int next_prim_rtr_dly : SC_DEBUG_2_next_prim_rtr_dly_SIZE; + unsigned int next_prim_rts_dly : SC_DEBUG_2_next_prim_rts_dly_SIZE; + unsigned int prim_rts : SC_DEBUG_2_prim_rts_SIZE; + unsigned int pipe_freeze_b : SC_DEBUG_2_pipe_freeze_b_SIZE; + unsigned int : 1; + unsigned int qmask_ff_alm_full_d1 : SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE; + unsigned int rc_rtr_dly : SC_DEBUG_2_rc_rtr_dly_SIZE; + } sc_debug_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_2_t f; +} sc_debug_2_u; + + +/* + * SC_DEBUG_3 struct + */ + +#define SC_DEBUG_3_x_curr_s1_SIZE 11 +#define SC_DEBUG_3_y_curr_s1_SIZE 11 +#define SC_DEBUG_3_trigger_SIZE 1 + +#define SC_DEBUG_3_x_curr_s1_SHIFT 0 +#define SC_DEBUG_3_y_curr_s1_SHIFT 11 +#define SC_DEBUG_3_trigger_SHIFT 31 + +#define SC_DEBUG_3_x_curr_s1_MASK 0x000007ff +#define SC_DEBUG_3_y_curr_s1_MASK 0x003ff800 +#define SC_DEBUG_3_trigger_MASK 0x80000000 + +#define SC_DEBUG_3_MASK \ + (SC_DEBUG_3_x_curr_s1_MASK | \ + SC_DEBUG_3_y_curr_s1_MASK | \ + SC_DEBUG_3_trigger_MASK) + +#define SC_DEBUG_3(x_curr_s1, y_curr_s1, trigger) \ + ((x_curr_s1 << SC_DEBUG_3_x_curr_s1_SHIFT) | \ + (y_curr_s1 << SC_DEBUG_3_y_curr_s1_SHIFT) | \ + (trigger << SC_DEBUG_3_trigger_SHIFT)) + +#define SC_DEBUG_3_GET_x_curr_s1(sc_debug_3) \ + ((sc_debug_3 & SC_DEBUG_3_x_curr_s1_MASK) >> SC_DEBUG_3_x_curr_s1_SHIFT) +#define SC_DEBUG_3_GET_y_curr_s1(sc_debug_3) \ + ((sc_debug_3 & SC_DEBUG_3_y_curr_s1_MASK) >> SC_DEBUG_3_y_curr_s1_SHIFT) +#define SC_DEBUG_3_GET_trigger(sc_debug_3) \ + ((sc_debug_3 & SC_DEBUG_3_trigger_MASK) >> SC_DEBUG_3_trigger_SHIFT) + +#define SC_DEBUG_3_SET_x_curr_s1(sc_debug_3_reg, x_curr_s1) \ + sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_x_curr_s1_MASK) | (x_curr_s1 << SC_DEBUG_3_x_curr_s1_SHIFT) +#define SC_DEBUG_3_SET_y_curr_s1(sc_debug_3_reg, y_curr_s1) \ + sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_y_curr_s1_MASK) | (y_curr_s1 << SC_DEBUG_3_y_curr_s1_SHIFT) +#define SC_DEBUG_3_SET_trigger(sc_debug_3_reg, trigger) \ + sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_trigger_MASK) | (trigger << SC_DEBUG_3_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_3_t { + unsigned int x_curr_s1 : SC_DEBUG_3_x_curr_s1_SIZE; + unsigned int y_curr_s1 : SC_DEBUG_3_y_curr_s1_SIZE; + unsigned int : 9; + unsigned int trigger : SC_DEBUG_3_trigger_SIZE; + } sc_debug_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_3_t { + unsigned int trigger : SC_DEBUG_3_trigger_SIZE; + unsigned int : 9; + unsigned int y_curr_s1 : SC_DEBUG_3_y_curr_s1_SIZE; + unsigned int x_curr_s1 : SC_DEBUG_3_x_curr_s1_SIZE; + } sc_debug_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_3_t f; +} sc_debug_3_u; + + +/* + * SC_DEBUG_4 struct + */ + +#define SC_DEBUG_4_y_end_s1_SIZE 14 +#define SC_DEBUG_4_y_start_s1_SIZE 14 +#define SC_DEBUG_4_y_dir_s1_SIZE 1 +#define SC_DEBUG_4_trigger_SIZE 1 + +#define SC_DEBUG_4_y_end_s1_SHIFT 0 +#define SC_DEBUG_4_y_start_s1_SHIFT 14 +#define SC_DEBUG_4_y_dir_s1_SHIFT 28 +#define SC_DEBUG_4_trigger_SHIFT 31 + +#define SC_DEBUG_4_y_end_s1_MASK 0x00003fff +#define SC_DEBUG_4_y_start_s1_MASK 0x0fffc000 +#define SC_DEBUG_4_y_dir_s1_MASK 0x10000000 +#define SC_DEBUG_4_trigger_MASK 0x80000000 + +#define SC_DEBUG_4_MASK \ + (SC_DEBUG_4_y_end_s1_MASK | \ + SC_DEBUG_4_y_start_s1_MASK | \ + SC_DEBUG_4_y_dir_s1_MASK | \ + SC_DEBUG_4_trigger_MASK) + +#define SC_DEBUG_4(y_end_s1, y_start_s1, y_dir_s1, trigger) \ + ((y_end_s1 << SC_DEBUG_4_y_end_s1_SHIFT) | \ + (y_start_s1 << SC_DEBUG_4_y_start_s1_SHIFT) | \ + (y_dir_s1 << SC_DEBUG_4_y_dir_s1_SHIFT) | \ + (trigger << SC_DEBUG_4_trigger_SHIFT)) + +#define SC_DEBUG_4_GET_y_end_s1(sc_debug_4) \ + ((sc_debug_4 & SC_DEBUG_4_y_end_s1_MASK) >> SC_DEBUG_4_y_end_s1_SHIFT) +#define SC_DEBUG_4_GET_y_start_s1(sc_debug_4) \ + ((sc_debug_4 & SC_DEBUG_4_y_start_s1_MASK) >> SC_DEBUG_4_y_start_s1_SHIFT) +#define SC_DEBUG_4_GET_y_dir_s1(sc_debug_4) \ + ((sc_debug_4 & SC_DEBUG_4_y_dir_s1_MASK) >> SC_DEBUG_4_y_dir_s1_SHIFT) +#define SC_DEBUG_4_GET_trigger(sc_debug_4) \ + ((sc_debug_4 & SC_DEBUG_4_trigger_MASK) >> SC_DEBUG_4_trigger_SHIFT) + +#define SC_DEBUG_4_SET_y_end_s1(sc_debug_4_reg, y_end_s1) \ + sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_end_s1_MASK) | (y_end_s1 << SC_DEBUG_4_y_end_s1_SHIFT) +#define SC_DEBUG_4_SET_y_start_s1(sc_debug_4_reg, y_start_s1) \ + sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_start_s1_MASK) | (y_start_s1 << SC_DEBUG_4_y_start_s1_SHIFT) +#define SC_DEBUG_4_SET_y_dir_s1(sc_debug_4_reg, y_dir_s1) \ + sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_dir_s1_MASK) | (y_dir_s1 << SC_DEBUG_4_y_dir_s1_SHIFT) +#define SC_DEBUG_4_SET_trigger(sc_debug_4_reg, trigger) \ + sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_trigger_MASK) | (trigger << SC_DEBUG_4_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_4_t { + unsigned int y_end_s1 : SC_DEBUG_4_y_end_s1_SIZE; + unsigned int y_start_s1 : SC_DEBUG_4_y_start_s1_SIZE; + unsigned int y_dir_s1 : SC_DEBUG_4_y_dir_s1_SIZE; + unsigned int : 2; + unsigned int trigger : SC_DEBUG_4_trigger_SIZE; + } sc_debug_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_4_t { + unsigned int trigger : SC_DEBUG_4_trigger_SIZE; + unsigned int : 2; + unsigned int y_dir_s1 : SC_DEBUG_4_y_dir_s1_SIZE; + unsigned int y_start_s1 : SC_DEBUG_4_y_start_s1_SIZE; + unsigned int y_end_s1 : SC_DEBUG_4_y_end_s1_SIZE; + } sc_debug_4_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_4_t f; +} sc_debug_4_u; + + +/* + * SC_DEBUG_5 struct + */ + +#define SC_DEBUG_5_x_end_s1_SIZE 14 +#define SC_DEBUG_5_x_start_s1_SIZE 14 +#define SC_DEBUG_5_x_dir_s1_SIZE 1 +#define SC_DEBUG_5_trigger_SIZE 1 + +#define SC_DEBUG_5_x_end_s1_SHIFT 0 +#define SC_DEBUG_5_x_start_s1_SHIFT 14 +#define SC_DEBUG_5_x_dir_s1_SHIFT 28 +#define SC_DEBUG_5_trigger_SHIFT 31 + +#define SC_DEBUG_5_x_end_s1_MASK 0x00003fff +#define SC_DEBUG_5_x_start_s1_MASK 0x0fffc000 +#define SC_DEBUG_5_x_dir_s1_MASK 0x10000000 +#define SC_DEBUG_5_trigger_MASK 0x80000000 + +#define SC_DEBUG_5_MASK \ + (SC_DEBUG_5_x_end_s1_MASK | \ + SC_DEBUG_5_x_start_s1_MASK | \ + SC_DEBUG_5_x_dir_s1_MASK | \ + SC_DEBUG_5_trigger_MASK) + +#define SC_DEBUG_5(x_end_s1, x_start_s1, x_dir_s1, trigger) \ + ((x_end_s1 << SC_DEBUG_5_x_end_s1_SHIFT) | \ + (x_start_s1 << SC_DEBUG_5_x_start_s1_SHIFT) | \ + (x_dir_s1 << SC_DEBUG_5_x_dir_s1_SHIFT) | \ + (trigger << SC_DEBUG_5_trigger_SHIFT)) + +#define SC_DEBUG_5_GET_x_end_s1(sc_debug_5) \ + ((sc_debug_5 & SC_DEBUG_5_x_end_s1_MASK) >> SC_DEBUG_5_x_end_s1_SHIFT) +#define SC_DEBUG_5_GET_x_start_s1(sc_debug_5) \ + ((sc_debug_5 & SC_DEBUG_5_x_start_s1_MASK) >> SC_DEBUG_5_x_start_s1_SHIFT) +#define SC_DEBUG_5_GET_x_dir_s1(sc_debug_5) \ + ((sc_debug_5 & SC_DEBUG_5_x_dir_s1_MASK) >> SC_DEBUG_5_x_dir_s1_SHIFT) +#define SC_DEBUG_5_GET_trigger(sc_debug_5) \ + ((sc_debug_5 & SC_DEBUG_5_trigger_MASK) >> SC_DEBUG_5_trigger_SHIFT) + +#define SC_DEBUG_5_SET_x_end_s1(sc_debug_5_reg, x_end_s1) \ + sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_end_s1_MASK) | (x_end_s1 << SC_DEBUG_5_x_end_s1_SHIFT) +#define SC_DEBUG_5_SET_x_start_s1(sc_debug_5_reg, x_start_s1) \ + sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_start_s1_MASK) | (x_start_s1 << SC_DEBUG_5_x_start_s1_SHIFT) +#define SC_DEBUG_5_SET_x_dir_s1(sc_debug_5_reg, x_dir_s1) \ + sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_dir_s1_MASK) | (x_dir_s1 << SC_DEBUG_5_x_dir_s1_SHIFT) +#define SC_DEBUG_5_SET_trigger(sc_debug_5_reg, trigger) \ + sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_trigger_MASK) | (trigger << SC_DEBUG_5_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_5_t { + unsigned int x_end_s1 : SC_DEBUG_5_x_end_s1_SIZE; + unsigned int x_start_s1 : SC_DEBUG_5_x_start_s1_SIZE; + unsigned int x_dir_s1 : SC_DEBUG_5_x_dir_s1_SIZE; + unsigned int : 2; + unsigned int trigger : SC_DEBUG_5_trigger_SIZE; + } sc_debug_5_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_5_t { + unsigned int trigger : SC_DEBUG_5_trigger_SIZE; + unsigned int : 2; + unsigned int x_dir_s1 : SC_DEBUG_5_x_dir_s1_SIZE; + unsigned int x_start_s1 : SC_DEBUG_5_x_start_s1_SIZE; + unsigned int x_end_s1 : SC_DEBUG_5_x_end_s1_SIZE; + } sc_debug_5_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_5_t f; +} sc_debug_5_u; + + +/* + * SC_DEBUG_6 struct + */ + +#define SC_DEBUG_6_z_ff_empty_SIZE 1 +#define SC_DEBUG_6_qmcntl_ff_empty_SIZE 1 +#define SC_DEBUG_6_xy_ff_empty_SIZE 1 +#define SC_DEBUG_6_event_flag_SIZE 1 +#define SC_DEBUG_6_z_mask_needed_SIZE 1 +#define SC_DEBUG_6_state_SIZE 3 +#define SC_DEBUG_6_state_delayed_SIZE 3 +#define SC_DEBUG_6_data_valid_SIZE 1 +#define SC_DEBUG_6_data_valid_d_SIZE 1 +#define SC_DEBUG_6_tilex_delayed_SIZE 9 +#define SC_DEBUG_6_tiley_delayed_SIZE 9 +#define SC_DEBUG_6_trigger_SIZE 1 + +#define SC_DEBUG_6_z_ff_empty_SHIFT 0 +#define SC_DEBUG_6_qmcntl_ff_empty_SHIFT 1 +#define SC_DEBUG_6_xy_ff_empty_SHIFT 2 +#define SC_DEBUG_6_event_flag_SHIFT 3 +#define SC_DEBUG_6_z_mask_needed_SHIFT 4 +#define SC_DEBUG_6_state_SHIFT 5 +#define SC_DEBUG_6_state_delayed_SHIFT 8 +#define SC_DEBUG_6_data_valid_SHIFT 11 +#define SC_DEBUG_6_data_valid_d_SHIFT 12 +#define SC_DEBUG_6_tilex_delayed_SHIFT 13 +#define SC_DEBUG_6_tiley_delayed_SHIFT 22 +#define SC_DEBUG_6_trigger_SHIFT 31 + +#define SC_DEBUG_6_z_ff_empty_MASK 0x00000001 +#define SC_DEBUG_6_qmcntl_ff_empty_MASK 0x00000002 +#define SC_DEBUG_6_xy_ff_empty_MASK 0x00000004 +#define SC_DEBUG_6_event_flag_MASK 0x00000008 +#define SC_DEBUG_6_z_mask_needed_MASK 0x00000010 +#define SC_DEBUG_6_state_MASK 0x000000e0 +#define SC_DEBUG_6_state_delayed_MASK 0x00000700 +#define SC_DEBUG_6_data_valid_MASK 0x00000800 +#define SC_DEBUG_6_data_valid_d_MASK 0x00001000 +#define SC_DEBUG_6_tilex_delayed_MASK 0x003fe000 +#define SC_DEBUG_6_tiley_delayed_MASK 0x7fc00000 +#define SC_DEBUG_6_trigger_MASK 0x80000000 + +#define SC_DEBUG_6_MASK \ + (SC_DEBUG_6_z_ff_empty_MASK | \ + SC_DEBUG_6_qmcntl_ff_empty_MASK | \ + SC_DEBUG_6_xy_ff_empty_MASK | \ + SC_DEBUG_6_event_flag_MASK | \ + SC_DEBUG_6_z_mask_needed_MASK | \ + SC_DEBUG_6_state_MASK | \ + SC_DEBUG_6_state_delayed_MASK | \ + SC_DEBUG_6_data_valid_MASK | \ + SC_DEBUG_6_data_valid_d_MASK | \ + SC_DEBUG_6_tilex_delayed_MASK | \ + SC_DEBUG_6_tiley_delayed_MASK | \ + SC_DEBUG_6_trigger_MASK) + +#define SC_DEBUG_6(z_ff_empty, qmcntl_ff_empty, xy_ff_empty, event_flag, z_mask_needed, state, state_delayed, data_valid, data_valid_d, tilex_delayed, tiley_delayed, trigger) \ + ((z_ff_empty << SC_DEBUG_6_z_ff_empty_SHIFT) | \ + (qmcntl_ff_empty << SC_DEBUG_6_qmcntl_ff_empty_SHIFT) | \ + (xy_ff_empty << SC_DEBUG_6_xy_ff_empty_SHIFT) | \ + (event_flag << SC_DEBUG_6_event_flag_SHIFT) | \ + (z_mask_needed << SC_DEBUG_6_z_mask_needed_SHIFT) | \ + (state << SC_DEBUG_6_state_SHIFT) | \ + (state_delayed << SC_DEBUG_6_state_delayed_SHIFT) | \ + (data_valid << SC_DEBUG_6_data_valid_SHIFT) | \ + (data_valid_d << SC_DEBUG_6_data_valid_d_SHIFT) | \ + (tilex_delayed << SC_DEBUG_6_tilex_delayed_SHIFT) | \ + (tiley_delayed << SC_DEBUG_6_tiley_delayed_SHIFT) | \ + (trigger << SC_DEBUG_6_trigger_SHIFT)) + +#define SC_DEBUG_6_GET_z_ff_empty(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_z_ff_empty_MASK) >> SC_DEBUG_6_z_ff_empty_SHIFT) +#define SC_DEBUG_6_GET_qmcntl_ff_empty(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_qmcntl_ff_empty_MASK) >> SC_DEBUG_6_qmcntl_ff_empty_SHIFT) +#define SC_DEBUG_6_GET_xy_ff_empty(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_xy_ff_empty_MASK) >> SC_DEBUG_6_xy_ff_empty_SHIFT) +#define SC_DEBUG_6_GET_event_flag(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_event_flag_MASK) >> SC_DEBUG_6_event_flag_SHIFT) +#define SC_DEBUG_6_GET_z_mask_needed(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_z_mask_needed_MASK) >> SC_DEBUG_6_z_mask_needed_SHIFT) +#define SC_DEBUG_6_GET_state(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_state_MASK) >> SC_DEBUG_6_state_SHIFT) +#define SC_DEBUG_6_GET_state_delayed(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_state_delayed_MASK) >> SC_DEBUG_6_state_delayed_SHIFT) +#define SC_DEBUG_6_GET_data_valid(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_data_valid_MASK) >> SC_DEBUG_6_data_valid_SHIFT) +#define SC_DEBUG_6_GET_data_valid_d(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_data_valid_d_MASK) >> SC_DEBUG_6_data_valid_d_SHIFT) +#define SC_DEBUG_6_GET_tilex_delayed(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_tilex_delayed_MASK) >> SC_DEBUG_6_tilex_delayed_SHIFT) +#define SC_DEBUG_6_GET_tiley_delayed(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_tiley_delayed_MASK) >> SC_DEBUG_6_tiley_delayed_SHIFT) +#define SC_DEBUG_6_GET_trigger(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_trigger_MASK) >> SC_DEBUG_6_trigger_SHIFT) + +#define SC_DEBUG_6_SET_z_ff_empty(sc_debug_6_reg, z_ff_empty) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_z_ff_empty_MASK) | (z_ff_empty << SC_DEBUG_6_z_ff_empty_SHIFT) +#define SC_DEBUG_6_SET_qmcntl_ff_empty(sc_debug_6_reg, qmcntl_ff_empty) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_qmcntl_ff_empty_MASK) | (qmcntl_ff_empty << SC_DEBUG_6_qmcntl_ff_empty_SHIFT) +#define SC_DEBUG_6_SET_xy_ff_empty(sc_debug_6_reg, xy_ff_empty) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_xy_ff_empty_MASK) | (xy_ff_empty << SC_DEBUG_6_xy_ff_empty_SHIFT) +#define SC_DEBUG_6_SET_event_flag(sc_debug_6_reg, event_flag) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_event_flag_MASK) | (event_flag << SC_DEBUG_6_event_flag_SHIFT) +#define SC_DEBUG_6_SET_z_mask_needed(sc_debug_6_reg, z_mask_needed) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_z_mask_needed_MASK) | (z_mask_needed << SC_DEBUG_6_z_mask_needed_SHIFT) +#define SC_DEBUG_6_SET_state(sc_debug_6_reg, state) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_state_MASK) | (state << SC_DEBUG_6_state_SHIFT) +#define SC_DEBUG_6_SET_state_delayed(sc_debug_6_reg, state_delayed) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_state_delayed_MASK) | (state_delayed << SC_DEBUG_6_state_delayed_SHIFT) +#define SC_DEBUG_6_SET_data_valid(sc_debug_6_reg, data_valid) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_data_valid_MASK) | (data_valid << SC_DEBUG_6_data_valid_SHIFT) +#define SC_DEBUG_6_SET_data_valid_d(sc_debug_6_reg, data_valid_d) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_data_valid_d_MASK) | (data_valid_d << SC_DEBUG_6_data_valid_d_SHIFT) +#define SC_DEBUG_6_SET_tilex_delayed(sc_debug_6_reg, tilex_delayed) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_tilex_delayed_MASK) | (tilex_delayed << SC_DEBUG_6_tilex_delayed_SHIFT) +#define SC_DEBUG_6_SET_tiley_delayed(sc_debug_6_reg, tiley_delayed) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_tiley_delayed_MASK) | (tiley_delayed << SC_DEBUG_6_tiley_delayed_SHIFT) +#define SC_DEBUG_6_SET_trigger(sc_debug_6_reg, trigger) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_trigger_MASK) | (trigger << SC_DEBUG_6_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_6_t { + unsigned int z_ff_empty : SC_DEBUG_6_z_ff_empty_SIZE; + unsigned int qmcntl_ff_empty : SC_DEBUG_6_qmcntl_ff_empty_SIZE; + unsigned int xy_ff_empty : SC_DEBUG_6_xy_ff_empty_SIZE; + unsigned int event_flag : SC_DEBUG_6_event_flag_SIZE; + unsigned int z_mask_needed : SC_DEBUG_6_z_mask_needed_SIZE; + unsigned int state : SC_DEBUG_6_state_SIZE; + unsigned int state_delayed : SC_DEBUG_6_state_delayed_SIZE; + unsigned int data_valid : SC_DEBUG_6_data_valid_SIZE; + unsigned int data_valid_d : SC_DEBUG_6_data_valid_d_SIZE; + unsigned int tilex_delayed : SC_DEBUG_6_tilex_delayed_SIZE; + unsigned int tiley_delayed : SC_DEBUG_6_tiley_delayed_SIZE; + unsigned int trigger : SC_DEBUG_6_trigger_SIZE; + } sc_debug_6_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_6_t { + unsigned int trigger : SC_DEBUG_6_trigger_SIZE; + unsigned int tiley_delayed : SC_DEBUG_6_tiley_delayed_SIZE; + unsigned int tilex_delayed : SC_DEBUG_6_tilex_delayed_SIZE; + unsigned int data_valid_d : SC_DEBUG_6_data_valid_d_SIZE; + unsigned int data_valid : SC_DEBUG_6_data_valid_SIZE; + unsigned int state_delayed : SC_DEBUG_6_state_delayed_SIZE; + unsigned int state : SC_DEBUG_6_state_SIZE; + unsigned int z_mask_needed : SC_DEBUG_6_z_mask_needed_SIZE; + unsigned int event_flag : SC_DEBUG_6_event_flag_SIZE; + unsigned int xy_ff_empty : SC_DEBUG_6_xy_ff_empty_SIZE; + unsigned int qmcntl_ff_empty : SC_DEBUG_6_qmcntl_ff_empty_SIZE; + unsigned int z_ff_empty : SC_DEBUG_6_z_ff_empty_SIZE; + } sc_debug_6_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_6_t f; +} sc_debug_6_u; + + +/* + * SC_DEBUG_7 struct + */ + +#define SC_DEBUG_7_event_flag_SIZE 1 +#define SC_DEBUG_7_deallocate_SIZE 3 +#define SC_DEBUG_7_fpos_SIZE 1 +#define SC_DEBUG_7_sr_prim_we_SIZE 1 +#define SC_DEBUG_7_last_tile_SIZE 1 +#define SC_DEBUG_7_tile_ff_we_SIZE 1 +#define SC_DEBUG_7_qs_data_valid_SIZE 1 +#define SC_DEBUG_7_qs_q0_y_SIZE 2 +#define SC_DEBUG_7_qs_q0_x_SIZE 2 +#define SC_DEBUG_7_qs_q0_valid_SIZE 1 +#define SC_DEBUG_7_prim_ff_we_SIZE 1 +#define SC_DEBUG_7_tile_ff_re_SIZE 1 +#define SC_DEBUG_7_fw_prim_data_valid_SIZE 1 +#define SC_DEBUG_7_last_quad_of_tile_SIZE 1 +#define SC_DEBUG_7_first_quad_of_tile_SIZE 1 +#define SC_DEBUG_7_first_quad_of_prim_SIZE 1 +#define SC_DEBUG_7_new_prim_SIZE 1 +#define SC_DEBUG_7_load_new_tile_data_SIZE 1 +#define SC_DEBUG_7_state_SIZE 2 +#define SC_DEBUG_7_fifos_ready_SIZE 1 +#define SC_DEBUG_7_trigger_SIZE 1 + +#define SC_DEBUG_7_event_flag_SHIFT 0 +#define SC_DEBUG_7_deallocate_SHIFT 1 +#define SC_DEBUG_7_fpos_SHIFT 4 +#define SC_DEBUG_7_sr_prim_we_SHIFT 5 +#define SC_DEBUG_7_last_tile_SHIFT 6 +#define SC_DEBUG_7_tile_ff_we_SHIFT 7 +#define SC_DEBUG_7_qs_data_valid_SHIFT 8 +#define SC_DEBUG_7_qs_q0_y_SHIFT 9 +#define SC_DEBUG_7_qs_q0_x_SHIFT 11 +#define SC_DEBUG_7_qs_q0_valid_SHIFT 13 +#define SC_DEBUG_7_prim_ff_we_SHIFT 14 +#define SC_DEBUG_7_tile_ff_re_SHIFT 15 +#define SC_DEBUG_7_fw_prim_data_valid_SHIFT 16 +#define SC_DEBUG_7_last_quad_of_tile_SHIFT 17 +#define SC_DEBUG_7_first_quad_of_tile_SHIFT 18 +#define SC_DEBUG_7_first_quad_of_prim_SHIFT 19 +#define SC_DEBUG_7_new_prim_SHIFT 20 +#define SC_DEBUG_7_load_new_tile_data_SHIFT 21 +#define SC_DEBUG_7_state_SHIFT 22 +#define SC_DEBUG_7_fifos_ready_SHIFT 24 +#define SC_DEBUG_7_trigger_SHIFT 31 + +#define SC_DEBUG_7_event_flag_MASK 0x00000001 +#define SC_DEBUG_7_deallocate_MASK 0x0000000e +#define SC_DEBUG_7_fpos_MASK 0x00000010 +#define SC_DEBUG_7_sr_prim_we_MASK 0x00000020 +#define SC_DEBUG_7_last_tile_MASK 0x00000040 +#define SC_DEBUG_7_tile_ff_we_MASK 0x00000080 +#define SC_DEBUG_7_qs_data_valid_MASK 0x00000100 +#define SC_DEBUG_7_qs_q0_y_MASK 0x00000600 +#define SC_DEBUG_7_qs_q0_x_MASK 0x00001800 +#define SC_DEBUG_7_qs_q0_valid_MASK 0x00002000 +#define SC_DEBUG_7_prim_ff_we_MASK 0x00004000 +#define SC_DEBUG_7_tile_ff_re_MASK 0x00008000 +#define SC_DEBUG_7_fw_prim_data_valid_MASK 0x00010000 +#define SC_DEBUG_7_last_quad_of_tile_MASK 0x00020000 +#define SC_DEBUG_7_first_quad_of_tile_MASK 0x00040000 +#define SC_DEBUG_7_first_quad_of_prim_MASK 0x00080000 +#define SC_DEBUG_7_new_prim_MASK 0x00100000 +#define SC_DEBUG_7_load_new_tile_data_MASK 0x00200000 +#define SC_DEBUG_7_state_MASK 0x00c00000 +#define SC_DEBUG_7_fifos_ready_MASK 0x01000000 +#define SC_DEBUG_7_trigger_MASK 0x80000000 + +#define SC_DEBUG_7_MASK \ + (SC_DEBUG_7_event_flag_MASK | \ + SC_DEBUG_7_deallocate_MASK | \ + SC_DEBUG_7_fpos_MASK | \ + SC_DEBUG_7_sr_prim_we_MASK | \ + SC_DEBUG_7_last_tile_MASK | \ + SC_DEBUG_7_tile_ff_we_MASK | \ + SC_DEBUG_7_qs_data_valid_MASK | \ + SC_DEBUG_7_qs_q0_y_MASK | \ + SC_DEBUG_7_qs_q0_x_MASK | \ + SC_DEBUG_7_qs_q0_valid_MASK | \ + SC_DEBUG_7_prim_ff_we_MASK | \ + SC_DEBUG_7_tile_ff_re_MASK | \ + SC_DEBUG_7_fw_prim_data_valid_MASK | \ + SC_DEBUG_7_last_quad_of_tile_MASK | \ + SC_DEBUG_7_first_quad_of_tile_MASK | \ + SC_DEBUG_7_first_quad_of_prim_MASK | \ + SC_DEBUG_7_new_prim_MASK | \ + SC_DEBUG_7_load_new_tile_data_MASK | \ + SC_DEBUG_7_state_MASK | \ + SC_DEBUG_7_fifos_ready_MASK | \ + SC_DEBUG_7_trigger_MASK) + +#define SC_DEBUG_7(event_flag, deallocate, fpos, sr_prim_we, last_tile, tile_ff_we, qs_data_valid, qs_q0_y, qs_q0_x, qs_q0_valid, prim_ff_we, tile_ff_re, fw_prim_data_valid, last_quad_of_tile, first_quad_of_tile, first_quad_of_prim, new_prim, load_new_tile_data, state, fifos_ready, trigger) \ + ((event_flag << SC_DEBUG_7_event_flag_SHIFT) | \ + (deallocate << SC_DEBUG_7_deallocate_SHIFT) | \ + (fpos << SC_DEBUG_7_fpos_SHIFT) | \ + (sr_prim_we << SC_DEBUG_7_sr_prim_we_SHIFT) | \ + (last_tile << SC_DEBUG_7_last_tile_SHIFT) | \ + (tile_ff_we << SC_DEBUG_7_tile_ff_we_SHIFT) | \ + (qs_data_valid << SC_DEBUG_7_qs_data_valid_SHIFT) | \ + (qs_q0_y << SC_DEBUG_7_qs_q0_y_SHIFT) | \ + (qs_q0_x << SC_DEBUG_7_qs_q0_x_SHIFT) | \ + (qs_q0_valid << SC_DEBUG_7_qs_q0_valid_SHIFT) | \ + (prim_ff_we << SC_DEBUG_7_prim_ff_we_SHIFT) | \ + (tile_ff_re << SC_DEBUG_7_tile_ff_re_SHIFT) | \ + (fw_prim_data_valid << SC_DEBUG_7_fw_prim_data_valid_SHIFT) | \ + (last_quad_of_tile << SC_DEBUG_7_last_quad_of_tile_SHIFT) | \ + (first_quad_of_tile << SC_DEBUG_7_first_quad_of_tile_SHIFT) | \ + (first_quad_of_prim << SC_DEBUG_7_first_quad_of_prim_SHIFT) | \ + (new_prim << SC_DEBUG_7_new_prim_SHIFT) | \ + (load_new_tile_data << SC_DEBUG_7_load_new_tile_data_SHIFT) | \ + (state << SC_DEBUG_7_state_SHIFT) | \ + (fifos_ready << SC_DEBUG_7_fifos_ready_SHIFT) | \ + (trigger << SC_DEBUG_7_trigger_SHIFT)) + +#define SC_DEBUG_7_GET_event_flag(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_event_flag_MASK) >> SC_DEBUG_7_event_flag_SHIFT) +#define SC_DEBUG_7_GET_deallocate(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_deallocate_MASK) >> SC_DEBUG_7_deallocate_SHIFT) +#define SC_DEBUG_7_GET_fpos(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_fpos_MASK) >> SC_DEBUG_7_fpos_SHIFT) +#define SC_DEBUG_7_GET_sr_prim_we(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_sr_prim_we_MASK) >> SC_DEBUG_7_sr_prim_we_SHIFT) +#define SC_DEBUG_7_GET_last_tile(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_last_tile_MASK) >> SC_DEBUG_7_last_tile_SHIFT) +#define SC_DEBUG_7_GET_tile_ff_we(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_tile_ff_we_MASK) >> SC_DEBUG_7_tile_ff_we_SHIFT) +#define SC_DEBUG_7_GET_qs_data_valid(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_qs_data_valid_MASK) >> SC_DEBUG_7_qs_data_valid_SHIFT) +#define SC_DEBUG_7_GET_qs_q0_y(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_qs_q0_y_MASK) >> SC_DEBUG_7_qs_q0_y_SHIFT) +#define SC_DEBUG_7_GET_qs_q0_x(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_qs_q0_x_MASK) >> SC_DEBUG_7_qs_q0_x_SHIFT) +#define SC_DEBUG_7_GET_qs_q0_valid(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_qs_q0_valid_MASK) >> SC_DEBUG_7_qs_q0_valid_SHIFT) +#define SC_DEBUG_7_GET_prim_ff_we(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_prim_ff_we_MASK) >> SC_DEBUG_7_prim_ff_we_SHIFT) +#define SC_DEBUG_7_GET_tile_ff_re(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_tile_ff_re_MASK) >> SC_DEBUG_7_tile_ff_re_SHIFT) +#define SC_DEBUG_7_GET_fw_prim_data_valid(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_fw_prim_data_valid_MASK) >> SC_DEBUG_7_fw_prim_data_valid_SHIFT) +#define SC_DEBUG_7_GET_last_quad_of_tile(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_last_quad_of_tile_MASK) >> SC_DEBUG_7_last_quad_of_tile_SHIFT) +#define SC_DEBUG_7_GET_first_quad_of_tile(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_first_quad_of_tile_MASK) >> SC_DEBUG_7_first_quad_of_tile_SHIFT) +#define SC_DEBUG_7_GET_first_quad_of_prim(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_first_quad_of_prim_MASK) >> SC_DEBUG_7_first_quad_of_prim_SHIFT) +#define SC_DEBUG_7_GET_new_prim(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_new_prim_MASK) >> SC_DEBUG_7_new_prim_SHIFT) +#define SC_DEBUG_7_GET_load_new_tile_data(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_load_new_tile_data_MASK) >> SC_DEBUG_7_load_new_tile_data_SHIFT) +#define SC_DEBUG_7_GET_state(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_state_MASK) >> SC_DEBUG_7_state_SHIFT) +#define SC_DEBUG_7_GET_fifos_ready(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_fifos_ready_MASK) >> SC_DEBUG_7_fifos_ready_SHIFT) +#define SC_DEBUG_7_GET_trigger(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_trigger_MASK) >> SC_DEBUG_7_trigger_SHIFT) + +#define SC_DEBUG_7_SET_event_flag(sc_debug_7_reg, event_flag) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_event_flag_MASK) | (event_flag << SC_DEBUG_7_event_flag_SHIFT) +#define SC_DEBUG_7_SET_deallocate(sc_debug_7_reg, deallocate) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_deallocate_MASK) | (deallocate << SC_DEBUG_7_deallocate_SHIFT) +#define SC_DEBUG_7_SET_fpos(sc_debug_7_reg, fpos) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fpos_MASK) | (fpos << SC_DEBUG_7_fpos_SHIFT) +#define SC_DEBUG_7_SET_sr_prim_we(sc_debug_7_reg, sr_prim_we) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_sr_prim_we_MASK) | (sr_prim_we << SC_DEBUG_7_sr_prim_we_SHIFT) +#define SC_DEBUG_7_SET_last_tile(sc_debug_7_reg, last_tile) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_last_tile_MASK) | (last_tile << SC_DEBUG_7_last_tile_SHIFT) +#define SC_DEBUG_7_SET_tile_ff_we(sc_debug_7_reg, tile_ff_we) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_tile_ff_we_MASK) | (tile_ff_we << SC_DEBUG_7_tile_ff_we_SHIFT) +#define SC_DEBUG_7_SET_qs_data_valid(sc_debug_7_reg, qs_data_valid) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_data_valid_MASK) | (qs_data_valid << SC_DEBUG_7_qs_data_valid_SHIFT) +#define SC_DEBUG_7_SET_qs_q0_y(sc_debug_7_reg, qs_q0_y) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_y_MASK) | (qs_q0_y << SC_DEBUG_7_qs_q0_y_SHIFT) +#define SC_DEBUG_7_SET_qs_q0_x(sc_debug_7_reg, qs_q0_x) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_x_MASK) | (qs_q0_x << SC_DEBUG_7_qs_q0_x_SHIFT) +#define SC_DEBUG_7_SET_qs_q0_valid(sc_debug_7_reg, qs_q0_valid) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_valid_MASK) | (qs_q0_valid << SC_DEBUG_7_qs_q0_valid_SHIFT) +#define SC_DEBUG_7_SET_prim_ff_we(sc_debug_7_reg, prim_ff_we) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_prim_ff_we_MASK) | (prim_ff_we << SC_DEBUG_7_prim_ff_we_SHIFT) +#define SC_DEBUG_7_SET_tile_ff_re(sc_debug_7_reg, tile_ff_re) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_tile_ff_re_MASK) | (tile_ff_re << SC_DEBUG_7_tile_ff_re_SHIFT) +#define SC_DEBUG_7_SET_fw_prim_data_valid(sc_debug_7_reg, fw_prim_data_valid) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fw_prim_data_valid_MASK) | (fw_prim_data_valid << SC_DEBUG_7_fw_prim_data_valid_SHIFT) +#define SC_DEBUG_7_SET_last_quad_of_tile(sc_debug_7_reg, last_quad_of_tile) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_last_quad_of_tile_MASK) | (last_quad_of_tile << SC_DEBUG_7_last_quad_of_tile_SHIFT) +#define SC_DEBUG_7_SET_first_quad_of_tile(sc_debug_7_reg, first_quad_of_tile) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_first_quad_of_tile_MASK) | (first_quad_of_tile << SC_DEBUG_7_first_quad_of_tile_SHIFT) +#define SC_DEBUG_7_SET_first_quad_of_prim(sc_debug_7_reg, first_quad_of_prim) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_first_quad_of_prim_MASK) | (first_quad_of_prim << SC_DEBUG_7_first_quad_of_prim_SHIFT) +#define SC_DEBUG_7_SET_new_prim(sc_debug_7_reg, new_prim) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_new_prim_MASK) | (new_prim << SC_DEBUG_7_new_prim_SHIFT) +#define SC_DEBUG_7_SET_load_new_tile_data(sc_debug_7_reg, load_new_tile_data) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_load_new_tile_data_MASK) | (load_new_tile_data << SC_DEBUG_7_load_new_tile_data_SHIFT) +#define SC_DEBUG_7_SET_state(sc_debug_7_reg, state) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_state_MASK) | (state << SC_DEBUG_7_state_SHIFT) +#define SC_DEBUG_7_SET_fifos_ready(sc_debug_7_reg, fifos_ready) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fifos_ready_MASK) | (fifos_ready << SC_DEBUG_7_fifos_ready_SHIFT) +#define SC_DEBUG_7_SET_trigger(sc_debug_7_reg, trigger) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_trigger_MASK) | (trigger << SC_DEBUG_7_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_7_t { + unsigned int event_flag : SC_DEBUG_7_event_flag_SIZE; + unsigned int deallocate : SC_DEBUG_7_deallocate_SIZE; + unsigned int fpos : SC_DEBUG_7_fpos_SIZE; + unsigned int sr_prim_we : SC_DEBUG_7_sr_prim_we_SIZE; + unsigned int last_tile : SC_DEBUG_7_last_tile_SIZE; + unsigned int tile_ff_we : SC_DEBUG_7_tile_ff_we_SIZE; + unsigned int qs_data_valid : SC_DEBUG_7_qs_data_valid_SIZE; + unsigned int qs_q0_y : SC_DEBUG_7_qs_q0_y_SIZE; + unsigned int qs_q0_x : SC_DEBUG_7_qs_q0_x_SIZE; + unsigned int qs_q0_valid : SC_DEBUG_7_qs_q0_valid_SIZE; + unsigned int prim_ff_we : SC_DEBUG_7_prim_ff_we_SIZE; + unsigned int tile_ff_re : SC_DEBUG_7_tile_ff_re_SIZE; + unsigned int fw_prim_data_valid : SC_DEBUG_7_fw_prim_data_valid_SIZE; + unsigned int last_quad_of_tile : SC_DEBUG_7_last_quad_of_tile_SIZE; + unsigned int first_quad_of_tile : SC_DEBUG_7_first_quad_of_tile_SIZE; + unsigned int first_quad_of_prim : SC_DEBUG_7_first_quad_of_prim_SIZE; + unsigned int new_prim : SC_DEBUG_7_new_prim_SIZE; + unsigned int load_new_tile_data : SC_DEBUG_7_load_new_tile_data_SIZE; + unsigned int state : SC_DEBUG_7_state_SIZE; + unsigned int fifos_ready : SC_DEBUG_7_fifos_ready_SIZE; + unsigned int : 6; + unsigned int trigger : SC_DEBUG_7_trigger_SIZE; + } sc_debug_7_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_7_t { + unsigned int trigger : SC_DEBUG_7_trigger_SIZE; + unsigned int : 6; + unsigned int fifos_ready : SC_DEBUG_7_fifos_ready_SIZE; + unsigned int state : SC_DEBUG_7_state_SIZE; + unsigned int load_new_tile_data : SC_DEBUG_7_load_new_tile_data_SIZE; + unsigned int new_prim : SC_DEBUG_7_new_prim_SIZE; + unsigned int first_quad_of_prim : SC_DEBUG_7_first_quad_of_prim_SIZE; + unsigned int first_quad_of_tile : SC_DEBUG_7_first_quad_of_tile_SIZE; + unsigned int last_quad_of_tile : SC_DEBUG_7_last_quad_of_tile_SIZE; + unsigned int fw_prim_data_valid : SC_DEBUG_7_fw_prim_data_valid_SIZE; + unsigned int tile_ff_re : SC_DEBUG_7_tile_ff_re_SIZE; + unsigned int prim_ff_we : SC_DEBUG_7_prim_ff_we_SIZE; + unsigned int qs_q0_valid : SC_DEBUG_7_qs_q0_valid_SIZE; + unsigned int qs_q0_x : SC_DEBUG_7_qs_q0_x_SIZE; + unsigned int qs_q0_y : SC_DEBUG_7_qs_q0_y_SIZE; + unsigned int qs_data_valid : SC_DEBUG_7_qs_data_valid_SIZE; + unsigned int tile_ff_we : SC_DEBUG_7_tile_ff_we_SIZE; + unsigned int last_tile : SC_DEBUG_7_last_tile_SIZE; + unsigned int sr_prim_we : SC_DEBUG_7_sr_prim_we_SIZE; + unsigned int fpos : SC_DEBUG_7_fpos_SIZE; + unsigned int deallocate : SC_DEBUG_7_deallocate_SIZE; + unsigned int event_flag : SC_DEBUG_7_event_flag_SIZE; + } sc_debug_7_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_7_t f; +} sc_debug_7_u; + + +/* + * SC_DEBUG_8 struct + */ + +#define SC_DEBUG_8_sample_last_SIZE 1 +#define SC_DEBUG_8_sample_mask_SIZE 4 +#define SC_DEBUG_8_sample_y_SIZE 2 +#define SC_DEBUG_8_sample_x_SIZE 2 +#define SC_DEBUG_8_sample_send_SIZE 1 +#define SC_DEBUG_8_next_cycle_SIZE 2 +#define SC_DEBUG_8_ez_sample_ff_full_SIZE 1 +#define SC_DEBUG_8_rb_sc_samp_rtr_SIZE 1 +#define SC_DEBUG_8_num_samples_SIZE 2 +#define SC_DEBUG_8_last_quad_of_tile_SIZE 1 +#define SC_DEBUG_8_last_quad_of_prim_SIZE 1 +#define SC_DEBUG_8_first_quad_of_prim_SIZE 1 +#define SC_DEBUG_8_sample_we_SIZE 1 +#define SC_DEBUG_8_fpos_SIZE 1 +#define SC_DEBUG_8_event_id_SIZE 5 +#define SC_DEBUG_8_event_flag_SIZE 1 +#define SC_DEBUG_8_fw_prim_data_valid_SIZE 1 +#define SC_DEBUG_8_trigger_SIZE 1 + +#define SC_DEBUG_8_sample_last_SHIFT 0 +#define SC_DEBUG_8_sample_mask_SHIFT 1 +#define SC_DEBUG_8_sample_y_SHIFT 5 +#define SC_DEBUG_8_sample_x_SHIFT 7 +#define SC_DEBUG_8_sample_send_SHIFT 9 +#define SC_DEBUG_8_next_cycle_SHIFT 10 +#define SC_DEBUG_8_ez_sample_ff_full_SHIFT 12 +#define SC_DEBUG_8_rb_sc_samp_rtr_SHIFT 13 +#define SC_DEBUG_8_num_samples_SHIFT 14 +#define SC_DEBUG_8_last_quad_of_tile_SHIFT 16 +#define SC_DEBUG_8_last_quad_of_prim_SHIFT 17 +#define SC_DEBUG_8_first_quad_of_prim_SHIFT 18 +#define SC_DEBUG_8_sample_we_SHIFT 19 +#define SC_DEBUG_8_fpos_SHIFT 20 +#define SC_DEBUG_8_event_id_SHIFT 21 +#define SC_DEBUG_8_event_flag_SHIFT 26 +#define SC_DEBUG_8_fw_prim_data_valid_SHIFT 27 +#define SC_DEBUG_8_trigger_SHIFT 31 + +#define SC_DEBUG_8_sample_last_MASK 0x00000001 +#define SC_DEBUG_8_sample_mask_MASK 0x0000001e +#define SC_DEBUG_8_sample_y_MASK 0x00000060 +#define SC_DEBUG_8_sample_x_MASK 0x00000180 +#define SC_DEBUG_8_sample_send_MASK 0x00000200 +#define SC_DEBUG_8_next_cycle_MASK 0x00000c00 +#define SC_DEBUG_8_ez_sample_ff_full_MASK 0x00001000 +#define SC_DEBUG_8_rb_sc_samp_rtr_MASK 0x00002000 +#define SC_DEBUG_8_num_samples_MASK 0x0000c000 +#define SC_DEBUG_8_last_quad_of_tile_MASK 0x00010000 +#define SC_DEBUG_8_last_quad_of_prim_MASK 0x00020000 +#define SC_DEBUG_8_first_quad_of_prim_MASK 0x00040000 +#define SC_DEBUG_8_sample_we_MASK 0x00080000 +#define SC_DEBUG_8_fpos_MASK 0x00100000 +#define SC_DEBUG_8_event_id_MASK 0x03e00000 +#define SC_DEBUG_8_event_flag_MASK 0x04000000 +#define SC_DEBUG_8_fw_prim_data_valid_MASK 0x08000000 +#define SC_DEBUG_8_trigger_MASK 0x80000000 + +#define SC_DEBUG_8_MASK \ + (SC_DEBUG_8_sample_last_MASK | \ + SC_DEBUG_8_sample_mask_MASK | \ + SC_DEBUG_8_sample_y_MASK | \ + SC_DEBUG_8_sample_x_MASK | \ + SC_DEBUG_8_sample_send_MASK | \ + SC_DEBUG_8_next_cycle_MASK | \ + SC_DEBUG_8_ez_sample_ff_full_MASK | \ + SC_DEBUG_8_rb_sc_samp_rtr_MASK | \ + SC_DEBUG_8_num_samples_MASK | \ + SC_DEBUG_8_last_quad_of_tile_MASK | \ + SC_DEBUG_8_last_quad_of_prim_MASK | \ + SC_DEBUG_8_first_quad_of_prim_MASK | \ + SC_DEBUG_8_sample_we_MASK | \ + SC_DEBUG_8_fpos_MASK | \ + SC_DEBUG_8_event_id_MASK | \ + SC_DEBUG_8_event_flag_MASK | \ + SC_DEBUG_8_fw_prim_data_valid_MASK | \ + SC_DEBUG_8_trigger_MASK) + +#define SC_DEBUG_8(sample_last, sample_mask, sample_y, sample_x, sample_send, next_cycle, ez_sample_ff_full, rb_sc_samp_rtr, num_samples, last_quad_of_tile, last_quad_of_prim, first_quad_of_prim, sample_we, fpos, event_id, event_flag, fw_prim_data_valid, trigger) \ + ((sample_last << SC_DEBUG_8_sample_last_SHIFT) | \ + (sample_mask << SC_DEBUG_8_sample_mask_SHIFT) | \ + (sample_y << SC_DEBUG_8_sample_y_SHIFT) | \ + (sample_x << SC_DEBUG_8_sample_x_SHIFT) | \ + (sample_send << SC_DEBUG_8_sample_send_SHIFT) | \ + (next_cycle << SC_DEBUG_8_next_cycle_SHIFT) | \ + (ez_sample_ff_full << SC_DEBUG_8_ez_sample_ff_full_SHIFT) | \ + (rb_sc_samp_rtr << SC_DEBUG_8_rb_sc_samp_rtr_SHIFT) | \ + (num_samples << SC_DEBUG_8_num_samples_SHIFT) | \ + (last_quad_of_tile << SC_DEBUG_8_last_quad_of_tile_SHIFT) | \ + (last_quad_of_prim << SC_DEBUG_8_last_quad_of_prim_SHIFT) | \ + (first_quad_of_prim << SC_DEBUG_8_first_quad_of_prim_SHIFT) | \ + (sample_we << SC_DEBUG_8_sample_we_SHIFT) | \ + (fpos << SC_DEBUG_8_fpos_SHIFT) | \ + (event_id << SC_DEBUG_8_event_id_SHIFT) | \ + (event_flag << SC_DEBUG_8_event_flag_SHIFT) | \ + (fw_prim_data_valid << SC_DEBUG_8_fw_prim_data_valid_SHIFT) | \ + (trigger << SC_DEBUG_8_trigger_SHIFT)) + +#define SC_DEBUG_8_GET_sample_last(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_last_MASK) >> SC_DEBUG_8_sample_last_SHIFT) +#define SC_DEBUG_8_GET_sample_mask(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_mask_MASK) >> SC_DEBUG_8_sample_mask_SHIFT) +#define SC_DEBUG_8_GET_sample_y(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_y_MASK) >> SC_DEBUG_8_sample_y_SHIFT) +#define SC_DEBUG_8_GET_sample_x(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_x_MASK) >> SC_DEBUG_8_sample_x_SHIFT) +#define SC_DEBUG_8_GET_sample_send(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_send_MASK) >> SC_DEBUG_8_sample_send_SHIFT) +#define SC_DEBUG_8_GET_next_cycle(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_next_cycle_MASK) >> SC_DEBUG_8_next_cycle_SHIFT) +#define SC_DEBUG_8_GET_ez_sample_ff_full(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_ez_sample_ff_full_MASK) >> SC_DEBUG_8_ez_sample_ff_full_SHIFT) +#define SC_DEBUG_8_GET_rb_sc_samp_rtr(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_rb_sc_samp_rtr_MASK) >> SC_DEBUG_8_rb_sc_samp_rtr_SHIFT) +#define SC_DEBUG_8_GET_num_samples(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_num_samples_MASK) >> SC_DEBUG_8_num_samples_SHIFT) +#define SC_DEBUG_8_GET_last_quad_of_tile(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_last_quad_of_tile_MASK) >> SC_DEBUG_8_last_quad_of_tile_SHIFT) +#define SC_DEBUG_8_GET_last_quad_of_prim(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_last_quad_of_prim_MASK) >> SC_DEBUG_8_last_quad_of_prim_SHIFT) +#define SC_DEBUG_8_GET_first_quad_of_prim(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_first_quad_of_prim_MASK) >> SC_DEBUG_8_first_quad_of_prim_SHIFT) +#define SC_DEBUG_8_GET_sample_we(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_we_MASK) >> SC_DEBUG_8_sample_we_SHIFT) +#define SC_DEBUG_8_GET_fpos(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_fpos_MASK) >> SC_DEBUG_8_fpos_SHIFT) +#define SC_DEBUG_8_GET_event_id(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_event_id_MASK) >> SC_DEBUG_8_event_id_SHIFT) +#define SC_DEBUG_8_GET_event_flag(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_event_flag_MASK) >> SC_DEBUG_8_event_flag_SHIFT) +#define SC_DEBUG_8_GET_fw_prim_data_valid(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_fw_prim_data_valid_MASK) >> SC_DEBUG_8_fw_prim_data_valid_SHIFT) +#define SC_DEBUG_8_GET_trigger(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_trigger_MASK) >> SC_DEBUG_8_trigger_SHIFT) + +#define SC_DEBUG_8_SET_sample_last(sc_debug_8_reg, sample_last) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_last_MASK) | (sample_last << SC_DEBUG_8_sample_last_SHIFT) +#define SC_DEBUG_8_SET_sample_mask(sc_debug_8_reg, sample_mask) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_mask_MASK) | (sample_mask << SC_DEBUG_8_sample_mask_SHIFT) +#define SC_DEBUG_8_SET_sample_y(sc_debug_8_reg, sample_y) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_y_MASK) | (sample_y << SC_DEBUG_8_sample_y_SHIFT) +#define SC_DEBUG_8_SET_sample_x(sc_debug_8_reg, sample_x) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_x_MASK) | (sample_x << SC_DEBUG_8_sample_x_SHIFT) +#define SC_DEBUG_8_SET_sample_send(sc_debug_8_reg, sample_send) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_send_MASK) | (sample_send << SC_DEBUG_8_sample_send_SHIFT) +#define SC_DEBUG_8_SET_next_cycle(sc_debug_8_reg, next_cycle) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_next_cycle_MASK) | (next_cycle << SC_DEBUG_8_next_cycle_SHIFT) +#define SC_DEBUG_8_SET_ez_sample_ff_full(sc_debug_8_reg, ez_sample_ff_full) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_ez_sample_ff_full_MASK) | (ez_sample_ff_full << SC_DEBUG_8_ez_sample_ff_full_SHIFT) +#define SC_DEBUG_8_SET_rb_sc_samp_rtr(sc_debug_8_reg, rb_sc_samp_rtr) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_rb_sc_samp_rtr_MASK) | (rb_sc_samp_rtr << SC_DEBUG_8_rb_sc_samp_rtr_SHIFT) +#define SC_DEBUG_8_SET_num_samples(sc_debug_8_reg, num_samples) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_num_samples_MASK) | (num_samples << SC_DEBUG_8_num_samples_SHIFT) +#define SC_DEBUG_8_SET_last_quad_of_tile(sc_debug_8_reg, last_quad_of_tile) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_last_quad_of_tile_MASK) | (last_quad_of_tile << SC_DEBUG_8_last_quad_of_tile_SHIFT) +#define SC_DEBUG_8_SET_last_quad_of_prim(sc_debug_8_reg, last_quad_of_prim) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_last_quad_of_prim_MASK) | (last_quad_of_prim << SC_DEBUG_8_last_quad_of_prim_SHIFT) +#define SC_DEBUG_8_SET_first_quad_of_prim(sc_debug_8_reg, first_quad_of_prim) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_first_quad_of_prim_MASK) | (first_quad_of_prim << SC_DEBUG_8_first_quad_of_prim_SHIFT) +#define SC_DEBUG_8_SET_sample_we(sc_debug_8_reg, sample_we) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_we_MASK) | (sample_we << SC_DEBUG_8_sample_we_SHIFT) +#define SC_DEBUG_8_SET_fpos(sc_debug_8_reg, fpos) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_fpos_MASK) | (fpos << SC_DEBUG_8_fpos_SHIFT) +#define SC_DEBUG_8_SET_event_id(sc_debug_8_reg, event_id) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_event_id_MASK) | (event_id << SC_DEBUG_8_event_id_SHIFT) +#define SC_DEBUG_8_SET_event_flag(sc_debug_8_reg, event_flag) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_event_flag_MASK) | (event_flag << SC_DEBUG_8_event_flag_SHIFT) +#define SC_DEBUG_8_SET_fw_prim_data_valid(sc_debug_8_reg, fw_prim_data_valid) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_fw_prim_data_valid_MASK) | (fw_prim_data_valid << SC_DEBUG_8_fw_prim_data_valid_SHIFT) +#define SC_DEBUG_8_SET_trigger(sc_debug_8_reg, trigger) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_trigger_MASK) | (trigger << SC_DEBUG_8_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_8_t { + unsigned int sample_last : SC_DEBUG_8_sample_last_SIZE; + unsigned int sample_mask : SC_DEBUG_8_sample_mask_SIZE; + unsigned int sample_y : SC_DEBUG_8_sample_y_SIZE; + unsigned int sample_x : SC_DEBUG_8_sample_x_SIZE; + unsigned int sample_send : SC_DEBUG_8_sample_send_SIZE; + unsigned int next_cycle : SC_DEBUG_8_next_cycle_SIZE; + unsigned int ez_sample_ff_full : SC_DEBUG_8_ez_sample_ff_full_SIZE; + unsigned int rb_sc_samp_rtr : SC_DEBUG_8_rb_sc_samp_rtr_SIZE; + unsigned int num_samples : SC_DEBUG_8_num_samples_SIZE; + unsigned int last_quad_of_tile : SC_DEBUG_8_last_quad_of_tile_SIZE; + unsigned int last_quad_of_prim : SC_DEBUG_8_last_quad_of_prim_SIZE; + unsigned int first_quad_of_prim : SC_DEBUG_8_first_quad_of_prim_SIZE; + unsigned int sample_we : SC_DEBUG_8_sample_we_SIZE; + unsigned int fpos : SC_DEBUG_8_fpos_SIZE; + unsigned int event_id : SC_DEBUG_8_event_id_SIZE; + unsigned int event_flag : SC_DEBUG_8_event_flag_SIZE; + unsigned int fw_prim_data_valid : SC_DEBUG_8_fw_prim_data_valid_SIZE; + unsigned int : 3; + unsigned int trigger : SC_DEBUG_8_trigger_SIZE; + } sc_debug_8_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_8_t { + unsigned int trigger : SC_DEBUG_8_trigger_SIZE; + unsigned int : 3; + unsigned int fw_prim_data_valid : SC_DEBUG_8_fw_prim_data_valid_SIZE; + unsigned int event_flag : SC_DEBUG_8_event_flag_SIZE; + unsigned int event_id : SC_DEBUG_8_event_id_SIZE; + unsigned int fpos : SC_DEBUG_8_fpos_SIZE; + unsigned int sample_we : SC_DEBUG_8_sample_we_SIZE; + unsigned int first_quad_of_prim : SC_DEBUG_8_first_quad_of_prim_SIZE; + unsigned int last_quad_of_prim : SC_DEBUG_8_last_quad_of_prim_SIZE; + unsigned int last_quad_of_tile : SC_DEBUG_8_last_quad_of_tile_SIZE; + unsigned int num_samples : SC_DEBUG_8_num_samples_SIZE; + unsigned int rb_sc_samp_rtr : SC_DEBUG_8_rb_sc_samp_rtr_SIZE; + unsigned int ez_sample_ff_full : SC_DEBUG_8_ez_sample_ff_full_SIZE; + unsigned int next_cycle : SC_DEBUG_8_next_cycle_SIZE; + unsigned int sample_send : SC_DEBUG_8_sample_send_SIZE; + unsigned int sample_x : SC_DEBUG_8_sample_x_SIZE; + unsigned int sample_y : SC_DEBUG_8_sample_y_SIZE; + unsigned int sample_mask : SC_DEBUG_8_sample_mask_SIZE; + unsigned int sample_last : SC_DEBUG_8_sample_last_SIZE; + } sc_debug_8_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_8_t f; +} sc_debug_8_u; + + +/* + * SC_DEBUG_9 struct + */ + +#define SC_DEBUG_9_rb_sc_send_SIZE 1 +#define SC_DEBUG_9_rb_sc_ez_mask_SIZE 4 +#define SC_DEBUG_9_fifo_data_ready_SIZE 1 +#define SC_DEBUG_9_early_z_enable_SIZE 1 +#define SC_DEBUG_9_mask_state_SIZE 2 +#define SC_DEBUG_9_next_ez_mask_SIZE 16 +#define SC_DEBUG_9_mask_ready_SIZE 1 +#define SC_DEBUG_9_drop_sample_SIZE 1 +#define SC_DEBUG_9_fetch_new_sample_data_SIZE 1 +#define SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE 1 +#define SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE 1 +#define SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE 1 +#define SC_DEBUG_9_trigger_SIZE 1 + +#define SC_DEBUG_9_rb_sc_send_SHIFT 0 +#define SC_DEBUG_9_rb_sc_ez_mask_SHIFT 1 +#define SC_DEBUG_9_fifo_data_ready_SHIFT 5 +#define SC_DEBUG_9_early_z_enable_SHIFT 6 +#define SC_DEBUG_9_mask_state_SHIFT 7 +#define SC_DEBUG_9_next_ez_mask_SHIFT 9 +#define SC_DEBUG_9_mask_ready_SHIFT 25 +#define SC_DEBUG_9_drop_sample_SHIFT 26 +#define SC_DEBUG_9_fetch_new_sample_data_SHIFT 27 +#define SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT 28 +#define SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT 29 +#define SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT 30 +#define SC_DEBUG_9_trigger_SHIFT 31 + +#define SC_DEBUG_9_rb_sc_send_MASK 0x00000001 +#define SC_DEBUG_9_rb_sc_ez_mask_MASK 0x0000001e +#define SC_DEBUG_9_fifo_data_ready_MASK 0x00000020 +#define SC_DEBUG_9_early_z_enable_MASK 0x00000040 +#define SC_DEBUG_9_mask_state_MASK 0x00000180 +#define SC_DEBUG_9_next_ez_mask_MASK 0x01fffe00 +#define SC_DEBUG_9_mask_ready_MASK 0x02000000 +#define SC_DEBUG_9_drop_sample_MASK 0x04000000 +#define SC_DEBUG_9_fetch_new_sample_data_MASK 0x08000000 +#define SC_DEBUG_9_fetch_new_ez_sample_mask_MASK 0x10000000 +#define SC_DEBUG_9_pkr_fetch_new_sample_data_MASK 0x20000000 +#define SC_DEBUG_9_pkr_fetch_new_prim_data_MASK 0x40000000 +#define SC_DEBUG_9_trigger_MASK 0x80000000 + +#define SC_DEBUG_9_MASK \ + (SC_DEBUG_9_rb_sc_send_MASK | \ + SC_DEBUG_9_rb_sc_ez_mask_MASK | \ + SC_DEBUG_9_fifo_data_ready_MASK | \ + SC_DEBUG_9_early_z_enable_MASK | \ + SC_DEBUG_9_mask_state_MASK | \ + SC_DEBUG_9_next_ez_mask_MASK | \ + SC_DEBUG_9_mask_ready_MASK | \ + SC_DEBUG_9_drop_sample_MASK | \ + SC_DEBUG_9_fetch_new_sample_data_MASK | \ + SC_DEBUG_9_fetch_new_ez_sample_mask_MASK | \ + SC_DEBUG_9_pkr_fetch_new_sample_data_MASK | \ + SC_DEBUG_9_pkr_fetch_new_prim_data_MASK | \ + SC_DEBUG_9_trigger_MASK) + +#define SC_DEBUG_9(rb_sc_send, rb_sc_ez_mask, fifo_data_ready, early_z_enable, mask_state, next_ez_mask, mask_ready, drop_sample, fetch_new_sample_data, fetch_new_ez_sample_mask, pkr_fetch_new_sample_data, pkr_fetch_new_prim_data, trigger) \ + ((rb_sc_send << SC_DEBUG_9_rb_sc_send_SHIFT) | \ + (rb_sc_ez_mask << SC_DEBUG_9_rb_sc_ez_mask_SHIFT) | \ + (fifo_data_ready << SC_DEBUG_9_fifo_data_ready_SHIFT) | \ + (early_z_enable << SC_DEBUG_9_early_z_enable_SHIFT) | \ + (mask_state << SC_DEBUG_9_mask_state_SHIFT) | \ + (next_ez_mask << SC_DEBUG_9_next_ez_mask_SHIFT) | \ + (mask_ready << SC_DEBUG_9_mask_ready_SHIFT) | \ + (drop_sample << SC_DEBUG_9_drop_sample_SHIFT) | \ + (fetch_new_sample_data << SC_DEBUG_9_fetch_new_sample_data_SHIFT) | \ + (fetch_new_ez_sample_mask << SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT) | \ + (pkr_fetch_new_sample_data << SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT) | \ + (pkr_fetch_new_prim_data << SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT) | \ + (trigger << SC_DEBUG_9_trigger_SHIFT)) + +#define SC_DEBUG_9_GET_rb_sc_send(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_rb_sc_send_MASK) >> SC_DEBUG_9_rb_sc_send_SHIFT) +#define SC_DEBUG_9_GET_rb_sc_ez_mask(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_rb_sc_ez_mask_MASK) >> SC_DEBUG_9_rb_sc_ez_mask_SHIFT) +#define SC_DEBUG_9_GET_fifo_data_ready(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_fifo_data_ready_MASK) >> SC_DEBUG_9_fifo_data_ready_SHIFT) +#define SC_DEBUG_9_GET_early_z_enable(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_early_z_enable_MASK) >> SC_DEBUG_9_early_z_enable_SHIFT) +#define SC_DEBUG_9_GET_mask_state(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_mask_state_MASK) >> SC_DEBUG_9_mask_state_SHIFT) +#define SC_DEBUG_9_GET_next_ez_mask(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_next_ez_mask_MASK) >> SC_DEBUG_9_next_ez_mask_SHIFT) +#define SC_DEBUG_9_GET_mask_ready(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_mask_ready_MASK) >> SC_DEBUG_9_mask_ready_SHIFT) +#define SC_DEBUG_9_GET_drop_sample(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_drop_sample_MASK) >> SC_DEBUG_9_drop_sample_SHIFT) +#define SC_DEBUG_9_GET_fetch_new_sample_data(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_fetch_new_sample_data_MASK) >> SC_DEBUG_9_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_9_GET_fetch_new_ez_sample_mask(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_fetch_new_ez_sample_mask_MASK) >> SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT) +#define SC_DEBUG_9_GET_pkr_fetch_new_sample_data(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_pkr_fetch_new_sample_data_MASK) >> SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_9_GET_pkr_fetch_new_prim_data(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_pkr_fetch_new_prim_data_MASK) >> SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT) +#define SC_DEBUG_9_GET_trigger(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_trigger_MASK) >> SC_DEBUG_9_trigger_SHIFT) + +#define SC_DEBUG_9_SET_rb_sc_send(sc_debug_9_reg, rb_sc_send) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_rb_sc_send_MASK) | (rb_sc_send << SC_DEBUG_9_rb_sc_send_SHIFT) +#define SC_DEBUG_9_SET_rb_sc_ez_mask(sc_debug_9_reg, rb_sc_ez_mask) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_rb_sc_ez_mask_MASK) | (rb_sc_ez_mask << SC_DEBUG_9_rb_sc_ez_mask_SHIFT) +#define SC_DEBUG_9_SET_fifo_data_ready(sc_debug_9_reg, fifo_data_ready) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fifo_data_ready_MASK) | (fifo_data_ready << SC_DEBUG_9_fifo_data_ready_SHIFT) +#define SC_DEBUG_9_SET_early_z_enable(sc_debug_9_reg, early_z_enable) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_early_z_enable_MASK) | (early_z_enable << SC_DEBUG_9_early_z_enable_SHIFT) +#define SC_DEBUG_9_SET_mask_state(sc_debug_9_reg, mask_state) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_mask_state_MASK) | (mask_state << SC_DEBUG_9_mask_state_SHIFT) +#define SC_DEBUG_9_SET_next_ez_mask(sc_debug_9_reg, next_ez_mask) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_next_ez_mask_MASK) | (next_ez_mask << SC_DEBUG_9_next_ez_mask_SHIFT) +#define SC_DEBUG_9_SET_mask_ready(sc_debug_9_reg, mask_ready) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_mask_ready_MASK) | (mask_ready << SC_DEBUG_9_mask_ready_SHIFT) +#define SC_DEBUG_9_SET_drop_sample(sc_debug_9_reg, drop_sample) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_drop_sample_MASK) | (drop_sample << SC_DEBUG_9_drop_sample_SHIFT) +#define SC_DEBUG_9_SET_fetch_new_sample_data(sc_debug_9_reg, fetch_new_sample_data) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fetch_new_sample_data_MASK) | (fetch_new_sample_data << SC_DEBUG_9_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_9_SET_fetch_new_ez_sample_mask(sc_debug_9_reg, fetch_new_ez_sample_mask) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fetch_new_ez_sample_mask_MASK) | (fetch_new_ez_sample_mask << SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT) +#define SC_DEBUG_9_SET_pkr_fetch_new_sample_data(sc_debug_9_reg, pkr_fetch_new_sample_data) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_pkr_fetch_new_sample_data_MASK) | (pkr_fetch_new_sample_data << SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_9_SET_pkr_fetch_new_prim_data(sc_debug_9_reg, pkr_fetch_new_prim_data) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_pkr_fetch_new_prim_data_MASK) | (pkr_fetch_new_prim_data << SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT) +#define SC_DEBUG_9_SET_trigger(sc_debug_9_reg, trigger) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_trigger_MASK) | (trigger << SC_DEBUG_9_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_9_t { + unsigned int rb_sc_send : SC_DEBUG_9_rb_sc_send_SIZE; + unsigned int rb_sc_ez_mask : SC_DEBUG_9_rb_sc_ez_mask_SIZE; + unsigned int fifo_data_ready : SC_DEBUG_9_fifo_data_ready_SIZE; + unsigned int early_z_enable : SC_DEBUG_9_early_z_enable_SIZE; + unsigned int mask_state : SC_DEBUG_9_mask_state_SIZE; + unsigned int next_ez_mask : SC_DEBUG_9_next_ez_mask_SIZE; + unsigned int mask_ready : SC_DEBUG_9_mask_ready_SIZE; + unsigned int drop_sample : SC_DEBUG_9_drop_sample_SIZE; + unsigned int fetch_new_sample_data : SC_DEBUG_9_fetch_new_sample_data_SIZE; + unsigned int fetch_new_ez_sample_mask : SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE; + unsigned int pkr_fetch_new_sample_data : SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE; + unsigned int pkr_fetch_new_prim_data : SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE; + unsigned int trigger : SC_DEBUG_9_trigger_SIZE; + } sc_debug_9_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_9_t { + unsigned int trigger : SC_DEBUG_9_trigger_SIZE; + unsigned int pkr_fetch_new_prim_data : SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE; + unsigned int pkr_fetch_new_sample_data : SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE; + unsigned int fetch_new_ez_sample_mask : SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE; + unsigned int fetch_new_sample_data : SC_DEBUG_9_fetch_new_sample_data_SIZE; + unsigned int drop_sample : SC_DEBUG_9_drop_sample_SIZE; + unsigned int mask_ready : SC_DEBUG_9_mask_ready_SIZE; + unsigned int next_ez_mask : SC_DEBUG_9_next_ez_mask_SIZE; + unsigned int mask_state : SC_DEBUG_9_mask_state_SIZE; + unsigned int early_z_enable : SC_DEBUG_9_early_z_enable_SIZE; + unsigned int fifo_data_ready : SC_DEBUG_9_fifo_data_ready_SIZE; + unsigned int rb_sc_ez_mask : SC_DEBUG_9_rb_sc_ez_mask_SIZE; + unsigned int rb_sc_send : SC_DEBUG_9_rb_sc_send_SIZE; + } sc_debug_9_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_9_t f; +} sc_debug_9_u; + + +/* + * SC_DEBUG_10 struct + */ + +#define SC_DEBUG_10_combined_sample_mask_SIZE 16 +#define SC_DEBUG_10_trigger_SIZE 1 + +#define SC_DEBUG_10_combined_sample_mask_SHIFT 0 +#define SC_DEBUG_10_trigger_SHIFT 31 + +#define SC_DEBUG_10_combined_sample_mask_MASK 0x0000ffff +#define SC_DEBUG_10_trigger_MASK 0x80000000 + +#define SC_DEBUG_10_MASK \ + (SC_DEBUG_10_combined_sample_mask_MASK | \ + SC_DEBUG_10_trigger_MASK) + +#define SC_DEBUG_10(combined_sample_mask, trigger) \ + ((combined_sample_mask << SC_DEBUG_10_combined_sample_mask_SHIFT) | \ + (trigger << SC_DEBUG_10_trigger_SHIFT)) + +#define SC_DEBUG_10_GET_combined_sample_mask(sc_debug_10) \ + ((sc_debug_10 & SC_DEBUG_10_combined_sample_mask_MASK) >> SC_DEBUG_10_combined_sample_mask_SHIFT) +#define SC_DEBUG_10_GET_trigger(sc_debug_10) \ + ((sc_debug_10 & SC_DEBUG_10_trigger_MASK) >> SC_DEBUG_10_trigger_SHIFT) + +#define SC_DEBUG_10_SET_combined_sample_mask(sc_debug_10_reg, combined_sample_mask) \ + sc_debug_10_reg = (sc_debug_10_reg & ~SC_DEBUG_10_combined_sample_mask_MASK) | (combined_sample_mask << SC_DEBUG_10_combined_sample_mask_SHIFT) +#define SC_DEBUG_10_SET_trigger(sc_debug_10_reg, trigger) \ + sc_debug_10_reg = (sc_debug_10_reg & ~SC_DEBUG_10_trigger_MASK) | (trigger << SC_DEBUG_10_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_10_t { + unsigned int combined_sample_mask : SC_DEBUG_10_combined_sample_mask_SIZE; + unsigned int : 15; + unsigned int trigger : SC_DEBUG_10_trigger_SIZE; + } sc_debug_10_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_10_t { + unsigned int trigger : SC_DEBUG_10_trigger_SIZE; + unsigned int : 15; + unsigned int combined_sample_mask : SC_DEBUG_10_combined_sample_mask_SIZE; + } sc_debug_10_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_10_t f; +} sc_debug_10_u; + + +/* + * SC_DEBUG_11 struct + */ + +#define SC_DEBUG_11_ez_sample_data_ready_SIZE 1 +#define SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE 1 +#define SC_DEBUG_11_ez_prim_data_ready_SIZE 1 +#define SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE 1 +#define SC_DEBUG_11_iterator_input_fz_SIZE 1 +#define SC_DEBUG_11_packer_send_quads_SIZE 1 +#define SC_DEBUG_11_packer_send_cmd_SIZE 1 +#define SC_DEBUG_11_packer_send_event_SIZE 1 +#define SC_DEBUG_11_next_state_SIZE 3 +#define SC_DEBUG_11_state_SIZE 3 +#define SC_DEBUG_11_stall_SIZE 1 +#define SC_DEBUG_11_trigger_SIZE 1 + +#define SC_DEBUG_11_ez_sample_data_ready_SHIFT 0 +#define SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT 1 +#define SC_DEBUG_11_ez_prim_data_ready_SHIFT 2 +#define SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT 3 +#define SC_DEBUG_11_iterator_input_fz_SHIFT 4 +#define SC_DEBUG_11_packer_send_quads_SHIFT 5 +#define SC_DEBUG_11_packer_send_cmd_SHIFT 6 +#define SC_DEBUG_11_packer_send_event_SHIFT 7 +#define SC_DEBUG_11_next_state_SHIFT 8 +#define SC_DEBUG_11_state_SHIFT 11 +#define SC_DEBUG_11_stall_SHIFT 14 +#define SC_DEBUG_11_trigger_SHIFT 31 + +#define SC_DEBUG_11_ez_sample_data_ready_MASK 0x00000001 +#define SC_DEBUG_11_pkr_fetch_new_sample_data_MASK 0x00000002 +#define SC_DEBUG_11_ez_prim_data_ready_MASK 0x00000004 +#define SC_DEBUG_11_pkr_fetch_new_prim_data_MASK 0x00000008 +#define SC_DEBUG_11_iterator_input_fz_MASK 0x00000010 +#define SC_DEBUG_11_packer_send_quads_MASK 0x00000020 +#define SC_DEBUG_11_packer_send_cmd_MASK 0x00000040 +#define SC_DEBUG_11_packer_send_event_MASK 0x00000080 +#define SC_DEBUG_11_next_state_MASK 0x00000700 +#define SC_DEBUG_11_state_MASK 0x00003800 +#define SC_DEBUG_11_stall_MASK 0x00004000 +#define SC_DEBUG_11_trigger_MASK 0x80000000 + +#define SC_DEBUG_11_MASK \ + (SC_DEBUG_11_ez_sample_data_ready_MASK | \ + SC_DEBUG_11_pkr_fetch_new_sample_data_MASK | \ + SC_DEBUG_11_ez_prim_data_ready_MASK | \ + SC_DEBUG_11_pkr_fetch_new_prim_data_MASK | \ + SC_DEBUG_11_iterator_input_fz_MASK | \ + SC_DEBUG_11_packer_send_quads_MASK | \ + SC_DEBUG_11_packer_send_cmd_MASK | \ + SC_DEBUG_11_packer_send_event_MASK | \ + SC_DEBUG_11_next_state_MASK | \ + SC_DEBUG_11_state_MASK | \ + SC_DEBUG_11_stall_MASK | \ + SC_DEBUG_11_trigger_MASK) + +#define SC_DEBUG_11(ez_sample_data_ready, pkr_fetch_new_sample_data, ez_prim_data_ready, pkr_fetch_new_prim_data, iterator_input_fz, packer_send_quads, packer_send_cmd, packer_send_event, next_state, state, stall, trigger) \ + ((ez_sample_data_ready << SC_DEBUG_11_ez_sample_data_ready_SHIFT) | \ + (pkr_fetch_new_sample_data << SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT) | \ + (ez_prim_data_ready << SC_DEBUG_11_ez_prim_data_ready_SHIFT) | \ + (pkr_fetch_new_prim_data << SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT) | \ + (iterator_input_fz << SC_DEBUG_11_iterator_input_fz_SHIFT) | \ + (packer_send_quads << SC_DEBUG_11_packer_send_quads_SHIFT) | \ + (packer_send_cmd << SC_DEBUG_11_packer_send_cmd_SHIFT) | \ + (packer_send_event << SC_DEBUG_11_packer_send_event_SHIFT) | \ + (next_state << SC_DEBUG_11_next_state_SHIFT) | \ + (state << SC_DEBUG_11_state_SHIFT) | \ + (stall << SC_DEBUG_11_stall_SHIFT) | \ + (trigger << SC_DEBUG_11_trigger_SHIFT)) + +#define SC_DEBUG_11_GET_ez_sample_data_ready(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_ez_sample_data_ready_MASK) >> SC_DEBUG_11_ez_sample_data_ready_SHIFT) +#define SC_DEBUG_11_GET_pkr_fetch_new_sample_data(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_pkr_fetch_new_sample_data_MASK) >> SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_11_GET_ez_prim_data_ready(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_ez_prim_data_ready_MASK) >> SC_DEBUG_11_ez_prim_data_ready_SHIFT) +#define SC_DEBUG_11_GET_pkr_fetch_new_prim_data(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_pkr_fetch_new_prim_data_MASK) >> SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT) +#define SC_DEBUG_11_GET_iterator_input_fz(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_iterator_input_fz_MASK) >> SC_DEBUG_11_iterator_input_fz_SHIFT) +#define SC_DEBUG_11_GET_packer_send_quads(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_packer_send_quads_MASK) >> SC_DEBUG_11_packer_send_quads_SHIFT) +#define SC_DEBUG_11_GET_packer_send_cmd(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_packer_send_cmd_MASK) >> SC_DEBUG_11_packer_send_cmd_SHIFT) +#define SC_DEBUG_11_GET_packer_send_event(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_packer_send_event_MASK) >> SC_DEBUG_11_packer_send_event_SHIFT) +#define SC_DEBUG_11_GET_next_state(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_next_state_MASK) >> SC_DEBUG_11_next_state_SHIFT) +#define SC_DEBUG_11_GET_state(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_state_MASK) >> SC_DEBUG_11_state_SHIFT) +#define SC_DEBUG_11_GET_stall(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_stall_MASK) >> SC_DEBUG_11_stall_SHIFT) +#define SC_DEBUG_11_GET_trigger(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_trigger_MASK) >> SC_DEBUG_11_trigger_SHIFT) + +#define SC_DEBUG_11_SET_ez_sample_data_ready(sc_debug_11_reg, ez_sample_data_ready) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_ez_sample_data_ready_MASK) | (ez_sample_data_ready << SC_DEBUG_11_ez_sample_data_ready_SHIFT) +#define SC_DEBUG_11_SET_pkr_fetch_new_sample_data(sc_debug_11_reg, pkr_fetch_new_sample_data) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_pkr_fetch_new_sample_data_MASK) | (pkr_fetch_new_sample_data << SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_11_SET_ez_prim_data_ready(sc_debug_11_reg, ez_prim_data_ready) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_ez_prim_data_ready_MASK) | (ez_prim_data_ready << SC_DEBUG_11_ez_prim_data_ready_SHIFT) +#define SC_DEBUG_11_SET_pkr_fetch_new_prim_data(sc_debug_11_reg, pkr_fetch_new_prim_data) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_pkr_fetch_new_prim_data_MASK) | (pkr_fetch_new_prim_data << SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT) +#define SC_DEBUG_11_SET_iterator_input_fz(sc_debug_11_reg, iterator_input_fz) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_iterator_input_fz_MASK) | (iterator_input_fz << SC_DEBUG_11_iterator_input_fz_SHIFT) +#define SC_DEBUG_11_SET_packer_send_quads(sc_debug_11_reg, packer_send_quads) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_quads_MASK) | (packer_send_quads << SC_DEBUG_11_packer_send_quads_SHIFT) +#define SC_DEBUG_11_SET_packer_send_cmd(sc_debug_11_reg, packer_send_cmd) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_cmd_MASK) | (packer_send_cmd << SC_DEBUG_11_packer_send_cmd_SHIFT) +#define SC_DEBUG_11_SET_packer_send_event(sc_debug_11_reg, packer_send_event) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_event_MASK) | (packer_send_event << SC_DEBUG_11_packer_send_event_SHIFT) +#define SC_DEBUG_11_SET_next_state(sc_debug_11_reg, next_state) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_next_state_MASK) | (next_state << SC_DEBUG_11_next_state_SHIFT) +#define SC_DEBUG_11_SET_state(sc_debug_11_reg, state) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_state_MASK) | (state << SC_DEBUG_11_state_SHIFT) +#define SC_DEBUG_11_SET_stall(sc_debug_11_reg, stall) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_stall_MASK) | (stall << SC_DEBUG_11_stall_SHIFT) +#define SC_DEBUG_11_SET_trigger(sc_debug_11_reg, trigger) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_trigger_MASK) | (trigger << SC_DEBUG_11_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_11_t { + unsigned int ez_sample_data_ready : SC_DEBUG_11_ez_sample_data_ready_SIZE; + unsigned int pkr_fetch_new_sample_data : SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE; + unsigned int ez_prim_data_ready : SC_DEBUG_11_ez_prim_data_ready_SIZE; + unsigned int pkr_fetch_new_prim_data : SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE; + unsigned int iterator_input_fz : SC_DEBUG_11_iterator_input_fz_SIZE; + unsigned int packer_send_quads : SC_DEBUG_11_packer_send_quads_SIZE; + unsigned int packer_send_cmd : SC_DEBUG_11_packer_send_cmd_SIZE; + unsigned int packer_send_event : SC_DEBUG_11_packer_send_event_SIZE; + unsigned int next_state : SC_DEBUG_11_next_state_SIZE; + unsigned int state : SC_DEBUG_11_state_SIZE; + unsigned int stall : SC_DEBUG_11_stall_SIZE; + unsigned int : 16; + unsigned int trigger : SC_DEBUG_11_trigger_SIZE; + } sc_debug_11_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_11_t { + unsigned int trigger : SC_DEBUG_11_trigger_SIZE; + unsigned int : 16; + unsigned int stall : SC_DEBUG_11_stall_SIZE; + unsigned int state : SC_DEBUG_11_state_SIZE; + unsigned int next_state : SC_DEBUG_11_next_state_SIZE; + unsigned int packer_send_event : SC_DEBUG_11_packer_send_event_SIZE; + unsigned int packer_send_cmd : SC_DEBUG_11_packer_send_cmd_SIZE; + unsigned int packer_send_quads : SC_DEBUG_11_packer_send_quads_SIZE; + unsigned int iterator_input_fz : SC_DEBUG_11_iterator_input_fz_SIZE; + unsigned int pkr_fetch_new_prim_data : SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE; + unsigned int ez_prim_data_ready : SC_DEBUG_11_ez_prim_data_ready_SIZE; + unsigned int pkr_fetch_new_sample_data : SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE; + unsigned int ez_sample_data_ready : SC_DEBUG_11_ez_sample_data_ready_SIZE; + } sc_debug_11_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_11_t f; +} sc_debug_11_u; + + +/* + * SC_DEBUG_12 struct + */ + +#define SC_DEBUG_12_SQ_iterator_free_buff_SIZE 1 +#define SC_DEBUG_12_event_id_SIZE 5 +#define SC_DEBUG_12_event_flag_SIZE 1 +#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE 1 +#define SC_DEBUG_12_itercmdfifo_full_SIZE 1 +#define SC_DEBUG_12_itercmdfifo_empty_SIZE 1 +#define SC_DEBUG_12_iter_ds_one_clk_command_SIZE 1 +#define SC_DEBUG_12_iter_ds_end_of_prim0_SIZE 1 +#define SC_DEBUG_12_iter_ds_end_of_vector_SIZE 1 +#define SC_DEBUG_12_iter_qdhit0_SIZE 1 +#define SC_DEBUG_12_bc_use_centers_reg_SIZE 1 +#define SC_DEBUG_12_bc_output_xy_reg_SIZE 1 +#define SC_DEBUG_12_iter_phase_out_SIZE 2 +#define SC_DEBUG_12_iter_phase_reg_SIZE 2 +#define SC_DEBUG_12_iterator_SP_valid_SIZE 1 +#define SC_DEBUG_12_eopv_reg_SIZE 1 +#define SC_DEBUG_12_one_clk_cmd_reg_SIZE 1 +#define SC_DEBUG_12_iter_dx_end_of_prim_SIZE 1 +#define SC_DEBUG_12_trigger_SIZE 1 + +#define SC_DEBUG_12_SQ_iterator_free_buff_SHIFT 0 +#define SC_DEBUG_12_event_id_SHIFT 1 +#define SC_DEBUG_12_event_flag_SHIFT 6 +#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT 7 +#define SC_DEBUG_12_itercmdfifo_full_SHIFT 8 +#define SC_DEBUG_12_itercmdfifo_empty_SHIFT 9 +#define SC_DEBUG_12_iter_ds_one_clk_command_SHIFT 10 +#define SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT 11 +#define SC_DEBUG_12_iter_ds_end_of_vector_SHIFT 12 +#define SC_DEBUG_12_iter_qdhit0_SHIFT 13 +#define SC_DEBUG_12_bc_use_centers_reg_SHIFT 14 +#define SC_DEBUG_12_bc_output_xy_reg_SHIFT 15 +#define SC_DEBUG_12_iter_phase_out_SHIFT 16 +#define SC_DEBUG_12_iter_phase_reg_SHIFT 18 +#define SC_DEBUG_12_iterator_SP_valid_SHIFT 20 +#define SC_DEBUG_12_eopv_reg_SHIFT 21 +#define SC_DEBUG_12_one_clk_cmd_reg_SHIFT 22 +#define SC_DEBUG_12_iter_dx_end_of_prim_SHIFT 23 +#define SC_DEBUG_12_trigger_SHIFT 31 + +#define SC_DEBUG_12_SQ_iterator_free_buff_MASK 0x00000001 +#define SC_DEBUG_12_event_id_MASK 0x0000003e +#define SC_DEBUG_12_event_flag_MASK 0x00000040 +#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK 0x00000080 +#define SC_DEBUG_12_itercmdfifo_full_MASK 0x00000100 +#define SC_DEBUG_12_itercmdfifo_empty_MASK 0x00000200 +#define SC_DEBUG_12_iter_ds_one_clk_command_MASK 0x00000400 +#define SC_DEBUG_12_iter_ds_end_of_prim0_MASK 0x00000800 +#define SC_DEBUG_12_iter_ds_end_of_vector_MASK 0x00001000 +#define SC_DEBUG_12_iter_qdhit0_MASK 0x00002000 +#define SC_DEBUG_12_bc_use_centers_reg_MASK 0x00004000 +#define SC_DEBUG_12_bc_output_xy_reg_MASK 0x00008000 +#define SC_DEBUG_12_iter_phase_out_MASK 0x00030000 +#define SC_DEBUG_12_iter_phase_reg_MASK 0x000c0000 +#define SC_DEBUG_12_iterator_SP_valid_MASK 0x00100000 +#define SC_DEBUG_12_eopv_reg_MASK 0x00200000 +#define SC_DEBUG_12_one_clk_cmd_reg_MASK 0x00400000 +#define SC_DEBUG_12_iter_dx_end_of_prim_MASK 0x00800000 +#define SC_DEBUG_12_trigger_MASK 0x80000000 + +#define SC_DEBUG_12_MASK \ + (SC_DEBUG_12_SQ_iterator_free_buff_MASK | \ + SC_DEBUG_12_event_id_MASK | \ + SC_DEBUG_12_event_flag_MASK | \ + SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK | \ + SC_DEBUG_12_itercmdfifo_full_MASK | \ + SC_DEBUG_12_itercmdfifo_empty_MASK | \ + SC_DEBUG_12_iter_ds_one_clk_command_MASK | \ + SC_DEBUG_12_iter_ds_end_of_prim0_MASK | \ + SC_DEBUG_12_iter_ds_end_of_vector_MASK | \ + SC_DEBUG_12_iter_qdhit0_MASK | \ + SC_DEBUG_12_bc_use_centers_reg_MASK | \ + SC_DEBUG_12_bc_output_xy_reg_MASK | \ + SC_DEBUG_12_iter_phase_out_MASK | \ + SC_DEBUG_12_iter_phase_reg_MASK | \ + SC_DEBUG_12_iterator_SP_valid_MASK | \ + SC_DEBUG_12_eopv_reg_MASK | \ + SC_DEBUG_12_one_clk_cmd_reg_MASK | \ + SC_DEBUG_12_iter_dx_end_of_prim_MASK | \ + SC_DEBUG_12_trigger_MASK) + +#define SC_DEBUG_12(sq_iterator_free_buff, event_id, event_flag, itercmdfifo_busy_nc_dly, itercmdfifo_full, itercmdfifo_empty, iter_ds_one_clk_command, iter_ds_end_of_prim0, iter_ds_end_of_vector, iter_qdhit0, bc_use_centers_reg, bc_output_xy_reg, iter_phase_out, iter_phase_reg, iterator_sp_valid, eopv_reg, one_clk_cmd_reg, iter_dx_end_of_prim, trigger) \ + ((sq_iterator_free_buff << SC_DEBUG_12_SQ_iterator_free_buff_SHIFT) | \ + (event_id << SC_DEBUG_12_event_id_SHIFT) | \ + (event_flag << SC_DEBUG_12_event_flag_SHIFT) | \ + (itercmdfifo_busy_nc_dly << SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT) | \ + (itercmdfifo_full << SC_DEBUG_12_itercmdfifo_full_SHIFT) | \ + (itercmdfifo_empty << SC_DEBUG_12_itercmdfifo_empty_SHIFT) | \ + (iter_ds_one_clk_command << SC_DEBUG_12_iter_ds_one_clk_command_SHIFT) | \ + (iter_ds_end_of_prim0 << SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT) | \ + (iter_ds_end_of_vector << SC_DEBUG_12_iter_ds_end_of_vector_SHIFT) | \ + (iter_qdhit0 << SC_DEBUG_12_iter_qdhit0_SHIFT) | \ + (bc_use_centers_reg << SC_DEBUG_12_bc_use_centers_reg_SHIFT) | \ + (bc_output_xy_reg << SC_DEBUG_12_bc_output_xy_reg_SHIFT) | \ + (iter_phase_out << SC_DEBUG_12_iter_phase_out_SHIFT) | \ + (iter_phase_reg << SC_DEBUG_12_iter_phase_reg_SHIFT) | \ + (iterator_sp_valid << SC_DEBUG_12_iterator_SP_valid_SHIFT) | \ + (eopv_reg << SC_DEBUG_12_eopv_reg_SHIFT) | \ + (one_clk_cmd_reg << SC_DEBUG_12_one_clk_cmd_reg_SHIFT) | \ + (iter_dx_end_of_prim << SC_DEBUG_12_iter_dx_end_of_prim_SHIFT) | \ + (trigger << SC_DEBUG_12_trigger_SHIFT)) + +#define SC_DEBUG_12_GET_SQ_iterator_free_buff(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_SQ_iterator_free_buff_MASK) >> SC_DEBUG_12_SQ_iterator_free_buff_SHIFT) +#define SC_DEBUG_12_GET_event_id(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_event_id_MASK) >> SC_DEBUG_12_event_id_SHIFT) +#define SC_DEBUG_12_GET_event_flag(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_event_flag_MASK) >> SC_DEBUG_12_event_flag_SHIFT) +#define SC_DEBUG_12_GET_itercmdfifo_busy_nc_dly(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK) >> SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT) +#define SC_DEBUG_12_GET_itercmdfifo_full(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_full_MASK) >> SC_DEBUG_12_itercmdfifo_full_SHIFT) +#define SC_DEBUG_12_GET_itercmdfifo_empty(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_empty_MASK) >> SC_DEBUG_12_itercmdfifo_empty_SHIFT) +#define SC_DEBUG_12_GET_iter_ds_one_clk_command(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_ds_one_clk_command_MASK) >> SC_DEBUG_12_iter_ds_one_clk_command_SHIFT) +#define SC_DEBUG_12_GET_iter_ds_end_of_prim0(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_ds_end_of_prim0_MASK) >> SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT) +#define SC_DEBUG_12_GET_iter_ds_end_of_vector(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_ds_end_of_vector_MASK) >> SC_DEBUG_12_iter_ds_end_of_vector_SHIFT) +#define SC_DEBUG_12_GET_iter_qdhit0(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_qdhit0_MASK) >> SC_DEBUG_12_iter_qdhit0_SHIFT) +#define SC_DEBUG_12_GET_bc_use_centers_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_bc_use_centers_reg_MASK) >> SC_DEBUG_12_bc_use_centers_reg_SHIFT) +#define SC_DEBUG_12_GET_bc_output_xy_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_bc_output_xy_reg_MASK) >> SC_DEBUG_12_bc_output_xy_reg_SHIFT) +#define SC_DEBUG_12_GET_iter_phase_out(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_phase_out_MASK) >> SC_DEBUG_12_iter_phase_out_SHIFT) +#define SC_DEBUG_12_GET_iter_phase_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_phase_reg_MASK) >> SC_DEBUG_12_iter_phase_reg_SHIFT) +#define SC_DEBUG_12_GET_iterator_SP_valid(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iterator_SP_valid_MASK) >> SC_DEBUG_12_iterator_SP_valid_SHIFT) +#define SC_DEBUG_12_GET_eopv_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_eopv_reg_MASK) >> SC_DEBUG_12_eopv_reg_SHIFT) +#define SC_DEBUG_12_GET_one_clk_cmd_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_one_clk_cmd_reg_MASK) >> SC_DEBUG_12_one_clk_cmd_reg_SHIFT) +#define SC_DEBUG_12_GET_iter_dx_end_of_prim(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_dx_end_of_prim_MASK) >> SC_DEBUG_12_iter_dx_end_of_prim_SHIFT) +#define SC_DEBUG_12_GET_trigger(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_trigger_MASK) >> SC_DEBUG_12_trigger_SHIFT) + +#define SC_DEBUG_12_SET_SQ_iterator_free_buff(sc_debug_12_reg, sq_iterator_free_buff) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_SQ_iterator_free_buff_MASK) | (sq_iterator_free_buff << SC_DEBUG_12_SQ_iterator_free_buff_SHIFT) +#define SC_DEBUG_12_SET_event_id(sc_debug_12_reg, event_id) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_event_id_MASK) | (event_id << SC_DEBUG_12_event_id_SHIFT) +#define SC_DEBUG_12_SET_event_flag(sc_debug_12_reg, event_flag) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_event_flag_MASK) | (event_flag << SC_DEBUG_12_event_flag_SHIFT) +#define SC_DEBUG_12_SET_itercmdfifo_busy_nc_dly(sc_debug_12_reg, itercmdfifo_busy_nc_dly) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK) | (itercmdfifo_busy_nc_dly << SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT) +#define SC_DEBUG_12_SET_itercmdfifo_full(sc_debug_12_reg, itercmdfifo_full) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_full_MASK) | (itercmdfifo_full << SC_DEBUG_12_itercmdfifo_full_SHIFT) +#define SC_DEBUG_12_SET_itercmdfifo_empty(sc_debug_12_reg, itercmdfifo_empty) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_empty_MASK) | (itercmdfifo_empty << SC_DEBUG_12_itercmdfifo_empty_SHIFT) +#define SC_DEBUG_12_SET_iter_ds_one_clk_command(sc_debug_12_reg, iter_ds_one_clk_command) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_one_clk_command_MASK) | (iter_ds_one_clk_command << SC_DEBUG_12_iter_ds_one_clk_command_SHIFT) +#define SC_DEBUG_12_SET_iter_ds_end_of_prim0(sc_debug_12_reg, iter_ds_end_of_prim0) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_end_of_prim0_MASK) | (iter_ds_end_of_prim0 << SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT) +#define SC_DEBUG_12_SET_iter_ds_end_of_vector(sc_debug_12_reg, iter_ds_end_of_vector) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_end_of_vector_MASK) | (iter_ds_end_of_vector << SC_DEBUG_12_iter_ds_end_of_vector_SHIFT) +#define SC_DEBUG_12_SET_iter_qdhit0(sc_debug_12_reg, iter_qdhit0) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_qdhit0_MASK) | (iter_qdhit0 << SC_DEBUG_12_iter_qdhit0_SHIFT) +#define SC_DEBUG_12_SET_bc_use_centers_reg(sc_debug_12_reg, bc_use_centers_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_bc_use_centers_reg_MASK) | (bc_use_centers_reg << SC_DEBUG_12_bc_use_centers_reg_SHIFT) +#define SC_DEBUG_12_SET_bc_output_xy_reg(sc_debug_12_reg, bc_output_xy_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_bc_output_xy_reg_MASK) | (bc_output_xy_reg << SC_DEBUG_12_bc_output_xy_reg_SHIFT) +#define SC_DEBUG_12_SET_iter_phase_out(sc_debug_12_reg, iter_phase_out) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_phase_out_MASK) | (iter_phase_out << SC_DEBUG_12_iter_phase_out_SHIFT) +#define SC_DEBUG_12_SET_iter_phase_reg(sc_debug_12_reg, iter_phase_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_phase_reg_MASK) | (iter_phase_reg << SC_DEBUG_12_iter_phase_reg_SHIFT) +#define SC_DEBUG_12_SET_iterator_SP_valid(sc_debug_12_reg, iterator_sp_valid) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iterator_SP_valid_MASK) | (iterator_sp_valid << SC_DEBUG_12_iterator_SP_valid_SHIFT) +#define SC_DEBUG_12_SET_eopv_reg(sc_debug_12_reg, eopv_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_eopv_reg_MASK) | (eopv_reg << SC_DEBUG_12_eopv_reg_SHIFT) +#define SC_DEBUG_12_SET_one_clk_cmd_reg(sc_debug_12_reg, one_clk_cmd_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_one_clk_cmd_reg_MASK) | (one_clk_cmd_reg << SC_DEBUG_12_one_clk_cmd_reg_SHIFT) +#define SC_DEBUG_12_SET_iter_dx_end_of_prim(sc_debug_12_reg, iter_dx_end_of_prim) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_dx_end_of_prim_MASK) | (iter_dx_end_of_prim << SC_DEBUG_12_iter_dx_end_of_prim_SHIFT) +#define SC_DEBUG_12_SET_trigger(sc_debug_12_reg, trigger) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_trigger_MASK) | (trigger << SC_DEBUG_12_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_12_t { + unsigned int sq_iterator_free_buff : SC_DEBUG_12_SQ_iterator_free_buff_SIZE; + unsigned int event_id : SC_DEBUG_12_event_id_SIZE; + unsigned int event_flag : SC_DEBUG_12_event_flag_SIZE; + unsigned int itercmdfifo_busy_nc_dly : SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE; + unsigned int itercmdfifo_full : SC_DEBUG_12_itercmdfifo_full_SIZE; + unsigned int itercmdfifo_empty : SC_DEBUG_12_itercmdfifo_empty_SIZE; + unsigned int iter_ds_one_clk_command : SC_DEBUG_12_iter_ds_one_clk_command_SIZE; + unsigned int iter_ds_end_of_prim0 : SC_DEBUG_12_iter_ds_end_of_prim0_SIZE; + unsigned int iter_ds_end_of_vector : SC_DEBUG_12_iter_ds_end_of_vector_SIZE; + unsigned int iter_qdhit0 : SC_DEBUG_12_iter_qdhit0_SIZE; + unsigned int bc_use_centers_reg : SC_DEBUG_12_bc_use_centers_reg_SIZE; + unsigned int bc_output_xy_reg : SC_DEBUG_12_bc_output_xy_reg_SIZE; + unsigned int iter_phase_out : SC_DEBUG_12_iter_phase_out_SIZE; + unsigned int iter_phase_reg : SC_DEBUG_12_iter_phase_reg_SIZE; + unsigned int iterator_sp_valid : SC_DEBUG_12_iterator_SP_valid_SIZE; + unsigned int eopv_reg : SC_DEBUG_12_eopv_reg_SIZE; + unsigned int one_clk_cmd_reg : SC_DEBUG_12_one_clk_cmd_reg_SIZE; + unsigned int iter_dx_end_of_prim : SC_DEBUG_12_iter_dx_end_of_prim_SIZE; + unsigned int : 7; + unsigned int trigger : SC_DEBUG_12_trigger_SIZE; + } sc_debug_12_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_12_t { + unsigned int trigger : SC_DEBUG_12_trigger_SIZE; + unsigned int : 7; + unsigned int iter_dx_end_of_prim : SC_DEBUG_12_iter_dx_end_of_prim_SIZE; + unsigned int one_clk_cmd_reg : SC_DEBUG_12_one_clk_cmd_reg_SIZE; + unsigned int eopv_reg : SC_DEBUG_12_eopv_reg_SIZE; + unsigned int iterator_sp_valid : SC_DEBUG_12_iterator_SP_valid_SIZE; + unsigned int iter_phase_reg : SC_DEBUG_12_iter_phase_reg_SIZE; + unsigned int iter_phase_out : SC_DEBUG_12_iter_phase_out_SIZE; + unsigned int bc_output_xy_reg : SC_DEBUG_12_bc_output_xy_reg_SIZE; + unsigned int bc_use_centers_reg : SC_DEBUG_12_bc_use_centers_reg_SIZE; + unsigned int iter_qdhit0 : SC_DEBUG_12_iter_qdhit0_SIZE; + unsigned int iter_ds_end_of_vector : SC_DEBUG_12_iter_ds_end_of_vector_SIZE; + unsigned int iter_ds_end_of_prim0 : SC_DEBUG_12_iter_ds_end_of_prim0_SIZE; + unsigned int iter_ds_one_clk_command : SC_DEBUG_12_iter_ds_one_clk_command_SIZE; + unsigned int itercmdfifo_empty : SC_DEBUG_12_itercmdfifo_empty_SIZE; + unsigned int itercmdfifo_full : SC_DEBUG_12_itercmdfifo_full_SIZE; + unsigned int itercmdfifo_busy_nc_dly : SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE; + unsigned int event_flag : SC_DEBUG_12_event_flag_SIZE; + unsigned int event_id : SC_DEBUG_12_event_id_SIZE; + unsigned int sq_iterator_free_buff : SC_DEBUG_12_SQ_iterator_free_buff_SIZE; + } sc_debug_12_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_12_t f; +} sc_debug_12_u; + + +#endif + + +#if !defined (_VGT_FIDDLE_H) +#define _VGT_FIDDLE_H + +/***************************************************************************************************************** + * + * vgt_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + +/* + * VGT_OUT_PRIM_TYPE enum + */ + +#define VGT_OUT_POINT 0x00000000 +#define VGT_OUT_LINE 0x00000001 +#define VGT_OUT_TRI 0x00000002 +#define VGT_OUT_RECT_V0 0x00000003 +#define VGT_OUT_RECT_V1 0x00000004 +#define VGT_OUT_RECT_V2 0x00000005 +#define VGT_OUT_RECT_V3 0x00000006 +#define VGT_OUT_RESERVED 0x00000007 +#define VGT_TE_QUAD 0x00000008 +#define VGT_TE_PRIM_INDEX_LINE 0x00000009 +#define VGT_TE_PRIM_INDEX_TRI 0x0000000a +#define VGT_TE_PRIM_INDEX_QUAD 0x0000000b + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * GFX_COPY_STATE struct + */ + +#define GFX_COPY_STATE_SRC_STATE_ID_SIZE 1 + +#define GFX_COPY_STATE_SRC_STATE_ID_SHIFT 0 + +#define GFX_COPY_STATE_SRC_STATE_ID_MASK 0x00000001 + +#define GFX_COPY_STATE_MASK \ + (GFX_COPY_STATE_SRC_STATE_ID_MASK) + +#define GFX_COPY_STATE(src_state_id) \ + ((src_state_id << GFX_COPY_STATE_SRC_STATE_ID_SHIFT)) + +#define GFX_COPY_STATE_GET_SRC_STATE_ID(gfx_copy_state) \ + ((gfx_copy_state & GFX_COPY_STATE_SRC_STATE_ID_MASK) >> GFX_COPY_STATE_SRC_STATE_ID_SHIFT) + +#define GFX_COPY_STATE_SET_SRC_STATE_ID(gfx_copy_state_reg, src_state_id) \ + gfx_copy_state_reg = (gfx_copy_state_reg & ~GFX_COPY_STATE_SRC_STATE_ID_MASK) | (src_state_id << GFX_COPY_STATE_SRC_STATE_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _gfx_copy_state_t { + unsigned int src_state_id : GFX_COPY_STATE_SRC_STATE_ID_SIZE; + unsigned int : 31; + } gfx_copy_state_t; + +#else // !BIGENDIAN_OS + + typedef struct _gfx_copy_state_t { + unsigned int : 31; + unsigned int src_state_id : GFX_COPY_STATE_SRC_STATE_ID_SIZE; + } gfx_copy_state_t; + +#endif + +typedef union { + unsigned int val : 32; + gfx_copy_state_t f; +} gfx_copy_state_u; + + +/* + * VGT_DRAW_INITIATOR struct + */ + +#define VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE 6 +#define VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE 2 +#define VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE 1 +#define VGT_DRAW_INITIATOR_NOT_EOP_SIZE 1 +#define VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE 1 +#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE 1 +#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE 1 +#define VGT_DRAW_INITIATOR_NUM_INDICES_SIZE 16 + +#define VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT 0 +#define VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT 6 +#define VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT 11 +#define VGT_DRAW_INITIATOR_NOT_EOP_SHIFT 12 +#define VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT 13 +#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT 14 +#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT 15 +#define VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT 16 + +#define VGT_DRAW_INITIATOR_PRIM_TYPE_MASK 0x0000003f +#define VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK 0x000000c0 +#define VGT_DRAW_INITIATOR_INDEX_SIZE_MASK 0x00000800 +#define VGT_DRAW_INITIATOR_NOT_EOP_MASK 0x00001000 +#define VGT_DRAW_INITIATOR_SMALL_INDEX_MASK 0x00002000 +#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK 0x00004000 +#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK 0x00008000 +#define VGT_DRAW_INITIATOR_NUM_INDICES_MASK 0xffff0000 + +#define VGT_DRAW_INITIATOR_MASK \ + (VGT_DRAW_INITIATOR_PRIM_TYPE_MASK | \ + VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK | \ + VGT_DRAW_INITIATOR_INDEX_SIZE_MASK | \ + VGT_DRAW_INITIATOR_NOT_EOP_MASK | \ + VGT_DRAW_INITIATOR_SMALL_INDEX_MASK | \ + VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK | \ + VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK | \ + VGT_DRAW_INITIATOR_NUM_INDICES_MASK) + +#define VGT_DRAW_INITIATOR(prim_type, source_select, index_size, not_eop, small_index, pre_fetch_cull_enable, grp_cull_enable, num_indices) \ + ((prim_type << VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT) | \ + (source_select << VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT) | \ + (index_size << VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT) | \ + (not_eop << VGT_DRAW_INITIATOR_NOT_EOP_SHIFT) | \ + (small_index << VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT) | \ + (pre_fetch_cull_enable << VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT) | \ + (grp_cull_enable << VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT) | \ + (num_indices << VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT)) + +#define VGT_DRAW_INITIATOR_GET_PRIM_TYPE(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_PRIM_TYPE_MASK) >> VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT) +#define VGT_DRAW_INITIATOR_GET_SOURCE_SELECT(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK) >> VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT) +#define VGT_DRAW_INITIATOR_GET_INDEX_SIZE(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_INDEX_SIZE_MASK) >> VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT) +#define VGT_DRAW_INITIATOR_GET_NOT_EOP(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_NOT_EOP_MASK) >> VGT_DRAW_INITIATOR_NOT_EOP_SHIFT) +#define VGT_DRAW_INITIATOR_GET_SMALL_INDEX(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_SMALL_INDEX_MASK) >> VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT) +#define VGT_DRAW_INITIATOR_GET_PRE_FETCH_CULL_ENABLE(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK) >> VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT) +#define VGT_DRAW_INITIATOR_GET_GRP_CULL_ENABLE(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK) >> VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT) +#define VGT_DRAW_INITIATOR_GET_NUM_INDICES(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_NUM_INDICES_MASK) >> VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT) + +#define VGT_DRAW_INITIATOR_SET_PRIM_TYPE(vgt_draw_initiator_reg, prim_type) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_PRIM_TYPE_MASK) | (prim_type << VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT) +#define VGT_DRAW_INITIATOR_SET_SOURCE_SELECT(vgt_draw_initiator_reg, source_select) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK) | (source_select << VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT) +#define VGT_DRAW_INITIATOR_SET_INDEX_SIZE(vgt_draw_initiator_reg, index_size) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_INDEX_SIZE_MASK) | (index_size << VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT) +#define VGT_DRAW_INITIATOR_SET_NOT_EOP(vgt_draw_initiator_reg, not_eop) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_NOT_EOP_MASK) | (not_eop << VGT_DRAW_INITIATOR_NOT_EOP_SHIFT) +#define VGT_DRAW_INITIATOR_SET_SMALL_INDEX(vgt_draw_initiator_reg, small_index) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_SMALL_INDEX_MASK) | (small_index << VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT) +#define VGT_DRAW_INITIATOR_SET_PRE_FETCH_CULL_ENABLE(vgt_draw_initiator_reg, pre_fetch_cull_enable) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK) | (pre_fetch_cull_enable << VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT) +#define VGT_DRAW_INITIATOR_SET_GRP_CULL_ENABLE(vgt_draw_initiator_reg, grp_cull_enable) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK) | (grp_cull_enable << VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT) +#define VGT_DRAW_INITIATOR_SET_NUM_INDICES(vgt_draw_initiator_reg, num_indices) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_NUM_INDICES_MASK) | (num_indices << VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_draw_initiator_t { + unsigned int prim_type : VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE; + unsigned int source_select : VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE; + unsigned int : 3; + unsigned int index_size : VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE; + unsigned int not_eop : VGT_DRAW_INITIATOR_NOT_EOP_SIZE; + unsigned int small_index : VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE; + unsigned int pre_fetch_cull_enable : VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE; + unsigned int grp_cull_enable : VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE; + unsigned int num_indices : VGT_DRAW_INITIATOR_NUM_INDICES_SIZE; + } vgt_draw_initiator_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_draw_initiator_t { + unsigned int num_indices : VGT_DRAW_INITIATOR_NUM_INDICES_SIZE; + unsigned int grp_cull_enable : VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE; + unsigned int pre_fetch_cull_enable : VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE; + unsigned int small_index : VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE; + unsigned int not_eop : VGT_DRAW_INITIATOR_NOT_EOP_SIZE; + unsigned int index_size : VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE; + unsigned int : 3; + unsigned int source_select : VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE; + unsigned int prim_type : VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE; + } vgt_draw_initiator_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_draw_initiator_t f; +} vgt_draw_initiator_u; + + +/* + * VGT_EVENT_INITIATOR struct + */ + +#define VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE 6 + +#define VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT 0 + +#define VGT_EVENT_INITIATOR_EVENT_TYPE_MASK 0x0000003f + +#define VGT_EVENT_INITIATOR_MASK \ + (VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) + +#define VGT_EVENT_INITIATOR(event_type) \ + ((event_type << VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT)) + +#define VGT_EVENT_INITIATOR_GET_EVENT_TYPE(vgt_event_initiator) \ + ((vgt_event_initiator & VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) >> VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT) + +#define VGT_EVENT_INITIATOR_SET_EVENT_TYPE(vgt_event_initiator_reg, event_type) \ + vgt_event_initiator_reg = (vgt_event_initiator_reg & ~VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) | (event_type << VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_event_initiator_t { + unsigned int event_type : VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE; + unsigned int : 26; + } vgt_event_initiator_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_event_initiator_t { + unsigned int : 26; + unsigned int event_type : VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE; + } vgt_event_initiator_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_event_initiator_t f; +} vgt_event_initiator_u; + + +/* + * VGT_DMA_BASE struct + */ + +#define VGT_DMA_BASE_BASE_ADDR_SIZE 32 + +#define VGT_DMA_BASE_BASE_ADDR_SHIFT 0 + +#define VGT_DMA_BASE_BASE_ADDR_MASK 0xffffffff + +#define VGT_DMA_BASE_MASK \ + (VGT_DMA_BASE_BASE_ADDR_MASK) + +#define VGT_DMA_BASE(base_addr) \ + ((base_addr << VGT_DMA_BASE_BASE_ADDR_SHIFT)) + +#define VGT_DMA_BASE_GET_BASE_ADDR(vgt_dma_base) \ + ((vgt_dma_base & VGT_DMA_BASE_BASE_ADDR_MASK) >> VGT_DMA_BASE_BASE_ADDR_SHIFT) + +#define VGT_DMA_BASE_SET_BASE_ADDR(vgt_dma_base_reg, base_addr) \ + vgt_dma_base_reg = (vgt_dma_base_reg & ~VGT_DMA_BASE_BASE_ADDR_MASK) | (base_addr << VGT_DMA_BASE_BASE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_dma_base_t { + unsigned int base_addr : VGT_DMA_BASE_BASE_ADDR_SIZE; + } vgt_dma_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_dma_base_t { + unsigned int base_addr : VGT_DMA_BASE_BASE_ADDR_SIZE; + } vgt_dma_base_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_dma_base_t f; +} vgt_dma_base_u; + + +/* + * VGT_DMA_SIZE struct + */ + +#define VGT_DMA_SIZE_NUM_WORDS_SIZE 24 +#define VGT_DMA_SIZE_SWAP_MODE_SIZE 2 + +#define VGT_DMA_SIZE_NUM_WORDS_SHIFT 0 +#define VGT_DMA_SIZE_SWAP_MODE_SHIFT 30 + +#define VGT_DMA_SIZE_NUM_WORDS_MASK 0x00ffffff +#define VGT_DMA_SIZE_SWAP_MODE_MASK 0xc0000000 + +#define VGT_DMA_SIZE_MASK \ + (VGT_DMA_SIZE_NUM_WORDS_MASK | \ + VGT_DMA_SIZE_SWAP_MODE_MASK) + +#define VGT_DMA_SIZE(num_words, swap_mode) \ + ((num_words << VGT_DMA_SIZE_NUM_WORDS_SHIFT) | \ + (swap_mode << VGT_DMA_SIZE_SWAP_MODE_SHIFT)) + +#define VGT_DMA_SIZE_GET_NUM_WORDS(vgt_dma_size) \ + ((vgt_dma_size & VGT_DMA_SIZE_NUM_WORDS_MASK) >> VGT_DMA_SIZE_NUM_WORDS_SHIFT) +#define VGT_DMA_SIZE_GET_SWAP_MODE(vgt_dma_size) \ + ((vgt_dma_size & VGT_DMA_SIZE_SWAP_MODE_MASK) >> VGT_DMA_SIZE_SWAP_MODE_SHIFT) + +#define VGT_DMA_SIZE_SET_NUM_WORDS(vgt_dma_size_reg, num_words) \ + vgt_dma_size_reg = (vgt_dma_size_reg & ~VGT_DMA_SIZE_NUM_WORDS_MASK) | (num_words << VGT_DMA_SIZE_NUM_WORDS_SHIFT) +#define VGT_DMA_SIZE_SET_SWAP_MODE(vgt_dma_size_reg, swap_mode) \ + vgt_dma_size_reg = (vgt_dma_size_reg & ~VGT_DMA_SIZE_SWAP_MODE_MASK) | (swap_mode << VGT_DMA_SIZE_SWAP_MODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_dma_size_t { + unsigned int num_words : VGT_DMA_SIZE_NUM_WORDS_SIZE; + unsigned int : 6; + unsigned int swap_mode : VGT_DMA_SIZE_SWAP_MODE_SIZE; + } vgt_dma_size_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_dma_size_t { + unsigned int swap_mode : VGT_DMA_SIZE_SWAP_MODE_SIZE; + unsigned int : 6; + unsigned int num_words : VGT_DMA_SIZE_NUM_WORDS_SIZE; + } vgt_dma_size_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_dma_size_t f; +} vgt_dma_size_u; + + +/* + * VGT_BIN_BASE struct + */ + +#define VGT_BIN_BASE_BIN_BASE_ADDR_SIZE 32 + +#define VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT 0 + +#define VGT_BIN_BASE_BIN_BASE_ADDR_MASK 0xffffffff + +#define VGT_BIN_BASE_MASK \ + (VGT_BIN_BASE_BIN_BASE_ADDR_MASK) + +#define VGT_BIN_BASE(bin_base_addr) \ + ((bin_base_addr << VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT)) + +#define VGT_BIN_BASE_GET_BIN_BASE_ADDR(vgt_bin_base) \ + ((vgt_bin_base & VGT_BIN_BASE_BIN_BASE_ADDR_MASK) >> VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT) + +#define VGT_BIN_BASE_SET_BIN_BASE_ADDR(vgt_bin_base_reg, bin_base_addr) \ + vgt_bin_base_reg = (vgt_bin_base_reg & ~VGT_BIN_BASE_BIN_BASE_ADDR_MASK) | (bin_base_addr << VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_bin_base_t { + unsigned int bin_base_addr : VGT_BIN_BASE_BIN_BASE_ADDR_SIZE; + } vgt_bin_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_bin_base_t { + unsigned int bin_base_addr : VGT_BIN_BASE_BIN_BASE_ADDR_SIZE; + } vgt_bin_base_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_bin_base_t f; +} vgt_bin_base_u; + + +/* + * VGT_BIN_SIZE struct + */ + +#define VGT_BIN_SIZE_NUM_WORDS_SIZE 24 + +#define VGT_BIN_SIZE_NUM_WORDS_SHIFT 0 + +#define VGT_BIN_SIZE_NUM_WORDS_MASK 0x00ffffff + +#define VGT_BIN_SIZE_MASK \ + (VGT_BIN_SIZE_NUM_WORDS_MASK) + +#define VGT_BIN_SIZE(num_words) \ + ((num_words << VGT_BIN_SIZE_NUM_WORDS_SHIFT)) + +#define VGT_BIN_SIZE_GET_NUM_WORDS(vgt_bin_size) \ + ((vgt_bin_size & VGT_BIN_SIZE_NUM_WORDS_MASK) >> VGT_BIN_SIZE_NUM_WORDS_SHIFT) + +#define VGT_BIN_SIZE_SET_NUM_WORDS(vgt_bin_size_reg, num_words) \ + vgt_bin_size_reg = (vgt_bin_size_reg & ~VGT_BIN_SIZE_NUM_WORDS_MASK) | (num_words << VGT_BIN_SIZE_NUM_WORDS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_bin_size_t { + unsigned int num_words : VGT_BIN_SIZE_NUM_WORDS_SIZE; + unsigned int : 8; + } vgt_bin_size_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_bin_size_t { + unsigned int : 8; + unsigned int num_words : VGT_BIN_SIZE_NUM_WORDS_SIZE; + } vgt_bin_size_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_bin_size_t f; +} vgt_bin_size_u; + + +/* + * VGT_CURRENT_BIN_ID_MIN struct + */ + +#define VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE 3 +#define VGT_CURRENT_BIN_ID_MIN_ROW_SIZE 3 +#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE 3 + +#define VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT 0 +#define VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT 3 +#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT 6 + +#define VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK 0x00000007 +#define VGT_CURRENT_BIN_ID_MIN_ROW_MASK 0x00000038 +#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK 0x000001c0 + +#define VGT_CURRENT_BIN_ID_MIN_MASK \ + (VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK | \ + VGT_CURRENT_BIN_ID_MIN_ROW_MASK | \ + VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) + +#define VGT_CURRENT_BIN_ID_MIN(column, row, guard_band) \ + ((column << VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT) | \ + (row << VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT) | \ + (guard_band << VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT)) + +#define VGT_CURRENT_BIN_ID_MIN_GET_COLUMN(vgt_current_bin_id_min) \ + ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK) >> VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT) +#define VGT_CURRENT_BIN_ID_MIN_GET_ROW(vgt_current_bin_id_min) \ + ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_ROW_MASK) >> VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT) +#define VGT_CURRENT_BIN_ID_MIN_GET_GUARD_BAND(vgt_current_bin_id_min) \ + ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) >> VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT) + +#define VGT_CURRENT_BIN_ID_MIN_SET_COLUMN(vgt_current_bin_id_min_reg, column) \ + vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK) | (column << VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT) +#define VGT_CURRENT_BIN_ID_MIN_SET_ROW(vgt_current_bin_id_min_reg, row) \ + vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_ROW_MASK) | (row << VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT) +#define VGT_CURRENT_BIN_ID_MIN_SET_GUARD_BAND(vgt_current_bin_id_min_reg, guard_band) \ + vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) | (guard_band << VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_current_bin_id_min_t { + unsigned int column : VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE; + unsigned int row : VGT_CURRENT_BIN_ID_MIN_ROW_SIZE; + unsigned int guard_band : VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE; + unsigned int : 23; + } vgt_current_bin_id_min_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_current_bin_id_min_t { + unsigned int : 23; + unsigned int guard_band : VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE; + unsigned int row : VGT_CURRENT_BIN_ID_MIN_ROW_SIZE; + unsigned int column : VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE; + } vgt_current_bin_id_min_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_current_bin_id_min_t f; +} vgt_current_bin_id_min_u; + + +/* + * VGT_CURRENT_BIN_ID_MAX struct + */ + +#define VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE 3 +#define VGT_CURRENT_BIN_ID_MAX_ROW_SIZE 3 +#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE 3 + +#define VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT 0 +#define VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT 3 +#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT 6 + +#define VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK 0x00000007 +#define VGT_CURRENT_BIN_ID_MAX_ROW_MASK 0x00000038 +#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK 0x000001c0 + +#define VGT_CURRENT_BIN_ID_MAX_MASK \ + (VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK | \ + VGT_CURRENT_BIN_ID_MAX_ROW_MASK | \ + VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) + +#define VGT_CURRENT_BIN_ID_MAX(column, row, guard_band) \ + ((column << VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT) | \ + (row << VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT) | \ + (guard_band << VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT)) + +#define VGT_CURRENT_BIN_ID_MAX_GET_COLUMN(vgt_current_bin_id_max) \ + ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK) >> VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT) +#define VGT_CURRENT_BIN_ID_MAX_GET_ROW(vgt_current_bin_id_max) \ + ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_ROW_MASK) >> VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT) +#define VGT_CURRENT_BIN_ID_MAX_GET_GUARD_BAND(vgt_current_bin_id_max) \ + ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) >> VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT) + +#define VGT_CURRENT_BIN_ID_MAX_SET_COLUMN(vgt_current_bin_id_max_reg, column) \ + vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK) | (column << VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT) +#define VGT_CURRENT_BIN_ID_MAX_SET_ROW(vgt_current_bin_id_max_reg, row) \ + vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_ROW_MASK) | (row << VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT) +#define VGT_CURRENT_BIN_ID_MAX_SET_GUARD_BAND(vgt_current_bin_id_max_reg, guard_band) \ + vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) | (guard_band << VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_current_bin_id_max_t { + unsigned int column : VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE; + unsigned int row : VGT_CURRENT_BIN_ID_MAX_ROW_SIZE; + unsigned int guard_band : VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE; + unsigned int : 23; + } vgt_current_bin_id_max_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_current_bin_id_max_t { + unsigned int : 23; + unsigned int guard_band : VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE; + unsigned int row : VGT_CURRENT_BIN_ID_MAX_ROW_SIZE; + unsigned int column : VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE; + } vgt_current_bin_id_max_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_current_bin_id_max_t f; +} vgt_current_bin_id_max_u; + + +/* + * VGT_IMMED_DATA struct + */ + +#define VGT_IMMED_DATA_DATA_SIZE 32 + +#define VGT_IMMED_DATA_DATA_SHIFT 0 + +#define VGT_IMMED_DATA_DATA_MASK 0xffffffff + +#define VGT_IMMED_DATA_MASK \ + (VGT_IMMED_DATA_DATA_MASK) + +#define VGT_IMMED_DATA(data) \ + ((data << VGT_IMMED_DATA_DATA_SHIFT)) + +#define VGT_IMMED_DATA_GET_DATA(vgt_immed_data) \ + ((vgt_immed_data & VGT_IMMED_DATA_DATA_MASK) >> VGT_IMMED_DATA_DATA_SHIFT) + +#define VGT_IMMED_DATA_SET_DATA(vgt_immed_data_reg, data) \ + vgt_immed_data_reg = (vgt_immed_data_reg & ~VGT_IMMED_DATA_DATA_MASK) | (data << VGT_IMMED_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_immed_data_t { + unsigned int data : VGT_IMMED_DATA_DATA_SIZE; + } vgt_immed_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_immed_data_t { + unsigned int data : VGT_IMMED_DATA_DATA_SIZE; + } vgt_immed_data_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_immed_data_t f; +} vgt_immed_data_u; + + +/* + * VGT_MAX_VTX_INDX struct + */ + +#define VGT_MAX_VTX_INDX_MAX_INDX_SIZE 24 + +#define VGT_MAX_VTX_INDX_MAX_INDX_SHIFT 0 + +#define VGT_MAX_VTX_INDX_MAX_INDX_MASK 0x00ffffff + +#define VGT_MAX_VTX_INDX_MASK \ + (VGT_MAX_VTX_INDX_MAX_INDX_MASK) + +#define VGT_MAX_VTX_INDX(max_indx) \ + ((max_indx << VGT_MAX_VTX_INDX_MAX_INDX_SHIFT)) + +#define VGT_MAX_VTX_INDX_GET_MAX_INDX(vgt_max_vtx_indx) \ + ((vgt_max_vtx_indx & VGT_MAX_VTX_INDX_MAX_INDX_MASK) >> VGT_MAX_VTX_INDX_MAX_INDX_SHIFT) + +#define VGT_MAX_VTX_INDX_SET_MAX_INDX(vgt_max_vtx_indx_reg, max_indx) \ + vgt_max_vtx_indx_reg = (vgt_max_vtx_indx_reg & ~VGT_MAX_VTX_INDX_MAX_INDX_MASK) | (max_indx << VGT_MAX_VTX_INDX_MAX_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_max_vtx_indx_t { + unsigned int max_indx : VGT_MAX_VTX_INDX_MAX_INDX_SIZE; + unsigned int : 8; + } vgt_max_vtx_indx_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_max_vtx_indx_t { + unsigned int : 8; + unsigned int max_indx : VGT_MAX_VTX_INDX_MAX_INDX_SIZE; + } vgt_max_vtx_indx_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_max_vtx_indx_t f; +} vgt_max_vtx_indx_u; + + +/* + * VGT_MIN_VTX_INDX struct + */ + +#define VGT_MIN_VTX_INDX_MIN_INDX_SIZE 24 + +#define VGT_MIN_VTX_INDX_MIN_INDX_SHIFT 0 + +#define VGT_MIN_VTX_INDX_MIN_INDX_MASK 0x00ffffff + +#define VGT_MIN_VTX_INDX_MASK \ + (VGT_MIN_VTX_INDX_MIN_INDX_MASK) + +#define VGT_MIN_VTX_INDX(min_indx) \ + ((min_indx << VGT_MIN_VTX_INDX_MIN_INDX_SHIFT)) + +#define VGT_MIN_VTX_INDX_GET_MIN_INDX(vgt_min_vtx_indx) \ + ((vgt_min_vtx_indx & VGT_MIN_VTX_INDX_MIN_INDX_MASK) >> VGT_MIN_VTX_INDX_MIN_INDX_SHIFT) + +#define VGT_MIN_VTX_INDX_SET_MIN_INDX(vgt_min_vtx_indx_reg, min_indx) \ + vgt_min_vtx_indx_reg = (vgt_min_vtx_indx_reg & ~VGT_MIN_VTX_INDX_MIN_INDX_MASK) | (min_indx << VGT_MIN_VTX_INDX_MIN_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_min_vtx_indx_t { + unsigned int min_indx : VGT_MIN_VTX_INDX_MIN_INDX_SIZE; + unsigned int : 8; + } vgt_min_vtx_indx_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_min_vtx_indx_t { + unsigned int : 8; + unsigned int min_indx : VGT_MIN_VTX_INDX_MIN_INDX_SIZE; + } vgt_min_vtx_indx_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_min_vtx_indx_t f; +} vgt_min_vtx_indx_u; + + +/* + * VGT_INDX_OFFSET struct + */ + +#define VGT_INDX_OFFSET_INDX_OFFSET_SIZE 24 + +#define VGT_INDX_OFFSET_INDX_OFFSET_SHIFT 0 + +#define VGT_INDX_OFFSET_INDX_OFFSET_MASK 0x00ffffff + +#define VGT_INDX_OFFSET_MASK \ + (VGT_INDX_OFFSET_INDX_OFFSET_MASK) + +#define VGT_INDX_OFFSET(indx_offset) \ + ((indx_offset << VGT_INDX_OFFSET_INDX_OFFSET_SHIFT)) + +#define VGT_INDX_OFFSET_GET_INDX_OFFSET(vgt_indx_offset) \ + ((vgt_indx_offset & VGT_INDX_OFFSET_INDX_OFFSET_MASK) >> VGT_INDX_OFFSET_INDX_OFFSET_SHIFT) + +#define VGT_INDX_OFFSET_SET_INDX_OFFSET(vgt_indx_offset_reg, indx_offset) \ + vgt_indx_offset_reg = (vgt_indx_offset_reg & ~VGT_INDX_OFFSET_INDX_OFFSET_MASK) | (indx_offset << VGT_INDX_OFFSET_INDX_OFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_indx_offset_t { + unsigned int indx_offset : VGT_INDX_OFFSET_INDX_OFFSET_SIZE; + unsigned int : 8; + } vgt_indx_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_indx_offset_t { + unsigned int : 8; + unsigned int indx_offset : VGT_INDX_OFFSET_INDX_OFFSET_SIZE; + } vgt_indx_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_indx_offset_t f; +} vgt_indx_offset_u; + + +/* + * VGT_VERTEX_REUSE_BLOCK_CNTL struct + */ + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE 3 + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT 0 + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK 0x00000007 + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_MASK \ + (VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) + +#define VGT_VERTEX_REUSE_BLOCK_CNTL(vtx_reuse_depth) \ + ((vtx_reuse_depth << VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT)) + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_GET_VTX_REUSE_DEPTH(vgt_vertex_reuse_block_cntl) \ + ((vgt_vertex_reuse_block_cntl & VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) >> VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT) + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_SET_VTX_REUSE_DEPTH(vgt_vertex_reuse_block_cntl_reg, vtx_reuse_depth) \ + vgt_vertex_reuse_block_cntl_reg = (vgt_vertex_reuse_block_cntl_reg & ~VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) | (vtx_reuse_depth << VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_vertex_reuse_block_cntl_t { + unsigned int vtx_reuse_depth : VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE; + unsigned int : 29; + } vgt_vertex_reuse_block_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_vertex_reuse_block_cntl_t { + unsigned int : 29; + unsigned int vtx_reuse_depth : VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE; + } vgt_vertex_reuse_block_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_vertex_reuse_block_cntl_t f; +} vgt_vertex_reuse_block_cntl_u; + + +/* + * VGT_OUT_DEALLOC_CNTL struct + */ + +#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE 2 + +#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT 0 + +#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK 0x00000003 + +#define VGT_OUT_DEALLOC_CNTL_MASK \ + (VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) + +#define VGT_OUT_DEALLOC_CNTL(dealloc_dist) \ + ((dealloc_dist << VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT)) + +#define VGT_OUT_DEALLOC_CNTL_GET_DEALLOC_DIST(vgt_out_dealloc_cntl) \ + ((vgt_out_dealloc_cntl & VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) >> VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT) + +#define VGT_OUT_DEALLOC_CNTL_SET_DEALLOC_DIST(vgt_out_dealloc_cntl_reg, dealloc_dist) \ + vgt_out_dealloc_cntl_reg = (vgt_out_dealloc_cntl_reg & ~VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) | (dealloc_dist << VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_out_dealloc_cntl_t { + unsigned int dealloc_dist : VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE; + unsigned int : 30; + } vgt_out_dealloc_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_out_dealloc_cntl_t { + unsigned int : 30; + unsigned int dealloc_dist : VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE; + } vgt_out_dealloc_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_out_dealloc_cntl_t f; +} vgt_out_dealloc_cntl_u; + + +/* + * VGT_MULTI_PRIM_IB_RESET_INDX struct + */ + +#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE 24 + +#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT 0 + +#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK 0x00ffffff + +#define VGT_MULTI_PRIM_IB_RESET_INDX_MASK \ + (VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) + +#define VGT_MULTI_PRIM_IB_RESET_INDX(reset_indx) \ + ((reset_indx << VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT)) + +#define VGT_MULTI_PRIM_IB_RESET_INDX_GET_RESET_INDX(vgt_multi_prim_ib_reset_indx) \ + ((vgt_multi_prim_ib_reset_indx & VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) >> VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT) + +#define VGT_MULTI_PRIM_IB_RESET_INDX_SET_RESET_INDX(vgt_multi_prim_ib_reset_indx_reg, reset_indx) \ + vgt_multi_prim_ib_reset_indx_reg = (vgt_multi_prim_ib_reset_indx_reg & ~VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) | (reset_indx << VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_multi_prim_ib_reset_indx_t { + unsigned int reset_indx : VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE; + unsigned int : 8; + } vgt_multi_prim_ib_reset_indx_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_multi_prim_ib_reset_indx_t { + unsigned int : 8; + unsigned int reset_indx : VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE; + } vgt_multi_prim_ib_reset_indx_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_multi_prim_ib_reset_indx_t f; +} vgt_multi_prim_ib_reset_indx_u; + + +/* + * VGT_ENHANCE struct + */ + +#define VGT_ENHANCE_MISC_SIZE 16 + +#define VGT_ENHANCE_MISC_SHIFT 0 + +#define VGT_ENHANCE_MISC_MASK 0x0000ffff + +#define VGT_ENHANCE_MASK \ + (VGT_ENHANCE_MISC_MASK) + +#define VGT_ENHANCE(misc) \ + ((misc << VGT_ENHANCE_MISC_SHIFT)) + +#define VGT_ENHANCE_GET_MISC(vgt_enhance) \ + ((vgt_enhance & VGT_ENHANCE_MISC_MASK) >> VGT_ENHANCE_MISC_SHIFT) + +#define VGT_ENHANCE_SET_MISC(vgt_enhance_reg, misc) \ + vgt_enhance_reg = (vgt_enhance_reg & ~VGT_ENHANCE_MISC_MASK) | (misc << VGT_ENHANCE_MISC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_enhance_t { + unsigned int misc : VGT_ENHANCE_MISC_SIZE; + unsigned int : 16; + } vgt_enhance_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_enhance_t { + unsigned int : 16; + unsigned int misc : VGT_ENHANCE_MISC_SIZE; + } vgt_enhance_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_enhance_t f; +} vgt_enhance_u; + + +/* + * VGT_VTX_VECT_EJECT_REG struct + */ + +#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE 5 + +#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT 0 + +#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK 0x0000001f + +#define VGT_VTX_VECT_EJECT_REG_MASK \ + (VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) + +#define VGT_VTX_VECT_EJECT_REG(prim_count) \ + ((prim_count << VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT)) + +#define VGT_VTX_VECT_EJECT_REG_GET_PRIM_COUNT(vgt_vtx_vect_eject_reg) \ + ((vgt_vtx_vect_eject_reg & VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) >> VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT) + +#define VGT_VTX_VECT_EJECT_REG_SET_PRIM_COUNT(vgt_vtx_vect_eject_reg_reg, prim_count) \ + vgt_vtx_vect_eject_reg_reg = (vgt_vtx_vect_eject_reg_reg & ~VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) | (prim_count << VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_vtx_vect_eject_reg_t { + unsigned int prim_count : VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE; + unsigned int : 27; + } vgt_vtx_vect_eject_reg_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_vtx_vect_eject_reg_t { + unsigned int : 27; + unsigned int prim_count : VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE; + } vgt_vtx_vect_eject_reg_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_vtx_vect_eject_reg_t f; +} vgt_vtx_vect_eject_reg_u; + + +/* + * VGT_LAST_COPY_STATE struct + */ + +#define VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE 1 +#define VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE 1 + +#define VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT 0 +#define VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT 16 + +#define VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK 0x00000001 +#define VGT_LAST_COPY_STATE_DST_STATE_ID_MASK 0x00010000 + +#define VGT_LAST_COPY_STATE_MASK \ + (VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK | \ + VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) + +#define VGT_LAST_COPY_STATE(src_state_id, dst_state_id) \ + ((src_state_id << VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT) | \ + (dst_state_id << VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT)) + +#define VGT_LAST_COPY_STATE_GET_SRC_STATE_ID(vgt_last_copy_state) \ + ((vgt_last_copy_state & VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK) >> VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT) +#define VGT_LAST_COPY_STATE_GET_DST_STATE_ID(vgt_last_copy_state) \ + ((vgt_last_copy_state & VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) >> VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT) + +#define VGT_LAST_COPY_STATE_SET_SRC_STATE_ID(vgt_last_copy_state_reg, src_state_id) \ + vgt_last_copy_state_reg = (vgt_last_copy_state_reg & ~VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK) | (src_state_id << VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT) +#define VGT_LAST_COPY_STATE_SET_DST_STATE_ID(vgt_last_copy_state_reg, dst_state_id) \ + vgt_last_copy_state_reg = (vgt_last_copy_state_reg & ~VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) | (dst_state_id << VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_last_copy_state_t { + unsigned int src_state_id : VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE; + unsigned int : 15; + unsigned int dst_state_id : VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE; + unsigned int : 15; + } vgt_last_copy_state_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_last_copy_state_t { + unsigned int : 15; + unsigned int dst_state_id : VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE; + unsigned int : 15; + unsigned int src_state_id : VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE; + } vgt_last_copy_state_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_last_copy_state_t f; +} vgt_last_copy_state_u; + + +/* + * VGT_DEBUG_CNTL struct + */ + +#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE 5 + +#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT 0 + +#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK 0x0000001f + +#define VGT_DEBUG_CNTL_MASK \ + (VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) + +#define VGT_DEBUG_CNTL(vgt_debug_indx) \ + ((vgt_debug_indx << VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT)) + +#define VGT_DEBUG_CNTL_GET_VGT_DEBUG_INDX(vgt_debug_cntl) \ + ((vgt_debug_cntl & VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) >> VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT) + +#define VGT_DEBUG_CNTL_SET_VGT_DEBUG_INDX(vgt_debug_cntl_reg, vgt_debug_indx) \ + vgt_debug_cntl_reg = (vgt_debug_cntl_reg & ~VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) | (vgt_debug_indx << VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_cntl_t { + unsigned int vgt_debug_indx : VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE; + unsigned int : 27; + } vgt_debug_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_cntl_t { + unsigned int : 27; + unsigned int vgt_debug_indx : VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE; + } vgt_debug_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_cntl_t f; +} vgt_debug_cntl_u; + + +/* + * VGT_DEBUG_DATA struct + */ + +#define VGT_DEBUG_DATA_DATA_SIZE 32 + +#define VGT_DEBUG_DATA_DATA_SHIFT 0 + +#define VGT_DEBUG_DATA_DATA_MASK 0xffffffff + +#define VGT_DEBUG_DATA_MASK \ + (VGT_DEBUG_DATA_DATA_MASK) + +#define VGT_DEBUG_DATA(data) \ + ((data << VGT_DEBUG_DATA_DATA_SHIFT)) + +#define VGT_DEBUG_DATA_GET_DATA(vgt_debug_data) \ + ((vgt_debug_data & VGT_DEBUG_DATA_DATA_MASK) >> VGT_DEBUG_DATA_DATA_SHIFT) + +#define VGT_DEBUG_DATA_SET_DATA(vgt_debug_data_reg, data) \ + vgt_debug_data_reg = (vgt_debug_data_reg & ~VGT_DEBUG_DATA_DATA_MASK) | (data << VGT_DEBUG_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_data_t { + unsigned int data : VGT_DEBUG_DATA_DATA_SIZE; + } vgt_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_data_t { + unsigned int data : VGT_DEBUG_DATA_DATA_SIZE; + } vgt_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_data_t f; +} vgt_debug_data_u; + + +/* + * VGT_CNTL_STATUS struct + */ + +#define VGT_CNTL_STATUS_VGT_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE 1 + +#define VGT_CNTL_STATUS_VGT_BUSY_SHIFT 0 +#define VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT 1 +#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT 2 +#define VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT 3 +#define VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT 4 +#define VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT 5 +#define VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT 6 +#define VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT 7 +#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT 8 + +#define VGT_CNTL_STATUS_VGT_BUSY_MASK 0x00000001 +#define VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK 0x00000002 +#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK 0x00000004 +#define VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK 0x00000008 +#define VGT_CNTL_STATUS_VGT_VR_BUSY_MASK 0x00000010 +#define VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK 0x00000020 +#define VGT_CNTL_STATUS_VGT_PT_BUSY_MASK 0x00000040 +#define VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK 0x00000080 +#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK 0x00000100 + +#define VGT_CNTL_STATUS_MASK \ + (VGT_CNTL_STATUS_VGT_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_VR_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_PT_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) + +#define VGT_CNTL_STATUS(vgt_busy, vgt_dma_busy, vgt_dma_req_busy, vgt_grp_busy, vgt_vr_busy, vgt_bin_busy, vgt_pt_busy, vgt_out_busy, vgt_out_indx_busy) \ + ((vgt_busy << VGT_CNTL_STATUS_VGT_BUSY_SHIFT) | \ + (vgt_dma_busy << VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT) | \ + (vgt_dma_req_busy << VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT) | \ + (vgt_grp_busy << VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT) | \ + (vgt_vr_busy << VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT) | \ + (vgt_bin_busy << VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT) | \ + (vgt_pt_busy << VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT) | \ + (vgt_out_busy << VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT) | \ + (vgt_out_indx_busy << VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT)) + +#define VGT_CNTL_STATUS_GET_VGT_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_DMA_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_DMA_REQ_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_GRP_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_VR_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_VR_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_BIN_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_PT_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_PT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_OUT_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_OUT_INDX_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT) + +#define VGT_CNTL_STATUS_SET_VGT_BUSY(vgt_cntl_status_reg, vgt_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_BUSY_MASK) | (vgt_busy << VGT_CNTL_STATUS_VGT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_DMA_BUSY(vgt_cntl_status_reg, vgt_dma_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK) | (vgt_dma_busy << VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_DMA_REQ_BUSY(vgt_cntl_status_reg, vgt_dma_req_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK) | (vgt_dma_req_busy << VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_GRP_BUSY(vgt_cntl_status_reg, vgt_grp_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK) | (vgt_grp_busy << VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_VR_BUSY(vgt_cntl_status_reg, vgt_vr_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_VR_BUSY_MASK) | (vgt_vr_busy << VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_BIN_BUSY(vgt_cntl_status_reg, vgt_bin_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK) | (vgt_bin_busy << VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_PT_BUSY(vgt_cntl_status_reg, vgt_pt_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_PT_BUSY_MASK) | (vgt_pt_busy << VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_OUT_BUSY(vgt_cntl_status_reg, vgt_out_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK) | (vgt_out_busy << VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_OUT_INDX_BUSY(vgt_cntl_status_reg, vgt_out_indx_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) | (vgt_out_indx_busy << VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_cntl_status_t { + unsigned int vgt_busy : VGT_CNTL_STATUS_VGT_BUSY_SIZE; + unsigned int vgt_dma_busy : VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE; + unsigned int vgt_dma_req_busy : VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE; + unsigned int vgt_grp_busy : VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE; + unsigned int vgt_vr_busy : VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE; + unsigned int vgt_bin_busy : VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE; + unsigned int vgt_pt_busy : VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE; + unsigned int vgt_out_busy : VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE; + unsigned int vgt_out_indx_busy : VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE; + unsigned int : 23; + } vgt_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_cntl_status_t { + unsigned int : 23; + unsigned int vgt_out_indx_busy : VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE; + unsigned int vgt_out_busy : VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE; + unsigned int vgt_pt_busy : VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE; + unsigned int vgt_bin_busy : VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE; + unsigned int vgt_vr_busy : VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE; + unsigned int vgt_grp_busy : VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE; + unsigned int vgt_dma_req_busy : VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE; + unsigned int vgt_dma_busy : VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE; + unsigned int vgt_busy : VGT_CNTL_STATUS_VGT_BUSY_SIZE; + } vgt_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_cntl_status_t f; +} vgt_cntl_status_u; + + +/* + * VGT_DEBUG_REG0 struct + */ + +#define VGT_DEBUG_REG0_te_grp_busy_SIZE 1 +#define VGT_DEBUG_REG0_pt_grp_busy_SIZE 1 +#define VGT_DEBUG_REG0_vr_grp_busy_SIZE 1 +#define VGT_DEBUG_REG0_dma_request_busy_SIZE 1 +#define VGT_DEBUG_REG0_out_busy_SIZE 1 +#define VGT_DEBUG_REG0_grp_backend_busy_SIZE 1 +#define VGT_DEBUG_REG0_grp_busy_SIZE 1 +#define VGT_DEBUG_REG0_dma_busy_SIZE 1 +#define VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE 1 +#define VGT_DEBUG_REG0_rbiu_busy_SIZE 1 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE 1 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE 1 +#define VGT_DEBUG_REG0_vgt_busy_extended_SIZE 1 +#define VGT_DEBUG_REG0_vgt_busy_SIZE 1 +#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE 1 +#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE 1 +#define VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE 1 + +#define VGT_DEBUG_REG0_te_grp_busy_SHIFT 0 +#define VGT_DEBUG_REG0_pt_grp_busy_SHIFT 1 +#define VGT_DEBUG_REG0_vr_grp_busy_SHIFT 2 +#define VGT_DEBUG_REG0_dma_request_busy_SHIFT 3 +#define VGT_DEBUG_REG0_out_busy_SHIFT 4 +#define VGT_DEBUG_REG0_grp_backend_busy_SHIFT 5 +#define VGT_DEBUG_REG0_grp_busy_SHIFT 6 +#define VGT_DEBUG_REG0_dma_busy_SHIFT 7 +#define VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT 8 +#define VGT_DEBUG_REG0_rbiu_busy_SHIFT 9 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT 10 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT 11 +#define VGT_DEBUG_REG0_vgt_busy_extended_SHIFT 12 +#define VGT_DEBUG_REG0_vgt_busy_SHIFT 13 +#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT 14 +#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT 15 +#define VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT 16 + +#define VGT_DEBUG_REG0_te_grp_busy_MASK 0x00000001 +#define VGT_DEBUG_REG0_pt_grp_busy_MASK 0x00000002 +#define VGT_DEBUG_REG0_vr_grp_busy_MASK 0x00000004 +#define VGT_DEBUG_REG0_dma_request_busy_MASK 0x00000008 +#define VGT_DEBUG_REG0_out_busy_MASK 0x00000010 +#define VGT_DEBUG_REG0_grp_backend_busy_MASK 0x00000020 +#define VGT_DEBUG_REG0_grp_busy_MASK 0x00000040 +#define VGT_DEBUG_REG0_dma_busy_MASK 0x00000080 +#define VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK 0x00000100 +#define VGT_DEBUG_REG0_rbiu_busy_MASK 0x00000200 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK 0x00000400 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_MASK 0x00000800 +#define VGT_DEBUG_REG0_vgt_busy_extended_MASK 0x00001000 +#define VGT_DEBUG_REG0_vgt_busy_MASK 0x00002000 +#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK 0x00004000 +#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK 0x00008000 +#define VGT_DEBUG_REG0_VGT_RBBM_busy_MASK 0x00010000 + +#define VGT_DEBUG_REG0_MASK \ + (VGT_DEBUG_REG0_te_grp_busy_MASK | \ + VGT_DEBUG_REG0_pt_grp_busy_MASK | \ + VGT_DEBUG_REG0_vr_grp_busy_MASK | \ + VGT_DEBUG_REG0_dma_request_busy_MASK | \ + VGT_DEBUG_REG0_out_busy_MASK | \ + VGT_DEBUG_REG0_grp_backend_busy_MASK | \ + VGT_DEBUG_REG0_grp_busy_MASK | \ + VGT_DEBUG_REG0_dma_busy_MASK | \ + VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK | \ + VGT_DEBUG_REG0_rbiu_busy_MASK | \ + VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK | \ + VGT_DEBUG_REG0_vgt_no_dma_busy_MASK | \ + VGT_DEBUG_REG0_vgt_busy_extended_MASK | \ + VGT_DEBUG_REG0_vgt_busy_MASK | \ + VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK | \ + VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK | \ + VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) + +#define VGT_DEBUG_REG0(te_grp_busy, pt_grp_busy, vr_grp_busy, dma_request_busy, out_busy, grp_backend_busy, grp_busy, dma_busy, rbiu_dma_request_busy, rbiu_busy, vgt_no_dma_busy_extended, vgt_no_dma_busy, vgt_busy_extended, vgt_busy, rbbm_skid_fifo_busy_out, vgt_rbbm_no_dma_busy, vgt_rbbm_busy) \ + ((te_grp_busy << VGT_DEBUG_REG0_te_grp_busy_SHIFT) | \ + (pt_grp_busy << VGT_DEBUG_REG0_pt_grp_busy_SHIFT) | \ + (vr_grp_busy << VGT_DEBUG_REG0_vr_grp_busy_SHIFT) | \ + (dma_request_busy << VGT_DEBUG_REG0_dma_request_busy_SHIFT) | \ + (out_busy << VGT_DEBUG_REG0_out_busy_SHIFT) | \ + (grp_backend_busy << VGT_DEBUG_REG0_grp_backend_busy_SHIFT) | \ + (grp_busy << VGT_DEBUG_REG0_grp_busy_SHIFT) | \ + (dma_busy << VGT_DEBUG_REG0_dma_busy_SHIFT) | \ + (rbiu_dma_request_busy << VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT) | \ + (rbiu_busy << VGT_DEBUG_REG0_rbiu_busy_SHIFT) | \ + (vgt_no_dma_busy_extended << VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT) | \ + (vgt_no_dma_busy << VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT) | \ + (vgt_busy_extended << VGT_DEBUG_REG0_vgt_busy_extended_SHIFT) | \ + (vgt_busy << VGT_DEBUG_REG0_vgt_busy_SHIFT) | \ + (rbbm_skid_fifo_busy_out << VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT) | \ + (vgt_rbbm_no_dma_busy << VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT) | \ + (vgt_rbbm_busy << VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT)) + +#define VGT_DEBUG_REG0_GET_te_grp_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_te_grp_busy_MASK) >> VGT_DEBUG_REG0_te_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_pt_grp_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_pt_grp_busy_MASK) >> VGT_DEBUG_REG0_pt_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_vr_grp_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vr_grp_busy_MASK) >> VGT_DEBUG_REG0_vr_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_dma_request_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_dma_request_busy_MASK) >> VGT_DEBUG_REG0_dma_request_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_out_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_out_busy_MASK) >> VGT_DEBUG_REG0_out_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_grp_backend_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_grp_backend_busy_MASK) >> VGT_DEBUG_REG0_grp_backend_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_grp_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_grp_busy_MASK) >> VGT_DEBUG_REG0_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_dma_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_dma_busy_MASK) >> VGT_DEBUG_REG0_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_rbiu_dma_request_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK) >> VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_rbiu_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbiu_busy_MASK) >> VGT_DEBUG_REG0_rbiu_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_vgt_no_dma_busy_extended(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK) >> VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT) +#define VGT_DEBUG_REG0_GET_vgt_no_dma_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_no_dma_busy_MASK) >> VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_vgt_busy_extended(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_busy_extended_MASK) >> VGT_DEBUG_REG0_vgt_busy_extended_SHIFT) +#define VGT_DEBUG_REG0_GET_vgt_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_busy_MASK) >> VGT_DEBUG_REG0_vgt_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_rbbm_skid_fifo_busy_out(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK) >> VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT) +#define VGT_DEBUG_REG0_GET_VGT_RBBM_no_dma_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK) >> VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_VGT_RBBM_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) >> VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT) + +#define VGT_DEBUG_REG0_SET_te_grp_busy(vgt_debug_reg0_reg, te_grp_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_te_grp_busy_MASK) | (te_grp_busy << VGT_DEBUG_REG0_te_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_pt_grp_busy(vgt_debug_reg0_reg, pt_grp_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_pt_grp_busy_MASK) | (pt_grp_busy << VGT_DEBUG_REG0_pt_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_vr_grp_busy(vgt_debug_reg0_reg, vr_grp_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vr_grp_busy_MASK) | (vr_grp_busy << VGT_DEBUG_REG0_vr_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_dma_request_busy(vgt_debug_reg0_reg, dma_request_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_dma_request_busy_MASK) | (dma_request_busy << VGT_DEBUG_REG0_dma_request_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_out_busy(vgt_debug_reg0_reg, out_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_out_busy_MASK) | (out_busy << VGT_DEBUG_REG0_out_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_grp_backend_busy(vgt_debug_reg0_reg, grp_backend_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_grp_backend_busy_MASK) | (grp_backend_busy << VGT_DEBUG_REG0_grp_backend_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_grp_busy(vgt_debug_reg0_reg, grp_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_grp_busy_MASK) | (grp_busy << VGT_DEBUG_REG0_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_dma_busy(vgt_debug_reg0_reg, dma_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_dma_busy_MASK) | (dma_busy << VGT_DEBUG_REG0_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_rbiu_dma_request_busy(vgt_debug_reg0_reg, rbiu_dma_request_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK) | (rbiu_dma_request_busy << VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_rbiu_busy(vgt_debug_reg0_reg, rbiu_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbiu_busy_MASK) | (rbiu_busy << VGT_DEBUG_REG0_rbiu_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_vgt_no_dma_busy_extended(vgt_debug_reg0_reg, vgt_no_dma_busy_extended) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK) | (vgt_no_dma_busy_extended << VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT) +#define VGT_DEBUG_REG0_SET_vgt_no_dma_busy(vgt_debug_reg0_reg, vgt_no_dma_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_no_dma_busy_MASK) | (vgt_no_dma_busy << VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_vgt_busy_extended(vgt_debug_reg0_reg, vgt_busy_extended) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_busy_extended_MASK) | (vgt_busy_extended << VGT_DEBUG_REG0_vgt_busy_extended_SHIFT) +#define VGT_DEBUG_REG0_SET_vgt_busy(vgt_debug_reg0_reg, vgt_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_busy_MASK) | (vgt_busy << VGT_DEBUG_REG0_vgt_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_rbbm_skid_fifo_busy_out(vgt_debug_reg0_reg, rbbm_skid_fifo_busy_out) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK) | (rbbm_skid_fifo_busy_out << VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT) +#define VGT_DEBUG_REG0_SET_VGT_RBBM_no_dma_busy(vgt_debug_reg0_reg, vgt_rbbm_no_dma_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK) | (vgt_rbbm_no_dma_busy << VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_VGT_RBBM_busy(vgt_debug_reg0_reg, vgt_rbbm_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) | (vgt_rbbm_busy << VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg0_t { + unsigned int te_grp_busy : VGT_DEBUG_REG0_te_grp_busy_SIZE; + unsigned int pt_grp_busy : VGT_DEBUG_REG0_pt_grp_busy_SIZE; + unsigned int vr_grp_busy : VGT_DEBUG_REG0_vr_grp_busy_SIZE; + unsigned int dma_request_busy : VGT_DEBUG_REG0_dma_request_busy_SIZE; + unsigned int out_busy : VGT_DEBUG_REG0_out_busy_SIZE; + unsigned int grp_backend_busy : VGT_DEBUG_REG0_grp_backend_busy_SIZE; + unsigned int grp_busy : VGT_DEBUG_REG0_grp_busy_SIZE; + unsigned int dma_busy : VGT_DEBUG_REG0_dma_busy_SIZE; + unsigned int rbiu_dma_request_busy : VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE; + unsigned int rbiu_busy : VGT_DEBUG_REG0_rbiu_busy_SIZE; + unsigned int vgt_no_dma_busy_extended : VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE; + unsigned int vgt_no_dma_busy : VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE; + unsigned int vgt_busy_extended : VGT_DEBUG_REG0_vgt_busy_extended_SIZE; + unsigned int vgt_busy : VGT_DEBUG_REG0_vgt_busy_SIZE; + unsigned int rbbm_skid_fifo_busy_out : VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE; + unsigned int vgt_rbbm_no_dma_busy : VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE; + unsigned int vgt_rbbm_busy : VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE; + unsigned int : 15; + } vgt_debug_reg0_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg0_t { + unsigned int : 15; + unsigned int vgt_rbbm_busy : VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE; + unsigned int vgt_rbbm_no_dma_busy : VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE; + unsigned int rbbm_skid_fifo_busy_out : VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE; + unsigned int vgt_busy : VGT_DEBUG_REG0_vgt_busy_SIZE; + unsigned int vgt_busy_extended : VGT_DEBUG_REG0_vgt_busy_extended_SIZE; + unsigned int vgt_no_dma_busy : VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE; + unsigned int vgt_no_dma_busy_extended : VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE; + unsigned int rbiu_busy : VGT_DEBUG_REG0_rbiu_busy_SIZE; + unsigned int rbiu_dma_request_busy : VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE; + unsigned int dma_busy : VGT_DEBUG_REG0_dma_busy_SIZE; + unsigned int grp_busy : VGT_DEBUG_REG0_grp_busy_SIZE; + unsigned int grp_backend_busy : VGT_DEBUG_REG0_grp_backend_busy_SIZE; + unsigned int out_busy : VGT_DEBUG_REG0_out_busy_SIZE; + unsigned int dma_request_busy : VGT_DEBUG_REG0_dma_request_busy_SIZE; + unsigned int vr_grp_busy : VGT_DEBUG_REG0_vr_grp_busy_SIZE; + unsigned int pt_grp_busy : VGT_DEBUG_REG0_pt_grp_busy_SIZE; + unsigned int te_grp_busy : VGT_DEBUG_REG0_te_grp_busy_SIZE; + } vgt_debug_reg0_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg0_t f; +} vgt_debug_reg0_u; + + +/* + * VGT_DEBUG_REG1 struct + */ + +#define VGT_DEBUG_REG1_out_te_data_read_SIZE 1 +#define VGT_DEBUG_REG1_te_out_data_valid_SIZE 1 +#define VGT_DEBUG_REG1_out_pt_prim_read_SIZE 1 +#define VGT_DEBUG_REG1_pt_out_prim_valid_SIZE 1 +#define VGT_DEBUG_REG1_out_pt_data_read_SIZE 1 +#define VGT_DEBUG_REG1_pt_out_indx_valid_SIZE 1 +#define VGT_DEBUG_REG1_out_vr_prim_read_SIZE 1 +#define VGT_DEBUG_REG1_vr_out_prim_valid_SIZE 1 +#define VGT_DEBUG_REG1_out_vr_indx_read_SIZE 1 +#define VGT_DEBUG_REG1_vr_out_indx_valid_SIZE 1 +#define VGT_DEBUG_REG1_te_grp_read_SIZE 1 +#define VGT_DEBUG_REG1_grp_te_valid_SIZE 1 +#define VGT_DEBUG_REG1_pt_grp_read_SIZE 1 +#define VGT_DEBUG_REG1_grp_pt_valid_SIZE 1 +#define VGT_DEBUG_REG1_vr_grp_read_SIZE 1 +#define VGT_DEBUG_REG1_grp_vr_valid_SIZE 1 +#define VGT_DEBUG_REG1_grp_dma_read_SIZE 1 +#define VGT_DEBUG_REG1_dma_grp_valid_SIZE 1 +#define VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE 1 +#define VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE 1 +#define VGT_DEBUG_REG1_MH_VGT_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_MH_send_SIZE 1 +#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE 1 +#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE 1 +#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE 1 +#define VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_SQ_send_SIZE 1 +#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE 1 + +#define VGT_DEBUG_REG1_out_te_data_read_SHIFT 0 +#define VGT_DEBUG_REG1_te_out_data_valid_SHIFT 1 +#define VGT_DEBUG_REG1_out_pt_prim_read_SHIFT 2 +#define VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT 3 +#define VGT_DEBUG_REG1_out_pt_data_read_SHIFT 4 +#define VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT 5 +#define VGT_DEBUG_REG1_out_vr_prim_read_SHIFT 6 +#define VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT 7 +#define VGT_DEBUG_REG1_out_vr_indx_read_SHIFT 8 +#define VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT 9 +#define VGT_DEBUG_REG1_te_grp_read_SHIFT 10 +#define VGT_DEBUG_REG1_grp_te_valid_SHIFT 11 +#define VGT_DEBUG_REG1_pt_grp_read_SHIFT 12 +#define VGT_DEBUG_REG1_grp_pt_valid_SHIFT 13 +#define VGT_DEBUG_REG1_vr_grp_read_SHIFT 14 +#define VGT_DEBUG_REG1_grp_vr_valid_SHIFT 15 +#define VGT_DEBUG_REG1_grp_dma_read_SHIFT 16 +#define VGT_DEBUG_REG1_dma_grp_valid_SHIFT 17 +#define VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT 18 +#define VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT 19 +#define VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT 20 +#define VGT_DEBUG_REG1_VGT_MH_send_SHIFT 21 +#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT 22 +#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT 23 +#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT 24 +#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT 25 +#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT 26 +#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT 27 +#define VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT 28 +#define VGT_DEBUG_REG1_VGT_SQ_send_SHIFT 29 +#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT 30 + +#define VGT_DEBUG_REG1_out_te_data_read_MASK 0x00000001 +#define VGT_DEBUG_REG1_te_out_data_valid_MASK 0x00000002 +#define VGT_DEBUG_REG1_out_pt_prim_read_MASK 0x00000004 +#define VGT_DEBUG_REG1_pt_out_prim_valid_MASK 0x00000008 +#define VGT_DEBUG_REG1_out_pt_data_read_MASK 0x00000010 +#define VGT_DEBUG_REG1_pt_out_indx_valid_MASK 0x00000020 +#define VGT_DEBUG_REG1_out_vr_prim_read_MASK 0x00000040 +#define VGT_DEBUG_REG1_vr_out_prim_valid_MASK 0x00000080 +#define VGT_DEBUG_REG1_out_vr_indx_read_MASK 0x00000100 +#define VGT_DEBUG_REG1_vr_out_indx_valid_MASK 0x00000200 +#define VGT_DEBUG_REG1_te_grp_read_MASK 0x00000400 +#define VGT_DEBUG_REG1_grp_te_valid_MASK 0x00000800 +#define VGT_DEBUG_REG1_pt_grp_read_MASK 0x00001000 +#define VGT_DEBUG_REG1_grp_pt_valid_MASK 0x00002000 +#define VGT_DEBUG_REG1_vr_grp_read_MASK 0x00004000 +#define VGT_DEBUG_REG1_grp_vr_valid_MASK 0x00008000 +#define VGT_DEBUG_REG1_grp_dma_read_MASK 0x00010000 +#define VGT_DEBUG_REG1_dma_grp_valid_MASK 0x00020000 +#define VGT_DEBUG_REG1_grp_rbiu_di_read_MASK 0x00040000 +#define VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK 0x00080000 +#define VGT_DEBUG_REG1_MH_VGT_rtr_MASK 0x00100000 +#define VGT_DEBUG_REG1_VGT_MH_send_MASK 0x00200000 +#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK 0x00400000 +#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK 0x00800000 +#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK 0x01000000 +#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK 0x02000000 +#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK 0x04000000 +#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK 0x08000000 +#define VGT_DEBUG_REG1_SQ_VGT_rtr_MASK 0x10000000 +#define VGT_DEBUG_REG1_VGT_SQ_send_MASK 0x20000000 +#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK 0x40000000 + +#define VGT_DEBUG_REG1_MASK \ + (VGT_DEBUG_REG1_out_te_data_read_MASK | \ + VGT_DEBUG_REG1_te_out_data_valid_MASK | \ + VGT_DEBUG_REG1_out_pt_prim_read_MASK | \ + VGT_DEBUG_REG1_pt_out_prim_valid_MASK | \ + VGT_DEBUG_REG1_out_pt_data_read_MASK | \ + VGT_DEBUG_REG1_pt_out_indx_valid_MASK | \ + VGT_DEBUG_REG1_out_vr_prim_read_MASK | \ + VGT_DEBUG_REG1_vr_out_prim_valid_MASK | \ + VGT_DEBUG_REG1_out_vr_indx_read_MASK | \ + VGT_DEBUG_REG1_vr_out_indx_valid_MASK | \ + VGT_DEBUG_REG1_te_grp_read_MASK | \ + VGT_DEBUG_REG1_grp_te_valid_MASK | \ + VGT_DEBUG_REG1_pt_grp_read_MASK | \ + VGT_DEBUG_REG1_grp_pt_valid_MASK | \ + VGT_DEBUG_REG1_vr_grp_read_MASK | \ + VGT_DEBUG_REG1_grp_vr_valid_MASK | \ + VGT_DEBUG_REG1_grp_dma_read_MASK | \ + VGT_DEBUG_REG1_dma_grp_valid_MASK | \ + VGT_DEBUG_REG1_grp_rbiu_di_read_MASK | \ + VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK | \ + VGT_DEBUG_REG1_MH_VGT_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_MH_send_MASK | \ + VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK | \ + VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK | \ + VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK | \ + VGT_DEBUG_REG1_SQ_VGT_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_SQ_send_MASK | \ + VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) + +#define VGT_DEBUG_REG1(out_te_data_read, te_out_data_valid, out_pt_prim_read, pt_out_prim_valid, out_pt_data_read, pt_out_indx_valid, out_vr_prim_read, vr_out_prim_valid, out_vr_indx_read, vr_out_indx_valid, te_grp_read, grp_te_valid, pt_grp_read, grp_pt_valid, vr_grp_read, grp_vr_valid, grp_dma_read, dma_grp_valid, grp_rbiu_di_read, rbiu_grp_di_valid, mh_vgt_rtr, vgt_mh_send, pa_vgt_clip_s_rtr, vgt_pa_clip_s_send, pa_vgt_clip_p_rtr, vgt_pa_clip_p_send, pa_vgt_clip_v_rtr, vgt_pa_clip_v_send, sq_vgt_rtr, vgt_sq_send, mh_vgt_tag_7_q) \ + ((out_te_data_read << VGT_DEBUG_REG1_out_te_data_read_SHIFT) | \ + (te_out_data_valid << VGT_DEBUG_REG1_te_out_data_valid_SHIFT) | \ + (out_pt_prim_read << VGT_DEBUG_REG1_out_pt_prim_read_SHIFT) | \ + (pt_out_prim_valid << VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT) | \ + (out_pt_data_read << VGT_DEBUG_REG1_out_pt_data_read_SHIFT) | \ + (pt_out_indx_valid << VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT) | \ + (out_vr_prim_read << VGT_DEBUG_REG1_out_vr_prim_read_SHIFT) | \ + (vr_out_prim_valid << VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT) | \ + (out_vr_indx_read << VGT_DEBUG_REG1_out_vr_indx_read_SHIFT) | \ + (vr_out_indx_valid << VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT) | \ + (te_grp_read << VGT_DEBUG_REG1_te_grp_read_SHIFT) | \ + (grp_te_valid << VGT_DEBUG_REG1_grp_te_valid_SHIFT) | \ + (pt_grp_read << VGT_DEBUG_REG1_pt_grp_read_SHIFT) | \ + (grp_pt_valid << VGT_DEBUG_REG1_grp_pt_valid_SHIFT) | \ + (vr_grp_read << VGT_DEBUG_REG1_vr_grp_read_SHIFT) | \ + (grp_vr_valid << VGT_DEBUG_REG1_grp_vr_valid_SHIFT) | \ + (grp_dma_read << VGT_DEBUG_REG1_grp_dma_read_SHIFT) | \ + (dma_grp_valid << VGT_DEBUG_REG1_dma_grp_valid_SHIFT) | \ + (grp_rbiu_di_read << VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT) | \ + (rbiu_grp_di_valid << VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT) | \ + (mh_vgt_rtr << VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT) | \ + (vgt_mh_send << VGT_DEBUG_REG1_VGT_MH_send_SHIFT) | \ + (pa_vgt_clip_s_rtr << VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT) | \ + (vgt_pa_clip_s_send << VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT) | \ + (pa_vgt_clip_p_rtr << VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT) | \ + (vgt_pa_clip_p_send << VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT) | \ + (pa_vgt_clip_v_rtr << VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT) | \ + (vgt_pa_clip_v_send << VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT) | \ + (sq_vgt_rtr << VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT) | \ + (vgt_sq_send << VGT_DEBUG_REG1_VGT_SQ_send_SHIFT) | \ + (mh_vgt_tag_7_q << VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT)) + +#define VGT_DEBUG_REG1_GET_out_te_data_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_te_data_read_MASK) >> VGT_DEBUG_REG1_out_te_data_read_SHIFT) +#define VGT_DEBUG_REG1_GET_te_out_data_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_te_out_data_valid_MASK) >> VGT_DEBUG_REG1_te_out_data_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_out_pt_prim_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_pt_prim_read_MASK) >> VGT_DEBUG_REG1_out_pt_prim_read_SHIFT) +#define VGT_DEBUG_REG1_GET_pt_out_prim_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_out_prim_valid_MASK) >> VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_out_pt_data_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_pt_data_read_MASK) >> VGT_DEBUG_REG1_out_pt_data_read_SHIFT) +#define VGT_DEBUG_REG1_GET_pt_out_indx_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_out_indx_valid_MASK) >> VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_out_vr_prim_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_vr_prim_read_MASK) >> VGT_DEBUG_REG1_out_vr_prim_read_SHIFT) +#define VGT_DEBUG_REG1_GET_vr_out_prim_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_out_prim_valid_MASK) >> VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_out_vr_indx_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_vr_indx_read_MASK) >> VGT_DEBUG_REG1_out_vr_indx_read_SHIFT) +#define VGT_DEBUG_REG1_GET_vr_out_indx_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_out_indx_valid_MASK) >> VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_te_grp_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_te_grp_read_MASK) >> VGT_DEBUG_REG1_te_grp_read_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_te_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_te_valid_MASK) >> VGT_DEBUG_REG1_grp_te_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_pt_grp_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_grp_read_MASK) >> VGT_DEBUG_REG1_pt_grp_read_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_pt_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_pt_valid_MASK) >> VGT_DEBUG_REG1_grp_pt_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_vr_grp_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_grp_read_MASK) >> VGT_DEBUG_REG1_vr_grp_read_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_vr_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_vr_valid_MASK) >> VGT_DEBUG_REG1_grp_vr_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_dma_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_dma_read_MASK) >> VGT_DEBUG_REG1_grp_dma_read_SHIFT) +#define VGT_DEBUG_REG1_GET_dma_grp_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_dma_grp_valid_MASK) >> VGT_DEBUG_REG1_dma_grp_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_rbiu_di_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_rbiu_di_read_MASK) >> VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT) +#define VGT_DEBUG_REG1_GET_rbiu_grp_di_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK) >> VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_MH_VGT_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_MH_VGT_rtr_MASK) >> VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_MH_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_MH_send_MASK) >> VGT_DEBUG_REG1_VGT_MH_send_SHIFT) +#define VGT_DEBUG_REG1_GET_PA_VGT_clip_s_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_PA_clip_s_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT) +#define VGT_DEBUG_REG1_GET_PA_VGT_clip_p_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_PA_clip_p_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT) +#define VGT_DEBUG_REG1_GET_PA_VGT_clip_v_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_PA_clip_v_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT) +#define VGT_DEBUG_REG1_GET_SQ_VGT_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_SQ_VGT_rtr_MASK) >> VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_SQ_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_SQ_send_MASK) >> VGT_DEBUG_REG1_VGT_SQ_send_SHIFT) +#define VGT_DEBUG_REG1_GET_mh_vgt_tag_7_q(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) >> VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT) + +#define VGT_DEBUG_REG1_SET_out_te_data_read(vgt_debug_reg1_reg, out_te_data_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_te_data_read_MASK) | (out_te_data_read << VGT_DEBUG_REG1_out_te_data_read_SHIFT) +#define VGT_DEBUG_REG1_SET_te_out_data_valid(vgt_debug_reg1_reg, te_out_data_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_te_out_data_valid_MASK) | (te_out_data_valid << VGT_DEBUG_REG1_te_out_data_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_out_pt_prim_read(vgt_debug_reg1_reg, out_pt_prim_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_pt_prim_read_MASK) | (out_pt_prim_read << VGT_DEBUG_REG1_out_pt_prim_read_SHIFT) +#define VGT_DEBUG_REG1_SET_pt_out_prim_valid(vgt_debug_reg1_reg, pt_out_prim_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_out_prim_valid_MASK) | (pt_out_prim_valid << VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_out_pt_data_read(vgt_debug_reg1_reg, out_pt_data_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_pt_data_read_MASK) | (out_pt_data_read << VGT_DEBUG_REG1_out_pt_data_read_SHIFT) +#define VGT_DEBUG_REG1_SET_pt_out_indx_valid(vgt_debug_reg1_reg, pt_out_indx_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_out_indx_valid_MASK) | (pt_out_indx_valid << VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_out_vr_prim_read(vgt_debug_reg1_reg, out_vr_prim_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_vr_prim_read_MASK) | (out_vr_prim_read << VGT_DEBUG_REG1_out_vr_prim_read_SHIFT) +#define VGT_DEBUG_REG1_SET_vr_out_prim_valid(vgt_debug_reg1_reg, vr_out_prim_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_out_prim_valid_MASK) | (vr_out_prim_valid << VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_out_vr_indx_read(vgt_debug_reg1_reg, out_vr_indx_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_vr_indx_read_MASK) | (out_vr_indx_read << VGT_DEBUG_REG1_out_vr_indx_read_SHIFT) +#define VGT_DEBUG_REG1_SET_vr_out_indx_valid(vgt_debug_reg1_reg, vr_out_indx_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_out_indx_valid_MASK) | (vr_out_indx_valid << VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_te_grp_read(vgt_debug_reg1_reg, te_grp_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_te_grp_read_MASK) | (te_grp_read << VGT_DEBUG_REG1_te_grp_read_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_te_valid(vgt_debug_reg1_reg, grp_te_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_te_valid_MASK) | (grp_te_valid << VGT_DEBUG_REG1_grp_te_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_pt_grp_read(vgt_debug_reg1_reg, pt_grp_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_grp_read_MASK) | (pt_grp_read << VGT_DEBUG_REG1_pt_grp_read_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_pt_valid(vgt_debug_reg1_reg, grp_pt_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_pt_valid_MASK) | (grp_pt_valid << VGT_DEBUG_REG1_grp_pt_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_vr_grp_read(vgt_debug_reg1_reg, vr_grp_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_grp_read_MASK) | (vr_grp_read << VGT_DEBUG_REG1_vr_grp_read_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_vr_valid(vgt_debug_reg1_reg, grp_vr_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_vr_valid_MASK) | (grp_vr_valid << VGT_DEBUG_REG1_grp_vr_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_dma_read(vgt_debug_reg1_reg, grp_dma_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_dma_read_MASK) | (grp_dma_read << VGT_DEBUG_REG1_grp_dma_read_SHIFT) +#define VGT_DEBUG_REG1_SET_dma_grp_valid(vgt_debug_reg1_reg, dma_grp_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_dma_grp_valid_MASK) | (dma_grp_valid << VGT_DEBUG_REG1_dma_grp_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_rbiu_di_read(vgt_debug_reg1_reg, grp_rbiu_di_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_rbiu_di_read_MASK) | (grp_rbiu_di_read << VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT) +#define VGT_DEBUG_REG1_SET_rbiu_grp_di_valid(vgt_debug_reg1_reg, rbiu_grp_di_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK) | (rbiu_grp_di_valid << VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_MH_VGT_rtr(vgt_debug_reg1_reg, mh_vgt_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_MH_VGT_rtr_MASK) | (mh_vgt_rtr << VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_MH_send(vgt_debug_reg1_reg, vgt_mh_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_MH_send_MASK) | (vgt_mh_send << VGT_DEBUG_REG1_VGT_MH_send_SHIFT) +#define VGT_DEBUG_REG1_SET_PA_VGT_clip_s_rtr(vgt_debug_reg1_reg, pa_vgt_clip_s_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK) | (pa_vgt_clip_s_rtr << VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_PA_clip_s_send(vgt_debug_reg1_reg, vgt_pa_clip_s_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK) | (vgt_pa_clip_s_send << VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT) +#define VGT_DEBUG_REG1_SET_PA_VGT_clip_p_rtr(vgt_debug_reg1_reg, pa_vgt_clip_p_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK) | (pa_vgt_clip_p_rtr << VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_PA_clip_p_send(vgt_debug_reg1_reg, vgt_pa_clip_p_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK) | (vgt_pa_clip_p_send << VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT) +#define VGT_DEBUG_REG1_SET_PA_VGT_clip_v_rtr(vgt_debug_reg1_reg, pa_vgt_clip_v_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK) | (pa_vgt_clip_v_rtr << VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_PA_clip_v_send(vgt_debug_reg1_reg, vgt_pa_clip_v_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK) | (vgt_pa_clip_v_send << VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT) +#define VGT_DEBUG_REG1_SET_SQ_VGT_rtr(vgt_debug_reg1_reg, sq_vgt_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_SQ_VGT_rtr_MASK) | (sq_vgt_rtr << VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_SQ_send(vgt_debug_reg1_reg, vgt_sq_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_SQ_send_MASK) | (vgt_sq_send << VGT_DEBUG_REG1_VGT_SQ_send_SHIFT) +#define VGT_DEBUG_REG1_SET_mh_vgt_tag_7_q(vgt_debug_reg1_reg, mh_vgt_tag_7_q) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) | (mh_vgt_tag_7_q << VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg1_t { + unsigned int out_te_data_read : VGT_DEBUG_REG1_out_te_data_read_SIZE; + unsigned int te_out_data_valid : VGT_DEBUG_REG1_te_out_data_valid_SIZE; + unsigned int out_pt_prim_read : VGT_DEBUG_REG1_out_pt_prim_read_SIZE; + unsigned int pt_out_prim_valid : VGT_DEBUG_REG1_pt_out_prim_valid_SIZE; + unsigned int out_pt_data_read : VGT_DEBUG_REG1_out_pt_data_read_SIZE; + unsigned int pt_out_indx_valid : VGT_DEBUG_REG1_pt_out_indx_valid_SIZE; + unsigned int out_vr_prim_read : VGT_DEBUG_REG1_out_vr_prim_read_SIZE; + unsigned int vr_out_prim_valid : VGT_DEBUG_REG1_vr_out_prim_valid_SIZE; + unsigned int out_vr_indx_read : VGT_DEBUG_REG1_out_vr_indx_read_SIZE; + unsigned int vr_out_indx_valid : VGT_DEBUG_REG1_vr_out_indx_valid_SIZE; + unsigned int te_grp_read : VGT_DEBUG_REG1_te_grp_read_SIZE; + unsigned int grp_te_valid : VGT_DEBUG_REG1_grp_te_valid_SIZE; + unsigned int pt_grp_read : VGT_DEBUG_REG1_pt_grp_read_SIZE; + unsigned int grp_pt_valid : VGT_DEBUG_REG1_grp_pt_valid_SIZE; + unsigned int vr_grp_read : VGT_DEBUG_REG1_vr_grp_read_SIZE; + unsigned int grp_vr_valid : VGT_DEBUG_REG1_grp_vr_valid_SIZE; + unsigned int grp_dma_read : VGT_DEBUG_REG1_grp_dma_read_SIZE; + unsigned int dma_grp_valid : VGT_DEBUG_REG1_dma_grp_valid_SIZE; + unsigned int grp_rbiu_di_read : VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE; + unsigned int rbiu_grp_di_valid : VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE; + unsigned int mh_vgt_rtr : VGT_DEBUG_REG1_MH_VGT_rtr_SIZE; + unsigned int vgt_mh_send : VGT_DEBUG_REG1_VGT_MH_send_SIZE; + unsigned int pa_vgt_clip_s_rtr : VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE; + unsigned int vgt_pa_clip_s_send : VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE; + unsigned int pa_vgt_clip_p_rtr : VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE; + unsigned int vgt_pa_clip_p_send : VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE; + unsigned int pa_vgt_clip_v_rtr : VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE; + unsigned int vgt_pa_clip_v_send : VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE; + unsigned int sq_vgt_rtr : VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE; + unsigned int vgt_sq_send : VGT_DEBUG_REG1_VGT_SQ_send_SIZE; + unsigned int mh_vgt_tag_7_q : VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE; + unsigned int : 1; + } vgt_debug_reg1_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg1_t { + unsigned int : 1; + unsigned int mh_vgt_tag_7_q : VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE; + unsigned int vgt_sq_send : VGT_DEBUG_REG1_VGT_SQ_send_SIZE; + unsigned int sq_vgt_rtr : VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE; + unsigned int vgt_pa_clip_v_send : VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE; + unsigned int pa_vgt_clip_v_rtr : VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE; + unsigned int vgt_pa_clip_p_send : VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE; + unsigned int pa_vgt_clip_p_rtr : VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE; + unsigned int vgt_pa_clip_s_send : VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE; + unsigned int pa_vgt_clip_s_rtr : VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE; + unsigned int vgt_mh_send : VGT_DEBUG_REG1_VGT_MH_send_SIZE; + unsigned int mh_vgt_rtr : VGT_DEBUG_REG1_MH_VGT_rtr_SIZE; + unsigned int rbiu_grp_di_valid : VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE; + unsigned int grp_rbiu_di_read : VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE; + unsigned int dma_grp_valid : VGT_DEBUG_REG1_dma_grp_valid_SIZE; + unsigned int grp_dma_read : VGT_DEBUG_REG1_grp_dma_read_SIZE; + unsigned int grp_vr_valid : VGT_DEBUG_REG1_grp_vr_valid_SIZE; + unsigned int vr_grp_read : VGT_DEBUG_REG1_vr_grp_read_SIZE; + unsigned int grp_pt_valid : VGT_DEBUG_REG1_grp_pt_valid_SIZE; + unsigned int pt_grp_read : VGT_DEBUG_REG1_pt_grp_read_SIZE; + unsigned int grp_te_valid : VGT_DEBUG_REG1_grp_te_valid_SIZE; + unsigned int te_grp_read : VGT_DEBUG_REG1_te_grp_read_SIZE; + unsigned int vr_out_indx_valid : VGT_DEBUG_REG1_vr_out_indx_valid_SIZE; + unsigned int out_vr_indx_read : VGT_DEBUG_REG1_out_vr_indx_read_SIZE; + unsigned int vr_out_prim_valid : VGT_DEBUG_REG1_vr_out_prim_valid_SIZE; + unsigned int out_vr_prim_read : VGT_DEBUG_REG1_out_vr_prim_read_SIZE; + unsigned int pt_out_indx_valid : VGT_DEBUG_REG1_pt_out_indx_valid_SIZE; + unsigned int out_pt_data_read : VGT_DEBUG_REG1_out_pt_data_read_SIZE; + unsigned int pt_out_prim_valid : VGT_DEBUG_REG1_pt_out_prim_valid_SIZE; + unsigned int out_pt_prim_read : VGT_DEBUG_REG1_out_pt_prim_read_SIZE; + unsigned int te_out_data_valid : VGT_DEBUG_REG1_te_out_data_valid_SIZE; + unsigned int out_te_data_read : VGT_DEBUG_REG1_out_te_data_read_SIZE; + } vgt_debug_reg1_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg1_t f; +} vgt_debug_reg1_u; + + +/* + * VGT_DEBUG_REG3 struct + */ + +#define VGT_DEBUG_REG3_vgt_clk_en_SIZE 1 +#define VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE 1 + +#define VGT_DEBUG_REG3_vgt_clk_en_SHIFT 0 +#define VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT 1 + +#define VGT_DEBUG_REG3_vgt_clk_en_MASK 0x00000001 +#define VGT_DEBUG_REG3_reg_fifos_clk_en_MASK 0x00000002 + +#define VGT_DEBUG_REG3_MASK \ + (VGT_DEBUG_REG3_vgt_clk_en_MASK | \ + VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) + +#define VGT_DEBUG_REG3(vgt_clk_en, reg_fifos_clk_en) \ + ((vgt_clk_en << VGT_DEBUG_REG3_vgt_clk_en_SHIFT) | \ + (reg_fifos_clk_en << VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT)) + +#define VGT_DEBUG_REG3_GET_vgt_clk_en(vgt_debug_reg3) \ + ((vgt_debug_reg3 & VGT_DEBUG_REG3_vgt_clk_en_MASK) >> VGT_DEBUG_REG3_vgt_clk_en_SHIFT) +#define VGT_DEBUG_REG3_GET_reg_fifos_clk_en(vgt_debug_reg3) \ + ((vgt_debug_reg3 & VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) >> VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT) + +#define VGT_DEBUG_REG3_SET_vgt_clk_en(vgt_debug_reg3_reg, vgt_clk_en) \ + vgt_debug_reg3_reg = (vgt_debug_reg3_reg & ~VGT_DEBUG_REG3_vgt_clk_en_MASK) | (vgt_clk_en << VGT_DEBUG_REG3_vgt_clk_en_SHIFT) +#define VGT_DEBUG_REG3_SET_reg_fifos_clk_en(vgt_debug_reg3_reg, reg_fifos_clk_en) \ + vgt_debug_reg3_reg = (vgt_debug_reg3_reg & ~VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) | (reg_fifos_clk_en << VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg3_t { + unsigned int vgt_clk_en : VGT_DEBUG_REG3_vgt_clk_en_SIZE; + unsigned int reg_fifos_clk_en : VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE; + unsigned int : 30; + } vgt_debug_reg3_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg3_t { + unsigned int : 30; + unsigned int reg_fifos_clk_en : VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE; + unsigned int vgt_clk_en : VGT_DEBUG_REG3_vgt_clk_en_SIZE; + } vgt_debug_reg3_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg3_t f; +} vgt_debug_reg3_u; + + +/* + * VGT_DEBUG_REG6 struct + */ + +#define VGT_DEBUG_REG6_shifter_byte_count_q_SIZE 5 +#define VGT_DEBUG_REG6_right_word_indx_q_SIZE 5 +#define VGT_DEBUG_REG6_input_data_valid_SIZE 1 +#define VGT_DEBUG_REG6_input_data_xfer_SIZE 1 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE 1 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE 1 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE 1 +#define VGT_DEBUG_REG6_space_avail_from_shift_SIZE 1 +#define VGT_DEBUG_REG6_shifter_first_load_SIZE 1 +#define VGT_DEBUG_REG6_di_state_sel_q_SIZE 1 +#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE 1 +#define VGT_DEBUG_REG6_di_first_group_flag_q_SIZE 1 +#define VGT_DEBUG_REG6_di_event_flag_q_SIZE 1 +#define VGT_DEBUG_REG6_read_draw_initiator_SIZE 1 +#define VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE 1 +#define VGT_DEBUG_REG6_last_shift_of_packet_SIZE 1 +#define VGT_DEBUG_REG6_last_decr_of_packet_SIZE 1 +#define VGT_DEBUG_REG6_extract_vector_SIZE 1 +#define VGT_DEBUG_REG6_shift_vect_rtr_SIZE 1 +#define VGT_DEBUG_REG6_destination_rtr_SIZE 1 +#define VGT_DEBUG_REG6_grp_trigger_SIZE 1 + +#define VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT 0 +#define VGT_DEBUG_REG6_right_word_indx_q_SHIFT 5 +#define VGT_DEBUG_REG6_input_data_valid_SHIFT 10 +#define VGT_DEBUG_REG6_input_data_xfer_SHIFT 11 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT 12 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT 13 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT 14 +#define VGT_DEBUG_REG6_space_avail_from_shift_SHIFT 15 +#define VGT_DEBUG_REG6_shifter_first_load_SHIFT 16 +#define VGT_DEBUG_REG6_di_state_sel_q_SHIFT 17 +#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT 18 +#define VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT 19 +#define VGT_DEBUG_REG6_di_event_flag_q_SHIFT 20 +#define VGT_DEBUG_REG6_read_draw_initiator_SHIFT 21 +#define VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT 22 +#define VGT_DEBUG_REG6_last_shift_of_packet_SHIFT 23 +#define VGT_DEBUG_REG6_last_decr_of_packet_SHIFT 24 +#define VGT_DEBUG_REG6_extract_vector_SHIFT 25 +#define VGT_DEBUG_REG6_shift_vect_rtr_SHIFT 26 +#define VGT_DEBUG_REG6_destination_rtr_SHIFT 27 +#define VGT_DEBUG_REG6_grp_trigger_SHIFT 28 + +#define VGT_DEBUG_REG6_shifter_byte_count_q_MASK 0x0000001f +#define VGT_DEBUG_REG6_right_word_indx_q_MASK 0x000003e0 +#define VGT_DEBUG_REG6_input_data_valid_MASK 0x00000400 +#define VGT_DEBUG_REG6_input_data_xfer_MASK 0x00000800 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK 0x00001000 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK 0x00002000 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK 0x00004000 +#define VGT_DEBUG_REG6_space_avail_from_shift_MASK 0x00008000 +#define VGT_DEBUG_REG6_shifter_first_load_MASK 0x00010000 +#define VGT_DEBUG_REG6_di_state_sel_q_MASK 0x00020000 +#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK 0x00040000 +#define VGT_DEBUG_REG6_di_first_group_flag_q_MASK 0x00080000 +#define VGT_DEBUG_REG6_di_event_flag_q_MASK 0x00100000 +#define VGT_DEBUG_REG6_read_draw_initiator_MASK 0x00200000 +#define VGT_DEBUG_REG6_loading_di_requires_shifter_MASK 0x00400000 +#define VGT_DEBUG_REG6_last_shift_of_packet_MASK 0x00800000 +#define VGT_DEBUG_REG6_last_decr_of_packet_MASK 0x01000000 +#define VGT_DEBUG_REG6_extract_vector_MASK 0x02000000 +#define VGT_DEBUG_REG6_shift_vect_rtr_MASK 0x04000000 +#define VGT_DEBUG_REG6_destination_rtr_MASK 0x08000000 +#define VGT_DEBUG_REG6_grp_trigger_MASK 0x10000000 + +#define VGT_DEBUG_REG6_MASK \ + (VGT_DEBUG_REG6_shifter_byte_count_q_MASK | \ + VGT_DEBUG_REG6_right_word_indx_q_MASK | \ + VGT_DEBUG_REG6_input_data_valid_MASK | \ + VGT_DEBUG_REG6_input_data_xfer_MASK | \ + VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK | \ + VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK | \ + VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK | \ + VGT_DEBUG_REG6_space_avail_from_shift_MASK | \ + VGT_DEBUG_REG6_shifter_first_load_MASK | \ + VGT_DEBUG_REG6_di_state_sel_q_MASK | \ + VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK | \ + VGT_DEBUG_REG6_di_first_group_flag_q_MASK | \ + VGT_DEBUG_REG6_di_event_flag_q_MASK | \ + VGT_DEBUG_REG6_read_draw_initiator_MASK | \ + VGT_DEBUG_REG6_loading_di_requires_shifter_MASK | \ + VGT_DEBUG_REG6_last_shift_of_packet_MASK | \ + VGT_DEBUG_REG6_last_decr_of_packet_MASK | \ + VGT_DEBUG_REG6_extract_vector_MASK | \ + VGT_DEBUG_REG6_shift_vect_rtr_MASK | \ + VGT_DEBUG_REG6_destination_rtr_MASK | \ + VGT_DEBUG_REG6_grp_trigger_MASK) + +#define VGT_DEBUG_REG6(shifter_byte_count_q, right_word_indx_q, input_data_valid, input_data_xfer, next_shift_is_vect_1_q, next_shift_is_vect_1_d, next_shift_is_vect_1_pre_d, space_avail_from_shift, shifter_first_load, di_state_sel_q, shifter_waiting_for_first_load_q, di_first_group_flag_q, di_event_flag_q, read_draw_initiator, loading_di_requires_shifter, last_shift_of_packet, last_decr_of_packet, extract_vector, shift_vect_rtr, destination_rtr, grp_trigger) \ + ((shifter_byte_count_q << VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT) | \ + (right_word_indx_q << VGT_DEBUG_REG6_right_word_indx_q_SHIFT) | \ + (input_data_valid << VGT_DEBUG_REG6_input_data_valid_SHIFT) | \ + (input_data_xfer << VGT_DEBUG_REG6_input_data_xfer_SHIFT) | \ + (next_shift_is_vect_1_q << VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT) | \ + (next_shift_is_vect_1_d << VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT) | \ + (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT) | \ + (space_avail_from_shift << VGT_DEBUG_REG6_space_avail_from_shift_SHIFT) | \ + (shifter_first_load << VGT_DEBUG_REG6_shifter_first_load_SHIFT) | \ + (di_state_sel_q << VGT_DEBUG_REG6_di_state_sel_q_SHIFT) | \ + (shifter_waiting_for_first_load_q << VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT) | \ + (di_first_group_flag_q << VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT) | \ + (di_event_flag_q << VGT_DEBUG_REG6_di_event_flag_q_SHIFT) | \ + (read_draw_initiator << VGT_DEBUG_REG6_read_draw_initiator_SHIFT) | \ + (loading_di_requires_shifter << VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT) | \ + (last_shift_of_packet << VGT_DEBUG_REG6_last_shift_of_packet_SHIFT) | \ + (last_decr_of_packet << VGT_DEBUG_REG6_last_decr_of_packet_SHIFT) | \ + (extract_vector << VGT_DEBUG_REG6_extract_vector_SHIFT) | \ + (shift_vect_rtr << VGT_DEBUG_REG6_shift_vect_rtr_SHIFT) | \ + (destination_rtr << VGT_DEBUG_REG6_destination_rtr_SHIFT) | \ + (grp_trigger << VGT_DEBUG_REG6_grp_trigger_SHIFT)) + +#define VGT_DEBUG_REG6_GET_shifter_byte_count_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_byte_count_q_MASK) >> VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT) +#define VGT_DEBUG_REG6_GET_right_word_indx_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_right_word_indx_q_MASK) >> VGT_DEBUG_REG6_right_word_indx_q_SHIFT) +#define VGT_DEBUG_REG6_GET_input_data_valid(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_input_data_valid_MASK) >> VGT_DEBUG_REG6_input_data_valid_SHIFT) +#define VGT_DEBUG_REG6_GET_input_data_xfer(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_input_data_xfer_MASK) >> VGT_DEBUG_REG6_input_data_xfer_SHIFT) +#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT) +#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_d(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT) +#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_pre_d(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT) +#define VGT_DEBUG_REG6_GET_space_avail_from_shift(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_space_avail_from_shift_MASK) >> VGT_DEBUG_REG6_space_avail_from_shift_SHIFT) +#define VGT_DEBUG_REG6_GET_shifter_first_load(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_first_load_MASK) >> VGT_DEBUG_REG6_shifter_first_load_SHIFT) +#define VGT_DEBUG_REG6_GET_di_state_sel_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_state_sel_q_MASK) >> VGT_DEBUG_REG6_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG6_GET_shifter_waiting_for_first_load_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK) >> VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT) +#define VGT_DEBUG_REG6_GET_di_first_group_flag_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_first_group_flag_q_MASK) >> VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT) +#define VGT_DEBUG_REG6_GET_di_event_flag_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_event_flag_q_MASK) >> VGT_DEBUG_REG6_di_event_flag_q_SHIFT) +#define VGT_DEBUG_REG6_GET_read_draw_initiator(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_read_draw_initiator_MASK) >> VGT_DEBUG_REG6_read_draw_initiator_SHIFT) +#define VGT_DEBUG_REG6_GET_loading_di_requires_shifter(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_loading_di_requires_shifter_MASK) >> VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT) +#define VGT_DEBUG_REG6_GET_last_shift_of_packet(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_last_shift_of_packet_MASK) >> VGT_DEBUG_REG6_last_shift_of_packet_SHIFT) +#define VGT_DEBUG_REG6_GET_last_decr_of_packet(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_last_decr_of_packet_MASK) >> VGT_DEBUG_REG6_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG6_GET_extract_vector(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_extract_vector_MASK) >> VGT_DEBUG_REG6_extract_vector_SHIFT) +#define VGT_DEBUG_REG6_GET_shift_vect_rtr(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_shift_vect_rtr_MASK) >> VGT_DEBUG_REG6_shift_vect_rtr_SHIFT) +#define VGT_DEBUG_REG6_GET_destination_rtr(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_destination_rtr_MASK) >> VGT_DEBUG_REG6_destination_rtr_SHIFT) +#define VGT_DEBUG_REG6_GET_grp_trigger(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_grp_trigger_MASK) >> VGT_DEBUG_REG6_grp_trigger_SHIFT) + +#define VGT_DEBUG_REG6_SET_shifter_byte_count_q(vgt_debug_reg6_reg, shifter_byte_count_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_byte_count_q_MASK) | (shifter_byte_count_q << VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT) +#define VGT_DEBUG_REG6_SET_right_word_indx_q(vgt_debug_reg6_reg, right_word_indx_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_right_word_indx_q_MASK) | (right_word_indx_q << VGT_DEBUG_REG6_right_word_indx_q_SHIFT) +#define VGT_DEBUG_REG6_SET_input_data_valid(vgt_debug_reg6_reg, input_data_valid) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_input_data_valid_MASK) | (input_data_valid << VGT_DEBUG_REG6_input_data_valid_SHIFT) +#define VGT_DEBUG_REG6_SET_input_data_xfer(vgt_debug_reg6_reg, input_data_xfer) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_input_data_xfer_MASK) | (input_data_xfer << VGT_DEBUG_REG6_input_data_xfer_SHIFT) +#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_q(vgt_debug_reg6_reg, next_shift_is_vect_1_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK) | (next_shift_is_vect_1_q << VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT) +#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_d(vgt_debug_reg6_reg, next_shift_is_vect_1_d) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK) | (next_shift_is_vect_1_d << VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT) +#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_pre_d(vgt_debug_reg6_reg, next_shift_is_vect_1_pre_d) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK) | (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT) +#define VGT_DEBUG_REG6_SET_space_avail_from_shift(vgt_debug_reg6_reg, space_avail_from_shift) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_space_avail_from_shift_MASK) | (space_avail_from_shift << VGT_DEBUG_REG6_space_avail_from_shift_SHIFT) +#define VGT_DEBUG_REG6_SET_shifter_first_load(vgt_debug_reg6_reg, shifter_first_load) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_first_load_MASK) | (shifter_first_load << VGT_DEBUG_REG6_shifter_first_load_SHIFT) +#define VGT_DEBUG_REG6_SET_di_state_sel_q(vgt_debug_reg6_reg, di_state_sel_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG6_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG6_SET_shifter_waiting_for_first_load_q(vgt_debug_reg6_reg, shifter_waiting_for_first_load_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK) | (shifter_waiting_for_first_load_q << VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT) +#define VGT_DEBUG_REG6_SET_di_first_group_flag_q(vgt_debug_reg6_reg, di_first_group_flag_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_first_group_flag_q_MASK) | (di_first_group_flag_q << VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT) +#define VGT_DEBUG_REG6_SET_di_event_flag_q(vgt_debug_reg6_reg, di_event_flag_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_event_flag_q_MASK) | (di_event_flag_q << VGT_DEBUG_REG6_di_event_flag_q_SHIFT) +#define VGT_DEBUG_REG6_SET_read_draw_initiator(vgt_debug_reg6_reg, read_draw_initiator) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_read_draw_initiator_MASK) | (read_draw_initiator << VGT_DEBUG_REG6_read_draw_initiator_SHIFT) +#define VGT_DEBUG_REG6_SET_loading_di_requires_shifter(vgt_debug_reg6_reg, loading_di_requires_shifter) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_loading_di_requires_shifter_MASK) | (loading_di_requires_shifter << VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT) +#define VGT_DEBUG_REG6_SET_last_shift_of_packet(vgt_debug_reg6_reg, last_shift_of_packet) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_last_shift_of_packet_MASK) | (last_shift_of_packet << VGT_DEBUG_REG6_last_shift_of_packet_SHIFT) +#define VGT_DEBUG_REG6_SET_last_decr_of_packet(vgt_debug_reg6_reg, last_decr_of_packet) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG6_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG6_SET_extract_vector(vgt_debug_reg6_reg, extract_vector) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_extract_vector_MASK) | (extract_vector << VGT_DEBUG_REG6_extract_vector_SHIFT) +#define VGT_DEBUG_REG6_SET_shift_vect_rtr(vgt_debug_reg6_reg, shift_vect_rtr) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shift_vect_rtr_MASK) | (shift_vect_rtr << VGT_DEBUG_REG6_shift_vect_rtr_SHIFT) +#define VGT_DEBUG_REG6_SET_destination_rtr(vgt_debug_reg6_reg, destination_rtr) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_destination_rtr_MASK) | (destination_rtr << VGT_DEBUG_REG6_destination_rtr_SHIFT) +#define VGT_DEBUG_REG6_SET_grp_trigger(vgt_debug_reg6_reg, grp_trigger) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG6_grp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg6_t { + unsigned int shifter_byte_count_q : VGT_DEBUG_REG6_shifter_byte_count_q_SIZE; + unsigned int right_word_indx_q : VGT_DEBUG_REG6_right_word_indx_q_SIZE; + unsigned int input_data_valid : VGT_DEBUG_REG6_input_data_valid_SIZE; + unsigned int input_data_xfer : VGT_DEBUG_REG6_input_data_xfer_SIZE; + unsigned int next_shift_is_vect_1_q : VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE; + unsigned int next_shift_is_vect_1_d : VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE; + unsigned int next_shift_is_vect_1_pre_d : VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE; + unsigned int space_avail_from_shift : VGT_DEBUG_REG6_space_avail_from_shift_SIZE; + unsigned int shifter_first_load : VGT_DEBUG_REG6_shifter_first_load_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG6_di_state_sel_q_SIZE; + unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE; + unsigned int di_first_group_flag_q : VGT_DEBUG_REG6_di_first_group_flag_q_SIZE; + unsigned int di_event_flag_q : VGT_DEBUG_REG6_di_event_flag_q_SIZE; + unsigned int read_draw_initiator : VGT_DEBUG_REG6_read_draw_initiator_SIZE; + unsigned int loading_di_requires_shifter : VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE; + unsigned int last_shift_of_packet : VGT_DEBUG_REG6_last_shift_of_packet_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG6_last_decr_of_packet_SIZE; + unsigned int extract_vector : VGT_DEBUG_REG6_extract_vector_SIZE; + unsigned int shift_vect_rtr : VGT_DEBUG_REG6_shift_vect_rtr_SIZE; + unsigned int destination_rtr : VGT_DEBUG_REG6_destination_rtr_SIZE; + unsigned int grp_trigger : VGT_DEBUG_REG6_grp_trigger_SIZE; + unsigned int : 3; + } vgt_debug_reg6_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg6_t { + unsigned int : 3; + unsigned int grp_trigger : VGT_DEBUG_REG6_grp_trigger_SIZE; + unsigned int destination_rtr : VGT_DEBUG_REG6_destination_rtr_SIZE; + unsigned int shift_vect_rtr : VGT_DEBUG_REG6_shift_vect_rtr_SIZE; + unsigned int extract_vector : VGT_DEBUG_REG6_extract_vector_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG6_last_decr_of_packet_SIZE; + unsigned int last_shift_of_packet : VGT_DEBUG_REG6_last_shift_of_packet_SIZE; + unsigned int loading_di_requires_shifter : VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE; + unsigned int read_draw_initiator : VGT_DEBUG_REG6_read_draw_initiator_SIZE; + unsigned int di_event_flag_q : VGT_DEBUG_REG6_di_event_flag_q_SIZE; + unsigned int di_first_group_flag_q : VGT_DEBUG_REG6_di_first_group_flag_q_SIZE; + unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG6_di_state_sel_q_SIZE; + unsigned int shifter_first_load : VGT_DEBUG_REG6_shifter_first_load_SIZE; + unsigned int space_avail_from_shift : VGT_DEBUG_REG6_space_avail_from_shift_SIZE; + unsigned int next_shift_is_vect_1_pre_d : VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE; + unsigned int next_shift_is_vect_1_d : VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE; + unsigned int next_shift_is_vect_1_q : VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE; + unsigned int input_data_xfer : VGT_DEBUG_REG6_input_data_xfer_SIZE; + unsigned int input_data_valid : VGT_DEBUG_REG6_input_data_valid_SIZE; + unsigned int right_word_indx_q : VGT_DEBUG_REG6_right_word_indx_q_SIZE; + unsigned int shifter_byte_count_q : VGT_DEBUG_REG6_shifter_byte_count_q_SIZE; + } vgt_debug_reg6_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg6_t f; +} vgt_debug_reg6_u; + + +/* + * VGT_DEBUG_REG7 struct + */ + +#define VGT_DEBUG_REG7_di_index_counter_q_SIZE 16 +#define VGT_DEBUG_REG7_shift_amount_no_extract_SIZE 4 +#define VGT_DEBUG_REG7_shift_amount_extract_SIZE 4 +#define VGT_DEBUG_REG7_di_prim_type_q_SIZE 6 +#define VGT_DEBUG_REG7_current_source_sel_SIZE 2 + +#define VGT_DEBUG_REG7_di_index_counter_q_SHIFT 0 +#define VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT 16 +#define VGT_DEBUG_REG7_shift_amount_extract_SHIFT 20 +#define VGT_DEBUG_REG7_di_prim_type_q_SHIFT 24 +#define VGT_DEBUG_REG7_current_source_sel_SHIFT 30 + +#define VGT_DEBUG_REG7_di_index_counter_q_MASK 0x0000ffff +#define VGT_DEBUG_REG7_shift_amount_no_extract_MASK 0x000f0000 +#define VGT_DEBUG_REG7_shift_amount_extract_MASK 0x00f00000 +#define VGT_DEBUG_REG7_di_prim_type_q_MASK 0x3f000000 +#define VGT_DEBUG_REG7_current_source_sel_MASK 0xc0000000 + +#define VGT_DEBUG_REG7_MASK \ + (VGT_DEBUG_REG7_di_index_counter_q_MASK | \ + VGT_DEBUG_REG7_shift_amount_no_extract_MASK | \ + VGT_DEBUG_REG7_shift_amount_extract_MASK | \ + VGT_DEBUG_REG7_di_prim_type_q_MASK | \ + VGT_DEBUG_REG7_current_source_sel_MASK) + +#define VGT_DEBUG_REG7(di_index_counter_q, shift_amount_no_extract, shift_amount_extract, di_prim_type_q, current_source_sel) \ + ((di_index_counter_q << VGT_DEBUG_REG7_di_index_counter_q_SHIFT) | \ + (shift_amount_no_extract << VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT) | \ + (shift_amount_extract << VGT_DEBUG_REG7_shift_amount_extract_SHIFT) | \ + (di_prim_type_q << VGT_DEBUG_REG7_di_prim_type_q_SHIFT) | \ + (current_source_sel << VGT_DEBUG_REG7_current_source_sel_SHIFT)) + +#define VGT_DEBUG_REG7_GET_di_index_counter_q(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_di_index_counter_q_MASK) >> VGT_DEBUG_REG7_di_index_counter_q_SHIFT) +#define VGT_DEBUG_REG7_GET_shift_amount_no_extract(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_shift_amount_no_extract_MASK) >> VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT) +#define VGT_DEBUG_REG7_GET_shift_amount_extract(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_shift_amount_extract_MASK) >> VGT_DEBUG_REG7_shift_amount_extract_SHIFT) +#define VGT_DEBUG_REG7_GET_di_prim_type_q(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_di_prim_type_q_MASK) >> VGT_DEBUG_REG7_di_prim_type_q_SHIFT) +#define VGT_DEBUG_REG7_GET_current_source_sel(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_current_source_sel_MASK) >> VGT_DEBUG_REG7_current_source_sel_SHIFT) + +#define VGT_DEBUG_REG7_SET_di_index_counter_q(vgt_debug_reg7_reg, di_index_counter_q) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_di_index_counter_q_MASK) | (di_index_counter_q << VGT_DEBUG_REG7_di_index_counter_q_SHIFT) +#define VGT_DEBUG_REG7_SET_shift_amount_no_extract(vgt_debug_reg7_reg, shift_amount_no_extract) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_shift_amount_no_extract_MASK) | (shift_amount_no_extract << VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT) +#define VGT_DEBUG_REG7_SET_shift_amount_extract(vgt_debug_reg7_reg, shift_amount_extract) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_shift_amount_extract_MASK) | (shift_amount_extract << VGT_DEBUG_REG7_shift_amount_extract_SHIFT) +#define VGT_DEBUG_REG7_SET_di_prim_type_q(vgt_debug_reg7_reg, di_prim_type_q) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_di_prim_type_q_MASK) | (di_prim_type_q << VGT_DEBUG_REG7_di_prim_type_q_SHIFT) +#define VGT_DEBUG_REG7_SET_current_source_sel(vgt_debug_reg7_reg, current_source_sel) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG7_current_source_sel_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg7_t { + unsigned int di_index_counter_q : VGT_DEBUG_REG7_di_index_counter_q_SIZE; + unsigned int shift_amount_no_extract : VGT_DEBUG_REG7_shift_amount_no_extract_SIZE; + unsigned int shift_amount_extract : VGT_DEBUG_REG7_shift_amount_extract_SIZE; + unsigned int di_prim_type_q : VGT_DEBUG_REG7_di_prim_type_q_SIZE; + unsigned int current_source_sel : VGT_DEBUG_REG7_current_source_sel_SIZE; + } vgt_debug_reg7_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg7_t { + unsigned int current_source_sel : VGT_DEBUG_REG7_current_source_sel_SIZE; + unsigned int di_prim_type_q : VGT_DEBUG_REG7_di_prim_type_q_SIZE; + unsigned int shift_amount_extract : VGT_DEBUG_REG7_shift_amount_extract_SIZE; + unsigned int shift_amount_no_extract : VGT_DEBUG_REG7_shift_amount_no_extract_SIZE; + unsigned int di_index_counter_q : VGT_DEBUG_REG7_di_index_counter_q_SIZE; + } vgt_debug_reg7_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg7_t f; +} vgt_debug_reg7_u; + + +/* + * VGT_DEBUG_REG8 struct + */ + +#define VGT_DEBUG_REG8_current_source_sel_SIZE 2 +#define VGT_DEBUG_REG8_left_word_indx_q_SIZE 5 +#define VGT_DEBUG_REG8_input_data_cnt_SIZE 5 +#define VGT_DEBUG_REG8_input_data_lsw_SIZE 5 +#define VGT_DEBUG_REG8_input_data_msw_SIZE 5 +#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE 5 +#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE 5 + +#define VGT_DEBUG_REG8_current_source_sel_SHIFT 0 +#define VGT_DEBUG_REG8_left_word_indx_q_SHIFT 2 +#define VGT_DEBUG_REG8_input_data_cnt_SHIFT 7 +#define VGT_DEBUG_REG8_input_data_lsw_SHIFT 12 +#define VGT_DEBUG_REG8_input_data_msw_SHIFT 17 +#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT 22 +#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT 27 + +#define VGT_DEBUG_REG8_current_source_sel_MASK 0x00000003 +#define VGT_DEBUG_REG8_left_word_indx_q_MASK 0x0000007c +#define VGT_DEBUG_REG8_input_data_cnt_MASK 0x00000f80 +#define VGT_DEBUG_REG8_input_data_lsw_MASK 0x0001f000 +#define VGT_DEBUG_REG8_input_data_msw_MASK 0x003e0000 +#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK 0x07c00000 +#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK 0xf8000000 + +#define VGT_DEBUG_REG8_MASK \ + (VGT_DEBUG_REG8_current_source_sel_MASK | \ + VGT_DEBUG_REG8_left_word_indx_q_MASK | \ + VGT_DEBUG_REG8_input_data_cnt_MASK | \ + VGT_DEBUG_REG8_input_data_lsw_MASK | \ + VGT_DEBUG_REG8_input_data_msw_MASK | \ + VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK | \ + VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) + +#define VGT_DEBUG_REG8(current_source_sel, left_word_indx_q, input_data_cnt, input_data_lsw, input_data_msw, next_small_stride_shift_limit_q, current_small_stride_shift_limit_q) \ + ((current_source_sel << VGT_DEBUG_REG8_current_source_sel_SHIFT) | \ + (left_word_indx_q << VGT_DEBUG_REG8_left_word_indx_q_SHIFT) | \ + (input_data_cnt << VGT_DEBUG_REG8_input_data_cnt_SHIFT) | \ + (input_data_lsw << VGT_DEBUG_REG8_input_data_lsw_SHIFT) | \ + (input_data_msw << VGT_DEBUG_REG8_input_data_msw_SHIFT) | \ + (next_small_stride_shift_limit_q << VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT) | \ + (current_small_stride_shift_limit_q << VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT)) + +#define VGT_DEBUG_REG8_GET_current_source_sel(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_current_source_sel_MASK) >> VGT_DEBUG_REG8_current_source_sel_SHIFT) +#define VGT_DEBUG_REG8_GET_left_word_indx_q(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_left_word_indx_q_MASK) >> VGT_DEBUG_REG8_left_word_indx_q_SHIFT) +#define VGT_DEBUG_REG8_GET_input_data_cnt(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_cnt_MASK) >> VGT_DEBUG_REG8_input_data_cnt_SHIFT) +#define VGT_DEBUG_REG8_GET_input_data_lsw(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_lsw_MASK) >> VGT_DEBUG_REG8_input_data_lsw_SHIFT) +#define VGT_DEBUG_REG8_GET_input_data_msw(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_msw_MASK) >> VGT_DEBUG_REG8_input_data_msw_SHIFT) +#define VGT_DEBUG_REG8_GET_next_small_stride_shift_limit_q(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT) +#define VGT_DEBUG_REG8_GET_current_small_stride_shift_limit_q(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT) + +#define VGT_DEBUG_REG8_SET_current_source_sel(vgt_debug_reg8_reg, current_source_sel) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG8_current_source_sel_SHIFT) +#define VGT_DEBUG_REG8_SET_left_word_indx_q(vgt_debug_reg8_reg, left_word_indx_q) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_left_word_indx_q_MASK) | (left_word_indx_q << VGT_DEBUG_REG8_left_word_indx_q_SHIFT) +#define VGT_DEBUG_REG8_SET_input_data_cnt(vgt_debug_reg8_reg, input_data_cnt) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_cnt_MASK) | (input_data_cnt << VGT_DEBUG_REG8_input_data_cnt_SHIFT) +#define VGT_DEBUG_REG8_SET_input_data_lsw(vgt_debug_reg8_reg, input_data_lsw) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_lsw_MASK) | (input_data_lsw << VGT_DEBUG_REG8_input_data_lsw_SHIFT) +#define VGT_DEBUG_REG8_SET_input_data_msw(vgt_debug_reg8_reg, input_data_msw) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_msw_MASK) | (input_data_msw << VGT_DEBUG_REG8_input_data_msw_SHIFT) +#define VGT_DEBUG_REG8_SET_next_small_stride_shift_limit_q(vgt_debug_reg8_reg, next_small_stride_shift_limit_q) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK) | (next_small_stride_shift_limit_q << VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT) +#define VGT_DEBUG_REG8_SET_current_small_stride_shift_limit_q(vgt_debug_reg8_reg, current_small_stride_shift_limit_q) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) | (current_small_stride_shift_limit_q << VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg8_t { + unsigned int current_source_sel : VGT_DEBUG_REG8_current_source_sel_SIZE; + unsigned int left_word_indx_q : VGT_DEBUG_REG8_left_word_indx_q_SIZE; + unsigned int input_data_cnt : VGT_DEBUG_REG8_input_data_cnt_SIZE; + unsigned int input_data_lsw : VGT_DEBUG_REG8_input_data_lsw_SIZE; + unsigned int input_data_msw : VGT_DEBUG_REG8_input_data_msw_SIZE; + unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE; + unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE; + } vgt_debug_reg8_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg8_t { + unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE; + unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE; + unsigned int input_data_msw : VGT_DEBUG_REG8_input_data_msw_SIZE; + unsigned int input_data_lsw : VGT_DEBUG_REG8_input_data_lsw_SIZE; + unsigned int input_data_cnt : VGT_DEBUG_REG8_input_data_cnt_SIZE; + unsigned int left_word_indx_q : VGT_DEBUG_REG8_left_word_indx_q_SIZE; + unsigned int current_source_sel : VGT_DEBUG_REG8_current_source_sel_SIZE; + } vgt_debug_reg8_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg8_t f; +} vgt_debug_reg8_u; + + +/* + * VGT_DEBUG_REG9 struct + */ + +#define VGT_DEBUG_REG9_next_stride_q_SIZE 5 +#define VGT_DEBUG_REG9_next_stride_d_SIZE 5 +#define VGT_DEBUG_REG9_current_shift_q_SIZE 5 +#define VGT_DEBUG_REG9_current_shift_d_SIZE 5 +#define VGT_DEBUG_REG9_current_stride_q_SIZE 5 +#define VGT_DEBUG_REG9_current_stride_d_SIZE 5 +#define VGT_DEBUG_REG9_grp_trigger_SIZE 1 + +#define VGT_DEBUG_REG9_next_stride_q_SHIFT 0 +#define VGT_DEBUG_REG9_next_stride_d_SHIFT 5 +#define VGT_DEBUG_REG9_current_shift_q_SHIFT 10 +#define VGT_DEBUG_REG9_current_shift_d_SHIFT 15 +#define VGT_DEBUG_REG9_current_stride_q_SHIFT 20 +#define VGT_DEBUG_REG9_current_stride_d_SHIFT 25 +#define VGT_DEBUG_REG9_grp_trigger_SHIFT 30 + +#define VGT_DEBUG_REG9_next_stride_q_MASK 0x0000001f +#define VGT_DEBUG_REG9_next_stride_d_MASK 0x000003e0 +#define VGT_DEBUG_REG9_current_shift_q_MASK 0x00007c00 +#define VGT_DEBUG_REG9_current_shift_d_MASK 0x000f8000 +#define VGT_DEBUG_REG9_current_stride_q_MASK 0x01f00000 +#define VGT_DEBUG_REG9_current_stride_d_MASK 0x3e000000 +#define VGT_DEBUG_REG9_grp_trigger_MASK 0x40000000 + +#define VGT_DEBUG_REG9_MASK \ + (VGT_DEBUG_REG9_next_stride_q_MASK | \ + VGT_DEBUG_REG9_next_stride_d_MASK | \ + VGT_DEBUG_REG9_current_shift_q_MASK | \ + VGT_DEBUG_REG9_current_shift_d_MASK | \ + VGT_DEBUG_REG9_current_stride_q_MASK | \ + VGT_DEBUG_REG9_current_stride_d_MASK | \ + VGT_DEBUG_REG9_grp_trigger_MASK) + +#define VGT_DEBUG_REG9(next_stride_q, next_stride_d, current_shift_q, current_shift_d, current_stride_q, current_stride_d, grp_trigger) \ + ((next_stride_q << VGT_DEBUG_REG9_next_stride_q_SHIFT) | \ + (next_stride_d << VGT_DEBUG_REG9_next_stride_d_SHIFT) | \ + (current_shift_q << VGT_DEBUG_REG9_current_shift_q_SHIFT) | \ + (current_shift_d << VGT_DEBUG_REG9_current_shift_d_SHIFT) | \ + (current_stride_q << VGT_DEBUG_REG9_current_stride_q_SHIFT) | \ + (current_stride_d << VGT_DEBUG_REG9_current_stride_d_SHIFT) | \ + (grp_trigger << VGT_DEBUG_REG9_grp_trigger_SHIFT)) + +#define VGT_DEBUG_REG9_GET_next_stride_q(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_next_stride_q_MASK) >> VGT_DEBUG_REG9_next_stride_q_SHIFT) +#define VGT_DEBUG_REG9_GET_next_stride_d(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_next_stride_d_MASK) >> VGT_DEBUG_REG9_next_stride_d_SHIFT) +#define VGT_DEBUG_REG9_GET_current_shift_q(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_shift_q_MASK) >> VGT_DEBUG_REG9_current_shift_q_SHIFT) +#define VGT_DEBUG_REG9_GET_current_shift_d(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_shift_d_MASK) >> VGT_DEBUG_REG9_current_shift_d_SHIFT) +#define VGT_DEBUG_REG9_GET_current_stride_q(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_stride_q_MASK) >> VGT_DEBUG_REG9_current_stride_q_SHIFT) +#define VGT_DEBUG_REG9_GET_current_stride_d(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_stride_d_MASK) >> VGT_DEBUG_REG9_current_stride_d_SHIFT) +#define VGT_DEBUG_REG9_GET_grp_trigger(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_grp_trigger_MASK) >> VGT_DEBUG_REG9_grp_trigger_SHIFT) + +#define VGT_DEBUG_REG9_SET_next_stride_q(vgt_debug_reg9_reg, next_stride_q) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_next_stride_q_MASK) | (next_stride_q << VGT_DEBUG_REG9_next_stride_q_SHIFT) +#define VGT_DEBUG_REG9_SET_next_stride_d(vgt_debug_reg9_reg, next_stride_d) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_next_stride_d_MASK) | (next_stride_d << VGT_DEBUG_REG9_next_stride_d_SHIFT) +#define VGT_DEBUG_REG9_SET_current_shift_q(vgt_debug_reg9_reg, current_shift_q) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_shift_q_MASK) | (current_shift_q << VGT_DEBUG_REG9_current_shift_q_SHIFT) +#define VGT_DEBUG_REG9_SET_current_shift_d(vgt_debug_reg9_reg, current_shift_d) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_shift_d_MASK) | (current_shift_d << VGT_DEBUG_REG9_current_shift_d_SHIFT) +#define VGT_DEBUG_REG9_SET_current_stride_q(vgt_debug_reg9_reg, current_stride_q) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_stride_q_MASK) | (current_stride_q << VGT_DEBUG_REG9_current_stride_q_SHIFT) +#define VGT_DEBUG_REG9_SET_current_stride_d(vgt_debug_reg9_reg, current_stride_d) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_stride_d_MASK) | (current_stride_d << VGT_DEBUG_REG9_current_stride_d_SHIFT) +#define VGT_DEBUG_REG9_SET_grp_trigger(vgt_debug_reg9_reg, grp_trigger) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG9_grp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg9_t { + unsigned int next_stride_q : VGT_DEBUG_REG9_next_stride_q_SIZE; + unsigned int next_stride_d : VGT_DEBUG_REG9_next_stride_d_SIZE; + unsigned int current_shift_q : VGT_DEBUG_REG9_current_shift_q_SIZE; + unsigned int current_shift_d : VGT_DEBUG_REG9_current_shift_d_SIZE; + unsigned int current_stride_q : VGT_DEBUG_REG9_current_stride_q_SIZE; + unsigned int current_stride_d : VGT_DEBUG_REG9_current_stride_d_SIZE; + unsigned int grp_trigger : VGT_DEBUG_REG9_grp_trigger_SIZE; + unsigned int : 1; + } vgt_debug_reg9_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg9_t { + unsigned int : 1; + unsigned int grp_trigger : VGT_DEBUG_REG9_grp_trigger_SIZE; + unsigned int current_stride_d : VGT_DEBUG_REG9_current_stride_d_SIZE; + unsigned int current_stride_q : VGT_DEBUG_REG9_current_stride_q_SIZE; + unsigned int current_shift_d : VGT_DEBUG_REG9_current_shift_d_SIZE; + unsigned int current_shift_q : VGT_DEBUG_REG9_current_shift_q_SIZE; + unsigned int next_stride_d : VGT_DEBUG_REG9_next_stride_d_SIZE; + unsigned int next_stride_q : VGT_DEBUG_REG9_next_stride_q_SIZE; + } vgt_debug_reg9_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg9_t f; +} vgt_debug_reg9_u; + + +/* + * VGT_DEBUG_REG10 struct + */ + +#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE 1 +#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE 1 +#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE 1 +#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE 1 +#define VGT_DEBUG_REG10_di_state_sel_q_SIZE 1 +#define VGT_DEBUG_REG10_last_decr_of_packet_SIZE 1 +#define VGT_DEBUG_REG10_bin_valid_SIZE 1 +#define VGT_DEBUG_REG10_read_block_SIZE 1 +#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE 1 +#define VGT_DEBUG_REG10_last_bit_enable_q_SIZE 1 +#define VGT_DEBUG_REG10_last_bit_end_di_q_SIZE 1 +#define VGT_DEBUG_REG10_selected_data_SIZE 8 +#define VGT_DEBUG_REG10_mask_input_data_SIZE 8 +#define VGT_DEBUG_REG10_gap_q_SIZE 1 +#define VGT_DEBUG_REG10_temp_mini_reset_z_SIZE 1 +#define VGT_DEBUG_REG10_temp_mini_reset_y_SIZE 1 +#define VGT_DEBUG_REG10_temp_mini_reset_x_SIZE 1 +#define VGT_DEBUG_REG10_grp_trigger_SIZE 1 + +#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT 0 +#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT 1 +#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT 2 +#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT 3 +#define VGT_DEBUG_REG10_di_state_sel_q_SHIFT 4 +#define VGT_DEBUG_REG10_last_decr_of_packet_SHIFT 5 +#define VGT_DEBUG_REG10_bin_valid_SHIFT 6 +#define VGT_DEBUG_REG10_read_block_SHIFT 7 +#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT 8 +#define VGT_DEBUG_REG10_last_bit_enable_q_SHIFT 9 +#define VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT 10 +#define VGT_DEBUG_REG10_selected_data_SHIFT 11 +#define VGT_DEBUG_REG10_mask_input_data_SHIFT 19 +#define VGT_DEBUG_REG10_gap_q_SHIFT 27 +#define VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT 28 +#define VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT 29 +#define VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT 30 +#define VGT_DEBUG_REG10_grp_trigger_SHIFT 31 + +#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK 0x00000001 +#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK 0x00000002 +#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK 0x00000004 +#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK 0x00000008 +#define VGT_DEBUG_REG10_di_state_sel_q_MASK 0x00000010 +#define VGT_DEBUG_REG10_last_decr_of_packet_MASK 0x00000020 +#define VGT_DEBUG_REG10_bin_valid_MASK 0x00000040 +#define VGT_DEBUG_REG10_read_block_MASK 0x00000080 +#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK 0x00000100 +#define VGT_DEBUG_REG10_last_bit_enable_q_MASK 0x00000200 +#define VGT_DEBUG_REG10_last_bit_end_di_q_MASK 0x00000400 +#define VGT_DEBUG_REG10_selected_data_MASK 0x0007f800 +#define VGT_DEBUG_REG10_mask_input_data_MASK 0x07f80000 +#define VGT_DEBUG_REG10_gap_q_MASK 0x08000000 +#define VGT_DEBUG_REG10_temp_mini_reset_z_MASK 0x10000000 +#define VGT_DEBUG_REG10_temp_mini_reset_y_MASK 0x20000000 +#define VGT_DEBUG_REG10_temp_mini_reset_x_MASK 0x40000000 +#define VGT_DEBUG_REG10_grp_trigger_MASK 0x80000000 + +#define VGT_DEBUG_REG10_MASK \ + (VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK | \ + VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK | \ + VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK | \ + VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK | \ + VGT_DEBUG_REG10_di_state_sel_q_MASK | \ + VGT_DEBUG_REG10_last_decr_of_packet_MASK | \ + VGT_DEBUG_REG10_bin_valid_MASK | \ + VGT_DEBUG_REG10_read_block_MASK | \ + VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK | \ + VGT_DEBUG_REG10_last_bit_enable_q_MASK | \ + VGT_DEBUG_REG10_last_bit_end_di_q_MASK | \ + VGT_DEBUG_REG10_selected_data_MASK | \ + VGT_DEBUG_REG10_mask_input_data_MASK | \ + VGT_DEBUG_REG10_gap_q_MASK | \ + VGT_DEBUG_REG10_temp_mini_reset_z_MASK | \ + VGT_DEBUG_REG10_temp_mini_reset_y_MASK | \ + VGT_DEBUG_REG10_temp_mini_reset_x_MASK | \ + VGT_DEBUG_REG10_grp_trigger_MASK) + +#define VGT_DEBUG_REG10(temp_derived_di_prim_type_t0, temp_derived_di_small_index_t0, temp_derived_di_cull_enable_t0, temp_derived_di_pre_fetch_cull_enable_t0, di_state_sel_q, last_decr_of_packet, bin_valid, read_block, grp_bgrp_last_bit_read, last_bit_enable_q, last_bit_end_di_q, selected_data, mask_input_data, gap_q, temp_mini_reset_z, temp_mini_reset_y, temp_mini_reset_x, grp_trigger) \ + ((temp_derived_di_prim_type_t0 << VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT) | \ + (temp_derived_di_small_index_t0 << VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT) | \ + (temp_derived_di_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT) | \ + (temp_derived_di_pre_fetch_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT) | \ + (di_state_sel_q << VGT_DEBUG_REG10_di_state_sel_q_SHIFT) | \ + (last_decr_of_packet << VGT_DEBUG_REG10_last_decr_of_packet_SHIFT) | \ + (bin_valid << VGT_DEBUG_REG10_bin_valid_SHIFT) | \ + (read_block << VGT_DEBUG_REG10_read_block_SHIFT) | \ + (grp_bgrp_last_bit_read << VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT) | \ + (last_bit_enable_q << VGT_DEBUG_REG10_last_bit_enable_q_SHIFT) | \ + (last_bit_end_di_q << VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT) | \ + (selected_data << VGT_DEBUG_REG10_selected_data_SHIFT) | \ + (mask_input_data << VGT_DEBUG_REG10_mask_input_data_SHIFT) | \ + (gap_q << VGT_DEBUG_REG10_gap_q_SHIFT) | \ + (temp_mini_reset_z << VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT) | \ + (temp_mini_reset_y << VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT) | \ + (temp_mini_reset_x << VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT) | \ + (grp_trigger << VGT_DEBUG_REG10_grp_trigger_SHIFT)) + +#define VGT_DEBUG_REG10_GET_temp_derived_di_prim_type_t0(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_derived_di_small_index_t0(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_derived_di_cull_enable_t0(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_derived_di_pre_fetch_cull_enable_t0(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT) +#define VGT_DEBUG_REG10_GET_di_state_sel_q(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_di_state_sel_q_MASK) >> VGT_DEBUG_REG10_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG10_GET_last_decr_of_packet(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_decr_of_packet_MASK) >> VGT_DEBUG_REG10_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG10_GET_bin_valid(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_bin_valid_MASK) >> VGT_DEBUG_REG10_bin_valid_SHIFT) +#define VGT_DEBUG_REG10_GET_read_block(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_read_block_MASK) >> VGT_DEBUG_REG10_read_block_SHIFT) +#define VGT_DEBUG_REG10_GET_grp_bgrp_last_bit_read(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK) >> VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT) +#define VGT_DEBUG_REG10_GET_last_bit_enable_q(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_bit_enable_q_MASK) >> VGT_DEBUG_REG10_last_bit_enable_q_SHIFT) +#define VGT_DEBUG_REG10_GET_last_bit_end_di_q(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_bit_end_di_q_MASK) >> VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT) +#define VGT_DEBUG_REG10_GET_selected_data(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_selected_data_MASK) >> VGT_DEBUG_REG10_selected_data_SHIFT) +#define VGT_DEBUG_REG10_GET_mask_input_data(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_mask_input_data_MASK) >> VGT_DEBUG_REG10_mask_input_data_SHIFT) +#define VGT_DEBUG_REG10_GET_gap_q(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_gap_q_MASK) >> VGT_DEBUG_REG10_gap_q_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_mini_reset_z(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_z_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_mini_reset_y(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_y_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_mini_reset_x(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_x_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT) +#define VGT_DEBUG_REG10_GET_grp_trigger(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_grp_trigger_MASK) >> VGT_DEBUG_REG10_grp_trigger_SHIFT) + +#define VGT_DEBUG_REG10_SET_temp_derived_di_prim_type_t0(vgt_debug_reg10_reg, temp_derived_di_prim_type_t0) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK) | (temp_derived_di_prim_type_t0 << VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_derived_di_small_index_t0(vgt_debug_reg10_reg, temp_derived_di_small_index_t0) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK) | (temp_derived_di_small_index_t0 << VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_derived_di_cull_enable_t0(vgt_debug_reg10_reg, temp_derived_di_cull_enable_t0) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK) | (temp_derived_di_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_derived_di_pre_fetch_cull_enable_t0(vgt_debug_reg10_reg, temp_derived_di_pre_fetch_cull_enable_t0) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK) | (temp_derived_di_pre_fetch_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT) +#define VGT_DEBUG_REG10_SET_di_state_sel_q(vgt_debug_reg10_reg, di_state_sel_q) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG10_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG10_SET_last_decr_of_packet(vgt_debug_reg10_reg, last_decr_of_packet) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG10_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG10_SET_bin_valid(vgt_debug_reg10_reg, bin_valid) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_bin_valid_MASK) | (bin_valid << VGT_DEBUG_REG10_bin_valid_SHIFT) +#define VGT_DEBUG_REG10_SET_read_block(vgt_debug_reg10_reg, read_block) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_read_block_MASK) | (read_block << VGT_DEBUG_REG10_read_block_SHIFT) +#define VGT_DEBUG_REG10_SET_grp_bgrp_last_bit_read(vgt_debug_reg10_reg, grp_bgrp_last_bit_read) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK) | (grp_bgrp_last_bit_read << VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT) +#define VGT_DEBUG_REG10_SET_last_bit_enable_q(vgt_debug_reg10_reg, last_bit_enable_q) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_bit_enable_q_MASK) | (last_bit_enable_q << VGT_DEBUG_REG10_last_bit_enable_q_SHIFT) +#define VGT_DEBUG_REG10_SET_last_bit_end_di_q(vgt_debug_reg10_reg, last_bit_end_di_q) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_bit_end_di_q_MASK) | (last_bit_end_di_q << VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT) +#define VGT_DEBUG_REG10_SET_selected_data(vgt_debug_reg10_reg, selected_data) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_selected_data_MASK) | (selected_data << VGT_DEBUG_REG10_selected_data_SHIFT) +#define VGT_DEBUG_REG10_SET_mask_input_data(vgt_debug_reg10_reg, mask_input_data) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_mask_input_data_MASK) | (mask_input_data << VGT_DEBUG_REG10_mask_input_data_SHIFT) +#define VGT_DEBUG_REG10_SET_gap_q(vgt_debug_reg10_reg, gap_q) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_gap_q_MASK) | (gap_q << VGT_DEBUG_REG10_gap_q_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_mini_reset_z(vgt_debug_reg10_reg, temp_mini_reset_z) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_z_MASK) | (temp_mini_reset_z << VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_mini_reset_y(vgt_debug_reg10_reg, temp_mini_reset_y) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_y_MASK) | (temp_mini_reset_y << VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_mini_reset_x(vgt_debug_reg10_reg, temp_mini_reset_x) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_x_MASK) | (temp_mini_reset_x << VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT) +#define VGT_DEBUG_REG10_SET_grp_trigger(vgt_debug_reg10_reg, grp_trigger) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG10_grp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg10_t { + unsigned int temp_derived_di_prim_type_t0 : VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE; + unsigned int temp_derived_di_small_index_t0 : VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE; + unsigned int temp_derived_di_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE; + unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG10_di_state_sel_q_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG10_last_decr_of_packet_SIZE; + unsigned int bin_valid : VGT_DEBUG_REG10_bin_valid_SIZE; + unsigned int read_block : VGT_DEBUG_REG10_read_block_SIZE; + unsigned int grp_bgrp_last_bit_read : VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE; + unsigned int last_bit_enable_q : VGT_DEBUG_REG10_last_bit_enable_q_SIZE; + unsigned int last_bit_end_di_q : VGT_DEBUG_REG10_last_bit_end_di_q_SIZE; + unsigned int selected_data : VGT_DEBUG_REG10_selected_data_SIZE; + unsigned int mask_input_data : VGT_DEBUG_REG10_mask_input_data_SIZE; + unsigned int gap_q : VGT_DEBUG_REG10_gap_q_SIZE; + unsigned int temp_mini_reset_z : VGT_DEBUG_REG10_temp_mini_reset_z_SIZE; + unsigned int temp_mini_reset_y : VGT_DEBUG_REG10_temp_mini_reset_y_SIZE; + unsigned int temp_mini_reset_x : VGT_DEBUG_REG10_temp_mini_reset_x_SIZE; + unsigned int grp_trigger : VGT_DEBUG_REG10_grp_trigger_SIZE; + } vgt_debug_reg10_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg10_t { + unsigned int grp_trigger : VGT_DEBUG_REG10_grp_trigger_SIZE; + unsigned int temp_mini_reset_x : VGT_DEBUG_REG10_temp_mini_reset_x_SIZE; + unsigned int temp_mini_reset_y : VGT_DEBUG_REG10_temp_mini_reset_y_SIZE; + unsigned int temp_mini_reset_z : VGT_DEBUG_REG10_temp_mini_reset_z_SIZE; + unsigned int gap_q : VGT_DEBUG_REG10_gap_q_SIZE; + unsigned int mask_input_data : VGT_DEBUG_REG10_mask_input_data_SIZE; + unsigned int selected_data : VGT_DEBUG_REG10_selected_data_SIZE; + unsigned int last_bit_end_di_q : VGT_DEBUG_REG10_last_bit_end_di_q_SIZE; + unsigned int last_bit_enable_q : VGT_DEBUG_REG10_last_bit_enable_q_SIZE; + unsigned int grp_bgrp_last_bit_read : VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE; + unsigned int read_block : VGT_DEBUG_REG10_read_block_SIZE; + unsigned int bin_valid : VGT_DEBUG_REG10_bin_valid_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG10_last_decr_of_packet_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG10_di_state_sel_q_SIZE; + unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE; + unsigned int temp_derived_di_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE; + unsigned int temp_derived_di_small_index_t0 : VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE; + unsigned int temp_derived_di_prim_type_t0 : VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE; + } vgt_debug_reg10_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg10_t f; +} vgt_debug_reg10_u; + + +/* + * VGT_DEBUG_REG12 struct + */ + +#define VGT_DEBUG_REG12_shifter_byte_count_q_SIZE 5 +#define VGT_DEBUG_REG12_right_word_indx_q_SIZE 5 +#define VGT_DEBUG_REG12_input_data_valid_SIZE 1 +#define VGT_DEBUG_REG12_input_data_xfer_SIZE 1 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE 1 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE 1 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE 1 +#define VGT_DEBUG_REG12_space_avail_from_shift_SIZE 1 +#define VGT_DEBUG_REG12_shifter_first_load_SIZE 1 +#define VGT_DEBUG_REG12_di_state_sel_q_SIZE 1 +#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE 1 +#define VGT_DEBUG_REG12_di_first_group_flag_q_SIZE 1 +#define VGT_DEBUG_REG12_di_event_flag_q_SIZE 1 +#define VGT_DEBUG_REG12_read_draw_initiator_SIZE 1 +#define VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE 1 +#define VGT_DEBUG_REG12_last_shift_of_packet_SIZE 1 +#define VGT_DEBUG_REG12_last_decr_of_packet_SIZE 1 +#define VGT_DEBUG_REG12_extract_vector_SIZE 1 +#define VGT_DEBUG_REG12_shift_vect_rtr_SIZE 1 +#define VGT_DEBUG_REG12_destination_rtr_SIZE 1 +#define VGT_DEBUG_REG12_bgrp_trigger_SIZE 1 + +#define VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT 0 +#define VGT_DEBUG_REG12_right_word_indx_q_SHIFT 5 +#define VGT_DEBUG_REG12_input_data_valid_SHIFT 10 +#define VGT_DEBUG_REG12_input_data_xfer_SHIFT 11 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT 12 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT 13 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT 14 +#define VGT_DEBUG_REG12_space_avail_from_shift_SHIFT 15 +#define VGT_DEBUG_REG12_shifter_first_load_SHIFT 16 +#define VGT_DEBUG_REG12_di_state_sel_q_SHIFT 17 +#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT 18 +#define VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT 19 +#define VGT_DEBUG_REG12_di_event_flag_q_SHIFT 20 +#define VGT_DEBUG_REG12_read_draw_initiator_SHIFT 21 +#define VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT 22 +#define VGT_DEBUG_REG12_last_shift_of_packet_SHIFT 23 +#define VGT_DEBUG_REG12_last_decr_of_packet_SHIFT 24 +#define VGT_DEBUG_REG12_extract_vector_SHIFT 25 +#define VGT_DEBUG_REG12_shift_vect_rtr_SHIFT 26 +#define VGT_DEBUG_REG12_destination_rtr_SHIFT 27 +#define VGT_DEBUG_REG12_bgrp_trigger_SHIFT 28 + +#define VGT_DEBUG_REG12_shifter_byte_count_q_MASK 0x0000001f +#define VGT_DEBUG_REG12_right_word_indx_q_MASK 0x000003e0 +#define VGT_DEBUG_REG12_input_data_valid_MASK 0x00000400 +#define VGT_DEBUG_REG12_input_data_xfer_MASK 0x00000800 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK 0x00001000 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK 0x00002000 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK 0x00004000 +#define VGT_DEBUG_REG12_space_avail_from_shift_MASK 0x00008000 +#define VGT_DEBUG_REG12_shifter_first_load_MASK 0x00010000 +#define VGT_DEBUG_REG12_di_state_sel_q_MASK 0x00020000 +#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK 0x00040000 +#define VGT_DEBUG_REG12_di_first_group_flag_q_MASK 0x00080000 +#define VGT_DEBUG_REG12_di_event_flag_q_MASK 0x00100000 +#define VGT_DEBUG_REG12_read_draw_initiator_MASK 0x00200000 +#define VGT_DEBUG_REG12_loading_di_requires_shifter_MASK 0x00400000 +#define VGT_DEBUG_REG12_last_shift_of_packet_MASK 0x00800000 +#define VGT_DEBUG_REG12_last_decr_of_packet_MASK 0x01000000 +#define VGT_DEBUG_REG12_extract_vector_MASK 0x02000000 +#define VGT_DEBUG_REG12_shift_vect_rtr_MASK 0x04000000 +#define VGT_DEBUG_REG12_destination_rtr_MASK 0x08000000 +#define VGT_DEBUG_REG12_bgrp_trigger_MASK 0x10000000 + +#define VGT_DEBUG_REG12_MASK \ + (VGT_DEBUG_REG12_shifter_byte_count_q_MASK | \ + VGT_DEBUG_REG12_right_word_indx_q_MASK | \ + VGT_DEBUG_REG12_input_data_valid_MASK | \ + VGT_DEBUG_REG12_input_data_xfer_MASK | \ + VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK | \ + VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK | \ + VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK | \ + VGT_DEBUG_REG12_space_avail_from_shift_MASK | \ + VGT_DEBUG_REG12_shifter_first_load_MASK | \ + VGT_DEBUG_REG12_di_state_sel_q_MASK | \ + VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK | \ + VGT_DEBUG_REG12_di_first_group_flag_q_MASK | \ + VGT_DEBUG_REG12_di_event_flag_q_MASK | \ + VGT_DEBUG_REG12_read_draw_initiator_MASK | \ + VGT_DEBUG_REG12_loading_di_requires_shifter_MASK | \ + VGT_DEBUG_REG12_last_shift_of_packet_MASK | \ + VGT_DEBUG_REG12_last_decr_of_packet_MASK | \ + VGT_DEBUG_REG12_extract_vector_MASK | \ + VGT_DEBUG_REG12_shift_vect_rtr_MASK | \ + VGT_DEBUG_REG12_destination_rtr_MASK | \ + VGT_DEBUG_REG12_bgrp_trigger_MASK) + +#define VGT_DEBUG_REG12(shifter_byte_count_q, right_word_indx_q, input_data_valid, input_data_xfer, next_shift_is_vect_1_q, next_shift_is_vect_1_d, next_shift_is_vect_1_pre_d, space_avail_from_shift, shifter_first_load, di_state_sel_q, shifter_waiting_for_first_load_q, di_first_group_flag_q, di_event_flag_q, read_draw_initiator, loading_di_requires_shifter, last_shift_of_packet, last_decr_of_packet, extract_vector, shift_vect_rtr, destination_rtr, bgrp_trigger) \ + ((shifter_byte_count_q << VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT) | \ + (right_word_indx_q << VGT_DEBUG_REG12_right_word_indx_q_SHIFT) | \ + (input_data_valid << VGT_DEBUG_REG12_input_data_valid_SHIFT) | \ + (input_data_xfer << VGT_DEBUG_REG12_input_data_xfer_SHIFT) | \ + (next_shift_is_vect_1_q << VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT) | \ + (next_shift_is_vect_1_d << VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT) | \ + (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT) | \ + (space_avail_from_shift << VGT_DEBUG_REG12_space_avail_from_shift_SHIFT) | \ + (shifter_first_load << VGT_DEBUG_REG12_shifter_first_load_SHIFT) | \ + (di_state_sel_q << VGT_DEBUG_REG12_di_state_sel_q_SHIFT) | \ + (shifter_waiting_for_first_load_q << VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT) | \ + (di_first_group_flag_q << VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT) | \ + (di_event_flag_q << VGT_DEBUG_REG12_di_event_flag_q_SHIFT) | \ + (read_draw_initiator << VGT_DEBUG_REG12_read_draw_initiator_SHIFT) | \ + (loading_di_requires_shifter << VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT) | \ + (last_shift_of_packet << VGT_DEBUG_REG12_last_shift_of_packet_SHIFT) | \ + (last_decr_of_packet << VGT_DEBUG_REG12_last_decr_of_packet_SHIFT) | \ + (extract_vector << VGT_DEBUG_REG12_extract_vector_SHIFT) | \ + (shift_vect_rtr << VGT_DEBUG_REG12_shift_vect_rtr_SHIFT) | \ + (destination_rtr << VGT_DEBUG_REG12_destination_rtr_SHIFT) | \ + (bgrp_trigger << VGT_DEBUG_REG12_bgrp_trigger_SHIFT)) + +#define VGT_DEBUG_REG12_GET_shifter_byte_count_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_byte_count_q_MASK) >> VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT) +#define VGT_DEBUG_REG12_GET_right_word_indx_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_right_word_indx_q_MASK) >> VGT_DEBUG_REG12_right_word_indx_q_SHIFT) +#define VGT_DEBUG_REG12_GET_input_data_valid(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_input_data_valid_MASK) >> VGT_DEBUG_REG12_input_data_valid_SHIFT) +#define VGT_DEBUG_REG12_GET_input_data_xfer(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_input_data_xfer_MASK) >> VGT_DEBUG_REG12_input_data_xfer_SHIFT) +#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT) +#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_d(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT) +#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_pre_d(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT) +#define VGT_DEBUG_REG12_GET_space_avail_from_shift(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_space_avail_from_shift_MASK) >> VGT_DEBUG_REG12_space_avail_from_shift_SHIFT) +#define VGT_DEBUG_REG12_GET_shifter_first_load(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_first_load_MASK) >> VGT_DEBUG_REG12_shifter_first_load_SHIFT) +#define VGT_DEBUG_REG12_GET_di_state_sel_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_state_sel_q_MASK) >> VGT_DEBUG_REG12_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG12_GET_shifter_waiting_for_first_load_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK) >> VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT) +#define VGT_DEBUG_REG12_GET_di_first_group_flag_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_first_group_flag_q_MASK) >> VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT) +#define VGT_DEBUG_REG12_GET_di_event_flag_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_event_flag_q_MASK) >> VGT_DEBUG_REG12_di_event_flag_q_SHIFT) +#define VGT_DEBUG_REG12_GET_read_draw_initiator(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_read_draw_initiator_MASK) >> VGT_DEBUG_REG12_read_draw_initiator_SHIFT) +#define VGT_DEBUG_REG12_GET_loading_di_requires_shifter(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_loading_di_requires_shifter_MASK) >> VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT) +#define VGT_DEBUG_REG12_GET_last_shift_of_packet(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_last_shift_of_packet_MASK) >> VGT_DEBUG_REG12_last_shift_of_packet_SHIFT) +#define VGT_DEBUG_REG12_GET_last_decr_of_packet(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_last_decr_of_packet_MASK) >> VGT_DEBUG_REG12_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG12_GET_extract_vector(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_extract_vector_MASK) >> VGT_DEBUG_REG12_extract_vector_SHIFT) +#define VGT_DEBUG_REG12_GET_shift_vect_rtr(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_shift_vect_rtr_MASK) >> VGT_DEBUG_REG12_shift_vect_rtr_SHIFT) +#define VGT_DEBUG_REG12_GET_destination_rtr(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_destination_rtr_MASK) >> VGT_DEBUG_REG12_destination_rtr_SHIFT) +#define VGT_DEBUG_REG12_GET_bgrp_trigger(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_bgrp_trigger_MASK) >> VGT_DEBUG_REG12_bgrp_trigger_SHIFT) + +#define VGT_DEBUG_REG12_SET_shifter_byte_count_q(vgt_debug_reg12_reg, shifter_byte_count_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_byte_count_q_MASK) | (shifter_byte_count_q << VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT) +#define VGT_DEBUG_REG12_SET_right_word_indx_q(vgt_debug_reg12_reg, right_word_indx_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_right_word_indx_q_MASK) | (right_word_indx_q << VGT_DEBUG_REG12_right_word_indx_q_SHIFT) +#define VGT_DEBUG_REG12_SET_input_data_valid(vgt_debug_reg12_reg, input_data_valid) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_input_data_valid_MASK) | (input_data_valid << VGT_DEBUG_REG12_input_data_valid_SHIFT) +#define VGT_DEBUG_REG12_SET_input_data_xfer(vgt_debug_reg12_reg, input_data_xfer) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_input_data_xfer_MASK) | (input_data_xfer << VGT_DEBUG_REG12_input_data_xfer_SHIFT) +#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_q(vgt_debug_reg12_reg, next_shift_is_vect_1_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK) | (next_shift_is_vect_1_q << VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT) +#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_d(vgt_debug_reg12_reg, next_shift_is_vect_1_d) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK) | (next_shift_is_vect_1_d << VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT) +#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_pre_d(vgt_debug_reg12_reg, next_shift_is_vect_1_pre_d) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK) | (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT) +#define VGT_DEBUG_REG12_SET_space_avail_from_shift(vgt_debug_reg12_reg, space_avail_from_shift) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_space_avail_from_shift_MASK) | (space_avail_from_shift << VGT_DEBUG_REG12_space_avail_from_shift_SHIFT) +#define VGT_DEBUG_REG12_SET_shifter_first_load(vgt_debug_reg12_reg, shifter_first_load) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_first_load_MASK) | (shifter_first_load << VGT_DEBUG_REG12_shifter_first_load_SHIFT) +#define VGT_DEBUG_REG12_SET_di_state_sel_q(vgt_debug_reg12_reg, di_state_sel_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG12_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG12_SET_shifter_waiting_for_first_load_q(vgt_debug_reg12_reg, shifter_waiting_for_first_load_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK) | (shifter_waiting_for_first_load_q << VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT) +#define VGT_DEBUG_REG12_SET_di_first_group_flag_q(vgt_debug_reg12_reg, di_first_group_flag_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_first_group_flag_q_MASK) | (di_first_group_flag_q << VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT) +#define VGT_DEBUG_REG12_SET_di_event_flag_q(vgt_debug_reg12_reg, di_event_flag_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_event_flag_q_MASK) | (di_event_flag_q << VGT_DEBUG_REG12_di_event_flag_q_SHIFT) +#define VGT_DEBUG_REG12_SET_read_draw_initiator(vgt_debug_reg12_reg, read_draw_initiator) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_read_draw_initiator_MASK) | (read_draw_initiator << VGT_DEBUG_REG12_read_draw_initiator_SHIFT) +#define VGT_DEBUG_REG12_SET_loading_di_requires_shifter(vgt_debug_reg12_reg, loading_di_requires_shifter) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_loading_di_requires_shifter_MASK) | (loading_di_requires_shifter << VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT) +#define VGT_DEBUG_REG12_SET_last_shift_of_packet(vgt_debug_reg12_reg, last_shift_of_packet) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_last_shift_of_packet_MASK) | (last_shift_of_packet << VGT_DEBUG_REG12_last_shift_of_packet_SHIFT) +#define VGT_DEBUG_REG12_SET_last_decr_of_packet(vgt_debug_reg12_reg, last_decr_of_packet) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG12_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG12_SET_extract_vector(vgt_debug_reg12_reg, extract_vector) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_extract_vector_MASK) | (extract_vector << VGT_DEBUG_REG12_extract_vector_SHIFT) +#define VGT_DEBUG_REG12_SET_shift_vect_rtr(vgt_debug_reg12_reg, shift_vect_rtr) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shift_vect_rtr_MASK) | (shift_vect_rtr << VGT_DEBUG_REG12_shift_vect_rtr_SHIFT) +#define VGT_DEBUG_REG12_SET_destination_rtr(vgt_debug_reg12_reg, destination_rtr) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_destination_rtr_MASK) | (destination_rtr << VGT_DEBUG_REG12_destination_rtr_SHIFT) +#define VGT_DEBUG_REG12_SET_bgrp_trigger(vgt_debug_reg12_reg, bgrp_trigger) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG12_bgrp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg12_t { + unsigned int shifter_byte_count_q : VGT_DEBUG_REG12_shifter_byte_count_q_SIZE; + unsigned int right_word_indx_q : VGT_DEBUG_REG12_right_word_indx_q_SIZE; + unsigned int input_data_valid : VGT_DEBUG_REG12_input_data_valid_SIZE; + unsigned int input_data_xfer : VGT_DEBUG_REG12_input_data_xfer_SIZE; + unsigned int next_shift_is_vect_1_q : VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE; + unsigned int next_shift_is_vect_1_d : VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE; + unsigned int next_shift_is_vect_1_pre_d : VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE; + unsigned int space_avail_from_shift : VGT_DEBUG_REG12_space_avail_from_shift_SIZE; + unsigned int shifter_first_load : VGT_DEBUG_REG12_shifter_first_load_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG12_di_state_sel_q_SIZE; + unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE; + unsigned int di_first_group_flag_q : VGT_DEBUG_REG12_di_first_group_flag_q_SIZE; + unsigned int di_event_flag_q : VGT_DEBUG_REG12_di_event_flag_q_SIZE; + unsigned int read_draw_initiator : VGT_DEBUG_REG12_read_draw_initiator_SIZE; + unsigned int loading_di_requires_shifter : VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE; + unsigned int last_shift_of_packet : VGT_DEBUG_REG12_last_shift_of_packet_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG12_last_decr_of_packet_SIZE; + unsigned int extract_vector : VGT_DEBUG_REG12_extract_vector_SIZE; + unsigned int shift_vect_rtr : VGT_DEBUG_REG12_shift_vect_rtr_SIZE; + unsigned int destination_rtr : VGT_DEBUG_REG12_destination_rtr_SIZE; + unsigned int bgrp_trigger : VGT_DEBUG_REG12_bgrp_trigger_SIZE; + unsigned int : 3; + } vgt_debug_reg12_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg12_t { + unsigned int : 3; + unsigned int bgrp_trigger : VGT_DEBUG_REG12_bgrp_trigger_SIZE; + unsigned int destination_rtr : VGT_DEBUG_REG12_destination_rtr_SIZE; + unsigned int shift_vect_rtr : VGT_DEBUG_REG12_shift_vect_rtr_SIZE; + unsigned int extract_vector : VGT_DEBUG_REG12_extract_vector_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG12_last_decr_of_packet_SIZE; + unsigned int last_shift_of_packet : VGT_DEBUG_REG12_last_shift_of_packet_SIZE; + unsigned int loading_di_requires_shifter : VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE; + unsigned int read_draw_initiator : VGT_DEBUG_REG12_read_draw_initiator_SIZE; + unsigned int di_event_flag_q : VGT_DEBUG_REG12_di_event_flag_q_SIZE; + unsigned int di_first_group_flag_q : VGT_DEBUG_REG12_di_first_group_flag_q_SIZE; + unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG12_di_state_sel_q_SIZE; + unsigned int shifter_first_load : VGT_DEBUG_REG12_shifter_first_load_SIZE; + unsigned int space_avail_from_shift : VGT_DEBUG_REG12_space_avail_from_shift_SIZE; + unsigned int next_shift_is_vect_1_pre_d : VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE; + unsigned int next_shift_is_vect_1_d : VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE; + unsigned int next_shift_is_vect_1_q : VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE; + unsigned int input_data_xfer : VGT_DEBUG_REG12_input_data_xfer_SIZE; + unsigned int input_data_valid : VGT_DEBUG_REG12_input_data_valid_SIZE; + unsigned int right_word_indx_q : VGT_DEBUG_REG12_right_word_indx_q_SIZE; + unsigned int shifter_byte_count_q : VGT_DEBUG_REG12_shifter_byte_count_q_SIZE; + } vgt_debug_reg12_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg12_t f; +} vgt_debug_reg12_u; + + +/* + * VGT_DEBUG_REG13 struct + */ + +#define VGT_DEBUG_REG13_di_index_counter_q_SIZE 16 +#define VGT_DEBUG_REG13_shift_amount_no_extract_SIZE 4 +#define VGT_DEBUG_REG13_shift_amount_extract_SIZE 4 +#define VGT_DEBUG_REG13_di_prim_type_q_SIZE 6 +#define VGT_DEBUG_REG13_current_source_sel_SIZE 2 + +#define VGT_DEBUG_REG13_di_index_counter_q_SHIFT 0 +#define VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT 16 +#define VGT_DEBUG_REG13_shift_amount_extract_SHIFT 20 +#define VGT_DEBUG_REG13_di_prim_type_q_SHIFT 24 +#define VGT_DEBUG_REG13_current_source_sel_SHIFT 30 + +#define VGT_DEBUG_REG13_di_index_counter_q_MASK 0x0000ffff +#define VGT_DEBUG_REG13_shift_amount_no_extract_MASK 0x000f0000 +#define VGT_DEBUG_REG13_shift_amount_extract_MASK 0x00f00000 +#define VGT_DEBUG_REG13_di_prim_type_q_MASK 0x3f000000 +#define VGT_DEBUG_REG13_current_source_sel_MASK 0xc0000000 + +#define VGT_DEBUG_REG13_MASK \ + (VGT_DEBUG_REG13_di_index_counter_q_MASK | \ + VGT_DEBUG_REG13_shift_amount_no_extract_MASK | \ + VGT_DEBUG_REG13_shift_amount_extract_MASK | \ + VGT_DEBUG_REG13_di_prim_type_q_MASK | \ + VGT_DEBUG_REG13_current_source_sel_MASK) + +#define VGT_DEBUG_REG13(di_index_counter_q, shift_amount_no_extract, shift_amount_extract, di_prim_type_q, current_source_sel) \ + ((di_index_counter_q << VGT_DEBUG_REG13_di_index_counter_q_SHIFT) | \ + (shift_amount_no_extract << VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT) | \ + (shift_amount_extract << VGT_DEBUG_REG13_shift_amount_extract_SHIFT) | \ + (di_prim_type_q << VGT_DEBUG_REG13_di_prim_type_q_SHIFT) | \ + (current_source_sel << VGT_DEBUG_REG13_current_source_sel_SHIFT)) + +#define VGT_DEBUG_REG13_GET_di_index_counter_q(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_di_index_counter_q_MASK) >> VGT_DEBUG_REG13_di_index_counter_q_SHIFT) +#define VGT_DEBUG_REG13_GET_shift_amount_no_extract(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_shift_amount_no_extract_MASK) >> VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT) +#define VGT_DEBUG_REG13_GET_shift_amount_extract(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_shift_amount_extract_MASK) >> VGT_DEBUG_REG13_shift_amount_extract_SHIFT) +#define VGT_DEBUG_REG13_GET_di_prim_type_q(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_di_prim_type_q_MASK) >> VGT_DEBUG_REG13_di_prim_type_q_SHIFT) +#define VGT_DEBUG_REG13_GET_current_source_sel(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_current_source_sel_MASK) >> VGT_DEBUG_REG13_current_source_sel_SHIFT) + +#define VGT_DEBUG_REG13_SET_di_index_counter_q(vgt_debug_reg13_reg, di_index_counter_q) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_di_index_counter_q_MASK) | (di_index_counter_q << VGT_DEBUG_REG13_di_index_counter_q_SHIFT) +#define VGT_DEBUG_REG13_SET_shift_amount_no_extract(vgt_debug_reg13_reg, shift_amount_no_extract) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_shift_amount_no_extract_MASK) | (shift_amount_no_extract << VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT) +#define VGT_DEBUG_REG13_SET_shift_amount_extract(vgt_debug_reg13_reg, shift_amount_extract) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_shift_amount_extract_MASK) | (shift_amount_extract << VGT_DEBUG_REG13_shift_amount_extract_SHIFT) +#define VGT_DEBUG_REG13_SET_di_prim_type_q(vgt_debug_reg13_reg, di_prim_type_q) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_di_prim_type_q_MASK) | (di_prim_type_q << VGT_DEBUG_REG13_di_prim_type_q_SHIFT) +#define VGT_DEBUG_REG13_SET_current_source_sel(vgt_debug_reg13_reg, current_source_sel) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG13_current_source_sel_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg13_t { + unsigned int di_index_counter_q : VGT_DEBUG_REG13_di_index_counter_q_SIZE; + unsigned int shift_amount_no_extract : VGT_DEBUG_REG13_shift_amount_no_extract_SIZE; + unsigned int shift_amount_extract : VGT_DEBUG_REG13_shift_amount_extract_SIZE; + unsigned int di_prim_type_q : VGT_DEBUG_REG13_di_prim_type_q_SIZE; + unsigned int current_source_sel : VGT_DEBUG_REG13_current_source_sel_SIZE; + } vgt_debug_reg13_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg13_t { + unsigned int current_source_sel : VGT_DEBUG_REG13_current_source_sel_SIZE; + unsigned int di_prim_type_q : VGT_DEBUG_REG13_di_prim_type_q_SIZE; + unsigned int shift_amount_extract : VGT_DEBUG_REG13_shift_amount_extract_SIZE; + unsigned int shift_amount_no_extract : VGT_DEBUG_REG13_shift_amount_no_extract_SIZE; + unsigned int di_index_counter_q : VGT_DEBUG_REG13_di_index_counter_q_SIZE; + } vgt_debug_reg13_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg13_t f; +} vgt_debug_reg13_u; + + +/* + * VGT_DEBUG_REG14 struct + */ + +#define VGT_DEBUG_REG14_current_source_sel_SIZE 2 +#define VGT_DEBUG_REG14_left_word_indx_q_SIZE 5 +#define VGT_DEBUG_REG14_input_data_cnt_SIZE 5 +#define VGT_DEBUG_REG14_input_data_lsw_SIZE 5 +#define VGT_DEBUG_REG14_input_data_msw_SIZE 5 +#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE 5 +#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE 5 + +#define VGT_DEBUG_REG14_current_source_sel_SHIFT 0 +#define VGT_DEBUG_REG14_left_word_indx_q_SHIFT 2 +#define VGT_DEBUG_REG14_input_data_cnt_SHIFT 7 +#define VGT_DEBUG_REG14_input_data_lsw_SHIFT 12 +#define VGT_DEBUG_REG14_input_data_msw_SHIFT 17 +#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT 22 +#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT 27 + +#define VGT_DEBUG_REG14_current_source_sel_MASK 0x00000003 +#define VGT_DEBUG_REG14_left_word_indx_q_MASK 0x0000007c +#define VGT_DEBUG_REG14_input_data_cnt_MASK 0x00000f80 +#define VGT_DEBUG_REG14_input_data_lsw_MASK 0x0001f000 +#define VGT_DEBUG_REG14_input_data_msw_MASK 0x003e0000 +#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK 0x07c00000 +#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK 0xf8000000 + +#define VGT_DEBUG_REG14_MASK \ + (VGT_DEBUG_REG14_current_source_sel_MASK | \ + VGT_DEBUG_REG14_left_word_indx_q_MASK | \ + VGT_DEBUG_REG14_input_data_cnt_MASK | \ + VGT_DEBUG_REG14_input_data_lsw_MASK | \ + VGT_DEBUG_REG14_input_data_msw_MASK | \ + VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK | \ + VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) + +#define VGT_DEBUG_REG14(current_source_sel, left_word_indx_q, input_data_cnt, input_data_lsw, input_data_msw, next_small_stride_shift_limit_q, current_small_stride_shift_limit_q) \ + ((current_source_sel << VGT_DEBUG_REG14_current_source_sel_SHIFT) | \ + (left_word_indx_q << VGT_DEBUG_REG14_left_word_indx_q_SHIFT) | \ + (input_data_cnt << VGT_DEBUG_REG14_input_data_cnt_SHIFT) | \ + (input_data_lsw << VGT_DEBUG_REG14_input_data_lsw_SHIFT) | \ + (input_data_msw << VGT_DEBUG_REG14_input_data_msw_SHIFT) | \ + (next_small_stride_shift_limit_q << VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT) | \ + (current_small_stride_shift_limit_q << VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT)) + +#define VGT_DEBUG_REG14_GET_current_source_sel(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_current_source_sel_MASK) >> VGT_DEBUG_REG14_current_source_sel_SHIFT) +#define VGT_DEBUG_REG14_GET_left_word_indx_q(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_left_word_indx_q_MASK) >> VGT_DEBUG_REG14_left_word_indx_q_SHIFT) +#define VGT_DEBUG_REG14_GET_input_data_cnt(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_cnt_MASK) >> VGT_DEBUG_REG14_input_data_cnt_SHIFT) +#define VGT_DEBUG_REG14_GET_input_data_lsw(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_lsw_MASK) >> VGT_DEBUG_REG14_input_data_lsw_SHIFT) +#define VGT_DEBUG_REG14_GET_input_data_msw(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_msw_MASK) >> VGT_DEBUG_REG14_input_data_msw_SHIFT) +#define VGT_DEBUG_REG14_GET_next_small_stride_shift_limit_q(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT) +#define VGT_DEBUG_REG14_GET_current_small_stride_shift_limit_q(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT) + +#define VGT_DEBUG_REG14_SET_current_source_sel(vgt_debug_reg14_reg, current_source_sel) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG14_current_source_sel_SHIFT) +#define VGT_DEBUG_REG14_SET_left_word_indx_q(vgt_debug_reg14_reg, left_word_indx_q) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_left_word_indx_q_MASK) | (left_word_indx_q << VGT_DEBUG_REG14_left_word_indx_q_SHIFT) +#define VGT_DEBUG_REG14_SET_input_data_cnt(vgt_debug_reg14_reg, input_data_cnt) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_cnt_MASK) | (input_data_cnt << VGT_DEBUG_REG14_input_data_cnt_SHIFT) +#define VGT_DEBUG_REG14_SET_input_data_lsw(vgt_debug_reg14_reg, input_data_lsw) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_lsw_MASK) | (input_data_lsw << VGT_DEBUG_REG14_input_data_lsw_SHIFT) +#define VGT_DEBUG_REG14_SET_input_data_msw(vgt_debug_reg14_reg, input_data_msw) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_msw_MASK) | (input_data_msw << VGT_DEBUG_REG14_input_data_msw_SHIFT) +#define VGT_DEBUG_REG14_SET_next_small_stride_shift_limit_q(vgt_debug_reg14_reg, next_small_stride_shift_limit_q) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK) | (next_small_stride_shift_limit_q << VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT) +#define VGT_DEBUG_REG14_SET_current_small_stride_shift_limit_q(vgt_debug_reg14_reg, current_small_stride_shift_limit_q) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) | (current_small_stride_shift_limit_q << VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg14_t { + unsigned int current_source_sel : VGT_DEBUG_REG14_current_source_sel_SIZE; + unsigned int left_word_indx_q : VGT_DEBUG_REG14_left_word_indx_q_SIZE; + unsigned int input_data_cnt : VGT_DEBUG_REG14_input_data_cnt_SIZE; + unsigned int input_data_lsw : VGT_DEBUG_REG14_input_data_lsw_SIZE; + unsigned int input_data_msw : VGT_DEBUG_REG14_input_data_msw_SIZE; + unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE; + unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE; + } vgt_debug_reg14_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg14_t { + unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE; + unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE; + unsigned int input_data_msw : VGT_DEBUG_REG14_input_data_msw_SIZE; + unsigned int input_data_lsw : VGT_DEBUG_REG14_input_data_lsw_SIZE; + unsigned int input_data_cnt : VGT_DEBUG_REG14_input_data_cnt_SIZE; + unsigned int left_word_indx_q : VGT_DEBUG_REG14_left_word_indx_q_SIZE; + unsigned int current_source_sel : VGT_DEBUG_REG14_current_source_sel_SIZE; + } vgt_debug_reg14_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg14_t f; +} vgt_debug_reg14_u; + + +/* + * VGT_DEBUG_REG15 struct + */ + +#define VGT_DEBUG_REG15_next_stride_q_SIZE 5 +#define VGT_DEBUG_REG15_next_stride_d_SIZE 5 +#define VGT_DEBUG_REG15_current_shift_q_SIZE 5 +#define VGT_DEBUG_REG15_current_shift_d_SIZE 5 +#define VGT_DEBUG_REG15_current_stride_q_SIZE 5 +#define VGT_DEBUG_REG15_current_stride_d_SIZE 5 +#define VGT_DEBUG_REG15_bgrp_trigger_SIZE 1 + +#define VGT_DEBUG_REG15_next_stride_q_SHIFT 0 +#define VGT_DEBUG_REG15_next_stride_d_SHIFT 5 +#define VGT_DEBUG_REG15_current_shift_q_SHIFT 10 +#define VGT_DEBUG_REG15_current_shift_d_SHIFT 15 +#define VGT_DEBUG_REG15_current_stride_q_SHIFT 20 +#define VGT_DEBUG_REG15_current_stride_d_SHIFT 25 +#define VGT_DEBUG_REG15_bgrp_trigger_SHIFT 30 + +#define VGT_DEBUG_REG15_next_stride_q_MASK 0x0000001f +#define VGT_DEBUG_REG15_next_stride_d_MASK 0x000003e0 +#define VGT_DEBUG_REG15_current_shift_q_MASK 0x00007c00 +#define VGT_DEBUG_REG15_current_shift_d_MASK 0x000f8000 +#define VGT_DEBUG_REG15_current_stride_q_MASK 0x01f00000 +#define VGT_DEBUG_REG15_current_stride_d_MASK 0x3e000000 +#define VGT_DEBUG_REG15_bgrp_trigger_MASK 0x40000000 + +#define VGT_DEBUG_REG15_MASK \ + (VGT_DEBUG_REG15_next_stride_q_MASK | \ + VGT_DEBUG_REG15_next_stride_d_MASK | \ + VGT_DEBUG_REG15_current_shift_q_MASK | \ + VGT_DEBUG_REG15_current_shift_d_MASK | \ + VGT_DEBUG_REG15_current_stride_q_MASK | \ + VGT_DEBUG_REG15_current_stride_d_MASK | \ + VGT_DEBUG_REG15_bgrp_trigger_MASK) + +#define VGT_DEBUG_REG15(next_stride_q, next_stride_d, current_shift_q, current_shift_d, current_stride_q, current_stride_d, bgrp_trigger) \ + ((next_stride_q << VGT_DEBUG_REG15_next_stride_q_SHIFT) | \ + (next_stride_d << VGT_DEBUG_REG15_next_stride_d_SHIFT) | \ + (current_shift_q << VGT_DEBUG_REG15_current_shift_q_SHIFT) | \ + (current_shift_d << VGT_DEBUG_REG15_current_shift_d_SHIFT) | \ + (current_stride_q << VGT_DEBUG_REG15_current_stride_q_SHIFT) | \ + (current_stride_d << VGT_DEBUG_REG15_current_stride_d_SHIFT) | \ + (bgrp_trigger << VGT_DEBUG_REG15_bgrp_trigger_SHIFT)) + +#define VGT_DEBUG_REG15_GET_next_stride_q(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_next_stride_q_MASK) >> VGT_DEBUG_REG15_next_stride_q_SHIFT) +#define VGT_DEBUG_REG15_GET_next_stride_d(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_next_stride_d_MASK) >> VGT_DEBUG_REG15_next_stride_d_SHIFT) +#define VGT_DEBUG_REG15_GET_current_shift_q(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_shift_q_MASK) >> VGT_DEBUG_REG15_current_shift_q_SHIFT) +#define VGT_DEBUG_REG15_GET_current_shift_d(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_shift_d_MASK) >> VGT_DEBUG_REG15_current_shift_d_SHIFT) +#define VGT_DEBUG_REG15_GET_current_stride_q(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_stride_q_MASK) >> VGT_DEBUG_REG15_current_stride_q_SHIFT) +#define VGT_DEBUG_REG15_GET_current_stride_d(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_stride_d_MASK) >> VGT_DEBUG_REG15_current_stride_d_SHIFT) +#define VGT_DEBUG_REG15_GET_bgrp_trigger(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_bgrp_trigger_MASK) >> VGT_DEBUG_REG15_bgrp_trigger_SHIFT) + +#define VGT_DEBUG_REG15_SET_next_stride_q(vgt_debug_reg15_reg, next_stride_q) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_next_stride_q_MASK) | (next_stride_q << VGT_DEBUG_REG15_next_stride_q_SHIFT) +#define VGT_DEBUG_REG15_SET_next_stride_d(vgt_debug_reg15_reg, next_stride_d) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_next_stride_d_MASK) | (next_stride_d << VGT_DEBUG_REG15_next_stride_d_SHIFT) +#define VGT_DEBUG_REG15_SET_current_shift_q(vgt_debug_reg15_reg, current_shift_q) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_shift_q_MASK) | (current_shift_q << VGT_DEBUG_REG15_current_shift_q_SHIFT) +#define VGT_DEBUG_REG15_SET_current_shift_d(vgt_debug_reg15_reg, current_shift_d) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_shift_d_MASK) | (current_shift_d << VGT_DEBUG_REG15_current_shift_d_SHIFT) +#define VGT_DEBUG_REG15_SET_current_stride_q(vgt_debug_reg15_reg, current_stride_q) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_stride_q_MASK) | (current_stride_q << VGT_DEBUG_REG15_current_stride_q_SHIFT) +#define VGT_DEBUG_REG15_SET_current_stride_d(vgt_debug_reg15_reg, current_stride_d) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_stride_d_MASK) | (current_stride_d << VGT_DEBUG_REG15_current_stride_d_SHIFT) +#define VGT_DEBUG_REG15_SET_bgrp_trigger(vgt_debug_reg15_reg, bgrp_trigger) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG15_bgrp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg15_t { + unsigned int next_stride_q : VGT_DEBUG_REG15_next_stride_q_SIZE; + unsigned int next_stride_d : VGT_DEBUG_REG15_next_stride_d_SIZE; + unsigned int current_shift_q : VGT_DEBUG_REG15_current_shift_q_SIZE; + unsigned int current_shift_d : VGT_DEBUG_REG15_current_shift_d_SIZE; + unsigned int current_stride_q : VGT_DEBUG_REG15_current_stride_q_SIZE; + unsigned int current_stride_d : VGT_DEBUG_REG15_current_stride_d_SIZE; + unsigned int bgrp_trigger : VGT_DEBUG_REG15_bgrp_trigger_SIZE; + unsigned int : 1; + } vgt_debug_reg15_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg15_t { + unsigned int : 1; + unsigned int bgrp_trigger : VGT_DEBUG_REG15_bgrp_trigger_SIZE; + unsigned int current_stride_d : VGT_DEBUG_REG15_current_stride_d_SIZE; + unsigned int current_stride_q : VGT_DEBUG_REG15_current_stride_q_SIZE; + unsigned int current_shift_d : VGT_DEBUG_REG15_current_shift_d_SIZE; + unsigned int current_shift_q : VGT_DEBUG_REG15_current_shift_q_SIZE; + unsigned int next_stride_d : VGT_DEBUG_REG15_next_stride_d_SIZE; + unsigned int next_stride_q : VGT_DEBUG_REG15_next_stride_q_SIZE; + } vgt_debug_reg15_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg15_t f; +} vgt_debug_reg15_u; + + +/* + * VGT_DEBUG_REG16 struct + */ + +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE 1 +#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE 1 +#define VGT_DEBUG_REG16_rst_last_bit_SIZE 1 +#define VGT_DEBUG_REG16_current_state_q_SIZE 1 +#define VGT_DEBUG_REG16_old_state_q_SIZE 1 +#define VGT_DEBUG_REG16_old_state_en_SIZE 1 +#define VGT_DEBUG_REG16_prev_last_bit_q_SIZE 1 +#define VGT_DEBUG_REG16_dbl_last_bit_q_SIZE 1 +#define VGT_DEBUG_REG16_last_bit_block_q_SIZE 1 +#define VGT_DEBUG_REG16_ast_bit_block2_q_SIZE 1 +#define VGT_DEBUG_REG16_load_empty_reg_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE 8 +#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE 2 +#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE 1 +#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_trigger_SIZE 1 + +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT 0 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT 1 +#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT 2 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT 3 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT 4 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT 5 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT 6 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT 7 +#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT 8 +#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT 9 +#define VGT_DEBUG_REG16_rst_last_bit_SHIFT 10 +#define VGT_DEBUG_REG16_current_state_q_SHIFT 11 +#define VGT_DEBUG_REG16_old_state_q_SHIFT 12 +#define VGT_DEBUG_REG16_old_state_en_SHIFT 13 +#define VGT_DEBUG_REG16_prev_last_bit_q_SHIFT 14 +#define VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT 15 +#define VGT_DEBUG_REG16_last_bit_block_q_SHIFT 16 +#define VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT 17 +#define VGT_DEBUG_REG16_load_empty_reg_SHIFT 18 +#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT 19 +#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT 27 +#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT 29 +#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT 30 +#define VGT_DEBUG_REG16_bgrp_trigger_SHIFT 31 + +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK 0x00000001 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK 0x00000002 +#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK 0x00000004 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK 0x00000008 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK 0x00000010 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK 0x00000020 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK 0x00000040 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK 0x00000080 +#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK 0x00000100 +#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK 0x00000200 +#define VGT_DEBUG_REG16_rst_last_bit_MASK 0x00000400 +#define VGT_DEBUG_REG16_current_state_q_MASK 0x00000800 +#define VGT_DEBUG_REG16_old_state_q_MASK 0x00001000 +#define VGT_DEBUG_REG16_old_state_en_MASK 0x00002000 +#define VGT_DEBUG_REG16_prev_last_bit_q_MASK 0x00004000 +#define VGT_DEBUG_REG16_dbl_last_bit_q_MASK 0x00008000 +#define VGT_DEBUG_REG16_last_bit_block_q_MASK 0x00010000 +#define VGT_DEBUG_REG16_ast_bit_block2_q_MASK 0x00020000 +#define VGT_DEBUG_REG16_load_empty_reg_MASK 0x00040000 +#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK 0x07f80000 +#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK 0x18000000 +#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK 0x20000000 +#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK 0x40000000 +#define VGT_DEBUG_REG16_bgrp_trigger_MASK 0x80000000 + +#define VGT_DEBUG_REG16_MASK \ + (VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK | \ + VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK | \ + VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK | \ + VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK | \ + VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK | \ + VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK | \ + VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK | \ + VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK | \ + VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK | \ + VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK | \ + VGT_DEBUG_REG16_rst_last_bit_MASK | \ + VGT_DEBUG_REG16_current_state_q_MASK | \ + VGT_DEBUG_REG16_old_state_q_MASK | \ + VGT_DEBUG_REG16_old_state_en_MASK | \ + VGT_DEBUG_REG16_prev_last_bit_q_MASK | \ + VGT_DEBUG_REG16_dbl_last_bit_q_MASK | \ + VGT_DEBUG_REG16_last_bit_block_q_MASK | \ + VGT_DEBUG_REG16_ast_bit_block2_q_MASK | \ + VGT_DEBUG_REG16_load_empty_reg_MASK | \ + VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK | \ + VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK | \ + VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK | \ + VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK | \ + VGT_DEBUG_REG16_bgrp_trigger_MASK) + +#define VGT_DEBUG_REG16(bgrp_cull_fetch_fifo_full, bgrp_cull_fetch_fifo_empty, dma_bgrp_cull_fetch_read, bgrp_cull_fetch_fifo_we, bgrp_byte_mask_fifo_full, bgrp_byte_mask_fifo_empty, bgrp_byte_mask_fifo_re_q, bgrp_byte_mask_fifo_we, bgrp_dma_mask_kill, bgrp_grp_bin_valid, rst_last_bit, current_state_q, old_state_q, old_state_en, prev_last_bit_q, dbl_last_bit_q, last_bit_block_q, ast_bit_block2_q, load_empty_reg, bgrp_grp_byte_mask_rdata, dma_bgrp_dma_data_fifo_rptr, top_di_pre_fetch_cull_enable, top_di_grp_cull_enable_q, bgrp_trigger) \ + ((bgrp_cull_fetch_fifo_full << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT) | \ + (bgrp_cull_fetch_fifo_empty << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT) | \ + (dma_bgrp_cull_fetch_read << VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT) | \ + (bgrp_cull_fetch_fifo_we << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT) | \ + (bgrp_byte_mask_fifo_full << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT) | \ + (bgrp_byte_mask_fifo_empty << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT) | \ + (bgrp_byte_mask_fifo_re_q << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT) | \ + (bgrp_byte_mask_fifo_we << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT) | \ + (bgrp_dma_mask_kill << VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT) | \ + (bgrp_grp_bin_valid << VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT) | \ + (rst_last_bit << VGT_DEBUG_REG16_rst_last_bit_SHIFT) | \ + (current_state_q << VGT_DEBUG_REG16_current_state_q_SHIFT) | \ + (old_state_q << VGT_DEBUG_REG16_old_state_q_SHIFT) | \ + (old_state_en << VGT_DEBUG_REG16_old_state_en_SHIFT) | \ + (prev_last_bit_q << VGT_DEBUG_REG16_prev_last_bit_q_SHIFT) | \ + (dbl_last_bit_q << VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT) | \ + (last_bit_block_q << VGT_DEBUG_REG16_last_bit_block_q_SHIFT) | \ + (ast_bit_block2_q << VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT) | \ + (load_empty_reg << VGT_DEBUG_REG16_load_empty_reg_SHIFT) | \ + (bgrp_grp_byte_mask_rdata << VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT) | \ + (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT) | \ + (top_di_pre_fetch_cull_enable << VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT) | \ + (top_di_grp_cull_enable_q << VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT) | \ + (bgrp_trigger << VGT_DEBUG_REG16_bgrp_trigger_SHIFT)) + +#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_full(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_empty(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT) +#define VGT_DEBUG_REG16_GET_dma_bgrp_cull_fetch_read(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK) >> VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_we(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_full(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_empty(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_re_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_we(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_dma_mask_kill(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK) >> VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_grp_bin_valid(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK) >> VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT) +#define VGT_DEBUG_REG16_GET_rst_last_bit(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_rst_last_bit_MASK) >> VGT_DEBUG_REG16_rst_last_bit_SHIFT) +#define VGT_DEBUG_REG16_GET_current_state_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_current_state_q_MASK) >> VGT_DEBUG_REG16_current_state_q_SHIFT) +#define VGT_DEBUG_REG16_GET_old_state_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_old_state_q_MASK) >> VGT_DEBUG_REG16_old_state_q_SHIFT) +#define VGT_DEBUG_REG16_GET_old_state_en(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_old_state_en_MASK) >> VGT_DEBUG_REG16_old_state_en_SHIFT) +#define VGT_DEBUG_REG16_GET_prev_last_bit_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_prev_last_bit_q_MASK) >> VGT_DEBUG_REG16_prev_last_bit_q_SHIFT) +#define VGT_DEBUG_REG16_GET_dbl_last_bit_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_dbl_last_bit_q_MASK) >> VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT) +#define VGT_DEBUG_REG16_GET_last_bit_block_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_last_bit_block_q_MASK) >> VGT_DEBUG_REG16_last_bit_block_q_SHIFT) +#define VGT_DEBUG_REG16_GET_ast_bit_block2_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_ast_bit_block2_q_MASK) >> VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT) +#define VGT_DEBUG_REG16_GET_load_empty_reg(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_load_empty_reg_MASK) >> VGT_DEBUG_REG16_load_empty_reg_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_grp_byte_mask_rdata(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK) >> VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT) +#define VGT_DEBUG_REG16_GET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK) >> VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT) +#define VGT_DEBUG_REG16_GET_top_di_pre_fetch_cull_enable(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK) >> VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT) +#define VGT_DEBUG_REG16_GET_top_di_grp_cull_enable_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK) >> VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_trigger(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_trigger_MASK) >> VGT_DEBUG_REG16_bgrp_trigger_SHIFT) + +#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_full(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_full) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK) | (bgrp_cull_fetch_fifo_full << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_empty(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_empty) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK) | (bgrp_cull_fetch_fifo_empty << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT) +#define VGT_DEBUG_REG16_SET_dma_bgrp_cull_fetch_read(vgt_debug_reg16_reg, dma_bgrp_cull_fetch_read) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK) | (dma_bgrp_cull_fetch_read << VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_we(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_we) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK) | (bgrp_cull_fetch_fifo_we << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_full(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_full) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK) | (bgrp_byte_mask_fifo_full << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_empty(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_empty) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK) | (bgrp_byte_mask_fifo_empty << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_re_q(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_re_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK) | (bgrp_byte_mask_fifo_re_q << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_we(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_we) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK) | (bgrp_byte_mask_fifo_we << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_dma_mask_kill(vgt_debug_reg16_reg, bgrp_dma_mask_kill) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK) | (bgrp_dma_mask_kill << VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_grp_bin_valid(vgt_debug_reg16_reg, bgrp_grp_bin_valid) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK) | (bgrp_grp_bin_valid << VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT) +#define VGT_DEBUG_REG16_SET_rst_last_bit(vgt_debug_reg16_reg, rst_last_bit) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_rst_last_bit_MASK) | (rst_last_bit << VGT_DEBUG_REG16_rst_last_bit_SHIFT) +#define VGT_DEBUG_REG16_SET_current_state_q(vgt_debug_reg16_reg, current_state_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_current_state_q_MASK) | (current_state_q << VGT_DEBUG_REG16_current_state_q_SHIFT) +#define VGT_DEBUG_REG16_SET_old_state_q(vgt_debug_reg16_reg, old_state_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_old_state_q_MASK) | (old_state_q << VGT_DEBUG_REG16_old_state_q_SHIFT) +#define VGT_DEBUG_REG16_SET_old_state_en(vgt_debug_reg16_reg, old_state_en) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_old_state_en_MASK) | (old_state_en << VGT_DEBUG_REG16_old_state_en_SHIFT) +#define VGT_DEBUG_REG16_SET_prev_last_bit_q(vgt_debug_reg16_reg, prev_last_bit_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_prev_last_bit_q_MASK) | (prev_last_bit_q << VGT_DEBUG_REG16_prev_last_bit_q_SHIFT) +#define VGT_DEBUG_REG16_SET_dbl_last_bit_q(vgt_debug_reg16_reg, dbl_last_bit_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dbl_last_bit_q_MASK) | (dbl_last_bit_q << VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT) +#define VGT_DEBUG_REG16_SET_last_bit_block_q(vgt_debug_reg16_reg, last_bit_block_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_last_bit_block_q_MASK) | (last_bit_block_q << VGT_DEBUG_REG16_last_bit_block_q_SHIFT) +#define VGT_DEBUG_REG16_SET_ast_bit_block2_q(vgt_debug_reg16_reg, ast_bit_block2_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_ast_bit_block2_q_MASK) | (ast_bit_block2_q << VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT) +#define VGT_DEBUG_REG16_SET_load_empty_reg(vgt_debug_reg16_reg, load_empty_reg) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_load_empty_reg_MASK) | (load_empty_reg << VGT_DEBUG_REG16_load_empty_reg_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_grp_byte_mask_rdata(vgt_debug_reg16_reg, bgrp_grp_byte_mask_rdata) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK) | (bgrp_grp_byte_mask_rdata << VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT) +#define VGT_DEBUG_REG16_SET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg16_reg, dma_bgrp_dma_data_fifo_rptr) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK) | (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT) +#define VGT_DEBUG_REG16_SET_top_di_pre_fetch_cull_enable(vgt_debug_reg16_reg, top_di_pre_fetch_cull_enable) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK) | (top_di_pre_fetch_cull_enable << VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT) +#define VGT_DEBUG_REG16_SET_top_di_grp_cull_enable_q(vgt_debug_reg16_reg, top_di_grp_cull_enable_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK) | (top_di_grp_cull_enable_q << VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_trigger(vgt_debug_reg16_reg, bgrp_trigger) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG16_bgrp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg16_t { + unsigned int bgrp_cull_fetch_fifo_full : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE; + unsigned int bgrp_cull_fetch_fifo_empty : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE; + unsigned int dma_bgrp_cull_fetch_read : VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE; + unsigned int bgrp_cull_fetch_fifo_we : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE; + unsigned int bgrp_byte_mask_fifo_full : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE; + unsigned int bgrp_byte_mask_fifo_empty : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE; + unsigned int bgrp_byte_mask_fifo_re_q : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE; + unsigned int bgrp_byte_mask_fifo_we : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE; + unsigned int bgrp_dma_mask_kill : VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE; + unsigned int bgrp_grp_bin_valid : VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE; + unsigned int rst_last_bit : VGT_DEBUG_REG16_rst_last_bit_SIZE; + unsigned int current_state_q : VGT_DEBUG_REG16_current_state_q_SIZE; + unsigned int old_state_q : VGT_DEBUG_REG16_old_state_q_SIZE; + unsigned int old_state_en : VGT_DEBUG_REG16_old_state_en_SIZE; + unsigned int prev_last_bit_q : VGT_DEBUG_REG16_prev_last_bit_q_SIZE; + unsigned int dbl_last_bit_q : VGT_DEBUG_REG16_dbl_last_bit_q_SIZE; + unsigned int last_bit_block_q : VGT_DEBUG_REG16_last_bit_block_q_SIZE; + unsigned int ast_bit_block2_q : VGT_DEBUG_REG16_ast_bit_block2_q_SIZE; + unsigned int load_empty_reg : VGT_DEBUG_REG16_load_empty_reg_SIZE; + unsigned int bgrp_grp_byte_mask_rdata : VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE; + unsigned int dma_bgrp_dma_data_fifo_rptr : VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE; + unsigned int top_di_pre_fetch_cull_enable : VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE; + unsigned int top_di_grp_cull_enable_q : VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE; + unsigned int bgrp_trigger : VGT_DEBUG_REG16_bgrp_trigger_SIZE; + } vgt_debug_reg16_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg16_t { + unsigned int bgrp_trigger : VGT_DEBUG_REG16_bgrp_trigger_SIZE; + unsigned int top_di_grp_cull_enable_q : VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE; + unsigned int top_di_pre_fetch_cull_enable : VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE; + unsigned int dma_bgrp_dma_data_fifo_rptr : VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE; + unsigned int bgrp_grp_byte_mask_rdata : VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE; + unsigned int load_empty_reg : VGT_DEBUG_REG16_load_empty_reg_SIZE; + unsigned int ast_bit_block2_q : VGT_DEBUG_REG16_ast_bit_block2_q_SIZE; + unsigned int last_bit_block_q : VGT_DEBUG_REG16_last_bit_block_q_SIZE; + unsigned int dbl_last_bit_q : VGT_DEBUG_REG16_dbl_last_bit_q_SIZE; + unsigned int prev_last_bit_q : VGT_DEBUG_REG16_prev_last_bit_q_SIZE; + unsigned int old_state_en : VGT_DEBUG_REG16_old_state_en_SIZE; + unsigned int old_state_q : VGT_DEBUG_REG16_old_state_q_SIZE; + unsigned int current_state_q : VGT_DEBUG_REG16_current_state_q_SIZE; + unsigned int rst_last_bit : VGT_DEBUG_REG16_rst_last_bit_SIZE; + unsigned int bgrp_grp_bin_valid : VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE; + unsigned int bgrp_dma_mask_kill : VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE; + unsigned int bgrp_byte_mask_fifo_we : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE; + unsigned int bgrp_byte_mask_fifo_re_q : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE; + unsigned int bgrp_byte_mask_fifo_empty : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE; + unsigned int bgrp_byte_mask_fifo_full : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE; + unsigned int bgrp_cull_fetch_fifo_we : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE; + unsigned int dma_bgrp_cull_fetch_read : VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE; + unsigned int bgrp_cull_fetch_fifo_empty : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE; + unsigned int bgrp_cull_fetch_fifo_full : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE; + } vgt_debug_reg16_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg16_t f; +} vgt_debug_reg16_u; + + +/* + * VGT_DEBUG_REG17 struct + */ + +#define VGT_DEBUG_REG17_save_read_q_SIZE 1 +#define VGT_DEBUG_REG17_extend_read_q_SIZE 1 +#define VGT_DEBUG_REG17_grp_indx_size_SIZE 2 +#define VGT_DEBUG_REG17_cull_prim_true_SIZE 1 +#define VGT_DEBUG_REG17_reset_bit2_q_SIZE 1 +#define VGT_DEBUG_REG17_reset_bit1_q_SIZE 1 +#define VGT_DEBUG_REG17_first_reg_first_q_SIZE 1 +#define VGT_DEBUG_REG17_check_second_reg_SIZE 1 +#define VGT_DEBUG_REG17_check_first_reg_SIZE 1 +#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE 1 +#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE 1 +#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE 1 +#define VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE 1 +#define VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE 1 +#define VGT_DEBUG_REG17_to_second_reg_q_SIZE 1 +#define VGT_DEBUG_REG17_roll_over_msk_q_SIZE 1 +#define VGT_DEBUG_REG17_max_msk_ptr_q_SIZE 7 +#define VGT_DEBUG_REG17_min_msk_ptr_q_SIZE 7 +#define VGT_DEBUG_REG17_bgrp_trigger_SIZE 1 + +#define VGT_DEBUG_REG17_save_read_q_SHIFT 0 +#define VGT_DEBUG_REG17_extend_read_q_SHIFT 1 +#define VGT_DEBUG_REG17_grp_indx_size_SHIFT 2 +#define VGT_DEBUG_REG17_cull_prim_true_SHIFT 4 +#define VGT_DEBUG_REG17_reset_bit2_q_SHIFT 5 +#define VGT_DEBUG_REG17_reset_bit1_q_SHIFT 6 +#define VGT_DEBUG_REG17_first_reg_first_q_SHIFT 7 +#define VGT_DEBUG_REG17_check_second_reg_SHIFT 8 +#define VGT_DEBUG_REG17_check_first_reg_SHIFT 9 +#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT 10 +#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT 11 +#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT 12 +#define VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT 13 +#define VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT 14 +#define VGT_DEBUG_REG17_to_second_reg_q_SHIFT 15 +#define VGT_DEBUG_REG17_roll_over_msk_q_SHIFT 16 +#define VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT 17 +#define VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT 24 +#define VGT_DEBUG_REG17_bgrp_trigger_SHIFT 31 + +#define VGT_DEBUG_REG17_save_read_q_MASK 0x00000001 +#define VGT_DEBUG_REG17_extend_read_q_MASK 0x00000002 +#define VGT_DEBUG_REG17_grp_indx_size_MASK 0x0000000c +#define VGT_DEBUG_REG17_cull_prim_true_MASK 0x00000010 +#define VGT_DEBUG_REG17_reset_bit2_q_MASK 0x00000020 +#define VGT_DEBUG_REG17_reset_bit1_q_MASK 0x00000040 +#define VGT_DEBUG_REG17_first_reg_first_q_MASK 0x00000080 +#define VGT_DEBUG_REG17_check_second_reg_MASK 0x00000100 +#define VGT_DEBUG_REG17_check_first_reg_MASK 0x00000200 +#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK 0x00000400 +#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK 0x00000800 +#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK 0x00001000 +#define VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK 0x00002000 +#define VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK 0x00004000 +#define VGT_DEBUG_REG17_to_second_reg_q_MASK 0x00008000 +#define VGT_DEBUG_REG17_roll_over_msk_q_MASK 0x00010000 +#define VGT_DEBUG_REG17_max_msk_ptr_q_MASK 0x00fe0000 +#define VGT_DEBUG_REG17_min_msk_ptr_q_MASK 0x7f000000 +#define VGT_DEBUG_REG17_bgrp_trigger_MASK 0x80000000 + +#define VGT_DEBUG_REG17_MASK \ + (VGT_DEBUG_REG17_save_read_q_MASK | \ + VGT_DEBUG_REG17_extend_read_q_MASK | \ + VGT_DEBUG_REG17_grp_indx_size_MASK | \ + VGT_DEBUG_REG17_cull_prim_true_MASK | \ + VGT_DEBUG_REG17_reset_bit2_q_MASK | \ + VGT_DEBUG_REG17_reset_bit1_q_MASK | \ + VGT_DEBUG_REG17_first_reg_first_q_MASK | \ + VGT_DEBUG_REG17_check_second_reg_MASK | \ + VGT_DEBUG_REG17_check_first_reg_MASK | \ + VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK | \ + VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK | \ + VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK | \ + VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK | \ + VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK | \ + VGT_DEBUG_REG17_to_second_reg_q_MASK | \ + VGT_DEBUG_REG17_roll_over_msk_q_MASK | \ + VGT_DEBUG_REG17_max_msk_ptr_q_MASK | \ + VGT_DEBUG_REG17_min_msk_ptr_q_MASK | \ + VGT_DEBUG_REG17_bgrp_trigger_MASK) + +#define VGT_DEBUG_REG17(save_read_q, extend_read_q, grp_indx_size, cull_prim_true, reset_bit2_q, reset_bit1_q, first_reg_first_q, check_second_reg, check_first_reg, bgrp_cull_fetch_fifo_wdata, save_cull_fetch_data2_q, save_cull_fetch_data1_q, save_byte_mask_data2_q, save_byte_mask_data1_q, to_second_reg_q, roll_over_msk_q, max_msk_ptr_q, min_msk_ptr_q, bgrp_trigger) \ + ((save_read_q << VGT_DEBUG_REG17_save_read_q_SHIFT) | \ + (extend_read_q << VGT_DEBUG_REG17_extend_read_q_SHIFT) | \ + (grp_indx_size << VGT_DEBUG_REG17_grp_indx_size_SHIFT) | \ + (cull_prim_true << VGT_DEBUG_REG17_cull_prim_true_SHIFT) | \ + (reset_bit2_q << VGT_DEBUG_REG17_reset_bit2_q_SHIFT) | \ + (reset_bit1_q << VGT_DEBUG_REG17_reset_bit1_q_SHIFT) | \ + (first_reg_first_q << VGT_DEBUG_REG17_first_reg_first_q_SHIFT) | \ + (check_second_reg << VGT_DEBUG_REG17_check_second_reg_SHIFT) | \ + (check_first_reg << VGT_DEBUG_REG17_check_first_reg_SHIFT) | \ + (bgrp_cull_fetch_fifo_wdata << VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT) | \ + (save_cull_fetch_data2_q << VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT) | \ + (save_cull_fetch_data1_q << VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT) | \ + (save_byte_mask_data2_q << VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT) | \ + (save_byte_mask_data1_q << VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT) | \ + (to_second_reg_q << VGT_DEBUG_REG17_to_second_reg_q_SHIFT) | \ + (roll_over_msk_q << VGT_DEBUG_REG17_roll_over_msk_q_SHIFT) | \ + (max_msk_ptr_q << VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT) | \ + (min_msk_ptr_q << VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT) | \ + (bgrp_trigger << VGT_DEBUG_REG17_bgrp_trigger_SHIFT)) + +#define VGT_DEBUG_REG17_GET_save_read_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_read_q_MASK) >> VGT_DEBUG_REG17_save_read_q_SHIFT) +#define VGT_DEBUG_REG17_GET_extend_read_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_extend_read_q_MASK) >> VGT_DEBUG_REG17_extend_read_q_SHIFT) +#define VGT_DEBUG_REG17_GET_grp_indx_size(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_grp_indx_size_MASK) >> VGT_DEBUG_REG17_grp_indx_size_SHIFT) +#define VGT_DEBUG_REG17_GET_cull_prim_true(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_cull_prim_true_MASK) >> VGT_DEBUG_REG17_cull_prim_true_SHIFT) +#define VGT_DEBUG_REG17_GET_reset_bit2_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_reset_bit2_q_MASK) >> VGT_DEBUG_REG17_reset_bit2_q_SHIFT) +#define VGT_DEBUG_REG17_GET_reset_bit1_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_reset_bit1_q_MASK) >> VGT_DEBUG_REG17_reset_bit1_q_SHIFT) +#define VGT_DEBUG_REG17_GET_first_reg_first_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_first_reg_first_q_MASK) >> VGT_DEBUG_REG17_first_reg_first_q_SHIFT) +#define VGT_DEBUG_REG17_GET_check_second_reg(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_check_second_reg_MASK) >> VGT_DEBUG_REG17_check_second_reg_SHIFT) +#define VGT_DEBUG_REG17_GET_check_first_reg(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_check_first_reg_MASK) >> VGT_DEBUG_REG17_check_first_reg_SHIFT) +#define VGT_DEBUG_REG17_GET_bgrp_cull_fetch_fifo_wdata(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK) >> VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT) +#define VGT_DEBUG_REG17_GET_save_cull_fetch_data2_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK) >> VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT) +#define VGT_DEBUG_REG17_GET_save_cull_fetch_data1_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK) >> VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT) +#define VGT_DEBUG_REG17_GET_save_byte_mask_data2_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK) >> VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT) +#define VGT_DEBUG_REG17_GET_save_byte_mask_data1_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK) >> VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT) +#define VGT_DEBUG_REG17_GET_to_second_reg_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_to_second_reg_q_MASK) >> VGT_DEBUG_REG17_to_second_reg_q_SHIFT) +#define VGT_DEBUG_REG17_GET_roll_over_msk_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_roll_over_msk_q_MASK) >> VGT_DEBUG_REG17_roll_over_msk_q_SHIFT) +#define VGT_DEBUG_REG17_GET_max_msk_ptr_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_max_msk_ptr_q_MASK) >> VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT) +#define VGT_DEBUG_REG17_GET_min_msk_ptr_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_min_msk_ptr_q_MASK) >> VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT) +#define VGT_DEBUG_REG17_GET_bgrp_trigger(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_bgrp_trigger_MASK) >> VGT_DEBUG_REG17_bgrp_trigger_SHIFT) + +#define VGT_DEBUG_REG17_SET_save_read_q(vgt_debug_reg17_reg, save_read_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_read_q_MASK) | (save_read_q << VGT_DEBUG_REG17_save_read_q_SHIFT) +#define VGT_DEBUG_REG17_SET_extend_read_q(vgt_debug_reg17_reg, extend_read_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_extend_read_q_MASK) | (extend_read_q << VGT_DEBUG_REG17_extend_read_q_SHIFT) +#define VGT_DEBUG_REG17_SET_grp_indx_size(vgt_debug_reg17_reg, grp_indx_size) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_grp_indx_size_MASK) | (grp_indx_size << VGT_DEBUG_REG17_grp_indx_size_SHIFT) +#define VGT_DEBUG_REG17_SET_cull_prim_true(vgt_debug_reg17_reg, cull_prim_true) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_cull_prim_true_MASK) | (cull_prim_true << VGT_DEBUG_REG17_cull_prim_true_SHIFT) +#define VGT_DEBUG_REG17_SET_reset_bit2_q(vgt_debug_reg17_reg, reset_bit2_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_reset_bit2_q_MASK) | (reset_bit2_q << VGT_DEBUG_REG17_reset_bit2_q_SHIFT) +#define VGT_DEBUG_REG17_SET_reset_bit1_q(vgt_debug_reg17_reg, reset_bit1_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_reset_bit1_q_MASK) | (reset_bit1_q << VGT_DEBUG_REG17_reset_bit1_q_SHIFT) +#define VGT_DEBUG_REG17_SET_first_reg_first_q(vgt_debug_reg17_reg, first_reg_first_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_first_reg_first_q_MASK) | (first_reg_first_q << VGT_DEBUG_REG17_first_reg_first_q_SHIFT) +#define VGT_DEBUG_REG17_SET_check_second_reg(vgt_debug_reg17_reg, check_second_reg) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_check_second_reg_MASK) | (check_second_reg << VGT_DEBUG_REG17_check_second_reg_SHIFT) +#define VGT_DEBUG_REG17_SET_check_first_reg(vgt_debug_reg17_reg, check_first_reg) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_check_first_reg_MASK) | (check_first_reg << VGT_DEBUG_REG17_check_first_reg_SHIFT) +#define VGT_DEBUG_REG17_SET_bgrp_cull_fetch_fifo_wdata(vgt_debug_reg17_reg, bgrp_cull_fetch_fifo_wdata) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK) | (bgrp_cull_fetch_fifo_wdata << VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT) +#define VGT_DEBUG_REG17_SET_save_cull_fetch_data2_q(vgt_debug_reg17_reg, save_cull_fetch_data2_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK) | (save_cull_fetch_data2_q << VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT) +#define VGT_DEBUG_REG17_SET_save_cull_fetch_data1_q(vgt_debug_reg17_reg, save_cull_fetch_data1_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK) | (save_cull_fetch_data1_q << VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT) +#define VGT_DEBUG_REG17_SET_save_byte_mask_data2_q(vgt_debug_reg17_reg, save_byte_mask_data2_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK) | (save_byte_mask_data2_q << VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT) +#define VGT_DEBUG_REG17_SET_save_byte_mask_data1_q(vgt_debug_reg17_reg, save_byte_mask_data1_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK) | (save_byte_mask_data1_q << VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT) +#define VGT_DEBUG_REG17_SET_to_second_reg_q(vgt_debug_reg17_reg, to_second_reg_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_to_second_reg_q_MASK) | (to_second_reg_q << VGT_DEBUG_REG17_to_second_reg_q_SHIFT) +#define VGT_DEBUG_REG17_SET_roll_over_msk_q(vgt_debug_reg17_reg, roll_over_msk_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_roll_over_msk_q_MASK) | (roll_over_msk_q << VGT_DEBUG_REG17_roll_over_msk_q_SHIFT) +#define VGT_DEBUG_REG17_SET_max_msk_ptr_q(vgt_debug_reg17_reg, max_msk_ptr_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_max_msk_ptr_q_MASK) | (max_msk_ptr_q << VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT) +#define VGT_DEBUG_REG17_SET_min_msk_ptr_q(vgt_debug_reg17_reg, min_msk_ptr_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_min_msk_ptr_q_MASK) | (min_msk_ptr_q << VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT) +#define VGT_DEBUG_REG17_SET_bgrp_trigger(vgt_debug_reg17_reg, bgrp_trigger) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG17_bgrp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg17_t { + unsigned int save_read_q : VGT_DEBUG_REG17_save_read_q_SIZE; + unsigned int extend_read_q : VGT_DEBUG_REG17_extend_read_q_SIZE; + unsigned int grp_indx_size : VGT_DEBUG_REG17_grp_indx_size_SIZE; + unsigned int cull_prim_true : VGT_DEBUG_REG17_cull_prim_true_SIZE; + unsigned int reset_bit2_q : VGT_DEBUG_REG17_reset_bit2_q_SIZE; + unsigned int reset_bit1_q : VGT_DEBUG_REG17_reset_bit1_q_SIZE; + unsigned int first_reg_first_q : VGT_DEBUG_REG17_first_reg_first_q_SIZE; + unsigned int check_second_reg : VGT_DEBUG_REG17_check_second_reg_SIZE; + unsigned int check_first_reg : VGT_DEBUG_REG17_check_first_reg_SIZE; + unsigned int bgrp_cull_fetch_fifo_wdata : VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE; + unsigned int save_cull_fetch_data2_q : VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE; + unsigned int save_cull_fetch_data1_q : VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE; + unsigned int save_byte_mask_data2_q : VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE; + unsigned int save_byte_mask_data1_q : VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE; + unsigned int to_second_reg_q : VGT_DEBUG_REG17_to_second_reg_q_SIZE; + unsigned int roll_over_msk_q : VGT_DEBUG_REG17_roll_over_msk_q_SIZE; + unsigned int max_msk_ptr_q : VGT_DEBUG_REG17_max_msk_ptr_q_SIZE; + unsigned int min_msk_ptr_q : VGT_DEBUG_REG17_min_msk_ptr_q_SIZE; + unsigned int bgrp_trigger : VGT_DEBUG_REG17_bgrp_trigger_SIZE; + } vgt_debug_reg17_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg17_t { + unsigned int bgrp_trigger : VGT_DEBUG_REG17_bgrp_trigger_SIZE; + unsigned int min_msk_ptr_q : VGT_DEBUG_REG17_min_msk_ptr_q_SIZE; + unsigned int max_msk_ptr_q : VGT_DEBUG_REG17_max_msk_ptr_q_SIZE; + unsigned int roll_over_msk_q : VGT_DEBUG_REG17_roll_over_msk_q_SIZE; + unsigned int to_second_reg_q : VGT_DEBUG_REG17_to_second_reg_q_SIZE; + unsigned int save_byte_mask_data1_q : VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE; + unsigned int save_byte_mask_data2_q : VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE; + unsigned int save_cull_fetch_data1_q : VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE; + unsigned int save_cull_fetch_data2_q : VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE; + unsigned int bgrp_cull_fetch_fifo_wdata : VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE; + unsigned int check_first_reg : VGT_DEBUG_REG17_check_first_reg_SIZE; + unsigned int check_second_reg : VGT_DEBUG_REG17_check_second_reg_SIZE; + unsigned int first_reg_first_q : VGT_DEBUG_REG17_first_reg_first_q_SIZE; + unsigned int reset_bit1_q : VGT_DEBUG_REG17_reset_bit1_q_SIZE; + unsigned int reset_bit2_q : VGT_DEBUG_REG17_reset_bit2_q_SIZE; + unsigned int cull_prim_true : VGT_DEBUG_REG17_cull_prim_true_SIZE; + unsigned int grp_indx_size : VGT_DEBUG_REG17_grp_indx_size_SIZE; + unsigned int extend_read_q : VGT_DEBUG_REG17_extend_read_q_SIZE; + unsigned int save_read_q : VGT_DEBUG_REG17_save_read_q_SIZE; + } vgt_debug_reg17_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg17_t f; +} vgt_debug_reg17_u; + + +/* + * VGT_DEBUG_REG18 struct + */ + +#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE 6 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE 6 +#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE 1 +#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE 2 +#define VGT_DEBUG_REG18_dma_mem_full_SIZE 1 +#define VGT_DEBUG_REG18_dma_ram_re_SIZE 1 +#define VGT_DEBUG_REG18_dma_ram_we_SIZE 1 +#define VGT_DEBUG_REG18_dma_mem_empty_SIZE 1 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE 1 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE 1 +#define VGT_DEBUG_REG18_bin_mem_full_SIZE 1 +#define VGT_DEBUG_REG18_bin_ram_we_SIZE 1 +#define VGT_DEBUG_REG18_bin_ram_re_SIZE 1 +#define VGT_DEBUG_REG18_bin_mem_empty_SIZE 1 +#define VGT_DEBUG_REG18_start_bin_req_SIZE 1 +#define VGT_DEBUG_REG18_fetch_cull_not_used_SIZE 1 +#define VGT_DEBUG_REG18_dma_req_xfer_SIZE 1 +#define VGT_DEBUG_REG18_have_valid_bin_req_SIZE 1 +#define VGT_DEBUG_REG18_have_valid_dma_req_SIZE 1 +#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE 1 +#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE 1 + +#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT 0 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT 6 +#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT 12 +#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT 13 +#define VGT_DEBUG_REG18_dma_mem_full_SHIFT 15 +#define VGT_DEBUG_REG18_dma_ram_re_SHIFT 16 +#define VGT_DEBUG_REG18_dma_ram_we_SHIFT 17 +#define VGT_DEBUG_REG18_dma_mem_empty_SHIFT 18 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT 19 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT 20 +#define VGT_DEBUG_REG18_bin_mem_full_SHIFT 21 +#define VGT_DEBUG_REG18_bin_ram_we_SHIFT 22 +#define VGT_DEBUG_REG18_bin_ram_re_SHIFT 23 +#define VGT_DEBUG_REG18_bin_mem_empty_SHIFT 24 +#define VGT_DEBUG_REG18_start_bin_req_SHIFT 25 +#define VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT 26 +#define VGT_DEBUG_REG18_dma_req_xfer_SHIFT 27 +#define VGT_DEBUG_REG18_have_valid_bin_req_SHIFT 28 +#define VGT_DEBUG_REG18_have_valid_dma_req_SHIFT 29 +#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT 30 +#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT 31 + +#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK 0x0000003f +#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK 0x00000fc0 +#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK 0x00001000 +#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK 0x00006000 +#define VGT_DEBUG_REG18_dma_mem_full_MASK 0x00008000 +#define VGT_DEBUG_REG18_dma_ram_re_MASK 0x00010000 +#define VGT_DEBUG_REG18_dma_ram_we_MASK 0x00020000 +#define VGT_DEBUG_REG18_dma_mem_empty_MASK 0x00040000 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK 0x00080000 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK 0x00100000 +#define VGT_DEBUG_REG18_bin_mem_full_MASK 0x00200000 +#define VGT_DEBUG_REG18_bin_ram_we_MASK 0x00400000 +#define VGT_DEBUG_REG18_bin_ram_re_MASK 0x00800000 +#define VGT_DEBUG_REG18_bin_mem_empty_MASK 0x01000000 +#define VGT_DEBUG_REG18_start_bin_req_MASK 0x02000000 +#define VGT_DEBUG_REG18_fetch_cull_not_used_MASK 0x04000000 +#define VGT_DEBUG_REG18_dma_req_xfer_MASK 0x08000000 +#define VGT_DEBUG_REG18_have_valid_bin_req_MASK 0x10000000 +#define VGT_DEBUG_REG18_have_valid_dma_req_MASK 0x20000000 +#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK 0x40000000 +#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK 0x80000000 + +#define VGT_DEBUG_REG18_MASK \ + (VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK | \ + VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK | \ + VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK | \ + VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK | \ + VGT_DEBUG_REG18_dma_mem_full_MASK | \ + VGT_DEBUG_REG18_dma_ram_re_MASK | \ + VGT_DEBUG_REG18_dma_ram_we_MASK | \ + VGT_DEBUG_REG18_dma_mem_empty_MASK | \ + VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK | \ + VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK | \ + VGT_DEBUG_REG18_bin_mem_full_MASK | \ + VGT_DEBUG_REG18_bin_ram_we_MASK | \ + VGT_DEBUG_REG18_bin_ram_re_MASK | \ + VGT_DEBUG_REG18_bin_mem_empty_MASK | \ + VGT_DEBUG_REG18_start_bin_req_MASK | \ + VGT_DEBUG_REG18_fetch_cull_not_used_MASK | \ + VGT_DEBUG_REG18_dma_req_xfer_MASK | \ + VGT_DEBUG_REG18_have_valid_bin_req_MASK | \ + VGT_DEBUG_REG18_have_valid_dma_req_MASK | \ + VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK | \ + VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) + +#define VGT_DEBUG_REG18(dma_data_fifo_mem_raddr, dma_data_fifo_mem_waddr, dma_bgrp_byte_mask_fifo_re, dma_bgrp_dma_data_fifo_rptr, dma_mem_full, dma_ram_re, dma_ram_we, dma_mem_empty, dma_data_fifo_mem_re, dma_data_fifo_mem_we, bin_mem_full, bin_ram_we, bin_ram_re, bin_mem_empty, start_bin_req, fetch_cull_not_used, dma_req_xfer, have_valid_bin_req, have_valid_dma_req, bgrp_dma_di_grp_cull_enable, bgrp_dma_di_pre_fetch_cull_enable) \ + ((dma_data_fifo_mem_raddr << VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT) | \ + (dma_data_fifo_mem_waddr << VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT) | \ + (dma_bgrp_byte_mask_fifo_re << VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT) | \ + (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT) | \ + (dma_mem_full << VGT_DEBUG_REG18_dma_mem_full_SHIFT) | \ + (dma_ram_re << VGT_DEBUG_REG18_dma_ram_re_SHIFT) | \ + (dma_ram_we << VGT_DEBUG_REG18_dma_ram_we_SHIFT) | \ + (dma_mem_empty << VGT_DEBUG_REG18_dma_mem_empty_SHIFT) | \ + (dma_data_fifo_mem_re << VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT) | \ + (dma_data_fifo_mem_we << VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT) | \ + (bin_mem_full << VGT_DEBUG_REG18_bin_mem_full_SHIFT) | \ + (bin_ram_we << VGT_DEBUG_REG18_bin_ram_we_SHIFT) | \ + (bin_ram_re << VGT_DEBUG_REG18_bin_ram_re_SHIFT) | \ + (bin_mem_empty << VGT_DEBUG_REG18_bin_mem_empty_SHIFT) | \ + (start_bin_req << VGT_DEBUG_REG18_start_bin_req_SHIFT) | \ + (fetch_cull_not_used << VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT) | \ + (dma_req_xfer << VGT_DEBUG_REG18_dma_req_xfer_SHIFT) | \ + (have_valid_bin_req << VGT_DEBUG_REG18_have_valid_bin_req_SHIFT) | \ + (have_valid_dma_req << VGT_DEBUG_REG18_have_valid_dma_req_SHIFT) | \ + (bgrp_dma_di_grp_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT) | \ + (bgrp_dma_di_pre_fetch_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT)) + +#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_raddr(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_waddr(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_bgrp_byte_mask_fifo_re(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK) >> VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK) >> VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_mem_full(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_mem_full_MASK) >> VGT_DEBUG_REG18_dma_mem_full_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_ram_re(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_ram_re_MASK) >> VGT_DEBUG_REG18_dma_ram_re_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_ram_we(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_ram_we_MASK) >> VGT_DEBUG_REG18_dma_ram_we_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_mem_empty(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_mem_empty_MASK) >> VGT_DEBUG_REG18_dma_mem_empty_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_re(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_we(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT) +#define VGT_DEBUG_REG18_GET_bin_mem_full(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_mem_full_MASK) >> VGT_DEBUG_REG18_bin_mem_full_SHIFT) +#define VGT_DEBUG_REG18_GET_bin_ram_we(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_ram_we_MASK) >> VGT_DEBUG_REG18_bin_ram_we_SHIFT) +#define VGT_DEBUG_REG18_GET_bin_ram_re(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_ram_re_MASK) >> VGT_DEBUG_REG18_bin_ram_re_SHIFT) +#define VGT_DEBUG_REG18_GET_bin_mem_empty(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_mem_empty_MASK) >> VGT_DEBUG_REG18_bin_mem_empty_SHIFT) +#define VGT_DEBUG_REG18_GET_start_bin_req(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_start_bin_req_MASK) >> VGT_DEBUG_REG18_start_bin_req_SHIFT) +#define VGT_DEBUG_REG18_GET_fetch_cull_not_used(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_fetch_cull_not_used_MASK) >> VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_req_xfer(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_req_xfer_MASK) >> VGT_DEBUG_REG18_dma_req_xfer_SHIFT) +#define VGT_DEBUG_REG18_GET_have_valid_bin_req(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_have_valid_bin_req_MASK) >> VGT_DEBUG_REG18_have_valid_bin_req_SHIFT) +#define VGT_DEBUG_REG18_GET_have_valid_dma_req(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_have_valid_dma_req_MASK) >> VGT_DEBUG_REG18_have_valid_dma_req_SHIFT) +#define VGT_DEBUG_REG18_GET_bgrp_dma_di_grp_cull_enable(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK) >> VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT) +#define VGT_DEBUG_REG18_GET_bgrp_dma_di_pre_fetch_cull_enable(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) >> VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT) + +#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_raddr(vgt_debug_reg18_reg, dma_data_fifo_mem_raddr) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK) | (dma_data_fifo_mem_raddr << VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_waddr(vgt_debug_reg18_reg, dma_data_fifo_mem_waddr) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK) | (dma_data_fifo_mem_waddr << VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_bgrp_byte_mask_fifo_re(vgt_debug_reg18_reg, dma_bgrp_byte_mask_fifo_re) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK) | (dma_bgrp_byte_mask_fifo_re << VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg18_reg, dma_bgrp_dma_data_fifo_rptr) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK) | (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_mem_full(vgt_debug_reg18_reg, dma_mem_full) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_mem_full_MASK) | (dma_mem_full << VGT_DEBUG_REG18_dma_mem_full_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_ram_re(vgt_debug_reg18_reg, dma_ram_re) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_ram_re_MASK) | (dma_ram_re << VGT_DEBUG_REG18_dma_ram_re_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_ram_we(vgt_debug_reg18_reg, dma_ram_we) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_ram_we_MASK) | (dma_ram_we << VGT_DEBUG_REG18_dma_ram_we_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_mem_empty(vgt_debug_reg18_reg, dma_mem_empty) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_mem_empty_MASK) | (dma_mem_empty << VGT_DEBUG_REG18_dma_mem_empty_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_re(vgt_debug_reg18_reg, dma_data_fifo_mem_re) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK) | (dma_data_fifo_mem_re << VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_we(vgt_debug_reg18_reg, dma_data_fifo_mem_we) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK) | (dma_data_fifo_mem_we << VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT) +#define VGT_DEBUG_REG18_SET_bin_mem_full(vgt_debug_reg18_reg, bin_mem_full) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_mem_full_MASK) | (bin_mem_full << VGT_DEBUG_REG18_bin_mem_full_SHIFT) +#define VGT_DEBUG_REG18_SET_bin_ram_we(vgt_debug_reg18_reg, bin_ram_we) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_ram_we_MASK) | (bin_ram_we << VGT_DEBUG_REG18_bin_ram_we_SHIFT) +#define VGT_DEBUG_REG18_SET_bin_ram_re(vgt_debug_reg18_reg, bin_ram_re) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_ram_re_MASK) | (bin_ram_re << VGT_DEBUG_REG18_bin_ram_re_SHIFT) +#define VGT_DEBUG_REG18_SET_bin_mem_empty(vgt_debug_reg18_reg, bin_mem_empty) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_mem_empty_MASK) | (bin_mem_empty << VGT_DEBUG_REG18_bin_mem_empty_SHIFT) +#define VGT_DEBUG_REG18_SET_start_bin_req(vgt_debug_reg18_reg, start_bin_req) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_start_bin_req_MASK) | (start_bin_req << VGT_DEBUG_REG18_start_bin_req_SHIFT) +#define VGT_DEBUG_REG18_SET_fetch_cull_not_used(vgt_debug_reg18_reg, fetch_cull_not_used) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_fetch_cull_not_used_MASK) | (fetch_cull_not_used << VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_req_xfer(vgt_debug_reg18_reg, dma_req_xfer) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_req_xfer_MASK) | (dma_req_xfer << VGT_DEBUG_REG18_dma_req_xfer_SHIFT) +#define VGT_DEBUG_REG18_SET_have_valid_bin_req(vgt_debug_reg18_reg, have_valid_bin_req) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_have_valid_bin_req_MASK) | (have_valid_bin_req << VGT_DEBUG_REG18_have_valid_bin_req_SHIFT) +#define VGT_DEBUG_REG18_SET_have_valid_dma_req(vgt_debug_reg18_reg, have_valid_dma_req) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_have_valid_dma_req_MASK) | (have_valid_dma_req << VGT_DEBUG_REG18_have_valid_dma_req_SHIFT) +#define VGT_DEBUG_REG18_SET_bgrp_dma_di_grp_cull_enable(vgt_debug_reg18_reg, bgrp_dma_di_grp_cull_enable) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK) | (bgrp_dma_di_grp_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT) +#define VGT_DEBUG_REG18_SET_bgrp_dma_di_pre_fetch_cull_enable(vgt_debug_reg18_reg, bgrp_dma_di_pre_fetch_cull_enable) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) | (bgrp_dma_di_pre_fetch_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg18_t { + unsigned int dma_data_fifo_mem_raddr : VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE; + unsigned int dma_data_fifo_mem_waddr : VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE; + unsigned int dma_bgrp_byte_mask_fifo_re : VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE; + unsigned int dma_bgrp_dma_data_fifo_rptr : VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE; + unsigned int dma_mem_full : VGT_DEBUG_REG18_dma_mem_full_SIZE; + unsigned int dma_ram_re : VGT_DEBUG_REG18_dma_ram_re_SIZE; + unsigned int dma_ram_we : VGT_DEBUG_REG18_dma_ram_we_SIZE; + unsigned int dma_mem_empty : VGT_DEBUG_REG18_dma_mem_empty_SIZE; + unsigned int dma_data_fifo_mem_re : VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE; + unsigned int dma_data_fifo_mem_we : VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE; + unsigned int bin_mem_full : VGT_DEBUG_REG18_bin_mem_full_SIZE; + unsigned int bin_ram_we : VGT_DEBUG_REG18_bin_ram_we_SIZE; + unsigned int bin_ram_re : VGT_DEBUG_REG18_bin_ram_re_SIZE; + unsigned int bin_mem_empty : VGT_DEBUG_REG18_bin_mem_empty_SIZE; + unsigned int start_bin_req : VGT_DEBUG_REG18_start_bin_req_SIZE; + unsigned int fetch_cull_not_used : VGT_DEBUG_REG18_fetch_cull_not_used_SIZE; + unsigned int dma_req_xfer : VGT_DEBUG_REG18_dma_req_xfer_SIZE; + unsigned int have_valid_bin_req : VGT_DEBUG_REG18_have_valid_bin_req_SIZE; + unsigned int have_valid_dma_req : VGT_DEBUG_REG18_have_valid_dma_req_SIZE; + unsigned int bgrp_dma_di_grp_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE; + unsigned int bgrp_dma_di_pre_fetch_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE; + } vgt_debug_reg18_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg18_t { + unsigned int bgrp_dma_di_pre_fetch_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE; + unsigned int bgrp_dma_di_grp_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE; + unsigned int have_valid_dma_req : VGT_DEBUG_REG18_have_valid_dma_req_SIZE; + unsigned int have_valid_bin_req : VGT_DEBUG_REG18_have_valid_bin_req_SIZE; + unsigned int dma_req_xfer : VGT_DEBUG_REG18_dma_req_xfer_SIZE; + unsigned int fetch_cull_not_used : VGT_DEBUG_REG18_fetch_cull_not_used_SIZE; + unsigned int start_bin_req : VGT_DEBUG_REG18_start_bin_req_SIZE; + unsigned int bin_mem_empty : VGT_DEBUG_REG18_bin_mem_empty_SIZE; + unsigned int bin_ram_re : VGT_DEBUG_REG18_bin_ram_re_SIZE; + unsigned int bin_ram_we : VGT_DEBUG_REG18_bin_ram_we_SIZE; + unsigned int bin_mem_full : VGT_DEBUG_REG18_bin_mem_full_SIZE; + unsigned int dma_data_fifo_mem_we : VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE; + unsigned int dma_data_fifo_mem_re : VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE; + unsigned int dma_mem_empty : VGT_DEBUG_REG18_dma_mem_empty_SIZE; + unsigned int dma_ram_we : VGT_DEBUG_REG18_dma_ram_we_SIZE; + unsigned int dma_ram_re : VGT_DEBUG_REG18_dma_ram_re_SIZE; + unsigned int dma_mem_full : VGT_DEBUG_REG18_dma_mem_full_SIZE; + unsigned int dma_bgrp_dma_data_fifo_rptr : VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE; + unsigned int dma_bgrp_byte_mask_fifo_re : VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE; + unsigned int dma_data_fifo_mem_waddr : VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE; + unsigned int dma_data_fifo_mem_raddr : VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE; + } vgt_debug_reg18_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg18_t f; +} vgt_debug_reg18_u; + + +/* + * VGT_DEBUG_REG20 struct + */ + +#define VGT_DEBUG_REG20_prim_side_indx_valid_SIZE 1 +#define VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE 1 +#define VGT_DEBUG_REG20_indx_side_fifo_re_SIZE 1 +#define VGT_DEBUG_REG20_indx_side_fifo_we_SIZE 1 +#define VGT_DEBUG_REG20_indx_side_fifo_full_SIZE 1 +#define VGT_DEBUG_REG20_prim_buffer_empty_SIZE 1 +#define VGT_DEBUG_REG20_prim_buffer_re_SIZE 1 +#define VGT_DEBUG_REG20_prim_buffer_we_SIZE 1 +#define VGT_DEBUG_REG20_prim_buffer_full_SIZE 1 +#define VGT_DEBUG_REG20_indx_buffer_empty_SIZE 1 +#define VGT_DEBUG_REG20_indx_buffer_re_SIZE 1 +#define VGT_DEBUG_REG20_indx_buffer_we_SIZE 1 +#define VGT_DEBUG_REG20_indx_buffer_full_SIZE 1 +#define VGT_DEBUG_REG20_hold_prim_SIZE 1 +#define VGT_DEBUG_REG20_sent_cnt_SIZE 4 +#define VGT_DEBUG_REG20_start_of_vtx_vector_SIZE 1 +#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE 1 +#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE 1 +#define VGT_DEBUG_REG20_buffered_prim_type_event_SIZE 5 +#define VGT_DEBUG_REG20_out_trigger_SIZE 1 + +#define VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT 0 +#define VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT 1 +#define VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT 2 +#define VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT 3 +#define VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT 4 +#define VGT_DEBUG_REG20_prim_buffer_empty_SHIFT 5 +#define VGT_DEBUG_REG20_prim_buffer_re_SHIFT 6 +#define VGT_DEBUG_REG20_prim_buffer_we_SHIFT 7 +#define VGT_DEBUG_REG20_prim_buffer_full_SHIFT 8 +#define VGT_DEBUG_REG20_indx_buffer_empty_SHIFT 9 +#define VGT_DEBUG_REG20_indx_buffer_re_SHIFT 10 +#define VGT_DEBUG_REG20_indx_buffer_we_SHIFT 11 +#define VGT_DEBUG_REG20_indx_buffer_full_SHIFT 12 +#define VGT_DEBUG_REG20_hold_prim_SHIFT 13 +#define VGT_DEBUG_REG20_sent_cnt_SHIFT 14 +#define VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT 18 +#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT 19 +#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT 20 +#define VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT 21 +#define VGT_DEBUG_REG20_out_trigger_SHIFT 26 + +#define VGT_DEBUG_REG20_prim_side_indx_valid_MASK 0x00000001 +#define VGT_DEBUG_REG20_indx_side_fifo_empty_MASK 0x00000002 +#define VGT_DEBUG_REG20_indx_side_fifo_re_MASK 0x00000004 +#define VGT_DEBUG_REG20_indx_side_fifo_we_MASK 0x00000008 +#define VGT_DEBUG_REG20_indx_side_fifo_full_MASK 0x00000010 +#define VGT_DEBUG_REG20_prim_buffer_empty_MASK 0x00000020 +#define VGT_DEBUG_REG20_prim_buffer_re_MASK 0x00000040 +#define VGT_DEBUG_REG20_prim_buffer_we_MASK 0x00000080 +#define VGT_DEBUG_REG20_prim_buffer_full_MASK 0x00000100 +#define VGT_DEBUG_REG20_indx_buffer_empty_MASK 0x00000200 +#define VGT_DEBUG_REG20_indx_buffer_re_MASK 0x00000400 +#define VGT_DEBUG_REG20_indx_buffer_we_MASK 0x00000800 +#define VGT_DEBUG_REG20_indx_buffer_full_MASK 0x00001000 +#define VGT_DEBUG_REG20_hold_prim_MASK 0x00002000 +#define VGT_DEBUG_REG20_sent_cnt_MASK 0x0003c000 +#define VGT_DEBUG_REG20_start_of_vtx_vector_MASK 0x00040000 +#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK 0x00080000 +#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK 0x00100000 +#define VGT_DEBUG_REG20_buffered_prim_type_event_MASK 0x03e00000 +#define VGT_DEBUG_REG20_out_trigger_MASK 0x04000000 + +#define VGT_DEBUG_REG20_MASK \ + (VGT_DEBUG_REG20_prim_side_indx_valid_MASK | \ + VGT_DEBUG_REG20_indx_side_fifo_empty_MASK | \ + VGT_DEBUG_REG20_indx_side_fifo_re_MASK | \ + VGT_DEBUG_REG20_indx_side_fifo_we_MASK | \ + VGT_DEBUG_REG20_indx_side_fifo_full_MASK | \ + VGT_DEBUG_REG20_prim_buffer_empty_MASK | \ + VGT_DEBUG_REG20_prim_buffer_re_MASK | \ + VGT_DEBUG_REG20_prim_buffer_we_MASK | \ + VGT_DEBUG_REG20_prim_buffer_full_MASK | \ + VGT_DEBUG_REG20_indx_buffer_empty_MASK | \ + VGT_DEBUG_REG20_indx_buffer_re_MASK | \ + VGT_DEBUG_REG20_indx_buffer_we_MASK | \ + VGT_DEBUG_REG20_indx_buffer_full_MASK | \ + VGT_DEBUG_REG20_hold_prim_MASK | \ + VGT_DEBUG_REG20_sent_cnt_MASK | \ + VGT_DEBUG_REG20_start_of_vtx_vector_MASK | \ + VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK | \ + VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK | \ + VGT_DEBUG_REG20_buffered_prim_type_event_MASK | \ + VGT_DEBUG_REG20_out_trigger_MASK) + +#define VGT_DEBUG_REG20(prim_side_indx_valid, indx_side_fifo_empty, indx_side_fifo_re, indx_side_fifo_we, indx_side_fifo_full, prim_buffer_empty, prim_buffer_re, prim_buffer_we, prim_buffer_full, indx_buffer_empty, indx_buffer_re, indx_buffer_we, indx_buffer_full, hold_prim, sent_cnt, start_of_vtx_vector, clip_s_pre_hold_prim, clip_p_pre_hold_prim, buffered_prim_type_event, out_trigger) \ + ((prim_side_indx_valid << VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT) | \ + (indx_side_fifo_empty << VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT) | \ + (indx_side_fifo_re << VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT) | \ + (indx_side_fifo_we << VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT) | \ + (indx_side_fifo_full << VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT) | \ + (prim_buffer_empty << VGT_DEBUG_REG20_prim_buffer_empty_SHIFT) | \ + (prim_buffer_re << VGT_DEBUG_REG20_prim_buffer_re_SHIFT) | \ + (prim_buffer_we << VGT_DEBUG_REG20_prim_buffer_we_SHIFT) | \ + (prim_buffer_full << VGT_DEBUG_REG20_prim_buffer_full_SHIFT) | \ + (indx_buffer_empty << VGT_DEBUG_REG20_indx_buffer_empty_SHIFT) | \ + (indx_buffer_re << VGT_DEBUG_REG20_indx_buffer_re_SHIFT) | \ + (indx_buffer_we << VGT_DEBUG_REG20_indx_buffer_we_SHIFT) | \ + (indx_buffer_full << VGT_DEBUG_REG20_indx_buffer_full_SHIFT) | \ + (hold_prim << VGT_DEBUG_REG20_hold_prim_SHIFT) | \ + (sent_cnt << VGT_DEBUG_REG20_sent_cnt_SHIFT) | \ + (start_of_vtx_vector << VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT) | \ + (clip_s_pre_hold_prim << VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT) | \ + (clip_p_pre_hold_prim << VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT) | \ + (buffered_prim_type_event << VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT) | \ + (out_trigger << VGT_DEBUG_REG20_out_trigger_SHIFT)) + +#define VGT_DEBUG_REG20_GET_prim_side_indx_valid(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_side_indx_valid_MASK) >> VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_side_fifo_empty(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_empty_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_side_fifo_re(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_re_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_side_fifo_we(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_we_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_side_fifo_full(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_full_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT) +#define VGT_DEBUG_REG20_GET_prim_buffer_empty(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_empty_MASK) >> VGT_DEBUG_REG20_prim_buffer_empty_SHIFT) +#define VGT_DEBUG_REG20_GET_prim_buffer_re(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_re_MASK) >> VGT_DEBUG_REG20_prim_buffer_re_SHIFT) +#define VGT_DEBUG_REG20_GET_prim_buffer_we(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_we_MASK) >> VGT_DEBUG_REG20_prim_buffer_we_SHIFT) +#define VGT_DEBUG_REG20_GET_prim_buffer_full(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_full_MASK) >> VGT_DEBUG_REG20_prim_buffer_full_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_buffer_empty(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_empty_MASK) >> VGT_DEBUG_REG20_indx_buffer_empty_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_buffer_re(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_re_MASK) >> VGT_DEBUG_REG20_indx_buffer_re_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_buffer_we(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_we_MASK) >> VGT_DEBUG_REG20_indx_buffer_we_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_buffer_full(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_full_MASK) >> VGT_DEBUG_REG20_indx_buffer_full_SHIFT) +#define VGT_DEBUG_REG20_GET_hold_prim(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_hold_prim_MASK) >> VGT_DEBUG_REG20_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_GET_sent_cnt(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_sent_cnt_MASK) >> VGT_DEBUG_REG20_sent_cnt_SHIFT) +#define VGT_DEBUG_REG20_GET_start_of_vtx_vector(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_start_of_vtx_vector_MASK) >> VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT) +#define VGT_DEBUG_REG20_GET_clip_s_pre_hold_prim(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK) >> VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_GET_clip_p_pre_hold_prim(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK) >> VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_GET_buffered_prim_type_event(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_buffered_prim_type_event_MASK) >> VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT) +#define VGT_DEBUG_REG20_GET_out_trigger(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_out_trigger_MASK) >> VGT_DEBUG_REG20_out_trigger_SHIFT) + +#define VGT_DEBUG_REG20_SET_prim_side_indx_valid(vgt_debug_reg20_reg, prim_side_indx_valid) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_side_indx_valid_MASK) | (prim_side_indx_valid << VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_side_fifo_empty(vgt_debug_reg20_reg, indx_side_fifo_empty) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_empty_MASK) | (indx_side_fifo_empty << VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_side_fifo_re(vgt_debug_reg20_reg, indx_side_fifo_re) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_re_MASK) | (indx_side_fifo_re << VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_side_fifo_we(vgt_debug_reg20_reg, indx_side_fifo_we) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_we_MASK) | (indx_side_fifo_we << VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_side_fifo_full(vgt_debug_reg20_reg, indx_side_fifo_full) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_full_MASK) | (indx_side_fifo_full << VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT) +#define VGT_DEBUG_REG20_SET_prim_buffer_empty(vgt_debug_reg20_reg, prim_buffer_empty) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_empty_MASK) | (prim_buffer_empty << VGT_DEBUG_REG20_prim_buffer_empty_SHIFT) +#define VGT_DEBUG_REG20_SET_prim_buffer_re(vgt_debug_reg20_reg, prim_buffer_re) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_re_MASK) | (prim_buffer_re << VGT_DEBUG_REG20_prim_buffer_re_SHIFT) +#define VGT_DEBUG_REG20_SET_prim_buffer_we(vgt_debug_reg20_reg, prim_buffer_we) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_we_MASK) | (prim_buffer_we << VGT_DEBUG_REG20_prim_buffer_we_SHIFT) +#define VGT_DEBUG_REG20_SET_prim_buffer_full(vgt_debug_reg20_reg, prim_buffer_full) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_full_MASK) | (prim_buffer_full << VGT_DEBUG_REG20_prim_buffer_full_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_buffer_empty(vgt_debug_reg20_reg, indx_buffer_empty) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_empty_MASK) | (indx_buffer_empty << VGT_DEBUG_REG20_indx_buffer_empty_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_buffer_re(vgt_debug_reg20_reg, indx_buffer_re) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_re_MASK) | (indx_buffer_re << VGT_DEBUG_REG20_indx_buffer_re_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_buffer_we(vgt_debug_reg20_reg, indx_buffer_we) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_we_MASK) | (indx_buffer_we << VGT_DEBUG_REG20_indx_buffer_we_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_buffer_full(vgt_debug_reg20_reg, indx_buffer_full) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_full_MASK) | (indx_buffer_full << VGT_DEBUG_REG20_indx_buffer_full_SHIFT) +#define VGT_DEBUG_REG20_SET_hold_prim(vgt_debug_reg20_reg, hold_prim) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_hold_prim_MASK) | (hold_prim << VGT_DEBUG_REG20_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_SET_sent_cnt(vgt_debug_reg20_reg, sent_cnt) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_sent_cnt_MASK) | (sent_cnt << VGT_DEBUG_REG20_sent_cnt_SHIFT) +#define VGT_DEBUG_REG20_SET_start_of_vtx_vector(vgt_debug_reg20_reg, start_of_vtx_vector) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_start_of_vtx_vector_MASK) | (start_of_vtx_vector << VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT) +#define VGT_DEBUG_REG20_SET_clip_s_pre_hold_prim(vgt_debug_reg20_reg, clip_s_pre_hold_prim) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK) | (clip_s_pre_hold_prim << VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_SET_clip_p_pre_hold_prim(vgt_debug_reg20_reg, clip_p_pre_hold_prim) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK) | (clip_p_pre_hold_prim << VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_SET_buffered_prim_type_event(vgt_debug_reg20_reg, buffered_prim_type_event) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_buffered_prim_type_event_MASK) | (buffered_prim_type_event << VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT) +#define VGT_DEBUG_REG20_SET_out_trigger(vgt_debug_reg20_reg, out_trigger) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_out_trigger_MASK) | (out_trigger << VGT_DEBUG_REG20_out_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg20_t { + unsigned int prim_side_indx_valid : VGT_DEBUG_REG20_prim_side_indx_valid_SIZE; + unsigned int indx_side_fifo_empty : VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE; + unsigned int indx_side_fifo_re : VGT_DEBUG_REG20_indx_side_fifo_re_SIZE; + unsigned int indx_side_fifo_we : VGT_DEBUG_REG20_indx_side_fifo_we_SIZE; + unsigned int indx_side_fifo_full : VGT_DEBUG_REG20_indx_side_fifo_full_SIZE; + unsigned int prim_buffer_empty : VGT_DEBUG_REG20_prim_buffer_empty_SIZE; + unsigned int prim_buffer_re : VGT_DEBUG_REG20_prim_buffer_re_SIZE; + unsigned int prim_buffer_we : VGT_DEBUG_REG20_prim_buffer_we_SIZE; + unsigned int prim_buffer_full : VGT_DEBUG_REG20_prim_buffer_full_SIZE; + unsigned int indx_buffer_empty : VGT_DEBUG_REG20_indx_buffer_empty_SIZE; + unsigned int indx_buffer_re : VGT_DEBUG_REG20_indx_buffer_re_SIZE; + unsigned int indx_buffer_we : VGT_DEBUG_REG20_indx_buffer_we_SIZE; + unsigned int indx_buffer_full : VGT_DEBUG_REG20_indx_buffer_full_SIZE; + unsigned int hold_prim : VGT_DEBUG_REG20_hold_prim_SIZE; + unsigned int sent_cnt : VGT_DEBUG_REG20_sent_cnt_SIZE; + unsigned int start_of_vtx_vector : VGT_DEBUG_REG20_start_of_vtx_vector_SIZE; + unsigned int clip_s_pre_hold_prim : VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE; + unsigned int clip_p_pre_hold_prim : VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE; + unsigned int buffered_prim_type_event : VGT_DEBUG_REG20_buffered_prim_type_event_SIZE; + unsigned int out_trigger : VGT_DEBUG_REG20_out_trigger_SIZE; + unsigned int : 5; + } vgt_debug_reg20_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg20_t { + unsigned int : 5; + unsigned int out_trigger : VGT_DEBUG_REG20_out_trigger_SIZE; + unsigned int buffered_prim_type_event : VGT_DEBUG_REG20_buffered_prim_type_event_SIZE; + unsigned int clip_p_pre_hold_prim : VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE; + unsigned int clip_s_pre_hold_prim : VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE; + unsigned int start_of_vtx_vector : VGT_DEBUG_REG20_start_of_vtx_vector_SIZE; + unsigned int sent_cnt : VGT_DEBUG_REG20_sent_cnt_SIZE; + unsigned int hold_prim : VGT_DEBUG_REG20_hold_prim_SIZE; + unsigned int indx_buffer_full : VGT_DEBUG_REG20_indx_buffer_full_SIZE; + unsigned int indx_buffer_we : VGT_DEBUG_REG20_indx_buffer_we_SIZE; + unsigned int indx_buffer_re : VGT_DEBUG_REG20_indx_buffer_re_SIZE; + unsigned int indx_buffer_empty : VGT_DEBUG_REG20_indx_buffer_empty_SIZE; + unsigned int prim_buffer_full : VGT_DEBUG_REG20_prim_buffer_full_SIZE; + unsigned int prim_buffer_we : VGT_DEBUG_REG20_prim_buffer_we_SIZE; + unsigned int prim_buffer_re : VGT_DEBUG_REG20_prim_buffer_re_SIZE; + unsigned int prim_buffer_empty : VGT_DEBUG_REG20_prim_buffer_empty_SIZE; + unsigned int indx_side_fifo_full : VGT_DEBUG_REG20_indx_side_fifo_full_SIZE; + unsigned int indx_side_fifo_we : VGT_DEBUG_REG20_indx_side_fifo_we_SIZE; + unsigned int indx_side_fifo_re : VGT_DEBUG_REG20_indx_side_fifo_re_SIZE; + unsigned int indx_side_fifo_empty : VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE; + unsigned int prim_side_indx_valid : VGT_DEBUG_REG20_prim_side_indx_valid_SIZE; + } vgt_debug_reg20_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg20_t f; +} vgt_debug_reg20_u; + + +/* + * VGT_DEBUG_REG21 struct + */ + +#define VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE 1 +#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE 3 +#define VGT_DEBUG_REG21_alloc_counter_q_SIZE 3 +#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE 3 +#define VGT_DEBUG_REG21_int_vtx_counter_q_SIZE 4 +#define VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE 4 +#define VGT_DEBUG_REG21_new_packet_q_SIZE 1 +#define VGT_DEBUG_REG21_new_allocate_q_SIZE 1 +#define VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE 2 +#define VGT_DEBUG_REG21_inserted_null_prim_q_SIZE 1 +#define VGT_DEBUG_REG21_insert_null_prim_SIZE 1 +#define VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE 1 +#define VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE 1 +#define VGT_DEBUG_REG21_buffered_thread_size_SIZE 1 +#define VGT_DEBUG_REG21_out_trigger_SIZE 1 + +#define VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT 0 +#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT 1 +#define VGT_DEBUG_REG21_alloc_counter_q_SHIFT 4 +#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT 7 +#define VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT 10 +#define VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT 14 +#define VGT_DEBUG_REG21_new_packet_q_SHIFT 18 +#define VGT_DEBUG_REG21_new_allocate_q_SHIFT 19 +#define VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT 20 +#define VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT 22 +#define VGT_DEBUG_REG21_insert_null_prim_SHIFT 23 +#define VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT 24 +#define VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT 25 +#define VGT_DEBUG_REG21_buffered_thread_size_SHIFT 26 +#define VGT_DEBUG_REG21_out_trigger_SHIFT 31 + +#define VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK 0x00000001 +#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK 0x0000000e +#define VGT_DEBUG_REG21_alloc_counter_q_MASK 0x00000070 +#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK 0x00000380 +#define VGT_DEBUG_REG21_int_vtx_counter_q_MASK 0x00003c00 +#define VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK 0x0003c000 +#define VGT_DEBUG_REG21_new_packet_q_MASK 0x00040000 +#define VGT_DEBUG_REG21_new_allocate_q_MASK 0x00080000 +#define VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK 0x00300000 +#define VGT_DEBUG_REG21_inserted_null_prim_q_MASK 0x00400000 +#define VGT_DEBUG_REG21_insert_null_prim_MASK 0x00800000 +#define VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK 0x01000000 +#define VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK 0x02000000 +#define VGT_DEBUG_REG21_buffered_thread_size_MASK 0x04000000 +#define VGT_DEBUG_REG21_out_trigger_MASK 0x80000000 + +#define VGT_DEBUG_REG21_MASK \ + (VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK | \ + VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK | \ + VGT_DEBUG_REG21_alloc_counter_q_MASK | \ + VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK | \ + VGT_DEBUG_REG21_int_vtx_counter_q_MASK | \ + VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK | \ + VGT_DEBUG_REG21_new_packet_q_MASK | \ + VGT_DEBUG_REG21_new_allocate_q_MASK | \ + VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK | \ + VGT_DEBUG_REG21_inserted_null_prim_q_MASK | \ + VGT_DEBUG_REG21_insert_null_prim_MASK | \ + VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK | \ + VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK | \ + VGT_DEBUG_REG21_buffered_thread_size_MASK | \ + VGT_DEBUG_REG21_out_trigger_MASK) + +#define VGT_DEBUG_REG21(null_terminate_vtx_vector, prim_end_of_vtx_vect_flags, alloc_counter_q, curr_slot_in_vtx_vect_q, int_vtx_counter_q, curr_dealloc_distance_q, new_packet_q, new_allocate_q, num_new_unique_rel_indx, inserted_null_prim_q, insert_null_prim, buffered_prim_eop_mux, prim_buffer_empty_mux, buffered_thread_size, out_trigger) \ + ((null_terminate_vtx_vector << VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT) | \ + (prim_end_of_vtx_vect_flags << VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT) | \ + (alloc_counter_q << VGT_DEBUG_REG21_alloc_counter_q_SHIFT) | \ + (curr_slot_in_vtx_vect_q << VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT) | \ + (int_vtx_counter_q << VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT) | \ + (curr_dealloc_distance_q << VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT) | \ + (new_packet_q << VGT_DEBUG_REG21_new_packet_q_SHIFT) | \ + (new_allocate_q << VGT_DEBUG_REG21_new_allocate_q_SHIFT) | \ + (num_new_unique_rel_indx << VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT) | \ + (inserted_null_prim_q << VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT) | \ + (insert_null_prim << VGT_DEBUG_REG21_insert_null_prim_SHIFT) | \ + (buffered_prim_eop_mux << VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT) | \ + (prim_buffer_empty_mux << VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT) | \ + (buffered_thread_size << VGT_DEBUG_REG21_buffered_thread_size_SHIFT) | \ + (out_trigger << VGT_DEBUG_REG21_out_trigger_SHIFT)) + +#define VGT_DEBUG_REG21_GET_null_terminate_vtx_vector(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK) >> VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT) +#define VGT_DEBUG_REG21_GET_prim_end_of_vtx_vect_flags(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK) >> VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT) +#define VGT_DEBUG_REG21_GET_alloc_counter_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_alloc_counter_q_MASK) >> VGT_DEBUG_REG21_alloc_counter_q_SHIFT) +#define VGT_DEBUG_REG21_GET_curr_slot_in_vtx_vect_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK) >> VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT) +#define VGT_DEBUG_REG21_GET_int_vtx_counter_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_int_vtx_counter_q_MASK) >> VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT) +#define VGT_DEBUG_REG21_GET_curr_dealloc_distance_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK) >> VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT) +#define VGT_DEBUG_REG21_GET_new_packet_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_new_packet_q_MASK) >> VGT_DEBUG_REG21_new_packet_q_SHIFT) +#define VGT_DEBUG_REG21_GET_new_allocate_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_new_allocate_q_MASK) >> VGT_DEBUG_REG21_new_allocate_q_SHIFT) +#define VGT_DEBUG_REG21_GET_num_new_unique_rel_indx(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK) >> VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT) +#define VGT_DEBUG_REG21_GET_inserted_null_prim_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_inserted_null_prim_q_MASK) >> VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT) +#define VGT_DEBUG_REG21_GET_insert_null_prim(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_insert_null_prim_MASK) >> VGT_DEBUG_REG21_insert_null_prim_SHIFT) +#define VGT_DEBUG_REG21_GET_buffered_prim_eop_mux(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK) >> VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT) +#define VGT_DEBUG_REG21_GET_prim_buffer_empty_mux(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK) >> VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT) +#define VGT_DEBUG_REG21_GET_buffered_thread_size(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_buffered_thread_size_MASK) >> VGT_DEBUG_REG21_buffered_thread_size_SHIFT) +#define VGT_DEBUG_REG21_GET_out_trigger(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_out_trigger_MASK) >> VGT_DEBUG_REG21_out_trigger_SHIFT) + +#define VGT_DEBUG_REG21_SET_null_terminate_vtx_vector(vgt_debug_reg21_reg, null_terminate_vtx_vector) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK) | (null_terminate_vtx_vector << VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT) +#define VGT_DEBUG_REG21_SET_prim_end_of_vtx_vect_flags(vgt_debug_reg21_reg, prim_end_of_vtx_vect_flags) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK) | (prim_end_of_vtx_vect_flags << VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT) +#define VGT_DEBUG_REG21_SET_alloc_counter_q(vgt_debug_reg21_reg, alloc_counter_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_alloc_counter_q_MASK) | (alloc_counter_q << VGT_DEBUG_REG21_alloc_counter_q_SHIFT) +#define VGT_DEBUG_REG21_SET_curr_slot_in_vtx_vect_q(vgt_debug_reg21_reg, curr_slot_in_vtx_vect_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK) | (curr_slot_in_vtx_vect_q << VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT) +#define VGT_DEBUG_REG21_SET_int_vtx_counter_q(vgt_debug_reg21_reg, int_vtx_counter_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_int_vtx_counter_q_MASK) | (int_vtx_counter_q << VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT) +#define VGT_DEBUG_REG21_SET_curr_dealloc_distance_q(vgt_debug_reg21_reg, curr_dealloc_distance_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK) | (curr_dealloc_distance_q << VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT) +#define VGT_DEBUG_REG21_SET_new_packet_q(vgt_debug_reg21_reg, new_packet_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_new_packet_q_MASK) | (new_packet_q << VGT_DEBUG_REG21_new_packet_q_SHIFT) +#define VGT_DEBUG_REG21_SET_new_allocate_q(vgt_debug_reg21_reg, new_allocate_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_new_allocate_q_MASK) | (new_allocate_q << VGT_DEBUG_REG21_new_allocate_q_SHIFT) +#define VGT_DEBUG_REG21_SET_num_new_unique_rel_indx(vgt_debug_reg21_reg, num_new_unique_rel_indx) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK) | (num_new_unique_rel_indx << VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT) +#define VGT_DEBUG_REG21_SET_inserted_null_prim_q(vgt_debug_reg21_reg, inserted_null_prim_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_inserted_null_prim_q_MASK) | (inserted_null_prim_q << VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT) +#define VGT_DEBUG_REG21_SET_insert_null_prim(vgt_debug_reg21_reg, insert_null_prim) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_insert_null_prim_MASK) | (insert_null_prim << VGT_DEBUG_REG21_insert_null_prim_SHIFT) +#define VGT_DEBUG_REG21_SET_buffered_prim_eop_mux(vgt_debug_reg21_reg, buffered_prim_eop_mux) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK) | (buffered_prim_eop_mux << VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT) +#define VGT_DEBUG_REG21_SET_prim_buffer_empty_mux(vgt_debug_reg21_reg, prim_buffer_empty_mux) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK) | (prim_buffer_empty_mux << VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT) +#define VGT_DEBUG_REG21_SET_buffered_thread_size(vgt_debug_reg21_reg, buffered_thread_size) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_buffered_thread_size_MASK) | (buffered_thread_size << VGT_DEBUG_REG21_buffered_thread_size_SHIFT) +#define VGT_DEBUG_REG21_SET_out_trigger(vgt_debug_reg21_reg, out_trigger) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_out_trigger_MASK) | (out_trigger << VGT_DEBUG_REG21_out_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg21_t { + unsigned int null_terminate_vtx_vector : VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE; + unsigned int prim_end_of_vtx_vect_flags : VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE; + unsigned int alloc_counter_q : VGT_DEBUG_REG21_alloc_counter_q_SIZE; + unsigned int curr_slot_in_vtx_vect_q : VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE; + unsigned int int_vtx_counter_q : VGT_DEBUG_REG21_int_vtx_counter_q_SIZE; + unsigned int curr_dealloc_distance_q : VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE; + unsigned int new_packet_q : VGT_DEBUG_REG21_new_packet_q_SIZE; + unsigned int new_allocate_q : VGT_DEBUG_REG21_new_allocate_q_SIZE; + unsigned int num_new_unique_rel_indx : VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE; + unsigned int inserted_null_prim_q : VGT_DEBUG_REG21_inserted_null_prim_q_SIZE; + unsigned int insert_null_prim : VGT_DEBUG_REG21_insert_null_prim_SIZE; + unsigned int buffered_prim_eop_mux : VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE; + unsigned int prim_buffer_empty_mux : VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE; + unsigned int buffered_thread_size : VGT_DEBUG_REG21_buffered_thread_size_SIZE; + unsigned int : 4; + unsigned int out_trigger : VGT_DEBUG_REG21_out_trigger_SIZE; + } vgt_debug_reg21_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg21_t { + unsigned int out_trigger : VGT_DEBUG_REG21_out_trigger_SIZE; + unsigned int : 4; + unsigned int buffered_thread_size : VGT_DEBUG_REG21_buffered_thread_size_SIZE; + unsigned int prim_buffer_empty_mux : VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE; + unsigned int buffered_prim_eop_mux : VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE; + unsigned int insert_null_prim : VGT_DEBUG_REG21_insert_null_prim_SIZE; + unsigned int inserted_null_prim_q : VGT_DEBUG_REG21_inserted_null_prim_q_SIZE; + unsigned int num_new_unique_rel_indx : VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE; + unsigned int new_allocate_q : VGT_DEBUG_REG21_new_allocate_q_SIZE; + unsigned int new_packet_q : VGT_DEBUG_REG21_new_packet_q_SIZE; + unsigned int curr_dealloc_distance_q : VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE; + unsigned int int_vtx_counter_q : VGT_DEBUG_REG21_int_vtx_counter_q_SIZE; + unsigned int curr_slot_in_vtx_vect_q : VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE; + unsigned int alloc_counter_q : VGT_DEBUG_REG21_alloc_counter_q_SIZE; + unsigned int prim_end_of_vtx_vect_flags : VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE; + unsigned int null_terminate_vtx_vector : VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE; + } vgt_debug_reg21_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg21_t f; +} vgt_debug_reg21_u; + + +/* + * VGT_CRC_SQ_DATA struct + */ + +#define VGT_CRC_SQ_DATA_CRC_SIZE 32 + +#define VGT_CRC_SQ_DATA_CRC_SHIFT 0 + +#define VGT_CRC_SQ_DATA_CRC_MASK 0xffffffff + +#define VGT_CRC_SQ_DATA_MASK \ + (VGT_CRC_SQ_DATA_CRC_MASK) + +#define VGT_CRC_SQ_DATA(crc) \ + ((crc << VGT_CRC_SQ_DATA_CRC_SHIFT)) + +#define VGT_CRC_SQ_DATA_GET_CRC(vgt_crc_sq_data) \ + ((vgt_crc_sq_data & VGT_CRC_SQ_DATA_CRC_MASK) >> VGT_CRC_SQ_DATA_CRC_SHIFT) + +#define VGT_CRC_SQ_DATA_SET_CRC(vgt_crc_sq_data_reg, crc) \ + vgt_crc_sq_data_reg = (vgt_crc_sq_data_reg & ~VGT_CRC_SQ_DATA_CRC_MASK) | (crc << VGT_CRC_SQ_DATA_CRC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_crc_sq_data_t { + unsigned int crc : VGT_CRC_SQ_DATA_CRC_SIZE; + } vgt_crc_sq_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_crc_sq_data_t { + unsigned int crc : VGT_CRC_SQ_DATA_CRC_SIZE; + } vgt_crc_sq_data_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_crc_sq_data_t f; +} vgt_crc_sq_data_u; + + +/* + * VGT_CRC_SQ_CTRL struct + */ + +#define VGT_CRC_SQ_CTRL_CRC_SIZE 32 + +#define VGT_CRC_SQ_CTRL_CRC_SHIFT 0 + +#define VGT_CRC_SQ_CTRL_CRC_MASK 0xffffffff + +#define VGT_CRC_SQ_CTRL_MASK \ + (VGT_CRC_SQ_CTRL_CRC_MASK) + +#define VGT_CRC_SQ_CTRL(crc) \ + ((crc << VGT_CRC_SQ_CTRL_CRC_SHIFT)) + +#define VGT_CRC_SQ_CTRL_GET_CRC(vgt_crc_sq_ctrl) \ + ((vgt_crc_sq_ctrl & VGT_CRC_SQ_CTRL_CRC_MASK) >> VGT_CRC_SQ_CTRL_CRC_SHIFT) + +#define VGT_CRC_SQ_CTRL_SET_CRC(vgt_crc_sq_ctrl_reg, crc) \ + vgt_crc_sq_ctrl_reg = (vgt_crc_sq_ctrl_reg & ~VGT_CRC_SQ_CTRL_CRC_MASK) | (crc << VGT_CRC_SQ_CTRL_CRC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_crc_sq_ctrl_t { + unsigned int crc : VGT_CRC_SQ_CTRL_CRC_SIZE; + } vgt_crc_sq_ctrl_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_crc_sq_ctrl_t { + unsigned int crc : VGT_CRC_SQ_CTRL_CRC_SIZE; + } vgt_crc_sq_ctrl_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_crc_sq_ctrl_t f; +} vgt_crc_sq_ctrl_u; + + +/* + * VGT_PERFCOUNTER0_SELECT struct + */ + +#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define VGT_PERFCOUNTER0_SELECT_MASK \ + (VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define VGT_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define VGT_PERFCOUNTER0_SELECT_GET_PERF_SEL(vgt_perfcounter0_select) \ + ((vgt_perfcounter0_select & VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define VGT_PERFCOUNTER0_SELECT_SET_PERF_SEL(vgt_perfcounter0_select_reg, perf_sel) \ + vgt_perfcounter0_select_reg = (vgt_perfcounter0_select_reg & ~VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_select_t { + unsigned int perf_sel : VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } vgt_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } vgt_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter0_select_t f; +} vgt_perfcounter0_select_u; + + +/* + * VGT_PERFCOUNTER1_SELECT struct + */ + +#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8 + +#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0 + +#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff + +#define VGT_PERFCOUNTER1_SELECT_MASK \ + (VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) + +#define VGT_PERFCOUNTER1_SELECT(perf_sel) \ + ((perf_sel << VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)) + +#define VGT_PERFCOUNTER1_SELECT_GET_PERF_SEL(vgt_perfcounter1_select) \ + ((vgt_perfcounter1_select & VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#define VGT_PERFCOUNTER1_SELECT_SET_PERF_SEL(vgt_perfcounter1_select_reg, perf_sel) \ + vgt_perfcounter1_select_reg = (vgt_perfcounter1_select_reg & ~VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_select_t { + unsigned int perf_sel : VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } vgt_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_select_t { + unsigned int : 24; + unsigned int perf_sel : VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + } vgt_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter1_select_t f; +} vgt_perfcounter1_select_u; + + +/* + * VGT_PERFCOUNTER2_SELECT struct + */ + +#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8 + +#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0 + +#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff + +#define VGT_PERFCOUNTER2_SELECT_MASK \ + (VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) + +#define VGT_PERFCOUNTER2_SELECT(perf_sel) \ + ((perf_sel << VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)) + +#define VGT_PERFCOUNTER2_SELECT_GET_PERF_SEL(vgt_perfcounter2_select) \ + ((vgt_perfcounter2_select & VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#define VGT_PERFCOUNTER2_SELECT_SET_PERF_SEL(vgt_perfcounter2_select_reg, perf_sel) \ + vgt_perfcounter2_select_reg = (vgt_perfcounter2_select_reg & ~VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_select_t { + unsigned int perf_sel : VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } vgt_perfcounter2_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_select_t { + unsigned int : 24; + unsigned int perf_sel : VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + } vgt_perfcounter2_select_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter2_select_t f; +} vgt_perfcounter2_select_u; + + +/* + * VGT_PERFCOUNTER3_SELECT struct + */ + +#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8 + +#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0 + +#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff + +#define VGT_PERFCOUNTER3_SELECT_MASK \ + (VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) + +#define VGT_PERFCOUNTER3_SELECT(perf_sel) \ + ((perf_sel << VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)) + +#define VGT_PERFCOUNTER3_SELECT_GET_PERF_SEL(vgt_perfcounter3_select) \ + ((vgt_perfcounter3_select & VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#define VGT_PERFCOUNTER3_SELECT_SET_PERF_SEL(vgt_perfcounter3_select_reg, perf_sel) \ + vgt_perfcounter3_select_reg = (vgt_perfcounter3_select_reg & ~VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_select_t { + unsigned int perf_sel : VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } vgt_perfcounter3_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_select_t { + unsigned int : 24; + unsigned int perf_sel : VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + } vgt_perfcounter3_select_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter3_select_t f; +} vgt_perfcounter3_select_u; + + +/* + * VGT_PERFCOUNTER0_LOW struct + */ + +#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define VGT_PERFCOUNTER0_LOW_MASK \ + (VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER0_LOW_GET_PERF_COUNT(vgt_perfcounter0_low) \ + ((vgt_perfcounter0_low & VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER0_LOW_SET_PERF_COUNT(vgt_perfcounter0_low_reg, perf_count) \ + vgt_perfcounter0_low_reg = (vgt_perfcounter0_low_reg & ~VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_low_t { + unsigned int perf_count : VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_low_t { + unsigned int perf_count : VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter0_low_t f; +} vgt_perfcounter0_low_u; + + +/* + * VGT_PERFCOUNTER1_LOW struct + */ + +#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32 + +#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff + +#define VGT_PERFCOUNTER1_LOW_MASK \ + (VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER1_LOW(perf_count) \ + ((perf_count << VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER1_LOW_GET_PERF_COUNT(vgt_perfcounter1_low) \ + ((vgt_perfcounter1_low & VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER1_LOW_SET_PERF_COUNT(vgt_perfcounter1_low_reg, perf_count) \ + vgt_perfcounter1_low_reg = (vgt_perfcounter1_low_reg & ~VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_low_t { + unsigned int perf_count : VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_low_t { + unsigned int perf_count : VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter1_low_t f; +} vgt_perfcounter1_low_u; + + +/* + * VGT_PERFCOUNTER2_LOW struct + */ + +#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32 + +#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff + +#define VGT_PERFCOUNTER2_LOW_MASK \ + (VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER2_LOW(perf_count) \ + ((perf_count << VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER2_LOW_GET_PERF_COUNT(vgt_perfcounter2_low) \ + ((vgt_perfcounter2_low & VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER2_LOW_SET_PERF_COUNT(vgt_perfcounter2_low_reg, perf_count) \ + vgt_perfcounter2_low_reg = (vgt_perfcounter2_low_reg & ~VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_low_t { + unsigned int perf_count : VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter2_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_low_t { + unsigned int perf_count : VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter2_low_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter2_low_t f; +} vgt_perfcounter2_low_u; + + +/* + * VGT_PERFCOUNTER3_LOW struct + */ + +#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32 + +#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff + +#define VGT_PERFCOUNTER3_LOW_MASK \ + (VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER3_LOW(perf_count) \ + ((perf_count << VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER3_LOW_GET_PERF_COUNT(vgt_perfcounter3_low) \ + ((vgt_perfcounter3_low & VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER3_LOW_SET_PERF_COUNT(vgt_perfcounter3_low_reg, perf_count) \ + vgt_perfcounter3_low_reg = (vgt_perfcounter3_low_reg & ~VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_low_t { + unsigned int perf_count : VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter3_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_low_t { + unsigned int perf_count : VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter3_low_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter3_low_t f; +} vgt_perfcounter3_low_u; + + +/* + * VGT_PERFCOUNTER0_HI struct + */ + +#define VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define VGT_PERFCOUNTER0_HI_MASK \ + (VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER0_HI_GET_PERF_COUNT(vgt_perfcounter0_hi) \ + ((vgt_perfcounter0_hi & VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER0_HI_SET_PERF_COUNT(vgt_perfcounter0_hi_reg, perf_count) \ + vgt_perfcounter0_hi_reg = (vgt_perfcounter0_hi_reg & ~VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_hi_t { + unsigned int perf_count : VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } vgt_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } vgt_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter0_hi_t f; +} vgt_perfcounter0_hi_u; + + +/* + * VGT_PERFCOUNTER1_HI struct + */ + +#define VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16 + +#define VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff + +#define VGT_PERFCOUNTER1_HI_MASK \ + (VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER1_HI(perf_count) \ + ((perf_count << VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER1_HI_GET_PERF_COUNT(vgt_perfcounter1_hi) \ + ((vgt_perfcounter1_hi & VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER1_HI_SET_PERF_COUNT(vgt_perfcounter1_hi_reg, perf_count) \ + vgt_perfcounter1_hi_reg = (vgt_perfcounter1_hi_reg & ~VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_hi_t { + unsigned int perf_count : VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } vgt_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_count : VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + } vgt_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter1_hi_t f; +} vgt_perfcounter1_hi_u; + + +/* + * VGT_PERFCOUNTER2_HI struct + */ + +#define VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16 + +#define VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff + +#define VGT_PERFCOUNTER2_HI_MASK \ + (VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER2_HI(perf_count) \ + ((perf_count << VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER2_HI_GET_PERF_COUNT(vgt_perfcounter2_hi) \ + ((vgt_perfcounter2_hi & VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER2_HI_SET_PERF_COUNT(vgt_perfcounter2_hi_reg, perf_count) \ + vgt_perfcounter2_hi_reg = (vgt_perfcounter2_hi_reg & ~VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_hi_t { + unsigned int perf_count : VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } vgt_perfcounter2_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_hi_t { + unsigned int : 16; + unsigned int perf_count : VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + } vgt_perfcounter2_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter2_hi_t f; +} vgt_perfcounter2_hi_u; + + +/* + * VGT_PERFCOUNTER3_HI struct + */ + +#define VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16 + +#define VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff + +#define VGT_PERFCOUNTER3_HI_MASK \ + (VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER3_HI(perf_count) \ + ((perf_count << VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER3_HI_GET_PERF_COUNT(vgt_perfcounter3_hi) \ + ((vgt_perfcounter3_hi & VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER3_HI_SET_PERF_COUNT(vgt_perfcounter3_hi_reg, perf_count) \ + vgt_perfcounter3_hi_reg = (vgt_perfcounter3_hi_reg & ~VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_hi_t { + unsigned int perf_count : VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } vgt_perfcounter3_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_hi_t { + unsigned int : 16; + unsigned int perf_count : VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + } vgt_perfcounter3_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter3_hi_t f; +} vgt_perfcounter3_hi_u; + + +#endif + + +#if !defined (_SQ_FIDDLE_H) +#define _SQ_FIDDLE_H + +/***************************************************************************************************************** + * + * sq_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * SQ_GPR_MANAGEMENT struct + */ + +#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE 1 +#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE 7 +#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE 7 + +#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT 0 +#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT 4 +#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT 12 + +#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK 0x00000001 +#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK 0x000007f0 +#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK 0x0007f000 + +#define SQ_GPR_MANAGEMENT_MASK \ + (SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK | \ + SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK | \ + SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) + +#define SQ_GPR_MANAGEMENT(reg_dynamic, reg_size_pix, reg_size_vtx) \ + ((reg_dynamic << SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT) | \ + (reg_size_pix << SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT) | \ + (reg_size_vtx << SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT)) + +#define SQ_GPR_MANAGEMENT_GET_REG_DYNAMIC(sq_gpr_management) \ + ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK) >> SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT) +#define SQ_GPR_MANAGEMENT_GET_REG_SIZE_PIX(sq_gpr_management) \ + ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK) >> SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT) +#define SQ_GPR_MANAGEMENT_GET_REG_SIZE_VTX(sq_gpr_management) \ + ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) >> SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT) + +#define SQ_GPR_MANAGEMENT_SET_REG_DYNAMIC(sq_gpr_management_reg, reg_dynamic) \ + sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK) | (reg_dynamic << SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT) +#define SQ_GPR_MANAGEMENT_SET_REG_SIZE_PIX(sq_gpr_management_reg, reg_size_pix) \ + sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK) | (reg_size_pix << SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT) +#define SQ_GPR_MANAGEMENT_SET_REG_SIZE_VTX(sq_gpr_management_reg, reg_size_vtx) \ + sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) | (reg_size_vtx << SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_gpr_management_t { + unsigned int reg_dynamic : SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE; + unsigned int : 3; + unsigned int reg_size_pix : SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE; + unsigned int : 1; + unsigned int reg_size_vtx : SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE; + unsigned int : 13; + } sq_gpr_management_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_gpr_management_t { + unsigned int : 13; + unsigned int reg_size_vtx : SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE; + unsigned int : 1; + unsigned int reg_size_pix : SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE; + unsigned int : 3; + unsigned int reg_dynamic : SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE; + } sq_gpr_management_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_gpr_management_t f; +} sq_gpr_management_u; + + +/* + * SQ_FLOW_CONTROL struct + */ + +#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE 2 +#define SQ_FLOW_CONTROL_ONE_THREAD_SIZE 1 +#define SQ_FLOW_CONTROL_ONE_ALU_SIZE 1 +#define SQ_FLOW_CONTROL_CF_WR_BASE_SIZE 4 +#define SQ_FLOW_CONTROL_NO_PV_PS_SIZE 1 +#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE 1 +#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE 1 +#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE 2 +#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE 1 +#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE 1 +#define SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE 1 +#define SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE 1 +#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE 1 +#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE 1 +#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE 1 + +#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT 0 +#define SQ_FLOW_CONTROL_ONE_THREAD_SHIFT 4 +#define SQ_FLOW_CONTROL_ONE_ALU_SHIFT 8 +#define SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT 12 +#define SQ_FLOW_CONTROL_NO_PV_PS_SHIFT 16 +#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT 17 +#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT 18 +#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT 19 +#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT 21 +#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT 22 +#define SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT 23 +#define SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT 24 +#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT 25 +#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT 26 +#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT 27 + +#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK 0x00000003 +#define SQ_FLOW_CONTROL_ONE_THREAD_MASK 0x00000010 +#define SQ_FLOW_CONTROL_ONE_ALU_MASK 0x00000100 +#define SQ_FLOW_CONTROL_CF_WR_BASE_MASK 0x0000f000 +#define SQ_FLOW_CONTROL_NO_PV_PS_MASK 0x00010000 +#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK 0x00020000 +#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK 0x00040000 +#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK 0x00180000 +#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK 0x00200000 +#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK 0x00400000 +#define SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK 0x00800000 +#define SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK 0x01000000 +#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK 0x02000000 +#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK 0x04000000 +#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK 0x08000000 + +#define SQ_FLOW_CONTROL_MASK \ + (SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK | \ + SQ_FLOW_CONTROL_ONE_THREAD_MASK | \ + SQ_FLOW_CONTROL_ONE_ALU_MASK | \ + SQ_FLOW_CONTROL_CF_WR_BASE_MASK | \ + SQ_FLOW_CONTROL_NO_PV_PS_MASK | \ + SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK | \ + SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK | \ + SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK | \ + SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK | \ + SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK | \ + SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK | \ + SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK | \ + SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK | \ + SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK | \ + SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) + +#define SQ_FLOW_CONTROL(input_arbitration_policy, one_thread, one_alu, cf_wr_base, no_pv_ps, no_loop_exit, no_cexec_optimize, texture_arbitration_policy, vc_arbitration_policy, alu_arbitration_policy, no_arb_eject, no_cfs_eject, pos_exp_priority, no_early_thread_termination, ps_prefetch_color_alloc) \ + ((input_arbitration_policy << SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT) | \ + (one_thread << SQ_FLOW_CONTROL_ONE_THREAD_SHIFT) | \ + (one_alu << SQ_FLOW_CONTROL_ONE_ALU_SHIFT) | \ + (cf_wr_base << SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT) | \ + (no_pv_ps << SQ_FLOW_CONTROL_NO_PV_PS_SHIFT) | \ + (no_loop_exit << SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT) | \ + (no_cexec_optimize << SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT) | \ + (texture_arbitration_policy << SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT) | \ + (vc_arbitration_policy << SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT) | \ + (alu_arbitration_policy << SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT) | \ + (no_arb_eject << SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT) | \ + (no_cfs_eject << SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT) | \ + (pos_exp_priority << SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT) | \ + (no_early_thread_termination << SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT) | \ + (ps_prefetch_color_alloc << SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT)) + +#define SQ_FLOW_CONTROL_GET_INPUT_ARBITRATION_POLICY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_GET_ONE_THREAD(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_ONE_THREAD_MASK) >> SQ_FLOW_CONTROL_ONE_THREAD_SHIFT) +#define SQ_FLOW_CONTROL_GET_ONE_ALU(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_ONE_ALU_MASK) >> SQ_FLOW_CONTROL_ONE_ALU_SHIFT) +#define SQ_FLOW_CONTROL_GET_CF_WR_BASE(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_CF_WR_BASE_MASK) >> SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_PV_PS(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_PV_PS_MASK) >> SQ_FLOW_CONTROL_NO_PV_PS_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_LOOP_EXIT(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK) >> SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_CEXEC_OPTIMIZE(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK) >> SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT) +#define SQ_FLOW_CONTROL_GET_TEXTURE_ARBITRATION_POLICY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_GET_VC_ARBITRATION_POLICY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_GET_ALU_ARBITRATION_POLICY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_ARB_EJECT(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK) >> SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_CFS_EJECT(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK) >> SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT) +#define SQ_FLOW_CONTROL_GET_POS_EXP_PRIORITY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK) >> SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_EARLY_THREAD_TERMINATION(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK) >> SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT) +#define SQ_FLOW_CONTROL_GET_PS_PREFETCH_COLOR_ALLOC(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) >> SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT) + +#define SQ_FLOW_CONTROL_SET_INPUT_ARBITRATION_POLICY(sq_flow_control_reg, input_arbitration_policy) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK) | (input_arbitration_policy << SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_SET_ONE_THREAD(sq_flow_control_reg, one_thread) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ONE_THREAD_MASK) | (one_thread << SQ_FLOW_CONTROL_ONE_THREAD_SHIFT) +#define SQ_FLOW_CONTROL_SET_ONE_ALU(sq_flow_control_reg, one_alu) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ONE_ALU_MASK) | (one_alu << SQ_FLOW_CONTROL_ONE_ALU_SHIFT) +#define SQ_FLOW_CONTROL_SET_CF_WR_BASE(sq_flow_control_reg, cf_wr_base) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_CF_WR_BASE_MASK) | (cf_wr_base << SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_PV_PS(sq_flow_control_reg, no_pv_ps) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_PV_PS_MASK) | (no_pv_ps << SQ_FLOW_CONTROL_NO_PV_PS_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_LOOP_EXIT(sq_flow_control_reg, no_loop_exit) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK) | (no_loop_exit << SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_CEXEC_OPTIMIZE(sq_flow_control_reg, no_cexec_optimize) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK) | (no_cexec_optimize << SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT) +#define SQ_FLOW_CONTROL_SET_TEXTURE_ARBITRATION_POLICY(sq_flow_control_reg, texture_arbitration_policy) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK) | (texture_arbitration_policy << SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_SET_VC_ARBITRATION_POLICY(sq_flow_control_reg, vc_arbitration_policy) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK) | (vc_arbitration_policy << SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_SET_ALU_ARBITRATION_POLICY(sq_flow_control_reg, alu_arbitration_policy) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK) | (alu_arbitration_policy << SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_ARB_EJECT(sq_flow_control_reg, no_arb_eject) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK) | (no_arb_eject << SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_CFS_EJECT(sq_flow_control_reg, no_cfs_eject) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK) | (no_cfs_eject << SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT) +#define SQ_FLOW_CONTROL_SET_POS_EXP_PRIORITY(sq_flow_control_reg, pos_exp_priority) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK) | (pos_exp_priority << SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_EARLY_THREAD_TERMINATION(sq_flow_control_reg, no_early_thread_termination) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK) | (no_early_thread_termination << SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT) +#define SQ_FLOW_CONTROL_SET_PS_PREFETCH_COLOR_ALLOC(sq_flow_control_reg, ps_prefetch_color_alloc) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) | (ps_prefetch_color_alloc << SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_flow_control_t { + unsigned int input_arbitration_policy : SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE; + unsigned int : 2; + unsigned int one_thread : SQ_FLOW_CONTROL_ONE_THREAD_SIZE; + unsigned int : 3; + unsigned int one_alu : SQ_FLOW_CONTROL_ONE_ALU_SIZE; + unsigned int : 3; + unsigned int cf_wr_base : SQ_FLOW_CONTROL_CF_WR_BASE_SIZE; + unsigned int no_pv_ps : SQ_FLOW_CONTROL_NO_PV_PS_SIZE; + unsigned int no_loop_exit : SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE; + unsigned int no_cexec_optimize : SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE; + unsigned int texture_arbitration_policy : SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE; + unsigned int vc_arbitration_policy : SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE; + unsigned int alu_arbitration_policy : SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE; + unsigned int no_arb_eject : SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE; + unsigned int no_cfs_eject : SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE; + unsigned int pos_exp_priority : SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE; + unsigned int no_early_thread_termination : SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE; + unsigned int ps_prefetch_color_alloc : SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE; + unsigned int : 4; + } sq_flow_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_flow_control_t { + unsigned int : 4; + unsigned int ps_prefetch_color_alloc : SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE; + unsigned int no_early_thread_termination : SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE; + unsigned int pos_exp_priority : SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE; + unsigned int no_cfs_eject : SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE; + unsigned int no_arb_eject : SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE; + unsigned int alu_arbitration_policy : SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE; + unsigned int vc_arbitration_policy : SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE; + unsigned int texture_arbitration_policy : SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE; + unsigned int no_cexec_optimize : SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE; + unsigned int no_loop_exit : SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE; + unsigned int no_pv_ps : SQ_FLOW_CONTROL_NO_PV_PS_SIZE; + unsigned int cf_wr_base : SQ_FLOW_CONTROL_CF_WR_BASE_SIZE; + unsigned int : 3; + unsigned int one_alu : SQ_FLOW_CONTROL_ONE_ALU_SIZE; + unsigned int : 3; + unsigned int one_thread : SQ_FLOW_CONTROL_ONE_THREAD_SIZE; + unsigned int : 2; + unsigned int input_arbitration_policy : SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE; + } sq_flow_control_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_flow_control_t f; +} sq_flow_control_u; + + +/* + * SQ_INST_STORE_MANAGMENT struct + */ + +#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE 12 +#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE 12 + +#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT 0 +#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT 16 + +#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK 0x00000fff +#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK 0x0fff0000 + +#define SQ_INST_STORE_MANAGMENT_MASK \ + (SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK | \ + SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) + +#define SQ_INST_STORE_MANAGMENT(inst_base_pix, inst_base_vtx) \ + ((inst_base_pix << SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT) | \ + (inst_base_vtx << SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT)) + +#define SQ_INST_STORE_MANAGMENT_GET_INST_BASE_PIX(sq_inst_store_managment) \ + ((sq_inst_store_managment & SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK) >> SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT) +#define SQ_INST_STORE_MANAGMENT_GET_INST_BASE_VTX(sq_inst_store_managment) \ + ((sq_inst_store_managment & SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) >> SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT) + +#define SQ_INST_STORE_MANAGMENT_SET_INST_BASE_PIX(sq_inst_store_managment_reg, inst_base_pix) \ + sq_inst_store_managment_reg = (sq_inst_store_managment_reg & ~SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK) | (inst_base_pix << SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT) +#define SQ_INST_STORE_MANAGMENT_SET_INST_BASE_VTX(sq_inst_store_managment_reg, inst_base_vtx) \ + sq_inst_store_managment_reg = (sq_inst_store_managment_reg & ~SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) | (inst_base_vtx << SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_inst_store_managment_t { + unsigned int inst_base_pix : SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE; + unsigned int : 4; + unsigned int inst_base_vtx : SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE; + unsigned int : 4; + } sq_inst_store_managment_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_inst_store_managment_t { + unsigned int : 4; + unsigned int inst_base_vtx : SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE; + unsigned int : 4; + unsigned int inst_base_pix : SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE; + } sq_inst_store_managment_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_inst_store_managment_t f; +} sq_inst_store_managment_u; + + +/* + * SQ_RESOURCE_MANAGMENT struct + */ + +#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE 8 +#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE 8 +#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE 9 + +#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT 0 +#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT 8 +#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT 16 + +#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK 0x000000ff +#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK 0x0000ff00 +#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK 0x01ff0000 + +#define SQ_RESOURCE_MANAGMENT_MASK \ + (SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK | \ + SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK | \ + SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) + +#define SQ_RESOURCE_MANAGMENT(vtx_thread_buf_entries, pix_thread_buf_entries, export_buf_entries) \ + ((vtx_thread_buf_entries << SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT) | \ + (pix_thread_buf_entries << SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT) | \ + (export_buf_entries << SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT)) + +#define SQ_RESOURCE_MANAGMENT_GET_VTX_THREAD_BUF_ENTRIES(sq_resource_managment) \ + ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT) +#define SQ_RESOURCE_MANAGMENT_GET_PIX_THREAD_BUF_ENTRIES(sq_resource_managment) \ + ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT) +#define SQ_RESOURCE_MANAGMENT_GET_EXPORT_BUF_ENTRIES(sq_resource_managment) \ + ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT) + +#define SQ_RESOURCE_MANAGMENT_SET_VTX_THREAD_BUF_ENTRIES(sq_resource_managment_reg, vtx_thread_buf_entries) \ + sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK) | (vtx_thread_buf_entries << SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT) +#define SQ_RESOURCE_MANAGMENT_SET_PIX_THREAD_BUF_ENTRIES(sq_resource_managment_reg, pix_thread_buf_entries) \ + sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK) | (pix_thread_buf_entries << SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT) +#define SQ_RESOURCE_MANAGMENT_SET_EXPORT_BUF_ENTRIES(sq_resource_managment_reg, export_buf_entries) \ + sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) | (export_buf_entries << SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_resource_managment_t { + unsigned int vtx_thread_buf_entries : SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE; + unsigned int pix_thread_buf_entries : SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE; + unsigned int export_buf_entries : SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE; + unsigned int : 7; + } sq_resource_managment_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_resource_managment_t { + unsigned int : 7; + unsigned int export_buf_entries : SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE; + unsigned int pix_thread_buf_entries : SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE; + unsigned int vtx_thread_buf_entries : SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE; + } sq_resource_managment_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_resource_managment_t f; +} sq_resource_managment_u; + + +/* + * SQ_EO_RT struct + */ + +#define SQ_EO_RT_EO_CONSTANTS_RT_SIZE 8 +#define SQ_EO_RT_EO_TSTATE_RT_SIZE 8 + +#define SQ_EO_RT_EO_CONSTANTS_RT_SHIFT 0 +#define SQ_EO_RT_EO_TSTATE_RT_SHIFT 16 + +#define SQ_EO_RT_EO_CONSTANTS_RT_MASK 0x000000ff +#define SQ_EO_RT_EO_TSTATE_RT_MASK 0x00ff0000 + +#define SQ_EO_RT_MASK \ + (SQ_EO_RT_EO_CONSTANTS_RT_MASK | \ + SQ_EO_RT_EO_TSTATE_RT_MASK) + +#define SQ_EO_RT(eo_constants_rt, eo_tstate_rt) \ + ((eo_constants_rt << SQ_EO_RT_EO_CONSTANTS_RT_SHIFT) | \ + (eo_tstate_rt << SQ_EO_RT_EO_TSTATE_RT_SHIFT)) + +#define SQ_EO_RT_GET_EO_CONSTANTS_RT(sq_eo_rt) \ + ((sq_eo_rt & SQ_EO_RT_EO_CONSTANTS_RT_MASK) >> SQ_EO_RT_EO_CONSTANTS_RT_SHIFT) +#define SQ_EO_RT_GET_EO_TSTATE_RT(sq_eo_rt) \ + ((sq_eo_rt & SQ_EO_RT_EO_TSTATE_RT_MASK) >> SQ_EO_RT_EO_TSTATE_RT_SHIFT) + +#define SQ_EO_RT_SET_EO_CONSTANTS_RT(sq_eo_rt_reg, eo_constants_rt) \ + sq_eo_rt_reg = (sq_eo_rt_reg & ~SQ_EO_RT_EO_CONSTANTS_RT_MASK) | (eo_constants_rt << SQ_EO_RT_EO_CONSTANTS_RT_SHIFT) +#define SQ_EO_RT_SET_EO_TSTATE_RT(sq_eo_rt_reg, eo_tstate_rt) \ + sq_eo_rt_reg = (sq_eo_rt_reg & ~SQ_EO_RT_EO_TSTATE_RT_MASK) | (eo_tstate_rt << SQ_EO_RT_EO_TSTATE_RT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_eo_rt_t { + unsigned int eo_constants_rt : SQ_EO_RT_EO_CONSTANTS_RT_SIZE; + unsigned int : 8; + unsigned int eo_tstate_rt : SQ_EO_RT_EO_TSTATE_RT_SIZE; + unsigned int : 8; + } sq_eo_rt_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_eo_rt_t { + unsigned int : 8; + unsigned int eo_tstate_rt : SQ_EO_RT_EO_TSTATE_RT_SIZE; + unsigned int : 8; + unsigned int eo_constants_rt : SQ_EO_RT_EO_CONSTANTS_RT_SIZE; + } sq_eo_rt_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_eo_rt_t f; +} sq_eo_rt_u; + + +/* + * SQ_DEBUG_MISC struct + */ + +#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE 11 +#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE 8 +#define SQ_DEBUG_MISC_DB_READ_CTX_SIZE 1 +#define SQ_DEBUG_MISC_RESERVED_SIZE 2 +#define SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE 2 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE 1 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE 1 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE 1 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE 1 + +#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT 0 +#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT 12 +#define SQ_DEBUG_MISC_DB_READ_CTX_SHIFT 20 +#define SQ_DEBUG_MISC_RESERVED_SHIFT 21 +#define SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT 23 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT 25 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT 26 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT 27 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT 28 + +#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK 0x000007ff +#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK 0x000ff000 +#define SQ_DEBUG_MISC_DB_READ_CTX_MASK 0x00100000 +#define SQ_DEBUG_MISC_RESERVED_MASK 0x00600000 +#define SQ_DEBUG_MISC_DB_READ_MEMORY_MASK 0x01800000 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK 0x02000000 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK 0x04000000 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK 0x08000000 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK 0x10000000 + +#define SQ_DEBUG_MISC_MASK \ + (SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK | \ + SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK | \ + SQ_DEBUG_MISC_DB_READ_CTX_MASK | \ + SQ_DEBUG_MISC_RESERVED_MASK | \ + SQ_DEBUG_MISC_DB_READ_MEMORY_MASK | \ + SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK | \ + SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK | \ + SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK | \ + SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) + +#define SQ_DEBUG_MISC(db_alucst_size, db_tstate_size, db_read_ctx, reserved, db_read_memory, db_wen_memory_0, db_wen_memory_1, db_wen_memory_2, db_wen_memory_3) \ + ((db_alucst_size << SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT) | \ + (db_tstate_size << SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT) | \ + (db_read_ctx << SQ_DEBUG_MISC_DB_READ_CTX_SHIFT) | \ + (reserved << SQ_DEBUG_MISC_RESERVED_SHIFT) | \ + (db_read_memory << SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT) | \ + (db_wen_memory_0 << SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT) | \ + (db_wen_memory_1 << SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT) | \ + (db_wen_memory_2 << SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT) | \ + (db_wen_memory_3 << SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT)) + +#define SQ_DEBUG_MISC_GET_DB_ALUCST_SIZE(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK) >> SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_TSTATE_SIZE(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK) >> SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_READ_CTX(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_READ_CTX_MASK) >> SQ_DEBUG_MISC_DB_READ_CTX_SHIFT) +#define SQ_DEBUG_MISC_GET_RESERVED(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_RESERVED_MASK) >> SQ_DEBUG_MISC_RESERVED_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_READ_MEMORY(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_READ_MEMORY_MASK) >> SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_0(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_1(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_2(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_3(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT) + +#define SQ_DEBUG_MISC_SET_DB_ALUCST_SIZE(sq_debug_misc_reg, db_alucst_size) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK) | (db_alucst_size << SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_TSTATE_SIZE(sq_debug_misc_reg, db_tstate_size) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK) | (db_tstate_size << SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_READ_CTX(sq_debug_misc_reg, db_read_ctx) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_READ_CTX_MASK) | (db_read_ctx << SQ_DEBUG_MISC_DB_READ_CTX_SHIFT) +#define SQ_DEBUG_MISC_SET_RESERVED(sq_debug_misc_reg, reserved) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_RESERVED_MASK) | (reserved << SQ_DEBUG_MISC_RESERVED_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_READ_MEMORY(sq_debug_misc_reg, db_read_memory) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_READ_MEMORY_MASK) | (db_read_memory << SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_0(sq_debug_misc_reg, db_wen_memory_0) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK) | (db_wen_memory_0 << SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_1(sq_debug_misc_reg, db_wen_memory_1) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK) | (db_wen_memory_1 << SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_2(sq_debug_misc_reg, db_wen_memory_2) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK) | (db_wen_memory_2 << SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_3(sq_debug_misc_reg, db_wen_memory_3) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) | (db_wen_memory_3 << SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_misc_t { + unsigned int db_alucst_size : SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE; + unsigned int : 1; + unsigned int db_tstate_size : SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE; + unsigned int db_read_ctx : SQ_DEBUG_MISC_DB_READ_CTX_SIZE; + unsigned int reserved : SQ_DEBUG_MISC_RESERVED_SIZE; + unsigned int db_read_memory : SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE; + unsigned int db_wen_memory_0 : SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE; + unsigned int db_wen_memory_1 : SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE; + unsigned int db_wen_memory_2 : SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE; + unsigned int db_wen_memory_3 : SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE; + unsigned int : 3; + } sq_debug_misc_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_misc_t { + unsigned int : 3; + unsigned int db_wen_memory_3 : SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE; + unsigned int db_wen_memory_2 : SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE; + unsigned int db_wen_memory_1 : SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE; + unsigned int db_wen_memory_0 : SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE; + unsigned int db_read_memory : SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE; + unsigned int reserved : SQ_DEBUG_MISC_RESERVED_SIZE; + unsigned int db_read_ctx : SQ_DEBUG_MISC_DB_READ_CTX_SIZE; + unsigned int db_tstate_size : SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE; + unsigned int : 1; + unsigned int db_alucst_size : SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE; + } sq_debug_misc_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_misc_t f; +} sq_debug_misc_u; + + +/* + * SQ_ACTIVITY_METER_CNTL struct + */ + +#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE 8 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE 8 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE 8 +#define SQ_ACTIVITY_METER_CNTL_SPARE_SIZE 8 + +#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT 0 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT 8 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT 16 +#define SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT 24 + +#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK 0x000000ff +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK 0x0000ff00 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK 0x00ff0000 +#define SQ_ACTIVITY_METER_CNTL_SPARE_MASK 0xff000000 + +#define SQ_ACTIVITY_METER_CNTL_MASK \ + (SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK | \ + SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK | \ + SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK | \ + SQ_ACTIVITY_METER_CNTL_SPARE_MASK) + +#define SQ_ACTIVITY_METER_CNTL(timebase, threshold_low, threshold_high, spare) \ + ((timebase << SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT) | \ + (threshold_low << SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT) | \ + (threshold_high << SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT) | \ + (spare << SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT)) + +#define SQ_ACTIVITY_METER_CNTL_GET_TIMEBASE(sq_activity_meter_cntl) \ + ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK) >> SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_GET_THRESHOLD_LOW(sq_activity_meter_cntl) \ + ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK) >> SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_GET_THRESHOLD_HIGH(sq_activity_meter_cntl) \ + ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK) >> SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_GET_SPARE(sq_activity_meter_cntl) \ + ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_SPARE_MASK) >> SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT) + +#define SQ_ACTIVITY_METER_CNTL_SET_TIMEBASE(sq_activity_meter_cntl_reg, timebase) \ + sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK) | (timebase << SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_SET_THRESHOLD_LOW(sq_activity_meter_cntl_reg, threshold_low) \ + sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK) | (threshold_low << SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_SET_THRESHOLD_HIGH(sq_activity_meter_cntl_reg, threshold_high) \ + sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK) | (threshold_high << SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_SET_SPARE(sq_activity_meter_cntl_reg, spare) \ + sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_SPARE_MASK) | (spare << SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_activity_meter_cntl_t { + unsigned int timebase : SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE; + unsigned int threshold_low : SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE; + unsigned int threshold_high : SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE; + unsigned int spare : SQ_ACTIVITY_METER_CNTL_SPARE_SIZE; + } sq_activity_meter_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_activity_meter_cntl_t { + unsigned int spare : SQ_ACTIVITY_METER_CNTL_SPARE_SIZE; + unsigned int threshold_high : SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE; + unsigned int threshold_low : SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE; + unsigned int timebase : SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE; + } sq_activity_meter_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_activity_meter_cntl_t f; +} sq_activity_meter_cntl_u; + + +/* + * SQ_ACTIVITY_METER_STATUS struct + */ + +#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE 8 + +#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT 0 + +#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK 0x000000ff + +#define SQ_ACTIVITY_METER_STATUS_MASK \ + (SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) + +#define SQ_ACTIVITY_METER_STATUS(percent_busy) \ + ((percent_busy << SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT)) + +#define SQ_ACTIVITY_METER_STATUS_GET_PERCENT_BUSY(sq_activity_meter_status) \ + ((sq_activity_meter_status & SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) >> SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT) + +#define SQ_ACTIVITY_METER_STATUS_SET_PERCENT_BUSY(sq_activity_meter_status_reg, percent_busy) \ + sq_activity_meter_status_reg = (sq_activity_meter_status_reg & ~SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) | (percent_busy << SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_activity_meter_status_t { + unsigned int percent_busy : SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE; + unsigned int : 24; + } sq_activity_meter_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_activity_meter_status_t { + unsigned int : 24; + unsigned int percent_busy : SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE; + } sq_activity_meter_status_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_activity_meter_status_t f; +} sq_activity_meter_status_u; + + +/* + * SQ_INPUT_ARB_PRIORITY struct + */ + +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE 3 +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE 1 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE 3 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE 1 +#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE 10 + +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT 0 +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT 3 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT 4 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT 7 +#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT 8 + +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK 0x00000007 +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK 0x00000008 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK 0x00000070 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK 0x00000080 +#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK 0x0003ff00 + +#define SQ_INPUT_ARB_PRIORITY_MASK \ + (SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK | \ + SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK | \ + SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK | \ + SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK | \ + SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) + +#define SQ_INPUT_ARB_PRIORITY(pc_avail_weight, pc_avail_sign, sx_avail_weight, sx_avail_sign, threshold) \ + ((pc_avail_weight << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) | \ + (pc_avail_sign << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) | \ + (sx_avail_weight << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) | \ + (sx_avail_sign << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) | \ + (threshold << SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT)) + +#define SQ_INPUT_ARB_PRIORITY_GET_PC_AVAIL_WEIGHT(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) >> SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_GET_PC_AVAIL_SIGN(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) >> SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_GET_SX_AVAIL_WEIGHT(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) >> SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_GET_SX_AVAIL_SIGN(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) >> SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_GET_THRESHOLD(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) >> SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT) + +#define SQ_INPUT_ARB_PRIORITY_SET_PC_AVAIL_WEIGHT(sq_input_arb_priority_reg, pc_avail_weight) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) | (pc_avail_weight << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_SET_PC_AVAIL_SIGN(sq_input_arb_priority_reg, pc_avail_sign) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) | (pc_avail_sign << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_SET_SX_AVAIL_WEIGHT(sq_input_arb_priority_reg, sx_avail_weight) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) | (sx_avail_weight << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_SET_SX_AVAIL_SIGN(sq_input_arb_priority_reg, sx_avail_sign) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) | (sx_avail_sign << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_SET_THRESHOLD(sq_input_arb_priority_reg, threshold) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) | (threshold << SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_input_arb_priority_t { + unsigned int pc_avail_weight : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE; + unsigned int pc_avail_sign : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE; + unsigned int sx_avail_weight : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE; + unsigned int sx_avail_sign : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE; + unsigned int threshold : SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE; + unsigned int : 14; + } sq_input_arb_priority_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_input_arb_priority_t { + unsigned int : 14; + unsigned int threshold : SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE; + unsigned int sx_avail_sign : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE; + unsigned int sx_avail_weight : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE; + unsigned int pc_avail_sign : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE; + unsigned int pc_avail_weight : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE; + } sq_input_arb_priority_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_input_arb_priority_t f; +} sq_input_arb_priority_u; + + +/* + * SQ_THREAD_ARB_PRIORITY struct + */ + +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE 3 +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE 1 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE 3 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE 1 +#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE 10 +#define SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE 2 +#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE 1 +#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE 1 +#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE 1 + +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT 0 +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT 3 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT 4 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT 7 +#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT 8 +#define SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT 18 +#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT 20 +#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT 21 +#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT 22 + +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK 0x00000007 +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK 0x00000008 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK 0x00000070 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK 0x00000080 +#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK 0x0003ff00 +#define SQ_THREAD_ARB_PRIORITY_RESERVED_MASK 0x000c0000 +#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK 0x00100000 +#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK 0x00200000 +#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK 0x00400000 + +#define SQ_THREAD_ARB_PRIORITY_MASK \ + (SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK | \ + SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK | \ + SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK | \ + SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK | \ + SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK | \ + SQ_THREAD_ARB_PRIORITY_RESERVED_MASK | \ + SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK | \ + SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK | \ + SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) + +#define SQ_THREAD_ARB_PRIORITY(pc_avail_weight, pc_avail_sign, sx_avail_weight, sx_avail_sign, threshold, reserved, vs_prioritize_serial, ps_prioritize_serial, use_serial_count_threshold) \ + ((pc_avail_weight << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) | \ + (pc_avail_sign << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) | \ + (sx_avail_weight << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) | \ + (sx_avail_sign << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) | \ + (threshold << SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT) | \ + (reserved << SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT) | \ + (vs_prioritize_serial << SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT) | \ + (ps_prioritize_serial << SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT) | \ + (use_serial_count_threshold << SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT)) + +#define SQ_THREAD_ARB_PRIORITY_GET_PC_AVAIL_WEIGHT(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) >> SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_PC_AVAIL_SIGN(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) >> SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_SX_AVAIL_WEIGHT(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) >> SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_SX_AVAIL_SIGN(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) >> SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_THRESHOLD(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK) >> SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_RESERVED(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_RESERVED_MASK) >> SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_VS_PRIORITIZE_SERIAL(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK) >> SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_PS_PRIORITIZE_SERIAL(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK) >> SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_USE_SERIAL_COUNT_THRESHOLD(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) >> SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT) + +#define SQ_THREAD_ARB_PRIORITY_SET_PC_AVAIL_WEIGHT(sq_thread_arb_priority_reg, pc_avail_weight) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) | (pc_avail_weight << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_PC_AVAIL_SIGN(sq_thread_arb_priority_reg, pc_avail_sign) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) | (pc_avail_sign << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_SX_AVAIL_WEIGHT(sq_thread_arb_priority_reg, sx_avail_weight) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) | (sx_avail_weight << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_SX_AVAIL_SIGN(sq_thread_arb_priority_reg, sx_avail_sign) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) | (sx_avail_sign << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_THRESHOLD(sq_thread_arb_priority_reg, threshold) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK) | (threshold << SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_RESERVED(sq_thread_arb_priority_reg, reserved) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_RESERVED_MASK) | (reserved << SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_VS_PRIORITIZE_SERIAL(sq_thread_arb_priority_reg, vs_prioritize_serial) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK) | (vs_prioritize_serial << SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_PS_PRIORITIZE_SERIAL(sq_thread_arb_priority_reg, ps_prioritize_serial) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK) | (ps_prioritize_serial << SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_USE_SERIAL_COUNT_THRESHOLD(sq_thread_arb_priority_reg, use_serial_count_threshold) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) | (use_serial_count_threshold << SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_thread_arb_priority_t { + unsigned int pc_avail_weight : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE; + unsigned int pc_avail_sign : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE; + unsigned int sx_avail_weight : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE; + unsigned int sx_avail_sign : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE; + unsigned int threshold : SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE; + unsigned int reserved : SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE; + unsigned int vs_prioritize_serial : SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE; + unsigned int ps_prioritize_serial : SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE; + unsigned int use_serial_count_threshold : SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE; + unsigned int : 9; + } sq_thread_arb_priority_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_thread_arb_priority_t { + unsigned int : 9; + unsigned int use_serial_count_threshold : SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE; + unsigned int ps_prioritize_serial : SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE; + unsigned int vs_prioritize_serial : SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE; + unsigned int reserved : SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE; + unsigned int threshold : SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE; + unsigned int sx_avail_sign : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE; + unsigned int sx_avail_weight : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE; + unsigned int pc_avail_sign : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE; + unsigned int pc_avail_weight : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE; + } sq_thread_arb_priority_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_thread_arb_priority_t f; +} sq_thread_arb_priority_u; + + +/* + * SQ_DEBUG_INPUT_FSM struct + */ + +#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE 3 +#define SQ_DEBUG_INPUT_FSM_RESERVED_SIZE 1 +#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE 4 +#define SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE 3 +#define SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE 1 +#define SQ_DEBUG_INPUT_FSM_PC_AS_SIZE 3 +#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE 5 +#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE 8 + +#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT 0 +#define SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT 3 +#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT 4 +#define SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT 8 +#define SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT 11 +#define SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT 12 +#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT 15 +#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT 20 + +#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK 0x00000007 +#define SQ_DEBUG_INPUT_FSM_RESERVED_MASK 0x00000008 +#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK 0x000000f0 +#define SQ_DEBUG_INPUT_FSM_PC_PISM_MASK 0x00000700 +#define SQ_DEBUG_INPUT_FSM_RESERVED1_MASK 0x00000800 +#define SQ_DEBUG_INPUT_FSM_PC_AS_MASK 0x00007000 +#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK 0x000f8000 +#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK 0x0ff00000 + +#define SQ_DEBUG_INPUT_FSM_MASK \ + (SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK | \ + SQ_DEBUG_INPUT_FSM_RESERVED_MASK | \ + SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK | \ + SQ_DEBUG_INPUT_FSM_PC_PISM_MASK | \ + SQ_DEBUG_INPUT_FSM_RESERVED1_MASK | \ + SQ_DEBUG_INPUT_FSM_PC_AS_MASK | \ + SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK | \ + SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) + +#define SQ_DEBUG_INPUT_FSM(vc_vsr_ld, reserved, vc_gpr_ld, pc_pism, reserved1, pc_as, pc_interp_cnt, pc_gpr_size) \ + ((vc_vsr_ld << SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT) | \ + (reserved << SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT) | \ + (vc_gpr_ld << SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT) | \ + (pc_pism << SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT) | \ + (reserved1 << SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT) | \ + (pc_as << SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT) | \ + (pc_interp_cnt << SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT) | \ + (pc_gpr_size << SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT)) + +#define SQ_DEBUG_INPUT_FSM_GET_VC_VSR_LD(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK) >> SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_RESERVED(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_RESERVED_MASK) >> SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_VC_GPR_LD(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK) >> SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_PC_PISM(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_PISM_MASK) >> SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_RESERVED1(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_RESERVED1_MASK) >> SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_PC_AS(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_AS_MASK) >> SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_PC_INTERP_CNT(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK) >> SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_PC_GPR_SIZE(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) >> SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT) + +#define SQ_DEBUG_INPUT_FSM_SET_VC_VSR_LD(sq_debug_input_fsm_reg, vc_vsr_ld) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK) | (vc_vsr_ld << SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_RESERVED(sq_debug_input_fsm_reg, reserved) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_RESERVED_MASK) | (reserved << SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_VC_GPR_LD(sq_debug_input_fsm_reg, vc_gpr_ld) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK) | (vc_gpr_ld << SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_PC_PISM(sq_debug_input_fsm_reg, pc_pism) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_PISM_MASK) | (pc_pism << SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_RESERVED1(sq_debug_input_fsm_reg, reserved1) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_PC_AS(sq_debug_input_fsm_reg, pc_as) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_AS_MASK) | (pc_as << SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_PC_INTERP_CNT(sq_debug_input_fsm_reg, pc_interp_cnt) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK) | (pc_interp_cnt << SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_PC_GPR_SIZE(sq_debug_input_fsm_reg, pc_gpr_size) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) | (pc_gpr_size << SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_input_fsm_t { + unsigned int vc_vsr_ld : SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE; + unsigned int reserved : SQ_DEBUG_INPUT_FSM_RESERVED_SIZE; + unsigned int vc_gpr_ld : SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE; + unsigned int pc_pism : SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE; + unsigned int reserved1 : SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE; + unsigned int pc_as : SQ_DEBUG_INPUT_FSM_PC_AS_SIZE; + unsigned int pc_interp_cnt : SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE; + unsigned int pc_gpr_size : SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE; + unsigned int : 4; + } sq_debug_input_fsm_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_input_fsm_t { + unsigned int : 4; + unsigned int pc_gpr_size : SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE; + unsigned int pc_interp_cnt : SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE; + unsigned int pc_as : SQ_DEBUG_INPUT_FSM_PC_AS_SIZE; + unsigned int reserved1 : SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE; + unsigned int pc_pism : SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE; + unsigned int vc_gpr_ld : SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE; + unsigned int reserved : SQ_DEBUG_INPUT_FSM_RESERVED_SIZE; + unsigned int vc_vsr_ld : SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE; + } sq_debug_input_fsm_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_input_fsm_t f; +} sq_debug_input_fsm_u; + + +/* + * SQ_DEBUG_CONST_MGR_FSM struct + */ + +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE 5 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE 3 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE 5 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE 3 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE 2 +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE 2 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE 1 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE 1 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE 1 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE 1 + +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT 0 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT 5 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT 8 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT 13 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT 16 +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT 18 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT 20 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT 21 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT 22 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT 23 + +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK 0x0000001f +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK 0x000000e0 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK 0x00001f00 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK 0x0000e000 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK 0x00030000 +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK 0x000c0000 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK 0x00100000 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK 0x00200000 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK 0x00400000 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK 0x00800000 + +#define SQ_DEBUG_CONST_MGR_FSM_MASK \ + (SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) + +#define SQ_DEBUG_CONST_MGR_FSM(tex_const_event_state, reserved1, alu_const_event_state, reserved2, alu_const_cntx_valid, tex_const_cntx_valid, cntx0_vtx_event_done, cntx0_pix_event_done, cntx1_vtx_event_done, cntx1_pix_event_done) \ + ((tex_const_event_state << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT) | \ + (reserved1 << SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT) | \ + (alu_const_event_state << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT) | \ + (reserved2 << SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT) | \ + (alu_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT) | \ + (tex_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT) | \ + (cntx0_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT) | \ + (cntx0_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT) | \ + (cntx1_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT) | \ + (cntx1_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT)) + +#define SQ_DEBUG_CONST_MGR_FSM_GET_TEX_CONST_EVENT_STATE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_RESERVED1(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK) >> SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_ALU_CONST_EVENT_STATE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_RESERVED2(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK) >> SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_ALU_CONST_CNTX_VALID(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK) >> SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_TEX_CONST_CNTX_VALID(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK) >> SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX0_VTX_EVENT_DONE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX0_PIX_EVENT_DONE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX1_VTX_EVENT_DONE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX1_PIX_EVENT_DONE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT) + +#define SQ_DEBUG_CONST_MGR_FSM_SET_TEX_CONST_EVENT_STATE(sq_debug_const_mgr_fsm_reg, tex_const_event_state) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK) | (tex_const_event_state << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_RESERVED1(sq_debug_const_mgr_fsm_reg, reserved1) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_ALU_CONST_EVENT_STATE(sq_debug_const_mgr_fsm_reg, alu_const_event_state) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK) | (alu_const_event_state << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_RESERVED2(sq_debug_const_mgr_fsm_reg, reserved2) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_ALU_CONST_CNTX_VALID(sq_debug_const_mgr_fsm_reg, alu_const_cntx_valid) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK) | (alu_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_TEX_CONST_CNTX_VALID(sq_debug_const_mgr_fsm_reg, tex_const_cntx_valid) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK) | (tex_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX0_VTX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx0_vtx_event_done) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK) | (cntx0_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX0_PIX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx0_pix_event_done) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK) | (cntx0_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX1_VTX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx1_vtx_event_done) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK) | (cntx1_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX1_PIX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx1_pix_event_done) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) | (cntx1_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_const_mgr_fsm_t { + unsigned int tex_const_event_state : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE; + unsigned int reserved1 : SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE; + unsigned int alu_const_event_state : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE; + unsigned int reserved2 : SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE; + unsigned int alu_const_cntx_valid : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE; + unsigned int tex_const_cntx_valid : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE; + unsigned int cntx0_vtx_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE; + unsigned int cntx0_pix_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE; + unsigned int cntx1_vtx_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE; + unsigned int cntx1_pix_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE; + unsigned int : 8; + } sq_debug_const_mgr_fsm_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_const_mgr_fsm_t { + unsigned int : 8; + unsigned int cntx1_pix_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE; + unsigned int cntx1_vtx_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE; + unsigned int cntx0_pix_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE; + unsigned int cntx0_vtx_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE; + unsigned int tex_const_cntx_valid : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE; + unsigned int alu_const_cntx_valid : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE; + unsigned int reserved2 : SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE; + unsigned int alu_const_event_state : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE; + unsigned int reserved1 : SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE; + unsigned int tex_const_event_state : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE; + } sq_debug_const_mgr_fsm_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_const_mgr_fsm_t f; +} sq_debug_const_mgr_fsm_u; + + +/* + * SQ_DEBUG_TP_FSM struct + */ + +#define SQ_DEBUG_TP_FSM_EX_TP_SIZE 3 +#define SQ_DEBUG_TP_FSM_RESERVED0_SIZE 1 +#define SQ_DEBUG_TP_FSM_CF_TP_SIZE 4 +#define SQ_DEBUG_TP_FSM_IF_TP_SIZE 3 +#define SQ_DEBUG_TP_FSM_RESERVED1_SIZE 1 +#define SQ_DEBUG_TP_FSM_TIS_TP_SIZE 2 +#define SQ_DEBUG_TP_FSM_RESERVED2_SIZE 2 +#define SQ_DEBUG_TP_FSM_GS_TP_SIZE 2 +#define SQ_DEBUG_TP_FSM_RESERVED3_SIZE 2 +#define SQ_DEBUG_TP_FSM_FCR_TP_SIZE 2 +#define SQ_DEBUG_TP_FSM_RESERVED4_SIZE 2 +#define SQ_DEBUG_TP_FSM_FCS_TP_SIZE 2 +#define SQ_DEBUG_TP_FSM_RESERVED5_SIZE 2 +#define SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE 3 + +#define SQ_DEBUG_TP_FSM_EX_TP_SHIFT 0 +#define SQ_DEBUG_TP_FSM_RESERVED0_SHIFT 3 +#define SQ_DEBUG_TP_FSM_CF_TP_SHIFT 4 +#define SQ_DEBUG_TP_FSM_IF_TP_SHIFT 8 +#define SQ_DEBUG_TP_FSM_RESERVED1_SHIFT 11 +#define SQ_DEBUG_TP_FSM_TIS_TP_SHIFT 12 +#define SQ_DEBUG_TP_FSM_RESERVED2_SHIFT 14 +#define SQ_DEBUG_TP_FSM_GS_TP_SHIFT 16 +#define SQ_DEBUG_TP_FSM_RESERVED3_SHIFT 18 +#define SQ_DEBUG_TP_FSM_FCR_TP_SHIFT 20 +#define SQ_DEBUG_TP_FSM_RESERVED4_SHIFT 22 +#define SQ_DEBUG_TP_FSM_FCS_TP_SHIFT 24 +#define SQ_DEBUG_TP_FSM_RESERVED5_SHIFT 26 +#define SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT 28 + +#define SQ_DEBUG_TP_FSM_EX_TP_MASK 0x00000007 +#define SQ_DEBUG_TP_FSM_RESERVED0_MASK 0x00000008 +#define SQ_DEBUG_TP_FSM_CF_TP_MASK 0x000000f0 +#define SQ_DEBUG_TP_FSM_IF_TP_MASK 0x00000700 +#define SQ_DEBUG_TP_FSM_RESERVED1_MASK 0x00000800 +#define SQ_DEBUG_TP_FSM_TIS_TP_MASK 0x00003000 +#define SQ_DEBUG_TP_FSM_RESERVED2_MASK 0x0000c000 +#define SQ_DEBUG_TP_FSM_GS_TP_MASK 0x00030000 +#define SQ_DEBUG_TP_FSM_RESERVED3_MASK 0x000c0000 +#define SQ_DEBUG_TP_FSM_FCR_TP_MASK 0x00300000 +#define SQ_DEBUG_TP_FSM_RESERVED4_MASK 0x00c00000 +#define SQ_DEBUG_TP_FSM_FCS_TP_MASK 0x03000000 +#define SQ_DEBUG_TP_FSM_RESERVED5_MASK 0x0c000000 +#define SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK 0x70000000 + +#define SQ_DEBUG_TP_FSM_MASK \ + (SQ_DEBUG_TP_FSM_EX_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED0_MASK | \ + SQ_DEBUG_TP_FSM_CF_TP_MASK | \ + SQ_DEBUG_TP_FSM_IF_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED1_MASK | \ + SQ_DEBUG_TP_FSM_TIS_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED2_MASK | \ + SQ_DEBUG_TP_FSM_GS_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED3_MASK | \ + SQ_DEBUG_TP_FSM_FCR_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED4_MASK | \ + SQ_DEBUG_TP_FSM_FCS_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED5_MASK | \ + SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) + +#define SQ_DEBUG_TP_FSM(ex_tp, reserved0, cf_tp, if_tp, reserved1, tis_tp, reserved2, gs_tp, reserved3, fcr_tp, reserved4, fcs_tp, reserved5, arb_tr_tp) \ + ((ex_tp << SQ_DEBUG_TP_FSM_EX_TP_SHIFT) | \ + (reserved0 << SQ_DEBUG_TP_FSM_RESERVED0_SHIFT) | \ + (cf_tp << SQ_DEBUG_TP_FSM_CF_TP_SHIFT) | \ + (if_tp << SQ_DEBUG_TP_FSM_IF_TP_SHIFT) | \ + (reserved1 << SQ_DEBUG_TP_FSM_RESERVED1_SHIFT) | \ + (tis_tp << SQ_DEBUG_TP_FSM_TIS_TP_SHIFT) | \ + (reserved2 << SQ_DEBUG_TP_FSM_RESERVED2_SHIFT) | \ + (gs_tp << SQ_DEBUG_TP_FSM_GS_TP_SHIFT) | \ + (reserved3 << SQ_DEBUG_TP_FSM_RESERVED3_SHIFT) | \ + (fcr_tp << SQ_DEBUG_TP_FSM_FCR_TP_SHIFT) | \ + (reserved4 << SQ_DEBUG_TP_FSM_RESERVED4_SHIFT) | \ + (fcs_tp << SQ_DEBUG_TP_FSM_FCS_TP_SHIFT) | \ + (reserved5 << SQ_DEBUG_TP_FSM_RESERVED5_SHIFT) | \ + (arb_tr_tp << SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT)) + +#define SQ_DEBUG_TP_FSM_GET_EX_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_EX_TP_MASK) >> SQ_DEBUG_TP_FSM_EX_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED0(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED0_MASK) >> SQ_DEBUG_TP_FSM_RESERVED0_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_CF_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_CF_TP_MASK) >> SQ_DEBUG_TP_FSM_CF_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_IF_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_IF_TP_MASK) >> SQ_DEBUG_TP_FSM_IF_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED1(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED1_MASK) >> SQ_DEBUG_TP_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_TIS_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_TIS_TP_MASK) >> SQ_DEBUG_TP_FSM_TIS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED2(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED2_MASK) >> SQ_DEBUG_TP_FSM_RESERVED2_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_GS_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_GS_TP_MASK) >> SQ_DEBUG_TP_FSM_GS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED3(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED3_MASK) >> SQ_DEBUG_TP_FSM_RESERVED3_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_FCR_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_FCR_TP_MASK) >> SQ_DEBUG_TP_FSM_FCR_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED4(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED4_MASK) >> SQ_DEBUG_TP_FSM_RESERVED4_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_FCS_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_FCS_TP_MASK) >> SQ_DEBUG_TP_FSM_FCS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED5(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED5_MASK) >> SQ_DEBUG_TP_FSM_RESERVED5_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_ARB_TR_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) >> SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT) + +#define SQ_DEBUG_TP_FSM_SET_EX_TP(sq_debug_tp_fsm_reg, ex_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_EX_TP_MASK) | (ex_tp << SQ_DEBUG_TP_FSM_EX_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED0(sq_debug_tp_fsm_reg, reserved0) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_TP_FSM_RESERVED0_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_CF_TP(sq_debug_tp_fsm_reg, cf_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_CF_TP_MASK) | (cf_tp << SQ_DEBUG_TP_FSM_CF_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_IF_TP(sq_debug_tp_fsm_reg, if_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_IF_TP_MASK) | (if_tp << SQ_DEBUG_TP_FSM_IF_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED1(sq_debug_tp_fsm_reg, reserved1) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_TP_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_TIS_TP(sq_debug_tp_fsm_reg, tis_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_TIS_TP_MASK) | (tis_tp << SQ_DEBUG_TP_FSM_TIS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED2(sq_debug_tp_fsm_reg, reserved2) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_TP_FSM_RESERVED2_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_GS_TP(sq_debug_tp_fsm_reg, gs_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_GS_TP_MASK) | (gs_tp << SQ_DEBUG_TP_FSM_GS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED3(sq_debug_tp_fsm_reg, reserved3) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_TP_FSM_RESERVED3_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_FCR_TP(sq_debug_tp_fsm_reg, fcr_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_FCR_TP_MASK) | (fcr_tp << SQ_DEBUG_TP_FSM_FCR_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED4(sq_debug_tp_fsm_reg, reserved4) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_TP_FSM_RESERVED4_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_FCS_TP(sq_debug_tp_fsm_reg, fcs_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_FCS_TP_MASK) | (fcs_tp << SQ_DEBUG_TP_FSM_FCS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED5(sq_debug_tp_fsm_reg, reserved5) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_TP_FSM_RESERVED5_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_ARB_TR_TP(sq_debug_tp_fsm_reg, arb_tr_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) | (arb_tr_tp << SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_tp_fsm_t { + unsigned int ex_tp : SQ_DEBUG_TP_FSM_EX_TP_SIZE; + unsigned int reserved0 : SQ_DEBUG_TP_FSM_RESERVED0_SIZE; + unsigned int cf_tp : SQ_DEBUG_TP_FSM_CF_TP_SIZE; + unsigned int if_tp : SQ_DEBUG_TP_FSM_IF_TP_SIZE; + unsigned int reserved1 : SQ_DEBUG_TP_FSM_RESERVED1_SIZE; + unsigned int tis_tp : SQ_DEBUG_TP_FSM_TIS_TP_SIZE; + unsigned int reserved2 : SQ_DEBUG_TP_FSM_RESERVED2_SIZE; + unsigned int gs_tp : SQ_DEBUG_TP_FSM_GS_TP_SIZE; + unsigned int reserved3 : SQ_DEBUG_TP_FSM_RESERVED3_SIZE; + unsigned int fcr_tp : SQ_DEBUG_TP_FSM_FCR_TP_SIZE; + unsigned int reserved4 : SQ_DEBUG_TP_FSM_RESERVED4_SIZE; + unsigned int fcs_tp : SQ_DEBUG_TP_FSM_FCS_TP_SIZE; + unsigned int reserved5 : SQ_DEBUG_TP_FSM_RESERVED5_SIZE; + unsigned int arb_tr_tp : SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE; + unsigned int : 1; + } sq_debug_tp_fsm_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_tp_fsm_t { + unsigned int : 1; + unsigned int arb_tr_tp : SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE; + unsigned int reserved5 : SQ_DEBUG_TP_FSM_RESERVED5_SIZE; + unsigned int fcs_tp : SQ_DEBUG_TP_FSM_FCS_TP_SIZE; + unsigned int reserved4 : SQ_DEBUG_TP_FSM_RESERVED4_SIZE; + unsigned int fcr_tp : SQ_DEBUG_TP_FSM_FCR_TP_SIZE; + unsigned int reserved3 : SQ_DEBUG_TP_FSM_RESERVED3_SIZE; + unsigned int gs_tp : SQ_DEBUG_TP_FSM_GS_TP_SIZE; + unsigned int reserved2 : SQ_DEBUG_TP_FSM_RESERVED2_SIZE; + unsigned int tis_tp : SQ_DEBUG_TP_FSM_TIS_TP_SIZE; + unsigned int reserved1 : SQ_DEBUG_TP_FSM_RESERVED1_SIZE; + unsigned int if_tp : SQ_DEBUG_TP_FSM_IF_TP_SIZE; + unsigned int cf_tp : SQ_DEBUG_TP_FSM_CF_TP_SIZE; + unsigned int reserved0 : SQ_DEBUG_TP_FSM_RESERVED0_SIZE; + unsigned int ex_tp : SQ_DEBUG_TP_FSM_EX_TP_SIZE; + } sq_debug_tp_fsm_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_tp_fsm_t f; +} sq_debug_tp_fsm_u; + + +/* + * SQ_DEBUG_FSM_ALU_0 struct + */ + +#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE 4 +#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE 3 + +#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT 0 +#define SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT 3 +#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT 4 +#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT 8 +#define SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT 11 +#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT 12 +#define SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT 15 +#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT 16 +#define SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT 19 +#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT 20 +#define SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT 23 +#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT 24 +#define SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT 27 +#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT 28 + +#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK 0x00000007 +#define SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK 0x00000008 +#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK 0x000000f0 +#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK 0x00000700 +#define SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK 0x00000800 +#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK 0x00007000 +#define SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK 0x00008000 +#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK 0x00070000 +#define SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK 0x00080000 +#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK 0x00700000 +#define SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK 0x00800000 +#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK 0x07000000 +#define SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK 0x08000000 +#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK 0x70000000 + +#define SQ_DEBUG_FSM_ALU_0_MASK \ + (SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK | \ + SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK | \ + SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK | \ + SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK | \ + SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK | \ + SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK | \ + SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) + +#define SQ_DEBUG_FSM_ALU_0(ex_alu_0, reserved0, cf_alu_0, if_alu_0, reserved1, du1_alu_0, reserved2, du0_alu_0, reserved3, ais_alu_0, reserved4, acs_alu_0, reserved5, arb_tr_alu) \ + ((ex_alu_0 << SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT) | \ + (reserved0 << SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT) | \ + (cf_alu_0 << SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT) | \ + (if_alu_0 << SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT) | \ + (reserved1 << SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT) | \ + (du1_alu_0 << SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT) | \ + (reserved2 << SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT) | \ + (du0_alu_0 << SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT) | \ + (reserved3 << SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT) | \ + (ais_alu_0 << SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT) | \ + (reserved4 << SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT) | \ + (acs_alu_0 << SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT) | \ + (reserved5 << SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT) | \ + (arb_tr_alu << SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT)) + +#define SQ_DEBUG_FSM_ALU_0_GET_EX_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_CF_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_IF_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED1(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_DU1_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED2(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_DU0_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED3(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_AIS_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED4(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_ACS_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED5(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_ARB_TR_ALU(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) >> SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT) + +#define SQ_DEBUG_FSM_ALU_0_SET_EX_ALU_0(sq_debug_fsm_alu_0_reg, ex_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK) | (ex_alu_0 << SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED0(sq_debug_fsm_alu_0_reg, reserved0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_CF_ALU_0(sq_debug_fsm_alu_0_reg, cf_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK) | (cf_alu_0 << SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_IF_ALU_0(sq_debug_fsm_alu_0_reg, if_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK) | (if_alu_0 << SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED1(sq_debug_fsm_alu_0_reg, reserved1) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_DU1_ALU_0(sq_debug_fsm_alu_0_reg, du1_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK) | (du1_alu_0 << SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED2(sq_debug_fsm_alu_0_reg, reserved2) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_DU0_ALU_0(sq_debug_fsm_alu_0_reg, du0_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK) | (du0_alu_0 << SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED3(sq_debug_fsm_alu_0_reg, reserved3) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_AIS_ALU_0(sq_debug_fsm_alu_0_reg, ais_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK) | (ais_alu_0 << SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED4(sq_debug_fsm_alu_0_reg, reserved4) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_ACS_ALU_0(sq_debug_fsm_alu_0_reg, acs_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK) | (acs_alu_0 << SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED5(sq_debug_fsm_alu_0_reg, reserved5) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_ARB_TR_ALU(sq_debug_fsm_alu_0_reg, arb_tr_alu) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) | (arb_tr_alu << SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_fsm_alu_0_t { + unsigned int ex_alu_0 : SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE; + unsigned int reserved0 : SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE; + unsigned int cf_alu_0 : SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE; + unsigned int if_alu_0 : SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE; + unsigned int reserved1 : SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE; + unsigned int du1_alu_0 : SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE; + unsigned int reserved2 : SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE; + unsigned int du0_alu_0 : SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE; + unsigned int reserved3 : SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE; + unsigned int ais_alu_0 : SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE; + unsigned int reserved4 : SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE; + unsigned int acs_alu_0 : SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE; + unsigned int reserved5 : SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE; + unsigned int arb_tr_alu : SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE; + unsigned int : 1; + } sq_debug_fsm_alu_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_fsm_alu_0_t { + unsigned int : 1; + unsigned int arb_tr_alu : SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE; + unsigned int reserved5 : SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE; + unsigned int acs_alu_0 : SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE; + unsigned int reserved4 : SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE; + unsigned int ais_alu_0 : SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE; + unsigned int reserved3 : SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE; + unsigned int du0_alu_0 : SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE; + unsigned int reserved2 : SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE; + unsigned int du1_alu_0 : SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE; + unsigned int reserved1 : SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE; + unsigned int if_alu_0 : SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE; + unsigned int cf_alu_0 : SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE; + unsigned int reserved0 : SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE; + unsigned int ex_alu_0 : SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE; + } sq_debug_fsm_alu_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_fsm_alu_0_t f; +} sq_debug_fsm_alu_0_u; + + +/* + * SQ_DEBUG_FSM_ALU_1 struct + */ + +#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE 4 +#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE 3 + +#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT 0 +#define SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT 3 +#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT 4 +#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT 8 +#define SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT 11 +#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT 12 +#define SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT 15 +#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT 16 +#define SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT 19 +#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT 20 +#define SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT 23 +#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT 24 +#define SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT 27 +#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT 28 + +#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK 0x00000007 +#define SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK 0x00000008 +#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK 0x000000f0 +#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK 0x00000700 +#define SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK 0x00000800 +#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK 0x00007000 +#define SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK 0x00008000 +#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK 0x00070000 +#define SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK 0x00080000 +#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK 0x00700000 +#define SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK 0x00800000 +#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK 0x07000000 +#define SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK 0x08000000 +#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK 0x70000000 + +#define SQ_DEBUG_FSM_ALU_1_MASK \ + (SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK | \ + SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK | \ + SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK | \ + SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK | \ + SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK | \ + SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK | \ + SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) + +#define SQ_DEBUG_FSM_ALU_1(ex_alu_0, reserved0, cf_alu_0, if_alu_0, reserved1, du1_alu_0, reserved2, du0_alu_0, reserved3, ais_alu_0, reserved4, acs_alu_0, reserved5, arb_tr_alu) \ + ((ex_alu_0 << SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT) | \ + (reserved0 << SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT) | \ + (cf_alu_0 << SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT) | \ + (if_alu_0 << SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT) | \ + (reserved1 << SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT) | \ + (du1_alu_0 << SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT) | \ + (reserved2 << SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT) | \ + (du0_alu_0 << SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT) | \ + (reserved3 << SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT) | \ + (ais_alu_0 << SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT) | \ + (reserved4 << SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT) | \ + (acs_alu_0 << SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT) | \ + (reserved5 << SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT) | \ + (arb_tr_alu << SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT)) + +#define SQ_DEBUG_FSM_ALU_1_GET_EX_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_CF_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_IF_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED1(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_DU1_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED2(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_DU0_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED3(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_AIS_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED4(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_ACS_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED5(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_ARB_TR_ALU(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) >> SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT) + +#define SQ_DEBUG_FSM_ALU_1_SET_EX_ALU_0(sq_debug_fsm_alu_1_reg, ex_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK) | (ex_alu_0 << SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED0(sq_debug_fsm_alu_1_reg, reserved0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_CF_ALU_0(sq_debug_fsm_alu_1_reg, cf_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK) | (cf_alu_0 << SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_IF_ALU_0(sq_debug_fsm_alu_1_reg, if_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK) | (if_alu_0 << SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED1(sq_debug_fsm_alu_1_reg, reserved1) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_DU1_ALU_0(sq_debug_fsm_alu_1_reg, du1_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK) | (du1_alu_0 << SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED2(sq_debug_fsm_alu_1_reg, reserved2) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_DU0_ALU_0(sq_debug_fsm_alu_1_reg, du0_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK) | (du0_alu_0 << SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED3(sq_debug_fsm_alu_1_reg, reserved3) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_AIS_ALU_0(sq_debug_fsm_alu_1_reg, ais_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK) | (ais_alu_0 << SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED4(sq_debug_fsm_alu_1_reg, reserved4) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_ACS_ALU_0(sq_debug_fsm_alu_1_reg, acs_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK) | (acs_alu_0 << SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED5(sq_debug_fsm_alu_1_reg, reserved5) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_ARB_TR_ALU(sq_debug_fsm_alu_1_reg, arb_tr_alu) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) | (arb_tr_alu << SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_fsm_alu_1_t { + unsigned int ex_alu_0 : SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE; + unsigned int reserved0 : SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE; + unsigned int cf_alu_0 : SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE; + unsigned int if_alu_0 : SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE; + unsigned int reserved1 : SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE; + unsigned int du1_alu_0 : SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE; + unsigned int reserved2 : SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE; + unsigned int du0_alu_0 : SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE; + unsigned int reserved3 : SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE; + unsigned int ais_alu_0 : SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE; + unsigned int reserved4 : SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE; + unsigned int acs_alu_0 : SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE; + unsigned int reserved5 : SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE; + unsigned int arb_tr_alu : SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE; + unsigned int : 1; + } sq_debug_fsm_alu_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_fsm_alu_1_t { + unsigned int : 1; + unsigned int arb_tr_alu : SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE; + unsigned int reserved5 : SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE; + unsigned int acs_alu_0 : SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE; + unsigned int reserved4 : SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE; + unsigned int ais_alu_0 : SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE; + unsigned int reserved3 : SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE; + unsigned int du0_alu_0 : SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE; + unsigned int reserved2 : SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE; + unsigned int du1_alu_0 : SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE; + unsigned int reserved1 : SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE; + unsigned int if_alu_0 : SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE; + unsigned int cf_alu_0 : SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE; + unsigned int reserved0 : SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE; + unsigned int ex_alu_0 : SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE; + } sq_debug_fsm_alu_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_fsm_alu_1_t f; +} sq_debug_fsm_alu_1_u; + + +/* + * SQ_DEBUG_EXP_ALLOC struct + */ + +#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE 4 +#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE 8 +#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE 3 +#define SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE 1 +#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE 6 + +#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT 0 +#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT 4 +#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT 12 +#define SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT 15 +#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT 16 + +#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK 0x0000000f +#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK 0x00000ff0 +#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK 0x00007000 +#define SQ_DEBUG_EXP_ALLOC_RESERVED_MASK 0x00008000 +#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK 0x003f0000 + +#define SQ_DEBUG_EXP_ALLOC_MASK \ + (SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK | \ + SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK | \ + SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK | \ + SQ_DEBUG_EXP_ALLOC_RESERVED_MASK | \ + SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) + +#define SQ_DEBUG_EXP_ALLOC(pos_buf_avail, color_buf_avail, ea_buf_avail, reserved, alloc_tbl_buf_avail) \ + ((pos_buf_avail << SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT) | \ + (color_buf_avail << SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT) | \ + (ea_buf_avail << SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT) | \ + (reserved << SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT) | \ + (alloc_tbl_buf_avail << SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT)) + +#define SQ_DEBUG_EXP_ALLOC_GET_POS_BUF_AVAIL(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_GET_COLOR_BUF_AVAIL(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_GET_EA_BUF_AVAIL(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_GET_RESERVED(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_RESERVED_MASK) >> SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_GET_ALLOC_TBL_BUF_AVAIL(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT) + +#define SQ_DEBUG_EXP_ALLOC_SET_POS_BUF_AVAIL(sq_debug_exp_alloc_reg, pos_buf_avail) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK) | (pos_buf_avail << SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_SET_COLOR_BUF_AVAIL(sq_debug_exp_alloc_reg, color_buf_avail) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK) | (color_buf_avail << SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_SET_EA_BUF_AVAIL(sq_debug_exp_alloc_reg, ea_buf_avail) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK) | (ea_buf_avail << SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_SET_RESERVED(sq_debug_exp_alloc_reg, reserved) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_RESERVED_MASK) | (reserved << SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_SET_ALLOC_TBL_BUF_AVAIL(sq_debug_exp_alloc_reg, alloc_tbl_buf_avail) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) | (alloc_tbl_buf_avail << SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_exp_alloc_t { + unsigned int pos_buf_avail : SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE; + unsigned int color_buf_avail : SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE; + unsigned int ea_buf_avail : SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE; + unsigned int reserved : SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE; + unsigned int alloc_tbl_buf_avail : SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE; + unsigned int : 10; + } sq_debug_exp_alloc_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_exp_alloc_t { + unsigned int : 10; + unsigned int alloc_tbl_buf_avail : SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE; + unsigned int reserved : SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE; + unsigned int ea_buf_avail : SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE; + unsigned int color_buf_avail : SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE; + unsigned int pos_buf_avail : SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE; + } sq_debug_exp_alloc_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_exp_alloc_t f; +} sq_debug_exp_alloc_u; + + +/* + * SQ_DEBUG_PTR_BUFF struct + */ + +#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE 4 +#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE 3 +#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE 5 +#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE 11 + +#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT 0 +#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT 1 +#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT 5 +#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT 6 +#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT 9 +#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT 14 +#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT 15 +#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT 16 +#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT 17 + +#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK 0x00000001 +#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK 0x0000001e +#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK 0x00000020 +#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK 0x000001c0 +#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK 0x00003e00 +#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK 0x00004000 +#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK 0x00008000 +#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK 0x00010000 +#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK 0x0ffe0000 + +#define SQ_DEBUG_PTR_BUFF_MASK \ + (SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK | \ + SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK | \ + SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK | \ + SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK | \ + SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK | \ + SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK | \ + SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK | \ + SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK | \ + SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) + +#define SQ_DEBUG_PTR_BUFF(end_of_buffer, dealloc_cnt, qual_new_vector, event_context_id, sc_event_id, qual_event, prim_type_polygon, ef_empty, vtx_sync_cnt) \ + ((end_of_buffer << SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT) | \ + (dealloc_cnt << SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT) | \ + (qual_new_vector << SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT) | \ + (event_context_id << SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT) | \ + (sc_event_id << SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT) | \ + (qual_event << SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT) | \ + (prim_type_polygon << SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT) | \ + (ef_empty << SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT) | \ + (vtx_sync_cnt << SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT)) + +#define SQ_DEBUG_PTR_BUFF_GET_END_OF_BUFFER(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK) >> SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_DEALLOC_CNT(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK) >> SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_QUAL_NEW_VECTOR(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK) >> SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_EVENT_CONTEXT_ID(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK) >> SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_SC_EVENT_ID(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK) >> SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_QUAL_EVENT(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK) >> SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_PRIM_TYPE_POLYGON(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK) >> SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_EF_EMPTY(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK) >> SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_VTX_SYNC_CNT(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) >> SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT) + +#define SQ_DEBUG_PTR_BUFF_SET_END_OF_BUFFER(sq_debug_ptr_buff_reg, end_of_buffer) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK) | (end_of_buffer << SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_DEALLOC_CNT(sq_debug_ptr_buff_reg, dealloc_cnt) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK) | (dealloc_cnt << SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_QUAL_NEW_VECTOR(sq_debug_ptr_buff_reg, qual_new_vector) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK) | (qual_new_vector << SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_EVENT_CONTEXT_ID(sq_debug_ptr_buff_reg, event_context_id) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK) | (event_context_id << SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_SC_EVENT_ID(sq_debug_ptr_buff_reg, sc_event_id) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK) | (sc_event_id << SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_QUAL_EVENT(sq_debug_ptr_buff_reg, qual_event) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK) | (qual_event << SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_PRIM_TYPE_POLYGON(sq_debug_ptr_buff_reg, prim_type_polygon) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK) | (prim_type_polygon << SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_EF_EMPTY(sq_debug_ptr_buff_reg, ef_empty) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK) | (ef_empty << SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_VTX_SYNC_CNT(sq_debug_ptr_buff_reg, vtx_sync_cnt) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) | (vtx_sync_cnt << SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_ptr_buff_t { + unsigned int end_of_buffer : SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE; + unsigned int dealloc_cnt : SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE; + unsigned int qual_new_vector : SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE; + unsigned int event_context_id : SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE; + unsigned int sc_event_id : SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE; + unsigned int qual_event : SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE; + unsigned int prim_type_polygon : SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE; + unsigned int ef_empty : SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE; + unsigned int vtx_sync_cnt : SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE; + unsigned int : 4; + } sq_debug_ptr_buff_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_ptr_buff_t { + unsigned int : 4; + unsigned int vtx_sync_cnt : SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE; + unsigned int ef_empty : SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE; + unsigned int prim_type_polygon : SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE; + unsigned int qual_event : SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE; + unsigned int sc_event_id : SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE; + unsigned int event_context_id : SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE; + unsigned int qual_new_vector : SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE; + unsigned int dealloc_cnt : SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE; + unsigned int end_of_buffer : SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE; + } sq_debug_ptr_buff_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_ptr_buff_t f; +} sq_debug_ptr_buff_u; + + +/* + * SQ_DEBUG_GPR_VTX struct + */ + +#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE 7 +#define SQ_DEBUG_GPR_VTX_RESERVED_SIZE 1 +#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE 7 +#define SQ_DEBUG_GPR_VTX_RESERVED1_SIZE 1 +#define SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE 7 +#define SQ_DEBUG_GPR_VTX_RESERVED2_SIZE 1 +#define SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE 7 + +#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT 0 +#define SQ_DEBUG_GPR_VTX_RESERVED_SHIFT 7 +#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT 8 +#define SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT 15 +#define SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT 16 +#define SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT 23 +#define SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT 24 + +#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK 0x0000007f +#define SQ_DEBUG_GPR_VTX_RESERVED_MASK 0x00000080 +#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK 0x00007f00 +#define SQ_DEBUG_GPR_VTX_RESERVED1_MASK 0x00008000 +#define SQ_DEBUG_GPR_VTX_VTX_MAX_MASK 0x007f0000 +#define SQ_DEBUG_GPR_VTX_RESERVED2_MASK 0x00800000 +#define SQ_DEBUG_GPR_VTX_VTX_FREE_MASK 0x7f000000 + +#define SQ_DEBUG_GPR_VTX_MASK \ + (SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK | \ + SQ_DEBUG_GPR_VTX_RESERVED_MASK | \ + SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK | \ + SQ_DEBUG_GPR_VTX_RESERVED1_MASK | \ + SQ_DEBUG_GPR_VTX_VTX_MAX_MASK | \ + SQ_DEBUG_GPR_VTX_RESERVED2_MASK | \ + SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) + +#define SQ_DEBUG_GPR_VTX(vtx_tail_ptr, reserved, vtx_head_ptr, reserved1, vtx_max, reserved2, vtx_free) \ + ((vtx_tail_ptr << SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT) | \ + (reserved << SQ_DEBUG_GPR_VTX_RESERVED_SHIFT) | \ + (vtx_head_ptr << SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT) | \ + (reserved1 << SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT) | \ + (vtx_max << SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT) | \ + (reserved2 << SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT) | \ + (vtx_free << SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT)) + +#define SQ_DEBUG_GPR_VTX_GET_VTX_TAIL_PTR(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK) >> SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_RESERVED(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_VTX_HEAD_PTR(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK) >> SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_RESERVED1(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED1_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_VTX_MAX(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_MAX_MASK) >> SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_RESERVED2(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED2_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_VTX_FREE(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) >> SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT) + +#define SQ_DEBUG_GPR_VTX_SET_VTX_TAIL_PTR(sq_debug_gpr_vtx_reg, vtx_tail_ptr) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK) | (vtx_tail_ptr << SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_RESERVED(sq_debug_gpr_vtx_reg, reserved) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED_MASK) | (reserved << SQ_DEBUG_GPR_VTX_RESERVED_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_VTX_HEAD_PTR(sq_debug_gpr_vtx_reg, vtx_head_ptr) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK) | (vtx_head_ptr << SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_RESERVED1(sq_debug_gpr_vtx_reg, reserved1) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_VTX_MAX(sq_debug_gpr_vtx_reg, vtx_max) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_MAX_MASK) | (vtx_max << SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_RESERVED2(sq_debug_gpr_vtx_reg, reserved2) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_VTX_FREE(sq_debug_gpr_vtx_reg, vtx_free) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) | (vtx_free << SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_gpr_vtx_t { + unsigned int vtx_tail_ptr : SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE; + unsigned int reserved : SQ_DEBUG_GPR_VTX_RESERVED_SIZE; + unsigned int vtx_head_ptr : SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE; + unsigned int reserved1 : SQ_DEBUG_GPR_VTX_RESERVED1_SIZE; + unsigned int vtx_max : SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE; + unsigned int reserved2 : SQ_DEBUG_GPR_VTX_RESERVED2_SIZE; + unsigned int vtx_free : SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE; + unsigned int : 1; + } sq_debug_gpr_vtx_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_gpr_vtx_t { + unsigned int : 1; + unsigned int vtx_free : SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE; + unsigned int reserved2 : SQ_DEBUG_GPR_VTX_RESERVED2_SIZE; + unsigned int vtx_max : SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE; + unsigned int reserved1 : SQ_DEBUG_GPR_VTX_RESERVED1_SIZE; + unsigned int vtx_head_ptr : SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE; + unsigned int reserved : SQ_DEBUG_GPR_VTX_RESERVED_SIZE; + unsigned int vtx_tail_ptr : SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE; + } sq_debug_gpr_vtx_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_gpr_vtx_t f; +} sq_debug_gpr_vtx_u; + + +/* + * SQ_DEBUG_GPR_PIX struct + */ + +#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE 7 +#define SQ_DEBUG_GPR_PIX_RESERVED_SIZE 1 +#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE 7 +#define SQ_DEBUG_GPR_PIX_RESERVED1_SIZE 1 +#define SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE 7 +#define SQ_DEBUG_GPR_PIX_RESERVED2_SIZE 1 +#define SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE 7 + +#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT 0 +#define SQ_DEBUG_GPR_PIX_RESERVED_SHIFT 7 +#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT 8 +#define SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT 15 +#define SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT 16 +#define SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT 23 +#define SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT 24 + +#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK 0x0000007f +#define SQ_DEBUG_GPR_PIX_RESERVED_MASK 0x00000080 +#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK 0x00007f00 +#define SQ_DEBUG_GPR_PIX_RESERVED1_MASK 0x00008000 +#define SQ_DEBUG_GPR_PIX_PIX_MAX_MASK 0x007f0000 +#define SQ_DEBUG_GPR_PIX_RESERVED2_MASK 0x00800000 +#define SQ_DEBUG_GPR_PIX_PIX_FREE_MASK 0x7f000000 + +#define SQ_DEBUG_GPR_PIX_MASK \ + (SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK | \ + SQ_DEBUG_GPR_PIX_RESERVED_MASK | \ + SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK | \ + SQ_DEBUG_GPR_PIX_RESERVED1_MASK | \ + SQ_DEBUG_GPR_PIX_PIX_MAX_MASK | \ + SQ_DEBUG_GPR_PIX_RESERVED2_MASK | \ + SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) + +#define SQ_DEBUG_GPR_PIX(pix_tail_ptr, reserved, pix_head_ptr, reserved1, pix_max, reserved2, pix_free) \ + ((pix_tail_ptr << SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT) | \ + (reserved << SQ_DEBUG_GPR_PIX_RESERVED_SHIFT) | \ + (pix_head_ptr << SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT) | \ + (reserved1 << SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT) | \ + (pix_max << SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT) | \ + (reserved2 << SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT) | \ + (pix_free << SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT)) + +#define SQ_DEBUG_GPR_PIX_GET_PIX_TAIL_PTR(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK) >> SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_RESERVED(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_PIX_HEAD_PTR(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK) >> SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_RESERVED1(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED1_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_PIX_MAX(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_MAX_MASK) >> SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_RESERVED2(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED2_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_PIX_FREE(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) >> SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT) + +#define SQ_DEBUG_GPR_PIX_SET_PIX_TAIL_PTR(sq_debug_gpr_pix_reg, pix_tail_ptr) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK) | (pix_tail_ptr << SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_RESERVED(sq_debug_gpr_pix_reg, reserved) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED_MASK) | (reserved << SQ_DEBUG_GPR_PIX_RESERVED_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_PIX_HEAD_PTR(sq_debug_gpr_pix_reg, pix_head_ptr) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK) | (pix_head_ptr << SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_RESERVED1(sq_debug_gpr_pix_reg, reserved1) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_PIX_MAX(sq_debug_gpr_pix_reg, pix_max) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_MAX_MASK) | (pix_max << SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_RESERVED2(sq_debug_gpr_pix_reg, reserved2) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_PIX_FREE(sq_debug_gpr_pix_reg, pix_free) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) | (pix_free << SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_gpr_pix_t { + unsigned int pix_tail_ptr : SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE; + unsigned int reserved : SQ_DEBUG_GPR_PIX_RESERVED_SIZE; + unsigned int pix_head_ptr : SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE; + unsigned int reserved1 : SQ_DEBUG_GPR_PIX_RESERVED1_SIZE; + unsigned int pix_max : SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE; + unsigned int reserved2 : SQ_DEBUG_GPR_PIX_RESERVED2_SIZE; + unsigned int pix_free : SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE; + unsigned int : 1; + } sq_debug_gpr_pix_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_gpr_pix_t { + unsigned int : 1; + unsigned int pix_free : SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE; + unsigned int reserved2 : SQ_DEBUG_GPR_PIX_RESERVED2_SIZE; + unsigned int pix_max : SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE; + unsigned int reserved1 : SQ_DEBUG_GPR_PIX_RESERVED1_SIZE; + unsigned int pix_head_ptr : SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE; + unsigned int reserved : SQ_DEBUG_GPR_PIX_RESERVED_SIZE; + unsigned int pix_tail_ptr : SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE; + } sq_debug_gpr_pix_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_gpr_pix_t f; +} sq_debug_gpr_pix_u; + + +/* + * SQ_DEBUG_TB_STATUS_SEL struct + */ + +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE 4 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE 3 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE 4 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE 1 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE 1 +#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE 2 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE 4 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE 3 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE 6 +#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE 2 +#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE 1 + +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT 0 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT 4 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT 7 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT 11 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT 12 +#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT 14 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT 16 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT 20 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT 23 +#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT 29 +#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT 31 + +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK 0x0000000f +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK 0x00000070 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK 0x00000780 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK 0x00000800 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK 0x00001000 +#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK 0x0000c000 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK 0x000f0000 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK 0x00700000 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK 0x1f800000 +#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK 0x60000000 +#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK 0x80000000 + +#define SQ_DEBUG_TB_STATUS_SEL_MASK \ + (SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) + +#define SQ_DEBUG_TB_STATUS_SEL(vtx_tb_status_reg_sel, vtx_tb_state_mem_dw_sel, vtx_tb_state_mem_rd_addr, vtx_tb_state_mem_rd_en, pix_tb_state_mem_rd_en, debug_bus_trigger_sel, pix_tb_status_reg_sel, pix_tb_state_mem_dw_sel, pix_tb_state_mem_rd_addr, vc_thread_buf_dly, disable_strict_ctx_sync) \ + ((vtx_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT) | \ + (vtx_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT) | \ + (vtx_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT) | \ + (vtx_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT) | \ + (pix_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT) | \ + (debug_bus_trigger_sel << SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT) | \ + (pix_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT) | \ + (pix_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT) | \ + (pix_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT) | \ + (vc_thread_buf_dly << SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT) | \ + (disable_strict_ctx_sync << SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT)) + +#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_DEBUG_BUS_TRIGGER_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_VC_THREAD_BUF_DLY(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_DISABLE_STRICT_CTX_SYNC(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) >> SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT) + +#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel_reg, vtx_tb_status_reg_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK) | (vtx_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_dw_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK) | (vtx_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_rd_addr) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK) | (vtx_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_rd_en) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK) | (vtx_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel_reg, pix_tb_state_mem_rd_en) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK) | (pix_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_DEBUG_BUS_TRIGGER_SEL(sq_debug_tb_status_sel_reg, debug_bus_trigger_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK) | (debug_bus_trigger_sel << SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel_reg, pix_tb_status_reg_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK) | (pix_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel_reg, pix_tb_state_mem_dw_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK) | (pix_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel_reg, pix_tb_state_mem_rd_addr) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK) | (pix_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_VC_THREAD_BUF_DLY(sq_debug_tb_status_sel_reg, vc_thread_buf_dly) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK) | (vc_thread_buf_dly << SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_DISABLE_STRICT_CTX_SYNC(sq_debug_tb_status_sel_reg, disable_strict_ctx_sync) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) | (disable_strict_ctx_sync << SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_tb_status_sel_t { + unsigned int vtx_tb_status_reg_sel : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE; + unsigned int vtx_tb_state_mem_dw_sel : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE; + unsigned int vtx_tb_state_mem_rd_addr : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE; + unsigned int vtx_tb_state_mem_rd_en : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE; + unsigned int pix_tb_state_mem_rd_en : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE; + unsigned int : 1; + unsigned int debug_bus_trigger_sel : SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE; + unsigned int pix_tb_status_reg_sel : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE; + unsigned int pix_tb_state_mem_dw_sel : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE; + unsigned int pix_tb_state_mem_rd_addr : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE; + unsigned int vc_thread_buf_dly : SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE; + unsigned int disable_strict_ctx_sync : SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE; + } sq_debug_tb_status_sel_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_tb_status_sel_t { + unsigned int disable_strict_ctx_sync : SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE; + unsigned int vc_thread_buf_dly : SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE; + unsigned int pix_tb_state_mem_rd_addr : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE; + unsigned int pix_tb_state_mem_dw_sel : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE; + unsigned int pix_tb_status_reg_sel : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE; + unsigned int debug_bus_trigger_sel : SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE; + unsigned int : 1; + unsigned int pix_tb_state_mem_rd_en : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE; + unsigned int vtx_tb_state_mem_rd_en : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE; + unsigned int vtx_tb_state_mem_rd_addr : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE; + unsigned int vtx_tb_state_mem_dw_sel : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE; + unsigned int vtx_tb_status_reg_sel : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE; + } sq_debug_tb_status_sel_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_tb_status_sel_t f; +} sq_debug_tb_status_sel_u; + + +/* + * SQ_DEBUG_VTX_TB_0 struct + */ + +#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE 1 +#define SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE 1 + +#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT 0 +#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT 4 +#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT 8 +#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT 12 +#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT 16 +#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT 20 +#define SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT 21 + +#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK 0x0000000f +#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK 0x000000f0 +#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK 0x00000f00 +#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK 0x0000f000 +#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK 0x000f0000 +#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK 0x00100000 +#define SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK 0x00200000 + +#define SQ_DEBUG_VTX_TB_0_MASK \ + (SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK | \ + SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK | \ + SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK | \ + SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK | \ + SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK | \ + SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK | \ + SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) + +#define SQ_DEBUG_VTX_TB_0(vtx_head_ptr_q, tail_ptr_q, full_cnt_q, nxt_pos_alloc_cnt, nxt_pc_alloc_cnt, sx_event_full, busy_q) \ + ((vtx_head_ptr_q << SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT) | \ + (tail_ptr_q << SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT) | \ + (full_cnt_q << SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT) | \ + (nxt_pos_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT) | \ + (nxt_pc_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT) | \ + (sx_event_full << SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT) | \ + (busy_q << SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT)) + +#define SQ_DEBUG_VTX_TB_0_GET_VTX_HEAD_PTR_Q(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK) >> SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_TAIL_PTR_Q(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK) >> SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_FULL_CNT_Q(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK) >> SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_NXT_POS_ALLOC_CNT(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK) >> SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_NXT_PC_ALLOC_CNT(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK) >> SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_SX_EVENT_FULL(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK) >> SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_BUSY_Q(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) >> SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT) + +#define SQ_DEBUG_VTX_TB_0_SET_VTX_HEAD_PTR_Q(sq_debug_vtx_tb_0_reg, vtx_head_ptr_q) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK) | (vtx_head_ptr_q << SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_TAIL_PTR_Q(sq_debug_vtx_tb_0_reg, tail_ptr_q) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK) | (tail_ptr_q << SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_FULL_CNT_Q(sq_debug_vtx_tb_0_reg, full_cnt_q) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK) | (full_cnt_q << SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_NXT_POS_ALLOC_CNT(sq_debug_vtx_tb_0_reg, nxt_pos_alloc_cnt) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK) | (nxt_pos_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_NXT_PC_ALLOC_CNT(sq_debug_vtx_tb_0_reg, nxt_pc_alloc_cnt) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK) | (nxt_pc_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_SX_EVENT_FULL(sq_debug_vtx_tb_0_reg, sx_event_full) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK) | (sx_event_full << SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_BUSY_Q(sq_debug_vtx_tb_0_reg, busy_q) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) | (busy_q << SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_0_t { + unsigned int vtx_head_ptr_q : SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE; + unsigned int tail_ptr_q : SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE; + unsigned int full_cnt_q : SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE; + unsigned int nxt_pos_alloc_cnt : SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE; + unsigned int nxt_pc_alloc_cnt : SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE; + unsigned int sx_event_full : SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE; + unsigned int busy_q : SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE; + unsigned int : 10; + } sq_debug_vtx_tb_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_0_t { + unsigned int : 10; + unsigned int busy_q : SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE; + unsigned int sx_event_full : SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE; + unsigned int nxt_pc_alloc_cnt : SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE; + unsigned int nxt_pos_alloc_cnt : SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE; + unsigned int full_cnt_q : SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE; + unsigned int tail_ptr_q : SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE; + unsigned int vtx_head_ptr_q : SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE; + } sq_debug_vtx_tb_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_vtx_tb_0_t f; +} sq_debug_vtx_tb_0_u; + + +/* + * SQ_DEBUG_VTX_TB_1 struct + */ + +#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE 16 + +#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT 0 + +#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK 0x0000ffff + +#define SQ_DEBUG_VTX_TB_1_MASK \ + (SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) + +#define SQ_DEBUG_VTX_TB_1(vs_done_ptr) \ + ((vs_done_ptr << SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT)) + +#define SQ_DEBUG_VTX_TB_1_GET_VS_DONE_PTR(sq_debug_vtx_tb_1) \ + ((sq_debug_vtx_tb_1 & SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) >> SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT) + +#define SQ_DEBUG_VTX_TB_1_SET_VS_DONE_PTR(sq_debug_vtx_tb_1_reg, vs_done_ptr) \ + sq_debug_vtx_tb_1_reg = (sq_debug_vtx_tb_1_reg & ~SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) | (vs_done_ptr << SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_1_t { + unsigned int vs_done_ptr : SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE; + unsigned int : 16; + } sq_debug_vtx_tb_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_1_t { + unsigned int : 16; + unsigned int vs_done_ptr : SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE; + } sq_debug_vtx_tb_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_vtx_tb_1_t f; +} sq_debug_vtx_tb_1_u; + + +/* + * SQ_DEBUG_VTX_TB_STATUS_REG struct + */ + +#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE 32 + +#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT 0 + +#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK 0xffffffff + +#define SQ_DEBUG_VTX_TB_STATUS_REG_MASK \ + (SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) + +#define SQ_DEBUG_VTX_TB_STATUS_REG(vs_status_reg) \ + ((vs_status_reg << SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT)) + +#define SQ_DEBUG_VTX_TB_STATUS_REG_GET_VS_STATUS_REG(sq_debug_vtx_tb_status_reg) \ + ((sq_debug_vtx_tb_status_reg & SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) >> SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT) + +#define SQ_DEBUG_VTX_TB_STATUS_REG_SET_VS_STATUS_REG(sq_debug_vtx_tb_status_reg_reg, vs_status_reg) \ + sq_debug_vtx_tb_status_reg_reg = (sq_debug_vtx_tb_status_reg_reg & ~SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) | (vs_status_reg << SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_status_reg_t { + unsigned int vs_status_reg : SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE; + } sq_debug_vtx_tb_status_reg_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_status_reg_t { + unsigned int vs_status_reg : SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE; + } sq_debug_vtx_tb_status_reg_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_vtx_tb_status_reg_t f; +} sq_debug_vtx_tb_status_reg_u; + + +/* + * SQ_DEBUG_VTX_TB_STATE_MEM struct + */ + +#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE 32 + +#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT 0 + +#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK 0xffffffff + +#define SQ_DEBUG_VTX_TB_STATE_MEM_MASK \ + (SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) + +#define SQ_DEBUG_VTX_TB_STATE_MEM(vs_state_mem) \ + ((vs_state_mem << SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT)) + +#define SQ_DEBUG_VTX_TB_STATE_MEM_GET_VS_STATE_MEM(sq_debug_vtx_tb_state_mem) \ + ((sq_debug_vtx_tb_state_mem & SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) >> SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT) + +#define SQ_DEBUG_VTX_TB_STATE_MEM_SET_VS_STATE_MEM(sq_debug_vtx_tb_state_mem_reg, vs_state_mem) \ + sq_debug_vtx_tb_state_mem_reg = (sq_debug_vtx_tb_state_mem_reg & ~SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) | (vs_state_mem << SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_state_mem_t { + unsigned int vs_state_mem : SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE; + } sq_debug_vtx_tb_state_mem_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_state_mem_t { + unsigned int vs_state_mem : SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE; + } sq_debug_vtx_tb_state_mem_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_vtx_tb_state_mem_t f; +} sq_debug_vtx_tb_state_mem_u; + + +/* + * SQ_DEBUG_PIX_TB_0 struct + */ + +#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE 6 +#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE 6 +#define SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE 7 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE 6 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE 6 +#define SQ_DEBUG_PIX_TB_0_BUSY_SIZE 1 + +#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT 0 +#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT 6 +#define SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT 12 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT 19 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT 25 +#define SQ_DEBUG_PIX_TB_0_BUSY_SHIFT 31 + +#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK 0x0000003f +#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK 0x00000fc0 +#define SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK 0x0007f000 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK 0x01f80000 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK 0x7e000000 +#define SQ_DEBUG_PIX_TB_0_BUSY_MASK 0x80000000 + +#define SQ_DEBUG_PIX_TB_0_MASK \ + (SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK | \ + SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK | \ + SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK | \ + SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK | \ + SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK | \ + SQ_DEBUG_PIX_TB_0_BUSY_MASK) + +#define SQ_DEBUG_PIX_TB_0(pix_head_ptr, tail_ptr, full_cnt, nxt_pix_alloc_cnt, nxt_pix_exp_cnt, busy) \ + ((pix_head_ptr << SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT) | \ + (tail_ptr << SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT) | \ + (full_cnt << SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT) | \ + (nxt_pix_alloc_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT) | \ + (nxt_pix_exp_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT) | \ + (busy << SQ_DEBUG_PIX_TB_0_BUSY_SHIFT)) + +#define SQ_DEBUG_PIX_TB_0_GET_PIX_HEAD_PTR(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK) >> SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_TAIL_PTR(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK) >> SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_FULL_CNT(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_NXT_PIX_ALLOC_CNT(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_NXT_PIX_EXP_CNT(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_BUSY(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_BUSY_MASK) >> SQ_DEBUG_PIX_TB_0_BUSY_SHIFT) + +#define SQ_DEBUG_PIX_TB_0_SET_PIX_HEAD_PTR(sq_debug_pix_tb_0_reg, pix_head_ptr) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK) | (pix_head_ptr << SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_TAIL_PTR(sq_debug_pix_tb_0_reg, tail_ptr) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK) | (tail_ptr << SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_FULL_CNT(sq_debug_pix_tb_0_reg, full_cnt) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK) | (full_cnt << SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_NXT_PIX_ALLOC_CNT(sq_debug_pix_tb_0_reg, nxt_pix_alloc_cnt) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK) | (nxt_pix_alloc_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_NXT_PIX_EXP_CNT(sq_debug_pix_tb_0_reg, nxt_pix_exp_cnt) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK) | (nxt_pix_exp_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_BUSY(sq_debug_pix_tb_0_reg, busy) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_BUSY_MASK) | (busy << SQ_DEBUG_PIX_TB_0_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_0_t { + unsigned int pix_head_ptr : SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE; + unsigned int tail_ptr : SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE; + unsigned int full_cnt : SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE; + unsigned int nxt_pix_alloc_cnt : SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE; + unsigned int nxt_pix_exp_cnt : SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE; + unsigned int busy : SQ_DEBUG_PIX_TB_0_BUSY_SIZE; + } sq_debug_pix_tb_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_0_t { + unsigned int busy : SQ_DEBUG_PIX_TB_0_BUSY_SIZE; + unsigned int nxt_pix_exp_cnt : SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE; + unsigned int nxt_pix_alloc_cnt : SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE; + unsigned int full_cnt : SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE; + unsigned int tail_ptr : SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE; + unsigned int pix_head_ptr : SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE; + } sq_debug_pix_tb_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_0_t f; +} sq_debug_pix_tb_0_u; + + +/* + * SQ_DEBUG_PIX_TB_STATUS_REG_0 struct + */ + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_MASK \ + (SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0(pix_tb_status_reg_0) \ + ((pix_tb_status_reg_0 << SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_GET_PIX_TB_STATUS_REG_0(sq_debug_pix_tb_status_reg_0) \ + ((sq_debug_pix_tb_status_reg_0 & SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_SET_PIX_TB_STATUS_REG_0(sq_debug_pix_tb_status_reg_0_reg, pix_tb_status_reg_0) \ + sq_debug_pix_tb_status_reg_0_reg = (sq_debug_pix_tb_status_reg_0_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) | (pix_tb_status_reg_0 << SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_0_t { + unsigned int pix_tb_status_reg_0 : SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE; + } sq_debug_pix_tb_status_reg_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_0_t { + unsigned int pix_tb_status_reg_0 : SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE; + } sq_debug_pix_tb_status_reg_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_status_reg_0_t f; +} sq_debug_pix_tb_status_reg_0_u; + + +/* + * SQ_DEBUG_PIX_TB_STATUS_REG_1 struct + */ + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_MASK \ + (SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1(pix_tb_status_reg_1) \ + ((pix_tb_status_reg_1 << SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_GET_PIX_TB_STATUS_REG_1(sq_debug_pix_tb_status_reg_1) \ + ((sq_debug_pix_tb_status_reg_1 & SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_SET_PIX_TB_STATUS_REG_1(sq_debug_pix_tb_status_reg_1_reg, pix_tb_status_reg_1) \ + sq_debug_pix_tb_status_reg_1_reg = (sq_debug_pix_tb_status_reg_1_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) | (pix_tb_status_reg_1 << SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_1_t { + unsigned int pix_tb_status_reg_1 : SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE; + } sq_debug_pix_tb_status_reg_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_1_t { + unsigned int pix_tb_status_reg_1 : SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE; + } sq_debug_pix_tb_status_reg_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_status_reg_1_t f; +} sq_debug_pix_tb_status_reg_1_u; + + +/* + * SQ_DEBUG_PIX_TB_STATUS_REG_2 struct + */ + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_MASK \ + (SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2(pix_tb_status_reg_2) \ + ((pix_tb_status_reg_2 << SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_GET_PIX_TB_STATUS_REG_2(sq_debug_pix_tb_status_reg_2) \ + ((sq_debug_pix_tb_status_reg_2 & SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_SET_PIX_TB_STATUS_REG_2(sq_debug_pix_tb_status_reg_2_reg, pix_tb_status_reg_2) \ + sq_debug_pix_tb_status_reg_2_reg = (sq_debug_pix_tb_status_reg_2_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) | (pix_tb_status_reg_2 << SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_2_t { + unsigned int pix_tb_status_reg_2 : SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE; + } sq_debug_pix_tb_status_reg_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_2_t { + unsigned int pix_tb_status_reg_2 : SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE; + } sq_debug_pix_tb_status_reg_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_status_reg_2_t f; +} sq_debug_pix_tb_status_reg_2_u; + + +/* + * SQ_DEBUG_PIX_TB_STATUS_REG_3 struct + */ + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_MASK \ + (SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3(pix_tb_status_reg_3) \ + ((pix_tb_status_reg_3 << SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_GET_PIX_TB_STATUS_REG_3(sq_debug_pix_tb_status_reg_3) \ + ((sq_debug_pix_tb_status_reg_3 & SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_SET_PIX_TB_STATUS_REG_3(sq_debug_pix_tb_status_reg_3_reg, pix_tb_status_reg_3) \ + sq_debug_pix_tb_status_reg_3_reg = (sq_debug_pix_tb_status_reg_3_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) | (pix_tb_status_reg_3 << SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_3_t { + unsigned int pix_tb_status_reg_3 : SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE; + } sq_debug_pix_tb_status_reg_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_3_t { + unsigned int pix_tb_status_reg_3 : SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE; + } sq_debug_pix_tb_status_reg_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_status_reg_3_t f; +} sq_debug_pix_tb_status_reg_3_u; + + +/* + * SQ_DEBUG_PIX_TB_STATE_MEM struct + */ + +#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATE_MEM_MASK \ + (SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) + +#define SQ_DEBUG_PIX_TB_STATE_MEM(pix_tb_state_mem) \ + ((pix_tb_state_mem << SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATE_MEM_GET_PIX_TB_STATE_MEM(sq_debug_pix_tb_state_mem) \ + ((sq_debug_pix_tb_state_mem & SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) >> SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATE_MEM_SET_PIX_TB_STATE_MEM(sq_debug_pix_tb_state_mem_reg, pix_tb_state_mem) \ + sq_debug_pix_tb_state_mem_reg = (sq_debug_pix_tb_state_mem_reg & ~SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) | (pix_tb_state_mem << SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_state_mem_t { + unsigned int pix_tb_state_mem : SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE; + } sq_debug_pix_tb_state_mem_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_state_mem_t { + unsigned int pix_tb_state_mem : SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE; + } sq_debug_pix_tb_state_mem_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_state_mem_t f; +} sq_debug_pix_tb_state_mem_u; + + +/* + * SQ_PERFCOUNTER0_SELECT struct + */ + +#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define SQ_PERFCOUNTER0_SELECT_MASK \ + (SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define SQ_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define SQ_PERFCOUNTER0_SELECT_GET_PERF_SEL(sq_perfcounter0_select) \ + ((sq_perfcounter0_select & SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define SQ_PERFCOUNTER0_SELECT_SET_PERF_SEL(sq_perfcounter0_select_reg, perf_sel) \ + sq_perfcounter0_select_reg = (sq_perfcounter0_select_reg & ~SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter0_select_t { + unsigned int perf_sel : SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sq_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } sq_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter0_select_t f; +} sq_perfcounter0_select_u; + + +/* + * SQ_PERFCOUNTER1_SELECT struct + */ + +#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8 + +#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0 + +#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff + +#define SQ_PERFCOUNTER1_SELECT_MASK \ + (SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) + +#define SQ_PERFCOUNTER1_SELECT(perf_sel) \ + ((perf_sel << SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)) + +#define SQ_PERFCOUNTER1_SELECT_GET_PERF_SEL(sq_perfcounter1_select) \ + ((sq_perfcounter1_select & SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#define SQ_PERFCOUNTER1_SELECT_SET_PERF_SEL(sq_perfcounter1_select_reg, perf_sel) \ + sq_perfcounter1_select_reg = (sq_perfcounter1_select_reg & ~SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter1_select_t { + unsigned int perf_sel : SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sq_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter1_select_t { + unsigned int : 24; + unsigned int perf_sel : SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + } sq_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter1_select_t f; +} sq_perfcounter1_select_u; + + +/* + * SQ_PERFCOUNTER2_SELECT struct + */ + +#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8 + +#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0 + +#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff + +#define SQ_PERFCOUNTER2_SELECT_MASK \ + (SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) + +#define SQ_PERFCOUNTER2_SELECT(perf_sel) \ + ((perf_sel << SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)) + +#define SQ_PERFCOUNTER2_SELECT_GET_PERF_SEL(sq_perfcounter2_select) \ + ((sq_perfcounter2_select & SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#define SQ_PERFCOUNTER2_SELECT_SET_PERF_SEL(sq_perfcounter2_select_reg, perf_sel) \ + sq_perfcounter2_select_reg = (sq_perfcounter2_select_reg & ~SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter2_select_t { + unsigned int perf_sel : SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sq_perfcounter2_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter2_select_t { + unsigned int : 24; + unsigned int perf_sel : SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + } sq_perfcounter2_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter2_select_t f; +} sq_perfcounter2_select_u; + + +/* + * SQ_PERFCOUNTER3_SELECT struct + */ + +#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8 + +#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0 + +#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff + +#define SQ_PERFCOUNTER3_SELECT_MASK \ + (SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) + +#define SQ_PERFCOUNTER3_SELECT(perf_sel) \ + ((perf_sel << SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)) + +#define SQ_PERFCOUNTER3_SELECT_GET_PERF_SEL(sq_perfcounter3_select) \ + ((sq_perfcounter3_select & SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#define SQ_PERFCOUNTER3_SELECT_SET_PERF_SEL(sq_perfcounter3_select_reg, perf_sel) \ + sq_perfcounter3_select_reg = (sq_perfcounter3_select_reg & ~SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter3_select_t { + unsigned int perf_sel : SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sq_perfcounter3_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter3_select_t { + unsigned int : 24; + unsigned int perf_sel : SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + } sq_perfcounter3_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter3_select_t f; +} sq_perfcounter3_select_u; + + +/* + * SQ_PERFCOUNTER0_LOW struct + */ + +#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define SQ_PERFCOUNTER0_LOW_MASK \ + (SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER0_LOW_GET_PERF_COUNT(sq_perfcounter0_low) \ + ((sq_perfcounter0_low & SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER0_LOW_SET_PERF_COUNT(sq_perfcounter0_low_reg, perf_count) \ + sq_perfcounter0_low_reg = (sq_perfcounter0_low_reg & ~SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter0_low_t { + unsigned int perf_count : SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } sq_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter0_low_t { + unsigned int perf_count : SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } sq_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter0_low_t f; +} sq_perfcounter0_low_u; + + +/* + * SQ_PERFCOUNTER0_HI struct + */ + +#define SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define SQ_PERFCOUNTER0_HI_MASK \ + (SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER0_HI_GET_PERF_COUNT(sq_perfcounter0_hi) \ + ((sq_perfcounter0_hi & SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER0_HI_SET_PERF_COUNT(sq_perfcounter0_hi_reg, perf_count) \ + sq_perfcounter0_hi_reg = (sq_perfcounter0_hi_reg & ~SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter0_hi_t { + unsigned int perf_count : SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sq_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } sq_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter0_hi_t f; +} sq_perfcounter0_hi_u; + + +/* + * SQ_PERFCOUNTER1_LOW struct + */ + +#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32 + +#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff + +#define SQ_PERFCOUNTER1_LOW_MASK \ + (SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER1_LOW(perf_count) \ + ((perf_count << SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER1_LOW_GET_PERF_COUNT(sq_perfcounter1_low) \ + ((sq_perfcounter1_low & SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER1_LOW_SET_PERF_COUNT(sq_perfcounter1_low_reg, perf_count) \ + sq_perfcounter1_low_reg = (sq_perfcounter1_low_reg & ~SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter1_low_t { + unsigned int perf_count : SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } sq_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter1_low_t { + unsigned int perf_count : SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } sq_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter1_low_t f; +} sq_perfcounter1_low_u; + + +/* + * SQ_PERFCOUNTER1_HI struct + */ + +#define SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16 + +#define SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff + +#define SQ_PERFCOUNTER1_HI_MASK \ + (SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER1_HI(perf_count) \ + ((perf_count << SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER1_HI_GET_PERF_COUNT(sq_perfcounter1_hi) \ + ((sq_perfcounter1_hi & SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER1_HI_SET_PERF_COUNT(sq_perfcounter1_hi_reg, perf_count) \ + sq_perfcounter1_hi_reg = (sq_perfcounter1_hi_reg & ~SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter1_hi_t { + unsigned int perf_count : SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sq_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_count : SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + } sq_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter1_hi_t f; +} sq_perfcounter1_hi_u; + + +/* + * SQ_PERFCOUNTER2_LOW struct + */ + +#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32 + +#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff + +#define SQ_PERFCOUNTER2_LOW_MASK \ + (SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER2_LOW(perf_count) \ + ((perf_count << SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER2_LOW_GET_PERF_COUNT(sq_perfcounter2_low) \ + ((sq_perfcounter2_low & SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER2_LOW_SET_PERF_COUNT(sq_perfcounter2_low_reg, perf_count) \ + sq_perfcounter2_low_reg = (sq_perfcounter2_low_reg & ~SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter2_low_t { + unsigned int perf_count : SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } sq_perfcounter2_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter2_low_t { + unsigned int perf_count : SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } sq_perfcounter2_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter2_low_t f; +} sq_perfcounter2_low_u; + + +/* + * SQ_PERFCOUNTER2_HI struct + */ + +#define SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16 + +#define SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff + +#define SQ_PERFCOUNTER2_HI_MASK \ + (SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER2_HI(perf_count) \ + ((perf_count << SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER2_HI_GET_PERF_COUNT(sq_perfcounter2_hi) \ + ((sq_perfcounter2_hi & SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER2_HI_SET_PERF_COUNT(sq_perfcounter2_hi_reg, perf_count) \ + sq_perfcounter2_hi_reg = (sq_perfcounter2_hi_reg & ~SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter2_hi_t { + unsigned int perf_count : SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sq_perfcounter2_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter2_hi_t { + unsigned int : 16; + unsigned int perf_count : SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + } sq_perfcounter2_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter2_hi_t f; +} sq_perfcounter2_hi_u; + + +/* + * SQ_PERFCOUNTER3_LOW struct + */ + +#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32 + +#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff + +#define SQ_PERFCOUNTER3_LOW_MASK \ + (SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER3_LOW(perf_count) \ + ((perf_count << SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER3_LOW_GET_PERF_COUNT(sq_perfcounter3_low) \ + ((sq_perfcounter3_low & SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER3_LOW_SET_PERF_COUNT(sq_perfcounter3_low_reg, perf_count) \ + sq_perfcounter3_low_reg = (sq_perfcounter3_low_reg & ~SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter3_low_t { + unsigned int perf_count : SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } sq_perfcounter3_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter3_low_t { + unsigned int perf_count : SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } sq_perfcounter3_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter3_low_t f; +} sq_perfcounter3_low_u; + + +/* + * SQ_PERFCOUNTER3_HI struct + */ + +#define SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16 + +#define SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff + +#define SQ_PERFCOUNTER3_HI_MASK \ + (SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER3_HI(perf_count) \ + ((perf_count << SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER3_HI_GET_PERF_COUNT(sq_perfcounter3_hi) \ + ((sq_perfcounter3_hi & SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER3_HI_SET_PERF_COUNT(sq_perfcounter3_hi_reg, perf_count) \ + sq_perfcounter3_hi_reg = (sq_perfcounter3_hi_reg & ~SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter3_hi_t { + unsigned int perf_count : SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sq_perfcounter3_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter3_hi_t { + unsigned int : 16; + unsigned int perf_count : SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + } sq_perfcounter3_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter3_hi_t f; +} sq_perfcounter3_hi_u; + + +/* + * SX_PERFCOUNTER0_SELECT struct + */ + +#define SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define SX_PERFCOUNTER0_SELECT_MASK \ + (SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define SX_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define SX_PERFCOUNTER0_SELECT_GET_PERF_SEL(sx_perfcounter0_select) \ + ((sx_perfcounter0_select & SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define SX_PERFCOUNTER0_SELECT_SET_PERF_SEL(sx_perfcounter0_select_reg, perf_sel) \ + sx_perfcounter0_select_reg = (sx_perfcounter0_select_reg & ~SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sx_perfcounter0_select_t { + unsigned int perf_sel : SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sx_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sx_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } sx_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sx_perfcounter0_select_t f; +} sx_perfcounter0_select_u; + + +/* + * SX_PERFCOUNTER0_LOW struct + */ + +#define SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define SX_PERFCOUNTER0_LOW_MASK \ + (SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define SX_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define SX_PERFCOUNTER0_LOW_GET_PERF_COUNT(sx_perfcounter0_low) \ + ((sx_perfcounter0_low & SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define SX_PERFCOUNTER0_LOW_SET_PERF_COUNT(sx_perfcounter0_low_reg, perf_count) \ + sx_perfcounter0_low_reg = (sx_perfcounter0_low_reg & ~SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sx_perfcounter0_low_t { + unsigned int perf_count : SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } sx_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sx_perfcounter0_low_t { + unsigned int perf_count : SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } sx_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sx_perfcounter0_low_t f; +} sx_perfcounter0_low_u; + + +/* + * SX_PERFCOUNTER0_HI struct + */ + +#define SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define SX_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define SX_PERFCOUNTER0_HI_MASK \ + (SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define SX_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define SX_PERFCOUNTER0_HI_GET_PERF_COUNT(sx_perfcounter0_hi) \ + ((sx_perfcounter0_hi & SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define SX_PERFCOUNTER0_HI_SET_PERF_COUNT(sx_perfcounter0_hi_reg, perf_count) \ + sx_perfcounter0_hi_reg = (sx_perfcounter0_hi_reg & ~SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sx_perfcounter0_hi_t { + unsigned int perf_count : SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sx_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sx_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } sx_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sx_perfcounter0_hi_t f; +} sx_perfcounter0_hi_u; + + +/* + * SQ_INSTRUCTION_ALU_0 struct + */ + +#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE 6 +#define SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE 6 +#define SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE 4 +#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE 4 +#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE 6 + +#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT 0 +#define SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_SHIFT 6 +#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT 7 +#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT 8 +#define SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_SHIFT 14 +#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT 15 +#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT 16 +#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT 20 +#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT 24 +#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT 25 +#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT 26 + +#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK 0x0000003f +#define SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_MASK 0x00000040 +#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK 0x00000080 +#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK 0x00003f00 +#define SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_MASK 0x00004000 +#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK 0x00008000 +#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK 0x000f0000 +#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK 0x00f00000 +#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK 0x01000000 +#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK 0x02000000 +#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK 0xfc000000 + +#define SQ_INSTRUCTION_ALU_0_MASK \ + (SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK | \ + SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_MASK | \ + SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK | \ + SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK | \ + SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_MASK | \ + SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK | \ + SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK | \ + SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK | \ + SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK | \ + SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK | \ + SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) + +#define SQ_INSTRUCTION_ALU_0(vector_result, cst_0_abs_mod, low_precision_16b_fp, scalar_result, sst_0_abs_mod, export_data, vector_wrt_msk, scalar_wrt_msk, vector_clamp, scalar_clamp, scalar_opcode) \ + ((vector_result << SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT) | \ + (cst_0_abs_mod << SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_SHIFT) | \ + (low_precision_16b_fp << SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT) | \ + (scalar_result << SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT) | \ + (sst_0_abs_mod << SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_SHIFT) | \ + (export_data << SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT) | \ + (vector_wrt_msk << SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT) | \ + (scalar_wrt_msk << SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT) | \ + (vector_clamp << SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT) | \ + (scalar_clamp << SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT) | \ + (scalar_opcode << SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_RESULT(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_CST_0_ABS_MOD(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_MASK) >> SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_LOW_PRECISION_16B_FP(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK) >> SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_RESULT(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SST_0_ABS_MOD(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_MASK) >> SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_EXPORT_DATA(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK) >> SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_WRT_MSK(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_WRT_MSK(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_CLAMP(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_CLAMP(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_OPCODE(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_RESULT(sq_instruction_alu_0_reg, vector_result) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK) | (vector_result << SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_CST_0_ABS_MOD(sq_instruction_alu_0_reg, cst_0_abs_mod) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_MASK) | (cst_0_abs_mod << SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_LOW_PRECISION_16B_FP(sq_instruction_alu_0_reg, low_precision_16b_fp) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK) | (low_precision_16b_fp << SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_RESULT(sq_instruction_alu_0_reg, scalar_result) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK) | (scalar_result << SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SST_0_ABS_MOD(sq_instruction_alu_0_reg, sst_0_abs_mod) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_MASK) | (sst_0_abs_mod << SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_EXPORT_DATA(sq_instruction_alu_0_reg, export_data) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK) | (export_data << SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_WRT_MSK(sq_instruction_alu_0_reg, vector_wrt_msk) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK) | (vector_wrt_msk << SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_WRT_MSK(sq_instruction_alu_0_reg, scalar_wrt_msk) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK) | (scalar_wrt_msk << SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_CLAMP(sq_instruction_alu_0_reg, vector_clamp) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK) | (vector_clamp << SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_CLAMP(sq_instruction_alu_0_reg, scalar_clamp) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK) | (scalar_clamp << SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_OPCODE(sq_instruction_alu_0_reg, scalar_opcode) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) | (scalar_opcode << SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_alu_0_t { + unsigned int vector_result : SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE; + unsigned int cst_0_abs_mod : SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_SIZE; + unsigned int low_precision_16b_fp : SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE; + unsigned int scalar_result : SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE; + unsigned int sst_0_abs_mod : SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_SIZE; + unsigned int export_data : SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE; + unsigned int vector_wrt_msk : SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE; + unsigned int scalar_wrt_msk : SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE; + unsigned int vector_clamp : SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE; + unsigned int scalar_clamp : SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE; + unsigned int scalar_opcode : SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE; + } sq_instruction_alu_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_alu_0_t { + unsigned int scalar_opcode : SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE; + unsigned int scalar_clamp : SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE; + unsigned int vector_clamp : SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE; + unsigned int scalar_wrt_msk : SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE; + unsigned int vector_wrt_msk : SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE; + unsigned int export_data : SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE; + unsigned int sst_0_abs_mod : SQ_INSTRUCTION_ALU_0_SST_0_ABS_MOD_SIZE; + unsigned int scalar_result : SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE; + unsigned int low_precision_16b_fp : SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE; + unsigned int cst_0_abs_mod : SQ_INSTRUCTION_ALU_0_CST_0_ABS_MOD_SIZE; + unsigned int vector_result : SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE; + } sq_instruction_alu_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_alu_0_t f; +} sq_instruction_alu_0_u; + + +/* + * SQ_INSTRUCTION_ALU_1 struct + */ + +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE 1 + +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT 0 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT 4 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT 6 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT 8 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT 10 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT 12 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT 14 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT 16 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT 18 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT 20 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT 22 +#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT 24 +#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT 25 +#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT 26 +#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT 27 +#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT 29 +#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT 30 +#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT 31 + +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK 0x00000003 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK 0x0000000c +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK 0x00000030 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK 0x000000c0 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK 0x00000300 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK 0x00000c00 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK 0x00003000 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK 0x0000c000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK 0x00030000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK 0x000c0000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK 0x00300000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK 0x00c00000 +#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK 0x01000000 +#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK 0x02000000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK 0x04000000 +#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK 0x18000000 +#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK 0x20000000 +#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK 0x40000000 +#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK 0x80000000 + +#define SQ_INSTRUCTION_ALU_1_MASK \ + (SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK | \ + SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK | \ + SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK | \ + SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK | \ + SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) + +#define SQ_INSTRUCTION_ALU_1(src_c_swizzle_r, src_c_swizzle_g, src_c_swizzle_b, src_c_swizzle_a, src_b_swizzle_r, src_b_swizzle_g, src_b_swizzle_b, src_b_swizzle_a, src_a_swizzle_r, src_a_swizzle_g, src_a_swizzle_b, src_a_swizzle_a, src_c_arg_mod, src_b_arg_mod, src_a_arg_mod, pred_select, relative_addr, const_1_rel_abs, const_0_rel_abs) \ + ((src_c_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT) | \ + (src_c_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT) | \ + (src_c_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT) | \ + (src_c_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT) | \ + (src_b_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT) | \ + (src_b_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT) | \ + (src_b_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT) | \ + (src_b_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT) | \ + (src_a_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT) | \ + (src_a_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT) | \ + (src_a_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT) | \ + (src_a_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT) | \ + (src_c_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT) | \ + (src_b_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT) | \ + (src_a_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT) | \ + (pred_select << SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT) | \ + (relative_addr << SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT) | \ + (const_1_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT) | \ + (const_0_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT)) + +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_R(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_G(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_B(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_A(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_R(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_G(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_B(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_A(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_R(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_G(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_B(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_A(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_ARG_MOD(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_ARG_MOD(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_ARG_MOD(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_PRED_SELECT(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_RELATIVE_ADDR(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK) >> SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_CONST_1_REL_ABS(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK) >> SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_CONST_0_REL_ABS(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) >> SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT) + +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_R(sq_instruction_alu_1_reg, src_c_swizzle_r) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK) | (src_c_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_G(sq_instruction_alu_1_reg, src_c_swizzle_g) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK) | (src_c_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_B(sq_instruction_alu_1_reg, src_c_swizzle_b) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK) | (src_c_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_A(sq_instruction_alu_1_reg, src_c_swizzle_a) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK) | (src_c_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_R(sq_instruction_alu_1_reg, src_b_swizzle_r) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK) | (src_b_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_G(sq_instruction_alu_1_reg, src_b_swizzle_g) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK) | (src_b_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_B(sq_instruction_alu_1_reg, src_b_swizzle_b) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK) | (src_b_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_A(sq_instruction_alu_1_reg, src_b_swizzle_a) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK) | (src_b_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_R(sq_instruction_alu_1_reg, src_a_swizzle_r) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK) | (src_a_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_G(sq_instruction_alu_1_reg, src_a_swizzle_g) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK) | (src_a_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_B(sq_instruction_alu_1_reg, src_a_swizzle_b) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK) | (src_a_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_A(sq_instruction_alu_1_reg, src_a_swizzle_a) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK) | (src_a_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_ARG_MOD(sq_instruction_alu_1_reg, src_c_arg_mod) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK) | (src_c_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_ARG_MOD(sq_instruction_alu_1_reg, src_b_arg_mod) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK) | (src_b_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_ARG_MOD(sq_instruction_alu_1_reg, src_a_arg_mod) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK) | (src_a_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_PRED_SELECT(sq_instruction_alu_1_reg, pred_select) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_RELATIVE_ADDR(sq_instruction_alu_1_reg, relative_addr) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK) | (relative_addr << SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_CONST_1_REL_ABS(sq_instruction_alu_1_reg, const_1_rel_abs) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK) | (const_1_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_CONST_0_REL_ABS(sq_instruction_alu_1_reg, const_0_rel_abs) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) | (const_0_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_alu_1_t { + unsigned int src_c_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE; + unsigned int src_c_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE; + unsigned int src_c_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE; + unsigned int src_c_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE; + unsigned int src_b_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE; + unsigned int src_b_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE; + unsigned int src_b_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE; + unsigned int src_b_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE; + unsigned int src_a_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE; + unsigned int src_a_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE; + unsigned int src_a_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE; + unsigned int src_a_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE; + unsigned int src_c_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE; + unsigned int src_b_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE; + unsigned int src_a_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE; + unsigned int pred_select : SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE; + unsigned int relative_addr : SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE; + unsigned int const_1_rel_abs : SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE; + unsigned int const_0_rel_abs : SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE; + } sq_instruction_alu_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_alu_1_t { + unsigned int const_0_rel_abs : SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE; + unsigned int const_1_rel_abs : SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE; + unsigned int relative_addr : SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE; + unsigned int pred_select : SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE; + unsigned int src_a_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE; + unsigned int src_b_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE; + unsigned int src_c_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE; + unsigned int src_a_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE; + unsigned int src_a_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE; + unsigned int src_a_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE; + unsigned int src_a_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE; + unsigned int src_b_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE; + unsigned int src_b_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE; + unsigned int src_b_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE; + unsigned int src_b_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE; + unsigned int src_c_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE; + unsigned int src_c_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE; + unsigned int src_c_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE; + unsigned int src_c_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE; + } sq_instruction_alu_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_alu_1_t f; +} sq_instruction_alu_1_u; + + +/* + * SQ_INSTRUCTION_ALU_2 struct + */ + +#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE 6 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE 6 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE 6 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE 5 +#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE 1 + +#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT 0 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT 6 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT 7 +#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT 8 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT 14 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT 15 +#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT 16 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT 22 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT 23 +#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT 24 +#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT 29 +#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT 30 +#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT 31 + +#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK 0x0000003f +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK 0x00000040 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK 0x00000080 +#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK 0x00003f00 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK 0x00004000 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK 0x00008000 +#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK 0x003f0000 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK 0x00400000 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK 0x00800000 +#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK 0x1f000000 +#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK 0x20000000 +#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK 0x40000000 +#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK 0x80000000 + +#define SQ_INSTRUCTION_ALU_2_MASK \ + (SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK | \ + SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) + +#define SQ_INSTRUCTION_ALU_2(src_c_reg_ptr, reg_select_c, reg_abs_mod_c, src_b_reg_ptr, reg_select_b, reg_abs_mod_b, src_a_reg_ptr, reg_select_a, reg_abs_mod_a, vector_opcode, src_c_sel, src_b_sel, src_a_sel) \ + ((src_c_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT) | \ + (reg_select_c << SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT) | \ + (reg_abs_mod_c << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT) | \ + (src_b_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT) | \ + (reg_select_b << SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT) | \ + (reg_abs_mod_b << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT) | \ + (src_a_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT) | \ + (reg_select_a << SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT) | \ + (reg_abs_mod_a << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT) | \ + (vector_opcode << SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT) | \ + (src_c_sel << SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT) | \ + (src_b_sel << SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT) | \ + (src_a_sel << SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT)) + +#define SQ_INSTRUCTION_ALU_2_GET_SRC_C_REG_PTR(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_C(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_C(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_B_REG_PTR(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_B(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_B(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_A_REG_PTR(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_A(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_A(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_VECTOR_OPCODE(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK) >> SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_C_SEL(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_B_SEL(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_A_SEL(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT) + +#define SQ_INSTRUCTION_ALU_2_SET_SRC_C_REG_PTR(sq_instruction_alu_2_reg, src_c_reg_ptr) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK) | (src_c_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_C(sq_instruction_alu_2_reg, reg_select_c) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK) | (reg_select_c << SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_C(sq_instruction_alu_2_reg, reg_abs_mod_c) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK) | (reg_abs_mod_c << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_B_REG_PTR(sq_instruction_alu_2_reg, src_b_reg_ptr) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK) | (src_b_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_B(sq_instruction_alu_2_reg, reg_select_b) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK) | (reg_select_b << SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_B(sq_instruction_alu_2_reg, reg_abs_mod_b) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK) | (reg_abs_mod_b << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_A_REG_PTR(sq_instruction_alu_2_reg, src_a_reg_ptr) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK) | (src_a_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_A(sq_instruction_alu_2_reg, reg_select_a) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK) | (reg_select_a << SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_A(sq_instruction_alu_2_reg, reg_abs_mod_a) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK) | (reg_abs_mod_a << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_VECTOR_OPCODE(sq_instruction_alu_2_reg, vector_opcode) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK) | (vector_opcode << SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_C_SEL(sq_instruction_alu_2_reg, src_c_sel) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK) | (src_c_sel << SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_B_SEL(sq_instruction_alu_2_reg, src_b_sel) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK) | (src_b_sel << SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_A_SEL(sq_instruction_alu_2_reg, src_a_sel) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) | (src_a_sel << SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_alu_2_t { + unsigned int src_c_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE; + unsigned int reg_select_c : SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE; + unsigned int reg_abs_mod_c : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE; + unsigned int src_b_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE; + unsigned int reg_select_b : SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE; + unsigned int reg_abs_mod_b : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE; + unsigned int src_a_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE; + unsigned int reg_select_a : SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE; + unsigned int reg_abs_mod_a : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE; + unsigned int vector_opcode : SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE; + unsigned int src_c_sel : SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE; + unsigned int src_b_sel : SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE; + unsigned int src_a_sel : SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE; + } sq_instruction_alu_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_alu_2_t { + unsigned int src_a_sel : SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE; + unsigned int src_b_sel : SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE; + unsigned int src_c_sel : SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE; + unsigned int vector_opcode : SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE; + unsigned int reg_abs_mod_a : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE; + unsigned int reg_select_a : SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE; + unsigned int src_a_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE; + unsigned int reg_abs_mod_b : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE; + unsigned int reg_select_b : SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE; + unsigned int src_b_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE; + unsigned int reg_abs_mod_c : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE; + unsigned int reg_select_c : SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE; + unsigned int src_c_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE; + } sq_instruction_alu_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_alu_2_t f; +} sq_instruction_alu_2_u; + + +/* + * SQ_INSTRUCTION_CF_EXEC_0 struct + */ + +#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE 9 +#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE 3 +#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE 3 +#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE 1 + +#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT 0 +#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT 9 +#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT 12 +#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT 15 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT 16 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT 17 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT 18 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT 19 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT 20 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT 21 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT 22 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT 23 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT 24 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT 25 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT 26 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT 27 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT 28 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT 29 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT 30 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT 31 + +#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK 0x000001ff +#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK 0x00000e00 +#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK 0x00007000 +#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK 0x00008000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK 0x00010000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK 0x00020000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK 0x00040000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK 0x00080000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK 0x00100000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK 0x00200000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK 0x00400000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK 0x00800000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK 0x01000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK 0x02000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK 0x04000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK 0x10000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK 0x20000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK 0x40000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK 0x80000000 + +#define SQ_INSTRUCTION_CF_EXEC_0_MASK \ + (SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) + +#define SQ_INSTRUCTION_CF_EXEC_0(address, reserved, count, yield, inst_type_0, inst_serial_0, inst_type_1, inst_serial_1, inst_type_2, inst_serial_2, inst_type_3, inst_serial_3, inst_type_4, inst_serial_4, inst_type_5, inst_serial_5, inst_vc_0, inst_vc_1, inst_vc_2, inst_vc_3) \ + ((address << SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT) | \ + (reserved << SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT) | \ + (count << SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT) | \ + (yield << SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT) | \ + (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT) | \ + (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT) | \ + (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT) | \ + (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT) | \ + (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT) | \ + (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT) | \ + (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT) | \ + (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT) | \ + (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT) | \ + (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT) | \ + (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT) | \ + (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT) | \ + (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT) | \ + (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT) | \ + (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT) | \ + (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT)) + +#define SQ_INSTRUCTION_CF_EXEC_0_GET_ADDRESS(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_RESERVED(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_COUNT(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_YIELD(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_0(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_0(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_1(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_1(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_2(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_2(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_3(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_3(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_4(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_4(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_5(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_5(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_0(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_1(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_2(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_3(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT) + +#define SQ_INSTRUCTION_CF_EXEC_0_SET_ADDRESS(sq_instruction_cf_exec_0_reg, address) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_RESERVED(sq_instruction_cf_exec_0_reg, reserved) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_COUNT(sq_instruction_cf_exec_0_reg, count) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK) | (count << SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_YIELD(sq_instruction_cf_exec_0_reg, yield) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK) | (yield << SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_0(sq_instruction_cf_exec_0_reg, inst_type_0) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK) | (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_0(sq_instruction_cf_exec_0_reg, inst_serial_0) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK) | (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_1(sq_instruction_cf_exec_0_reg, inst_type_1) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK) | (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_1(sq_instruction_cf_exec_0_reg, inst_serial_1) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK) | (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_2(sq_instruction_cf_exec_0_reg, inst_type_2) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK) | (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_2(sq_instruction_cf_exec_0_reg, inst_serial_2) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK) | (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_3(sq_instruction_cf_exec_0_reg, inst_type_3) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK) | (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_3(sq_instruction_cf_exec_0_reg, inst_serial_3) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK) | (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_4(sq_instruction_cf_exec_0_reg, inst_type_4) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK) | (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_4(sq_instruction_cf_exec_0_reg, inst_serial_4) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK) | (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_5(sq_instruction_cf_exec_0_reg, inst_type_5) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK) | (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_5(sq_instruction_cf_exec_0_reg, inst_serial_5) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK) | (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_0(sq_instruction_cf_exec_0_reg, inst_vc_0) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK) | (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_1(sq_instruction_cf_exec_0_reg, inst_vc_1) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK) | (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_2(sq_instruction_cf_exec_0_reg, inst_vc_2) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK) | (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_3(sq_instruction_cf_exec_0_reg, inst_vc_3) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) | (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_0_t { + unsigned int address : SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE; + unsigned int count : SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE; + unsigned int yield : SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE; + unsigned int inst_type_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE; + unsigned int inst_serial_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE; + unsigned int inst_type_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE; + unsigned int inst_serial_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE; + unsigned int inst_type_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE; + unsigned int inst_serial_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE; + unsigned int inst_type_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE; + unsigned int inst_serial_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE; + unsigned int inst_type_4 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE; + unsigned int inst_serial_4 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE; + unsigned int inst_type_5 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE; + unsigned int inst_serial_5 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE; + unsigned int inst_vc_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE; + unsigned int inst_vc_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE; + unsigned int inst_vc_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE; + unsigned int inst_vc_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE; + } sq_instruction_cf_exec_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_0_t { + unsigned int inst_vc_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE; + unsigned int inst_vc_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE; + unsigned int inst_vc_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE; + unsigned int inst_vc_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE; + unsigned int inst_serial_5 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE; + unsigned int inst_type_5 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE; + unsigned int inst_serial_4 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE; + unsigned int inst_type_4 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE; + unsigned int inst_serial_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE; + unsigned int inst_type_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE; + unsigned int inst_serial_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE; + unsigned int inst_type_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE; + unsigned int inst_serial_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE; + unsigned int inst_type_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE; + unsigned int inst_serial_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE; + unsigned int inst_type_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE; + unsigned int yield : SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE; + unsigned int count : SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE; + } sq_instruction_cf_exec_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_exec_0_t f; +} sq_instruction_cf_exec_0_u; + + +/* + * SQ_INSTRUCTION_CF_EXEC_1 struct + */ + +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE 8 +#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE 4 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE 9 +#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE 3 +#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE 3 +#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE 1 + +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT 0 +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT 1 +#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT 2 +#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT 10 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT 11 +#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT 12 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT 16 +#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT 25 +#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT 28 +#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT 31 + +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK 0x00000001 +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK 0x00000002 +#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK 0x000003fc +#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK 0x00000400 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK 0x0000f000 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK 0x01ff0000 +#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK 0x0e000000 +#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK 0x70000000 +#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK 0x80000000 + +#define SQ_INSTRUCTION_CF_EXEC_1_MASK \ + (SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) + +#define SQ_INSTRUCTION_CF_EXEC_1(inst_vc_4, inst_vc_5, bool_addr, condition, address_mode, opcode, address, reserved, count, yield) \ + ((inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT) | \ + (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT) | \ + (bool_addr << SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT) | \ + (condition << SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT) | \ + (address << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT) | \ + (reserved << SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT) | \ + (count << SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT) | \ + (yield << SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT)) + +#define SQ_INSTRUCTION_CF_EXEC_1_GET_INST_VC_4(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_INST_VC_5(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_BOOL_ADDR(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_CONDITION(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_ADDRESS_MODE(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_OPCODE(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_ADDRESS(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_RESERVED(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_COUNT(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_YIELD(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT) + +#define SQ_INSTRUCTION_CF_EXEC_1_SET_INST_VC_4(sq_instruction_cf_exec_1_reg, inst_vc_4) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK) | (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_INST_VC_5(sq_instruction_cf_exec_1_reg, inst_vc_5) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK) | (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_BOOL_ADDR(sq_instruction_cf_exec_1_reg, bool_addr) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_CONDITION(sq_instruction_cf_exec_1_reg, condition) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_ADDRESS_MODE(sq_instruction_cf_exec_1_reg, address_mode) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_OPCODE(sq_instruction_cf_exec_1_reg, opcode) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_ADDRESS(sq_instruction_cf_exec_1_reg, address) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_RESERVED(sq_instruction_cf_exec_1_reg, reserved) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_COUNT(sq_instruction_cf_exec_1_reg, count) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK) | (count << SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_YIELD(sq_instruction_cf_exec_1_reg, yield) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) | (yield << SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_1_t { + unsigned int inst_vc_4 : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE; + unsigned int inst_vc_5 : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE; + unsigned int count : SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE; + unsigned int yield : SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE; + } sq_instruction_cf_exec_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_1_t { + unsigned int yield : SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE; + unsigned int count : SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE; + unsigned int inst_vc_5 : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE; + unsigned int inst_vc_4 : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE; + } sq_instruction_cf_exec_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_exec_1_t f; +} sq_instruction_cf_exec_1_u; + + +/* + * SQ_INSTRUCTION_CF_EXEC_2 struct + */ + +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE 8 +#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE 4 + +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT 0 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT 2 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT 3 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT 4 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT 5 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT 6 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT 7 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT 8 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT 9 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT 10 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT 11 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT 12 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT 13 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT 14 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT 15 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT 16 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT 17 +#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT 18 +#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT 26 +#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT 27 +#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT 28 + +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK 0x00000001 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK 0x00000002 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK 0x00000004 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK 0x00000008 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK 0x00000010 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK 0x00000020 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK 0x00000040 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK 0x00000080 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK 0x00000100 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK 0x00000200 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK 0x00000400 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK 0x00001000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK 0x00002000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK 0x00004000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK 0x00008000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK 0x00010000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK 0x00020000 +#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK 0x03fc0000 +#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK 0x04000000 +#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK 0xf0000000 + +#define SQ_INSTRUCTION_CF_EXEC_2_MASK \ + (SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) + +#define SQ_INSTRUCTION_CF_EXEC_2(inst_type_0, inst_serial_0, inst_type_1, inst_serial_1, inst_type_2, inst_serial_2, inst_type_3, inst_serial_3, inst_type_4, inst_serial_4, inst_type_5, inst_serial_5, inst_vc_0, inst_vc_1, inst_vc_2, inst_vc_3, inst_vc_4, inst_vc_5, bool_addr, condition, address_mode, opcode) \ + ((inst_type_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT) | \ + (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT) | \ + (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT) | \ + (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT) | \ + (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT) | \ + (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT) | \ + (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT) | \ + (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT) | \ + (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT) | \ + (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT) | \ + (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT) | \ + (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT) | \ + (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT) | \ + (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT) | \ + (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT) | \ + (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT) | \ + (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT) | \ + (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT) | \ + (bool_addr << SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT) | \ + (condition << SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_0(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_0(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_1(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_1(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_2(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_2(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_3(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_3(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_4(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_4(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_5(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_5(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_0(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_1(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_2(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_3(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_4(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_5(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_BOOL_ADDR(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_CONDITION(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_ADDRESS_MODE(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_OPCODE(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_0(sq_instruction_cf_exec_2_reg, inst_type_0) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK) | (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_0(sq_instruction_cf_exec_2_reg, inst_serial_0) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK) | (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_1(sq_instruction_cf_exec_2_reg, inst_type_1) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK) | (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_1(sq_instruction_cf_exec_2_reg, inst_serial_1) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK) | (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_2(sq_instruction_cf_exec_2_reg, inst_type_2) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK) | (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_2(sq_instruction_cf_exec_2_reg, inst_serial_2) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK) | (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_3(sq_instruction_cf_exec_2_reg, inst_type_3) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK) | (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_3(sq_instruction_cf_exec_2_reg, inst_serial_3) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK) | (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_4(sq_instruction_cf_exec_2_reg, inst_type_4) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK) | (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_4(sq_instruction_cf_exec_2_reg, inst_serial_4) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK) | (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_5(sq_instruction_cf_exec_2_reg, inst_type_5) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK) | (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_5(sq_instruction_cf_exec_2_reg, inst_serial_5) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK) | (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_0(sq_instruction_cf_exec_2_reg, inst_vc_0) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK) | (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_1(sq_instruction_cf_exec_2_reg, inst_vc_1) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK) | (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_2(sq_instruction_cf_exec_2_reg, inst_vc_2) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK) | (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_3(sq_instruction_cf_exec_2_reg, inst_vc_3) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK) | (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_4(sq_instruction_cf_exec_2_reg, inst_vc_4) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK) | (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_5(sq_instruction_cf_exec_2_reg, inst_vc_5) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK) | (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_BOOL_ADDR(sq_instruction_cf_exec_2_reg, bool_addr) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_CONDITION(sq_instruction_cf_exec_2_reg, condition) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_ADDRESS_MODE(sq_instruction_cf_exec_2_reg, address_mode) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_OPCODE(sq_instruction_cf_exec_2_reg, opcode) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_2_t { + unsigned int inst_type_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE; + unsigned int inst_serial_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE; + unsigned int inst_type_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE; + unsigned int inst_serial_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE; + unsigned int inst_type_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE; + unsigned int inst_serial_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE; + unsigned int inst_type_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE; + unsigned int inst_serial_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE; + unsigned int inst_type_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE; + unsigned int inst_serial_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE; + unsigned int inst_type_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE; + unsigned int inst_serial_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE; + unsigned int inst_vc_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE; + unsigned int inst_vc_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE; + unsigned int inst_vc_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE; + unsigned int inst_vc_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE; + unsigned int inst_vc_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE; + unsigned int inst_vc_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE; + } sq_instruction_cf_exec_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_2_t { + unsigned int opcode : SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE; + unsigned int inst_vc_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE; + unsigned int inst_vc_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE; + unsigned int inst_vc_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE; + unsigned int inst_vc_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE; + unsigned int inst_vc_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE; + unsigned int inst_vc_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE; + unsigned int inst_serial_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE; + unsigned int inst_type_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE; + unsigned int inst_serial_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE; + unsigned int inst_type_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE; + unsigned int inst_serial_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE; + unsigned int inst_type_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE; + unsigned int inst_serial_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE; + unsigned int inst_type_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE; + unsigned int inst_serial_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE; + unsigned int inst_type_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE; + unsigned int inst_serial_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE; + unsigned int inst_type_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE; + } sq_instruction_cf_exec_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_exec_2_t f; +} sq_instruction_cf_exec_2_u; + + +/* + * SQ_INSTRUCTION_CF_LOOP_0 struct + */ + +#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE 10 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE 6 +#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE 5 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE 11 + +#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT 0 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT 10 +#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT 16 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT 21 + +#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK 0x000003ff +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK 0x0000fc00 +#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK 0x001f0000 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK 0xffe00000 + +#define SQ_INSTRUCTION_CF_LOOP_0_MASK \ + (SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK | \ + SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) + +#define SQ_INSTRUCTION_CF_LOOP_0(address, reserved_0, loop_id, reserved_1) \ + ((address << SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT) | \ + (reserved_0 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT) | \ + (loop_id << SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT)) + +#define SQ_INSTRUCTION_CF_LOOP_0_GET_ADDRESS(sq_instruction_cf_loop_0) \ + ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_GET_RESERVED_0(sq_instruction_cf_loop_0) \ + ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_GET_LOOP_ID(sq_instruction_cf_loop_0) \ + ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_GET_RESERVED_1(sq_instruction_cf_loop_0) \ + ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT) + +#define SQ_INSTRUCTION_CF_LOOP_0_SET_ADDRESS(sq_instruction_cf_loop_0_reg, address) \ + sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_SET_RESERVED_0(sq_instruction_cf_loop_0_reg, reserved_0) \ + sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_SET_LOOP_ID(sq_instruction_cf_loop_0_reg, loop_id) \ + sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK) | (loop_id << SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_SET_RESERVED_1(sq_instruction_cf_loop_0_reg, reserved_1) \ + sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_0_t { + unsigned int address : SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE; + unsigned int loop_id : SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE; + } sq_instruction_cf_loop_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_0_t { + unsigned int reserved_1 : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE; + unsigned int loop_id : SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE; + } sq_instruction_cf_loop_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_loop_0_t f; +} sq_instruction_cf_loop_0_u; + + +/* + * SQ_INSTRUCTION_CF_LOOP_1 struct + */ + +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE 11 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE 4 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE 10 +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE 6 + +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT 0 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT 11 +#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT 12 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT 16 +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT 26 + +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK 0x000007ff +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK 0x0000f000 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK 0x03ff0000 +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK 0xfc000000 + +#define SQ_INSTRUCTION_CF_LOOP_1_MASK \ + (SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK | \ + SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) + +#define SQ_INSTRUCTION_CF_LOOP_1(reserved_0, address_mode, opcode, address, reserved_1) \ + ((reserved_0 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT) | \ + (address << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT)) + +#define SQ_INSTRUCTION_CF_LOOP_1_GET_RESERVED_0(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_GET_ADDRESS_MODE(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_GET_OPCODE(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_GET_ADDRESS(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_GET_RESERVED_1(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT) + +#define SQ_INSTRUCTION_CF_LOOP_1_SET_RESERVED_0(sq_instruction_cf_loop_1_reg, reserved_0) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_SET_ADDRESS_MODE(sq_instruction_cf_loop_1_reg, address_mode) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_SET_OPCODE(sq_instruction_cf_loop_1_reg, opcode) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_SET_ADDRESS(sq_instruction_cf_loop_1_reg, address) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_SET_RESERVED_1(sq_instruction_cf_loop_1_reg, reserved_1) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_1_t { + unsigned int reserved_0 : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE; + } sq_instruction_cf_loop_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_1_t { + unsigned int reserved_1 : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE; + } sq_instruction_cf_loop_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_loop_1_t f; +} sq_instruction_cf_loop_1_u; + + +/* + * SQ_INSTRUCTION_CF_LOOP_2 struct + */ + +#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE 5 +#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE 22 +#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE 4 + +#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT 0 +#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT 5 +#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT 27 +#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT 28 + +#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK 0x0000001f +#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK 0x07ffffe0 +#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK 0xf0000000 + +#define SQ_INSTRUCTION_CF_LOOP_2_MASK \ + (SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK | \ + SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) + +#define SQ_INSTRUCTION_CF_LOOP_2(loop_id, reserved, address_mode, opcode) \ + ((loop_id << SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT) | \ + (reserved << SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_CF_LOOP_2_GET_LOOP_ID(sq_instruction_cf_loop_2) \ + ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_GET_RESERVED(sq_instruction_cf_loop_2) \ + ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_GET_ADDRESS_MODE(sq_instruction_cf_loop_2) \ + ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_GET_OPCODE(sq_instruction_cf_loop_2) \ + ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_CF_LOOP_2_SET_LOOP_ID(sq_instruction_cf_loop_2_reg, loop_id) \ + sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK) | (loop_id << SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_SET_RESERVED(sq_instruction_cf_loop_2_reg, reserved) \ + sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_SET_ADDRESS_MODE(sq_instruction_cf_loop_2_reg, address_mode) \ + sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_SET_OPCODE(sq_instruction_cf_loop_2_reg, opcode) \ + sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_2_t { + unsigned int loop_id : SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE; + } sq_instruction_cf_loop_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_2_t { + unsigned int opcode : SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE; + unsigned int loop_id : SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE; + } sq_instruction_cf_loop_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_loop_2_t f; +} sq_instruction_cf_loop_2_u; + + +/* + * SQ_INSTRUCTION_CF_JMP_CALL_0 struct + */ + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE 10 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE 3 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE 17 + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT 0 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT 10 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT 13 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT 14 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT 15 + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK 0x000003ff +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK 0x00001c00 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK 0x00002000 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK 0x00004000 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK 0xffff8000 + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_MASK \ + (SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) + +#define SQ_INSTRUCTION_CF_JMP_CALL_0(address, reserved_0, force_call, predicated_jmp, reserved_1) \ + ((address << SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT) | \ + (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT) | \ + (force_call << SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT) | \ + (predicated_jmp << SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT)) + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_ADDRESS(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_RESERVED_0(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_FORCE_CALL(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_PREDICATED_JMP(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_RESERVED_1(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT) + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_ADDRESS(sq_instruction_cf_jmp_call_0_reg, address) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_RESERVED_0(sq_instruction_cf_jmp_call_0_reg, reserved_0) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_FORCE_CALL(sq_instruction_cf_jmp_call_0_reg, force_call) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK) | (force_call << SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_PREDICATED_JMP(sq_instruction_cf_jmp_call_0_reg, predicated_jmp) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK) | (predicated_jmp << SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_RESERVED_1(sq_instruction_cf_jmp_call_0_reg, reserved_1) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_0_t { + unsigned int address : SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE; + unsigned int force_call : SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE; + unsigned int predicated_jmp : SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE; + } sq_instruction_cf_jmp_call_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_0_t { + unsigned int reserved_1 : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE; + unsigned int predicated_jmp : SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE; + unsigned int force_call : SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE; + } sq_instruction_cf_jmp_call_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_jmp_call_0_t f; +} sq_instruction_cf_jmp_call_0_u; + + +/* + * SQ_INSTRUCTION_CF_JMP_CALL_1 struct + */ + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE 8 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE 4 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE 10 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE 3 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE 2 + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT 0 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT 2 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT 10 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT 11 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT 12 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT 16 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT 26 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT 29 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT 30 + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK 0x00000001 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK 0x00000002 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK 0x000003fc +#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK 0x00000400 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK 0x0000f000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK 0x03ff0000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK 0x1c000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK 0x20000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK 0xc0000000 + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_MASK \ + (SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) + +#define SQ_INSTRUCTION_CF_JMP_CALL_1(reserved_0, direction, bool_addr, condition, address_mode, opcode, address, reserved_1, force_call, reserved_2) \ + ((reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT) | \ + (direction << SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT) | \ + (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT) | \ + (condition << SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT) | \ + (address << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT) | \ + (force_call << SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT) | \ + (reserved_2 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT)) + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_0(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_DIRECTION(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_BOOL_ADDR(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_CONDITION(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_ADDRESS_MODE(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_OPCODE(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_ADDRESS(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_1(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_FORCE_CALL(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_2(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT) + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_0(sq_instruction_cf_jmp_call_1_reg, reserved_0) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_DIRECTION(sq_instruction_cf_jmp_call_1_reg, direction) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK) | (direction << SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_BOOL_ADDR(sq_instruction_cf_jmp_call_1_reg, bool_addr) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_CONDITION(sq_instruction_cf_jmp_call_1_reg, condition) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_ADDRESS_MODE(sq_instruction_cf_jmp_call_1_reg, address_mode) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_OPCODE(sq_instruction_cf_jmp_call_1_reg, opcode) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_ADDRESS(sq_instruction_cf_jmp_call_1_reg, address) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_1(sq_instruction_cf_jmp_call_1_reg, reserved_1) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_FORCE_CALL(sq_instruction_cf_jmp_call_1_reg, force_call) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK) | (force_call << SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_2(sq_instruction_cf_jmp_call_1_reg, reserved_2) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) | (reserved_2 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_1_t { + unsigned int reserved_0 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE; + unsigned int direction : SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE; + unsigned int force_call : SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE; + unsigned int reserved_2 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE; + } sq_instruction_cf_jmp_call_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_1_t { + unsigned int reserved_2 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE; + unsigned int force_call : SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE; + unsigned int direction : SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE; + } sq_instruction_cf_jmp_call_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_jmp_call_1_t f; +} sq_instruction_cf_jmp_call_1_u; + + +/* + * SQ_INSTRUCTION_CF_JMP_CALL_2 struct + */ + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE 17 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE 8 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE 4 + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT 0 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT 17 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT 18 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT 26 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT 27 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT 28 + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK 0x0001ffff +#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK 0x00020000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK 0x03fc0000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK 0x04000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK 0xf0000000 + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_MASK \ + (SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) + +#define SQ_INSTRUCTION_CF_JMP_CALL_2(reserved, direction, bool_addr, condition, address_mode, opcode) \ + ((reserved << SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT) | \ + (direction << SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT) | \ + (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT) | \ + (condition << SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_RESERVED(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_DIRECTION(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_BOOL_ADDR(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_CONDITION(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_ADDRESS_MODE(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_OPCODE(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_RESERVED(sq_instruction_cf_jmp_call_2_reg, reserved) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_DIRECTION(sq_instruction_cf_jmp_call_2_reg, direction) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK) | (direction << SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_BOOL_ADDR(sq_instruction_cf_jmp_call_2_reg, bool_addr) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_CONDITION(sq_instruction_cf_jmp_call_2_reg, condition) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_ADDRESS_MODE(sq_instruction_cf_jmp_call_2_reg, address_mode) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_OPCODE(sq_instruction_cf_jmp_call_2_reg, opcode) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_2_t { + unsigned int reserved : SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE; + unsigned int direction : SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE; + } sq_instruction_cf_jmp_call_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_2_t { + unsigned int opcode : SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE; + unsigned int direction : SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE; + } sq_instruction_cf_jmp_call_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_jmp_call_2_t f; +} sq_instruction_cf_jmp_call_2_u; + + +/* + * SQ_INSTRUCTION_CF_ALLOC_0 struct + */ + +#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE 4 +#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE 28 + +#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT 0 +#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT 4 + +#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK 0x0000000f +#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK 0xfffffff0 + +#define SQ_INSTRUCTION_CF_ALLOC_0_MASK \ + (SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) + +#define SQ_INSTRUCTION_CF_ALLOC_0(size, reserved) \ + ((size << SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT) | \ + (reserved << SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT)) + +#define SQ_INSTRUCTION_CF_ALLOC_0_GET_SIZE(sq_instruction_cf_alloc_0) \ + ((sq_instruction_cf_alloc_0 & SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_0_GET_RESERVED(sq_instruction_cf_alloc_0) \ + ((sq_instruction_cf_alloc_0 & SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) >> SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT) + +#define SQ_INSTRUCTION_CF_ALLOC_0_SET_SIZE(sq_instruction_cf_alloc_0_reg, size) \ + sq_instruction_cf_alloc_0_reg = (sq_instruction_cf_alloc_0_reg & ~SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK) | (size << SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_0_SET_RESERVED(sq_instruction_cf_alloc_0_reg, reserved) \ + sq_instruction_cf_alloc_0_reg = (sq_instruction_cf_alloc_0_reg & ~SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_0_t { + unsigned int size : SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE; + } sq_instruction_cf_alloc_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_0_t { + unsigned int reserved : SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE; + unsigned int size : SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE; + } sq_instruction_cf_alloc_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_alloc_0_t f; +} sq_instruction_cf_alloc_0_u; + + +/* + * SQ_INSTRUCTION_CF_ALLOC_1 struct + */ + +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE 8 +#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE 1 +#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE 2 +#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE 4 +#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE 4 +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE 12 + +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT 0 +#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT 8 +#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT 9 +#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT 11 +#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT 12 +#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT 16 +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT 20 + +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK 0x000000ff +#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK 0x00000100 +#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK 0x00000600 +#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK 0x0000f000 +#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK 0x000f0000 +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK 0xfff00000 + +#define SQ_INSTRUCTION_CF_ALLOC_1_MASK \ + (SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) + +#define SQ_INSTRUCTION_CF_ALLOC_1(reserved_0, no_serial, buffer_select, alloc_mode, opcode, size, reserved_1) \ + ((reserved_0 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT) | \ + (no_serial << SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT) | \ + (buffer_select << SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT) | \ + (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT) | \ + (size << SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT)) + +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_RESERVED_0(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_NO_SERIAL(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_BUFFER_SELECT(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_ALLOC_MODE(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_OPCODE(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_SIZE(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_RESERVED_1(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT) + +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_RESERVED_0(sq_instruction_cf_alloc_1_reg, reserved_0) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_NO_SERIAL(sq_instruction_cf_alloc_1_reg, no_serial) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK) | (no_serial << SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_BUFFER_SELECT(sq_instruction_cf_alloc_1_reg, buffer_select) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK) | (buffer_select << SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_ALLOC_MODE(sq_instruction_cf_alloc_1_reg, alloc_mode) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK) | (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_OPCODE(sq_instruction_cf_alloc_1_reg, opcode) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_SIZE(sq_instruction_cf_alloc_1_reg, size) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK) | (size << SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_RESERVED_1(sq_instruction_cf_alloc_1_reg, reserved_1) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_1_t { + unsigned int reserved_0 : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE; + unsigned int no_serial : SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE; + unsigned int buffer_select : SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE; + unsigned int alloc_mode : SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE; + unsigned int size : SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE; + } sq_instruction_cf_alloc_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_1_t { + unsigned int reserved_1 : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE; + unsigned int size : SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE; + unsigned int alloc_mode : SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE; + unsigned int buffer_select : SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE; + unsigned int no_serial : SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE; + } sq_instruction_cf_alloc_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_alloc_1_t f; +} sq_instruction_cf_alloc_1_u; + + +/* + * SQ_INSTRUCTION_CF_ALLOC_2 struct + */ + +#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE 24 +#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE 1 +#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE 2 +#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE 4 + +#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT 0 +#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT 24 +#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT 25 +#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT 27 +#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT 28 + +#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK 0x00ffffff +#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK 0x01000000 +#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK 0x06000000 +#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK 0xf0000000 + +#define SQ_INSTRUCTION_CF_ALLOC_2_MASK \ + (SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) + +#define SQ_INSTRUCTION_CF_ALLOC_2(reserved, no_serial, buffer_select, alloc_mode, opcode) \ + ((reserved << SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT) | \ + (no_serial << SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT) | \ + (buffer_select << SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT) | \ + (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_RESERVED(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_NO_SERIAL(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_BUFFER_SELECT(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_ALLOC_MODE(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_OPCODE(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_RESERVED(sq_instruction_cf_alloc_2_reg, reserved) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_NO_SERIAL(sq_instruction_cf_alloc_2_reg, no_serial) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK) | (no_serial << SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_BUFFER_SELECT(sq_instruction_cf_alloc_2_reg, buffer_select) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK) | (buffer_select << SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_ALLOC_MODE(sq_instruction_cf_alloc_2_reg, alloc_mode) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK) | (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_OPCODE(sq_instruction_cf_alloc_2_reg, opcode) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_2_t { + unsigned int reserved : SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE; + unsigned int no_serial : SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE; + unsigned int buffer_select : SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE; + unsigned int alloc_mode : SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE; + } sq_instruction_cf_alloc_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_2_t { + unsigned int opcode : SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE; + unsigned int alloc_mode : SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE; + unsigned int buffer_select : SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE; + unsigned int no_serial : SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE; + } sq_instruction_cf_alloc_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_alloc_2_t f; +} sq_instruction_cf_alloc_2_u; + + +/* + * SQ_INSTRUCTION_TFETCH_0 struct + */ + +#define SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE 6 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE 6 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE 2 + +#define SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT 0 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT 5 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT 11 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT 12 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT 18 +#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT 19 +#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT 20 +#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT 25 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT 26 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT 28 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT 30 + +#define SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK 0x0000001f +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK 0x000007e0 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK 0x00000800 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK 0x0003f000 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK 0x00040000 +#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK 0x00080000 +#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK 0x01f00000 +#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK 0x02000000 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK 0x0c000000 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK 0x30000000 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK 0xc0000000 + +#define SQ_INSTRUCTION_TFETCH_0_MASK \ + (SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK | \ + SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK | \ + SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK | \ + SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK | \ + SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK | \ + SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) + +#define SQ_INSTRUCTION_TFETCH_0(opcode, src_gpr, src_gpr_am, dst_gpr, dst_gpr_am, fetch_valid_only, const_index, tx_coord_denorm, src_sel_x, src_sel_y, src_sel_z) \ + ((opcode << SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT) | \ + (src_gpr << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT) | \ + (src_gpr_am << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT) | \ + (dst_gpr << SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT) | \ + (dst_gpr_am << SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT) | \ + (fetch_valid_only << SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT) | \ + (const_index << SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT) | \ + (tx_coord_denorm << SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT) | \ + (src_sel_x << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT) | \ + (src_sel_y << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT) | \ + (src_sel_z << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT)) + +#define SQ_INSTRUCTION_TFETCH_0_GET_OPCODE(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK) >> SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_GPR(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_GPR_AM(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_DST_GPR(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK) >> SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_DST_GPR_AM(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK) >> SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_FETCH_VALID_ONLY(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK) >> SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_CONST_INDEX(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK) >> SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_TX_COORD_DENORM(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK) >> SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_X(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_Y(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_Z(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT) + +#define SQ_INSTRUCTION_TFETCH_0_SET_OPCODE(sq_instruction_tfetch_0_reg, opcode) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_GPR(sq_instruction_tfetch_0_reg, src_gpr) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK) | (src_gpr << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_GPR_AM(sq_instruction_tfetch_0_reg, src_gpr_am) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK) | (src_gpr_am << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_DST_GPR(sq_instruction_tfetch_0_reg, dst_gpr) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK) | (dst_gpr << SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_DST_GPR_AM(sq_instruction_tfetch_0_reg, dst_gpr_am) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK) | (dst_gpr_am << SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_FETCH_VALID_ONLY(sq_instruction_tfetch_0_reg, fetch_valid_only) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK) | (fetch_valid_only << SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_CONST_INDEX(sq_instruction_tfetch_0_reg, const_index) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK) | (const_index << SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_TX_COORD_DENORM(sq_instruction_tfetch_0_reg, tx_coord_denorm) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK) | (tx_coord_denorm << SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_X(sq_instruction_tfetch_0_reg, src_sel_x) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK) | (src_sel_x << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_Y(sq_instruction_tfetch_0_reg, src_sel_y) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK) | (src_sel_y << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_Z(sq_instruction_tfetch_0_reg, src_sel_z) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) | (src_sel_z << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_0_t { + unsigned int opcode : SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE; + unsigned int src_gpr : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE; + unsigned int src_gpr_am : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE; + unsigned int dst_gpr : SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE; + unsigned int dst_gpr_am : SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE; + unsigned int fetch_valid_only : SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE; + unsigned int const_index : SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE; + unsigned int tx_coord_denorm : SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE; + unsigned int src_sel_x : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE; + unsigned int src_sel_y : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE; + unsigned int src_sel_z : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE; + } sq_instruction_tfetch_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_0_t { + unsigned int src_sel_z : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE; + unsigned int src_sel_y : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE; + unsigned int src_sel_x : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE; + unsigned int tx_coord_denorm : SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE; + unsigned int const_index : SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE; + unsigned int fetch_valid_only : SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE; + unsigned int dst_gpr_am : SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE; + unsigned int dst_gpr : SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE; + unsigned int src_gpr_am : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE; + unsigned int src_gpr : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE; + unsigned int opcode : SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE; + } sq_instruction_tfetch_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_tfetch_0_t f; +} sq_instruction_tfetch_0_u; + + +/* + * SQ_INSTRUCTION_TFETCH_1 struct + */ + +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE 1 + +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT 0 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT 3 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT 6 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT 9 +#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT 12 +#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT 14 +#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT 16 +#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT 18 +#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT 21 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT 24 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT 26 +#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT 28 +#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT 29 +#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT 31 + +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK 0x00000007 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK 0x00000038 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK 0x000001c0 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK 0x00000e00 +#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK 0x00003000 +#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK 0x0000c000 +#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK 0x00030000 +#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK 0x001c0000 +#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK 0x00e00000 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK 0x03000000 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK 0x0c000000 +#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK 0x10000000 +#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK 0x60000000 +#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK 0x80000000 + +#define SQ_INSTRUCTION_TFETCH_1_MASK \ + (SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK | \ + SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK | \ + SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK | \ + SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK | \ + SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK | \ + SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK | \ + SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) + +#define SQ_INSTRUCTION_TFETCH_1(dst_sel_x, dst_sel_y, dst_sel_z, dst_sel_w, mag_filter, min_filter, mip_filter, aniso_filter, arbitrary_filter, vol_mag_filter, vol_min_filter, use_comp_lod, use_reg_lod, pred_select) \ + ((dst_sel_x << SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT) | \ + (dst_sel_y << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT) | \ + (dst_sel_z << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT) | \ + (dst_sel_w << SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT) | \ + (mag_filter << SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT) | \ + (min_filter << SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT) | \ + (mip_filter << SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT) | \ + (aniso_filter << SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT) | \ + (arbitrary_filter << SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT) | \ + (vol_mag_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT) | \ + (vol_min_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT) | \ + (use_comp_lod << SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT) | \ + (use_reg_lod << SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT) | \ + (pred_select << SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT)) + +#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_X(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_Y(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_Z(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_W(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_MAG_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_MIN_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_MIP_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_ANISO_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_ARBITRARY_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_VOL_MAG_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_VOL_MIN_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_USE_COMP_LOD(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK) >> SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_USE_REG_LOD(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK) >> SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_PRED_SELECT(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT) + +#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_X(sq_instruction_tfetch_1_reg, dst_sel_x) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK) | (dst_sel_x << SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_Y(sq_instruction_tfetch_1_reg, dst_sel_y) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK) | (dst_sel_y << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_Z(sq_instruction_tfetch_1_reg, dst_sel_z) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK) | (dst_sel_z << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_W(sq_instruction_tfetch_1_reg, dst_sel_w) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK) | (dst_sel_w << SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_MAG_FILTER(sq_instruction_tfetch_1_reg, mag_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK) | (mag_filter << SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_MIN_FILTER(sq_instruction_tfetch_1_reg, min_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK) | (min_filter << SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_MIP_FILTER(sq_instruction_tfetch_1_reg, mip_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK) | (mip_filter << SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_ANISO_FILTER(sq_instruction_tfetch_1_reg, aniso_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK) | (aniso_filter << SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_ARBITRARY_FILTER(sq_instruction_tfetch_1_reg, arbitrary_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK) | (arbitrary_filter << SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_VOL_MAG_FILTER(sq_instruction_tfetch_1_reg, vol_mag_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK) | (vol_mag_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_VOL_MIN_FILTER(sq_instruction_tfetch_1_reg, vol_min_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK) | (vol_min_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_USE_COMP_LOD(sq_instruction_tfetch_1_reg, use_comp_lod) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK) | (use_comp_lod << SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_USE_REG_LOD(sq_instruction_tfetch_1_reg, use_reg_lod) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK) | (use_reg_lod << SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_PRED_SELECT(sq_instruction_tfetch_1_reg, pred_select) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_1_t { + unsigned int dst_sel_x : SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE; + unsigned int dst_sel_y : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE; + unsigned int dst_sel_z : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE; + unsigned int dst_sel_w : SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE; + unsigned int mag_filter : SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE; + unsigned int min_filter : SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE; + unsigned int mip_filter : SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE; + unsigned int aniso_filter : SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE; + unsigned int arbitrary_filter : SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE; + unsigned int vol_mag_filter : SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE; + unsigned int vol_min_filter : SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE; + unsigned int use_comp_lod : SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE; + unsigned int use_reg_lod : SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE; + unsigned int pred_select : SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE; + } sq_instruction_tfetch_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_1_t { + unsigned int pred_select : SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE; + unsigned int use_reg_lod : SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE; + unsigned int use_comp_lod : SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE; + unsigned int vol_min_filter : SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE; + unsigned int vol_mag_filter : SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE; + unsigned int arbitrary_filter : SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE; + unsigned int aniso_filter : SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE; + unsigned int mip_filter : SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE; + unsigned int min_filter : SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE; + unsigned int mag_filter : SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE; + unsigned int dst_sel_w : SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE; + unsigned int dst_sel_z : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE; + unsigned int dst_sel_y : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE; + unsigned int dst_sel_x : SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE; + } sq_instruction_tfetch_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_tfetch_1_t f; +} sq_instruction_tfetch_1_u; + + +/* + * SQ_INSTRUCTION_TFETCH_2 struct + */ + +#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE 7 +#define SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE 7 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE 1 + +#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT 0 +#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT 1 +#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT 2 +#define SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT 9 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT 16 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT 21 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT 26 +#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT 31 + +#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK 0x00000001 +#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK 0x00000002 +#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK 0x000001fc +#define SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK 0x0000fe00 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK 0x001f0000 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK 0x03e00000 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK 0x7c000000 +#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK 0x80000000 + +#define SQ_INSTRUCTION_TFETCH_2_MASK \ + (SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK | \ + SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK | \ + SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK | \ + SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK | \ + SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK | \ + SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK | \ + SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK | \ + SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) + +#define SQ_INSTRUCTION_TFETCH_2(use_reg_gradients, sample_location, lod_bias, unused, offset_x, offset_y, offset_z, pred_condition) \ + ((use_reg_gradients << SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT) | \ + (sample_location << SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT) | \ + (lod_bias << SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT) | \ + (unused << SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT) | \ + (offset_x << SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT) | \ + (offset_y << SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT) | \ + (offset_z << SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT) | \ + (pred_condition << SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT)) + +#define SQ_INSTRUCTION_TFETCH_2_GET_USE_REG_GRADIENTS(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK) >> SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_SAMPLE_LOCATION(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK) >> SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_LOD_BIAS(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK) >> SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_UNUSED(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK) >> SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_X(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_Y(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_Z(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_PRED_CONDITION(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) >> SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT) + +#define SQ_INSTRUCTION_TFETCH_2_SET_USE_REG_GRADIENTS(sq_instruction_tfetch_2_reg, use_reg_gradients) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK) | (use_reg_gradients << SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_SAMPLE_LOCATION(sq_instruction_tfetch_2_reg, sample_location) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK) | (sample_location << SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_LOD_BIAS(sq_instruction_tfetch_2_reg, lod_bias) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK) | (lod_bias << SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_UNUSED(sq_instruction_tfetch_2_reg, unused) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK) | (unused << SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_X(sq_instruction_tfetch_2_reg, offset_x) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK) | (offset_x << SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_Y(sq_instruction_tfetch_2_reg, offset_y) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK) | (offset_y << SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_Z(sq_instruction_tfetch_2_reg, offset_z) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK) | (offset_z << SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_PRED_CONDITION(sq_instruction_tfetch_2_reg, pred_condition) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) | (pred_condition << SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_2_t { + unsigned int use_reg_gradients : SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE; + unsigned int sample_location : SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE; + unsigned int lod_bias : SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE; + unsigned int unused : SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE; + unsigned int offset_x : SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE; + unsigned int offset_y : SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE; + unsigned int offset_z : SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE; + unsigned int pred_condition : SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE; + } sq_instruction_tfetch_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_2_t { + unsigned int pred_condition : SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE; + unsigned int offset_z : SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE; + unsigned int offset_y : SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE; + unsigned int offset_x : SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE; + unsigned int unused : SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE; + unsigned int lod_bias : SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE; + unsigned int sample_location : SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE; + unsigned int use_reg_gradients : SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE; + } sq_instruction_tfetch_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_tfetch_2_t f; +} sq_instruction_tfetch_2_u; + + +/* + * SQ_INSTRUCTION_VFETCH_0 struct + */ + +#define SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE 5 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE 6 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE 6 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE 5 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE 2 +#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE 2 + +#define SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT 0 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT 5 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT 11 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT 12 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT 18 +#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT 19 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT 20 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT 25 +#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT 30 + +#define SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK 0x0000001f +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK 0x000007e0 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK 0x00000800 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK 0x0003f000 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK 0x00040000 +#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK 0x00080000 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK 0x01f00000 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK 0x06000000 +#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK 0xc0000000 + +#define SQ_INSTRUCTION_VFETCH_0_MASK \ + (SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK | \ + SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK | \ + SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK | \ + SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK | \ + SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK | \ + SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK | \ + SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK | \ + SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK | \ + SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) + +#define SQ_INSTRUCTION_VFETCH_0(opcode, src_gpr, src_gpr_am, dst_gpr, dst_gpr_am, must_be_one, const_index, const_index_sel, src_sel) \ + ((opcode << SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT) | \ + (src_gpr << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT) | \ + (src_gpr_am << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT) | \ + (dst_gpr << SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT) | \ + (dst_gpr_am << SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT) | \ + (must_be_one << SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT) | \ + (const_index << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT) | \ + (const_index_sel << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT) | \ + (src_sel << SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT)) + +#define SQ_INSTRUCTION_VFETCH_0_GET_OPCODE(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK) >> SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_GPR(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_GPR_AM(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_DST_GPR(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK) >> SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_DST_GPR_AM(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK) >> SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_MUST_BE_ONE(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK) >> SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_CONST_INDEX(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK) >> SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_CONST_INDEX_SEL(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK) >> SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_SEL(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT) + +#define SQ_INSTRUCTION_VFETCH_0_SET_OPCODE(sq_instruction_vfetch_0_reg, opcode) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_GPR(sq_instruction_vfetch_0_reg, src_gpr) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK) | (src_gpr << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_GPR_AM(sq_instruction_vfetch_0_reg, src_gpr_am) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK) | (src_gpr_am << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_DST_GPR(sq_instruction_vfetch_0_reg, dst_gpr) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK) | (dst_gpr << SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_DST_GPR_AM(sq_instruction_vfetch_0_reg, dst_gpr_am) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK) | (dst_gpr_am << SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_MUST_BE_ONE(sq_instruction_vfetch_0_reg, must_be_one) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK) | (must_be_one << SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_CONST_INDEX(sq_instruction_vfetch_0_reg, const_index) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK) | (const_index << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_CONST_INDEX_SEL(sq_instruction_vfetch_0_reg, const_index_sel) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK) | (const_index_sel << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_SEL(sq_instruction_vfetch_0_reg, src_sel) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) | (src_sel << SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_0_t { + unsigned int opcode : SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE; + unsigned int src_gpr : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE; + unsigned int src_gpr_am : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE; + unsigned int dst_gpr : SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE; + unsigned int dst_gpr_am : SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE; + unsigned int must_be_one : SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE; + unsigned int const_index : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE; + unsigned int const_index_sel : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE; + unsigned int : 3; + unsigned int src_sel : SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE; + } sq_instruction_vfetch_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_0_t { + unsigned int src_sel : SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE; + unsigned int : 3; + unsigned int const_index_sel : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE; + unsigned int const_index : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE; + unsigned int must_be_one : SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE; + unsigned int dst_gpr_am : SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE; + unsigned int dst_gpr : SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE; + unsigned int src_gpr_am : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE; + unsigned int src_gpr : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE; + unsigned int opcode : SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE; + } sq_instruction_vfetch_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_vfetch_0_t f; +} sq_instruction_vfetch_0_u; + + +/* + * SQ_INSTRUCTION_VFETCH_1 struct + */ + +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE 3 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE 3 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE 3 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE 3 +#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE 6 +#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE 7 +#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE 1 + +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT 0 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT 3 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT 6 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT 9 +#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT 12 +#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT 13 +#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT 14 +#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT 16 +#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT 23 +#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT 31 + +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK 0x00000007 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK 0x00000038 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK 0x000001c0 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK 0x00000e00 +#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK 0x00001000 +#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK 0x00002000 +#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK 0x00004000 +#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK 0x003f0000 +#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK 0x3f800000 +#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK 0x80000000 + +#define SQ_INSTRUCTION_VFETCH_1_MASK \ + (SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK | \ + SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK | \ + SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK | \ + SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK | \ + SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK | \ + SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK | \ + SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK | \ + SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK | \ + SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK | \ + SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) + +#define SQ_INSTRUCTION_VFETCH_1(dst_sel_x, dst_sel_y, dst_sel_z, dst_sel_w, format_comp_all, num_format_all, signed_rf_mode_all, data_format, exp_adjust_all, pred_select) \ + ((dst_sel_x << SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT) | \ + (dst_sel_y << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT) | \ + (dst_sel_z << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT) | \ + (dst_sel_w << SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT) | \ + (format_comp_all << SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT) | \ + (num_format_all << SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT) | \ + (signed_rf_mode_all << SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT) | \ + (data_format << SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT) | \ + (exp_adjust_all << SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT) | \ + (pred_select << SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT)) + +#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_X(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_Y(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_Z(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_W(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_FORMAT_COMP_ALL(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_NUM_FORMAT_ALL(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_SIGNED_RF_MODE_ALL(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_DATA_FORMAT(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK) >> SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_EXP_ADJUST_ALL(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_PRED_SELECT(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT) + +#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_X(sq_instruction_vfetch_1_reg, dst_sel_x) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK) | (dst_sel_x << SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_Y(sq_instruction_vfetch_1_reg, dst_sel_y) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK) | (dst_sel_y << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_Z(sq_instruction_vfetch_1_reg, dst_sel_z) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK) | (dst_sel_z << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_W(sq_instruction_vfetch_1_reg, dst_sel_w) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK) | (dst_sel_w << SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_FORMAT_COMP_ALL(sq_instruction_vfetch_1_reg, format_comp_all) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK) | (format_comp_all << SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_NUM_FORMAT_ALL(sq_instruction_vfetch_1_reg, num_format_all) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK) | (num_format_all << SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_SIGNED_RF_MODE_ALL(sq_instruction_vfetch_1_reg, signed_rf_mode_all) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK) | (signed_rf_mode_all << SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_DATA_FORMAT(sq_instruction_vfetch_1_reg, data_format) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK) | (data_format << SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_EXP_ADJUST_ALL(sq_instruction_vfetch_1_reg, exp_adjust_all) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK) | (exp_adjust_all << SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_PRED_SELECT(sq_instruction_vfetch_1_reg, pred_select) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_1_t { + unsigned int dst_sel_x : SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE; + unsigned int dst_sel_y : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE; + unsigned int dst_sel_z : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE; + unsigned int dst_sel_w : SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE; + unsigned int format_comp_all : SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE; + unsigned int num_format_all : SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE; + unsigned int signed_rf_mode_all : SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE; + unsigned int : 1; + unsigned int data_format : SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE; + unsigned int : 1; + unsigned int exp_adjust_all : SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE; + unsigned int : 1; + unsigned int pred_select : SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE; + } sq_instruction_vfetch_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_1_t { + unsigned int pred_select : SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE; + unsigned int : 1; + unsigned int exp_adjust_all : SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE; + unsigned int : 1; + unsigned int data_format : SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE; + unsigned int : 1; + unsigned int signed_rf_mode_all : SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE; + unsigned int num_format_all : SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE; + unsigned int format_comp_all : SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE; + unsigned int dst_sel_w : SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE; + unsigned int dst_sel_z : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE; + unsigned int dst_sel_y : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE; + unsigned int dst_sel_x : SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE; + } sq_instruction_vfetch_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_vfetch_1_t f; +} sq_instruction_vfetch_1_u; + + +/* + * SQ_INSTRUCTION_VFETCH_2 struct + */ + +#define SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE 8 +#define SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE 8 +#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE 1 + +#define SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT 0 +#define SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT 16 +#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT 31 + +#define SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK 0x000000ff +#define SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK 0x00ff0000 +#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK 0x80000000 + +#define SQ_INSTRUCTION_VFETCH_2_MASK \ + (SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK | \ + SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK | \ + SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) + +#define SQ_INSTRUCTION_VFETCH_2(stride, offset, pred_condition) \ + ((stride << SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT) | \ + (offset << SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT) | \ + (pred_condition << SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT)) + +#define SQ_INSTRUCTION_VFETCH_2_GET_STRIDE(sq_instruction_vfetch_2) \ + ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK) >> SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_2_GET_OFFSET(sq_instruction_vfetch_2) \ + ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK) >> SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT) +#define SQ_INSTRUCTION_VFETCH_2_GET_PRED_CONDITION(sq_instruction_vfetch_2) \ + ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) >> SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT) + +#define SQ_INSTRUCTION_VFETCH_2_SET_STRIDE(sq_instruction_vfetch_2_reg, stride) \ + sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK) | (stride << SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_2_SET_OFFSET(sq_instruction_vfetch_2_reg, offset) \ + sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK) | (offset << SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT) +#define SQ_INSTRUCTION_VFETCH_2_SET_PRED_CONDITION(sq_instruction_vfetch_2_reg, pred_condition) \ + sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) | (pred_condition << SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_2_t { + unsigned int stride : SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE; + unsigned int : 8; + unsigned int offset : SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE; + unsigned int : 7; + unsigned int pred_condition : SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE; + } sq_instruction_vfetch_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_2_t { + unsigned int pred_condition : SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE; + unsigned int : 7; + unsigned int offset : SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE; + unsigned int : 8; + unsigned int stride : SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE; + } sq_instruction_vfetch_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_vfetch_2_t f; +} sq_instruction_vfetch_2_u; + + +/* + * SQ_CONSTANT_0 struct + */ + +#define SQ_CONSTANT_0_RED_SIZE 32 + +#define SQ_CONSTANT_0_RED_SHIFT 0 + +#define SQ_CONSTANT_0_RED_MASK 0xffffffff + +#define SQ_CONSTANT_0_MASK \ + (SQ_CONSTANT_0_RED_MASK) + +#define SQ_CONSTANT_0(red) \ + ((red << SQ_CONSTANT_0_RED_SHIFT)) + +#define SQ_CONSTANT_0_GET_RED(sq_constant_0) \ + ((sq_constant_0 & SQ_CONSTANT_0_RED_MASK) >> SQ_CONSTANT_0_RED_SHIFT) + +#define SQ_CONSTANT_0_SET_RED(sq_constant_0_reg, red) \ + sq_constant_0_reg = (sq_constant_0_reg & ~SQ_CONSTANT_0_RED_MASK) | (red << SQ_CONSTANT_0_RED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_0_t { + unsigned int red : SQ_CONSTANT_0_RED_SIZE; + } sq_constant_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_0_t { + unsigned int red : SQ_CONSTANT_0_RED_SIZE; + } sq_constant_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_0_t f; +} sq_constant_0_u; + + +/* + * SQ_CONSTANT_1 struct + */ + +#define SQ_CONSTANT_1_GREEN_SIZE 32 + +#define SQ_CONSTANT_1_GREEN_SHIFT 0 + +#define SQ_CONSTANT_1_GREEN_MASK 0xffffffff + +#define SQ_CONSTANT_1_MASK \ + (SQ_CONSTANT_1_GREEN_MASK) + +#define SQ_CONSTANT_1(green) \ + ((green << SQ_CONSTANT_1_GREEN_SHIFT)) + +#define SQ_CONSTANT_1_GET_GREEN(sq_constant_1) \ + ((sq_constant_1 & SQ_CONSTANT_1_GREEN_MASK) >> SQ_CONSTANT_1_GREEN_SHIFT) + +#define SQ_CONSTANT_1_SET_GREEN(sq_constant_1_reg, green) \ + sq_constant_1_reg = (sq_constant_1_reg & ~SQ_CONSTANT_1_GREEN_MASK) | (green << SQ_CONSTANT_1_GREEN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_1_t { + unsigned int green : SQ_CONSTANT_1_GREEN_SIZE; + } sq_constant_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_1_t { + unsigned int green : SQ_CONSTANT_1_GREEN_SIZE; + } sq_constant_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_1_t f; +} sq_constant_1_u; + + +/* + * SQ_CONSTANT_2 struct + */ + +#define SQ_CONSTANT_2_BLUE_SIZE 32 + +#define SQ_CONSTANT_2_BLUE_SHIFT 0 + +#define SQ_CONSTANT_2_BLUE_MASK 0xffffffff + +#define SQ_CONSTANT_2_MASK \ + (SQ_CONSTANT_2_BLUE_MASK) + +#define SQ_CONSTANT_2(blue) \ + ((blue << SQ_CONSTANT_2_BLUE_SHIFT)) + +#define SQ_CONSTANT_2_GET_BLUE(sq_constant_2) \ + ((sq_constant_2 & SQ_CONSTANT_2_BLUE_MASK) >> SQ_CONSTANT_2_BLUE_SHIFT) + +#define SQ_CONSTANT_2_SET_BLUE(sq_constant_2_reg, blue) \ + sq_constant_2_reg = (sq_constant_2_reg & ~SQ_CONSTANT_2_BLUE_MASK) | (blue << SQ_CONSTANT_2_BLUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_2_t { + unsigned int blue : SQ_CONSTANT_2_BLUE_SIZE; + } sq_constant_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_2_t { + unsigned int blue : SQ_CONSTANT_2_BLUE_SIZE; + } sq_constant_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_2_t f; +} sq_constant_2_u; + + +/* + * SQ_CONSTANT_3 struct + */ + +#define SQ_CONSTANT_3_ALPHA_SIZE 32 + +#define SQ_CONSTANT_3_ALPHA_SHIFT 0 + +#define SQ_CONSTANT_3_ALPHA_MASK 0xffffffff + +#define SQ_CONSTANT_3_MASK \ + (SQ_CONSTANT_3_ALPHA_MASK) + +#define SQ_CONSTANT_3(alpha) \ + ((alpha << SQ_CONSTANT_3_ALPHA_SHIFT)) + +#define SQ_CONSTANT_3_GET_ALPHA(sq_constant_3) \ + ((sq_constant_3 & SQ_CONSTANT_3_ALPHA_MASK) >> SQ_CONSTANT_3_ALPHA_SHIFT) + +#define SQ_CONSTANT_3_SET_ALPHA(sq_constant_3_reg, alpha) \ + sq_constant_3_reg = (sq_constant_3_reg & ~SQ_CONSTANT_3_ALPHA_MASK) | (alpha << SQ_CONSTANT_3_ALPHA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_3_t { + unsigned int alpha : SQ_CONSTANT_3_ALPHA_SIZE; + } sq_constant_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_3_t { + unsigned int alpha : SQ_CONSTANT_3_ALPHA_SIZE; + } sq_constant_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_3_t f; +} sq_constant_3_u; + + +/* + * SQ_FETCH_0 struct + */ + +#define SQ_FETCH_0_VALUE_SIZE 32 + +#define SQ_FETCH_0_VALUE_SHIFT 0 + +#define SQ_FETCH_0_VALUE_MASK 0xffffffff + +#define SQ_FETCH_0_MASK \ + (SQ_FETCH_0_VALUE_MASK) + +#define SQ_FETCH_0(value) \ + ((value << SQ_FETCH_0_VALUE_SHIFT)) + +#define SQ_FETCH_0_GET_VALUE(sq_fetch_0) \ + ((sq_fetch_0 & SQ_FETCH_0_VALUE_MASK) >> SQ_FETCH_0_VALUE_SHIFT) + +#define SQ_FETCH_0_SET_VALUE(sq_fetch_0_reg, value) \ + sq_fetch_0_reg = (sq_fetch_0_reg & ~SQ_FETCH_0_VALUE_MASK) | (value << SQ_FETCH_0_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_0_t { + unsigned int value : SQ_FETCH_0_VALUE_SIZE; + } sq_fetch_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_0_t { + unsigned int value : SQ_FETCH_0_VALUE_SIZE; + } sq_fetch_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_0_t f; +} sq_fetch_0_u; + + +/* + * SQ_FETCH_1 struct + */ + +#define SQ_FETCH_1_VALUE_SIZE 32 + +#define SQ_FETCH_1_VALUE_SHIFT 0 + +#define SQ_FETCH_1_VALUE_MASK 0xffffffff + +#define SQ_FETCH_1_MASK \ + (SQ_FETCH_1_VALUE_MASK) + +#define SQ_FETCH_1(value) \ + ((value << SQ_FETCH_1_VALUE_SHIFT)) + +#define SQ_FETCH_1_GET_VALUE(sq_fetch_1) \ + ((sq_fetch_1 & SQ_FETCH_1_VALUE_MASK) >> SQ_FETCH_1_VALUE_SHIFT) + +#define SQ_FETCH_1_SET_VALUE(sq_fetch_1_reg, value) \ + sq_fetch_1_reg = (sq_fetch_1_reg & ~SQ_FETCH_1_VALUE_MASK) | (value << SQ_FETCH_1_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_1_t { + unsigned int value : SQ_FETCH_1_VALUE_SIZE; + } sq_fetch_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_1_t { + unsigned int value : SQ_FETCH_1_VALUE_SIZE; + } sq_fetch_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_1_t f; +} sq_fetch_1_u; + + +/* + * SQ_FETCH_2 struct + */ + +#define SQ_FETCH_2_VALUE_SIZE 32 + +#define SQ_FETCH_2_VALUE_SHIFT 0 + +#define SQ_FETCH_2_VALUE_MASK 0xffffffff + +#define SQ_FETCH_2_MASK \ + (SQ_FETCH_2_VALUE_MASK) + +#define SQ_FETCH_2(value) \ + ((value << SQ_FETCH_2_VALUE_SHIFT)) + +#define SQ_FETCH_2_GET_VALUE(sq_fetch_2) \ + ((sq_fetch_2 & SQ_FETCH_2_VALUE_MASK) >> SQ_FETCH_2_VALUE_SHIFT) + +#define SQ_FETCH_2_SET_VALUE(sq_fetch_2_reg, value) \ + sq_fetch_2_reg = (sq_fetch_2_reg & ~SQ_FETCH_2_VALUE_MASK) | (value << SQ_FETCH_2_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_2_t { + unsigned int value : SQ_FETCH_2_VALUE_SIZE; + } sq_fetch_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_2_t { + unsigned int value : SQ_FETCH_2_VALUE_SIZE; + } sq_fetch_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_2_t f; +} sq_fetch_2_u; + + +/* + * SQ_FETCH_3 struct + */ + +#define SQ_FETCH_3_VALUE_SIZE 32 + +#define SQ_FETCH_3_VALUE_SHIFT 0 + +#define SQ_FETCH_3_VALUE_MASK 0xffffffff + +#define SQ_FETCH_3_MASK \ + (SQ_FETCH_3_VALUE_MASK) + +#define SQ_FETCH_3(value) \ + ((value << SQ_FETCH_3_VALUE_SHIFT)) + +#define SQ_FETCH_3_GET_VALUE(sq_fetch_3) \ + ((sq_fetch_3 & SQ_FETCH_3_VALUE_MASK) >> SQ_FETCH_3_VALUE_SHIFT) + +#define SQ_FETCH_3_SET_VALUE(sq_fetch_3_reg, value) \ + sq_fetch_3_reg = (sq_fetch_3_reg & ~SQ_FETCH_3_VALUE_MASK) | (value << SQ_FETCH_3_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_3_t { + unsigned int value : SQ_FETCH_3_VALUE_SIZE; + } sq_fetch_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_3_t { + unsigned int value : SQ_FETCH_3_VALUE_SIZE; + } sq_fetch_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_3_t f; +} sq_fetch_3_u; + + +/* + * SQ_FETCH_4 struct + */ + +#define SQ_FETCH_4_VALUE_SIZE 32 + +#define SQ_FETCH_4_VALUE_SHIFT 0 + +#define SQ_FETCH_4_VALUE_MASK 0xffffffff + +#define SQ_FETCH_4_MASK \ + (SQ_FETCH_4_VALUE_MASK) + +#define SQ_FETCH_4(value) \ + ((value << SQ_FETCH_4_VALUE_SHIFT)) + +#define SQ_FETCH_4_GET_VALUE(sq_fetch_4) \ + ((sq_fetch_4 & SQ_FETCH_4_VALUE_MASK) >> SQ_FETCH_4_VALUE_SHIFT) + +#define SQ_FETCH_4_SET_VALUE(sq_fetch_4_reg, value) \ + sq_fetch_4_reg = (sq_fetch_4_reg & ~SQ_FETCH_4_VALUE_MASK) | (value << SQ_FETCH_4_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_4_t { + unsigned int value : SQ_FETCH_4_VALUE_SIZE; + } sq_fetch_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_4_t { + unsigned int value : SQ_FETCH_4_VALUE_SIZE; + } sq_fetch_4_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_4_t f; +} sq_fetch_4_u; + + +/* + * SQ_FETCH_5 struct + */ + +#define SQ_FETCH_5_VALUE_SIZE 32 + +#define SQ_FETCH_5_VALUE_SHIFT 0 + +#define SQ_FETCH_5_VALUE_MASK 0xffffffff + +#define SQ_FETCH_5_MASK \ + (SQ_FETCH_5_VALUE_MASK) + +#define SQ_FETCH_5(value) \ + ((value << SQ_FETCH_5_VALUE_SHIFT)) + +#define SQ_FETCH_5_GET_VALUE(sq_fetch_5) \ + ((sq_fetch_5 & SQ_FETCH_5_VALUE_MASK) >> SQ_FETCH_5_VALUE_SHIFT) + +#define SQ_FETCH_5_SET_VALUE(sq_fetch_5_reg, value) \ + sq_fetch_5_reg = (sq_fetch_5_reg & ~SQ_FETCH_5_VALUE_MASK) | (value << SQ_FETCH_5_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_5_t { + unsigned int value : SQ_FETCH_5_VALUE_SIZE; + } sq_fetch_5_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_5_t { + unsigned int value : SQ_FETCH_5_VALUE_SIZE; + } sq_fetch_5_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_5_t f; +} sq_fetch_5_u; + + +/* + * SQ_CONSTANT_VFETCH_0 struct + */ + +#define SQ_CONSTANT_VFETCH_0_TYPE_SIZE 1 +#define SQ_CONSTANT_VFETCH_0_STATE_SIZE 1 +#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE 30 + +#define SQ_CONSTANT_VFETCH_0_TYPE_SHIFT 0 +#define SQ_CONSTANT_VFETCH_0_STATE_SHIFT 1 +#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT 2 + +#define SQ_CONSTANT_VFETCH_0_TYPE_MASK 0x00000001 +#define SQ_CONSTANT_VFETCH_0_STATE_MASK 0x00000002 +#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK 0xfffffffc + +#define SQ_CONSTANT_VFETCH_0_MASK \ + (SQ_CONSTANT_VFETCH_0_TYPE_MASK | \ + SQ_CONSTANT_VFETCH_0_STATE_MASK | \ + SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) + +#define SQ_CONSTANT_VFETCH_0(type, state, base_address) \ + ((type << SQ_CONSTANT_VFETCH_0_TYPE_SHIFT) | \ + (state << SQ_CONSTANT_VFETCH_0_STATE_SHIFT) | \ + (base_address << SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT)) + +#define SQ_CONSTANT_VFETCH_0_GET_TYPE(sq_constant_vfetch_0) \ + ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_TYPE_MASK) >> SQ_CONSTANT_VFETCH_0_TYPE_SHIFT) +#define SQ_CONSTANT_VFETCH_0_GET_STATE(sq_constant_vfetch_0) \ + ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_STATE_MASK) >> SQ_CONSTANT_VFETCH_0_STATE_SHIFT) +#define SQ_CONSTANT_VFETCH_0_GET_BASE_ADDRESS(sq_constant_vfetch_0) \ + ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) >> SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT) + +#define SQ_CONSTANT_VFETCH_0_SET_TYPE(sq_constant_vfetch_0_reg, type) \ + sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_TYPE_MASK) | (type << SQ_CONSTANT_VFETCH_0_TYPE_SHIFT) +#define SQ_CONSTANT_VFETCH_0_SET_STATE(sq_constant_vfetch_0_reg, state) \ + sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_STATE_MASK) | (state << SQ_CONSTANT_VFETCH_0_STATE_SHIFT) +#define SQ_CONSTANT_VFETCH_0_SET_BASE_ADDRESS(sq_constant_vfetch_0_reg, base_address) \ + sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) | (base_address << SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_vfetch_0_t { + unsigned int type : SQ_CONSTANT_VFETCH_0_TYPE_SIZE; + unsigned int state : SQ_CONSTANT_VFETCH_0_STATE_SIZE; + unsigned int base_address : SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE; + } sq_constant_vfetch_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_vfetch_0_t { + unsigned int base_address : SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE; + unsigned int state : SQ_CONSTANT_VFETCH_0_STATE_SIZE; + unsigned int type : SQ_CONSTANT_VFETCH_0_TYPE_SIZE; + } sq_constant_vfetch_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_vfetch_0_t f; +} sq_constant_vfetch_0_u; + + +/* + * SQ_CONSTANT_VFETCH_1 struct + */ + +#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE 2 +#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE 30 + +#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT 0 +#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT 2 + +#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK 0x00000003 +#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK 0xfffffffc + +#define SQ_CONSTANT_VFETCH_1_MASK \ + (SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK | \ + SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) + +#define SQ_CONSTANT_VFETCH_1(endian_swap, limit_address) \ + ((endian_swap << SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT) | \ + (limit_address << SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT)) + +#define SQ_CONSTANT_VFETCH_1_GET_ENDIAN_SWAP(sq_constant_vfetch_1) \ + ((sq_constant_vfetch_1 & SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK) >> SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT) +#define SQ_CONSTANT_VFETCH_1_GET_LIMIT_ADDRESS(sq_constant_vfetch_1) \ + ((sq_constant_vfetch_1 & SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) >> SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT) + +#define SQ_CONSTANT_VFETCH_1_SET_ENDIAN_SWAP(sq_constant_vfetch_1_reg, endian_swap) \ + sq_constant_vfetch_1_reg = (sq_constant_vfetch_1_reg & ~SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK) | (endian_swap << SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT) +#define SQ_CONSTANT_VFETCH_1_SET_LIMIT_ADDRESS(sq_constant_vfetch_1_reg, limit_address) \ + sq_constant_vfetch_1_reg = (sq_constant_vfetch_1_reg & ~SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) | (limit_address << SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_vfetch_1_t { + unsigned int endian_swap : SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE; + unsigned int limit_address : SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE; + } sq_constant_vfetch_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_vfetch_1_t { + unsigned int limit_address : SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE; + unsigned int endian_swap : SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE; + } sq_constant_vfetch_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_vfetch_1_t f; +} sq_constant_vfetch_1_u; + + +/* + * SQ_CONSTANT_T2 struct + */ + +#define SQ_CONSTANT_T2_VALUE_SIZE 32 + +#define SQ_CONSTANT_T2_VALUE_SHIFT 0 + +#define SQ_CONSTANT_T2_VALUE_MASK 0xffffffff + +#define SQ_CONSTANT_T2_MASK \ + (SQ_CONSTANT_T2_VALUE_MASK) + +#define SQ_CONSTANT_T2(value) \ + ((value << SQ_CONSTANT_T2_VALUE_SHIFT)) + +#define SQ_CONSTANT_T2_GET_VALUE(sq_constant_t2) \ + ((sq_constant_t2 & SQ_CONSTANT_T2_VALUE_MASK) >> SQ_CONSTANT_T2_VALUE_SHIFT) + +#define SQ_CONSTANT_T2_SET_VALUE(sq_constant_t2_reg, value) \ + sq_constant_t2_reg = (sq_constant_t2_reg & ~SQ_CONSTANT_T2_VALUE_MASK) | (value << SQ_CONSTANT_T2_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_t2_t { + unsigned int value : SQ_CONSTANT_T2_VALUE_SIZE; + } sq_constant_t2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_t2_t { + unsigned int value : SQ_CONSTANT_T2_VALUE_SIZE; + } sq_constant_t2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_t2_t f; +} sq_constant_t2_u; + + +/* + * SQ_CONSTANT_T3 struct + */ + +#define SQ_CONSTANT_T3_VALUE_SIZE 32 + +#define SQ_CONSTANT_T3_VALUE_SHIFT 0 + +#define SQ_CONSTANT_T3_VALUE_MASK 0xffffffff + +#define SQ_CONSTANT_T3_MASK \ + (SQ_CONSTANT_T3_VALUE_MASK) + +#define SQ_CONSTANT_T3(value) \ + ((value << SQ_CONSTANT_T3_VALUE_SHIFT)) + +#define SQ_CONSTANT_T3_GET_VALUE(sq_constant_t3) \ + ((sq_constant_t3 & SQ_CONSTANT_T3_VALUE_MASK) >> SQ_CONSTANT_T3_VALUE_SHIFT) + +#define SQ_CONSTANT_T3_SET_VALUE(sq_constant_t3_reg, value) \ + sq_constant_t3_reg = (sq_constant_t3_reg & ~SQ_CONSTANT_T3_VALUE_MASK) | (value << SQ_CONSTANT_T3_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_t3_t { + unsigned int value : SQ_CONSTANT_T3_VALUE_SIZE; + } sq_constant_t3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_t3_t { + unsigned int value : SQ_CONSTANT_T3_VALUE_SIZE; + } sq_constant_t3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_t3_t f; +} sq_constant_t3_u; + + +/* + * SQ_CF_BOOLEANS struct + */ + +#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE 8 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE 8 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE 8 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE 8 + +#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT 0 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT 8 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT 16 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT 24 + +#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK 0x000000ff +#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK 0x0000ff00 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK 0x00ff0000 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK 0xff000000 + +#define SQ_CF_BOOLEANS_MASK \ + (SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK | \ + SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK | \ + SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK | \ + SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) + +#define SQ_CF_BOOLEANS(cf_booleans_0, cf_booleans_1, cf_booleans_2, cf_booleans_3) \ + ((cf_booleans_0 << SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT) | \ + (cf_booleans_1 << SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT) | \ + (cf_booleans_2 << SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT) | \ + (cf_booleans_3 << SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT)) + +#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_0(sq_cf_booleans) \ + ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT) +#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_1(sq_cf_booleans) \ + ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT) +#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_2(sq_cf_booleans) \ + ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT) +#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_3(sq_cf_booleans) \ + ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT) + +#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_0(sq_cf_booleans_reg, cf_booleans_0) \ + sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK) | (cf_booleans_0 << SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT) +#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_1(sq_cf_booleans_reg, cf_booleans_1) \ + sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK) | (cf_booleans_1 << SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT) +#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_2(sq_cf_booleans_reg, cf_booleans_2) \ + sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK) | (cf_booleans_2 << SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT) +#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_3(sq_cf_booleans_reg, cf_booleans_3) \ + sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) | (cf_booleans_3 << SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_booleans_t { + unsigned int cf_booleans_0 : SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE; + unsigned int cf_booleans_1 : SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE; + unsigned int cf_booleans_2 : SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE; + unsigned int cf_booleans_3 : SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE; + } sq_cf_booleans_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_booleans_t { + unsigned int cf_booleans_3 : SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE; + unsigned int cf_booleans_2 : SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE; + unsigned int cf_booleans_1 : SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE; + unsigned int cf_booleans_0 : SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE; + } sq_cf_booleans_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_booleans_t f; +} sq_cf_booleans_u; + + +/* + * SQ_CF_LOOP struct + */ + +#define SQ_CF_LOOP_CF_LOOP_COUNT_SIZE 8 +#define SQ_CF_LOOP_CF_LOOP_START_SIZE 8 +#define SQ_CF_LOOP_CF_LOOP_STEP_SIZE 8 + +#define SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT 0 +#define SQ_CF_LOOP_CF_LOOP_START_SHIFT 8 +#define SQ_CF_LOOP_CF_LOOP_STEP_SHIFT 16 + +#define SQ_CF_LOOP_CF_LOOP_COUNT_MASK 0x000000ff +#define SQ_CF_LOOP_CF_LOOP_START_MASK 0x0000ff00 +#define SQ_CF_LOOP_CF_LOOP_STEP_MASK 0x00ff0000 + +#define SQ_CF_LOOP_MASK \ + (SQ_CF_LOOP_CF_LOOP_COUNT_MASK | \ + SQ_CF_LOOP_CF_LOOP_START_MASK | \ + SQ_CF_LOOP_CF_LOOP_STEP_MASK) + +#define SQ_CF_LOOP(cf_loop_count, cf_loop_start, cf_loop_step) \ + ((cf_loop_count << SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT) | \ + (cf_loop_start << SQ_CF_LOOP_CF_LOOP_START_SHIFT) | \ + (cf_loop_step << SQ_CF_LOOP_CF_LOOP_STEP_SHIFT)) + +#define SQ_CF_LOOP_GET_CF_LOOP_COUNT(sq_cf_loop) \ + ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_COUNT_MASK) >> SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT) +#define SQ_CF_LOOP_GET_CF_LOOP_START(sq_cf_loop) \ + ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_START_MASK) >> SQ_CF_LOOP_CF_LOOP_START_SHIFT) +#define SQ_CF_LOOP_GET_CF_LOOP_STEP(sq_cf_loop) \ + ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_STEP_MASK) >> SQ_CF_LOOP_CF_LOOP_STEP_SHIFT) + +#define SQ_CF_LOOP_SET_CF_LOOP_COUNT(sq_cf_loop_reg, cf_loop_count) \ + sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_COUNT_MASK) | (cf_loop_count << SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT) +#define SQ_CF_LOOP_SET_CF_LOOP_START(sq_cf_loop_reg, cf_loop_start) \ + sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_START_MASK) | (cf_loop_start << SQ_CF_LOOP_CF_LOOP_START_SHIFT) +#define SQ_CF_LOOP_SET_CF_LOOP_STEP(sq_cf_loop_reg, cf_loop_step) \ + sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_STEP_MASK) | (cf_loop_step << SQ_CF_LOOP_CF_LOOP_STEP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_loop_t { + unsigned int cf_loop_count : SQ_CF_LOOP_CF_LOOP_COUNT_SIZE; + unsigned int cf_loop_start : SQ_CF_LOOP_CF_LOOP_START_SIZE; + unsigned int cf_loop_step : SQ_CF_LOOP_CF_LOOP_STEP_SIZE; + unsigned int : 8; + } sq_cf_loop_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_loop_t { + unsigned int : 8; + unsigned int cf_loop_step : SQ_CF_LOOP_CF_LOOP_STEP_SIZE; + unsigned int cf_loop_start : SQ_CF_LOOP_CF_LOOP_START_SIZE; + unsigned int cf_loop_count : SQ_CF_LOOP_CF_LOOP_COUNT_SIZE; + } sq_cf_loop_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_loop_t f; +} sq_cf_loop_u; + + +/* + * SQ_CONSTANT_RT_0 struct + */ + +#define SQ_CONSTANT_RT_0_RED_SIZE 32 + +#define SQ_CONSTANT_RT_0_RED_SHIFT 0 + +#define SQ_CONSTANT_RT_0_RED_MASK 0xffffffff + +#define SQ_CONSTANT_RT_0_MASK \ + (SQ_CONSTANT_RT_0_RED_MASK) + +#define SQ_CONSTANT_RT_0(red) \ + ((red << SQ_CONSTANT_RT_0_RED_SHIFT)) + +#define SQ_CONSTANT_RT_0_GET_RED(sq_constant_rt_0) \ + ((sq_constant_rt_0 & SQ_CONSTANT_RT_0_RED_MASK) >> SQ_CONSTANT_RT_0_RED_SHIFT) + +#define SQ_CONSTANT_RT_0_SET_RED(sq_constant_rt_0_reg, red) \ + sq_constant_rt_0_reg = (sq_constant_rt_0_reg & ~SQ_CONSTANT_RT_0_RED_MASK) | (red << SQ_CONSTANT_RT_0_RED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_rt_0_t { + unsigned int red : SQ_CONSTANT_RT_0_RED_SIZE; + } sq_constant_rt_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_rt_0_t { + unsigned int red : SQ_CONSTANT_RT_0_RED_SIZE; + } sq_constant_rt_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_rt_0_t f; +} sq_constant_rt_0_u; + + +/* + * SQ_CONSTANT_RT_1 struct + */ + +#define SQ_CONSTANT_RT_1_GREEN_SIZE 32 + +#define SQ_CONSTANT_RT_1_GREEN_SHIFT 0 + +#define SQ_CONSTANT_RT_1_GREEN_MASK 0xffffffff + +#define SQ_CONSTANT_RT_1_MASK \ + (SQ_CONSTANT_RT_1_GREEN_MASK) + +#define SQ_CONSTANT_RT_1(green) \ + ((green << SQ_CONSTANT_RT_1_GREEN_SHIFT)) + +#define SQ_CONSTANT_RT_1_GET_GREEN(sq_constant_rt_1) \ + ((sq_constant_rt_1 & SQ_CONSTANT_RT_1_GREEN_MASK) >> SQ_CONSTANT_RT_1_GREEN_SHIFT) + +#define SQ_CONSTANT_RT_1_SET_GREEN(sq_constant_rt_1_reg, green) \ + sq_constant_rt_1_reg = (sq_constant_rt_1_reg & ~SQ_CONSTANT_RT_1_GREEN_MASK) | (green << SQ_CONSTANT_RT_1_GREEN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_rt_1_t { + unsigned int green : SQ_CONSTANT_RT_1_GREEN_SIZE; + } sq_constant_rt_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_rt_1_t { + unsigned int green : SQ_CONSTANT_RT_1_GREEN_SIZE; + } sq_constant_rt_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_rt_1_t f; +} sq_constant_rt_1_u; + + +/* + * SQ_CONSTANT_RT_2 struct + */ + +#define SQ_CONSTANT_RT_2_BLUE_SIZE 32 + +#define SQ_CONSTANT_RT_2_BLUE_SHIFT 0 + +#define SQ_CONSTANT_RT_2_BLUE_MASK 0xffffffff + +#define SQ_CONSTANT_RT_2_MASK \ + (SQ_CONSTANT_RT_2_BLUE_MASK) + +#define SQ_CONSTANT_RT_2(blue) \ + ((blue << SQ_CONSTANT_RT_2_BLUE_SHIFT)) + +#define SQ_CONSTANT_RT_2_GET_BLUE(sq_constant_rt_2) \ + ((sq_constant_rt_2 & SQ_CONSTANT_RT_2_BLUE_MASK) >> SQ_CONSTANT_RT_2_BLUE_SHIFT) + +#define SQ_CONSTANT_RT_2_SET_BLUE(sq_constant_rt_2_reg, blue) \ + sq_constant_rt_2_reg = (sq_constant_rt_2_reg & ~SQ_CONSTANT_RT_2_BLUE_MASK) | (blue << SQ_CONSTANT_RT_2_BLUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_rt_2_t { + unsigned int blue : SQ_CONSTANT_RT_2_BLUE_SIZE; + } sq_constant_rt_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_rt_2_t { + unsigned int blue : SQ_CONSTANT_RT_2_BLUE_SIZE; + } sq_constant_rt_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_rt_2_t f; +} sq_constant_rt_2_u; + + +/* + * SQ_CONSTANT_RT_3 struct + */ + +#define SQ_CONSTANT_RT_3_ALPHA_SIZE 32 + +#define SQ_CONSTANT_RT_3_ALPHA_SHIFT 0 + +#define SQ_CONSTANT_RT_3_ALPHA_MASK 0xffffffff + +#define SQ_CONSTANT_RT_3_MASK \ + (SQ_CONSTANT_RT_3_ALPHA_MASK) + +#define SQ_CONSTANT_RT_3(alpha) \ + ((alpha << SQ_CONSTANT_RT_3_ALPHA_SHIFT)) + +#define SQ_CONSTANT_RT_3_GET_ALPHA(sq_constant_rt_3) \ + ((sq_constant_rt_3 & SQ_CONSTANT_RT_3_ALPHA_MASK) >> SQ_CONSTANT_RT_3_ALPHA_SHIFT) + +#define SQ_CONSTANT_RT_3_SET_ALPHA(sq_constant_rt_3_reg, alpha) \ + sq_constant_rt_3_reg = (sq_constant_rt_3_reg & ~SQ_CONSTANT_RT_3_ALPHA_MASK) | (alpha << SQ_CONSTANT_RT_3_ALPHA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_rt_3_t { + unsigned int alpha : SQ_CONSTANT_RT_3_ALPHA_SIZE; + } sq_constant_rt_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_rt_3_t { + unsigned int alpha : SQ_CONSTANT_RT_3_ALPHA_SIZE; + } sq_constant_rt_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_rt_3_t f; +} sq_constant_rt_3_u; + + +/* + * SQ_FETCH_RT_0 struct + */ + +#define SQ_FETCH_RT_0_VALUE_SIZE 32 + +#define SQ_FETCH_RT_0_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_0_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_0_MASK \ + (SQ_FETCH_RT_0_VALUE_MASK) + +#define SQ_FETCH_RT_0(value) \ + ((value << SQ_FETCH_RT_0_VALUE_SHIFT)) + +#define SQ_FETCH_RT_0_GET_VALUE(sq_fetch_rt_0) \ + ((sq_fetch_rt_0 & SQ_FETCH_RT_0_VALUE_MASK) >> SQ_FETCH_RT_0_VALUE_SHIFT) + +#define SQ_FETCH_RT_0_SET_VALUE(sq_fetch_rt_0_reg, value) \ + sq_fetch_rt_0_reg = (sq_fetch_rt_0_reg & ~SQ_FETCH_RT_0_VALUE_MASK) | (value << SQ_FETCH_RT_0_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_0_t { + unsigned int value : SQ_FETCH_RT_0_VALUE_SIZE; + } sq_fetch_rt_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_0_t { + unsigned int value : SQ_FETCH_RT_0_VALUE_SIZE; + } sq_fetch_rt_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_0_t f; +} sq_fetch_rt_0_u; + + +/* + * SQ_FETCH_RT_1 struct + */ + +#define SQ_FETCH_RT_1_VALUE_SIZE 32 + +#define SQ_FETCH_RT_1_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_1_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_1_MASK \ + (SQ_FETCH_RT_1_VALUE_MASK) + +#define SQ_FETCH_RT_1(value) \ + ((value << SQ_FETCH_RT_1_VALUE_SHIFT)) + +#define SQ_FETCH_RT_1_GET_VALUE(sq_fetch_rt_1) \ + ((sq_fetch_rt_1 & SQ_FETCH_RT_1_VALUE_MASK) >> SQ_FETCH_RT_1_VALUE_SHIFT) + +#define SQ_FETCH_RT_1_SET_VALUE(sq_fetch_rt_1_reg, value) \ + sq_fetch_rt_1_reg = (sq_fetch_rt_1_reg & ~SQ_FETCH_RT_1_VALUE_MASK) | (value << SQ_FETCH_RT_1_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_1_t { + unsigned int value : SQ_FETCH_RT_1_VALUE_SIZE; + } sq_fetch_rt_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_1_t { + unsigned int value : SQ_FETCH_RT_1_VALUE_SIZE; + } sq_fetch_rt_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_1_t f; +} sq_fetch_rt_1_u; + + +/* + * SQ_FETCH_RT_2 struct + */ + +#define SQ_FETCH_RT_2_VALUE_SIZE 32 + +#define SQ_FETCH_RT_2_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_2_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_2_MASK \ + (SQ_FETCH_RT_2_VALUE_MASK) + +#define SQ_FETCH_RT_2(value) \ + ((value << SQ_FETCH_RT_2_VALUE_SHIFT)) + +#define SQ_FETCH_RT_2_GET_VALUE(sq_fetch_rt_2) \ + ((sq_fetch_rt_2 & SQ_FETCH_RT_2_VALUE_MASK) >> SQ_FETCH_RT_2_VALUE_SHIFT) + +#define SQ_FETCH_RT_2_SET_VALUE(sq_fetch_rt_2_reg, value) \ + sq_fetch_rt_2_reg = (sq_fetch_rt_2_reg & ~SQ_FETCH_RT_2_VALUE_MASK) | (value << SQ_FETCH_RT_2_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_2_t { + unsigned int value : SQ_FETCH_RT_2_VALUE_SIZE; + } sq_fetch_rt_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_2_t { + unsigned int value : SQ_FETCH_RT_2_VALUE_SIZE; + } sq_fetch_rt_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_2_t f; +} sq_fetch_rt_2_u; + + +/* + * SQ_FETCH_RT_3 struct + */ + +#define SQ_FETCH_RT_3_VALUE_SIZE 32 + +#define SQ_FETCH_RT_3_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_3_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_3_MASK \ + (SQ_FETCH_RT_3_VALUE_MASK) + +#define SQ_FETCH_RT_3(value) \ + ((value << SQ_FETCH_RT_3_VALUE_SHIFT)) + +#define SQ_FETCH_RT_3_GET_VALUE(sq_fetch_rt_3) \ + ((sq_fetch_rt_3 & SQ_FETCH_RT_3_VALUE_MASK) >> SQ_FETCH_RT_3_VALUE_SHIFT) + +#define SQ_FETCH_RT_3_SET_VALUE(sq_fetch_rt_3_reg, value) \ + sq_fetch_rt_3_reg = (sq_fetch_rt_3_reg & ~SQ_FETCH_RT_3_VALUE_MASK) | (value << SQ_FETCH_RT_3_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_3_t { + unsigned int value : SQ_FETCH_RT_3_VALUE_SIZE; + } sq_fetch_rt_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_3_t { + unsigned int value : SQ_FETCH_RT_3_VALUE_SIZE; + } sq_fetch_rt_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_3_t f; +} sq_fetch_rt_3_u; + + +/* + * SQ_FETCH_RT_4 struct + */ + +#define SQ_FETCH_RT_4_VALUE_SIZE 32 + +#define SQ_FETCH_RT_4_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_4_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_4_MASK \ + (SQ_FETCH_RT_4_VALUE_MASK) + +#define SQ_FETCH_RT_4(value) \ + ((value << SQ_FETCH_RT_4_VALUE_SHIFT)) + +#define SQ_FETCH_RT_4_GET_VALUE(sq_fetch_rt_4) \ + ((sq_fetch_rt_4 & SQ_FETCH_RT_4_VALUE_MASK) >> SQ_FETCH_RT_4_VALUE_SHIFT) + +#define SQ_FETCH_RT_4_SET_VALUE(sq_fetch_rt_4_reg, value) \ + sq_fetch_rt_4_reg = (sq_fetch_rt_4_reg & ~SQ_FETCH_RT_4_VALUE_MASK) | (value << SQ_FETCH_RT_4_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_4_t { + unsigned int value : SQ_FETCH_RT_4_VALUE_SIZE; + } sq_fetch_rt_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_4_t { + unsigned int value : SQ_FETCH_RT_4_VALUE_SIZE; + } sq_fetch_rt_4_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_4_t f; +} sq_fetch_rt_4_u; + + +/* + * SQ_FETCH_RT_5 struct + */ + +#define SQ_FETCH_RT_5_VALUE_SIZE 32 + +#define SQ_FETCH_RT_5_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_5_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_5_MASK \ + (SQ_FETCH_RT_5_VALUE_MASK) + +#define SQ_FETCH_RT_5(value) \ + ((value << SQ_FETCH_RT_5_VALUE_SHIFT)) + +#define SQ_FETCH_RT_5_GET_VALUE(sq_fetch_rt_5) \ + ((sq_fetch_rt_5 & SQ_FETCH_RT_5_VALUE_MASK) >> SQ_FETCH_RT_5_VALUE_SHIFT) + +#define SQ_FETCH_RT_5_SET_VALUE(sq_fetch_rt_5_reg, value) \ + sq_fetch_rt_5_reg = (sq_fetch_rt_5_reg & ~SQ_FETCH_RT_5_VALUE_MASK) | (value << SQ_FETCH_RT_5_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_5_t { + unsigned int value : SQ_FETCH_RT_5_VALUE_SIZE; + } sq_fetch_rt_5_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_5_t { + unsigned int value : SQ_FETCH_RT_5_VALUE_SIZE; + } sq_fetch_rt_5_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_5_t f; +} sq_fetch_rt_5_u; + + +/* + * SQ_CF_RT_BOOLEANS struct + */ + +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE 8 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE 8 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE 8 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE 8 + +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT 0 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT 8 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT 16 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT 24 + +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK 0x000000ff +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK 0x0000ff00 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK 0x00ff0000 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK 0xff000000 + +#define SQ_CF_RT_BOOLEANS_MASK \ + (SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK | \ + SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK | \ + SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK | \ + SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) + +#define SQ_CF_RT_BOOLEANS(cf_booleans_0, cf_booleans_1, cf_booleans_2, cf_booleans_3) \ + ((cf_booleans_0 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT) | \ + (cf_booleans_1 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT) | \ + (cf_booleans_2 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT) | \ + (cf_booleans_3 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT)) + +#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_0(sq_cf_rt_booleans) \ + ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT) +#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_1(sq_cf_rt_booleans) \ + ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT) +#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_2(sq_cf_rt_booleans) \ + ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT) +#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_3(sq_cf_rt_booleans) \ + ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT) + +#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_0(sq_cf_rt_booleans_reg, cf_booleans_0) \ + sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK) | (cf_booleans_0 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT) +#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_1(sq_cf_rt_booleans_reg, cf_booleans_1) \ + sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK) | (cf_booleans_1 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT) +#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_2(sq_cf_rt_booleans_reg, cf_booleans_2) \ + sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK) | (cf_booleans_2 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT) +#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_3(sq_cf_rt_booleans_reg, cf_booleans_3) \ + sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) | (cf_booleans_3 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_rt_booleans_t { + unsigned int cf_booleans_0 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE; + unsigned int cf_booleans_1 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE; + unsigned int cf_booleans_2 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE; + unsigned int cf_booleans_3 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE; + } sq_cf_rt_booleans_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_rt_booleans_t { + unsigned int cf_booleans_3 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE; + unsigned int cf_booleans_2 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE; + unsigned int cf_booleans_1 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE; + unsigned int cf_booleans_0 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE; + } sq_cf_rt_booleans_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_rt_booleans_t f; +} sq_cf_rt_booleans_u; + + +/* + * SQ_CF_RT_LOOP struct + */ + +#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE 8 +#define SQ_CF_RT_LOOP_CF_LOOP_START_SIZE 8 +#define SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE 8 + +#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT 0 +#define SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT 8 +#define SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT 16 + +#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK 0x000000ff +#define SQ_CF_RT_LOOP_CF_LOOP_START_MASK 0x0000ff00 +#define SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK 0x00ff0000 + +#define SQ_CF_RT_LOOP_MASK \ + (SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK | \ + SQ_CF_RT_LOOP_CF_LOOP_START_MASK | \ + SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) + +#define SQ_CF_RT_LOOP(cf_loop_count, cf_loop_start, cf_loop_step) \ + ((cf_loop_count << SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT) | \ + (cf_loop_start << SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT) | \ + (cf_loop_step << SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT)) + +#define SQ_CF_RT_LOOP_GET_CF_LOOP_COUNT(sq_cf_rt_loop) \ + ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT) +#define SQ_CF_RT_LOOP_GET_CF_LOOP_START(sq_cf_rt_loop) \ + ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_START_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT) +#define SQ_CF_RT_LOOP_GET_CF_LOOP_STEP(sq_cf_rt_loop) \ + ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT) + +#define SQ_CF_RT_LOOP_SET_CF_LOOP_COUNT(sq_cf_rt_loop_reg, cf_loop_count) \ + sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK) | (cf_loop_count << SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT) +#define SQ_CF_RT_LOOP_SET_CF_LOOP_START(sq_cf_rt_loop_reg, cf_loop_start) \ + sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_START_MASK) | (cf_loop_start << SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT) +#define SQ_CF_RT_LOOP_SET_CF_LOOP_STEP(sq_cf_rt_loop_reg, cf_loop_step) \ + sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) | (cf_loop_step << SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_rt_loop_t { + unsigned int cf_loop_count : SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE; + unsigned int cf_loop_start : SQ_CF_RT_LOOP_CF_LOOP_START_SIZE; + unsigned int cf_loop_step : SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE; + unsigned int : 8; + } sq_cf_rt_loop_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_rt_loop_t { + unsigned int : 8; + unsigned int cf_loop_step : SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE; + unsigned int cf_loop_start : SQ_CF_RT_LOOP_CF_LOOP_START_SIZE; + unsigned int cf_loop_count : SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE; + } sq_cf_rt_loop_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_rt_loop_t f; +} sq_cf_rt_loop_u; + + +/* + * SQ_VS_PROGRAM struct + */ + +#define SQ_VS_PROGRAM_BASE_SIZE 12 +#define SQ_VS_PROGRAM_SIZE_SIZE 12 + +#define SQ_VS_PROGRAM_BASE_SHIFT 0 +#define SQ_VS_PROGRAM_SIZE_SHIFT 12 + +#define SQ_VS_PROGRAM_BASE_MASK 0x00000fff +#define SQ_VS_PROGRAM_SIZE_MASK 0x00fff000 + +#define SQ_VS_PROGRAM_MASK \ + (SQ_VS_PROGRAM_BASE_MASK | \ + SQ_VS_PROGRAM_SIZE_MASK) + +#define SQ_VS_PROGRAM(base, size) \ + ((base << SQ_VS_PROGRAM_BASE_SHIFT) | \ + (size << SQ_VS_PROGRAM_SIZE_SHIFT)) + +#define SQ_VS_PROGRAM_GET_BASE(sq_vs_program) \ + ((sq_vs_program & SQ_VS_PROGRAM_BASE_MASK) >> SQ_VS_PROGRAM_BASE_SHIFT) +#define SQ_VS_PROGRAM_GET_SIZE(sq_vs_program) \ + ((sq_vs_program & SQ_VS_PROGRAM_SIZE_MASK) >> SQ_VS_PROGRAM_SIZE_SHIFT) + +#define SQ_VS_PROGRAM_SET_BASE(sq_vs_program_reg, base) \ + sq_vs_program_reg = (sq_vs_program_reg & ~SQ_VS_PROGRAM_BASE_MASK) | (base << SQ_VS_PROGRAM_BASE_SHIFT) +#define SQ_VS_PROGRAM_SET_SIZE(sq_vs_program_reg, size) \ + sq_vs_program_reg = (sq_vs_program_reg & ~SQ_VS_PROGRAM_SIZE_MASK) | (size << SQ_VS_PROGRAM_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_vs_program_t { + unsigned int base : SQ_VS_PROGRAM_BASE_SIZE; + unsigned int size : SQ_VS_PROGRAM_SIZE_SIZE; + unsigned int : 8; + } sq_vs_program_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_vs_program_t { + unsigned int : 8; + unsigned int size : SQ_VS_PROGRAM_SIZE_SIZE; + unsigned int base : SQ_VS_PROGRAM_BASE_SIZE; + } sq_vs_program_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_vs_program_t f; +} sq_vs_program_u; + + +/* + * SQ_PS_PROGRAM struct + */ + +#define SQ_PS_PROGRAM_BASE_SIZE 12 +#define SQ_PS_PROGRAM_SIZE_SIZE 12 + +#define SQ_PS_PROGRAM_BASE_SHIFT 0 +#define SQ_PS_PROGRAM_SIZE_SHIFT 12 + +#define SQ_PS_PROGRAM_BASE_MASK 0x00000fff +#define SQ_PS_PROGRAM_SIZE_MASK 0x00fff000 + +#define SQ_PS_PROGRAM_MASK \ + (SQ_PS_PROGRAM_BASE_MASK | \ + SQ_PS_PROGRAM_SIZE_MASK) + +#define SQ_PS_PROGRAM(base, size) \ + ((base << SQ_PS_PROGRAM_BASE_SHIFT) | \ + (size << SQ_PS_PROGRAM_SIZE_SHIFT)) + +#define SQ_PS_PROGRAM_GET_BASE(sq_ps_program) \ + ((sq_ps_program & SQ_PS_PROGRAM_BASE_MASK) >> SQ_PS_PROGRAM_BASE_SHIFT) +#define SQ_PS_PROGRAM_GET_SIZE(sq_ps_program) \ + ((sq_ps_program & SQ_PS_PROGRAM_SIZE_MASK) >> SQ_PS_PROGRAM_SIZE_SHIFT) + +#define SQ_PS_PROGRAM_SET_BASE(sq_ps_program_reg, base) \ + sq_ps_program_reg = (sq_ps_program_reg & ~SQ_PS_PROGRAM_BASE_MASK) | (base << SQ_PS_PROGRAM_BASE_SHIFT) +#define SQ_PS_PROGRAM_SET_SIZE(sq_ps_program_reg, size) \ + sq_ps_program_reg = (sq_ps_program_reg & ~SQ_PS_PROGRAM_SIZE_MASK) | (size << SQ_PS_PROGRAM_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_ps_program_t { + unsigned int base : SQ_PS_PROGRAM_BASE_SIZE; + unsigned int size : SQ_PS_PROGRAM_SIZE_SIZE; + unsigned int : 8; + } sq_ps_program_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_ps_program_t { + unsigned int : 8; + unsigned int size : SQ_PS_PROGRAM_SIZE_SIZE; + unsigned int base : SQ_PS_PROGRAM_BASE_SIZE; + } sq_ps_program_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_ps_program_t f; +} sq_ps_program_u; + + +/* + * SQ_CF_PROGRAM_SIZE struct + */ + +#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE 11 +#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE 11 + +#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT 0 +#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT 12 + +#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK 0x000007ff +#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK 0x007ff000 + +#define SQ_CF_PROGRAM_SIZE_MASK \ + (SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK | \ + SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) + +#define SQ_CF_PROGRAM_SIZE(vs_cf_size, ps_cf_size) \ + ((vs_cf_size << SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT) | \ + (ps_cf_size << SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT)) + +#define SQ_CF_PROGRAM_SIZE_GET_VS_CF_SIZE(sq_cf_program_size) \ + ((sq_cf_program_size & SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK) >> SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT) +#define SQ_CF_PROGRAM_SIZE_GET_PS_CF_SIZE(sq_cf_program_size) \ + ((sq_cf_program_size & SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) >> SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT) + +#define SQ_CF_PROGRAM_SIZE_SET_VS_CF_SIZE(sq_cf_program_size_reg, vs_cf_size) \ + sq_cf_program_size_reg = (sq_cf_program_size_reg & ~SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK) | (vs_cf_size << SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT) +#define SQ_CF_PROGRAM_SIZE_SET_PS_CF_SIZE(sq_cf_program_size_reg, ps_cf_size) \ + sq_cf_program_size_reg = (sq_cf_program_size_reg & ~SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) | (ps_cf_size << SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_program_size_t { + unsigned int vs_cf_size : SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE; + unsigned int : 1; + unsigned int ps_cf_size : SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE; + unsigned int : 9; + } sq_cf_program_size_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_program_size_t { + unsigned int : 9; + unsigned int ps_cf_size : SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE; + unsigned int : 1; + unsigned int vs_cf_size : SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE; + } sq_cf_program_size_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_program_size_t f; +} sq_cf_program_size_u; + + +/* + * SQ_INTERPOLATOR_CNTL struct + */ + +#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE 16 +#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE 16 + +#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT 0 +#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT 16 + +#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK 0x0000ffff +#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK 0xffff0000 + +#define SQ_INTERPOLATOR_CNTL_MASK \ + (SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK | \ + SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) + +#define SQ_INTERPOLATOR_CNTL(param_shade, sampling_pattern) \ + ((param_shade << SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT) | \ + (sampling_pattern << SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT)) + +#define SQ_INTERPOLATOR_CNTL_GET_PARAM_SHADE(sq_interpolator_cntl) \ + ((sq_interpolator_cntl & SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK) >> SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT) +#define SQ_INTERPOLATOR_CNTL_GET_SAMPLING_PATTERN(sq_interpolator_cntl) \ + ((sq_interpolator_cntl & SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) >> SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT) + +#define SQ_INTERPOLATOR_CNTL_SET_PARAM_SHADE(sq_interpolator_cntl_reg, param_shade) \ + sq_interpolator_cntl_reg = (sq_interpolator_cntl_reg & ~SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK) | (param_shade << SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT) +#define SQ_INTERPOLATOR_CNTL_SET_SAMPLING_PATTERN(sq_interpolator_cntl_reg, sampling_pattern) \ + sq_interpolator_cntl_reg = (sq_interpolator_cntl_reg & ~SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) | (sampling_pattern << SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_interpolator_cntl_t { + unsigned int param_shade : SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE; + unsigned int sampling_pattern : SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE; + } sq_interpolator_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_interpolator_cntl_t { + unsigned int sampling_pattern : SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE; + unsigned int param_shade : SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE; + } sq_interpolator_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_interpolator_cntl_t f; +} sq_interpolator_cntl_u; + + +/* + * SQ_PROGRAM_CNTL struct + */ + +#define SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE 6 +#define SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE 6 +#define SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE 1 +#define SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE 1 +#define SQ_PROGRAM_CNTL_PARAM_GEN_SIZE 1 +#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE 1 +#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE 4 +#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE 3 +#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE 4 +#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE 1 + +#define SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT 0 +#define SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT 8 +#define SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT 16 +#define SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT 17 +#define SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT 18 +#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT 19 +#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT 20 +#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT 24 +#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT 27 +#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT 31 + +#define SQ_PROGRAM_CNTL_VS_NUM_REG_MASK 0x0000003f +#define SQ_PROGRAM_CNTL_PS_NUM_REG_MASK 0x00003f00 +#define SQ_PROGRAM_CNTL_VS_RESOURCE_MASK 0x00010000 +#define SQ_PROGRAM_CNTL_PS_RESOURCE_MASK 0x00020000 +#define SQ_PROGRAM_CNTL_PARAM_GEN_MASK 0x00040000 +#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK 0x00080000 +#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK 0x00f00000 +#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK 0x07000000 +#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK 0x78000000 +#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK 0x80000000 + +#define SQ_PROGRAM_CNTL_MASK \ + (SQ_PROGRAM_CNTL_VS_NUM_REG_MASK | \ + SQ_PROGRAM_CNTL_PS_NUM_REG_MASK | \ + SQ_PROGRAM_CNTL_VS_RESOURCE_MASK | \ + SQ_PROGRAM_CNTL_PS_RESOURCE_MASK | \ + SQ_PROGRAM_CNTL_PARAM_GEN_MASK | \ + SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK | \ + SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK | \ + SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK | \ + SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK | \ + SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) + +#define SQ_PROGRAM_CNTL(vs_num_reg, ps_num_reg, vs_resource, ps_resource, param_gen, gen_index_pix, vs_export_count, vs_export_mode, ps_export_mode, gen_index_vtx) \ + ((vs_num_reg << SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT) | \ + (ps_num_reg << SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT) | \ + (vs_resource << SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT) | \ + (ps_resource << SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT) | \ + (param_gen << SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT) | \ + (gen_index_pix << SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT) | \ + (vs_export_count << SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT) | \ + (vs_export_mode << SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT) | \ + (ps_export_mode << SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT) | \ + (gen_index_vtx << SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT)) + +#define SQ_PROGRAM_CNTL_GET_VS_NUM_REG(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_NUM_REG_MASK) >> SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT) +#define SQ_PROGRAM_CNTL_GET_PS_NUM_REG(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_NUM_REG_MASK) >> SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT) +#define SQ_PROGRAM_CNTL_GET_VS_RESOURCE(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_RESOURCE_MASK) >> SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT) +#define SQ_PROGRAM_CNTL_GET_PS_RESOURCE(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_RESOURCE_MASK) >> SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT) +#define SQ_PROGRAM_CNTL_GET_PARAM_GEN(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_PARAM_GEN_MASK) >> SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT) +#define SQ_PROGRAM_CNTL_GET_GEN_INDEX_PIX(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK) >> SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT) +#define SQ_PROGRAM_CNTL_GET_VS_EXPORT_COUNT(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK) >> SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT) +#define SQ_PROGRAM_CNTL_GET_VS_EXPORT_MODE(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK) >> SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT) +#define SQ_PROGRAM_CNTL_GET_PS_EXPORT_MODE(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK) >> SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT) +#define SQ_PROGRAM_CNTL_GET_GEN_INDEX_VTX(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) >> SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT) + +#define SQ_PROGRAM_CNTL_SET_VS_NUM_REG(sq_program_cntl_reg, vs_num_reg) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_NUM_REG_MASK) | (vs_num_reg << SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT) +#define SQ_PROGRAM_CNTL_SET_PS_NUM_REG(sq_program_cntl_reg, ps_num_reg) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_NUM_REG_MASK) | (ps_num_reg << SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT) +#define SQ_PROGRAM_CNTL_SET_VS_RESOURCE(sq_program_cntl_reg, vs_resource) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_RESOURCE_MASK) | (vs_resource << SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT) +#define SQ_PROGRAM_CNTL_SET_PS_RESOURCE(sq_program_cntl_reg, ps_resource) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_RESOURCE_MASK) | (ps_resource << SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT) +#define SQ_PROGRAM_CNTL_SET_PARAM_GEN(sq_program_cntl_reg, param_gen) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PARAM_GEN_MASK) | (param_gen << SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT) +#define SQ_PROGRAM_CNTL_SET_GEN_INDEX_PIX(sq_program_cntl_reg, gen_index_pix) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK) | (gen_index_pix << SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT) +#define SQ_PROGRAM_CNTL_SET_VS_EXPORT_COUNT(sq_program_cntl_reg, vs_export_count) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK) | (vs_export_count << SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT) +#define SQ_PROGRAM_CNTL_SET_VS_EXPORT_MODE(sq_program_cntl_reg, vs_export_mode) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK) | (vs_export_mode << SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT) +#define SQ_PROGRAM_CNTL_SET_PS_EXPORT_MODE(sq_program_cntl_reg, ps_export_mode) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK) | (ps_export_mode << SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT) +#define SQ_PROGRAM_CNTL_SET_GEN_INDEX_VTX(sq_program_cntl_reg, gen_index_vtx) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) | (gen_index_vtx << SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_program_cntl_t { + unsigned int vs_num_reg : SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE; + unsigned int : 2; + unsigned int ps_num_reg : SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE; + unsigned int : 2; + unsigned int vs_resource : SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE; + unsigned int ps_resource : SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE; + unsigned int param_gen : SQ_PROGRAM_CNTL_PARAM_GEN_SIZE; + unsigned int gen_index_pix : SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE; + unsigned int vs_export_count : SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE; + unsigned int vs_export_mode : SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE; + unsigned int ps_export_mode : SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE; + unsigned int gen_index_vtx : SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE; + } sq_program_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_program_cntl_t { + unsigned int gen_index_vtx : SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE; + unsigned int ps_export_mode : SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE; + unsigned int vs_export_mode : SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE; + unsigned int vs_export_count : SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE; + unsigned int gen_index_pix : SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE; + unsigned int param_gen : SQ_PROGRAM_CNTL_PARAM_GEN_SIZE; + unsigned int ps_resource : SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE; + unsigned int vs_resource : SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE; + unsigned int : 2; + unsigned int ps_num_reg : SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE; + unsigned int : 2; + unsigned int vs_num_reg : SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE; + } sq_program_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_program_cntl_t f; +} sq_program_cntl_u; + + +/* + * SQ_WRAPPING_0 struct + */ + +#define SQ_WRAPPING_0_PARAM_WRAP_0_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_1_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_2_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_3_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_4_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_5_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_6_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_7_SIZE 4 + +#define SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT 0 +#define SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT 4 +#define SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT 8 +#define SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT 12 +#define SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT 16 +#define SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT 20 +#define SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT 24 +#define SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT 28 + +#define SQ_WRAPPING_0_PARAM_WRAP_0_MASK 0x0000000f +#define SQ_WRAPPING_0_PARAM_WRAP_1_MASK 0x000000f0 +#define SQ_WRAPPING_0_PARAM_WRAP_2_MASK 0x00000f00 +#define SQ_WRAPPING_0_PARAM_WRAP_3_MASK 0x0000f000 +#define SQ_WRAPPING_0_PARAM_WRAP_4_MASK 0x000f0000 +#define SQ_WRAPPING_0_PARAM_WRAP_5_MASK 0x00f00000 +#define SQ_WRAPPING_0_PARAM_WRAP_6_MASK 0x0f000000 +#define SQ_WRAPPING_0_PARAM_WRAP_7_MASK 0xf0000000 + +#define SQ_WRAPPING_0_MASK \ + (SQ_WRAPPING_0_PARAM_WRAP_0_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_1_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_2_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_3_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_4_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_5_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_6_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_7_MASK) + +#define SQ_WRAPPING_0(param_wrap_0, param_wrap_1, param_wrap_2, param_wrap_3, param_wrap_4, param_wrap_5, param_wrap_6, param_wrap_7) \ + ((param_wrap_0 << SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT) | \ + (param_wrap_1 << SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT) | \ + (param_wrap_2 << SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT) | \ + (param_wrap_3 << SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT) | \ + (param_wrap_4 << SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT) | \ + (param_wrap_5 << SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT) | \ + (param_wrap_6 << SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT) | \ + (param_wrap_7 << SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT)) + +#define SQ_WRAPPING_0_GET_PARAM_WRAP_0(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_0_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_1(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_1_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_2(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_2_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_3(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_3_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_4(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_4_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_5(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_5_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_6(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_6_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_7(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_7_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT) + +#define SQ_WRAPPING_0_SET_PARAM_WRAP_0(sq_wrapping_0_reg, param_wrap_0) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_0_MASK) | (param_wrap_0 << SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_1(sq_wrapping_0_reg, param_wrap_1) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_1_MASK) | (param_wrap_1 << SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_2(sq_wrapping_0_reg, param_wrap_2) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_2_MASK) | (param_wrap_2 << SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_3(sq_wrapping_0_reg, param_wrap_3) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_3_MASK) | (param_wrap_3 << SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_4(sq_wrapping_0_reg, param_wrap_4) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_4_MASK) | (param_wrap_4 << SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_5(sq_wrapping_0_reg, param_wrap_5) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_5_MASK) | (param_wrap_5 << SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_6(sq_wrapping_0_reg, param_wrap_6) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_6_MASK) | (param_wrap_6 << SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_7(sq_wrapping_0_reg, param_wrap_7) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_7_MASK) | (param_wrap_7 << SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_wrapping_0_t { + unsigned int param_wrap_0 : SQ_WRAPPING_0_PARAM_WRAP_0_SIZE; + unsigned int param_wrap_1 : SQ_WRAPPING_0_PARAM_WRAP_1_SIZE; + unsigned int param_wrap_2 : SQ_WRAPPING_0_PARAM_WRAP_2_SIZE; + unsigned int param_wrap_3 : SQ_WRAPPING_0_PARAM_WRAP_3_SIZE; + unsigned int param_wrap_4 : SQ_WRAPPING_0_PARAM_WRAP_4_SIZE; + unsigned int param_wrap_5 : SQ_WRAPPING_0_PARAM_WRAP_5_SIZE; + unsigned int param_wrap_6 : SQ_WRAPPING_0_PARAM_WRAP_6_SIZE; + unsigned int param_wrap_7 : SQ_WRAPPING_0_PARAM_WRAP_7_SIZE; + } sq_wrapping_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_wrapping_0_t { + unsigned int param_wrap_7 : SQ_WRAPPING_0_PARAM_WRAP_7_SIZE; + unsigned int param_wrap_6 : SQ_WRAPPING_0_PARAM_WRAP_6_SIZE; + unsigned int param_wrap_5 : SQ_WRAPPING_0_PARAM_WRAP_5_SIZE; + unsigned int param_wrap_4 : SQ_WRAPPING_0_PARAM_WRAP_4_SIZE; + unsigned int param_wrap_3 : SQ_WRAPPING_0_PARAM_WRAP_3_SIZE; + unsigned int param_wrap_2 : SQ_WRAPPING_0_PARAM_WRAP_2_SIZE; + unsigned int param_wrap_1 : SQ_WRAPPING_0_PARAM_WRAP_1_SIZE; + unsigned int param_wrap_0 : SQ_WRAPPING_0_PARAM_WRAP_0_SIZE; + } sq_wrapping_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_wrapping_0_t f; +} sq_wrapping_0_u; + + +/* + * SQ_WRAPPING_1 struct + */ + +#define SQ_WRAPPING_1_PARAM_WRAP_8_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_9_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_10_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_11_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_12_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_13_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_14_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_15_SIZE 4 + +#define SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT 0 +#define SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT 4 +#define SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT 8 +#define SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT 12 +#define SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT 16 +#define SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT 20 +#define SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT 24 +#define SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT 28 + +#define SQ_WRAPPING_1_PARAM_WRAP_8_MASK 0x0000000f +#define SQ_WRAPPING_1_PARAM_WRAP_9_MASK 0x000000f0 +#define SQ_WRAPPING_1_PARAM_WRAP_10_MASK 0x00000f00 +#define SQ_WRAPPING_1_PARAM_WRAP_11_MASK 0x0000f000 +#define SQ_WRAPPING_1_PARAM_WRAP_12_MASK 0x000f0000 +#define SQ_WRAPPING_1_PARAM_WRAP_13_MASK 0x00f00000 +#define SQ_WRAPPING_1_PARAM_WRAP_14_MASK 0x0f000000 +#define SQ_WRAPPING_1_PARAM_WRAP_15_MASK 0xf0000000 + +#define SQ_WRAPPING_1_MASK \ + (SQ_WRAPPING_1_PARAM_WRAP_8_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_9_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_10_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_11_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_12_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_13_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_14_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_15_MASK) + +#define SQ_WRAPPING_1(param_wrap_8, param_wrap_9, param_wrap_10, param_wrap_11, param_wrap_12, param_wrap_13, param_wrap_14, param_wrap_15) \ + ((param_wrap_8 << SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT) | \ + (param_wrap_9 << SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT) | \ + (param_wrap_10 << SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT) | \ + (param_wrap_11 << SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT) | \ + (param_wrap_12 << SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT) | \ + (param_wrap_13 << SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT) | \ + (param_wrap_14 << SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT) | \ + (param_wrap_15 << SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT)) + +#define SQ_WRAPPING_1_GET_PARAM_WRAP_8(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_8_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_9(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_9_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_10(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_10_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_11(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_11_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_12(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_12_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_13(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_13_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_14(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_14_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_15(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_15_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT) + +#define SQ_WRAPPING_1_SET_PARAM_WRAP_8(sq_wrapping_1_reg, param_wrap_8) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_8_MASK) | (param_wrap_8 << SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_9(sq_wrapping_1_reg, param_wrap_9) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_9_MASK) | (param_wrap_9 << SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_10(sq_wrapping_1_reg, param_wrap_10) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_10_MASK) | (param_wrap_10 << SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_11(sq_wrapping_1_reg, param_wrap_11) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_11_MASK) | (param_wrap_11 << SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_12(sq_wrapping_1_reg, param_wrap_12) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_12_MASK) | (param_wrap_12 << SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_13(sq_wrapping_1_reg, param_wrap_13) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_13_MASK) | (param_wrap_13 << SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_14(sq_wrapping_1_reg, param_wrap_14) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_14_MASK) | (param_wrap_14 << SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_15(sq_wrapping_1_reg, param_wrap_15) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_15_MASK) | (param_wrap_15 << SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_wrapping_1_t { + unsigned int param_wrap_8 : SQ_WRAPPING_1_PARAM_WRAP_8_SIZE; + unsigned int param_wrap_9 : SQ_WRAPPING_1_PARAM_WRAP_9_SIZE; + unsigned int param_wrap_10 : SQ_WRAPPING_1_PARAM_WRAP_10_SIZE; + unsigned int param_wrap_11 : SQ_WRAPPING_1_PARAM_WRAP_11_SIZE; + unsigned int param_wrap_12 : SQ_WRAPPING_1_PARAM_WRAP_12_SIZE; + unsigned int param_wrap_13 : SQ_WRAPPING_1_PARAM_WRAP_13_SIZE; + unsigned int param_wrap_14 : SQ_WRAPPING_1_PARAM_WRAP_14_SIZE; + unsigned int param_wrap_15 : SQ_WRAPPING_1_PARAM_WRAP_15_SIZE; + } sq_wrapping_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_wrapping_1_t { + unsigned int param_wrap_15 : SQ_WRAPPING_1_PARAM_WRAP_15_SIZE; + unsigned int param_wrap_14 : SQ_WRAPPING_1_PARAM_WRAP_14_SIZE; + unsigned int param_wrap_13 : SQ_WRAPPING_1_PARAM_WRAP_13_SIZE; + unsigned int param_wrap_12 : SQ_WRAPPING_1_PARAM_WRAP_12_SIZE; + unsigned int param_wrap_11 : SQ_WRAPPING_1_PARAM_WRAP_11_SIZE; + unsigned int param_wrap_10 : SQ_WRAPPING_1_PARAM_WRAP_10_SIZE; + unsigned int param_wrap_9 : SQ_WRAPPING_1_PARAM_WRAP_9_SIZE; + unsigned int param_wrap_8 : SQ_WRAPPING_1_PARAM_WRAP_8_SIZE; + } sq_wrapping_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_wrapping_1_t f; +} sq_wrapping_1_u; + + +/* + * SQ_VS_CONST struct + */ + +#define SQ_VS_CONST_BASE_SIZE 9 +#define SQ_VS_CONST_SIZE_SIZE 9 + +#define SQ_VS_CONST_BASE_SHIFT 0 +#define SQ_VS_CONST_SIZE_SHIFT 12 + +#define SQ_VS_CONST_BASE_MASK 0x000001ff +#define SQ_VS_CONST_SIZE_MASK 0x001ff000 + +#define SQ_VS_CONST_MASK \ + (SQ_VS_CONST_BASE_MASK | \ + SQ_VS_CONST_SIZE_MASK) + +#define SQ_VS_CONST(base, size) \ + ((base << SQ_VS_CONST_BASE_SHIFT) | \ + (size << SQ_VS_CONST_SIZE_SHIFT)) + +#define SQ_VS_CONST_GET_BASE(sq_vs_const) \ + ((sq_vs_const & SQ_VS_CONST_BASE_MASK) >> SQ_VS_CONST_BASE_SHIFT) +#define SQ_VS_CONST_GET_SIZE(sq_vs_const) \ + ((sq_vs_const & SQ_VS_CONST_SIZE_MASK) >> SQ_VS_CONST_SIZE_SHIFT) + +#define SQ_VS_CONST_SET_BASE(sq_vs_const_reg, base) \ + sq_vs_const_reg = (sq_vs_const_reg & ~SQ_VS_CONST_BASE_MASK) | (base << SQ_VS_CONST_BASE_SHIFT) +#define SQ_VS_CONST_SET_SIZE(sq_vs_const_reg, size) \ + sq_vs_const_reg = (sq_vs_const_reg & ~SQ_VS_CONST_SIZE_MASK) | (size << SQ_VS_CONST_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_vs_const_t { + unsigned int base : SQ_VS_CONST_BASE_SIZE; + unsigned int : 3; + unsigned int size : SQ_VS_CONST_SIZE_SIZE; + unsigned int : 11; + } sq_vs_const_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_vs_const_t { + unsigned int : 11; + unsigned int size : SQ_VS_CONST_SIZE_SIZE; + unsigned int : 3; + unsigned int base : SQ_VS_CONST_BASE_SIZE; + } sq_vs_const_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_vs_const_t f; +} sq_vs_const_u; + + +/* + * SQ_PS_CONST struct + */ + +#define SQ_PS_CONST_BASE_SIZE 9 +#define SQ_PS_CONST_SIZE_SIZE 9 + +#define SQ_PS_CONST_BASE_SHIFT 0 +#define SQ_PS_CONST_SIZE_SHIFT 12 + +#define SQ_PS_CONST_BASE_MASK 0x000001ff +#define SQ_PS_CONST_SIZE_MASK 0x001ff000 + +#define SQ_PS_CONST_MASK \ + (SQ_PS_CONST_BASE_MASK | \ + SQ_PS_CONST_SIZE_MASK) + +#define SQ_PS_CONST(base, size) \ + ((base << SQ_PS_CONST_BASE_SHIFT) | \ + (size << SQ_PS_CONST_SIZE_SHIFT)) + +#define SQ_PS_CONST_GET_BASE(sq_ps_const) \ + ((sq_ps_const & SQ_PS_CONST_BASE_MASK) >> SQ_PS_CONST_BASE_SHIFT) +#define SQ_PS_CONST_GET_SIZE(sq_ps_const) \ + ((sq_ps_const & SQ_PS_CONST_SIZE_MASK) >> SQ_PS_CONST_SIZE_SHIFT) + +#define SQ_PS_CONST_SET_BASE(sq_ps_const_reg, base) \ + sq_ps_const_reg = (sq_ps_const_reg & ~SQ_PS_CONST_BASE_MASK) | (base << SQ_PS_CONST_BASE_SHIFT) +#define SQ_PS_CONST_SET_SIZE(sq_ps_const_reg, size) \ + sq_ps_const_reg = (sq_ps_const_reg & ~SQ_PS_CONST_SIZE_MASK) | (size << SQ_PS_CONST_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_ps_const_t { + unsigned int base : SQ_PS_CONST_BASE_SIZE; + unsigned int : 3; + unsigned int size : SQ_PS_CONST_SIZE_SIZE; + unsigned int : 11; + } sq_ps_const_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_ps_const_t { + unsigned int : 11; + unsigned int size : SQ_PS_CONST_SIZE_SIZE; + unsigned int : 3; + unsigned int base : SQ_PS_CONST_BASE_SIZE; + } sq_ps_const_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_ps_const_t f; +} sq_ps_const_u; + + +/* + * SQ_CONTEXT_MISC struct + */ + +#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE 1 +#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE 1 +#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE 2 +#define SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE 8 +#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE 1 +#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE 1 +#define SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE 1 + +#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT 0 +#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT 1 +#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT 2 +#define SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT 8 +#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT 16 +#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT 17 +#define SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT 18 + +#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK 0x00000001 +#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK 0x00000002 +#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK 0x0000000c +#define SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK 0x0000ff00 +#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK 0x00010000 +#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK 0x00020000 +#define SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK 0x00040000 + +#define SQ_CONTEXT_MISC_MASK \ + (SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK | \ + SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK | \ + SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK | \ + SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK | \ + SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK | \ + SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK | \ + SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) + +#define SQ_CONTEXT_MISC(inst_pred_optimize, sc_output_screen_xy, sc_sample_cntl, param_gen_pos, perfcounter_ref, yeild_optimize, tx_cache_sel) \ + ((inst_pred_optimize << SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT) | \ + (sc_output_screen_xy << SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT) | \ + (sc_sample_cntl << SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT) | \ + (param_gen_pos << SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT) | \ + (perfcounter_ref << SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT) | \ + (yeild_optimize << SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT) | \ + (tx_cache_sel << SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT)) + +#define SQ_CONTEXT_MISC_GET_INST_PRED_OPTIMIZE(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK) >> SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT) +#define SQ_CONTEXT_MISC_GET_SC_OUTPUT_SCREEN_XY(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK) >> SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT) +#define SQ_CONTEXT_MISC_GET_SC_SAMPLE_CNTL(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK) >> SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT) +#define SQ_CONTEXT_MISC_GET_PARAM_GEN_POS(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK) >> SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT) +#define SQ_CONTEXT_MISC_GET_PERFCOUNTER_REF(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK) >> SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT) +#define SQ_CONTEXT_MISC_GET_YEILD_OPTIMIZE(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK) >> SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT) +#define SQ_CONTEXT_MISC_GET_TX_CACHE_SEL(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) >> SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT) + +#define SQ_CONTEXT_MISC_SET_INST_PRED_OPTIMIZE(sq_context_misc_reg, inst_pred_optimize) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK) | (inst_pred_optimize << SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT) +#define SQ_CONTEXT_MISC_SET_SC_OUTPUT_SCREEN_XY(sq_context_misc_reg, sc_output_screen_xy) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK) | (sc_output_screen_xy << SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT) +#define SQ_CONTEXT_MISC_SET_SC_SAMPLE_CNTL(sq_context_misc_reg, sc_sample_cntl) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK) | (sc_sample_cntl << SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT) +#define SQ_CONTEXT_MISC_SET_PARAM_GEN_POS(sq_context_misc_reg, param_gen_pos) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK) | (param_gen_pos << SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT) +#define SQ_CONTEXT_MISC_SET_PERFCOUNTER_REF(sq_context_misc_reg, perfcounter_ref) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK) | (perfcounter_ref << SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT) +#define SQ_CONTEXT_MISC_SET_YEILD_OPTIMIZE(sq_context_misc_reg, yeild_optimize) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK) | (yeild_optimize << SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT) +#define SQ_CONTEXT_MISC_SET_TX_CACHE_SEL(sq_context_misc_reg, tx_cache_sel) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) | (tx_cache_sel << SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_context_misc_t { + unsigned int inst_pred_optimize : SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE; + unsigned int sc_output_screen_xy : SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE; + unsigned int sc_sample_cntl : SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE; + unsigned int : 4; + unsigned int param_gen_pos : SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE; + unsigned int perfcounter_ref : SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE; + unsigned int yeild_optimize : SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE; + unsigned int tx_cache_sel : SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE; + unsigned int : 13; + } sq_context_misc_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_context_misc_t { + unsigned int : 13; + unsigned int tx_cache_sel : SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE; + unsigned int yeild_optimize : SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE; + unsigned int perfcounter_ref : SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE; + unsigned int param_gen_pos : SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE; + unsigned int : 4; + unsigned int sc_sample_cntl : SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE; + unsigned int sc_output_screen_xy : SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE; + unsigned int inst_pred_optimize : SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE; + } sq_context_misc_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_context_misc_t f; +} sq_context_misc_u; + + +/* + * SQ_CF_RD_BASE struct + */ + +#define SQ_CF_RD_BASE_RD_BASE_SIZE 3 + +#define SQ_CF_RD_BASE_RD_BASE_SHIFT 0 + +#define SQ_CF_RD_BASE_RD_BASE_MASK 0x00000007 + +#define SQ_CF_RD_BASE_MASK \ + (SQ_CF_RD_BASE_RD_BASE_MASK) + +#define SQ_CF_RD_BASE(rd_base) \ + ((rd_base << SQ_CF_RD_BASE_RD_BASE_SHIFT)) + +#define SQ_CF_RD_BASE_GET_RD_BASE(sq_cf_rd_base) \ + ((sq_cf_rd_base & SQ_CF_RD_BASE_RD_BASE_MASK) >> SQ_CF_RD_BASE_RD_BASE_SHIFT) + +#define SQ_CF_RD_BASE_SET_RD_BASE(sq_cf_rd_base_reg, rd_base) \ + sq_cf_rd_base_reg = (sq_cf_rd_base_reg & ~SQ_CF_RD_BASE_RD_BASE_MASK) | (rd_base << SQ_CF_RD_BASE_RD_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_rd_base_t { + unsigned int rd_base : SQ_CF_RD_BASE_RD_BASE_SIZE; + unsigned int : 29; + } sq_cf_rd_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_rd_base_t { + unsigned int : 29; + unsigned int rd_base : SQ_CF_RD_BASE_RD_BASE_SIZE; + } sq_cf_rd_base_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_rd_base_t f; +} sq_cf_rd_base_u; + + +/* + * SQ_DEBUG_MISC_0 struct + */ + +#define SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE 1 +#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE 1 +#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE 11 +#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE 8 + +#define SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT 0 +#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT 4 +#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT 8 +#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT 24 + +#define SQ_DEBUG_MISC_0_DB_PROB_ON_MASK 0x00000001 +#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK 0x00000010 +#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK 0x0007ff00 +#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK 0xff000000 + +#define SQ_DEBUG_MISC_0_MASK \ + (SQ_DEBUG_MISC_0_DB_PROB_ON_MASK | \ + SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK | \ + SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK | \ + SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) + +#define SQ_DEBUG_MISC_0(db_prob_on, db_prob_break, db_prob_addr, db_prob_count) \ + ((db_prob_on << SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT) | \ + (db_prob_break << SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT) | \ + (db_prob_addr << SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT) | \ + (db_prob_count << SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT)) + +#define SQ_DEBUG_MISC_0_GET_DB_PROB_ON(sq_debug_misc_0) \ + ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_ON_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT) +#define SQ_DEBUG_MISC_0_GET_DB_PROB_BREAK(sq_debug_misc_0) \ + ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT) +#define SQ_DEBUG_MISC_0_GET_DB_PROB_ADDR(sq_debug_misc_0) \ + ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT) +#define SQ_DEBUG_MISC_0_GET_DB_PROB_COUNT(sq_debug_misc_0) \ + ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT) + +#define SQ_DEBUG_MISC_0_SET_DB_PROB_ON(sq_debug_misc_0_reg, db_prob_on) \ + sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_ON_MASK) | (db_prob_on << SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT) +#define SQ_DEBUG_MISC_0_SET_DB_PROB_BREAK(sq_debug_misc_0_reg, db_prob_break) \ + sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK) | (db_prob_break << SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT) +#define SQ_DEBUG_MISC_0_SET_DB_PROB_ADDR(sq_debug_misc_0_reg, db_prob_addr) \ + sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK) | (db_prob_addr << SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT) +#define SQ_DEBUG_MISC_0_SET_DB_PROB_COUNT(sq_debug_misc_0_reg, db_prob_count) \ + sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) | (db_prob_count << SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_misc_0_t { + unsigned int db_prob_on : SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE; + unsigned int : 3; + unsigned int db_prob_break : SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE; + unsigned int : 3; + unsigned int db_prob_addr : SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE; + unsigned int : 5; + unsigned int db_prob_count : SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE; + } sq_debug_misc_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_misc_0_t { + unsigned int db_prob_count : SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE; + unsigned int : 5; + unsigned int db_prob_addr : SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE; + unsigned int : 3; + unsigned int db_prob_break : SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE; + unsigned int : 3; + unsigned int db_prob_on : SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE; + } sq_debug_misc_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_misc_0_t f; +} sq_debug_misc_0_u; + + +/* + * SQ_DEBUG_MISC_1 struct + */ + +#define SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE 1 +#define SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE 1 +#define SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE 8 +#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE 11 + +#define SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT 0 +#define SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT 1 +#define SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT 8 +#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT 16 + +#define SQ_DEBUG_MISC_1_DB_ON_PIX_MASK 0x00000001 +#define SQ_DEBUG_MISC_1_DB_ON_VTX_MASK 0x00000002 +#define SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK 0x0000ff00 +#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK 0x07ff0000 + +#define SQ_DEBUG_MISC_1_MASK \ + (SQ_DEBUG_MISC_1_DB_ON_PIX_MASK | \ + SQ_DEBUG_MISC_1_DB_ON_VTX_MASK | \ + SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK | \ + SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) + +#define SQ_DEBUG_MISC_1(db_on_pix, db_on_vtx, db_inst_count, db_break_addr) \ + ((db_on_pix << SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT) | \ + (db_on_vtx << SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT) | \ + (db_inst_count << SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT) | \ + (db_break_addr << SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT)) + +#define SQ_DEBUG_MISC_1_GET_DB_ON_PIX(sq_debug_misc_1) \ + ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_ON_PIX_MASK) >> SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT) +#define SQ_DEBUG_MISC_1_GET_DB_ON_VTX(sq_debug_misc_1) \ + ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_ON_VTX_MASK) >> SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT) +#define SQ_DEBUG_MISC_1_GET_DB_INST_COUNT(sq_debug_misc_1) \ + ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK) >> SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT) +#define SQ_DEBUG_MISC_1_GET_DB_BREAK_ADDR(sq_debug_misc_1) \ + ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) >> SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT) + +#define SQ_DEBUG_MISC_1_SET_DB_ON_PIX(sq_debug_misc_1_reg, db_on_pix) \ + sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_ON_PIX_MASK) | (db_on_pix << SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT) +#define SQ_DEBUG_MISC_1_SET_DB_ON_VTX(sq_debug_misc_1_reg, db_on_vtx) \ + sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_ON_VTX_MASK) | (db_on_vtx << SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT) +#define SQ_DEBUG_MISC_1_SET_DB_INST_COUNT(sq_debug_misc_1_reg, db_inst_count) \ + sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK) | (db_inst_count << SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT) +#define SQ_DEBUG_MISC_1_SET_DB_BREAK_ADDR(sq_debug_misc_1_reg, db_break_addr) \ + sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) | (db_break_addr << SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_misc_1_t { + unsigned int db_on_pix : SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE; + unsigned int db_on_vtx : SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE; + unsigned int : 6; + unsigned int db_inst_count : SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE; + unsigned int db_break_addr : SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE; + unsigned int : 5; + } sq_debug_misc_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_misc_1_t { + unsigned int : 5; + unsigned int db_break_addr : SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE; + unsigned int db_inst_count : SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE; + unsigned int : 6; + unsigned int db_on_vtx : SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE; + unsigned int db_on_pix : SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE; + } sq_debug_misc_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_misc_1_t f; +} sq_debug_misc_1_u; + + +#endif + + +#if !defined (_SX_FIDDLE_H) +#define _SX_FIDDLE_H + +/***************************************************************************************************************** + * + * sx_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +#endif + + +#if !defined (_TP_FIDDLE_H) +#define _TP_FIDDLE_H + +/***************************************************************************************************************** + * + * tp_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * TC_CNTL_STATUS struct + */ + +#define TC_CNTL_STATUS_L2_INVALIDATE_SIZE 1 +#define TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE 2 +#define TC_CNTL_STATUS_TC_BUSY_SIZE 1 + +#define TC_CNTL_STATUS_L2_INVALIDATE_SHIFT 0 +#define TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT 18 +#define TC_CNTL_STATUS_TC_BUSY_SHIFT 31 + +#define TC_CNTL_STATUS_L2_INVALIDATE_MASK 0x00000001 +#define TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK 0x000c0000 +#define TC_CNTL_STATUS_TC_BUSY_MASK 0x80000000 + +#define TC_CNTL_STATUS_MASK \ + (TC_CNTL_STATUS_L2_INVALIDATE_MASK | \ + TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK | \ + TC_CNTL_STATUS_TC_BUSY_MASK) + +#define TC_CNTL_STATUS(l2_invalidate, tc_l2_hit_miss, tc_busy) \ + ((l2_invalidate << TC_CNTL_STATUS_L2_INVALIDATE_SHIFT) | \ + (tc_l2_hit_miss << TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT) | \ + (tc_busy << TC_CNTL_STATUS_TC_BUSY_SHIFT)) + +#define TC_CNTL_STATUS_GET_L2_INVALIDATE(tc_cntl_status) \ + ((tc_cntl_status & TC_CNTL_STATUS_L2_INVALIDATE_MASK) >> TC_CNTL_STATUS_L2_INVALIDATE_SHIFT) +#define TC_CNTL_STATUS_GET_TC_L2_HIT_MISS(tc_cntl_status) \ + ((tc_cntl_status & TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK) >> TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT) +#define TC_CNTL_STATUS_GET_TC_BUSY(tc_cntl_status) \ + ((tc_cntl_status & TC_CNTL_STATUS_TC_BUSY_MASK) >> TC_CNTL_STATUS_TC_BUSY_SHIFT) + +#define TC_CNTL_STATUS_SET_L2_INVALIDATE(tc_cntl_status_reg, l2_invalidate) \ + tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_L2_INVALIDATE_MASK) | (l2_invalidate << TC_CNTL_STATUS_L2_INVALIDATE_SHIFT) +#define TC_CNTL_STATUS_SET_TC_L2_HIT_MISS(tc_cntl_status_reg, tc_l2_hit_miss) \ + tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK) | (tc_l2_hit_miss << TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT) +#define TC_CNTL_STATUS_SET_TC_BUSY(tc_cntl_status_reg, tc_busy) \ + tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_TC_BUSY_MASK) | (tc_busy << TC_CNTL_STATUS_TC_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tc_cntl_status_t { + unsigned int l2_invalidate : TC_CNTL_STATUS_L2_INVALIDATE_SIZE; + unsigned int : 17; + unsigned int tc_l2_hit_miss : TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE; + unsigned int : 11; + unsigned int tc_busy : TC_CNTL_STATUS_TC_BUSY_SIZE; + } tc_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _tc_cntl_status_t { + unsigned int tc_busy : TC_CNTL_STATUS_TC_BUSY_SIZE; + unsigned int : 11; + unsigned int tc_l2_hit_miss : TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE; + unsigned int : 17; + unsigned int l2_invalidate : TC_CNTL_STATUS_L2_INVALIDATE_SIZE; + } tc_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + tc_cntl_status_t f; +} tc_cntl_status_u; + + +/* + * TCR_CHICKEN struct + */ + +#define TCR_CHICKEN_SPARE_SIZE 32 + +#define TCR_CHICKEN_SPARE_SHIFT 0 + +#define TCR_CHICKEN_SPARE_MASK 0xffffffff + +#define TCR_CHICKEN_MASK \ + (TCR_CHICKEN_SPARE_MASK) + +#define TCR_CHICKEN(spare) \ + ((spare << TCR_CHICKEN_SPARE_SHIFT)) + +#define TCR_CHICKEN_GET_SPARE(tcr_chicken) \ + ((tcr_chicken & TCR_CHICKEN_SPARE_MASK) >> TCR_CHICKEN_SPARE_SHIFT) + +#define TCR_CHICKEN_SET_SPARE(tcr_chicken_reg, spare) \ + tcr_chicken_reg = (tcr_chicken_reg & ~TCR_CHICKEN_SPARE_MASK) | (spare << TCR_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_chicken_t { + unsigned int spare : TCR_CHICKEN_SPARE_SIZE; + } tcr_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_chicken_t { + unsigned int spare : TCR_CHICKEN_SPARE_SIZE; + } tcr_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_chicken_t f; +} tcr_chicken_u; + + +/* + * TCF_CHICKEN struct + */ + +#define TCF_CHICKEN_SPARE_SIZE 32 + +#define TCF_CHICKEN_SPARE_SHIFT 0 + +#define TCF_CHICKEN_SPARE_MASK 0xffffffff + +#define TCF_CHICKEN_MASK \ + (TCF_CHICKEN_SPARE_MASK) + +#define TCF_CHICKEN(spare) \ + ((spare << TCF_CHICKEN_SPARE_SHIFT)) + +#define TCF_CHICKEN_GET_SPARE(tcf_chicken) \ + ((tcf_chicken & TCF_CHICKEN_SPARE_MASK) >> TCF_CHICKEN_SPARE_SHIFT) + +#define TCF_CHICKEN_SET_SPARE(tcf_chicken_reg, spare) \ + tcf_chicken_reg = (tcf_chicken_reg & ~TCF_CHICKEN_SPARE_MASK) | (spare << TCF_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_chicken_t { + unsigned int spare : TCF_CHICKEN_SPARE_SIZE; + } tcf_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_chicken_t { + unsigned int spare : TCF_CHICKEN_SPARE_SIZE; + } tcf_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_chicken_t f; +} tcf_chicken_u; + + +/* + * TCM_CHICKEN struct + */ + +#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE 8 +#define TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE 1 +#define TCM_CHICKEN_SPARE_SIZE 23 + +#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT 0 +#define TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT 8 +#define TCM_CHICKEN_SPARE_SHIFT 9 + +#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK 0x000000ff +#define TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK 0x00000100 +#define TCM_CHICKEN_SPARE_MASK 0xfffffe00 + +#define TCM_CHICKEN_MASK \ + (TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK | \ + TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK | \ + TCM_CHICKEN_SPARE_MASK) + +#define TCM_CHICKEN(tco_read_latency_fifo_prog_depth, etc_color_endian, spare) \ + ((tco_read_latency_fifo_prog_depth << TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT) | \ + (etc_color_endian << TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT) | \ + (spare << TCM_CHICKEN_SPARE_SHIFT)) + +#define TCM_CHICKEN_GET_TCO_READ_LATENCY_FIFO_PROG_DEPTH(tcm_chicken) \ + ((tcm_chicken & TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK) >> TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT) +#define TCM_CHICKEN_GET_ETC_COLOR_ENDIAN(tcm_chicken) \ + ((tcm_chicken & TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK) >> TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT) +#define TCM_CHICKEN_GET_SPARE(tcm_chicken) \ + ((tcm_chicken & TCM_CHICKEN_SPARE_MASK) >> TCM_CHICKEN_SPARE_SHIFT) + +#define TCM_CHICKEN_SET_TCO_READ_LATENCY_FIFO_PROG_DEPTH(tcm_chicken_reg, tco_read_latency_fifo_prog_depth) \ + tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK) | (tco_read_latency_fifo_prog_depth << TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT) +#define TCM_CHICKEN_SET_ETC_COLOR_ENDIAN(tcm_chicken_reg, etc_color_endian) \ + tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK) | (etc_color_endian << TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT) +#define TCM_CHICKEN_SET_SPARE(tcm_chicken_reg, spare) \ + tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_SPARE_MASK) | (spare << TCM_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_chicken_t { + unsigned int tco_read_latency_fifo_prog_depth : TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE; + unsigned int etc_color_endian : TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE; + unsigned int spare : TCM_CHICKEN_SPARE_SIZE; + } tcm_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_chicken_t { + unsigned int spare : TCM_CHICKEN_SPARE_SIZE; + unsigned int etc_color_endian : TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE; + unsigned int tco_read_latency_fifo_prog_depth : TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE; + } tcm_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_chicken_t f; +} tcm_chicken_u; + + +/* + * TCR_PERFCOUNTER0_SELECT struct + */ + +#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCR_PERFCOUNTER0_SELECT_MASK \ + (TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCR_PERFCOUNTER0_SELECT(perfcounter_select) \ + ((perfcounter_select << TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCR_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcr_perfcounter0_select) \ + ((tcr_perfcounter0_select & TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCR_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcr_perfcounter0_select_reg, perfcounter_select) \ + tcr_perfcounter0_select_reg = (tcr_perfcounter0_select_reg & ~TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_select_t { + unsigned int perfcounter_select : TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcr_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcr_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter0_select_t f; +} tcr_perfcounter0_select_u; + + +/* + * TCR_PERFCOUNTER1_SELECT struct + */ + +#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCR_PERFCOUNTER1_SELECT_MASK \ + (TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCR_PERFCOUNTER1_SELECT(perfcounter_select) \ + ((perfcounter_select << TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCR_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcr_perfcounter1_select) \ + ((tcr_perfcounter1_select & TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCR_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcr_perfcounter1_select_reg, perfcounter_select) \ + tcr_perfcounter1_select_reg = (tcr_perfcounter1_select_reg & ~TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_select_t { + unsigned int perfcounter_select : TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcr_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcr_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter1_select_t f; +} tcr_perfcounter1_select_u; + + +/* + * TCR_PERFCOUNTER0_HI struct + */ + +#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCR_PERFCOUNTER0_HI_MASK \ + (TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) + +#define TCR_PERFCOUNTER0_HI(perfcounter_hi) \ + ((perfcounter_hi << TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCR_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcr_perfcounter0_hi) \ + ((tcr_perfcounter0_hi & TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#define TCR_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcr_perfcounter0_hi_reg, perfcounter_hi) \ + tcr_perfcounter0_hi_reg = (tcr_perfcounter0_hi_reg & ~TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_hi_t { + unsigned int perfcounter_hi : TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcr_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + } tcr_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter0_hi_t f; +} tcr_perfcounter0_hi_u; + + +/* + * TCR_PERFCOUNTER1_HI struct + */ + +#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCR_PERFCOUNTER1_HI_MASK \ + (TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) + +#define TCR_PERFCOUNTER1_HI(perfcounter_hi) \ + ((perfcounter_hi << TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCR_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcr_perfcounter1_hi) \ + ((tcr_perfcounter1_hi & TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#define TCR_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcr_perfcounter1_hi_reg, perfcounter_hi) \ + tcr_perfcounter1_hi_reg = (tcr_perfcounter1_hi_reg & ~TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_hi_t { + unsigned int perfcounter_hi : TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcr_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + } tcr_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter1_hi_t f; +} tcr_perfcounter1_hi_u; + + +/* + * TCR_PERFCOUNTER0_LOW struct + */ + +#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCR_PERFCOUNTER0_LOW_MASK \ + (TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) + +#define TCR_PERFCOUNTER0_LOW(perfcounter_low) \ + ((perfcounter_low << TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCR_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcr_perfcounter0_low) \ + ((tcr_perfcounter0_low & TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCR_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcr_perfcounter0_low_reg, perfcounter_low) \ + tcr_perfcounter0_low_reg = (tcr_perfcounter0_low_reg & ~TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_low_t { + unsigned int perfcounter_low : TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcr_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_low_t { + unsigned int perfcounter_low : TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcr_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter0_low_t f; +} tcr_perfcounter0_low_u; + + +/* + * TCR_PERFCOUNTER1_LOW struct + */ + +#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCR_PERFCOUNTER1_LOW_MASK \ + (TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) + +#define TCR_PERFCOUNTER1_LOW(perfcounter_low) \ + ((perfcounter_low << TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCR_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcr_perfcounter1_low) \ + ((tcr_perfcounter1_low & TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCR_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcr_perfcounter1_low_reg, perfcounter_low) \ + tcr_perfcounter1_low_reg = (tcr_perfcounter1_low_reg & ~TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_low_t { + unsigned int perfcounter_low : TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcr_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_low_t { + unsigned int perfcounter_low : TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcr_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter1_low_t f; +} tcr_perfcounter1_low_u; + + +/* + * TP_TC_CLKGATE_CNTL struct + */ + +#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE 3 +#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE 3 + +#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT 0 +#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT 3 + +#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK 0x00000007 +#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK 0x00000038 + +#define TP_TC_CLKGATE_CNTL_MASK \ + (TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK | \ + TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) + +#define TP_TC_CLKGATE_CNTL(tp_busy_extend, tc_busy_extend) \ + ((tp_busy_extend << TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT) | \ + (tc_busy_extend << TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT)) + +#define TP_TC_CLKGATE_CNTL_GET_TP_BUSY_EXTEND(tp_tc_clkgate_cntl) \ + ((tp_tc_clkgate_cntl & TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK) >> TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT) +#define TP_TC_CLKGATE_CNTL_GET_TC_BUSY_EXTEND(tp_tc_clkgate_cntl) \ + ((tp_tc_clkgate_cntl & TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) >> TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT) + +#define TP_TC_CLKGATE_CNTL_SET_TP_BUSY_EXTEND(tp_tc_clkgate_cntl_reg, tp_busy_extend) \ + tp_tc_clkgate_cntl_reg = (tp_tc_clkgate_cntl_reg & ~TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK) | (tp_busy_extend << TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT) +#define TP_TC_CLKGATE_CNTL_SET_TC_BUSY_EXTEND(tp_tc_clkgate_cntl_reg, tc_busy_extend) \ + tp_tc_clkgate_cntl_reg = (tp_tc_clkgate_cntl_reg & ~TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) | (tc_busy_extend << TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp_tc_clkgate_cntl_t { + unsigned int tp_busy_extend : TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE; + unsigned int tc_busy_extend : TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE; + unsigned int : 26; + } tp_tc_clkgate_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp_tc_clkgate_cntl_t { + unsigned int : 26; + unsigned int tc_busy_extend : TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE; + unsigned int tp_busy_extend : TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE; + } tp_tc_clkgate_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + tp_tc_clkgate_cntl_t f; +} tp_tc_clkgate_cntl_u; + + +/* + * TPC_CNTL_STATUS struct + */ + +#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TF_TW_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TF_TW_RTR_SIZE 1 +#define TPC_CNTL_STATUS_TW_TA_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TW_TA_RTR_SIZE 1 +#define TPC_CNTL_STATUS_TA_TB_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TA_TB_RTR_SIZE 1 +#define TPC_CNTL_STATUS_TA_TF_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE 1 +#define TPC_CNTL_STATUS_TP_SQ_DEC_SIZE 1 +#define TPC_CNTL_STATUS_TPC_BUSY_SIZE 1 + +#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT 0 +#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT 1 +#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT 2 +#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT 3 +#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT 4 +#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT 5 +#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT 6 +#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT 8 +#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT 9 +#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT 10 +#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT 12 +#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT 13 +#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT 14 +#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT 15 +#define TPC_CNTL_STATUS_TF_TW_RTS_SHIFT 16 +#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT 17 +#define TPC_CNTL_STATUS_TF_TW_RTR_SHIFT 19 +#define TPC_CNTL_STATUS_TW_TA_RTS_SHIFT 20 +#define TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT 21 +#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT 22 +#define TPC_CNTL_STATUS_TW_TA_RTR_SHIFT 23 +#define TPC_CNTL_STATUS_TA_TB_RTS_SHIFT 24 +#define TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT 25 +#define TPC_CNTL_STATUS_TA_TB_RTR_SHIFT 27 +#define TPC_CNTL_STATUS_TA_TF_RTS_SHIFT 28 +#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT 29 +#define TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT 30 +#define TPC_CNTL_STATUS_TPC_BUSY_SHIFT 31 + +#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK 0x00000001 +#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK 0x00000002 +#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK 0x00000004 +#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK 0x00000008 +#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK 0x00000010 +#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK 0x00000020 +#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK 0x00000040 +#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK 0x00000100 +#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK 0x00000200 +#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK 0x00000400 +#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK 0x00001000 +#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK 0x00002000 +#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK 0x00004000 +#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK 0x00008000 +#define TPC_CNTL_STATUS_TF_TW_RTS_MASK 0x00010000 +#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK 0x00020000 +#define TPC_CNTL_STATUS_TF_TW_RTR_MASK 0x00080000 +#define TPC_CNTL_STATUS_TW_TA_RTS_MASK 0x00100000 +#define TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK 0x00200000 +#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK 0x00400000 +#define TPC_CNTL_STATUS_TW_TA_RTR_MASK 0x00800000 +#define TPC_CNTL_STATUS_TA_TB_RTS_MASK 0x01000000 +#define TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK 0x02000000 +#define TPC_CNTL_STATUS_TA_TB_RTR_MASK 0x08000000 +#define TPC_CNTL_STATUS_TA_TF_RTS_MASK 0x10000000 +#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK 0x20000000 +#define TPC_CNTL_STATUS_TP_SQ_DEC_MASK 0x40000000 +#define TPC_CNTL_STATUS_TPC_BUSY_MASK 0x80000000 + +#define TPC_CNTL_STATUS_MASK \ + (TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK | \ + TPC_CNTL_STATUS_TF_TW_RTS_MASK | \ + TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK | \ + TPC_CNTL_STATUS_TF_TW_RTR_MASK | \ + TPC_CNTL_STATUS_TW_TA_RTS_MASK | \ + TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK | \ + TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK | \ + TPC_CNTL_STATUS_TW_TA_RTR_MASK | \ + TPC_CNTL_STATUS_TA_TB_RTS_MASK | \ + TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK | \ + TPC_CNTL_STATUS_TA_TB_RTR_MASK | \ + TPC_CNTL_STATUS_TA_TF_RTS_MASK | \ + TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK | \ + TPC_CNTL_STATUS_TP_SQ_DEC_MASK | \ + TPC_CNTL_STATUS_TPC_BUSY_MASK) + +#define TPC_CNTL_STATUS(tpc_input_busy, tpc_tc_fifo_busy, tpc_state_fifo_busy, tpc_fetch_fifo_busy, tpc_walker_pipe_busy, tpc_walk_fifo_busy, tpc_walker_busy, tpc_aligner_pipe_busy, tpc_align_fifo_busy, tpc_aligner_busy, tpc_rr_fifo_busy, tpc_blend_pipe_busy, tpc_out_fifo_busy, tpc_blend_busy, tf_tw_rts, tf_tw_state_rts, tf_tw_rtr, tw_ta_rts, tw_ta_tt_rts, tw_ta_last_rts, tw_ta_rtr, ta_tb_rts, ta_tb_tt_rts, ta_tb_rtr, ta_tf_rts, ta_tf_tc_fifo_ren, tp_sq_dec, tpc_busy) \ + ((tpc_input_busy << TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT) | \ + (tpc_tc_fifo_busy << TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT) | \ + (tpc_state_fifo_busy << TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT) | \ + (tpc_fetch_fifo_busy << TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT) | \ + (tpc_walker_pipe_busy << TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT) | \ + (tpc_walk_fifo_busy << TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT) | \ + (tpc_walker_busy << TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT) | \ + (tpc_aligner_pipe_busy << TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT) | \ + (tpc_align_fifo_busy << TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT) | \ + (tpc_aligner_busy << TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT) | \ + (tpc_rr_fifo_busy << TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT) | \ + (tpc_blend_pipe_busy << TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT) | \ + (tpc_out_fifo_busy << TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT) | \ + (tpc_blend_busy << TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT) | \ + (tf_tw_rts << TPC_CNTL_STATUS_TF_TW_RTS_SHIFT) | \ + (tf_tw_state_rts << TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT) | \ + (tf_tw_rtr << TPC_CNTL_STATUS_TF_TW_RTR_SHIFT) | \ + (tw_ta_rts << TPC_CNTL_STATUS_TW_TA_RTS_SHIFT) | \ + (tw_ta_tt_rts << TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT) | \ + (tw_ta_last_rts << TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT) | \ + (tw_ta_rtr << TPC_CNTL_STATUS_TW_TA_RTR_SHIFT) | \ + (ta_tb_rts << TPC_CNTL_STATUS_TA_TB_RTS_SHIFT) | \ + (ta_tb_tt_rts << TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT) | \ + (ta_tb_rtr << TPC_CNTL_STATUS_TA_TB_RTR_SHIFT) | \ + (ta_tf_rts << TPC_CNTL_STATUS_TA_TF_RTS_SHIFT) | \ + (ta_tf_tc_fifo_ren << TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT) | \ + (tp_sq_dec << TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT) | \ + (tpc_busy << TPC_CNTL_STATUS_TPC_BUSY_SHIFT)) + +#define TPC_CNTL_STATUS_GET_TPC_INPUT_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_TC_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_STATE_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_FETCH_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_WALKER_PIPE_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_WALK_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_WALKER_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_ALIGNER_PIPE_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_ALIGN_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_ALIGNER_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_RR_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_BLEND_PIPE_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_OUT_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_BLEND_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TF_TW_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_RTS_MASK) >> TPC_CNTL_STATUS_TF_TW_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TF_TW_STATE_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK) >> TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TF_TW_RTR(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_RTR_MASK) >> TPC_CNTL_STATUS_TF_TW_RTR_SHIFT) +#define TPC_CNTL_STATUS_GET_TW_TA_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TW_TA_TT_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TW_TA_LAST_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TW_TA_RTR(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_RTR_MASK) >> TPC_CNTL_STATUS_TW_TA_RTR_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TB_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_RTS_MASK) >> TPC_CNTL_STATUS_TA_TB_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TB_TT_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK) >> TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TB_RTR(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_RTR_MASK) >> TPC_CNTL_STATUS_TA_TB_RTR_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TF_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TF_RTS_MASK) >> TPC_CNTL_STATUS_TA_TF_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TF_TC_FIFO_REN(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK) >> TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT) +#define TPC_CNTL_STATUS_GET_TP_SQ_DEC(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TP_SQ_DEC_MASK) >> TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BUSY_SHIFT) + +#define TPC_CNTL_STATUS_SET_TPC_INPUT_BUSY(tpc_cntl_status_reg, tpc_input_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK) | (tpc_input_busy << TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_TC_FIFO_BUSY(tpc_cntl_status_reg, tpc_tc_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK) | (tpc_tc_fifo_busy << TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_STATE_FIFO_BUSY(tpc_cntl_status_reg, tpc_state_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK) | (tpc_state_fifo_busy << TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_FETCH_FIFO_BUSY(tpc_cntl_status_reg, tpc_fetch_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK) | (tpc_fetch_fifo_busy << TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_WALKER_PIPE_BUSY(tpc_cntl_status_reg, tpc_walker_pipe_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK) | (tpc_walker_pipe_busy << TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_WALK_FIFO_BUSY(tpc_cntl_status_reg, tpc_walk_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK) | (tpc_walk_fifo_busy << TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_WALKER_BUSY(tpc_cntl_status_reg, tpc_walker_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK) | (tpc_walker_busy << TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_ALIGNER_PIPE_BUSY(tpc_cntl_status_reg, tpc_aligner_pipe_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK) | (tpc_aligner_pipe_busy << TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_ALIGN_FIFO_BUSY(tpc_cntl_status_reg, tpc_align_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK) | (tpc_align_fifo_busy << TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_ALIGNER_BUSY(tpc_cntl_status_reg, tpc_aligner_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK) | (tpc_aligner_busy << TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_RR_FIFO_BUSY(tpc_cntl_status_reg, tpc_rr_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK) | (tpc_rr_fifo_busy << TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_BLEND_PIPE_BUSY(tpc_cntl_status_reg, tpc_blend_pipe_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK) | (tpc_blend_pipe_busy << TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_OUT_FIFO_BUSY(tpc_cntl_status_reg, tpc_out_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK) | (tpc_out_fifo_busy << TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_BLEND_BUSY(tpc_cntl_status_reg, tpc_blend_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK) | (tpc_blend_busy << TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TF_TW_RTS(tpc_cntl_status_reg, tf_tw_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_RTS_MASK) | (tf_tw_rts << TPC_CNTL_STATUS_TF_TW_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TF_TW_STATE_RTS(tpc_cntl_status_reg, tf_tw_state_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK) | (tf_tw_state_rts << TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TF_TW_RTR(tpc_cntl_status_reg, tf_tw_rtr) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_RTR_MASK) | (tf_tw_rtr << TPC_CNTL_STATUS_TF_TW_RTR_SHIFT) +#define TPC_CNTL_STATUS_SET_TW_TA_RTS(tpc_cntl_status_reg, tw_ta_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_RTS_MASK) | (tw_ta_rts << TPC_CNTL_STATUS_TW_TA_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TW_TA_TT_RTS(tpc_cntl_status_reg, tw_ta_tt_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK) | (tw_ta_tt_rts << TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TW_TA_LAST_RTS(tpc_cntl_status_reg, tw_ta_last_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK) | (tw_ta_last_rts << TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TW_TA_RTR(tpc_cntl_status_reg, tw_ta_rtr) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_RTR_MASK) | (tw_ta_rtr << TPC_CNTL_STATUS_TW_TA_RTR_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TB_RTS(tpc_cntl_status_reg, ta_tb_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_RTS_MASK) | (ta_tb_rts << TPC_CNTL_STATUS_TA_TB_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TB_TT_RTS(tpc_cntl_status_reg, ta_tb_tt_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK) | (ta_tb_tt_rts << TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TB_RTR(tpc_cntl_status_reg, ta_tb_rtr) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_RTR_MASK) | (ta_tb_rtr << TPC_CNTL_STATUS_TA_TB_RTR_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TF_RTS(tpc_cntl_status_reg, ta_tf_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TF_RTS_MASK) | (ta_tf_rts << TPC_CNTL_STATUS_TA_TF_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TF_TC_FIFO_REN(tpc_cntl_status_reg, ta_tf_tc_fifo_ren) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK) | (ta_tf_tc_fifo_ren << TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT) +#define TPC_CNTL_STATUS_SET_TP_SQ_DEC(tpc_cntl_status_reg, tp_sq_dec) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TP_SQ_DEC_MASK) | (tp_sq_dec << TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_BUSY(tpc_cntl_status_reg, tpc_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BUSY_MASK) | (tpc_busy << TPC_CNTL_STATUS_TPC_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tpc_cntl_status_t { + unsigned int tpc_input_busy : TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE; + unsigned int tpc_tc_fifo_busy : TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE; + unsigned int tpc_state_fifo_busy : TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE; + unsigned int tpc_fetch_fifo_busy : TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE; + unsigned int tpc_walker_pipe_busy : TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE; + unsigned int tpc_walk_fifo_busy : TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE; + unsigned int tpc_walker_busy : TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_aligner_pipe_busy : TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE; + unsigned int tpc_align_fifo_busy : TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE; + unsigned int tpc_aligner_busy : TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_rr_fifo_busy : TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE; + unsigned int tpc_blend_pipe_busy : TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE; + unsigned int tpc_out_fifo_busy : TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE; + unsigned int tpc_blend_busy : TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE; + unsigned int tf_tw_rts : TPC_CNTL_STATUS_TF_TW_RTS_SIZE; + unsigned int tf_tw_state_rts : TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE; + unsigned int : 1; + unsigned int tf_tw_rtr : TPC_CNTL_STATUS_TF_TW_RTR_SIZE; + unsigned int tw_ta_rts : TPC_CNTL_STATUS_TW_TA_RTS_SIZE; + unsigned int tw_ta_tt_rts : TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE; + unsigned int tw_ta_last_rts : TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE; + unsigned int tw_ta_rtr : TPC_CNTL_STATUS_TW_TA_RTR_SIZE; + unsigned int ta_tb_rts : TPC_CNTL_STATUS_TA_TB_RTS_SIZE; + unsigned int ta_tb_tt_rts : TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE; + unsigned int : 1; + unsigned int ta_tb_rtr : TPC_CNTL_STATUS_TA_TB_RTR_SIZE; + unsigned int ta_tf_rts : TPC_CNTL_STATUS_TA_TF_RTS_SIZE; + unsigned int ta_tf_tc_fifo_ren : TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE; + unsigned int tp_sq_dec : TPC_CNTL_STATUS_TP_SQ_DEC_SIZE; + unsigned int tpc_busy : TPC_CNTL_STATUS_TPC_BUSY_SIZE; + } tpc_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _tpc_cntl_status_t { + unsigned int tpc_busy : TPC_CNTL_STATUS_TPC_BUSY_SIZE; + unsigned int tp_sq_dec : TPC_CNTL_STATUS_TP_SQ_DEC_SIZE; + unsigned int ta_tf_tc_fifo_ren : TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE; + unsigned int ta_tf_rts : TPC_CNTL_STATUS_TA_TF_RTS_SIZE; + unsigned int ta_tb_rtr : TPC_CNTL_STATUS_TA_TB_RTR_SIZE; + unsigned int : 1; + unsigned int ta_tb_tt_rts : TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE; + unsigned int ta_tb_rts : TPC_CNTL_STATUS_TA_TB_RTS_SIZE; + unsigned int tw_ta_rtr : TPC_CNTL_STATUS_TW_TA_RTR_SIZE; + unsigned int tw_ta_last_rts : TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE; + unsigned int tw_ta_tt_rts : TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE; + unsigned int tw_ta_rts : TPC_CNTL_STATUS_TW_TA_RTS_SIZE; + unsigned int tf_tw_rtr : TPC_CNTL_STATUS_TF_TW_RTR_SIZE; + unsigned int : 1; + unsigned int tf_tw_state_rts : TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE; + unsigned int tf_tw_rts : TPC_CNTL_STATUS_TF_TW_RTS_SIZE; + unsigned int tpc_blend_busy : TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE; + unsigned int tpc_out_fifo_busy : TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE; + unsigned int tpc_blend_pipe_busy : TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE; + unsigned int tpc_rr_fifo_busy : TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_aligner_busy : TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE; + unsigned int tpc_align_fifo_busy : TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE; + unsigned int tpc_aligner_pipe_busy : TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_walker_busy : TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE; + unsigned int tpc_walk_fifo_busy : TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE; + unsigned int tpc_walker_pipe_busy : TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE; + unsigned int tpc_fetch_fifo_busy : TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE; + unsigned int tpc_state_fifo_busy : TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE; + unsigned int tpc_tc_fifo_busy : TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE; + unsigned int tpc_input_busy : TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE; + } tpc_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + tpc_cntl_status_t f; +} tpc_cntl_status_u; + + +/* + * TPC_DEBUG0 struct + */ + +#define TPC_DEBUG0_LOD_CNTL_SIZE 2 +#define TPC_DEBUG0_IC_CTR_SIZE 2 +#define TPC_DEBUG0_WALKER_CNTL_SIZE 4 +#define TPC_DEBUG0_ALIGNER_CNTL_SIZE 3 +#define TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE 1 +#define TPC_DEBUG0_WALKER_STATE_SIZE 10 +#define TPC_DEBUG0_ALIGNER_STATE_SIZE 2 +#define TPC_DEBUG0_REG_CLK_EN_SIZE 1 +#define TPC_DEBUG0_TPC_CLK_EN_SIZE 1 +#define TPC_DEBUG0_SQ_TP_WAKEUP_SIZE 1 + +#define TPC_DEBUG0_LOD_CNTL_SHIFT 0 +#define TPC_DEBUG0_IC_CTR_SHIFT 2 +#define TPC_DEBUG0_WALKER_CNTL_SHIFT 4 +#define TPC_DEBUG0_ALIGNER_CNTL_SHIFT 8 +#define TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT 12 +#define TPC_DEBUG0_WALKER_STATE_SHIFT 16 +#define TPC_DEBUG0_ALIGNER_STATE_SHIFT 26 +#define TPC_DEBUG0_REG_CLK_EN_SHIFT 29 +#define TPC_DEBUG0_TPC_CLK_EN_SHIFT 30 +#define TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT 31 + +#define TPC_DEBUG0_LOD_CNTL_MASK 0x00000003 +#define TPC_DEBUG0_IC_CTR_MASK 0x0000000c +#define TPC_DEBUG0_WALKER_CNTL_MASK 0x000000f0 +#define TPC_DEBUG0_ALIGNER_CNTL_MASK 0x00000700 +#define TPC_DEBUG0_PREV_TC_STATE_VALID_MASK 0x00001000 +#define TPC_DEBUG0_WALKER_STATE_MASK 0x03ff0000 +#define TPC_DEBUG0_ALIGNER_STATE_MASK 0x0c000000 +#define TPC_DEBUG0_REG_CLK_EN_MASK 0x20000000 +#define TPC_DEBUG0_TPC_CLK_EN_MASK 0x40000000 +#define TPC_DEBUG0_SQ_TP_WAKEUP_MASK 0x80000000 + +#define TPC_DEBUG0_MASK \ + (TPC_DEBUG0_LOD_CNTL_MASK | \ + TPC_DEBUG0_IC_CTR_MASK | \ + TPC_DEBUG0_WALKER_CNTL_MASK | \ + TPC_DEBUG0_ALIGNER_CNTL_MASK | \ + TPC_DEBUG0_PREV_TC_STATE_VALID_MASK | \ + TPC_DEBUG0_WALKER_STATE_MASK | \ + TPC_DEBUG0_ALIGNER_STATE_MASK | \ + TPC_DEBUG0_REG_CLK_EN_MASK | \ + TPC_DEBUG0_TPC_CLK_EN_MASK | \ + TPC_DEBUG0_SQ_TP_WAKEUP_MASK) + +#define TPC_DEBUG0(lod_cntl, ic_ctr, walker_cntl, aligner_cntl, prev_tc_state_valid, walker_state, aligner_state, reg_clk_en, tpc_clk_en, sq_tp_wakeup) \ + ((lod_cntl << TPC_DEBUG0_LOD_CNTL_SHIFT) | \ + (ic_ctr << TPC_DEBUG0_IC_CTR_SHIFT) | \ + (walker_cntl << TPC_DEBUG0_WALKER_CNTL_SHIFT) | \ + (aligner_cntl << TPC_DEBUG0_ALIGNER_CNTL_SHIFT) | \ + (prev_tc_state_valid << TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT) | \ + (walker_state << TPC_DEBUG0_WALKER_STATE_SHIFT) | \ + (aligner_state << TPC_DEBUG0_ALIGNER_STATE_SHIFT) | \ + (reg_clk_en << TPC_DEBUG0_REG_CLK_EN_SHIFT) | \ + (tpc_clk_en << TPC_DEBUG0_TPC_CLK_EN_SHIFT) | \ + (sq_tp_wakeup << TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT)) + +#define TPC_DEBUG0_GET_LOD_CNTL(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_LOD_CNTL_MASK) >> TPC_DEBUG0_LOD_CNTL_SHIFT) +#define TPC_DEBUG0_GET_IC_CTR(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_IC_CTR_MASK) >> TPC_DEBUG0_IC_CTR_SHIFT) +#define TPC_DEBUG0_GET_WALKER_CNTL(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_WALKER_CNTL_MASK) >> TPC_DEBUG0_WALKER_CNTL_SHIFT) +#define TPC_DEBUG0_GET_ALIGNER_CNTL(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_ALIGNER_CNTL_MASK) >> TPC_DEBUG0_ALIGNER_CNTL_SHIFT) +#define TPC_DEBUG0_GET_PREV_TC_STATE_VALID(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_PREV_TC_STATE_VALID_MASK) >> TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT) +#define TPC_DEBUG0_GET_WALKER_STATE(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_WALKER_STATE_MASK) >> TPC_DEBUG0_WALKER_STATE_SHIFT) +#define TPC_DEBUG0_GET_ALIGNER_STATE(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_ALIGNER_STATE_MASK) >> TPC_DEBUG0_ALIGNER_STATE_SHIFT) +#define TPC_DEBUG0_GET_REG_CLK_EN(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_REG_CLK_EN_MASK) >> TPC_DEBUG0_REG_CLK_EN_SHIFT) +#define TPC_DEBUG0_GET_TPC_CLK_EN(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_TPC_CLK_EN_MASK) >> TPC_DEBUG0_TPC_CLK_EN_SHIFT) +#define TPC_DEBUG0_GET_SQ_TP_WAKEUP(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_SQ_TP_WAKEUP_MASK) >> TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT) + +#define TPC_DEBUG0_SET_LOD_CNTL(tpc_debug0_reg, lod_cntl) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_LOD_CNTL_MASK) | (lod_cntl << TPC_DEBUG0_LOD_CNTL_SHIFT) +#define TPC_DEBUG0_SET_IC_CTR(tpc_debug0_reg, ic_ctr) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_IC_CTR_MASK) | (ic_ctr << TPC_DEBUG0_IC_CTR_SHIFT) +#define TPC_DEBUG0_SET_WALKER_CNTL(tpc_debug0_reg, walker_cntl) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_WALKER_CNTL_MASK) | (walker_cntl << TPC_DEBUG0_WALKER_CNTL_SHIFT) +#define TPC_DEBUG0_SET_ALIGNER_CNTL(tpc_debug0_reg, aligner_cntl) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_ALIGNER_CNTL_MASK) | (aligner_cntl << TPC_DEBUG0_ALIGNER_CNTL_SHIFT) +#define TPC_DEBUG0_SET_PREV_TC_STATE_VALID(tpc_debug0_reg, prev_tc_state_valid) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_PREV_TC_STATE_VALID_MASK) | (prev_tc_state_valid << TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT) +#define TPC_DEBUG0_SET_WALKER_STATE(tpc_debug0_reg, walker_state) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_WALKER_STATE_MASK) | (walker_state << TPC_DEBUG0_WALKER_STATE_SHIFT) +#define TPC_DEBUG0_SET_ALIGNER_STATE(tpc_debug0_reg, aligner_state) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_ALIGNER_STATE_MASK) | (aligner_state << TPC_DEBUG0_ALIGNER_STATE_SHIFT) +#define TPC_DEBUG0_SET_REG_CLK_EN(tpc_debug0_reg, reg_clk_en) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_REG_CLK_EN_MASK) | (reg_clk_en << TPC_DEBUG0_REG_CLK_EN_SHIFT) +#define TPC_DEBUG0_SET_TPC_CLK_EN(tpc_debug0_reg, tpc_clk_en) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_TPC_CLK_EN_MASK) | (tpc_clk_en << TPC_DEBUG0_TPC_CLK_EN_SHIFT) +#define TPC_DEBUG0_SET_SQ_TP_WAKEUP(tpc_debug0_reg, sq_tp_wakeup) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_SQ_TP_WAKEUP_MASK) | (sq_tp_wakeup << TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tpc_debug0_t { + unsigned int lod_cntl : TPC_DEBUG0_LOD_CNTL_SIZE; + unsigned int ic_ctr : TPC_DEBUG0_IC_CTR_SIZE; + unsigned int walker_cntl : TPC_DEBUG0_WALKER_CNTL_SIZE; + unsigned int aligner_cntl : TPC_DEBUG0_ALIGNER_CNTL_SIZE; + unsigned int : 1; + unsigned int prev_tc_state_valid : TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE; + unsigned int : 3; + unsigned int walker_state : TPC_DEBUG0_WALKER_STATE_SIZE; + unsigned int aligner_state : TPC_DEBUG0_ALIGNER_STATE_SIZE; + unsigned int : 1; + unsigned int reg_clk_en : TPC_DEBUG0_REG_CLK_EN_SIZE; + unsigned int tpc_clk_en : TPC_DEBUG0_TPC_CLK_EN_SIZE; + unsigned int sq_tp_wakeup : TPC_DEBUG0_SQ_TP_WAKEUP_SIZE; + } tpc_debug0_t; + +#else // !BIGENDIAN_OS + + typedef struct _tpc_debug0_t { + unsigned int sq_tp_wakeup : TPC_DEBUG0_SQ_TP_WAKEUP_SIZE; + unsigned int tpc_clk_en : TPC_DEBUG0_TPC_CLK_EN_SIZE; + unsigned int reg_clk_en : TPC_DEBUG0_REG_CLK_EN_SIZE; + unsigned int : 1; + unsigned int aligner_state : TPC_DEBUG0_ALIGNER_STATE_SIZE; + unsigned int walker_state : TPC_DEBUG0_WALKER_STATE_SIZE; + unsigned int : 3; + unsigned int prev_tc_state_valid : TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE; + unsigned int : 1; + unsigned int aligner_cntl : TPC_DEBUG0_ALIGNER_CNTL_SIZE; + unsigned int walker_cntl : TPC_DEBUG0_WALKER_CNTL_SIZE; + unsigned int ic_ctr : TPC_DEBUG0_IC_CTR_SIZE; + unsigned int lod_cntl : TPC_DEBUG0_LOD_CNTL_SIZE; + } tpc_debug0_t; + +#endif + +typedef union { + unsigned int val : 32; + tpc_debug0_t f; +} tpc_debug0_u; + + +/* + * TPC_DEBUG1 struct + */ + +#define TPC_DEBUG1_UNUSED_SIZE 1 + +#define TPC_DEBUG1_UNUSED_SHIFT 0 + +#define TPC_DEBUG1_UNUSED_MASK 0x00000001 + +#define TPC_DEBUG1_MASK \ + (TPC_DEBUG1_UNUSED_MASK) + +#define TPC_DEBUG1(unused) \ + ((unused << TPC_DEBUG1_UNUSED_SHIFT)) + +#define TPC_DEBUG1_GET_UNUSED(tpc_debug1) \ + ((tpc_debug1 & TPC_DEBUG1_UNUSED_MASK) >> TPC_DEBUG1_UNUSED_SHIFT) + +#define TPC_DEBUG1_SET_UNUSED(tpc_debug1_reg, unused) \ + tpc_debug1_reg = (tpc_debug1_reg & ~TPC_DEBUG1_UNUSED_MASK) | (unused << TPC_DEBUG1_UNUSED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tpc_debug1_t { + unsigned int unused : TPC_DEBUG1_UNUSED_SIZE; + unsigned int : 31; + } tpc_debug1_t; + +#else // !BIGENDIAN_OS + + typedef struct _tpc_debug1_t { + unsigned int : 31; + unsigned int unused : TPC_DEBUG1_UNUSED_SIZE; + } tpc_debug1_t; + +#endif + +typedef union { + unsigned int val : 32; + tpc_debug1_t f; +} tpc_debug1_u; + + +/* + * TPC_CHICKEN struct + */ + +#define TPC_CHICKEN_BLEND_PRECISION_SIZE 1 +#define TPC_CHICKEN_SPARE_SIZE 31 + +#define TPC_CHICKEN_BLEND_PRECISION_SHIFT 0 +#define TPC_CHICKEN_SPARE_SHIFT 1 + +#define TPC_CHICKEN_BLEND_PRECISION_MASK 0x00000001 +#define TPC_CHICKEN_SPARE_MASK 0xfffffffe + +#define TPC_CHICKEN_MASK \ + (TPC_CHICKEN_BLEND_PRECISION_MASK | \ + TPC_CHICKEN_SPARE_MASK) + +#define TPC_CHICKEN(blend_precision, spare) \ + ((blend_precision << TPC_CHICKEN_BLEND_PRECISION_SHIFT) | \ + (spare << TPC_CHICKEN_SPARE_SHIFT)) + +#define TPC_CHICKEN_GET_BLEND_PRECISION(tpc_chicken) \ + ((tpc_chicken & TPC_CHICKEN_BLEND_PRECISION_MASK) >> TPC_CHICKEN_BLEND_PRECISION_SHIFT) +#define TPC_CHICKEN_GET_SPARE(tpc_chicken) \ + ((tpc_chicken & TPC_CHICKEN_SPARE_MASK) >> TPC_CHICKEN_SPARE_SHIFT) + +#define TPC_CHICKEN_SET_BLEND_PRECISION(tpc_chicken_reg, blend_precision) \ + tpc_chicken_reg = (tpc_chicken_reg & ~TPC_CHICKEN_BLEND_PRECISION_MASK) | (blend_precision << TPC_CHICKEN_BLEND_PRECISION_SHIFT) +#define TPC_CHICKEN_SET_SPARE(tpc_chicken_reg, spare) \ + tpc_chicken_reg = (tpc_chicken_reg & ~TPC_CHICKEN_SPARE_MASK) | (spare << TPC_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tpc_chicken_t { + unsigned int blend_precision : TPC_CHICKEN_BLEND_PRECISION_SIZE; + unsigned int spare : TPC_CHICKEN_SPARE_SIZE; + } tpc_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tpc_chicken_t { + unsigned int spare : TPC_CHICKEN_SPARE_SIZE; + unsigned int blend_precision : TPC_CHICKEN_BLEND_PRECISION_SIZE; + } tpc_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tpc_chicken_t f; +} tpc_chicken_u; + + +/* + * TP0_CNTL_STATUS struct + */ + +#define TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_TT_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_IN_LC_RTS_SIZE 1 +#define TP0_CNTL_STATUS_LC_LA_RTS_SIZE 1 +#define TP0_CNTL_STATUS_LA_FL_RTS_SIZE 1 +#define TP0_CNTL_STATUS_FL_TA_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TA_FA_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_FA_AL_RTS_SIZE 1 +#define TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_AL_TF_RTS_SIZE 1 +#define TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TF_TB_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TB_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE 1 +#define TP0_CNTL_STATUS_TB_TO_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TP_BUSY_SIZE 1 + +#define TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT 0 +#define TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT 1 +#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT 2 +#define TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT 3 +#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT 4 +#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT 5 +#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT 6 +#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT 7 +#define TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT 8 +#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT 9 +#define TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT 10 +#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT 11 +#define TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT 12 +#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT 13 +#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT 14 +#define TP0_CNTL_STATUS_IN_LC_RTS_SHIFT 16 +#define TP0_CNTL_STATUS_LC_LA_RTS_SHIFT 17 +#define TP0_CNTL_STATUS_LA_FL_RTS_SHIFT 18 +#define TP0_CNTL_STATUS_FL_TA_RTS_SHIFT 19 +#define TP0_CNTL_STATUS_TA_FA_RTS_SHIFT 20 +#define TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT 21 +#define TP0_CNTL_STATUS_FA_AL_RTS_SHIFT 22 +#define TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT 23 +#define TP0_CNTL_STATUS_AL_TF_RTS_SHIFT 24 +#define TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT 25 +#define TP0_CNTL_STATUS_TF_TB_RTS_SHIFT 26 +#define TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT 27 +#define TP0_CNTL_STATUS_TB_TT_RTS_SHIFT 28 +#define TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT 29 +#define TP0_CNTL_STATUS_TB_TO_RTS_SHIFT 30 +#define TP0_CNTL_STATUS_TP_BUSY_SHIFT 31 + +#define TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK 0x00000001 +#define TP0_CNTL_STATUS_TP_LOD_BUSY_MASK 0x00000002 +#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK 0x00000004 +#define TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK 0x00000008 +#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK 0x00000010 +#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK 0x00000020 +#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK 0x00000040 +#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK 0x00000080 +#define TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK 0x00000100 +#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK 0x00000200 +#define TP0_CNTL_STATUS_TP_TT_BUSY_MASK 0x00000400 +#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK 0x00000800 +#define TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK 0x00001000 +#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK 0x00002000 +#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK 0x00004000 +#define TP0_CNTL_STATUS_IN_LC_RTS_MASK 0x00010000 +#define TP0_CNTL_STATUS_LC_LA_RTS_MASK 0x00020000 +#define TP0_CNTL_STATUS_LA_FL_RTS_MASK 0x00040000 +#define TP0_CNTL_STATUS_FL_TA_RTS_MASK 0x00080000 +#define TP0_CNTL_STATUS_TA_FA_RTS_MASK 0x00100000 +#define TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK 0x00200000 +#define TP0_CNTL_STATUS_FA_AL_RTS_MASK 0x00400000 +#define TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK 0x00800000 +#define TP0_CNTL_STATUS_AL_TF_RTS_MASK 0x01000000 +#define TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK 0x02000000 +#define TP0_CNTL_STATUS_TF_TB_RTS_MASK 0x04000000 +#define TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK 0x08000000 +#define TP0_CNTL_STATUS_TB_TT_RTS_MASK 0x10000000 +#define TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK 0x20000000 +#define TP0_CNTL_STATUS_TB_TO_RTS_MASK 0x40000000 +#define TP0_CNTL_STATUS_TP_BUSY_MASK 0x80000000 + +#define TP0_CNTL_STATUS_MASK \ + (TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_LOD_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_TT_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK | \ + TP0_CNTL_STATUS_IN_LC_RTS_MASK | \ + TP0_CNTL_STATUS_LC_LA_RTS_MASK | \ + TP0_CNTL_STATUS_LA_FL_RTS_MASK | \ + TP0_CNTL_STATUS_FL_TA_RTS_MASK | \ + TP0_CNTL_STATUS_TA_FA_RTS_MASK | \ + TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK | \ + TP0_CNTL_STATUS_FA_AL_RTS_MASK | \ + TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK | \ + TP0_CNTL_STATUS_AL_TF_RTS_MASK | \ + TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK | \ + TP0_CNTL_STATUS_TF_TB_RTS_MASK | \ + TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK | \ + TP0_CNTL_STATUS_TB_TT_RTS_MASK | \ + TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK | \ + TP0_CNTL_STATUS_TB_TO_RTS_MASK | \ + TP0_CNTL_STATUS_TP_BUSY_MASK) + +#define TP0_CNTL_STATUS(tp_input_busy, tp_lod_busy, tp_lod_fifo_busy, tp_addr_busy, tp_align_fifo_busy, tp_aligner_busy, tp_tc_fifo_busy, tp_rr_fifo_busy, tp_fetch_busy, tp_ch_blend_busy, tp_tt_busy, tp_hicolor_busy, tp_blend_busy, tp_out_fifo_busy, tp_output_busy, in_lc_rts, lc_la_rts, la_fl_rts, fl_ta_rts, ta_fa_rts, ta_fa_tt_rts, fa_al_rts, fa_al_tt_rts, al_tf_rts, al_tf_tt_rts, tf_tb_rts, tf_tb_tt_rts, tb_tt_rts, tb_tt_tt_reset, tb_to_rts, tp_busy) \ + ((tp_input_busy << TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT) | \ + (tp_lod_busy << TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT) | \ + (tp_lod_fifo_busy << TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT) | \ + (tp_addr_busy << TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT) | \ + (tp_align_fifo_busy << TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT) | \ + (tp_aligner_busy << TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT) | \ + (tp_tc_fifo_busy << TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT) | \ + (tp_rr_fifo_busy << TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT) | \ + (tp_fetch_busy << TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT) | \ + (tp_ch_blend_busy << TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT) | \ + (tp_tt_busy << TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT) | \ + (tp_hicolor_busy << TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT) | \ + (tp_blend_busy << TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT) | \ + (tp_out_fifo_busy << TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT) | \ + (tp_output_busy << TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT) | \ + (in_lc_rts << TP0_CNTL_STATUS_IN_LC_RTS_SHIFT) | \ + (lc_la_rts << TP0_CNTL_STATUS_LC_LA_RTS_SHIFT) | \ + (la_fl_rts << TP0_CNTL_STATUS_LA_FL_RTS_SHIFT) | \ + (fl_ta_rts << TP0_CNTL_STATUS_FL_TA_RTS_SHIFT) | \ + (ta_fa_rts << TP0_CNTL_STATUS_TA_FA_RTS_SHIFT) | \ + (ta_fa_tt_rts << TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT) | \ + (fa_al_rts << TP0_CNTL_STATUS_FA_AL_RTS_SHIFT) | \ + (fa_al_tt_rts << TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT) | \ + (al_tf_rts << TP0_CNTL_STATUS_AL_TF_RTS_SHIFT) | \ + (al_tf_tt_rts << TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT) | \ + (tf_tb_rts << TP0_CNTL_STATUS_TF_TB_RTS_SHIFT) | \ + (tf_tb_tt_rts << TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT) | \ + (tb_tt_rts << TP0_CNTL_STATUS_TB_TT_RTS_SHIFT) | \ + (tb_tt_tt_reset << TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT) | \ + (tb_to_rts << TP0_CNTL_STATUS_TB_TO_RTS_SHIFT) | \ + (tp_busy << TP0_CNTL_STATUS_TP_BUSY_SHIFT)) + +#define TP0_CNTL_STATUS_GET_TP_INPUT_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_LOD_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_LOD_BUSY_MASK) >> TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_LOD_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_ADDR_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_ALIGN_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_ALIGNER_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_TC_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_RR_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_FETCH_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK) >> TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_CH_BLEND_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK) >> TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_TT_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_TT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_HICOLOR_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK) >> TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_BLEND_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK) >> TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_OUT_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_OUTPUT_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_IN_LC_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_IN_LC_RTS_MASK) >> TP0_CNTL_STATUS_IN_LC_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_LC_LA_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_LC_LA_RTS_MASK) >> TP0_CNTL_STATUS_LC_LA_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_LA_FL_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_LA_FL_RTS_MASK) >> TP0_CNTL_STATUS_LA_FL_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_FL_TA_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_FL_TA_RTS_MASK) >> TP0_CNTL_STATUS_FL_TA_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TA_FA_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TA_FA_RTS_MASK) >> TP0_CNTL_STATUS_TA_FA_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TA_FA_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK) >> TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_FA_AL_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_FA_AL_RTS_MASK) >> TP0_CNTL_STATUS_FA_AL_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_FA_AL_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK) >> TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_AL_TF_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_AL_TF_RTS_MASK) >> TP0_CNTL_STATUS_AL_TF_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_AL_TF_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK) >> TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TF_TB_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TF_TB_RTS_MASK) >> TP0_CNTL_STATUS_TF_TB_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TF_TB_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK) >> TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TB_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TT_RTS_MASK) >> TP0_CNTL_STATUS_TB_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TB_TT_TT_RESET(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK) >> TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT) +#define TP0_CNTL_STATUS_GET_TB_TO_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TO_RTS_MASK) >> TP0_CNTL_STATUS_TB_TO_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_BUSY_MASK) >> TP0_CNTL_STATUS_TP_BUSY_SHIFT) + +#define TP0_CNTL_STATUS_SET_TP_INPUT_BUSY(tp0_cntl_status_reg, tp_input_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK) | (tp_input_busy << TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_LOD_BUSY(tp0_cntl_status_reg, tp_lod_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_LOD_BUSY_MASK) | (tp_lod_busy << TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_LOD_FIFO_BUSY(tp0_cntl_status_reg, tp_lod_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK) | (tp_lod_fifo_busy << TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_ADDR_BUSY(tp0_cntl_status_reg, tp_addr_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK) | (tp_addr_busy << TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_ALIGN_FIFO_BUSY(tp0_cntl_status_reg, tp_align_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK) | (tp_align_fifo_busy << TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_ALIGNER_BUSY(tp0_cntl_status_reg, tp_aligner_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK) | (tp_aligner_busy << TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_TC_FIFO_BUSY(tp0_cntl_status_reg, tp_tc_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK) | (tp_tc_fifo_busy << TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_RR_FIFO_BUSY(tp0_cntl_status_reg, tp_rr_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK) | (tp_rr_fifo_busy << TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_FETCH_BUSY(tp0_cntl_status_reg, tp_fetch_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK) | (tp_fetch_busy << TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_CH_BLEND_BUSY(tp0_cntl_status_reg, tp_ch_blend_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK) | (tp_ch_blend_busy << TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_TT_BUSY(tp0_cntl_status_reg, tp_tt_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_TT_BUSY_MASK) | (tp_tt_busy << TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_HICOLOR_BUSY(tp0_cntl_status_reg, tp_hicolor_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK) | (tp_hicolor_busy << TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_BLEND_BUSY(tp0_cntl_status_reg, tp_blend_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK) | (tp_blend_busy << TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_OUT_FIFO_BUSY(tp0_cntl_status_reg, tp_out_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK) | (tp_out_fifo_busy << TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_OUTPUT_BUSY(tp0_cntl_status_reg, tp_output_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK) | (tp_output_busy << TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_IN_LC_RTS(tp0_cntl_status_reg, in_lc_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_IN_LC_RTS_MASK) | (in_lc_rts << TP0_CNTL_STATUS_IN_LC_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_LC_LA_RTS(tp0_cntl_status_reg, lc_la_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_LC_LA_RTS_MASK) | (lc_la_rts << TP0_CNTL_STATUS_LC_LA_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_LA_FL_RTS(tp0_cntl_status_reg, la_fl_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_LA_FL_RTS_MASK) | (la_fl_rts << TP0_CNTL_STATUS_LA_FL_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_FL_TA_RTS(tp0_cntl_status_reg, fl_ta_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FL_TA_RTS_MASK) | (fl_ta_rts << TP0_CNTL_STATUS_FL_TA_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TA_FA_RTS(tp0_cntl_status_reg, ta_fa_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TA_FA_RTS_MASK) | (ta_fa_rts << TP0_CNTL_STATUS_TA_FA_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TA_FA_TT_RTS(tp0_cntl_status_reg, ta_fa_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK) | (ta_fa_tt_rts << TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_FA_AL_RTS(tp0_cntl_status_reg, fa_al_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FA_AL_RTS_MASK) | (fa_al_rts << TP0_CNTL_STATUS_FA_AL_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_FA_AL_TT_RTS(tp0_cntl_status_reg, fa_al_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK) | (fa_al_tt_rts << TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_AL_TF_RTS(tp0_cntl_status_reg, al_tf_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_AL_TF_RTS_MASK) | (al_tf_rts << TP0_CNTL_STATUS_AL_TF_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_AL_TF_TT_RTS(tp0_cntl_status_reg, al_tf_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK) | (al_tf_tt_rts << TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TF_TB_RTS(tp0_cntl_status_reg, tf_tb_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TF_TB_RTS_MASK) | (tf_tb_rts << TP0_CNTL_STATUS_TF_TB_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TF_TB_TT_RTS(tp0_cntl_status_reg, tf_tb_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK) | (tf_tb_tt_rts << TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TB_TT_RTS(tp0_cntl_status_reg, tb_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TT_RTS_MASK) | (tb_tt_rts << TP0_CNTL_STATUS_TB_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TB_TT_TT_RESET(tp0_cntl_status_reg, tb_tt_tt_reset) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK) | (tb_tt_tt_reset << TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT) +#define TP0_CNTL_STATUS_SET_TB_TO_RTS(tp0_cntl_status_reg, tb_to_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TO_RTS_MASK) | (tb_to_rts << TP0_CNTL_STATUS_TB_TO_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_BUSY(tp0_cntl_status_reg, tp_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_BUSY_MASK) | (tp_busy << TP0_CNTL_STATUS_TP_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_cntl_status_t { + unsigned int tp_input_busy : TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE; + unsigned int tp_lod_busy : TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE; + unsigned int tp_lod_fifo_busy : TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE; + unsigned int tp_addr_busy : TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE; + unsigned int tp_align_fifo_busy : TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE; + unsigned int tp_aligner_busy : TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE; + unsigned int tp_tc_fifo_busy : TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE; + unsigned int tp_rr_fifo_busy : TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE; + unsigned int tp_fetch_busy : TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE; + unsigned int tp_ch_blend_busy : TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE; + unsigned int tp_tt_busy : TP0_CNTL_STATUS_TP_TT_BUSY_SIZE; + unsigned int tp_hicolor_busy : TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE; + unsigned int tp_blend_busy : TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE; + unsigned int tp_out_fifo_busy : TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE; + unsigned int tp_output_busy : TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE; + unsigned int : 1; + unsigned int in_lc_rts : TP0_CNTL_STATUS_IN_LC_RTS_SIZE; + unsigned int lc_la_rts : TP0_CNTL_STATUS_LC_LA_RTS_SIZE; + unsigned int la_fl_rts : TP0_CNTL_STATUS_LA_FL_RTS_SIZE; + unsigned int fl_ta_rts : TP0_CNTL_STATUS_FL_TA_RTS_SIZE; + unsigned int ta_fa_rts : TP0_CNTL_STATUS_TA_FA_RTS_SIZE; + unsigned int ta_fa_tt_rts : TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE; + unsigned int fa_al_rts : TP0_CNTL_STATUS_FA_AL_RTS_SIZE; + unsigned int fa_al_tt_rts : TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE; + unsigned int al_tf_rts : TP0_CNTL_STATUS_AL_TF_RTS_SIZE; + unsigned int al_tf_tt_rts : TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE; + unsigned int tf_tb_rts : TP0_CNTL_STATUS_TF_TB_RTS_SIZE; + unsigned int tf_tb_tt_rts : TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE; + unsigned int tb_tt_rts : TP0_CNTL_STATUS_TB_TT_RTS_SIZE; + unsigned int tb_tt_tt_reset : TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE; + unsigned int tb_to_rts : TP0_CNTL_STATUS_TB_TO_RTS_SIZE; + unsigned int tp_busy : TP0_CNTL_STATUS_TP_BUSY_SIZE; + } tp0_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_cntl_status_t { + unsigned int tp_busy : TP0_CNTL_STATUS_TP_BUSY_SIZE; + unsigned int tb_to_rts : TP0_CNTL_STATUS_TB_TO_RTS_SIZE; + unsigned int tb_tt_tt_reset : TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE; + unsigned int tb_tt_rts : TP0_CNTL_STATUS_TB_TT_RTS_SIZE; + unsigned int tf_tb_tt_rts : TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE; + unsigned int tf_tb_rts : TP0_CNTL_STATUS_TF_TB_RTS_SIZE; + unsigned int al_tf_tt_rts : TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE; + unsigned int al_tf_rts : TP0_CNTL_STATUS_AL_TF_RTS_SIZE; + unsigned int fa_al_tt_rts : TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE; + unsigned int fa_al_rts : TP0_CNTL_STATUS_FA_AL_RTS_SIZE; + unsigned int ta_fa_tt_rts : TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE; + unsigned int ta_fa_rts : TP0_CNTL_STATUS_TA_FA_RTS_SIZE; + unsigned int fl_ta_rts : TP0_CNTL_STATUS_FL_TA_RTS_SIZE; + unsigned int la_fl_rts : TP0_CNTL_STATUS_LA_FL_RTS_SIZE; + unsigned int lc_la_rts : TP0_CNTL_STATUS_LC_LA_RTS_SIZE; + unsigned int in_lc_rts : TP0_CNTL_STATUS_IN_LC_RTS_SIZE; + unsigned int : 1; + unsigned int tp_output_busy : TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE; + unsigned int tp_out_fifo_busy : TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE; + unsigned int tp_blend_busy : TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE; + unsigned int tp_hicolor_busy : TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE; + unsigned int tp_tt_busy : TP0_CNTL_STATUS_TP_TT_BUSY_SIZE; + unsigned int tp_ch_blend_busy : TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE; + unsigned int tp_fetch_busy : TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE; + unsigned int tp_rr_fifo_busy : TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE; + unsigned int tp_tc_fifo_busy : TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE; + unsigned int tp_aligner_busy : TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE; + unsigned int tp_align_fifo_busy : TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE; + unsigned int tp_addr_busy : TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE; + unsigned int tp_lod_fifo_busy : TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE; + unsigned int tp_lod_busy : TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE; + unsigned int tp_input_busy : TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE; + } tp0_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_cntl_status_t f; +} tp0_cntl_status_u; + + +/* + * TP0_DEBUG struct + */ + +#define TP0_DEBUG_Q_LOD_CNTL_SIZE 2 +#define TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE 1 +#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE 17 +#define TP0_DEBUG_REG_CLK_EN_SIZE 1 +#define TP0_DEBUG_PERF_CLK_EN_SIZE 1 +#define TP0_DEBUG_TP_CLK_EN_SIZE 1 +#define TP0_DEBUG_Q_WALKER_CNTL_SIZE 4 +#define TP0_DEBUG_Q_ALIGNER_CNTL_SIZE 3 + +#define TP0_DEBUG_Q_LOD_CNTL_SHIFT 0 +#define TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT 3 +#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT 4 +#define TP0_DEBUG_REG_CLK_EN_SHIFT 21 +#define TP0_DEBUG_PERF_CLK_EN_SHIFT 22 +#define TP0_DEBUG_TP_CLK_EN_SHIFT 23 +#define TP0_DEBUG_Q_WALKER_CNTL_SHIFT 24 +#define TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT 28 + +#define TP0_DEBUG_Q_LOD_CNTL_MASK 0x00000003 +#define TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK 0x00000008 +#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK 0x001ffff0 +#define TP0_DEBUG_REG_CLK_EN_MASK 0x00200000 +#define TP0_DEBUG_PERF_CLK_EN_MASK 0x00400000 +#define TP0_DEBUG_TP_CLK_EN_MASK 0x00800000 +#define TP0_DEBUG_Q_WALKER_CNTL_MASK 0x0f000000 +#define TP0_DEBUG_Q_ALIGNER_CNTL_MASK 0x70000000 + +#define TP0_DEBUG_MASK \ + (TP0_DEBUG_Q_LOD_CNTL_MASK | \ + TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK | \ + TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK | \ + TP0_DEBUG_REG_CLK_EN_MASK | \ + TP0_DEBUG_PERF_CLK_EN_MASK | \ + TP0_DEBUG_TP_CLK_EN_MASK | \ + TP0_DEBUG_Q_WALKER_CNTL_MASK | \ + TP0_DEBUG_Q_ALIGNER_CNTL_MASK) + +#define TP0_DEBUG(q_lod_cntl, q_sq_tp_wakeup, fl_ta_addresser_cntl, reg_clk_en, perf_clk_en, tp_clk_en, q_walker_cntl, q_aligner_cntl) \ + ((q_lod_cntl << TP0_DEBUG_Q_LOD_CNTL_SHIFT) | \ + (q_sq_tp_wakeup << TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT) | \ + (fl_ta_addresser_cntl << TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT) | \ + (reg_clk_en << TP0_DEBUG_REG_CLK_EN_SHIFT) | \ + (perf_clk_en << TP0_DEBUG_PERF_CLK_EN_SHIFT) | \ + (tp_clk_en << TP0_DEBUG_TP_CLK_EN_SHIFT) | \ + (q_walker_cntl << TP0_DEBUG_Q_WALKER_CNTL_SHIFT) | \ + (q_aligner_cntl << TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT)) + +#define TP0_DEBUG_GET_Q_LOD_CNTL(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_Q_LOD_CNTL_MASK) >> TP0_DEBUG_Q_LOD_CNTL_SHIFT) +#define TP0_DEBUG_GET_Q_SQ_TP_WAKEUP(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK) >> TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT) +#define TP0_DEBUG_GET_FL_TA_ADDRESSER_CNTL(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK) >> TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT) +#define TP0_DEBUG_GET_REG_CLK_EN(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_REG_CLK_EN_MASK) >> TP0_DEBUG_REG_CLK_EN_SHIFT) +#define TP0_DEBUG_GET_PERF_CLK_EN(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_PERF_CLK_EN_MASK) >> TP0_DEBUG_PERF_CLK_EN_SHIFT) +#define TP0_DEBUG_GET_TP_CLK_EN(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_TP_CLK_EN_MASK) >> TP0_DEBUG_TP_CLK_EN_SHIFT) +#define TP0_DEBUG_GET_Q_WALKER_CNTL(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_Q_WALKER_CNTL_MASK) >> TP0_DEBUG_Q_WALKER_CNTL_SHIFT) +#define TP0_DEBUG_GET_Q_ALIGNER_CNTL(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_Q_ALIGNER_CNTL_MASK) >> TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT) + +#define TP0_DEBUG_SET_Q_LOD_CNTL(tp0_debug_reg, q_lod_cntl) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_LOD_CNTL_MASK) | (q_lod_cntl << TP0_DEBUG_Q_LOD_CNTL_SHIFT) +#define TP0_DEBUG_SET_Q_SQ_TP_WAKEUP(tp0_debug_reg, q_sq_tp_wakeup) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK) | (q_sq_tp_wakeup << TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT) +#define TP0_DEBUG_SET_FL_TA_ADDRESSER_CNTL(tp0_debug_reg, fl_ta_addresser_cntl) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK) | (fl_ta_addresser_cntl << TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT) +#define TP0_DEBUG_SET_REG_CLK_EN(tp0_debug_reg, reg_clk_en) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_REG_CLK_EN_MASK) | (reg_clk_en << TP0_DEBUG_REG_CLK_EN_SHIFT) +#define TP0_DEBUG_SET_PERF_CLK_EN(tp0_debug_reg, perf_clk_en) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_PERF_CLK_EN_MASK) | (perf_clk_en << TP0_DEBUG_PERF_CLK_EN_SHIFT) +#define TP0_DEBUG_SET_TP_CLK_EN(tp0_debug_reg, tp_clk_en) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_TP_CLK_EN_MASK) | (tp_clk_en << TP0_DEBUG_TP_CLK_EN_SHIFT) +#define TP0_DEBUG_SET_Q_WALKER_CNTL(tp0_debug_reg, q_walker_cntl) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_WALKER_CNTL_MASK) | (q_walker_cntl << TP0_DEBUG_Q_WALKER_CNTL_SHIFT) +#define TP0_DEBUG_SET_Q_ALIGNER_CNTL(tp0_debug_reg, q_aligner_cntl) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_ALIGNER_CNTL_MASK) | (q_aligner_cntl << TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_debug_t { + unsigned int q_lod_cntl : TP0_DEBUG_Q_LOD_CNTL_SIZE; + unsigned int : 1; + unsigned int q_sq_tp_wakeup : TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE; + unsigned int fl_ta_addresser_cntl : TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE; + unsigned int reg_clk_en : TP0_DEBUG_REG_CLK_EN_SIZE; + unsigned int perf_clk_en : TP0_DEBUG_PERF_CLK_EN_SIZE; + unsigned int tp_clk_en : TP0_DEBUG_TP_CLK_EN_SIZE; + unsigned int q_walker_cntl : TP0_DEBUG_Q_WALKER_CNTL_SIZE; + unsigned int q_aligner_cntl : TP0_DEBUG_Q_ALIGNER_CNTL_SIZE; + unsigned int : 1; + } tp0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_debug_t { + unsigned int : 1; + unsigned int q_aligner_cntl : TP0_DEBUG_Q_ALIGNER_CNTL_SIZE; + unsigned int q_walker_cntl : TP0_DEBUG_Q_WALKER_CNTL_SIZE; + unsigned int tp_clk_en : TP0_DEBUG_TP_CLK_EN_SIZE; + unsigned int perf_clk_en : TP0_DEBUG_PERF_CLK_EN_SIZE; + unsigned int reg_clk_en : TP0_DEBUG_REG_CLK_EN_SIZE; + unsigned int fl_ta_addresser_cntl : TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE; + unsigned int q_sq_tp_wakeup : TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE; + unsigned int : 1; + unsigned int q_lod_cntl : TP0_DEBUG_Q_LOD_CNTL_SIZE; + } tp0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_debug_t f; +} tp0_debug_u; + + +/* + * TP0_CHICKEN struct + */ + +#define TP0_CHICKEN_TT_MODE_SIZE 1 +#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE 1 +#define TP0_CHICKEN_SPARE_SIZE 30 + +#define TP0_CHICKEN_TT_MODE_SHIFT 0 +#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT 1 +#define TP0_CHICKEN_SPARE_SHIFT 2 + +#define TP0_CHICKEN_TT_MODE_MASK 0x00000001 +#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK 0x00000002 +#define TP0_CHICKEN_SPARE_MASK 0xfffffffc + +#define TP0_CHICKEN_MASK \ + (TP0_CHICKEN_TT_MODE_MASK | \ + TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK | \ + TP0_CHICKEN_SPARE_MASK) + +#define TP0_CHICKEN(tt_mode, vfetch_address_mode, spare) \ + ((tt_mode << TP0_CHICKEN_TT_MODE_SHIFT) | \ + (vfetch_address_mode << TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT) | \ + (spare << TP0_CHICKEN_SPARE_SHIFT)) + +#define TP0_CHICKEN_GET_TT_MODE(tp0_chicken) \ + ((tp0_chicken & TP0_CHICKEN_TT_MODE_MASK) >> TP0_CHICKEN_TT_MODE_SHIFT) +#define TP0_CHICKEN_GET_VFETCH_ADDRESS_MODE(tp0_chicken) \ + ((tp0_chicken & TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK) >> TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT) +#define TP0_CHICKEN_GET_SPARE(tp0_chicken) \ + ((tp0_chicken & TP0_CHICKEN_SPARE_MASK) >> TP0_CHICKEN_SPARE_SHIFT) + +#define TP0_CHICKEN_SET_TT_MODE(tp0_chicken_reg, tt_mode) \ + tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_TT_MODE_MASK) | (tt_mode << TP0_CHICKEN_TT_MODE_SHIFT) +#define TP0_CHICKEN_SET_VFETCH_ADDRESS_MODE(tp0_chicken_reg, vfetch_address_mode) \ + tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK) | (vfetch_address_mode << TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT) +#define TP0_CHICKEN_SET_SPARE(tp0_chicken_reg, spare) \ + tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_SPARE_MASK) | (spare << TP0_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_chicken_t { + unsigned int tt_mode : TP0_CHICKEN_TT_MODE_SIZE; + unsigned int vfetch_address_mode : TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE; + unsigned int spare : TP0_CHICKEN_SPARE_SIZE; + } tp0_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_chicken_t { + unsigned int spare : TP0_CHICKEN_SPARE_SIZE; + unsigned int vfetch_address_mode : TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE; + unsigned int tt_mode : TP0_CHICKEN_TT_MODE_SIZE; + } tp0_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_chicken_t f; +} tp0_chicken_u; + + +/* + * TP0_PERFCOUNTER0_SELECT struct + */ + +#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TP0_PERFCOUNTER0_SELECT_MASK \ + (TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TP0_PERFCOUNTER0_SELECT(perfcounter_select) \ + ((perfcounter_select << TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TP0_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tp0_perfcounter0_select) \ + ((tp0_perfcounter0_select & TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TP0_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tp0_perfcounter0_select_reg, perfcounter_select) \ + tp0_perfcounter0_select_reg = (tp0_perfcounter0_select_reg & ~TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_select_t { + unsigned int perfcounter_select : TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tp0_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + } tp0_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter0_select_t f; +} tp0_perfcounter0_select_u; + + +/* + * TP0_PERFCOUNTER0_HI struct + */ + +#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16 + +#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TP0_PERFCOUNTER0_HI_MASK \ + (TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) + +#define TP0_PERFCOUNTER0_HI(perfcounter_hi) \ + ((perfcounter_hi << TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)) + +#define TP0_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tp0_perfcounter0_hi) \ + ((tp0_perfcounter0_hi & TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#define TP0_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tp0_perfcounter0_hi_reg, perfcounter_hi) \ + tp0_perfcounter0_hi_reg = (tp0_perfcounter0_hi_reg & ~TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_hi_t { + unsigned int perfcounter_hi : TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tp0_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + } tp0_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter0_hi_t f; +} tp0_perfcounter0_hi_u; + + +/* + * TP0_PERFCOUNTER0_LOW struct + */ + +#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TP0_PERFCOUNTER0_LOW_MASK \ + (TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) + +#define TP0_PERFCOUNTER0_LOW(perfcounter_low) \ + ((perfcounter_low << TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TP0_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tp0_perfcounter0_low) \ + ((tp0_perfcounter0_low & TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TP0_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tp0_perfcounter0_low_reg, perfcounter_low) \ + tp0_perfcounter0_low_reg = (tp0_perfcounter0_low_reg & ~TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_low_t { + unsigned int perfcounter_low : TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tp0_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_low_t { + unsigned int perfcounter_low : TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tp0_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter0_low_t f; +} tp0_perfcounter0_low_u; + + +/* + * TP0_PERFCOUNTER1_SELECT struct + */ + +#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TP0_PERFCOUNTER1_SELECT_MASK \ + (TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TP0_PERFCOUNTER1_SELECT(perfcounter_select) \ + ((perfcounter_select << TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TP0_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tp0_perfcounter1_select) \ + ((tp0_perfcounter1_select & TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TP0_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tp0_perfcounter1_select_reg, perfcounter_select) \ + tp0_perfcounter1_select_reg = (tp0_perfcounter1_select_reg & ~TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_select_t { + unsigned int perfcounter_select : TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tp0_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + } tp0_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter1_select_t f; +} tp0_perfcounter1_select_u; + + +/* + * TP0_PERFCOUNTER1_HI struct + */ + +#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16 + +#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TP0_PERFCOUNTER1_HI_MASK \ + (TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) + +#define TP0_PERFCOUNTER1_HI(perfcounter_hi) \ + ((perfcounter_hi << TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)) + +#define TP0_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tp0_perfcounter1_hi) \ + ((tp0_perfcounter1_hi & TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#define TP0_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tp0_perfcounter1_hi_reg, perfcounter_hi) \ + tp0_perfcounter1_hi_reg = (tp0_perfcounter1_hi_reg & ~TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_hi_t { + unsigned int perfcounter_hi : TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tp0_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + } tp0_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter1_hi_t f; +} tp0_perfcounter1_hi_u; + + +/* + * TP0_PERFCOUNTER1_LOW struct + */ + +#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TP0_PERFCOUNTER1_LOW_MASK \ + (TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) + +#define TP0_PERFCOUNTER1_LOW(perfcounter_low) \ + ((perfcounter_low << TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TP0_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tp0_perfcounter1_low) \ + ((tp0_perfcounter1_low & TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TP0_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tp0_perfcounter1_low_reg, perfcounter_low) \ + tp0_perfcounter1_low_reg = (tp0_perfcounter1_low_reg & ~TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_low_t { + unsigned int perfcounter_low : TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tp0_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_low_t { + unsigned int perfcounter_low : TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tp0_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter1_low_t f; +} tp0_perfcounter1_low_u; + + +/* + * TCM_PERFCOUNTER0_SELECT struct + */ + +#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCM_PERFCOUNTER0_SELECT_MASK \ + (TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCM_PERFCOUNTER0_SELECT(perfcounter_select) \ + ((perfcounter_select << TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCM_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcm_perfcounter0_select) \ + ((tcm_perfcounter0_select & TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCM_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcm_perfcounter0_select_reg, perfcounter_select) \ + tcm_perfcounter0_select_reg = (tcm_perfcounter0_select_reg & ~TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_select_t { + unsigned int perfcounter_select : TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcm_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcm_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter0_select_t f; +} tcm_perfcounter0_select_u; + + +/* + * TCM_PERFCOUNTER1_SELECT struct + */ + +#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCM_PERFCOUNTER1_SELECT_MASK \ + (TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCM_PERFCOUNTER1_SELECT(perfcounter_select) \ + ((perfcounter_select << TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCM_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcm_perfcounter1_select) \ + ((tcm_perfcounter1_select & TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCM_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcm_perfcounter1_select_reg, perfcounter_select) \ + tcm_perfcounter1_select_reg = (tcm_perfcounter1_select_reg & ~TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_select_t { + unsigned int perfcounter_select : TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcm_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcm_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter1_select_t f; +} tcm_perfcounter1_select_u; + + +/* + * TCM_PERFCOUNTER0_HI struct + */ + +#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCM_PERFCOUNTER0_HI_MASK \ + (TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) + +#define TCM_PERFCOUNTER0_HI(perfcounter_hi) \ + ((perfcounter_hi << TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCM_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcm_perfcounter0_hi) \ + ((tcm_perfcounter0_hi & TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#define TCM_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcm_perfcounter0_hi_reg, perfcounter_hi) \ + tcm_perfcounter0_hi_reg = (tcm_perfcounter0_hi_reg & ~TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_hi_t { + unsigned int perfcounter_hi : TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcm_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + } tcm_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter0_hi_t f; +} tcm_perfcounter0_hi_u; + + +/* + * TCM_PERFCOUNTER1_HI struct + */ + +#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCM_PERFCOUNTER1_HI_MASK \ + (TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) + +#define TCM_PERFCOUNTER1_HI(perfcounter_hi) \ + ((perfcounter_hi << TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCM_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcm_perfcounter1_hi) \ + ((tcm_perfcounter1_hi & TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#define TCM_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcm_perfcounter1_hi_reg, perfcounter_hi) \ + tcm_perfcounter1_hi_reg = (tcm_perfcounter1_hi_reg & ~TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_hi_t { + unsigned int perfcounter_hi : TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcm_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + } tcm_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter1_hi_t f; +} tcm_perfcounter1_hi_u; + + +/* + * TCM_PERFCOUNTER0_LOW struct + */ + +#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCM_PERFCOUNTER0_LOW_MASK \ + (TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) + +#define TCM_PERFCOUNTER0_LOW(perfcounter_low) \ + ((perfcounter_low << TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCM_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcm_perfcounter0_low) \ + ((tcm_perfcounter0_low & TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCM_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcm_perfcounter0_low_reg, perfcounter_low) \ + tcm_perfcounter0_low_reg = (tcm_perfcounter0_low_reg & ~TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_low_t { + unsigned int perfcounter_low : TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcm_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_low_t { + unsigned int perfcounter_low : TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcm_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter0_low_t f; +} tcm_perfcounter0_low_u; + + +/* + * TCM_PERFCOUNTER1_LOW struct + */ + +#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCM_PERFCOUNTER1_LOW_MASK \ + (TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) + +#define TCM_PERFCOUNTER1_LOW(perfcounter_low) \ + ((perfcounter_low << TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCM_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcm_perfcounter1_low) \ + ((tcm_perfcounter1_low & TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCM_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcm_perfcounter1_low_reg, perfcounter_low) \ + tcm_perfcounter1_low_reg = (tcm_perfcounter1_low_reg & ~TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_low_t { + unsigned int perfcounter_low : TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcm_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_low_t { + unsigned int perfcounter_low : TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcm_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter1_low_t f; +} tcm_perfcounter1_low_u; + + +/* + * TCF_PERFCOUNTER0_SELECT struct + */ + +#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER0_SELECT_MASK \ + (TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER0_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter0_select) \ + ((tcf_perfcounter0_select & TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter0_select_reg, perfcounter_select) \ + tcf_perfcounter0_select_reg = (tcf_perfcounter0_select_reg & ~TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter0_select_t f; +} tcf_perfcounter0_select_u; + + +/* + * TCF_PERFCOUNTER1_SELECT struct + */ + +#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER1_SELECT_MASK \ + (TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER1_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter1_select) \ + ((tcf_perfcounter1_select & TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter1_select_reg, perfcounter_select) \ + tcf_perfcounter1_select_reg = (tcf_perfcounter1_select_reg & ~TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter1_select_t f; +} tcf_perfcounter1_select_u; + + +/* + * TCF_PERFCOUNTER2_SELECT struct + */ + +#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER2_SELECT_MASK \ + (TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER2_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER2_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter2_select) \ + ((tcf_perfcounter2_select & TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER2_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter2_select_reg, perfcounter_select) \ + tcf_perfcounter2_select_reg = (tcf_perfcounter2_select_reg & ~TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter2_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter2_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter2_select_t f; +} tcf_perfcounter2_select_u; + + +/* + * TCF_PERFCOUNTER3_SELECT struct + */ + +#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER3_SELECT_MASK \ + (TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER3_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER3_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter3_select) \ + ((tcf_perfcounter3_select & TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER3_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter3_select_reg, perfcounter_select) \ + tcf_perfcounter3_select_reg = (tcf_perfcounter3_select_reg & ~TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter3_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter3_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter3_select_t f; +} tcf_perfcounter3_select_u; + + +/* + * TCF_PERFCOUNTER4_SELECT struct + */ + +#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER4_SELECT_MASK \ + (TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER4_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER4_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter4_select) \ + ((tcf_perfcounter4_select & TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER4_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter4_select_reg, perfcounter_select) \ + tcf_perfcounter4_select_reg = (tcf_perfcounter4_select_reg & ~TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter4_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter4_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter4_select_t f; +} tcf_perfcounter4_select_u; + + +/* + * TCF_PERFCOUNTER5_SELECT struct + */ + +#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER5_SELECT_MASK \ + (TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER5_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER5_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter5_select) \ + ((tcf_perfcounter5_select & TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER5_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter5_select_reg, perfcounter_select) \ + tcf_perfcounter5_select_reg = (tcf_perfcounter5_select_reg & ~TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter5_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter5_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter5_select_t f; +} tcf_perfcounter5_select_u; + + +/* + * TCF_PERFCOUNTER6_SELECT struct + */ + +#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER6_SELECT_MASK \ + (TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER6_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER6_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter6_select) \ + ((tcf_perfcounter6_select & TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER6_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter6_select_reg, perfcounter_select) \ + tcf_perfcounter6_select_reg = (tcf_perfcounter6_select_reg & ~TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter6_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter6_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter6_select_t f; +} tcf_perfcounter6_select_u; + + +/* + * TCF_PERFCOUNTER7_SELECT struct + */ + +#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER7_SELECT_MASK \ + (TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER7_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER7_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter7_select) \ + ((tcf_perfcounter7_select & TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER7_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter7_select_reg, perfcounter_select) \ + tcf_perfcounter7_select_reg = (tcf_perfcounter7_select_reg & ~TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter7_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter7_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter7_select_t f; +} tcf_perfcounter7_select_u; + + +/* + * TCF_PERFCOUNTER8_SELECT struct + */ + +#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER8_SELECT_MASK \ + (TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER8_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER8_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter8_select) \ + ((tcf_perfcounter8_select & TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER8_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter8_select_reg, perfcounter_select) \ + tcf_perfcounter8_select_reg = (tcf_perfcounter8_select_reg & ~TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter8_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter8_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter8_select_t f; +} tcf_perfcounter8_select_u; + + +/* + * TCF_PERFCOUNTER9_SELECT struct + */ + +#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER9_SELECT_MASK \ + (TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER9_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER9_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter9_select) \ + ((tcf_perfcounter9_select & TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER9_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter9_select_reg, perfcounter_select) \ + tcf_perfcounter9_select_reg = (tcf_perfcounter9_select_reg & ~TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter9_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter9_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter9_select_t f; +} tcf_perfcounter9_select_u; + + +/* + * TCF_PERFCOUNTER10_SELECT struct + */ + +#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER10_SELECT_MASK \ + (TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER10_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER10_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter10_select) \ + ((tcf_perfcounter10_select & TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER10_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter10_select_reg, perfcounter_select) \ + tcf_perfcounter10_select_reg = (tcf_perfcounter10_select_reg & ~TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter10_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter10_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter10_select_t f; +} tcf_perfcounter10_select_u; + + +/* + * TCF_PERFCOUNTER11_SELECT struct + */ + +#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER11_SELECT_MASK \ + (TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER11_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER11_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter11_select) \ + ((tcf_perfcounter11_select & TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER11_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter11_select_reg, perfcounter_select) \ + tcf_perfcounter11_select_reg = (tcf_perfcounter11_select_reg & ~TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter11_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter11_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter11_select_t f; +} tcf_perfcounter11_select_u; + + +/* + * TCF_PERFCOUNTER0_HI struct + */ + +#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER0_HI_MASK \ + (TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER0_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcf_perfcounter0_hi) \ + ((tcf_perfcounter0_hi & TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcf_perfcounter0_hi_reg, perfcounter_hi) \ + tcf_perfcounter0_hi_reg = (tcf_perfcounter0_hi_reg & ~TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter0_hi_t f; +} tcf_perfcounter0_hi_u; + + +/* + * TCF_PERFCOUNTER1_HI struct + */ + +#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER1_HI_MASK \ + (TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER1_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcf_perfcounter1_hi) \ + ((tcf_perfcounter1_hi & TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcf_perfcounter1_hi_reg, perfcounter_hi) \ + tcf_perfcounter1_hi_reg = (tcf_perfcounter1_hi_reg & ~TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter1_hi_t f; +} tcf_perfcounter1_hi_u; + + +/* + * TCF_PERFCOUNTER2_HI struct + */ + +#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER2_HI_MASK \ + (TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER2_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER2_HI_GET_PERFCOUNTER_HI(tcf_perfcounter2_hi) \ + ((tcf_perfcounter2_hi & TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER2_HI_SET_PERFCOUNTER_HI(tcf_perfcounter2_hi_reg, perfcounter_hi) \ + tcf_perfcounter2_hi_reg = (tcf_perfcounter2_hi_reg & ~TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter2_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter2_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter2_hi_t f; +} tcf_perfcounter2_hi_u; + + +/* + * TCF_PERFCOUNTER3_HI struct + */ + +#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER3_HI_MASK \ + (TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER3_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER3_HI_GET_PERFCOUNTER_HI(tcf_perfcounter3_hi) \ + ((tcf_perfcounter3_hi & TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER3_HI_SET_PERFCOUNTER_HI(tcf_perfcounter3_hi_reg, perfcounter_hi) \ + tcf_perfcounter3_hi_reg = (tcf_perfcounter3_hi_reg & ~TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter3_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter3_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter3_hi_t f; +} tcf_perfcounter3_hi_u; + + +/* + * TCF_PERFCOUNTER4_HI struct + */ + +#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER4_HI_MASK \ + (TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER4_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER4_HI_GET_PERFCOUNTER_HI(tcf_perfcounter4_hi) \ + ((tcf_perfcounter4_hi & TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER4_HI_SET_PERFCOUNTER_HI(tcf_perfcounter4_hi_reg, perfcounter_hi) \ + tcf_perfcounter4_hi_reg = (tcf_perfcounter4_hi_reg & ~TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter4_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter4_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter4_hi_t f; +} tcf_perfcounter4_hi_u; + + +/* + * TCF_PERFCOUNTER5_HI struct + */ + +#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER5_HI_MASK \ + (TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER5_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER5_HI_GET_PERFCOUNTER_HI(tcf_perfcounter5_hi) \ + ((tcf_perfcounter5_hi & TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER5_HI_SET_PERFCOUNTER_HI(tcf_perfcounter5_hi_reg, perfcounter_hi) \ + tcf_perfcounter5_hi_reg = (tcf_perfcounter5_hi_reg & ~TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter5_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter5_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter5_hi_t f; +} tcf_perfcounter5_hi_u; + + +/* + * TCF_PERFCOUNTER6_HI struct + */ + +#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER6_HI_MASK \ + (TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER6_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER6_HI_GET_PERFCOUNTER_HI(tcf_perfcounter6_hi) \ + ((tcf_perfcounter6_hi & TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER6_HI_SET_PERFCOUNTER_HI(tcf_perfcounter6_hi_reg, perfcounter_hi) \ + tcf_perfcounter6_hi_reg = (tcf_perfcounter6_hi_reg & ~TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter6_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter6_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter6_hi_t f; +} tcf_perfcounter6_hi_u; + + +/* + * TCF_PERFCOUNTER7_HI struct + */ + +#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER7_HI_MASK \ + (TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER7_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER7_HI_GET_PERFCOUNTER_HI(tcf_perfcounter7_hi) \ + ((tcf_perfcounter7_hi & TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER7_HI_SET_PERFCOUNTER_HI(tcf_perfcounter7_hi_reg, perfcounter_hi) \ + tcf_perfcounter7_hi_reg = (tcf_perfcounter7_hi_reg & ~TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter7_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter7_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter7_hi_t f; +} tcf_perfcounter7_hi_u; + + +/* + * TCF_PERFCOUNTER8_HI struct + */ + +#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER8_HI_MASK \ + (TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER8_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER8_HI_GET_PERFCOUNTER_HI(tcf_perfcounter8_hi) \ + ((tcf_perfcounter8_hi & TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER8_HI_SET_PERFCOUNTER_HI(tcf_perfcounter8_hi_reg, perfcounter_hi) \ + tcf_perfcounter8_hi_reg = (tcf_perfcounter8_hi_reg & ~TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter8_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter8_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter8_hi_t f; +} tcf_perfcounter8_hi_u; + + +/* + * TCF_PERFCOUNTER9_HI struct + */ + +#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER9_HI_MASK \ + (TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER9_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER9_HI_GET_PERFCOUNTER_HI(tcf_perfcounter9_hi) \ + ((tcf_perfcounter9_hi & TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER9_HI_SET_PERFCOUNTER_HI(tcf_perfcounter9_hi_reg, perfcounter_hi) \ + tcf_perfcounter9_hi_reg = (tcf_perfcounter9_hi_reg & ~TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter9_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter9_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter9_hi_t f; +} tcf_perfcounter9_hi_u; + + +/* + * TCF_PERFCOUNTER10_HI struct + */ + +#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER10_HI_MASK \ + (TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER10_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER10_HI_GET_PERFCOUNTER_HI(tcf_perfcounter10_hi) \ + ((tcf_perfcounter10_hi & TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER10_HI_SET_PERFCOUNTER_HI(tcf_perfcounter10_hi_reg, perfcounter_hi) \ + tcf_perfcounter10_hi_reg = (tcf_perfcounter10_hi_reg & ~TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter10_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter10_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter10_hi_t f; +} tcf_perfcounter10_hi_u; + + +/* + * TCF_PERFCOUNTER11_HI struct + */ + +#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER11_HI_MASK \ + (TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER11_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER11_HI_GET_PERFCOUNTER_HI(tcf_perfcounter11_hi) \ + ((tcf_perfcounter11_hi & TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER11_HI_SET_PERFCOUNTER_HI(tcf_perfcounter11_hi_reg, perfcounter_hi) \ + tcf_perfcounter11_hi_reg = (tcf_perfcounter11_hi_reg & ~TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter11_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter11_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter11_hi_t f; +} tcf_perfcounter11_hi_u; + + +/* + * TCF_PERFCOUNTER0_LOW struct + */ + +#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER0_LOW_MASK \ + (TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER0_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter0_low) \ + ((tcf_perfcounter0_low & TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter0_low_reg, perfcounter_low) \ + tcf_perfcounter0_low_reg = (tcf_perfcounter0_low_reg & ~TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter0_low_t f; +} tcf_perfcounter0_low_u; + + +/* + * TCF_PERFCOUNTER1_LOW struct + */ + +#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER1_LOW_MASK \ + (TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER1_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter1_low) \ + ((tcf_perfcounter1_low & TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter1_low_reg, perfcounter_low) \ + tcf_perfcounter1_low_reg = (tcf_perfcounter1_low_reg & ~TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter1_low_t f; +} tcf_perfcounter1_low_u; + + +/* + * TCF_PERFCOUNTER2_LOW struct + */ + +#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER2_LOW_MASK \ + (TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER2_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER2_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter2_low) \ + ((tcf_perfcounter2_low & TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER2_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter2_low_reg, perfcounter_low) \ + tcf_perfcounter2_low_reg = (tcf_perfcounter2_low_reg & ~TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter2_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter2_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter2_low_t f; +} tcf_perfcounter2_low_u; + + +/* + * TCF_PERFCOUNTER3_LOW struct + */ + +#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER3_LOW_MASK \ + (TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER3_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER3_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter3_low) \ + ((tcf_perfcounter3_low & TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER3_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter3_low_reg, perfcounter_low) \ + tcf_perfcounter3_low_reg = (tcf_perfcounter3_low_reg & ~TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter3_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter3_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter3_low_t f; +} tcf_perfcounter3_low_u; + + +/* + * TCF_PERFCOUNTER4_LOW struct + */ + +#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER4_LOW_MASK \ + (TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER4_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER4_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter4_low) \ + ((tcf_perfcounter4_low & TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER4_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter4_low_reg, perfcounter_low) \ + tcf_perfcounter4_low_reg = (tcf_perfcounter4_low_reg & ~TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter4_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter4_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter4_low_t f; +} tcf_perfcounter4_low_u; + + +/* + * TCF_PERFCOUNTER5_LOW struct + */ + +#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER5_LOW_MASK \ + (TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER5_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER5_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter5_low) \ + ((tcf_perfcounter5_low & TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER5_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter5_low_reg, perfcounter_low) \ + tcf_perfcounter5_low_reg = (tcf_perfcounter5_low_reg & ~TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter5_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter5_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter5_low_t f; +} tcf_perfcounter5_low_u; + + +/* + * TCF_PERFCOUNTER6_LOW struct + */ + +#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER6_LOW_MASK \ + (TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER6_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER6_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter6_low) \ + ((tcf_perfcounter6_low & TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER6_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter6_low_reg, perfcounter_low) \ + tcf_perfcounter6_low_reg = (tcf_perfcounter6_low_reg & ~TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter6_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter6_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter6_low_t f; +} tcf_perfcounter6_low_u; + + +/* + * TCF_PERFCOUNTER7_LOW struct + */ + +#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER7_LOW_MASK \ + (TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER7_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER7_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter7_low) \ + ((tcf_perfcounter7_low & TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER7_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter7_low_reg, perfcounter_low) \ + tcf_perfcounter7_low_reg = (tcf_perfcounter7_low_reg & ~TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter7_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter7_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter7_low_t f; +} tcf_perfcounter7_low_u; + + +/* + * TCF_PERFCOUNTER8_LOW struct + */ + +#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER8_LOW_MASK \ + (TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER8_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER8_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter8_low) \ + ((tcf_perfcounter8_low & TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER8_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter8_low_reg, perfcounter_low) \ + tcf_perfcounter8_low_reg = (tcf_perfcounter8_low_reg & ~TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter8_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter8_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter8_low_t f; +} tcf_perfcounter8_low_u; + + +/* + * TCF_PERFCOUNTER9_LOW struct + */ + +#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER9_LOW_MASK \ + (TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER9_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER9_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter9_low) \ + ((tcf_perfcounter9_low & TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER9_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter9_low_reg, perfcounter_low) \ + tcf_perfcounter9_low_reg = (tcf_perfcounter9_low_reg & ~TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter9_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter9_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter9_low_t f; +} tcf_perfcounter9_low_u; + + +/* + * TCF_PERFCOUNTER10_LOW struct + */ + +#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER10_LOW_MASK \ + (TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER10_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER10_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter10_low) \ + ((tcf_perfcounter10_low & TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER10_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter10_low_reg, perfcounter_low) \ + tcf_perfcounter10_low_reg = (tcf_perfcounter10_low_reg & ~TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter10_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter10_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter10_low_t f; +} tcf_perfcounter10_low_u; + + +/* + * TCF_PERFCOUNTER11_LOW struct + */ + +#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER11_LOW_MASK \ + (TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER11_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER11_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter11_low) \ + ((tcf_perfcounter11_low & TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER11_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter11_low_reg, perfcounter_low) \ + tcf_perfcounter11_low_reg = (tcf_perfcounter11_low_reg & ~TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter11_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter11_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter11_low_t f; +} tcf_perfcounter11_low_u; + + +/* + * TCF_DEBUG struct + */ + +#define TCF_DEBUG_not_MH_TC_rtr_SIZE 1 +#define TCF_DEBUG_TC_MH_send_SIZE 1 +#define TCF_DEBUG_not_FG0_rtr_SIZE 1 +#define TCF_DEBUG_not_TCB_TCO_rtr_SIZE 1 +#define TCF_DEBUG_TCB_ff_stall_SIZE 1 +#define TCF_DEBUG_TCB_miss_stall_SIZE 1 +#define TCF_DEBUG_TCA_TCB_stall_SIZE 1 +#define TCF_DEBUG_PF0_stall_SIZE 1 +#define TCF_DEBUG_TP0_full_SIZE 1 +#define TCF_DEBUG_TPC_full_SIZE 1 +#define TCF_DEBUG_not_TPC_rtr_SIZE 1 +#define TCF_DEBUG_tca_state_rts_SIZE 1 +#define TCF_DEBUG_tca_rts_SIZE 1 + +#define TCF_DEBUG_not_MH_TC_rtr_SHIFT 6 +#define TCF_DEBUG_TC_MH_send_SHIFT 7 +#define TCF_DEBUG_not_FG0_rtr_SHIFT 8 +#define TCF_DEBUG_not_TCB_TCO_rtr_SHIFT 12 +#define TCF_DEBUG_TCB_ff_stall_SHIFT 13 +#define TCF_DEBUG_TCB_miss_stall_SHIFT 14 +#define TCF_DEBUG_TCA_TCB_stall_SHIFT 15 +#define TCF_DEBUG_PF0_stall_SHIFT 16 +#define TCF_DEBUG_TP0_full_SHIFT 20 +#define TCF_DEBUG_TPC_full_SHIFT 24 +#define TCF_DEBUG_not_TPC_rtr_SHIFT 25 +#define TCF_DEBUG_tca_state_rts_SHIFT 26 +#define TCF_DEBUG_tca_rts_SHIFT 27 + +#define TCF_DEBUG_not_MH_TC_rtr_MASK 0x00000040 +#define TCF_DEBUG_TC_MH_send_MASK 0x00000080 +#define TCF_DEBUG_not_FG0_rtr_MASK 0x00000100 +#define TCF_DEBUG_not_TCB_TCO_rtr_MASK 0x00001000 +#define TCF_DEBUG_TCB_ff_stall_MASK 0x00002000 +#define TCF_DEBUG_TCB_miss_stall_MASK 0x00004000 +#define TCF_DEBUG_TCA_TCB_stall_MASK 0x00008000 +#define TCF_DEBUG_PF0_stall_MASK 0x00010000 +#define TCF_DEBUG_TP0_full_MASK 0x00100000 +#define TCF_DEBUG_TPC_full_MASK 0x01000000 +#define TCF_DEBUG_not_TPC_rtr_MASK 0x02000000 +#define TCF_DEBUG_tca_state_rts_MASK 0x04000000 +#define TCF_DEBUG_tca_rts_MASK 0x08000000 + +#define TCF_DEBUG_MASK \ + (TCF_DEBUG_not_MH_TC_rtr_MASK | \ + TCF_DEBUG_TC_MH_send_MASK | \ + TCF_DEBUG_not_FG0_rtr_MASK | \ + TCF_DEBUG_not_TCB_TCO_rtr_MASK | \ + TCF_DEBUG_TCB_ff_stall_MASK | \ + TCF_DEBUG_TCB_miss_stall_MASK | \ + TCF_DEBUG_TCA_TCB_stall_MASK | \ + TCF_DEBUG_PF0_stall_MASK | \ + TCF_DEBUG_TP0_full_MASK | \ + TCF_DEBUG_TPC_full_MASK | \ + TCF_DEBUG_not_TPC_rtr_MASK | \ + TCF_DEBUG_tca_state_rts_MASK | \ + TCF_DEBUG_tca_rts_MASK) + +#define TCF_DEBUG(not_mh_tc_rtr, tc_mh_send, not_fg0_rtr, not_tcb_tco_rtr, tcb_ff_stall, tcb_miss_stall, tca_tcb_stall, pf0_stall, tp0_full, tpc_full, not_tpc_rtr, tca_state_rts, tca_rts) \ + ((not_mh_tc_rtr << TCF_DEBUG_not_MH_TC_rtr_SHIFT) | \ + (tc_mh_send << TCF_DEBUG_TC_MH_send_SHIFT) | \ + (not_fg0_rtr << TCF_DEBUG_not_FG0_rtr_SHIFT) | \ + (not_tcb_tco_rtr << TCF_DEBUG_not_TCB_TCO_rtr_SHIFT) | \ + (tcb_ff_stall << TCF_DEBUG_TCB_ff_stall_SHIFT) | \ + (tcb_miss_stall << TCF_DEBUG_TCB_miss_stall_SHIFT) | \ + (tca_tcb_stall << TCF_DEBUG_TCA_TCB_stall_SHIFT) | \ + (pf0_stall << TCF_DEBUG_PF0_stall_SHIFT) | \ + (tp0_full << TCF_DEBUG_TP0_full_SHIFT) | \ + (tpc_full << TCF_DEBUG_TPC_full_SHIFT) | \ + (not_tpc_rtr << TCF_DEBUG_not_TPC_rtr_SHIFT) | \ + (tca_state_rts << TCF_DEBUG_tca_state_rts_SHIFT) | \ + (tca_rts << TCF_DEBUG_tca_rts_SHIFT)) + +#define TCF_DEBUG_GET_not_MH_TC_rtr(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_not_MH_TC_rtr_MASK) >> TCF_DEBUG_not_MH_TC_rtr_SHIFT) +#define TCF_DEBUG_GET_TC_MH_send(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TC_MH_send_MASK) >> TCF_DEBUG_TC_MH_send_SHIFT) +#define TCF_DEBUG_GET_not_FG0_rtr(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_not_FG0_rtr_MASK) >> TCF_DEBUG_not_FG0_rtr_SHIFT) +#define TCF_DEBUG_GET_not_TCB_TCO_rtr(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_not_TCB_TCO_rtr_MASK) >> TCF_DEBUG_not_TCB_TCO_rtr_SHIFT) +#define TCF_DEBUG_GET_TCB_ff_stall(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TCB_ff_stall_MASK) >> TCF_DEBUG_TCB_ff_stall_SHIFT) +#define TCF_DEBUG_GET_TCB_miss_stall(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TCB_miss_stall_MASK) >> TCF_DEBUG_TCB_miss_stall_SHIFT) +#define TCF_DEBUG_GET_TCA_TCB_stall(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TCA_TCB_stall_MASK) >> TCF_DEBUG_TCA_TCB_stall_SHIFT) +#define TCF_DEBUG_GET_PF0_stall(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_PF0_stall_MASK) >> TCF_DEBUG_PF0_stall_SHIFT) +#define TCF_DEBUG_GET_TP0_full(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TP0_full_MASK) >> TCF_DEBUG_TP0_full_SHIFT) +#define TCF_DEBUG_GET_TPC_full(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TPC_full_MASK) >> TCF_DEBUG_TPC_full_SHIFT) +#define TCF_DEBUG_GET_not_TPC_rtr(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_not_TPC_rtr_MASK) >> TCF_DEBUG_not_TPC_rtr_SHIFT) +#define TCF_DEBUG_GET_tca_state_rts(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_tca_state_rts_MASK) >> TCF_DEBUG_tca_state_rts_SHIFT) +#define TCF_DEBUG_GET_tca_rts(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_tca_rts_MASK) >> TCF_DEBUG_tca_rts_SHIFT) + +#define TCF_DEBUG_SET_not_MH_TC_rtr(tcf_debug_reg, not_mh_tc_rtr) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_MH_TC_rtr_MASK) | (not_mh_tc_rtr << TCF_DEBUG_not_MH_TC_rtr_SHIFT) +#define TCF_DEBUG_SET_TC_MH_send(tcf_debug_reg, tc_mh_send) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TC_MH_send_MASK) | (tc_mh_send << TCF_DEBUG_TC_MH_send_SHIFT) +#define TCF_DEBUG_SET_not_FG0_rtr(tcf_debug_reg, not_fg0_rtr) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_FG0_rtr_MASK) | (not_fg0_rtr << TCF_DEBUG_not_FG0_rtr_SHIFT) +#define TCF_DEBUG_SET_not_TCB_TCO_rtr(tcf_debug_reg, not_tcb_tco_rtr) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_TCB_TCO_rtr_MASK) | (not_tcb_tco_rtr << TCF_DEBUG_not_TCB_TCO_rtr_SHIFT) +#define TCF_DEBUG_SET_TCB_ff_stall(tcf_debug_reg, tcb_ff_stall) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCB_ff_stall_MASK) | (tcb_ff_stall << TCF_DEBUG_TCB_ff_stall_SHIFT) +#define TCF_DEBUG_SET_TCB_miss_stall(tcf_debug_reg, tcb_miss_stall) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCB_miss_stall_MASK) | (tcb_miss_stall << TCF_DEBUG_TCB_miss_stall_SHIFT) +#define TCF_DEBUG_SET_TCA_TCB_stall(tcf_debug_reg, tca_tcb_stall) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCA_TCB_stall_MASK) | (tca_tcb_stall << TCF_DEBUG_TCA_TCB_stall_SHIFT) +#define TCF_DEBUG_SET_PF0_stall(tcf_debug_reg, pf0_stall) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_PF0_stall_MASK) | (pf0_stall << TCF_DEBUG_PF0_stall_SHIFT) +#define TCF_DEBUG_SET_TP0_full(tcf_debug_reg, tp0_full) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TP0_full_MASK) | (tp0_full << TCF_DEBUG_TP0_full_SHIFT) +#define TCF_DEBUG_SET_TPC_full(tcf_debug_reg, tpc_full) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TPC_full_MASK) | (tpc_full << TCF_DEBUG_TPC_full_SHIFT) +#define TCF_DEBUG_SET_not_TPC_rtr(tcf_debug_reg, not_tpc_rtr) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_TPC_rtr_MASK) | (not_tpc_rtr << TCF_DEBUG_not_TPC_rtr_SHIFT) +#define TCF_DEBUG_SET_tca_state_rts(tcf_debug_reg, tca_state_rts) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_tca_state_rts_MASK) | (tca_state_rts << TCF_DEBUG_tca_state_rts_SHIFT) +#define TCF_DEBUG_SET_tca_rts(tcf_debug_reg, tca_rts) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_tca_rts_MASK) | (tca_rts << TCF_DEBUG_tca_rts_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_debug_t { + unsigned int : 6; + unsigned int not_mh_tc_rtr : TCF_DEBUG_not_MH_TC_rtr_SIZE; + unsigned int tc_mh_send : TCF_DEBUG_TC_MH_send_SIZE; + unsigned int not_fg0_rtr : TCF_DEBUG_not_FG0_rtr_SIZE; + unsigned int : 3; + unsigned int not_tcb_tco_rtr : TCF_DEBUG_not_TCB_TCO_rtr_SIZE; + unsigned int tcb_ff_stall : TCF_DEBUG_TCB_ff_stall_SIZE; + unsigned int tcb_miss_stall : TCF_DEBUG_TCB_miss_stall_SIZE; + unsigned int tca_tcb_stall : TCF_DEBUG_TCA_TCB_stall_SIZE; + unsigned int pf0_stall : TCF_DEBUG_PF0_stall_SIZE; + unsigned int : 3; + unsigned int tp0_full : TCF_DEBUG_TP0_full_SIZE; + unsigned int : 3; + unsigned int tpc_full : TCF_DEBUG_TPC_full_SIZE; + unsigned int not_tpc_rtr : TCF_DEBUG_not_TPC_rtr_SIZE; + unsigned int tca_state_rts : TCF_DEBUG_tca_state_rts_SIZE; + unsigned int tca_rts : TCF_DEBUG_tca_rts_SIZE; + unsigned int : 4; + } tcf_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_debug_t { + unsigned int : 4; + unsigned int tca_rts : TCF_DEBUG_tca_rts_SIZE; + unsigned int tca_state_rts : TCF_DEBUG_tca_state_rts_SIZE; + unsigned int not_tpc_rtr : TCF_DEBUG_not_TPC_rtr_SIZE; + unsigned int tpc_full : TCF_DEBUG_TPC_full_SIZE; + unsigned int : 3; + unsigned int tp0_full : TCF_DEBUG_TP0_full_SIZE; + unsigned int : 3; + unsigned int pf0_stall : TCF_DEBUG_PF0_stall_SIZE; + unsigned int tca_tcb_stall : TCF_DEBUG_TCA_TCB_stall_SIZE; + unsigned int tcb_miss_stall : TCF_DEBUG_TCB_miss_stall_SIZE; + unsigned int tcb_ff_stall : TCF_DEBUG_TCB_ff_stall_SIZE; + unsigned int not_tcb_tco_rtr : TCF_DEBUG_not_TCB_TCO_rtr_SIZE; + unsigned int : 3; + unsigned int not_fg0_rtr : TCF_DEBUG_not_FG0_rtr_SIZE; + unsigned int tc_mh_send : TCF_DEBUG_TC_MH_send_SIZE; + unsigned int not_mh_tc_rtr : TCF_DEBUG_not_MH_TC_rtr_SIZE; + unsigned int : 6; + } tcf_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_debug_t f; +} tcf_debug_u; + + +/* + * TCA_FIFO_DEBUG struct + */ + +#define TCA_FIFO_DEBUG_tp0_full_SIZE 1 +#define TCA_FIFO_DEBUG_tpc_full_SIZE 1 +#define TCA_FIFO_DEBUG_load_tpc_fifo_SIZE 1 +#define TCA_FIFO_DEBUG_load_tp_fifos_SIZE 1 +#define TCA_FIFO_DEBUG_FW_full_SIZE 1 +#define TCA_FIFO_DEBUG_not_FW_rtr0_SIZE 1 +#define TCA_FIFO_DEBUG_FW_rts0_SIZE 1 +#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE 1 +#define TCA_FIFO_DEBUG_FW_tpc_rts_SIZE 1 + +#define TCA_FIFO_DEBUG_tp0_full_SHIFT 0 +#define TCA_FIFO_DEBUG_tpc_full_SHIFT 4 +#define TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT 5 +#define TCA_FIFO_DEBUG_load_tp_fifos_SHIFT 6 +#define TCA_FIFO_DEBUG_FW_full_SHIFT 7 +#define TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT 8 +#define TCA_FIFO_DEBUG_FW_rts0_SHIFT 12 +#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT 16 +#define TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT 17 + +#define TCA_FIFO_DEBUG_tp0_full_MASK 0x00000001 +#define TCA_FIFO_DEBUG_tpc_full_MASK 0x00000010 +#define TCA_FIFO_DEBUG_load_tpc_fifo_MASK 0x00000020 +#define TCA_FIFO_DEBUG_load_tp_fifos_MASK 0x00000040 +#define TCA_FIFO_DEBUG_FW_full_MASK 0x00000080 +#define TCA_FIFO_DEBUG_not_FW_rtr0_MASK 0x00000100 +#define TCA_FIFO_DEBUG_FW_rts0_MASK 0x00001000 +#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK 0x00010000 +#define TCA_FIFO_DEBUG_FW_tpc_rts_MASK 0x00020000 + +#define TCA_FIFO_DEBUG_MASK \ + (TCA_FIFO_DEBUG_tp0_full_MASK | \ + TCA_FIFO_DEBUG_tpc_full_MASK | \ + TCA_FIFO_DEBUG_load_tpc_fifo_MASK | \ + TCA_FIFO_DEBUG_load_tp_fifos_MASK | \ + TCA_FIFO_DEBUG_FW_full_MASK | \ + TCA_FIFO_DEBUG_not_FW_rtr0_MASK | \ + TCA_FIFO_DEBUG_FW_rts0_MASK | \ + TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK | \ + TCA_FIFO_DEBUG_FW_tpc_rts_MASK) + +#define TCA_FIFO_DEBUG(tp0_full, tpc_full, load_tpc_fifo, load_tp_fifos, fw_full, not_fw_rtr0, fw_rts0, not_fw_tpc_rtr, fw_tpc_rts) \ + ((tp0_full << TCA_FIFO_DEBUG_tp0_full_SHIFT) | \ + (tpc_full << TCA_FIFO_DEBUG_tpc_full_SHIFT) | \ + (load_tpc_fifo << TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT) | \ + (load_tp_fifos << TCA_FIFO_DEBUG_load_tp_fifos_SHIFT) | \ + (fw_full << TCA_FIFO_DEBUG_FW_full_SHIFT) | \ + (not_fw_rtr0 << TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT) | \ + (fw_rts0 << TCA_FIFO_DEBUG_FW_rts0_SHIFT) | \ + (not_fw_tpc_rtr << TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT) | \ + (fw_tpc_rts << TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT)) + +#define TCA_FIFO_DEBUG_GET_tp0_full(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_tp0_full_MASK) >> TCA_FIFO_DEBUG_tp0_full_SHIFT) +#define TCA_FIFO_DEBUG_GET_tpc_full(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_tpc_full_MASK) >> TCA_FIFO_DEBUG_tpc_full_SHIFT) +#define TCA_FIFO_DEBUG_GET_load_tpc_fifo(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_load_tpc_fifo_MASK) >> TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT) +#define TCA_FIFO_DEBUG_GET_load_tp_fifos(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_load_tp_fifos_MASK) >> TCA_FIFO_DEBUG_load_tp_fifos_SHIFT) +#define TCA_FIFO_DEBUG_GET_FW_full(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_full_MASK) >> TCA_FIFO_DEBUG_FW_full_SHIFT) +#define TCA_FIFO_DEBUG_GET_not_FW_rtr0(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_not_FW_rtr0_MASK) >> TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT) +#define TCA_FIFO_DEBUG_GET_FW_rts0(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_rts0_MASK) >> TCA_FIFO_DEBUG_FW_rts0_SHIFT) +#define TCA_FIFO_DEBUG_GET_not_FW_tpc_rtr(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK) >> TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT) +#define TCA_FIFO_DEBUG_GET_FW_tpc_rts(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_tpc_rts_MASK) >> TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT) + +#define TCA_FIFO_DEBUG_SET_tp0_full(tca_fifo_debug_reg, tp0_full) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_tp0_full_MASK) | (tp0_full << TCA_FIFO_DEBUG_tp0_full_SHIFT) +#define TCA_FIFO_DEBUG_SET_tpc_full(tca_fifo_debug_reg, tpc_full) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_tpc_full_MASK) | (tpc_full << TCA_FIFO_DEBUG_tpc_full_SHIFT) +#define TCA_FIFO_DEBUG_SET_load_tpc_fifo(tca_fifo_debug_reg, load_tpc_fifo) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_load_tpc_fifo_MASK) | (load_tpc_fifo << TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT) +#define TCA_FIFO_DEBUG_SET_load_tp_fifos(tca_fifo_debug_reg, load_tp_fifos) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_load_tp_fifos_MASK) | (load_tp_fifos << TCA_FIFO_DEBUG_load_tp_fifos_SHIFT) +#define TCA_FIFO_DEBUG_SET_FW_full(tca_fifo_debug_reg, fw_full) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_full_MASK) | (fw_full << TCA_FIFO_DEBUG_FW_full_SHIFT) +#define TCA_FIFO_DEBUG_SET_not_FW_rtr0(tca_fifo_debug_reg, not_fw_rtr0) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_not_FW_rtr0_MASK) | (not_fw_rtr0 << TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT) +#define TCA_FIFO_DEBUG_SET_FW_rts0(tca_fifo_debug_reg, fw_rts0) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_rts0_MASK) | (fw_rts0 << TCA_FIFO_DEBUG_FW_rts0_SHIFT) +#define TCA_FIFO_DEBUG_SET_not_FW_tpc_rtr(tca_fifo_debug_reg, not_fw_tpc_rtr) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK) | (not_fw_tpc_rtr << TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT) +#define TCA_FIFO_DEBUG_SET_FW_tpc_rts(tca_fifo_debug_reg, fw_tpc_rts) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_tpc_rts_MASK) | (fw_tpc_rts << TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tca_fifo_debug_t { + unsigned int tp0_full : TCA_FIFO_DEBUG_tp0_full_SIZE; + unsigned int : 3; + unsigned int tpc_full : TCA_FIFO_DEBUG_tpc_full_SIZE; + unsigned int load_tpc_fifo : TCA_FIFO_DEBUG_load_tpc_fifo_SIZE; + unsigned int load_tp_fifos : TCA_FIFO_DEBUG_load_tp_fifos_SIZE; + unsigned int fw_full : TCA_FIFO_DEBUG_FW_full_SIZE; + unsigned int not_fw_rtr0 : TCA_FIFO_DEBUG_not_FW_rtr0_SIZE; + unsigned int : 3; + unsigned int fw_rts0 : TCA_FIFO_DEBUG_FW_rts0_SIZE; + unsigned int : 3; + unsigned int not_fw_tpc_rtr : TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE; + unsigned int fw_tpc_rts : TCA_FIFO_DEBUG_FW_tpc_rts_SIZE; + unsigned int : 14; + } tca_fifo_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tca_fifo_debug_t { + unsigned int : 14; + unsigned int fw_tpc_rts : TCA_FIFO_DEBUG_FW_tpc_rts_SIZE; + unsigned int not_fw_tpc_rtr : TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE; + unsigned int : 3; + unsigned int fw_rts0 : TCA_FIFO_DEBUG_FW_rts0_SIZE; + unsigned int : 3; + unsigned int not_fw_rtr0 : TCA_FIFO_DEBUG_not_FW_rtr0_SIZE; + unsigned int fw_full : TCA_FIFO_DEBUG_FW_full_SIZE; + unsigned int load_tp_fifos : TCA_FIFO_DEBUG_load_tp_fifos_SIZE; + unsigned int load_tpc_fifo : TCA_FIFO_DEBUG_load_tpc_fifo_SIZE; + unsigned int tpc_full : TCA_FIFO_DEBUG_tpc_full_SIZE; + unsigned int : 3; + unsigned int tp0_full : TCA_FIFO_DEBUG_tp0_full_SIZE; + } tca_fifo_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tca_fifo_debug_t f; +} tca_fifo_debug_u; + + +/* + * TCA_PROBE_DEBUG struct + */ + +#define TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE 1 + +#define TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT 0 + +#define TCA_PROBE_DEBUG_ProbeFilter_stall_MASK 0x00000001 + +#define TCA_PROBE_DEBUG_MASK \ + (TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) + +#define TCA_PROBE_DEBUG(probefilter_stall) \ + ((probefilter_stall << TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT)) + +#define TCA_PROBE_DEBUG_GET_ProbeFilter_stall(tca_probe_debug) \ + ((tca_probe_debug & TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) >> TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT) + +#define TCA_PROBE_DEBUG_SET_ProbeFilter_stall(tca_probe_debug_reg, probefilter_stall) \ + tca_probe_debug_reg = (tca_probe_debug_reg & ~TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) | (probefilter_stall << TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tca_probe_debug_t { + unsigned int probefilter_stall : TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE; + unsigned int : 31; + } tca_probe_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tca_probe_debug_t { + unsigned int : 31; + unsigned int probefilter_stall : TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE; + } tca_probe_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tca_probe_debug_t f; +} tca_probe_debug_u; + + +/* + * TCA_TPC_DEBUG struct + */ + +#define TCA_TPC_DEBUG_captue_state_rts_SIZE 1 +#define TCA_TPC_DEBUG_capture_tca_rts_SIZE 1 + +#define TCA_TPC_DEBUG_captue_state_rts_SHIFT 12 +#define TCA_TPC_DEBUG_capture_tca_rts_SHIFT 13 + +#define TCA_TPC_DEBUG_captue_state_rts_MASK 0x00001000 +#define TCA_TPC_DEBUG_capture_tca_rts_MASK 0x00002000 + +#define TCA_TPC_DEBUG_MASK \ + (TCA_TPC_DEBUG_captue_state_rts_MASK | \ + TCA_TPC_DEBUG_capture_tca_rts_MASK) + +#define TCA_TPC_DEBUG(captue_state_rts, capture_tca_rts) \ + ((captue_state_rts << TCA_TPC_DEBUG_captue_state_rts_SHIFT) | \ + (capture_tca_rts << TCA_TPC_DEBUG_capture_tca_rts_SHIFT)) + +#define TCA_TPC_DEBUG_GET_captue_state_rts(tca_tpc_debug) \ + ((tca_tpc_debug & TCA_TPC_DEBUG_captue_state_rts_MASK) >> TCA_TPC_DEBUG_captue_state_rts_SHIFT) +#define TCA_TPC_DEBUG_GET_capture_tca_rts(tca_tpc_debug) \ + ((tca_tpc_debug & TCA_TPC_DEBUG_capture_tca_rts_MASK) >> TCA_TPC_DEBUG_capture_tca_rts_SHIFT) + +#define TCA_TPC_DEBUG_SET_captue_state_rts(tca_tpc_debug_reg, captue_state_rts) \ + tca_tpc_debug_reg = (tca_tpc_debug_reg & ~TCA_TPC_DEBUG_captue_state_rts_MASK) | (captue_state_rts << TCA_TPC_DEBUG_captue_state_rts_SHIFT) +#define TCA_TPC_DEBUG_SET_capture_tca_rts(tca_tpc_debug_reg, capture_tca_rts) \ + tca_tpc_debug_reg = (tca_tpc_debug_reg & ~TCA_TPC_DEBUG_capture_tca_rts_MASK) | (capture_tca_rts << TCA_TPC_DEBUG_capture_tca_rts_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tca_tpc_debug_t { + unsigned int : 12; + unsigned int captue_state_rts : TCA_TPC_DEBUG_captue_state_rts_SIZE; + unsigned int capture_tca_rts : TCA_TPC_DEBUG_capture_tca_rts_SIZE; + unsigned int : 18; + } tca_tpc_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tca_tpc_debug_t { + unsigned int : 18; + unsigned int capture_tca_rts : TCA_TPC_DEBUG_capture_tca_rts_SIZE; + unsigned int captue_state_rts : TCA_TPC_DEBUG_captue_state_rts_SIZE; + unsigned int : 12; + } tca_tpc_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tca_tpc_debug_t f; +} tca_tpc_debug_u; + + +/* + * TCB_CORE_DEBUG struct + */ + +#define TCB_CORE_DEBUG_access512_SIZE 1 +#define TCB_CORE_DEBUG_tiled_SIZE 1 +#define TCB_CORE_DEBUG_opcode_SIZE 3 +#define TCB_CORE_DEBUG_format_SIZE 6 +#define TCB_CORE_DEBUG_sector_format_SIZE 5 +#define TCB_CORE_DEBUG_sector_format512_SIZE 3 + +#define TCB_CORE_DEBUG_access512_SHIFT 0 +#define TCB_CORE_DEBUG_tiled_SHIFT 1 +#define TCB_CORE_DEBUG_opcode_SHIFT 4 +#define TCB_CORE_DEBUG_format_SHIFT 8 +#define TCB_CORE_DEBUG_sector_format_SHIFT 16 +#define TCB_CORE_DEBUG_sector_format512_SHIFT 24 + +#define TCB_CORE_DEBUG_access512_MASK 0x00000001 +#define TCB_CORE_DEBUG_tiled_MASK 0x00000002 +#define TCB_CORE_DEBUG_opcode_MASK 0x00000070 +#define TCB_CORE_DEBUG_format_MASK 0x00003f00 +#define TCB_CORE_DEBUG_sector_format_MASK 0x001f0000 +#define TCB_CORE_DEBUG_sector_format512_MASK 0x07000000 + +#define TCB_CORE_DEBUG_MASK \ + (TCB_CORE_DEBUG_access512_MASK | \ + TCB_CORE_DEBUG_tiled_MASK | \ + TCB_CORE_DEBUG_opcode_MASK | \ + TCB_CORE_DEBUG_format_MASK | \ + TCB_CORE_DEBUG_sector_format_MASK | \ + TCB_CORE_DEBUG_sector_format512_MASK) + +#define TCB_CORE_DEBUG(access512, tiled, opcode, format, sector_format, sector_format512) \ + ((access512 << TCB_CORE_DEBUG_access512_SHIFT) | \ + (tiled << TCB_CORE_DEBUG_tiled_SHIFT) | \ + (opcode << TCB_CORE_DEBUG_opcode_SHIFT) | \ + (format << TCB_CORE_DEBUG_format_SHIFT) | \ + (sector_format << TCB_CORE_DEBUG_sector_format_SHIFT) | \ + (sector_format512 << TCB_CORE_DEBUG_sector_format512_SHIFT)) + +#define TCB_CORE_DEBUG_GET_access512(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_access512_MASK) >> TCB_CORE_DEBUG_access512_SHIFT) +#define TCB_CORE_DEBUG_GET_tiled(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_tiled_MASK) >> TCB_CORE_DEBUG_tiled_SHIFT) +#define TCB_CORE_DEBUG_GET_opcode(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_opcode_MASK) >> TCB_CORE_DEBUG_opcode_SHIFT) +#define TCB_CORE_DEBUG_GET_format(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_format_MASK) >> TCB_CORE_DEBUG_format_SHIFT) +#define TCB_CORE_DEBUG_GET_sector_format(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_sector_format_MASK) >> TCB_CORE_DEBUG_sector_format_SHIFT) +#define TCB_CORE_DEBUG_GET_sector_format512(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_sector_format512_MASK) >> TCB_CORE_DEBUG_sector_format512_SHIFT) + +#define TCB_CORE_DEBUG_SET_access512(tcb_core_debug_reg, access512) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_access512_MASK) | (access512 << TCB_CORE_DEBUG_access512_SHIFT) +#define TCB_CORE_DEBUG_SET_tiled(tcb_core_debug_reg, tiled) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_tiled_MASK) | (tiled << TCB_CORE_DEBUG_tiled_SHIFT) +#define TCB_CORE_DEBUG_SET_opcode(tcb_core_debug_reg, opcode) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_opcode_MASK) | (opcode << TCB_CORE_DEBUG_opcode_SHIFT) +#define TCB_CORE_DEBUG_SET_format(tcb_core_debug_reg, format) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_format_MASK) | (format << TCB_CORE_DEBUG_format_SHIFT) +#define TCB_CORE_DEBUG_SET_sector_format(tcb_core_debug_reg, sector_format) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_sector_format_MASK) | (sector_format << TCB_CORE_DEBUG_sector_format_SHIFT) +#define TCB_CORE_DEBUG_SET_sector_format512(tcb_core_debug_reg, sector_format512) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_sector_format512_MASK) | (sector_format512 << TCB_CORE_DEBUG_sector_format512_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_core_debug_t { + unsigned int access512 : TCB_CORE_DEBUG_access512_SIZE; + unsigned int tiled : TCB_CORE_DEBUG_tiled_SIZE; + unsigned int : 2; + unsigned int opcode : TCB_CORE_DEBUG_opcode_SIZE; + unsigned int : 1; + unsigned int format : TCB_CORE_DEBUG_format_SIZE; + unsigned int : 2; + unsigned int sector_format : TCB_CORE_DEBUG_sector_format_SIZE; + unsigned int : 3; + unsigned int sector_format512 : TCB_CORE_DEBUG_sector_format512_SIZE; + unsigned int : 5; + } tcb_core_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_core_debug_t { + unsigned int : 5; + unsigned int sector_format512 : TCB_CORE_DEBUG_sector_format512_SIZE; + unsigned int : 3; + unsigned int sector_format : TCB_CORE_DEBUG_sector_format_SIZE; + unsigned int : 2; + unsigned int format : TCB_CORE_DEBUG_format_SIZE; + unsigned int : 1; + unsigned int opcode : TCB_CORE_DEBUG_opcode_SIZE; + unsigned int : 2; + unsigned int tiled : TCB_CORE_DEBUG_tiled_SIZE; + unsigned int access512 : TCB_CORE_DEBUG_access512_SIZE; + } tcb_core_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_core_debug_t f; +} tcb_core_debug_u; + + +/* + * TCB_TAG0_DEBUG struct + */ + +#define TCB_TAG0_DEBUG_mem_read_cycle_SIZE 10 +#define TCB_TAG0_DEBUG_tag_access_cycle_SIZE 9 +#define TCB_TAG0_DEBUG_miss_stall_SIZE 1 +#define TCB_TAG0_DEBUG_num_feee_lines_SIZE 5 +#define TCB_TAG0_DEBUG_max_misses_SIZE 3 + +#define TCB_TAG0_DEBUG_mem_read_cycle_SHIFT 0 +#define TCB_TAG0_DEBUG_tag_access_cycle_SHIFT 12 +#define TCB_TAG0_DEBUG_miss_stall_SHIFT 23 +#define TCB_TAG0_DEBUG_num_feee_lines_SHIFT 24 +#define TCB_TAG0_DEBUG_max_misses_SHIFT 29 + +#define TCB_TAG0_DEBUG_mem_read_cycle_MASK 0x000003ff +#define TCB_TAG0_DEBUG_tag_access_cycle_MASK 0x001ff000 +#define TCB_TAG0_DEBUG_miss_stall_MASK 0x00800000 +#define TCB_TAG0_DEBUG_num_feee_lines_MASK 0x1f000000 +#define TCB_TAG0_DEBUG_max_misses_MASK 0xe0000000 + +#define TCB_TAG0_DEBUG_MASK \ + (TCB_TAG0_DEBUG_mem_read_cycle_MASK | \ + TCB_TAG0_DEBUG_tag_access_cycle_MASK | \ + TCB_TAG0_DEBUG_miss_stall_MASK | \ + TCB_TAG0_DEBUG_num_feee_lines_MASK | \ + TCB_TAG0_DEBUG_max_misses_MASK) + +#define TCB_TAG0_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \ + ((mem_read_cycle << TCB_TAG0_DEBUG_mem_read_cycle_SHIFT) | \ + (tag_access_cycle << TCB_TAG0_DEBUG_tag_access_cycle_SHIFT) | \ + (miss_stall << TCB_TAG0_DEBUG_miss_stall_SHIFT) | \ + (num_feee_lines << TCB_TAG0_DEBUG_num_feee_lines_SHIFT) | \ + (max_misses << TCB_TAG0_DEBUG_max_misses_SHIFT)) + +#define TCB_TAG0_DEBUG_GET_mem_read_cycle(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_mem_read_cycle_MASK) >> TCB_TAG0_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG0_DEBUG_GET_tag_access_cycle(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_tag_access_cycle_MASK) >> TCB_TAG0_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG0_DEBUG_GET_miss_stall(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_miss_stall_MASK) >> TCB_TAG0_DEBUG_miss_stall_SHIFT) +#define TCB_TAG0_DEBUG_GET_num_feee_lines(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_num_feee_lines_MASK) >> TCB_TAG0_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG0_DEBUG_GET_max_misses(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_max_misses_MASK) >> TCB_TAG0_DEBUG_max_misses_SHIFT) + +#define TCB_TAG0_DEBUG_SET_mem_read_cycle(tcb_tag0_debug_reg, mem_read_cycle) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG0_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG0_DEBUG_SET_tag_access_cycle(tcb_tag0_debug_reg, tag_access_cycle) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG0_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG0_DEBUG_SET_miss_stall(tcb_tag0_debug_reg, miss_stall) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG0_DEBUG_miss_stall_SHIFT) +#define TCB_TAG0_DEBUG_SET_num_feee_lines(tcb_tag0_debug_reg, num_feee_lines) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG0_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG0_DEBUG_SET_max_misses(tcb_tag0_debug_reg, max_misses) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG0_DEBUG_max_misses_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_tag0_debug_t { + unsigned int mem_read_cycle : TCB_TAG0_DEBUG_mem_read_cycle_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG0_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int miss_stall : TCB_TAG0_DEBUG_miss_stall_SIZE; + unsigned int num_feee_lines : TCB_TAG0_DEBUG_num_feee_lines_SIZE; + unsigned int max_misses : TCB_TAG0_DEBUG_max_misses_SIZE; + } tcb_tag0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_tag0_debug_t { + unsigned int max_misses : TCB_TAG0_DEBUG_max_misses_SIZE; + unsigned int num_feee_lines : TCB_TAG0_DEBUG_num_feee_lines_SIZE; + unsigned int miss_stall : TCB_TAG0_DEBUG_miss_stall_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG0_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int mem_read_cycle : TCB_TAG0_DEBUG_mem_read_cycle_SIZE; + } tcb_tag0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_tag0_debug_t f; +} tcb_tag0_debug_u; + + +/* + * TCB_TAG1_DEBUG struct + */ + +#define TCB_TAG1_DEBUG_mem_read_cycle_SIZE 10 +#define TCB_TAG1_DEBUG_tag_access_cycle_SIZE 9 +#define TCB_TAG1_DEBUG_miss_stall_SIZE 1 +#define TCB_TAG1_DEBUG_num_feee_lines_SIZE 5 +#define TCB_TAG1_DEBUG_max_misses_SIZE 3 + +#define TCB_TAG1_DEBUG_mem_read_cycle_SHIFT 0 +#define TCB_TAG1_DEBUG_tag_access_cycle_SHIFT 12 +#define TCB_TAG1_DEBUG_miss_stall_SHIFT 23 +#define TCB_TAG1_DEBUG_num_feee_lines_SHIFT 24 +#define TCB_TAG1_DEBUG_max_misses_SHIFT 29 + +#define TCB_TAG1_DEBUG_mem_read_cycle_MASK 0x000003ff +#define TCB_TAG1_DEBUG_tag_access_cycle_MASK 0x001ff000 +#define TCB_TAG1_DEBUG_miss_stall_MASK 0x00800000 +#define TCB_TAG1_DEBUG_num_feee_lines_MASK 0x1f000000 +#define TCB_TAG1_DEBUG_max_misses_MASK 0xe0000000 + +#define TCB_TAG1_DEBUG_MASK \ + (TCB_TAG1_DEBUG_mem_read_cycle_MASK | \ + TCB_TAG1_DEBUG_tag_access_cycle_MASK | \ + TCB_TAG1_DEBUG_miss_stall_MASK | \ + TCB_TAG1_DEBUG_num_feee_lines_MASK | \ + TCB_TAG1_DEBUG_max_misses_MASK) + +#define TCB_TAG1_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \ + ((mem_read_cycle << TCB_TAG1_DEBUG_mem_read_cycle_SHIFT) | \ + (tag_access_cycle << TCB_TAG1_DEBUG_tag_access_cycle_SHIFT) | \ + (miss_stall << TCB_TAG1_DEBUG_miss_stall_SHIFT) | \ + (num_feee_lines << TCB_TAG1_DEBUG_num_feee_lines_SHIFT) | \ + (max_misses << TCB_TAG1_DEBUG_max_misses_SHIFT)) + +#define TCB_TAG1_DEBUG_GET_mem_read_cycle(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_mem_read_cycle_MASK) >> TCB_TAG1_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG1_DEBUG_GET_tag_access_cycle(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_tag_access_cycle_MASK) >> TCB_TAG1_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG1_DEBUG_GET_miss_stall(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_miss_stall_MASK) >> TCB_TAG1_DEBUG_miss_stall_SHIFT) +#define TCB_TAG1_DEBUG_GET_num_feee_lines(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_num_feee_lines_MASK) >> TCB_TAG1_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG1_DEBUG_GET_max_misses(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_max_misses_MASK) >> TCB_TAG1_DEBUG_max_misses_SHIFT) + +#define TCB_TAG1_DEBUG_SET_mem_read_cycle(tcb_tag1_debug_reg, mem_read_cycle) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG1_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG1_DEBUG_SET_tag_access_cycle(tcb_tag1_debug_reg, tag_access_cycle) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG1_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG1_DEBUG_SET_miss_stall(tcb_tag1_debug_reg, miss_stall) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG1_DEBUG_miss_stall_SHIFT) +#define TCB_TAG1_DEBUG_SET_num_feee_lines(tcb_tag1_debug_reg, num_feee_lines) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG1_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG1_DEBUG_SET_max_misses(tcb_tag1_debug_reg, max_misses) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG1_DEBUG_max_misses_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_tag1_debug_t { + unsigned int mem_read_cycle : TCB_TAG1_DEBUG_mem_read_cycle_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG1_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int miss_stall : TCB_TAG1_DEBUG_miss_stall_SIZE; + unsigned int num_feee_lines : TCB_TAG1_DEBUG_num_feee_lines_SIZE; + unsigned int max_misses : TCB_TAG1_DEBUG_max_misses_SIZE; + } tcb_tag1_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_tag1_debug_t { + unsigned int max_misses : TCB_TAG1_DEBUG_max_misses_SIZE; + unsigned int num_feee_lines : TCB_TAG1_DEBUG_num_feee_lines_SIZE; + unsigned int miss_stall : TCB_TAG1_DEBUG_miss_stall_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG1_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int mem_read_cycle : TCB_TAG1_DEBUG_mem_read_cycle_SIZE; + } tcb_tag1_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_tag1_debug_t f; +} tcb_tag1_debug_u; + + +/* + * TCB_TAG2_DEBUG struct + */ + +#define TCB_TAG2_DEBUG_mem_read_cycle_SIZE 10 +#define TCB_TAG2_DEBUG_tag_access_cycle_SIZE 9 +#define TCB_TAG2_DEBUG_miss_stall_SIZE 1 +#define TCB_TAG2_DEBUG_num_feee_lines_SIZE 5 +#define TCB_TAG2_DEBUG_max_misses_SIZE 3 + +#define TCB_TAG2_DEBUG_mem_read_cycle_SHIFT 0 +#define TCB_TAG2_DEBUG_tag_access_cycle_SHIFT 12 +#define TCB_TAG2_DEBUG_miss_stall_SHIFT 23 +#define TCB_TAG2_DEBUG_num_feee_lines_SHIFT 24 +#define TCB_TAG2_DEBUG_max_misses_SHIFT 29 + +#define TCB_TAG2_DEBUG_mem_read_cycle_MASK 0x000003ff +#define TCB_TAG2_DEBUG_tag_access_cycle_MASK 0x001ff000 +#define TCB_TAG2_DEBUG_miss_stall_MASK 0x00800000 +#define TCB_TAG2_DEBUG_num_feee_lines_MASK 0x1f000000 +#define TCB_TAG2_DEBUG_max_misses_MASK 0xe0000000 + +#define TCB_TAG2_DEBUG_MASK \ + (TCB_TAG2_DEBUG_mem_read_cycle_MASK | \ + TCB_TAG2_DEBUG_tag_access_cycle_MASK | \ + TCB_TAG2_DEBUG_miss_stall_MASK | \ + TCB_TAG2_DEBUG_num_feee_lines_MASK | \ + TCB_TAG2_DEBUG_max_misses_MASK) + +#define TCB_TAG2_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \ + ((mem_read_cycle << TCB_TAG2_DEBUG_mem_read_cycle_SHIFT) | \ + (tag_access_cycle << TCB_TAG2_DEBUG_tag_access_cycle_SHIFT) | \ + (miss_stall << TCB_TAG2_DEBUG_miss_stall_SHIFT) | \ + (num_feee_lines << TCB_TAG2_DEBUG_num_feee_lines_SHIFT) | \ + (max_misses << TCB_TAG2_DEBUG_max_misses_SHIFT)) + +#define TCB_TAG2_DEBUG_GET_mem_read_cycle(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_mem_read_cycle_MASK) >> TCB_TAG2_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG2_DEBUG_GET_tag_access_cycle(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_tag_access_cycle_MASK) >> TCB_TAG2_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG2_DEBUG_GET_miss_stall(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_miss_stall_MASK) >> TCB_TAG2_DEBUG_miss_stall_SHIFT) +#define TCB_TAG2_DEBUG_GET_num_feee_lines(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_num_feee_lines_MASK) >> TCB_TAG2_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG2_DEBUG_GET_max_misses(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_max_misses_MASK) >> TCB_TAG2_DEBUG_max_misses_SHIFT) + +#define TCB_TAG2_DEBUG_SET_mem_read_cycle(tcb_tag2_debug_reg, mem_read_cycle) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG2_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG2_DEBUG_SET_tag_access_cycle(tcb_tag2_debug_reg, tag_access_cycle) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG2_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG2_DEBUG_SET_miss_stall(tcb_tag2_debug_reg, miss_stall) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG2_DEBUG_miss_stall_SHIFT) +#define TCB_TAG2_DEBUG_SET_num_feee_lines(tcb_tag2_debug_reg, num_feee_lines) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG2_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG2_DEBUG_SET_max_misses(tcb_tag2_debug_reg, max_misses) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG2_DEBUG_max_misses_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_tag2_debug_t { + unsigned int mem_read_cycle : TCB_TAG2_DEBUG_mem_read_cycle_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG2_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int miss_stall : TCB_TAG2_DEBUG_miss_stall_SIZE; + unsigned int num_feee_lines : TCB_TAG2_DEBUG_num_feee_lines_SIZE; + unsigned int max_misses : TCB_TAG2_DEBUG_max_misses_SIZE; + } tcb_tag2_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_tag2_debug_t { + unsigned int max_misses : TCB_TAG2_DEBUG_max_misses_SIZE; + unsigned int num_feee_lines : TCB_TAG2_DEBUG_num_feee_lines_SIZE; + unsigned int miss_stall : TCB_TAG2_DEBUG_miss_stall_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG2_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int mem_read_cycle : TCB_TAG2_DEBUG_mem_read_cycle_SIZE; + } tcb_tag2_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_tag2_debug_t f; +} tcb_tag2_debug_u; + + +/* + * TCB_TAG3_DEBUG struct + */ + +#define TCB_TAG3_DEBUG_mem_read_cycle_SIZE 10 +#define TCB_TAG3_DEBUG_tag_access_cycle_SIZE 9 +#define TCB_TAG3_DEBUG_miss_stall_SIZE 1 +#define TCB_TAG3_DEBUG_num_feee_lines_SIZE 5 +#define TCB_TAG3_DEBUG_max_misses_SIZE 3 + +#define TCB_TAG3_DEBUG_mem_read_cycle_SHIFT 0 +#define TCB_TAG3_DEBUG_tag_access_cycle_SHIFT 12 +#define TCB_TAG3_DEBUG_miss_stall_SHIFT 23 +#define TCB_TAG3_DEBUG_num_feee_lines_SHIFT 24 +#define TCB_TAG3_DEBUG_max_misses_SHIFT 29 + +#define TCB_TAG3_DEBUG_mem_read_cycle_MASK 0x000003ff +#define TCB_TAG3_DEBUG_tag_access_cycle_MASK 0x001ff000 +#define TCB_TAG3_DEBUG_miss_stall_MASK 0x00800000 +#define TCB_TAG3_DEBUG_num_feee_lines_MASK 0x1f000000 +#define TCB_TAG3_DEBUG_max_misses_MASK 0xe0000000 + +#define TCB_TAG3_DEBUG_MASK \ + (TCB_TAG3_DEBUG_mem_read_cycle_MASK | \ + TCB_TAG3_DEBUG_tag_access_cycle_MASK | \ + TCB_TAG3_DEBUG_miss_stall_MASK | \ + TCB_TAG3_DEBUG_num_feee_lines_MASK | \ + TCB_TAG3_DEBUG_max_misses_MASK) + +#define TCB_TAG3_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \ + ((mem_read_cycle << TCB_TAG3_DEBUG_mem_read_cycle_SHIFT) | \ + (tag_access_cycle << TCB_TAG3_DEBUG_tag_access_cycle_SHIFT) | \ + (miss_stall << TCB_TAG3_DEBUG_miss_stall_SHIFT) | \ + (num_feee_lines << TCB_TAG3_DEBUG_num_feee_lines_SHIFT) | \ + (max_misses << TCB_TAG3_DEBUG_max_misses_SHIFT)) + +#define TCB_TAG3_DEBUG_GET_mem_read_cycle(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_mem_read_cycle_MASK) >> TCB_TAG3_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG3_DEBUG_GET_tag_access_cycle(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_tag_access_cycle_MASK) >> TCB_TAG3_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG3_DEBUG_GET_miss_stall(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_miss_stall_MASK) >> TCB_TAG3_DEBUG_miss_stall_SHIFT) +#define TCB_TAG3_DEBUG_GET_num_feee_lines(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_num_feee_lines_MASK) >> TCB_TAG3_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG3_DEBUG_GET_max_misses(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_max_misses_MASK) >> TCB_TAG3_DEBUG_max_misses_SHIFT) + +#define TCB_TAG3_DEBUG_SET_mem_read_cycle(tcb_tag3_debug_reg, mem_read_cycle) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG3_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG3_DEBUG_SET_tag_access_cycle(tcb_tag3_debug_reg, tag_access_cycle) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG3_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG3_DEBUG_SET_miss_stall(tcb_tag3_debug_reg, miss_stall) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG3_DEBUG_miss_stall_SHIFT) +#define TCB_TAG3_DEBUG_SET_num_feee_lines(tcb_tag3_debug_reg, num_feee_lines) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG3_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG3_DEBUG_SET_max_misses(tcb_tag3_debug_reg, max_misses) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG3_DEBUG_max_misses_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_tag3_debug_t { + unsigned int mem_read_cycle : TCB_TAG3_DEBUG_mem_read_cycle_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG3_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int miss_stall : TCB_TAG3_DEBUG_miss_stall_SIZE; + unsigned int num_feee_lines : TCB_TAG3_DEBUG_num_feee_lines_SIZE; + unsigned int max_misses : TCB_TAG3_DEBUG_max_misses_SIZE; + } tcb_tag3_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_tag3_debug_t { + unsigned int max_misses : TCB_TAG3_DEBUG_max_misses_SIZE; + unsigned int num_feee_lines : TCB_TAG3_DEBUG_num_feee_lines_SIZE; + unsigned int miss_stall : TCB_TAG3_DEBUG_miss_stall_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG3_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int mem_read_cycle : TCB_TAG3_DEBUG_mem_read_cycle_SIZE; + } tcb_tag3_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_tag3_debug_t f; +} tcb_tag3_debug_u; + + +/* + * TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG struct + */ + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE 5 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE 16 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE 1 + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT 0 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT 2 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT 4 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT 5 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT 6 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT 7 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT 12 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT 28 + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK 0x00000001 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK 0x00000004 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK 0x00000010 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK 0x00000020 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK 0x00000040 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK 0x00000f80 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK 0x0ffff000 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK 0x10000000 + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_MASK \ + (TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG(left_done, fg0_sends_left, one_sector_to_go_left_q, no_sectors_to_go, update_left, sector_mask_left_count_q, sector_mask_left_q, valid_left_q) \ + ((left_done << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT) | \ + (fg0_sends_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT) | \ + (one_sector_to_go_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT) | \ + (no_sectors_to_go << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT) | \ + (update_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT) | \ + (sector_mask_left_count_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT) | \ + (sector_mask_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT) | \ + (valid_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT)) + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_left_done(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_fg0_sends_left(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_one_sector_to_go_left_q(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_no_sectors_to_go(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_update_left(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_sector_mask_left_count_q(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_sector_mask_left_q(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_valid_left_q(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT) + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_left_done(tcb_fetch_gen_sector_walker0_debug_reg, left_done) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK) | (left_done << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_fg0_sends_left(tcb_fetch_gen_sector_walker0_debug_reg, fg0_sends_left) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK) | (fg0_sends_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_one_sector_to_go_left_q(tcb_fetch_gen_sector_walker0_debug_reg, one_sector_to_go_left_q) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK) | (one_sector_to_go_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_no_sectors_to_go(tcb_fetch_gen_sector_walker0_debug_reg, no_sectors_to_go) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK) | (no_sectors_to_go << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_update_left(tcb_fetch_gen_sector_walker0_debug_reg, update_left) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK) | (update_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_sector_mask_left_count_q(tcb_fetch_gen_sector_walker0_debug_reg, sector_mask_left_count_q) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK) | (sector_mask_left_count_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_sector_mask_left_q(tcb_fetch_gen_sector_walker0_debug_reg, sector_mask_left_q) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK) | (sector_mask_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_valid_left_q(tcb_fetch_gen_sector_walker0_debug_reg, valid_left_q) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) | (valid_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_sector_walker0_debug_t { + unsigned int left_done : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE; + unsigned int : 1; + unsigned int fg0_sends_left : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE; + unsigned int : 1; + unsigned int one_sector_to_go_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE; + unsigned int no_sectors_to_go : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE; + unsigned int update_left : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE; + unsigned int sector_mask_left_count_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE; + unsigned int sector_mask_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE; + unsigned int valid_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE; + unsigned int : 3; + } tcb_fetch_gen_sector_walker0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_sector_walker0_debug_t { + unsigned int : 3; + unsigned int valid_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE; + unsigned int sector_mask_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE; + unsigned int sector_mask_left_count_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE; + unsigned int update_left : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE; + unsigned int no_sectors_to_go : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE; + unsigned int one_sector_to_go_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE; + unsigned int : 1; + unsigned int fg0_sends_left : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE; + unsigned int : 1; + unsigned int left_done : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE; + } tcb_fetch_gen_sector_walker0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_fetch_gen_sector_walker0_debug_t f; +} tcb_fetch_gen_sector_walker0_debug_u; + + +/* + * TCB_FETCH_GEN_WALKER_DEBUG struct + */ + +#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE 2 +#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE 2 +#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE 1 +#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE 3 +#define TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE 1 +#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE 4 + +#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT 4 +#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT 6 +#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT 11 +#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT 12 +#define TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT 15 +#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT 16 + +#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK 0x00000030 +#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK 0x000000c0 +#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK 0x00000800 +#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK 0x00007000 +#define TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK 0x00008000 +#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK 0x000f0000 + +#define TCB_FETCH_GEN_WALKER_DEBUG_MASK \ + (TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) + +#define TCB_FETCH_GEN_WALKER_DEBUG(quad_sel_left, set_sel_left, right_eq_left, ff_fg_type512, busy, setquads_to_send) \ + ((quad_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT) | \ + (set_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT) | \ + (right_eq_left << TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT) | \ + (ff_fg_type512 << TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT) | \ + (busy << TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT) | \ + (setquads_to_send << TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT)) + +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_quad_sel_left(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_set_sel_left(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_right_eq_left(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_ff_fg_type512(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_busy(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_setquads_to_send(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT) + +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_quad_sel_left(tcb_fetch_gen_walker_debug_reg, quad_sel_left) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK) | (quad_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_set_sel_left(tcb_fetch_gen_walker_debug_reg, set_sel_left) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK) | (set_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_right_eq_left(tcb_fetch_gen_walker_debug_reg, right_eq_left) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK) | (right_eq_left << TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_ff_fg_type512(tcb_fetch_gen_walker_debug_reg, ff_fg_type512) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK) | (ff_fg_type512 << TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_busy(tcb_fetch_gen_walker_debug_reg, busy) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK) | (busy << TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_setquads_to_send(tcb_fetch_gen_walker_debug_reg, setquads_to_send) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) | (setquads_to_send << TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_walker_debug_t { + unsigned int : 4; + unsigned int quad_sel_left : TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE; + unsigned int set_sel_left : TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE; + unsigned int : 3; + unsigned int right_eq_left : TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE; + unsigned int ff_fg_type512 : TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE; + unsigned int busy : TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE; + unsigned int setquads_to_send : TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE; + unsigned int : 12; + } tcb_fetch_gen_walker_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_walker_debug_t { + unsigned int : 12; + unsigned int setquads_to_send : TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE; + unsigned int busy : TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE; + unsigned int ff_fg_type512 : TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE; + unsigned int right_eq_left : TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE; + unsigned int : 3; + unsigned int set_sel_left : TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE; + unsigned int quad_sel_left : TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE; + unsigned int : 4; + } tcb_fetch_gen_walker_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_fetch_gen_walker_debug_t f; +} tcb_fetch_gen_walker_debug_u; + + +/* + * TCB_FETCH_GEN_PIPE0_DEBUG struct + */ + +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE 12 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE 5 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE 2 +#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE 2 +#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE 1 + +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT 0 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT 2 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT 4 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT 16 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT 21 +#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT 23 +#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT 24 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT 25 +#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT 26 +#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT 28 +#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT 30 + +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK 0x00000001 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK 0x00000004 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK 0x0000fff0 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK 0x001f0000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK 0x00600000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK 0x00800000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK 0x01000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK 0x02000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK 0x0c000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK 0x10000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK 0x40000000 + +#define TCB_FETCH_GEN_PIPE0_DEBUG_MASK \ + (TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) + +#define TCB_FETCH_GEN_PIPE0_DEBUG(tc0_arb_rts, ga_out_rts, tc_arb_format, tc_arb_fmsopcode, tc_arb_request_type, busy, fgo_busy, ga_busy, mc_sel_q, valid_q, arb_rtr) \ + ((tc0_arb_rts << TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT) | \ + (ga_out_rts << TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT) | \ + (tc_arb_format << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT) | \ + (tc_arb_fmsopcode << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT) | \ + (tc_arb_request_type << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT) | \ + (busy << TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT) | \ + (fgo_busy << TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT) | \ + (ga_busy << TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT) | \ + (mc_sel_q << TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT) | \ + (valid_q << TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT) | \ + (arb_rtr << TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT)) + +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc0_arb_rts(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_ga_out_rts(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_format(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_fmsopcode(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_request_type(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_busy(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_fgo_busy(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_ga_busy(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_mc_sel_q(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_valid_q(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_arb_RTR(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT) + +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc0_arb_rts(tcb_fetch_gen_pipe0_debug_reg, tc0_arb_rts) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK) | (tc0_arb_rts << TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_ga_out_rts(tcb_fetch_gen_pipe0_debug_reg, ga_out_rts) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK) | (ga_out_rts << TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_format(tcb_fetch_gen_pipe0_debug_reg, tc_arb_format) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK) | (tc_arb_format << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_fmsopcode(tcb_fetch_gen_pipe0_debug_reg, tc_arb_fmsopcode) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK) | (tc_arb_fmsopcode << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_request_type(tcb_fetch_gen_pipe0_debug_reg, tc_arb_request_type) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK) | (tc_arb_request_type << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_busy(tcb_fetch_gen_pipe0_debug_reg, busy) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK) | (busy << TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_fgo_busy(tcb_fetch_gen_pipe0_debug_reg, fgo_busy) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK) | (fgo_busy << TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_ga_busy(tcb_fetch_gen_pipe0_debug_reg, ga_busy) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK) | (ga_busy << TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_mc_sel_q(tcb_fetch_gen_pipe0_debug_reg, mc_sel_q) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK) | (mc_sel_q << TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_valid_q(tcb_fetch_gen_pipe0_debug_reg, valid_q) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK) | (valid_q << TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_arb_RTR(tcb_fetch_gen_pipe0_debug_reg, arb_rtr) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) | (arb_rtr << TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_pipe0_debug_t { + unsigned int tc0_arb_rts : TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE; + unsigned int : 1; + unsigned int ga_out_rts : TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE; + unsigned int : 1; + unsigned int tc_arb_format : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE; + unsigned int tc_arb_fmsopcode : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE; + unsigned int tc_arb_request_type : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE; + unsigned int busy : TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE; + unsigned int fgo_busy : TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE; + unsigned int ga_busy : TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE; + unsigned int mc_sel_q : TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE; + unsigned int valid_q : TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE; + unsigned int : 1; + unsigned int arb_rtr : TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE; + unsigned int : 1; + } tcb_fetch_gen_pipe0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_pipe0_debug_t { + unsigned int : 1; + unsigned int arb_rtr : TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE; + unsigned int : 1; + unsigned int valid_q : TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE; + unsigned int mc_sel_q : TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE; + unsigned int ga_busy : TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE; + unsigned int fgo_busy : TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE; + unsigned int busy : TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE; + unsigned int tc_arb_request_type : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE; + unsigned int tc_arb_fmsopcode : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE; + unsigned int tc_arb_format : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE; + unsigned int : 1; + unsigned int ga_out_rts : TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE; + unsigned int : 1; + unsigned int tc0_arb_rts : TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE; + } tcb_fetch_gen_pipe0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_fetch_gen_pipe0_debug_t f; +} tcb_fetch_gen_pipe0_debug_u; + + +/* + * TCD_INPUT0_DEBUG struct + */ + +#define TCD_INPUT0_DEBUG_empty_SIZE 1 +#define TCD_INPUT0_DEBUG_full_SIZE 1 +#define TCD_INPUT0_DEBUG_valid_q1_SIZE 1 +#define TCD_INPUT0_DEBUG_cnt_q1_SIZE 2 +#define TCD_INPUT0_DEBUG_last_send_q1_SIZE 1 +#define TCD_INPUT0_DEBUG_ip_send_SIZE 1 +#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE 1 +#define TCD_INPUT0_DEBUG_ipbuf_busy_SIZE 1 + +#define TCD_INPUT0_DEBUG_empty_SHIFT 16 +#define TCD_INPUT0_DEBUG_full_SHIFT 17 +#define TCD_INPUT0_DEBUG_valid_q1_SHIFT 20 +#define TCD_INPUT0_DEBUG_cnt_q1_SHIFT 21 +#define TCD_INPUT0_DEBUG_last_send_q1_SHIFT 23 +#define TCD_INPUT0_DEBUG_ip_send_SHIFT 24 +#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT 25 +#define TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT 26 + +#define TCD_INPUT0_DEBUG_empty_MASK 0x00010000 +#define TCD_INPUT0_DEBUG_full_MASK 0x00020000 +#define TCD_INPUT0_DEBUG_valid_q1_MASK 0x00100000 +#define TCD_INPUT0_DEBUG_cnt_q1_MASK 0x00600000 +#define TCD_INPUT0_DEBUG_last_send_q1_MASK 0x00800000 +#define TCD_INPUT0_DEBUG_ip_send_MASK 0x01000000 +#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK 0x02000000 +#define TCD_INPUT0_DEBUG_ipbuf_busy_MASK 0x04000000 + +#define TCD_INPUT0_DEBUG_MASK \ + (TCD_INPUT0_DEBUG_empty_MASK | \ + TCD_INPUT0_DEBUG_full_MASK | \ + TCD_INPUT0_DEBUG_valid_q1_MASK | \ + TCD_INPUT0_DEBUG_cnt_q1_MASK | \ + TCD_INPUT0_DEBUG_last_send_q1_MASK | \ + TCD_INPUT0_DEBUG_ip_send_MASK | \ + TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK | \ + TCD_INPUT0_DEBUG_ipbuf_busy_MASK) + +#define TCD_INPUT0_DEBUG(empty, full, valid_q1, cnt_q1, last_send_q1, ip_send, ipbuf_dxt_send, ipbuf_busy) \ + ((empty << TCD_INPUT0_DEBUG_empty_SHIFT) | \ + (full << TCD_INPUT0_DEBUG_full_SHIFT) | \ + (valid_q1 << TCD_INPUT0_DEBUG_valid_q1_SHIFT) | \ + (cnt_q1 << TCD_INPUT0_DEBUG_cnt_q1_SHIFT) | \ + (last_send_q1 << TCD_INPUT0_DEBUG_last_send_q1_SHIFT) | \ + (ip_send << TCD_INPUT0_DEBUG_ip_send_SHIFT) | \ + (ipbuf_dxt_send << TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT) | \ + (ipbuf_busy << TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT)) + +#define TCD_INPUT0_DEBUG_GET_empty(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_empty_MASK) >> TCD_INPUT0_DEBUG_empty_SHIFT) +#define TCD_INPUT0_DEBUG_GET_full(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_full_MASK) >> TCD_INPUT0_DEBUG_full_SHIFT) +#define TCD_INPUT0_DEBUG_GET_valid_q1(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_valid_q1_MASK) >> TCD_INPUT0_DEBUG_valid_q1_SHIFT) +#define TCD_INPUT0_DEBUG_GET_cnt_q1(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_cnt_q1_MASK) >> TCD_INPUT0_DEBUG_cnt_q1_SHIFT) +#define TCD_INPUT0_DEBUG_GET_last_send_q1(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_last_send_q1_MASK) >> TCD_INPUT0_DEBUG_last_send_q1_SHIFT) +#define TCD_INPUT0_DEBUG_GET_ip_send(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_ip_send_MASK) >> TCD_INPUT0_DEBUG_ip_send_SHIFT) +#define TCD_INPUT0_DEBUG_GET_ipbuf_dxt_send(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK) >> TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT) +#define TCD_INPUT0_DEBUG_GET_ipbuf_busy(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_ipbuf_busy_MASK) >> TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT) + +#define TCD_INPUT0_DEBUG_SET_empty(tcd_input0_debug_reg, empty) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_empty_MASK) | (empty << TCD_INPUT0_DEBUG_empty_SHIFT) +#define TCD_INPUT0_DEBUG_SET_full(tcd_input0_debug_reg, full) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_full_MASK) | (full << TCD_INPUT0_DEBUG_full_SHIFT) +#define TCD_INPUT0_DEBUG_SET_valid_q1(tcd_input0_debug_reg, valid_q1) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_valid_q1_MASK) | (valid_q1 << TCD_INPUT0_DEBUG_valid_q1_SHIFT) +#define TCD_INPUT0_DEBUG_SET_cnt_q1(tcd_input0_debug_reg, cnt_q1) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_cnt_q1_MASK) | (cnt_q1 << TCD_INPUT0_DEBUG_cnt_q1_SHIFT) +#define TCD_INPUT0_DEBUG_SET_last_send_q1(tcd_input0_debug_reg, last_send_q1) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_last_send_q1_MASK) | (last_send_q1 << TCD_INPUT0_DEBUG_last_send_q1_SHIFT) +#define TCD_INPUT0_DEBUG_SET_ip_send(tcd_input0_debug_reg, ip_send) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ip_send_MASK) | (ip_send << TCD_INPUT0_DEBUG_ip_send_SHIFT) +#define TCD_INPUT0_DEBUG_SET_ipbuf_dxt_send(tcd_input0_debug_reg, ipbuf_dxt_send) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK) | (ipbuf_dxt_send << TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT) +#define TCD_INPUT0_DEBUG_SET_ipbuf_busy(tcd_input0_debug_reg, ipbuf_busy) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ipbuf_busy_MASK) | (ipbuf_busy << TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_input0_debug_t { + unsigned int : 16; + unsigned int empty : TCD_INPUT0_DEBUG_empty_SIZE; + unsigned int full : TCD_INPUT0_DEBUG_full_SIZE; + unsigned int : 2; + unsigned int valid_q1 : TCD_INPUT0_DEBUG_valid_q1_SIZE; + unsigned int cnt_q1 : TCD_INPUT0_DEBUG_cnt_q1_SIZE; + unsigned int last_send_q1 : TCD_INPUT0_DEBUG_last_send_q1_SIZE; + unsigned int ip_send : TCD_INPUT0_DEBUG_ip_send_SIZE; + unsigned int ipbuf_dxt_send : TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE; + unsigned int ipbuf_busy : TCD_INPUT0_DEBUG_ipbuf_busy_SIZE; + unsigned int : 5; + } tcd_input0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_input0_debug_t { + unsigned int : 5; + unsigned int ipbuf_busy : TCD_INPUT0_DEBUG_ipbuf_busy_SIZE; + unsigned int ipbuf_dxt_send : TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE; + unsigned int ip_send : TCD_INPUT0_DEBUG_ip_send_SIZE; + unsigned int last_send_q1 : TCD_INPUT0_DEBUG_last_send_q1_SIZE; + unsigned int cnt_q1 : TCD_INPUT0_DEBUG_cnt_q1_SIZE; + unsigned int valid_q1 : TCD_INPUT0_DEBUG_valid_q1_SIZE; + unsigned int : 2; + unsigned int full : TCD_INPUT0_DEBUG_full_SIZE; + unsigned int empty : TCD_INPUT0_DEBUG_empty_SIZE; + unsigned int : 16; + } tcd_input0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_input0_debug_t f; +} tcd_input0_debug_u; + + +/* + * TCD_DEGAMMA_DEBUG struct + */ + +#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE 2 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE 1 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE 1 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE 1 +#define TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE 1 +#define TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE 1 + +#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT 0 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT 2 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT 3 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT 4 +#define TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT 5 +#define TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT 6 + +#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK 0x00000003 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK 0x00000004 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK 0x00000008 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK 0x00000010 +#define TCD_DEGAMMA_DEBUG_dgmm_stall_MASK 0x00000020 +#define TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK 0x00000040 + +#define TCD_DEGAMMA_DEBUG_MASK \ + (TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_stall_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) + +#define TCD_DEGAMMA_DEBUG(dgmm_ftfconv_dgmmen, dgmm_ctrl_dgmm8, dgmm_ctrl_last_send, dgmm_ctrl_send, dgmm_stall, dgmm_pstate) \ + ((dgmm_ftfconv_dgmmen << TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT) | \ + (dgmm_ctrl_dgmm8 << TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT) | \ + (dgmm_ctrl_last_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT) | \ + (dgmm_ctrl_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT) | \ + (dgmm_stall << TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT) | \ + (dgmm_pstate << TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT)) + +#define TCD_DEGAMMA_DEBUG_GET_dgmm_ftfconv_dgmmen(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_dgmm8(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_last_send(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_send(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_stall(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_stall_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_pstate(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT) + +#define TCD_DEGAMMA_DEBUG_SET_dgmm_ftfconv_dgmmen(tcd_degamma_debug_reg, dgmm_ftfconv_dgmmen) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK) | (dgmm_ftfconv_dgmmen << TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_dgmm8(tcd_degamma_debug_reg, dgmm_ctrl_dgmm8) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK) | (dgmm_ctrl_dgmm8 << TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_last_send(tcd_degamma_debug_reg, dgmm_ctrl_last_send) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK) | (dgmm_ctrl_last_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_send(tcd_degamma_debug_reg, dgmm_ctrl_send) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK) | (dgmm_ctrl_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_stall(tcd_degamma_debug_reg, dgmm_stall) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_stall_MASK) | (dgmm_stall << TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_pstate(tcd_degamma_debug_reg, dgmm_pstate) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) | (dgmm_pstate << TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_degamma_debug_t { + unsigned int dgmm_ftfconv_dgmmen : TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE; + unsigned int dgmm_ctrl_dgmm8 : TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE; + unsigned int dgmm_ctrl_last_send : TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE; + unsigned int dgmm_ctrl_send : TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE; + unsigned int dgmm_stall : TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE; + unsigned int dgmm_pstate : TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE; + unsigned int : 25; + } tcd_degamma_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_degamma_debug_t { + unsigned int : 25; + unsigned int dgmm_pstate : TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE; + unsigned int dgmm_stall : TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE; + unsigned int dgmm_ctrl_send : TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE; + unsigned int dgmm_ctrl_last_send : TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE; + unsigned int dgmm_ctrl_dgmm8 : TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE; + unsigned int dgmm_ftfconv_dgmmen : TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE; + } tcd_degamma_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_degamma_debug_t f; +} tcd_degamma_debug_u; + + +/* + * TCD_DXTMUX_SCTARB_DEBUG struct + */ + +#define TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE 1 + +#define TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT 9 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT 10 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT 11 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT 15 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT 16 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT 20 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT 27 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT 28 +#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT 29 + +#define TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK 0x00000200 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK 0x00000400 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK 0x00000800 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK 0x00008000 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK 0x00010000 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK 0x00100000 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK 0x08000000 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK 0x10000000 +#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK 0x20000000 + +#define TCD_DXTMUX_SCTARB_DEBUG_MASK \ + (TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) + +#define TCD_DXTMUX_SCTARB_DEBUG(pstate, sctrmx_rtr, dxtc_rtr, sctrarb_multcyl_send, sctrmx0_sctrarb_rts, dxtc_sctrarb_send, dxtc_dgmmpd_last_send, dxtc_dgmmpd_send, dcmp_mux_send) \ + ((pstate << TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT) | \ + (sctrmx_rtr << TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT) | \ + (dxtc_rtr << TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT) | \ + (sctrarb_multcyl_send << TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT) | \ + (sctrmx0_sctrarb_rts << TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT) | \ + (dxtc_sctrarb_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT) | \ + (dxtc_dgmmpd_last_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT) | \ + (dxtc_dgmmpd_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT) | \ + (dcmp_mux_send << TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT)) + +#define TCD_DXTMUX_SCTARB_DEBUG_GET_pstate(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrmx_rtr(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_rtr(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrarb_multcyl_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrmx0_sctrarb_rts(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_sctrarb_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_dgmmpd_last_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_dgmmpd_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dcmp_mux_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT) + +#define TCD_DXTMUX_SCTARB_DEBUG_SET_pstate(tcd_dxtmux_sctarb_debug_reg, pstate) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK) | (pstate << TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrmx_rtr(tcd_dxtmux_sctarb_debug_reg, sctrmx_rtr) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK) | (sctrmx_rtr << TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_rtr(tcd_dxtmux_sctarb_debug_reg, dxtc_rtr) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK) | (dxtc_rtr << TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrarb_multcyl_send(tcd_dxtmux_sctarb_debug_reg, sctrarb_multcyl_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK) | (sctrarb_multcyl_send << TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrmx0_sctrarb_rts(tcd_dxtmux_sctarb_debug_reg, sctrmx0_sctrarb_rts) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK) | (sctrmx0_sctrarb_rts << TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_sctrarb_send(tcd_dxtmux_sctarb_debug_reg, dxtc_sctrarb_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK) | (dxtc_sctrarb_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_dgmmpd_last_send(tcd_dxtmux_sctarb_debug_reg, dxtc_dgmmpd_last_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK) | (dxtc_dgmmpd_last_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_dgmmpd_send(tcd_dxtmux_sctarb_debug_reg, dxtc_dgmmpd_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK) | (dxtc_dgmmpd_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dcmp_mux_send(tcd_dxtmux_sctarb_debug_reg, dcmp_mux_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) | (dcmp_mux_send << TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_dxtmux_sctarb_debug_t { + unsigned int : 9; + unsigned int pstate : TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE; + unsigned int sctrmx_rtr : TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE; + unsigned int dxtc_rtr : TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE; + unsigned int : 3; + unsigned int sctrarb_multcyl_send : TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE; + unsigned int sctrmx0_sctrarb_rts : TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE; + unsigned int : 3; + unsigned int dxtc_sctrarb_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE; + unsigned int : 6; + unsigned int dxtc_dgmmpd_last_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE; + unsigned int dxtc_dgmmpd_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE; + unsigned int dcmp_mux_send : TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE; + unsigned int : 2; + } tcd_dxtmux_sctarb_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_dxtmux_sctarb_debug_t { + unsigned int : 2; + unsigned int dcmp_mux_send : TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE; + unsigned int dxtc_dgmmpd_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE; + unsigned int dxtc_dgmmpd_last_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE; + unsigned int : 6; + unsigned int dxtc_sctrarb_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE; + unsigned int : 3; + unsigned int sctrmx0_sctrarb_rts : TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE; + unsigned int sctrarb_multcyl_send : TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE; + unsigned int : 3; + unsigned int dxtc_rtr : TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE; + unsigned int sctrmx_rtr : TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE; + unsigned int pstate : TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE; + unsigned int : 9; + } tcd_dxtmux_sctarb_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_dxtmux_sctarb_debug_t f; +} tcd_dxtmux_sctarb_debug_u; + + +/* + * TCD_DXTC_ARB_DEBUG struct + */ + +#define TCD_DXTC_ARB_DEBUG_n0_stall_SIZE 1 +#define TCD_DXTC_ARB_DEBUG_pstate_SIZE 1 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE 1 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE 2 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE 3 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE 6 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE 12 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE 1 +#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE 1 + +#define TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT 4 +#define TCD_DXTC_ARB_DEBUG_pstate_SHIFT 5 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT 6 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT 7 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT 9 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT 12 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT 18 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT 30 +#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT 31 + +#define TCD_DXTC_ARB_DEBUG_n0_stall_MASK 0x00000010 +#define TCD_DXTC_ARB_DEBUG_pstate_MASK 0x00000020 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK 0x00000040 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK 0x00000180 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK 0x00000e00 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK 0x0003f000 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK 0x3ffc0000 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK 0x40000000 +#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK 0x80000000 + +#define TCD_DXTC_ARB_DEBUG_MASK \ + (TCD_DXTC_ARB_DEBUG_n0_stall_MASK | \ + TCD_DXTC_ARB_DEBUG_pstate_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK | \ + TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) + +#define TCD_DXTC_ARB_DEBUG(n0_stall, pstate, arb_dcmp01_last_send, arb_dcmp01_cnt, arb_dcmp01_sector, arb_dcmp01_cacheline, arb_dcmp01_format, arb_dcmp01_send, n0_dxt2_4_types) \ + ((n0_stall << TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT) | \ + (pstate << TCD_DXTC_ARB_DEBUG_pstate_SHIFT) | \ + (arb_dcmp01_last_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT) | \ + (arb_dcmp01_cnt << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT) | \ + (arb_dcmp01_sector << TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT) | \ + (arb_dcmp01_cacheline << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT) | \ + (arb_dcmp01_format << TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT) | \ + (arb_dcmp01_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT) | \ + (n0_dxt2_4_types << TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT)) + +#define TCD_DXTC_ARB_DEBUG_GET_n0_stall(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_n0_stall_MASK) >> TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_pstate(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_pstate_MASK) >> TCD_DXTC_ARB_DEBUG_pstate_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_last_send(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_cnt(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_sector(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_cacheline(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_format(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_send(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_n0_dxt2_4_types(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) >> TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT) + +#define TCD_DXTC_ARB_DEBUG_SET_n0_stall(tcd_dxtc_arb_debug_reg, n0_stall) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_n0_stall_MASK) | (n0_stall << TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_pstate(tcd_dxtc_arb_debug_reg, pstate) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_pstate_MASK) | (pstate << TCD_DXTC_ARB_DEBUG_pstate_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_last_send(tcd_dxtc_arb_debug_reg, arb_dcmp01_last_send) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK) | (arb_dcmp01_last_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_cnt(tcd_dxtc_arb_debug_reg, arb_dcmp01_cnt) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK) | (arb_dcmp01_cnt << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_sector(tcd_dxtc_arb_debug_reg, arb_dcmp01_sector) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK) | (arb_dcmp01_sector << TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_cacheline(tcd_dxtc_arb_debug_reg, arb_dcmp01_cacheline) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK) | (arb_dcmp01_cacheline << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_format(tcd_dxtc_arb_debug_reg, arb_dcmp01_format) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK) | (arb_dcmp01_format << TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_send(tcd_dxtc_arb_debug_reg, arb_dcmp01_send) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK) | (arb_dcmp01_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_n0_dxt2_4_types(tcd_dxtc_arb_debug_reg, n0_dxt2_4_types) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) | (n0_dxt2_4_types << TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_dxtc_arb_debug_t { + unsigned int : 4; + unsigned int n0_stall : TCD_DXTC_ARB_DEBUG_n0_stall_SIZE; + unsigned int pstate : TCD_DXTC_ARB_DEBUG_pstate_SIZE; + unsigned int arb_dcmp01_last_send : TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE; + unsigned int arb_dcmp01_cnt : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE; + unsigned int arb_dcmp01_sector : TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE; + unsigned int arb_dcmp01_cacheline : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE; + unsigned int arb_dcmp01_format : TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE; + unsigned int arb_dcmp01_send : TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE; + unsigned int n0_dxt2_4_types : TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE; + } tcd_dxtc_arb_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_dxtc_arb_debug_t { + unsigned int n0_dxt2_4_types : TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE; + unsigned int arb_dcmp01_send : TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE; + unsigned int arb_dcmp01_format : TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE; + unsigned int arb_dcmp01_cacheline : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE; + unsigned int arb_dcmp01_sector : TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE; + unsigned int arb_dcmp01_cnt : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE; + unsigned int arb_dcmp01_last_send : TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE; + unsigned int pstate : TCD_DXTC_ARB_DEBUG_pstate_SIZE; + unsigned int n0_stall : TCD_DXTC_ARB_DEBUG_n0_stall_SIZE; + unsigned int : 4; + } tcd_dxtc_arb_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_dxtc_arb_debug_t f; +} tcd_dxtc_arb_debug_u; + + +/* + * TCD_STALLS_DEBUG struct + */ + +#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_incoming_rtr_SIZE 1 + +#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT 10 +#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT 11 +#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT 17 +#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT 18 +#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT 19 +#define TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT 31 + +#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK 0x00000400 +#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK 0x00000800 +#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK 0x00020000 +#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK 0x00040000 +#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK 0x00080000 +#define TCD_STALLS_DEBUG_not_incoming_rtr_MASK 0x80000000 + +#define TCD_STALLS_DEBUG_MASK \ + (TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK | \ + TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK | \ + TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK | \ + TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK | \ + TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK | \ + TCD_STALLS_DEBUG_not_incoming_rtr_MASK) + +#define TCD_STALLS_DEBUG(not_multcyl_sctrarb_rtr, not_sctrmx0_sctrarb_rtr, not_dcmp0_arb_rtr, not_dgmmpd_dxtc_rtr, not_mux_dcmp_rtr, not_incoming_rtr) \ + ((not_multcyl_sctrarb_rtr << TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT) | \ + (not_sctrmx0_sctrarb_rtr << TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT) | \ + (not_dcmp0_arb_rtr << TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT) | \ + (not_dgmmpd_dxtc_rtr << TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT) | \ + (not_mux_dcmp_rtr << TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT) | \ + (not_incoming_rtr << TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT)) + +#define TCD_STALLS_DEBUG_GET_not_multcyl_sctrarb_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK) >> TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_sctrmx0_sctrarb_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK) >> TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_dcmp0_arb_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK) >> TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_dgmmpd_dxtc_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK) >> TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_mux_dcmp_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK) >> TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_incoming_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_incoming_rtr_MASK) >> TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT) + +#define TCD_STALLS_DEBUG_SET_not_multcyl_sctrarb_rtr(tcd_stalls_debug_reg, not_multcyl_sctrarb_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK) | (not_multcyl_sctrarb_rtr << TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_sctrmx0_sctrarb_rtr(tcd_stalls_debug_reg, not_sctrmx0_sctrarb_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK) | (not_sctrmx0_sctrarb_rtr << TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_dcmp0_arb_rtr(tcd_stalls_debug_reg, not_dcmp0_arb_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK) | (not_dcmp0_arb_rtr << TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_dgmmpd_dxtc_rtr(tcd_stalls_debug_reg, not_dgmmpd_dxtc_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK) | (not_dgmmpd_dxtc_rtr << TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_mux_dcmp_rtr(tcd_stalls_debug_reg, not_mux_dcmp_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK) | (not_mux_dcmp_rtr << TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_incoming_rtr(tcd_stalls_debug_reg, not_incoming_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_incoming_rtr_MASK) | (not_incoming_rtr << TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_stalls_debug_t { + unsigned int : 10; + unsigned int not_multcyl_sctrarb_rtr : TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE; + unsigned int not_sctrmx0_sctrarb_rtr : TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE; + unsigned int : 5; + unsigned int not_dcmp0_arb_rtr : TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE; + unsigned int not_dgmmpd_dxtc_rtr : TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE; + unsigned int not_mux_dcmp_rtr : TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE; + unsigned int : 11; + unsigned int not_incoming_rtr : TCD_STALLS_DEBUG_not_incoming_rtr_SIZE; + } tcd_stalls_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_stalls_debug_t { + unsigned int not_incoming_rtr : TCD_STALLS_DEBUG_not_incoming_rtr_SIZE; + unsigned int : 11; + unsigned int not_mux_dcmp_rtr : TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE; + unsigned int not_dgmmpd_dxtc_rtr : TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE; + unsigned int not_dcmp0_arb_rtr : TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE; + unsigned int : 5; + unsigned int not_sctrmx0_sctrarb_rtr : TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE; + unsigned int not_multcyl_sctrarb_rtr : TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE; + unsigned int : 10; + } tcd_stalls_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_stalls_debug_t f; +} tcd_stalls_debug_u; + + +/* + * TCO_STALLS_DEBUG struct + */ + +#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE 1 +#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE 1 +#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE 1 + +#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT 5 +#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT 6 +#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT 7 + +#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK 0x00000020 +#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK 0x00000040 +#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK 0x00000080 + +#define TCO_STALLS_DEBUG_MASK \ + (TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK | \ + TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK | \ + TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) + +#define TCO_STALLS_DEBUG(quad0_sg_crd_rtr, quad0_rl_sg_rtr, quad0_tco_tcb_rtr_d) \ + ((quad0_sg_crd_rtr << TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT) | \ + (quad0_rl_sg_rtr << TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT) | \ + (quad0_tco_tcb_rtr_d << TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT)) + +#define TCO_STALLS_DEBUG_GET_quad0_sg_crd_RTR(tco_stalls_debug) \ + ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK) >> TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT) +#define TCO_STALLS_DEBUG_GET_quad0_rl_sg_RTR(tco_stalls_debug) \ + ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK) >> TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT) +#define TCO_STALLS_DEBUG_GET_quad0_TCO_TCB_rtr_d(tco_stalls_debug) \ + ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) >> TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT) + +#define TCO_STALLS_DEBUG_SET_quad0_sg_crd_RTR(tco_stalls_debug_reg, quad0_sg_crd_rtr) \ + tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK) | (quad0_sg_crd_rtr << TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT) +#define TCO_STALLS_DEBUG_SET_quad0_rl_sg_RTR(tco_stalls_debug_reg, quad0_rl_sg_rtr) \ + tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK) | (quad0_rl_sg_rtr << TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT) +#define TCO_STALLS_DEBUG_SET_quad0_TCO_TCB_rtr_d(tco_stalls_debug_reg, quad0_tco_tcb_rtr_d) \ + tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) | (quad0_tco_tcb_rtr_d << TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tco_stalls_debug_t { + unsigned int : 5; + unsigned int quad0_sg_crd_rtr : TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE; + unsigned int quad0_rl_sg_rtr : TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE; + unsigned int quad0_tco_tcb_rtr_d : TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE; + unsigned int : 24; + } tco_stalls_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tco_stalls_debug_t { + unsigned int : 24; + unsigned int quad0_tco_tcb_rtr_d : TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE; + unsigned int quad0_rl_sg_rtr : TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE; + unsigned int quad0_sg_crd_rtr : TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE; + unsigned int : 5; + } tco_stalls_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tco_stalls_debug_t f; +} tco_stalls_debug_u; + + +/* + * TCO_QUAD0_DEBUG0 struct + */ + +#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE 8 +#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE 1 +#define TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE 1 +#define TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE 1 +#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE 1 +#define TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE 1 +#define TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE 1 +#define TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE 1 +#define TCO_QUAD0_DEBUG0_read_cache_q_SIZE 1 +#define TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE 1 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE 1 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE 1 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE 1 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE 1 +#define TCO_QUAD0_DEBUG0_busy_SIZE 1 + +#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT 0 +#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT 8 +#define TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT 9 +#define TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT 10 +#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT 11 +#define TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT 12 +#define TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT 13 +#define TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT 16 +#define TCO_QUAD0_DEBUG0_read_cache_q_SHIFT 24 +#define TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT 25 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT 26 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT 27 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT 28 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT 29 +#define TCO_QUAD0_DEBUG0_busy_SHIFT 30 + +#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK 0x000000ff +#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK 0x00000100 +#define TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK 0x00000200 +#define TCO_QUAD0_DEBUG0_rl_sg_rts_MASK 0x00000400 +#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK 0x00000800 +#define TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK 0x00001000 +#define TCO_QUAD0_DEBUG0_sg_crd_rts_MASK 0x00002000 +#define TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK 0x00010000 +#define TCO_QUAD0_DEBUG0_read_cache_q_MASK 0x01000000 +#define TCO_QUAD0_DEBUG0_cache_read_RTR_MASK 0x02000000 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK 0x04000000 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK 0x08000000 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK 0x10000000 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK 0x20000000 +#define TCO_QUAD0_DEBUG0_busy_MASK 0x40000000 + +#define TCO_QUAD0_DEBUG0_MASK \ + (TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK | \ + TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK | \ + TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK | \ + TCO_QUAD0_DEBUG0_rl_sg_rts_MASK | \ + TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK | \ + TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK | \ + TCO_QUAD0_DEBUG0_sg_crd_rts_MASK | \ + TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK | \ + TCO_QUAD0_DEBUG0_read_cache_q_MASK | \ + TCO_QUAD0_DEBUG0_cache_read_RTR_MASK | \ + TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK | \ + TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK | \ + TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK | \ + TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK | \ + TCO_QUAD0_DEBUG0_busy_MASK) + +#define TCO_QUAD0_DEBUG0(rl_sg_sector_format, rl_sg_end_of_sample, rl_sg_rtr, rl_sg_rts, sg_crd_end_of_sample, sg_crd_rtr, sg_crd_rts, stagen1_valid_q, read_cache_q, cache_read_rtr, all_sectors_written_set3, all_sectors_written_set2, all_sectors_written_set1, all_sectors_written_set0, busy) \ + ((rl_sg_sector_format << TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT) | \ + (rl_sg_end_of_sample << TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT) | \ + (rl_sg_rtr << TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT) | \ + (rl_sg_rts << TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT) | \ + (sg_crd_end_of_sample << TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT) | \ + (sg_crd_rtr << TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT) | \ + (sg_crd_rts << TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT) | \ + (stagen1_valid_q << TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT) | \ + (read_cache_q << TCO_QUAD0_DEBUG0_read_cache_q_SHIFT) | \ + (cache_read_rtr << TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT) | \ + (all_sectors_written_set3 << TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT) | \ + (all_sectors_written_set2 << TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT) | \ + (all_sectors_written_set1 << TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT) | \ + (all_sectors_written_set0 << TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT) | \ + (busy << TCO_QUAD0_DEBUG0_busy_SHIFT)) + +#define TCO_QUAD0_DEBUG0_GET_rl_sg_sector_format(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_rl_sg_end_of_sample(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_rl_sg_rtr(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_rl_sg_rts(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_rts_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_sg_crd_end_of_sample(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_sg_crd_rtr(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_sg_crd_rts(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_rts_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_stageN1_valid_q(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK) >> TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_read_cache_q(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_read_cache_q_MASK) >> TCO_QUAD0_DEBUG0_read_cache_q_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_cache_read_RTR(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_cache_read_RTR_MASK) >> TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set3(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set2(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set1(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set0(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_busy(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_busy_MASK) >> TCO_QUAD0_DEBUG0_busy_SHIFT) + +#define TCO_QUAD0_DEBUG0_SET_rl_sg_sector_format(tco_quad0_debug0_reg, rl_sg_sector_format) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK) | (rl_sg_sector_format << TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_rl_sg_end_of_sample(tco_quad0_debug0_reg, rl_sg_end_of_sample) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK) | (rl_sg_end_of_sample << TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_rl_sg_rtr(tco_quad0_debug0_reg, rl_sg_rtr) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK) | (rl_sg_rtr << TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_rl_sg_rts(tco_quad0_debug0_reg, rl_sg_rts) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_rts_MASK) | (rl_sg_rts << TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_sg_crd_end_of_sample(tco_quad0_debug0_reg, sg_crd_end_of_sample) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK) | (sg_crd_end_of_sample << TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_sg_crd_rtr(tco_quad0_debug0_reg, sg_crd_rtr) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK) | (sg_crd_rtr << TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_sg_crd_rts(tco_quad0_debug0_reg, sg_crd_rts) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_rts_MASK) | (sg_crd_rts << TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_stageN1_valid_q(tco_quad0_debug0_reg, stagen1_valid_q) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK) | (stagen1_valid_q << TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_read_cache_q(tco_quad0_debug0_reg, read_cache_q) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_read_cache_q_MASK) | (read_cache_q << TCO_QUAD0_DEBUG0_read_cache_q_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_cache_read_RTR(tco_quad0_debug0_reg, cache_read_rtr) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_cache_read_RTR_MASK) | (cache_read_rtr << TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set3(tco_quad0_debug0_reg, all_sectors_written_set3) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK) | (all_sectors_written_set3 << TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set2(tco_quad0_debug0_reg, all_sectors_written_set2) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK) | (all_sectors_written_set2 << TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set1(tco_quad0_debug0_reg, all_sectors_written_set1) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK) | (all_sectors_written_set1 << TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set0(tco_quad0_debug0_reg, all_sectors_written_set0) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK) | (all_sectors_written_set0 << TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_busy(tco_quad0_debug0_reg, busy) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_busy_MASK) | (busy << TCO_QUAD0_DEBUG0_busy_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tco_quad0_debug0_t { + unsigned int rl_sg_sector_format : TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE; + unsigned int rl_sg_end_of_sample : TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE; + unsigned int rl_sg_rtr : TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE; + unsigned int rl_sg_rts : TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE; + unsigned int sg_crd_end_of_sample : TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE; + unsigned int sg_crd_rtr : TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE; + unsigned int sg_crd_rts : TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE; + unsigned int : 2; + unsigned int stagen1_valid_q : TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE; + unsigned int : 7; + unsigned int read_cache_q : TCO_QUAD0_DEBUG0_read_cache_q_SIZE; + unsigned int cache_read_rtr : TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE; + unsigned int all_sectors_written_set3 : TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE; + unsigned int all_sectors_written_set2 : TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE; + unsigned int all_sectors_written_set1 : TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE; + unsigned int all_sectors_written_set0 : TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE; + unsigned int busy : TCO_QUAD0_DEBUG0_busy_SIZE; + unsigned int : 1; + } tco_quad0_debug0_t; + +#else // !BIGENDIAN_OS + + typedef struct _tco_quad0_debug0_t { + unsigned int : 1; + unsigned int busy : TCO_QUAD0_DEBUG0_busy_SIZE; + unsigned int all_sectors_written_set0 : TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE; + unsigned int all_sectors_written_set1 : TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE; + unsigned int all_sectors_written_set2 : TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE; + unsigned int all_sectors_written_set3 : TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE; + unsigned int cache_read_rtr : TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE; + unsigned int read_cache_q : TCO_QUAD0_DEBUG0_read_cache_q_SIZE; + unsigned int : 7; + unsigned int stagen1_valid_q : TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE; + unsigned int : 2; + unsigned int sg_crd_rts : TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE; + unsigned int sg_crd_rtr : TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE; + unsigned int sg_crd_end_of_sample : TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE; + unsigned int rl_sg_rts : TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE; + unsigned int rl_sg_rtr : TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE; + unsigned int rl_sg_end_of_sample : TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE; + unsigned int rl_sg_sector_format : TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE; + } tco_quad0_debug0_t; + +#endif + +typedef union { + unsigned int val : 32; + tco_quad0_debug0_t f; +} tco_quad0_debug0_u; + + +/* + * TCO_QUAD0_DEBUG1 struct + */ + +#define TCO_QUAD0_DEBUG1_fifo_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_empty_SIZE 1 +#define TCO_QUAD0_DEBUG1_full_SIZE 1 +#define TCO_QUAD0_DEBUG1_write_enable_SIZE 1 +#define TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE 7 +#define TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE 7 +#define TCO_QUAD0_DEBUG1_cache_read_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_input_quad_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE 1 +#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE 1 +#define TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE 1 +#define TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE 1 +#define TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE 1 +#define TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE 1 +#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE 1 + +#define TCO_QUAD0_DEBUG1_fifo_busy_SHIFT 0 +#define TCO_QUAD0_DEBUG1_empty_SHIFT 1 +#define TCO_QUAD0_DEBUG1_full_SHIFT 2 +#define TCO_QUAD0_DEBUG1_write_enable_SHIFT 3 +#define TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT 4 +#define TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT 11 +#define TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT 20 +#define TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT 21 +#define TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT 22 +#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT 23 +#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT 24 +#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT 25 +#define TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT 26 +#define TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT 27 +#define TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT 28 +#define TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT 29 +#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT 30 + +#define TCO_QUAD0_DEBUG1_fifo_busy_MASK 0x00000001 +#define TCO_QUAD0_DEBUG1_empty_MASK 0x00000002 +#define TCO_QUAD0_DEBUG1_full_MASK 0x00000004 +#define TCO_QUAD0_DEBUG1_write_enable_MASK 0x00000008 +#define TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK 0x000007f0 +#define TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK 0x0003f800 +#define TCO_QUAD0_DEBUG1_cache_read_busy_MASK 0x00100000 +#define TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK 0x00200000 +#define TCO_QUAD0_DEBUG1_input_quad_busy_MASK 0x00400000 +#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK 0x00800000 +#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK 0x01000000 +#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK 0x02000000 +#define TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK 0x04000000 +#define TCO_QUAD0_DEBUG1_rl_sg_rts_MASK 0x08000000 +#define TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK 0x10000000 +#define TCO_QUAD0_DEBUG1_sg_crd_rts_MASK 0x20000000 +#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK 0x40000000 + +#define TCO_QUAD0_DEBUG1_MASK \ + (TCO_QUAD0_DEBUG1_fifo_busy_MASK | \ + TCO_QUAD0_DEBUG1_empty_MASK | \ + TCO_QUAD0_DEBUG1_full_MASK | \ + TCO_QUAD0_DEBUG1_write_enable_MASK | \ + TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK | \ + TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK | \ + TCO_QUAD0_DEBUG1_cache_read_busy_MASK | \ + TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK | \ + TCO_QUAD0_DEBUG1_input_quad_busy_MASK | \ + TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK | \ + TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK | \ + TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK | \ + TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK | \ + TCO_QUAD0_DEBUG1_rl_sg_rts_MASK | \ + TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK | \ + TCO_QUAD0_DEBUG1_sg_crd_rts_MASK | \ + TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) + +#define TCO_QUAD0_DEBUG1(fifo_busy, empty, full, write_enable, fifo_write_ptr, fifo_read_ptr, cache_read_busy, latency_fifo_busy, input_quad_busy, tco_quad_pipe_busy, tcb_tco_rtr_d, tcb_tco_xfc_q, rl_sg_rtr, rl_sg_rts, sg_crd_rtr, sg_crd_rts, tco_tcb_read_xfc) \ + ((fifo_busy << TCO_QUAD0_DEBUG1_fifo_busy_SHIFT) | \ + (empty << TCO_QUAD0_DEBUG1_empty_SHIFT) | \ + (full << TCO_QUAD0_DEBUG1_full_SHIFT) | \ + (write_enable << TCO_QUAD0_DEBUG1_write_enable_SHIFT) | \ + (fifo_write_ptr << TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT) | \ + (fifo_read_ptr << TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT) | \ + (cache_read_busy << TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT) | \ + (latency_fifo_busy << TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT) | \ + (input_quad_busy << TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT) | \ + (tco_quad_pipe_busy << TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT) | \ + (tcb_tco_rtr_d << TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT) | \ + (tcb_tco_xfc_q << TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT) | \ + (rl_sg_rtr << TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT) | \ + (rl_sg_rts << TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT) | \ + (sg_crd_rtr << TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT) | \ + (sg_crd_rts << TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT) | \ + (tco_tcb_read_xfc << TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT)) + +#define TCO_QUAD0_DEBUG1_GET_fifo_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_busy_MASK) >> TCO_QUAD0_DEBUG1_fifo_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_empty(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_empty_MASK) >> TCO_QUAD0_DEBUG1_empty_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_full(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_full_MASK) >> TCO_QUAD0_DEBUG1_full_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_write_enable(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_write_enable_MASK) >> TCO_QUAD0_DEBUG1_write_enable_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_fifo_write_ptr(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK) >> TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_fifo_read_ptr(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK) >> TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_cache_read_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_cache_read_busy_MASK) >> TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_latency_fifo_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK) >> TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_input_quad_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_input_quad_busy_MASK) >> TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_tco_quad_pipe_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK) >> TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_TCB_TCO_rtr_d(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK) >> TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_TCB_TCO_xfc_q(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK) >> TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_rl_sg_rtr(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK) >> TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_rl_sg_rts(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_rl_sg_rts_MASK) >> TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_sg_crd_rtr(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK) >> TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_sg_crd_rts(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_sg_crd_rts_MASK) >> TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_TCO_TCB_read_xfc(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) >> TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT) + +#define TCO_QUAD0_DEBUG1_SET_fifo_busy(tco_quad0_debug1_reg, fifo_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_busy_MASK) | (fifo_busy << TCO_QUAD0_DEBUG1_fifo_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_empty(tco_quad0_debug1_reg, empty) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_empty_MASK) | (empty << TCO_QUAD0_DEBUG1_empty_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_full(tco_quad0_debug1_reg, full) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_full_MASK) | (full << TCO_QUAD0_DEBUG1_full_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_write_enable(tco_quad0_debug1_reg, write_enable) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_write_enable_MASK) | (write_enable << TCO_QUAD0_DEBUG1_write_enable_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_fifo_write_ptr(tco_quad0_debug1_reg, fifo_write_ptr) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK) | (fifo_write_ptr << TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_fifo_read_ptr(tco_quad0_debug1_reg, fifo_read_ptr) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK) | (fifo_read_ptr << TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_cache_read_busy(tco_quad0_debug1_reg, cache_read_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_cache_read_busy_MASK) | (cache_read_busy << TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_latency_fifo_busy(tco_quad0_debug1_reg, latency_fifo_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK) | (latency_fifo_busy << TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_input_quad_busy(tco_quad0_debug1_reg, input_quad_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_input_quad_busy_MASK) | (input_quad_busy << TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_tco_quad_pipe_busy(tco_quad0_debug1_reg, tco_quad_pipe_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK) | (tco_quad_pipe_busy << TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_TCB_TCO_rtr_d(tco_quad0_debug1_reg, tcb_tco_rtr_d) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK) | (tcb_tco_rtr_d << TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_TCB_TCO_xfc_q(tco_quad0_debug1_reg, tcb_tco_xfc_q) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK) | (tcb_tco_xfc_q << TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_rl_sg_rtr(tco_quad0_debug1_reg, rl_sg_rtr) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK) | (rl_sg_rtr << TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_rl_sg_rts(tco_quad0_debug1_reg, rl_sg_rts) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_rl_sg_rts_MASK) | (rl_sg_rts << TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_sg_crd_rtr(tco_quad0_debug1_reg, sg_crd_rtr) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK) | (sg_crd_rtr << TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_sg_crd_rts(tco_quad0_debug1_reg, sg_crd_rts) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_sg_crd_rts_MASK) | (sg_crd_rts << TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_TCO_TCB_read_xfc(tco_quad0_debug1_reg, tco_tcb_read_xfc) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) | (tco_tcb_read_xfc << TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tco_quad0_debug1_t { + unsigned int fifo_busy : TCO_QUAD0_DEBUG1_fifo_busy_SIZE; + unsigned int empty : TCO_QUAD0_DEBUG1_empty_SIZE; + unsigned int full : TCO_QUAD0_DEBUG1_full_SIZE; + unsigned int write_enable : TCO_QUAD0_DEBUG1_write_enable_SIZE; + unsigned int fifo_write_ptr : TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE; + unsigned int fifo_read_ptr : TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE; + unsigned int : 2; + unsigned int cache_read_busy : TCO_QUAD0_DEBUG1_cache_read_busy_SIZE; + unsigned int latency_fifo_busy : TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE; + unsigned int input_quad_busy : TCO_QUAD0_DEBUG1_input_quad_busy_SIZE; + unsigned int tco_quad_pipe_busy : TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE; + unsigned int tcb_tco_rtr_d : TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE; + unsigned int tcb_tco_xfc_q : TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE; + unsigned int rl_sg_rtr : TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE; + unsigned int rl_sg_rts : TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE; + unsigned int sg_crd_rtr : TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE; + unsigned int sg_crd_rts : TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE; + unsigned int tco_tcb_read_xfc : TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE; + unsigned int : 1; + } tco_quad0_debug1_t; + +#else // !BIGENDIAN_OS + + typedef struct _tco_quad0_debug1_t { + unsigned int : 1; + unsigned int tco_tcb_read_xfc : TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE; + unsigned int sg_crd_rts : TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE; + unsigned int sg_crd_rtr : TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE; + unsigned int rl_sg_rts : TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE; + unsigned int rl_sg_rtr : TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE; + unsigned int tcb_tco_xfc_q : TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE; + unsigned int tcb_tco_rtr_d : TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE; + unsigned int tco_quad_pipe_busy : TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE; + unsigned int input_quad_busy : TCO_QUAD0_DEBUG1_input_quad_busy_SIZE; + unsigned int latency_fifo_busy : TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE; + unsigned int cache_read_busy : TCO_QUAD0_DEBUG1_cache_read_busy_SIZE; + unsigned int : 2; + unsigned int fifo_read_ptr : TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE; + unsigned int fifo_write_ptr : TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE; + unsigned int write_enable : TCO_QUAD0_DEBUG1_write_enable_SIZE; + unsigned int full : TCO_QUAD0_DEBUG1_full_SIZE; + unsigned int empty : TCO_QUAD0_DEBUG1_empty_SIZE; + unsigned int fifo_busy : TCO_QUAD0_DEBUG1_fifo_busy_SIZE; + } tco_quad0_debug1_t; + +#endif + +typedef union { + unsigned int val : 32; + tco_quad0_debug1_t f; +} tco_quad0_debug1_u; + + +#endif + + +#if !defined (_TC_FIDDLE_H) +#define _TC_FIDDLE_H + +/***************************************************************************************************************** + * + * tc_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +#endif + + +#if !defined (_SC_FIDDLE_H) +#define _SC_FIDDLE_H + +/***************************************************************************************************************** + * + * sc_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +#endif + + +#if !defined (_BC_FIDDLE_H) +#define _BC_FIDDLE_H + +/***************************************************************************************************************** + * + * bc_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * RB_SURFACE_INFO struct + */ + +#define RB_SURFACE_INFO_SURFACE_PITCH_SIZE 14 +#define RB_SURFACE_INFO_MSAA_SAMPLES_SIZE 2 + +#define RB_SURFACE_INFO_SURFACE_PITCH_SHIFT 0 +#define RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT 14 + +#define RB_SURFACE_INFO_SURFACE_PITCH_MASK 0x00003fff +#define RB_SURFACE_INFO_MSAA_SAMPLES_MASK 0x0000c000 + +#define RB_SURFACE_INFO_MASK \ + (RB_SURFACE_INFO_SURFACE_PITCH_MASK | \ + RB_SURFACE_INFO_MSAA_SAMPLES_MASK) + +#define RB_SURFACE_INFO(surface_pitch, msaa_samples) \ + ((surface_pitch << RB_SURFACE_INFO_SURFACE_PITCH_SHIFT) | \ + (msaa_samples << RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT)) + +#define RB_SURFACE_INFO_GET_SURFACE_PITCH(rb_surface_info) \ + ((rb_surface_info & RB_SURFACE_INFO_SURFACE_PITCH_MASK) >> RB_SURFACE_INFO_SURFACE_PITCH_SHIFT) +#define RB_SURFACE_INFO_GET_MSAA_SAMPLES(rb_surface_info) \ + ((rb_surface_info & RB_SURFACE_INFO_MSAA_SAMPLES_MASK) >> RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT) + +#define RB_SURFACE_INFO_SET_SURFACE_PITCH(rb_surface_info_reg, surface_pitch) \ + rb_surface_info_reg = (rb_surface_info_reg & ~RB_SURFACE_INFO_SURFACE_PITCH_MASK) | (surface_pitch << RB_SURFACE_INFO_SURFACE_PITCH_SHIFT) +#define RB_SURFACE_INFO_SET_MSAA_SAMPLES(rb_surface_info_reg, msaa_samples) \ + rb_surface_info_reg = (rb_surface_info_reg & ~RB_SURFACE_INFO_MSAA_SAMPLES_MASK) | (msaa_samples << RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_surface_info_t { + unsigned int surface_pitch : RB_SURFACE_INFO_SURFACE_PITCH_SIZE; + unsigned int msaa_samples : RB_SURFACE_INFO_MSAA_SAMPLES_SIZE; + unsigned int : 16; + } rb_surface_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_surface_info_t { + unsigned int : 16; + unsigned int msaa_samples : RB_SURFACE_INFO_MSAA_SAMPLES_SIZE; + unsigned int surface_pitch : RB_SURFACE_INFO_SURFACE_PITCH_SIZE; + } rb_surface_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_surface_info_t f; +} rb_surface_info_u; + + +/* + * RB_COLOR_INFO struct + */ + +#define RB_COLOR_INFO_COLOR_FORMAT_SIZE 4 +#define RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE 2 +#define RB_COLOR_INFO_COLOR_LINEAR_SIZE 1 +#define RB_COLOR_INFO_COLOR_ENDIAN_SIZE 2 +#define RB_COLOR_INFO_COLOR_SWAP_SIZE 2 +#define RB_COLOR_INFO_COLOR_BASE_SIZE 20 + +#define RB_COLOR_INFO_COLOR_FORMAT_SHIFT 0 +#define RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT 4 +#define RB_COLOR_INFO_COLOR_LINEAR_SHIFT 6 +#define RB_COLOR_INFO_COLOR_ENDIAN_SHIFT 7 +#define RB_COLOR_INFO_COLOR_SWAP_SHIFT 9 +#define RB_COLOR_INFO_COLOR_BASE_SHIFT 12 + +#define RB_COLOR_INFO_COLOR_FORMAT_MASK 0x0000000f +#define RB_COLOR_INFO_COLOR_ROUND_MODE_MASK 0x00000030 +#define RB_COLOR_INFO_COLOR_LINEAR_MASK 0x00000040 +#define RB_COLOR_INFO_COLOR_ENDIAN_MASK 0x00000180 +#define RB_COLOR_INFO_COLOR_SWAP_MASK 0x00000600 +#define RB_COLOR_INFO_COLOR_BASE_MASK 0xfffff000 + +#define RB_COLOR_INFO_MASK \ + (RB_COLOR_INFO_COLOR_FORMAT_MASK | \ + RB_COLOR_INFO_COLOR_ROUND_MODE_MASK | \ + RB_COLOR_INFO_COLOR_LINEAR_MASK | \ + RB_COLOR_INFO_COLOR_ENDIAN_MASK | \ + RB_COLOR_INFO_COLOR_SWAP_MASK | \ + RB_COLOR_INFO_COLOR_BASE_MASK) + +#define RB_COLOR_INFO(color_format, color_round_mode, color_linear, color_endian, color_swap, color_base) \ + ((color_format << RB_COLOR_INFO_COLOR_FORMAT_SHIFT) | \ + (color_round_mode << RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT) | \ + (color_linear << RB_COLOR_INFO_COLOR_LINEAR_SHIFT) | \ + (color_endian << RB_COLOR_INFO_COLOR_ENDIAN_SHIFT) | \ + (color_swap << RB_COLOR_INFO_COLOR_SWAP_SHIFT) | \ + (color_base << RB_COLOR_INFO_COLOR_BASE_SHIFT)) + +#define RB_COLOR_INFO_GET_COLOR_FORMAT(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_FORMAT_MASK) >> RB_COLOR_INFO_COLOR_FORMAT_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_ROUND_MODE(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_ROUND_MODE_MASK) >> RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_LINEAR(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_LINEAR_MASK) >> RB_COLOR_INFO_COLOR_LINEAR_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_ENDIAN(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_ENDIAN_MASK) >> RB_COLOR_INFO_COLOR_ENDIAN_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_SWAP(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_SWAP_MASK) >> RB_COLOR_INFO_COLOR_SWAP_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_BASE(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_BASE_MASK) >> RB_COLOR_INFO_COLOR_BASE_SHIFT) + +#define RB_COLOR_INFO_SET_COLOR_FORMAT(rb_color_info_reg, color_format) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_FORMAT_MASK) | (color_format << RB_COLOR_INFO_COLOR_FORMAT_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_ROUND_MODE(rb_color_info_reg, color_round_mode) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_ROUND_MODE_MASK) | (color_round_mode << RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_LINEAR(rb_color_info_reg, color_linear) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_LINEAR_MASK) | (color_linear << RB_COLOR_INFO_COLOR_LINEAR_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_ENDIAN(rb_color_info_reg, color_endian) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_ENDIAN_MASK) | (color_endian << RB_COLOR_INFO_COLOR_ENDIAN_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_SWAP(rb_color_info_reg, color_swap) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_SWAP_MASK) | (color_swap << RB_COLOR_INFO_COLOR_SWAP_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_BASE(rb_color_info_reg, color_base) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_BASE_MASK) | (color_base << RB_COLOR_INFO_COLOR_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_color_info_t { + unsigned int color_format : RB_COLOR_INFO_COLOR_FORMAT_SIZE; + unsigned int color_round_mode : RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE; + unsigned int color_linear : RB_COLOR_INFO_COLOR_LINEAR_SIZE; + unsigned int color_endian : RB_COLOR_INFO_COLOR_ENDIAN_SIZE; + unsigned int color_swap : RB_COLOR_INFO_COLOR_SWAP_SIZE; + unsigned int : 1; + unsigned int color_base : RB_COLOR_INFO_COLOR_BASE_SIZE; + } rb_color_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_color_info_t { + unsigned int color_base : RB_COLOR_INFO_COLOR_BASE_SIZE; + unsigned int : 1; + unsigned int color_swap : RB_COLOR_INFO_COLOR_SWAP_SIZE; + unsigned int color_endian : RB_COLOR_INFO_COLOR_ENDIAN_SIZE; + unsigned int color_linear : RB_COLOR_INFO_COLOR_LINEAR_SIZE; + unsigned int color_round_mode : RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE; + unsigned int color_format : RB_COLOR_INFO_COLOR_FORMAT_SIZE; + } rb_color_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_color_info_t f; +} rb_color_info_u; + + +/* + * RB_DEPTH_INFO struct + */ + +#define RB_DEPTH_INFO_DEPTH_FORMAT_SIZE 1 +#define RB_DEPTH_INFO_DEPTH_BASE_SIZE 20 + +#define RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT 0 +#define RB_DEPTH_INFO_DEPTH_BASE_SHIFT 12 + +#define RB_DEPTH_INFO_DEPTH_FORMAT_MASK 0x00000001 +#define RB_DEPTH_INFO_DEPTH_BASE_MASK 0xfffff000 + +#define RB_DEPTH_INFO_MASK \ + (RB_DEPTH_INFO_DEPTH_FORMAT_MASK | \ + RB_DEPTH_INFO_DEPTH_BASE_MASK) + +#define RB_DEPTH_INFO(depth_format, depth_base) \ + ((depth_format << RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT) | \ + (depth_base << RB_DEPTH_INFO_DEPTH_BASE_SHIFT)) + +#define RB_DEPTH_INFO_GET_DEPTH_FORMAT(rb_depth_info) \ + ((rb_depth_info & RB_DEPTH_INFO_DEPTH_FORMAT_MASK) >> RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT) +#define RB_DEPTH_INFO_GET_DEPTH_BASE(rb_depth_info) \ + ((rb_depth_info & RB_DEPTH_INFO_DEPTH_BASE_MASK) >> RB_DEPTH_INFO_DEPTH_BASE_SHIFT) + +#define RB_DEPTH_INFO_SET_DEPTH_FORMAT(rb_depth_info_reg, depth_format) \ + rb_depth_info_reg = (rb_depth_info_reg & ~RB_DEPTH_INFO_DEPTH_FORMAT_MASK) | (depth_format << RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT) +#define RB_DEPTH_INFO_SET_DEPTH_BASE(rb_depth_info_reg, depth_base) \ + rb_depth_info_reg = (rb_depth_info_reg & ~RB_DEPTH_INFO_DEPTH_BASE_MASK) | (depth_base << RB_DEPTH_INFO_DEPTH_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_depth_info_t { + unsigned int depth_format : RB_DEPTH_INFO_DEPTH_FORMAT_SIZE; + unsigned int : 11; + unsigned int depth_base : RB_DEPTH_INFO_DEPTH_BASE_SIZE; + } rb_depth_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_depth_info_t { + unsigned int depth_base : RB_DEPTH_INFO_DEPTH_BASE_SIZE; + unsigned int : 11; + unsigned int depth_format : RB_DEPTH_INFO_DEPTH_FORMAT_SIZE; + } rb_depth_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_depth_info_t f; +} rb_depth_info_u; + + +/* + * RB_STENCILREFMASK struct + */ + +#define RB_STENCILREFMASK_STENCILREF_SIZE 8 +#define RB_STENCILREFMASK_STENCILMASK_SIZE 8 +#define RB_STENCILREFMASK_STENCILWRITEMASK_SIZE 8 + +#define RB_STENCILREFMASK_STENCILREF_SHIFT 0 +#define RB_STENCILREFMASK_STENCILMASK_SHIFT 8 +#define RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT 16 + +#define RB_STENCILREFMASK_STENCILREF_MASK 0x000000ff +#define RB_STENCILREFMASK_STENCILMASK_MASK 0x0000ff00 +#define RB_STENCILREFMASK_STENCILWRITEMASK_MASK 0x00ff0000 + +#define RB_STENCILREFMASK_MASK \ + (RB_STENCILREFMASK_STENCILREF_MASK | \ + RB_STENCILREFMASK_STENCILMASK_MASK | \ + RB_STENCILREFMASK_STENCILWRITEMASK_MASK) + +#define RB_STENCILREFMASK(stencilref, stencilmask, stencilwritemask) \ + ((stencilref << RB_STENCILREFMASK_STENCILREF_SHIFT) | \ + (stencilmask << RB_STENCILREFMASK_STENCILMASK_SHIFT) | \ + (stencilwritemask << RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT)) + +#define RB_STENCILREFMASK_GET_STENCILREF(rb_stencilrefmask) \ + ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILREF_MASK) >> RB_STENCILREFMASK_STENCILREF_SHIFT) +#define RB_STENCILREFMASK_GET_STENCILMASK(rb_stencilrefmask) \ + ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILMASK_MASK) >> RB_STENCILREFMASK_STENCILMASK_SHIFT) +#define RB_STENCILREFMASK_GET_STENCILWRITEMASK(rb_stencilrefmask) \ + ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILWRITEMASK_MASK) >> RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT) + +#define RB_STENCILREFMASK_SET_STENCILREF(rb_stencilrefmask_reg, stencilref) \ + rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILREF_MASK) | (stencilref << RB_STENCILREFMASK_STENCILREF_SHIFT) +#define RB_STENCILREFMASK_SET_STENCILMASK(rb_stencilrefmask_reg, stencilmask) \ + rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILMASK_MASK) | (stencilmask << RB_STENCILREFMASK_STENCILMASK_SHIFT) +#define RB_STENCILREFMASK_SET_STENCILWRITEMASK(rb_stencilrefmask_reg, stencilwritemask) \ + rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILWRITEMASK_MASK) | (stencilwritemask << RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_stencilrefmask_t { + unsigned int stencilref : RB_STENCILREFMASK_STENCILREF_SIZE; + unsigned int stencilmask : RB_STENCILREFMASK_STENCILMASK_SIZE; + unsigned int stencilwritemask : RB_STENCILREFMASK_STENCILWRITEMASK_SIZE; + unsigned int : 8; + } rb_stencilrefmask_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_stencilrefmask_t { + unsigned int : 8; + unsigned int stencilwritemask : RB_STENCILREFMASK_STENCILWRITEMASK_SIZE; + unsigned int stencilmask : RB_STENCILREFMASK_STENCILMASK_SIZE; + unsigned int stencilref : RB_STENCILREFMASK_STENCILREF_SIZE; + } rb_stencilrefmask_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_stencilrefmask_t f; +} rb_stencilrefmask_u; + + +/* + * RB_ALPHA_REF struct + */ + +#define RB_ALPHA_REF_ALPHA_REF_SIZE 32 + +#define RB_ALPHA_REF_ALPHA_REF_SHIFT 0 + +#define RB_ALPHA_REF_ALPHA_REF_MASK 0xffffffff + +#define RB_ALPHA_REF_MASK \ + (RB_ALPHA_REF_ALPHA_REF_MASK) + +#define RB_ALPHA_REF(alpha_ref) \ + ((alpha_ref << RB_ALPHA_REF_ALPHA_REF_SHIFT)) + +#define RB_ALPHA_REF_GET_ALPHA_REF(rb_alpha_ref) \ + ((rb_alpha_ref & RB_ALPHA_REF_ALPHA_REF_MASK) >> RB_ALPHA_REF_ALPHA_REF_SHIFT) + +#define RB_ALPHA_REF_SET_ALPHA_REF(rb_alpha_ref_reg, alpha_ref) \ + rb_alpha_ref_reg = (rb_alpha_ref_reg & ~RB_ALPHA_REF_ALPHA_REF_MASK) | (alpha_ref << RB_ALPHA_REF_ALPHA_REF_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_alpha_ref_t { + unsigned int alpha_ref : RB_ALPHA_REF_ALPHA_REF_SIZE; + } rb_alpha_ref_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_alpha_ref_t { + unsigned int alpha_ref : RB_ALPHA_REF_ALPHA_REF_SIZE; + } rb_alpha_ref_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_alpha_ref_t f; +} rb_alpha_ref_u; + + +/* + * RB_COLOR_MASK struct + */ + +#define RB_COLOR_MASK_WRITE_RED_SIZE 1 +#define RB_COLOR_MASK_WRITE_GREEN_SIZE 1 +#define RB_COLOR_MASK_WRITE_BLUE_SIZE 1 +#define RB_COLOR_MASK_WRITE_ALPHA_SIZE 1 + +#define RB_COLOR_MASK_WRITE_RED_SHIFT 0 +#define RB_COLOR_MASK_WRITE_GREEN_SHIFT 1 +#define RB_COLOR_MASK_WRITE_BLUE_SHIFT 2 +#define RB_COLOR_MASK_WRITE_ALPHA_SHIFT 3 + +#define RB_COLOR_MASK_WRITE_RED_MASK 0x00000001 +#define RB_COLOR_MASK_WRITE_GREEN_MASK 0x00000002 +#define RB_COLOR_MASK_WRITE_BLUE_MASK 0x00000004 +#define RB_COLOR_MASK_WRITE_ALPHA_MASK 0x00000008 + +#define RB_COLOR_MASK_MASK \ + (RB_COLOR_MASK_WRITE_RED_MASK | \ + RB_COLOR_MASK_WRITE_GREEN_MASK | \ + RB_COLOR_MASK_WRITE_BLUE_MASK | \ + RB_COLOR_MASK_WRITE_ALPHA_MASK) + +#define RB_COLOR_MASK(write_red, write_green, write_blue, write_alpha) \ + ((write_red << RB_COLOR_MASK_WRITE_RED_SHIFT) | \ + (write_green << RB_COLOR_MASK_WRITE_GREEN_SHIFT) | \ + (write_blue << RB_COLOR_MASK_WRITE_BLUE_SHIFT) | \ + (write_alpha << RB_COLOR_MASK_WRITE_ALPHA_SHIFT)) + +#define RB_COLOR_MASK_GET_WRITE_RED(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_WRITE_RED_MASK) >> RB_COLOR_MASK_WRITE_RED_SHIFT) +#define RB_COLOR_MASK_GET_WRITE_GREEN(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_WRITE_GREEN_MASK) >> RB_COLOR_MASK_WRITE_GREEN_SHIFT) +#define RB_COLOR_MASK_GET_WRITE_BLUE(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_WRITE_BLUE_MASK) >> RB_COLOR_MASK_WRITE_BLUE_SHIFT) +#define RB_COLOR_MASK_GET_WRITE_ALPHA(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_WRITE_ALPHA_MASK) >> RB_COLOR_MASK_WRITE_ALPHA_SHIFT) + +#define RB_COLOR_MASK_SET_WRITE_RED(rb_color_mask_reg, write_red) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_RED_MASK) | (write_red << RB_COLOR_MASK_WRITE_RED_SHIFT) +#define RB_COLOR_MASK_SET_WRITE_GREEN(rb_color_mask_reg, write_green) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_GREEN_MASK) | (write_green << RB_COLOR_MASK_WRITE_GREEN_SHIFT) +#define RB_COLOR_MASK_SET_WRITE_BLUE(rb_color_mask_reg, write_blue) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_BLUE_MASK) | (write_blue << RB_COLOR_MASK_WRITE_BLUE_SHIFT) +#define RB_COLOR_MASK_SET_WRITE_ALPHA(rb_color_mask_reg, write_alpha) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_ALPHA_MASK) | (write_alpha << RB_COLOR_MASK_WRITE_ALPHA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_color_mask_t { + unsigned int write_red : RB_COLOR_MASK_WRITE_RED_SIZE; + unsigned int write_green : RB_COLOR_MASK_WRITE_GREEN_SIZE; + unsigned int write_blue : RB_COLOR_MASK_WRITE_BLUE_SIZE; + unsigned int write_alpha : RB_COLOR_MASK_WRITE_ALPHA_SIZE; + unsigned int : 28; + } rb_color_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_color_mask_t { + unsigned int : 28; + unsigned int write_alpha : RB_COLOR_MASK_WRITE_ALPHA_SIZE; + unsigned int write_blue : RB_COLOR_MASK_WRITE_BLUE_SIZE; + unsigned int write_green : RB_COLOR_MASK_WRITE_GREEN_SIZE; + unsigned int write_red : RB_COLOR_MASK_WRITE_RED_SIZE; + } rb_color_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_color_mask_t f; +} rb_color_mask_u; + + +/* + * RB_BLEND_RED struct + */ + +#define RB_BLEND_RED_BLEND_RED_SIZE 8 + +#define RB_BLEND_RED_BLEND_RED_SHIFT 0 + +#define RB_BLEND_RED_BLEND_RED_MASK 0x000000ff + +#define RB_BLEND_RED_MASK \ + (RB_BLEND_RED_BLEND_RED_MASK) + +#define RB_BLEND_RED(blend_red) \ + ((blend_red << RB_BLEND_RED_BLEND_RED_SHIFT)) + +#define RB_BLEND_RED_GET_BLEND_RED(rb_blend_red) \ + ((rb_blend_red & RB_BLEND_RED_BLEND_RED_MASK) >> RB_BLEND_RED_BLEND_RED_SHIFT) + +#define RB_BLEND_RED_SET_BLEND_RED(rb_blend_red_reg, blend_red) \ + rb_blend_red_reg = (rb_blend_red_reg & ~RB_BLEND_RED_BLEND_RED_MASK) | (blend_red << RB_BLEND_RED_BLEND_RED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blend_red_t { + unsigned int blend_red : RB_BLEND_RED_BLEND_RED_SIZE; + unsigned int : 24; + } rb_blend_red_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blend_red_t { + unsigned int : 24; + unsigned int blend_red : RB_BLEND_RED_BLEND_RED_SIZE; + } rb_blend_red_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blend_red_t f; +} rb_blend_red_u; + + +/* + * RB_BLEND_GREEN struct + */ + +#define RB_BLEND_GREEN_BLEND_GREEN_SIZE 8 + +#define RB_BLEND_GREEN_BLEND_GREEN_SHIFT 0 + +#define RB_BLEND_GREEN_BLEND_GREEN_MASK 0x000000ff + +#define RB_BLEND_GREEN_MASK \ + (RB_BLEND_GREEN_BLEND_GREEN_MASK) + +#define RB_BLEND_GREEN(blend_green) \ + ((blend_green << RB_BLEND_GREEN_BLEND_GREEN_SHIFT)) + +#define RB_BLEND_GREEN_GET_BLEND_GREEN(rb_blend_green) \ + ((rb_blend_green & RB_BLEND_GREEN_BLEND_GREEN_MASK) >> RB_BLEND_GREEN_BLEND_GREEN_SHIFT) + +#define RB_BLEND_GREEN_SET_BLEND_GREEN(rb_blend_green_reg, blend_green) \ + rb_blend_green_reg = (rb_blend_green_reg & ~RB_BLEND_GREEN_BLEND_GREEN_MASK) | (blend_green << RB_BLEND_GREEN_BLEND_GREEN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blend_green_t { + unsigned int blend_green : RB_BLEND_GREEN_BLEND_GREEN_SIZE; + unsigned int : 24; + } rb_blend_green_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blend_green_t { + unsigned int : 24; + unsigned int blend_green : RB_BLEND_GREEN_BLEND_GREEN_SIZE; + } rb_blend_green_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blend_green_t f; +} rb_blend_green_u; + + +/* + * RB_BLEND_BLUE struct + */ + +#define RB_BLEND_BLUE_BLEND_BLUE_SIZE 8 + +#define RB_BLEND_BLUE_BLEND_BLUE_SHIFT 0 + +#define RB_BLEND_BLUE_BLEND_BLUE_MASK 0x000000ff + +#define RB_BLEND_BLUE_MASK \ + (RB_BLEND_BLUE_BLEND_BLUE_MASK) + +#define RB_BLEND_BLUE(blend_blue) \ + ((blend_blue << RB_BLEND_BLUE_BLEND_BLUE_SHIFT)) + +#define RB_BLEND_BLUE_GET_BLEND_BLUE(rb_blend_blue) \ + ((rb_blend_blue & RB_BLEND_BLUE_BLEND_BLUE_MASK) >> RB_BLEND_BLUE_BLEND_BLUE_SHIFT) + +#define RB_BLEND_BLUE_SET_BLEND_BLUE(rb_blend_blue_reg, blend_blue) \ + rb_blend_blue_reg = (rb_blend_blue_reg & ~RB_BLEND_BLUE_BLEND_BLUE_MASK) | (blend_blue << RB_BLEND_BLUE_BLEND_BLUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blend_blue_t { + unsigned int blend_blue : RB_BLEND_BLUE_BLEND_BLUE_SIZE; + unsigned int : 24; + } rb_blend_blue_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blend_blue_t { + unsigned int : 24; + unsigned int blend_blue : RB_BLEND_BLUE_BLEND_BLUE_SIZE; + } rb_blend_blue_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blend_blue_t f; +} rb_blend_blue_u; + + +/* + * RB_BLEND_ALPHA struct + */ + +#define RB_BLEND_ALPHA_BLEND_ALPHA_SIZE 8 + +#define RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT 0 + +#define RB_BLEND_ALPHA_BLEND_ALPHA_MASK 0x000000ff + +#define RB_BLEND_ALPHA_MASK \ + (RB_BLEND_ALPHA_BLEND_ALPHA_MASK) + +#define RB_BLEND_ALPHA(blend_alpha) \ + ((blend_alpha << RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT)) + +#define RB_BLEND_ALPHA_GET_BLEND_ALPHA(rb_blend_alpha) \ + ((rb_blend_alpha & RB_BLEND_ALPHA_BLEND_ALPHA_MASK) >> RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT) + +#define RB_BLEND_ALPHA_SET_BLEND_ALPHA(rb_blend_alpha_reg, blend_alpha) \ + rb_blend_alpha_reg = (rb_blend_alpha_reg & ~RB_BLEND_ALPHA_BLEND_ALPHA_MASK) | (blend_alpha << RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blend_alpha_t { + unsigned int blend_alpha : RB_BLEND_ALPHA_BLEND_ALPHA_SIZE; + unsigned int : 24; + } rb_blend_alpha_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blend_alpha_t { + unsigned int : 24; + unsigned int blend_alpha : RB_BLEND_ALPHA_BLEND_ALPHA_SIZE; + } rb_blend_alpha_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blend_alpha_t f; +} rb_blend_alpha_u; + + +/* + * RB_FOG_COLOR struct + */ + +#define RB_FOG_COLOR_FOG_RED_SIZE 8 +#define RB_FOG_COLOR_FOG_GREEN_SIZE 8 +#define RB_FOG_COLOR_FOG_BLUE_SIZE 8 + +#define RB_FOG_COLOR_FOG_RED_SHIFT 0 +#define RB_FOG_COLOR_FOG_GREEN_SHIFT 8 +#define RB_FOG_COLOR_FOG_BLUE_SHIFT 16 + +#define RB_FOG_COLOR_FOG_RED_MASK 0x000000ff +#define RB_FOG_COLOR_FOG_GREEN_MASK 0x0000ff00 +#define RB_FOG_COLOR_FOG_BLUE_MASK 0x00ff0000 + +#define RB_FOG_COLOR_MASK \ + (RB_FOG_COLOR_FOG_RED_MASK | \ + RB_FOG_COLOR_FOG_GREEN_MASK | \ + RB_FOG_COLOR_FOG_BLUE_MASK) + +#define RB_FOG_COLOR(fog_red, fog_green, fog_blue) \ + ((fog_red << RB_FOG_COLOR_FOG_RED_SHIFT) | \ + (fog_green << RB_FOG_COLOR_FOG_GREEN_SHIFT) | \ + (fog_blue << RB_FOG_COLOR_FOG_BLUE_SHIFT)) + +#define RB_FOG_COLOR_GET_FOG_RED(rb_fog_color) \ + ((rb_fog_color & RB_FOG_COLOR_FOG_RED_MASK) >> RB_FOG_COLOR_FOG_RED_SHIFT) +#define RB_FOG_COLOR_GET_FOG_GREEN(rb_fog_color) \ + ((rb_fog_color & RB_FOG_COLOR_FOG_GREEN_MASK) >> RB_FOG_COLOR_FOG_GREEN_SHIFT) +#define RB_FOG_COLOR_GET_FOG_BLUE(rb_fog_color) \ + ((rb_fog_color & RB_FOG_COLOR_FOG_BLUE_MASK) >> RB_FOG_COLOR_FOG_BLUE_SHIFT) + +#define RB_FOG_COLOR_SET_FOG_RED(rb_fog_color_reg, fog_red) \ + rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_RED_MASK) | (fog_red << RB_FOG_COLOR_FOG_RED_SHIFT) +#define RB_FOG_COLOR_SET_FOG_GREEN(rb_fog_color_reg, fog_green) \ + rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_GREEN_MASK) | (fog_green << RB_FOG_COLOR_FOG_GREEN_SHIFT) +#define RB_FOG_COLOR_SET_FOG_BLUE(rb_fog_color_reg, fog_blue) \ + rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_BLUE_MASK) | (fog_blue << RB_FOG_COLOR_FOG_BLUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_fog_color_t { + unsigned int fog_red : RB_FOG_COLOR_FOG_RED_SIZE; + unsigned int fog_green : RB_FOG_COLOR_FOG_GREEN_SIZE; + unsigned int fog_blue : RB_FOG_COLOR_FOG_BLUE_SIZE; + unsigned int : 8; + } rb_fog_color_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_fog_color_t { + unsigned int : 8; + unsigned int fog_blue : RB_FOG_COLOR_FOG_BLUE_SIZE; + unsigned int fog_green : RB_FOG_COLOR_FOG_GREEN_SIZE; + unsigned int fog_red : RB_FOG_COLOR_FOG_RED_SIZE; + } rb_fog_color_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_fog_color_t f; +} rb_fog_color_u; + + +/* + * RB_STENCILREFMASK_BF struct + */ + +#define RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE 8 +#define RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE 8 +#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE 8 + +#define RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT 0 +#define RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT 8 +#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT 16 + +#define RB_STENCILREFMASK_BF_STENCILREF_BF_MASK 0x000000ff +#define RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK 0x0000ff00 +#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK 0x00ff0000 + +#define RB_STENCILREFMASK_BF_MASK \ + (RB_STENCILREFMASK_BF_STENCILREF_BF_MASK | \ + RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK | \ + RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK) + +#define RB_STENCILREFMASK_BF(stencilref_bf, stencilmask_bf, stencilwritemask_bf) \ + ((stencilref_bf << RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT) | \ + (stencilmask_bf << RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT) | \ + (stencilwritemask_bf << RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT)) + +#define RB_STENCILREFMASK_BF_GET_STENCILREF_BF(rb_stencilrefmask_bf) \ + ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILREF_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT) +#define RB_STENCILREFMASK_BF_GET_STENCILMASK_BF(rb_stencilrefmask_bf) \ + ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT) +#define RB_STENCILREFMASK_BF_GET_STENCILWRITEMASK_BF(rb_stencilrefmask_bf) \ + ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT) + +#define RB_STENCILREFMASK_BF_SET_STENCILREF_BF(rb_stencilrefmask_bf_reg, stencilref_bf) \ + rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILREF_BF_MASK) | (stencilref_bf << RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT) +#define RB_STENCILREFMASK_BF_SET_STENCILMASK_BF(rb_stencilrefmask_bf_reg, stencilmask_bf) \ + rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK) | (stencilmask_bf << RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT) +#define RB_STENCILREFMASK_BF_SET_STENCILWRITEMASK_BF(rb_stencilrefmask_bf_reg, stencilwritemask_bf) \ + rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK) | (stencilwritemask_bf << RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_stencilrefmask_bf_t { + unsigned int stencilref_bf : RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE; + unsigned int stencilmask_bf : RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE; + unsigned int stencilwritemask_bf : RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE; + unsigned int : 8; + } rb_stencilrefmask_bf_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_stencilrefmask_bf_t { + unsigned int : 8; + unsigned int stencilwritemask_bf : RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE; + unsigned int stencilmask_bf : RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE; + unsigned int stencilref_bf : RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE; + } rb_stencilrefmask_bf_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_stencilrefmask_bf_t f; +} rb_stencilrefmask_bf_u; + + +/* + * RB_DEPTHCONTROL struct + */ + +#define RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_Z_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_ZFUNC_SIZE 3 +#define RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_STENCILFUNC_SIZE 3 +#define RB_DEPTHCONTROL_STENCILFAIL_SIZE 3 +#define RB_DEPTHCONTROL_STENCILZPASS_SIZE 3 +#define RB_DEPTHCONTROL_STENCILZFAIL_SIZE 3 +#define RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE 3 +#define RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE 3 +#define RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE 3 +#define RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE 3 + +#define RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT 0 +#define RB_DEPTHCONTROL_Z_ENABLE_SHIFT 1 +#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT 2 +#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT 3 +#define RB_DEPTHCONTROL_ZFUNC_SHIFT 4 +#define RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT 7 +#define RB_DEPTHCONTROL_STENCILFUNC_SHIFT 8 +#define RB_DEPTHCONTROL_STENCILFAIL_SHIFT 11 +#define RB_DEPTHCONTROL_STENCILZPASS_SHIFT 14 +#define RB_DEPTHCONTROL_STENCILZFAIL_SHIFT 17 +#define RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT 20 +#define RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT 23 +#define RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT 26 +#define RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT 29 + +#define RB_DEPTHCONTROL_STENCIL_ENABLE_MASK 0x00000001 +#define RB_DEPTHCONTROL_Z_ENABLE_MASK 0x00000002 +#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK 0x00000004 +#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK 0x00000008 +#define RB_DEPTHCONTROL_ZFUNC_MASK 0x00000070 +#define RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK 0x00000080 +#define RB_DEPTHCONTROL_STENCILFUNC_MASK 0x00000700 +#define RB_DEPTHCONTROL_STENCILFAIL_MASK 0x00003800 +#define RB_DEPTHCONTROL_STENCILZPASS_MASK 0x0001c000 +#define RB_DEPTHCONTROL_STENCILZFAIL_MASK 0x000e0000 +#define RB_DEPTHCONTROL_STENCILFUNC_BF_MASK 0x00700000 +#define RB_DEPTHCONTROL_STENCILFAIL_BF_MASK 0x03800000 +#define RB_DEPTHCONTROL_STENCILZPASS_BF_MASK 0x1c000000 +#define RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK 0xe0000000 + +#define RB_DEPTHCONTROL_MASK \ + (RB_DEPTHCONTROL_STENCIL_ENABLE_MASK | \ + RB_DEPTHCONTROL_Z_ENABLE_MASK | \ + RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK | \ + RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK | \ + RB_DEPTHCONTROL_ZFUNC_MASK | \ + RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK | \ + RB_DEPTHCONTROL_STENCILFUNC_MASK | \ + RB_DEPTHCONTROL_STENCILFAIL_MASK | \ + RB_DEPTHCONTROL_STENCILZPASS_MASK | \ + RB_DEPTHCONTROL_STENCILZFAIL_MASK | \ + RB_DEPTHCONTROL_STENCILFUNC_BF_MASK | \ + RB_DEPTHCONTROL_STENCILFAIL_BF_MASK | \ + RB_DEPTHCONTROL_STENCILZPASS_BF_MASK | \ + RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) + +#define RB_DEPTHCONTROL(stencil_enable, z_enable, z_write_enable, early_z_enable, zfunc, backface_enable, stencilfunc, stencilfail, stencilzpass, stencilzfail, stencilfunc_bf, stencilfail_bf, stencilzpass_bf, stencilzfail_bf) \ + ((stencil_enable << RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT) | \ + (z_enable << RB_DEPTHCONTROL_Z_ENABLE_SHIFT) | \ + (z_write_enable << RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT) | \ + (early_z_enable << RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT) | \ + (zfunc << RB_DEPTHCONTROL_ZFUNC_SHIFT) | \ + (backface_enable << RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT) | \ + (stencilfunc << RB_DEPTHCONTROL_STENCILFUNC_SHIFT) | \ + (stencilfail << RB_DEPTHCONTROL_STENCILFAIL_SHIFT) | \ + (stencilzpass << RB_DEPTHCONTROL_STENCILZPASS_SHIFT) | \ + (stencilzfail << RB_DEPTHCONTROL_STENCILZFAIL_SHIFT) | \ + (stencilfunc_bf << RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT) | \ + (stencilfail_bf << RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT) | \ + (stencilzpass_bf << RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT) | \ + (stencilzfail_bf << RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT)) + +#define RB_DEPTHCONTROL_GET_STENCIL_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCIL_ENABLE_MASK) >> RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_Z_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_Z_ENABLE_MASK) >> RB_DEPTHCONTROL_Z_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_Z_WRITE_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK) >> RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_EARLY_Z_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK) >> RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_ZFUNC(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_ZFUNC_MASK) >> RB_DEPTHCONTROL_ZFUNC_SHIFT) +#define RB_DEPTHCONTROL_GET_BACKFACE_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK) >> RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILFUNC(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFUNC_MASK) >> RB_DEPTHCONTROL_STENCILFUNC_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILFAIL(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFAIL_MASK) >> RB_DEPTHCONTROL_STENCILFAIL_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILZPASS(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZPASS_MASK) >> RB_DEPTHCONTROL_STENCILZPASS_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILZFAIL(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZFAIL_MASK) >> RB_DEPTHCONTROL_STENCILZFAIL_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILFUNC_BF(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFUNC_BF_MASK) >> RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILFAIL_BF(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFAIL_BF_MASK) >> RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILZPASS_BF(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZPASS_BF_MASK) >> RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILZFAIL_BF(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) >> RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT) + +#define RB_DEPTHCONTROL_SET_STENCIL_ENABLE(rb_depthcontrol_reg, stencil_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCIL_ENABLE_MASK) | (stencil_enable << RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_Z_ENABLE(rb_depthcontrol_reg, z_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_Z_ENABLE_MASK) | (z_enable << RB_DEPTHCONTROL_Z_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_Z_WRITE_ENABLE(rb_depthcontrol_reg, z_write_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK) | (z_write_enable << RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_EARLY_Z_ENABLE(rb_depthcontrol_reg, early_z_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK) | (early_z_enable << RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_ZFUNC(rb_depthcontrol_reg, zfunc) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_ZFUNC_MASK) | (zfunc << RB_DEPTHCONTROL_ZFUNC_SHIFT) +#define RB_DEPTHCONTROL_SET_BACKFACE_ENABLE(rb_depthcontrol_reg, backface_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK) | (backface_enable << RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILFUNC(rb_depthcontrol_reg, stencilfunc) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFUNC_MASK) | (stencilfunc << RB_DEPTHCONTROL_STENCILFUNC_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILFAIL(rb_depthcontrol_reg, stencilfail) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFAIL_MASK) | (stencilfail << RB_DEPTHCONTROL_STENCILFAIL_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILZPASS(rb_depthcontrol_reg, stencilzpass) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZPASS_MASK) | (stencilzpass << RB_DEPTHCONTROL_STENCILZPASS_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILZFAIL(rb_depthcontrol_reg, stencilzfail) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZFAIL_MASK) | (stencilzfail << RB_DEPTHCONTROL_STENCILZFAIL_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILFUNC_BF(rb_depthcontrol_reg, stencilfunc_bf) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFUNC_BF_MASK) | (stencilfunc_bf << RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILFAIL_BF(rb_depthcontrol_reg, stencilfail_bf) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFAIL_BF_MASK) | (stencilfail_bf << RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILZPASS_BF(rb_depthcontrol_reg, stencilzpass_bf) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZPASS_BF_MASK) | (stencilzpass_bf << RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILZFAIL_BF(rb_depthcontrol_reg, stencilzfail_bf) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) | (stencilzfail_bf << RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_depthcontrol_t { + unsigned int stencil_enable : RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE; + unsigned int z_enable : RB_DEPTHCONTROL_Z_ENABLE_SIZE; + unsigned int z_write_enable : RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE; + unsigned int early_z_enable : RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE; + unsigned int zfunc : RB_DEPTHCONTROL_ZFUNC_SIZE; + unsigned int backface_enable : RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE; + unsigned int stencilfunc : RB_DEPTHCONTROL_STENCILFUNC_SIZE; + unsigned int stencilfail : RB_DEPTHCONTROL_STENCILFAIL_SIZE; + unsigned int stencilzpass : RB_DEPTHCONTROL_STENCILZPASS_SIZE; + unsigned int stencilzfail : RB_DEPTHCONTROL_STENCILZFAIL_SIZE; + unsigned int stencilfunc_bf : RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE; + unsigned int stencilfail_bf : RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE; + unsigned int stencilzpass_bf : RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE; + unsigned int stencilzfail_bf : RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE; + } rb_depthcontrol_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_depthcontrol_t { + unsigned int stencilzfail_bf : RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE; + unsigned int stencilzpass_bf : RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE; + unsigned int stencilfail_bf : RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE; + unsigned int stencilfunc_bf : RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE; + unsigned int stencilzfail : RB_DEPTHCONTROL_STENCILZFAIL_SIZE; + unsigned int stencilzpass : RB_DEPTHCONTROL_STENCILZPASS_SIZE; + unsigned int stencilfail : RB_DEPTHCONTROL_STENCILFAIL_SIZE; + unsigned int stencilfunc : RB_DEPTHCONTROL_STENCILFUNC_SIZE; + unsigned int backface_enable : RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE; + unsigned int zfunc : RB_DEPTHCONTROL_ZFUNC_SIZE; + unsigned int early_z_enable : RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE; + unsigned int z_write_enable : RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE; + unsigned int z_enable : RB_DEPTHCONTROL_Z_ENABLE_SIZE; + unsigned int stencil_enable : RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE; + } rb_depthcontrol_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_depthcontrol_t f; +} rb_depthcontrol_u; + + +/* + * RB_BLENDCONTROL struct + */ + +#define RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE 5 +#define RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE 3 +#define RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE 5 +#define RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE 5 +#define RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE 3 +#define RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE 5 +#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE 1 +#define RB_BLENDCONTROL_BLEND_FORCE_SIZE 1 + +#define RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT 0 +#define RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT 5 +#define RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT 8 +#define RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT 16 +#define RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT 21 +#define RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT 24 +#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT 29 +#define RB_BLENDCONTROL_BLEND_FORCE_SHIFT 30 + +#define RB_BLENDCONTROL_COLOR_SRCBLEND_MASK 0x0000001f +#define RB_BLENDCONTROL_COLOR_COMB_FCN_MASK 0x000000e0 +#define RB_BLENDCONTROL_COLOR_DESTBLEND_MASK 0x00001f00 +#define RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK 0x001f0000 +#define RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK 0x00e00000 +#define RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK 0x1f000000 +#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK 0x20000000 +#define RB_BLENDCONTROL_BLEND_FORCE_MASK 0x40000000 + +#define RB_BLENDCONTROL_MASK \ + (RB_BLENDCONTROL_COLOR_SRCBLEND_MASK | \ + RB_BLENDCONTROL_COLOR_COMB_FCN_MASK | \ + RB_BLENDCONTROL_COLOR_DESTBLEND_MASK | \ + RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK | \ + RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK | \ + RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK | \ + RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK | \ + RB_BLENDCONTROL_BLEND_FORCE_MASK) + +#define RB_BLENDCONTROL(color_srcblend, color_comb_fcn, color_destblend, alpha_srcblend, alpha_comb_fcn, alpha_destblend, blend_force_enable, blend_force) \ + ((color_srcblend << RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT) | \ + (color_comb_fcn << RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT) | \ + (color_destblend << RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT) | \ + (alpha_srcblend << RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT) | \ + (alpha_comb_fcn << RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT) | \ + (alpha_destblend << RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT) | \ + (blend_force_enable << RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT) | \ + (blend_force << RB_BLENDCONTROL_BLEND_FORCE_SHIFT)) + +#define RB_BLENDCONTROL_GET_COLOR_SRCBLEND(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_SRCBLEND_MASK) >> RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT) +#define RB_BLENDCONTROL_GET_COLOR_COMB_FCN(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_COMB_FCN_MASK) >> RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT) +#define RB_BLENDCONTROL_GET_COLOR_DESTBLEND(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_DESTBLEND_MASK) >> RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT) +#define RB_BLENDCONTROL_GET_ALPHA_SRCBLEND(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK) >> RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT) +#define RB_BLENDCONTROL_GET_ALPHA_COMB_FCN(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK) >> RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT) +#define RB_BLENDCONTROL_GET_ALPHA_DESTBLEND(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK) >> RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT) +#define RB_BLENDCONTROL_GET_BLEND_FORCE_ENABLE(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK) >> RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT) +#define RB_BLENDCONTROL_GET_BLEND_FORCE(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_BLEND_FORCE_MASK) >> RB_BLENDCONTROL_BLEND_FORCE_SHIFT) + +#define RB_BLENDCONTROL_SET_COLOR_SRCBLEND(rb_blendcontrol_reg, color_srcblend) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_SRCBLEND_MASK) | (color_srcblend << RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT) +#define RB_BLENDCONTROL_SET_COLOR_COMB_FCN(rb_blendcontrol_reg, color_comb_fcn) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_COMB_FCN_MASK) | (color_comb_fcn << RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT) +#define RB_BLENDCONTROL_SET_COLOR_DESTBLEND(rb_blendcontrol_reg, color_destblend) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_DESTBLEND_MASK) | (color_destblend << RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT) +#define RB_BLENDCONTROL_SET_ALPHA_SRCBLEND(rb_blendcontrol_reg, alpha_srcblend) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK) | (alpha_srcblend << RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT) +#define RB_BLENDCONTROL_SET_ALPHA_COMB_FCN(rb_blendcontrol_reg, alpha_comb_fcn) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK) | (alpha_comb_fcn << RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT) +#define RB_BLENDCONTROL_SET_ALPHA_DESTBLEND(rb_blendcontrol_reg, alpha_destblend) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK) | (alpha_destblend << RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT) +#define RB_BLENDCONTROL_SET_BLEND_FORCE_ENABLE(rb_blendcontrol_reg, blend_force_enable) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK) | (blend_force_enable << RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT) +#define RB_BLENDCONTROL_SET_BLEND_FORCE(rb_blendcontrol_reg, blend_force) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_BLEND_FORCE_MASK) | (blend_force << RB_BLENDCONTROL_BLEND_FORCE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blendcontrol_t { + unsigned int color_srcblend : RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE; + unsigned int color_comb_fcn : RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE; + unsigned int color_destblend : RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE; + unsigned int : 3; + unsigned int alpha_srcblend : RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE; + unsigned int alpha_comb_fcn : RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE; + unsigned int alpha_destblend : RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE; + unsigned int blend_force_enable : RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE; + unsigned int blend_force : RB_BLENDCONTROL_BLEND_FORCE_SIZE; + unsigned int : 1; + } rb_blendcontrol_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blendcontrol_t { + unsigned int : 1; + unsigned int blend_force : RB_BLENDCONTROL_BLEND_FORCE_SIZE; + unsigned int blend_force_enable : RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE; + unsigned int alpha_destblend : RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE; + unsigned int alpha_comb_fcn : RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE; + unsigned int alpha_srcblend : RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE; + unsigned int : 3; + unsigned int color_destblend : RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE; + unsigned int color_comb_fcn : RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE; + unsigned int color_srcblend : RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE; + } rb_blendcontrol_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blendcontrol_t f; +} rb_blendcontrol_u; + + +/* + * RB_COLORCONTROL struct + */ + +#define RB_COLORCONTROL_ALPHA_FUNC_SIZE 3 +#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE 1 +#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE 1 +#define RB_COLORCONTROL_BLEND_DISABLE_SIZE 1 +#define RB_COLORCONTROL_FOG_ENABLE_SIZE 1 +#define RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE 1 +#define RB_COLORCONTROL_ROP_CODE_SIZE 4 +#define RB_COLORCONTROL_DITHER_MODE_SIZE 2 +#define RB_COLORCONTROL_DITHER_TYPE_SIZE 2 +#define RB_COLORCONTROL_PIXEL_FOG_SIZE 1 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE 2 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE 2 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE 2 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE 2 + +#define RB_COLORCONTROL_ALPHA_FUNC_SHIFT 0 +#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT 3 +#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT 4 +#define RB_COLORCONTROL_BLEND_DISABLE_SHIFT 5 +#define RB_COLORCONTROL_FOG_ENABLE_SHIFT 6 +#define RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT 7 +#define RB_COLORCONTROL_ROP_CODE_SHIFT 8 +#define RB_COLORCONTROL_DITHER_MODE_SHIFT 12 +#define RB_COLORCONTROL_DITHER_TYPE_SHIFT 14 +#define RB_COLORCONTROL_PIXEL_FOG_SHIFT 16 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT 24 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT 26 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT 28 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT 30 + +#define RB_COLORCONTROL_ALPHA_FUNC_MASK 0x00000007 +#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK 0x00000008 +#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK 0x00000010 +#define RB_COLORCONTROL_BLEND_DISABLE_MASK 0x00000020 +#define RB_COLORCONTROL_FOG_ENABLE_MASK 0x00000040 +#define RB_COLORCONTROL_VS_EXPORTS_FOG_MASK 0x00000080 +#define RB_COLORCONTROL_ROP_CODE_MASK 0x00000f00 +#define RB_COLORCONTROL_DITHER_MODE_MASK 0x00003000 +#define RB_COLORCONTROL_DITHER_TYPE_MASK 0x0000c000 +#define RB_COLORCONTROL_PIXEL_FOG_MASK 0x00010000 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK 0x03000000 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK 0x0c000000 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK 0x30000000 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK 0xc0000000 + +#define RB_COLORCONTROL_MASK \ + (RB_COLORCONTROL_ALPHA_FUNC_MASK | \ + RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK | \ + RB_COLORCONTROL_BLEND_DISABLE_MASK | \ + RB_COLORCONTROL_FOG_ENABLE_MASK | \ + RB_COLORCONTROL_VS_EXPORTS_FOG_MASK | \ + RB_COLORCONTROL_ROP_CODE_MASK | \ + RB_COLORCONTROL_DITHER_MODE_MASK | \ + RB_COLORCONTROL_DITHER_TYPE_MASK | \ + RB_COLORCONTROL_PIXEL_FOG_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) + +#define RB_COLORCONTROL(alpha_func, alpha_test_enable, alpha_to_mask_enable, blend_disable, fog_enable, vs_exports_fog, rop_code, dither_mode, dither_type, pixel_fog, alpha_to_mask_offset0, alpha_to_mask_offset1, alpha_to_mask_offset2, alpha_to_mask_offset3) \ + ((alpha_func << RB_COLORCONTROL_ALPHA_FUNC_SHIFT) | \ + (alpha_test_enable << RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT) | \ + (alpha_to_mask_enable << RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT) | \ + (blend_disable << RB_COLORCONTROL_BLEND_DISABLE_SHIFT) | \ + (fog_enable << RB_COLORCONTROL_FOG_ENABLE_SHIFT) | \ + (vs_exports_fog << RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT) | \ + (rop_code << RB_COLORCONTROL_ROP_CODE_SHIFT) | \ + (dither_mode << RB_COLORCONTROL_DITHER_MODE_SHIFT) | \ + (dither_type << RB_COLORCONTROL_DITHER_TYPE_SHIFT) | \ + (pixel_fog << RB_COLORCONTROL_PIXEL_FOG_SHIFT) | \ + (alpha_to_mask_offset0 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT) | \ + (alpha_to_mask_offset1 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT) | \ + (alpha_to_mask_offset2 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT) | \ + (alpha_to_mask_offset3 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT)) + +#define RB_COLORCONTROL_GET_ALPHA_FUNC(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_FUNC_MASK) >> RB_COLORCONTROL_ALPHA_FUNC_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TEST_ENABLE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK) >> RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_ENABLE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT) +#define RB_COLORCONTROL_GET_BLEND_DISABLE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_BLEND_DISABLE_MASK) >> RB_COLORCONTROL_BLEND_DISABLE_SHIFT) +#define RB_COLORCONTROL_GET_FOG_ENABLE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_FOG_ENABLE_MASK) >> RB_COLORCONTROL_FOG_ENABLE_SHIFT) +#define RB_COLORCONTROL_GET_VS_EXPORTS_FOG(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_VS_EXPORTS_FOG_MASK) >> RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT) +#define RB_COLORCONTROL_GET_ROP_CODE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ROP_CODE_MASK) >> RB_COLORCONTROL_ROP_CODE_SHIFT) +#define RB_COLORCONTROL_GET_DITHER_MODE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_DITHER_MODE_MASK) >> RB_COLORCONTROL_DITHER_MODE_SHIFT) +#define RB_COLORCONTROL_GET_DITHER_TYPE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_DITHER_TYPE_MASK) >> RB_COLORCONTROL_DITHER_TYPE_SHIFT) +#define RB_COLORCONTROL_GET_PIXEL_FOG(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_PIXEL_FOG_MASK) >> RB_COLORCONTROL_PIXEL_FOG_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET0(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET1(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET2(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET3(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT) + +#define RB_COLORCONTROL_SET_ALPHA_FUNC(rb_colorcontrol_reg, alpha_func) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_FUNC_MASK) | (alpha_func << RB_COLORCONTROL_ALPHA_FUNC_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TEST_ENABLE(rb_colorcontrol_reg, alpha_test_enable) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK) | (alpha_test_enable << RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_ENABLE(rb_colorcontrol_reg, alpha_to_mask_enable) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK) | (alpha_to_mask_enable << RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT) +#define RB_COLORCONTROL_SET_BLEND_DISABLE(rb_colorcontrol_reg, blend_disable) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_BLEND_DISABLE_MASK) | (blend_disable << RB_COLORCONTROL_BLEND_DISABLE_SHIFT) +#define RB_COLORCONTROL_SET_FOG_ENABLE(rb_colorcontrol_reg, fog_enable) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_FOG_ENABLE_MASK) | (fog_enable << RB_COLORCONTROL_FOG_ENABLE_SHIFT) +#define RB_COLORCONTROL_SET_VS_EXPORTS_FOG(rb_colorcontrol_reg, vs_exports_fog) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_VS_EXPORTS_FOG_MASK) | (vs_exports_fog << RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT) +#define RB_COLORCONTROL_SET_ROP_CODE(rb_colorcontrol_reg, rop_code) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ROP_CODE_MASK) | (rop_code << RB_COLORCONTROL_ROP_CODE_SHIFT) +#define RB_COLORCONTROL_SET_DITHER_MODE(rb_colorcontrol_reg, dither_mode) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_DITHER_MODE_MASK) | (dither_mode << RB_COLORCONTROL_DITHER_MODE_SHIFT) +#define RB_COLORCONTROL_SET_DITHER_TYPE(rb_colorcontrol_reg, dither_type) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_DITHER_TYPE_MASK) | (dither_type << RB_COLORCONTROL_DITHER_TYPE_SHIFT) +#define RB_COLORCONTROL_SET_PIXEL_FOG(rb_colorcontrol_reg, pixel_fog) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_PIXEL_FOG_MASK) | (pixel_fog << RB_COLORCONTROL_PIXEL_FOG_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET0(rb_colorcontrol_reg, alpha_to_mask_offset0) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK) | (alpha_to_mask_offset0 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET1(rb_colorcontrol_reg, alpha_to_mask_offset1) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK) | (alpha_to_mask_offset1 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET2(rb_colorcontrol_reg, alpha_to_mask_offset2) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK) | (alpha_to_mask_offset2 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET3(rb_colorcontrol_reg, alpha_to_mask_offset3) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) | (alpha_to_mask_offset3 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_colorcontrol_t { + unsigned int alpha_func : RB_COLORCONTROL_ALPHA_FUNC_SIZE; + unsigned int alpha_test_enable : RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE; + unsigned int alpha_to_mask_enable : RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE; + unsigned int blend_disable : RB_COLORCONTROL_BLEND_DISABLE_SIZE; + unsigned int fog_enable : RB_COLORCONTROL_FOG_ENABLE_SIZE; + unsigned int vs_exports_fog : RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE; + unsigned int rop_code : RB_COLORCONTROL_ROP_CODE_SIZE; + unsigned int dither_mode : RB_COLORCONTROL_DITHER_MODE_SIZE; + unsigned int dither_type : RB_COLORCONTROL_DITHER_TYPE_SIZE; + unsigned int pixel_fog : RB_COLORCONTROL_PIXEL_FOG_SIZE; + unsigned int : 7; + unsigned int alpha_to_mask_offset0 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE; + unsigned int alpha_to_mask_offset1 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE; + unsigned int alpha_to_mask_offset2 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE; + unsigned int alpha_to_mask_offset3 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE; + } rb_colorcontrol_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_colorcontrol_t { + unsigned int alpha_to_mask_offset3 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE; + unsigned int alpha_to_mask_offset2 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE; + unsigned int alpha_to_mask_offset1 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE; + unsigned int alpha_to_mask_offset0 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE; + unsigned int : 7; + unsigned int pixel_fog : RB_COLORCONTROL_PIXEL_FOG_SIZE; + unsigned int dither_type : RB_COLORCONTROL_DITHER_TYPE_SIZE; + unsigned int dither_mode : RB_COLORCONTROL_DITHER_MODE_SIZE; + unsigned int rop_code : RB_COLORCONTROL_ROP_CODE_SIZE; + unsigned int vs_exports_fog : RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE; + unsigned int fog_enable : RB_COLORCONTROL_FOG_ENABLE_SIZE; + unsigned int blend_disable : RB_COLORCONTROL_BLEND_DISABLE_SIZE; + unsigned int alpha_to_mask_enable : RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE; + unsigned int alpha_test_enable : RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE; + unsigned int alpha_func : RB_COLORCONTROL_ALPHA_FUNC_SIZE; + } rb_colorcontrol_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_colorcontrol_t f; +} rb_colorcontrol_u; + + +/* + * RB_MODECONTROL struct + */ + +#define RB_MODECONTROL_EDRAM_MODE_SIZE 3 + +#define RB_MODECONTROL_EDRAM_MODE_SHIFT 0 + +#define RB_MODECONTROL_EDRAM_MODE_MASK 0x00000007 + +#define RB_MODECONTROL_MASK \ + (RB_MODECONTROL_EDRAM_MODE_MASK) + +#define RB_MODECONTROL(edram_mode) \ + ((edram_mode << RB_MODECONTROL_EDRAM_MODE_SHIFT)) + +#define RB_MODECONTROL_GET_EDRAM_MODE(rb_modecontrol) \ + ((rb_modecontrol & RB_MODECONTROL_EDRAM_MODE_MASK) >> RB_MODECONTROL_EDRAM_MODE_SHIFT) + +#define RB_MODECONTROL_SET_EDRAM_MODE(rb_modecontrol_reg, edram_mode) \ + rb_modecontrol_reg = (rb_modecontrol_reg & ~RB_MODECONTROL_EDRAM_MODE_MASK) | (edram_mode << RB_MODECONTROL_EDRAM_MODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_modecontrol_t { + unsigned int edram_mode : RB_MODECONTROL_EDRAM_MODE_SIZE; + unsigned int : 29; + } rb_modecontrol_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_modecontrol_t { + unsigned int : 29; + unsigned int edram_mode : RB_MODECONTROL_EDRAM_MODE_SIZE; + } rb_modecontrol_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_modecontrol_t f; +} rb_modecontrol_u; + + +/* + * RB_COLOR_DEST_MASK struct + */ + +#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE 32 + +#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT 0 + +#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK 0xffffffff + +#define RB_COLOR_DEST_MASK_MASK \ + (RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) + +#define RB_COLOR_DEST_MASK(color_dest_mask) \ + ((color_dest_mask << RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT)) + +#define RB_COLOR_DEST_MASK_GET_COLOR_DEST_MASK(rb_color_dest_mask) \ + ((rb_color_dest_mask & RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) >> RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT) + +#define RB_COLOR_DEST_MASK_SET_COLOR_DEST_MASK(rb_color_dest_mask_reg, color_dest_mask) \ + rb_color_dest_mask_reg = (rb_color_dest_mask_reg & ~RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) | (color_dest_mask << RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_color_dest_mask_t { + unsigned int color_dest_mask : RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE; + } rb_color_dest_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_color_dest_mask_t { + unsigned int color_dest_mask : RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE; + } rb_color_dest_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_color_dest_mask_t f; +} rb_color_dest_mask_u; + + +/* + * RB_COPY_CONTROL struct + */ + +#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE 3 +#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE 1 +#define RB_COPY_CONTROL_CLEAR_MASK_SIZE 4 + +#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT 0 +#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT 3 +#define RB_COPY_CONTROL_CLEAR_MASK_SHIFT 4 + +#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK 0x00000007 +#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK 0x00000008 +#define RB_COPY_CONTROL_CLEAR_MASK_MASK 0x000000f0 + +#define RB_COPY_CONTROL_MASK \ + (RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK | \ + RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK | \ + RB_COPY_CONTROL_CLEAR_MASK_MASK) + +#define RB_COPY_CONTROL(copy_sample_select, depth_clear_enable, clear_mask) \ + ((copy_sample_select << RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT) | \ + (depth_clear_enable << RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT) | \ + (clear_mask << RB_COPY_CONTROL_CLEAR_MASK_SHIFT)) + +#define RB_COPY_CONTROL_GET_COPY_SAMPLE_SELECT(rb_copy_control) \ + ((rb_copy_control & RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK) >> RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT) +#define RB_COPY_CONTROL_GET_DEPTH_CLEAR_ENABLE(rb_copy_control) \ + ((rb_copy_control & RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK) >> RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT) +#define RB_COPY_CONTROL_GET_CLEAR_MASK(rb_copy_control) \ + ((rb_copy_control & RB_COPY_CONTROL_CLEAR_MASK_MASK) >> RB_COPY_CONTROL_CLEAR_MASK_SHIFT) + +#define RB_COPY_CONTROL_SET_COPY_SAMPLE_SELECT(rb_copy_control_reg, copy_sample_select) \ + rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK) | (copy_sample_select << RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT) +#define RB_COPY_CONTROL_SET_DEPTH_CLEAR_ENABLE(rb_copy_control_reg, depth_clear_enable) \ + rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK) | (depth_clear_enable << RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT) +#define RB_COPY_CONTROL_SET_CLEAR_MASK(rb_copy_control_reg, clear_mask) \ + rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_CLEAR_MASK_MASK) | (clear_mask << RB_COPY_CONTROL_CLEAR_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_control_t { + unsigned int copy_sample_select : RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE; + unsigned int depth_clear_enable : RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE; + unsigned int clear_mask : RB_COPY_CONTROL_CLEAR_MASK_SIZE; + unsigned int : 24; + } rb_copy_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_control_t { + unsigned int : 24; + unsigned int clear_mask : RB_COPY_CONTROL_CLEAR_MASK_SIZE; + unsigned int depth_clear_enable : RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE; + unsigned int copy_sample_select : RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE; + } rb_copy_control_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_control_t f; +} rb_copy_control_u; + + +/* + * RB_COPY_DEST_BASE struct + */ + +#define RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE 20 + +#define RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT 12 + +#define RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK 0xfffff000 + +#define RB_COPY_DEST_BASE_MASK \ + (RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) + +#define RB_COPY_DEST_BASE(copy_dest_base) \ + ((copy_dest_base << RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT)) + +#define RB_COPY_DEST_BASE_GET_COPY_DEST_BASE(rb_copy_dest_base) \ + ((rb_copy_dest_base & RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) >> RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT) + +#define RB_COPY_DEST_BASE_SET_COPY_DEST_BASE(rb_copy_dest_base_reg, copy_dest_base) \ + rb_copy_dest_base_reg = (rb_copy_dest_base_reg & ~RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) | (copy_dest_base << RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_dest_base_t { + unsigned int : 12; + unsigned int copy_dest_base : RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE; + } rb_copy_dest_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_dest_base_t { + unsigned int copy_dest_base : RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE; + unsigned int : 12; + } rb_copy_dest_base_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_dest_base_t f; +} rb_copy_dest_base_u; + + +/* + * RB_COPY_DEST_PITCH struct + */ + +#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE 9 + +#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT 0 + +#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK 0x000001ff + +#define RB_COPY_DEST_PITCH_MASK \ + (RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) + +#define RB_COPY_DEST_PITCH(copy_dest_pitch) \ + ((copy_dest_pitch << RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT)) + +#define RB_COPY_DEST_PITCH_GET_COPY_DEST_PITCH(rb_copy_dest_pitch) \ + ((rb_copy_dest_pitch & RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) >> RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT) + +#define RB_COPY_DEST_PITCH_SET_COPY_DEST_PITCH(rb_copy_dest_pitch_reg, copy_dest_pitch) \ + rb_copy_dest_pitch_reg = (rb_copy_dest_pitch_reg & ~RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) | (copy_dest_pitch << RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_dest_pitch_t { + unsigned int copy_dest_pitch : RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE; + unsigned int : 23; + } rb_copy_dest_pitch_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_dest_pitch_t { + unsigned int : 23; + unsigned int copy_dest_pitch : RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE; + } rb_copy_dest_pitch_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_dest_pitch_t f; +} rb_copy_dest_pitch_u; + + +/* + * RB_COPY_DEST_INFO struct + */ + +#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE 3 +#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE 1 +#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE 4 +#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE 2 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE 2 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE 2 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE 1 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE 1 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE 1 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE 1 + +#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT 0 +#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT 3 +#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT 4 +#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT 8 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT 10 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT 12 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT 14 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT 15 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT 16 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT 17 + +#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK 0x00000007 +#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK 0x00000008 +#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK 0x000000f0 +#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK 0x00000300 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK 0x00000c00 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK 0x00003000 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK 0x00004000 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK 0x00008000 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK 0x00010000 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK 0x00020000 + +#define RB_COPY_DEST_INFO_MASK \ + (RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK | \ + RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK | \ + RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK | \ + RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK | \ + RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) + +#define RB_COPY_DEST_INFO(copy_dest_endian, copy_dest_linear, copy_dest_format, copy_dest_swap, copy_dest_dither_mode, copy_dest_dither_type, copy_mask_write_red, copy_mask_write_green, copy_mask_write_blue, copy_mask_write_alpha) \ + ((copy_dest_endian << RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT) | \ + (copy_dest_linear << RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT) | \ + (copy_dest_format << RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT) | \ + (copy_dest_swap << RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT) | \ + (copy_dest_dither_mode << RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT) | \ + (copy_dest_dither_type << RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT) | \ + (copy_mask_write_red << RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT) | \ + (copy_mask_write_green << RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT) | \ + (copy_mask_write_blue << RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT) | \ + (copy_mask_write_alpha << RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT)) + +#define RB_COPY_DEST_INFO_GET_COPY_DEST_ENDIAN(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_LINEAR(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_FORMAT(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_SWAP(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_DITHER_MODE(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_DITHER_TYPE(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_RED(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_GREEN(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_BLUE(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_ALPHA(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT) + +#define RB_COPY_DEST_INFO_SET_COPY_DEST_ENDIAN(rb_copy_dest_info_reg, copy_dest_endian) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK) | (copy_dest_endian << RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_LINEAR(rb_copy_dest_info_reg, copy_dest_linear) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK) | (copy_dest_linear << RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_FORMAT(rb_copy_dest_info_reg, copy_dest_format) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK) | (copy_dest_format << RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_SWAP(rb_copy_dest_info_reg, copy_dest_swap) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK) | (copy_dest_swap << RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_DITHER_MODE(rb_copy_dest_info_reg, copy_dest_dither_mode) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK) | (copy_dest_dither_mode << RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_DITHER_TYPE(rb_copy_dest_info_reg, copy_dest_dither_type) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK) | (copy_dest_dither_type << RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_RED(rb_copy_dest_info_reg, copy_mask_write_red) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK) | (copy_mask_write_red << RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_GREEN(rb_copy_dest_info_reg, copy_mask_write_green) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK) | (copy_mask_write_green << RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_BLUE(rb_copy_dest_info_reg, copy_mask_write_blue) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK) | (copy_mask_write_blue << RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_ALPHA(rb_copy_dest_info_reg, copy_mask_write_alpha) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) | (copy_mask_write_alpha << RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_dest_info_t { + unsigned int copy_dest_endian : RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE; + unsigned int copy_dest_linear : RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE; + unsigned int copy_dest_format : RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE; + unsigned int copy_dest_swap : RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE; + unsigned int copy_dest_dither_mode : RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE; + unsigned int copy_dest_dither_type : RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE; + unsigned int copy_mask_write_red : RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE; + unsigned int copy_mask_write_green : RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE; + unsigned int copy_mask_write_blue : RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE; + unsigned int copy_mask_write_alpha : RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE; + unsigned int : 14; + } rb_copy_dest_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_dest_info_t { + unsigned int : 14; + unsigned int copy_mask_write_alpha : RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE; + unsigned int copy_mask_write_blue : RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE; + unsigned int copy_mask_write_green : RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE; + unsigned int copy_mask_write_red : RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE; + unsigned int copy_dest_dither_type : RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE; + unsigned int copy_dest_dither_mode : RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE; + unsigned int copy_dest_swap : RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE; + unsigned int copy_dest_format : RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE; + unsigned int copy_dest_linear : RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE; + unsigned int copy_dest_endian : RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE; + } rb_copy_dest_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_dest_info_t f; +} rb_copy_dest_info_u; + + +/* + * RB_COPY_DEST_PIXEL_OFFSET struct + */ + +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE 13 +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE 13 + +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT 0 +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT 13 + +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK 0x00001fff +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK 0x03ffe000 + +#define RB_COPY_DEST_PIXEL_OFFSET_MASK \ + (RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK | \ + RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) + +#define RB_COPY_DEST_PIXEL_OFFSET(offset_x, offset_y) \ + ((offset_x << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT) | \ + (offset_y << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT)) + +#define RB_COPY_DEST_PIXEL_OFFSET_GET_OFFSET_X(rb_copy_dest_pixel_offset) \ + ((rb_copy_dest_pixel_offset & RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK) >> RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT) +#define RB_COPY_DEST_PIXEL_OFFSET_GET_OFFSET_Y(rb_copy_dest_pixel_offset) \ + ((rb_copy_dest_pixel_offset & RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) >> RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT) + +#define RB_COPY_DEST_PIXEL_OFFSET_SET_OFFSET_X(rb_copy_dest_pixel_offset_reg, offset_x) \ + rb_copy_dest_pixel_offset_reg = (rb_copy_dest_pixel_offset_reg & ~RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK) | (offset_x << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT) +#define RB_COPY_DEST_PIXEL_OFFSET_SET_OFFSET_Y(rb_copy_dest_pixel_offset_reg, offset_y) \ + rb_copy_dest_pixel_offset_reg = (rb_copy_dest_pixel_offset_reg & ~RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) | (offset_y << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_dest_pixel_offset_t { + unsigned int offset_x : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE; + unsigned int offset_y : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE; + unsigned int : 6; + } rb_copy_dest_pixel_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_dest_pixel_offset_t { + unsigned int : 6; + unsigned int offset_y : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE; + unsigned int offset_x : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE; + } rb_copy_dest_pixel_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_dest_pixel_offset_t f; +} rb_copy_dest_pixel_offset_u; + + +/* + * RB_DEPTH_CLEAR struct + */ + +#define RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE 32 + +#define RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT 0 + +#define RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK 0xffffffff + +#define RB_DEPTH_CLEAR_MASK \ + (RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) + +#define RB_DEPTH_CLEAR(depth_clear) \ + ((depth_clear << RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT)) + +#define RB_DEPTH_CLEAR_GET_DEPTH_CLEAR(rb_depth_clear) \ + ((rb_depth_clear & RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) >> RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT) + +#define RB_DEPTH_CLEAR_SET_DEPTH_CLEAR(rb_depth_clear_reg, depth_clear) \ + rb_depth_clear_reg = (rb_depth_clear_reg & ~RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) | (depth_clear << RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_depth_clear_t { + unsigned int depth_clear : RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE; + } rb_depth_clear_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_depth_clear_t { + unsigned int depth_clear : RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE; + } rb_depth_clear_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_depth_clear_t f; +} rb_depth_clear_u; + + +/* + * RB_SAMPLE_COUNT_CTL struct + */ + +#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE 1 +#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE 1 + +#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT 0 +#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT 1 + +#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK 0x00000001 +#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK 0x00000002 + +#define RB_SAMPLE_COUNT_CTL_MASK \ + (RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK | \ + RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) + +#define RB_SAMPLE_COUNT_CTL(reset_sample_count, copy_sample_count) \ + ((reset_sample_count << RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT) | \ + (copy_sample_count << RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT)) + +#define RB_SAMPLE_COUNT_CTL_GET_RESET_SAMPLE_COUNT(rb_sample_count_ctl) \ + ((rb_sample_count_ctl & RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK) >> RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT) +#define RB_SAMPLE_COUNT_CTL_GET_COPY_SAMPLE_COUNT(rb_sample_count_ctl) \ + ((rb_sample_count_ctl & RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) >> RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT) + +#define RB_SAMPLE_COUNT_CTL_SET_RESET_SAMPLE_COUNT(rb_sample_count_ctl_reg, reset_sample_count) \ + rb_sample_count_ctl_reg = (rb_sample_count_ctl_reg & ~RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK) | (reset_sample_count << RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT) +#define RB_SAMPLE_COUNT_CTL_SET_COPY_SAMPLE_COUNT(rb_sample_count_ctl_reg, copy_sample_count) \ + rb_sample_count_ctl_reg = (rb_sample_count_ctl_reg & ~RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) | (copy_sample_count << RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_sample_count_ctl_t { + unsigned int reset_sample_count : RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE; + unsigned int copy_sample_count : RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE; + unsigned int : 30; + } rb_sample_count_ctl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_sample_count_ctl_t { + unsigned int : 30; + unsigned int copy_sample_count : RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE; + unsigned int reset_sample_count : RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE; + } rb_sample_count_ctl_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_sample_count_ctl_t f; +} rb_sample_count_ctl_u; + + +/* + * RB_SAMPLE_COUNT_ADDR struct + */ + +#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE 32 + +#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT 0 + +#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK 0xffffffff + +#define RB_SAMPLE_COUNT_ADDR_MASK \ + (RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) + +#define RB_SAMPLE_COUNT_ADDR(sample_count_addr) \ + ((sample_count_addr << RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT)) + +#define RB_SAMPLE_COUNT_ADDR_GET_SAMPLE_COUNT_ADDR(rb_sample_count_addr) \ + ((rb_sample_count_addr & RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) >> RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT) + +#define RB_SAMPLE_COUNT_ADDR_SET_SAMPLE_COUNT_ADDR(rb_sample_count_addr_reg, sample_count_addr) \ + rb_sample_count_addr_reg = (rb_sample_count_addr_reg & ~RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) | (sample_count_addr << RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_sample_count_addr_t { + unsigned int sample_count_addr : RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE; + } rb_sample_count_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_sample_count_addr_t { + unsigned int sample_count_addr : RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE; + } rb_sample_count_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_sample_count_addr_t f; +} rb_sample_count_addr_u; + + +/* + * RB_BC_CONTROL struct + */ + +#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE 1 +#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE 2 +#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE 1 +#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE 1 +#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE 1 +#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE 1 +#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE 1 +#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE 5 +#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE 1 +#define RB_BC_CONTROL_CRC_MODE_SIZE 1 +#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE 1 +#define RB_BC_CONTROL_DISABLE_ACCUM_SIZE 1 +#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE 4 +#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE 1 +#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE 4 +#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE 2 +#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE 1 +#define RB_BC_CONTROL_RESERVED9_SIZE 1 +#define RB_BC_CONTROL_RESERVED10_SIZE 1 + +#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT 0 +#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT 1 +#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT 3 +#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT 4 +#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT 5 +#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT 6 +#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT 7 +#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT 8 +#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT 14 +#define RB_BC_CONTROL_CRC_MODE_SHIFT 15 +#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT 16 +#define RB_BC_CONTROL_DISABLE_ACCUM_SHIFT 17 +#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT 18 +#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT 22 +#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT 23 +#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT 27 +#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT 29 +#define RB_BC_CONTROL_RESERVED9_SHIFT 30 +#define RB_BC_CONTROL_RESERVED10_SHIFT 31 + +#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK 0x00000001 +#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK 0x00000006 +#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK 0x00000008 +#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK 0x00000010 +#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK 0x00000020 +#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK 0x00000040 +#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK 0x00000080 +#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK 0x00001f00 +#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK 0x00004000 +#define RB_BC_CONTROL_CRC_MODE_MASK 0x00008000 +#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK 0x00010000 +#define RB_BC_CONTROL_DISABLE_ACCUM_MASK 0x00020000 +#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK 0x003c0000 +#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK 0x00400000 +#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK 0x07800000 +#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK 0x18000000 +#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK 0x20000000 +#define RB_BC_CONTROL_RESERVED9_MASK 0x40000000 +#define RB_BC_CONTROL_RESERVED10_MASK 0x80000000 + +#define RB_BC_CONTROL_MASK \ + (RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK | \ + RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK | \ + RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK | \ + RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK | \ + RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK | \ + RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK | \ + RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK | \ + RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK | \ + RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK | \ + RB_BC_CONTROL_CRC_MODE_MASK | \ + RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK | \ + RB_BC_CONTROL_DISABLE_ACCUM_MASK | \ + RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK | \ + RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK | \ + RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK | \ + RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK | \ + RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK | \ + RB_BC_CONTROL_RESERVED9_MASK | \ + RB_BC_CONTROL_RESERVED10_MASK) + +#define RB_BC_CONTROL(accum_linear_mode_enable, accum_timeout_select, disable_edram_cam, disable_ez_fast_context_switch, disable_ez_null_zcmd_drop, disable_lz_null_zcmd_drop, enable_az_throttle, az_throttle_count, enable_crc_update, crc_mode, disable_sample_counters, disable_accum, accum_alloc_mask, linear_performance_enable, accum_data_fifo_limit, mem_export_timeout_select, mem_export_linear_mode_enable, reserved9, reserved10) \ + ((accum_linear_mode_enable << RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT) | \ + (accum_timeout_select << RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT) | \ + (disable_edram_cam << RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT) | \ + (disable_ez_fast_context_switch << RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT) | \ + (disable_ez_null_zcmd_drop << RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT) | \ + (disable_lz_null_zcmd_drop << RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT) | \ + (enable_az_throttle << RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT) | \ + (az_throttle_count << RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT) | \ + (enable_crc_update << RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT) | \ + (crc_mode << RB_BC_CONTROL_CRC_MODE_SHIFT) | \ + (disable_sample_counters << RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT) | \ + (disable_accum << RB_BC_CONTROL_DISABLE_ACCUM_SHIFT) | \ + (accum_alloc_mask << RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT) | \ + (linear_performance_enable << RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT) | \ + (accum_data_fifo_limit << RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT) | \ + (mem_export_timeout_select << RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT) | \ + (mem_export_linear_mode_enable << RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT) | \ + (reserved9 << RB_BC_CONTROL_RESERVED9_SHIFT) | \ + (reserved10 << RB_BC_CONTROL_RESERVED10_SHIFT)) + +#define RB_BC_CONTROL_GET_ACCUM_LINEAR_MODE_ENABLE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK) >> RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT) +#define RB_BC_CONTROL_GET_ACCUM_TIMEOUT_SELECT(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK) >> RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_EDRAM_CAM(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK) >> RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_EZ_FAST_CONTEXT_SWITCH(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK) >> RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_EZ_NULL_ZCMD_DROP(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK) >> RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_LZ_NULL_ZCMD_DROP(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK) >> RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT) +#define RB_BC_CONTROL_GET_ENABLE_AZ_THROTTLE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK) >> RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT) +#define RB_BC_CONTROL_GET_AZ_THROTTLE_COUNT(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK) >> RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT) +#define RB_BC_CONTROL_GET_ENABLE_CRC_UPDATE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK) >> RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT) +#define RB_BC_CONTROL_GET_CRC_MODE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_CRC_MODE_MASK) >> RB_BC_CONTROL_CRC_MODE_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_SAMPLE_COUNTERS(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK) >> RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_ACCUM(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_ACCUM_MASK) >> RB_BC_CONTROL_DISABLE_ACCUM_SHIFT) +#define RB_BC_CONTROL_GET_ACCUM_ALLOC_MASK(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK) >> RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT) +#define RB_BC_CONTROL_GET_LINEAR_PERFORMANCE_ENABLE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK) >> RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT) +#define RB_BC_CONTROL_GET_ACCUM_DATA_FIFO_LIMIT(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK) >> RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT) +#define RB_BC_CONTROL_GET_MEM_EXPORT_TIMEOUT_SELECT(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK) >> RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT) +#define RB_BC_CONTROL_GET_MEM_EXPORT_LINEAR_MODE_ENABLE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK) >> RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT) +#define RB_BC_CONTROL_GET_RESERVED9(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_RESERVED9_MASK) >> RB_BC_CONTROL_RESERVED9_SHIFT) +#define RB_BC_CONTROL_GET_RESERVED10(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_RESERVED10_MASK) >> RB_BC_CONTROL_RESERVED10_SHIFT) + +#define RB_BC_CONTROL_SET_ACCUM_LINEAR_MODE_ENABLE(rb_bc_control_reg, accum_linear_mode_enable) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK) | (accum_linear_mode_enable << RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT) +#define RB_BC_CONTROL_SET_ACCUM_TIMEOUT_SELECT(rb_bc_control_reg, accum_timeout_select) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK) | (accum_timeout_select << RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_EDRAM_CAM(rb_bc_control_reg, disable_edram_cam) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK) | (disable_edram_cam << RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_EZ_FAST_CONTEXT_SWITCH(rb_bc_control_reg, disable_ez_fast_context_switch) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK) | (disable_ez_fast_context_switch << RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_EZ_NULL_ZCMD_DROP(rb_bc_control_reg, disable_ez_null_zcmd_drop) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK) | (disable_ez_null_zcmd_drop << RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_LZ_NULL_ZCMD_DROP(rb_bc_control_reg, disable_lz_null_zcmd_drop) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK) | (disable_lz_null_zcmd_drop << RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT) +#define RB_BC_CONTROL_SET_ENABLE_AZ_THROTTLE(rb_bc_control_reg, enable_az_throttle) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK) | (enable_az_throttle << RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT) +#define RB_BC_CONTROL_SET_AZ_THROTTLE_COUNT(rb_bc_control_reg, az_throttle_count) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK) | (az_throttle_count << RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT) +#define RB_BC_CONTROL_SET_ENABLE_CRC_UPDATE(rb_bc_control_reg, enable_crc_update) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK) | (enable_crc_update << RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT) +#define RB_BC_CONTROL_SET_CRC_MODE(rb_bc_control_reg, crc_mode) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_CRC_MODE_MASK) | (crc_mode << RB_BC_CONTROL_CRC_MODE_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_SAMPLE_COUNTERS(rb_bc_control_reg, disable_sample_counters) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK) | (disable_sample_counters << RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_ACCUM(rb_bc_control_reg, disable_accum) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_ACCUM_MASK) | (disable_accum << RB_BC_CONTROL_DISABLE_ACCUM_SHIFT) +#define RB_BC_CONTROL_SET_ACCUM_ALLOC_MASK(rb_bc_control_reg, accum_alloc_mask) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK) | (accum_alloc_mask << RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT) +#define RB_BC_CONTROL_SET_LINEAR_PERFORMANCE_ENABLE(rb_bc_control_reg, linear_performance_enable) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK) | (linear_performance_enable << RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT) +#define RB_BC_CONTROL_SET_ACCUM_DATA_FIFO_LIMIT(rb_bc_control_reg, accum_data_fifo_limit) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK) | (accum_data_fifo_limit << RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT) +#define RB_BC_CONTROL_SET_MEM_EXPORT_TIMEOUT_SELECT(rb_bc_control_reg, mem_export_timeout_select) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK) | (mem_export_timeout_select << RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT) +#define RB_BC_CONTROL_SET_MEM_EXPORT_LINEAR_MODE_ENABLE(rb_bc_control_reg, mem_export_linear_mode_enable) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK) | (mem_export_linear_mode_enable << RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT) +#define RB_BC_CONTROL_SET_RESERVED9(rb_bc_control_reg, reserved9) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_RESERVED9_MASK) | (reserved9 << RB_BC_CONTROL_RESERVED9_SHIFT) +#define RB_BC_CONTROL_SET_RESERVED10(rb_bc_control_reg, reserved10) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_RESERVED10_MASK) | (reserved10 << RB_BC_CONTROL_RESERVED10_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_bc_control_t { + unsigned int accum_linear_mode_enable : RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE; + unsigned int accum_timeout_select : RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE; + unsigned int disable_edram_cam : RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE; + unsigned int disable_ez_fast_context_switch : RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE; + unsigned int disable_ez_null_zcmd_drop : RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE; + unsigned int disable_lz_null_zcmd_drop : RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE; + unsigned int enable_az_throttle : RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE; + unsigned int az_throttle_count : RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE; + unsigned int : 1; + unsigned int enable_crc_update : RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE; + unsigned int crc_mode : RB_BC_CONTROL_CRC_MODE_SIZE; + unsigned int disable_sample_counters : RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE; + unsigned int disable_accum : RB_BC_CONTROL_DISABLE_ACCUM_SIZE; + unsigned int accum_alloc_mask : RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE; + unsigned int linear_performance_enable : RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE; + unsigned int accum_data_fifo_limit : RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE; + unsigned int mem_export_timeout_select : RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE; + unsigned int mem_export_linear_mode_enable : RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE; + unsigned int reserved9 : RB_BC_CONTROL_RESERVED9_SIZE; + unsigned int reserved10 : RB_BC_CONTROL_RESERVED10_SIZE; + } rb_bc_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_bc_control_t { + unsigned int reserved10 : RB_BC_CONTROL_RESERVED10_SIZE; + unsigned int reserved9 : RB_BC_CONTROL_RESERVED9_SIZE; + unsigned int mem_export_linear_mode_enable : RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE; + unsigned int mem_export_timeout_select : RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE; + unsigned int accum_data_fifo_limit : RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE; + unsigned int linear_performance_enable : RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE; + unsigned int accum_alloc_mask : RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE; + unsigned int disable_accum : RB_BC_CONTROL_DISABLE_ACCUM_SIZE; + unsigned int disable_sample_counters : RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE; + unsigned int crc_mode : RB_BC_CONTROL_CRC_MODE_SIZE; + unsigned int enable_crc_update : RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE; + unsigned int : 1; + unsigned int az_throttle_count : RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE; + unsigned int enable_az_throttle : RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE; + unsigned int disable_lz_null_zcmd_drop : RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE; + unsigned int disable_ez_null_zcmd_drop : RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE; + unsigned int disable_ez_fast_context_switch : RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE; + unsigned int disable_edram_cam : RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE; + unsigned int accum_timeout_select : RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE; + unsigned int accum_linear_mode_enable : RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE; + } rb_bc_control_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_bc_control_t f; +} rb_bc_control_u; + + +/* + * RB_EDRAM_INFO struct + */ + +#define RB_EDRAM_INFO_EDRAM_SIZE_SIZE 4 +#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE 2 +#define RB_EDRAM_INFO_EDRAM_RANGE_SIZE 18 + +#define RB_EDRAM_INFO_EDRAM_SIZE_SHIFT 0 +#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT 4 +#define RB_EDRAM_INFO_EDRAM_RANGE_SHIFT 14 + +#define RB_EDRAM_INFO_EDRAM_SIZE_MASK 0x0000000f +#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK 0x00000030 +#define RB_EDRAM_INFO_EDRAM_RANGE_MASK 0xffffc000 + +#define RB_EDRAM_INFO_MASK \ + (RB_EDRAM_INFO_EDRAM_SIZE_MASK | \ + RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK | \ + RB_EDRAM_INFO_EDRAM_RANGE_MASK) + +#define RB_EDRAM_INFO(edram_size, edram_mapping_mode, edram_range) \ + ((edram_size << RB_EDRAM_INFO_EDRAM_SIZE_SHIFT) | \ + (edram_mapping_mode << RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT) | \ + (edram_range << RB_EDRAM_INFO_EDRAM_RANGE_SHIFT)) + +#define RB_EDRAM_INFO_GET_EDRAM_SIZE(rb_edram_info) \ + ((rb_edram_info & RB_EDRAM_INFO_EDRAM_SIZE_MASK) >> RB_EDRAM_INFO_EDRAM_SIZE_SHIFT) +#define RB_EDRAM_INFO_GET_EDRAM_MAPPING_MODE(rb_edram_info) \ + ((rb_edram_info & RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK) >> RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT) +#define RB_EDRAM_INFO_GET_EDRAM_RANGE(rb_edram_info) \ + ((rb_edram_info & RB_EDRAM_INFO_EDRAM_RANGE_MASK) >> RB_EDRAM_INFO_EDRAM_RANGE_SHIFT) + +#define RB_EDRAM_INFO_SET_EDRAM_SIZE(rb_edram_info_reg, edram_size) \ + rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_SIZE_MASK) | (edram_size << RB_EDRAM_INFO_EDRAM_SIZE_SHIFT) +#define RB_EDRAM_INFO_SET_EDRAM_MAPPING_MODE(rb_edram_info_reg, edram_mapping_mode) \ + rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK) | (edram_mapping_mode << RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT) +#define RB_EDRAM_INFO_SET_EDRAM_RANGE(rb_edram_info_reg, edram_range) \ + rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_RANGE_MASK) | (edram_range << RB_EDRAM_INFO_EDRAM_RANGE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_edram_info_t { + unsigned int edram_size : RB_EDRAM_INFO_EDRAM_SIZE_SIZE; + unsigned int edram_mapping_mode : RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE; + unsigned int : 8; + unsigned int edram_range : RB_EDRAM_INFO_EDRAM_RANGE_SIZE; + } rb_edram_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_edram_info_t { + unsigned int edram_range : RB_EDRAM_INFO_EDRAM_RANGE_SIZE; + unsigned int : 8; + unsigned int edram_mapping_mode : RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE; + unsigned int edram_size : RB_EDRAM_INFO_EDRAM_SIZE_SIZE; + } rb_edram_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_edram_info_t f; +} rb_edram_info_u; + + +/* + * RB_CRC_RD_PORT struct + */ + +#define RB_CRC_RD_PORT_CRC_DATA_SIZE 32 + +#define RB_CRC_RD_PORT_CRC_DATA_SHIFT 0 + +#define RB_CRC_RD_PORT_CRC_DATA_MASK 0xffffffff + +#define RB_CRC_RD_PORT_MASK \ + (RB_CRC_RD_PORT_CRC_DATA_MASK) + +#define RB_CRC_RD_PORT(crc_data) \ + ((crc_data << RB_CRC_RD_PORT_CRC_DATA_SHIFT)) + +#define RB_CRC_RD_PORT_GET_CRC_DATA(rb_crc_rd_port) \ + ((rb_crc_rd_port & RB_CRC_RD_PORT_CRC_DATA_MASK) >> RB_CRC_RD_PORT_CRC_DATA_SHIFT) + +#define RB_CRC_RD_PORT_SET_CRC_DATA(rb_crc_rd_port_reg, crc_data) \ + rb_crc_rd_port_reg = (rb_crc_rd_port_reg & ~RB_CRC_RD_PORT_CRC_DATA_MASK) | (crc_data << RB_CRC_RD_PORT_CRC_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_crc_rd_port_t { + unsigned int crc_data : RB_CRC_RD_PORT_CRC_DATA_SIZE; + } rb_crc_rd_port_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_crc_rd_port_t { + unsigned int crc_data : RB_CRC_RD_PORT_CRC_DATA_SIZE; + } rb_crc_rd_port_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_crc_rd_port_t f; +} rb_crc_rd_port_u; + + +/* + * RB_CRC_CONTROL struct + */ + +#define RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE 1 + +#define RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT 0 + +#define RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK 0x00000001 + +#define RB_CRC_CONTROL_MASK \ + (RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) + +#define RB_CRC_CONTROL(crc_rd_advance) \ + ((crc_rd_advance << RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT)) + +#define RB_CRC_CONTROL_GET_CRC_RD_ADVANCE(rb_crc_control) \ + ((rb_crc_control & RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) >> RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT) + +#define RB_CRC_CONTROL_SET_CRC_RD_ADVANCE(rb_crc_control_reg, crc_rd_advance) \ + rb_crc_control_reg = (rb_crc_control_reg & ~RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) | (crc_rd_advance << RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_crc_control_t { + unsigned int crc_rd_advance : RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE; + unsigned int : 31; + } rb_crc_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_crc_control_t { + unsigned int : 31; + unsigned int crc_rd_advance : RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE; + } rb_crc_control_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_crc_control_t f; +} rb_crc_control_u; + + +/* + * RB_CRC_MASK struct + */ + +#define RB_CRC_MASK_CRC_MASK_SIZE 32 + +#define RB_CRC_MASK_CRC_MASK_SHIFT 0 + +#define RB_CRC_MASK_CRC_MASK_MASK 0xffffffff + +#define RB_CRC_MASK_MASK \ + (RB_CRC_MASK_CRC_MASK_MASK) + +#define RB_CRC_MASK(crc_mask) \ + ((crc_mask << RB_CRC_MASK_CRC_MASK_SHIFT)) + +#define RB_CRC_MASK_GET_CRC_MASK(rb_crc_mask) \ + ((rb_crc_mask & RB_CRC_MASK_CRC_MASK_MASK) >> RB_CRC_MASK_CRC_MASK_SHIFT) + +#define RB_CRC_MASK_SET_CRC_MASK(rb_crc_mask_reg, crc_mask) \ + rb_crc_mask_reg = (rb_crc_mask_reg & ~RB_CRC_MASK_CRC_MASK_MASK) | (crc_mask << RB_CRC_MASK_CRC_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_crc_mask_t { + unsigned int crc_mask : RB_CRC_MASK_CRC_MASK_SIZE; + } rb_crc_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_crc_mask_t { + unsigned int crc_mask : RB_CRC_MASK_CRC_MASK_SIZE; + } rb_crc_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_crc_mask_t f; +} rb_crc_mask_u; + + +/* + * RB_PERFCOUNTER0_SELECT struct + */ + +#define RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define RB_PERFCOUNTER0_SELECT_MASK \ + (RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define RB_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define RB_PERFCOUNTER0_SELECT_GET_PERF_SEL(rb_perfcounter0_select) \ + ((rb_perfcounter0_select & RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define RB_PERFCOUNTER0_SELECT_SET_PERF_SEL(rb_perfcounter0_select_reg, perf_sel) \ + rb_perfcounter0_select_reg = (rb_perfcounter0_select_reg & ~RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_perfcounter0_select_t { + unsigned int perf_sel : RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } rb_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } rb_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_perfcounter0_select_t f; +} rb_perfcounter0_select_u; + + +/* + * RB_PERFCOUNTER0_LOW struct + */ + +#define RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define RB_PERFCOUNTER0_LOW_MASK \ + (RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define RB_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define RB_PERFCOUNTER0_LOW_GET_PERF_COUNT(rb_perfcounter0_low) \ + ((rb_perfcounter0_low & RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define RB_PERFCOUNTER0_LOW_SET_PERF_COUNT(rb_perfcounter0_low_reg, perf_count) \ + rb_perfcounter0_low_reg = (rb_perfcounter0_low_reg & ~RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_perfcounter0_low_t { + unsigned int perf_count : RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } rb_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_perfcounter0_low_t { + unsigned int perf_count : RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } rb_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_perfcounter0_low_t f; +} rb_perfcounter0_low_u; + + +/* + * RB_PERFCOUNTER0_HI struct + */ + +#define RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define RB_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define RB_PERFCOUNTER0_HI_MASK \ + (RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define RB_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define RB_PERFCOUNTER0_HI_GET_PERF_COUNT(rb_perfcounter0_hi) \ + ((rb_perfcounter0_hi & RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define RB_PERFCOUNTER0_HI_SET_PERF_COUNT(rb_perfcounter0_hi_reg, perf_count) \ + rb_perfcounter0_hi_reg = (rb_perfcounter0_hi_reg & ~RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_perfcounter0_hi_t { + unsigned int perf_count : RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } rb_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } rb_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_perfcounter0_hi_t f; +} rb_perfcounter0_hi_u; + + +/* + * RB_TOTAL_SAMPLES struct + */ + +#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE 32 + +#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT 0 + +#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK 0xffffffff + +#define RB_TOTAL_SAMPLES_MASK \ + (RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) + +#define RB_TOTAL_SAMPLES(total_samples) \ + ((total_samples << RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT)) + +#define RB_TOTAL_SAMPLES_GET_TOTAL_SAMPLES(rb_total_samples) \ + ((rb_total_samples & RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) >> RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT) + +#define RB_TOTAL_SAMPLES_SET_TOTAL_SAMPLES(rb_total_samples_reg, total_samples) \ + rb_total_samples_reg = (rb_total_samples_reg & ~RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) | (total_samples << RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_total_samples_t { + unsigned int total_samples : RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE; + } rb_total_samples_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_total_samples_t { + unsigned int total_samples : RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE; + } rb_total_samples_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_total_samples_t f; +} rb_total_samples_u; + + +/* + * RB_ZPASS_SAMPLES struct + */ + +#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE 32 + +#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT 0 + +#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK 0xffffffff + +#define RB_ZPASS_SAMPLES_MASK \ + (RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) + +#define RB_ZPASS_SAMPLES(zpass_samples) \ + ((zpass_samples << RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT)) + +#define RB_ZPASS_SAMPLES_GET_ZPASS_SAMPLES(rb_zpass_samples) \ + ((rb_zpass_samples & RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) >> RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT) + +#define RB_ZPASS_SAMPLES_SET_ZPASS_SAMPLES(rb_zpass_samples_reg, zpass_samples) \ + rb_zpass_samples_reg = (rb_zpass_samples_reg & ~RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) | (zpass_samples << RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_zpass_samples_t { + unsigned int zpass_samples : RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE; + } rb_zpass_samples_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_zpass_samples_t { + unsigned int zpass_samples : RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE; + } rb_zpass_samples_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_zpass_samples_t f; +} rb_zpass_samples_u; + + +/* + * RB_ZFAIL_SAMPLES struct + */ + +#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE 32 + +#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT 0 + +#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK 0xffffffff + +#define RB_ZFAIL_SAMPLES_MASK \ + (RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) + +#define RB_ZFAIL_SAMPLES(zfail_samples) \ + ((zfail_samples << RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT)) + +#define RB_ZFAIL_SAMPLES_GET_ZFAIL_SAMPLES(rb_zfail_samples) \ + ((rb_zfail_samples & RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) >> RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT) + +#define RB_ZFAIL_SAMPLES_SET_ZFAIL_SAMPLES(rb_zfail_samples_reg, zfail_samples) \ + rb_zfail_samples_reg = (rb_zfail_samples_reg & ~RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) | (zfail_samples << RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_zfail_samples_t { + unsigned int zfail_samples : RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE; + } rb_zfail_samples_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_zfail_samples_t { + unsigned int zfail_samples : RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE; + } rb_zfail_samples_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_zfail_samples_t f; +} rb_zfail_samples_u; + + +/* + * RB_SFAIL_SAMPLES struct + */ + +#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE 32 + +#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT 0 + +#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK 0xffffffff + +#define RB_SFAIL_SAMPLES_MASK \ + (RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) + +#define RB_SFAIL_SAMPLES(sfail_samples) \ + ((sfail_samples << RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT)) + +#define RB_SFAIL_SAMPLES_GET_SFAIL_SAMPLES(rb_sfail_samples) \ + ((rb_sfail_samples & RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) >> RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT) + +#define RB_SFAIL_SAMPLES_SET_SFAIL_SAMPLES(rb_sfail_samples_reg, sfail_samples) \ + rb_sfail_samples_reg = (rb_sfail_samples_reg & ~RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) | (sfail_samples << RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_sfail_samples_t { + unsigned int sfail_samples : RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE; + } rb_sfail_samples_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_sfail_samples_t { + unsigned int sfail_samples : RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE; + } rb_sfail_samples_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_sfail_samples_t f; +} rb_sfail_samples_u; + + +/* + * RB_DEBUG_0 struct + */ + +#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_Z1_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_Z0_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_C1_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_C0_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_Z1_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_Z0_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_C1_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_C0_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE 1 +#define RB_DEBUG_0_C_SX_LAT_FULL_SIZE 1 +#define RB_DEBUG_0_C_SX_CMD_FULL_SIZE 1 +#define RB_DEBUG_0_C_EZ_TILE_FULL_SIZE 1 +#define RB_DEBUG_0_C_REQ_FULL_SIZE 1 +#define RB_DEBUG_0_C_MASK_FULL_SIZE 1 +#define RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE 1 + +#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT 0 +#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT 1 +#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT 2 +#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT 3 +#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT 4 +#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT 5 +#define RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT 6 +#define RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT 7 +#define RB_DEBUG_0_RDREQ_C1_FULL_SHIFT 8 +#define RB_DEBUG_0_RDREQ_C0_FULL_SHIFT 9 +#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT 10 +#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT 11 +#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT 12 +#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT 13 +#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT 14 +#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT 15 +#define RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT 16 +#define RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT 17 +#define RB_DEBUG_0_WRREQ_C1_FULL_SHIFT 18 +#define RB_DEBUG_0_WRREQ_C0_FULL_SHIFT 19 +#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT 20 +#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT 21 +#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT 22 +#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT 23 +#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT 24 +#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT 25 +#define RB_DEBUG_0_C_SX_LAT_FULL_SHIFT 26 +#define RB_DEBUG_0_C_SX_CMD_FULL_SHIFT 27 +#define RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT 28 +#define RB_DEBUG_0_C_REQ_FULL_SHIFT 29 +#define RB_DEBUG_0_C_MASK_FULL_SHIFT 30 +#define RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT 31 + +#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK 0x00000001 +#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK 0x00000002 +#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK 0x00000004 +#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK 0x00000008 +#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK 0x00000010 +#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK 0x00000020 +#define RB_DEBUG_0_RDREQ_Z1_FULL_MASK 0x00000040 +#define RB_DEBUG_0_RDREQ_Z0_FULL_MASK 0x00000080 +#define RB_DEBUG_0_RDREQ_C1_FULL_MASK 0x00000100 +#define RB_DEBUG_0_RDREQ_C0_FULL_MASK 0x00000200 +#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK 0x00000400 +#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK 0x00000800 +#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK 0x00001000 +#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK 0x00002000 +#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK 0x00004000 +#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK 0x00008000 +#define RB_DEBUG_0_WRREQ_Z1_FULL_MASK 0x00010000 +#define RB_DEBUG_0_WRREQ_Z0_FULL_MASK 0x00020000 +#define RB_DEBUG_0_WRREQ_C1_FULL_MASK 0x00040000 +#define RB_DEBUG_0_WRREQ_C0_FULL_MASK 0x00080000 +#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK 0x00100000 +#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK 0x00200000 +#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK 0x00400000 +#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK 0x00800000 +#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK 0x01000000 +#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK 0x02000000 +#define RB_DEBUG_0_C_SX_LAT_FULL_MASK 0x04000000 +#define RB_DEBUG_0_C_SX_CMD_FULL_MASK 0x08000000 +#define RB_DEBUG_0_C_EZ_TILE_FULL_MASK 0x10000000 +#define RB_DEBUG_0_C_REQ_FULL_MASK 0x20000000 +#define RB_DEBUG_0_C_MASK_FULL_MASK 0x40000000 +#define RB_DEBUG_0_EZ_INFSAMP_FULL_MASK 0x80000000 + +#define RB_DEBUG_0_MASK \ + (RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK | \ + RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK | \ + RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK | \ + RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK | \ + RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK | \ + RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK | \ + RB_DEBUG_0_RDREQ_Z1_FULL_MASK | \ + RB_DEBUG_0_RDREQ_Z0_FULL_MASK | \ + RB_DEBUG_0_RDREQ_C1_FULL_MASK | \ + RB_DEBUG_0_RDREQ_C0_FULL_MASK | \ + RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK | \ + RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK | \ + RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK | \ + RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK | \ + RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK | \ + RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK | \ + RB_DEBUG_0_WRREQ_Z1_FULL_MASK | \ + RB_DEBUG_0_WRREQ_Z0_FULL_MASK | \ + RB_DEBUG_0_WRREQ_C1_FULL_MASK | \ + RB_DEBUG_0_WRREQ_C0_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK | \ + RB_DEBUG_0_C_SX_LAT_FULL_MASK | \ + RB_DEBUG_0_C_SX_CMD_FULL_MASK | \ + RB_DEBUG_0_C_EZ_TILE_FULL_MASK | \ + RB_DEBUG_0_C_REQ_FULL_MASK | \ + RB_DEBUG_0_C_MASK_FULL_MASK | \ + RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) + +#define RB_DEBUG_0(rdreq_ctl_z1_pre_full, rdreq_ctl_z0_pre_full, rdreq_ctl_c1_pre_full, rdreq_ctl_c0_pre_full, rdreq_e1_ordering_full, rdreq_e0_ordering_full, rdreq_z1_full, rdreq_z0_full, rdreq_c1_full, rdreq_c0_full, wrreq_e1_macro_hi_full, wrreq_e1_macro_lo_full, wrreq_e0_macro_hi_full, wrreq_e0_macro_lo_full, wrreq_c_we_hi_full, wrreq_c_we_lo_full, wrreq_z1_full, wrreq_z0_full, wrreq_c1_full, wrreq_c0_full, cmdfifo_z1_hold_full, cmdfifo_z0_hold_full, cmdfifo_c1_hold_full, cmdfifo_c0_hold_full, cmdfifo_z_ordering_full, cmdfifo_c_ordering_full, c_sx_lat_full, c_sx_cmd_full, c_ez_tile_full, c_req_full, c_mask_full, ez_infsamp_full) \ + ((rdreq_ctl_z1_pre_full << RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT) | \ + (rdreq_ctl_z0_pre_full << RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT) | \ + (rdreq_ctl_c1_pre_full << RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT) | \ + (rdreq_ctl_c0_pre_full << RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT) | \ + (rdreq_e1_ordering_full << RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT) | \ + (rdreq_e0_ordering_full << RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT) | \ + (rdreq_z1_full << RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT) | \ + (rdreq_z0_full << RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT) | \ + (rdreq_c1_full << RB_DEBUG_0_RDREQ_C1_FULL_SHIFT) | \ + (rdreq_c0_full << RB_DEBUG_0_RDREQ_C0_FULL_SHIFT) | \ + (wrreq_e1_macro_hi_full << RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT) | \ + (wrreq_e1_macro_lo_full << RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT) | \ + (wrreq_e0_macro_hi_full << RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT) | \ + (wrreq_e0_macro_lo_full << RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT) | \ + (wrreq_c_we_hi_full << RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT) | \ + (wrreq_c_we_lo_full << RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT) | \ + (wrreq_z1_full << RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT) | \ + (wrreq_z0_full << RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT) | \ + (wrreq_c1_full << RB_DEBUG_0_WRREQ_C1_FULL_SHIFT) | \ + (wrreq_c0_full << RB_DEBUG_0_WRREQ_C0_FULL_SHIFT) | \ + (cmdfifo_z1_hold_full << RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT) | \ + (cmdfifo_z0_hold_full << RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT) | \ + (cmdfifo_c1_hold_full << RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT) | \ + (cmdfifo_c0_hold_full << RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT) | \ + (cmdfifo_z_ordering_full << RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT) | \ + (cmdfifo_c_ordering_full << RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT) | \ + (c_sx_lat_full << RB_DEBUG_0_C_SX_LAT_FULL_SHIFT) | \ + (c_sx_cmd_full << RB_DEBUG_0_C_SX_CMD_FULL_SHIFT) | \ + (c_ez_tile_full << RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT) | \ + (c_req_full << RB_DEBUG_0_C_REQ_FULL_SHIFT) | \ + (c_mask_full << RB_DEBUG_0_C_MASK_FULL_SHIFT) | \ + (ez_infsamp_full << RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT)) + +#define RB_DEBUG_0_GET_RDREQ_CTL_Z1_PRE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_CTL_Z0_PRE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_CTL_C1_PRE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_CTL_C0_PRE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_E1_ORDERING_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK) >> RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_E0_ORDERING_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK) >> RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_Z1_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_Z1_FULL_MASK) >> RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_Z0_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_Z0_FULL_MASK) >> RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_C1_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_C1_FULL_MASK) >> RB_DEBUG_0_RDREQ_C1_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_C0_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_C0_FULL_MASK) >> RB_DEBUG_0_RDREQ_C0_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_E1_MACRO_HI_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_E1_MACRO_LO_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_E0_MACRO_HI_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_E0_MACRO_LO_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_C_WE_HI_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_C_WE_LO_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_Z1_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_Z1_FULL_MASK) >> RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_Z0_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_Z0_FULL_MASK) >> RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_C1_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_C1_FULL_MASK) >> RB_DEBUG_0_WRREQ_C1_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_C0_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_C0_FULL_MASK) >> RB_DEBUG_0_WRREQ_C0_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_Z1_HOLD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_Z0_HOLD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_C1_HOLD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_C0_HOLD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_Z_ORDERING_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_C_ORDERING_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_SX_LAT_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_SX_LAT_FULL_MASK) >> RB_DEBUG_0_C_SX_LAT_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_SX_CMD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_SX_CMD_FULL_MASK) >> RB_DEBUG_0_C_SX_CMD_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_EZ_TILE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_EZ_TILE_FULL_MASK) >> RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_REQ_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_REQ_FULL_MASK) >> RB_DEBUG_0_C_REQ_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_MASK_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_MASK_FULL_MASK) >> RB_DEBUG_0_C_MASK_FULL_SHIFT) +#define RB_DEBUG_0_GET_EZ_INFSAMP_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) >> RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT) + +#define RB_DEBUG_0_SET_RDREQ_CTL_Z1_PRE_FULL(rb_debug_0_reg, rdreq_ctl_z1_pre_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK) | (rdreq_ctl_z1_pre_full << RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_CTL_Z0_PRE_FULL(rb_debug_0_reg, rdreq_ctl_z0_pre_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK) | (rdreq_ctl_z0_pre_full << RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_CTL_C1_PRE_FULL(rb_debug_0_reg, rdreq_ctl_c1_pre_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK) | (rdreq_ctl_c1_pre_full << RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_CTL_C0_PRE_FULL(rb_debug_0_reg, rdreq_ctl_c0_pre_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK) | (rdreq_ctl_c0_pre_full << RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_E1_ORDERING_FULL(rb_debug_0_reg, rdreq_e1_ordering_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK) | (rdreq_e1_ordering_full << RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_E0_ORDERING_FULL(rb_debug_0_reg, rdreq_e0_ordering_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK) | (rdreq_e0_ordering_full << RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_Z1_FULL(rb_debug_0_reg, rdreq_z1_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_Z1_FULL_MASK) | (rdreq_z1_full << RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_Z0_FULL(rb_debug_0_reg, rdreq_z0_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_Z0_FULL_MASK) | (rdreq_z0_full << RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_C1_FULL(rb_debug_0_reg, rdreq_c1_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_C1_FULL_MASK) | (rdreq_c1_full << RB_DEBUG_0_RDREQ_C1_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_C0_FULL(rb_debug_0_reg, rdreq_c0_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_C0_FULL_MASK) | (rdreq_c0_full << RB_DEBUG_0_RDREQ_C0_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_E1_MACRO_HI_FULL(rb_debug_0_reg, wrreq_e1_macro_hi_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK) | (wrreq_e1_macro_hi_full << RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_E1_MACRO_LO_FULL(rb_debug_0_reg, wrreq_e1_macro_lo_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK) | (wrreq_e1_macro_lo_full << RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_E0_MACRO_HI_FULL(rb_debug_0_reg, wrreq_e0_macro_hi_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK) | (wrreq_e0_macro_hi_full << RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_E0_MACRO_LO_FULL(rb_debug_0_reg, wrreq_e0_macro_lo_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK) | (wrreq_e0_macro_lo_full << RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_C_WE_HI_FULL(rb_debug_0_reg, wrreq_c_we_hi_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK) | (wrreq_c_we_hi_full << RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_C_WE_LO_FULL(rb_debug_0_reg, wrreq_c_we_lo_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK) | (wrreq_c_we_lo_full << RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_Z1_FULL(rb_debug_0_reg, wrreq_z1_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_Z1_FULL_MASK) | (wrreq_z1_full << RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_Z0_FULL(rb_debug_0_reg, wrreq_z0_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_Z0_FULL_MASK) | (wrreq_z0_full << RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_C1_FULL(rb_debug_0_reg, wrreq_c1_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C1_FULL_MASK) | (wrreq_c1_full << RB_DEBUG_0_WRREQ_C1_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_C0_FULL(rb_debug_0_reg, wrreq_c0_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C0_FULL_MASK) | (wrreq_c0_full << RB_DEBUG_0_WRREQ_C0_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_Z1_HOLD_FULL(rb_debug_0_reg, cmdfifo_z1_hold_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK) | (cmdfifo_z1_hold_full << RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_Z0_HOLD_FULL(rb_debug_0_reg, cmdfifo_z0_hold_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK) | (cmdfifo_z0_hold_full << RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_C1_HOLD_FULL(rb_debug_0_reg, cmdfifo_c1_hold_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK) | (cmdfifo_c1_hold_full << RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_C0_HOLD_FULL(rb_debug_0_reg, cmdfifo_c0_hold_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK) | (cmdfifo_c0_hold_full << RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_Z_ORDERING_FULL(rb_debug_0_reg, cmdfifo_z_ordering_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK) | (cmdfifo_z_ordering_full << RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_C_ORDERING_FULL(rb_debug_0_reg, cmdfifo_c_ordering_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK) | (cmdfifo_c_ordering_full << RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_SX_LAT_FULL(rb_debug_0_reg, c_sx_lat_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_SX_LAT_FULL_MASK) | (c_sx_lat_full << RB_DEBUG_0_C_SX_LAT_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_SX_CMD_FULL(rb_debug_0_reg, c_sx_cmd_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_SX_CMD_FULL_MASK) | (c_sx_cmd_full << RB_DEBUG_0_C_SX_CMD_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_EZ_TILE_FULL(rb_debug_0_reg, c_ez_tile_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_EZ_TILE_FULL_MASK) | (c_ez_tile_full << RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_REQ_FULL(rb_debug_0_reg, c_req_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_REQ_FULL_MASK) | (c_req_full << RB_DEBUG_0_C_REQ_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_MASK_FULL(rb_debug_0_reg, c_mask_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_MASK_FULL_MASK) | (c_mask_full << RB_DEBUG_0_C_MASK_FULL_SHIFT) +#define RB_DEBUG_0_SET_EZ_INFSAMP_FULL(rb_debug_0_reg, ez_infsamp_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) | (ez_infsamp_full << RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_0_t { + unsigned int rdreq_ctl_z1_pre_full : RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE; + unsigned int rdreq_ctl_z0_pre_full : RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE; + unsigned int rdreq_ctl_c1_pre_full : RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE; + unsigned int rdreq_ctl_c0_pre_full : RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE; + unsigned int rdreq_e1_ordering_full : RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE; + unsigned int rdreq_e0_ordering_full : RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE; + unsigned int rdreq_z1_full : RB_DEBUG_0_RDREQ_Z1_FULL_SIZE; + unsigned int rdreq_z0_full : RB_DEBUG_0_RDREQ_Z0_FULL_SIZE; + unsigned int rdreq_c1_full : RB_DEBUG_0_RDREQ_C1_FULL_SIZE; + unsigned int rdreq_c0_full : RB_DEBUG_0_RDREQ_C0_FULL_SIZE; + unsigned int wrreq_e1_macro_hi_full : RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE; + unsigned int wrreq_e1_macro_lo_full : RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE; + unsigned int wrreq_e0_macro_hi_full : RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE; + unsigned int wrreq_e0_macro_lo_full : RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE; + unsigned int wrreq_c_we_hi_full : RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE; + unsigned int wrreq_c_we_lo_full : RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE; + unsigned int wrreq_z1_full : RB_DEBUG_0_WRREQ_Z1_FULL_SIZE; + unsigned int wrreq_z0_full : RB_DEBUG_0_WRREQ_Z0_FULL_SIZE; + unsigned int wrreq_c1_full : RB_DEBUG_0_WRREQ_C1_FULL_SIZE; + unsigned int wrreq_c0_full : RB_DEBUG_0_WRREQ_C0_FULL_SIZE; + unsigned int cmdfifo_z1_hold_full : RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE; + unsigned int cmdfifo_z0_hold_full : RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE; + unsigned int cmdfifo_c1_hold_full : RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE; + unsigned int cmdfifo_c0_hold_full : RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE; + unsigned int cmdfifo_z_ordering_full : RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE; + unsigned int cmdfifo_c_ordering_full : RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE; + unsigned int c_sx_lat_full : RB_DEBUG_0_C_SX_LAT_FULL_SIZE; + unsigned int c_sx_cmd_full : RB_DEBUG_0_C_SX_CMD_FULL_SIZE; + unsigned int c_ez_tile_full : RB_DEBUG_0_C_EZ_TILE_FULL_SIZE; + unsigned int c_req_full : RB_DEBUG_0_C_REQ_FULL_SIZE; + unsigned int c_mask_full : RB_DEBUG_0_C_MASK_FULL_SIZE; + unsigned int ez_infsamp_full : RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE; + } rb_debug_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_0_t { + unsigned int ez_infsamp_full : RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE; + unsigned int c_mask_full : RB_DEBUG_0_C_MASK_FULL_SIZE; + unsigned int c_req_full : RB_DEBUG_0_C_REQ_FULL_SIZE; + unsigned int c_ez_tile_full : RB_DEBUG_0_C_EZ_TILE_FULL_SIZE; + unsigned int c_sx_cmd_full : RB_DEBUG_0_C_SX_CMD_FULL_SIZE; + unsigned int c_sx_lat_full : RB_DEBUG_0_C_SX_LAT_FULL_SIZE; + unsigned int cmdfifo_c_ordering_full : RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE; + unsigned int cmdfifo_z_ordering_full : RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE; + unsigned int cmdfifo_c0_hold_full : RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE; + unsigned int cmdfifo_c1_hold_full : RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE; + unsigned int cmdfifo_z0_hold_full : RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE; + unsigned int cmdfifo_z1_hold_full : RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE; + unsigned int wrreq_c0_full : RB_DEBUG_0_WRREQ_C0_FULL_SIZE; + unsigned int wrreq_c1_full : RB_DEBUG_0_WRREQ_C1_FULL_SIZE; + unsigned int wrreq_z0_full : RB_DEBUG_0_WRREQ_Z0_FULL_SIZE; + unsigned int wrreq_z1_full : RB_DEBUG_0_WRREQ_Z1_FULL_SIZE; + unsigned int wrreq_c_we_lo_full : RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE; + unsigned int wrreq_c_we_hi_full : RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE; + unsigned int wrreq_e0_macro_lo_full : RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE; + unsigned int wrreq_e0_macro_hi_full : RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE; + unsigned int wrreq_e1_macro_lo_full : RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE; + unsigned int wrreq_e1_macro_hi_full : RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE; + unsigned int rdreq_c0_full : RB_DEBUG_0_RDREQ_C0_FULL_SIZE; + unsigned int rdreq_c1_full : RB_DEBUG_0_RDREQ_C1_FULL_SIZE; + unsigned int rdreq_z0_full : RB_DEBUG_0_RDREQ_Z0_FULL_SIZE; + unsigned int rdreq_z1_full : RB_DEBUG_0_RDREQ_Z1_FULL_SIZE; + unsigned int rdreq_e0_ordering_full : RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE; + unsigned int rdreq_e1_ordering_full : RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE; + unsigned int rdreq_ctl_c0_pre_full : RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE; + unsigned int rdreq_ctl_c1_pre_full : RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE; + unsigned int rdreq_ctl_z0_pre_full : RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE; + unsigned int rdreq_ctl_z1_pre_full : RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE; + } rb_debug_0_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_0_t f; +} rb_debug_0_u; + + +/* + * RB_DEBUG_1 struct + */ + +#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_REQ_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_MASK_EMPTY_SIZE 1 +#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE 1 + +#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT 0 +#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT 1 +#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT 2 +#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT 3 +#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT 4 +#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT 5 +#define RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT 6 +#define RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT 7 +#define RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT 8 +#define RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT 9 +#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT 10 +#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT 11 +#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT 12 +#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT 13 +#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT 14 +#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT 15 +#define RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT 16 +#define RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT 17 +#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT 18 +#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT 19 +#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT 20 +#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT 21 +#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT 22 +#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT 23 +#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT 24 +#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT 25 +#define RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT 26 +#define RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT 27 +#define RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT 28 +#define RB_DEBUG_1_C_REQ_EMPTY_SHIFT 29 +#define RB_DEBUG_1_C_MASK_EMPTY_SHIFT 30 +#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT 31 + +#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK 0x00000001 +#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK 0x00000002 +#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK 0x00000004 +#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK 0x00000008 +#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK 0x00000010 +#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK 0x00000020 +#define RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK 0x00000040 +#define RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK 0x00000080 +#define RB_DEBUG_1_RDREQ_C1_EMPTY_MASK 0x00000100 +#define RB_DEBUG_1_RDREQ_C0_EMPTY_MASK 0x00000200 +#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK 0x00000400 +#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK 0x00000800 +#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK 0x00001000 +#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK 0x00002000 +#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK 0x00004000 +#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK 0x00008000 +#define RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK 0x00010000 +#define RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK 0x00020000 +#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK 0x00040000 +#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK 0x00080000 +#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK 0x00100000 +#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK 0x00200000 +#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK 0x00400000 +#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK 0x00800000 +#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK 0x01000000 +#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK 0x02000000 +#define RB_DEBUG_1_C_SX_LAT_EMPTY_MASK 0x04000000 +#define RB_DEBUG_1_C_SX_CMD_EMPTY_MASK 0x08000000 +#define RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK 0x10000000 +#define RB_DEBUG_1_C_REQ_EMPTY_MASK 0x20000000 +#define RB_DEBUG_1_C_MASK_EMPTY_MASK 0x40000000 +#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK 0x80000000 + +#define RB_DEBUG_1_MASK \ + (RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_C1_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_C0_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK | \ + RB_DEBUG_1_C_SX_LAT_EMPTY_MASK | \ + RB_DEBUG_1_C_SX_CMD_EMPTY_MASK | \ + RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK | \ + RB_DEBUG_1_C_REQ_EMPTY_MASK | \ + RB_DEBUG_1_C_MASK_EMPTY_MASK | \ + RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) + +#define RB_DEBUG_1(rdreq_z1_cmd_empty, rdreq_z0_cmd_empty, rdreq_c1_cmd_empty, rdreq_c0_cmd_empty, rdreq_e1_ordering_empty, rdreq_e0_ordering_empty, rdreq_z1_empty, rdreq_z0_empty, rdreq_c1_empty, rdreq_c0_empty, wrreq_e1_macro_hi_empty, wrreq_e1_macro_lo_empty, wrreq_e0_macro_hi_empty, wrreq_e0_macro_lo_empty, wrreq_c_we_hi_empty, wrreq_c_we_lo_empty, wrreq_z1_empty, wrreq_z0_empty, wrreq_c1_pre_empty, wrreq_c0_pre_empty, cmdfifo_z1_hold_empty, cmdfifo_z0_hold_empty, cmdfifo_c1_hold_empty, cmdfifo_c0_hold_empty, cmdfifo_z_ordering_empty, cmdfifo_c_ordering_empty, c_sx_lat_empty, c_sx_cmd_empty, c_ez_tile_empty, c_req_empty, c_mask_empty, ez_infsamp_empty) \ + ((rdreq_z1_cmd_empty << RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT) | \ + (rdreq_z0_cmd_empty << RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT) | \ + (rdreq_c1_cmd_empty << RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT) | \ + (rdreq_c0_cmd_empty << RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT) | \ + (rdreq_e1_ordering_empty << RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT) | \ + (rdreq_e0_ordering_empty << RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT) | \ + (rdreq_z1_empty << RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT) | \ + (rdreq_z0_empty << RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT) | \ + (rdreq_c1_empty << RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT) | \ + (rdreq_c0_empty << RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT) | \ + (wrreq_e1_macro_hi_empty << RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT) | \ + (wrreq_e1_macro_lo_empty << RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT) | \ + (wrreq_e0_macro_hi_empty << RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT) | \ + (wrreq_e0_macro_lo_empty << RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT) | \ + (wrreq_c_we_hi_empty << RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT) | \ + (wrreq_c_we_lo_empty << RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT) | \ + (wrreq_z1_empty << RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT) | \ + (wrreq_z0_empty << RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT) | \ + (wrreq_c1_pre_empty << RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT) | \ + (wrreq_c0_pre_empty << RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT) | \ + (cmdfifo_z1_hold_empty << RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT) | \ + (cmdfifo_z0_hold_empty << RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT) | \ + (cmdfifo_c1_hold_empty << RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT) | \ + (cmdfifo_c0_hold_empty << RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT) | \ + (cmdfifo_z_ordering_empty << RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT) | \ + (cmdfifo_c_ordering_empty << RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT) | \ + (c_sx_lat_empty << RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT) | \ + (c_sx_cmd_empty << RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT) | \ + (c_ez_tile_empty << RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT) | \ + (c_req_empty << RB_DEBUG_1_C_REQ_EMPTY_SHIFT) | \ + (c_mask_empty << RB_DEBUG_1_C_MASK_EMPTY_SHIFT) | \ + (ez_infsamp_empty << RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT)) + +#define RB_DEBUG_1_GET_RDREQ_Z1_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_Z0_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_C1_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_C0_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_E1_ORDERING_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_E0_ORDERING_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_Z1_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_Z0_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_C1_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_C1_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_C0_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_C0_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_E1_MACRO_HI_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_E1_MACRO_LO_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_E0_MACRO_HI_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_E0_MACRO_LO_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_C_WE_HI_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_C_WE_LO_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_Z1_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_Z0_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_C1_PRE_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_C0_PRE_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_Z1_HOLD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_Z0_HOLD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_C1_HOLD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_C0_HOLD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_Z_ORDERING_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_C_ORDERING_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_SX_LAT_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_SX_LAT_EMPTY_MASK) >> RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_SX_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_SX_CMD_EMPTY_MASK) >> RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_EZ_TILE_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK) >> RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_REQ_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_REQ_EMPTY_MASK) >> RB_DEBUG_1_C_REQ_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_MASK_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_MASK_EMPTY_MASK) >> RB_DEBUG_1_C_MASK_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_EZ_INFSAMP_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) >> RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT) + +#define RB_DEBUG_1_SET_RDREQ_Z1_CMD_EMPTY(rb_debug_1_reg, rdreq_z1_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK) | (rdreq_z1_cmd_empty << RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_Z0_CMD_EMPTY(rb_debug_1_reg, rdreq_z0_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK) | (rdreq_z0_cmd_empty << RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_C1_CMD_EMPTY(rb_debug_1_reg, rdreq_c1_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK) | (rdreq_c1_cmd_empty << RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_C0_CMD_EMPTY(rb_debug_1_reg, rdreq_c0_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK) | (rdreq_c0_cmd_empty << RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_E1_ORDERING_EMPTY(rb_debug_1_reg, rdreq_e1_ordering_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK) | (rdreq_e1_ordering_empty << RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_E0_ORDERING_EMPTY(rb_debug_1_reg, rdreq_e0_ordering_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK) | (rdreq_e0_ordering_empty << RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_Z1_EMPTY(rb_debug_1_reg, rdreq_z1_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK) | (rdreq_z1_empty << RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_Z0_EMPTY(rb_debug_1_reg, rdreq_z0_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK) | (rdreq_z0_empty << RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_C1_EMPTY(rb_debug_1_reg, rdreq_c1_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C1_EMPTY_MASK) | (rdreq_c1_empty << RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_C0_EMPTY(rb_debug_1_reg, rdreq_c0_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C0_EMPTY_MASK) | (rdreq_c0_empty << RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_E1_MACRO_HI_EMPTY(rb_debug_1_reg, wrreq_e1_macro_hi_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK) | (wrreq_e1_macro_hi_empty << RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_E1_MACRO_LO_EMPTY(rb_debug_1_reg, wrreq_e1_macro_lo_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK) | (wrreq_e1_macro_lo_empty << RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_E0_MACRO_HI_EMPTY(rb_debug_1_reg, wrreq_e0_macro_hi_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK) | (wrreq_e0_macro_hi_empty << RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_E0_MACRO_LO_EMPTY(rb_debug_1_reg, wrreq_e0_macro_lo_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK) | (wrreq_e0_macro_lo_empty << RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_C_WE_HI_EMPTY(rb_debug_1_reg, wrreq_c_we_hi_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK) | (wrreq_c_we_hi_empty << RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_C_WE_LO_EMPTY(rb_debug_1_reg, wrreq_c_we_lo_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK) | (wrreq_c_we_lo_empty << RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_Z1_EMPTY(rb_debug_1_reg, wrreq_z1_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK) | (wrreq_z1_empty << RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_Z0_EMPTY(rb_debug_1_reg, wrreq_z0_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK) | (wrreq_z0_empty << RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_C1_PRE_EMPTY(rb_debug_1_reg, wrreq_c1_pre_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK) | (wrreq_c1_pre_empty << RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_C0_PRE_EMPTY(rb_debug_1_reg, wrreq_c0_pre_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK) | (wrreq_c0_pre_empty << RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_Z1_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_z1_hold_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK) | (cmdfifo_z1_hold_empty << RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_Z0_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_z0_hold_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK) | (cmdfifo_z0_hold_empty << RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_C1_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_c1_hold_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK) | (cmdfifo_c1_hold_empty << RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_C0_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_c0_hold_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK) | (cmdfifo_c0_hold_empty << RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_Z_ORDERING_EMPTY(rb_debug_1_reg, cmdfifo_z_ordering_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK) | (cmdfifo_z_ordering_empty << RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_C_ORDERING_EMPTY(rb_debug_1_reg, cmdfifo_c_ordering_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK) | (cmdfifo_c_ordering_empty << RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_SX_LAT_EMPTY(rb_debug_1_reg, c_sx_lat_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_SX_LAT_EMPTY_MASK) | (c_sx_lat_empty << RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_SX_CMD_EMPTY(rb_debug_1_reg, c_sx_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_SX_CMD_EMPTY_MASK) | (c_sx_cmd_empty << RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_EZ_TILE_EMPTY(rb_debug_1_reg, c_ez_tile_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK) | (c_ez_tile_empty << RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_REQ_EMPTY(rb_debug_1_reg, c_req_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_REQ_EMPTY_MASK) | (c_req_empty << RB_DEBUG_1_C_REQ_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_MASK_EMPTY(rb_debug_1_reg, c_mask_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_MASK_EMPTY_MASK) | (c_mask_empty << RB_DEBUG_1_C_MASK_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_EZ_INFSAMP_EMPTY(rb_debug_1_reg, ez_infsamp_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) | (ez_infsamp_empty << RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_1_t { + unsigned int rdreq_z1_cmd_empty : RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE; + unsigned int rdreq_z0_cmd_empty : RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE; + unsigned int rdreq_c1_cmd_empty : RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE; + unsigned int rdreq_c0_cmd_empty : RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE; + unsigned int rdreq_e1_ordering_empty : RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE; + unsigned int rdreq_e0_ordering_empty : RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE; + unsigned int rdreq_z1_empty : RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE; + unsigned int rdreq_z0_empty : RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE; + unsigned int rdreq_c1_empty : RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE; + unsigned int rdreq_c0_empty : RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE; + unsigned int wrreq_e1_macro_hi_empty : RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE; + unsigned int wrreq_e1_macro_lo_empty : RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE; + unsigned int wrreq_e0_macro_hi_empty : RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE; + unsigned int wrreq_e0_macro_lo_empty : RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE; + unsigned int wrreq_c_we_hi_empty : RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE; + unsigned int wrreq_c_we_lo_empty : RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE; + unsigned int wrreq_z1_empty : RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE; + unsigned int wrreq_z0_empty : RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE; + unsigned int wrreq_c1_pre_empty : RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE; + unsigned int wrreq_c0_pre_empty : RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE; + unsigned int cmdfifo_z1_hold_empty : RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_z0_hold_empty : RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_c1_hold_empty : RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_c0_hold_empty : RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_z_ordering_empty : RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE; + unsigned int cmdfifo_c_ordering_empty : RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE; + unsigned int c_sx_lat_empty : RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE; + unsigned int c_sx_cmd_empty : RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE; + unsigned int c_ez_tile_empty : RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE; + unsigned int c_req_empty : RB_DEBUG_1_C_REQ_EMPTY_SIZE; + unsigned int c_mask_empty : RB_DEBUG_1_C_MASK_EMPTY_SIZE; + unsigned int ez_infsamp_empty : RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE; + } rb_debug_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_1_t { + unsigned int ez_infsamp_empty : RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE; + unsigned int c_mask_empty : RB_DEBUG_1_C_MASK_EMPTY_SIZE; + unsigned int c_req_empty : RB_DEBUG_1_C_REQ_EMPTY_SIZE; + unsigned int c_ez_tile_empty : RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE; + unsigned int c_sx_cmd_empty : RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE; + unsigned int c_sx_lat_empty : RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE; + unsigned int cmdfifo_c_ordering_empty : RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE; + unsigned int cmdfifo_z_ordering_empty : RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE; + unsigned int cmdfifo_c0_hold_empty : RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_c1_hold_empty : RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_z0_hold_empty : RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_z1_hold_empty : RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE; + unsigned int wrreq_c0_pre_empty : RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE; + unsigned int wrreq_c1_pre_empty : RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE; + unsigned int wrreq_z0_empty : RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE; + unsigned int wrreq_z1_empty : RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE; + unsigned int wrreq_c_we_lo_empty : RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE; + unsigned int wrreq_c_we_hi_empty : RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE; + unsigned int wrreq_e0_macro_lo_empty : RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE; + unsigned int wrreq_e0_macro_hi_empty : RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE; + unsigned int wrreq_e1_macro_lo_empty : RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE; + unsigned int wrreq_e1_macro_hi_empty : RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE; + unsigned int rdreq_c0_empty : RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE; + unsigned int rdreq_c1_empty : RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE; + unsigned int rdreq_z0_empty : RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE; + unsigned int rdreq_z1_empty : RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE; + unsigned int rdreq_e0_ordering_empty : RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE; + unsigned int rdreq_e1_ordering_empty : RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE; + unsigned int rdreq_c0_cmd_empty : RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE; + unsigned int rdreq_c1_cmd_empty : RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE; + unsigned int rdreq_z0_cmd_empty : RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE; + unsigned int rdreq_z1_cmd_empty : RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE; + } rb_debug_1_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_1_t f; +} rb_debug_1_u; + + +/* + * RB_DEBUG_2 struct + */ + +#define RB_DEBUG_2_TILE_FIFO_COUNT_SIZE 4 +#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE 7 +#define RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE 1 +#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE 1 +#define RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE 1 +#define RB_DEBUG_2_EZ_INFTILE_FULL_SIZE 1 +#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE 1 +#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE 1 +#define RB_DEBUG_2_Z0_MASK_FULL_SIZE 1 +#define RB_DEBUG_2_Z1_MASK_FULL_SIZE 1 +#define RB_DEBUG_2_Z0_REQ_FULL_SIZE 1 +#define RB_DEBUG_2_Z1_REQ_FULL_SIZE 1 +#define RB_DEBUG_2_Z_SAMP_FULL_SIZE 1 +#define RB_DEBUG_2_Z_TILE_FULL_SIZE 1 +#define RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE 1 +#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE 1 +#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z0_MASK_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z1_MASK_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z0_REQ_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z1_REQ_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z_SAMP_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z_TILE_EMPTY_SIZE 1 + +#define RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT 0 +#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT 4 +#define RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT 11 +#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT 12 +#define RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT 13 +#define RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT 14 +#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT 15 +#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT 16 +#define RB_DEBUG_2_Z0_MASK_FULL_SHIFT 17 +#define RB_DEBUG_2_Z1_MASK_FULL_SHIFT 18 +#define RB_DEBUG_2_Z0_REQ_FULL_SHIFT 19 +#define RB_DEBUG_2_Z1_REQ_FULL_SHIFT 20 +#define RB_DEBUG_2_Z_SAMP_FULL_SHIFT 21 +#define RB_DEBUG_2_Z_TILE_FULL_SHIFT 22 +#define RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT 23 +#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT 24 +#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT 25 +#define RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT 26 +#define RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT 27 +#define RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT 28 +#define RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT 29 +#define RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT 30 +#define RB_DEBUG_2_Z_TILE_EMPTY_SHIFT 31 + +#define RB_DEBUG_2_TILE_FIFO_COUNT_MASK 0x0000000f +#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK 0x000007f0 +#define RB_DEBUG_2_MEM_EXPORT_FLAG_MASK 0x00000800 +#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK 0x00001000 +#define RB_DEBUG_2_CURRENT_TILE_EVENT_MASK 0x00002000 +#define RB_DEBUG_2_EZ_INFTILE_FULL_MASK 0x00004000 +#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK 0x00008000 +#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK 0x00010000 +#define RB_DEBUG_2_Z0_MASK_FULL_MASK 0x00020000 +#define RB_DEBUG_2_Z1_MASK_FULL_MASK 0x00040000 +#define RB_DEBUG_2_Z0_REQ_FULL_MASK 0x00080000 +#define RB_DEBUG_2_Z1_REQ_FULL_MASK 0x00100000 +#define RB_DEBUG_2_Z_SAMP_FULL_MASK 0x00200000 +#define RB_DEBUG_2_Z_TILE_FULL_MASK 0x00400000 +#define RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK 0x00800000 +#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK 0x01000000 +#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK 0x02000000 +#define RB_DEBUG_2_Z0_MASK_EMPTY_MASK 0x04000000 +#define RB_DEBUG_2_Z1_MASK_EMPTY_MASK 0x08000000 +#define RB_DEBUG_2_Z0_REQ_EMPTY_MASK 0x10000000 +#define RB_DEBUG_2_Z1_REQ_EMPTY_MASK 0x20000000 +#define RB_DEBUG_2_Z_SAMP_EMPTY_MASK 0x40000000 +#define RB_DEBUG_2_Z_TILE_EMPTY_MASK 0x80000000 + +#define RB_DEBUG_2_MASK \ + (RB_DEBUG_2_TILE_FIFO_COUNT_MASK | \ + RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK | \ + RB_DEBUG_2_MEM_EXPORT_FLAG_MASK | \ + RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK | \ + RB_DEBUG_2_CURRENT_TILE_EVENT_MASK | \ + RB_DEBUG_2_EZ_INFTILE_FULL_MASK | \ + RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK | \ + RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK | \ + RB_DEBUG_2_Z0_MASK_FULL_MASK | \ + RB_DEBUG_2_Z1_MASK_FULL_MASK | \ + RB_DEBUG_2_Z0_REQ_FULL_MASK | \ + RB_DEBUG_2_Z1_REQ_FULL_MASK | \ + RB_DEBUG_2_Z_SAMP_FULL_MASK | \ + RB_DEBUG_2_Z_TILE_FULL_MASK | \ + RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK | \ + RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK | \ + RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK | \ + RB_DEBUG_2_Z0_MASK_EMPTY_MASK | \ + RB_DEBUG_2_Z1_MASK_EMPTY_MASK | \ + RB_DEBUG_2_Z0_REQ_EMPTY_MASK | \ + RB_DEBUG_2_Z1_REQ_EMPTY_MASK | \ + RB_DEBUG_2_Z_SAMP_EMPTY_MASK | \ + RB_DEBUG_2_Z_TILE_EMPTY_MASK) + +#define RB_DEBUG_2(tile_fifo_count, sx_lat_fifo_count, mem_export_flag, sysmem_blend_flag, current_tile_event, ez_inftile_full, ez_mask_lower_full, ez_mask_upper_full, z0_mask_full, z1_mask_full, z0_req_full, z1_req_full, z_samp_full, z_tile_full, ez_inftile_empty, ez_mask_lower_empty, ez_mask_upper_empty, z0_mask_empty, z1_mask_empty, z0_req_empty, z1_req_empty, z_samp_empty, z_tile_empty) \ + ((tile_fifo_count << RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT) | \ + (sx_lat_fifo_count << RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT) | \ + (mem_export_flag << RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT) | \ + (sysmem_blend_flag << RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT) | \ + (current_tile_event << RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT) | \ + (ez_inftile_full << RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT) | \ + (ez_mask_lower_full << RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT) | \ + (ez_mask_upper_full << RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT) | \ + (z0_mask_full << RB_DEBUG_2_Z0_MASK_FULL_SHIFT) | \ + (z1_mask_full << RB_DEBUG_2_Z1_MASK_FULL_SHIFT) | \ + (z0_req_full << RB_DEBUG_2_Z0_REQ_FULL_SHIFT) | \ + (z1_req_full << RB_DEBUG_2_Z1_REQ_FULL_SHIFT) | \ + (z_samp_full << RB_DEBUG_2_Z_SAMP_FULL_SHIFT) | \ + (z_tile_full << RB_DEBUG_2_Z_TILE_FULL_SHIFT) | \ + (ez_inftile_empty << RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT) | \ + (ez_mask_lower_empty << RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT) | \ + (ez_mask_upper_empty << RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT) | \ + (z0_mask_empty << RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT) | \ + (z1_mask_empty << RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT) | \ + (z0_req_empty << RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT) | \ + (z1_req_empty << RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT) | \ + (z_samp_empty << RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT) | \ + (z_tile_empty << RB_DEBUG_2_Z_TILE_EMPTY_SHIFT)) + +#define RB_DEBUG_2_GET_TILE_FIFO_COUNT(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_TILE_FIFO_COUNT_MASK) >> RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT) +#define RB_DEBUG_2_GET_SX_LAT_FIFO_COUNT(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK) >> RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT) +#define RB_DEBUG_2_GET_MEM_EXPORT_FLAG(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_MEM_EXPORT_FLAG_MASK) >> RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT) +#define RB_DEBUG_2_GET_SYSMEM_BLEND_FLAG(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK) >> RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT) +#define RB_DEBUG_2_GET_CURRENT_TILE_EVENT(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_CURRENT_TILE_EVENT_MASK) >> RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT) +#define RB_DEBUG_2_GET_EZ_INFTILE_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_INFTILE_FULL_MASK) >> RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT) +#define RB_DEBUG_2_GET_EZ_MASK_LOWER_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK) >> RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT) +#define RB_DEBUG_2_GET_EZ_MASK_UPPER_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK) >> RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z0_MASK_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z0_MASK_FULL_MASK) >> RB_DEBUG_2_Z0_MASK_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z1_MASK_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z1_MASK_FULL_MASK) >> RB_DEBUG_2_Z1_MASK_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z0_REQ_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z0_REQ_FULL_MASK) >> RB_DEBUG_2_Z0_REQ_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z1_REQ_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z1_REQ_FULL_MASK) >> RB_DEBUG_2_Z1_REQ_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z_SAMP_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z_SAMP_FULL_MASK) >> RB_DEBUG_2_Z_SAMP_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z_TILE_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z_TILE_FULL_MASK) >> RB_DEBUG_2_Z_TILE_FULL_SHIFT) +#define RB_DEBUG_2_GET_EZ_INFTILE_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK) >> RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_EZ_MASK_LOWER_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK) >> RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_EZ_MASK_UPPER_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK) >> RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z0_MASK_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z0_MASK_EMPTY_MASK) >> RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z1_MASK_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z1_MASK_EMPTY_MASK) >> RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z0_REQ_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z0_REQ_EMPTY_MASK) >> RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z1_REQ_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z1_REQ_EMPTY_MASK) >> RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z_SAMP_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z_SAMP_EMPTY_MASK) >> RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z_TILE_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z_TILE_EMPTY_MASK) >> RB_DEBUG_2_Z_TILE_EMPTY_SHIFT) + +#define RB_DEBUG_2_SET_TILE_FIFO_COUNT(rb_debug_2_reg, tile_fifo_count) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_TILE_FIFO_COUNT_MASK) | (tile_fifo_count << RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT) +#define RB_DEBUG_2_SET_SX_LAT_FIFO_COUNT(rb_debug_2_reg, sx_lat_fifo_count) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK) | (sx_lat_fifo_count << RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT) +#define RB_DEBUG_2_SET_MEM_EXPORT_FLAG(rb_debug_2_reg, mem_export_flag) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_MEM_EXPORT_FLAG_MASK) | (mem_export_flag << RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT) +#define RB_DEBUG_2_SET_SYSMEM_BLEND_FLAG(rb_debug_2_reg, sysmem_blend_flag) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK) | (sysmem_blend_flag << RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT) +#define RB_DEBUG_2_SET_CURRENT_TILE_EVENT(rb_debug_2_reg, current_tile_event) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_CURRENT_TILE_EVENT_MASK) | (current_tile_event << RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT) +#define RB_DEBUG_2_SET_EZ_INFTILE_FULL(rb_debug_2_reg, ez_inftile_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_INFTILE_FULL_MASK) | (ez_inftile_full << RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT) +#define RB_DEBUG_2_SET_EZ_MASK_LOWER_FULL(rb_debug_2_reg, ez_mask_lower_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK) | (ez_mask_lower_full << RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT) +#define RB_DEBUG_2_SET_EZ_MASK_UPPER_FULL(rb_debug_2_reg, ez_mask_upper_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK) | (ez_mask_upper_full << RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z0_MASK_FULL(rb_debug_2_reg, z0_mask_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_MASK_FULL_MASK) | (z0_mask_full << RB_DEBUG_2_Z0_MASK_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z1_MASK_FULL(rb_debug_2_reg, z1_mask_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_MASK_FULL_MASK) | (z1_mask_full << RB_DEBUG_2_Z1_MASK_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z0_REQ_FULL(rb_debug_2_reg, z0_req_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_REQ_FULL_MASK) | (z0_req_full << RB_DEBUG_2_Z0_REQ_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z1_REQ_FULL(rb_debug_2_reg, z1_req_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_REQ_FULL_MASK) | (z1_req_full << RB_DEBUG_2_Z1_REQ_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z_SAMP_FULL(rb_debug_2_reg, z_samp_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_SAMP_FULL_MASK) | (z_samp_full << RB_DEBUG_2_Z_SAMP_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z_TILE_FULL(rb_debug_2_reg, z_tile_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_TILE_FULL_MASK) | (z_tile_full << RB_DEBUG_2_Z_TILE_FULL_SHIFT) +#define RB_DEBUG_2_SET_EZ_INFTILE_EMPTY(rb_debug_2_reg, ez_inftile_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK) | (ez_inftile_empty << RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_EZ_MASK_LOWER_EMPTY(rb_debug_2_reg, ez_mask_lower_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK) | (ez_mask_lower_empty << RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_EZ_MASK_UPPER_EMPTY(rb_debug_2_reg, ez_mask_upper_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK) | (ez_mask_upper_empty << RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z0_MASK_EMPTY(rb_debug_2_reg, z0_mask_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_MASK_EMPTY_MASK) | (z0_mask_empty << RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z1_MASK_EMPTY(rb_debug_2_reg, z1_mask_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_MASK_EMPTY_MASK) | (z1_mask_empty << RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z0_REQ_EMPTY(rb_debug_2_reg, z0_req_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_REQ_EMPTY_MASK) | (z0_req_empty << RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z1_REQ_EMPTY(rb_debug_2_reg, z1_req_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_REQ_EMPTY_MASK) | (z1_req_empty << RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z_SAMP_EMPTY(rb_debug_2_reg, z_samp_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_SAMP_EMPTY_MASK) | (z_samp_empty << RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z_TILE_EMPTY(rb_debug_2_reg, z_tile_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_TILE_EMPTY_MASK) | (z_tile_empty << RB_DEBUG_2_Z_TILE_EMPTY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_2_t { + unsigned int tile_fifo_count : RB_DEBUG_2_TILE_FIFO_COUNT_SIZE; + unsigned int sx_lat_fifo_count : RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE; + unsigned int mem_export_flag : RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE; + unsigned int sysmem_blend_flag : RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE; + unsigned int current_tile_event : RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE; + unsigned int ez_inftile_full : RB_DEBUG_2_EZ_INFTILE_FULL_SIZE; + unsigned int ez_mask_lower_full : RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE; + unsigned int ez_mask_upper_full : RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE; + unsigned int z0_mask_full : RB_DEBUG_2_Z0_MASK_FULL_SIZE; + unsigned int z1_mask_full : RB_DEBUG_2_Z1_MASK_FULL_SIZE; + unsigned int z0_req_full : RB_DEBUG_2_Z0_REQ_FULL_SIZE; + unsigned int z1_req_full : RB_DEBUG_2_Z1_REQ_FULL_SIZE; + unsigned int z_samp_full : RB_DEBUG_2_Z_SAMP_FULL_SIZE; + unsigned int z_tile_full : RB_DEBUG_2_Z_TILE_FULL_SIZE; + unsigned int ez_inftile_empty : RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE; + unsigned int ez_mask_lower_empty : RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE; + unsigned int ez_mask_upper_empty : RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE; + unsigned int z0_mask_empty : RB_DEBUG_2_Z0_MASK_EMPTY_SIZE; + unsigned int z1_mask_empty : RB_DEBUG_2_Z1_MASK_EMPTY_SIZE; + unsigned int z0_req_empty : RB_DEBUG_2_Z0_REQ_EMPTY_SIZE; + unsigned int z1_req_empty : RB_DEBUG_2_Z1_REQ_EMPTY_SIZE; + unsigned int z_samp_empty : RB_DEBUG_2_Z_SAMP_EMPTY_SIZE; + unsigned int z_tile_empty : RB_DEBUG_2_Z_TILE_EMPTY_SIZE; + } rb_debug_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_2_t { + unsigned int z_tile_empty : RB_DEBUG_2_Z_TILE_EMPTY_SIZE; + unsigned int z_samp_empty : RB_DEBUG_2_Z_SAMP_EMPTY_SIZE; + unsigned int z1_req_empty : RB_DEBUG_2_Z1_REQ_EMPTY_SIZE; + unsigned int z0_req_empty : RB_DEBUG_2_Z0_REQ_EMPTY_SIZE; + unsigned int z1_mask_empty : RB_DEBUG_2_Z1_MASK_EMPTY_SIZE; + unsigned int z0_mask_empty : RB_DEBUG_2_Z0_MASK_EMPTY_SIZE; + unsigned int ez_mask_upper_empty : RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE; + unsigned int ez_mask_lower_empty : RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE; + unsigned int ez_inftile_empty : RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE; + unsigned int z_tile_full : RB_DEBUG_2_Z_TILE_FULL_SIZE; + unsigned int z_samp_full : RB_DEBUG_2_Z_SAMP_FULL_SIZE; + unsigned int z1_req_full : RB_DEBUG_2_Z1_REQ_FULL_SIZE; + unsigned int z0_req_full : RB_DEBUG_2_Z0_REQ_FULL_SIZE; + unsigned int z1_mask_full : RB_DEBUG_2_Z1_MASK_FULL_SIZE; + unsigned int z0_mask_full : RB_DEBUG_2_Z0_MASK_FULL_SIZE; + unsigned int ez_mask_upper_full : RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE; + unsigned int ez_mask_lower_full : RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE; + unsigned int ez_inftile_full : RB_DEBUG_2_EZ_INFTILE_FULL_SIZE; + unsigned int current_tile_event : RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE; + unsigned int sysmem_blend_flag : RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE; + unsigned int mem_export_flag : RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE; + unsigned int sx_lat_fifo_count : RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE; + unsigned int tile_fifo_count : RB_DEBUG_2_TILE_FIFO_COUNT_SIZE; + } rb_debug_2_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_2_t f; +} rb_debug_2_u; + + +/* + * RB_DEBUG_3 struct + */ + +#define RB_DEBUG_3_ACCUM_VALID_SIZE 4 +#define RB_DEBUG_3_ACCUM_FLUSHING_SIZE 4 +#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE 6 +#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE 1 +#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE 4 +#define RB_DEBUG_3_SHD_FULL_SIZE 1 +#define RB_DEBUG_3_SHD_EMPTY_SIZE 1 +#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE 1 +#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE 1 +#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE 1 +#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE 1 +#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE 1 +#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE 1 +#define RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE 1 +#define RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE 1 + +#define RB_DEBUG_3_ACCUM_VALID_SHIFT 0 +#define RB_DEBUG_3_ACCUM_FLUSHING_SHIFT 4 +#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT 8 +#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT 14 +#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT 15 +#define RB_DEBUG_3_SHD_FULL_SHIFT 19 +#define RB_DEBUG_3_SHD_EMPTY_SHIFT 20 +#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT 21 +#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT 22 +#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT 23 +#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT 24 +#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT 25 +#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT 26 +#define RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT 27 +#define RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT 28 + +#define RB_DEBUG_3_ACCUM_VALID_MASK 0x0000000f +#define RB_DEBUG_3_ACCUM_FLUSHING_MASK 0x000000f0 +#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK 0x00003f00 +#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK 0x00004000 +#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK 0x00078000 +#define RB_DEBUG_3_SHD_FULL_MASK 0x00080000 +#define RB_DEBUG_3_SHD_EMPTY_MASK 0x00100000 +#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK 0x00200000 +#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK 0x00400000 +#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK 0x00800000 +#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK 0x01000000 +#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK 0x02000000 +#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK 0x04000000 +#define RB_DEBUG_3_ZEXP_LOWER_FULL_MASK 0x08000000 +#define RB_DEBUG_3_ZEXP_UPPER_FULL_MASK 0x10000000 + +#define RB_DEBUG_3_MASK \ + (RB_DEBUG_3_ACCUM_VALID_MASK | \ + RB_DEBUG_3_ACCUM_FLUSHING_MASK | \ + RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK | \ + RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK | \ + RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK | \ + RB_DEBUG_3_SHD_FULL_MASK | \ + RB_DEBUG_3_SHD_EMPTY_MASK | \ + RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK | \ + RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK | \ + RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK | \ + RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK | \ + RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK | \ + RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK | \ + RB_DEBUG_3_ZEXP_LOWER_FULL_MASK | \ + RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) + +#define RB_DEBUG_3(accum_valid, accum_flushing, accum_write_clean_count, accum_input_reg_valid, accum_data_fifo_cnt, shd_full, shd_empty, ez_return_lower_empty, ez_return_upper_empty, ez_return_lower_full, ez_return_upper_full, zexp_lower_empty, zexp_upper_empty, zexp_lower_full, zexp_upper_full) \ + ((accum_valid << RB_DEBUG_3_ACCUM_VALID_SHIFT) | \ + (accum_flushing << RB_DEBUG_3_ACCUM_FLUSHING_SHIFT) | \ + (accum_write_clean_count << RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT) | \ + (accum_input_reg_valid << RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT) | \ + (accum_data_fifo_cnt << RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT) | \ + (shd_full << RB_DEBUG_3_SHD_FULL_SHIFT) | \ + (shd_empty << RB_DEBUG_3_SHD_EMPTY_SHIFT) | \ + (ez_return_lower_empty << RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT) | \ + (ez_return_upper_empty << RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT) | \ + (ez_return_lower_full << RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT) | \ + (ez_return_upper_full << RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT) | \ + (zexp_lower_empty << RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT) | \ + (zexp_upper_empty << RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT) | \ + (zexp_lower_full << RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT) | \ + (zexp_upper_full << RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT)) + +#define RB_DEBUG_3_GET_ACCUM_VALID(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_VALID_MASK) >> RB_DEBUG_3_ACCUM_VALID_SHIFT) +#define RB_DEBUG_3_GET_ACCUM_FLUSHING(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_FLUSHING_MASK) >> RB_DEBUG_3_ACCUM_FLUSHING_SHIFT) +#define RB_DEBUG_3_GET_ACCUM_WRITE_CLEAN_COUNT(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK) >> RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT) +#define RB_DEBUG_3_GET_ACCUM_INPUT_REG_VALID(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK) >> RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT) +#define RB_DEBUG_3_GET_ACCUM_DATA_FIFO_CNT(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK) >> RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT) +#define RB_DEBUG_3_GET_SHD_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_SHD_FULL_MASK) >> RB_DEBUG_3_SHD_FULL_SHIFT) +#define RB_DEBUG_3_GET_SHD_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_SHD_EMPTY_MASK) >> RB_DEBUG_3_SHD_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_EZ_RETURN_LOWER_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK) >> RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_EZ_RETURN_UPPER_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK) >> RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_EZ_RETURN_LOWER_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK) >> RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT) +#define RB_DEBUG_3_GET_EZ_RETURN_UPPER_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK) >> RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT) +#define RB_DEBUG_3_GET_ZEXP_LOWER_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK) >> RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_ZEXP_UPPER_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK) >> RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_ZEXP_LOWER_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ZEXP_LOWER_FULL_MASK) >> RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT) +#define RB_DEBUG_3_GET_ZEXP_UPPER_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) >> RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT) + +#define RB_DEBUG_3_SET_ACCUM_VALID(rb_debug_3_reg, accum_valid) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_VALID_MASK) | (accum_valid << RB_DEBUG_3_ACCUM_VALID_SHIFT) +#define RB_DEBUG_3_SET_ACCUM_FLUSHING(rb_debug_3_reg, accum_flushing) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_FLUSHING_MASK) | (accum_flushing << RB_DEBUG_3_ACCUM_FLUSHING_SHIFT) +#define RB_DEBUG_3_SET_ACCUM_WRITE_CLEAN_COUNT(rb_debug_3_reg, accum_write_clean_count) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK) | (accum_write_clean_count << RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT) +#define RB_DEBUG_3_SET_ACCUM_INPUT_REG_VALID(rb_debug_3_reg, accum_input_reg_valid) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK) | (accum_input_reg_valid << RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT) +#define RB_DEBUG_3_SET_ACCUM_DATA_FIFO_CNT(rb_debug_3_reg, accum_data_fifo_cnt) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK) | (accum_data_fifo_cnt << RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT) +#define RB_DEBUG_3_SET_SHD_FULL(rb_debug_3_reg, shd_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_SHD_FULL_MASK) | (shd_full << RB_DEBUG_3_SHD_FULL_SHIFT) +#define RB_DEBUG_3_SET_SHD_EMPTY(rb_debug_3_reg, shd_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_SHD_EMPTY_MASK) | (shd_empty << RB_DEBUG_3_SHD_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_EZ_RETURN_LOWER_EMPTY(rb_debug_3_reg, ez_return_lower_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK) | (ez_return_lower_empty << RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_EZ_RETURN_UPPER_EMPTY(rb_debug_3_reg, ez_return_upper_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK) | (ez_return_upper_empty << RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_EZ_RETURN_LOWER_FULL(rb_debug_3_reg, ez_return_lower_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK) | (ez_return_lower_full << RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT) +#define RB_DEBUG_3_SET_EZ_RETURN_UPPER_FULL(rb_debug_3_reg, ez_return_upper_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK) | (ez_return_upper_full << RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT) +#define RB_DEBUG_3_SET_ZEXP_LOWER_EMPTY(rb_debug_3_reg, zexp_lower_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK) | (zexp_lower_empty << RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_ZEXP_UPPER_EMPTY(rb_debug_3_reg, zexp_upper_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK) | (zexp_upper_empty << RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_ZEXP_LOWER_FULL(rb_debug_3_reg, zexp_lower_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_LOWER_FULL_MASK) | (zexp_lower_full << RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT) +#define RB_DEBUG_3_SET_ZEXP_UPPER_FULL(rb_debug_3_reg, zexp_upper_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) | (zexp_upper_full << RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_3_t { + unsigned int accum_valid : RB_DEBUG_3_ACCUM_VALID_SIZE; + unsigned int accum_flushing : RB_DEBUG_3_ACCUM_FLUSHING_SIZE; + unsigned int accum_write_clean_count : RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE; + unsigned int accum_input_reg_valid : RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE; + unsigned int accum_data_fifo_cnt : RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE; + unsigned int shd_full : RB_DEBUG_3_SHD_FULL_SIZE; + unsigned int shd_empty : RB_DEBUG_3_SHD_EMPTY_SIZE; + unsigned int ez_return_lower_empty : RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE; + unsigned int ez_return_upper_empty : RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE; + unsigned int ez_return_lower_full : RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE; + unsigned int ez_return_upper_full : RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE; + unsigned int zexp_lower_empty : RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE; + unsigned int zexp_upper_empty : RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE; + unsigned int zexp_lower_full : RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE; + unsigned int zexp_upper_full : RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE; + unsigned int : 3; + } rb_debug_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_3_t { + unsigned int : 3; + unsigned int zexp_upper_full : RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE; + unsigned int zexp_lower_full : RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE; + unsigned int zexp_upper_empty : RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE; + unsigned int zexp_lower_empty : RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE; + unsigned int ez_return_upper_full : RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE; + unsigned int ez_return_lower_full : RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE; + unsigned int ez_return_upper_empty : RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE; + unsigned int ez_return_lower_empty : RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE; + unsigned int shd_empty : RB_DEBUG_3_SHD_EMPTY_SIZE; + unsigned int shd_full : RB_DEBUG_3_SHD_FULL_SIZE; + unsigned int accum_data_fifo_cnt : RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE; + unsigned int accum_input_reg_valid : RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE; + unsigned int accum_write_clean_count : RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE; + unsigned int accum_flushing : RB_DEBUG_3_ACCUM_FLUSHING_SIZE; + unsigned int accum_valid : RB_DEBUG_3_ACCUM_VALID_SIZE; + } rb_debug_3_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_3_t f; +} rb_debug_3_u; + + +/* + * RB_DEBUG_4 struct + */ + +#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE 1 +#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE 1 +#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE 1 +#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE 1 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE 1 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE 1 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE 1 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE 1 +#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE 1 +#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE 4 + +#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT 0 +#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT 1 +#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT 2 +#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT 3 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT 4 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT 5 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT 6 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT 7 +#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT 8 +#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT 9 + +#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK 0x00000001 +#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK 0x00000002 +#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK 0x00000004 +#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK 0x00000008 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK 0x00000010 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK 0x00000020 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK 0x00000040 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK 0x00000080 +#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK 0x00000100 +#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK 0x00001e00 + +#define RB_DEBUG_4_MASK \ + (RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK | \ + RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK | \ + RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK | \ + RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK | \ + RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK | \ + RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK | \ + RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK | \ + RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK | \ + RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK | \ + RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) + +#define RB_DEBUG_4(gmem_rd_access_flag, gmem_wr_access_flag, sysmem_rd_access_flag, sysmem_wr_access_flag, accum_data_fifo_empty, accum_order_fifo_empty, accum_data_fifo_full, accum_order_fifo_full, sysmem_write_count_overflow, context_count_debug) \ + ((gmem_rd_access_flag << RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT) | \ + (gmem_wr_access_flag << RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT) | \ + (sysmem_rd_access_flag << RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT) | \ + (sysmem_wr_access_flag << RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT) | \ + (accum_data_fifo_empty << RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT) | \ + (accum_order_fifo_empty << RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT) | \ + (accum_data_fifo_full << RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT) | \ + (accum_order_fifo_full << RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT) | \ + (sysmem_write_count_overflow << RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT) | \ + (context_count_debug << RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT)) + +#define RB_DEBUG_4_GET_GMEM_RD_ACCESS_FLAG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK) >> RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_GET_GMEM_WR_ACCESS_FLAG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK) >> RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_GET_SYSMEM_RD_ACCESS_FLAG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK) >> RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_GET_SYSMEM_WR_ACCESS_FLAG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK) >> RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_GET_ACCUM_DATA_FIFO_EMPTY(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK) >> RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT) +#define RB_DEBUG_4_GET_ACCUM_ORDER_FIFO_EMPTY(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK) >> RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT) +#define RB_DEBUG_4_GET_ACCUM_DATA_FIFO_FULL(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK) >> RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT) +#define RB_DEBUG_4_GET_ACCUM_ORDER_FIFO_FULL(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK) >> RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT) +#define RB_DEBUG_4_GET_SYSMEM_WRITE_COUNT_OVERFLOW(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK) >> RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT) +#define RB_DEBUG_4_GET_CONTEXT_COUNT_DEBUG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) >> RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT) + +#define RB_DEBUG_4_SET_GMEM_RD_ACCESS_FLAG(rb_debug_4_reg, gmem_rd_access_flag) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK) | (gmem_rd_access_flag << RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_SET_GMEM_WR_ACCESS_FLAG(rb_debug_4_reg, gmem_wr_access_flag) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK) | (gmem_wr_access_flag << RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_SET_SYSMEM_RD_ACCESS_FLAG(rb_debug_4_reg, sysmem_rd_access_flag) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK) | (sysmem_rd_access_flag << RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_SET_SYSMEM_WR_ACCESS_FLAG(rb_debug_4_reg, sysmem_wr_access_flag) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK) | (sysmem_wr_access_flag << RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_SET_ACCUM_DATA_FIFO_EMPTY(rb_debug_4_reg, accum_data_fifo_empty) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK) | (accum_data_fifo_empty << RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT) +#define RB_DEBUG_4_SET_ACCUM_ORDER_FIFO_EMPTY(rb_debug_4_reg, accum_order_fifo_empty) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK) | (accum_order_fifo_empty << RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT) +#define RB_DEBUG_4_SET_ACCUM_DATA_FIFO_FULL(rb_debug_4_reg, accum_data_fifo_full) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK) | (accum_data_fifo_full << RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT) +#define RB_DEBUG_4_SET_ACCUM_ORDER_FIFO_FULL(rb_debug_4_reg, accum_order_fifo_full) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK) | (accum_order_fifo_full << RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT) +#define RB_DEBUG_4_SET_SYSMEM_WRITE_COUNT_OVERFLOW(rb_debug_4_reg, sysmem_write_count_overflow) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK) | (sysmem_write_count_overflow << RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT) +#define RB_DEBUG_4_SET_CONTEXT_COUNT_DEBUG(rb_debug_4_reg, context_count_debug) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) | (context_count_debug << RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_4_t { + unsigned int gmem_rd_access_flag : RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE; + unsigned int gmem_wr_access_flag : RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE; + unsigned int sysmem_rd_access_flag : RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE; + unsigned int sysmem_wr_access_flag : RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE; + unsigned int accum_data_fifo_empty : RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE; + unsigned int accum_order_fifo_empty : RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE; + unsigned int accum_data_fifo_full : RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE; + unsigned int accum_order_fifo_full : RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE; + unsigned int sysmem_write_count_overflow : RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE; + unsigned int context_count_debug : RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE; + unsigned int : 19; + } rb_debug_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_4_t { + unsigned int : 19; + unsigned int context_count_debug : RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE; + unsigned int sysmem_write_count_overflow : RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE; + unsigned int accum_order_fifo_full : RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE; + unsigned int accum_data_fifo_full : RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE; + unsigned int accum_order_fifo_empty : RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE; + unsigned int accum_data_fifo_empty : RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE; + unsigned int sysmem_wr_access_flag : RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE; + unsigned int sysmem_rd_access_flag : RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE; + unsigned int gmem_wr_access_flag : RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE; + unsigned int gmem_rd_access_flag : RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE; + } rb_debug_4_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_4_t f; +} rb_debug_4_u; + + +/* + * RB_FLAG_CONTROL struct + */ + +#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE 1 + +#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT 0 + +#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK 0x00000001 + +#define RB_FLAG_CONTROL_MASK \ + (RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) + +#define RB_FLAG_CONTROL(debug_flag_clear) \ + ((debug_flag_clear << RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT)) + +#define RB_FLAG_CONTROL_GET_DEBUG_FLAG_CLEAR(rb_flag_control) \ + ((rb_flag_control & RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) >> RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT) + +#define RB_FLAG_CONTROL_SET_DEBUG_FLAG_CLEAR(rb_flag_control_reg, debug_flag_clear) \ + rb_flag_control_reg = (rb_flag_control_reg & ~RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) | (debug_flag_clear << RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_flag_control_t { + unsigned int debug_flag_clear : RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE; + unsigned int : 31; + } rb_flag_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_flag_control_t { + unsigned int : 31; + unsigned int debug_flag_clear : RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE; + } rb_flag_control_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_flag_control_t f; +} rb_flag_control_u; + + +/* + * BC_DUMMY_CRAYRB_ENUMS struct + */ + +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE 6 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE 1 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE 2 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE 2 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE 6 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE 3 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE 6 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE 1 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE 2 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE 3 + +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT 0 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT 6 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT 7 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT 9 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT 11 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT 17 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT 20 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT 26 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT 27 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT 29 + +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK 0x0000003f +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK 0x00000040 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK 0x00000180 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK 0x00000600 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK 0x0001f800 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK 0x000e0000 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK 0x03f00000 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK 0x04000000 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK 0x18000000 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK 0xe0000000 + +#define BC_DUMMY_CRAYRB_ENUMS_MASK \ + (BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) + +#define BC_DUMMY_CRAYRB_ENUMS(dummy_crayrb_depth_format, dummy_crayrb_surface_swap, dummy_crayrb_depth_array, dummy_crayrb_array, dummy_crayrb_color_format, dummy_crayrb_surface_number, dummy_crayrb_surface_format, dummy_crayrb_surface_tiling, dummy_crayrb_surface_array, dummy_rb_copy_dest_info_number) \ + ((dummy_crayrb_depth_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT) | \ + (dummy_crayrb_surface_swap << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT) | \ + (dummy_crayrb_depth_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT) | \ + (dummy_crayrb_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT) | \ + (dummy_crayrb_color_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT) | \ + (dummy_crayrb_surface_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT) | \ + (dummy_crayrb_surface_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT) | \ + (dummy_crayrb_surface_tiling << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT) | \ + (dummy_crayrb_surface_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT) | \ + (dummy_rb_copy_dest_info_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT)) + +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_DEPTH_FORMAT(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_SWAP(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_DEPTH_ARRAY(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_ARRAY(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_COLOR_FORMAT(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_NUMBER(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_FORMAT(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_TILING(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_ARRAY(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_RB_COPY_DEST_INFO_NUMBER(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT) + +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_DEPTH_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_depth_format) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK) | (dummy_crayrb_depth_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_SWAP(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_swap) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK) | (dummy_crayrb_surface_swap << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_DEPTH_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_depth_array) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK) | (dummy_crayrb_depth_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_array) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK) | (dummy_crayrb_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_COLOR_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_color_format) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK) | (dummy_crayrb_color_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_NUMBER(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_number) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK) | (dummy_crayrb_surface_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_format) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK) | (dummy_crayrb_surface_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_TILING(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_tiling) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK) | (dummy_crayrb_surface_tiling << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_array) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK) | (dummy_crayrb_surface_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_RB_COPY_DEST_INFO_NUMBER(bc_dummy_crayrb_enums_reg, dummy_rb_copy_dest_info_number) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) | (dummy_rb_copy_dest_info_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bc_dummy_crayrb_enums_t { + unsigned int dummy_crayrb_depth_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE; + unsigned int dummy_crayrb_surface_swap : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE; + unsigned int dummy_crayrb_depth_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE; + unsigned int dummy_crayrb_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE; + unsigned int dummy_crayrb_color_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE; + unsigned int dummy_crayrb_surface_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE; + unsigned int dummy_crayrb_surface_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE; + unsigned int dummy_crayrb_surface_tiling : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE; + unsigned int dummy_crayrb_surface_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE; + unsigned int dummy_rb_copy_dest_info_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE; + } bc_dummy_crayrb_enums_t; + +#else // !BIGENDIAN_OS + + typedef struct _bc_dummy_crayrb_enums_t { + unsigned int dummy_rb_copy_dest_info_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE; + unsigned int dummy_crayrb_surface_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE; + unsigned int dummy_crayrb_surface_tiling : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE; + unsigned int dummy_crayrb_surface_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE; + unsigned int dummy_crayrb_surface_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE; + unsigned int dummy_crayrb_color_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE; + unsigned int dummy_crayrb_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE; + unsigned int dummy_crayrb_depth_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE; + unsigned int dummy_crayrb_surface_swap : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE; + unsigned int dummy_crayrb_depth_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE; + } bc_dummy_crayrb_enums_t; + +#endif + +typedef union { + unsigned int val : 32; + bc_dummy_crayrb_enums_t f; +} bc_dummy_crayrb_enums_u; + + +/* + * BC_DUMMY_CRAYRB_MOREENUMS struct + */ + +#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE 2 + +#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT 0 + +#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK 0x00000003 + +#define BC_DUMMY_CRAYRB_MOREENUMS_MASK \ + (BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) + +#define BC_DUMMY_CRAYRB_MOREENUMS(dummy_crayrb_colorarrayx) \ + ((dummy_crayrb_colorarrayx << BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT)) + +#define BC_DUMMY_CRAYRB_MOREENUMS_GET_DUMMY_CRAYRB_COLORARRAYX(bc_dummy_crayrb_moreenums) \ + ((bc_dummy_crayrb_moreenums & BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) >> BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT) + +#define BC_DUMMY_CRAYRB_MOREENUMS_SET_DUMMY_CRAYRB_COLORARRAYX(bc_dummy_crayrb_moreenums_reg, dummy_crayrb_colorarrayx) \ + bc_dummy_crayrb_moreenums_reg = (bc_dummy_crayrb_moreenums_reg & ~BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) | (dummy_crayrb_colorarrayx << BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bc_dummy_crayrb_moreenums_t { + unsigned int dummy_crayrb_colorarrayx : BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE; + unsigned int : 30; + } bc_dummy_crayrb_moreenums_t; + +#else // !BIGENDIAN_OS + + typedef struct _bc_dummy_crayrb_moreenums_t { + unsigned int : 30; + unsigned int dummy_crayrb_colorarrayx : BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE; + } bc_dummy_crayrb_moreenums_t; + +#endif + +typedef union { + unsigned int val : 32; + bc_dummy_crayrb_moreenums_t f; +} bc_dummy_crayrb_moreenums_u; + + +#endif + + diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_typedef.h b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_typedef.h new file mode 100644 index 000000000000..1feebebda054 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_typedef.h @@ -0,0 +1,540 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_TYPEDEF_HEADER) +#define _yamato_TYPEDEF_HEADER + +#include "yamato_registers.h" + +typedef union PA_CL_VPORT_XSCALE regPA_CL_VPORT_XSCALE; +typedef union PA_CL_VPORT_XOFFSET regPA_CL_VPORT_XOFFSET; +typedef union PA_CL_VPORT_YSCALE regPA_CL_VPORT_YSCALE; +typedef union PA_CL_VPORT_YOFFSET regPA_CL_VPORT_YOFFSET; +typedef union PA_CL_VPORT_ZSCALE regPA_CL_VPORT_ZSCALE; +typedef union PA_CL_VPORT_ZOFFSET regPA_CL_VPORT_ZOFFSET; +typedef union PA_CL_VTE_CNTL regPA_CL_VTE_CNTL; +typedef union PA_CL_CLIP_CNTL regPA_CL_CLIP_CNTL; +typedef union PA_CL_GB_VERT_CLIP_ADJ regPA_CL_GB_VERT_CLIP_ADJ; +typedef union PA_CL_GB_VERT_DISC_ADJ regPA_CL_GB_VERT_DISC_ADJ; +typedef union PA_CL_GB_HORZ_CLIP_ADJ regPA_CL_GB_HORZ_CLIP_ADJ; +typedef union PA_CL_GB_HORZ_DISC_ADJ regPA_CL_GB_HORZ_DISC_ADJ; +typedef union PA_CL_ENHANCE regPA_CL_ENHANCE; +typedef union PA_SC_ENHANCE regPA_SC_ENHANCE; +typedef union PA_SU_VTX_CNTL regPA_SU_VTX_CNTL; +typedef union PA_SU_POINT_SIZE regPA_SU_POINT_SIZE; +typedef union PA_SU_POINT_MINMAX regPA_SU_POINT_MINMAX; +typedef union PA_SU_LINE_CNTL regPA_SU_LINE_CNTL; +typedef union PA_SU_SC_MODE_CNTL regPA_SU_SC_MODE_CNTL; +typedef union PA_SU_POLY_OFFSET_FRONT_SCALE regPA_SU_POLY_OFFSET_FRONT_SCALE; +typedef union PA_SU_POLY_OFFSET_FRONT_OFFSET regPA_SU_POLY_OFFSET_FRONT_OFFSET; +typedef union PA_SU_POLY_OFFSET_BACK_SCALE regPA_SU_POLY_OFFSET_BACK_SCALE; +typedef union PA_SU_POLY_OFFSET_BACK_OFFSET regPA_SU_POLY_OFFSET_BACK_OFFSET; +typedef union PA_SU_PERFCOUNTER0_SELECT regPA_SU_PERFCOUNTER0_SELECT; +typedef union PA_SU_PERFCOUNTER1_SELECT regPA_SU_PERFCOUNTER1_SELECT; +typedef union PA_SU_PERFCOUNTER2_SELECT regPA_SU_PERFCOUNTER2_SELECT; +typedef union PA_SU_PERFCOUNTER3_SELECT regPA_SU_PERFCOUNTER3_SELECT; +typedef union PA_SU_PERFCOUNTER0_LOW regPA_SU_PERFCOUNTER0_LOW; +typedef union PA_SU_PERFCOUNTER0_HI regPA_SU_PERFCOUNTER0_HI; +typedef union PA_SU_PERFCOUNTER1_LOW regPA_SU_PERFCOUNTER1_LOW; +typedef union PA_SU_PERFCOUNTER1_HI regPA_SU_PERFCOUNTER1_HI; +typedef union PA_SU_PERFCOUNTER2_LOW regPA_SU_PERFCOUNTER2_LOW; +typedef union PA_SU_PERFCOUNTER2_HI regPA_SU_PERFCOUNTER2_HI; +typedef union PA_SU_PERFCOUNTER3_LOW regPA_SU_PERFCOUNTER3_LOW; +typedef union PA_SU_PERFCOUNTER3_HI regPA_SU_PERFCOUNTER3_HI; +typedef union PA_SC_WINDOW_OFFSET regPA_SC_WINDOW_OFFSET; +typedef union PA_SC_AA_CONFIG regPA_SC_AA_CONFIG; +typedef union PA_SC_AA_MASK regPA_SC_AA_MASK; +typedef union PA_SC_LINE_STIPPLE regPA_SC_LINE_STIPPLE; +typedef union PA_SC_LINE_CNTL regPA_SC_LINE_CNTL; +typedef union PA_SC_WINDOW_SCISSOR_TL regPA_SC_WINDOW_SCISSOR_TL; +typedef union PA_SC_WINDOW_SCISSOR_BR regPA_SC_WINDOW_SCISSOR_BR; +typedef union PA_SC_SCREEN_SCISSOR_TL regPA_SC_SCREEN_SCISSOR_TL; +typedef union PA_SC_SCREEN_SCISSOR_BR regPA_SC_SCREEN_SCISSOR_BR; +typedef union PA_SC_VIZ_QUERY regPA_SC_VIZ_QUERY; +typedef union PA_SC_VIZ_QUERY_STATUS regPA_SC_VIZ_QUERY_STATUS; +typedef union PA_SC_LINE_STIPPLE_STATE regPA_SC_LINE_STIPPLE_STATE; +typedef union PA_SC_PERFCOUNTER0_SELECT regPA_SC_PERFCOUNTER0_SELECT; +typedef union PA_SC_PERFCOUNTER0_LOW regPA_SC_PERFCOUNTER0_LOW; +typedef union PA_SC_PERFCOUNTER0_HI regPA_SC_PERFCOUNTER0_HI; +typedef union PA_CL_CNTL_STATUS regPA_CL_CNTL_STATUS; +typedef union PA_SU_CNTL_STATUS regPA_SU_CNTL_STATUS; +typedef union PA_SC_CNTL_STATUS regPA_SC_CNTL_STATUS; +typedef union PA_SU_DEBUG_CNTL regPA_SU_DEBUG_CNTL; +typedef union PA_SU_DEBUG_DATA regPA_SU_DEBUG_DATA; +typedef union PA_SC_DEBUG_CNTL regPA_SC_DEBUG_CNTL; +typedef union PA_SC_DEBUG_DATA regPA_SC_DEBUG_DATA; +typedef union GFX_COPY_STATE regGFX_COPY_STATE; +typedef union VGT_DRAW_INITIATOR regVGT_DRAW_INITIATOR; +typedef union VGT_EVENT_INITIATOR regVGT_EVENT_INITIATOR; +typedef union VGT_DMA_BASE regVGT_DMA_BASE; +typedef union VGT_DMA_SIZE regVGT_DMA_SIZE; +typedef union VGT_BIN_BASE regVGT_BIN_BASE; +typedef union VGT_BIN_SIZE regVGT_BIN_SIZE; +typedef union VGT_CURRENT_BIN_ID_MIN regVGT_CURRENT_BIN_ID_MIN; +typedef union VGT_CURRENT_BIN_ID_MAX regVGT_CURRENT_BIN_ID_MAX; +typedef union VGT_IMMED_DATA regVGT_IMMED_DATA; +typedef union VGT_MAX_VTX_INDX regVGT_MAX_VTX_INDX; +typedef union VGT_MIN_VTX_INDX regVGT_MIN_VTX_INDX; +typedef union VGT_INDX_OFFSET regVGT_INDX_OFFSET; +typedef union VGT_VERTEX_REUSE_BLOCK_CNTL regVGT_VERTEX_REUSE_BLOCK_CNTL; +typedef union VGT_OUT_DEALLOC_CNTL regVGT_OUT_DEALLOC_CNTL; +typedef union VGT_MULTI_PRIM_IB_RESET_INDX regVGT_MULTI_PRIM_IB_RESET_INDX; +typedef union VGT_ENHANCE regVGT_ENHANCE; +typedef union VGT_VTX_VECT_EJECT_REG regVGT_VTX_VECT_EJECT_REG; +typedef union VGT_LAST_COPY_STATE regVGT_LAST_COPY_STATE; +typedef union VGT_DEBUG_CNTL regVGT_DEBUG_CNTL; +typedef union VGT_DEBUG_DATA regVGT_DEBUG_DATA; +typedef union VGT_CNTL_STATUS regVGT_CNTL_STATUS; +typedef union VGT_CRC_SQ_DATA regVGT_CRC_SQ_DATA; +typedef union VGT_CRC_SQ_CTRL regVGT_CRC_SQ_CTRL; +typedef union VGT_PERFCOUNTER0_SELECT regVGT_PERFCOUNTER0_SELECT; +typedef union VGT_PERFCOUNTER1_SELECT regVGT_PERFCOUNTER1_SELECT; +typedef union VGT_PERFCOUNTER2_SELECT regVGT_PERFCOUNTER2_SELECT; +typedef union VGT_PERFCOUNTER3_SELECT regVGT_PERFCOUNTER3_SELECT; +typedef union VGT_PERFCOUNTER0_LOW regVGT_PERFCOUNTER0_LOW; +typedef union VGT_PERFCOUNTER1_LOW regVGT_PERFCOUNTER1_LOW; +typedef union VGT_PERFCOUNTER2_LOW regVGT_PERFCOUNTER2_LOW; +typedef union VGT_PERFCOUNTER3_LOW regVGT_PERFCOUNTER3_LOW; +typedef union VGT_PERFCOUNTER0_HI regVGT_PERFCOUNTER0_HI; +typedef union VGT_PERFCOUNTER1_HI regVGT_PERFCOUNTER1_HI; +typedef union VGT_PERFCOUNTER2_HI regVGT_PERFCOUNTER2_HI; +typedef union VGT_PERFCOUNTER3_HI regVGT_PERFCOUNTER3_HI; +typedef union TC_CNTL_STATUS regTC_CNTL_STATUS; +typedef union TCR_CHICKEN regTCR_CHICKEN; +typedef union TCF_CHICKEN regTCF_CHICKEN; +typedef union TCM_CHICKEN regTCM_CHICKEN; +typedef union TCR_PERFCOUNTER0_SELECT regTCR_PERFCOUNTER0_SELECT; +typedef union TCR_PERFCOUNTER1_SELECT regTCR_PERFCOUNTER1_SELECT; +typedef union TCR_PERFCOUNTER0_HI regTCR_PERFCOUNTER0_HI; +typedef union TCR_PERFCOUNTER1_HI regTCR_PERFCOUNTER1_HI; +typedef union TCR_PERFCOUNTER0_LOW regTCR_PERFCOUNTER0_LOW; +typedef union TCR_PERFCOUNTER1_LOW regTCR_PERFCOUNTER1_LOW; +typedef union TP_TC_CLKGATE_CNTL regTP_TC_CLKGATE_CNTL; +typedef union TPC_CNTL_STATUS regTPC_CNTL_STATUS; +typedef union TPC_DEBUG0 regTPC_DEBUG0; +typedef union TPC_DEBUG1 regTPC_DEBUG1; +typedef union TPC_CHICKEN regTPC_CHICKEN; +typedef union TP0_CNTL_STATUS regTP0_CNTL_STATUS; +typedef union TP0_DEBUG regTP0_DEBUG; +typedef union TP0_CHICKEN regTP0_CHICKEN; +typedef union TP0_PERFCOUNTER0_SELECT regTP0_PERFCOUNTER0_SELECT; +typedef union TP0_PERFCOUNTER0_HI regTP0_PERFCOUNTER0_HI; +typedef union TP0_PERFCOUNTER0_LOW regTP0_PERFCOUNTER0_LOW; +typedef union TP0_PERFCOUNTER1_SELECT regTP0_PERFCOUNTER1_SELECT; +typedef union TP0_PERFCOUNTER1_HI regTP0_PERFCOUNTER1_HI; +typedef union TP0_PERFCOUNTER1_LOW regTP0_PERFCOUNTER1_LOW; +typedef union TCM_PERFCOUNTER0_SELECT regTCM_PERFCOUNTER0_SELECT; +typedef union TCM_PERFCOUNTER1_SELECT regTCM_PERFCOUNTER1_SELECT; +typedef union TCM_PERFCOUNTER0_HI regTCM_PERFCOUNTER0_HI; +typedef union TCM_PERFCOUNTER1_HI regTCM_PERFCOUNTER1_HI; +typedef union TCM_PERFCOUNTER0_LOW regTCM_PERFCOUNTER0_LOW; +typedef union TCM_PERFCOUNTER1_LOW regTCM_PERFCOUNTER1_LOW; +typedef union TCF_PERFCOUNTER0_SELECT regTCF_PERFCOUNTER0_SELECT; +typedef union TCF_PERFCOUNTER1_SELECT regTCF_PERFCOUNTER1_SELECT; +typedef union TCF_PERFCOUNTER2_SELECT regTCF_PERFCOUNTER2_SELECT; +typedef union TCF_PERFCOUNTER3_SELECT regTCF_PERFCOUNTER3_SELECT; +typedef union TCF_PERFCOUNTER4_SELECT regTCF_PERFCOUNTER4_SELECT; +typedef union TCF_PERFCOUNTER5_SELECT regTCF_PERFCOUNTER5_SELECT; +typedef union TCF_PERFCOUNTER6_SELECT regTCF_PERFCOUNTER6_SELECT; +typedef union TCF_PERFCOUNTER7_SELECT regTCF_PERFCOUNTER7_SELECT; +typedef union TCF_PERFCOUNTER8_SELECT regTCF_PERFCOUNTER8_SELECT; +typedef union TCF_PERFCOUNTER9_SELECT regTCF_PERFCOUNTER9_SELECT; +typedef union TCF_PERFCOUNTER10_SELECT regTCF_PERFCOUNTER10_SELECT; +typedef union TCF_PERFCOUNTER11_SELECT regTCF_PERFCOUNTER11_SELECT; +typedef union TCF_PERFCOUNTER0_HI regTCF_PERFCOUNTER0_HI; +typedef union TCF_PERFCOUNTER1_HI regTCF_PERFCOUNTER1_HI; +typedef union TCF_PERFCOUNTER2_HI regTCF_PERFCOUNTER2_HI; +typedef union TCF_PERFCOUNTER3_HI regTCF_PERFCOUNTER3_HI; +typedef union TCF_PERFCOUNTER4_HI regTCF_PERFCOUNTER4_HI; +typedef union TCF_PERFCOUNTER5_HI regTCF_PERFCOUNTER5_HI; +typedef union TCF_PERFCOUNTER6_HI regTCF_PERFCOUNTER6_HI; +typedef union TCF_PERFCOUNTER7_HI regTCF_PERFCOUNTER7_HI; +typedef union TCF_PERFCOUNTER8_HI regTCF_PERFCOUNTER8_HI; +typedef union TCF_PERFCOUNTER9_HI regTCF_PERFCOUNTER9_HI; +typedef union TCF_PERFCOUNTER10_HI regTCF_PERFCOUNTER10_HI; +typedef union TCF_PERFCOUNTER11_HI regTCF_PERFCOUNTER11_HI; +typedef union TCF_PERFCOUNTER0_LOW regTCF_PERFCOUNTER0_LOW; +typedef union TCF_PERFCOUNTER1_LOW regTCF_PERFCOUNTER1_LOW; +typedef union TCF_PERFCOUNTER2_LOW regTCF_PERFCOUNTER2_LOW; +typedef union TCF_PERFCOUNTER3_LOW regTCF_PERFCOUNTER3_LOW; +typedef union TCF_PERFCOUNTER4_LOW regTCF_PERFCOUNTER4_LOW; +typedef union TCF_PERFCOUNTER5_LOW regTCF_PERFCOUNTER5_LOW; +typedef union TCF_PERFCOUNTER6_LOW regTCF_PERFCOUNTER6_LOW; +typedef union TCF_PERFCOUNTER7_LOW regTCF_PERFCOUNTER7_LOW; +typedef union TCF_PERFCOUNTER8_LOW regTCF_PERFCOUNTER8_LOW; +typedef union TCF_PERFCOUNTER9_LOW regTCF_PERFCOUNTER9_LOW; +typedef union TCF_PERFCOUNTER10_LOW regTCF_PERFCOUNTER10_LOW; +typedef union TCF_PERFCOUNTER11_LOW regTCF_PERFCOUNTER11_LOW; +typedef union TCF_DEBUG regTCF_DEBUG; +typedef union TCA_FIFO_DEBUG regTCA_FIFO_DEBUG; +typedef union TCA_PROBE_DEBUG regTCA_PROBE_DEBUG; +typedef union TCA_TPC_DEBUG regTCA_TPC_DEBUG; +typedef union TCB_CORE_DEBUG regTCB_CORE_DEBUG; +typedef union TCB_TAG0_DEBUG regTCB_TAG0_DEBUG; +typedef union TCB_TAG1_DEBUG regTCB_TAG1_DEBUG; +typedef union TCB_TAG2_DEBUG regTCB_TAG2_DEBUG; +typedef union TCB_TAG3_DEBUG regTCB_TAG3_DEBUG; +typedef union TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG regTCB_FETCH_GEN_SECTOR_WALKER0_DEBUG; +typedef union TCB_FETCH_GEN_WALKER_DEBUG regTCB_FETCH_GEN_WALKER_DEBUG; +typedef union TCB_FETCH_GEN_PIPE0_DEBUG regTCB_FETCH_GEN_PIPE0_DEBUG; +typedef union TCD_INPUT0_DEBUG regTCD_INPUT0_DEBUG; +typedef union TCD_DEGAMMA_DEBUG regTCD_DEGAMMA_DEBUG; +typedef union TCD_DXTMUX_SCTARB_DEBUG regTCD_DXTMUX_SCTARB_DEBUG; +typedef union TCD_DXTC_ARB_DEBUG regTCD_DXTC_ARB_DEBUG; +typedef union TCD_STALLS_DEBUG regTCD_STALLS_DEBUG; +typedef union TCO_STALLS_DEBUG regTCO_STALLS_DEBUG; +typedef union TCO_QUAD0_DEBUG0 regTCO_QUAD0_DEBUG0; +typedef union TCO_QUAD0_DEBUG1 regTCO_QUAD0_DEBUG1; +typedef union SQ_GPR_MANAGEMENT regSQ_GPR_MANAGEMENT; +typedef union SQ_FLOW_CONTROL regSQ_FLOW_CONTROL; +typedef union SQ_INST_STORE_MANAGMENT regSQ_INST_STORE_MANAGMENT; +typedef union SQ_RESOURCE_MANAGMENT regSQ_RESOURCE_MANAGMENT; +typedef union SQ_EO_RT regSQ_EO_RT; +typedef union SQ_DEBUG_MISC regSQ_DEBUG_MISC; +typedef union SQ_ACTIVITY_METER_CNTL regSQ_ACTIVITY_METER_CNTL; +typedef union SQ_ACTIVITY_METER_STATUS regSQ_ACTIVITY_METER_STATUS; +typedef union SQ_INPUT_ARB_PRIORITY regSQ_INPUT_ARB_PRIORITY; +typedef union SQ_THREAD_ARB_PRIORITY regSQ_THREAD_ARB_PRIORITY; +typedef union SQ_DEBUG_INPUT_FSM regSQ_DEBUG_INPUT_FSM; +typedef union SQ_DEBUG_CONST_MGR_FSM regSQ_DEBUG_CONST_MGR_FSM; +typedef union SQ_DEBUG_TP_FSM regSQ_DEBUG_TP_FSM; +typedef union SQ_DEBUG_FSM_ALU_0 regSQ_DEBUG_FSM_ALU_0; +typedef union SQ_DEBUG_FSM_ALU_1 regSQ_DEBUG_FSM_ALU_1; +typedef union SQ_DEBUG_EXP_ALLOC regSQ_DEBUG_EXP_ALLOC; +typedef union SQ_DEBUG_PTR_BUFF regSQ_DEBUG_PTR_BUFF; +typedef union SQ_DEBUG_GPR_VTX regSQ_DEBUG_GPR_VTX; +typedef union SQ_DEBUG_GPR_PIX regSQ_DEBUG_GPR_PIX; +typedef union SQ_DEBUG_TB_STATUS_SEL regSQ_DEBUG_TB_STATUS_SEL; +typedef union SQ_DEBUG_VTX_TB_0 regSQ_DEBUG_VTX_TB_0; +typedef union SQ_DEBUG_VTX_TB_1 regSQ_DEBUG_VTX_TB_1; +typedef union SQ_DEBUG_VTX_TB_STATUS_REG regSQ_DEBUG_VTX_TB_STATUS_REG; +typedef union SQ_DEBUG_VTX_TB_STATE_MEM regSQ_DEBUG_VTX_TB_STATE_MEM; +typedef union SQ_DEBUG_PIX_TB_0 regSQ_DEBUG_PIX_TB_0; +typedef union SQ_DEBUG_PIX_TB_STATUS_REG_0 regSQ_DEBUG_PIX_TB_STATUS_REG_0; +typedef union SQ_DEBUG_PIX_TB_STATUS_REG_1 regSQ_DEBUG_PIX_TB_STATUS_REG_1; +typedef union SQ_DEBUG_PIX_TB_STATUS_REG_2 regSQ_DEBUG_PIX_TB_STATUS_REG_2; +typedef union SQ_DEBUG_PIX_TB_STATUS_REG_3 regSQ_DEBUG_PIX_TB_STATUS_REG_3; +typedef union SQ_DEBUG_PIX_TB_STATE_MEM regSQ_DEBUG_PIX_TB_STATE_MEM; +typedef union SQ_PERFCOUNTER0_SELECT regSQ_PERFCOUNTER0_SELECT; +typedef union SQ_PERFCOUNTER1_SELECT regSQ_PERFCOUNTER1_SELECT; +typedef union SQ_PERFCOUNTER2_SELECT regSQ_PERFCOUNTER2_SELECT; +typedef union SQ_PERFCOUNTER3_SELECT regSQ_PERFCOUNTER3_SELECT; +typedef union SQ_PERFCOUNTER0_LOW regSQ_PERFCOUNTER0_LOW; +typedef union SQ_PERFCOUNTER0_HI regSQ_PERFCOUNTER0_HI; +typedef union SQ_PERFCOUNTER1_LOW regSQ_PERFCOUNTER1_LOW; +typedef union SQ_PERFCOUNTER1_HI regSQ_PERFCOUNTER1_HI; +typedef union SQ_PERFCOUNTER2_LOW regSQ_PERFCOUNTER2_LOW; +typedef union SQ_PERFCOUNTER2_HI regSQ_PERFCOUNTER2_HI; +typedef union SQ_PERFCOUNTER3_LOW regSQ_PERFCOUNTER3_LOW; +typedef union SQ_PERFCOUNTER3_HI regSQ_PERFCOUNTER3_HI; +typedef union SX_PERFCOUNTER0_SELECT regSX_PERFCOUNTER0_SELECT; +typedef union SX_PERFCOUNTER0_LOW regSX_PERFCOUNTER0_LOW; +typedef union SX_PERFCOUNTER0_HI regSX_PERFCOUNTER0_HI; +typedef union SQ_INSTRUCTION_ALU_0 regSQ_INSTRUCTION_ALU_0; +typedef union SQ_INSTRUCTION_ALU_1 regSQ_INSTRUCTION_ALU_1; +typedef union SQ_INSTRUCTION_ALU_2 regSQ_INSTRUCTION_ALU_2; +typedef union SQ_INSTRUCTION_CF_EXEC_0 regSQ_INSTRUCTION_CF_EXEC_0; +typedef union SQ_INSTRUCTION_CF_EXEC_1 regSQ_INSTRUCTION_CF_EXEC_1; +typedef union SQ_INSTRUCTION_CF_EXEC_2 regSQ_INSTRUCTION_CF_EXEC_2; +typedef union SQ_INSTRUCTION_CF_LOOP_0 regSQ_INSTRUCTION_CF_LOOP_0; +typedef union SQ_INSTRUCTION_CF_LOOP_1 regSQ_INSTRUCTION_CF_LOOP_1; +typedef union SQ_INSTRUCTION_CF_LOOP_2 regSQ_INSTRUCTION_CF_LOOP_2; +typedef union SQ_INSTRUCTION_CF_JMP_CALL_0 regSQ_INSTRUCTION_CF_JMP_CALL_0; +typedef union SQ_INSTRUCTION_CF_JMP_CALL_1 regSQ_INSTRUCTION_CF_JMP_CALL_1; +typedef union SQ_INSTRUCTION_CF_JMP_CALL_2 regSQ_INSTRUCTION_CF_JMP_CALL_2; +typedef union SQ_INSTRUCTION_CF_ALLOC_0 regSQ_INSTRUCTION_CF_ALLOC_0; +typedef union SQ_INSTRUCTION_CF_ALLOC_1 regSQ_INSTRUCTION_CF_ALLOC_1; +typedef union SQ_INSTRUCTION_CF_ALLOC_2 regSQ_INSTRUCTION_CF_ALLOC_2; +typedef union SQ_INSTRUCTION_TFETCH_0 regSQ_INSTRUCTION_TFETCH_0; +typedef union SQ_INSTRUCTION_TFETCH_1 regSQ_INSTRUCTION_TFETCH_1; +typedef union SQ_INSTRUCTION_TFETCH_2 regSQ_INSTRUCTION_TFETCH_2; +typedef union SQ_INSTRUCTION_VFETCH_0 regSQ_INSTRUCTION_VFETCH_0; +typedef union SQ_INSTRUCTION_VFETCH_1 regSQ_INSTRUCTION_VFETCH_1; +typedef union SQ_INSTRUCTION_VFETCH_2 regSQ_INSTRUCTION_VFETCH_2; +typedef union SQ_CONSTANT_0 regSQ_CONSTANT_0; +typedef union SQ_CONSTANT_1 regSQ_CONSTANT_1; +typedef union SQ_CONSTANT_2 regSQ_CONSTANT_2; +typedef union SQ_CONSTANT_3 regSQ_CONSTANT_3; +typedef union SQ_FETCH_0 regSQ_FETCH_0; +typedef union SQ_FETCH_1 regSQ_FETCH_1; +typedef union SQ_FETCH_2 regSQ_FETCH_2; +typedef union SQ_FETCH_3 regSQ_FETCH_3; +typedef union SQ_FETCH_4 regSQ_FETCH_4; +typedef union SQ_FETCH_5 regSQ_FETCH_5; +typedef union SQ_CONSTANT_VFETCH_0 regSQ_CONSTANT_VFETCH_0; +typedef union SQ_CONSTANT_VFETCH_1 regSQ_CONSTANT_VFETCH_1; +typedef union SQ_CONSTANT_T2 regSQ_CONSTANT_T2; +typedef union SQ_CONSTANT_T3 regSQ_CONSTANT_T3; +typedef union SQ_CF_BOOLEANS regSQ_CF_BOOLEANS; +typedef union SQ_CF_LOOP regSQ_CF_LOOP; +typedef union SQ_CONSTANT_RT_0 regSQ_CONSTANT_RT_0; +typedef union SQ_CONSTANT_RT_1 regSQ_CONSTANT_RT_1; +typedef union SQ_CONSTANT_RT_2 regSQ_CONSTANT_RT_2; +typedef union SQ_CONSTANT_RT_3 regSQ_CONSTANT_RT_3; +typedef union SQ_FETCH_RT_0 regSQ_FETCH_RT_0; +typedef union SQ_FETCH_RT_1 regSQ_FETCH_RT_1; +typedef union SQ_FETCH_RT_2 regSQ_FETCH_RT_2; +typedef union SQ_FETCH_RT_3 regSQ_FETCH_RT_3; +typedef union SQ_FETCH_RT_4 regSQ_FETCH_RT_4; +typedef union SQ_FETCH_RT_5 regSQ_FETCH_RT_5; +typedef union SQ_CF_RT_BOOLEANS regSQ_CF_RT_BOOLEANS; +typedef union SQ_CF_RT_LOOP regSQ_CF_RT_LOOP; +typedef union SQ_VS_PROGRAM regSQ_VS_PROGRAM; +typedef union SQ_PS_PROGRAM regSQ_PS_PROGRAM; +typedef union SQ_CF_PROGRAM_SIZE regSQ_CF_PROGRAM_SIZE; +typedef union SQ_INTERPOLATOR_CNTL regSQ_INTERPOLATOR_CNTL; +typedef union SQ_PROGRAM_CNTL regSQ_PROGRAM_CNTL; +typedef union SQ_WRAPPING_0 regSQ_WRAPPING_0; +typedef union SQ_WRAPPING_1 regSQ_WRAPPING_1; +typedef union SQ_VS_CONST regSQ_VS_CONST; +typedef union SQ_PS_CONST regSQ_PS_CONST; +typedef union SQ_CONTEXT_MISC regSQ_CONTEXT_MISC; +typedef union SQ_CF_RD_BASE regSQ_CF_RD_BASE; +typedef union SQ_DEBUG_MISC_0 regSQ_DEBUG_MISC_0; +typedef union SQ_DEBUG_MISC_1 regSQ_DEBUG_MISC_1; +typedef union MH_ARBITER_CONFIG regMH_ARBITER_CONFIG; +typedef union MH_CLNT_AXI_ID_REUSE regMH_CLNT_AXI_ID_REUSE; +typedef union MH_INTERRUPT_MASK regMH_INTERRUPT_MASK; +typedef union MH_INTERRUPT_STATUS regMH_INTERRUPT_STATUS; +typedef union MH_INTERRUPT_CLEAR regMH_INTERRUPT_CLEAR; +typedef union MH_AXI_ERROR regMH_AXI_ERROR; +typedef union MH_PERFCOUNTER0_SELECT regMH_PERFCOUNTER0_SELECT; +typedef union MH_PERFCOUNTER1_SELECT regMH_PERFCOUNTER1_SELECT; +typedef union MH_PERFCOUNTER0_CONFIG regMH_PERFCOUNTER0_CONFIG; +typedef union MH_PERFCOUNTER1_CONFIG regMH_PERFCOUNTER1_CONFIG; +typedef union MH_PERFCOUNTER0_LOW regMH_PERFCOUNTER0_LOW; +typedef union MH_PERFCOUNTER1_LOW regMH_PERFCOUNTER1_LOW; +typedef union MH_PERFCOUNTER0_HI regMH_PERFCOUNTER0_HI; +typedef union MH_PERFCOUNTER1_HI regMH_PERFCOUNTER1_HI; +typedef union MH_DEBUG_CTRL regMH_DEBUG_CTRL; +typedef union MH_DEBUG_DATA regMH_DEBUG_DATA; +typedef union MH_MMU_CONFIG regMH_MMU_CONFIG; +typedef union MH_MMU_VA_RANGE regMH_MMU_VA_RANGE; +typedef union MH_MMU_PT_BASE regMH_MMU_PT_BASE; +typedef union MH_MMU_PAGE_FAULT regMH_MMU_PAGE_FAULT; +typedef union MH_MMU_TRAN_ERROR regMH_MMU_TRAN_ERROR; +typedef union MH_MMU_INVALIDATE regMH_MMU_INVALIDATE; +typedef union MH_MMU_MPU_BASE regMH_MMU_MPU_BASE; +typedef union MH_MMU_MPU_END regMH_MMU_MPU_END; +typedef union WAIT_UNTIL regWAIT_UNTIL; +typedef union RBBM_ISYNC_CNTL regRBBM_ISYNC_CNTL; +typedef union RBBM_STATUS regRBBM_STATUS; +typedef union RBBM_DSPLY regRBBM_DSPLY; +typedef union RBBM_RENDER_LATEST regRBBM_RENDER_LATEST; +typedef union RBBM_RTL_RELEASE regRBBM_RTL_RELEASE; +typedef union RBBM_PATCH_RELEASE regRBBM_PATCH_RELEASE; +typedef union RBBM_AUXILIARY_CONFIG regRBBM_AUXILIARY_CONFIG; +typedef union RBBM_PERIPHID0 regRBBM_PERIPHID0; +typedef union RBBM_PERIPHID1 regRBBM_PERIPHID1; +typedef union RBBM_PERIPHID2 regRBBM_PERIPHID2; +typedef union RBBM_PERIPHID3 regRBBM_PERIPHID3; +typedef union RBBM_CNTL regRBBM_CNTL; +typedef union RBBM_SKEW_CNTL regRBBM_SKEW_CNTL; +typedef union RBBM_SOFT_RESET regRBBM_SOFT_RESET; +typedef union RBBM_PM_OVERRIDE1 regRBBM_PM_OVERRIDE1; +typedef union RBBM_PM_OVERRIDE2 regRBBM_PM_OVERRIDE2; +typedef union GC_SYS_IDLE regGC_SYS_IDLE; +typedef union NQWAIT_UNTIL regNQWAIT_UNTIL; +typedef union RBBM_DEBUG regRBBM_DEBUG; +typedef union RBBM_READ_ERROR regRBBM_READ_ERROR; +typedef union RBBM_WAIT_IDLE_CLOCKS regRBBM_WAIT_IDLE_CLOCKS; +typedef union RBBM_INT_CNTL regRBBM_INT_CNTL; +typedef union RBBM_INT_STATUS regRBBM_INT_STATUS; +typedef union RBBM_INT_ACK regRBBM_INT_ACK; +typedef union MASTER_INT_SIGNAL regMASTER_INT_SIGNAL; +typedef union RBBM_PERFCOUNTER1_SELECT regRBBM_PERFCOUNTER1_SELECT; +typedef union RBBM_PERFCOUNTER1_LO regRBBM_PERFCOUNTER1_LO; +typedef union RBBM_PERFCOUNTER1_HI regRBBM_PERFCOUNTER1_HI; +typedef union CP_RB_BASE regCP_RB_BASE; +typedef union CP_RB_CNTL regCP_RB_CNTL; +typedef union CP_RB_RPTR_ADDR regCP_RB_RPTR_ADDR; +typedef union CP_RB_RPTR regCP_RB_RPTR; +typedef union CP_RB_RPTR_WR regCP_RB_RPTR_WR; +typedef union CP_RB_WPTR regCP_RB_WPTR; +typedef union CP_RB_WPTR_DELAY regCP_RB_WPTR_DELAY; +typedef union CP_RB_WPTR_BASE regCP_RB_WPTR_BASE; +typedef union CP_IB1_BASE regCP_IB1_BASE; +typedef union CP_IB1_BUFSZ regCP_IB1_BUFSZ; +typedef union CP_IB2_BASE regCP_IB2_BASE; +typedef union CP_IB2_BUFSZ regCP_IB2_BUFSZ; +typedef union CP_ST_BASE regCP_ST_BASE; +typedef union CP_ST_BUFSZ regCP_ST_BUFSZ; +typedef union CP_QUEUE_THRESHOLDS regCP_QUEUE_THRESHOLDS; +typedef union CP_MEQ_THRESHOLDS regCP_MEQ_THRESHOLDS; +typedef union CP_CSQ_AVAIL regCP_CSQ_AVAIL; +typedef union CP_STQ_AVAIL regCP_STQ_AVAIL; +typedef union CP_MEQ_AVAIL regCP_MEQ_AVAIL; +typedef union CP_CSQ_RB_STAT regCP_CSQ_RB_STAT; +typedef union CP_CSQ_IB1_STAT regCP_CSQ_IB1_STAT; +typedef union CP_CSQ_IB2_STAT regCP_CSQ_IB2_STAT; +typedef union CP_NON_PREFETCH_CNTRS regCP_NON_PREFETCH_CNTRS; +typedef union CP_STQ_ST_STAT regCP_STQ_ST_STAT; +typedef union CP_MEQ_STAT regCP_MEQ_STAT; +typedef union CP_MIU_TAG_STAT regCP_MIU_TAG_STAT; +typedef union CP_CMD_INDEX regCP_CMD_INDEX; +typedef union CP_CMD_DATA regCP_CMD_DATA; +typedef union CP_ME_CNTL regCP_ME_CNTL; +typedef union CP_ME_STATUS regCP_ME_STATUS; +typedef union CP_ME_RAM_WADDR regCP_ME_RAM_WADDR; +typedef union CP_ME_RAM_RADDR regCP_ME_RAM_RADDR; +typedef union CP_ME_RAM_DATA regCP_ME_RAM_DATA; +typedef union CP_ME_RDADDR regCP_ME_RDADDR; +typedef union CP_DEBUG regCP_DEBUG; +typedef union SCRATCH_REG0 regSCRATCH_REG0; +typedef union GUI_SCRATCH_REG0 regGUI_SCRATCH_REG0; +typedef union SCRATCH_REG1 regSCRATCH_REG1; +typedef union GUI_SCRATCH_REG1 regGUI_SCRATCH_REG1; +typedef union SCRATCH_REG2 regSCRATCH_REG2; +typedef union GUI_SCRATCH_REG2 regGUI_SCRATCH_REG2; +typedef union SCRATCH_REG3 regSCRATCH_REG3; +typedef union GUI_SCRATCH_REG3 regGUI_SCRATCH_REG3; +typedef union SCRATCH_REG4 regSCRATCH_REG4; +typedef union GUI_SCRATCH_REG4 regGUI_SCRATCH_REG4; +typedef union SCRATCH_REG5 regSCRATCH_REG5; +typedef union GUI_SCRATCH_REG5 regGUI_SCRATCH_REG5; +typedef union SCRATCH_REG6 regSCRATCH_REG6; +typedef union GUI_SCRATCH_REG6 regGUI_SCRATCH_REG6; +typedef union SCRATCH_REG7 regSCRATCH_REG7; +typedef union GUI_SCRATCH_REG7 regGUI_SCRATCH_REG7; +typedef union SCRATCH_UMSK regSCRATCH_UMSK; +typedef union SCRATCH_ADDR regSCRATCH_ADDR; +typedef union CP_ME_VS_EVENT_SRC regCP_ME_VS_EVENT_SRC; +typedef union CP_ME_VS_EVENT_ADDR regCP_ME_VS_EVENT_ADDR; +typedef union CP_ME_VS_EVENT_DATA regCP_ME_VS_EVENT_DATA; +typedef union CP_ME_VS_EVENT_ADDR_SWM regCP_ME_VS_EVENT_ADDR_SWM; +typedef union CP_ME_VS_EVENT_DATA_SWM regCP_ME_VS_EVENT_DATA_SWM; +typedef union CP_ME_PS_EVENT_SRC regCP_ME_PS_EVENT_SRC; +typedef union CP_ME_PS_EVENT_ADDR regCP_ME_PS_EVENT_ADDR; +typedef union CP_ME_PS_EVENT_DATA regCP_ME_PS_EVENT_DATA; +typedef union CP_ME_PS_EVENT_ADDR_SWM regCP_ME_PS_EVENT_ADDR_SWM; +typedef union CP_ME_PS_EVENT_DATA_SWM regCP_ME_PS_EVENT_DATA_SWM; +typedef union CP_ME_CF_EVENT_SRC regCP_ME_CF_EVENT_SRC; +typedef union CP_ME_CF_EVENT_ADDR regCP_ME_CF_EVENT_ADDR; +typedef union CP_ME_CF_EVENT_DATA regCP_ME_CF_EVENT_DATA; +typedef union CP_ME_NRT_ADDR regCP_ME_NRT_ADDR; +typedef union CP_ME_NRT_DATA regCP_ME_NRT_DATA; +typedef union CP_ME_VS_FETCH_DONE_SRC regCP_ME_VS_FETCH_DONE_SRC; +typedef union CP_ME_VS_FETCH_DONE_ADDR regCP_ME_VS_FETCH_DONE_ADDR; +typedef union CP_ME_VS_FETCH_DONE_DATA regCP_ME_VS_FETCH_DONE_DATA; +typedef union CP_INT_CNTL regCP_INT_CNTL; +typedef union CP_INT_STATUS regCP_INT_STATUS; +typedef union CP_INT_ACK regCP_INT_ACK; +typedef union CP_PFP_UCODE_ADDR regCP_PFP_UCODE_ADDR; +typedef union CP_PFP_UCODE_DATA regCP_PFP_UCODE_DATA; +typedef union CP_PERFMON_CNTL regCP_PERFMON_CNTL; +typedef union CP_PERFCOUNTER_SELECT regCP_PERFCOUNTER_SELECT; +typedef union CP_PERFCOUNTER_LO regCP_PERFCOUNTER_LO; +typedef union CP_PERFCOUNTER_HI regCP_PERFCOUNTER_HI; +typedef union CP_BIN_MASK_LO regCP_BIN_MASK_LO; +typedef union CP_BIN_MASK_HI regCP_BIN_MASK_HI; +typedef union CP_BIN_SELECT_LO regCP_BIN_SELECT_LO; +typedef union CP_BIN_SELECT_HI regCP_BIN_SELECT_HI; +typedef union CP_NV_FLAGS_0 regCP_NV_FLAGS_0; +typedef union CP_NV_FLAGS_1 regCP_NV_FLAGS_1; +typedef union CP_NV_FLAGS_2 regCP_NV_FLAGS_2; +typedef union CP_NV_FLAGS_3 regCP_NV_FLAGS_3; +typedef union CP_STATE_DEBUG_INDEX regCP_STATE_DEBUG_INDEX; +typedef union CP_STATE_DEBUG_DATA regCP_STATE_DEBUG_DATA; +typedef union CP_PROG_COUNTER regCP_PROG_COUNTER; +typedef union CP_STAT regCP_STAT; +typedef union BIOS_0_SCRATCH regBIOS_0_SCRATCH; +typedef union BIOS_1_SCRATCH regBIOS_1_SCRATCH; +typedef union BIOS_2_SCRATCH regBIOS_2_SCRATCH; +typedef union BIOS_3_SCRATCH regBIOS_3_SCRATCH; +typedef union BIOS_4_SCRATCH regBIOS_4_SCRATCH; +typedef union BIOS_5_SCRATCH regBIOS_5_SCRATCH; +typedef union BIOS_6_SCRATCH regBIOS_6_SCRATCH; +typedef union BIOS_7_SCRATCH regBIOS_7_SCRATCH; +typedef union BIOS_8_SCRATCH regBIOS_8_SCRATCH; +typedef union BIOS_9_SCRATCH regBIOS_9_SCRATCH; +typedef union BIOS_10_SCRATCH regBIOS_10_SCRATCH; +typedef union BIOS_11_SCRATCH regBIOS_11_SCRATCH; +typedef union BIOS_12_SCRATCH regBIOS_12_SCRATCH; +typedef union BIOS_13_SCRATCH regBIOS_13_SCRATCH; +typedef union BIOS_14_SCRATCH regBIOS_14_SCRATCH; +typedef union BIOS_15_SCRATCH regBIOS_15_SCRATCH; +typedef union COHER_SIZE_PM4 regCOHER_SIZE_PM4; +typedef union COHER_BASE_PM4 regCOHER_BASE_PM4; +typedef union COHER_STATUS_PM4 regCOHER_STATUS_PM4; +typedef union COHER_SIZE_HOST regCOHER_SIZE_HOST; +typedef union COHER_BASE_HOST regCOHER_BASE_HOST; +typedef union COHER_STATUS_HOST regCOHER_STATUS_HOST; +typedef union COHER_DEST_BASE_0 regCOHER_DEST_BASE_0; +typedef union COHER_DEST_BASE_1 regCOHER_DEST_BASE_1; +typedef union COHER_DEST_BASE_2 regCOHER_DEST_BASE_2; +typedef union COHER_DEST_BASE_3 regCOHER_DEST_BASE_3; +typedef union COHER_DEST_BASE_4 regCOHER_DEST_BASE_4; +typedef union COHER_DEST_BASE_5 regCOHER_DEST_BASE_5; +typedef union COHER_DEST_BASE_6 regCOHER_DEST_BASE_6; +typedef union COHER_DEST_BASE_7 regCOHER_DEST_BASE_7; +typedef union RB_SURFACE_INFO regRB_SURFACE_INFO; +typedef union RB_COLOR_INFO regRB_COLOR_INFO; +typedef union RB_DEPTH_INFO regRB_DEPTH_INFO; +typedef union RB_STENCILREFMASK regRB_STENCILREFMASK; +typedef union RB_ALPHA_REF regRB_ALPHA_REF; +typedef union RB_COLOR_MASK regRB_COLOR_MASK; +typedef union RB_BLEND_RED regRB_BLEND_RED; +typedef union RB_BLEND_GREEN regRB_BLEND_GREEN; +typedef union RB_BLEND_BLUE regRB_BLEND_BLUE; +typedef union RB_BLEND_ALPHA regRB_BLEND_ALPHA; +typedef union RB_FOG_COLOR regRB_FOG_COLOR; +typedef union RB_STENCILREFMASK_BF regRB_STENCILREFMASK_BF; +typedef union RB_DEPTHCONTROL regRB_DEPTHCONTROL; +typedef union RB_BLENDCONTROL regRB_BLENDCONTROL; +typedef union RB_COLORCONTROL regRB_COLORCONTROL; +typedef union RB_MODECONTROL regRB_MODECONTROL; +typedef union RB_COLOR_DEST_MASK regRB_COLOR_DEST_MASK; +typedef union RB_COPY_CONTROL regRB_COPY_CONTROL; +typedef union RB_COPY_DEST_BASE regRB_COPY_DEST_BASE; +typedef union RB_COPY_DEST_PITCH regRB_COPY_DEST_PITCH; +typedef union RB_COPY_DEST_INFO regRB_COPY_DEST_INFO; +typedef union RB_COPY_DEST_PIXEL_OFFSET regRB_COPY_DEST_PIXEL_OFFSET; +typedef union RB_DEPTH_CLEAR regRB_DEPTH_CLEAR; +typedef union RB_SAMPLE_COUNT_CTL regRB_SAMPLE_COUNT_CTL; +typedef union RB_SAMPLE_COUNT_ADDR regRB_SAMPLE_COUNT_ADDR; +typedef union RB_BC_CONTROL regRB_BC_CONTROL; +typedef union RB_EDRAM_INFO regRB_EDRAM_INFO; +typedef union RB_CRC_RD_PORT regRB_CRC_RD_PORT; +typedef union RB_CRC_CONTROL regRB_CRC_CONTROL; +typedef union RB_CRC_MASK regRB_CRC_MASK; +typedef union RB_PERFCOUNTER0_SELECT regRB_PERFCOUNTER0_SELECT; +typedef union RB_PERFCOUNTER0_LOW regRB_PERFCOUNTER0_LOW; +typedef union RB_PERFCOUNTER0_HI regRB_PERFCOUNTER0_HI; +typedef union RB_TOTAL_SAMPLES regRB_TOTAL_SAMPLES; +typedef union RB_ZPASS_SAMPLES regRB_ZPASS_SAMPLES; +typedef union RB_ZFAIL_SAMPLES regRB_ZFAIL_SAMPLES; +typedef union RB_SFAIL_SAMPLES regRB_SFAIL_SAMPLES; +typedef union RB_DEBUG_0 regRB_DEBUG_0; +typedef union RB_DEBUG_1 regRB_DEBUG_1; +typedef union RB_DEBUG_2 regRB_DEBUG_2; +typedef union RB_DEBUG_3 regRB_DEBUG_3; +typedef union RB_DEBUG_4 regRB_DEBUG_4; +typedef union RB_FLAG_CONTROL regRB_FLAG_CONTROL; +typedef union BC_DUMMY_CRAYRB_ENUMS regBC_DUMMY_CRAYRB_ENUMS; +typedef union BC_DUMMY_CRAYRB_MOREENUMS regBC_DUMMY_CRAYRB_MOREENUMS; +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_enum.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_enum.h new file mode 100644 index 000000000000..15cfbebf2907 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_enum.h @@ -0,0 +1,1897 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_ENUM_HEADER) +#define _yamato_ENUM_HEADER + + + +#ifndef _DRIVER_BUILD +#ifndef GL_ZERO +#define GL__ZERO BLEND_ZERO +#define GL__ONE BLEND_ONE +#define GL__SRC_COLOR BLEND_SRC_COLOR +#define GL__ONE_MINUS_SRC_COLOR BLEND_ONE_MINUS_SRC_COLOR +#define GL__DST_COLOR BLEND_DST_COLOR +#define GL__ONE_MINUS_DST_COLOR BLEND_ONE_MINUS_DST_COLOR +#define GL__SRC_ALPHA BLEND_SRC_ALPHA +#define GL__ONE_MINUS_SRC_ALPHA BLEND_ONE_MINUS_SRC_ALPHA +#define GL__DST_ALPHA BLEND_DST_ALPHA +#define GL__ONE_MINUS_DST_ALPHA BLEND_ONE_MINUS_DST_ALPHA +#define GL__SRC_ALPHA_SATURATE BLEND_SRC_ALPHA_SATURATE +#define GL__CONSTANT_COLOR BLEND_CONSTANT_COLOR +#define GL__ONE_MINUS_CONSTANT_COLOR BLEND_ONE_MINUS_CONSTANT_COLOR +#define GL__CONSTANT_ALPHA BLEND_CONSTANT_ALPHA +#define GL__ONE_MINUS_CONSTANT_ALPHA BLEND_ONE_MINUS_CONSTANT_ALPHA +#endif +#endif + +/******************************************************* + * PA Enums + *******************************************************/ +#ifndef ENUMS_SU_PERFCNT_SELECT_H +#define ENUMS_SU_PERFCNT_SELECT_H +typedef enum SU_PERFCNT_SELECT { + PERF_PAPC_PASX_REQ = 0, + UNUSED1 = 1, + PERF_PAPC_PASX_FIRST_VECTOR = 2, + PERF_PAPC_PASX_SECOND_VECTOR = 3, + PERF_PAPC_PASX_FIRST_DEAD = 4, + PERF_PAPC_PASX_SECOND_DEAD = 5, + PERF_PAPC_PASX_VTX_KILL_DISCARD = 6, + PERF_PAPC_PASX_VTX_NAN_DISCARD = 7, + PERF_PAPC_PA_INPUT_PRIM = 8, + PERF_PAPC_PA_INPUT_NULL_PRIM = 9, + PERF_PAPC_PA_INPUT_EVENT_FLAG = 10, + PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11, + PERF_PAPC_PA_INPUT_END_OF_PACKET = 12, + PERF_PAPC_CLPR_CULL_PRIM = 13, + UNUSED2 = 14, + PERF_PAPC_CLPR_VV_CULL_PRIM = 15, + UNUSED3 = 16, + PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 17, + PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 18, + PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 19, + UNUSED4 = 20, + PERF_PAPC_CLPR_VV_CLIP_PRIM = 21, + UNUSED5 = 22, + PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 23, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 24, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 25, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 26, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 27, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_5 = 28, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_6 = 29, + PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 30, + PERF_PAPC_CLPR_CLIP_PLANE_FAR = 31, + PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 32, + PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 33, + PERF_PAPC_CLPR_CLIP_PLANE_TOP = 34, + PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 35, + PERF_PAPC_CLSM_NULL_PRIM = 36, + PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 37, + PERF_PAPC_CLSM_CLIP_PRIM = 38, + PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 39, + PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 40, + PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 41, + PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 42, + PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 43, + PERF_PAPC_CLSM_OUT_PRIM_CNT_5 = 44, + PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7 = 45, + PERF_PAPC_CLSM_NON_TRIVIAL_CULL = 46, + PERF_PAPC_SU_INPUT_PRIM = 47, + PERF_PAPC_SU_INPUT_CLIP_PRIM = 48, + PERF_PAPC_SU_INPUT_NULL_PRIM = 49, + PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 50, + PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 51, + PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 52, + PERF_PAPC_SU_POLYMODE_FACE_CULL = 53, + PERF_PAPC_SU_POLYMODE_BACK_CULL = 54, + PERF_PAPC_SU_POLYMODE_FRONT_CULL = 55, + PERF_PAPC_SU_POLYMODE_INVALID_FILL = 56, + PERF_PAPC_SU_OUTPUT_PRIM = 57, + PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 58, + PERF_PAPC_SU_OUTPUT_NULL_PRIM = 59, + PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 60, + PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 61, + PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 62, + PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 63, + PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 64, + PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 65, + PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 66, + PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 67, + PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 68, + PERF_PAPC_PASX_REQ_IDLE = 69, + PERF_PAPC_PASX_REQ_BUSY = 70, + PERF_PAPC_PASX_REQ_STALLED = 71, + PERF_PAPC_PASX_REC_IDLE = 72, + PERF_PAPC_PASX_REC_BUSY = 73, + PERF_PAPC_PASX_REC_STARVED_SX = 74, + PERF_PAPC_PASX_REC_STALLED = 75, + PERF_PAPC_PASX_REC_STALLED_POS_MEM = 76, + PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 77, + PERF_PAPC_CCGSM_IDLE = 78, + PERF_PAPC_CCGSM_BUSY = 79, + PERF_PAPC_CCGSM_STALLED = 80, + PERF_PAPC_CLPRIM_IDLE = 81, + PERF_PAPC_CLPRIM_BUSY = 82, + PERF_PAPC_CLPRIM_STALLED = 83, + PERF_PAPC_CLPRIM_STARVED_CCGSM = 84, + PERF_PAPC_CLIPSM_IDLE = 85, + PERF_PAPC_CLIPSM_BUSY = 86, + PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 87, + PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 88, + PERF_PAPC_CLIPSM_WAIT_CLIPGA = 89, + PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 90, + PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 91, + PERF_PAPC_CLIPGA_IDLE = 92, + PERF_PAPC_CLIPGA_BUSY = 93, + PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 94, + PERF_PAPC_CLIPGA_STALLED = 95, + PERF_PAPC_CLIP_IDLE = 96, + PERF_PAPC_CLIP_BUSY = 97, + PERF_PAPC_SU_IDLE = 98, + PERF_PAPC_SU_BUSY = 99, + PERF_PAPC_SU_STARVED_CLIP = 100, + PERF_PAPC_SU_STALLED_SC = 101, + PERF_PAPC_SU_FACENESS_CULL = 102, +} SU_PERFCNT_SELECT; +#endif /*ENUMS_SU_PERFCNT_SELECT_H*/ + +#ifndef ENUMS_SC_PERFCNT_SELECT_H +#define ENUMS_SC_PERFCNT_SELECT_H +typedef enum SC_PERFCNT_SELECT { + SC_SR_WINDOW_VALID = 0, + SC_CW_WINDOW_VALID = 1, + SC_QM_WINDOW_VALID = 2, + SC_FW_WINDOW_VALID = 3, + SC_EZ_WINDOW_VALID = 4, + SC_IT_WINDOW_VALID = 5, + SC_STARVED_BY_PA = 6, + SC_STALLED_BY_RB_TILE = 7, + SC_STALLED_BY_RB_SAMP = 8, + SC_STARVED_BY_RB_EZ = 9, + SC_STALLED_BY_SAMPLE_FF = 10, + SC_STALLED_BY_SQ = 11, + SC_STALLED_BY_SP = 12, + SC_TOTAL_NO_PRIMS = 13, + SC_NON_EMPTY_PRIMS = 14, + SC_NO_TILES_PASSING_QM = 15, + SC_NO_PIXELS_PRE_EZ = 16, + SC_NO_PIXELS_POST_EZ = 17, +} SC_PERFCNT_SELECT; +#endif /*ENUMS_SC_PERFCNT_SELECT_H*/ + +/******************************************************* + * VGT Enums + *******************************************************/ +#ifndef ENUMS_VGT_DI_PRIM_TYPE_H +#define ENUMS_VGT_DI_PRIM_TYPE_H +typedef enum VGT_DI_PRIM_TYPE { + DI_PT_NONE = 0, + DI_PT_POINTLIST = 1, + DI_PT_LINELIST = 2, + DI_PT_LINESTRIP = 3, + DI_PT_TRILIST = 4, + DI_PT_TRIFAN = 5, + DI_PT_TRISTRIP = 6, + DI_PT_UNUSED_1 = 7, + DI_PT_RECTLIST = 8, + DI_PT_UNUSED_2 = 9, + DI_PT_UNUSED_3 = 10, + DI_PT_UNUSED_4 = 11, + DI_PT_UNUSED_5 = 12, + DI_PT_QUADLIST = 13, + DI_PT_QUADSTRIP = 14, + DI_PT_POLYGON = 15, + DI_PT_2D_COPY_RECT_LIST_V0 = 16, + DI_PT_2D_COPY_RECT_LIST_V1 = 17, + DI_PT_2D_COPY_RECT_LIST_V2 = 18, + DI_PT_2D_COPY_RECT_LIST_V3 = 19, + DI_PT_2D_FILL_RECT_LIST = 20, + DI_PT_2D_LINE_STRIP = 21, + DI_PT_2D_TRI_STRIP = 22, +} VGT_DI_PRIM_TYPE; +#endif /*ENUMS_VGT_DI_PRIM_TYPE_H*/ + +#ifndef ENUMS_VGT_DI_SOURCE_SELECT_H +#define ENUMS_VGT_DI_SOURCE_SELECT_H +typedef enum VGT_DI_SOURCE_SELECT { + DI_SRC_SEL_DMA = 0, + DI_SRC_SEL_IMMEDIATE = 1, + DI_SRC_SEL_AUTO_INDEX = 2, + DI_SRC_SEL_RESERVED = 3 +} VGT_DI_SOURCE_SELECT; +#endif /*ENUMS_VGT_DI_SOURCE_SELECT_H*/ + +#ifndef ENUMS_VGT_DI_FACENESS_CULL_SELECT_H +#define ENUMS_VGT_DI_FACENESS_CULL_SELECT_H +typedef enum VGT_DI_FACENESS_CULL_SELECT { + DI_FACE_CULL_NONE = 0, + DI_FACE_CULL_FETCH = 1, + DI_FACE_BACKFACE_CULL = 2, + DI_FACE_FRONTFACE_CULL = 3 +} VGT_DI_FACENESS_CULL_SELECT; +#endif /*ENUMS_VGT_DI_FACENESS_CULL_SELECT_H*/ + +#ifndef ENUMS_VGT_DI_INDEX_SIZE_H +#define ENUMS_VGT_DI_INDEX_SIZE_H +typedef enum VGT_DI_INDEX_SIZE { + DI_INDEX_SIZE_16_BIT = 0, + DI_INDEX_SIZE_32_BIT = 1 +} VGT_DI_INDEX_SIZE; +#endif /*ENUMS_VGT_DI_INDEX_SIZE_H*/ + +#ifndef ENUMS_VGT_DI_SMALL_INDEX_H +#define ENUMS_VGT_DI_SMALL_INDEX_H +typedef enum VGT_DI_SMALL_INDEX { + DI_USE_INDEX_SIZE = 0, + DI_INDEX_SIZE_8_BIT = 1 +} VGT_DI_SMALL_INDEX; +#endif /*ENUMS_VGT_DI_SMALL_INDEX_H*/ + +#ifndef ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H +#define ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H +typedef enum VGT_DI_PRE_FETCH_CULL_ENABLE { + DISABLE_PRE_FETCH_CULL_ENABLE = 0, + PRE_FETCH_CULL_ENABLE = 1 +} VGT_DI_PRE_FETCH_CULL_ENABLE; +#endif /*ENUMS_VGT_DI_PRE_FETCH_CULL_ENABLE_H*/ + +#ifndef ENUMS_VGT_DI_GRP_CULL_ENABLE_H +#define ENUMS_VGT_DI_GRP_CULL_ENABLE_H +typedef enum VGT_DI_GRP_CULL_ENABLE { + DISABLE_GRP_CULL_ENABLE = 0, + GRP_CULL_ENABLE = 1 +} VGT_DI_GRP_CULL_ENABLE; +#endif /*ENUMS_VGT_DI_GRP_CULL_ENABLE_H*/ + +#ifndef ENUMS_VGT_EVENT_TYPE_H +#define ENUMS_VGT_EVENT_TYPE_H +typedef enum VGT_EVENT_TYPE { + VS_DEALLOC = 0, + PS_DEALLOC = 1, + VS_DONE_TS = 2, + PS_DONE_TS = 3, + CACHE_FLUSH_TS = 4, + CONTEXT_DONE = 5, + CACHE_FLUSH = 6, + VIZQUERY_START = 7, + VIZQUERY_END = 8, + SC_WAIT_WC = 9, + RST_PIX_CNT = 13, + RST_VTX_CNT = 14, + TILE_FLUSH = 15, + CACHE_FLUSH_AND_INV_TS_EVENT = 20, + ZPASS_DONE = 21, + CACHE_FLUSH_AND_INV_EVENT = 22, + PERFCOUNTER_START = 23, + PERFCOUNTER_STOP = 24, + VS_FETCH_DONE = 27, + FACENESS_FLUSH = 28, +} VGT_EVENT_TYPE; +#endif /*ENUMS_VGT_EVENT_TYPE_H*/ + +#ifndef ENUMS_VGT_DMA_SWAP_MODE_H +#define ENUMS_VGT_DMA_SWAP_MODE_H +typedef enum VGT_DMA_SWAP_MODE { + VGT_DMA_SWAP_NONE = 0, + VGT_DMA_SWAP_16_BIT = 1, + VGT_DMA_SWAP_32_BIT = 2, + VGT_DMA_SWAP_WORD = 3 +} VGT_DMA_SWAP_MODE; +#endif /*ENUMS_VGT_DMA_SWAP_MODE_H*/ + +#ifndef ENUMS_VGT_PERFCOUNT_SELECT_H +#define ENUMS_VGT_PERFCOUNT_SELECT_H +typedef enum VGT_PERFCOUNT_SELECT { + VGT_SQ_EVENT_WINDOW_ACTIVE = 0, + VGT_SQ_SEND = 1, + VGT_SQ_STALLED = 2, + VGT_SQ_STARVED_BUSY = 3, + VGT_SQ_STARVED_IDLE = 4, + VGT_SQ_STATIC = 5, + VGT_PA_EVENT_WINDOW_ACTIVE = 6, + VGT_PA_CLIP_V_SEND = 7, + VGT_PA_CLIP_V_STALLED = 8, + VGT_PA_CLIP_V_STARVED_BUSY = 9, + VGT_PA_CLIP_V_STARVED_IDLE = 10, + VGT_PA_CLIP_V_STATIC = 11, + VGT_PA_CLIP_P_SEND = 12, + VGT_PA_CLIP_P_STALLED = 13, + VGT_PA_CLIP_P_STARVED_BUSY = 14, + VGT_PA_CLIP_P_STARVED_IDLE = 15, + VGT_PA_CLIP_P_STATIC = 16, + VGT_PA_CLIP_S_SEND = 17, + VGT_PA_CLIP_S_STALLED = 18, + VGT_PA_CLIP_S_STARVED_BUSY = 19, + VGT_PA_CLIP_S_STARVED_IDLE = 20, + VGT_PA_CLIP_S_STATIC = 21, + RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 22, + RBIU_IMMED_DATA_FIFO_STARVED = 23, + RBIU_IMMED_DATA_FIFO_STALLED = 24, + RBIU_DMA_REQUEST_FIFO_STARVED = 25, + RBIU_DMA_REQUEST_FIFO_STALLED = 26, + RBIU_DRAW_INITIATOR_FIFO_STARVED = 27, + RBIU_DRAW_INITIATOR_FIFO_STALLED = 28, + BIN_PRIM_NEAR_CULL = 29, + BIN_PRIM_ZERO_CULL = 30, + BIN_PRIM_FAR_CULL = 31, + BIN_PRIM_BIN_CULL = 32, + BIN_PRIM_FACE_CULL = 33, + SPARE34 = 34, + SPARE35 = 35, + SPARE36 = 36, + SPARE37 = 37, + SPARE38 = 38, + SPARE39 = 39, + TE_SU_IN_VALID = 40, + TE_SU_IN_READ = 41, + TE_SU_IN_PRIM = 42, + TE_SU_IN_EOP = 43, + TE_SU_IN_NULL_PRIM = 44, + TE_WK_IN_VALID = 45, + TE_WK_IN_READ = 46, + TE_OUT_PRIM_VALID = 47, + TE_OUT_PRIM_READ = 48, +} VGT_PERFCOUNT_SELECT; +#endif /*ENUMS_VGT_PERFCOUNT_SELECT_H*/ + +/******************************************************* + * TP Enums + *******************************************************/ +#ifndef ENUMS_TCR_PERFCOUNT_SELECT_H +#define ENUMS_TCR_PERFCOUNT_SELECT_H +typedef enum TCR_PERFCOUNT_SELECT { + DGMMPD_IPMUX0_STALL = 0, + reserved_46 = 1, + reserved_47 = 2, + reserved_48 = 3, + DGMMPD_IPMUX_ALL_STALL = 4, + OPMUX0_L2_WRITES = 5, + reserved_49 = 6, + reserved_50 = 7, + reserved_51 = 8, +} TCR_PERFCOUNT_SELECT; +#endif /*ENUMS_TCR_PERFCOUNT_SELECT_H*/ + +#ifndef ENUMS_TP_PERFCOUNT_SELECT_H +#define ENUMS_TP_PERFCOUNT_SELECT_H +typedef enum TP_PERFCOUNT_SELECT { + POINT_QUADS = 0, + BILIN_QUADS = 1, + ANISO_QUADS = 2, + MIP_QUADS = 3, + VOL_QUADS = 4, + MIP_VOL_QUADS = 5, + MIP_ANISO_QUADS = 6, + VOL_ANISO_QUADS = 7, + ANISO_2_1_QUADS = 8, + ANISO_4_1_QUADS = 9, + ANISO_6_1_QUADS = 10, + ANISO_8_1_QUADS = 11, + ANISO_10_1_QUADS = 12, + ANISO_12_1_QUADS = 13, + ANISO_14_1_QUADS = 14, + ANISO_16_1_QUADS = 15, + MIP_VOL_ANISO_QUADS = 16, + ALIGN_2_QUADS = 17, + ALIGN_4_QUADS = 18, + PIX_0_QUAD = 19, + PIX_1_QUAD = 20, + PIX_2_QUAD = 21, + PIX_3_QUAD = 22, + PIX_4_QUAD = 23, + TP_MIPMAP_LOD0 = 24, + TP_MIPMAP_LOD1 = 25, + TP_MIPMAP_LOD2 = 26, + TP_MIPMAP_LOD3 = 27, + TP_MIPMAP_LOD4 = 28, + TP_MIPMAP_LOD5 = 29, + TP_MIPMAP_LOD6 = 30, + TP_MIPMAP_LOD7 = 31, + TP_MIPMAP_LOD8 = 32, + TP_MIPMAP_LOD9 = 33, + TP_MIPMAP_LOD10 = 34, + TP_MIPMAP_LOD11 = 35, + TP_MIPMAP_LOD12 = 36, + TP_MIPMAP_LOD13 = 37, + TP_MIPMAP_LOD14 = 38, +} TP_PERFCOUNT_SELECT; +#endif /*ENUMS_TP_PERFCOUNT_SELECT_H*/ + +#ifndef ENUMS_TCM_PERFCOUNT_SELECT_H +#define ENUMS_TCM_PERFCOUNT_SELECT_H +typedef enum TCM_PERFCOUNT_SELECT { + QUAD0_RD_LAT_FIFO_EMPTY = 0, + reserved_01 = 1, + reserved_02 = 2, + QUAD0_RD_LAT_FIFO_4TH_FULL = 3, + QUAD0_RD_LAT_FIFO_HALF_FULL = 4, + QUAD0_RD_LAT_FIFO_FULL = 5, + QUAD0_RD_LAT_FIFO_LT_4TH_FULL = 6, + reserved_07 = 7, + reserved_08 = 8, + reserved_09 = 9, + reserved_10 = 10, + reserved_11 = 11, + reserved_12 = 12, + reserved_13 = 13, + reserved_14 = 14, + reserved_15 = 15, + reserved_16 = 16, + reserved_17 = 17, + reserved_18 = 18, + reserved_19 = 19, + reserved_20 = 20, + reserved_21 = 21, + reserved_22 = 22, + reserved_23 = 23, + reserved_24 = 24, + reserved_25 = 25, + reserved_26 = 26, + reserved_27 = 27, + READ_STARVED_QUAD0 = 28, + reserved_29 = 29, + reserved_30 = 30, + reserved_31 = 31, + READ_STARVED = 32, + READ_STALLED_QUAD0 = 33, + reserved_34 = 34, + reserved_35 = 35, + reserved_36 = 36, + READ_STALLED = 37, + VALID_READ_QUAD0 = 38, + reserved_39 = 39, + reserved_40 = 40, + reserved_41 = 41, + TC_TP_STARVED_QUAD0 = 42, + reserved_43 = 43, + reserved_44 = 44, + reserved_45 = 45, + TC_TP_STARVED = 46, +} TCM_PERFCOUNT_SELECT; +#endif /*ENUMS_TCM_PERFCOUNT_SELECT_H*/ + +#ifndef ENUMS_TCF_PERFCOUNT_SELECT_H +#define ENUMS_TCF_PERFCOUNT_SELECT_H +typedef enum TCF_PERFCOUNT_SELECT { + VALID_CYCLES = 0, + SINGLE_PHASES = 1, + ANISO_PHASES = 2, + MIP_PHASES = 3, + VOL_PHASES = 4, + MIP_VOL_PHASES = 5, + MIP_ANISO_PHASES = 6, + VOL_ANISO_PHASES = 7, + ANISO_2_1_PHASES = 8, + ANISO_4_1_PHASES = 9, + ANISO_6_1_PHASES = 10, + ANISO_8_1_PHASES = 11, + ANISO_10_1_PHASES = 12, + ANISO_12_1_PHASES = 13, + ANISO_14_1_PHASES = 14, + ANISO_16_1_PHASES = 15, + MIP_VOL_ANISO_PHASES = 16, + ALIGN_2_PHASES = 17, + ALIGN_4_PHASES = 18, + TPC_BUSY = 19, + TPC_STALLED = 20, + TPC_STARVED = 21, + TPC_WORKING = 22, + TPC_WALKER_BUSY = 23, + TPC_WALKER_STALLED = 24, + TPC_WALKER_WORKING = 25, + TPC_ALIGNER_BUSY = 26, + TPC_ALIGNER_STALLED = 27, + TPC_ALIGNER_STALLED_BY_BLEND = 28, + TPC_ALIGNER_STALLED_BY_CACHE = 29, + TPC_ALIGNER_WORKING = 30, + TPC_BLEND_BUSY = 31, + TPC_BLEND_SYNC = 32, + TPC_BLEND_STARVED = 33, + TPC_BLEND_WORKING = 34, + OPCODE_0x00 = 35, + OPCODE_0x01 = 36, + OPCODE_0x04 = 37, + OPCODE_0x10 = 38, + OPCODE_0x11 = 39, + OPCODE_0x12 = 40, + OPCODE_0x13 = 41, + OPCODE_0x18 = 42, + OPCODE_0x19 = 43, + OPCODE_0x1A = 44, + OPCODE_OTHER = 45, + IN_FIFO_0_EMPTY = 56, + IN_FIFO_0_LT_HALF_FULL = 57, + IN_FIFO_0_HALF_FULL = 58, + IN_FIFO_0_FULL = 59, + IN_FIFO_TPC_EMPTY = 72, + IN_FIFO_TPC_LT_HALF_FULL = 73, + IN_FIFO_TPC_HALF_FULL = 74, + IN_FIFO_TPC_FULL = 75, + TPC_TC_XFC = 76, + TPC_TC_STATE = 77, + TC_STALL = 78, + QUAD0_TAPS = 79, + QUADS = 83, + TCA_SYNC_STALL = 84, + TAG_STALL = 85, + TCB_SYNC_STALL = 88, + TCA_VALID = 89, + PROBES_VALID = 90, + MISS_STALL = 91, + FETCH_FIFO_STALL = 92, + TCO_STALL = 93, + ANY_STALL = 94, + TAG_MISSES = 95, + TAG_HITS = 96, + SUB_TAG_MISSES = 97, + SET0_INVALIDATES = 98, + SET1_INVALIDATES = 99, + SET2_INVALIDATES = 100, + SET3_INVALIDATES = 101, + SET0_TAG_MISSES = 102, + SET1_TAG_MISSES = 103, + SET2_TAG_MISSES = 104, + SET3_TAG_MISSES = 105, + SET0_TAG_HITS = 106, + SET1_TAG_HITS = 107, + SET2_TAG_HITS = 108, + SET3_TAG_HITS = 109, + SET0_SUB_TAG_MISSES = 110, + SET1_SUB_TAG_MISSES = 111, + SET2_SUB_TAG_MISSES = 112, + SET3_SUB_TAG_MISSES = 113, + SET0_EVICT1 = 114, + SET0_EVICT2 = 115, + SET0_EVICT3 = 116, + SET0_EVICT4 = 117, + SET0_EVICT5 = 118, + SET0_EVICT6 = 119, + SET0_EVICT7 = 120, + SET0_EVICT8 = 121, + SET1_EVICT1 = 130, + SET1_EVICT2 = 131, + SET1_EVICT3 = 132, + SET1_EVICT4 = 133, + SET1_EVICT5 = 134, + SET1_EVICT6 = 135, + SET1_EVICT7 = 136, + SET1_EVICT8 = 137, + SET2_EVICT1 = 146, + SET2_EVICT2 = 147, + SET2_EVICT3 = 148, + SET2_EVICT4 = 149, + SET2_EVICT5 = 150, + SET2_EVICT6 = 151, + SET2_EVICT7 = 152, + SET2_EVICT8 = 153, + SET3_EVICT1 = 162, + SET3_EVICT2 = 163, + SET3_EVICT3 = 164, + SET3_EVICT4 = 165, + SET3_EVICT5 = 166, + SET3_EVICT6 = 167, + SET3_EVICT7 = 168, + SET3_EVICT8 = 169, + FF_EMPTY = 178, + FF_LT_HALF_FULL = 179, + FF_HALF_FULL = 180, + FF_FULL = 181, + FF_XFC = 182, + FF_STALLED = 183, + FG_MASKS = 184, + FG_LEFT_MASKS = 185, + FG_LEFT_MASK_STALLED = 186, + FG_LEFT_NOT_DONE_STALL = 187, + FG_LEFT_FG_STALL = 188, + FG_LEFT_SECTORS = 189, + FG0_REQUESTS = 195, + FG0_STALLED = 196, + MEM_REQ512 = 199, + MEM_REQ_SENT = 200, + MEM_LOCAL_READ_REQ = 202, + TC0_MH_STALLED = 203, +} TCF_PERFCOUNT_SELECT; +#endif /*ENUMS_TCF_PERFCOUNT_SELECT_H*/ + +/******************************************************* + * TC Enums + *******************************************************/ +/******************************************************* + * SQ Enums + *******************************************************/ +#ifndef ENUMS_SQ_PERFCNT_SELECT_H +#define ENUMS_SQ_PERFCNT_SELECT_H +typedef enum SQ_PERFCNT_SELECT { + SQ_PIXEL_VECTORS_SUB = 0, + SQ_VERTEX_VECTORS_SUB = 1, + SQ_ALU0_ACTIVE_VTX_SIMD0 = 2, + SQ_ALU1_ACTIVE_VTX_SIMD0 = 3, + SQ_ALU0_ACTIVE_PIX_SIMD0 = 4, + SQ_ALU1_ACTIVE_PIX_SIMD0 = 5, + SQ_ALU0_ACTIVE_VTX_SIMD1 = 6, + SQ_ALU1_ACTIVE_VTX_SIMD1 = 7, + SQ_ALU0_ACTIVE_PIX_SIMD1 = 8, + SQ_ALU1_ACTIVE_PIX_SIMD1 = 9, + SQ_EXPORT_CYCLES = 10, + SQ_ALU_CST_WRITTEN = 11, + SQ_TEX_CST_WRITTEN = 12, + SQ_ALU_CST_STALL = 13, + SQ_ALU_TEX_STALL = 14, + SQ_INST_WRITTEN = 15, + SQ_BOOLEAN_WRITTEN = 16, + SQ_LOOPS_WRITTEN = 17, + SQ_PIXEL_SWAP_IN = 18, + SQ_PIXEL_SWAP_OUT = 19, + SQ_VERTEX_SWAP_IN = 20, + SQ_VERTEX_SWAP_OUT = 21, + SQ_ALU_VTX_INST_ISSUED = 22, + SQ_TEX_VTX_INST_ISSUED = 23, + SQ_VC_VTX_INST_ISSUED = 24, + SQ_CF_VTX_INST_ISSUED = 25, + SQ_ALU_PIX_INST_ISSUED = 26, + SQ_TEX_PIX_INST_ISSUED = 27, + SQ_VC_PIX_INST_ISSUED = 28, + SQ_CF_PIX_INST_ISSUED = 29, + SQ_ALU0_FIFO_EMPTY_SIMD0 = 30, + SQ_ALU1_FIFO_EMPTY_SIMD0 = 31, + SQ_ALU0_FIFO_EMPTY_SIMD1 = 32, + SQ_ALU1_FIFO_EMPTY_SIMD1 = 33, + SQ_ALU_NOPS = 34, + SQ_PRED_SKIP = 35, + SQ_SYNC_ALU_STALL_SIMD0_VTX = 36, + SQ_SYNC_ALU_STALL_SIMD1_VTX = 37, + SQ_SYNC_TEX_STALL_VTX = 38, + SQ_SYNC_VC_STALL_VTX = 39, + SQ_CONSTANTS_USED_SIMD0 = 40, + SQ_CONSTANTS_SENT_SP_SIMD0 = 41, + SQ_GPR_STALL_VTX = 42, + SQ_GPR_STALL_PIX = 43, + SQ_VTX_RS_STALL = 44, + SQ_PIX_RS_STALL = 45, + SQ_SX_PC_FULL = 46, + SQ_SX_EXP_BUFF_FULL = 47, + SQ_SX_POS_BUFF_FULL = 48, + SQ_INTERP_QUADS = 49, + SQ_INTERP_ACTIVE = 50, + SQ_IN_PIXEL_STALL = 51, + SQ_IN_VTX_STALL = 52, + SQ_VTX_CNT = 53, + SQ_VTX_VECTOR2 = 54, + SQ_VTX_VECTOR3 = 55, + SQ_VTX_VECTOR4 = 56, + SQ_PIXEL_VECTOR1 = 57, + SQ_PIXEL_VECTOR23 = 58, + SQ_PIXEL_VECTOR4 = 59, + SQ_CONSTANTS_USED_SIMD1 = 60, + SQ_CONSTANTS_SENT_SP_SIMD1 = 61, + SQ_SX_MEM_EXP_FULL = 62, + SQ_ALU0_ACTIVE_VTX_SIMD2 = 63, + SQ_ALU1_ACTIVE_VTX_SIMD2 = 64, + SQ_ALU0_ACTIVE_PIX_SIMD2 = 65, + SQ_ALU1_ACTIVE_PIX_SIMD2 = 66, + SQ_ALU0_ACTIVE_VTX_SIMD3 = 67, + SQ_PERFCOUNT_VTX_QUAL_TP_DONE = 68, + SQ_ALU0_ACTIVE_PIX_SIMD3 = 69, + SQ_PERFCOUNT_PIX_QUAL_TP_DONE = 70, + SQ_ALU0_FIFO_EMPTY_SIMD2 = 71, + SQ_ALU1_FIFO_EMPTY_SIMD2 = 72, + SQ_ALU0_FIFO_EMPTY_SIMD3 = 73, + SQ_ALU1_FIFO_EMPTY_SIMD3 = 74, + SQ_SYNC_ALU_STALL_SIMD2_VTX = 75, + SQ_PERFCOUNT_VTX_POP_THREAD = 76, + SQ_SYNC_ALU_STALL_SIMD0_PIX = 77, + SQ_SYNC_ALU_STALL_SIMD1_PIX = 78, + SQ_SYNC_ALU_STALL_SIMD2_PIX = 79, + SQ_PERFCOUNT_PIX_POP_THREAD = 80, + SQ_SYNC_TEX_STALL_PIX = 81, + SQ_SYNC_VC_STALL_PIX = 82, + SQ_CONSTANTS_USED_SIMD2 = 83, + SQ_CONSTANTS_SENT_SP_SIMD2 = 84, + SQ_PERFCOUNT_VTX_DEALLOC_ACK = 85, + SQ_PERFCOUNT_PIX_DEALLOC_ACK = 86, + SQ_ALU0_FIFO_FULL_SIMD0 = 87, + SQ_ALU1_FIFO_FULL_SIMD0 = 88, + SQ_ALU0_FIFO_FULL_SIMD1 = 89, + SQ_ALU1_FIFO_FULL_SIMD1 = 90, + SQ_ALU0_FIFO_FULL_SIMD2 = 91, + SQ_ALU1_FIFO_FULL_SIMD2 = 92, + SQ_ALU0_FIFO_FULL_SIMD3 = 93, + SQ_ALU1_FIFO_FULL_SIMD3 = 94, + VC_PERF_STATIC = 95, + VC_PERF_STALLED = 96, + VC_PERF_STARVED = 97, + VC_PERF_SEND = 98, + VC_PERF_ACTUAL_STARVED = 99, + PIXEL_THREAD_0_ACTIVE = 100, + VERTEX_THREAD_0_ACTIVE = 101, + PIXEL_THREAD_0_NUMBER = 102, + VERTEX_THREAD_0_NUMBER = 103, + VERTEX_EVENT_NUMBER = 104, + PIXEL_EVENT_NUMBER = 105, + PTRBUFF_EF_PUSH = 106, + PTRBUFF_EF_POP_EVENT = 107, + PTRBUFF_EF_POP_NEW_VTX = 108, + PTRBUFF_EF_POP_DEALLOC = 109, + PTRBUFF_EF_POP_PVECTOR = 110, + PTRBUFF_EF_POP_PVECTOR_X = 111, + PTRBUFF_EF_POP_PVECTOR_VNZ = 112, + PTRBUFF_PB_DEALLOC = 113, + PTRBUFF_PI_STATE_PPB_POP = 114, + PTRBUFF_PI_RTR = 115, + PTRBUFF_PI_READ_EN = 116, + PTRBUFF_PI_BUFF_SWAP = 117, + PTRBUFF_SQ_FREE_BUFF = 118, + PTRBUFF_SQ_DEC = 119, + PTRBUFF_SC_VALID_CNTL_EVENT = 120, + PTRBUFF_SC_VALID_IJ_XFER = 121, + PTRBUFF_SC_NEW_VECTOR_1_Q = 122, + PTRBUFF_QUAL_NEW_VECTOR = 123, + PTRBUFF_QUAL_EVENT = 124, + PTRBUFF_END_BUFFER = 125, + PTRBUFF_FILL_QUAD = 126, + VERTS_WRITTEN_SPI = 127, + TP_FETCH_INSTR_EXEC = 128, + TP_FETCH_INSTR_REQ = 129, + TP_DATA_RETURN = 130, + SPI_WRITE_CYCLES_SP = 131, + SPI_WRITES_SP = 132, + SP_ALU_INSTR_EXEC = 133, + SP_CONST_ADDR_TO_SQ = 134, + SP_PRED_KILLS_TO_SQ = 135, + SP_EXPORT_CYCLES_TO_SX = 136, + SP_EXPORTS_TO_SX = 137, + SQ_CYCLES_ELAPSED = 138, + SQ_TCFS_OPT_ALLOC_EXEC = 139, + SQ_TCFS_NO_OPT_ALLOC = 140, + SQ_ALU0_NO_OPT_ALLOC = 141, + SQ_ALU1_NO_OPT_ALLOC = 142, + SQ_TCFS_ARB_XFC_CNT = 143, + SQ_ALU0_ARB_XFC_CNT = 144, + SQ_ALU1_ARB_XFC_CNT = 145, + SQ_TCFS_CFS_UPDATE_CNT = 146, + SQ_ALU0_CFS_UPDATE_CNT = 147, + SQ_ALU1_CFS_UPDATE_CNT = 148, + SQ_VTX_PUSH_THREAD_CNT = 149, + SQ_VTX_POP_THREAD_CNT = 150, + SQ_PIX_PUSH_THREAD_CNT = 151, + SQ_PIX_POP_THREAD_CNT = 152, + SQ_PIX_TOTAL = 153, + SQ_PIX_KILLED = 154, +} SQ_PERFCNT_SELECT; +#endif /*ENUMS_SQ_PERFCNT_SELECT_H*/ + +#ifndef ENUMS_SX_PERFCNT_SELECT_H +#define ENUMS_SX_PERFCNT_SELECT_H +typedef enum SX_PERFCNT_SELECT { + SX_EXPORT_VECTORS = 0, + SX_DUMMY_QUADS = 1, + SX_ALPHA_FAIL = 2, + SX_RB_QUAD_BUSY = 3, + SX_RB_COLOR_BUSY = 4, + SX_RB_QUAD_STALL = 5, + SX_RB_COLOR_STALL = 6, +} SX_PERFCNT_SELECT; +#endif /*ENUMS_SX_PERFCNT_SELECT_H*/ + +#ifndef ENUMS_Abs_modifier_H +#define ENUMS_Abs_modifier_H +typedef enum Abs_modifier { + NO_ABS_MOD = 0, + ABS_MOD = 1 +} Abs_modifier; +#endif /*ENUMS_Abs_modifier_H*/ + +#ifndef ENUMS_Exporting_H +#define ENUMS_Exporting_H +typedef enum Exporting { + NOT_EXPORTING = 0, + EXPORTING = 1 +} Exporting; +#endif /*ENUMS_Exporting_H*/ + +#ifndef ENUMS_ScalarOpcode_H +#define ENUMS_ScalarOpcode_H +typedef enum ScalarOpcode { + ADDs = 0, + ADD_PREVs = 1, + MULs = 2, + MUL_PREVs = 3, + MUL_PREV2s = 4, + MAXs = 5, + MINs = 6, + SETEs = 7, + SETGTs = 8, + SETGTEs = 9, + SETNEs = 10, + FRACs = 11, + TRUNCs = 12, + FLOORs = 13, + EXP_IEEE = 14, + LOG_CLAMP = 15, + LOG_IEEE = 16, + RECIP_CLAMP = 17, + RECIP_FF = 18, + RECIP_IEEE = 19, + RECIPSQ_CLAMP = 20, + RECIPSQ_FF = 21, + RECIPSQ_IEEE = 22, + MOVAs = 23, + MOVA_FLOORs = 24, + SUBs = 25, + SUB_PREVs = 26, + PRED_SETEs = 27, + PRED_SETNEs = 28, + PRED_SETGTs = 29, + PRED_SETGTEs = 30, + PRED_SET_INVs = 31, + PRED_SET_POPs = 32, + PRED_SET_CLRs = 33, + PRED_SET_RESTOREs = 34, + KILLEs = 35, + KILLGTs = 36, + KILLGTEs = 37, + KILLNEs = 38, + KILLONEs = 39, + SQRT_IEEE = 40, + MUL_CONST_0 = 42, + MUL_CONST_1 = 43, + ADD_CONST_0 = 44, + ADD_CONST_1 = 45, + SUB_CONST_0 = 46, + SUB_CONST_1 = 47, + SIN = 48, + COS = 49, + RETAIN_PREV = 50, +} ScalarOpcode; +#endif /*ENUMS_ScalarOpcode_H*/ + +#ifndef ENUMS_SwizzleType_H +#define ENUMS_SwizzleType_H +typedef enum SwizzleType { + NO_SWIZZLE = 0, + SHIFT_RIGHT_1 = 1, + SHIFT_RIGHT_2 = 2, + SHIFT_RIGHT_3 = 3 +} SwizzleType; +#endif /*ENUMS_SwizzleType_H*/ + +#ifndef ENUMS_InputModifier_H +#define ENUMS_InputModifier_H +typedef enum InputModifier { + NIL = 0, + NEGATE = 1 +} InputModifier; +#endif /*ENUMS_InputModifier_H*/ + +#ifndef ENUMS_PredicateSelect_H +#define ENUMS_PredicateSelect_H +typedef enum PredicateSelect { + NO_PREDICATION = 0, + PREDICATE_QUAD = 1, + PREDICATED_2 = 2, + PREDICATED_3 = 3 +} PredicateSelect; +#endif /*ENUMS_PredicateSelect_H*/ + +#ifndef ENUMS_OperandSelect1_H +#define ENUMS_OperandSelect1_H +typedef enum OperandSelect1 { + ABSOLUTE_REG = 0, + RELATIVE_REG = 1 +} OperandSelect1; +#endif /*ENUMS_OperandSelect1_H*/ + +#ifndef ENUMS_VectorOpcode_H +#define ENUMS_VectorOpcode_H +typedef enum VectorOpcode { + ADDv = 0, + MULv = 1, + MAXv = 2, + MINv = 3, + SETEv = 4, + SETGTv = 5, + SETGTEv = 6, + SETNEv = 7, + FRACv = 8, + TRUNCv = 9, + FLOORv = 10, + MULADDv = 11, + CNDEv = 12, + CNDGTEv = 13, + CNDGTv = 14, + DOT4v = 15, + DOT3v = 16, + DOT2ADDv = 17, + CUBEv = 18, + MAX4v = 19, + PRED_SETE_PUSHv = 20, + PRED_SETNE_PUSHv = 21, + PRED_SETGT_PUSHv = 22, + PRED_SETGTE_PUSHv = 23, + KILLEv = 24, + KILLGTv = 25, + KILLGTEv = 26, + KILLNEv = 27, + DSTv = 28, + MOVAv = 29, +} VectorOpcode; +#endif /*ENUMS_VectorOpcode_H*/ + +#ifndef ENUMS_OperandSelect0_H +#define ENUMS_OperandSelect0_H +typedef enum OperandSelect0 { + CONSTANT = 0, + NON_CONSTANT = 1 +} OperandSelect0; +#endif /*ENUMS_OperandSelect0_H*/ + +#ifndef ENUMS_Ressource_type_H +#define ENUMS_Ressource_type_H +typedef enum Ressource_type { + ALU = 0, + TEXTURE = 1 +} Ressource_type; +#endif /*ENUMS_Ressource_type_H*/ + +#ifndef ENUMS_Instruction_serial_H +#define ENUMS_Instruction_serial_H +typedef enum Instruction_serial { + NOT_SERIAL = 0, + SERIAL = 1 +} Instruction_serial; +#endif /*ENUMS_Instruction_serial_H*/ + +#ifndef ENUMS_VC_type_H +#define ENUMS_VC_type_H +typedef enum VC_type { + ALU_TP_REQUEST = 0, + VC_REQUEST = 1 +} VC_type; +#endif /*ENUMS_VC_type_H*/ + +#ifndef ENUMS_Addressing_H +#define ENUMS_Addressing_H +typedef enum Addressing { + RELATIVE_ADDR = 0, + ABSOLUTE_ADDR = 1 +} Addressing; +#endif /*ENUMS_Addressing_H*/ + +#ifndef ENUMS_CFOpcode_H +#define ENUMS_CFOpcode_H +typedef enum CFOpcode { + NOP = 0, + EXECUTE = 1, + EXECUTE_END = 2, + COND_EXECUTE = 3, + COND_EXECUTE_END = 4, + COND_PRED_EXECUTE = 5, + COND_PRED_EXECUTE_END = 6, + LOOP_START = 7, + LOOP_END = 8, + COND_CALL = 9, + RETURN = 10, + COND_JMP = 11, + ALLOCATE = 12, + COND_EXECUTE_PRED_CLEAN = 13, + COND_EXECUTE_PRED_CLEAN_END = 14, + MARK_VS_FETCH_DONE = 15 +} CFOpcode; +#endif /*ENUMS_CFOpcode_H*/ + +#ifndef ENUMS_Allocation_type_H +#define ENUMS_Allocation_type_H +typedef enum Allocation_type { + SQ_NO_ALLOC = 0, + SQ_POSITION = 1, + SQ_PARAMETER_PIXEL = 2, + SQ_MEMORY = 3 +} Allocation_type; +#endif /*ENUMS_Allocation_type_H*/ + +#ifndef ENUMS_TexInstOpcode_H +#define ENUMS_TexInstOpcode_H +typedef enum TexInstOpcode { + TEX_INST_FETCH = 1, + TEX_INST_RESERVED_1 = 2, + TEX_INST_RESERVED_2 = 3, + TEX_INST_RESERVED_3 = 4, + TEX_INST_GET_BORDER_COLOR_FRAC = 16, + TEX_INST_GET_COMP_TEX_LOD = 17, + TEX_INST_GET_GRADIENTS = 18, + TEX_INST_GET_WEIGHTS = 19, + TEX_INST_SET_TEX_LOD = 24, + TEX_INST_SET_GRADIENTS_H = 25, + TEX_INST_SET_GRADIENTS_V = 26, + TEX_INST_RESERVED_4 = 27, +} TexInstOpcode; +#endif /*ENUMS_TexInstOpcode_H*/ + +#ifndef ENUMS_Addressmode_H +#define ENUMS_Addressmode_H +typedef enum Addressmode { + LOGICAL = 0, + LOOP_RELATIVE = 1 +} Addressmode; +#endif /*ENUMS_Addressmode_H*/ + +#ifndef ENUMS_TexCoordDenorm_H +#define ENUMS_TexCoordDenorm_H +typedef enum TexCoordDenorm { + TEX_COORD_NORMALIZED = 0, + TEX_COORD_UNNORMALIZED = 1 +} TexCoordDenorm; +#endif /*ENUMS_TexCoordDenorm_H*/ + +#ifndef ENUMS_SrcSel_H +#define ENUMS_SrcSel_H +typedef enum SrcSel { + SRC_SEL_X = 0, + SRC_SEL_Y = 1, + SRC_SEL_Z = 2, + SRC_SEL_W = 3 +} SrcSel; +#endif /*ENUMS_SrcSel_H*/ + +#ifndef ENUMS_DstSel_H +#define ENUMS_DstSel_H +typedef enum DstSel { + DST_SEL_X = 0, + DST_SEL_Y = 1, + DST_SEL_Z = 2, + DST_SEL_W = 3, + DST_SEL_0 = 4, + DST_SEL_1 = 5, + DST_SEL_RSVD = 6, + DST_SEL_MASK = 7 +} DstSel; +#endif /*ENUMS_DstSel_H*/ + +#ifndef ENUMS_MagFilter_H +#define ENUMS_MagFilter_H +typedef enum MagFilter { + MAG_FILTER_POINT = 0, + MAG_FILTER_LINEAR = 1, + MAG_FILTER_RESERVED_0 = 2, + MAG_FILTER_USE_FETCH_CONST = 3 +} MagFilter; +#endif /*ENUMS_MagFilter_H*/ + +#ifndef ENUMS_MinFilter_H +#define ENUMS_MinFilter_H +typedef enum MinFilter { + MIN_FILTER_POINT = 0, + MIN_FILTER_LINEAR = 1, + MIN_FILTER_RESERVED_0 = 2, + MIN_FILTER_USE_FETCH_CONST = 3 +} MinFilter; +#endif /*ENUMS_MinFilter_H*/ + +#ifndef ENUMS_MipFilter_H +#define ENUMS_MipFilter_H +typedef enum MipFilter { + MIP_FILTER_POINT = 0, + MIP_FILTER_LINEAR = 1, + MIP_FILTER_BASEMAP = 2, + MIP_FILTER_USE_FETCH_CONST = 3 +} MipFilter; +#endif /*ENUMS_MipFilter_H*/ + +#ifndef ENUMS_AnisoFilter_H +#define ENUMS_AnisoFilter_H +typedef enum AnisoFilter { + ANISO_FILTER_DISABLED = 0, + ANISO_FILTER_MAX_1_1 = 1, + ANISO_FILTER_MAX_2_1 = 2, + ANISO_FILTER_MAX_4_1 = 3, + ANISO_FILTER_MAX_8_1 = 4, + ANISO_FILTER_MAX_16_1 = 5, + ANISO_FILTER_USE_FETCH_CONST = 7 +} AnisoFilter; +#endif /*ENUMS_AnisoFilter_H*/ + +#ifndef ENUMS_ArbitraryFilter_H +#define ENUMS_ArbitraryFilter_H +typedef enum ArbitraryFilter { + ARBITRARY_FILTER_2X4_SYM = 0, + ARBITRARY_FILTER_2X4_ASYM = 1, + ARBITRARY_FILTER_4X2_SYM = 2, + ARBITRARY_FILTER_4X2_ASYM = 3, + ARBITRARY_FILTER_4X4_SYM = 4, + ARBITRARY_FILTER_4X4_ASYM = 5, + ARBITRARY_FILTER_USE_FETCH_CONST = 7 +} ArbitraryFilter; +#endif /*ENUMS_ArbitraryFilter_H*/ + +#ifndef ENUMS_VolMagFilter_H +#define ENUMS_VolMagFilter_H +typedef enum VolMagFilter { + VOL_MAG_FILTER_POINT = 0, + VOL_MAG_FILTER_LINEAR = 1, + VOL_MAG_FILTER_USE_FETCH_CONST = 3 +} VolMagFilter; +#endif /*ENUMS_VolMagFilter_H*/ + +#ifndef ENUMS_VolMinFilter_H +#define ENUMS_VolMinFilter_H +typedef enum VolMinFilter { + VOL_MIN_FILTER_POINT = 0, + VOL_MIN_FILTER_LINEAR = 1, + VOL_MIN_FILTER_USE_FETCH_CONST = 3 +} VolMinFilter; +#endif /*ENUMS_VolMinFilter_H*/ + +#ifndef ENUMS_PredSelect_H +#define ENUMS_PredSelect_H +typedef enum PredSelect { + NOT_PREDICATED = 0, + PREDICATED = 1 +} PredSelect; +#endif /*ENUMS_PredSelect_H*/ + +#ifndef ENUMS_SampleLocation_H +#define ENUMS_SampleLocation_H +typedef enum SampleLocation { + SAMPLE_CENTROID = 0, + SAMPLE_CENTER = 1 +} SampleLocation; +#endif /*ENUMS_SampleLocation_H*/ + +#ifndef ENUMS_VertexMode_H +#define ENUMS_VertexMode_H +typedef enum VertexMode { + POSITION_1_VECTOR = 0, + POSITION_2_VECTORS_UNUSED = 1, + POSITION_2_VECTORS_SPRITE = 2, + POSITION_2_VECTORS_EDGE = 3, + POSITION_2_VECTORS_KILL = 4, + POSITION_2_VECTORS_SPRITE_KILL = 5, + POSITION_2_VECTORS_EDGE_KILL = 6, + MULTIPASS = 7 +} VertexMode; +#endif /*ENUMS_VertexMode_H*/ + +#ifndef ENUMS_Sample_Cntl_H +#define ENUMS_Sample_Cntl_H +typedef enum Sample_Cntl { + CENTROIDS_ONLY = 0, + CENTERS_ONLY = 1, + CENTROIDS_AND_CENTERS = 2, + UNDEF = 3 +} Sample_Cntl; +#endif /*ENUMS_Sample_Cntl_H*/ + +/******************************************************* + * SX Enums + *******************************************************/ +/******************************************************* + * MH Enums + *******************************************************/ +#ifndef ENUMS_MhPerfEncode_H +#define ENUMS_MhPerfEncode_H +typedef enum MhPerfEncode { + CP_R0_REQUESTS = 0, + CP_R1_REQUESTS = 1, + CP_R2_REQUESTS = 2, + CP_R3_REQUESTS = 3, + CP_R4_REQUESTS = 4, + CP_TOTAL_READ_REQUESTS = 5, + CP_TOTAL_WRITE_REQUESTS = 6, + CP_TOTAL_REQUESTS = 7, + CP_DATA_BYTES_WRITTEN = 8, + CP_WRITE_CLEAN_RESPONSES = 9, + CP_R0_READ_BURSTS_RECEIVED = 10, + CP_R1_READ_BURSTS_RECEIVED = 11, + CP_R2_READ_BURSTS_RECEIVED = 12, + CP_R3_READ_BURSTS_RECEIVED = 13, + CP_R4_READ_BURSTS_RECEIVED = 14, + CP_TOTAL_READ_BURSTS_RECEIVED = 15, + CP_R0_DATA_BEATS_READ = 16, + CP_R1_DATA_BEATS_READ = 17, + CP_R2_DATA_BEATS_READ = 18, + CP_R3_DATA_BEATS_READ = 19, + CP_R4_DATA_BEATS_READ = 20, + CP_TOTAL_DATA_BEATS_READ = 21, + VGT_R0_REQUESTS = 22, + VGT_R1_REQUESTS = 23, + VGT_TOTAL_REQUESTS = 24, + VGT_R0_READ_BURSTS_RECEIVED = 25, + VGT_R1_READ_BURSTS_RECEIVED = 26, + VGT_TOTAL_READ_BURSTS_RECEIVED = 27, + VGT_R0_DATA_BEATS_READ = 28, + VGT_R1_DATA_BEATS_READ = 29, + VGT_TOTAL_DATA_BEATS_READ = 30, + TC_TOTAL_REQUESTS = 31, + TC_ROQ_REQUESTS = 32, + TC_INFO_SENT = 33, + TC_READ_BURSTS_RECEIVED = 34, + TC_DATA_BEATS_READ = 35, + TCD_BURSTS_READ = 36, + RB_REQUESTS = 37, + RB_DATA_BYTES_WRITTEN = 38, + RB_WRITE_CLEAN_RESPONSES = 39, + AXI_READ_REQUESTS_ID_0 = 40, + AXI_READ_REQUESTS_ID_1 = 41, + AXI_READ_REQUESTS_ID_2 = 42, + AXI_READ_REQUESTS_ID_3 = 43, + AXI_READ_REQUESTS_ID_4 = 44, + AXI_READ_REQUESTS_ID_5 = 45, + AXI_READ_REQUESTS_ID_6 = 46, + AXI_READ_REQUESTS_ID_7 = 47, + AXI_TOTAL_READ_REQUESTS = 48, + AXI_WRITE_REQUESTS_ID_0 = 49, + AXI_WRITE_REQUESTS_ID_1 = 50, + AXI_WRITE_REQUESTS_ID_2 = 51, + AXI_WRITE_REQUESTS_ID_3 = 52, + AXI_WRITE_REQUESTS_ID_4 = 53, + AXI_WRITE_REQUESTS_ID_5 = 54, + AXI_WRITE_REQUESTS_ID_6 = 55, + AXI_WRITE_REQUESTS_ID_7 = 56, + AXI_TOTAL_WRITE_REQUESTS = 57, + AXI_TOTAL_REQUESTS_ID_0 = 58, + AXI_TOTAL_REQUESTS_ID_1 = 59, + AXI_TOTAL_REQUESTS_ID_2 = 60, + AXI_TOTAL_REQUESTS_ID_3 = 61, + AXI_TOTAL_REQUESTS_ID_4 = 62, + AXI_TOTAL_REQUESTS_ID_5 = 63, + AXI_TOTAL_REQUESTS_ID_6 = 64, + AXI_TOTAL_REQUESTS_ID_7 = 65, + AXI_TOTAL_REQUESTS = 66, + AXI_READ_CHANNEL_BURSTS_ID_0 = 67, + AXI_READ_CHANNEL_BURSTS_ID_1 = 68, + AXI_READ_CHANNEL_BURSTS_ID_2 = 69, + AXI_READ_CHANNEL_BURSTS_ID_3 = 70, + AXI_READ_CHANNEL_BURSTS_ID_4 = 71, + AXI_READ_CHANNEL_BURSTS_ID_5 = 72, + AXI_READ_CHANNEL_BURSTS_ID_6 = 73, + AXI_READ_CHANNEL_BURSTS_ID_7 = 74, + AXI_READ_CHANNEL_TOTAL_BURSTS = 75, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0 = 76, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1 = 77, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2 = 78, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3 = 79, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4 = 80, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5 = 81, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6 = 82, + AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7 = 83, + AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ = 84, + AXI_WRITE_CHANNEL_BURSTS_ID_0 = 85, + AXI_WRITE_CHANNEL_BURSTS_ID_1 = 86, + AXI_WRITE_CHANNEL_BURSTS_ID_2 = 87, + AXI_WRITE_CHANNEL_BURSTS_ID_3 = 88, + AXI_WRITE_CHANNEL_BURSTS_ID_4 = 89, + AXI_WRITE_CHANNEL_BURSTS_ID_5 = 90, + AXI_WRITE_CHANNEL_BURSTS_ID_6 = 91, + AXI_WRITE_CHANNEL_BURSTS_ID_7 = 92, + AXI_WRITE_CHANNEL_TOTAL_BURSTS = 93, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0 = 94, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1 = 95, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2 = 96, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3 = 97, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4 = 98, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5 = 99, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6 = 100, + AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7 = 101, + AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN = 102, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0 = 103, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1 = 104, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2 = 105, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3 = 106, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4 = 107, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5 = 108, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6 = 109, + AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7 = 110, + AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES = 111, + TOTAL_MMU_MISSES = 112, + MMU_READ_MISSES = 113, + MMU_WRITE_MISSES = 114, + TOTAL_MMU_HITS = 115, + MMU_READ_HITS = 116, + MMU_WRITE_HITS = 117, + SPLIT_MODE_TC_HITS = 118, + SPLIT_MODE_TC_MISSES = 119, + SPLIT_MODE_NON_TC_HITS = 120, + SPLIT_MODE_NON_TC_MISSES = 121, + STALL_AWAITING_TLB_MISS_FETCH = 122, + MMU_TLB_MISS_READ_BURSTS_RECEIVED = 123, + MMU_TLB_MISS_DATA_BEATS_READ = 124, + CP_CYCLES_HELD_OFF = 125, + VGT_CYCLES_HELD_OFF = 126, + TC_CYCLES_HELD_OFF = 127, + TC_ROQ_CYCLES_HELD_OFF = 128, + TC_CYCLES_HELD_OFF_TCD_FULL = 129, + RB_CYCLES_HELD_OFF = 130, + TOTAL_CYCLES_ANY_CLNT_HELD_OFF = 131, + TLB_MISS_CYCLES_HELD_OFF = 132, + AXI_READ_REQUEST_HELD_OFF = 133, + AXI_WRITE_REQUEST_HELD_OFF = 134, + AXI_REQUEST_HELD_OFF = 135, + AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT = 136, + AXI_WRITE_DATA_HELD_OFF = 137, + CP_SAME_PAGE_BANK_REQUESTS = 138, + VGT_SAME_PAGE_BANK_REQUESTS = 139, + TC_SAME_PAGE_BANK_REQUESTS = 140, + TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS = 141, + RB_SAME_PAGE_BANK_REQUESTS = 142, + TOTAL_SAME_PAGE_BANK_REQUESTS = 143, + CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 144, + VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 145, + TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 146, + RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 147, + TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT = 148, + TOTAL_MH_READ_REQUESTS = 149, + TOTAL_MH_WRITE_REQUESTS = 150, + TOTAL_MH_REQUESTS = 151, + MH_BUSY = 152, + CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 153, + VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 154, + TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 155, + RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 156, + TC_ROQ_N_VALID_ENTRIES = 157, + ARQ_N_ENTRIES = 158, + WDB_N_ENTRIES = 159, + MH_READ_LATENCY_OUTST_REQ_SUM = 160, + MC_READ_LATENCY_OUTST_REQ_SUM = 161, + MC_TOTAL_READ_REQUESTS = 162, + ELAPSED_CYCLES_MH_GATED_CLK = 163, + ELAPSED_CLK_CYCLES = 164, + CP_W_16B_REQUESTS = 165, + CP_W_32B_REQUESTS = 166, + TC_16B_REQUESTS = 167, + TC_32B_REQUESTS = 168, + PA_REQUESTS = 169, + PA_DATA_BYTES_WRITTEN = 170, + PA_WRITE_CLEAN_RESPONSES = 171, + PA_CYCLES_HELD_OFF = 172, + AXI_READ_REQUEST_DATA_BEATS_ID_0 = 173, + AXI_READ_REQUEST_DATA_BEATS_ID_1 = 174, + AXI_READ_REQUEST_DATA_BEATS_ID_2 = 175, + AXI_READ_REQUEST_DATA_BEATS_ID_3 = 176, + AXI_READ_REQUEST_DATA_BEATS_ID_4 = 177, + AXI_READ_REQUEST_DATA_BEATS_ID_5 = 178, + AXI_READ_REQUEST_DATA_BEATS_ID_6 = 179, + AXI_READ_REQUEST_DATA_BEATS_ID_7 = 180, + AXI_TOTAL_READ_REQUEST_DATA_BEATS = 181, +} MhPerfEncode; +#endif /*ENUMS_MhPerfEncode_H*/ + +#ifndef ENUMS_MmuClntBeh_H +#define ENUMS_MmuClntBeh_H +typedef enum MmuClntBeh { + BEH_NEVR = 0, + BEH_TRAN_RNG = 1, + BEH_TRAN_FLT = 2, +} MmuClntBeh; +#endif /*ENUMS_MmuClntBeh_H*/ + +/******************************************************* + * RBBM Enums + *******************************************************/ +#ifndef ENUMS_RBBM_PERFCOUNT1_SEL_H +#define ENUMS_RBBM_PERFCOUNT1_SEL_H +typedef enum RBBM_PERFCOUNT1_SEL { + RBBM1_COUNT = 0, + RBBM1_NRT_BUSY = 1, + RBBM1_RB_BUSY = 2, + RBBM1_SQ_CNTX0_BUSY = 3, + RBBM1_SQ_CNTX17_BUSY = 4, + RBBM1_VGT_BUSY = 5, + RBBM1_VGT_NODMA_BUSY = 6, + RBBM1_PA_BUSY = 7, + RBBM1_SC_CNTX_BUSY = 8, + RBBM1_TPC_BUSY = 9, + RBBM1_TC_BUSY = 10, + RBBM1_SX_BUSY = 11, + RBBM1_CP_COHER_BUSY = 12, + RBBM1_CP_NRT_BUSY = 13, + RBBM1_GFX_IDLE_STALL = 14, + RBBM1_INTERRUPT = 15, +} RBBM_PERFCOUNT1_SEL; +#endif /*ENUMS_RBBM_PERFCOUNT1_SEL_H*/ + +/******************************************************* + * CP Enums + *******************************************************/ +#ifndef ENUMS_CP_PERFCOUNT_SEL_H +#define ENUMS_CP_PERFCOUNT_SEL_H +typedef enum CP_PERFCOUNT_SEL { + ALWAYS_COUNT = 0, + TRANS_FIFO_FULL = 1, + TRANS_FIFO_AF = 2, + RCIU_PFPTRANS_WAIT = 3, + Reserved_04 = 4, + Reserved_05 = 5, + RCIU_NRTTRANS_WAIT = 6, + Reserved_07 = 7, + CSF_NRT_READ_WAIT = 8, + CSF_I1_FIFO_FULL = 9, + CSF_I2_FIFO_FULL = 10, + CSF_ST_FIFO_FULL = 11, + Reserved_12 = 12, + CSF_RING_ROQ_FULL = 13, + CSF_I1_ROQ_FULL = 14, + CSF_I2_ROQ_FULL = 15, + CSF_ST_ROQ_FULL = 16, + Reserved_17 = 17, + MIU_TAG_MEM_FULL = 18, + MIU_WRITECLEAN = 19, + Reserved_20 = 20, + Reserved_21 = 21, + MIU_NRT_WRITE_STALLED = 22, + MIU_NRT_READ_STALLED = 23, + ME_WRITE_CONFIRM_FIFO_FULL = 24, + ME_VS_DEALLOC_FIFO_FULL = 25, + ME_PS_DEALLOC_FIFO_FULL = 26, + ME_REGS_VS_EVENT_FIFO_FULL = 27, + ME_REGS_PS_EVENT_FIFO_FULL = 28, + ME_REGS_CF_EVENT_FIFO_FULL = 29, + ME_MICRO_RB_STARVED = 30, + ME_MICRO_I1_STARVED = 31, + ME_MICRO_I2_STARVED = 32, + ME_MICRO_ST_STARVED = 33, + Reserved_34 = 34, + Reserved_35 = 35, + Reserved_36 = 36, + Reserved_37 = 37, + Reserved_38 = 38, + Reserved_39 = 39, + RCIU_RBBM_DWORD_SENT = 40, + ME_BUSY_CLOCKS = 41, + ME_WAIT_CONTEXT_AVAIL = 42, + PFP_TYPE0_PACKET = 43, + PFP_TYPE3_PACKET = 44, + CSF_RB_WPTR_NEQ_RPTR = 45, + CSF_I1_SIZE_NEQ_ZERO = 46, + CSF_I2_SIZE_NEQ_ZERO = 47, + CSF_RBI1I2_FETCHING = 48, + Reserved_49 = 49, + Reserved_50 = 50, + Reserved_51 = 51, + Reserved_52 = 52, + Reserved_53 = 53, + Reserved_54 = 54, + Reserved_55 = 55, + Reserved_56 = 56, + Reserved_57 = 57, + Reserved_58 = 58, + Reserved_59 = 59, + Reserved_60 = 60, + Reserved_61 = 61, + Reserved_62 = 62, + Reserved_63 = 63 +} CP_PERFCOUNT_SEL; +#endif /*ENUMS_CP_PERFCOUNT_SEL_H*/ + +/******************************************************* + * SC Enums + *******************************************************/ +/******************************************************* + * BC Enums + *******************************************************/ +#ifndef ENUMS_ColorformatX_H +#define ENUMS_ColorformatX_H +typedef enum ColorformatX { + COLORX_4_4_4_4 = 0, + COLORX_1_5_5_5 = 1, + COLORX_5_6_5 = 2, + COLORX_8 = 3, + COLORX_8_8 = 4, + COLORX_8_8_8_8 = 5, + COLORX_S8_8_8_8 = 6, + COLORX_16_FLOAT = 7, + COLORX_16_16_FLOAT = 8, + COLORX_16_16_16_16_FLOAT = 9, + COLORX_32_FLOAT = 10, + COLORX_32_32_FLOAT = 11, + COLORX_32_32_32_32_FLOAT = 12, + COLORX_2_3_3 = 13, + COLORX_8_8_8 = 14, +} ColorformatX; +#endif /*ENUMS_ColorformatX_H*/ + +#ifndef ENUMS_DepthformatX_H +#define ENUMS_DepthformatX_H +typedef enum DepthformatX { + DEPTHX_16 = 0, + DEPTHX_24_8 = 1 +} DepthformatX; +#endif /*ENUMS_DepthformatX_H*/ + +#ifndef ENUMS_CompareFrag_H +#define ENUMS_CompareFrag_H +typedef enum CompareFrag { + FRAG_NEVER = 0, + FRAG_LESS = 1, + FRAG_EQUAL = 2, + FRAG_LEQUAL = 3, + FRAG_GREATER = 4, + FRAG_NOTEQUAL = 5, + FRAG_GEQUAL = 6, + FRAG_ALWAYS = 7 +} CompareFrag; +#endif /*ENUMS_CompareFrag_H*/ + +#ifndef ENUMS_CompareRef_H +#define ENUMS_CompareRef_H +typedef enum CompareRef { + REF_NEVER = 0, + REF_LESS = 1, + REF_EQUAL = 2, + REF_LEQUAL = 3, + REF_GREATER = 4, + REF_NOTEQUAL = 5, + REF_GEQUAL = 6, + REF_ALWAYS = 7 +} CompareRef; +#endif /*ENUMS_CompareRef_H*/ + +#ifndef ENUMS_StencilOp_H +#define ENUMS_StencilOp_H +typedef enum StencilOp { + STENCIL_KEEP = 0, + STENCIL_ZERO = 1, + STENCIL_REPLACE = 2, + STENCIL_INCR_CLAMP = 3, + STENCIL_DECR_CLAMP = 4, + STENCIL_INVERT = 5, + STENCIL_INCR_WRAP = 6, + STENCIL_DECR_WRAP = 7 +} StencilOp; +#endif /*ENUMS_StencilOp_H*/ + +#ifndef ENUMS_BlendOpX_H +#define ENUMS_BlendOpX_H +typedef enum BlendOpX { + BLENDX_ZERO = 0, + BLENDX_ONE = 1, + BLENDX_SRC_COLOR = 4, + BLENDX_ONE_MINUS_SRC_COLOR = 5, + BLENDX_SRC_ALPHA = 6, + BLENDX_ONE_MINUS_SRC_ALPHA = 7, + BLENDX_DST_COLOR = 8, + BLENDX_ONE_MINUS_DST_COLOR = 9, + BLENDX_DST_ALPHA = 10, + BLENDX_ONE_MINUS_DST_ALPHA = 11, + BLENDX_CONSTANT_COLOR = 12, + BLENDX_ONE_MINUS_CONSTANT_COLOR = 13, + BLENDX_CONSTANT_ALPHA = 14, + BLENDX_ONE_MINUS_CONSTANT_ALPHA = 15, + BLENDX_SRC_ALPHA_SATURATE = 16, +} BlendOpX; +#endif /*ENUMS_BlendOpX_H*/ + +#ifndef ENUMS_CombFuncX_H +#define ENUMS_CombFuncX_H +typedef enum CombFuncX { + COMB_DST_PLUS_SRC = 0, + COMB_SRC_MINUS_DST = 1, + COMB_MIN_DST_SRC = 2, + COMB_MAX_DST_SRC = 3, + COMB_DST_MINUS_SRC = 4, + COMB_DST_PLUS_SRC_BIAS = 5, +} CombFuncX; +#endif /*ENUMS_CombFuncX_H*/ + +#ifndef ENUMS_DitherModeX_H +#define ENUMS_DitherModeX_H +typedef enum DitherModeX { + DITHER_DISABLE = 0, + DITHER_ALWAYS = 1, + DITHER_IF_ALPHA_OFF = 2, +} DitherModeX; +#endif /*ENUMS_DitherModeX_H*/ + +#ifndef ENUMS_DitherTypeX_H +#define ENUMS_DitherTypeX_H +typedef enum DitherTypeX { + DITHER_PIXEL = 0, + DITHER_SUBPIXEL = 1, +} DitherTypeX; +#endif /*ENUMS_DitherTypeX_H*/ + +#ifndef ENUMS_EdramMode_H +#define ENUMS_EdramMode_H +typedef enum EdramMode { + EDRAM_NOP = 0, + COLOR_DEPTH = 4, + DEPTH_ONLY = 5, + EDRAM_COPY = 6, +} EdramMode; +#endif /*ENUMS_EdramMode_H*/ + +#ifndef ENUMS_SurfaceEndian_H +#define ENUMS_SurfaceEndian_H +typedef enum SurfaceEndian { + ENDIAN_NONE = 0, + ENDIAN_8IN16 = 1, + ENDIAN_8IN32 = 2, + ENDIAN_16IN32 = 3, + ENDIAN_8IN64 = 4, + ENDIAN_8IN128 = 5, +} SurfaceEndian; +#endif /*ENUMS_SurfaceEndian_H*/ + +#ifndef ENUMS_EdramSizeX_H +#define ENUMS_EdramSizeX_H +typedef enum EdramSizeX { + EDRAMSIZE_16KB = 0, + EDRAMSIZE_32KB = 1, + EDRAMSIZE_64KB = 2, + EDRAMSIZE_128KB = 3, + EDRAMSIZE_256KB = 4, + EDRAMSIZE_512KB = 5, + EDRAMSIZE_1MB = 6, + EDRAMSIZE_2MB = 7, + EDRAMSIZE_4MB = 8, + EDRAMSIZE_8MB = 9, + EDRAMSIZE_16MB = 10, +} EdramSizeX; +#endif /*ENUMS_EdramSizeX_H*/ + +#ifndef ENUMS_RB_PERFCNT_SELECT_H +#define ENUMS_RB_PERFCNT_SELECT_H +typedef enum RB_PERFCNT_SELECT { + RBPERF_CNTX_BUSY = 0, + RBPERF_CNTX_BUSY_MAX = 1, + RBPERF_SX_QUAD_STARVED = 2, + RBPERF_SX_QUAD_STARVED_MAX = 3, + RBPERF_GA_GC_CH0_SYS_REQ = 4, + RBPERF_GA_GC_CH0_SYS_REQ_MAX = 5, + RBPERF_GA_GC_CH1_SYS_REQ = 6, + RBPERF_GA_GC_CH1_SYS_REQ_MAX = 7, + RBPERF_MH_STARVED = 8, + RBPERF_MH_STARVED_MAX = 9, + RBPERF_AZ_BC_COLOR_BUSY = 10, + RBPERF_AZ_BC_COLOR_BUSY_MAX = 11, + RBPERF_AZ_BC_Z_BUSY = 12, + RBPERF_AZ_BC_Z_BUSY_MAX = 13, + RBPERF_RB_SC_TILE_RTR_N = 14, + RBPERF_RB_SC_TILE_RTR_N_MAX = 15, + RBPERF_RB_SC_SAMP_RTR_N = 16, + RBPERF_RB_SC_SAMP_RTR_N_MAX = 17, + RBPERF_RB_SX_QUAD_RTR_N = 18, + RBPERF_RB_SX_QUAD_RTR_N_MAX = 19, + RBPERF_RB_SX_COLOR_RTR_N = 20, + RBPERF_RB_SX_COLOR_RTR_N_MAX = 21, + RBPERF_RB_SC_SAMP_LZ_BUSY = 22, + RBPERF_RB_SC_SAMP_LZ_BUSY_MAX = 23, + RBPERF_ZXP_STALL = 24, + RBPERF_ZXP_STALL_MAX = 25, + RBPERF_EVENT_PENDING = 26, + RBPERF_EVENT_PENDING_MAX = 27, + RBPERF_RB_MH_VALID = 28, + RBPERF_RB_MH_VALID_MAX = 29, + RBPERF_SX_RB_QUAD_SEND = 30, + RBPERF_SX_RB_COLOR_SEND = 31, + RBPERF_SC_RB_TILE_SEND = 32, + RBPERF_SC_RB_SAMPLE_SEND = 33, + RBPERF_SX_RB_MEM_EXPORT = 34, + RBPERF_SX_RB_QUAD_EVENT = 35, + RBPERF_SC_RB_TILE_EVENT_FILTERED = 36, + RBPERF_SC_RB_TILE_EVENT_ALL = 37, + RBPERF_RB_SC_EZ_SEND = 38, + RBPERF_RB_SX_INDEX_SEND = 39, + RBPERF_GMEM_INTFO_RD = 40, + RBPERF_GMEM_INTF1_RD = 41, + RBPERF_GMEM_INTFO_WR = 42, + RBPERF_GMEM_INTF1_WR = 43, + RBPERF_RB_CP_CONTEXT_DONE = 44, + RBPERF_RB_CP_CACHE_FLUSH = 45, + RBPERF_ZPASS_DONE = 46, + RBPERF_ZCMD_VALID = 47, + RBPERF_CCMD_VALID = 48, + RBPERF_ACCUM_GRANT = 49, + RBPERF_ACCUM_C0_GRANT = 50, + RBPERF_ACCUM_C1_GRANT = 51, + RBPERF_ACCUM_FULL_BE_WR = 52, + RBPERF_ACCUM_REQUEST_NO_GRANT = 53, + RBPERF_ACCUM_TIMEOUT_PULSE = 54, + RBPERF_ACCUM_LIN_TIMEOUT_PULSE = 55, + RBPERF_ACCUM_CAM_HIT_FLUSHING = 56, +} RB_PERFCNT_SELECT; +#endif /*ENUMS_RB_PERFCNT_SELECT_H*/ + +#ifndef ENUMS_DepthFormat_H +#define ENUMS_DepthFormat_H +typedef enum DepthFormat { + DEPTH_24_8 = 22, + DEPTH_24_8_FLOAT = 23, + DEPTH_16 = 24, +} DepthFormat; +#endif /*ENUMS_DepthFormat_H*/ + +#ifndef ENUMS_SurfaceSwap_H +#define ENUMS_SurfaceSwap_H +typedef enum SurfaceSwap { + SWAP_LOWRED = 0, + SWAP_LOWBLUE = 1 +} SurfaceSwap; +#endif /*ENUMS_SurfaceSwap_H*/ + +#ifndef ENUMS_DepthArray_H +#define ENUMS_DepthArray_H +typedef enum DepthArray { + ARRAY_2D_ALT_DEPTH = 0, + ARRAY_2D_DEPTH = 1, +} DepthArray; +#endif /*ENUMS_DepthArray_H*/ + +#ifndef ENUMS_ColorArray_H +#define ENUMS_ColorArray_H +typedef enum ColorArray { + ARRAY_2D_ALT_COLOR = 0, + ARRAY_2D_COLOR = 1, + ARRAY_3D_SLICE_COLOR = 3 +} ColorArray; +#endif /*ENUMS_ColorArray_H*/ + +#ifndef ENUMS_ColorFormat_H +#define ENUMS_ColorFormat_H +typedef enum ColorFormat { + COLOR_8 = 2, + COLOR_1_5_5_5 = 3, + COLOR_5_6_5 = 4, + COLOR_6_5_5 = 5, + COLOR_8_8_8_8 = 6, + COLOR_2_10_10_10 = 7, + COLOR_8_A = 8, + COLOR_8_B = 9, + COLOR_8_8 = 10, + COLOR_8_8_8 = 11, + COLOR_8_8_8_8_A = 14, + COLOR_4_4_4_4 = 15, + COLOR_10_11_11 = 16, + COLOR_11_11_10 = 17, + COLOR_16 = 24, + COLOR_16_16 = 25, + COLOR_16_16_16_16 = 26, + COLOR_16_FLOAT = 30, + COLOR_16_16_FLOAT = 31, + COLOR_16_16_16_16_FLOAT = 32, + COLOR_32_FLOAT = 36, + COLOR_32_32_FLOAT = 37, + COLOR_32_32_32_32_FLOAT = 38, + COLOR_2_3_3 = 39, +} ColorFormat; +#endif /*ENUMS_ColorFormat_H*/ + +#ifndef ENUMS_SurfaceNumber_H +#define ENUMS_SurfaceNumber_H +typedef enum SurfaceNumber { + NUMBER_UREPEAT = 0, + NUMBER_SREPEAT = 1, + NUMBER_UINTEGER = 2, + NUMBER_SINTEGER = 3, + NUMBER_GAMMA = 4, + NUMBER_FIXED = 5, + NUMBER_FLOAT = 7 +} SurfaceNumber; +#endif /*ENUMS_SurfaceNumber_H*/ + +#ifndef ENUMS_SurfaceFormat_H +#define ENUMS_SurfaceFormat_H +typedef enum SurfaceFormat { + FMT_1_REVERSE = 0, + FMT_1 = 1, + FMT_8 = 2, + FMT_1_5_5_5 = 3, + FMT_5_6_5 = 4, + FMT_6_5_5 = 5, + FMT_8_8_8_8 = 6, + FMT_2_10_10_10 = 7, + FMT_8_A = 8, + FMT_8_B = 9, + FMT_8_8 = 10, + FMT_Cr_Y1_Cb_Y0 = 11, + FMT_Y1_Cr_Y0_Cb = 12, + FMT_5_5_5_1 = 13, + FMT_8_8_8_8_A = 14, + FMT_4_4_4_4 = 15, + FMT_8_8_8 = 16, + FMT_DXT1 = 18, + FMT_DXT2_3 = 19, + FMT_DXT4_5 = 20, + FMT_10_10_10_2 = 21, + FMT_24_8 = 22, + FMT_16 = 24, + FMT_16_16 = 25, + FMT_16_16_16_16 = 26, + FMT_16_EXPAND = 27, + FMT_16_16_EXPAND = 28, + FMT_16_16_16_16_EXPAND = 29, + FMT_16_FLOAT = 30, + FMT_16_16_FLOAT = 31, + FMT_16_16_16_16_FLOAT = 32, + FMT_32 = 33, + FMT_32_32 = 34, + FMT_32_32_32_32 = 35, + FMT_32_FLOAT = 36, + FMT_32_32_FLOAT = 37, + FMT_32_32_32_32_FLOAT = 38, + FMT_ATI_TC_RGB = 39, + FMT_ATI_TC_RGBA = 40, + FMT_ATI_TC_555_565_RGB = 41, + FMT_ATI_TC_555_565_RGBA = 42, + FMT_ATI_TC_RGBA_INTERP = 43, + FMT_ATI_TC_555_565_RGBA_INTERP = 44, + FMT_ETC1_RGBA_INTERP = 46, + FMT_ETC1_RGB = 47, + FMT_ETC1_RGBA = 48, + FMT_DXN = 49, + FMT_2_3_3 = 51, + FMT_2_10_10_10_AS_16_16_16_16 = 54, + FMT_10_10_10_2_AS_16_16_16_16 = 55, + FMT_32_32_32_FLOAT = 57, + FMT_DXT3A = 58, + FMT_DXT5A = 59, + FMT_CTX1 = 60, +} SurfaceFormat; +#endif /*ENUMS_SurfaceFormat_H*/ + +#ifndef ENUMS_SurfaceTiling_H +#define ENUMS_SurfaceTiling_H +typedef enum SurfaceTiling { + ARRAY_LINEAR = 0, + ARRAY_TILED = 1 +} SurfaceTiling; +#endif /*ENUMS_SurfaceTiling_H*/ + +#ifndef ENUMS_SurfaceArray_H +#define ENUMS_SurfaceArray_H +typedef enum SurfaceArray { + ARRAY_1D = 0, + ARRAY_2D = 1, + ARRAY_3D = 2, + ARRAY_3D_SLICE = 3 +} SurfaceArray; +#endif /*ENUMS_SurfaceArray_H*/ + +#ifndef ENUMS_SurfaceNumberX_H +#define ENUMS_SurfaceNumberX_H +typedef enum SurfaceNumberX { + NUMBERX_UREPEAT = 0, + NUMBERX_SREPEAT = 1, + NUMBERX_UINTEGER = 2, + NUMBERX_SINTEGER = 3, + NUMBERX_FLOAT = 7 +} SurfaceNumberX; +#endif /*ENUMS_SurfaceNumberX_H*/ + +#ifndef ENUMS_ColorArrayX_H +#define ENUMS_ColorArrayX_H +typedef enum ColorArrayX { + ARRAYX_2D_COLOR = 0, + ARRAYX_3D_SLICE_COLOR = 1, +} ColorArrayX; +#endif /*ENUMS_ColorArrayX_H*/ + +#endif /*_yamato_ENUM_HEADER*/ + diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_genenum.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_genenum.h new file mode 100644 index 000000000000..87a454a1e38a --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_genenum.h @@ -0,0 +1,1703 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +START_ENUMTYPE(SU_PERFCNT_SELECT) + GENERATE_ENUM(PERF_PAPC_PASX_REQ, 0) + GENERATE_ENUM(UNUSED1, 1) + GENERATE_ENUM(PERF_PAPC_PASX_FIRST_VECTOR, 2) + GENERATE_ENUM(PERF_PAPC_PASX_SECOND_VECTOR, 3) + GENERATE_ENUM(PERF_PAPC_PASX_FIRST_DEAD, 4) + GENERATE_ENUM(PERF_PAPC_PASX_SECOND_DEAD, 5) + GENERATE_ENUM(PERF_PAPC_PASX_VTX_KILL_DISCARD, 6) + GENERATE_ENUM(PERF_PAPC_PASX_VTX_NAN_DISCARD, 7) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_PRIM, 8) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_NULL_PRIM, 9) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_EVENT_FLAG, 10) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT, 11) + GENERATE_ENUM(PERF_PAPC_PA_INPUT_END_OF_PACKET, 12) + GENERATE_ENUM(PERF_PAPC_CLPR_CULL_PRIM, 13) + GENERATE_ENUM(UNUSED2, 14) + GENERATE_ENUM(PERF_PAPC_CLPR_VV_CULL_PRIM, 15) + GENERATE_ENUM(UNUSED3, 16) + GENERATE_ENUM(PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM, 17) + GENERATE_ENUM(PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM, 18) + GENERATE_ENUM(PERF_PAPC_CLPR_CULL_TO_NULL_PRIM, 19) + GENERATE_ENUM(UNUSED4, 20) + GENERATE_ENUM(PERF_PAPC_CLPR_VV_CLIP_PRIM, 21) + GENERATE_ENUM(UNUSED5, 22) + GENERATE_ENUM(PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE, 23) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_1, 24) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_2, 25) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_3, 26) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_4, 27) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_5, 28) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_CNT_6, 29) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_NEAR, 30) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_FAR, 31) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_LEFT, 32) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_RIGHT, 33) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_TOP, 34) + GENERATE_ENUM(PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM, 35) + GENERATE_ENUM(PERF_PAPC_CLSM_NULL_PRIM, 36) + GENERATE_ENUM(PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM, 37) + GENERATE_ENUM(PERF_PAPC_CLSM_CLIP_PRIM, 38) + GENERATE_ENUM(PERF_PAPC_CLSM_CULL_TO_NULL_PRIM, 39) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_1, 40) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_2, 41) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_3, 42) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_4, 43) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_5, 44) + GENERATE_ENUM(PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7, 45) + GENERATE_ENUM(PERF_PAPC_CLSM_NON_TRIVIAL_CULL, 46) + GENERATE_ENUM(PERF_PAPC_SU_INPUT_PRIM, 47) + GENERATE_ENUM(PERF_PAPC_SU_INPUT_CLIP_PRIM, 48) + GENERATE_ENUM(PERF_PAPC_SU_INPUT_NULL_PRIM, 49) + GENERATE_ENUM(PERF_PAPC_SU_ZERO_AREA_CULL_PRIM, 50) + GENERATE_ENUM(PERF_PAPC_SU_BACK_FACE_CULL_PRIM, 51) + GENERATE_ENUM(PERF_PAPC_SU_FRONT_FACE_CULL_PRIM, 52) + GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_FACE_CULL, 53) + GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_BACK_CULL, 54) + GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_FRONT_CULL, 55) + GENERATE_ENUM(PERF_PAPC_SU_POLYMODE_INVALID_FILL, 56) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_PRIM, 57) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_CLIP_PRIM, 58) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_NULL_PRIM, 59) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_EVENT_FLAG, 60) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT, 61) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_END_OF_PACKET, 62) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_FACE, 63) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_BACK, 64) + GENERATE_ENUM(PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT, 65) + GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE, 66) + GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK, 67) + GENERATE_ENUM(PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT, 68) + GENERATE_ENUM(PERF_PAPC_PASX_REQ_IDLE, 69) + GENERATE_ENUM(PERF_PAPC_PASX_REQ_BUSY, 70) + GENERATE_ENUM(PERF_PAPC_PASX_REQ_STALLED, 71) + GENERATE_ENUM(PERF_PAPC_PASX_REC_IDLE, 72) + GENERATE_ENUM(PERF_PAPC_PASX_REC_BUSY, 73) + GENERATE_ENUM(PERF_PAPC_PASX_REC_STARVED_SX, 74) + GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED, 75) + GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED_POS_MEM, 76) + GENERATE_ENUM(PERF_PAPC_PASX_REC_STALLED_CCGSM_IN, 77) + GENERATE_ENUM(PERF_PAPC_CCGSM_IDLE, 78) + GENERATE_ENUM(PERF_PAPC_CCGSM_BUSY, 79) + GENERATE_ENUM(PERF_PAPC_CCGSM_STALLED, 80) + GENERATE_ENUM(PERF_PAPC_CLPRIM_IDLE, 81) + GENERATE_ENUM(PERF_PAPC_CLPRIM_BUSY, 82) + GENERATE_ENUM(PERF_PAPC_CLPRIM_STALLED, 83) + GENERATE_ENUM(PERF_PAPC_CLPRIM_STARVED_CCGSM, 84) + GENERATE_ENUM(PERF_PAPC_CLIPSM_IDLE, 85) + GENERATE_ENUM(PERF_PAPC_CLIPSM_BUSY, 86) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH, 87) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ, 88) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIPGA, 89) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP, 90) + GENERATE_ENUM(PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM, 91) + GENERATE_ENUM(PERF_PAPC_CLIPGA_IDLE, 92) + GENERATE_ENUM(PERF_PAPC_CLIPGA_BUSY, 93) + GENERATE_ENUM(PERF_PAPC_CLIPGA_STARVED_VTE_CLIP, 94) + GENERATE_ENUM(PERF_PAPC_CLIPGA_STALLED, 95) + GENERATE_ENUM(PERF_PAPC_CLIP_IDLE, 96) + GENERATE_ENUM(PERF_PAPC_CLIP_BUSY, 97) + GENERATE_ENUM(PERF_PAPC_SU_IDLE, 98) + GENERATE_ENUM(PERF_PAPC_SU_BUSY, 99) + GENERATE_ENUM(PERF_PAPC_SU_STARVED_CLIP, 100) + GENERATE_ENUM(PERF_PAPC_SU_STALLED_SC, 101) + GENERATE_ENUM(PERF_PAPC_SU_FACENESS_CULL, 102) +END_ENUMTYPE(SU_PERFCNT_SELECT) + +START_ENUMTYPE(SC_PERFCNT_SELECT) + GENERATE_ENUM(SC_SR_WINDOW_VALID, 0) + GENERATE_ENUM(SC_CW_WINDOW_VALID, 1) + GENERATE_ENUM(SC_QM_WINDOW_VALID, 2) + GENERATE_ENUM(SC_FW_WINDOW_VALID, 3) + GENERATE_ENUM(SC_EZ_WINDOW_VALID, 4) + GENERATE_ENUM(SC_IT_WINDOW_VALID, 5) + GENERATE_ENUM(SC_STARVED_BY_PA, 6) + GENERATE_ENUM(SC_STALLED_BY_RB_TILE, 7) + GENERATE_ENUM(SC_STALLED_BY_RB_SAMP, 8) + GENERATE_ENUM(SC_STARVED_BY_RB_EZ, 9) + GENERATE_ENUM(SC_STALLED_BY_SAMPLE_FF, 10) + GENERATE_ENUM(SC_STALLED_BY_SQ, 11) + GENERATE_ENUM(SC_STALLED_BY_SP, 12) + GENERATE_ENUM(SC_TOTAL_NO_PRIMS, 13) + GENERATE_ENUM(SC_NON_EMPTY_PRIMS, 14) + GENERATE_ENUM(SC_NO_TILES_PASSING_QM, 15) + GENERATE_ENUM(SC_NO_PIXELS_PRE_EZ, 16) + GENERATE_ENUM(SC_NO_PIXELS_POST_EZ, 17) +END_ENUMTYPE(SC_PERFCNT_SELECT) + +START_ENUMTYPE(VGT_DI_PRIM_TYPE) + GENERATE_ENUM(DI_PT_NONE, 0) + GENERATE_ENUM(DI_PT_POINTLIST, 1) + GENERATE_ENUM(DI_PT_LINELIST, 2) + GENERATE_ENUM(DI_PT_LINESTRIP, 3) + GENERATE_ENUM(DI_PT_TRILIST, 4) + GENERATE_ENUM(DI_PT_TRIFAN, 5) + GENERATE_ENUM(DI_PT_TRISTRIP, 6) + GENERATE_ENUM(DI_PT_UNUSED_1, 7) + GENERATE_ENUM(DI_PT_RECTLIST, 8) + GENERATE_ENUM(DI_PT_UNUSED_2, 9) + GENERATE_ENUM(DI_PT_UNUSED_3, 10) + GENERATE_ENUM(DI_PT_UNUSED_4, 11) + GENERATE_ENUM(DI_PT_UNUSED_5, 12) + GENERATE_ENUM(DI_PT_QUADLIST, 13) + GENERATE_ENUM(DI_PT_QUADSTRIP, 14) + GENERATE_ENUM(DI_PT_POLYGON, 15) + GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V0, 16) + GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V1, 17) + GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V2, 18) + GENERATE_ENUM(DI_PT_2D_COPY_RECT_LIST_V3, 19) + GENERATE_ENUM(DI_PT_2D_FILL_RECT_LIST, 20) + GENERATE_ENUM(DI_PT_2D_LINE_STRIP, 21) + GENERATE_ENUM(DI_PT_2D_TRI_STRIP, 22) +END_ENUMTYPE(VGT_DI_PRIM_TYPE) + +START_ENUMTYPE(VGT_DI_SOURCE_SELECT) + GENERATE_ENUM(DI_SRC_SEL_DMA, 0) + GENERATE_ENUM(DI_SRC_SEL_IMMEDIATE, 1) + GENERATE_ENUM(DI_SRC_SEL_AUTO_INDEX, 2) + GENERATE_ENUM(DI_SRC_SEL_RESERVED, 3) +END_ENUMTYPE(VGT_DI_SOURCE_SELECT) + +START_ENUMTYPE(VGT_DI_FACENESS_CULL_SELECT) + GENERATE_ENUM(DI_FACE_CULL_NONE, 0) + GENERATE_ENUM(DI_FACE_CULL_FETCH, 1) + GENERATE_ENUM(DI_FACE_BACKFACE_CULL, 2) + GENERATE_ENUM(DI_FACE_FRONTFACE_CULL, 3) +END_ENUMTYPE(VGT_DI_FACENESS_CULL_SELECT) + +START_ENUMTYPE(VGT_DI_INDEX_SIZE) + GENERATE_ENUM(DI_INDEX_SIZE_16_BIT, 0) + GENERATE_ENUM(DI_INDEX_SIZE_32_BIT, 1) +END_ENUMTYPE(VGT_DI_INDEX_SIZE) + +START_ENUMTYPE(VGT_DI_SMALL_INDEX) + GENERATE_ENUM(DI_USE_INDEX_SIZE, 0) + GENERATE_ENUM(DI_INDEX_SIZE_8_BIT, 1) +END_ENUMTYPE(VGT_DI_SMALL_INDEX) + +START_ENUMTYPE(VGT_DI_PRE_FETCH_CULL_ENABLE) + GENERATE_ENUM(DISABLE_PRE_FETCH_CULL_ENABLE, 0) + GENERATE_ENUM(PRE_FETCH_CULL_ENABLE, 1) +END_ENUMTYPE(VGT_DI_PRE_FETCH_CULL_ENABLE) + +START_ENUMTYPE(VGT_DI_GRP_CULL_ENABLE) + GENERATE_ENUM(DISABLE_GRP_CULL_ENABLE, 0) + GENERATE_ENUM(GRP_CULL_ENABLE, 1) +END_ENUMTYPE(VGT_DI_GRP_CULL_ENABLE) + +START_ENUMTYPE(VGT_EVENT_TYPE) + GENERATE_ENUM(VS_DEALLOC, 0) + GENERATE_ENUM(PS_DEALLOC, 1) + GENERATE_ENUM(VS_DONE_TS, 2) + GENERATE_ENUM(PS_DONE_TS, 3) + GENERATE_ENUM(CACHE_FLUSH_TS, 4) + GENERATE_ENUM(CONTEXT_DONE, 5) + GENERATE_ENUM(CACHE_FLUSH, 6) + GENERATE_ENUM(VIZQUERY_START, 7) + GENERATE_ENUM(VIZQUERY_END, 8) + GENERATE_ENUM(SC_WAIT_WC, 9) + GENERATE_ENUM(RST_PIX_CNT, 13) + GENERATE_ENUM(RST_VTX_CNT, 14) + GENERATE_ENUM(TILE_FLUSH, 15) + GENERATE_ENUM(CACHE_FLUSH_AND_INV_TS_EVENT, 20) + GENERATE_ENUM(ZPASS_DONE, 21) + GENERATE_ENUM(CACHE_FLUSH_AND_INV_EVENT, 22) + GENERATE_ENUM(PERFCOUNTER_START, 23) + GENERATE_ENUM(PERFCOUNTER_STOP, 24) + GENERATE_ENUM(VS_FETCH_DONE, 27) + GENERATE_ENUM(FACENESS_FLUSH, 28) +END_ENUMTYPE(VGT_EVENT_TYPE) + +START_ENUMTYPE(VGT_DMA_SWAP_MODE) + GENERATE_ENUM(VGT_DMA_SWAP_NONE, 0) + GENERATE_ENUM(VGT_DMA_SWAP_16_BIT, 1) + GENERATE_ENUM(VGT_DMA_SWAP_32_BIT, 2) + GENERATE_ENUM(VGT_DMA_SWAP_WORD, 3) +END_ENUMTYPE(VGT_DMA_SWAP_MODE) + +START_ENUMTYPE(VGT_PERFCOUNT_SELECT) + GENERATE_ENUM(VGT_SQ_EVENT_WINDOW_ACTIVE, 0) + GENERATE_ENUM(VGT_SQ_SEND, 1) + GENERATE_ENUM(VGT_SQ_STALLED, 2) + GENERATE_ENUM(VGT_SQ_STARVED_BUSY, 3) + GENERATE_ENUM(VGT_SQ_STARVED_IDLE, 4) + GENERATE_ENUM(VGT_SQ_STATIC, 5) + GENERATE_ENUM(VGT_PA_EVENT_WINDOW_ACTIVE, 6) + GENERATE_ENUM(VGT_PA_CLIP_V_SEND, 7) + GENERATE_ENUM(VGT_PA_CLIP_V_STALLED, 8) + GENERATE_ENUM(VGT_PA_CLIP_V_STARVED_BUSY, 9) + GENERATE_ENUM(VGT_PA_CLIP_V_STARVED_IDLE, 10) + GENERATE_ENUM(VGT_PA_CLIP_V_STATIC, 11) + GENERATE_ENUM(VGT_PA_CLIP_P_SEND, 12) + GENERATE_ENUM(VGT_PA_CLIP_P_STALLED, 13) + GENERATE_ENUM(VGT_PA_CLIP_P_STARVED_BUSY, 14) + GENERATE_ENUM(VGT_PA_CLIP_P_STARVED_IDLE, 15) + GENERATE_ENUM(VGT_PA_CLIP_P_STATIC, 16) + GENERATE_ENUM(VGT_PA_CLIP_S_SEND, 17) + GENERATE_ENUM(VGT_PA_CLIP_S_STALLED, 18) + GENERATE_ENUM(VGT_PA_CLIP_S_STARVED_BUSY, 19) + GENERATE_ENUM(VGT_PA_CLIP_S_STARVED_IDLE, 20) + GENERATE_ENUM(VGT_PA_CLIP_S_STATIC, 21) + GENERATE_ENUM(RBIU_FIFOS_EVENT_WINDOW_ACTIVE, 22) + GENERATE_ENUM(RBIU_IMMED_DATA_FIFO_STARVED, 23) + GENERATE_ENUM(RBIU_IMMED_DATA_FIFO_STALLED, 24) + GENERATE_ENUM(RBIU_DMA_REQUEST_FIFO_STARVED, 25) + GENERATE_ENUM(RBIU_DMA_REQUEST_FIFO_STALLED, 26) + GENERATE_ENUM(RBIU_DRAW_INITIATOR_FIFO_STARVED, 27) + GENERATE_ENUM(RBIU_DRAW_INITIATOR_FIFO_STALLED, 28) + GENERATE_ENUM(BIN_PRIM_NEAR_CULL, 29) + GENERATE_ENUM(BIN_PRIM_ZERO_CULL, 30) + GENERATE_ENUM(BIN_PRIM_FAR_CULL, 31) + GENERATE_ENUM(BIN_PRIM_BIN_CULL, 32) + GENERATE_ENUM(BIN_PRIM_FACE_CULL, 33) + GENERATE_ENUM(SPARE34, 34) + GENERATE_ENUM(SPARE35, 35) + GENERATE_ENUM(SPARE36, 36) + GENERATE_ENUM(SPARE37, 37) + GENERATE_ENUM(SPARE38, 38) + GENERATE_ENUM(SPARE39, 39) + GENERATE_ENUM(TE_SU_IN_VALID, 40) + GENERATE_ENUM(TE_SU_IN_READ, 41) + GENERATE_ENUM(TE_SU_IN_PRIM, 42) + GENERATE_ENUM(TE_SU_IN_EOP, 43) + GENERATE_ENUM(TE_SU_IN_NULL_PRIM, 44) + GENERATE_ENUM(TE_WK_IN_VALID, 45) + GENERATE_ENUM(TE_WK_IN_READ, 46) + GENERATE_ENUM(TE_OUT_PRIM_VALID, 47) + GENERATE_ENUM(TE_OUT_PRIM_READ, 48) +END_ENUMTYPE(VGT_PERFCOUNT_SELECT) + +START_ENUMTYPE(TCR_PERFCOUNT_SELECT) + GENERATE_ENUM(DGMMPD_IPMUX0_STALL, 0) + GENERATE_ENUM(reserved_46, 1) + GENERATE_ENUM(reserved_47, 2) + GENERATE_ENUM(reserved_48, 3) + GENERATE_ENUM(DGMMPD_IPMUX_ALL_STALL, 4) + GENERATE_ENUM(OPMUX0_L2_WRITES, 5) + GENERATE_ENUM(reserved_49, 6) + GENERATE_ENUM(reserved_50, 7) + GENERATE_ENUM(reserved_51, 8) +END_ENUMTYPE(TCR_PERFCOUNT_SELECT) + +START_ENUMTYPE(TP_PERFCOUNT_SELECT) + GENERATE_ENUM(POINT_QUADS, 0) + GENERATE_ENUM(BILIN_QUADS, 1) + GENERATE_ENUM(ANISO_QUADS, 2) + GENERATE_ENUM(MIP_QUADS, 3) + GENERATE_ENUM(VOL_QUADS, 4) + GENERATE_ENUM(MIP_VOL_QUADS, 5) + GENERATE_ENUM(MIP_ANISO_QUADS, 6) + GENERATE_ENUM(VOL_ANISO_QUADS, 7) + GENERATE_ENUM(ANISO_2_1_QUADS, 8) + GENERATE_ENUM(ANISO_4_1_QUADS, 9) + GENERATE_ENUM(ANISO_6_1_QUADS, 10) + GENERATE_ENUM(ANISO_8_1_QUADS, 11) + GENERATE_ENUM(ANISO_10_1_QUADS, 12) + GENERATE_ENUM(ANISO_12_1_QUADS, 13) + GENERATE_ENUM(ANISO_14_1_QUADS, 14) + GENERATE_ENUM(ANISO_16_1_QUADS, 15) + GENERATE_ENUM(MIP_VOL_ANISO_QUADS, 16) + GENERATE_ENUM(ALIGN_2_QUADS, 17) + GENERATE_ENUM(ALIGN_4_QUADS, 18) + GENERATE_ENUM(PIX_0_QUAD, 19) + GENERATE_ENUM(PIX_1_QUAD, 20) + GENERATE_ENUM(PIX_2_QUAD, 21) + GENERATE_ENUM(PIX_3_QUAD, 22) + GENERATE_ENUM(PIX_4_QUAD, 23) + GENERATE_ENUM(TP_MIPMAP_LOD0, 24) + GENERATE_ENUM(TP_MIPMAP_LOD1, 25) + GENERATE_ENUM(TP_MIPMAP_LOD2, 26) + GENERATE_ENUM(TP_MIPMAP_LOD3, 27) + GENERATE_ENUM(TP_MIPMAP_LOD4, 28) + GENERATE_ENUM(TP_MIPMAP_LOD5, 29) + GENERATE_ENUM(TP_MIPMAP_LOD6, 30) + GENERATE_ENUM(TP_MIPMAP_LOD7, 31) + GENERATE_ENUM(TP_MIPMAP_LOD8, 32) + GENERATE_ENUM(TP_MIPMAP_LOD9, 33) + GENERATE_ENUM(TP_MIPMAP_LOD10, 34) + GENERATE_ENUM(TP_MIPMAP_LOD11, 35) + GENERATE_ENUM(TP_MIPMAP_LOD12, 36) + GENERATE_ENUM(TP_MIPMAP_LOD13, 37) + GENERATE_ENUM(TP_MIPMAP_LOD14, 38) +END_ENUMTYPE(TP_PERFCOUNT_SELECT) + +START_ENUMTYPE(TCM_PERFCOUNT_SELECT) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_EMPTY, 0) + GENERATE_ENUM(reserved_01, 1) + GENERATE_ENUM(reserved_02, 2) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_4TH_FULL, 3) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_HALF_FULL, 4) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_FULL, 5) + GENERATE_ENUM(QUAD0_RD_LAT_FIFO_LT_4TH_FULL, 6) + GENERATE_ENUM(reserved_07, 7) + GENERATE_ENUM(reserved_08, 8) + GENERATE_ENUM(reserved_09, 9) + GENERATE_ENUM(reserved_10, 10) + GENERATE_ENUM(reserved_11, 11) + GENERATE_ENUM(reserved_12, 12) + GENERATE_ENUM(reserved_13, 13) + GENERATE_ENUM(reserved_14, 14) + GENERATE_ENUM(reserved_15, 15) + GENERATE_ENUM(reserved_16, 16) + GENERATE_ENUM(reserved_17, 17) + GENERATE_ENUM(reserved_18, 18) + GENERATE_ENUM(reserved_19, 19) + GENERATE_ENUM(reserved_20, 20) + GENERATE_ENUM(reserved_21, 21) + GENERATE_ENUM(reserved_22, 22) + GENERATE_ENUM(reserved_23, 23) + GENERATE_ENUM(reserved_24, 24) + GENERATE_ENUM(reserved_25, 25) + GENERATE_ENUM(reserved_26, 26) + GENERATE_ENUM(reserved_27, 27) + GENERATE_ENUM(READ_STARVED_QUAD0, 28) + GENERATE_ENUM(reserved_29, 29) + GENERATE_ENUM(reserved_30, 30) + GENERATE_ENUM(reserved_31, 31) + GENERATE_ENUM(READ_STARVED, 32) + GENERATE_ENUM(READ_STALLED_QUAD0, 33) + GENERATE_ENUM(reserved_34, 34) + GENERATE_ENUM(reserved_35, 35) + GENERATE_ENUM(reserved_36, 36) + GENERATE_ENUM(READ_STALLED, 37) + GENERATE_ENUM(VALID_READ_QUAD0, 38) + GENERATE_ENUM(reserved_39, 39) + GENERATE_ENUM(reserved_40, 40) + GENERATE_ENUM(reserved_41, 41) + GENERATE_ENUM(TC_TP_STARVED_QUAD0, 42) + GENERATE_ENUM(reserved_43, 43) + GENERATE_ENUM(reserved_44, 44) + GENERATE_ENUM(reserved_45, 45) + GENERATE_ENUM(TC_TP_STARVED, 46) +END_ENUMTYPE(TCM_PERFCOUNT_SELECT) + +START_ENUMTYPE(TCF_PERFCOUNT_SELECT) + GENERATE_ENUM(VALID_CYCLES, 0) + GENERATE_ENUM(SINGLE_PHASES, 1) + GENERATE_ENUM(ANISO_PHASES, 2) + GENERATE_ENUM(MIP_PHASES, 3) + GENERATE_ENUM(VOL_PHASES, 4) + GENERATE_ENUM(MIP_VOL_PHASES, 5) + GENERATE_ENUM(MIP_ANISO_PHASES, 6) + GENERATE_ENUM(VOL_ANISO_PHASES, 7) + GENERATE_ENUM(ANISO_2_1_PHASES, 8) + GENERATE_ENUM(ANISO_4_1_PHASES, 9) + GENERATE_ENUM(ANISO_6_1_PHASES, 10) + GENERATE_ENUM(ANISO_8_1_PHASES, 11) + GENERATE_ENUM(ANISO_10_1_PHASES, 12) + GENERATE_ENUM(ANISO_12_1_PHASES, 13) + GENERATE_ENUM(ANISO_14_1_PHASES, 14) + GENERATE_ENUM(ANISO_16_1_PHASES, 15) + GENERATE_ENUM(MIP_VOL_ANISO_PHASES, 16) + GENERATE_ENUM(ALIGN_2_PHASES, 17) + GENERATE_ENUM(ALIGN_4_PHASES, 18) + GENERATE_ENUM(TPC_BUSY, 19) + GENERATE_ENUM(TPC_STALLED, 20) + GENERATE_ENUM(TPC_STARVED, 21) + GENERATE_ENUM(TPC_WORKING, 22) + GENERATE_ENUM(TPC_WALKER_BUSY, 23) + GENERATE_ENUM(TPC_WALKER_STALLED, 24) + GENERATE_ENUM(TPC_WALKER_WORKING, 25) + GENERATE_ENUM(TPC_ALIGNER_BUSY, 26) + GENERATE_ENUM(TPC_ALIGNER_STALLED, 27) + GENERATE_ENUM(TPC_ALIGNER_STALLED_BY_BLEND, 28) + GENERATE_ENUM(TPC_ALIGNER_STALLED_BY_CACHE, 29) + GENERATE_ENUM(TPC_ALIGNER_WORKING, 30) + GENERATE_ENUM(TPC_BLEND_BUSY, 31) + GENERATE_ENUM(TPC_BLEND_SYNC, 32) + GENERATE_ENUM(TPC_BLEND_STARVED, 33) + GENERATE_ENUM(TPC_BLEND_WORKING, 34) + GENERATE_ENUM(OPCODE_0x00, 35) + GENERATE_ENUM(OPCODE_0x01, 36) + GENERATE_ENUM(OPCODE_0x04, 37) + GENERATE_ENUM(OPCODE_0x10, 38) + GENERATE_ENUM(OPCODE_0x11, 39) + GENERATE_ENUM(OPCODE_0x12, 40) + GENERATE_ENUM(OPCODE_0x13, 41) + GENERATE_ENUM(OPCODE_0x18, 42) + GENERATE_ENUM(OPCODE_0x19, 43) + GENERATE_ENUM(OPCODE_0x1A, 44) + GENERATE_ENUM(OPCODE_OTHER, 45) + GENERATE_ENUM(IN_FIFO_0_EMPTY, 56) + GENERATE_ENUM(IN_FIFO_0_LT_HALF_FULL, 57) + GENERATE_ENUM(IN_FIFO_0_HALF_FULL, 58) + GENERATE_ENUM(IN_FIFO_0_FULL, 59) + GENERATE_ENUM(IN_FIFO_TPC_EMPTY, 72) + GENERATE_ENUM(IN_FIFO_TPC_LT_HALF_FULL, 73) + GENERATE_ENUM(IN_FIFO_TPC_HALF_FULL, 74) + GENERATE_ENUM(IN_FIFO_TPC_FULL, 75) + GENERATE_ENUM(TPC_TC_XFC, 76) + GENERATE_ENUM(TPC_TC_STATE, 77) + GENERATE_ENUM(TC_STALL, 78) + GENERATE_ENUM(QUAD0_TAPS, 79) + GENERATE_ENUM(QUADS, 83) + GENERATE_ENUM(TCA_SYNC_STALL, 84) + GENERATE_ENUM(TAG_STALL, 85) + GENERATE_ENUM(TCB_SYNC_STALL, 88) + GENERATE_ENUM(TCA_VALID, 89) + GENERATE_ENUM(PROBES_VALID, 90) + GENERATE_ENUM(MISS_STALL, 91) + GENERATE_ENUM(FETCH_FIFO_STALL, 92) + GENERATE_ENUM(TCO_STALL, 93) + GENERATE_ENUM(ANY_STALL, 94) + GENERATE_ENUM(TAG_MISSES, 95) + GENERATE_ENUM(TAG_HITS, 96) + GENERATE_ENUM(SUB_TAG_MISSES, 97) + GENERATE_ENUM(SET0_INVALIDATES, 98) + GENERATE_ENUM(SET1_INVALIDATES, 99) + GENERATE_ENUM(SET2_INVALIDATES, 100) + GENERATE_ENUM(SET3_INVALIDATES, 101) + GENERATE_ENUM(SET0_TAG_MISSES, 102) + GENERATE_ENUM(SET1_TAG_MISSES, 103) + GENERATE_ENUM(SET2_TAG_MISSES, 104) + GENERATE_ENUM(SET3_TAG_MISSES, 105) + GENERATE_ENUM(SET0_TAG_HITS, 106) + GENERATE_ENUM(SET1_TAG_HITS, 107) + GENERATE_ENUM(SET2_TAG_HITS, 108) + GENERATE_ENUM(SET3_TAG_HITS, 109) + GENERATE_ENUM(SET0_SUB_TAG_MISSES, 110) + GENERATE_ENUM(SET1_SUB_TAG_MISSES, 111) + GENERATE_ENUM(SET2_SUB_TAG_MISSES, 112) + GENERATE_ENUM(SET3_SUB_TAG_MISSES, 113) + GENERATE_ENUM(SET0_EVICT1, 114) + GENERATE_ENUM(SET0_EVICT2, 115) + GENERATE_ENUM(SET0_EVICT3, 116) + GENERATE_ENUM(SET0_EVICT4, 117) + GENERATE_ENUM(SET0_EVICT5, 118) + GENERATE_ENUM(SET0_EVICT6, 119) + GENERATE_ENUM(SET0_EVICT7, 120) + GENERATE_ENUM(SET0_EVICT8, 121) + GENERATE_ENUM(SET1_EVICT1, 130) + GENERATE_ENUM(SET1_EVICT2, 131) + GENERATE_ENUM(SET1_EVICT3, 132) + GENERATE_ENUM(SET1_EVICT4, 133) + GENERATE_ENUM(SET1_EVICT5, 134) + GENERATE_ENUM(SET1_EVICT6, 135) + GENERATE_ENUM(SET1_EVICT7, 136) + GENERATE_ENUM(SET1_EVICT8, 137) + GENERATE_ENUM(SET2_EVICT1, 146) + GENERATE_ENUM(SET2_EVICT2, 147) + GENERATE_ENUM(SET2_EVICT3, 148) + GENERATE_ENUM(SET2_EVICT4, 149) + GENERATE_ENUM(SET2_EVICT5, 150) + GENERATE_ENUM(SET2_EVICT6, 151) + GENERATE_ENUM(SET2_EVICT7, 152) + GENERATE_ENUM(SET2_EVICT8, 153) + GENERATE_ENUM(SET3_EVICT1, 162) + GENERATE_ENUM(SET3_EVICT2, 163) + GENERATE_ENUM(SET3_EVICT3, 164) + GENERATE_ENUM(SET3_EVICT4, 165) + GENERATE_ENUM(SET3_EVICT5, 166) + GENERATE_ENUM(SET3_EVICT6, 167) + GENERATE_ENUM(SET3_EVICT7, 168) + GENERATE_ENUM(SET3_EVICT8, 169) + GENERATE_ENUM(FF_EMPTY, 178) + GENERATE_ENUM(FF_LT_HALF_FULL, 179) + GENERATE_ENUM(FF_HALF_FULL, 180) + GENERATE_ENUM(FF_FULL, 181) + GENERATE_ENUM(FF_XFC, 182) + GENERATE_ENUM(FF_STALLED, 183) + GENERATE_ENUM(FG_MASKS, 184) + GENERATE_ENUM(FG_LEFT_MASKS, 185) + GENERATE_ENUM(FG_LEFT_MASK_STALLED, 186) + GENERATE_ENUM(FG_LEFT_NOT_DONE_STALL, 187) + GENERATE_ENUM(FG_LEFT_FG_STALL, 188) + GENERATE_ENUM(FG_LEFT_SECTORS, 189) + GENERATE_ENUM(FG0_REQUESTS, 195) + GENERATE_ENUM(FG0_STALLED, 196) + GENERATE_ENUM(MEM_REQ512, 199) + GENERATE_ENUM(MEM_REQ_SENT, 200) + GENERATE_ENUM(MEM_LOCAL_READ_REQ, 202) + GENERATE_ENUM(TC0_MH_STALLED, 203) +END_ENUMTYPE(TCF_PERFCOUNT_SELECT) + +START_ENUMTYPE(SQ_PERFCNT_SELECT) + GENERATE_ENUM(SQ_PIXEL_VECTORS_SUB, 0) + GENERATE_ENUM(SQ_VERTEX_VECTORS_SUB, 1) + GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD0, 2) + GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD0, 3) + GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD0, 4) + GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD0, 5) + GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD1, 6) + GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD1, 7) + GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD1, 8) + GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD1, 9) + GENERATE_ENUM(SQ_EXPORT_CYCLES, 10) + GENERATE_ENUM(SQ_ALU_CST_WRITTEN, 11) + GENERATE_ENUM(SQ_TEX_CST_WRITTEN, 12) + GENERATE_ENUM(SQ_ALU_CST_STALL, 13) + GENERATE_ENUM(SQ_ALU_TEX_STALL, 14) + GENERATE_ENUM(SQ_INST_WRITTEN, 15) + GENERATE_ENUM(SQ_BOOLEAN_WRITTEN, 16) + GENERATE_ENUM(SQ_LOOPS_WRITTEN, 17) + GENERATE_ENUM(SQ_PIXEL_SWAP_IN, 18) + GENERATE_ENUM(SQ_PIXEL_SWAP_OUT, 19) + GENERATE_ENUM(SQ_VERTEX_SWAP_IN, 20) + GENERATE_ENUM(SQ_VERTEX_SWAP_OUT, 21) + GENERATE_ENUM(SQ_ALU_VTX_INST_ISSUED, 22) + GENERATE_ENUM(SQ_TEX_VTX_INST_ISSUED, 23) + GENERATE_ENUM(SQ_VC_VTX_INST_ISSUED, 24) + GENERATE_ENUM(SQ_CF_VTX_INST_ISSUED, 25) + GENERATE_ENUM(SQ_ALU_PIX_INST_ISSUED, 26) + GENERATE_ENUM(SQ_TEX_PIX_INST_ISSUED, 27) + GENERATE_ENUM(SQ_VC_PIX_INST_ISSUED, 28) + GENERATE_ENUM(SQ_CF_PIX_INST_ISSUED, 29) + GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD0, 30) + GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD0, 31) + GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD1, 32) + GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD1, 33) + GENERATE_ENUM(SQ_ALU_NOPS, 34) + GENERATE_ENUM(SQ_PRED_SKIP, 35) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD0_VTX, 36) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD1_VTX, 37) + GENERATE_ENUM(SQ_SYNC_TEX_STALL_VTX, 38) + GENERATE_ENUM(SQ_SYNC_VC_STALL_VTX, 39) + GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD0, 40) + GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD0, 41) + GENERATE_ENUM(SQ_GPR_STALL_VTX, 42) + GENERATE_ENUM(SQ_GPR_STALL_PIX, 43) + GENERATE_ENUM(SQ_VTX_RS_STALL, 44) + GENERATE_ENUM(SQ_PIX_RS_STALL, 45) + GENERATE_ENUM(SQ_SX_PC_FULL, 46) + GENERATE_ENUM(SQ_SX_EXP_BUFF_FULL, 47) + GENERATE_ENUM(SQ_SX_POS_BUFF_FULL, 48) + GENERATE_ENUM(SQ_INTERP_QUADS, 49) + GENERATE_ENUM(SQ_INTERP_ACTIVE, 50) + GENERATE_ENUM(SQ_IN_PIXEL_STALL, 51) + GENERATE_ENUM(SQ_IN_VTX_STALL, 52) + GENERATE_ENUM(SQ_VTX_CNT, 53) + GENERATE_ENUM(SQ_VTX_VECTOR2, 54) + GENERATE_ENUM(SQ_VTX_VECTOR3, 55) + GENERATE_ENUM(SQ_VTX_VECTOR4, 56) + GENERATE_ENUM(SQ_PIXEL_VECTOR1, 57) + GENERATE_ENUM(SQ_PIXEL_VECTOR23, 58) + GENERATE_ENUM(SQ_PIXEL_VECTOR4, 59) + GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD1, 60) + GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD1, 61) + GENERATE_ENUM(SQ_SX_MEM_EXP_FULL, 62) + GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD2, 63) + GENERATE_ENUM(SQ_ALU1_ACTIVE_VTX_SIMD2, 64) + GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD2, 65) + GENERATE_ENUM(SQ_ALU1_ACTIVE_PIX_SIMD2, 66) + GENERATE_ENUM(SQ_ALU0_ACTIVE_VTX_SIMD3, 67) + GENERATE_ENUM(SQ_PERFCOUNT_VTX_QUAL_TP_DONE, 68) + GENERATE_ENUM(SQ_ALU0_ACTIVE_PIX_SIMD3, 69) + GENERATE_ENUM(SQ_PERFCOUNT_PIX_QUAL_TP_DONE, 70) + GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD2, 71) + GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD2, 72) + GENERATE_ENUM(SQ_ALU0_FIFO_EMPTY_SIMD3, 73) + GENERATE_ENUM(SQ_ALU1_FIFO_EMPTY_SIMD3, 74) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD2_VTX, 75) + GENERATE_ENUM(SQ_PERFCOUNT_VTX_POP_THREAD, 76) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD0_PIX, 77) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD1_PIX, 78) + GENERATE_ENUM(SQ_SYNC_ALU_STALL_SIMD2_PIX, 79) + GENERATE_ENUM(SQ_PERFCOUNT_PIX_POP_THREAD, 80) + GENERATE_ENUM(SQ_SYNC_TEX_STALL_PIX, 81) + GENERATE_ENUM(SQ_SYNC_VC_STALL_PIX, 82) + GENERATE_ENUM(SQ_CONSTANTS_USED_SIMD2, 83) + GENERATE_ENUM(SQ_CONSTANTS_SENT_SP_SIMD2, 84) + GENERATE_ENUM(SQ_PERFCOUNT_VTX_DEALLOC_ACK, 85) + GENERATE_ENUM(SQ_PERFCOUNT_PIX_DEALLOC_ACK, 86) + GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD0, 87) + GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD0, 88) + GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD1, 89) + GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD1, 90) + GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD2, 91) + GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD2, 92) + GENERATE_ENUM(SQ_ALU0_FIFO_FULL_SIMD3, 93) + GENERATE_ENUM(SQ_ALU1_FIFO_FULL_SIMD3, 94) + GENERATE_ENUM(VC_PERF_STATIC, 95) + GENERATE_ENUM(VC_PERF_STALLED, 96) + GENERATE_ENUM(VC_PERF_STARVED, 97) + GENERATE_ENUM(VC_PERF_SEND, 98) + GENERATE_ENUM(VC_PERF_ACTUAL_STARVED, 99) + GENERATE_ENUM(PIXEL_THREAD_0_ACTIVE, 100) + GENERATE_ENUM(VERTEX_THREAD_0_ACTIVE, 101) + GENERATE_ENUM(PIXEL_THREAD_0_NUMBER, 102) + GENERATE_ENUM(VERTEX_THREAD_0_NUMBER, 103) + GENERATE_ENUM(VERTEX_EVENT_NUMBER, 104) + GENERATE_ENUM(PIXEL_EVENT_NUMBER, 105) + GENERATE_ENUM(PTRBUFF_EF_PUSH, 106) + GENERATE_ENUM(PTRBUFF_EF_POP_EVENT, 107) + GENERATE_ENUM(PTRBUFF_EF_POP_NEW_VTX, 108) + GENERATE_ENUM(PTRBUFF_EF_POP_DEALLOC, 109) + GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR, 110) + GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR_X, 111) + GENERATE_ENUM(PTRBUFF_EF_POP_PVECTOR_VNZ, 112) + GENERATE_ENUM(PTRBUFF_PB_DEALLOC, 113) + GENERATE_ENUM(PTRBUFF_PI_STATE_PPB_POP, 114) + GENERATE_ENUM(PTRBUFF_PI_RTR, 115) + GENERATE_ENUM(PTRBUFF_PI_READ_EN, 116) + GENERATE_ENUM(PTRBUFF_PI_BUFF_SWAP, 117) + GENERATE_ENUM(PTRBUFF_SQ_FREE_BUFF, 118) + GENERATE_ENUM(PTRBUFF_SQ_DEC, 119) + GENERATE_ENUM(PTRBUFF_SC_VALID_CNTL_EVENT, 120) + GENERATE_ENUM(PTRBUFF_SC_VALID_IJ_XFER, 121) + GENERATE_ENUM(PTRBUFF_SC_NEW_VECTOR_1_Q, 122) + GENERATE_ENUM(PTRBUFF_QUAL_NEW_VECTOR, 123) + GENERATE_ENUM(PTRBUFF_QUAL_EVENT, 124) + GENERATE_ENUM(PTRBUFF_END_BUFFER, 125) + GENERATE_ENUM(PTRBUFF_FILL_QUAD, 126) + GENERATE_ENUM(VERTS_WRITTEN_SPI, 127) + GENERATE_ENUM(TP_FETCH_INSTR_EXEC, 128) + GENERATE_ENUM(TP_FETCH_INSTR_REQ, 129) + GENERATE_ENUM(TP_DATA_RETURN, 130) + GENERATE_ENUM(SPI_WRITE_CYCLES_SP, 131) + GENERATE_ENUM(SPI_WRITES_SP, 132) + GENERATE_ENUM(SP_ALU_INSTR_EXEC, 133) + GENERATE_ENUM(SP_CONST_ADDR_TO_SQ, 134) + GENERATE_ENUM(SP_PRED_KILLS_TO_SQ, 135) + GENERATE_ENUM(SP_EXPORT_CYCLES_TO_SX, 136) + GENERATE_ENUM(SP_EXPORTS_TO_SX, 137) + GENERATE_ENUM(SQ_CYCLES_ELAPSED, 138) + GENERATE_ENUM(SQ_TCFS_OPT_ALLOC_EXEC, 139) + GENERATE_ENUM(SQ_TCFS_NO_OPT_ALLOC, 140) + GENERATE_ENUM(SQ_ALU0_NO_OPT_ALLOC, 141) + GENERATE_ENUM(SQ_ALU1_NO_OPT_ALLOC, 142) + GENERATE_ENUM(SQ_TCFS_ARB_XFC_CNT, 143) + GENERATE_ENUM(SQ_ALU0_ARB_XFC_CNT, 144) + GENERATE_ENUM(SQ_ALU1_ARB_XFC_CNT, 145) + GENERATE_ENUM(SQ_TCFS_CFS_UPDATE_CNT, 146) + GENERATE_ENUM(SQ_ALU0_CFS_UPDATE_CNT, 147) + GENERATE_ENUM(SQ_ALU1_CFS_UPDATE_CNT, 148) + GENERATE_ENUM(SQ_VTX_PUSH_THREAD_CNT, 149) + GENERATE_ENUM(SQ_VTX_POP_THREAD_CNT, 150) + GENERATE_ENUM(SQ_PIX_PUSH_THREAD_CNT, 151) + GENERATE_ENUM(SQ_PIX_POP_THREAD_CNT, 152) + GENERATE_ENUM(SQ_PIX_TOTAL, 153) + GENERATE_ENUM(SQ_PIX_KILLED, 154) +END_ENUMTYPE(SQ_PERFCNT_SELECT) + +START_ENUMTYPE(SX_PERFCNT_SELECT) + GENERATE_ENUM(SX_EXPORT_VECTORS, 0) + GENERATE_ENUM(SX_DUMMY_QUADS, 1) + GENERATE_ENUM(SX_ALPHA_FAIL, 2) + GENERATE_ENUM(SX_RB_QUAD_BUSY, 3) + GENERATE_ENUM(SX_RB_COLOR_BUSY, 4) + GENERATE_ENUM(SX_RB_QUAD_STALL, 5) + GENERATE_ENUM(SX_RB_COLOR_STALL, 6) +END_ENUMTYPE(SX_PERFCNT_SELECT) + +START_ENUMTYPE(Abs_modifier) + GENERATE_ENUM(NO_ABS_MOD, 0) + GENERATE_ENUM(ABS_MOD, 1) +END_ENUMTYPE(Abs_modifier) + +START_ENUMTYPE(Exporting) + GENERATE_ENUM(NOT_EXPORTING, 0) + GENERATE_ENUM(EXPORTING, 1) +END_ENUMTYPE(Exporting) + +START_ENUMTYPE(ScalarOpcode) + GENERATE_ENUM(ADDs, 0) + GENERATE_ENUM(ADD_PREVs, 1) + GENERATE_ENUM(MULs, 2) + GENERATE_ENUM(MUL_PREVs, 3) + GENERATE_ENUM(MUL_PREV2s, 4) + GENERATE_ENUM(MAXs, 5) + GENERATE_ENUM(MINs, 6) + GENERATE_ENUM(SETEs, 7) + GENERATE_ENUM(SETGTs, 8) + GENERATE_ENUM(SETGTEs, 9) + GENERATE_ENUM(SETNEs, 10) + GENERATE_ENUM(FRACs, 11) + GENERATE_ENUM(TRUNCs, 12) + GENERATE_ENUM(FLOORs, 13) + GENERATE_ENUM(EXP_IEEE, 14) + GENERATE_ENUM(LOG_CLAMP, 15) + GENERATE_ENUM(LOG_IEEE, 16) + GENERATE_ENUM(RECIP_CLAMP, 17) + GENERATE_ENUM(RECIP_FF, 18) + GENERATE_ENUM(RECIP_IEEE, 19) + GENERATE_ENUM(RECIPSQ_CLAMP, 20) + GENERATE_ENUM(RECIPSQ_FF, 21) + GENERATE_ENUM(RECIPSQ_IEEE, 22) + GENERATE_ENUM(MOVAs, 23) + GENERATE_ENUM(MOVA_FLOORs, 24) + GENERATE_ENUM(SUBs, 25) + GENERATE_ENUM(SUB_PREVs, 26) + GENERATE_ENUM(PRED_SETEs, 27) + GENERATE_ENUM(PRED_SETNEs, 28) + GENERATE_ENUM(PRED_SETGTs, 29) + GENERATE_ENUM(PRED_SETGTEs, 30) + GENERATE_ENUM(PRED_SET_INVs, 31) + GENERATE_ENUM(PRED_SET_POPs, 32) + GENERATE_ENUM(PRED_SET_CLRs, 33) + GENERATE_ENUM(PRED_SET_RESTOREs, 34) + GENERATE_ENUM(KILLEs, 35) + GENERATE_ENUM(KILLGTs, 36) + GENERATE_ENUM(KILLGTEs, 37) + GENERATE_ENUM(KILLNEs, 38) + GENERATE_ENUM(KILLONEs, 39) + GENERATE_ENUM(SQRT_IEEE, 40) + GENERATE_ENUM(MUL_CONST_0, 42) + GENERATE_ENUM(MUL_CONST_1, 43) + GENERATE_ENUM(ADD_CONST_0, 44) + GENERATE_ENUM(ADD_CONST_1, 45) + GENERATE_ENUM(SUB_CONST_0, 46) + GENERATE_ENUM(SUB_CONST_1, 47) + GENERATE_ENUM(SIN, 48) + GENERATE_ENUM(COS, 49) + GENERATE_ENUM(RETAIN_PREV, 50) +END_ENUMTYPE(ScalarOpcode) + +START_ENUMTYPE(SwizzleType) + GENERATE_ENUM(NO_SWIZZLE, 0) + GENERATE_ENUM(SHIFT_RIGHT_1, 1) + GENERATE_ENUM(SHIFT_RIGHT_2, 2) + GENERATE_ENUM(SHIFT_RIGHT_3, 3) +END_ENUMTYPE(SwizzleType) + +START_ENUMTYPE(InputModifier) + GENERATE_ENUM(NIL, 0) + GENERATE_ENUM(NEGATE, 1) +END_ENUMTYPE(InputModifier) + +START_ENUMTYPE(PredicateSelect) + GENERATE_ENUM(NO_PREDICATION, 0) + GENERATE_ENUM(PREDICATE_QUAD, 1) + GENERATE_ENUM(PREDICATED_2, 2) + GENERATE_ENUM(PREDICATED_3, 3) +END_ENUMTYPE(PredicateSelect) + +START_ENUMTYPE(OperandSelect1) + GENERATE_ENUM(ABSOLUTE_REG, 0) + GENERATE_ENUM(RELATIVE_REG, 1) +END_ENUMTYPE(OperandSelect1) + +START_ENUMTYPE(VectorOpcode) + GENERATE_ENUM(ADDv, 0) + GENERATE_ENUM(MULv, 1) + GENERATE_ENUM(MAXv, 2) + GENERATE_ENUM(MINv, 3) + GENERATE_ENUM(SETEv, 4) + GENERATE_ENUM(SETGTv, 5) + GENERATE_ENUM(SETGTEv, 6) + GENERATE_ENUM(SETNEv, 7) + GENERATE_ENUM(FRACv, 8) + GENERATE_ENUM(TRUNCv, 9) + GENERATE_ENUM(FLOORv, 10) + GENERATE_ENUM(MULADDv, 11) + GENERATE_ENUM(CNDEv, 12) + GENERATE_ENUM(CNDGTEv, 13) + GENERATE_ENUM(CNDGTv, 14) + GENERATE_ENUM(DOT4v, 15) + GENERATE_ENUM(DOT3v, 16) + GENERATE_ENUM(DOT2ADDv, 17) + GENERATE_ENUM(CUBEv, 18) + GENERATE_ENUM(MAX4v, 19) + GENERATE_ENUM(PRED_SETE_PUSHv, 20) + GENERATE_ENUM(PRED_SETNE_PUSHv, 21) + GENERATE_ENUM(PRED_SETGT_PUSHv, 22) + GENERATE_ENUM(PRED_SETGTE_PUSHv, 23) + GENERATE_ENUM(KILLEv, 24) + GENERATE_ENUM(KILLGTv, 25) + GENERATE_ENUM(KILLGTEv, 26) + GENERATE_ENUM(KILLNEv, 27) + GENERATE_ENUM(DSTv, 28) + GENERATE_ENUM(MOVAv, 29) +END_ENUMTYPE(VectorOpcode) + +START_ENUMTYPE(OperandSelect0) + GENERATE_ENUM(CONSTANT, 0) + GENERATE_ENUM(NON_CONSTANT, 1) +END_ENUMTYPE(OperandSelect0) + +START_ENUMTYPE(Ressource_type) + GENERATE_ENUM(ALU, 0) + GENERATE_ENUM(TEXTURE, 1) +END_ENUMTYPE(Ressource_type) + +START_ENUMTYPE(Instruction_serial) + GENERATE_ENUM(NOT_SERIAL, 0) + GENERATE_ENUM(SERIAL, 1) +END_ENUMTYPE(Instruction_serial) + +START_ENUMTYPE(VC_type) + GENERATE_ENUM(ALU_TP_REQUEST, 0) + GENERATE_ENUM(VC_REQUEST, 1) +END_ENUMTYPE(VC_type) + +START_ENUMTYPE(Addressing) + GENERATE_ENUM(RELATIVE_ADDR, 0) + GENERATE_ENUM(ABSOLUTE_ADDR, 1) +END_ENUMTYPE(Addressing) + +START_ENUMTYPE(CFOpcode) + GENERATE_ENUM(NOP, 0) + GENERATE_ENUM(EXECUTE, 1) + GENERATE_ENUM(EXECUTE_END, 2) + GENERATE_ENUM(COND_EXECUTE, 3) + GENERATE_ENUM(COND_EXECUTE_END, 4) + GENERATE_ENUM(COND_PRED_EXECUTE, 5) + GENERATE_ENUM(COND_PRED_EXECUTE_END, 6) + GENERATE_ENUM(LOOP_START, 7) + GENERATE_ENUM(LOOP_END, 8) + GENERATE_ENUM(COND_CALL, 9) + GENERATE_ENUM(RETURN, 10) + GENERATE_ENUM(COND_JMP, 11) + GENERATE_ENUM(ALLOCATE, 12) + GENERATE_ENUM(COND_EXECUTE_PRED_CLEAN, 13) + GENERATE_ENUM(COND_EXECUTE_PRED_CLEAN_END, 14) + GENERATE_ENUM(MARK_VS_FETCH_DONE, 15) +END_ENUMTYPE(CFOpcode) + +START_ENUMTYPE(Allocation_type) + GENERATE_ENUM(SQ_NO_ALLOC, 0) + GENERATE_ENUM(SQ_POSITION, 1) + GENERATE_ENUM(SQ_PARAMETER_PIXEL, 2) + GENERATE_ENUM(SQ_MEMORY, 3) +END_ENUMTYPE(Allocation_type) + +START_ENUMTYPE(TexInstOpcode) + GENERATE_ENUM(TEX_INST_FETCH, 1) + GENERATE_ENUM(TEX_INST_RESERVED_1, 2) + GENERATE_ENUM(TEX_INST_RESERVED_2, 3) + GENERATE_ENUM(TEX_INST_RESERVED_3, 4) + GENERATE_ENUM(TEX_INST_GET_BORDER_COLOR_FRAC, 16) + GENERATE_ENUM(TEX_INST_GET_COMP_TEX_LOD, 17) + GENERATE_ENUM(TEX_INST_GET_GRADIENTS, 18) + GENERATE_ENUM(TEX_INST_GET_WEIGHTS, 19) + GENERATE_ENUM(TEX_INST_SET_TEX_LOD, 24) + GENERATE_ENUM(TEX_INST_SET_GRADIENTS_H, 25) + GENERATE_ENUM(TEX_INST_SET_GRADIENTS_V, 26) + GENERATE_ENUM(TEX_INST_RESERVED_4, 27) +END_ENUMTYPE(TexInstOpcode) + +START_ENUMTYPE(Addressmode) + GENERATE_ENUM(LOGICAL, 0) + GENERATE_ENUM(LOOP_RELATIVE, 1) +END_ENUMTYPE(Addressmode) + +START_ENUMTYPE(TexCoordDenorm) + GENERATE_ENUM(TEX_COORD_NORMALIZED, 0) + GENERATE_ENUM(TEX_COORD_UNNORMALIZED, 1) +END_ENUMTYPE(TexCoordDenorm) + +START_ENUMTYPE(SrcSel) + GENERATE_ENUM(SRC_SEL_X, 0) + GENERATE_ENUM(SRC_SEL_Y, 1) + GENERATE_ENUM(SRC_SEL_Z, 2) + GENERATE_ENUM(SRC_SEL_W, 3) +END_ENUMTYPE(SrcSel) + +START_ENUMTYPE(DstSel) + GENERATE_ENUM(DST_SEL_X, 0) + GENERATE_ENUM(DST_SEL_Y, 1) + GENERATE_ENUM(DST_SEL_Z, 2) + GENERATE_ENUM(DST_SEL_W, 3) + GENERATE_ENUM(DST_SEL_0, 4) + GENERATE_ENUM(DST_SEL_1, 5) + GENERATE_ENUM(DST_SEL_RSVD, 6) + GENERATE_ENUM(DST_SEL_MASK, 7) +END_ENUMTYPE(DstSel) + +START_ENUMTYPE(MagFilter) + GENERATE_ENUM(MAG_FILTER_POINT, 0) + GENERATE_ENUM(MAG_FILTER_LINEAR, 1) + GENERATE_ENUM(MAG_FILTER_RESERVED_0, 2) + GENERATE_ENUM(MAG_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(MagFilter) + +START_ENUMTYPE(MinFilter) + GENERATE_ENUM(MIN_FILTER_POINT, 0) + GENERATE_ENUM(MIN_FILTER_LINEAR, 1) + GENERATE_ENUM(MIN_FILTER_RESERVED_0, 2) + GENERATE_ENUM(MIN_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(MinFilter) + +START_ENUMTYPE(MipFilter) + GENERATE_ENUM(MIP_FILTER_POINT, 0) + GENERATE_ENUM(MIP_FILTER_LINEAR, 1) + GENERATE_ENUM(MIP_FILTER_BASEMAP, 2) + GENERATE_ENUM(MIP_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(MipFilter) + +START_ENUMTYPE(AnisoFilter) + GENERATE_ENUM(ANISO_FILTER_DISABLED, 0) + GENERATE_ENUM(ANISO_FILTER_MAX_1_1, 1) + GENERATE_ENUM(ANISO_FILTER_MAX_2_1, 2) + GENERATE_ENUM(ANISO_FILTER_MAX_4_1, 3) + GENERATE_ENUM(ANISO_FILTER_MAX_8_1, 4) + GENERATE_ENUM(ANISO_FILTER_MAX_16_1, 5) + GENERATE_ENUM(ANISO_FILTER_USE_FETCH_CONST, 7) +END_ENUMTYPE(AnisoFilter) + +START_ENUMTYPE(ArbitraryFilter) + GENERATE_ENUM(ARBITRARY_FILTER_2X4_SYM, 0) + GENERATE_ENUM(ARBITRARY_FILTER_2X4_ASYM, 1) + GENERATE_ENUM(ARBITRARY_FILTER_4X2_SYM, 2) + GENERATE_ENUM(ARBITRARY_FILTER_4X2_ASYM, 3) + GENERATE_ENUM(ARBITRARY_FILTER_4X4_SYM, 4) + GENERATE_ENUM(ARBITRARY_FILTER_4X4_ASYM, 5) + GENERATE_ENUM(ARBITRARY_FILTER_USE_FETCH_CONST, 7) +END_ENUMTYPE(ArbitraryFilter) + +START_ENUMTYPE(VolMagFilter) + GENERATE_ENUM(VOL_MAG_FILTER_POINT, 0) + GENERATE_ENUM(VOL_MAG_FILTER_LINEAR, 1) + GENERATE_ENUM(VOL_MAG_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(VolMagFilter) + +START_ENUMTYPE(VolMinFilter) + GENERATE_ENUM(VOL_MIN_FILTER_POINT, 0) + GENERATE_ENUM(VOL_MIN_FILTER_LINEAR, 1) + GENERATE_ENUM(VOL_MIN_FILTER_USE_FETCH_CONST, 3) +END_ENUMTYPE(VolMinFilter) + +START_ENUMTYPE(PredSelect) + GENERATE_ENUM(NOT_PREDICATED, 0) + GENERATE_ENUM(PREDICATED, 1) +END_ENUMTYPE(PredSelect) + +START_ENUMTYPE(SampleLocation) + GENERATE_ENUM(SAMPLE_CENTROID, 0) + GENERATE_ENUM(SAMPLE_CENTER, 1) +END_ENUMTYPE(SampleLocation) + +START_ENUMTYPE(VertexMode) + GENERATE_ENUM(POSITION_1_VECTOR, 0) + GENERATE_ENUM(POSITION_2_VECTORS_UNUSED, 1) + GENERATE_ENUM(POSITION_2_VECTORS_SPRITE, 2) + GENERATE_ENUM(POSITION_2_VECTORS_EDGE, 3) + GENERATE_ENUM(POSITION_2_VECTORS_KILL, 4) + GENERATE_ENUM(POSITION_2_VECTORS_SPRITE_KILL, 5) + GENERATE_ENUM(POSITION_2_VECTORS_EDGE_KILL, 6) + GENERATE_ENUM(MULTIPASS, 7) +END_ENUMTYPE(VertexMode) + +START_ENUMTYPE(Sample_Cntl) + GENERATE_ENUM(CENTROIDS_ONLY, 0) + GENERATE_ENUM(CENTERS_ONLY, 1) + GENERATE_ENUM(CENTROIDS_AND_CENTERS, 2) + GENERATE_ENUM(UNDEF, 3) +END_ENUMTYPE(Sample_Cntl) + +START_ENUMTYPE(MhPerfEncode) + GENERATE_ENUM(CP_R0_REQUESTS, 0) + GENERATE_ENUM(CP_R1_REQUESTS, 1) + GENERATE_ENUM(CP_R2_REQUESTS, 2) + GENERATE_ENUM(CP_R3_REQUESTS, 3) + GENERATE_ENUM(CP_R4_REQUESTS, 4) + GENERATE_ENUM(CP_TOTAL_READ_REQUESTS, 5) + GENERATE_ENUM(CP_TOTAL_WRITE_REQUESTS, 6) + GENERATE_ENUM(CP_TOTAL_REQUESTS, 7) + GENERATE_ENUM(CP_DATA_BYTES_WRITTEN, 8) + GENERATE_ENUM(CP_WRITE_CLEAN_RESPONSES, 9) + GENERATE_ENUM(CP_R0_READ_BURSTS_RECEIVED, 10) + GENERATE_ENUM(CP_R1_READ_BURSTS_RECEIVED, 11) + GENERATE_ENUM(CP_R2_READ_BURSTS_RECEIVED, 12) + GENERATE_ENUM(CP_R3_READ_BURSTS_RECEIVED, 13) + GENERATE_ENUM(CP_R4_READ_BURSTS_RECEIVED, 14) + GENERATE_ENUM(CP_TOTAL_READ_BURSTS_RECEIVED, 15) + GENERATE_ENUM(CP_R0_DATA_BEATS_READ, 16) + GENERATE_ENUM(CP_R1_DATA_BEATS_READ, 17) + GENERATE_ENUM(CP_R2_DATA_BEATS_READ, 18) + GENERATE_ENUM(CP_R3_DATA_BEATS_READ, 19) + GENERATE_ENUM(CP_R4_DATA_BEATS_READ, 20) + GENERATE_ENUM(CP_TOTAL_DATA_BEATS_READ, 21) + GENERATE_ENUM(VGT_R0_REQUESTS, 22) + GENERATE_ENUM(VGT_R1_REQUESTS, 23) + GENERATE_ENUM(VGT_TOTAL_REQUESTS, 24) + GENERATE_ENUM(VGT_R0_READ_BURSTS_RECEIVED, 25) + GENERATE_ENUM(VGT_R1_READ_BURSTS_RECEIVED, 26) + GENERATE_ENUM(VGT_TOTAL_READ_BURSTS_RECEIVED, 27) + GENERATE_ENUM(VGT_R0_DATA_BEATS_READ, 28) + GENERATE_ENUM(VGT_R1_DATA_BEATS_READ, 29) + GENERATE_ENUM(VGT_TOTAL_DATA_BEATS_READ, 30) + GENERATE_ENUM(TC_TOTAL_REQUESTS, 31) + GENERATE_ENUM(TC_ROQ_REQUESTS, 32) + GENERATE_ENUM(TC_INFO_SENT, 33) + GENERATE_ENUM(TC_READ_BURSTS_RECEIVED, 34) + GENERATE_ENUM(TC_DATA_BEATS_READ, 35) + GENERATE_ENUM(TCD_BURSTS_READ, 36) + GENERATE_ENUM(RB_REQUESTS, 37) + GENERATE_ENUM(RB_DATA_BYTES_WRITTEN, 38) + GENERATE_ENUM(RB_WRITE_CLEAN_RESPONSES, 39) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_0, 40) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_1, 41) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_2, 42) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_3, 43) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_4, 44) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_5, 45) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_6, 46) + GENERATE_ENUM(AXI_READ_REQUESTS_ID_7, 47) + GENERATE_ENUM(AXI_TOTAL_READ_REQUESTS, 48) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_0, 49) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_1, 50) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_2, 51) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_3, 52) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_4, 53) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_5, 54) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_6, 55) + GENERATE_ENUM(AXI_WRITE_REQUESTS_ID_7, 56) + GENERATE_ENUM(AXI_TOTAL_WRITE_REQUESTS, 57) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_0, 58) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_1, 59) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_2, 60) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_3, 61) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_4, 62) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_5, 63) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_6, 64) + GENERATE_ENUM(AXI_TOTAL_REQUESTS_ID_7, 65) + GENERATE_ENUM(AXI_TOTAL_REQUESTS, 66) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_0, 67) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_1, 68) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_2, 69) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_3, 70) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_4, 71) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_5, 72) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_6, 73) + GENERATE_ENUM(AXI_READ_CHANNEL_BURSTS_ID_7, 74) + GENERATE_ENUM(AXI_READ_CHANNEL_TOTAL_BURSTS, 75) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0, 76) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1, 77) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2, 78) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3, 79) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4, 80) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5, 81) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6, 82) + GENERATE_ENUM(AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7, 83) + GENERATE_ENUM(AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ, 84) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_0, 85) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_1, 86) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_2, 87) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_3, 88) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_4, 89) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_5, 90) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_6, 91) + GENERATE_ENUM(AXI_WRITE_CHANNEL_BURSTS_ID_7, 92) + GENERATE_ENUM(AXI_WRITE_CHANNEL_TOTAL_BURSTS, 93) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0, 94) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1, 95) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2, 96) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3, 97) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4, 98) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5, 99) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6, 100) + GENERATE_ENUM(AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7, 101) + GENERATE_ENUM(AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN, 102) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0, 103) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1, 104) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2, 105) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3, 106) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4, 107) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5, 108) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6, 109) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7, 110) + GENERATE_ENUM(AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES, 111) + GENERATE_ENUM(TOTAL_MMU_MISSES, 112) + GENERATE_ENUM(MMU_READ_MISSES, 113) + GENERATE_ENUM(MMU_WRITE_MISSES, 114) + GENERATE_ENUM(TOTAL_MMU_HITS, 115) + GENERATE_ENUM(MMU_READ_HITS, 116) + GENERATE_ENUM(MMU_WRITE_HITS, 117) + GENERATE_ENUM(SPLIT_MODE_TC_HITS, 118) + GENERATE_ENUM(SPLIT_MODE_TC_MISSES, 119) + GENERATE_ENUM(SPLIT_MODE_NON_TC_HITS, 120) + GENERATE_ENUM(SPLIT_MODE_NON_TC_MISSES, 121) + GENERATE_ENUM(STALL_AWAITING_TLB_MISS_FETCH, 122) + GENERATE_ENUM(MMU_TLB_MISS_READ_BURSTS_RECEIVED, 123) + GENERATE_ENUM(MMU_TLB_MISS_DATA_BEATS_READ, 124) + GENERATE_ENUM(CP_CYCLES_HELD_OFF, 125) + GENERATE_ENUM(VGT_CYCLES_HELD_OFF, 126) + GENERATE_ENUM(TC_CYCLES_HELD_OFF, 127) + GENERATE_ENUM(TC_ROQ_CYCLES_HELD_OFF, 128) + GENERATE_ENUM(TC_CYCLES_HELD_OFF_TCD_FULL, 129) + GENERATE_ENUM(RB_CYCLES_HELD_OFF, 130) + GENERATE_ENUM(TOTAL_CYCLES_ANY_CLNT_HELD_OFF, 131) + GENERATE_ENUM(TLB_MISS_CYCLES_HELD_OFF, 132) + GENERATE_ENUM(AXI_READ_REQUEST_HELD_OFF, 133) + GENERATE_ENUM(AXI_WRITE_REQUEST_HELD_OFF, 134) + GENERATE_ENUM(AXI_REQUEST_HELD_OFF, 135) + GENERATE_ENUM(AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT, 136) + GENERATE_ENUM(AXI_WRITE_DATA_HELD_OFF, 137) + GENERATE_ENUM(CP_SAME_PAGE_BANK_REQUESTS, 138) + GENERATE_ENUM(VGT_SAME_PAGE_BANK_REQUESTS, 139) + GENERATE_ENUM(TC_SAME_PAGE_BANK_REQUESTS, 140) + GENERATE_ENUM(TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS, 141) + GENERATE_ENUM(RB_SAME_PAGE_BANK_REQUESTS, 142) + GENERATE_ENUM(TOTAL_SAME_PAGE_BANK_REQUESTS, 143) + GENERATE_ENUM(CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 144) + GENERATE_ENUM(VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 145) + GENERATE_ENUM(TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 146) + GENERATE_ENUM(RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT, 147) + GENERATE_ENUM(TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT, 148) + GENERATE_ENUM(TOTAL_MH_READ_REQUESTS, 149) + GENERATE_ENUM(TOTAL_MH_WRITE_REQUESTS, 150) + GENERATE_ENUM(TOTAL_MH_REQUESTS, 151) + GENERATE_ENUM(MH_BUSY, 152) + GENERATE_ENUM(CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 153) + GENERATE_ENUM(VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 154) + GENERATE_ENUM(TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 155) + GENERATE_ENUM(RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE, 156) + GENERATE_ENUM(TC_ROQ_N_VALID_ENTRIES, 157) + GENERATE_ENUM(ARQ_N_ENTRIES, 158) + GENERATE_ENUM(WDB_N_ENTRIES, 159) + GENERATE_ENUM(MH_READ_LATENCY_OUTST_REQ_SUM, 160) + GENERATE_ENUM(MC_READ_LATENCY_OUTST_REQ_SUM, 161) + GENERATE_ENUM(MC_TOTAL_READ_REQUESTS, 162) + GENERATE_ENUM(ELAPSED_CYCLES_MH_GATED_CLK, 163) + GENERATE_ENUM(ELAPSED_CLK_CYCLES, 164) + GENERATE_ENUM(CP_W_16B_REQUESTS, 165) + GENERATE_ENUM(CP_W_32B_REQUESTS, 166) + GENERATE_ENUM(TC_16B_REQUESTS, 167) + GENERATE_ENUM(TC_32B_REQUESTS, 168) + GENERATE_ENUM(PA_REQUESTS, 169) + GENERATE_ENUM(PA_DATA_BYTES_WRITTEN, 170) + GENERATE_ENUM(PA_WRITE_CLEAN_RESPONSES, 171) + GENERATE_ENUM(PA_CYCLES_HELD_OFF, 172) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_0, 173) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_1, 174) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_2, 175) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_3, 176) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_4, 177) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_5, 178) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_6, 179) + GENERATE_ENUM(AXI_READ_REQUEST_DATA_BEATS_ID_7, 180) + GENERATE_ENUM(AXI_TOTAL_READ_REQUEST_DATA_BEATS, 181) +END_ENUMTYPE(MhPerfEncode) + +START_ENUMTYPE(MmuClntBeh) + GENERATE_ENUM(BEH_NEVR, 0) + GENERATE_ENUM(BEH_TRAN_RNG, 1) + GENERATE_ENUM(BEH_TRAN_FLT, 2) +END_ENUMTYPE(MmuClntBeh) + +START_ENUMTYPE(RBBM_PERFCOUNT1_SEL) + GENERATE_ENUM(RBBM1_COUNT, 0) + GENERATE_ENUM(RBBM1_NRT_BUSY, 1) + GENERATE_ENUM(RBBM1_RB_BUSY, 2) + GENERATE_ENUM(RBBM1_SQ_CNTX0_BUSY, 3) + GENERATE_ENUM(RBBM1_SQ_CNTX17_BUSY, 4) + GENERATE_ENUM(RBBM1_VGT_BUSY, 5) + GENERATE_ENUM(RBBM1_VGT_NODMA_BUSY, 6) + GENERATE_ENUM(RBBM1_PA_BUSY, 7) + GENERATE_ENUM(RBBM1_SC_CNTX_BUSY, 8) + GENERATE_ENUM(RBBM1_TPC_BUSY, 9) + GENERATE_ENUM(RBBM1_TC_BUSY, 10) + GENERATE_ENUM(RBBM1_SX_BUSY, 11) + GENERATE_ENUM(RBBM1_CP_COHER_BUSY, 12) + GENERATE_ENUM(RBBM1_CP_NRT_BUSY, 13) + GENERATE_ENUM(RBBM1_GFX_IDLE_STALL, 14) + GENERATE_ENUM(RBBM1_INTERRUPT, 15) +END_ENUMTYPE(RBBM_PERFCOUNT1_SEL) + +START_ENUMTYPE(CP_PERFCOUNT_SEL) + GENERATE_ENUM(ALWAYS_COUNT, 0) + GENERATE_ENUM(TRANS_FIFO_FULL, 1) + GENERATE_ENUM(TRANS_FIFO_AF, 2) + GENERATE_ENUM(RCIU_PFPTRANS_WAIT, 3) + GENERATE_ENUM(Reserved_04, 4) + GENERATE_ENUM(Reserved_05, 5) + GENERATE_ENUM(RCIU_NRTTRANS_WAIT, 6) + GENERATE_ENUM(Reserved_07, 7) + GENERATE_ENUM(CSF_NRT_READ_WAIT, 8) + GENERATE_ENUM(CSF_I1_FIFO_FULL, 9) + GENERATE_ENUM(CSF_I2_FIFO_FULL, 10) + GENERATE_ENUM(CSF_ST_FIFO_FULL, 11) + GENERATE_ENUM(Reserved_12, 12) + GENERATE_ENUM(CSF_RING_ROQ_FULL, 13) + GENERATE_ENUM(CSF_I1_ROQ_FULL, 14) + GENERATE_ENUM(CSF_I2_ROQ_FULL, 15) + GENERATE_ENUM(CSF_ST_ROQ_FULL, 16) + GENERATE_ENUM(Reserved_17, 17) + GENERATE_ENUM(MIU_TAG_MEM_FULL, 18) + GENERATE_ENUM(MIU_WRITECLEAN, 19) + GENERATE_ENUM(Reserved_20, 20) + GENERATE_ENUM(Reserved_21, 21) + GENERATE_ENUM(MIU_NRT_WRITE_STALLED, 22) + GENERATE_ENUM(MIU_NRT_READ_STALLED, 23) + GENERATE_ENUM(ME_WRITE_CONFIRM_FIFO_FULL, 24) + GENERATE_ENUM(ME_VS_DEALLOC_FIFO_FULL, 25) + GENERATE_ENUM(ME_PS_DEALLOC_FIFO_FULL, 26) + GENERATE_ENUM(ME_REGS_VS_EVENT_FIFO_FULL, 27) + GENERATE_ENUM(ME_REGS_PS_EVENT_FIFO_FULL, 28) + GENERATE_ENUM(ME_REGS_CF_EVENT_FIFO_FULL, 29) + GENERATE_ENUM(ME_MICRO_RB_STARVED, 30) + GENERATE_ENUM(ME_MICRO_I1_STARVED, 31) + GENERATE_ENUM(ME_MICRO_I2_STARVED, 32) + GENERATE_ENUM(ME_MICRO_ST_STARVED, 33) + GENERATE_ENUM(Reserved_34, 34) + GENERATE_ENUM(Reserved_35, 35) + GENERATE_ENUM(Reserved_36, 36) + GENERATE_ENUM(Reserved_37, 37) + GENERATE_ENUM(Reserved_38, 38) + GENERATE_ENUM(Reserved_39, 39) + GENERATE_ENUM(RCIU_RBBM_DWORD_SENT, 40) + GENERATE_ENUM(ME_BUSY_CLOCKS, 41) + GENERATE_ENUM(ME_WAIT_CONTEXT_AVAIL, 42) + GENERATE_ENUM(PFP_TYPE0_PACKET, 43) + GENERATE_ENUM(PFP_TYPE3_PACKET, 44) + GENERATE_ENUM(CSF_RB_WPTR_NEQ_RPTR, 45) + GENERATE_ENUM(CSF_I1_SIZE_NEQ_ZERO, 46) + GENERATE_ENUM(CSF_I2_SIZE_NEQ_ZERO, 47) + GENERATE_ENUM(CSF_RBI1I2_FETCHING, 48) + GENERATE_ENUM(Reserved_49, 49) + GENERATE_ENUM(Reserved_50, 50) + GENERATE_ENUM(Reserved_51, 51) + GENERATE_ENUM(Reserved_52, 52) + GENERATE_ENUM(Reserved_53, 53) + GENERATE_ENUM(Reserved_54, 54) + GENERATE_ENUM(Reserved_55, 55) + GENERATE_ENUM(Reserved_56, 56) + GENERATE_ENUM(Reserved_57, 57) + GENERATE_ENUM(Reserved_58, 58) + GENERATE_ENUM(Reserved_59, 59) + GENERATE_ENUM(Reserved_60, 60) + GENERATE_ENUM(Reserved_61, 61) + GENERATE_ENUM(Reserved_62, 62) + GENERATE_ENUM(Reserved_63, 63) +END_ENUMTYPE(CP_PERFCOUNT_SEL) + +START_ENUMTYPE(ColorformatX) + GENERATE_ENUM(COLORX_4_4_4_4, 0) + GENERATE_ENUM(COLORX_1_5_5_5, 1) + GENERATE_ENUM(COLORX_5_6_5, 2) + GENERATE_ENUM(COLORX_8, 3) + GENERATE_ENUM(COLORX_8_8, 4) + GENERATE_ENUM(COLORX_8_8_8_8, 5) + GENERATE_ENUM(COLORX_S8_8_8_8, 6) + GENERATE_ENUM(COLORX_16_FLOAT, 7) + GENERATE_ENUM(COLORX_16_16_FLOAT, 8) + GENERATE_ENUM(COLORX_16_16_16_16_FLOAT, 9) + GENERATE_ENUM(COLORX_32_FLOAT, 10) + GENERATE_ENUM(COLORX_32_32_FLOAT, 11) + GENERATE_ENUM(COLORX_32_32_32_32_FLOAT, 12) + GENERATE_ENUM(COLORX_2_3_3, 13) + GENERATE_ENUM(COLORX_8_8_8, 14) +END_ENUMTYPE(ColorformatX) + +START_ENUMTYPE(DepthformatX) + GENERATE_ENUM(DEPTHX_16, 0) + GENERATE_ENUM(DEPTHX_24_8, 1) +END_ENUMTYPE(DepthformatX) + +START_ENUMTYPE(CompareFrag) + GENERATE_ENUM(FRAG_NEVER, 0) + GENERATE_ENUM(FRAG_LESS, 1) + GENERATE_ENUM(FRAG_EQUAL, 2) + GENERATE_ENUM(FRAG_LEQUAL, 3) + GENERATE_ENUM(FRAG_GREATER, 4) + GENERATE_ENUM(FRAG_NOTEQUAL, 5) + GENERATE_ENUM(FRAG_GEQUAL, 6) + GENERATE_ENUM(FRAG_ALWAYS, 7) +END_ENUMTYPE(CompareFrag) + +START_ENUMTYPE(CompareRef) + GENERATE_ENUM(REF_NEVER, 0) + GENERATE_ENUM(REF_LESS, 1) + GENERATE_ENUM(REF_EQUAL, 2) + GENERATE_ENUM(REF_LEQUAL, 3) + GENERATE_ENUM(REF_GREATER, 4) + GENERATE_ENUM(REF_NOTEQUAL, 5) + GENERATE_ENUM(REF_GEQUAL, 6) + GENERATE_ENUM(REF_ALWAYS, 7) +END_ENUMTYPE(CompareRef) + +START_ENUMTYPE(StencilOp) + GENERATE_ENUM(STENCIL_KEEP, 0) + GENERATE_ENUM(STENCIL_ZERO, 1) + GENERATE_ENUM(STENCIL_REPLACE, 2) + GENERATE_ENUM(STENCIL_INCR_CLAMP, 3) + GENERATE_ENUM(STENCIL_DECR_CLAMP, 4) + GENERATE_ENUM(STENCIL_INVERT, 5) + GENERATE_ENUM(STENCIL_INCR_WRAP, 6) + GENERATE_ENUM(STENCIL_DECR_WRAP, 7) +END_ENUMTYPE(StencilOp) + +START_ENUMTYPE(BlendOpX) + GENERATE_ENUM(BLENDX_ZERO, 0) + GENERATE_ENUM(BLENDX_ONE, 1) + GENERATE_ENUM(BLENDX_SRC_COLOR, 4) + GENERATE_ENUM(BLENDX_ONE_MINUS_SRC_COLOR, 5) + GENERATE_ENUM(BLENDX_SRC_ALPHA, 6) + GENERATE_ENUM(BLENDX_ONE_MINUS_SRC_ALPHA, 7) + GENERATE_ENUM(BLENDX_DST_COLOR, 8) + GENERATE_ENUM(BLENDX_ONE_MINUS_DST_COLOR, 9) + GENERATE_ENUM(BLENDX_DST_ALPHA, 10) + GENERATE_ENUM(BLENDX_ONE_MINUS_DST_ALPHA, 11) + GENERATE_ENUM(BLENDX_CONSTANT_COLOR, 12) + GENERATE_ENUM(BLENDX_ONE_MINUS_CONSTANT_COLOR, 13) + GENERATE_ENUM(BLENDX_CONSTANT_ALPHA, 14) + GENERATE_ENUM(BLENDX_ONE_MINUS_CONSTANT_ALPHA, 15) + GENERATE_ENUM(BLENDX_SRC_ALPHA_SATURATE, 16) +END_ENUMTYPE(BlendOpX) + +START_ENUMTYPE(CombFuncX) + GENERATE_ENUM(COMB_DST_PLUS_SRC, 0) + GENERATE_ENUM(COMB_SRC_MINUS_DST, 1) + GENERATE_ENUM(COMB_MIN_DST_SRC, 2) + GENERATE_ENUM(COMB_MAX_DST_SRC, 3) + GENERATE_ENUM(COMB_DST_MINUS_SRC, 4) + GENERATE_ENUM(COMB_DST_PLUS_SRC_BIAS, 5) +END_ENUMTYPE(CombFuncX) + +START_ENUMTYPE(DitherModeX) + GENERATE_ENUM(DITHER_DISABLE, 0) + GENERATE_ENUM(DITHER_ALWAYS, 1) + GENERATE_ENUM(DITHER_IF_ALPHA_OFF, 2) +END_ENUMTYPE(DitherModeX) + +START_ENUMTYPE(DitherTypeX) + GENERATE_ENUM(DITHER_PIXEL, 0) + GENERATE_ENUM(DITHER_SUBPIXEL, 1) +END_ENUMTYPE(DitherTypeX) + +START_ENUMTYPE(EdramMode) + GENERATE_ENUM(EDRAM_NOP, 0) + GENERATE_ENUM(COLOR_DEPTH, 4) + GENERATE_ENUM(DEPTH_ONLY, 5) + GENERATE_ENUM(EDRAM_COPY, 6) +END_ENUMTYPE(EdramMode) + +START_ENUMTYPE(SurfaceEndian) + GENERATE_ENUM(ENDIAN_NONE, 0) + GENERATE_ENUM(ENDIAN_8IN16, 1) + GENERATE_ENUM(ENDIAN_8IN32, 2) + GENERATE_ENUM(ENDIAN_16IN32, 3) + GENERATE_ENUM(ENDIAN_8IN64, 4) + GENERATE_ENUM(ENDIAN_8IN128, 5) +END_ENUMTYPE(SurfaceEndian) + +START_ENUMTYPE(EdramSizeX) + GENERATE_ENUM(EDRAMSIZE_16KB, 0) + GENERATE_ENUM(EDRAMSIZE_32KB, 1) + GENERATE_ENUM(EDRAMSIZE_64KB, 2) + GENERATE_ENUM(EDRAMSIZE_128KB, 3) + GENERATE_ENUM(EDRAMSIZE_256KB, 4) + GENERATE_ENUM(EDRAMSIZE_512KB, 5) + GENERATE_ENUM(EDRAMSIZE_1MB, 6) + GENERATE_ENUM(EDRAMSIZE_2MB, 7) + GENERATE_ENUM(EDRAMSIZE_4MB, 8) + GENERATE_ENUM(EDRAMSIZE_8MB, 9) + GENERATE_ENUM(EDRAMSIZE_16MB, 10) +END_ENUMTYPE(EdramSizeX) + +START_ENUMTYPE(RB_PERFCNT_SELECT) + GENERATE_ENUM(RBPERF_CNTX_BUSY, 0) + GENERATE_ENUM(RBPERF_CNTX_BUSY_MAX, 1) + GENERATE_ENUM(RBPERF_SX_QUAD_STARVED, 2) + GENERATE_ENUM(RBPERF_SX_QUAD_STARVED_MAX, 3) + GENERATE_ENUM(RBPERF_GA_GC_CH0_SYS_REQ, 4) + GENERATE_ENUM(RBPERF_GA_GC_CH0_SYS_REQ_MAX, 5) + GENERATE_ENUM(RBPERF_GA_GC_CH1_SYS_REQ, 6) + GENERATE_ENUM(RBPERF_GA_GC_CH1_SYS_REQ_MAX, 7) + GENERATE_ENUM(RBPERF_MH_STARVED, 8) + GENERATE_ENUM(RBPERF_MH_STARVED_MAX, 9) + GENERATE_ENUM(RBPERF_AZ_BC_COLOR_BUSY, 10) + GENERATE_ENUM(RBPERF_AZ_BC_COLOR_BUSY_MAX, 11) + GENERATE_ENUM(RBPERF_AZ_BC_Z_BUSY, 12) + GENERATE_ENUM(RBPERF_AZ_BC_Z_BUSY_MAX, 13) + GENERATE_ENUM(RBPERF_RB_SC_TILE_RTR_N, 14) + GENERATE_ENUM(RBPERF_RB_SC_TILE_RTR_N_MAX, 15) + GENERATE_ENUM(RBPERF_RB_SC_SAMP_RTR_N, 16) + GENERATE_ENUM(RBPERF_RB_SC_SAMP_RTR_N_MAX, 17) + GENERATE_ENUM(RBPERF_RB_SX_QUAD_RTR_N, 18) + GENERATE_ENUM(RBPERF_RB_SX_QUAD_RTR_N_MAX, 19) + GENERATE_ENUM(RBPERF_RB_SX_COLOR_RTR_N, 20) + GENERATE_ENUM(RBPERF_RB_SX_COLOR_RTR_N_MAX, 21) + GENERATE_ENUM(RBPERF_RB_SC_SAMP_LZ_BUSY, 22) + GENERATE_ENUM(RBPERF_RB_SC_SAMP_LZ_BUSY_MAX, 23) + GENERATE_ENUM(RBPERF_ZXP_STALL, 24) + GENERATE_ENUM(RBPERF_ZXP_STALL_MAX, 25) + GENERATE_ENUM(RBPERF_EVENT_PENDING, 26) + GENERATE_ENUM(RBPERF_EVENT_PENDING_MAX, 27) + GENERATE_ENUM(RBPERF_RB_MH_VALID, 28) + GENERATE_ENUM(RBPERF_RB_MH_VALID_MAX, 29) + GENERATE_ENUM(RBPERF_SX_RB_QUAD_SEND, 30) + GENERATE_ENUM(RBPERF_SX_RB_COLOR_SEND, 31) + GENERATE_ENUM(RBPERF_SC_RB_TILE_SEND, 32) + GENERATE_ENUM(RBPERF_SC_RB_SAMPLE_SEND, 33) + GENERATE_ENUM(RBPERF_SX_RB_MEM_EXPORT, 34) + GENERATE_ENUM(RBPERF_SX_RB_QUAD_EVENT, 35) + GENERATE_ENUM(RBPERF_SC_RB_TILE_EVENT_FILTERED, 36) + GENERATE_ENUM(RBPERF_SC_RB_TILE_EVENT_ALL, 37) + GENERATE_ENUM(RBPERF_RB_SC_EZ_SEND, 38) + GENERATE_ENUM(RBPERF_RB_SX_INDEX_SEND, 39) + GENERATE_ENUM(RBPERF_GMEM_INTFO_RD, 40) + GENERATE_ENUM(RBPERF_GMEM_INTF1_RD, 41) + GENERATE_ENUM(RBPERF_GMEM_INTFO_WR, 42) + GENERATE_ENUM(RBPERF_GMEM_INTF1_WR, 43) + GENERATE_ENUM(RBPERF_RB_CP_CONTEXT_DONE, 44) + GENERATE_ENUM(RBPERF_RB_CP_CACHE_FLUSH, 45) + GENERATE_ENUM(RBPERF_ZPASS_DONE, 46) + GENERATE_ENUM(RBPERF_ZCMD_VALID, 47) + GENERATE_ENUM(RBPERF_CCMD_VALID, 48) + GENERATE_ENUM(RBPERF_ACCUM_GRANT, 49) + GENERATE_ENUM(RBPERF_ACCUM_C0_GRANT, 50) + GENERATE_ENUM(RBPERF_ACCUM_C1_GRANT, 51) + GENERATE_ENUM(RBPERF_ACCUM_FULL_BE_WR, 52) + GENERATE_ENUM(RBPERF_ACCUM_REQUEST_NO_GRANT, 53) + GENERATE_ENUM(RBPERF_ACCUM_TIMEOUT_PULSE, 54) + GENERATE_ENUM(RBPERF_ACCUM_LIN_TIMEOUT_PULSE, 55) + GENERATE_ENUM(RBPERF_ACCUM_CAM_HIT_FLUSHING, 56) +END_ENUMTYPE(RB_PERFCNT_SELECT) + +START_ENUMTYPE(DepthFormat) + GENERATE_ENUM(DEPTH_24_8, 22) + GENERATE_ENUM(DEPTH_24_8_FLOAT, 23) + GENERATE_ENUM(DEPTH_16, 24) +END_ENUMTYPE(DepthFormat) + +START_ENUMTYPE(SurfaceSwap) + GENERATE_ENUM(SWAP_LOWRED, 0) + GENERATE_ENUM(SWAP_LOWBLUE, 1) +END_ENUMTYPE(SurfaceSwap) + +START_ENUMTYPE(DepthArray) + GENERATE_ENUM(ARRAY_2D_ALT_DEPTH, 0) + GENERATE_ENUM(ARRAY_2D_DEPTH, 1) +END_ENUMTYPE(DepthArray) + +START_ENUMTYPE(ColorArray) + GENERATE_ENUM(ARRAY_2D_ALT_COLOR, 0) + GENERATE_ENUM(ARRAY_2D_COLOR, 1) + GENERATE_ENUM(ARRAY_3D_SLICE_COLOR, 3) +END_ENUMTYPE(ColorArray) + +START_ENUMTYPE(ColorFormat) + GENERATE_ENUM(COLOR_8, 2) + GENERATE_ENUM(COLOR_1_5_5_5, 3) + GENERATE_ENUM(COLOR_5_6_5, 4) + GENERATE_ENUM(COLOR_6_5_5, 5) + GENERATE_ENUM(COLOR_8_8_8_8, 6) + GENERATE_ENUM(COLOR_2_10_10_10, 7) + GENERATE_ENUM(COLOR_8_A, 8) + GENERATE_ENUM(COLOR_8_B, 9) + GENERATE_ENUM(COLOR_8_8, 10) + GENERATE_ENUM(COLOR_8_8_8, 11) + GENERATE_ENUM(COLOR_8_8_8_8_A, 14) + GENERATE_ENUM(COLOR_4_4_4_4, 15) + GENERATE_ENUM(COLOR_10_11_11, 16) + GENERATE_ENUM(COLOR_11_11_10, 17) + GENERATE_ENUM(COLOR_16, 24) + GENERATE_ENUM(COLOR_16_16, 25) + GENERATE_ENUM(COLOR_16_16_16_16, 26) + GENERATE_ENUM(COLOR_16_FLOAT, 30) + GENERATE_ENUM(COLOR_16_16_FLOAT, 31) + GENERATE_ENUM(COLOR_16_16_16_16_FLOAT, 32) + GENERATE_ENUM(COLOR_32_FLOAT, 36) + GENERATE_ENUM(COLOR_32_32_FLOAT, 37) + GENERATE_ENUM(COLOR_32_32_32_32_FLOAT, 38) + GENERATE_ENUM(COLOR_2_3_3, 39) +END_ENUMTYPE(ColorFormat) + +START_ENUMTYPE(SurfaceNumber) + GENERATE_ENUM(NUMBER_UREPEAT, 0) + GENERATE_ENUM(NUMBER_SREPEAT, 1) + GENERATE_ENUM(NUMBER_UINTEGER, 2) + GENERATE_ENUM(NUMBER_SINTEGER, 3) + GENERATE_ENUM(NUMBER_GAMMA, 4) + GENERATE_ENUM(NUMBER_FIXED, 5) + GENERATE_ENUM(NUMBER_FLOAT, 7) +END_ENUMTYPE(SurfaceNumber) + +START_ENUMTYPE(SurfaceFormat) + GENERATE_ENUM(FMT_1_REVERSE, 0) + GENERATE_ENUM(FMT_1, 1) + GENERATE_ENUM(FMT_8, 2) + GENERATE_ENUM(FMT_1_5_5_5, 3) + GENERATE_ENUM(FMT_5_6_5, 4) + GENERATE_ENUM(FMT_6_5_5, 5) + GENERATE_ENUM(FMT_8_8_8_8, 6) + GENERATE_ENUM(FMT_2_10_10_10, 7) + GENERATE_ENUM(FMT_8_A, 8) + GENERATE_ENUM(FMT_8_B, 9) + GENERATE_ENUM(FMT_8_8, 10) + GENERATE_ENUM(FMT_Cr_Y1_Cb_Y0, 11) + GENERATE_ENUM(FMT_Y1_Cr_Y0_Cb, 12) + GENERATE_ENUM(FMT_5_5_5_1, 13) + GENERATE_ENUM(FMT_8_8_8_8_A, 14) + GENERATE_ENUM(FMT_4_4_4_4, 15) + GENERATE_ENUM(FMT_8_8_8, 16) + GENERATE_ENUM(FMT_DXT1, 18) + GENERATE_ENUM(FMT_DXT2_3, 19) + GENERATE_ENUM(FMT_DXT4_5, 20) + GENERATE_ENUM(FMT_10_10_10_2, 21) + GENERATE_ENUM(FMT_24_8, 22) + GENERATE_ENUM(FMT_16, 24) + GENERATE_ENUM(FMT_16_16, 25) + GENERATE_ENUM(FMT_16_16_16_16, 26) + GENERATE_ENUM(FMT_16_EXPAND, 27) + GENERATE_ENUM(FMT_16_16_EXPAND, 28) + GENERATE_ENUM(FMT_16_16_16_16_EXPAND, 29) + GENERATE_ENUM(FMT_16_FLOAT, 30) + GENERATE_ENUM(FMT_16_16_FLOAT, 31) + GENERATE_ENUM(FMT_16_16_16_16_FLOAT, 32) + GENERATE_ENUM(FMT_32, 33) + GENERATE_ENUM(FMT_32_32, 34) + GENERATE_ENUM(FMT_32_32_32_32, 35) + GENERATE_ENUM(FMT_32_FLOAT, 36) + GENERATE_ENUM(FMT_32_32_FLOAT, 37) + GENERATE_ENUM(FMT_32_32_32_32_FLOAT, 38) + GENERATE_ENUM(FMT_ATI_TC_RGB, 39) + GENERATE_ENUM(FMT_ATI_TC_RGBA, 40) + GENERATE_ENUM(FMT_ATI_TC_555_565_RGB, 41) + GENERATE_ENUM(FMT_ATI_TC_555_565_RGBA, 42) + GENERATE_ENUM(FMT_ATI_TC_RGBA_INTERP, 43) + GENERATE_ENUM(FMT_ATI_TC_555_565_RGBA_INTERP, 44) + GENERATE_ENUM(FMT_ETC1_RGBA_INTERP, 46) + GENERATE_ENUM(FMT_ETC1_RGB, 47) + GENERATE_ENUM(FMT_ETC1_RGBA, 48) + GENERATE_ENUM(FMT_DXN, 49) + GENERATE_ENUM(FMT_2_3_3, 51) + GENERATE_ENUM(FMT_2_10_10_10_AS_16_16_16_16, 54) + GENERATE_ENUM(FMT_10_10_10_2_AS_16_16_16_16, 55) + GENERATE_ENUM(FMT_32_32_32_FLOAT, 57) + GENERATE_ENUM(FMT_DXT3A, 58) + GENERATE_ENUM(FMT_DXT5A, 59) + GENERATE_ENUM(FMT_CTX1, 60) +END_ENUMTYPE(SurfaceFormat) + +START_ENUMTYPE(SurfaceTiling) + GENERATE_ENUM(ARRAY_LINEAR, 0) + GENERATE_ENUM(ARRAY_TILED, 1) +END_ENUMTYPE(SurfaceTiling) + +START_ENUMTYPE(SurfaceArray) + GENERATE_ENUM(ARRAY_1D, 0) + GENERATE_ENUM(ARRAY_2D, 1) + GENERATE_ENUM(ARRAY_3D, 2) + GENERATE_ENUM(ARRAY_3D_SLICE, 3) +END_ENUMTYPE(SurfaceArray) + +START_ENUMTYPE(SurfaceNumberX) + GENERATE_ENUM(NUMBERX_UREPEAT, 0) + GENERATE_ENUM(NUMBERX_SREPEAT, 1) + GENERATE_ENUM(NUMBERX_UINTEGER, 2) + GENERATE_ENUM(NUMBERX_SINTEGER, 3) + GENERATE_ENUM(NUMBERX_FLOAT, 7) +END_ENUMTYPE(SurfaceNumberX) + +START_ENUMTYPE(ColorArrayX) + GENERATE_ENUM(ARRAYX_2D_COLOR, 0) + GENERATE_ENUM(ARRAYX_3D_SLICE_COLOR, 1) +END_ENUMTYPE(ColorArrayX) + + + + +// ************************************************************************** +// These are ones that had to be added in addition to what's generated +// by the autoreg (in CSIM) +// ************************************************************************** +START_ENUMTYPE(DXClipSpaceDef) + GENERATE_ENUM(DXCLIP_OPENGL, 0) + GENERATE_ENUM(DXCLIP_DIRECTX, 1) +END_ENUMTYPE(DXClipSpaceDef) + +START_ENUMTYPE(PixCenter) + GENERATE_ENUM(PIXCENTER_D3D, 0) + GENERATE_ENUM(PIXCENTER_OGL, 1) +END_ENUMTYPE(PixCenter) + +START_ENUMTYPE(RoundMode) + GENERATE_ENUM(TRUNCATE, 0) + GENERATE_ENUM(ROUND, 1) + GENERATE_ENUM(ROUNDTOEVEN, 2) + GENERATE_ENUM(ROUNDTOODD, 3) +END_ENUMTYPE(RoundMode) + +START_ENUMTYPE(QuantMode) + GENERATE_ENUM(ONE_SIXTEENTH, 0) + GENERATE_ENUM(ONE_EIGHTH, 1) + GENERATE_ENUM(ONE_QUARTER, 2) + GENERATE_ENUM(ONE_HALF, 3) + GENERATE_ENUM(ONE, 4) +END_ENUMTYPE(QuantMode) + +START_ENUMTYPE(FrontFace) + GENERATE_ENUM(FRONT_CCW, 0) + GENERATE_ENUM(FRONT_CW, 1) +END_ENUMTYPE(FrontFace) + +START_ENUMTYPE(PolyMode) + GENERATE_ENUM(DISABLED, 0) + GENERATE_ENUM(DUALMODE, 1) +END_ENUMTYPE(PolyMode) + +START_ENUMTYPE(PType) + GENERATE_ENUM(DRAW_POINTS, 0) + GENERATE_ENUM(DRAW_LINES, 1) + GENERATE_ENUM(DRAW_TRIANGLES, 2) +END_ENUMTYPE(PType) + +START_ENUMTYPE(MSAANumSamples) + GENERATE_ENUM(ONE, 0) + GENERATE_ENUM(TWO, 1) + GENERATE_ENUM(FOUR, 3) +END_ENUMTYPE(MSAANumSamples) + +START_ENUMTYPE(PatternBitOrder) + GENERATE_ENUM(LITTLE, 0) + GENERATE_ENUM(BIG, 1) +END_ENUMTYPE(PatternBitOrder) + +START_ENUMTYPE(AutoResetCntl) + GENERATE_ENUM(NEVER, 0) + GENERATE_ENUM(EACHPRIMITIVE, 1) + GENERATE_ENUM(EACHPACKET, 2) +END_ENUMTYPE(AutoResetCntl) + +START_ENUMTYPE(ParamShade) + GENERATE_ENUM(FLAT, 0) + GENERATE_ENUM(GOURAUD, 1) +END_ENUMTYPE(ParamShade) + +START_ENUMTYPE(SamplingPattern) + GENERATE_ENUM(CENTROID, 0) + GENERATE_ENUM(PIXCENTER, 1) +END_ENUMTYPE(SamplingPattern) + +START_ENUMTYPE(MSAASamples) + GENERATE_ENUM(ONE, 0) + GENERATE_ENUM(TWO, 1) + GENERATE_ENUM(FOUR, 2) +END_ENUMTYPE(MSAASamples) + +START_ENUMTYPE(CopySampleSelect) + GENERATE_ENUM(SAMPLE_0, 0) + GENERATE_ENUM(SAMPLE_1, 1) + GENERATE_ENUM(SAMPLE_2, 2) + GENERATE_ENUM(SAMPLE_3, 3) + GENERATE_ENUM(SAMPLE_01, 4) + GENERATE_ENUM(SAMPLE_23, 5) + GENERATE_ENUM(SAMPLE_0123, 6) +END_ENUMTYPE(CopySampleSelect) + + +#undef START_ENUMTYPE +#undef GENERATE_ENUM +#undef END_ENUMTYPE + + diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_genreg.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_genreg.h new file mode 100644 index 000000000000..d04379887b78 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_genreg.h @@ -0,0 +1,3405 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +START_REGISTER(PA_CL_VPORT_XSCALE) + GENERATE_FIELD(VPORT_XSCALE, float) +END_REGISTER(PA_CL_VPORT_XSCALE) + +START_REGISTER(PA_CL_VPORT_XOFFSET) + GENERATE_FIELD(VPORT_XOFFSET, float) +END_REGISTER(PA_CL_VPORT_XOFFSET) + +START_REGISTER(PA_CL_VPORT_YSCALE) + GENERATE_FIELD(VPORT_YSCALE, float) +END_REGISTER(PA_CL_VPORT_YSCALE) + +START_REGISTER(PA_CL_VPORT_YOFFSET) + GENERATE_FIELD(VPORT_YOFFSET, float) +END_REGISTER(PA_CL_VPORT_YOFFSET) + +START_REGISTER(PA_CL_VPORT_ZSCALE) + GENERATE_FIELD(VPORT_ZSCALE, float) +END_REGISTER(PA_CL_VPORT_ZSCALE) + +START_REGISTER(PA_CL_VPORT_ZOFFSET) + GENERATE_FIELD(VPORT_ZOFFSET, float) +END_REGISTER(PA_CL_VPORT_ZOFFSET) + +START_REGISTER(PA_CL_VTE_CNTL) + GENERATE_FIELD(VPORT_X_SCALE_ENA, bool) + GENERATE_FIELD(VPORT_X_OFFSET_ENA, bool) + GENERATE_FIELD(VPORT_Y_SCALE_ENA, bool) + GENERATE_FIELD(VPORT_Y_OFFSET_ENA, bool) + GENERATE_FIELD(VPORT_Z_SCALE_ENA, bool) + GENERATE_FIELD(VPORT_Z_OFFSET_ENA, bool) + GENERATE_FIELD(VTX_XY_FMT, bool) + GENERATE_FIELD(VTX_Z_FMT, bool) + GENERATE_FIELD(VTX_W0_FMT, bool) + GENERATE_FIELD(PERFCOUNTER_REF, bool) +END_REGISTER(PA_CL_VTE_CNTL) + +START_REGISTER(PA_CL_CLIP_CNTL) + GENERATE_FIELD(CLIP_DISABLE, bool) + GENERATE_FIELD(BOUNDARY_EDGE_FLAG_ENA, bool) + GENERATE_FIELD(DX_CLIP_SPACE_DEF, DXClipSpaceDef) + GENERATE_FIELD(DIS_CLIP_ERR_DETECT, bool) + GENERATE_FIELD(VTX_KILL_OR, bool) + GENERATE_FIELD(XY_NAN_RETAIN, bool) + GENERATE_FIELD(Z_NAN_RETAIN, bool) + GENERATE_FIELD(W_NAN_RETAIN, bool) +END_REGISTER(PA_CL_CLIP_CNTL) + +START_REGISTER(PA_CL_GB_VERT_CLIP_ADJ) + GENERATE_FIELD(DATA_REGISTER, float) +END_REGISTER(PA_CL_GB_VERT_CLIP_ADJ) + +START_REGISTER(PA_CL_GB_VERT_DISC_ADJ) + GENERATE_FIELD(DATA_REGISTER, float) +END_REGISTER(PA_CL_GB_VERT_DISC_ADJ) + +START_REGISTER(PA_CL_GB_HORZ_CLIP_ADJ) + GENERATE_FIELD(DATA_REGISTER, float) +END_REGISTER(PA_CL_GB_HORZ_CLIP_ADJ) + +START_REGISTER(PA_CL_GB_HORZ_DISC_ADJ) + GENERATE_FIELD(DATA_REGISTER, float) +END_REGISTER(PA_CL_GB_HORZ_DISC_ADJ) + +START_REGISTER(PA_CL_ENHANCE) + GENERATE_FIELD(CLIP_VTX_REORDER_ENA, bool) + GENERATE_FIELD(ECO_SPARE3, int) + GENERATE_FIELD(ECO_SPARE2, int) + GENERATE_FIELD(ECO_SPARE1, int) + GENERATE_FIELD(ECO_SPARE0, int) +END_REGISTER(PA_CL_ENHANCE) + +START_REGISTER(PA_SC_ENHANCE) + GENERATE_FIELD(ECO_SPARE3, int) + GENERATE_FIELD(ECO_SPARE2, int) + GENERATE_FIELD(ECO_SPARE1, int) + GENERATE_FIELD(ECO_SPARE0, int) +END_REGISTER(PA_SC_ENHANCE) + +START_REGISTER(PA_SU_VTX_CNTL) + GENERATE_FIELD(PIX_CENTER, PixCenter) + GENERATE_FIELD(ROUND_MODE, RoundMode) + GENERATE_FIELD(QUANT_MODE, QuantMode) +END_REGISTER(PA_SU_VTX_CNTL) + +START_REGISTER(PA_SU_POINT_SIZE) + GENERATE_FIELD(HEIGHT, fixed12_4) + GENERATE_FIELD(WIDTH, fixed12_4) +END_REGISTER(PA_SU_POINT_SIZE) + +START_REGISTER(PA_SU_POINT_MINMAX) + GENERATE_FIELD(MIN_SIZE, fixed12_4) + GENERATE_FIELD(MAX_SIZE, fixed12_4) +END_REGISTER(PA_SU_POINT_MINMAX) + +START_REGISTER(PA_SU_LINE_CNTL) + GENERATE_FIELD(WIDTH, fixed12_4) +END_REGISTER(PA_SU_LINE_CNTL) + +START_REGISTER(PA_SU_FACE_DATA) + GENERATE_FIELD(BASE_ADDR, int) +END_REGISTER(PA_SU_FACE_DATA) + +START_REGISTER(PA_SU_SC_MODE_CNTL) + GENERATE_FIELD(CULL_FRONT, bool) + GENERATE_FIELD(CULL_BACK, bool) + GENERATE_FIELD(FACE, FrontFace) + GENERATE_FIELD(POLY_MODE, PolyMode) + GENERATE_FIELD(POLYMODE_FRONT_PTYPE, PType) + GENERATE_FIELD(POLYMODE_BACK_PTYPE, PType) + GENERATE_FIELD(POLY_OFFSET_FRONT_ENABLE, bool) + GENERATE_FIELD(POLY_OFFSET_BACK_ENABLE, bool) + GENERATE_FIELD(POLY_OFFSET_PARA_ENABLE, bool) + GENERATE_FIELD(MSAA_ENABLE, bool) + GENERATE_FIELD(VTX_WINDOW_OFFSET_ENABLE, bool) + GENERATE_FIELD(LINE_STIPPLE_ENABLE, bool) + GENERATE_FIELD(PROVOKING_VTX_LAST, bool) + GENERATE_FIELD(PERSP_CORR_DIS, bool) + GENERATE_FIELD(MULTI_PRIM_IB_ENA, bool) + GENERATE_FIELD(QUAD_ORDER_ENABLE, bool) + GENERATE_FIELD(WAIT_RB_IDLE_ALL_TRI, bool) + GENERATE_FIELD(WAIT_RB_IDLE_FIRST_TRI_NEW_STATE, bool) + GENERATE_FIELD(CLAMPED_FACENESS, bool) + GENERATE_FIELD(ZERO_AREA_FACENESS, bool) + GENERATE_FIELD(FACE_KILL_ENABLE, bool) + GENERATE_FIELD(FACE_WRITE_ENABLE, bool) +END_REGISTER(PA_SU_SC_MODE_CNTL) + +START_REGISTER(PA_SU_POLY_OFFSET_FRONT_SCALE) + GENERATE_FIELD(SCALE, float) +END_REGISTER(PA_SU_POLY_OFFSET_FRONT_SCALE) + +START_REGISTER(PA_SU_POLY_OFFSET_FRONT_OFFSET) + GENERATE_FIELD(OFFSET, float) +END_REGISTER(PA_SU_POLY_OFFSET_FRONT_OFFSET) + +START_REGISTER(PA_SU_POLY_OFFSET_BACK_SCALE) + GENERATE_FIELD(SCALE, float) +END_REGISTER(PA_SU_POLY_OFFSET_BACK_SCALE) + +START_REGISTER(PA_SU_POLY_OFFSET_BACK_OFFSET) + GENERATE_FIELD(OFFSET, float) +END_REGISTER(PA_SU_POLY_OFFSET_BACK_OFFSET) + +START_REGISTER(PA_SU_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, SU_PERFCNT_SELECT) +END_REGISTER(PA_SU_PERFCOUNTER0_SELECT) + +START_REGISTER(PA_SU_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(PA_SU_PERFCOUNTER1_SELECT) + +START_REGISTER(PA_SU_PERFCOUNTER2_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(PA_SU_PERFCOUNTER2_SELECT) + +START_REGISTER(PA_SU_PERFCOUNTER3_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(PA_SU_PERFCOUNTER3_SELECT) + +START_REGISTER(PA_SU_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER0_LOW) + +START_REGISTER(PA_SU_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER0_HI) + +START_REGISTER(PA_SU_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER1_LOW) + +START_REGISTER(PA_SU_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER1_HI) + +START_REGISTER(PA_SU_PERFCOUNTER2_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER2_LOW) + +START_REGISTER(PA_SU_PERFCOUNTER2_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER2_HI) + +START_REGISTER(PA_SU_PERFCOUNTER3_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER3_LOW) + +START_REGISTER(PA_SU_PERFCOUNTER3_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SU_PERFCOUNTER3_HI) + +START_REGISTER(PA_SC_WINDOW_OFFSET) + GENERATE_FIELD(WINDOW_X_OFFSET, signedint15) + GENERATE_FIELD(WINDOW_Y_OFFSET, signedint15) +END_REGISTER(PA_SC_WINDOW_OFFSET) + +START_REGISTER(PA_SC_AA_CONFIG) + GENERATE_FIELD(MSAA_NUM_SAMPLES, MSAANumSamples) + GENERATE_FIELD(MAX_SAMPLE_DIST, int) +END_REGISTER(PA_SC_AA_CONFIG) + +START_REGISTER(PA_SC_AA_MASK) + GENERATE_FIELD(AA_MASK, hex) +END_REGISTER(PA_SC_AA_MASK) + +START_REGISTER(PA_SC_LINE_STIPPLE) + GENERATE_FIELD(LINE_PATTERN, hex) + GENERATE_FIELD(REPEAT_COUNT, intMinusOne) + GENERATE_FIELD(PATTERN_BIT_ORDER, PatternBitOrder) + GENERATE_FIELD(AUTO_RESET_CNTL, AutoResetCntl) +END_REGISTER(PA_SC_LINE_STIPPLE) + +START_REGISTER(PA_SC_LINE_CNTL) + GENERATE_FIELD(BRES_CNTL, int) + GENERATE_FIELD(USE_BRES_CNTL, bool) + GENERATE_FIELD(EXPAND_LINE_WIDTH, bool) + GENERATE_FIELD(LAST_PIXEL, bool) +END_REGISTER(PA_SC_LINE_CNTL) + +START_REGISTER(PA_SC_WINDOW_SCISSOR_TL) + GENERATE_FIELD(TL_X, int) + GENERATE_FIELD(TL_Y, int) + GENERATE_FIELD(WINDOW_OFFSET_DISABLE, bool) +END_REGISTER(PA_SC_WINDOW_SCISSOR_TL) + +START_REGISTER(PA_SC_WINDOW_SCISSOR_BR) + GENERATE_FIELD(BR_X, int) + GENERATE_FIELD(BR_Y, int) +END_REGISTER(PA_SC_WINDOW_SCISSOR_BR) + +START_REGISTER(PA_SC_SCREEN_SCISSOR_TL) + GENERATE_FIELD(TL_X, int) + GENERATE_FIELD(TL_Y, int) +END_REGISTER(PA_SC_SCREEN_SCISSOR_TL) + +START_REGISTER(PA_SC_SCREEN_SCISSOR_BR) + GENERATE_FIELD(BR_X, int) + GENERATE_FIELD(BR_Y, int) +END_REGISTER(PA_SC_SCREEN_SCISSOR_BR) + +START_REGISTER(PA_SC_VIZ_QUERY) + GENERATE_FIELD(VIZ_QUERY_ENA, bool) + GENERATE_FIELD(VIZ_QUERY_ID, int) + GENERATE_FIELD(KILL_PIX_POST_EARLY_Z, bool) +END_REGISTER(PA_SC_VIZ_QUERY) + +START_REGISTER(PA_SC_VIZ_QUERY_STATUS) + GENERATE_FIELD(STATUS_BITS, hex) +END_REGISTER(PA_SC_VIZ_QUERY_STATUS) + +START_REGISTER(PA_SC_LINE_STIPPLE_STATE) + GENERATE_FIELD(CURRENT_PTR, int) + GENERATE_FIELD(CURRENT_COUNT, int) +END_REGISTER(PA_SC_LINE_STIPPLE_STATE) + +START_REGISTER(PA_SC_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, SC_PERFCNT_SELECT) +END_REGISTER(PA_SC_PERFCOUNTER0_SELECT) + +START_REGISTER(PA_SC_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SC_PERFCOUNTER0_LOW) + +START_REGISTER(PA_SC_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(PA_SC_PERFCOUNTER0_HI) + +START_REGISTER(PA_CL_CNTL_STATUS) + GENERATE_FIELD(CL_BUSY, int) +END_REGISTER(PA_CL_CNTL_STATUS) + +START_REGISTER(PA_SU_CNTL_STATUS) + GENERATE_FIELD(SU_BUSY, int) +END_REGISTER(PA_SU_CNTL_STATUS) + +START_REGISTER(PA_SC_CNTL_STATUS) + GENERATE_FIELD(SC_BUSY, int) +END_REGISTER(PA_SC_CNTL_STATUS) + +START_REGISTER(PA_SU_DEBUG_CNTL) + GENERATE_FIELD(SU_DEBUG_INDX, int) +END_REGISTER(PA_SU_DEBUG_CNTL) + +START_REGISTER(PA_SU_DEBUG_DATA) + GENERATE_FIELD(DATA, hex) +END_REGISTER(PA_SU_DEBUG_DATA) + +START_REGISTER(PA_SC_DEBUG_CNTL) + GENERATE_FIELD(SC_DEBUG_INDX, int) +END_REGISTER(PA_SC_DEBUG_CNTL) + +START_REGISTER(PA_SC_DEBUG_DATA) + GENERATE_FIELD(DATA, int) +END_REGISTER(PA_SC_DEBUG_DATA) + +START_REGISTER(GFX_COPY_STATE) + GENERATE_FIELD(SRC_STATE_ID, int) +END_REGISTER(GFX_COPY_STATE) + +START_REGISTER(VGT_DRAW_INITIATOR) + GENERATE_FIELD(PRIM_TYPE, VGT_DI_PRIM_TYPE) + GENERATE_FIELD(SOURCE_SELECT, VGT_DI_SOURCE_SELECT) + GENERATE_FIELD(FACENESS_CULL_SELECT, VGT_DI_FACENESS_CULL_SELECT) + GENERATE_FIELD(INDEX_SIZE, VGT_DI_INDEX_SIZE) + GENERATE_FIELD(NOT_EOP, bool) + GENERATE_FIELD(SMALL_INDEX, VGT_DI_SMALL_INDEX) + GENERATE_FIELD(PRE_FETCH_CULL_ENABLE, VGT_DI_PRE_FETCH_CULL_ENABLE) + GENERATE_FIELD(GRP_CULL_ENABLE, VGT_DI_GRP_CULL_ENABLE) + GENERATE_FIELD(NUM_INDICES, uint) +END_REGISTER(VGT_DRAW_INITIATOR) + +START_REGISTER(VGT_EVENT_INITIATOR) + GENERATE_FIELD(EVENT_TYPE, VGT_EVENT_TYPE) +END_REGISTER(VGT_EVENT_INITIATOR) + +START_REGISTER(VGT_DMA_BASE) + GENERATE_FIELD(BASE_ADDR, uint) +END_REGISTER(VGT_DMA_BASE) + +START_REGISTER(VGT_DMA_SIZE) + GENERATE_FIELD(NUM_WORDS, uint) + GENERATE_FIELD(SWAP_MODE, VGT_DMA_SWAP_MODE) +END_REGISTER(VGT_DMA_SIZE) + +START_REGISTER(VGT_BIN_BASE) + GENERATE_FIELD(BIN_BASE_ADDR, uint) +END_REGISTER(VGT_BIN_BASE) + +START_REGISTER(VGT_BIN_SIZE) + GENERATE_FIELD(NUM_WORDS, uint) + GENERATE_FIELD(FACENESS_FETCH, int) + GENERATE_FIELD(FACENESS_RESET, int) +END_REGISTER(VGT_BIN_SIZE) + +START_REGISTER(VGT_CURRENT_BIN_ID_MIN) + GENERATE_FIELD(COLUMN, int) + GENERATE_FIELD(ROW, int) + GENERATE_FIELD(GUARD_BAND, int) +END_REGISTER(VGT_CURRENT_BIN_ID_MIN) + +START_REGISTER(VGT_CURRENT_BIN_ID_MAX) + GENERATE_FIELD(COLUMN, int) + GENERATE_FIELD(ROW, int) + GENERATE_FIELD(GUARD_BAND, int) +END_REGISTER(VGT_CURRENT_BIN_ID_MAX) + +START_REGISTER(VGT_IMMED_DATA) + GENERATE_FIELD(DATA, hex) +END_REGISTER(VGT_IMMED_DATA) + +START_REGISTER(VGT_MAX_VTX_INDX) + GENERATE_FIELD(MAX_INDX, int) +END_REGISTER(VGT_MAX_VTX_INDX) + +START_REGISTER(VGT_MIN_VTX_INDX) + GENERATE_FIELD(MIN_INDX, int) +END_REGISTER(VGT_MIN_VTX_INDX) + +START_REGISTER(VGT_INDX_OFFSET) + GENERATE_FIELD(INDX_OFFSET, int) +END_REGISTER(VGT_INDX_OFFSET) + +START_REGISTER(VGT_VERTEX_REUSE_BLOCK_CNTL) + GENERATE_FIELD(VTX_REUSE_DEPTH, int) +END_REGISTER(VGT_VERTEX_REUSE_BLOCK_CNTL) + +START_REGISTER(VGT_OUT_DEALLOC_CNTL) + GENERATE_FIELD(DEALLOC_DIST, int) +END_REGISTER(VGT_OUT_DEALLOC_CNTL) + +START_REGISTER(VGT_MULTI_PRIM_IB_RESET_INDX) + GENERATE_FIELD(RESET_INDX, int) +END_REGISTER(VGT_MULTI_PRIM_IB_RESET_INDX) + +START_REGISTER(VGT_ENHANCE) + GENERATE_FIELD(MISC, hex) +END_REGISTER(VGT_ENHANCE) + +START_REGISTER(VGT_VTX_VECT_EJECT_REG) + GENERATE_FIELD(PRIM_COUNT, int) +END_REGISTER(VGT_VTX_VECT_EJECT_REG) + +START_REGISTER(VGT_LAST_COPY_STATE) + GENERATE_FIELD(SRC_STATE_ID, int) + GENERATE_FIELD(DST_STATE_ID, int) +END_REGISTER(VGT_LAST_COPY_STATE) + +START_REGISTER(VGT_DEBUG_CNTL) + GENERATE_FIELD(VGT_DEBUG_INDX, int) +END_REGISTER(VGT_DEBUG_CNTL) + +START_REGISTER(VGT_DEBUG_DATA) + GENERATE_FIELD(DATA, hex) +END_REGISTER(VGT_DEBUG_DATA) + +START_REGISTER(VGT_CNTL_STATUS) + GENERATE_FIELD(VGT_BUSY, int) + GENERATE_FIELD(VGT_DMA_BUSY, int) + GENERATE_FIELD(VGT_DMA_REQ_BUSY, int) + GENERATE_FIELD(VGT_GRP_BUSY, int) + GENERATE_FIELD(VGT_VR_BUSY, int) + GENERATE_FIELD(VGT_BIN_BUSY, int) + GENERATE_FIELD(VGT_PT_BUSY, int) + GENERATE_FIELD(VGT_OUT_BUSY, int) + GENERATE_FIELD(VGT_OUT_INDX_BUSY, int) +END_REGISTER(VGT_CNTL_STATUS) + +START_REGISTER(VGT_CRC_SQ_DATA) + GENERATE_FIELD(CRC, hex) +END_REGISTER(VGT_CRC_SQ_DATA) + +START_REGISTER(VGT_CRC_SQ_CTRL) + GENERATE_FIELD(CRC, hex) +END_REGISTER(VGT_CRC_SQ_CTRL) + +START_REGISTER(VGT_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT) +END_REGISTER(VGT_PERFCOUNTER0_SELECT) + +START_REGISTER(VGT_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT) +END_REGISTER(VGT_PERFCOUNTER1_SELECT) + +START_REGISTER(VGT_PERFCOUNTER2_SELECT) + GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT) +END_REGISTER(VGT_PERFCOUNTER2_SELECT) + +START_REGISTER(VGT_PERFCOUNTER3_SELECT) + GENERATE_FIELD(PERF_SEL, VGT_PERFCOUNT_SELECT) +END_REGISTER(VGT_PERFCOUNTER3_SELECT) + +START_REGISTER(VGT_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER0_LOW) + +START_REGISTER(VGT_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER1_LOW) + +START_REGISTER(VGT_PERFCOUNTER2_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER2_LOW) + +START_REGISTER(VGT_PERFCOUNTER3_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER3_LOW) + +START_REGISTER(VGT_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER0_HI) + +START_REGISTER(VGT_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER1_HI) + +START_REGISTER(VGT_PERFCOUNTER2_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER2_HI) + +START_REGISTER(VGT_PERFCOUNTER3_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(VGT_PERFCOUNTER3_HI) + +START_REGISTER(TC_CNTL_STATUS) + GENERATE_FIELD(L2_INVALIDATE, int) + GENERATE_FIELD(TC_L2_HIT_MISS, int) + GENERATE_FIELD(TC_BUSY, int) +END_REGISTER(TC_CNTL_STATUS) + +START_REGISTER(TCR_CHICKEN) + GENERATE_FIELD(SPARE, hex) +END_REGISTER(TCR_CHICKEN) + +START_REGISTER(TCF_CHICKEN) + GENERATE_FIELD(SPARE, hex) +END_REGISTER(TCF_CHICKEN) + +START_REGISTER(TCM_CHICKEN) + GENERATE_FIELD(TCO_READ_LATENCY_FIFO_PROG_DEPTH, int) + GENERATE_FIELD(ETC_COLOR_ENDIAN, int) + GENERATE_FIELD(SPARE, hex) +END_REGISTER(TCM_CHICKEN) + +START_REGISTER(TCR_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCR_PERFCOUNT_SELECT) +END_REGISTER(TCR_PERFCOUNTER0_SELECT) + +START_REGISTER(TCR_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCR_PERFCOUNT_SELECT) +END_REGISTER(TCR_PERFCOUNTER1_SELECT) + +START_REGISTER(TCR_PERFCOUNTER0_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCR_PERFCOUNTER0_HI) + +START_REGISTER(TCR_PERFCOUNTER1_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCR_PERFCOUNTER1_HI) + +START_REGISTER(TCR_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCR_PERFCOUNTER0_LOW) + +START_REGISTER(TCR_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCR_PERFCOUNTER1_LOW) + +START_REGISTER(TP_TC_CLKGATE_CNTL) + GENERATE_FIELD(TP_BUSY_EXTEND, int) + GENERATE_FIELD(TC_BUSY_EXTEND, int) +END_REGISTER(TP_TC_CLKGATE_CNTL) + +START_REGISTER(TPC_CNTL_STATUS) + GENERATE_FIELD(TPC_INPUT_BUSY, int) + GENERATE_FIELD(TPC_TC_FIFO_BUSY, int) + GENERATE_FIELD(TPC_STATE_FIFO_BUSY, int) + GENERATE_FIELD(TPC_FETCH_FIFO_BUSY, int) + GENERATE_FIELD(TPC_WALKER_PIPE_BUSY, int) + GENERATE_FIELD(TPC_WALK_FIFO_BUSY, int) + GENERATE_FIELD(TPC_WALKER_BUSY, int) + GENERATE_FIELD(TPC_ALIGNER_PIPE_BUSY, int) + GENERATE_FIELD(TPC_ALIGN_FIFO_BUSY, int) + GENERATE_FIELD(TPC_ALIGNER_BUSY, int) + GENERATE_FIELD(TPC_RR_FIFO_BUSY, int) + GENERATE_FIELD(TPC_BLEND_PIPE_BUSY, int) + GENERATE_FIELD(TPC_OUT_FIFO_BUSY, int) + GENERATE_FIELD(TPC_BLEND_BUSY, int) + GENERATE_FIELD(TF_TW_RTS, int) + GENERATE_FIELD(TF_TW_STATE_RTS, int) + GENERATE_FIELD(TF_TW_RTR, int) + GENERATE_FIELD(TW_TA_RTS, int) + GENERATE_FIELD(TW_TA_TT_RTS, int) + GENERATE_FIELD(TW_TA_LAST_RTS, int) + GENERATE_FIELD(TW_TA_RTR, int) + GENERATE_FIELD(TA_TB_RTS, int) + GENERATE_FIELD(TA_TB_TT_RTS, int) + GENERATE_FIELD(TA_TB_RTR, int) + GENERATE_FIELD(TA_TF_RTS, int) + GENERATE_FIELD(TA_TF_TC_FIFO_REN, int) + GENERATE_FIELD(TP_SQ_DEC, int) + GENERATE_FIELD(TPC_BUSY, int) +END_REGISTER(TPC_CNTL_STATUS) + +START_REGISTER(TPC_DEBUG0) + GENERATE_FIELD(LOD_CNTL, int) + GENERATE_FIELD(IC_CTR, int) + GENERATE_FIELD(WALKER_CNTL, int) + GENERATE_FIELD(ALIGNER_CNTL, int) + GENERATE_FIELD(PREV_TC_STATE_VALID, int) + GENERATE_FIELD(WALKER_STATE, int) + GENERATE_FIELD(ALIGNER_STATE, int) + GENERATE_FIELD(REG_CLK_EN, int) + GENERATE_FIELD(TPC_CLK_EN, int) + GENERATE_FIELD(SQ_TP_WAKEUP, int) +END_REGISTER(TPC_DEBUG0) + +START_REGISTER(TPC_DEBUG1) + GENERATE_FIELD(UNUSED, int) +END_REGISTER(TPC_DEBUG1) + +START_REGISTER(TPC_CHICKEN) + GENERATE_FIELD(BLEND_PRECISION, int) + GENERATE_FIELD(SPARE, int) +END_REGISTER(TPC_CHICKEN) + +START_REGISTER(TP0_CNTL_STATUS) + GENERATE_FIELD(TP_INPUT_BUSY, int) + GENERATE_FIELD(TP_LOD_BUSY, int) + GENERATE_FIELD(TP_LOD_FIFO_BUSY, int) + GENERATE_FIELD(TP_ADDR_BUSY, int) + GENERATE_FIELD(TP_ALIGN_FIFO_BUSY, int) + GENERATE_FIELD(TP_ALIGNER_BUSY, int) + GENERATE_FIELD(TP_TC_FIFO_BUSY, int) + GENERATE_FIELD(TP_RR_FIFO_BUSY, int) + GENERATE_FIELD(TP_FETCH_BUSY, int) + GENERATE_FIELD(TP_CH_BLEND_BUSY, int) + GENERATE_FIELD(TP_TT_BUSY, int) + GENERATE_FIELD(TP_HICOLOR_BUSY, int) + GENERATE_FIELD(TP_BLEND_BUSY, int) + GENERATE_FIELD(TP_OUT_FIFO_BUSY, int) + GENERATE_FIELD(TP_OUTPUT_BUSY, int) + GENERATE_FIELD(IN_LC_RTS, int) + GENERATE_FIELD(LC_LA_RTS, int) + GENERATE_FIELD(LA_FL_RTS, int) + GENERATE_FIELD(FL_TA_RTS, int) + GENERATE_FIELD(TA_FA_RTS, int) + GENERATE_FIELD(TA_FA_TT_RTS, int) + GENERATE_FIELD(FA_AL_RTS, int) + GENERATE_FIELD(FA_AL_TT_RTS, int) + GENERATE_FIELD(AL_TF_RTS, int) + GENERATE_FIELD(AL_TF_TT_RTS, int) + GENERATE_FIELD(TF_TB_RTS, int) + GENERATE_FIELD(TF_TB_TT_RTS, int) + GENERATE_FIELD(TB_TT_RTS, int) + GENERATE_FIELD(TB_TT_TT_RESET, int) + GENERATE_FIELD(TB_TO_RTS, int) + GENERATE_FIELD(TP_BUSY, int) +END_REGISTER(TP0_CNTL_STATUS) + +START_REGISTER(TP0_DEBUG) + GENERATE_FIELD(Q_LOD_CNTL, int) + GENERATE_FIELD(Q_SQ_TP_WAKEUP, int) + GENERATE_FIELD(FL_TA_ADDRESSER_CNTL, int) + GENERATE_FIELD(REG_CLK_EN, int) + GENERATE_FIELD(PERF_CLK_EN, int) + GENERATE_FIELD(TP_CLK_EN, int) + GENERATE_FIELD(Q_WALKER_CNTL, int) + GENERATE_FIELD(Q_ALIGNER_CNTL, int) +END_REGISTER(TP0_DEBUG) + +START_REGISTER(TP0_CHICKEN) + GENERATE_FIELD(TT_MODE, int) + GENERATE_FIELD(VFETCH_ADDRESS_MODE, int) + GENERATE_FIELD(SPARE, int) +END_REGISTER(TP0_CHICKEN) + +START_REGISTER(TP0_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TP_PERFCOUNT_SELECT) +END_REGISTER(TP0_PERFCOUNTER0_SELECT) + +START_REGISTER(TP0_PERFCOUNTER0_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TP0_PERFCOUNTER0_HI) + +START_REGISTER(TP0_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TP0_PERFCOUNTER0_LOW) + +START_REGISTER(TP0_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, int) +END_REGISTER(TP0_PERFCOUNTER1_SELECT) + +START_REGISTER(TP0_PERFCOUNTER1_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TP0_PERFCOUNTER1_HI) + +START_REGISTER(TP0_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TP0_PERFCOUNTER1_LOW) + +START_REGISTER(TCM_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCM_PERFCOUNT_SELECT) +END_REGISTER(TCM_PERFCOUNTER0_SELECT) + +START_REGISTER(TCM_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCM_PERFCOUNT_SELECT) +END_REGISTER(TCM_PERFCOUNTER1_SELECT) + +START_REGISTER(TCM_PERFCOUNTER0_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCM_PERFCOUNTER0_HI) + +START_REGISTER(TCM_PERFCOUNTER1_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCM_PERFCOUNTER1_HI) + +START_REGISTER(TCM_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCM_PERFCOUNTER0_LOW) + +START_REGISTER(TCM_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCM_PERFCOUNTER1_LOW) + +START_REGISTER(TCF_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER0_SELECT) + +START_REGISTER(TCF_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER1_SELECT) + +START_REGISTER(TCF_PERFCOUNTER2_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER2_SELECT) + +START_REGISTER(TCF_PERFCOUNTER3_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER3_SELECT) + +START_REGISTER(TCF_PERFCOUNTER4_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER4_SELECT) + +START_REGISTER(TCF_PERFCOUNTER5_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER5_SELECT) + +START_REGISTER(TCF_PERFCOUNTER6_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER6_SELECT) + +START_REGISTER(TCF_PERFCOUNTER7_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER7_SELECT) + +START_REGISTER(TCF_PERFCOUNTER8_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER8_SELECT) + +START_REGISTER(TCF_PERFCOUNTER9_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER9_SELECT) + +START_REGISTER(TCF_PERFCOUNTER10_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER10_SELECT) + +START_REGISTER(TCF_PERFCOUNTER11_SELECT) + GENERATE_FIELD(PERFCOUNTER_SELECT, TCF_PERFCOUNT_SELECT) +END_REGISTER(TCF_PERFCOUNTER11_SELECT) + +START_REGISTER(TCF_PERFCOUNTER0_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER0_HI) + +START_REGISTER(TCF_PERFCOUNTER1_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER1_HI) + +START_REGISTER(TCF_PERFCOUNTER2_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER2_HI) + +START_REGISTER(TCF_PERFCOUNTER3_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER3_HI) + +START_REGISTER(TCF_PERFCOUNTER4_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER4_HI) + +START_REGISTER(TCF_PERFCOUNTER5_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER5_HI) + +START_REGISTER(TCF_PERFCOUNTER6_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER6_HI) + +START_REGISTER(TCF_PERFCOUNTER7_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER7_HI) + +START_REGISTER(TCF_PERFCOUNTER8_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER8_HI) + +START_REGISTER(TCF_PERFCOUNTER9_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER9_HI) + +START_REGISTER(TCF_PERFCOUNTER10_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER10_HI) + +START_REGISTER(TCF_PERFCOUNTER11_HI) + GENERATE_FIELD(PERFCOUNTER_HI, int) +END_REGISTER(TCF_PERFCOUNTER11_HI) + +START_REGISTER(TCF_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER0_LOW) + +START_REGISTER(TCF_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER1_LOW) + +START_REGISTER(TCF_PERFCOUNTER2_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER2_LOW) + +START_REGISTER(TCF_PERFCOUNTER3_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER3_LOW) + +START_REGISTER(TCF_PERFCOUNTER4_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER4_LOW) + +START_REGISTER(TCF_PERFCOUNTER5_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER5_LOW) + +START_REGISTER(TCF_PERFCOUNTER6_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER6_LOW) + +START_REGISTER(TCF_PERFCOUNTER7_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER7_LOW) + +START_REGISTER(TCF_PERFCOUNTER8_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER8_LOW) + +START_REGISTER(TCF_PERFCOUNTER9_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER9_LOW) + +START_REGISTER(TCF_PERFCOUNTER10_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER10_LOW) + +START_REGISTER(TCF_PERFCOUNTER11_LOW) + GENERATE_FIELD(PERFCOUNTER_LOW, int) +END_REGISTER(TCF_PERFCOUNTER11_LOW) + +START_REGISTER(TCF_DEBUG) + GENERATE_FIELD(not_MH_TC_rtr, int) + GENERATE_FIELD(TC_MH_send, int) + GENERATE_FIELD(not_FG0_rtr, int) + GENERATE_FIELD(not_TCB_TCO_rtr, int) + GENERATE_FIELD(TCB_ff_stall, int) + GENERATE_FIELD(TCB_miss_stall, int) + GENERATE_FIELD(TCA_TCB_stall, int) + GENERATE_FIELD(PF0_stall, int) + GENERATE_FIELD(TP0_full, int) + GENERATE_FIELD(TPC_full, int) + GENERATE_FIELD(not_TPC_rtr, int) + GENERATE_FIELD(tca_state_rts, int) + GENERATE_FIELD(tca_rts, int) +END_REGISTER(TCF_DEBUG) + +START_REGISTER(TCA_FIFO_DEBUG) + GENERATE_FIELD(tp0_full, int) + GENERATE_FIELD(tpc_full, int) + GENERATE_FIELD(load_tpc_fifo, int) + GENERATE_FIELD(load_tp_fifos, int) + GENERATE_FIELD(FW_full, int) + GENERATE_FIELD(not_FW_rtr0, int) + GENERATE_FIELD(FW_rts0, int) + GENERATE_FIELD(not_FW_tpc_rtr, int) + GENERATE_FIELD(FW_tpc_rts, int) +END_REGISTER(TCA_FIFO_DEBUG) + +START_REGISTER(TCA_PROBE_DEBUG) + GENERATE_FIELD(ProbeFilter_stall, int) +END_REGISTER(TCA_PROBE_DEBUG) + +START_REGISTER(TCA_TPC_DEBUG) + GENERATE_FIELD(captue_state_rts, int) + GENERATE_FIELD(capture_tca_rts, int) +END_REGISTER(TCA_TPC_DEBUG) + +START_REGISTER(TCB_CORE_DEBUG) + GENERATE_FIELD(access512, int) + GENERATE_FIELD(tiled, int) + GENERATE_FIELD(opcode, int) + GENERATE_FIELD(format, int) + GENERATE_FIELD(sector_format, int) + GENERATE_FIELD(sector_format512, int) +END_REGISTER(TCB_CORE_DEBUG) + +START_REGISTER(TCB_TAG0_DEBUG) + GENERATE_FIELD(mem_read_cycle, int) + GENERATE_FIELD(tag_access_cycle, int) + GENERATE_FIELD(miss_stall, int) + GENERATE_FIELD(num_feee_lines, int) + GENERATE_FIELD(max_misses, int) +END_REGISTER(TCB_TAG0_DEBUG) + +START_REGISTER(TCB_TAG1_DEBUG) + GENERATE_FIELD(mem_read_cycle, int) + GENERATE_FIELD(tag_access_cycle, int) + GENERATE_FIELD(miss_stall, int) + GENERATE_FIELD(num_feee_lines, int) + GENERATE_FIELD(max_misses, int) +END_REGISTER(TCB_TAG1_DEBUG) + +START_REGISTER(TCB_TAG2_DEBUG) + GENERATE_FIELD(mem_read_cycle, int) + GENERATE_FIELD(tag_access_cycle, int) + GENERATE_FIELD(miss_stall, int) + GENERATE_FIELD(num_feee_lines, int) + GENERATE_FIELD(max_misses, int) +END_REGISTER(TCB_TAG2_DEBUG) + +START_REGISTER(TCB_TAG3_DEBUG) + GENERATE_FIELD(mem_read_cycle, int) + GENERATE_FIELD(tag_access_cycle, int) + GENERATE_FIELD(miss_stall, int) + GENERATE_FIELD(num_feee_lines, int) + GENERATE_FIELD(max_misses, int) +END_REGISTER(TCB_TAG3_DEBUG) + +START_REGISTER(TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG) + GENERATE_FIELD(left_done, int) + GENERATE_FIELD(fg0_sends_left, int) + GENERATE_FIELD(one_sector_to_go_left_q, int) + GENERATE_FIELD(no_sectors_to_go, int) + GENERATE_FIELD(update_left, int) + GENERATE_FIELD(sector_mask_left_count_q, int) + GENERATE_FIELD(sector_mask_left_q, int) + GENERATE_FIELD(valid_left_q, int) +END_REGISTER(TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG) + +START_REGISTER(TCB_FETCH_GEN_WALKER_DEBUG) + GENERATE_FIELD(quad_sel_left, int) + GENERATE_FIELD(set_sel_left, int) + GENERATE_FIELD(right_eq_left, int) + GENERATE_FIELD(ff_fg_type512, int) + GENERATE_FIELD(busy, int) + GENERATE_FIELD(setquads_to_send, int) +END_REGISTER(TCB_FETCH_GEN_WALKER_DEBUG) + +START_REGISTER(TCB_FETCH_GEN_PIPE0_DEBUG) + GENERATE_FIELD(tc0_arb_rts, int) + GENERATE_FIELD(ga_out_rts, int) + GENERATE_FIELD(tc_arb_format, int) + GENERATE_FIELD(tc_arb_fmsopcode, int) + GENERATE_FIELD(tc_arb_request_type, int) + GENERATE_FIELD(busy, int) + GENERATE_FIELD(fgo_busy, int) + GENERATE_FIELD(ga_busy, int) + GENERATE_FIELD(mc_sel_q, int) + GENERATE_FIELD(valid_q, int) + GENERATE_FIELD(arb_RTR, int) +END_REGISTER(TCB_FETCH_GEN_PIPE0_DEBUG) + +START_REGISTER(TCD_INPUT0_DEBUG) + GENERATE_FIELD(empty, int) + GENERATE_FIELD(full, int) + GENERATE_FIELD(valid_q1, int) + GENERATE_FIELD(cnt_q1, int) + GENERATE_FIELD(last_send_q1, int) + GENERATE_FIELD(ip_send, int) + GENERATE_FIELD(ipbuf_dxt_send, int) + GENERATE_FIELD(ipbuf_busy, int) +END_REGISTER(TCD_INPUT0_DEBUG) + +START_REGISTER(TCD_DEGAMMA_DEBUG) + GENERATE_FIELD(dgmm_ftfconv_dgmmen, int) + GENERATE_FIELD(dgmm_ctrl_dgmm8, int) + GENERATE_FIELD(dgmm_ctrl_last_send, int) + GENERATE_FIELD(dgmm_ctrl_send, int) + GENERATE_FIELD(dgmm_stall, int) + GENERATE_FIELD(dgmm_pstate, int) +END_REGISTER(TCD_DEGAMMA_DEBUG) + +START_REGISTER(TCD_DXTMUX_SCTARB_DEBUG) + GENERATE_FIELD(pstate, int) + GENERATE_FIELD(sctrmx_rtr, int) + GENERATE_FIELD(dxtc_rtr, int) + GENERATE_FIELD(sctrarb_multcyl_send, int) + GENERATE_FIELD(sctrmx0_sctrarb_rts, int) + GENERATE_FIELD(dxtc_sctrarb_send, int) + GENERATE_FIELD(dxtc_dgmmpd_last_send, int) + GENERATE_FIELD(dxtc_dgmmpd_send, int) + GENERATE_FIELD(dcmp_mux_send, int) +END_REGISTER(TCD_DXTMUX_SCTARB_DEBUG) + +START_REGISTER(TCD_DXTC_ARB_DEBUG) + GENERATE_FIELD(n0_stall, int) + GENERATE_FIELD(pstate, int) + GENERATE_FIELD(arb_dcmp01_last_send, int) + GENERATE_FIELD(arb_dcmp01_cnt, int) + GENERATE_FIELD(arb_dcmp01_sector, int) + GENERATE_FIELD(arb_dcmp01_cacheline, int) + GENERATE_FIELD(arb_dcmp01_format, int) + GENERATE_FIELD(arb_dcmp01_send, int) + GENERATE_FIELD(n0_dxt2_4_types, int) +END_REGISTER(TCD_DXTC_ARB_DEBUG) + +START_REGISTER(TCD_STALLS_DEBUG) + GENERATE_FIELD(not_multcyl_sctrarb_rtr, int) + GENERATE_FIELD(not_sctrmx0_sctrarb_rtr, int) + GENERATE_FIELD(not_dcmp0_arb_rtr, int) + GENERATE_FIELD(not_dgmmpd_dxtc_rtr, int) + GENERATE_FIELD(not_mux_dcmp_rtr, int) + GENERATE_FIELD(not_incoming_rtr, int) +END_REGISTER(TCD_STALLS_DEBUG) + +START_REGISTER(TCO_STALLS_DEBUG) + GENERATE_FIELD(quad0_sg_crd_RTR, int) + GENERATE_FIELD(quad0_rl_sg_RTR, int) + GENERATE_FIELD(quad0_TCO_TCB_rtr_d, int) +END_REGISTER(TCO_STALLS_DEBUG) + +START_REGISTER(TCO_QUAD0_DEBUG0) + GENERATE_FIELD(rl_sg_sector_format, int) + GENERATE_FIELD(rl_sg_end_of_sample, int) + GENERATE_FIELD(rl_sg_rtr, int) + GENERATE_FIELD(rl_sg_rts, int) + GENERATE_FIELD(sg_crd_end_of_sample, int) + GENERATE_FIELD(sg_crd_rtr, int) + GENERATE_FIELD(sg_crd_rts, int) + GENERATE_FIELD(stageN1_valid_q, int) + GENERATE_FIELD(read_cache_q, int) + GENERATE_FIELD(cache_read_RTR, int) + GENERATE_FIELD(all_sectors_written_set3, int) + GENERATE_FIELD(all_sectors_written_set2, int) + GENERATE_FIELD(all_sectors_written_set1, int) + GENERATE_FIELD(all_sectors_written_set0, int) + GENERATE_FIELD(busy, int) +END_REGISTER(TCO_QUAD0_DEBUG0) + +START_REGISTER(TCO_QUAD0_DEBUG1) + GENERATE_FIELD(fifo_busy, int) + GENERATE_FIELD(empty, int) + GENERATE_FIELD(full, int) + GENERATE_FIELD(write_enable, int) + GENERATE_FIELD(fifo_write_ptr, int) + GENERATE_FIELD(fifo_read_ptr, int) + GENERATE_FIELD(cache_read_busy, int) + GENERATE_FIELD(latency_fifo_busy, int) + GENERATE_FIELD(input_quad_busy, int) + GENERATE_FIELD(tco_quad_pipe_busy, int) + GENERATE_FIELD(TCB_TCO_rtr_d, int) + GENERATE_FIELD(TCB_TCO_xfc_q, int) + GENERATE_FIELD(rl_sg_rtr, int) + GENERATE_FIELD(rl_sg_rts, int) + GENERATE_FIELD(sg_crd_rtr, int) + GENERATE_FIELD(sg_crd_rts, int) + GENERATE_FIELD(TCO_TCB_read_xfc, int) +END_REGISTER(TCO_QUAD0_DEBUG1) + +START_REGISTER(SQ_GPR_MANAGEMENT) + GENERATE_FIELD(REG_DYNAMIC, int) + GENERATE_FIELD(REG_SIZE_PIX, int) + GENERATE_FIELD(REG_SIZE_VTX, int) +END_REGISTER(SQ_GPR_MANAGEMENT) + +START_REGISTER(SQ_FLOW_CONTROL) + GENERATE_FIELD(INPUT_ARBITRATION_POLICY, int) + GENERATE_FIELD(ONE_THREAD, int) + GENERATE_FIELD(ONE_ALU, int) + GENERATE_FIELD(CF_WR_BASE, hex) + GENERATE_FIELD(NO_PV_PS, int) + GENERATE_FIELD(NO_LOOP_EXIT, int) + GENERATE_FIELD(NO_CEXEC_OPTIMIZE, int) + GENERATE_FIELD(TEXTURE_ARBITRATION_POLICY, int) + GENERATE_FIELD(VC_ARBITRATION_POLICY, int) + GENERATE_FIELD(ALU_ARBITRATION_POLICY, int) + GENERATE_FIELD(NO_ARB_EJECT, int) + GENERATE_FIELD(NO_CFS_EJECT, int) + GENERATE_FIELD(POS_EXP_PRIORITY, int) + GENERATE_FIELD(NO_EARLY_THREAD_TERMINATION, int) + GENERATE_FIELD(PS_PREFETCH_COLOR_ALLOC, int) +END_REGISTER(SQ_FLOW_CONTROL) + +START_REGISTER(SQ_INST_STORE_MANAGMENT) + GENERATE_FIELD(INST_BASE_PIX, int) + GENERATE_FIELD(INST_BASE_VTX, int) +END_REGISTER(SQ_INST_STORE_MANAGMENT) + +START_REGISTER(SQ_RESOURCE_MANAGMENT) + GENERATE_FIELD(VTX_THREAD_BUF_ENTRIES, int) + GENERATE_FIELD(PIX_THREAD_BUF_ENTRIES, int) + GENERATE_FIELD(EXPORT_BUF_ENTRIES, int) +END_REGISTER(SQ_RESOURCE_MANAGMENT) + +START_REGISTER(SQ_EO_RT) + GENERATE_FIELD(EO_CONSTANTS_RT, int) + GENERATE_FIELD(EO_TSTATE_RT, int) +END_REGISTER(SQ_EO_RT) + +START_REGISTER(SQ_DEBUG_MISC) + GENERATE_FIELD(DB_ALUCST_SIZE, int) + GENERATE_FIELD(DB_TSTATE_SIZE, int) + GENERATE_FIELD(DB_READ_CTX, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(DB_READ_MEMORY, int) + GENERATE_FIELD(DB_WEN_MEMORY_0, int) + GENERATE_FIELD(DB_WEN_MEMORY_1, int) + GENERATE_FIELD(DB_WEN_MEMORY_2, int) + GENERATE_FIELD(DB_WEN_MEMORY_3, int) +END_REGISTER(SQ_DEBUG_MISC) + +START_REGISTER(SQ_ACTIVITY_METER_CNTL) + GENERATE_FIELD(TIMEBASE, int) + GENERATE_FIELD(THRESHOLD_LOW, int) + GENERATE_FIELD(THRESHOLD_HIGH, int) + GENERATE_FIELD(SPARE, int) +END_REGISTER(SQ_ACTIVITY_METER_CNTL) + +START_REGISTER(SQ_ACTIVITY_METER_STATUS) + GENERATE_FIELD(PERCENT_BUSY, int) +END_REGISTER(SQ_ACTIVITY_METER_STATUS) + +START_REGISTER(SQ_INPUT_ARB_PRIORITY) + GENERATE_FIELD(PC_AVAIL_WEIGHT, int) + GENERATE_FIELD(PC_AVAIL_SIGN, int) + GENERATE_FIELD(SX_AVAIL_WEIGHT, int) + GENERATE_FIELD(SX_AVAIL_SIGN, int) + GENERATE_FIELD(THRESHOLD, int) +END_REGISTER(SQ_INPUT_ARB_PRIORITY) + +START_REGISTER(SQ_THREAD_ARB_PRIORITY) + GENERATE_FIELD(PC_AVAIL_WEIGHT, int) + GENERATE_FIELD(PC_AVAIL_SIGN, int) + GENERATE_FIELD(SX_AVAIL_WEIGHT, int) + GENERATE_FIELD(SX_AVAIL_SIGN, int) + GENERATE_FIELD(THRESHOLD, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(VS_PRIORITIZE_SERIAL, int) + GENERATE_FIELD(PS_PRIORITIZE_SERIAL, int) + GENERATE_FIELD(USE_SERIAL_COUNT_THRESHOLD, int) +END_REGISTER(SQ_THREAD_ARB_PRIORITY) + +START_REGISTER(SQ_VS_WATCHDOG_TIMER) + GENERATE_FIELD(ENABLE, int) + GENERATE_FIELD(TIMEOUT_COUNT, int) +END_REGISTER(SQ_VS_WATCHDOG_TIMER) + +START_REGISTER(SQ_PS_WATCHDOG_TIMER) + GENERATE_FIELD(ENABLE, int) + GENERATE_FIELD(TIMEOUT_COUNT, int) +END_REGISTER(SQ_PS_WATCHDOG_TIMER) + +START_REGISTER(SQ_INT_CNTL) + GENERATE_FIELD(PS_WATCHDOG_MASK, int) + GENERATE_FIELD(VS_WATCHDOG_MASK, int) +END_REGISTER(SQ_INT_CNTL) + +START_REGISTER(SQ_INT_STATUS) + GENERATE_FIELD(PS_WATCHDOG_TIMEOUT, int) + GENERATE_FIELD(VS_WATCHDOG_TIMEOUT, int) +END_REGISTER(SQ_INT_STATUS) + +START_REGISTER(SQ_INT_ACK) + GENERATE_FIELD(PS_WATCHDOG_ACK, int) + GENERATE_FIELD(VS_WATCHDOG_ACK, int) +END_REGISTER(SQ_INT_ACK) + +START_REGISTER(SQ_DEBUG_INPUT_FSM) + GENERATE_FIELD(VC_VSR_LD, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(VC_GPR_LD, int) + GENERATE_FIELD(PC_PISM, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(PC_AS, int) + GENERATE_FIELD(PC_INTERP_CNT, int) + GENERATE_FIELD(PC_GPR_SIZE, int) +END_REGISTER(SQ_DEBUG_INPUT_FSM) + +START_REGISTER(SQ_DEBUG_CONST_MGR_FSM) + GENERATE_FIELD(TEX_CONST_EVENT_STATE, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(ALU_CONST_EVENT_STATE, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(ALU_CONST_CNTX_VALID, int) + GENERATE_FIELD(TEX_CONST_CNTX_VALID, int) + GENERATE_FIELD(CNTX0_VTX_EVENT_DONE, int) + GENERATE_FIELD(CNTX0_PIX_EVENT_DONE, int) + GENERATE_FIELD(CNTX1_VTX_EVENT_DONE, int) + GENERATE_FIELD(CNTX1_PIX_EVENT_DONE, int) +END_REGISTER(SQ_DEBUG_CONST_MGR_FSM) + +START_REGISTER(SQ_DEBUG_TP_FSM) + GENERATE_FIELD(EX_TP, int) + GENERATE_FIELD(RESERVED0, int) + GENERATE_FIELD(CF_TP, int) + GENERATE_FIELD(IF_TP, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(TIS_TP, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(GS_TP, int) + GENERATE_FIELD(RESERVED3, int) + GENERATE_FIELD(FCR_TP, int) + GENERATE_FIELD(RESERVED4, int) + GENERATE_FIELD(FCS_TP, int) + GENERATE_FIELD(RESERVED5, int) + GENERATE_FIELD(ARB_TR_TP, int) +END_REGISTER(SQ_DEBUG_TP_FSM) + +START_REGISTER(SQ_DEBUG_FSM_ALU_0) + GENERATE_FIELD(EX_ALU_0, int) + GENERATE_FIELD(RESERVED0, int) + GENERATE_FIELD(CF_ALU_0, int) + GENERATE_FIELD(IF_ALU_0, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(DU1_ALU_0, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(DU0_ALU_0, int) + GENERATE_FIELD(RESERVED3, int) + GENERATE_FIELD(AIS_ALU_0, int) + GENERATE_FIELD(RESERVED4, int) + GENERATE_FIELD(ACS_ALU_0, int) + GENERATE_FIELD(RESERVED5, int) + GENERATE_FIELD(ARB_TR_ALU, int) +END_REGISTER(SQ_DEBUG_FSM_ALU_0) + +START_REGISTER(SQ_DEBUG_FSM_ALU_1) + GENERATE_FIELD(EX_ALU_0, int) + GENERATE_FIELD(RESERVED0, int) + GENERATE_FIELD(CF_ALU_0, int) + GENERATE_FIELD(IF_ALU_0, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(DU1_ALU_0, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(DU0_ALU_0, int) + GENERATE_FIELD(RESERVED3, int) + GENERATE_FIELD(AIS_ALU_0, int) + GENERATE_FIELD(RESERVED4, int) + GENERATE_FIELD(ACS_ALU_0, int) + GENERATE_FIELD(RESERVED5, int) + GENERATE_FIELD(ARB_TR_ALU, int) +END_REGISTER(SQ_DEBUG_FSM_ALU_1) + +START_REGISTER(SQ_DEBUG_EXP_ALLOC) + GENERATE_FIELD(POS_BUF_AVAIL, int) + GENERATE_FIELD(COLOR_BUF_AVAIL, int) + GENERATE_FIELD(EA_BUF_AVAIL, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(ALLOC_TBL_BUF_AVAIL, int) +END_REGISTER(SQ_DEBUG_EXP_ALLOC) + +START_REGISTER(SQ_DEBUG_PTR_BUFF) + GENERATE_FIELD(END_OF_BUFFER, int) + GENERATE_FIELD(DEALLOC_CNT, int) + GENERATE_FIELD(QUAL_NEW_VECTOR, int) + GENERATE_FIELD(EVENT_CONTEXT_ID, int) + GENERATE_FIELD(SC_EVENT_ID, int) + GENERATE_FIELD(QUAL_EVENT, int) + GENERATE_FIELD(PRIM_TYPE_POLYGON, int) + GENERATE_FIELD(EF_EMPTY, int) + GENERATE_FIELD(VTX_SYNC_CNT, int) +END_REGISTER(SQ_DEBUG_PTR_BUFF) + +START_REGISTER(SQ_DEBUG_GPR_VTX) + GENERATE_FIELD(VTX_TAIL_PTR, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(VTX_HEAD_PTR, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(VTX_MAX, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(VTX_FREE, int) +END_REGISTER(SQ_DEBUG_GPR_VTX) + +START_REGISTER(SQ_DEBUG_GPR_PIX) + GENERATE_FIELD(PIX_TAIL_PTR, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(PIX_HEAD_PTR, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(PIX_MAX, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(PIX_FREE, int) +END_REGISTER(SQ_DEBUG_GPR_PIX) + +START_REGISTER(SQ_DEBUG_TB_STATUS_SEL) + GENERATE_FIELD(VTX_TB_STATUS_REG_SEL, int) + GENERATE_FIELD(VTX_TB_STATE_MEM_DW_SEL, int) + GENERATE_FIELD(VTX_TB_STATE_MEM_RD_ADDR, int) + GENERATE_FIELD(VTX_TB_STATE_MEM_RD_EN, int) + GENERATE_FIELD(PIX_TB_STATE_MEM_RD_EN, int) + GENERATE_FIELD(DEBUG_BUS_TRIGGER_SEL, int) + GENERATE_FIELD(PIX_TB_STATUS_REG_SEL, int) + GENERATE_FIELD(PIX_TB_STATE_MEM_DW_SEL, int) + GENERATE_FIELD(PIX_TB_STATE_MEM_RD_ADDR, int) + GENERATE_FIELD(VC_THREAD_BUF_DLY, int) + GENERATE_FIELD(DISABLE_STRICT_CTX_SYNC, int) +END_REGISTER(SQ_DEBUG_TB_STATUS_SEL) + +START_REGISTER(SQ_DEBUG_VTX_TB_0) + GENERATE_FIELD(VTX_HEAD_PTR_Q, int) + GENERATE_FIELD(TAIL_PTR_Q, int) + GENERATE_FIELD(FULL_CNT_Q, int) + GENERATE_FIELD(NXT_POS_ALLOC_CNT, int) + GENERATE_FIELD(NXT_PC_ALLOC_CNT, int) + GENERATE_FIELD(SX_EVENT_FULL, int) + GENERATE_FIELD(BUSY_Q, int) +END_REGISTER(SQ_DEBUG_VTX_TB_0) + +START_REGISTER(SQ_DEBUG_VTX_TB_1) + GENERATE_FIELD(VS_DONE_PTR, int) +END_REGISTER(SQ_DEBUG_VTX_TB_1) + +START_REGISTER(SQ_DEBUG_VTX_TB_STATUS_REG) + GENERATE_FIELD(VS_STATUS_REG, int) +END_REGISTER(SQ_DEBUG_VTX_TB_STATUS_REG) + +START_REGISTER(SQ_DEBUG_VTX_TB_STATE_MEM) + GENERATE_FIELD(VS_STATE_MEM, int) +END_REGISTER(SQ_DEBUG_VTX_TB_STATE_MEM) + +START_REGISTER(SQ_DEBUG_PIX_TB_0) + GENERATE_FIELD(PIX_HEAD_PTR, int) + GENERATE_FIELD(TAIL_PTR, int) + GENERATE_FIELD(FULL_CNT, int) + GENERATE_FIELD(NXT_PIX_ALLOC_CNT, int) + GENERATE_FIELD(NXT_PIX_EXP_CNT, int) + GENERATE_FIELD(BUSY, int) +END_REGISTER(SQ_DEBUG_PIX_TB_0) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_0) + GENERATE_FIELD(PIX_TB_STATUS_REG_0, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_0) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_1) + GENERATE_FIELD(PIX_TB_STATUS_REG_1, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_1) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_2) + GENERATE_FIELD(PIX_TB_STATUS_REG_2, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_2) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_3) + GENERATE_FIELD(PIX_TB_STATUS_REG_3, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATUS_REG_3) + +START_REGISTER(SQ_DEBUG_PIX_TB_STATE_MEM) + GENERATE_FIELD(PIX_TB_STATE_MEM, int) +END_REGISTER(SQ_DEBUG_PIX_TB_STATE_MEM) + +START_REGISTER(SQ_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, SQ_PERFCNT_SELECT) +END_REGISTER(SQ_PERFCOUNTER0_SELECT) + +START_REGISTER(SQ_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(SQ_PERFCOUNTER1_SELECT) + +START_REGISTER(SQ_PERFCOUNTER2_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(SQ_PERFCOUNTER2_SELECT) + +START_REGISTER(SQ_PERFCOUNTER3_SELECT) + GENERATE_FIELD(PERF_SEL, int) +END_REGISTER(SQ_PERFCOUNTER3_SELECT) + +START_REGISTER(SQ_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER0_LOW) + +START_REGISTER(SQ_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER0_HI) + +START_REGISTER(SQ_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER1_LOW) + +START_REGISTER(SQ_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER1_HI) + +START_REGISTER(SQ_PERFCOUNTER2_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER2_LOW) + +START_REGISTER(SQ_PERFCOUNTER2_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER2_HI) + +START_REGISTER(SQ_PERFCOUNTER3_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER3_LOW) + +START_REGISTER(SQ_PERFCOUNTER3_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SQ_PERFCOUNTER3_HI) + +START_REGISTER(SX_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, SX_PERFCNT_SELECT) +END_REGISTER(SX_PERFCOUNTER0_SELECT) + +START_REGISTER(SX_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SX_PERFCOUNTER0_LOW) + +START_REGISTER(SX_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(SX_PERFCOUNTER0_HI) + +START_REGISTER(SQ_INSTRUCTION_ALU_0) + GENERATE_FIELD(VECTOR_RESULT, int) + GENERATE_FIELD(VECTOR_DST_REL, Abs_modifier) + GENERATE_FIELD(LOW_PRECISION_16B_FP, int) + GENERATE_FIELD(SCALAR_RESULT, int) + GENERATE_FIELD(SCALAR_DST_REL, int) + GENERATE_FIELD(EXPORT_DATA, Exporting) + GENERATE_FIELD(VECTOR_WRT_MSK, int) + GENERATE_FIELD(SCALAR_WRT_MSK, int) + GENERATE_FIELD(VECTOR_CLAMP, int) + GENERATE_FIELD(SCALAR_CLAMP, int) + GENERATE_FIELD(SCALAR_OPCODE, ScalarOpcode) +END_REGISTER(SQ_INSTRUCTION_ALU_0) + +START_REGISTER(SQ_INSTRUCTION_ALU_1) + GENERATE_FIELD(SRC_C_SWIZZLE_R, SwizzleType) + GENERATE_FIELD(SRC_C_SWIZZLE_G, SwizzleType) + GENERATE_FIELD(SRC_C_SWIZZLE_B, SwizzleType) + GENERATE_FIELD(SRC_C_SWIZZLE_A, SwizzleType) + GENERATE_FIELD(SRC_B_SWIZZLE_R, SwizzleType) + GENERATE_FIELD(SRC_B_SWIZZLE_G, SwizzleType) + GENERATE_FIELD(SRC_B_SWIZZLE_B, SwizzleType) + GENERATE_FIELD(SRC_B_SWIZZLE_A, SwizzleType) + GENERATE_FIELD(SRC_A_SWIZZLE_R, SwizzleType) + GENERATE_FIELD(SRC_A_SWIZZLE_G, SwizzleType) + GENERATE_FIELD(SRC_A_SWIZZLE_B, SwizzleType) + GENERATE_FIELD(SRC_A_SWIZZLE_A, SwizzleType) + GENERATE_FIELD(SRC_C_ARG_MOD, InputModifier) + GENERATE_FIELD(SRC_B_ARG_MOD, InputModifier) + GENERATE_FIELD(SRC_A_ARG_MOD, InputModifier) + GENERATE_FIELD(PRED_SELECT, PredicateSelect) + GENERATE_FIELD(RELATIVE_ADDR, int) + GENERATE_FIELD(CONST_1_REL_ABS, int) + GENERATE_FIELD(CONST_0_REL_ABS, int) +END_REGISTER(SQ_INSTRUCTION_ALU_1) + +START_REGISTER(SQ_INSTRUCTION_ALU_2) + GENERATE_FIELD(SRC_C_REG_PTR, int) + GENERATE_FIELD(REG_SELECT_C, OperandSelect1) + GENERATE_FIELD(REG_ABS_MOD_C, Abs_modifier) + GENERATE_FIELD(SRC_B_REG_PTR, int) + GENERATE_FIELD(REG_SELECT_B, OperandSelect1) + GENERATE_FIELD(REG_ABS_MOD_B, Abs_modifier) + GENERATE_FIELD(SRC_A_REG_PTR, int) + GENERATE_FIELD(REG_SELECT_A, OperandSelect1) + GENERATE_FIELD(REG_ABS_MOD_A, Abs_modifier) + GENERATE_FIELD(VECTOR_OPCODE, VectorOpcode) + GENERATE_FIELD(SRC_C_SEL, OperandSelect0) + GENERATE_FIELD(SRC_B_SEL, OperandSelect0) + GENERATE_FIELD(SRC_A_SEL, OperandSelect0) +END_REGISTER(SQ_INSTRUCTION_ALU_2) + +START_REGISTER(SQ_INSTRUCTION_CF_EXEC_0) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(COUNT, int) + GENERATE_FIELD(YIELD, int) + GENERATE_FIELD(INST_TYPE_0, Ressource_type) + GENERATE_FIELD(INST_SERIAL_0, Instruction_serial) + GENERATE_FIELD(INST_TYPE_1, Ressource_type) + GENERATE_FIELD(INST_SERIAL_1, Instruction_serial) + GENERATE_FIELD(INST_TYPE_2, Ressource_type) + GENERATE_FIELD(INST_SERIAL_2, Instruction_serial) + GENERATE_FIELD(INST_TYPE_3, Ressource_type) + GENERATE_FIELD(INST_SERIAL_3, Instruction_serial) + GENERATE_FIELD(INST_TYPE_4, Ressource_type) + GENERATE_FIELD(INST_SERIAL_4, Instruction_serial) + GENERATE_FIELD(INST_TYPE_5, Ressource_type) + GENERATE_FIELD(INST_SERIAL_5, Instruction_serial) + GENERATE_FIELD(INST_VC_0, VC_type) + GENERATE_FIELD(INST_VC_1, VC_type) + GENERATE_FIELD(INST_VC_2, VC_type) + GENERATE_FIELD(INST_VC_3, VC_type) +END_REGISTER(SQ_INSTRUCTION_CF_EXEC_0) + +START_REGISTER(SQ_INSTRUCTION_CF_EXEC_1) + GENERATE_FIELD(INST_VC_4, VC_type) + GENERATE_FIELD(INST_VC_5, VC_type) + GENERATE_FIELD(BOOL_ADDR, int) + GENERATE_FIELD(CONDITION, int) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(COUNT, int) + GENERATE_FIELD(YIELD, int) +END_REGISTER(SQ_INSTRUCTION_CF_EXEC_1) + +START_REGISTER(SQ_INSTRUCTION_CF_EXEC_2) + GENERATE_FIELD(INST_TYPE_0, Ressource_type) + GENERATE_FIELD(INST_SERIAL_0, Instruction_serial) + GENERATE_FIELD(INST_TYPE_1, Ressource_type) + GENERATE_FIELD(INST_SERIAL_1, Instruction_serial) + GENERATE_FIELD(INST_TYPE_2, Ressource_type) + GENERATE_FIELD(INST_SERIAL_2, Instruction_serial) + GENERATE_FIELD(INST_TYPE_3, Ressource_type) + GENERATE_FIELD(INST_SERIAL_3, Instruction_serial) + GENERATE_FIELD(INST_TYPE_4, Ressource_type) + GENERATE_FIELD(INST_SERIAL_4, Instruction_serial) + GENERATE_FIELD(INST_TYPE_5, Ressource_type) + GENERATE_FIELD(INST_SERIAL_5, Instruction_serial) + GENERATE_FIELD(INST_VC_0, VC_type) + GENERATE_FIELD(INST_VC_1, VC_type) + GENERATE_FIELD(INST_VC_2, VC_type) + GENERATE_FIELD(INST_VC_3, VC_type) + GENERATE_FIELD(INST_VC_4, VC_type) + GENERATE_FIELD(INST_VC_5, VC_type) + GENERATE_FIELD(BOOL_ADDR, int) + GENERATE_FIELD(CONDITION, int) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(OPCODE, CFOpcode) +END_REGISTER(SQ_INSTRUCTION_CF_EXEC_2) + +START_REGISTER(SQ_INSTRUCTION_CF_LOOP_0) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(RESERVED_0, int) + GENERATE_FIELD(LOOP_ID, int) + GENERATE_FIELD(RESERVED_1, int) +END_REGISTER(SQ_INSTRUCTION_CF_LOOP_0) + +START_REGISTER(SQ_INSTRUCTION_CF_LOOP_1) + GENERATE_FIELD(RESERVED_0, int) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(RESERVED_1, int) +END_REGISTER(SQ_INSTRUCTION_CF_LOOP_1) + +START_REGISTER(SQ_INSTRUCTION_CF_LOOP_2) + GENERATE_FIELD(LOOP_ID, int) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(OPCODE, CFOpcode) +END_REGISTER(SQ_INSTRUCTION_CF_LOOP_2) + +START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_0) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(RESERVED_0, int) + GENERATE_FIELD(FORCE_CALL, int) + GENERATE_FIELD(PREDICATED_JMP, int) + GENERATE_FIELD(RESERVED_1, int) +END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_0) + +START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_1) + GENERATE_FIELD(RESERVED_0, int) + GENERATE_FIELD(DIRECTION, int) + GENERATE_FIELD(BOOL_ADDR, int) + GENERATE_FIELD(CONDITION, int) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(ADDRESS, int) + GENERATE_FIELD(RESERVED_1, int) + GENERATE_FIELD(FORCE_CALL, int) + GENERATE_FIELD(RESERVED_2, int) +END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_1) + +START_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_2) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(DIRECTION, int) + GENERATE_FIELD(BOOL_ADDR, int) + GENERATE_FIELD(CONDITION, int) + GENERATE_FIELD(ADDRESS_MODE, Addressing) + GENERATE_FIELD(OPCODE, CFOpcode) +END_REGISTER(SQ_INSTRUCTION_CF_JMP_CALL_2) + +START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_0) + GENERATE_FIELD(SIZE, int) + GENERATE_FIELD(RESERVED, int) +END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_0) + +START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_1) + GENERATE_FIELD(RESERVED_0, int) + GENERATE_FIELD(NO_SERIAL, int) + GENERATE_FIELD(BUFFER_SELECT, Allocation_type) + GENERATE_FIELD(ALLOC_MODE, int) + GENERATE_FIELD(OPCODE, CFOpcode) + GENERATE_FIELD(SIZE, int) + GENERATE_FIELD(RESERVED_1, int) +END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_1) + +START_REGISTER(SQ_INSTRUCTION_CF_ALLOC_2) + GENERATE_FIELD(RESERVED, int) + GENERATE_FIELD(NO_SERIAL, int) + GENERATE_FIELD(BUFFER_SELECT, Allocation_type) + GENERATE_FIELD(ALLOC_MODE, int) + GENERATE_FIELD(OPCODE, CFOpcode) +END_REGISTER(SQ_INSTRUCTION_CF_ALLOC_2) + +START_REGISTER(SQ_INSTRUCTION_TFETCH_0) + GENERATE_FIELD(OPCODE, TexInstOpcode) + GENERATE_FIELD(SRC_GPR, int) + GENERATE_FIELD(SRC_GPR_AM, Addressmode) + GENERATE_FIELD(DST_GPR, int) + GENERATE_FIELD(DST_GPR_AM, Addressmode) + GENERATE_FIELD(FETCH_VALID_ONLY, int) + GENERATE_FIELD(CONST_INDEX, int) + GENERATE_FIELD(TX_COORD_DENORM, TexCoordDenorm) + GENERATE_FIELD(SRC_SEL_X, SrcSel) + GENERATE_FIELD(SRC_SEL_Y, SrcSel) + GENERATE_FIELD(SRC_SEL_Z, SrcSel) +END_REGISTER(SQ_INSTRUCTION_TFETCH_0) + +START_REGISTER(SQ_INSTRUCTION_TFETCH_1) + GENERATE_FIELD(DST_SEL_X, DstSel) + GENERATE_FIELD(DST_SEL_Y, DstSel) + GENERATE_FIELD(DST_SEL_Z, DstSel) + GENERATE_FIELD(DST_SEL_W, DstSel) + GENERATE_FIELD(MAG_FILTER, MagFilter) + GENERATE_FIELD(MIN_FILTER, MinFilter) + GENERATE_FIELD(MIP_FILTER, MipFilter) + GENERATE_FIELD(ANISO_FILTER, AnisoFilter) + GENERATE_FIELD(ARBITRARY_FILTER, ArbitraryFilter) + GENERATE_FIELD(VOL_MAG_FILTER, VolMagFilter) + GENERATE_FIELD(VOL_MIN_FILTER, VolMinFilter) + GENERATE_FIELD(USE_COMP_LOD, int) + GENERATE_FIELD(USE_REG_LOD, int) + GENERATE_FIELD(PRED_SELECT, PredSelect) +END_REGISTER(SQ_INSTRUCTION_TFETCH_1) + +START_REGISTER(SQ_INSTRUCTION_TFETCH_2) + GENERATE_FIELD(USE_REG_GRADIENTS, int) + GENERATE_FIELD(SAMPLE_LOCATION, SampleLocation) + GENERATE_FIELD(LOD_BIAS, int) + GENERATE_FIELD(UNUSED, int) + GENERATE_FIELD(OFFSET_X, int) + GENERATE_FIELD(OFFSET_Y, int) + GENERATE_FIELD(OFFSET_Z, int) + GENERATE_FIELD(PRED_CONDITION, int) +END_REGISTER(SQ_INSTRUCTION_TFETCH_2) + +START_REGISTER(SQ_INSTRUCTION_VFETCH_0) + GENERATE_FIELD(OPCODE, int) + GENERATE_FIELD(SRC_GPR, int) + GENERATE_FIELD(SRC_GPR_AM, int) + GENERATE_FIELD(DST_GPR, int) + GENERATE_FIELD(DST_GPR_AM, int) + GENERATE_FIELD(MUST_BE_ONE, int) + GENERATE_FIELD(CONST_INDEX, int) + GENERATE_FIELD(CONST_INDEX_SEL, int) + GENERATE_FIELD(SRC_SEL, int) +END_REGISTER(SQ_INSTRUCTION_VFETCH_0) + +START_REGISTER(SQ_INSTRUCTION_VFETCH_1) + GENERATE_FIELD(DST_SEL_X, int) + GENERATE_FIELD(DST_SEL_Y, int) + GENERATE_FIELD(DST_SEL_Z, int) + GENERATE_FIELD(DST_SEL_W, int) + GENERATE_FIELD(FORMAT_COMP_ALL, int) + GENERATE_FIELD(NUM_FORMAT_ALL, int) + GENERATE_FIELD(SIGNED_RF_MODE_ALL, int) + GENERATE_FIELD(DATA_FORMAT, int) + GENERATE_FIELD(EXP_ADJUST_ALL, int) + GENERATE_FIELD(PRED_SELECT, int) +END_REGISTER(SQ_INSTRUCTION_VFETCH_1) + +START_REGISTER(SQ_INSTRUCTION_VFETCH_2) + GENERATE_FIELD(STRIDE, int) + GENERATE_FIELD(OFFSET, int) + GENERATE_FIELD(PRED_CONDITION, int) +END_REGISTER(SQ_INSTRUCTION_VFETCH_2) + +START_REGISTER(SQ_CONSTANT_0) + GENERATE_FIELD(RED, float) +END_REGISTER(SQ_CONSTANT_0) + +START_REGISTER(SQ_CONSTANT_1) + GENERATE_FIELD(GREEN, float) +END_REGISTER(SQ_CONSTANT_1) + +START_REGISTER(SQ_CONSTANT_2) + GENERATE_FIELD(BLUE, float) +END_REGISTER(SQ_CONSTANT_2) + +START_REGISTER(SQ_CONSTANT_3) + GENERATE_FIELD(ALPHA, float) +END_REGISTER(SQ_CONSTANT_3) + +START_REGISTER(SQ_FETCH_0) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_0) + +START_REGISTER(SQ_FETCH_1) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_1) + +START_REGISTER(SQ_FETCH_2) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_2) + +START_REGISTER(SQ_FETCH_3) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_3) + +START_REGISTER(SQ_FETCH_4) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_4) + +START_REGISTER(SQ_FETCH_5) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_5) + +START_REGISTER(SQ_CONSTANT_VFETCH_0) + GENERATE_FIELD(TYPE, int) + GENERATE_FIELD(STATE, int) + GENERATE_FIELD(BASE_ADDRESS, hex) +END_REGISTER(SQ_CONSTANT_VFETCH_0) + +START_REGISTER(SQ_CONSTANT_VFETCH_1) + GENERATE_FIELD(ENDIAN_SWAP, int) + GENERATE_FIELD(LIMIT_ADDRESS, hex) +END_REGISTER(SQ_CONSTANT_VFETCH_1) + +START_REGISTER(SQ_CONSTANT_T2) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_CONSTANT_T2) + +START_REGISTER(SQ_CONSTANT_T3) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_CONSTANT_T3) + +START_REGISTER(SQ_CF_BOOLEANS) + GENERATE_FIELD(CF_BOOLEANS_0, int) + GENERATE_FIELD(CF_BOOLEANS_1, int) + GENERATE_FIELD(CF_BOOLEANS_2, int) + GENERATE_FIELD(CF_BOOLEANS_3, int) +END_REGISTER(SQ_CF_BOOLEANS) + +START_REGISTER(SQ_CF_LOOP) + GENERATE_FIELD(CF_LOOP_COUNT, int) + GENERATE_FIELD(CF_LOOP_START, int) + GENERATE_FIELD(CF_LOOP_STEP, int) +END_REGISTER(SQ_CF_LOOP) + +START_REGISTER(SQ_CONSTANT_RT_0) + GENERATE_FIELD(RED, float) +END_REGISTER(SQ_CONSTANT_RT_0) + +START_REGISTER(SQ_CONSTANT_RT_1) + GENERATE_FIELD(GREEN, float) +END_REGISTER(SQ_CONSTANT_RT_1) + +START_REGISTER(SQ_CONSTANT_RT_2) + GENERATE_FIELD(BLUE, float) +END_REGISTER(SQ_CONSTANT_RT_2) + +START_REGISTER(SQ_CONSTANT_RT_3) + GENERATE_FIELD(ALPHA, float) +END_REGISTER(SQ_CONSTANT_RT_3) + +START_REGISTER(SQ_FETCH_RT_0) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_0) + +START_REGISTER(SQ_FETCH_RT_1) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_1) + +START_REGISTER(SQ_FETCH_RT_2) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_2) + +START_REGISTER(SQ_FETCH_RT_3) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_3) + +START_REGISTER(SQ_FETCH_RT_4) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_4) + +START_REGISTER(SQ_FETCH_RT_5) + GENERATE_FIELD(VALUE, int) +END_REGISTER(SQ_FETCH_RT_5) + +START_REGISTER(SQ_CF_RT_BOOLEANS) + GENERATE_FIELD(CF_BOOLEANS_0, int) + GENERATE_FIELD(CF_BOOLEANS_1, int) + GENERATE_FIELD(CF_BOOLEANS_2, int) + GENERATE_FIELD(CF_BOOLEANS_3, int) +END_REGISTER(SQ_CF_RT_BOOLEANS) + +START_REGISTER(SQ_CF_RT_LOOP) + GENERATE_FIELD(CF_LOOP_COUNT, int) + GENERATE_FIELD(CF_LOOP_START, int) + GENERATE_FIELD(CF_LOOP_STEP, int) +END_REGISTER(SQ_CF_RT_LOOP) + +START_REGISTER(SQ_VS_PROGRAM) + GENERATE_FIELD(BASE, int) + GENERATE_FIELD(SIZE, int) +END_REGISTER(SQ_VS_PROGRAM) + +START_REGISTER(SQ_PS_PROGRAM) + GENERATE_FIELD(BASE, int) + GENERATE_FIELD(SIZE, int) +END_REGISTER(SQ_PS_PROGRAM) + +START_REGISTER(SQ_CF_PROGRAM_SIZE) + GENERATE_FIELD(VS_CF_SIZE, int) + GENERATE_FIELD(PS_CF_SIZE, int) +END_REGISTER(SQ_CF_PROGRAM_SIZE) + +START_REGISTER(SQ_INTERPOLATOR_CNTL) + GENERATE_FIELD(PARAM_SHADE, ParamShade) + GENERATE_FIELD(SAMPLING_PATTERN, SamplingPattern) +END_REGISTER(SQ_INTERPOLATOR_CNTL) + +START_REGISTER(SQ_PROGRAM_CNTL) + GENERATE_FIELD(VS_NUM_REG, intMinusOne) + GENERATE_FIELD(PS_NUM_REG, intMinusOne) + GENERATE_FIELD(VS_RESOURCE, int) + GENERATE_FIELD(PS_RESOURCE, int) + GENERATE_FIELD(PARAM_GEN, int) + GENERATE_FIELD(GEN_INDEX_PIX, int) + GENERATE_FIELD(VS_EXPORT_COUNT, intMinusOne) + GENERATE_FIELD(VS_EXPORT_MODE, VertexMode) + GENERATE_FIELD(PS_EXPORT_MODE, int) + GENERATE_FIELD(GEN_INDEX_VTX, int) +END_REGISTER(SQ_PROGRAM_CNTL) + +START_REGISTER(SQ_WRAPPING_0) + GENERATE_FIELD(PARAM_WRAP_0, hex) + GENERATE_FIELD(PARAM_WRAP_1, hex) + GENERATE_FIELD(PARAM_WRAP_2, hex) + GENERATE_FIELD(PARAM_WRAP_3, hex) + GENERATE_FIELD(PARAM_WRAP_4, hex) + GENERATE_FIELD(PARAM_WRAP_5, hex) + GENERATE_FIELD(PARAM_WRAP_6, hex) + GENERATE_FIELD(PARAM_WRAP_7, hex) +END_REGISTER(SQ_WRAPPING_0) + +START_REGISTER(SQ_WRAPPING_1) + GENERATE_FIELD(PARAM_WRAP_8, hex) + GENERATE_FIELD(PARAM_WRAP_9, hex) + GENERATE_FIELD(PARAM_WRAP_10, hex) + GENERATE_FIELD(PARAM_WRAP_11, hex) + GENERATE_FIELD(PARAM_WRAP_12, hex) + GENERATE_FIELD(PARAM_WRAP_13, hex) + GENERATE_FIELD(PARAM_WRAP_14, hex) + GENERATE_FIELD(PARAM_WRAP_15, hex) +END_REGISTER(SQ_WRAPPING_1) + +START_REGISTER(SQ_VS_CONST) + GENERATE_FIELD(BASE, int) + GENERATE_FIELD(SIZE, int) +END_REGISTER(SQ_VS_CONST) + +START_REGISTER(SQ_PS_CONST) + GENERATE_FIELD(BASE, int) + GENERATE_FIELD(SIZE, int) +END_REGISTER(SQ_PS_CONST) + +START_REGISTER(SQ_CONTEXT_MISC) + GENERATE_FIELD(INST_PRED_OPTIMIZE, int) + GENERATE_FIELD(SC_OUTPUT_SCREEN_XY, int) + GENERATE_FIELD(SC_SAMPLE_CNTL, Sample_Cntl) + GENERATE_FIELD(PARAM_GEN_POS, int) + GENERATE_FIELD(PERFCOUNTER_REF, int) + GENERATE_FIELD(YEILD_OPTIMIZE, int) + GENERATE_FIELD(TX_CACHE_SEL, int) +END_REGISTER(SQ_CONTEXT_MISC) + +START_REGISTER(SQ_CF_RD_BASE) + GENERATE_FIELD(RD_BASE, hex) +END_REGISTER(SQ_CF_RD_BASE) + +START_REGISTER(SQ_DEBUG_MISC_0) + GENERATE_FIELD(DB_PROB_ON, int) + GENERATE_FIELD(DB_PROB_BREAK, int) + GENERATE_FIELD(DB_PROB_ADDR, int) + GENERATE_FIELD(DB_PROB_COUNT, int) +END_REGISTER(SQ_DEBUG_MISC_0) + +START_REGISTER(SQ_DEBUG_MISC_1) + GENERATE_FIELD(DB_ON_PIX, int) + GENERATE_FIELD(DB_ON_VTX, int) + GENERATE_FIELD(DB_INST_COUNT, int) + GENERATE_FIELD(DB_BREAK_ADDR, int) +END_REGISTER(SQ_DEBUG_MISC_1) + +START_REGISTER(MH_ARBITER_CONFIG) + GENERATE_FIELD(SAME_PAGE_LIMIT, int) + GENERATE_FIELD(SAME_PAGE_GRANULARITY, int) + GENERATE_FIELD(L1_ARB_ENABLE, bool) + GENERATE_FIELD(L1_ARB_HOLD_ENABLE, int) + GENERATE_FIELD(L2_ARB_CONTROL, int) + GENERATE_FIELD(PAGE_SIZE, int) + GENERATE_FIELD(TC_REORDER_ENABLE, bool) + GENERATE_FIELD(TC_ARB_HOLD_ENABLE, bool) + GENERATE_FIELD(IN_FLIGHT_LIMIT_ENABLE, bool) + GENERATE_FIELD(IN_FLIGHT_LIMIT, int) + GENERATE_FIELD(CP_CLNT_ENABLE, bool) + GENERATE_FIELD(VGT_CLNT_ENABLE, bool) + GENERATE_FIELD(TC_CLNT_ENABLE, bool) + GENERATE_FIELD(RB_CLNT_ENABLE, bool) + GENERATE_FIELD(PA_CLNT_ENABLE, bool) +END_REGISTER(MH_ARBITER_CONFIG) + +START_REGISTER(MH_CLNT_AXI_ID_REUSE) + GENERATE_FIELD(CPw_ID, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(RBw_ID, int) + GENERATE_FIELD(RESERVED2, int) + GENERATE_FIELD(MMUr_ID, int) + GENERATE_FIELD(RESERVED3, int) + GENERATE_FIELD(PAw_ID, int) +END_REGISTER(MH_CLNT_AXI_ID_REUSE) + +START_REGISTER(MH_INTERRUPT_MASK) + GENERATE_FIELD(AXI_READ_ERROR, bool) + GENERATE_FIELD(AXI_WRITE_ERROR, bool) + GENERATE_FIELD(MMU_PAGE_FAULT, bool) +END_REGISTER(MH_INTERRUPT_MASK) + +START_REGISTER(MH_INTERRUPT_STATUS) + GENERATE_FIELD(AXI_READ_ERROR, int) + GENERATE_FIELD(AXI_WRITE_ERROR, int) + GENERATE_FIELD(MMU_PAGE_FAULT, int) +END_REGISTER(MH_INTERRUPT_STATUS) + +START_REGISTER(MH_INTERRUPT_CLEAR) + GENERATE_FIELD(AXI_READ_ERROR, int) + GENERATE_FIELD(AXI_WRITE_ERROR, int) + GENERATE_FIELD(MMU_PAGE_FAULT, int) +END_REGISTER(MH_INTERRUPT_CLEAR) + +START_REGISTER(MH_AXI_ERROR) + GENERATE_FIELD(AXI_READ_ID, int) + GENERATE_FIELD(AXI_READ_ERROR, int) + GENERATE_FIELD(AXI_WRITE_ID, int) + GENERATE_FIELD(AXI_WRITE_ERROR, int) +END_REGISTER(MH_AXI_ERROR) + +START_REGISTER(MH_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, MhPerfEncode) +END_REGISTER(MH_PERFCOUNTER0_SELECT) + +START_REGISTER(MH_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_SEL, MhPerfEncode) +END_REGISTER(MH_PERFCOUNTER1_SELECT) + +START_REGISTER(MH_PERFCOUNTER0_CONFIG) + GENERATE_FIELD(N_VALUE, int) +END_REGISTER(MH_PERFCOUNTER0_CONFIG) + +START_REGISTER(MH_PERFCOUNTER1_CONFIG) + GENERATE_FIELD(N_VALUE, int) +END_REGISTER(MH_PERFCOUNTER1_CONFIG) + +START_REGISTER(MH_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNTER_LOW, int) +END_REGISTER(MH_PERFCOUNTER0_LOW) + +START_REGISTER(MH_PERFCOUNTER1_LOW) + GENERATE_FIELD(PERF_COUNTER_LOW, int) +END_REGISTER(MH_PERFCOUNTER1_LOW) + +START_REGISTER(MH_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNTER_HI, int) +END_REGISTER(MH_PERFCOUNTER0_HI) + +START_REGISTER(MH_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNTER_HI, int) +END_REGISTER(MH_PERFCOUNTER1_HI) + +START_REGISTER(MH_DEBUG_CTRL) + GENERATE_FIELD(INDEX, int) +END_REGISTER(MH_DEBUG_CTRL) + +START_REGISTER(MH_DEBUG_DATA) + GENERATE_FIELD(DATA, int) +END_REGISTER(MH_DEBUG_DATA) + +START_REGISTER(MH_AXI_HALT_CONTROL) + GENERATE_FIELD(AXI_HALT, bool) +END_REGISTER(MH_AXI_HALT_CONTROL) + +START_REGISTER(MH_MMU_CONFIG) + GENERATE_FIELD(MMU_ENABLE, bool) + GENERATE_FIELD(SPLIT_MODE_ENABLE, bool) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(RB_W_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_W_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R0_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R1_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R2_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R3_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(CP_R4_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(VGT_R0_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(VGT_R1_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(TC_R_CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(PA_W_CLNT_BEHAVIOR, MmuClntBeh) +END_REGISTER(MH_MMU_CONFIG) + +START_REGISTER(MH_MMU_VA_RANGE) + GENERATE_FIELD(NUM_64KB_REGIONS, int) + GENERATE_FIELD(VA_BASE, int) +END_REGISTER(MH_MMU_VA_RANGE) + +START_REGISTER(MH_MMU_PT_BASE) + GENERATE_FIELD(PT_BASE, int) +END_REGISTER(MH_MMU_PT_BASE) + +START_REGISTER(MH_MMU_PAGE_FAULT) + GENERATE_FIELD(PAGE_FAULT, int) + GENERATE_FIELD(OP_TYPE, int) + GENERATE_FIELD(CLNT_BEHAVIOR, MmuClntBeh) + GENERATE_FIELD(AXI_ID, int) + GENERATE_FIELD(RESERVED1, int) + GENERATE_FIELD(MPU_ADDRESS_OUT_OF_RANGE, int) + GENERATE_FIELD(ADDRESS_OUT_OF_RANGE, int) + GENERATE_FIELD(READ_PROTECTION_ERROR, int) + GENERATE_FIELD(WRITE_PROTECTION_ERROR, int) + GENERATE_FIELD(REQ_VA, int) +END_REGISTER(MH_MMU_PAGE_FAULT) + +START_REGISTER(MH_MMU_TRAN_ERROR) + GENERATE_FIELD(TRAN_ERROR, int) +END_REGISTER(MH_MMU_TRAN_ERROR) + +START_REGISTER(MH_MMU_INVALIDATE) + GENERATE_FIELD(INVALIDATE_ALL, int) + GENERATE_FIELD(INVALIDATE_TC, int) +END_REGISTER(MH_MMU_INVALIDATE) + +START_REGISTER(MH_MMU_MPU_BASE) + GENERATE_FIELD(MPU_BASE, int) +END_REGISTER(MH_MMU_MPU_BASE) + +START_REGISTER(MH_MMU_MPU_END) + GENERATE_FIELD(MPU_END, int) +END_REGISTER(MH_MMU_MPU_END) + +START_REGISTER(WAIT_UNTIL) + GENERATE_FIELD(WAIT_RE_VSYNC, int) + GENERATE_FIELD(WAIT_FE_VSYNC, int) + GENERATE_FIELD(WAIT_VSYNC, int) + GENERATE_FIELD(WAIT_DSPLY_ID0, int) + GENERATE_FIELD(WAIT_DSPLY_ID1, int) + GENERATE_FIELD(WAIT_DSPLY_ID2, int) + GENERATE_FIELD(WAIT_CMDFIFO, int) + GENERATE_FIELD(WAIT_2D_IDLE, int) + GENERATE_FIELD(WAIT_3D_IDLE, int) + GENERATE_FIELD(WAIT_2D_IDLECLEAN, int) + GENERATE_FIELD(WAIT_3D_IDLECLEAN, int) + GENERATE_FIELD(CMDFIFO_ENTRIES, int) +END_REGISTER(WAIT_UNTIL) + +START_REGISTER(RBBM_ISYNC_CNTL) + GENERATE_FIELD(ISYNC_WAIT_IDLEGUI, int) + GENERATE_FIELD(ISYNC_CPSCRATCH_IDLEGUI, int) +END_REGISTER(RBBM_ISYNC_CNTL) + +START_REGISTER(RBBM_STATUS) + GENERATE_FIELD(CMDFIFO_AVAIL, int) + GENERATE_FIELD(TC_BUSY, int) + GENERATE_FIELD(HIRQ_PENDING, int) + GENERATE_FIELD(CPRQ_PENDING, int) + GENERATE_FIELD(CFRQ_PENDING, int) + GENERATE_FIELD(PFRQ_PENDING, int) + GENERATE_FIELD(VGT_BUSY_NO_DMA, int) + GENERATE_FIELD(RBBM_WU_BUSY, int) + GENERATE_FIELD(CP_NRT_BUSY, int) + GENERATE_FIELD(MH_BUSY, int) + GENERATE_FIELD(MH_COHERENCY_BUSY, int) + GENERATE_FIELD(SX_BUSY, int) + GENERATE_FIELD(TPC_BUSY, int) + GENERATE_FIELD(SC_CNTX_BUSY, int) + GENERATE_FIELD(PA_BUSY, int) + GENERATE_FIELD(VGT_BUSY, int) + GENERATE_FIELD(SQ_CNTX17_BUSY, int) + GENERATE_FIELD(SQ_CNTX0_BUSY, int) + GENERATE_FIELD(RB_CNTX_BUSY, int) + GENERATE_FIELD(GUI_ACTIVE, int) +END_REGISTER(RBBM_STATUS) + +START_REGISTER(RBBM_DSPLY) + GENERATE_FIELD(SEL_DMI_ACTIVE_BUFID0, int) + GENERATE_FIELD(SEL_DMI_ACTIVE_BUFID1, int) + GENERATE_FIELD(SEL_DMI_ACTIVE_BUFID2, int) + GENERATE_FIELD(SEL_DMI_VSYNC_VALID, int) + GENERATE_FIELD(DMI_CH1_USE_BUFID0, int) + GENERATE_FIELD(DMI_CH1_USE_BUFID1, int) + GENERATE_FIELD(DMI_CH1_USE_BUFID2, int) + GENERATE_FIELD(DMI_CH1_SW_CNTL, int) + GENERATE_FIELD(DMI_CH1_NUM_BUFS, int) + GENERATE_FIELD(DMI_CH2_USE_BUFID0, int) + GENERATE_FIELD(DMI_CH2_USE_BUFID1, int) + GENERATE_FIELD(DMI_CH2_USE_BUFID2, int) + GENERATE_FIELD(DMI_CH2_SW_CNTL, int) + GENERATE_FIELD(DMI_CH2_NUM_BUFS, int) + GENERATE_FIELD(DMI_CHANNEL_SELECT, int) + GENERATE_FIELD(DMI_CH3_USE_BUFID0, int) + GENERATE_FIELD(DMI_CH3_USE_BUFID1, int) + GENERATE_FIELD(DMI_CH3_USE_BUFID2, int) + GENERATE_FIELD(DMI_CH3_SW_CNTL, int) + GENERATE_FIELD(DMI_CH3_NUM_BUFS, int) + GENERATE_FIELD(DMI_CH4_USE_BUFID0, int) + GENERATE_FIELD(DMI_CH4_USE_BUFID1, int) + GENERATE_FIELD(DMI_CH4_USE_BUFID2, int) + GENERATE_FIELD(DMI_CH4_SW_CNTL, int) + GENERATE_FIELD(DMI_CH4_NUM_BUFS, int) +END_REGISTER(RBBM_DSPLY) + +START_REGISTER(RBBM_RENDER_LATEST) + GENERATE_FIELD(DMI_CH1_BUFFER_ID, int) + GENERATE_FIELD(DMI_CH2_BUFFER_ID, int) + GENERATE_FIELD(DMI_CH3_BUFFER_ID, int) + GENERATE_FIELD(DMI_CH4_BUFFER_ID, int) +END_REGISTER(RBBM_RENDER_LATEST) + +START_REGISTER(RBBM_RTL_RELEASE) + GENERATE_FIELD(CHANGELIST, int) +END_REGISTER(RBBM_RTL_RELEASE) + +START_REGISTER(RBBM_PATCH_RELEASE) + GENERATE_FIELD(PATCH_REVISION, int) + GENERATE_FIELD(PATCH_SELECTION, int) + GENERATE_FIELD(CUSTOMER_ID, int) +END_REGISTER(RBBM_PATCH_RELEASE) + +START_REGISTER(RBBM_AUXILIARY_CONFIG) + GENERATE_FIELD(RESERVED, int) +END_REGISTER(RBBM_AUXILIARY_CONFIG) + +START_REGISTER(RBBM_PERIPHID0) + GENERATE_FIELD(PARTNUMBER0, int) +END_REGISTER(RBBM_PERIPHID0) + +START_REGISTER(RBBM_PERIPHID1) + GENERATE_FIELD(PARTNUMBER1, int) + GENERATE_FIELD(DESIGNER0, int) +END_REGISTER(RBBM_PERIPHID1) + +START_REGISTER(RBBM_PERIPHID2) + GENERATE_FIELD(DESIGNER1, int) + GENERATE_FIELD(REVISION, int) +END_REGISTER(RBBM_PERIPHID2) + +START_REGISTER(RBBM_PERIPHID3) + GENERATE_FIELD(RBBM_HOST_INTERFACE, int) + GENERATE_FIELD(GARB_SLAVE_INTERFACE, int) + GENERATE_FIELD(MH_INTERFACE, int) + GENERATE_FIELD(CONTINUATION, int) +END_REGISTER(RBBM_PERIPHID3) + +START_REGISTER(RBBM_CNTL) + GENERATE_FIELD(READ_TIMEOUT, int) + GENERATE_FIELD(REGCLK_DEASSERT_TIME, int) +END_REGISTER(RBBM_CNTL) + +START_REGISTER(RBBM_SKEW_CNTL) + GENERATE_FIELD(SKEW_TOP_THRESHOLD, int) + GENERATE_FIELD(SKEW_COUNT, int) +END_REGISTER(RBBM_SKEW_CNTL) + +START_REGISTER(RBBM_SOFT_RESET) + GENERATE_FIELD(SOFT_RESET_CP, int) + GENERATE_FIELD(SOFT_RESET_PA, int) + GENERATE_FIELD(SOFT_RESET_MH, int) + GENERATE_FIELD(SOFT_RESET_BC, int) + GENERATE_FIELD(SOFT_RESET_SQ, int) + GENERATE_FIELD(SOFT_RESET_SX, int) + GENERATE_FIELD(SOFT_RESET_CIB, int) + GENERATE_FIELD(SOFT_RESET_SC, int) + GENERATE_FIELD(SOFT_RESET_VGT, int) +END_REGISTER(RBBM_SOFT_RESET) + +START_REGISTER(RBBM_PM_OVERRIDE1) + GENERATE_FIELD(RBBM_AHBCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SC_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SC_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SP_TOP_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SP_V0_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SQ_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SQ_REG_FIFOS_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SQ_CONST_MEM_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SQ_SQ_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SX_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SX_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCM_TCO_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCM_TCM_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCM_TCD_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCM_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TPC_TPC_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TPC_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCF_TCA_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCF_TCB_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TCF_TCB_READ_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TP_TP_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(TP_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(CP_G_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(CP_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(CP_G_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(SPI_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(RB_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(RB_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(MH_MH_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(MH_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(MH_MMU_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(MH_TCROQ_SCLK_PM_OVERRIDE, int) +END_REGISTER(RBBM_PM_OVERRIDE1) + +START_REGISTER(RBBM_PM_OVERRIDE2) + GENERATE_FIELD(PA_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(PA_PA_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(PA_AG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(VGT_REG_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(VGT_FIFOS_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(VGT_VGT_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(DEBUG_PERF_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(PERM_SCLK_PM_OVERRIDE, int) + GENERATE_FIELD(GC_GA_GMEM0_PM_OVERRIDE, int) + GENERATE_FIELD(GC_GA_GMEM1_PM_OVERRIDE, int) + GENERATE_FIELD(GC_GA_GMEM2_PM_OVERRIDE, int) + GENERATE_FIELD(GC_GA_GMEM3_PM_OVERRIDE, int) +END_REGISTER(RBBM_PM_OVERRIDE2) + +START_REGISTER(GC_SYS_IDLE) + GENERATE_FIELD(GC_SYS_IDLE_DELAY, int) + GENERATE_FIELD(GC_SYS_WAIT_DMI_MASK, int) + GENERATE_FIELD(GC_SYS_URGENT_RAMP, int) + GENERATE_FIELD(GC_SYS_WAIT_DMI, int) + GENERATE_FIELD(GC_SYS_URGENT_RAMP_OVERRIDE, int) + GENERATE_FIELD(GC_SYS_WAIT_DMI_OVERRIDE, int) + GENERATE_FIELD(GC_SYS_IDLE_OVERRIDE, int) +END_REGISTER(GC_SYS_IDLE) + +START_REGISTER(NQWAIT_UNTIL) + GENERATE_FIELD(WAIT_GUI_IDLE, int) +END_REGISTER(NQWAIT_UNTIL) + +START_REGISTER(RBBM_DEBUG_OUT) + GENERATE_FIELD(DEBUG_BUS_OUT, int) +END_REGISTER(RBBM_DEBUG_OUT) + +START_REGISTER(RBBM_DEBUG_CNTL) + GENERATE_FIELD(SUB_BLOCK_ADDR, int) + GENERATE_FIELD(SUB_BLOCK_SEL, int) + GENERATE_FIELD(SW_ENABLE, int) + GENERATE_FIELD(GPIO_SUB_BLOCK_ADDR, int) + GENERATE_FIELD(GPIO_SUB_BLOCK_SEL, int) + GENERATE_FIELD(GPIO_BYTE_LANE_ENB, int) +END_REGISTER(RBBM_DEBUG_CNTL) + +START_REGISTER(RBBM_DEBUG) + GENERATE_FIELD(IGNORE_RTR, int) + GENERATE_FIELD(IGNORE_CP_SCHED_WU, int) + GENERATE_FIELD(IGNORE_CP_SCHED_ISYNC, int) + GENERATE_FIELD(IGNORE_CP_SCHED_NQ_HI, int) + GENERATE_FIELD(HYSTERESIS_NRT_GUI_ACTIVE, int) + GENERATE_FIELD(IGNORE_RTR_FOR_HI, int) + GENERATE_FIELD(IGNORE_CP_RBBM_NRTRTR_FOR_HI, int) + GENERATE_FIELD(IGNORE_VGT_RBBM_NRTRTR_FOR_HI, int) + GENERATE_FIELD(IGNORE_SQ_RBBM_NRTRTR_FOR_HI, int) + GENERATE_FIELD(CP_RBBM_NRTRTR, int) + GENERATE_FIELD(VGT_RBBM_NRTRTR, int) + GENERATE_FIELD(SQ_RBBM_NRTRTR, int) + GENERATE_FIELD(CLIENTS_FOR_NRT_RTR_FOR_HI, int) + GENERATE_FIELD(CLIENTS_FOR_NRT_RTR, int) + GENERATE_FIELD(IGNORE_SX_RBBM_BUSY, int) +END_REGISTER(RBBM_DEBUG) + +START_REGISTER(RBBM_READ_ERROR) + GENERATE_FIELD(READ_ADDRESS, int) + GENERATE_FIELD(READ_REQUESTER, int) + GENERATE_FIELD(READ_ERROR, int) +END_REGISTER(RBBM_READ_ERROR) + +START_REGISTER(RBBM_WAIT_IDLE_CLOCKS) + GENERATE_FIELD(WAIT_IDLE_CLOCKS_NRT, int) +END_REGISTER(RBBM_WAIT_IDLE_CLOCKS) + +START_REGISTER(RBBM_INT_CNTL) + GENERATE_FIELD(RDERR_INT_MASK, int) + GENERATE_FIELD(DISPLAY_UPDATE_INT_MASK, int) + GENERATE_FIELD(GUI_IDLE_INT_MASK, int) +END_REGISTER(RBBM_INT_CNTL) + +START_REGISTER(RBBM_INT_STATUS) + GENERATE_FIELD(RDERR_INT_STAT, int) + GENERATE_FIELD(DISPLAY_UPDATE_INT_STAT, int) + GENERATE_FIELD(GUI_IDLE_INT_STAT, int) +END_REGISTER(RBBM_INT_STATUS) + +START_REGISTER(RBBM_INT_ACK) + GENERATE_FIELD(RDERR_INT_ACK, int) + GENERATE_FIELD(DISPLAY_UPDATE_INT_ACK, int) + GENERATE_FIELD(GUI_IDLE_INT_ACK, int) +END_REGISTER(RBBM_INT_ACK) + +START_REGISTER(MASTER_INT_SIGNAL) + GENERATE_FIELD(MH_INT_STAT, int) + GENERATE_FIELD(SQ_INT_STAT, int) + GENERATE_FIELD(CP_INT_STAT, int) + GENERATE_FIELD(RBBM_INT_STAT, int) +END_REGISTER(MASTER_INT_SIGNAL) + +START_REGISTER(RBBM_PERFCOUNTER1_SELECT) + GENERATE_FIELD(PERF_COUNT1_SEL, RBBM_PERFCOUNT1_SEL) +END_REGISTER(RBBM_PERFCOUNTER1_SELECT) + +START_REGISTER(RBBM_PERFCOUNTER1_LO) + GENERATE_FIELD(PERF_COUNT1_LO, int) +END_REGISTER(RBBM_PERFCOUNTER1_LO) + +START_REGISTER(RBBM_PERFCOUNTER1_HI) + GENERATE_FIELD(PERF_COUNT1_HI, int) +END_REGISTER(RBBM_PERFCOUNTER1_HI) + +START_REGISTER(CP_RB_BASE) + GENERATE_FIELD(RB_BASE, int) +END_REGISTER(CP_RB_BASE) + +START_REGISTER(CP_RB_CNTL) + GENERATE_FIELD(RB_BUFSZ, int) + GENERATE_FIELD(RB_BLKSZ, int) + GENERATE_FIELD(BUF_SWAP, int) + GENERATE_FIELD(RB_POLL_EN, int) + GENERATE_FIELD(RB_NO_UPDATE, int) + GENERATE_FIELD(RB_RPTR_WR_ENA, int) +END_REGISTER(CP_RB_CNTL) + +START_REGISTER(CP_RB_RPTR_ADDR) + GENERATE_FIELD(RB_RPTR_SWAP, int) + GENERATE_FIELD(RB_RPTR_ADDR, int) +END_REGISTER(CP_RB_RPTR_ADDR) + +START_REGISTER(CP_RB_RPTR) + GENERATE_FIELD(RB_RPTR, int) +END_REGISTER(CP_RB_RPTR) + +START_REGISTER(CP_RB_RPTR_WR) + GENERATE_FIELD(RB_RPTR_WR, int) +END_REGISTER(CP_RB_RPTR_WR) + +START_REGISTER(CP_RB_WPTR) + GENERATE_FIELD(RB_WPTR, int) +END_REGISTER(CP_RB_WPTR) + +START_REGISTER(CP_RB_WPTR_DELAY) + GENERATE_FIELD(PRE_WRITE_TIMER, int) + GENERATE_FIELD(PRE_WRITE_LIMIT, int) +END_REGISTER(CP_RB_WPTR_DELAY) + +START_REGISTER(CP_RB_WPTR_BASE) + GENERATE_FIELD(RB_WPTR_SWAP, int) + GENERATE_FIELD(RB_WPTR_BASE, int) +END_REGISTER(CP_RB_WPTR_BASE) + +START_REGISTER(CP_IB1_BASE) + GENERATE_FIELD(IB1_BASE, int) +END_REGISTER(CP_IB1_BASE) + +START_REGISTER(CP_IB1_BUFSZ) + GENERATE_FIELD(IB1_BUFSZ, int) +END_REGISTER(CP_IB1_BUFSZ) + +START_REGISTER(CP_IB2_BASE) + GENERATE_FIELD(IB2_BASE, int) +END_REGISTER(CP_IB2_BASE) + +START_REGISTER(CP_IB2_BUFSZ) + GENERATE_FIELD(IB2_BUFSZ, int) +END_REGISTER(CP_IB2_BUFSZ) + +START_REGISTER(CP_ST_BASE) + GENERATE_FIELD(ST_BASE, int) +END_REGISTER(CP_ST_BASE) + +START_REGISTER(CP_ST_BUFSZ) + GENERATE_FIELD(ST_BUFSZ, int) +END_REGISTER(CP_ST_BUFSZ) + +START_REGISTER(CP_QUEUE_THRESHOLDS) + GENERATE_FIELD(CSQ_IB1_START, int) + GENERATE_FIELD(CSQ_IB2_START, int) + GENERATE_FIELD(CSQ_ST_START, int) +END_REGISTER(CP_QUEUE_THRESHOLDS) + +START_REGISTER(CP_MEQ_THRESHOLDS) + GENERATE_FIELD(MEQ_END, int) + GENERATE_FIELD(ROQ_END, int) +END_REGISTER(CP_MEQ_THRESHOLDS) + +START_REGISTER(CP_CSQ_AVAIL) + GENERATE_FIELD(CSQ_CNT_RING, int) + GENERATE_FIELD(CSQ_CNT_IB1, int) + GENERATE_FIELD(CSQ_CNT_IB2, int) +END_REGISTER(CP_CSQ_AVAIL) + +START_REGISTER(CP_STQ_AVAIL) + GENERATE_FIELD(STQ_CNT_ST, int) +END_REGISTER(CP_STQ_AVAIL) + +START_REGISTER(CP_MEQ_AVAIL) + GENERATE_FIELD(MEQ_CNT, int) +END_REGISTER(CP_MEQ_AVAIL) + +START_REGISTER(CP_CSQ_RB_STAT) + GENERATE_FIELD(CSQ_RPTR_PRIMARY, int) + GENERATE_FIELD(CSQ_WPTR_PRIMARY, int) +END_REGISTER(CP_CSQ_RB_STAT) + +START_REGISTER(CP_CSQ_IB1_STAT) + GENERATE_FIELD(CSQ_RPTR_INDIRECT1, int) + GENERATE_FIELD(CSQ_WPTR_INDIRECT1, int) +END_REGISTER(CP_CSQ_IB1_STAT) + +START_REGISTER(CP_CSQ_IB2_STAT) + GENERATE_FIELD(CSQ_RPTR_INDIRECT2, int) + GENERATE_FIELD(CSQ_WPTR_INDIRECT2, int) +END_REGISTER(CP_CSQ_IB2_STAT) + +START_REGISTER(CP_NON_PREFETCH_CNTRS) + GENERATE_FIELD(IB1_COUNTER, int) + GENERATE_FIELD(IB2_COUNTER, int) +END_REGISTER(CP_NON_PREFETCH_CNTRS) + +START_REGISTER(CP_STQ_ST_STAT) + GENERATE_FIELD(STQ_RPTR_ST, int) + GENERATE_FIELD(STQ_WPTR_ST, int) +END_REGISTER(CP_STQ_ST_STAT) + +START_REGISTER(CP_MEQ_STAT) + GENERATE_FIELD(MEQ_RPTR, int) + GENERATE_FIELD(MEQ_WPTR, int) +END_REGISTER(CP_MEQ_STAT) + +START_REGISTER(CP_MIU_TAG_STAT) + GENERATE_FIELD(TAG_0_STAT, int) + GENERATE_FIELD(TAG_1_STAT, int) + GENERATE_FIELD(TAG_2_STAT, int) + GENERATE_FIELD(TAG_3_STAT, int) + GENERATE_FIELD(TAG_4_STAT, int) + GENERATE_FIELD(TAG_5_STAT, int) + GENERATE_FIELD(TAG_6_STAT, int) + GENERATE_FIELD(TAG_7_STAT, int) + GENERATE_FIELD(TAG_8_STAT, int) + GENERATE_FIELD(TAG_9_STAT, int) + GENERATE_FIELD(TAG_10_STAT, int) + GENERATE_FIELD(TAG_11_STAT, int) + GENERATE_FIELD(TAG_12_STAT, int) + GENERATE_FIELD(TAG_13_STAT, int) + GENERATE_FIELD(TAG_14_STAT, int) + GENERATE_FIELD(TAG_15_STAT, int) + GENERATE_FIELD(TAG_16_STAT, int) + GENERATE_FIELD(TAG_17_STAT, int) + GENERATE_FIELD(INVALID_RETURN_TAG, int) +END_REGISTER(CP_MIU_TAG_STAT) + +START_REGISTER(CP_CMD_INDEX) + GENERATE_FIELD(CMD_INDEX, int) + GENERATE_FIELD(CMD_QUEUE_SEL, int) +END_REGISTER(CP_CMD_INDEX) + +START_REGISTER(CP_CMD_DATA) + GENERATE_FIELD(CMD_DATA, int) +END_REGISTER(CP_CMD_DATA) + +START_REGISTER(CP_ME_CNTL) + GENERATE_FIELD(ME_STATMUX, int) + GENERATE_FIELD(VTX_DEALLOC_FIFO_EMPTY, int) + GENERATE_FIELD(PIX_DEALLOC_FIFO_EMPTY, int) + GENERATE_FIELD(ME_HALT, int) + GENERATE_FIELD(ME_BUSY, int) + GENERATE_FIELD(PROG_CNT_SIZE, int) +END_REGISTER(CP_ME_CNTL) + +START_REGISTER(CP_ME_STATUS) + GENERATE_FIELD(ME_DEBUG_DATA, int) +END_REGISTER(CP_ME_STATUS) + +START_REGISTER(CP_ME_RAM_WADDR) + GENERATE_FIELD(ME_RAM_WADDR, int) +END_REGISTER(CP_ME_RAM_WADDR) + +START_REGISTER(CP_ME_RAM_RADDR) + GENERATE_FIELD(ME_RAM_RADDR, int) +END_REGISTER(CP_ME_RAM_RADDR) + +START_REGISTER(CP_ME_RAM_DATA) + GENERATE_FIELD(ME_RAM_DATA, int) +END_REGISTER(CP_ME_RAM_DATA) + +START_REGISTER(CP_ME_RDADDR) + GENERATE_FIELD(ME_RDADDR, int) +END_REGISTER(CP_ME_RDADDR) + +START_REGISTER(CP_DEBUG) + GENERATE_FIELD(CP_DEBUG_UNUSED_22_to_0, int) + GENERATE_FIELD(PREDICATE_DISABLE, int) + GENERATE_FIELD(PROG_END_PTR_ENABLE, int) + GENERATE_FIELD(MIU_128BIT_WRITE_ENABLE, int) + GENERATE_FIELD(PREFETCH_PASS_NOPS, int) + GENERATE_FIELD(DYNAMIC_CLK_DISABLE, int) + GENERATE_FIELD(PREFETCH_MATCH_DISABLE, int) + GENERATE_FIELD(SIMPLE_ME_FLOW_CONTROL, int) + GENERATE_FIELD(MIU_WRITE_PACK_DISABLE, int) +END_REGISTER(CP_DEBUG) + +START_REGISTER(SCRATCH_REG0) + GENERATE_FIELD(SCRATCH_REG0, int) +END_REGISTER(SCRATCH_REG0) + +START_REGISTER(SCRATCH_REG1) + GENERATE_FIELD(SCRATCH_REG1, int) +END_REGISTER(SCRATCH_REG1) + +START_REGISTER(SCRATCH_REG2) + GENERATE_FIELD(SCRATCH_REG2, int) +END_REGISTER(SCRATCH_REG2) + +START_REGISTER(SCRATCH_REG3) + GENERATE_FIELD(SCRATCH_REG3, int) +END_REGISTER(SCRATCH_REG3) + +START_REGISTER(SCRATCH_REG4) + GENERATE_FIELD(SCRATCH_REG4, int) +END_REGISTER(SCRATCH_REG4) + +START_REGISTER(SCRATCH_REG5) + GENERATE_FIELD(SCRATCH_REG5, int) +END_REGISTER(SCRATCH_REG5) + +START_REGISTER(SCRATCH_REG6) + GENERATE_FIELD(SCRATCH_REG6, int) +END_REGISTER(SCRATCH_REG6) + +START_REGISTER(SCRATCH_REG7) + GENERATE_FIELD(SCRATCH_REG7, int) +END_REGISTER(SCRATCH_REG7) + +START_REGISTER(SCRATCH_UMSK) + GENERATE_FIELD(SCRATCH_UMSK, int) + GENERATE_FIELD(SCRATCH_SWAP, int) +END_REGISTER(SCRATCH_UMSK) + +START_REGISTER(SCRATCH_ADDR) + GENERATE_FIELD(SCRATCH_ADDR, hex) +END_REGISTER(SCRATCH_ADDR) + +START_REGISTER(CP_ME_VS_EVENT_SRC) + GENERATE_FIELD(VS_DONE_SWM, int) + GENERATE_FIELD(VS_DONE_CNTR, int) +END_REGISTER(CP_ME_VS_EVENT_SRC) + +START_REGISTER(CP_ME_VS_EVENT_ADDR) + GENERATE_FIELD(VS_DONE_SWAP, int) + GENERATE_FIELD(VS_DONE_ADDR, int) +END_REGISTER(CP_ME_VS_EVENT_ADDR) + +START_REGISTER(CP_ME_VS_EVENT_DATA) + GENERATE_FIELD(VS_DONE_DATA, int) +END_REGISTER(CP_ME_VS_EVENT_DATA) + +START_REGISTER(CP_ME_VS_EVENT_ADDR_SWM) + GENERATE_FIELD(VS_DONE_SWAP_SWM, int) + GENERATE_FIELD(VS_DONE_ADDR_SWM, int) +END_REGISTER(CP_ME_VS_EVENT_ADDR_SWM) + +START_REGISTER(CP_ME_VS_EVENT_DATA_SWM) + GENERATE_FIELD(VS_DONE_DATA_SWM, int) +END_REGISTER(CP_ME_VS_EVENT_DATA_SWM) + +START_REGISTER(CP_ME_PS_EVENT_SRC) + GENERATE_FIELD(PS_DONE_SWM, int) + GENERATE_FIELD(PS_DONE_CNTR, int) +END_REGISTER(CP_ME_PS_EVENT_SRC) + +START_REGISTER(CP_ME_PS_EVENT_ADDR) + GENERATE_FIELD(PS_DONE_SWAP, int) + GENERATE_FIELD(PS_DONE_ADDR, int) +END_REGISTER(CP_ME_PS_EVENT_ADDR) + +START_REGISTER(CP_ME_PS_EVENT_DATA) + GENERATE_FIELD(PS_DONE_DATA, int) +END_REGISTER(CP_ME_PS_EVENT_DATA) + +START_REGISTER(CP_ME_PS_EVENT_ADDR_SWM) + GENERATE_FIELD(PS_DONE_SWAP_SWM, int) + GENERATE_FIELD(PS_DONE_ADDR_SWM, int) +END_REGISTER(CP_ME_PS_EVENT_ADDR_SWM) + +START_REGISTER(CP_ME_PS_EVENT_DATA_SWM) + GENERATE_FIELD(PS_DONE_DATA_SWM, int) +END_REGISTER(CP_ME_PS_EVENT_DATA_SWM) + +START_REGISTER(CP_ME_CF_EVENT_SRC) + GENERATE_FIELD(CF_DONE_SRC, int) +END_REGISTER(CP_ME_CF_EVENT_SRC) + +START_REGISTER(CP_ME_CF_EVENT_ADDR) + GENERATE_FIELD(CF_DONE_SWAP, int) + GENERATE_FIELD(CF_DONE_ADDR, int) +END_REGISTER(CP_ME_CF_EVENT_ADDR) + +START_REGISTER(CP_ME_CF_EVENT_DATA) + GENERATE_FIELD(CF_DONE_DATA, int) +END_REGISTER(CP_ME_CF_EVENT_DATA) + +START_REGISTER(CP_ME_NRT_ADDR) + GENERATE_FIELD(NRT_WRITE_SWAP, int) + GENERATE_FIELD(NRT_WRITE_ADDR, int) +END_REGISTER(CP_ME_NRT_ADDR) + +START_REGISTER(CP_ME_NRT_DATA) + GENERATE_FIELD(NRT_WRITE_DATA, int) +END_REGISTER(CP_ME_NRT_DATA) + +START_REGISTER(CP_ME_VS_FETCH_DONE_SRC) + GENERATE_FIELD(VS_FETCH_DONE_CNTR, int) +END_REGISTER(CP_ME_VS_FETCH_DONE_SRC) + +START_REGISTER(CP_ME_VS_FETCH_DONE_ADDR) + GENERATE_FIELD(VS_FETCH_DONE_SWAP, int) + GENERATE_FIELD(VS_FETCH_DONE_ADDR, int) +END_REGISTER(CP_ME_VS_FETCH_DONE_ADDR) + +START_REGISTER(CP_ME_VS_FETCH_DONE_DATA) + GENERATE_FIELD(VS_FETCH_DONE_DATA, int) +END_REGISTER(CP_ME_VS_FETCH_DONE_DATA) + +START_REGISTER(CP_INT_CNTL) + GENERATE_FIELD(SW_INT_MASK, int) + GENERATE_FIELD(T0_PACKET_IN_IB_MASK, int) + GENERATE_FIELD(OPCODE_ERROR_MASK, int) + GENERATE_FIELD(PROTECTED_MODE_ERROR_MASK, int) + GENERATE_FIELD(RESERVED_BIT_ERROR_MASK, int) + GENERATE_FIELD(IB_ERROR_MASK, int) + GENERATE_FIELD(IB2_INT_MASK, int) + GENERATE_FIELD(IB1_INT_MASK, int) + GENERATE_FIELD(RB_INT_MASK, int) +END_REGISTER(CP_INT_CNTL) + +START_REGISTER(CP_INT_STATUS) + GENERATE_FIELD(SW_INT_STAT, int) + GENERATE_FIELD(T0_PACKET_IN_IB_STAT, int) + GENERATE_FIELD(OPCODE_ERROR_STAT, int) + GENERATE_FIELD(PROTECTED_MODE_ERROR_STAT, int) + GENERATE_FIELD(RESERVED_BIT_ERROR_STAT, int) + GENERATE_FIELD(IB_ERROR_STAT, int) + GENERATE_FIELD(IB2_INT_STAT, int) + GENERATE_FIELD(IB1_INT_STAT, int) + GENERATE_FIELD(RB_INT_STAT, int) +END_REGISTER(CP_INT_STATUS) + +START_REGISTER(CP_INT_ACK) + GENERATE_FIELD(SW_INT_ACK, int) + GENERATE_FIELD(T0_PACKET_IN_IB_ACK, int) + GENERATE_FIELD(OPCODE_ERROR_ACK, int) + GENERATE_FIELD(PROTECTED_MODE_ERROR_ACK, int) + GENERATE_FIELD(RESERVED_BIT_ERROR_ACK, int) + GENERATE_FIELD(IB_ERROR_ACK, int) + GENERATE_FIELD(IB2_INT_ACK, int) + GENERATE_FIELD(IB1_INT_ACK, int) + GENERATE_FIELD(RB_INT_ACK, int) +END_REGISTER(CP_INT_ACK) + +START_REGISTER(CP_PFP_UCODE_ADDR) + GENERATE_FIELD(UCODE_ADDR, hex) +END_REGISTER(CP_PFP_UCODE_ADDR) + +START_REGISTER(CP_PFP_UCODE_DATA) + GENERATE_FIELD(UCODE_DATA, hex) +END_REGISTER(CP_PFP_UCODE_DATA) + +START_REGISTER(CP_PERFMON_CNTL) + GENERATE_FIELD(PERFMON_STATE, int) + GENERATE_FIELD(PERFMON_ENABLE_MODE, int) +END_REGISTER(CP_PERFMON_CNTL) + +START_REGISTER(CP_PERFCOUNTER_SELECT) + GENERATE_FIELD(PERFCOUNT_SEL, CP_PERFCOUNT_SEL) +END_REGISTER(CP_PERFCOUNTER_SELECT) + +START_REGISTER(CP_PERFCOUNTER_LO) + GENERATE_FIELD(PERFCOUNT_LO, int) +END_REGISTER(CP_PERFCOUNTER_LO) + +START_REGISTER(CP_PERFCOUNTER_HI) + GENERATE_FIELD(PERFCOUNT_HI, int) +END_REGISTER(CP_PERFCOUNTER_HI) + +START_REGISTER(CP_BIN_MASK_LO) + GENERATE_FIELD(BIN_MASK_LO, int) +END_REGISTER(CP_BIN_MASK_LO) + +START_REGISTER(CP_BIN_MASK_HI) + GENERATE_FIELD(BIN_MASK_HI, int) +END_REGISTER(CP_BIN_MASK_HI) + +START_REGISTER(CP_BIN_SELECT_LO) + GENERATE_FIELD(BIN_SELECT_LO, int) +END_REGISTER(CP_BIN_SELECT_LO) + +START_REGISTER(CP_BIN_SELECT_HI) + GENERATE_FIELD(BIN_SELECT_HI, int) +END_REGISTER(CP_BIN_SELECT_HI) + +START_REGISTER(CP_NV_FLAGS_0) + GENERATE_FIELD(DISCARD_0, int) + GENERATE_FIELD(END_RCVD_0, int) + GENERATE_FIELD(DISCARD_1, int) + GENERATE_FIELD(END_RCVD_1, int) + GENERATE_FIELD(DISCARD_2, int) + GENERATE_FIELD(END_RCVD_2, int) + GENERATE_FIELD(DISCARD_3, int) + GENERATE_FIELD(END_RCVD_3, int) + GENERATE_FIELD(DISCARD_4, int) + GENERATE_FIELD(END_RCVD_4, int) + GENERATE_FIELD(DISCARD_5, int) + GENERATE_FIELD(END_RCVD_5, int) + GENERATE_FIELD(DISCARD_6, int) + GENERATE_FIELD(END_RCVD_6, int) + GENERATE_FIELD(DISCARD_7, int) + GENERATE_FIELD(END_RCVD_7, int) + GENERATE_FIELD(DISCARD_8, int) + GENERATE_FIELD(END_RCVD_8, int) + GENERATE_FIELD(DISCARD_9, int) + GENERATE_FIELD(END_RCVD_9, int) + GENERATE_FIELD(DISCARD_10, int) + GENERATE_FIELD(END_RCVD_10, int) + GENERATE_FIELD(DISCARD_11, int) + GENERATE_FIELD(END_RCVD_11, int) + GENERATE_FIELD(DISCARD_12, int) + GENERATE_FIELD(END_RCVD_12, int) + GENERATE_FIELD(DISCARD_13, int) + GENERATE_FIELD(END_RCVD_13, int) + GENERATE_FIELD(DISCARD_14, int) + GENERATE_FIELD(END_RCVD_14, int) + GENERATE_FIELD(DISCARD_15, int) + GENERATE_FIELD(END_RCVD_15, int) +END_REGISTER(CP_NV_FLAGS_0) + +START_REGISTER(CP_NV_FLAGS_1) + GENERATE_FIELD(DISCARD_16, int) + GENERATE_FIELD(END_RCVD_16, int) + GENERATE_FIELD(DISCARD_17, int) + GENERATE_FIELD(END_RCVD_17, int) + GENERATE_FIELD(DISCARD_18, int) + GENERATE_FIELD(END_RCVD_18, int) + GENERATE_FIELD(DISCARD_19, int) + GENERATE_FIELD(END_RCVD_19, int) + GENERATE_FIELD(DISCARD_20, int) + GENERATE_FIELD(END_RCVD_20, int) + GENERATE_FIELD(DISCARD_21, int) + GENERATE_FIELD(END_RCVD_21, int) + GENERATE_FIELD(DISCARD_22, int) + GENERATE_FIELD(END_RCVD_22, int) + GENERATE_FIELD(DISCARD_23, int) + GENERATE_FIELD(END_RCVD_23, int) + GENERATE_FIELD(DISCARD_24, int) + GENERATE_FIELD(END_RCVD_24, int) + GENERATE_FIELD(DISCARD_25, int) + GENERATE_FIELD(END_RCVD_25, int) + GENERATE_FIELD(DISCARD_26, int) + GENERATE_FIELD(END_RCVD_26, int) + GENERATE_FIELD(DISCARD_27, int) + GENERATE_FIELD(END_RCVD_27, int) + GENERATE_FIELD(DISCARD_28, int) + GENERATE_FIELD(END_RCVD_28, int) + GENERATE_FIELD(DISCARD_29, int) + GENERATE_FIELD(END_RCVD_29, int) + GENERATE_FIELD(DISCARD_30, int) + GENERATE_FIELD(END_RCVD_30, int) + GENERATE_FIELD(DISCARD_31, int) + GENERATE_FIELD(END_RCVD_31, int) +END_REGISTER(CP_NV_FLAGS_1) + +START_REGISTER(CP_NV_FLAGS_2) + GENERATE_FIELD(DISCARD_32, int) + GENERATE_FIELD(END_RCVD_32, int) + GENERATE_FIELD(DISCARD_33, int) + GENERATE_FIELD(END_RCVD_33, int) + GENERATE_FIELD(DISCARD_34, int) + GENERATE_FIELD(END_RCVD_34, int) + GENERATE_FIELD(DISCARD_35, int) + GENERATE_FIELD(END_RCVD_35, int) + GENERATE_FIELD(DISCARD_36, int) + GENERATE_FIELD(END_RCVD_36, int) + GENERATE_FIELD(DISCARD_37, int) + GENERATE_FIELD(END_RCVD_37, int) + GENERATE_FIELD(DISCARD_38, int) + GENERATE_FIELD(END_RCVD_38, int) + GENERATE_FIELD(DISCARD_39, int) + GENERATE_FIELD(END_RCVD_39, int) + GENERATE_FIELD(DISCARD_40, int) + GENERATE_FIELD(END_RCVD_40, int) + GENERATE_FIELD(DISCARD_41, int) + GENERATE_FIELD(END_RCVD_41, int) + GENERATE_FIELD(DISCARD_42, int) + GENERATE_FIELD(END_RCVD_42, int) + GENERATE_FIELD(DISCARD_43, int) + GENERATE_FIELD(END_RCVD_43, int) + GENERATE_FIELD(DISCARD_44, int) + GENERATE_FIELD(END_RCVD_44, int) + GENERATE_FIELD(DISCARD_45, int) + GENERATE_FIELD(END_RCVD_45, int) + GENERATE_FIELD(DISCARD_46, int) + GENERATE_FIELD(END_RCVD_46, int) + GENERATE_FIELD(DISCARD_47, int) + GENERATE_FIELD(END_RCVD_47, int) +END_REGISTER(CP_NV_FLAGS_2) + +START_REGISTER(CP_NV_FLAGS_3) + GENERATE_FIELD(DISCARD_48, int) + GENERATE_FIELD(END_RCVD_48, int) + GENERATE_FIELD(DISCARD_49, int) + GENERATE_FIELD(END_RCVD_49, int) + GENERATE_FIELD(DISCARD_50, int) + GENERATE_FIELD(END_RCVD_50, int) + GENERATE_FIELD(DISCARD_51, int) + GENERATE_FIELD(END_RCVD_51, int) + GENERATE_FIELD(DISCARD_52, int) + GENERATE_FIELD(END_RCVD_52, int) + GENERATE_FIELD(DISCARD_53, int) + GENERATE_FIELD(END_RCVD_53, int) + GENERATE_FIELD(DISCARD_54, int) + GENERATE_FIELD(END_RCVD_54, int) + GENERATE_FIELD(DISCARD_55, int) + GENERATE_FIELD(END_RCVD_55, int) + GENERATE_FIELD(DISCARD_56, int) + GENERATE_FIELD(END_RCVD_56, int) + GENERATE_FIELD(DISCARD_57, int) + GENERATE_FIELD(END_RCVD_57, int) + GENERATE_FIELD(DISCARD_58, int) + GENERATE_FIELD(END_RCVD_58, int) + GENERATE_FIELD(DISCARD_59, int) + GENERATE_FIELD(END_RCVD_59, int) + GENERATE_FIELD(DISCARD_60, int) + GENERATE_FIELD(END_RCVD_60, int) + GENERATE_FIELD(DISCARD_61, int) + GENERATE_FIELD(END_RCVD_61, int) + GENERATE_FIELD(DISCARD_62, int) + GENERATE_FIELD(END_RCVD_62, int) + GENERATE_FIELD(DISCARD_63, int) + GENERATE_FIELD(END_RCVD_63, int) +END_REGISTER(CP_NV_FLAGS_3) + +START_REGISTER(CP_STATE_DEBUG_INDEX) + GENERATE_FIELD(STATE_DEBUG_INDEX, int) +END_REGISTER(CP_STATE_DEBUG_INDEX) + +START_REGISTER(CP_STATE_DEBUG_DATA) + GENERATE_FIELD(STATE_DEBUG_DATA, int) +END_REGISTER(CP_STATE_DEBUG_DATA) + +START_REGISTER(CP_PROG_COUNTER) + GENERATE_FIELD(COUNTER, int) +END_REGISTER(CP_PROG_COUNTER) + +START_REGISTER(CP_STAT) + GENERATE_FIELD(MIU_WR_BUSY, int) + GENERATE_FIELD(MIU_RD_REQ_BUSY, int) + GENERATE_FIELD(MIU_RD_RETURN_BUSY, int) + GENERATE_FIELD(RBIU_BUSY, int) + GENERATE_FIELD(RCIU_BUSY, int) + GENERATE_FIELD(CSF_RING_BUSY, int) + GENERATE_FIELD(CSF_INDIRECTS_BUSY, int) + GENERATE_FIELD(CSF_INDIRECT2_BUSY, int) + GENERATE_FIELD(CSF_ST_BUSY, int) + GENERATE_FIELD(CSF_BUSY, int) + GENERATE_FIELD(RING_QUEUE_BUSY, int) + GENERATE_FIELD(INDIRECTS_QUEUE_BUSY, int) + GENERATE_FIELD(INDIRECT2_QUEUE_BUSY, int) + GENERATE_FIELD(ST_QUEUE_BUSY, int) + GENERATE_FIELD(PFP_BUSY, int) + GENERATE_FIELD(MEQ_RING_BUSY, int) + GENERATE_FIELD(MEQ_INDIRECTS_BUSY, int) + GENERATE_FIELD(MEQ_INDIRECT2_BUSY, int) + GENERATE_FIELD(MIU_WC_STALL, int) + GENERATE_FIELD(CP_NRT_BUSY, int) + GENERATE_FIELD(_3D_BUSY, int) + GENERATE_FIELD(ME_BUSY, int) + GENERATE_FIELD(ME_WC_BUSY, int) + GENERATE_FIELD(MIU_WC_TRACK_FIFO_EMPTY, int) + GENERATE_FIELD(CP_BUSY, int) +END_REGISTER(CP_STAT) + +START_REGISTER(BIOS_0_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_0_SCRATCH) + +START_REGISTER(BIOS_1_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_1_SCRATCH) + +START_REGISTER(BIOS_2_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_2_SCRATCH) + +START_REGISTER(BIOS_3_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_3_SCRATCH) + +START_REGISTER(BIOS_4_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_4_SCRATCH) + +START_REGISTER(BIOS_5_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_5_SCRATCH) + +START_REGISTER(BIOS_6_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_6_SCRATCH) + +START_REGISTER(BIOS_7_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_7_SCRATCH) + +START_REGISTER(BIOS_8_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_8_SCRATCH) + +START_REGISTER(BIOS_9_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_9_SCRATCH) + +START_REGISTER(BIOS_10_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_10_SCRATCH) + +START_REGISTER(BIOS_11_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_11_SCRATCH) + +START_REGISTER(BIOS_12_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_12_SCRATCH) + +START_REGISTER(BIOS_13_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_13_SCRATCH) + +START_REGISTER(BIOS_14_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_14_SCRATCH) + +START_REGISTER(BIOS_15_SCRATCH) + GENERATE_FIELD(BIOS_SCRATCH, hex) +END_REGISTER(BIOS_15_SCRATCH) + +START_REGISTER(COHER_SIZE_PM4) + GENERATE_FIELD(SIZE, int) +END_REGISTER(COHER_SIZE_PM4) + +START_REGISTER(COHER_BASE_PM4) + GENERATE_FIELD(BASE, int) +END_REGISTER(COHER_BASE_PM4) + +START_REGISTER(COHER_STATUS_PM4) + GENERATE_FIELD(MATCHING_CONTEXTS, int) + GENERATE_FIELD(RB_COPY_DEST_BASE_ENA, int) + GENERATE_FIELD(DEST_BASE_0_ENA, int) + GENERATE_FIELD(DEST_BASE_1_ENA, int) + GENERATE_FIELD(DEST_BASE_2_ENA, int) + GENERATE_FIELD(DEST_BASE_3_ENA, int) + GENERATE_FIELD(DEST_BASE_4_ENA, int) + GENERATE_FIELD(DEST_BASE_5_ENA, int) + GENERATE_FIELD(DEST_BASE_6_ENA, int) + GENERATE_FIELD(DEST_BASE_7_ENA, int) + GENERATE_FIELD(RB_COLOR_INFO_ENA, int) + GENERATE_FIELD(TC_ACTION_ENA, int) + GENERATE_FIELD(STATUS, int) +END_REGISTER(COHER_STATUS_PM4) + +START_REGISTER(COHER_SIZE_HOST) + GENERATE_FIELD(SIZE, int) +END_REGISTER(COHER_SIZE_HOST) + +START_REGISTER(COHER_BASE_HOST) + GENERATE_FIELD(BASE, hex) +END_REGISTER(COHER_BASE_HOST) + +START_REGISTER(COHER_STATUS_HOST) + GENERATE_FIELD(MATCHING_CONTEXTS, int) + GENERATE_FIELD(RB_COPY_DEST_BASE_ENA, int) + GENERATE_FIELD(DEST_BASE_0_ENA, int) + GENERATE_FIELD(DEST_BASE_1_ENA, int) + GENERATE_FIELD(DEST_BASE_2_ENA, int) + GENERATE_FIELD(DEST_BASE_3_ENA, int) + GENERATE_FIELD(DEST_BASE_4_ENA, int) + GENERATE_FIELD(DEST_BASE_5_ENA, int) + GENERATE_FIELD(DEST_BASE_6_ENA, int) + GENERATE_FIELD(DEST_BASE_7_ENA, int) + GENERATE_FIELD(RB_COLOR_INFO_ENA, int) + GENERATE_FIELD(TC_ACTION_ENA, int) + GENERATE_FIELD(STATUS, int) +END_REGISTER(COHER_STATUS_HOST) + +START_REGISTER(COHER_DEST_BASE_0) + GENERATE_FIELD(DEST_BASE_0, hex) +END_REGISTER(COHER_DEST_BASE_0) + +START_REGISTER(COHER_DEST_BASE_1) + GENERATE_FIELD(DEST_BASE_1, hex) +END_REGISTER(COHER_DEST_BASE_1) + +START_REGISTER(COHER_DEST_BASE_2) + GENERATE_FIELD(DEST_BASE_2, hex) +END_REGISTER(COHER_DEST_BASE_2) + +START_REGISTER(COHER_DEST_BASE_3) + GENERATE_FIELD(DEST_BASE_3, hex) +END_REGISTER(COHER_DEST_BASE_3) + +START_REGISTER(COHER_DEST_BASE_4) + GENERATE_FIELD(DEST_BASE_4, hex) +END_REGISTER(COHER_DEST_BASE_4) + +START_REGISTER(COHER_DEST_BASE_5) + GENERATE_FIELD(DEST_BASE_5, hex) +END_REGISTER(COHER_DEST_BASE_5) + +START_REGISTER(COHER_DEST_BASE_6) + GENERATE_FIELD(DEST_BASE_6, hex) +END_REGISTER(COHER_DEST_BASE_6) + +START_REGISTER(COHER_DEST_BASE_7) + GENERATE_FIELD(DEST_BASE_7, hex) +END_REGISTER(COHER_DEST_BASE_7) + +START_REGISTER(RB_SURFACE_INFO) + GENERATE_FIELD(SURFACE_PITCH, uint) + GENERATE_FIELD(MSAA_SAMPLES, MSAASamples) +END_REGISTER(RB_SURFACE_INFO) + +START_REGISTER(RB_COLOR_INFO) + GENERATE_FIELD(COLOR_FORMAT, ColorformatX) + GENERATE_FIELD(COLOR_ROUND_MODE, uint) + GENERATE_FIELD(COLOR_LINEAR, bool) + GENERATE_FIELD(COLOR_ENDIAN, uint) + GENERATE_FIELD(COLOR_SWAP, uint) + GENERATE_FIELD(COLOR_BASE, uint) +END_REGISTER(RB_COLOR_INFO) + +START_REGISTER(RB_DEPTH_INFO) + GENERATE_FIELD(DEPTH_FORMAT, DepthformatX) + GENERATE_FIELD(DEPTH_BASE, uint) +END_REGISTER(RB_DEPTH_INFO) + +START_REGISTER(RB_STENCILREFMASK) + GENERATE_FIELD(STENCILREF, hex) + GENERATE_FIELD(STENCILMASK, hex) + GENERATE_FIELD(STENCILWRITEMASK, hex) + GENERATE_FIELD(RESERVED0, bool) + GENERATE_FIELD(RESERVED1, bool) +END_REGISTER(RB_STENCILREFMASK) + +START_REGISTER(RB_ALPHA_REF) + GENERATE_FIELD(ALPHA_REF, float) +END_REGISTER(RB_ALPHA_REF) + +START_REGISTER(RB_COLOR_MASK) + GENERATE_FIELD(WRITE_RED, bool) + GENERATE_FIELD(WRITE_GREEN, bool) + GENERATE_FIELD(WRITE_BLUE, bool) + GENERATE_FIELD(WRITE_ALPHA, bool) + GENERATE_FIELD(RESERVED2, bool) + GENERATE_FIELD(RESERVED3, bool) +END_REGISTER(RB_COLOR_MASK) + +START_REGISTER(RB_BLEND_RED) + GENERATE_FIELD(BLEND_RED, uint) +END_REGISTER(RB_BLEND_RED) + +START_REGISTER(RB_BLEND_GREEN) + GENERATE_FIELD(BLEND_GREEN, uint) +END_REGISTER(RB_BLEND_GREEN) + +START_REGISTER(RB_BLEND_BLUE) + GENERATE_FIELD(BLEND_BLUE, uint) +END_REGISTER(RB_BLEND_BLUE) + +START_REGISTER(RB_BLEND_ALPHA) + GENERATE_FIELD(BLEND_ALPHA, uint) +END_REGISTER(RB_BLEND_ALPHA) + +START_REGISTER(RB_FOG_COLOR) + GENERATE_FIELD(FOG_RED, uint) + GENERATE_FIELD(FOG_GREEN, uint) + GENERATE_FIELD(FOG_BLUE, uint) +END_REGISTER(RB_FOG_COLOR) + +START_REGISTER(RB_STENCILREFMASK_BF) + GENERATE_FIELD(STENCILREF_BF, hex) + GENERATE_FIELD(STENCILMASK_BF, hex) + GENERATE_FIELD(STENCILWRITEMASK_BF, hex) + GENERATE_FIELD(RESERVED4, bool) + GENERATE_FIELD(RESERVED5, bool) +END_REGISTER(RB_STENCILREFMASK_BF) + +START_REGISTER(RB_DEPTHCONTROL) + GENERATE_FIELD(STENCIL_ENABLE, bool) + GENERATE_FIELD(Z_ENABLE, bool) + GENERATE_FIELD(Z_WRITE_ENABLE, bool) + GENERATE_FIELD(EARLY_Z_ENABLE, bool) + GENERATE_FIELD(ZFUNC, CompareFrag) + GENERATE_FIELD(BACKFACE_ENABLE, bool) + GENERATE_FIELD(STENCILFUNC, CompareRef) + GENERATE_FIELD(STENCILFAIL, StencilOp) + GENERATE_FIELD(STENCILZPASS, StencilOp) + GENERATE_FIELD(STENCILZFAIL, StencilOp) + GENERATE_FIELD(STENCILFUNC_BF, CompareRef) + GENERATE_FIELD(STENCILFAIL_BF, StencilOp) + GENERATE_FIELD(STENCILZPASS_BF, StencilOp) + GENERATE_FIELD(STENCILZFAIL_BF, StencilOp) +END_REGISTER(RB_DEPTHCONTROL) + +START_REGISTER(RB_BLENDCONTROL) + GENERATE_FIELD(COLOR_SRCBLEND, BlendOpX) + GENERATE_FIELD(COLOR_COMB_FCN, CombFuncX) + GENERATE_FIELD(COLOR_DESTBLEND, BlendOpX) + GENERATE_FIELD(ALPHA_SRCBLEND, BlendOpX) + GENERATE_FIELD(ALPHA_COMB_FCN, CombFuncX) + GENERATE_FIELD(ALPHA_DESTBLEND, BlendOpX) + GENERATE_FIELD(BLEND_FORCE_ENABLE, bool) + GENERATE_FIELD(BLEND_FORCE, bool) +END_REGISTER(RB_BLENDCONTROL) + +START_REGISTER(RB_COLORCONTROL) + GENERATE_FIELD(ALPHA_FUNC, CompareRef) + GENERATE_FIELD(ALPHA_TEST_ENABLE, bool) + GENERATE_FIELD(ALPHA_TO_MASK_ENABLE, bool) + GENERATE_FIELD(BLEND_DISABLE, bool) + GENERATE_FIELD(FOG_ENABLE, bool) + GENERATE_FIELD(VS_EXPORTS_FOG, bool) + GENERATE_FIELD(ROP_CODE, uint) + GENERATE_FIELD(DITHER_MODE, DitherModeX) + GENERATE_FIELD(DITHER_TYPE, DitherTypeX) + GENERATE_FIELD(PIXEL_FOG, bool) + GENERATE_FIELD(ALPHA_TO_MASK_OFFSET0, hex) + GENERATE_FIELD(ALPHA_TO_MASK_OFFSET1, hex) + GENERATE_FIELD(ALPHA_TO_MASK_OFFSET2, hex) + GENERATE_FIELD(ALPHA_TO_MASK_OFFSET3, hex) +END_REGISTER(RB_COLORCONTROL) + +START_REGISTER(RB_MODECONTROL) + GENERATE_FIELD(EDRAM_MODE, EdramMode) +END_REGISTER(RB_MODECONTROL) + +START_REGISTER(RB_COLOR_DEST_MASK) + GENERATE_FIELD(COLOR_DEST_MASK, uint) +END_REGISTER(RB_COLOR_DEST_MASK) + +START_REGISTER(RB_COPY_CONTROL) + GENERATE_FIELD(COPY_SAMPLE_SELECT, CopySampleSelect) + GENERATE_FIELD(DEPTH_CLEAR_ENABLE, bool) + GENERATE_FIELD(CLEAR_MASK, uint) +END_REGISTER(RB_COPY_CONTROL) + +START_REGISTER(RB_COPY_DEST_BASE) + GENERATE_FIELD(COPY_DEST_BASE, uint) +END_REGISTER(RB_COPY_DEST_BASE) + +START_REGISTER(RB_COPY_DEST_PITCH) + GENERATE_FIELD(COPY_DEST_PITCH, uint) +END_REGISTER(RB_COPY_DEST_PITCH) + +START_REGISTER(RB_COPY_DEST_INFO) + GENERATE_FIELD(COPY_DEST_ENDIAN, SurfaceEndian) + GENERATE_FIELD(COPY_DEST_LINEAR, uint) + GENERATE_FIELD(COPY_DEST_FORMAT, ColorformatX) + GENERATE_FIELD(COPY_DEST_SWAP, uint) + GENERATE_FIELD(COPY_DEST_DITHER_MODE, DitherModeX) + GENERATE_FIELD(COPY_DEST_DITHER_TYPE, DitherTypeX) + GENERATE_FIELD(COPY_MASK_WRITE_RED, hex) + GENERATE_FIELD(COPY_MASK_WRITE_GREEN, hex) + GENERATE_FIELD(COPY_MASK_WRITE_BLUE, hex) + GENERATE_FIELD(COPY_MASK_WRITE_ALPHA, hex) +END_REGISTER(RB_COPY_DEST_INFO) + +START_REGISTER(RB_COPY_DEST_PIXEL_OFFSET) + GENERATE_FIELD(OFFSET_X, uint) + GENERATE_FIELD(OFFSET_Y, uint) +END_REGISTER(RB_COPY_DEST_PIXEL_OFFSET) + +START_REGISTER(RB_DEPTH_CLEAR) + GENERATE_FIELD(DEPTH_CLEAR, uint) +END_REGISTER(RB_DEPTH_CLEAR) + +START_REGISTER(RB_SAMPLE_COUNT_CTL) + GENERATE_FIELD(RESET_SAMPLE_COUNT, bool) + GENERATE_FIELD(COPY_SAMPLE_COUNT, bool) +END_REGISTER(RB_SAMPLE_COUNT_CTL) + +START_REGISTER(RB_SAMPLE_COUNT_ADDR) + GENERATE_FIELD(SAMPLE_COUNT_ADDR, uint) +END_REGISTER(RB_SAMPLE_COUNT_ADDR) + +START_REGISTER(RB_BC_CONTROL) + GENERATE_FIELD(ACCUM_LINEAR_MODE_ENABLE, bool) + GENERATE_FIELD(ACCUM_TIMEOUT_SELECT, uint) + GENERATE_FIELD(DISABLE_EDRAM_CAM, bool) + GENERATE_FIELD(DISABLE_EZ_FAST_CONTEXT_SWITCH, bool) + GENERATE_FIELD(DISABLE_EZ_NULL_ZCMD_DROP, bool) + GENERATE_FIELD(DISABLE_LZ_NULL_ZCMD_DROP, bool) + GENERATE_FIELD(ENABLE_AZ_THROTTLE, bool) + GENERATE_FIELD(AZ_THROTTLE_COUNT, uint) + GENERATE_FIELD(ENABLE_CRC_UPDATE, bool) + GENERATE_FIELD(CRC_MODE, bool) + GENERATE_FIELD(DISABLE_SAMPLE_COUNTERS, bool) + GENERATE_FIELD(DISABLE_ACCUM, bool) + GENERATE_FIELD(ACCUM_ALLOC_MASK, uint) + GENERATE_FIELD(LINEAR_PERFORMANCE_ENABLE, bool) + GENERATE_FIELD(ACCUM_DATA_FIFO_LIMIT, bool) + GENERATE_FIELD(MEM_EXPORT_TIMEOUT_SELECT, int) + GENERATE_FIELD(MEM_EXPORT_LINEAR_MODE_ENABLE, bool) + GENERATE_FIELD(CRC_SYSTEM, bool) + GENERATE_FIELD(RESERVED6, bool) +END_REGISTER(RB_BC_CONTROL) + +START_REGISTER(RB_EDRAM_INFO) + GENERATE_FIELD(EDRAM_SIZE, EdramSizeX) + GENERATE_FIELD(EDRAM_MAPPING_MODE, uint) + GENERATE_FIELD(EDRAM_RANGE, hex) +END_REGISTER(RB_EDRAM_INFO) + +START_REGISTER(RB_CRC_RD_PORT) + GENERATE_FIELD(CRC_DATA, hex) +END_REGISTER(RB_CRC_RD_PORT) + +START_REGISTER(RB_CRC_CONTROL) + GENERATE_FIELD(CRC_RD_ADVANCE, bool) +END_REGISTER(RB_CRC_CONTROL) + +START_REGISTER(RB_CRC_MASK) + GENERATE_FIELD(CRC_MASK, hex) +END_REGISTER(RB_CRC_MASK) + +START_REGISTER(RB_PERFCOUNTER0_SELECT) + GENERATE_FIELD(PERF_SEL, RB_PERFCNT_SELECT) +END_REGISTER(RB_PERFCOUNTER0_SELECT) + +START_REGISTER(RB_PERFCOUNTER0_LOW) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(RB_PERFCOUNTER0_LOW) + +START_REGISTER(RB_PERFCOUNTER0_HI) + GENERATE_FIELD(PERF_COUNT, int) +END_REGISTER(RB_PERFCOUNTER0_HI) + +START_REGISTER(RB_TOTAL_SAMPLES) + GENERATE_FIELD(TOTAL_SAMPLES, int) +END_REGISTER(RB_TOTAL_SAMPLES) + +START_REGISTER(RB_ZPASS_SAMPLES) + GENERATE_FIELD(ZPASS_SAMPLES, int) +END_REGISTER(RB_ZPASS_SAMPLES) + +START_REGISTER(RB_ZFAIL_SAMPLES) + GENERATE_FIELD(ZFAIL_SAMPLES, int) +END_REGISTER(RB_ZFAIL_SAMPLES) + +START_REGISTER(RB_SFAIL_SAMPLES) + GENERATE_FIELD(SFAIL_SAMPLES, int) +END_REGISTER(RB_SFAIL_SAMPLES) + +START_REGISTER(RB_DEBUG_0) + GENERATE_FIELD(RDREQ_CTL_Z1_PRE_FULL, bool) + GENERATE_FIELD(RDREQ_CTL_Z0_PRE_FULL, bool) + GENERATE_FIELD(RDREQ_CTL_C1_PRE_FULL, bool) + GENERATE_FIELD(RDREQ_CTL_C0_PRE_FULL, bool) + GENERATE_FIELD(RDREQ_E1_ORDERING_FULL, bool) + GENERATE_FIELD(RDREQ_E0_ORDERING_FULL, bool) + GENERATE_FIELD(RDREQ_Z1_FULL, bool) + GENERATE_FIELD(RDREQ_Z0_FULL, bool) + GENERATE_FIELD(RDREQ_C1_FULL, bool) + GENERATE_FIELD(RDREQ_C0_FULL, bool) + GENERATE_FIELD(WRREQ_E1_MACRO_HI_FULL, bool) + GENERATE_FIELD(WRREQ_E1_MACRO_LO_FULL, bool) + GENERATE_FIELD(WRREQ_E0_MACRO_HI_FULL, bool) + GENERATE_FIELD(WRREQ_E0_MACRO_LO_FULL, bool) + GENERATE_FIELD(WRREQ_C_WE_HI_FULL, bool) + GENERATE_FIELD(WRREQ_C_WE_LO_FULL, bool) + GENERATE_FIELD(WRREQ_Z1_FULL, bool) + GENERATE_FIELD(WRREQ_Z0_FULL, bool) + GENERATE_FIELD(WRREQ_C1_FULL, bool) + GENERATE_FIELD(WRREQ_C0_FULL, bool) + GENERATE_FIELD(CMDFIFO_Z1_HOLD_FULL, bool) + GENERATE_FIELD(CMDFIFO_Z0_HOLD_FULL, bool) + GENERATE_FIELD(CMDFIFO_C1_HOLD_FULL, bool) + GENERATE_FIELD(CMDFIFO_C0_HOLD_FULL, bool) + GENERATE_FIELD(CMDFIFO_Z_ORDERING_FULL, bool) + GENERATE_FIELD(CMDFIFO_C_ORDERING_FULL, bool) + GENERATE_FIELD(C_SX_LAT_FULL, bool) + GENERATE_FIELD(C_SX_CMD_FULL, bool) + GENERATE_FIELD(C_EZ_TILE_FULL, bool) + GENERATE_FIELD(C_REQ_FULL, bool) + GENERATE_FIELD(C_MASK_FULL, bool) + GENERATE_FIELD(EZ_INFSAMP_FULL, bool) +END_REGISTER(RB_DEBUG_0) + +START_REGISTER(RB_DEBUG_1) + GENERATE_FIELD(RDREQ_Z1_CMD_EMPTY, bool) + GENERATE_FIELD(RDREQ_Z0_CMD_EMPTY, bool) + GENERATE_FIELD(RDREQ_C1_CMD_EMPTY, bool) + GENERATE_FIELD(RDREQ_C0_CMD_EMPTY, bool) + GENERATE_FIELD(RDREQ_E1_ORDERING_EMPTY, bool) + GENERATE_FIELD(RDREQ_E0_ORDERING_EMPTY, bool) + GENERATE_FIELD(RDREQ_Z1_EMPTY, bool) + GENERATE_FIELD(RDREQ_Z0_EMPTY, bool) + GENERATE_FIELD(RDREQ_C1_EMPTY, bool) + GENERATE_FIELD(RDREQ_C0_EMPTY, bool) + GENERATE_FIELD(WRREQ_E1_MACRO_HI_EMPTY, bool) + GENERATE_FIELD(WRREQ_E1_MACRO_LO_EMPTY, bool) + GENERATE_FIELD(WRREQ_E0_MACRO_HI_EMPTY, bool) + GENERATE_FIELD(WRREQ_E0_MACRO_LO_EMPTY, bool) + GENERATE_FIELD(WRREQ_C_WE_HI_EMPTY, bool) + GENERATE_FIELD(WRREQ_C_WE_LO_EMPTY, bool) + GENERATE_FIELD(WRREQ_Z1_EMPTY, bool) + GENERATE_FIELD(WRREQ_Z0_EMPTY, bool) + GENERATE_FIELD(WRREQ_C1_PRE_EMPTY, bool) + GENERATE_FIELD(WRREQ_C0_PRE_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_Z1_HOLD_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_Z0_HOLD_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_C1_HOLD_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_C0_HOLD_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_Z_ORDERING_EMPTY, bool) + GENERATE_FIELD(CMDFIFO_C_ORDERING_EMPTY, bool) + GENERATE_FIELD(C_SX_LAT_EMPTY, bool) + GENERATE_FIELD(C_SX_CMD_EMPTY, bool) + GENERATE_FIELD(C_EZ_TILE_EMPTY, bool) + GENERATE_FIELD(C_REQ_EMPTY, bool) + GENERATE_FIELD(C_MASK_EMPTY, bool) + GENERATE_FIELD(EZ_INFSAMP_EMPTY, bool) +END_REGISTER(RB_DEBUG_1) + +START_REGISTER(RB_DEBUG_2) + GENERATE_FIELD(TILE_FIFO_COUNT, bool) + GENERATE_FIELD(SX_LAT_FIFO_COUNT, bool) + GENERATE_FIELD(MEM_EXPORT_FLAG, bool) + GENERATE_FIELD(SYSMEM_BLEND_FLAG, bool) + GENERATE_FIELD(CURRENT_TILE_EVENT, bool) + GENERATE_FIELD(EZ_INFTILE_FULL, bool) + GENERATE_FIELD(EZ_MASK_LOWER_FULL, bool) + GENERATE_FIELD(EZ_MASK_UPPER_FULL, bool) + GENERATE_FIELD(Z0_MASK_FULL, bool) + GENERATE_FIELD(Z1_MASK_FULL, bool) + GENERATE_FIELD(Z0_REQ_FULL, bool) + GENERATE_FIELD(Z1_REQ_FULL, bool) + GENERATE_FIELD(Z_SAMP_FULL, bool) + GENERATE_FIELD(Z_TILE_FULL, bool) + GENERATE_FIELD(EZ_INFTILE_EMPTY, bool) + GENERATE_FIELD(EZ_MASK_LOWER_EMPTY, bool) + GENERATE_FIELD(EZ_MASK_UPPER_EMPTY, bool) + GENERATE_FIELD(Z0_MASK_EMPTY, bool) + GENERATE_FIELD(Z1_MASK_EMPTY, bool) + GENERATE_FIELD(Z0_REQ_EMPTY, bool) + GENERATE_FIELD(Z1_REQ_EMPTY, bool) + GENERATE_FIELD(Z_SAMP_EMPTY, bool) + GENERATE_FIELD(Z_TILE_EMPTY, bool) +END_REGISTER(RB_DEBUG_2) + +START_REGISTER(RB_DEBUG_3) + GENERATE_FIELD(ACCUM_VALID, bool) + GENERATE_FIELD(ACCUM_FLUSHING, bool) + GENERATE_FIELD(ACCUM_WRITE_CLEAN_COUNT, bool) + GENERATE_FIELD(ACCUM_INPUT_REG_VALID, bool) + GENERATE_FIELD(ACCUM_DATA_FIFO_CNT, bool) + GENERATE_FIELD(SHD_FULL, bool) + GENERATE_FIELD(SHD_EMPTY, bool) + GENERATE_FIELD(EZ_RETURN_LOWER_EMPTY, bool) + GENERATE_FIELD(EZ_RETURN_UPPER_EMPTY, bool) + GENERATE_FIELD(EZ_RETURN_LOWER_FULL, bool) + GENERATE_FIELD(EZ_RETURN_UPPER_FULL, bool) + GENERATE_FIELD(ZEXP_LOWER_EMPTY, bool) + GENERATE_FIELD(ZEXP_UPPER_EMPTY, bool) + GENERATE_FIELD(ZEXP_LOWER_FULL, bool) + GENERATE_FIELD(ZEXP_UPPER_FULL, bool) +END_REGISTER(RB_DEBUG_3) + +START_REGISTER(RB_DEBUG_4) + GENERATE_FIELD(GMEM_RD_ACCESS_FLAG, bool) + GENERATE_FIELD(GMEM_WR_ACCESS_FLAG, bool) + GENERATE_FIELD(SYSMEM_RD_ACCESS_FLAG, bool) + GENERATE_FIELD(SYSMEM_WR_ACCESS_FLAG, bool) + GENERATE_FIELD(ACCUM_DATA_FIFO_EMPTY, bool) + GENERATE_FIELD(ACCUM_ORDER_FIFO_EMPTY, bool) + GENERATE_FIELD(ACCUM_DATA_FIFO_FULL, bool) + GENERATE_FIELD(ACCUM_ORDER_FIFO_FULL, bool) + GENERATE_FIELD(SYSMEM_WRITE_COUNT_OVERFLOW, bool) + GENERATE_FIELD(CONTEXT_COUNT_DEBUG, bool) +END_REGISTER(RB_DEBUG_4) + +START_REGISTER(RB_FLAG_CONTROL) + GENERATE_FIELD(DEBUG_FLAG_CLEAR, bool) +END_REGISTER(RB_FLAG_CONTROL) + +START_REGISTER(RB_BC_SPARES) + GENERATE_FIELD(RESERVED, bool) +END_REGISTER(RB_BC_SPARES) + +START_REGISTER(BC_DUMMY_CRAYRB_ENUMS) + GENERATE_FIELD(DUMMY_CRAYRB_DEPTH_FORMAT, DepthFormat) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_SWAP, SurfaceSwap) + GENERATE_FIELD(DUMMY_CRAYRB_DEPTH_ARRAY, DepthArray) + GENERATE_FIELD(DUMMY_CRAYRB_ARRAY, ColorArray) + GENERATE_FIELD(DUMMY_CRAYRB_COLOR_FORMAT, ColorFormat) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_NUMBER, SurfaceNumber) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_FORMAT, SurfaceFormat) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_TILING, SurfaceTiling) + GENERATE_FIELD(DUMMY_CRAYRB_SURFACE_ARRAY, SurfaceArray) + GENERATE_FIELD(DUMMY_RB_COPY_DEST_INFO_NUMBER, SurfaceNumberX) +END_REGISTER(BC_DUMMY_CRAYRB_ENUMS) + +START_REGISTER(BC_DUMMY_CRAYRB_MOREENUMS) + GENERATE_FIELD(DUMMY_CRAYRB_COLORARRAYX, ColorArrayX) +END_REGISTER(BC_DUMMY_CRAYRB_MOREENUMS) + diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_ipt.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_ipt.h new file mode 100644 index 000000000000..0e32e421d0a3 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_ipt.h @@ -0,0 +1,95 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _R400IPT_H_ +#define _R400IPT_H_ + +// Hand-generated list from Yamato_PM4_Spec.doc + +#define PM4_PACKET0_NOP 0x00000000 // Empty type-0 packet header +#define PM4_PACKET1_NOP 0x40000000 // Empty type-1 packet header +#define PM4_PACKET2_NOP 0x80000000 // Empty type-2 packet header (reserved) + +#define PM4_COUNT_SHIFT 16 +#define PM4_COUNT_MASK +#define PM4_PACKET_COUNT(__x) ((((__x)-1) << PM4_COUNT_SHIFT) & 0x3fff0000) +// Type 3 packet headers + +#define PM4_PACKET3_NOP 0xC0001000 // Do nothing. +#define PM4_PACKET3_IB_PREFETCH_END 0xC0001700 // Internal Packet Used Only by CP +#define PM4_PACKET3_SUBBLK_PREFETCH 0xC0001F00 // Internal Packet Used Only by CP + +#define PM4_PACKET3_INSTR_PREFETCH 0xC0002000 // Internal Packet Used Only by CP +#define PM4_PACKET3_REG_RMW 0xC0002100 // Register Read-Modify-Write New for R400 +#define PM4_PACKET3_DRAW_INDX 0xC0002200 // Initiate fetch of index buffer New for R400 +#define PM4_PACKET3_VIZ_QUERY 0xC0002300 // Begin/End initiator for Viz Query extent processing New for R400 +#define PM4_PACKET3_SET_STATE 0xC0002500 // Fetch State Sub-Blocks and Initiate Shader Code DMAs New for R400 +#define PM4_PACKET3_WAIT_FOR_IDLE 0xC0002600 // Wait for the engine to be idle. +#define PM4_PACKET3_IM_LOAD 0xC0002700 // Load Sequencer Instruction Memory for a Specific Shader New for R400 +#define PM4_PACKET3_IM_LOAD_IMMEDIATE 0xC0002B00 // Load Sequencer Instruction Memory for a Specific Shader New for R400 +#define PM4_PACKET3_SET_CONSTANT 0xC0002D00 // Load Constant Into Chip & Shadow to Memory New for R400 +#define PM4_PACKET3_LOAD_CONSTANT_CONTEXT 0xC0002E00 // Load All Constants from a Location in Memory New for R400 +#define PM4_PACKET3_LOAD_ALU_CONSTANT 0xC0002F00 // Load ALu constants from a location in memory - similar to SET_CONSTANT but tuned for performance when loading only ALU constants + +#define PM4_PACKET3_DRAW_INDX_BIN 0xC0003400 // Initiate fetch of index buffer and BIN info used for visibility test +#define PM4_PACKET3_3D_DRAW_INDX_2_BIN 0xC0003500 // Draw using supplied indices and initiate fetch of BIN info for visibility test +#define PM4_PACKET3_3D_DRAW_INDX_2 0xC0003600 // Draw primitives using vertex buf and Indices in this packet. Pkt does NOT contain vtx fmt +#define PM4_PACKET3_INDIRECT_BUFFER_PFD 0xC0003700 +#define PM4_PACKET3_INVALIDATE_STATE 0xC0003B00 // Selective Invalidation of State Pointers New for R400 +#define PM4_PACKET3_WAIT_REG_MEM 0xC0003C00 // Wait Until a Register or Memory Location is a Specific Value. New for R400 +#define PM4_PACKET3_MEM_WRITE 0xC0003D00 // Write DWORD to Memory For Synchronization New for R400 +#define PM4_PACKET3_REG_TO_MEM 0xC0003E00 // Reads Register in Chip and Writes to Memory New for R400 +#define PM4_PACKET3_INDIRECT_BUFFER 0xC0003F00 // Indirect Buffer Dispatch - Pre-fetch parser uses this packet type in determining to pre-fetch the indirect buffer. Supported + +#define PM4_PACKET3_CP_INTERRUPT 0xC0004000 // Generate Interrupt from the Command Stream New for R400 +#define PM4_PACKET3_COND_EXEC 0xC0004400 // Conditional execution of a sequence of packets +#define PM4_PACKET3_COND_WRITE 0xC0004500 // Conditional Write to Memory New for R400 +#define PM4_PACKET3_EVENT_WRITE 0xC0004600 // Generate An Event that Creates a Write to Memory when Completed New for R400 +#define PM4_PACKET3_INSTR_MATCH 0xC0004700 // Internal Packet Used Only by CP +#define PM4_PACKET3_ME_INIT 0xC0004800 // Initialize CP's Micro Engine New for R400 +#define PM4_PACKET3_CONST_PREFETCH 0xC0004900 // Internal packet used only by CP +#define PM4_PACKET3_MEM_WRITE_CNTR 0xC0004F00 + +#define PM4_PACKET3_SET_BIN_MASK 0xC0005000 // Sets the 64-bit BIN_MASK register in the PFP +#define PM4_PACKET3_SET_BIN_SELECT 0xC0005100 // Sets the 64-bit BIN_SELECT register in the PFP +#define PM4_PACKET3_WAIT_REG_EQ 0xC0005200 // Wait until a register location is equal to a specific value +#define PM4_PACKET3_WAIT_REG_GTE 0xC0005300 // Wait until a register location is greater than or equal to a specific value +#define PM4_PACKET3_INCR_UPDT_STATE 0xC0005500 // Internal Packet Used Only by CP +#define PM4_PACKET3_INCR_UPDT_CONST 0xC0005600 // Internal Packet Used Only by CP +#define PM4_PACKET3_INCR_UPDT_INSTR 0xC0005700 // Internal Packet Used Only by CP +#define PM4_PACKET3_EVENT_WRITE_SHD 0xC0005800 // Generate a VS|PS_Done Event. +#define PM4_PACKET3_EVENT_WRITE_CFL 0xC0005900 // Generate a Cach Flush Done Event +#define PM4_PACKET3_EVENT_WRITE_ZPD 0xC0005B00 // Generate a Cach Flush Done Event +#define PM4_PACKET3_WAIT_UNTIL_READ 0xC0005C00 // Wait Until a Read completes. +#define PM4_PACKET3_WAIT_IB_PFD_COMPLETE 0xC0005D00 // Wait Until all Base/Size writes from an IB_PFD packet have completed. +#define PM4_PACKET3_CONTEXT_UPDATE 0xC0005E00 // Updates the current context if needed. + + /****** New Opcodes For R400 (all decode values are TBD) ******/ + + +#endif // _R400IPT_H_ diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_mask.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_mask.h new file mode 100644 index 000000000000..52ced9af774c --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_mask.h @@ -0,0 +1,5908 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_MASK_HEADER) +#define _yamato_MASK_HEADER + +// PA_CL_VPORT_XSCALE +#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xffffffffL + +// PA_CL_VPORT_XOFFSET +#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xffffffffL + +// PA_CL_VPORT_YSCALE +#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xffffffffL + +// PA_CL_VPORT_YOFFSET +#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xffffffffL + +// PA_CL_VPORT_ZSCALE +#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xffffffffL + +// PA_CL_VPORT_ZOFFSET +#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xffffffffL + +// PA_CL_VTE_CNTL +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x00000001L +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA 0x00000001L +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x00000002L +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA 0x00000002L +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x00000004L +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA 0x00000004L +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x00000008L +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA 0x00000008L +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x00000010L +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA 0x00000010L +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x00000020L +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA 0x00000020L +#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100L +#define PA_CL_VTE_CNTL__VTX_XY_FMT 0x00000100L +#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200L +#define PA_CL_VTE_CNTL__VTX_Z_FMT 0x00000200L +#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x00000400L +#define PA_CL_VTE_CNTL__VTX_W0_FMT 0x00000400L +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x00000800L +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF 0x00000800L + +// PA_CL_CLIP_CNTL +#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x00010000L +#define PA_CL_CLIP_CNTL__CLIP_DISABLE 0x00010000L +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000L +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA 0x00040000L +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x00080000L +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF 0x00080000L +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x00100000L +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT 0x00100000L +#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x00200000L +#define PA_CL_CLIP_CNTL__VTX_KILL_OR 0x00200000L +#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN_MASK 0x00400000L +#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN 0x00400000L +#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN_MASK 0x00800000L +#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN 0x00800000L +#define PA_CL_CLIP_CNTL__W_NAN_RETAIN_MASK 0x01000000L +#define PA_CL_CLIP_CNTL__W_NAN_RETAIN 0x01000000L + +// PA_CL_GB_VERT_CLIP_ADJ +#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffffL + +// PA_CL_GB_VERT_DISC_ADJ +#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xffffffffL + +// PA_CL_GB_HORZ_CLIP_ADJ +#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffffL + +// PA_CL_GB_HORZ_DISC_ADJ +#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xffffffffL + +// PA_CL_ENHANCE +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x00000001L +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA 0x00000001L +#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000L +#define PA_CL_ENHANCE__ECO_SPARE3 0x10000000L +#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000L +#define PA_CL_ENHANCE__ECO_SPARE2 0x20000000L +#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000L +#define PA_CL_ENHANCE__ECO_SPARE1 0x40000000L +#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000L +#define PA_CL_ENHANCE__ECO_SPARE0 0x80000000L + +// PA_SC_ENHANCE +#define PA_SC_ENHANCE__ECO_SPARE3_MASK 0x10000000L +#define PA_SC_ENHANCE__ECO_SPARE3 0x10000000L +#define PA_SC_ENHANCE__ECO_SPARE2_MASK 0x20000000L +#define PA_SC_ENHANCE__ECO_SPARE2 0x20000000L +#define PA_SC_ENHANCE__ECO_SPARE1_MASK 0x40000000L +#define PA_SC_ENHANCE__ECO_SPARE1 0x40000000L +#define PA_SC_ENHANCE__ECO_SPARE0_MASK 0x80000000L +#define PA_SC_ENHANCE__ECO_SPARE0 0x80000000L + +// PA_SU_VTX_CNTL +#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x00000001L +#define PA_SU_VTX_CNTL__PIX_CENTER 0x00000001L +#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x00000006L +#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x00000038L + +// PA_SU_POINT_SIZE +#define PA_SU_POINT_SIZE__HEIGHT_MASK 0x0000ffffL +#define PA_SU_POINT_SIZE__WIDTH_MASK 0xffff0000L + +// PA_SU_POINT_MINMAX +#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0x0000ffffL +#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xffff0000L + +// PA_SU_LINE_CNTL +#define PA_SU_LINE_CNTL__WIDTH_MASK 0x0000ffffL + +// PA_SU_FACE_DATA +#define PA_SU_FACE_DATA__BASE_ADDR_MASK 0xffffffe0L + +// PA_SU_SC_MODE_CNTL +#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x00000001L +#define PA_SU_SC_MODE_CNTL__CULL_FRONT 0x00000001L +#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x00000002L +#define PA_SU_SC_MODE_CNTL__CULL_BACK 0x00000002L +#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x00000004L +#define PA_SU_SC_MODE_CNTL__FACE 0x00000004L +#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x00000018L +#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0x000000e0L +#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x00000700L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE 0x00000800L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x00001000L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE 0x00001000L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x00002000L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE 0x00002000L +#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE_MASK 0x00008000L +#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE 0x00008000L +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000L +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE 0x00010000L +#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE_MASK 0x00040000L +#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE 0x00040000L +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x00080000L +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST 0x00080000L +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x00100000L +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS 0x00100000L +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x00200000L +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA 0x00200000L +#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE_MASK 0x00800000L +#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE 0x00800000L +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI_MASK 0x02000000L +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI 0x02000000L +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK 0x04000000L +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE 0x04000000L +#define PA_SU_SC_MODE_CNTL__CLAMPED_FACENESS_MASK 0x10000000L +#define PA_SU_SC_MODE_CNTL__CLAMPED_FACENESS 0x10000000L +#define PA_SU_SC_MODE_CNTL__ZERO_AREA_FACENESS_MASK 0x20000000L +#define PA_SU_SC_MODE_CNTL__ZERO_AREA_FACENESS 0x20000000L +#define PA_SU_SC_MODE_CNTL__FACE_KILL_ENABLE_MASK 0x40000000L +#define PA_SU_SC_MODE_CNTL__FACE_KILL_ENABLE 0x40000000L +#define PA_SU_SC_MODE_CNTL__FACE_WRITE_ENABLE_MASK 0x80000000L +#define PA_SU_SC_MODE_CNTL__FACE_WRITE_ENABLE 0x80000000L + +// PA_SU_POLY_OFFSET_FRONT_SCALE +#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xffffffffL + +// PA_SU_POLY_OFFSET_FRONT_OFFSET +#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xffffffffL + +// PA_SU_POLY_OFFSET_BACK_SCALE +#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xffffffffL + +// PA_SU_POLY_OFFSET_BACK_OFFSET +#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER0_SELECT +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SU_PERFCOUNTER1_SELECT +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SU_PERFCOUNTER2_SELECT +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SU_PERFCOUNTER3_SELECT +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SU_PERFCOUNTER0_LOW +#define PA_SU_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER0_HI +#define PA_SU_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_SU_PERFCOUNTER1_LOW +#define PA_SU_PERFCOUNTER1_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER1_HI +#define PA_SU_PERFCOUNTER1_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_SU_PERFCOUNTER2_LOW +#define PA_SU_PERFCOUNTER2_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER2_HI +#define PA_SU_PERFCOUNTER2_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_SU_PERFCOUNTER3_LOW +#define PA_SU_PERFCOUNTER3_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SU_PERFCOUNTER3_HI +#define PA_SU_PERFCOUNTER3_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_SC_WINDOW_OFFSET +#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0x00007fffL +#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0x7fff0000L + +// PA_SC_AA_CONFIG +#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x00000007L +#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x0001e000L + +// PA_SC_AA_MASK +#define PA_SC_AA_MASK__AA_MASK_MASK 0x0000ffffL + +// PA_SC_LINE_STIPPLE +#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0x0000ffffL +#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0x00ff0000L +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000L +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER 0x10000000L +#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000L + +// PA_SC_LINE_CNTL +#define PA_SC_LINE_CNTL__BRES_CNTL_MASK 0x000000ffL +#define PA_SC_LINE_CNTL__USE_BRES_CNTL_MASK 0x00000100L +#define PA_SC_LINE_CNTL__USE_BRES_CNTL 0x00000100L +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x00000200L +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH 0x00000200L +#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x00000400L +#define PA_SC_LINE_CNTL__LAST_PIXEL 0x00000400L + +// PA_SC_WINDOW_SCISSOR_TL +#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x00003fffL +#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x3fff0000L +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE 0x80000000L + +// PA_SC_WINDOW_SCISSOR_BR +#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x00003fffL +#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x3fff0000L + +// PA_SC_SCREEN_SCISSOR_TL +#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0x00007fffL +#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0x7fff0000L + +// PA_SC_SCREEN_SCISSOR_BR +#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0x00007fffL +#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0x7fff0000L + +// PA_SC_VIZ_QUERY +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA_MASK 0x00000001L +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA 0x00000001L +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ID_MASK 0x0000003eL +#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z_MASK 0x00000080L +#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z 0x00000080L + +// PA_SC_VIZ_QUERY_STATUS +#define PA_SC_VIZ_QUERY_STATUS__STATUS_BITS_MASK 0xffffffffL + +// PA_SC_LINE_STIPPLE_STATE +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0x0000000fL +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0x0000ff00L + +// PA_SC_PERFCOUNTER0_SELECT +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// PA_SC_PERFCOUNTER0_LOW +#define PA_SC_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// PA_SC_PERFCOUNTER0_HI +#define PA_SC_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// PA_CL_CNTL_STATUS +#define PA_CL_CNTL_STATUS__CL_BUSY_MASK 0x80000000L +#define PA_CL_CNTL_STATUS__CL_BUSY 0x80000000L + +// PA_SU_CNTL_STATUS +#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000L +#define PA_SU_CNTL_STATUS__SU_BUSY 0x80000000L + +// PA_SC_CNTL_STATUS +#define PA_SC_CNTL_STATUS__SC_BUSY_MASK 0x80000000L +#define PA_SC_CNTL_STATUS__SC_BUSY 0x80000000L + +// PA_SU_DEBUG_CNTL +#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK 0x0000001fL + +// PA_SU_DEBUG_DATA +#define PA_SU_DEBUG_DATA__DATA_MASK 0xffffffffL + +// CLIPPER_DEBUG_REG00 +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK 0x00000001L +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write 0x00000001L +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full_MASK 0x00000002L +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full 0x00000002L +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK 0x00000004L +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write 0x00000004L +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK 0x00000008L +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full 0x00000008L +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x00000010L +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty 0x00000010L +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x00000020L +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full 0x00000020L +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x00000040L +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty 0x00000040L +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK 0x00000080L +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full 0x00000080L +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK 0x00000100L +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty 0x00000100L +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK 0x00000200L +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full 0x00000200L +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK 0x00000400L +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty 0x00000400L +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK 0x00000800L +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full 0x00000800L +#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x00001000L +#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty 0x00001000L +#define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK 0x00002000L +#define CLIPPER_DEBUG_REG00__clipcode_fifo_full 0x00002000L +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x00004000L +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty 0x00004000L +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x00008000L +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full 0x00008000L +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x00010000L +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty 0x00010000L +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x00020000L +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full 0x00020000L +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x00040000L +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty 0x00040000L +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x00080000L +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full 0x00080000L +#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK 0xfff00000L + +// CLIPPER_DEBUG_REG01 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet_MASK 0x00000001L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet 0x00000001L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot_MASK 0x00000002L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot 0x00000002L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0x0000001cL +#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim_MASK 0x00000020L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim 0x00000020L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x00000040L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive 0x00000040L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_2_MASK 0x00000780L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_1_MASK 0x00007800L +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_0_MASK 0x00078000L +#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK 0x00380000L +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0x00c00000L +#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK 0xff000000L + +// CLIPPER_DEBUG_REG02 +#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO1_MASK 0x001fffffL +#define CLIPPER_DEBUG_REG02__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00e00000L +#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO0_MASK 0x7f000000L +#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000L +#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid 0x80000000L + +// CLIPPER_DEBUG_REG03 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO3_MASK 0x00000007L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x00000008L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive 0x00000008L +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO2_MASK 0x00000070L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x00000080L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive 0x00000080L +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO1_MASK 0x000fff00L +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x03f00000L +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO0_MASK 0xfc000000L + +// CLIPPER_DEBUG_REG04 +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO2_MASK 0x00000007L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x00000008L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot 0x00000008L +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO1_MASK 0x00000070L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x00000080L +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event 0x00000080L +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO0_MASK 0xffffff00L + +// CLIPPER_DEBUG_REG05 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx_MASK 0x00000001L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx 0x00000001L +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO3_MASK 0x00000006L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x00000038L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_event_id_MASK 0x00000fc0L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0000f000L +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO2_MASK 0x00030000L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x003c0000L +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO1_MASK 0x00c00000L +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x0f000000L +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO0_MASK 0xf0000000L + +// CLIPPER_DEBUG_REG09 +#define CLIPPER_DEBUG_REG09__clprim_in_back_event_MASK 0x00000001L +#define CLIPPER_DEBUG_REG09__clprim_in_back_event 0x00000001L +#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive_MASK 0x00000002L +#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive 0x00000002L +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_2_MASK 0x0000003cL +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO2_MASK 0x000000c0L +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_1_MASK 0x00000f00L +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO1_MASK 0x00003000L +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_0_MASK 0x0003c000L +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO0_MASK 0x000c0000L +#define CLIPPER_DEBUG_REG09__prim_back_valid_MASK 0x00100000L +#define CLIPPER_DEBUG_REG09__prim_back_valid 0x00100000L +#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_out_cnt_MASK 0x01e00000L +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_orig_vertices_MASK 0x06000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait_MASK 0x08000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait 0x08000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty_MASK 0x10000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty 0x10000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full_MASK 0x20000000L +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full 0x20000000L +#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_load_MASK 0xc0000000L + +// CLIPPER_DEBUG_REG10 +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x0000000fL +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO3_MASK 0x00000030L +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x000003c0L +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO2_MASK 0x00000c00L +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x0000f000L +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO1_MASK 0x00030000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx_MASK 0x00040000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx 0x00040000L +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO0_MASK 0x00180000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet_MASK 0x00200000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet 0x00200000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot_MASK 0x00400000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot 0x00400000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_deallocate_slot_MASK 0x03800000L +#define CLIPPER_DEBUG_REG10__clprim_in_back_event_id_MASK 0xfc000000L + +// CLIPPER_DEBUG_REG11 +#define CLIPPER_DEBUG_REG11__vertval_bits_vertex_vertex_store_msb_MASK 0x0000000fL +#define CLIPPER_DEBUG_REG11__ALWAYS_ZERO_MASK 0xfffffff0L + +// CLIPPER_DEBUG_REG12 +#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x00000003L +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO2_MASK 0x0000001cL +#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty_MASK 0x00000020L +#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty 0x00000020L +#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x000007c0L +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO1_MASK 0x00007800L +#define CLIPPER_DEBUG_REG12__vertval_bits_vertex_cc_next_valid_MASK 0x00078000L +#define CLIPPER_DEBUG_REG12__clipcc_vertex_store_indx_MASK 0x00180000L +#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid_MASK 0x00200000L +#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid 0x00200000L +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO0_MASK 0xffc00000L + +// CLIPPER_DEBUG_REG13 +#define CLIPPER_DEBUG_REG13__sm0_clip_vert_cnt_MASK 0x0000000fL +#define CLIPPER_DEBUG_REG13__sm0_prim_end_state_MASK 0x000007f0L +#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO1_MASK 0x00003800L +#define CLIPPER_DEBUG_REG13__sm0_vertex_clip_cnt_MASK 0x0003c000L +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1_MASK 0x00040000L +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1 0x00040000L +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0_MASK 0x00080000L +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0 0x00080000L +#define CLIPPER_DEBUG_REG13__sm0_current_state_MASK 0x07f00000L +#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO0_MASK 0xf8000000L + +// SXIFCCG_DEBUG_REG0 +#define SXIFCCG_DEBUG_REG0__nan_kill_flag_MASK 0x0000000fL +#define SXIFCCG_DEBUG_REG0__position_address_MASK 0x00000070L +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO2_MASK 0x00000380L +#define SXIFCCG_DEBUG_REG0__point_address_MASK 0x00001c00L +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO1_MASK 0x0000e000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx_MASK 0x00010000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx 0x00010000L +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO0_MASK 0x00060000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask_MASK 0x00780000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci_MASK 0x3f800000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc_MASK 0x40000000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc 0x40000000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel_MASK 0x80000000L +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel 0x80000000L + +// SXIFCCG_DEBUG_REG1 +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO3_MASK 0x00000003L +#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_MASK 0x0000000cL +#define SXIFCCG_DEBUG_REG1__available_positions_MASK 0x00000070L +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO2_MASK 0x00000780L +#define SXIFCCG_DEBUG_REG1__sx_pending_advance_MASK 0x00000800L +#define SXIFCCG_DEBUG_REG1__sx_pending_advance 0x00000800L +#define SXIFCCG_DEBUG_REG1__sx_receive_indx_MASK 0x00007000L +#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector_MASK 0x00008000L +#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector 0x00008000L +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO1_MASK 0x000f0000L +#define SXIFCCG_DEBUG_REG1__aux_sel_MASK 0x00100000L +#define SXIFCCG_DEBUG_REG1__aux_sel 0x00100000L +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO0_MASK 0x00600000L +#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_MASK 0x01800000L +#define SXIFCCG_DEBUG_REG1__param_cache_base_MASK 0xfe000000L + +// SXIFCCG_DEBUG_REG2 +#define SXIFCCG_DEBUG_REG2__sx_sent_MASK 0x00000001L +#define SXIFCCG_DEBUG_REG2__sx_sent 0x00000001L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3_MASK 0x00000002L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3 0x00000002L +#define SXIFCCG_DEBUG_REG2__sx_aux_MASK 0x00000004L +#define SXIFCCG_DEBUG_REG2__sx_aux 0x00000004L +#define SXIFCCG_DEBUG_REG2__sx_request_indx_MASK 0x000001f8L +#define SXIFCCG_DEBUG_REG2__req_active_verts_MASK 0x0000fe00L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2_MASK 0x00010000L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2 0x00010000L +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx_MASK 0x00020000L +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx 0x00020000L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO1_MASK 0x000c0000L +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts_MASK 0x00300000L +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO0_MASK 0x03c00000L +#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded_MASK 0x04000000L +#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded 0x04000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty_MASK 0x08000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty 0x08000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full_MASK 0x10000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full 0x10000000L +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_contents_MASK 0xe0000000L + +// SXIFCCG_DEBUG_REG3 +#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable_MASK 0x0000000fL +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3_MASK 0x00000010L +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3 0x00000010L +#define SXIFCCG_DEBUG_REG3__available_positions_MASK 0x000000e0L +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO2_MASK 0x00000f00L +#define SXIFCCG_DEBUG_REG3__current_state_MASK 0x00003000L +#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty_MASK 0x00004000L +#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty 0x00004000L +#define SXIFCCG_DEBUG_REG3__vertex_fifo_full_MASK 0x00008000L +#define SXIFCCG_DEBUG_REG3__vertex_fifo_full 0x00008000L +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO1_MASK 0x00030000L +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty_MASK 0x00040000L +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty 0x00040000L +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full_MASK 0x00080000L +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full 0x00080000L +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty_MASK 0x00100000L +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty 0x00100000L +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full_MASK 0x00200000L +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full 0x00200000L +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO0_MASK 0xffc00000L + +// SETUP_DEBUG_REG0 +#define SETUP_DEBUG_REG0__su_cntl_state_MASK 0x0000001fL +#define SETUP_DEBUG_REG0__pmode_state_MASK 0x000007e0L +#define SETUP_DEBUG_REG0__ge_stallb_MASK 0x00000800L +#define SETUP_DEBUG_REG0__ge_stallb 0x00000800L +#define SETUP_DEBUG_REG0__geom_enable_MASK 0x00001000L +#define SETUP_DEBUG_REG0__geom_enable 0x00001000L +#define SETUP_DEBUG_REG0__su_clip_baryc_rtr_MASK 0x00002000L +#define SETUP_DEBUG_REG0__su_clip_baryc_rtr 0x00002000L +#define SETUP_DEBUG_REG0__su_clip_rtr_MASK 0x00004000L +#define SETUP_DEBUG_REG0__su_clip_rtr 0x00004000L +#define SETUP_DEBUG_REG0__pfifo_busy_MASK 0x00008000L +#define SETUP_DEBUG_REG0__pfifo_busy 0x00008000L +#define SETUP_DEBUG_REG0__su_cntl_busy_MASK 0x00010000L +#define SETUP_DEBUG_REG0__su_cntl_busy 0x00010000L +#define SETUP_DEBUG_REG0__geom_busy_MASK 0x00020000L +#define SETUP_DEBUG_REG0__geom_busy 0x00020000L + +// SETUP_DEBUG_REG1 +#define SETUP_DEBUG_REG1__y_sort0_gated_17_4_MASK 0x00003fffL +#define SETUP_DEBUG_REG1__x_sort0_gated_17_4_MASK 0x0fffc000L + +// SETUP_DEBUG_REG2 +#define SETUP_DEBUG_REG2__y_sort1_gated_17_4_MASK 0x00003fffL +#define SETUP_DEBUG_REG2__x_sort1_gated_17_4_MASK 0x0fffc000L + +// SETUP_DEBUG_REG3 +#define SETUP_DEBUG_REG3__y_sort2_gated_17_4_MASK 0x00003fffL +#define SETUP_DEBUG_REG3__x_sort2_gated_17_4_MASK 0x0fffc000L + +// SETUP_DEBUG_REG4 +#define SETUP_DEBUG_REG4__attr_indx_sort0_gated_MASK 0x000007ffL +#define SETUP_DEBUG_REG4__null_prim_gated_MASK 0x00000800L +#define SETUP_DEBUG_REG4__null_prim_gated 0x00000800L +#define SETUP_DEBUG_REG4__backfacing_gated_MASK 0x00001000L +#define SETUP_DEBUG_REG4__backfacing_gated 0x00001000L +#define SETUP_DEBUG_REG4__st_indx_gated_MASK 0x0000e000L +#define SETUP_DEBUG_REG4__clipped_gated_MASK 0x00010000L +#define SETUP_DEBUG_REG4__clipped_gated 0x00010000L +#define SETUP_DEBUG_REG4__dealloc_slot_gated_MASK 0x000e0000L +#define SETUP_DEBUG_REG4__xmajor_gated_MASK 0x00100000L +#define SETUP_DEBUG_REG4__xmajor_gated 0x00100000L +#define SETUP_DEBUG_REG4__diamond_rule_gated_MASK 0x00600000L +#define SETUP_DEBUG_REG4__type_gated_MASK 0x03800000L +#define SETUP_DEBUG_REG4__fpov_gated_MASK 0x04000000L +#define SETUP_DEBUG_REG4__fpov_gated 0x04000000L +#define SETUP_DEBUG_REG4__pmode_prim_gated_MASK 0x08000000L +#define SETUP_DEBUG_REG4__pmode_prim_gated 0x08000000L +#define SETUP_DEBUG_REG4__event_gated_MASK 0x10000000L +#define SETUP_DEBUG_REG4__event_gated 0x10000000L +#define SETUP_DEBUG_REG4__eop_gated_MASK 0x20000000L +#define SETUP_DEBUG_REG4__eop_gated 0x20000000L + +// SETUP_DEBUG_REG5 +#define SETUP_DEBUG_REG5__attr_indx_sort2_gated_MASK 0x000007ffL +#define SETUP_DEBUG_REG5__attr_indx_sort1_gated_MASK 0x003ff800L +#define SETUP_DEBUG_REG5__provoking_vtx_gated_MASK 0x00c00000L +#define SETUP_DEBUG_REG5__event_id_gated_MASK 0x1f000000L + +// PA_SC_DEBUG_CNTL +#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK 0x0000001fL + +// PA_SC_DEBUG_DATA +#define PA_SC_DEBUG_DATA__DATA_MASK 0xffffffffL + +// SC_DEBUG_0 +#define SC_DEBUG_0__pa_freeze_b1_MASK 0x00000001L +#define SC_DEBUG_0__pa_freeze_b1 0x00000001L +#define SC_DEBUG_0__pa_sc_valid_MASK 0x00000002L +#define SC_DEBUG_0__pa_sc_valid 0x00000002L +#define SC_DEBUG_0__pa_sc_phase_MASK 0x0000001cL +#define SC_DEBUG_0__cntx_cnt_MASK 0x00000fe0L +#define SC_DEBUG_0__decr_cntx_cnt_MASK 0x00001000L +#define SC_DEBUG_0__decr_cntx_cnt 0x00001000L +#define SC_DEBUG_0__incr_cntx_cnt_MASK 0x00002000L +#define SC_DEBUG_0__incr_cntx_cnt 0x00002000L +#define SC_DEBUG_0__trigger_MASK 0x80000000L +#define SC_DEBUG_0__trigger 0x80000000L + +// SC_DEBUG_1 +#define SC_DEBUG_1__em_state_MASK 0x00000007L +#define SC_DEBUG_1__em1_data_ready_MASK 0x00000008L +#define SC_DEBUG_1__em1_data_ready 0x00000008L +#define SC_DEBUG_1__em2_data_ready_MASK 0x00000010L +#define SC_DEBUG_1__em2_data_ready 0x00000010L +#define SC_DEBUG_1__move_em1_to_em2_MASK 0x00000020L +#define SC_DEBUG_1__move_em1_to_em2 0x00000020L +#define SC_DEBUG_1__ef_data_ready_MASK 0x00000040L +#define SC_DEBUG_1__ef_data_ready 0x00000040L +#define SC_DEBUG_1__ef_state_MASK 0x00000180L +#define SC_DEBUG_1__pipe_valid_MASK 0x00000200L +#define SC_DEBUG_1__pipe_valid 0x00000200L +#define SC_DEBUG_1__trigger_MASK 0x80000000L +#define SC_DEBUG_1__trigger 0x80000000L + +// SC_DEBUG_2 +#define SC_DEBUG_2__rc_rtr_dly_MASK 0x00000001L +#define SC_DEBUG_2__rc_rtr_dly 0x00000001L +#define SC_DEBUG_2__qmask_ff_alm_full_d1_MASK 0x00000002L +#define SC_DEBUG_2__qmask_ff_alm_full_d1 0x00000002L +#define SC_DEBUG_2__pipe_freeze_b_MASK 0x00000008L +#define SC_DEBUG_2__pipe_freeze_b 0x00000008L +#define SC_DEBUG_2__prim_rts_MASK 0x00000010L +#define SC_DEBUG_2__prim_rts 0x00000010L +#define SC_DEBUG_2__next_prim_rts_dly_MASK 0x00000020L +#define SC_DEBUG_2__next_prim_rts_dly 0x00000020L +#define SC_DEBUG_2__next_prim_rtr_dly_MASK 0x00000040L +#define SC_DEBUG_2__next_prim_rtr_dly 0x00000040L +#define SC_DEBUG_2__pre_stage1_rts_d1_MASK 0x00000080L +#define SC_DEBUG_2__pre_stage1_rts_d1 0x00000080L +#define SC_DEBUG_2__stage0_rts_MASK 0x00000100L +#define SC_DEBUG_2__stage0_rts 0x00000100L +#define SC_DEBUG_2__phase_rts_dly_MASK 0x00000200L +#define SC_DEBUG_2__phase_rts_dly 0x00000200L +#define SC_DEBUG_2__end_of_prim_s1_dly_MASK 0x00008000L +#define SC_DEBUG_2__end_of_prim_s1_dly 0x00008000L +#define SC_DEBUG_2__pass_empty_prim_s1_MASK 0x00010000L +#define SC_DEBUG_2__pass_empty_prim_s1 0x00010000L +#define SC_DEBUG_2__event_id_s1_MASK 0x003e0000L +#define SC_DEBUG_2__event_s1_MASK 0x00400000L +#define SC_DEBUG_2__event_s1 0x00400000L +#define SC_DEBUG_2__trigger_MASK 0x80000000L +#define SC_DEBUG_2__trigger 0x80000000L + +// SC_DEBUG_3 +#define SC_DEBUG_3__x_curr_s1_MASK 0x000007ffL +#define SC_DEBUG_3__y_curr_s1_MASK 0x003ff800L +#define SC_DEBUG_3__trigger_MASK 0x80000000L +#define SC_DEBUG_3__trigger 0x80000000L + +// SC_DEBUG_4 +#define SC_DEBUG_4__y_end_s1_MASK 0x00003fffL +#define SC_DEBUG_4__y_start_s1_MASK 0x0fffc000L +#define SC_DEBUG_4__y_dir_s1_MASK 0x10000000L +#define SC_DEBUG_4__y_dir_s1 0x10000000L +#define SC_DEBUG_4__trigger_MASK 0x80000000L +#define SC_DEBUG_4__trigger 0x80000000L + +// SC_DEBUG_5 +#define SC_DEBUG_5__x_end_s1_MASK 0x00003fffL +#define SC_DEBUG_5__x_start_s1_MASK 0x0fffc000L +#define SC_DEBUG_5__x_dir_s1_MASK 0x10000000L +#define SC_DEBUG_5__x_dir_s1 0x10000000L +#define SC_DEBUG_5__trigger_MASK 0x80000000L +#define SC_DEBUG_5__trigger 0x80000000L + +// SC_DEBUG_6 +#define SC_DEBUG_6__z_ff_empty_MASK 0x00000001L +#define SC_DEBUG_6__z_ff_empty 0x00000001L +#define SC_DEBUG_6__qmcntl_ff_empty_MASK 0x00000002L +#define SC_DEBUG_6__qmcntl_ff_empty 0x00000002L +#define SC_DEBUG_6__xy_ff_empty_MASK 0x00000004L +#define SC_DEBUG_6__xy_ff_empty 0x00000004L +#define SC_DEBUG_6__event_flag_MASK 0x00000008L +#define SC_DEBUG_6__event_flag 0x00000008L +#define SC_DEBUG_6__z_mask_needed_MASK 0x00000010L +#define SC_DEBUG_6__z_mask_needed 0x00000010L +#define SC_DEBUG_6__state_MASK 0x000000e0L +#define SC_DEBUG_6__state_delayed_MASK 0x00000700L +#define SC_DEBUG_6__data_valid_MASK 0x00000800L +#define SC_DEBUG_6__data_valid 0x00000800L +#define SC_DEBUG_6__data_valid_d_MASK 0x00001000L +#define SC_DEBUG_6__data_valid_d 0x00001000L +#define SC_DEBUG_6__tilex_delayed_MASK 0x003fe000L +#define SC_DEBUG_6__tiley_delayed_MASK 0x7fc00000L +#define SC_DEBUG_6__trigger_MASK 0x80000000L +#define SC_DEBUG_6__trigger 0x80000000L + +// SC_DEBUG_7 +#define SC_DEBUG_7__event_flag_MASK 0x00000001L +#define SC_DEBUG_7__event_flag 0x00000001L +#define SC_DEBUG_7__deallocate_MASK 0x0000000eL +#define SC_DEBUG_7__fposition_MASK 0x00000010L +#define SC_DEBUG_7__fposition 0x00000010L +#define SC_DEBUG_7__sr_prim_we_MASK 0x00000020L +#define SC_DEBUG_7__sr_prim_we 0x00000020L +#define SC_DEBUG_7__last_tile_MASK 0x00000040L +#define SC_DEBUG_7__last_tile 0x00000040L +#define SC_DEBUG_7__tile_ff_we_MASK 0x00000080L +#define SC_DEBUG_7__tile_ff_we 0x00000080L +#define SC_DEBUG_7__qs_data_valid_MASK 0x00000100L +#define SC_DEBUG_7__qs_data_valid 0x00000100L +#define SC_DEBUG_7__qs_q0_y_MASK 0x00000600L +#define SC_DEBUG_7__qs_q0_x_MASK 0x00001800L +#define SC_DEBUG_7__qs_q0_valid_MASK 0x00002000L +#define SC_DEBUG_7__qs_q0_valid 0x00002000L +#define SC_DEBUG_7__prim_ff_we_MASK 0x00004000L +#define SC_DEBUG_7__prim_ff_we 0x00004000L +#define SC_DEBUG_7__tile_ff_re_MASK 0x00008000L +#define SC_DEBUG_7__tile_ff_re 0x00008000L +#define SC_DEBUG_7__fw_prim_data_valid_MASK 0x00010000L +#define SC_DEBUG_7__fw_prim_data_valid 0x00010000L +#define SC_DEBUG_7__last_quad_of_tile_MASK 0x00020000L +#define SC_DEBUG_7__last_quad_of_tile 0x00020000L +#define SC_DEBUG_7__first_quad_of_tile_MASK 0x00040000L +#define SC_DEBUG_7__first_quad_of_tile 0x00040000L +#define SC_DEBUG_7__first_quad_of_prim_MASK 0x00080000L +#define SC_DEBUG_7__first_quad_of_prim 0x00080000L +#define SC_DEBUG_7__new_prim_MASK 0x00100000L +#define SC_DEBUG_7__new_prim 0x00100000L +#define SC_DEBUG_7__load_new_tile_data_MASK 0x00200000L +#define SC_DEBUG_7__load_new_tile_data 0x00200000L +#define SC_DEBUG_7__state_MASK 0x00c00000L +#define SC_DEBUG_7__fifos_ready_MASK 0x01000000L +#define SC_DEBUG_7__fifos_ready 0x01000000L +#define SC_DEBUG_7__trigger_MASK 0x80000000L +#define SC_DEBUG_7__trigger 0x80000000L + +// SC_DEBUG_8 +#define SC_DEBUG_8__sample_last_MASK 0x00000001L +#define SC_DEBUG_8__sample_last 0x00000001L +#define SC_DEBUG_8__sample_mask_MASK 0x0000001eL +#define SC_DEBUG_8__sample_y_MASK 0x00000060L +#define SC_DEBUG_8__sample_x_MASK 0x00000180L +#define SC_DEBUG_8__sample_send_MASK 0x00000200L +#define SC_DEBUG_8__sample_send 0x00000200L +#define SC_DEBUG_8__next_cycle_MASK 0x00000c00L +#define SC_DEBUG_8__ez_sample_ff_full_MASK 0x00001000L +#define SC_DEBUG_8__ez_sample_ff_full 0x00001000L +#define SC_DEBUG_8__rb_sc_samp_rtr_MASK 0x00002000L +#define SC_DEBUG_8__rb_sc_samp_rtr 0x00002000L +#define SC_DEBUG_8__num_samples_MASK 0x0000c000L +#define SC_DEBUG_8__last_quad_of_tile_MASK 0x00010000L +#define SC_DEBUG_8__last_quad_of_tile 0x00010000L +#define SC_DEBUG_8__last_quad_of_prim_MASK 0x00020000L +#define SC_DEBUG_8__last_quad_of_prim 0x00020000L +#define SC_DEBUG_8__first_quad_of_prim_MASK 0x00040000L +#define SC_DEBUG_8__first_quad_of_prim 0x00040000L +#define SC_DEBUG_8__sample_we_MASK 0x00080000L +#define SC_DEBUG_8__sample_we 0x00080000L +#define SC_DEBUG_8__fposition_MASK 0x00100000L +#define SC_DEBUG_8__fposition 0x00100000L +#define SC_DEBUG_8__event_id_MASK 0x03e00000L +#define SC_DEBUG_8__event_flag_MASK 0x04000000L +#define SC_DEBUG_8__event_flag 0x04000000L +#define SC_DEBUG_8__fw_prim_data_valid_MASK 0x08000000L +#define SC_DEBUG_8__fw_prim_data_valid 0x08000000L +#define SC_DEBUG_8__trigger_MASK 0x80000000L +#define SC_DEBUG_8__trigger 0x80000000L + +// SC_DEBUG_9 +#define SC_DEBUG_9__rb_sc_send_MASK 0x00000001L +#define SC_DEBUG_9__rb_sc_send 0x00000001L +#define SC_DEBUG_9__rb_sc_ez_mask_MASK 0x0000001eL +#define SC_DEBUG_9__fifo_data_ready_MASK 0x00000020L +#define SC_DEBUG_9__fifo_data_ready 0x00000020L +#define SC_DEBUG_9__early_z_enable_MASK 0x00000040L +#define SC_DEBUG_9__early_z_enable 0x00000040L +#define SC_DEBUG_9__mask_state_MASK 0x00000180L +#define SC_DEBUG_9__next_ez_mask_MASK 0x01fffe00L +#define SC_DEBUG_9__mask_ready_MASK 0x02000000L +#define SC_DEBUG_9__mask_ready 0x02000000L +#define SC_DEBUG_9__drop_sample_MASK 0x04000000L +#define SC_DEBUG_9__drop_sample 0x04000000L +#define SC_DEBUG_9__fetch_new_sample_data_MASK 0x08000000L +#define SC_DEBUG_9__fetch_new_sample_data 0x08000000L +#define SC_DEBUG_9__fetch_new_ez_sample_mask_MASK 0x10000000L +#define SC_DEBUG_9__fetch_new_ez_sample_mask 0x10000000L +#define SC_DEBUG_9__pkr_fetch_new_sample_data_MASK 0x20000000L +#define SC_DEBUG_9__pkr_fetch_new_sample_data 0x20000000L +#define SC_DEBUG_9__pkr_fetch_new_prim_data_MASK 0x40000000L +#define SC_DEBUG_9__pkr_fetch_new_prim_data 0x40000000L +#define SC_DEBUG_9__trigger_MASK 0x80000000L +#define SC_DEBUG_9__trigger 0x80000000L + +// SC_DEBUG_10 +#define SC_DEBUG_10__combined_sample_mask_MASK 0x0000ffffL +#define SC_DEBUG_10__trigger_MASK 0x80000000L +#define SC_DEBUG_10__trigger 0x80000000L + +// SC_DEBUG_11 +#define SC_DEBUG_11__ez_sample_data_ready_MASK 0x00000001L +#define SC_DEBUG_11__ez_sample_data_ready 0x00000001L +#define SC_DEBUG_11__pkr_fetch_new_sample_data_MASK 0x00000002L +#define SC_DEBUG_11__pkr_fetch_new_sample_data 0x00000002L +#define SC_DEBUG_11__ez_prim_data_ready_MASK 0x00000004L +#define SC_DEBUG_11__ez_prim_data_ready 0x00000004L +#define SC_DEBUG_11__pkr_fetch_new_prim_data_MASK 0x00000008L +#define SC_DEBUG_11__pkr_fetch_new_prim_data 0x00000008L +#define SC_DEBUG_11__iterator_input_fz_MASK 0x00000010L +#define SC_DEBUG_11__iterator_input_fz 0x00000010L +#define SC_DEBUG_11__packer_send_quads_MASK 0x00000020L +#define SC_DEBUG_11__packer_send_quads 0x00000020L +#define SC_DEBUG_11__packer_send_cmd_MASK 0x00000040L +#define SC_DEBUG_11__packer_send_cmd 0x00000040L +#define SC_DEBUG_11__packer_send_event_MASK 0x00000080L +#define SC_DEBUG_11__packer_send_event 0x00000080L +#define SC_DEBUG_11__next_state_MASK 0x00000700L +#define SC_DEBUG_11__state_MASK 0x00003800L +#define SC_DEBUG_11__stall_MASK 0x00004000L +#define SC_DEBUG_11__stall 0x00004000L +#define SC_DEBUG_11__trigger_MASK 0x80000000L +#define SC_DEBUG_11__trigger 0x80000000L + +// SC_DEBUG_12 +#define SC_DEBUG_12__SQ_iterator_free_buff_MASK 0x00000001L +#define SC_DEBUG_12__SQ_iterator_free_buff 0x00000001L +#define SC_DEBUG_12__event_id_MASK 0x0000003eL +#define SC_DEBUG_12__event_flag_MASK 0x00000040L +#define SC_DEBUG_12__event_flag 0x00000040L +#define SC_DEBUG_12__itercmdfifo_busy_nc_dly_MASK 0x00000080L +#define SC_DEBUG_12__itercmdfifo_busy_nc_dly 0x00000080L +#define SC_DEBUG_12__itercmdfifo_full_MASK 0x00000100L +#define SC_DEBUG_12__itercmdfifo_full 0x00000100L +#define SC_DEBUG_12__itercmdfifo_empty_MASK 0x00000200L +#define SC_DEBUG_12__itercmdfifo_empty 0x00000200L +#define SC_DEBUG_12__iter_ds_one_clk_command_MASK 0x00000400L +#define SC_DEBUG_12__iter_ds_one_clk_command 0x00000400L +#define SC_DEBUG_12__iter_ds_end_of_prim0_MASK 0x00000800L +#define SC_DEBUG_12__iter_ds_end_of_prim0 0x00000800L +#define SC_DEBUG_12__iter_ds_end_of_vector_MASK 0x00001000L +#define SC_DEBUG_12__iter_ds_end_of_vector 0x00001000L +#define SC_DEBUG_12__iter_qdhit0_MASK 0x00002000L +#define SC_DEBUG_12__iter_qdhit0 0x00002000L +#define SC_DEBUG_12__bc_use_centers_reg_MASK 0x00004000L +#define SC_DEBUG_12__bc_use_centers_reg 0x00004000L +#define SC_DEBUG_12__bc_output_xy_reg_MASK 0x00008000L +#define SC_DEBUG_12__bc_output_xy_reg 0x00008000L +#define SC_DEBUG_12__iter_phase_out_MASK 0x00030000L +#define SC_DEBUG_12__iter_phase_reg_MASK 0x000c0000L +#define SC_DEBUG_12__iterator_SP_valid_MASK 0x00100000L +#define SC_DEBUG_12__iterator_SP_valid 0x00100000L +#define SC_DEBUG_12__eopv_reg_MASK 0x00200000L +#define SC_DEBUG_12__eopv_reg 0x00200000L +#define SC_DEBUG_12__one_clk_cmd_reg_MASK 0x00400000L +#define SC_DEBUG_12__one_clk_cmd_reg 0x00400000L +#define SC_DEBUG_12__iter_dx_end_of_prim_MASK 0x00800000L +#define SC_DEBUG_12__iter_dx_end_of_prim 0x00800000L +#define SC_DEBUG_12__trigger_MASK 0x80000000L +#define SC_DEBUG_12__trigger 0x80000000L + +// GFX_COPY_STATE +#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x00000001L +#define GFX_COPY_STATE__SRC_STATE_ID 0x00000001L + +// VGT_DRAW_INITIATOR +#define VGT_DRAW_INITIATOR__PRIM_TYPE_MASK 0x0000003fL +#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x000000c0L +#define VGT_DRAW_INITIATOR__FACENESS_CULL_SELECT_MASK 0x00000300L +#define VGT_DRAW_INITIATOR__INDEX_SIZE_MASK 0x00000800L +#define VGT_DRAW_INITIATOR__INDEX_SIZE 0x00000800L +#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x00001000L +#define VGT_DRAW_INITIATOR__NOT_EOP 0x00001000L +#define VGT_DRAW_INITIATOR__SMALL_INDEX_MASK 0x00002000L +#define VGT_DRAW_INITIATOR__SMALL_INDEX 0x00002000L +#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE_MASK 0x00004000L +#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE 0x00004000L +#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE_MASK 0x00008000L +#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE 0x00008000L +#define VGT_DRAW_INITIATOR__NUM_INDICES_MASK 0xffff0000L + +// VGT_EVENT_INITIATOR +#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003fL + +// VGT_DMA_BASE +#define VGT_DMA_BASE__BASE_ADDR_MASK 0xffffffffL + +// VGT_DMA_SIZE +#define VGT_DMA_SIZE__NUM_WORDS_MASK 0x00ffffffL +#define VGT_DMA_SIZE__SWAP_MODE_MASK 0xc0000000L + +// VGT_BIN_BASE +#define VGT_BIN_BASE__BIN_BASE_ADDR_MASK 0xffffffffL + +// VGT_BIN_SIZE +#define VGT_BIN_SIZE__NUM_WORDS_MASK 0x00ffffffL +#define VGT_BIN_SIZE__FACENESS_FETCH_MASK 0x40000000L +#define VGT_BIN_SIZE__FACENESS_FETCH 0x40000000L +#define VGT_BIN_SIZE__FACENESS_RESET_MASK 0x80000000L +#define VGT_BIN_SIZE__FACENESS_RESET 0x80000000L + +// VGT_CURRENT_BIN_ID_MIN +#define VGT_CURRENT_BIN_ID_MIN__COLUMN_MASK 0x00000007L +#define VGT_CURRENT_BIN_ID_MIN__ROW_MASK 0x00000038L +#define VGT_CURRENT_BIN_ID_MIN__GUARD_BAND_MASK 0x000001c0L + +// VGT_CURRENT_BIN_ID_MAX +#define VGT_CURRENT_BIN_ID_MAX__COLUMN_MASK 0x00000007L +#define VGT_CURRENT_BIN_ID_MAX__ROW_MASK 0x00000038L +#define VGT_CURRENT_BIN_ID_MAX__GUARD_BAND_MASK 0x000001c0L + +// VGT_IMMED_DATA +#define VGT_IMMED_DATA__DATA_MASK 0xffffffffL + +// VGT_MAX_VTX_INDX +#define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0x00ffffffL + +// VGT_MIN_VTX_INDX +#define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0x00ffffffL + +// VGT_INDX_OFFSET +#define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0x00ffffffL + +// VGT_VERTEX_REUSE_BLOCK_CNTL +#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0x00000007L + +// VGT_OUT_DEALLOC_CNTL +#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x00000003L + +// VGT_MULTI_PRIM_IB_RESET_INDX +#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0x00ffffffL + +// VGT_ENHANCE +#define VGT_ENHANCE__MISC_MASK 0x0000ffffL + +// VGT_VTX_VECT_EJECT_REG +#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x0000001fL + +// VGT_LAST_COPY_STATE +#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x00000001L +#define VGT_LAST_COPY_STATE__SRC_STATE_ID 0x00000001L +#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x00010000L +#define VGT_LAST_COPY_STATE__DST_STATE_ID 0x00010000L + +// VGT_DEBUG_CNTL +#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX_MASK 0x0000001fL + +// VGT_DEBUG_DATA +#define VGT_DEBUG_DATA__DATA_MASK 0xffffffffL + +// VGT_CNTL_STATUS +#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x00000001L +#define VGT_CNTL_STATUS__VGT_BUSY 0x00000001L +#define VGT_CNTL_STATUS__VGT_DMA_BUSY_MASK 0x00000002L +#define VGT_CNTL_STATUS__VGT_DMA_BUSY 0x00000002L +#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY_MASK 0x00000004L +#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY 0x00000004L +#define VGT_CNTL_STATUS__VGT_GRP_BUSY_MASK 0x00000008L +#define VGT_CNTL_STATUS__VGT_GRP_BUSY 0x00000008L +#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x00000010L +#define VGT_CNTL_STATUS__VGT_VR_BUSY 0x00000010L +#define VGT_CNTL_STATUS__VGT_BIN_BUSY_MASK 0x00000020L +#define VGT_CNTL_STATUS__VGT_BIN_BUSY 0x00000020L +#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x00000040L +#define VGT_CNTL_STATUS__VGT_PT_BUSY 0x00000040L +#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x00000080L +#define VGT_CNTL_STATUS__VGT_OUT_BUSY 0x00000080L +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x00000100L +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY 0x00000100L + +// VGT_DEBUG_REG0 +#define VGT_DEBUG_REG0__te_grp_busy_MASK 0x00000001L +#define VGT_DEBUG_REG0__te_grp_busy 0x00000001L +#define VGT_DEBUG_REG0__pt_grp_busy_MASK 0x00000002L +#define VGT_DEBUG_REG0__pt_grp_busy 0x00000002L +#define VGT_DEBUG_REG0__vr_grp_busy_MASK 0x00000004L +#define VGT_DEBUG_REG0__vr_grp_busy 0x00000004L +#define VGT_DEBUG_REG0__dma_request_busy_MASK 0x00000008L +#define VGT_DEBUG_REG0__dma_request_busy 0x00000008L +#define VGT_DEBUG_REG0__out_busy_MASK 0x00000010L +#define VGT_DEBUG_REG0__out_busy 0x00000010L +#define VGT_DEBUG_REG0__grp_backend_busy_MASK 0x00000020L +#define VGT_DEBUG_REG0__grp_backend_busy 0x00000020L +#define VGT_DEBUG_REG0__grp_busy_MASK 0x00000040L +#define VGT_DEBUG_REG0__grp_busy 0x00000040L +#define VGT_DEBUG_REG0__dma_busy_MASK 0x00000080L +#define VGT_DEBUG_REG0__dma_busy 0x00000080L +#define VGT_DEBUG_REG0__rbiu_dma_request_busy_MASK 0x00000100L +#define VGT_DEBUG_REG0__rbiu_dma_request_busy 0x00000100L +#define VGT_DEBUG_REG0__rbiu_busy_MASK 0x00000200L +#define VGT_DEBUG_REG0__rbiu_busy 0x00000200L +#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended_MASK 0x00000400L +#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended 0x00000400L +#define VGT_DEBUG_REG0__vgt_no_dma_busy_MASK 0x00000800L +#define VGT_DEBUG_REG0__vgt_no_dma_busy 0x00000800L +#define VGT_DEBUG_REG0__vgt_busy_extended_MASK 0x00001000L +#define VGT_DEBUG_REG0__vgt_busy_extended 0x00001000L +#define VGT_DEBUG_REG0__vgt_busy_MASK 0x00002000L +#define VGT_DEBUG_REG0__vgt_busy 0x00002000L +#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out_MASK 0x00004000L +#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out 0x00004000L +#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy_MASK 0x00008000L +#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy 0x00008000L +#define VGT_DEBUG_REG0__VGT_RBBM_busy_MASK 0x00010000L +#define VGT_DEBUG_REG0__VGT_RBBM_busy 0x00010000L + +// VGT_DEBUG_REG1 +#define VGT_DEBUG_REG1__out_te_data_read_MASK 0x00000001L +#define VGT_DEBUG_REG1__out_te_data_read 0x00000001L +#define VGT_DEBUG_REG1__te_out_data_valid_MASK 0x00000002L +#define VGT_DEBUG_REG1__te_out_data_valid 0x00000002L +#define VGT_DEBUG_REG1__out_pt_prim_read_MASK 0x00000004L +#define VGT_DEBUG_REG1__out_pt_prim_read 0x00000004L +#define VGT_DEBUG_REG1__pt_out_prim_valid_MASK 0x00000008L +#define VGT_DEBUG_REG1__pt_out_prim_valid 0x00000008L +#define VGT_DEBUG_REG1__out_pt_data_read_MASK 0x00000010L +#define VGT_DEBUG_REG1__out_pt_data_read 0x00000010L +#define VGT_DEBUG_REG1__pt_out_indx_valid_MASK 0x00000020L +#define VGT_DEBUG_REG1__pt_out_indx_valid 0x00000020L +#define VGT_DEBUG_REG1__out_vr_prim_read_MASK 0x00000040L +#define VGT_DEBUG_REG1__out_vr_prim_read 0x00000040L +#define VGT_DEBUG_REG1__vr_out_prim_valid_MASK 0x00000080L +#define VGT_DEBUG_REG1__vr_out_prim_valid 0x00000080L +#define VGT_DEBUG_REG1__out_vr_indx_read_MASK 0x00000100L +#define VGT_DEBUG_REG1__out_vr_indx_read 0x00000100L +#define VGT_DEBUG_REG1__vr_out_indx_valid_MASK 0x00000200L +#define VGT_DEBUG_REG1__vr_out_indx_valid 0x00000200L +#define VGT_DEBUG_REG1__te_grp_read_MASK 0x00000400L +#define VGT_DEBUG_REG1__te_grp_read 0x00000400L +#define VGT_DEBUG_REG1__grp_te_valid_MASK 0x00000800L +#define VGT_DEBUG_REG1__grp_te_valid 0x00000800L +#define VGT_DEBUG_REG1__pt_grp_read_MASK 0x00001000L +#define VGT_DEBUG_REG1__pt_grp_read 0x00001000L +#define VGT_DEBUG_REG1__grp_pt_valid_MASK 0x00002000L +#define VGT_DEBUG_REG1__grp_pt_valid 0x00002000L +#define VGT_DEBUG_REG1__vr_grp_read_MASK 0x00004000L +#define VGT_DEBUG_REG1__vr_grp_read 0x00004000L +#define VGT_DEBUG_REG1__grp_vr_valid_MASK 0x00008000L +#define VGT_DEBUG_REG1__grp_vr_valid 0x00008000L +#define VGT_DEBUG_REG1__grp_dma_read_MASK 0x00010000L +#define VGT_DEBUG_REG1__grp_dma_read 0x00010000L +#define VGT_DEBUG_REG1__dma_grp_valid_MASK 0x00020000L +#define VGT_DEBUG_REG1__dma_grp_valid 0x00020000L +#define VGT_DEBUG_REG1__grp_rbiu_di_read_MASK 0x00040000L +#define VGT_DEBUG_REG1__grp_rbiu_di_read 0x00040000L +#define VGT_DEBUG_REG1__rbiu_grp_di_valid_MASK 0x00080000L +#define VGT_DEBUG_REG1__rbiu_grp_di_valid 0x00080000L +#define VGT_DEBUG_REG1__MH_VGT_rtr_MASK 0x00100000L +#define VGT_DEBUG_REG1__MH_VGT_rtr 0x00100000L +#define VGT_DEBUG_REG1__VGT_MH_send_MASK 0x00200000L +#define VGT_DEBUG_REG1__VGT_MH_send 0x00200000L +#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr_MASK 0x00400000L +#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr 0x00400000L +#define VGT_DEBUG_REG1__VGT_PA_clip_s_send_MASK 0x00800000L +#define VGT_DEBUG_REG1__VGT_PA_clip_s_send 0x00800000L +#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr_MASK 0x01000000L +#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr 0x01000000L +#define VGT_DEBUG_REG1__VGT_PA_clip_p_send_MASK 0x02000000L +#define VGT_DEBUG_REG1__VGT_PA_clip_p_send 0x02000000L +#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr_MASK 0x04000000L +#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr 0x04000000L +#define VGT_DEBUG_REG1__VGT_PA_clip_v_send_MASK 0x08000000L +#define VGT_DEBUG_REG1__VGT_PA_clip_v_send 0x08000000L +#define VGT_DEBUG_REG1__SQ_VGT_rtr_MASK 0x10000000L +#define VGT_DEBUG_REG1__SQ_VGT_rtr 0x10000000L +#define VGT_DEBUG_REG1__VGT_SQ_send_MASK 0x20000000L +#define VGT_DEBUG_REG1__VGT_SQ_send 0x20000000L +#define VGT_DEBUG_REG1__mh_vgt_tag_7_q_MASK 0x40000000L +#define VGT_DEBUG_REG1__mh_vgt_tag_7_q 0x40000000L + +// VGT_DEBUG_REG3 +#define VGT_DEBUG_REG3__vgt_clk_en_MASK 0x00000001L +#define VGT_DEBUG_REG3__vgt_clk_en 0x00000001L +#define VGT_DEBUG_REG3__reg_fifos_clk_en_MASK 0x00000002L +#define VGT_DEBUG_REG3__reg_fifos_clk_en 0x00000002L + +// VGT_DEBUG_REG6 +#define VGT_DEBUG_REG6__shifter_byte_count_q_MASK 0x0000001fL +#define VGT_DEBUG_REG6__right_word_indx_q_MASK 0x000003e0L +#define VGT_DEBUG_REG6__input_data_valid_MASK 0x00000400L +#define VGT_DEBUG_REG6__input_data_valid 0x00000400L +#define VGT_DEBUG_REG6__input_data_xfer_MASK 0x00000800L +#define VGT_DEBUG_REG6__input_data_xfer 0x00000800L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_q_MASK 0x00001000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_q 0x00001000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_d_MASK 0x00002000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_d 0x00002000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d_MASK 0x00004000L +#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d 0x00004000L +#define VGT_DEBUG_REG6__space_avail_from_shift_MASK 0x00008000L +#define VGT_DEBUG_REG6__space_avail_from_shift 0x00008000L +#define VGT_DEBUG_REG6__shifter_first_load_MASK 0x00010000L +#define VGT_DEBUG_REG6__shifter_first_load 0x00010000L +#define VGT_DEBUG_REG6__di_state_sel_q_MASK 0x00020000L +#define VGT_DEBUG_REG6__di_state_sel_q 0x00020000L +#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q_MASK 0x00040000L +#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q 0x00040000L +#define VGT_DEBUG_REG6__di_first_group_flag_q_MASK 0x00080000L +#define VGT_DEBUG_REG6__di_first_group_flag_q 0x00080000L +#define VGT_DEBUG_REG6__di_event_flag_q_MASK 0x00100000L +#define VGT_DEBUG_REG6__di_event_flag_q 0x00100000L +#define VGT_DEBUG_REG6__read_draw_initiator_MASK 0x00200000L +#define VGT_DEBUG_REG6__read_draw_initiator 0x00200000L +#define VGT_DEBUG_REG6__loading_di_requires_shifter_MASK 0x00400000L +#define VGT_DEBUG_REG6__loading_di_requires_shifter 0x00400000L +#define VGT_DEBUG_REG6__last_shift_of_packet_MASK 0x00800000L +#define VGT_DEBUG_REG6__last_shift_of_packet 0x00800000L +#define VGT_DEBUG_REG6__last_decr_of_packet_MASK 0x01000000L +#define VGT_DEBUG_REG6__last_decr_of_packet 0x01000000L +#define VGT_DEBUG_REG6__extract_vector_MASK 0x02000000L +#define VGT_DEBUG_REG6__extract_vector 0x02000000L +#define VGT_DEBUG_REG6__shift_vect_rtr_MASK 0x04000000L +#define VGT_DEBUG_REG6__shift_vect_rtr 0x04000000L +#define VGT_DEBUG_REG6__destination_rtr_MASK 0x08000000L +#define VGT_DEBUG_REG6__destination_rtr 0x08000000L +#define VGT_DEBUG_REG6__grp_trigger_MASK 0x10000000L +#define VGT_DEBUG_REG6__grp_trigger 0x10000000L + +// VGT_DEBUG_REG7 +#define VGT_DEBUG_REG7__di_index_counter_q_MASK 0x0000ffffL +#define VGT_DEBUG_REG7__shift_amount_no_extract_MASK 0x000f0000L +#define VGT_DEBUG_REG7__shift_amount_extract_MASK 0x00f00000L +#define VGT_DEBUG_REG7__di_prim_type_q_MASK 0x3f000000L +#define VGT_DEBUG_REG7__current_source_sel_MASK 0xc0000000L + +// VGT_DEBUG_REG8 +#define VGT_DEBUG_REG8__current_source_sel_MASK 0x00000003L +#define VGT_DEBUG_REG8__left_word_indx_q_MASK 0x0000007cL +#define VGT_DEBUG_REG8__input_data_cnt_MASK 0x00000f80L +#define VGT_DEBUG_REG8__input_data_lsw_MASK 0x0001f000L +#define VGT_DEBUG_REG8__input_data_msw_MASK 0x003e0000L +#define VGT_DEBUG_REG8__next_small_stride_shift_limit_q_MASK 0x07c00000L +#define VGT_DEBUG_REG8__current_small_stride_shift_limit_q_MASK 0xf8000000L + +// VGT_DEBUG_REG9 +#define VGT_DEBUG_REG9__next_stride_q_MASK 0x0000001fL +#define VGT_DEBUG_REG9__next_stride_d_MASK 0x000003e0L +#define VGT_DEBUG_REG9__current_shift_q_MASK 0x00007c00L +#define VGT_DEBUG_REG9__current_shift_d_MASK 0x000f8000L +#define VGT_DEBUG_REG9__current_stride_q_MASK 0x01f00000L +#define VGT_DEBUG_REG9__current_stride_d_MASK 0x3e000000L +#define VGT_DEBUG_REG9__grp_trigger_MASK 0x40000000L +#define VGT_DEBUG_REG9__grp_trigger 0x40000000L + +// VGT_DEBUG_REG10 +#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0_MASK 0x00000001L +#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0 0x00000001L +#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0_MASK 0x00000002L +#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0 0x00000002L +#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0_MASK 0x00000004L +#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0 0x00000004L +#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0_MASK 0x00000008L +#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0 0x00000008L +#define VGT_DEBUG_REG10__di_state_sel_q_MASK 0x00000010L +#define VGT_DEBUG_REG10__di_state_sel_q 0x00000010L +#define VGT_DEBUG_REG10__last_decr_of_packet_MASK 0x00000020L +#define VGT_DEBUG_REG10__last_decr_of_packet 0x00000020L +#define VGT_DEBUG_REG10__bin_valid_MASK 0x00000040L +#define VGT_DEBUG_REG10__bin_valid 0x00000040L +#define VGT_DEBUG_REG10__read_block_MASK 0x00000080L +#define VGT_DEBUG_REG10__read_block 0x00000080L +#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read_MASK 0x00000100L +#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read 0x00000100L +#define VGT_DEBUG_REG10__last_bit_enable_q_MASK 0x00000200L +#define VGT_DEBUG_REG10__last_bit_enable_q 0x00000200L +#define VGT_DEBUG_REG10__last_bit_end_di_q_MASK 0x00000400L +#define VGT_DEBUG_REG10__last_bit_end_di_q 0x00000400L +#define VGT_DEBUG_REG10__selected_data_MASK 0x0007f800L +#define VGT_DEBUG_REG10__mask_input_data_MASK 0x07f80000L +#define VGT_DEBUG_REG10__gap_q_MASK 0x08000000L +#define VGT_DEBUG_REG10__gap_q 0x08000000L +#define VGT_DEBUG_REG10__temp_mini_reset_z_MASK 0x10000000L +#define VGT_DEBUG_REG10__temp_mini_reset_z 0x10000000L +#define VGT_DEBUG_REG10__temp_mini_reset_y_MASK 0x20000000L +#define VGT_DEBUG_REG10__temp_mini_reset_y 0x20000000L +#define VGT_DEBUG_REG10__temp_mini_reset_x_MASK 0x40000000L +#define VGT_DEBUG_REG10__temp_mini_reset_x 0x40000000L +#define VGT_DEBUG_REG10__grp_trigger_MASK 0x80000000L +#define VGT_DEBUG_REG10__grp_trigger 0x80000000L + +// VGT_DEBUG_REG12 +#define VGT_DEBUG_REG12__shifter_byte_count_q_MASK 0x0000001fL +#define VGT_DEBUG_REG12__right_word_indx_q_MASK 0x000003e0L +#define VGT_DEBUG_REG12__input_data_valid_MASK 0x00000400L +#define VGT_DEBUG_REG12__input_data_valid 0x00000400L +#define VGT_DEBUG_REG12__input_data_xfer_MASK 0x00000800L +#define VGT_DEBUG_REG12__input_data_xfer 0x00000800L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_q_MASK 0x00001000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_q 0x00001000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_d_MASK 0x00002000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_d 0x00002000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d_MASK 0x00004000L +#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d 0x00004000L +#define VGT_DEBUG_REG12__space_avail_from_shift_MASK 0x00008000L +#define VGT_DEBUG_REG12__space_avail_from_shift 0x00008000L +#define VGT_DEBUG_REG12__shifter_first_load_MASK 0x00010000L +#define VGT_DEBUG_REG12__shifter_first_load 0x00010000L +#define VGT_DEBUG_REG12__di_state_sel_q_MASK 0x00020000L +#define VGT_DEBUG_REG12__di_state_sel_q 0x00020000L +#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q_MASK 0x00040000L +#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q 0x00040000L +#define VGT_DEBUG_REG12__di_first_group_flag_q_MASK 0x00080000L +#define VGT_DEBUG_REG12__di_first_group_flag_q 0x00080000L +#define VGT_DEBUG_REG12__di_event_flag_q_MASK 0x00100000L +#define VGT_DEBUG_REG12__di_event_flag_q 0x00100000L +#define VGT_DEBUG_REG12__read_draw_initiator_MASK 0x00200000L +#define VGT_DEBUG_REG12__read_draw_initiator 0x00200000L +#define VGT_DEBUG_REG12__loading_di_requires_shifter_MASK 0x00400000L +#define VGT_DEBUG_REG12__loading_di_requires_shifter 0x00400000L +#define VGT_DEBUG_REG12__last_shift_of_packet_MASK 0x00800000L +#define VGT_DEBUG_REG12__last_shift_of_packet 0x00800000L +#define VGT_DEBUG_REG12__last_decr_of_packet_MASK 0x01000000L +#define VGT_DEBUG_REG12__last_decr_of_packet 0x01000000L +#define VGT_DEBUG_REG12__extract_vector_MASK 0x02000000L +#define VGT_DEBUG_REG12__extract_vector 0x02000000L +#define VGT_DEBUG_REG12__shift_vect_rtr_MASK 0x04000000L +#define VGT_DEBUG_REG12__shift_vect_rtr 0x04000000L +#define VGT_DEBUG_REG12__destination_rtr_MASK 0x08000000L +#define VGT_DEBUG_REG12__destination_rtr 0x08000000L +#define VGT_DEBUG_REG12__bgrp_trigger_MASK 0x10000000L +#define VGT_DEBUG_REG12__bgrp_trigger 0x10000000L + +// VGT_DEBUG_REG13 +#define VGT_DEBUG_REG13__di_index_counter_q_MASK 0x0000ffffL +#define VGT_DEBUG_REG13__shift_amount_no_extract_MASK 0x000f0000L +#define VGT_DEBUG_REG13__shift_amount_extract_MASK 0x00f00000L +#define VGT_DEBUG_REG13__di_prim_type_q_MASK 0x3f000000L +#define VGT_DEBUG_REG13__current_source_sel_MASK 0xc0000000L + +// VGT_DEBUG_REG14 +#define VGT_DEBUG_REG14__current_source_sel_MASK 0x00000003L +#define VGT_DEBUG_REG14__left_word_indx_q_MASK 0x0000007cL +#define VGT_DEBUG_REG14__input_data_cnt_MASK 0x00000f80L +#define VGT_DEBUG_REG14__input_data_lsw_MASK 0x0001f000L +#define VGT_DEBUG_REG14__input_data_msw_MASK 0x003e0000L +#define VGT_DEBUG_REG14__next_small_stride_shift_limit_q_MASK 0x07c00000L +#define VGT_DEBUG_REG14__current_small_stride_shift_limit_q_MASK 0xf8000000L + +// VGT_DEBUG_REG15 +#define VGT_DEBUG_REG15__next_stride_q_MASK 0x0000001fL +#define VGT_DEBUG_REG15__next_stride_d_MASK 0x000003e0L +#define VGT_DEBUG_REG15__current_shift_q_MASK 0x00007c00L +#define VGT_DEBUG_REG15__current_shift_d_MASK 0x000f8000L +#define VGT_DEBUG_REG15__current_stride_q_MASK 0x01f00000L +#define VGT_DEBUG_REG15__current_stride_d_MASK 0x3e000000L +#define VGT_DEBUG_REG15__bgrp_trigger_MASK 0x40000000L +#define VGT_DEBUG_REG15__bgrp_trigger 0x40000000L + +// VGT_DEBUG_REG16 +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full_MASK 0x00000001L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full 0x00000001L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty_MASK 0x00000002L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty 0x00000002L +#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read_MASK 0x00000004L +#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read 0x00000004L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we_MASK 0x00000008L +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we 0x00000008L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full_MASK 0x00000010L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full 0x00000010L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty_MASK 0x00000020L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty 0x00000020L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q_MASK 0x00000040L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q 0x00000040L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we_MASK 0x00000080L +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we 0x00000080L +#define VGT_DEBUG_REG16__bgrp_dma_mask_kill_MASK 0x00000100L +#define VGT_DEBUG_REG16__bgrp_dma_mask_kill 0x00000100L +#define VGT_DEBUG_REG16__bgrp_grp_bin_valid_MASK 0x00000200L +#define VGT_DEBUG_REG16__bgrp_grp_bin_valid 0x00000200L +#define VGT_DEBUG_REG16__rst_last_bit_MASK 0x00000400L +#define VGT_DEBUG_REG16__rst_last_bit 0x00000400L +#define VGT_DEBUG_REG16__current_state_q_MASK 0x00000800L +#define VGT_DEBUG_REG16__current_state_q 0x00000800L +#define VGT_DEBUG_REG16__old_state_q_MASK 0x00001000L +#define VGT_DEBUG_REG16__old_state_q 0x00001000L +#define VGT_DEBUG_REG16__old_state_en_MASK 0x00002000L +#define VGT_DEBUG_REG16__old_state_en 0x00002000L +#define VGT_DEBUG_REG16__prev_last_bit_q_MASK 0x00004000L +#define VGT_DEBUG_REG16__prev_last_bit_q 0x00004000L +#define VGT_DEBUG_REG16__dbl_last_bit_q_MASK 0x00008000L +#define VGT_DEBUG_REG16__dbl_last_bit_q 0x00008000L +#define VGT_DEBUG_REG16__last_bit_block_q_MASK 0x00010000L +#define VGT_DEBUG_REG16__last_bit_block_q 0x00010000L +#define VGT_DEBUG_REG16__ast_bit_block2_q_MASK 0x00020000L +#define VGT_DEBUG_REG16__ast_bit_block2_q 0x00020000L +#define VGT_DEBUG_REG16__load_empty_reg_MASK 0x00040000L +#define VGT_DEBUG_REG16__load_empty_reg 0x00040000L +#define VGT_DEBUG_REG16__bgrp_grp_byte_mask_rdata_MASK 0x07f80000L +#define VGT_DEBUG_REG16__dma_bgrp_dma_data_fifo_rptr_MASK 0x18000000L +#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable_MASK 0x20000000L +#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable 0x20000000L +#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q_MASK 0x40000000L +#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q 0x40000000L +#define VGT_DEBUG_REG16__bgrp_trigger_MASK 0x80000000L +#define VGT_DEBUG_REG16__bgrp_trigger 0x80000000L + +// VGT_DEBUG_REG17 +#define VGT_DEBUG_REG17__save_read_q_MASK 0x00000001L +#define VGT_DEBUG_REG17__save_read_q 0x00000001L +#define VGT_DEBUG_REG17__extend_read_q_MASK 0x00000002L +#define VGT_DEBUG_REG17__extend_read_q 0x00000002L +#define VGT_DEBUG_REG17__grp_indx_size_MASK 0x0000000cL +#define VGT_DEBUG_REG17__cull_prim_true_MASK 0x00000010L +#define VGT_DEBUG_REG17__cull_prim_true 0x00000010L +#define VGT_DEBUG_REG17__reset_bit2_q_MASK 0x00000020L +#define VGT_DEBUG_REG17__reset_bit2_q 0x00000020L +#define VGT_DEBUG_REG17__reset_bit1_q_MASK 0x00000040L +#define VGT_DEBUG_REG17__reset_bit1_q 0x00000040L +#define VGT_DEBUG_REG17__first_reg_first_q_MASK 0x00000080L +#define VGT_DEBUG_REG17__first_reg_first_q 0x00000080L +#define VGT_DEBUG_REG17__check_second_reg_MASK 0x00000100L +#define VGT_DEBUG_REG17__check_second_reg 0x00000100L +#define VGT_DEBUG_REG17__check_first_reg_MASK 0x00000200L +#define VGT_DEBUG_REG17__check_first_reg 0x00000200L +#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata_MASK 0x00000400L +#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata 0x00000400L +#define VGT_DEBUG_REG17__save_cull_fetch_data2_q_MASK 0x00000800L +#define VGT_DEBUG_REG17__save_cull_fetch_data2_q 0x00000800L +#define VGT_DEBUG_REG17__save_cull_fetch_data1_q_MASK 0x00001000L +#define VGT_DEBUG_REG17__save_cull_fetch_data1_q 0x00001000L +#define VGT_DEBUG_REG17__save_byte_mask_data2_q_MASK 0x00002000L +#define VGT_DEBUG_REG17__save_byte_mask_data2_q 0x00002000L +#define VGT_DEBUG_REG17__save_byte_mask_data1_q_MASK 0x00004000L +#define VGT_DEBUG_REG17__save_byte_mask_data1_q 0x00004000L +#define VGT_DEBUG_REG17__to_second_reg_q_MASK 0x00008000L +#define VGT_DEBUG_REG17__to_second_reg_q 0x00008000L +#define VGT_DEBUG_REG17__roll_over_msk_q_MASK 0x00010000L +#define VGT_DEBUG_REG17__roll_over_msk_q 0x00010000L +#define VGT_DEBUG_REG17__max_msk_ptr_q_MASK 0x00fe0000L +#define VGT_DEBUG_REG17__min_msk_ptr_q_MASK 0x7f000000L +#define VGT_DEBUG_REG17__bgrp_trigger_MASK 0x80000000L +#define VGT_DEBUG_REG17__bgrp_trigger 0x80000000L + +// VGT_DEBUG_REG18 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_raddr_MASK 0x0000003fL +#define VGT_DEBUG_REG18__dma_data_fifo_mem_waddr_MASK 0x00000fc0L +#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re_MASK 0x00001000L +#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re 0x00001000L +#define VGT_DEBUG_REG18__dma_bgrp_dma_data_fifo_rptr_MASK 0x00006000L +#define VGT_DEBUG_REG18__dma_mem_full_MASK 0x00008000L +#define VGT_DEBUG_REG18__dma_mem_full 0x00008000L +#define VGT_DEBUG_REG18__dma_ram_re_MASK 0x00010000L +#define VGT_DEBUG_REG18__dma_ram_re 0x00010000L +#define VGT_DEBUG_REG18__dma_ram_we_MASK 0x00020000L +#define VGT_DEBUG_REG18__dma_ram_we 0x00020000L +#define VGT_DEBUG_REG18__dma_mem_empty_MASK 0x00040000L +#define VGT_DEBUG_REG18__dma_mem_empty 0x00040000L +#define VGT_DEBUG_REG18__dma_data_fifo_mem_re_MASK 0x00080000L +#define VGT_DEBUG_REG18__dma_data_fifo_mem_re 0x00080000L +#define VGT_DEBUG_REG18__dma_data_fifo_mem_we_MASK 0x00100000L +#define VGT_DEBUG_REG18__dma_data_fifo_mem_we 0x00100000L +#define VGT_DEBUG_REG18__bin_mem_full_MASK 0x00200000L +#define VGT_DEBUG_REG18__bin_mem_full 0x00200000L +#define VGT_DEBUG_REG18__bin_ram_we_MASK 0x00400000L +#define VGT_DEBUG_REG18__bin_ram_we 0x00400000L +#define VGT_DEBUG_REG18__bin_ram_re_MASK 0x00800000L +#define VGT_DEBUG_REG18__bin_ram_re 0x00800000L +#define VGT_DEBUG_REG18__bin_mem_empty_MASK 0x01000000L +#define VGT_DEBUG_REG18__bin_mem_empty 0x01000000L +#define VGT_DEBUG_REG18__start_bin_req_MASK 0x02000000L +#define VGT_DEBUG_REG18__start_bin_req 0x02000000L +#define VGT_DEBUG_REG18__fetch_cull_not_used_MASK 0x04000000L +#define VGT_DEBUG_REG18__fetch_cull_not_used 0x04000000L +#define VGT_DEBUG_REG18__dma_req_xfer_MASK 0x08000000L +#define VGT_DEBUG_REG18__dma_req_xfer 0x08000000L +#define VGT_DEBUG_REG18__have_valid_bin_req_MASK 0x10000000L +#define VGT_DEBUG_REG18__have_valid_bin_req 0x10000000L +#define VGT_DEBUG_REG18__have_valid_dma_req_MASK 0x20000000L +#define VGT_DEBUG_REG18__have_valid_dma_req 0x20000000L +#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable_MASK 0x40000000L +#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable 0x40000000L +#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable_MASK 0x80000000L +#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable 0x80000000L + +// VGT_DEBUG_REG20 +#define VGT_DEBUG_REG20__prim_side_indx_valid_MASK 0x00000001L +#define VGT_DEBUG_REG20__prim_side_indx_valid 0x00000001L +#define VGT_DEBUG_REG20__indx_side_fifo_empty_MASK 0x00000002L +#define VGT_DEBUG_REG20__indx_side_fifo_empty 0x00000002L +#define VGT_DEBUG_REG20__indx_side_fifo_re_MASK 0x00000004L +#define VGT_DEBUG_REG20__indx_side_fifo_re 0x00000004L +#define VGT_DEBUG_REG20__indx_side_fifo_we_MASK 0x00000008L +#define VGT_DEBUG_REG20__indx_side_fifo_we 0x00000008L +#define VGT_DEBUG_REG20__indx_side_fifo_full_MASK 0x00000010L +#define VGT_DEBUG_REG20__indx_side_fifo_full 0x00000010L +#define VGT_DEBUG_REG20__prim_buffer_empty_MASK 0x00000020L +#define VGT_DEBUG_REG20__prim_buffer_empty 0x00000020L +#define VGT_DEBUG_REG20__prim_buffer_re_MASK 0x00000040L +#define VGT_DEBUG_REG20__prim_buffer_re 0x00000040L +#define VGT_DEBUG_REG20__prim_buffer_we_MASK 0x00000080L +#define VGT_DEBUG_REG20__prim_buffer_we 0x00000080L +#define VGT_DEBUG_REG20__prim_buffer_full_MASK 0x00000100L +#define VGT_DEBUG_REG20__prim_buffer_full 0x00000100L +#define VGT_DEBUG_REG20__indx_buffer_empty_MASK 0x00000200L +#define VGT_DEBUG_REG20__indx_buffer_empty 0x00000200L +#define VGT_DEBUG_REG20__indx_buffer_re_MASK 0x00000400L +#define VGT_DEBUG_REG20__indx_buffer_re 0x00000400L +#define VGT_DEBUG_REG20__indx_buffer_we_MASK 0x00000800L +#define VGT_DEBUG_REG20__indx_buffer_we 0x00000800L +#define VGT_DEBUG_REG20__indx_buffer_full_MASK 0x00001000L +#define VGT_DEBUG_REG20__indx_buffer_full 0x00001000L +#define VGT_DEBUG_REG20__hold_prim_MASK 0x00002000L +#define VGT_DEBUG_REG20__hold_prim 0x00002000L +#define VGT_DEBUG_REG20__sent_cnt_MASK 0x0003c000L +#define VGT_DEBUG_REG20__start_of_vtx_vector_MASK 0x00040000L +#define VGT_DEBUG_REG20__start_of_vtx_vector 0x00040000L +#define VGT_DEBUG_REG20__clip_s_pre_hold_prim_MASK 0x00080000L +#define VGT_DEBUG_REG20__clip_s_pre_hold_prim 0x00080000L +#define VGT_DEBUG_REG20__clip_p_pre_hold_prim_MASK 0x00100000L +#define VGT_DEBUG_REG20__clip_p_pre_hold_prim 0x00100000L +#define VGT_DEBUG_REG20__buffered_prim_type_event_MASK 0x03e00000L +#define VGT_DEBUG_REG20__out_trigger_MASK 0x04000000L +#define VGT_DEBUG_REG20__out_trigger 0x04000000L + +// VGT_DEBUG_REG21 +#define VGT_DEBUG_REG21__null_terminate_vtx_vector_MASK 0x00000001L +#define VGT_DEBUG_REG21__null_terminate_vtx_vector 0x00000001L +#define VGT_DEBUG_REG21__prim_end_of_vtx_vect_flags_MASK 0x0000000eL +#define VGT_DEBUG_REG21__alloc_counter_q_MASK 0x00000070L +#define VGT_DEBUG_REG21__curr_slot_in_vtx_vect_q_MASK 0x00000380L +#define VGT_DEBUG_REG21__int_vtx_counter_q_MASK 0x00003c00L +#define VGT_DEBUG_REG21__curr_dealloc_distance_q_MASK 0x0003c000L +#define VGT_DEBUG_REG21__new_packet_q_MASK 0x00040000L +#define VGT_DEBUG_REG21__new_packet_q 0x00040000L +#define VGT_DEBUG_REG21__new_allocate_q_MASK 0x00080000L +#define VGT_DEBUG_REG21__new_allocate_q 0x00080000L +#define VGT_DEBUG_REG21__num_new_unique_rel_indx_MASK 0x00300000L +#define VGT_DEBUG_REG21__inserted_null_prim_q_MASK 0x00400000L +#define VGT_DEBUG_REG21__inserted_null_prim_q 0x00400000L +#define VGT_DEBUG_REG21__insert_null_prim_MASK 0x00800000L +#define VGT_DEBUG_REG21__insert_null_prim 0x00800000L +#define VGT_DEBUG_REG21__buffered_prim_eop_mux_MASK 0x01000000L +#define VGT_DEBUG_REG21__buffered_prim_eop_mux 0x01000000L +#define VGT_DEBUG_REG21__prim_buffer_empty_mux_MASK 0x02000000L +#define VGT_DEBUG_REG21__prim_buffer_empty_mux 0x02000000L +#define VGT_DEBUG_REG21__buffered_thread_size_MASK 0x04000000L +#define VGT_DEBUG_REG21__buffered_thread_size 0x04000000L +#define VGT_DEBUG_REG21__out_trigger_MASK 0x80000000L +#define VGT_DEBUG_REG21__out_trigger 0x80000000L + +// VGT_CRC_SQ_DATA +#define VGT_CRC_SQ_DATA__CRC_MASK 0xffffffffL + +// VGT_CRC_SQ_CTRL +#define VGT_CRC_SQ_CTRL__CRC_MASK 0xffffffffL + +// VGT_PERFCOUNTER0_SELECT +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// VGT_PERFCOUNTER1_SELECT +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL + +// VGT_PERFCOUNTER2_SELECT +#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL + +// VGT_PERFCOUNTER3_SELECT +#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL + +// VGT_PERFCOUNTER0_LOW +#define VGT_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// VGT_PERFCOUNTER1_LOW +#define VGT_PERFCOUNTER1_LOW__PERF_COUNT_MASK 0xffffffffL + +// VGT_PERFCOUNTER2_LOW +#define VGT_PERFCOUNTER2_LOW__PERF_COUNT_MASK 0xffffffffL + +// VGT_PERFCOUNTER3_LOW +#define VGT_PERFCOUNTER3_LOW__PERF_COUNT_MASK 0xffffffffL + +// VGT_PERFCOUNTER0_HI +#define VGT_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// VGT_PERFCOUNTER1_HI +#define VGT_PERFCOUNTER1_HI__PERF_COUNT_MASK 0x0000ffffL + +// VGT_PERFCOUNTER2_HI +#define VGT_PERFCOUNTER2_HI__PERF_COUNT_MASK 0x0000ffffL + +// VGT_PERFCOUNTER3_HI +#define VGT_PERFCOUNTER3_HI__PERF_COUNT_MASK 0x0000ffffL + +// TC_CNTL_STATUS +#define TC_CNTL_STATUS__L2_INVALIDATE_MASK 0x00000001L +#define TC_CNTL_STATUS__L2_INVALIDATE 0x00000001L +#define TC_CNTL_STATUS__TC_L2_HIT_MISS_MASK 0x000c0000L +#define TC_CNTL_STATUS__TC_BUSY_MASK 0x80000000L +#define TC_CNTL_STATUS__TC_BUSY 0x80000000L + +// TCR_CHICKEN +#define TCR_CHICKEN__SPARE_MASK 0xffffffffL + +// TCF_CHICKEN +#define TCF_CHICKEN__SPARE_MASK 0xffffffffL + +// TCM_CHICKEN +#define TCM_CHICKEN__TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK 0x000000ffL +#define TCM_CHICKEN__ETC_COLOR_ENDIAN_MASK 0x00000100L +#define TCM_CHICKEN__ETC_COLOR_ENDIAN 0x00000100L +#define TCM_CHICKEN__SPARE_MASK 0xfffffe00L + +// TCR_PERFCOUNTER0_SELECT +#define TCR_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCR_PERFCOUNTER1_SELECT +#define TCR_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCR_PERFCOUNTER0_HI +#define TCR_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCR_PERFCOUNTER1_HI +#define TCR_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCR_PERFCOUNTER0_LOW +#define TCR_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCR_PERFCOUNTER1_LOW +#define TCR_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TP_TC_CLKGATE_CNTL +#define TP_TC_CLKGATE_CNTL__TP_BUSY_EXTEND_MASK 0x00000007L +#define TP_TC_CLKGATE_CNTL__TC_BUSY_EXTEND_MASK 0x00000038L + +// TPC_CNTL_STATUS +#define TPC_CNTL_STATUS__TPC_INPUT_BUSY_MASK 0x00000001L +#define TPC_CNTL_STATUS__TPC_INPUT_BUSY 0x00000001L +#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY_MASK 0x00000002L +#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY 0x00000002L +#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY_MASK 0x00000004L +#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY 0x00000004L +#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY_MASK 0x00000008L +#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY 0x00000008L +#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY_MASK 0x00000010L +#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY 0x00000010L +#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY_MASK 0x00000020L +#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY 0x00000020L +#define TPC_CNTL_STATUS__TPC_WALKER_BUSY_MASK 0x00000040L +#define TPC_CNTL_STATUS__TPC_WALKER_BUSY 0x00000040L +#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY_MASK 0x00000100L +#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY 0x00000100L +#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY_MASK 0x00000200L +#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY 0x00000200L +#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY_MASK 0x00000400L +#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY 0x00000400L +#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY_MASK 0x00001000L +#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY 0x00001000L +#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY_MASK 0x00002000L +#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY 0x00002000L +#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY_MASK 0x00004000L +#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY 0x00004000L +#define TPC_CNTL_STATUS__TPC_BLEND_BUSY_MASK 0x00008000L +#define TPC_CNTL_STATUS__TPC_BLEND_BUSY 0x00008000L +#define TPC_CNTL_STATUS__TF_TW_RTS_MASK 0x00010000L +#define TPC_CNTL_STATUS__TF_TW_RTS 0x00010000L +#define TPC_CNTL_STATUS__TF_TW_STATE_RTS_MASK 0x00020000L +#define TPC_CNTL_STATUS__TF_TW_STATE_RTS 0x00020000L +#define TPC_CNTL_STATUS__TF_TW_RTR_MASK 0x00080000L +#define TPC_CNTL_STATUS__TF_TW_RTR 0x00080000L +#define TPC_CNTL_STATUS__TW_TA_RTS_MASK 0x00100000L +#define TPC_CNTL_STATUS__TW_TA_RTS 0x00100000L +#define TPC_CNTL_STATUS__TW_TA_TT_RTS_MASK 0x00200000L +#define TPC_CNTL_STATUS__TW_TA_TT_RTS 0x00200000L +#define TPC_CNTL_STATUS__TW_TA_LAST_RTS_MASK 0x00400000L +#define TPC_CNTL_STATUS__TW_TA_LAST_RTS 0x00400000L +#define TPC_CNTL_STATUS__TW_TA_RTR_MASK 0x00800000L +#define TPC_CNTL_STATUS__TW_TA_RTR 0x00800000L +#define TPC_CNTL_STATUS__TA_TB_RTS_MASK 0x01000000L +#define TPC_CNTL_STATUS__TA_TB_RTS 0x01000000L +#define TPC_CNTL_STATUS__TA_TB_TT_RTS_MASK 0x02000000L +#define TPC_CNTL_STATUS__TA_TB_TT_RTS 0x02000000L +#define TPC_CNTL_STATUS__TA_TB_RTR_MASK 0x08000000L +#define TPC_CNTL_STATUS__TA_TB_RTR 0x08000000L +#define TPC_CNTL_STATUS__TA_TF_RTS_MASK 0x10000000L +#define TPC_CNTL_STATUS__TA_TF_RTS 0x10000000L +#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN_MASK 0x20000000L +#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN 0x20000000L +#define TPC_CNTL_STATUS__TP_SQ_DEC_MASK 0x40000000L +#define TPC_CNTL_STATUS__TP_SQ_DEC 0x40000000L +#define TPC_CNTL_STATUS__TPC_BUSY_MASK 0x80000000L +#define TPC_CNTL_STATUS__TPC_BUSY 0x80000000L + +// TPC_DEBUG0 +#define TPC_DEBUG0__LOD_CNTL_MASK 0x00000003L +#define TPC_DEBUG0__IC_CTR_MASK 0x0000000cL +#define TPC_DEBUG0__WALKER_CNTL_MASK 0x000000f0L +#define TPC_DEBUG0__ALIGNER_CNTL_MASK 0x00000700L +#define TPC_DEBUG0__PREV_TC_STATE_VALID_MASK 0x00001000L +#define TPC_DEBUG0__PREV_TC_STATE_VALID 0x00001000L +#define TPC_DEBUG0__WALKER_STATE_MASK 0x03ff0000L +#define TPC_DEBUG0__ALIGNER_STATE_MASK 0x0c000000L +#define TPC_DEBUG0__REG_CLK_EN_MASK 0x20000000L +#define TPC_DEBUG0__REG_CLK_EN 0x20000000L +#define TPC_DEBUG0__TPC_CLK_EN_MASK 0x40000000L +#define TPC_DEBUG0__TPC_CLK_EN 0x40000000L +#define TPC_DEBUG0__SQ_TP_WAKEUP_MASK 0x80000000L +#define TPC_DEBUG0__SQ_TP_WAKEUP 0x80000000L + +// TPC_DEBUG1 +#define TPC_DEBUG1__UNUSED_MASK 0x00000001L +#define TPC_DEBUG1__UNUSED 0x00000001L + +// TPC_CHICKEN +#define TPC_CHICKEN__BLEND_PRECISION_MASK 0x00000001L +#define TPC_CHICKEN__BLEND_PRECISION 0x00000001L +#define TPC_CHICKEN__SPARE_MASK 0xfffffffeL + +// TP0_CNTL_STATUS +#define TP0_CNTL_STATUS__TP_INPUT_BUSY_MASK 0x00000001L +#define TP0_CNTL_STATUS__TP_INPUT_BUSY 0x00000001L +#define TP0_CNTL_STATUS__TP_LOD_BUSY_MASK 0x00000002L +#define TP0_CNTL_STATUS__TP_LOD_BUSY 0x00000002L +#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY_MASK 0x00000004L +#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY 0x00000004L +#define TP0_CNTL_STATUS__TP_ADDR_BUSY_MASK 0x00000008L +#define TP0_CNTL_STATUS__TP_ADDR_BUSY 0x00000008L +#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY_MASK 0x00000010L +#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY 0x00000010L +#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY_MASK 0x00000020L +#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY 0x00000020L +#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY_MASK 0x00000040L +#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY 0x00000040L +#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY_MASK 0x00000080L +#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY 0x00000080L +#define TP0_CNTL_STATUS__TP_FETCH_BUSY_MASK 0x00000100L +#define TP0_CNTL_STATUS__TP_FETCH_BUSY 0x00000100L +#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY_MASK 0x00000200L +#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY 0x00000200L +#define TP0_CNTL_STATUS__TP_TT_BUSY_MASK 0x00000400L +#define TP0_CNTL_STATUS__TP_TT_BUSY 0x00000400L +#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY_MASK 0x00000800L +#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY 0x00000800L +#define TP0_CNTL_STATUS__TP_BLEND_BUSY_MASK 0x00001000L +#define TP0_CNTL_STATUS__TP_BLEND_BUSY 0x00001000L +#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY_MASK 0x00002000L +#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY 0x00002000L +#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY_MASK 0x00004000L +#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY 0x00004000L +#define TP0_CNTL_STATUS__IN_LC_RTS_MASK 0x00010000L +#define TP0_CNTL_STATUS__IN_LC_RTS 0x00010000L +#define TP0_CNTL_STATUS__LC_LA_RTS_MASK 0x00020000L +#define TP0_CNTL_STATUS__LC_LA_RTS 0x00020000L +#define TP0_CNTL_STATUS__LA_FL_RTS_MASK 0x00040000L +#define TP0_CNTL_STATUS__LA_FL_RTS 0x00040000L +#define TP0_CNTL_STATUS__FL_TA_RTS_MASK 0x00080000L +#define TP0_CNTL_STATUS__FL_TA_RTS 0x00080000L +#define TP0_CNTL_STATUS__TA_FA_RTS_MASK 0x00100000L +#define TP0_CNTL_STATUS__TA_FA_RTS 0x00100000L +#define TP0_CNTL_STATUS__TA_FA_TT_RTS_MASK 0x00200000L +#define TP0_CNTL_STATUS__TA_FA_TT_RTS 0x00200000L +#define TP0_CNTL_STATUS__FA_AL_RTS_MASK 0x00400000L +#define TP0_CNTL_STATUS__FA_AL_RTS 0x00400000L +#define TP0_CNTL_STATUS__FA_AL_TT_RTS_MASK 0x00800000L +#define TP0_CNTL_STATUS__FA_AL_TT_RTS 0x00800000L +#define TP0_CNTL_STATUS__AL_TF_RTS_MASK 0x01000000L +#define TP0_CNTL_STATUS__AL_TF_RTS 0x01000000L +#define TP0_CNTL_STATUS__AL_TF_TT_RTS_MASK 0x02000000L +#define TP0_CNTL_STATUS__AL_TF_TT_RTS 0x02000000L +#define TP0_CNTL_STATUS__TF_TB_RTS_MASK 0x04000000L +#define TP0_CNTL_STATUS__TF_TB_RTS 0x04000000L +#define TP0_CNTL_STATUS__TF_TB_TT_RTS_MASK 0x08000000L +#define TP0_CNTL_STATUS__TF_TB_TT_RTS 0x08000000L +#define TP0_CNTL_STATUS__TB_TT_RTS_MASK 0x10000000L +#define TP0_CNTL_STATUS__TB_TT_RTS 0x10000000L +#define TP0_CNTL_STATUS__TB_TT_TT_RESET_MASK 0x20000000L +#define TP0_CNTL_STATUS__TB_TT_TT_RESET 0x20000000L +#define TP0_CNTL_STATUS__TB_TO_RTS_MASK 0x40000000L +#define TP0_CNTL_STATUS__TB_TO_RTS 0x40000000L +#define TP0_CNTL_STATUS__TP_BUSY_MASK 0x80000000L +#define TP0_CNTL_STATUS__TP_BUSY 0x80000000L + +// TP0_DEBUG +#define TP0_DEBUG__Q_LOD_CNTL_MASK 0x00000003L +#define TP0_DEBUG__Q_SQ_TP_WAKEUP_MASK 0x00000008L +#define TP0_DEBUG__Q_SQ_TP_WAKEUP 0x00000008L +#define TP0_DEBUG__FL_TA_ADDRESSER_CNTL_MASK 0x001ffff0L +#define TP0_DEBUG__REG_CLK_EN_MASK 0x00200000L +#define TP0_DEBUG__REG_CLK_EN 0x00200000L +#define TP0_DEBUG__PERF_CLK_EN_MASK 0x00400000L +#define TP0_DEBUG__PERF_CLK_EN 0x00400000L +#define TP0_DEBUG__TP_CLK_EN_MASK 0x00800000L +#define TP0_DEBUG__TP_CLK_EN 0x00800000L +#define TP0_DEBUG__Q_WALKER_CNTL_MASK 0x0f000000L +#define TP0_DEBUG__Q_ALIGNER_CNTL_MASK 0x70000000L + +// TP0_CHICKEN +#define TP0_CHICKEN__TT_MODE_MASK 0x00000001L +#define TP0_CHICKEN__TT_MODE 0x00000001L +#define TP0_CHICKEN__VFETCH_ADDRESS_MODE_MASK 0x00000002L +#define TP0_CHICKEN__VFETCH_ADDRESS_MODE 0x00000002L +#define TP0_CHICKEN__SPARE_MASK 0xfffffffcL + +// TP0_PERFCOUNTER0_SELECT +#define TP0_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TP0_PERFCOUNTER0_HI +#define TP0_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TP0_PERFCOUNTER0_LOW +#define TP0_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TP0_PERFCOUNTER1_SELECT +#define TP0_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TP0_PERFCOUNTER1_HI +#define TP0_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TP0_PERFCOUNTER1_LOW +#define TP0_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCM_PERFCOUNTER0_SELECT +#define TCM_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCM_PERFCOUNTER1_SELECT +#define TCM_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCM_PERFCOUNTER0_HI +#define TCM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCM_PERFCOUNTER1_HI +#define TCM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCM_PERFCOUNTER0_LOW +#define TCM_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCM_PERFCOUNTER1_LOW +#define TCM_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER0_SELECT +#define TCF_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER1_SELECT +#define TCF_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER2_SELECT +#define TCF_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER3_SELECT +#define TCF_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER4_SELECT +#define TCF_PERFCOUNTER4_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER5_SELECT +#define TCF_PERFCOUNTER5_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER6_SELECT +#define TCF_PERFCOUNTER6_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER7_SELECT +#define TCF_PERFCOUNTER7_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER8_SELECT +#define TCF_PERFCOUNTER8_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER9_SELECT +#define TCF_PERFCOUNTER9_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER10_SELECT +#define TCF_PERFCOUNTER10_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER11_SELECT +#define TCF_PERFCOUNTER11_SELECT__PERFCOUNTER_SELECT_MASK 0x000000ffL + +// TCF_PERFCOUNTER0_HI +#define TCF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER1_HI +#define TCF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER2_HI +#define TCF_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER3_HI +#define TCF_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER4_HI +#define TCF_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER5_HI +#define TCF_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER6_HI +#define TCF_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER7_HI +#define TCF_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER8_HI +#define TCF_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER9_HI +#define TCF_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER10_HI +#define TCF_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER11_HI +#define TCF_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0x0000ffffL + +// TCF_PERFCOUNTER0_LOW +#define TCF_PERFCOUNTER0_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER1_LOW +#define TCF_PERFCOUNTER1_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER2_LOW +#define TCF_PERFCOUNTER2_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER3_LOW +#define TCF_PERFCOUNTER3_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER4_LOW +#define TCF_PERFCOUNTER4_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER5_LOW +#define TCF_PERFCOUNTER5_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER6_LOW +#define TCF_PERFCOUNTER6_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER7_LOW +#define TCF_PERFCOUNTER7_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER8_LOW +#define TCF_PERFCOUNTER8_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER9_LOW +#define TCF_PERFCOUNTER9_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER10_LOW +#define TCF_PERFCOUNTER10_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_PERFCOUNTER11_LOW +#define TCF_PERFCOUNTER11_LOW__PERFCOUNTER_LOW_MASK 0xffffffffL + +// TCF_DEBUG +#define TCF_DEBUG__not_MH_TC_rtr_MASK 0x00000040L +#define TCF_DEBUG__not_MH_TC_rtr 0x00000040L +#define TCF_DEBUG__TC_MH_send_MASK 0x00000080L +#define TCF_DEBUG__TC_MH_send 0x00000080L +#define TCF_DEBUG__not_FG0_rtr_MASK 0x00000100L +#define TCF_DEBUG__not_FG0_rtr 0x00000100L +#define TCF_DEBUG__not_TCB_TCO_rtr_MASK 0x00001000L +#define TCF_DEBUG__not_TCB_TCO_rtr 0x00001000L +#define TCF_DEBUG__TCB_ff_stall_MASK 0x00002000L +#define TCF_DEBUG__TCB_ff_stall 0x00002000L +#define TCF_DEBUG__TCB_miss_stall_MASK 0x00004000L +#define TCF_DEBUG__TCB_miss_stall 0x00004000L +#define TCF_DEBUG__TCA_TCB_stall_MASK 0x00008000L +#define TCF_DEBUG__TCA_TCB_stall 0x00008000L +#define TCF_DEBUG__PF0_stall_MASK 0x00010000L +#define TCF_DEBUG__PF0_stall 0x00010000L +#define TCF_DEBUG__TP0_full_MASK 0x00100000L +#define TCF_DEBUG__TP0_full 0x00100000L +#define TCF_DEBUG__TPC_full_MASK 0x01000000L +#define TCF_DEBUG__TPC_full 0x01000000L +#define TCF_DEBUG__not_TPC_rtr_MASK 0x02000000L +#define TCF_DEBUG__not_TPC_rtr 0x02000000L +#define TCF_DEBUG__tca_state_rts_MASK 0x04000000L +#define TCF_DEBUG__tca_state_rts 0x04000000L +#define TCF_DEBUG__tca_rts_MASK 0x08000000L +#define TCF_DEBUG__tca_rts 0x08000000L + +// TCA_FIFO_DEBUG +#define TCA_FIFO_DEBUG__tp0_full_MASK 0x00000001L +#define TCA_FIFO_DEBUG__tp0_full 0x00000001L +#define TCA_FIFO_DEBUG__tpc_full_MASK 0x00000010L +#define TCA_FIFO_DEBUG__tpc_full 0x00000010L +#define TCA_FIFO_DEBUG__load_tpc_fifo_MASK 0x00000020L +#define TCA_FIFO_DEBUG__load_tpc_fifo 0x00000020L +#define TCA_FIFO_DEBUG__load_tp_fifos_MASK 0x00000040L +#define TCA_FIFO_DEBUG__load_tp_fifos 0x00000040L +#define TCA_FIFO_DEBUG__FW_full_MASK 0x00000080L +#define TCA_FIFO_DEBUG__FW_full 0x00000080L +#define TCA_FIFO_DEBUG__not_FW_rtr0_MASK 0x00000100L +#define TCA_FIFO_DEBUG__not_FW_rtr0 0x00000100L +#define TCA_FIFO_DEBUG__FW_rts0_MASK 0x00001000L +#define TCA_FIFO_DEBUG__FW_rts0 0x00001000L +#define TCA_FIFO_DEBUG__not_FW_tpc_rtr_MASK 0x00010000L +#define TCA_FIFO_DEBUG__not_FW_tpc_rtr 0x00010000L +#define TCA_FIFO_DEBUG__FW_tpc_rts_MASK 0x00020000L +#define TCA_FIFO_DEBUG__FW_tpc_rts 0x00020000L + +// TCA_PROBE_DEBUG +#define TCA_PROBE_DEBUG__ProbeFilter_stall_MASK 0x00000001L +#define TCA_PROBE_DEBUG__ProbeFilter_stall 0x00000001L + +// TCA_TPC_DEBUG +#define TCA_TPC_DEBUG__captue_state_rts_MASK 0x00001000L +#define TCA_TPC_DEBUG__captue_state_rts 0x00001000L +#define TCA_TPC_DEBUG__capture_tca_rts_MASK 0x00002000L +#define TCA_TPC_DEBUG__capture_tca_rts 0x00002000L + +// TCB_CORE_DEBUG +#define TCB_CORE_DEBUG__access512_MASK 0x00000001L +#define TCB_CORE_DEBUG__access512 0x00000001L +#define TCB_CORE_DEBUG__tiled_MASK 0x00000002L +#define TCB_CORE_DEBUG__tiled 0x00000002L +#define TCB_CORE_DEBUG__opcode_MASK 0x00000070L +#define TCB_CORE_DEBUG__format_MASK 0x00003f00L +#define TCB_CORE_DEBUG__sector_format_MASK 0x001f0000L +#define TCB_CORE_DEBUG__sector_format512_MASK 0x07000000L + +// TCB_TAG0_DEBUG +#define TCB_TAG0_DEBUG__mem_read_cycle_MASK 0x000003ffL +#define TCB_TAG0_DEBUG__tag_access_cycle_MASK 0x001ff000L +#define TCB_TAG0_DEBUG__miss_stall_MASK 0x00800000L +#define TCB_TAG0_DEBUG__miss_stall 0x00800000L +#define TCB_TAG0_DEBUG__num_feee_lines_MASK 0x1f000000L +#define TCB_TAG0_DEBUG__max_misses_MASK 0xe0000000L + +// TCB_TAG1_DEBUG +#define TCB_TAG1_DEBUG__mem_read_cycle_MASK 0x000003ffL +#define TCB_TAG1_DEBUG__tag_access_cycle_MASK 0x001ff000L +#define TCB_TAG1_DEBUG__miss_stall_MASK 0x00800000L +#define TCB_TAG1_DEBUG__miss_stall 0x00800000L +#define TCB_TAG1_DEBUG__num_feee_lines_MASK 0x1f000000L +#define TCB_TAG1_DEBUG__max_misses_MASK 0xe0000000L + +// TCB_TAG2_DEBUG +#define TCB_TAG2_DEBUG__mem_read_cycle_MASK 0x000003ffL +#define TCB_TAG2_DEBUG__tag_access_cycle_MASK 0x001ff000L +#define TCB_TAG2_DEBUG__miss_stall_MASK 0x00800000L +#define TCB_TAG2_DEBUG__miss_stall 0x00800000L +#define TCB_TAG2_DEBUG__num_feee_lines_MASK 0x1f000000L +#define TCB_TAG2_DEBUG__max_misses_MASK 0xe0000000L + +// TCB_TAG3_DEBUG +#define TCB_TAG3_DEBUG__mem_read_cycle_MASK 0x000003ffL +#define TCB_TAG3_DEBUG__tag_access_cycle_MASK 0x001ff000L +#define TCB_TAG3_DEBUG__miss_stall_MASK 0x00800000L +#define TCB_TAG3_DEBUG__miss_stall 0x00800000L +#define TCB_TAG3_DEBUG__num_feee_lines_MASK 0x1f000000L +#define TCB_TAG3_DEBUG__max_misses_MASK 0xe0000000L + +// TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done_MASK 0x00000001L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done 0x00000001L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left_MASK 0x00000004L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left 0x00000004L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q_MASK 0x00000010L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q 0x00000010L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go_MASK 0x00000020L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go 0x00000020L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left_MASK 0x00000040L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left 0x00000040L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_count_q_MASK 0x00000f80L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_q_MASK 0x0ffff000L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q_MASK 0x10000000L +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q 0x10000000L + +// TCB_FETCH_GEN_WALKER_DEBUG +#define TCB_FETCH_GEN_WALKER_DEBUG__quad_sel_left_MASK 0x00000030L +#define TCB_FETCH_GEN_WALKER_DEBUG__set_sel_left_MASK 0x000000c0L +#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left_MASK 0x00000800L +#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left 0x00000800L +#define TCB_FETCH_GEN_WALKER_DEBUG__ff_fg_type512_MASK 0x00007000L +#define TCB_FETCH_GEN_WALKER_DEBUG__busy_MASK 0x00008000L +#define TCB_FETCH_GEN_WALKER_DEBUG__busy 0x00008000L +#define TCB_FETCH_GEN_WALKER_DEBUG__setquads_to_send_MASK 0x000f0000L + +// TCB_FETCH_GEN_PIPE0_DEBUG +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts_MASK 0x00000001L +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts 0x00000001L +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts_MASK 0x00000004L +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts 0x00000004L +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_format_MASK 0x0000fff0L +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_fmsopcode_MASK 0x001f0000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_request_type_MASK 0x00600000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__busy_MASK 0x00800000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__busy 0x00800000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy_MASK 0x01000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy 0x01000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy_MASK 0x02000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy 0x02000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__mc_sel_q_MASK 0x0c000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q_MASK 0x10000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q 0x10000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR_MASK 0x40000000L +#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR 0x40000000L + +// TCD_INPUT0_DEBUG +#define TCD_INPUT0_DEBUG__empty_MASK 0x00010000L +#define TCD_INPUT0_DEBUG__empty 0x00010000L +#define TCD_INPUT0_DEBUG__full_MASK 0x00020000L +#define TCD_INPUT0_DEBUG__full 0x00020000L +#define TCD_INPUT0_DEBUG__valid_q1_MASK 0x00100000L +#define TCD_INPUT0_DEBUG__valid_q1 0x00100000L +#define TCD_INPUT0_DEBUG__cnt_q1_MASK 0x00600000L +#define TCD_INPUT0_DEBUG__last_send_q1_MASK 0x00800000L +#define TCD_INPUT0_DEBUG__last_send_q1 0x00800000L +#define TCD_INPUT0_DEBUG__ip_send_MASK 0x01000000L +#define TCD_INPUT0_DEBUG__ip_send 0x01000000L +#define TCD_INPUT0_DEBUG__ipbuf_dxt_send_MASK 0x02000000L +#define TCD_INPUT0_DEBUG__ipbuf_dxt_send 0x02000000L +#define TCD_INPUT0_DEBUG__ipbuf_busy_MASK 0x04000000L +#define TCD_INPUT0_DEBUG__ipbuf_busy 0x04000000L + +// TCD_DEGAMMA_DEBUG +#define TCD_DEGAMMA_DEBUG__dgmm_ftfconv_dgmmen_MASK 0x00000003L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8_MASK 0x00000004L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8 0x00000004L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send_MASK 0x00000008L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send 0x00000008L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send_MASK 0x00000010L +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send 0x00000010L +#define TCD_DEGAMMA_DEBUG__dgmm_stall_MASK 0x00000020L +#define TCD_DEGAMMA_DEBUG__dgmm_stall 0x00000020L +#define TCD_DEGAMMA_DEBUG__dgmm_pstate_MASK 0x00000040L +#define TCD_DEGAMMA_DEBUG__dgmm_pstate 0x00000040L + +// TCD_DXTMUX_SCTARB_DEBUG +#define TCD_DXTMUX_SCTARB_DEBUG__pstate_MASK 0x00000200L +#define TCD_DXTMUX_SCTARB_DEBUG__pstate 0x00000200L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr_MASK 0x00000400L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr 0x00000400L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr_MASK 0x00000800L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr 0x00000800L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send_MASK 0x00008000L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send 0x00008000L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts_MASK 0x00010000L +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts 0x00010000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send_MASK 0x00100000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send 0x00100000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send_MASK 0x08000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send 0x08000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send_MASK 0x10000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send 0x10000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send_MASK 0x20000000L +#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send 0x20000000L + +// TCD_DXTC_ARB_DEBUG +#define TCD_DXTC_ARB_DEBUG__n0_stall_MASK 0x00000010L +#define TCD_DXTC_ARB_DEBUG__n0_stall 0x00000010L +#define TCD_DXTC_ARB_DEBUG__pstate_MASK 0x00000020L +#define TCD_DXTC_ARB_DEBUG__pstate 0x00000020L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send_MASK 0x00000040L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send 0x00000040L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cnt_MASK 0x00000180L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_sector_MASK 0x00000e00L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cacheline_MASK 0x0003f000L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_format_MASK 0x3ffc0000L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send_MASK 0x40000000L +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send 0x40000000L +#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types_MASK 0x80000000L +#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types 0x80000000L + +// TCD_STALLS_DEBUG +#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr_MASK 0x00000400L +#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr 0x00000400L +#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr_MASK 0x00000800L +#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr 0x00000800L +#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr_MASK 0x00020000L +#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr 0x00020000L +#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr_MASK 0x00040000L +#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr 0x00040000L +#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr_MASK 0x00080000L +#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr 0x00080000L +#define TCD_STALLS_DEBUG__not_incoming_rtr_MASK 0x80000000L +#define TCD_STALLS_DEBUG__not_incoming_rtr 0x80000000L + +// TCO_STALLS_DEBUG +#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR_MASK 0x00000020L +#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR 0x00000020L +#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR_MASK 0x00000040L +#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR 0x00000040L +#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d_MASK 0x00000080L +#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d 0x00000080L + +// TCO_QUAD0_DEBUG0 +#define TCO_QUAD0_DEBUG0__rl_sg_sector_format_MASK 0x000000ffL +#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample_MASK 0x00000100L +#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample 0x00000100L +#define TCO_QUAD0_DEBUG0__rl_sg_rtr_MASK 0x00000200L +#define TCO_QUAD0_DEBUG0__rl_sg_rtr 0x00000200L +#define TCO_QUAD0_DEBUG0__rl_sg_rts_MASK 0x00000400L +#define TCO_QUAD0_DEBUG0__rl_sg_rts 0x00000400L +#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample_MASK 0x00000800L +#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample 0x00000800L +#define TCO_QUAD0_DEBUG0__sg_crd_rtr_MASK 0x00001000L +#define TCO_QUAD0_DEBUG0__sg_crd_rtr 0x00001000L +#define TCO_QUAD0_DEBUG0__sg_crd_rts_MASK 0x00002000L +#define TCO_QUAD0_DEBUG0__sg_crd_rts 0x00002000L +#define TCO_QUAD0_DEBUG0__stageN1_valid_q_MASK 0x00010000L +#define TCO_QUAD0_DEBUG0__stageN1_valid_q 0x00010000L +#define TCO_QUAD0_DEBUG0__read_cache_q_MASK 0x01000000L +#define TCO_QUAD0_DEBUG0__read_cache_q 0x01000000L +#define TCO_QUAD0_DEBUG0__cache_read_RTR_MASK 0x02000000L +#define TCO_QUAD0_DEBUG0__cache_read_RTR 0x02000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set3_MASK 0x04000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set3 0x04000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set2_MASK 0x08000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set2 0x08000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set1_MASK 0x10000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set1 0x10000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set0_MASK 0x20000000L +#define TCO_QUAD0_DEBUG0__all_sectors_written_set0 0x20000000L +#define TCO_QUAD0_DEBUG0__busy_MASK 0x40000000L +#define TCO_QUAD0_DEBUG0__busy 0x40000000L + +// TCO_QUAD0_DEBUG1 +#define TCO_QUAD0_DEBUG1__fifo_busy_MASK 0x00000001L +#define TCO_QUAD0_DEBUG1__fifo_busy 0x00000001L +#define TCO_QUAD0_DEBUG1__empty_MASK 0x00000002L +#define TCO_QUAD0_DEBUG1__empty 0x00000002L +#define TCO_QUAD0_DEBUG1__full_MASK 0x00000004L +#define TCO_QUAD0_DEBUG1__full 0x00000004L +#define TCO_QUAD0_DEBUG1__write_enable_MASK 0x00000008L +#define TCO_QUAD0_DEBUG1__write_enable 0x00000008L +#define TCO_QUAD0_DEBUG1__fifo_write_ptr_MASK 0x000007f0L +#define TCO_QUAD0_DEBUG1__fifo_read_ptr_MASK 0x0003f800L +#define TCO_QUAD0_DEBUG1__cache_read_busy_MASK 0x00100000L +#define TCO_QUAD0_DEBUG1__cache_read_busy 0x00100000L +#define TCO_QUAD0_DEBUG1__latency_fifo_busy_MASK 0x00200000L +#define TCO_QUAD0_DEBUG1__latency_fifo_busy 0x00200000L +#define TCO_QUAD0_DEBUG1__input_quad_busy_MASK 0x00400000L +#define TCO_QUAD0_DEBUG1__input_quad_busy 0x00400000L +#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy_MASK 0x00800000L +#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy 0x00800000L +#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d_MASK 0x01000000L +#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d 0x01000000L +#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q_MASK 0x02000000L +#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q 0x02000000L +#define TCO_QUAD0_DEBUG1__rl_sg_rtr_MASK 0x04000000L +#define TCO_QUAD0_DEBUG1__rl_sg_rtr 0x04000000L +#define TCO_QUAD0_DEBUG1__rl_sg_rts_MASK 0x08000000L +#define TCO_QUAD0_DEBUG1__rl_sg_rts 0x08000000L +#define TCO_QUAD0_DEBUG1__sg_crd_rtr_MASK 0x10000000L +#define TCO_QUAD0_DEBUG1__sg_crd_rtr 0x10000000L +#define TCO_QUAD0_DEBUG1__sg_crd_rts_MASK 0x20000000L +#define TCO_QUAD0_DEBUG1__sg_crd_rts 0x20000000L +#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc_MASK 0x40000000L +#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc 0x40000000L + +// SQ_GPR_MANAGEMENT +#define SQ_GPR_MANAGEMENT__REG_DYNAMIC_MASK 0x00000001L +#define SQ_GPR_MANAGEMENT__REG_DYNAMIC 0x00000001L +#define SQ_GPR_MANAGEMENT__REG_SIZE_PIX_MASK 0x000007f0L +#define SQ_GPR_MANAGEMENT__REG_SIZE_VTX_MASK 0x0007f000L + +// SQ_FLOW_CONTROL +#define SQ_FLOW_CONTROL__INPUT_ARBITRATION_POLICY_MASK 0x00000003L +#define SQ_FLOW_CONTROL__ONE_THREAD_MASK 0x00000010L +#define SQ_FLOW_CONTROL__ONE_THREAD 0x00000010L +#define SQ_FLOW_CONTROL__ONE_ALU_MASK 0x00000100L +#define SQ_FLOW_CONTROL__ONE_ALU 0x00000100L +#define SQ_FLOW_CONTROL__CF_WR_BASE_MASK 0x0000f000L +#define SQ_FLOW_CONTROL__NO_PV_PS_MASK 0x00010000L +#define SQ_FLOW_CONTROL__NO_PV_PS 0x00010000L +#define SQ_FLOW_CONTROL__NO_LOOP_EXIT_MASK 0x00020000L +#define SQ_FLOW_CONTROL__NO_LOOP_EXIT 0x00020000L +#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE_MASK 0x00040000L +#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE 0x00040000L +#define SQ_FLOW_CONTROL__TEXTURE_ARBITRATION_POLICY_MASK 0x00180000L +#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY_MASK 0x00200000L +#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY 0x00200000L +#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY_MASK 0x00400000L +#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY 0x00400000L +#define SQ_FLOW_CONTROL__NO_ARB_EJECT_MASK 0x00800000L +#define SQ_FLOW_CONTROL__NO_ARB_EJECT 0x00800000L +#define SQ_FLOW_CONTROL__NO_CFS_EJECT_MASK 0x01000000L +#define SQ_FLOW_CONTROL__NO_CFS_EJECT 0x01000000L +#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY_MASK 0x02000000L +#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY 0x02000000L +#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION_MASK 0x04000000L +#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION 0x04000000L +#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC_MASK 0x08000000L +#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC 0x08000000L + +// SQ_INST_STORE_MANAGMENT +#define SQ_INST_STORE_MANAGMENT__INST_BASE_PIX_MASK 0x00000fffL +#define SQ_INST_STORE_MANAGMENT__INST_BASE_VTX_MASK 0x0fff0000L + +// SQ_RESOURCE_MANAGMENT +#define SQ_RESOURCE_MANAGMENT__VTX_THREAD_BUF_ENTRIES_MASK 0x000000ffL +#define SQ_RESOURCE_MANAGMENT__PIX_THREAD_BUF_ENTRIES_MASK 0x0000ff00L +#define SQ_RESOURCE_MANAGMENT__EXPORT_BUF_ENTRIES_MASK 0x01ff0000L + +// SQ_EO_RT +#define SQ_EO_RT__EO_CONSTANTS_RT_MASK 0x000000ffL +#define SQ_EO_RT__EO_TSTATE_RT_MASK 0x00ff0000L + +// SQ_DEBUG_MISC +#define SQ_DEBUG_MISC__DB_ALUCST_SIZE_MASK 0x000007ffL +#define SQ_DEBUG_MISC__DB_TSTATE_SIZE_MASK 0x000ff000L +#define SQ_DEBUG_MISC__DB_READ_CTX_MASK 0x00100000L +#define SQ_DEBUG_MISC__DB_READ_CTX 0x00100000L +#define SQ_DEBUG_MISC__RESERVED_MASK 0x00600000L +#define SQ_DEBUG_MISC__DB_READ_MEMORY_MASK 0x01800000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0_MASK 0x02000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0 0x02000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1_MASK 0x04000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1 0x04000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2_MASK 0x08000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2 0x08000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3_MASK 0x10000000L +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3 0x10000000L + +// SQ_ACTIVITY_METER_CNTL +#define SQ_ACTIVITY_METER_CNTL__TIMEBASE_MASK 0x000000ffL +#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_LOW_MASK 0x0000ff00L +#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_HIGH_MASK 0x00ff0000L +#define SQ_ACTIVITY_METER_CNTL__SPARE_MASK 0xff000000L + +// SQ_ACTIVITY_METER_STATUS +#define SQ_ACTIVITY_METER_STATUS__PERCENT_BUSY_MASK 0x000000ffL + +// SQ_INPUT_ARB_PRIORITY +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_WEIGHT_MASK 0x00000007L +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN_MASK 0x00000008L +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN 0x00000008L +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_WEIGHT_MASK 0x00000070L +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN_MASK 0x00000080L +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN 0x00000080L +#define SQ_INPUT_ARB_PRIORITY__THRESHOLD_MASK 0x0003ff00L + +// SQ_THREAD_ARB_PRIORITY +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_WEIGHT_MASK 0x00000007L +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN_MASK 0x00000008L +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN 0x00000008L +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_WEIGHT_MASK 0x00000070L +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN_MASK 0x00000080L +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN 0x00000080L +#define SQ_THREAD_ARB_PRIORITY__THRESHOLD_MASK 0x0003ff00L +#define SQ_THREAD_ARB_PRIORITY__RESERVED_MASK 0x000c0000L +#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL_MASK 0x00100000L +#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL 0x00100000L +#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL_MASK 0x00200000L +#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL 0x00200000L +#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD_MASK 0x00400000L +#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD 0x00400000L + +// SQ_VS_WATCHDOG_TIMER +#define SQ_VS_WATCHDOG_TIMER__ENABLE_MASK 0x00000001L +#define SQ_VS_WATCHDOG_TIMER__ENABLE 0x00000001L +#define SQ_VS_WATCHDOG_TIMER__TIMEOUT_COUNT_MASK 0xfffffffeL + +// SQ_PS_WATCHDOG_TIMER +#define SQ_PS_WATCHDOG_TIMER__ENABLE_MASK 0x00000001L +#define SQ_PS_WATCHDOG_TIMER__ENABLE 0x00000001L +#define SQ_PS_WATCHDOG_TIMER__TIMEOUT_COUNT_MASK 0xfffffffeL + +// SQ_INT_CNTL +#define SQ_INT_CNTL__PS_WATCHDOG_MASK_MASK 0x00000001L +#define SQ_INT_CNTL__PS_WATCHDOG_MASK 0x00000001L +#define SQ_INT_CNTL__VS_WATCHDOG_MASK_MASK 0x00000002L +#define SQ_INT_CNTL__VS_WATCHDOG_MASK 0x00000002L + +// SQ_INT_STATUS +#define SQ_INT_STATUS__PS_WATCHDOG_TIMEOUT_MASK 0x00000001L +#define SQ_INT_STATUS__PS_WATCHDOG_TIMEOUT 0x00000001L +#define SQ_INT_STATUS__VS_WATCHDOG_TIMEOUT_MASK 0x00000002L +#define SQ_INT_STATUS__VS_WATCHDOG_TIMEOUT 0x00000002L + +// SQ_INT_ACK +#define SQ_INT_ACK__PS_WATCHDOG_ACK_MASK 0x00000001L +#define SQ_INT_ACK__PS_WATCHDOG_ACK 0x00000001L +#define SQ_INT_ACK__VS_WATCHDOG_ACK_MASK 0x00000002L +#define SQ_INT_ACK__VS_WATCHDOG_ACK 0x00000002L + +// SQ_DEBUG_INPUT_FSM +#define SQ_DEBUG_INPUT_FSM__VC_VSR_LD_MASK 0x00000007L +#define SQ_DEBUG_INPUT_FSM__RESERVED_MASK 0x00000008L +#define SQ_DEBUG_INPUT_FSM__RESERVED 0x00000008L +#define SQ_DEBUG_INPUT_FSM__VC_GPR_LD_MASK 0x000000f0L +#define SQ_DEBUG_INPUT_FSM__PC_PISM_MASK 0x00000700L +#define SQ_DEBUG_INPUT_FSM__RESERVED1_MASK 0x00000800L +#define SQ_DEBUG_INPUT_FSM__RESERVED1 0x00000800L +#define SQ_DEBUG_INPUT_FSM__PC_AS_MASK 0x00007000L +#define SQ_DEBUG_INPUT_FSM__PC_INTERP_CNT_MASK 0x000f8000L +#define SQ_DEBUG_INPUT_FSM__PC_GPR_SIZE_MASK 0x0ff00000L + +// SQ_DEBUG_CONST_MGR_FSM +#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_EVENT_STATE_MASK 0x0000001fL +#define SQ_DEBUG_CONST_MGR_FSM__RESERVED1_MASK 0x000000e0L +#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_EVENT_STATE_MASK 0x00001f00L +#define SQ_DEBUG_CONST_MGR_FSM__RESERVED2_MASK 0x0000e000L +#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_CNTX_VALID_MASK 0x00030000L +#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_CNTX_VALID_MASK 0x000c0000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE_MASK 0x00100000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE 0x00100000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE_MASK 0x00200000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE 0x00200000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE_MASK 0x00400000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE 0x00400000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE_MASK 0x00800000L +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE 0x00800000L + +// SQ_DEBUG_TP_FSM +#define SQ_DEBUG_TP_FSM__EX_TP_MASK 0x00000007L +#define SQ_DEBUG_TP_FSM__RESERVED0_MASK 0x00000008L +#define SQ_DEBUG_TP_FSM__RESERVED0 0x00000008L +#define SQ_DEBUG_TP_FSM__CF_TP_MASK 0x000000f0L +#define SQ_DEBUG_TP_FSM__IF_TP_MASK 0x00000700L +#define SQ_DEBUG_TP_FSM__RESERVED1_MASK 0x00000800L +#define SQ_DEBUG_TP_FSM__RESERVED1 0x00000800L +#define SQ_DEBUG_TP_FSM__TIS_TP_MASK 0x00003000L +#define SQ_DEBUG_TP_FSM__RESERVED2_MASK 0x0000c000L +#define SQ_DEBUG_TP_FSM__GS_TP_MASK 0x00030000L +#define SQ_DEBUG_TP_FSM__RESERVED3_MASK 0x000c0000L +#define SQ_DEBUG_TP_FSM__FCR_TP_MASK 0x00300000L +#define SQ_DEBUG_TP_FSM__RESERVED4_MASK 0x00c00000L +#define SQ_DEBUG_TP_FSM__FCS_TP_MASK 0x03000000L +#define SQ_DEBUG_TP_FSM__RESERVED5_MASK 0x0c000000L +#define SQ_DEBUG_TP_FSM__ARB_TR_TP_MASK 0x70000000L + +// SQ_DEBUG_FSM_ALU_0 +#define SQ_DEBUG_FSM_ALU_0__EX_ALU_0_MASK 0x00000007L +#define SQ_DEBUG_FSM_ALU_0__RESERVED0_MASK 0x00000008L +#define SQ_DEBUG_FSM_ALU_0__RESERVED0 0x00000008L +#define SQ_DEBUG_FSM_ALU_0__CF_ALU_0_MASK 0x000000f0L +#define SQ_DEBUG_FSM_ALU_0__IF_ALU_0_MASK 0x00000700L +#define SQ_DEBUG_FSM_ALU_0__RESERVED1_MASK 0x00000800L +#define SQ_DEBUG_FSM_ALU_0__RESERVED1 0x00000800L +#define SQ_DEBUG_FSM_ALU_0__DU1_ALU_0_MASK 0x00007000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED2_MASK 0x00008000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED2 0x00008000L +#define SQ_DEBUG_FSM_ALU_0__DU0_ALU_0_MASK 0x00070000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED3_MASK 0x00080000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED3 0x00080000L +#define SQ_DEBUG_FSM_ALU_0__AIS_ALU_0_MASK 0x00700000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED4_MASK 0x00800000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED4 0x00800000L +#define SQ_DEBUG_FSM_ALU_0__ACS_ALU_0_MASK 0x07000000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED5_MASK 0x08000000L +#define SQ_DEBUG_FSM_ALU_0__RESERVED5 0x08000000L +#define SQ_DEBUG_FSM_ALU_0__ARB_TR_ALU_MASK 0x70000000L + +// SQ_DEBUG_FSM_ALU_1 +#define SQ_DEBUG_FSM_ALU_1__EX_ALU_0_MASK 0x00000007L +#define SQ_DEBUG_FSM_ALU_1__RESERVED0_MASK 0x00000008L +#define SQ_DEBUG_FSM_ALU_1__RESERVED0 0x00000008L +#define SQ_DEBUG_FSM_ALU_1__CF_ALU_0_MASK 0x000000f0L +#define SQ_DEBUG_FSM_ALU_1__IF_ALU_0_MASK 0x00000700L +#define SQ_DEBUG_FSM_ALU_1__RESERVED1_MASK 0x00000800L +#define SQ_DEBUG_FSM_ALU_1__RESERVED1 0x00000800L +#define SQ_DEBUG_FSM_ALU_1__DU1_ALU_0_MASK 0x00007000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED2_MASK 0x00008000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED2 0x00008000L +#define SQ_DEBUG_FSM_ALU_1__DU0_ALU_0_MASK 0x00070000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED3_MASK 0x00080000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED3 0x00080000L +#define SQ_DEBUG_FSM_ALU_1__AIS_ALU_0_MASK 0x00700000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED4_MASK 0x00800000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED4 0x00800000L +#define SQ_DEBUG_FSM_ALU_1__ACS_ALU_0_MASK 0x07000000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED5_MASK 0x08000000L +#define SQ_DEBUG_FSM_ALU_1__RESERVED5 0x08000000L +#define SQ_DEBUG_FSM_ALU_1__ARB_TR_ALU_MASK 0x70000000L + +// SQ_DEBUG_EXP_ALLOC +#define SQ_DEBUG_EXP_ALLOC__POS_BUF_AVAIL_MASK 0x0000000fL +#define SQ_DEBUG_EXP_ALLOC__COLOR_BUF_AVAIL_MASK 0x00000ff0L +#define SQ_DEBUG_EXP_ALLOC__EA_BUF_AVAIL_MASK 0x00007000L +#define SQ_DEBUG_EXP_ALLOC__RESERVED_MASK 0x00008000L +#define SQ_DEBUG_EXP_ALLOC__RESERVED 0x00008000L +#define SQ_DEBUG_EXP_ALLOC__ALLOC_TBL_BUF_AVAIL_MASK 0x003f0000L + +// SQ_DEBUG_PTR_BUFF +#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER_MASK 0x00000001L +#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER 0x00000001L +#define SQ_DEBUG_PTR_BUFF__DEALLOC_CNT_MASK 0x0000001eL +#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR_MASK 0x00000020L +#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR 0x00000020L +#define SQ_DEBUG_PTR_BUFF__EVENT_CONTEXT_ID_MASK 0x000001c0L +#define SQ_DEBUG_PTR_BUFF__SC_EVENT_ID_MASK 0x00003e00L +#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT_MASK 0x00004000L +#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT 0x00004000L +#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON_MASK 0x00008000L +#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON 0x00008000L +#define SQ_DEBUG_PTR_BUFF__EF_EMPTY_MASK 0x00010000L +#define SQ_DEBUG_PTR_BUFF__EF_EMPTY 0x00010000L +#define SQ_DEBUG_PTR_BUFF__VTX_SYNC_CNT_MASK 0x0ffe0000L + +// SQ_DEBUG_GPR_VTX +#define SQ_DEBUG_GPR_VTX__VTX_TAIL_PTR_MASK 0x0000007fL +#define SQ_DEBUG_GPR_VTX__RESERVED_MASK 0x00000080L +#define SQ_DEBUG_GPR_VTX__RESERVED 0x00000080L +#define SQ_DEBUG_GPR_VTX__VTX_HEAD_PTR_MASK 0x00007f00L +#define SQ_DEBUG_GPR_VTX__RESERVED1_MASK 0x00008000L +#define SQ_DEBUG_GPR_VTX__RESERVED1 0x00008000L +#define SQ_DEBUG_GPR_VTX__VTX_MAX_MASK 0x007f0000L +#define SQ_DEBUG_GPR_VTX__RESERVED2_MASK 0x00800000L +#define SQ_DEBUG_GPR_VTX__RESERVED2 0x00800000L +#define SQ_DEBUG_GPR_VTX__VTX_FREE_MASK 0x7f000000L + +// SQ_DEBUG_GPR_PIX +#define SQ_DEBUG_GPR_PIX__PIX_TAIL_PTR_MASK 0x0000007fL +#define SQ_DEBUG_GPR_PIX__RESERVED_MASK 0x00000080L +#define SQ_DEBUG_GPR_PIX__RESERVED 0x00000080L +#define SQ_DEBUG_GPR_PIX__PIX_HEAD_PTR_MASK 0x00007f00L +#define SQ_DEBUG_GPR_PIX__RESERVED1_MASK 0x00008000L +#define SQ_DEBUG_GPR_PIX__RESERVED1 0x00008000L +#define SQ_DEBUG_GPR_PIX__PIX_MAX_MASK 0x007f0000L +#define SQ_DEBUG_GPR_PIX__RESERVED2_MASK 0x00800000L +#define SQ_DEBUG_GPR_PIX__RESERVED2 0x00800000L +#define SQ_DEBUG_GPR_PIX__PIX_FREE_MASK 0x7f000000L + +// SQ_DEBUG_TB_STATUS_SEL +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATUS_REG_SEL_MASK 0x0000000fL +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_DW_SEL_MASK 0x00000070L +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_ADDR_MASK 0x00000780L +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN_MASK 0x00000800L +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN 0x00000800L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN_MASK 0x00001000L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN 0x00001000L +#define SQ_DEBUG_TB_STATUS_SEL__DEBUG_BUS_TRIGGER_SEL_MASK 0x0000c000L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATUS_REG_SEL_MASK 0x000f0000L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_DW_SEL_MASK 0x00700000L +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_ADDR_MASK 0x1f800000L +#define SQ_DEBUG_TB_STATUS_SEL__VC_THREAD_BUF_DLY_MASK 0x60000000L +#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC_MASK 0x80000000L +#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC 0x80000000L + +// SQ_DEBUG_VTX_TB_0 +#define SQ_DEBUG_VTX_TB_0__VTX_HEAD_PTR_Q_MASK 0x0000000fL +#define SQ_DEBUG_VTX_TB_0__TAIL_PTR_Q_MASK 0x000000f0L +#define SQ_DEBUG_VTX_TB_0__FULL_CNT_Q_MASK 0x00000f00L +#define SQ_DEBUG_VTX_TB_0__NXT_POS_ALLOC_CNT_MASK 0x0000f000L +#define SQ_DEBUG_VTX_TB_0__NXT_PC_ALLOC_CNT_MASK 0x000f0000L +#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL_MASK 0x00100000L +#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL 0x00100000L +#define SQ_DEBUG_VTX_TB_0__BUSY_Q_MASK 0x00200000L +#define SQ_DEBUG_VTX_TB_0__BUSY_Q 0x00200000L + +// SQ_DEBUG_VTX_TB_1 +#define SQ_DEBUG_VTX_TB_1__VS_DONE_PTR_MASK 0x0000ffffL + +// SQ_DEBUG_VTX_TB_STATUS_REG +#define SQ_DEBUG_VTX_TB_STATUS_REG__VS_STATUS_REG_MASK 0xffffffffL + +// SQ_DEBUG_VTX_TB_STATE_MEM +#define SQ_DEBUG_VTX_TB_STATE_MEM__VS_STATE_MEM_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_0 +#define SQ_DEBUG_PIX_TB_0__PIX_HEAD_PTR_MASK 0x0000003fL +#define SQ_DEBUG_PIX_TB_0__TAIL_PTR_MASK 0x00000fc0L +#define SQ_DEBUG_PIX_TB_0__FULL_CNT_MASK 0x0007f000L +#define SQ_DEBUG_PIX_TB_0__NXT_PIX_ALLOC_CNT_MASK 0x01f80000L +#define SQ_DEBUG_PIX_TB_0__NXT_PIX_EXP_CNT_MASK 0x7e000000L +#define SQ_DEBUG_PIX_TB_0__BUSY_MASK 0x80000000L +#define SQ_DEBUG_PIX_TB_0__BUSY 0x80000000L + +// SQ_DEBUG_PIX_TB_STATUS_REG_0 +#define SQ_DEBUG_PIX_TB_STATUS_REG_0__PIX_TB_STATUS_REG_0_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_STATUS_REG_1 +#define SQ_DEBUG_PIX_TB_STATUS_REG_1__PIX_TB_STATUS_REG_1_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_STATUS_REG_2 +#define SQ_DEBUG_PIX_TB_STATUS_REG_2__PIX_TB_STATUS_REG_2_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_STATUS_REG_3 +#define SQ_DEBUG_PIX_TB_STATUS_REG_3__PIX_TB_STATUS_REG_3_MASK 0xffffffffL + +// SQ_DEBUG_PIX_TB_STATE_MEM +#define SQ_DEBUG_PIX_TB_STATE_MEM__PIX_TB_STATE_MEM_MASK 0xffffffffL + +// SQ_PERFCOUNTER0_SELECT +#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// SQ_PERFCOUNTER1_SELECT +#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL + +// SQ_PERFCOUNTER2_SELECT +#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL + +// SQ_PERFCOUNTER3_SELECT +#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL + +// SQ_PERFCOUNTER0_LOW +#define SQ_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// SQ_PERFCOUNTER0_HI +#define SQ_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// SQ_PERFCOUNTER1_LOW +#define SQ_PERFCOUNTER1_LOW__PERF_COUNT_MASK 0xffffffffL + +// SQ_PERFCOUNTER1_HI +#define SQ_PERFCOUNTER1_HI__PERF_COUNT_MASK 0x0000ffffL + +// SQ_PERFCOUNTER2_LOW +#define SQ_PERFCOUNTER2_LOW__PERF_COUNT_MASK 0xffffffffL + +// SQ_PERFCOUNTER2_HI +#define SQ_PERFCOUNTER2_HI__PERF_COUNT_MASK 0x0000ffffL + +// SQ_PERFCOUNTER3_LOW +#define SQ_PERFCOUNTER3_LOW__PERF_COUNT_MASK 0xffffffffL + +// SQ_PERFCOUNTER3_HI +#define SQ_PERFCOUNTER3_HI__PERF_COUNT_MASK 0x0000ffffL + +// SX_PERFCOUNTER0_SELECT +#define SX_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// SX_PERFCOUNTER0_LOW +#define SX_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// SX_PERFCOUNTER0_HI +#define SX_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// SQ_INSTRUCTION_ALU_0 +#define SQ_INSTRUCTION_ALU_0__VECTOR_RESULT_MASK 0x0000003fL +#define SQ_INSTRUCTION_ALU_0__VECTOR_DST_REL_MASK 0x00000040L +#define SQ_INSTRUCTION_ALU_0__VECTOR_DST_REL 0x00000040L +#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP_MASK 0x00000080L +#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP 0x00000080L +#define SQ_INSTRUCTION_ALU_0__SCALAR_RESULT_MASK 0x00003f00L +#define SQ_INSTRUCTION_ALU_0__SCALAR_DST_REL_MASK 0x00004000L +#define SQ_INSTRUCTION_ALU_0__SCALAR_DST_REL 0x00004000L +#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA_MASK 0x00008000L +#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA 0x00008000L +#define SQ_INSTRUCTION_ALU_0__VECTOR_WRT_MSK_MASK 0x000f0000L +#define SQ_INSTRUCTION_ALU_0__SCALAR_WRT_MSK_MASK 0x00f00000L +#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP_MASK 0x01000000L +#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP 0x01000000L +#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP_MASK 0x02000000L +#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP 0x02000000L +#define SQ_INSTRUCTION_ALU_0__SCALAR_OPCODE_MASK 0xfc000000L + +// SQ_INSTRUCTION_ALU_1 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_R_MASK 0x00000003L +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_G_MASK 0x0000000cL +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_B_MASK 0x00000030L +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_A_MASK 0x000000c0L +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_R_MASK 0x00000300L +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_G_MASK 0x00000c00L +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_B_MASK 0x00003000L +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_A_MASK 0x0000c000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_R_MASK 0x00030000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_G_MASK 0x000c0000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_B_MASK 0x00300000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_A_MASK 0x00c00000L +#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD_MASK 0x01000000L +#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD 0x01000000L +#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD_MASK 0x02000000L +#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD 0x02000000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD_MASK 0x04000000L +#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD 0x04000000L +#define SQ_INSTRUCTION_ALU_1__PRED_SELECT_MASK 0x18000000L +#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR_MASK 0x20000000L +#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR 0x20000000L +#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS_MASK 0x40000000L +#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS 0x40000000L +#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS_MASK 0x80000000L +#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS 0x80000000L + +// SQ_INSTRUCTION_ALU_2 +#define SQ_INSTRUCTION_ALU_2__SRC_C_REG_PTR_MASK 0x0000003fL +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C_MASK 0x00000040L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C 0x00000040L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C_MASK 0x00000080L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C 0x00000080L +#define SQ_INSTRUCTION_ALU_2__SRC_B_REG_PTR_MASK 0x00003f00L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B_MASK 0x00004000L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B 0x00004000L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B_MASK 0x00008000L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B 0x00008000L +#define SQ_INSTRUCTION_ALU_2__SRC_A_REG_PTR_MASK 0x003f0000L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A_MASK 0x00400000L +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A 0x00400000L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A_MASK 0x00800000L +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A 0x00800000L +#define SQ_INSTRUCTION_ALU_2__VECTOR_OPCODE_MASK 0x1f000000L +#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL_MASK 0x20000000L +#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL 0x20000000L +#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL_MASK 0x40000000L +#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL 0x40000000L +#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL_MASK 0x80000000L +#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL 0x80000000L + +// SQ_INSTRUCTION_CF_EXEC_0 +#define SQ_INSTRUCTION_CF_EXEC_0__ADDRESS_MASK 0x000001ffL +#define SQ_INSTRUCTION_CF_EXEC_0__RESERVED_MASK 0x00000e00L +#define SQ_INSTRUCTION_CF_EXEC_0__COUNT_MASK 0x00007000L +#define SQ_INSTRUCTION_CF_EXEC_0__YIELD_MASK 0x00008000L +#define SQ_INSTRUCTION_CF_EXEC_0__YIELD 0x00008000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0_MASK 0x00010000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0 0x00010000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0_MASK 0x00020000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0 0x00020000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1_MASK 0x00040000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1 0x00040000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1_MASK 0x00080000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1 0x00080000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2_MASK 0x00100000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2 0x00100000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2_MASK 0x00200000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2 0x00200000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3_MASK 0x00400000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3 0x00400000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3_MASK 0x00800000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3 0x00800000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4_MASK 0x01000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4 0x01000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4_MASK 0x02000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4 0x02000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5_MASK 0x04000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5 0x04000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5 0x08000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0_MASK 0x10000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0 0x10000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1_MASK 0x20000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1 0x20000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2_MASK 0x40000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2 0x40000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3_MASK 0x80000000L +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3 0x80000000L + +// SQ_INSTRUCTION_CF_EXEC_1 +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4_MASK 0x00000001L +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4 0x00000001L +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5_MASK 0x00000002L +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5 0x00000002L +#define SQ_INSTRUCTION_CF_EXEC_1__BOOL_ADDR_MASK 0x000003fcL +#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION_MASK 0x00000400L +#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION 0x00000400L +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE 0x00000800L +#define SQ_INSTRUCTION_CF_EXEC_1__OPCODE_MASK 0x0000f000L +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MASK 0x01ff0000L +#define SQ_INSTRUCTION_CF_EXEC_1__RESERVED_MASK 0x0e000000L +#define SQ_INSTRUCTION_CF_EXEC_1__COUNT_MASK 0x70000000L +#define SQ_INSTRUCTION_CF_EXEC_1__YIELD_MASK 0x80000000L +#define SQ_INSTRUCTION_CF_EXEC_1__YIELD 0x80000000L + +// SQ_INSTRUCTION_CF_EXEC_2 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0_MASK 0x00000001L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0 0x00000001L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0_MASK 0x00000002L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0 0x00000002L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1_MASK 0x00000004L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1 0x00000004L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1_MASK 0x00000008L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1 0x00000008L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2_MASK 0x00000010L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2 0x00000010L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2_MASK 0x00000020L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2 0x00000020L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3_MASK 0x00000040L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3 0x00000040L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3_MASK 0x00000080L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3 0x00000080L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4_MASK 0x00000100L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4 0x00000100L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4_MASK 0x00000200L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4 0x00000200L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5_MASK 0x00000400L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5 0x00000400L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5 0x00000800L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0_MASK 0x00001000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0 0x00001000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1_MASK 0x00002000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1 0x00002000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2_MASK 0x00004000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2 0x00004000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3_MASK 0x00008000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3 0x00008000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4_MASK 0x00010000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4 0x00010000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5_MASK 0x00020000L +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5 0x00020000L +#define SQ_INSTRUCTION_CF_EXEC_2__BOOL_ADDR_MASK 0x03fc0000L +#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION_MASK 0x04000000L +#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION 0x04000000L +#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE 0x08000000L +#define SQ_INSTRUCTION_CF_EXEC_2__OPCODE_MASK 0xf0000000L + +// SQ_INSTRUCTION_CF_LOOP_0 +#define SQ_INSTRUCTION_CF_LOOP_0__ADDRESS_MASK 0x000003ffL +#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_0_MASK 0x0000fc00L +#define SQ_INSTRUCTION_CF_LOOP_0__LOOP_ID_MASK 0x001f0000L +#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_1_MASK 0xffe00000L + +// SQ_INSTRUCTION_CF_LOOP_1 +#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_0_MASK 0x000007ffL +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE 0x00000800L +#define SQ_INSTRUCTION_CF_LOOP_1__OPCODE_MASK 0x0000f000L +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MASK 0x03ff0000L +#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_1_MASK 0xfc000000L + +// SQ_INSTRUCTION_CF_LOOP_2 +#define SQ_INSTRUCTION_CF_LOOP_2__LOOP_ID_MASK 0x0000001fL +#define SQ_INSTRUCTION_CF_LOOP_2__RESERVED_MASK 0x07ffffe0L +#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE 0x08000000L +#define SQ_INSTRUCTION_CF_LOOP_2__OPCODE_MASK 0xf0000000L + +// SQ_INSTRUCTION_CF_JMP_CALL_0 +#define SQ_INSTRUCTION_CF_JMP_CALL_0__ADDRESS_MASK 0x000003ffL +#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_0_MASK 0x00001c00L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL_MASK 0x00002000L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL 0x00002000L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP_MASK 0x00004000L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP 0x00004000L +#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_1_MASK 0xffff8000L + +// SQ_INSTRUCTION_CF_JMP_CALL_1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0_MASK 0x00000001L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0 0x00000001L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION_MASK 0x00000002L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION 0x00000002L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__BOOL_ADDR_MASK 0x000003fcL +#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION_MASK 0x00000400L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION 0x00000400L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE 0x00000800L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__OPCODE_MASK 0x0000f000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MASK 0x03ff0000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_1_MASK 0x1c000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL_MASK 0x20000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL 0x20000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_2_MASK 0xc0000000L + +// SQ_INSTRUCTION_CF_JMP_CALL_2 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__RESERVED_MASK 0x0001ffffL +#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION_MASK 0x00020000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION 0x00020000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__BOOL_ADDR_MASK 0x03fc0000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION_MASK 0x04000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION 0x04000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE 0x08000000L +#define SQ_INSTRUCTION_CF_JMP_CALL_2__OPCODE_MASK 0xf0000000L + +// SQ_INSTRUCTION_CF_ALLOC_0 +#define SQ_INSTRUCTION_CF_ALLOC_0__SIZE_MASK 0x0000000fL +#define SQ_INSTRUCTION_CF_ALLOC_0__RESERVED_MASK 0xfffffff0L + +// SQ_INSTRUCTION_CF_ALLOC_1 +#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_0_MASK 0x000000ffL +#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL_MASK 0x00000100L +#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL 0x00000100L +#define SQ_INSTRUCTION_CF_ALLOC_1__BUFFER_SELECT_MASK 0x00000600L +#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE_MASK 0x00000800L +#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE 0x00000800L +#define SQ_INSTRUCTION_CF_ALLOC_1__OPCODE_MASK 0x0000f000L +#define SQ_INSTRUCTION_CF_ALLOC_1__SIZE_MASK 0x000f0000L +#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_1_MASK 0xfff00000L + +// SQ_INSTRUCTION_CF_ALLOC_2 +#define SQ_INSTRUCTION_CF_ALLOC_2__RESERVED_MASK 0x00ffffffL +#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL_MASK 0x01000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL 0x01000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__BUFFER_SELECT_MASK 0x06000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE_MASK 0x08000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE 0x08000000L +#define SQ_INSTRUCTION_CF_ALLOC_2__OPCODE_MASK 0xf0000000L + +// SQ_INSTRUCTION_TFETCH_0 +#define SQ_INSTRUCTION_TFETCH_0__OPCODE_MASK 0x0000001fL +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_MASK 0x000007e0L +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM_MASK 0x00000800L +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM 0x00000800L +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_MASK 0x0003f000L +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM_MASK 0x00040000L +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM 0x00040000L +#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY_MASK 0x00080000L +#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY 0x00080000L +#define SQ_INSTRUCTION_TFETCH_0__CONST_INDEX_MASK 0x01f00000L +#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM_MASK 0x02000000L +#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM 0x02000000L +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_X_MASK 0x0c000000L +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Y_MASK 0x30000000L +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Z_MASK 0xc0000000L + +// SQ_INSTRUCTION_TFETCH_1 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_X_MASK 0x00000007L +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Y_MASK 0x00000038L +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Z_MASK 0x000001c0L +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_W_MASK 0x00000e00L +#define SQ_INSTRUCTION_TFETCH_1__MAG_FILTER_MASK 0x00003000L +#define SQ_INSTRUCTION_TFETCH_1__MIN_FILTER_MASK 0x0000c000L +#define SQ_INSTRUCTION_TFETCH_1__MIP_FILTER_MASK 0x00030000L +#define SQ_INSTRUCTION_TFETCH_1__ANISO_FILTER_MASK 0x001c0000L +#define SQ_INSTRUCTION_TFETCH_1__ARBITRARY_FILTER_MASK 0x00e00000L +#define SQ_INSTRUCTION_TFETCH_1__VOL_MAG_FILTER_MASK 0x03000000L +#define SQ_INSTRUCTION_TFETCH_1__VOL_MIN_FILTER_MASK 0x0c000000L +#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD_MASK 0x10000000L +#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD 0x10000000L +#define SQ_INSTRUCTION_TFETCH_1__USE_REG_LOD_MASK 0x60000000L +#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT_MASK 0x80000000L +#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT 0x80000000L + +// SQ_INSTRUCTION_TFETCH_2 +#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS_MASK 0x00000001L +#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS 0x00000001L +#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION_MASK 0x00000002L +#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION 0x00000002L +#define SQ_INSTRUCTION_TFETCH_2__LOD_BIAS_MASK 0x000001fcL +#define SQ_INSTRUCTION_TFETCH_2__UNUSED_MASK 0x0000fe00L +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_X_MASK 0x001f0000L +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Y_MASK 0x03e00000L +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Z_MASK 0x7c000000L +#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION_MASK 0x80000000L +#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION 0x80000000L + +// SQ_INSTRUCTION_VFETCH_0 +#define SQ_INSTRUCTION_VFETCH_0__OPCODE_MASK 0x0000001fL +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_MASK 0x000007e0L +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM_MASK 0x00000800L +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM 0x00000800L +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_MASK 0x0003f000L +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM_MASK 0x00040000L +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM 0x00040000L +#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE_MASK 0x00080000L +#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE 0x00080000L +#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_MASK 0x01f00000L +#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_SEL_MASK 0x06000000L +#define SQ_INSTRUCTION_VFETCH_0__SRC_SEL_MASK 0xc0000000L + +// SQ_INSTRUCTION_VFETCH_1 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_X_MASK 0x00000007L +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Y_MASK 0x00000038L +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Z_MASK 0x000001c0L +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_W_MASK 0x00000e00L +#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL_MASK 0x00001000L +#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL 0x00001000L +#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL_MASK 0x00002000L +#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL 0x00002000L +#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL_MASK 0x00004000L +#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL 0x00004000L +#define SQ_INSTRUCTION_VFETCH_1__DATA_FORMAT_MASK 0x003f0000L +#define SQ_INSTRUCTION_VFETCH_1__EXP_ADJUST_ALL_MASK 0x3f800000L +#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT_MASK 0x80000000L +#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT 0x80000000L + +// SQ_INSTRUCTION_VFETCH_2 +#define SQ_INSTRUCTION_VFETCH_2__STRIDE_MASK 0x000000ffL +#define SQ_INSTRUCTION_VFETCH_2__OFFSET_MASK 0x00ff0000L +#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION_MASK 0x80000000L +#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION 0x80000000L + +// SQ_CONSTANT_0 +#define SQ_CONSTANT_0__RED_MASK 0xffffffffL + +// SQ_CONSTANT_1 +#define SQ_CONSTANT_1__GREEN_MASK 0xffffffffL + +// SQ_CONSTANT_2 +#define SQ_CONSTANT_2__BLUE_MASK 0xffffffffL + +// SQ_CONSTANT_3 +#define SQ_CONSTANT_3__ALPHA_MASK 0xffffffffL + +// SQ_FETCH_0 +#define SQ_FETCH_0__VALUE_MASK 0xffffffffL + +// SQ_FETCH_1 +#define SQ_FETCH_1__VALUE_MASK 0xffffffffL + +// SQ_FETCH_2 +#define SQ_FETCH_2__VALUE_MASK 0xffffffffL + +// SQ_FETCH_3 +#define SQ_FETCH_3__VALUE_MASK 0xffffffffL + +// SQ_FETCH_4 +#define SQ_FETCH_4__VALUE_MASK 0xffffffffL + +// SQ_FETCH_5 +#define SQ_FETCH_5__VALUE_MASK 0xffffffffL + +// SQ_CONSTANT_VFETCH_0 +#define SQ_CONSTANT_VFETCH_0__TYPE_MASK 0x00000001L +#define SQ_CONSTANT_VFETCH_0__TYPE 0x00000001L +#define SQ_CONSTANT_VFETCH_0__STATE_MASK 0x00000002L +#define SQ_CONSTANT_VFETCH_0__STATE 0x00000002L +#define SQ_CONSTANT_VFETCH_0__BASE_ADDRESS_MASK 0xfffffffcL + +// SQ_CONSTANT_VFETCH_1 +#define SQ_CONSTANT_VFETCH_1__ENDIAN_SWAP_MASK 0x00000003L +#define SQ_CONSTANT_VFETCH_1__LIMIT_ADDRESS_MASK 0xfffffffcL + +// SQ_CONSTANT_T2 +#define SQ_CONSTANT_T2__VALUE_MASK 0xffffffffL + +// SQ_CONSTANT_T3 +#define SQ_CONSTANT_T3__VALUE_MASK 0xffffffffL + +// SQ_CF_BOOLEANS +#define SQ_CF_BOOLEANS__CF_BOOLEANS_0_MASK 0x000000ffL +#define SQ_CF_BOOLEANS__CF_BOOLEANS_1_MASK 0x0000ff00L +#define SQ_CF_BOOLEANS__CF_BOOLEANS_2_MASK 0x00ff0000L +#define SQ_CF_BOOLEANS__CF_BOOLEANS_3_MASK 0xff000000L + +// SQ_CF_LOOP +#define SQ_CF_LOOP__CF_LOOP_COUNT_MASK 0x000000ffL +#define SQ_CF_LOOP__CF_LOOP_START_MASK 0x0000ff00L +#define SQ_CF_LOOP__CF_LOOP_STEP_MASK 0x00ff0000L + +// SQ_CONSTANT_RT_0 +#define SQ_CONSTANT_RT_0__RED_MASK 0xffffffffL + +// SQ_CONSTANT_RT_1 +#define SQ_CONSTANT_RT_1__GREEN_MASK 0xffffffffL + +// SQ_CONSTANT_RT_2 +#define SQ_CONSTANT_RT_2__BLUE_MASK 0xffffffffL + +// SQ_CONSTANT_RT_3 +#define SQ_CONSTANT_RT_3__ALPHA_MASK 0xffffffffL + +// SQ_FETCH_RT_0 +#define SQ_FETCH_RT_0__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_1 +#define SQ_FETCH_RT_1__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_2 +#define SQ_FETCH_RT_2__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_3 +#define SQ_FETCH_RT_3__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_4 +#define SQ_FETCH_RT_4__VALUE_MASK 0xffffffffL + +// SQ_FETCH_RT_5 +#define SQ_FETCH_RT_5__VALUE_MASK 0xffffffffL + +// SQ_CF_RT_BOOLEANS +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_0_MASK 0x000000ffL +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_1_MASK 0x0000ff00L +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_2_MASK 0x00ff0000L +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_3_MASK 0xff000000L + +// SQ_CF_RT_LOOP +#define SQ_CF_RT_LOOP__CF_LOOP_COUNT_MASK 0x000000ffL +#define SQ_CF_RT_LOOP__CF_LOOP_START_MASK 0x0000ff00L +#define SQ_CF_RT_LOOP__CF_LOOP_STEP_MASK 0x00ff0000L + +// SQ_VS_PROGRAM +#define SQ_VS_PROGRAM__BASE_MASK 0x00000fffL +#define SQ_VS_PROGRAM__SIZE_MASK 0x00fff000L + +// SQ_PS_PROGRAM +#define SQ_PS_PROGRAM__BASE_MASK 0x00000fffL +#define SQ_PS_PROGRAM__SIZE_MASK 0x00fff000L + +// SQ_CF_PROGRAM_SIZE +#define SQ_CF_PROGRAM_SIZE__VS_CF_SIZE_MASK 0x000007ffL +#define SQ_CF_PROGRAM_SIZE__PS_CF_SIZE_MASK 0x007ff000L + +// SQ_INTERPOLATOR_CNTL +#define SQ_INTERPOLATOR_CNTL__PARAM_SHADE_MASK 0x0000ffffL +#define SQ_INTERPOLATOR_CNTL__SAMPLING_PATTERN_MASK 0xffff0000L + +// SQ_PROGRAM_CNTL +#define SQ_PROGRAM_CNTL__VS_NUM_REG_MASK 0x0000003fL +#define SQ_PROGRAM_CNTL__PS_NUM_REG_MASK 0x00003f00L +#define SQ_PROGRAM_CNTL__VS_RESOURCE_MASK 0x00010000L +#define SQ_PROGRAM_CNTL__VS_RESOURCE 0x00010000L +#define SQ_PROGRAM_CNTL__PS_RESOURCE_MASK 0x00020000L +#define SQ_PROGRAM_CNTL__PS_RESOURCE 0x00020000L +#define SQ_PROGRAM_CNTL__PARAM_GEN_MASK 0x00040000L +#define SQ_PROGRAM_CNTL__PARAM_GEN 0x00040000L +#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX_MASK 0x00080000L +#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX 0x00080000L +#define SQ_PROGRAM_CNTL__VS_EXPORT_COUNT_MASK 0x00f00000L +#define SQ_PROGRAM_CNTL__VS_EXPORT_MODE_MASK 0x07000000L +#define SQ_PROGRAM_CNTL__PS_EXPORT_MODE_MASK 0x78000000L +#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX_MASK 0x80000000L +#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX 0x80000000L + +// SQ_WRAPPING_0 +#define SQ_WRAPPING_0__PARAM_WRAP_0_MASK 0x0000000fL +#define SQ_WRAPPING_0__PARAM_WRAP_1_MASK 0x000000f0L +#define SQ_WRAPPING_0__PARAM_WRAP_2_MASK 0x00000f00L +#define SQ_WRAPPING_0__PARAM_WRAP_3_MASK 0x0000f000L +#define SQ_WRAPPING_0__PARAM_WRAP_4_MASK 0x000f0000L +#define SQ_WRAPPING_0__PARAM_WRAP_5_MASK 0x00f00000L +#define SQ_WRAPPING_0__PARAM_WRAP_6_MASK 0x0f000000L +#define SQ_WRAPPING_0__PARAM_WRAP_7_MASK 0xf0000000L + +// SQ_WRAPPING_1 +#define SQ_WRAPPING_1__PARAM_WRAP_8_MASK 0x0000000fL +#define SQ_WRAPPING_1__PARAM_WRAP_9_MASK 0x000000f0L +#define SQ_WRAPPING_1__PARAM_WRAP_10_MASK 0x00000f00L +#define SQ_WRAPPING_1__PARAM_WRAP_11_MASK 0x0000f000L +#define SQ_WRAPPING_1__PARAM_WRAP_12_MASK 0x000f0000L +#define SQ_WRAPPING_1__PARAM_WRAP_13_MASK 0x00f00000L +#define SQ_WRAPPING_1__PARAM_WRAP_14_MASK 0x0f000000L +#define SQ_WRAPPING_1__PARAM_WRAP_15_MASK 0xf0000000L + +// SQ_VS_CONST +#define SQ_VS_CONST__BASE_MASK 0x000001ffL +#define SQ_VS_CONST__SIZE_MASK 0x001ff000L + +// SQ_PS_CONST +#define SQ_PS_CONST__BASE_MASK 0x000001ffL +#define SQ_PS_CONST__SIZE_MASK 0x001ff000L + +// SQ_CONTEXT_MISC +#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE_MASK 0x00000001L +#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE 0x00000001L +#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY_MASK 0x00000002L +#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY 0x00000002L +#define SQ_CONTEXT_MISC__SC_SAMPLE_CNTL_MASK 0x0000000cL +#define SQ_CONTEXT_MISC__PARAM_GEN_POS_MASK 0x0000ff00L +#define SQ_CONTEXT_MISC__PERFCOUNTER_REF_MASK 0x00010000L +#define SQ_CONTEXT_MISC__PERFCOUNTER_REF 0x00010000L +#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE_MASK 0x00020000L +#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE 0x00020000L +#define SQ_CONTEXT_MISC__TX_CACHE_SEL_MASK 0x00040000L +#define SQ_CONTEXT_MISC__TX_CACHE_SEL 0x00040000L + +// SQ_CF_RD_BASE +#define SQ_CF_RD_BASE__RD_BASE_MASK 0x00000007L + +// SQ_DEBUG_MISC_0 +#define SQ_DEBUG_MISC_0__DB_PROB_ON_MASK 0x00000001L +#define SQ_DEBUG_MISC_0__DB_PROB_ON 0x00000001L +#define SQ_DEBUG_MISC_0__DB_PROB_BREAK_MASK 0x00000010L +#define SQ_DEBUG_MISC_0__DB_PROB_BREAK 0x00000010L +#define SQ_DEBUG_MISC_0__DB_PROB_ADDR_MASK 0x0007ff00L +#define SQ_DEBUG_MISC_0__DB_PROB_COUNT_MASK 0xff000000L + +// SQ_DEBUG_MISC_1 +#define SQ_DEBUG_MISC_1__DB_ON_PIX_MASK 0x00000001L +#define SQ_DEBUG_MISC_1__DB_ON_PIX 0x00000001L +#define SQ_DEBUG_MISC_1__DB_ON_VTX_MASK 0x00000002L +#define SQ_DEBUG_MISC_1__DB_ON_VTX 0x00000002L +#define SQ_DEBUG_MISC_1__DB_INST_COUNT_MASK 0x0000ff00L +#define SQ_DEBUG_MISC_1__DB_BREAK_ADDR_MASK 0x07ff0000L + +// MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG__SAME_PAGE_LIMIT_MASK 0x0000003fL +#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY_MASK 0x00000040L +#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY 0x00000040L +#define MH_ARBITER_CONFIG__L1_ARB_ENABLE_MASK 0x00000080L +#define MH_ARBITER_CONFIG__L1_ARB_ENABLE 0x00000080L +#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE_MASK 0x00000100L +#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE 0x00000100L +#define MH_ARBITER_CONFIG__L2_ARB_CONTROL_MASK 0x00000200L +#define MH_ARBITER_CONFIG__L2_ARB_CONTROL 0x00000200L +#define MH_ARBITER_CONFIG__PAGE_SIZE_MASK 0x00001c00L +#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE_MASK 0x00002000L +#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE 0x00002000L +#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE_MASK 0x00004000L +#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE 0x00004000L +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE_MASK 0x00008000L +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE 0x00008000L +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_MASK 0x003f0000L +#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE_MASK 0x00400000L +#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE 0x00400000L +#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE_MASK 0x00800000L +#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE 0x00800000L +#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE_MASK 0x01000000L +#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE 0x01000000L +#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE_MASK 0x02000000L +#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE 0x02000000L +#define MH_ARBITER_CONFIG__PA_CLNT_ENABLE_MASK 0x04000000L +#define MH_ARBITER_CONFIG__PA_CLNT_ENABLE 0x04000000L + +// MH_CLNT_AXI_ID_REUSE +#define MH_CLNT_AXI_ID_REUSE__CPw_ID_MASK 0x00000007L +#define MH_CLNT_AXI_ID_REUSE__RESERVED1_MASK 0x00000008L +#define MH_CLNT_AXI_ID_REUSE__RESERVED1 0x00000008L +#define MH_CLNT_AXI_ID_REUSE__RBw_ID_MASK 0x00000070L +#define MH_CLNT_AXI_ID_REUSE__RESERVED2_MASK 0x00000080L +#define MH_CLNT_AXI_ID_REUSE__RESERVED2 0x00000080L +#define MH_CLNT_AXI_ID_REUSE__MMUr_ID_MASK 0x00000700L +#define MH_CLNT_AXI_ID_REUSE__RESERVED3_MASK 0x00000800L +#define MH_CLNT_AXI_ID_REUSE__RESERVED3 0x00000800L +#define MH_CLNT_AXI_ID_REUSE__PAw_ID_MASK 0x00007000L + +// MH_INTERRUPT_MASK +#define MH_INTERRUPT_MASK__AXI_READ_ERROR_MASK 0x00000001L +#define MH_INTERRUPT_MASK__AXI_READ_ERROR 0x00000001L +#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR_MASK 0x00000002L +#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR 0x00000002L +#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT_MASK 0x00000004L +#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT 0x00000004L + +// MH_INTERRUPT_STATUS +#define MH_INTERRUPT_STATUS__AXI_READ_ERROR_MASK 0x00000001L +#define MH_INTERRUPT_STATUS__AXI_READ_ERROR 0x00000001L +#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR_MASK 0x00000002L +#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR 0x00000002L +#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT_MASK 0x00000004L +#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT 0x00000004L + +// MH_INTERRUPT_CLEAR +#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR_MASK 0x00000001L +#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR 0x00000001L +#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR_MASK 0x00000002L +#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR 0x00000002L +#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT_MASK 0x00000004L +#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT 0x00000004L + +// MH_AXI_ERROR +#define MH_AXI_ERROR__AXI_READ_ID_MASK 0x00000007L +#define MH_AXI_ERROR__AXI_READ_ERROR_MASK 0x00000008L +#define MH_AXI_ERROR__AXI_READ_ERROR 0x00000008L +#define MH_AXI_ERROR__AXI_WRITE_ID_MASK 0x00000070L +#define MH_AXI_ERROR__AXI_WRITE_ERROR_MASK 0x00000080L +#define MH_AXI_ERROR__AXI_WRITE_ERROR 0x00000080L + +// MH_PERFCOUNTER0_SELECT +#define MH_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// MH_PERFCOUNTER1_SELECT +#define MH_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL + +// MH_PERFCOUNTER0_CONFIG +#define MH_PERFCOUNTER0_CONFIG__N_VALUE_MASK 0x000000ffL + +// MH_PERFCOUNTER1_CONFIG +#define MH_PERFCOUNTER1_CONFIG__N_VALUE_MASK 0x000000ffL + +// MH_PERFCOUNTER0_LOW +#define MH_PERFCOUNTER0_LOW__PERF_COUNTER_LOW_MASK 0xffffffffL + +// MH_PERFCOUNTER1_LOW +#define MH_PERFCOUNTER1_LOW__PERF_COUNTER_LOW_MASK 0xffffffffL + +// MH_PERFCOUNTER0_HI +#define MH_PERFCOUNTER0_HI__PERF_COUNTER_HI_MASK 0x0000ffffL + +// MH_PERFCOUNTER1_HI +#define MH_PERFCOUNTER1_HI__PERF_COUNTER_HI_MASK 0x0000ffffL + +// MH_DEBUG_CTRL +#define MH_DEBUG_CTRL__INDEX_MASK 0x0000003fL + +// MH_DEBUG_DATA +#define MH_DEBUG_DATA__DATA_MASK 0xffffffffL + +// MH_AXI_HALT_CONTROL +#define MH_AXI_HALT_CONTROL__AXI_HALT_MASK 0x00000001L +#define MH_AXI_HALT_CONTROL__AXI_HALT 0x00000001L + +// MH_DEBUG_REG00 +#define MH_DEBUG_REG00__MH_BUSY_MASK 0x00000001L +#define MH_DEBUG_REG00__MH_BUSY 0x00000001L +#define MH_DEBUG_REG00__TRANS_OUTSTANDING_MASK 0x00000002L +#define MH_DEBUG_REG00__TRANS_OUTSTANDING 0x00000002L +#define MH_DEBUG_REG00__CP_REQUEST_MASK 0x00000004L +#define MH_DEBUG_REG00__CP_REQUEST 0x00000004L +#define MH_DEBUG_REG00__VGT_REQUEST_MASK 0x00000008L +#define MH_DEBUG_REG00__VGT_REQUEST 0x00000008L +#define MH_DEBUG_REG00__TC_REQUEST_MASK 0x00000010L +#define MH_DEBUG_REG00__TC_REQUEST 0x00000010L +#define MH_DEBUG_REG00__TC_CAM_EMPTY_MASK 0x00000020L +#define MH_DEBUG_REG00__TC_CAM_EMPTY 0x00000020L +#define MH_DEBUG_REG00__TC_CAM_FULL_MASK 0x00000040L +#define MH_DEBUG_REG00__TC_CAM_FULL 0x00000040L +#define MH_DEBUG_REG00__TCD_EMPTY_MASK 0x00000080L +#define MH_DEBUG_REG00__TCD_EMPTY 0x00000080L +#define MH_DEBUG_REG00__TCD_FULL_MASK 0x00000100L +#define MH_DEBUG_REG00__TCD_FULL 0x00000100L +#define MH_DEBUG_REG00__RB_REQUEST_MASK 0x00000200L +#define MH_DEBUG_REG00__RB_REQUEST 0x00000200L +#define MH_DEBUG_REG00__PA_REQUEST_MASK 0x00000400L +#define MH_DEBUG_REG00__PA_REQUEST 0x00000400L +#define MH_DEBUG_REG00__MH_CLK_EN_STATE_MASK 0x00000800L +#define MH_DEBUG_REG00__MH_CLK_EN_STATE 0x00000800L +#define MH_DEBUG_REG00__ARQ_EMPTY_MASK 0x00001000L +#define MH_DEBUG_REG00__ARQ_EMPTY 0x00001000L +#define MH_DEBUG_REG00__ARQ_FULL_MASK 0x00002000L +#define MH_DEBUG_REG00__ARQ_FULL 0x00002000L +#define MH_DEBUG_REG00__WDB_EMPTY_MASK 0x00004000L +#define MH_DEBUG_REG00__WDB_EMPTY 0x00004000L +#define MH_DEBUG_REG00__WDB_FULL_MASK 0x00008000L +#define MH_DEBUG_REG00__WDB_FULL 0x00008000L +#define MH_DEBUG_REG00__AXI_AVALID_MASK 0x00010000L +#define MH_DEBUG_REG00__AXI_AVALID 0x00010000L +#define MH_DEBUG_REG00__AXI_AREADY_MASK 0x00020000L +#define MH_DEBUG_REG00__AXI_AREADY 0x00020000L +#define MH_DEBUG_REG00__AXI_ARVALID_MASK 0x00040000L +#define MH_DEBUG_REG00__AXI_ARVALID 0x00040000L +#define MH_DEBUG_REG00__AXI_ARREADY_MASK 0x00080000L +#define MH_DEBUG_REG00__AXI_ARREADY 0x00080000L +#define MH_DEBUG_REG00__AXI_WVALID_MASK 0x00100000L +#define MH_DEBUG_REG00__AXI_WVALID 0x00100000L +#define MH_DEBUG_REG00__AXI_WREADY_MASK 0x00200000L +#define MH_DEBUG_REG00__AXI_WREADY 0x00200000L +#define MH_DEBUG_REG00__AXI_RVALID_MASK 0x00400000L +#define MH_DEBUG_REG00__AXI_RVALID 0x00400000L +#define MH_DEBUG_REG00__AXI_RREADY_MASK 0x00800000L +#define MH_DEBUG_REG00__AXI_RREADY 0x00800000L +#define MH_DEBUG_REG00__AXI_BVALID_MASK 0x01000000L +#define MH_DEBUG_REG00__AXI_BVALID 0x01000000L +#define MH_DEBUG_REG00__AXI_BREADY_MASK 0x02000000L +#define MH_DEBUG_REG00__AXI_BREADY 0x02000000L +#define MH_DEBUG_REG00__AXI_HALT_REQ_MASK 0x04000000L +#define MH_DEBUG_REG00__AXI_HALT_REQ 0x04000000L +#define MH_DEBUG_REG00__AXI_HALT_ACK_MASK 0x08000000L +#define MH_DEBUG_REG00__AXI_HALT_ACK 0x08000000L +#define MH_DEBUG_REG00__AXI_RDY_ENA_MASK 0x10000000L +#define MH_DEBUG_REG00__AXI_RDY_ENA 0x10000000L + +// MH_DEBUG_REG01 +#define MH_DEBUG_REG01__CP_SEND_q_MASK 0x00000001L +#define MH_DEBUG_REG01__CP_SEND_q 0x00000001L +#define MH_DEBUG_REG01__CP_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG01__CP_RTR_q 0x00000002L +#define MH_DEBUG_REG01__CP_WRITE_q_MASK 0x00000004L +#define MH_DEBUG_REG01__CP_WRITE_q 0x00000004L +#define MH_DEBUG_REG01__CP_TAG_q_MASK 0x00000038L +#define MH_DEBUG_REG01__CP_BLEN_q_MASK 0x00000040L +#define MH_DEBUG_REG01__CP_BLEN_q 0x00000040L +#define MH_DEBUG_REG01__VGT_SEND_q_MASK 0x00000080L +#define MH_DEBUG_REG01__VGT_SEND_q 0x00000080L +#define MH_DEBUG_REG01__VGT_RTR_q_MASK 0x00000100L +#define MH_DEBUG_REG01__VGT_RTR_q 0x00000100L +#define MH_DEBUG_REG01__VGT_TAG_q_MASK 0x00000200L +#define MH_DEBUG_REG01__VGT_TAG_q 0x00000200L +#define MH_DEBUG_REG01__TC_SEND_q_MASK 0x00000400L +#define MH_DEBUG_REG01__TC_SEND_q 0x00000400L +#define MH_DEBUG_REG01__TC_RTR_q_MASK 0x00000800L +#define MH_DEBUG_REG01__TC_RTR_q 0x00000800L +#define MH_DEBUG_REG01__TC_BLEN_q_MASK 0x00001000L +#define MH_DEBUG_REG01__TC_BLEN_q 0x00001000L +#define MH_DEBUG_REG01__TC_ROQ_SEND_q_MASK 0x00002000L +#define MH_DEBUG_REG01__TC_ROQ_SEND_q 0x00002000L +#define MH_DEBUG_REG01__TC_ROQ_RTR_q_MASK 0x00004000L +#define MH_DEBUG_REG01__TC_ROQ_RTR_q 0x00004000L +#define MH_DEBUG_REG01__TC_MH_written_MASK 0x00008000L +#define MH_DEBUG_REG01__TC_MH_written 0x00008000L +#define MH_DEBUG_REG01__RB_SEND_q_MASK 0x00010000L +#define MH_DEBUG_REG01__RB_SEND_q 0x00010000L +#define MH_DEBUG_REG01__RB_RTR_q_MASK 0x00020000L +#define MH_DEBUG_REG01__RB_RTR_q 0x00020000L +#define MH_DEBUG_REG01__PA_SEND_q_MASK 0x00040000L +#define MH_DEBUG_REG01__PA_SEND_q 0x00040000L +#define MH_DEBUG_REG01__PA_RTR_q_MASK 0x00080000L +#define MH_DEBUG_REG01__PA_RTR_q 0x00080000L + +// MH_DEBUG_REG02 +#define MH_DEBUG_REG02__MH_CP_grb_send_MASK 0x00000001L +#define MH_DEBUG_REG02__MH_CP_grb_send 0x00000001L +#define MH_DEBUG_REG02__MH_VGT_grb_send_MASK 0x00000002L +#define MH_DEBUG_REG02__MH_VGT_grb_send 0x00000002L +#define MH_DEBUG_REG02__MH_TC_mcsend_MASK 0x00000004L +#define MH_DEBUG_REG02__MH_TC_mcsend 0x00000004L +#define MH_DEBUG_REG02__MH_CLNT_rlast_MASK 0x00000008L +#define MH_DEBUG_REG02__MH_CLNT_rlast 0x00000008L +#define MH_DEBUG_REG02__MH_CLNT_tag_MASK 0x00000070L +#define MH_DEBUG_REG02__RDC_RID_MASK 0x00000380L +#define MH_DEBUG_REG02__RDC_RRESP_MASK 0x00000c00L +#define MH_DEBUG_REG02__MH_CP_writeclean_MASK 0x00001000L +#define MH_DEBUG_REG02__MH_CP_writeclean 0x00001000L +#define MH_DEBUG_REG02__MH_RB_writeclean_MASK 0x00002000L +#define MH_DEBUG_REG02__MH_RB_writeclean 0x00002000L +#define MH_DEBUG_REG02__MH_PA_writeclean_MASK 0x00004000L +#define MH_DEBUG_REG02__MH_PA_writeclean 0x00004000L +#define MH_DEBUG_REG02__BRC_BID_MASK 0x00038000L +#define MH_DEBUG_REG02__BRC_BRESP_MASK 0x000c0000L + +// MH_DEBUG_REG03 +#define MH_DEBUG_REG03__MH_CLNT_data_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG04 +#define MH_DEBUG_REG04__MH_CLNT_data_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG05 +#define MH_DEBUG_REG05__CP_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG05__CP_MH_send 0x00000001L +#define MH_DEBUG_REG05__CP_MH_write_MASK 0x00000002L +#define MH_DEBUG_REG05__CP_MH_write 0x00000002L +#define MH_DEBUG_REG05__CP_MH_tag_MASK 0x0000001cL +#define MH_DEBUG_REG05__CP_MH_ad_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG06 +#define MH_DEBUG_REG06__CP_MH_data_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG07 +#define MH_DEBUG_REG07__CP_MH_data_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG08 +#define MH_DEBUG_REG08__CP_MH_be_MASK 0x000000ffL +#define MH_DEBUG_REG08__RB_MH_be_MASK 0x0000ff00L +#define MH_DEBUG_REG08__PA_MH_be_MASK 0x00ff0000L + +// MH_DEBUG_REG09 +#define MH_DEBUG_REG09__ALWAYS_ZERO_MASK 0x00000007L +#define MH_DEBUG_REG09__VGT_MH_send_MASK 0x00000008L +#define MH_DEBUG_REG09__VGT_MH_send 0x00000008L +#define MH_DEBUG_REG09__VGT_MH_tagbe_MASK 0x00000010L +#define MH_DEBUG_REG09__VGT_MH_tagbe 0x00000010L +#define MH_DEBUG_REG09__VGT_MH_ad_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG10 +#define MH_DEBUG_REG10__ALWAYS_ZERO_MASK 0x00000003L +#define MH_DEBUG_REG10__TC_MH_send_MASK 0x00000004L +#define MH_DEBUG_REG10__TC_MH_send 0x00000004L +#define MH_DEBUG_REG10__TC_MH_mask_MASK 0x00000018L +#define MH_DEBUG_REG10__TC_MH_addr_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG11 +#define MH_DEBUG_REG11__TC_MH_info_MASK 0x01ffffffL +#define MH_DEBUG_REG11__TC_MH_send_MASK 0x02000000L +#define MH_DEBUG_REG11__TC_MH_send 0x02000000L + +// MH_DEBUG_REG12 +#define MH_DEBUG_REG12__MH_TC_mcinfo_MASK 0x01ffffffL +#define MH_DEBUG_REG12__MH_TC_mcinfo_send_MASK 0x02000000L +#define MH_DEBUG_REG12__MH_TC_mcinfo_send 0x02000000L +#define MH_DEBUG_REG12__TC_MH_written_MASK 0x04000000L +#define MH_DEBUG_REG12__TC_MH_written 0x04000000L + +// MH_DEBUG_REG13 +#define MH_DEBUG_REG13__ALWAYS_ZERO_MASK 0x00000003L +#define MH_DEBUG_REG13__TC_ROQ_SEND_MASK 0x00000004L +#define MH_DEBUG_REG13__TC_ROQ_SEND 0x00000004L +#define MH_DEBUG_REG13__TC_ROQ_MASK_MASK 0x00000018L +#define MH_DEBUG_REG13__TC_ROQ_ADDR_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG14 +#define MH_DEBUG_REG14__TC_ROQ_INFO_MASK 0x01ffffffL +#define MH_DEBUG_REG14__TC_ROQ_SEND_MASK 0x02000000L +#define MH_DEBUG_REG14__TC_ROQ_SEND 0x02000000L + +// MH_DEBUG_REG15 +#define MH_DEBUG_REG15__ALWAYS_ZERO_MASK 0x0000000fL +#define MH_DEBUG_REG15__RB_MH_send_MASK 0x00000010L +#define MH_DEBUG_REG15__RB_MH_send 0x00000010L +#define MH_DEBUG_REG15__RB_MH_addr_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG16 +#define MH_DEBUG_REG16__RB_MH_data_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG17 +#define MH_DEBUG_REG17__RB_MH_data_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG18 +#define MH_DEBUG_REG18__ALWAYS_ZERO_MASK 0x0000000fL +#define MH_DEBUG_REG18__PA_MH_send_MASK 0x00000010L +#define MH_DEBUG_REG18__PA_MH_send 0x00000010L +#define MH_DEBUG_REG18__PA_MH_addr_31_5_MASK 0xffffffe0L + +// MH_DEBUG_REG19 +#define MH_DEBUG_REG19__PA_MH_data_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG20 +#define MH_DEBUG_REG20__PA_MH_data_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG21 +#define MH_DEBUG_REG21__AVALID_q_MASK 0x00000001L +#define MH_DEBUG_REG21__AVALID_q 0x00000001L +#define MH_DEBUG_REG21__AREADY_q_MASK 0x00000002L +#define MH_DEBUG_REG21__AREADY_q 0x00000002L +#define MH_DEBUG_REG21__AID_q_MASK 0x0000001cL +#define MH_DEBUG_REG21__ALEN_q_2_0_MASK 0x000000e0L +#define MH_DEBUG_REG21__ARVALID_q_MASK 0x00000100L +#define MH_DEBUG_REG21__ARVALID_q 0x00000100L +#define MH_DEBUG_REG21__ARREADY_q_MASK 0x00000200L +#define MH_DEBUG_REG21__ARREADY_q 0x00000200L +#define MH_DEBUG_REG21__ARID_q_MASK 0x00001c00L +#define MH_DEBUG_REG21__ARLEN_q_1_0_MASK 0x00006000L +#define MH_DEBUG_REG21__RVALID_q_MASK 0x00008000L +#define MH_DEBUG_REG21__RVALID_q 0x00008000L +#define MH_DEBUG_REG21__RREADY_q_MASK 0x00010000L +#define MH_DEBUG_REG21__RREADY_q 0x00010000L +#define MH_DEBUG_REG21__RLAST_q_MASK 0x00020000L +#define MH_DEBUG_REG21__RLAST_q 0x00020000L +#define MH_DEBUG_REG21__RID_q_MASK 0x001c0000L +#define MH_DEBUG_REG21__WVALID_q_MASK 0x00200000L +#define MH_DEBUG_REG21__WVALID_q 0x00200000L +#define MH_DEBUG_REG21__WREADY_q_MASK 0x00400000L +#define MH_DEBUG_REG21__WREADY_q 0x00400000L +#define MH_DEBUG_REG21__WLAST_q_MASK 0x00800000L +#define MH_DEBUG_REG21__WLAST_q 0x00800000L +#define MH_DEBUG_REG21__WID_q_MASK 0x07000000L +#define MH_DEBUG_REG21__BVALID_q_MASK 0x08000000L +#define MH_DEBUG_REG21__BVALID_q 0x08000000L +#define MH_DEBUG_REG21__BREADY_q_MASK 0x10000000L +#define MH_DEBUG_REG21__BREADY_q 0x10000000L +#define MH_DEBUG_REG21__BID_q_MASK 0xe0000000L + +// MH_DEBUG_REG22 +#define MH_DEBUG_REG22__AVALID_q_MASK 0x00000001L +#define MH_DEBUG_REG22__AVALID_q 0x00000001L +#define MH_DEBUG_REG22__AREADY_q_MASK 0x00000002L +#define MH_DEBUG_REG22__AREADY_q 0x00000002L +#define MH_DEBUG_REG22__AID_q_MASK 0x0000001cL +#define MH_DEBUG_REG22__ALEN_q_1_0_MASK 0x00000060L +#define MH_DEBUG_REG22__ARVALID_q_MASK 0x00000080L +#define MH_DEBUG_REG22__ARVALID_q 0x00000080L +#define MH_DEBUG_REG22__ARREADY_q_MASK 0x00000100L +#define MH_DEBUG_REG22__ARREADY_q 0x00000100L +#define MH_DEBUG_REG22__ARID_q_MASK 0x00000e00L +#define MH_DEBUG_REG22__ARLEN_q_1_1_MASK 0x00001000L +#define MH_DEBUG_REG22__ARLEN_q_1_1 0x00001000L +#define MH_DEBUG_REG22__WVALID_q_MASK 0x00002000L +#define MH_DEBUG_REG22__WVALID_q 0x00002000L +#define MH_DEBUG_REG22__WREADY_q_MASK 0x00004000L +#define MH_DEBUG_REG22__WREADY_q 0x00004000L +#define MH_DEBUG_REG22__WLAST_q_MASK 0x00008000L +#define MH_DEBUG_REG22__WLAST_q 0x00008000L +#define MH_DEBUG_REG22__WID_q_MASK 0x00070000L +#define MH_DEBUG_REG22__WSTRB_q_MASK 0x07f80000L +#define MH_DEBUG_REG22__BVALID_q_MASK 0x08000000L +#define MH_DEBUG_REG22__BVALID_q 0x08000000L +#define MH_DEBUG_REG22__BREADY_q_MASK 0x10000000L +#define MH_DEBUG_REG22__BREADY_q 0x10000000L +#define MH_DEBUG_REG22__BID_q_MASK 0xe0000000L + +// MH_DEBUG_REG23 +#define MH_DEBUG_REG23__ARC_CTRL_RE_q_MASK 0x00000001L +#define MH_DEBUG_REG23__ARC_CTRL_RE_q 0x00000001L +#define MH_DEBUG_REG23__CTRL_ARC_ID_MASK 0x0000000eL +#define MH_DEBUG_REG23__CTRL_ARC_PAD_MASK 0xfffffff0L + +// MH_DEBUG_REG24 +#define MH_DEBUG_REG24__ALWAYS_ZERO_MASK 0x00000003L +#define MH_DEBUG_REG24__REG_A_MASK 0x0000fffcL +#define MH_DEBUG_REG24__REG_RE_MASK 0x00010000L +#define MH_DEBUG_REG24__REG_RE 0x00010000L +#define MH_DEBUG_REG24__REG_WE_MASK 0x00020000L +#define MH_DEBUG_REG24__REG_WE 0x00020000L +#define MH_DEBUG_REG24__BLOCK_RS_MASK 0x00040000L +#define MH_DEBUG_REG24__BLOCK_RS 0x00040000L + +// MH_DEBUG_REG25 +#define MH_DEBUG_REG25__REG_WD_MASK 0xffffffffL + +// MH_DEBUG_REG26 +#define MH_DEBUG_REG26__MH_RBBM_busy_MASK 0x00000001L +#define MH_DEBUG_REG26__MH_RBBM_busy 0x00000001L +#define MH_DEBUG_REG26__MH_CIB_mh_clk_en_int_MASK 0x00000002L +#define MH_DEBUG_REG26__MH_CIB_mh_clk_en_int 0x00000002L +#define MH_DEBUG_REG26__MH_CIB_mmu_clk_en_int_MASK 0x00000004L +#define MH_DEBUG_REG26__MH_CIB_mmu_clk_en_int 0x00000004L +#define MH_DEBUG_REG26__MH_CIB_tcroq_clk_en_int_MASK 0x00000008L +#define MH_DEBUG_REG26__MH_CIB_tcroq_clk_en_int 0x00000008L +#define MH_DEBUG_REG26__GAT_CLK_ENA_MASK 0x00000010L +#define MH_DEBUG_REG26__GAT_CLK_ENA 0x00000010L +#define MH_DEBUG_REG26__RBBM_MH_clk_en_override_MASK 0x00000020L +#define MH_DEBUG_REG26__RBBM_MH_clk_en_override 0x00000020L +#define MH_DEBUG_REG26__CNT_q_MASK 0x00000fc0L +#define MH_DEBUG_REG26__TCD_EMPTY_q_MASK 0x00001000L +#define MH_DEBUG_REG26__TCD_EMPTY_q 0x00001000L +#define MH_DEBUG_REG26__TC_ROQ_EMPTY_MASK 0x00002000L +#define MH_DEBUG_REG26__TC_ROQ_EMPTY 0x00002000L +#define MH_DEBUG_REG26__MH_BUSY_d_MASK 0x00004000L +#define MH_DEBUG_REG26__MH_BUSY_d 0x00004000L +#define MH_DEBUG_REG26__ANY_CLNT_BUSY_MASK 0x00008000L +#define MH_DEBUG_REG26__ANY_CLNT_BUSY 0x00008000L +#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00010000L +#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_ALL 0x00010000L +#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_TC_MASK 0x00020000L +#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_TC 0x00020000L +#define MH_DEBUG_REG26__CP_SEND_q_MASK 0x00040000L +#define MH_DEBUG_REG26__CP_SEND_q 0x00040000L +#define MH_DEBUG_REG26__CP_RTR_q_MASK 0x00080000L +#define MH_DEBUG_REG26__CP_RTR_q 0x00080000L +#define MH_DEBUG_REG26__VGT_SEND_q_MASK 0x00100000L +#define MH_DEBUG_REG26__VGT_SEND_q 0x00100000L +#define MH_DEBUG_REG26__VGT_RTR_q_MASK 0x00200000L +#define MH_DEBUG_REG26__VGT_RTR_q 0x00200000L +#define MH_DEBUG_REG26__TC_ROQ_SEND_q_MASK 0x00400000L +#define MH_DEBUG_REG26__TC_ROQ_SEND_q 0x00400000L +#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q_MASK 0x00800000L +#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q 0x00800000L +#define MH_DEBUG_REG26__RB_SEND_q_MASK 0x01000000L +#define MH_DEBUG_REG26__RB_SEND_q 0x01000000L +#define MH_DEBUG_REG26__RB_RTR_q_MASK 0x02000000L +#define MH_DEBUG_REG26__RB_RTR_q 0x02000000L +#define MH_DEBUG_REG26__PA_SEND_q_MASK 0x04000000L +#define MH_DEBUG_REG26__PA_SEND_q 0x04000000L +#define MH_DEBUG_REG26__PA_RTR_q_MASK 0x08000000L +#define MH_DEBUG_REG26__PA_RTR_q 0x08000000L +#define MH_DEBUG_REG26__RDC_VALID_MASK 0x10000000L +#define MH_DEBUG_REG26__RDC_VALID 0x10000000L +#define MH_DEBUG_REG26__RDC_RLAST_MASK 0x20000000L +#define MH_DEBUG_REG26__RDC_RLAST 0x20000000L +#define MH_DEBUG_REG26__TLBMISS_VALID_MASK 0x40000000L +#define MH_DEBUG_REG26__TLBMISS_VALID 0x40000000L +#define MH_DEBUG_REG26__BRC_VALID_MASK 0x80000000L +#define MH_DEBUG_REG26__BRC_VALID 0x80000000L + +// MH_DEBUG_REG27 +#define MH_DEBUG_REG27__EFF2_FP_WINNER_MASK 0x00000007L +#define MH_DEBUG_REG27__EFF2_LRU_WINNER_out_MASK 0x00000038L +#define MH_DEBUG_REG27__EFF1_WINNER_MASK 0x000001c0L +#define MH_DEBUG_REG27__ARB_WINNER_MASK 0x00000e00L +#define MH_DEBUG_REG27__ARB_WINNER_q_MASK 0x00007000L +#define MH_DEBUG_REG27__EFF1_WIN_MASK 0x00008000L +#define MH_DEBUG_REG27__EFF1_WIN 0x00008000L +#define MH_DEBUG_REG27__KILL_EFF1_MASK 0x00010000L +#define MH_DEBUG_REG27__KILL_EFF1 0x00010000L +#define MH_DEBUG_REG27__ARB_HOLD_MASK 0x00020000L +#define MH_DEBUG_REG27__ARB_HOLD 0x00020000L +#define MH_DEBUG_REG27__ARB_RTR_q_MASK 0x00040000L +#define MH_DEBUG_REG27__ARB_RTR_q 0x00040000L +#define MH_DEBUG_REG27__CP_SEND_QUAL_MASK 0x00080000L +#define MH_DEBUG_REG27__CP_SEND_QUAL 0x00080000L +#define MH_DEBUG_REG27__VGT_SEND_QUAL_MASK 0x00100000L +#define MH_DEBUG_REG27__VGT_SEND_QUAL 0x00100000L +#define MH_DEBUG_REG27__TC_SEND_QUAL_MASK 0x00200000L +#define MH_DEBUG_REG27__TC_SEND_QUAL 0x00200000L +#define MH_DEBUG_REG27__TC_SEND_EFF1_QUAL_MASK 0x00400000L +#define MH_DEBUG_REG27__TC_SEND_EFF1_QUAL 0x00400000L +#define MH_DEBUG_REG27__RB_SEND_QUAL_MASK 0x00800000L +#define MH_DEBUG_REG27__RB_SEND_QUAL 0x00800000L +#define MH_DEBUG_REG27__PA_SEND_QUAL_MASK 0x01000000L +#define MH_DEBUG_REG27__PA_SEND_QUAL 0x01000000L +#define MH_DEBUG_REG27__ARB_QUAL_MASK 0x02000000L +#define MH_DEBUG_REG27__ARB_QUAL 0x02000000L +#define MH_DEBUG_REG27__CP_EFF1_REQ_MASK 0x04000000L +#define MH_DEBUG_REG27__CP_EFF1_REQ 0x04000000L +#define MH_DEBUG_REG27__VGT_EFF1_REQ_MASK 0x08000000L +#define MH_DEBUG_REG27__VGT_EFF1_REQ 0x08000000L +#define MH_DEBUG_REG27__TC_EFF1_REQ_MASK 0x10000000L +#define MH_DEBUG_REG27__TC_EFF1_REQ 0x10000000L +#define MH_DEBUG_REG27__RB_EFF1_REQ_MASK 0x20000000L +#define MH_DEBUG_REG27__RB_EFF1_REQ 0x20000000L +#define MH_DEBUG_REG27__TCD_NEARFULL_q_MASK 0x40000000L +#define MH_DEBUG_REG27__TCD_NEARFULL_q 0x40000000L +#define MH_DEBUG_REG27__TCHOLD_IP_q_MASK 0x80000000L +#define MH_DEBUG_REG27__TCHOLD_IP_q 0x80000000L + +// MH_DEBUG_REG28 +#define MH_DEBUG_REG28__EFF1_WINNER_MASK 0x00000007L +#define MH_DEBUG_REG28__ARB_WINNER_MASK 0x00000038L +#define MH_DEBUG_REG28__CP_SEND_QUAL_MASK 0x00000040L +#define MH_DEBUG_REG28__CP_SEND_QUAL 0x00000040L +#define MH_DEBUG_REG28__VGT_SEND_QUAL_MASK 0x00000080L +#define MH_DEBUG_REG28__VGT_SEND_QUAL 0x00000080L +#define MH_DEBUG_REG28__TC_SEND_QUAL_MASK 0x00000100L +#define MH_DEBUG_REG28__TC_SEND_QUAL 0x00000100L +#define MH_DEBUG_REG28__TC_SEND_EFF1_QUAL_MASK 0x00000200L +#define MH_DEBUG_REG28__TC_SEND_EFF1_QUAL 0x00000200L +#define MH_DEBUG_REG28__RB_SEND_QUAL_MASK 0x00000400L +#define MH_DEBUG_REG28__RB_SEND_QUAL 0x00000400L +#define MH_DEBUG_REG28__ARB_QUAL_MASK 0x00000800L +#define MH_DEBUG_REG28__ARB_QUAL 0x00000800L +#define MH_DEBUG_REG28__CP_EFF1_REQ_MASK 0x00001000L +#define MH_DEBUG_REG28__CP_EFF1_REQ 0x00001000L +#define MH_DEBUG_REG28__VGT_EFF1_REQ_MASK 0x00002000L +#define MH_DEBUG_REG28__VGT_EFF1_REQ 0x00002000L +#define MH_DEBUG_REG28__TC_EFF1_REQ_MASK 0x00004000L +#define MH_DEBUG_REG28__TC_EFF1_REQ 0x00004000L +#define MH_DEBUG_REG28__RB_EFF1_REQ_MASK 0x00008000L +#define MH_DEBUG_REG28__RB_EFF1_REQ 0x00008000L +#define MH_DEBUG_REG28__EFF1_WIN_MASK 0x00010000L +#define MH_DEBUG_REG28__EFF1_WIN 0x00010000L +#define MH_DEBUG_REG28__KILL_EFF1_MASK 0x00020000L +#define MH_DEBUG_REG28__KILL_EFF1 0x00020000L +#define MH_DEBUG_REG28__TCD_NEARFULL_q_MASK 0x00040000L +#define MH_DEBUG_REG28__TCD_NEARFULL_q 0x00040000L +#define MH_DEBUG_REG28__TC_ARB_HOLD_MASK 0x00080000L +#define MH_DEBUG_REG28__TC_ARB_HOLD 0x00080000L +#define MH_DEBUG_REG28__ARB_HOLD_MASK 0x00100000L +#define MH_DEBUG_REG28__ARB_HOLD 0x00100000L +#define MH_DEBUG_REG28__ARB_RTR_q_MASK 0x00200000L +#define MH_DEBUG_REG28__ARB_RTR_q 0x00200000L +#define MH_DEBUG_REG28__SAME_PAGE_LIMIT_COUNT_q_MASK 0xffc00000L + +// MH_DEBUG_REG29 +#define MH_DEBUG_REG29__EFF2_LRU_WINNER_out_MASK 0x00000007L +#define MH_DEBUG_REG29__LEAST_RECENT_INDEX_d_MASK 0x00000038L +#define MH_DEBUG_REG29__LEAST_RECENT_d_MASK 0x000001c0L +#define MH_DEBUG_REG29__UPDATE_RECENT_STACK_d_MASK 0x00000200L +#define MH_DEBUG_REG29__UPDATE_RECENT_STACK_d 0x00000200L +#define MH_DEBUG_REG29__ARB_HOLD_MASK 0x00000400L +#define MH_DEBUG_REG29__ARB_HOLD 0x00000400L +#define MH_DEBUG_REG29__ARB_RTR_q_MASK 0x00000800L +#define MH_DEBUG_REG29__ARB_RTR_q 0x00000800L +#define MH_DEBUG_REG29__CLNT_REQ_MASK 0x0001f000L +#define MH_DEBUG_REG29__RECENT_d_0_MASK 0x000e0000L +#define MH_DEBUG_REG29__RECENT_d_1_MASK 0x00700000L +#define MH_DEBUG_REG29__RECENT_d_2_MASK 0x03800000L +#define MH_DEBUG_REG29__RECENT_d_3_MASK 0x1c000000L +#define MH_DEBUG_REG29__RECENT_d_4_MASK 0xe0000000L + +// MH_DEBUG_REG30 +#define MH_DEBUG_REG30__TC_ARB_HOLD_MASK 0x00000001L +#define MH_DEBUG_REG30__TC_ARB_HOLD 0x00000001L +#define MH_DEBUG_REG30__TC_NOROQ_SAME_ROW_BANK_MASK 0x00000002L +#define MH_DEBUG_REG30__TC_NOROQ_SAME_ROW_BANK 0x00000002L +#define MH_DEBUG_REG30__TC_ROQ_SAME_ROW_BANK_MASK 0x00000004L +#define MH_DEBUG_REG30__TC_ROQ_SAME_ROW_BANK 0x00000004L +#define MH_DEBUG_REG30__TCD_NEARFULL_q_MASK 0x00000008L +#define MH_DEBUG_REG30__TCD_NEARFULL_q 0x00000008L +#define MH_DEBUG_REG30__TCHOLD_IP_q_MASK 0x00000010L +#define MH_DEBUG_REG30__TCHOLD_IP_q 0x00000010L +#define MH_DEBUG_REG30__TCHOLD_CNT_q_MASK 0x000000e0L +#define MH_DEBUG_REG30__MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00000100L +#define MH_DEBUG_REG30__MH_ARBITER_CONFIG_TC_REORDER_ENABLE 0x00000100L +#define MH_DEBUG_REG30__TC_ROQ_RTR_DBG_q_MASK 0x00000200L +#define MH_DEBUG_REG30__TC_ROQ_RTR_DBG_q 0x00000200L +#define MH_DEBUG_REG30__TC_ROQ_SEND_q_MASK 0x00000400L +#define MH_DEBUG_REG30__TC_ROQ_SEND_q 0x00000400L +#define MH_DEBUG_REG30__TC_MH_written_MASK 0x00000800L +#define MH_DEBUG_REG30__TC_MH_written 0x00000800L +#define MH_DEBUG_REG30__TCD_FULLNESS_CNT_q_MASK 0x0007f000L +#define MH_DEBUG_REG30__WBURST_ACTIVE_MASK 0x00080000L +#define MH_DEBUG_REG30__WBURST_ACTIVE 0x00080000L +#define MH_DEBUG_REG30__WLAST_q_MASK 0x00100000L +#define MH_DEBUG_REG30__WLAST_q 0x00100000L +#define MH_DEBUG_REG30__WBURST_IP_q_MASK 0x00200000L +#define MH_DEBUG_REG30__WBURST_IP_q 0x00200000L +#define MH_DEBUG_REG30__WBURST_CNT_q_MASK 0x01c00000L +#define MH_DEBUG_REG30__CP_SEND_QUAL_MASK 0x02000000L +#define MH_DEBUG_REG30__CP_SEND_QUAL 0x02000000L +#define MH_DEBUG_REG30__CP_MH_write_MASK 0x04000000L +#define MH_DEBUG_REG30__CP_MH_write 0x04000000L +#define MH_DEBUG_REG30__RB_SEND_QUAL_MASK 0x08000000L +#define MH_DEBUG_REG30__RB_SEND_QUAL 0x08000000L +#define MH_DEBUG_REG30__PA_SEND_QUAL_MASK 0x10000000L +#define MH_DEBUG_REG30__PA_SEND_QUAL 0x10000000L +#define MH_DEBUG_REG30__ARB_WINNER_MASK 0xe0000000L + +// MH_DEBUG_REG31 +#define MH_DEBUG_REG31__RF_ARBITER_CONFIG_q_MASK 0x03ffffffL +#define MH_DEBUG_REG31__MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x1c000000L + +// MH_DEBUG_REG32 +#define MH_DEBUG_REG32__SAME_ROW_BANK_q_MASK 0x000000ffL +#define MH_DEBUG_REG32__ROQ_MARK_q_MASK 0x0000ff00L +#define MH_DEBUG_REG32__ROQ_VALID_q_MASK 0x00ff0000L +#define MH_DEBUG_REG32__TC_MH_send_MASK 0x01000000L +#define MH_DEBUG_REG32__TC_MH_send 0x01000000L +#define MH_DEBUG_REG32__TC_ROQ_RTR_q_MASK 0x02000000L +#define MH_DEBUG_REG32__TC_ROQ_RTR_q 0x02000000L +#define MH_DEBUG_REG32__KILL_EFF1_MASK 0x04000000L +#define MH_DEBUG_REG32__KILL_EFF1 0x04000000L +#define MH_DEBUG_REG32__TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000L +#define MH_DEBUG_REG32__TC_ROQ_SAME_ROW_BANK_SEL 0x08000000L +#define MH_DEBUG_REG32__ANY_SAME_ROW_BANK_MASK 0x10000000L +#define MH_DEBUG_REG32__ANY_SAME_ROW_BANK 0x10000000L +#define MH_DEBUG_REG32__TC_EFF1_QUAL_MASK 0x20000000L +#define MH_DEBUG_REG32__TC_EFF1_QUAL 0x20000000L +#define MH_DEBUG_REG32__TC_ROQ_EMPTY_MASK 0x40000000L +#define MH_DEBUG_REG32__TC_ROQ_EMPTY 0x40000000L +#define MH_DEBUG_REG32__TC_ROQ_FULL_MASK 0x80000000L +#define MH_DEBUG_REG32__TC_ROQ_FULL 0x80000000L + +// MH_DEBUG_REG33 +#define MH_DEBUG_REG33__SAME_ROW_BANK_q_MASK 0x000000ffL +#define MH_DEBUG_REG33__ROQ_MARK_d_MASK 0x0000ff00L +#define MH_DEBUG_REG33__ROQ_VALID_d_MASK 0x00ff0000L +#define MH_DEBUG_REG33__TC_MH_send_MASK 0x01000000L +#define MH_DEBUG_REG33__TC_MH_send 0x01000000L +#define MH_DEBUG_REG33__TC_ROQ_RTR_q_MASK 0x02000000L +#define MH_DEBUG_REG33__TC_ROQ_RTR_q 0x02000000L +#define MH_DEBUG_REG33__KILL_EFF1_MASK 0x04000000L +#define MH_DEBUG_REG33__KILL_EFF1 0x04000000L +#define MH_DEBUG_REG33__TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000L +#define MH_DEBUG_REG33__TC_ROQ_SAME_ROW_BANK_SEL 0x08000000L +#define MH_DEBUG_REG33__ANY_SAME_ROW_BANK_MASK 0x10000000L +#define MH_DEBUG_REG33__ANY_SAME_ROW_BANK 0x10000000L +#define MH_DEBUG_REG33__TC_EFF1_QUAL_MASK 0x20000000L +#define MH_DEBUG_REG33__TC_EFF1_QUAL 0x20000000L +#define MH_DEBUG_REG33__TC_ROQ_EMPTY_MASK 0x40000000L +#define MH_DEBUG_REG33__TC_ROQ_EMPTY 0x40000000L +#define MH_DEBUG_REG33__TC_ROQ_FULL_MASK 0x80000000L +#define MH_DEBUG_REG33__TC_ROQ_FULL 0x80000000L + +// MH_DEBUG_REG34 +#define MH_DEBUG_REG34__SAME_ROW_BANK_WIN_MASK 0x000000ffL +#define MH_DEBUG_REG34__SAME_ROW_BANK_REQ_MASK 0x0000ff00L +#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_WIN_MASK 0x00ff0000L +#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_REQ_MASK 0xff000000L + +// MH_DEBUG_REG35 +#define MH_DEBUG_REG35__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG35__TC_MH_send 0x00000001L +#define MH_DEBUG_REG35__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG35__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG35__ROQ_MARK_q_0_MASK 0x00000004L +#define MH_DEBUG_REG35__ROQ_MARK_q_0 0x00000004L +#define MH_DEBUG_REG35__ROQ_VALID_q_0_MASK 0x00000008L +#define MH_DEBUG_REG35__ROQ_VALID_q_0 0x00000008L +#define MH_DEBUG_REG35__SAME_ROW_BANK_q_0_MASK 0x00000010L +#define MH_DEBUG_REG35__SAME_ROW_BANK_q_0 0x00000010L +#define MH_DEBUG_REG35__ROQ_ADDR_0_MASK 0xffffffe0L + +// MH_DEBUG_REG36 +#define MH_DEBUG_REG36__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG36__TC_MH_send 0x00000001L +#define MH_DEBUG_REG36__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG36__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG36__ROQ_MARK_q_1_MASK 0x00000004L +#define MH_DEBUG_REG36__ROQ_MARK_q_1 0x00000004L +#define MH_DEBUG_REG36__ROQ_VALID_q_1_MASK 0x00000008L +#define MH_DEBUG_REG36__ROQ_VALID_q_1 0x00000008L +#define MH_DEBUG_REG36__SAME_ROW_BANK_q_1_MASK 0x00000010L +#define MH_DEBUG_REG36__SAME_ROW_BANK_q_1 0x00000010L +#define MH_DEBUG_REG36__ROQ_ADDR_1_MASK 0xffffffe0L + +// MH_DEBUG_REG37 +#define MH_DEBUG_REG37__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG37__TC_MH_send 0x00000001L +#define MH_DEBUG_REG37__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG37__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG37__ROQ_MARK_q_2_MASK 0x00000004L +#define MH_DEBUG_REG37__ROQ_MARK_q_2 0x00000004L +#define MH_DEBUG_REG37__ROQ_VALID_q_2_MASK 0x00000008L +#define MH_DEBUG_REG37__ROQ_VALID_q_2 0x00000008L +#define MH_DEBUG_REG37__SAME_ROW_BANK_q_2_MASK 0x00000010L +#define MH_DEBUG_REG37__SAME_ROW_BANK_q_2 0x00000010L +#define MH_DEBUG_REG37__ROQ_ADDR_2_MASK 0xffffffe0L + +// MH_DEBUG_REG38 +#define MH_DEBUG_REG38__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG38__TC_MH_send 0x00000001L +#define MH_DEBUG_REG38__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG38__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG38__ROQ_MARK_q_3_MASK 0x00000004L +#define MH_DEBUG_REG38__ROQ_MARK_q_3 0x00000004L +#define MH_DEBUG_REG38__ROQ_VALID_q_3_MASK 0x00000008L +#define MH_DEBUG_REG38__ROQ_VALID_q_3 0x00000008L +#define MH_DEBUG_REG38__SAME_ROW_BANK_q_3_MASK 0x00000010L +#define MH_DEBUG_REG38__SAME_ROW_BANK_q_3 0x00000010L +#define MH_DEBUG_REG38__ROQ_ADDR_3_MASK 0xffffffe0L + +// MH_DEBUG_REG39 +#define MH_DEBUG_REG39__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG39__TC_MH_send 0x00000001L +#define MH_DEBUG_REG39__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG39__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG39__ROQ_MARK_q_4_MASK 0x00000004L +#define MH_DEBUG_REG39__ROQ_MARK_q_4 0x00000004L +#define MH_DEBUG_REG39__ROQ_VALID_q_4_MASK 0x00000008L +#define MH_DEBUG_REG39__ROQ_VALID_q_4 0x00000008L +#define MH_DEBUG_REG39__SAME_ROW_BANK_q_4_MASK 0x00000010L +#define MH_DEBUG_REG39__SAME_ROW_BANK_q_4 0x00000010L +#define MH_DEBUG_REG39__ROQ_ADDR_4_MASK 0xffffffe0L + +// MH_DEBUG_REG40 +#define MH_DEBUG_REG40__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG40__TC_MH_send 0x00000001L +#define MH_DEBUG_REG40__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG40__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG40__ROQ_MARK_q_5_MASK 0x00000004L +#define MH_DEBUG_REG40__ROQ_MARK_q_5 0x00000004L +#define MH_DEBUG_REG40__ROQ_VALID_q_5_MASK 0x00000008L +#define MH_DEBUG_REG40__ROQ_VALID_q_5 0x00000008L +#define MH_DEBUG_REG40__SAME_ROW_BANK_q_5_MASK 0x00000010L +#define MH_DEBUG_REG40__SAME_ROW_BANK_q_5 0x00000010L +#define MH_DEBUG_REG40__ROQ_ADDR_5_MASK 0xffffffe0L + +// MH_DEBUG_REG41 +#define MH_DEBUG_REG41__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG41__TC_MH_send 0x00000001L +#define MH_DEBUG_REG41__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG41__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG41__ROQ_MARK_q_6_MASK 0x00000004L +#define MH_DEBUG_REG41__ROQ_MARK_q_6 0x00000004L +#define MH_DEBUG_REG41__ROQ_VALID_q_6_MASK 0x00000008L +#define MH_DEBUG_REG41__ROQ_VALID_q_6 0x00000008L +#define MH_DEBUG_REG41__SAME_ROW_BANK_q_6_MASK 0x00000010L +#define MH_DEBUG_REG41__SAME_ROW_BANK_q_6 0x00000010L +#define MH_DEBUG_REG41__ROQ_ADDR_6_MASK 0xffffffe0L + +// MH_DEBUG_REG42 +#define MH_DEBUG_REG42__TC_MH_send_MASK 0x00000001L +#define MH_DEBUG_REG42__TC_MH_send 0x00000001L +#define MH_DEBUG_REG42__TC_ROQ_RTR_q_MASK 0x00000002L +#define MH_DEBUG_REG42__TC_ROQ_RTR_q 0x00000002L +#define MH_DEBUG_REG42__ROQ_MARK_q_7_MASK 0x00000004L +#define MH_DEBUG_REG42__ROQ_MARK_q_7 0x00000004L +#define MH_DEBUG_REG42__ROQ_VALID_q_7_MASK 0x00000008L +#define MH_DEBUG_REG42__ROQ_VALID_q_7 0x00000008L +#define MH_DEBUG_REG42__SAME_ROW_BANK_q_7_MASK 0x00000010L +#define MH_DEBUG_REG42__SAME_ROW_BANK_q_7 0x00000010L +#define MH_DEBUG_REG42__ROQ_ADDR_7_MASK 0xffffffe0L + +// MH_DEBUG_REG43 +#define MH_DEBUG_REG43__ARB_REG_WE_q_MASK 0x00000001L +#define MH_DEBUG_REG43__ARB_REG_WE_q 0x00000001L +#define MH_DEBUG_REG43__ARB_WE_MASK 0x00000002L +#define MH_DEBUG_REG43__ARB_WE 0x00000002L +#define MH_DEBUG_REG43__ARB_REG_VALID_q_MASK 0x00000004L +#define MH_DEBUG_REG43__ARB_REG_VALID_q 0x00000004L +#define MH_DEBUG_REG43__ARB_RTR_q_MASK 0x00000008L +#define MH_DEBUG_REG43__ARB_RTR_q 0x00000008L +#define MH_DEBUG_REG43__ARB_REG_RTR_MASK 0x00000010L +#define MH_DEBUG_REG43__ARB_REG_RTR 0x00000010L +#define MH_DEBUG_REG43__WDAT_BURST_RTR_MASK 0x00000020L +#define MH_DEBUG_REG43__WDAT_BURST_RTR 0x00000020L +#define MH_DEBUG_REG43__MMU_RTR_MASK 0x00000040L +#define MH_DEBUG_REG43__MMU_RTR 0x00000040L +#define MH_DEBUG_REG43__ARB_ID_q_MASK 0x00000380L +#define MH_DEBUG_REG43__ARB_WRITE_q_MASK 0x00000400L +#define MH_DEBUG_REG43__ARB_WRITE_q 0x00000400L +#define MH_DEBUG_REG43__ARB_BLEN_q_MASK 0x00000800L +#define MH_DEBUG_REG43__ARB_BLEN_q 0x00000800L +#define MH_DEBUG_REG43__ARQ_CTRL_EMPTY_MASK 0x00001000L +#define MH_DEBUG_REG43__ARQ_CTRL_EMPTY 0x00001000L +#define MH_DEBUG_REG43__ARQ_FIFO_CNT_q_MASK 0x0000e000L +#define MH_DEBUG_REG43__MMU_WE_MASK 0x00010000L +#define MH_DEBUG_REG43__MMU_WE 0x00010000L +#define MH_DEBUG_REG43__ARQ_RTR_MASK 0x00020000L +#define MH_DEBUG_REG43__ARQ_RTR 0x00020000L +#define MH_DEBUG_REG43__MMU_ID_MASK 0x001c0000L +#define MH_DEBUG_REG43__MMU_WRITE_MASK 0x00200000L +#define MH_DEBUG_REG43__MMU_WRITE 0x00200000L +#define MH_DEBUG_REG43__MMU_BLEN_MASK 0x00400000L +#define MH_DEBUG_REG43__MMU_BLEN 0x00400000L +#define MH_DEBUG_REG43__WBURST_IP_q_MASK 0x00800000L +#define MH_DEBUG_REG43__WBURST_IP_q 0x00800000L +#define MH_DEBUG_REG43__WDAT_REG_WE_q_MASK 0x01000000L +#define MH_DEBUG_REG43__WDAT_REG_WE_q 0x01000000L +#define MH_DEBUG_REG43__WDB_WE_MASK 0x02000000L +#define MH_DEBUG_REG43__WDB_WE 0x02000000L +#define MH_DEBUG_REG43__WDB_RTR_SKID_4_MASK 0x04000000L +#define MH_DEBUG_REG43__WDB_RTR_SKID_4 0x04000000L +#define MH_DEBUG_REG43__WDB_RTR_SKID_3_MASK 0x08000000L +#define MH_DEBUG_REG43__WDB_RTR_SKID_3 0x08000000L + +// MH_DEBUG_REG44 +#define MH_DEBUG_REG44__ARB_WE_MASK 0x00000001L +#define MH_DEBUG_REG44__ARB_WE 0x00000001L +#define MH_DEBUG_REG44__ARB_ID_q_MASK 0x0000000eL +#define MH_DEBUG_REG44__ARB_VAD_q_MASK 0xfffffff0L + +// MH_DEBUG_REG45 +#define MH_DEBUG_REG45__MMU_WE_MASK 0x00000001L +#define MH_DEBUG_REG45__MMU_WE 0x00000001L +#define MH_DEBUG_REG45__MMU_ID_MASK 0x0000000eL +#define MH_DEBUG_REG45__MMU_PAD_MASK 0xfffffff0L + +// MH_DEBUG_REG46 +#define MH_DEBUG_REG46__WDAT_REG_WE_q_MASK 0x00000001L +#define MH_DEBUG_REG46__WDAT_REG_WE_q 0x00000001L +#define MH_DEBUG_REG46__WDB_WE_MASK 0x00000002L +#define MH_DEBUG_REG46__WDB_WE 0x00000002L +#define MH_DEBUG_REG46__WDAT_REG_VALID_q_MASK 0x00000004L +#define MH_DEBUG_REG46__WDAT_REG_VALID_q 0x00000004L +#define MH_DEBUG_REG46__WDB_RTR_SKID_4_MASK 0x00000008L +#define MH_DEBUG_REG46__WDB_RTR_SKID_4 0x00000008L +#define MH_DEBUG_REG46__ARB_WSTRB_q_MASK 0x00000ff0L +#define MH_DEBUG_REG46__ARB_WLAST_MASK 0x00001000L +#define MH_DEBUG_REG46__ARB_WLAST 0x00001000L +#define MH_DEBUG_REG46__WDB_CTRL_EMPTY_MASK 0x00002000L +#define MH_DEBUG_REG46__WDB_CTRL_EMPTY 0x00002000L +#define MH_DEBUG_REG46__WDB_FIFO_CNT_q_MASK 0x0007c000L +#define MH_DEBUG_REG46__WDC_WDB_RE_q_MASK 0x00080000L +#define MH_DEBUG_REG46__WDC_WDB_RE_q 0x00080000L +#define MH_DEBUG_REG46__WDB_WDC_WID_MASK 0x00700000L +#define MH_DEBUG_REG46__WDB_WDC_WLAST_MASK 0x00800000L +#define MH_DEBUG_REG46__WDB_WDC_WLAST 0x00800000L +#define MH_DEBUG_REG46__WDB_WDC_WSTRB_MASK 0xff000000L + +// MH_DEBUG_REG47 +#define MH_DEBUG_REG47__WDB_WDC_WDATA_31_0_MASK 0xffffffffL + +// MH_DEBUG_REG48 +#define MH_DEBUG_REG48__WDB_WDC_WDATA_63_32_MASK 0xffffffffL + +// MH_DEBUG_REG49 +#define MH_DEBUG_REG49__CTRL_ARC_EMPTY_MASK 0x00000001L +#define MH_DEBUG_REG49__CTRL_ARC_EMPTY 0x00000001L +#define MH_DEBUG_REG49__CTRL_RARC_EMPTY_MASK 0x00000002L +#define MH_DEBUG_REG49__CTRL_RARC_EMPTY 0x00000002L +#define MH_DEBUG_REG49__ARQ_CTRL_EMPTY_MASK 0x00000004L +#define MH_DEBUG_REG49__ARQ_CTRL_EMPTY 0x00000004L +#define MH_DEBUG_REG49__ARQ_CTRL_WRITE_MASK 0x00000008L +#define MH_DEBUG_REG49__ARQ_CTRL_WRITE 0x00000008L +#define MH_DEBUG_REG49__TLBMISS_CTRL_RTS_MASK 0x00000010L +#define MH_DEBUG_REG49__TLBMISS_CTRL_RTS 0x00000010L +#define MH_DEBUG_REG49__CTRL_TLBMISS_RE_q_MASK 0x00000020L +#define MH_DEBUG_REG49__CTRL_TLBMISS_RE_q 0x00000020L +#define MH_DEBUG_REG49__INFLT_LIMIT_q_MASK 0x00000040L +#define MH_DEBUG_REG49__INFLT_LIMIT_q 0x00000040L +#define MH_DEBUG_REG49__INFLT_LIMIT_CNT_q_MASK 0x00001f80L +#define MH_DEBUG_REG49__ARC_CTRL_RE_q_MASK 0x00002000L +#define MH_DEBUG_REG49__ARC_CTRL_RE_q 0x00002000L +#define MH_DEBUG_REG49__RARC_CTRL_RE_q_MASK 0x00004000L +#define MH_DEBUG_REG49__RARC_CTRL_RE_q 0x00004000L +#define MH_DEBUG_REG49__RVALID_q_MASK 0x00008000L +#define MH_DEBUG_REG49__RVALID_q 0x00008000L +#define MH_DEBUG_REG49__RREADY_q_MASK 0x00010000L +#define MH_DEBUG_REG49__RREADY_q 0x00010000L +#define MH_DEBUG_REG49__RLAST_q_MASK 0x00020000L +#define MH_DEBUG_REG49__RLAST_q 0x00020000L +#define MH_DEBUG_REG49__BVALID_q_MASK 0x00040000L +#define MH_DEBUG_REG49__BVALID_q 0x00040000L +#define MH_DEBUG_REG49__BREADY_q_MASK 0x00080000L +#define MH_DEBUG_REG49__BREADY_q 0x00080000L + +// MH_DEBUG_REG50 +#define MH_DEBUG_REG50__MH_CP_grb_send_MASK 0x00000001L +#define MH_DEBUG_REG50__MH_CP_grb_send 0x00000001L +#define MH_DEBUG_REG50__MH_VGT_grb_send_MASK 0x00000002L +#define MH_DEBUG_REG50__MH_VGT_grb_send 0x00000002L +#define MH_DEBUG_REG50__MH_TC_mcsend_MASK 0x00000004L +#define MH_DEBUG_REG50__MH_TC_mcsend 0x00000004L +#define MH_DEBUG_REG50__MH_TLBMISS_SEND_MASK 0x00000008L +#define MH_DEBUG_REG50__MH_TLBMISS_SEND 0x00000008L +#define MH_DEBUG_REG50__TLBMISS_VALID_MASK 0x00000010L +#define MH_DEBUG_REG50__TLBMISS_VALID 0x00000010L +#define MH_DEBUG_REG50__RDC_VALID_MASK 0x00000020L +#define MH_DEBUG_REG50__RDC_VALID 0x00000020L +#define MH_DEBUG_REG50__RDC_RID_MASK 0x000001c0L +#define MH_DEBUG_REG50__RDC_RLAST_MASK 0x00000200L +#define MH_DEBUG_REG50__RDC_RLAST 0x00000200L +#define MH_DEBUG_REG50__RDC_RRESP_MASK 0x00000c00L +#define MH_DEBUG_REG50__TLBMISS_CTRL_RTS_MASK 0x00001000L +#define MH_DEBUG_REG50__TLBMISS_CTRL_RTS 0x00001000L +#define MH_DEBUG_REG50__CTRL_TLBMISS_RE_q_MASK 0x00002000L +#define MH_DEBUG_REG50__CTRL_TLBMISS_RE_q 0x00002000L +#define MH_DEBUG_REG50__MMU_ID_REQUEST_q_MASK 0x00004000L +#define MH_DEBUG_REG50__MMU_ID_REQUEST_q 0x00004000L +#define MH_DEBUG_REG50__OUTSTANDING_MMUID_CNT_q_MASK 0x001f8000L +#define MH_DEBUG_REG50__MMU_ID_RESPONSE_MASK 0x00200000L +#define MH_DEBUG_REG50__MMU_ID_RESPONSE 0x00200000L +#define MH_DEBUG_REG50__TLBMISS_RETURN_CNT_q_MASK 0x0fc00000L +#define MH_DEBUG_REG50__CNT_HOLD_q1_MASK 0x10000000L +#define MH_DEBUG_REG50__CNT_HOLD_q1 0x10000000L +#define MH_DEBUG_REG50__MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0xe0000000L + +// MH_DEBUG_REG51 +#define MH_DEBUG_REG51__RF_MMU_PAGE_FAULT_MASK 0xffffffffL + +// MH_DEBUG_REG52 +#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_1_to_0_MASK 0x00000003L +#define MH_DEBUG_REG52__ARB_WE_MASK 0x00000004L +#define MH_DEBUG_REG52__ARB_WE 0x00000004L +#define MH_DEBUG_REG52__MMU_RTR_MASK 0x00000008L +#define MH_DEBUG_REG52__MMU_RTR 0x00000008L +#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_25_to_4_MASK 0x03fffff0L +#define MH_DEBUG_REG52__ARB_ID_q_MASK 0x1c000000L +#define MH_DEBUG_REG52__ARB_WRITE_q_MASK 0x20000000L +#define MH_DEBUG_REG52__ARB_WRITE_q 0x20000000L +#define MH_DEBUG_REG52__client_behavior_q_MASK 0xc0000000L + +// MH_DEBUG_REG53 +#define MH_DEBUG_REG53__stage1_valid_MASK 0x00000001L +#define MH_DEBUG_REG53__stage1_valid 0x00000001L +#define MH_DEBUG_REG53__IGNORE_TAG_MISS_q_MASK 0x00000002L +#define MH_DEBUG_REG53__IGNORE_TAG_MISS_q 0x00000002L +#define MH_DEBUG_REG53__pa_in_mpu_range_MASK 0x00000004L +#define MH_DEBUG_REG53__pa_in_mpu_range 0x00000004L +#define MH_DEBUG_REG53__tag_match_q_MASK 0x00000008L +#define MH_DEBUG_REG53__tag_match_q 0x00000008L +#define MH_DEBUG_REG53__tag_miss_q_MASK 0x00000010L +#define MH_DEBUG_REG53__tag_miss_q 0x00000010L +#define MH_DEBUG_REG53__va_in_range_q_MASK 0x00000020L +#define MH_DEBUG_REG53__va_in_range_q 0x00000020L +#define MH_DEBUG_REG53__MMU_MISS_MASK 0x00000040L +#define MH_DEBUG_REG53__MMU_MISS 0x00000040L +#define MH_DEBUG_REG53__MMU_READ_MISS_MASK 0x00000080L +#define MH_DEBUG_REG53__MMU_READ_MISS 0x00000080L +#define MH_DEBUG_REG53__MMU_WRITE_MISS_MASK 0x00000100L +#define MH_DEBUG_REG53__MMU_WRITE_MISS 0x00000100L +#define MH_DEBUG_REG53__MMU_HIT_MASK 0x00000200L +#define MH_DEBUG_REG53__MMU_HIT 0x00000200L +#define MH_DEBUG_REG53__MMU_READ_HIT_MASK 0x00000400L +#define MH_DEBUG_REG53__MMU_READ_HIT 0x00000400L +#define MH_DEBUG_REG53__MMU_WRITE_HIT_MASK 0x00000800L +#define MH_DEBUG_REG53__MMU_WRITE_HIT 0x00000800L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_MISS_MASK 0x00001000L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_MISS 0x00001000L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_HIT_MASK 0x00002000L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_HIT 0x00002000L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_MISS_MASK 0x00004000L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_MISS 0x00004000L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_HIT_MASK 0x00008000L +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_HIT 0x00008000L +#define MH_DEBUG_REG53__REQ_VA_OFFSET_q_MASK 0xffff0000L + +// MH_DEBUG_REG54 +#define MH_DEBUG_REG54__ARQ_RTR_MASK 0x00000001L +#define MH_DEBUG_REG54__ARQ_RTR 0x00000001L +#define MH_DEBUG_REG54__MMU_WE_MASK 0x00000002L +#define MH_DEBUG_REG54__MMU_WE 0x00000002L +#define MH_DEBUG_REG54__CTRL_TLBMISS_RE_q_MASK 0x00000004L +#define MH_DEBUG_REG54__CTRL_TLBMISS_RE_q 0x00000004L +#define MH_DEBUG_REG54__TLBMISS_CTRL_RTS_MASK 0x00000008L +#define MH_DEBUG_REG54__TLBMISS_CTRL_RTS 0x00000008L +#define MH_DEBUG_REG54__MH_TLBMISS_SEND_MASK 0x00000010L +#define MH_DEBUG_REG54__MH_TLBMISS_SEND 0x00000010L +#define MH_DEBUG_REG54__MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK 0x00000020L +#define MH_DEBUG_REG54__MMU_STALL_AWAITING_TLB_MISS_FETCH 0x00000020L +#define MH_DEBUG_REG54__pa_in_mpu_range_MASK 0x00000040L +#define MH_DEBUG_REG54__pa_in_mpu_range 0x00000040L +#define MH_DEBUG_REG54__stage1_valid_MASK 0x00000080L +#define MH_DEBUG_REG54__stage1_valid 0x00000080L +#define MH_DEBUG_REG54__stage2_valid_MASK 0x00000100L +#define MH_DEBUG_REG54__stage2_valid 0x00000100L +#define MH_DEBUG_REG54__client_behavior_q_MASK 0x00000600L +#define MH_DEBUG_REG54__IGNORE_TAG_MISS_q_MASK 0x00000800L +#define MH_DEBUG_REG54__IGNORE_TAG_MISS_q 0x00000800L +#define MH_DEBUG_REG54__tag_match_q_MASK 0x00001000L +#define MH_DEBUG_REG54__tag_match_q 0x00001000L +#define MH_DEBUG_REG54__tag_miss_q_MASK 0x00002000L +#define MH_DEBUG_REG54__tag_miss_q 0x00002000L +#define MH_DEBUG_REG54__va_in_range_q_MASK 0x00004000L +#define MH_DEBUG_REG54__va_in_range_q 0x00004000L +#define MH_DEBUG_REG54__PTE_FETCH_COMPLETE_q_MASK 0x00008000L +#define MH_DEBUG_REG54__PTE_FETCH_COMPLETE_q 0x00008000L +#define MH_DEBUG_REG54__TAG_valid_q_MASK 0xffff0000L + +// MH_DEBUG_REG55 +#define MH_DEBUG_REG55__TAG0_VA_MASK 0x00001fffL +#define MH_DEBUG_REG55__TAG_valid_q_0_MASK 0x00002000L +#define MH_DEBUG_REG55__TAG_valid_q_0 0x00002000L +#define MH_DEBUG_REG55__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG55__TAG1_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG55__TAG_valid_q_1_MASK 0x20000000L +#define MH_DEBUG_REG55__TAG_valid_q_1 0x20000000L + +// MH_DEBUG_REG56 +#define MH_DEBUG_REG56__TAG2_VA_MASK 0x00001fffL +#define MH_DEBUG_REG56__TAG_valid_q_2_MASK 0x00002000L +#define MH_DEBUG_REG56__TAG_valid_q_2 0x00002000L +#define MH_DEBUG_REG56__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG56__TAG3_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG56__TAG_valid_q_3_MASK 0x20000000L +#define MH_DEBUG_REG56__TAG_valid_q_3 0x20000000L + +// MH_DEBUG_REG57 +#define MH_DEBUG_REG57__TAG4_VA_MASK 0x00001fffL +#define MH_DEBUG_REG57__TAG_valid_q_4_MASK 0x00002000L +#define MH_DEBUG_REG57__TAG_valid_q_4 0x00002000L +#define MH_DEBUG_REG57__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG57__TAG5_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG57__TAG_valid_q_5_MASK 0x20000000L +#define MH_DEBUG_REG57__TAG_valid_q_5 0x20000000L + +// MH_DEBUG_REG58 +#define MH_DEBUG_REG58__TAG6_VA_MASK 0x00001fffL +#define MH_DEBUG_REG58__TAG_valid_q_6_MASK 0x00002000L +#define MH_DEBUG_REG58__TAG_valid_q_6 0x00002000L +#define MH_DEBUG_REG58__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG58__TAG7_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG58__TAG_valid_q_7_MASK 0x20000000L +#define MH_DEBUG_REG58__TAG_valid_q_7 0x20000000L + +// MH_DEBUG_REG59 +#define MH_DEBUG_REG59__TAG8_VA_MASK 0x00001fffL +#define MH_DEBUG_REG59__TAG_valid_q_8_MASK 0x00002000L +#define MH_DEBUG_REG59__TAG_valid_q_8 0x00002000L +#define MH_DEBUG_REG59__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG59__TAG9_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG59__TAG_valid_q_9_MASK 0x20000000L +#define MH_DEBUG_REG59__TAG_valid_q_9 0x20000000L + +// MH_DEBUG_REG60 +#define MH_DEBUG_REG60__TAG10_VA_MASK 0x00001fffL +#define MH_DEBUG_REG60__TAG_valid_q_10_MASK 0x00002000L +#define MH_DEBUG_REG60__TAG_valid_q_10 0x00002000L +#define MH_DEBUG_REG60__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG60__TAG11_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG60__TAG_valid_q_11_MASK 0x20000000L +#define MH_DEBUG_REG60__TAG_valid_q_11 0x20000000L + +// MH_DEBUG_REG61 +#define MH_DEBUG_REG61__TAG12_VA_MASK 0x00001fffL +#define MH_DEBUG_REG61__TAG_valid_q_12_MASK 0x00002000L +#define MH_DEBUG_REG61__TAG_valid_q_12 0x00002000L +#define MH_DEBUG_REG61__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG61__TAG13_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG61__TAG_valid_q_13_MASK 0x20000000L +#define MH_DEBUG_REG61__TAG_valid_q_13 0x20000000L + +// MH_DEBUG_REG62 +#define MH_DEBUG_REG62__TAG14_VA_MASK 0x00001fffL +#define MH_DEBUG_REG62__TAG_valid_q_14_MASK 0x00002000L +#define MH_DEBUG_REG62__TAG_valid_q_14 0x00002000L +#define MH_DEBUG_REG62__ALWAYS_ZERO_MASK 0x0000c000L +#define MH_DEBUG_REG62__TAG15_VA_MASK 0x1fff0000L +#define MH_DEBUG_REG62__TAG_valid_q_15_MASK 0x20000000L +#define MH_DEBUG_REG62__TAG_valid_q_15 0x20000000L + +// MH_DEBUG_REG63 +#define MH_DEBUG_REG63__MH_DBG_DEFAULT_MASK 0xffffffffL + +// MH_MMU_CONFIG +#define MH_MMU_CONFIG__MMU_ENABLE_MASK 0x00000001L +#define MH_MMU_CONFIG__MMU_ENABLE 0x00000001L +#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE_MASK 0x00000002L +#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE 0x00000002L +#define MH_MMU_CONFIG__RESERVED1_MASK 0x0000000cL +#define MH_MMU_CONFIG__RB_W_CLNT_BEHAVIOR_MASK 0x00000030L +#define MH_MMU_CONFIG__CP_W_CLNT_BEHAVIOR_MASK 0x000000c0L +#define MH_MMU_CONFIG__CP_R0_CLNT_BEHAVIOR_MASK 0x00000300L +#define MH_MMU_CONFIG__CP_R1_CLNT_BEHAVIOR_MASK 0x00000c00L +#define MH_MMU_CONFIG__CP_R2_CLNT_BEHAVIOR_MASK 0x00003000L +#define MH_MMU_CONFIG__CP_R3_CLNT_BEHAVIOR_MASK 0x0000c000L +#define MH_MMU_CONFIG__CP_R4_CLNT_BEHAVIOR_MASK 0x00030000L +#define MH_MMU_CONFIG__VGT_R0_CLNT_BEHAVIOR_MASK 0x000c0000L +#define MH_MMU_CONFIG__VGT_R1_CLNT_BEHAVIOR_MASK 0x00300000L +#define MH_MMU_CONFIG__TC_R_CLNT_BEHAVIOR_MASK 0x00c00000L +#define MH_MMU_CONFIG__PA_W_CLNT_BEHAVIOR_MASK 0x03000000L + +// MH_MMU_VA_RANGE +#define MH_MMU_VA_RANGE__NUM_64KB_REGIONS_MASK 0x00000fffL +#define MH_MMU_VA_RANGE__VA_BASE_MASK 0xfffff000L + +// MH_MMU_PT_BASE +#define MH_MMU_PT_BASE__PT_BASE_MASK 0xfffff000L + +// MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT__PAGE_FAULT_MASK 0x00000001L +#define MH_MMU_PAGE_FAULT__PAGE_FAULT 0x00000001L +#define MH_MMU_PAGE_FAULT__OP_TYPE_MASK 0x00000002L +#define MH_MMU_PAGE_FAULT__OP_TYPE 0x00000002L +#define MH_MMU_PAGE_FAULT__CLNT_BEHAVIOR_MASK 0x0000000cL +#define MH_MMU_PAGE_FAULT__AXI_ID_MASK 0x00000070L +#define MH_MMU_PAGE_FAULT__RESERVED1_MASK 0x00000080L +#define MH_MMU_PAGE_FAULT__RESERVED1 0x00000080L +#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE_MASK 0x00000100L +#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE 0x00000100L +#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE_MASK 0x00000200L +#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE 0x00000200L +#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR_MASK 0x00000400L +#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR 0x00000400L +#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR_MASK 0x00000800L +#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR 0x00000800L +#define MH_MMU_PAGE_FAULT__REQ_VA_MASK 0xfffff000L + +// MH_MMU_TRAN_ERROR +#define MH_MMU_TRAN_ERROR__TRAN_ERROR_MASK 0xffffffe0L + +// MH_MMU_INVALIDATE +#define MH_MMU_INVALIDATE__INVALIDATE_ALL_MASK 0x00000001L +#define MH_MMU_INVALIDATE__INVALIDATE_ALL 0x00000001L +#define MH_MMU_INVALIDATE__INVALIDATE_TC_MASK 0x00000002L +#define MH_MMU_INVALIDATE__INVALIDATE_TC 0x00000002L + +// MH_MMU_MPU_BASE +#define MH_MMU_MPU_BASE__MPU_BASE_MASK 0xfffff000L + +// MH_MMU_MPU_END +#define MH_MMU_MPU_END__MPU_END_MASK 0xfffff000L + +// WAIT_UNTIL +#define WAIT_UNTIL__WAIT_RE_VSYNC_MASK 0x00000002L +#define WAIT_UNTIL__WAIT_RE_VSYNC 0x00000002L +#define WAIT_UNTIL__WAIT_FE_VSYNC_MASK 0x00000004L +#define WAIT_UNTIL__WAIT_FE_VSYNC 0x00000004L +#define WAIT_UNTIL__WAIT_VSYNC_MASK 0x00000008L +#define WAIT_UNTIL__WAIT_VSYNC 0x00000008L +#define WAIT_UNTIL__WAIT_DSPLY_ID0_MASK 0x00000010L +#define WAIT_UNTIL__WAIT_DSPLY_ID0 0x00000010L +#define WAIT_UNTIL__WAIT_DSPLY_ID1_MASK 0x00000020L +#define WAIT_UNTIL__WAIT_DSPLY_ID1 0x00000020L +#define WAIT_UNTIL__WAIT_DSPLY_ID2_MASK 0x00000040L +#define WAIT_UNTIL__WAIT_DSPLY_ID2 0x00000040L +#define WAIT_UNTIL__WAIT_CMDFIFO_MASK 0x00000400L +#define WAIT_UNTIL__WAIT_CMDFIFO 0x00000400L +#define WAIT_UNTIL__WAIT_2D_IDLE_MASK 0x00004000L +#define WAIT_UNTIL__WAIT_2D_IDLE 0x00004000L +#define WAIT_UNTIL__WAIT_3D_IDLE_MASK 0x00008000L +#define WAIT_UNTIL__WAIT_3D_IDLE 0x00008000L +#define WAIT_UNTIL__WAIT_2D_IDLECLEAN_MASK 0x00010000L +#define WAIT_UNTIL__WAIT_2D_IDLECLEAN 0x00010000L +#define WAIT_UNTIL__WAIT_3D_IDLECLEAN_MASK 0x00020000L +#define WAIT_UNTIL__WAIT_3D_IDLECLEAN 0x00020000L +#define WAIT_UNTIL__CMDFIFO_ENTRIES_MASK 0x00f00000L + +// RBBM_ISYNC_CNTL +#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI_MASK 0x00000010L +#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI 0x00000010L +#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI_MASK 0x00000020L +#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI 0x00000020L + +// RBBM_STATUS +#define RBBM_STATUS__CMDFIFO_AVAIL_MASK 0x0000001fL +#define RBBM_STATUS__TC_BUSY_MASK 0x00000020L +#define RBBM_STATUS__TC_BUSY 0x00000020L +#define RBBM_STATUS__HIRQ_PENDING_MASK 0x00000100L +#define RBBM_STATUS__HIRQ_PENDING 0x00000100L +#define RBBM_STATUS__CPRQ_PENDING_MASK 0x00000200L +#define RBBM_STATUS__CPRQ_PENDING 0x00000200L +#define RBBM_STATUS__CFRQ_PENDING_MASK 0x00000400L +#define RBBM_STATUS__CFRQ_PENDING 0x00000400L +#define RBBM_STATUS__PFRQ_PENDING_MASK 0x00000800L +#define RBBM_STATUS__PFRQ_PENDING 0x00000800L +#define RBBM_STATUS__VGT_BUSY_NO_DMA_MASK 0x00001000L +#define RBBM_STATUS__VGT_BUSY_NO_DMA 0x00001000L +#define RBBM_STATUS__RBBM_WU_BUSY_MASK 0x00004000L +#define RBBM_STATUS__RBBM_WU_BUSY 0x00004000L +#define RBBM_STATUS__CP_NRT_BUSY_MASK 0x00010000L +#define RBBM_STATUS__CP_NRT_BUSY 0x00010000L +#define RBBM_STATUS__MH_BUSY_MASK 0x00040000L +#define RBBM_STATUS__MH_BUSY 0x00040000L +#define RBBM_STATUS__MH_COHERENCY_BUSY_MASK 0x00080000L +#define RBBM_STATUS__MH_COHERENCY_BUSY 0x00080000L +#define RBBM_STATUS__SX_BUSY_MASK 0x00200000L +#define RBBM_STATUS__SX_BUSY 0x00200000L +#define RBBM_STATUS__TPC_BUSY_MASK 0x00400000L +#define RBBM_STATUS__TPC_BUSY 0x00400000L +#define RBBM_STATUS__SC_CNTX_BUSY_MASK 0x01000000L +#define RBBM_STATUS__SC_CNTX_BUSY 0x01000000L +#define RBBM_STATUS__PA_BUSY_MASK 0x02000000L +#define RBBM_STATUS__PA_BUSY 0x02000000L +#define RBBM_STATUS__VGT_BUSY_MASK 0x04000000L +#define RBBM_STATUS__VGT_BUSY 0x04000000L +#define RBBM_STATUS__SQ_CNTX17_BUSY_MASK 0x08000000L +#define RBBM_STATUS__SQ_CNTX17_BUSY 0x08000000L +#define RBBM_STATUS__SQ_CNTX0_BUSY_MASK 0x10000000L +#define RBBM_STATUS__SQ_CNTX0_BUSY 0x10000000L +#define RBBM_STATUS__RB_CNTX_BUSY_MASK 0x40000000L +#define RBBM_STATUS__RB_CNTX_BUSY 0x40000000L +#define RBBM_STATUS__GUI_ACTIVE_MASK 0x80000000L +#define RBBM_STATUS__GUI_ACTIVE 0x80000000L + +// RBBM_DSPLY +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID0_MASK 0x00000001L +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID0 0x00000001L +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID1_MASK 0x00000002L +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID1 0x00000002L +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID2_MASK 0x00000004L +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID2 0x00000004L +#define RBBM_DSPLY__SEL_DMI_VSYNC_VALID_MASK 0x00000008L +#define RBBM_DSPLY__SEL_DMI_VSYNC_VALID 0x00000008L +#define RBBM_DSPLY__DMI_CH1_USE_BUFID0_MASK 0x00000010L +#define RBBM_DSPLY__DMI_CH1_USE_BUFID0 0x00000010L +#define RBBM_DSPLY__DMI_CH1_USE_BUFID1_MASK 0x00000020L +#define RBBM_DSPLY__DMI_CH1_USE_BUFID1 0x00000020L +#define RBBM_DSPLY__DMI_CH1_USE_BUFID2_MASK 0x00000040L +#define RBBM_DSPLY__DMI_CH1_USE_BUFID2 0x00000040L +#define RBBM_DSPLY__DMI_CH1_SW_CNTL_MASK 0x00000080L +#define RBBM_DSPLY__DMI_CH1_SW_CNTL 0x00000080L +#define RBBM_DSPLY__DMI_CH1_NUM_BUFS_MASK 0x00000300L +#define RBBM_DSPLY__DMI_CH2_USE_BUFID0_MASK 0x00000400L +#define RBBM_DSPLY__DMI_CH2_USE_BUFID0 0x00000400L +#define RBBM_DSPLY__DMI_CH2_USE_BUFID1_MASK 0x00000800L +#define RBBM_DSPLY__DMI_CH2_USE_BUFID1 0x00000800L +#define RBBM_DSPLY__DMI_CH2_USE_BUFID2_MASK 0x00001000L +#define RBBM_DSPLY__DMI_CH2_USE_BUFID2 0x00001000L +#define RBBM_DSPLY__DMI_CH2_SW_CNTL_MASK 0x00002000L +#define RBBM_DSPLY__DMI_CH2_SW_CNTL 0x00002000L +#define RBBM_DSPLY__DMI_CH2_NUM_BUFS_MASK 0x0000c000L +#define RBBM_DSPLY__DMI_CHANNEL_SELECT_MASK 0x00030000L +#define RBBM_DSPLY__DMI_CH3_USE_BUFID0_MASK 0x00100000L +#define RBBM_DSPLY__DMI_CH3_USE_BUFID0 0x00100000L +#define RBBM_DSPLY__DMI_CH3_USE_BUFID1_MASK 0x00200000L +#define RBBM_DSPLY__DMI_CH3_USE_BUFID1 0x00200000L +#define RBBM_DSPLY__DMI_CH3_USE_BUFID2_MASK 0x00400000L +#define RBBM_DSPLY__DMI_CH3_USE_BUFID2 0x00400000L +#define RBBM_DSPLY__DMI_CH3_SW_CNTL_MASK 0x00800000L +#define RBBM_DSPLY__DMI_CH3_SW_CNTL 0x00800000L +#define RBBM_DSPLY__DMI_CH3_NUM_BUFS_MASK 0x03000000L +#define RBBM_DSPLY__DMI_CH4_USE_BUFID0_MASK 0x04000000L +#define RBBM_DSPLY__DMI_CH4_USE_BUFID0 0x04000000L +#define RBBM_DSPLY__DMI_CH4_USE_BUFID1_MASK 0x08000000L +#define RBBM_DSPLY__DMI_CH4_USE_BUFID1 0x08000000L +#define RBBM_DSPLY__DMI_CH4_USE_BUFID2_MASK 0x10000000L +#define RBBM_DSPLY__DMI_CH4_USE_BUFID2 0x10000000L +#define RBBM_DSPLY__DMI_CH4_SW_CNTL_MASK 0x20000000L +#define RBBM_DSPLY__DMI_CH4_SW_CNTL 0x20000000L +#define RBBM_DSPLY__DMI_CH4_NUM_BUFS_MASK 0xc0000000L + +// RBBM_RENDER_LATEST +#define RBBM_RENDER_LATEST__DMI_CH1_BUFFER_ID_MASK 0x00000003L +#define RBBM_RENDER_LATEST__DMI_CH2_BUFFER_ID_MASK 0x00000300L +#define RBBM_RENDER_LATEST__DMI_CH3_BUFFER_ID_MASK 0x00030000L +#define RBBM_RENDER_LATEST__DMI_CH4_BUFFER_ID_MASK 0x03000000L + +// RBBM_RTL_RELEASE +#define RBBM_RTL_RELEASE__CHANGELIST_MASK 0xffffffffL + +// RBBM_PATCH_RELEASE +#define RBBM_PATCH_RELEASE__PATCH_REVISION_MASK 0x0000ffffL +#define RBBM_PATCH_RELEASE__PATCH_SELECTION_MASK 0x00ff0000L +#define RBBM_PATCH_RELEASE__CUSTOMER_ID_MASK 0xff000000L + +// RBBM_AUXILIARY_CONFIG +#define RBBM_AUXILIARY_CONFIG__RESERVED_MASK 0xffffffffL + +// RBBM_PERIPHID0 +#define RBBM_PERIPHID0__PARTNUMBER0_MASK 0x000000ffL + +// RBBM_PERIPHID1 +#define RBBM_PERIPHID1__PARTNUMBER1_MASK 0x0000000fL +#define RBBM_PERIPHID1__DESIGNER0_MASK 0x000000f0L + +// RBBM_PERIPHID2 +#define RBBM_PERIPHID2__DESIGNER1_MASK 0x0000000fL +#define RBBM_PERIPHID2__REVISION_MASK 0x000000f0L + +// RBBM_PERIPHID3 +#define RBBM_PERIPHID3__RBBM_HOST_INTERFACE_MASK 0x00000003L +#define RBBM_PERIPHID3__GARB_SLAVE_INTERFACE_MASK 0x0000000cL +#define RBBM_PERIPHID3__MH_INTERFACE_MASK 0x00000030L +#define RBBM_PERIPHID3__CONTINUATION_MASK 0x00000080L +#define RBBM_PERIPHID3__CONTINUATION 0x00000080L + +// RBBM_CNTL +#define RBBM_CNTL__READ_TIMEOUT_MASK 0x000000ffL +#define RBBM_CNTL__REGCLK_DEASSERT_TIME_MASK 0x0001ff00L + +// RBBM_SKEW_CNTL +#define RBBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x0000001fL +#define RBBM_SKEW_CNTL__SKEW_COUNT_MASK 0x000003e0L + +// RBBM_SOFT_RESET +#define RBBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L +#define RBBM_SOFT_RESET__SOFT_RESET_CP 0x00000001L +#define RBBM_SOFT_RESET__SOFT_RESET_PA_MASK 0x00000004L +#define RBBM_SOFT_RESET__SOFT_RESET_PA 0x00000004L +#define RBBM_SOFT_RESET__SOFT_RESET_MH_MASK 0x00000008L +#define RBBM_SOFT_RESET__SOFT_RESET_MH 0x00000008L +#define RBBM_SOFT_RESET__SOFT_RESET_BC_MASK 0x00000010L +#define RBBM_SOFT_RESET__SOFT_RESET_BC 0x00000010L +#define RBBM_SOFT_RESET__SOFT_RESET_SQ_MASK 0x00000020L +#define RBBM_SOFT_RESET__SOFT_RESET_SQ 0x00000020L +#define RBBM_SOFT_RESET__SOFT_RESET_SX_MASK 0x00000040L +#define RBBM_SOFT_RESET__SOFT_RESET_SX 0x00000040L +#define RBBM_SOFT_RESET__SOFT_RESET_CIB_MASK 0x00001000L +#define RBBM_SOFT_RESET__SOFT_RESET_CIB 0x00001000L +#define RBBM_SOFT_RESET__SOFT_RESET_SC_MASK 0x00008000L +#define RBBM_SOFT_RESET__SOFT_RESET_SC 0x00008000L +#define RBBM_SOFT_RESET__SOFT_RESET_VGT_MASK 0x00010000L +#define RBBM_SOFT_RESET__SOFT_RESET_VGT 0x00010000L + +// RBBM_PM_OVERRIDE1 +#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE_MASK 0x00000001L +#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE 0x00000001L +#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE_MASK 0x00000002L +#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE 0x00000002L +#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE_MASK 0x00000004L +#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE 0x00000004L +#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE_MASK 0x00000008L +#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE 0x00000008L +#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE_MASK 0x00000010L +#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE 0x00000010L +#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE_MASK 0x00000020L +#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE 0x00000020L +#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000040L +#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE 0x00000040L +#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK 0x00000080L +#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE 0x00000080L +#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE_MASK 0x00000100L +#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE 0x00000100L +#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE_MASK 0x00000200L +#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE 0x00000200L +#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE_MASK 0x00000400L +#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE 0x00000400L +#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE_MASK 0x00000800L +#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE 0x00000800L +#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE_MASK 0x00001000L +#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE 0x00001000L +#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE_MASK 0x00002000L +#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE 0x00002000L +#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE_MASK 0x00004000L +#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE 0x00004000L +#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE_MASK 0x00008000L +#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE 0x00008000L +#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE_MASK 0x00010000L +#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE 0x00010000L +#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE_MASK 0x00020000L +#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE 0x00020000L +#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE_MASK 0x00040000L +#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE 0x00040000L +#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK 0x00080000L +#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE 0x00080000L +#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE_MASK 0x00100000L +#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE 0x00100000L +#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE_MASK 0x00200000L +#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE 0x00200000L +#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE_MASK 0x00400000L +#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE 0x00400000L +#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE_MASK 0x00800000L +#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE 0x00800000L +#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE_MASK 0x01000000L +#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE 0x01000000L +#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE_MASK 0x02000000L +#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE 0x02000000L +#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE_MASK 0x04000000L +#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE 0x04000000L +#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE_MASK 0x08000000L +#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE 0x08000000L +#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE_MASK 0x10000000L +#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE 0x10000000L +#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE_MASK 0x20000000L +#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE 0x20000000L +#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE_MASK 0x40000000L +#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE 0x40000000L +#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE_MASK 0x80000000L +#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE 0x80000000L + +// RBBM_PM_OVERRIDE2 +#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE_MASK 0x00000001L +#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE 0x00000001L +#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE_MASK 0x00000002L +#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE 0x00000002L +#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE_MASK 0x00000004L +#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE 0x00000004L +#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE_MASK 0x00000008L +#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE 0x00000008L +#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000010L +#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE 0x00000010L +#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE_MASK 0x00000020L +#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE 0x00000020L +#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE_MASK 0x00000040L +#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE 0x00000040L +#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE_MASK 0x00000080L +#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE 0x00000080L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE_MASK 0x00000100L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE 0x00000100L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE_MASK 0x00000200L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE 0x00000200L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE_MASK 0x00000400L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE 0x00000400L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE_MASK 0x00000800L +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE 0x00000800L + +// GC_SYS_IDLE +#define GC_SYS_IDLE__GC_SYS_IDLE_DELAY_MASK 0x0000ffffL +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_MASK_MASK 0x003f0000L +#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_MASK 0x01000000L +#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP 0x01000000L +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_MASK 0x02000000L +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI 0x02000000L +#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_OVERRIDE_MASK 0x20000000L +#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_OVERRIDE 0x20000000L +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_OVERRIDE_MASK 0x40000000L +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_OVERRIDE 0x40000000L +#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE_MASK 0x80000000L +#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE 0x80000000L + +// NQWAIT_UNTIL +#define NQWAIT_UNTIL__WAIT_GUI_IDLE_MASK 0x00000001L +#define NQWAIT_UNTIL__WAIT_GUI_IDLE 0x00000001L + +// RBBM_DEBUG_OUT +#define RBBM_DEBUG_OUT__DEBUG_BUS_OUT_MASK 0xffffffffL + +// RBBM_DEBUG_CNTL +#define RBBM_DEBUG_CNTL__SUB_BLOCK_ADDR_MASK 0x0000003fL +#define RBBM_DEBUG_CNTL__SUB_BLOCK_SEL_MASK 0x00000f00L +#define RBBM_DEBUG_CNTL__SW_ENABLE_MASK 0x00001000L +#define RBBM_DEBUG_CNTL__SW_ENABLE 0x00001000L +#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_ADDR_MASK 0x003f0000L +#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_SEL_MASK 0x0f000000L +#define RBBM_DEBUG_CNTL__GPIO_BYTE_LANE_ENB_MASK 0xf0000000L + +// RBBM_DEBUG +#define RBBM_DEBUG__IGNORE_RTR_MASK 0x00000002L +#define RBBM_DEBUG__IGNORE_RTR 0x00000002L +#define RBBM_DEBUG__IGNORE_CP_SCHED_WU_MASK 0x00000004L +#define RBBM_DEBUG__IGNORE_CP_SCHED_WU 0x00000004L +#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC_MASK 0x00000008L +#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC 0x00000008L +#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI_MASK 0x00000010L +#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI 0x00000010L +#define RBBM_DEBUG__HYSTERESIS_NRT_GUI_ACTIVE_MASK 0x00000f00L +#define RBBM_DEBUG__IGNORE_RTR_FOR_HI_MASK 0x00010000L +#define RBBM_DEBUG__IGNORE_RTR_FOR_HI 0x00010000L +#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK 0x00020000L +#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI 0x00020000L +#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK 0x00040000L +#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI 0x00040000L +#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK 0x00080000L +#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI 0x00080000L +#define RBBM_DEBUG__CP_RBBM_NRTRTR_MASK 0x00100000L +#define RBBM_DEBUG__CP_RBBM_NRTRTR 0x00100000L +#define RBBM_DEBUG__VGT_RBBM_NRTRTR_MASK 0x00200000L +#define RBBM_DEBUG__VGT_RBBM_NRTRTR 0x00200000L +#define RBBM_DEBUG__SQ_RBBM_NRTRTR_MASK 0x00400000L +#define RBBM_DEBUG__SQ_RBBM_NRTRTR 0x00400000L +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI_MASK 0x00800000L +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI 0x00800000L +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_MASK 0x01000000L +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR 0x01000000L +#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY_MASK 0x80000000L +#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY 0x80000000L + +// RBBM_READ_ERROR +#define RBBM_READ_ERROR__READ_ADDRESS_MASK 0x0001fffcL +#define RBBM_READ_ERROR__READ_REQUESTER_MASK 0x40000000L +#define RBBM_READ_ERROR__READ_REQUESTER 0x40000000L +#define RBBM_READ_ERROR__READ_ERROR_MASK 0x80000000L +#define RBBM_READ_ERROR__READ_ERROR 0x80000000L + +// RBBM_WAIT_IDLE_CLOCKS +#define RBBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_NRT_MASK 0x000000ffL + +// RBBM_INT_CNTL +#define RBBM_INT_CNTL__RDERR_INT_MASK_MASK 0x00000001L +#define RBBM_INT_CNTL__RDERR_INT_MASK 0x00000001L +#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK_MASK 0x00000002L +#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK 0x00000002L +#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK_MASK 0x00080000L +#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK 0x00080000L + +// RBBM_INT_STATUS +#define RBBM_INT_STATUS__RDERR_INT_STAT_MASK 0x00000001L +#define RBBM_INT_STATUS__RDERR_INT_STAT 0x00000001L +#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT_MASK 0x00000002L +#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT 0x00000002L +#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT_MASK 0x00080000L +#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT 0x00080000L + +// RBBM_INT_ACK +#define RBBM_INT_ACK__RDERR_INT_ACK_MASK 0x00000001L +#define RBBM_INT_ACK__RDERR_INT_ACK 0x00000001L +#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK_MASK 0x00000002L +#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK 0x00000002L +#define RBBM_INT_ACK__GUI_IDLE_INT_ACK_MASK 0x00080000L +#define RBBM_INT_ACK__GUI_IDLE_INT_ACK 0x00080000L + +// MASTER_INT_SIGNAL +#define MASTER_INT_SIGNAL__MH_INT_STAT_MASK 0x00000020L +#define MASTER_INT_SIGNAL__MH_INT_STAT 0x00000020L +#define MASTER_INT_SIGNAL__SQ_INT_STAT_MASK 0x04000000L +#define MASTER_INT_SIGNAL__SQ_INT_STAT 0x04000000L +#define MASTER_INT_SIGNAL__CP_INT_STAT_MASK 0x40000000L +#define MASTER_INT_SIGNAL__CP_INT_STAT 0x40000000L +#define MASTER_INT_SIGNAL__RBBM_INT_STAT_MASK 0x80000000L +#define MASTER_INT_SIGNAL__RBBM_INT_STAT 0x80000000L + +// RBBM_PERFCOUNTER1_SELECT +#define RBBM_PERFCOUNTER1_SELECT__PERF_COUNT1_SEL_MASK 0x0000003fL + +// RBBM_PERFCOUNTER1_LO +#define RBBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK 0xffffffffL + +// RBBM_PERFCOUNTER1_HI +#define RBBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK 0x0000ffffL + +// CP_RB_BASE +#define CP_RB_BASE__RB_BASE_MASK 0xffffffe0L + +// CP_RB_CNTL +#define CP_RB_CNTL__RB_BUFSZ_MASK 0x0000003fL +#define CP_RB_CNTL__RB_BLKSZ_MASK 0x00003f00L +#define CP_RB_CNTL__BUF_SWAP_MASK 0x00030000L +#define CP_RB_CNTL__RB_POLL_EN_MASK 0x00100000L +#define CP_RB_CNTL__RB_POLL_EN 0x00100000L +#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x08000000L +#define CP_RB_CNTL__RB_NO_UPDATE 0x08000000L +#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L +#define CP_RB_CNTL__RB_RPTR_WR_ENA 0x80000000L + +// CP_RB_RPTR_ADDR +#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x00000003L +#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffcL + +// CP_RB_RPTR +#define CP_RB_RPTR__RB_RPTR_MASK 0x000fffffL + +// CP_RB_RPTR_WR +#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0x000fffffL + +// CP_RB_WPTR +#define CP_RB_WPTR__RB_WPTR_MASK 0x000fffffL + +// CP_RB_WPTR_DELAY +#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0x0fffffffL +#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xf0000000L + +// CP_RB_WPTR_BASE +#define CP_RB_WPTR_BASE__RB_WPTR_SWAP_MASK 0x00000003L +#define CP_RB_WPTR_BASE__RB_WPTR_BASE_MASK 0xfffffffcL + +// CP_IB1_BASE +#define CP_IB1_BASE__IB1_BASE_MASK 0xfffffffcL + +// CP_IB1_BUFSZ +#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000fffffL + +// CP_IB2_BASE +#define CP_IB2_BASE__IB2_BASE_MASK 0xfffffffcL + +// CP_IB2_BUFSZ +#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000fffffL + +// CP_ST_BASE +#define CP_ST_BASE__ST_BASE_MASK 0xfffffffcL + +// CP_ST_BUFSZ +#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0x000fffffL + +// CP_QUEUE_THRESHOLDS +#define CP_QUEUE_THRESHOLDS__CSQ_IB1_START_MASK 0x0000000fL +#define CP_QUEUE_THRESHOLDS__CSQ_IB2_START_MASK 0x00000f00L +#define CP_QUEUE_THRESHOLDS__CSQ_ST_START_MASK 0x000f0000L + +// CP_MEQ_THRESHOLDS +#define CP_MEQ_THRESHOLDS__MEQ_END_MASK 0x001f0000L +#define CP_MEQ_THRESHOLDS__ROQ_END_MASK 0x1f000000L + +// CP_CSQ_AVAIL +#define CP_CSQ_AVAIL__CSQ_CNT_RING_MASK 0x0000007fL +#define CP_CSQ_AVAIL__CSQ_CNT_IB1_MASK 0x00007f00L +#define CP_CSQ_AVAIL__CSQ_CNT_IB2_MASK 0x007f0000L + +// CP_STQ_AVAIL +#define CP_STQ_AVAIL__STQ_CNT_ST_MASK 0x0000007fL + +// CP_MEQ_AVAIL +#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x0000001fL + +// CP_CSQ_RB_STAT +#define CP_CSQ_RB_STAT__CSQ_RPTR_PRIMARY_MASK 0x0000007fL +#define CP_CSQ_RB_STAT__CSQ_WPTR_PRIMARY_MASK 0x007f0000L + +// CP_CSQ_IB1_STAT +#define CP_CSQ_IB1_STAT__CSQ_RPTR_INDIRECT1_MASK 0x0000007fL +#define CP_CSQ_IB1_STAT__CSQ_WPTR_INDIRECT1_MASK 0x007f0000L + +// CP_CSQ_IB2_STAT +#define CP_CSQ_IB2_STAT__CSQ_RPTR_INDIRECT2_MASK 0x0000007fL +#define CP_CSQ_IB2_STAT__CSQ_WPTR_INDIRECT2_MASK 0x007f0000L + +// CP_NON_PREFETCH_CNTRS +#define CP_NON_PREFETCH_CNTRS__IB1_COUNTER_MASK 0x00000007L +#define CP_NON_PREFETCH_CNTRS__IB2_COUNTER_MASK 0x00000700L + +// CP_STQ_ST_STAT +#define CP_STQ_ST_STAT__STQ_RPTR_ST_MASK 0x0000007fL +#define CP_STQ_ST_STAT__STQ_WPTR_ST_MASK 0x007f0000L + +// CP_MEQ_STAT +#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x000003ffL +#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x03ff0000L + +// CP_MIU_TAG_STAT +#define CP_MIU_TAG_STAT__TAG_0_STAT_MASK 0x00000001L +#define CP_MIU_TAG_STAT__TAG_0_STAT 0x00000001L +#define CP_MIU_TAG_STAT__TAG_1_STAT_MASK 0x00000002L +#define CP_MIU_TAG_STAT__TAG_1_STAT 0x00000002L +#define CP_MIU_TAG_STAT__TAG_2_STAT_MASK 0x00000004L +#define CP_MIU_TAG_STAT__TAG_2_STAT 0x00000004L +#define CP_MIU_TAG_STAT__TAG_3_STAT_MASK 0x00000008L +#define CP_MIU_TAG_STAT__TAG_3_STAT 0x00000008L +#define CP_MIU_TAG_STAT__TAG_4_STAT_MASK 0x00000010L +#define CP_MIU_TAG_STAT__TAG_4_STAT 0x00000010L +#define CP_MIU_TAG_STAT__TAG_5_STAT_MASK 0x00000020L +#define CP_MIU_TAG_STAT__TAG_5_STAT 0x00000020L +#define CP_MIU_TAG_STAT__TAG_6_STAT_MASK 0x00000040L +#define CP_MIU_TAG_STAT__TAG_6_STAT 0x00000040L +#define CP_MIU_TAG_STAT__TAG_7_STAT_MASK 0x00000080L +#define CP_MIU_TAG_STAT__TAG_7_STAT 0x00000080L +#define CP_MIU_TAG_STAT__TAG_8_STAT_MASK 0x00000100L +#define CP_MIU_TAG_STAT__TAG_8_STAT 0x00000100L +#define CP_MIU_TAG_STAT__TAG_9_STAT_MASK 0x00000200L +#define CP_MIU_TAG_STAT__TAG_9_STAT 0x00000200L +#define CP_MIU_TAG_STAT__TAG_10_STAT_MASK 0x00000400L +#define CP_MIU_TAG_STAT__TAG_10_STAT 0x00000400L +#define CP_MIU_TAG_STAT__TAG_11_STAT_MASK 0x00000800L +#define CP_MIU_TAG_STAT__TAG_11_STAT 0x00000800L +#define CP_MIU_TAG_STAT__TAG_12_STAT_MASK 0x00001000L +#define CP_MIU_TAG_STAT__TAG_12_STAT 0x00001000L +#define CP_MIU_TAG_STAT__TAG_13_STAT_MASK 0x00002000L +#define CP_MIU_TAG_STAT__TAG_13_STAT 0x00002000L +#define CP_MIU_TAG_STAT__TAG_14_STAT_MASK 0x00004000L +#define CP_MIU_TAG_STAT__TAG_14_STAT 0x00004000L +#define CP_MIU_TAG_STAT__TAG_15_STAT_MASK 0x00008000L +#define CP_MIU_TAG_STAT__TAG_15_STAT 0x00008000L +#define CP_MIU_TAG_STAT__TAG_16_STAT_MASK 0x00010000L +#define CP_MIU_TAG_STAT__TAG_16_STAT 0x00010000L +#define CP_MIU_TAG_STAT__TAG_17_STAT_MASK 0x00020000L +#define CP_MIU_TAG_STAT__TAG_17_STAT 0x00020000L +#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG_MASK 0x80000000L +#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG 0x80000000L + +// CP_CMD_INDEX +#define CP_CMD_INDEX__CMD_INDEX_MASK 0x0000007fL +#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x00030000L + +// CP_CMD_DATA +#define CP_CMD_DATA__CMD_DATA_MASK 0xffffffffL + +// CP_ME_CNTL +#define CP_ME_CNTL__ME_STATMUX_MASK 0x0000ffffL +#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY_MASK 0x02000000L +#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY 0x02000000L +#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY_MASK 0x04000000L +#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY 0x04000000L +#define CP_ME_CNTL__ME_HALT_MASK 0x10000000L +#define CP_ME_CNTL__ME_HALT 0x10000000L +#define CP_ME_CNTL__ME_BUSY_MASK 0x20000000L +#define CP_ME_CNTL__ME_BUSY 0x20000000L +#define CP_ME_CNTL__PROG_CNT_SIZE_MASK 0x80000000L +#define CP_ME_CNTL__PROG_CNT_SIZE 0x80000000L + +// CP_ME_STATUS +#define CP_ME_STATUS__ME_DEBUG_DATA_MASK 0xffffffffL + +// CP_ME_RAM_WADDR +#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x000003ffL + +// CP_ME_RAM_RADDR +#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x000003ffL + +// CP_ME_RAM_DATA +#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xffffffffL + +// CP_ME_RDADDR +#define CP_ME_RDADDR__ME_RDADDR_MASK 0xffffffffL + +// CP_DEBUG +#define CP_DEBUG__CP_DEBUG_UNUSED_22_to_0_MASK 0x007fffffL +#define CP_DEBUG__PREDICATE_DISABLE_MASK 0x00800000L +#define CP_DEBUG__PREDICATE_DISABLE 0x00800000L +#define CP_DEBUG__PROG_END_PTR_ENABLE_MASK 0x01000000L +#define CP_DEBUG__PROG_END_PTR_ENABLE 0x01000000L +#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE_MASK 0x02000000L +#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE 0x02000000L +#define CP_DEBUG__PREFETCH_PASS_NOPS_MASK 0x04000000L +#define CP_DEBUG__PREFETCH_PASS_NOPS 0x04000000L +#define CP_DEBUG__DYNAMIC_CLK_DISABLE_MASK 0x08000000L +#define CP_DEBUG__DYNAMIC_CLK_DISABLE 0x08000000L +#define CP_DEBUG__PREFETCH_MATCH_DISABLE_MASK 0x10000000L +#define CP_DEBUG__PREFETCH_MATCH_DISABLE 0x10000000L +#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL_MASK 0x40000000L +#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL 0x40000000L +#define CP_DEBUG__MIU_WRITE_PACK_DISABLE_MASK 0x80000000L +#define CP_DEBUG__MIU_WRITE_PACK_DISABLE 0x80000000L + +// SCRATCH_REG0 +#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffffL +#define GUI_SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffffL + +// SCRATCH_REG1 +#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffffL +#define GUI_SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffffL + +// SCRATCH_REG2 +#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffffL +#define GUI_SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffffL + +// SCRATCH_REG3 +#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffffL +#define GUI_SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffffL + +// SCRATCH_REG4 +#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffffL +#define GUI_SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffffL + +// SCRATCH_REG5 +#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffffL +#define GUI_SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffffL + +// SCRATCH_REG6 +#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffffL +#define GUI_SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffffL + +// SCRATCH_REG7 +#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffffL +#define GUI_SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffffL + +// SCRATCH_UMSK +#define SCRATCH_UMSK__SCRATCH_UMSK_MASK 0x000000ffL +#define SCRATCH_UMSK__SCRATCH_SWAP_MASK 0x00030000L + +// SCRATCH_ADDR +#define SCRATCH_ADDR__SCRATCH_ADDR_MASK 0xffffffe0L + +// CP_ME_VS_EVENT_SRC +#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM_MASK 0x00000001L +#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM 0x00000001L +#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR_MASK 0x00000002L +#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR 0x00000002L + +// CP_ME_VS_EVENT_ADDR +#define CP_ME_VS_EVENT_ADDR__VS_DONE_SWAP_MASK 0x00000003L +#define CP_ME_VS_EVENT_ADDR__VS_DONE_ADDR_MASK 0xfffffffcL + +// CP_ME_VS_EVENT_DATA +#define CP_ME_VS_EVENT_DATA__VS_DONE_DATA_MASK 0xffffffffL + +// CP_ME_VS_EVENT_ADDR_SWM +#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_SWAP_SWM_MASK 0x00000003L +#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_ADDR_SWM_MASK 0xfffffffcL + +// CP_ME_VS_EVENT_DATA_SWM +#define CP_ME_VS_EVENT_DATA_SWM__VS_DONE_DATA_SWM_MASK 0xffffffffL + +// CP_ME_PS_EVENT_SRC +#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM_MASK 0x00000001L +#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM 0x00000001L +#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR_MASK 0x00000002L +#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR 0x00000002L + +// CP_ME_PS_EVENT_ADDR +#define CP_ME_PS_EVENT_ADDR__PS_DONE_SWAP_MASK 0x00000003L +#define CP_ME_PS_EVENT_ADDR__PS_DONE_ADDR_MASK 0xfffffffcL + +// CP_ME_PS_EVENT_DATA +#define CP_ME_PS_EVENT_DATA__PS_DONE_DATA_MASK 0xffffffffL + +// CP_ME_PS_EVENT_ADDR_SWM +#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_SWAP_SWM_MASK 0x00000003L +#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_ADDR_SWM_MASK 0xfffffffcL + +// CP_ME_PS_EVENT_DATA_SWM +#define CP_ME_PS_EVENT_DATA_SWM__PS_DONE_DATA_SWM_MASK 0xffffffffL + +// CP_ME_CF_EVENT_SRC +#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC_MASK 0x00000001L +#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC 0x00000001L + +// CP_ME_CF_EVENT_ADDR +#define CP_ME_CF_EVENT_ADDR__CF_DONE_SWAP_MASK 0x00000003L +#define CP_ME_CF_EVENT_ADDR__CF_DONE_ADDR_MASK 0xfffffffcL + +// CP_ME_CF_EVENT_DATA +#define CP_ME_CF_EVENT_DATA__CF_DONE_DATA_MASK 0xffffffffL + +// CP_ME_NRT_ADDR +#define CP_ME_NRT_ADDR__NRT_WRITE_SWAP_MASK 0x00000003L +#define CP_ME_NRT_ADDR__NRT_WRITE_ADDR_MASK 0xfffffffcL + +// CP_ME_NRT_DATA +#define CP_ME_NRT_DATA__NRT_WRITE_DATA_MASK 0xffffffffL + +// CP_ME_VS_FETCH_DONE_SRC +#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR_MASK 0x00000001L +#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR 0x00000001L + +// CP_ME_VS_FETCH_DONE_ADDR +#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_SWAP_MASK 0x00000003L +#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_ADDR_MASK 0xfffffffcL + +// CP_ME_VS_FETCH_DONE_DATA +#define CP_ME_VS_FETCH_DONE_DATA__VS_FETCH_DONE_DATA_MASK 0xffffffffL + +// CP_INT_CNTL +#define CP_INT_CNTL__SW_INT_MASK_MASK 0x00080000L +#define CP_INT_CNTL__SW_INT_MASK 0x00080000L +#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK_MASK 0x00800000L +#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK 0x00800000L +#define CP_INT_CNTL__OPCODE_ERROR_MASK_MASK 0x01000000L +#define CP_INT_CNTL__OPCODE_ERROR_MASK 0x01000000L +#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK_MASK 0x02000000L +#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK 0x02000000L +#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK_MASK 0x04000000L +#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK 0x04000000L +#define CP_INT_CNTL__IB_ERROR_MASK_MASK 0x08000000L +#define CP_INT_CNTL__IB_ERROR_MASK 0x08000000L +#define CP_INT_CNTL__IB2_INT_MASK_MASK 0x20000000L +#define CP_INT_CNTL__IB2_INT_MASK 0x20000000L +#define CP_INT_CNTL__IB1_INT_MASK_MASK 0x40000000L +#define CP_INT_CNTL__IB1_INT_MASK 0x40000000L +#define CP_INT_CNTL__RB_INT_MASK_MASK 0x80000000L +#define CP_INT_CNTL__RB_INT_MASK 0x80000000L + +// CP_INT_STATUS +#define CP_INT_STATUS__SW_INT_STAT_MASK 0x00080000L +#define CP_INT_STATUS__SW_INT_STAT 0x00080000L +#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT_MASK 0x00800000L +#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT 0x00800000L +#define CP_INT_STATUS__OPCODE_ERROR_STAT_MASK 0x01000000L +#define CP_INT_STATUS__OPCODE_ERROR_STAT 0x01000000L +#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT_MASK 0x02000000L +#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT 0x02000000L +#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT_MASK 0x04000000L +#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT 0x04000000L +#define CP_INT_STATUS__IB_ERROR_STAT_MASK 0x08000000L +#define CP_INT_STATUS__IB_ERROR_STAT 0x08000000L +#define CP_INT_STATUS__IB2_INT_STAT_MASK 0x20000000L +#define CP_INT_STATUS__IB2_INT_STAT 0x20000000L +#define CP_INT_STATUS__IB1_INT_STAT_MASK 0x40000000L +#define CP_INT_STATUS__IB1_INT_STAT 0x40000000L +#define CP_INT_STATUS__RB_INT_STAT_MASK 0x80000000L +#define CP_INT_STATUS__RB_INT_STAT 0x80000000L + +// CP_INT_ACK +#define CP_INT_ACK__SW_INT_ACK_MASK 0x00080000L +#define CP_INT_ACK__SW_INT_ACK 0x00080000L +#define CP_INT_ACK__T0_PACKET_IN_IB_ACK_MASK 0x00800000L +#define CP_INT_ACK__T0_PACKET_IN_IB_ACK 0x00800000L +#define CP_INT_ACK__OPCODE_ERROR_ACK_MASK 0x01000000L +#define CP_INT_ACK__OPCODE_ERROR_ACK 0x01000000L +#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK_MASK 0x02000000L +#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK 0x02000000L +#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK_MASK 0x04000000L +#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK 0x04000000L +#define CP_INT_ACK__IB_ERROR_ACK_MASK 0x08000000L +#define CP_INT_ACK__IB_ERROR_ACK 0x08000000L +#define CP_INT_ACK__IB2_INT_ACK_MASK 0x20000000L +#define CP_INT_ACK__IB2_INT_ACK 0x20000000L +#define CP_INT_ACK__IB1_INT_ACK_MASK 0x40000000L +#define CP_INT_ACK__IB1_INT_ACK 0x40000000L +#define CP_INT_ACK__RB_INT_ACK_MASK 0x80000000L +#define CP_INT_ACK__RB_INT_ACK 0x80000000L + +// CP_PFP_UCODE_ADDR +#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x000001ffL + +// CP_PFP_UCODE_DATA +#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0x00ffffffL + +// CP_PERFMON_CNTL +#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000fL +#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L + +// CP_PERFCOUNTER_SELECT +#define CP_PERFCOUNTER_SELECT__PERFCOUNT_SEL_MASK 0x0000003fL + +// CP_PERFCOUNTER_LO +#define CP_PERFCOUNTER_LO__PERFCOUNT_LO_MASK 0xffffffffL + +// CP_PERFCOUNTER_HI +#define CP_PERFCOUNTER_HI__PERFCOUNT_HI_MASK 0x0000ffffL + +// CP_BIN_MASK_LO +#define CP_BIN_MASK_LO__BIN_MASK_LO_MASK 0xffffffffL + +// CP_BIN_MASK_HI +#define CP_BIN_MASK_HI__BIN_MASK_HI_MASK 0xffffffffL + +// CP_BIN_SELECT_LO +#define CP_BIN_SELECT_LO__BIN_SELECT_LO_MASK 0xffffffffL + +// CP_BIN_SELECT_HI +#define CP_BIN_SELECT_HI__BIN_SELECT_HI_MASK 0xffffffffL + +// CP_NV_FLAGS_0 +#define CP_NV_FLAGS_0__DISCARD_0_MASK 0x00000001L +#define CP_NV_FLAGS_0__DISCARD_0 0x00000001L +#define CP_NV_FLAGS_0__END_RCVD_0_MASK 0x00000002L +#define CP_NV_FLAGS_0__END_RCVD_0 0x00000002L +#define CP_NV_FLAGS_0__DISCARD_1_MASK 0x00000004L +#define CP_NV_FLAGS_0__DISCARD_1 0x00000004L +#define CP_NV_FLAGS_0__END_RCVD_1_MASK 0x00000008L +#define CP_NV_FLAGS_0__END_RCVD_1 0x00000008L +#define CP_NV_FLAGS_0__DISCARD_2_MASK 0x00000010L +#define CP_NV_FLAGS_0__DISCARD_2 0x00000010L +#define CP_NV_FLAGS_0__END_RCVD_2_MASK 0x00000020L +#define CP_NV_FLAGS_0__END_RCVD_2 0x00000020L +#define CP_NV_FLAGS_0__DISCARD_3_MASK 0x00000040L +#define CP_NV_FLAGS_0__DISCARD_3 0x00000040L +#define CP_NV_FLAGS_0__END_RCVD_3_MASK 0x00000080L +#define CP_NV_FLAGS_0__END_RCVD_3 0x00000080L +#define CP_NV_FLAGS_0__DISCARD_4_MASK 0x00000100L +#define CP_NV_FLAGS_0__DISCARD_4 0x00000100L +#define CP_NV_FLAGS_0__END_RCVD_4_MASK 0x00000200L +#define CP_NV_FLAGS_0__END_RCVD_4 0x00000200L +#define CP_NV_FLAGS_0__DISCARD_5_MASK 0x00000400L +#define CP_NV_FLAGS_0__DISCARD_5 0x00000400L +#define CP_NV_FLAGS_0__END_RCVD_5_MASK 0x00000800L +#define CP_NV_FLAGS_0__END_RCVD_5 0x00000800L +#define CP_NV_FLAGS_0__DISCARD_6_MASK 0x00001000L +#define CP_NV_FLAGS_0__DISCARD_6 0x00001000L +#define CP_NV_FLAGS_0__END_RCVD_6_MASK 0x00002000L +#define CP_NV_FLAGS_0__END_RCVD_6 0x00002000L +#define CP_NV_FLAGS_0__DISCARD_7_MASK 0x00004000L +#define CP_NV_FLAGS_0__DISCARD_7 0x00004000L +#define CP_NV_FLAGS_0__END_RCVD_7_MASK 0x00008000L +#define CP_NV_FLAGS_0__END_RCVD_7 0x00008000L +#define CP_NV_FLAGS_0__DISCARD_8_MASK 0x00010000L +#define CP_NV_FLAGS_0__DISCARD_8 0x00010000L +#define CP_NV_FLAGS_0__END_RCVD_8_MASK 0x00020000L +#define CP_NV_FLAGS_0__END_RCVD_8 0x00020000L +#define CP_NV_FLAGS_0__DISCARD_9_MASK 0x00040000L +#define CP_NV_FLAGS_0__DISCARD_9 0x00040000L +#define CP_NV_FLAGS_0__END_RCVD_9_MASK 0x00080000L +#define CP_NV_FLAGS_0__END_RCVD_9 0x00080000L +#define CP_NV_FLAGS_0__DISCARD_10_MASK 0x00100000L +#define CP_NV_FLAGS_0__DISCARD_10 0x00100000L +#define CP_NV_FLAGS_0__END_RCVD_10_MASK 0x00200000L +#define CP_NV_FLAGS_0__END_RCVD_10 0x00200000L +#define CP_NV_FLAGS_0__DISCARD_11_MASK 0x00400000L +#define CP_NV_FLAGS_0__DISCARD_11 0x00400000L +#define CP_NV_FLAGS_0__END_RCVD_11_MASK 0x00800000L +#define CP_NV_FLAGS_0__END_RCVD_11 0x00800000L +#define CP_NV_FLAGS_0__DISCARD_12_MASK 0x01000000L +#define CP_NV_FLAGS_0__DISCARD_12 0x01000000L +#define CP_NV_FLAGS_0__END_RCVD_12_MASK 0x02000000L +#define CP_NV_FLAGS_0__END_RCVD_12 0x02000000L +#define CP_NV_FLAGS_0__DISCARD_13_MASK 0x04000000L +#define CP_NV_FLAGS_0__DISCARD_13 0x04000000L +#define CP_NV_FLAGS_0__END_RCVD_13_MASK 0x08000000L +#define CP_NV_FLAGS_0__END_RCVD_13 0x08000000L +#define CP_NV_FLAGS_0__DISCARD_14_MASK 0x10000000L +#define CP_NV_FLAGS_0__DISCARD_14 0x10000000L +#define CP_NV_FLAGS_0__END_RCVD_14_MASK 0x20000000L +#define CP_NV_FLAGS_0__END_RCVD_14 0x20000000L +#define CP_NV_FLAGS_0__DISCARD_15_MASK 0x40000000L +#define CP_NV_FLAGS_0__DISCARD_15 0x40000000L +#define CP_NV_FLAGS_0__END_RCVD_15_MASK 0x80000000L +#define CP_NV_FLAGS_0__END_RCVD_15 0x80000000L + +// CP_NV_FLAGS_1 +#define CP_NV_FLAGS_1__DISCARD_16_MASK 0x00000001L +#define CP_NV_FLAGS_1__DISCARD_16 0x00000001L +#define CP_NV_FLAGS_1__END_RCVD_16_MASK 0x00000002L +#define CP_NV_FLAGS_1__END_RCVD_16 0x00000002L +#define CP_NV_FLAGS_1__DISCARD_17_MASK 0x00000004L +#define CP_NV_FLAGS_1__DISCARD_17 0x00000004L +#define CP_NV_FLAGS_1__END_RCVD_17_MASK 0x00000008L +#define CP_NV_FLAGS_1__END_RCVD_17 0x00000008L +#define CP_NV_FLAGS_1__DISCARD_18_MASK 0x00000010L +#define CP_NV_FLAGS_1__DISCARD_18 0x00000010L +#define CP_NV_FLAGS_1__END_RCVD_18_MASK 0x00000020L +#define CP_NV_FLAGS_1__END_RCVD_18 0x00000020L +#define CP_NV_FLAGS_1__DISCARD_19_MASK 0x00000040L +#define CP_NV_FLAGS_1__DISCARD_19 0x00000040L +#define CP_NV_FLAGS_1__END_RCVD_19_MASK 0x00000080L +#define CP_NV_FLAGS_1__END_RCVD_19 0x00000080L +#define CP_NV_FLAGS_1__DISCARD_20_MASK 0x00000100L +#define CP_NV_FLAGS_1__DISCARD_20 0x00000100L +#define CP_NV_FLAGS_1__END_RCVD_20_MASK 0x00000200L +#define CP_NV_FLAGS_1__END_RCVD_20 0x00000200L +#define CP_NV_FLAGS_1__DISCARD_21_MASK 0x00000400L +#define CP_NV_FLAGS_1__DISCARD_21 0x00000400L +#define CP_NV_FLAGS_1__END_RCVD_21_MASK 0x00000800L +#define CP_NV_FLAGS_1__END_RCVD_21 0x00000800L +#define CP_NV_FLAGS_1__DISCARD_22_MASK 0x00001000L +#define CP_NV_FLAGS_1__DISCARD_22 0x00001000L +#define CP_NV_FLAGS_1__END_RCVD_22_MASK 0x00002000L +#define CP_NV_FLAGS_1__END_RCVD_22 0x00002000L +#define CP_NV_FLAGS_1__DISCARD_23_MASK 0x00004000L +#define CP_NV_FLAGS_1__DISCARD_23 0x00004000L +#define CP_NV_FLAGS_1__END_RCVD_23_MASK 0x00008000L +#define CP_NV_FLAGS_1__END_RCVD_23 0x00008000L +#define CP_NV_FLAGS_1__DISCARD_24_MASK 0x00010000L +#define CP_NV_FLAGS_1__DISCARD_24 0x00010000L +#define CP_NV_FLAGS_1__END_RCVD_24_MASK 0x00020000L +#define CP_NV_FLAGS_1__END_RCVD_24 0x00020000L +#define CP_NV_FLAGS_1__DISCARD_25_MASK 0x00040000L +#define CP_NV_FLAGS_1__DISCARD_25 0x00040000L +#define CP_NV_FLAGS_1__END_RCVD_25_MASK 0x00080000L +#define CP_NV_FLAGS_1__END_RCVD_25 0x00080000L +#define CP_NV_FLAGS_1__DISCARD_26_MASK 0x00100000L +#define CP_NV_FLAGS_1__DISCARD_26 0x00100000L +#define CP_NV_FLAGS_1__END_RCVD_26_MASK 0x00200000L +#define CP_NV_FLAGS_1__END_RCVD_26 0x00200000L +#define CP_NV_FLAGS_1__DISCARD_27_MASK 0x00400000L +#define CP_NV_FLAGS_1__DISCARD_27 0x00400000L +#define CP_NV_FLAGS_1__END_RCVD_27_MASK 0x00800000L +#define CP_NV_FLAGS_1__END_RCVD_27 0x00800000L +#define CP_NV_FLAGS_1__DISCARD_28_MASK 0x01000000L +#define CP_NV_FLAGS_1__DISCARD_28 0x01000000L +#define CP_NV_FLAGS_1__END_RCVD_28_MASK 0x02000000L +#define CP_NV_FLAGS_1__END_RCVD_28 0x02000000L +#define CP_NV_FLAGS_1__DISCARD_29_MASK 0x04000000L +#define CP_NV_FLAGS_1__DISCARD_29 0x04000000L +#define CP_NV_FLAGS_1__END_RCVD_29_MASK 0x08000000L +#define CP_NV_FLAGS_1__END_RCVD_29 0x08000000L +#define CP_NV_FLAGS_1__DISCARD_30_MASK 0x10000000L +#define CP_NV_FLAGS_1__DISCARD_30 0x10000000L +#define CP_NV_FLAGS_1__END_RCVD_30_MASK 0x20000000L +#define CP_NV_FLAGS_1__END_RCVD_30 0x20000000L +#define CP_NV_FLAGS_1__DISCARD_31_MASK 0x40000000L +#define CP_NV_FLAGS_1__DISCARD_31 0x40000000L +#define CP_NV_FLAGS_1__END_RCVD_31_MASK 0x80000000L +#define CP_NV_FLAGS_1__END_RCVD_31 0x80000000L + +// CP_NV_FLAGS_2 +#define CP_NV_FLAGS_2__DISCARD_32_MASK 0x00000001L +#define CP_NV_FLAGS_2__DISCARD_32 0x00000001L +#define CP_NV_FLAGS_2__END_RCVD_32_MASK 0x00000002L +#define CP_NV_FLAGS_2__END_RCVD_32 0x00000002L +#define CP_NV_FLAGS_2__DISCARD_33_MASK 0x00000004L +#define CP_NV_FLAGS_2__DISCARD_33 0x00000004L +#define CP_NV_FLAGS_2__END_RCVD_33_MASK 0x00000008L +#define CP_NV_FLAGS_2__END_RCVD_33 0x00000008L +#define CP_NV_FLAGS_2__DISCARD_34_MASK 0x00000010L +#define CP_NV_FLAGS_2__DISCARD_34 0x00000010L +#define CP_NV_FLAGS_2__END_RCVD_34_MASK 0x00000020L +#define CP_NV_FLAGS_2__END_RCVD_34 0x00000020L +#define CP_NV_FLAGS_2__DISCARD_35_MASK 0x00000040L +#define CP_NV_FLAGS_2__DISCARD_35 0x00000040L +#define CP_NV_FLAGS_2__END_RCVD_35_MASK 0x00000080L +#define CP_NV_FLAGS_2__END_RCVD_35 0x00000080L +#define CP_NV_FLAGS_2__DISCARD_36_MASK 0x00000100L +#define CP_NV_FLAGS_2__DISCARD_36 0x00000100L +#define CP_NV_FLAGS_2__END_RCVD_36_MASK 0x00000200L +#define CP_NV_FLAGS_2__END_RCVD_36 0x00000200L +#define CP_NV_FLAGS_2__DISCARD_37_MASK 0x00000400L +#define CP_NV_FLAGS_2__DISCARD_37 0x00000400L +#define CP_NV_FLAGS_2__END_RCVD_37_MASK 0x00000800L +#define CP_NV_FLAGS_2__END_RCVD_37 0x00000800L +#define CP_NV_FLAGS_2__DISCARD_38_MASK 0x00001000L +#define CP_NV_FLAGS_2__DISCARD_38 0x00001000L +#define CP_NV_FLAGS_2__END_RCVD_38_MASK 0x00002000L +#define CP_NV_FLAGS_2__END_RCVD_38 0x00002000L +#define CP_NV_FLAGS_2__DISCARD_39_MASK 0x00004000L +#define CP_NV_FLAGS_2__DISCARD_39 0x00004000L +#define CP_NV_FLAGS_2__END_RCVD_39_MASK 0x00008000L +#define CP_NV_FLAGS_2__END_RCVD_39 0x00008000L +#define CP_NV_FLAGS_2__DISCARD_40_MASK 0x00010000L +#define CP_NV_FLAGS_2__DISCARD_40 0x00010000L +#define CP_NV_FLAGS_2__END_RCVD_40_MASK 0x00020000L +#define CP_NV_FLAGS_2__END_RCVD_40 0x00020000L +#define CP_NV_FLAGS_2__DISCARD_41_MASK 0x00040000L +#define CP_NV_FLAGS_2__DISCARD_41 0x00040000L +#define CP_NV_FLAGS_2__END_RCVD_41_MASK 0x00080000L +#define CP_NV_FLAGS_2__END_RCVD_41 0x00080000L +#define CP_NV_FLAGS_2__DISCARD_42_MASK 0x00100000L +#define CP_NV_FLAGS_2__DISCARD_42 0x00100000L +#define CP_NV_FLAGS_2__END_RCVD_42_MASK 0x00200000L +#define CP_NV_FLAGS_2__END_RCVD_42 0x00200000L +#define CP_NV_FLAGS_2__DISCARD_43_MASK 0x00400000L +#define CP_NV_FLAGS_2__DISCARD_43 0x00400000L +#define CP_NV_FLAGS_2__END_RCVD_43_MASK 0x00800000L +#define CP_NV_FLAGS_2__END_RCVD_43 0x00800000L +#define CP_NV_FLAGS_2__DISCARD_44_MASK 0x01000000L +#define CP_NV_FLAGS_2__DISCARD_44 0x01000000L +#define CP_NV_FLAGS_2__END_RCVD_44_MASK 0x02000000L +#define CP_NV_FLAGS_2__END_RCVD_44 0x02000000L +#define CP_NV_FLAGS_2__DISCARD_45_MASK 0x04000000L +#define CP_NV_FLAGS_2__DISCARD_45 0x04000000L +#define CP_NV_FLAGS_2__END_RCVD_45_MASK 0x08000000L +#define CP_NV_FLAGS_2__END_RCVD_45 0x08000000L +#define CP_NV_FLAGS_2__DISCARD_46_MASK 0x10000000L +#define CP_NV_FLAGS_2__DISCARD_46 0x10000000L +#define CP_NV_FLAGS_2__END_RCVD_46_MASK 0x20000000L +#define CP_NV_FLAGS_2__END_RCVD_46 0x20000000L +#define CP_NV_FLAGS_2__DISCARD_47_MASK 0x40000000L +#define CP_NV_FLAGS_2__DISCARD_47 0x40000000L +#define CP_NV_FLAGS_2__END_RCVD_47_MASK 0x80000000L +#define CP_NV_FLAGS_2__END_RCVD_47 0x80000000L + +// CP_NV_FLAGS_3 +#define CP_NV_FLAGS_3__DISCARD_48_MASK 0x00000001L +#define CP_NV_FLAGS_3__DISCARD_48 0x00000001L +#define CP_NV_FLAGS_3__END_RCVD_48_MASK 0x00000002L +#define CP_NV_FLAGS_3__END_RCVD_48 0x00000002L +#define CP_NV_FLAGS_3__DISCARD_49_MASK 0x00000004L +#define CP_NV_FLAGS_3__DISCARD_49 0x00000004L +#define CP_NV_FLAGS_3__END_RCVD_49_MASK 0x00000008L +#define CP_NV_FLAGS_3__END_RCVD_49 0x00000008L +#define CP_NV_FLAGS_3__DISCARD_50_MASK 0x00000010L +#define CP_NV_FLAGS_3__DISCARD_50 0x00000010L +#define CP_NV_FLAGS_3__END_RCVD_50_MASK 0x00000020L +#define CP_NV_FLAGS_3__END_RCVD_50 0x00000020L +#define CP_NV_FLAGS_3__DISCARD_51_MASK 0x00000040L +#define CP_NV_FLAGS_3__DISCARD_51 0x00000040L +#define CP_NV_FLAGS_3__END_RCVD_51_MASK 0x00000080L +#define CP_NV_FLAGS_3__END_RCVD_51 0x00000080L +#define CP_NV_FLAGS_3__DISCARD_52_MASK 0x00000100L +#define CP_NV_FLAGS_3__DISCARD_52 0x00000100L +#define CP_NV_FLAGS_3__END_RCVD_52_MASK 0x00000200L +#define CP_NV_FLAGS_3__END_RCVD_52 0x00000200L +#define CP_NV_FLAGS_3__DISCARD_53_MASK 0x00000400L +#define CP_NV_FLAGS_3__DISCARD_53 0x00000400L +#define CP_NV_FLAGS_3__END_RCVD_53_MASK 0x00000800L +#define CP_NV_FLAGS_3__END_RCVD_53 0x00000800L +#define CP_NV_FLAGS_3__DISCARD_54_MASK 0x00001000L +#define CP_NV_FLAGS_3__DISCARD_54 0x00001000L +#define CP_NV_FLAGS_3__END_RCVD_54_MASK 0x00002000L +#define CP_NV_FLAGS_3__END_RCVD_54 0x00002000L +#define CP_NV_FLAGS_3__DISCARD_55_MASK 0x00004000L +#define CP_NV_FLAGS_3__DISCARD_55 0x00004000L +#define CP_NV_FLAGS_3__END_RCVD_55_MASK 0x00008000L +#define CP_NV_FLAGS_3__END_RCVD_55 0x00008000L +#define CP_NV_FLAGS_3__DISCARD_56_MASK 0x00010000L +#define CP_NV_FLAGS_3__DISCARD_56 0x00010000L +#define CP_NV_FLAGS_3__END_RCVD_56_MASK 0x00020000L +#define CP_NV_FLAGS_3__END_RCVD_56 0x00020000L +#define CP_NV_FLAGS_3__DISCARD_57_MASK 0x00040000L +#define CP_NV_FLAGS_3__DISCARD_57 0x00040000L +#define CP_NV_FLAGS_3__END_RCVD_57_MASK 0x00080000L +#define CP_NV_FLAGS_3__END_RCVD_57 0x00080000L +#define CP_NV_FLAGS_3__DISCARD_58_MASK 0x00100000L +#define CP_NV_FLAGS_3__DISCARD_58 0x00100000L +#define CP_NV_FLAGS_3__END_RCVD_58_MASK 0x00200000L +#define CP_NV_FLAGS_3__END_RCVD_58 0x00200000L +#define CP_NV_FLAGS_3__DISCARD_59_MASK 0x00400000L +#define CP_NV_FLAGS_3__DISCARD_59 0x00400000L +#define CP_NV_FLAGS_3__END_RCVD_59_MASK 0x00800000L +#define CP_NV_FLAGS_3__END_RCVD_59 0x00800000L +#define CP_NV_FLAGS_3__DISCARD_60_MASK 0x01000000L +#define CP_NV_FLAGS_3__DISCARD_60 0x01000000L +#define CP_NV_FLAGS_3__END_RCVD_60_MASK 0x02000000L +#define CP_NV_FLAGS_3__END_RCVD_60 0x02000000L +#define CP_NV_FLAGS_3__DISCARD_61_MASK 0x04000000L +#define CP_NV_FLAGS_3__DISCARD_61 0x04000000L +#define CP_NV_FLAGS_3__END_RCVD_61_MASK 0x08000000L +#define CP_NV_FLAGS_3__END_RCVD_61 0x08000000L +#define CP_NV_FLAGS_3__DISCARD_62_MASK 0x10000000L +#define CP_NV_FLAGS_3__DISCARD_62 0x10000000L +#define CP_NV_FLAGS_3__END_RCVD_62_MASK 0x20000000L +#define CP_NV_FLAGS_3__END_RCVD_62 0x20000000L +#define CP_NV_FLAGS_3__DISCARD_63_MASK 0x40000000L +#define CP_NV_FLAGS_3__DISCARD_63 0x40000000L +#define CP_NV_FLAGS_3__END_RCVD_63_MASK 0x80000000L +#define CP_NV_FLAGS_3__END_RCVD_63 0x80000000L + +// CP_STATE_DEBUG_INDEX +#define CP_STATE_DEBUG_INDEX__STATE_DEBUG_INDEX_MASK 0x0000001fL + +// CP_STATE_DEBUG_DATA +#define CP_STATE_DEBUG_DATA__STATE_DEBUG_DATA_MASK 0xffffffffL + +// CP_PROG_COUNTER +#define CP_PROG_COUNTER__COUNTER_MASK 0xffffffffL + +// CP_STAT +#define CP_STAT__MIU_WR_BUSY_MASK 0x00000001L +#define CP_STAT__MIU_WR_BUSY 0x00000001L +#define CP_STAT__MIU_RD_REQ_BUSY_MASK 0x00000002L +#define CP_STAT__MIU_RD_REQ_BUSY 0x00000002L +#define CP_STAT__MIU_RD_RETURN_BUSY_MASK 0x00000004L +#define CP_STAT__MIU_RD_RETURN_BUSY 0x00000004L +#define CP_STAT__RBIU_BUSY_MASK 0x00000008L +#define CP_STAT__RBIU_BUSY 0x00000008L +#define CP_STAT__RCIU_BUSY_MASK 0x00000010L +#define CP_STAT__RCIU_BUSY 0x00000010L +#define CP_STAT__CSF_RING_BUSY_MASK 0x00000020L +#define CP_STAT__CSF_RING_BUSY 0x00000020L +#define CP_STAT__CSF_INDIRECTS_BUSY_MASK 0x00000040L +#define CP_STAT__CSF_INDIRECTS_BUSY 0x00000040L +#define CP_STAT__CSF_INDIRECT2_BUSY_MASK 0x00000080L +#define CP_STAT__CSF_INDIRECT2_BUSY 0x00000080L +#define CP_STAT__CSF_ST_BUSY_MASK 0x00000200L +#define CP_STAT__CSF_ST_BUSY 0x00000200L +#define CP_STAT__CSF_BUSY_MASK 0x00000400L +#define CP_STAT__CSF_BUSY 0x00000400L +#define CP_STAT__RING_QUEUE_BUSY_MASK 0x00000800L +#define CP_STAT__RING_QUEUE_BUSY 0x00000800L +#define CP_STAT__INDIRECTS_QUEUE_BUSY_MASK 0x00001000L +#define CP_STAT__INDIRECTS_QUEUE_BUSY 0x00001000L +#define CP_STAT__INDIRECT2_QUEUE_BUSY_MASK 0x00002000L +#define CP_STAT__INDIRECT2_QUEUE_BUSY 0x00002000L +#define CP_STAT__ST_QUEUE_BUSY_MASK 0x00010000L +#define CP_STAT__ST_QUEUE_BUSY 0x00010000L +#define CP_STAT__PFP_BUSY_MASK 0x00020000L +#define CP_STAT__PFP_BUSY 0x00020000L +#define CP_STAT__MEQ_RING_BUSY_MASK 0x00040000L +#define CP_STAT__MEQ_RING_BUSY 0x00040000L +#define CP_STAT__MEQ_INDIRECTS_BUSY_MASK 0x00080000L +#define CP_STAT__MEQ_INDIRECTS_BUSY 0x00080000L +#define CP_STAT__MEQ_INDIRECT2_BUSY_MASK 0x00100000L +#define CP_STAT__MEQ_INDIRECT2_BUSY 0x00100000L +#define CP_STAT__MIU_WC_STALL_MASK 0x00200000L +#define CP_STAT__MIU_WC_STALL 0x00200000L +#define CP_STAT__CP_NRT_BUSY_MASK 0x00400000L +#define CP_STAT__CP_NRT_BUSY 0x00400000L +#define CP_STAT___3D_BUSY_MASK 0x00800000L +#define CP_STAT___3D_BUSY 0x00800000L +#define CP_STAT__ME_BUSY_MASK 0x04000000L +#define CP_STAT__ME_BUSY 0x04000000L +#define CP_STAT__ME_WC_BUSY_MASK 0x20000000L +#define CP_STAT__ME_WC_BUSY 0x20000000L +#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY_MASK 0x40000000L +#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY 0x40000000L +#define CP_STAT__CP_BUSY_MASK 0x80000000L +#define CP_STAT__CP_BUSY 0x80000000L + +// BIOS_0_SCRATCH +#define BIOS_0_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_1_SCRATCH +#define BIOS_1_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_2_SCRATCH +#define BIOS_2_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_3_SCRATCH +#define BIOS_3_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_4_SCRATCH +#define BIOS_4_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_5_SCRATCH +#define BIOS_5_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_6_SCRATCH +#define BIOS_6_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_7_SCRATCH +#define BIOS_7_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_8_SCRATCH +#define BIOS_8_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_9_SCRATCH +#define BIOS_9_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_10_SCRATCH +#define BIOS_10_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_11_SCRATCH +#define BIOS_11_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_12_SCRATCH +#define BIOS_12_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_13_SCRATCH +#define BIOS_13_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_14_SCRATCH +#define BIOS_14_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// BIOS_15_SCRATCH +#define BIOS_15_SCRATCH__BIOS_SCRATCH_MASK 0xffffffffL + +// COHER_SIZE_PM4 +#define COHER_SIZE_PM4__SIZE_MASK 0xffffffffL + +// COHER_BASE_PM4 +#define COHER_BASE_PM4__BASE_MASK 0xffffffffL + +// COHER_STATUS_PM4 +#define COHER_STATUS_PM4__MATCHING_CONTEXTS_MASK 0x000000ffL +#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA_MASK 0x00000100L +#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA 0x00000100L +#define COHER_STATUS_PM4__DEST_BASE_0_ENA_MASK 0x00000200L +#define COHER_STATUS_PM4__DEST_BASE_0_ENA 0x00000200L +#define COHER_STATUS_PM4__DEST_BASE_1_ENA_MASK 0x00000400L +#define COHER_STATUS_PM4__DEST_BASE_1_ENA 0x00000400L +#define COHER_STATUS_PM4__DEST_BASE_2_ENA_MASK 0x00000800L +#define COHER_STATUS_PM4__DEST_BASE_2_ENA 0x00000800L +#define COHER_STATUS_PM4__DEST_BASE_3_ENA_MASK 0x00001000L +#define COHER_STATUS_PM4__DEST_BASE_3_ENA 0x00001000L +#define COHER_STATUS_PM4__DEST_BASE_4_ENA_MASK 0x00002000L +#define COHER_STATUS_PM4__DEST_BASE_4_ENA 0x00002000L +#define COHER_STATUS_PM4__DEST_BASE_5_ENA_MASK 0x00004000L +#define COHER_STATUS_PM4__DEST_BASE_5_ENA 0x00004000L +#define COHER_STATUS_PM4__DEST_BASE_6_ENA_MASK 0x00008000L +#define COHER_STATUS_PM4__DEST_BASE_6_ENA 0x00008000L +#define COHER_STATUS_PM4__DEST_BASE_7_ENA_MASK 0x00010000L +#define COHER_STATUS_PM4__DEST_BASE_7_ENA 0x00010000L +#define COHER_STATUS_PM4__RB_COLOR_INFO_ENA_MASK 0x00020000L +#define COHER_STATUS_PM4__RB_COLOR_INFO_ENA 0x00020000L +#define COHER_STATUS_PM4__TC_ACTION_ENA_MASK 0x02000000L +#define COHER_STATUS_PM4__TC_ACTION_ENA 0x02000000L +#define COHER_STATUS_PM4__STATUS_MASK 0x80000000L +#define COHER_STATUS_PM4__STATUS 0x80000000L + +// COHER_SIZE_HOST +#define COHER_SIZE_HOST__SIZE_MASK 0xffffffffL + +// COHER_BASE_HOST +#define COHER_BASE_HOST__BASE_MASK 0xffffffffL + +// COHER_STATUS_HOST +#define COHER_STATUS_HOST__MATCHING_CONTEXTS_MASK 0x000000ffL +#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA_MASK 0x00000100L +#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA 0x00000100L +#define COHER_STATUS_HOST__DEST_BASE_0_ENA_MASK 0x00000200L +#define COHER_STATUS_HOST__DEST_BASE_0_ENA 0x00000200L +#define COHER_STATUS_HOST__DEST_BASE_1_ENA_MASK 0x00000400L +#define COHER_STATUS_HOST__DEST_BASE_1_ENA 0x00000400L +#define COHER_STATUS_HOST__DEST_BASE_2_ENA_MASK 0x00000800L +#define COHER_STATUS_HOST__DEST_BASE_2_ENA 0x00000800L +#define COHER_STATUS_HOST__DEST_BASE_3_ENA_MASK 0x00001000L +#define COHER_STATUS_HOST__DEST_BASE_3_ENA 0x00001000L +#define COHER_STATUS_HOST__DEST_BASE_4_ENA_MASK 0x00002000L +#define COHER_STATUS_HOST__DEST_BASE_4_ENA 0x00002000L +#define COHER_STATUS_HOST__DEST_BASE_5_ENA_MASK 0x00004000L +#define COHER_STATUS_HOST__DEST_BASE_5_ENA 0x00004000L +#define COHER_STATUS_HOST__DEST_BASE_6_ENA_MASK 0x00008000L +#define COHER_STATUS_HOST__DEST_BASE_6_ENA 0x00008000L +#define COHER_STATUS_HOST__DEST_BASE_7_ENA_MASK 0x00010000L +#define COHER_STATUS_HOST__DEST_BASE_7_ENA 0x00010000L +#define COHER_STATUS_HOST__RB_COLOR_INFO_ENA_MASK 0x00020000L +#define COHER_STATUS_HOST__RB_COLOR_INFO_ENA 0x00020000L +#define COHER_STATUS_HOST__TC_ACTION_ENA_MASK 0x02000000L +#define COHER_STATUS_HOST__TC_ACTION_ENA 0x02000000L +#define COHER_STATUS_HOST__STATUS_MASK 0x80000000L +#define COHER_STATUS_HOST__STATUS 0x80000000L + +// COHER_DEST_BASE_0 +#define COHER_DEST_BASE_0__DEST_BASE_0_MASK 0xfffff000L + +// COHER_DEST_BASE_1 +#define COHER_DEST_BASE_1__DEST_BASE_1_MASK 0xfffff000L + +// COHER_DEST_BASE_2 +#define COHER_DEST_BASE_2__DEST_BASE_2_MASK 0xfffff000L + +// COHER_DEST_BASE_3 +#define COHER_DEST_BASE_3__DEST_BASE_3_MASK 0xfffff000L + +// COHER_DEST_BASE_4 +#define COHER_DEST_BASE_4__DEST_BASE_4_MASK 0xfffff000L + +// COHER_DEST_BASE_5 +#define COHER_DEST_BASE_5__DEST_BASE_5_MASK 0xfffff000L + +// COHER_DEST_BASE_6 +#define COHER_DEST_BASE_6__DEST_BASE_6_MASK 0xfffff000L + +// COHER_DEST_BASE_7 +#define COHER_DEST_BASE_7__DEST_BASE_7_MASK 0xfffff000L + +// RB_SURFACE_INFO +#define RB_SURFACE_INFO__SURFACE_PITCH_MASK 0x00003fffL +#define RB_SURFACE_INFO__MSAA_SAMPLES_MASK 0x0000c000L + +// RB_COLOR_INFO +#define RB_COLOR_INFO__COLOR_FORMAT_MASK 0x0000000fL +#define RB_COLOR_INFO__COLOR_ROUND_MODE_MASK 0x00000030L +#define RB_COLOR_INFO__COLOR_LINEAR_MASK 0x00000040L +#define RB_COLOR_INFO__COLOR_LINEAR 0x00000040L +#define RB_COLOR_INFO__COLOR_ENDIAN_MASK 0x00000180L +#define RB_COLOR_INFO__COLOR_SWAP_MASK 0x00000600L +#define RB_COLOR_INFO__COLOR_BASE_MASK 0xfffff000L + +// RB_DEPTH_INFO +#define RB_DEPTH_INFO__DEPTH_FORMAT_MASK 0x00000001L +#define RB_DEPTH_INFO__DEPTH_FORMAT 0x00000001L +#define RB_DEPTH_INFO__DEPTH_BASE_MASK 0xfffff000L + +// RB_STENCILREFMASK +#define RB_STENCILREFMASK__STENCILREF_MASK 0x000000ffL +#define RB_STENCILREFMASK__STENCILMASK_MASK 0x0000ff00L +#define RB_STENCILREFMASK__STENCILWRITEMASK_MASK 0x00ff0000L +#define RB_STENCILREFMASK__RESERVED0_MASK 0x01000000L +#define RB_STENCILREFMASK__RESERVED0 0x01000000L +#define RB_STENCILREFMASK__RESERVED1_MASK 0x02000000L +#define RB_STENCILREFMASK__RESERVED1 0x02000000L + +// RB_ALPHA_REF +#define RB_ALPHA_REF__ALPHA_REF_MASK 0xffffffffL + +// RB_COLOR_MASK +#define RB_COLOR_MASK__WRITE_RED_MASK 0x00000001L +#define RB_COLOR_MASK__WRITE_RED 0x00000001L +#define RB_COLOR_MASK__WRITE_GREEN_MASK 0x00000002L +#define RB_COLOR_MASK__WRITE_GREEN 0x00000002L +#define RB_COLOR_MASK__WRITE_BLUE_MASK 0x00000004L +#define RB_COLOR_MASK__WRITE_BLUE 0x00000004L +#define RB_COLOR_MASK__WRITE_ALPHA_MASK 0x00000008L +#define RB_COLOR_MASK__WRITE_ALPHA 0x00000008L +#define RB_COLOR_MASK__RESERVED2_MASK 0x00000010L +#define RB_COLOR_MASK__RESERVED2 0x00000010L +#define RB_COLOR_MASK__RESERVED3_MASK 0x00000020L +#define RB_COLOR_MASK__RESERVED3 0x00000020L + +// RB_BLEND_RED +#define RB_BLEND_RED__BLEND_RED_MASK 0x000000ffL + +// RB_BLEND_GREEN +#define RB_BLEND_GREEN__BLEND_GREEN_MASK 0x000000ffL + +// RB_BLEND_BLUE +#define RB_BLEND_BLUE__BLEND_BLUE_MASK 0x000000ffL + +// RB_BLEND_ALPHA +#define RB_BLEND_ALPHA__BLEND_ALPHA_MASK 0x000000ffL + +// RB_FOG_COLOR +#define RB_FOG_COLOR__FOG_RED_MASK 0x000000ffL +#define RB_FOG_COLOR__FOG_GREEN_MASK 0x0000ff00L +#define RB_FOG_COLOR__FOG_BLUE_MASK 0x00ff0000L + +// RB_STENCILREFMASK_BF +#define RB_STENCILREFMASK_BF__STENCILREF_BF_MASK 0x000000ffL +#define RB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0x0000ff00L +#define RB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0x00ff0000L +#define RB_STENCILREFMASK_BF__RESERVED4_MASK 0x01000000L +#define RB_STENCILREFMASK_BF__RESERVED4 0x01000000L +#define RB_STENCILREFMASK_BF__RESERVED5_MASK 0x02000000L +#define RB_STENCILREFMASK_BF__RESERVED5 0x02000000L + +// RB_DEPTHCONTROL +#define RB_DEPTHCONTROL__STENCIL_ENABLE_MASK 0x00000001L +#define RB_DEPTHCONTROL__STENCIL_ENABLE 0x00000001L +#define RB_DEPTHCONTROL__Z_ENABLE_MASK 0x00000002L +#define RB_DEPTHCONTROL__Z_ENABLE 0x00000002L +#define RB_DEPTHCONTROL__Z_WRITE_ENABLE_MASK 0x00000004L +#define RB_DEPTHCONTROL__Z_WRITE_ENABLE 0x00000004L +#define RB_DEPTHCONTROL__EARLY_Z_ENABLE_MASK 0x00000008L +#define RB_DEPTHCONTROL__EARLY_Z_ENABLE 0x00000008L +#define RB_DEPTHCONTROL__ZFUNC_MASK 0x00000070L +#define RB_DEPTHCONTROL__BACKFACE_ENABLE_MASK 0x00000080L +#define RB_DEPTHCONTROL__BACKFACE_ENABLE 0x00000080L +#define RB_DEPTHCONTROL__STENCILFUNC_MASK 0x00000700L +#define RB_DEPTHCONTROL__STENCILFAIL_MASK 0x00003800L +#define RB_DEPTHCONTROL__STENCILZPASS_MASK 0x0001c000L +#define RB_DEPTHCONTROL__STENCILZFAIL_MASK 0x000e0000L +#define RB_DEPTHCONTROL__STENCILFUNC_BF_MASK 0x00700000L +#define RB_DEPTHCONTROL__STENCILFAIL_BF_MASK 0x03800000L +#define RB_DEPTHCONTROL__STENCILZPASS_BF_MASK 0x1c000000L +#define RB_DEPTHCONTROL__STENCILZFAIL_BF_MASK 0xe0000000L + +// RB_BLENDCONTROL +#define RB_BLENDCONTROL__COLOR_SRCBLEND_MASK 0x0000001fL +#define RB_BLENDCONTROL__COLOR_COMB_FCN_MASK 0x000000e0L +#define RB_BLENDCONTROL__COLOR_DESTBLEND_MASK 0x00001f00L +#define RB_BLENDCONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L +#define RB_BLENDCONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L +#define RB_BLENDCONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L +#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE_MASK 0x20000000L +#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE 0x20000000L +#define RB_BLENDCONTROL__BLEND_FORCE_MASK 0x40000000L +#define RB_BLENDCONTROL__BLEND_FORCE 0x40000000L + +// RB_COLORCONTROL +#define RB_COLORCONTROL__ALPHA_FUNC_MASK 0x00000007L +#define RB_COLORCONTROL__ALPHA_TEST_ENABLE_MASK 0x00000008L +#define RB_COLORCONTROL__ALPHA_TEST_ENABLE 0x00000008L +#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE_MASK 0x00000010L +#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE 0x00000010L +#define RB_COLORCONTROL__BLEND_DISABLE_MASK 0x00000020L +#define RB_COLORCONTROL__BLEND_DISABLE 0x00000020L +#define RB_COLORCONTROL__FOG_ENABLE_MASK 0x00000040L +#define RB_COLORCONTROL__FOG_ENABLE 0x00000040L +#define RB_COLORCONTROL__VS_EXPORTS_FOG_MASK 0x00000080L +#define RB_COLORCONTROL__VS_EXPORTS_FOG 0x00000080L +#define RB_COLORCONTROL__ROP_CODE_MASK 0x00000f00L +#define RB_COLORCONTROL__DITHER_MODE_MASK 0x00003000L +#define RB_COLORCONTROL__DITHER_TYPE_MASK 0x0000c000L +#define RB_COLORCONTROL__PIXEL_FOG_MASK 0x00010000L +#define RB_COLORCONTROL__PIXEL_FOG 0x00010000L +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET0_MASK 0x03000000L +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET1_MASK 0x0c000000L +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET2_MASK 0x30000000L +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET3_MASK 0xc0000000L + +// RB_MODECONTROL +#define RB_MODECONTROL__EDRAM_MODE_MASK 0x00000007L + +// RB_COLOR_DEST_MASK +#define RB_COLOR_DEST_MASK__COLOR_DEST_MASK_MASK 0xffffffffL + +// RB_COPY_CONTROL +#define RB_COPY_CONTROL__COPY_SAMPLE_SELECT_MASK 0x00000007L +#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x00000008L +#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE 0x00000008L +#define RB_COPY_CONTROL__CLEAR_MASK_MASK 0x000000f0L + +// RB_COPY_DEST_BASE +#define RB_COPY_DEST_BASE__COPY_DEST_BASE_MASK 0xfffff000L + +// RB_COPY_DEST_PITCH +#define RB_COPY_DEST_PITCH__COPY_DEST_PITCH_MASK 0x000001ffL + +// RB_COPY_DEST_INFO +#define RB_COPY_DEST_INFO__COPY_DEST_ENDIAN_MASK 0x00000007L +#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR_MASK 0x00000008L +#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR 0x00000008L +#define RB_COPY_DEST_INFO__COPY_DEST_FORMAT_MASK 0x000000f0L +#define RB_COPY_DEST_INFO__COPY_DEST_SWAP_MASK 0x00000300L +#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_MODE_MASK 0x00000c00L +#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_TYPE_MASK 0x00003000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED_MASK 0x00004000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED 0x00004000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN_MASK 0x00008000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN 0x00008000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE_MASK 0x00010000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE 0x00010000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA_MASK 0x00020000L +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA 0x00020000L + +// RB_COPY_DEST_PIXEL_OFFSET +#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_X_MASK 0x00001fffL +#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_Y_MASK 0x03ffe000L + +// RB_DEPTH_CLEAR +#define RB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xffffffffL + +// RB_SAMPLE_COUNT_CTL +#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT_MASK 0x00000001L +#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT 0x00000001L +#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT_MASK 0x00000002L +#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT 0x00000002L + +// RB_SAMPLE_COUNT_ADDR +#define RB_SAMPLE_COUNT_ADDR__SAMPLE_COUNT_ADDR_MASK 0xffffffffL + +// RB_BC_CONTROL +#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE_MASK 0x00000001L +#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE 0x00000001L +#define RB_BC_CONTROL__ACCUM_TIMEOUT_SELECT_MASK 0x00000006L +#define RB_BC_CONTROL__DISABLE_EDRAM_CAM_MASK 0x00000008L +#define RB_BC_CONTROL__DISABLE_EDRAM_CAM 0x00000008L +#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK 0x00000010L +#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH 0x00000010L +#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP_MASK 0x00000020L +#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP 0x00000020L +#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP_MASK 0x00000040L +#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP 0x00000040L +#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE_MASK 0x00000080L +#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE 0x00000080L +#define RB_BC_CONTROL__AZ_THROTTLE_COUNT_MASK 0x00001f00L +#define RB_BC_CONTROL__ENABLE_CRC_UPDATE_MASK 0x00004000L +#define RB_BC_CONTROL__ENABLE_CRC_UPDATE 0x00004000L +#define RB_BC_CONTROL__CRC_MODE_MASK 0x00008000L +#define RB_BC_CONTROL__CRC_MODE 0x00008000L +#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS_MASK 0x00010000L +#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS 0x00010000L +#define RB_BC_CONTROL__DISABLE_ACCUM_MASK 0x00020000L +#define RB_BC_CONTROL__DISABLE_ACCUM 0x00020000L +#define RB_BC_CONTROL__ACCUM_ALLOC_MASK_MASK 0x003c0000L +#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE_MASK 0x00400000L +#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE 0x00400000L +#define RB_BC_CONTROL__ACCUM_DATA_FIFO_LIMIT_MASK 0x07800000L +#define RB_BC_CONTROL__MEM_EXPORT_TIMEOUT_SELECT_MASK 0x18000000L +#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE_MASK 0x20000000L +#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE 0x20000000L +#define RB_BC_CONTROL__CRC_SYSTEM_MASK 0x40000000L +#define RB_BC_CONTROL__CRC_SYSTEM 0x40000000L +#define RB_BC_CONTROL__RESERVED6_MASK 0x80000000L +#define RB_BC_CONTROL__RESERVED6 0x80000000L + +// RB_EDRAM_INFO +#define RB_EDRAM_INFO__EDRAM_SIZE_MASK 0x0000000fL +#define RB_EDRAM_INFO__EDRAM_MAPPING_MODE_MASK 0x00000030L +#define RB_EDRAM_INFO__EDRAM_RANGE_MASK 0xffffc000L + +// RB_CRC_RD_PORT +#define RB_CRC_RD_PORT__CRC_DATA_MASK 0xffffffffL + +// RB_CRC_CONTROL +#define RB_CRC_CONTROL__CRC_RD_ADVANCE_MASK 0x00000001L +#define RB_CRC_CONTROL__CRC_RD_ADVANCE 0x00000001L + +// RB_CRC_MASK +#define RB_CRC_MASK__CRC_MASK_MASK 0xffffffffL + +// RB_PERFCOUNTER0_SELECT +#define RB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL + +// RB_PERFCOUNTER0_LOW +#define RB_PERFCOUNTER0_LOW__PERF_COUNT_MASK 0xffffffffL + +// RB_PERFCOUNTER0_HI +#define RB_PERFCOUNTER0_HI__PERF_COUNT_MASK 0x0000ffffL + +// RB_TOTAL_SAMPLES +#define RB_TOTAL_SAMPLES__TOTAL_SAMPLES_MASK 0xffffffffL + +// RB_ZPASS_SAMPLES +#define RB_ZPASS_SAMPLES__ZPASS_SAMPLES_MASK 0xffffffffL + +// RB_ZFAIL_SAMPLES +#define RB_ZFAIL_SAMPLES__ZFAIL_SAMPLES_MASK 0xffffffffL + +// RB_SFAIL_SAMPLES +#define RB_SFAIL_SAMPLES__SFAIL_SAMPLES_MASK 0xffffffffL + +// RB_DEBUG_0 +#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL_MASK 0x00000001L +#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL 0x00000001L +#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL_MASK 0x00000002L +#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL 0x00000002L +#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL_MASK 0x00000004L +#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL 0x00000004L +#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL_MASK 0x00000008L +#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL 0x00000008L +#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL_MASK 0x00000010L +#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL 0x00000010L +#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL_MASK 0x00000020L +#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL 0x00000020L +#define RB_DEBUG_0__RDREQ_Z1_FULL_MASK 0x00000040L +#define RB_DEBUG_0__RDREQ_Z1_FULL 0x00000040L +#define RB_DEBUG_0__RDREQ_Z0_FULL_MASK 0x00000080L +#define RB_DEBUG_0__RDREQ_Z0_FULL 0x00000080L +#define RB_DEBUG_0__RDREQ_C1_FULL_MASK 0x00000100L +#define RB_DEBUG_0__RDREQ_C1_FULL 0x00000100L +#define RB_DEBUG_0__RDREQ_C0_FULL_MASK 0x00000200L +#define RB_DEBUG_0__RDREQ_C0_FULL 0x00000200L +#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL_MASK 0x00000400L +#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL 0x00000400L +#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL_MASK 0x00000800L +#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL 0x00000800L +#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL_MASK 0x00001000L +#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL 0x00001000L +#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL_MASK 0x00002000L +#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL 0x00002000L +#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL_MASK 0x00004000L +#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL 0x00004000L +#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL_MASK 0x00008000L +#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL 0x00008000L +#define RB_DEBUG_0__WRREQ_Z1_FULL_MASK 0x00010000L +#define RB_DEBUG_0__WRREQ_Z1_FULL 0x00010000L +#define RB_DEBUG_0__WRREQ_Z0_FULL_MASK 0x00020000L +#define RB_DEBUG_0__WRREQ_Z0_FULL 0x00020000L +#define RB_DEBUG_0__WRREQ_C1_FULL_MASK 0x00040000L +#define RB_DEBUG_0__WRREQ_C1_FULL 0x00040000L +#define RB_DEBUG_0__WRREQ_C0_FULL_MASK 0x00080000L +#define RB_DEBUG_0__WRREQ_C0_FULL 0x00080000L +#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL_MASK 0x00100000L +#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL 0x00100000L +#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL_MASK 0x00200000L +#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL 0x00200000L +#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL_MASK 0x00400000L +#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL 0x00400000L +#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL_MASK 0x00800000L +#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL 0x00800000L +#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL_MASK 0x01000000L +#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL 0x01000000L +#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL_MASK 0x02000000L +#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL 0x02000000L +#define RB_DEBUG_0__C_SX_LAT_FULL_MASK 0x04000000L +#define RB_DEBUG_0__C_SX_LAT_FULL 0x04000000L +#define RB_DEBUG_0__C_SX_CMD_FULL_MASK 0x08000000L +#define RB_DEBUG_0__C_SX_CMD_FULL 0x08000000L +#define RB_DEBUG_0__C_EZ_TILE_FULL_MASK 0x10000000L +#define RB_DEBUG_0__C_EZ_TILE_FULL 0x10000000L +#define RB_DEBUG_0__C_REQ_FULL_MASK 0x20000000L +#define RB_DEBUG_0__C_REQ_FULL 0x20000000L +#define RB_DEBUG_0__C_MASK_FULL_MASK 0x40000000L +#define RB_DEBUG_0__C_MASK_FULL 0x40000000L +#define RB_DEBUG_0__EZ_INFSAMP_FULL_MASK 0x80000000L +#define RB_DEBUG_0__EZ_INFSAMP_FULL 0x80000000L + +// RB_DEBUG_1 +#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY_MASK 0x00000001L +#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY 0x00000001L +#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY_MASK 0x00000002L +#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY 0x00000002L +#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY_MASK 0x00000004L +#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY 0x00000004L +#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY_MASK 0x00000008L +#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY 0x00000008L +#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY_MASK 0x00000010L +#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY 0x00000010L +#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY_MASK 0x00000020L +#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY 0x00000020L +#define RB_DEBUG_1__RDREQ_Z1_EMPTY_MASK 0x00000040L +#define RB_DEBUG_1__RDREQ_Z1_EMPTY 0x00000040L +#define RB_DEBUG_1__RDREQ_Z0_EMPTY_MASK 0x00000080L +#define RB_DEBUG_1__RDREQ_Z0_EMPTY 0x00000080L +#define RB_DEBUG_1__RDREQ_C1_EMPTY_MASK 0x00000100L +#define RB_DEBUG_1__RDREQ_C1_EMPTY 0x00000100L +#define RB_DEBUG_1__RDREQ_C0_EMPTY_MASK 0x00000200L +#define RB_DEBUG_1__RDREQ_C0_EMPTY 0x00000200L +#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY_MASK 0x00000400L +#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY 0x00000400L +#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY_MASK 0x00000800L +#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY 0x00000800L +#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY_MASK 0x00001000L +#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY 0x00001000L +#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY_MASK 0x00002000L +#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY 0x00002000L +#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY_MASK 0x00004000L +#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY 0x00004000L +#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY_MASK 0x00008000L +#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY 0x00008000L +#define RB_DEBUG_1__WRREQ_Z1_EMPTY_MASK 0x00010000L +#define RB_DEBUG_1__WRREQ_Z1_EMPTY 0x00010000L +#define RB_DEBUG_1__WRREQ_Z0_EMPTY_MASK 0x00020000L +#define RB_DEBUG_1__WRREQ_Z0_EMPTY 0x00020000L +#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY_MASK 0x00040000L +#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY 0x00040000L +#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY_MASK 0x00080000L +#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY 0x00080000L +#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY_MASK 0x00100000L +#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY 0x00100000L +#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY_MASK 0x00200000L +#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY 0x00200000L +#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY_MASK 0x00400000L +#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY 0x00400000L +#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY_MASK 0x00800000L +#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY 0x00800000L +#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY_MASK 0x01000000L +#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY 0x01000000L +#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY_MASK 0x02000000L +#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY 0x02000000L +#define RB_DEBUG_1__C_SX_LAT_EMPTY_MASK 0x04000000L +#define RB_DEBUG_1__C_SX_LAT_EMPTY 0x04000000L +#define RB_DEBUG_1__C_SX_CMD_EMPTY_MASK 0x08000000L +#define RB_DEBUG_1__C_SX_CMD_EMPTY 0x08000000L +#define RB_DEBUG_1__C_EZ_TILE_EMPTY_MASK 0x10000000L +#define RB_DEBUG_1__C_EZ_TILE_EMPTY 0x10000000L +#define RB_DEBUG_1__C_REQ_EMPTY_MASK 0x20000000L +#define RB_DEBUG_1__C_REQ_EMPTY 0x20000000L +#define RB_DEBUG_1__C_MASK_EMPTY_MASK 0x40000000L +#define RB_DEBUG_1__C_MASK_EMPTY 0x40000000L +#define RB_DEBUG_1__EZ_INFSAMP_EMPTY_MASK 0x80000000L +#define RB_DEBUG_1__EZ_INFSAMP_EMPTY 0x80000000L + +// RB_DEBUG_2 +#define RB_DEBUG_2__TILE_FIFO_COUNT_MASK 0x0000000fL +#define RB_DEBUG_2__SX_LAT_FIFO_COUNT_MASK 0x000007f0L +#define RB_DEBUG_2__MEM_EXPORT_FLAG_MASK 0x00000800L +#define RB_DEBUG_2__MEM_EXPORT_FLAG 0x00000800L +#define RB_DEBUG_2__SYSMEM_BLEND_FLAG_MASK 0x00001000L +#define RB_DEBUG_2__SYSMEM_BLEND_FLAG 0x00001000L +#define RB_DEBUG_2__CURRENT_TILE_EVENT_MASK 0x00002000L +#define RB_DEBUG_2__CURRENT_TILE_EVENT 0x00002000L +#define RB_DEBUG_2__EZ_INFTILE_FULL_MASK 0x00004000L +#define RB_DEBUG_2__EZ_INFTILE_FULL 0x00004000L +#define RB_DEBUG_2__EZ_MASK_LOWER_FULL_MASK 0x00008000L +#define RB_DEBUG_2__EZ_MASK_LOWER_FULL 0x00008000L +#define RB_DEBUG_2__EZ_MASK_UPPER_FULL_MASK 0x00010000L +#define RB_DEBUG_2__EZ_MASK_UPPER_FULL 0x00010000L +#define RB_DEBUG_2__Z0_MASK_FULL_MASK 0x00020000L +#define RB_DEBUG_2__Z0_MASK_FULL 0x00020000L +#define RB_DEBUG_2__Z1_MASK_FULL_MASK 0x00040000L +#define RB_DEBUG_2__Z1_MASK_FULL 0x00040000L +#define RB_DEBUG_2__Z0_REQ_FULL_MASK 0x00080000L +#define RB_DEBUG_2__Z0_REQ_FULL 0x00080000L +#define RB_DEBUG_2__Z1_REQ_FULL_MASK 0x00100000L +#define RB_DEBUG_2__Z1_REQ_FULL 0x00100000L +#define RB_DEBUG_2__Z_SAMP_FULL_MASK 0x00200000L +#define RB_DEBUG_2__Z_SAMP_FULL 0x00200000L +#define RB_DEBUG_2__Z_TILE_FULL_MASK 0x00400000L +#define RB_DEBUG_2__Z_TILE_FULL 0x00400000L +#define RB_DEBUG_2__EZ_INFTILE_EMPTY_MASK 0x00800000L +#define RB_DEBUG_2__EZ_INFTILE_EMPTY 0x00800000L +#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY_MASK 0x01000000L +#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY 0x01000000L +#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY_MASK 0x02000000L +#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY 0x02000000L +#define RB_DEBUG_2__Z0_MASK_EMPTY_MASK 0x04000000L +#define RB_DEBUG_2__Z0_MASK_EMPTY 0x04000000L +#define RB_DEBUG_2__Z1_MASK_EMPTY_MASK 0x08000000L +#define RB_DEBUG_2__Z1_MASK_EMPTY 0x08000000L +#define RB_DEBUG_2__Z0_REQ_EMPTY_MASK 0x10000000L +#define RB_DEBUG_2__Z0_REQ_EMPTY 0x10000000L +#define RB_DEBUG_2__Z1_REQ_EMPTY_MASK 0x20000000L +#define RB_DEBUG_2__Z1_REQ_EMPTY 0x20000000L +#define RB_DEBUG_2__Z_SAMP_EMPTY_MASK 0x40000000L +#define RB_DEBUG_2__Z_SAMP_EMPTY 0x40000000L +#define RB_DEBUG_2__Z_TILE_EMPTY_MASK 0x80000000L +#define RB_DEBUG_2__Z_TILE_EMPTY 0x80000000L + +// RB_DEBUG_3 +#define RB_DEBUG_3__ACCUM_VALID_MASK 0x0000000fL +#define RB_DEBUG_3__ACCUM_FLUSHING_MASK 0x000000f0L +#define RB_DEBUG_3__ACCUM_WRITE_CLEAN_COUNT_MASK 0x00003f00L +#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID_MASK 0x00004000L +#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID 0x00004000L +#define RB_DEBUG_3__ACCUM_DATA_FIFO_CNT_MASK 0x00078000L +#define RB_DEBUG_3__SHD_FULL_MASK 0x00080000L +#define RB_DEBUG_3__SHD_FULL 0x00080000L +#define RB_DEBUG_3__SHD_EMPTY_MASK 0x00100000L +#define RB_DEBUG_3__SHD_EMPTY 0x00100000L +#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY_MASK 0x00200000L +#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY 0x00200000L +#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY_MASK 0x00400000L +#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY 0x00400000L +#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL_MASK 0x00800000L +#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL 0x00800000L +#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL_MASK 0x01000000L +#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL 0x01000000L +#define RB_DEBUG_3__ZEXP_LOWER_EMPTY_MASK 0x02000000L +#define RB_DEBUG_3__ZEXP_LOWER_EMPTY 0x02000000L +#define RB_DEBUG_3__ZEXP_UPPER_EMPTY_MASK 0x04000000L +#define RB_DEBUG_3__ZEXP_UPPER_EMPTY 0x04000000L +#define RB_DEBUG_3__ZEXP_LOWER_FULL_MASK 0x08000000L +#define RB_DEBUG_3__ZEXP_LOWER_FULL 0x08000000L +#define RB_DEBUG_3__ZEXP_UPPER_FULL_MASK 0x10000000L +#define RB_DEBUG_3__ZEXP_UPPER_FULL 0x10000000L + +// RB_DEBUG_4 +#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG_MASK 0x00000001L +#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG 0x00000001L +#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG_MASK 0x00000002L +#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG 0x00000002L +#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG_MASK 0x00000004L +#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG 0x00000004L +#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG_MASK 0x00000008L +#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG 0x00000008L +#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY_MASK 0x00000010L +#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY 0x00000010L +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY_MASK 0x00000020L +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY 0x00000020L +#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL_MASK 0x00000040L +#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL 0x00000040L +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL_MASK 0x00000080L +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL 0x00000080L +#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW_MASK 0x00000100L +#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW 0x00000100L +#define RB_DEBUG_4__CONTEXT_COUNT_DEBUG_MASK 0x00001e00L + +// RB_FLAG_CONTROL +#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR_MASK 0x00000001L +#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR 0x00000001L + +// RB_BC_SPARES +#define RB_BC_SPARES__RESERVED_MASK 0xffffffffL + +// BC_DUMMY_CRAYRB_ENUMS +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_FORMAT_MASK 0x0000003fL +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP_MASK 0x00000040L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP 0x00000040L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_ARRAY_MASK 0x00000180L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_ARRAY_MASK 0x00000600L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_COLOR_FORMAT_MASK 0x0001f800L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_NUMBER_MASK 0x000e0000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_FORMAT_MASK 0x03f00000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING_MASK 0x04000000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING 0x04000000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_ARRAY_MASK 0x18000000L +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK 0xe0000000L + +// BC_DUMMY_CRAYRB_MOREENUMS +#define BC_DUMMY_CRAYRB_MOREENUMS__DUMMY_CRAYRB_COLORARRAYX_MASK 0x00000003L + +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_offset.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_offset.h new file mode 100644 index 000000000000..83be5f82ed8c --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_offset.h @@ -0,0 +1,591 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _yamato_OFFSET_HEADER +#define _yamato_OFFSET_HEADER + + +// Registers from PA block + +#define mmPA_CL_VPORT_XSCALE 0x210F +#define mmPA_CL_VPORT_XOFFSET 0x2110 +#define mmPA_CL_VPORT_YSCALE 0x2111 +#define mmPA_CL_VPORT_YOFFSET 0x2112 +#define mmPA_CL_VPORT_ZSCALE 0x2113 +#define mmPA_CL_VPORT_ZOFFSET 0x2114 +#define mmPA_CL_VTE_CNTL 0x2206 +#define mmPA_CL_CLIP_CNTL 0x2204 +#define mmPA_CL_GB_VERT_CLIP_ADJ 0x2303 +#define mmPA_CL_GB_VERT_DISC_ADJ 0x2304 +#define mmPA_CL_GB_HORZ_CLIP_ADJ 0x2305 +#define mmPA_CL_GB_HORZ_DISC_ADJ 0x2306 +#define mmPA_CL_ENHANCE 0x0C85 +#define mmPA_SC_ENHANCE 0x0CA5 +#define mmPA_SU_VTX_CNTL 0x2302 +#define mmPA_SU_POINT_SIZE 0x2280 +#define mmPA_SU_POINT_MINMAX 0x2281 +#define mmPA_SU_LINE_CNTL 0x2282 +#define mmPA_SU_FACE_DATA 0x0C86 +#define mmPA_SU_SC_MODE_CNTL 0x2205 +#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0x2380 +#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0x2381 +#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0x2382 +#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0x2383 +#define mmPA_SU_PERFCOUNTER0_SELECT 0x0C88 +#define mmPA_SU_PERFCOUNTER1_SELECT 0x0C89 +#define mmPA_SU_PERFCOUNTER2_SELECT 0x0C8A +#define mmPA_SU_PERFCOUNTER3_SELECT 0x0C8B +#define mmPA_SU_PERFCOUNTER0_LOW 0x0C8C +#define mmPA_SU_PERFCOUNTER0_HI 0x0C8D +#define mmPA_SU_PERFCOUNTER1_LOW 0x0C8E +#define mmPA_SU_PERFCOUNTER1_HI 0x0C8F +#define mmPA_SU_PERFCOUNTER2_LOW 0x0C90 +#define mmPA_SU_PERFCOUNTER2_HI 0x0C91 +#define mmPA_SU_PERFCOUNTER3_LOW 0x0C92 +#define mmPA_SU_PERFCOUNTER3_HI 0x0C93 +#define mmPA_SC_WINDOW_OFFSET 0x2080 +#define mmPA_SC_AA_CONFIG 0x2301 +#define mmPA_SC_AA_MASK 0x2312 +#define mmPA_SC_LINE_STIPPLE 0x2283 +#define mmPA_SC_LINE_CNTL 0x2300 +#define mmPA_SC_WINDOW_SCISSOR_TL 0x2081 +#define mmPA_SC_WINDOW_SCISSOR_BR 0x2082 +#define mmPA_SC_SCREEN_SCISSOR_TL 0x200E +#define mmPA_SC_SCREEN_SCISSOR_BR 0x200F +#define mmPA_SC_VIZ_QUERY 0x2293 +#define mmPA_SC_VIZ_QUERY_STATUS 0x0C44 +#define mmPA_SC_LINE_STIPPLE_STATE 0x0C40 +#define mmPA_SC_PERFCOUNTER0_SELECT 0x0C98 +#define mmPA_SC_PERFCOUNTER0_LOW 0x0C99 +#define mmPA_SC_PERFCOUNTER0_HI 0x0C9A +#define mmPA_CL_CNTL_STATUS 0x0C84 +#define mmPA_SU_CNTL_STATUS 0x0C94 +#define mmPA_SC_CNTL_STATUS 0x0CA4 +#define mmPA_SU_DEBUG_CNTL 0x0C80 +#define mmPA_SU_DEBUG_DATA 0x0C81 +#define mmPA_SC_DEBUG_CNTL 0x0C82 +#define mmPA_SC_DEBUG_DATA 0x0C83 + + +// Registers from VGT block + +#define mmGFX_COPY_STATE 0x21F4 +#define mmVGT_DRAW_INITIATOR 0x21FC +#define mmVGT_EVENT_INITIATOR 0x21F9 +#define mmVGT_DMA_BASE 0x21FA +#define mmVGT_DMA_SIZE 0x21FB +#define mmVGT_BIN_BASE 0x21FE +#define mmVGT_BIN_SIZE 0x21FF +#define mmVGT_CURRENT_BIN_ID_MIN 0x2207 +#define mmVGT_CURRENT_BIN_ID_MAX 0x2203 +#define mmVGT_IMMED_DATA 0x21FD +#define mmVGT_MAX_VTX_INDX 0x2100 +#define mmVGT_MIN_VTX_INDX 0x2101 +#define mmVGT_INDX_OFFSET 0x2102 +#define mmVGT_VERTEX_REUSE_BLOCK_CNTL 0x2316 +#define mmVGT_OUT_DEALLOC_CNTL 0x2317 +#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0x2103 +#define mmVGT_ENHANCE 0x2294 +#define mmVGT_VTX_VECT_EJECT_REG 0x0C2C +#define mmVGT_LAST_COPY_STATE 0x0C30 +#define mmVGT_DEBUG_CNTL 0x0C38 +#define mmVGT_DEBUG_DATA 0x0C39 +#define mmVGT_CNTL_STATUS 0x0C3C +#define mmVGT_CRC_SQ_DATA 0x0C3A +#define mmVGT_CRC_SQ_CTRL 0x0C3B +#define mmVGT_PERFCOUNTER0_SELECT 0x0C48 +#define mmVGT_PERFCOUNTER1_SELECT 0x0C49 +#define mmVGT_PERFCOUNTER2_SELECT 0x0C4A +#define mmVGT_PERFCOUNTER3_SELECT 0x0C4B +#define mmVGT_PERFCOUNTER0_LOW 0x0C4C +#define mmVGT_PERFCOUNTER1_LOW 0x0C4E +#define mmVGT_PERFCOUNTER2_LOW 0x0C50 +#define mmVGT_PERFCOUNTER3_LOW 0x0C52 +#define mmVGT_PERFCOUNTER0_HI 0x0C4D +#define mmVGT_PERFCOUNTER1_HI 0x0C4F +#define mmVGT_PERFCOUNTER2_HI 0x0C51 +#define mmVGT_PERFCOUNTER3_HI 0x0C53 + + +// Registers from TP block + +#define mmTC_CNTL_STATUS 0x0E00 +#define mmTCR_CHICKEN 0x0E02 +#define mmTCF_CHICKEN 0x0E03 +#define mmTCM_CHICKEN 0x0E04 +#define mmTCR_PERFCOUNTER0_SELECT 0x0E05 +#define mmTCR_PERFCOUNTER1_SELECT 0x0E08 +#define mmTCR_PERFCOUNTER0_HI 0x0E06 +#define mmTCR_PERFCOUNTER1_HI 0x0E09 +#define mmTCR_PERFCOUNTER0_LOW 0x0E07 +#define mmTCR_PERFCOUNTER1_LOW 0x0E0A +#define mmTP_TC_CLKGATE_CNTL 0x0E17 +#define mmTPC_CNTL_STATUS 0x0E18 +#define mmTPC_DEBUG0 0x0E19 +#define mmTPC_DEBUG1 0x0E1A +#define mmTPC_CHICKEN 0x0E1B +#define mmTP0_CNTL_STATUS 0x0E1C +#define mmTP0_DEBUG 0x0E1D +#define mmTP0_CHICKEN 0x0E1E +#define mmTP0_PERFCOUNTER0_SELECT 0x0E1F +#define mmTP0_PERFCOUNTER0_HI 0x0E20 +#define mmTP0_PERFCOUNTER0_LOW 0x0E21 +#define mmTP0_PERFCOUNTER1_SELECT 0x0E22 +#define mmTP0_PERFCOUNTER1_HI 0x0E23 +#define mmTP0_PERFCOUNTER1_LOW 0x0E24 +#define mmTCM_PERFCOUNTER0_SELECT 0x0E54 +#define mmTCM_PERFCOUNTER1_SELECT 0x0E57 +#define mmTCM_PERFCOUNTER0_HI 0x0E55 +#define mmTCM_PERFCOUNTER1_HI 0x0E58 +#define mmTCM_PERFCOUNTER0_LOW 0x0E56 +#define mmTCM_PERFCOUNTER1_LOW 0x0E59 +#define mmTCF_PERFCOUNTER0_SELECT 0x0E5A +#define mmTCF_PERFCOUNTER1_SELECT 0x0E5D +#define mmTCF_PERFCOUNTER2_SELECT 0x0E60 +#define mmTCF_PERFCOUNTER3_SELECT 0x0E63 +#define mmTCF_PERFCOUNTER4_SELECT 0x0E66 +#define mmTCF_PERFCOUNTER5_SELECT 0x0E69 +#define mmTCF_PERFCOUNTER6_SELECT 0x0E6C +#define mmTCF_PERFCOUNTER7_SELECT 0x0E6F +#define mmTCF_PERFCOUNTER8_SELECT 0x0E72 +#define mmTCF_PERFCOUNTER9_SELECT 0x0E75 +#define mmTCF_PERFCOUNTER10_SELECT 0x0E78 +#define mmTCF_PERFCOUNTER11_SELECT 0x0E7B +#define mmTCF_PERFCOUNTER0_HI 0x0E5B +#define mmTCF_PERFCOUNTER1_HI 0x0E5E +#define mmTCF_PERFCOUNTER2_HI 0x0E61 +#define mmTCF_PERFCOUNTER3_HI 0x0E64 +#define mmTCF_PERFCOUNTER4_HI 0x0E67 +#define mmTCF_PERFCOUNTER5_HI 0x0E6A +#define mmTCF_PERFCOUNTER6_HI 0x0E6D +#define mmTCF_PERFCOUNTER7_HI 0x0E70 +#define mmTCF_PERFCOUNTER8_HI 0x0E73 +#define mmTCF_PERFCOUNTER9_HI 0x0E76 +#define mmTCF_PERFCOUNTER10_HI 0x0E79 +#define mmTCF_PERFCOUNTER11_HI 0x0E7C +#define mmTCF_PERFCOUNTER0_LOW 0x0E5C +#define mmTCF_PERFCOUNTER1_LOW 0x0E5F +#define mmTCF_PERFCOUNTER2_LOW 0x0E62 +#define mmTCF_PERFCOUNTER3_LOW 0x0E65 +#define mmTCF_PERFCOUNTER4_LOW 0x0E68 +#define mmTCF_PERFCOUNTER5_LOW 0x0E6B +#define mmTCF_PERFCOUNTER6_LOW 0x0E6E +#define mmTCF_PERFCOUNTER7_LOW 0x0E71 +#define mmTCF_PERFCOUNTER8_LOW 0x0E74 +#define mmTCF_PERFCOUNTER9_LOW 0x0E77 +#define mmTCF_PERFCOUNTER10_LOW 0x0E7A +#define mmTCF_PERFCOUNTER11_LOW 0x0E7D +#define mmTCF_DEBUG 0x0EC0 +#define mmTCA_FIFO_DEBUG 0x0EC1 +#define mmTCA_PROBE_DEBUG 0x0EC2 +#define mmTCA_TPC_DEBUG 0x0EC3 +#define mmTCB_CORE_DEBUG 0x0EC4 +#define mmTCB_TAG0_DEBUG 0x0EC5 +#define mmTCB_TAG1_DEBUG 0x0EC6 +#define mmTCB_TAG2_DEBUG 0x0EC7 +#define mmTCB_TAG3_DEBUG 0x0EC8 +#define mmTCB_FETCH_GEN_SECTOR_WALKER0_DEBUG 0x0EC9 +#define mmTCB_FETCH_GEN_WALKER_DEBUG 0x0ECB +#define mmTCB_FETCH_GEN_PIPE0_DEBUG 0x0ECC +#define mmTCD_INPUT0_DEBUG 0x0ED0 +#define mmTCD_DEGAMMA_DEBUG 0x0ED4 +#define mmTCD_DXTMUX_SCTARB_DEBUG 0x0ED5 +#define mmTCD_DXTC_ARB_DEBUG 0x0ED6 +#define mmTCD_STALLS_DEBUG 0x0ED7 +#define mmTCO_STALLS_DEBUG 0x0EE0 +#define mmTCO_QUAD0_DEBUG0 0x0EE1 +#define mmTCO_QUAD0_DEBUG1 0x0EE2 + + +// Registers from TC block + + + +// Registers from SQ block + +#define mmSQ_GPR_MANAGEMENT 0x0D00 +#define mmSQ_FLOW_CONTROL 0x0D01 +#define mmSQ_INST_STORE_MANAGMENT 0x0D02 +#define mmSQ_RESOURCE_MANAGMENT 0x0D03 +#define mmSQ_EO_RT 0x0D04 +#define mmSQ_DEBUG_MISC 0x0D05 +#define mmSQ_ACTIVITY_METER_CNTL 0x0D06 +#define mmSQ_ACTIVITY_METER_STATUS 0x0D07 +#define mmSQ_INPUT_ARB_PRIORITY 0x0D08 +#define mmSQ_THREAD_ARB_PRIORITY 0x0D09 +#define mmSQ_VS_WATCHDOG_TIMER 0x0D0A +#define mmSQ_PS_WATCHDOG_TIMER 0x0D0B +#define mmSQ_INT_CNTL 0x0D34 +#define mmSQ_INT_STATUS 0x0D35 +#define mmSQ_INT_ACK 0x0D36 +#define mmSQ_DEBUG_INPUT_FSM 0x0DAE +#define mmSQ_DEBUG_CONST_MGR_FSM 0x0DAF +#define mmSQ_DEBUG_TP_FSM 0x0DB0 +#define mmSQ_DEBUG_FSM_ALU_0 0x0DB1 +#define mmSQ_DEBUG_FSM_ALU_1 0x0DB2 +#define mmSQ_DEBUG_EXP_ALLOC 0x0DB3 +#define mmSQ_DEBUG_PTR_BUFF 0x0DB4 +#define mmSQ_DEBUG_GPR_VTX 0x0DB5 +#define mmSQ_DEBUG_GPR_PIX 0x0DB6 +#define mmSQ_DEBUG_TB_STATUS_SEL 0x0DB7 +#define mmSQ_DEBUG_VTX_TB_0 0x0DB8 +#define mmSQ_DEBUG_VTX_TB_1 0x0DB9 +#define mmSQ_DEBUG_VTX_TB_STATUS_REG 0x0DBA +#define mmSQ_DEBUG_VTX_TB_STATE_MEM 0x0DBB +#define mmSQ_DEBUG_PIX_TB_0 0x0DBC +#define mmSQ_DEBUG_PIX_TB_STATUS_REG_0 0x0DBD +#define mmSQ_DEBUG_PIX_TB_STATUS_REG_1 0x0DBE +#define mmSQ_DEBUG_PIX_TB_STATUS_REG_2 0x0DBF +#define mmSQ_DEBUG_PIX_TB_STATUS_REG_3 0x0DC0 +#define mmSQ_DEBUG_PIX_TB_STATE_MEM 0x0DC1 +#define mmSQ_PERFCOUNTER0_SELECT 0x0DC8 +#define mmSQ_PERFCOUNTER1_SELECT 0x0DC9 +#define mmSQ_PERFCOUNTER2_SELECT 0x0DCA +#define mmSQ_PERFCOUNTER3_SELECT 0x0DCB +#define mmSQ_PERFCOUNTER0_LOW 0x0DCC +#define mmSQ_PERFCOUNTER0_HI 0x0DCD +#define mmSQ_PERFCOUNTER1_LOW 0x0DCE +#define mmSQ_PERFCOUNTER1_HI 0x0DCF +#define mmSQ_PERFCOUNTER2_LOW 0x0DD0 +#define mmSQ_PERFCOUNTER2_HI 0x0DD1 +#define mmSQ_PERFCOUNTER3_LOW 0x0DD2 +#define mmSQ_PERFCOUNTER3_HI 0x0DD3 +#define mmSX_PERFCOUNTER0_SELECT 0x0DD4 +#define mmSX_PERFCOUNTER0_LOW 0x0DD8 +#define mmSX_PERFCOUNTER0_HI 0x0DD9 +#define mmSQ_INSTRUCTION_ALU_0 0x5000 +#define mmSQ_INSTRUCTION_ALU_1 0x5001 +#define mmSQ_INSTRUCTION_ALU_2 0x5002 +#define mmSQ_INSTRUCTION_CF_EXEC_0 0x5080 +#define mmSQ_INSTRUCTION_CF_EXEC_1 0x5081 +#define mmSQ_INSTRUCTION_CF_EXEC_2 0x5082 +#define mmSQ_INSTRUCTION_CF_LOOP_0 0x5083 +#define mmSQ_INSTRUCTION_CF_LOOP_1 0x5084 +#define mmSQ_INSTRUCTION_CF_LOOP_2 0x5085 +#define mmSQ_INSTRUCTION_CF_JMP_CALL_0 0x5086 +#define mmSQ_INSTRUCTION_CF_JMP_CALL_1 0x5087 +#define mmSQ_INSTRUCTION_CF_JMP_CALL_2 0x5088 +#define mmSQ_INSTRUCTION_CF_ALLOC_0 0x5089 +#define mmSQ_INSTRUCTION_CF_ALLOC_1 0x508A +#define mmSQ_INSTRUCTION_CF_ALLOC_2 0x508B +#define mmSQ_INSTRUCTION_TFETCH_0 0x5043 +#define mmSQ_INSTRUCTION_TFETCH_1 0x5044 +#define mmSQ_INSTRUCTION_TFETCH_2 0x5045 +#define mmSQ_INSTRUCTION_VFETCH_0 0x5040 +#define mmSQ_INSTRUCTION_VFETCH_1 0x5041 +#define mmSQ_INSTRUCTION_VFETCH_2 0x5042 +#define mmSQ_CONSTANT_0 0x4000 +#define mmSQ_CONSTANT_1 0x4001 +#define mmSQ_CONSTANT_2 0x4002 +#define mmSQ_CONSTANT_3 0x4003 +#define mmSQ_FETCH_0 0x4800 +#define mmSQ_FETCH_1 0x4801 +#define mmSQ_FETCH_2 0x4802 +#define mmSQ_FETCH_3 0x4803 +#define mmSQ_FETCH_4 0x4804 +#define mmSQ_FETCH_5 0x4805 +#define mmSQ_CONSTANT_VFETCH_0 0x4806 +#define mmSQ_CONSTANT_VFETCH_1 0x4808 +#define mmSQ_CONSTANT_T2 0x480C +#define mmSQ_CONSTANT_T3 0x4812 +#define mmSQ_CF_BOOLEANS 0x4900 +#define mmSQ_CF_LOOP 0x4908 +#define mmSQ_CONSTANT_RT_0 0x4940 +#define mmSQ_CONSTANT_RT_1 0x4941 +#define mmSQ_CONSTANT_RT_2 0x4942 +#define mmSQ_CONSTANT_RT_3 0x4943 +#define mmSQ_FETCH_RT_0 0x4D40 +#define mmSQ_FETCH_RT_1 0x4D41 +#define mmSQ_FETCH_RT_2 0x4D42 +#define mmSQ_FETCH_RT_3 0x4D43 +#define mmSQ_FETCH_RT_4 0x4D44 +#define mmSQ_FETCH_RT_5 0x4D45 +#define mmSQ_CF_RT_BOOLEANS 0x4E00 +#define mmSQ_CF_RT_LOOP 0x4E14 +#define mmSQ_VS_PROGRAM 0x21F7 +#define mmSQ_PS_PROGRAM 0x21F6 +#define mmSQ_CF_PROGRAM_SIZE 0x2315 +#define mmSQ_INTERPOLATOR_CNTL 0x2182 +#define mmSQ_PROGRAM_CNTL 0x2180 +#define mmSQ_WRAPPING_0 0x2183 +#define mmSQ_WRAPPING_1 0x2184 +#define mmSQ_VS_CONST 0x2307 +#define mmSQ_PS_CONST 0x2308 +#define mmSQ_CONTEXT_MISC 0x2181 +#define mmSQ_CF_RD_BASE 0x21F5 +#define mmSQ_DEBUG_MISC_0 0x2309 +#define mmSQ_DEBUG_MISC_1 0x230A + + +// Registers from SX block + + + +// Registers from MH block + +#define mmMH_ARBITER_CONFIG 0x0A40 +#define mmMH_CLNT_AXI_ID_REUSE 0x0A41 +#define mmMH_INTERRUPT_MASK 0x0A42 +#define mmMH_INTERRUPT_STATUS 0x0A43 +#define mmMH_INTERRUPT_CLEAR 0x0A44 +#define mmMH_AXI_ERROR 0x0A45 +#define mmMH_PERFCOUNTER0_SELECT 0x0A46 +#define mmMH_PERFCOUNTER1_SELECT 0x0A4A +#define mmMH_PERFCOUNTER0_CONFIG 0x0A47 +#define mmMH_PERFCOUNTER1_CONFIG 0x0A4B +#define mmMH_PERFCOUNTER0_LOW 0x0A48 +#define mmMH_PERFCOUNTER1_LOW 0x0A4C +#define mmMH_PERFCOUNTER0_HI 0x0A49 +#define mmMH_PERFCOUNTER1_HI 0x0A4D +#define mmMH_DEBUG_CTRL 0x0A4E +#define mmMH_DEBUG_DATA 0x0A4F +#define mmMH_AXI_HALT_CONTROL 0x0A50 +#define mmMH_MMU_CONFIG 0x0040 +#define mmMH_MMU_VA_RANGE 0x0041 +#define mmMH_MMU_PT_BASE 0x0042 +#define mmMH_MMU_PAGE_FAULT 0x0043 +#define mmMH_MMU_TRAN_ERROR 0x0044 +#define mmMH_MMU_INVALIDATE 0x0045 +#define mmMH_MMU_MPU_BASE 0x0046 +#define mmMH_MMU_MPU_END 0x0047 + + +// Registers from RBBM block + +#define mmWAIT_UNTIL 0x05C8 +#define mmRBBM_ISYNC_CNTL 0x05C9 +#define mmRBBM_STATUS 0x05D0 +#define mmRBBM_DSPLY 0x0391 +#define mmRBBM_RENDER_LATEST 0x0392 +#define mmRBBM_RTL_RELEASE 0x0000 +#define mmRBBM_PATCH_RELEASE 0x0001 +#define mmRBBM_AUXILIARY_CONFIG 0x0002 +#define mmRBBM_PERIPHID0 0x03F8 +#define mmRBBM_PERIPHID1 0x03F9 +#define mmRBBM_PERIPHID2 0x03FA +#define mmRBBM_PERIPHID3 0x03FB +#define mmRBBM_CNTL 0x003B +#define mmRBBM_SKEW_CNTL 0x003D +#define mmRBBM_SOFT_RESET 0x003C +#define mmRBBM_PM_OVERRIDE1 0x039C +#define mmRBBM_PM_OVERRIDE2 0x039D +#define mmGC_SYS_IDLE 0x039E +#define mmNQWAIT_UNTIL 0x0394 +#define mmRBBM_DEBUG_OUT 0x03A0 +#define mmRBBM_DEBUG_CNTL 0x03A1 +#define mmRBBM_DEBUG 0x039B +#define mmRBBM_READ_ERROR 0x03B3 +#define mmRBBM_WAIT_IDLE_CLOCKS 0x03B2 +#define mmRBBM_INT_CNTL 0x03B4 +#define mmRBBM_INT_STATUS 0x03B5 +#define mmRBBM_INT_ACK 0x03B6 +#define mmMASTER_INT_SIGNAL 0x03B7 +#define mmRBBM_PERFCOUNTER1_SELECT 0x0395 +#define mmRBBM_PERFCOUNTER1_LO 0x0397 +#define mmRBBM_PERFCOUNTER1_HI 0x0398 + + +// Registers from CP block + +#define mmCP_RB_BASE 0x01C0 +#define mmCP_RB_CNTL 0x01C1 +#define mmCP_RB_RPTR_ADDR 0x01C3 +#define mmCP_RB_RPTR 0x01C4 +#define mmCP_RB_RPTR_WR 0x01C7 +#define mmCP_RB_WPTR 0x01C5 +#define mmCP_RB_WPTR_DELAY 0x01C6 +#define mmCP_RB_WPTR_BASE 0x01C8 +#define mmCP_IB1_BASE 0x0458 +#define mmCP_IB1_BUFSZ 0x0459 +#define mmCP_IB2_BASE 0x045A +#define mmCP_IB2_BUFSZ 0x045B +#define mmCP_ST_BASE 0x044D +#define mmCP_ST_BUFSZ 0x044E +#define mmCP_QUEUE_THRESHOLDS 0x01D5 +#define mmCP_MEQ_THRESHOLDS 0x01D6 +#define mmCP_CSQ_AVAIL 0x01D7 +#define mmCP_STQ_AVAIL 0x01D8 +#define mmCP_MEQ_AVAIL 0x01D9 +#define mmCP_CSQ_RB_STAT 0x01FD +#define mmCP_CSQ_IB1_STAT 0x01FE +#define mmCP_CSQ_IB2_STAT 0x01FF +#define mmCP_NON_PREFETCH_CNTRS 0x0440 +#define mmCP_STQ_ST_STAT 0x0443 +#define mmCP_MEQ_STAT 0x044F +#define mmCP_MIU_TAG_STAT 0x0452 +#define mmCP_CMD_INDEX 0x01DA +#define mmCP_CMD_DATA 0x01DB +#define mmCP_ME_CNTL 0x01F6 +#define mmCP_ME_STATUS 0x01F7 +#define mmCP_ME_RAM_WADDR 0x01F8 +#define mmCP_ME_RAM_RADDR 0x01F9 +#define mmCP_ME_RAM_DATA 0x01FA +#define mmCP_ME_RDADDR 0x01EA +#define mmCP_DEBUG 0x01FC +#define mmSCRATCH_REG0 0x0578 +#define mmGUI_SCRATCH_REG0 0x0578 +#define mmSCRATCH_REG1 0x0579 +#define mmGUI_SCRATCH_REG1 0x0579 +#define mmSCRATCH_REG2 0x057A +#define mmGUI_SCRATCH_REG2 0x057A +#define mmSCRATCH_REG3 0x057B +#define mmGUI_SCRATCH_REG3 0x057B +#define mmSCRATCH_REG4 0x057C +#define mmGUI_SCRATCH_REG4 0x057C +#define mmSCRATCH_REG5 0x057D +#define mmGUI_SCRATCH_REG5 0x057D +#define mmSCRATCH_REG6 0x057E +#define mmGUI_SCRATCH_REG6 0x057E +#define mmSCRATCH_REG7 0x057F +#define mmGUI_SCRATCH_REG7 0x057F +#define mmSCRATCH_UMSK 0x01DC +#define mmSCRATCH_ADDR 0x01DD +#define mmCP_ME_VS_EVENT_SRC 0x0600 +#define mmCP_ME_VS_EVENT_ADDR 0x0601 +#define mmCP_ME_VS_EVENT_DATA 0x0602 +#define mmCP_ME_VS_EVENT_ADDR_SWM 0x0603 +#define mmCP_ME_VS_EVENT_DATA_SWM 0x0604 +#define mmCP_ME_PS_EVENT_SRC 0x0605 +#define mmCP_ME_PS_EVENT_ADDR 0x0606 +#define mmCP_ME_PS_EVENT_DATA 0x0607 +#define mmCP_ME_PS_EVENT_ADDR_SWM 0x0608 +#define mmCP_ME_PS_EVENT_DATA_SWM 0x0609 +#define mmCP_ME_CF_EVENT_SRC 0x060A +#define mmCP_ME_CF_EVENT_ADDR 0x060B +#define mmCP_ME_CF_EVENT_DATA 0x060C +#define mmCP_ME_NRT_ADDR 0x060D +#define mmCP_ME_NRT_DATA 0x060E +#define mmCP_ME_VS_FETCH_DONE_SRC 0x0612 +#define mmCP_ME_VS_FETCH_DONE_ADDR 0x0613 +#define mmCP_ME_VS_FETCH_DONE_DATA 0x0614 +#define mmCP_INT_CNTL 0x01F2 +#define mmCP_INT_STATUS 0x01F3 +#define mmCP_INT_ACK 0x01F4 +#define mmCP_PFP_UCODE_ADDR 0x00C0 +#define mmCP_PFP_UCODE_DATA 0x00C1 +#define mmCP_PERFMON_CNTL 0x0444 +#define mmCP_PERFCOUNTER_SELECT 0x0445 +#define mmCP_PERFCOUNTER_LO 0x0446 +#define mmCP_PERFCOUNTER_HI 0x0447 +#define mmCP_BIN_MASK_LO 0x0454 +#define mmCP_BIN_MASK_HI 0x0455 +#define mmCP_BIN_SELECT_LO 0x0456 +#define mmCP_BIN_SELECT_HI 0x0457 +#define mmCP_NV_FLAGS_0 0x01EE +#define mmCP_NV_FLAGS_1 0x01EF +#define mmCP_NV_FLAGS_2 0x01F0 +#define mmCP_NV_FLAGS_3 0x01F1 +#define mmCP_STATE_DEBUG_INDEX 0x01EC +#define mmCP_STATE_DEBUG_DATA 0x01ED +#define mmCP_PROG_COUNTER 0x044B +#define mmCP_STAT 0x047F +#define mmBIOS_0_SCRATCH 0x0004 +#define mmBIOS_1_SCRATCH 0x0005 +#define mmBIOS_2_SCRATCH 0x0006 +#define mmBIOS_3_SCRATCH 0x0007 +#define mmBIOS_4_SCRATCH 0x0008 +#define mmBIOS_5_SCRATCH 0x0009 +#define mmBIOS_6_SCRATCH 0x000A +#define mmBIOS_7_SCRATCH 0x000B +#define mmBIOS_8_SCRATCH 0x0580 +#define mmBIOS_9_SCRATCH 0x0581 +#define mmBIOS_10_SCRATCH 0x0582 +#define mmBIOS_11_SCRATCH 0x0583 +#define mmBIOS_12_SCRATCH 0x0584 +#define mmBIOS_13_SCRATCH 0x0585 +#define mmBIOS_14_SCRATCH 0x0586 +#define mmBIOS_15_SCRATCH 0x0587 +#define mmCOHER_SIZE_PM4 0x0A29 +#define mmCOHER_BASE_PM4 0x0A2A +#define mmCOHER_STATUS_PM4 0x0A2B +#define mmCOHER_SIZE_HOST 0x0A2F +#define mmCOHER_BASE_HOST 0x0A30 +#define mmCOHER_STATUS_HOST 0x0A31 +#define mmCOHER_DEST_BASE_0 0x2006 +#define mmCOHER_DEST_BASE_1 0x2007 +#define mmCOHER_DEST_BASE_2 0x2008 +#define mmCOHER_DEST_BASE_3 0x2009 +#define mmCOHER_DEST_BASE_4 0x200A +#define mmCOHER_DEST_BASE_5 0x200B +#define mmCOHER_DEST_BASE_6 0x200C +#define mmCOHER_DEST_BASE_7 0x200D + + +// Registers from SC block + + + +// Registers from BC block + +#define mmRB_SURFACE_INFO 0x2000 +#define mmRB_COLOR_INFO 0x2001 +#define mmRB_DEPTH_INFO 0x2002 +#define mmRB_STENCILREFMASK 0x210D +#define mmRB_ALPHA_REF 0x210E +#define mmRB_COLOR_MASK 0x2104 +#define mmRB_BLEND_RED 0x2105 +#define mmRB_BLEND_GREEN 0x2106 +#define mmRB_BLEND_BLUE 0x2107 +#define mmRB_BLEND_ALPHA 0x2108 +#define mmRB_FOG_COLOR 0x2109 +#define mmRB_STENCILREFMASK_BF 0x210C +#define mmRB_DEPTHCONTROL 0x2200 +#define mmRB_BLENDCONTROL 0x2201 +#define mmRB_COLORCONTROL 0x2202 +#define mmRB_MODECONTROL 0x2208 +#define mmRB_COLOR_DEST_MASK 0x2326 +#define mmRB_COPY_CONTROL 0x2318 +#define mmRB_COPY_DEST_BASE 0x2319 +#define mmRB_COPY_DEST_PITCH 0x231A +#define mmRB_COPY_DEST_INFO 0x231B +#define mmRB_COPY_DEST_PIXEL_OFFSET 0x231C +#define mmRB_DEPTH_CLEAR 0x231D +#define mmRB_SAMPLE_COUNT_CTL 0x2324 +#define mmRB_SAMPLE_COUNT_ADDR 0x2325 +#define mmRB_BC_CONTROL 0x0F01 +#define mmRB_EDRAM_INFO 0x0F02 +#define mmRB_CRC_RD_PORT 0x0F0C +#define mmRB_CRC_CONTROL 0x0F0D +#define mmRB_CRC_MASK 0x0F0E +#define mmRB_PERFCOUNTER0_SELECT 0x0F04 +#define mmRB_PERFCOUNTER0_LOW 0x0F08 +#define mmRB_PERFCOUNTER0_HI 0x0F09 +#define mmRB_TOTAL_SAMPLES 0x0F0F +#define mmRB_ZPASS_SAMPLES 0x0F10 +#define mmRB_ZFAIL_SAMPLES 0x0F11 +#define mmRB_SFAIL_SAMPLES 0x0F12 +#define mmRB_DEBUG_0 0x0F26 +#define mmRB_DEBUG_1 0x0F27 +#define mmRB_DEBUG_2 0x0F28 +#define mmRB_DEBUG_3 0x0F29 +#define mmRB_DEBUG_4 0x0F2A +#define mmRB_FLAG_CONTROL 0x0F2B +#define mmRB_BC_SPARES 0x0F2C +#define mmBC_DUMMY_CRAYRB_ENUMS 0x0F15 +#define mmBC_DUMMY_CRAYRB_MOREENUMS 0x0F16 +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_random.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_random.h new file mode 100644 index 000000000000..17379dcfa0e7 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_random.h @@ -0,0 +1,223 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_RANDOM_HEADER) +#define _yamato_RANDOM_HEADER + +/************************************************************* + * THIS FILE IS AUTOMATICALLY CREATED. DO NOT EDIT THIS FILE. + *************************************************************/ +/******************************************************* + * PA Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * VGT Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * TP Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * TC Enums + *******************************************************/ +/******************************************************* + * SQ Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * SX Enums + *******************************************************/ +/******************************************************* + * MH Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * RBBM Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * CP Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +/******************************************************* + * SC Enums + *******************************************************/ +/******************************************************* + * BC Enums + *******************************************************/ +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +template class DllImportExport_RANDOM RANDOM_TEMPLATE_ENUM; + +#endif /*_yamato_RANDOM_HEADER*/ + diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_registers.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_registers.h new file mode 100644 index 000000000000..bcc28f133b08 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_registers.h @@ -0,0 +1,14280 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_REG_HEADER) +#define _yamato_REG_HEADER + + union PA_CL_VPORT_XSCALE { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_XSCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_XSCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_XOFFSET { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_XOFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_XOFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_YSCALE { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_YSCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_YSCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_YOFFSET { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_YOFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_YOFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_ZSCALE { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_ZSCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_ZSCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VPORT_ZOFFSET { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_ZOFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VPORT_ZOFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_VTE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int VPORT_X_SCALE_ENA : 1; + unsigned int VPORT_X_OFFSET_ENA : 1; + unsigned int VPORT_Y_SCALE_ENA : 1; + unsigned int VPORT_Y_OFFSET_ENA : 1; + unsigned int VPORT_Z_SCALE_ENA : 1; + unsigned int VPORT_Z_OFFSET_ENA : 1; + unsigned int : 2; + unsigned int VTX_XY_FMT : 1; + unsigned int VTX_Z_FMT : 1; + unsigned int VTX_W0_FMT : 1; + unsigned int PERFCOUNTER_REF : 1; + unsigned int : 20; +#else /* !defined(qLittleEndian) */ + unsigned int : 20; + unsigned int PERFCOUNTER_REF : 1; + unsigned int VTX_W0_FMT : 1; + unsigned int VTX_Z_FMT : 1; + unsigned int VTX_XY_FMT : 1; + unsigned int : 2; + unsigned int VPORT_Z_OFFSET_ENA : 1; + unsigned int VPORT_Z_SCALE_ENA : 1; + unsigned int VPORT_Y_OFFSET_ENA : 1; + unsigned int VPORT_Y_SCALE_ENA : 1; + unsigned int VPORT_X_OFFSET_ENA : 1; + unsigned int VPORT_X_SCALE_ENA : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_CLIP_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int : 16; + unsigned int CLIP_DISABLE : 1; + unsigned int : 1; + unsigned int BOUNDARY_EDGE_FLAG_ENA : 1; + unsigned int DX_CLIP_SPACE_DEF : 1; + unsigned int DIS_CLIP_ERR_DETECT : 1; + unsigned int VTX_KILL_OR : 1; + unsigned int XY_NAN_RETAIN : 1; + unsigned int Z_NAN_RETAIN : 1; + unsigned int W_NAN_RETAIN : 1; + unsigned int : 7; +#else /* !defined(qLittleEndian) */ + unsigned int : 7; + unsigned int W_NAN_RETAIN : 1; + unsigned int Z_NAN_RETAIN : 1; + unsigned int XY_NAN_RETAIN : 1; + unsigned int VTX_KILL_OR : 1; + unsigned int DIS_CLIP_ERR_DETECT : 1; + unsigned int DX_CLIP_SPACE_DEF : 1; + unsigned int BOUNDARY_EDGE_FLAG_ENA : 1; + unsigned int : 1; + unsigned int CLIP_DISABLE : 1; + unsigned int : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_GB_VERT_CLIP_ADJ { + struct { +#if defined(qLittleEndian) + unsigned int DATA_REGISTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA_REGISTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_GB_VERT_DISC_ADJ { + struct { +#if defined(qLittleEndian) + unsigned int DATA_REGISTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA_REGISTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_GB_HORZ_CLIP_ADJ { + struct { +#if defined(qLittleEndian) + unsigned int DATA_REGISTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA_REGISTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_GB_HORZ_DISC_ADJ { + struct { +#if defined(qLittleEndian) + unsigned int DATA_REGISTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA_REGISTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_ENHANCE { + struct { +#if defined(qLittleEndian) + unsigned int CLIP_VTX_REORDER_ENA : 1; + unsigned int : 27; + unsigned int ECO_SPARE3 : 1; + unsigned int ECO_SPARE2 : 1; + unsigned int ECO_SPARE1 : 1; + unsigned int ECO_SPARE0 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int ECO_SPARE0 : 1; + unsigned int ECO_SPARE1 : 1; + unsigned int ECO_SPARE2 : 1; + unsigned int ECO_SPARE3 : 1; + unsigned int : 27; + unsigned int CLIP_VTX_REORDER_ENA : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_ENHANCE { + struct { +#if defined(qLittleEndian) + unsigned int : 28; + unsigned int ECO_SPARE3 : 1; + unsigned int ECO_SPARE2 : 1; + unsigned int ECO_SPARE1 : 1; + unsigned int ECO_SPARE0 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int ECO_SPARE0 : 1; + unsigned int ECO_SPARE1 : 1; + unsigned int ECO_SPARE2 : 1; + unsigned int ECO_SPARE3 : 1; + unsigned int : 28; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_VTX_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int PIX_CENTER : 1; + unsigned int ROUND_MODE : 2; + unsigned int QUANT_MODE : 3; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int QUANT_MODE : 3; + unsigned int ROUND_MODE : 2; + unsigned int PIX_CENTER : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POINT_SIZE { + struct { +#if defined(qLittleEndian) + unsigned int HEIGHT : 16; + unsigned int WIDTH : 16; +#else /* !defined(qLittleEndian) */ + unsigned int WIDTH : 16; + unsigned int HEIGHT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POINT_MINMAX { + struct { +#if defined(qLittleEndian) + unsigned int MIN_SIZE : 16; + unsigned int MAX_SIZE : 16; +#else /* !defined(qLittleEndian) */ + unsigned int MAX_SIZE : 16; + unsigned int MIN_SIZE : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_LINE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int WIDTH : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int WIDTH : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_FACE_DATA { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int BASE_ADDR : 27; +#else /* !defined(qLittleEndian) */ + unsigned int BASE_ADDR : 27; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_SC_MODE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int CULL_FRONT : 1; + unsigned int CULL_BACK : 1; + unsigned int FACE : 1; + unsigned int POLY_MODE : 2; + unsigned int POLYMODE_FRONT_PTYPE : 3; + unsigned int POLYMODE_BACK_PTYPE : 3; + unsigned int POLY_OFFSET_FRONT_ENABLE : 1; + unsigned int POLY_OFFSET_BACK_ENABLE : 1; + unsigned int POLY_OFFSET_PARA_ENABLE : 1; + unsigned int : 1; + unsigned int MSAA_ENABLE : 1; + unsigned int VTX_WINDOW_OFFSET_ENABLE : 1; + unsigned int : 1; + unsigned int LINE_STIPPLE_ENABLE : 1; + unsigned int PROVOKING_VTX_LAST : 1; + unsigned int PERSP_CORR_DIS : 1; + unsigned int MULTI_PRIM_IB_ENA : 1; + unsigned int : 1; + unsigned int QUAD_ORDER_ENABLE : 1; + unsigned int : 1; + unsigned int WAIT_RB_IDLE_ALL_TRI : 1; + unsigned int WAIT_RB_IDLE_FIRST_TRI_NEW_STATE : 1; + unsigned int : 1; + unsigned int CLAMPED_FACENESS : 1; + unsigned int ZERO_AREA_FACENESS : 1; + unsigned int FACE_KILL_ENABLE : 1; + unsigned int FACE_WRITE_ENABLE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int FACE_WRITE_ENABLE : 1; + unsigned int FACE_KILL_ENABLE : 1; + unsigned int ZERO_AREA_FACENESS : 1; + unsigned int CLAMPED_FACENESS : 1; + unsigned int : 1; + unsigned int WAIT_RB_IDLE_FIRST_TRI_NEW_STATE : 1; + unsigned int WAIT_RB_IDLE_ALL_TRI : 1; + unsigned int : 1; + unsigned int QUAD_ORDER_ENABLE : 1; + unsigned int : 1; + unsigned int MULTI_PRIM_IB_ENA : 1; + unsigned int PERSP_CORR_DIS : 1; + unsigned int PROVOKING_VTX_LAST : 1; + unsigned int LINE_STIPPLE_ENABLE : 1; + unsigned int : 1; + unsigned int VTX_WINDOW_OFFSET_ENABLE : 1; + unsigned int MSAA_ENABLE : 1; + unsigned int : 1; + unsigned int POLY_OFFSET_PARA_ENABLE : 1; + unsigned int POLY_OFFSET_BACK_ENABLE : 1; + unsigned int POLY_OFFSET_FRONT_ENABLE : 1; + unsigned int POLYMODE_BACK_PTYPE : 3; + unsigned int POLYMODE_FRONT_PTYPE : 3; + unsigned int POLY_MODE : 2; + unsigned int FACE : 1; + unsigned int CULL_BACK : 1; + unsigned int CULL_FRONT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POLY_OFFSET_FRONT_SCALE { + struct { +#if defined(qLittleEndian) + unsigned int SCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POLY_OFFSET_FRONT_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int OFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int OFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POLY_OFFSET_BACK_SCALE { + struct { +#if defined(qLittleEndian) + unsigned int SCALE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCALE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_POLY_OFFSET_BACK_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int OFFSET : 32; +#else /* !defined(qLittleEndian) */ + unsigned int OFFSET : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER2_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER3_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER2_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER2_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER3_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_PERFCOUNTER3_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_WINDOW_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int WINDOW_X_OFFSET : 15; + unsigned int : 1; + unsigned int WINDOW_Y_OFFSET : 15; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int WINDOW_Y_OFFSET : 15; + unsigned int : 1; + unsigned int WINDOW_X_OFFSET : 15; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_AA_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int MSAA_NUM_SAMPLES : 3; + unsigned int : 10; + unsigned int MAX_SAMPLE_DIST : 4; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int MAX_SAMPLE_DIST : 4; + unsigned int : 10; + unsigned int MSAA_NUM_SAMPLES : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_AA_MASK { + struct { +#if defined(qLittleEndian) + unsigned int AA_MASK : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int AA_MASK : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_LINE_STIPPLE { + struct { +#if defined(qLittleEndian) + unsigned int LINE_PATTERN : 16; + unsigned int REPEAT_COUNT : 8; + unsigned int : 4; + unsigned int PATTERN_BIT_ORDER : 1; + unsigned int AUTO_RESET_CNTL : 2; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int AUTO_RESET_CNTL : 2; + unsigned int PATTERN_BIT_ORDER : 1; + unsigned int : 4; + unsigned int REPEAT_COUNT : 8; + unsigned int LINE_PATTERN : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_LINE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int BRES_CNTL : 8; + unsigned int USE_BRES_CNTL : 1; + unsigned int EXPAND_LINE_WIDTH : 1; + unsigned int LAST_PIXEL : 1; + unsigned int : 21; +#else /* !defined(qLittleEndian) */ + unsigned int : 21; + unsigned int LAST_PIXEL : 1; + unsigned int EXPAND_LINE_WIDTH : 1; + unsigned int USE_BRES_CNTL : 1; + unsigned int BRES_CNTL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_WINDOW_SCISSOR_TL { + struct { +#if defined(qLittleEndian) + unsigned int TL_X : 14; + unsigned int : 2; + unsigned int TL_Y : 14; + unsigned int : 1; + unsigned int WINDOW_OFFSET_DISABLE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int WINDOW_OFFSET_DISABLE : 1; + unsigned int : 1; + unsigned int TL_Y : 14; + unsigned int : 2; + unsigned int TL_X : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_WINDOW_SCISSOR_BR { + struct { +#if defined(qLittleEndian) + unsigned int BR_X : 14; + unsigned int : 2; + unsigned int BR_Y : 14; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int BR_Y : 14; + unsigned int : 2; + unsigned int BR_X : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_SCREEN_SCISSOR_TL { + struct { +#if defined(qLittleEndian) + unsigned int TL_X : 15; + unsigned int : 1; + unsigned int TL_Y : 15; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int TL_Y : 15; + unsigned int : 1; + unsigned int TL_X : 15; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_SCREEN_SCISSOR_BR { + struct { +#if defined(qLittleEndian) + unsigned int BR_X : 15; + unsigned int : 1; + unsigned int BR_Y : 15; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int BR_Y : 15; + unsigned int : 1; + unsigned int BR_X : 15; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_VIZ_QUERY { + struct { +#if defined(qLittleEndian) + unsigned int VIZ_QUERY_ENA : 1; + unsigned int VIZ_QUERY_ID : 5; + unsigned int : 1; + unsigned int KILL_PIX_POST_EARLY_Z : 1; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int KILL_PIX_POST_EARLY_Z : 1; + unsigned int : 1; + unsigned int VIZ_QUERY_ID : 5; + unsigned int VIZ_QUERY_ENA : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_VIZ_QUERY_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int STATUS_BITS : 32; +#else /* !defined(qLittleEndian) */ + unsigned int STATUS_BITS : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_LINE_STIPPLE_STATE { + struct { +#if defined(qLittleEndian) + unsigned int CURRENT_PTR : 4; + unsigned int : 4; + unsigned int CURRENT_COUNT : 8; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int CURRENT_COUNT : 8; + unsigned int : 4; + unsigned int CURRENT_PTR : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_CL_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int : 31; + unsigned int CL_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int CL_BUSY : 1; + unsigned int : 31; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int : 31; + unsigned int SU_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int SU_BUSY : 1; + unsigned int : 31; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int : 31; + unsigned int SC_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int SC_BUSY : 1; + unsigned int : 31; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_DEBUG_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int SU_DEBUG_INDX : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int SU_DEBUG_INDX : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SU_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG00 { + struct { +#if defined(qLittleEndian) + unsigned int clip_ga_bc_fifo_write : 1; + unsigned int clip_ga_bc_fifo_full : 1; + unsigned int clip_to_ga_fifo_write : 1; + unsigned int clip_to_ga_fifo_full : 1; + unsigned int primic_to_clprim_fifo_empty : 1; + unsigned int primic_to_clprim_fifo_full : 1; + unsigned int clip_to_outsm_fifo_empty : 1; + unsigned int clip_to_outsm_fifo_full : 1; + unsigned int vgt_to_clipp_fifo_empty : 1; + unsigned int vgt_to_clipp_fifo_full : 1; + unsigned int vgt_to_clips_fifo_empty : 1; + unsigned int vgt_to_clips_fifo_full : 1; + unsigned int clipcode_fifo_fifo_empty : 1; + unsigned int clipcode_fifo_full : 1; + unsigned int vte_out_clip_fifo_fifo_empty : 1; + unsigned int vte_out_clip_fifo_fifo_full : 1; + unsigned int vte_out_orig_fifo_fifo_empty : 1; + unsigned int vte_out_orig_fifo_fifo_full : 1; + unsigned int ccgen_to_clipcc_fifo_empty : 1; + unsigned int ccgen_to_clipcc_fifo_full : 1; + unsigned int ALWAYS_ZERO : 12; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO : 12; + unsigned int ccgen_to_clipcc_fifo_full : 1; + unsigned int ccgen_to_clipcc_fifo_empty : 1; + unsigned int vte_out_orig_fifo_fifo_full : 1; + unsigned int vte_out_orig_fifo_fifo_empty : 1; + unsigned int vte_out_clip_fifo_fifo_full : 1; + unsigned int vte_out_clip_fifo_fifo_empty : 1; + unsigned int clipcode_fifo_full : 1; + unsigned int clipcode_fifo_fifo_empty : 1; + unsigned int vgt_to_clips_fifo_full : 1; + unsigned int vgt_to_clips_fifo_empty : 1; + unsigned int vgt_to_clipp_fifo_full : 1; + unsigned int vgt_to_clipp_fifo_empty : 1; + unsigned int clip_to_outsm_fifo_full : 1; + unsigned int clip_to_outsm_fifo_empty : 1; + unsigned int primic_to_clprim_fifo_full : 1; + unsigned int primic_to_clprim_fifo_empty : 1; + unsigned int clip_to_ga_fifo_full : 1; + unsigned int clip_to_ga_fifo_write : 1; + unsigned int clip_ga_bc_fifo_full : 1; + unsigned int clip_ga_bc_fifo_write : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG01 { + struct { +#if defined(qLittleEndian) + unsigned int clip_to_outsm_end_of_packet : 1; + unsigned int clip_to_outsm_first_prim_of_slot : 1; + unsigned int clip_to_outsm_deallocate_slot : 3; + unsigned int clip_to_outsm_clipped_prim : 1; + unsigned int clip_to_outsm_null_primitive : 1; + unsigned int clip_to_outsm_vertex_store_indx_2 : 4; + unsigned int clip_to_outsm_vertex_store_indx_1 : 4; + unsigned int clip_to_outsm_vertex_store_indx_0 : 4; + unsigned int clip_vert_vte_valid : 3; + unsigned int vte_out_clip_rd_vertex_store_indx : 2; + unsigned int ALWAYS_ZERO : 8; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO : 8; + unsigned int vte_out_clip_rd_vertex_store_indx : 2; + unsigned int clip_vert_vte_valid : 3; + unsigned int clip_to_outsm_vertex_store_indx_0 : 4; + unsigned int clip_to_outsm_vertex_store_indx_1 : 4; + unsigned int clip_to_outsm_vertex_store_indx_2 : 4; + unsigned int clip_to_outsm_null_primitive : 1; + unsigned int clip_to_outsm_clipped_prim : 1; + unsigned int clip_to_outsm_deallocate_slot : 3; + unsigned int clip_to_outsm_first_prim_of_slot : 1; + unsigned int clip_to_outsm_end_of_packet : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG02 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO1 : 21; + unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : 3; + unsigned int ALWAYS_ZERO0 : 7; + unsigned int clipsm0_clprim_to_clip_prim_valid : 1; +#else /* !defined(qLittleEndian) */ + unsigned int clipsm0_clprim_to_clip_prim_valid : 1; + unsigned int ALWAYS_ZERO0 : 7; + unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : 3; + unsigned int ALWAYS_ZERO1 : 21; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG03 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO3 : 3; + unsigned int clipsm0_clprim_to_clip_clip_primitive : 1; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clipsm0_clprim_to_clip_null_primitive : 1; + unsigned int ALWAYS_ZERO1 : 12; + unsigned int clipsm0_clprim_to_clip_clip_code_or : 6; + unsigned int ALWAYS_ZERO0 : 6; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 6; + unsigned int clipsm0_clprim_to_clip_clip_code_or : 6; + unsigned int ALWAYS_ZERO1 : 12; + unsigned int clipsm0_clprim_to_clip_null_primitive : 1; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clipsm0_clprim_to_clip_clip_primitive : 1; + unsigned int ALWAYS_ZERO3 : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG04 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : 1; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int clipsm0_clprim_to_clip_event : 1; + unsigned int ALWAYS_ZERO0 : 24; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 24; + unsigned int clipsm0_clprim_to_clip_event : 1; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : 1; + unsigned int ALWAYS_ZERO2 : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG05 { + struct { +#if defined(qLittleEndian) + unsigned int clipsm0_clprim_to_clip_state_var_indx : 1; + unsigned int ALWAYS_ZERO3 : 2; + unsigned int clipsm0_clprim_to_clip_deallocate_slot : 3; + unsigned int clipsm0_clprim_to_clip_event_id : 6; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO0 : 4; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 4; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : 4; + unsigned int clipsm0_clprim_to_clip_event_id : 6; + unsigned int clipsm0_clprim_to_clip_deallocate_slot : 3; + unsigned int ALWAYS_ZERO3 : 2; + unsigned int clipsm0_clprim_to_clip_state_var_indx : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG09 { + struct { +#if defined(qLittleEndian) + unsigned int clprim_in_back_event : 1; + unsigned int outputclprimtoclip_null_primitive : 1; + unsigned int clprim_in_back_vertex_store_indx_2 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int clprim_in_back_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clprim_in_back_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int prim_back_valid : 1; + unsigned int clip_priority_seq_indx_out_cnt : 4; + unsigned int outsm_clr_rd_orig_vertices : 2; + unsigned int outsm_clr_rd_clipsm_wait : 1; + unsigned int outsm_clr_fifo_empty : 1; + unsigned int outsm_clr_fifo_full : 1; + unsigned int clip_priority_seq_indx_load : 2; +#else /* !defined(qLittleEndian) */ + unsigned int clip_priority_seq_indx_load : 2; + unsigned int outsm_clr_fifo_full : 1; + unsigned int outsm_clr_fifo_empty : 1; + unsigned int outsm_clr_rd_clipsm_wait : 1; + unsigned int outsm_clr_rd_orig_vertices : 2; + unsigned int clip_priority_seq_indx_out_cnt : 4; + unsigned int prim_back_valid : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int clprim_in_back_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clprim_in_back_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int clprim_in_back_vertex_store_indx_2 : 4; + unsigned int outputclprimtoclip_null_primitive : 1; + unsigned int clprim_in_back_event : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG10 { + struct { +#if defined(qLittleEndian) + unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : 4; + unsigned int ALWAYS_ZERO3 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int clprim_in_back_state_var_indx : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int clprim_in_back_end_of_packet : 1; + unsigned int clprim_in_back_first_prim_of_slot : 1; + unsigned int clprim_in_back_deallocate_slot : 3; + unsigned int clprim_in_back_event_id : 6; +#else /* !defined(qLittleEndian) */ + unsigned int clprim_in_back_event_id : 6; + unsigned int clprim_in_back_deallocate_slot : 3; + unsigned int clprim_in_back_first_prim_of_slot : 1; + unsigned int clprim_in_back_end_of_packet : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int clprim_in_back_state_var_indx : 1; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : 4; + unsigned int ALWAYS_ZERO2 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : 4; + unsigned int ALWAYS_ZERO3 : 2; + unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG11 { + struct { +#if defined(qLittleEndian) + unsigned int vertval_bits_vertex_vertex_store_msb : 4; + unsigned int ALWAYS_ZERO : 28; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO : 28; + unsigned int vertval_bits_vertex_vertex_store_msb : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG12 { + struct { +#if defined(qLittleEndian) + unsigned int clip_priority_available_vte_out_clip : 2; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clip_vertex_fifo_empty : 1; + unsigned int clip_priority_available_clip_verts : 5; + unsigned int ALWAYS_ZERO1 : 4; + unsigned int vertval_bits_vertex_cc_next_valid : 4; + unsigned int clipcc_vertex_store_indx : 2; + unsigned int primic_to_clprim_valid : 1; + unsigned int ALWAYS_ZERO0 : 10; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 10; + unsigned int primic_to_clprim_valid : 1; + unsigned int clipcc_vertex_store_indx : 2; + unsigned int vertval_bits_vertex_cc_next_valid : 4; + unsigned int ALWAYS_ZERO1 : 4; + unsigned int clip_priority_available_clip_verts : 5; + unsigned int clip_vertex_fifo_empty : 1; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int clip_priority_available_vte_out_clip : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CLIPPER_DEBUG_REG13 { + struct { +#if defined(qLittleEndian) + unsigned int sm0_clip_vert_cnt : 4; + unsigned int sm0_prim_end_state : 7; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int sm0_vertex_clip_cnt : 4; + unsigned int sm0_inv_to_clip_data_valid_1 : 1; + unsigned int sm0_inv_to_clip_data_valid_0 : 1; + unsigned int sm0_current_state : 7; + unsigned int ALWAYS_ZERO0 : 5; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 5; + unsigned int sm0_current_state : 7; + unsigned int sm0_inv_to_clip_data_valid_0 : 1; + unsigned int sm0_inv_to_clip_data_valid_1 : 1; + unsigned int sm0_vertex_clip_cnt : 4; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int sm0_prim_end_state : 7; + unsigned int sm0_clip_vert_cnt : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SXIFCCG_DEBUG_REG0 { + struct { +#if defined(qLittleEndian) + unsigned int nan_kill_flag : 4; + unsigned int position_address : 3; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int point_address : 3; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int sx_pending_rd_state_var_indx : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int sx_pending_rd_req_mask : 4; + unsigned int sx_pending_rd_pci : 7; + unsigned int sx_pending_rd_aux_inc : 1; + unsigned int sx_pending_rd_aux_sel : 1; +#else /* !defined(qLittleEndian) */ + unsigned int sx_pending_rd_aux_sel : 1; + unsigned int sx_pending_rd_aux_inc : 1; + unsigned int sx_pending_rd_pci : 7; + unsigned int sx_pending_rd_req_mask : 4; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int sx_pending_rd_state_var_indx : 1; + unsigned int ALWAYS_ZERO1 : 3; + unsigned int point_address : 3; + unsigned int ALWAYS_ZERO2 : 3; + unsigned int position_address : 3; + unsigned int nan_kill_flag : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SXIFCCG_DEBUG_REG1 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO3 : 2; + unsigned int sx_to_pa_empty : 2; + unsigned int available_positions : 3; + unsigned int ALWAYS_ZERO2 : 4; + unsigned int sx_pending_advance : 1; + unsigned int sx_receive_indx : 3; + unsigned int statevar_bits_sxpa_aux_vector : 1; + unsigned int ALWAYS_ZERO1 : 4; + unsigned int aux_sel : 1; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int pasx_req_cnt : 2; + unsigned int param_cache_base : 7; +#else /* !defined(qLittleEndian) */ + unsigned int param_cache_base : 7; + unsigned int pasx_req_cnt : 2; + unsigned int ALWAYS_ZERO0 : 2; + unsigned int aux_sel : 1; + unsigned int ALWAYS_ZERO1 : 4; + unsigned int statevar_bits_sxpa_aux_vector : 1; + unsigned int sx_receive_indx : 3; + unsigned int sx_pending_advance : 1; + unsigned int ALWAYS_ZERO2 : 4; + unsigned int available_positions : 3; + unsigned int sx_to_pa_empty : 2; + unsigned int ALWAYS_ZERO3 : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SXIFCCG_DEBUG_REG2 { + struct { +#if defined(qLittleEndian) + unsigned int sx_sent : 1; + unsigned int ALWAYS_ZERO3 : 1; + unsigned int sx_aux : 1; + unsigned int sx_request_indx : 6; + unsigned int req_active_verts : 7; + unsigned int ALWAYS_ZERO2 : 1; + unsigned int vgt_to_ccgen_state_var_indx : 1; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int vgt_to_ccgen_active_verts : 2; + unsigned int ALWAYS_ZERO0 : 4; + unsigned int req_active_verts_loaded : 1; + unsigned int sx_pending_fifo_empty : 1; + unsigned int sx_pending_fifo_full : 1; + unsigned int sx_pending_fifo_contents : 3; +#else /* !defined(qLittleEndian) */ + unsigned int sx_pending_fifo_contents : 3; + unsigned int sx_pending_fifo_full : 1; + unsigned int sx_pending_fifo_empty : 1; + unsigned int req_active_verts_loaded : 1; + unsigned int ALWAYS_ZERO0 : 4; + unsigned int vgt_to_ccgen_active_verts : 2; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int vgt_to_ccgen_state_var_indx : 1; + unsigned int ALWAYS_ZERO2 : 1; + unsigned int req_active_verts : 7; + unsigned int sx_request_indx : 6; + unsigned int sx_aux : 1; + unsigned int ALWAYS_ZERO3 : 1; + unsigned int sx_sent : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SXIFCCG_DEBUG_REG3 { + struct { +#if defined(qLittleEndian) + unsigned int vertex_fifo_entriesavailable : 4; + unsigned int ALWAYS_ZERO3 : 1; + unsigned int available_positions : 3; + unsigned int ALWAYS_ZERO2 : 4; + unsigned int current_state : 2; + unsigned int vertex_fifo_empty : 1; + unsigned int vertex_fifo_full : 1; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int sx0_receive_fifo_empty : 1; + unsigned int sx0_receive_fifo_full : 1; + unsigned int vgt_to_ccgen_fifo_empty : 1; + unsigned int vgt_to_ccgen_fifo_full : 1; + unsigned int ALWAYS_ZERO0 : 10; +#else /* !defined(qLittleEndian) */ + unsigned int ALWAYS_ZERO0 : 10; + unsigned int vgt_to_ccgen_fifo_full : 1; + unsigned int vgt_to_ccgen_fifo_empty : 1; + unsigned int sx0_receive_fifo_full : 1; + unsigned int sx0_receive_fifo_empty : 1; + unsigned int ALWAYS_ZERO1 : 2; + unsigned int vertex_fifo_full : 1; + unsigned int vertex_fifo_empty : 1; + unsigned int current_state : 2; + unsigned int ALWAYS_ZERO2 : 4; + unsigned int available_positions : 3; + unsigned int ALWAYS_ZERO3 : 1; + unsigned int vertex_fifo_entriesavailable : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG0 { + struct { +#if defined(qLittleEndian) + unsigned int su_cntl_state : 5; + unsigned int pmode_state : 6; + unsigned int ge_stallb : 1; + unsigned int geom_enable : 1; + unsigned int su_clip_baryc_rtr : 1; + unsigned int su_clip_rtr : 1; + unsigned int pfifo_busy : 1; + unsigned int su_cntl_busy : 1; + unsigned int geom_busy : 1; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int geom_busy : 1; + unsigned int su_cntl_busy : 1; + unsigned int pfifo_busy : 1; + unsigned int su_clip_rtr : 1; + unsigned int su_clip_baryc_rtr : 1; + unsigned int geom_enable : 1; + unsigned int ge_stallb : 1; + unsigned int pmode_state : 6; + unsigned int su_cntl_state : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG1 { + struct { +#if defined(qLittleEndian) + unsigned int y_sort0_gated_17_4 : 14; + unsigned int x_sort0_gated_17_4 : 14; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int x_sort0_gated_17_4 : 14; + unsigned int y_sort0_gated_17_4 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG2 { + struct { +#if defined(qLittleEndian) + unsigned int y_sort1_gated_17_4 : 14; + unsigned int x_sort1_gated_17_4 : 14; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int x_sort1_gated_17_4 : 14; + unsigned int y_sort1_gated_17_4 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG3 { + struct { +#if defined(qLittleEndian) + unsigned int y_sort2_gated_17_4 : 14; + unsigned int x_sort2_gated_17_4 : 14; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int x_sort2_gated_17_4 : 14; + unsigned int y_sort2_gated_17_4 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG4 { + struct { +#if defined(qLittleEndian) + unsigned int attr_indx_sort0_gated : 11; + unsigned int null_prim_gated : 1; + unsigned int backfacing_gated : 1; + unsigned int st_indx_gated : 3; + unsigned int clipped_gated : 1; + unsigned int dealloc_slot_gated : 3; + unsigned int xmajor_gated : 1; + unsigned int diamond_rule_gated : 2; + unsigned int type_gated : 3; + unsigned int fpov_gated : 1; + unsigned int pmode_prim_gated : 1; + unsigned int event_gated : 1; + unsigned int eop_gated : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int eop_gated : 1; + unsigned int event_gated : 1; + unsigned int pmode_prim_gated : 1; + unsigned int fpov_gated : 1; + unsigned int type_gated : 3; + unsigned int diamond_rule_gated : 2; + unsigned int xmajor_gated : 1; + unsigned int dealloc_slot_gated : 3; + unsigned int clipped_gated : 1; + unsigned int st_indx_gated : 3; + unsigned int backfacing_gated : 1; + unsigned int null_prim_gated : 1; + unsigned int attr_indx_sort0_gated : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SETUP_DEBUG_REG5 { + struct { +#if defined(qLittleEndian) + unsigned int attr_indx_sort2_gated : 11; + unsigned int attr_indx_sort1_gated : 11; + unsigned int provoking_vtx_gated : 2; + unsigned int event_id_gated : 5; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int event_id_gated : 5; + unsigned int provoking_vtx_gated : 2; + unsigned int attr_indx_sort1_gated : 11; + unsigned int attr_indx_sort2_gated : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_DEBUG_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int SC_DEBUG_INDX : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int SC_DEBUG_INDX : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union PA_SC_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_0 { + struct { +#if defined(qLittleEndian) + unsigned int pa_freeze_b1 : 1; + unsigned int pa_sc_valid : 1; + unsigned int pa_sc_phase : 3; + unsigned int cntx_cnt : 7; + unsigned int decr_cntx_cnt : 1; + unsigned int incr_cntx_cnt : 1; + unsigned int : 17; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 17; + unsigned int incr_cntx_cnt : 1; + unsigned int decr_cntx_cnt : 1; + unsigned int cntx_cnt : 7; + unsigned int pa_sc_phase : 3; + unsigned int pa_sc_valid : 1; + unsigned int pa_freeze_b1 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_1 { + struct { +#if defined(qLittleEndian) + unsigned int em_state : 3; + unsigned int em1_data_ready : 1; + unsigned int em2_data_ready : 1; + unsigned int move_em1_to_em2 : 1; + unsigned int ef_data_ready : 1; + unsigned int ef_state : 2; + unsigned int pipe_valid : 1; + unsigned int : 21; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 21; + unsigned int pipe_valid : 1; + unsigned int ef_state : 2; + unsigned int ef_data_ready : 1; + unsigned int move_em1_to_em2 : 1; + unsigned int em2_data_ready : 1; + unsigned int em1_data_ready : 1; + unsigned int em_state : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_2 { + struct { +#if defined(qLittleEndian) + unsigned int rc_rtr_dly : 1; + unsigned int qmask_ff_alm_full_d1 : 1; + unsigned int : 1; + unsigned int pipe_freeze_b : 1; + unsigned int prim_rts : 1; + unsigned int next_prim_rts_dly : 1; + unsigned int next_prim_rtr_dly : 1; + unsigned int pre_stage1_rts_d1 : 1; + unsigned int stage0_rts : 1; + unsigned int phase_rts_dly : 1; + unsigned int : 5; + unsigned int end_of_prim_s1_dly : 1; + unsigned int pass_empty_prim_s1 : 1; + unsigned int event_id_s1 : 5; + unsigned int event_s1 : 1; + unsigned int : 8; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 8; + unsigned int event_s1 : 1; + unsigned int event_id_s1 : 5; + unsigned int pass_empty_prim_s1 : 1; + unsigned int end_of_prim_s1_dly : 1; + unsigned int : 5; + unsigned int phase_rts_dly : 1; + unsigned int stage0_rts : 1; + unsigned int pre_stage1_rts_d1 : 1; + unsigned int next_prim_rtr_dly : 1; + unsigned int next_prim_rts_dly : 1; + unsigned int prim_rts : 1; + unsigned int pipe_freeze_b : 1; + unsigned int : 1; + unsigned int qmask_ff_alm_full_d1 : 1; + unsigned int rc_rtr_dly : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_3 { + struct { +#if defined(qLittleEndian) + unsigned int x_curr_s1 : 11; + unsigned int y_curr_s1 : 11; + unsigned int : 9; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 9; + unsigned int y_curr_s1 : 11; + unsigned int x_curr_s1 : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_4 { + struct { +#if defined(qLittleEndian) + unsigned int y_end_s1 : 14; + unsigned int y_start_s1 : 14; + unsigned int y_dir_s1 : 1; + unsigned int : 2; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 2; + unsigned int y_dir_s1 : 1; + unsigned int y_start_s1 : 14; + unsigned int y_end_s1 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_5 { + struct { +#if defined(qLittleEndian) + unsigned int x_end_s1 : 14; + unsigned int x_start_s1 : 14; + unsigned int x_dir_s1 : 1; + unsigned int : 2; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 2; + unsigned int x_dir_s1 : 1; + unsigned int x_start_s1 : 14; + unsigned int x_end_s1 : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_6 { + struct { +#if defined(qLittleEndian) + unsigned int z_ff_empty : 1; + unsigned int qmcntl_ff_empty : 1; + unsigned int xy_ff_empty : 1; + unsigned int event_flag : 1; + unsigned int z_mask_needed : 1; + unsigned int state : 3; + unsigned int state_delayed : 3; + unsigned int data_valid : 1; + unsigned int data_valid_d : 1; + unsigned int tilex_delayed : 9; + unsigned int tiley_delayed : 9; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int tiley_delayed : 9; + unsigned int tilex_delayed : 9; + unsigned int data_valid_d : 1; + unsigned int data_valid : 1; + unsigned int state_delayed : 3; + unsigned int state : 3; + unsigned int z_mask_needed : 1; + unsigned int event_flag : 1; + unsigned int xy_ff_empty : 1; + unsigned int qmcntl_ff_empty : 1; + unsigned int z_ff_empty : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_7 { + struct { +#if defined(qLittleEndian) + unsigned int event_flag : 1; + unsigned int deallocate : 3; + unsigned int fposition : 1; + unsigned int sr_prim_we : 1; + unsigned int last_tile : 1; + unsigned int tile_ff_we : 1; + unsigned int qs_data_valid : 1; + unsigned int qs_q0_y : 2; + unsigned int qs_q0_x : 2; + unsigned int qs_q0_valid : 1; + unsigned int prim_ff_we : 1; + unsigned int tile_ff_re : 1; + unsigned int fw_prim_data_valid : 1; + unsigned int last_quad_of_tile : 1; + unsigned int first_quad_of_tile : 1; + unsigned int first_quad_of_prim : 1; + unsigned int new_prim : 1; + unsigned int load_new_tile_data : 1; + unsigned int state : 2; + unsigned int fifos_ready : 1; + unsigned int : 6; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 6; + unsigned int fifos_ready : 1; + unsigned int state : 2; + unsigned int load_new_tile_data : 1; + unsigned int new_prim : 1; + unsigned int first_quad_of_prim : 1; + unsigned int first_quad_of_tile : 1; + unsigned int last_quad_of_tile : 1; + unsigned int fw_prim_data_valid : 1; + unsigned int tile_ff_re : 1; + unsigned int prim_ff_we : 1; + unsigned int qs_q0_valid : 1; + unsigned int qs_q0_x : 2; + unsigned int qs_q0_y : 2; + unsigned int qs_data_valid : 1; + unsigned int tile_ff_we : 1; + unsigned int last_tile : 1; + unsigned int sr_prim_we : 1; + unsigned int fposition : 1; + unsigned int deallocate : 3; + unsigned int event_flag : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_8 { + struct { +#if defined(qLittleEndian) + unsigned int sample_last : 1; + unsigned int sample_mask : 4; + unsigned int sample_y : 2; + unsigned int sample_x : 2; + unsigned int sample_send : 1; + unsigned int next_cycle : 2; + unsigned int ez_sample_ff_full : 1; + unsigned int rb_sc_samp_rtr : 1; + unsigned int num_samples : 2; + unsigned int last_quad_of_tile : 1; + unsigned int last_quad_of_prim : 1; + unsigned int first_quad_of_prim : 1; + unsigned int sample_we : 1; + unsigned int fposition : 1; + unsigned int event_id : 5; + unsigned int event_flag : 1; + unsigned int fw_prim_data_valid : 1; + unsigned int : 3; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 3; + unsigned int fw_prim_data_valid : 1; + unsigned int event_flag : 1; + unsigned int event_id : 5; + unsigned int fposition : 1; + unsigned int sample_we : 1; + unsigned int first_quad_of_prim : 1; + unsigned int last_quad_of_prim : 1; + unsigned int last_quad_of_tile : 1; + unsigned int num_samples : 2; + unsigned int rb_sc_samp_rtr : 1; + unsigned int ez_sample_ff_full : 1; + unsigned int next_cycle : 2; + unsigned int sample_send : 1; + unsigned int sample_x : 2; + unsigned int sample_y : 2; + unsigned int sample_mask : 4; + unsigned int sample_last : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_9 { + struct { +#if defined(qLittleEndian) + unsigned int rb_sc_send : 1; + unsigned int rb_sc_ez_mask : 4; + unsigned int fifo_data_ready : 1; + unsigned int early_z_enable : 1; + unsigned int mask_state : 2; + unsigned int next_ez_mask : 16; + unsigned int mask_ready : 1; + unsigned int drop_sample : 1; + unsigned int fetch_new_sample_data : 1; + unsigned int fetch_new_ez_sample_mask : 1; + unsigned int pkr_fetch_new_sample_data : 1; + unsigned int pkr_fetch_new_prim_data : 1; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int pkr_fetch_new_prim_data : 1; + unsigned int pkr_fetch_new_sample_data : 1; + unsigned int fetch_new_ez_sample_mask : 1; + unsigned int fetch_new_sample_data : 1; + unsigned int drop_sample : 1; + unsigned int mask_ready : 1; + unsigned int next_ez_mask : 16; + unsigned int mask_state : 2; + unsigned int early_z_enable : 1; + unsigned int fifo_data_ready : 1; + unsigned int rb_sc_ez_mask : 4; + unsigned int rb_sc_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_10 { + struct { +#if defined(qLittleEndian) + unsigned int combined_sample_mask : 16; + unsigned int : 15; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 15; + unsigned int combined_sample_mask : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_11 { + struct { +#if defined(qLittleEndian) + unsigned int ez_sample_data_ready : 1; + unsigned int pkr_fetch_new_sample_data : 1; + unsigned int ez_prim_data_ready : 1; + unsigned int pkr_fetch_new_prim_data : 1; + unsigned int iterator_input_fz : 1; + unsigned int packer_send_quads : 1; + unsigned int packer_send_cmd : 1; + unsigned int packer_send_event : 1; + unsigned int next_state : 3; + unsigned int state : 3; + unsigned int stall : 1; + unsigned int : 16; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 16; + unsigned int stall : 1; + unsigned int state : 3; + unsigned int next_state : 3; + unsigned int packer_send_event : 1; + unsigned int packer_send_cmd : 1; + unsigned int packer_send_quads : 1; + unsigned int iterator_input_fz : 1; + unsigned int pkr_fetch_new_prim_data : 1; + unsigned int ez_prim_data_ready : 1; + unsigned int pkr_fetch_new_sample_data : 1; + unsigned int ez_sample_data_ready : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SC_DEBUG_12 { + struct { +#if defined(qLittleEndian) + unsigned int SQ_iterator_free_buff : 1; + unsigned int event_id : 5; + unsigned int event_flag : 1; + unsigned int itercmdfifo_busy_nc_dly : 1; + unsigned int itercmdfifo_full : 1; + unsigned int itercmdfifo_empty : 1; + unsigned int iter_ds_one_clk_command : 1; + unsigned int iter_ds_end_of_prim0 : 1; + unsigned int iter_ds_end_of_vector : 1; + unsigned int iter_qdhit0 : 1; + unsigned int bc_use_centers_reg : 1; + unsigned int bc_output_xy_reg : 1; + unsigned int iter_phase_out : 2; + unsigned int iter_phase_reg : 2; + unsigned int iterator_SP_valid : 1; + unsigned int eopv_reg : 1; + unsigned int one_clk_cmd_reg : 1; + unsigned int iter_dx_end_of_prim : 1; + unsigned int : 7; + unsigned int trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int trigger : 1; + unsigned int : 7; + unsigned int iter_dx_end_of_prim : 1; + unsigned int one_clk_cmd_reg : 1; + unsigned int eopv_reg : 1; + unsigned int iterator_SP_valid : 1; + unsigned int iter_phase_reg : 2; + unsigned int iter_phase_out : 2; + unsigned int bc_output_xy_reg : 1; + unsigned int bc_use_centers_reg : 1; + unsigned int iter_qdhit0 : 1; + unsigned int iter_ds_end_of_vector : 1; + unsigned int iter_ds_end_of_prim0 : 1; + unsigned int iter_ds_one_clk_command : 1; + unsigned int itercmdfifo_empty : 1; + unsigned int itercmdfifo_full : 1; + unsigned int itercmdfifo_busy_nc_dly : 1; + unsigned int event_flag : 1; + unsigned int event_id : 5; + unsigned int SQ_iterator_free_buff : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union GFX_COPY_STATE { + struct { +#if defined(qLittleEndian) + unsigned int SRC_STATE_ID : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int SRC_STATE_ID : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DRAW_INITIATOR { + struct { +#if defined(qLittleEndian) + unsigned int PRIM_TYPE : 6; + unsigned int SOURCE_SELECT : 2; + unsigned int FACENESS_CULL_SELECT : 2; + unsigned int : 1; + unsigned int INDEX_SIZE : 1; + unsigned int NOT_EOP : 1; + unsigned int SMALL_INDEX : 1; + unsigned int PRE_FETCH_CULL_ENABLE : 1; + unsigned int GRP_CULL_ENABLE : 1; + unsigned int NUM_INDICES : 16; +#else /* !defined(qLittleEndian) */ + unsigned int NUM_INDICES : 16; + unsigned int GRP_CULL_ENABLE : 1; + unsigned int PRE_FETCH_CULL_ENABLE : 1; + unsigned int SMALL_INDEX : 1; + unsigned int NOT_EOP : 1; + unsigned int INDEX_SIZE : 1; + unsigned int : 1; + unsigned int FACENESS_CULL_SELECT : 2; + unsigned int SOURCE_SELECT : 2; + unsigned int PRIM_TYPE : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_EVENT_INITIATOR { + struct { +#if defined(qLittleEndian) + unsigned int EVENT_TYPE : 6; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int EVENT_TYPE : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DMA_BASE { + struct { +#if defined(qLittleEndian) + unsigned int BASE_ADDR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BASE_ADDR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DMA_SIZE { + struct { +#if defined(qLittleEndian) + unsigned int NUM_WORDS : 24; + unsigned int : 6; + unsigned int SWAP_MODE : 2; +#else /* !defined(qLittleEndian) */ + unsigned int SWAP_MODE : 2; + unsigned int : 6; + unsigned int NUM_WORDS : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_BIN_BASE { + struct { +#if defined(qLittleEndian) + unsigned int BIN_BASE_ADDR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_BASE_ADDR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_BIN_SIZE { + struct { +#if defined(qLittleEndian) + unsigned int NUM_WORDS : 24; + unsigned int : 6; + unsigned int FACENESS_FETCH : 1; + unsigned int FACENESS_RESET : 1; +#else /* !defined(qLittleEndian) */ + unsigned int FACENESS_RESET : 1; + unsigned int FACENESS_FETCH : 1; + unsigned int : 6; + unsigned int NUM_WORDS : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CURRENT_BIN_ID_MIN { + struct { +#if defined(qLittleEndian) + unsigned int COLUMN : 3; + unsigned int ROW : 3; + unsigned int GUARD_BAND : 3; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int GUARD_BAND : 3; + unsigned int ROW : 3; + unsigned int COLUMN : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CURRENT_BIN_ID_MAX { + struct { +#if defined(qLittleEndian) + unsigned int COLUMN : 3; + unsigned int ROW : 3; + unsigned int GUARD_BAND : 3; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int GUARD_BAND : 3; + unsigned int ROW : 3; + unsigned int COLUMN : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_IMMED_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_MAX_VTX_INDX { + struct { +#if defined(qLittleEndian) + unsigned int MAX_INDX : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int MAX_INDX : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_MIN_VTX_INDX { + struct { +#if defined(qLittleEndian) + unsigned int MIN_INDX : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int MIN_INDX : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_INDX_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int INDX_OFFSET : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int INDX_OFFSET : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_VERTEX_REUSE_BLOCK_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int VTX_REUSE_DEPTH : 3; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int VTX_REUSE_DEPTH : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_OUT_DEALLOC_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int DEALLOC_DIST : 2; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int DEALLOC_DIST : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_MULTI_PRIM_IB_RESET_INDX { + struct { +#if defined(qLittleEndian) + unsigned int RESET_INDX : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int RESET_INDX : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_ENHANCE { + struct { +#if defined(qLittleEndian) + unsigned int MISC : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int MISC : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_VTX_VECT_EJECT_REG { + struct { +#if defined(qLittleEndian) + unsigned int PRIM_COUNT : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int PRIM_COUNT : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_LAST_COPY_STATE { + struct { +#if defined(qLittleEndian) + unsigned int SRC_STATE_ID : 1; + unsigned int : 15; + unsigned int DST_STATE_ID : 1; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int DST_STATE_ID : 1; + unsigned int : 15; + unsigned int SRC_STATE_ID : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int VGT_DEBUG_INDX : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int VGT_DEBUG_INDX : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int VGT_BUSY : 1; + unsigned int VGT_DMA_BUSY : 1; + unsigned int VGT_DMA_REQ_BUSY : 1; + unsigned int VGT_GRP_BUSY : 1; + unsigned int VGT_VR_BUSY : 1; + unsigned int VGT_BIN_BUSY : 1; + unsigned int VGT_PT_BUSY : 1; + unsigned int VGT_OUT_BUSY : 1; + unsigned int VGT_OUT_INDX_BUSY : 1; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int VGT_OUT_INDX_BUSY : 1; + unsigned int VGT_OUT_BUSY : 1; + unsigned int VGT_PT_BUSY : 1; + unsigned int VGT_BIN_BUSY : 1; + unsigned int VGT_VR_BUSY : 1; + unsigned int VGT_GRP_BUSY : 1; + unsigned int VGT_DMA_REQ_BUSY : 1; + unsigned int VGT_DMA_BUSY : 1; + unsigned int VGT_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG0 { + struct { +#if defined(qLittleEndian) + unsigned int te_grp_busy : 1; + unsigned int pt_grp_busy : 1; + unsigned int vr_grp_busy : 1; + unsigned int dma_request_busy : 1; + unsigned int out_busy : 1; + unsigned int grp_backend_busy : 1; + unsigned int grp_busy : 1; + unsigned int dma_busy : 1; + unsigned int rbiu_dma_request_busy : 1; + unsigned int rbiu_busy : 1; + unsigned int vgt_no_dma_busy_extended : 1; + unsigned int vgt_no_dma_busy : 1; + unsigned int vgt_busy_extended : 1; + unsigned int vgt_busy : 1; + unsigned int rbbm_skid_fifo_busy_out : 1; + unsigned int VGT_RBBM_no_dma_busy : 1; + unsigned int VGT_RBBM_busy : 1; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int VGT_RBBM_busy : 1; + unsigned int VGT_RBBM_no_dma_busy : 1; + unsigned int rbbm_skid_fifo_busy_out : 1; + unsigned int vgt_busy : 1; + unsigned int vgt_busy_extended : 1; + unsigned int vgt_no_dma_busy : 1; + unsigned int vgt_no_dma_busy_extended : 1; + unsigned int rbiu_busy : 1; + unsigned int rbiu_dma_request_busy : 1; + unsigned int dma_busy : 1; + unsigned int grp_busy : 1; + unsigned int grp_backend_busy : 1; + unsigned int out_busy : 1; + unsigned int dma_request_busy : 1; + unsigned int vr_grp_busy : 1; + unsigned int pt_grp_busy : 1; + unsigned int te_grp_busy : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG1 { + struct { +#if defined(qLittleEndian) + unsigned int out_te_data_read : 1; + unsigned int te_out_data_valid : 1; + unsigned int out_pt_prim_read : 1; + unsigned int pt_out_prim_valid : 1; + unsigned int out_pt_data_read : 1; + unsigned int pt_out_indx_valid : 1; + unsigned int out_vr_prim_read : 1; + unsigned int vr_out_prim_valid : 1; + unsigned int out_vr_indx_read : 1; + unsigned int vr_out_indx_valid : 1; + unsigned int te_grp_read : 1; + unsigned int grp_te_valid : 1; + unsigned int pt_grp_read : 1; + unsigned int grp_pt_valid : 1; + unsigned int vr_grp_read : 1; + unsigned int grp_vr_valid : 1; + unsigned int grp_dma_read : 1; + unsigned int dma_grp_valid : 1; + unsigned int grp_rbiu_di_read : 1; + unsigned int rbiu_grp_di_valid : 1; + unsigned int MH_VGT_rtr : 1; + unsigned int VGT_MH_send : 1; + unsigned int PA_VGT_clip_s_rtr : 1; + unsigned int VGT_PA_clip_s_send : 1; + unsigned int PA_VGT_clip_p_rtr : 1; + unsigned int VGT_PA_clip_p_send : 1; + unsigned int PA_VGT_clip_v_rtr : 1; + unsigned int VGT_PA_clip_v_send : 1; + unsigned int SQ_VGT_rtr : 1; + unsigned int VGT_SQ_send : 1; + unsigned int mh_vgt_tag_7_q : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int mh_vgt_tag_7_q : 1; + unsigned int VGT_SQ_send : 1; + unsigned int SQ_VGT_rtr : 1; + unsigned int VGT_PA_clip_v_send : 1; + unsigned int PA_VGT_clip_v_rtr : 1; + unsigned int VGT_PA_clip_p_send : 1; + unsigned int PA_VGT_clip_p_rtr : 1; + unsigned int VGT_PA_clip_s_send : 1; + unsigned int PA_VGT_clip_s_rtr : 1; + unsigned int VGT_MH_send : 1; + unsigned int MH_VGT_rtr : 1; + unsigned int rbiu_grp_di_valid : 1; + unsigned int grp_rbiu_di_read : 1; + unsigned int dma_grp_valid : 1; + unsigned int grp_dma_read : 1; + unsigned int grp_vr_valid : 1; + unsigned int vr_grp_read : 1; + unsigned int grp_pt_valid : 1; + unsigned int pt_grp_read : 1; + unsigned int grp_te_valid : 1; + unsigned int te_grp_read : 1; + unsigned int vr_out_indx_valid : 1; + unsigned int out_vr_indx_read : 1; + unsigned int vr_out_prim_valid : 1; + unsigned int out_vr_prim_read : 1; + unsigned int pt_out_indx_valid : 1; + unsigned int out_pt_data_read : 1; + unsigned int pt_out_prim_valid : 1; + unsigned int out_pt_prim_read : 1; + unsigned int te_out_data_valid : 1; + unsigned int out_te_data_read : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG3 { + struct { +#if defined(qLittleEndian) + unsigned int vgt_clk_en : 1; + unsigned int reg_fifos_clk_en : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int reg_fifos_clk_en : 1; + unsigned int vgt_clk_en : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG6 { + struct { +#if defined(qLittleEndian) + unsigned int shifter_byte_count_q : 5; + unsigned int right_word_indx_q : 5; + unsigned int input_data_valid : 1; + unsigned int input_data_xfer : 1; + unsigned int next_shift_is_vect_1_q : 1; + unsigned int next_shift_is_vect_1_d : 1; + unsigned int next_shift_is_vect_1_pre_d : 1; + unsigned int space_avail_from_shift : 1; + unsigned int shifter_first_load : 1; + unsigned int di_state_sel_q : 1; + unsigned int shifter_waiting_for_first_load_q : 1; + unsigned int di_first_group_flag_q : 1; + unsigned int di_event_flag_q : 1; + unsigned int read_draw_initiator : 1; + unsigned int loading_di_requires_shifter : 1; + unsigned int last_shift_of_packet : 1; + unsigned int last_decr_of_packet : 1; + unsigned int extract_vector : 1; + unsigned int shift_vect_rtr : 1; + unsigned int destination_rtr : 1; + unsigned int grp_trigger : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int grp_trigger : 1; + unsigned int destination_rtr : 1; + unsigned int shift_vect_rtr : 1; + unsigned int extract_vector : 1; + unsigned int last_decr_of_packet : 1; + unsigned int last_shift_of_packet : 1; + unsigned int loading_di_requires_shifter : 1; + unsigned int read_draw_initiator : 1; + unsigned int di_event_flag_q : 1; + unsigned int di_first_group_flag_q : 1; + unsigned int shifter_waiting_for_first_load_q : 1; + unsigned int di_state_sel_q : 1; + unsigned int shifter_first_load : 1; + unsigned int space_avail_from_shift : 1; + unsigned int next_shift_is_vect_1_pre_d : 1; + unsigned int next_shift_is_vect_1_d : 1; + unsigned int next_shift_is_vect_1_q : 1; + unsigned int input_data_xfer : 1; + unsigned int input_data_valid : 1; + unsigned int right_word_indx_q : 5; + unsigned int shifter_byte_count_q : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG7 { + struct { +#if defined(qLittleEndian) + unsigned int di_index_counter_q : 16; + unsigned int shift_amount_no_extract : 4; + unsigned int shift_amount_extract : 4; + unsigned int di_prim_type_q : 6; + unsigned int current_source_sel : 2; +#else /* !defined(qLittleEndian) */ + unsigned int current_source_sel : 2; + unsigned int di_prim_type_q : 6; + unsigned int shift_amount_extract : 4; + unsigned int shift_amount_no_extract : 4; + unsigned int di_index_counter_q : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG8 { + struct { +#if defined(qLittleEndian) + unsigned int current_source_sel : 2; + unsigned int left_word_indx_q : 5; + unsigned int input_data_cnt : 5; + unsigned int input_data_lsw : 5; + unsigned int input_data_msw : 5; + unsigned int next_small_stride_shift_limit_q : 5; + unsigned int current_small_stride_shift_limit_q : 5; +#else /* !defined(qLittleEndian) */ + unsigned int current_small_stride_shift_limit_q : 5; + unsigned int next_small_stride_shift_limit_q : 5; + unsigned int input_data_msw : 5; + unsigned int input_data_lsw : 5; + unsigned int input_data_cnt : 5; + unsigned int left_word_indx_q : 5; + unsigned int current_source_sel : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG9 { + struct { +#if defined(qLittleEndian) + unsigned int next_stride_q : 5; + unsigned int next_stride_d : 5; + unsigned int current_shift_q : 5; + unsigned int current_shift_d : 5; + unsigned int current_stride_q : 5; + unsigned int current_stride_d : 5; + unsigned int grp_trigger : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int grp_trigger : 1; + unsigned int current_stride_d : 5; + unsigned int current_stride_q : 5; + unsigned int current_shift_d : 5; + unsigned int current_shift_q : 5; + unsigned int next_stride_d : 5; + unsigned int next_stride_q : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG10 { + struct { +#if defined(qLittleEndian) + unsigned int temp_derived_di_prim_type_t0 : 1; + unsigned int temp_derived_di_small_index_t0 : 1; + unsigned int temp_derived_di_cull_enable_t0 : 1; + unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : 1; + unsigned int di_state_sel_q : 1; + unsigned int last_decr_of_packet : 1; + unsigned int bin_valid : 1; + unsigned int read_block : 1; + unsigned int grp_bgrp_last_bit_read : 1; + unsigned int last_bit_enable_q : 1; + unsigned int last_bit_end_di_q : 1; + unsigned int selected_data : 8; + unsigned int mask_input_data : 8; + unsigned int gap_q : 1; + unsigned int temp_mini_reset_z : 1; + unsigned int temp_mini_reset_y : 1; + unsigned int temp_mini_reset_x : 1; + unsigned int grp_trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int grp_trigger : 1; + unsigned int temp_mini_reset_x : 1; + unsigned int temp_mini_reset_y : 1; + unsigned int temp_mini_reset_z : 1; + unsigned int gap_q : 1; + unsigned int mask_input_data : 8; + unsigned int selected_data : 8; + unsigned int last_bit_end_di_q : 1; + unsigned int last_bit_enable_q : 1; + unsigned int grp_bgrp_last_bit_read : 1; + unsigned int read_block : 1; + unsigned int bin_valid : 1; + unsigned int last_decr_of_packet : 1; + unsigned int di_state_sel_q : 1; + unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : 1; + unsigned int temp_derived_di_cull_enable_t0 : 1; + unsigned int temp_derived_di_small_index_t0 : 1; + unsigned int temp_derived_di_prim_type_t0 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG12 { + struct { +#if defined(qLittleEndian) + unsigned int shifter_byte_count_q : 5; + unsigned int right_word_indx_q : 5; + unsigned int input_data_valid : 1; + unsigned int input_data_xfer : 1; + unsigned int next_shift_is_vect_1_q : 1; + unsigned int next_shift_is_vect_1_d : 1; + unsigned int next_shift_is_vect_1_pre_d : 1; + unsigned int space_avail_from_shift : 1; + unsigned int shifter_first_load : 1; + unsigned int di_state_sel_q : 1; + unsigned int shifter_waiting_for_first_load_q : 1; + unsigned int di_first_group_flag_q : 1; + unsigned int di_event_flag_q : 1; + unsigned int read_draw_initiator : 1; + unsigned int loading_di_requires_shifter : 1; + unsigned int last_shift_of_packet : 1; + unsigned int last_decr_of_packet : 1; + unsigned int extract_vector : 1; + unsigned int shift_vect_rtr : 1; + unsigned int destination_rtr : 1; + unsigned int bgrp_trigger : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int bgrp_trigger : 1; + unsigned int destination_rtr : 1; + unsigned int shift_vect_rtr : 1; + unsigned int extract_vector : 1; + unsigned int last_decr_of_packet : 1; + unsigned int last_shift_of_packet : 1; + unsigned int loading_di_requires_shifter : 1; + unsigned int read_draw_initiator : 1; + unsigned int di_event_flag_q : 1; + unsigned int di_first_group_flag_q : 1; + unsigned int shifter_waiting_for_first_load_q : 1; + unsigned int di_state_sel_q : 1; + unsigned int shifter_first_load : 1; + unsigned int space_avail_from_shift : 1; + unsigned int next_shift_is_vect_1_pre_d : 1; + unsigned int next_shift_is_vect_1_d : 1; + unsigned int next_shift_is_vect_1_q : 1; + unsigned int input_data_xfer : 1; + unsigned int input_data_valid : 1; + unsigned int right_word_indx_q : 5; + unsigned int shifter_byte_count_q : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG13 { + struct { +#if defined(qLittleEndian) + unsigned int di_index_counter_q : 16; + unsigned int shift_amount_no_extract : 4; + unsigned int shift_amount_extract : 4; + unsigned int di_prim_type_q : 6; + unsigned int current_source_sel : 2; +#else /* !defined(qLittleEndian) */ + unsigned int current_source_sel : 2; + unsigned int di_prim_type_q : 6; + unsigned int shift_amount_extract : 4; + unsigned int shift_amount_no_extract : 4; + unsigned int di_index_counter_q : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG14 { + struct { +#if defined(qLittleEndian) + unsigned int current_source_sel : 2; + unsigned int left_word_indx_q : 5; + unsigned int input_data_cnt : 5; + unsigned int input_data_lsw : 5; + unsigned int input_data_msw : 5; + unsigned int next_small_stride_shift_limit_q : 5; + unsigned int current_small_stride_shift_limit_q : 5; +#else /* !defined(qLittleEndian) */ + unsigned int current_small_stride_shift_limit_q : 5; + unsigned int next_small_stride_shift_limit_q : 5; + unsigned int input_data_msw : 5; + unsigned int input_data_lsw : 5; + unsigned int input_data_cnt : 5; + unsigned int left_word_indx_q : 5; + unsigned int current_source_sel : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG15 { + struct { +#if defined(qLittleEndian) + unsigned int next_stride_q : 5; + unsigned int next_stride_d : 5; + unsigned int current_shift_q : 5; + unsigned int current_shift_d : 5; + unsigned int current_stride_q : 5; + unsigned int current_stride_d : 5; + unsigned int bgrp_trigger : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int bgrp_trigger : 1; + unsigned int current_stride_d : 5; + unsigned int current_stride_q : 5; + unsigned int current_shift_d : 5; + unsigned int current_shift_q : 5; + unsigned int next_stride_d : 5; + unsigned int next_stride_q : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG16 { + struct { +#if defined(qLittleEndian) + unsigned int bgrp_cull_fetch_fifo_full : 1; + unsigned int bgrp_cull_fetch_fifo_empty : 1; + unsigned int dma_bgrp_cull_fetch_read : 1; + unsigned int bgrp_cull_fetch_fifo_we : 1; + unsigned int bgrp_byte_mask_fifo_full : 1; + unsigned int bgrp_byte_mask_fifo_empty : 1; + unsigned int bgrp_byte_mask_fifo_re_q : 1; + unsigned int bgrp_byte_mask_fifo_we : 1; + unsigned int bgrp_dma_mask_kill : 1; + unsigned int bgrp_grp_bin_valid : 1; + unsigned int rst_last_bit : 1; + unsigned int current_state_q : 1; + unsigned int old_state_q : 1; + unsigned int old_state_en : 1; + unsigned int prev_last_bit_q : 1; + unsigned int dbl_last_bit_q : 1; + unsigned int last_bit_block_q : 1; + unsigned int ast_bit_block2_q : 1; + unsigned int load_empty_reg : 1; + unsigned int bgrp_grp_byte_mask_rdata : 8; + unsigned int dma_bgrp_dma_data_fifo_rptr : 2; + unsigned int top_di_pre_fetch_cull_enable : 1; + unsigned int top_di_grp_cull_enable_q : 1; + unsigned int bgrp_trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int bgrp_trigger : 1; + unsigned int top_di_grp_cull_enable_q : 1; + unsigned int top_di_pre_fetch_cull_enable : 1; + unsigned int dma_bgrp_dma_data_fifo_rptr : 2; + unsigned int bgrp_grp_byte_mask_rdata : 8; + unsigned int load_empty_reg : 1; + unsigned int ast_bit_block2_q : 1; + unsigned int last_bit_block_q : 1; + unsigned int dbl_last_bit_q : 1; + unsigned int prev_last_bit_q : 1; + unsigned int old_state_en : 1; + unsigned int old_state_q : 1; + unsigned int current_state_q : 1; + unsigned int rst_last_bit : 1; + unsigned int bgrp_grp_bin_valid : 1; + unsigned int bgrp_dma_mask_kill : 1; + unsigned int bgrp_byte_mask_fifo_we : 1; + unsigned int bgrp_byte_mask_fifo_re_q : 1; + unsigned int bgrp_byte_mask_fifo_empty : 1; + unsigned int bgrp_byte_mask_fifo_full : 1; + unsigned int bgrp_cull_fetch_fifo_we : 1; + unsigned int dma_bgrp_cull_fetch_read : 1; + unsigned int bgrp_cull_fetch_fifo_empty : 1; + unsigned int bgrp_cull_fetch_fifo_full : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG17 { + struct { +#if defined(qLittleEndian) + unsigned int save_read_q : 1; + unsigned int extend_read_q : 1; + unsigned int grp_indx_size : 2; + unsigned int cull_prim_true : 1; + unsigned int reset_bit2_q : 1; + unsigned int reset_bit1_q : 1; + unsigned int first_reg_first_q : 1; + unsigned int check_second_reg : 1; + unsigned int check_first_reg : 1; + unsigned int bgrp_cull_fetch_fifo_wdata : 1; + unsigned int save_cull_fetch_data2_q : 1; + unsigned int save_cull_fetch_data1_q : 1; + unsigned int save_byte_mask_data2_q : 1; + unsigned int save_byte_mask_data1_q : 1; + unsigned int to_second_reg_q : 1; + unsigned int roll_over_msk_q : 1; + unsigned int max_msk_ptr_q : 7; + unsigned int min_msk_ptr_q : 7; + unsigned int bgrp_trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int bgrp_trigger : 1; + unsigned int min_msk_ptr_q : 7; + unsigned int max_msk_ptr_q : 7; + unsigned int roll_over_msk_q : 1; + unsigned int to_second_reg_q : 1; + unsigned int save_byte_mask_data1_q : 1; + unsigned int save_byte_mask_data2_q : 1; + unsigned int save_cull_fetch_data1_q : 1; + unsigned int save_cull_fetch_data2_q : 1; + unsigned int bgrp_cull_fetch_fifo_wdata : 1; + unsigned int check_first_reg : 1; + unsigned int check_second_reg : 1; + unsigned int first_reg_first_q : 1; + unsigned int reset_bit1_q : 1; + unsigned int reset_bit2_q : 1; + unsigned int cull_prim_true : 1; + unsigned int grp_indx_size : 2; + unsigned int extend_read_q : 1; + unsigned int save_read_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG18 { + struct { +#if defined(qLittleEndian) + unsigned int dma_data_fifo_mem_raddr : 6; + unsigned int dma_data_fifo_mem_waddr : 6; + unsigned int dma_bgrp_byte_mask_fifo_re : 1; + unsigned int dma_bgrp_dma_data_fifo_rptr : 2; + unsigned int dma_mem_full : 1; + unsigned int dma_ram_re : 1; + unsigned int dma_ram_we : 1; + unsigned int dma_mem_empty : 1; + unsigned int dma_data_fifo_mem_re : 1; + unsigned int dma_data_fifo_mem_we : 1; + unsigned int bin_mem_full : 1; + unsigned int bin_ram_we : 1; + unsigned int bin_ram_re : 1; + unsigned int bin_mem_empty : 1; + unsigned int start_bin_req : 1; + unsigned int fetch_cull_not_used : 1; + unsigned int dma_req_xfer : 1; + unsigned int have_valid_bin_req : 1; + unsigned int have_valid_dma_req : 1; + unsigned int bgrp_dma_di_grp_cull_enable : 1; + unsigned int bgrp_dma_di_pre_fetch_cull_enable : 1; +#else /* !defined(qLittleEndian) */ + unsigned int bgrp_dma_di_pre_fetch_cull_enable : 1; + unsigned int bgrp_dma_di_grp_cull_enable : 1; + unsigned int have_valid_dma_req : 1; + unsigned int have_valid_bin_req : 1; + unsigned int dma_req_xfer : 1; + unsigned int fetch_cull_not_used : 1; + unsigned int start_bin_req : 1; + unsigned int bin_mem_empty : 1; + unsigned int bin_ram_re : 1; + unsigned int bin_ram_we : 1; + unsigned int bin_mem_full : 1; + unsigned int dma_data_fifo_mem_we : 1; + unsigned int dma_data_fifo_mem_re : 1; + unsigned int dma_mem_empty : 1; + unsigned int dma_ram_we : 1; + unsigned int dma_ram_re : 1; + unsigned int dma_mem_full : 1; + unsigned int dma_bgrp_dma_data_fifo_rptr : 2; + unsigned int dma_bgrp_byte_mask_fifo_re : 1; + unsigned int dma_data_fifo_mem_waddr : 6; + unsigned int dma_data_fifo_mem_raddr : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG20 { + struct { +#if defined(qLittleEndian) + unsigned int prim_side_indx_valid : 1; + unsigned int indx_side_fifo_empty : 1; + unsigned int indx_side_fifo_re : 1; + unsigned int indx_side_fifo_we : 1; + unsigned int indx_side_fifo_full : 1; + unsigned int prim_buffer_empty : 1; + unsigned int prim_buffer_re : 1; + unsigned int prim_buffer_we : 1; + unsigned int prim_buffer_full : 1; + unsigned int indx_buffer_empty : 1; + unsigned int indx_buffer_re : 1; + unsigned int indx_buffer_we : 1; + unsigned int indx_buffer_full : 1; + unsigned int hold_prim : 1; + unsigned int sent_cnt : 4; + unsigned int start_of_vtx_vector : 1; + unsigned int clip_s_pre_hold_prim : 1; + unsigned int clip_p_pre_hold_prim : 1; + unsigned int buffered_prim_type_event : 5; + unsigned int out_trigger : 1; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int out_trigger : 1; + unsigned int buffered_prim_type_event : 5; + unsigned int clip_p_pre_hold_prim : 1; + unsigned int clip_s_pre_hold_prim : 1; + unsigned int start_of_vtx_vector : 1; + unsigned int sent_cnt : 4; + unsigned int hold_prim : 1; + unsigned int indx_buffer_full : 1; + unsigned int indx_buffer_we : 1; + unsigned int indx_buffer_re : 1; + unsigned int indx_buffer_empty : 1; + unsigned int prim_buffer_full : 1; + unsigned int prim_buffer_we : 1; + unsigned int prim_buffer_re : 1; + unsigned int prim_buffer_empty : 1; + unsigned int indx_side_fifo_full : 1; + unsigned int indx_side_fifo_we : 1; + unsigned int indx_side_fifo_re : 1; + unsigned int indx_side_fifo_empty : 1; + unsigned int prim_side_indx_valid : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_DEBUG_REG21 { + struct { +#if defined(qLittleEndian) + unsigned int null_terminate_vtx_vector : 1; + unsigned int prim_end_of_vtx_vect_flags : 3; + unsigned int alloc_counter_q : 3; + unsigned int curr_slot_in_vtx_vect_q : 3; + unsigned int int_vtx_counter_q : 4; + unsigned int curr_dealloc_distance_q : 4; + unsigned int new_packet_q : 1; + unsigned int new_allocate_q : 1; + unsigned int num_new_unique_rel_indx : 2; + unsigned int inserted_null_prim_q : 1; + unsigned int insert_null_prim : 1; + unsigned int buffered_prim_eop_mux : 1; + unsigned int prim_buffer_empty_mux : 1; + unsigned int buffered_thread_size : 1; + unsigned int : 4; + unsigned int out_trigger : 1; +#else /* !defined(qLittleEndian) */ + unsigned int out_trigger : 1; + unsigned int : 4; + unsigned int buffered_thread_size : 1; + unsigned int prim_buffer_empty_mux : 1; + unsigned int buffered_prim_eop_mux : 1; + unsigned int insert_null_prim : 1; + unsigned int inserted_null_prim_q : 1; + unsigned int num_new_unique_rel_indx : 2; + unsigned int new_allocate_q : 1; + unsigned int new_packet_q : 1; + unsigned int curr_dealloc_distance_q : 4; + unsigned int int_vtx_counter_q : 4; + unsigned int curr_slot_in_vtx_vect_q : 3; + unsigned int alloc_counter_q : 3; + unsigned int prim_end_of_vtx_vect_flags : 3; + unsigned int null_terminate_vtx_vector : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CRC_SQ_DATA { + struct { +#if defined(qLittleEndian) + unsigned int CRC : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CRC : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_CRC_SQ_CTRL { + struct { +#if defined(qLittleEndian) + unsigned int CRC : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CRC : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER2_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER3_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER2_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER3_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER2_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union VGT_PERFCOUNTER3_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TC_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int L2_INVALIDATE : 1; + unsigned int : 17; + unsigned int TC_L2_HIT_MISS : 2; + unsigned int : 11; + unsigned int TC_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TC_BUSY : 1; + unsigned int : 11; + unsigned int TC_L2_HIT_MISS : 2; + unsigned int : 17; + unsigned int L2_INVALIDATE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int SPARE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int SPARE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int TCO_READ_LATENCY_FIFO_PROG_DEPTH : 8; + unsigned int ETC_COLOR_ENDIAN : 1; + unsigned int SPARE : 23; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 23; + unsigned int ETC_COLOR_ENDIAN : 1; + unsigned int TCO_READ_LATENCY_FIFO_PROG_DEPTH : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCR_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP_TC_CLKGATE_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int TP_BUSY_EXTEND : 3; + unsigned int TC_BUSY_EXTEND : 3; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int TC_BUSY_EXTEND : 3; + unsigned int TP_BUSY_EXTEND : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TPC_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int TPC_INPUT_BUSY : 1; + unsigned int TPC_TC_FIFO_BUSY : 1; + unsigned int TPC_STATE_FIFO_BUSY : 1; + unsigned int TPC_FETCH_FIFO_BUSY : 1; + unsigned int TPC_WALKER_PIPE_BUSY : 1; + unsigned int TPC_WALK_FIFO_BUSY : 1; + unsigned int TPC_WALKER_BUSY : 1; + unsigned int : 1; + unsigned int TPC_ALIGNER_PIPE_BUSY : 1; + unsigned int TPC_ALIGN_FIFO_BUSY : 1; + unsigned int TPC_ALIGNER_BUSY : 1; + unsigned int : 1; + unsigned int TPC_RR_FIFO_BUSY : 1; + unsigned int TPC_BLEND_PIPE_BUSY : 1; + unsigned int TPC_OUT_FIFO_BUSY : 1; + unsigned int TPC_BLEND_BUSY : 1; + unsigned int TF_TW_RTS : 1; + unsigned int TF_TW_STATE_RTS : 1; + unsigned int : 1; + unsigned int TF_TW_RTR : 1; + unsigned int TW_TA_RTS : 1; + unsigned int TW_TA_TT_RTS : 1; + unsigned int TW_TA_LAST_RTS : 1; + unsigned int TW_TA_RTR : 1; + unsigned int TA_TB_RTS : 1; + unsigned int TA_TB_TT_RTS : 1; + unsigned int : 1; + unsigned int TA_TB_RTR : 1; + unsigned int TA_TF_RTS : 1; + unsigned int TA_TF_TC_FIFO_REN : 1; + unsigned int TP_SQ_DEC : 1; + unsigned int TPC_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TPC_BUSY : 1; + unsigned int TP_SQ_DEC : 1; + unsigned int TA_TF_TC_FIFO_REN : 1; + unsigned int TA_TF_RTS : 1; + unsigned int TA_TB_RTR : 1; + unsigned int : 1; + unsigned int TA_TB_TT_RTS : 1; + unsigned int TA_TB_RTS : 1; + unsigned int TW_TA_RTR : 1; + unsigned int TW_TA_LAST_RTS : 1; + unsigned int TW_TA_TT_RTS : 1; + unsigned int TW_TA_RTS : 1; + unsigned int TF_TW_RTR : 1; + unsigned int : 1; + unsigned int TF_TW_STATE_RTS : 1; + unsigned int TF_TW_RTS : 1; + unsigned int TPC_BLEND_BUSY : 1; + unsigned int TPC_OUT_FIFO_BUSY : 1; + unsigned int TPC_BLEND_PIPE_BUSY : 1; + unsigned int TPC_RR_FIFO_BUSY : 1; + unsigned int : 1; + unsigned int TPC_ALIGNER_BUSY : 1; + unsigned int TPC_ALIGN_FIFO_BUSY : 1; + unsigned int TPC_ALIGNER_PIPE_BUSY : 1; + unsigned int : 1; + unsigned int TPC_WALKER_BUSY : 1; + unsigned int TPC_WALK_FIFO_BUSY : 1; + unsigned int TPC_WALKER_PIPE_BUSY : 1; + unsigned int TPC_FETCH_FIFO_BUSY : 1; + unsigned int TPC_STATE_FIFO_BUSY : 1; + unsigned int TPC_TC_FIFO_BUSY : 1; + unsigned int TPC_INPUT_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TPC_DEBUG0 { + struct { +#if defined(qLittleEndian) + unsigned int LOD_CNTL : 2; + unsigned int IC_CTR : 2; + unsigned int WALKER_CNTL : 4; + unsigned int ALIGNER_CNTL : 3; + unsigned int : 1; + unsigned int PREV_TC_STATE_VALID : 1; + unsigned int : 3; + unsigned int WALKER_STATE : 10; + unsigned int ALIGNER_STATE : 2; + unsigned int : 1; + unsigned int REG_CLK_EN : 1; + unsigned int TPC_CLK_EN : 1; + unsigned int SQ_TP_WAKEUP : 1; +#else /* !defined(qLittleEndian) */ + unsigned int SQ_TP_WAKEUP : 1; + unsigned int TPC_CLK_EN : 1; + unsigned int REG_CLK_EN : 1; + unsigned int : 1; + unsigned int ALIGNER_STATE : 2; + unsigned int WALKER_STATE : 10; + unsigned int : 3; + unsigned int PREV_TC_STATE_VALID : 1; + unsigned int : 1; + unsigned int ALIGNER_CNTL : 3; + unsigned int WALKER_CNTL : 4; + unsigned int IC_CTR : 2; + unsigned int LOD_CNTL : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TPC_DEBUG1 { + struct { +#if defined(qLittleEndian) + unsigned int UNUSED : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int UNUSED : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TPC_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_PRECISION : 1; + unsigned int SPARE : 31; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 31; + unsigned int BLEND_PRECISION : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_CNTL_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int TP_INPUT_BUSY : 1; + unsigned int TP_LOD_BUSY : 1; + unsigned int TP_LOD_FIFO_BUSY : 1; + unsigned int TP_ADDR_BUSY : 1; + unsigned int TP_ALIGN_FIFO_BUSY : 1; + unsigned int TP_ALIGNER_BUSY : 1; + unsigned int TP_TC_FIFO_BUSY : 1; + unsigned int TP_RR_FIFO_BUSY : 1; + unsigned int TP_FETCH_BUSY : 1; + unsigned int TP_CH_BLEND_BUSY : 1; + unsigned int TP_TT_BUSY : 1; + unsigned int TP_HICOLOR_BUSY : 1; + unsigned int TP_BLEND_BUSY : 1; + unsigned int TP_OUT_FIFO_BUSY : 1; + unsigned int TP_OUTPUT_BUSY : 1; + unsigned int : 1; + unsigned int IN_LC_RTS : 1; + unsigned int LC_LA_RTS : 1; + unsigned int LA_FL_RTS : 1; + unsigned int FL_TA_RTS : 1; + unsigned int TA_FA_RTS : 1; + unsigned int TA_FA_TT_RTS : 1; + unsigned int FA_AL_RTS : 1; + unsigned int FA_AL_TT_RTS : 1; + unsigned int AL_TF_RTS : 1; + unsigned int AL_TF_TT_RTS : 1; + unsigned int TF_TB_RTS : 1; + unsigned int TF_TB_TT_RTS : 1; + unsigned int TB_TT_RTS : 1; + unsigned int TB_TT_TT_RESET : 1; + unsigned int TB_TO_RTS : 1; + unsigned int TP_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TP_BUSY : 1; + unsigned int TB_TO_RTS : 1; + unsigned int TB_TT_TT_RESET : 1; + unsigned int TB_TT_RTS : 1; + unsigned int TF_TB_TT_RTS : 1; + unsigned int TF_TB_RTS : 1; + unsigned int AL_TF_TT_RTS : 1; + unsigned int AL_TF_RTS : 1; + unsigned int FA_AL_TT_RTS : 1; + unsigned int FA_AL_RTS : 1; + unsigned int TA_FA_TT_RTS : 1; + unsigned int TA_FA_RTS : 1; + unsigned int FL_TA_RTS : 1; + unsigned int LA_FL_RTS : 1; + unsigned int LC_LA_RTS : 1; + unsigned int IN_LC_RTS : 1; + unsigned int : 1; + unsigned int TP_OUTPUT_BUSY : 1; + unsigned int TP_OUT_FIFO_BUSY : 1; + unsigned int TP_BLEND_BUSY : 1; + unsigned int TP_HICOLOR_BUSY : 1; + unsigned int TP_TT_BUSY : 1; + unsigned int TP_CH_BLEND_BUSY : 1; + unsigned int TP_FETCH_BUSY : 1; + unsigned int TP_RR_FIFO_BUSY : 1; + unsigned int TP_TC_FIFO_BUSY : 1; + unsigned int TP_ALIGNER_BUSY : 1; + unsigned int TP_ALIGN_FIFO_BUSY : 1; + unsigned int TP_ADDR_BUSY : 1; + unsigned int TP_LOD_FIFO_BUSY : 1; + unsigned int TP_LOD_BUSY : 1; + unsigned int TP_INPUT_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int Q_LOD_CNTL : 2; + unsigned int : 1; + unsigned int Q_SQ_TP_WAKEUP : 1; + unsigned int FL_TA_ADDRESSER_CNTL : 17; + unsigned int REG_CLK_EN : 1; + unsigned int PERF_CLK_EN : 1; + unsigned int TP_CLK_EN : 1; + unsigned int Q_WALKER_CNTL : 4; + unsigned int Q_ALIGNER_CNTL : 3; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int Q_ALIGNER_CNTL : 3; + unsigned int Q_WALKER_CNTL : 4; + unsigned int TP_CLK_EN : 1; + unsigned int PERF_CLK_EN : 1; + unsigned int REG_CLK_EN : 1; + unsigned int FL_TA_ADDRESSER_CNTL : 17; + unsigned int Q_SQ_TP_WAKEUP : 1; + unsigned int : 1; + unsigned int Q_LOD_CNTL : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_CHICKEN { + struct { +#if defined(qLittleEndian) + unsigned int TT_MODE : 1; + unsigned int VFETCH_ADDRESS_MODE : 1; + unsigned int SPARE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 30; + unsigned int VFETCH_ADDRESS_MODE : 1; + unsigned int TT_MODE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TP0_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCM_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER2_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER3_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER4_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER5_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER6_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER7_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER8_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER9_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER10_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER11_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_SELECT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERFCOUNTER_SELECT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER2_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER3_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER4_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER5_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER6_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER7_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER8_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER9_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER10_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER11_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER2_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER3_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER4_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER5_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER6_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER7_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER8_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER9_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER10_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_PERFCOUNTER11_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCF_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 6; + unsigned int not_MH_TC_rtr : 1; + unsigned int TC_MH_send : 1; + unsigned int not_FG0_rtr : 1; + unsigned int : 3; + unsigned int not_TCB_TCO_rtr : 1; + unsigned int TCB_ff_stall : 1; + unsigned int TCB_miss_stall : 1; + unsigned int TCA_TCB_stall : 1; + unsigned int PF0_stall : 1; + unsigned int : 3; + unsigned int TP0_full : 1; + unsigned int : 3; + unsigned int TPC_full : 1; + unsigned int not_TPC_rtr : 1; + unsigned int tca_state_rts : 1; + unsigned int tca_rts : 1; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int tca_rts : 1; + unsigned int tca_state_rts : 1; + unsigned int not_TPC_rtr : 1; + unsigned int TPC_full : 1; + unsigned int : 3; + unsigned int TP0_full : 1; + unsigned int : 3; + unsigned int PF0_stall : 1; + unsigned int TCA_TCB_stall : 1; + unsigned int TCB_miss_stall : 1; + unsigned int TCB_ff_stall : 1; + unsigned int not_TCB_TCO_rtr : 1; + unsigned int : 3; + unsigned int not_FG0_rtr : 1; + unsigned int TC_MH_send : 1; + unsigned int not_MH_TC_rtr : 1; + unsigned int : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCA_FIFO_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int tp0_full : 1; + unsigned int : 3; + unsigned int tpc_full : 1; + unsigned int load_tpc_fifo : 1; + unsigned int load_tp_fifos : 1; + unsigned int FW_full : 1; + unsigned int not_FW_rtr0 : 1; + unsigned int : 3; + unsigned int FW_rts0 : 1; + unsigned int : 3; + unsigned int not_FW_tpc_rtr : 1; + unsigned int FW_tpc_rts : 1; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int FW_tpc_rts : 1; + unsigned int not_FW_tpc_rtr : 1; + unsigned int : 3; + unsigned int FW_rts0 : 1; + unsigned int : 3; + unsigned int not_FW_rtr0 : 1; + unsigned int FW_full : 1; + unsigned int load_tp_fifos : 1; + unsigned int load_tpc_fifo : 1; + unsigned int tpc_full : 1; + unsigned int : 3; + unsigned int tp0_full : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCA_PROBE_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int ProbeFilter_stall : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int ProbeFilter_stall : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCA_TPC_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int captue_state_rts : 1; + unsigned int capture_tca_rts : 1; + unsigned int : 18; +#else /* !defined(qLittleEndian) */ + unsigned int : 18; + unsigned int capture_tca_rts : 1; + unsigned int captue_state_rts : 1; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_CORE_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int access512 : 1; + unsigned int tiled : 1; + unsigned int : 2; + unsigned int opcode : 3; + unsigned int : 1; + unsigned int format : 6; + unsigned int : 2; + unsigned int sector_format : 5; + unsigned int : 3; + unsigned int sector_format512 : 3; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int sector_format512 : 3; + unsigned int : 3; + unsigned int sector_format : 5; + unsigned int : 2; + unsigned int format : 6; + unsigned int : 1; + unsigned int opcode : 3; + unsigned int : 2; + unsigned int tiled : 1; + unsigned int access512 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_TAG0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int mem_read_cycle : 10; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int miss_stall : 1; + unsigned int num_feee_lines : 5; + unsigned int max_misses : 3; +#else /* !defined(qLittleEndian) */ + unsigned int max_misses : 3; + unsigned int num_feee_lines : 5; + unsigned int miss_stall : 1; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int mem_read_cycle : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_TAG1_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int mem_read_cycle : 10; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int miss_stall : 1; + unsigned int num_feee_lines : 5; + unsigned int max_misses : 3; +#else /* !defined(qLittleEndian) */ + unsigned int max_misses : 3; + unsigned int num_feee_lines : 5; + unsigned int miss_stall : 1; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int mem_read_cycle : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_TAG2_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int mem_read_cycle : 10; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int miss_stall : 1; + unsigned int num_feee_lines : 5; + unsigned int max_misses : 3; +#else /* !defined(qLittleEndian) */ + unsigned int max_misses : 3; + unsigned int num_feee_lines : 5; + unsigned int miss_stall : 1; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int mem_read_cycle : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_TAG3_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int mem_read_cycle : 10; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int miss_stall : 1; + unsigned int num_feee_lines : 5; + unsigned int max_misses : 3; +#else /* !defined(qLittleEndian) */ + unsigned int max_misses : 3; + unsigned int num_feee_lines : 5; + unsigned int miss_stall : 1; + unsigned int : 2; + unsigned int tag_access_cycle : 9; + unsigned int : 2; + unsigned int mem_read_cycle : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int left_done : 1; + unsigned int : 1; + unsigned int fg0_sends_left : 1; + unsigned int : 1; + unsigned int one_sector_to_go_left_q : 1; + unsigned int no_sectors_to_go : 1; + unsigned int update_left : 1; + unsigned int sector_mask_left_count_q : 5; + unsigned int sector_mask_left_q : 16; + unsigned int valid_left_q : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int valid_left_q : 1; + unsigned int sector_mask_left_q : 16; + unsigned int sector_mask_left_count_q : 5; + unsigned int update_left : 1; + unsigned int no_sectors_to_go : 1; + unsigned int one_sector_to_go_left_q : 1; + unsigned int : 1; + unsigned int fg0_sends_left : 1; + unsigned int : 1; + unsigned int left_done : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_FETCH_GEN_WALKER_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 4; + unsigned int quad_sel_left : 2; + unsigned int set_sel_left : 2; + unsigned int : 3; + unsigned int right_eq_left : 1; + unsigned int ff_fg_type512 : 3; + unsigned int busy : 1; + unsigned int setquads_to_send : 4; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int setquads_to_send : 4; + unsigned int busy : 1; + unsigned int ff_fg_type512 : 3; + unsigned int right_eq_left : 1; + unsigned int : 3; + unsigned int set_sel_left : 2; + unsigned int quad_sel_left : 2; + unsigned int : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCB_FETCH_GEN_PIPE0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int tc0_arb_rts : 1; + unsigned int : 1; + unsigned int ga_out_rts : 1; + unsigned int : 1; + unsigned int tc_arb_format : 12; + unsigned int tc_arb_fmsopcode : 5; + unsigned int tc_arb_request_type : 2; + unsigned int busy : 1; + unsigned int fgo_busy : 1; + unsigned int ga_busy : 1; + unsigned int mc_sel_q : 2; + unsigned int valid_q : 1; + unsigned int : 1; + unsigned int arb_RTR : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int arb_RTR : 1; + unsigned int : 1; + unsigned int valid_q : 1; + unsigned int mc_sel_q : 2; + unsigned int ga_busy : 1; + unsigned int fgo_busy : 1; + unsigned int busy : 1; + unsigned int tc_arb_request_type : 2; + unsigned int tc_arb_fmsopcode : 5; + unsigned int tc_arb_format : 12; + unsigned int : 1; + unsigned int ga_out_rts : 1; + unsigned int : 1; + unsigned int tc0_arb_rts : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_INPUT0_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 16; + unsigned int empty : 1; + unsigned int full : 1; + unsigned int : 2; + unsigned int valid_q1 : 1; + unsigned int cnt_q1 : 2; + unsigned int last_send_q1 : 1; + unsigned int ip_send : 1; + unsigned int ipbuf_dxt_send : 1; + unsigned int ipbuf_busy : 1; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int ipbuf_busy : 1; + unsigned int ipbuf_dxt_send : 1; + unsigned int ip_send : 1; + unsigned int last_send_q1 : 1; + unsigned int cnt_q1 : 2; + unsigned int valid_q1 : 1; + unsigned int : 2; + unsigned int full : 1; + unsigned int empty : 1; + unsigned int : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_DEGAMMA_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int dgmm_ftfconv_dgmmen : 2; + unsigned int dgmm_ctrl_dgmm8 : 1; + unsigned int dgmm_ctrl_last_send : 1; + unsigned int dgmm_ctrl_send : 1; + unsigned int dgmm_stall : 1; + unsigned int dgmm_pstate : 1; + unsigned int : 25; +#else /* !defined(qLittleEndian) */ + unsigned int : 25; + unsigned int dgmm_pstate : 1; + unsigned int dgmm_stall : 1; + unsigned int dgmm_ctrl_send : 1; + unsigned int dgmm_ctrl_last_send : 1; + unsigned int dgmm_ctrl_dgmm8 : 1; + unsigned int dgmm_ftfconv_dgmmen : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_DXTMUX_SCTARB_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 9; + unsigned int pstate : 1; + unsigned int sctrmx_rtr : 1; + unsigned int dxtc_rtr : 1; + unsigned int : 3; + unsigned int sctrarb_multcyl_send : 1; + unsigned int sctrmx0_sctrarb_rts : 1; + unsigned int : 3; + unsigned int dxtc_sctrarb_send : 1; + unsigned int : 6; + unsigned int dxtc_dgmmpd_last_send : 1; + unsigned int dxtc_dgmmpd_send : 1; + unsigned int dcmp_mux_send : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int dcmp_mux_send : 1; + unsigned int dxtc_dgmmpd_send : 1; + unsigned int dxtc_dgmmpd_last_send : 1; + unsigned int : 6; + unsigned int dxtc_sctrarb_send : 1; + unsigned int : 3; + unsigned int sctrmx0_sctrarb_rts : 1; + unsigned int sctrarb_multcyl_send : 1; + unsigned int : 3; + unsigned int dxtc_rtr : 1; + unsigned int sctrmx_rtr : 1; + unsigned int pstate : 1; + unsigned int : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_DXTC_ARB_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 4; + unsigned int n0_stall : 1; + unsigned int pstate : 1; + unsigned int arb_dcmp01_last_send : 1; + unsigned int arb_dcmp01_cnt : 2; + unsigned int arb_dcmp01_sector : 3; + unsigned int arb_dcmp01_cacheline : 6; + unsigned int arb_dcmp01_format : 12; + unsigned int arb_dcmp01_send : 1; + unsigned int n0_dxt2_4_types : 1; +#else /* !defined(qLittleEndian) */ + unsigned int n0_dxt2_4_types : 1; + unsigned int arb_dcmp01_send : 1; + unsigned int arb_dcmp01_format : 12; + unsigned int arb_dcmp01_cacheline : 6; + unsigned int arb_dcmp01_sector : 3; + unsigned int arb_dcmp01_cnt : 2; + unsigned int arb_dcmp01_last_send : 1; + unsigned int pstate : 1; + unsigned int n0_stall : 1; + unsigned int : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCD_STALLS_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 10; + unsigned int not_multcyl_sctrarb_rtr : 1; + unsigned int not_sctrmx0_sctrarb_rtr : 1; + unsigned int : 5; + unsigned int not_dcmp0_arb_rtr : 1; + unsigned int not_dgmmpd_dxtc_rtr : 1; + unsigned int not_mux_dcmp_rtr : 1; + unsigned int : 11; + unsigned int not_incoming_rtr : 1; +#else /* !defined(qLittleEndian) */ + unsigned int not_incoming_rtr : 1; + unsigned int : 11; + unsigned int not_mux_dcmp_rtr : 1; + unsigned int not_dgmmpd_dxtc_rtr : 1; + unsigned int not_dcmp0_arb_rtr : 1; + unsigned int : 5; + unsigned int not_sctrmx0_sctrarb_rtr : 1; + unsigned int not_multcyl_sctrarb_rtr : 1; + unsigned int : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCO_STALLS_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int quad0_sg_crd_RTR : 1; + unsigned int quad0_rl_sg_RTR : 1; + unsigned int quad0_TCO_TCB_rtr_d : 1; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int quad0_TCO_TCB_rtr_d : 1; + unsigned int quad0_rl_sg_RTR : 1; + unsigned int quad0_sg_crd_RTR : 1; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCO_QUAD0_DEBUG0 { + struct { +#if defined(qLittleEndian) + unsigned int rl_sg_sector_format : 8; + unsigned int rl_sg_end_of_sample : 1; + unsigned int rl_sg_rtr : 1; + unsigned int rl_sg_rts : 1; + unsigned int sg_crd_end_of_sample : 1; + unsigned int sg_crd_rtr : 1; + unsigned int sg_crd_rts : 1; + unsigned int : 2; + unsigned int stageN1_valid_q : 1; + unsigned int : 7; + unsigned int read_cache_q : 1; + unsigned int cache_read_RTR : 1; + unsigned int all_sectors_written_set3 : 1; + unsigned int all_sectors_written_set2 : 1; + unsigned int all_sectors_written_set1 : 1; + unsigned int all_sectors_written_set0 : 1; + unsigned int busy : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int busy : 1; + unsigned int all_sectors_written_set0 : 1; + unsigned int all_sectors_written_set1 : 1; + unsigned int all_sectors_written_set2 : 1; + unsigned int all_sectors_written_set3 : 1; + unsigned int cache_read_RTR : 1; + unsigned int read_cache_q : 1; + unsigned int : 7; + unsigned int stageN1_valid_q : 1; + unsigned int : 2; + unsigned int sg_crd_rts : 1; + unsigned int sg_crd_rtr : 1; + unsigned int sg_crd_end_of_sample : 1; + unsigned int rl_sg_rts : 1; + unsigned int rl_sg_rtr : 1; + unsigned int rl_sg_end_of_sample : 1; + unsigned int rl_sg_sector_format : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union TCO_QUAD0_DEBUG1 { + struct { +#if defined(qLittleEndian) + unsigned int fifo_busy : 1; + unsigned int empty : 1; + unsigned int full : 1; + unsigned int write_enable : 1; + unsigned int fifo_write_ptr : 7; + unsigned int fifo_read_ptr : 7; + unsigned int : 2; + unsigned int cache_read_busy : 1; + unsigned int latency_fifo_busy : 1; + unsigned int input_quad_busy : 1; + unsigned int tco_quad_pipe_busy : 1; + unsigned int TCB_TCO_rtr_d : 1; + unsigned int TCB_TCO_xfc_q : 1; + unsigned int rl_sg_rtr : 1; + unsigned int rl_sg_rts : 1; + unsigned int sg_crd_rtr : 1; + unsigned int sg_crd_rts : 1; + unsigned int TCO_TCB_read_xfc : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int TCO_TCB_read_xfc : 1; + unsigned int sg_crd_rts : 1; + unsigned int sg_crd_rtr : 1; + unsigned int rl_sg_rts : 1; + unsigned int rl_sg_rtr : 1; + unsigned int TCB_TCO_xfc_q : 1; + unsigned int TCB_TCO_rtr_d : 1; + unsigned int tco_quad_pipe_busy : 1; + unsigned int input_quad_busy : 1; + unsigned int latency_fifo_busy : 1; + unsigned int cache_read_busy : 1; + unsigned int : 2; + unsigned int fifo_read_ptr : 7; + unsigned int fifo_write_ptr : 7; + unsigned int write_enable : 1; + unsigned int full : 1; + unsigned int empty : 1; + unsigned int fifo_busy : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_GPR_MANAGEMENT { + struct { +#if defined(qLittleEndian) + unsigned int REG_DYNAMIC : 1; + unsigned int : 3; + unsigned int REG_SIZE_PIX : 7; + unsigned int : 1; + unsigned int REG_SIZE_VTX : 7; + unsigned int : 13; +#else /* !defined(qLittleEndian) */ + unsigned int : 13; + unsigned int REG_SIZE_VTX : 7; + unsigned int : 1; + unsigned int REG_SIZE_PIX : 7; + unsigned int : 3; + unsigned int REG_DYNAMIC : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FLOW_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int INPUT_ARBITRATION_POLICY : 2; + unsigned int : 2; + unsigned int ONE_THREAD : 1; + unsigned int : 3; + unsigned int ONE_ALU : 1; + unsigned int : 3; + unsigned int CF_WR_BASE : 4; + unsigned int NO_PV_PS : 1; + unsigned int NO_LOOP_EXIT : 1; + unsigned int NO_CEXEC_OPTIMIZE : 1; + unsigned int TEXTURE_ARBITRATION_POLICY : 2; + unsigned int VC_ARBITRATION_POLICY : 1; + unsigned int ALU_ARBITRATION_POLICY : 1; + unsigned int NO_ARB_EJECT : 1; + unsigned int NO_CFS_EJECT : 1; + unsigned int POS_EXP_PRIORITY : 1; + unsigned int NO_EARLY_THREAD_TERMINATION : 1; + unsigned int PS_PREFETCH_COLOR_ALLOC : 1; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int PS_PREFETCH_COLOR_ALLOC : 1; + unsigned int NO_EARLY_THREAD_TERMINATION : 1; + unsigned int POS_EXP_PRIORITY : 1; + unsigned int NO_CFS_EJECT : 1; + unsigned int NO_ARB_EJECT : 1; + unsigned int ALU_ARBITRATION_POLICY : 1; + unsigned int VC_ARBITRATION_POLICY : 1; + unsigned int TEXTURE_ARBITRATION_POLICY : 2; + unsigned int NO_CEXEC_OPTIMIZE : 1; + unsigned int NO_LOOP_EXIT : 1; + unsigned int NO_PV_PS : 1; + unsigned int CF_WR_BASE : 4; + unsigned int : 3; + unsigned int ONE_ALU : 1; + unsigned int : 3; + unsigned int ONE_THREAD : 1; + unsigned int : 2; + unsigned int INPUT_ARBITRATION_POLICY : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INST_STORE_MANAGMENT { + struct { +#if defined(qLittleEndian) + unsigned int INST_BASE_PIX : 12; + unsigned int : 4; + unsigned int INST_BASE_VTX : 12; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int INST_BASE_VTX : 12; + unsigned int : 4; + unsigned int INST_BASE_PIX : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_RESOURCE_MANAGMENT { + struct { +#if defined(qLittleEndian) + unsigned int VTX_THREAD_BUF_ENTRIES : 8; + unsigned int PIX_THREAD_BUF_ENTRIES : 8; + unsigned int EXPORT_BUF_ENTRIES : 9; + unsigned int : 7; +#else /* !defined(qLittleEndian) */ + unsigned int : 7; + unsigned int EXPORT_BUF_ENTRIES : 9; + unsigned int PIX_THREAD_BUF_ENTRIES : 8; + unsigned int VTX_THREAD_BUF_ENTRIES : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_EO_RT { + struct { +#if defined(qLittleEndian) + unsigned int EO_CONSTANTS_RT : 8; + unsigned int : 8; + unsigned int EO_TSTATE_RT : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int EO_TSTATE_RT : 8; + unsigned int : 8; + unsigned int EO_CONSTANTS_RT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_MISC { + struct { +#if defined(qLittleEndian) + unsigned int DB_ALUCST_SIZE : 11; + unsigned int : 1; + unsigned int DB_TSTATE_SIZE : 8; + unsigned int DB_READ_CTX : 1; + unsigned int RESERVED : 2; + unsigned int DB_READ_MEMORY : 2; + unsigned int DB_WEN_MEMORY_0 : 1; + unsigned int DB_WEN_MEMORY_1 : 1; + unsigned int DB_WEN_MEMORY_2 : 1; + unsigned int DB_WEN_MEMORY_3 : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int DB_WEN_MEMORY_3 : 1; + unsigned int DB_WEN_MEMORY_2 : 1; + unsigned int DB_WEN_MEMORY_1 : 1; + unsigned int DB_WEN_MEMORY_0 : 1; + unsigned int DB_READ_MEMORY : 2; + unsigned int RESERVED : 2; + unsigned int DB_READ_CTX : 1; + unsigned int DB_TSTATE_SIZE : 8; + unsigned int : 1; + unsigned int DB_ALUCST_SIZE : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_ACTIVITY_METER_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int TIMEBASE : 8; + unsigned int THRESHOLD_LOW : 8; + unsigned int THRESHOLD_HIGH : 8; + unsigned int SPARE : 8; +#else /* !defined(qLittleEndian) */ + unsigned int SPARE : 8; + unsigned int THRESHOLD_HIGH : 8; + unsigned int THRESHOLD_LOW : 8; + unsigned int TIMEBASE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_ACTIVITY_METER_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int PERCENT_BUSY : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERCENT_BUSY : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INPUT_ARB_PRIORITY { + struct { +#if defined(qLittleEndian) + unsigned int PC_AVAIL_WEIGHT : 3; + unsigned int PC_AVAIL_SIGN : 1; + unsigned int SX_AVAIL_WEIGHT : 3; + unsigned int SX_AVAIL_SIGN : 1; + unsigned int THRESHOLD : 10; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int THRESHOLD : 10; + unsigned int SX_AVAIL_SIGN : 1; + unsigned int SX_AVAIL_WEIGHT : 3; + unsigned int PC_AVAIL_SIGN : 1; + unsigned int PC_AVAIL_WEIGHT : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_THREAD_ARB_PRIORITY { + struct { +#if defined(qLittleEndian) + unsigned int PC_AVAIL_WEIGHT : 3; + unsigned int PC_AVAIL_SIGN : 1; + unsigned int SX_AVAIL_WEIGHT : 3; + unsigned int SX_AVAIL_SIGN : 1; + unsigned int THRESHOLD : 10; + unsigned int RESERVED : 2; + unsigned int VS_PRIORITIZE_SERIAL : 1; + unsigned int PS_PRIORITIZE_SERIAL : 1; + unsigned int USE_SERIAL_COUNT_THRESHOLD : 1; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int USE_SERIAL_COUNT_THRESHOLD : 1; + unsigned int PS_PRIORITIZE_SERIAL : 1; + unsigned int VS_PRIORITIZE_SERIAL : 1; + unsigned int RESERVED : 2; + unsigned int THRESHOLD : 10; + unsigned int SX_AVAIL_SIGN : 1; + unsigned int SX_AVAIL_WEIGHT : 3; + unsigned int PC_AVAIL_SIGN : 1; + unsigned int PC_AVAIL_WEIGHT : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_VS_WATCHDOG_TIMER { + struct { +#if defined(qLittleEndian) + unsigned int ENABLE : 1; + unsigned int TIMEOUT_COUNT : 31; +#else /* !defined(qLittleEndian) */ + unsigned int TIMEOUT_COUNT : 31; + unsigned int ENABLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PS_WATCHDOG_TIMER { + struct { +#if defined(qLittleEndian) + unsigned int ENABLE : 1; + unsigned int TIMEOUT_COUNT : 31; +#else /* !defined(qLittleEndian) */ + unsigned int TIMEOUT_COUNT : 31; + unsigned int ENABLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INT_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int PS_WATCHDOG_MASK : 1; + unsigned int VS_WATCHDOG_MASK : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int VS_WATCHDOG_MASK : 1; + unsigned int PS_WATCHDOG_MASK : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INT_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int PS_WATCHDOG_TIMEOUT : 1; + unsigned int VS_WATCHDOG_TIMEOUT : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int VS_WATCHDOG_TIMEOUT : 1; + unsigned int PS_WATCHDOG_TIMEOUT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INT_ACK { + struct { +#if defined(qLittleEndian) + unsigned int PS_WATCHDOG_ACK : 1; + unsigned int VS_WATCHDOG_ACK : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int VS_WATCHDOG_ACK : 1; + unsigned int PS_WATCHDOG_ACK : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_INPUT_FSM { + struct { +#if defined(qLittleEndian) + unsigned int VC_VSR_LD : 3; + unsigned int RESERVED : 1; + unsigned int VC_GPR_LD : 4; + unsigned int PC_PISM : 3; + unsigned int RESERVED1 : 1; + unsigned int PC_AS : 3; + unsigned int PC_INTERP_CNT : 5; + unsigned int PC_GPR_SIZE : 8; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int PC_GPR_SIZE : 8; + unsigned int PC_INTERP_CNT : 5; + unsigned int PC_AS : 3; + unsigned int RESERVED1 : 1; + unsigned int PC_PISM : 3; + unsigned int VC_GPR_LD : 4; + unsigned int RESERVED : 1; + unsigned int VC_VSR_LD : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_CONST_MGR_FSM { + struct { +#if defined(qLittleEndian) + unsigned int TEX_CONST_EVENT_STATE : 5; + unsigned int RESERVED1 : 3; + unsigned int ALU_CONST_EVENT_STATE : 5; + unsigned int RESERVED2 : 3; + unsigned int ALU_CONST_CNTX_VALID : 2; + unsigned int TEX_CONST_CNTX_VALID : 2; + unsigned int CNTX0_VTX_EVENT_DONE : 1; + unsigned int CNTX0_PIX_EVENT_DONE : 1; + unsigned int CNTX1_VTX_EVENT_DONE : 1; + unsigned int CNTX1_PIX_EVENT_DONE : 1; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int CNTX1_PIX_EVENT_DONE : 1; + unsigned int CNTX1_VTX_EVENT_DONE : 1; + unsigned int CNTX0_PIX_EVENT_DONE : 1; + unsigned int CNTX0_VTX_EVENT_DONE : 1; + unsigned int TEX_CONST_CNTX_VALID : 2; + unsigned int ALU_CONST_CNTX_VALID : 2; + unsigned int RESERVED2 : 3; + unsigned int ALU_CONST_EVENT_STATE : 5; + unsigned int RESERVED1 : 3; + unsigned int TEX_CONST_EVENT_STATE : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_TP_FSM { + struct { +#if defined(qLittleEndian) + unsigned int EX_TP : 3; + unsigned int RESERVED0 : 1; + unsigned int CF_TP : 4; + unsigned int IF_TP : 3; + unsigned int RESERVED1 : 1; + unsigned int TIS_TP : 2; + unsigned int RESERVED2 : 2; + unsigned int GS_TP : 2; + unsigned int RESERVED3 : 2; + unsigned int FCR_TP : 2; + unsigned int RESERVED4 : 2; + unsigned int FCS_TP : 2; + unsigned int RESERVED5 : 2; + unsigned int ARB_TR_TP : 3; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int ARB_TR_TP : 3; + unsigned int RESERVED5 : 2; + unsigned int FCS_TP : 2; + unsigned int RESERVED4 : 2; + unsigned int FCR_TP : 2; + unsigned int RESERVED3 : 2; + unsigned int GS_TP : 2; + unsigned int RESERVED2 : 2; + unsigned int TIS_TP : 2; + unsigned int RESERVED1 : 1; + unsigned int IF_TP : 3; + unsigned int CF_TP : 4; + unsigned int RESERVED0 : 1; + unsigned int EX_TP : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_FSM_ALU_0 { + struct { +#if defined(qLittleEndian) + unsigned int EX_ALU_0 : 3; + unsigned int RESERVED0 : 1; + unsigned int CF_ALU_0 : 4; + unsigned int IF_ALU_0 : 3; + unsigned int RESERVED1 : 1; + unsigned int DU1_ALU_0 : 3; + unsigned int RESERVED2 : 1; + unsigned int DU0_ALU_0 : 3; + unsigned int RESERVED3 : 1; + unsigned int AIS_ALU_0 : 3; + unsigned int RESERVED4 : 1; + unsigned int ACS_ALU_0 : 3; + unsigned int RESERVED5 : 1; + unsigned int ARB_TR_ALU : 3; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int ARB_TR_ALU : 3; + unsigned int RESERVED5 : 1; + unsigned int ACS_ALU_0 : 3; + unsigned int RESERVED4 : 1; + unsigned int AIS_ALU_0 : 3; + unsigned int RESERVED3 : 1; + unsigned int DU0_ALU_0 : 3; + unsigned int RESERVED2 : 1; + unsigned int DU1_ALU_0 : 3; + unsigned int RESERVED1 : 1; + unsigned int IF_ALU_0 : 3; + unsigned int CF_ALU_0 : 4; + unsigned int RESERVED0 : 1; + unsigned int EX_ALU_0 : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_FSM_ALU_1 { + struct { +#if defined(qLittleEndian) + unsigned int EX_ALU_0 : 3; + unsigned int RESERVED0 : 1; + unsigned int CF_ALU_0 : 4; + unsigned int IF_ALU_0 : 3; + unsigned int RESERVED1 : 1; + unsigned int DU1_ALU_0 : 3; + unsigned int RESERVED2 : 1; + unsigned int DU0_ALU_0 : 3; + unsigned int RESERVED3 : 1; + unsigned int AIS_ALU_0 : 3; + unsigned int RESERVED4 : 1; + unsigned int ACS_ALU_0 : 3; + unsigned int RESERVED5 : 1; + unsigned int ARB_TR_ALU : 3; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int ARB_TR_ALU : 3; + unsigned int RESERVED5 : 1; + unsigned int ACS_ALU_0 : 3; + unsigned int RESERVED4 : 1; + unsigned int AIS_ALU_0 : 3; + unsigned int RESERVED3 : 1; + unsigned int DU0_ALU_0 : 3; + unsigned int RESERVED2 : 1; + unsigned int DU1_ALU_0 : 3; + unsigned int RESERVED1 : 1; + unsigned int IF_ALU_0 : 3; + unsigned int CF_ALU_0 : 4; + unsigned int RESERVED0 : 1; + unsigned int EX_ALU_0 : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_EXP_ALLOC { + struct { +#if defined(qLittleEndian) + unsigned int POS_BUF_AVAIL : 4; + unsigned int COLOR_BUF_AVAIL : 8; + unsigned int EA_BUF_AVAIL : 3; + unsigned int RESERVED : 1; + unsigned int ALLOC_TBL_BUF_AVAIL : 6; + unsigned int : 10; +#else /* !defined(qLittleEndian) */ + unsigned int : 10; + unsigned int ALLOC_TBL_BUF_AVAIL : 6; + unsigned int RESERVED : 1; + unsigned int EA_BUF_AVAIL : 3; + unsigned int COLOR_BUF_AVAIL : 8; + unsigned int POS_BUF_AVAIL : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PTR_BUFF { + struct { +#if defined(qLittleEndian) + unsigned int END_OF_BUFFER : 1; + unsigned int DEALLOC_CNT : 4; + unsigned int QUAL_NEW_VECTOR : 1; + unsigned int EVENT_CONTEXT_ID : 3; + unsigned int SC_EVENT_ID : 5; + unsigned int QUAL_EVENT : 1; + unsigned int PRIM_TYPE_POLYGON : 1; + unsigned int EF_EMPTY : 1; + unsigned int VTX_SYNC_CNT : 11; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int VTX_SYNC_CNT : 11; + unsigned int EF_EMPTY : 1; + unsigned int PRIM_TYPE_POLYGON : 1; + unsigned int QUAL_EVENT : 1; + unsigned int SC_EVENT_ID : 5; + unsigned int EVENT_CONTEXT_ID : 3; + unsigned int QUAL_NEW_VECTOR : 1; + unsigned int DEALLOC_CNT : 4; + unsigned int END_OF_BUFFER : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_GPR_VTX { + struct { +#if defined(qLittleEndian) + unsigned int VTX_TAIL_PTR : 7; + unsigned int RESERVED : 1; + unsigned int VTX_HEAD_PTR : 7; + unsigned int RESERVED1 : 1; + unsigned int VTX_MAX : 7; + unsigned int RESERVED2 : 1; + unsigned int VTX_FREE : 7; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int VTX_FREE : 7; + unsigned int RESERVED2 : 1; + unsigned int VTX_MAX : 7; + unsigned int RESERVED1 : 1; + unsigned int VTX_HEAD_PTR : 7; + unsigned int RESERVED : 1; + unsigned int VTX_TAIL_PTR : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_GPR_PIX { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TAIL_PTR : 7; + unsigned int RESERVED : 1; + unsigned int PIX_HEAD_PTR : 7; + unsigned int RESERVED1 : 1; + unsigned int PIX_MAX : 7; + unsigned int RESERVED2 : 1; + unsigned int PIX_FREE : 7; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int PIX_FREE : 7; + unsigned int RESERVED2 : 1; + unsigned int PIX_MAX : 7; + unsigned int RESERVED1 : 1; + unsigned int PIX_HEAD_PTR : 7; + unsigned int RESERVED : 1; + unsigned int PIX_TAIL_PTR : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_TB_STATUS_SEL { + struct { +#if defined(qLittleEndian) + unsigned int VTX_TB_STATUS_REG_SEL : 4; + unsigned int VTX_TB_STATE_MEM_DW_SEL : 3; + unsigned int VTX_TB_STATE_MEM_RD_ADDR : 4; + unsigned int VTX_TB_STATE_MEM_RD_EN : 1; + unsigned int PIX_TB_STATE_MEM_RD_EN : 1; + unsigned int : 1; + unsigned int DEBUG_BUS_TRIGGER_SEL : 2; + unsigned int PIX_TB_STATUS_REG_SEL : 4; + unsigned int PIX_TB_STATE_MEM_DW_SEL : 3; + unsigned int PIX_TB_STATE_MEM_RD_ADDR : 6; + unsigned int VC_THREAD_BUF_DLY : 2; + unsigned int DISABLE_STRICT_CTX_SYNC : 1; +#else /* !defined(qLittleEndian) */ + unsigned int DISABLE_STRICT_CTX_SYNC : 1; + unsigned int VC_THREAD_BUF_DLY : 2; + unsigned int PIX_TB_STATE_MEM_RD_ADDR : 6; + unsigned int PIX_TB_STATE_MEM_DW_SEL : 3; + unsigned int PIX_TB_STATUS_REG_SEL : 4; + unsigned int DEBUG_BUS_TRIGGER_SEL : 2; + unsigned int : 1; + unsigned int PIX_TB_STATE_MEM_RD_EN : 1; + unsigned int VTX_TB_STATE_MEM_RD_EN : 1; + unsigned int VTX_TB_STATE_MEM_RD_ADDR : 4; + unsigned int VTX_TB_STATE_MEM_DW_SEL : 3; + unsigned int VTX_TB_STATUS_REG_SEL : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_VTX_TB_0 { + struct { +#if defined(qLittleEndian) + unsigned int VTX_HEAD_PTR_Q : 4; + unsigned int TAIL_PTR_Q : 4; + unsigned int FULL_CNT_Q : 4; + unsigned int NXT_POS_ALLOC_CNT : 4; + unsigned int NXT_PC_ALLOC_CNT : 4; + unsigned int SX_EVENT_FULL : 1; + unsigned int BUSY_Q : 1; + unsigned int : 10; +#else /* !defined(qLittleEndian) */ + unsigned int : 10; + unsigned int BUSY_Q : 1; + unsigned int SX_EVENT_FULL : 1; + unsigned int NXT_PC_ALLOC_CNT : 4; + unsigned int NXT_POS_ALLOC_CNT : 4; + unsigned int FULL_CNT_Q : 4; + unsigned int TAIL_PTR_Q : 4; + unsigned int VTX_HEAD_PTR_Q : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_VTX_TB_1 { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_PTR : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int VS_DONE_PTR : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_VTX_TB_STATUS_REG { + struct { +#if defined(qLittleEndian) + unsigned int VS_STATUS_REG : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_STATUS_REG : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_VTX_TB_STATE_MEM { + struct { +#if defined(qLittleEndian) + unsigned int VS_STATE_MEM : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_STATE_MEM : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_0 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_HEAD_PTR : 6; + unsigned int TAIL_PTR : 6; + unsigned int FULL_CNT : 7; + unsigned int NXT_PIX_ALLOC_CNT : 6; + unsigned int NXT_PIX_EXP_CNT : 6; + unsigned int BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int BUSY : 1; + unsigned int NXT_PIX_EXP_CNT : 6; + unsigned int NXT_PIX_ALLOC_CNT : 6; + unsigned int FULL_CNT : 7; + unsigned int TAIL_PTR : 6; + unsigned int PIX_HEAD_PTR : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATUS_REG_0 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATUS_REG_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATUS_REG_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATUS_REG_1 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATUS_REG_1 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATUS_REG_1 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATUS_REG_2 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATUS_REG_2 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATUS_REG_2 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATUS_REG_3 { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATUS_REG_3 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATUS_REG_3 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_PIX_TB_STATE_MEM { + struct { +#if defined(qLittleEndian) + unsigned int PIX_TB_STATE_MEM : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PIX_TB_STATE_MEM : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER2_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER3_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER2_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER2_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER3_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PERFCOUNTER3_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SX_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SX_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SX_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_ALU_0 { + struct { +#if defined(qLittleEndian) + unsigned int VECTOR_RESULT : 6; + unsigned int VECTOR_DST_REL : 1; + unsigned int LOW_PRECISION_16B_FP : 1; + unsigned int SCALAR_RESULT : 6; + unsigned int SCALAR_DST_REL : 1; + unsigned int EXPORT_DATA : 1; + unsigned int VECTOR_WRT_MSK : 4; + unsigned int SCALAR_WRT_MSK : 4; + unsigned int VECTOR_CLAMP : 1; + unsigned int SCALAR_CLAMP : 1; + unsigned int SCALAR_OPCODE : 6; +#else /* !defined(qLittleEndian) */ + unsigned int SCALAR_OPCODE : 6; + unsigned int SCALAR_CLAMP : 1; + unsigned int VECTOR_CLAMP : 1; + unsigned int SCALAR_WRT_MSK : 4; + unsigned int VECTOR_WRT_MSK : 4; + unsigned int EXPORT_DATA : 1; + unsigned int SCALAR_DST_REL : 1; + unsigned int SCALAR_RESULT : 6; + unsigned int LOW_PRECISION_16B_FP : 1; + unsigned int VECTOR_DST_REL : 1; + unsigned int VECTOR_RESULT : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_ALU_1 { + struct { +#if defined(qLittleEndian) + unsigned int SRC_C_SWIZZLE_R : 2; + unsigned int SRC_C_SWIZZLE_G : 2; + unsigned int SRC_C_SWIZZLE_B : 2; + unsigned int SRC_C_SWIZZLE_A : 2; + unsigned int SRC_B_SWIZZLE_R : 2; + unsigned int SRC_B_SWIZZLE_G : 2; + unsigned int SRC_B_SWIZZLE_B : 2; + unsigned int SRC_B_SWIZZLE_A : 2; + unsigned int SRC_A_SWIZZLE_R : 2; + unsigned int SRC_A_SWIZZLE_G : 2; + unsigned int SRC_A_SWIZZLE_B : 2; + unsigned int SRC_A_SWIZZLE_A : 2; + unsigned int SRC_C_ARG_MOD : 1; + unsigned int SRC_B_ARG_MOD : 1; + unsigned int SRC_A_ARG_MOD : 1; + unsigned int PRED_SELECT : 2; + unsigned int RELATIVE_ADDR : 1; + unsigned int CONST_1_REL_ABS : 1; + unsigned int CONST_0_REL_ABS : 1; +#else /* !defined(qLittleEndian) */ + unsigned int CONST_0_REL_ABS : 1; + unsigned int CONST_1_REL_ABS : 1; + unsigned int RELATIVE_ADDR : 1; + unsigned int PRED_SELECT : 2; + unsigned int SRC_A_ARG_MOD : 1; + unsigned int SRC_B_ARG_MOD : 1; + unsigned int SRC_C_ARG_MOD : 1; + unsigned int SRC_A_SWIZZLE_A : 2; + unsigned int SRC_A_SWIZZLE_B : 2; + unsigned int SRC_A_SWIZZLE_G : 2; + unsigned int SRC_A_SWIZZLE_R : 2; + unsigned int SRC_B_SWIZZLE_A : 2; + unsigned int SRC_B_SWIZZLE_B : 2; + unsigned int SRC_B_SWIZZLE_G : 2; + unsigned int SRC_B_SWIZZLE_R : 2; + unsigned int SRC_C_SWIZZLE_A : 2; + unsigned int SRC_C_SWIZZLE_B : 2; + unsigned int SRC_C_SWIZZLE_G : 2; + unsigned int SRC_C_SWIZZLE_R : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_ALU_2 { + struct { +#if defined(qLittleEndian) + unsigned int SRC_C_REG_PTR : 6; + unsigned int REG_SELECT_C : 1; + unsigned int REG_ABS_MOD_C : 1; + unsigned int SRC_B_REG_PTR : 6; + unsigned int REG_SELECT_B : 1; + unsigned int REG_ABS_MOD_B : 1; + unsigned int SRC_A_REG_PTR : 6; + unsigned int REG_SELECT_A : 1; + unsigned int REG_ABS_MOD_A : 1; + unsigned int VECTOR_OPCODE : 5; + unsigned int SRC_C_SEL : 1; + unsigned int SRC_B_SEL : 1; + unsigned int SRC_A_SEL : 1; +#else /* !defined(qLittleEndian) */ + unsigned int SRC_A_SEL : 1; + unsigned int SRC_B_SEL : 1; + unsigned int SRC_C_SEL : 1; + unsigned int VECTOR_OPCODE : 5; + unsigned int REG_ABS_MOD_A : 1; + unsigned int REG_SELECT_A : 1; + unsigned int SRC_A_REG_PTR : 6; + unsigned int REG_ABS_MOD_B : 1; + unsigned int REG_SELECT_B : 1; + unsigned int SRC_B_REG_PTR : 6; + unsigned int REG_ABS_MOD_C : 1; + unsigned int REG_SELECT_C : 1; + unsigned int SRC_C_REG_PTR : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_EXEC_0 { + struct { +#if defined(qLittleEndian) + unsigned int ADDRESS : 9; + unsigned int RESERVED : 3; + unsigned int COUNT : 3; + unsigned int YIELD : 1; + unsigned int INST_TYPE_0 : 1; + unsigned int INST_SERIAL_0 : 1; + unsigned int INST_TYPE_1 : 1; + unsigned int INST_SERIAL_1 : 1; + unsigned int INST_TYPE_2 : 1; + unsigned int INST_SERIAL_2 : 1; + unsigned int INST_TYPE_3 : 1; + unsigned int INST_SERIAL_3 : 1; + unsigned int INST_TYPE_4 : 1; + unsigned int INST_SERIAL_4 : 1; + unsigned int INST_TYPE_5 : 1; + unsigned int INST_SERIAL_5 : 1; + unsigned int INST_VC_0 : 1; + unsigned int INST_VC_1 : 1; + unsigned int INST_VC_2 : 1; + unsigned int INST_VC_3 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int INST_VC_3 : 1; + unsigned int INST_VC_2 : 1; + unsigned int INST_VC_1 : 1; + unsigned int INST_VC_0 : 1; + unsigned int INST_SERIAL_5 : 1; + unsigned int INST_TYPE_5 : 1; + unsigned int INST_SERIAL_4 : 1; + unsigned int INST_TYPE_4 : 1; + unsigned int INST_SERIAL_3 : 1; + unsigned int INST_TYPE_3 : 1; + unsigned int INST_SERIAL_2 : 1; + unsigned int INST_TYPE_2 : 1; + unsigned int INST_SERIAL_1 : 1; + unsigned int INST_TYPE_1 : 1; + unsigned int INST_SERIAL_0 : 1; + unsigned int INST_TYPE_0 : 1; + unsigned int YIELD : 1; + unsigned int COUNT : 3; + unsigned int RESERVED : 3; + unsigned int ADDRESS : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_EXEC_1 { + struct { +#if defined(qLittleEndian) + unsigned int INST_VC_4 : 1; + unsigned int INST_VC_5 : 1; + unsigned int BOOL_ADDR : 8; + unsigned int CONDITION : 1; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; + unsigned int ADDRESS : 9; + unsigned int RESERVED : 3; + unsigned int COUNT : 3; + unsigned int YIELD : 1; +#else /* !defined(qLittleEndian) */ + unsigned int YIELD : 1; + unsigned int COUNT : 3; + unsigned int RESERVED : 3; + unsigned int ADDRESS : 9; + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int CONDITION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int INST_VC_5 : 1; + unsigned int INST_VC_4 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_EXEC_2 { + struct { +#if defined(qLittleEndian) + unsigned int INST_TYPE_0 : 1; + unsigned int INST_SERIAL_0 : 1; + unsigned int INST_TYPE_1 : 1; + unsigned int INST_SERIAL_1 : 1; + unsigned int INST_TYPE_2 : 1; + unsigned int INST_SERIAL_2 : 1; + unsigned int INST_TYPE_3 : 1; + unsigned int INST_SERIAL_3 : 1; + unsigned int INST_TYPE_4 : 1; + unsigned int INST_SERIAL_4 : 1; + unsigned int INST_TYPE_5 : 1; + unsigned int INST_SERIAL_5 : 1; + unsigned int INST_VC_0 : 1; + unsigned int INST_VC_1 : 1; + unsigned int INST_VC_2 : 1; + unsigned int INST_VC_3 : 1; + unsigned int INST_VC_4 : 1; + unsigned int INST_VC_5 : 1; + unsigned int BOOL_ADDR : 8; + unsigned int CONDITION : 1; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; +#else /* !defined(qLittleEndian) */ + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int CONDITION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int INST_VC_5 : 1; + unsigned int INST_VC_4 : 1; + unsigned int INST_VC_3 : 1; + unsigned int INST_VC_2 : 1; + unsigned int INST_VC_1 : 1; + unsigned int INST_VC_0 : 1; + unsigned int INST_SERIAL_5 : 1; + unsigned int INST_TYPE_5 : 1; + unsigned int INST_SERIAL_4 : 1; + unsigned int INST_TYPE_4 : 1; + unsigned int INST_SERIAL_3 : 1; + unsigned int INST_TYPE_3 : 1; + unsigned int INST_SERIAL_2 : 1; + unsigned int INST_TYPE_2 : 1; + unsigned int INST_SERIAL_1 : 1; + unsigned int INST_TYPE_1 : 1; + unsigned int INST_SERIAL_0 : 1; + unsigned int INST_TYPE_0 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_LOOP_0 { + struct { +#if defined(qLittleEndian) + unsigned int ADDRESS : 10; + unsigned int RESERVED_0 : 6; + unsigned int LOOP_ID : 5; + unsigned int RESERVED_1 : 11; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_1 : 11; + unsigned int LOOP_ID : 5; + unsigned int RESERVED_0 : 6; + unsigned int ADDRESS : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_LOOP_1 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED_0 : 11; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; + unsigned int ADDRESS : 10; + unsigned int RESERVED_1 : 6; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_1 : 6; + unsigned int ADDRESS : 10; + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int RESERVED_0 : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_LOOP_2 { + struct { +#if defined(qLittleEndian) + unsigned int LOOP_ID : 5; + unsigned int RESERVED : 22; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; +#else /* !defined(qLittleEndian) */ + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int RESERVED : 22; + unsigned int LOOP_ID : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_JMP_CALL_0 { + struct { +#if defined(qLittleEndian) + unsigned int ADDRESS : 10; + unsigned int RESERVED_0 : 3; + unsigned int FORCE_CALL : 1; + unsigned int PREDICATED_JMP : 1; + unsigned int RESERVED_1 : 17; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_1 : 17; + unsigned int PREDICATED_JMP : 1; + unsigned int FORCE_CALL : 1; + unsigned int RESERVED_0 : 3; + unsigned int ADDRESS : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_JMP_CALL_1 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED_0 : 1; + unsigned int DIRECTION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int CONDITION : 1; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; + unsigned int ADDRESS : 10; + unsigned int RESERVED_1 : 3; + unsigned int FORCE_CALL : 1; + unsigned int RESERVED_2 : 2; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_2 : 2; + unsigned int FORCE_CALL : 1; + unsigned int RESERVED_1 : 3; + unsigned int ADDRESS : 10; + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int CONDITION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int DIRECTION : 1; + unsigned int RESERVED_0 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_JMP_CALL_2 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED : 17; + unsigned int DIRECTION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int CONDITION : 1; + unsigned int ADDRESS_MODE : 1; + unsigned int OPCODE : 4; +#else /* !defined(qLittleEndian) */ + unsigned int OPCODE : 4; + unsigned int ADDRESS_MODE : 1; + unsigned int CONDITION : 1; + unsigned int BOOL_ADDR : 8; + unsigned int DIRECTION : 1; + unsigned int RESERVED : 17; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_ALLOC_0 { + struct { +#if defined(qLittleEndian) + unsigned int SIZE : 4; + unsigned int RESERVED : 28; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED : 28; + unsigned int SIZE : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_ALLOC_1 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED_0 : 8; + unsigned int NO_SERIAL : 1; + unsigned int BUFFER_SELECT : 2; + unsigned int ALLOC_MODE : 1; + unsigned int OPCODE : 4; + unsigned int SIZE : 4; + unsigned int RESERVED_1 : 12; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED_1 : 12; + unsigned int SIZE : 4; + unsigned int OPCODE : 4; + unsigned int ALLOC_MODE : 1; + unsigned int BUFFER_SELECT : 2; + unsigned int NO_SERIAL : 1; + unsigned int RESERVED_0 : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_CF_ALLOC_2 { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED : 24; + unsigned int NO_SERIAL : 1; + unsigned int BUFFER_SELECT : 2; + unsigned int ALLOC_MODE : 1; + unsigned int OPCODE : 4; +#else /* !defined(qLittleEndian) */ + unsigned int OPCODE : 4; + unsigned int ALLOC_MODE : 1; + unsigned int BUFFER_SELECT : 2; + unsigned int NO_SERIAL : 1; + unsigned int RESERVED : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_TFETCH_0 { + struct { +#if defined(qLittleEndian) + unsigned int OPCODE : 5; + unsigned int SRC_GPR : 6; + unsigned int SRC_GPR_AM : 1; + unsigned int DST_GPR : 6; + unsigned int DST_GPR_AM : 1; + unsigned int FETCH_VALID_ONLY : 1; + unsigned int CONST_INDEX : 5; + unsigned int TX_COORD_DENORM : 1; + unsigned int SRC_SEL_X : 2; + unsigned int SRC_SEL_Y : 2; + unsigned int SRC_SEL_Z : 2; +#else /* !defined(qLittleEndian) */ + unsigned int SRC_SEL_Z : 2; + unsigned int SRC_SEL_Y : 2; + unsigned int SRC_SEL_X : 2; + unsigned int TX_COORD_DENORM : 1; + unsigned int CONST_INDEX : 5; + unsigned int FETCH_VALID_ONLY : 1; + unsigned int DST_GPR_AM : 1; + unsigned int DST_GPR : 6; + unsigned int SRC_GPR_AM : 1; + unsigned int SRC_GPR : 6; + unsigned int OPCODE : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_TFETCH_1 { + struct { +#if defined(qLittleEndian) + unsigned int DST_SEL_X : 3; + unsigned int DST_SEL_Y : 3; + unsigned int DST_SEL_Z : 3; + unsigned int DST_SEL_W : 3; + unsigned int MAG_FILTER : 2; + unsigned int MIN_FILTER : 2; + unsigned int MIP_FILTER : 2; + unsigned int ANISO_FILTER : 3; + unsigned int ARBITRARY_FILTER : 3; + unsigned int VOL_MAG_FILTER : 2; + unsigned int VOL_MIN_FILTER : 2; + unsigned int USE_COMP_LOD : 1; + unsigned int USE_REG_LOD : 2; + unsigned int PRED_SELECT : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PRED_SELECT : 1; + unsigned int USE_REG_LOD : 2; + unsigned int USE_COMP_LOD : 1; + unsigned int VOL_MIN_FILTER : 2; + unsigned int VOL_MAG_FILTER : 2; + unsigned int ARBITRARY_FILTER : 3; + unsigned int ANISO_FILTER : 3; + unsigned int MIP_FILTER : 2; + unsigned int MIN_FILTER : 2; + unsigned int MAG_FILTER : 2; + unsigned int DST_SEL_W : 3; + unsigned int DST_SEL_Z : 3; + unsigned int DST_SEL_Y : 3; + unsigned int DST_SEL_X : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_TFETCH_2 { + struct { +#if defined(qLittleEndian) + unsigned int USE_REG_GRADIENTS : 1; + unsigned int SAMPLE_LOCATION : 1; + unsigned int LOD_BIAS : 7; + unsigned int UNUSED : 7; + unsigned int OFFSET_X : 5; + unsigned int OFFSET_Y : 5; + unsigned int OFFSET_Z : 5; + unsigned int PRED_CONDITION : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PRED_CONDITION : 1; + unsigned int OFFSET_Z : 5; + unsigned int OFFSET_Y : 5; + unsigned int OFFSET_X : 5; + unsigned int UNUSED : 7; + unsigned int LOD_BIAS : 7; + unsigned int SAMPLE_LOCATION : 1; + unsigned int USE_REG_GRADIENTS : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_VFETCH_0 { + struct { +#if defined(qLittleEndian) + unsigned int OPCODE : 5; + unsigned int SRC_GPR : 6; + unsigned int SRC_GPR_AM : 1; + unsigned int DST_GPR : 6; + unsigned int DST_GPR_AM : 1; + unsigned int MUST_BE_ONE : 1; + unsigned int CONST_INDEX : 5; + unsigned int CONST_INDEX_SEL : 2; + unsigned int : 3; + unsigned int SRC_SEL : 2; +#else /* !defined(qLittleEndian) */ + unsigned int SRC_SEL : 2; + unsigned int : 3; + unsigned int CONST_INDEX_SEL : 2; + unsigned int CONST_INDEX : 5; + unsigned int MUST_BE_ONE : 1; + unsigned int DST_GPR_AM : 1; + unsigned int DST_GPR : 6; + unsigned int SRC_GPR_AM : 1; + unsigned int SRC_GPR : 6; + unsigned int OPCODE : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_VFETCH_1 { + struct { +#if defined(qLittleEndian) + unsigned int DST_SEL_X : 3; + unsigned int DST_SEL_Y : 3; + unsigned int DST_SEL_Z : 3; + unsigned int DST_SEL_W : 3; + unsigned int FORMAT_COMP_ALL : 1; + unsigned int NUM_FORMAT_ALL : 1; + unsigned int SIGNED_RF_MODE_ALL : 1; + unsigned int : 1; + unsigned int DATA_FORMAT : 6; + unsigned int : 1; + unsigned int EXP_ADJUST_ALL : 7; + unsigned int : 1; + unsigned int PRED_SELECT : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PRED_SELECT : 1; + unsigned int : 1; + unsigned int EXP_ADJUST_ALL : 7; + unsigned int : 1; + unsigned int DATA_FORMAT : 6; + unsigned int : 1; + unsigned int SIGNED_RF_MODE_ALL : 1; + unsigned int NUM_FORMAT_ALL : 1; + unsigned int FORMAT_COMP_ALL : 1; + unsigned int DST_SEL_W : 3; + unsigned int DST_SEL_Z : 3; + unsigned int DST_SEL_Y : 3; + unsigned int DST_SEL_X : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INSTRUCTION_VFETCH_2 { + struct { +#if defined(qLittleEndian) + unsigned int STRIDE : 8; + unsigned int : 8; + unsigned int OFFSET : 8; + unsigned int : 7; + unsigned int PRED_CONDITION : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PRED_CONDITION : 1; + unsigned int : 7; + unsigned int OFFSET : 8; + unsigned int : 8; + unsigned int STRIDE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_0 { + struct { +#if defined(qLittleEndian) + unsigned int RED : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RED : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_1 { + struct { +#if defined(qLittleEndian) + unsigned int GREEN : 32; +#else /* !defined(qLittleEndian) */ + unsigned int GREEN : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_2 { + struct { +#if defined(qLittleEndian) + unsigned int BLUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BLUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_3 { + struct { +#if defined(qLittleEndian) + unsigned int ALPHA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ALPHA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_0 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_1 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_2 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_3 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_4 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_5 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_VFETCH_0 { + struct { +#if defined(qLittleEndian) + unsigned int TYPE : 1; + unsigned int STATE : 1; + unsigned int BASE_ADDRESS : 30; +#else /* !defined(qLittleEndian) */ + unsigned int BASE_ADDRESS : 30; + unsigned int STATE : 1; + unsigned int TYPE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_VFETCH_1 { + struct { +#if defined(qLittleEndian) + unsigned int ENDIAN_SWAP : 2; + unsigned int LIMIT_ADDRESS : 30; +#else /* !defined(qLittleEndian) */ + unsigned int LIMIT_ADDRESS : 30; + unsigned int ENDIAN_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_T2 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_T3 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_BOOLEANS { + struct { +#if defined(qLittleEndian) + unsigned int CF_BOOLEANS_0 : 8; + unsigned int CF_BOOLEANS_1 : 8; + unsigned int CF_BOOLEANS_2 : 8; + unsigned int CF_BOOLEANS_3 : 8; +#else /* !defined(qLittleEndian) */ + unsigned int CF_BOOLEANS_3 : 8; + unsigned int CF_BOOLEANS_2 : 8; + unsigned int CF_BOOLEANS_1 : 8; + unsigned int CF_BOOLEANS_0 : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_LOOP { + struct { +#if defined(qLittleEndian) + unsigned int CF_LOOP_COUNT : 8; + unsigned int CF_LOOP_START : 8; + unsigned int CF_LOOP_STEP : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int CF_LOOP_STEP : 8; + unsigned int CF_LOOP_START : 8; + unsigned int CF_LOOP_COUNT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_RT_0 { + struct { +#if defined(qLittleEndian) + unsigned int RED : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RED : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_RT_1 { + struct { +#if defined(qLittleEndian) + unsigned int GREEN : 32; +#else /* !defined(qLittleEndian) */ + unsigned int GREEN : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_RT_2 { + struct { +#if defined(qLittleEndian) + unsigned int BLUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BLUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONSTANT_RT_3 { + struct { +#if defined(qLittleEndian) + unsigned int ALPHA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ALPHA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_0 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_1 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_2 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_3 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_4 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_FETCH_RT_5 { + struct { +#if defined(qLittleEndian) + unsigned int VALUE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VALUE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_RT_BOOLEANS { + struct { +#if defined(qLittleEndian) + unsigned int CF_BOOLEANS_0 : 8; + unsigned int CF_BOOLEANS_1 : 8; + unsigned int CF_BOOLEANS_2 : 8; + unsigned int CF_BOOLEANS_3 : 8; +#else /* !defined(qLittleEndian) */ + unsigned int CF_BOOLEANS_3 : 8; + unsigned int CF_BOOLEANS_2 : 8; + unsigned int CF_BOOLEANS_1 : 8; + unsigned int CF_BOOLEANS_0 : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_RT_LOOP { + struct { +#if defined(qLittleEndian) + unsigned int CF_LOOP_COUNT : 8; + unsigned int CF_LOOP_START : 8; + unsigned int CF_LOOP_STEP : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int CF_LOOP_STEP : 8; + unsigned int CF_LOOP_START : 8; + unsigned int CF_LOOP_COUNT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_VS_PROGRAM { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 12; + unsigned int SIZE : 12; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int SIZE : 12; + unsigned int BASE : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PS_PROGRAM { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 12; + unsigned int SIZE : 12; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int SIZE : 12; + unsigned int BASE : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_PROGRAM_SIZE { + struct { +#if defined(qLittleEndian) + unsigned int VS_CF_SIZE : 11; + unsigned int : 1; + unsigned int PS_CF_SIZE : 11; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int PS_CF_SIZE : 11; + unsigned int : 1; + unsigned int VS_CF_SIZE : 11; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_INTERPOLATOR_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int PARAM_SHADE : 16; + unsigned int SAMPLING_PATTERN : 16; +#else /* !defined(qLittleEndian) */ + unsigned int SAMPLING_PATTERN : 16; + unsigned int PARAM_SHADE : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PROGRAM_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int VS_NUM_REG : 6; + unsigned int : 2; + unsigned int PS_NUM_REG : 6; + unsigned int : 2; + unsigned int VS_RESOURCE : 1; + unsigned int PS_RESOURCE : 1; + unsigned int PARAM_GEN : 1; + unsigned int GEN_INDEX_PIX : 1; + unsigned int VS_EXPORT_COUNT : 4; + unsigned int VS_EXPORT_MODE : 3; + unsigned int PS_EXPORT_MODE : 4; + unsigned int GEN_INDEX_VTX : 1; +#else /* !defined(qLittleEndian) */ + unsigned int GEN_INDEX_VTX : 1; + unsigned int PS_EXPORT_MODE : 4; + unsigned int VS_EXPORT_MODE : 3; + unsigned int VS_EXPORT_COUNT : 4; + unsigned int GEN_INDEX_PIX : 1; + unsigned int PARAM_GEN : 1; + unsigned int PS_RESOURCE : 1; + unsigned int VS_RESOURCE : 1; + unsigned int : 2; + unsigned int PS_NUM_REG : 6; + unsigned int : 2; + unsigned int VS_NUM_REG : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_WRAPPING_0 { + struct { +#if defined(qLittleEndian) + unsigned int PARAM_WRAP_0 : 4; + unsigned int PARAM_WRAP_1 : 4; + unsigned int PARAM_WRAP_2 : 4; + unsigned int PARAM_WRAP_3 : 4; + unsigned int PARAM_WRAP_4 : 4; + unsigned int PARAM_WRAP_5 : 4; + unsigned int PARAM_WRAP_6 : 4; + unsigned int PARAM_WRAP_7 : 4; +#else /* !defined(qLittleEndian) */ + unsigned int PARAM_WRAP_7 : 4; + unsigned int PARAM_WRAP_6 : 4; + unsigned int PARAM_WRAP_5 : 4; + unsigned int PARAM_WRAP_4 : 4; + unsigned int PARAM_WRAP_3 : 4; + unsigned int PARAM_WRAP_2 : 4; + unsigned int PARAM_WRAP_1 : 4; + unsigned int PARAM_WRAP_0 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_WRAPPING_1 { + struct { +#if defined(qLittleEndian) + unsigned int PARAM_WRAP_8 : 4; + unsigned int PARAM_WRAP_9 : 4; + unsigned int PARAM_WRAP_10 : 4; + unsigned int PARAM_WRAP_11 : 4; + unsigned int PARAM_WRAP_12 : 4; + unsigned int PARAM_WRAP_13 : 4; + unsigned int PARAM_WRAP_14 : 4; + unsigned int PARAM_WRAP_15 : 4; +#else /* !defined(qLittleEndian) */ + unsigned int PARAM_WRAP_15 : 4; + unsigned int PARAM_WRAP_14 : 4; + unsigned int PARAM_WRAP_13 : 4; + unsigned int PARAM_WRAP_12 : 4; + unsigned int PARAM_WRAP_11 : 4; + unsigned int PARAM_WRAP_10 : 4; + unsigned int PARAM_WRAP_9 : 4; + unsigned int PARAM_WRAP_8 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_VS_CONST { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 9; + unsigned int : 3; + unsigned int SIZE : 9; + unsigned int : 11; +#else /* !defined(qLittleEndian) */ + unsigned int : 11; + unsigned int SIZE : 9; + unsigned int : 3; + unsigned int BASE : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_PS_CONST { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 9; + unsigned int : 3; + unsigned int SIZE : 9; + unsigned int : 11; +#else /* !defined(qLittleEndian) */ + unsigned int : 11; + unsigned int SIZE : 9; + unsigned int : 3; + unsigned int BASE : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CONTEXT_MISC { + struct { +#if defined(qLittleEndian) + unsigned int INST_PRED_OPTIMIZE : 1; + unsigned int SC_OUTPUT_SCREEN_XY : 1; + unsigned int SC_SAMPLE_CNTL : 2; + unsigned int : 4; + unsigned int PARAM_GEN_POS : 8; + unsigned int PERFCOUNTER_REF : 1; + unsigned int YEILD_OPTIMIZE : 1; + unsigned int TX_CACHE_SEL : 1; + unsigned int : 13; +#else /* !defined(qLittleEndian) */ + unsigned int : 13; + unsigned int TX_CACHE_SEL : 1; + unsigned int YEILD_OPTIMIZE : 1; + unsigned int PERFCOUNTER_REF : 1; + unsigned int PARAM_GEN_POS : 8; + unsigned int : 4; + unsigned int SC_SAMPLE_CNTL : 2; + unsigned int SC_OUTPUT_SCREEN_XY : 1; + unsigned int INST_PRED_OPTIMIZE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_CF_RD_BASE { + struct { +#if defined(qLittleEndian) + unsigned int RD_BASE : 3; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int RD_BASE : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_MISC_0 { + struct { +#if defined(qLittleEndian) + unsigned int DB_PROB_ON : 1; + unsigned int : 3; + unsigned int DB_PROB_BREAK : 1; + unsigned int : 3; + unsigned int DB_PROB_ADDR : 11; + unsigned int : 5; + unsigned int DB_PROB_COUNT : 8; +#else /* !defined(qLittleEndian) */ + unsigned int DB_PROB_COUNT : 8; + unsigned int : 5; + unsigned int DB_PROB_ADDR : 11; + unsigned int : 3; + unsigned int DB_PROB_BREAK : 1; + unsigned int : 3; + unsigned int DB_PROB_ON : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SQ_DEBUG_MISC_1 { + struct { +#if defined(qLittleEndian) + unsigned int DB_ON_PIX : 1; + unsigned int DB_ON_VTX : 1; + unsigned int : 6; + unsigned int DB_INST_COUNT : 8; + unsigned int DB_BREAK_ADDR : 11; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int DB_BREAK_ADDR : 11; + unsigned int DB_INST_COUNT : 8; + unsigned int : 6; + unsigned int DB_ON_VTX : 1; + unsigned int DB_ON_PIX : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_ARBITER_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int SAME_PAGE_LIMIT : 6; + unsigned int SAME_PAGE_GRANULARITY : 1; + unsigned int L1_ARB_ENABLE : 1; + unsigned int L1_ARB_HOLD_ENABLE : 1; + unsigned int L2_ARB_CONTROL : 1; + unsigned int PAGE_SIZE : 3; + unsigned int TC_REORDER_ENABLE : 1; + unsigned int TC_ARB_HOLD_ENABLE : 1; + unsigned int IN_FLIGHT_LIMIT_ENABLE : 1; + unsigned int IN_FLIGHT_LIMIT : 6; + unsigned int CP_CLNT_ENABLE : 1; + unsigned int VGT_CLNT_ENABLE : 1; + unsigned int TC_CLNT_ENABLE : 1; + unsigned int RB_CLNT_ENABLE : 1; + unsigned int PA_CLNT_ENABLE : 1; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int PA_CLNT_ENABLE : 1; + unsigned int RB_CLNT_ENABLE : 1; + unsigned int TC_CLNT_ENABLE : 1; + unsigned int VGT_CLNT_ENABLE : 1; + unsigned int CP_CLNT_ENABLE : 1; + unsigned int IN_FLIGHT_LIMIT : 6; + unsigned int IN_FLIGHT_LIMIT_ENABLE : 1; + unsigned int TC_ARB_HOLD_ENABLE : 1; + unsigned int TC_REORDER_ENABLE : 1; + unsigned int PAGE_SIZE : 3; + unsigned int L2_ARB_CONTROL : 1; + unsigned int L1_ARB_HOLD_ENABLE : 1; + unsigned int L1_ARB_ENABLE : 1; + unsigned int SAME_PAGE_GRANULARITY : 1; + unsigned int SAME_PAGE_LIMIT : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_CLNT_AXI_ID_REUSE { + struct { +#if defined(qLittleEndian) + unsigned int CPw_ID : 3; + unsigned int RESERVED1 : 1; + unsigned int RBw_ID : 3; + unsigned int RESERVED2 : 1; + unsigned int MMUr_ID : 3; + unsigned int RESERVED3 : 1; + unsigned int PAw_ID : 3; + unsigned int : 17; +#else /* !defined(qLittleEndian) */ + unsigned int : 17; + unsigned int PAw_ID : 3; + unsigned int RESERVED3 : 1; + unsigned int MMUr_ID : 3; + unsigned int RESERVED2 : 1; + unsigned int RBw_ID : 3; + unsigned int RESERVED1 : 1; + unsigned int CPw_ID : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_INTERRUPT_MASK { + struct { +#if defined(qLittleEndian) + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int AXI_READ_ERROR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_INTERRUPT_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int AXI_READ_ERROR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_INTERRUPT_CLEAR { + struct { +#if defined(qLittleEndian) + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int MMU_PAGE_FAULT : 1; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int AXI_READ_ERROR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_AXI_ERROR { + struct { +#if defined(qLittleEndian) + unsigned int AXI_READ_ID : 3; + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_WRITE_ID : 3; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int AXI_WRITE_ERROR : 1; + unsigned int AXI_WRITE_ID : 3; + unsigned int AXI_READ_ERROR : 1; + unsigned int AXI_READ_ID : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER0_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int N_VALUE : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int N_VALUE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER1_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int N_VALUE : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int N_VALUE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER1_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNTER_LOW : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNTER_LOW : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNTER_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNTER_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_CTRL { + struct { +#if defined(qLittleEndian) + unsigned int INDEX : 6; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int INDEX : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_AXI_HALT_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int AXI_HALT : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int AXI_HALT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG00 { + struct { +#if defined(qLittleEndian) + unsigned int MH_BUSY : 1; + unsigned int TRANS_OUTSTANDING : 1; + unsigned int CP_REQUEST : 1; + unsigned int VGT_REQUEST : 1; + unsigned int TC_REQUEST : 1; + unsigned int TC_CAM_EMPTY : 1; + unsigned int TC_CAM_FULL : 1; + unsigned int TCD_EMPTY : 1; + unsigned int TCD_FULL : 1; + unsigned int RB_REQUEST : 1; + unsigned int PA_REQUEST : 1; + unsigned int MH_CLK_EN_STATE : 1; + unsigned int ARQ_EMPTY : 1; + unsigned int ARQ_FULL : 1; + unsigned int WDB_EMPTY : 1; + unsigned int WDB_FULL : 1; + unsigned int AXI_AVALID : 1; + unsigned int AXI_AREADY : 1; + unsigned int AXI_ARVALID : 1; + unsigned int AXI_ARREADY : 1; + unsigned int AXI_WVALID : 1; + unsigned int AXI_WREADY : 1; + unsigned int AXI_RVALID : 1; + unsigned int AXI_RREADY : 1; + unsigned int AXI_BVALID : 1; + unsigned int AXI_BREADY : 1; + unsigned int AXI_HALT_REQ : 1; + unsigned int AXI_HALT_ACK : 1; + unsigned int AXI_RDY_ENA : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int AXI_RDY_ENA : 1; + unsigned int AXI_HALT_ACK : 1; + unsigned int AXI_HALT_REQ : 1; + unsigned int AXI_BREADY : 1; + unsigned int AXI_BVALID : 1; + unsigned int AXI_RREADY : 1; + unsigned int AXI_RVALID : 1; + unsigned int AXI_WREADY : 1; + unsigned int AXI_WVALID : 1; + unsigned int AXI_ARREADY : 1; + unsigned int AXI_ARVALID : 1; + unsigned int AXI_AREADY : 1; + unsigned int AXI_AVALID : 1; + unsigned int WDB_FULL : 1; + unsigned int WDB_EMPTY : 1; + unsigned int ARQ_FULL : 1; + unsigned int ARQ_EMPTY : 1; + unsigned int MH_CLK_EN_STATE : 1; + unsigned int PA_REQUEST : 1; + unsigned int RB_REQUEST : 1; + unsigned int TCD_FULL : 1; + unsigned int TCD_EMPTY : 1; + unsigned int TC_CAM_FULL : 1; + unsigned int TC_CAM_EMPTY : 1; + unsigned int TC_REQUEST : 1; + unsigned int VGT_REQUEST : 1; + unsigned int CP_REQUEST : 1; + unsigned int TRANS_OUTSTANDING : 1; + unsigned int MH_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG01 { + struct { +#if defined(qLittleEndian) + unsigned int CP_SEND_q : 1; + unsigned int CP_RTR_q : 1; + unsigned int CP_WRITE_q : 1; + unsigned int CP_TAG_q : 3; + unsigned int CP_BLEN_q : 1; + unsigned int VGT_SEND_q : 1; + unsigned int VGT_RTR_q : 1; + unsigned int VGT_TAG_q : 1; + unsigned int TC_SEND_q : 1; + unsigned int TC_RTR_q : 1; + unsigned int TC_BLEN_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_written : 1; + unsigned int RB_SEND_q : 1; + unsigned int RB_RTR_q : 1; + unsigned int PA_SEND_q : 1; + unsigned int PA_RTR_q : 1; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int PA_RTR_q : 1; + unsigned int PA_SEND_q : 1; + unsigned int RB_RTR_q : 1; + unsigned int RB_SEND_q : 1; + unsigned int TC_MH_written : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_BLEN_q : 1; + unsigned int TC_RTR_q : 1; + unsigned int TC_SEND_q : 1; + unsigned int VGT_TAG_q : 1; + unsigned int VGT_RTR_q : 1; + unsigned int VGT_SEND_q : 1; + unsigned int CP_BLEN_q : 1; + unsigned int CP_TAG_q : 3; + unsigned int CP_WRITE_q : 1; + unsigned int CP_RTR_q : 1; + unsigned int CP_SEND_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG02 { + struct { +#if defined(qLittleEndian) + unsigned int MH_CP_grb_send : 1; + unsigned int MH_VGT_grb_send : 1; + unsigned int MH_TC_mcsend : 1; + unsigned int MH_CLNT_rlast : 1; + unsigned int MH_CLNT_tag : 3; + unsigned int RDC_RID : 3; + unsigned int RDC_RRESP : 2; + unsigned int MH_CP_writeclean : 1; + unsigned int MH_RB_writeclean : 1; + unsigned int MH_PA_writeclean : 1; + unsigned int BRC_BID : 3; + unsigned int BRC_BRESP : 2; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int BRC_BRESP : 2; + unsigned int BRC_BID : 3; + unsigned int MH_PA_writeclean : 1; + unsigned int MH_RB_writeclean : 1; + unsigned int MH_CP_writeclean : 1; + unsigned int RDC_RRESP : 2; + unsigned int RDC_RID : 3; + unsigned int MH_CLNT_tag : 3; + unsigned int MH_CLNT_rlast : 1; + unsigned int MH_TC_mcsend : 1; + unsigned int MH_VGT_grb_send : 1; + unsigned int MH_CP_grb_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG03 { + struct { +#if defined(qLittleEndian) + unsigned int MH_CLNT_data_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int MH_CLNT_data_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG04 { + struct { +#if defined(qLittleEndian) + unsigned int MH_CLNT_data_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int MH_CLNT_data_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG05 { + struct { +#if defined(qLittleEndian) + unsigned int CP_MH_send : 1; + unsigned int CP_MH_write : 1; + unsigned int CP_MH_tag : 3; + unsigned int CP_MH_ad_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int CP_MH_ad_31_5 : 27; + unsigned int CP_MH_tag : 3; + unsigned int CP_MH_write : 1; + unsigned int CP_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG06 { + struct { +#if defined(qLittleEndian) + unsigned int CP_MH_data_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CP_MH_data_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG07 { + struct { +#if defined(qLittleEndian) + unsigned int CP_MH_data_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CP_MH_data_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG08 { + struct { +#if defined(qLittleEndian) + unsigned int CP_MH_be : 8; + unsigned int RB_MH_be : 8; + unsigned int PA_MH_be : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int PA_MH_be : 8; + unsigned int RB_MH_be : 8; + unsigned int CP_MH_be : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG09 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 3; + unsigned int VGT_MH_send : 1; + unsigned int VGT_MH_tagbe : 1; + unsigned int VGT_MH_ad_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int VGT_MH_ad_31_5 : 27; + unsigned int VGT_MH_tagbe : 1; + unsigned int VGT_MH_send : 1; + unsigned int ALWAYS_ZERO : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG10 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 2; + unsigned int TC_MH_send : 1; + unsigned int TC_MH_mask : 2; + unsigned int TC_MH_addr_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int TC_MH_addr_31_5 : 27; + unsigned int TC_MH_mask : 2; + unsigned int TC_MH_send : 1; + unsigned int ALWAYS_ZERO : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG11 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_info : 25; + unsigned int TC_MH_send : 1; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int TC_MH_send : 1; + unsigned int TC_MH_info : 25; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG12 { + struct { +#if defined(qLittleEndian) + unsigned int MH_TC_mcinfo : 25; + unsigned int MH_TC_mcinfo_send : 1; + unsigned int TC_MH_written : 1; + unsigned int : 5; +#else /* !defined(qLittleEndian) */ + unsigned int : 5; + unsigned int TC_MH_written : 1; + unsigned int MH_TC_mcinfo_send : 1; + unsigned int MH_TC_mcinfo : 25; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG13 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 2; + unsigned int TC_ROQ_SEND : 1; + unsigned int TC_ROQ_MASK : 2; + unsigned int TC_ROQ_ADDR_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int TC_ROQ_ADDR_31_5 : 27; + unsigned int TC_ROQ_MASK : 2; + unsigned int TC_ROQ_SEND : 1; + unsigned int ALWAYS_ZERO : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG14 { + struct { +#if defined(qLittleEndian) + unsigned int TC_ROQ_INFO : 25; + unsigned int TC_ROQ_SEND : 1; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int TC_ROQ_SEND : 1; + unsigned int TC_ROQ_INFO : 25; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG15 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 4; + unsigned int RB_MH_send : 1; + unsigned int RB_MH_addr_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int RB_MH_addr_31_5 : 27; + unsigned int RB_MH_send : 1; + unsigned int ALWAYS_ZERO : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG16 { + struct { +#if defined(qLittleEndian) + unsigned int RB_MH_data_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RB_MH_data_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG17 { + struct { +#if defined(qLittleEndian) + unsigned int RB_MH_data_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RB_MH_data_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG18 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 4; + unsigned int PA_MH_send : 1; + unsigned int PA_MH_addr_31_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int PA_MH_addr_31_5 : 27; + unsigned int PA_MH_send : 1; + unsigned int ALWAYS_ZERO : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG19 { + struct { +#if defined(qLittleEndian) + unsigned int PA_MH_data_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PA_MH_data_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG20 { + struct { +#if defined(qLittleEndian) + unsigned int PA_MH_data_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PA_MH_data_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG21 { + struct { +#if defined(qLittleEndian) + unsigned int AVALID_q : 1; + unsigned int AREADY_q : 1; + unsigned int AID_q : 3; + unsigned int ALEN_q_2_0 : 3; + unsigned int ARVALID_q : 1; + unsigned int ARREADY_q : 1; + unsigned int ARID_q : 3; + unsigned int ARLEN_q_1_0 : 2; + unsigned int RVALID_q : 1; + unsigned int RREADY_q : 1; + unsigned int RLAST_q : 1; + unsigned int RID_q : 3; + unsigned int WVALID_q : 1; + unsigned int WREADY_q : 1; + unsigned int WLAST_q : 1; + unsigned int WID_q : 3; + unsigned int BVALID_q : 1; + unsigned int BREADY_q : 1; + unsigned int BID_q : 3; +#else /* !defined(qLittleEndian) */ + unsigned int BID_q : 3; + unsigned int BREADY_q : 1; + unsigned int BVALID_q : 1; + unsigned int WID_q : 3; + unsigned int WLAST_q : 1; + unsigned int WREADY_q : 1; + unsigned int WVALID_q : 1; + unsigned int RID_q : 3; + unsigned int RLAST_q : 1; + unsigned int RREADY_q : 1; + unsigned int RVALID_q : 1; + unsigned int ARLEN_q_1_0 : 2; + unsigned int ARID_q : 3; + unsigned int ARREADY_q : 1; + unsigned int ARVALID_q : 1; + unsigned int ALEN_q_2_0 : 3; + unsigned int AID_q : 3; + unsigned int AREADY_q : 1; + unsigned int AVALID_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG22 { + struct { +#if defined(qLittleEndian) + unsigned int AVALID_q : 1; + unsigned int AREADY_q : 1; + unsigned int AID_q : 3; + unsigned int ALEN_q_1_0 : 2; + unsigned int ARVALID_q : 1; + unsigned int ARREADY_q : 1; + unsigned int ARID_q : 3; + unsigned int ARLEN_q_1_1 : 1; + unsigned int WVALID_q : 1; + unsigned int WREADY_q : 1; + unsigned int WLAST_q : 1; + unsigned int WID_q : 3; + unsigned int WSTRB_q : 8; + unsigned int BVALID_q : 1; + unsigned int BREADY_q : 1; + unsigned int BID_q : 3; +#else /* !defined(qLittleEndian) */ + unsigned int BID_q : 3; + unsigned int BREADY_q : 1; + unsigned int BVALID_q : 1; + unsigned int WSTRB_q : 8; + unsigned int WID_q : 3; + unsigned int WLAST_q : 1; + unsigned int WREADY_q : 1; + unsigned int WVALID_q : 1; + unsigned int ARLEN_q_1_1 : 1; + unsigned int ARID_q : 3; + unsigned int ARREADY_q : 1; + unsigned int ARVALID_q : 1; + unsigned int ALEN_q_1_0 : 2; + unsigned int AID_q : 3; + unsigned int AREADY_q : 1; + unsigned int AVALID_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG23 { + struct { +#if defined(qLittleEndian) + unsigned int ARC_CTRL_RE_q : 1; + unsigned int CTRL_ARC_ID : 3; + unsigned int CTRL_ARC_PAD : 28; +#else /* !defined(qLittleEndian) */ + unsigned int CTRL_ARC_PAD : 28; + unsigned int CTRL_ARC_ID : 3; + unsigned int ARC_CTRL_RE_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG24 { + struct { +#if defined(qLittleEndian) + unsigned int ALWAYS_ZERO : 2; + unsigned int REG_A : 14; + unsigned int REG_RE : 1; + unsigned int REG_WE : 1; + unsigned int BLOCK_RS : 1; + unsigned int : 13; +#else /* !defined(qLittleEndian) */ + unsigned int : 13; + unsigned int BLOCK_RS : 1; + unsigned int REG_WE : 1; + unsigned int REG_RE : 1; + unsigned int REG_A : 14; + unsigned int ALWAYS_ZERO : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG25 { + struct { +#if defined(qLittleEndian) + unsigned int REG_WD : 32; +#else /* !defined(qLittleEndian) */ + unsigned int REG_WD : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG26 { + struct { +#if defined(qLittleEndian) + unsigned int MH_RBBM_busy : 1; + unsigned int MH_CIB_mh_clk_en_int : 1; + unsigned int MH_CIB_mmu_clk_en_int : 1; + unsigned int MH_CIB_tcroq_clk_en_int : 1; + unsigned int GAT_CLK_ENA : 1; + unsigned int RBBM_MH_clk_en_override : 1; + unsigned int CNT_q : 6; + unsigned int TCD_EMPTY_q : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int MH_BUSY_d : 1; + unsigned int ANY_CLNT_BUSY : 1; + unsigned int MH_MMU_INVALIDATE_INVALIDATE_ALL : 1; + unsigned int MH_MMU_INVALIDATE_INVALIDATE_TC : 1; + unsigned int CP_SEND_q : 1; + unsigned int CP_RTR_q : 1; + unsigned int VGT_SEND_q : 1; + unsigned int VGT_RTR_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_ROQ_RTR_DBG_q : 1; + unsigned int RB_SEND_q : 1; + unsigned int RB_RTR_q : 1; + unsigned int PA_SEND_q : 1; + unsigned int PA_RTR_q : 1; + unsigned int RDC_VALID : 1; + unsigned int RDC_RLAST : 1; + unsigned int TLBMISS_VALID : 1; + unsigned int BRC_VALID : 1; +#else /* !defined(qLittleEndian) */ + unsigned int BRC_VALID : 1; + unsigned int TLBMISS_VALID : 1; + unsigned int RDC_RLAST : 1; + unsigned int RDC_VALID : 1; + unsigned int PA_RTR_q : 1; + unsigned int PA_SEND_q : 1; + unsigned int RB_RTR_q : 1; + unsigned int RB_SEND_q : 1; + unsigned int TC_ROQ_RTR_DBG_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int VGT_RTR_q : 1; + unsigned int VGT_SEND_q : 1; + unsigned int CP_RTR_q : 1; + unsigned int CP_SEND_q : 1; + unsigned int MH_MMU_INVALIDATE_INVALIDATE_TC : 1; + unsigned int MH_MMU_INVALIDATE_INVALIDATE_ALL : 1; + unsigned int ANY_CLNT_BUSY : 1; + unsigned int MH_BUSY_d : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TCD_EMPTY_q : 1; + unsigned int CNT_q : 6; + unsigned int RBBM_MH_clk_en_override : 1; + unsigned int GAT_CLK_ENA : 1; + unsigned int MH_CIB_tcroq_clk_en_int : 1; + unsigned int MH_CIB_mmu_clk_en_int : 1; + unsigned int MH_CIB_mh_clk_en_int : 1; + unsigned int MH_RBBM_busy : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG27 { + struct { +#if defined(qLittleEndian) + unsigned int EFF2_FP_WINNER : 3; + unsigned int EFF2_LRU_WINNER_out : 3; + unsigned int EFF1_WINNER : 3; + unsigned int ARB_WINNER : 3; + unsigned int ARB_WINNER_q : 3; + unsigned int EFF1_WIN : 1; + unsigned int KILL_EFF1 : 1; + unsigned int ARB_HOLD : 1; + unsigned int ARB_RTR_q : 1; + unsigned int CP_SEND_QUAL : 1; + unsigned int VGT_SEND_QUAL : 1; + unsigned int TC_SEND_QUAL : 1; + unsigned int TC_SEND_EFF1_QUAL : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int PA_SEND_QUAL : 1; + unsigned int ARB_QUAL : 1; + unsigned int CP_EFF1_REQ : 1; + unsigned int VGT_EFF1_REQ : 1; + unsigned int TC_EFF1_REQ : 1; + unsigned int RB_EFF1_REQ : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int TCHOLD_IP_q : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TCHOLD_IP_q : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int RB_EFF1_REQ : 1; + unsigned int TC_EFF1_REQ : 1; + unsigned int VGT_EFF1_REQ : 1; + unsigned int CP_EFF1_REQ : 1; + unsigned int ARB_QUAL : 1; + unsigned int PA_SEND_QUAL : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int TC_SEND_EFF1_QUAL : 1; + unsigned int TC_SEND_QUAL : 1; + unsigned int VGT_SEND_QUAL : 1; + unsigned int CP_SEND_QUAL : 1; + unsigned int ARB_RTR_q : 1; + unsigned int ARB_HOLD : 1; + unsigned int KILL_EFF1 : 1; + unsigned int EFF1_WIN : 1; + unsigned int ARB_WINNER_q : 3; + unsigned int ARB_WINNER : 3; + unsigned int EFF1_WINNER : 3; + unsigned int EFF2_LRU_WINNER_out : 3; + unsigned int EFF2_FP_WINNER : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG28 { + struct { +#if defined(qLittleEndian) + unsigned int EFF1_WINNER : 3; + unsigned int ARB_WINNER : 3; + unsigned int CP_SEND_QUAL : 1; + unsigned int VGT_SEND_QUAL : 1; + unsigned int TC_SEND_QUAL : 1; + unsigned int TC_SEND_EFF1_QUAL : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int ARB_QUAL : 1; + unsigned int CP_EFF1_REQ : 1; + unsigned int VGT_EFF1_REQ : 1; + unsigned int TC_EFF1_REQ : 1; + unsigned int RB_EFF1_REQ : 1; + unsigned int EFF1_WIN : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int TC_ARB_HOLD : 1; + unsigned int ARB_HOLD : 1; + unsigned int ARB_RTR_q : 1; + unsigned int SAME_PAGE_LIMIT_COUNT_q : 10; +#else /* !defined(qLittleEndian) */ + unsigned int SAME_PAGE_LIMIT_COUNT_q : 10; + unsigned int ARB_RTR_q : 1; + unsigned int ARB_HOLD : 1; + unsigned int TC_ARB_HOLD : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int KILL_EFF1 : 1; + unsigned int EFF1_WIN : 1; + unsigned int RB_EFF1_REQ : 1; + unsigned int TC_EFF1_REQ : 1; + unsigned int VGT_EFF1_REQ : 1; + unsigned int CP_EFF1_REQ : 1; + unsigned int ARB_QUAL : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int TC_SEND_EFF1_QUAL : 1; + unsigned int TC_SEND_QUAL : 1; + unsigned int VGT_SEND_QUAL : 1; + unsigned int CP_SEND_QUAL : 1; + unsigned int ARB_WINNER : 3; + unsigned int EFF1_WINNER : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG29 { + struct { +#if defined(qLittleEndian) + unsigned int EFF2_LRU_WINNER_out : 3; + unsigned int LEAST_RECENT_INDEX_d : 3; + unsigned int LEAST_RECENT_d : 3; + unsigned int UPDATE_RECENT_STACK_d : 1; + unsigned int ARB_HOLD : 1; + unsigned int ARB_RTR_q : 1; + unsigned int CLNT_REQ : 5; + unsigned int RECENT_d_0 : 3; + unsigned int RECENT_d_1 : 3; + unsigned int RECENT_d_2 : 3; + unsigned int RECENT_d_3 : 3; + unsigned int RECENT_d_4 : 3; +#else /* !defined(qLittleEndian) */ + unsigned int RECENT_d_4 : 3; + unsigned int RECENT_d_3 : 3; + unsigned int RECENT_d_2 : 3; + unsigned int RECENT_d_1 : 3; + unsigned int RECENT_d_0 : 3; + unsigned int CLNT_REQ : 5; + unsigned int ARB_RTR_q : 1; + unsigned int ARB_HOLD : 1; + unsigned int UPDATE_RECENT_STACK_d : 1; + unsigned int LEAST_RECENT_d : 3; + unsigned int LEAST_RECENT_INDEX_d : 3; + unsigned int EFF2_LRU_WINNER_out : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG30 { + struct { +#if defined(qLittleEndian) + unsigned int TC_ARB_HOLD : 1; + unsigned int TC_NOROQ_SAME_ROW_BANK : 1; + unsigned int TC_ROQ_SAME_ROW_BANK : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int TCHOLD_IP_q : 1; + unsigned int TCHOLD_CNT_q : 3; + unsigned int MH_ARBITER_CONFIG_TC_REORDER_ENABLE : 1; + unsigned int TC_ROQ_RTR_DBG_q : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_MH_written : 1; + unsigned int TCD_FULLNESS_CNT_q : 7; + unsigned int WBURST_ACTIVE : 1; + unsigned int WLAST_q : 1; + unsigned int WBURST_IP_q : 1; + unsigned int WBURST_CNT_q : 3; + unsigned int CP_SEND_QUAL : 1; + unsigned int CP_MH_write : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int PA_SEND_QUAL : 1; + unsigned int ARB_WINNER : 3; +#else /* !defined(qLittleEndian) */ + unsigned int ARB_WINNER : 3; + unsigned int PA_SEND_QUAL : 1; + unsigned int RB_SEND_QUAL : 1; + unsigned int CP_MH_write : 1; + unsigned int CP_SEND_QUAL : 1; + unsigned int WBURST_CNT_q : 3; + unsigned int WBURST_IP_q : 1; + unsigned int WLAST_q : 1; + unsigned int WBURST_ACTIVE : 1; + unsigned int TCD_FULLNESS_CNT_q : 7; + unsigned int TC_MH_written : 1; + unsigned int TC_ROQ_SEND_q : 1; + unsigned int TC_ROQ_RTR_DBG_q : 1; + unsigned int MH_ARBITER_CONFIG_TC_REORDER_ENABLE : 1; + unsigned int TCHOLD_CNT_q : 3; + unsigned int TCHOLD_IP_q : 1; + unsigned int TCD_NEARFULL_q : 1; + unsigned int TC_ROQ_SAME_ROW_BANK : 1; + unsigned int TC_NOROQ_SAME_ROW_BANK : 1; + unsigned int TC_ARB_HOLD : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG31 { + struct { +#if defined(qLittleEndian) + unsigned int RF_ARBITER_CONFIG_q : 26; + unsigned int MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3; + unsigned int RF_ARBITER_CONFIG_q : 26; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG32 { + struct { +#if defined(qLittleEndian) + unsigned int SAME_ROW_BANK_q : 8; + unsigned int ROQ_MARK_q : 8; + unsigned int ROQ_VALID_q : 8; + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TC_ROQ_SAME_ROW_BANK_SEL : 1; + unsigned int ANY_SAME_ROW_BANK : 1; + unsigned int TC_EFF1_QUAL : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TC_ROQ_FULL : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TC_ROQ_FULL : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TC_EFF1_QUAL : 1; + unsigned int ANY_SAME_ROW_BANK : 1; + unsigned int TC_ROQ_SAME_ROW_BANK_SEL : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; + unsigned int ROQ_VALID_q : 8; + unsigned int ROQ_MARK_q : 8; + unsigned int SAME_ROW_BANK_q : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG33 { + struct { +#if defined(qLittleEndian) + unsigned int SAME_ROW_BANK_q : 8; + unsigned int ROQ_MARK_d : 8; + unsigned int ROQ_VALID_d : 8; + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TC_ROQ_SAME_ROW_BANK_SEL : 1; + unsigned int ANY_SAME_ROW_BANK : 1; + unsigned int TC_EFF1_QUAL : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TC_ROQ_FULL : 1; +#else /* !defined(qLittleEndian) */ + unsigned int TC_ROQ_FULL : 1; + unsigned int TC_ROQ_EMPTY : 1; + unsigned int TC_EFF1_QUAL : 1; + unsigned int ANY_SAME_ROW_BANK : 1; + unsigned int TC_ROQ_SAME_ROW_BANK_SEL : 1; + unsigned int KILL_EFF1 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; + unsigned int ROQ_VALID_d : 8; + unsigned int ROQ_MARK_d : 8; + unsigned int SAME_ROW_BANK_q : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG34 { + struct { +#if defined(qLittleEndian) + unsigned int SAME_ROW_BANK_WIN : 8; + unsigned int SAME_ROW_BANK_REQ : 8; + unsigned int NON_SAME_ROW_BANK_WIN : 8; + unsigned int NON_SAME_ROW_BANK_REQ : 8; +#else /* !defined(qLittleEndian) */ + unsigned int NON_SAME_ROW_BANK_REQ : 8; + unsigned int NON_SAME_ROW_BANK_WIN : 8; + unsigned int SAME_ROW_BANK_REQ : 8; + unsigned int SAME_ROW_BANK_WIN : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG35 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_0 : 1; + unsigned int ROQ_VALID_q_0 : 1; + unsigned int SAME_ROW_BANK_q_0 : 1; + unsigned int ROQ_ADDR_0 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_0 : 27; + unsigned int SAME_ROW_BANK_q_0 : 1; + unsigned int ROQ_VALID_q_0 : 1; + unsigned int ROQ_MARK_q_0 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG36 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_1 : 1; + unsigned int ROQ_VALID_q_1 : 1; + unsigned int SAME_ROW_BANK_q_1 : 1; + unsigned int ROQ_ADDR_1 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_1 : 27; + unsigned int SAME_ROW_BANK_q_1 : 1; + unsigned int ROQ_VALID_q_1 : 1; + unsigned int ROQ_MARK_q_1 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG37 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_2 : 1; + unsigned int ROQ_VALID_q_2 : 1; + unsigned int SAME_ROW_BANK_q_2 : 1; + unsigned int ROQ_ADDR_2 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_2 : 27; + unsigned int SAME_ROW_BANK_q_2 : 1; + unsigned int ROQ_VALID_q_2 : 1; + unsigned int ROQ_MARK_q_2 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG38 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_3 : 1; + unsigned int ROQ_VALID_q_3 : 1; + unsigned int SAME_ROW_BANK_q_3 : 1; + unsigned int ROQ_ADDR_3 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_3 : 27; + unsigned int SAME_ROW_BANK_q_3 : 1; + unsigned int ROQ_VALID_q_3 : 1; + unsigned int ROQ_MARK_q_3 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG39 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_4 : 1; + unsigned int ROQ_VALID_q_4 : 1; + unsigned int SAME_ROW_BANK_q_4 : 1; + unsigned int ROQ_ADDR_4 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_4 : 27; + unsigned int SAME_ROW_BANK_q_4 : 1; + unsigned int ROQ_VALID_q_4 : 1; + unsigned int ROQ_MARK_q_4 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG40 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_5 : 1; + unsigned int ROQ_VALID_q_5 : 1; + unsigned int SAME_ROW_BANK_q_5 : 1; + unsigned int ROQ_ADDR_5 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_5 : 27; + unsigned int SAME_ROW_BANK_q_5 : 1; + unsigned int ROQ_VALID_q_5 : 1; + unsigned int ROQ_MARK_q_5 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG41 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_6 : 1; + unsigned int ROQ_VALID_q_6 : 1; + unsigned int SAME_ROW_BANK_q_6 : 1; + unsigned int ROQ_ADDR_6 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_6 : 27; + unsigned int SAME_ROW_BANK_q_6 : 1; + unsigned int ROQ_VALID_q_6 : 1; + unsigned int ROQ_MARK_q_6 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG42 { + struct { +#if defined(qLittleEndian) + unsigned int TC_MH_send : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int ROQ_MARK_q_7 : 1; + unsigned int ROQ_VALID_q_7 : 1; + unsigned int SAME_ROW_BANK_q_7 : 1; + unsigned int ROQ_ADDR_7 : 27; +#else /* !defined(qLittleEndian) */ + unsigned int ROQ_ADDR_7 : 27; + unsigned int SAME_ROW_BANK_q_7 : 1; + unsigned int ROQ_VALID_q_7 : 1; + unsigned int ROQ_MARK_q_7 : 1; + unsigned int TC_ROQ_RTR_q : 1; + unsigned int TC_MH_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG43 { + struct { +#if defined(qLittleEndian) + unsigned int ARB_REG_WE_q : 1; + unsigned int ARB_WE : 1; + unsigned int ARB_REG_VALID_q : 1; + unsigned int ARB_RTR_q : 1; + unsigned int ARB_REG_RTR : 1; + unsigned int WDAT_BURST_RTR : 1; + unsigned int MMU_RTR : 1; + unsigned int ARB_ID_q : 3; + unsigned int ARB_WRITE_q : 1; + unsigned int ARB_BLEN_q : 1; + unsigned int ARQ_CTRL_EMPTY : 1; + unsigned int ARQ_FIFO_CNT_q : 3; + unsigned int MMU_WE : 1; + unsigned int ARQ_RTR : 1; + unsigned int MMU_ID : 3; + unsigned int MMU_WRITE : 1; + unsigned int MMU_BLEN : 1; + unsigned int WBURST_IP_q : 1; + unsigned int WDAT_REG_WE_q : 1; + unsigned int WDB_WE : 1; + unsigned int WDB_RTR_SKID_4 : 1; + unsigned int WDB_RTR_SKID_3 : 1; + unsigned int : 4; +#else /* !defined(qLittleEndian) */ + unsigned int : 4; + unsigned int WDB_RTR_SKID_3 : 1; + unsigned int WDB_RTR_SKID_4 : 1; + unsigned int WDB_WE : 1; + unsigned int WDAT_REG_WE_q : 1; + unsigned int WBURST_IP_q : 1; + unsigned int MMU_BLEN : 1; + unsigned int MMU_WRITE : 1; + unsigned int MMU_ID : 3; + unsigned int ARQ_RTR : 1; + unsigned int MMU_WE : 1; + unsigned int ARQ_FIFO_CNT_q : 3; + unsigned int ARQ_CTRL_EMPTY : 1; + unsigned int ARB_BLEN_q : 1; + unsigned int ARB_WRITE_q : 1; + unsigned int ARB_ID_q : 3; + unsigned int MMU_RTR : 1; + unsigned int WDAT_BURST_RTR : 1; + unsigned int ARB_REG_RTR : 1; + unsigned int ARB_RTR_q : 1; + unsigned int ARB_REG_VALID_q : 1; + unsigned int ARB_WE : 1; + unsigned int ARB_REG_WE_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG44 { + struct { +#if defined(qLittleEndian) + unsigned int ARB_WE : 1; + unsigned int ARB_ID_q : 3; + unsigned int ARB_VAD_q : 28; +#else /* !defined(qLittleEndian) */ + unsigned int ARB_VAD_q : 28; + unsigned int ARB_ID_q : 3; + unsigned int ARB_WE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG45 { + struct { +#if defined(qLittleEndian) + unsigned int MMU_WE : 1; + unsigned int MMU_ID : 3; + unsigned int MMU_PAD : 28; +#else /* !defined(qLittleEndian) */ + unsigned int MMU_PAD : 28; + unsigned int MMU_ID : 3; + unsigned int MMU_WE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG46 { + struct { +#if defined(qLittleEndian) + unsigned int WDAT_REG_WE_q : 1; + unsigned int WDB_WE : 1; + unsigned int WDAT_REG_VALID_q : 1; + unsigned int WDB_RTR_SKID_4 : 1; + unsigned int ARB_WSTRB_q : 8; + unsigned int ARB_WLAST : 1; + unsigned int WDB_CTRL_EMPTY : 1; + unsigned int WDB_FIFO_CNT_q : 5; + unsigned int WDC_WDB_RE_q : 1; + unsigned int WDB_WDC_WID : 3; + unsigned int WDB_WDC_WLAST : 1; + unsigned int WDB_WDC_WSTRB : 8; +#else /* !defined(qLittleEndian) */ + unsigned int WDB_WDC_WSTRB : 8; + unsigned int WDB_WDC_WLAST : 1; + unsigned int WDB_WDC_WID : 3; + unsigned int WDC_WDB_RE_q : 1; + unsigned int WDB_FIFO_CNT_q : 5; + unsigned int WDB_CTRL_EMPTY : 1; + unsigned int ARB_WLAST : 1; + unsigned int ARB_WSTRB_q : 8; + unsigned int WDB_RTR_SKID_4 : 1; + unsigned int WDAT_REG_VALID_q : 1; + unsigned int WDB_WE : 1; + unsigned int WDAT_REG_WE_q : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG47 { + struct { +#if defined(qLittleEndian) + unsigned int WDB_WDC_WDATA_31_0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int WDB_WDC_WDATA_31_0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG48 { + struct { +#if defined(qLittleEndian) + unsigned int WDB_WDC_WDATA_63_32 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int WDB_WDC_WDATA_63_32 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG49 { + struct { +#if defined(qLittleEndian) + unsigned int CTRL_ARC_EMPTY : 1; + unsigned int CTRL_RARC_EMPTY : 1; + unsigned int ARQ_CTRL_EMPTY : 1; + unsigned int ARQ_CTRL_WRITE : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int INFLT_LIMIT_q : 1; + unsigned int INFLT_LIMIT_CNT_q : 6; + unsigned int ARC_CTRL_RE_q : 1; + unsigned int RARC_CTRL_RE_q : 1; + unsigned int RVALID_q : 1; + unsigned int RREADY_q : 1; + unsigned int RLAST_q : 1; + unsigned int BVALID_q : 1; + unsigned int BREADY_q : 1; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int BREADY_q : 1; + unsigned int BVALID_q : 1; + unsigned int RLAST_q : 1; + unsigned int RREADY_q : 1; + unsigned int RVALID_q : 1; + unsigned int RARC_CTRL_RE_q : 1; + unsigned int ARC_CTRL_RE_q : 1; + unsigned int INFLT_LIMIT_CNT_q : 6; + unsigned int INFLT_LIMIT_q : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int ARQ_CTRL_WRITE : 1; + unsigned int ARQ_CTRL_EMPTY : 1; + unsigned int CTRL_RARC_EMPTY : 1; + unsigned int CTRL_ARC_EMPTY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG50 { + struct { +#if defined(qLittleEndian) + unsigned int MH_CP_grb_send : 1; + unsigned int MH_VGT_grb_send : 1; + unsigned int MH_TC_mcsend : 1; + unsigned int MH_TLBMISS_SEND : 1; + unsigned int TLBMISS_VALID : 1; + unsigned int RDC_VALID : 1; + unsigned int RDC_RID : 3; + unsigned int RDC_RLAST : 1; + unsigned int RDC_RRESP : 2; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int MMU_ID_REQUEST_q : 1; + unsigned int OUTSTANDING_MMUID_CNT_q : 6; + unsigned int MMU_ID_RESPONSE : 1; + unsigned int TLBMISS_RETURN_CNT_q : 6; + unsigned int CNT_HOLD_q1 : 1; + unsigned int MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3; +#else /* !defined(qLittleEndian) */ + unsigned int MH_CLNT_AXI_ID_REUSE_MMUr_ID : 3; + unsigned int CNT_HOLD_q1 : 1; + unsigned int TLBMISS_RETURN_CNT_q : 6; + unsigned int MMU_ID_RESPONSE : 1; + unsigned int OUTSTANDING_MMUID_CNT_q : 6; + unsigned int MMU_ID_REQUEST_q : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int RDC_RRESP : 2; + unsigned int RDC_RLAST : 1; + unsigned int RDC_RID : 3; + unsigned int RDC_VALID : 1; + unsigned int TLBMISS_VALID : 1; + unsigned int MH_TLBMISS_SEND : 1; + unsigned int MH_TC_mcsend : 1; + unsigned int MH_VGT_grb_send : 1; + unsigned int MH_CP_grb_send : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG51 { + struct { +#if defined(qLittleEndian) + unsigned int RF_MMU_PAGE_FAULT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RF_MMU_PAGE_FAULT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG52 { + struct { +#if defined(qLittleEndian) + unsigned int RF_MMU_CONFIG_q_1_to_0 : 2; + unsigned int ARB_WE : 1; + unsigned int MMU_RTR : 1; + unsigned int RF_MMU_CONFIG_q_25_to_4 : 22; + unsigned int ARB_ID_q : 3; + unsigned int ARB_WRITE_q : 1; + unsigned int client_behavior_q : 2; +#else /* !defined(qLittleEndian) */ + unsigned int client_behavior_q : 2; + unsigned int ARB_WRITE_q : 1; + unsigned int ARB_ID_q : 3; + unsigned int RF_MMU_CONFIG_q_25_to_4 : 22; + unsigned int MMU_RTR : 1; + unsigned int ARB_WE : 1; + unsigned int RF_MMU_CONFIG_q_1_to_0 : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG53 { + struct { +#if defined(qLittleEndian) + unsigned int stage1_valid : 1; + unsigned int IGNORE_TAG_MISS_q : 1; + unsigned int pa_in_mpu_range : 1; + unsigned int tag_match_q : 1; + unsigned int tag_miss_q : 1; + unsigned int va_in_range_q : 1; + unsigned int MMU_MISS : 1; + unsigned int MMU_READ_MISS : 1; + unsigned int MMU_WRITE_MISS : 1; + unsigned int MMU_HIT : 1; + unsigned int MMU_READ_HIT : 1; + unsigned int MMU_WRITE_HIT : 1; + unsigned int MMU_SPLIT_MODE_TC_MISS : 1; + unsigned int MMU_SPLIT_MODE_TC_HIT : 1; + unsigned int MMU_SPLIT_MODE_nonTC_MISS : 1; + unsigned int MMU_SPLIT_MODE_nonTC_HIT : 1; + unsigned int REQ_VA_OFFSET_q : 16; +#else /* !defined(qLittleEndian) */ + unsigned int REQ_VA_OFFSET_q : 16; + unsigned int MMU_SPLIT_MODE_nonTC_HIT : 1; + unsigned int MMU_SPLIT_MODE_nonTC_MISS : 1; + unsigned int MMU_SPLIT_MODE_TC_HIT : 1; + unsigned int MMU_SPLIT_MODE_TC_MISS : 1; + unsigned int MMU_WRITE_HIT : 1; + unsigned int MMU_READ_HIT : 1; + unsigned int MMU_HIT : 1; + unsigned int MMU_WRITE_MISS : 1; + unsigned int MMU_READ_MISS : 1; + unsigned int MMU_MISS : 1; + unsigned int va_in_range_q : 1; + unsigned int tag_miss_q : 1; + unsigned int tag_match_q : 1; + unsigned int pa_in_mpu_range : 1; + unsigned int IGNORE_TAG_MISS_q : 1; + unsigned int stage1_valid : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG54 { + struct { +#if defined(qLittleEndian) + unsigned int ARQ_RTR : 1; + unsigned int MMU_WE : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int MH_TLBMISS_SEND : 1; + unsigned int MMU_STALL_AWAITING_TLB_MISS_FETCH : 1; + unsigned int pa_in_mpu_range : 1; + unsigned int stage1_valid : 1; + unsigned int stage2_valid : 1; + unsigned int client_behavior_q : 2; + unsigned int IGNORE_TAG_MISS_q : 1; + unsigned int tag_match_q : 1; + unsigned int tag_miss_q : 1; + unsigned int va_in_range_q : 1; + unsigned int PTE_FETCH_COMPLETE_q : 1; + unsigned int TAG_valid_q : 16; +#else /* !defined(qLittleEndian) */ + unsigned int TAG_valid_q : 16; + unsigned int PTE_FETCH_COMPLETE_q : 1; + unsigned int va_in_range_q : 1; + unsigned int tag_miss_q : 1; + unsigned int tag_match_q : 1; + unsigned int IGNORE_TAG_MISS_q : 1; + unsigned int client_behavior_q : 2; + unsigned int stage2_valid : 1; + unsigned int stage1_valid : 1; + unsigned int pa_in_mpu_range : 1; + unsigned int MMU_STALL_AWAITING_TLB_MISS_FETCH : 1; + unsigned int MH_TLBMISS_SEND : 1; + unsigned int TLBMISS_CTRL_RTS : 1; + unsigned int CTRL_TLBMISS_RE_q : 1; + unsigned int MMU_WE : 1; + unsigned int ARQ_RTR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG55 { + struct { +#if defined(qLittleEndian) + unsigned int TAG0_VA : 13; + unsigned int TAG_valid_q_0 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG1_VA : 13; + unsigned int TAG_valid_q_1 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_1 : 1; + unsigned int TAG1_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_0 : 1; + unsigned int TAG0_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG56 { + struct { +#if defined(qLittleEndian) + unsigned int TAG2_VA : 13; + unsigned int TAG_valid_q_2 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG3_VA : 13; + unsigned int TAG_valid_q_3 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_3 : 1; + unsigned int TAG3_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_2 : 1; + unsigned int TAG2_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG57 { + struct { +#if defined(qLittleEndian) + unsigned int TAG4_VA : 13; + unsigned int TAG_valid_q_4 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG5_VA : 13; + unsigned int TAG_valid_q_5 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_5 : 1; + unsigned int TAG5_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_4 : 1; + unsigned int TAG4_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG58 { + struct { +#if defined(qLittleEndian) + unsigned int TAG6_VA : 13; + unsigned int TAG_valid_q_6 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG7_VA : 13; + unsigned int TAG_valid_q_7 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_7 : 1; + unsigned int TAG7_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_6 : 1; + unsigned int TAG6_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG59 { + struct { +#if defined(qLittleEndian) + unsigned int TAG8_VA : 13; + unsigned int TAG_valid_q_8 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG9_VA : 13; + unsigned int TAG_valid_q_9 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_9 : 1; + unsigned int TAG9_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_8 : 1; + unsigned int TAG8_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG60 { + struct { +#if defined(qLittleEndian) + unsigned int TAG10_VA : 13; + unsigned int TAG_valid_q_10 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG11_VA : 13; + unsigned int TAG_valid_q_11 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_11 : 1; + unsigned int TAG11_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_10 : 1; + unsigned int TAG10_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG61 { + struct { +#if defined(qLittleEndian) + unsigned int TAG12_VA : 13; + unsigned int TAG_valid_q_12 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG13_VA : 13; + unsigned int TAG_valid_q_13 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_13 : 1; + unsigned int TAG13_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_12 : 1; + unsigned int TAG12_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG62 { + struct { +#if defined(qLittleEndian) + unsigned int TAG14_VA : 13; + unsigned int TAG_valid_q_14 : 1; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG15_VA : 13; + unsigned int TAG_valid_q_15 : 1; + unsigned int : 2; +#else /* !defined(qLittleEndian) */ + unsigned int : 2; + unsigned int TAG_valid_q_15 : 1; + unsigned int TAG15_VA : 13; + unsigned int ALWAYS_ZERO : 2; + unsigned int TAG_valid_q_14 : 1; + unsigned int TAG14_VA : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_DEBUG_REG63 { + struct { +#if defined(qLittleEndian) + unsigned int MH_DBG_DEFAULT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int MH_DBG_DEFAULT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int MMU_ENABLE : 1; + unsigned int SPLIT_MODE_ENABLE : 1; + unsigned int RESERVED1 : 2; + unsigned int RB_W_CLNT_BEHAVIOR : 2; + unsigned int CP_W_CLNT_BEHAVIOR : 2; + unsigned int CP_R0_CLNT_BEHAVIOR : 2; + unsigned int CP_R1_CLNT_BEHAVIOR : 2; + unsigned int CP_R2_CLNT_BEHAVIOR : 2; + unsigned int CP_R3_CLNT_BEHAVIOR : 2; + unsigned int CP_R4_CLNT_BEHAVIOR : 2; + unsigned int VGT_R0_CLNT_BEHAVIOR : 2; + unsigned int VGT_R1_CLNT_BEHAVIOR : 2; + unsigned int TC_R_CLNT_BEHAVIOR : 2; + unsigned int PA_W_CLNT_BEHAVIOR : 2; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int PA_W_CLNT_BEHAVIOR : 2; + unsigned int TC_R_CLNT_BEHAVIOR : 2; + unsigned int VGT_R1_CLNT_BEHAVIOR : 2; + unsigned int VGT_R0_CLNT_BEHAVIOR : 2; + unsigned int CP_R4_CLNT_BEHAVIOR : 2; + unsigned int CP_R3_CLNT_BEHAVIOR : 2; + unsigned int CP_R2_CLNT_BEHAVIOR : 2; + unsigned int CP_R1_CLNT_BEHAVIOR : 2; + unsigned int CP_R0_CLNT_BEHAVIOR : 2; + unsigned int CP_W_CLNT_BEHAVIOR : 2; + unsigned int RB_W_CLNT_BEHAVIOR : 2; + unsigned int RESERVED1 : 2; + unsigned int SPLIT_MODE_ENABLE : 1; + unsigned int MMU_ENABLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_VA_RANGE { + struct { +#if defined(qLittleEndian) + unsigned int NUM_64KB_REGIONS : 12; + unsigned int VA_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int VA_BASE : 20; + unsigned int NUM_64KB_REGIONS : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_PT_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int PT_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int PT_BASE : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_PAGE_FAULT { + struct { +#if defined(qLittleEndian) + unsigned int PAGE_FAULT : 1; + unsigned int OP_TYPE : 1; + unsigned int CLNT_BEHAVIOR : 2; + unsigned int AXI_ID : 3; + unsigned int RESERVED1 : 1; + unsigned int MPU_ADDRESS_OUT_OF_RANGE : 1; + unsigned int ADDRESS_OUT_OF_RANGE : 1; + unsigned int READ_PROTECTION_ERROR : 1; + unsigned int WRITE_PROTECTION_ERROR : 1; + unsigned int REQ_VA : 20; +#else /* !defined(qLittleEndian) */ + unsigned int REQ_VA : 20; + unsigned int WRITE_PROTECTION_ERROR : 1; + unsigned int READ_PROTECTION_ERROR : 1; + unsigned int ADDRESS_OUT_OF_RANGE : 1; + unsigned int MPU_ADDRESS_OUT_OF_RANGE : 1; + unsigned int RESERVED1 : 1; + unsigned int AXI_ID : 3; + unsigned int CLNT_BEHAVIOR : 2; + unsigned int OP_TYPE : 1; + unsigned int PAGE_FAULT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_TRAN_ERROR { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int TRAN_ERROR : 27; +#else /* !defined(qLittleEndian) */ + unsigned int TRAN_ERROR : 27; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_INVALIDATE { + struct { +#if defined(qLittleEndian) + unsigned int INVALIDATE_ALL : 1; + unsigned int INVALIDATE_TC : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int INVALIDATE_TC : 1; + unsigned int INVALIDATE_ALL : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_MPU_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int MPU_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int MPU_BASE : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MH_MMU_MPU_END { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int MPU_END : 20; +#else /* !defined(qLittleEndian) */ + unsigned int MPU_END : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union WAIT_UNTIL { + struct { +#if defined(qLittleEndian) + unsigned int : 1; + unsigned int WAIT_RE_VSYNC : 1; + unsigned int WAIT_FE_VSYNC : 1; + unsigned int WAIT_VSYNC : 1; + unsigned int WAIT_DSPLY_ID0 : 1; + unsigned int WAIT_DSPLY_ID1 : 1; + unsigned int WAIT_DSPLY_ID2 : 1; + unsigned int : 3; + unsigned int WAIT_CMDFIFO : 1; + unsigned int : 3; + unsigned int WAIT_2D_IDLE : 1; + unsigned int WAIT_3D_IDLE : 1; + unsigned int WAIT_2D_IDLECLEAN : 1; + unsigned int WAIT_3D_IDLECLEAN : 1; + unsigned int : 2; + unsigned int CMDFIFO_ENTRIES : 4; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int CMDFIFO_ENTRIES : 4; + unsigned int : 2; + unsigned int WAIT_3D_IDLECLEAN : 1; + unsigned int WAIT_2D_IDLECLEAN : 1; + unsigned int WAIT_3D_IDLE : 1; + unsigned int WAIT_2D_IDLE : 1; + unsigned int : 3; + unsigned int WAIT_CMDFIFO : 1; + unsigned int : 3; + unsigned int WAIT_DSPLY_ID2 : 1; + unsigned int WAIT_DSPLY_ID1 : 1; + unsigned int WAIT_DSPLY_ID0 : 1; + unsigned int WAIT_VSYNC : 1; + unsigned int WAIT_FE_VSYNC : 1; + unsigned int WAIT_RE_VSYNC : 1; + unsigned int : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_ISYNC_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int : 4; + unsigned int ISYNC_WAIT_IDLEGUI : 1; + unsigned int ISYNC_CPSCRATCH_IDLEGUI : 1; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int ISYNC_CPSCRATCH_IDLEGUI : 1; + unsigned int ISYNC_WAIT_IDLEGUI : 1; + unsigned int : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int CMDFIFO_AVAIL : 5; + unsigned int TC_BUSY : 1; + unsigned int : 2; + unsigned int HIRQ_PENDING : 1; + unsigned int CPRQ_PENDING : 1; + unsigned int CFRQ_PENDING : 1; + unsigned int PFRQ_PENDING : 1; + unsigned int VGT_BUSY_NO_DMA : 1; + unsigned int : 1; + unsigned int RBBM_WU_BUSY : 1; + unsigned int : 1; + unsigned int CP_NRT_BUSY : 1; + unsigned int : 1; + unsigned int MH_BUSY : 1; + unsigned int MH_COHERENCY_BUSY : 1; + unsigned int : 1; + unsigned int SX_BUSY : 1; + unsigned int TPC_BUSY : 1; + unsigned int : 1; + unsigned int SC_CNTX_BUSY : 1; + unsigned int PA_BUSY : 1; + unsigned int VGT_BUSY : 1; + unsigned int SQ_CNTX17_BUSY : 1; + unsigned int SQ_CNTX0_BUSY : 1; + unsigned int : 1; + unsigned int RB_CNTX_BUSY : 1; + unsigned int GUI_ACTIVE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int GUI_ACTIVE : 1; + unsigned int RB_CNTX_BUSY : 1; + unsigned int : 1; + unsigned int SQ_CNTX0_BUSY : 1; + unsigned int SQ_CNTX17_BUSY : 1; + unsigned int VGT_BUSY : 1; + unsigned int PA_BUSY : 1; + unsigned int SC_CNTX_BUSY : 1; + unsigned int : 1; + unsigned int TPC_BUSY : 1; + unsigned int SX_BUSY : 1; + unsigned int : 1; + unsigned int MH_COHERENCY_BUSY : 1; + unsigned int MH_BUSY : 1; + unsigned int : 1; + unsigned int CP_NRT_BUSY : 1; + unsigned int : 1; + unsigned int RBBM_WU_BUSY : 1; + unsigned int : 1; + unsigned int VGT_BUSY_NO_DMA : 1; + unsigned int PFRQ_PENDING : 1; + unsigned int CFRQ_PENDING : 1; + unsigned int CPRQ_PENDING : 1; + unsigned int HIRQ_PENDING : 1; + unsigned int : 2; + unsigned int TC_BUSY : 1; + unsigned int CMDFIFO_AVAIL : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_DSPLY { + struct { +#if defined(qLittleEndian) + unsigned int SEL_DMI_ACTIVE_BUFID0 : 1; + unsigned int SEL_DMI_ACTIVE_BUFID1 : 1; + unsigned int SEL_DMI_ACTIVE_BUFID2 : 1; + unsigned int SEL_DMI_VSYNC_VALID : 1; + unsigned int DMI_CH1_USE_BUFID0 : 1; + unsigned int DMI_CH1_USE_BUFID1 : 1; + unsigned int DMI_CH1_USE_BUFID2 : 1; + unsigned int DMI_CH1_SW_CNTL : 1; + unsigned int DMI_CH1_NUM_BUFS : 2; + unsigned int DMI_CH2_USE_BUFID0 : 1; + unsigned int DMI_CH2_USE_BUFID1 : 1; + unsigned int DMI_CH2_USE_BUFID2 : 1; + unsigned int DMI_CH2_SW_CNTL : 1; + unsigned int DMI_CH2_NUM_BUFS : 2; + unsigned int DMI_CHANNEL_SELECT : 2; + unsigned int : 2; + unsigned int DMI_CH3_USE_BUFID0 : 1; + unsigned int DMI_CH3_USE_BUFID1 : 1; + unsigned int DMI_CH3_USE_BUFID2 : 1; + unsigned int DMI_CH3_SW_CNTL : 1; + unsigned int DMI_CH3_NUM_BUFS : 2; + unsigned int DMI_CH4_USE_BUFID0 : 1; + unsigned int DMI_CH4_USE_BUFID1 : 1; + unsigned int DMI_CH4_USE_BUFID2 : 1; + unsigned int DMI_CH4_SW_CNTL : 1; + unsigned int DMI_CH4_NUM_BUFS : 2; +#else /* !defined(qLittleEndian) */ + unsigned int DMI_CH4_NUM_BUFS : 2; + unsigned int DMI_CH4_SW_CNTL : 1; + unsigned int DMI_CH4_USE_BUFID2 : 1; + unsigned int DMI_CH4_USE_BUFID1 : 1; + unsigned int DMI_CH4_USE_BUFID0 : 1; + unsigned int DMI_CH3_NUM_BUFS : 2; + unsigned int DMI_CH3_SW_CNTL : 1; + unsigned int DMI_CH3_USE_BUFID2 : 1; + unsigned int DMI_CH3_USE_BUFID1 : 1; + unsigned int DMI_CH3_USE_BUFID0 : 1; + unsigned int : 2; + unsigned int DMI_CHANNEL_SELECT : 2; + unsigned int DMI_CH2_NUM_BUFS : 2; + unsigned int DMI_CH2_SW_CNTL : 1; + unsigned int DMI_CH2_USE_BUFID2 : 1; + unsigned int DMI_CH2_USE_BUFID1 : 1; + unsigned int DMI_CH2_USE_BUFID0 : 1; + unsigned int DMI_CH1_NUM_BUFS : 2; + unsigned int DMI_CH1_SW_CNTL : 1; + unsigned int DMI_CH1_USE_BUFID2 : 1; + unsigned int DMI_CH1_USE_BUFID1 : 1; + unsigned int DMI_CH1_USE_BUFID0 : 1; + unsigned int SEL_DMI_VSYNC_VALID : 1; + unsigned int SEL_DMI_ACTIVE_BUFID2 : 1; + unsigned int SEL_DMI_ACTIVE_BUFID1 : 1; + unsigned int SEL_DMI_ACTIVE_BUFID0 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_RENDER_LATEST { + struct { +#if defined(qLittleEndian) + unsigned int DMI_CH1_BUFFER_ID : 2; + unsigned int : 6; + unsigned int DMI_CH2_BUFFER_ID : 2; + unsigned int : 6; + unsigned int DMI_CH3_BUFFER_ID : 2; + unsigned int : 6; + unsigned int DMI_CH4_BUFFER_ID : 2; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int DMI_CH4_BUFFER_ID : 2; + unsigned int : 6; + unsigned int DMI_CH3_BUFFER_ID : 2; + unsigned int : 6; + unsigned int DMI_CH2_BUFFER_ID : 2; + unsigned int : 6; + unsigned int DMI_CH1_BUFFER_ID : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_RTL_RELEASE { + struct { +#if defined(qLittleEndian) + unsigned int CHANGELIST : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CHANGELIST : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PATCH_RELEASE { + struct { +#if defined(qLittleEndian) + unsigned int PATCH_REVISION : 16; + unsigned int PATCH_SELECTION : 8; + unsigned int CUSTOMER_ID : 8; +#else /* !defined(qLittleEndian) */ + unsigned int CUSTOMER_ID : 8; + unsigned int PATCH_SELECTION : 8; + unsigned int PATCH_REVISION : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_AUXILIARY_CONFIG { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERIPHID0 { + struct { +#if defined(qLittleEndian) + unsigned int PARTNUMBER0 : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PARTNUMBER0 : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERIPHID1 { + struct { +#if defined(qLittleEndian) + unsigned int PARTNUMBER1 : 4; + unsigned int DESIGNER0 : 4; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int DESIGNER0 : 4; + unsigned int PARTNUMBER1 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERIPHID2 { + struct { +#if defined(qLittleEndian) + unsigned int DESIGNER1 : 4; + unsigned int REVISION : 4; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int REVISION : 4; + unsigned int DESIGNER1 : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERIPHID3 { + struct { +#if defined(qLittleEndian) + unsigned int RBBM_HOST_INTERFACE : 2; + unsigned int GARB_SLAVE_INTERFACE : 2; + unsigned int MH_INTERFACE : 2; + unsigned int : 1; + unsigned int CONTINUATION : 1; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int CONTINUATION : 1; + unsigned int : 1; + unsigned int MH_INTERFACE : 2; + unsigned int GARB_SLAVE_INTERFACE : 2; + unsigned int RBBM_HOST_INTERFACE : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int READ_TIMEOUT : 8; + unsigned int REGCLK_DEASSERT_TIME : 9; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int REGCLK_DEASSERT_TIME : 9; + unsigned int READ_TIMEOUT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_SKEW_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int SKEW_TOP_THRESHOLD : 5; + unsigned int SKEW_COUNT : 5; + unsigned int : 22; +#else /* !defined(qLittleEndian) */ + unsigned int : 22; + unsigned int SKEW_COUNT : 5; + unsigned int SKEW_TOP_THRESHOLD : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_SOFT_RESET { + struct { +#if defined(qLittleEndian) + unsigned int SOFT_RESET_CP : 1; + unsigned int : 1; + unsigned int SOFT_RESET_PA : 1; + unsigned int SOFT_RESET_MH : 1; + unsigned int SOFT_RESET_BC : 1; + unsigned int SOFT_RESET_SQ : 1; + unsigned int SOFT_RESET_SX : 1; + unsigned int : 5; + unsigned int SOFT_RESET_CIB : 1; + unsigned int : 2; + unsigned int SOFT_RESET_SC : 1; + unsigned int SOFT_RESET_VGT : 1; + unsigned int : 15; +#else /* !defined(qLittleEndian) */ + unsigned int : 15; + unsigned int SOFT_RESET_VGT : 1; + unsigned int SOFT_RESET_SC : 1; + unsigned int : 2; + unsigned int SOFT_RESET_CIB : 1; + unsigned int : 5; + unsigned int SOFT_RESET_SX : 1; + unsigned int SOFT_RESET_SQ : 1; + unsigned int SOFT_RESET_BC : 1; + unsigned int SOFT_RESET_MH : 1; + unsigned int SOFT_RESET_PA : 1; + unsigned int : 1; + unsigned int SOFT_RESET_CP : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PM_OVERRIDE1 { + struct { +#if defined(qLittleEndian) + unsigned int RBBM_AHBCLK_PM_OVERRIDE : 1; + unsigned int SC_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SC_SCLK_PM_OVERRIDE : 1; + unsigned int SP_TOP_SCLK_PM_OVERRIDE : 1; + unsigned int SP_V0_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_REG_FIFOS_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_CONST_MEM_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_SQ_SCLK_PM_OVERRIDE : 1; + unsigned int SX_SCLK_PM_OVERRIDE : 1; + unsigned int SX_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCO_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCM_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCD_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TPC_TPC_SCLK_PM_OVERRIDE : 1; + unsigned int TPC_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCA_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCB_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCB_READ_SCLK_PM_OVERRIDE : 1; + unsigned int TP_TP_SCLK_PM_OVERRIDE : 1; + unsigned int TP_REG_SCLK_PM_OVERRIDE : 1; + unsigned int CP_G_SCLK_PM_OVERRIDE : 1; + unsigned int CP_REG_SCLK_PM_OVERRIDE : 1; + unsigned int CP_G_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SPI_SCLK_PM_OVERRIDE : 1; + unsigned int RB_REG_SCLK_PM_OVERRIDE : 1; + unsigned int RB_SCLK_PM_OVERRIDE : 1; + unsigned int MH_MH_SCLK_PM_OVERRIDE : 1; + unsigned int MH_REG_SCLK_PM_OVERRIDE : 1; + unsigned int MH_MMU_SCLK_PM_OVERRIDE : 1; + unsigned int MH_TCROQ_SCLK_PM_OVERRIDE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int MH_TCROQ_SCLK_PM_OVERRIDE : 1; + unsigned int MH_MMU_SCLK_PM_OVERRIDE : 1; + unsigned int MH_REG_SCLK_PM_OVERRIDE : 1; + unsigned int MH_MH_SCLK_PM_OVERRIDE : 1; + unsigned int RB_SCLK_PM_OVERRIDE : 1; + unsigned int RB_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SPI_SCLK_PM_OVERRIDE : 1; + unsigned int CP_G_REG_SCLK_PM_OVERRIDE : 1; + unsigned int CP_REG_SCLK_PM_OVERRIDE : 1; + unsigned int CP_G_SCLK_PM_OVERRIDE : 1; + unsigned int TP_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TP_TP_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCB_READ_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCB_SCLK_PM_OVERRIDE : 1; + unsigned int TCF_TCA_SCLK_PM_OVERRIDE : 1; + unsigned int TPC_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TPC_TPC_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_REG_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCD_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCM_SCLK_PM_OVERRIDE : 1; + unsigned int TCM_TCO_SCLK_PM_OVERRIDE : 1; + unsigned int SX_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SX_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_SQ_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_CONST_MEM_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_REG_FIFOS_SCLK_PM_OVERRIDE : 1; + unsigned int SQ_REG_SCLK_PM_OVERRIDE : 1; + unsigned int SP_V0_SCLK_PM_OVERRIDE : 1; + unsigned int SP_TOP_SCLK_PM_OVERRIDE : 1; + unsigned int SC_SCLK_PM_OVERRIDE : 1; + unsigned int SC_REG_SCLK_PM_OVERRIDE : 1; + unsigned int RBBM_AHBCLK_PM_OVERRIDE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PM_OVERRIDE2 { + struct { +#if defined(qLittleEndian) + unsigned int PA_REG_SCLK_PM_OVERRIDE : 1; + unsigned int PA_PA_SCLK_PM_OVERRIDE : 1; + unsigned int PA_AG_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_REG_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_FIFOS_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_VGT_SCLK_PM_OVERRIDE : 1; + unsigned int DEBUG_PERF_SCLK_PM_OVERRIDE : 1; + unsigned int PERM_SCLK_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM0_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM1_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM2_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM3_PM_OVERRIDE : 1; + unsigned int : 20; +#else /* !defined(qLittleEndian) */ + unsigned int : 20; + unsigned int GC_GA_GMEM3_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM2_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM1_PM_OVERRIDE : 1; + unsigned int GC_GA_GMEM0_PM_OVERRIDE : 1; + unsigned int PERM_SCLK_PM_OVERRIDE : 1; + unsigned int DEBUG_PERF_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_VGT_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_FIFOS_SCLK_PM_OVERRIDE : 1; + unsigned int VGT_REG_SCLK_PM_OVERRIDE : 1; + unsigned int PA_AG_SCLK_PM_OVERRIDE : 1; + unsigned int PA_PA_SCLK_PM_OVERRIDE : 1; + unsigned int PA_REG_SCLK_PM_OVERRIDE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union GC_SYS_IDLE { + struct { +#if defined(qLittleEndian) + unsigned int GC_SYS_IDLE_DELAY : 16; + unsigned int GC_SYS_WAIT_DMI_MASK : 6; + unsigned int : 2; + unsigned int GC_SYS_URGENT_RAMP : 1; + unsigned int GC_SYS_WAIT_DMI : 1; + unsigned int : 3; + unsigned int GC_SYS_URGENT_RAMP_OVERRIDE : 1; + unsigned int GC_SYS_WAIT_DMI_OVERRIDE : 1; + unsigned int GC_SYS_IDLE_OVERRIDE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int GC_SYS_IDLE_OVERRIDE : 1; + unsigned int GC_SYS_WAIT_DMI_OVERRIDE : 1; + unsigned int GC_SYS_URGENT_RAMP_OVERRIDE : 1; + unsigned int : 3; + unsigned int GC_SYS_WAIT_DMI : 1; + unsigned int GC_SYS_URGENT_RAMP : 1; + unsigned int : 2; + unsigned int GC_SYS_WAIT_DMI_MASK : 6; + unsigned int GC_SYS_IDLE_DELAY : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union NQWAIT_UNTIL { + struct { +#if defined(qLittleEndian) + unsigned int WAIT_GUI_IDLE : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int WAIT_GUI_IDLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_DEBUG_OUT { + struct { +#if defined(qLittleEndian) + unsigned int DEBUG_BUS_OUT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DEBUG_BUS_OUT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_DEBUG_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int SUB_BLOCK_ADDR : 6; + unsigned int : 2; + unsigned int SUB_BLOCK_SEL : 4; + unsigned int SW_ENABLE : 1; + unsigned int : 3; + unsigned int GPIO_SUB_BLOCK_ADDR : 6; + unsigned int : 2; + unsigned int GPIO_SUB_BLOCK_SEL : 4; + unsigned int GPIO_BYTE_LANE_ENB : 4; +#else /* !defined(qLittleEndian) */ + unsigned int GPIO_BYTE_LANE_ENB : 4; + unsigned int GPIO_SUB_BLOCK_SEL : 4; + unsigned int : 2; + unsigned int GPIO_SUB_BLOCK_ADDR : 6; + unsigned int : 3; + unsigned int SW_ENABLE : 1; + unsigned int SUB_BLOCK_SEL : 4; + unsigned int : 2; + unsigned int SUB_BLOCK_ADDR : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int : 1; + unsigned int IGNORE_RTR : 1; + unsigned int IGNORE_CP_SCHED_WU : 1; + unsigned int IGNORE_CP_SCHED_ISYNC : 1; + unsigned int IGNORE_CP_SCHED_NQ_HI : 1; + unsigned int : 3; + unsigned int HYSTERESIS_NRT_GUI_ACTIVE : 4; + unsigned int : 4; + unsigned int IGNORE_RTR_FOR_HI : 1; + unsigned int IGNORE_CP_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_VGT_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_SQ_RBBM_NRTRTR_FOR_HI : 1; + unsigned int CP_RBBM_NRTRTR : 1; + unsigned int VGT_RBBM_NRTRTR : 1; + unsigned int SQ_RBBM_NRTRTR : 1; + unsigned int CLIENTS_FOR_NRT_RTR_FOR_HI : 1; + unsigned int CLIENTS_FOR_NRT_RTR : 1; + unsigned int : 6; + unsigned int IGNORE_SX_RBBM_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int IGNORE_SX_RBBM_BUSY : 1; + unsigned int : 6; + unsigned int CLIENTS_FOR_NRT_RTR : 1; + unsigned int CLIENTS_FOR_NRT_RTR_FOR_HI : 1; + unsigned int SQ_RBBM_NRTRTR : 1; + unsigned int VGT_RBBM_NRTRTR : 1; + unsigned int CP_RBBM_NRTRTR : 1; + unsigned int IGNORE_SQ_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_VGT_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_CP_RBBM_NRTRTR_FOR_HI : 1; + unsigned int IGNORE_RTR_FOR_HI : 1; + unsigned int : 4; + unsigned int HYSTERESIS_NRT_GUI_ACTIVE : 4; + unsigned int : 3; + unsigned int IGNORE_CP_SCHED_NQ_HI : 1; + unsigned int IGNORE_CP_SCHED_ISYNC : 1; + unsigned int IGNORE_CP_SCHED_WU : 1; + unsigned int IGNORE_RTR : 1; + unsigned int : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_READ_ERROR { + struct { +#if defined(qLittleEndian) + unsigned int : 2; + unsigned int READ_ADDRESS : 15; + unsigned int : 13; + unsigned int READ_REQUESTER : 1; + unsigned int READ_ERROR : 1; +#else /* !defined(qLittleEndian) */ + unsigned int READ_ERROR : 1; + unsigned int READ_REQUESTER : 1; + unsigned int : 13; + unsigned int READ_ADDRESS : 15; + unsigned int : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_WAIT_IDLE_CLOCKS { + struct { +#if defined(qLittleEndian) + unsigned int WAIT_IDLE_CLOCKS_NRT : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int WAIT_IDLE_CLOCKS_NRT : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_INT_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int RDERR_INT_MASK : 1; + unsigned int DISPLAY_UPDATE_INT_MASK : 1; + unsigned int : 17; + unsigned int GUI_IDLE_INT_MASK : 1; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int GUI_IDLE_INT_MASK : 1; + unsigned int : 17; + unsigned int DISPLAY_UPDATE_INT_MASK : 1; + unsigned int RDERR_INT_MASK : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_INT_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int RDERR_INT_STAT : 1; + unsigned int DISPLAY_UPDATE_INT_STAT : 1; + unsigned int : 17; + unsigned int GUI_IDLE_INT_STAT : 1; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int GUI_IDLE_INT_STAT : 1; + unsigned int : 17; + unsigned int DISPLAY_UPDATE_INT_STAT : 1; + unsigned int RDERR_INT_STAT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_INT_ACK { + struct { +#if defined(qLittleEndian) + unsigned int RDERR_INT_ACK : 1; + unsigned int DISPLAY_UPDATE_INT_ACK : 1; + unsigned int : 17; + unsigned int GUI_IDLE_INT_ACK : 1; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int GUI_IDLE_INT_ACK : 1; + unsigned int : 17; + unsigned int DISPLAY_UPDATE_INT_ACK : 1; + unsigned int RDERR_INT_ACK : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union MASTER_INT_SIGNAL { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int MH_INT_STAT : 1; + unsigned int : 20; + unsigned int SQ_INT_STAT : 1; + unsigned int : 3; + unsigned int CP_INT_STAT : 1; + unsigned int RBBM_INT_STAT : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RBBM_INT_STAT : 1; + unsigned int CP_INT_STAT : 1; + unsigned int : 3; + unsigned int SQ_INT_STAT : 1; + unsigned int : 20; + unsigned int MH_INT_STAT : 1; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERFCOUNTER1_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT1_SEL : 6; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int PERF_COUNT1_SEL : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERFCOUNTER1_LO { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT1_LO : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT1_LO : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RBBM_PERFCOUNTER1_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT1_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT1_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int RB_BASE : 27; +#else /* !defined(qLittleEndian) */ + unsigned int RB_BASE : 27; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int RB_BUFSZ : 6; + unsigned int : 2; + unsigned int RB_BLKSZ : 6; + unsigned int : 2; + unsigned int BUF_SWAP : 2; + unsigned int : 2; + unsigned int RB_POLL_EN : 1; + unsigned int : 6; + unsigned int RB_NO_UPDATE : 1; + unsigned int : 3; + unsigned int RB_RPTR_WR_ENA : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RB_RPTR_WR_ENA : 1; + unsigned int : 3; + unsigned int RB_NO_UPDATE : 1; + unsigned int : 6; + unsigned int RB_POLL_EN : 1; + unsigned int : 2; + unsigned int BUF_SWAP : 2; + unsigned int : 2; + unsigned int RB_BLKSZ : 6; + unsigned int : 2; + unsigned int RB_BUFSZ : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_RPTR_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int RB_RPTR_SWAP : 2; + unsigned int RB_RPTR_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int RB_RPTR_ADDR : 30; + unsigned int RB_RPTR_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_RPTR { + struct { +#if defined(qLittleEndian) + unsigned int RB_RPTR : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int RB_RPTR : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_RPTR_WR { + struct { +#if defined(qLittleEndian) + unsigned int RB_RPTR_WR : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int RB_RPTR_WR : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_WPTR { + struct { +#if defined(qLittleEndian) + unsigned int RB_WPTR : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int RB_WPTR : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_WPTR_DELAY { + struct { +#if defined(qLittleEndian) + unsigned int PRE_WRITE_TIMER : 28; + unsigned int PRE_WRITE_LIMIT : 4; +#else /* !defined(qLittleEndian) */ + unsigned int PRE_WRITE_LIMIT : 4; + unsigned int PRE_WRITE_TIMER : 28; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_RB_WPTR_BASE { + struct { +#if defined(qLittleEndian) + unsigned int RB_WPTR_SWAP : 2; + unsigned int RB_WPTR_BASE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int RB_WPTR_BASE : 30; + unsigned int RB_WPTR_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_IB1_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 2; + unsigned int IB1_BASE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int IB1_BASE : 30; + unsigned int : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_IB1_BUFSZ { + struct { +#if defined(qLittleEndian) + unsigned int IB1_BUFSZ : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int IB1_BUFSZ : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_IB2_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 2; + unsigned int IB2_BASE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int IB2_BASE : 30; + unsigned int : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_IB2_BUFSZ { + struct { +#if defined(qLittleEndian) + unsigned int IB2_BUFSZ : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int IB2_BUFSZ : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ST_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 2; + unsigned int ST_BASE : 30; +#else /* !defined(qLittleEndian) */ + unsigned int ST_BASE : 30; + unsigned int : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ST_BUFSZ { + struct { +#if defined(qLittleEndian) + unsigned int ST_BUFSZ : 20; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int ST_BUFSZ : 20; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_QUEUE_THRESHOLDS { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_IB1_START : 4; + unsigned int : 4; + unsigned int CSQ_IB2_START : 4; + unsigned int : 4; + unsigned int CSQ_ST_START : 4; + unsigned int : 12; +#else /* !defined(qLittleEndian) */ + unsigned int : 12; + unsigned int CSQ_ST_START : 4; + unsigned int : 4; + unsigned int CSQ_IB2_START : 4; + unsigned int : 4; + unsigned int CSQ_IB1_START : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_MEQ_THRESHOLDS { + struct { +#if defined(qLittleEndian) + unsigned int : 16; + unsigned int MEQ_END : 5; + unsigned int : 3; + unsigned int ROQ_END : 5; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int ROQ_END : 5; + unsigned int : 3; + unsigned int MEQ_END : 5; + unsigned int : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CSQ_AVAIL { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_CNT_RING : 7; + unsigned int : 1; + unsigned int CSQ_CNT_IB1 : 7; + unsigned int : 1; + unsigned int CSQ_CNT_IB2 : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int CSQ_CNT_IB2 : 7; + unsigned int : 1; + unsigned int CSQ_CNT_IB1 : 7; + unsigned int : 1; + unsigned int CSQ_CNT_RING : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STQ_AVAIL { + struct { +#if defined(qLittleEndian) + unsigned int STQ_CNT_ST : 7; + unsigned int : 25; +#else /* !defined(qLittleEndian) */ + unsigned int : 25; + unsigned int STQ_CNT_ST : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_MEQ_AVAIL { + struct { +#if defined(qLittleEndian) + unsigned int MEQ_CNT : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int MEQ_CNT : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CSQ_RB_STAT { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_RPTR_PRIMARY : 7; + unsigned int : 9; + unsigned int CSQ_WPTR_PRIMARY : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int CSQ_WPTR_PRIMARY : 7; + unsigned int : 9; + unsigned int CSQ_RPTR_PRIMARY : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CSQ_IB1_STAT { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_RPTR_INDIRECT1 : 7; + unsigned int : 9; + unsigned int CSQ_WPTR_INDIRECT1 : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int CSQ_WPTR_INDIRECT1 : 7; + unsigned int : 9; + unsigned int CSQ_RPTR_INDIRECT1 : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CSQ_IB2_STAT { + struct { +#if defined(qLittleEndian) + unsigned int CSQ_RPTR_INDIRECT2 : 7; + unsigned int : 9; + unsigned int CSQ_WPTR_INDIRECT2 : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int CSQ_WPTR_INDIRECT2 : 7; + unsigned int : 9; + unsigned int CSQ_RPTR_INDIRECT2 : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NON_PREFETCH_CNTRS { + struct { +#if defined(qLittleEndian) + unsigned int IB1_COUNTER : 3; + unsigned int : 5; + unsigned int IB2_COUNTER : 3; + unsigned int : 21; +#else /* !defined(qLittleEndian) */ + unsigned int : 21; + unsigned int IB2_COUNTER : 3; + unsigned int : 5; + unsigned int IB1_COUNTER : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STQ_ST_STAT { + struct { +#if defined(qLittleEndian) + unsigned int STQ_RPTR_ST : 7; + unsigned int : 9; + unsigned int STQ_WPTR_ST : 7; + unsigned int : 9; +#else /* !defined(qLittleEndian) */ + unsigned int : 9; + unsigned int STQ_WPTR_ST : 7; + unsigned int : 9; + unsigned int STQ_RPTR_ST : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_MEQ_STAT { + struct { +#if defined(qLittleEndian) + unsigned int MEQ_RPTR : 10; + unsigned int : 6; + unsigned int MEQ_WPTR : 10; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int MEQ_WPTR : 10; + unsigned int : 6; + unsigned int MEQ_RPTR : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_MIU_TAG_STAT { + struct { +#if defined(qLittleEndian) + unsigned int TAG_0_STAT : 1; + unsigned int TAG_1_STAT : 1; + unsigned int TAG_2_STAT : 1; + unsigned int TAG_3_STAT : 1; + unsigned int TAG_4_STAT : 1; + unsigned int TAG_5_STAT : 1; + unsigned int TAG_6_STAT : 1; + unsigned int TAG_7_STAT : 1; + unsigned int TAG_8_STAT : 1; + unsigned int TAG_9_STAT : 1; + unsigned int TAG_10_STAT : 1; + unsigned int TAG_11_STAT : 1; + unsigned int TAG_12_STAT : 1; + unsigned int TAG_13_STAT : 1; + unsigned int TAG_14_STAT : 1; + unsigned int TAG_15_STAT : 1; + unsigned int TAG_16_STAT : 1; + unsigned int TAG_17_STAT : 1; + unsigned int : 13; + unsigned int INVALID_RETURN_TAG : 1; +#else /* !defined(qLittleEndian) */ + unsigned int INVALID_RETURN_TAG : 1; + unsigned int : 13; + unsigned int TAG_17_STAT : 1; + unsigned int TAG_16_STAT : 1; + unsigned int TAG_15_STAT : 1; + unsigned int TAG_14_STAT : 1; + unsigned int TAG_13_STAT : 1; + unsigned int TAG_12_STAT : 1; + unsigned int TAG_11_STAT : 1; + unsigned int TAG_10_STAT : 1; + unsigned int TAG_9_STAT : 1; + unsigned int TAG_8_STAT : 1; + unsigned int TAG_7_STAT : 1; + unsigned int TAG_6_STAT : 1; + unsigned int TAG_5_STAT : 1; + unsigned int TAG_4_STAT : 1; + unsigned int TAG_3_STAT : 1; + unsigned int TAG_2_STAT : 1; + unsigned int TAG_1_STAT : 1; + unsigned int TAG_0_STAT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CMD_INDEX { + struct { +#if defined(qLittleEndian) + unsigned int CMD_INDEX : 7; + unsigned int : 9; + unsigned int CMD_QUEUE_SEL : 2; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int CMD_QUEUE_SEL : 2; + unsigned int : 9; + unsigned int CMD_INDEX : 7; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_CMD_DATA { + struct { +#if defined(qLittleEndian) + unsigned int CMD_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CMD_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int ME_STATMUX : 16; + unsigned int : 9; + unsigned int VTX_DEALLOC_FIFO_EMPTY : 1; + unsigned int PIX_DEALLOC_FIFO_EMPTY : 1; + unsigned int : 1; + unsigned int ME_HALT : 1; + unsigned int ME_BUSY : 1; + unsigned int : 1; + unsigned int PROG_CNT_SIZE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int PROG_CNT_SIZE : 1; + unsigned int : 1; + unsigned int ME_BUSY : 1; + unsigned int ME_HALT : 1; + unsigned int : 1; + unsigned int PIX_DEALLOC_FIFO_EMPTY : 1; + unsigned int VTX_DEALLOC_FIFO_EMPTY : 1; + unsigned int : 9; + unsigned int ME_STATMUX : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int ME_DEBUG_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ME_DEBUG_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_RAM_WADDR { + struct { +#if defined(qLittleEndian) + unsigned int ME_RAM_WADDR : 10; + unsigned int : 22; +#else /* !defined(qLittleEndian) */ + unsigned int : 22; + unsigned int ME_RAM_WADDR : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_RAM_RADDR { + struct { +#if defined(qLittleEndian) + unsigned int ME_RAM_RADDR : 10; + unsigned int : 22; +#else /* !defined(qLittleEndian) */ + unsigned int : 22; + unsigned int ME_RAM_RADDR : 10; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_RAM_DATA { + struct { +#if defined(qLittleEndian) + unsigned int ME_RAM_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ME_RAM_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_RDADDR { + struct { +#if defined(qLittleEndian) + unsigned int ME_RDADDR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ME_RDADDR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_DEBUG { + struct { +#if defined(qLittleEndian) + unsigned int CP_DEBUG_UNUSED_22_to_0 : 23; + unsigned int PREDICATE_DISABLE : 1; + unsigned int PROG_END_PTR_ENABLE : 1; + unsigned int MIU_128BIT_WRITE_ENABLE : 1; + unsigned int PREFETCH_PASS_NOPS : 1; + unsigned int DYNAMIC_CLK_DISABLE : 1; + unsigned int PREFETCH_MATCH_DISABLE : 1; + unsigned int : 1; + unsigned int SIMPLE_ME_FLOW_CONTROL : 1; + unsigned int MIU_WRITE_PACK_DISABLE : 1; +#else /* !defined(qLittleEndian) */ + unsigned int MIU_WRITE_PACK_DISABLE : 1; + unsigned int SIMPLE_ME_FLOW_CONTROL : 1; + unsigned int : 1; + unsigned int PREFETCH_MATCH_DISABLE : 1; + unsigned int DYNAMIC_CLK_DISABLE : 1; + unsigned int PREFETCH_PASS_NOPS : 1; + unsigned int MIU_128BIT_WRITE_ENABLE : 1; + unsigned int PROG_END_PTR_ENABLE : 1; + unsigned int PREDICATE_DISABLE : 1; + unsigned int CP_DEBUG_UNUSED_22_to_0 : 23; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG0 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG0 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG0 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG1 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG1 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG1 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG2 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG2 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG2 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG3 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG3 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG3 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG4 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG4 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG4 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG5 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG5 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG5 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG6 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG6 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG6 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_REG7 { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_REG7 : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_REG7 : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_UMSK { + struct { +#if defined(qLittleEndian) + unsigned int SCRATCH_UMSK : 8; + unsigned int : 8; + unsigned int SCRATCH_SWAP : 2; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int SCRATCH_SWAP : 2; + unsigned int : 8; + unsigned int SCRATCH_UMSK : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union SCRATCH_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int : 5; + unsigned int SCRATCH_ADDR : 27; +#else /* !defined(qLittleEndian) */ + unsigned int SCRATCH_ADDR : 27; + unsigned int : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_SRC { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_SWM : 1; + unsigned int VS_DONE_CNTR : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int VS_DONE_CNTR : 1; + unsigned int VS_DONE_SWM : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_SWAP : 2; + unsigned int VS_DONE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int VS_DONE_ADDR : 30; + unsigned int VS_DONE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_DATA { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_DONE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_ADDR_SWM { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_SWAP_SWM : 2; + unsigned int VS_DONE_ADDR_SWM : 30; +#else /* !defined(qLittleEndian) */ + unsigned int VS_DONE_ADDR_SWM : 30; + unsigned int VS_DONE_SWAP_SWM : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_EVENT_DATA_SWM { + struct { +#if defined(qLittleEndian) + unsigned int VS_DONE_DATA_SWM : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_DONE_DATA_SWM : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_SRC { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_SWM : 1; + unsigned int PS_DONE_CNTR : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int PS_DONE_CNTR : 1; + unsigned int PS_DONE_SWM : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_SWAP : 2; + unsigned int PS_DONE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int PS_DONE_ADDR : 30; + unsigned int PS_DONE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_DATA { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PS_DONE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_ADDR_SWM { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_SWAP_SWM : 2; + unsigned int PS_DONE_ADDR_SWM : 30; +#else /* !defined(qLittleEndian) */ + unsigned int PS_DONE_ADDR_SWM : 30; + unsigned int PS_DONE_SWAP_SWM : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_PS_EVENT_DATA_SWM { + struct { +#if defined(qLittleEndian) + unsigned int PS_DONE_DATA_SWM : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PS_DONE_DATA_SWM : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_CF_EVENT_SRC { + struct { +#if defined(qLittleEndian) + unsigned int CF_DONE_SRC : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int CF_DONE_SRC : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_CF_EVENT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int CF_DONE_SWAP : 2; + unsigned int CF_DONE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int CF_DONE_ADDR : 30; + unsigned int CF_DONE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_CF_EVENT_DATA { + struct { +#if defined(qLittleEndian) + unsigned int CF_DONE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CF_DONE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_NRT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int NRT_WRITE_SWAP : 2; + unsigned int NRT_WRITE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int NRT_WRITE_ADDR : 30; + unsigned int NRT_WRITE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_NRT_DATA { + struct { +#if defined(qLittleEndian) + unsigned int NRT_WRITE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int NRT_WRITE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_FETCH_DONE_SRC { + struct { +#if defined(qLittleEndian) + unsigned int VS_FETCH_DONE_CNTR : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int VS_FETCH_DONE_CNTR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_FETCH_DONE_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int VS_FETCH_DONE_SWAP : 2; + unsigned int VS_FETCH_DONE_ADDR : 30; +#else /* !defined(qLittleEndian) */ + unsigned int VS_FETCH_DONE_ADDR : 30; + unsigned int VS_FETCH_DONE_SWAP : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_ME_VS_FETCH_DONE_DATA { + struct { +#if defined(qLittleEndian) + unsigned int VS_FETCH_DONE_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int VS_FETCH_DONE_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_INT_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int : 19; + unsigned int SW_INT_MASK : 1; + unsigned int : 3; + unsigned int T0_PACKET_IN_IB_MASK : 1; + unsigned int OPCODE_ERROR_MASK : 1; + unsigned int PROTECTED_MODE_ERROR_MASK : 1; + unsigned int RESERVED_BIT_ERROR_MASK : 1; + unsigned int IB_ERROR_MASK : 1; + unsigned int : 1; + unsigned int IB2_INT_MASK : 1; + unsigned int IB1_INT_MASK : 1; + unsigned int RB_INT_MASK : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RB_INT_MASK : 1; + unsigned int IB1_INT_MASK : 1; + unsigned int IB2_INT_MASK : 1; + unsigned int : 1; + unsigned int IB_ERROR_MASK : 1; + unsigned int RESERVED_BIT_ERROR_MASK : 1; + unsigned int PROTECTED_MODE_ERROR_MASK : 1; + unsigned int OPCODE_ERROR_MASK : 1; + unsigned int T0_PACKET_IN_IB_MASK : 1; + unsigned int : 3; + unsigned int SW_INT_MASK : 1; + unsigned int : 19; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_INT_STATUS { + struct { +#if defined(qLittleEndian) + unsigned int : 19; + unsigned int SW_INT_STAT : 1; + unsigned int : 3; + unsigned int T0_PACKET_IN_IB_STAT : 1; + unsigned int OPCODE_ERROR_STAT : 1; + unsigned int PROTECTED_MODE_ERROR_STAT : 1; + unsigned int RESERVED_BIT_ERROR_STAT : 1; + unsigned int IB_ERROR_STAT : 1; + unsigned int : 1; + unsigned int IB2_INT_STAT : 1; + unsigned int IB1_INT_STAT : 1; + unsigned int RB_INT_STAT : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RB_INT_STAT : 1; + unsigned int IB1_INT_STAT : 1; + unsigned int IB2_INT_STAT : 1; + unsigned int : 1; + unsigned int IB_ERROR_STAT : 1; + unsigned int RESERVED_BIT_ERROR_STAT : 1; + unsigned int PROTECTED_MODE_ERROR_STAT : 1; + unsigned int OPCODE_ERROR_STAT : 1; + unsigned int T0_PACKET_IN_IB_STAT : 1; + unsigned int : 3; + unsigned int SW_INT_STAT : 1; + unsigned int : 19; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_INT_ACK { + struct { +#if defined(qLittleEndian) + unsigned int : 19; + unsigned int SW_INT_ACK : 1; + unsigned int : 3; + unsigned int T0_PACKET_IN_IB_ACK : 1; + unsigned int OPCODE_ERROR_ACK : 1; + unsigned int PROTECTED_MODE_ERROR_ACK : 1; + unsigned int RESERVED_BIT_ERROR_ACK : 1; + unsigned int IB_ERROR_ACK : 1; + unsigned int : 1; + unsigned int IB2_INT_ACK : 1; + unsigned int IB1_INT_ACK : 1; + unsigned int RB_INT_ACK : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RB_INT_ACK : 1; + unsigned int IB1_INT_ACK : 1; + unsigned int IB2_INT_ACK : 1; + unsigned int : 1; + unsigned int IB_ERROR_ACK : 1; + unsigned int RESERVED_BIT_ERROR_ACK : 1; + unsigned int PROTECTED_MODE_ERROR_ACK : 1; + unsigned int OPCODE_ERROR_ACK : 1; + unsigned int T0_PACKET_IN_IB_ACK : 1; + unsigned int : 3; + unsigned int SW_INT_ACK : 1; + unsigned int : 19; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PFP_UCODE_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int UCODE_ADDR : 9; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int UCODE_ADDR : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PFP_UCODE_DATA { + struct { +#if defined(qLittleEndian) + unsigned int UCODE_DATA : 24; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int UCODE_DATA : 24; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PERFMON_CNTL { + struct { +#if defined(qLittleEndian) + unsigned int PERFMON_STATE : 4; + unsigned int : 4; + unsigned int PERFMON_ENABLE_MODE : 2; + unsigned int : 22; +#else /* !defined(qLittleEndian) */ + unsigned int : 22; + unsigned int PERFMON_ENABLE_MODE : 2; + unsigned int : 4; + unsigned int PERFMON_STATE : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PERFCOUNTER_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNT_SEL : 6; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int PERFCOUNT_SEL : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PERFCOUNTER_LO { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNT_LO : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERFCOUNT_LO : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PERFCOUNTER_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERFCOUNT_HI : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERFCOUNT_HI : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_BIN_MASK_LO { + struct { +#if defined(qLittleEndian) + unsigned int BIN_MASK_LO : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_MASK_LO : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_BIN_MASK_HI { + struct { +#if defined(qLittleEndian) + unsigned int BIN_MASK_HI : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_MASK_HI : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_BIN_SELECT_LO { + struct { +#if defined(qLittleEndian) + unsigned int BIN_SELECT_LO : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_SELECT_LO : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_BIN_SELECT_HI { + struct { +#if defined(qLittleEndian) + unsigned int BIN_SELECT_HI : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIN_SELECT_HI : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NV_FLAGS_0 { + struct { +#if defined(qLittleEndian) + unsigned int DISCARD_0 : 1; + unsigned int END_RCVD_0 : 1; + unsigned int DISCARD_1 : 1; + unsigned int END_RCVD_1 : 1; + unsigned int DISCARD_2 : 1; + unsigned int END_RCVD_2 : 1; + unsigned int DISCARD_3 : 1; + unsigned int END_RCVD_3 : 1; + unsigned int DISCARD_4 : 1; + unsigned int END_RCVD_4 : 1; + unsigned int DISCARD_5 : 1; + unsigned int END_RCVD_5 : 1; + unsigned int DISCARD_6 : 1; + unsigned int END_RCVD_6 : 1; + unsigned int DISCARD_7 : 1; + unsigned int END_RCVD_7 : 1; + unsigned int DISCARD_8 : 1; + unsigned int END_RCVD_8 : 1; + unsigned int DISCARD_9 : 1; + unsigned int END_RCVD_9 : 1; + unsigned int DISCARD_10 : 1; + unsigned int END_RCVD_10 : 1; + unsigned int DISCARD_11 : 1; + unsigned int END_RCVD_11 : 1; + unsigned int DISCARD_12 : 1; + unsigned int END_RCVD_12 : 1; + unsigned int DISCARD_13 : 1; + unsigned int END_RCVD_13 : 1; + unsigned int DISCARD_14 : 1; + unsigned int END_RCVD_14 : 1; + unsigned int DISCARD_15 : 1; + unsigned int END_RCVD_15 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int END_RCVD_15 : 1; + unsigned int DISCARD_15 : 1; + unsigned int END_RCVD_14 : 1; + unsigned int DISCARD_14 : 1; + unsigned int END_RCVD_13 : 1; + unsigned int DISCARD_13 : 1; + unsigned int END_RCVD_12 : 1; + unsigned int DISCARD_12 : 1; + unsigned int END_RCVD_11 : 1; + unsigned int DISCARD_11 : 1; + unsigned int END_RCVD_10 : 1; + unsigned int DISCARD_10 : 1; + unsigned int END_RCVD_9 : 1; + unsigned int DISCARD_9 : 1; + unsigned int END_RCVD_8 : 1; + unsigned int DISCARD_8 : 1; + unsigned int END_RCVD_7 : 1; + unsigned int DISCARD_7 : 1; + unsigned int END_RCVD_6 : 1; + unsigned int DISCARD_6 : 1; + unsigned int END_RCVD_5 : 1; + unsigned int DISCARD_5 : 1; + unsigned int END_RCVD_4 : 1; + unsigned int DISCARD_4 : 1; + unsigned int END_RCVD_3 : 1; + unsigned int DISCARD_3 : 1; + unsigned int END_RCVD_2 : 1; + unsigned int DISCARD_2 : 1; + unsigned int END_RCVD_1 : 1; + unsigned int DISCARD_1 : 1; + unsigned int END_RCVD_0 : 1; + unsigned int DISCARD_0 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NV_FLAGS_1 { + struct { +#if defined(qLittleEndian) + unsigned int DISCARD_16 : 1; + unsigned int END_RCVD_16 : 1; + unsigned int DISCARD_17 : 1; + unsigned int END_RCVD_17 : 1; + unsigned int DISCARD_18 : 1; + unsigned int END_RCVD_18 : 1; + unsigned int DISCARD_19 : 1; + unsigned int END_RCVD_19 : 1; + unsigned int DISCARD_20 : 1; + unsigned int END_RCVD_20 : 1; + unsigned int DISCARD_21 : 1; + unsigned int END_RCVD_21 : 1; + unsigned int DISCARD_22 : 1; + unsigned int END_RCVD_22 : 1; + unsigned int DISCARD_23 : 1; + unsigned int END_RCVD_23 : 1; + unsigned int DISCARD_24 : 1; + unsigned int END_RCVD_24 : 1; + unsigned int DISCARD_25 : 1; + unsigned int END_RCVD_25 : 1; + unsigned int DISCARD_26 : 1; + unsigned int END_RCVD_26 : 1; + unsigned int DISCARD_27 : 1; + unsigned int END_RCVD_27 : 1; + unsigned int DISCARD_28 : 1; + unsigned int END_RCVD_28 : 1; + unsigned int DISCARD_29 : 1; + unsigned int END_RCVD_29 : 1; + unsigned int DISCARD_30 : 1; + unsigned int END_RCVD_30 : 1; + unsigned int DISCARD_31 : 1; + unsigned int END_RCVD_31 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int END_RCVD_31 : 1; + unsigned int DISCARD_31 : 1; + unsigned int END_RCVD_30 : 1; + unsigned int DISCARD_30 : 1; + unsigned int END_RCVD_29 : 1; + unsigned int DISCARD_29 : 1; + unsigned int END_RCVD_28 : 1; + unsigned int DISCARD_28 : 1; + unsigned int END_RCVD_27 : 1; + unsigned int DISCARD_27 : 1; + unsigned int END_RCVD_26 : 1; + unsigned int DISCARD_26 : 1; + unsigned int END_RCVD_25 : 1; + unsigned int DISCARD_25 : 1; + unsigned int END_RCVD_24 : 1; + unsigned int DISCARD_24 : 1; + unsigned int END_RCVD_23 : 1; + unsigned int DISCARD_23 : 1; + unsigned int END_RCVD_22 : 1; + unsigned int DISCARD_22 : 1; + unsigned int END_RCVD_21 : 1; + unsigned int DISCARD_21 : 1; + unsigned int END_RCVD_20 : 1; + unsigned int DISCARD_20 : 1; + unsigned int END_RCVD_19 : 1; + unsigned int DISCARD_19 : 1; + unsigned int END_RCVD_18 : 1; + unsigned int DISCARD_18 : 1; + unsigned int END_RCVD_17 : 1; + unsigned int DISCARD_17 : 1; + unsigned int END_RCVD_16 : 1; + unsigned int DISCARD_16 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NV_FLAGS_2 { + struct { +#if defined(qLittleEndian) + unsigned int DISCARD_32 : 1; + unsigned int END_RCVD_32 : 1; + unsigned int DISCARD_33 : 1; + unsigned int END_RCVD_33 : 1; + unsigned int DISCARD_34 : 1; + unsigned int END_RCVD_34 : 1; + unsigned int DISCARD_35 : 1; + unsigned int END_RCVD_35 : 1; + unsigned int DISCARD_36 : 1; + unsigned int END_RCVD_36 : 1; + unsigned int DISCARD_37 : 1; + unsigned int END_RCVD_37 : 1; + unsigned int DISCARD_38 : 1; + unsigned int END_RCVD_38 : 1; + unsigned int DISCARD_39 : 1; + unsigned int END_RCVD_39 : 1; + unsigned int DISCARD_40 : 1; + unsigned int END_RCVD_40 : 1; + unsigned int DISCARD_41 : 1; + unsigned int END_RCVD_41 : 1; + unsigned int DISCARD_42 : 1; + unsigned int END_RCVD_42 : 1; + unsigned int DISCARD_43 : 1; + unsigned int END_RCVD_43 : 1; + unsigned int DISCARD_44 : 1; + unsigned int END_RCVD_44 : 1; + unsigned int DISCARD_45 : 1; + unsigned int END_RCVD_45 : 1; + unsigned int DISCARD_46 : 1; + unsigned int END_RCVD_46 : 1; + unsigned int DISCARD_47 : 1; + unsigned int END_RCVD_47 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int END_RCVD_47 : 1; + unsigned int DISCARD_47 : 1; + unsigned int END_RCVD_46 : 1; + unsigned int DISCARD_46 : 1; + unsigned int END_RCVD_45 : 1; + unsigned int DISCARD_45 : 1; + unsigned int END_RCVD_44 : 1; + unsigned int DISCARD_44 : 1; + unsigned int END_RCVD_43 : 1; + unsigned int DISCARD_43 : 1; + unsigned int END_RCVD_42 : 1; + unsigned int DISCARD_42 : 1; + unsigned int END_RCVD_41 : 1; + unsigned int DISCARD_41 : 1; + unsigned int END_RCVD_40 : 1; + unsigned int DISCARD_40 : 1; + unsigned int END_RCVD_39 : 1; + unsigned int DISCARD_39 : 1; + unsigned int END_RCVD_38 : 1; + unsigned int DISCARD_38 : 1; + unsigned int END_RCVD_37 : 1; + unsigned int DISCARD_37 : 1; + unsigned int END_RCVD_36 : 1; + unsigned int DISCARD_36 : 1; + unsigned int END_RCVD_35 : 1; + unsigned int DISCARD_35 : 1; + unsigned int END_RCVD_34 : 1; + unsigned int DISCARD_34 : 1; + unsigned int END_RCVD_33 : 1; + unsigned int DISCARD_33 : 1; + unsigned int END_RCVD_32 : 1; + unsigned int DISCARD_32 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_NV_FLAGS_3 { + struct { +#if defined(qLittleEndian) + unsigned int DISCARD_48 : 1; + unsigned int END_RCVD_48 : 1; + unsigned int DISCARD_49 : 1; + unsigned int END_RCVD_49 : 1; + unsigned int DISCARD_50 : 1; + unsigned int END_RCVD_50 : 1; + unsigned int DISCARD_51 : 1; + unsigned int END_RCVD_51 : 1; + unsigned int DISCARD_52 : 1; + unsigned int END_RCVD_52 : 1; + unsigned int DISCARD_53 : 1; + unsigned int END_RCVD_53 : 1; + unsigned int DISCARD_54 : 1; + unsigned int END_RCVD_54 : 1; + unsigned int DISCARD_55 : 1; + unsigned int END_RCVD_55 : 1; + unsigned int DISCARD_56 : 1; + unsigned int END_RCVD_56 : 1; + unsigned int DISCARD_57 : 1; + unsigned int END_RCVD_57 : 1; + unsigned int DISCARD_58 : 1; + unsigned int END_RCVD_58 : 1; + unsigned int DISCARD_59 : 1; + unsigned int END_RCVD_59 : 1; + unsigned int DISCARD_60 : 1; + unsigned int END_RCVD_60 : 1; + unsigned int DISCARD_61 : 1; + unsigned int END_RCVD_61 : 1; + unsigned int DISCARD_62 : 1; + unsigned int END_RCVD_62 : 1; + unsigned int DISCARD_63 : 1; + unsigned int END_RCVD_63 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int END_RCVD_63 : 1; + unsigned int DISCARD_63 : 1; + unsigned int END_RCVD_62 : 1; + unsigned int DISCARD_62 : 1; + unsigned int END_RCVD_61 : 1; + unsigned int DISCARD_61 : 1; + unsigned int END_RCVD_60 : 1; + unsigned int DISCARD_60 : 1; + unsigned int END_RCVD_59 : 1; + unsigned int DISCARD_59 : 1; + unsigned int END_RCVD_58 : 1; + unsigned int DISCARD_58 : 1; + unsigned int END_RCVD_57 : 1; + unsigned int DISCARD_57 : 1; + unsigned int END_RCVD_56 : 1; + unsigned int DISCARD_56 : 1; + unsigned int END_RCVD_55 : 1; + unsigned int DISCARD_55 : 1; + unsigned int END_RCVD_54 : 1; + unsigned int DISCARD_54 : 1; + unsigned int END_RCVD_53 : 1; + unsigned int DISCARD_53 : 1; + unsigned int END_RCVD_52 : 1; + unsigned int DISCARD_52 : 1; + unsigned int END_RCVD_51 : 1; + unsigned int DISCARD_51 : 1; + unsigned int END_RCVD_50 : 1; + unsigned int DISCARD_50 : 1; + unsigned int END_RCVD_49 : 1; + unsigned int DISCARD_49 : 1; + unsigned int END_RCVD_48 : 1; + unsigned int DISCARD_48 : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STATE_DEBUG_INDEX { + struct { +#if defined(qLittleEndian) + unsigned int STATE_DEBUG_INDEX : 5; + unsigned int : 27; +#else /* !defined(qLittleEndian) */ + unsigned int : 27; + unsigned int STATE_DEBUG_INDEX : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STATE_DEBUG_DATA { + struct { +#if defined(qLittleEndian) + unsigned int STATE_DEBUG_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int STATE_DEBUG_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_PROG_COUNTER { + struct { +#if defined(qLittleEndian) + unsigned int COUNTER : 32; +#else /* !defined(qLittleEndian) */ + unsigned int COUNTER : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union CP_STAT { + struct { +#if defined(qLittleEndian) + unsigned int MIU_WR_BUSY : 1; + unsigned int MIU_RD_REQ_BUSY : 1; + unsigned int MIU_RD_RETURN_BUSY : 1; + unsigned int RBIU_BUSY : 1; + unsigned int RCIU_BUSY : 1; + unsigned int CSF_RING_BUSY : 1; + unsigned int CSF_INDIRECTS_BUSY : 1; + unsigned int CSF_INDIRECT2_BUSY : 1; + unsigned int : 1; + unsigned int CSF_ST_BUSY : 1; + unsigned int CSF_BUSY : 1; + unsigned int RING_QUEUE_BUSY : 1; + unsigned int INDIRECTS_QUEUE_BUSY : 1; + unsigned int INDIRECT2_QUEUE_BUSY : 1; + unsigned int : 2; + unsigned int ST_QUEUE_BUSY : 1; + unsigned int PFP_BUSY : 1; + unsigned int MEQ_RING_BUSY : 1; + unsigned int MEQ_INDIRECTS_BUSY : 1; + unsigned int MEQ_INDIRECT2_BUSY : 1; + unsigned int MIU_WC_STALL : 1; + unsigned int CP_NRT_BUSY : 1; + unsigned int _3D_BUSY : 1; + unsigned int : 2; + unsigned int ME_BUSY : 1; + unsigned int : 2; + unsigned int ME_WC_BUSY : 1; + unsigned int MIU_WC_TRACK_FIFO_EMPTY : 1; + unsigned int CP_BUSY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int CP_BUSY : 1; + unsigned int MIU_WC_TRACK_FIFO_EMPTY : 1; + unsigned int ME_WC_BUSY : 1; + unsigned int : 2; + unsigned int ME_BUSY : 1; + unsigned int : 2; + unsigned int _3D_BUSY : 1; + unsigned int CP_NRT_BUSY : 1; + unsigned int MIU_WC_STALL : 1; + unsigned int MEQ_INDIRECT2_BUSY : 1; + unsigned int MEQ_INDIRECTS_BUSY : 1; + unsigned int MEQ_RING_BUSY : 1; + unsigned int PFP_BUSY : 1; + unsigned int ST_QUEUE_BUSY : 1; + unsigned int : 2; + unsigned int INDIRECT2_QUEUE_BUSY : 1; + unsigned int INDIRECTS_QUEUE_BUSY : 1; + unsigned int RING_QUEUE_BUSY : 1; + unsigned int CSF_BUSY : 1; + unsigned int CSF_ST_BUSY : 1; + unsigned int : 1; + unsigned int CSF_INDIRECT2_BUSY : 1; + unsigned int CSF_INDIRECTS_BUSY : 1; + unsigned int CSF_RING_BUSY : 1; + unsigned int RCIU_BUSY : 1; + unsigned int RBIU_BUSY : 1; + unsigned int MIU_RD_RETURN_BUSY : 1; + unsigned int MIU_RD_REQ_BUSY : 1; + unsigned int MIU_WR_BUSY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_0_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_1_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_2_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_3_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_4_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_5_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_6_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_7_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_8_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_9_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_10_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_11_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_12_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_13_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_14_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BIOS_15_SCRATCH { + struct { +#if defined(qLittleEndian) + unsigned int BIOS_SCRATCH : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BIOS_SCRATCH : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_SIZE_PM4 { + struct { +#if defined(qLittleEndian) + unsigned int SIZE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SIZE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_BASE_PM4 { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BASE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_STATUS_PM4 { + struct { +#if defined(qLittleEndian) + unsigned int MATCHING_CONTEXTS : 8; + unsigned int RB_COPY_DEST_BASE_ENA : 1; + unsigned int DEST_BASE_0_ENA : 1; + unsigned int DEST_BASE_1_ENA : 1; + unsigned int DEST_BASE_2_ENA : 1; + unsigned int DEST_BASE_3_ENA : 1; + unsigned int DEST_BASE_4_ENA : 1; + unsigned int DEST_BASE_5_ENA : 1; + unsigned int DEST_BASE_6_ENA : 1; + unsigned int DEST_BASE_7_ENA : 1; + unsigned int RB_COLOR_INFO_ENA : 1; + unsigned int : 7; + unsigned int TC_ACTION_ENA : 1; + unsigned int : 5; + unsigned int STATUS : 1; +#else /* !defined(qLittleEndian) */ + unsigned int STATUS : 1; + unsigned int : 5; + unsigned int TC_ACTION_ENA : 1; + unsigned int : 7; + unsigned int RB_COLOR_INFO_ENA : 1; + unsigned int DEST_BASE_7_ENA : 1; + unsigned int DEST_BASE_6_ENA : 1; + unsigned int DEST_BASE_5_ENA : 1; + unsigned int DEST_BASE_4_ENA : 1; + unsigned int DEST_BASE_3_ENA : 1; + unsigned int DEST_BASE_2_ENA : 1; + unsigned int DEST_BASE_1_ENA : 1; + unsigned int DEST_BASE_0_ENA : 1; + unsigned int RB_COPY_DEST_BASE_ENA : 1; + unsigned int MATCHING_CONTEXTS : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_SIZE_HOST { + struct { +#if defined(qLittleEndian) + unsigned int SIZE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SIZE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_BASE_HOST { + struct { +#if defined(qLittleEndian) + unsigned int BASE : 32; +#else /* !defined(qLittleEndian) */ + unsigned int BASE : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_STATUS_HOST { + struct { +#if defined(qLittleEndian) + unsigned int MATCHING_CONTEXTS : 8; + unsigned int RB_COPY_DEST_BASE_ENA : 1; + unsigned int DEST_BASE_0_ENA : 1; + unsigned int DEST_BASE_1_ENA : 1; + unsigned int DEST_BASE_2_ENA : 1; + unsigned int DEST_BASE_3_ENA : 1; + unsigned int DEST_BASE_4_ENA : 1; + unsigned int DEST_BASE_5_ENA : 1; + unsigned int DEST_BASE_6_ENA : 1; + unsigned int DEST_BASE_7_ENA : 1; + unsigned int RB_COLOR_INFO_ENA : 1; + unsigned int : 7; + unsigned int TC_ACTION_ENA : 1; + unsigned int : 5; + unsigned int STATUS : 1; +#else /* !defined(qLittleEndian) */ + unsigned int STATUS : 1; + unsigned int : 5; + unsigned int TC_ACTION_ENA : 1; + unsigned int : 7; + unsigned int RB_COLOR_INFO_ENA : 1; + unsigned int DEST_BASE_7_ENA : 1; + unsigned int DEST_BASE_6_ENA : 1; + unsigned int DEST_BASE_5_ENA : 1; + unsigned int DEST_BASE_4_ENA : 1; + unsigned int DEST_BASE_3_ENA : 1; + unsigned int DEST_BASE_2_ENA : 1; + unsigned int DEST_BASE_1_ENA : 1; + unsigned int DEST_BASE_0_ENA : 1; + unsigned int RB_COPY_DEST_BASE_ENA : 1; + unsigned int MATCHING_CONTEXTS : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_0 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_0 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_0 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_1 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_1 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_1 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_2 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_2 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_2 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_3 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_3 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_3 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_4 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_4 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_4 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_5 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_5 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_5 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_6 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_6 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_6 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union COHER_DEST_BASE_7 { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int DEST_BASE_7 : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEST_BASE_7 : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_SURFACE_INFO { + struct { +#if defined(qLittleEndian) + unsigned int SURFACE_PITCH : 14; + unsigned int MSAA_SAMPLES : 2; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int MSAA_SAMPLES : 2; + unsigned int SURFACE_PITCH : 14; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COLOR_INFO { + struct { +#if defined(qLittleEndian) + unsigned int COLOR_FORMAT : 4; + unsigned int COLOR_ROUND_MODE : 2; + unsigned int COLOR_LINEAR : 1; + unsigned int COLOR_ENDIAN : 2; + unsigned int COLOR_SWAP : 2; + unsigned int : 1; + unsigned int COLOR_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int COLOR_BASE : 20; + unsigned int : 1; + unsigned int COLOR_SWAP : 2; + unsigned int COLOR_ENDIAN : 2; + unsigned int COLOR_LINEAR : 1; + unsigned int COLOR_ROUND_MODE : 2; + unsigned int COLOR_FORMAT : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEPTH_INFO { + struct { +#if defined(qLittleEndian) + unsigned int DEPTH_FORMAT : 1; + unsigned int : 11; + unsigned int DEPTH_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int DEPTH_BASE : 20; + unsigned int : 11; + unsigned int DEPTH_FORMAT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_STENCILREFMASK { + struct { +#if defined(qLittleEndian) + unsigned int STENCILREF : 8; + unsigned int STENCILMASK : 8; + unsigned int STENCILWRITEMASK : 8; + unsigned int RESERVED0 : 1; + unsigned int RESERVED1 : 1; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int RESERVED1 : 1; + unsigned int RESERVED0 : 1; + unsigned int STENCILWRITEMASK : 8; + unsigned int STENCILMASK : 8; + unsigned int STENCILREF : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_ALPHA_REF { + struct { +#if defined(qLittleEndian) + unsigned int ALPHA_REF : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ALPHA_REF : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COLOR_MASK { + struct { +#if defined(qLittleEndian) + unsigned int WRITE_RED : 1; + unsigned int WRITE_GREEN : 1; + unsigned int WRITE_BLUE : 1; + unsigned int WRITE_ALPHA : 1; + unsigned int RESERVED2 : 1; + unsigned int RESERVED3 : 1; + unsigned int : 26; +#else /* !defined(qLittleEndian) */ + unsigned int : 26; + unsigned int RESERVED3 : 1; + unsigned int RESERVED2 : 1; + unsigned int WRITE_ALPHA : 1; + unsigned int WRITE_BLUE : 1; + unsigned int WRITE_GREEN : 1; + unsigned int WRITE_RED : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLEND_RED { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_RED : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int BLEND_RED : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLEND_GREEN { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_GREEN : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int BLEND_GREEN : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLEND_BLUE { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_BLUE : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int BLEND_BLUE : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLEND_ALPHA { + struct { +#if defined(qLittleEndian) + unsigned int BLEND_ALPHA : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int BLEND_ALPHA : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_FOG_COLOR { + struct { +#if defined(qLittleEndian) + unsigned int FOG_RED : 8; + unsigned int FOG_GREEN : 8; + unsigned int FOG_BLUE : 8; + unsigned int : 8; +#else /* !defined(qLittleEndian) */ + unsigned int : 8; + unsigned int FOG_BLUE : 8; + unsigned int FOG_GREEN : 8; + unsigned int FOG_RED : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_STENCILREFMASK_BF { + struct { +#if defined(qLittleEndian) + unsigned int STENCILREF_BF : 8; + unsigned int STENCILMASK_BF : 8; + unsigned int STENCILWRITEMASK_BF : 8; + unsigned int RESERVED4 : 1; + unsigned int RESERVED5 : 1; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int RESERVED5 : 1; + unsigned int RESERVED4 : 1; + unsigned int STENCILWRITEMASK_BF : 8; + unsigned int STENCILMASK_BF : 8; + unsigned int STENCILREF_BF : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEPTHCONTROL { + struct { +#if defined(qLittleEndian) + unsigned int STENCIL_ENABLE : 1; + unsigned int Z_ENABLE : 1; + unsigned int Z_WRITE_ENABLE : 1; + unsigned int EARLY_Z_ENABLE : 1; + unsigned int ZFUNC : 3; + unsigned int BACKFACE_ENABLE : 1; + unsigned int STENCILFUNC : 3; + unsigned int STENCILFAIL : 3; + unsigned int STENCILZPASS : 3; + unsigned int STENCILZFAIL : 3; + unsigned int STENCILFUNC_BF : 3; + unsigned int STENCILFAIL_BF : 3; + unsigned int STENCILZPASS_BF : 3; + unsigned int STENCILZFAIL_BF : 3; +#else /* !defined(qLittleEndian) */ + unsigned int STENCILZFAIL_BF : 3; + unsigned int STENCILZPASS_BF : 3; + unsigned int STENCILFAIL_BF : 3; + unsigned int STENCILFUNC_BF : 3; + unsigned int STENCILZFAIL : 3; + unsigned int STENCILZPASS : 3; + unsigned int STENCILFAIL : 3; + unsigned int STENCILFUNC : 3; + unsigned int BACKFACE_ENABLE : 1; + unsigned int ZFUNC : 3; + unsigned int EARLY_Z_ENABLE : 1; + unsigned int Z_WRITE_ENABLE : 1; + unsigned int Z_ENABLE : 1; + unsigned int STENCIL_ENABLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BLENDCONTROL { + struct { +#if defined(qLittleEndian) + unsigned int COLOR_SRCBLEND : 5; + unsigned int COLOR_COMB_FCN : 3; + unsigned int COLOR_DESTBLEND : 5; + unsigned int : 3; + unsigned int ALPHA_SRCBLEND : 5; + unsigned int ALPHA_COMB_FCN : 3; + unsigned int ALPHA_DESTBLEND : 5; + unsigned int BLEND_FORCE_ENABLE : 1; + unsigned int BLEND_FORCE : 1; + unsigned int : 1; +#else /* !defined(qLittleEndian) */ + unsigned int : 1; + unsigned int BLEND_FORCE : 1; + unsigned int BLEND_FORCE_ENABLE : 1; + unsigned int ALPHA_DESTBLEND : 5; + unsigned int ALPHA_COMB_FCN : 3; + unsigned int ALPHA_SRCBLEND : 5; + unsigned int : 3; + unsigned int COLOR_DESTBLEND : 5; + unsigned int COLOR_COMB_FCN : 3; + unsigned int COLOR_SRCBLEND : 5; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COLORCONTROL { + struct { +#if defined(qLittleEndian) + unsigned int ALPHA_FUNC : 3; + unsigned int ALPHA_TEST_ENABLE : 1; + unsigned int ALPHA_TO_MASK_ENABLE : 1; + unsigned int BLEND_DISABLE : 1; + unsigned int FOG_ENABLE : 1; + unsigned int VS_EXPORTS_FOG : 1; + unsigned int ROP_CODE : 4; + unsigned int DITHER_MODE : 2; + unsigned int DITHER_TYPE : 2; + unsigned int PIXEL_FOG : 1; + unsigned int : 7; + unsigned int ALPHA_TO_MASK_OFFSET0 : 2; + unsigned int ALPHA_TO_MASK_OFFSET1 : 2; + unsigned int ALPHA_TO_MASK_OFFSET2 : 2; + unsigned int ALPHA_TO_MASK_OFFSET3 : 2; +#else /* !defined(qLittleEndian) */ + unsigned int ALPHA_TO_MASK_OFFSET3 : 2; + unsigned int ALPHA_TO_MASK_OFFSET2 : 2; + unsigned int ALPHA_TO_MASK_OFFSET1 : 2; + unsigned int ALPHA_TO_MASK_OFFSET0 : 2; + unsigned int : 7; + unsigned int PIXEL_FOG : 1; + unsigned int DITHER_TYPE : 2; + unsigned int DITHER_MODE : 2; + unsigned int ROP_CODE : 4; + unsigned int VS_EXPORTS_FOG : 1; + unsigned int FOG_ENABLE : 1; + unsigned int BLEND_DISABLE : 1; + unsigned int ALPHA_TO_MASK_ENABLE : 1; + unsigned int ALPHA_TEST_ENABLE : 1; + unsigned int ALPHA_FUNC : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_MODECONTROL { + struct { +#if defined(qLittleEndian) + unsigned int EDRAM_MODE : 3; + unsigned int : 29; +#else /* !defined(qLittleEndian) */ + unsigned int : 29; + unsigned int EDRAM_MODE : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COLOR_DEST_MASK { + struct { +#if defined(qLittleEndian) + unsigned int COLOR_DEST_MASK : 32; +#else /* !defined(qLittleEndian) */ + unsigned int COLOR_DEST_MASK : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int COPY_SAMPLE_SELECT : 3; + unsigned int DEPTH_CLEAR_ENABLE : 1; + unsigned int CLEAR_MASK : 4; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int CLEAR_MASK : 4; + unsigned int DEPTH_CLEAR_ENABLE : 1; + unsigned int COPY_SAMPLE_SELECT : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_DEST_BASE { + struct { +#if defined(qLittleEndian) + unsigned int : 12; + unsigned int COPY_DEST_BASE : 20; +#else /* !defined(qLittleEndian) */ + unsigned int COPY_DEST_BASE : 20; + unsigned int : 12; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_DEST_PITCH { + struct { +#if defined(qLittleEndian) + unsigned int COPY_DEST_PITCH : 9; + unsigned int : 23; +#else /* !defined(qLittleEndian) */ + unsigned int : 23; + unsigned int COPY_DEST_PITCH : 9; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_DEST_INFO { + struct { +#if defined(qLittleEndian) + unsigned int COPY_DEST_ENDIAN : 3; + unsigned int COPY_DEST_LINEAR : 1; + unsigned int COPY_DEST_FORMAT : 4; + unsigned int COPY_DEST_SWAP : 2; + unsigned int COPY_DEST_DITHER_MODE : 2; + unsigned int COPY_DEST_DITHER_TYPE : 2; + unsigned int COPY_MASK_WRITE_RED : 1; + unsigned int COPY_MASK_WRITE_GREEN : 1; + unsigned int COPY_MASK_WRITE_BLUE : 1; + unsigned int COPY_MASK_WRITE_ALPHA : 1; + unsigned int : 14; +#else /* !defined(qLittleEndian) */ + unsigned int : 14; + unsigned int COPY_MASK_WRITE_ALPHA : 1; + unsigned int COPY_MASK_WRITE_BLUE : 1; + unsigned int COPY_MASK_WRITE_GREEN : 1; + unsigned int COPY_MASK_WRITE_RED : 1; + unsigned int COPY_DEST_DITHER_TYPE : 2; + unsigned int COPY_DEST_DITHER_MODE : 2; + unsigned int COPY_DEST_SWAP : 2; + unsigned int COPY_DEST_FORMAT : 4; + unsigned int COPY_DEST_LINEAR : 1; + unsigned int COPY_DEST_ENDIAN : 3; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_COPY_DEST_PIXEL_OFFSET { + struct { +#if defined(qLittleEndian) + unsigned int OFFSET_X : 13; + unsigned int OFFSET_Y : 13; + unsigned int : 6; +#else /* !defined(qLittleEndian) */ + unsigned int : 6; + unsigned int OFFSET_Y : 13; + unsigned int OFFSET_X : 13; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEPTH_CLEAR { + struct { +#if defined(qLittleEndian) + unsigned int DEPTH_CLEAR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int DEPTH_CLEAR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_SAMPLE_COUNT_CTL { + struct { +#if defined(qLittleEndian) + unsigned int RESET_SAMPLE_COUNT : 1; + unsigned int COPY_SAMPLE_COUNT : 1; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int COPY_SAMPLE_COUNT : 1; + unsigned int RESET_SAMPLE_COUNT : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_SAMPLE_COUNT_ADDR { + struct { +#if defined(qLittleEndian) + unsigned int SAMPLE_COUNT_ADDR : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SAMPLE_COUNT_ADDR : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BC_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int ACCUM_LINEAR_MODE_ENABLE : 1; + unsigned int ACCUM_TIMEOUT_SELECT : 2; + unsigned int DISABLE_EDRAM_CAM : 1; + unsigned int DISABLE_EZ_FAST_CONTEXT_SWITCH : 1; + unsigned int DISABLE_EZ_NULL_ZCMD_DROP : 1; + unsigned int DISABLE_LZ_NULL_ZCMD_DROP : 1; + unsigned int ENABLE_AZ_THROTTLE : 1; + unsigned int AZ_THROTTLE_COUNT : 5; + unsigned int : 1; + unsigned int ENABLE_CRC_UPDATE : 1; + unsigned int CRC_MODE : 1; + unsigned int DISABLE_SAMPLE_COUNTERS : 1; + unsigned int DISABLE_ACCUM : 1; + unsigned int ACCUM_ALLOC_MASK : 4; + unsigned int LINEAR_PERFORMANCE_ENABLE : 1; + unsigned int ACCUM_DATA_FIFO_LIMIT : 4; + unsigned int MEM_EXPORT_TIMEOUT_SELECT : 2; + unsigned int MEM_EXPORT_LINEAR_MODE_ENABLE : 1; + unsigned int CRC_SYSTEM : 1; + unsigned int RESERVED6 : 1; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED6 : 1; + unsigned int CRC_SYSTEM : 1; + unsigned int MEM_EXPORT_LINEAR_MODE_ENABLE : 1; + unsigned int MEM_EXPORT_TIMEOUT_SELECT : 2; + unsigned int ACCUM_DATA_FIFO_LIMIT : 4; + unsigned int LINEAR_PERFORMANCE_ENABLE : 1; + unsigned int ACCUM_ALLOC_MASK : 4; + unsigned int DISABLE_ACCUM : 1; + unsigned int DISABLE_SAMPLE_COUNTERS : 1; + unsigned int CRC_MODE : 1; + unsigned int ENABLE_CRC_UPDATE : 1; + unsigned int : 1; + unsigned int AZ_THROTTLE_COUNT : 5; + unsigned int ENABLE_AZ_THROTTLE : 1; + unsigned int DISABLE_LZ_NULL_ZCMD_DROP : 1; + unsigned int DISABLE_EZ_NULL_ZCMD_DROP : 1; + unsigned int DISABLE_EZ_FAST_CONTEXT_SWITCH : 1; + unsigned int DISABLE_EDRAM_CAM : 1; + unsigned int ACCUM_TIMEOUT_SELECT : 2; + unsigned int ACCUM_LINEAR_MODE_ENABLE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_EDRAM_INFO { + struct { +#if defined(qLittleEndian) + unsigned int EDRAM_SIZE : 4; + unsigned int EDRAM_MAPPING_MODE : 2; + unsigned int : 8; + unsigned int EDRAM_RANGE : 18; +#else /* !defined(qLittleEndian) */ + unsigned int EDRAM_RANGE : 18; + unsigned int : 8; + unsigned int EDRAM_MAPPING_MODE : 2; + unsigned int EDRAM_SIZE : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_CRC_RD_PORT { + struct { +#if defined(qLittleEndian) + unsigned int CRC_DATA : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CRC_DATA : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_CRC_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int CRC_RD_ADVANCE : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int CRC_RD_ADVANCE : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_CRC_MASK { + struct { +#if defined(qLittleEndian) + unsigned int CRC_MASK : 32; +#else /* !defined(qLittleEndian) */ + unsigned int CRC_MASK : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_PERFCOUNTER0_SELECT { + struct { +#if defined(qLittleEndian) + unsigned int PERF_SEL : 8; + unsigned int : 24; +#else /* !defined(qLittleEndian) */ + unsigned int : 24; + unsigned int PERF_SEL : 8; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_PERFCOUNTER0_LOW { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 32; +#else /* !defined(qLittleEndian) */ + unsigned int PERF_COUNT : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_PERFCOUNTER0_HI { + struct { +#if defined(qLittleEndian) + unsigned int PERF_COUNT : 16; + unsigned int : 16; +#else /* !defined(qLittleEndian) */ + unsigned int : 16; + unsigned int PERF_COUNT : 16; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_TOTAL_SAMPLES { + struct { +#if defined(qLittleEndian) + unsigned int TOTAL_SAMPLES : 32; +#else /* !defined(qLittleEndian) */ + unsigned int TOTAL_SAMPLES : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_ZPASS_SAMPLES { + struct { +#if defined(qLittleEndian) + unsigned int ZPASS_SAMPLES : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ZPASS_SAMPLES : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_ZFAIL_SAMPLES { + struct { +#if defined(qLittleEndian) + unsigned int ZFAIL_SAMPLES : 32; +#else /* !defined(qLittleEndian) */ + unsigned int ZFAIL_SAMPLES : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_SFAIL_SAMPLES { + struct { +#if defined(qLittleEndian) + unsigned int SFAIL_SAMPLES : 32; +#else /* !defined(qLittleEndian) */ + unsigned int SFAIL_SAMPLES : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_0 { + struct { +#if defined(qLittleEndian) + unsigned int RDREQ_CTL_Z1_PRE_FULL : 1; + unsigned int RDREQ_CTL_Z0_PRE_FULL : 1; + unsigned int RDREQ_CTL_C1_PRE_FULL : 1; + unsigned int RDREQ_CTL_C0_PRE_FULL : 1; + unsigned int RDREQ_E1_ORDERING_FULL : 1; + unsigned int RDREQ_E0_ORDERING_FULL : 1; + unsigned int RDREQ_Z1_FULL : 1; + unsigned int RDREQ_Z0_FULL : 1; + unsigned int RDREQ_C1_FULL : 1; + unsigned int RDREQ_C0_FULL : 1; + unsigned int WRREQ_E1_MACRO_HI_FULL : 1; + unsigned int WRREQ_E1_MACRO_LO_FULL : 1; + unsigned int WRREQ_E0_MACRO_HI_FULL : 1; + unsigned int WRREQ_E0_MACRO_LO_FULL : 1; + unsigned int WRREQ_C_WE_HI_FULL : 1; + unsigned int WRREQ_C_WE_LO_FULL : 1; + unsigned int WRREQ_Z1_FULL : 1; + unsigned int WRREQ_Z0_FULL : 1; + unsigned int WRREQ_C1_FULL : 1; + unsigned int WRREQ_C0_FULL : 1; + unsigned int CMDFIFO_Z1_HOLD_FULL : 1; + unsigned int CMDFIFO_Z0_HOLD_FULL : 1; + unsigned int CMDFIFO_C1_HOLD_FULL : 1; + unsigned int CMDFIFO_C0_HOLD_FULL : 1; + unsigned int CMDFIFO_Z_ORDERING_FULL : 1; + unsigned int CMDFIFO_C_ORDERING_FULL : 1; + unsigned int C_SX_LAT_FULL : 1; + unsigned int C_SX_CMD_FULL : 1; + unsigned int C_EZ_TILE_FULL : 1; + unsigned int C_REQ_FULL : 1; + unsigned int C_MASK_FULL : 1; + unsigned int EZ_INFSAMP_FULL : 1; +#else /* !defined(qLittleEndian) */ + unsigned int EZ_INFSAMP_FULL : 1; + unsigned int C_MASK_FULL : 1; + unsigned int C_REQ_FULL : 1; + unsigned int C_EZ_TILE_FULL : 1; + unsigned int C_SX_CMD_FULL : 1; + unsigned int C_SX_LAT_FULL : 1; + unsigned int CMDFIFO_C_ORDERING_FULL : 1; + unsigned int CMDFIFO_Z_ORDERING_FULL : 1; + unsigned int CMDFIFO_C0_HOLD_FULL : 1; + unsigned int CMDFIFO_C1_HOLD_FULL : 1; + unsigned int CMDFIFO_Z0_HOLD_FULL : 1; + unsigned int CMDFIFO_Z1_HOLD_FULL : 1; + unsigned int WRREQ_C0_FULL : 1; + unsigned int WRREQ_C1_FULL : 1; + unsigned int WRREQ_Z0_FULL : 1; + unsigned int WRREQ_Z1_FULL : 1; + unsigned int WRREQ_C_WE_LO_FULL : 1; + unsigned int WRREQ_C_WE_HI_FULL : 1; + unsigned int WRREQ_E0_MACRO_LO_FULL : 1; + unsigned int WRREQ_E0_MACRO_HI_FULL : 1; + unsigned int WRREQ_E1_MACRO_LO_FULL : 1; + unsigned int WRREQ_E1_MACRO_HI_FULL : 1; + unsigned int RDREQ_C0_FULL : 1; + unsigned int RDREQ_C1_FULL : 1; + unsigned int RDREQ_Z0_FULL : 1; + unsigned int RDREQ_Z1_FULL : 1; + unsigned int RDREQ_E0_ORDERING_FULL : 1; + unsigned int RDREQ_E1_ORDERING_FULL : 1; + unsigned int RDREQ_CTL_C0_PRE_FULL : 1; + unsigned int RDREQ_CTL_C1_PRE_FULL : 1; + unsigned int RDREQ_CTL_Z0_PRE_FULL : 1; + unsigned int RDREQ_CTL_Z1_PRE_FULL : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_1 { + struct { +#if defined(qLittleEndian) + unsigned int RDREQ_Z1_CMD_EMPTY : 1; + unsigned int RDREQ_Z0_CMD_EMPTY : 1; + unsigned int RDREQ_C1_CMD_EMPTY : 1; + unsigned int RDREQ_C0_CMD_EMPTY : 1; + unsigned int RDREQ_E1_ORDERING_EMPTY : 1; + unsigned int RDREQ_E0_ORDERING_EMPTY : 1; + unsigned int RDREQ_Z1_EMPTY : 1; + unsigned int RDREQ_Z0_EMPTY : 1; + unsigned int RDREQ_C1_EMPTY : 1; + unsigned int RDREQ_C0_EMPTY : 1; + unsigned int WRREQ_E1_MACRO_HI_EMPTY : 1; + unsigned int WRREQ_E1_MACRO_LO_EMPTY : 1; + unsigned int WRREQ_E0_MACRO_HI_EMPTY : 1; + unsigned int WRREQ_E0_MACRO_LO_EMPTY : 1; + unsigned int WRREQ_C_WE_HI_EMPTY : 1; + unsigned int WRREQ_C_WE_LO_EMPTY : 1; + unsigned int WRREQ_Z1_EMPTY : 1; + unsigned int WRREQ_Z0_EMPTY : 1; + unsigned int WRREQ_C1_PRE_EMPTY : 1; + unsigned int WRREQ_C0_PRE_EMPTY : 1; + unsigned int CMDFIFO_Z1_HOLD_EMPTY : 1; + unsigned int CMDFIFO_Z0_HOLD_EMPTY : 1; + unsigned int CMDFIFO_C1_HOLD_EMPTY : 1; + unsigned int CMDFIFO_C0_HOLD_EMPTY : 1; + unsigned int CMDFIFO_Z_ORDERING_EMPTY : 1; + unsigned int CMDFIFO_C_ORDERING_EMPTY : 1; + unsigned int C_SX_LAT_EMPTY : 1; + unsigned int C_SX_CMD_EMPTY : 1; + unsigned int C_EZ_TILE_EMPTY : 1; + unsigned int C_REQ_EMPTY : 1; + unsigned int C_MASK_EMPTY : 1; + unsigned int EZ_INFSAMP_EMPTY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int EZ_INFSAMP_EMPTY : 1; + unsigned int C_MASK_EMPTY : 1; + unsigned int C_REQ_EMPTY : 1; + unsigned int C_EZ_TILE_EMPTY : 1; + unsigned int C_SX_CMD_EMPTY : 1; + unsigned int C_SX_LAT_EMPTY : 1; + unsigned int CMDFIFO_C_ORDERING_EMPTY : 1; + unsigned int CMDFIFO_Z_ORDERING_EMPTY : 1; + unsigned int CMDFIFO_C0_HOLD_EMPTY : 1; + unsigned int CMDFIFO_C1_HOLD_EMPTY : 1; + unsigned int CMDFIFO_Z0_HOLD_EMPTY : 1; + unsigned int CMDFIFO_Z1_HOLD_EMPTY : 1; + unsigned int WRREQ_C0_PRE_EMPTY : 1; + unsigned int WRREQ_C1_PRE_EMPTY : 1; + unsigned int WRREQ_Z0_EMPTY : 1; + unsigned int WRREQ_Z1_EMPTY : 1; + unsigned int WRREQ_C_WE_LO_EMPTY : 1; + unsigned int WRREQ_C_WE_HI_EMPTY : 1; + unsigned int WRREQ_E0_MACRO_LO_EMPTY : 1; + unsigned int WRREQ_E0_MACRO_HI_EMPTY : 1; + unsigned int WRREQ_E1_MACRO_LO_EMPTY : 1; + unsigned int WRREQ_E1_MACRO_HI_EMPTY : 1; + unsigned int RDREQ_C0_EMPTY : 1; + unsigned int RDREQ_C1_EMPTY : 1; + unsigned int RDREQ_Z0_EMPTY : 1; + unsigned int RDREQ_Z1_EMPTY : 1; + unsigned int RDREQ_E0_ORDERING_EMPTY : 1; + unsigned int RDREQ_E1_ORDERING_EMPTY : 1; + unsigned int RDREQ_C0_CMD_EMPTY : 1; + unsigned int RDREQ_C1_CMD_EMPTY : 1; + unsigned int RDREQ_Z0_CMD_EMPTY : 1; + unsigned int RDREQ_Z1_CMD_EMPTY : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_2 { + struct { +#if defined(qLittleEndian) + unsigned int TILE_FIFO_COUNT : 4; + unsigned int SX_LAT_FIFO_COUNT : 7; + unsigned int MEM_EXPORT_FLAG : 1; + unsigned int SYSMEM_BLEND_FLAG : 1; + unsigned int CURRENT_TILE_EVENT : 1; + unsigned int EZ_INFTILE_FULL : 1; + unsigned int EZ_MASK_LOWER_FULL : 1; + unsigned int EZ_MASK_UPPER_FULL : 1; + unsigned int Z0_MASK_FULL : 1; + unsigned int Z1_MASK_FULL : 1; + unsigned int Z0_REQ_FULL : 1; + unsigned int Z1_REQ_FULL : 1; + unsigned int Z_SAMP_FULL : 1; + unsigned int Z_TILE_FULL : 1; + unsigned int EZ_INFTILE_EMPTY : 1; + unsigned int EZ_MASK_LOWER_EMPTY : 1; + unsigned int EZ_MASK_UPPER_EMPTY : 1; + unsigned int Z0_MASK_EMPTY : 1; + unsigned int Z1_MASK_EMPTY : 1; + unsigned int Z0_REQ_EMPTY : 1; + unsigned int Z1_REQ_EMPTY : 1; + unsigned int Z_SAMP_EMPTY : 1; + unsigned int Z_TILE_EMPTY : 1; +#else /* !defined(qLittleEndian) */ + unsigned int Z_TILE_EMPTY : 1; + unsigned int Z_SAMP_EMPTY : 1; + unsigned int Z1_REQ_EMPTY : 1; + unsigned int Z0_REQ_EMPTY : 1; + unsigned int Z1_MASK_EMPTY : 1; + unsigned int Z0_MASK_EMPTY : 1; + unsigned int EZ_MASK_UPPER_EMPTY : 1; + unsigned int EZ_MASK_LOWER_EMPTY : 1; + unsigned int EZ_INFTILE_EMPTY : 1; + unsigned int Z_TILE_FULL : 1; + unsigned int Z_SAMP_FULL : 1; + unsigned int Z1_REQ_FULL : 1; + unsigned int Z0_REQ_FULL : 1; + unsigned int Z1_MASK_FULL : 1; + unsigned int Z0_MASK_FULL : 1; + unsigned int EZ_MASK_UPPER_FULL : 1; + unsigned int EZ_MASK_LOWER_FULL : 1; + unsigned int EZ_INFTILE_FULL : 1; + unsigned int CURRENT_TILE_EVENT : 1; + unsigned int SYSMEM_BLEND_FLAG : 1; + unsigned int MEM_EXPORT_FLAG : 1; + unsigned int SX_LAT_FIFO_COUNT : 7; + unsigned int TILE_FIFO_COUNT : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_3 { + struct { +#if defined(qLittleEndian) + unsigned int ACCUM_VALID : 4; + unsigned int ACCUM_FLUSHING : 4; + unsigned int ACCUM_WRITE_CLEAN_COUNT : 6; + unsigned int ACCUM_INPUT_REG_VALID : 1; + unsigned int ACCUM_DATA_FIFO_CNT : 4; + unsigned int SHD_FULL : 1; + unsigned int SHD_EMPTY : 1; + unsigned int EZ_RETURN_LOWER_EMPTY : 1; + unsigned int EZ_RETURN_UPPER_EMPTY : 1; + unsigned int EZ_RETURN_LOWER_FULL : 1; + unsigned int EZ_RETURN_UPPER_FULL : 1; + unsigned int ZEXP_LOWER_EMPTY : 1; + unsigned int ZEXP_UPPER_EMPTY : 1; + unsigned int ZEXP_LOWER_FULL : 1; + unsigned int ZEXP_UPPER_FULL : 1; + unsigned int : 3; +#else /* !defined(qLittleEndian) */ + unsigned int : 3; + unsigned int ZEXP_UPPER_FULL : 1; + unsigned int ZEXP_LOWER_FULL : 1; + unsigned int ZEXP_UPPER_EMPTY : 1; + unsigned int ZEXP_LOWER_EMPTY : 1; + unsigned int EZ_RETURN_UPPER_FULL : 1; + unsigned int EZ_RETURN_LOWER_FULL : 1; + unsigned int EZ_RETURN_UPPER_EMPTY : 1; + unsigned int EZ_RETURN_LOWER_EMPTY : 1; + unsigned int SHD_EMPTY : 1; + unsigned int SHD_FULL : 1; + unsigned int ACCUM_DATA_FIFO_CNT : 4; + unsigned int ACCUM_INPUT_REG_VALID : 1; + unsigned int ACCUM_WRITE_CLEAN_COUNT : 6; + unsigned int ACCUM_FLUSHING : 4; + unsigned int ACCUM_VALID : 4; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_DEBUG_4 { + struct { +#if defined(qLittleEndian) + unsigned int GMEM_RD_ACCESS_FLAG : 1; + unsigned int GMEM_WR_ACCESS_FLAG : 1; + unsigned int SYSMEM_RD_ACCESS_FLAG : 1; + unsigned int SYSMEM_WR_ACCESS_FLAG : 1; + unsigned int ACCUM_DATA_FIFO_EMPTY : 1; + unsigned int ACCUM_ORDER_FIFO_EMPTY : 1; + unsigned int ACCUM_DATA_FIFO_FULL : 1; + unsigned int ACCUM_ORDER_FIFO_FULL : 1; + unsigned int SYSMEM_WRITE_COUNT_OVERFLOW : 1; + unsigned int CONTEXT_COUNT_DEBUG : 4; + unsigned int : 19; +#else /* !defined(qLittleEndian) */ + unsigned int : 19; + unsigned int CONTEXT_COUNT_DEBUG : 4; + unsigned int SYSMEM_WRITE_COUNT_OVERFLOW : 1; + unsigned int ACCUM_ORDER_FIFO_FULL : 1; + unsigned int ACCUM_DATA_FIFO_FULL : 1; + unsigned int ACCUM_ORDER_FIFO_EMPTY : 1; + unsigned int ACCUM_DATA_FIFO_EMPTY : 1; + unsigned int SYSMEM_WR_ACCESS_FLAG : 1; + unsigned int SYSMEM_RD_ACCESS_FLAG : 1; + unsigned int GMEM_WR_ACCESS_FLAG : 1; + unsigned int GMEM_RD_ACCESS_FLAG : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_FLAG_CONTROL { + struct { +#if defined(qLittleEndian) + unsigned int DEBUG_FLAG_CLEAR : 1; + unsigned int : 31; +#else /* !defined(qLittleEndian) */ + unsigned int : 31; + unsigned int DEBUG_FLAG_CLEAR : 1; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union RB_BC_SPARES { + struct { +#if defined(qLittleEndian) + unsigned int RESERVED : 32; +#else /* !defined(qLittleEndian) */ + unsigned int RESERVED : 32; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BC_DUMMY_CRAYRB_ENUMS { + struct { +#if defined(qLittleEndian) + unsigned int DUMMY_CRAYRB_DEPTH_FORMAT : 6; + unsigned int DUMMY_CRAYRB_SURFACE_SWAP : 1; + unsigned int DUMMY_CRAYRB_DEPTH_ARRAY : 2; + unsigned int DUMMY_CRAYRB_ARRAY : 2; + unsigned int DUMMY_CRAYRB_COLOR_FORMAT : 6; + unsigned int DUMMY_CRAYRB_SURFACE_NUMBER : 3; + unsigned int DUMMY_CRAYRB_SURFACE_FORMAT : 6; + unsigned int DUMMY_CRAYRB_SURFACE_TILING : 1; + unsigned int DUMMY_CRAYRB_SURFACE_ARRAY : 2; + unsigned int DUMMY_RB_COPY_DEST_INFO_NUMBER : 3; +#else /* !defined(qLittleEndian) */ + unsigned int DUMMY_RB_COPY_DEST_INFO_NUMBER : 3; + unsigned int DUMMY_CRAYRB_SURFACE_ARRAY : 2; + unsigned int DUMMY_CRAYRB_SURFACE_TILING : 1; + unsigned int DUMMY_CRAYRB_SURFACE_FORMAT : 6; + unsigned int DUMMY_CRAYRB_SURFACE_NUMBER : 3; + unsigned int DUMMY_CRAYRB_COLOR_FORMAT : 6; + unsigned int DUMMY_CRAYRB_ARRAY : 2; + unsigned int DUMMY_CRAYRB_DEPTH_ARRAY : 2; + unsigned int DUMMY_CRAYRB_SURFACE_SWAP : 1; + unsigned int DUMMY_CRAYRB_DEPTH_FORMAT : 6; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + + union BC_DUMMY_CRAYRB_MOREENUMS { + struct { +#if defined(qLittleEndian) + unsigned int DUMMY_CRAYRB_COLORARRAYX : 2; + unsigned int : 30; +#else /* !defined(qLittleEndian) */ + unsigned int : 30; + unsigned int DUMMY_CRAYRB_COLORARRAYX : 2; +#endif /* defined(qLittleEndian) */ + } bitfields, bits; + unsigned int u32All; + signed int i32All; + float f32All; + }; + + +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_shift.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_shift.h new file mode 100644 index 000000000000..69677996b133 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_shift.h @@ -0,0 +1,4184 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_SHIFT_HEADER) +#define _yamato_SHIFT_HEADER + +// PA_CL_VPORT_XSCALE +#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x00000000 + +// PA_CL_VPORT_XOFFSET +#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x00000000 + +// PA_CL_VPORT_YSCALE +#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x00000000 + +// PA_CL_VPORT_YOFFSET +#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x00000000 + +// PA_CL_VPORT_ZSCALE +#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x00000000 + +// PA_CL_VPORT_ZOFFSET +#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x00000000 + +// PA_CL_VTE_CNTL +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x00000000 +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x00000001 +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x00000002 +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x00000003 +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x00000004 +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x00000005 +#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x00000008 +#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x00000009 +#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0x0000000a +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0x0000000b + +// PA_CL_CLIP_CNTL +#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x00000010 +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x00000012 +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x00000013 +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x00000014 +#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x00000015 +#define PA_CL_CLIP_CNTL__XY_NAN_RETAIN__SHIFT 0x00000016 +#define PA_CL_CLIP_CNTL__Z_NAN_RETAIN__SHIFT 0x00000017 +#define PA_CL_CLIP_CNTL__W_NAN_RETAIN__SHIFT 0x00000018 + +// PA_CL_GB_VERT_CLIP_ADJ +#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x00000000 + +// PA_CL_GB_VERT_DISC_ADJ +#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x00000000 + +// PA_CL_GB_HORZ_CLIP_ADJ +#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x00000000 + +// PA_CL_GB_HORZ_DISC_ADJ +#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x00000000 + +// PA_CL_ENHANCE +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x00000000 +#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x0000001c +#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x0000001d +#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x0000001e +#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x0000001f + +// PA_SC_ENHANCE +#define PA_SC_ENHANCE__ECO_SPARE3__SHIFT 0x0000001c +#define PA_SC_ENHANCE__ECO_SPARE2__SHIFT 0x0000001d +#define PA_SC_ENHANCE__ECO_SPARE1__SHIFT 0x0000001e +#define PA_SC_ENHANCE__ECO_SPARE0__SHIFT 0x0000001f + +// PA_SU_VTX_CNTL +#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x00000000 +#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x00000001 +#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x00000003 + +// PA_SU_POINT_SIZE +#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x00000000 +#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x00000010 + +// PA_SU_POINT_MINMAX +#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x00000000 +#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x00000010 + +// PA_SU_LINE_CNTL +#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x00000000 + +// PA_SU_FACE_DATA +#define PA_SU_FACE_DATA__BASE_ADDR__SHIFT 0x00000005 + +// PA_SU_SC_MODE_CNTL +#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x00000000 +#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x00000001 +#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x00000002 +#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x00000003 +#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x00000005 +#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x00000008 +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0x0000000b +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0x0000000c +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0x0000000d +#define PA_SU_SC_MODE_CNTL__MSAA_ENABLE__SHIFT 0x0000000f +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x00000010 +#define PA_SU_SC_MODE_CNTL__LINE_STIPPLE_ENABLE__SHIFT 0x00000012 +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x00000013 +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x00000014 +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x00000015 +#define PA_SU_SC_MODE_CNTL__QUAD_ORDER_ENABLE__SHIFT 0x00000017 +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_ALL_TRI__SHIFT 0x00000019 +#define PA_SU_SC_MODE_CNTL__WAIT_RB_IDLE_FIRST_TRI_NEW_STATE__SHIFT 0x0000001a +#define PA_SU_SC_MODE_CNTL__CLAMPED_FACENESS__SHIFT 0x0000001c +#define PA_SU_SC_MODE_CNTL__ZERO_AREA_FACENESS__SHIFT 0x0000001d +#define PA_SU_SC_MODE_CNTL__FACE_KILL_ENABLE__SHIFT 0x0000001e +#define PA_SU_SC_MODE_CNTL__FACE_WRITE_ENABLE__SHIFT 0x0000001f + +// PA_SU_POLY_OFFSET_FRONT_SCALE +#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x00000000 + +// PA_SU_POLY_OFFSET_FRONT_OFFSET +#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x00000000 + +// PA_SU_POLY_OFFSET_BACK_SCALE +#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x00000000 + +// PA_SU_POLY_OFFSET_BACK_OFFSET +#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER0_SELECT +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER1_SELECT +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER2_SELECT +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER3_SELECT +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER0_LOW +#define PA_SU_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER0_HI +#define PA_SU_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER1_LOW +#define PA_SU_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER1_HI +#define PA_SU_PERFCOUNTER1_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER2_LOW +#define PA_SU_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER2_HI +#define PA_SU_PERFCOUNTER2_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER3_LOW +#define PA_SU_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SU_PERFCOUNTER3_HI +#define PA_SU_PERFCOUNTER3_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_SC_WINDOW_OFFSET +#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x00000000 +#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x00000010 + +// PA_SC_AA_CONFIG +#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x00000000 +#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0x0000000d + +// PA_SC_AA_MASK +#define PA_SC_AA_MASK__AA_MASK__SHIFT 0x00000000 + +// PA_SC_LINE_STIPPLE +#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x00000000 +#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x00000010 +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x0000001c +#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x0000001d + +// PA_SC_LINE_CNTL +#define PA_SC_LINE_CNTL__BRES_CNTL__SHIFT 0x00000000 +#define PA_SC_LINE_CNTL__USE_BRES_CNTL__SHIFT 0x00000008 +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x00000009 +#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0x0000000a + +// PA_SC_WINDOW_SCISSOR_TL +#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x00000010 +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x0000001f + +// PA_SC_WINDOW_SCISSOR_BR +#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x00000010 + +// PA_SC_SCREEN_SCISSOR_TL +#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x00000000 +#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x00000010 + +// PA_SC_SCREEN_SCISSOR_BR +#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x00000000 +#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x00000010 + +// PA_SC_VIZ_QUERY +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ENA__SHIFT 0x00000000 +#define PA_SC_VIZ_QUERY__VIZ_QUERY_ID__SHIFT 0x00000001 +#define PA_SC_VIZ_QUERY__KILL_PIX_POST_EARLY_Z__SHIFT 0x00000007 + +// PA_SC_VIZ_QUERY_STATUS +#define PA_SC_VIZ_QUERY_STATUS__STATUS_BITS__SHIFT 0x00000000 + +// PA_SC_LINE_STIPPLE_STATE +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x00000000 +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x00000008 + +// PA_SC_PERFCOUNTER0_SELECT +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// PA_SC_PERFCOUNTER0_LOW +#define PA_SC_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// PA_SC_PERFCOUNTER0_HI +#define PA_SC_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// PA_CL_CNTL_STATUS +#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT 0x0000001f + +// PA_SU_CNTL_STATUS +#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x0000001f + +// PA_SC_CNTL_STATUS +#define PA_SC_CNTL_STATUS__SC_BUSY__SHIFT 0x0000001f + +// PA_SU_DEBUG_CNTL +#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT 0x00000000 + +// PA_SU_DEBUG_DATA +#define PA_SU_DEBUG_DATA__DATA__SHIFT 0x00000000 + +// CLIPPER_DEBUG_REG00 +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_full__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT 0x00000002 +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT 0x00000003 +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0x00000005 +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x00000009 +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x0000000a +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT 0x0000000d +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x0000000e +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x0000000f +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x00000010 +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x00000011 +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT 0x00000014 + +// CLIPPER_DEBUG_REG01 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_end_of_packet__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_first_prim_of_slot__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x00000002 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_clipped_prim__SHIFT 0x00000005 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_2__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_1__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_store_indx_0__SHIFT 0x0000000f +#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x00000016 +#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT 0x00000018 + +// CLIPPER_DEBUG_REG02 +#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO1__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG02__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG02__ALWAYS_ZERO0__SHIFT 0x00000018 +#define CLIPPER_DEBUG_REG02__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f + +// CLIPPER_DEBUG_REG03 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO3__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x00000003 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO2__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO1__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG03__ALWAYS_ZERO0__SHIFT 0x0000001a + +// CLIPPER_DEBUG_REG04 +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO2__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x00000003 +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO1__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x00000007 +#define CLIPPER_DEBUG_REG04__ALWAYS_ZERO0__SHIFT 0x00000008 + +// CLIPPER_DEBUG_REG05 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO3__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x00000003 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_event_id__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO2__SHIFT 0x00000010 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO1__SHIFT 0x00000016 +#define CLIPPER_DEBUG_REG05__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000018 +#define CLIPPER_DEBUG_REG05__ALWAYS_ZERO0__SHIFT 0x0000001c + +// CLIPPER_DEBUG_REG09 +#define CLIPPER_DEBUG_REG09__clprim_in_back_event__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG09__outputclprimtoclip_null_primitive__SHIFT 0x00000001 +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_2__SHIFT 0x00000002 +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO2__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_1__SHIFT 0x00000008 +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO1__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG09__clprim_in_back_vertex_store_indx_0__SHIFT 0x0000000e +#define CLIPPER_DEBUG_REG09__ALWAYS_ZERO0__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG09__prim_back_valid__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_out_cnt__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_orig_vertices__SHIFT 0x00000019 +#define CLIPPER_DEBUG_REG09__outsm_clr_rd_clipsm_wait__SHIFT 0x0000001b +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_empty__SHIFT 0x0000001c +#define CLIPPER_DEBUG_REG09__outsm_clr_fifo_full__SHIFT 0x0000001d +#define CLIPPER_DEBUG_REG09__clip_priority_seq_indx_load__SHIFT 0x0000001e + +// CLIPPER_DEBUG_REG10 +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO3__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO2__SHIFT 0x0000000a +#define CLIPPER_DEBUG_REG10__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x0000000c +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO1__SHIFT 0x00000010 +#define CLIPPER_DEBUG_REG10__clprim_in_back_state_var_indx__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG10__ALWAYS_ZERO0__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG10__clprim_in_back_end_of_packet__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG10__clprim_in_back_first_prim_of_slot__SHIFT 0x00000016 +#define CLIPPER_DEBUG_REG10__clprim_in_back_deallocate_slot__SHIFT 0x00000017 +#define CLIPPER_DEBUG_REG10__clprim_in_back_event_id__SHIFT 0x0000001a + +// CLIPPER_DEBUG_REG11 +#define CLIPPER_DEBUG_REG11__vertval_bits_vertex_vertex_store_msb__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG11__ALWAYS_ZERO__SHIFT 0x00000004 + +// CLIPPER_DEBUG_REG12 +#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO2__SHIFT 0x00000002 +#define CLIPPER_DEBUG_REG12__clip_vertex_fifo_empty__SHIFT 0x00000005 +#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0x00000006 +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO1__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG12__vertval_bits_vertex_cc_next_valid__SHIFT 0x0000000f +#define CLIPPER_DEBUG_REG12__clipcc_vertex_store_indx__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG12__primic_to_clprim_valid__SHIFT 0x00000015 +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO0__SHIFT 0x00000016 + +// CLIPPER_DEBUG_REG13 +#define CLIPPER_DEBUG_REG13__sm0_clip_vert_cnt__SHIFT 0x00000000 +#define CLIPPER_DEBUG_REG13__sm0_prim_end_state__SHIFT 0x00000004 +#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO1__SHIFT 0x0000000b +#define CLIPPER_DEBUG_REG13__sm0_vertex_clip_cnt__SHIFT 0x0000000e +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_1__SHIFT 0x00000012 +#define CLIPPER_DEBUG_REG13__sm0_inv_to_clip_data_valid_0__SHIFT 0x00000013 +#define CLIPPER_DEBUG_REG13__sm0_current_state__SHIFT 0x00000014 +#define CLIPPER_DEBUG_REG13__ALWAYS_ZERO0__SHIFT 0x0000001b + +// SXIFCCG_DEBUG_REG0 +#define SXIFCCG_DEBUG_REG0__nan_kill_flag__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG0__position_address__SHIFT 0x00000004 +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO2__SHIFT 0x00000007 +#define SXIFCCG_DEBUG_REG0__point_address__SHIFT 0x0000000a +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO1__SHIFT 0x0000000d +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx__SHIFT 0x00000010 +#define SXIFCCG_DEBUG_REG0__ALWAYS_ZERO0__SHIFT 0x00000011 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask__SHIFT 0x00000013 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci__SHIFT 0x00000017 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc__SHIFT 0x0000001e +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel__SHIFT 0x0000001f + +// SXIFCCG_DEBUG_REG1 +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO3__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty__SHIFT 0x00000002 +#define SXIFCCG_DEBUG_REG1__available_positions__SHIFT 0x00000004 +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO2__SHIFT 0x00000007 +#define SXIFCCG_DEBUG_REG1__sx_pending_advance__SHIFT 0x0000000b +#define SXIFCCG_DEBUG_REG1__sx_receive_indx__SHIFT 0x0000000c +#define SXIFCCG_DEBUG_REG1__statevar_bits_sxpa_aux_vector__SHIFT 0x0000000f +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO1__SHIFT 0x00000010 +#define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT 0x00000014 +#define SXIFCCG_DEBUG_REG1__ALWAYS_ZERO0__SHIFT 0x00000015 +#define SXIFCCG_DEBUG_REG1__pasx_req_cnt__SHIFT 0x00000017 +#define SXIFCCG_DEBUG_REG1__param_cache_base__SHIFT 0x00000019 + +// SXIFCCG_DEBUG_REG2 +#define SXIFCCG_DEBUG_REG2__sx_sent__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO3__SHIFT 0x00000001 +#define SXIFCCG_DEBUG_REG2__sx_aux__SHIFT 0x00000002 +#define SXIFCCG_DEBUG_REG2__sx_request_indx__SHIFT 0x00000003 +#define SXIFCCG_DEBUG_REG2__req_active_verts__SHIFT 0x00000009 +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO2__SHIFT 0x00000010 +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx__SHIFT 0x00000011 +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO1__SHIFT 0x00000012 +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts__SHIFT 0x00000014 +#define SXIFCCG_DEBUG_REG2__ALWAYS_ZERO0__SHIFT 0x00000016 +#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded__SHIFT 0x0000001a +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_empty__SHIFT 0x0000001b +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_full__SHIFT 0x0000001c +#define SXIFCCG_DEBUG_REG2__sx_pending_fifo_contents__SHIFT 0x0000001d + +// SXIFCCG_DEBUG_REG3 +#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable__SHIFT 0x00000000 +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO3__SHIFT 0x00000004 +#define SXIFCCG_DEBUG_REG3__available_positions__SHIFT 0x00000005 +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO2__SHIFT 0x00000008 +#define SXIFCCG_DEBUG_REG3__current_state__SHIFT 0x0000000c +#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty__SHIFT 0x0000000e +#define SXIFCCG_DEBUG_REG3__vertex_fifo_full__SHIFT 0x0000000f +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO1__SHIFT 0x00000010 +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty__SHIFT 0x00000012 +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full__SHIFT 0x00000013 +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty__SHIFT 0x00000014 +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full__SHIFT 0x00000015 +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO0__SHIFT 0x00000016 + +// SETUP_DEBUG_REG0 +#define SETUP_DEBUG_REG0__su_cntl_state__SHIFT 0x00000000 +#define SETUP_DEBUG_REG0__pmode_state__SHIFT 0x00000005 +#define SETUP_DEBUG_REG0__ge_stallb__SHIFT 0x0000000b +#define SETUP_DEBUG_REG0__geom_enable__SHIFT 0x0000000c +#define SETUP_DEBUG_REG0__su_clip_baryc_rtr__SHIFT 0x0000000d +#define SETUP_DEBUG_REG0__su_clip_rtr__SHIFT 0x0000000e +#define SETUP_DEBUG_REG0__pfifo_busy__SHIFT 0x0000000f +#define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT 0x00000010 +#define SETUP_DEBUG_REG0__geom_busy__SHIFT 0x00000011 + +// SETUP_DEBUG_REG1 +#define SETUP_DEBUG_REG1__y_sort0_gated_17_4__SHIFT 0x00000000 +#define SETUP_DEBUG_REG1__x_sort0_gated_17_4__SHIFT 0x0000000e + +// SETUP_DEBUG_REG2 +#define SETUP_DEBUG_REG2__y_sort1_gated_17_4__SHIFT 0x00000000 +#define SETUP_DEBUG_REG2__x_sort1_gated_17_4__SHIFT 0x0000000e + +// SETUP_DEBUG_REG3 +#define SETUP_DEBUG_REG3__y_sort2_gated_17_4__SHIFT 0x00000000 +#define SETUP_DEBUG_REG3__x_sort2_gated_17_4__SHIFT 0x0000000e + +// SETUP_DEBUG_REG4 +#define SETUP_DEBUG_REG4__attr_indx_sort0_gated__SHIFT 0x00000000 +#define SETUP_DEBUG_REG4__null_prim_gated__SHIFT 0x0000000b +#define SETUP_DEBUG_REG4__backfacing_gated__SHIFT 0x0000000c +#define SETUP_DEBUG_REG4__st_indx_gated__SHIFT 0x0000000d +#define SETUP_DEBUG_REG4__clipped_gated__SHIFT 0x00000010 +#define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT 0x00000011 +#define SETUP_DEBUG_REG4__xmajor_gated__SHIFT 0x00000014 +#define SETUP_DEBUG_REG4__diamond_rule_gated__SHIFT 0x00000015 +#define SETUP_DEBUG_REG4__type_gated__SHIFT 0x00000017 +#define SETUP_DEBUG_REG4__fpov_gated__SHIFT 0x0000001a +#define SETUP_DEBUG_REG4__pmode_prim_gated__SHIFT 0x0000001b +#define SETUP_DEBUG_REG4__event_gated__SHIFT 0x0000001c +#define SETUP_DEBUG_REG4__eop_gated__SHIFT 0x0000001d + +// SETUP_DEBUG_REG5 +#define SETUP_DEBUG_REG5__attr_indx_sort2_gated__SHIFT 0x00000000 +#define SETUP_DEBUG_REG5__attr_indx_sort1_gated__SHIFT 0x0000000b +#define SETUP_DEBUG_REG5__provoking_vtx_gated__SHIFT 0x00000016 +#define SETUP_DEBUG_REG5__event_id_gated__SHIFT 0x00000018 + +// PA_SC_DEBUG_CNTL +#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT 0x00000000 + +// PA_SC_DEBUG_DATA +#define PA_SC_DEBUG_DATA__DATA__SHIFT 0x00000000 + +// SC_DEBUG_0 +#define SC_DEBUG_0__pa_freeze_b1__SHIFT 0x00000000 +#define SC_DEBUG_0__pa_sc_valid__SHIFT 0x00000001 +#define SC_DEBUG_0__pa_sc_phase__SHIFT 0x00000002 +#define SC_DEBUG_0__cntx_cnt__SHIFT 0x00000005 +#define SC_DEBUG_0__decr_cntx_cnt__SHIFT 0x0000000c +#define SC_DEBUG_0__incr_cntx_cnt__SHIFT 0x0000000d +#define SC_DEBUG_0__trigger__SHIFT 0x0000001f + +// SC_DEBUG_1 +#define SC_DEBUG_1__em_state__SHIFT 0x00000000 +#define SC_DEBUG_1__em1_data_ready__SHIFT 0x00000003 +#define SC_DEBUG_1__em2_data_ready__SHIFT 0x00000004 +#define SC_DEBUG_1__move_em1_to_em2__SHIFT 0x00000005 +#define SC_DEBUG_1__ef_data_ready__SHIFT 0x00000006 +#define SC_DEBUG_1__ef_state__SHIFT 0x00000007 +#define SC_DEBUG_1__pipe_valid__SHIFT 0x00000009 +#define SC_DEBUG_1__trigger__SHIFT 0x0000001f + +// SC_DEBUG_2 +#define SC_DEBUG_2__rc_rtr_dly__SHIFT 0x00000000 +#define SC_DEBUG_2__qmask_ff_alm_full_d1__SHIFT 0x00000001 +#define SC_DEBUG_2__pipe_freeze_b__SHIFT 0x00000003 +#define SC_DEBUG_2__prim_rts__SHIFT 0x00000004 +#define SC_DEBUG_2__next_prim_rts_dly__SHIFT 0x00000005 +#define SC_DEBUG_2__next_prim_rtr_dly__SHIFT 0x00000006 +#define SC_DEBUG_2__pre_stage1_rts_d1__SHIFT 0x00000007 +#define SC_DEBUG_2__stage0_rts__SHIFT 0x00000008 +#define SC_DEBUG_2__phase_rts_dly__SHIFT 0x00000009 +#define SC_DEBUG_2__end_of_prim_s1_dly__SHIFT 0x0000000f +#define SC_DEBUG_2__pass_empty_prim_s1__SHIFT 0x00000010 +#define SC_DEBUG_2__event_id_s1__SHIFT 0x00000011 +#define SC_DEBUG_2__event_s1__SHIFT 0x00000016 +#define SC_DEBUG_2__trigger__SHIFT 0x0000001f + +// SC_DEBUG_3 +#define SC_DEBUG_3__x_curr_s1__SHIFT 0x00000000 +#define SC_DEBUG_3__y_curr_s1__SHIFT 0x0000000b +#define SC_DEBUG_3__trigger__SHIFT 0x0000001f + +// SC_DEBUG_4 +#define SC_DEBUG_4__y_end_s1__SHIFT 0x00000000 +#define SC_DEBUG_4__y_start_s1__SHIFT 0x0000000e +#define SC_DEBUG_4__y_dir_s1__SHIFT 0x0000001c +#define SC_DEBUG_4__trigger__SHIFT 0x0000001f + +// SC_DEBUG_5 +#define SC_DEBUG_5__x_end_s1__SHIFT 0x00000000 +#define SC_DEBUG_5__x_start_s1__SHIFT 0x0000000e +#define SC_DEBUG_5__x_dir_s1__SHIFT 0x0000001c +#define SC_DEBUG_5__trigger__SHIFT 0x0000001f + +// SC_DEBUG_6 +#define SC_DEBUG_6__z_ff_empty__SHIFT 0x00000000 +#define SC_DEBUG_6__qmcntl_ff_empty__SHIFT 0x00000001 +#define SC_DEBUG_6__xy_ff_empty__SHIFT 0x00000002 +#define SC_DEBUG_6__event_flag__SHIFT 0x00000003 +#define SC_DEBUG_6__z_mask_needed__SHIFT 0x00000004 +#define SC_DEBUG_6__state__SHIFT 0x00000005 +#define SC_DEBUG_6__state_delayed__SHIFT 0x00000008 +#define SC_DEBUG_6__data_valid__SHIFT 0x0000000b +#define SC_DEBUG_6__data_valid_d__SHIFT 0x0000000c +#define SC_DEBUG_6__tilex_delayed__SHIFT 0x0000000d +#define SC_DEBUG_6__tiley_delayed__SHIFT 0x00000016 +#define SC_DEBUG_6__trigger__SHIFT 0x0000001f + +// SC_DEBUG_7 +#define SC_DEBUG_7__event_flag__SHIFT 0x00000000 +#define SC_DEBUG_7__deallocate__SHIFT 0x00000001 +#define SC_DEBUG_7__fposition__SHIFT 0x00000004 +#define SC_DEBUG_7__sr_prim_we__SHIFT 0x00000005 +#define SC_DEBUG_7__last_tile__SHIFT 0x00000006 +#define SC_DEBUG_7__tile_ff_we__SHIFT 0x00000007 +#define SC_DEBUG_7__qs_data_valid__SHIFT 0x00000008 +#define SC_DEBUG_7__qs_q0_y__SHIFT 0x00000009 +#define SC_DEBUG_7__qs_q0_x__SHIFT 0x0000000b +#define SC_DEBUG_7__qs_q0_valid__SHIFT 0x0000000d +#define SC_DEBUG_7__prim_ff_we__SHIFT 0x0000000e +#define SC_DEBUG_7__tile_ff_re__SHIFT 0x0000000f +#define SC_DEBUG_7__fw_prim_data_valid__SHIFT 0x00000010 +#define SC_DEBUG_7__last_quad_of_tile__SHIFT 0x00000011 +#define SC_DEBUG_7__first_quad_of_tile__SHIFT 0x00000012 +#define SC_DEBUG_7__first_quad_of_prim__SHIFT 0x00000013 +#define SC_DEBUG_7__new_prim__SHIFT 0x00000014 +#define SC_DEBUG_7__load_new_tile_data__SHIFT 0x00000015 +#define SC_DEBUG_7__state__SHIFT 0x00000016 +#define SC_DEBUG_7__fifos_ready__SHIFT 0x00000018 +#define SC_DEBUG_7__trigger__SHIFT 0x0000001f + +// SC_DEBUG_8 +#define SC_DEBUG_8__sample_last__SHIFT 0x00000000 +#define SC_DEBUG_8__sample_mask__SHIFT 0x00000001 +#define SC_DEBUG_8__sample_y__SHIFT 0x00000005 +#define SC_DEBUG_8__sample_x__SHIFT 0x00000007 +#define SC_DEBUG_8__sample_send__SHIFT 0x00000009 +#define SC_DEBUG_8__next_cycle__SHIFT 0x0000000a +#define SC_DEBUG_8__ez_sample_ff_full__SHIFT 0x0000000c +#define SC_DEBUG_8__rb_sc_samp_rtr__SHIFT 0x0000000d +#define SC_DEBUG_8__num_samples__SHIFT 0x0000000e +#define SC_DEBUG_8__last_quad_of_tile__SHIFT 0x00000010 +#define SC_DEBUG_8__last_quad_of_prim__SHIFT 0x00000011 +#define SC_DEBUG_8__first_quad_of_prim__SHIFT 0x00000012 +#define SC_DEBUG_8__sample_we__SHIFT 0x00000013 +#define SC_DEBUG_8__fposition__SHIFT 0x00000014 +#define SC_DEBUG_8__event_id__SHIFT 0x00000015 +#define SC_DEBUG_8__event_flag__SHIFT 0x0000001a +#define SC_DEBUG_8__fw_prim_data_valid__SHIFT 0x0000001b +#define SC_DEBUG_8__trigger__SHIFT 0x0000001f + +// SC_DEBUG_9 +#define SC_DEBUG_9__rb_sc_send__SHIFT 0x00000000 +#define SC_DEBUG_9__rb_sc_ez_mask__SHIFT 0x00000001 +#define SC_DEBUG_9__fifo_data_ready__SHIFT 0x00000005 +#define SC_DEBUG_9__early_z_enable__SHIFT 0x00000006 +#define SC_DEBUG_9__mask_state__SHIFT 0x00000007 +#define SC_DEBUG_9__next_ez_mask__SHIFT 0x00000009 +#define SC_DEBUG_9__mask_ready__SHIFT 0x00000019 +#define SC_DEBUG_9__drop_sample__SHIFT 0x0000001a +#define SC_DEBUG_9__fetch_new_sample_data__SHIFT 0x0000001b +#define SC_DEBUG_9__fetch_new_ez_sample_mask__SHIFT 0x0000001c +#define SC_DEBUG_9__pkr_fetch_new_sample_data__SHIFT 0x0000001d +#define SC_DEBUG_9__pkr_fetch_new_prim_data__SHIFT 0x0000001e +#define SC_DEBUG_9__trigger__SHIFT 0x0000001f + +// SC_DEBUG_10 +#define SC_DEBUG_10__combined_sample_mask__SHIFT 0x00000000 +#define SC_DEBUG_10__trigger__SHIFT 0x0000001f + +// SC_DEBUG_11 +#define SC_DEBUG_11__ez_sample_data_ready__SHIFT 0x00000000 +#define SC_DEBUG_11__pkr_fetch_new_sample_data__SHIFT 0x00000001 +#define SC_DEBUG_11__ez_prim_data_ready__SHIFT 0x00000002 +#define SC_DEBUG_11__pkr_fetch_new_prim_data__SHIFT 0x00000003 +#define SC_DEBUG_11__iterator_input_fz__SHIFT 0x00000004 +#define SC_DEBUG_11__packer_send_quads__SHIFT 0x00000005 +#define SC_DEBUG_11__packer_send_cmd__SHIFT 0x00000006 +#define SC_DEBUG_11__packer_send_event__SHIFT 0x00000007 +#define SC_DEBUG_11__next_state__SHIFT 0x00000008 +#define SC_DEBUG_11__state__SHIFT 0x0000000b +#define SC_DEBUG_11__stall__SHIFT 0x0000000e +#define SC_DEBUG_11__trigger__SHIFT 0x0000001f + +// SC_DEBUG_12 +#define SC_DEBUG_12__SQ_iterator_free_buff__SHIFT 0x00000000 +#define SC_DEBUG_12__event_id__SHIFT 0x00000001 +#define SC_DEBUG_12__event_flag__SHIFT 0x00000006 +#define SC_DEBUG_12__itercmdfifo_busy_nc_dly__SHIFT 0x00000007 +#define SC_DEBUG_12__itercmdfifo_full__SHIFT 0x00000008 +#define SC_DEBUG_12__itercmdfifo_empty__SHIFT 0x00000009 +#define SC_DEBUG_12__iter_ds_one_clk_command__SHIFT 0x0000000a +#define SC_DEBUG_12__iter_ds_end_of_prim0__SHIFT 0x0000000b +#define SC_DEBUG_12__iter_ds_end_of_vector__SHIFT 0x0000000c +#define SC_DEBUG_12__iter_qdhit0__SHIFT 0x0000000d +#define SC_DEBUG_12__bc_use_centers_reg__SHIFT 0x0000000e +#define SC_DEBUG_12__bc_output_xy_reg__SHIFT 0x0000000f +#define SC_DEBUG_12__iter_phase_out__SHIFT 0x00000010 +#define SC_DEBUG_12__iter_phase_reg__SHIFT 0x00000012 +#define SC_DEBUG_12__iterator_SP_valid__SHIFT 0x00000014 +#define SC_DEBUG_12__eopv_reg__SHIFT 0x00000015 +#define SC_DEBUG_12__one_clk_cmd_reg__SHIFT 0x00000016 +#define SC_DEBUG_12__iter_dx_end_of_prim__SHIFT 0x00000017 +#define SC_DEBUG_12__trigger__SHIFT 0x0000001f + +// GFX_COPY_STATE +#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x00000000 + +// VGT_DRAW_INITIATOR +#define VGT_DRAW_INITIATOR__PRIM_TYPE__SHIFT 0x00000000 +#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x00000006 +#define VGT_DRAW_INITIATOR__FACENESS_CULL_SELECT__SHIFT 0x00000008 +#define VGT_DRAW_INITIATOR__INDEX_SIZE__SHIFT 0x0000000b +#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x0000000c +#define VGT_DRAW_INITIATOR__SMALL_INDEX__SHIFT 0x0000000d +#define VGT_DRAW_INITIATOR__PRE_FETCH_CULL_ENABLE__SHIFT 0x0000000e +#define VGT_DRAW_INITIATOR__GRP_CULL_ENABLE__SHIFT 0x0000000f +#define VGT_DRAW_INITIATOR__NUM_INDICES__SHIFT 0x00000010 + +// VGT_EVENT_INITIATOR +#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x00000000 + +// VGT_DMA_BASE +#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x00000000 + +// VGT_DMA_SIZE +#define VGT_DMA_SIZE__NUM_WORDS__SHIFT 0x00000000 +#define VGT_DMA_SIZE__SWAP_MODE__SHIFT 0x0000001e + +// VGT_BIN_BASE +#define VGT_BIN_BASE__BIN_BASE_ADDR__SHIFT 0x00000000 + +// VGT_BIN_SIZE +#define VGT_BIN_SIZE__NUM_WORDS__SHIFT 0x00000000 +#define VGT_BIN_SIZE__FACENESS_FETCH__SHIFT 0x0000001e +#define VGT_BIN_SIZE__FACENESS_RESET__SHIFT 0x0000001f + +// VGT_CURRENT_BIN_ID_MIN +#define VGT_CURRENT_BIN_ID_MIN__COLUMN__SHIFT 0x00000000 +#define VGT_CURRENT_BIN_ID_MIN__ROW__SHIFT 0x00000003 +#define VGT_CURRENT_BIN_ID_MIN__GUARD_BAND__SHIFT 0x00000006 + +// VGT_CURRENT_BIN_ID_MAX +#define VGT_CURRENT_BIN_ID_MAX__COLUMN__SHIFT 0x00000000 +#define VGT_CURRENT_BIN_ID_MAX__ROW__SHIFT 0x00000003 +#define VGT_CURRENT_BIN_ID_MAX__GUARD_BAND__SHIFT 0x00000006 + +// VGT_IMMED_DATA +#define VGT_IMMED_DATA__DATA__SHIFT 0x00000000 + +// VGT_MAX_VTX_INDX +#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x00000000 + +// VGT_MIN_VTX_INDX +#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x00000000 + +// VGT_INDX_OFFSET +#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x00000000 + +// VGT_VERTEX_REUSE_BLOCK_CNTL +#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x00000000 + +// VGT_OUT_DEALLOC_CNTL +#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x00000000 + +// VGT_MULTI_PRIM_IB_RESET_INDX +#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x00000000 + +// VGT_ENHANCE +#define VGT_ENHANCE__MISC__SHIFT 0x00000000 + +// VGT_VTX_VECT_EJECT_REG +#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x00000000 + +// VGT_LAST_COPY_STATE +#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x00000000 +#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x00000010 + +// VGT_DEBUG_CNTL +#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX__SHIFT 0x00000000 + +// VGT_DEBUG_DATA +#define VGT_DEBUG_DATA__DATA__SHIFT 0x00000000 + +// VGT_CNTL_STATUS +#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x00000000 +#define VGT_CNTL_STATUS__VGT_DMA_BUSY__SHIFT 0x00000001 +#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY__SHIFT 0x00000002 +#define VGT_CNTL_STATUS__VGT_GRP_BUSY__SHIFT 0x00000003 +#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x00000004 +#define VGT_CNTL_STATUS__VGT_BIN_BUSY__SHIFT 0x00000005 +#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x00000006 +#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x00000007 +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x00000008 + +// VGT_DEBUG_REG0 +#define VGT_DEBUG_REG0__te_grp_busy__SHIFT 0x00000000 +#define VGT_DEBUG_REG0__pt_grp_busy__SHIFT 0x00000001 +#define VGT_DEBUG_REG0__vr_grp_busy__SHIFT 0x00000002 +#define VGT_DEBUG_REG0__dma_request_busy__SHIFT 0x00000003 +#define VGT_DEBUG_REG0__out_busy__SHIFT 0x00000004 +#define VGT_DEBUG_REG0__grp_backend_busy__SHIFT 0x00000005 +#define VGT_DEBUG_REG0__grp_busy__SHIFT 0x00000006 +#define VGT_DEBUG_REG0__dma_busy__SHIFT 0x00000007 +#define VGT_DEBUG_REG0__rbiu_dma_request_busy__SHIFT 0x00000008 +#define VGT_DEBUG_REG0__rbiu_busy__SHIFT 0x00000009 +#define VGT_DEBUG_REG0__vgt_no_dma_busy_extended__SHIFT 0x0000000a +#define VGT_DEBUG_REG0__vgt_no_dma_busy__SHIFT 0x0000000b +#define VGT_DEBUG_REG0__vgt_busy_extended__SHIFT 0x0000000c +#define VGT_DEBUG_REG0__vgt_busy__SHIFT 0x0000000d +#define VGT_DEBUG_REG0__rbbm_skid_fifo_busy_out__SHIFT 0x0000000e +#define VGT_DEBUG_REG0__VGT_RBBM_no_dma_busy__SHIFT 0x0000000f +#define VGT_DEBUG_REG0__VGT_RBBM_busy__SHIFT 0x00000010 + +// VGT_DEBUG_REG1 +#define VGT_DEBUG_REG1__out_te_data_read__SHIFT 0x00000000 +#define VGT_DEBUG_REG1__te_out_data_valid__SHIFT 0x00000001 +#define VGT_DEBUG_REG1__out_pt_prim_read__SHIFT 0x00000002 +#define VGT_DEBUG_REG1__pt_out_prim_valid__SHIFT 0x00000003 +#define VGT_DEBUG_REG1__out_pt_data_read__SHIFT 0x00000004 +#define VGT_DEBUG_REG1__pt_out_indx_valid__SHIFT 0x00000005 +#define VGT_DEBUG_REG1__out_vr_prim_read__SHIFT 0x00000006 +#define VGT_DEBUG_REG1__vr_out_prim_valid__SHIFT 0x00000007 +#define VGT_DEBUG_REG1__out_vr_indx_read__SHIFT 0x00000008 +#define VGT_DEBUG_REG1__vr_out_indx_valid__SHIFT 0x00000009 +#define VGT_DEBUG_REG1__te_grp_read__SHIFT 0x0000000a +#define VGT_DEBUG_REG1__grp_te_valid__SHIFT 0x0000000b +#define VGT_DEBUG_REG1__pt_grp_read__SHIFT 0x0000000c +#define VGT_DEBUG_REG1__grp_pt_valid__SHIFT 0x0000000d +#define VGT_DEBUG_REG1__vr_grp_read__SHIFT 0x0000000e +#define VGT_DEBUG_REG1__grp_vr_valid__SHIFT 0x0000000f +#define VGT_DEBUG_REG1__grp_dma_read__SHIFT 0x00000010 +#define VGT_DEBUG_REG1__dma_grp_valid__SHIFT 0x00000011 +#define VGT_DEBUG_REG1__grp_rbiu_di_read__SHIFT 0x00000012 +#define VGT_DEBUG_REG1__rbiu_grp_di_valid__SHIFT 0x00000013 +#define VGT_DEBUG_REG1__MH_VGT_rtr__SHIFT 0x00000014 +#define VGT_DEBUG_REG1__VGT_MH_send__SHIFT 0x00000015 +#define VGT_DEBUG_REG1__PA_VGT_clip_s_rtr__SHIFT 0x00000016 +#define VGT_DEBUG_REG1__VGT_PA_clip_s_send__SHIFT 0x00000017 +#define VGT_DEBUG_REG1__PA_VGT_clip_p_rtr__SHIFT 0x00000018 +#define VGT_DEBUG_REG1__VGT_PA_clip_p_send__SHIFT 0x00000019 +#define VGT_DEBUG_REG1__PA_VGT_clip_v_rtr__SHIFT 0x0000001a +#define VGT_DEBUG_REG1__VGT_PA_clip_v_send__SHIFT 0x0000001b +#define VGT_DEBUG_REG1__SQ_VGT_rtr__SHIFT 0x0000001c +#define VGT_DEBUG_REG1__VGT_SQ_send__SHIFT 0x0000001d +#define VGT_DEBUG_REG1__mh_vgt_tag_7_q__SHIFT 0x0000001e + +// VGT_DEBUG_REG3 +#define VGT_DEBUG_REG3__vgt_clk_en__SHIFT 0x00000000 +#define VGT_DEBUG_REG3__reg_fifos_clk_en__SHIFT 0x00000001 + +// VGT_DEBUG_REG6 +#define VGT_DEBUG_REG6__shifter_byte_count_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG6__right_word_indx_q__SHIFT 0x00000005 +#define VGT_DEBUG_REG6__input_data_valid__SHIFT 0x0000000a +#define VGT_DEBUG_REG6__input_data_xfer__SHIFT 0x0000000b +#define VGT_DEBUG_REG6__next_shift_is_vect_1_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG6__next_shift_is_vect_1_d__SHIFT 0x0000000d +#define VGT_DEBUG_REG6__next_shift_is_vect_1_pre_d__SHIFT 0x0000000e +#define VGT_DEBUG_REG6__space_avail_from_shift__SHIFT 0x0000000f +#define VGT_DEBUG_REG6__shifter_first_load__SHIFT 0x00000010 +#define VGT_DEBUG_REG6__di_state_sel_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG6__shifter_waiting_for_first_load_q__SHIFT 0x00000012 +#define VGT_DEBUG_REG6__di_first_group_flag_q__SHIFT 0x00000013 +#define VGT_DEBUG_REG6__di_event_flag_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG6__read_draw_initiator__SHIFT 0x00000015 +#define VGT_DEBUG_REG6__loading_di_requires_shifter__SHIFT 0x00000016 +#define VGT_DEBUG_REG6__last_shift_of_packet__SHIFT 0x00000017 +#define VGT_DEBUG_REG6__last_decr_of_packet__SHIFT 0x00000018 +#define VGT_DEBUG_REG6__extract_vector__SHIFT 0x00000019 +#define VGT_DEBUG_REG6__shift_vect_rtr__SHIFT 0x0000001a +#define VGT_DEBUG_REG6__destination_rtr__SHIFT 0x0000001b +#define VGT_DEBUG_REG6__grp_trigger__SHIFT 0x0000001c + +// VGT_DEBUG_REG7 +#define VGT_DEBUG_REG7__di_index_counter_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG7__shift_amount_no_extract__SHIFT 0x00000010 +#define VGT_DEBUG_REG7__shift_amount_extract__SHIFT 0x00000014 +#define VGT_DEBUG_REG7__di_prim_type_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG7__current_source_sel__SHIFT 0x0000001e + +// VGT_DEBUG_REG8 +#define VGT_DEBUG_REG8__current_source_sel__SHIFT 0x00000000 +#define VGT_DEBUG_REG8__left_word_indx_q__SHIFT 0x00000002 +#define VGT_DEBUG_REG8__input_data_cnt__SHIFT 0x00000007 +#define VGT_DEBUG_REG8__input_data_lsw__SHIFT 0x0000000c +#define VGT_DEBUG_REG8__input_data_msw__SHIFT 0x00000011 +#define VGT_DEBUG_REG8__next_small_stride_shift_limit_q__SHIFT 0x00000016 +#define VGT_DEBUG_REG8__current_small_stride_shift_limit_q__SHIFT 0x0000001b + +// VGT_DEBUG_REG9 +#define VGT_DEBUG_REG9__next_stride_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG9__next_stride_d__SHIFT 0x00000005 +#define VGT_DEBUG_REG9__current_shift_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG9__current_shift_d__SHIFT 0x0000000f +#define VGT_DEBUG_REG9__current_stride_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG9__current_stride_d__SHIFT 0x00000019 +#define VGT_DEBUG_REG9__grp_trigger__SHIFT 0x0000001e + +// VGT_DEBUG_REG10 +#define VGT_DEBUG_REG10__temp_derived_di_prim_type_t0__SHIFT 0x00000000 +#define VGT_DEBUG_REG10__temp_derived_di_small_index_t0__SHIFT 0x00000001 +#define VGT_DEBUG_REG10__temp_derived_di_cull_enable_t0__SHIFT 0x00000002 +#define VGT_DEBUG_REG10__temp_derived_di_pre_fetch_cull_enable_t0__SHIFT 0x00000003 +#define VGT_DEBUG_REG10__di_state_sel_q__SHIFT 0x00000004 +#define VGT_DEBUG_REG10__last_decr_of_packet__SHIFT 0x00000005 +#define VGT_DEBUG_REG10__bin_valid__SHIFT 0x00000006 +#define VGT_DEBUG_REG10__read_block__SHIFT 0x00000007 +#define VGT_DEBUG_REG10__grp_bgrp_last_bit_read__SHIFT 0x00000008 +#define VGT_DEBUG_REG10__last_bit_enable_q__SHIFT 0x00000009 +#define VGT_DEBUG_REG10__last_bit_end_di_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG10__selected_data__SHIFT 0x0000000b +#define VGT_DEBUG_REG10__mask_input_data__SHIFT 0x00000013 +#define VGT_DEBUG_REG10__gap_q__SHIFT 0x0000001b +#define VGT_DEBUG_REG10__temp_mini_reset_z__SHIFT 0x0000001c +#define VGT_DEBUG_REG10__temp_mini_reset_y__SHIFT 0x0000001d +#define VGT_DEBUG_REG10__temp_mini_reset_x__SHIFT 0x0000001e +#define VGT_DEBUG_REG10__grp_trigger__SHIFT 0x0000001f + +// VGT_DEBUG_REG12 +#define VGT_DEBUG_REG12__shifter_byte_count_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG12__right_word_indx_q__SHIFT 0x00000005 +#define VGT_DEBUG_REG12__input_data_valid__SHIFT 0x0000000a +#define VGT_DEBUG_REG12__input_data_xfer__SHIFT 0x0000000b +#define VGT_DEBUG_REG12__next_shift_is_vect_1_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG12__next_shift_is_vect_1_d__SHIFT 0x0000000d +#define VGT_DEBUG_REG12__next_shift_is_vect_1_pre_d__SHIFT 0x0000000e +#define VGT_DEBUG_REG12__space_avail_from_shift__SHIFT 0x0000000f +#define VGT_DEBUG_REG12__shifter_first_load__SHIFT 0x00000010 +#define VGT_DEBUG_REG12__di_state_sel_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG12__shifter_waiting_for_first_load_q__SHIFT 0x00000012 +#define VGT_DEBUG_REG12__di_first_group_flag_q__SHIFT 0x00000013 +#define VGT_DEBUG_REG12__di_event_flag_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG12__read_draw_initiator__SHIFT 0x00000015 +#define VGT_DEBUG_REG12__loading_di_requires_shifter__SHIFT 0x00000016 +#define VGT_DEBUG_REG12__last_shift_of_packet__SHIFT 0x00000017 +#define VGT_DEBUG_REG12__last_decr_of_packet__SHIFT 0x00000018 +#define VGT_DEBUG_REG12__extract_vector__SHIFT 0x00000019 +#define VGT_DEBUG_REG12__shift_vect_rtr__SHIFT 0x0000001a +#define VGT_DEBUG_REG12__destination_rtr__SHIFT 0x0000001b +#define VGT_DEBUG_REG12__bgrp_trigger__SHIFT 0x0000001c + +// VGT_DEBUG_REG13 +#define VGT_DEBUG_REG13__di_index_counter_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG13__shift_amount_no_extract__SHIFT 0x00000010 +#define VGT_DEBUG_REG13__shift_amount_extract__SHIFT 0x00000014 +#define VGT_DEBUG_REG13__di_prim_type_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG13__current_source_sel__SHIFT 0x0000001e + +// VGT_DEBUG_REG14 +#define VGT_DEBUG_REG14__current_source_sel__SHIFT 0x00000000 +#define VGT_DEBUG_REG14__left_word_indx_q__SHIFT 0x00000002 +#define VGT_DEBUG_REG14__input_data_cnt__SHIFT 0x00000007 +#define VGT_DEBUG_REG14__input_data_lsw__SHIFT 0x0000000c +#define VGT_DEBUG_REG14__input_data_msw__SHIFT 0x00000011 +#define VGT_DEBUG_REG14__next_small_stride_shift_limit_q__SHIFT 0x00000016 +#define VGT_DEBUG_REG14__current_small_stride_shift_limit_q__SHIFT 0x0000001b + +// VGT_DEBUG_REG15 +#define VGT_DEBUG_REG15__next_stride_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG15__next_stride_d__SHIFT 0x00000005 +#define VGT_DEBUG_REG15__current_shift_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG15__current_shift_d__SHIFT 0x0000000f +#define VGT_DEBUG_REG15__current_stride_q__SHIFT 0x00000014 +#define VGT_DEBUG_REG15__current_stride_d__SHIFT 0x00000019 +#define VGT_DEBUG_REG15__bgrp_trigger__SHIFT 0x0000001e + +// VGT_DEBUG_REG16 +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_full__SHIFT 0x00000000 +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_empty__SHIFT 0x00000001 +#define VGT_DEBUG_REG16__dma_bgrp_cull_fetch_read__SHIFT 0x00000002 +#define VGT_DEBUG_REG16__bgrp_cull_fetch_fifo_we__SHIFT 0x00000003 +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_full__SHIFT 0x00000004 +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_empty__SHIFT 0x00000005 +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_re_q__SHIFT 0x00000006 +#define VGT_DEBUG_REG16__bgrp_byte_mask_fifo_we__SHIFT 0x00000007 +#define VGT_DEBUG_REG16__bgrp_dma_mask_kill__SHIFT 0x00000008 +#define VGT_DEBUG_REG16__bgrp_grp_bin_valid__SHIFT 0x00000009 +#define VGT_DEBUG_REG16__rst_last_bit__SHIFT 0x0000000a +#define VGT_DEBUG_REG16__current_state_q__SHIFT 0x0000000b +#define VGT_DEBUG_REG16__old_state_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG16__old_state_en__SHIFT 0x0000000d +#define VGT_DEBUG_REG16__prev_last_bit_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG16__dbl_last_bit_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG16__last_bit_block_q__SHIFT 0x00000010 +#define VGT_DEBUG_REG16__ast_bit_block2_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG16__load_empty_reg__SHIFT 0x00000012 +#define VGT_DEBUG_REG16__bgrp_grp_byte_mask_rdata__SHIFT 0x00000013 +#define VGT_DEBUG_REG16__dma_bgrp_dma_data_fifo_rptr__SHIFT 0x0000001b +#define VGT_DEBUG_REG16__top_di_pre_fetch_cull_enable__SHIFT 0x0000001d +#define VGT_DEBUG_REG16__top_di_grp_cull_enable_q__SHIFT 0x0000001e +#define VGT_DEBUG_REG16__bgrp_trigger__SHIFT 0x0000001f + +// VGT_DEBUG_REG17 +#define VGT_DEBUG_REG17__save_read_q__SHIFT 0x00000000 +#define VGT_DEBUG_REG17__extend_read_q__SHIFT 0x00000001 +#define VGT_DEBUG_REG17__grp_indx_size__SHIFT 0x00000002 +#define VGT_DEBUG_REG17__cull_prim_true__SHIFT 0x00000004 +#define VGT_DEBUG_REG17__reset_bit2_q__SHIFT 0x00000005 +#define VGT_DEBUG_REG17__reset_bit1_q__SHIFT 0x00000006 +#define VGT_DEBUG_REG17__first_reg_first_q__SHIFT 0x00000007 +#define VGT_DEBUG_REG17__check_second_reg__SHIFT 0x00000008 +#define VGT_DEBUG_REG17__check_first_reg__SHIFT 0x00000009 +#define VGT_DEBUG_REG17__bgrp_cull_fetch_fifo_wdata__SHIFT 0x0000000a +#define VGT_DEBUG_REG17__save_cull_fetch_data2_q__SHIFT 0x0000000b +#define VGT_DEBUG_REG17__save_cull_fetch_data1_q__SHIFT 0x0000000c +#define VGT_DEBUG_REG17__save_byte_mask_data2_q__SHIFT 0x0000000d +#define VGT_DEBUG_REG17__save_byte_mask_data1_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG17__to_second_reg_q__SHIFT 0x0000000f +#define VGT_DEBUG_REG17__roll_over_msk_q__SHIFT 0x00000010 +#define VGT_DEBUG_REG17__max_msk_ptr_q__SHIFT 0x00000011 +#define VGT_DEBUG_REG17__min_msk_ptr_q__SHIFT 0x00000018 +#define VGT_DEBUG_REG17__bgrp_trigger__SHIFT 0x0000001f + +// VGT_DEBUG_REG18 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_raddr__SHIFT 0x00000000 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_waddr__SHIFT 0x00000006 +#define VGT_DEBUG_REG18__dma_bgrp_byte_mask_fifo_re__SHIFT 0x0000000c +#define VGT_DEBUG_REG18__dma_bgrp_dma_data_fifo_rptr__SHIFT 0x0000000d +#define VGT_DEBUG_REG18__dma_mem_full__SHIFT 0x0000000f +#define VGT_DEBUG_REG18__dma_ram_re__SHIFT 0x00000010 +#define VGT_DEBUG_REG18__dma_ram_we__SHIFT 0x00000011 +#define VGT_DEBUG_REG18__dma_mem_empty__SHIFT 0x00000012 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_re__SHIFT 0x00000013 +#define VGT_DEBUG_REG18__dma_data_fifo_mem_we__SHIFT 0x00000014 +#define VGT_DEBUG_REG18__bin_mem_full__SHIFT 0x00000015 +#define VGT_DEBUG_REG18__bin_ram_we__SHIFT 0x00000016 +#define VGT_DEBUG_REG18__bin_ram_re__SHIFT 0x00000017 +#define VGT_DEBUG_REG18__bin_mem_empty__SHIFT 0x00000018 +#define VGT_DEBUG_REG18__start_bin_req__SHIFT 0x00000019 +#define VGT_DEBUG_REG18__fetch_cull_not_used__SHIFT 0x0000001a +#define VGT_DEBUG_REG18__dma_req_xfer__SHIFT 0x0000001b +#define VGT_DEBUG_REG18__have_valid_bin_req__SHIFT 0x0000001c +#define VGT_DEBUG_REG18__have_valid_dma_req__SHIFT 0x0000001d +#define VGT_DEBUG_REG18__bgrp_dma_di_grp_cull_enable__SHIFT 0x0000001e +#define VGT_DEBUG_REG18__bgrp_dma_di_pre_fetch_cull_enable__SHIFT 0x0000001f + +// VGT_DEBUG_REG20 +#define VGT_DEBUG_REG20__prim_side_indx_valid__SHIFT 0x00000000 +#define VGT_DEBUG_REG20__indx_side_fifo_empty__SHIFT 0x00000001 +#define VGT_DEBUG_REG20__indx_side_fifo_re__SHIFT 0x00000002 +#define VGT_DEBUG_REG20__indx_side_fifo_we__SHIFT 0x00000003 +#define VGT_DEBUG_REG20__indx_side_fifo_full__SHIFT 0x00000004 +#define VGT_DEBUG_REG20__prim_buffer_empty__SHIFT 0x00000005 +#define VGT_DEBUG_REG20__prim_buffer_re__SHIFT 0x00000006 +#define VGT_DEBUG_REG20__prim_buffer_we__SHIFT 0x00000007 +#define VGT_DEBUG_REG20__prim_buffer_full__SHIFT 0x00000008 +#define VGT_DEBUG_REG20__indx_buffer_empty__SHIFT 0x00000009 +#define VGT_DEBUG_REG20__indx_buffer_re__SHIFT 0x0000000a +#define VGT_DEBUG_REG20__indx_buffer_we__SHIFT 0x0000000b +#define VGT_DEBUG_REG20__indx_buffer_full__SHIFT 0x0000000c +#define VGT_DEBUG_REG20__hold_prim__SHIFT 0x0000000d +#define VGT_DEBUG_REG20__sent_cnt__SHIFT 0x0000000e +#define VGT_DEBUG_REG20__start_of_vtx_vector__SHIFT 0x00000012 +#define VGT_DEBUG_REG20__clip_s_pre_hold_prim__SHIFT 0x00000013 +#define VGT_DEBUG_REG20__clip_p_pre_hold_prim__SHIFT 0x00000014 +#define VGT_DEBUG_REG20__buffered_prim_type_event__SHIFT 0x00000015 +#define VGT_DEBUG_REG20__out_trigger__SHIFT 0x0000001a + +// VGT_DEBUG_REG21 +#define VGT_DEBUG_REG21__null_terminate_vtx_vector__SHIFT 0x00000000 +#define VGT_DEBUG_REG21__prim_end_of_vtx_vect_flags__SHIFT 0x00000001 +#define VGT_DEBUG_REG21__alloc_counter_q__SHIFT 0x00000004 +#define VGT_DEBUG_REG21__curr_slot_in_vtx_vect_q__SHIFT 0x00000007 +#define VGT_DEBUG_REG21__int_vtx_counter_q__SHIFT 0x0000000a +#define VGT_DEBUG_REG21__curr_dealloc_distance_q__SHIFT 0x0000000e +#define VGT_DEBUG_REG21__new_packet_q__SHIFT 0x00000012 +#define VGT_DEBUG_REG21__new_allocate_q__SHIFT 0x00000013 +#define VGT_DEBUG_REG21__num_new_unique_rel_indx__SHIFT 0x00000014 +#define VGT_DEBUG_REG21__inserted_null_prim_q__SHIFT 0x00000016 +#define VGT_DEBUG_REG21__insert_null_prim__SHIFT 0x00000017 +#define VGT_DEBUG_REG21__buffered_prim_eop_mux__SHIFT 0x00000018 +#define VGT_DEBUG_REG21__prim_buffer_empty_mux__SHIFT 0x00000019 +#define VGT_DEBUG_REG21__buffered_thread_size__SHIFT 0x0000001a +#define VGT_DEBUG_REG21__out_trigger__SHIFT 0x0000001f + +// VGT_CRC_SQ_DATA +#define VGT_CRC_SQ_DATA__CRC__SHIFT 0x00000000 + +// VGT_CRC_SQ_CTRL +#define VGT_CRC_SQ_CTRL__CRC__SHIFT 0x00000000 + +// VGT_PERFCOUNTER0_SELECT +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// VGT_PERFCOUNTER1_SELECT +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 + +// VGT_PERFCOUNTER2_SELECT +#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 + +// VGT_PERFCOUNTER3_SELECT +#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 + +// VGT_PERFCOUNTER0_LOW +#define VGT_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER1_LOW +#define VGT_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER2_LOW +#define VGT_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER3_LOW +#define VGT_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER0_HI +#define VGT_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER1_HI +#define VGT_PERFCOUNTER1_HI__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER2_HI +#define VGT_PERFCOUNTER2_HI__PERF_COUNT__SHIFT 0x00000000 + +// VGT_PERFCOUNTER3_HI +#define VGT_PERFCOUNTER3_HI__PERF_COUNT__SHIFT 0x00000000 + +// TC_CNTL_STATUS +#define TC_CNTL_STATUS__L2_INVALIDATE__SHIFT 0x00000000 +#define TC_CNTL_STATUS__TC_L2_HIT_MISS__SHIFT 0x00000012 +#define TC_CNTL_STATUS__TC_BUSY__SHIFT 0x0000001f + +// TCR_CHICKEN +#define TCR_CHICKEN__SPARE__SHIFT 0x00000000 + +// TCF_CHICKEN +#define TCF_CHICKEN__SPARE__SHIFT 0x00000000 + +// TCM_CHICKEN +#define TCM_CHICKEN__TCO_READ_LATENCY_FIFO_PROG_DEPTH__SHIFT 0x00000000 +#define TCM_CHICKEN__ETC_COLOR_ENDIAN__SHIFT 0x00000008 +#define TCM_CHICKEN__SPARE__SHIFT 0x00000009 + +// TCR_PERFCOUNTER0_SELECT +#define TCR_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCR_PERFCOUNTER1_SELECT +#define TCR_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCR_PERFCOUNTER0_HI +#define TCR_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCR_PERFCOUNTER1_HI +#define TCR_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCR_PERFCOUNTER0_LOW +#define TCR_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCR_PERFCOUNTER1_LOW +#define TCR_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TP_TC_CLKGATE_CNTL +#define TP_TC_CLKGATE_CNTL__TP_BUSY_EXTEND__SHIFT 0x00000000 +#define TP_TC_CLKGATE_CNTL__TC_BUSY_EXTEND__SHIFT 0x00000003 + +// TPC_CNTL_STATUS +#define TPC_CNTL_STATUS__TPC_INPUT_BUSY__SHIFT 0x00000000 +#define TPC_CNTL_STATUS__TPC_TC_FIFO_BUSY__SHIFT 0x00000001 +#define TPC_CNTL_STATUS__TPC_STATE_FIFO_BUSY__SHIFT 0x00000002 +#define TPC_CNTL_STATUS__TPC_FETCH_FIFO_BUSY__SHIFT 0x00000003 +#define TPC_CNTL_STATUS__TPC_WALKER_PIPE_BUSY__SHIFT 0x00000004 +#define TPC_CNTL_STATUS__TPC_WALK_FIFO_BUSY__SHIFT 0x00000005 +#define TPC_CNTL_STATUS__TPC_WALKER_BUSY__SHIFT 0x00000006 +#define TPC_CNTL_STATUS__TPC_ALIGNER_PIPE_BUSY__SHIFT 0x00000008 +#define TPC_CNTL_STATUS__TPC_ALIGN_FIFO_BUSY__SHIFT 0x00000009 +#define TPC_CNTL_STATUS__TPC_ALIGNER_BUSY__SHIFT 0x0000000a +#define TPC_CNTL_STATUS__TPC_RR_FIFO_BUSY__SHIFT 0x0000000c +#define TPC_CNTL_STATUS__TPC_BLEND_PIPE_BUSY__SHIFT 0x0000000d +#define TPC_CNTL_STATUS__TPC_OUT_FIFO_BUSY__SHIFT 0x0000000e +#define TPC_CNTL_STATUS__TPC_BLEND_BUSY__SHIFT 0x0000000f +#define TPC_CNTL_STATUS__TF_TW_RTS__SHIFT 0x00000010 +#define TPC_CNTL_STATUS__TF_TW_STATE_RTS__SHIFT 0x00000011 +#define TPC_CNTL_STATUS__TF_TW_RTR__SHIFT 0x00000013 +#define TPC_CNTL_STATUS__TW_TA_RTS__SHIFT 0x00000014 +#define TPC_CNTL_STATUS__TW_TA_TT_RTS__SHIFT 0x00000015 +#define TPC_CNTL_STATUS__TW_TA_LAST_RTS__SHIFT 0x00000016 +#define TPC_CNTL_STATUS__TW_TA_RTR__SHIFT 0x00000017 +#define TPC_CNTL_STATUS__TA_TB_RTS__SHIFT 0x00000018 +#define TPC_CNTL_STATUS__TA_TB_TT_RTS__SHIFT 0x00000019 +#define TPC_CNTL_STATUS__TA_TB_RTR__SHIFT 0x0000001b +#define TPC_CNTL_STATUS__TA_TF_RTS__SHIFT 0x0000001c +#define TPC_CNTL_STATUS__TA_TF_TC_FIFO_REN__SHIFT 0x0000001d +#define TPC_CNTL_STATUS__TP_SQ_DEC__SHIFT 0x0000001e +#define TPC_CNTL_STATUS__TPC_BUSY__SHIFT 0x0000001f + +// TPC_DEBUG0 +#define TPC_DEBUG0__LOD_CNTL__SHIFT 0x00000000 +#define TPC_DEBUG0__IC_CTR__SHIFT 0x00000002 +#define TPC_DEBUG0__WALKER_CNTL__SHIFT 0x00000004 +#define TPC_DEBUG0__ALIGNER_CNTL__SHIFT 0x00000008 +#define TPC_DEBUG0__PREV_TC_STATE_VALID__SHIFT 0x0000000c +#define TPC_DEBUG0__WALKER_STATE__SHIFT 0x00000010 +#define TPC_DEBUG0__ALIGNER_STATE__SHIFT 0x0000001a +#define TPC_DEBUG0__REG_CLK_EN__SHIFT 0x0000001d +#define TPC_DEBUG0__TPC_CLK_EN__SHIFT 0x0000001e +#define TPC_DEBUG0__SQ_TP_WAKEUP__SHIFT 0x0000001f + +// TPC_DEBUG1 +#define TPC_DEBUG1__UNUSED__SHIFT 0x00000000 + +// TPC_CHICKEN +#define TPC_CHICKEN__BLEND_PRECISION__SHIFT 0x00000000 +#define TPC_CHICKEN__SPARE__SHIFT 0x00000001 + +// TP0_CNTL_STATUS +#define TP0_CNTL_STATUS__TP_INPUT_BUSY__SHIFT 0x00000000 +#define TP0_CNTL_STATUS__TP_LOD_BUSY__SHIFT 0x00000001 +#define TP0_CNTL_STATUS__TP_LOD_FIFO_BUSY__SHIFT 0x00000002 +#define TP0_CNTL_STATUS__TP_ADDR_BUSY__SHIFT 0x00000003 +#define TP0_CNTL_STATUS__TP_ALIGN_FIFO_BUSY__SHIFT 0x00000004 +#define TP0_CNTL_STATUS__TP_ALIGNER_BUSY__SHIFT 0x00000005 +#define TP0_CNTL_STATUS__TP_TC_FIFO_BUSY__SHIFT 0x00000006 +#define TP0_CNTL_STATUS__TP_RR_FIFO_BUSY__SHIFT 0x00000007 +#define TP0_CNTL_STATUS__TP_FETCH_BUSY__SHIFT 0x00000008 +#define TP0_CNTL_STATUS__TP_CH_BLEND_BUSY__SHIFT 0x00000009 +#define TP0_CNTL_STATUS__TP_TT_BUSY__SHIFT 0x0000000a +#define TP0_CNTL_STATUS__TP_HICOLOR_BUSY__SHIFT 0x0000000b +#define TP0_CNTL_STATUS__TP_BLEND_BUSY__SHIFT 0x0000000c +#define TP0_CNTL_STATUS__TP_OUT_FIFO_BUSY__SHIFT 0x0000000d +#define TP0_CNTL_STATUS__TP_OUTPUT_BUSY__SHIFT 0x0000000e +#define TP0_CNTL_STATUS__IN_LC_RTS__SHIFT 0x00000010 +#define TP0_CNTL_STATUS__LC_LA_RTS__SHIFT 0x00000011 +#define TP0_CNTL_STATUS__LA_FL_RTS__SHIFT 0x00000012 +#define TP0_CNTL_STATUS__FL_TA_RTS__SHIFT 0x00000013 +#define TP0_CNTL_STATUS__TA_FA_RTS__SHIFT 0x00000014 +#define TP0_CNTL_STATUS__TA_FA_TT_RTS__SHIFT 0x00000015 +#define TP0_CNTL_STATUS__FA_AL_RTS__SHIFT 0x00000016 +#define TP0_CNTL_STATUS__FA_AL_TT_RTS__SHIFT 0x00000017 +#define TP0_CNTL_STATUS__AL_TF_RTS__SHIFT 0x00000018 +#define TP0_CNTL_STATUS__AL_TF_TT_RTS__SHIFT 0x00000019 +#define TP0_CNTL_STATUS__TF_TB_RTS__SHIFT 0x0000001a +#define TP0_CNTL_STATUS__TF_TB_TT_RTS__SHIFT 0x0000001b +#define TP0_CNTL_STATUS__TB_TT_RTS__SHIFT 0x0000001c +#define TP0_CNTL_STATUS__TB_TT_TT_RESET__SHIFT 0x0000001d +#define TP0_CNTL_STATUS__TB_TO_RTS__SHIFT 0x0000001e +#define TP0_CNTL_STATUS__TP_BUSY__SHIFT 0x0000001f + +// TP0_DEBUG +#define TP0_DEBUG__Q_LOD_CNTL__SHIFT 0x00000000 +#define TP0_DEBUG__Q_SQ_TP_WAKEUP__SHIFT 0x00000003 +#define TP0_DEBUG__FL_TA_ADDRESSER_CNTL__SHIFT 0x00000004 +#define TP0_DEBUG__REG_CLK_EN__SHIFT 0x00000015 +#define TP0_DEBUG__PERF_CLK_EN__SHIFT 0x00000016 +#define TP0_DEBUG__TP_CLK_EN__SHIFT 0x00000017 +#define TP0_DEBUG__Q_WALKER_CNTL__SHIFT 0x00000018 +#define TP0_DEBUG__Q_ALIGNER_CNTL__SHIFT 0x0000001c + +// TP0_CHICKEN +#define TP0_CHICKEN__TT_MODE__SHIFT 0x00000000 +#define TP0_CHICKEN__VFETCH_ADDRESS_MODE__SHIFT 0x00000001 +#define TP0_CHICKEN__SPARE__SHIFT 0x00000002 + +// TP0_PERFCOUNTER0_SELECT +#define TP0_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TP0_PERFCOUNTER0_HI +#define TP0_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TP0_PERFCOUNTER0_LOW +#define TP0_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TP0_PERFCOUNTER1_SELECT +#define TP0_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TP0_PERFCOUNTER1_HI +#define TP0_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TP0_PERFCOUNTER1_LOW +#define TP0_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCM_PERFCOUNTER0_SELECT +#define TCM_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCM_PERFCOUNTER1_SELECT +#define TCM_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCM_PERFCOUNTER0_HI +#define TCM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCM_PERFCOUNTER1_HI +#define TCM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCM_PERFCOUNTER0_LOW +#define TCM_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCM_PERFCOUNTER1_LOW +#define TCM_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER0_SELECT +#define TCF_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER1_SELECT +#define TCF_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER2_SELECT +#define TCF_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER3_SELECT +#define TCF_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER4_SELECT +#define TCF_PERFCOUNTER4_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER5_SELECT +#define TCF_PERFCOUNTER5_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER6_SELECT +#define TCF_PERFCOUNTER6_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER7_SELECT +#define TCF_PERFCOUNTER7_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER8_SELECT +#define TCF_PERFCOUNTER8_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER9_SELECT +#define TCF_PERFCOUNTER9_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER10_SELECT +#define TCF_PERFCOUNTER10_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER11_SELECT +#define TCF_PERFCOUNTER11_SELECT__PERFCOUNTER_SELECT__SHIFT 0x00000000 + +// TCF_PERFCOUNTER0_HI +#define TCF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER1_HI +#define TCF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER2_HI +#define TCF_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER3_HI +#define TCF_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER4_HI +#define TCF_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER5_HI +#define TCF_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER6_HI +#define TCF_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER7_HI +#define TCF_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER8_HI +#define TCF_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER9_HI +#define TCF_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER10_HI +#define TCF_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER11_HI +#define TCF_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x00000000 + +// TCF_PERFCOUNTER0_LOW +#define TCF_PERFCOUNTER0_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER1_LOW +#define TCF_PERFCOUNTER1_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER2_LOW +#define TCF_PERFCOUNTER2_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER3_LOW +#define TCF_PERFCOUNTER3_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER4_LOW +#define TCF_PERFCOUNTER4_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER5_LOW +#define TCF_PERFCOUNTER5_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER6_LOW +#define TCF_PERFCOUNTER6_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER7_LOW +#define TCF_PERFCOUNTER7_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER8_LOW +#define TCF_PERFCOUNTER8_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER9_LOW +#define TCF_PERFCOUNTER9_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER10_LOW +#define TCF_PERFCOUNTER10_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_PERFCOUNTER11_LOW +#define TCF_PERFCOUNTER11_LOW__PERFCOUNTER_LOW__SHIFT 0x00000000 + +// TCF_DEBUG +#define TCF_DEBUG__not_MH_TC_rtr__SHIFT 0x00000006 +#define TCF_DEBUG__TC_MH_send__SHIFT 0x00000007 +#define TCF_DEBUG__not_FG0_rtr__SHIFT 0x00000008 +#define TCF_DEBUG__not_TCB_TCO_rtr__SHIFT 0x0000000c +#define TCF_DEBUG__TCB_ff_stall__SHIFT 0x0000000d +#define TCF_DEBUG__TCB_miss_stall__SHIFT 0x0000000e +#define TCF_DEBUG__TCA_TCB_stall__SHIFT 0x0000000f +#define TCF_DEBUG__PF0_stall__SHIFT 0x00000010 +#define TCF_DEBUG__TP0_full__SHIFT 0x00000014 +#define TCF_DEBUG__TPC_full__SHIFT 0x00000018 +#define TCF_DEBUG__not_TPC_rtr__SHIFT 0x00000019 +#define TCF_DEBUG__tca_state_rts__SHIFT 0x0000001a +#define TCF_DEBUG__tca_rts__SHIFT 0x0000001b + +// TCA_FIFO_DEBUG +#define TCA_FIFO_DEBUG__tp0_full__SHIFT 0x00000000 +#define TCA_FIFO_DEBUG__tpc_full__SHIFT 0x00000004 +#define TCA_FIFO_DEBUG__load_tpc_fifo__SHIFT 0x00000005 +#define TCA_FIFO_DEBUG__load_tp_fifos__SHIFT 0x00000006 +#define TCA_FIFO_DEBUG__FW_full__SHIFT 0x00000007 +#define TCA_FIFO_DEBUG__not_FW_rtr0__SHIFT 0x00000008 +#define TCA_FIFO_DEBUG__FW_rts0__SHIFT 0x0000000c +#define TCA_FIFO_DEBUG__not_FW_tpc_rtr__SHIFT 0x00000010 +#define TCA_FIFO_DEBUG__FW_tpc_rts__SHIFT 0x00000011 + +// TCA_PROBE_DEBUG +#define TCA_PROBE_DEBUG__ProbeFilter_stall__SHIFT 0x00000000 + +// TCA_TPC_DEBUG +#define TCA_TPC_DEBUG__captue_state_rts__SHIFT 0x0000000c +#define TCA_TPC_DEBUG__capture_tca_rts__SHIFT 0x0000000d + +// TCB_CORE_DEBUG +#define TCB_CORE_DEBUG__access512__SHIFT 0x00000000 +#define TCB_CORE_DEBUG__tiled__SHIFT 0x00000001 +#define TCB_CORE_DEBUG__opcode__SHIFT 0x00000004 +#define TCB_CORE_DEBUG__format__SHIFT 0x00000008 +#define TCB_CORE_DEBUG__sector_format__SHIFT 0x00000010 +#define TCB_CORE_DEBUG__sector_format512__SHIFT 0x00000018 + +// TCB_TAG0_DEBUG +#define TCB_TAG0_DEBUG__mem_read_cycle__SHIFT 0x00000000 +#define TCB_TAG0_DEBUG__tag_access_cycle__SHIFT 0x0000000c +#define TCB_TAG0_DEBUG__miss_stall__SHIFT 0x00000017 +#define TCB_TAG0_DEBUG__num_feee_lines__SHIFT 0x00000018 +#define TCB_TAG0_DEBUG__max_misses__SHIFT 0x0000001d + +// TCB_TAG1_DEBUG +#define TCB_TAG1_DEBUG__mem_read_cycle__SHIFT 0x00000000 +#define TCB_TAG1_DEBUG__tag_access_cycle__SHIFT 0x0000000c +#define TCB_TAG1_DEBUG__miss_stall__SHIFT 0x00000017 +#define TCB_TAG1_DEBUG__num_feee_lines__SHIFT 0x00000018 +#define TCB_TAG1_DEBUG__max_misses__SHIFT 0x0000001d + +// TCB_TAG2_DEBUG +#define TCB_TAG2_DEBUG__mem_read_cycle__SHIFT 0x00000000 +#define TCB_TAG2_DEBUG__tag_access_cycle__SHIFT 0x0000000c +#define TCB_TAG2_DEBUG__miss_stall__SHIFT 0x00000017 +#define TCB_TAG2_DEBUG__num_feee_lines__SHIFT 0x00000018 +#define TCB_TAG2_DEBUG__max_misses__SHIFT 0x0000001d + +// TCB_TAG3_DEBUG +#define TCB_TAG3_DEBUG__mem_read_cycle__SHIFT 0x00000000 +#define TCB_TAG3_DEBUG__tag_access_cycle__SHIFT 0x0000000c +#define TCB_TAG3_DEBUG__miss_stall__SHIFT 0x00000017 +#define TCB_TAG3_DEBUG__num_feee_lines__SHIFT 0x00000018 +#define TCB_TAG3_DEBUG__max_misses__SHIFT 0x0000001d + +// TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__left_done__SHIFT 0x00000000 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__fg0_sends_left__SHIFT 0x00000002 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__one_sector_to_go_left_q__SHIFT 0x00000004 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__no_sectors_to_go__SHIFT 0x00000005 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__update_left__SHIFT 0x00000006 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_count_q__SHIFT 0x00000007 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__sector_mask_left_q__SHIFT 0x0000000c +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG__valid_left_q__SHIFT 0x0000001c + +// TCB_FETCH_GEN_WALKER_DEBUG +#define TCB_FETCH_GEN_WALKER_DEBUG__quad_sel_left__SHIFT 0x00000004 +#define TCB_FETCH_GEN_WALKER_DEBUG__set_sel_left__SHIFT 0x00000006 +#define TCB_FETCH_GEN_WALKER_DEBUG__right_eq_left__SHIFT 0x0000000b +#define TCB_FETCH_GEN_WALKER_DEBUG__ff_fg_type512__SHIFT 0x0000000c +#define TCB_FETCH_GEN_WALKER_DEBUG__busy__SHIFT 0x0000000f +#define TCB_FETCH_GEN_WALKER_DEBUG__setquads_to_send__SHIFT 0x00000010 + +// TCB_FETCH_GEN_PIPE0_DEBUG +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc0_arb_rts__SHIFT 0x00000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_out_rts__SHIFT 0x00000002 +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_format__SHIFT 0x00000004 +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_fmsopcode__SHIFT 0x00000010 +#define TCB_FETCH_GEN_PIPE0_DEBUG__tc_arb_request_type__SHIFT 0x00000015 +#define TCB_FETCH_GEN_PIPE0_DEBUG__busy__SHIFT 0x00000017 +#define TCB_FETCH_GEN_PIPE0_DEBUG__fgo_busy__SHIFT 0x00000018 +#define TCB_FETCH_GEN_PIPE0_DEBUG__ga_busy__SHIFT 0x00000019 +#define TCB_FETCH_GEN_PIPE0_DEBUG__mc_sel_q__SHIFT 0x0000001a +#define TCB_FETCH_GEN_PIPE0_DEBUG__valid_q__SHIFT 0x0000001c +#define TCB_FETCH_GEN_PIPE0_DEBUG__arb_RTR__SHIFT 0x0000001e + +// TCD_INPUT0_DEBUG +#define TCD_INPUT0_DEBUG__empty__SHIFT 0x00000010 +#define TCD_INPUT0_DEBUG__full__SHIFT 0x00000011 +#define TCD_INPUT0_DEBUG__valid_q1__SHIFT 0x00000014 +#define TCD_INPUT0_DEBUG__cnt_q1__SHIFT 0x00000015 +#define TCD_INPUT0_DEBUG__last_send_q1__SHIFT 0x00000017 +#define TCD_INPUT0_DEBUG__ip_send__SHIFT 0x00000018 +#define TCD_INPUT0_DEBUG__ipbuf_dxt_send__SHIFT 0x00000019 +#define TCD_INPUT0_DEBUG__ipbuf_busy__SHIFT 0x0000001a + +// TCD_DEGAMMA_DEBUG +#define TCD_DEGAMMA_DEBUG__dgmm_ftfconv_dgmmen__SHIFT 0x00000000 +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_dgmm8__SHIFT 0x00000002 +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_last_send__SHIFT 0x00000003 +#define TCD_DEGAMMA_DEBUG__dgmm_ctrl_send__SHIFT 0x00000004 +#define TCD_DEGAMMA_DEBUG__dgmm_stall__SHIFT 0x00000005 +#define TCD_DEGAMMA_DEBUG__dgmm_pstate__SHIFT 0x00000006 + +// TCD_DXTMUX_SCTARB_DEBUG +#define TCD_DXTMUX_SCTARB_DEBUG__pstate__SHIFT 0x00000009 +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx_rtr__SHIFT 0x0000000a +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_rtr__SHIFT 0x0000000b +#define TCD_DXTMUX_SCTARB_DEBUG__sctrarb_multcyl_send__SHIFT 0x0000000f +#define TCD_DXTMUX_SCTARB_DEBUG__sctrmx0_sctrarb_rts__SHIFT 0x00000010 +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_sctrarb_send__SHIFT 0x00000014 +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_last_send__SHIFT 0x0000001b +#define TCD_DXTMUX_SCTARB_DEBUG__dxtc_dgmmpd_send__SHIFT 0x0000001c +#define TCD_DXTMUX_SCTARB_DEBUG__dcmp_mux_send__SHIFT 0x0000001d + +// TCD_DXTC_ARB_DEBUG +#define TCD_DXTC_ARB_DEBUG__n0_stall__SHIFT 0x00000004 +#define TCD_DXTC_ARB_DEBUG__pstate__SHIFT 0x00000005 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_last_send__SHIFT 0x00000006 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cnt__SHIFT 0x00000007 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_sector__SHIFT 0x00000009 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_cacheline__SHIFT 0x0000000c +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_format__SHIFT 0x00000012 +#define TCD_DXTC_ARB_DEBUG__arb_dcmp01_send__SHIFT 0x0000001e +#define TCD_DXTC_ARB_DEBUG__n0_dxt2_4_types__SHIFT 0x0000001f + +// TCD_STALLS_DEBUG +#define TCD_STALLS_DEBUG__not_multcyl_sctrarb_rtr__SHIFT 0x0000000a +#define TCD_STALLS_DEBUG__not_sctrmx0_sctrarb_rtr__SHIFT 0x0000000b +#define TCD_STALLS_DEBUG__not_dcmp0_arb_rtr__SHIFT 0x00000011 +#define TCD_STALLS_DEBUG__not_dgmmpd_dxtc_rtr__SHIFT 0x00000012 +#define TCD_STALLS_DEBUG__not_mux_dcmp_rtr__SHIFT 0x00000013 +#define TCD_STALLS_DEBUG__not_incoming_rtr__SHIFT 0x0000001f + +// TCO_STALLS_DEBUG +#define TCO_STALLS_DEBUG__quad0_sg_crd_RTR__SHIFT 0x00000005 +#define TCO_STALLS_DEBUG__quad0_rl_sg_RTR__SHIFT 0x00000006 +#define TCO_STALLS_DEBUG__quad0_TCO_TCB_rtr_d__SHIFT 0x00000007 + +// TCO_QUAD0_DEBUG0 +#define TCO_QUAD0_DEBUG0__rl_sg_sector_format__SHIFT 0x00000000 +#define TCO_QUAD0_DEBUG0__rl_sg_end_of_sample__SHIFT 0x00000008 +#define TCO_QUAD0_DEBUG0__rl_sg_rtr__SHIFT 0x00000009 +#define TCO_QUAD0_DEBUG0__rl_sg_rts__SHIFT 0x0000000a +#define TCO_QUAD0_DEBUG0__sg_crd_end_of_sample__SHIFT 0x0000000b +#define TCO_QUAD0_DEBUG0__sg_crd_rtr__SHIFT 0x0000000c +#define TCO_QUAD0_DEBUG0__sg_crd_rts__SHIFT 0x0000000d +#define TCO_QUAD0_DEBUG0__stageN1_valid_q__SHIFT 0x00000010 +#define TCO_QUAD0_DEBUG0__read_cache_q__SHIFT 0x00000018 +#define TCO_QUAD0_DEBUG0__cache_read_RTR__SHIFT 0x00000019 +#define TCO_QUAD0_DEBUG0__all_sectors_written_set3__SHIFT 0x0000001a +#define TCO_QUAD0_DEBUG0__all_sectors_written_set2__SHIFT 0x0000001b +#define TCO_QUAD0_DEBUG0__all_sectors_written_set1__SHIFT 0x0000001c +#define TCO_QUAD0_DEBUG0__all_sectors_written_set0__SHIFT 0x0000001d +#define TCO_QUAD0_DEBUG0__busy__SHIFT 0x0000001e + +// TCO_QUAD0_DEBUG1 +#define TCO_QUAD0_DEBUG1__fifo_busy__SHIFT 0x00000000 +#define TCO_QUAD0_DEBUG1__empty__SHIFT 0x00000001 +#define TCO_QUAD0_DEBUG1__full__SHIFT 0x00000002 +#define TCO_QUAD0_DEBUG1__write_enable__SHIFT 0x00000003 +#define TCO_QUAD0_DEBUG1__fifo_write_ptr__SHIFT 0x00000004 +#define TCO_QUAD0_DEBUG1__fifo_read_ptr__SHIFT 0x0000000b +#define TCO_QUAD0_DEBUG1__cache_read_busy__SHIFT 0x00000014 +#define TCO_QUAD0_DEBUG1__latency_fifo_busy__SHIFT 0x00000015 +#define TCO_QUAD0_DEBUG1__input_quad_busy__SHIFT 0x00000016 +#define TCO_QUAD0_DEBUG1__tco_quad_pipe_busy__SHIFT 0x00000017 +#define TCO_QUAD0_DEBUG1__TCB_TCO_rtr_d__SHIFT 0x00000018 +#define TCO_QUAD0_DEBUG1__TCB_TCO_xfc_q__SHIFT 0x00000019 +#define TCO_QUAD0_DEBUG1__rl_sg_rtr__SHIFT 0x0000001a +#define TCO_QUAD0_DEBUG1__rl_sg_rts__SHIFT 0x0000001b +#define TCO_QUAD0_DEBUG1__sg_crd_rtr__SHIFT 0x0000001c +#define TCO_QUAD0_DEBUG1__sg_crd_rts__SHIFT 0x0000001d +#define TCO_QUAD0_DEBUG1__TCO_TCB_read_xfc__SHIFT 0x0000001e + +// SQ_GPR_MANAGEMENT +#define SQ_GPR_MANAGEMENT__REG_DYNAMIC__SHIFT 0x00000000 +#define SQ_GPR_MANAGEMENT__REG_SIZE_PIX__SHIFT 0x00000004 +#define SQ_GPR_MANAGEMENT__REG_SIZE_VTX__SHIFT 0x0000000c + +// SQ_FLOW_CONTROL +#define SQ_FLOW_CONTROL__INPUT_ARBITRATION_POLICY__SHIFT 0x00000000 +#define SQ_FLOW_CONTROL__ONE_THREAD__SHIFT 0x00000004 +#define SQ_FLOW_CONTROL__ONE_ALU__SHIFT 0x00000008 +#define SQ_FLOW_CONTROL__CF_WR_BASE__SHIFT 0x0000000c +#define SQ_FLOW_CONTROL__NO_PV_PS__SHIFT 0x00000010 +#define SQ_FLOW_CONTROL__NO_LOOP_EXIT__SHIFT 0x00000011 +#define SQ_FLOW_CONTROL__NO_CEXEC_OPTIMIZE__SHIFT 0x00000012 +#define SQ_FLOW_CONTROL__TEXTURE_ARBITRATION_POLICY__SHIFT 0x00000013 +#define SQ_FLOW_CONTROL__VC_ARBITRATION_POLICY__SHIFT 0x00000015 +#define SQ_FLOW_CONTROL__ALU_ARBITRATION_POLICY__SHIFT 0x00000016 +#define SQ_FLOW_CONTROL__NO_ARB_EJECT__SHIFT 0x00000017 +#define SQ_FLOW_CONTROL__NO_CFS_EJECT__SHIFT 0x00000018 +#define SQ_FLOW_CONTROL__POS_EXP_PRIORITY__SHIFT 0x00000019 +#define SQ_FLOW_CONTROL__NO_EARLY_THREAD_TERMINATION__SHIFT 0x0000001a +#define SQ_FLOW_CONTROL__PS_PREFETCH_COLOR_ALLOC__SHIFT 0x0000001b + +// SQ_INST_STORE_MANAGMENT +#define SQ_INST_STORE_MANAGMENT__INST_BASE_PIX__SHIFT 0x00000000 +#define SQ_INST_STORE_MANAGMENT__INST_BASE_VTX__SHIFT 0x00000010 + +// SQ_RESOURCE_MANAGMENT +#define SQ_RESOURCE_MANAGMENT__VTX_THREAD_BUF_ENTRIES__SHIFT 0x00000000 +#define SQ_RESOURCE_MANAGMENT__PIX_THREAD_BUF_ENTRIES__SHIFT 0x00000008 +#define SQ_RESOURCE_MANAGMENT__EXPORT_BUF_ENTRIES__SHIFT 0x00000010 + +// SQ_EO_RT +#define SQ_EO_RT__EO_CONSTANTS_RT__SHIFT 0x00000000 +#define SQ_EO_RT__EO_TSTATE_RT__SHIFT 0x00000010 + +// SQ_DEBUG_MISC +#define SQ_DEBUG_MISC__DB_ALUCST_SIZE__SHIFT 0x00000000 +#define SQ_DEBUG_MISC__DB_TSTATE_SIZE__SHIFT 0x0000000c +#define SQ_DEBUG_MISC__DB_READ_CTX__SHIFT 0x00000014 +#define SQ_DEBUG_MISC__RESERVED__SHIFT 0x00000015 +#define SQ_DEBUG_MISC__DB_READ_MEMORY__SHIFT 0x00000017 +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_0__SHIFT 0x00000019 +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_1__SHIFT 0x0000001a +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_2__SHIFT 0x0000001b +#define SQ_DEBUG_MISC__DB_WEN_MEMORY_3__SHIFT 0x0000001c + +// SQ_ACTIVITY_METER_CNTL +#define SQ_ACTIVITY_METER_CNTL__TIMEBASE__SHIFT 0x00000000 +#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_LOW__SHIFT 0x00000008 +#define SQ_ACTIVITY_METER_CNTL__THRESHOLD_HIGH__SHIFT 0x00000010 +#define SQ_ACTIVITY_METER_CNTL__SPARE__SHIFT 0x00000018 + +// SQ_ACTIVITY_METER_STATUS +#define SQ_ACTIVITY_METER_STATUS__PERCENT_BUSY__SHIFT 0x00000000 + +// SQ_INPUT_ARB_PRIORITY +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_WEIGHT__SHIFT 0x00000000 +#define SQ_INPUT_ARB_PRIORITY__PC_AVAIL_SIGN__SHIFT 0x00000003 +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_WEIGHT__SHIFT 0x00000004 +#define SQ_INPUT_ARB_PRIORITY__SX_AVAIL_SIGN__SHIFT 0x00000007 +#define SQ_INPUT_ARB_PRIORITY__THRESHOLD__SHIFT 0x00000008 + +// SQ_THREAD_ARB_PRIORITY +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_WEIGHT__SHIFT 0x00000000 +#define SQ_THREAD_ARB_PRIORITY__PC_AVAIL_SIGN__SHIFT 0x00000003 +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_WEIGHT__SHIFT 0x00000004 +#define SQ_THREAD_ARB_PRIORITY__SX_AVAIL_SIGN__SHIFT 0x00000007 +#define SQ_THREAD_ARB_PRIORITY__THRESHOLD__SHIFT 0x00000008 +#define SQ_THREAD_ARB_PRIORITY__RESERVED__SHIFT 0x00000012 +#define SQ_THREAD_ARB_PRIORITY__VS_PRIORITIZE_SERIAL__SHIFT 0x00000014 +#define SQ_THREAD_ARB_PRIORITY__PS_PRIORITIZE_SERIAL__SHIFT 0x00000015 +#define SQ_THREAD_ARB_PRIORITY__USE_SERIAL_COUNT_THRESHOLD__SHIFT 0x00000016 + +// SQ_VS_WATCHDOG_TIMER +#define SQ_VS_WATCHDOG_TIMER__ENABLE__SHIFT 0x00000000 +#define SQ_VS_WATCHDOG_TIMER__TIMEOUT_COUNT__SHIFT 0x00000001 + +// SQ_PS_WATCHDOG_TIMER +#define SQ_PS_WATCHDOG_TIMER__ENABLE__SHIFT 0x00000000 +#define SQ_PS_WATCHDOG_TIMER__TIMEOUT_COUNT__SHIFT 0x00000001 + +// SQ_INT_CNTL +#define SQ_INT_CNTL__PS_WATCHDOG_MASK__SHIFT 0x00000000 +#define SQ_INT_CNTL__VS_WATCHDOG_MASK__SHIFT 0x00000001 + +// SQ_INT_STATUS +#define SQ_INT_STATUS__PS_WATCHDOG_TIMEOUT__SHIFT 0x00000000 +#define SQ_INT_STATUS__VS_WATCHDOG_TIMEOUT__SHIFT 0x00000001 + +// SQ_INT_ACK +#define SQ_INT_ACK__PS_WATCHDOG_ACK__SHIFT 0x00000000 +#define SQ_INT_ACK__VS_WATCHDOG_ACK__SHIFT 0x00000001 + +// SQ_DEBUG_INPUT_FSM +#define SQ_DEBUG_INPUT_FSM__VC_VSR_LD__SHIFT 0x00000000 +#define SQ_DEBUG_INPUT_FSM__RESERVED__SHIFT 0x00000003 +#define SQ_DEBUG_INPUT_FSM__VC_GPR_LD__SHIFT 0x00000004 +#define SQ_DEBUG_INPUT_FSM__PC_PISM__SHIFT 0x00000008 +#define SQ_DEBUG_INPUT_FSM__RESERVED1__SHIFT 0x0000000b +#define SQ_DEBUG_INPUT_FSM__PC_AS__SHIFT 0x0000000c +#define SQ_DEBUG_INPUT_FSM__PC_INTERP_CNT__SHIFT 0x0000000f +#define SQ_DEBUG_INPUT_FSM__PC_GPR_SIZE__SHIFT 0x00000014 + +// SQ_DEBUG_CONST_MGR_FSM +#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_EVENT_STATE__SHIFT 0x00000000 +#define SQ_DEBUG_CONST_MGR_FSM__RESERVED1__SHIFT 0x00000005 +#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_EVENT_STATE__SHIFT 0x00000008 +#define SQ_DEBUG_CONST_MGR_FSM__RESERVED2__SHIFT 0x0000000d +#define SQ_DEBUG_CONST_MGR_FSM__ALU_CONST_CNTX_VALID__SHIFT 0x00000010 +#define SQ_DEBUG_CONST_MGR_FSM__TEX_CONST_CNTX_VALID__SHIFT 0x00000012 +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_VTX_EVENT_DONE__SHIFT 0x00000014 +#define SQ_DEBUG_CONST_MGR_FSM__CNTX0_PIX_EVENT_DONE__SHIFT 0x00000015 +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_VTX_EVENT_DONE__SHIFT 0x00000016 +#define SQ_DEBUG_CONST_MGR_FSM__CNTX1_PIX_EVENT_DONE__SHIFT 0x00000017 + +// SQ_DEBUG_TP_FSM +#define SQ_DEBUG_TP_FSM__EX_TP__SHIFT 0x00000000 +#define SQ_DEBUG_TP_FSM__RESERVED0__SHIFT 0x00000003 +#define SQ_DEBUG_TP_FSM__CF_TP__SHIFT 0x00000004 +#define SQ_DEBUG_TP_FSM__IF_TP__SHIFT 0x00000008 +#define SQ_DEBUG_TP_FSM__RESERVED1__SHIFT 0x0000000b +#define SQ_DEBUG_TP_FSM__TIS_TP__SHIFT 0x0000000c +#define SQ_DEBUG_TP_FSM__RESERVED2__SHIFT 0x0000000e +#define SQ_DEBUG_TP_FSM__GS_TP__SHIFT 0x00000010 +#define SQ_DEBUG_TP_FSM__RESERVED3__SHIFT 0x00000012 +#define SQ_DEBUG_TP_FSM__FCR_TP__SHIFT 0x00000014 +#define SQ_DEBUG_TP_FSM__RESERVED4__SHIFT 0x00000016 +#define SQ_DEBUG_TP_FSM__FCS_TP__SHIFT 0x00000018 +#define SQ_DEBUG_TP_FSM__RESERVED5__SHIFT 0x0000001a +#define SQ_DEBUG_TP_FSM__ARB_TR_TP__SHIFT 0x0000001c + +// SQ_DEBUG_FSM_ALU_0 +#define SQ_DEBUG_FSM_ALU_0__EX_ALU_0__SHIFT 0x00000000 +#define SQ_DEBUG_FSM_ALU_0__RESERVED0__SHIFT 0x00000003 +#define SQ_DEBUG_FSM_ALU_0__CF_ALU_0__SHIFT 0x00000004 +#define SQ_DEBUG_FSM_ALU_0__IF_ALU_0__SHIFT 0x00000008 +#define SQ_DEBUG_FSM_ALU_0__RESERVED1__SHIFT 0x0000000b +#define SQ_DEBUG_FSM_ALU_0__DU1_ALU_0__SHIFT 0x0000000c +#define SQ_DEBUG_FSM_ALU_0__RESERVED2__SHIFT 0x0000000f +#define SQ_DEBUG_FSM_ALU_0__DU0_ALU_0__SHIFT 0x00000010 +#define SQ_DEBUG_FSM_ALU_0__RESERVED3__SHIFT 0x00000013 +#define SQ_DEBUG_FSM_ALU_0__AIS_ALU_0__SHIFT 0x00000014 +#define SQ_DEBUG_FSM_ALU_0__RESERVED4__SHIFT 0x00000017 +#define SQ_DEBUG_FSM_ALU_0__ACS_ALU_0__SHIFT 0x00000018 +#define SQ_DEBUG_FSM_ALU_0__RESERVED5__SHIFT 0x0000001b +#define SQ_DEBUG_FSM_ALU_0__ARB_TR_ALU__SHIFT 0x0000001c + +// SQ_DEBUG_FSM_ALU_1 +#define SQ_DEBUG_FSM_ALU_1__EX_ALU_0__SHIFT 0x00000000 +#define SQ_DEBUG_FSM_ALU_1__RESERVED0__SHIFT 0x00000003 +#define SQ_DEBUG_FSM_ALU_1__CF_ALU_0__SHIFT 0x00000004 +#define SQ_DEBUG_FSM_ALU_1__IF_ALU_0__SHIFT 0x00000008 +#define SQ_DEBUG_FSM_ALU_1__RESERVED1__SHIFT 0x0000000b +#define SQ_DEBUG_FSM_ALU_1__DU1_ALU_0__SHIFT 0x0000000c +#define SQ_DEBUG_FSM_ALU_1__RESERVED2__SHIFT 0x0000000f +#define SQ_DEBUG_FSM_ALU_1__DU0_ALU_0__SHIFT 0x00000010 +#define SQ_DEBUG_FSM_ALU_1__RESERVED3__SHIFT 0x00000013 +#define SQ_DEBUG_FSM_ALU_1__AIS_ALU_0__SHIFT 0x00000014 +#define SQ_DEBUG_FSM_ALU_1__RESERVED4__SHIFT 0x00000017 +#define SQ_DEBUG_FSM_ALU_1__ACS_ALU_0__SHIFT 0x00000018 +#define SQ_DEBUG_FSM_ALU_1__RESERVED5__SHIFT 0x0000001b +#define SQ_DEBUG_FSM_ALU_1__ARB_TR_ALU__SHIFT 0x0000001c + +// SQ_DEBUG_EXP_ALLOC +#define SQ_DEBUG_EXP_ALLOC__POS_BUF_AVAIL__SHIFT 0x00000000 +#define SQ_DEBUG_EXP_ALLOC__COLOR_BUF_AVAIL__SHIFT 0x00000004 +#define SQ_DEBUG_EXP_ALLOC__EA_BUF_AVAIL__SHIFT 0x0000000c +#define SQ_DEBUG_EXP_ALLOC__RESERVED__SHIFT 0x0000000f +#define SQ_DEBUG_EXP_ALLOC__ALLOC_TBL_BUF_AVAIL__SHIFT 0x00000010 + +// SQ_DEBUG_PTR_BUFF +#define SQ_DEBUG_PTR_BUFF__END_OF_BUFFER__SHIFT 0x00000000 +#define SQ_DEBUG_PTR_BUFF__DEALLOC_CNT__SHIFT 0x00000001 +#define SQ_DEBUG_PTR_BUFF__QUAL_NEW_VECTOR__SHIFT 0x00000005 +#define SQ_DEBUG_PTR_BUFF__EVENT_CONTEXT_ID__SHIFT 0x00000006 +#define SQ_DEBUG_PTR_BUFF__SC_EVENT_ID__SHIFT 0x00000009 +#define SQ_DEBUG_PTR_BUFF__QUAL_EVENT__SHIFT 0x0000000e +#define SQ_DEBUG_PTR_BUFF__PRIM_TYPE_POLYGON__SHIFT 0x0000000f +#define SQ_DEBUG_PTR_BUFF__EF_EMPTY__SHIFT 0x00000010 +#define SQ_DEBUG_PTR_BUFF__VTX_SYNC_CNT__SHIFT 0x00000011 + +// SQ_DEBUG_GPR_VTX +#define SQ_DEBUG_GPR_VTX__VTX_TAIL_PTR__SHIFT 0x00000000 +#define SQ_DEBUG_GPR_VTX__RESERVED__SHIFT 0x00000007 +#define SQ_DEBUG_GPR_VTX__VTX_HEAD_PTR__SHIFT 0x00000008 +#define SQ_DEBUG_GPR_VTX__RESERVED1__SHIFT 0x0000000f +#define SQ_DEBUG_GPR_VTX__VTX_MAX__SHIFT 0x00000010 +#define SQ_DEBUG_GPR_VTX__RESERVED2__SHIFT 0x00000017 +#define SQ_DEBUG_GPR_VTX__VTX_FREE__SHIFT 0x00000018 + +// SQ_DEBUG_GPR_PIX +#define SQ_DEBUG_GPR_PIX__PIX_TAIL_PTR__SHIFT 0x00000000 +#define SQ_DEBUG_GPR_PIX__RESERVED__SHIFT 0x00000007 +#define SQ_DEBUG_GPR_PIX__PIX_HEAD_PTR__SHIFT 0x00000008 +#define SQ_DEBUG_GPR_PIX__RESERVED1__SHIFT 0x0000000f +#define SQ_DEBUG_GPR_PIX__PIX_MAX__SHIFT 0x00000010 +#define SQ_DEBUG_GPR_PIX__RESERVED2__SHIFT 0x00000017 +#define SQ_DEBUG_GPR_PIX__PIX_FREE__SHIFT 0x00000018 + +// SQ_DEBUG_TB_STATUS_SEL +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATUS_REG_SEL__SHIFT 0x00000000 +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_DW_SEL__SHIFT 0x00000004 +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_ADDR__SHIFT 0x00000007 +#define SQ_DEBUG_TB_STATUS_SEL__VTX_TB_STATE_MEM_RD_EN__SHIFT 0x0000000b +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_EN__SHIFT 0x0000000c +#define SQ_DEBUG_TB_STATUS_SEL__DEBUG_BUS_TRIGGER_SEL__SHIFT 0x0000000e +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATUS_REG_SEL__SHIFT 0x00000010 +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_DW_SEL__SHIFT 0x00000014 +#define SQ_DEBUG_TB_STATUS_SEL__PIX_TB_STATE_MEM_RD_ADDR__SHIFT 0x00000017 +#define SQ_DEBUG_TB_STATUS_SEL__VC_THREAD_BUF_DLY__SHIFT 0x0000001d +#define SQ_DEBUG_TB_STATUS_SEL__DISABLE_STRICT_CTX_SYNC__SHIFT 0x0000001f + +// SQ_DEBUG_VTX_TB_0 +#define SQ_DEBUG_VTX_TB_0__VTX_HEAD_PTR_Q__SHIFT 0x00000000 +#define SQ_DEBUG_VTX_TB_0__TAIL_PTR_Q__SHIFT 0x00000004 +#define SQ_DEBUG_VTX_TB_0__FULL_CNT_Q__SHIFT 0x00000008 +#define SQ_DEBUG_VTX_TB_0__NXT_POS_ALLOC_CNT__SHIFT 0x0000000c +#define SQ_DEBUG_VTX_TB_0__NXT_PC_ALLOC_CNT__SHIFT 0x00000010 +#define SQ_DEBUG_VTX_TB_0__SX_EVENT_FULL__SHIFT 0x00000014 +#define SQ_DEBUG_VTX_TB_0__BUSY_Q__SHIFT 0x00000015 + +// SQ_DEBUG_VTX_TB_1 +#define SQ_DEBUG_VTX_TB_1__VS_DONE_PTR__SHIFT 0x00000000 + +// SQ_DEBUG_VTX_TB_STATUS_REG +#define SQ_DEBUG_VTX_TB_STATUS_REG__VS_STATUS_REG__SHIFT 0x00000000 + +// SQ_DEBUG_VTX_TB_STATE_MEM +#define SQ_DEBUG_VTX_TB_STATE_MEM__VS_STATE_MEM__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_0 +#define SQ_DEBUG_PIX_TB_0__PIX_HEAD_PTR__SHIFT 0x00000000 +#define SQ_DEBUG_PIX_TB_0__TAIL_PTR__SHIFT 0x00000006 +#define SQ_DEBUG_PIX_TB_0__FULL_CNT__SHIFT 0x0000000c +#define SQ_DEBUG_PIX_TB_0__NXT_PIX_ALLOC_CNT__SHIFT 0x00000013 +#define SQ_DEBUG_PIX_TB_0__NXT_PIX_EXP_CNT__SHIFT 0x00000019 +#define SQ_DEBUG_PIX_TB_0__BUSY__SHIFT 0x0000001f + +// SQ_DEBUG_PIX_TB_STATUS_REG_0 +#define SQ_DEBUG_PIX_TB_STATUS_REG_0__PIX_TB_STATUS_REG_0__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_STATUS_REG_1 +#define SQ_DEBUG_PIX_TB_STATUS_REG_1__PIX_TB_STATUS_REG_1__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_STATUS_REG_2 +#define SQ_DEBUG_PIX_TB_STATUS_REG_2__PIX_TB_STATUS_REG_2__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_STATUS_REG_3 +#define SQ_DEBUG_PIX_TB_STATUS_REG_3__PIX_TB_STATUS_REG_3__SHIFT 0x00000000 + +// SQ_DEBUG_PIX_TB_STATE_MEM +#define SQ_DEBUG_PIX_TB_STATE_MEM__PIX_TB_STATE_MEM__SHIFT 0x00000000 + +// SQ_PERFCOUNTER0_SELECT +#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SQ_PERFCOUNTER1_SELECT +#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SQ_PERFCOUNTER2_SELECT +#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SQ_PERFCOUNTER3_SELECT +#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SQ_PERFCOUNTER0_LOW +#define SQ_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER0_HI +#define SQ_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER1_LOW +#define SQ_PERFCOUNTER1_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER1_HI +#define SQ_PERFCOUNTER1_HI__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER2_LOW +#define SQ_PERFCOUNTER2_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER2_HI +#define SQ_PERFCOUNTER2_HI__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER3_LOW +#define SQ_PERFCOUNTER3_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SQ_PERFCOUNTER3_HI +#define SQ_PERFCOUNTER3_HI__PERF_COUNT__SHIFT 0x00000000 + +// SX_PERFCOUNTER0_SELECT +#define SX_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// SX_PERFCOUNTER0_LOW +#define SX_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// SX_PERFCOUNTER0_HI +#define SX_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// SQ_INSTRUCTION_ALU_0 +#define SQ_INSTRUCTION_ALU_0__VECTOR_RESULT__SHIFT 0x00000000 +#define SQ_INSTRUCTION_ALU_0__VECTOR_DST_REL__SHIFT 0x00000006 +#define SQ_INSTRUCTION_ALU_0__LOW_PRECISION_16B_FP__SHIFT 0x00000007 +#define SQ_INSTRUCTION_ALU_0__SCALAR_RESULT__SHIFT 0x00000008 +#define SQ_INSTRUCTION_ALU_0__SCALAR_DST_REL__SHIFT 0x0000000e +#define SQ_INSTRUCTION_ALU_0__EXPORT_DATA__SHIFT 0x0000000f +#define SQ_INSTRUCTION_ALU_0__VECTOR_WRT_MSK__SHIFT 0x00000010 +#define SQ_INSTRUCTION_ALU_0__SCALAR_WRT_MSK__SHIFT 0x00000014 +#define SQ_INSTRUCTION_ALU_0__VECTOR_CLAMP__SHIFT 0x00000018 +#define SQ_INSTRUCTION_ALU_0__SCALAR_CLAMP__SHIFT 0x00000019 +#define SQ_INSTRUCTION_ALU_0__SCALAR_OPCODE__SHIFT 0x0000001a + +// SQ_INSTRUCTION_ALU_1 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_R__SHIFT 0x00000000 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_G__SHIFT 0x00000002 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_B__SHIFT 0x00000004 +#define SQ_INSTRUCTION_ALU_1__SRC_C_SWIZZLE_A__SHIFT 0x00000006 +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_R__SHIFT 0x00000008 +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_G__SHIFT 0x0000000a +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_B__SHIFT 0x0000000c +#define SQ_INSTRUCTION_ALU_1__SRC_B_SWIZZLE_A__SHIFT 0x0000000e +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_R__SHIFT 0x00000010 +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_G__SHIFT 0x00000012 +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_B__SHIFT 0x00000014 +#define SQ_INSTRUCTION_ALU_1__SRC_A_SWIZZLE_A__SHIFT 0x00000016 +#define SQ_INSTRUCTION_ALU_1__SRC_C_ARG_MOD__SHIFT 0x00000018 +#define SQ_INSTRUCTION_ALU_1__SRC_B_ARG_MOD__SHIFT 0x00000019 +#define SQ_INSTRUCTION_ALU_1__SRC_A_ARG_MOD__SHIFT 0x0000001a +#define SQ_INSTRUCTION_ALU_1__PRED_SELECT__SHIFT 0x0000001b +#define SQ_INSTRUCTION_ALU_1__RELATIVE_ADDR__SHIFT 0x0000001d +#define SQ_INSTRUCTION_ALU_1__CONST_1_REL_ABS__SHIFT 0x0000001e +#define SQ_INSTRUCTION_ALU_1__CONST_0_REL_ABS__SHIFT 0x0000001f + +// SQ_INSTRUCTION_ALU_2 +#define SQ_INSTRUCTION_ALU_2__SRC_C_REG_PTR__SHIFT 0x00000000 +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_C__SHIFT 0x00000006 +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_C__SHIFT 0x00000007 +#define SQ_INSTRUCTION_ALU_2__SRC_B_REG_PTR__SHIFT 0x00000008 +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_B__SHIFT 0x0000000e +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_B__SHIFT 0x0000000f +#define SQ_INSTRUCTION_ALU_2__SRC_A_REG_PTR__SHIFT 0x00000010 +#define SQ_INSTRUCTION_ALU_2__REG_SELECT_A__SHIFT 0x00000016 +#define SQ_INSTRUCTION_ALU_2__REG_ABS_MOD_A__SHIFT 0x00000017 +#define SQ_INSTRUCTION_ALU_2__VECTOR_OPCODE__SHIFT 0x00000018 +#define SQ_INSTRUCTION_ALU_2__SRC_C_SEL__SHIFT 0x0000001d +#define SQ_INSTRUCTION_ALU_2__SRC_B_SEL__SHIFT 0x0000001e +#define SQ_INSTRUCTION_ALU_2__SRC_A_SEL__SHIFT 0x0000001f + +// SQ_INSTRUCTION_CF_EXEC_0 +#define SQ_INSTRUCTION_CF_EXEC_0__ADDRESS__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_EXEC_0__RESERVED__SHIFT 0x00000009 +#define SQ_INSTRUCTION_CF_EXEC_0__COUNT__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_EXEC_0__YIELD__SHIFT 0x0000000f +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_0__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_0__SHIFT 0x00000011 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_1__SHIFT 0x00000012 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_1__SHIFT 0x00000013 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_2__SHIFT 0x00000014 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_2__SHIFT 0x00000015 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_3__SHIFT 0x00000016 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_3__SHIFT 0x00000017 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_4__SHIFT 0x00000018 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_4__SHIFT 0x00000019 +#define SQ_INSTRUCTION_CF_EXEC_0__INST_TYPE_5__SHIFT 0x0000001a +#define SQ_INSTRUCTION_CF_EXEC_0__INST_SERIAL_5__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_0__SHIFT 0x0000001c +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_1__SHIFT 0x0000001d +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_2__SHIFT 0x0000001e +#define SQ_INSTRUCTION_CF_EXEC_0__INST_VC_3__SHIFT 0x0000001f + +// SQ_INSTRUCTION_CF_EXEC_1 +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_4__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_EXEC_1__INST_VC_5__SHIFT 0x00000001 +#define SQ_INSTRUCTION_CF_EXEC_1__BOOL_ADDR__SHIFT 0x00000002 +#define SQ_INSTRUCTION_CF_EXEC_1__CONDITION__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS_MODE__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_EXEC_1__OPCODE__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_EXEC_1__ADDRESS__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_EXEC_1__RESERVED__SHIFT 0x00000019 +#define SQ_INSTRUCTION_CF_EXEC_1__COUNT__SHIFT 0x0000001c +#define SQ_INSTRUCTION_CF_EXEC_1__YIELD__SHIFT 0x0000001f + +// SQ_INSTRUCTION_CF_EXEC_2 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_0__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_0__SHIFT 0x00000001 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_1__SHIFT 0x00000002 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_1__SHIFT 0x00000003 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_2__SHIFT 0x00000004 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_2__SHIFT 0x00000005 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_3__SHIFT 0x00000006 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_3__SHIFT 0x00000007 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_4__SHIFT 0x00000008 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_4__SHIFT 0x00000009 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_TYPE_5__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_EXEC_2__INST_SERIAL_5__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_0__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_1__SHIFT 0x0000000d +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_2__SHIFT 0x0000000e +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_3__SHIFT 0x0000000f +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_4__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_EXEC_2__INST_VC_5__SHIFT 0x00000011 +#define SQ_INSTRUCTION_CF_EXEC_2__BOOL_ADDR__SHIFT 0x00000012 +#define SQ_INSTRUCTION_CF_EXEC_2__CONDITION__SHIFT 0x0000001a +#define SQ_INSTRUCTION_CF_EXEC_2__ADDRESS_MODE__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_EXEC_2__OPCODE__SHIFT 0x0000001c + +// SQ_INSTRUCTION_CF_LOOP_0 +#define SQ_INSTRUCTION_CF_LOOP_0__ADDRESS__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_0__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_LOOP_0__LOOP_ID__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_LOOP_0__RESERVED_1__SHIFT 0x00000015 + +// SQ_INSTRUCTION_CF_LOOP_1 +#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_0__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS_MODE__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_LOOP_1__OPCODE__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_LOOP_1__ADDRESS__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_LOOP_1__RESERVED_1__SHIFT 0x0000001a + +// SQ_INSTRUCTION_CF_LOOP_2 +#define SQ_INSTRUCTION_CF_LOOP_2__LOOP_ID__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_LOOP_2__RESERVED__SHIFT 0x00000005 +#define SQ_INSTRUCTION_CF_LOOP_2__ADDRESS_MODE__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_LOOP_2__OPCODE__SHIFT 0x0000001c + +// SQ_INSTRUCTION_CF_JMP_CALL_0 +#define SQ_INSTRUCTION_CF_JMP_CALL_0__ADDRESS__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_0__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_JMP_CALL_0__FORCE_CALL__SHIFT 0x0000000d +#define SQ_INSTRUCTION_CF_JMP_CALL_0__PREDICATED_JMP__SHIFT 0x0000000e +#define SQ_INSTRUCTION_CF_JMP_CALL_0__RESERVED_1__SHIFT 0x0000000f + +// SQ_INSTRUCTION_CF_JMP_CALL_1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_0__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__DIRECTION__SHIFT 0x00000001 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__BOOL_ADDR__SHIFT 0x00000002 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__CONDITION__SHIFT 0x0000000a +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS_MODE__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_JMP_CALL_1__OPCODE__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_JMP_CALL_1__ADDRESS__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_1__SHIFT 0x0000001a +#define SQ_INSTRUCTION_CF_JMP_CALL_1__FORCE_CALL__SHIFT 0x0000001d +#define SQ_INSTRUCTION_CF_JMP_CALL_1__RESERVED_2__SHIFT 0x0000001e + +// SQ_INSTRUCTION_CF_JMP_CALL_2 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__RESERVED__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__DIRECTION__SHIFT 0x00000011 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__BOOL_ADDR__SHIFT 0x00000012 +#define SQ_INSTRUCTION_CF_JMP_CALL_2__CONDITION__SHIFT 0x0000001a +#define SQ_INSTRUCTION_CF_JMP_CALL_2__ADDRESS_MODE__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_JMP_CALL_2__OPCODE__SHIFT 0x0000001c + +// SQ_INSTRUCTION_CF_ALLOC_0 +#define SQ_INSTRUCTION_CF_ALLOC_0__SIZE__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_ALLOC_0__RESERVED__SHIFT 0x00000004 + +// SQ_INSTRUCTION_CF_ALLOC_1 +#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_0__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_ALLOC_1__NO_SERIAL__SHIFT 0x00000008 +#define SQ_INSTRUCTION_CF_ALLOC_1__BUFFER_SELECT__SHIFT 0x00000009 +#define SQ_INSTRUCTION_CF_ALLOC_1__ALLOC_MODE__SHIFT 0x0000000b +#define SQ_INSTRUCTION_CF_ALLOC_1__OPCODE__SHIFT 0x0000000c +#define SQ_INSTRUCTION_CF_ALLOC_1__SIZE__SHIFT 0x00000010 +#define SQ_INSTRUCTION_CF_ALLOC_1__RESERVED_1__SHIFT 0x00000014 + +// SQ_INSTRUCTION_CF_ALLOC_2 +#define SQ_INSTRUCTION_CF_ALLOC_2__RESERVED__SHIFT 0x00000000 +#define SQ_INSTRUCTION_CF_ALLOC_2__NO_SERIAL__SHIFT 0x00000018 +#define SQ_INSTRUCTION_CF_ALLOC_2__BUFFER_SELECT__SHIFT 0x00000019 +#define SQ_INSTRUCTION_CF_ALLOC_2__ALLOC_MODE__SHIFT 0x0000001b +#define SQ_INSTRUCTION_CF_ALLOC_2__OPCODE__SHIFT 0x0000001c + +// SQ_INSTRUCTION_TFETCH_0 +#define SQ_INSTRUCTION_TFETCH_0__OPCODE__SHIFT 0x00000000 +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR__SHIFT 0x00000005 +#define SQ_INSTRUCTION_TFETCH_0__SRC_GPR_AM__SHIFT 0x0000000b +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR__SHIFT 0x0000000c +#define SQ_INSTRUCTION_TFETCH_0__DST_GPR_AM__SHIFT 0x00000012 +#define SQ_INSTRUCTION_TFETCH_0__FETCH_VALID_ONLY__SHIFT 0x00000013 +#define SQ_INSTRUCTION_TFETCH_0__CONST_INDEX__SHIFT 0x00000014 +#define SQ_INSTRUCTION_TFETCH_0__TX_COORD_DENORM__SHIFT 0x00000019 +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_X__SHIFT 0x0000001a +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Y__SHIFT 0x0000001c +#define SQ_INSTRUCTION_TFETCH_0__SRC_SEL_Z__SHIFT 0x0000001e + +// SQ_INSTRUCTION_TFETCH_1 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_X__SHIFT 0x00000000 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Y__SHIFT 0x00000003 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_Z__SHIFT 0x00000006 +#define SQ_INSTRUCTION_TFETCH_1__DST_SEL_W__SHIFT 0x00000009 +#define SQ_INSTRUCTION_TFETCH_1__MAG_FILTER__SHIFT 0x0000000c +#define SQ_INSTRUCTION_TFETCH_1__MIN_FILTER__SHIFT 0x0000000e +#define SQ_INSTRUCTION_TFETCH_1__MIP_FILTER__SHIFT 0x00000010 +#define SQ_INSTRUCTION_TFETCH_1__ANISO_FILTER__SHIFT 0x00000012 +#define SQ_INSTRUCTION_TFETCH_1__ARBITRARY_FILTER__SHIFT 0x00000015 +#define SQ_INSTRUCTION_TFETCH_1__VOL_MAG_FILTER__SHIFT 0x00000018 +#define SQ_INSTRUCTION_TFETCH_1__VOL_MIN_FILTER__SHIFT 0x0000001a +#define SQ_INSTRUCTION_TFETCH_1__USE_COMP_LOD__SHIFT 0x0000001c +#define SQ_INSTRUCTION_TFETCH_1__USE_REG_LOD__SHIFT 0x0000001d +#define SQ_INSTRUCTION_TFETCH_1__PRED_SELECT__SHIFT 0x0000001f + +// SQ_INSTRUCTION_TFETCH_2 +#define SQ_INSTRUCTION_TFETCH_2__USE_REG_GRADIENTS__SHIFT 0x00000000 +#define SQ_INSTRUCTION_TFETCH_2__SAMPLE_LOCATION__SHIFT 0x00000001 +#define SQ_INSTRUCTION_TFETCH_2__LOD_BIAS__SHIFT 0x00000002 +#define SQ_INSTRUCTION_TFETCH_2__UNUSED__SHIFT 0x00000009 +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_X__SHIFT 0x00000010 +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Y__SHIFT 0x00000015 +#define SQ_INSTRUCTION_TFETCH_2__OFFSET_Z__SHIFT 0x0000001a +#define SQ_INSTRUCTION_TFETCH_2__PRED_CONDITION__SHIFT 0x0000001f + +// SQ_INSTRUCTION_VFETCH_0 +#define SQ_INSTRUCTION_VFETCH_0__OPCODE__SHIFT 0x00000000 +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR__SHIFT 0x00000005 +#define SQ_INSTRUCTION_VFETCH_0__SRC_GPR_AM__SHIFT 0x0000000b +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR__SHIFT 0x0000000c +#define SQ_INSTRUCTION_VFETCH_0__DST_GPR_AM__SHIFT 0x00000012 +#define SQ_INSTRUCTION_VFETCH_0__MUST_BE_ONE__SHIFT 0x00000013 +#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX__SHIFT 0x00000014 +#define SQ_INSTRUCTION_VFETCH_0__CONST_INDEX_SEL__SHIFT 0x00000019 +#define SQ_INSTRUCTION_VFETCH_0__SRC_SEL__SHIFT 0x0000001e + +// SQ_INSTRUCTION_VFETCH_1 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_X__SHIFT 0x00000000 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Y__SHIFT 0x00000003 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_Z__SHIFT 0x00000006 +#define SQ_INSTRUCTION_VFETCH_1__DST_SEL_W__SHIFT 0x00000009 +#define SQ_INSTRUCTION_VFETCH_1__FORMAT_COMP_ALL__SHIFT 0x0000000c +#define SQ_INSTRUCTION_VFETCH_1__NUM_FORMAT_ALL__SHIFT 0x0000000d +#define SQ_INSTRUCTION_VFETCH_1__SIGNED_RF_MODE_ALL__SHIFT 0x0000000e +#define SQ_INSTRUCTION_VFETCH_1__DATA_FORMAT__SHIFT 0x00000010 +#define SQ_INSTRUCTION_VFETCH_1__EXP_ADJUST_ALL__SHIFT 0x00000017 +#define SQ_INSTRUCTION_VFETCH_1__PRED_SELECT__SHIFT 0x0000001f + +// SQ_INSTRUCTION_VFETCH_2 +#define SQ_INSTRUCTION_VFETCH_2__STRIDE__SHIFT 0x00000000 +#define SQ_INSTRUCTION_VFETCH_2__OFFSET__SHIFT 0x00000010 +#define SQ_INSTRUCTION_VFETCH_2__PRED_CONDITION__SHIFT 0x0000001f + +// SQ_CONSTANT_0 +#define SQ_CONSTANT_0__RED__SHIFT 0x00000000 + +// SQ_CONSTANT_1 +#define SQ_CONSTANT_1__GREEN__SHIFT 0x00000000 + +// SQ_CONSTANT_2 +#define SQ_CONSTANT_2__BLUE__SHIFT 0x00000000 + +// SQ_CONSTANT_3 +#define SQ_CONSTANT_3__ALPHA__SHIFT 0x00000000 + +// SQ_FETCH_0 +#define SQ_FETCH_0__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_1 +#define SQ_FETCH_1__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_2 +#define SQ_FETCH_2__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_3 +#define SQ_FETCH_3__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_4 +#define SQ_FETCH_4__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_5 +#define SQ_FETCH_5__VALUE__SHIFT 0x00000000 + +// SQ_CONSTANT_VFETCH_0 +#define SQ_CONSTANT_VFETCH_0__TYPE__SHIFT 0x00000000 +#define SQ_CONSTANT_VFETCH_0__STATE__SHIFT 0x00000001 +#define SQ_CONSTANT_VFETCH_0__BASE_ADDRESS__SHIFT 0x00000002 + +// SQ_CONSTANT_VFETCH_1 +#define SQ_CONSTANT_VFETCH_1__ENDIAN_SWAP__SHIFT 0x00000000 +#define SQ_CONSTANT_VFETCH_1__LIMIT_ADDRESS__SHIFT 0x00000002 + +// SQ_CONSTANT_T2 +#define SQ_CONSTANT_T2__VALUE__SHIFT 0x00000000 + +// SQ_CONSTANT_T3 +#define SQ_CONSTANT_T3__VALUE__SHIFT 0x00000000 + +// SQ_CF_BOOLEANS +#define SQ_CF_BOOLEANS__CF_BOOLEANS_0__SHIFT 0x00000000 +#define SQ_CF_BOOLEANS__CF_BOOLEANS_1__SHIFT 0x00000008 +#define SQ_CF_BOOLEANS__CF_BOOLEANS_2__SHIFT 0x00000010 +#define SQ_CF_BOOLEANS__CF_BOOLEANS_3__SHIFT 0x00000018 + +// SQ_CF_LOOP +#define SQ_CF_LOOP__CF_LOOP_COUNT__SHIFT 0x00000000 +#define SQ_CF_LOOP__CF_LOOP_START__SHIFT 0x00000008 +#define SQ_CF_LOOP__CF_LOOP_STEP__SHIFT 0x00000010 + +// SQ_CONSTANT_RT_0 +#define SQ_CONSTANT_RT_0__RED__SHIFT 0x00000000 + +// SQ_CONSTANT_RT_1 +#define SQ_CONSTANT_RT_1__GREEN__SHIFT 0x00000000 + +// SQ_CONSTANT_RT_2 +#define SQ_CONSTANT_RT_2__BLUE__SHIFT 0x00000000 + +// SQ_CONSTANT_RT_3 +#define SQ_CONSTANT_RT_3__ALPHA__SHIFT 0x00000000 + +// SQ_FETCH_RT_0 +#define SQ_FETCH_RT_0__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_1 +#define SQ_FETCH_RT_1__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_2 +#define SQ_FETCH_RT_2__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_3 +#define SQ_FETCH_RT_3__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_4 +#define SQ_FETCH_RT_4__VALUE__SHIFT 0x00000000 + +// SQ_FETCH_RT_5 +#define SQ_FETCH_RT_5__VALUE__SHIFT 0x00000000 + +// SQ_CF_RT_BOOLEANS +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_0__SHIFT 0x00000000 +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_1__SHIFT 0x00000008 +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_2__SHIFT 0x00000010 +#define SQ_CF_RT_BOOLEANS__CF_BOOLEANS_3__SHIFT 0x00000018 + +// SQ_CF_RT_LOOP +#define SQ_CF_RT_LOOP__CF_LOOP_COUNT__SHIFT 0x00000000 +#define SQ_CF_RT_LOOP__CF_LOOP_START__SHIFT 0x00000008 +#define SQ_CF_RT_LOOP__CF_LOOP_STEP__SHIFT 0x00000010 + +// SQ_VS_PROGRAM +#define SQ_VS_PROGRAM__BASE__SHIFT 0x00000000 +#define SQ_VS_PROGRAM__SIZE__SHIFT 0x0000000c + +// SQ_PS_PROGRAM +#define SQ_PS_PROGRAM__BASE__SHIFT 0x00000000 +#define SQ_PS_PROGRAM__SIZE__SHIFT 0x0000000c + +// SQ_CF_PROGRAM_SIZE +#define SQ_CF_PROGRAM_SIZE__VS_CF_SIZE__SHIFT 0x00000000 +#define SQ_CF_PROGRAM_SIZE__PS_CF_SIZE__SHIFT 0x0000000c + +// SQ_INTERPOLATOR_CNTL +#define SQ_INTERPOLATOR_CNTL__PARAM_SHADE__SHIFT 0x00000000 +#define SQ_INTERPOLATOR_CNTL__SAMPLING_PATTERN__SHIFT 0x00000010 + +// SQ_PROGRAM_CNTL +#define SQ_PROGRAM_CNTL__VS_NUM_REG__SHIFT 0x00000000 +#define SQ_PROGRAM_CNTL__PS_NUM_REG__SHIFT 0x00000008 +#define SQ_PROGRAM_CNTL__VS_RESOURCE__SHIFT 0x00000010 +#define SQ_PROGRAM_CNTL__PS_RESOURCE__SHIFT 0x00000011 +#define SQ_PROGRAM_CNTL__PARAM_GEN__SHIFT 0x00000012 +#define SQ_PROGRAM_CNTL__GEN_INDEX_PIX__SHIFT 0x00000013 +#define SQ_PROGRAM_CNTL__VS_EXPORT_COUNT__SHIFT 0x00000014 +#define SQ_PROGRAM_CNTL__VS_EXPORT_MODE__SHIFT 0x00000018 +#define SQ_PROGRAM_CNTL__PS_EXPORT_MODE__SHIFT 0x0000001b +#define SQ_PROGRAM_CNTL__GEN_INDEX_VTX__SHIFT 0x0000001f + +// SQ_WRAPPING_0 +#define SQ_WRAPPING_0__PARAM_WRAP_0__SHIFT 0x00000000 +#define SQ_WRAPPING_0__PARAM_WRAP_1__SHIFT 0x00000004 +#define SQ_WRAPPING_0__PARAM_WRAP_2__SHIFT 0x00000008 +#define SQ_WRAPPING_0__PARAM_WRAP_3__SHIFT 0x0000000c +#define SQ_WRAPPING_0__PARAM_WRAP_4__SHIFT 0x00000010 +#define SQ_WRAPPING_0__PARAM_WRAP_5__SHIFT 0x00000014 +#define SQ_WRAPPING_0__PARAM_WRAP_6__SHIFT 0x00000018 +#define SQ_WRAPPING_0__PARAM_WRAP_7__SHIFT 0x0000001c + +// SQ_WRAPPING_1 +#define SQ_WRAPPING_1__PARAM_WRAP_8__SHIFT 0x00000000 +#define SQ_WRAPPING_1__PARAM_WRAP_9__SHIFT 0x00000004 +#define SQ_WRAPPING_1__PARAM_WRAP_10__SHIFT 0x00000008 +#define SQ_WRAPPING_1__PARAM_WRAP_11__SHIFT 0x0000000c +#define SQ_WRAPPING_1__PARAM_WRAP_12__SHIFT 0x00000010 +#define SQ_WRAPPING_1__PARAM_WRAP_13__SHIFT 0x00000014 +#define SQ_WRAPPING_1__PARAM_WRAP_14__SHIFT 0x00000018 +#define SQ_WRAPPING_1__PARAM_WRAP_15__SHIFT 0x0000001c + +// SQ_VS_CONST +#define SQ_VS_CONST__BASE__SHIFT 0x00000000 +#define SQ_VS_CONST__SIZE__SHIFT 0x0000000c + +// SQ_PS_CONST +#define SQ_PS_CONST__BASE__SHIFT 0x00000000 +#define SQ_PS_CONST__SIZE__SHIFT 0x0000000c + +// SQ_CONTEXT_MISC +#define SQ_CONTEXT_MISC__INST_PRED_OPTIMIZE__SHIFT 0x00000000 +#define SQ_CONTEXT_MISC__SC_OUTPUT_SCREEN_XY__SHIFT 0x00000001 +#define SQ_CONTEXT_MISC__SC_SAMPLE_CNTL__SHIFT 0x00000002 +#define SQ_CONTEXT_MISC__PARAM_GEN_POS__SHIFT 0x00000008 +#define SQ_CONTEXT_MISC__PERFCOUNTER_REF__SHIFT 0x00000010 +#define SQ_CONTEXT_MISC__YEILD_OPTIMIZE__SHIFT 0x00000011 +#define SQ_CONTEXT_MISC__TX_CACHE_SEL__SHIFT 0x00000012 + +// SQ_CF_RD_BASE +#define SQ_CF_RD_BASE__RD_BASE__SHIFT 0x00000000 + +// SQ_DEBUG_MISC_0 +#define SQ_DEBUG_MISC_0__DB_PROB_ON__SHIFT 0x00000000 +#define SQ_DEBUG_MISC_0__DB_PROB_BREAK__SHIFT 0x00000004 +#define SQ_DEBUG_MISC_0__DB_PROB_ADDR__SHIFT 0x00000008 +#define SQ_DEBUG_MISC_0__DB_PROB_COUNT__SHIFT 0x00000018 + +// SQ_DEBUG_MISC_1 +#define SQ_DEBUG_MISC_1__DB_ON_PIX__SHIFT 0x00000000 +#define SQ_DEBUG_MISC_1__DB_ON_VTX__SHIFT 0x00000001 +#define SQ_DEBUG_MISC_1__DB_INST_COUNT__SHIFT 0x00000008 +#define SQ_DEBUG_MISC_1__DB_BREAK_ADDR__SHIFT 0x00000010 + +// MH_ARBITER_CONFIG +#define MH_ARBITER_CONFIG__SAME_PAGE_LIMIT__SHIFT 0x00000000 +#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY__SHIFT 0x00000006 +#define MH_ARBITER_CONFIG__L1_ARB_ENABLE__SHIFT 0x00000007 +#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE__SHIFT 0x00000008 +#define MH_ARBITER_CONFIG__L2_ARB_CONTROL__SHIFT 0x00000009 +#define MH_ARBITER_CONFIG__PAGE_SIZE__SHIFT 0x0000000a +#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE__SHIFT 0x0000000d +#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE__SHIFT 0x0000000e +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE__SHIFT 0x0000000f +#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT__SHIFT 0x00000010 +#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE__SHIFT 0x00000016 +#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE__SHIFT 0x00000017 +#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE__SHIFT 0x00000018 +#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE__SHIFT 0x00000019 +#define MH_ARBITER_CONFIG__PA_CLNT_ENABLE__SHIFT 0x0000001a + +// MH_CLNT_AXI_ID_REUSE +#define MH_CLNT_AXI_ID_REUSE__CPw_ID__SHIFT 0x00000000 +#define MH_CLNT_AXI_ID_REUSE__RESERVED1__SHIFT 0x00000003 +#define MH_CLNT_AXI_ID_REUSE__RBw_ID__SHIFT 0x00000004 +#define MH_CLNT_AXI_ID_REUSE__RESERVED2__SHIFT 0x00000007 +#define MH_CLNT_AXI_ID_REUSE__MMUr_ID__SHIFT 0x00000008 +#define MH_CLNT_AXI_ID_REUSE__RESERVED3__SHIFT 0x0000000b +#define MH_CLNT_AXI_ID_REUSE__PAw_ID__SHIFT 0x0000000c + +// MH_INTERRUPT_MASK +#define MH_INTERRUPT_MASK__AXI_READ_ERROR__SHIFT 0x00000000 +#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR__SHIFT 0x00000001 +#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT__SHIFT 0x00000002 + +// MH_INTERRUPT_STATUS +#define MH_INTERRUPT_STATUS__AXI_READ_ERROR__SHIFT 0x00000000 +#define MH_INTERRUPT_STATUS__AXI_WRITE_ERROR__SHIFT 0x00000001 +#define MH_INTERRUPT_STATUS__MMU_PAGE_FAULT__SHIFT 0x00000002 + +// MH_INTERRUPT_CLEAR +#define MH_INTERRUPT_CLEAR__AXI_READ_ERROR__SHIFT 0x00000000 +#define MH_INTERRUPT_CLEAR__AXI_WRITE_ERROR__SHIFT 0x00000001 +#define MH_INTERRUPT_CLEAR__MMU_PAGE_FAULT__SHIFT 0x00000002 + +// MH_AXI_ERROR +#define MH_AXI_ERROR__AXI_READ_ID__SHIFT 0x00000000 +#define MH_AXI_ERROR__AXI_READ_ERROR__SHIFT 0x00000003 +#define MH_AXI_ERROR__AXI_WRITE_ID__SHIFT 0x00000004 +#define MH_AXI_ERROR__AXI_WRITE_ERROR__SHIFT 0x00000007 + +// MH_PERFCOUNTER0_SELECT +#define MH_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// MH_PERFCOUNTER1_SELECT +#define MH_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000 + +// MH_PERFCOUNTER0_CONFIG +#define MH_PERFCOUNTER0_CONFIG__N_VALUE__SHIFT 0x00000000 + +// MH_PERFCOUNTER1_CONFIG +#define MH_PERFCOUNTER1_CONFIG__N_VALUE__SHIFT 0x00000000 + +// MH_PERFCOUNTER0_LOW +#define MH_PERFCOUNTER0_LOW__PERF_COUNTER_LOW__SHIFT 0x00000000 + +// MH_PERFCOUNTER1_LOW +#define MH_PERFCOUNTER1_LOW__PERF_COUNTER_LOW__SHIFT 0x00000000 + +// MH_PERFCOUNTER0_HI +#define MH_PERFCOUNTER0_HI__PERF_COUNTER_HI__SHIFT 0x00000000 + +// MH_PERFCOUNTER1_HI +#define MH_PERFCOUNTER1_HI__PERF_COUNTER_HI__SHIFT 0x00000000 + +// MH_DEBUG_CTRL +#define MH_DEBUG_CTRL__INDEX__SHIFT 0x00000000 + +// MH_DEBUG_DATA +#define MH_DEBUG_DATA__DATA__SHIFT 0x00000000 + +// MH_AXI_HALT_CONTROL +#define MH_AXI_HALT_CONTROL__AXI_HALT__SHIFT 0x00000000 + +// MH_DEBUG_REG00 +#define MH_DEBUG_REG00__MH_BUSY__SHIFT 0x00000000 +#define MH_DEBUG_REG00__TRANS_OUTSTANDING__SHIFT 0x00000001 +#define MH_DEBUG_REG00__CP_REQUEST__SHIFT 0x00000002 +#define MH_DEBUG_REG00__VGT_REQUEST__SHIFT 0x00000003 +#define MH_DEBUG_REG00__TC_REQUEST__SHIFT 0x00000004 +#define MH_DEBUG_REG00__TC_CAM_EMPTY__SHIFT 0x00000005 +#define MH_DEBUG_REG00__TC_CAM_FULL__SHIFT 0x00000006 +#define MH_DEBUG_REG00__TCD_EMPTY__SHIFT 0x00000007 +#define MH_DEBUG_REG00__TCD_FULL__SHIFT 0x00000008 +#define MH_DEBUG_REG00__RB_REQUEST__SHIFT 0x00000009 +#define MH_DEBUG_REG00__PA_REQUEST__SHIFT 0x0000000a +#define MH_DEBUG_REG00__MH_CLK_EN_STATE__SHIFT 0x0000000b +#define MH_DEBUG_REG00__ARQ_EMPTY__SHIFT 0x0000000c +#define MH_DEBUG_REG00__ARQ_FULL__SHIFT 0x0000000d +#define MH_DEBUG_REG00__WDB_EMPTY__SHIFT 0x0000000e +#define MH_DEBUG_REG00__WDB_FULL__SHIFT 0x0000000f +#define MH_DEBUG_REG00__AXI_AVALID__SHIFT 0x00000010 +#define MH_DEBUG_REG00__AXI_AREADY__SHIFT 0x00000011 +#define MH_DEBUG_REG00__AXI_ARVALID__SHIFT 0x00000012 +#define MH_DEBUG_REG00__AXI_ARREADY__SHIFT 0x00000013 +#define MH_DEBUG_REG00__AXI_WVALID__SHIFT 0x00000014 +#define MH_DEBUG_REG00__AXI_WREADY__SHIFT 0x00000015 +#define MH_DEBUG_REG00__AXI_RVALID__SHIFT 0x00000016 +#define MH_DEBUG_REG00__AXI_RREADY__SHIFT 0x00000017 +#define MH_DEBUG_REG00__AXI_BVALID__SHIFT 0x00000018 +#define MH_DEBUG_REG00__AXI_BREADY__SHIFT 0x00000019 +#define MH_DEBUG_REG00__AXI_HALT_REQ__SHIFT 0x0000001a +#define MH_DEBUG_REG00__AXI_HALT_ACK__SHIFT 0x0000001b +#define MH_DEBUG_REG00__AXI_RDY_ENA__SHIFT 0x0000001c + +// MH_DEBUG_REG01 +#define MH_DEBUG_REG01__CP_SEND_q__SHIFT 0x00000000 +#define MH_DEBUG_REG01__CP_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG01__CP_WRITE_q__SHIFT 0x00000002 +#define MH_DEBUG_REG01__CP_TAG_q__SHIFT 0x00000003 +#define MH_DEBUG_REG01__CP_BLEN_q__SHIFT 0x00000006 +#define MH_DEBUG_REG01__VGT_SEND_q__SHIFT 0x00000007 +#define MH_DEBUG_REG01__VGT_RTR_q__SHIFT 0x00000008 +#define MH_DEBUG_REG01__VGT_TAG_q__SHIFT 0x00000009 +#define MH_DEBUG_REG01__TC_SEND_q__SHIFT 0x0000000a +#define MH_DEBUG_REG01__TC_RTR_q__SHIFT 0x0000000b +#define MH_DEBUG_REG01__TC_BLEN_q__SHIFT 0x0000000c +#define MH_DEBUG_REG01__TC_ROQ_SEND_q__SHIFT 0x0000000d +#define MH_DEBUG_REG01__TC_ROQ_RTR_q__SHIFT 0x0000000e +#define MH_DEBUG_REG01__TC_MH_written__SHIFT 0x0000000f +#define MH_DEBUG_REG01__RB_SEND_q__SHIFT 0x00000010 +#define MH_DEBUG_REG01__RB_RTR_q__SHIFT 0x00000011 +#define MH_DEBUG_REG01__PA_SEND_q__SHIFT 0x00000012 +#define MH_DEBUG_REG01__PA_RTR_q__SHIFT 0x00000013 + +// MH_DEBUG_REG02 +#define MH_DEBUG_REG02__MH_CP_grb_send__SHIFT 0x00000000 +#define MH_DEBUG_REG02__MH_VGT_grb_send__SHIFT 0x00000001 +#define MH_DEBUG_REG02__MH_TC_mcsend__SHIFT 0x00000002 +#define MH_DEBUG_REG02__MH_CLNT_rlast__SHIFT 0x00000003 +#define MH_DEBUG_REG02__MH_CLNT_tag__SHIFT 0x00000004 +#define MH_DEBUG_REG02__RDC_RID__SHIFT 0x00000007 +#define MH_DEBUG_REG02__RDC_RRESP__SHIFT 0x0000000a +#define MH_DEBUG_REG02__MH_CP_writeclean__SHIFT 0x0000000c +#define MH_DEBUG_REG02__MH_RB_writeclean__SHIFT 0x0000000d +#define MH_DEBUG_REG02__MH_PA_writeclean__SHIFT 0x0000000e +#define MH_DEBUG_REG02__BRC_BID__SHIFT 0x0000000f +#define MH_DEBUG_REG02__BRC_BRESP__SHIFT 0x00000012 + +// MH_DEBUG_REG03 +#define MH_DEBUG_REG03__MH_CLNT_data_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG04 +#define MH_DEBUG_REG04__MH_CLNT_data_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG05 +#define MH_DEBUG_REG05__CP_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG05__CP_MH_write__SHIFT 0x00000001 +#define MH_DEBUG_REG05__CP_MH_tag__SHIFT 0x00000002 +#define MH_DEBUG_REG05__CP_MH_ad_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG06 +#define MH_DEBUG_REG06__CP_MH_data_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG07 +#define MH_DEBUG_REG07__CP_MH_data_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG08 +#define MH_DEBUG_REG08__CP_MH_be__SHIFT 0x00000000 +#define MH_DEBUG_REG08__RB_MH_be__SHIFT 0x00000008 +#define MH_DEBUG_REG08__PA_MH_be__SHIFT 0x00000010 + +// MH_DEBUG_REG09 +#define MH_DEBUG_REG09__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG09__VGT_MH_send__SHIFT 0x00000003 +#define MH_DEBUG_REG09__VGT_MH_tagbe__SHIFT 0x00000004 +#define MH_DEBUG_REG09__VGT_MH_ad_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG10 +#define MH_DEBUG_REG10__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG10__TC_MH_send__SHIFT 0x00000002 +#define MH_DEBUG_REG10__TC_MH_mask__SHIFT 0x00000003 +#define MH_DEBUG_REG10__TC_MH_addr_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG11 +#define MH_DEBUG_REG11__TC_MH_info__SHIFT 0x00000000 +#define MH_DEBUG_REG11__TC_MH_send__SHIFT 0x00000019 + +// MH_DEBUG_REG12 +#define MH_DEBUG_REG12__MH_TC_mcinfo__SHIFT 0x00000000 +#define MH_DEBUG_REG12__MH_TC_mcinfo_send__SHIFT 0x00000019 +#define MH_DEBUG_REG12__TC_MH_written__SHIFT 0x0000001a + +// MH_DEBUG_REG13 +#define MH_DEBUG_REG13__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG13__TC_ROQ_SEND__SHIFT 0x00000002 +#define MH_DEBUG_REG13__TC_ROQ_MASK__SHIFT 0x00000003 +#define MH_DEBUG_REG13__TC_ROQ_ADDR_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG14 +#define MH_DEBUG_REG14__TC_ROQ_INFO__SHIFT 0x00000000 +#define MH_DEBUG_REG14__TC_ROQ_SEND__SHIFT 0x00000019 + +// MH_DEBUG_REG15 +#define MH_DEBUG_REG15__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG15__RB_MH_send__SHIFT 0x00000004 +#define MH_DEBUG_REG15__RB_MH_addr_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG16 +#define MH_DEBUG_REG16__RB_MH_data_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG17 +#define MH_DEBUG_REG17__RB_MH_data_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG18 +#define MH_DEBUG_REG18__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG18__PA_MH_send__SHIFT 0x00000004 +#define MH_DEBUG_REG18__PA_MH_addr_31_5__SHIFT 0x00000005 + +// MH_DEBUG_REG19 +#define MH_DEBUG_REG19__PA_MH_data_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG20 +#define MH_DEBUG_REG20__PA_MH_data_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG21 +#define MH_DEBUG_REG21__AVALID_q__SHIFT 0x00000000 +#define MH_DEBUG_REG21__AREADY_q__SHIFT 0x00000001 +#define MH_DEBUG_REG21__AID_q__SHIFT 0x00000002 +#define MH_DEBUG_REG21__ALEN_q_2_0__SHIFT 0x00000005 +#define MH_DEBUG_REG21__ARVALID_q__SHIFT 0x00000008 +#define MH_DEBUG_REG21__ARREADY_q__SHIFT 0x00000009 +#define MH_DEBUG_REG21__ARID_q__SHIFT 0x0000000a +#define MH_DEBUG_REG21__ARLEN_q_1_0__SHIFT 0x0000000d +#define MH_DEBUG_REG21__RVALID_q__SHIFT 0x0000000f +#define MH_DEBUG_REG21__RREADY_q__SHIFT 0x00000010 +#define MH_DEBUG_REG21__RLAST_q__SHIFT 0x00000011 +#define MH_DEBUG_REG21__RID_q__SHIFT 0x00000012 +#define MH_DEBUG_REG21__WVALID_q__SHIFT 0x00000015 +#define MH_DEBUG_REG21__WREADY_q__SHIFT 0x00000016 +#define MH_DEBUG_REG21__WLAST_q__SHIFT 0x00000017 +#define MH_DEBUG_REG21__WID_q__SHIFT 0x00000018 +#define MH_DEBUG_REG21__BVALID_q__SHIFT 0x0000001b +#define MH_DEBUG_REG21__BREADY_q__SHIFT 0x0000001c +#define MH_DEBUG_REG21__BID_q__SHIFT 0x0000001d + +// MH_DEBUG_REG22 +#define MH_DEBUG_REG22__AVALID_q__SHIFT 0x00000000 +#define MH_DEBUG_REG22__AREADY_q__SHIFT 0x00000001 +#define MH_DEBUG_REG22__AID_q__SHIFT 0x00000002 +#define MH_DEBUG_REG22__ALEN_q_1_0__SHIFT 0x00000005 +#define MH_DEBUG_REG22__ARVALID_q__SHIFT 0x00000007 +#define MH_DEBUG_REG22__ARREADY_q__SHIFT 0x00000008 +#define MH_DEBUG_REG22__ARID_q__SHIFT 0x00000009 +#define MH_DEBUG_REG22__ARLEN_q_1_1__SHIFT 0x0000000c +#define MH_DEBUG_REG22__WVALID_q__SHIFT 0x0000000d +#define MH_DEBUG_REG22__WREADY_q__SHIFT 0x0000000e +#define MH_DEBUG_REG22__WLAST_q__SHIFT 0x0000000f +#define MH_DEBUG_REG22__WID_q__SHIFT 0x00000010 +#define MH_DEBUG_REG22__WSTRB_q__SHIFT 0x00000013 +#define MH_DEBUG_REG22__BVALID_q__SHIFT 0x0000001b +#define MH_DEBUG_REG22__BREADY_q__SHIFT 0x0000001c +#define MH_DEBUG_REG22__BID_q__SHIFT 0x0000001d + +// MH_DEBUG_REG23 +#define MH_DEBUG_REG23__ARC_CTRL_RE_q__SHIFT 0x00000000 +#define MH_DEBUG_REG23__CTRL_ARC_ID__SHIFT 0x00000001 +#define MH_DEBUG_REG23__CTRL_ARC_PAD__SHIFT 0x00000004 + +// MH_DEBUG_REG24 +#define MH_DEBUG_REG24__ALWAYS_ZERO__SHIFT 0x00000000 +#define MH_DEBUG_REG24__REG_A__SHIFT 0x00000002 +#define MH_DEBUG_REG24__REG_RE__SHIFT 0x00000010 +#define MH_DEBUG_REG24__REG_WE__SHIFT 0x00000011 +#define MH_DEBUG_REG24__BLOCK_RS__SHIFT 0x00000012 + +// MH_DEBUG_REG25 +#define MH_DEBUG_REG25__REG_WD__SHIFT 0x00000000 + +// MH_DEBUG_REG26 +#define MH_DEBUG_REG26__MH_RBBM_busy__SHIFT 0x00000000 +#define MH_DEBUG_REG26__MH_CIB_mh_clk_en_int__SHIFT 0x00000001 +#define MH_DEBUG_REG26__MH_CIB_mmu_clk_en_int__SHIFT 0x00000002 +#define MH_DEBUG_REG26__MH_CIB_tcroq_clk_en_int__SHIFT 0x00000003 +#define MH_DEBUG_REG26__GAT_CLK_ENA__SHIFT 0x00000004 +#define MH_DEBUG_REG26__RBBM_MH_clk_en_override__SHIFT 0x00000005 +#define MH_DEBUG_REG26__CNT_q__SHIFT 0x00000006 +#define MH_DEBUG_REG26__TCD_EMPTY_q__SHIFT 0x0000000c +#define MH_DEBUG_REG26__TC_ROQ_EMPTY__SHIFT 0x0000000d +#define MH_DEBUG_REG26__MH_BUSY_d__SHIFT 0x0000000e +#define MH_DEBUG_REG26__ANY_CLNT_BUSY__SHIFT 0x0000000f +#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_ALL__SHIFT 0x00000010 +#define MH_DEBUG_REG26__MH_MMU_INVALIDATE_INVALIDATE_TC__SHIFT 0x00000011 +#define MH_DEBUG_REG26__CP_SEND_q__SHIFT 0x00000012 +#define MH_DEBUG_REG26__CP_RTR_q__SHIFT 0x00000013 +#define MH_DEBUG_REG26__VGT_SEND_q__SHIFT 0x00000014 +#define MH_DEBUG_REG26__VGT_RTR_q__SHIFT 0x00000015 +#define MH_DEBUG_REG26__TC_ROQ_SEND_q__SHIFT 0x00000016 +#define MH_DEBUG_REG26__TC_ROQ_RTR_DBG_q__SHIFT 0x00000017 +#define MH_DEBUG_REG26__RB_SEND_q__SHIFT 0x00000018 +#define MH_DEBUG_REG26__RB_RTR_q__SHIFT 0x00000019 +#define MH_DEBUG_REG26__PA_SEND_q__SHIFT 0x0000001a +#define MH_DEBUG_REG26__PA_RTR_q__SHIFT 0x0000001b +#define MH_DEBUG_REG26__RDC_VALID__SHIFT 0x0000001c +#define MH_DEBUG_REG26__RDC_RLAST__SHIFT 0x0000001d +#define MH_DEBUG_REG26__TLBMISS_VALID__SHIFT 0x0000001e +#define MH_DEBUG_REG26__BRC_VALID__SHIFT 0x0000001f + +// MH_DEBUG_REG27 +#define MH_DEBUG_REG27__EFF2_FP_WINNER__SHIFT 0x00000000 +#define MH_DEBUG_REG27__EFF2_LRU_WINNER_out__SHIFT 0x00000003 +#define MH_DEBUG_REG27__EFF1_WINNER__SHIFT 0x00000006 +#define MH_DEBUG_REG27__ARB_WINNER__SHIFT 0x00000009 +#define MH_DEBUG_REG27__ARB_WINNER_q__SHIFT 0x0000000c +#define MH_DEBUG_REG27__EFF1_WIN__SHIFT 0x0000000f +#define MH_DEBUG_REG27__KILL_EFF1__SHIFT 0x00000010 +#define MH_DEBUG_REG27__ARB_HOLD__SHIFT 0x00000011 +#define MH_DEBUG_REG27__ARB_RTR_q__SHIFT 0x00000012 +#define MH_DEBUG_REG27__CP_SEND_QUAL__SHIFT 0x00000013 +#define MH_DEBUG_REG27__VGT_SEND_QUAL__SHIFT 0x00000014 +#define MH_DEBUG_REG27__TC_SEND_QUAL__SHIFT 0x00000015 +#define MH_DEBUG_REG27__TC_SEND_EFF1_QUAL__SHIFT 0x00000016 +#define MH_DEBUG_REG27__RB_SEND_QUAL__SHIFT 0x00000017 +#define MH_DEBUG_REG27__PA_SEND_QUAL__SHIFT 0x00000018 +#define MH_DEBUG_REG27__ARB_QUAL__SHIFT 0x00000019 +#define MH_DEBUG_REG27__CP_EFF1_REQ__SHIFT 0x0000001a +#define MH_DEBUG_REG27__VGT_EFF1_REQ__SHIFT 0x0000001b +#define MH_DEBUG_REG27__TC_EFF1_REQ__SHIFT 0x0000001c +#define MH_DEBUG_REG27__RB_EFF1_REQ__SHIFT 0x0000001d +#define MH_DEBUG_REG27__TCD_NEARFULL_q__SHIFT 0x0000001e +#define MH_DEBUG_REG27__TCHOLD_IP_q__SHIFT 0x0000001f + +// MH_DEBUG_REG28 +#define MH_DEBUG_REG28__EFF1_WINNER__SHIFT 0x00000000 +#define MH_DEBUG_REG28__ARB_WINNER__SHIFT 0x00000003 +#define MH_DEBUG_REG28__CP_SEND_QUAL__SHIFT 0x00000006 +#define MH_DEBUG_REG28__VGT_SEND_QUAL__SHIFT 0x00000007 +#define MH_DEBUG_REG28__TC_SEND_QUAL__SHIFT 0x00000008 +#define MH_DEBUG_REG28__TC_SEND_EFF1_QUAL__SHIFT 0x00000009 +#define MH_DEBUG_REG28__RB_SEND_QUAL__SHIFT 0x0000000a +#define MH_DEBUG_REG28__ARB_QUAL__SHIFT 0x0000000b +#define MH_DEBUG_REG28__CP_EFF1_REQ__SHIFT 0x0000000c +#define MH_DEBUG_REG28__VGT_EFF1_REQ__SHIFT 0x0000000d +#define MH_DEBUG_REG28__TC_EFF1_REQ__SHIFT 0x0000000e +#define MH_DEBUG_REG28__RB_EFF1_REQ__SHIFT 0x0000000f +#define MH_DEBUG_REG28__EFF1_WIN__SHIFT 0x00000010 +#define MH_DEBUG_REG28__KILL_EFF1__SHIFT 0x00000011 +#define MH_DEBUG_REG28__TCD_NEARFULL_q__SHIFT 0x00000012 +#define MH_DEBUG_REG28__TC_ARB_HOLD__SHIFT 0x00000013 +#define MH_DEBUG_REG28__ARB_HOLD__SHIFT 0x00000014 +#define MH_DEBUG_REG28__ARB_RTR_q__SHIFT 0x00000015 +#define MH_DEBUG_REG28__SAME_PAGE_LIMIT_COUNT_q__SHIFT 0x00000016 + +// MH_DEBUG_REG29 +#define MH_DEBUG_REG29__EFF2_LRU_WINNER_out__SHIFT 0x00000000 +#define MH_DEBUG_REG29__LEAST_RECENT_INDEX_d__SHIFT 0x00000003 +#define MH_DEBUG_REG29__LEAST_RECENT_d__SHIFT 0x00000006 +#define MH_DEBUG_REG29__UPDATE_RECENT_STACK_d__SHIFT 0x00000009 +#define MH_DEBUG_REG29__ARB_HOLD__SHIFT 0x0000000a +#define MH_DEBUG_REG29__ARB_RTR_q__SHIFT 0x0000000b +#define MH_DEBUG_REG29__CLNT_REQ__SHIFT 0x0000000c +#define MH_DEBUG_REG29__RECENT_d_0__SHIFT 0x00000011 +#define MH_DEBUG_REG29__RECENT_d_1__SHIFT 0x00000014 +#define MH_DEBUG_REG29__RECENT_d_2__SHIFT 0x00000017 +#define MH_DEBUG_REG29__RECENT_d_3__SHIFT 0x0000001a +#define MH_DEBUG_REG29__RECENT_d_4__SHIFT 0x0000001d + +// MH_DEBUG_REG30 +#define MH_DEBUG_REG30__TC_ARB_HOLD__SHIFT 0x00000000 +#define MH_DEBUG_REG30__TC_NOROQ_SAME_ROW_BANK__SHIFT 0x00000001 +#define MH_DEBUG_REG30__TC_ROQ_SAME_ROW_BANK__SHIFT 0x00000002 +#define MH_DEBUG_REG30__TCD_NEARFULL_q__SHIFT 0x00000003 +#define MH_DEBUG_REG30__TCHOLD_IP_q__SHIFT 0x00000004 +#define MH_DEBUG_REG30__TCHOLD_CNT_q__SHIFT 0x00000005 +#define MH_DEBUG_REG30__MH_ARBITER_CONFIG_TC_REORDER_ENABLE__SHIFT 0x00000008 +#define MH_DEBUG_REG30__TC_ROQ_RTR_DBG_q__SHIFT 0x00000009 +#define MH_DEBUG_REG30__TC_ROQ_SEND_q__SHIFT 0x0000000a +#define MH_DEBUG_REG30__TC_MH_written__SHIFT 0x0000000b +#define MH_DEBUG_REG30__TCD_FULLNESS_CNT_q__SHIFT 0x0000000c +#define MH_DEBUG_REG30__WBURST_ACTIVE__SHIFT 0x00000013 +#define MH_DEBUG_REG30__WLAST_q__SHIFT 0x00000014 +#define MH_DEBUG_REG30__WBURST_IP_q__SHIFT 0x00000015 +#define MH_DEBUG_REG30__WBURST_CNT_q__SHIFT 0x00000016 +#define MH_DEBUG_REG30__CP_SEND_QUAL__SHIFT 0x00000019 +#define MH_DEBUG_REG30__CP_MH_write__SHIFT 0x0000001a +#define MH_DEBUG_REG30__RB_SEND_QUAL__SHIFT 0x0000001b +#define MH_DEBUG_REG30__PA_SEND_QUAL__SHIFT 0x0000001c +#define MH_DEBUG_REG30__ARB_WINNER__SHIFT 0x0000001d + +// MH_DEBUG_REG31 +#define MH_DEBUG_REG31__RF_ARBITER_CONFIG_q__SHIFT 0x00000000 +#define MH_DEBUG_REG31__MH_CLNT_AXI_ID_REUSE_MMUr_ID__SHIFT 0x0000001a + +// MH_DEBUG_REG32 +#define MH_DEBUG_REG32__SAME_ROW_BANK_q__SHIFT 0x00000000 +#define MH_DEBUG_REG32__ROQ_MARK_q__SHIFT 0x00000008 +#define MH_DEBUG_REG32__ROQ_VALID_q__SHIFT 0x00000010 +#define MH_DEBUG_REG32__TC_MH_send__SHIFT 0x00000018 +#define MH_DEBUG_REG32__TC_ROQ_RTR_q__SHIFT 0x00000019 +#define MH_DEBUG_REG32__KILL_EFF1__SHIFT 0x0000001a +#define MH_DEBUG_REG32__TC_ROQ_SAME_ROW_BANK_SEL__SHIFT 0x0000001b +#define MH_DEBUG_REG32__ANY_SAME_ROW_BANK__SHIFT 0x0000001c +#define MH_DEBUG_REG32__TC_EFF1_QUAL__SHIFT 0x0000001d +#define MH_DEBUG_REG32__TC_ROQ_EMPTY__SHIFT 0x0000001e +#define MH_DEBUG_REG32__TC_ROQ_FULL__SHIFT 0x0000001f + +// MH_DEBUG_REG33 +#define MH_DEBUG_REG33__SAME_ROW_BANK_q__SHIFT 0x00000000 +#define MH_DEBUG_REG33__ROQ_MARK_d__SHIFT 0x00000008 +#define MH_DEBUG_REG33__ROQ_VALID_d__SHIFT 0x00000010 +#define MH_DEBUG_REG33__TC_MH_send__SHIFT 0x00000018 +#define MH_DEBUG_REG33__TC_ROQ_RTR_q__SHIFT 0x00000019 +#define MH_DEBUG_REG33__KILL_EFF1__SHIFT 0x0000001a +#define MH_DEBUG_REG33__TC_ROQ_SAME_ROW_BANK_SEL__SHIFT 0x0000001b +#define MH_DEBUG_REG33__ANY_SAME_ROW_BANK__SHIFT 0x0000001c +#define MH_DEBUG_REG33__TC_EFF1_QUAL__SHIFT 0x0000001d +#define MH_DEBUG_REG33__TC_ROQ_EMPTY__SHIFT 0x0000001e +#define MH_DEBUG_REG33__TC_ROQ_FULL__SHIFT 0x0000001f + +// MH_DEBUG_REG34 +#define MH_DEBUG_REG34__SAME_ROW_BANK_WIN__SHIFT 0x00000000 +#define MH_DEBUG_REG34__SAME_ROW_BANK_REQ__SHIFT 0x00000008 +#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_WIN__SHIFT 0x00000010 +#define MH_DEBUG_REG34__NON_SAME_ROW_BANK_REQ__SHIFT 0x00000018 + +// MH_DEBUG_REG35 +#define MH_DEBUG_REG35__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG35__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG35__ROQ_MARK_q_0__SHIFT 0x00000002 +#define MH_DEBUG_REG35__ROQ_VALID_q_0__SHIFT 0x00000003 +#define MH_DEBUG_REG35__SAME_ROW_BANK_q_0__SHIFT 0x00000004 +#define MH_DEBUG_REG35__ROQ_ADDR_0__SHIFT 0x00000005 + +// MH_DEBUG_REG36 +#define MH_DEBUG_REG36__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG36__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG36__ROQ_MARK_q_1__SHIFT 0x00000002 +#define MH_DEBUG_REG36__ROQ_VALID_q_1__SHIFT 0x00000003 +#define MH_DEBUG_REG36__SAME_ROW_BANK_q_1__SHIFT 0x00000004 +#define MH_DEBUG_REG36__ROQ_ADDR_1__SHIFT 0x00000005 + +// MH_DEBUG_REG37 +#define MH_DEBUG_REG37__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG37__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG37__ROQ_MARK_q_2__SHIFT 0x00000002 +#define MH_DEBUG_REG37__ROQ_VALID_q_2__SHIFT 0x00000003 +#define MH_DEBUG_REG37__SAME_ROW_BANK_q_2__SHIFT 0x00000004 +#define MH_DEBUG_REG37__ROQ_ADDR_2__SHIFT 0x00000005 + +// MH_DEBUG_REG38 +#define MH_DEBUG_REG38__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG38__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG38__ROQ_MARK_q_3__SHIFT 0x00000002 +#define MH_DEBUG_REG38__ROQ_VALID_q_3__SHIFT 0x00000003 +#define MH_DEBUG_REG38__SAME_ROW_BANK_q_3__SHIFT 0x00000004 +#define MH_DEBUG_REG38__ROQ_ADDR_3__SHIFT 0x00000005 + +// MH_DEBUG_REG39 +#define MH_DEBUG_REG39__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG39__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG39__ROQ_MARK_q_4__SHIFT 0x00000002 +#define MH_DEBUG_REG39__ROQ_VALID_q_4__SHIFT 0x00000003 +#define MH_DEBUG_REG39__SAME_ROW_BANK_q_4__SHIFT 0x00000004 +#define MH_DEBUG_REG39__ROQ_ADDR_4__SHIFT 0x00000005 + +// MH_DEBUG_REG40 +#define MH_DEBUG_REG40__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG40__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG40__ROQ_MARK_q_5__SHIFT 0x00000002 +#define MH_DEBUG_REG40__ROQ_VALID_q_5__SHIFT 0x00000003 +#define MH_DEBUG_REG40__SAME_ROW_BANK_q_5__SHIFT 0x00000004 +#define MH_DEBUG_REG40__ROQ_ADDR_5__SHIFT 0x00000005 + +// MH_DEBUG_REG41 +#define MH_DEBUG_REG41__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG41__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG41__ROQ_MARK_q_6__SHIFT 0x00000002 +#define MH_DEBUG_REG41__ROQ_VALID_q_6__SHIFT 0x00000003 +#define MH_DEBUG_REG41__SAME_ROW_BANK_q_6__SHIFT 0x00000004 +#define MH_DEBUG_REG41__ROQ_ADDR_6__SHIFT 0x00000005 + +// MH_DEBUG_REG42 +#define MH_DEBUG_REG42__TC_MH_send__SHIFT 0x00000000 +#define MH_DEBUG_REG42__TC_ROQ_RTR_q__SHIFT 0x00000001 +#define MH_DEBUG_REG42__ROQ_MARK_q_7__SHIFT 0x00000002 +#define MH_DEBUG_REG42__ROQ_VALID_q_7__SHIFT 0x00000003 +#define MH_DEBUG_REG42__SAME_ROW_BANK_q_7__SHIFT 0x00000004 +#define MH_DEBUG_REG42__ROQ_ADDR_7__SHIFT 0x00000005 + +// MH_DEBUG_REG43 +#define MH_DEBUG_REG43__ARB_REG_WE_q__SHIFT 0x00000000 +#define MH_DEBUG_REG43__ARB_WE__SHIFT 0x00000001 +#define MH_DEBUG_REG43__ARB_REG_VALID_q__SHIFT 0x00000002 +#define MH_DEBUG_REG43__ARB_RTR_q__SHIFT 0x00000003 +#define MH_DEBUG_REG43__ARB_REG_RTR__SHIFT 0x00000004 +#define MH_DEBUG_REG43__WDAT_BURST_RTR__SHIFT 0x00000005 +#define MH_DEBUG_REG43__MMU_RTR__SHIFT 0x00000006 +#define MH_DEBUG_REG43__ARB_ID_q__SHIFT 0x00000007 +#define MH_DEBUG_REG43__ARB_WRITE_q__SHIFT 0x0000000a +#define MH_DEBUG_REG43__ARB_BLEN_q__SHIFT 0x0000000b +#define MH_DEBUG_REG43__ARQ_CTRL_EMPTY__SHIFT 0x0000000c +#define MH_DEBUG_REG43__ARQ_FIFO_CNT_q__SHIFT 0x0000000d +#define MH_DEBUG_REG43__MMU_WE__SHIFT 0x00000010 +#define MH_DEBUG_REG43__ARQ_RTR__SHIFT 0x00000011 +#define MH_DEBUG_REG43__MMU_ID__SHIFT 0x00000012 +#define MH_DEBUG_REG43__MMU_WRITE__SHIFT 0x00000015 +#define MH_DEBUG_REG43__MMU_BLEN__SHIFT 0x00000016 +#define MH_DEBUG_REG43__WBURST_IP_q__SHIFT 0x00000017 +#define MH_DEBUG_REG43__WDAT_REG_WE_q__SHIFT 0x00000018 +#define MH_DEBUG_REG43__WDB_WE__SHIFT 0x00000019 +#define MH_DEBUG_REG43__WDB_RTR_SKID_4__SHIFT 0x0000001a +#define MH_DEBUG_REG43__WDB_RTR_SKID_3__SHIFT 0x0000001b + +// MH_DEBUG_REG44 +#define MH_DEBUG_REG44__ARB_WE__SHIFT 0x00000000 +#define MH_DEBUG_REG44__ARB_ID_q__SHIFT 0x00000001 +#define MH_DEBUG_REG44__ARB_VAD_q__SHIFT 0x00000004 + +// MH_DEBUG_REG45 +#define MH_DEBUG_REG45__MMU_WE__SHIFT 0x00000000 +#define MH_DEBUG_REG45__MMU_ID__SHIFT 0x00000001 +#define MH_DEBUG_REG45__MMU_PAD__SHIFT 0x00000004 + +// MH_DEBUG_REG46 +#define MH_DEBUG_REG46__WDAT_REG_WE_q__SHIFT 0x00000000 +#define MH_DEBUG_REG46__WDB_WE__SHIFT 0x00000001 +#define MH_DEBUG_REG46__WDAT_REG_VALID_q__SHIFT 0x00000002 +#define MH_DEBUG_REG46__WDB_RTR_SKID_4__SHIFT 0x00000003 +#define MH_DEBUG_REG46__ARB_WSTRB_q__SHIFT 0x00000004 +#define MH_DEBUG_REG46__ARB_WLAST__SHIFT 0x0000000c +#define MH_DEBUG_REG46__WDB_CTRL_EMPTY__SHIFT 0x0000000d +#define MH_DEBUG_REG46__WDB_FIFO_CNT_q__SHIFT 0x0000000e +#define MH_DEBUG_REG46__WDC_WDB_RE_q__SHIFT 0x00000013 +#define MH_DEBUG_REG46__WDB_WDC_WID__SHIFT 0x00000014 +#define MH_DEBUG_REG46__WDB_WDC_WLAST__SHIFT 0x00000017 +#define MH_DEBUG_REG46__WDB_WDC_WSTRB__SHIFT 0x00000018 + +// MH_DEBUG_REG47 +#define MH_DEBUG_REG47__WDB_WDC_WDATA_31_0__SHIFT 0x00000000 + +// MH_DEBUG_REG48 +#define MH_DEBUG_REG48__WDB_WDC_WDATA_63_32__SHIFT 0x00000000 + +// MH_DEBUG_REG49 +#define MH_DEBUG_REG49__CTRL_ARC_EMPTY__SHIFT 0x00000000 +#define MH_DEBUG_REG49__CTRL_RARC_EMPTY__SHIFT 0x00000001 +#define MH_DEBUG_REG49__ARQ_CTRL_EMPTY__SHIFT 0x00000002 +#define MH_DEBUG_REG49__ARQ_CTRL_WRITE__SHIFT 0x00000003 +#define MH_DEBUG_REG49__TLBMISS_CTRL_RTS__SHIFT 0x00000004 +#define MH_DEBUG_REG49__CTRL_TLBMISS_RE_q__SHIFT 0x00000005 +#define MH_DEBUG_REG49__INFLT_LIMIT_q__SHIFT 0x00000006 +#define MH_DEBUG_REG49__INFLT_LIMIT_CNT_q__SHIFT 0x00000007 +#define MH_DEBUG_REG49__ARC_CTRL_RE_q__SHIFT 0x0000000d +#define MH_DEBUG_REG49__RARC_CTRL_RE_q__SHIFT 0x0000000e +#define MH_DEBUG_REG49__RVALID_q__SHIFT 0x0000000f +#define MH_DEBUG_REG49__RREADY_q__SHIFT 0x00000010 +#define MH_DEBUG_REG49__RLAST_q__SHIFT 0x00000011 +#define MH_DEBUG_REG49__BVALID_q__SHIFT 0x00000012 +#define MH_DEBUG_REG49__BREADY_q__SHIFT 0x00000013 + +// MH_DEBUG_REG50 +#define MH_DEBUG_REG50__MH_CP_grb_send__SHIFT 0x00000000 +#define MH_DEBUG_REG50__MH_VGT_grb_send__SHIFT 0x00000001 +#define MH_DEBUG_REG50__MH_TC_mcsend__SHIFT 0x00000002 +#define MH_DEBUG_REG50__MH_TLBMISS_SEND__SHIFT 0x00000003 +#define MH_DEBUG_REG50__TLBMISS_VALID__SHIFT 0x00000004 +#define MH_DEBUG_REG50__RDC_VALID__SHIFT 0x00000005 +#define MH_DEBUG_REG50__RDC_RID__SHIFT 0x00000006 +#define MH_DEBUG_REG50__RDC_RLAST__SHIFT 0x00000009 +#define MH_DEBUG_REG50__RDC_RRESP__SHIFT 0x0000000a +#define MH_DEBUG_REG50__TLBMISS_CTRL_RTS__SHIFT 0x0000000c +#define MH_DEBUG_REG50__CTRL_TLBMISS_RE_q__SHIFT 0x0000000d +#define MH_DEBUG_REG50__MMU_ID_REQUEST_q__SHIFT 0x0000000e +#define MH_DEBUG_REG50__OUTSTANDING_MMUID_CNT_q__SHIFT 0x0000000f +#define MH_DEBUG_REG50__MMU_ID_RESPONSE__SHIFT 0x00000015 +#define MH_DEBUG_REG50__TLBMISS_RETURN_CNT_q__SHIFT 0x00000016 +#define MH_DEBUG_REG50__CNT_HOLD_q1__SHIFT 0x0000001c +#define MH_DEBUG_REG50__MH_CLNT_AXI_ID_REUSE_MMUr_ID__SHIFT 0x0000001d + +// MH_DEBUG_REG51 +#define MH_DEBUG_REG51__RF_MMU_PAGE_FAULT__SHIFT 0x00000000 + +// MH_DEBUG_REG52 +#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_1_to_0__SHIFT 0x00000000 +#define MH_DEBUG_REG52__ARB_WE__SHIFT 0x00000002 +#define MH_DEBUG_REG52__MMU_RTR__SHIFT 0x00000003 +#define MH_DEBUG_REG52__RF_MMU_CONFIG_q_25_to_4__SHIFT 0x00000004 +#define MH_DEBUG_REG52__ARB_ID_q__SHIFT 0x0000001a +#define MH_DEBUG_REG52__ARB_WRITE_q__SHIFT 0x0000001d +#define MH_DEBUG_REG52__client_behavior_q__SHIFT 0x0000001e + +// MH_DEBUG_REG53 +#define MH_DEBUG_REG53__stage1_valid__SHIFT 0x00000000 +#define MH_DEBUG_REG53__IGNORE_TAG_MISS_q__SHIFT 0x00000001 +#define MH_DEBUG_REG53__pa_in_mpu_range__SHIFT 0x00000002 +#define MH_DEBUG_REG53__tag_match_q__SHIFT 0x00000003 +#define MH_DEBUG_REG53__tag_miss_q__SHIFT 0x00000004 +#define MH_DEBUG_REG53__va_in_range_q__SHIFT 0x00000005 +#define MH_DEBUG_REG53__MMU_MISS__SHIFT 0x00000006 +#define MH_DEBUG_REG53__MMU_READ_MISS__SHIFT 0x00000007 +#define MH_DEBUG_REG53__MMU_WRITE_MISS__SHIFT 0x00000008 +#define MH_DEBUG_REG53__MMU_HIT__SHIFT 0x00000009 +#define MH_DEBUG_REG53__MMU_READ_HIT__SHIFT 0x0000000a +#define MH_DEBUG_REG53__MMU_WRITE_HIT__SHIFT 0x0000000b +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_MISS__SHIFT 0x0000000c +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_TC_HIT__SHIFT 0x0000000d +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_MISS__SHIFT 0x0000000e +#define MH_DEBUG_REG53__MMU_SPLIT_MODE_nonTC_HIT__SHIFT 0x0000000f +#define MH_DEBUG_REG53__REQ_VA_OFFSET_q__SHIFT 0x00000010 + +// MH_DEBUG_REG54 +#define MH_DEBUG_REG54__ARQ_RTR__SHIFT 0x00000000 +#define MH_DEBUG_REG54__MMU_WE__SHIFT 0x00000001 +#define MH_DEBUG_REG54__CTRL_TLBMISS_RE_q__SHIFT 0x00000002 +#define MH_DEBUG_REG54__TLBMISS_CTRL_RTS__SHIFT 0x00000003 +#define MH_DEBUG_REG54__MH_TLBMISS_SEND__SHIFT 0x00000004 +#define MH_DEBUG_REG54__MMU_STALL_AWAITING_TLB_MISS_FETCH__SHIFT 0x00000005 +#define MH_DEBUG_REG54__pa_in_mpu_range__SHIFT 0x00000006 +#define MH_DEBUG_REG54__stage1_valid__SHIFT 0x00000007 +#define MH_DEBUG_REG54__stage2_valid__SHIFT 0x00000008 +#define MH_DEBUG_REG54__client_behavior_q__SHIFT 0x00000009 +#define MH_DEBUG_REG54__IGNORE_TAG_MISS_q__SHIFT 0x0000000b +#define MH_DEBUG_REG54__tag_match_q__SHIFT 0x0000000c +#define MH_DEBUG_REG54__tag_miss_q__SHIFT 0x0000000d +#define MH_DEBUG_REG54__va_in_range_q__SHIFT 0x0000000e +#define MH_DEBUG_REG54__PTE_FETCH_COMPLETE_q__SHIFT 0x0000000f +#define MH_DEBUG_REG54__TAG_valid_q__SHIFT 0x00000010 + +// MH_DEBUG_REG55 +#define MH_DEBUG_REG55__TAG0_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG55__TAG_valid_q_0__SHIFT 0x0000000d +#define MH_DEBUG_REG55__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG55__TAG1_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG55__TAG_valid_q_1__SHIFT 0x0000001d + +// MH_DEBUG_REG56 +#define MH_DEBUG_REG56__TAG2_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG56__TAG_valid_q_2__SHIFT 0x0000000d +#define MH_DEBUG_REG56__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG56__TAG3_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG56__TAG_valid_q_3__SHIFT 0x0000001d + +// MH_DEBUG_REG57 +#define MH_DEBUG_REG57__TAG4_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG57__TAG_valid_q_4__SHIFT 0x0000000d +#define MH_DEBUG_REG57__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG57__TAG5_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG57__TAG_valid_q_5__SHIFT 0x0000001d + +// MH_DEBUG_REG58 +#define MH_DEBUG_REG58__TAG6_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG58__TAG_valid_q_6__SHIFT 0x0000000d +#define MH_DEBUG_REG58__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG58__TAG7_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG58__TAG_valid_q_7__SHIFT 0x0000001d + +// MH_DEBUG_REG59 +#define MH_DEBUG_REG59__TAG8_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG59__TAG_valid_q_8__SHIFT 0x0000000d +#define MH_DEBUG_REG59__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG59__TAG9_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG59__TAG_valid_q_9__SHIFT 0x0000001d + +// MH_DEBUG_REG60 +#define MH_DEBUG_REG60__TAG10_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG60__TAG_valid_q_10__SHIFT 0x0000000d +#define MH_DEBUG_REG60__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG60__TAG11_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG60__TAG_valid_q_11__SHIFT 0x0000001d + +// MH_DEBUG_REG61 +#define MH_DEBUG_REG61__TAG12_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG61__TAG_valid_q_12__SHIFT 0x0000000d +#define MH_DEBUG_REG61__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG61__TAG13_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG61__TAG_valid_q_13__SHIFT 0x0000001d + +// MH_DEBUG_REG62 +#define MH_DEBUG_REG62__TAG14_VA__SHIFT 0x00000000 +#define MH_DEBUG_REG62__TAG_valid_q_14__SHIFT 0x0000000d +#define MH_DEBUG_REG62__ALWAYS_ZERO__SHIFT 0x0000000e +#define MH_DEBUG_REG62__TAG15_VA__SHIFT 0x00000010 +#define MH_DEBUG_REG62__TAG_valid_q_15__SHIFT 0x0000001d + +// MH_DEBUG_REG63 +#define MH_DEBUG_REG63__MH_DBG_DEFAULT__SHIFT 0x00000000 + +// MH_MMU_CONFIG +#define MH_MMU_CONFIG__MMU_ENABLE__SHIFT 0x00000000 +#define MH_MMU_CONFIG__SPLIT_MODE_ENABLE__SHIFT 0x00000001 +#define MH_MMU_CONFIG__RESERVED1__SHIFT 0x00000002 +#define MH_MMU_CONFIG__RB_W_CLNT_BEHAVIOR__SHIFT 0x00000004 +#define MH_MMU_CONFIG__CP_W_CLNT_BEHAVIOR__SHIFT 0x00000006 +#define MH_MMU_CONFIG__CP_R0_CLNT_BEHAVIOR__SHIFT 0x00000008 +#define MH_MMU_CONFIG__CP_R1_CLNT_BEHAVIOR__SHIFT 0x0000000a +#define MH_MMU_CONFIG__CP_R2_CLNT_BEHAVIOR__SHIFT 0x0000000c +#define MH_MMU_CONFIG__CP_R3_CLNT_BEHAVIOR__SHIFT 0x0000000e +#define MH_MMU_CONFIG__CP_R4_CLNT_BEHAVIOR__SHIFT 0x00000010 +#define MH_MMU_CONFIG__VGT_R0_CLNT_BEHAVIOR__SHIFT 0x00000012 +#define MH_MMU_CONFIG__VGT_R1_CLNT_BEHAVIOR__SHIFT 0x00000014 +#define MH_MMU_CONFIG__TC_R_CLNT_BEHAVIOR__SHIFT 0x00000016 +#define MH_MMU_CONFIG__PA_W_CLNT_BEHAVIOR__SHIFT 0x00000018 + +// MH_MMU_VA_RANGE +#define MH_MMU_VA_RANGE__NUM_64KB_REGIONS__SHIFT 0x00000000 +#define MH_MMU_VA_RANGE__VA_BASE__SHIFT 0x0000000c + +// MH_MMU_PT_BASE +#define MH_MMU_PT_BASE__PT_BASE__SHIFT 0x0000000c + +// MH_MMU_PAGE_FAULT +#define MH_MMU_PAGE_FAULT__PAGE_FAULT__SHIFT 0x00000000 +#define MH_MMU_PAGE_FAULT__OP_TYPE__SHIFT 0x00000001 +#define MH_MMU_PAGE_FAULT__CLNT_BEHAVIOR__SHIFT 0x00000002 +#define MH_MMU_PAGE_FAULT__AXI_ID__SHIFT 0x00000004 +#define MH_MMU_PAGE_FAULT__RESERVED1__SHIFT 0x00000007 +#define MH_MMU_PAGE_FAULT__MPU_ADDRESS_OUT_OF_RANGE__SHIFT 0x00000008 +#define MH_MMU_PAGE_FAULT__ADDRESS_OUT_OF_RANGE__SHIFT 0x00000009 +#define MH_MMU_PAGE_FAULT__READ_PROTECTION_ERROR__SHIFT 0x0000000a +#define MH_MMU_PAGE_FAULT__WRITE_PROTECTION_ERROR__SHIFT 0x0000000b +#define MH_MMU_PAGE_FAULT__REQ_VA__SHIFT 0x0000000c + +// MH_MMU_TRAN_ERROR +#define MH_MMU_TRAN_ERROR__TRAN_ERROR__SHIFT 0x00000005 + +// MH_MMU_INVALIDATE +#define MH_MMU_INVALIDATE__INVALIDATE_ALL__SHIFT 0x00000000 +#define MH_MMU_INVALIDATE__INVALIDATE_TC__SHIFT 0x00000001 + +// MH_MMU_MPU_BASE +#define MH_MMU_MPU_BASE__MPU_BASE__SHIFT 0x0000000c + +// MH_MMU_MPU_END +#define MH_MMU_MPU_END__MPU_END__SHIFT 0x0000000c + +// WAIT_UNTIL +#define WAIT_UNTIL__WAIT_RE_VSYNC__SHIFT 0x00000001 +#define WAIT_UNTIL__WAIT_FE_VSYNC__SHIFT 0x00000002 +#define WAIT_UNTIL__WAIT_VSYNC__SHIFT 0x00000003 +#define WAIT_UNTIL__WAIT_DSPLY_ID0__SHIFT 0x00000004 +#define WAIT_UNTIL__WAIT_DSPLY_ID1__SHIFT 0x00000005 +#define WAIT_UNTIL__WAIT_DSPLY_ID2__SHIFT 0x00000006 +#define WAIT_UNTIL__WAIT_CMDFIFO__SHIFT 0x0000000a +#define WAIT_UNTIL__WAIT_2D_IDLE__SHIFT 0x0000000e +#define WAIT_UNTIL__WAIT_3D_IDLE__SHIFT 0x0000000f +#define WAIT_UNTIL__WAIT_2D_IDLECLEAN__SHIFT 0x00000010 +#define WAIT_UNTIL__WAIT_3D_IDLECLEAN__SHIFT 0x00000011 +#define WAIT_UNTIL__CMDFIFO_ENTRIES__SHIFT 0x00000014 + +// RBBM_ISYNC_CNTL +#define RBBM_ISYNC_CNTL__ISYNC_WAIT_IDLEGUI__SHIFT 0x00000004 +#define RBBM_ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI__SHIFT 0x00000005 + +// RBBM_STATUS +#define RBBM_STATUS__CMDFIFO_AVAIL__SHIFT 0x00000000 +#define RBBM_STATUS__TC_BUSY__SHIFT 0x00000005 +#define RBBM_STATUS__HIRQ_PENDING__SHIFT 0x00000008 +#define RBBM_STATUS__CPRQ_PENDING__SHIFT 0x00000009 +#define RBBM_STATUS__CFRQ_PENDING__SHIFT 0x0000000a +#define RBBM_STATUS__PFRQ_PENDING__SHIFT 0x0000000b +#define RBBM_STATUS__VGT_BUSY_NO_DMA__SHIFT 0x0000000c +#define RBBM_STATUS__RBBM_WU_BUSY__SHIFT 0x0000000e +#define RBBM_STATUS__CP_NRT_BUSY__SHIFT 0x00000010 +#define RBBM_STATUS__MH_BUSY__SHIFT 0x00000012 +#define RBBM_STATUS__MH_COHERENCY_BUSY__SHIFT 0x00000013 +#define RBBM_STATUS__SX_BUSY__SHIFT 0x00000015 +#define RBBM_STATUS__TPC_BUSY__SHIFT 0x00000016 +#define RBBM_STATUS__SC_CNTX_BUSY__SHIFT 0x00000018 +#define RBBM_STATUS__PA_BUSY__SHIFT 0x00000019 +#define RBBM_STATUS__VGT_BUSY__SHIFT 0x0000001a +#define RBBM_STATUS__SQ_CNTX17_BUSY__SHIFT 0x0000001b +#define RBBM_STATUS__SQ_CNTX0_BUSY__SHIFT 0x0000001c +#define RBBM_STATUS__RB_CNTX_BUSY__SHIFT 0x0000001e +#define RBBM_STATUS__GUI_ACTIVE__SHIFT 0x0000001f + +// RBBM_DSPLY +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID0__SHIFT 0x00000000 +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID1__SHIFT 0x00000001 +#define RBBM_DSPLY__SEL_DMI_ACTIVE_BUFID2__SHIFT 0x00000002 +#define RBBM_DSPLY__SEL_DMI_VSYNC_VALID__SHIFT 0x00000003 +#define RBBM_DSPLY__DMI_CH1_USE_BUFID0__SHIFT 0x00000004 +#define RBBM_DSPLY__DMI_CH1_USE_BUFID1__SHIFT 0x00000005 +#define RBBM_DSPLY__DMI_CH1_USE_BUFID2__SHIFT 0x00000006 +#define RBBM_DSPLY__DMI_CH1_SW_CNTL__SHIFT 0x00000007 +#define RBBM_DSPLY__DMI_CH1_NUM_BUFS__SHIFT 0x00000008 +#define RBBM_DSPLY__DMI_CH2_USE_BUFID0__SHIFT 0x0000000a +#define RBBM_DSPLY__DMI_CH2_USE_BUFID1__SHIFT 0x0000000b +#define RBBM_DSPLY__DMI_CH2_USE_BUFID2__SHIFT 0x0000000c +#define RBBM_DSPLY__DMI_CH2_SW_CNTL__SHIFT 0x0000000d +#define RBBM_DSPLY__DMI_CH2_NUM_BUFS__SHIFT 0x0000000e +#define RBBM_DSPLY__DMI_CHANNEL_SELECT__SHIFT 0x00000010 +#define RBBM_DSPLY__DMI_CH3_USE_BUFID0__SHIFT 0x00000014 +#define RBBM_DSPLY__DMI_CH3_USE_BUFID1__SHIFT 0x00000015 +#define RBBM_DSPLY__DMI_CH3_USE_BUFID2__SHIFT 0x00000016 +#define RBBM_DSPLY__DMI_CH3_SW_CNTL__SHIFT 0x00000017 +#define RBBM_DSPLY__DMI_CH3_NUM_BUFS__SHIFT 0x00000018 +#define RBBM_DSPLY__DMI_CH4_USE_BUFID0__SHIFT 0x0000001a +#define RBBM_DSPLY__DMI_CH4_USE_BUFID1__SHIFT 0x0000001b +#define RBBM_DSPLY__DMI_CH4_USE_BUFID2__SHIFT 0x0000001c +#define RBBM_DSPLY__DMI_CH4_SW_CNTL__SHIFT 0x0000001d +#define RBBM_DSPLY__DMI_CH4_NUM_BUFS__SHIFT 0x0000001e + +// RBBM_RENDER_LATEST +#define RBBM_RENDER_LATEST__DMI_CH1_BUFFER_ID__SHIFT 0x00000000 +#define RBBM_RENDER_LATEST__DMI_CH2_BUFFER_ID__SHIFT 0x00000008 +#define RBBM_RENDER_LATEST__DMI_CH3_BUFFER_ID__SHIFT 0x00000010 +#define RBBM_RENDER_LATEST__DMI_CH4_BUFFER_ID__SHIFT 0x00000018 + +// RBBM_RTL_RELEASE +#define RBBM_RTL_RELEASE__CHANGELIST__SHIFT 0x00000000 + +// RBBM_PATCH_RELEASE +#define RBBM_PATCH_RELEASE__PATCH_REVISION__SHIFT 0x00000000 +#define RBBM_PATCH_RELEASE__PATCH_SELECTION__SHIFT 0x00000010 +#define RBBM_PATCH_RELEASE__CUSTOMER_ID__SHIFT 0x00000018 + +// RBBM_AUXILIARY_CONFIG +#define RBBM_AUXILIARY_CONFIG__RESERVED__SHIFT 0x00000000 + +// RBBM_PERIPHID0 +#define RBBM_PERIPHID0__PARTNUMBER0__SHIFT 0x00000000 + +// RBBM_PERIPHID1 +#define RBBM_PERIPHID1__PARTNUMBER1__SHIFT 0x00000000 +#define RBBM_PERIPHID1__DESIGNER0__SHIFT 0x00000004 + +// RBBM_PERIPHID2 +#define RBBM_PERIPHID2__DESIGNER1__SHIFT 0x00000000 +#define RBBM_PERIPHID2__REVISION__SHIFT 0x00000004 + +// RBBM_PERIPHID3 +#define RBBM_PERIPHID3__RBBM_HOST_INTERFACE__SHIFT 0x00000000 +#define RBBM_PERIPHID3__GARB_SLAVE_INTERFACE__SHIFT 0x00000002 +#define RBBM_PERIPHID3__MH_INTERFACE__SHIFT 0x00000004 +#define RBBM_PERIPHID3__CONTINUATION__SHIFT 0x00000007 + +// RBBM_CNTL +#define RBBM_CNTL__READ_TIMEOUT__SHIFT 0x00000000 +#define RBBM_CNTL__REGCLK_DEASSERT_TIME__SHIFT 0x00000008 + +// RBBM_SKEW_CNTL +#define RBBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x00000000 +#define RBBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x00000005 + +// RBBM_SOFT_RESET +#define RBBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x00000000 +#define RBBM_SOFT_RESET__SOFT_RESET_PA__SHIFT 0x00000002 +#define RBBM_SOFT_RESET__SOFT_RESET_MH__SHIFT 0x00000003 +#define RBBM_SOFT_RESET__SOFT_RESET_BC__SHIFT 0x00000004 +#define RBBM_SOFT_RESET__SOFT_RESET_SQ__SHIFT 0x00000005 +#define RBBM_SOFT_RESET__SOFT_RESET_SX__SHIFT 0x00000006 +#define RBBM_SOFT_RESET__SOFT_RESET_CIB__SHIFT 0x0000000c +#define RBBM_SOFT_RESET__SOFT_RESET_SC__SHIFT 0x0000000f +#define RBBM_SOFT_RESET__SOFT_RESET_VGT__SHIFT 0x00000010 + +// RBBM_PM_OVERRIDE1 +#define RBBM_PM_OVERRIDE1__RBBM_AHBCLK_PM_OVERRIDE__SHIFT 0x00000000 +#define RBBM_PM_OVERRIDE1__SC_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000001 +#define RBBM_PM_OVERRIDE1__SC_SCLK_PM_OVERRIDE__SHIFT 0x00000002 +#define RBBM_PM_OVERRIDE1__SP_TOP_SCLK_PM_OVERRIDE__SHIFT 0x00000003 +#define RBBM_PM_OVERRIDE1__SP_V0_SCLK_PM_OVERRIDE__SHIFT 0x00000004 +#define RBBM_PM_OVERRIDE1__SQ_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000005 +#define RBBM_PM_OVERRIDE1__SQ_REG_FIFOS_SCLK_PM_OVERRIDE__SHIFT 0x00000006 +#define RBBM_PM_OVERRIDE1__SQ_CONST_MEM_SCLK_PM_OVERRIDE__SHIFT 0x00000007 +#define RBBM_PM_OVERRIDE1__SQ_SQ_SCLK_PM_OVERRIDE__SHIFT 0x00000008 +#define RBBM_PM_OVERRIDE1__SX_SCLK_PM_OVERRIDE__SHIFT 0x00000009 +#define RBBM_PM_OVERRIDE1__SX_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000000a +#define RBBM_PM_OVERRIDE1__TCM_TCO_SCLK_PM_OVERRIDE__SHIFT 0x0000000b +#define RBBM_PM_OVERRIDE1__TCM_TCM_SCLK_PM_OVERRIDE__SHIFT 0x0000000c +#define RBBM_PM_OVERRIDE1__TCM_TCD_SCLK_PM_OVERRIDE__SHIFT 0x0000000d +#define RBBM_PM_OVERRIDE1__TCM_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000000e +#define RBBM_PM_OVERRIDE1__TPC_TPC_SCLK_PM_OVERRIDE__SHIFT 0x0000000f +#define RBBM_PM_OVERRIDE1__TPC_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000010 +#define RBBM_PM_OVERRIDE1__TCF_TCA_SCLK_PM_OVERRIDE__SHIFT 0x00000011 +#define RBBM_PM_OVERRIDE1__TCF_TCB_SCLK_PM_OVERRIDE__SHIFT 0x00000012 +#define RBBM_PM_OVERRIDE1__TCF_TCB_READ_SCLK_PM_OVERRIDE__SHIFT 0x00000013 +#define RBBM_PM_OVERRIDE1__TP_TP_SCLK_PM_OVERRIDE__SHIFT 0x00000014 +#define RBBM_PM_OVERRIDE1__TP_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000015 +#define RBBM_PM_OVERRIDE1__CP_G_SCLK_PM_OVERRIDE__SHIFT 0x00000016 +#define RBBM_PM_OVERRIDE1__CP_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000017 +#define RBBM_PM_OVERRIDE1__CP_G_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000018 +#define RBBM_PM_OVERRIDE1__SPI_SCLK_PM_OVERRIDE__SHIFT 0x00000019 +#define RBBM_PM_OVERRIDE1__RB_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000001a +#define RBBM_PM_OVERRIDE1__RB_SCLK_PM_OVERRIDE__SHIFT 0x0000001b +#define RBBM_PM_OVERRIDE1__MH_MH_SCLK_PM_OVERRIDE__SHIFT 0x0000001c +#define RBBM_PM_OVERRIDE1__MH_REG_SCLK_PM_OVERRIDE__SHIFT 0x0000001d +#define RBBM_PM_OVERRIDE1__MH_MMU_SCLK_PM_OVERRIDE__SHIFT 0x0000001e +#define RBBM_PM_OVERRIDE1__MH_TCROQ_SCLK_PM_OVERRIDE__SHIFT 0x0000001f + +// RBBM_PM_OVERRIDE2 +#define RBBM_PM_OVERRIDE2__PA_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000000 +#define RBBM_PM_OVERRIDE2__PA_PA_SCLK_PM_OVERRIDE__SHIFT 0x00000001 +#define RBBM_PM_OVERRIDE2__PA_AG_SCLK_PM_OVERRIDE__SHIFT 0x00000002 +#define RBBM_PM_OVERRIDE2__VGT_REG_SCLK_PM_OVERRIDE__SHIFT 0x00000003 +#define RBBM_PM_OVERRIDE2__VGT_FIFOS_SCLK_PM_OVERRIDE__SHIFT 0x00000004 +#define RBBM_PM_OVERRIDE2__VGT_VGT_SCLK_PM_OVERRIDE__SHIFT 0x00000005 +#define RBBM_PM_OVERRIDE2__DEBUG_PERF_SCLK_PM_OVERRIDE__SHIFT 0x00000006 +#define RBBM_PM_OVERRIDE2__PERM_SCLK_PM_OVERRIDE__SHIFT 0x00000007 +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM0_PM_OVERRIDE__SHIFT 0x00000008 +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM1_PM_OVERRIDE__SHIFT 0x00000009 +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM2_PM_OVERRIDE__SHIFT 0x0000000a +#define RBBM_PM_OVERRIDE2__GC_GA_GMEM3_PM_OVERRIDE__SHIFT 0x0000000b + +// GC_SYS_IDLE +#define GC_SYS_IDLE__GC_SYS_IDLE_DELAY__SHIFT 0x00000000 +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_MASK__SHIFT 0x00000010 +#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP__SHIFT 0x00000018 +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI__SHIFT 0x00000019 +#define GC_SYS_IDLE__GC_SYS_URGENT_RAMP_OVERRIDE__SHIFT 0x0000001d +#define GC_SYS_IDLE__GC_SYS_WAIT_DMI_OVERRIDE__SHIFT 0x0000001e +#define GC_SYS_IDLE__GC_SYS_IDLE_OVERRIDE__SHIFT 0x0000001f + +// NQWAIT_UNTIL +#define NQWAIT_UNTIL__WAIT_GUI_IDLE__SHIFT 0x00000000 + +// RBBM_DEBUG_OUT +#define RBBM_DEBUG_OUT__DEBUG_BUS_OUT__SHIFT 0x00000000 + +// RBBM_DEBUG_CNTL +#define RBBM_DEBUG_CNTL__SUB_BLOCK_ADDR__SHIFT 0x00000000 +#define RBBM_DEBUG_CNTL__SUB_BLOCK_SEL__SHIFT 0x00000008 +#define RBBM_DEBUG_CNTL__SW_ENABLE__SHIFT 0x0000000c +#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_ADDR__SHIFT 0x00000010 +#define RBBM_DEBUG_CNTL__GPIO_SUB_BLOCK_SEL__SHIFT 0x00000018 +#define RBBM_DEBUG_CNTL__GPIO_BYTE_LANE_ENB__SHIFT 0x0000001c + +// RBBM_DEBUG +#define RBBM_DEBUG__IGNORE_RTR__SHIFT 0x00000001 +#define RBBM_DEBUG__IGNORE_CP_SCHED_WU__SHIFT 0x00000002 +#define RBBM_DEBUG__IGNORE_CP_SCHED_ISYNC__SHIFT 0x00000003 +#define RBBM_DEBUG__IGNORE_CP_SCHED_NQ_HI__SHIFT 0x00000004 +#define RBBM_DEBUG__HYSTERESIS_NRT_GUI_ACTIVE__SHIFT 0x00000008 +#define RBBM_DEBUG__IGNORE_RTR_FOR_HI__SHIFT 0x00000010 +#define RBBM_DEBUG__IGNORE_CP_RBBM_NRTRTR_FOR_HI__SHIFT 0x00000011 +#define RBBM_DEBUG__IGNORE_VGT_RBBM_NRTRTR_FOR_HI__SHIFT 0x00000012 +#define RBBM_DEBUG__IGNORE_SQ_RBBM_NRTRTR_FOR_HI__SHIFT 0x00000013 +#define RBBM_DEBUG__CP_RBBM_NRTRTR__SHIFT 0x00000014 +#define RBBM_DEBUG__VGT_RBBM_NRTRTR__SHIFT 0x00000015 +#define RBBM_DEBUG__SQ_RBBM_NRTRTR__SHIFT 0x00000016 +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR_FOR_HI__SHIFT 0x00000017 +#define RBBM_DEBUG__CLIENTS_FOR_NRT_RTR__SHIFT 0x00000018 +#define RBBM_DEBUG__IGNORE_SX_RBBM_BUSY__SHIFT 0x0000001f + +// RBBM_READ_ERROR +#define RBBM_READ_ERROR__READ_ADDRESS__SHIFT 0x00000002 +#define RBBM_READ_ERROR__READ_REQUESTER__SHIFT 0x0000001e +#define RBBM_READ_ERROR__READ_ERROR__SHIFT 0x0000001f + +// RBBM_WAIT_IDLE_CLOCKS +#define RBBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_NRT__SHIFT 0x00000000 + +// RBBM_INT_CNTL +#define RBBM_INT_CNTL__RDERR_INT_MASK__SHIFT 0x00000000 +#define RBBM_INT_CNTL__DISPLAY_UPDATE_INT_MASK__SHIFT 0x00000001 +#define RBBM_INT_CNTL__GUI_IDLE_INT_MASK__SHIFT 0x00000013 + +// RBBM_INT_STATUS +#define RBBM_INT_STATUS__RDERR_INT_STAT__SHIFT 0x00000000 +#define RBBM_INT_STATUS__DISPLAY_UPDATE_INT_STAT__SHIFT 0x00000001 +#define RBBM_INT_STATUS__GUI_IDLE_INT_STAT__SHIFT 0x00000013 + +// RBBM_INT_ACK +#define RBBM_INT_ACK__RDERR_INT_ACK__SHIFT 0x00000000 +#define RBBM_INT_ACK__DISPLAY_UPDATE_INT_ACK__SHIFT 0x00000001 +#define RBBM_INT_ACK__GUI_IDLE_INT_ACK__SHIFT 0x00000013 + +// MASTER_INT_SIGNAL +#define MASTER_INT_SIGNAL__MH_INT_STAT__SHIFT 0x00000005 +#define MASTER_INT_SIGNAL__SQ_INT_STAT__SHIFT 0x0000001a +#define MASTER_INT_SIGNAL__CP_INT_STAT__SHIFT 0x0000001e +#define MASTER_INT_SIGNAL__RBBM_INT_STAT__SHIFT 0x0000001f + +// RBBM_PERFCOUNTER1_SELECT +#define RBBM_PERFCOUNTER1_SELECT__PERF_COUNT1_SEL__SHIFT 0x00000000 + +// RBBM_PERFCOUNTER1_LO +#define RBBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT 0x00000000 + +// RBBM_PERFCOUNTER1_HI +#define RBBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT 0x00000000 + +// CP_RB_BASE +#define CP_RB_BASE__RB_BASE__SHIFT 0x00000005 + +// CP_RB_CNTL +#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x00000000 +#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x00000008 +#define CP_RB_CNTL__BUF_SWAP__SHIFT 0x00000010 +#define CP_RB_CNTL__RB_POLL_EN__SHIFT 0x00000014 +#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b +#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x0000001f + +// CP_RB_RPTR_ADDR +#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x00000000 +#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000002 + +// CP_RB_RPTR +#define CP_RB_RPTR__RB_RPTR__SHIFT 0x00000000 + +// CP_RB_RPTR_WR +#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x00000000 + +// CP_RB_WPTR +#define CP_RB_WPTR__RB_WPTR__SHIFT 0x00000000 + +// CP_RB_WPTR_DELAY +#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x00000000 +#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x0000001c + +// CP_RB_WPTR_BASE +#define CP_RB_WPTR_BASE__RB_WPTR_SWAP__SHIFT 0x00000000 +#define CP_RB_WPTR_BASE__RB_WPTR_BASE__SHIFT 0x00000002 + +// CP_IB1_BASE +#define CP_IB1_BASE__IB1_BASE__SHIFT 0x00000002 + +// CP_IB1_BUFSZ +#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x00000000 + +// CP_IB2_BASE +#define CP_IB2_BASE__IB2_BASE__SHIFT 0x00000002 + +// CP_IB2_BUFSZ +#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x00000000 + +// CP_ST_BASE +#define CP_ST_BASE__ST_BASE__SHIFT 0x00000002 + +// CP_ST_BUFSZ +#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x00000000 + +// CP_QUEUE_THRESHOLDS +#define CP_QUEUE_THRESHOLDS__CSQ_IB1_START__SHIFT 0x00000000 +#define CP_QUEUE_THRESHOLDS__CSQ_IB2_START__SHIFT 0x00000008 +#define CP_QUEUE_THRESHOLDS__CSQ_ST_START__SHIFT 0x00000010 + +// CP_MEQ_THRESHOLDS +#define CP_MEQ_THRESHOLDS__MEQ_END__SHIFT 0x00000010 +#define CP_MEQ_THRESHOLDS__ROQ_END__SHIFT 0x00000018 + +// CP_CSQ_AVAIL +#define CP_CSQ_AVAIL__CSQ_CNT_RING__SHIFT 0x00000000 +#define CP_CSQ_AVAIL__CSQ_CNT_IB1__SHIFT 0x00000008 +#define CP_CSQ_AVAIL__CSQ_CNT_IB2__SHIFT 0x00000010 + +// CP_STQ_AVAIL +#define CP_STQ_AVAIL__STQ_CNT_ST__SHIFT 0x00000000 + +// CP_MEQ_AVAIL +#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x00000000 + +// CP_CSQ_RB_STAT +#define CP_CSQ_RB_STAT__CSQ_RPTR_PRIMARY__SHIFT 0x00000000 +#define CP_CSQ_RB_STAT__CSQ_WPTR_PRIMARY__SHIFT 0x00000010 + +// CP_CSQ_IB1_STAT +#define CP_CSQ_IB1_STAT__CSQ_RPTR_INDIRECT1__SHIFT 0x00000000 +#define CP_CSQ_IB1_STAT__CSQ_WPTR_INDIRECT1__SHIFT 0x00000010 + +// CP_CSQ_IB2_STAT +#define CP_CSQ_IB2_STAT__CSQ_RPTR_INDIRECT2__SHIFT 0x00000000 +#define CP_CSQ_IB2_STAT__CSQ_WPTR_INDIRECT2__SHIFT 0x00000010 + +// CP_NON_PREFETCH_CNTRS +#define CP_NON_PREFETCH_CNTRS__IB1_COUNTER__SHIFT 0x00000000 +#define CP_NON_PREFETCH_CNTRS__IB2_COUNTER__SHIFT 0x00000008 + +// CP_STQ_ST_STAT +#define CP_STQ_ST_STAT__STQ_RPTR_ST__SHIFT 0x00000000 +#define CP_STQ_ST_STAT__STQ_WPTR_ST__SHIFT 0x00000010 + +// CP_MEQ_STAT +#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x00000000 +#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x00000010 + +// CP_MIU_TAG_STAT +#define CP_MIU_TAG_STAT__TAG_0_STAT__SHIFT 0x00000000 +#define CP_MIU_TAG_STAT__TAG_1_STAT__SHIFT 0x00000001 +#define CP_MIU_TAG_STAT__TAG_2_STAT__SHIFT 0x00000002 +#define CP_MIU_TAG_STAT__TAG_3_STAT__SHIFT 0x00000003 +#define CP_MIU_TAG_STAT__TAG_4_STAT__SHIFT 0x00000004 +#define CP_MIU_TAG_STAT__TAG_5_STAT__SHIFT 0x00000005 +#define CP_MIU_TAG_STAT__TAG_6_STAT__SHIFT 0x00000006 +#define CP_MIU_TAG_STAT__TAG_7_STAT__SHIFT 0x00000007 +#define CP_MIU_TAG_STAT__TAG_8_STAT__SHIFT 0x00000008 +#define CP_MIU_TAG_STAT__TAG_9_STAT__SHIFT 0x00000009 +#define CP_MIU_TAG_STAT__TAG_10_STAT__SHIFT 0x0000000a +#define CP_MIU_TAG_STAT__TAG_11_STAT__SHIFT 0x0000000b +#define CP_MIU_TAG_STAT__TAG_12_STAT__SHIFT 0x0000000c +#define CP_MIU_TAG_STAT__TAG_13_STAT__SHIFT 0x0000000d +#define CP_MIU_TAG_STAT__TAG_14_STAT__SHIFT 0x0000000e +#define CP_MIU_TAG_STAT__TAG_15_STAT__SHIFT 0x0000000f +#define CP_MIU_TAG_STAT__TAG_16_STAT__SHIFT 0x00000010 +#define CP_MIU_TAG_STAT__TAG_17_STAT__SHIFT 0x00000011 +#define CP_MIU_TAG_STAT__INVALID_RETURN_TAG__SHIFT 0x0000001f + +// CP_CMD_INDEX +#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x00000000 +#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x00000010 + +// CP_CMD_DATA +#define CP_CMD_DATA__CMD_DATA__SHIFT 0x00000000 + +// CP_ME_CNTL +#define CP_ME_CNTL__ME_STATMUX__SHIFT 0x00000000 +#define CP_ME_CNTL__VTX_DEALLOC_FIFO_EMPTY__SHIFT 0x00000019 +#define CP_ME_CNTL__PIX_DEALLOC_FIFO_EMPTY__SHIFT 0x0000001a +#define CP_ME_CNTL__ME_HALT__SHIFT 0x0000001c +#define CP_ME_CNTL__ME_BUSY__SHIFT 0x0000001d +#define CP_ME_CNTL__PROG_CNT_SIZE__SHIFT 0x0000001f + +// CP_ME_STATUS +#define CP_ME_STATUS__ME_DEBUG_DATA__SHIFT 0x00000000 + +// CP_ME_RAM_WADDR +#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x00000000 + +// CP_ME_RAM_RADDR +#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x00000000 + +// CP_ME_RAM_DATA +#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x00000000 + +// CP_ME_RDADDR +#define CP_ME_RDADDR__ME_RDADDR__SHIFT 0x00000000 + +// CP_DEBUG +#define CP_DEBUG__CP_DEBUG_UNUSED_22_to_0__SHIFT 0x00000000 +#define CP_DEBUG__PREDICATE_DISABLE__SHIFT 0x00000017 +#define CP_DEBUG__PROG_END_PTR_ENABLE__SHIFT 0x00000018 +#define CP_DEBUG__MIU_128BIT_WRITE_ENABLE__SHIFT 0x00000019 +#define CP_DEBUG__PREFETCH_PASS_NOPS__SHIFT 0x0000001a +#define CP_DEBUG__DYNAMIC_CLK_DISABLE__SHIFT 0x0000001b +#define CP_DEBUG__PREFETCH_MATCH_DISABLE__SHIFT 0x0000001c +#define CP_DEBUG__SIMPLE_ME_FLOW_CONTROL__SHIFT 0x0000001e +#define CP_DEBUG__MIU_WRITE_PACK_DISABLE__SHIFT 0x0000001f + +// SCRATCH_REG0 +#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x00000000 +#define GUI_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x00000000 + +// SCRATCH_REG1 +#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x00000000 +#define GUI_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x00000000 + +// SCRATCH_REG2 +#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x00000000 +#define GUI_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x00000000 + +// SCRATCH_REG3 +#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x00000000 +#define GUI_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x00000000 + +// SCRATCH_REG4 +#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x00000000 +#define GUI_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x00000000 + +// SCRATCH_REG5 +#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x00000000 +#define GUI_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x00000000 + +// SCRATCH_REG6 +#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x00000000 +#define GUI_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x00000000 + +// SCRATCH_REG7 +#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x00000000 +#define GUI_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x00000000 + +// SCRATCH_UMSK +#define SCRATCH_UMSK__SCRATCH_UMSK__SHIFT 0x00000000 +#define SCRATCH_UMSK__SCRATCH_SWAP__SHIFT 0x00000010 + +// SCRATCH_ADDR +#define SCRATCH_ADDR__SCRATCH_ADDR__SHIFT 0x00000005 + +// CP_ME_VS_EVENT_SRC +#define CP_ME_VS_EVENT_SRC__VS_DONE_SWM__SHIFT 0x00000000 +#define CP_ME_VS_EVENT_SRC__VS_DONE_CNTR__SHIFT 0x00000001 + +// CP_ME_VS_EVENT_ADDR +#define CP_ME_VS_EVENT_ADDR__VS_DONE_SWAP__SHIFT 0x00000000 +#define CP_ME_VS_EVENT_ADDR__VS_DONE_ADDR__SHIFT 0x00000002 + +// CP_ME_VS_EVENT_DATA +#define CP_ME_VS_EVENT_DATA__VS_DONE_DATA__SHIFT 0x00000000 + +// CP_ME_VS_EVENT_ADDR_SWM +#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_SWAP_SWM__SHIFT 0x00000000 +#define CP_ME_VS_EVENT_ADDR_SWM__VS_DONE_ADDR_SWM__SHIFT 0x00000002 + +// CP_ME_VS_EVENT_DATA_SWM +#define CP_ME_VS_EVENT_DATA_SWM__VS_DONE_DATA_SWM__SHIFT 0x00000000 + +// CP_ME_PS_EVENT_SRC +#define CP_ME_PS_EVENT_SRC__PS_DONE_SWM__SHIFT 0x00000000 +#define CP_ME_PS_EVENT_SRC__PS_DONE_CNTR__SHIFT 0x00000001 + +// CP_ME_PS_EVENT_ADDR +#define CP_ME_PS_EVENT_ADDR__PS_DONE_SWAP__SHIFT 0x00000000 +#define CP_ME_PS_EVENT_ADDR__PS_DONE_ADDR__SHIFT 0x00000002 + +// CP_ME_PS_EVENT_DATA +#define CP_ME_PS_EVENT_DATA__PS_DONE_DATA__SHIFT 0x00000000 + +// CP_ME_PS_EVENT_ADDR_SWM +#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_SWAP_SWM__SHIFT 0x00000000 +#define CP_ME_PS_EVENT_ADDR_SWM__PS_DONE_ADDR_SWM__SHIFT 0x00000002 + +// CP_ME_PS_EVENT_DATA_SWM +#define CP_ME_PS_EVENT_DATA_SWM__PS_DONE_DATA_SWM__SHIFT 0x00000000 + +// CP_ME_CF_EVENT_SRC +#define CP_ME_CF_EVENT_SRC__CF_DONE_SRC__SHIFT 0x00000000 + +// CP_ME_CF_EVENT_ADDR +#define CP_ME_CF_EVENT_ADDR__CF_DONE_SWAP__SHIFT 0x00000000 +#define CP_ME_CF_EVENT_ADDR__CF_DONE_ADDR__SHIFT 0x00000002 + +// CP_ME_CF_EVENT_DATA +#define CP_ME_CF_EVENT_DATA__CF_DONE_DATA__SHIFT 0x00000000 + +// CP_ME_NRT_ADDR +#define CP_ME_NRT_ADDR__NRT_WRITE_SWAP__SHIFT 0x00000000 +#define CP_ME_NRT_ADDR__NRT_WRITE_ADDR__SHIFT 0x00000002 + +// CP_ME_NRT_DATA +#define CP_ME_NRT_DATA__NRT_WRITE_DATA__SHIFT 0x00000000 + +// CP_ME_VS_FETCH_DONE_SRC +#define CP_ME_VS_FETCH_DONE_SRC__VS_FETCH_DONE_CNTR__SHIFT 0x00000000 + +// CP_ME_VS_FETCH_DONE_ADDR +#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_SWAP__SHIFT 0x00000000 +#define CP_ME_VS_FETCH_DONE_ADDR__VS_FETCH_DONE_ADDR__SHIFT 0x00000002 + +// CP_ME_VS_FETCH_DONE_DATA +#define CP_ME_VS_FETCH_DONE_DATA__VS_FETCH_DONE_DATA__SHIFT 0x00000000 + +// CP_INT_CNTL +#define CP_INT_CNTL__SW_INT_MASK__SHIFT 0x00000013 +#define CP_INT_CNTL__T0_PACKET_IN_IB_MASK__SHIFT 0x00000017 +#define CP_INT_CNTL__OPCODE_ERROR_MASK__SHIFT 0x00000018 +#define CP_INT_CNTL__PROTECTED_MODE_ERROR_MASK__SHIFT 0x00000019 +#define CP_INT_CNTL__RESERVED_BIT_ERROR_MASK__SHIFT 0x0000001a +#define CP_INT_CNTL__IB_ERROR_MASK__SHIFT 0x0000001b +#define CP_INT_CNTL__IB2_INT_MASK__SHIFT 0x0000001d +#define CP_INT_CNTL__IB1_INT_MASK__SHIFT 0x0000001e +#define CP_INT_CNTL__RB_INT_MASK__SHIFT 0x0000001f + +// CP_INT_STATUS +#define CP_INT_STATUS__SW_INT_STAT__SHIFT 0x00000013 +#define CP_INT_STATUS__T0_PACKET_IN_IB_STAT__SHIFT 0x00000017 +#define CP_INT_STATUS__OPCODE_ERROR_STAT__SHIFT 0x00000018 +#define CP_INT_STATUS__PROTECTED_MODE_ERROR_STAT__SHIFT 0x00000019 +#define CP_INT_STATUS__RESERVED_BIT_ERROR_STAT__SHIFT 0x0000001a +#define CP_INT_STATUS__IB_ERROR_STAT__SHIFT 0x0000001b +#define CP_INT_STATUS__IB2_INT_STAT__SHIFT 0x0000001d +#define CP_INT_STATUS__IB1_INT_STAT__SHIFT 0x0000001e +#define CP_INT_STATUS__RB_INT_STAT__SHIFT 0x0000001f + +// CP_INT_ACK +#define CP_INT_ACK__SW_INT_ACK__SHIFT 0x00000013 +#define CP_INT_ACK__T0_PACKET_IN_IB_ACK__SHIFT 0x00000017 +#define CP_INT_ACK__OPCODE_ERROR_ACK__SHIFT 0x00000018 +#define CP_INT_ACK__PROTECTED_MODE_ERROR_ACK__SHIFT 0x00000019 +#define CP_INT_ACK__RESERVED_BIT_ERROR_ACK__SHIFT 0x0000001a +#define CP_INT_ACK__IB_ERROR_ACK__SHIFT 0x0000001b +#define CP_INT_ACK__IB2_INT_ACK__SHIFT 0x0000001d +#define CP_INT_ACK__IB1_INT_ACK__SHIFT 0x0000001e +#define CP_INT_ACK__RB_INT_ACK__SHIFT 0x0000001f + +// CP_PFP_UCODE_ADDR +#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x00000000 + +// CP_PFP_UCODE_DATA +#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x00000000 + +// CP_PERFMON_CNTL +#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x00000000 +#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x00000008 + +// CP_PERFCOUNTER_SELECT +#define CP_PERFCOUNTER_SELECT__PERFCOUNT_SEL__SHIFT 0x00000000 + +// CP_PERFCOUNTER_LO +#define CP_PERFCOUNTER_LO__PERFCOUNT_LO__SHIFT 0x00000000 + +// CP_PERFCOUNTER_HI +#define CP_PERFCOUNTER_HI__PERFCOUNT_HI__SHIFT 0x00000000 + +// CP_BIN_MASK_LO +#define CP_BIN_MASK_LO__BIN_MASK_LO__SHIFT 0x00000000 + +// CP_BIN_MASK_HI +#define CP_BIN_MASK_HI__BIN_MASK_HI__SHIFT 0x00000000 + +// CP_BIN_SELECT_LO +#define CP_BIN_SELECT_LO__BIN_SELECT_LO__SHIFT 0x00000000 + +// CP_BIN_SELECT_HI +#define CP_BIN_SELECT_HI__BIN_SELECT_HI__SHIFT 0x00000000 + +// CP_NV_FLAGS_0 +#define CP_NV_FLAGS_0__DISCARD_0__SHIFT 0x00000000 +#define CP_NV_FLAGS_0__END_RCVD_0__SHIFT 0x00000001 +#define CP_NV_FLAGS_0__DISCARD_1__SHIFT 0x00000002 +#define CP_NV_FLAGS_0__END_RCVD_1__SHIFT 0x00000003 +#define CP_NV_FLAGS_0__DISCARD_2__SHIFT 0x00000004 +#define CP_NV_FLAGS_0__END_RCVD_2__SHIFT 0x00000005 +#define CP_NV_FLAGS_0__DISCARD_3__SHIFT 0x00000006 +#define CP_NV_FLAGS_0__END_RCVD_3__SHIFT 0x00000007 +#define CP_NV_FLAGS_0__DISCARD_4__SHIFT 0x00000008 +#define CP_NV_FLAGS_0__END_RCVD_4__SHIFT 0x00000009 +#define CP_NV_FLAGS_0__DISCARD_5__SHIFT 0x0000000a +#define CP_NV_FLAGS_0__END_RCVD_5__SHIFT 0x0000000b +#define CP_NV_FLAGS_0__DISCARD_6__SHIFT 0x0000000c +#define CP_NV_FLAGS_0__END_RCVD_6__SHIFT 0x0000000d +#define CP_NV_FLAGS_0__DISCARD_7__SHIFT 0x0000000e +#define CP_NV_FLAGS_0__END_RCVD_7__SHIFT 0x0000000f +#define CP_NV_FLAGS_0__DISCARD_8__SHIFT 0x00000010 +#define CP_NV_FLAGS_0__END_RCVD_8__SHIFT 0x00000011 +#define CP_NV_FLAGS_0__DISCARD_9__SHIFT 0x00000012 +#define CP_NV_FLAGS_0__END_RCVD_9__SHIFT 0x00000013 +#define CP_NV_FLAGS_0__DISCARD_10__SHIFT 0x00000014 +#define CP_NV_FLAGS_0__END_RCVD_10__SHIFT 0x00000015 +#define CP_NV_FLAGS_0__DISCARD_11__SHIFT 0x00000016 +#define CP_NV_FLAGS_0__END_RCVD_11__SHIFT 0x00000017 +#define CP_NV_FLAGS_0__DISCARD_12__SHIFT 0x00000018 +#define CP_NV_FLAGS_0__END_RCVD_12__SHIFT 0x00000019 +#define CP_NV_FLAGS_0__DISCARD_13__SHIFT 0x0000001a +#define CP_NV_FLAGS_0__END_RCVD_13__SHIFT 0x0000001b +#define CP_NV_FLAGS_0__DISCARD_14__SHIFT 0x0000001c +#define CP_NV_FLAGS_0__END_RCVD_14__SHIFT 0x0000001d +#define CP_NV_FLAGS_0__DISCARD_15__SHIFT 0x0000001e +#define CP_NV_FLAGS_0__END_RCVD_15__SHIFT 0x0000001f + +// CP_NV_FLAGS_1 +#define CP_NV_FLAGS_1__DISCARD_16__SHIFT 0x00000000 +#define CP_NV_FLAGS_1__END_RCVD_16__SHIFT 0x00000001 +#define CP_NV_FLAGS_1__DISCARD_17__SHIFT 0x00000002 +#define CP_NV_FLAGS_1__END_RCVD_17__SHIFT 0x00000003 +#define CP_NV_FLAGS_1__DISCARD_18__SHIFT 0x00000004 +#define CP_NV_FLAGS_1__END_RCVD_18__SHIFT 0x00000005 +#define CP_NV_FLAGS_1__DISCARD_19__SHIFT 0x00000006 +#define CP_NV_FLAGS_1__END_RCVD_19__SHIFT 0x00000007 +#define CP_NV_FLAGS_1__DISCARD_20__SHIFT 0x00000008 +#define CP_NV_FLAGS_1__END_RCVD_20__SHIFT 0x00000009 +#define CP_NV_FLAGS_1__DISCARD_21__SHIFT 0x0000000a +#define CP_NV_FLAGS_1__END_RCVD_21__SHIFT 0x0000000b +#define CP_NV_FLAGS_1__DISCARD_22__SHIFT 0x0000000c +#define CP_NV_FLAGS_1__END_RCVD_22__SHIFT 0x0000000d +#define CP_NV_FLAGS_1__DISCARD_23__SHIFT 0x0000000e +#define CP_NV_FLAGS_1__END_RCVD_23__SHIFT 0x0000000f +#define CP_NV_FLAGS_1__DISCARD_24__SHIFT 0x00000010 +#define CP_NV_FLAGS_1__END_RCVD_24__SHIFT 0x00000011 +#define CP_NV_FLAGS_1__DISCARD_25__SHIFT 0x00000012 +#define CP_NV_FLAGS_1__END_RCVD_25__SHIFT 0x00000013 +#define CP_NV_FLAGS_1__DISCARD_26__SHIFT 0x00000014 +#define CP_NV_FLAGS_1__END_RCVD_26__SHIFT 0x00000015 +#define CP_NV_FLAGS_1__DISCARD_27__SHIFT 0x00000016 +#define CP_NV_FLAGS_1__END_RCVD_27__SHIFT 0x00000017 +#define CP_NV_FLAGS_1__DISCARD_28__SHIFT 0x00000018 +#define CP_NV_FLAGS_1__END_RCVD_28__SHIFT 0x00000019 +#define CP_NV_FLAGS_1__DISCARD_29__SHIFT 0x0000001a +#define CP_NV_FLAGS_1__END_RCVD_29__SHIFT 0x0000001b +#define CP_NV_FLAGS_1__DISCARD_30__SHIFT 0x0000001c +#define CP_NV_FLAGS_1__END_RCVD_30__SHIFT 0x0000001d +#define CP_NV_FLAGS_1__DISCARD_31__SHIFT 0x0000001e +#define CP_NV_FLAGS_1__END_RCVD_31__SHIFT 0x0000001f + +// CP_NV_FLAGS_2 +#define CP_NV_FLAGS_2__DISCARD_32__SHIFT 0x00000000 +#define CP_NV_FLAGS_2__END_RCVD_32__SHIFT 0x00000001 +#define CP_NV_FLAGS_2__DISCARD_33__SHIFT 0x00000002 +#define CP_NV_FLAGS_2__END_RCVD_33__SHIFT 0x00000003 +#define CP_NV_FLAGS_2__DISCARD_34__SHIFT 0x00000004 +#define CP_NV_FLAGS_2__END_RCVD_34__SHIFT 0x00000005 +#define CP_NV_FLAGS_2__DISCARD_35__SHIFT 0x00000006 +#define CP_NV_FLAGS_2__END_RCVD_35__SHIFT 0x00000007 +#define CP_NV_FLAGS_2__DISCARD_36__SHIFT 0x00000008 +#define CP_NV_FLAGS_2__END_RCVD_36__SHIFT 0x00000009 +#define CP_NV_FLAGS_2__DISCARD_37__SHIFT 0x0000000a +#define CP_NV_FLAGS_2__END_RCVD_37__SHIFT 0x0000000b +#define CP_NV_FLAGS_2__DISCARD_38__SHIFT 0x0000000c +#define CP_NV_FLAGS_2__END_RCVD_38__SHIFT 0x0000000d +#define CP_NV_FLAGS_2__DISCARD_39__SHIFT 0x0000000e +#define CP_NV_FLAGS_2__END_RCVD_39__SHIFT 0x0000000f +#define CP_NV_FLAGS_2__DISCARD_40__SHIFT 0x00000010 +#define CP_NV_FLAGS_2__END_RCVD_40__SHIFT 0x00000011 +#define CP_NV_FLAGS_2__DISCARD_41__SHIFT 0x00000012 +#define CP_NV_FLAGS_2__END_RCVD_41__SHIFT 0x00000013 +#define CP_NV_FLAGS_2__DISCARD_42__SHIFT 0x00000014 +#define CP_NV_FLAGS_2__END_RCVD_42__SHIFT 0x00000015 +#define CP_NV_FLAGS_2__DISCARD_43__SHIFT 0x00000016 +#define CP_NV_FLAGS_2__END_RCVD_43__SHIFT 0x00000017 +#define CP_NV_FLAGS_2__DISCARD_44__SHIFT 0x00000018 +#define CP_NV_FLAGS_2__END_RCVD_44__SHIFT 0x00000019 +#define CP_NV_FLAGS_2__DISCARD_45__SHIFT 0x0000001a +#define CP_NV_FLAGS_2__END_RCVD_45__SHIFT 0x0000001b +#define CP_NV_FLAGS_2__DISCARD_46__SHIFT 0x0000001c +#define CP_NV_FLAGS_2__END_RCVD_46__SHIFT 0x0000001d +#define CP_NV_FLAGS_2__DISCARD_47__SHIFT 0x0000001e +#define CP_NV_FLAGS_2__END_RCVD_47__SHIFT 0x0000001f + +// CP_NV_FLAGS_3 +#define CP_NV_FLAGS_3__DISCARD_48__SHIFT 0x00000000 +#define CP_NV_FLAGS_3__END_RCVD_48__SHIFT 0x00000001 +#define CP_NV_FLAGS_3__DISCARD_49__SHIFT 0x00000002 +#define CP_NV_FLAGS_3__END_RCVD_49__SHIFT 0x00000003 +#define CP_NV_FLAGS_3__DISCARD_50__SHIFT 0x00000004 +#define CP_NV_FLAGS_3__END_RCVD_50__SHIFT 0x00000005 +#define CP_NV_FLAGS_3__DISCARD_51__SHIFT 0x00000006 +#define CP_NV_FLAGS_3__END_RCVD_51__SHIFT 0x00000007 +#define CP_NV_FLAGS_3__DISCARD_52__SHIFT 0x00000008 +#define CP_NV_FLAGS_3__END_RCVD_52__SHIFT 0x00000009 +#define CP_NV_FLAGS_3__DISCARD_53__SHIFT 0x0000000a +#define CP_NV_FLAGS_3__END_RCVD_53__SHIFT 0x0000000b +#define CP_NV_FLAGS_3__DISCARD_54__SHIFT 0x0000000c +#define CP_NV_FLAGS_3__END_RCVD_54__SHIFT 0x0000000d +#define CP_NV_FLAGS_3__DISCARD_55__SHIFT 0x0000000e +#define CP_NV_FLAGS_3__END_RCVD_55__SHIFT 0x0000000f +#define CP_NV_FLAGS_3__DISCARD_56__SHIFT 0x00000010 +#define CP_NV_FLAGS_3__END_RCVD_56__SHIFT 0x00000011 +#define CP_NV_FLAGS_3__DISCARD_57__SHIFT 0x00000012 +#define CP_NV_FLAGS_3__END_RCVD_57__SHIFT 0x00000013 +#define CP_NV_FLAGS_3__DISCARD_58__SHIFT 0x00000014 +#define CP_NV_FLAGS_3__END_RCVD_58__SHIFT 0x00000015 +#define CP_NV_FLAGS_3__DISCARD_59__SHIFT 0x00000016 +#define CP_NV_FLAGS_3__END_RCVD_59__SHIFT 0x00000017 +#define CP_NV_FLAGS_3__DISCARD_60__SHIFT 0x00000018 +#define CP_NV_FLAGS_3__END_RCVD_60__SHIFT 0x00000019 +#define CP_NV_FLAGS_3__DISCARD_61__SHIFT 0x0000001a +#define CP_NV_FLAGS_3__END_RCVD_61__SHIFT 0x0000001b +#define CP_NV_FLAGS_3__DISCARD_62__SHIFT 0x0000001c +#define CP_NV_FLAGS_3__END_RCVD_62__SHIFT 0x0000001d +#define CP_NV_FLAGS_3__DISCARD_63__SHIFT 0x0000001e +#define CP_NV_FLAGS_3__END_RCVD_63__SHIFT 0x0000001f + +// CP_STATE_DEBUG_INDEX +#define CP_STATE_DEBUG_INDEX__STATE_DEBUG_INDEX__SHIFT 0x00000000 + +// CP_STATE_DEBUG_DATA +#define CP_STATE_DEBUG_DATA__STATE_DEBUG_DATA__SHIFT 0x00000000 + +// CP_PROG_COUNTER +#define CP_PROG_COUNTER__COUNTER__SHIFT 0x00000000 + +// CP_STAT +#define CP_STAT__MIU_WR_BUSY__SHIFT 0x00000000 +#define CP_STAT__MIU_RD_REQ_BUSY__SHIFT 0x00000001 +#define CP_STAT__MIU_RD_RETURN_BUSY__SHIFT 0x00000002 +#define CP_STAT__RBIU_BUSY__SHIFT 0x00000003 +#define CP_STAT__RCIU_BUSY__SHIFT 0x00000004 +#define CP_STAT__CSF_RING_BUSY__SHIFT 0x00000005 +#define CP_STAT__CSF_INDIRECTS_BUSY__SHIFT 0x00000006 +#define CP_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x00000007 +#define CP_STAT__CSF_ST_BUSY__SHIFT 0x00000009 +#define CP_STAT__CSF_BUSY__SHIFT 0x0000000a +#define CP_STAT__RING_QUEUE_BUSY__SHIFT 0x0000000b +#define CP_STAT__INDIRECTS_QUEUE_BUSY__SHIFT 0x0000000c +#define CP_STAT__INDIRECT2_QUEUE_BUSY__SHIFT 0x0000000d +#define CP_STAT__ST_QUEUE_BUSY__SHIFT 0x00000010 +#define CP_STAT__PFP_BUSY__SHIFT 0x00000011 +#define CP_STAT__MEQ_RING_BUSY__SHIFT 0x00000012 +#define CP_STAT__MEQ_INDIRECTS_BUSY__SHIFT 0x00000013 +#define CP_STAT__MEQ_INDIRECT2_BUSY__SHIFT 0x00000014 +#define CP_STAT__MIU_WC_STALL__SHIFT 0x00000015 +#define CP_STAT__CP_NRT_BUSY__SHIFT 0x00000016 +#define CP_STAT___3D_BUSY__SHIFT 0x00000017 +#define CP_STAT__ME_BUSY__SHIFT 0x0000001a +#define CP_STAT__ME_WC_BUSY__SHIFT 0x0000001d +#define CP_STAT__MIU_WC_TRACK_FIFO_EMPTY__SHIFT 0x0000001e +#define CP_STAT__CP_BUSY__SHIFT 0x0000001f + +// BIOS_0_SCRATCH +#define BIOS_0_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_1_SCRATCH +#define BIOS_1_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_2_SCRATCH +#define BIOS_2_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_3_SCRATCH +#define BIOS_3_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_4_SCRATCH +#define BIOS_4_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_5_SCRATCH +#define BIOS_5_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_6_SCRATCH +#define BIOS_6_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_7_SCRATCH +#define BIOS_7_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_8_SCRATCH +#define BIOS_8_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_9_SCRATCH +#define BIOS_9_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_10_SCRATCH +#define BIOS_10_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_11_SCRATCH +#define BIOS_11_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_12_SCRATCH +#define BIOS_12_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_13_SCRATCH +#define BIOS_13_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_14_SCRATCH +#define BIOS_14_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// BIOS_15_SCRATCH +#define BIOS_15_SCRATCH__BIOS_SCRATCH__SHIFT 0x00000000 + +// COHER_SIZE_PM4 +#define COHER_SIZE_PM4__SIZE__SHIFT 0x00000000 + +// COHER_BASE_PM4 +#define COHER_BASE_PM4__BASE__SHIFT 0x00000000 + +// COHER_STATUS_PM4 +#define COHER_STATUS_PM4__MATCHING_CONTEXTS__SHIFT 0x00000000 +#define COHER_STATUS_PM4__RB_COPY_DEST_BASE_ENA__SHIFT 0x00000008 +#define COHER_STATUS_PM4__DEST_BASE_0_ENA__SHIFT 0x00000009 +#define COHER_STATUS_PM4__DEST_BASE_1_ENA__SHIFT 0x0000000a +#define COHER_STATUS_PM4__DEST_BASE_2_ENA__SHIFT 0x0000000b +#define COHER_STATUS_PM4__DEST_BASE_3_ENA__SHIFT 0x0000000c +#define COHER_STATUS_PM4__DEST_BASE_4_ENA__SHIFT 0x0000000d +#define COHER_STATUS_PM4__DEST_BASE_5_ENA__SHIFT 0x0000000e +#define COHER_STATUS_PM4__DEST_BASE_6_ENA__SHIFT 0x0000000f +#define COHER_STATUS_PM4__DEST_BASE_7_ENA__SHIFT 0x00000010 +#define COHER_STATUS_PM4__RB_COLOR_INFO_ENA__SHIFT 0x00000011 +#define COHER_STATUS_PM4__TC_ACTION_ENA__SHIFT 0x00000019 +#define COHER_STATUS_PM4__STATUS__SHIFT 0x0000001f + +// COHER_SIZE_HOST +#define COHER_SIZE_HOST__SIZE__SHIFT 0x00000000 + +// COHER_BASE_HOST +#define COHER_BASE_HOST__BASE__SHIFT 0x00000000 + +// COHER_STATUS_HOST +#define COHER_STATUS_HOST__MATCHING_CONTEXTS__SHIFT 0x00000000 +#define COHER_STATUS_HOST__RB_COPY_DEST_BASE_ENA__SHIFT 0x00000008 +#define COHER_STATUS_HOST__DEST_BASE_0_ENA__SHIFT 0x00000009 +#define COHER_STATUS_HOST__DEST_BASE_1_ENA__SHIFT 0x0000000a +#define COHER_STATUS_HOST__DEST_BASE_2_ENA__SHIFT 0x0000000b +#define COHER_STATUS_HOST__DEST_BASE_3_ENA__SHIFT 0x0000000c +#define COHER_STATUS_HOST__DEST_BASE_4_ENA__SHIFT 0x0000000d +#define COHER_STATUS_HOST__DEST_BASE_5_ENA__SHIFT 0x0000000e +#define COHER_STATUS_HOST__DEST_BASE_6_ENA__SHIFT 0x0000000f +#define COHER_STATUS_HOST__DEST_BASE_7_ENA__SHIFT 0x00000010 +#define COHER_STATUS_HOST__RB_COLOR_INFO_ENA__SHIFT 0x00000011 +#define COHER_STATUS_HOST__TC_ACTION_ENA__SHIFT 0x00000019 +#define COHER_STATUS_HOST__STATUS__SHIFT 0x0000001f + +// COHER_DEST_BASE_0 +#define COHER_DEST_BASE_0__DEST_BASE_0__SHIFT 0x0000000c + +// COHER_DEST_BASE_1 +#define COHER_DEST_BASE_1__DEST_BASE_1__SHIFT 0x0000000c + +// COHER_DEST_BASE_2 +#define COHER_DEST_BASE_2__DEST_BASE_2__SHIFT 0x0000000c + +// COHER_DEST_BASE_3 +#define COHER_DEST_BASE_3__DEST_BASE_3__SHIFT 0x0000000c + +// COHER_DEST_BASE_4 +#define COHER_DEST_BASE_4__DEST_BASE_4__SHIFT 0x0000000c + +// COHER_DEST_BASE_5 +#define COHER_DEST_BASE_5__DEST_BASE_5__SHIFT 0x0000000c + +// COHER_DEST_BASE_6 +#define COHER_DEST_BASE_6__DEST_BASE_6__SHIFT 0x0000000c + +// COHER_DEST_BASE_7 +#define COHER_DEST_BASE_7__DEST_BASE_7__SHIFT 0x0000000c + +// RB_SURFACE_INFO +#define RB_SURFACE_INFO__SURFACE_PITCH__SHIFT 0x00000000 +#define RB_SURFACE_INFO__MSAA_SAMPLES__SHIFT 0x0000000e + +// RB_COLOR_INFO +#define RB_COLOR_INFO__COLOR_FORMAT__SHIFT 0x00000000 +#define RB_COLOR_INFO__COLOR_ROUND_MODE__SHIFT 0x00000004 +#define RB_COLOR_INFO__COLOR_LINEAR__SHIFT 0x00000006 +#define RB_COLOR_INFO__COLOR_ENDIAN__SHIFT 0x00000007 +#define RB_COLOR_INFO__COLOR_SWAP__SHIFT 0x00000009 +#define RB_COLOR_INFO__COLOR_BASE__SHIFT 0x0000000c + +// RB_DEPTH_INFO +#define RB_DEPTH_INFO__DEPTH_FORMAT__SHIFT 0x00000000 +#define RB_DEPTH_INFO__DEPTH_BASE__SHIFT 0x0000000c + +// RB_STENCILREFMASK +#define RB_STENCILREFMASK__STENCILREF__SHIFT 0x00000000 +#define RB_STENCILREFMASK__STENCILMASK__SHIFT 0x00000008 +#define RB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x00000010 +#define RB_STENCILREFMASK__RESERVED0__SHIFT 0x00000018 +#define RB_STENCILREFMASK__RESERVED1__SHIFT 0x00000019 + +// RB_ALPHA_REF +#define RB_ALPHA_REF__ALPHA_REF__SHIFT 0x00000000 + +// RB_COLOR_MASK +#define RB_COLOR_MASK__WRITE_RED__SHIFT 0x00000000 +#define RB_COLOR_MASK__WRITE_GREEN__SHIFT 0x00000001 +#define RB_COLOR_MASK__WRITE_BLUE__SHIFT 0x00000002 +#define RB_COLOR_MASK__WRITE_ALPHA__SHIFT 0x00000003 +#define RB_COLOR_MASK__RESERVED2__SHIFT 0x00000004 +#define RB_COLOR_MASK__RESERVED3__SHIFT 0x00000005 + +// RB_BLEND_RED +#define RB_BLEND_RED__BLEND_RED__SHIFT 0x00000000 + +// RB_BLEND_GREEN +#define RB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x00000000 + +// RB_BLEND_BLUE +#define RB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x00000000 + +// RB_BLEND_ALPHA +#define RB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x00000000 + +// RB_FOG_COLOR +#define RB_FOG_COLOR__FOG_RED__SHIFT 0x00000000 +#define RB_FOG_COLOR__FOG_GREEN__SHIFT 0x00000008 +#define RB_FOG_COLOR__FOG_BLUE__SHIFT 0x00000010 + +// RB_STENCILREFMASK_BF +#define RB_STENCILREFMASK_BF__STENCILREF_BF__SHIFT 0x00000000 +#define RB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x00000008 +#define RB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x00000010 +#define RB_STENCILREFMASK_BF__RESERVED4__SHIFT 0x00000018 +#define RB_STENCILREFMASK_BF__RESERVED5__SHIFT 0x00000019 + +// RB_DEPTHCONTROL +#define RB_DEPTHCONTROL__STENCIL_ENABLE__SHIFT 0x00000000 +#define RB_DEPTHCONTROL__Z_ENABLE__SHIFT 0x00000001 +#define RB_DEPTHCONTROL__Z_WRITE_ENABLE__SHIFT 0x00000002 +#define RB_DEPTHCONTROL__EARLY_Z_ENABLE__SHIFT 0x00000003 +#define RB_DEPTHCONTROL__ZFUNC__SHIFT 0x00000004 +#define RB_DEPTHCONTROL__BACKFACE_ENABLE__SHIFT 0x00000007 +#define RB_DEPTHCONTROL__STENCILFUNC__SHIFT 0x00000008 +#define RB_DEPTHCONTROL__STENCILFAIL__SHIFT 0x0000000b +#define RB_DEPTHCONTROL__STENCILZPASS__SHIFT 0x0000000e +#define RB_DEPTHCONTROL__STENCILZFAIL__SHIFT 0x00000011 +#define RB_DEPTHCONTROL__STENCILFUNC_BF__SHIFT 0x00000014 +#define RB_DEPTHCONTROL__STENCILFAIL_BF__SHIFT 0x00000017 +#define RB_DEPTHCONTROL__STENCILZPASS_BF__SHIFT 0x0000001a +#define RB_DEPTHCONTROL__STENCILZFAIL_BF__SHIFT 0x0000001d + +// RB_BLENDCONTROL +#define RB_BLENDCONTROL__COLOR_SRCBLEND__SHIFT 0x00000000 +#define RB_BLENDCONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 +#define RB_BLENDCONTROL__COLOR_DESTBLEND__SHIFT 0x00000008 +#define RB_BLENDCONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 +#define RB_BLENDCONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 +#define RB_BLENDCONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 +#define RB_BLENDCONTROL__BLEND_FORCE_ENABLE__SHIFT 0x0000001d +#define RB_BLENDCONTROL__BLEND_FORCE__SHIFT 0x0000001e + +// RB_COLORCONTROL +#define RB_COLORCONTROL__ALPHA_FUNC__SHIFT 0x00000000 +#define RB_COLORCONTROL__ALPHA_TEST_ENABLE__SHIFT 0x00000003 +#define RB_COLORCONTROL__ALPHA_TO_MASK_ENABLE__SHIFT 0x00000004 +#define RB_COLORCONTROL__BLEND_DISABLE__SHIFT 0x00000005 +#define RB_COLORCONTROL__FOG_ENABLE__SHIFT 0x00000006 +#define RB_COLORCONTROL__VS_EXPORTS_FOG__SHIFT 0x00000007 +#define RB_COLORCONTROL__ROP_CODE__SHIFT 0x00000008 +#define RB_COLORCONTROL__DITHER_MODE__SHIFT 0x0000000c +#define RB_COLORCONTROL__DITHER_TYPE__SHIFT 0x0000000e +#define RB_COLORCONTROL__PIXEL_FOG__SHIFT 0x00000010 +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET0__SHIFT 0x00000018 +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET1__SHIFT 0x0000001a +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET2__SHIFT 0x0000001c +#define RB_COLORCONTROL__ALPHA_TO_MASK_OFFSET3__SHIFT 0x0000001e + +// RB_MODECONTROL +#define RB_MODECONTROL__EDRAM_MODE__SHIFT 0x00000000 + +// RB_COLOR_DEST_MASK +#define RB_COLOR_DEST_MASK__COLOR_DEST_MASK__SHIFT 0x00000000 + +// RB_COPY_CONTROL +#define RB_COPY_CONTROL__COPY_SAMPLE_SELECT__SHIFT 0x00000000 +#define RB_COPY_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x00000003 +#define RB_COPY_CONTROL__CLEAR_MASK__SHIFT 0x00000004 + +// RB_COPY_DEST_BASE +#define RB_COPY_DEST_BASE__COPY_DEST_BASE__SHIFT 0x0000000c + +// RB_COPY_DEST_PITCH +#define RB_COPY_DEST_PITCH__COPY_DEST_PITCH__SHIFT 0x00000000 + +// RB_COPY_DEST_INFO +#define RB_COPY_DEST_INFO__COPY_DEST_ENDIAN__SHIFT 0x00000000 +#define RB_COPY_DEST_INFO__COPY_DEST_LINEAR__SHIFT 0x00000003 +#define RB_COPY_DEST_INFO__COPY_DEST_FORMAT__SHIFT 0x00000004 +#define RB_COPY_DEST_INFO__COPY_DEST_SWAP__SHIFT 0x00000008 +#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_MODE__SHIFT 0x0000000a +#define RB_COPY_DEST_INFO__COPY_DEST_DITHER_TYPE__SHIFT 0x0000000c +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_RED__SHIFT 0x0000000e +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_GREEN__SHIFT 0x0000000f +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_BLUE__SHIFT 0x00000010 +#define RB_COPY_DEST_INFO__COPY_MASK_WRITE_ALPHA__SHIFT 0x00000011 + +// RB_COPY_DEST_PIXEL_OFFSET +#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_X__SHIFT 0x00000000 +#define RB_COPY_DEST_PIXEL_OFFSET__OFFSET_Y__SHIFT 0x0000000d + +// RB_DEPTH_CLEAR +#define RB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x00000000 + +// RB_SAMPLE_COUNT_CTL +#define RB_SAMPLE_COUNT_CTL__RESET_SAMPLE_COUNT__SHIFT 0x00000000 +#define RB_SAMPLE_COUNT_CTL__COPY_SAMPLE_COUNT__SHIFT 0x00000001 + +// RB_SAMPLE_COUNT_ADDR +#define RB_SAMPLE_COUNT_ADDR__SAMPLE_COUNT_ADDR__SHIFT 0x00000000 + +// RB_BC_CONTROL +#define RB_BC_CONTROL__ACCUM_LINEAR_MODE_ENABLE__SHIFT 0x00000000 +#define RB_BC_CONTROL__ACCUM_TIMEOUT_SELECT__SHIFT 0x00000001 +#define RB_BC_CONTROL__DISABLE_EDRAM_CAM__SHIFT 0x00000003 +#define RB_BC_CONTROL__DISABLE_EZ_FAST_CONTEXT_SWITCH__SHIFT 0x00000004 +#define RB_BC_CONTROL__DISABLE_EZ_NULL_ZCMD_DROP__SHIFT 0x00000005 +#define RB_BC_CONTROL__DISABLE_LZ_NULL_ZCMD_DROP__SHIFT 0x00000006 +#define RB_BC_CONTROL__ENABLE_AZ_THROTTLE__SHIFT 0x00000007 +#define RB_BC_CONTROL__AZ_THROTTLE_COUNT__SHIFT 0x00000008 +#define RB_BC_CONTROL__ENABLE_CRC_UPDATE__SHIFT 0x0000000e +#define RB_BC_CONTROL__CRC_MODE__SHIFT 0x0000000f +#define RB_BC_CONTROL__DISABLE_SAMPLE_COUNTERS__SHIFT 0x00000010 +#define RB_BC_CONTROL__DISABLE_ACCUM__SHIFT 0x00000011 +#define RB_BC_CONTROL__ACCUM_ALLOC_MASK__SHIFT 0x00000012 +#define RB_BC_CONTROL__LINEAR_PERFORMANCE_ENABLE__SHIFT 0x00000016 +#define RB_BC_CONTROL__ACCUM_DATA_FIFO_LIMIT__SHIFT 0x00000017 +#define RB_BC_CONTROL__MEM_EXPORT_TIMEOUT_SELECT__SHIFT 0x0000001b +#define RB_BC_CONTROL__MEM_EXPORT_LINEAR_MODE_ENABLE__SHIFT 0x0000001d +#define RB_BC_CONTROL__CRC_SYSTEM__SHIFT 0x0000001e +#define RB_BC_CONTROL__RESERVED6__SHIFT 0x0000001f + +// RB_EDRAM_INFO +#define RB_EDRAM_INFO__EDRAM_SIZE__SHIFT 0x00000000 +#define RB_EDRAM_INFO__EDRAM_MAPPING_MODE__SHIFT 0x00000004 +#define RB_EDRAM_INFO__EDRAM_RANGE__SHIFT 0x0000000e + +// RB_CRC_RD_PORT +#define RB_CRC_RD_PORT__CRC_DATA__SHIFT 0x00000000 + +// RB_CRC_CONTROL +#define RB_CRC_CONTROL__CRC_RD_ADVANCE__SHIFT 0x00000000 + +// RB_CRC_MASK +#define RB_CRC_MASK__CRC_MASK__SHIFT 0x00000000 + +// RB_PERFCOUNTER0_SELECT +#define RB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 + +// RB_PERFCOUNTER0_LOW +#define RB_PERFCOUNTER0_LOW__PERF_COUNT__SHIFT 0x00000000 + +// RB_PERFCOUNTER0_HI +#define RB_PERFCOUNTER0_HI__PERF_COUNT__SHIFT 0x00000000 + +// RB_TOTAL_SAMPLES +#define RB_TOTAL_SAMPLES__TOTAL_SAMPLES__SHIFT 0x00000000 + +// RB_ZPASS_SAMPLES +#define RB_ZPASS_SAMPLES__ZPASS_SAMPLES__SHIFT 0x00000000 + +// RB_ZFAIL_SAMPLES +#define RB_ZFAIL_SAMPLES__ZFAIL_SAMPLES__SHIFT 0x00000000 + +// RB_SFAIL_SAMPLES +#define RB_SFAIL_SAMPLES__SFAIL_SAMPLES__SHIFT 0x00000000 + +// RB_DEBUG_0 +#define RB_DEBUG_0__RDREQ_CTL_Z1_PRE_FULL__SHIFT 0x00000000 +#define RB_DEBUG_0__RDREQ_CTL_Z0_PRE_FULL__SHIFT 0x00000001 +#define RB_DEBUG_0__RDREQ_CTL_C1_PRE_FULL__SHIFT 0x00000002 +#define RB_DEBUG_0__RDREQ_CTL_C0_PRE_FULL__SHIFT 0x00000003 +#define RB_DEBUG_0__RDREQ_E1_ORDERING_FULL__SHIFT 0x00000004 +#define RB_DEBUG_0__RDREQ_E0_ORDERING_FULL__SHIFT 0x00000005 +#define RB_DEBUG_0__RDREQ_Z1_FULL__SHIFT 0x00000006 +#define RB_DEBUG_0__RDREQ_Z0_FULL__SHIFT 0x00000007 +#define RB_DEBUG_0__RDREQ_C1_FULL__SHIFT 0x00000008 +#define RB_DEBUG_0__RDREQ_C0_FULL__SHIFT 0x00000009 +#define RB_DEBUG_0__WRREQ_E1_MACRO_HI_FULL__SHIFT 0x0000000a +#define RB_DEBUG_0__WRREQ_E1_MACRO_LO_FULL__SHIFT 0x0000000b +#define RB_DEBUG_0__WRREQ_E0_MACRO_HI_FULL__SHIFT 0x0000000c +#define RB_DEBUG_0__WRREQ_E0_MACRO_LO_FULL__SHIFT 0x0000000d +#define RB_DEBUG_0__WRREQ_C_WE_HI_FULL__SHIFT 0x0000000e +#define RB_DEBUG_0__WRREQ_C_WE_LO_FULL__SHIFT 0x0000000f +#define RB_DEBUG_0__WRREQ_Z1_FULL__SHIFT 0x00000010 +#define RB_DEBUG_0__WRREQ_Z0_FULL__SHIFT 0x00000011 +#define RB_DEBUG_0__WRREQ_C1_FULL__SHIFT 0x00000012 +#define RB_DEBUG_0__WRREQ_C0_FULL__SHIFT 0x00000013 +#define RB_DEBUG_0__CMDFIFO_Z1_HOLD_FULL__SHIFT 0x00000014 +#define RB_DEBUG_0__CMDFIFO_Z0_HOLD_FULL__SHIFT 0x00000015 +#define RB_DEBUG_0__CMDFIFO_C1_HOLD_FULL__SHIFT 0x00000016 +#define RB_DEBUG_0__CMDFIFO_C0_HOLD_FULL__SHIFT 0x00000017 +#define RB_DEBUG_0__CMDFIFO_Z_ORDERING_FULL__SHIFT 0x00000018 +#define RB_DEBUG_0__CMDFIFO_C_ORDERING_FULL__SHIFT 0x00000019 +#define RB_DEBUG_0__C_SX_LAT_FULL__SHIFT 0x0000001a +#define RB_DEBUG_0__C_SX_CMD_FULL__SHIFT 0x0000001b +#define RB_DEBUG_0__C_EZ_TILE_FULL__SHIFT 0x0000001c +#define RB_DEBUG_0__C_REQ_FULL__SHIFT 0x0000001d +#define RB_DEBUG_0__C_MASK_FULL__SHIFT 0x0000001e +#define RB_DEBUG_0__EZ_INFSAMP_FULL__SHIFT 0x0000001f + +// RB_DEBUG_1 +#define RB_DEBUG_1__RDREQ_Z1_CMD_EMPTY__SHIFT 0x00000000 +#define RB_DEBUG_1__RDREQ_Z0_CMD_EMPTY__SHIFT 0x00000001 +#define RB_DEBUG_1__RDREQ_C1_CMD_EMPTY__SHIFT 0x00000002 +#define RB_DEBUG_1__RDREQ_C0_CMD_EMPTY__SHIFT 0x00000003 +#define RB_DEBUG_1__RDREQ_E1_ORDERING_EMPTY__SHIFT 0x00000004 +#define RB_DEBUG_1__RDREQ_E0_ORDERING_EMPTY__SHIFT 0x00000005 +#define RB_DEBUG_1__RDREQ_Z1_EMPTY__SHIFT 0x00000006 +#define RB_DEBUG_1__RDREQ_Z0_EMPTY__SHIFT 0x00000007 +#define RB_DEBUG_1__RDREQ_C1_EMPTY__SHIFT 0x00000008 +#define RB_DEBUG_1__RDREQ_C0_EMPTY__SHIFT 0x00000009 +#define RB_DEBUG_1__WRREQ_E1_MACRO_HI_EMPTY__SHIFT 0x0000000a +#define RB_DEBUG_1__WRREQ_E1_MACRO_LO_EMPTY__SHIFT 0x0000000b +#define RB_DEBUG_1__WRREQ_E0_MACRO_HI_EMPTY__SHIFT 0x0000000c +#define RB_DEBUG_1__WRREQ_E0_MACRO_LO_EMPTY__SHIFT 0x0000000d +#define RB_DEBUG_1__WRREQ_C_WE_HI_EMPTY__SHIFT 0x0000000e +#define RB_DEBUG_1__WRREQ_C_WE_LO_EMPTY__SHIFT 0x0000000f +#define RB_DEBUG_1__WRREQ_Z1_EMPTY__SHIFT 0x00000010 +#define RB_DEBUG_1__WRREQ_Z0_EMPTY__SHIFT 0x00000011 +#define RB_DEBUG_1__WRREQ_C1_PRE_EMPTY__SHIFT 0x00000012 +#define RB_DEBUG_1__WRREQ_C0_PRE_EMPTY__SHIFT 0x00000013 +#define RB_DEBUG_1__CMDFIFO_Z1_HOLD_EMPTY__SHIFT 0x00000014 +#define RB_DEBUG_1__CMDFIFO_Z0_HOLD_EMPTY__SHIFT 0x00000015 +#define RB_DEBUG_1__CMDFIFO_C1_HOLD_EMPTY__SHIFT 0x00000016 +#define RB_DEBUG_1__CMDFIFO_C0_HOLD_EMPTY__SHIFT 0x00000017 +#define RB_DEBUG_1__CMDFIFO_Z_ORDERING_EMPTY__SHIFT 0x00000018 +#define RB_DEBUG_1__CMDFIFO_C_ORDERING_EMPTY__SHIFT 0x00000019 +#define RB_DEBUG_1__C_SX_LAT_EMPTY__SHIFT 0x0000001a +#define RB_DEBUG_1__C_SX_CMD_EMPTY__SHIFT 0x0000001b +#define RB_DEBUG_1__C_EZ_TILE_EMPTY__SHIFT 0x0000001c +#define RB_DEBUG_1__C_REQ_EMPTY__SHIFT 0x0000001d +#define RB_DEBUG_1__C_MASK_EMPTY__SHIFT 0x0000001e +#define RB_DEBUG_1__EZ_INFSAMP_EMPTY__SHIFT 0x0000001f + +// RB_DEBUG_2 +#define RB_DEBUG_2__TILE_FIFO_COUNT__SHIFT 0x00000000 +#define RB_DEBUG_2__SX_LAT_FIFO_COUNT__SHIFT 0x00000004 +#define RB_DEBUG_2__MEM_EXPORT_FLAG__SHIFT 0x0000000b +#define RB_DEBUG_2__SYSMEM_BLEND_FLAG__SHIFT 0x0000000c +#define RB_DEBUG_2__CURRENT_TILE_EVENT__SHIFT 0x0000000d +#define RB_DEBUG_2__EZ_INFTILE_FULL__SHIFT 0x0000000e +#define RB_DEBUG_2__EZ_MASK_LOWER_FULL__SHIFT 0x0000000f +#define RB_DEBUG_2__EZ_MASK_UPPER_FULL__SHIFT 0x00000010 +#define RB_DEBUG_2__Z0_MASK_FULL__SHIFT 0x00000011 +#define RB_DEBUG_2__Z1_MASK_FULL__SHIFT 0x00000012 +#define RB_DEBUG_2__Z0_REQ_FULL__SHIFT 0x00000013 +#define RB_DEBUG_2__Z1_REQ_FULL__SHIFT 0x00000014 +#define RB_DEBUG_2__Z_SAMP_FULL__SHIFT 0x00000015 +#define RB_DEBUG_2__Z_TILE_FULL__SHIFT 0x00000016 +#define RB_DEBUG_2__EZ_INFTILE_EMPTY__SHIFT 0x00000017 +#define RB_DEBUG_2__EZ_MASK_LOWER_EMPTY__SHIFT 0x00000018 +#define RB_DEBUG_2__EZ_MASK_UPPER_EMPTY__SHIFT 0x00000019 +#define RB_DEBUG_2__Z0_MASK_EMPTY__SHIFT 0x0000001a +#define RB_DEBUG_2__Z1_MASK_EMPTY__SHIFT 0x0000001b +#define RB_DEBUG_2__Z0_REQ_EMPTY__SHIFT 0x0000001c +#define RB_DEBUG_2__Z1_REQ_EMPTY__SHIFT 0x0000001d +#define RB_DEBUG_2__Z_SAMP_EMPTY__SHIFT 0x0000001e +#define RB_DEBUG_2__Z_TILE_EMPTY__SHIFT 0x0000001f + +// RB_DEBUG_3 +#define RB_DEBUG_3__ACCUM_VALID__SHIFT 0x00000000 +#define RB_DEBUG_3__ACCUM_FLUSHING__SHIFT 0x00000004 +#define RB_DEBUG_3__ACCUM_WRITE_CLEAN_COUNT__SHIFT 0x00000008 +#define RB_DEBUG_3__ACCUM_INPUT_REG_VALID__SHIFT 0x0000000e +#define RB_DEBUG_3__ACCUM_DATA_FIFO_CNT__SHIFT 0x0000000f +#define RB_DEBUG_3__SHD_FULL__SHIFT 0x00000013 +#define RB_DEBUG_3__SHD_EMPTY__SHIFT 0x00000014 +#define RB_DEBUG_3__EZ_RETURN_LOWER_EMPTY__SHIFT 0x00000015 +#define RB_DEBUG_3__EZ_RETURN_UPPER_EMPTY__SHIFT 0x00000016 +#define RB_DEBUG_3__EZ_RETURN_LOWER_FULL__SHIFT 0x00000017 +#define RB_DEBUG_3__EZ_RETURN_UPPER_FULL__SHIFT 0x00000018 +#define RB_DEBUG_3__ZEXP_LOWER_EMPTY__SHIFT 0x00000019 +#define RB_DEBUG_3__ZEXP_UPPER_EMPTY__SHIFT 0x0000001a +#define RB_DEBUG_3__ZEXP_LOWER_FULL__SHIFT 0x0000001b +#define RB_DEBUG_3__ZEXP_UPPER_FULL__SHIFT 0x0000001c + +// RB_DEBUG_4 +#define RB_DEBUG_4__GMEM_RD_ACCESS_FLAG__SHIFT 0x00000000 +#define RB_DEBUG_4__GMEM_WR_ACCESS_FLAG__SHIFT 0x00000001 +#define RB_DEBUG_4__SYSMEM_RD_ACCESS_FLAG__SHIFT 0x00000002 +#define RB_DEBUG_4__SYSMEM_WR_ACCESS_FLAG__SHIFT 0x00000003 +#define RB_DEBUG_4__ACCUM_DATA_FIFO_EMPTY__SHIFT 0x00000004 +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_EMPTY__SHIFT 0x00000005 +#define RB_DEBUG_4__ACCUM_DATA_FIFO_FULL__SHIFT 0x00000006 +#define RB_DEBUG_4__ACCUM_ORDER_FIFO_FULL__SHIFT 0x00000007 +#define RB_DEBUG_4__SYSMEM_WRITE_COUNT_OVERFLOW__SHIFT 0x00000008 +#define RB_DEBUG_4__CONTEXT_COUNT_DEBUG__SHIFT 0x00000009 + +// RB_FLAG_CONTROL +#define RB_FLAG_CONTROL__DEBUG_FLAG_CLEAR__SHIFT 0x00000000 + +// RB_BC_SPARES +#define RB_BC_SPARES__RESERVED__SHIFT 0x00000000 + +// BC_DUMMY_CRAYRB_ENUMS +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_FORMAT__SHIFT 0x00000000 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_SWAP__SHIFT 0x00000006 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_DEPTH_ARRAY__SHIFT 0x00000007 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_ARRAY__SHIFT 0x00000009 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_COLOR_FORMAT__SHIFT 0x0000000b +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_NUMBER__SHIFT 0x00000011 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_FORMAT__SHIFT 0x00000014 +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_TILING__SHIFT 0x0000001a +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_CRAYRB_SURFACE_ARRAY__SHIFT 0x0000001b +#define BC_DUMMY_CRAYRB_ENUMS__DUMMY_RB_COPY_DEST_INFO_NUMBER__SHIFT 0x0000001d + +// BC_DUMMY_CRAYRB_MOREENUMS +#define BC_DUMMY_CRAYRB_MOREENUMS__DUMMY_CRAYRB_COLORARRAYX__SHIFT 0x00000000 + +#endif diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_struct.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_struct.h new file mode 100644 index 000000000000..78d4924ef79d --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_struct.h @@ -0,0 +1,52583 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_CP_FIDDLE_H) +#define _CP_FIDDLE_H + + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * CP_RB_BASE struct + */ + +#define CP_RB_BASE_RB_BASE_SIZE 27 + +#define CP_RB_BASE_RB_BASE_SHIFT 5 + +#define CP_RB_BASE_RB_BASE_MASK 0xffffffe0 + +#define CP_RB_BASE_MASK \ + (CP_RB_BASE_RB_BASE_MASK) + +#define CP_RB_BASE(rb_base) \ + ((rb_base << CP_RB_BASE_RB_BASE_SHIFT)) + +#define CP_RB_BASE_GET_RB_BASE(cp_rb_base) \ + ((cp_rb_base & CP_RB_BASE_RB_BASE_MASK) >> CP_RB_BASE_RB_BASE_SHIFT) + +#define CP_RB_BASE_SET_RB_BASE(cp_rb_base_reg, rb_base) \ + cp_rb_base_reg = (cp_rb_base_reg & ~CP_RB_BASE_RB_BASE_MASK) | (rb_base << CP_RB_BASE_RB_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_base_t { + unsigned int : 5; + unsigned int rb_base : CP_RB_BASE_RB_BASE_SIZE; + } cp_rb_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_base_t { + unsigned int rb_base : CP_RB_BASE_RB_BASE_SIZE; + unsigned int : 5; + } cp_rb_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_base_t f; +} cp_rb_base_u; + + +/* + * CP_RB_CNTL struct + */ + +#define CP_RB_CNTL_RB_BUFSZ_SIZE 6 +#define CP_RB_CNTL_RB_BLKSZ_SIZE 6 +#define CP_RB_CNTL_BUF_SWAP_SIZE 2 +#define CP_RB_CNTL_RB_POLL_EN_SIZE 1 +#define CP_RB_CNTL_RB_NO_UPDATE_SIZE 1 +#define CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE 1 + +#define CP_RB_CNTL_RB_BUFSZ_SHIFT 0 +#define CP_RB_CNTL_RB_BLKSZ_SHIFT 8 +#define CP_RB_CNTL_BUF_SWAP_SHIFT 16 +#define CP_RB_CNTL_RB_POLL_EN_SHIFT 20 +#define CP_RB_CNTL_RB_NO_UPDATE_SHIFT 27 +#define CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT 31 + +#define CP_RB_CNTL_RB_BUFSZ_MASK 0x0000003f +#define CP_RB_CNTL_RB_BLKSZ_MASK 0x00003f00 +#define CP_RB_CNTL_BUF_SWAP_MASK 0x00030000 +#define CP_RB_CNTL_RB_POLL_EN_MASK 0x00100000 +#define CP_RB_CNTL_RB_NO_UPDATE_MASK 0x08000000 +#define CP_RB_CNTL_RB_RPTR_WR_ENA_MASK 0x80000000 + +#define CP_RB_CNTL_MASK \ + (CP_RB_CNTL_RB_BUFSZ_MASK | \ + CP_RB_CNTL_RB_BLKSZ_MASK | \ + CP_RB_CNTL_BUF_SWAP_MASK | \ + CP_RB_CNTL_RB_POLL_EN_MASK | \ + CP_RB_CNTL_RB_NO_UPDATE_MASK | \ + CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) + +#define CP_RB_CNTL(rb_bufsz, rb_blksz, buf_swap, rb_poll_en, rb_no_update, rb_rptr_wr_ena) \ + ((rb_bufsz << CP_RB_CNTL_RB_BUFSZ_SHIFT) | \ + (rb_blksz << CP_RB_CNTL_RB_BLKSZ_SHIFT) | \ + (buf_swap << CP_RB_CNTL_BUF_SWAP_SHIFT) | \ + (rb_poll_en << CP_RB_CNTL_RB_POLL_EN_SHIFT) | \ + (rb_no_update << CP_RB_CNTL_RB_NO_UPDATE_SHIFT) | \ + (rb_rptr_wr_ena << CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT)) + +#define CP_RB_CNTL_GET_RB_BUFSZ(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_BUFSZ_MASK) >> CP_RB_CNTL_RB_BUFSZ_SHIFT) +#define CP_RB_CNTL_GET_RB_BLKSZ(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_BLKSZ_MASK) >> CP_RB_CNTL_RB_BLKSZ_SHIFT) +#define CP_RB_CNTL_GET_BUF_SWAP(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_BUF_SWAP_MASK) >> CP_RB_CNTL_BUF_SWAP_SHIFT) +#define CP_RB_CNTL_GET_RB_POLL_EN(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_POLL_EN_MASK) >> CP_RB_CNTL_RB_POLL_EN_SHIFT) +#define CP_RB_CNTL_GET_RB_NO_UPDATE(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_NO_UPDATE_MASK) >> CP_RB_CNTL_RB_NO_UPDATE_SHIFT) +#define CP_RB_CNTL_GET_RB_RPTR_WR_ENA(cp_rb_cntl) \ + ((cp_rb_cntl & CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) >> CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT) + +#define CP_RB_CNTL_SET_RB_BUFSZ(cp_rb_cntl_reg, rb_bufsz) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_BUFSZ_MASK) | (rb_bufsz << CP_RB_CNTL_RB_BUFSZ_SHIFT) +#define CP_RB_CNTL_SET_RB_BLKSZ(cp_rb_cntl_reg, rb_blksz) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_BLKSZ_MASK) | (rb_blksz << CP_RB_CNTL_RB_BLKSZ_SHIFT) +#define CP_RB_CNTL_SET_BUF_SWAP(cp_rb_cntl_reg, buf_swap) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_BUF_SWAP_MASK) | (buf_swap << CP_RB_CNTL_BUF_SWAP_SHIFT) +#define CP_RB_CNTL_SET_RB_POLL_EN(cp_rb_cntl_reg, rb_poll_en) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_POLL_EN_MASK) | (rb_poll_en << CP_RB_CNTL_RB_POLL_EN_SHIFT) +#define CP_RB_CNTL_SET_RB_NO_UPDATE(cp_rb_cntl_reg, rb_no_update) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_NO_UPDATE_MASK) | (rb_no_update << CP_RB_CNTL_RB_NO_UPDATE_SHIFT) +#define CP_RB_CNTL_SET_RB_RPTR_WR_ENA(cp_rb_cntl_reg, rb_rptr_wr_ena) \ + cp_rb_cntl_reg = (cp_rb_cntl_reg & ~CP_RB_CNTL_RB_RPTR_WR_ENA_MASK) | (rb_rptr_wr_ena << CP_RB_CNTL_RB_RPTR_WR_ENA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_cntl_t { + unsigned int rb_bufsz : CP_RB_CNTL_RB_BUFSZ_SIZE; + unsigned int : 2; + unsigned int rb_blksz : CP_RB_CNTL_RB_BLKSZ_SIZE; + unsigned int : 2; + unsigned int buf_swap : CP_RB_CNTL_BUF_SWAP_SIZE; + unsigned int : 2; + unsigned int rb_poll_en : CP_RB_CNTL_RB_POLL_EN_SIZE; + unsigned int : 6; + unsigned int rb_no_update : CP_RB_CNTL_RB_NO_UPDATE_SIZE; + unsigned int : 3; + unsigned int rb_rptr_wr_ena : CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE; + } cp_rb_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_cntl_t { + unsigned int rb_rptr_wr_ena : CP_RB_CNTL_RB_RPTR_WR_ENA_SIZE; + unsigned int : 3; + unsigned int rb_no_update : CP_RB_CNTL_RB_NO_UPDATE_SIZE; + unsigned int : 6; + unsigned int rb_poll_en : CP_RB_CNTL_RB_POLL_EN_SIZE; + unsigned int : 2; + unsigned int buf_swap : CP_RB_CNTL_BUF_SWAP_SIZE; + unsigned int : 2; + unsigned int rb_blksz : CP_RB_CNTL_RB_BLKSZ_SIZE; + unsigned int : 2; + unsigned int rb_bufsz : CP_RB_CNTL_RB_BUFSZ_SIZE; + } cp_rb_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_cntl_t f; +} cp_rb_cntl_u; + + +/* + * CP_RB_RPTR_ADDR struct + */ + +#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE 2 +#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE 30 + +#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT 0 +#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT 2 + +#define CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK 0x00000003 +#define CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK 0xfffffffc + +#define CP_RB_RPTR_ADDR_MASK \ + (CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK | \ + CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) + +#define CP_RB_RPTR_ADDR(rb_rptr_swap, rb_rptr_addr) \ + ((rb_rptr_swap << CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT) | \ + (rb_rptr_addr << CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT)) + +#define CP_RB_RPTR_ADDR_GET_RB_RPTR_SWAP(cp_rb_rptr_addr) \ + ((cp_rb_rptr_addr & CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK) >> CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT) +#define CP_RB_RPTR_ADDR_GET_RB_RPTR_ADDR(cp_rb_rptr_addr) \ + ((cp_rb_rptr_addr & CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) >> CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT) + +#define CP_RB_RPTR_ADDR_SET_RB_RPTR_SWAP(cp_rb_rptr_addr_reg, rb_rptr_swap) \ + cp_rb_rptr_addr_reg = (cp_rb_rptr_addr_reg & ~CP_RB_RPTR_ADDR_RB_RPTR_SWAP_MASK) | (rb_rptr_swap << CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SHIFT) +#define CP_RB_RPTR_ADDR_SET_RB_RPTR_ADDR(cp_rb_rptr_addr_reg, rb_rptr_addr) \ + cp_rb_rptr_addr_reg = (cp_rb_rptr_addr_reg & ~CP_RB_RPTR_ADDR_RB_RPTR_ADDR_MASK) | (rb_rptr_addr << CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_rptr_addr_t { + unsigned int rb_rptr_swap : CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE; + unsigned int rb_rptr_addr : CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE; + } cp_rb_rptr_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_rptr_addr_t { + unsigned int rb_rptr_addr : CP_RB_RPTR_ADDR_RB_RPTR_ADDR_SIZE; + unsigned int rb_rptr_swap : CP_RB_RPTR_ADDR_RB_RPTR_SWAP_SIZE; + } cp_rb_rptr_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_rptr_addr_t f; +} cp_rb_rptr_addr_u; + + +/* + * CP_RB_RPTR struct + */ + +#define CP_RB_RPTR_RB_RPTR_SIZE 20 + +#define CP_RB_RPTR_RB_RPTR_SHIFT 0 + +#define CP_RB_RPTR_RB_RPTR_MASK 0x000fffff + +#define CP_RB_RPTR_MASK \ + (CP_RB_RPTR_RB_RPTR_MASK) + +#define CP_RB_RPTR(rb_rptr) \ + ((rb_rptr << CP_RB_RPTR_RB_RPTR_SHIFT)) + +#define CP_RB_RPTR_GET_RB_RPTR(cp_rb_rptr) \ + ((cp_rb_rptr & CP_RB_RPTR_RB_RPTR_MASK) >> CP_RB_RPTR_RB_RPTR_SHIFT) + +#define CP_RB_RPTR_SET_RB_RPTR(cp_rb_rptr_reg, rb_rptr) \ + cp_rb_rptr_reg = (cp_rb_rptr_reg & ~CP_RB_RPTR_RB_RPTR_MASK) | (rb_rptr << CP_RB_RPTR_RB_RPTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_rptr_t { + unsigned int rb_rptr : CP_RB_RPTR_RB_RPTR_SIZE; + unsigned int : 12; + } cp_rb_rptr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_rptr_t { + unsigned int : 12; + unsigned int rb_rptr : CP_RB_RPTR_RB_RPTR_SIZE; + } cp_rb_rptr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_rptr_t f; +} cp_rb_rptr_u; + + +/* + * CP_RB_RPTR_WR struct + */ + +#define CP_RB_RPTR_WR_RB_RPTR_WR_SIZE 20 + +#define CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT 0 + +#define CP_RB_RPTR_WR_RB_RPTR_WR_MASK 0x000fffff + +#define CP_RB_RPTR_WR_MASK \ + (CP_RB_RPTR_WR_RB_RPTR_WR_MASK) + +#define CP_RB_RPTR_WR(rb_rptr_wr) \ + ((rb_rptr_wr << CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT)) + +#define CP_RB_RPTR_WR_GET_RB_RPTR_WR(cp_rb_rptr_wr) \ + ((cp_rb_rptr_wr & CP_RB_RPTR_WR_RB_RPTR_WR_MASK) >> CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT) + +#define CP_RB_RPTR_WR_SET_RB_RPTR_WR(cp_rb_rptr_wr_reg, rb_rptr_wr) \ + cp_rb_rptr_wr_reg = (cp_rb_rptr_wr_reg & ~CP_RB_RPTR_WR_RB_RPTR_WR_MASK) | (rb_rptr_wr << CP_RB_RPTR_WR_RB_RPTR_WR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_rptr_wr_t { + unsigned int rb_rptr_wr : CP_RB_RPTR_WR_RB_RPTR_WR_SIZE; + unsigned int : 12; + } cp_rb_rptr_wr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_rptr_wr_t { + unsigned int : 12; + unsigned int rb_rptr_wr : CP_RB_RPTR_WR_RB_RPTR_WR_SIZE; + } cp_rb_rptr_wr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_rptr_wr_t f; +} cp_rb_rptr_wr_u; + + +/* + * CP_RB_WPTR struct + */ + +#define CP_RB_WPTR_RB_WPTR_SIZE 20 + +#define CP_RB_WPTR_RB_WPTR_SHIFT 0 + +#define CP_RB_WPTR_RB_WPTR_MASK 0x000fffff + +#define CP_RB_WPTR_MASK \ + (CP_RB_WPTR_RB_WPTR_MASK) + +#define CP_RB_WPTR(rb_wptr) \ + ((rb_wptr << CP_RB_WPTR_RB_WPTR_SHIFT)) + +#define CP_RB_WPTR_GET_RB_WPTR(cp_rb_wptr) \ + ((cp_rb_wptr & CP_RB_WPTR_RB_WPTR_MASK) >> CP_RB_WPTR_RB_WPTR_SHIFT) + +#define CP_RB_WPTR_SET_RB_WPTR(cp_rb_wptr_reg, rb_wptr) \ + cp_rb_wptr_reg = (cp_rb_wptr_reg & ~CP_RB_WPTR_RB_WPTR_MASK) | (rb_wptr << CP_RB_WPTR_RB_WPTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_wptr_t { + unsigned int rb_wptr : CP_RB_WPTR_RB_WPTR_SIZE; + unsigned int : 12; + } cp_rb_wptr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_wptr_t { + unsigned int : 12; + unsigned int rb_wptr : CP_RB_WPTR_RB_WPTR_SIZE; + } cp_rb_wptr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_wptr_t f; +} cp_rb_wptr_u; + + +/* + * CP_RB_WPTR_DELAY struct + */ + +#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE 28 +#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE 4 + +#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT 0 +#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT 28 + +#define CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK 0x0fffffff +#define CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK 0xf0000000 + +#define CP_RB_WPTR_DELAY_MASK \ + (CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK | \ + CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) + +#define CP_RB_WPTR_DELAY(pre_write_timer, pre_write_limit) \ + ((pre_write_timer << CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT) | \ + (pre_write_limit << CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT)) + +#define CP_RB_WPTR_DELAY_GET_PRE_WRITE_TIMER(cp_rb_wptr_delay) \ + ((cp_rb_wptr_delay & CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK) >> CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT) +#define CP_RB_WPTR_DELAY_GET_PRE_WRITE_LIMIT(cp_rb_wptr_delay) \ + ((cp_rb_wptr_delay & CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) >> CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT) + +#define CP_RB_WPTR_DELAY_SET_PRE_WRITE_TIMER(cp_rb_wptr_delay_reg, pre_write_timer) \ + cp_rb_wptr_delay_reg = (cp_rb_wptr_delay_reg & ~CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_MASK) | (pre_write_timer << CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SHIFT) +#define CP_RB_WPTR_DELAY_SET_PRE_WRITE_LIMIT(cp_rb_wptr_delay_reg, pre_write_limit) \ + cp_rb_wptr_delay_reg = (cp_rb_wptr_delay_reg & ~CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_MASK) | (pre_write_limit << CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_wptr_delay_t { + unsigned int pre_write_timer : CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE; + unsigned int pre_write_limit : CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE; + } cp_rb_wptr_delay_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_wptr_delay_t { + unsigned int pre_write_limit : CP_RB_WPTR_DELAY_PRE_WRITE_LIMIT_SIZE; + unsigned int pre_write_timer : CP_RB_WPTR_DELAY_PRE_WRITE_TIMER_SIZE; + } cp_rb_wptr_delay_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_wptr_delay_t f; +} cp_rb_wptr_delay_u; + + +/* + * CP_RB_WPTR_BASE struct + */ + +#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE 2 +#define CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE 30 + +#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT 0 +#define CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT 2 + +#define CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK 0x00000003 +#define CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK 0xfffffffc + +#define CP_RB_WPTR_BASE_MASK \ + (CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK | \ + CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) + +#define CP_RB_WPTR_BASE(rb_wptr_swap, rb_wptr_base) \ + ((rb_wptr_swap << CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT) | \ + (rb_wptr_base << CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT)) + +#define CP_RB_WPTR_BASE_GET_RB_WPTR_SWAP(cp_rb_wptr_base) \ + ((cp_rb_wptr_base & CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK) >> CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT) +#define CP_RB_WPTR_BASE_GET_RB_WPTR_BASE(cp_rb_wptr_base) \ + ((cp_rb_wptr_base & CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) >> CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT) + +#define CP_RB_WPTR_BASE_SET_RB_WPTR_SWAP(cp_rb_wptr_base_reg, rb_wptr_swap) \ + cp_rb_wptr_base_reg = (cp_rb_wptr_base_reg & ~CP_RB_WPTR_BASE_RB_WPTR_SWAP_MASK) | (rb_wptr_swap << CP_RB_WPTR_BASE_RB_WPTR_SWAP_SHIFT) +#define CP_RB_WPTR_BASE_SET_RB_WPTR_BASE(cp_rb_wptr_base_reg, rb_wptr_base) \ + cp_rb_wptr_base_reg = (cp_rb_wptr_base_reg & ~CP_RB_WPTR_BASE_RB_WPTR_BASE_MASK) | (rb_wptr_base << CP_RB_WPTR_BASE_RB_WPTR_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_rb_wptr_base_t { + unsigned int rb_wptr_swap : CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE; + unsigned int rb_wptr_base : CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE; + } cp_rb_wptr_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_rb_wptr_base_t { + unsigned int rb_wptr_base : CP_RB_WPTR_BASE_RB_WPTR_BASE_SIZE; + unsigned int rb_wptr_swap : CP_RB_WPTR_BASE_RB_WPTR_SWAP_SIZE; + } cp_rb_wptr_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_rb_wptr_base_t f; +} cp_rb_wptr_base_u; + + +/* + * CP_IB1_BASE struct + */ + +#define CP_IB1_BASE_IB1_BASE_SIZE 30 + +#define CP_IB1_BASE_IB1_BASE_SHIFT 2 + +#define CP_IB1_BASE_IB1_BASE_MASK 0xfffffffc + +#define CP_IB1_BASE_MASK \ + (CP_IB1_BASE_IB1_BASE_MASK) + +#define CP_IB1_BASE(ib1_base) \ + ((ib1_base << CP_IB1_BASE_IB1_BASE_SHIFT)) + +#define CP_IB1_BASE_GET_IB1_BASE(cp_ib1_base) \ + ((cp_ib1_base & CP_IB1_BASE_IB1_BASE_MASK) >> CP_IB1_BASE_IB1_BASE_SHIFT) + +#define CP_IB1_BASE_SET_IB1_BASE(cp_ib1_base_reg, ib1_base) \ + cp_ib1_base_reg = (cp_ib1_base_reg & ~CP_IB1_BASE_IB1_BASE_MASK) | (ib1_base << CP_IB1_BASE_IB1_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_ib1_base_t { + unsigned int : 2; + unsigned int ib1_base : CP_IB1_BASE_IB1_BASE_SIZE; + } cp_ib1_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_ib1_base_t { + unsigned int ib1_base : CP_IB1_BASE_IB1_BASE_SIZE; + unsigned int : 2; + } cp_ib1_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_ib1_base_t f; +} cp_ib1_base_u; + + +/* + * CP_IB1_BUFSZ struct + */ + +#define CP_IB1_BUFSZ_IB1_BUFSZ_SIZE 20 + +#define CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT 0 + +#define CP_IB1_BUFSZ_IB1_BUFSZ_MASK 0x000fffff + +#define CP_IB1_BUFSZ_MASK \ + (CP_IB1_BUFSZ_IB1_BUFSZ_MASK) + +#define CP_IB1_BUFSZ(ib1_bufsz) \ + ((ib1_bufsz << CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT)) + +#define CP_IB1_BUFSZ_GET_IB1_BUFSZ(cp_ib1_bufsz) \ + ((cp_ib1_bufsz & CP_IB1_BUFSZ_IB1_BUFSZ_MASK) >> CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT) + +#define CP_IB1_BUFSZ_SET_IB1_BUFSZ(cp_ib1_bufsz_reg, ib1_bufsz) \ + cp_ib1_bufsz_reg = (cp_ib1_bufsz_reg & ~CP_IB1_BUFSZ_IB1_BUFSZ_MASK) | (ib1_bufsz << CP_IB1_BUFSZ_IB1_BUFSZ_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_ib1_bufsz_t { + unsigned int ib1_bufsz : CP_IB1_BUFSZ_IB1_BUFSZ_SIZE; + unsigned int : 12; + } cp_ib1_bufsz_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_ib1_bufsz_t { + unsigned int : 12; + unsigned int ib1_bufsz : CP_IB1_BUFSZ_IB1_BUFSZ_SIZE; + } cp_ib1_bufsz_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_ib1_bufsz_t f; +} cp_ib1_bufsz_u; + + +/* + * CP_IB2_BASE struct + */ + +#define CP_IB2_BASE_IB2_BASE_SIZE 30 + +#define CP_IB2_BASE_IB2_BASE_SHIFT 2 + +#define CP_IB2_BASE_IB2_BASE_MASK 0xfffffffc + +#define CP_IB2_BASE_MASK \ + (CP_IB2_BASE_IB2_BASE_MASK) + +#define CP_IB2_BASE(ib2_base) \ + ((ib2_base << CP_IB2_BASE_IB2_BASE_SHIFT)) + +#define CP_IB2_BASE_GET_IB2_BASE(cp_ib2_base) \ + ((cp_ib2_base & CP_IB2_BASE_IB2_BASE_MASK) >> CP_IB2_BASE_IB2_BASE_SHIFT) + +#define CP_IB2_BASE_SET_IB2_BASE(cp_ib2_base_reg, ib2_base) \ + cp_ib2_base_reg = (cp_ib2_base_reg & ~CP_IB2_BASE_IB2_BASE_MASK) | (ib2_base << CP_IB2_BASE_IB2_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_ib2_base_t { + unsigned int : 2; + unsigned int ib2_base : CP_IB2_BASE_IB2_BASE_SIZE; + } cp_ib2_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_ib2_base_t { + unsigned int ib2_base : CP_IB2_BASE_IB2_BASE_SIZE; + unsigned int : 2; + } cp_ib2_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_ib2_base_t f; +} cp_ib2_base_u; + + +/* + * CP_IB2_BUFSZ struct + */ + +#define CP_IB2_BUFSZ_IB2_BUFSZ_SIZE 20 + +#define CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT 0 + +#define CP_IB2_BUFSZ_IB2_BUFSZ_MASK 0x000fffff + +#define CP_IB2_BUFSZ_MASK \ + (CP_IB2_BUFSZ_IB2_BUFSZ_MASK) + +#define CP_IB2_BUFSZ(ib2_bufsz) \ + ((ib2_bufsz << CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT)) + +#define CP_IB2_BUFSZ_GET_IB2_BUFSZ(cp_ib2_bufsz) \ + ((cp_ib2_bufsz & CP_IB2_BUFSZ_IB2_BUFSZ_MASK) >> CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT) + +#define CP_IB2_BUFSZ_SET_IB2_BUFSZ(cp_ib2_bufsz_reg, ib2_bufsz) \ + cp_ib2_bufsz_reg = (cp_ib2_bufsz_reg & ~CP_IB2_BUFSZ_IB2_BUFSZ_MASK) | (ib2_bufsz << CP_IB2_BUFSZ_IB2_BUFSZ_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_ib2_bufsz_t { + unsigned int ib2_bufsz : CP_IB2_BUFSZ_IB2_BUFSZ_SIZE; + unsigned int : 12; + } cp_ib2_bufsz_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_ib2_bufsz_t { + unsigned int : 12; + unsigned int ib2_bufsz : CP_IB2_BUFSZ_IB2_BUFSZ_SIZE; + } cp_ib2_bufsz_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_ib2_bufsz_t f; +} cp_ib2_bufsz_u; + + +/* + * CP_ST_BASE struct + */ + +#define CP_ST_BASE_ST_BASE_SIZE 30 + +#define CP_ST_BASE_ST_BASE_SHIFT 2 + +#define CP_ST_BASE_ST_BASE_MASK 0xfffffffc + +#define CP_ST_BASE_MASK \ + (CP_ST_BASE_ST_BASE_MASK) + +#define CP_ST_BASE(st_base) \ + ((st_base << CP_ST_BASE_ST_BASE_SHIFT)) + +#define CP_ST_BASE_GET_ST_BASE(cp_st_base) \ + ((cp_st_base & CP_ST_BASE_ST_BASE_MASK) >> CP_ST_BASE_ST_BASE_SHIFT) + +#define CP_ST_BASE_SET_ST_BASE(cp_st_base_reg, st_base) \ + cp_st_base_reg = (cp_st_base_reg & ~CP_ST_BASE_ST_BASE_MASK) | (st_base << CP_ST_BASE_ST_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_st_base_t { + unsigned int : 2; + unsigned int st_base : CP_ST_BASE_ST_BASE_SIZE; + } cp_st_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_st_base_t { + unsigned int st_base : CP_ST_BASE_ST_BASE_SIZE; + unsigned int : 2; + } cp_st_base_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_st_base_t f; +} cp_st_base_u; + + +/* + * CP_ST_BUFSZ struct + */ + +#define CP_ST_BUFSZ_ST_BUFSZ_SIZE 20 + +#define CP_ST_BUFSZ_ST_BUFSZ_SHIFT 0 + +#define CP_ST_BUFSZ_ST_BUFSZ_MASK 0x000fffff + +#define CP_ST_BUFSZ_MASK \ + (CP_ST_BUFSZ_ST_BUFSZ_MASK) + +#define CP_ST_BUFSZ(st_bufsz) \ + ((st_bufsz << CP_ST_BUFSZ_ST_BUFSZ_SHIFT)) + +#define CP_ST_BUFSZ_GET_ST_BUFSZ(cp_st_bufsz) \ + ((cp_st_bufsz & CP_ST_BUFSZ_ST_BUFSZ_MASK) >> CP_ST_BUFSZ_ST_BUFSZ_SHIFT) + +#define CP_ST_BUFSZ_SET_ST_BUFSZ(cp_st_bufsz_reg, st_bufsz) \ + cp_st_bufsz_reg = (cp_st_bufsz_reg & ~CP_ST_BUFSZ_ST_BUFSZ_MASK) | (st_bufsz << CP_ST_BUFSZ_ST_BUFSZ_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_st_bufsz_t { + unsigned int st_bufsz : CP_ST_BUFSZ_ST_BUFSZ_SIZE; + unsigned int : 12; + } cp_st_bufsz_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_st_bufsz_t { + unsigned int : 12; + unsigned int st_bufsz : CP_ST_BUFSZ_ST_BUFSZ_SIZE; + } cp_st_bufsz_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_st_bufsz_t f; +} cp_st_bufsz_u; + + +/* + * CP_QUEUE_THRESHOLDS struct + */ + +#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE 4 +#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE 4 +#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE 4 + +#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT 0 +#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT 8 +#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT 16 + +#define CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK 0x0000000f +#define CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK 0x00000f00 +#define CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK 0x000f0000 + +#define CP_QUEUE_THRESHOLDS_MASK \ + (CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK | \ + CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK | \ + CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) + +#define CP_QUEUE_THRESHOLDS(csq_ib1_start, csq_ib2_start, csq_st_start) \ + ((csq_ib1_start << CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT) | \ + (csq_ib2_start << CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT) | \ + (csq_st_start << CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT)) + +#define CP_QUEUE_THRESHOLDS_GET_CSQ_IB1_START(cp_queue_thresholds) \ + ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT) +#define CP_QUEUE_THRESHOLDS_GET_CSQ_IB2_START(cp_queue_thresholds) \ + ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT) +#define CP_QUEUE_THRESHOLDS_GET_CSQ_ST_START(cp_queue_thresholds) \ + ((cp_queue_thresholds & CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) >> CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT) + +#define CP_QUEUE_THRESHOLDS_SET_CSQ_IB1_START(cp_queue_thresholds_reg, csq_ib1_start) \ + cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_IB1_START_MASK) | (csq_ib1_start << CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SHIFT) +#define CP_QUEUE_THRESHOLDS_SET_CSQ_IB2_START(cp_queue_thresholds_reg, csq_ib2_start) \ + cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_IB2_START_MASK) | (csq_ib2_start << CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SHIFT) +#define CP_QUEUE_THRESHOLDS_SET_CSQ_ST_START(cp_queue_thresholds_reg, csq_st_start) \ + cp_queue_thresholds_reg = (cp_queue_thresholds_reg & ~CP_QUEUE_THRESHOLDS_CSQ_ST_START_MASK) | (csq_st_start << CP_QUEUE_THRESHOLDS_CSQ_ST_START_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_queue_thresholds_t { + unsigned int csq_ib1_start : CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE; + unsigned int : 4; + unsigned int csq_ib2_start : CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE; + unsigned int : 4; + unsigned int csq_st_start : CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE; + unsigned int : 12; + } cp_queue_thresholds_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_queue_thresholds_t { + unsigned int : 12; + unsigned int csq_st_start : CP_QUEUE_THRESHOLDS_CSQ_ST_START_SIZE; + unsigned int : 4; + unsigned int csq_ib2_start : CP_QUEUE_THRESHOLDS_CSQ_IB2_START_SIZE; + unsigned int : 4; + unsigned int csq_ib1_start : CP_QUEUE_THRESHOLDS_CSQ_IB1_START_SIZE; + } cp_queue_thresholds_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_queue_thresholds_t f; +} cp_queue_thresholds_u; + + +/* + * CP_MEQ_THRESHOLDS struct + */ + +#define CP_MEQ_THRESHOLDS_MEQ_END_SIZE 5 +#define CP_MEQ_THRESHOLDS_ROQ_END_SIZE 5 + +#define CP_MEQ_THRESHOLDS_MEQ_END_SHIFT 16 +#define CP_MEQ_THRESHOLDS_ROQ_END_SHIFT 24 + +#define CP_MEQ_THRESHOLDS_MEQ_END_MASK 0x001f0000 +#define CP_MEQ_THRESHOLDS_ROQ_END_MASK 0x1f000000 + +#define CP_MEQ_THRESHOLDS_MASK \ + (CP_MEQ_THRESHOLDS_MEQ_END_MASK | \ + CP_MEQ_THRESHOLDS_ROQ_END_MASK) + +#define CP_MEQ_THRESHOLDS(meq_end, roq_end) \ + ((meq_end << CP_MEQ_THRESHOLDS_MEQ_END_SHIFT) | \ + (roq_end << CP_MEQ_THRESHOLDS_ROQ_END_SHIFT)) + +#define CP_MEQ_THRESHOLDS_GET_MEQ_END(cp_meq_thresholds) \ + ((cp_meq_thresholds & CP_MEQ_THRESHOLDS_MEQ_END_MASK) >> CP_MEQ_THRESHOLDS_MEQ_END_SHIFT) +#define CP_MEQ_THRESHOLDS_GET_ROQ_END(cp_meq_thresholds) \ + ((cp_meq_thresholds & CP_MEQ_THRESHOLDS_ROQ_END_MASK) >> CP_MEQ_THRESHOLDS_ROQ_END_SHIFT) + +#define CP_MEQ_THRESHOLDS_SET_MEQ_END(cp_meq_thresholds_reg, meq_end) \ + cp_meq_thresholds_reg = (cp_meq_thresholds_reg & ~CP_MEQ_THRESHOLDS_MEQ_END_MASK) | (meq_end << CP_MEQ_THRESHOLDS_MEQ_END_SHIFT) +#define CP_MEQ_THRESHOLDS_SET_ROQ_END(cp_meq_thresholds_reg, roq_end) \ + cp_meq_thresholds_reg = (cp_meq_thresholds_reg & ~CP_MEQ_THRESHOLDS_ROQ_END_MASK) | (roq_end << CP_MEQ_THRESHOLDS_ROQ_END_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_meq_thresholds_t { + unsigned int : 16; + unsigned int meq_end : CP_MEQ_THRESHOLDS_MEQ_END_SIZE; + unsigned int : 3; + unsigned int roq_end : CP_MEQ_THRESHOLDS_ROQ_END_SIZE; + unsigned int : 3; + } cp_meq_thresholds_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_meq_thresholds_t { + unsigned int : 3; + unsigned int roq_end : CP_MEQ_THRESHOLDS_ROQ_END_SIZE; + unsigned int : 3; + unsigned int meq_end : CP_MEQ_THRESHOLDS_MEQ_END_SIZE; + unsigned int : 16; + } cp_meq_thresholds_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_meq_thresholds_t f; +} cp_meq_thresholds_u; + + +/* + * CP_CSQ_AVAIL struct + */ + +#define CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE 7 +#define CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE 7 +#define CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE 7 + +#define CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT 0 +#define CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT 8 +#define CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT 16 + +#define CP_CSQ_AVAIL_CSQ_CNT_RING_MASK 0x0000007f +#define CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK 0x00007f00 +#define CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK 0x007f0000 + +#define CP_CSQ_AVAIL_MASK \ + (CP_CSQ_AVAIL_CSQ_CNT_RING_MASK | \ + CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK | \ + CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) + +#define CP_CSQ_AVAIL(csq_cnt_ring, csq_cnt_ib1, csq_cnt_ib2) \ + ((csq_cnt_ring << CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT) | \ + (csq_cnt_ib1 << CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT) | \ + (csq_cnt_ib2 << CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT)) + +#define CP_CSQ_AVAIL_GET_CSQ_CNT_RING(cp_csq_avail) \ + ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_RING_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT) +#define CP_CSQ_AVAIL_GET_CSQ_CNT_IB1(cp_csq_avail) \ + ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT) +#define CP_CSQ_AVAIL_GET_CSQ_CNT_IB2(cp_csq_avail) \ + ((cp_csq_avail & CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) >> CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT) + +#define CP_CSQ_AVAIL_SET_CSQ_CNT_RING(cp_csq_avail_reg, csq_cnt_ring) \ + cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_RING_MASK) | (csq_cnt_ring << CP_CSQ_AVAIL_CSQ_CNT_RING_SHIFT) +#define CP_CSQ_AVAIL_SET_CSQ_CNT_IB1(cp_csq_avail_reg, csq_cnt_ib1) \ + cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_IB1_MASK) | (csq_cnt_ib1 << CP_CSQ_AVAIL_CSQ_CNT_IB1_SHIFT) +#define CP_CSQ_AVAIL_SET_CSQ_CNT_IB2(cp_csq_avail_reg, csq_cnt_ib2) \ + cp_csq_avail_reg = (cp_csq_avail_reg & ~CP_CSQ_AVAIL_CSQ_CNT_IB2_MASK) | (csq_cnt_ib2 << CP_CSQ_AVAIL_CSQ_CNT_IB2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_csq_avail_t { + unsigned int csq_cnt_ring : CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE; + unsigned int : 1; + unsigned int csq_cnt_ib1 : CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE; + unsigned int : 1; + unsigned int csq_cnt_ib2 : CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE; + unsigned int : 9; + } cp_csq_avail_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_csq_avail_t { + unsigned int : 9; + unsigned int csq_cnt_ib2 : CP_CSQ_AVAIL_CSQ_CNT_IB2_SIZE; + unsigned int : 1; + unsigned int csq_cnt_ib1 : CP_CSQ_AVAIL_CSQ_CNT_IB1_SIZE; + unsigned int : 1; + unsigned int csq_cnt_ring : CP_CSQ_AVAIL_CSQ_CNT_RING_SIZE; + } cp_csq_avail_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_csq_avail_t f; +} cp_csq_avail_u; + + +/* + * CP_STQ_AVAIL struct + */ + +#define CP_STQ_AVAIL_STQ_CNT_ST_SIZE 7 + +#define CP_STQ_AVAIL_STQ_CNT_ST_SHIFT 0 + +#define CP_STQ_AVAIL_STQ_CNT_ST_MASK 0x0000007f + +#define CP_STQ_AVAIL_MASK \ + (CP_STQ_AVAIL_STQ_CNT_ST_MASK) + +#define CP_STQ_AVAIL(stq_cnt_st) \ + ((stq_cnt_st << CP_STQ_AVAIL_STQ_CNT_ST_SHIFT)) + +#define CP_STQ_AVAIL_GET_STQ_CNT_ST(cp_stq_avail) \ + ((cp_stq_avail & CP_STQ_AVAIL_STQ_CNT_ST_MASK) >> CP_STQ_AVAIL_STQ_CNT_ST_SHIFT) + +#define CP_STQ_AVAIL_SET_STQ_CNT_ST(cp_stq_avail_reg, stq_cnt_st) \ + cp_stq_avail_reg = (cp_stq_avail_reg & ~CP_STQ_AVAIL_STQ_CNT_ST_MASK) | (stq_cnt_st << CP_STQ_AVAIL_STQ_CNT_ST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_stq_avail_t { + unsigned int stq_cnt_st : CP_STQ_AVAIL_STQ_CNT_ST_SIZE; + unsigned int : 25; + } cp_stq_avail_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_stq_avail_t { + unsigned int : 25; + unsigned int stq_cnt_st : CP_STQ_AVAIL_STQ_CNT_ST_SIZE; + } cp_stq_avail_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_stq_avail_t f; +} cp_stq_avail_u; + + +/* + * CP_MEQ_AVAIL struct + */ + +#define CP_MEQ_AVAIL_MEQ_CNT_SIZE 5 + +#define CP_MEQ_AVAIL_MEQ_CNT_SHIFT 0 + +#define CP_MEQ_AVAIL_MEQ_CNT_MASK 0x0000001f + +#define CP_MEQ_AVAIL_MASK \ + (CP_MEQ_AVAIL_MEQ_CNT_MASK) + +#define CP_MEQ_AVAIL(meq_cnt) \ + ((meq_cnt << CP_MEQ_AVAIL_MEQ_CNT_SHIFT)) + +#define CP_MEQ_AVAIL_GET_MEQ_CNT(cp_meq_avail) \ + ((cp_meq_avail & CP_MEQ_AVAIL_MEQ_CNT_MASK) >> CP_MEQ_AVAIL_MEQ_CNT_SHIFT) + +#define CP_MEQ_AVAIL_SET_MEQ_CNT(cp_meq_avail_reg, meq_cnt) \ + cp_meq_avail_reg = (cp_meq_avail_reg & ~CP_MEQ_AVAIL_MEQ_CNT_MASK) | (meq_cnt << CP_MEQ_AVAIL_MEQ_CNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_meq_avail_t { + unsigned int meq_cnt : CP_MEQ_AVAIL_MEQ_CNT_SIZE; + unsigned int : 27; + } cp_meq_avail_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_meq_avail_t { + unsigned int : 27; + unsigned int meq_cnt : CP_MEQ_AVAIL_MEQ_CNT_SIZE; + } cp_meq_avail_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_meq_avail_t f; +} cp_meq_avail_u; + + +/* + * CP_CSQ_RB_STAT struct + */ + +#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE 7 +#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE 7 + +#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT 0 +#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT 16 + +#define CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK 0x0000007f +#define CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK 0x007f0000 + +#define CP_CSQ_RB_STAT_MASK \ + (CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK | \ + CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) + +#define CP_CSQ_RB_STAT(csq_rptr_primary, csq_wptr_primary) \ + ((csq_rptr_primary << CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT) | \ + (csq_wptr_primary << CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT)) + +#define CP_CSQ_RB_STAT_GET_CSQ_RPTR_PRIMARY(cp_csq_rb_stat) \ + ((cp_csq_rb_stat & CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK) >> CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT) +#define CP_CSQ_RB_STAT_GET_CSQ_WPTR_PRIMARY(cp_csq_rb_stat) \ + ((cp_csq_rb_stat & CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) >> CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT) + +#define CP_CSQ_RB_STAT_SET_CSQ_RPTR_PRIMARY(cp_csq_rb_stat_reg, csq_rptr_primary) \ + cp_csq_rb_stat_reg = (cp_csq_rb_stat_reg & ~CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_MASK) | (csq_rptr_primary << CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SHIFT) +#define CP_CSQ_RB_STAT_SET_CSQ_WPTR_PRIMARY(cp_csq_rb_stat_reg, csq_wptr_primary) \ + cp_csq_rb_stat_reg = (cp_csq_rb_stat_reg & ~CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_MASK) | (csq_wptr_primary << CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_csq_rb_stat_t { + unsigned int csq_rptr_primary : CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE; + unsigned int : 9; + unsigned int csq_wptr_primary : CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE; + unsigned int : 9; + } cp_csq_rb_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_csq_rb_stat_t { + unsigned int : 9; + unsigned int csq_wptr_primary : CP_CSQ_RB_STAT_CSQ_WPTR_PRIMARY_SIZE; + unsigned int : 9; + unsigned int csq_rptr_primary : CP_CSQ_RB_STAT_CSQ_RPTR_PRIMARY_SIZE; + } cp_csq_rb_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_csq_rb_stat_t f; +} cp_csq_rb_stat_u; + + +/* + * CP_CSQ_IB1_STAT struct + */ + +#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE 7 +#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE 7 + +#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT 0 +#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT 16 + +#define CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK 0x0000007f +#define CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK 0x007f0000 + +#define CP_CSQ_IB1_STAT_MASK \ + (CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK | \ + CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) + +#define CP_CSQ_IB1_STAT(csq_rptr_indirect1, csq_wptr_indirect1) \ + ((csq_rptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT) | \ + (csq_wptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT)) + +#define CP_CSQ_IB1_STAT_GET_CSQ_RPTR_INDIRECT1(cp_csq_ib1_stat) \ + ((cp_csq_ib1_stat & CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK) >> CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT) +#define CP_CSQ_IB1_STAT_GET_CSQ_WPTR_INDIRECT1(cp_csq_ib1_stat) \ + ((cp_csq_ib1_stat & CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) >> CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT) + +#define CP_CSQ_IB1_STAT_SET_CSQ_RPTR_INDIRECT1(cp_csq_ib1_stat_reg, csq_rptr_indirect1) \ + cp_csq_ib1_stat_reg = (cp_csq_ib1_stat_reg & ~CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_MASK) | (csq_rptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SHIFT) +#define CP_CSQ_IB1_STAT_SET_CSQ_WPTR_INDIRECT1(cp_csq_ib1_stat_reg, csq_wptr_indirect1) \ + cp_csq_ib1_stat_reg = (cp_csq_ib1_stat_reg & ~CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_MASK) | (csq_wptr_indirect1 << CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_csq_ib1_stat_t { + unsigned int csq_rptr_indirect1 : CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE; + unsigned int : 9; + unsigned int csq_wptr_indirect1 : CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE; + unsigned int : 9; + } cp_csq_ib1_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_csq_ib1_stat_t { + unsigned int : 9; + unsigned int csq_wptr_indirect1 : CP_CSQ_IB1_STAT_CSQ_WPTR_INDIRECT1_SIZE; + unsigned int : 9; + unsigned int csq_rptr_indirect1 : CP_CSQ_IB1_STAT_CSQ_RPTR_INDIRECT1_SIZE; + } cp_csq_ib1_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_csq_ib1_stat_t f; +} cp_csq_ib1_stat_u; + + +/* + * CP_CSQ_IB2_STAT struct + */ + +#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE 7 +#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE 7 + +#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT 0 +#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT 16 + +#define CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK 0x0000007f +#define CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK 0x007f0000 + +#define CP_CSQ_IB2_STAT_MASK \ + (CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK | \ + CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) + +#define CP_CSQ_IB2_STAT(csq_rptr_indirect2, csq_wptr_indirect2) \ + ((csq_rptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT) | \ + (csq_wptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT)) + +#define CP_CSQ_IB2_STAT_GET_CSQ_RPTR_INDIRECT2(cp_csq_ib2_stat) \ + ((cp_csq_ib2_stat & CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK) >> CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT) +#define CP_CSQ_IB2_STAT_GET_CSQ_WPTR_INDIRECT2(cp_csq_ib2_stat) \ + ((cp_csq_ib2_stat & CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) >> CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT) + +#define CP_CSQ_IB2_STAT_SET_CSQ_RPTR_INDIRECT2(cp_csq_ib2_stat_reg, csq_rptr_indirect2) \ + cp_csq_ib2_stat_reg = (cp_csq_ib2_stat_reg & ~CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_MASK) | (csq_rptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SHIFT) +#define CP_CSQ_IB2_STAT_SET_CSQ_WPTR_INDIRECT2(cp_csq_ib2_stat_reg, csq_wptr_indirect2) \ + cp_csq_ib2_stat_reg = (cp_csq_ib2_stat_reg & ~CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_MASK) | (csq_wptr_indirect2 << CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_csq_ib2_stat_t { + unsigned int csq_rptr_indirect2 : CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE; + unsigned int : 9; + unsigned int csq_wptr_indirect2 : CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE; + unsigned int : 9; + } cp_csq_ib2_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_csq_ib2_stat_t { + unsigned int : 9; + unsigned int csq_wptr_indirect2 : CP_CSQ_IB2_STAT_CSQ_WPTR_INDIRECT2_SIZE; + unsigned int : 9; + unsigned int csq_rptr_indirect2 : CP_CSQ_IB2_STAT_CSQ_RPTR_INDIRECT2_SIZE; + } cp_csq_ib2_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_csq_ib2_stat_t f; +} cp_csq_ib2_stat_u; + + +/* + * CP_NON_PREFETCH_CNTRS struct + */ + +#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE 3 +#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE 3 + +#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT 0 +#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT 8 + +#define CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK 0x00000007 +#define CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK 0x00000700 + +#define CP_NON_PREFETCH_CNTRS_MASK \ + (CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK | \ + CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) + +#define CP_NON_PREFETCH_CNTRS(ib1_counter, ib2_counter) \ + ((ib1_counter << CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT) | \ + (ib2_counter << CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT)) + +#define CP_NON_PREFETCH_CNTRS_GET_IB1_COUNTER(cp_non_prefetch_cntrs) \ + ((cp_non_prefetch_cntrs & CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK) >> CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT) +#define CP_NON_PREFETCH_CNTRS_GET_IB2_COUNTER(cp_non_prefetch_cntrs) \ + ((cp_non_prefetch_cntrs & CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) >> CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT) + +#define CP_NON_PREFETCH_CNTRS_SET_IB1_COUNTER(cp_non_prefetch_cntrs_reg, ib1_counter) \ + cp_non_prefetch_cntrs_reg = (cp_non_prefetch_cntrs_reg & ~CP_NON_PREFETCH_CNTRS_IB1_COUNTER_MASK) | (ib1_counter << CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SHIFT) +#define CP_NON_PREFETCH_CNTRS_SET_IB2_COUNTER(cp_non_prefetch_cntrs_reg, ib2_counter) \ + cp_non_prefetch_cntrs_reg = (cp_non_prefetch_cntrs_reg & ~CP_NON_PREFETCH_CNTRS_IB2_COUNTER_MASK) | (ib2_counter << CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_non_prefetch_cntrs_t { + unsigned int ib1_counter : CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE; + unsigned int : 5; + unsigned int ib2_counter : CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE; + unsigned int : 21; + } cp_non_prefetch_cntrs_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_non_prefetch_cntrs_t { + unsigned int : 21; + unsigned int ib2_counter : CP_NON_PREFETCH_CNTRS_IB2_COUNTER_SIZE; + unsigned int : 5; + unsigned int ib1_counter : CP_NON_PREFETCH_CNTRS_IB1_COUNTER_SIZE; + } cp_non_prefetch_cntrs_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_non_prefetch_cntrs_t f; +} cp_non_prefetch_cntrs_u; + + +/* + * CP_STQ_ST_STAT struct + */ + +#define CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE 7 +#define CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE 7 + +#define CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT 0 +#define CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT 16 + +#define CP_STQ_ST_STAT_STQ_RPTR_ST_MASK 0x0000007f +#define CP_STQ_ST_STAT_STQ_WPTR_ST_MASK 0x007f0000 + +#define CP_STQ_ST_STAT_MASK \ + (CP_STQ_ST_STAT_STQ_RPTR_ST_MASK | \ + CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) + +#define CP_STQ_ST_STAT(stq_rptr_st, stq_wptr_st) \ + ((stq_rptr_st << CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT) | \ + (stq_wptr_st << CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT)) + +#define CP_STQ_ST_STAT_GET_STQ_RPTR_ST(cp_stq_st_stat) \ + ((cp_stq_st_stat & CP_STQ_ST_STAT_STQ_RPTR_ST_MASK) >> CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT) +#define CP_STQ_ST_STAT_GET_STQ_WPTR_ST(cp_stq_st_stat) \ + ((cp_stq_st_stat & CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) >> CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT) + +#define CP_STQ_ST_STAT_SET_STQ_RPTR_ST(cp_stq_st_stat_reg, stq_rptr_st) \ + cp_stq_st_stat_reg = (cp_stq_st_stat_reg & ~CP_STQ_ST_STAT_STQ_RPTR_ST_MASK) | (stq_rptr_st << CP_STQ_ST_STAT_STQ_RPTR_ST_SHIFT) +#define CP_STQ_ST_STAT_SET_STQ_WPTR_ST(cp_stq_st_stat_reg, stq_wptr_st) \ + cp_stq_st_stat_reg = (cp_stq_st_stat_reg & ~CP_STQ_ST_STAT_STQ_WPTR_ST_MASK) | (stq_wptr_st << CP_STQ_ST_STAT_STQ_WPTR_ST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_stq_st_stat_t { + unsigned int stq_rptr_st : CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE; + unsigned int : 9; + unsigned int stq_wptr_st : CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE; + unsigned int : 9; + } cp_stq_st_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_stq_st_stat_t { + unsigned int : 9; + unsigned int stq_wptr_st : CP_STQ_ST_STAT_STQ_WPTR_ST_SIZE; + unsigned int : 9; + unsigned int stq_rptr_st : CP_STQ_ST_STAT_STQ_RPTR_ST_SIZE; + } cp_stq_st_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_stq_st_stat_t f; +} cp_stq_st_stat_u; + + +/* + * CP_MEQ_STAT struct + */ + +#define CP_MEQ_STAT_MEQ_RPTR_SIZE 10 +#define CP_MEQ_STAT_MEQ_WPTR_SIZE 10 + +#define CP_MEQ_STAT_MEQ_RPTR_SHIFT 0 +#define CP_MEQ_STAT_MEQ_WPTR_SHIFT 16 + +#define CP_MEQ_STAT_MEQ_RPTR_MASK 0x000003ff +#define CP_MEQ_STAT_MEQ_WPTR_MASK 0x03ff0000 + +#define CP_MEQ_STAT_MASK \ + (CP_MEQ_STAT_MEQ_RPTR_MASK | \ + CP_MEQ_STAT_MEQ_WPTR_MASK) + +#define CP_MEQ_STAT(meq_rptr, meq_wptr) \ + ((meq_rptr << CP_MEQ_STAT_MEQ_RPTR_SHIFT) | \ + (meq_wptr << CP_MEQ_STAT_MEQ_WPTR_SHIFT)) + +#define CP_MEQ_STAT_GET_MEQ_RPTR(cp_meq_stat) \ + ((cp_meq_stat & CP_MEQ_STAT_MEQ_RPTR_MASK) >> CP_MEQ_STAT_MEQ_RPTR_SHIFT) +#define CP_MEQ_STAT_GET_MEQ_WPTR(cp_meq_stat) \ + ((cp_meq_stat & CP_MEQ_STAT_MEQ_WPTR_MASK) >> CP_MEQ_STAT_MEQ_WPTR_SHIFT) + +#define CP_MEQ_STAT_SET_MEQ_RPTR(cp_meq_stat_reg, meq_rptr) \ + cp_meq_stat_reg = (cp_meq_stat_reg & ~CP_MEQ_STAT_MEQ_RPTR_MASK) | (meq_rptr << CP_MEQ_STAT_MEQ_RPTR_SHIFT) +#define CP_MEQ_STAT_SET_MEQ_WPTR(cp_meq_stat_reg, meq_wptr) \ + cp_meq_stat_reg = (cp_meq_stat_reg & ~CP_MEQ_STAT_MEQ_WPTR_MASK) | (meq_wptr << CP_MEQ_STAT_MEQ_WPTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_meq_stat_t { + unsigned int meq_rptr : CP_MEQ_STAT_MEQ_RPTR_SIZE; + unsigned int : 6; + unsigned int meq_wptr : CP_MEQ_STAT_MEQ_WPTR_SIZE; + unsigned int : 6; + } cp_meq_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_meq_stat_t { + unsigned int : 6; + unsigned int meq_wptr : CP_MEQ_STAT_MEQ_WPTR_SIZE; + unsigned int : 6; + unsigned int meq_rptr : CP_MEQ_STAT_MEQ_RPTR_SIZE; + } cp_meq_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_meq_stat_t f; +} cp_meq_stat_u; + + +/* + * CP_MIU_TAG_STAT struct + */ + +#define CP_MIU_TAG_STAT_TAG_0_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_1_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_2_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_3_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_4_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_5_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_6_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_7_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_8_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_9_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_10_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_11_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_12_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_13_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_14_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_15_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_16_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_TAG_17_STAT_SIZE 1 +#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE 1 + +#define CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT 0 +#define CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT 1 +#define CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT 2 +#define CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT 3 +#define CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT 4 +#define CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT 5 +#define CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT 6 +#define CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT 7 +#define CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT 8 +#define CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT 9 +#define CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT 10 +#define CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT 11 +#define CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT 12 +#define CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT 13 +#define CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT 14 +#define CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT 15 +#define CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT 16 +#define CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT 17 +#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT 31 + +#define CP_MIU_TAG_STAT_TAG_0_STAT_MASK 0x00000001 +#define CP_MIU_TAG_STAT_TAG_1_STAT_MASK 0x00000002 +#define CP_MIU_TAG_STAT_TAG_2_STAT_MASK 0x00000004 +#define CP_MIU_TAG_STAT_TAG_3_STAT_MASK 0x00000008 +#define CP_MIU_TAG_STAT_TAG_4_STAT_MASK 0x00000010 +#define CP_MIU_TAG_STAT_TAG_5_STAT_MASK 0x00000020 +#define CP_MIU_TAG_STAT_TAG_6_STAT_MASK 0x00000040 +#define CP_MIU_TAG_STAT_TAG_7_STAT_MASK 0x00000080 +#define CP_MIU_TAG_STAT_TAG_8_STAT_MASK 0x00000100 +#define CP_MIU_TAG_STAT_TAG_9_STAT_MASK 0x00000200 +#define CP_MIU_TAG_STAT_TAG_10_STAT_MASK 0x00000400 +#define CP_MIU_TAG_STAT_TAG_11_STAT_MASK 0x00000800 +#define CP_MIU_TAG_STAT_TAG_12_STAT_MASK 0x00001000 +#define CP_MIU_TAG_STAT_TAG_13_STAT_MASK 0x00002000 +#define CP_MIU_TAG_STAT_TAG_14_STAT_MASK 0x00004000 +#define CP_MIU_TAG_STAT_TAG_15_STAT_MASK 0x00008000 +#define CP_MIU_TAG_STAT_TAG_16_STAT_MASK 0x00010000 +#define CP_MIU_TAG_STAT_TAG_17_STAT_MASK 0x00020000 +#define CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK 0x80000000 + +#define CP_MIU_TAG_STAT_MASK \ + (CP_MIU_TAG_STAT_TAG_0_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_1_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_2_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_3_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_4_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_5_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_6_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_7_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_8_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_9_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_10_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_11_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_12_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_13_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_14_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_15_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_16_STAT_MASK | \ + CP_MIU_TAG_STAT_TAG_17_STAT_MASK | \ + CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) + +#define CP_MIU_TAG_STAT(tag_0_stat, tag_1_stat, tag_2_stat, tag_3_stat, tag_4_stat, tag_5_stat, tag_6_stat, tag_7_stat, tag_8_stat, tag_9_stat, tag_10_stat, tag_11_stat, tag_12_stat, tag_13_stat, tag_14_stat, tag_15_stat, tag_16_stat, tag_17_stat, invalid_return_tag) \ + ((tag_0_stat << CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT) | \ + (tag_1_stat << CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT) | \ + (tag_2_stat << CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT) | \ + (tag_3_stat << CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT) | \ + (tag_4_stat << CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT) | \ + (tag_5_stat << CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT) | \ + (tag_6_stat << CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT) | \ + (tag_7_stat << CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT) | \ + (tag_8_stat << CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT) | \ + (tag_9_stat << CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT) | \ + (tag_10_stat << CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT) | \ + (tag_11_stat << CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT) | \ + (tag_12_stat << CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT) | \ + (tag_13_stat << CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT) | \ + (tag_14_stat << CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT) | \ + (tag_15_stat << CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT) | \ + (tag_16_stat << CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT) | \ + (tag_17_stat << CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT) | \ + (invalid_return_tag << CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT)) + +#define CP_MIU_TAG_STAT_GET_TAG_0_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_0_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_1_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_1_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_2_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_2_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_3_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_3_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_4_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_4_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_5_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_5_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_6_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_6_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_7_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_7_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_8_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_8_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_9_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_9_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_10_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_10_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_11_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_11_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_12_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_12_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_13_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_13_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_14_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_14_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_15_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_15_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_16_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_16_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_TAG_17_STAT(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_TAG_17_STAT_MASK) >> CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT) +#define CP_MIU_TAG_STAT_GET_INVALID_RETURN_TAG(cp_miu_tag_stat) \ + ((cp_miu_tag_stat & CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) >> CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT) + +#define CP_MIU_TAG_STAT_SET_TAG_0_STAT(cp_miu_tag_stat_reg, tag_0_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_0_STAT_MASK) | (tag_0_stat << CP_MIU_TAG_STAT_TAG_0_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_1_STAT(cp_miu_tag_stat_reg, tag_1_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_1_STAT_MASK) | (tag_1_stat << CP_MIU_TAG_STAT_TAG_1_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_2_STAT(cp_miu_tag_stat_reg, tag_2_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_2_STAT_MASK) | (tag_2_stat << CP_MIU_TAG_STAT_TAG_2_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_3_STAT(cp_miu_tag_stat_reg, tag_3_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_3_STAT_MASK) | (tag_3_stat << CP_MIU_TAG_STAT_TAG_3_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_4_STAT(cp_miu_tag_stat_reg, tag_4_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_4_STAT_MASK) | (tag_4_stat << CP_MIU_TAG_STAT_TAG_4_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_5_STAT(cp_miu_tag_stat_reg, tag_5_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_5_STAT_MASK) | (tag_5_stat << CP_MIU_TAG_STAT_TAG_5_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_6_STAT(cp_miu_tag_stat_reg, tag_6_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_6_STAT_MASK) | (tag_6_stat << CP_MIU_TAG_STAT_TAG_6_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_7_STAT(cp_miu_tag_stat_reg, tag_7_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_7_STAT_MASK) | (tag_7_stat << CP_MIU_TAG_STAT_TAG_7_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_8_STAT(cp_miu_tag_stat_reg, tag_8_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_8_STAT_MASK) | (tag_8_stat << CP_MIU_TAG_STAT_TAG_8_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_9_STAT(cp_miu_tag_stat_reg, tag_9_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_9_STAT_MASK) | (tag_9_stat << CP_MIU_TAG_STAT_TAG_9_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_10_STAT(cp_miu_tag_stat_reg, tag_10_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_10_STAT_MASK) | (tag_10_stat << CP_MIU_TAG_STAT_TAG_10_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_11_STAT(cp_miu_tag_stat_reg, tag_11_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_11_STAT_MASK) | (tag_11_stat << CP_MIU_TAG_STAT_TAG_11_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_12_STAT(cp_miu_tag_stat_reg, tag_12_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_12_STAT_MASK) | (tag_12_stat << CP_MIU_TAG_STAT_TAG_12_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_13_STAT(cp_miu_tag_stat_reg, tag_13_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_13_STAT_MASK) | (tag_13_stat << CP_MIU_TAG_STAT_TAG_13_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_14_STAT(cp_miu_tag_stat_reg, tag_14_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_14_STAT_MASK) | (tag_14_stat << CP_MIU_TAG_STAT_TAG_14_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_15_STAT(cp_miu_tag_stat_reg, tag_15_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_15_STAT_MASK) | (tag_15_stat << CP_MIU_TAG_STAT_TAG_15_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_16_STAT(cp_miu_tag_stat_reg, tag_16_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_16_STAT_MASK) | (tag_16_stat << CP_MIU_TAG_STAT_TAG_16_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_TAG_17_STAT(cp_miu_tag_stat_reg, tag_17_stat) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_TAG_17_STAT_MASK) | (tag_17_stat << CP_MIU_TAG_STAT_TAG_17_STAT_SHIFT) +#define CP_MIU_TAG_STAT_SET_INVALID_RETURN_TAG(cp_miu_tag_stat_reg, invalid_return_tag) \ + cp_miu_tag_stat_reg = (cp_miu_tag_stat_reg & ~CP_MIU_TAG_STAT_INVALID_RETURN_TAG_MASK) | (invalid_return_tag << CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_miu_tag_stat_t { + unsigned int tag_0_stat : CP_MIU_TAG_STAT_TAG_0_STAT_SIZE; + unsigned int tag_1_stat : CP_MIU_TAG_STAT_TAG_1_STAT_SIZE; + unsigned int tag_2_stat : CP_MIU_TAG_STAT_TAG_2_STAT_SIZE; + unsigned int tag_3_stat : CP_MIU_TAG_STAT_TAG_3_STAT_SIZE; + unsigned int tag_4_stat : CP_MIU_TAG_STAT_TAG_4_STAT_SIZE; + unsigned int tag_5_stat : CP_MIU_TAG_STAT_TAG_5_STAT_SIZE; + unsigned int tag_6_stat : CP_MIU_TAG_STAT_TAG_6_STAT_SIZE; + unsigned int tag_7_stat : CP_MIU_TAG_STAT_TAG_7_STAT_SIZE; + unsigned int tag_8_stat : CP_MIU_TAG_STAT_TAG_8_STAT_SIZE; + unsigned int tag_9_stat : CP_MIU_TAG_STAT_TAG_9_STAT_SIZE; + unsigned int tag_10_stat : CP_MIU_TAG_STAT_TAG_10_STAT_SIZE; + unsigned int tag_11_stat : CP_MIU_TAG_STAT_TAG_11_STAT_SIZE; + unsigned int tag_12_stat : CP_MIU_TAG_STAT_TAG_12_STAT_SIZE; + unsigned int tag_13_stat : CP_MIU_TAG_STAT_TAG_13_STAT_SIZE; + unsigned int tag_14_stat : CP_MIU_TAG_STAT_TAG_14_STAT_SIZE; + unsigned int tag_15_stat : CP_MIU_TAG_STAT_TAG_15_STAT_SIZE; + unsigned int tag_16_stat : CP_MIU_TAG_STAT_TAG_16_STAT_SIZE; + unsigned int tag_17_stat : CP_MIU_TAG_STAT_TAG_17_STAT_SIZE; + unsigned int : 13; + unsigned int invalid_return_tag : CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE; + } cp_miu_tag_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_miu_tag_stat_t { + unsigned int invalid_return_tag : CP_MIU_TAG_STAT_INVALID_RETURN_TAG_SIZE; + unsigned int : 13; + unsigned int tag_17_stat : CP_MIU_TAG_STAT_TAG_17_STAT_SIZE; + unsigned int tag_16_stat : CP_MIU_TAG_STAT_TAG_16_STAT_SIZE; + unsigned int tag_15_stat : CP_MIU_TAG_STAT_TAG_15_STAT_SIZE; + unsigned int tag_14_stat : CP_MIU_TAG_STAT_TAG_14_STAT_SIZE; + unsigned int tag_13_stat : CP_MIU_TAG_STAT_TAG_13_STAT_SIZE; + unsigned int tag_12_stat : CP_MIU_TAG_STAT_TAG_12_STAT_SIZE; + unsigned int tag_11_stat : CP_MIU_TAG_STAT_TAG_11_STAT_SIZE; + unsigned int tag_10_stat : CP_MIU_TAG_STAT_TAG_10_STAT_SIZE; + unsigned int tag_9_stat : CP_MIU_TAG_STAT_TAG_9_STAT_SIZE; + unsigned int tag_8_stat : CP_MIU_TAG_STAT_TAG_8_STAT_SIZE; + unsigned int tag_7_stat : CP_MIU_TAG_STAT_TAG_7_STAT_SIZE; + unsigned int tag_6_stat : CP_MIU_TAG_STAT_TAG_6_STAT_SIZE; + unsigned int tag_5_stat : CP_MIU_TAG_STAT_TAG_5_STAT_SIZE; + unsigned int tag_4_stat : CP_MIU_TAG_STAT_TAG_4_STAT_SIZE; + unsigned int tag_3_stat : CP_MIU_TAG_STAT_TAG_3_STAT_SIZE; + unsigned int tag_2_stat : CP_MIU_TAG_STAT_TAG_2_STAT_SIZE; + unsigned int tag_1_stat : CP_MIU_TAG_STAT_TAG_1_STAT_SIZE; + unsigned int tag_0_stat : CP_MIU_TAG_STAT_TAG_0_STAT_SIZE; + } cp_miu_tag_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_miu_tag_stat_t f; +} cp_miu_tag_stat_u; + + +/* + * CP_CMD_INDEX struct + */ + +#define CP_CMD_INDEX_CMD_INDEX_SIZE 7 +#define CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE 2 + +#define CP_CMD_INDEX_CMD_INDEX_SHIFT 0 +#define CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT 16 + +#define CP_CMD_INDEX_CMD_INDEX_MASK 0x0000007f +#define CP_CMD_INDEX_CMD_QUEUE_SEL_MASK 0x00030000 + +#define CP_CMD_INDEX_MASK \ + (CP_CMD_INDEX_CMD_INDEX_MASK | \ + CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) + +#define CP_CMD_INDEX(cmd_index, cmd_queue_sel) \ + ((cmd_index << CP_CMD_INDEX_CMD_INDEX_SHIFT) | \ + (cmd_queue_sel << CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT)) + +#define CP_CMD_INDEX_GET_CMD_INDEX(cp_cmd_index) \ + ((cp_cmd_index & CP_CMD_INDEX_CMD_INDEX_MASK) >> CP_CMD_INDEX_CMD_INDEX_SHIFT) +#define CP_CMD_INDEX_GET_CMD_QUEUE_SEL(cp_cmd_index) \ + ((cp_cmd_index & CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) >> CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT) + +#define CP_CMD_INDEX_SET_CMD_INDEX(cp_cmd_index_reg, cmd_index) \ + cp_cmd_index_reg = (cp_cmd_index_reg & ~CP_CMD_INDEX_CMD_INDEX_MASK) | (cmd_index << CP_CMD_INDEX_CMD_INDEX_SHIFT) +#define CP_CMD_INDEX_SET_CMD_QUEUE_SEL(cp_cmd_index_reg, cmd_queue_sel) \ + cp_cmd_index_reg = (cp_cmd_index_reg & ~CP_CMD_INDEX_CMD_QUEUE_SEL_MASK) | (cmd_queue_sel << CP_CMD_INDEX_CMD_QUEUE_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_cmd_index_t { + unsigned int cmd_index : CP_CMD_INDEX_CMD_INDEX_SIZE; + unsigned int : 9; + unsigned int cmd_queue_sel : CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE; + unsigned int : 14; + } cp_cmd_index_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_cmd_index_t { + unsigned int : 14; + unsigned int cmd_queue_sel : CP_CMD_INDEX_CMD_QUEUE_SEL_SIZE; + unsigned int : 9; + unsigned int cmd_index : CP_CMD_INDEX_CMD_INDEX_SIZE; + } cp_cmd_index_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_cmd_index_t f; +} cp_cmd_index_u; + + +/* + * CP_CMD_DATA struct + */ + +#define CP_CMD_DATA_CMD_DATA_SIZE 32 + +#define CP_CMD_DATA_CMD_DATA_SHIFT 0 + +#define CP_CMD_DATA_CMD_DATA_MASK 0xffffffff + +#define CP_CMD_DATA_MASK \ + (CP_CMD_DATA_CMD_DATA_MASK) + +#define CP_CMD_DATA(cmd_data) \ + ((cmd_data << CP_CMD_DATA_CMD_DATA_SHIFT)) + +#define CP_CMD_DATA_GET_CMD_DATA(cp_cmd_data) \ + ((cp_cmd_data & CP_CMD_DATA_CMD_DATA_MASK) >> CP_CMD_DATA_CMD_DATA_SHIFT) + +#define CP_CMD_DATA_SET_CMD_DATA(cp_cmd_data_reg, cmd_data) \ + cp_cmd_data_reg = (cp_cmd_data_reg & ~CP_CMD_DATA_CMD_DATA_MASK) | (cmd_data << CP_CMD_DATA_CMD_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_cmd_data_t { + unsigned int cmd_data : CP_CMD_DATA_CMD_DATA_SIZE; + } cp_cmd_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_cmd_data_t { + unsigned int cmd_data : CP_CMD_DATA_CMD_DATA_SIZE; + } cp_cmd_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_cmd_data_t f; +} cp_cmd_data_u; + + +/* + * CP_ME_CNTL struct + */ + +#define CP_ME_CNTL_ME_STATMUX_SIZE 16 +#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE 1 +#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE 1 +#define CP_ME_CNTL_ME_HALT_SIZE 1 +#define CP_ME_CNTL_ME_BUSY_SIZE 1 +#define CP_ME_CNTL_PROG_CNT_SIZE_SIZE 1 + +#define CP_ME_CNTL_ME_STATMUX_SHIFT 0 +#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT 25 +#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT 26 +#define CP_ME_CNTL_ME_HALT_SHIFT 28 +#define CP_ME_CNTL_ME_BUSY_SHIFT 29 +#define CP_ME_CNTL_PROG_CNT_SIZE_SHIFT 31 + +#define CP_ME_CNTL_ME_STATMUX_MASK 0x0000ffff +#define CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK 0x02000000 +#define CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK 0x04000000 +#define CP_ME_CNTL_ME_HALT_MASK 0x10000000 +#define CP_ME_CNTL_ME_BUSY_MASK 0x20000000 +#define CP_ME_CNTL_PROG_CNT_SIZE_MASK 0x80000000 + +#define CP_ME_CNTL_MASK \ + (CP_ME_CNTL_ME_STATMUX_MASK | \ + CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK | \ + CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK | \ + CP_ME_CNTL_ME_HALT_MASK | \ + CP_ME_CNTL_ME_BUSY_MASK | \ + CP_ME_CNTL_PROG_CNT_SIZE_MASK) + +#define CP_ME_CNTL(me_statmux, vtx_dealloc_fifo_empty, pix_dealloc_fifo_empty, me_halt, me_busy, prog_cnt_size) \ + ((me_statmux << CP_ME_CNTL_ME_STATMUX_SHIFT) | \ + (vtx_dealloc_fifo_empty << CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT) | \ + (pix_dealloc_fifo_empty << CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT) | \ + (me_halt << CP_ME_CNTL_ME_HALT_SHIFT) | \ + (me_busy << CP_ME_CNTL_ME_BUSY_SHIFT) | \ + (prog_cnt_size << CP_ME_CNTL_PROG_CNT_SIZE_SHIFT)) + +#define CP_ME_CNTL_GET_ME_STATMUX(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_ME_STATMUX_MASK) >> CP_ME_CNTL_ME_STATMUX_SHIFT) +#define CP_ME_CNTL_GET_VTX_DEALLOC_FIFO_EMPTY(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK) >> CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT) +#define CP_ME_CNTL_GET_PIX_DEALLOC_FIFO_EMPTY(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK) >> CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT) +#define CP_ME_CNTL_GET_ME_HALT(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_ME_HALT_MASK) >> CP_ME_CNTL_ME_HALT_SHIFT) +#define CP_ME_CNTL_GET_ME_BUSY(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_ME_BUSY_MASK) >> CP_ME_CNTL_ME_BUSY_SHIFT) +#define CP_ME_CNTL_GET_PROG_CNT_SIZE(cp_me_cntl) \ + ((cp_me_cntl & CP_ME_CNTL_PROG_CNT_SIZE_MASK) >> CP_ME_CNTL_PROG_CNT_SIZE_SHIFT) + +#define CP_ME_CNTL_SET_ME_STATMUX(cp_me_cntl_reg, me_statmux) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_STATMUX_MASK) | (me_statmux << CP_ME_CNTL_ME_STATMUX_SHIFT) +#define CP_ME_CNTL_SET_VTX_DEALLOC_FIFO_EMPTY(cp_me_cntl_reg, vtx_dealloc_fifo_empty) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_MASK) | (vtx_dealloc_fifo_empty << CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SHIFT) +#define CP_ME_CNTL_SET_PIX_DEALLOC_FIFO_EMPTY(cp_me_cntl_reg, pix_dealloc_fifo_empty) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_MASK) | (pix_dealloc_fifo_empty << CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SHIFT) +#define CP_ME_CNTL_SET_ME_HALT(cp_me_cntl_reg, me_halt) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_HALT_MASK) | (me_halt << CP_ME_CNTL_ME_HALT_SHIFT) +#define CP_ME_CNTL_SET_ME_BUSY(cp_me_cntl_reg, me_busy) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_ME_BUSY_MASK) | (me_busy << CP_ME_CNTL_ME_BUSY_SHIFT) +#define CP_ME_CNTL_SET_PROG_CNT_SIZE(cp_me_cntl_reg, prog_cnt_size) \ + cp_me_cntl_reg = (cp_me_cntl_reg & ~CP_ME_CNTL_PROG_CNT_SIZE_MASK) | (prog_cnt_size << CP_ME_CNTL_PROG_CNT_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_cntl_t { + unsigned int me_statmux : CP_ME_CNTL_ME_STATMUX_SIZE; + unsigned int : 9; + unsigned int vtx_dealloc_fifo_empty : CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE; + unsigned int pix_dealloc_fifo_empty : CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE; + unsigned int : 1; + unsigned int me_halt : CP_ME_CNTL_ME_HALT_SIZE; + unsigned int me_busy : CP_ME_CNTL_ME_BUSY_SIZE; + unsigned int : 1; + unsigned int prog_cnt_size : CP_ME_CNTL_PROG_CNT_SIZE_SIZE; + } cp_me_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_cntl_t { + unsigned int prog_cnt_size : CP_ME_CNTL_PROG_CNT_SIZE_SIZE; + unsigned int : 1; + unsigned int me_busy : CP_ME_CNTL_ME_BUSY_SIZE; + unsigned int me_halt : CP_ME_CNTL_ME_HALT_SIZE; + unsigned int : 1; + unsigned int pix_dealloc_fifo_empty : CP_ME_CNTL_PIX_DEALLOC_FIFO_EMPTY_SIZE; + unsigned int vtx_dealloc_fifo_empty : CP_ME_CNTL_VTX_DEALLOC_FIFO_EMPTY_SIZE; + unsigned int : 9; + unsigned int me_statmux : CP_ME_CNTL_ME_STATMUX_SIZE; + } cp_me_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_cntl_t f; +} cp_me_cntl_u; + + +/* + * CP_ME_STATUS struct + */ + +#define CP_ME_STATUS_ME_DEBUG_DATA_SIZE 32 + +#define CP_ME_STATUS_ME_DEBUG_DATA_SHIFT 0 + +#define CP_ME_STATUS_ME_DEBUG_DATA_MASK 0xffffffff + +#define CP_ME_STATUS_MASK \ + (CP_ME_STATUS_ME_DEBUG_DATA_MASK) + +#define CP_ME_STATUS(me_debug_data) \ + ((me_debug_data << CP_ME_STATUS_ME_DEBUG_DATA_SHIFT)) + +#define CP_ME_STATUS_GET_ME_DEBUG_DATA(cp_me_status) \ + ((cp_me_status & CP_ME_STATUS_ME_DEBUG_DATA_MASK) >> CP_ME_STATUS_ME_DEBUG_DATA_SHIFT) + +#define CP_ME_STATUS_SET_ME_DEBUG_DATA(cp_me_status_reg, me_debug_data) \ + cp_me_status_reg = (cp_me_status_reg & ~CP_ME_STATUS_ME_DEBUG_DATA_MASK) | (me_debug_data << CP_ME_STATUS_ME_DEBUG_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_status_t { + unsigned int me_debug_data : CP_ME_STATUS_ME_DEBUG_DATA_SIZE; + } cp_me_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_status_t { + unsigned int me_debug_data : CP_ME_STATUS_ME_DEBUG_DATA_SIZE; + } cp_me_status_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_status_t f; +} cp_me_status_u; + + +/* + * CP_ME_RAM_WADDR struct + */ + +#define CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE 10 + +#define CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT 0 + +#define CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK 0x000003ff + +#define CP_ME_RAM_WADDR_MASK \ + (CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) + +#define CP_ME_RAM_WADDR(me_ram_waddr) \ + ((me_ram_waddr << CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT)) + +#define CP_ME_RAM_WADDR_GET_ME_RAM_WADDR(cp_me_ram_waddr) \ + ((cp_me_ram_waddr & CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) >> CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT) + +#define CP_ME_RAM_WADDR_SET_ME_RAM_WADDR(cp_me_ram_waddr_reg, me_ram_waddr) \ + cp_me_ram_waddr_reg = (cp_me_ram_waddr_reg & ~CP_ME_RAM_WADDR_ME_RAM_WADDR_MASK) | (me_ram_waddr << CP_ME_RAM_WADDR_ME_RAM_WADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ram_waddr_t { + unsigned int me_ram_waddr : CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE; + unsigned int : 22; + } cp_me_ram_waddr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ram_waddr_t { + unsigned int : 22; + unsigned int me_ram_waddr : CP_ME_RAM_WADDR_ME_RAM_WADDR_SIZE; + } cp_me_ram_waddr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ram_waddr_t f; +} cp_me_ram_waddr_u; + + +/* + * CP_ME_RAM_RADDR struct + */ + +#define CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE 10 + +#define CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT 0 + +#define CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK 0x000003ff + +#define CP_ME_RAM_RADDR_MASK \ + (CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) + +#define CP_ME_RAM_RADDR(me_ram_raddr) \ + ((me_ram_raddr << CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT)) + +#define CP_ME_RAM_RADDR_GET_ME_RAM_RADDR(cp_me_ram_raddr) \ + ((cp_me_ram_raddr & CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) >> CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT) + +#define CP_ME_RAM_RADDR_SET_ME_RAM_RADDR(cp_me_ram_raddr_reg, me_ram_raddr) \ + cp_me_ram_raddr_reg = (cp_me_ram_raddr_reg & ~CP_ME_RAM_RADDR_ME_RAM_RADDR_MASK) | (me_ram_raddr << CP_ME_RAM_RADDR_ME_RAM_RADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ram_raddr_t { + unsigned int me_ram_raddr : CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE; + unsigned int : 22; + } cp_me_ram_raddr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ram_raddr_t { + unsigned int : 22; + unsigned int me_ram_raddr : CP_ME_RAM_RADDR_ME_RAM_RADDR_SIZE; + } cp_me_ram_raddr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ram_raddr_t f; +} cp_me_ram_raddr_u; + + +/* + * CP_ME_RAM_DATA struct + */ + +#define CP_ME_RAM_DATA_ME_RAM_DATA_SIZE 32 + +#define CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT 0 + +#define CP_ME_RAM_DATA_ME_RAM_DATA_MASK 0xffffffff + +#define CP_ME_RAM_DATA_MASK \ + (CP_ME_RAM_DATA_ME_RAM_DATA_MASK) + +#define CP_ME_RAM_DATA(me_ram_data) \ + ((me_ram_data << CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT)) + +#define CP_ME_RAM_DATA_GET_ME_RAM_DATA(cp_me_ram_data) \ + ((cp_me_ram_data & CP_ME_RAM_DATA_ME_RAM_DATA_MASK) >> CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT) + +#define CP_ME_RAM_DATA_SET_ME_RAM_DATA(cp_me_ram_data_reg, me_ram_data) \ + cp_me_ram_data_reg = (cp_me_ram_data_reg & ~CP_ME_RAM_DATA_ME_RAM_DATA_MASK) | (me_ram_data << CP_ME_RAM_DATA_ME_RAM_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ram_data_t { + unsigned int me_ram_data : CP_ME_RAM_DATA_ME_RAM_DATA_SIZE; + } cp_me_ram_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ram_data_t { + unsigned int me_ram_data : CP_ME_RAM_DATA_ME_RAM_DATA_SIZE; + } cp_me_ram_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ram_data_t f; +} cp_me_ram_data_u; + + +/* + * CP_ME_RDADDR struct + */ + +#define CP_ME_RDADDR_ME_RDADDR_SIZE 32 + +#define CP_ME_RDADDR_ME_RDADDR_SHIFT 0 + +#define CP_ME_RDADDR_ME_RDADDR_MASK 0xffffffff + +#define CP_ME_RDADDR_MASK \ + (CP_ME_RDADDR_ME_RDADDR_MASK) + +#define CP_ME_RDADDR(me_rdaddr) \ + ((me_rdaddr << CP_ME_RDADDR_ME_RDADDR_SHIFT)) + +#define CP_ME_RDADDR_GET_ME_RDADDR(cp_me_rdaddr) \ + ((cp_me_rdaddr & CP_ME_RDADDR_ME_RDADDR_MASK) >> CP_ME_RDADDR_ME_RDADDR_SHIFT) + +#define CP_ME_RDADDR_SET_ME_RDADDR(cp_me_rdaddr_reg, me_rdaddr) \ + cp_me_rdaddr_reg = (cp_me_rdaddr_reg & ~CP_ME_RDADDR_ME_RDADDR_MASK) | (me_rdaddr << CP_ME_RDADDR_ME_RDADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_rdaddr_t { + unsigned int me_rdaddr : CP_ME_RDADDR_ME_RDADDR_SIZE; + } cp_me_rdaddr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_rdaddr_t { + unsigned int me_rdaddr : CP_ME_RDADDR_ME_RDADDR_SIZE; + } cp_me_rdaddr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_rdaddr_t f; +} cp_me_rdaddr_u; + + +/* + * CP_DEBUG struct + */ + +#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE 23 +#define CP_DEBUG_PREDICATE_DISABLE_SIZE 1 +#define CP_DEBUG_PROG_END_PTR_ENABLE_SIZE 1 +#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE 1 +#define CP_DEBUG_PREFETCH_PASS_NOPS_SIZE 1 +#define CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE 1 +#define CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE 1 +#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE 1 +#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE 1 + +#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT 0 +#define CP_DEBUG_PREDICATE_DISABLE_SHIFT 23 +#define CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT 24 +#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT 25 +#define CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT 26 +#define CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT 27 +#define CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT 28 +#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT 30 +#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT 31 + +#define CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK 0x007fffff +#define CP_DEBUG_PREDICATE_DISABLE_MASK 0x00800000 +#define CP_DEBUG_PROG_END_PTR_ENABLE_MASK 0x01000000 +#define CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK 0x02000000 +#define CP_DEBUG_PREFETCH_PASS_NOPS_MASK 0x04000000 +#define CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK 0x08000000 +#define CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK 0x10000000 +#define CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK 0x40000000 +#define CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK 0x80000000 + +#define CP_DEBUG_MASK \ + (CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK | \ + CP_DEBUG_PREDICATE_DISABLE_MASK | \ + CP_DEBUG_PROG_END_PTR_ENABLE_MASK | \ + CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK | \ + CP_DEBUG_PREFETCH_PASS_NOPS_MASK | \ + CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK | \ + CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK | \ + CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK | \ + CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) + +#define CP_DEBUG(cp_debug_unused_22_to_0, predicate_disable, prog_end_ptr_enable, miu_128bit_write_enable, prefetch_pass_nops, dynamic_clk_disable, prefetch_match_disable, simple_me_flow_control, miu_write_pack_disable) \ + ((cp_debug_unused_22_to_0 << CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT) | \ + (predicate_disable << CP_DEBUG_PREDICATE_DISABLE_SHIFT) | \ + (prog_end_ptr_enable << CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT) | \ + (miu_128bit_write_enable << CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT) | \ + (prefetch_pass_nops << CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT) | \ + (dynamic_clk_disable << CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT) | \ + (prefetch_match_disable << CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT) | \ + (simple_me_flow_control << CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT) | \ + (miu_write_pack_disable << CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT)) + +#define CP_DEBUG_GET_CP_DEBUG_UNUSED_22_to_0(cp_debug) \ + ((cp_debug & CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK) >> CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT) +#define CP_DEBUG_GET_PREDICATE_DISABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_PREDICATE_DISABLE_MASK) >> CP_DEBUG_PREDICATE_DISABLE_SHIFT) +#define CP_DEBUG_GET_PROG_END_PTR_ENABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_PROG_END_PTR_ENABLE_MASK) >> CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT) +#define CP_DEBUG_GET_MIU_128BIT_WRITE_ENABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK) >> CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT) +#define CP_DEBUG_GET_PREFETCH_PASS_NOPS(cp_debug) \ + ((cp_debug & CP_DEBUG_PREFETCH_PASS_NOPS_MASK) >> CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT) +#define CP_DEBUG_GET_DYNAMIC_CLK_DISABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK) >> CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT) +#define CP_DEBUG_GET_PREFETCH_MATCH_DISABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK) >> CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT) +#define CP_DEBUG_GET_SIMPLE_ME_FLOW_CONTROL(cp_debug) \ + ((cp_debug & CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK) >> CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT) +#define CP_DEBUG_GET_MIU_WRITE_PACK_DISABLE(cp_debug) \ + ((cp_debug & CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) >> CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT) + +#define CP_DEBUG_SET_CP_DEBUG_UNUSED_22_to_0(cp_debug_reg, cp_debug_unused_22_to_0) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_MASK) | (cp_debug_unused_22_to_0 << CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SHIFT) +#define CP_DEBUG_SET_PREDICATE_DISABLE(cp_debug_reg, predicate_disable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREDICATE_DISABLE_MASK) | (predicate_disable << CP_DEBUG_PREDICATE_DISABLE_SHIFT) +#define CP_DEBUG_SET_PROG_END_PTR_ENABLE(cp_debug_reg, prog_end_ptr_enable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PROG_END_PTR_ENABLE_MASK) | (prog_end_ptr_enable << CP_DEBUG_PROG_END_PTR_ENABLE_SHIFT) +#define CP_DEBUG_SET_MIU_128BIT_WRITE_ENABLE(cp_debug_reg, miu_128bit_write_enable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_MIU_128BIT_WRITE_ENABLE_MASK) | (miu_128bit_write_enable << CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SHIFT) +#define CP_DEBUG_SET_PREFETCH_PASS_NOPS(cp_debug_reg, prefetch_pass_nops) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREFETCH_PASS_NOPS_MASK) | (prefetch_pass_nops << CP_DEBUG_PREFETCH_PASS_NOPS_SHIFT) +#define CP_DEBUG_SET_DYNAMIC_CLK_DISABLE(cp_debug_reg, dynamic_clk_disable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_DYNAMIC_CLK_DISABLE_MASK) | (dynamic_clk_disable << CP_DEBUG_DYNAMIC_CLK_DISABLE_SHIFT) +#define CP_DEBUG_SET_PREFETCH_MATCH_DISABLE(cp_debug_reg, prefetch_match_disable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_PREFETCH_MATCH_DISABLE_MASK) | (prefetch_match_disable << CP_DEBUG_PREFETCH_MATCH_DISABLE_SHIFT) +#define CP_DEBUG_SET_SIMPLE_ME_FLOW_CONTROL(cp_debug_reg, simple_me_flow_control) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_MASK) | (simple_me_flow_control << CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SHIFT) +#define CP_DEBUG_SET_MIU_WRITE_PACK_DISABLE(cp_debug_reg, miu_write_pack_disable) \ + cp_debug_reg = (cp_debug_reg & ~CP_DEBUG_MIU_WRITE_PACK_DISABLE_MASK) | (miu_write_pack_disable << CP_DEBUG_MIU_WRITE_PACK_DISABLE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_debug_t { + unsigned int cp_debug_unused_22_to_0 : CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE; + unsigned int predicate_disable : CP_DEBUG_PREDICATE_DISABLE_SIZE; + unsigned int prog_end_ptr_enable : CP_DEBUG_PROG_END_PTR_ENABLE_SIZE; + unsigned int miu_128bit_write_enable : CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE; + unsigned int prefetch_pass_nops : CP_DEBUG_PREFETCH_PASS_NOPS_SIZE; + unsigned int dynamic_clk_disable : CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE; + unsigned int prefetch_match_disable : CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE; + unsigned int : 1; + unsigned int simple_me_flow_control : CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE; + unsigned int miu_write_pack_disable : CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE; + } cp_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_debug_t { + unsigned int miu_write_pack_disable : CP_DEBUG_MIU_WRITE_PACK_DISABLE_SIZE; + unsigned int simple_me_flow_control : CP_DEBUG_SIMPLE_ME_FLOW_CONTROL_SIZE; + unsigned int : 1; + unsigned int prefetch_match_disable : CP_DEBUG_PREFETCH_MATCH_DISABLE_SIZE; + unsigned int dynamic_clk_disable : CP_DEBUG_DYNAMIC_CLK_DISABLE_SIZE; + unsigned int prefetch_pass_nops : CP_DEBUG_PREFETCH_PASS_NOPS_SIZE; + unsigned int miu_128bit_write_enable : CP_DEBUG_MIU_128BIT_WRITE_ENABLE_SIZE; + unsigned int prog_end_ptr_enable : CP_DEBUG_PROG_END_PTR_ENABLE_SIZE; + unsigned int predicate_disable : CP_DEBUG_PREDICATE_DISABLE_SIZE; + unsigned int cp_debug_unused_22_to_0 : CP_DEBUG_CP_DEBUG_UNUSED_22_to_0_SIZE; + } cp_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_debug_t f; +} cp_debug_u; + + +/* + * SCRATCH_REG0 struct + */ + +#define SCRATCH_REG0_SCRATCH_REG0_SIZE 32 + +#define SCRATCH_REG0_SCRATCH_REG0_SHIFT 0 + +#define SCRATCH_REG0_SCRATCH_REG0_MASK 0xffffffff + +#define SCRATCH_REG0_MASK \ + (SCRATCH_REG0_SCRATCH_REG0_MASK) + +#define SCRATCH_REG0(scratch_reg0) \ + ((scratch_reg0 << SCRATCH_REG0_SCRATCH_REG0_SHIFT)) + +#define SCRATCH_REG0_GET_SCRATCH_REG0(scratch_reg0) \ + ((scratch_reg0 & SCRATCH_REG0_SCRATCH_REG0_MASK) >> SCRATCH_REG0_SCRATCH_REG0_SHIFT) + +#define SCRATCH_REG0_SET_SCRATCH_REG0(scratch_reg0_reg, scratch_reg0) \ + scratch_reg0_reg = (scratch_reg0_reg & ~SCRATCH_REG0_SCRATCH_REG0_MASK) | (scratch_reg0 << SCRATCH_REG0_SCRATCH_REG0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg0_t { + unsigned int scratch_reg0 : SCRATCH_REG0_SCRATCH_REG0_SIZE; + } scratch_reg0_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg0_t { + unsigned int scratch_reg0 : SCRATCH_REG0_SCRATCH_REG0_SIZE; + } scratch_reg0_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg0_t f; +} scratch_reg0_u; + + +/* + * SCRATCH_REG1 struct + */ + +#define SCRATCH_REG1_SCRATCH_REG1_SIZE 32 + +#define SCRATCH_REG1_SCRATCH_REG1_SHIFT 0 + +#define SCRATCH_REG1_SCRATCH_REG1_MASK 0xffffffff + +#define SCRATCH_REG1_MASK \ + (SCRATCH_REG1_SCRATCH_REG1_MASK) + +#define SCRATCH_REG1(scratch_reg1) \ + ((scratch_reg1 << SCRATCH_REG1_SCRATCH_REG1_SHIFT)) + +#define SCRATCH_REG1_GET_SCRATCH_REG1(scratch_reg1) \ + ((scratch_reg1 & SCRATCH_REG1_SCRATCH_REG1_MASK) >> SCRATCH_REG1_SCRATCH_REG1_SHIFT) + +#define SCRATCH_REG1_SET_SCRATCH_REG1(scratch_reg1_reg, scratch_reg1) \ + scratch_reg1_reg = (scratch_reg1_reg & ~SCRATCH_REG1_SCRATCH_REG1_MASK) | (scratch_reg1 << SCRATCH_REG1_SCRATCH_REG1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg1_t { + unsigned int scratch_reg1 : SCRATCH_REG1_SCRATCH_REG1_SIZE; + } scratch_reg1_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg1_t { + unsigned int scratch_reg1 : SCRATCH_REG1_SCRATCH_REG1_SIZE; + } scratch_reg1_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg1_t f; +} scratch_reg1_u; + + +/* + * SCRATCH_REG2 struct + */ + +#define SCRATCH_REG2_SCRATCH_REG2_SIZE 32 + +#define SCRATCH_REG2_SCRATCH_REG2_SHIFT 0 + +#define SCRATCH_REG2_SCRATCH_REG2_MASK 0xffffffff + +#define SCRATCH_REG2_MASK \ + (SCRATCH_REG2_SCRATCH_REG2_MASK) + +#define SCRATCH_REG2(scratch_reg2) \ + ((scratch_reg2 << SCRATCH_REG2_SCRATCH_REG2_SHIFT)) + +#define SCRATCH_REG2_GET_SCRATCH_REG2(scratch_reg2) \ + ((scratch_reg2 & SCRATCH_REG2_SCRATCH_REG2_MASK) >> SCRATCH_REG2_SCRATCH_REG2_SHIFT) + +#define SCRATCH_REG2_SET_SCRATCH_REG2(scratch_reg2_reg, scratch_reg2) \ + scratch_reg2_reg = (scratch_reg2_reg & ~SCRATCH_REG2_SCRATCH_REG2_MASK) | (scratch_reg2 << SCRATCH_REG2_SCRATCH_REG2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg2_t { + unsigned int scratch_reg2 : SCRATCH_REG2_SCRATCH_REG2_SIZE; + } scratch_reg2_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg2_t { + unsigned int scratch_reg2 : SCRATCH_REG2_SCRATCH_REG2_SIZE; + } scratch_reg2_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg2_t f; +} scratch_reg2_u; + + +/* + * SCRATCH_REG3 struct + */ + +#define SCRATCH_REG3_SCRATCH_REG3_SIZE 32 + +#define SCRATCH_REG3_SCRATCH_REG3_SHIFT 0 + +#define SCRATCH_REG3_SCRATCH_REG3_MASK 0xffffffff + +#define SCRATCH_REG3_MASK \ + (SCRATCH_REG3_SCRATCH_REG3_MASK) + +#define SCRATCH_REG3(scratch_reg3) \ + ((scratch_reg3 << SCRATCH_REG3_SCRATCH_REG3_SHIFT)) + +#define SCRATCH_REG3_GET_SCRATCH_REG3(scratch_reg3) \ + ((scratch_reg3 & SCRATCH_REG3_SCRATCH_REG3_MASK) >> SCRATCH_REG3_SCRATCH_REG3_SHIFT) + +#define SCRATCH_REG3_SET_SCRATCH_REG3(scratch_reg3_reg, scratch_reg3) \ + scratch_reg3_reg = (scratch_reg3_reg & ~SCRATCH_REG3_SCRATCH_REG3_MASK) | (scratch_reg3 << SCRATCH_REG3_SCRATCH_REG3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg3_t { + unsigned int scratch_reg3 : SCRATCH_REG3_SCRATCH_REG3_SIZE; + } scratch_reg3_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg3_t { + unsigned int scratch_reg3 : SCRATCH_REG3_SCRATCH_REG3_SIZE; + } scratch_reg3_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg3_t f; +} scratch_reg3_u; + + +/* + * SCRATCH_REG4 struct + */ + +#define SCRATCH_REG4_SCRATCH_REG4_SIZE 32 + +#define SCRATCH_REG4_SCRATCH_REG4_SHIFT 0 + +#define SCRATCH_REG4_SCRATCH_REG4_MASK 0xffffffff + +#define SCRATCH_REG4_MASK \ + (SCRATCH_REG4_SCRATCH_REG4_MASK) + +#define SCRATCH_REG4(scratch_reg4) \ + ((scratch_reg4 << SCRATCH_REG4_SCRATCH_REG4_SHIFT)) + +#define SCRATCH_REG4_GET_SCRATCH_REG4(scratch_reg4) \ + ((scratch_reg4 & SCRATCH_REG4_SCRATCH_REG4_MASK) >> SCRATCH_REG4_SCRATCH_REG4_SHIFT) + +#define SCRATCH_REG4_SET_SCRATCH_REG4(scratch_reg4_reg, scratch_reg4) \ + scratch_reg4_reg = (scratch_reg4_reg & ~SCRATCH_REG4_SCRATCH_REG4_MASK) | (scratch_reg4 << SCRATCH_REG4_SCRATCH_REG4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg4_t { + unsigned int scratch_reg4 : SCRATCH_REG4_SCRATCH_REG4_SIZE; + } scratch_reg4_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg4_t { + unsigned int scratch_reg4 : SCRATCH_REG4_SCRATCH_REG4_SIZE; + } scratch_reg4_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg4_t f; +} scratch_reg4_u; + + +/* + * SCRATCH_REG5 struct + */ + +#define SCRATCH_REG5_SCRATCH_REG5_SIZE 32 + +#define SCRATCH_REG5_SCRATCH_REG5_SHIFT 0 + +#define SCRATCH_REG5_SCRATCH_REG5_MASK 0xffffffff + +#define SCRATCH_REG5_MASK \ + (SCRATCH_REG5_SCRATCH_REG5_MASK) + +#define SCRATCH_REG5(scratch_reg5) \ + ((scratch_reg5 << SCRATCH_REG5_SCRATCH_REG5_SHIFT)) + +#define SCRATCH_REG5_GET_SCRATCH_REG5(scratch_reg5) \ + ((scratch_reg5 & SCRATCH_REG5_SCRATCH_REG5_MASK) >> SCRATCH_REG5_SCRATCH_REG5_SHIFT) + +#define SCRATCH_REG5_SET_SCRATCH_REG5(scratch_reg5_reg, scratch_reg5) \ + scratch_reg5_reg = (scratch_reg5_reg & ~SCRATCH_REG5_SCRATCH_REG5_MASK) | (scratch_reg5 << SCRATCH_REG5_SCRATCH_REG5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg5_t { + unsigned int scratch_reg5 : SCRATCH_REG5_SCRATCH_REG5_SIZE; + } scratch_reg5_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg5_t { + unsigned int scratch_reg5 : SCRATCH_REG5_SCRATCH_REG5_SIZE; + } scratch_reg5_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg5_t f; +} scratch_reg5_u; + + +/* + * SCRATCH_REG6 struct + */ + +#define SCRATCH_REG6_SCRATCH_REG6_SIZE 32 + +#define SCRATCH_REG6_SCRATCH_REG6_SHIFT 0 + +#define SCRATCH_REG6_SCRATCH_REG6_MASK 0xffffffff + +#define SCRATCH_REG6_MASK \ + (SCRATCH_REG6_SCRATCH_REG6_MASK) + +#define SCRATCH_REG6(scratch_reg6) \ + ((scratch_reg6 << SCRATCH_REG6_SCRATCH_REG6_SHIFT)) + +#define SCRATCH_REG6_GET_SCRATCH_REG6(scratch_reg6) \ + ((scratch_reg6 & SCRATCH_REG6_SCRATCH_REG6_MASK) >> SCRATCH_REG6_SCRATCH_REG6_SHIFT) + +#define SCRATCH_REG6_SET_SCRATCH_REG6(scratch_reg6_reg, scratch_reg6) \ + scratch_reg6_reg = (scratch_reg6_reg & ~SCRATCH_REG6_SCRATCH_REG6_MASK) | (scratch_reg6 << SCRATCH_REG6_SCRATCH_REG6_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg6_t { + unsigned int scratch_reg6 : SCRATCH_REG6_SCRATCH_REG6_SIZE; + } scratch_reg6_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg6_t { + unsigned int scratch_reg6 : SCRATCH_REG6_SCRATCH_REG6_SIZE; + } scratch_reg6_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg6_t f; +} scratch_reg6_u; + + +/* + * SCRATCH_REG7 struct + */ + +#define SCRATCH_REG7_SCRATCH_REG7_SIZE 32 + +#define SCRATCH_REG7_SCRATCH_REG7_SHIFT 0 + +#define SCRATCH_REG7_SCRATCH_REG7_MASK 0xffffffff + +#define SCRATCH_REG7_MASK \ + (SCRATCH_REG7_SCRATCH_REG7_MASK) + +#define SCRATCH_REG7(scratch_reg7) \ + ((scratch_reg7 << SCRATCH_REG7_SCRATCH_REG7_SHIFT)) + +#define SCRATCH_REG7_GET_SCRATCH_REG7(scratch_reg7) \ + ((scratch_reg7 & SCRATCH_REG7_SCRATCH_REG7_MASK) >> SCRATCH_REG7_SCRATCH_REG7_SHIFT) + +#define SCRATCH_REG7_SET_SCRATCH_REG7(scratch_reg7_reg, scratch_reg7) \ + scratch_reg7_reg = (scratch_reg7_reg & ~SCRATCH_REG7_SCRATCH_REG7_MASK) | (scratch_reg7 << SCRATCH_REG7_SCRATCH_REG7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_reg7_t { + unsigned int scratch_reg7 : SCRATCH_REG7_SCRATCH_REG7_SIZE; + } scratch_reg7_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_reg7_t { + unsigned int scratch_reg7 : SCRATCH_REG7_SCRATCH_REG7_SIZE; + } scratch_reg7_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_reg7_t f; +} scratch_reg7_u; + + +/* + * SCRATCH_UMSK struct + */ + +#define SCRATCH_UMSK_SCRATCH_UMSK_SIZE 8 +#define SCRATCH_UMSK_SCRATCH_SWAP_SIZE 2 + +#define SCRATCH_UMSK_SCRATCH_UMSK_SHIFT 0 +#define SCRATCH_UMSK_SCRATCH_SWAP_SHIFT 16 + +#define SCRATCH_UMSK_SCRATCH_UMSK_MASK 0x000000ff +#define SCRATCH_UMSK_SCRATCH_SWAP_MASK 0x00030000 + +#define SCRATCH_UMSK_MASK \ + (SCRATCH_UMSK_SCRATCH_UMSK_MASK | \ + SCRATCH_UMSK_SCRATCH_SWAP_MASK) + +#define SCRATCH_UMSK(scratch_umsk, scratch_swap) \ + ((scratch_umsk << SCRATCH_UMSK_SCRATCH_UMSK_SHIFT) | \ + (scratch_swap << SCRATCH_UMSK_SCRATCH_SWAP_SHIFT)) + +#define SCRATCH_UMSK_GET_SCRATCH_UMSK(scratch_umsk) \ + ((scratch_umsk & SCRATCH_UMSK_SCRATCH_UMSK_MASK) >> SCRATCH_UMSK_SCRATCH_UMSK_SHIFT) +#define SCRATCH_UMSK_GET_SCRATCH_SWAP(scratch_umsk) \ + ((scratch_umsk & SCRATCH_UMSK_SCRATCH_SWAP_MASK) >> SCRATCH_UMSK_SCRATCH_SWAP_SHIFT) + +#define SCRATCH_UMSK_SET_SCRATCH_UMSK(scratch_umsk_reg, scratch_umsk) \ + scratch_umsk_reg = (scratch_umsk_reg & ~SCRATCH_UMSK_SCRATCH_UMSK_MASK) | (scratch_umsk << SCRATCH_UMSK_SCRATCH_UMSK_SHIFT) +#define SCRATCH_UMSK_SET_SCRATCH_SWAP(scratch_umsk_reg, scratch_swap) \ + scratch_umsk_reg = (scratch_umsk_reg & ~SCRATCH_UMSK_SCRATCH_SWAP_MASK) | (scratch_swap << SCRATCH_UMSK_SCRATCH_SWAP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_umsk_t { + unsigned int scratch_umsk : SCRATCH_UMSK_SCRATCH_UMSK_SIZE; + unsigned int : 8; + unsigned int scratch_swap : SCRATCH_UMSK_SCRATCH_SWAP_SIZE; + unsigned int : 14; + } scratch_umsk_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_umsk_t { + unsigned int : 14; + unsigned int scratch_swap : SCRATCH_UMSK_SCRATCH_SWAP_SIZE; + unsigned int : 8; + unsigned int scratch_umsk : SCRATCH_UMSK_SCRATCH_UMSK_SIZE; + } scratch_umsk_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_umsk_t f; +} scratch_umsk_u; + + +/* + * SCRATCH_ADDR struct + */ + +#define SCRATCH_ADDR_SCRATCH_ADDR_SIZE 27 + +#define SCRATCH_ADDR_SCRATCH_ADDR_SHIFT 5 + +#define SCRATCH_ADDR_SCRATCH_ADDR_MASK 0xffffffe0 + +#define SCRATCH_ADDR_MASK \ + (SCRATCH_ADDR_SCRATCH_ADDR_MASK) + +#define SCRATCH_ADDR(scratch_addr) \ + ((scratch_addr << SCRATCH_ADDR_SCRATCH_ADDR_SHIFT)) + +#define SCRATCH_ADDR_GET_SCRATCH_ADDR(scratch_addr) \ + ((scratch_addr & SCRATCH_ADDR_SCRATCH_ADDR_MASK) >> SCRATCH_ADDR_SCRATCH_ADDR_SHIFT) + +#define SCRATCH_ADDR_SET_SCRATCH_ADDR(scratch_addr_reg, scratch_addr) \ + scratch_addr_reg = (scratch_addr_reg & ~SCRATCH_ADDR_SCRATCH_ADDR_MASK) | (scratch_addr << SCRATCH_ADDR_SCRATCH_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _scratch_addr_t { + unsigned int : 5; + unsigned int scratch_addr : SCRATCH_ADDR_SCRATCH_ADDR_SIZE; + } scratch_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _scratch_addr_t { + unsigned int scratch_addr : SCRATCH_ADDR_SCRATCH_ADDR_SIZE; + unsigned int : 5; + } scratch_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + scratch_addr_t f; +} scratch_addr_u; + + +/* + * CP_ME_VS_EVENT_SRC struct + */ + +#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE 1 +#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE 1 + +#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT 0 +#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT 1 + +#define CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK 0x00000001 +#define CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK 0x00000002 + +#define CP_ME_VS_EVENT_SRC_MASK \ + (CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK | \ + CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) + +#define CP_ME_VS_EVENT_SRC(vs_done_swm, vs_done_cntr) \ + ((vs_done_swm << CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT) | \ + (vs_done_cntr << CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT)) + +#define CP_ME_VS_EVENT_SRC_GET_VS_DONE_SWM(cp_me_vs_event_src) \ + ((cp_me_vs_event_src & CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK) >> CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT) +#define CP_ME_VS_EVENT_SRC_GET_VS_DONE_CNTR(cp_me_vs_event_src) \ + ((cp_me_vs_event_src & CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) >> CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT) + +#define CP_ME_VS_EVENT_SRC_SET_VS_DONE_SWM(cp_me_vs_event_src_reg, vs_done_swm) \ + cp_me_vs_event_src_reg = (cp_me_vs_event_src_reg & ~CP_ME_VS_EVENT_SRC_VS_DONE_SWM_MASK) | (vs_done_swm << CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SHIFT) +#define CP_ME_VS_EVENT_SRC_SET_VS_DONE_CNTR(cp_me_vs_event_src_reg, vs_done_cntr) \ + cp_me_vs_event_src_reg = (cp_me_vs_event_src_reg & ~CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_MASK) | (vs_done_cntr << CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_src_t { + unsigned int vs_done_swm : CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE; + unsigned int vs_done_cntr : CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE; + unsigned int : 30; + } cp_me_vs_event_src_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_src_t { + unsigned int : 30; + unsigned int vs_done_cntr : CP_ME_VS_EVENT_SRC_VS_DONE_CNTR_SIZE; + unsigned int vs_done_swm : CP_ME_VS_EVENT_SRC_VS_DONE_SWM_SIZE; + } cp_me_vs_event_src_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_src_t f; +} cp_me_vs_event_src_u; + + +/* + * CP_ME_VS_EVENT_ADDR struct + */ + +#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE 2 +#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE 30 + +#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT 0 +#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT 2 + +#define CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK 0x00000003 +#define CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK 0xfffffffc + +#define CP_ME_VS_EVENT_ADDR_MASK \ + (CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK | \ + CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) + +#define CP_ME_VS_EVENT_ADDR(vs_done_swap, vs_done_addr) \ + ((vs_done_swap << CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT) | \ + (vs_done_addr << CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT)) + +#define CP_ME_VS_EVENT_ADDR_GET_VS_DONE_SWAP(cp_me_vs_event_addr) \ + ((cp_me_vs_event_addr & CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK) >> CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT) +#define CP_ME_VS_EVENT_ADDR_GET_VS_DONE_ADDR(cp_me_vs_event_addr) \ + ((cp_me_vs_event_addr & CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) >> CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT) + +#define CP_ME_VS_EVENT_ADDR_SET_VS_DONE_SWAP(cp_me_vs_event_addr_reg, vs_done_swap) \ + cp_me_vs_event_addr_reg = (cp_me_vs_event_addr_reg & ~CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_MASK) | (vs_done_swap << CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SHIFT) +#define CP_ME_VS_EVENT_ADDR_SET_VS_DONE_ADDR(cp_me_vs_event_addr_reg, vs_done_addr) \ + cp_me_vs_event_addr_reg = (cp_me_vs_event_addr_reg & ~CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_MASK) | (vs_done_addr << CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_addr_t { + unsigned int vs_done_swap : CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE; + unsigned int vs_done_addr : CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE; + } cp_me_vs_event_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_addr_t { + unsigned int vs_done_addr : CP_ME_VS_EVENT_ADDR_VS_DONE_ADDR_SIZE; + unsigned int vs_done_swap : CP_ME_VS_EVENT_ADDR_VS_DONE_SWAP_SIZE; + } cp_me_vs_event_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_addr_t f; +} cp_me_vs_event_addr_u; + + +/* + * CP_ME_VS_EVENT_DATA struct + */ + +#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE 32 + +#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT 0 + +#define CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK 0xffffffff + +#define CP_ME_VS_EVENT_DATA_MASK \ + (CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) + +#define CP_ME_VS_EVENT_DATA(vs_done_data) \ + ((vs_done_data << CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT)) + +#define CP_ME_VS_EVENT_DATA_GET_VS_DONE_DATA(cp_me_vs_event_data) \ + ((cp_me_vs_event_data & CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) >> CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT) + +#define CP_ME_VS_EVENT_DATA_SET_VS_DONE_DATA(cp_me_vs_event_data_reg, vs_done_data) \ + cp_me_vs_event_data_reg = (cp_me_vs_event_data_reg & ~CP_ME_VS_EVENT_DATA_VS_DONE_DATA_MASK) | (vs_done_data << CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_data_t { + unsigned int vs_done_data : CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE; + } cp_me_vs_event_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_data_t { + unsigned int vs_done_data : CP_ME_VS_EVENT_DATA_VS_DONE_DATA_SIZE; + } cp_me_vs_event_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_data_t f; +} cp_me_vs_event_data_u; + + +/* + * CP_ME_VS_EVENT_ADDR_SWM struct + */ + +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE 2 +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE 30 + +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT 0 +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT 2 + +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK 0x00000003 +#define CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK 0xfffffffc + +#define CP_ME_VS_EVENT_ADDR_SWM_MASK \ + (CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK | \ + CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) + +#define CP_ME_VS_EVENT_ADDR_SWM(vs_done_swap_swm, vs_done_addr_swm) \ + ((vs_done_swap_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT) | \ + (vs_done_addr_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT)) + +#define CP_ME_VS_EVENT_ADDR_SWM_GET_VS_DONE_SWAP_SWM(cp_me_vs_event_addr_swm) \ + ((cp_me_vs_event_addr_swm & CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK) >> CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT) +#define CP_ME_VS_EVENT_ADDR_SWM_GET_VS_DONE_ADDR_SWM(cp_me_vs_event_addr_swm) \ + ((cp_me_vs_event_addr_swm & CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) >> CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT) + +#define CP_ME_VS_EVENT_ADDR_SWM_SET_VS_DONE_SWAP_SWM(cp_me_vs_event_addr_swm_reg, vs_done_swap_swm) \ + cp_me_vs_event_addr_swm_reg = (cp_me_vs_event_addr_swm_reg & ~CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_MASK) | (vs_done_swap_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SHIFT) +#define CP_ME_VS_EVENT_ADDR_SWM_SET_VS_DONE_ADDR_SWM(cp_me_vs_event_addr_swm_reg, vs_done_addr_swm) \ + cp_me_vs_event_addr_swm_reg = (cp_me_vs_event_addr_swm_reg & ~CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_MASK) | (vs_done_addr_swm << CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_addr_swm_t { + unsigned int vs_done_swap_swm : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE; + unsigned int vs_done_addr_swm : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE; + } cp_me_vs_event_addr_swm_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_addr_swm_t { + unsigned int vs_done_addr_swm : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_ADDR_SWM_SIZE; + unsigned int vs_done_swap_swm : CP_ME_VS_EVENT_ADDR_SWM_VS_DONE_SWAP_SWM_SIZE; + } cp_me_vs_event_addr_swm_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_addr_swm_t f; +} cp_me_vs_event_addr_swm_u; + + +/* + * CP_ME_VS_EVENT_DATA_SWM struct + */ + +#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE 32 + +#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT 0 + +#define CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK 0xffffffff + +#define CP_ME_VS_EVENT_DATA_SWM_MASK \ + (CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) + +#define CP_ME_VS_EVENT_DATA_SWM(vs_done_data_swm) \ + ((vs_done_data_swm << CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT)) + +#define CP_ME_VS_EVENT_DATA_SWM_GET_VS_DONE_DATA_SWM(cp_me_vs_event_data_swm) \ + ((cp_me_vs_event_data_swm & CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) >> CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT) + +#define CP_ME_VS_EVENT_DATA_SWM_SET_VS_DONE_DATA_SWM(cp_me_vs_event_data_swm_reg, vs_done_data_swm) \ + cp_me_vs_event_data_swm_reg = (cp_me_vs_event_data_swm_reg & ~CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_MASK) | (vs_done_data_swm << CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_event_data_swm_t { + unsigned int vs_done_data_swm : CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE; + } cp_me_vs_event_data_swm_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_event_data_swm_t { + unsigned int vs_done_data_swm : CP_ME_VS_EVENT_DATA_SWM_VS_DONE_DATA_SWM_SIZE; + } cp_me_vs_event_data_swm_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_event_data_swm_t f; +} cp_me_vs_event_data_swm_u; + + +/* + * CP_ME_PS_EVENT_SRC struct + */ + +#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE 1 +#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE 1 + +#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT 0 +#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT 1 + +#define CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK 0x00000001 +#define CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK 0x00000002 + +#define CP_ME_PS_EVENT_SRC_MASK \ + (CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK | \ + CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) + +#define CP_ME_PS_EVENT_SRC(ps_done_swm, ps_done_cntr) \ + ((ps_done_swm << CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT) | \ + (ps_done_cntr << CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT)) + +#define CP_ME_PS_EVENT_SRC_GET_PS_DONE_SWM(cp_me_ps_event_src) \ + ((cp_me_ps_event_src & CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK) >> CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT) +#define CP_ME_PS_EVENT_SRC_GET_PS_DONE_CNTR(cp_me_ps_event_src) \ + ((cp_me_ps_event_src & CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) >> CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT) + +#define CP_ME_PS_EVENT_SRC_SET_PS_DONE_SWM(cp_me_ps_event_src_reg, ps_done_swm) \ + cp_me_ps_event_src_reg = (cp_me_ps_event_src_reg & ~CP_ME_PS_EVENT_SRC_PS_DONE_SWM_MASK) | (ps_done_swm << CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SHIFT) +#define CP_ME_PS_EVENT_SRC_SET_PS_DONE_CNTR(cp_me_ps_event_src_reg, ps_done_cntr) \ + cp_me_ps_event_src_reg = (cp_me_ps_event_src_reg & ~CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_MASK) | (ps_done_cntr << CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_src_t { + unsigned int ps_done_swm : CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE; + unsigned int ps_done_cntr : CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE; + unsigned int : 30; + } cp_me_ps_event_src_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_src_t { + unsigned int : 30; + unsigned int ps_done_cntr : CP_ME_PS_EVENT_SRC_PS_DONE_CNTR_SIZE; + unsigned int ps_done_swm : CP_ME_PS_EVENT_SRC_PS_DONE_SWM_SIZE; + } cp_me_ps_event_src_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_src_t f; +} cp_me_ps_event_src_u; + + +/* + * CP_ME_PS_EVENT_ADDR struct + */ + +#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE 2 +#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE 30 + +#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT 0 +#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT 2 + +#define CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK 0x00000003 +#define CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK 0xfffffffc + +#define CP_ME_PS_EVENT_ADDR_MASK \ + (CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK | \ + CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) + +#define CP_ME_PS_EVENT_ADDR(ps_done_swap, ps_done_addr) \ + ((ps_done_swap << CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT) | \ + (ps_done_addr << CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT)) + +#define CP_ME_PS_EVENT_ADDR_GET_PS_DONE_SWAP(cp_me_ps_event_addr) \ + ((cp_me_ps_event_addr & CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK) >> CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT) +#define CP_ME_PS_EVENT_ADDR_GET_PS_DONE_ADDR(cp_me_ps_event_addr) \ + ((cp_me_ps_event_addr & CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) >> CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT) + +#define CP_ME_PS_EVENT_ADDR_SET_PS_DONE_SWAP(cp_me_ps_event_addr_reg, ps_done_swap) \ + cp_me_ps_event_addr_reg = (cp_me_ps_event_addr_reg & ~CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_MASK) | (ps_done_swap << CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SHIFT) +#define CP_ME_PS_EVENT_ADDR_SET_PS_DONE_ADDR(cp_me_ps_event_addr_reg, ps_done_addr) \ + cp_me_ps_event_addr_reg = (cp_me_ps_event_addr_reg & ~CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_MASK) | (ps_done_addr << CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_addr_t { + unsigned int ps_done_swap : CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE; + unsigned int ps_done_addr : CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE; + } cp_me_ps_event_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_addr_t { + unsigned int ps_done_addr : CP_ME_PS_EVENT_ADDR_PS_DONE_ADDR_SIZE; + unsigned int ps_done_swap : CP_ME_PS_EVENT_ADDR_PS_DONE_SWAP_SIZE; + } cp_me_ps_event_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_addr_t f; +} cp_me_ps_event_addr_u; + + +/* + * CP_ME_PS_EVENT_DATA struct + */ + +#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE 32 + +#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT 0 + +#define CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK 0xffffffff + +#define CP_ME_PS_EVENT_DATA_MASK \ + (CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) + +#define CP_ME_PS_EVENT_DATA(ps_done_data) \ + ((ps_done_data << CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT)) + +#define CP_ME_PS_EVENT_DATA_GET_PS_DONE_DATA(cp_me_ps_event_data) \ + ((cp_me_ps_event_data & CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) >> CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT) + +#define CP_ME_PS_EVENT_DATA_SET_PS_DONE_DATA(cp_me_ps_event_data_reg, ps_done_data) \ + cp_me_ps_event_data_reg = (cp_me_ps_event_data_reg & ~CP_ME_PS_EVENT_DATA_PS_DONE_DATA_MASK) | (ps_done_data << CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_data_t { + unsigned int ps_done_data : CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE; + } cp_me_ps_event_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_data_t { + unsigned int ps_done_data : CP_ME_PS_EVENT_DATA_PS_DONE_DATA_SIZE; + } cp_me_ps_event_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_data_t f; +} cp_me_ps_event_data_u; + + +/* + * CP_ME_PS_EVENT_ADDR_SWM struct + */ + +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE 2 +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE 30 + +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT 0 +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT 2 + +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK 0x00000003 +#define CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK 0xfffffffc + +#define CP_ME_PS_EVENT_ADDR_SWM_MASK \ + (CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK | \ + CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) + +#define CP_ME_PS_EVENT_ADDR_SWM(ps_done_swap_swm, ps_done_addr_swm) \ + ((ps_done_swap_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT) | \ + (ps_done_addr_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT)) + +#define CP_ME_PS_EVENT_ADDR_SWM_GET_PS_DONE_SWAP_SWM(cp_me_ps_event_addr_swm) \ + ((cp_me_ps_event_addr_swm & CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK) >> CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT) +#define CP_ME_PS_EVENT_ADDR_SWM_GET_PS_DONE_ADDR_SWM(cp_me_ps_event_addr_swm) \ + ((cp_me_ps_event_addr_swm & CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) >> CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT) + +#define CP_ME_PS_EVENT_ADDR_SWM_SET_PS_DONE_SWAP_SWM(cp_me_ps_event_addr_swm_reg, ps_done_swap_swm) \ + cp_me_ps_event_addr_swm_reg = (cp_me_ps_event_addr_swm_reg & ~CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_MASK) | (ps_done_swap_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SHIFT) +#define CP_ME_PS_EVENT_ADDR_SWM_SET_PS_DONE_ADDR_SWM(cp_me_ps_event_addr_swm_reg, ps_done_addr_swm) \ + cp_me_ps_event_addr_swm_reg = (cp_me_ps_event_addr_swm_reg & ~CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_MASK) | (ps_done_addr_swm << CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_addr_swm_t { + unsigned int ps_done_swap_swm : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE; + unsigned int ps_done_addr_swm : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE; + } cp_me_ps_event_addr_swm_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_addr_swm_t { + unsigned int ps_done_addr_swm : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_ADDR_SWM_SIZE; + unsigned int ps_done_swap_swm : CP_ME_PS_EVENT_ADDR_SWM_PS_DONE_SWAP_SWM_SIZE; + } cp_me_ps_event_addr_swm_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_addr_swm_t f; +} cp_me_ps_event_addr_swm_u; + + +/* + * CP_ME_PS_EVENT_DATA_SWM struct + */ + +#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE 32 + +#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT 0 + +#define CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK 0xffffffff + +#define CP_ME_PS_EVENT_DATA_SWM_MASK \ + (CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) + +#define CP_ME_PS_EVENT_DATA_SWM(ps_done_data_swm) \ + ((ps_done_data_swm << CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT)) + +#define CP_ME_PS_EVENT_DATA_SWM_GET_PS_DONE_DATA_SWM(cp_me_ps_event_data_swm) \ + ((cp_me_ps_event_data_swm & CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) >> CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT) + +#define CP_ME_PS_EVENT_DATA_SWM_SET_PS_DONE_DATA_SWM(cp_me_ps_event_data_swm_reg, ps_done_data_swm) \ + cp_me_ps_event_data_swm_reg = (cp_me_ps_event_data_swm_reg & ~CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_MASK) | (ps_done_data_swm << CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_ps_event_data_swm_t { + unsigned int ps_done_data_swm : CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE; + } cp_me_ps_event_data_swm_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_ps_event_data_swm_t { + unsigned int ps_done_data_swm : CP_ME_PS_EVENT_DATA_SWM_PS_DONE_DATA_SWM_SIZE; + } cp_me_ps_event_data_swm_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_ps_event_data_swm_t f; +} cp_me_ps_event_data_swm_u; + + +/* + * CP_ME_CF_EVENT_SRC struct + */ + +#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE 1 + +#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT 0 + +#define CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK 0x00000001 + +#define CP_ME_CF_EVENT_SRC_MASK \ + (CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) + +#define CP_ME_CF_EVENT_SRC(cf_done_src) \ + ((cf_done_src << CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT)) + +#define CP_ME_CF_EVENT_SRC_GET_CF_DONE_SRC(cp_me_cf_event_src) \ + ((cp_me_cf_event_src & CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) >> CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT) + +#define CP_ME_CF_EVENT_SRC_SET_CF_DONE_SRC(cp_me_cf_event_src_reg, cf_done_src) \ + cp_me_cf_event_src_reg = (cp_me_cf_event_src_reg & ~CP_ME_CF_EVENT_SRC_CF_DONE_SRC_MASK) | (cf_done_src << CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_cf_event_src_t { + unsigned int cf_done_src : CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE; + unsigned int : 31; + } cp_me_cf_event_src_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_cf_event_src_t { + unsigned int : 31; + unsigned int cf_done_src : CP_ME_CF_EVENT_SRC_CF_DONE_SRC_SIZE; + } cp_me_cf_event_src_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_cf_event_src_t f; +} cp_me_cf_event_src_u; + + +/* + * CP_ME_CF_EVENT_ADDR struct + */ + +#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE 2 +#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE 30 + +#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT 0 +#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT 2 + +#define CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK 0x00000003 +#define CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK 0xfffffffc + +#define CP_ME_CF_EVENT_ADDR_MASK \ + (CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK | \ + CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) + +#define CP_ME_CF_EVENT_ADDR(cf_done_swap, cf_done_addr) \ + ((cf_done_swap << CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT) | \ + (cf_done_addr << CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT)) + +#define CP_ME_CF_EVENT_ADDR_GET_CF_DONE_SWAP(cp_me_cf_event_addr) \ + ((cp_me_cf_event_addr & CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK) >> CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT) +#define CP_ME_CF_EVENT_ADDR_GET_CF_DONE_ADDR(cp_me_cf_event_addr) \ + ((cp_me_cf_event_addr & CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) >> CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT) + +#define CP_ME_CF_EVENT_ADDR_SET_CF_DONE_SWAP(cp_me_cf_event_addr_reg, cf_done_swap) \ + cp_me_cf_event_addr_reg = (cp_me_cf_event_addr_reg & ~CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_MASK) | (cf_done_swap << CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SHIFT) +#define CP_ME_CF_EVENT_ADDR_SET_CF_DONE_ADDR(cp_me_cf_event_addr_reg, cf_done_addr) \ + cp_me_cf_event_addr_reg = (cp_me_cf_event_addr_reg & ~CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_MASK) | (cf_done_addr << CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_cf_event_addr_t { + unsigned int cf_done_swap : CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE; + unsigned int cf_done_addr : CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE; + } cp_me_cf_event_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_cf_event_addr_t { + unsigned int cf_done_addr : CP_ME_CF_EVENT_ADDR_CF_DONE_ADDR_SIZE; + unsigned int cf_done_swap : CP_ME_CF_EVENT_ADDR_CF_DONE_SWAP_SIZE; + } cp_me_cf_event_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_cf_event_addr_t f; +} cp_me_cf_event_addr_u; + + +/* + * CP_ME_CF_EVENT_DATA struct + */ + +#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE 32 + +#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT 0 + +#define CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK 0xffffffff + +#define CP_ME_CF_EVENT_DATA_MASK \ + (CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) + +#define CP_ME_CF_EVENT_DATA(cf_done_data) \ + ((cf_done_data << CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT)) + +#define CP_ME_CF_EVENT_DATA_GET_CF_DONE_DATA(cp_me_cf_event_data) \ + ((cp_me_cf_event_data & CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) >> CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT) + +#define CP_ME_CF_EVENT_DATA_SET_CF_DONE_DATA(cp_me_cf_event_data_reg, cf_done_data) \ + cp_me_cf_event_data_reg = (cp_me_cf_event_data_reg & ~CP_ME_CF_EVENT_DATA_CF_DONE_DATA_MASK) | (cf_done_data << CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_cf_event_data_t { + unsigned int cf_done_data : CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE; + } cp_me_cf_event_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_cf_event_data_t { + unsigned int cf_done_data : CP_ME_CF_EVENT_DATA_CF_DONE_DATA_SIZE; + } cp_me_cf_event_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_cf_event_data_t f; +} cp_me_cf_event_data_u; + + +/* + * CP_ME_NRT_ADDR struct + */ + +#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE 2 +#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE 30 + +#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT 0 +#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT 2 + +#define CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK 0x00000003 +#define CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK 0xfffffffc + +#define CP_ME_NRT_ADDR_MASK \ + (CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK | \ + CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) + +#define CP_ME_NRT_ADDR(nrt_write_swap, nrt_write_addr) \ + ((nrt_write_swap << CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT) | \ + (nrt_write_addr << CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT)) + +#define CP_ME_NRT_ADDR_GET_NRT_WRITE_SWAP(cp_me_nrt_addr) \ + ((cp_me_nrt_addr & CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK) >> CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT) +#define CP_ME_NRT_ADDR_GET_NRT_WRITE_ADDR(cp_me_nrt_addr) \ + ((cp_me_nrt_addr & CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) >> CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT) + +#define CP_ME_NRT_ADDR_SET_NRT_WRITE_SWAP(cp_me_nrt_addr_reg, nrt_write_swap) \ + cp_me_nrt_addr_reg = (cp_me_nrt_addr_reg & ~CP_ME_NRT_ADDR_NRT_WRITE_SWAP_MASK) | (nrt_write_swap << CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SHIFT) +#define CP_ME_NRT_ADDR_SET_NRT_WRITE_ADDR(cp_me_nrt_addr_reg, nrt_write_addr) \ + cp_me_nrt_addr_reg = (cp_me_nrt_addr_reg & ~CP_ME_NRT_ADDR_NRT_WRITE_ADDR_MASK) | (nrt_write_addr << CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_nrt_addr_t { + unsigned int nrt_write_swap : CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE; + unsigned int nrt_write_addr : CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE; + } cp_me_nrt_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_nrt_addr_t { + unsigned int nrt_write_addr : CP_ME_NRT_ADDR_NRT_WRITE_ADDR_SIZE; + unsigned int nrt_write_swap : CP_ME_NRT_ADDR_NRT_WRITE_SWAP_SIZE; + } cp_me_nrt_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_nrt_addr_t f; +} cp_me_nrt_addr_u; + + +/* + * CP_ME_NRT_DATA struct + */ + +#define CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE 32 + +#define CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT 0 + +#define CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK 0xffffffff + +#define CP_ME_NRT_DATA_MASK \ + (CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) + +#define CP_ME_NRT_DATA(nrt_write_data) \ + ((nrt_write_data << CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT)) + +#define CP_ME_NRT_DATA_GET_NRT_WRITE_DATA(cp_me_nrt_data) \ + ((cp_me_nrt_data & CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) >> CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT) + +#define CP_ME_NRT_DATA_SET_NRT_WRITE_DATA(cp_me_nrt_data_reg, nrt_write_data) \ + cp_me_nrt_data_reg = (cp_me_nrt_data_reg & ~CP_ME_NRT_DATA_NRT_WRITE_DATA_MASK) | (nrt_write_data << CP_ME_NRT_DATA_NRT_WRITE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_nrt_data_t { + unsigned int nrt_write_data : CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE; + } cp_me_nrt_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_nrt_data_t { + unsigned int nrt_write_data : CP_ME_NRT_DATA_NRT_WRITE_DATA_SIZE; + } cp_me_nrt_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_nrt_data_t f; +} cp_me_nrt_data_u; + + +/* + * CP_ME_VS_FETCH_DONE_SRC struct + */ + +#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE 1 + +#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT 0 + +#define CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK 0x00000001 + +#define CP_ME_VS_FETCH_DONE_SRC_MASK \ + (CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) + +#define CP_ME_VS_FETCH_DONE_SRC(vs_fetch_done_cntr) \ + ((vs_fetch_done_cntr << CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT)) + +#define CP_ME_VS_FETCH_DONE_SRC_GET_VS_FETCH_DONE_CNTR(cp_me_vs_fetch_done_src) \ + ((cp_me_vs_fetch_done_src & CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) >> CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT) + +#define CP_ME_VS_FETCH_DONE_SRC_SET_VS_FETCH_DONE_CNTR(cp_me_vs_fetch_done_src_reg, vs_fetch_done_cntr) \ + cp_me_vs_fetch_done_src_reg = (cp_me_vs_fetch_done_src_reg & ~CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_MASK) | (vs_fetch_done_cntr << CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_src_t { + unsigned int vs_fetch_done_cntr : CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE; + unsigned int : 31; + } cp_me_vs_fetch_done_src_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_src_t { + unsigned int : 31; + unsigned int vs_fetch_done_cntr : CP_ME_VS_FETCH_DONE_SRC_VS_FETCH_DONE_CNTR_SIZE; + } cp_me_vs_fetch_done_src_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_fetch_done_src_t f; +} cp_me_vs_fetch_done_src_u; + + +/* + * CP_ME_VS_FETCH_DONE_ADDR struct + */ + +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE 2 +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE 30 + +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT 0 +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT 2 + +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK 0x00000003 +#define CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK 0xfffffffc + +#define CP_ME_VS_FETCH_DONE_ADDR_MASK \ + (CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK | \ + CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) + +#define CP_ME_VS_FETCH_DONE_ADDR(vs_fetch_done_swap, vs_fetch_done_addr) \ + ((vs_fetch_done_swap << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT) | \ + (vs_fetch_done_addr << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT)) + +#define CP_ME_VS_FETCH_DONE_ADDR_GET_VS_FETCH_DONE_SWAP(cp_me_vs_fetch_done_addr) \ + ((cp_me_vs_fetch_done_addr & CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK) >> CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT) +#define CP_ME_VS_FETCH_DONE_ADDR_GET_VS_FETCH_DONE_ADDR(cp_me_vs_fetch_done_addr) \ + ((cp_me_vs_fetch_done_addr & CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) >> CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT) + +#define CP_ME_VS_FETCH_DONE_ADDR_SET_VS_FETCH_DONE_SWAP(cp_me_vs_fetch_done_addr_reg, vs_fetch_done_swap) \ + cp_me_vs_fetch_done_addr_reg = (cp_me_vs_fetch_done_addr_reg & ~CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_MASK) | (vs_fetch_done_swap << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SHIFT) +#define CP_ME_VS_FETCH_DONE_ADDR_SET_VS_FETCH_DONE_ADDR(cp_me_vs_fetch_done_addr_reg, vs_fetch_done_addr) \ + cp_me_vs_fetch_done_addr_reg = (cp_me_vs_fetch_done_addr_reg & ~CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_MASK) | (vs_fetch_done_addr << CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_addr_t { + unsigned int vs_fetch_done_swap : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE; + unsigned int vs_fetch_done_addr : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE; + } cp_me_vs_fetch_done_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_addr_t { + unsigned int vs_fetch_done_addr : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_ADDR_SIZE; + unsigned int vs_fetch_done_swap : CP_ME_VS_FETCH_DONE_ADDR_VS_FETCH_DONE_SWAP_SIZE; + } cp_me_vs_fetch_done_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_fetch_done_addr_t f; +} cp_me_vs_fetch_done_addr_u; + + +/* + * CP_ME_VS_FETCH_DONE_DATA struct + */ + +#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE 32 + +#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT 0 + +#define CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK 0xffffffff + +#define CP_ME_VS_FETCH_DONE_DATA_MASK \ + (CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) + +#define CP_ME_VS_FETCH_DONE_DATA(vs_fetch_done_data) \ + ((vs_fetch_done_data << CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT)) + +#define CP_ME_VS_FETCH_DONE_DATA_GET_VS_FETCH_DONE_DATA(cp_me_vs_fetch_done_data) \ + ((cp_me_vs_fetch_done_data & CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) >> CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT) + +#define CP_ME_VS_FETCH_DONE_DATA_SET_VS_FETCH_DONE_DATA(cp_me_vs_fetch_done_data_reg, vs_fetch_done_data) \ + cp_me_vs_fetch_done_data_reg = (cp_me_vs_fetch_done_data_reg & ~CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_MASK) | (vs_fetch_done_data << CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_data_t { + unsigned int vs_fetch_done_data : CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE; + } cp_me_vs_fetch_done_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_me_vs_fetch_done_data_t { + unsigned int vs_fetch_done_data : CP_ME_VS_FETCH_DONE_DATA_VS_FETCH_DONE_DATA_SIZE; + } cp_me_vs_fetch_done_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_me_vs_fetch_done_data_t f; +} cp_me_vs_fetch_done_data_u; + + +/* + * CP_INT_CNTL struct + */ + +#define CP_INT_CNTL_SW_INT_MASK_SIZE 1 +#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE 1 +#define CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE 1 +#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE 1 +#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE 1 +#define CP_INT_CNTL_IB_ERROR_MASK_SIZE 1 +#define CP_INT_CNTL_IB2_INT_MASK_SIZE 1 +#define CP_INT_CNTL_IB1_INT_MASK_SIZE 1 +#define CP_INT_CNTL_RB_INT_MASK_SIZE 1 + +#define CP_INT_CNTL_SW_INT_MASK_SHIFT 19 +#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT 23 +#define CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT 24 +#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT 25 +#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT 26 +#define CP_INT_CNTL_IB_ERROR_MASK_SHIFT 27 +#define CP_INT_CNTL_IB2_INT_MASK_SHIFT 29 +#define CP_INT_CNTL_IB1_INT_MASK_SHIFT 30 +#define CP_INT_CNTL_RB_INT_MASK_SHIFT 31 + +#define CP_INT_CNTL_SW_INT_MASK_MASK 0x00080000 +#define CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK 0x00800000 +#define CP_INT_CNTL_OPCODE_ERROR_MASK_MASK 0x01000000 +#define CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK 0x02000000 +#define CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK 0x04000000 +#define CP_INT_CNTL_IB_ERROR_MASK_MASK 0x08000000 +#define CP_INT_CNTL_IB2_INT_MASK_MASK 0x20000000 +#define CP_INT_CNTL_IB1_INT_MASK_MASK 0x40000000 +#define CP_INT_CNTL_RB_INT_MASK_MASK 0x80000000 + +#define CP_INT_CNTL_MASK \ + (CP_INT_CNTL_SW_INT_MASK_MASK | \ + CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK | \ + CP_INT_CNTL_OPCODE_ERROR_MASK_MASK | \ + CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK | \ + CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK | \ + CP_INT_CNTL_IB_ERROR_MASK_MASK | \ + CP_INT_CNTL_IB2_INT_MASK_MASK | \ + CP_INT_CNTL_IB1_INT_MASK_MASK | \ + CP_INT_CNTL_RB_INT_MASK_MASK) + +#define CP_INT_CNTL(sw_int_mask, t0_packet_in_ib_mask, opcode_error_mask, protected_mode_error_mask, reserved_bit_error_mask, ib_error_mask, ib2_int_mask, ib1_int_mask, rb_int_mask) \ + ((sw_int_mask << CP_INT_CNTL_SW_INT_MASK_SHIFT) | \ + (t0_packet_in_ib_mask << CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT) | \ + (opcode_error_mask << CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT) | \ + (protected_mode_error_mask << CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT) | \ + (reserved_bit_error_mask << CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT) | \ + (ib_error_mask << CP_INT_CNTL_IB_ERROR_MASK_SHIFT) | \ + (ib2_int_mask << CP_INT_CNTL_IB2_INT_MASK_SHIFT) | \ + (ib1_int_mask << CP_INT_CNTL_IB1_INT_MASK_SHIFT) | \ + (rb_int_mask << CP_INT_CNTL_RB_INT_MASK_SHIFT)) + +#define CP_INT_CNTL_GET_SW_INT_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_SW_INT_MASK_MASK) >> CP_INT_CNTL_SW_INT_MASK_SHIFT) +#define CP_INT_CNTL_GET_T0_PACKET_IN_IB_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK) >> CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT) +#define CP_INT_CNTL_GET_OPCODE_ERROR_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_OPCODE_ERROR_MASK_MASK) >> CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_GET_PROTECTED_MODE_ERROR_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK) >> CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_GET_RESERVED_BIT_ERROR_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK) >> CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_GET_IB_ERROR_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_IB_ERROR_MASK_MASK) >> CP_INT_CNTL_IB_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_GET_IB2_INT_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_IB2_INT_MASK_MASK) >> CP_INT_CNTL_IB2_INT_MASK_SHIFT) +#define CP_INT_CNTL_GET_IB1_INT_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_IB1_INT_MASK_MASK) >> CP_INT_CNTL_IB1_INT_MASK_SHIFT) +#define CP_INT_CNTL_GET_RB_INT_MASK(cp_int_cntl) \ + ((cp_int_cntl & CP_INT_CNTL_RB_INT_MASK_MASK) >> CP_INT_CNTL_RB_INT_MASK_SHIFT) + +#define CP_INT_CNTL_SET_SW_INT_MASK(cp_int_cntl_reg, sw_int_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_SW_INT_MASK_MASK) | (sw_int_mask << CP_INT_CNTL_SW_INT_MASK_SHIFT) +#define CP_INT_CNTL_SET_T0_PACKET_IN_IB_MASK(cp_int_cntl_reg, t0_packet_in_ib_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_T0_PACKET_IN_IB_MASK_MASK) | (t0_packet_in_ib_mask << CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SHIFT) +#define CP_INT_CNTL_SET_OPCODE_ERROR_MASK(cp_int_cntl_reg, opcode_error_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_OPCODE_ERROR_MASK_MASK) | (opcode_error_mask << CP_INT_CNTL_OPCODE_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_SET_PROTECTED_MODE_ERROR_MASK(cp_int_cntl_reg, protected_mode_error_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_MASK) | (protected_mode_error_mask << CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_SET_RESERVED_BIT_ERROR_MASK(cp_int_cntl_reg, reserved_bit_error_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_MASK) | (reserved_bit_error_mask << CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_SET_IB_ERROR_MASK(cp_int_cntl_reg, ib_error_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB_ERROR_MASK_MASK) | (ib_error_mask << CP_INT_CNTL_IB_ERROR_MASK_SHIFT) +#define CP_INT_CNTL_SET_IB2_INT_MASK(cp_int_cntl_reg, ib2_int_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB2_INT_MASK_MASK) | (ib2_int_mask << CP_INT_CNTL_IB2_INT_MASK_SHIFT) +#define CP_INT_CNTL_SET_IB1_INT_MASK(cp_int_cntl_reg, ib1_int_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_IB1_INT_MASK_MASK) | (ib1_int_mask << CP_INT_CNTL_IB1_INT_MASK_SHIFT) +#define CP_INT_CNTL_SET_RB_INT_MASK(cp_int_cntl_reg, rb_int_mask) \ + cp_int_cntl_reg = (cp_int_cntl_reg & ~CP_INT_CNTL_RB_INT_MASK_MASK) | (rb_int_mask << CP_INT_CNTL_RB_INT_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_int_cntl_t { + unsigned int : 19; + unsigned int sw_int_mask : CP_INT_CNTL_SW_INT_MASK_SIZE; + unsigned int : 3; + unsigned int t0_packet_in_ib_mask : CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE; + unsigned int opcode_error_mask : CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE; + unsigned int protected_mode_error_mask : CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE; + unsigned int reserved_bit_error_mask : CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE; + unsigned int ib_error_mask : CP_INT_CNTL_IB_ERROR_MASK_SIZE; + unsigned int : 1; + unsigned int ib2_int_mask : CP_INT_CNTL_IB2_INT_MASK_SIZE; + unsigned int ib1_int_mask : CP_INT_CNTL_IB1_INT_MASK_SIZE; + unsigned int rb_int_mask : CP_INT_CNTL_RB_INT_MASK_SIZE; + } cp_int_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_int_cntl_t { + unsigned int rb_int_mask : CP_INT_CNTL_RB_INT_MASK_SIZE; + unsigned int ib1_int_mask : CP_INT_CNTL_IB1_INT_MASK_SIZE; + unsigned int ib2_int_mask : CP_INT_CNTL_IB2_INT_MASK_SIZE; + unsigned int : 1; + unsigned int ib_error_mask : CP_INT_CNTL_IB_ERROR_MASK_SIZE; + unsigned int reserved_bit_error_mask : CP_INT_CNTL_RESERVED_BIT_ERROR_MASK_SIZE; + unsigned int protected_mode_error_mask : CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK_SIZE; + unsigned int opcode_error_mask : CP_INT_CNTL_OPCODE_ERROR_MASK_SIZE; + unsigned int t0_packet_in_ib_mask : CP_INT_CNTL_T0_PACKET_IN_IB_MASK_SIZE; + unsigned int : 3; + unsigned int sw_int_mask : CP_INT_CNTL_SW_INT_MASK_SIZE; + unsigned int : 19; + } cp_int_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_int_cntl_t f; +} cp_int_cntl_u; + + +/* + * CP_INT_STATUS struct + */ + +#define CP_INT_STATUS_SW_INT_STAT_SIZE 1 +#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE 1 +#define CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE 1 +#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE 1 +#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE 1 +#define CP_INT_STATUS_IB_ERROR_STAT_SIZE 1 +#define CP_INT_STATUS_IB2_INT_STAT_SIZE 1 +#define CP_INT_STATUS_IB1_INT_STAT_SIZE 1 +#define CP_INT_STATUS_RB_INT_STAT_SIZE 1 + +#define CP_INT_STATUS_SW_INT_STAT_SHIFT 19 +#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT 23 +#define CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT 24 +#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT 25 +#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT 26 +#define CP_INT_STATUS_IB_ERROR_STAT_SHIFT 27 +#define CP_INT_STATUS_IB2_INT_STAT_SHIFT 29 +#define CP_INT_STATUS_IB1_INT_STAT_SHIFT 30 +#define CP_INT_STATUS_RB_INT_STAT_SHIFT 31 + +#define CP_INT_STATUS_SW_INT_STAT_MASK 0x00080000 +#define CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK 0x00800000 +#define CP_INT_STATUS_OPCODE_ERROR_STAT_MASK 0x01000000 +#define CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK 0x02000000 +#define CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK 0x04000000 +#define CP_INT_STATUS_IB_ERROR_STAT_MASK 0x08000000 +#define CP_INT_STATUS_IB2_INT_STAT_MASK 0x20000000 +#define CP_INT_STATUS_IB1_INT_STAT_MASK 0x40000000 +#define CP_INT_STATUS_RB_INT_STAT_MASK 0x80000000 + +#define CP_INT_STATUS_MASK \ + (CP_INT_STATUS_SW_INT_STAT_MASK | \ + CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK | \ + CP_INT_STATUS_OPCODE_ERROR_STAT_MASK | \ + CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK | \ + CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK | \ + CP_INT_STATUS_IB_ERROR_STAT_MASK | \ + CP_INT_STATUS_IB2_INT_STAT_MASK | \ + CP_INT_STATUS_IB1_INT_STAT_MASK | \ + CP_INT_STATUS_RB_INT_STAT_MASK) + +#define CP_INT_STATUS(sw_int_stat, t0_packet_in_ib_stat, opcode_error_stat, protected_mode_error_stat, reserved_bit_error_stat, ib_error_stat, ib2_int_stat, ib1_int_stat, rb_int_stat) \ + ((sw_int_stat << CP_INT_STATUS_SW_INT_STAT_SHIFT) | \ + (t0_packet_in_ib_stat << CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT) | \ + (opcode_error_stat << CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT) | \ + (protected_mode_error_stat << CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT) | \ + (reserved_bit_error_stat << CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT) | \ + (ib_error_stat << CP_INT_STATUS_IB_ERROR_STAT_SHIFT) | \ + (ib2_int_stat << CP_INT_STATUS_IB2_INT_STAT_SHIFT) | \ + (ib1_int_stat << CP_INT_STATUS_IB1_INT_STAT_SHIFT) | \ + (rb_int_stat << CP_INT_STATUS_RB_INT_STAT_SHIFT)) + +#define CP_INT_STATUS_GET_SW_INT_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_SW_INT_STAT_MASK) >> CP_INT_STATUS_SW_INT_STAT_SHIFT) +#define CP_INT_STATUS_GET_T0_PACKET_IN_IB_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK) >> CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT) +#define CP_INT_STATUS_GET_OPCODE_ERROR_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_OPCODE_ERROR_STAT_MASK) >> CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_GET_PROTECTED_MODE_ERROR_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK) >> CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_GET_RESERVED_BIT_ERROR_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK) >> CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_GET_IB_ERROR_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_IB_ERROR_STAT_MASK) >> CP_INT_STATUS_IB_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_GET_IB2_INT_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_IB2_INT_STAT_MASK) >> CP_INT_STATUS_IB2_INT_STAT_SHIFT) +#define CP_INT_STATUS_GET_IB1_INT_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_IB1_INT_STAT_MASK) >> CP_INT_STATUS_IB1_INT_STAT_SHIFT) +#define CP_INT_STATUS_GET_RB_INT_STAT(cp_int_status) \ + ((cp_int_status & CP_INT_STATUS_RB_INT_STAT_MASK) >> CP_INT_STATUS_RB_INT_STAT_SHIFT) + +#define CP_INT_STATUS_SET_SW_INT_STAT(cp_int_status_reg, sw_int_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_SW_INT_STAT_MASK) | (sw_int_stat << CP_INT_STATUS_SW_INT_STAT_SHIFT) +#define CP_INT_STATUS_SET_T0_PACKET_IN_IB_STAT(cp_int_status_reg, t0_packet_in_ib_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_T0_PACKET_IN_IB_STAT_MASK) | (t0_packet_in_ib_stat << CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SHIFT) +#define CP_INT_STATUS_SET_OPCODE_ERROR_STAT(cp_int_status_reg, opcode_error_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_OPCODE_ERROR_STAT_MASK) | (opcode_error_stat << CP_INT_STATUS_OPCODE_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_SET_PROTECTED_MODE_ERROR_STAT(cp_int_status_reg, protected_mode_error_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_MASK) | (protected_mode_error_stat << CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_SET_RESERVED_BIT_ERROR_STAT(cp_int_status_reg, reserved_bit_error_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_MASK) | (reserved_bit_error_stat << CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_SET_IB_ERROR_STAT(cp_int_status_reg, ib_error_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB_ERROR_STAT_MASK) | (ib_error_stat << CP_INT_STATUS_IB_ERROR_STAT_SHIFT) +#define CP_INT_STATUS_SET_IB2_INT_STAT(cp_int_status_reg, ib2_int_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB2_INT_STAT_MASK) | (ib2_int_stat << CP_INT_STATUS_IB2_INT_STAT_SHIFT) +#define CP_INT_STATUS_SET_IB1_INT_STAT(cp_int_status_reg, ib1_int_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_IB1_INT_STAT_MASK) | (ib1_int_stat << CP_INT_STATUS_IB1_INT_STAT_SHIFT) +#define CP_INT_STATUS_SET_RB_INT_STAT(cp_int_status_reg, rb_int_stat) \ + cp_int_status_reg = (cp_int_status_reg & ~CP_INT_STATUS_RB_INT_STAT_MASK) | (rb_int_stat << CP_INT_STATUS_RB_INT_STAT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_int_status_t { + unsigned int : 19; + unsigned int sw_int_stat : CP_INT_STATUS_SW_INT_STAT_SIZE; + unsigned int : 3; + unsigned int t0_packet_in_ib_stat : CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE; + unsigned int opcode_error_stat : CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE; + unsigned int protected_mode_error_stat : CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE; + unsigned int reserved_bit_error_stat : CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE; + unsigned int ib_error_stat : CP_INT_STATUS_IB_ERROR_STAT_SIZE; + unsigned int : 1; + unsigned int ib2_int_stat : CP_INT_STATUS_IB2_INT_STAT_SIZE; + unsigned int ib1_int_stat : CP_INT_STATUS_IB1_INT_STAT_SIZE; + unsigned int rb_int_stat : CP_INT_STATUS_RB_INT_STAT_SIZE; + } cp_int_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_int_status_t { + unsigned int rb_int_stat : CP_INT_STATUS_RB_INT_STAT_SIZE; + unsigned int ib1_int_stat : CP_INT_STATUS_IB1_INT_STAT_SIZE; + unsigned int ib2_int_stat : CP_INT_STATUS_IB2_INT_STAT_SIZE; + unsigned int : 1; + unsigned int ib_error_stat : CP_INT_STATUS_IB_ERROR_STAT_SIZE; + unsigned int reserved_bit_error_stat : CP_INT_STATUS_RESERVED_BIT_ERROR_STAT_SIZE; + unsigned int protected_mode_error_stat : CP_INT_STATUS_PROTECTED_MODE_ERROR_STAT_SIZE; + unsigned int opcode_error_stat : CP_INT_STATUS_OPCODE_ERROR_STAT_SIZE; + unsigned int t0_packet_in_ib_stat : CP_INT_STATUS_T0_PACKET_IN_IB_STAT_SIZE; + unsigned int : 3; + unsigned int sw_int_stat : CP_INT_STATUS_SW_INT_STAT_SIZE; + unsigned int : 19; + } cp_int_status_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_int_status_t f; +} cp_int_status_u; + + +/* + * CP_INT_ACK struct + */ + +#define CP_INT_ACK_SW_INT_ACK_SIZE 1 +#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE 1 +#define CP_INT_ACK_OPCODE_ERROR_ACK_SIZE 1 +#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE 1 +#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE 1 +#define CP_INT_ACK_IB_ERROR_ACK_SIZE 1 +#define CP_INT_ACK_IB2_INT_ACK_SIZE 1 +#define CP_INT_ACK_IB1_INT_ACK_SIZE 1 +#define CP_INT_ACK_RB_INT_ACK_SIZE 1 + +#define CP_INT_ACK_SW_INT_ACK_SHIFT 19 +#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT 23 +#define CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT 24 +#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT 25 +#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT 26 +#define CP_INT_ACK_IB_ERROR_ACK_SHIFT 27 +#define CP_INT_ACK_IB2_INT_ACK_SHIFT 29 +#define CP_INT_ACK_IB1_INT_ACK_SHIFT 30 +#define CP_INT_ACK_RB_INT_ACK_SHIFT 31 + +#define CP_INT_ACK_SW_INT_ACK_MASK 0x00080000 +#define CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK 0x00800000 +#define CP_INT_ACK_OPCODE_ERROR_ACK_MASK 0x01000000 +#define CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK 0x02000000 +#define CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK 0x04000000 +#define CP_INT_ACK_IB_ERROR_ACK_MASK 0x08000000 +#define CP_INT_ACK_IB2_INT_ACK_MASK 0x20000000 +#define CP_INT_ACK_IB1_INT_ACK_MASK 0x40000000 +#define CP_INT_ACK_RB_INT_ACK_MASK 0x80000000 + +#define CP_INT_ACK_MASK \ + (CP_INT_ACK_SW_INT_ACK_MASK | \ + CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK | \ + CP_INT_ACK_OPCODE_ERROR_ACK_MASK | \ + CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK | \ + CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK | \ + CP_INT_ACK_IB_ERROR_ACK_MASK | \ + CP_INT_ACK_IB2_INT_ACK_MASK | \ + CP_INT_ACK_IB1_INT_ACK_MASK | \ + CP_INT_ACK_RB_INT_ACK_MASK) + +#define CP_INT_ACK(sw_int_ack, t0_packet_in_ib_ack, opcode_error_ack, protected_mode_error_ack, reserved_bit_error_ack, ib_error_ack, ib2_int_ack, ib1_int_ack, rb_int_ack) \ + ((sw_int_ack << CP_INT_ACK_SW_INT_ACK_SHIFT) | \ + (t0_packet_in_ib_ack << CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT) | \ + (opcode_error_ack << CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT) | \ + (protected_mode_error_ack << CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT) | \ + (reserved_bit_error_ack << CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT) | \ + (ib_error_ack << CP_INT_ACK_IB_ERROR_ACK_SHIFT) | \ + (ib2_int_ack << CP_INT_ACK_IB2_INT_ACK_SHIFT) | \ + (ib1_int_ack << CP_INT_ACK_IB1_INT_ACK_SHIFT) | \ + (rb_int_ack << CP_INT_ACK_RB_INT_ACK_SHIFT)) + +#define CP_INT_ACK_GET_SW_INT_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_SW_INT_ACK_MASK) >> CP_INT_ACK_SW_INT_ACK_SHIFT) +#define CP_INT_ACK_GET_T0_PACKET_IN_IB_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK) >> CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT) +#define CP_INT_ACK_GET_OPCODE_ERROR_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_OPCODE_ERROR_ACK_MASK) >> CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT) +#define CP_INT_ACK_GET_PROTECTED_MODE_ERROR_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK) >> CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT) +#define CP_INT_ACK_GET_RESERVED_BIT_ERROR_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK) >> CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT) +#define CP_INT_ACK_GET_IB_ERROR_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_IB_ERROR_ACK_MASK) >> CP_INT_ACK_IB_ERROR_ACK_SHIFT) +#define CP_INT_ACK_GET_IB2_INT_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_IB2_INT_ACK_MASK) >> CP_INT_ACK_IB2_INT_ACK_SHIFT) +#define CP_INT_ACK_GET_IB1_INT_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_IB1_INT_ACK_MASK) >> CP_INT_ACK_IB1_INT_ACK_SHIFT) +#define CP_INT_ACK_GET_RB_INT_ACK(cp_int_ack) \ + ((cp_int_ack & CP_INT_ACK_RB_INT_ACK_MASK) >> CP_INT_ACK_RB_INT_ACK_SHIFT) + +#define CP_INT_ACK_SET_SW_INT_ACK(cp_int_ack_reg, sw_int_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_SW_INT_ACK_MASK) | (sw_int_ack << CP_INT_ACK_SW_INT_ACK_SHIFT) +#define CP_INT_ACK_SET_T0_PACKET_IN_IB_ACK(cp_int_ack_reg, t0_packet_in_ib_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_T0_PACKET_IN_IB_ACK_MASK) | (t0_packet_in_ib_ack << CP_INT_ACK_T0_PACKET_IN_IB_ACK_SHIFT) +#define CP_INT_ACK_SET_OPCODE_ERROR_ACK(cp_int_ack_reg, opcode_error_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_OPCODE_ERROR_ACK_MASK) | (opcode_error_ack << CP_INT_ACK_OPCODE_ERROR_ACK_SHIFT) +#define CP_INT_ACK_SET_PROTECTED_MODE_ERROR_ACK(cp_int_ack_reg, protected_mode_error_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_MASK) | (protected_mode_error_ack << CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SHIFT) +#define CP_INT_ACK_SET_RESERVED_BIT_ERROR_ACK(cp_int_ack_reg, reserved_bit_error_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_RESERVED_BIT_ERROR_ACK_MASK) | (reserved_bit_error_ack << CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SHIFT) +#define CP_INT_ACK_SET_IB_ERROR_ACK(cp_int_ack_reg, ib_error_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB_ERROR_ACK_MASK) | (ib_error_ack << CP_INT_ACK_IB_ERROR_ACK_SHIFT) +#define CP_INT_ACK_SET_IB2_INT_ACK(cp_int_ack_reg, ib2_int_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB2_INT_ACK_MASK) | (ib2_int_ack << CP_INT_ACK_IB2_INT_ACK_SHIFT) +#define CP_INT_ACK_SET_IB1_INT_ACK(cp_int_ack_reg, ib1_int_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_IB1_INT_ACK_MASK) | (ib1_int_ack << CP_INT_ACK_IB1_INT_ACK_SHIFT) +#define CP_INT_ACK_SET_RB_INT_ACK(cp_int_ack_reg, rb_int_ack) \ + cp_int_ack_reg = (cp_int_ack_reg & ~CP_INT_ACK_RB_INT_ACK_MASK) | (rb_int_ack << CP_INT_ACK_RB_INT_ACK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_int_ack_t { + unsigned int : 19; + unsigned int sw_int_ack : CP_INT_ACK_SW_INT_ACK_SIZE; + unsigned int : 3; + unsigned int t0_packet_in_ib_ack : CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE; + unsigned int opcode_error_ack : CP_INT_ACK_OPCODE_ERROR_ACK_SIZE; + unsigned int protected_mode_error_ack : CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE; + unsigned int reserved_bit_error_ack : CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE; + unsigned int ib_error_ack : CP_INT_ACK_IB_ERROR_ACK_SIZE; + unsigned int : 1; + unsigned int ib2_int_ack : CP_INT_ACK_IB2_INT_ACK_SIZE; + unsigned int ib1_int_ack : CP_INT_ACK_IB1_INT_ACK_SIZE; + unsigned int rb_int_ack : CP_INT_ACK_RB_INT_ACK_SIZE; + } cp_int_ack_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_int_ack_t { + unsigned int rb_int_ack : CP_INT_ACK_RB_INT_ACK_SIZE; + unsigned int ib1_int_ack : CP_INT_ACK_IB1_INT_ACK_SIZE; + unsigned int ib2_int_ack : CP_INT_ACK_IB2_INT_ACK_SIZE; + unsigned int : 1; + unsigned int ib_error_ack : CP_INT_ACK_IB_ERROR_ACK_SIZE; + unsigned int reserved_bit_error_ack : CP_INT_ACK_RESERVED_BIT_ERROR_ACK_SIZE; + unsigned int protected_mode_error_ack : CP_INT_ACK_PROTECTED_MODE_ERROR_ACK_SIZE; + unsigned int opcode_error_ack : CP_INT_ACK_OPCODE_ERROR_ACK_SIZE; + unsigned int t0_packet_in_ib_ack : CP_INT_ACK_T0_PACKET_IN_IB_ACK_SIZE; + unsigned int : 3; + unsigned int sw_int_ack : CP_INT_ACK_SW_INT_ACK_SIZE; + unsigned int : 19; + } cp_int_ack_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_int_ack_t f; +} cp_int_ack_u; + + +/* + * CP_PFP_UCODE_ADDR struct + */ + +#define CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE 9 + +#define CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT 0 + +#define CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK 0x000001ff + +#define CP_PFP_UCODE_ADDR_MASK \ + (CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) + +#define CP_PFP_UCODE_ADDR(ucode_addr) \ + ((ucode_addr << CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT)) + +#define CP_PFP_UCODE_ADDR_GET_UCODE_ADDR(cp_pfp_ucode_addr) \ + ((cp_pfp_ucode_addr & CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) >> CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT) + +#define CP_PFP_UCODE_ADDR_SET_UCODE_ADDR(cp_pfp_ucode_addr_reg, ucode_addr) \ + cp_pfp_ucode_addr_reg = (cp_pfp_ucode_addr_reg & ~CP_PFP_UCODE_ADDR_UCODE_ADDR_MASK) | (ucode_addr << CP_PFP_UCODE_ADDR_UCODE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_pfp_ucode_addr_t { + unsigned int ucode_addr : CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE; + unsigned int : 23; + } cp_pfp_ucode_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_pfp_ucode_addr_t { + unsigned int : 23; + unsigned int ucode_addr : CP_PFP_UCODE_ADDR_UCODE_ADDR_SIZE; + } cp_pfp_ucode_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_pfp_ucode_addr_t f; +} cp_pfp_ucode_addr_u; + + +/* + * CP_PFP_UCODE_DATA struct + */ + +#define CP_PFP_UCODE_DATA_UCODE_DATA_SIZE 24 + +#define CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT 0 + +#define CP_PFP_UCODE_DATA_UCODE_DATA_MASK 0x00ffffff + +#define CP_PFP_UCODE_DATA_MASK \ + (CP_PFP_UCODE_DATA_UCODE_DATA_MASK) + +#define CP_PFP_UCODE_DATA(ucode_data) \ + ((ucode_data << CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT)) + +#define CP_PFP_UCODE_DATA_GET_UCODE_DATA(cp_pfp_ucode_data) \ + ((cp_pfp_ucode_data & CP_PFP_UCODE_DATA_UCODE_DATA_MASK) >> CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT) + +#define CP_PFP_UCODE_DATA_SET_UCODE_DATA(cp_pfp_ucode_data_reg, ucode_data) \ + cp_pfp_ucode_data_reg = (cp_pfp_ucode_data_reg & ~CP_PFP_UCODE_DATA_UCODE_DATA_MASK) | (ucode_data << CP_PFP_UCODE_DATA_UCODE_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_pfp_ucode_data_t { + unsigned int ucode_data : CP_PFP_UCODE_DATA_UCODE_DATA_SIZE; + unsigned int : 8; + } cp_pfp_ucode_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_pfp_ucode_data_t { + unsigned int : 8; + unsigned int ucode_data : CP_PFP_UCODE_DATA_UCODE_DATA_SIZE; + } cp_pfp_ucode_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_pfp_ucode_data_t f; +} cp_pfp_ucode_data_u; + + +/* + * CP_PERFMON_CNTL struct + */ + +#define CP_PERFMON_CNTL_PERFMON_STATE_SIZE 4 +#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE 2 + +#define CP_PERFMON_CNTL_PERFMON_STATE_SHIFT 0 +#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT 8 + +#define CP_PERFMON_CNTL_PERFMON_STATE_MASK 0x0000000f +#define CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK 0x00000300 + +#define CP_PERFMON_CNTL_MASK \ + (CP_PERFMON_CNTL_PERFMON_STATE_MASK | \ + CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) + +#define CP_PERFMON_CNTL(perfmon_state, perfmon_enable_mode) \ + ((perfmon_state << CP_PERFMON_CNTL_PERFMON_STATE_SHIFT) | \ + (perfmon_enable_mode << CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT)) + +#define CP_PERFMON_CNTL_GET_PERFMON_STATE(cp_perfmon_cntl) \ + ((cp_perfmon_cntl & CP_PERFMON_CNTL_PERFMON_STATE_MASK) >> CP_PERFMON_CNTL_PERFMON_STATE_SHIFT) +#define CP_PERFMON_CNTL_GET_PERFMON_ENABLE_MODE(cp_perfmon_cntl) \ + ((cp_perfmon_cntl & CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) >> CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT) + +#define CP_PERFMON_CNTL_SET_PERFMON_STATE(cp_perfmon_cntl_reg, perfmon_state) \ + cp_perfmon_cntl_reg = (cp_perfmon_cntl_reg & ~CP_PERFMON_CNTL_PERFMON_STATE_MASK) | (perfmon_state << CP_PERFMON_CNTL_PERFMON_STATE_SHIFT) +#define CP_PERFMON_CNTL_SET_PERFMON_ENABLE_MODE(cp_perfmon_cntl_reg, perfmon_enable_mode) \ + cp_perfmon_cntl_reg = (cp_perfmon_cntl_reg & ~CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_MASK) | (perfmon_enable_mode << CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_perfmon_cntl_t { + unsigned int perfmon_state : CP_PERFMON_CNTL_PERFMON_STATE_SIZE; + unsigned int : 4; + unsigned int perfmon_enable_mode : CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE; + unsigned int : 22; + } cp_perfmon_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_perfmon_cntl_t { + unsigned int : 22; + unsigned int perfmon_enable_mode : CP_PERFMON_CNTL_PERFMON_ENABLE_MODE_SIZE; + unsigned int : 4; + unsigned int perfmon_state : CP_PERFMON_CNTL_PERFMON_STATE_SIZE; + } cp_perfmon_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_perfmon_cntl_t f; +} cp_perfmon_cntl_u; + + +/* + * CP_PERFCOUNTER_SELECT struct + */ + +#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE 6 + +#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT 0 + +#define CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK 0x0000003f + +#define CP_PERFCOUNTER_SELECT_MASK \ + (CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) + +#define CP_PERFCOUNTER_SELECT(perfcount_sel) \ + ((perfcount_sel << CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT)) + +#define CP_PERFCOUNTER_SELECT_GET_PERFCOUNT_SEL(cp_perfcounter_select) \ + ((cp_perfcounter_select & CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) >> CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT) + +#define CP_PERFCOUNTER_SELECT_SET_PERFCOUNT_SEL(cp_perfcounter_select_reg, perfcount_sel) \ + cp_perfcounter_select_reg = (cp_perfcounter_select_reg & ~CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_MASK) | (perfcount_sel << CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_perfcounter_select_t { + unsigned int perfcount_sel : CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE; + unsigned int : 26; + } cp_perfcounter_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_perfcounter_select_t { + unsigned int : 26; + unsigned int perfcount_sel : CP_PERFCOUNTER_SELECT_PERFCOUNT_SEL_SIZE; + } cp_perfcounter_select_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_perfcounter_select_t f; +} cp_perfcounter_select_u; + + +/* + * CP_PERFCOUNTER_LO struct + */ + +#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE 32 + +#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT 0 + +#define CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK 0xffffffff + +#define CP_PERFCOUNTER_LO_MASK \ + (CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) + +#define CP_PERFCOUNTER_LO(perfcount_lo) \ + ((perfcount_lo << CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT)) + +#define CP_PERFCOUNTER_LO_GET_PERFCOUNT_LO(cp_perfcounter_lo) \ + ((cp_perfcounter_lo & CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) >> CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT) + +#define CP_PERFCOUNTER_LO_SET_PERFCOUNT_LO(cp_perfcounter_lo_reg, perfcount_lo) \ + cp_perfcounter_lo_reg = (cp_perfcounter_lo_reg & ~CP_PERFCOUNTER_LO_PERFCOUNT_LO_MASK) | (perfcount_lo << CP_PERFCOUNTER_LO_PERFCOUNT_LO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_perfcounter_lo_t { + unsigned int perfcount_lo : CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE; + } cp_perfcounter_lo_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_perfcounter_lo_t { + unsigned int perfcount_lo : CP_PERFCOUNTER_LO_PERFCOUNT_LO_SIZE; + } cp_perfcounter_lo_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_perfcounter_lo_t f; +} cp_perfcounter_lo_u; + + +/* + * CP_PERFCOUNTER_HI struct + */ + +#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE 16 + +#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT 0 + +#define CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK 0x0000ffff + +#define CP_PERFCOUNTER_HI_MASK \ + (CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) + +#define CP_PERFCOUNTER_HI(perfcount_hi) \ + ((perfcount_hi << CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT)) + +#define CP_PERFCOUNTER_HI_GET_PERFCOUNT_HI(cp_perfcounter_hi) \ + ((cp_perfcounter_hi & CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) >> CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT) + +#define CP_PERFCOUNTER_HI_SET_PERFCOUNT_HI(cp_perfcounter_hi_reg, perfcount_hi) \ + cp_perfcounter_hi_reg = (cp_perfcounter_hi_reg & ~CP_PERFCOUNTER_HI_PERFCOUNT_HI_MASK) | (perfcount_hi << CP_PERFCOUNTER_HI_PERFCOUNT_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_perfcounter_hi_t { + unsigned int perfcount_hi : CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE; + unsigned int : 16; + } cp_perfcounter_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_perfcounter_hi_t { + unsigned int : 16; + unsigned int perfcount_hi : CP_PERFCOUNTER_HI_PERFCOUNT_HI_SIZE; + } cp_perfcounter_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_perfcounter_hi_t f; +} cp_perfcounter_hi_u; + + +/* + * CP_BIN_MASK_LO struct + */ + +#define CP_BIN_MASK_LO_BIN_MASK_LO_SIZE 32 + +#define CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT 0 + +#define CP_BIN_MASK_LO_BIN_MASK_LO_MASK 0xffffffff + +#define CP_BIN_MASK_LO_MASK \ + (CP_BIN_MASK_LO_BIN_MASK_LO_MASK) + +#define CP_BIN_MASK_LO(bin_mask_lo) \ + ((bin_mask_lo << CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT)) + +#define CP_BIN_MASK_LO_GET_BIN_MASK_LO(cp_bin_mask_lo) \ + ((cp_bin_mask_lo & CP_BIN_MASK_LO_BIN_MASK_LO_MASK) >> CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT) + +#define CP_BIN_MASK_LO_SET_BIN_MASK_LO(cp_bin_mask_lo_reg, bin_mask_lo) \ + cp_bin_mask_lo_reg = (cp_bin_mask_lo_reg & ~CP_BIN_MASK_LO_BIN_MASK_LO_MASK) | (bin_mask_lo << CP_BIN_MASK_LO_BIN_MASK_LO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_bin_mask_lo_t { + unsigned int bin_mask_lo : CP_BIN_MASK_LO_BIN_MASK_LO_SIZE; + } cp_bin_mask_lo_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_bin_mask_lo_t { + unsigned int bin_mask_lo : CP_BIN_MASK_LO_BIN_MASK_LO_SIZE; + } cp_bin_mask_lo_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_bin_mask_lo_t f; +} cp_bin_mask_lo_u; + + +/* + * CP_BIN_MASK_HI struct + */ + +#define CP_BIN_MASK_HI_BIN_MASK_HI_SIZE 32 + +#define CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT 0 + +#define CP_BIN_MASK_HI_BIN_MASK_HI_MASK 0xffffffff + +#define CP_BIN_MASK_HI_MASK \ + (CP_BIN_MASK_HI_BIN_MASK_HI_MASK) + +#define CP_BIN_MASK_HI(bin_mask_hi) \ + ((bin_mask_hi << CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT)) + +#define CP_BIN_MASK_HI_GET_BIN_MASK_HI(cp_bin_mask_hi) \ + ((cp_bin_mask_hi & CP_BIN_MASK_HI_BIN_MASK_HI_MASK) >> CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT) + +#define CP_BIN_MASK_HI_SET_BIN_MASK_HI(cp_bin_mask_hi_reg, bin_mask_hi) \ + cp_bin_mask_hi_reg = (cp_bin_mask_hi_reg & ~CP_BIN_MASK_HI_BIN_MASK_HI_MASK) | (bin_mask_hi << CP_BIN_MASK_HI_BIN_MASK_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_bin_mask_hi_t { + unsigned int bin_mask_hi : CP_BIN_MASK_HI_BIN_MASK_HI_SIZE; + } cp_bin_mask_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_bin_mask_hi_t { + unsigned int bin_mask_hi : CP_BIN_MASK_HI_BIN_MASK_HI_SIZE; + } cp_bin_mask_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_bin_mask_hi_t f; +} cp_bin_mask_hi_u; + + +/* + * CP_BIN_SELECT_LO struct + */ + +#define CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE 32 + +#define CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT 0 + +#define CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK 0xffffffff + +#define CP_BIN_SELECT_LO_MASK \ + (CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) + +#define CP_BIN_SELECT_LO(bin_select_lo) \ + ((bin_select_lo << CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT)) + +#define CP_BIN_SELECT_LO_GET_BIN_SELECT_LO(cp_bin_select_lo) \ + ((cp_bin_select_lo & CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) >> CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT) + +#define CP_BIN_SELECT_LO_SET_BIN_SELECT_LO(cp_bin_select_lo_reg, bin_select_lo) \ + cp_bin_select_lo_reg = (cp_bin_select_lo_reg & ~CP_BIN_SELECT_LO_BIN_SELECT_LO_MASK) | (bin_select_lo << CP_BIN_SELECT_LO_BIN_SELECT_LO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_bin_select_lo_t { + unsigned int bin_select_lo : CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE; + } cp_bin_select_lo_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_bin_select_lo_t { + unsigned int bin_select_lo : CP_BIN_SELECT_LO_BIN_SELECT_LO_SIZE; + } cp_bin_select_lo_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_bin_select_lo_t f; +} cp_bin_select_lo_u; + + +/* + * CP_BIN_SELECT_HI struct + */ + +#define CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE 32 + +#define CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT 0 + +#define CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK 0xffffffff + +#define CP_BIN_SELECT_HI_MASK \ + (CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) + +#define CP_BIN_SELECT_HI(bin_select_hi) \ + ((bin_select_hi << CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT)) + +#define CP_BIN_SELECT_HI_GET_BIN_SELECT_HI(cp_bin_select_hi) \ + ((cp_bin_select_hi & CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) >> CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT) + +#define CP_BIN_SELECT_HI_SET_BIN_SELECT_HI(cp_bin_select_hi_reg, bin_select_hi) \ + cp_bin_select_hi_reg = (cp_bin_select_hi_reg & ~CP_BIN_SELECT_HI_BIN_SELECT_HI_MASK) | (bin_select_hi << CP_BIN_SELECT_HI_BIN_SELECT_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_bin_select_hi_t { + unsigned int bin_select_hi : CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE; + } cp_bin_select_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_bin_select_hi_t { + unsigned int bin_select_hi : CP_BIN_SELECT_HI_BIN_SELECT_HI_SIZE; + } cp_bin_select_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_bin_select_hi_t f; +} cp_bin_select_hi_u; + + +/* + * CP_NV_FLAGS_0 struct + */ + +#define CP_NV_FLAGS_0_DISCARD_0_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_0_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_1_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_1_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_2_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_2_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_3_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_3_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_4_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_4_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_5_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_5_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_6_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_6_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_7_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_7_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_8_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_8_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_9_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_9_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_10_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_10_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_11_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_11_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_12_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_12_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_13_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_13_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_14_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_14_SIZE 1 +#define CP_NV_FLAGS_0_DISCARD_15_SIZE 1 +#define CP_NV_FLAGS_0_END_RCVD_15_SIZE 1 + +#define CP_NV_FLAGS_0_DISCARD_0_SHIFT 0 +#define CP_NV_FLAGS_0_END_RCVD_0_SHIFT 1 +#define CP_NV_FLAGS_0_DISCARD_1_SHIFT 2 +#define CP_NV_FLAGS_0_END_RCVD_1_SHIFT 3 +#define CP_NV_FLAGS_0_DISCARD_2_SHIFT 4 +#define CP_NV_FLAGS_0_END_RCVD_2_SHIFT 5 +#define CP_NV_FLAGS_0_DISCARD_3_SHIFT 6 +#define CP_NV_FLAGS_0_END_RCVD_3_SHIFT 7 +#define CP_NV_FLAGS_0_DISCARD_4_SHIFT 8 +#define CP_NV_FLAGS_0_END_RCVD_4_SHIFT 9 +#define CP_NV_FLAGS_0_DISCARD_5_SHIFT 10 +#define CP_NV_FLAGS_0_END_RCVD_5_SHIFT 11 +#define CP_NV_FLAGS_0_DISCARD_6_SHIFT 12 +#define CP_NV_FLAGS_0_END_RCVD_6_SHIFT 13 +#define CP_NV_FLAGS_0_DISCARD_7_SHIFT 14 +#define CP_NV_FLAGS_0_END_RCVD_7_SHIFT 15 +#define CP_NV_FLAGS_0_DISCARD_8_SHIFT 16 +#define CP_NV_FLAGS_0_END_RCVD_8_SHIFT 17 +#define CP_NV_FLAGS_0_DISCARD_9_SHIFT 18 +#define CP_NV_FLAGS_0_END_RCVD_9_SHIFT 19 +#define CP_NV_FLAGS_0_DISCARD_10_SHIFT 20 +#define CP_NV_FLAGS_0_END_RCVD_10_SHIFT 21 +#define CP_NV_FLAGS_0_DISCARD_11_SHIFT 22 +#define CP_NV_FLAGS_0_END_RCVD_11_SHIFT 23 +#define CP_NV_FLAGS_0_DISCARD_12_SHIFT 24 +#define CP_NV_FLAGS_0_END_RCVD_12_SHIFT 25 +#define CP_NV_FLAGS_0_DISCARD_13_SHIFT 26 +#define CP_NV_FLAGS_0_END_RCVD_13_SHIFT 27 +#define CP_NV_FLAGS_0_DISCARD_14_SHIFT 28 +#define CP_NV_FLAGS_0_END_RCVD_14_SHIFT 29 +#define CP_NV_FLAGS_0_DISCARD_15_SHIFT 30 +#define CP_NV_FLAGS_0_END_RCVD_15_SHIFT 31 + +#define CP_NV_FLAGS_0_DISCARD_0_MASK 0x00000001 +#define CP_NV_FLAGS_0_END_RCVD_0_MASK 0x00000002 +#define CP_NV_FLAGS_0_DISCARD_1_MASK 0x00000004 +#define CP_NV_FLAGS_0_END_RCVD_1_MASK 0x00000008 +#define CP_NV_FLAGS_0_DISCARD_2_MASK 0x00000010 +#define CP_NV_FLAGS_0_END_RCVD_2_MASK 0x00000020 +#define CP_NV_FLAGS_0_DISCARD_3_MASK 0x00000040 +#define CP_NV_FLAGS_0_END_RCVD_3_MASK 0x00000080 +#define CP_NV_FLAGS_0_DISCARD_4_MASK 0x00000100 +#define CP_NV_FLAGS_0_END_RCVD_4_MASK 0x00000200 +#define CP_NV_FLAGS_0_DISCARD_5_MASK 0x00000400 +#define CP_NV_FLAGS_0_END_RCVD_5_MASK 0x00000800 +#define CP_NV_FLAGS_0_DISCARD_6_MASK 0x00001000 +#define CP_NV_FLAGS_0_END_RCVD_6_MASK 0x00002000 +#define CP_NV_FLAGS_0_DISCARD_7_MASK 0x00004000 +#define CP_NV_FLAGS_0_END_RCVD_7_MASK 0x00008000 +#define CP_NV_FLAGS_0_DISCARD_8_MASK 0x00010000 +#define CP_NV_FLAGS_0_END_RCVD_8_MASK 0x00020000 +#define CP_NV_FLAGS_0_DISCARD_9_MASK 0x00040000 +#define CP_NV_FLAGS_0_END_RCVD_9_MASK 0x00080000 +#define CP_NV_FLAGS_0_DISCARD_10_MASK 0x00100000 +#define CP_NV_FLAGS_0_END_RCVD_10_MASK 0x00200000 +#define CP_NV_FLAGS_0_DISCARD_11_MASK 0x00400000 +#define CP_NV_FLAGS_0_END_RCVD_11_MASK 0x00800000 +#define CP_NV_FLAGS_0_DISCARD_12_MASK 0x01000000 +#define CP_NV_FLAGS_0_END_RCVD_12_MASK 0x02000000 +#define CP_NV_FLAGS_0_DISCARD_13_MASK 0x04000000 +#define CP_NV_FLAGS_0_END_RCVD_13_MASK 0x08000000 +#define CP_NV_FLAGS_0_DISCARD_14_MASK 0x10000000 +#define CP_NV_FLAGS_0_END_RCVD_14_MASK 0x20000000 +#define CP_NV_FLAGS_0_DISCARD_15_MASK 0x40000000 +#define CP_NV_FLAGS_0_END_RCVD_15_MASK 0x80000000 + +#define CP_NV_FLAGS_0_MASK \ + (CP_NV_FLAGS_0_DISCARD_0_MASK | \ + CP_NV_FLAGS_0_END_RCVD_0_MASK | \ + CP_NV_FLAGS_0_DISCARD_1_MASK | \ + CP_NV_FLAGS_0_END_RCVD_1_MASK | \ + CP_NV_FLAGS_0_DISCARD_2_MASK | \ + CP_NV_FLAGS_0_END_RCVD_2_MASK | \ + CP_NV_FLAGS_0_DISCARD_3_MASK | \ + CP_NV_FLAGS_0_END_RCVD_3_MASK | \ + CP_NV_FLAGS_0_DISCARD_4_MASK | \ + CP_NV_FLAGS_0_END_RCVD_4_MASK | \ + CP_NV_FLAGS_0_DISCARD_5_MASK | \ + CP_NV_FLAGS_0_END_RCVD_5_MASK | \ + CP_NV_FLAGS_0_DISCARD_6_MASK | \ + CP_NV_FLAGS_0_END_RCVD_6_MASK | \ + CP_NV_FLAGS_0_DISCARD_7_MASK | \ + CP_NV_FLAGS_0_END_RCVD_7_MASK | \ + CP_NV_FLAGS_0_DISCARD_8_MASK | \ + CP_NV_FLAGS_0_END_RCVD_8_MASK | \ + CP_NV_FLAGS_0_DISCARD_9_MASK | \ + CP_NV_FLAGS_0_END_RCVD_9_MASK | \ + CP_NV_FLAGS_0_DISCARD_10_MASK | \ + CP_NV_FLAGS_0_END_RCVD_10_MASK | \ + CP_NV_FLAGS_0_DISCARD_11_MASK | \ + CP_NV_FLAGS_0_END_RCVD_11_MASK | \ + CP_NV_FLAGS_0_DISCARD_12_MASK | \ + CP_NV_FLAGS_0_END_RCVD_12_MASK | \ + CP_NV_FLAGS_0_DISCARD_13_MASK | \ + CP_NV_FLAGS_0_END_RCVD_13_MASK | \ + CP_NV_FLAGS_0_DISCARD_14_MASK | \ + CP_NV_FLAGS_0_END_RCVD_14_MASK | \ + CP_NV_FLAGS_0_DISCARD_15_MASK | \ + CP_NV_FLAGS_0_END_RCVD_15_MASK) + +#define CP_NV_FLAGS_0(discard_0, end_rcvd_0, discard_1, end_rcvd_1, discard_2, end_rcvd_2, discard_3, end_rcvd_3, discard_4, end_rcvd_4, discard_5, end_rcvd_5, discard_6, end_rcvd_6, discard_7, end_rcvd_7, discard_8, end_rcvd_8, discard_9, end_rcvd_9, discard_10, end_rcvd_10, discard_11, end_rcvd_11, discard_12, end_rcvd_12, discard_13, end_rcvd_13, discard_14, end_rcvd_14, discard_15, end_rcvd_15) \ + ((discard_0 << CP_NV_FLAGS_0_DISCARD_0_SHIFT) | \ + (end_rcvd_0 << CP_NV_FLAGS_0_END_RCVD_0_SHIFT) | \ + (discard_1 << CP_NV_FLAGS_0_DISCARD_1_SHIFT) | \ + (end_rcvd_1 << CP_NV_FLAGS_0_END_RCVD_1_SHIFT) | \ + (discard_2 << CP_NV_FLAGS_0_DISCARD_2_SHIFT) | \ + (end_rcvd_2 << CP_NV_FLAGS_0_END_RCVD_2_SHIFT) | \ + (discard_3 << CP_NV_FLAGS_0_DISCARD_3_SHIFT) | \ + (end_rcvd_3 << CP_NV_FLAGS_0_END_RCVD_3_SHIFT) | \ + (discard_4 << CP_NV_FLAGS_0_DISCARD_4_SHIFT) | \ + (end_rcvd_4 << CP_NV_FLAGS_0_END_RCVD_4_SHIFT) | \ + (discard_5 << CP_NV_FLAGS_0_DISCARD_5_SHIFT) | \ + (end_rcvd_5 << CP_NV_FLAGS_0_END_RCVD_5_SHIFT) | \ + (discard_6 << CP_NV_FLAGS_0_DISCARD_6_SHIFT) | \ + (end_rcvd_6 << CP_NV_FLAGS_0_END_RCVD_6_SHIFT) | \ + (discard_7 << CP_NV_FLAGS_0_DISCARD_7_SHIFT) | \ + (end_rcvd_7 << CP_NV_FLAGS_0_END_RCVD_7_SHIFT) | \ + (discard_8 << CP_NV_FLAGS_0_DISCARD_8_SHIFT) | \ + (end_rcvd_8 << CP_NV_FLAGS_0_END_RCVD_8_SHIFT) | \ + (discard_9 << CP_NV_FLAGS_0_DISCARD_9_SHIFT) | \ + (end_rcvd_9 << CP_NV_FLAGS_0_END_RCVD_9_SHIFT) | \ + (discard_10 << CP_NV_FLAGS_0_DISCARD_10_SHIFT) | \ + (end_rcvd_10 << CP_NV_FLAGS_0_END_RCVD_10_SHIFT) | \ + (discard_11 << CP_NV_FLAGS_0_DISCARD_11_SHIFT) | \ + (end_rcvd_11 << CP_NV_FLAGS_0_END_RCVD_11_SHIFT) | \ + (discard_12 << CP_NV_FLAGS_0_DISCARD_12_SHIFT) | \ + (end_rcvd_12 << CP_NV_FLAGS_0_END_RCVD_12_SHIFT) | \ + (discard_13 << CP_NV_FLAGS_0_DISCARD_13_SHIFT) | \ + (end_rcvd_13 << CP_NV_FLAGS_0_END_RCVD_13_SHIFT) | \ + (discard_14 << CP_NV_FLAGS_0_DISCARD_14_SHIFT) | \ + (end_rcvd_14 << CP_NV_FLAGS_0_END_RCVD_14_SHIFT) | \ + (discard_15 << CP_NV_FLAGS_0_DISCARD_15_SHIFT) | \ + (end_rcvd_15 << CP_NV_FLAGS_0_END_RCVD_15_SHIFT)) + +#define CP_NV_FLAGS_0_GET_DISCARD_0(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_0_MASK) >> CP_NV_FLAGS_0_DISCARD_0_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_0(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_0_MASK) >> CP_NV_FLAGS_0_END_RCVD_0_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_1(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_1_MASK) >> CP_NV_FLAGS_0_DISCARD_1_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_1(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_1_MASK) >> CP_NV_FLAGS_0_END_RCVD_1_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_2(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_2_MASK) >> CP_NV_FLAGS_0_DISCARD_2_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_2(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_2_MASK) >> CP_NV_FLAGS_0_END_RCVD_2_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_3(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_3_MASK) >> CP_NV_FLAGS_0_DISCARD_3_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_3(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_3_MASK) >> CP_NV_FLAGS_0_END_RCVD_3_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_4(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_4_MASK) >> CP_NV_FLAGS_0_DISCARD_4_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_4(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_4_MASK) >> CP_NV_FLAGS_0_END_RCVD_4_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_5(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_5_MASK) >> CP_NV_FLAGS_0_DISCARD_5_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_5(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_5_MASK) >> CP_NV_FLAGS_0_END_RCVD_5_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_6(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_6_MASK) >> CP_NV_FLAGS_0_DISCARD_6_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_6(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_6_MASK) >> CP_NV_FLAGS_0_END_RCVD_6_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_7(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_7_MASK) >> CP_NV_FLAGS_0_DISCARD_7_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_7(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_7_MASK) >> CP_NV_FLAGS_0_END_RCVD_7_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_8(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_8_MASK) >> CP_NV_FLAGS_0_DISCARD_8_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_8(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_8_MASK) >> CP_NV_FLAGS_0_END_RCVD_8_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_9(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_9_MASK) >> CP_NV_FLAGS_0_DISCARD_9_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_9(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_9_MASK) >> CP_NV_FLAGS_0_END_RCVD_9_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_10(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_10_MASK) >> CP_NV_FLAGS_0_DISCARD_10_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_10(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_10_MASK) >> CP_NV_FLAGS_0_END_RCVD_10_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_11(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_11_MASK) >> CP_NV_FLAGS_0_DISCARD_11_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_11(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_11_MASK) >> CP_NV_FLAGS_0_END_RCVD_11_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_12(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_12_MASK) >> CP_NV_FLAGS_0_DISCARD_12_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_12(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_12_MASK) >> CP_NV_FLAGS_0_END_RCVD_12_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_13(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_13_MASK) >> CP_NV_FLAGS_0_DISCARD_13_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_13(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_13_MASK) >> CP_NV_FLAGS_0_END_RCVD_13_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_14(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_14_MASK) >> CP_NV_FLAGS_0_DISCARD_14_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_14(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_14_MASK) >> CP_NV_FLAGS_0_END_RCVD_14_SHIFT) +#define CP_NV_FLAGS_0_GET_DISCARD_15(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_DISCARD_15_MASK) >> CP_NV_FLAGS_0_DISCARD_15_SHIFT) +#define CP_NV_FLAGS_0_GET_END_RCVD_15(cp_nv_flags_0) \ + ((cp_nv_flags_0 & CP_NV_FLAGS_0_END_RCVD_15_MASK) >> CP_NV_FLAGS_0_END_RCVD_15_SHIFT) + +#define CP_NV_FLAGS_0_SET_DISCARD_0(cp_nv_flags_0_reg, discard_0) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_0_MASK) | (discard_0 << CP_NV_FLAGS_0_DISCARD_0_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_0(cp_nv_flags_0_reg, end_rcvd_0) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_0_MASK) | (end_rcvd_0 << CP_NV_FLAGS_0_END_RCVD_0_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_1(cp_nv_flags_0_reg, discard_1) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_1_MASK) | (discard_1 << CP_NV_FLAGS_0_DISCARD_1_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_1(cp_nv_flags_0_reg, end_rcvd_1) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_1_MASK) | (end_rcvd_1 << CP_NV_FLAGS_0_END_RCVD_1_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_2(cp_nv_flags_0_reg, discard_2) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_2_MASK) | (discard_2 << CP_NV_FLAGS_0_DISCARD_2_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_2(cp_nv_flags_0_reg, end_rcvd_2) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_2_MASK) | (end_rcvd_2 << CP_NV_FLAGS_0_END_RCVD_2_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_3(cp_nv_flags_0_reg, discard_3) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_3_MASK) | (discard_3 << CP_NV_FLAGS_0_DISCARD_3_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_3(cp_nv_flags_0_reg, end_rcvd_3) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_3_MASK) | (end_rcvd_3 << CP_NV_FLAGS_0_END_RCVD_3_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_4(cp_nv_flags_0_reg, discard_4) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_4_MASK) | (discard_4 << CP_NV_FLAGS_0_DISCARD_4_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_4(cp_nv_flags_0_reg, end_rcvd_4) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_4_MASK) | (end_rcvd_4 << CP_NV_FLAGS_0_END_RCVD_4_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_5(cp_nv_flags_0_reg, discard_5) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_5_MASK) | (discard_5 << CP_NV_FLAGS_0_DISCARD_5_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_5(cp_nv_flags_0_reg, end_rcvd_5) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_5_MASK) | (end_rcvd_5 << CP_NV_FLAGS_0_END_RCVD_5_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_6(cp_nv_flags_0_reg, discard_6) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_6_MASK) | (discard_6 << CP_NV_FLAGS_0_DISCARD_6_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_6(cp_nv_flags_0_reg, end_rcvd_6) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_6_MASK) | (end_rcvd_6 << CP_NV_FLAGS_0_END_RCVD_6_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_7(cp_nv_flags_0_reg, discard_7) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_7_MASK) | (discard_7 << CP_NV_FLAGS_0_DISCARD_7_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_7(cp_nv_flags_0_reg, end_rcvd_7) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_7_MASK) | (end_rcvd_7 << CP_NV_FLAGS_0_END_RCVD_7_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_8(cp_nv_flags_0_reg, discard_8) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_8_MASK) | (discard_8 << CP_NV_FLAGS_0_DISCARD_8_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_8(cp_nv_flags_0_reg, end_rcvd_8) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_8_MASK) | (end_rcvd_8 << CP_NV_FLAGS_0_END_RCVD_8_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_9(cp_nv_flags_0_reg, discard_9) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_9_MASK) | (discard_9 << CP_NV_FLAGS_0_DISCARD_9_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_9(cp_nv_flags_0_reg, end_rcvd_9) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_9_MASK) | (end_rcvd_9 << CP_NV_FLAGS_0_END_RCVD_9_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_10(cp_nv_flags_0_reg, discard_10) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_10_MASK) | (discard_10 << CP_NV_FLAGS_0_DISCARD_10_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_10(cp_nv_flags_0_reg, end_rcvd_10) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_10_MASK) | (end_rcvd_10 << CP_NV_FLAGS_0_END_RCVD_10_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_11(cp_nv_flags_0_reg, discard_11) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_11_MASK) | (discard_11 << CP_NV_FLAGS_0_DISCARD_11_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_11(cp_nv_flags_0_reg, end_rcvd_11) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_11_MASK) | (end_rcvd_11 << CP_NV_FLAGS_0_END_RCVD_11_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_12(cp_nv_flags_0_reg, discard_12) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_12_MASK) | (discard_12 << CP_NV_FLAGS_0_DISCARD_12_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_12(cp_nv_flags_0_reg, end_rcvd_12) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_12_MASK) | (end_rcvd_12 << CP_NV_FLAGS_0_END_RCVD_12_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_13(cp_nv_flags_0_reg, discard_13) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_13_MASK) | (discard_13 << CP_NV_FLAGS_0_DISCARD_13_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_13(cp_nv_flags_0_reg, end_rcvd_13) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_13_MASK) | (end_rcvd_13 << CP_NV_FLAGS_0_END_RCVD_13_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_14(cp_nv_flags_0_reg, discard_14) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_14_MASK) | (discard_14 << CP_NV_FLAGS_0_DISCARD_14_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_14(cp_nv_flags_0_reg, end_rcvd_14) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_14_MASK) | (end_rcvd_14 << CP_NV_FLAGS_0_END_RCVD_14_SHIFT) +#define CP_NV_FLAGS_0_SET_DISCARD_15(cp_nv_flags_0_reg, discard_15) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_DISCARD_15_MASK) | (discard_15 << CP_NV_FLAGS_0_DISCARD_15_SHIFT) +#define CP_NV_FLAGS_0_SET_END_RCVD_15(cp_nv_flags_0_reg, end_rcvd_15) \ + cp_nv_flags_0_reg = (cp_nv_flags_0_reg & ~CP_NV_FLAGS_0_END_RCVD_15_MASK) | (end_rcvd_15 << CP_NV_FLAGS_0_END_RCVD_15_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_nv_flags_0_t { + unsigned int discard_0 : CP_NV_FLAGS_0_DISCARD_0_SIZE; + unsigned int end_rcvd_0 : CP_NV_FLAGS_0_END_RCVD_0_SIZE; + unsigned int discard_1 : CP_NV_FLAGS_0_DISCARD_1_SIZE; + unsigned int end_rcvd_1 : CP_NV_FLAGS_0_END_RCVD_1_SIZE; + unsigned int discard_2 : CP_NV_FLAGS_0_DISCARD_2_SIZE; + unsigned int end_rcvd_2 : CP_NV_FLAGS_0_END_RCVD_2_SIZE; + unsigned int discard_3 : CP_NV_FLAGS_0_DISCARD_3_SIZE; + unsigned int end_rcvd_3 : CP_NV_FLAGS_0_END_RCVD_3_SIZE; + unsigned int discard_4 : CP_NV_FLAGS_0_DISCARD_4_SIZE; + unsigned int end_rcvd_4 : CP_NV_FLAGS_0_END_RCVD_4_SIZE; + unsigned int discard_5 : CP_NV_FLAGS_0_DISCARD_5_SIZE; + unsigned int end_rcvd_5 : CP_NV_FLAGS_0_END_RCVD_5_SIZE; + unsigned int discard_6 : CP_NV_FLAGS_0_DISCARD_6_SIZE; + unsigned int end_rcvd_6 : CP_NV_FLAGS_0_END_RCVD_6_SIZE; + unsigned int discard_7 : CP_NV_FLAGS_0_DISCARD_7_SIZE; + unsigned int end_rcvd_7 : CP_NV_FLAGS_0_END_RCVD_7_SIZE; + unsigned int discard_8 : CP_NV_FLAGS_0_DISCARD_8_SIZE; + unsigned int end_rcvd_8 : CP_NV_FLAGS_0_END_RCVD_8_SIZE; + unsigned int discard_9 : CP_NV_FLAGS_0_DISCARD_9_SIZE; + unsigned int end_rcvd_9 : CP_NV_FLAGS_0_END_RCVD_9_SIZE; + unsigned int discard_10 : CP_NV_FLAGS_0_DISCARD_10_SIZE; + unsigned int end_rcvd_10 : CP_NV_FLAGS_0_END_RCVD_10_SIZE; + unsigned int discard_11 : CP_NV_FLAGS_0_DISCARD_11_SIZE; + unsigned int end_rcvd_11 : CP_NV_FLAGS_0_END_RCVD_11_SIZE; + unsigned int discard_12 : CP_NV_FLAGS_0_DISCARD_12_SIZE; + unsigned int end_rcvd_12 : CP_NV_FLAGS_0_END_RCVD_12_SIZE; + unsigned int discard_13 : CP_NV_FLAGS_0_DISCARD_13_SIZE; + unsigned int end_rcvd_13 : CP_NV_FLAGS_0_END_RCVD_13_SIZE; + unsigned int discard_14 : CP_NV_FLAGS_0_DISCARD_14_SIZE; + unsigned int end_rcvd_14 : CP_NV_FLAGS_0_END_RCVD_14_SIZE; + unsigned int discard_15 : CP_NV_FLAGS_0_DISCARD_15_SIZE; + unsigned int end_rcvd_15 : CP_NV_FLAGS_0_END_RCVD_15_SIZE; + } cp_nv_flags_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_nv_flags_0_t { + unsigned int end_rcvd_15 : CP_NV_FLAGS_0_END_RCVD_15_SIZE; + unsigned int discard_15 : CP_NV_FLAGS_0_DISCARD_15_SIZE; + unsigned int end_rcvd_14 : CP_NV_FLAGS_0_END_RCVD_14_SIZE; + unsigned int discard_14 : CP_NV_FLAGS_0_DISCARD_14_SIZE; + unsigned int end_rcvd_13 : CP_NV_FLAGS_0_END_RCVD_13_SIZE; + unsigned int discard_13 : CP_NV_FLAGS_0_DISCARD_13_SIZE; + unsigned int end_rcvd_12 : CP_NV_FLAGS_0_END_RCVD_12_SIZE; + unsigned int discard_12 : CP_NV_FLAGS_0_DISCARD_12_SIZE; + unsigned int end_rcvd_11 : CP_NV_FLAGS_0_END_RCVD_11_SIZE; + unsigned int discard_11 : CP_NV_FLAGS_0_DISCARD_11_SIZE; + unsigned int end_rcvd_10 : CP_NV_FLAGS_0_END_RCVD_10_SIZE; + unsigned int discard_10 : CP_NV_FLAGS_0_DISCARD_10_SIZE; + unsigned int end_rcvd_9 : CP_NV_FLAGS_0_END_RCVD_9_SIZE; + unsigned int discard_9 : CP_NV_FLAGS_0_DISCARD_9_SIZE; + unsigned int end_rcvd_8 : CP_NV_FLAGS_0_END_RCVD_8_SIZE; + unsigned int discard_8 : CP_NV_FLAGS_0_DISCARD_8_SIZE; + unsigned int end_rcvd_7 : CP_NV_FLAGS_0_END_RCVD_7_SIZE; + unsigned int discard_7 : CP_NV_FLAGS_0_DISCARD_7_SIZE; + unsigned int end_rcvd_6 : CP_NV_FLAGS_0_END_RCVD_6_SIZE; + unsigned int discard_6 : CP_NV_FLAGS_0_DISCARD_6_SIZE; + unsigned int end_rcvd_5 : CP_NV_FLAGS_0_END_RCVD_5_SIZE; + unsigned int discard_5 : CP_NV_FLAGS_0_DISCARD_5_SIZE; + unsigned int end_rcvd_4 : CP_NV_FLAGS_0_END_RCVD_4_SIZE; + unsigned int discard_4 : CP_NV_FLAGS_0_DISCARD_4_SIZE; + unsigned int end_rcvd_3 : CP_NV_FLAGS_0_END_RCVD_3_SIZE; + unsigned int discard_3 : CP_NV_FLAGS_0_DISCARD_3_SIZE; + unsigned int end_rcvd_2 : CP_NV_FLAGS_0_END_RCVD_2_SIZE; + unsigned int discard_2 : CP_NV_FLAGS_0_DISCARD_2_SIZE; + unsigned int end_rcvd_1 : CP_NV_FLAGS_0_END_RCVD_1_SIZE; + unsigned int discard_1 : CP_NV_FLAGS_0_DISCARD_1_SIZE; + unsigned int end_rcvd_0 : CP_NV_FLAGS_0_END_RCVD_0_SIZE; + unsigned int discard_0 : CP_NV_FLAGS_0_DISCARD_0_SIZE; + } cp_nv_flags_0_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_nv_flags_0_t f; +} cp_nv_flags_0_u; + + +/* + * CP_NV_FLAGS_1 struct + */ + +#define CP_NV_FLAGS_1_DISCARD_16_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_16_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_17_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_17_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_18_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_18_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_19_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_19_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_20_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_20_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_21_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_21_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_22_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_22_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_23_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_23_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_24_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_24_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_25_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_25_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_26_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_26_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_27_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_27_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_28_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_28_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_29_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_29_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_30_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_30_SIZE 1 +#define CP_NV_FLAGS_1_DISCARD_31_SIZE 1 +#define CP_NV_FLAGS_1_END_RCVD_31_SIZE 1 + +#define CP_NV_FLAGS_1_DISCARD_16_SHIFT 0 +#define CP_NV_FLAGS_1_END_RCVD_16_SHIFT 1 +#define CP_NV_FLAGS_1_DISCARD_17_SHIFT 2 +#define CP_NV_FLAGS_1_END_RCVD_17_SHIFT 3 +#define CP_NV_FLAGS_1_DISCARD_18_SHIFT 4 +#define CP_NV_FLAGS_1_END_RCVD_18_SHIFT 5 +#define CP_NV_FLAGS_1_DISCARD_19_SHIFT 6 +#define CP_NV_FLAGS_1_END_RCVD_19_SHIFT 7 +#define CP_NV_FLAGS_1_DISCARD_20_SHIFT 8 +#define CP_NV_FLAGS_1_END_RCVD_20_SHIFT 9 +#define CP_NV_FLAGS_1_DISCARD_21_SHIFT 10 +#define CP_NV_FLAGS_1_END_RCVD_21_SHIFT 11 +#define CP_NV_FLAGS_1_DISCARD_22_SHIFT 12 +#define CP_NV_FLAGS_1_END_RCVD_22_SHIFT 13 +#define CP_NV_FLAGS_1_DISCARD_23_SHIFT 14 +#define CP_NV_FLAGS_1_END_RCVD_23_SHIFT 15 +#define CP_NV_FLAGS_1_DISCARD_24_SHIFT 16 +#define CP_NV_FLAGS_1_END_RCVD_24_SHIFT 17 +#define CP_NV_FLAGS_1_DISCARD_25_SHIFT 18 +#define CP_NV_FLAGS_1_END_RCVD_25_SHIFT 19 +#define CP_NV_FLAGS_1_DISCARD_26_SHIFT 20 +#define CP_NV_FLAGS_1_END_RCVD_26_SHIFT 21 +#define CP_NV_FLAGS_1_DISCARD_27_SHIFT 22 +#define CP_NV_FLAGS_1_END_RCVD_27_SHIFT 23 +#define CP_NV_FLAGS_1_DISCARD_28_SHIFT 24 +#define CP_NV_FLAGS_1_END_RCVD_28_SHIFT 25 +#define CP_NV_FLAGS_1_DISCARD_29_SHIFT 26 +#define CP_NV_FLAGS_1_END_RCVD_29_SHIFT 27 +#define CP_NV_FLAGS_1_DISCARD_30_SHIFT 28 +#define CP_NV_FLAGS_1_END_RCVD_30_SHIFT 29 +#define CP_NV_FLAGS_1_DISCARD_31_SHIFT 30 +#define CP_NV_FLAGS_1_END_RCVD_31_SHIFT 31 + +#define CP_NV_FLAGS_1_DISCARD_16_MASK 0x00000001 +#define CP_NV_FLAGS_1_END_RCVD_16_MASK 0x00000002 +#define CP_NV_FLAGS_1_DISCARD_17_MASK 0x00000004 +#define CP_NV_FLAGS_1_END_RCVD_17_MASK 0x00000008 +#define CP_NV_FLAGS_1_DISCARD_18_MASK 0x00000010 +#define CP_NV_FLAGS_1_END_RCVD_18_MASK 0x00000020 +#define CP_NV_FLAGS_1_DISCARD_19_MASK 0x00000040 +#define CP_NV_FLAGS_1_END_RCVD_19_MASK 0x00000080 +#define CP_NV_FLAGS_1_DISCARD_20_MASK 0x00000100 +#define CP_NV_FLAGS_1_END_RCVD_20_MASK 0x00000200 +#define CP_NV_FLAGS_1_DISCARD_21_MASK 0x00000400 +#define CP_NV_FLAGS_1_END_RCVD_21_MASK 0x00000800 +#define CP_NV_FLAGS_1_DISCARD_22_MASK 0x00001000 +#define CP_NV_FLAGS_1_END_RCVD_22_MASK 0x00002000 +#define CP_NV_FLAGS_1_DISCARD_23_MASK 0x00004000 +#define CP_NV_FLAGS_1_END_RCVD_23_MASK 0x00008000 +#define CP_NV_FLAGS_1_DISCARD_24_MASK 0x00010000 +#define CP_NV_FLAGS_1_END_RCVD_24_MASK 0x00020000 +#define CP_NV_FLAGS_1_DISCARD_25_MASK 0x00040000 +#define CP_NV_FLAGS_1_END_RCVD_25_MASK 0x00080000 +#define CP_NV_FLAGS_1_DISCARD_26_MASK 0x00100000 +#define CP_NV_FLAGS_1_END_RCVD_26_MASK 0x00200000 +#define CP_NV_FLAGS_1_DISCARD_27_MASK 0x00400000 +#define CP_NV_FLAGS_1_END_RCVD_27_MASK 0x00800000 +#define CP_NV_FLAGS_1_DISCARD_28_MASK 0x01000000 +#define CP_NV_FLAGS_1_END_RCVD_28_MASK 0x02000000 +#define CP_NV_FLAGS_1_DISCARD_29_MASK 0x04000000 +#define CP_NV_FLAGS_1_END_RCVD_29_MASK 0x08000000 +#define CP_NV_FLAGS_1_DISCARD_30_MASK 0x10000000 +#define CP_NV_FLAGS_1_END_RCVD_30_MASK 0x20000000 +#define CP_NV_FLAGS_1_DISCARD_31_MASK 0x40000000 +#define CP_NV_FLAGS_1_END_RCVD_31_MASK 0x80000000 + +#define CP_NV_FLAGS_1_MASK \ + (CP_NV_FLAGS_1_DISCARD_16_MASK | \ + CP_NV_FLAGS_1_END_RCVD_16_MASK | \ + CP_NV_FLAGS_1_DISCARD_17_MASK | \ + CP_NV_FLAGS_1_END_RCVD_17_MASK | \ + CP_NV_FLAGS_1_DISCARD_18_MASK | \ + CP_NV_FLAGS_1_END_RCVD_18_MASK | \ + CP_NV_FLAGS_1_DISCARD_19_MASK | \ + CP_NV_FLAGS_1_END_RCVD_19_MASK | \ + CP_NV_FLAGS_1_DISCARD_20_MASK | \ + CP_NV_FLAGS_1_END_RCVD_20_MASK | \ + CP_NV_FLAGS_1_DISCARD_21_MASK | \ + CP_NV_FLAGS_1_END_RCVD_21_MASK | \ + CP_NV_FLAGS_1_DISCARD_22_MASK | \ + CP_NV_FLAGS_1_END_RCVD_22_MASK | \ + CP_NV_FLAGS_1_DISCARD_23_MASK | \ + CP_NV_FLAGS_1_END_RCVD_23_MASK | \ + CP_NV_FLAGS_1_DISCARD_24_MASK | \ + CP_NV_FLAGS_1_END_RCVD_24_MASK | \ + CP_NV_FLAGS_1_DISCARD_25_MASK | \ + CP_NV_FLAGS_1_END_RCVD_25_MASK | \ + CP_NV_FLAGS_1_DISCARD_26_MASK | \ + CP_NV_FLAGS_1_END_RCVD_26_MASK | \ + CP_NV_FLAGS_1_DISCARD_27_MASK | \ + CP_NV_FLAGS_1_END_RCVD_27_MASK | \ + CP_NV_FLAGS_1_DISCARD_28_MASK | \ + CP_NV_FLAGS_1_END_RCVD_28_MASK | \ + CP_NV_FLAGS_1_DISCARD_29_MASK | \ + CP_NV_FLAGS_1_END_RCVD_29_MASK | \ + CP_NV_FLAGS_1_DISCARD_30_MASK | \ + CP_NV_FLAGS_1_END_RCVD_30_MASK | \ + CP_NV_FLAGS_1_DISCARD_31_MASK | \ + CP_NV_FLAGS_1_END_RCVD_31_MASK) + +#define CP_NV_FLAGS_1(discard_16, end_rcvd_16, discard_17, end_rcvd_17, discard_18, end_rcvd_18, discard_19, end_rcvd_19, discard_20, end_rcvd_20, discard_21, end_rcvd_21, discard_22, end_rcvd_22, discard_23, end_rcvd_23, discard_24, end_rcvd_24, discard_25, end_rcvd_25, discard_26, end_rcvd_26, discard_27, end_rcvd_27, discard_28, end_rcvd_28, discard_29, end_rcvd_29, discard_30, end_rcvd_30, discard_31, end_rcvd_31) \ + ((discard_16 << CP_NV_FLAGS_1_DISCARD_16_SHIFT) | \ + (end_rcvd_16 << CP_NV_FLAGS_1_END_RCVD_16_SHIFT) | \ + (discard_17 << CP_NV_FLAGS_1_DISCARD_17_SHIFT) | \ + (end_rcvd_17 << CP_NV_FLAGS_1_END_RCVD_17_SHIFT) | \ + (discard_18 << CP_NV_FLAGS_1_DISCARD_18_SHIFT) | \ + (end_rcvd_18 << CP_NV_FLAGS_1_END_RCVD_18_SHIFT) | \ + (discard_19 << CP_NV_FLAGS_1_DISCARD_19_SHIFT) | \ + (end_rcvd_19 << CP_NV_FLAGS_1_END_RCVD_19_SHIFT) | \ + (discard_20 << CP_NV_FLAGS_1_DISCARD_20_SHIFT) | \ + (end_rcvd_20 << CP_NV_FLAGS_1_END_RCVD_20_SHIFT) | \ + (discard_21 << CP_NV_FLAGS_1_DISCARD_21_SHIFT) | \ + (end_rcvd_21 << CP_NV_FLAGS_1_END_RCVD_21_SHIFT) | \ + (discard_22 << CP_NV_FLAGS_1_DISCARD_22_SHIFT) | \ + (end_rcvd_22 << CP_NV_FLAGS_1_END_RCVD_22_SHIFT) | \ + (discard_23 << CP_NV_FLAGS_1_DISCARD_23_SHIFT) | \ + (end_rcvd_23 << CP_NV_FLAGS_1_END_RCVD_23_SHIFT) | \ + (discard_24 << CP_NV_FLAGS_1_DISCARD_24_SHIFT) | \ + (end_rcvd_24 << CP_NV_FLAGS_1_END_RCVD_24_SHIFT) | \ + (discard_25 << CP_NV_FLAGS_1_DISCARD_25_SHIFT) | \ + (end_rcvd_25 << CP_NV_FLAGS_1_END_RCVD_25_SHIFT) | \ + (discard_26 << CP_NV_FLAGS_1_DISCARD_26_SHIFT) | \ + (end_rcvd_26 << CP_NV_FLAGS_1_END_RCVD_26_SHIFT) | \ + (discard_27 << CP_NV_FLAGS_1_DISCARD_27_SHIFT) | \ + (end_rcvd_27 << CP_NV_FLAGS_1_END_RCVD_27_SHIFT) | \ + (discard_28 << CP_NV_FLAGS_1_DISCARD_28_SHIFT) | \ + (end_rcvd_28 << CP_NV_FLAGS_1_END_RCVD_28_SHIFT) | \ + (discard_29 << CP_NV_FLAGS_1_DISCARD_29_SHIFT) | \ + (end_rcvd_29 << CP_NV_FLAGS_1_END_RCVD_29_SHIFT) | \ + (discard_30 << CP_NV_FLAGS_1_DISCARD_30_SHIFT) | \ + (end_rcvd_30 << CP_NV_FLAGS_1_END_RCVD_30_SHIFT) | \ + (discard_31 << CP_NV_FLAGS_1_DISCARD_31_SHIFT) | \ + (end_rcvd_31 << CP_NV_FLAGS_1_END_RCVD_31_SHIFT)) + +#define CP_NV_FLAGS_1_GET_DISCARD_16(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_16_MASK) >> CP_NV_FLAGS_1_DISCARD_16_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_16(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_16_MASK) >> CP_NV_FLAGS_1_END_RCVD_16_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_17(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_17_MASK) >> CP_NV_FLAGS_1_DISCARD_17_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_17(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_17_MASK) >> CP_NV_FLAGS_1_END_RCVD_17_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_18(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_18_MASK) >> CP_NV_FLAGS_1_DISCARD_18_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_18(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_18_MASK) >> CP_NV_FLAGS_1_END_RCVD_18_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_19(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_19_MASK) >> CP_NV_FLAGS_1_DISCARD_19_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_19(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_19_MASK) >> CP_NV_FLAGS_1_END_RCVD_19_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_20(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_20_MASK) >> CP_NV_FLAGS_1_DISCARD_20_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_20(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_20_MASK) >> CP_NV_FLAGS_1_END_RCVD_20_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_21(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_21_MASK) >> CP_NV_FLAGS_1_DISCARD_21_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_21(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_21_MASK) >> CP_NV_FLAGS_1_END_RCVD_21_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_22(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_22_MASK) >> CP_NV_FLAGS_1_DISCARD_22_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_22(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_22_MASK) >> CP_NV_FLAGS_1_END_RCVD_22_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_23(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_23_MASK) >> CP_NV_FLAGS_1_DISCARD_23_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_23(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_23_MASK) >> CP_NV_FLAGS_1_END_RCVD_23_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_24(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_24_MASK) >> CP_NV_FLAGS_1_DISCARD_24_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_24(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_24_MASK) >> CP_NV_FLAGS_1_END_RCVD_24_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_25(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_25_MASK) >> CP_NV_FLAGS_1_DISCARD_25_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_25(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_25_MASK) >> CP_NV_FLAGS_1_END_RCVD_25_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_26(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_26_MASK) >> CP_NV_FLAGS_1_DISCARD_26_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_26(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_26_MASK) >> CP_NV_FLAGS_1_END_RCVD_26_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_27(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_27_MASK) >> CP_NV_FLAGS_1_DISCARD_27_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_27(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_27_MASK) >> CP_NV_FLAGS_1_END_RCVD_27_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_28(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_28_MASK) >> CP_NV_FLAGS_1_DISCARD_28_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_28(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_28_MASK) >> CP_NV_FLAGS_1_END_RCVD_28_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_29(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_29_MASK) >> CP_NV_FLAGS_1_DISCARD_29_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_29(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_29_MASK) >> CP_NV_FLAGS_1_END_RCVD_29_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_30(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_30_MASK) >> CP_NV_FLAGS_1_DISCARD_30_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_30(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_30_MASK) >> CP_NV_FLAGS_1_END_RCVD_30_SHIFT) +#define CP_NV_FLAGS_1_GET_DISCARD_31(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_DISCARD_31_MASK) >> CP_NV_FLAGS_1_DISCARD_31_SHIFT) +#define CP_NV_FLAGS_1_GET_END_RCVD_31(cp_nv_flags_1) \ + ((cp_nv_flags_1 & CP_NV_FLAGS_1_END_RCVD_31_MASK) >> CP_NV_FLAGS_1_END_RCVD_31_SHIFT) + +#define CP_NV_FLAGS_1_SET_DISCARD_16(cp_nv_flags_1_reg, discard_16) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_16_MASK) | (discard_16 << CP_NV_FLAGS_1_DISCARD_16_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_16(cp_nv_flags_1_reg, end_rcvd_16) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_16_MASK) | (end_rcvd_16 << CP_NV_FLAGS_1_END_RCVD_16_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_17(cp_nv_flags_1_reg, discard_17) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_17_MASK) | (discard_17 << CP_NV_FLAGS_1_DISCARD_17_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_17(cp_nv_flags_1_reg, end_rcvd_17) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_17_MASK) | (end_rcvd_17 << CP_NV_FLAGS_1_END_RCVD_17_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_18(cp_nv_flags_1_reg, discard_18) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_18_MASK) | (discard_18 << CP_NV_FLAGS_1_DISCARD_18_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_18(cp_nv_flags_1_reg, end_rcvd_18) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_18_MASK) | (end_rcvd_18 << CP_NV_FLAGS_1_END_RCVD_18_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_19(cp_nv_flags_1_reg, discard_19) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_19_MASK) | (discard_19 << CP_NV_FLAGS_1_DISCARD_19_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_19(cp_nv_flags_1_reg, end_rcvd_19) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_19_MASK) | (end_rcvd_19 << CP_NV_FLAGS_1_END_RCVD_19_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_20(cp_nv_flags_1_reg, discard_20) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_20_MASK) | (discard_20 << CP_NV_FLAGS_1_DISCARD_20_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_20(cp_nv_flags_1_reg, end_rcvd_20) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_20_MASK) | (end_rcvd_20 << CP_NV_FLAGS_1_END_RCVD_20_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_21(cp_nv_flags_1_reg, discard_21) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_21_MASK) | (discard_21 << CP_NV_FLAGS_1_DISCARD_21_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_21(cp_nv_flags_1_reg, end_rcvd_21) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_21_MASK) | (end_rcvd_21 << CP_NV_FLAGS_1_END_RCVD_21_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_22(cp_nv_flags_1_reg, discard_22) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_22_MASK) | (discard_22 << CP_NV_FLAGS_1_DISCARD_22_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_22(cp_nv_flags_1_reg, end_rcvd_22) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_22_MASK) | (end_rcvd_22 << CP_NV_FLAGS_1_END_RCVD_22_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_23(cp_nv_flags_1_reg, discard_23) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_23_MASK) | (discard_23 << CP_NV_FLAGS_1_DISCARD_23_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_23(cp_nv_flags_1_reg, end_rcvd_23) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_23_MASK) | (end_rcvd_23 << CP_NV_FLAGS_1_END_RCVD_23_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_24(cp_nv_flags_1_reg, discard_24) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_24_MASK) | (discard_24 << CP_NV_FLAGS_1_DISCARD_24_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_24(cp_nv_flags_1_reg, end_rcvd_24) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_24_MASK) | (end_rcvd_24 << CP_NV_FLAGS_1_END_RCVD_24_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_25(cp_nv_flags_1_reg, discard_25) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_25_MASK) | (discard_25 << CP_NV_FLAGS_1_DISCARD_25_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_25(cp_nv_flags_1_reg, end_rcvd_25) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_25_MASK) | (end_rcvd_25 << CP_NV_FLAGS_1_END_RCVD_25_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_26(cp_nv_flags_1_reg, discard_26) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_26_MASK) | (discard_26 << CP_NV_FLAGS_1_DISCARD_26_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_26(cp_nv_flags_1_reg, end_rcvd_26) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_26_MASK) | (end_rcvd_26 << CP_NV_FLAGS_1_END_RCVD_26_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_27(cp_nv_flags_1_reg, discard_27) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_27_MASK) | (discard_27 << CP_NV_FLAGS_1_DISCARD_27_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_27(cp_nv_flags_1_reg, end_rcvd_27) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_27_MASK) | (end_rcvd_27 << CP_NV_FLAGS_1_END_RCVD_27_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_28(cp_nv_flags_1_reg, discard_28) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_28_MASK) | (discard_28 << CP_NV_FLAGS_1_DISCARD_28_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_28(cp_nv_flags_1_reg, end_rcvd_28) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_28_MASK) | (end_rcvd_28 << CP_NV_FLAGS_1_END_RCVD_28_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_29(cp_nv_flags_1_reg, discard_29) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_29_MASK) | (discard_29 << CP_NV_FLAGS_1_DISCARD_29_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_29(cp_nv_flags_1_reg, end_rcvd_29) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_29_MASK) | (end_rcvd_29 << CP_NV_FLAGS_1_END_RCVD_29_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_30(cp_nv_flags_1_reg, discard_30) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_30_MASK) | (discard_30 << CP_NV_FLAGS_1_DISCARD_30_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_30(cp_nv_flags_1_reg, end_rcvd_30) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_30_MASK) | (end_rcvd_30 << CP_NV_FLAGS_1_END_RCVD_30_SHIFT) +#define CP_NV_FLAGS_1_SET_DISCARD_31(cp_nv_flags_1_reg, discard_31) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_DISCARD_31_MASK) | (discard_31 << CP_NV_FLAGS_1_DISCARD_31_SHIFT) +#define CP_NV_FLAGS_1_SET_END_RCVD_31(cp_nv_flags_1_reg, end_rcvd_31) \ + cp_nv_flags_1_reg = (cp_nv_flags_1_reg & ~CP_NV_FLAGS_1_END_RCVD_31_MASK) | (end_rcvd_31 << CP_NV_FLAGS_1_END_RCVD_31_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_nv_flags_1_t { + unsigned int discard_16 : CP_NV_FLAGS_1_DISCARD_16_SIZE; + unsigned int end_rcvd_16 : CP_NV_FLAGS_1_END_RCVD_16_SIZE; + unsigned int discard_17 : CP_NV_FLAGS_1_DISCARD_17_SIZE; + unsigned int end_rcvd_17 : CP_NV_FLAGS_1_END_RCVD_17_SIZE; + unsigned int discard_18 : CP_NV_FLAGS_1_DISCARD_18_SIZE; + unsigned int end_rcvd_18 : CP_NV_FLAGS_1_END_RCVD_18_SIZE; + unsigned int discard_19 : CP_NV_FLAGS_1_DISCARD_19_SIZE; + unsigned int end_rcvd_19 : CP_NV_FLAGS_1_END_RCVD_19_SIZE; + unsigned int discard_20 : CP_NV_FLAGS_1_DISCARD_20_SIZE; + unsigned int end_rcvd_20 : CP_NV_FLAGS_1_END_RCVD_20_SIZE; + unsigned int discard_21 : CP_NV_FLAGS_1_DISCARD_21_SIZE; + unsigned int end_rcvd_21 : CP_NV_FLAGS_1_END_RCVD_21_SIZE; + unsigned int discard_22 : CP_NV_FLAGS_1_DISCARD_22_SIZE; + unsigned int end_rcvd_22 : CP_NV_FLAGS_1_END_RCVD_22_SIZE; + unsigned int discard_23 : CP_NV_FLAGS_1_DISCARD_23_SIZE; + unsigned int end_rcvd_23 : CP_NV_FLAGS_1_END_RCVD_23_SIZE; + unsigned int discard_24 : CP_NV_FLAGS_1_DISCARD_24_SIZE; + unsigned int end_rcvd_24 : CP_NV_FLAGS_1_END_RCVD_24_SIZE; + unsigned int discard_25 : CP_NV_FLAGS_1_DISCARD_25_SIZE; + unsigned int end_rcvd_25 : CP_NV_FLAGS_1_END_RCVD_25_SIZE; + unsigned int discard_26 : CP_NV_FLAGS_1_DISCARD_26_SIZE; + unsigned int end_rcvd_26 : CP_NV_FLAGS_1_END_RCVD_26_SIZE; + unsigned int discard_27 : CP_NV_FLAGS_1_DISCARD_27_SIZE; + unsigned int end_rcvd_27 : CP_NV_FLAGS_1_END_RCVD_27_SIZE; + unsigned int discard_28 : CP_NV_FLAGS_1_DISCARD_28_SIZE; + unsigned int end_rcvd_28 : CP_NV_FLAGS_1_END_RCVD_28_SIZE; + unsigned int discard_29 : CP_NV_FLAGS_1_DISCARD_29_SIZE; + unsigned int end_rcvd_29 : CP_NV_FLAGS_1_END_RCVD_29_SIZE; + unsigned int discard_30 : CP_NV_FLAGS_1_DISCARD_30_SIZE; + unsigned int end_rcvd_30 : CP_NV_FLAGS_1_END_RCVD_30_SIZE; + unsigned int discard_31 : CP_NV_FLAGS_1_DISCARD_31_SIZE; + unsigned int end_rcvd_31 : CP_NV_FLAGS_1_END_RCVD_31_SIZE; + } cp_nv_flags_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_nv_flags_1_t { + unsigned int end_rcvd_31 : CP_NV_FLAGS_1_END_RCVD_31_SIZE; + unsigned int discard_31 : CP_NV_FLAGS_1_DISCARD_31_SIZE; + unsigned int end_rcvd_30 : CP_NV_FLAGS_1_END_RCVD_30_SIZE; + unsigned int discard_30 : CP_NV_FLAGS_1_DISCARD_30_SIZE; + unsigned int end_rcvd_29 : CP_NV_FLAGS_1_END_RCVD_29_SIZE; + unsigned int discard_29 : CP_NV_FLAGS_1_DISCARD_29_SIZE; + unsigned int end_rcvd_28 : CP_NV_FLAGS_1_END_RCVD_28_SIZE; + unsigned int discard_28 : CP_NV_FLAGS_1_DISCARD_28_SIZE; + unsigned int end_rcvd_27 : CP_NV_FLAGS_1_END_RCVD_27_SIZE; + unsigned int discard_27 : CP_NV_FLAGS_1_DISCARD_27_SIZE; + unsigned int end_rcvd_26 : CP_NV_FLAGS_1_END_RCVD_26_SIZE; + unsigned int discard_26 : CP_NV_FLAGS_1_DISCARD_26_SIZE; + unsigned int end_rcvd_25 : CP_NV_FLAGS_1_END_RCVD_25_SIZE; + unsigned int discard_25 : CP_NV_FLAGS_1_DISCARD_25_SIZE; + unsigned int end_rcvd_24 : CP_NV_FLAGS_1_END_RCVD_24_SIZE; + unsigned int discard_24 : CP_NV_FLAGS_1_DISCARD_24_SIZE; + unsigned int end_rcvd_23 : CP_NV_FLAGS_1_END_RCVD_23_SIZE; + unsigned int discard_23 : CP_NV_FLAGS_1_DISCARD_23_SIZE; + unsigned int end_rcvd_22 : CP_NV_FLAGS_1_END_RCVD_22_SIZE; + unsigned int discard_22 : CP_NV_FLAGS_1_DISCARD_22_SIZE; + unsigned int end_rcvd_21 : CP_NV_FLAGS_1_END_RCVD_21_SIZE; + unsigned int discard_21 : CP_NV_FLAGS_1_DISCARD_21_SIZE; + unsigned int end_rcvd_20 : CP_NV_FLAGS_1_END_RCVD_20_SIZE; + unsigned int discard_20 : CP_NV_FLAGS_1_DISCARD_20_SIZE; + unsigned int end_rcvd_19 : CP_NV_FLAGS_1_END_RCVD_19_SIZE; + unsigned int discard_19 : CP_NV_FLAGS_1_DISCARD_19_SIZE; + unsigned int end_rcvd_18 : CP_NV_FLAGS_1_END_RCVD_18_SIZE; + unsigned int discard_18 : CP_NV_FLAGS_1_DISCARD_18_SIZE; + unsigned int end_rcvd_17 : CP_NV_FLAGS_1_END_RCVD_17_SIZE; + unsigned int discard_17 : CP_NV_FLAGS_1_DISCARD_17_SIZE; + unsigned int end_rcvd_16 : CP_NV_FLAGS_1_END_RCVD_16_SIZE; + unsigned int discard_16 : CP_NV_FLAGS_1_DISCARD_16_SIZE; + } cp_nv_flags_1_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_nv_flags_1_t f; +} cp_nv_flags_1_u; + + +/* + * CP_NV_FLAGS_2 struct + */ + +#define CP_NV_FLAGS_2_DISCARD_32_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_32_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_33_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_33_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_34_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_34_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_35_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_35_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_36_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_36_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_37_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_37_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_38_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_38_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_39_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_39_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_40_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_40_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_41_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_41_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_42_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_42_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_43_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_43_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_44_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_44_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_45_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_45_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_46_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_46_SIZE 1 +#define CP_NV_FLAGS_2_DISCARD_47_SIZE 1 +#define CP_NV_FLAGS_2_END_RCVD_47_SIZE 1 + +#define CP_NV_FLAGS_2_DISCARD_32_SHIFT 0 +#define CP_NV_FLAGS_2_END_RCVD_32_SHIFT 1 +#define CP_NV_FLAGS_2_DISCARD_33_SHIFT 2 +#define CP_NV_FLAGS_2_END_RCVD_33_SHIFT 3 +#define CP_NV_FLAGS_2_DISCARD_34_SHIFT 4 +#define CP_NV_FLAGS_2_END_RCVD_34_SHIFT 5 +#define CP_NV_FLAGS_2_DISCARD_35_SHIFT 6 +#define CP_NV_FLAGS_2_END_RCVD_35_SHIFT 7 +#define CP_NV_FLAGS_2_DISCARD_36_SHIFT 8 +#define CP_NV_FLAGS_2_END_RCVD_36_SHIFT 9 +#define CP_NV_FLAGS_2_DISCARD_37_SHIFT 10 +#define CP_NV_FLAGS_2_END_RCVD_37_SHIFT 11 +#define CP_NV_FLAGS_2_DISCARD_38_SHIFT 12 +#define CP_NV_FLAGS_2_END_RCVD_38_SHIFT 13 +#define CP_NV_FLAGS_2_DISCARD_39_SHIFT 14 +#define CP_NV_FLAGS_2_END_RCVD_39_SHIFT 15 +#define CP_NV_FLAGS_2_DISCARD_40_SHIFT 16 +#define CP_NV_FLAGS_2_END_RCVD_40_SHIFT 17 +#define CP_NV_FLAGS_2_DISCARD_41_SHIFT 18 +#define CP_NV_FLAGS_2_END_RCVD_41_SHIFT 19 +#define CP_NV_FLAGS_2_DISCARD_42_SHIFT 20 +#define CP_NV_FLAGS_2_END_RCVD_42_SHIFT 21 +#define CP_NV_FLAGS_2_DISCARD_43_SHIFT 22 +#define CP_NV_FLAGS_2_END_RCVD_43_SHIFT 23 +#define CP_NV_FLAGS_2_DISCARD_44_SHIFT 24 +#define CP_NV_FLAGS_2_END_RCVD_44_SHIFT 25 +#define CP_NV_FLAGS_2_DISCARD_45_SHIFT 26 +#define CP_NV_FLAGS_2_END_RCVD_45_SHIFT 27 +#define CP_NV_FLAGS_2_DISCARD_46_SHIFT 28 +#define CP_NV_FLAGS_2_END_RCVD_46_SHIFT 29 +#define CP_NV_FLAGS_2_DISCARD_47_SHIFT 30 +#define CP_NV_FLAGS_2_END_RCVD_47_SHIFT 31 + +#define CP_NV_FLAGS_2_DISCARD_32_MASK 0x00000001 +#define CP_NV_FLAGS_2_END_RCVD_32_MASK 0x00000002 +#define CP_NV_FLAGS_2_DISCARD_33_MASK 0x00000004 +#define CP_NV_FLAGS_2_END_RCVD_33_MASK 0x00000008 +#define CP_NV_FLAGS_2_DISCARD_34_MASK 0x00000010 +#define CP_NV_FLAGS_2_END_RCVD_34_MASK 0x00000020 +#define CP_NV_FLAGS_2_DISCARD_35_MASK 0x00000040 +#define CP_NV_FLAGS_2_END_RCVD_35_MASK 0x00000080 +#define CP_NV_FLAGS_2_DISCARD_36_MASK 0x00000100 +#define CP_NV_FLAGS_2_END_RCVD_36_MASK 0x00000200 +#define CP_NV_FLAGS_2_DISCARD_37_MASK 0x00000400 +#define CP_NV_FLAGS_2_END_RCVD_37_MASK 0x00000800 +#define CP_NV_FLAGS_2_DISCARD_38_MASK 0x00001000 +#define CP_NV_FLAGS_2_END_RCVD_38_MASK 0x00002000 +#define CP_NV_FLAGS_2_DISCARD_39_MASK 0x00004000 +#define CP_NV_FLAGS_2_END_RCVD_39_MASK 0x00008000 +#define CP_NV_FLAGS_2_DISCARD_40_MASK 0x00010000 +#define CP_NV_FLAGS_2_END_RCVD_40_MASK 0x00020000 +#define CP_NV_FLAGS_2_DISCARD_41_MASK 0x00040000 +#define CP_NV_FLAGS_2_END_RCVD_41_MASK 0x00080000 +#define CP_NV_FLAGS_2_DISCARD_42_MASK 0x00100000 +#define CP_NV_FLAGS_2_END_RCVD_42_MASK 0x00200000 +#define CP_NV_FLAGS_2_DISCARD_43_MASK 0x00400000 +#define CP_NV_FLAGS_2_END_RCVD_43_MASK 0x00800000 +#define CP_NV_FLAGS_2_DISCARD_44_MASK 0x01000000 +#define CP_NV_FLAGS_2_END_RCVD_44_MASK 0x02000000 +#define CP_NV_FLAGS_2_DISCARD_45_MASK 0x04000000 +#define CP_NV_FLAGS_2_END_RCVD_45_MASK 0x08000000 +#define CP_NV_FLAGS_2_DISCARD_46_MASK 0x10000000 +#define CP_NV_FLAGS_2_END_RCVD_46_MASK 0x20000000 +#define CP_NV_FLAGS_2_DISCARD_47_MASK 0x40000000 +#define CP_NV_FLAGS_2_END_RCVD_47_MASK 0x80000000 + +#define CP_NV_FLAGS_2_MASK \ + (CP_NV_FLAGS_2_DISCARD_32_MASK | \ + CP_NV_FLAGS_2_END_RCVD_32_MASK | \ + CP_NV_FLAGS_2_DISCARD_33_MASK | \ + CP_NV_FLAGS_2_END_RCVD_33_MASK | \ + CP_NV_FLAGS_2_DISCARD_34_MASK | \ + CP_NV_FLAGS_2_END_RCVD_34_MASK | \ + CP_NV_FLAGS_2_DISCARD_35_MASK | \ + CP_NV_FLAGS_2_END_RCVD_35_MASK | \ + CP_NV_FLAGS_2_DISCARD_36_MASK | \ + CP_NV_FLAGS_2_END_RCVD_36_MASK | \ + CP_NV_FLAGS_2_DISCARD_37_MASK | \ + CP_NV_FLAGS_2_END_RCVD_37_MASK | \ + CP_NV_FLAGS_2_DISCARD_38_MASK | \ + CP_NV_FLAGS_2_END_RCVD_38_MASK | \ + CP_NV_FLAGS_2_DISCARD_39_MASK | \ + CP_NV_FLAGS_2_END_RCVD_39_MASK | \ + CP_NV_FLAGS_2_DISCARD_40_MASK | \ + CP_NV_FLAGS_2_END_RCVD_40_MASK | \ + CP_NV_FLAGS_2_DISCARD_41_MASK | \ + CP_NV_FLAGS_2_END_RCVD_41_MASK | \ + CP_NV_FLAGS_2_DISCARD_42_MASK | \ + CP_NV_FLAGS_2_END_RCVD_42_MASK | \ + CP_NV_FLAGS_2_DISCARD_43_MASK | \ + CP_NV_FLAGS_2_END_RCVD_43_MASK | \ + CP_NV_FLAGS_2_DISCARD_44_MASK | \ + CP_NV_FLAGS_2_END_RCVD_44_MASK | \ + CP_NV_FLAGS_2_DISCARD_45_MASK | \ + CP_NV_FLAGS_2_END_RCVD_45_MASK | \ + CP_NV_FLAGS_2_DISCARD_46_MASK | \ + CP_NV_FLAGS_2_END_RCVD_46_MASK | \ + CP_NV_FLAGS_2_DISCARD_47_MASK | \ + CP_NV_FLAGS_2_END_RCVD_47_MASK) + +#define CP_NV_FLAGS_2(discard_32, end_rcvd_32, discard_33, end_rcvd_33, discard_34, end_rcvd_34, discard_35, end_rcvd_35, discard_36, end_rcvd_36, discard_37, end_rcvd_37, discard_38, end_rcvd_38, discard_39, end_rcvd_39, discard_40, end_rcvd_40, discard_41, end_rcvd_41, discard_42, end_rcvd_42, discard_43, end_rcvd_43, discard_44, end_rcvd_44, discard_45, end_rcvd_45, discard_46, end_rcvd_46, discard_47, end_rcvd_47) \ + ((discard_32 << CP_NV_FLAGS_2_DISCARD_32_SHIFT) | \ + (end_rcvd_32 << CP_NV_FLAGS_2_END_RCVD_32_SHIFT) | \ + (discard_33 << CP_NV_FLAGS_2_DISCARD_33_SHIFT) | \ + (end_rcvd_33 << CP_NV_FLAGS_2_END_RCVD_33_SHIFT) | \ + (discard_34 << CP_NV_FLAGS_2_DISCARD_34_SHIFT) | \ + (end_rcvd_34 << CP_NV_FLAGS_2_END_RCVD_34_SHIFT) | \ + (discard_35 << CP_NV_FLAGS_2_DISCARD_35_SHIFT) | \ + (end_rcvd_35 << CP_NV_FLAGS_2_END_RCVD_35_SHIFT) | \ + (discard_36 << CP_NV_FLAGS_2_DISCARD_36_SHIFT) | \ + (end_rcvd_36 << CP_NV_FLAGS_2_END_RCVD_36_SHIFT) | \ + (discard_37 << CP_NV_FLAGS_2_DISCARD_37_SHIFT) | \ + (end_rcvd_37 << CP_NV_FLAGS_2_END_RCVD_37_SHIFT) | \ + (discard_38 << CP_NV_FLAGS_2_DISCARD_38_SHIFT) | \ + (end_rcvd_38 << CP_NV_FLAGS_2_END_RCVD_38_SHIFT) | \ + (discard_39 << CP_NV_FLAGS_2_DISCARD_39_SHIFT) | \ + (end_rcvd_39 << CP_NV_FLAGS_2_END_RCVD_39_SHIFT) | \ + (discard_40 << CP_NV_FLAGS_2_DISCARD_40_SHIFT) | \ + (end_rcvd_40 << CP_NV_FLAGS_2_END_RCVD_40_SHIFT) | \ + (discard_41 << CP_NV_FLAGS_2_DISCARD_41_SHIFT) | \ + (end_rcvd_41 << CP_NV_FLAGS_2_END_RCVD_41_SHIFT) | \ + (discard_42 << CP_NV_FLAGS_2_DISCARD_42_SHIFT) | \ + (end_rcvd_42 << CP_NV_FLAGS_2_END_RCVD_42_SHIFT) | \ + (discard_43 << CP_NV_FLAGS_2_DISCARD_43_SHIFT) | \ + (end_rcvd_43 << CP_NV_FLAGS_2_END_RCVD_43_SHIFT) | \ + (discard_44 << CP_NV_FLAGS_2_DISCARD_44_SHIFT) | \ + (end_rcvd_44 << CP_NV_FLAGS_2_END_RCVD_44_SHIFT) | \ + (discard_45 << CP_NV_FLAGS_2_DISCARD_45_SHIFT) | \ + (end_rcvd_45 << CP_NV_FLAGS_2_END_RCVD_45_SHIFT) | \ + (discard_46 << CP_NV_FLAGS_2_DISCARD_46_SHIFT) | \ + (end_rcvd_46 << CP_NV_FLAGS_2_END_RCVD_46_SHIFT) | \ + (discard_47 << CP_NV_FLAGS_2_DISCARD_47_SHIFT) | \ + (end_rcvd_47 << CP_NV_FLAGS_2_END_RCVD_47_SHIFT)) + +#define CP_NV_FLAGS_2_GET_DISCARD_32(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_32_MASK) >> CP_NV_FLAGS_2_DISCARD_32_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_32(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_32_MASK) >> CP_NV_FLAGS_2_END_RCVD_32_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_33(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_33_MASK) >> CP_NV_FLAGS_2_DISCARD_33_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_33(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_33_MASK) >> CP_NV_FLAGS_2_END_RCVD_33_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_34(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_34_MASK) >> CP_NV_FLAGS_2_DISCARD_34_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_34(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_34_MASK) >> CP_NV_FLAGS_2_END_RCVD_34_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_35(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_35_MASK) >> CP_NV_FLAGS_2_DISCARD_35_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_35(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_35_MASK) >> CP_NV_FLAGS_2_END_RCVD_35_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_36(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_36_MASK) >> CP_NV_FLAGS_2_DISCARD_36_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_36(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_36_MASK) >> CP_NV_FLAGS_2_END_RCVD_36_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_37(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_37_MASK) >> CP_NV_FLAGS_2_DISCARD_37_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_37(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_37_MASK) >> CP_NV_FLAGS_2_END_RCVD_37_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_38(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_38_MASK) >> CP_NV_FLAGS_2_DISCARD_38_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_38(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_38_MASK) >> CP_NV_FLAGS_2_END_RCVD_38_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_39(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_39_MASK) >> CP_NV_FLAGS_2_DISCARD_39_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_39(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_39_MASK) >> CP_NV_FLAGS_2_END_RCVD_39_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_40(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_40_MASK) >> CP_NV_FLAGS_2_DISCARD_40_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_40(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_40_MASK) >> CP_NV_FLAGS_2_END_RCVD_40_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_41(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_41_MASK) >> CP_NV_FLAGS_2_DISCARD_41_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_41(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_41_MASK) >> CP_NV_FLAGS_2_END_RCVD_41_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_42(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_42_MASK) >> CP_NV_FLAGS_2_DISCARD_42_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_42(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_42_MASK) >> CP_NV_FLAGS_2_END_RCVD_42_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_43(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_43_MASK) >> CP_NV_FLAGS_2_DISCARD_43_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_43(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_43_MASK) >> CP_NV_FLAGS_2_END_RCVD_43_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_44(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_44_MASK) >> CP_NV_FLAGS_2_DISCARD_44_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_44(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_44_MASK) >> CP_NV_FLAGS_2_END_RCVD_44_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_45(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_45_MASK) >> CP_NV_FLAGS_2_DISCARD_45_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_45(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_45_MASK) >> CP_NV_FLAGS_2_END_RCVD_45_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_46(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_46_MASK) >> CP_NV_FLAGS_2_DISCARD_46_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_46(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_46_MASK) >> CP_NV_FLAGS_2_END_RCVD_46_SHIFT) +#define CP_NV_FLAGS_2_GET_DISCARD_47(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_DISCARD_47_MASK) >> CP_NV_FLAGS_2_DISCARD_47_SHIFT) +#define CP_NV_FLAGS_2_GET_END_RCVD_47(cp_nv_flags_2) \ + ((cp_nv_flags_2 & CP_NV_FLAGS_2_END_RCVD_47_MASK) >> CP_NV_FLAGS_2_END_RCVD_47_SHIFT) + +#define CP_NV_FLAGS_2_SET_DISCARD_32(cp_nv_flags_2_reg, discard_32) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_32_MASK) | (discard_32 << CP_NV_FLAGS_2_DISCARD_32_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_32(cp_nv_flags_2_reg, end_rcvd_32) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_32_MASK) | (end_rcvd_32 << CP_NV_FLAGS_2_END_RCVD_32_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_33(cp_nv_flags_2_reg, discard_33) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_33_MASK) | (discard_33 << CP_NV_FLAGS_2_DISCARD_33_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_33(cp_nv_flags_2_reg, end_rcvd_33) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_33_MASK) | (end_rcvd_33 << CP_NV_FLAGS_2_END_RCVD_33_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_34(cp_nv_flags_2_reg, discard_34) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_34_MASK) | (discard_34 << CP_NV_FLAGS_2_DISCARD_34_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_34(cp_nv_flags_2_reg, end_rcvd_34) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_34_MASK) | (end_rcvd_34 << CP_NV_FLAGS_2_END_RCVD_34_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_35(cp_nv_flags_2_reg, discard_35) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_35_MASK) | (discard_35 << CP_NV_FLAGS_2_DISCARD_35_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_35(cp_nv_flags_2_reg, end_rcvd_35) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_35_MASK) | (end_rcvd_35 << CP_NV_FLAGS_2_END_RCVD_35_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_36(cp_nv_flags_2_reg, discard_36) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_36_MASK) | (discard_36 << CP_NV_FLAGS_2_DISCARD_36_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_36(cp_nv_flags_2_reg, end_rcvd_36) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_36_MASK) | (end_rcvd_36 << CP_NV_FLAGS_2_END_RCVD_36_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_37(cp_nv_flags_2_reg, discard_37) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_37_MASK) | (discard_37 << CP_NV_FLAGS_2_DISCARD_37_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_37(cp_nv_flags_2_reg, end_rcvd_37) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_37_MASK) | (end_rcvd_37 << CP_NV_FLAGS_2_END_RCVD_37_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_38(cp_nv_flags_2_reg, discard_38) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_38_MASK) | (discard_38 << CP_NV_FLAGS_2_DISCARD_38_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_38(cp_nv_flags_2_reg, end_rcvd_38) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_38_MASK) | (end_rcvd_38 << CP_NV_FLAGS_2_END_RCVD_38_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_39(cp_nv_flags_2_reg, discard_39) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_39_MASK) | (discard_39 << CP_NV_FLAGS_2_DISCARD_39_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_39(cp_nv_flags_2_reg, end_rcvd_39) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_39_MASK) | (end_rcvd_39 << CP_NV_FLAGS_2_END_RCVD_39_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_40(cp_nv_flags_2_reg, discard_40) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_40_MASK) | (discard_40 << CP_NV_FLAGS_2_DISCARD_40_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_40(cp_nv_flags_2_reg, end_rcvd_40) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_40_MASK) | (end_rcvd_40 << CP_NV_FLAGS_2_END_RCVD_40_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_41(cp_nv_flags_2_reg, discard_41) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_41_MASK) | (discard_41 << CP_NV_FLAGS_2_DISCARD_41_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_41(cp_nv_flags_2_reg, end_rcvd_41) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_41_MASK) | (end_rcvd_41 << CP_NV_FLAGS_2_END_RCVD_41_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_42(cp_nv_flags_2_reg, discard_42) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_42_MASK) | (discard_42 << CP_NV_FLAGS_2_DISCARD_42_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_42(cp_nv_flags_2_reg, end_rcvd_42) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_42_MASK) | (end_rcvd_42 << CP_NV_FLAGS_2_END_RCVD_42_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_43(cp_nv_flags_2_reg, discard_43) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_43_MASK) | (discard_43 << CP_NV_FLAGS_2_DISCARD_43_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_43(cp_nv_flags_2_reg, end_rcvd_43) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_43_MASK) | (end_rcvd_43 << CP_NV_FLAGS_2_END_RCVD_43_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_44(cp_nv_flags_2_reg, discard_44) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_44_MASK) | (discard_44 << CP_NV_FLAGS_2_DISCARD_44_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_44(cp_nv_flags_2_reg, end_rcvd_44) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_44_MASK) | (end_rcvd_44 << CP_NV_FLAGS_2_END_RCVD_44_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_45(cp_nv_flags_2_reg, discard_45) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_45_MASK) | (discard_45 << CP_NV_FLAGS_2_DISCARD_45_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_45(cp_nv_flags_2_reg, end_rcvd_45) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_45_MASK) | (end_rcvd_45 << CP_NV_FLAGS_2_END_RCVD_45_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_46(cp_nv_flags_2_reg, discard_46) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_46_MASK) | (discard_46 << CP_NV_FLAGS_2_DISCARD_46_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_46(cp_nv_flags_2_reg, end_rcvd_46) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_46_MASK) | (end_rcvd_46 << CP_NV_FLAGS_2_END_RCVD_46_SHIFT) +#define CP_NV_FLAGS_2_SET_DISCARD_47(cp_nv_flags_2_reg, discard_47) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_DISCARD_47_MASK) | (discard_47 << CP_NV_FLAGS_2_DISCARD_47_SHIFT) +#define CP_NV_FLAGS_2_SET_END_RCVD_47(cp_nv_flags_2_reg, end_rcvd_47) \ + cp_nv_flags_2_reg = (cp_nv_flags_2_reg & ~CP_NV_FLAGS_2_END_RCVD_47_MASK) | (end_rcvd_47 << CP_NV_FLAGS_2_END_RCVD_47_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_nv_flags_2_t { + unsigned int discard_32 : CP_NV_FLAGS_2_DISCARD_32_SIZE; + unsigned int end_rcvd_32 : CP_NV_FLAGS_2_END_RCVD_32_SIZE; + unsigned int discard_33 : CP_NV_FLAGS_2_DISCARD_33_SIZE; + unsigned int end_rcvd_33 : CP_NV_FLAGS_2_END_RCVD_33_SIZE; + unsigned int discard_34 : CP_NV_FLAGS_2_DISCARD_34_SIZE; + unsigned int end_rcvd_34 : CP_NV_FLAGS_2_END_RCVD_34_SIZE; + unsigned int discard_35 : CP_NV_FLAGS_2_DISCARD_35_SIZE; + unsigned int end_rcvd_35 : CP_NV_FLAGS_2_END_RCVD_35_SIZE; + unsigned int discard_36 : CP_NV_FLAGS_2_DISCARD_36_SIZE; + unsigned int end_rcvd_36 : CP_NV_FLAGS_2_END_RCVD_36_SIZE; + unsigned int discard_37 : CP_NV_FLAGS_2_DISCARD_37_SIZE; + unsigned int end_rcvd_37 : CP_NV_FLAGS_2_END_RCVD_37_SIZE; + unsigned int discard_38 : CP_NV_FLAGS_2_DISCARD_38_SIZE; + unsigned int end_rcvd_38 : CP_NV_FLAGS_2_END_RCVD_38_SIZE; + unsigned int discard_39 : CP_NV_FLAGS_2_DISCARD_39_SIZE; + unsigned int end_rcvd_39 : CP_NV_FLAGS_2_END_RCVD_39_SIZE; + unsigned int discard_40 : CP_NV_FLAGS_2_DISCARD_40_SIZE; + unsigned int end_rcvd_40 : CP_NV_FLAGS_2_END_RCVD_40_SIZE; + unsigned int discard_41 : CP_NV_FLAGS_2_DISCARD_41_SIZE; + unsigned int end_rcvd_41 : CP_NV_FLAGS_2_END_RCVD_41_SIZE; + unsigned int discard_42 : CP_NV_FLAGS_2_DISCARD_42_SIZE; + unsigned int end_rcvd_42 : CP_NV_FLAGS_2_END_RCVD_42_SIZE; + unsigned int discard_43 : CP_NV_FLAGS_2_DISCARD_43_SIZE; + unsigned int end_rcvd_43 : CP_NV_FLAGS_2_END_RCVD_43_SIZE; + unsigned int discard_44 : CP_NV_FLAGS_2_DISCARD_44_SIZE; + unsigned int end_rcvd_44 : CP_NV_FLAGS_2_END_RCVD_44_SIZE; + unsigned int discard_45 : CP_NV_FLAGS_2_DISCARD_45_SIZE; + unsigned int end_rcvd_45 : CP_NV_FLAGS_2_END_RCVD_45_SIZE; + unsigned int discard_46 : CP_NV_FLAGS_2_DISCARD_46_SIZE; + unsigned int end_rcvd_46 : CP_NV_FLAGS_2_END_RCVD_46_SIZE; + unsigned int discard_47 : CP_NV_FLAGS_2_DISCARD_47_SIZE; + unsigned int end_rcvd_47 : CP_NV_FLAGS_2_END_RCVD_47_SIZE; + } cp_nv_flags_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_nv_flags_2_t { + unsigned int end_rcvd_47 : CP_NV_FLAGS_2_END_RCVD_47_SIZE; + unsigned int discard_47 : CP_NV_FLAGS_2_DISCARD_47_SIZE; + unsigned int end_rcvd_46 : CP_NV_FLAGS_2_END_RCVD_46_SIZE; + unsigned int discard_46 : CP_NV_FLAGS_2_DISCARD_46_SIZE; + unsigned int end_rcvd_45 : CP_NV_FLAGS_2_END_RCVD_45_SIZE; + unsigned int discard_45 : CP_NV_FLAGS_2_DISCARD_45_SIZE; + unsigned int end_rcvd_44 : CP_NV_FLAGS_2_END_RCVD_44_SIZE; + unsigned int discard_44 : CP_NV_FLAGS_2_DISCARD_44_SIZE; + unsigned int end_rcvd_43 : CP_NV_FLAGS_2_END_RCVD_43_SIZE; + unsigned int discard_43 : CP_NV_FLAGS_2_DISCARD_43_SIZE; + unsigned int end_rcvd_42 : CP_NV_FLAGS_2_END_RCVD_42_SIZE; + unsigned int discard_42 : CP_NV_FLAGS_2_DISCARD_42_SIZE; + unsigned int end_rcvd_41 : CP_NV_FLAGS_2_END_RCVD_41_SIZE; + unsigned int discard_41 : CP_NV_FLAGS_2_DISCARD_41_SIZE; + unsigned int end_rcvd_40 : CP_NV_FLAGS_2_END_RCVD_40_SIZE; + unsigned int discard_40 : CP_NV_FLAGS_2_DISCARD_40_SIZE; + unsigned int end_rcvd_39 : CP_NV_FLAGS_2_END_RCVD_39_SIZE; + unsigned int discard_39 : CP_NV_FLAGS_2_DISCARD_39_SIZE; + unsigned int end_rcvd_38 : CP_NV_FLAGS_2_END_RCVD_38_SIZE; + unsigned int discard_38 : CP_NV_FLAGS_2_DISCARD_38_SIZE; + unsigned int end_rcvd_37 : CP_NV_FLAGS_2_END_RCVD_37_SIZE; + unsigned int discard_37 : CP_NV_FLAGS_2_DISCARD_37_SIZE; + unsigned int end_rcvd_36 : CP_NV_FLAGS_2_END_RCVD_36_SIZE; + unsigned int discard_36 : CP_NV_FLAGS_2_DISCARD_36_SIZE; + unsigned int end_rcvd_35 : CP_NV_FLAGS_2_END_RCVD_35_SIZE; + unsigned int discard_35 : CP_NV_FLAGS_2_DISCARD_35_SIZE; + unsigned int end_rcvd_34 : CP_NV_FLAGS_2_END_RCVD_34_SIZE; + unsigned int discard_34 : CP_NV_FLAGS_2_DISCARD_34_SIZE; + unsigned int end_rcvd_33 : CP_NV_FLAGS_2_END_RCVD_33_SIZE; + unsigned int discard_33 : CP_NV_FLAGS_2_DISCARD_33_SIZE; + unsigned int end_rcvd_32 : CP_NV_FLAGS_2_END_RCVD_32_SIZE; + unsigned int discard_32 : CP_NV_FLAGS_2_DISCARD_32_SIZE; + } cp_nv_flags_2_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_nv_flags_2_t f; +} cp_nv_flags_2_u; + + +/* + * CP_NV_FLAGS_3 struct + */ + +#define CP_NV_FLAGS_3_DISCARD_48_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_48_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_49_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_49_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_50_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_50_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_51_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_51_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_52_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_52_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_53_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_53_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_54_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_54_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_55_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_55_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_56_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_56_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_57_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_57_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_58_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_58_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_59_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_59_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_60_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_60_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_61_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_61_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_62_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_62_SIZE 1 +#define CP_NV_FLAGS_3_DISCARD_63_SIZE 1 +#define CP_NV_FLAGS_3_END_RCVD_63_SIZE 1 + +#define CP_NV_FLAGS_3_DISCARD_48_SHIFT 0 +#define CP_NV_FLAGS_3_END_RCVD_48_SHIFT 1 +#define CP_NV_FLAGS_3_DISCARD_49_SHIFT 2 +#define CP_NV_FLAGS_3_END_RCVD_49_SHIFT 3 +#define CP_NV_FLAGS_3_DISCARD_50_SHIFT 4 +#define CP_NV_FLAGS_3_END_RCVD_50_SHIFT 5 +#define CP_NV_FLAGS_3_DISCARD_51_SHIFT 6 +#define CP_NV_FLAGS_3_END_RCVD_51_SHIFT 7 +#define CP_NV_FLAGS_3_DISCARD_52_SHIFT 8 +#define CP_NV_FLAGS_3_END_RCVD_52_SHIFT 9 +#define CP_NV_FLAGS_3_DISCARD_53_SHIFT 10 +#define CP_NV_FLAGS_3_END_RCVD_53_SHIFT 11 +#define CP_NV_FLAGS_3_DISCARD_54_SHIFT 12 +#define CP_NV_FLAGS_3_END_RCVD_54_SHIFT 13 +#define CP_NV_FLAGS_3_DISCARD_55_SHIFT 14 +#define CP_NV_FLAGS_3_END_RCVD_55_SHIFT 15 +#define CP_NV_FLAGS_3_DISCARD_56_SHIFT 16 +#define CP_NV_FLAGS_3_END_RCVD_56_SHIFT 17 +#define CP_NV_FLAGS_3_DISCARD_57_SHIFT 18 +#define CP_NV_FLAGS_3_END_RCVD_57_SHIFT 19 +#define CP_NV_FLAGS_3_DISCARD_58_SHIFT 20 +#define CP_NV_FLAGS_3_END_RCVD_58_SHIFT 21 +#define CP_NV_FLAGS_3_DISCARD_59_SHIFT 22 +#define CP_NV_FLAGS_3_END_RCVD_59_SHIFT 23 +#define CP_NV_FLAGS_3_DISCARD_60_SHIFT 24 +#define CP_NV_FLAGS_3_END_RCVD_60_SHIFT 25 +#define CP_NV_FLAGS_3_DISCARD_61_SHIFT 26 +#define CP_NV_FLAGS_3_END_RCVD_61_SHIFT 27 +#define CP_NV_FLAGS_3_DISCARD_62_SHIFT 28 +#define CP_NV_FLAGS_3_END_RCVD_62_SHIFT 29 +#define CP_NV_FLAGS_3_DISCARD_63_SHIFT 30 +#define CP_NV_FLAGS_3_END_RCVD_63_SHIFT 31 + +#define CP_NV_FLAGS_3_DISCARD_48_MASK 0x00000001 +#define CP_NV_FLAGS_3_END_RCVD_48_MASK 0x00000002 +#define CP_NV_FLAGS_3_DISCARD_49_MASK 0x00000004 +#define CP_NV_FLAGS_3_END_RCVD_49_MASK 0x00000008 +#define CP_NV_FLAGS_3_DISCARD_50_MASK 0x00000010 +#define CP_NV_FLAGS_3_END_RCVD_50_MASK 0x00000020 +#define CP_NV_FLAGS_3_DISCARD_51_MASK 0x00000040 +#define CP_NV_FLAGS_3_END_RCVD_51_MASK 0x00000080 +#define CP_NV_FLAGS_3_DISCARD_52_MASK 0x00000100 +#define CP_NV_FLAGS_3_END_RCVD_52_MASK 0x00000200 +#define CP_NV_FLAGS_3_DISCARD_53_MASK 0x00000400 +#define CP_NV_FLAGS_3_END_RCVD_53_MASK 0x00000800 +#define CP_NV_FLAGS_3_DISCARD_54_MASK 0x00001000 +#define CP_NV_FLAGS_3_END_RCVD_54_MASK 0x00002000 +#define CP_NV_FLAGS_3_DISCARD_55_MASK 0x00004000 +#define CP_NV_FLAGS_3_END_RCVD_55_MASK 0x00008000 +#define CP_NV_FLAGS_3_DISCARD_56_MASK 0x00010000 +#define CP_NV_FLAGS_3_END_RCVD_56_MASK 0x00020000 +#define CP_NV_FLAGS_3_DISCARD_57_MASK 0x00040000 +#define CP_NV_FLAGS_3_END_RCVD_57_MASK 0x00080000 +#define CP_NV_FLAGS_3_DISCARD_58_MASK 0x00100000 +#define CP_NV_FLAGS_3_END_RCVD_58_MASK 0x00200000 +#define CP_NV_FLAGS_3_DISCARD_59_MASK 0x00400000 +#define CP_NV_FLAGS_3_END_RCVD_59_MASK 0x00800000 +#define CP_NV_FLAGS_3_DISCARD_60_MASK 0x01000000 +#define CP_NV_FLAGS_3_END_RCVD_60_MASK 0x02000000 +#define CP_NV_FLAGS_3_DISCARD_61_MASK 0x04000000 +#define CP_NV_FLAGS_3_END_RCVD_61_MASK 0x08000000 +#define CP_NV_FLAGS_3_DISCARD_62_MASK 0x10000000 +#define CP_NV_FLAGS_3_END_RCVD_62_MASK 0x20000000 +#define CP_NV_FLAGS_3_DISCARD_63_MASK 0x40000000 +#define CP_NV_FLAGS_3_END_RCVD_63_MASK 0x80000000 + +#define CP_NV_FLAGS_3_MASK \ + (CP_NV_FLAGS_3_DISCARD_48_MASK | \ + CP_NV_FLAGS_3_END_RCVD_48_MASK | \ + CP_NV_FLAGS_3_DISCARD_49_MASK | \ + CP_NV_FLAGS_3_END_RCVD_49_MASK | \ + CP_NV_FLAGS_3_DISCARD_50_MASK | \ + CP_NV_FLAGS_3_END_RCVD_50_MASK | \ + CP_NV_FLAGS_3_DISCARD_51_MASK | \ + CP_NV_FLAGS_3_END_RCVD_51_MASK | \ + CP_NV_FLAGS_3_DISCARD_52_MASK | \ + CP_NV_FLAGS_3_END_RCVD_52_MASK | \ + CP_NV_FLAGS_3_DISCARD_53_MASK | \ + CP_NV_FLAGS_3_END_RCVD_53_MASK | \ + CP_NV_FLAGS_3_DISCARD_54_MASK | \ + CP_NV_FLAGS_3_END_RCVD_54_MASK | \ + CP_NV_FLAGS_3_DISCARD_55_MASK | \ + CP_NV_FLAGS_3_END_RCVD_55_MASK | \ + CP_NV_FLAGS_3_DISCARD_56_MASK | \ + CP_NV_FLAGS_3_END_RCVD_56_MASK | \ + CP_NV_FLAGS_3_DISCARD_57_MASK | \ + CP_NV_FLAGS_3_END_RCVD_57_MASK | \ + CP_NV_FLAGS_3_DISCARD_58_MASK | \ + CP_NV_FLAGS_3_END_RCVD_58_MASK | \ + CP_NV_FLAGS_3_DISCARD_59_MASK | \ + CP_NV_FLAGS_3_END_RCVD_59_MASK | \ + CP_NV_FLAGS_3_DISCARD_60_MASK | \ + CP_NV_FLAGS_3_END_RCVD_60_MASK | \ + CP_NV_FLAGS_3_DISCARD_61_MASK | \ + CP_NV_FLAGS_3_END_RCVD_61_MASK | \ + CP_NV_FLAGS_3_DISCARD_62_MASK | \ + CP_NV_FLAGS_3_END_RCVD_62_MASK | \ + CP_NV_FLAGS_3_DISCARD_63_MASK | \ + CP_NV_FLAGS_3_END_RCVD_63_MASK) + +#define CP_NV_FLAGS_3(discard_48, end_rcvd_48, discard_49, end_rcvd_49, discard_50, end_rcvd_50, discard_51, end_rcvd_51, discard_52, end_rcvd_52, discard_53, end_rcvd_53, discard_54, end_rcvd_54, discard_55, end_rcvd_55, discard_56, end_rcvd_56, discard_57, end_rcvd_57, discard_58, end_rcvd_58, discard_59, end_rcvd_59, discard_60, end_rcvd_60, discard_61, end_rcvd_61, discard_62, end_rcvd_62, discard_63, end_rcvd_63) \ + ((discard_48 << CP_NV_FLAGS_3_DISCARD_48_SHIFT) | \ + (end_rcvd_48 << CP_NV_FLAGS_3_END_RCVD_48_SHIFT) | \ + (discard_49 << CP_NV_FLAGS_3_DISCARD_49_SHIFT) | \ + (end_rcvd_49 << CP_NV_FLAGS_3_END_RCVD_49_SHIFT) | \ + (discard_50 << CP_NV_FLAGS_3_DISCARD_50_SHIFT) | \ + (end_rcvd_50 << CP_NV_FLAGS_3_END_RCVD_50_SHIFT) | \ + (discard_51 << CP_NV_FLAGS_3_DISCARD_51_SHIFT) | \ + (end_rcvd_51 << CP_NV_FLAGS_3_END_RCVD_51_SHIFT) | \ + (discard_52 << CP_NV_FLAGS_3_DISCARD_52_SHIFT) | \ + (end_rcvd_52 << CP_NV_FLAGS_3_END_RCVD_52_SHIFT) | \ + (discard_53 << CP_NV_FLAGS_3_DISCARD_53_SHIFT) | \ + (end_rcvd_53 << CP_NV_FLAGS_3_END_RCVD_53_SHIFT) | \ + (discard_54 << CP_NV_FLAGS_3_DISCARD_54_SHIFT) | \ + (end_rcvd_54 << CP_NV_FLAGS_3_END_RCVD_54_SHIFT) | \ + (discard_55 << CP_NV_FLAGS_3_DISCARD_55_SHIFT) | \ + (end_rcvd_55 << CP_NV_FLAGS_3_END_RCVD_55_SHIFT) | \ + (discard_56 << CP_NV_FLAGS_3_DISCARD_56_SHIFT) | \ + (end_rcvd_56 << CP_NV_FLAGS_3_END_RCVD_56_SHIFT) | \ + (discard_57 << CP_NV_FLAGS_3_DISCARD_57_SHIFT) | \ + (end_rcvd_57 << CP_NV_FLAGS_3_END_RCVD_57_SHIFT) | \ + (discard_58 << CP_NV_FLAGS_3_DISCARD_58_SHIFT) | \ + (end_rcvd_58 << CP_NV_FLAGS_3_END_RCVD_58_SHIFT) | \ + (discard_59 << CP_NV_FLAGS_3_DISCARD_59_SHIFT) | \ + (end_rcvd_59 << CP_NV_FLAGS_3_END_RCVD_59_SHIFT) | \ + (discard_60 << CP_NV_FLAGS_3_DISCARD_60_SHIFT) | \ + (end_rcvd_60 << CP_NV_FLAGS_3_END_RCVD_60_SHIFT) | \ + (discard_61 << CP_NV_FLAGS_3_DISCARD_61_SHIFT) | \ + (end_rcvd_61 << CP_NV_FLAGS_3_END_RCVD_61_SHIFT) | \ + (discard_62 << CP_NV_FLAGS_3_DISCARD_62_SHIFT) | \ + (end_rcvd_62 << CP_NV_FLAGS_3_END_RCVD_62_SHIFT) | \ + (discard_63 << CP_NV_FLAGS_3_DISCARD_63_SHIFT) | \ + (end_rcvd_63 << CP_NV_FLAGS_3_END_RCVD_63_SHIFT)) + +#define CP_NV_FLAGS_3_GET_DISCARD_48(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_48_MASK) >> CP_NV_FLAGS_3_DISCARD_48_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_48(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_48_MASK) >> CP_NV_FLAGS_3_END_RCVD_48_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_49(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_49_MASK) >> CP_NV_FLAGS_3_DISCARD_49_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_49(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_49_MASK) >> CP_NV_FLAGS_3_END_RCVD_49_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_50(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_50_MASK) >> CP_NV_FLAGS_3_DISCARD_50_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_50(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_50_MASK) >> CP_NV_FLAGS_3_END_RCVD_50_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_51(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_51_MASK) >> CP_NV_FLAGS_3_DISCARD_51_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_51(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_51_MASK) >> CP_NV_FLAGS_3_END_RCVD_51_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_52(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_52_MASK) >> CP_NV_FLAGS_3_DISCARD_52_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_52(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_52_MASK) >> CP_NV_FLAGS_3_END_RCVD_52_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_53(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_53_MASK) >> CP_NV_FLAGS_3_DISCARD_53_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_53(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_53_MASK) >> CP_NV_FLAGS_3_END_RCVD_53_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_54(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_54_MASK) >> CP_NV_FLAGS_3_DISCARD_54_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_54(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_54_MASK) >> CP_NV_FLAGS_3_END_RCVD_54_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_55(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_55_MASK) >> CP_NV_FLAGS_3_DISCARD_55_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_55(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_55_MASK) >> CP_NV_FLAGS_3_END_RCVD_55_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_56(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_56_MASK) >> CP_NV_FLAGS_3_DISCARD_56_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_56(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_56_MASK) >> CP_NV_FLAGS_3_END_RCVD_56_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_57(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_57_MASK) >> CP_NV_FLAGS_3_DISCARD_57_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_57(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_57_MASK) >> CP_NV_FLAGS_3_END_RCVD_57_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_58(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_58_MASK) >> CP_NV_FLAGS_3_DISCARD_58_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_58(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_58_MASK) >> CP_NV_FLAGS_3_END_RCVD_58_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_59(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_59_MASK) >> CP_NV_FLAGS_3_DISCARD_59_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_59(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_59_MASK) >> CP_NV_FLAGS_3_END_RCVD_59_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_60(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_60_MASK) >> CP_NV_FLAGS_3_DISCARD_60_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_60(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_60_MASK) >> CP_NV_FLAGS_3_END_RCVD_60_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_61(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_61_MASK) >> CP_NV_FLAGS_3_DISCARD_61_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_61(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_61_MASK) >> CP_NV_FLAGS_3_END_RCVD_61_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_62(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_62_MASK) >> CP_NV_FLAGS_3_DISCARD_62_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_62(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_62_MASK) >> CP_NV_FLAGS_3_END_RCVD_62_SHIFT) +#define CP_NV_FLAGS_3_GET_DISCARD_63(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_DISCARD_63_MASK) >> CP_NV_FLAGS_3_DISCARD_63_SHIFT) +#define CP_NV_FLAGS_3_GET_END_RCVD_63(cp_nv_flags_3) \ + ((cp_nv_flags_3 & CP_NV_FLAGS_3_END_RCVD_63_MASK) >> CP_NV_FLAGS_3_END_RCVD_63_SHIFT) + +#define CP_NV_FLAGS_3_SET_DISCARD_48(cp_nv_flags_3_reg, discard_48) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_48_MASK) | (discard_48 << CP_NV_FLAGS_3_DISCARD_48_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_48(cp_nv_flags_3_reg, end_rcvd_48) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_48_MASK) | (end_rcvd_48 << CP_NV_FLAGS_3_END_RCVD_48_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_49(cp_nv_flags_3_reg, discard_49) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_49_MASK) | (discard_49 << CP_NV_FLAGS_3_DISCARD_49_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_49(cp_nv_flags_3_reg, end_rcvd_49) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_49_MASK) | (end_rcvd_49 << CP_NV_FLAGS_3_END_RCVD_49_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_50(cp_nv_flags_3_reg, discard_50) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_50_MASK) | (discard_50 << CP_NV_FLAGS_3_DISCARD_50_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_50(cp_nv_flags_3_reg, end_rcvd_50) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_50_MASK) | (end_rcvd_50 << CP_NV_FLAGS_3_END_RCVD_50_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_51(cp_nv_flags_3_reg, discard_51) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_51_MASK) | (discard_51 << CP_NV_FLAGS_3_DISCARD_51_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_51(cp_nv_flags_3_reg, end_rcvd_51) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_51_MASK) | (end_rcvd_51 << CP_NV_FLAGS_3_END_RCVD_51_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_52(cp_nv_flags_3_reg, discard_52) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_52_MASK) | (discard_52 << CP_NV_FLAGS_3_DISCARD_52_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_52(cp_nv_flags_3_reg, end_rcvd_52) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_52_MASK) | (end_rcvd_52 << CP_NV_FLAGS_3_END_RCVD_52_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_53(cp_nv_flags_3_reg, discard_53) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_53_MASK) | (discard_53 << CP_NV_FLAGS_3_DISCARD_53_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_53(cp_nv_flags_3_reg, end_rcvd_53) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_53_MASK) | (end_rcvd_53 << CP_NV_FLAGS_3_END_RCVD_53_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_54(cp_nv_flags_3_reg, discard_54) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_54_MASK) | (discard_54 << CP_NV_FLAGS_3_DISCARD_54_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_54(cp_nv_flags_3_reg, end_rcvd_54) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_54_MASK) | (end_rcvd_54 << CP_NV_FLAGS_3_END_RCVD_54_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_55(cp_nv_flags_3_reg, discard_55) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_55_MASK) | (discard_55 << CP_NV_FLAGS_3_DISCARD_55_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_55(cp_nv_flags_3_reg, end_rcvd_55) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_55_MASK) | (end_rcvd_55 << CP_NV_FLAGS_3_END_RCVD_55_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_56(cp_nv_flags_3_reg, discard_56) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_56_MASK) | (discard_56 << CP_NV_FLAGS_3_DISCARD_56_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_56(cp_nv_flags_3_reg, end_rcvd_56) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_56_MASK) | (end_rcvd_56 << CP_NV_FLAGS_3_END_RCVD_56_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_57(cp_nv_flags_3_reg, discard_57) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_57_MASK) | (discard_57 << CP_NV_FLAGS_3_DISCARD_57_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_57(cp_nv_flags_3_reg, end_rcvd_57) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_57_MASK) | (end_rcvd_57 << CP_NV_FLAGS_3_END_RCVD_57_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_58(cp_nv_flags_3_reg, discard_58) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_58_MASK) | (discard_58 << CP_NV_FLAGS_3_DISCARD_58_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_58(cp_nv_flags_3_reg, end_rcvd_58) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_58_MASK) | (end_rcvd_58 << CP_NV_FLAGS_3_END_RCVD_58_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_59(cp_nv_flags_3_reg, discard_59) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_59_MASK) | (discard_59 << CP_NV_FLAGS_3_DISCARD_59_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_59(cp_nv_flags_3_reg, end_rcvd_59) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_59_MASK) | (end_rcvd_59 << CP_NV_FLAGS_3_END_RCVD_59_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_60(cp_nv_flags_3_reg, discard_60) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_60_MASK) | (discard_60 << CP_NV_FLAGS_3_DISCARD_60_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_60(cp_nv_flags_3_reg, end_rcvd_60) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_60_MASK) | (end_rcvd_60 << CP_NV_FLAGS_3_END_RCVD_60_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_61(cp_nv_flags_3_reg, discard_61) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_61_MASK) | (discard_61 << CP_NV_FLAGS_3_DISCARD_61_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_61(cp_nv_flags_3_reg, end_rcvd_61) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_61_MASK) | (end_rcvd_61 << CP_NV_FLAGS_3_END_RCVD_61_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_62(cp_nv_flags_3_reg, discard_62) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_62_MASK) | (discard_62 << CP_NV_FLAGS_3_DISCARD_62_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_62(cp_nv_flags_3_reg, end_rcvd_62) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_62_MASK) | (end_rcvd_62 << CP_NV_FLAGS_3_END_RCVD_62_SHIFT) +#define CP_NV_FLAGS_3_SET_DISCARD_63(cp_nv_flags_3_reg, discard_63) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_DISCARD_63_MASK) | (discard_63 << CP_NV_FLAGS_3_DISCARD_63_SHIFT) +#define CP_NV_FLAGS_3_SET_END_RCVD_63(cp_nv_flags_3_reg, end_rcvd_63) \ + cp_nv_flags_3_reg = (cp_nv_flags_3_reg & ~CP_NV_FLAGS_3_END_RCVD_63_MASK) | (end_rcvd_63 << CP_NV_FLAGS_3_END_RCVD_63_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_nv_flags_3_t { + unsigned int discard_48 : CP_NV_FLAGS_3_DISCARD_48_SIZE; + unsigned int end_rcvd_48 : CP_NV_FLAGS_3_END_RCVD_48_SIZE; + unsigned int discard_49 : CP_NV_FLAGS_3_DISCARD_49_SIZE; + unsigned int end_rcvd_49 : CP_NV_FLAGS_3_END_RCVD_49_SIZE; + unsigned int discard_50 : CP_NV_FLAGS_3_DISCARD_50_SIZE; + unsigned int end_rcvd_50 : CP_NV_FLAGS_3_END_RCVD_50_SIZE; + unsigned int discard_51 : CP_NV_FLAGS_3_DISCARD_51_SIZE; + unsigned int end_rcvd_51 : CP_NV_FLAGS_3_END_RCVD_51_SIZE; + unsigned int discard_52 : CP_NV_FLAGS_3_DISCARD_52_SIZE; + unsigned int end_rcvd_52 : CP_NV_FLAGS_3_END_RCVD_52_SIZE; + unsigned int discard_53 : CP_NV_FLAGS_3_DISCARD_53_SIZE; + unsigned int end_rcvd_53 : CP_NV_FLAGS_3_END_RCVD_53_SIZE; + unsigned int discard_54 : CP_NV_FLAGS_3_DISCARD_54_SIZE; + unsigned int end_rcvd_54 : CP_NV_FLAGS_3_END_RCVD_54_SIZE; + unsigned int discard_55 : CP_NV_FLAGS_3_DISCARD_55_SIZE; + unsigned int end_rcvd_55 : CP_NV_FLAGS_3_END_RCVD_55_SIZE; + unsigned int discard_56 : CP_NV_FLAGS_3_DISCARD_56_SIZE; + unsigned int end_rcvd_56 : CP_NV_FLAGS_3_END_RCVD_56_SIZE; + unsigned int discard_57 : CP_NV_FLAGS_3_DISCARD_57_SIZE; + unsigned int end_rcvd_57 : CP_NV_FLAGS_3_END_RCVD_57_SIZE; + unsigned int discard_58 : CP_NV_FLAGS_3_DISCARD_58_SIZE; + unsigned int end_rcvd_58 : CP_NV_FLAGS_3_END_RCVD_58_SIZE; + unsigned int discard_59 : CP_NV_FLAGS_3_DISCARD_59_SIZE; + unsigned int end_rcvd_59 : CP_NV_FLAGS_3_END_RCVD_59_SIZE; + unsigned int discard_60 : CP_NV_FLAGS_3_DISCARD_60_SIZE; + unsigned int end_rcvd_60 : CP_NV_FLAGS_3_END_RCVD_60_SIZE; + unsigned int discard_61 : CP_NV_FLAGS_3_DISCARD_61_SIZE; + unsigned int end_rcvd_61 : CP_NV_FLAGS_3_END_RCVD_61_SIZE; + unsigned int discard_62 : CP_NV_FLAGS_3_DISCARD_62_SIZE; + unsigned int end_rcvd_62 : CP_NV_FLAGS_3_END_RCVD_62_SIZE; + unsigned int discard_63 : CP_NV_FLAGS_3_DISCARD_63_SIZE; + unsigned int end_rcvd_63 : CP_NV_FLAGS_3_END_RCVD_63_SIZE; + } cp_nv_flags_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_nv_flags_3_t { + unsigned int end_rcvd_63 : CP_NV_FLAGS_3_END_RCVD_63_SIZE; + unsigned int discard_63 : CP_NV_FLAGS_3_DISCARD_63_SIZE; + unsigned int end_rcvd_62 : CP_NV_FLAGS_3_END_RCVD_62_SIZE; + unsigned int discard_62 : CP_NV_FLAGS_3_DISCARD_62_SIZE; + unsigned int end_rcvd_61 : CP_NV_FLAGS_3_END_RCVD_61_SIZE; + unsigned int discard_61 : CP_NV_FLAGS_3_DISCARD_61_SIZE; + unsigned int end_rcvd_60 : CP_NV_FLAGS_3_END_RCVD_60_SIZE; + unsigned int discard_60 : CP_NV_FLAGS_3_DISCARD_60_SIZE; + unsigned int end_rcvd_59 : CP_NV_FLAGS_3_END_RCVD_59_SIZE; + unsigned int discard_59 : CP_NV_FLAGS_3_DISCARD_59_SIZE; + unsigned int end_rcvd_58 : CP_NV_FLAGS_3_END_RCVD_58_SIZE; + unsigned int discard_58 : CP_NV_FLAGS_3_DISCARD_58_SIZE; + unsigned int end_rcvd_57 : CP_NV_FLAGS_3_END_RCVD_57_SIZE; + unsigned int discard_57 : CP_NV_FLAGS_3_DISCARD_57_SIZE; + unsigned int end_rcvd_56 : CP_NV_FLAGS_3_END_RCVD_56_SIZE; + unsigned int discard_56 : CP_NV_FLAGS_3_DISCARD_56_SIZE; + unsigned int end_rcvd_55 : CP_NV_FLAGS_3_END_RCVD_55_SIZE; + unsigned int discard_55 : CP_NV_FLAGS_3_DISCARD_55_SIZE; + unsigned int end_rcvd_54 : CP_NV_FLAGS_3_END_RCVD_54_SIZE; + unsigned int discard_54 : CP_NV_FLAGS_3_DISCARD_54_SIZE; + unsigned int end_rcvd_53 : CP_NV_FLAGS_3_END_RCVD_53_SIZE; + unsigned int discard_53 : CP_NV_FLAGS_3_DISCARD_53_SIZE; + unsigned int end_rcvd_52 : CP_NV_FLAGS_3_END_RCVD_52_SIZE; + unsigned int discard_52 : CP_NV_FLAGS_3_DISCARD_52_SIZE; + unsigned int end_rcvd_51 : CP_NV_FLAGS_3_END_RCVD_51_SIZE; + unsigned int discard_51 : CP_NV_FLAGS_3_DISCARD_51_SIZE; + unsigned int end_rcvd_50 : CP_NV_FLAGS_3_END_RCVD_50_SIZE; + unsigned int discard_50 : CP_NV_FLAGS_3_DISCARD_50_SIZE; + unsigned int end_rcvd_49 : CP_NV_FLAGS_3_END_RCVD_49_SIZE; + unsigned int discard_49 : CP_NV_FLAGS_3_DISCARD_49_SIZE; + unsigned int end_rcvd_48 : CP_NV_FLAGS_3_END_RCVD_48_SIZE; + unsigned int discard_48 : CP_NV_FLAGS_3_DISCARD_48_SIZE; + } cp_nv_flags_3_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_nv_flags_3_t f; +} cp_nv_flags_3_u; + + +/* + * CP_STATE_DEBUG_INDEX struct + */ + +#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE 5 + +#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT 0 + +#define CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK 0x0000001f + +#define CP_STATE_DEBUG_INDEX_MASK \ + (CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) + +#define CP_STATE_DEBUG_INDEX(state_debug_index) \ + ((state_debug_index << CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT)) + +#define CP_STATE_DEBUG_INDEX_GET_STATE_DEBUG_INDEX(cp_state_debug_index) \ + ((cp_state_debug_index & CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) >> CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT) + +#define CP_STATE_DEBUG_INDEX_SET_STATE_DEBUG_INDEX(cp_state_debug_index_reg, state_debug_index) \ + cp_state_debug_index_reg = (cp_state_debug_index_reg & ~CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_MASK) | (state_debug_index << CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_state_debug_index_t { + unsigned int state_debug_index : CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE; + unsigned int : 27; + } cp_state_debug_index_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_state_debug_index_t { + unsigned int : 27; + unsigned int state_debug_index : CP_STATE_DEBUG_INDEX_STATE_DEBUG_INDEX_SIZE; + } cp_state_debug_index_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_state_debug_index_t f; +} cp_state_debug_index_u; + + +/* + * CP_STATE_DEBUG_DATA struct + */ + +#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE 32 + +#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT 0 + +#define CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK 0xffffffff + +#define CP_STATE_DEBUG_DATA_MASK \ + (CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) + +#define CP_STATE_DEBUG_DATA(state_debug_data) \ + ((state_debug_data << CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT)) + +#define CP_STATE_DEBUG_DATA_GET_STATE_DEBUG_DATA(cp_state_debug_data) \ + ((cp_state_debug_data & CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) >> CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT) + +#define CP_STATE_DEBUG_DATA_SET_STATE_DEBUG_DATA(cp_state_debug_data_reg, state_debug_data) \ + cp_state_debug_data_reg = (cp_state_debug_data_reg & ~CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_MASK) | (state_debug_data << CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_state_debug_data_t { + unsigned int state_debug_data : CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE; + } cp_state_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_state_debug_data_t { + unsigned int state_debug_data : CP_STATE_DEBUG_DATA_STATE_DEBUG_DATA_SIZE; + } cp_state_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_state_debug_data_t f; +} cp_state_debug_data_u; + + +/* + * CP_PROG_COUNTER struct + */ + +#define CP_PROG_COUNTER_COUNTER_SIZE 32 + +#define CP_PROG_COUNTER_COUNTER_SHIFT 0 + +#define CP_PROG_COUNTER_COUNTER_MASK 0xffffffff + +#define CP_PROG_COUNTER_MASK \ + (CP_PROG_COUNTER_COUNTER_MASK) + +#define CP_PROG_COUNTER(counter) \ + ((counter << CP_PROG_COUNTER_COUNTER_SHIFT)) + +#define CP_PROG_COUNTER_GET_COUNTER(cp_prog_counter) \ + ((cp_prog_counter & CP_PROG_COUNTER_COUNTER_MASK) >> CP_PROG_COUNTER_COUNTER_SHIFT) + +#define CP_PROG_COUNTER_SET_COUNTER(cp_prog_counter_reg, counter) \ + cp_prog_counter_reg = (cp_prog_counter_reg & ~CP_PROG_COUNTER_COUNTER_MASK) | (counter << CP_PROG_COUNTER_COUNTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_prog_counter_t { + unsigned int counter : CP_PROG_COUNTER_COUNTER_SIZE; + } cp_prog_counter_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_prog_counter_t { + unsigned int counter : CP_PROG_COUNTER_COUNTER_SIZE; + } cp_prog_counter_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_prog_counter_t f; +} cp_prog_counter_u; + + +/* + * CP_STAT struct + */ + +#define CP_STAT_MIU_WR_BUSY_SIZE 1 +#define CP_STAT_MIU_RD_REQ_BUSY_SIZE 1 +#define CP_STAT_MIU_RD_RETURN_BUSY_SIZE 1 +#define CP_STAT_RBIU_BUSY_SIZE 1 +#define CP_STAT_RCIU_BUSY_SIZE 1 +#define CP_STAT_CSF_RING_BUSY_SIZE 1 +#define CP_STAT_CSF_INDIRECTS_BUSY_SIZE 1 +#define CP_STAT_CSF_INDIRECT2_BUSY_SIZE 1 +#define CP_STAT_CSF_ST_BUSY_SIZE 1 +#define CP_STAT_CSF_BUSY_SIZE 1 +#define CP_STAT_RING_QUEUE_BUSY_SIZE 1 +#define CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE 1 +#define CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE 1 +#define CP_STAT_ST_QUEUE_BUSY_SIZE 1 +#define CP_STAT_PFP_BUSY_SIZE 1 +#define CP_STAT_MEQ_RING_BUSY_SIZE 1 +#define CP_STAT_MEQ_INDIRECTS_BUSY_SIZE 1 +#define CP_STAT_MEQ_INDIRECT2_BUSY_SIZE 1 +#define CP_STAT_MIU_WC_STALL_SIZE 1 +#define CP_STAT_CP_NRT_BUSY_SIZE 1 +#define CP_STAT__3D_BUSY_SIZE 1 +#define CP_STAT_ME_BUSY_SIZE 1 +#define CP_STAT_ME_WC_BUSY_SIZE 1 +#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE 1 +#define CP_STAT_CP_BUSY_SIZE 1 + +#define CP_STAT_MIU_WR_BUSY_SHIFT 0 +#define CP_STAT_MIU_RD_REQ_BUSY_SHIFT 1 +#define CP_STAT_MIU_RD_RETURN_BUSY_SHIFT 2 +#define CP_STAT_RBIU_BUSY_SHIFT 3 +#define CP_STAT_RCIU_BUSY_SHIFT 4 +#define CP_STAT_CSF_RING_BUSY_SHIFT 5 +#define CP_STAT_CSF_INDIRECTS_BUSY_SHIFT 6 +#define CP_STAT_CSF_INDIRECT2_BUSY_SHIFT 7 +#define CP_STAT_CSF_ST_BUSY_SHIFT 9 +#define CP_STAT_CSF_BUSY_SHIFT 10 +#define CP_STAT_RING_QUEUE_BUSY_SHIFT 11 +#define CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT 12 +#define CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT 13 +#define CP_STAT_ST_QUEUE_BUSY_SHIFT 16 +#define CP_STAT_PFP_BUSY_SHIFT 17 +#define CP_STAT_MEQ_RING_BUSY_SHIFT 18 +#define CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT 19 +#define CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT 20 +#define CP_STAT_MIU_WC_STALL_SHIFT 21 +#define CP_STAT_CP_NRT_BUSY_SHIFT 22 +#define CP_STAT__3D_BUSY_SHIFT 23 +#define CP_STAT_ME_BUSY_SHIFT 26 +#define CP_STAT_ME_WC_BUSY_SHIFT 29 +#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT 30 +#define CP_STAT_CP_BUSY_SHIFT 31 + +#define CP_STAT_MIU_WR_BUSY_MASK 0x00000001 +#define CP_STAT_MIU_RD_REQ_BUSY_MASK 0x00000002 +#define CP_STAT_MIU_RD_RETURN_BUSY_MASK 0x00000004 +#define CP_STAT_RBIU_BUSY_MASK 0x00000008 +#define CP_STAT_RCIU_BUSY_MASK 0x00000010 +#define CP_STAT_CSF_RING_BUSY_MASK 0x00000020 +#define CP_STAT_CSF_INDIRECTS_BUSY_MASK 0x00000040 +#define CP_STAT_CSF_INDIRECT2_BUSY_MASK 0x00000080 +#define CP_STAT_CSF_ST_BUSY_MASK 0x00000200 +#define CP_STAT_CSF_BUSY_MASK 0x00000400 +#define CP_STAT_RING_QUEUE_BUSY_MASK 0x00000800 +#define CP_STAT_INDIRECTS_QUEUE_BUSY_MASK 0x00001000 +#define CP_STAT_INDIRECT2_QUEUE_BUSY_MASK 0x00002000 +#define CP_STAT_ST_QUEUE_BUSY_MASK 0x00010000 +#define CP_STAT_PFP_BUSY_MASK 0x00020000 +#define CP_STAT_MEQ_RING_BUSY_MASK 0x00040000 +#define CP_STAT_MEQ_INDIRECTS_BUSY_MASK 0x00080000 +#define CP_STAT_MEQ_INDIRECT2_BUSY_MASK 0x00100000 +#define CP_STAT_MIU_WC_STALL_MASK 0x00200000 +#define CP_STAT_CP_NRT_BUSY_MASK 0x00400000 +#define CP_STAT__3D_BUSY_MASK 0x00800000 +#define CP_STAT_ME_BUSY_MASK 0x04000000 +#define CP_STAT_ME_WC_BUSY_MASK 0x20000000 +#define CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK 0x40000000 +#define CP_STAT_CP_BUSY_MASK 0x80000000 + +#define CP_STAT_MASK \ + (CP_STAT_MIU_WR_BUSY_MASK | \ + CP_STAT_MIU_RD_REQ_BUSY_MASK | \ + CP_STAT_MIU_RD_RETURN_BUSY_MASK | \ + CP_STAT_RBIU_BUSY_MASK | \ + CP_STAT_RCIU_BUSY_MASK | \ + CP_STAT_CSF_RING_BUSY_MASK | \ + CP_STAT_CSF_INDIRECTS_BUSY_MASK | \ + CP_STAT_CSF_INDIRECT2_BUSY_MASK | \ + CP_STAT_CSF_ST_BUSY_MASK | \ + CP_STAT_CSF_BUSY_MASK | \ + CP_STAT_RING_QUEUE_BUSY_MASK | \ + CP_STAT_INDIRECTS_QUEUE_BUSY_MASK | \ + CP_STAT_INDIRECT2_QUEUE_BUSY_MASK | \ + CP_STAT_ST_QUEUE_BUSY_MASK | \ + CP_STAT_PFP_BUSY_MASK | \ + CP_STAT_MEQ_RING_BUSY_MASK | \ + CP_STAT_MEQ_INDIRECTS_BUSY_MASK | \ + CP_STAT_MEQ_INDIRECT2_BUSY_MASK | \ + CP_STAT_MIU_WC_STALL_MASK | \ + CP_STAT_CP_NRT_BUSY_MASK | \ + CP_STAT__3D_BUSY_MASK | \ + CP_STAT_ME_BUSY_MASK | \ + CP_STAT_ME_WC_BUSY_MASK | \ + CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK | \ + CP_STAT_CP_BUSY_MASK) + +#define CP_STAT(miu_wr_busy, miu_rd_req_busy, miu_rd_return_busy, rbiu_busy, rciu_busy, csf_ring_busy, csf_indirects_busy, csf_indirect2_busy, csf_st_busy, csf_busy, ring_queue_busy, indirects_queue_busy, indirect2_queue_busy, st_queue_busy, pfp_busy, meq_ring_busy, meq_indirects_busy, meq_indirect2_busy, miu_wc_stall, cp_nrt_busy, _3d_busy, me_busy, me_wc_busy, miu_wc_track_fifo_empty, cp_busy) \ + ((miu_wr_busy << CP_STAT_MIU_WR_BUSY_SHIFT) | \ + (miu_rd_req_busy << CP_STAT_MIU_RD_REQ_BUSY_SHIFT) | \ + (miu_rd_return_busy << CP_STAT_MIU_RD_RETURN_BUSY_SHIFT) | \ + (rbiu_busy << CP_STAT_RBIU_BUSY_SHIFT) | \ + (rciu_busy << CP_STAT_RCIU_BUSY_SHIFT) | \ + (csf_ring_busy << CP_STAT_CSF_RING_BUSY_SHIFT) | \ + (csf_indirects_busy << CP_STAT_CSF_INDIRECTS_BUSY_SHIFT) | \ + (csf_indirect2_busy << CP_STAT_CSF_INDIRECT2_BUSY_SHIFT) | \ + (csf_st_busy << CP_STAT_CSF_ST_BUSY_SHIFT) | \ + (csf_busy << CP_STAT_CSF_BUSY_SHIFT) | \ + (ring_queue_busy << CP_STAT_RING_QUEUE_BUSY_SHIFT) | \ + (indirects_queue_busy << CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT) | \ + (indirect2_queue_busy << CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT) | \ + (st_queue_busy << CP_STAT_ST_QUEUE_BUSY_SHIFT) | \ + (pfp_busy << CP_STAT_PFP_BUSY_SHIFT) | \ + (meq_ring_busy << CP_STAT_MEQ_RING_BUSY_SHIFT) | \ + (meq_indirects_busy << CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT) | \ + (meq_indirect2_busy << CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT) | \ + (miu_wc_stall << CP_STAT_MIU_WC_STALL_SHIFT) | \ + (cp_nrt_busy << CP_STAT_CP_NRT_BUSY_SHIFT) | \ + (_3d_busy << CP_STAT__3D_BUSY_SHIFT) | \ + (me_busy << CP_STAT_ME_BUSY_SHIFT) | \ + (me_wc_busy << CP_STAT_ME_WC_BUSY_SHIFT) | \ + (miu_wc_track_fifo_empty << CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT) | \ + (cp_busy << CP_STAT_CP_BUSY_SHIFT)) + +#define CP_STAT_GET_MIU_WR_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MIU_WR_BUSY_MASK) >> CP_STAT_MIU_WR_BUSY_SHIFT) +#define CP_STAT_GET_MIU_RD_REQ_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MIU_RD_REQ_BUSY_MASK) >> CP_STAT_MIU_RD_REQ_BUSY_SHIFT) +#define CP_STAT_GET_MIU_RD_RETURN_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MIU_RD_RETURN_BUSY_MASK) >> CP_STAT_MIU_RD_RETURN_BUSY_SHIFT) +#define CP_STAT_GET_RBIU_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_RBIU_BUSY_MASK) >> CP_STAT_RBIU_BUSY_SHIFT) +#define CP_STAT_GET_RCIU_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_RCIU_BUSY_MASK) >> CP_STAT_RCIU_BUSY_SHIFT) +#define CP_STAT_GET_CSF_RING_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_RING_BUSY_MASK) >> CP_STAT_CSF_RING_BUSY_SHIFT) +#define CP_STAT_GET_CSF_INDIRECTS_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_INDIRECTS_BUSY_MASK) >> CP_STAT_CSF_INDIRECTS_BUSY_SHIFT) +#define CP_STAT_GET_CSF_INDIRECT2_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_INDIRECT2_BUSY_MASK) >> CP_STAT_CSF_INDIRECT2_BUSY_SHIFT) +#define CP_STAT_GET_CSF_ST_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_ST_BUSY_MASK) >> CP_STAT_CSF_ST_BUSY_SHIFT) +#define CP_STAT_GET_CSF_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CSF_BUSY_MASK) >> CP_STAT_CSF_BUSY_SHIFT) +#define CP_STAT_GET_RING_QUEUE_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_RING_QUEUE_BUSY_MASK) >> CP_STAT_RING_QUEUE_BUSY_SHIFT) +#define CP_STAT_GET_INDIRECTS_QUEUE_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_INDIRECTS_QUEUE_BUSY_MASK) >> CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT) +#define CP_STAT_GET_INDIRECT2_QUEUE_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_INDIRECT2_QUEUE_BUSY_MASK) >> CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT) +#define CP_STAT_GET_ST_QUEUE_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_ST_QUEUE_BUSY_MASK) >> CP_STAT_ST_QUEUE_BUSY_SHIFT) +#define CP_STAT_GET_PFP_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_PFP_BUSY_MASK) >> CP_STAT_PFP_BUSY_SHIFT) +#define CP_STAT_GET_MEQ_RING_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MEQ_RING_BUSY_MASK) >> CP_STAT_MEQ_RING_BUSY_SHIFT) +#define CP_STAT_GET_MEQ_INDIRECTS_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MEQ_INDIRECTS_BUSY_MASK) >> CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT) +#define CP_STAT_GET_MEQ_INDIRECT2_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_MEQ_INDIRECT2_BUSY_MASK) >> CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT) +#define CP_STAT_GET_MIU_WC_STALL(cp_stat) \ + ((cp_stat & CP_STAT_MIU_WC_STALL_MASK) >> CP_STAT_MIU_WC_STALL_SHIFT) +#define CP_STAT_GET_CP_NRT_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CP_NRT_BUSY_MASK) >> CP_STAT_CP_NRT_BUSY_SHIFT) +#define CP_STAT_GET__3D_BUSY(cp_stat) \ + ((cp_stat & CP_STAT__3D_BUSY_MASK) >> CP_STAT__3D_BUSY_SHIFT) +#define CP_STAT_GET_ME_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_ME_BUSY_MASK) >> CP_STAT_ME_BUSY_SHIFT) +#define CP_STAT_GET_ME_WC_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_ME_WC_BUSY_MASK) >> CP_STAT_ME_WC_BUSY_SHIFT) +#define CP_STAT_GET_MIU_WC_TRACK_FIFO_EMPTY(cp_stat) \ + ((cp_stat & CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK) >> CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT) +#define CP_STAT_GET_CP_BUSY(cp_stat) \ + ((cp_stat & CP_STAT_CP_BUSY_MASK) >> CP_STAT_CP_BUSY_SHIFT) + +#define CP_STAT_SET_MIU_WR_BUSY(cp_stat_reg, miu_wr_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WR_BUSY_MASK) | (miu_wr_busy << CP_STAT_MIU_WR_BUSY_SHIFT) +#define CP_STAT_SET_MIU_RD_REQ_BUSY(cp_stat_reg, miu_rd_req_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_RD_REQ_BUSY_MASK) | (miu_rd_req_busy << CP_STAT_MIU_RD_REQ_BUSY_SHIFT) +#define CP_STAT_SET_MIU_RD_RETURN_BUSY(cp_stat_reg, miu_rd_return_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_RD_RETURN_BUSY_MASK) | (miu_rd_return_busy << CP_STAT_MIU_RD_RETURN_BUSY_SHIFT) +#define CP_STAT_SET_RBIU_BUSY(cp_stat_reg, rbiu_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_RBIU_BUSY_MASK) | (rbiu_busy << CP_STAT_RBIU_BUSY_SHIFT) +#define CP_STAT_SET_RCIU_BUSY(cp_stat_reg, rciu_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_RCIU_BUSY_MASK) | (rciu_busy << CP_STAT_RCIU_BUSY_SHIFT) +#define CP_STAT_SET_CSF_RING_BUSY(cp_stat_reg, csf_ring_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_RING_BUSY_MASK) | (csf_ring_busy << CP_STAT_CSF_RING_BUSY_SHIFT) +#define CP_STAT_SET_CSF_INDIRECTS_BUSY(cp_stat_reg, csf_indirects_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_INDIRECTS_BUSY_MASK) | (csf_indirects_busy << CP_STAT_CSF_INDIRECTS_BUSY_SHIFT) +#define CP_STAT_SET_CSF_INDIRECT2_BUSY(cp_stat_reg, csf_indirect2_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_INDIRECT2_BUSY_MASK) | (csf_indirect2_busy << CP_STAT_CSF_INDIRECT2_BUSY_SHIFT) +#define CP_STAT_SET_CSF_ST_BUSY(cp_stat_reg, csf_st_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_ST_BUSY_MASK) | (csf_st_busy << CP_STAT_CSF_ST_BUSY_SHIFT) +#define CP_STAT_SET_CSF_BUSY(cp_stat_reg, csf_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CSF_BUSY_MASK) | (csf_busy << CP_STAT_CSF_BUSY_SHIFT) +#define CP_STAT_SET_RING_QUEUE_BUSY(cp_stat_reg, ring_queue_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_RING_QUEUE_BUSY_MASK) | (ring_queue_busy << CP_STAT_RING_QUEUE_BUSY_SHIFT) +#define CP_STAT_SET_INDIRECTS_QUEUE_BUSY(cp_stat_reg, indirects_queue_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_INDIRECTS_QUEUE_BUSY_MASK) | (indirects_queue_busy << CP_STAT_INDIRECTS_QUEUE_BUSY_SHIFT) +#define CP_STAT_SET_INDIRECT2_QUEUE_BUSY(cp_stat_reg, indirect2_queue_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_INDIRECT2_QUEUE_BUSY_MASK) | (indirect2_queue_busy << CP_STAT_INDIRECT2_QUEUE_BUSY_SHIFT) +#define CP_STAT_SET_ST_QUEUE_BUSY(cp_stat_reg, st_queue_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_ST_QUEUE_BUSY_MASK) | (st_queue_busy << CP_STAT_ST_QUEUE_BUSY_SHIFT) +#define CP_STAT_SET_PFP_BUSY(cp_stat_reg, pfp_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_PFP_BUSY_MASK) | (pfp_busy << CP_STAT_PFP_BUSY_SHIFT) +#define CP_STAT_SET_MEQ_RING_BUSY(cp_stat_reg, meq_ring_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_RING_BUSY_MASK) | (meq_ring_busy << CP_STAT_MEQ_RING_BUSY_SHIFT) +#define CP_STAT_SET_MEQ_INDIRECTS_BUSY(cp_stat_reg, meq_indirects_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_INDIRECTS_BUSY_MASK) | (meq_indirects_busy << CP_STAT_MEQ_INDIRECTS_BUSY_SHIFT) +#define CP_STAT_SET_MEQ_INDIRECT2_BUSY(cp_stat_reg, meq_indirect2_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MEQ_INDIRECT2_BUSY_MASK) | (meq_indirect2_busy << CP_STAT_MEQ_INDIRECT2_BUSY_SHIFT) +#define CP_STAT_SET_MIU_WC_STALL(cp_stat_reg, miu_wc_stall) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WC_STALL_MASK) | (miu_wc_stall << CP_STAT_MIU_WC_STALL_SHIFT) +#define CP_STAT_SET_CP_NRT_BUSY(cp_stat_reg, cp_nrt_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CP_NRT_BUSY_MASK) | (cp_nrt_busy << CP_STAT_CP_NRT_BUSY_SHIFT) +#define CP_STAT_SET__3D_BUSY(cp_stat_reg, _3d_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT__3D_BUSY_MASK) | (_3d_busy << CP_STAT__3D_BUSY_SHIFT) +#define CP_STAT_SET_ME_BUSY(cp_stat_reg, me_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_ME_BUSY_MASK) | (me_busy << CP_STAT_ME_BUSY_SHIFT) +#define CP_STAT_SET_ME_WC_BUSY(cp_stat_reg, me_wc_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_ME_WC_BUSY_MASK) | (me_wc_busy << CP_STAT_ME_WC_BUSY_SHIFT) +#define CP_STAT_SET_MIU_WC_TRACK_FIFO_EMPTY(cp_stat_reg, miu_wc_track_fifo_empty) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_MASK) | (miu_wc_track_fifo_empty << CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SHIFT) +#define CP_STAT_SET_CP_BUSY(cp_stat_reg, cp_busy) \ + cp_stat_reg = (cp_stat_reg & ~CP_STAT_CP_BUSY_MASK) | (cp_busy << CP_STAT_CP_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _cp_stat_t { + unsigned int miu_wr_busy : CP_STAT_MIU_WR_BUSY_SIZE; + unsigned int miu_rd_req_busy : CP_STAT_MIU_RD_REQ_BUSY_SIZE; + unsigned int miu_rd_return_busy : CP_STAT_MIU_RD_RETURN_BUSY_SIZE; + unsigned int rbiu_busy : CP_STAT_RBIU_BUSY_SIZE; + unsigned int rciu_busy : CP_STAT_RCIU_BUSY_SIZE; + unsigned int csf_ring_busy : CP_STAT_CSF_RING_BUSY_SIZE; + unsigned int csf_indirects_busy : CP_STAT_CSF_INDIRECTS_BUSY_SIZE; + unsigned int csf_indirect2_busy : CP_STAT_CSF_INDIRECT2_BUSY_SIZE; + unsigned int : 1; + unsigned int csf_st_busy : CP_STAT_CSF_ST_BUSY_SIZE; + unsigned int csf_busy : CP_STAT_CSF_BUSY_SIZE; + unsigned int ring_queue_busy : CP_STAT_RING_QUEUE_BUSY_SIZE; + unsigned int indirects_queue_busy : CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE; + unsigned int indirect2_queue_busy : CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE; + unsigned int : 2; + unsigned int st_queue_busy : CP_STAT_ST_QUEUE_BUSY_SIZE; + unsigned int pfp_busy : CP_STAT_PFP_BUSY_SIZE; + unsigned int meq_ring_busy : CP_STAT_MEQ_RING_BUSY_SIZE; + unsigned int meq_indirects_busy : CP_STAT_MEQ_INDIRECTS_BUSY_SIZE; + unsigned int meq_indirect2_busy : CP_STAT_MEQ_INDIRECT2_BUSY_SIZE; + unsigned int miu_wc_stall : CP_STAT_MIU_WC_STALL_SIZE; + unsigned int cp_nrt_busy : CP_STAT_CP_NRT_BUSY_SIZE; + unsigned int _3d_busy : CP_STAT__3D_BUSY_SIZE; + unsigned int : 2; + unsigned int me_busy : CP_STAT_ME_BUSY_SIZE; + unsigned int : 2; + unsigned int me_wc_busy : CP_STAT_ME_WC_BUSY_SIZE; + unsigned int miu_wc_track_fifo_empty : CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE; + unsigned int cp_busy : CP_STAT_CP_BUSY_SIZE; + } cp_stat_t; + +#else // !BIGENDIAN_OS + + typedef struct _cp_stat_t { + unsigned int cp_busy : CP_STAT_CP_BUSY_SIZE; + unsigned int miu_wc_track_fifo_empty : CP_STAT_MIU_WC_TRACK_FIFO_EMPTY_SIZE; + unsigned int me_wc_busy : CP_STAT_ME_WC_BUSY_SIZE; + unsigned int : 2; + unsigned int me_busy : CP_STAT_ME_BUSY_SIZE; + unsigned int : 2; + unsigned int _3d_busy : CP_STAT__3D_BUSY_SIZE; + unsigned int cp_nrt_busy : CP_STAT_CP_NRT_BUSY_SIZE; + unsigned int miu_wc_stall : CP_STAT_MIU_WC_STALL_SIZE; + unsigned int meq_indirect2_busy : CP_STAT_MEQ_INDIRECT2_BUSY_SIZE; + unsigned int meq_indirects_busy : CP_STAT_MEQ_INDIRECTS_BUSY_SIZE; + unsigned int meq_ring_busy : CP_STAT_MEQ_RING_BUSY_SIZE; + unsigned int pfp_busy : CP_STAT_PFP_BUSY_SIZE; + unsigned int st_queue_busy : CP_STAT_ST_QUEUE_BUSY_SIZE; + unsigned int : 2; + unsigned int indirect2_queue_busy : CP_STAT_INDIRECT2_QUEUE_BUSY_SIZE; + unsigned int indirects_queue_busy : CP_STAT_INDIRECTS_QUEUE_BUSY_SIZE; + unsigned int ring_queue_busy : CP_STAT_RING_QUEUE_BUSY_SIZE; + unsigned int csf_busy : CP_STAT_CSF_BUSY_SIZE; + unsigned int csf_st_busy : CP_STAT_CSF_ST_BUSY_SIZE; + unsigned int : 1; + unsigned int csf_indirect2_busy : CP_STAT_CSF_INDIRECT2_BUSY_SIZE; + unsigned int csf_indirects_busy : CP_STAT_CSF_INDIRECTS_BUSY_SIZE; + unsigned int csf_ring_busy : CP_STAT_CSF_RING_BUSY_SIZE; + unsigned int rciu_busy : CP_STAT_RCIU_BUSY_SIZE; + unsigned int rbiu_busy : CP_STAT_RBIU_BUSY_SIZE; + unsigned int miu_rd_return_busy : CP_STAT_MIU_RD_RETURN_BUSY_SIZE; + unsigned int miu_rd_req_busy : CP_STAT_MIU_RD_REQ_BUSY_SIZE; + unsigned int miu_wr_busy : CP_STAT_MIU_WR_BUSY_SIZE; + } cp_stat_t; + +#endif + +typedef union { + unsigned int val : 32; + cp_stat_t f; +} cp_stat_u; + + +/* + * BIOS_0_SCRATCH struct + */ + +#define BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_0_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_0_SCRATCH_MASK \ + (BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_0_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_0_SCRATCH_GET_BIOS_SCRATCH(bios_0_scratch) \ + ((bios_0_scratch & BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_0_SCRATCH_SET_BIOS_SCRATCH(bios_0_scratch_reg, bios_scratch) \ + bios_0_scratch_reg = (bios_0_scratch_reg & ~BIOS_0_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_0_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_0_scratch_t { + unsigned int bios_scratch : BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_0_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_0_scratch_t { + unsigned int bios_scratch : BIOS_0_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_0_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_0_scratch_t f; +} bios_0_scratch_u; + + +/* + * BIOS_1_SCRATCH struct + */ + +#define BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_1_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_1_SCRATCH_MASK \ + (BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_1_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_1_SCRATCH_GET_BIOS_SCRATCH(bios_1_scratch) \ + ((bios_1_scratch & BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_1_SCRATCH_SET_BIOS_SCRATCH(bios_1_scratch_reg, bios_scratch) \ + bios_1_scratch_reg = (bios_1_scratch_reg & ~BIOS_1_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_1_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_1_scratch_t { + unsigned int bios_scratch : BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_1_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_1_scratch_t { + unsigned int bios_scratch : BIOS_1_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_1_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_1_scratch_t f; +} bios_1_scratch_u; + + +/* + * BIOS_2_SCRATCH struct + */ + +#define BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_2_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_2_SCRATCH_MASK \ + (BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_2_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_2_SCRATCH_GET_BIOS_SCRATCH(bios_2_scratch) \ + ((bios_2_scratch & BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_2_SCRATCH_SET_BIOS_SCRATCH(bios_2_scratch_reg, bios_scratch) \ + bios_2_scratch_reg = (bios_2_scratch_reg & ~BIOS_2_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_2_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_2_scratch_t { + unsigned int bios_scratch : BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_2_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_2_scratch_t { + unsigned int bios_scratch : BIOS_2_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_2_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_2_scratch_t f; +} bios_2_scratch_u; + + +/* + * BIOS_3_SCRATCH struct + */ + +#define BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_3_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_3_SCRATCH_MASK \ + (BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_3_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_3_SCRATCH_GET_BIOS_SCRATCH(bios_3_scratch) \ + ((bios_3_scratch & BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_3_SCRATCH_SET_BIOS_SCRATCH(bios_3_scratch_reg, bios_scratch) \ + bios_3_scratch_reg = (bios_3_scratch_reg & ~BIOS_3_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_3_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_3_scratch_t { + unsigned int bios_scratch : BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_3_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_3_scratch_t { + unsigned int bios_scratch : BIOS_3_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_3_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_3_scratch_t f; +} bios_3_scratch_u; + + +/* + * BIOS_4_SCRATCH struct + */ + +#define BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_4_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_4_SCRATCH_MASK \ + (BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_4_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_4_SCRATCH_GET_BIOS_SCRATCH(bios_4_scratch) \ + ((bios_4_scratch & BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_4_SCRATCH_SET_BIOS_SCRATCH(bios_4_scratch_reg, bios_scratch) \ + bios_4_scratch_reg = (bios_4_scratch_reg & ~BIOS_4_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_4_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_4_scratch_t { + unsigned int bios_scratch : BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_4_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_4_scratch_t { + unsigned int bios_scratch : BIOS_4_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_4_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_4_scratch_t f; +} bios_4_scratch_u; + + +/* + * BIOS_5_SCRATCH struct + */ + +#define BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_5_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_5_SCRATCH_MASK \ + (BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_5_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_5_SCRATCH_GET_BIOS_SCRATCH(bios_5_scratch) \ + ((bios_5_scratch & BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_5_SCRATCH_SET_BIOS_SCRATCH(bios_5_scratch_reg, bios_scratch) \ + bios_5_scratch_reg = (bios_5_scratch_reg & ~BIOS_5_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_5_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_5_scratch_t { + unsigned int bios_scratch : BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_5_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_5_scratch_t { + unsigned int bios_scratch : BIOS_5_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_5_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_5_scratch_t f; +} bios_5_scratch_u; + + +/* + * BIOS_6_SCRATCH struct + */ + +#define BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_6_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_6_SCRATCH_MASK \ + (BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_6_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_6_SCRATCH_GET_BIOS_SCRATCH(bios_6_scratch) \ + ((bios_6_scratch & BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_6_SCRATCH_SET_BIOS_SCRATCH(bios_6_scratch_reg, bios_scratch) \ + bios_6_scratch_reg = (bios_6_scratch_reg & ~BIOS_6_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_6_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_6_scratch_t { + unsigned int bios_scratch : BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_6_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_6_scratch_t { + unsigned int bios_scratch : BIOS_6_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_6_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_6_scratch_t f; +} bios_6_scratch_u; + + +/* + * BIOS_7_SCRATCH struct + */ + +#define BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_7_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_7_SCRATCH_MASK \ + (BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_7_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_7_SCRATCH_GET_BIOS_SCRATCH(bios_7_scratch) \ + ((bios_7_scratch & BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_7_SCRATCH_SET_BIOS_SCRATCH(bios_7_scratch_reg, bios_scratch) \ + bios_7_scratch_reg = (bios_7_scratch_reg & ~BIOS_7_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_7_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_7_scratch_t { + unsigned int bios_scratch : BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_7_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_7_scratch_t { + unsigned int bios_scratch : BIOS_7_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_7_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_7_scratch_t f; +} bios_7_scratch_u; + + +/* + * BIOS_8_SCRATCH struct + */ + +#define BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_8_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_8_SCRATCH_MASK \ + (BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_8_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_8_SCRATCH_GET_BIOS_SCRATCH(bios_8_scratch) \ + ((bios_8_scratch & BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_8_SCRATCH_SET_BIOS_SCRATCH(bios_8_scratch_reg, bios_scratch) \ + bios_8_scratch_reg = (bios_8_scratch_reg & ~BIOS_8_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_8_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_8_scratch_t { + unsigned int bios_scratch : BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_8_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_8_scratch_t { + unsigned int bios_scratch : BIOS_8_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_8_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_8_scratch_t f; +} bios_8_scratch_u; + + +/* + * BIOS_9_SCRATCH struct + */ + +#define BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_9_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_9_SCRATCH_MASK \ + (BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_9_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_9_SCRATCH_GET_BIOS_SCRATCH(bios_9_scratch) \ + ((bios_9_scratch & BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_9_SCRATCH_SET_BIOS_SCRATCH(bios_9_scratch_reg, bios_scratch) \ + bios_9_scratch_reg = (bios_9_scratch_reg & ~BIOS_9_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_9_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_9_scratch_t { + unsigned int bios_scratch : BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_9_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_9_scratch_t { + unsigned int bios_scratch : BIOS_9_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_9_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_9_scratch_t f; +} bios_9_scratch_u; + + +/* + * BIOS_10_SCRATCH struct + */ + +#define BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_10_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_10_SCRATCH_MASK \ + (BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_10_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_10_SCRATCH_GET_BIOS_SCRATCH(bios_10_scratch) \ + ((bios_10_scratch & BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_10_SCRATCH_SET_BIOS_SCRATCH(bios_10_scratch_reg, bios_scratch) \ + bios_10_scratch_reg = (bios_10_scratch_reg & ~BIOS_10_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_10_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_10_scratch_t { + unsigned int bios_scratch : BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_10_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_10_scratch_t { + unsigned int bios_scratch : BIOS_10_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_10_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_10_scratch_t f; +} bios_10_scratch_u; + + +/* + * BIOS_11_SCRATCH struct + */ + +#define BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_11_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_11_SCRATCH_MASK \ + (BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_11_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_11_SCRATCH_GET_BIOS_SCRATCH(bios_11_scratch) \ + ((bios_11_scratch & BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_11_SCRATCH_SET_BIOS_SCRATCH(bios_11_scratch_reg, bios_scratch) \ + bios_11_scratch_reg = (bios_11_scratch_reg & ~BIOS_11_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_11_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_11_scratch_t { + unsigned int bios_scratch : BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_11_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_11_scratch_t { + unsigned int bios_scratch : BIOS_11_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_11_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_11_scratch_t f; +} bios_11_scratch_u; + + +/* + * BIOS_12_SCRATCH struct + */ + +#define BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_12_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_12_SCRATCH_MASK \ + (BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_12_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_12_SCRATCH_GET_BIOS_SCRATCH(bios_12_scratch) \ + ((bios_12_scratch & BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_12_SCRATCH_SET_BIOS_SCRATCH(bios_12_scratch_reg, bios_scratch) \ + bios_12_scratch_reg = (bios_12_scratch_reg & ~BIOS_12_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_12_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_12_scratch_t { + unsigned int bios_scratch : BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_12_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_12_scratch_t { + unsigned int bios_scratch : BIOS_12_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_12_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_12_scratch_t f; +} bios_12_scratch_u; + + +/* + * BIOS_13_SCRATCH struct + */ + +#define BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_13_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_13_SCRATCH_MASK \ + (BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_13_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_13_SCRATCH_GET_BIOS_SCRATCH(bios_13_scratch) \ + ((bios_13_scratch & BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_13_SCRATCH_SET_BIOS_SCRATCH(bios_13_scratch_reg, bios_scratch) \ + bios_13_scratch_reg = (bios_13_scratch_reg & ~BIOS_13_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_13_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_13_scratch_t { + unsigned int bios_scratch : BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_13_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_13_scratch_t { + unsigned int bios_scratch : BIOS_13_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_13_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_13_scratch_t f; +} bios_13_scratch_u; + + +/* + * BIOS_14_SCRATCH struct + */ + +#define BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_14_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_14_SCRATCH_MASK \ + (BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_14_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_14_SCRATCH_GET_BIOS_SCRATCH(bios_14_scratch) \ + ((bios_14_scratch & BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_14_SCRATCH_SET_BIOS_SCRATCH(bios_14_scratch_reg, bios_scratch) \ + bios_14_scratch_reg = (bios_14_scratch_reg & ~BIOS_14_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_14_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_14_scratch_t { + unsigned int bios_scratch : BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_14_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_14_scratch_t { + unsigned int bios_scratch : BIOS_14_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_14_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_14_scratch_t f; +} bios_14_scratch_u; + + +/* + * BIOS_15_SCRATCH struct + */ + +#define BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE 32 + +#define BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT 0 + +#define BIOS_15_SCRATCH_BIOS_SCRATCH_MASK 0xffffffff + +#define BIOS_15_SCRATCH_MASK \ + (BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) + +#define BIOS_15_SCRATCH(bios_scratch) \ + ((bios_scratch << BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT)) + +#define BIOS_15_SCRATCH_GET_BIOS_SCRATCH(bios_15_scratch) \ + ((bios_15_scratch & BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) >> BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT) + +#define BIOS_15_SCRATCH_SET_BIOS_SCRATCH(bios_15_scratch_reg, bios_scratch) \ + bios_15_scratch_reg = (bios_15_scratch_reg & ~BIOS_15_SCRATCH_BIOS_SCRATCH_MASK) | (bios_scratch << BIOS_15_SCRATCH_BIOS_SCRATCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bios_15_scratch_t { + unsigned int bios_scratch : BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_15_scratch_t; + +#else // !BIGENDIAN_OS + + typedef struct _bios_15_scratch_t { + unsigned int bios_scratch : BIOS_15_SCRATCH_BIOS_SCRATCH_SIZE; + } bios_15_scratch_t; + +#endif + +typedef union { + unsigned int val : 32; + bios_15_scratch_t f; +} bios_15_scratch_u; + + +/* + * COHER_SIZE_PM4 struct + */ + +#define COHER_SIZE_PM4_SIZE_SIZE 32 + +#define COHER_SIZE_PM4_SIZE_SHIFT 0 + +#define COHER_SIZE_PM4_SIZE_MASK 0xffffffff + +#define COHER_SIZE_PM4_MASK \ + (COHER_SIZE_PM4_SIZE_MASK) + +#define COHER_SIZE_PM4(size) \ + ((size << COHER_SIZE_PM4_SIZE_SHIFT)) + +#define COHER_SIZE_PM4_GET_SIZE(coher_size_pm4) \ + ((coher_size_pm4 & COHER_SIZE_PM4_SIZE_MASK) >> COHER_SIZE_PM4_SIZE_SHIFT) + +#define COHER_SIZE_PM4_SET_SIZE(coher_size_pm4_reg, size) \ + coher_size_pm4_reg = (coher_size_pm4_reg & ~COHER_SIZE_PM4_SIZE_MASK) | (size << COHER_SIZE_PM4_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_size_pm4_t { + unsigned int size : COHER_SIZE_PM4_SIZE_SIZE; + } coher_size_pm4_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_size_pm4_t { + unsigned int size : COHER_SIZE_PM4_SIZE_SIZE; + } coher_size_pm4_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_size_pm4_t f; +} coher_size_pm4_u; + + +/* + * COHER_BASE_PM4 struct + */ + +#define COHER_BASE_PM4_BASE_SIZE 32 + +#define COHER_BASE_PM4_BASE_SHIFT 0 + +#define COHER_BASE_PM4_BASE_MASK 0xffffffff + +#define COHER_BASE_PM4_MASK \ + (COHER_BASE_PM4_BASE_MASK) + +#define COHER_BASE_PM4(base) \ + ((base << COHER_BASE_PM4_BASE_SHIFT)) + +#define COHER_BASE_PM4_GET_BASE(coher_base_pm4) \ + ((coher_base_pm4 & COHER_BASE_PM4_BASE_MASK) >> COHER_BASE_PM4_BASE_SHIFT) + +#define COHER_BASE_PM4_SET_BASE(coher_base_pm4_reg, base) \ + coher_base_pm4_reg = (coher_base_pm4_reg & ~COHER_BASE_PM4_BASE_MASK) | (base << COHER_BASE_PM4_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_base_pm4_t { + unsigned int base : COHER_BASE_PM4_BASE_SIZE; + } coher_base_pm4_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_base_pm4_t { + unsigned int base : COHER_BASE_PM4_BASE_SIZE; + } coher_base_pm4_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_base_pm4_t f; +} coher_base_pm4_u; + + +/* + * COHER_STATUS_PM4 struct + */ + +#define COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE 8 +#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE 1 +#define COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE 1 +#define COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SIZE 1 +#define COHER_STATUS_PM4_TC_ACTION_ENA_SIZE 1 +#define COHER_STATUS_PM4_STATUS_SIZE 1 + +#define COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT 0 +#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT 8 +#define COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT 9 +#define COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT 10 +#define COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT 11 +#define COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT 12 +#define COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT 13 +#define COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT 14 +#define COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT 15 +#define COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT 16 +#define COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT 17 +#define COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT 25 +#define COHER_STATUS_PM4_STATUS_SHIFT 31 + +#define COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK 0x000000ff +#define COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK 0x00000100 +#define COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK 0x00000200 +#define COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK 0x00000400 +#define COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK 0x00000800 +#define COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK 0x00001000 +#define COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK 0x00002000 +#define COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK 0x00004000 +#define COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK 0x00008000 +#define COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK 0x00010000 +#define COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK 0x00020000 +#define COHER_STATUS_PM4_TC_ACTION_ENA_MASK 0x02000000 +#define COHER_STATUS_PM4_STATUS_MASK 0x80000000 + +#define COHER_STATUS_PM4_MASK \ + (COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK | \ + COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK | \ + COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK | \ + COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK | \ + COHER_STATUS_PM4_TC_ACTION_ENA_MASK | \ + COHER_STATUS_PM4_STATUS_MASK) + +#define COHER_STATUS_PM4(matching_contexts, rb_copy_dest_base_ena, dest_base_0_ena, dest_base_1_ena, dest_base_2_ena, dest_base_3_ena, dest_base_4_ena, dest_base_5_ena, dest_base_6_ena, dest_base_7_ena, rb_color_info_ena, tc_action_ena, status) \ + ((matching_contexts << COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT) | \ + (rb_copy_dest_base_ena << COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT) | \ + (dest_base_0_ena << COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT) | \ + (dest_base_1_ena << COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT) | \ + (dest_base_2_ena << COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT) | \ + (dest_base_3_ena << COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT) | \ + (dest_base_4_ena << COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT) | \ + (dest_base_5_ena << COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT) | \ + (dest_base_6_ena << COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT) | \ + (dest_base_7_ena << COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT) | \ + (rb_color_info_ena << COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT) | \ + (tc_action_ena << COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT) | \ + (status << COHER_STATUS_PM4_STATUS_SHIFT)) + +#define COHER_STATUS_PM4_GET_MATCHING_CONTEXTS(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK) >> COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT) +#define COHER_STATUS_PM4_GET_RB_COPY_DEST_BASE_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK) >> COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_0_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_1_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_2_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_3_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_4_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_5_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_6_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_DEST_BASE_7_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK) >> COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_RB_COLOR_INFO_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK) >> COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_TC_ACTION_ENA(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_TC_ACTION_ENA_MASK) >> COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT) +#define COHER_STATUS_PM4_GET_STATUS(coher_status_pm4) \ + ((coher_status_pm4 & COHER_STATUS_PM4_STATUS_MASK) >> COHER_STATUS_PM4_STATUS_SHIFT) + +#define COHER_STATUS_PM4_SET_MATCHING_CONTEXTS(coher_status_pm4_reg, matching_contexts) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_MATCHING_CONTEXTS_MASK) | (matching_contexts << COHER_STATUS_PM4_MATCHING_CONTEXTS_SHIFT) +#define COHER_STATUS_PM4_SET_RB_COPY_DEST_BASE_ENA(coher_status_pm4_reg, rb_copy_dest_base_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_MASK) | (rb_copy_dest_base_ena << COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_0_ENA(coher_status_pm4_reg, dest_base_0_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_0_ENA_MASK) | (dest_base_0_ena << COHER_STATUS_PM4_DEST_BASE_0_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_1_ENA(coher_status_pm4_reg, dest_base_1_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_1_ENA_MASK) | (dest_base_1_ena << COHER_STATUS_PM4_DEST_BASE_1_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_2_ENA(coher_status_pm4_reg, dest_base_2_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_2_ENA_MASK) | (dest_base_2_ena << COHER_STATUS_PM4_DEST_BASE_2_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_3_ENA(coher_status_pm4_reg, dest_base_3_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_3_ENA_MASK) | (dest_base_3_ena << COHER_STATUS_PM4_DEST_BASE_3_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_4_ENA(coher_status_pm4_reg, dest_base_4_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_4_ENA_MASK) | (dest_base_4_ena << COHER_STATUS_PM4_DEST_BASE_4_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_5_ENA(coher_status_pm4_reg, dest_base_5_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_5_ENA_MASK) | (dest_base_5_ena << COHER_STATUS_PM4_DEST_BASE_5_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_6_ENA(coher_status_pm4_reg, dest_base_6_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_6_ENA_MASK) | (dest_base_6_ena << COHER_STATUS_PM4_DEST_BASE_6_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_DEST_BASE_7_ENA(coher_status_pm4_reg, dest_base_7_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_DEST_BASE_7_ENA_MASK) | (dest_base_7_ena << COHER_STATUS_PM4_DEST_BASE_7_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_RB_COLOR_INFO_ENA(coher_status_pm4_reg, rb_color_info_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_RB_COLOR_INFO_ENA_MASK) | (rb_color_info_ena << COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_TC_ACTION_ENA(coher_status_pm4_reg, tc_action_ena) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_TC_ACTION_ENA_MASK) | (tc_action_ena << COHER_STATUS_PM4_TC_ACTION_ENA_SHIFT) +#define COHER_STATUS_PM4_SET_STATUS(coher_status_pm4_reg, status) \ + coher_status_pm4_reg = (coher_status_pm4_reg & ~COHER_STATUS_PM4_STATUS_MASK) | (status << COHER_STATUS_PM4_STATUS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_status_pm4_t { + unsigned int matching_contexts : COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE; + unsigned int rb_copy_dest_base_ena : COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE; + unsigned int dest_base_0_ena : COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE; + unsigned int dest_base_1_ena : COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE; + unsigned int dest_base_2_ena : COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE; + unsigned int dest_base_3_ena : COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE; + unsigned int dest_base_4_ena : COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE; + unsigned int dest_base_5_ena : COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE; + unsigned int dest_base_6_ena : COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE; + unsigned int dest_base_7_ena : COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE; + unsigned int rb_color_info_ena : COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SIZE; + unsigned int : 7; + unsigned int tc_action_ena : COHER_STATUS_PM4_TC_ACTION_ENA_SIZE; + unsigned int : 5; + unsigned int status : COHER_STATUS_PM4_STATUS_SIZE; + } coher_status_pm4_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_status_pm4_t { + unsigned int status : COHER_STATUS_PM4_STATUS_SIZE; + unsigned int : 5; + unsigned int tc_action_ena : COHER_STATUS_PM4_TC_ACTION_ENA_SIZE; + unsigned int : 7; + unsigned int rb_color_info_ena : COHER_STATUS_PM4_RB_COLOR_INFO_ENA_SIZE; + unsigned int dest_base_7_ena : COHER_STATUS_PM4_DEST_BASE_7_ENA_SIZE; + unsigned int dest_base_6_ena : COHER_STATUS_PM4_DEST_BASE_6_ENA_SIZE; + unsigned int dest_base_5_ena : COHER_STATUS_PM4_DEST_BASE_5_ENA_SIZE; + unsigned int dest_base_4_ena : COHER_STATUS_PM4_DEST_BASE_4_ENA_SIZE; + unsigned int dest_base_3_ena : COHER_STATUS_PM4_DEST_BASE_3_ENA_SIZE; + unsigned int dest_base_2_ena : COHER_STATUS_PM4_DEST_BASE_2_ENA_SIZE; + unsigned int dest_base_1_ena : COHER_STATUS_PM4_DEST_BASE_1_ENA_SIZE; + unsigned int dest_base_0_ena : COHER_STATUS_PM4_DEST_BASE_0_ENA_SIZE; + unsigned int rb_copy_dest_base_ena : COHER_STATUS_PM4_RB_COPY_DEST_BASE_ENA_SIZE; + unsigned int matching_contexts : COHER_STATUS_PM4_MATCHING_CONTEXTS_SIZE; + } coher_status_pm4_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_status_pm4_t f; +} coher_status_pm4_u; + + +/* + * COHER_SIZE_HOST struct + */ + +#define COHER_SIZE_HOST_SIZE_SIZE 32 + +#define COHER_SIZE_HOST_SIZE_SHIFT 0 + +#define COHER_SIZE_HOST_SIZE_MASK 0xffffffff + +#define COHER_SIZE_HOST_MASK \ + (COHER_SIZE_HOST_SIZE_MASK) + +#define COHER_SIZE_HOST(size) \ + ((size << COHER_SIZE_HOST_SIZE_SHIFT)) + +#define COHER_SIZE_HOST_GET_SIZE(coher_size_host) \ + ((coher_size_host & COHER_SIZE_HOST_SIZE_MASK) >> COHER_SIZE_HOST_SIZE_SHIFT) + +#define COHER_SIZE_HOST_SET_SIZE(coher_size_host_reg, size) \ + coher_size_host_reg = (coher_size_host_reg & ~COHER_SIZE_HOST_SIZE_MASK) | (size << COHER_SIZE_HOST_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_size_host_t { + unsigned int size : COHER_SIZE_HOST_SIZE_SIZE; + } coher_size_host_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_size_host_t { + unsigned int size : COHER_SIZE_HOST_SIZE_SIZE; + } coher_size_host_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_size_host_t f; +} coher_size_host_u; + + +/* + * COHER_BASE_HOST struct + */ + +#define COHER_BASE_HOST_BASE_SIZE 32 + +#define COHER_BASE_HOST_BASE_SHIFT 0 + +#define COHER_BASE_HOST_BASE_MASK 0xffffffff + +#define COHER_BASE_HOST_MASK \ + (COHER_BASE_HOST_BASE_MASK) + +#define COHER_BASE_HOST(base) \ + ((base << COHER_BASE_HOST_BASE_SHIFT)) + +#define COHER_BASE_HOST_GET_BASE(coher_base_host) \ + ((coher_base_host & COHER_BASE_HOST_BASE_MASK) >> COHER_BASE_HOST_BASE_SHIFT) + +#define COHER_BASE_HOST_SET_BASE(coher_base_host_reg, base) \ + coher_base_host_reg = (coher_base_host_reg & ~COHER_BASE_HOST_BASE_MASK) | (base << COHER_BASE_HOST_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_base_host_t { + unsigned int base : COHER_BASE_HOST_BASE_SIZE; + } coher_base_host_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_base_host_t { + unsigned int base : COHER_BASE_HOST_BASE_SIZE; + } coher_base_host_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_base_host_t f; +} coher_base_host_u; + + +/* + * COHER_STATUS_HOST struct + */ + +#define COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE 8 +#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE 1 +#define COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE 1 +#define COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SIZE 1 +#define COHER_STATUS_HOST_TC_ACTION_ENA_SIZE 1 +#define COHER_STATUS_HOST_STATUS_SIZE 1 + +#define COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT 0 +#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT 8 +#define COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT 9 +#define COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT 10 +#define COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT 11 +#define COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT 12 +#define COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT 13 +#define COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT 14 +#define COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT 15 +#define COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT 16 +#define COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT 17 +#define COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT 25 +#define COHER_STATUS_HOST_STATUS_SHIFT 31 + +#define COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK 0x000000ff +#define COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK 0x00000100 +#define COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK 0x00000200 +#define COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK 0x00000400 +#define COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK 0x00000800 +#define COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK 0x00001000 +#define COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK 0x00002000 +#define COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK 0x00004000 +#define COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK 0x00008000 +#define COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK 0x00010000 +#define COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK 0x00020000 +#define COHER_STATUS_HOST_TC_ACTION_ENA_MASK 0x02000000 +#define COHER_STATUS_HOST_STATUS_MASK 0x80000000 + +#define COHER_STATUS_HOST_MASK \ + (COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK | \ + COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK | \ + COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK | \ + COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK | \ + COHER_STATUS_HOST_TC_ACTION_ENA_MASK | \ + COHER_STATUS_HOST_STATUS_MASK) + +#define COHER_STATUS_HOST(matching_contexts, rb_copy_dest_base_ena, dest_base_0_ena, dest_base_1_ena, dest_base_2_ena, dest_base_3_ena, dest_base_4_ena, dest_base_5_ena, dest_base_6_ena, dest_base_7_ena, rb_color_info_ena, tc_action_ena, status) \ + ((matching_contexts << COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT) | \ + (rb_copy_dest_base_ena << COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT) | \ + (dest_base_0_ena << COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT) | \ + (dest_base_1_ena << COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT) | \ + (dest_base_2_ena << COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT) | \ + (dest_base_3_ena << COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT) | \ + (dest_base_4_ena << COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT) | \ + (dest_base_5_ena << COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT) | \ + (dest_base_6_ena << COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT) | \ + (dest_base_7_ena << COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT) | \ + (rb_color_info_ena << COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT) | \ + (tc_action_ena << COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT) | \ + (status << COHER_STATUS_HOST_STATUS_SHIFT)) + +#define COHER_STATUS_HOST_GET_MATCHING_CONTEXTS(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK) >> COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT) +#define COHER_STATUS_HOST_GET_RB_COPY_DEST_BASE_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK) >> COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_0_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_1_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_2_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_3_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_4_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_5_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_6_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_DEST_BASE_7_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK) >> COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_RB_COLOR_INFO_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK) >> COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_TC_ACTION_ENA(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_TC_ACTION_ENA_MASK) >> COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT) +#define COHER_STATUS_HOST_GET_STATUS(coher_status_host) \ + ((coher_status_host & COHER_STATUS_HOST_STATUS_MASK) >> COHER_STATUS_HOST_STATUS_SHIFT) + +#define COHER_STATUS_HOST_SET_MATCHING_CONTEXTS(coher_status_host_reg, matching_contexts) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_MATCHING_CONTEXTS_MASK) | (matching_contexts << COHER_STATUS_HOST_MATCHING_CONTEXTS_SHIFT) +#define COHER_STATUS_HOST_SET_RB_COPY_DEST_BASE_ENA(coher_status_host_reg, rb_copy_dest_base_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_MASK) | (rb_copy_dest_base_ena << COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_0_ENA(coher_status_host_reg, dest_base_0_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_0_ENA_MASK) | (dest_base_0_ena << COHER_STATUS_HOST_DEST_BASE_0_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_1_ENA(coher_status_host_reg, dest_base_1_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_1_ENA_MASK) | (dest_base_1_ena << COHER_STATUS_HOST_DEST_BASE_1_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_2_ENA(coher_status_host_reg, dest_base_2_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_2_ENA_MASK) | (dest_base_2_ena << COHER_STATUS_HOST_DEST_BASE_2_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_3_ENA(coher_status_host_reg, dest_base_3_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_3_ENA_MASK) | (dest_base_3_ena << COHER_STATUS_HOST_DEST_BASE_3_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_4_ENA(coher_status_host_reg, dest_base_4_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_4_ENA_MASK) | (dest_base_4_ena << COHER_STATUS_HOST_DEST_BASE_4_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_5_ENA(coher_status_host_reg, dest_base_5_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_5_ENA_MASK) | (dest_base_5_ena << COHER_STATUS_HOST_DEST_BASE_5_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_6_ENA(coher_status_host_reg, dest_base_6_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_6_ENA_MASK) | (dest_base_6_ena << COHER_STATUS_HOST_DEST_BASE_6_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_DEST_BASE_7_ENA(coher_status_host_reg, dest_base_7_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_DEST_BASE_7_ENA_MASK) | (dest_base_7_ena << COHER_STATUS_HOST_DEST_BASE_7_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_RB_COLOR_INFO_ENA(coher_status_host_reg, rb_color_info_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_RB_COLOR_INFO_ENA_MASK) | (rb_color_info_ena << COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_TC_ACTION_ENA(coher_status_host_reg, tc_action_ena) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_TC_ACTION_ENA_MASK) | (tc_action_ena << COHER_STATUS_HOST_TC_ACTION_ENA_SHIFT) +#define COHER_STATUS_HOST_SET_STATUS(coher_status_host_reg, status) \ + coher_status_host_reg = (coher_status_host_reg & ~COHER_STATUS_HOST_STATUS_MASK) | (status << COHER_STATUS_HOST_STATUS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_status_host_t { + unsigned int matching_contexts : COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE; + unsigned int rb_copy_dest_base_ena : COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE; + unsigned int dest_base_0_ena : COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE; + unsigned int dest_base_1_ena : COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE; + unsigned int dest_base_2_ena : COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE; + unsigned int dest_base_3_ena : COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE; + unsigned int dest_base_4_ena : COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE; + unsigned int dest_base_5_ena : COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE; + unsigned int dest_base_6_ena : COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE; + unsigned int dest_base_7_ena : COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE; + unsigned int rb_color_info_ena : COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SIZE; + unsigned int : 7; + unsigned int tc_action_ena : COHER_STATUS_HOST_TC_ACTION_ENA_SIZE; + unsigned int : 5; + unsigned int status : COHER_STATUS_HOST_STATUS_SIZE; + } coher_status_host_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_status_host_t { + unsigned int status : COHER_STATUS_HOST_STATUS_SIZE; + unsigned int : 5; + unsigned int tc_action_ena : COHER_STATUS_HOST_TC_ACTION_ENA_SIZE; + unsigned int : 7; + unsigned int rb_color_info_ena : COHER_STATUS_HOST_RB_COLOR_INFO_ENA_SIZE; + unsigned int dest_base_7_ena : COHER_STATUS_HOST_DEST_BASE_7_ENA_SIZE; + unsigned int dest_base_6_ena : COHER_STATUS_HOST_DEST_BASE_6_ENA_SIZE; + unsigned int dest_base_5_ena : COHER_STATUS_HOST_DEST_BASE_5_ENA_SIZE; + unsigned int dest_base_4_ena : COHER_STATUS_HOST_DEST_BASE_4_ENA_SIZE; + unsigned int dest_base_3_ena : COHER_STATUS_HOST_DEST_BASE_3_ENA_SIZE; + unsigned int dest_base_2_ena : COHER_STATUS_HOST_DEST_BASE_2_ENA_SIZE; + unsigned int dest_base_1_ena : COHER_STATUS_HOST_DEST_BASE_1_ENA_SIZE; + unsigned int dest_base_0_ena : COHER_STATUS_HOST_DEST_BASE_0_ENA_SIZE; + unsigned int rb_copy_dest_base_ena : COHER_STATUS_HOST_RB_COPY_DEST_BASE_ENA_SIZE; + unsigned int matching_contexts : COHER_STATUS_HOST_MATCHING_CONTEXTS_SIZE; + } coher_status_host_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_status_host_t f; +} coher_status_host_u; + + +/* + * COHER_DEST_BASE_0 struct + */ + +#define COHER_DEST_BASE_0_DEST_BASE_0_SIZE 20 + +#define COHER_DEST_BASE_0_DEST_BASE_0_SHIFT 12 + +#define COHER_DEST_BASE_0_DEST_BASE_0_MASK 0xfffff000 + +#define COHER_DEST_BASE_0_MASK \ + (COHER_DEST_BASE_0_DEST_BASE_0_MASK) + +#define COHER_DEST_BASE_0(dest_base_0) \ + ((dest_base_0 << COHER_DEST_BASE_0_DEST_BASE_0_SHIFT)) + +#define COHER_DEST_BASE_0_GET_DEST_BASE_0(coher_dest_base_0) \ + ((coher_dest_base_0 & COHER_DEST_BASE_0_DEST_BASE_0_MASK) >> COHER_DEST_BASE_0_DEST_BASE_0_SHIFT) + +#define COHER_DEST_BASE_0_SET_DEST_BASE_0(coher_dest_base_0_reg, dest_base_0) \ + coher_dest_base_0_reg = (coher_dest_base_0_reg & ~COHER_DEST_BASE_0_DEST_BASE_0_MASK) | (dest_base_0 << COHER_DEST_BASE_0_DEST_BASE_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_0_t { + unsigned int : 12; + unsigned int dest_base_0 : COHER_DEST_BASE_0_DEST_BASE_0_SIZE; + } coher_dest_base_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_0_t { + unsigned int dest_base_0 : COHER_DEST_BASE_0_DEST_BASE_0_SIZE; + unsigned int : 12; + } coher_dest_base_0_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_0_t f; +} coher_dest_base_0_u; + + +/* + * COHER_DEST_BASE_1 struct + */ + +#define COHER_DEST_BASE_1_DEST_BASE_1_SIZE 20 + +#define COHER_DEST_BASE_1_DEST_BASE_1_SHIFT 12 + +#define COHER_DEST_BASE_1_DEST_BASE_1_MASK 0xfffff000 + +#define COHER_DEST_BASE_1_MASK \ + (COHER_DEST_BASE_1_DEST_BASE_1_MASK) + +#define COHER_DEST_BASE_1(dest_base_1) \ + ((dest_base_1 << COHER_DEST_BASE_1_DEST_BASE_1_SHIFT)) + +#define COHER_DEST_BASE_1_GET_DEST_BASE_1(coher_dest_base_1) \ + ((coher_dest_base_1 & COHER_DEST_BASE_1_DEST_BASE_1_MASK) >> COHER_DEST_BASE_1_DEST_BASE_1_SHIFT) + +#define COHER_DEST_BASE_1_SET_DEST_BASE_1(coher_dest_base_1_reg, dest_base_1) \ + coher_dest_base_1_reg = (coher_dest_base_1_reg & ~COHER_DEST_BASE_1_DEST_BASE_1_MASK) | (dest_base_1 << COHER_DEST_BASE_1_DEST_BASE_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_1_t { + unsigned int : 12; + unsigned int dest_base_1 : COHER_DEST_BASE_1_DEST_BASE_1_SIZE; + } coher_dest_base_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_1_t { + unsigned int dest_base_1 : COHER_DEST_BASE_1_DEST_BASE_1_SIZE; + unsigned int : 12; + } coher_dest_base_1_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_1_t f; +} coher_dest_base_1_u; + + +/* + * COHER_DEST_BASE_2 struct + */ + +#define COHER_DEST_BASE_2_DEST_BASE_2_SIZE 20 + +#define COHER_DEST_BASE_2_DEST_BASE_2_SHIFT 12 + +#define COHER_DEST_BASE_2_DEST_BASE_2_MASK 0xfffff000 + +#define COHER_DEST_BASE_2_MASK \ + (COHER_DEST_BASE_2_DEST_BASE_2_MASK) + +#define COHER_DEST_BASE_2(dest_base_2) \ + ((dest_base_2 << COHER_DEST_BASE_2_DEST_BASE_2_SHIFT)) + +#define COHER_DEST_BASE_2_GET_DEST_BASE_2(coher_dest_base_2) \ + ((coher_dest_base_2 & COHER_DEST_BASE_2_DEST_BASE_2_MASK) >> COHER_DEST_BASE_2_DEST_BASE_2_SHIFT) + +#define COHER_DEST_BASE_2_SET_DEST_BASE_2(coher_dest_base_2_reg, dest_base_2) \ + coher_dest_base_2_reg = (coher_dest_base_2_reg & ~COHER_DEST_BASE_2_DEST_BASE_2_MASK) | (dest_base_2 << COHER_DEST_BASE_2_DEST_BASE_2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_2_t { + unsigned int : 12; + unsigned int dest_base_2 : COHER_DEST_BASE_2_DEST_BASE_2_SIZE; + } coher_dest_base_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_2_t { + unsigned int dest_base_2 : COHER_DEST_BASE_2_DEST_BASE_2_SIZE; + unsigned int : 12; + } coher_dest_base_2_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_2_t f; +} coher_dest_base_2_u; + + +/* + * COHER_DEST_BASE_3 struct + */ + +#define COHER_DEST_BASE_3_DEST_BASE_3_SIZE 20 + +#define COHER_DEST_BASE_3_DEST_BASE_3_SHIFT 12 + +#define COHER_DEST_BASE_3_DEST_BASE_3_MASK 0xfffff000 + +#define COHER_DEST_BASE_3_MASK \ + (COHER_DEST_BASE_3_DEST_BASE_3_MASK) + +#define COHER_DEST_BASE_3(dest_base_3) \ + ((dest_base_3 << COHER_DEST_BASE_3_DEST_BASE_3_SHIFT)) + +#define COHER_DEST_BASE_3_GET_DEST_BASE_3(coher_dest_base_3) \ + ((coher_dest_base_3 & COHER_DEST_BASE_3_DEST_BASE_3_MASK) >> COHER_DEST_BASE_3_DEST_BASE_3_SHIFT) + +#define COHER_DEST_BASE_3_SET_DEST_BASE_3(coher_dest_base_3_reg, dest_base_3) \ + coher_dest_base_3_reg = (coher_dest_base_3_reg & ~COHER_DEST_BASE_3_DEST_BASE_3_MASK) | (dest_base_3 << COHER_DEST_BASE_3_DEST_BASE_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_3_t { + unsigned int : 12; + unsigned int dest_base_3 : COHER_DEST_BASE_3_DEST_BASE_3_SIZE; + } coher_dest_base_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_3_t { + unsigned int dest_base_3 : COHER_DEST_BASE_3_DEST_BASE_3_SIZE; + unsigned int : 12; + } coher_dest_base_3_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_3_t f; +} coher_dest_base_3_u; + + +/* + * COHER_DEST_BASE_4 struct + */ + +#define COHER_DEST_BASE_4_DEST_BASE_4_SIZE 20 + +#define COHER_DEST_BASE_4_DEST_BASE_4_SHIFT 12 + +#define COHER_DEST_BASE_4_DEST_BASE_4_MASK 0xfffff000 + +#define COHER_DEST_BASE_4_MASK \ + (COHER_DEST_BASE_4_DEST_BASE_4_MASK) + +#define COHER_DEST_BASE_4(dest_base_4) \ + ((dest_base_4 << COHER_DEST_BASE_4_DEST_BASE_4_SHIFT)) + +#define COHER_DEST_BASE_4_GET_DEST_BASE_4(coher_dest_base_4) \ + ((coher_dest_base_4 & COHER_DEST_BASE_4_DEST_BASE_4_MASK) >> COHER_DEST_BASE_4_DEST_BASE_4_SHIFT) + +#define COHER_DEST_BASE_4_SET_DEST_BASE_4(coher_dest_base_4_reg, dest_base_4) \ + coher_dest_base_4_reg = (coher_dest_base_4_reg & ~COHER_DEST_BASE_4_DEST_BASE_4_MASK) | (dest_base_4 << COHER_DEST_BASE_4_DEST_BASE_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_4_t { + unsigned int : 12; + unsigned int dest_base_4 : COHER_DEST_BASE_4_DEST_BASE_4_SIZE; + } coher_dest_base_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_4_t { + unsigned int dest_base_4 : COHER_DEST_BASE_4_DEST_BASE_4_SIZE; + unsigned int : 12; + } coher_dest_base_4_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_4_t f; +} coher_dest_base_4_u; + + +/* + * COHER_DEST_BASE_5 struct + */ + +#define COHER_DEST_BASE_5_DEST_BASE_5_SIZE 20 + +#define COHER_DEST_BASE_5_DEST_BASE_5_SHIFT 12 + +#define COHER_DEST_BASE_5_DEST_BASE_5_MASK 0xfffff000 + +#define COHER_DEST_BASE_5_MASK \ + (COHER_DEST_BASE_5_DEST_BASE_5_MASK) + +#define COHER_DEST_BASE_5(dest_base_5) \ + ((dest_base_5 << COHER_DEST_BASE_5_DEST_BASE_5_SHIFT)) + +#define COHER_DEST_BASE_5_GET_DEST_BASE_5(coher_dest_base_5) \ + ((coher_dest_base_5 & COHER_DEST_BASE_5_DEST_BASE_5_MASK) >> COHER_DEST_BASE_5_DEST_BASE_5_SHIFT) + +#define COHER_DEST_BASE_5_SET_DEST_BASE_5(coher_dest_base_5_reg, dest_base_5) \ + coher_dest_base_5_reg = (coher_dest_base_5_reg & ~COHER_DEST_BASE_5_DEST_BASE_5_MASK) | (dest_base_5 << COHER_DEST_BASE_5_DEST_BASE_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_5_t { + unsigned int : 12; + unsigned int dest_base_5 : COHER_DEST_BASE_5_DEST_BASE_5_SIZE; + } coher_dest_base_5_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_5_t { + unsigned int dest_base_5 : COHER_DEST_BASE_5_DEST_BASE_5_SIZE; + unsigned int : 12; + } coher_dest_base_5_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_5_t f; +} coher_dest_base_5_u; + + +/* + * COHER_DEST_BASE_6 struct + */ + +#define COHER_DEST_BASE_6_DEST_BASE_6_SIZE 20 + +#define COHER_DEST_BASE_6_DEST_BASE_6_SHIFT 12 + +#define COHER_DEST_BASE_6_DEST_BASE_6_MASK 0xfffff000 + +#define COHER_DEST_BASE_6_MASK \ + (COHER_DEST_BASE_6_DEST_BASE_6_MASK) + +#define COHER_DEST_BASE_6(dest_base_6) \ + ((dest_base_6 << COHER_DEST_BASE_6_DEST_BASE_6_SHIFT)) + +#define COHER_DEST_BASE_6_GET_DEST_BASE_6(coher_dest_base_6) \ + ((coher_dest_base_6 & COHER_DEST_BASE_6_DEST_BASE_6_MASK) >> COHER_DEST_BASE_6_DEST_BASE_6_SHIFT) + +#define COHER_DEST_BASE_6_SET_DEST_BASE_6(coher_dest_base_6_reg, dest_base_6) \ + coher_dest_base_6_reg = (coher_dest_base_6_reg & ~COHER_DEST_BASE_6_DEST_BASE_6_MASK) | (dest_base_6 << COHER_DEST_BASE_6_DEST_BASE_6_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_6_t { + unsigned int : 12; + unsigned int dest_base_6 : COHER_DEST_BASE_6_DEST_BASE_6_SIZE; + } coher_dest_base_6_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_6_t { + unsigned int dest_base_6 : COHER_DEST_BASE_6_DEST_BASE_6_SIZE; + unsigned int : 12; + } coher_dest_base_6_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_6_t f; +} coher_dest_base_6_u; + + +/* + * COHER_DEST_BASE_7 struct + */ + +#define COHER_DEST_BASE_7_DEST_BASE_7_SIZE 20 + +#define COHER_DEST_BASE_7_DEST_BASE_7_SHIFT 12 + +#define COHER_DEST_BASE_7_DEST_BASE_7_MASK 0xfffff000 + +#define COHER_DEST_BASE_7_MASK \ + (COHER_DEST_BASE_7_DEST_BASE_7_MASK) + +#define COHER_DEST_BASE_7(dest_base_7) \ + ((dest_base_7 << COHER_DEST_BASE_7_DEST_BASE_7_SHIFT)) + +#define COHER_DEST_BASE_7_GET_DEST_BASE_7(coher_dest_base_7) \ + ((coher_dest_base_7 & COHER_DEST_BASE_7_DEST_BASE_7_MASK) >> COHER_DEST_BASE_7_DEST_BASE_7_SHIFT) + +#define COHER_DEST_BASE_7_SET_DEST_BASE_7(coher_dest_base_7_reg, dest_base_7) \ + coher_dest_base_7_reg = (coher_dest_base_7_reg & ~COHER_DEST_BASE_7_DEST_BASE_7_MASK) | (dest_base_7 << COHER_DEST_BASE_7_DEST_BASE_7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _coher_dest_base_7_t { + unsigned int : 12; + unsigned int dest_base_7 : COHER_DEST_BASE_7_DEST_BASE_7_SIZE; + } coher_dest_base_7_t; + +#else // !BIGENDIAN_OS + + typedef struct _coher_dest_base_7_t { + unsigned int dest_base_7 : COHER_DEST_BASE_7_DEST_BASE_7_SIZE; + unsigned int : 12; + } coher_dest_base_7_t; + +#endif + +typedef union { + unsigned int val : 32; + coher_dest_base_7_t f; +} coher_dest_base_7_u; + + +#endif + + +#if !defined (_RBBM_FIDDLE_H) +#define _RBBM_FIDDLE_H + +/***************************************************************************************************************** + * + * rbbm_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * WAIT_UNTIL struct + */ + +#define WAIT_UNTIL_WAIT_RE_VSYNC_SIZE 1 +#define WAIT_UNTIL_WAIT_FE_VSYNC_SIZE 1 +#define WAIT_UNTIL_WAIT_VSYNC_SIZE 1 +#define WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE 1 +#define WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE 1 +#define WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE 1 +#define WAIT_UNTIL_WAIT_CMDFIFO_SIZE 1 +#define WAIT_UNTIL_WAIT_2D_IDLE_SIZE 1 +#define WAIT_UNTIL_WAIT_3D_IDLE_SIZE 1 +#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE 1 +#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE 1 +#define WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE 4 + +#define WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT 1 +#define WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT 2 +#define WAIT_UNTIL_WAIT_VSYNC_SHIFT 3 +#define WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT 4 +#define WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT 5 +#define WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT 6 +#define WAIT_UNTIL_WAIT_CMDFIFO_SHIFT 10 +#define WAIT_UNTIL_WAIT_2D_IDLE_SHIFT 14 +#define WAIT_UNTIL_WAIT_3D_IDLE_SHIFT 15 +#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT 16 +#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT 17 +#define WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT 20 + +#define WAIT_UNTIL_WAIT_RE_VSYNC_MASK 0x00000002 +#define WAIT_UNTIL_WAIT_FE_VSYNC_MASK 0x00000004 +#define WAIT_UNTIL_WAIT_VSYNC_MASK 0x00000008 +#define WAIT_UNTIL_WAIT_DSPLY_ID0_MASK 0x00000010 +#define WAIT_UNTIL_WAIT_DSPLY_ID1_MASK 0x00000020 +#define WAIT_UNTIL_WAIT_DSPLY_ID2_MASK 0x00000040 +#define WAIT_UNTIL_WAIT_CMDFIFO_MASK 0x00000400 +#define WAIT_UNTIL_WAIT_2D_IDLE_MASK 0x00004000 +#define WAIT_UNTIL_WAIT_3D_IDLE_MASK 0x00008000 +#define WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK 0x00010000 +#define WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK 0x00020000 +#define WAIT_UNTIL_CMDFIFO_ENTRIES_MASK 0x00f00000 + +#define WAIT_UNTIL_MASK \ + (WAIT_UNTIL_WAIT_RE_VSYNC_MASK | \ + WAIT_UNTIL_WAIT_FE_VSYNC_MASK | \ + WAIT_UNTIL_WAIT_VSYNC_MASK | \ + WAIT_UNTIL_WAIT_DSPLY_ID0_MASK | \ + WAIT_UNTIL_WAIT_DSPLY_ID1_MASK | \ + WAIT_UNTIL_WAIT_DSPLY_ID2_MASK | \ + WAIT_UNTIL_WAIT_CMDFIFO_MASK | \ + WAIT_UNTIL_WAIT_2D_IDLE_MASK | \ + WAIT_UNTIL_WAIT_3D_IDLE_MASK | \ + WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK | \ + WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK | \ + WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) + +#define WAIT_UNTIL(wait_re_vsync, wait_fe_vsync, wait_vsync, wait_dsply_id0, wait_dsply_id1, wait_dsply_id2, wait_cmdfifo, wait_2d_idle, wait_3d_idle, wait_2d_idleclean, wait_3d_idleclean, cmdfifo_entries) \ + ((wait_re_vsync << WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT) | \ + (wait_fe_vsync << WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT) | \ + (wait_vsync << WAIT_UNTIL_WAIT_VSYNC_SHIFT) | \ + (wait_dsply_id0 << WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT) | \ + (wait_dsply_id1 << WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT) | \ + (wait_dsply_id2 << WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT) | \ + (wait_cmdfifo << WAIT_UNTIL_WAIT_CMDFIFO_SHIFT) | \ + (wait_2d_idle << WAIT_UNTIL_WAIT_2D_IDLE_SHIFT) | \ + (wait_3d_idle << WAIT_UNTIL_WAIT_3D_IDLE_SHIFT) | \ + (wait_2d_idleclean << WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT) | \ + (wait_3d_idleclean << WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT) | \ + (cmdfifo_entries << WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT)) + +#define WAIT_UNTIL_GET_WAIT_RE_VSYNC(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_RE_VSYNC_MASK) >> WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT) +#define WAIT_UNTIL_GET_WAIT_FE_VSYNC(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_FE_VSYNC_MASK) >> WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT) +#define WAIT_UNTIL_GET_WAIT_VSYNC(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_VSYNC_MASK) >> WAIT_UNTIL_WAIT_VSYNC_SHIFT) +#define WAIT_UNTIL_GET_WAIT_DSPLY_ID0(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID0_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT) +#define WAIT_UNTIL_GET_WAIT_DSPLY_ID1(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID1_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT) +#define WAIT_UNTIL_GET_WAIT_DSPLY_ID2(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_DSPLY_ID2_MASK) >> WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT) +#define WAIT_UNTIL_GET_WAIT_CMDFIFO(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_CMDFIFO_MASK) >> WAIT_UNTIL_WAIT_CMDFIFO_SHIFT) +#define WAIT_UNTIL_GET_WAIT_2D_IDLE(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_2D_IDLE_MASK) >> WAIT_UNTIL_WAIT_2D_IDLE_SHIFT) +#define WAIT_UNTIL_GET_WAIT_3D_IDLE(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_3D_IDLE_MASK) >> WAIT_UNTIL_WAIT_3D_IDLE_SHIFT) +#define WAIT_UNTIL_GET_WAIT_2D_IDLECLEAN(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK) >> WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT) +#define WAIT_UNTIL_GET_WAIT_3D_IDLECLEAN(wait_until) \ + ((wait_until & WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK) >> WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT) +#define WAIT_UNTIL_GET_CMDFIFO_ENTRIES(wait_until) \ + ((wait_until & WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) >> WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT) + +#define WAIT_UNTIL_SET_WAIT_RE_VSYNC(wait_until_reg, wait_re_vsync) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_RE_VSYNC_MASK) | (wait_re_vsync << WAIT_UNTIL_WAIT_RE_VSYNC_SHIFT) +#define WAIT_UNTIL_SET_WAIT_FE_VSYNC(wait_until_reg, wait_fe_vsync) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_FE_VSYNC_MASK) | (wait_fe_vsync << WAIT_UNTIL_WAIT_FE_VSYNC_SHIFT) +#define WAIT_UNTIL_SET_WAIT_VSYNC(wait_until_reg, wait_vsync) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_VSYNC_MASK) | (wait_vsync << WAIT_UNTIL_WAIT_VSYNC_SHIFT) +#define WAIT_UNTIL_SET_WAIT_DSPLY_ID0(wait_until_reg, wait_dsply_id0) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID0_MASK) | (wait_dsply_id0 << WAIT_UNTIL_WAIT_DSPLY_ID0_SHIFT) +#define WAIT_UNTIL_SET_WAIT_DSPLY_ID1(wait_until_reg, wait_dsply_id1) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID1_MASK) | (wait_dsply_id1 << WAIT_UNTIL_WAIT_DSPLY_ID1_SHIFT) +#define WAIT_UNTIL_SET_WAIT_DSPLY_ID2(wait_until_reg, wait_dsply_id2) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_DSPLY_ID2_MASK) | (wait_dsply_id2 << WAIT_UNTIL_WAIT_DSPLY_ID2_SHIFT) +#define WAIT_UNTIL_SET_WAIT_CMDFIFO(wait_until_reg, wait_cmdfifo) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_CMDFIFO_MASK) | (wait_cmdfifo << WAIT_UNTIL_WAIT_CMDFIFO_SHIFT) +#define WAIT_UNTIL_SET_WAIT_2D_IDLE(wait_until_reg, wait_2d_idle) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_2D_IDLE_MASK) | (wait_2d_idle << WAIT_UNTIL_WAIT_2D_IDLE_SHIFT) +#define WAIT_UNTIL_SET_WAIT_3D_IDLE(wait_until_reg, wait_3d_idle) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_3D_IDLE_MASK) | (wait_3d_idle << WAIT_UNTIL_WAIT_3D_IDLE_SHIFT) +#define WAIT_UNTIL_SET_WAIT_2D_IDLECLEAN(wait_until_reg, wait_2d_idleclean) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_2D_IDLECLEAN_MASK) | (wait_2d_idleclean << WAIT_UNTIL_WAIT_2D_IDLECLEAN_SHIFT) +#define WAIT_UNTIL_SET_WAIT_3D_IDLECLEAN(wait_until_reg, wait_3d_idleclean) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_WAIT_3D_IDLECLEAN_MASK) | (wait_3d_idleclean << WAIT_UNTIL_WAIT_3D_IDLECLEAN_SHIFT) +#define WAIT_UNTIL_SET_CMDFIFO_ENTRIES(wait_until_reg, cmdfifo_entries) \ + wait_until_reg = (wait_until_reg & ~WAIT_UNTIL_CMDFIFO_ENTRIES_MASK) | (cmdfifo_entries << WAIT_UNTIL_CMDFIFO_ENTRIES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _wait_until_t { + unsigned int : 1; + unsigned int wait_re_vsync : WAIT_UNTIL_WAIT_RE_VSYNC_SIZE; + unsigned int wait_fe_vsync : WAIT_UNTIL_WAIT_FE_VSYNC_SIZE; + unsigned int wait_vsync : WAIT_UNTIL_WAIT_VSYNC_SIZE; + unsigned int wait_dsply_id0 : WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE; + unsigned int wait_dsply_id1 : WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE; + unsigned int wait_dsply_id2 : WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE; + unsigned int : 3; + unsigned int wait_cmdfifo : WAIT_UNTIL_WAIT_CMDFIFO_SIZE; + unsigned int : 3; + unsigned int wait_2d_idle : WAIT_UNTIL_WAIT_2D_IDLE_SIZE; + unsigned int wait_3d_idle : WAIT_UNTIL_WAIT_3D_IDLE_SIZE; + unsigned int wait_2d_idleclean : WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE; + unsigned int wait_3d_idleclean : WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE; + unsigned int : 2; + unsigned int cmdfifo_entries : WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE; + unsigned int : 8; + } wait_until_t; + +#else // !BIGENDIAN_OS + + typedef struct _wait_until_t { + unsigned int : 8; + unsigned int cmdfifo_entries : WAIT_UNTIL_CMDFIFO_ENTRIES_SIZE; + unsigned int : 2; + unsigned int wait_3d_idleclean : WAIT_UNTIL_WAIT_3D_IDLECLEAN_SIZE; + unsigned int wait_2d_idleclean : WAIT_UNTIL_WAIT_2D_IDLECLEAN_SIZE; + unsigned int wait_3d_idle : WAIT_UNTIL_WAIT_3D_IDLE_SIZE; + unsigned int wait_2d_idle : WAIT_UNTIL_WAIT_2D_IDLE_SIZE; + unsigned int : 3; + unsigned int wait_cmdfifo : WAIT_UNTIL_WAIT_CMDFIFO_SIZE; + unsigned int : 3; + unsigned int wait_dsply_id2 : WAIT_UNTIL_WAIT_DSPLY_ID2_SIZE; + unsigned int wait_dsply_id1 : WAIT_UNTIL_WAIT_DSPLY_ID1_SIZE; + unsigned int wait_dsply_id0 : WAIT_UNTIL_WAIT_DSPLY_ID0_SIZE; + unsigned int wait_vsync : WAIT_UNTIL_WAIT_VSYNC_SIZE; + unsigned int wait_fe_vsync : WAIT_UNTIL_WAIT_FE_VSYNC_SIZE; + unsigned int wait_re_vsync : WAIT_UNTIL_WAIT_RE_VSYNC_SIZE; + unsigned int : 1; + } wait_until_t; + +#endif + +typedef union { + unsigned int val : 32; + wait_until_t f; +} wait_until_u; + + +/* + * RBBM_ISYNC_CNTL struct + */ + +#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE 1 +#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE 1 + +#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT 4 +#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT 5 + +#define RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK 0x00000010 +#define RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK 0x00000020 + +#define RBBM_ISYNC_CNTL_MASK \ + (RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK | \ + RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) + +#define RBBM_ISYNC_CNTL(isync_wait_idlegui, isync_cpscratch_idlegui) \ + ((isync_wait_idlegui << RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT) | \ + (isync_cpscratch_idlegui << RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT)) + +#define RBBM_ISYNC_CNTL_GET_ISYNC_WAIT_IDLEGUI(rbbm_isync_cntl) \ + ((rbbm_isync_cntl & RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK) >> RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT) +#define RBBM_ISYNC_CNTL_GET_ISYNC_CPSCRATCH_IDLEGUI(rbbm_isync_cntl) \ + ((rbbm_isync_cntl & RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) >> RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT) + +#define RBBM_ISYNC_CNTL_SET_ISYNC_WAIT_IDLEGUI(rbbm_isync_cntl_reg, isync_wait_idlegui) \ + rbbm_isync_cntl_reg = (rbbm_isync_cntl_reg & ~RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_MASK) | (isync_wait_idlegui << RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SHIFT) +#define RBBM_ISYNC_CNTL_SET_ISYNC_CPSCRATCH_IDLEGUI(rbbm_isync_cntl_reg, isync_cpscratch_idlegui) \ + rbbm_isync_cntl_reg = (rbbm_isync_cntl_reg & ~RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_MASK) | (isync_cpscratch_idlegui << RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_isync_cntl_t { + unsigned int : 4; + unsigned int isync_wait_idlegui : RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE; + unsigned int isync_cpscratch_idlegui : RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE; + unsigned int : 26; + } rbbm_isync_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_isync_cntl_t { + unsigned int : 26; + unsigned int isync_cpscratch_idlegui : RBBM_ISYNC_CNTL_ISYNC_CPSCRATCH_IDLEGUI_SIZE; + unsigned int isync_wait_idlegui : RBBM_ISYNC_CNTL_ISYNC_WAIT_IDLEGUI_SIZE; + unsigned int : 4; + } rbbm_isync_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_isync_cntl_t f; +} rbbm_isync_cntl_u; + + +/* + * RBBM_STATUS struct + */ + +#define RBBM_STATUS_CMDFIFO_AVAIL_SIZE 5 +#define RBBM_STATUS_TC_BUSY_SIZE 1 +#define RBBM_STATUS_HIRQ_PENDING_SIZE 1 +#define RBBM_STATUS_CPRQ_PENDING_SIZE 1 +#define RBBM_STATUS_CFRQ_PENDING_SIZE 1 +#define RBBM_STATUS_PFRQ_PENDING_SIZE 1 +#define RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE 1 +#define RBBM_STATUS_RBBM_WU_BUSY_SIZE 1 +#define RBBM_STATUS_CP_NRT_BUSY_SIZE 1 +#define RBBM_STATUS_MH_BUSY_SIZE 1 +#define RBBM_STATUS_MH_COHERENCY_BUSY_SIZE 1 +#define RBBM_STATUS_SX_BUSY_SIZE 1 +#define RBBM_STATUS_TPC_BUSY_SIZE 1 +#define RBBM_STATUS_SC_CNTX_BUSY_SIZE 1 +#define RBBM_STATUS_PA_BUSY_SIZE 1 +#define RBBM_STATUS_VGT_BUSY_SIZE 1 +#define RBBM_STATUS_SQ_CNTX17_BUSY_SIZE 1 +#define RBBM_STATUS_SQ_CNTX0_BUSY_SIZE 1 +#define RBBM_STATUS_RB_CNTX_BUSY_SIZE 1 +#define RBBM_STATUS_GUI_ACTIVE_SIZE 1 + +#define RBBM_STATUS_CMDFIFO_AVAIL_SHIFT 0 +#define RBBM_STATUS_TC_BUSY_SHIFT 5 +#define RBBM_STATUS_HIRQ_PENDING_SHIFT 8 +#define RBBM_STATUS_CPRQ_PENDING_SHIFT 9 +#define RBBM_STATUS_CFRQ_PENDING_SHIFT 10 +#define RBBM_STATUS_PFRQ_PENDING_SHIFT 11 +#define RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT 12 +#define RBBM_STATUS_RBBM_WU_BUSY_SHIFT 14 +#define RBBM_STATUS_CP_NRT_BUSY_SHIFT 16 +#define RBBM_STATUS_MH_BUSY_SHIFT 18 +#define RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT 19 +#define RBBM_STATUS_SX_BUSY_SHIFT 21 +#define RBBM_STATUS_TPC_BUSY_SHIFT 22 +#define RBBM_STATUS_SC_CNTX_BUSY_SHIFT 24 +#define RBBM_STATUS_PA_BUSY_SHIFT 25 +#define RBBM_STATUS_VGT_BUSY_SHIFT 26 +#define RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT 27 +#define RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT 28 +#define RBBM_STATUS_RB_CNTX_BUSY_SHIFT 30 +#define RBBM_STATUS_GUI_ACTIVE_SHIFT 31 + +#define RBBM_STATUS_CMDFIFO_AVAIL_MASK 0x0000001f +#define RBBM_STATUS_TC_BUSY_MASK 0x00000020 +#define RBBM_STATUS_HIRQ_PENDING_MASK 0x00000100 +#define RBBM_STATUS_CPRQ_PENDING_MASK 0x00000200 +#define RBBM_STATUS_CFRQ_PENDING_MASK 0x00000400 +#define RBBM_STATUS_PFRQ_PENDING_MASK 0x00000800 +#define RBBM_STATUS_VGT_BUSY_NO_DMA_MASK 0x00001000 +#define RBBM_STATUS_RBBM_WU_BUSY_MASK 0x00004000 +#define RBBM_STATUS_CP_NRT_BUSY_MASK 0x00010000 +#define RBBM_STATUS_MH_BUSY_MASK 0x00040000 +#define RBBM_STATUS_MH_COHERENCY_BUSY_MASK 0x00080000 +#define RBBM_STATUS_SX_BUSY_MASK 0x00200000 +#define RBBM_STATUS_TPC_BUSY_MASK 0x00400000 +#define RBBM_STATUS_SC_CNTX_BUSY_MASK 0x01000000 +#define RBBM_STATUS_PA_BUSY_MASK 0x02000000 +#define RBBM_STATUS_VGT_BUSY_MASK 0x04000000 +#define RBBM_STATUS_SQ_CNTX17_BUSY_MASK 0x08000000 +#define RBBM_STATUS_SQ_CNTX0_BUSY_MASK 0x10000000 +#define RBBM_STATUS_RB_CNTX_BUSY_MASK 0x40000000 +#define RBBM_STATUS_GUI_ACTIVE_MASK 0x80000000 + +#define RBBM_STATUS_MASK \ + (RBBM_STATUS_CMDFIFO_AVAIL_MASK | \ + RBBM_STATUS_TC_BUSY_MASK | \ + RBBM_STATUS_HIRQ_PENDING_MASK | \ + RBBM_STATUS_CPRQ_PENDING_MASK | \ + RBBM_STATUS_CFRQ_PENDING_MASK | \ + RBBM_STATUS_PFRQ_PENDING_MASK | \ + RBBM_STATUS_VGT_BUSY_NO_DMA_MASK | \ + RBBM_STATUS_RBBM_WU_BUSY_MASK | \ + RBBM_STATUS_CP_NRT_BUSY_MASK | \ + RBBM_STATUS_MH_BUSY_MASK | \ + RBBM_STATUS_MH_COHERENCY_BUSY_MASK | \ + RBBM_STATUS_SX_BUSY_MASK | \ + RBBM_STATUS_TPC_BUSY_MASK | \ + RBBM_STATUS_SC_CNTX_BUSY_MASK | \ + RBBM_STATUS_PA_BUSY_MASK | \ + RBBM_STATUS_VGT_BUSY_MASK | \ + RBBM_STATUS_SQ_CNTX17_BUSY_MASK | \ + RBBM_STATUS_SQ_CNTX0_BUSY_MASK | \ + RBBM_STATUS_RB_CNTX_BUSY_MASK | \ + RBBM_STATUS_GUI_ACTIVE_MASK) + +#define RBBM_STATUS(cmdfifo_avail, tc_busy, hirq_pending, cprq_pending, cfrq_pending, pfrq_pending, vgt_busy_no_dma, rbbm_wu_busy, cp_nrt_busy, mh_busy, mh_coherency_busy, sx_busy, tpc_busy, sc_cntx_busy, pa_busy, vgt_busy, sq_cntx17_busy, sq_cntx0_busy, rb_cntx_busy, gui_active) \ + ((cmdfifo_avail << RBBM_STATUS_CMDFIFO_AVAIL_SHIFT) | \ + (tc_busy << RBBM_STATUS_TC_BUSY_SHIFT) | \ + (hirq_pending << RBBM_STATUS_HIRQ_PENDING_SHIFT) | \ + (cprq_pending << RBBM_STATUS_CPRQ_PENDING_SHIFT) | \ + (cfrq_pending << RBBM_STATUS_CFRQ_PENDING_SHIFT) | \ + (pfrq_pending << RBBM_STATUS_PFRQ_PENDING_SHIFT) | \ + (vgt_busy_no_dma << RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT) | \ + (rbbm_wu_busy << RBBM_STATUS_RBBM_WU_BUSY_SHIFT) | \ + (cp_nrt_busy << RBBM_STATUS_CP_NRT_BUSY_SHIFT) | \ + (mh_busy << RBBM_STATUS_MH_BUSY_SHIFT) | \ + (mh_coherency_busy << RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT) | \ + (sx_busy << RBBM_STATUS_SX_BUSY_SHIFT) | \ + (tpc_busy << RBBM_STATUS_TPC_BUSY_SHIFT) | \ + (sc_cntx_busy << RBBM_STATUS_SC_CNTX_BUSY_SHIFT) | \ + (pa_busy << RBBM_STATUS_PA_BUSY_SHIFT) | \ + (vgt_busy << RBBM_STATUS_VGT_BUSY_SHIFT) | \ + (sq_cntx17_busy << RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT) | \ + (sq_cntx0_busy << RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT) | \ + (rb_cntx_busy << RBBM_STATUS_RB_CNTX_BUSY_SHIFT) | \ + (gui_active << RBBM_STATUS_GUI_ACTIVE_SHIFT)) + +#define RBBM_STATUS_GET_CMDFIFO_AVAIL(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_CMDFIFO_AVAIL_MASK) >> RBBM_STATUS_CMDFIFO_AVAIL_SHIFT) +#define RBBM_STATUS_GET_TC_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_TC_BUSY_MASK) >> RBBM_STATUS_TC_BUSY_SHIFT) +#define RBBM_STATUS_GET_HIRQ_PENDING(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_HIRQ_PENDING_MASK) >> RBBM_STATUS_HIRQ_PENDING_SHIFT) +#define RBBM_STATUS_GET_CPRQ_PENDING(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_CPRQ_PENDING_MASK) >> RBBM_STATUS_CPRQ_PENDING_SHIFT) +#define RBBM_STATUS_GET_CFRQ_PENDING(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_CFRQ_PENDING_MASK) >> RBBM_STATUS_CFRQ_PENDING_SHIFT) +#define RBBM_STATUS_GET_PFRQ_PENDING(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_PFRQ_PENDING_MASK) >> RBBM_STATUS_PFRQ_PENDING_SHIFT) +#define RBBM_STATUS_GET_VGT_BUSY_NO_DMA(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_VGT_BUSY_NO_DMA_MASK) >> RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT) +#define RBBM_STATUS_GET_RBBM_WU_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_RBBM_WU_BUSY_MASK) >> RBBM_STATUS_RBBM_WU_BUSY_SHIFT) +#define RBBM_STATUS_GET_CP_NRT_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_CP_NRT_BUSY_MASK) >> RBBM_STATUS_CP_NRT_BUSY_SHIFT) +#define RBBM_STATUS_GET_MH_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_MH_BUSY_MASK) >> RBBM_STATUS_MH_BUSY_SHIFT) +#define RBBM_STATUS_GET_MH_COHERENCY_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_MH_COHERENCY_BUSY_MASK) >> RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT) +#define RBBM_STATUS_GET_SX_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_SX_BUSY_MASK) >> RBBM_STATUS_SX_BUSY_SHIFT) +#define RBBM_STATUS_GET_TPC_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_TPC_BUSY_MASK) >> RBBM_STATUS_TPC_BUSY_SHIFT) +#define RBBM_STATUS_GET_SC_CNTX_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_SC_CNTX_BUSY_MASK) >> RBBM_STATUS_SC_CNTX_BUSY_SHIFT) +#define RBBM_STATUS_GET_PA_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_PA_BUSY_MASK) >> RBBM_STATUS_PA_BUSY_SHIFT) +#define RBBM_STATUS_GET_VGT_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_VGT_BUSY_MASK) >> RBBM_STATUS_VGT_BUSY_SHIFT) +#define RBBM_STATUS_GET_SQ_CNTX17_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_SQ_CNTX17_BUSY_MASK) >> RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT) +#define RBBM_STATUS_GET_SQ_CNTX0_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_SQ_CNTX0_BUSY_MASK) >> RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT) +#define RBBM_STATUS_GET_RB_CNTX_BUSY(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_RB_CNTX_BUSY_MASK) >> RBBM_STATUS_RB_CNTX_BUSY_SHIFT) +#define RBBM_STATUS_GET_GUI_ACTIVE(rbbm_status) \ + ((rbbm_status & RBBM_STATUS_GUI_ACTIVE_MASK) >> RBBM_STATUS_GUI_ACTIVE_SHIFT) + +#define RBBM_STATUS_SET_CMDFIFO_AVAIL(rbbm_status_reg, cmdfifo_avail) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CMDFIFO_AVAIL_MASK) | (cmdfifo_avail << RBBM_STATUS_CMDFIFO_AVAIL_SHIFT) +#define RBBM_STATUS_SET_TC_BUSY(rbbm_status_reg, tc_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_TC_BUSY_MASK) | (tc_busy << RBBM_STATUS_TC_BUSY_SHIFT) +#define RBBM_STATUS_SET_HIRQ_PENDING(rbbm_status_reg, hirq_pending) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_HIRQ_PENDING_MASK) | (hirq_pending << RBBM_STATUS_HIRQ_PENDING_SHIFT) +#define RBBM_STATUS_SET_CPRQ_PENDING(rbbm_status_reg, cprq_pending) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CPRQ_PENDING_MASK) | (cprq_pending << RBBM_STATUS_CPRQ_PENDING_SHIFT) +#define RBBM_STATUS_SET_CFRQ_PENDING(rbbm_status_reg, cfrq_pending) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CFRQ_PENDING_MASK) | (cfrq_pending << RBBM_STATUS_CFRQ_PENDING_SHIFT) +#define RBBM_STATUS_SET_PFRQ_PENDING(rbbm_status_reg, pfrq_pending) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_PFRQ_PENDING_MASK) | (pfrq_pending << RBBM_STATUS_PFRQ_PENDING_SHIFT) +#define RBBM_STATUS_SET_VGT_BUSY_NO_DMA(rbbm_status_reg, vgt_busy_no_dma) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_VGT_BUSY_NO_DMA_MASK) | (vgt_busy_no_dma << RBBM_STATUS_VGT_BUSY_NO_DMA_SHIFT) +#define RBBM_STATUS_SET_RBBM_WU_BUSY(rbbm_status_reg, rbbm_wu_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_RBBM_WU_BUSY_MASK) | (rbbm_wu_busy << RBBM_STATUS_RBBM_WU_BUSY_SHIFT) +#define RBBM_STATUS_SET_CP_NRT_BUSY(rbbm_status_reg, cp_nrt_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_CP_NRT_BUSY_MASK) | (cp_nrt_busy << RBBM_STATUS_CP_NRT_BUSY_SHIFT) +#define RBBM_STATUS_SET_MH_BUSY(rbbm_status_reg, mh_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_MH_BUSY_MASK) | (mh_busy << RBBM_STATUS_MH_BUSY_SHIFT) +#define RBBM_STATUS_SET_MH_COHERENCY_BUSY(rbbm_status_reg, mh_coherency_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_MH_COHERENCY_BUSY_MASK) | (mh_coherency_busy << RBBM_STATUS_MH_COHERENCY_BUSY_SHIFT) +#define RBBM_STATUS_SET_SX_BUSY(rbbm_status_reg, sx_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SX_BUSY_MASK) | (sx_busy << RBBM_STATUS_SX_BUSY_SHIFT) +#define RBBM_STATUS_SET_TPC_BUSY(rbbm_status_reg, tpc_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_TPC_BUSY_MASK) | (tpc_busy << RBBM_STATUS_TPC_BUSY_SHIFT) +#define RBBM_STATUS_SET_SC_CNTX_BUSY(rbbm_status_reg, sc_cntx_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SC_CNTX_BUSY_MASK) | (sc_cntx_busy << RBBM_STATUS_SC_CNTX_BUSY_SHIFT) +#define RBBM_STATUS_SET_PA_BUSY(rbbm_status_reg, pa_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_PA_BUSY_MASK) | (pa_busy << RBBM_STATUS_PA_BUSY_SHIFT) +#define RBBM_STATUS_SET_VGT_BUSY(rbbm_status_reg, vgt_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_VGT_BUSY_MASK) | (vgt_busy << RBBM_STATUS_VGT_BUSY_SHIFT) +#define RBBM_STATUS_SET_SQ_CNTX17_BUSY(rbbm_status_reg, sq_cntx17_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SQ_CNTX17_BUSY_MASK) | (sq_cntx17_busy << RBBM_STATUS_SQ_CNTX17_BUSY_SHIFT) +#define RBBM_STATUS_SET_SQ_CNTX0_BUSY(rbbm_status_reg, sq_cntx0_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_SQ_CNTX0_BUSY_MASK) | (sq_cntx0_busy << RBBM_STATUS_SQ_CNTX0_BUSY_SHIFT) +#define RBBM_STATUS_SET_RB_CNTX_BUSY(rbbm_status_reg, rb_cntx_busy) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_RB_CNTX_BUSY_MASK) | (rb_cntx_busy << RBBM_STATUS_RB_CNTX_BUSY_SHIFT) +#define RBBM_STATUS_SET_GUI_ACTIVE(rbbm_status_reg, gui_active) \ + rbbm_status_reg = (rbbm_status_reg & ~RBBM_STATUS_GUI_ACTIVE_MASK) | (gui_active << RBBM_STATUS_GUI_ACTIVE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_status_t { + unsigned int cmdfifo_avail : RBBM_STATUS_CMDFIFO_AVAIL_SIZE; + unsigned int tc_busy : RBBM_STATUS_TC_BUSY_SIZE; + unsigned int : 2; + unsigned int hirq_pending : RBBM_STATUS_HIRQ_PENDING_SIZE; + unsigned int cprq_pending : RBBM_STATUS_CPRQ_PENDING_SIZE; + unsigned int cfrq_pending : RBBM_STATUS_CFRQ_PENDING_SIZE; + unsigned int pfrq_pending : RBBM_STATUS_PFRQ_PENDING_SIZE; + unsigned int vgt_busy_no_dma : RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE; + unsigned int : 1; + unsigned int rbbm_wu_busy : RBBM_STATUS_RBBM_WU_BUSY_SIZE; + unsigned int : 1; + unsigned int cp_nrt_busy : RBBM_STATUS_CP_NRT_BUSY_SIZE; + unsigned int : 1; + unsigned int mh_busy : RBBM_STATUS_MH_BUSY_SIZE; + unsigned int mh_coherency_busy : RBBM_STATUS_MH_COHERENCY_BUSY_SIZE; + unsigned int : 1; + unsigned int sx_busy : RBBM_STATUS_SX_BUSY_SIZE; + unsigned int tpc_busy : RBBM_STATUS_TPC_BUSY_SIZE; + unsigned int : 1; + unsigned int sc_cntx_busy : RBBM_STATUS_SC_CNTX_BUSY_SIZE; + unsigned int pa_busy : RBBM_STATUS_PA_BUSY_SIZE; + unsigned int vgt_busy : RBBM_STATUS_VGT_BUSY_SIZE; + unsigned int sq_cntx17_busy : RBBM_STATUS_SQ_CNTX17_BUSY_SIZE; + unsigned int sq_cntx0_busy : RBBM_STATUS_SQ_CNTX0_BUSY_SIZE; + unsigned int : 1; + unsigned int rb_cntx_busy : RBBM_STATUS_RB_CNTX_BUSY_SIZE; + unsigned int gui_active : RBBM_STATUS_GUI_ACTIVE_SIZE; + } rbbm_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_status_t { + unsigned int gui_active : RBBM_STATUS_GUI_ACTIVE_SIZE; + unsigned int rb_cntx_busy : RBBM_STATUS_RB_CNTX_BUSY_SIZE; + unsigned int : 1; + unsigned int sq_cntx0_busy : RBBM_STATUS_SQ_CNTX0_BUSY_SIZE; + unsigned int sq_cntx17_busy : RBBM_STATUS_SQ_CNTX17_BUSY_SIZE; + unsigned int vgt_busy : RBBM_STATUS_VGT_BUSY_SIZE; + unsigned int pa_busy : RBBM_STATUS_PA_BUSY_SIZE; + unsigned int sc_cntx_busy : RBBM_STATUS_SC_CNTX_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_busy : RBBM_STATUS_TPC_BUSY_SIZE; + unsigned int sx_busy : RBBM_STATUS_SX_BUSY_SIZE; + unsigned int : 1; + unsigned int mh_coherency_busy : RBBM_STATUS_MH_COHERENCY_BUSY_SIZE; + unsigned int mh_busy : RBBM_STATUS_MH_BUSY_SIZE; + unsigned int : 1; + unsigned int cp_nrt_busy : RBBM_STATUS_CP_NRT_BUSY_SIZE; + unsigned int : 1; + unsigned int rbbm_wu_busy : RBBM_STATUS_RBBM_WU_BUSY_SIZE; + unsigned int : 1; + unsigned int vgt_busy_no_dma : RBBM_STATUS_VGT_BUSY_NO_DMA_SIZE; + unsigned int pfrq_pending : RBBM_STATUS_PFRQ_PENDING_SIZE; + unsigned int cfrq_pending : RBBM_STATUS_CFRQ_PENDING_SIZE; + unsigned int cprq_pending : RBBM_STATUS_CPRQ_PENDING_SIZE; + unsigned int hirq_pending : RBBM_STATUS_HIRQ_PENDING_SIZE; + unsigned int : 2; + unsigned int tc_busy : RBBM_STATUS_TC_BUSY_SIZE; + unsigned int cmdfifo_avail : RBBM_STATUS_CMDFIFO_AVAIL_SIZE; + } rbbm_status_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_status_t f; +} rbbm_status_u; + + +/* + * RBBM_DSPLY struct + */ + +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SIZE 1 +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SIZE 1 +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SIZE 1 +#define RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SIZE 1 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID0_SIZE 1 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID1_SIZE 1 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID2_SIZE 1 +#define RBBM_DSPLY_DMI_CH1_SW_CNTL_SIZE 1 +#define RBBM_DSPLY_DMI_CH1_NUM_BUFS_SIZE 2 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID0_SIZE 1 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID1_SIZE 1 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID2_SIZE 1 +#define RBBM_DSPLY_DMI_CH2_SW_CNTL_SIZE 1 +#define RBBM_DSPLY_DMI_CH2_NUM_BUFS_SIZE 2 +#define RBBM_DSPLY_DMI_CHANNEL_SELECT_SIZE 2 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID0_SIZE 1 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID1_SIZE 1 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID2_SIZE 1 +#define RBBM_DSPLY_DMI_CH3_SW_CNTL_SIZE 1 +#define RBBM_DSPLY_DMI_CH3_NUM_BUFS_SIZE 2 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID0_SIZE 1 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID1_SIZE 1 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID2_SIZE 1 +#define RBBM_DSPLY_DMI_CH4_SW_CNTL_SIZE 1 +#define RBBM_DSPLY_DMI_CH4_NUM_BUFS_SIZE 2 + +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT 0 +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT 1 +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT 2 +#define RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT 3 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT 4 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT 5 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT 6 +#define RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT 7 +#define RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT 8 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT 10 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT 11 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT 12 +#define RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT 13 +#define RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT 14 +#define RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT 16 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT 20 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT 21 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT 22 +#define RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT 23 +#define RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT 24 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT 26 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT 27 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT 28 +#define RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT 29 +#define RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT 30 + +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK 0x00000001 +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK 0x00000002 +#define RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK 0x00000004 +#define RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK 0x00000008 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK 0x00000010 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK 0x00000020 +#define RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK 0x00000040 +#define RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK 0x00000080 +#define RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK 0x00000300 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK 0x00000400 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK 0x00000800 +#define RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK 0x00001000 +#define RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK 0x00002000 +#define RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK 0x0000c000 +#define RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK 0x00030000 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK 0x00100000 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK 0x00200000 +#define RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK 0x00400000 +#define RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK 0x00800000 +#define RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK 0x03000000 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK 0x04000000 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK 0x08000000 +#define RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK 0x10000000 +#define RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK 0x20000000 +#define RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK 0xc0000000 + +#define RBBM_DSPLY_MASK \ + (RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK | \ + RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK | \ + RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK | \ + RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK | \ + RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK | \ + RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK | \ + RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK | \ + RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK | \ + RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK | \ + RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK | \ + RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK | \ + RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK | \ + RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK | \ + RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK | \ + RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK | \ + RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK | \ + RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK | \ + RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK | \ + RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK | \ + RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK | \ + RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK | \ + RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK | \ + RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK | \ + RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK | \ + RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK) + +#define RBBM_DSPLY(sel_dmi_active_bufid0, sel_dmi_active_bufid1, sel_dmi_active_bufid2, sel_dmi_vsync_valid, dmi_ch1_use_bufid0, dmi_ch1_use_bufid1, dmi_ch1_use_bufid2, dmi_ch1_sw_cntl, dmi_ch1_num_bufs, dmi_ch2_use_bufid0, dmi_ch2_use_bufid1, dmi_ch2_use_bufid2, dmi_ch2_sw_cntl, dmi_ch2_num_bufs, dmi_channel_select, dmi_ch3_use_bufid0, dmi_ch3_use_bufid1, dmi_ch3_use_bufid2, dmi_ch3_sw_cntl, dmi_ch3_num_bufs, dmi_ch4_use_bufid0, dmi_ch4_use_bufid1, dmi_ch4_use_bufid2, dmi_ch4_sw_cntl, dmi_ch4_num_bufs) \ + ((sel_dmi_active_bufid0 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT) | \ + (sel_dmi_active_bufid1 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT) | \ + (sel_dmi_active_bufid2 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT) | \ + (sel_dmi_vsync_valid << RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT) | \ + (dmi_ch1_use_bufid0 << RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT) | \ + (dmi_ch1_use_bufid1 << RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT) | \ + (dmi_ch1_use_bufid2 << RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT) | \ + (dmi_ch1_sw_cntl << RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT) | \ + (dmi_ch1_num_bufs << RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT) | \ + (dmi_ch2_use_bufid0 << RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT) | \ + (dmi_ch2_use_bufid1 << RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT) | \ + (dmi_ch2_use_bufid2 << RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT) | \ + (dmi_ch2_sw_cntl << RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT) | \ + (dmi_ch2_num_bufs << RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT) | \ + (dmi_channel_select << RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT) | \ + (dmi_ch3_use_bufid0 << RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT) | \ + (dmi_ch3_use_bufid1 << RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT) | \ + (dmi_ch3_use_bufid2 << RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT) | \ + (dmi_ch3_sw_cntl << RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT) | \ + (dmi_ch3_num_bufs << RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT) | \ + (dmi_ch4_use_bufid0 << RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT) | \ + (dmi_ch4_use_bufid1 << RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT) | \ + (dmi_ch4_use_bufid2 << RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT) | \ + (dmi_ch4_sw_cntl << RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT) | \ + (dmi_ch4_num_bufs << RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT)) + +#define RBBM_DSPLY_GET_SEL_DMI_ACTIVE_BUFID0(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK) >> RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT) +#define RBBM_DSPLY_GET_SEL_DMI_ACTIVE_BUFID1(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK) >> RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT) +#define RBBM_DSPLY_GET_SEL_DMI_ACTIVE_BUFID2(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK) >> RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT) +#define RBBM_DSPLY_GET_SEL_DMI_VSYNC_VALID(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK) >> RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH1_USE_BUFID0(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH1_USE_BUFID1(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH1_USE_BUFID2(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH1_SW_CNTL(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH1_NUM_BUFS(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH2_USE_BUFID0(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH2_USE_BUFID1(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH2_USE_BUFID2(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH2_SW_CNTL(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH2_NUM_BUFS(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT) +#define RBBM_DSPLY_GET_DMI_CHANNEL_SELECT(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK) >> RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH3_USE_BUFID0(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH3_USE_BUFID1(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH3_USE_BUFID2(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH3_SW_CNTL(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH3_NUM_BUFS(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH4_USE_BUFID0(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK) >> RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH4_USE_BUFID1(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK) >> RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH4_USE_BUFID2(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK) >> RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH4_SW_CNTL(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK) >> RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT) +#define RBBM_DSPLY_GET_DMI_CH4_NUM_BUFS(rbbm_dsply) \ + ((rbbm_dsply & RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK) >> RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT) + +#define RBBM_DSPLY_SET_SEL_DMI_ACTIVE_BUFID0(rbbm_dsply_reg, sel_dmi_active_bufid0) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_MASK) | (sel_dmi_active_bufid0 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SHIFT) +#define RBBM_DSPLY_SET_SEL_DMI_ACTIVE_BUFID1(rbbm_dsply_reg, sel_dmi_active_bufid1) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_MASK) | (sel_dmi_active_bufid1 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SHIFT) +#define RBBM_DSPLY_SET_SEL_DMI_ACTIVE_BUFID2(rbbm_dsply_reg, sel_dmi_active_bufid2) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_MASK) | (sel_dmi_active_bufid2 << RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SHIFT) +#define RBBM_DSPLY_SET_SEL_DMI_VSYNC_VALID(rbbm_dsply_reg, sel_dmi_vsync_valid) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_SEL_DMI_VSYNC_VALID_MASK) | (sel_dmi_vsync_valid << RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH1_USE_BUFID0(rbbm_dsply_reg, dmi_ch1_use_bufid0) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_USE_BUFID0_MASK) | (dmi_ch1_use_bufid0 << RBBM_DSPLY_DMI_CH1_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH1_USE_BUFID1(rbbm_dsply_reg, dmi_ch1_use_bufid1) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_USE_BUFID1_MASK) | (dmi_ch1_use_bufid1 << RBBM_DSPLY_DMI_CH1_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH1_USE_BUFID2(rbbm_dsply_reg, dmi_ch1_use_bufid2) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_USE_BUFID2_MASK) | (dmi_ch1_use_bufid2 << RBBM_DSPLY_DMI_CH1_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH1_SW_CNTL(rbbm_dsply_reg, dmi_ch1_sw_cntl) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_SW_CNTL_MASK) | (dmi_ch1_sw_cntl << RBBM_DSPLY_DMI_CH1_SW_CNTL_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH1_NUM_BUFS(rbbm_dsply_reg, dmi_ch1_num_bufs) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH1_NUM_BUFS_MASK) | (dmi_ch1_num_bufs << RBBM_DSPLY_DMI_CH1_NUM_BUFS_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH2_USE_BUFID0(rbbm_dsply_reg, dmi_ch2_use_bufid0) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_USE_BUFID0_MASK) | (dmi_ch2_use_bufid0 << RBBM_DSPLY_DMI_CH2_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH2_USE_BUFID1(rbbm_dsply_reg, dmi_ch2_use_bufid1) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_USE_BUFID1_MASK) | (dmi_ch2_use_bufid1 << RBBM_DSPLY_DMI_CH2_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH2_USE_BUFID2(rbbm_dsply_reg, dmi_ch2_use_bufid2) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_USE_BUFID2_MASK) | (dmi_ch2_use_bufid2 << RBBM_DSPLY_DMI_CH2_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH2_SW_CNTL(rbbm_dsply_reg, dmi_ch2_sw_cntl) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_SW_CNTL_MASK) | (dmi_ch2_sw_cntl << RBBM_DSPLY_DMI_CH2_SW_CNTL_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH2_NUM_BUFS(rbbm_dsply_reg, dmi_ch2_num_bufs) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH2_NUM_BUFS_MASK) | (dmi_ch2_num_bufs << RBBM_DSPLY_DMI_CH2_NUM_BUFS_SHIFT) +#define RBBM_DSPLY_SET_DMI_CHANNEL_SELECT(rbbm_dsply_reg, dmi_channel_select) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CHANNEL_SELECT_MASK) | (dmi_channel_select << RBBM_DSPLY_DMI_CHANNEL_SELECT_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH3_USE_BUFID0(rbbm_dsply_reg, dmi_ch3_use_bufid0) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_USE_BUFID0_MASK) | (dmi_ch3_use_bufid0 << RBBM_DSPLY_DMI_CH3_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH3_USE_BUFID1(rbbm_dsply_reg, dmi_ch3_use_bufid1) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_USE_BUFID1_MASK) | (dmi_ch3_use_bufid1 << RBBM_DSPLY_DMI_CH3_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH3_USE_BUFID2(rbbm_dsply_reg, dmi_ch3_use_bufid2) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_USE_BUFID2_MASK) | (dmi_ch3_use_bufid2 << RBBM_DSPLY_DMI_CH3_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH3_SW_CNTL(rbbm_dsply_reg, dmi_ch3_sw_cntl) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_SW_CNTL_MASK) | (dmi_ch3_sw_cntl << RBBM_DSPLY_DMI_CH3_SW_CNTL_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH3_NUM_BUFS(rbbm_dsply_reg, dmi_ch3_num_bufs) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH3_NUM_BUFS_MASK) | (dmi_ch3_num_bufs << RBBM_DSPLY_DMI_CH3_NUM_BUFS_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH4_USE_BUFID0(rbbm_dsply_reg, dmi_ch4_use_bufid0) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_USE_BUFID0_MASK) | (dmi_ch4_use_bufid0 << RBBM_DSPLY_DMI_CH4_USE_BUFID0_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH4_USE_BUFID1(rbbm_dsply_reg, dmi_ch4_use_bufid1) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_USE_BUFID1_MASK) | (dmi_ch4_use_bufid1 << RBBM_DSPLY_DMI_CH4_USE_BUFID1_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH4_USE_BUFID2(rbbm_dsply_reg, dmi_ch4_use_bufid2) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_USE_BUFID2_MASK) | (dmi_ch4_use_bufid2 << RBBM_DSPLY_DMI_CH4_USE_BUFID2_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH4_SW_CNTL(rbbm_dsply_reg, dmi_ch4_sw_cntl) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_SW_CNTL_MASK) | (dmi_ch4_sw_cntl << RBBM_DSPLY_DMI_CH4_SW_CNTL_SHIFT) +#define RBBM_DSPLY_SET_DMI_CH4_NUM_BUFS(rbbm_dsply_reg, dmi_ch4_num_bufs) \ + rbbm_dsply_reg = (rbbm_dsply_reg & ~RBBM_DSPLY_DMI_CH4_NUM_BUFS_MASK) | (dmi_ch4_num_bufs << RBBM_DSPLY_DMI_CH4_NUM_BUFS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_dsply_t { + unsigned int sel_dmi_active_bufid0 : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SIZE; + unsigned int sel_dmi_active_bufid1 : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SIZE; + unsigned int sel_dmi_active_bufid2 : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SIZE; + unsigned int sel_dmi_vsync_valid : RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SIZE; + unsigned int dmi_ch1_use_bufid0 : RBBM_DSPLY_DMI_CH1_USE_BUFID0_SIZE; + unsigned int dmi_ch1_use_bufid1 : RBBM_DSPLY_DMI_CH1_USE_BUFID1_SIZE; + unsigned int dmi_ch1_use_bufid2 : RBBM_DSPLY_DMI_CH1_USE_BUFID2_SIZE; + unsigned int dmi_ch1_sw_cntl : RBBM_DSPLY_DMI_CH1_SW_CNTL_SIZE; + unsigned int dmi_ch1_num_bufs : RBBM_DSPLY_DMI_CH1_NUM_BUFS_SIZE; + unsigned int dmi_ch2_use_bufid0 : RBBM_DSPLY_DMI_CH2_USE_BUFID0_SIZE; + unsigned int dmi_ch2_use_bufid1 : RBBM_DSPLY_DMI_CH2_USE_BUFID1_SIZE; + unsigned int dmi_ch2_use_bufid2 : RBBM_DSPLY_DMI_CH2_USE_BUFID2_SIZE; + unsigned int dmi_ch2_sw_cntl : RBBM_DSPLY_DMI_CH2_SW_CNTL_SIZE; + unsigned int dmi_ch2_num_bufs : RBBM_DSPLY_DMI_CH2_NUM_BUFS_SIZE; + unsigned int dmi_channel_select : RBBM_DSPLY_DMI_CHANNEL_SELECT_SIZE; + unsigned int : 2; + unsigned int dmi_ch3_use_bufid0 : RBBM_DSPLY_DMI_CH3_USE_BUFID0_SIZE; + unsigned int dmi_ch3_use_bufid1 : RBBM_DSPLY_DMI_CH3_USE_BUFID1_SIZE; + unsigned int dmi_ch3_use_bufid2 : RBBM_DSPLY_DMI_CH3_USE_BUFID2_SIZE; + unsigned int dmi_ch3_sw_cntl : RBBM_DSPLY_DMI_CH3_SW_CNTL_SIZE; + unsigned int dmi_ch3_num_bufs : RBBM_DSPLY_DMI_CH3_NUM_BUFS_SIZE; + unsigned int dmi_ch4_use_bufid0 : RBBM_DSPLY_DMI_CH4_USE_BUFID0_SIZE; + unsigned int dmi_ch4_use_bufid1 : RBBM_DSPLY_DMI_CH4_USE_BUFID1_SIZE; + unsigned int dmi_ch4_use_bufid2 : RBBM_DSPLY_DMI_CH4_USE_BUFID2_SIZE; + unsigned int dmi_ch4_sw_cntl : RBBM_DSPLY_DMI_CH4_SW_CNTL_SIZE; + unsigned int dmi_ch4_num_bufs : RBBM_DSPLY_DMI_CH4_NUM_BUFS_SIZE; + } rbbm_dsply_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_dsply_t { + unsigned int dmi_ch4_num_bufs : RBBM_DSPLY_DMI_CH4_NUM_BUFS_SIZE; + unsigned int dmi_ch4_sw_cntl : RBBM_DSPLY_DMI_CH4_SW_CNTL_SIZE; + unsigned int dmi_ch4_use_bufid2 : RBBM_DSPLY_DMI_CH4_USE_BUFID2_SIZE; + unsigned int dmi_ch4_use_bufid1 : RBBM_DSPLY_DMI_CH4_USE_BUFID1_SIZE; + unsigned int dmi_ch4_use_bufid0 : RBBM_DSPLY_DMI_CH4_USE_BUFID0_SIZE; + unsigned int dmi_ch3_num_bufs : RBBM_DSPLY_DMI_CH3_NUM_BUFS_SIZE; + unsigned int dmi_ch3_sw_cntl : RBBM_DSPLY_DMI_CH3_SW_CNTL_SIZE; + unsigned int dmi_ch3_use_bufid2 : RBBM_DSPLY_DMI_CH3_USE_BUFID2_SIZE; + unsigned int dmi_ch3_use_bufid1 : RBBM_DSPLY_DMI_CH3_USE_BUFID1_SIZE; + unsigned int dmi_ch3_use_bufid0 : RBBM_DSPLY_DMI_CH3_USE_BUFID0_SIZE; + unsigned int : 2; + unsigned int dmi_channel_select : RBBM_DSPLY_DMI_CHANNEL_SELECT_SIZE; + unsigned int dmi_ch2_num_bufs : RBBM_DSPLY_DMI_CH2_NUM_BUFS_SIZE; + unsigned int dmi_ch2_sw_cntl : RBBM_DSPLY_DMI_CH2_SW_CNTL_SIZE; + unsigned int dmi_ch2_use_bufid2 : RBBM_DSPLY_DMI_CH2_USE_BUFID2_SIZE; + unsigned int dmi_ch2_use_bufid1 : RBBM_DSPLY_DMI_CH2_USE_BUFID1_SIZE; + unsigned int dmi_ch2_use_bufid0 : RBBM_DSPLY_DMI_CH2_USE_BUFID0_SIZE; + unsigned int dmi_ch1_num_bufs : RBBM_DSPLY_DMI_CH1_NUM_BUFS_SIZE; + unsigned int dmi_ch1_sw_cntl : RBBM_DSPLY_DMI_CH1_SW_CNTL_SIZE; + unsigned int dmi_ch1_use_bufid2 : RBBM_DSPLY_DMI_CH1_USE_BUFID2_SIZE; + unsigned int dmi_ch1_use_bufid1 : RBBM_DSPLY_DMI_CH1_USE_BUFID1_SIZE; + unsigned int dmi_ch1_use_bufid0 : RBBM_DSPLY_DMI_CH1_USE_BUFID0_SIZE; + unsigned int sel_dmi_vsync_valid : RBBM_DSPLY_SEL_DMI_VSYNC_VALID_SIZE; + unsigned int sel_dmi_active_bufid2 : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID2_SIZE; + unsigned int sel_dmi_active_bufid1 : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID1_SIZE; + unsigned int sel_dmi_active_bufid0 : RBBM_DSPLY_SEL_DMI_ACTIVE_BUFID0_SIZE; + } rbbm_dsply_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_dsply_t f; +} rbbm_dsply_u; + + +/* + * RBBM_RENDER_LATEST struct + */ + +#define RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SIZE 2 +#define RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SIZE 2 +#define RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SIZE 2 +#define RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SIZE 2 + +#define RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT 0 +#define RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT 8 +#define RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT 16 +#define RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT 24 + +#define RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK 0x00000003 +#define RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK 0x00000300 +#define RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK 0x00030000 +#define RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK 0x03000000 + +#define RBBM_RENDER_LATEST_MASK \ + (RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK | \ + RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK | \ + RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK | \ + RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK) + +#define RBBM_RENDER_LATEST(dmi_ch1_buffer_id, dmi_ch2_buffer_id, dmi_ch3_buffer_id, dmi_ch4_buffer_id) \ + ((dmi_ch1_buffer_id << RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT) | \ + (dmi_ch2_buffer_id << RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT) | \ + (dmi_ch3_buffer_id << RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT) | \ + (dmi_ch4_buffer_id << RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT)) + +#define RBBM_RENDER_LATEST_GET_DMI_CH1_BUFFER_ID(rbbm_render_latest) \ + ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT) +#define RBBM_RENDER_LATEST_GET_DMI_CH2_BUFFER_ID(rbbm_render_latest) \ + ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT) +#define RBBM_RENDER_LATEST_GET_DMI_CH3_BUFFER_ID(rbbm_render_latest) \ + ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT) +#define RBBM_RENDER_LATEST_GET_DMI_CH4_BUFFER_ID(rbbm_render_latest) \ + ((rbbm_render_latest & RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK) >> RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT) + +#define RBBM_RENDER_LATEST_SET_DMI_CH1_BUFFER_ID(rbbm_render_latest_reg, dmi_ch1_buffer_id) \ + rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_MASK) | (dmi_ch1_buffer_id << RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SHIFT) +#define RBBM_RENDER_LATEST_SET_DMI_CH2_BUFFER_ID(rbbm_render_latest_reg, dmi_ch2_buffer_id) \ + rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_MASK) | (dmi_ch2_buffer_id << RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SHIFT) +#define RBBM_RENDER_LATEST_SET_DMI_CH3_BUFFER_ID(rbbm_render_latest_reg, dmi_ch3_buffer_id) \ + rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_MASK) | (dmi_ch3_buffer_id << RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SHIFT) +#define RBBM_RENDER_LATEST_SET_DMI_CH4_BUFFER_ID(rbbm_render_latest_reg, dmi_ch4_buffer_id) \ + rbbm_render_latest_reg = (rbbm_render_latest_reg & ~RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_MASK) | (dmi_ch4_buffer_id << RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_render_latest_t { + unsigned int dmi_ch1_buffer_id : RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SIZE; + unsigned int : 6; + unsigned int dmi_ch2_buffer_id : RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SIZE; + unsigned int : 6; + unsigned int dmi_ch3_buffer_id : RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SIZE; + unsigned int : 6; + unsigned int dmi_ch4_buffer_id : RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SIZE; + unsigned int : 6; + } rbbm_render_latest_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_render_latest_t { + unsigned int : 6; + unsigned int dmi_ch4_buffer_id : RBBM_RENDER_LATEST_DMI_CH4_BUFFER_ID_SIZE; + unsigned int : 6; + unsigned int dmi_ch3_buffer_id : RBBM_RENDER_LATEST_DMI_CH3_BUFFER_ID_SIZE; + unsigned int : 6; + unsigned int dmi_ch2_buffer_id : RBBM_RENDER_LATEST_DMI_CH2_BUFFER_ID_SIZE; + unsigned int : 6; + unsigned int dmi_ch1_buffer_id : RBBM_RENDER_LATEST_DMI_CH1_BUFFER_ID_SIZE; + } rbbm_render_latest_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_render_latest_t f; +} rbbm_render_latest_u; + + +/* + * RBBM_RTL_RELEASE struct + */ + +#define RBBM_RTL_RELEASE_CHANGELIST_SIZE 32 + +#define RBBM_RTL_RELEASE_CHANGELIST_SHIFT 0 + +#define RBBM_RTL_RELEASE_CHANGELIST_MASK 0xffffffff + +#define RBBM_RTL_RELEASE_MASK \ + (RBBM_RTL_RELEASE_CHANGELIST_MASK) + +#define RBBM_RTL_RELEASE(changelist) \ + ((changelist << RBBM_RTL_RELEASE_CHANGELIST_SHIFT)) + +#define RBBM_RTL_RELEASE_GET_CHANGELIST(rbbm_rtl_release) \ + ((rbbm_rtl_release & RBBM_RTL_RELEASE_CHANGELIST_MASK) >> RBBM_RTL_RELEASE_CHANGELIST_SHIFT) + +#define RBBM_RTL_RELEASE_SET_CHANGELIST(rbbm_rtl_release_reg, changelist) \ + rbbm_rtl_release_reg = (rbbm_rtl_release_reg & ~RBBM_RTL_RELEASE_CHANGELIST_MASK) | (changelist << RBBM_RTL_RELEASE_CHANGELIST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_rtl_release_t { + unsigned int changelist : RBBM_RTL_RELEASE_CHANGELIST_SIZE; + } rbbm_rtl_release_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_rtl_release_t { + unsigned int changelist : RBBM_RTL_RELEASE_CHANGELIST_SIZE; + } rbbm_rtl_release_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_rtl_release_t f; +} rbbm_rtl_release_u; + + +/* + * RBBM_PATCH_RELEASE struct + */ + +#define RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE 16 +#define RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE 8 +#define RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE 8 + +#define RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT 0 +#define RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT 16 +#define RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT 24 + +#define RBBM_PATCH_RELEASE_PATCH_REVISION_MASK 0x0000ffff +#define RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK 0x00ff0000 +#define RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK 0xff000000 + +#define RBBM_PATCH_RELEASE_MASK \ + (RBBM_PATCH_RELEASE_PATCH_REVISION_MASK | \ + RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK | \ + RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) + +#define RBBM_PATCH_RELEASE(patch_revision, patch_selection, customer_id) \ + ((patch_revision << RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT) | \ + (patch_selection << RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT) | \ + (customer_id << RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT)) + +#define RBBM_PATCH_RELEASE_GET_PATCH_REVISION(rbbm_patch_release) \ + ((rbbm_patch_release & RBBM_PATCH_RELEASE_PATCH_REVISION_MASK) >> RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT) +#define RBBM_PATCH_RELEASE_GET_PATCH_SELECTION(rbbm_patch_release) \ + ((rbbm_patch_release & RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK) >> RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT) +#define RBBM_PATCH_RELEASE_GET_CUSTOMER_ID(rbbm_patch_release) \ + ((rbbm_patch_release & RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) >> RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT) + +#define RBBM_PATCH_RELEASE_SET_PATCH_REVISION(rbbm_patch_release_reg, patch_revision) \ + rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_PATCH_REVISION_MASK) | (patch_revision << RBBM_PATCH_RELEASE_PATCH_REVISION_SHIFT) +#define RBBM_PATCH_RELEASE_SET_PATCH_SELECTION(rbbm_patch_release_reg, patch_selection) \ + rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_PATCH_SELECTION_MASK) | (patch_selection << RBBM_PATCH_RELEASE_PATCH_SELECTION_SHIFT) +#define RBBM_PATCH_RELEASE_SET_CUSTOMER_ID(rbbm_patch_release_reg, customer_id) \ + rbbm_patch_release_reg = (rbbm_patch_release_reg & ~RBBM_PATCH_RELEASE_CUSTOMER_ID_MASK) | (customer_id << RBBM_PATCH_RELEASE_CUSTOMER_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_patch_release_t { + unsigned int patch_revision : RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE; + unsigned int patch_selection : RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE; + unsigned int customer_id : RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE; + } rbbm_patch_release_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_patch_release_t { + unsigned int customer_id : RBBM_PATCH_RELEASE_CUSTOMER_ID_SIZE; + unsigned int patch_selection : RBBM_PATCH_RELEASE_PATCH_SELECTION_SIZE; + unsigned int patch_revision : RBBM_PATCH_RELEASE_PATCH_REVISION_SIZE; + } rbbm_patch_release_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_patch_release_t f; +} rbbm_patch_release_u; + + +/* + * RBBM_AUXILIARY_CONFIG struct + */ + +#define RBBM_AUXILIARY_CONFIG_RESERVED_SIZE 32 + +#define RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT 0 + +#define RBBM_AUXILIARY_CONFIG_RESERVED_MASK 0xffffffff + +#define RBBM_AUXILIARY_CONFIG_MASK \ + (RBBM_AUXILIARY_CONFIG_RESERVED_MASK) + +#define RBBM_AUXILIARY_CONFIG(reserved) \ + ((reserved << RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT)) + +#define RBBM_AUXILIARY_CONFIG_GET_RESERVED(rbbm_auxiliary_config) \ + ((rbbm_auxiliary_config & RBBM_AUXILIARY_CONFIG_RESERVED_MASK) >> RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT) + +#define RBBM_AUXILIARY_CONFIG_SET_RESERVED(rbbm_auxiliary_config_reg, reserved) \ + rbbm_auxiliary_config_reg = (rbbm_auxiliary_config_reg & ~RBBM_AUXILIARY_CONFIG_RESERVED_MASK) | (reserved << RBBM_AUXILIARY_CONFIG_RESERVED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_auxiliary_config_t { + unsigned int reserved : RBBM_AUXILIARY_CONFIG_RESERVED_SIZE; + } rbbm_auxiliary_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_auxiliary_config_t { + unsigned int reserved : RBBM_AUXILIARY_CONFIG_RESERVED_SIZE; + } rbbm_auxiliary_config_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_auxiliary_config_t f; +} rbbm_auxiliary_config_u; + + +/* + * RBBM_PERIPHID0 struct + */ + +#define RBBM_PERIPHID0_PARTNUMBER0_SIZE 8 + +#define RBBM_PERIPHID0_PARTNUMBER0_SHIFT 0 + +#define RBBM_PERIPHID0_PARTNUMBER0_MASK 0x000000ff + +#define RBBM_PERIPHID0_MASK \ + (RBBM_PERIPHID0_PARTNUMBER0_MASK) + +#define RBBM_PERIPHID0(partnumber0) \ + ((partnumber0 << RBBM_PERIPHID0_PARTNUMBER0_SHIFT)) + +#define RBBM_PERIPHID0_GET_PARTNUMBER0(rbbm_periphid0) \ + ((rbbm_periphid0 & RBBM_PERIPHID0_PARTNUMBER0_MASK) >> RBBM_PERIPHID0_PARTNUMBER0_SHIFT) + +#define RBBM_PERIPHID0_SET_PARTNUMBER0(rbbm_periphid0_reg, partnumber0) \ + rbbm_periphid0_reg = (rbbm_periphid0_reg & ~RBBM_PERIPHID0_PARTNUMBER0_MASK) | (partnumber0 << RBBM_PERIPHID0_PARTNUMBER0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_periphid0_t { + unsigned int partnumber0 : RBBM_PERIPHID0_PARTNUMBER0_SIZE; + unsigned int : 24; + } rbbm_periphid0_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_periphid0_t { + unsigned int : 24; + unsigned int partnumber0 : RBBM_PERIPHID0_PARTNUMBER0_SIZE; + } rbbm_periphid0_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_periphid0_t f; +} rbbm_periphid0_u; + + +/* + * RBBM_PERIPHID1 struct + */ + +#define RBBM_PERIPHID1_PARTNUMBER1_SIZE 4 +#define RBBM_PERIPHID1_DESIGNER0_SIZE 4 + +#define RBBM_PERIPHID1_PARTNUMBER1_SHIFT 0 +#define RBBM_PERIPHID1_DESIGNER0_SHIFT 4 + +#define RBBM_PERIPHID1_PARTNUMBER1_MASK 0x0000000f +#define RBBM_PERIPHID1_DESIGNER0_MASK 0x000000f0 + +#define RBBM_PERIPHID1_MASK \ + (RBBM_PERIPHID1_PARTNUMBER1_MASK | \ + RBBM_PERIPHID1_DESIGNER0_MASK) + +#define RBBM_PERIPHID1(partnumber1, designer0) \ + ((partnumber1 << RBBM_PERIPHID1_PARTNUMBER1_SHIFT) | \ + (designer0 << RBBM_PERIPHID1_DESIGNER0_SHIFT)) + +#define RBBM_PERIPHID1_GET_PARTNUMBER1(rbbm_periphid1) \ + ((rbbm_periphid1 & RBBM_PERIPHID1_PARTNUMBER1_MASK) >> RBBM_PERIPHID1_PARTNUMBER1_SHIFT) +#define RBBM_PERIPHID1_GET_DESIGNER0(rbbm_periphid1) \ + ((rbbm_periphid1 & RBBM_PERIPHID1_DESIGNER0_MASK) >> RBBM_PERIPHID1_DESIGNER0_SHIFT) + +#define RBBM_PERIPHID1_SET_PARTNUMBER1(rbbm_periphid1_reg, partnumber1) \ + rbbm_periphid1_reg = (rbbm_periphid1_reg & ~RBBM_PERIPHID1_PARTNUMBER1_MASK) | (partnumber1 << RBBM_PERIPHID1_PARTNUMBER1_SHIFT) +#define RBBM_PERIPHID1_SET_DESIGNER0(rbbm_periphid1_reg, designer0) \ + rbbm_periphid1_reg = (rbbm_periphid1_reg & ~RBBM_PERIPHID1_DESIGNER0_MASK) | (designer0 << RBBM_PERIPHID1_DESIGNER0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_periphid1_t { + unsigned int partnumber1 : RBBM_PERIPHID1_PARTNUMBER1_SIZE; + unsigned int designer0 : RBBM_PERIPHID1_DESIGNER0_SIZE; + unsigned int : 24; + } rbbm_periphid1_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_periphid1_t { + unsigned int : 24; + unsigned int designer0 : RBBM_PERIPHID1_DESIGNER0_SIZE; + unsigned int partnumber1 : RBBM_PERIPHID1_PARTNUMBER1_SIZE; + } rbbm_periphid1_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_periphid1_t f; +} rbbm_periphid1_u; + + +/* + * RBBM_PERIPHID2 struct + */ + +#define RBBM_PERIPHID2_DESIGNER1_SIZE 4 +#define RBBM_PERIPHID2_REVISION_SIZE 4 + +#define RBBM_PERIPHID2_DESIGNER1_SHIFT 0 +#define RBBM_PERIPHID2_REVISION_SHIFT 4 + +#define RBBM_PERIPHID2_DESIGNER1_MASK 0x0000000f +#define RBBM_PERIPHID2_REVISION_MASK 0x000000f0 + +#define RBBM_PERIPHID2_MASK \ + (RBBM_PERIPHID2_DESIGNER1_MASK | \ + RBBM_PERIPHID2_REVISION_MASK) + +#define RBBM_PERIPHID2(designer1, revision) \ + ((designer1 << RBBM_PERIPHID2_DESIGNER1_SHIFT) | \ + (revision << RBBM_PERIPHID2_REVISION_SHIFT)) + +#define RBBM_PERIPHID2_GET_DESIGNER1(rbbm_periphid2) \ + ((rbbm_periphid2 & RBBM_PERIPHID2_DESIGNER1_MASK) >> RBBM_PERIPHID2_DESIGNER1_SHIFT) +#define RBBM_PERIPHID2_GET_REVISION(rbbm_periphid2) \ + ((rbbm_periphid2 & RBBM_PERIPHID2_REVISION_MASK) >> RBBM_PERIPHID2_REVISION_SHIFT) + +#define RBBM_PERIPHID2_SET_DESIGNER1(rbbm_periphid2_reg, designer1) \ + rbbm_periphid2_reg = (rbbm_periphid2_reg & ~RBBM_PERIPHID2_DESIGNER1_MASK) | (designer1 << RBBM_PERIPHID2_DESIGNER1_SHIFT) +#define RBBM_PERIPHID2_SET_REVISION(rbbm_periphid2_reg, revision) \ + rbbm_periphid2_reg = (rbbm_periphid2_reg & ~RBBM_PERIPHID2_REVISION_MASK) | (revision << RBBM_PERIPHID2_REVISION_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_periphid2_t { + unsigned int designer1 : RBBM_PERIPHID2_DESIGNER1_SIZE; + unsigned int revision : RBBM_PERIPHID2_REVISION_SIZE; + unsigned int : 24; + } rbbm_periphid2_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_periphid2_t { + unsigned int : 24; + unsigned int revision : RBBM_PERIPHID2_REVISION_SIZE; + unsigned int designer1 : RBBM_PERIPHID2_DESIGNER1_SIZE; + } rbbm_periphid2_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_periphid2_t f; +} rbbm_periphid2_u; + + +/* + * RBBM_PERIPHID3 struct + */ + +#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE 2 +#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE 2 +#define RBBM_PERIPHID3_MH_INTERFACE_SIZE 2 +#define RBBM_PERIPHID3_CONTINUATION_SIZE 1 + +#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT 0 +#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT 2 +#define RBBM_PERIPHID3_MH_INTERFACE_SHIFT 4 +#define RBBM_PERIPHID3_CONTINUATION_SHIFT 7 + +#define RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK 0x00000003 +#define RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK 0x0000000c +#define RBBM_PERIPHID3_MH_INTERFACE_MASK 0x00000030 +#define RBBM_PERIPHID3_CONTINUATION_MASK 0x00000080 + +#define RBBM_PERIPHID3_MASK \ + (RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK | \ + RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK | \ + RBBM_PERIPHID3_MH_INTERFACE_MASK | \ + RBBM_PERIPHID3_CONTINUATION_MASK) + +#define RBBM_PERIPHID3(rbbm_host_interface, garb_slave_interface, mh_interface, continuation) \ + ((rbbm_host_interface << RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT) | \ + (garb_slave_interface << RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT) | \ + (mh_interface << RBBM_PERIPHID3_MH_INTERFACE_SHIFT) | \ + (continuation << RBBM_PERIPHID3_CONTINUATION_SHIFT)) + +#define RBBM_PERIPHID3_GET_RBBM_HOST_INTERFACE(rbbm_periphid3) \ + ((rbbm_periphid3 & RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK) >> RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_GET_GARB_SLAVE_INTERFACE(rbbm_periphid3) \ + ((rbbm_periphid3 & RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK) >> RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_GET_MH_INTERFACE(rbbm_periphid3) \ + ((rbbm_periphid3 & RBBM_PERIPHID3_MH_INTERFACE_MASK) >> RBBM_PERIPHID3_MH_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_GET_CONTINUATION(rbbm_periphid3) \ + ((rbbm_periphid3 & RBBM_PERIPHID3_CONTINUATION_MASK) >> RBBM_PERIPHID3_CONTINUATION_SHIFT) + +#define RBBM_PERIPHID3_SET_RBBM_HOST_INTERFACE(rbbm_periphid3_reg, rbbm_host_interface) \ + rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_RBBM_HOST_INTERFACE_MASK) | (rbbm_host_interface << RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_SET_GARB_SLAVE_INTERFACE(rbbm_periphid3_reg, garb_slave_interface) \ + rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_MASK) | (garb_slave_interface << RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_SET_MH_INTERFACE(rbbm_periphid3_reg, mh_interface) \ + rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_MH_INTERFACE_MASK) | (mh_interface << RBBM_PERIPHID3_MH_INTERFACE_SHIFT) +#define RBBM_PERIPHID3_SET_CONTINUATION(rbbm_periphid3_reg, continuation) \ + rbbm_periphid3_reg = (rbbm_periphid3_reg & ~RBBM_PERIPHID3_CONTINUATION_MASK) | (continuation << RBBM_PERIPHID3_CONTINUATION_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_periphid3_t { + unsigned int rbbm_host_interface : RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE; + unsigned int garb_slave_interface : RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE; + unsigned int mh_interface : RBBM_PERIPHID3_MH_INTERFACE_SIZE; + unsigned int : 1; + unsigned int continuation : RBBM_PERIPHID3_CONTINUATION_SIZE; + unsigned int : 24; + } rbbm_periphid3_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_periphid3_t { + unsigned int : 24; + unsigned int continuation : RBBM_PERIPHID3_CONTINUATION_SIZE; + unsigned int : 1; + unsigned int mh_interface : RBBM_PERIPHID3_MH_INTERFACE_SIZE; + unsigned int garb_slave_interface : RBBM_PERIPHID3_GARB_SLAVE_INTERFACE_SIZE; + unsigned int rbbm_host_interface : RBBM_PERIPHID3_RBBM_HOST_INTERFACE_SIZE; + } rbbm_periphid3_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_periphid3_t f; +} rbbm_periphid3_u; + + +/* + * RBBM_CNTL struct + */ + +#define RBBM_CNTL_READ_TIMEOUT_SIZE 8 +#define RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE 9 + +#define RBBM_CNTL_READ_TIMEOUT_SHIFT 0 +#define RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT 8 + +#define RBBM_CNTL_READ_TIMEOUT_MASK 0x000000ff +#define RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK 0x0001ff00 + +#define RBBM_CNTL_MASK \ + (RBBM_CNTL_READ_TIMEOUT_MASK | \ + RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) + +#define RBBM_CNTL(read_timeout, regclk_deassert_time) \ + ((read_timeout << RBBM_CNTL_READ_TIMEOUT_SHIFT) | \ + (regclk_deassert_time << RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT)) + +#define RBBM_CNTL_GET_READ_TIMEOUT(rbbm_cntl) \ + ((rbbm_cntl & RBBM_CNTL_READ_TIMEOUT_MASK) >> RBBM_CNTL_READ_TIMEOUT_SHIFT) +#define RBBM_CNTL_GET_REGCLK_DEASSERT_TIME(rbbm_cntl) \ + ((rbbm_cntl & RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) >> RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT) + +#define RBBM_CNTL_SET_READ_TIMEOUT(rbbm_cntl_reg, read_timeout) \ + rbbm_cntl_reg = (rbbm_cntl_reg & ~RBBM_CNTL_READ_TIMEOUT_MASK) | (read_timeout << RBBM_CNTL_READ_TIMEOUT_SHIFT) +#define RBBM_CNTL_SET_REGCLK_DEASSERT_TIME(rbbm_cntl_reg, regclk_deassert_time) \ + rbbm_cntl_reg = (rbbm_cntl_reg & ~RBBM_CNTL_REGCLK_DEASSERT_TIME_MASK) | (regclk_deassert_time << RBBM_CNTL_REGCLK_DEASSERT_TIME_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_cntl_t { + unsigned int read_timeout : RBBM_CNTL_READ_TIMEOUT_SIZE; + unsigned int regclk_deassert_time : RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE; + unsigned int : 15; + } rbbm_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_cntl_t { + unsigned int : 15; + unsigned int regclk_deassert_time : RBBM_CNTL_REGCLK_DEASSERT_TIME_SIZE; + unsigned int read_timeout : RBBM_CNTL_READ_TIMEOUT_SIZE; + } rbbm_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_cntl_t f; +} rbbm_cntl_u; + + +/* + * RBBM_SKEW_CNTL struct + */ + +#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE 5 +#define RBBM_SKEW_CNTL_SKEW_COUNT_SIZE 5 + +#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT 0 +#define RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT 5 + +#define RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK 0x0000001f +#define RBBM_SKEW_CNTL_SKEW_COUNT_MASK 0x000003e0 + +#define RBBM_SKEW_CNTL_MASK \ + (RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK | \ + RBBM_SKEW_CNTL_SKEW_COUNT_MASK) + +#define RBBM_SKEW_CNTL(skew_top_threshold, skew_count) \ + ((skew_top_threshold << RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT) | \ + (skew_count << RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT)) + +#define RBBM_SKEW_CNTL_GET_SKEW_TOP_THRESHOLD(rbbm_skew_cntl) \ + ((rbbm_skew_cntl & RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK) >> RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT) +#define RBBM_SKEW_CNTL_GET_SKEW_COUNT(rbbm_skew_cntl) \ + ((rbbm_skew_cntl & RBBM_SKEW_CNTL_SKEW_COUNT_MASK) >> RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT) + +#define RBBM_SKEW_CNTL_SET_SKEW_TOP_THRESHOLD(rbbm_skew_cntl_reg, skew_top_threshold) \ + rbbm_skew_cntl_reg = (rbbm_skew_cntl_reg & ~RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_MASK) | (skew_top_threshold << RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SHIFT) +#define RBBM_SKEW_CNTL_SET_SKEW_COUNT(rbbm_skew_cntl_reg, skew_count) \ + rbbm_skew_cntl_reg = (rbbm_skew_cntl_reg & ~RBBM_SKEW_CNTL_SKEW_COUNT_MASK) | (skew_count << RBBM_SKEW_CNTL_SKEW_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_skew_cntl_t { + unsigned int skew_top_threshold : RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE; + unsigned int skew_count : RBBM_SKEW_CNTL_SKEW_COUNT_SIZE; + unsigned int : 22; + } rbbm_skew_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_skew_cntl_t { + unsigned int : 22; + unsigned int skew_count : RBBM_SKEW_CNTL_SKEW_COUNT_SIZE; + unsigned int skew_top_threshold : RBBM_SKEW_CNTL_SKEW_TOP_THRESHOLD_SIZE; + } rbbm_skew_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_skew_cntl_t f; +} rbbm_skew_cntl_u; + + +/* + * RBBM_SOFT_RESET struct + */ + +#define RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE 1 +#define RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE 1 + +#define RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT 0 +#define RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT 2 +#define RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT 3 +#define RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT 4 +#define RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT 5 +#define RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT 6 +#define RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT 12 +#define RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT 15 +#define RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT 16 + +#define RBBM_SOFT_RESET_SOFT_RESET_CP_MASK 0x00000001 +#define RBBM_SOFT_RESET_SOFT_RESET_PA_MASK 0x00000004 +#define RBBM_SOFT_RESET_SOFT_RESET_MH_MASK 0x00000008 +#define RBBM_SOFT_RESET_SOFT_RESET_BC_MASK 0x00000010 +#define RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK 0x00000020 +#define RBBM_SOFT_RESET_SOFT_RESET_SX_MASK 0x00000040 +#define RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK 0x00001000 +#define RBBM_SOFT_RESET_SOFT_RESET_SC_MASK 0x00008000 +#define RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK 0x00010000 + +#define RBBM_SOFT_RESET_MASK \ + (RBBM_SOFT_RESET_SOFT_RESET_CP_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_PA_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_MH_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_BC_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_SX_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_SC_MASK | \ + RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) + +#define RBBM_SOFT_RESET(soft_reset_cp, soft_reset_pa, soft_reset_mh, soft_reset_bc, soft_reset_sq, soft_reset_sx, soft_reset_cib, soft_reset_sc, soft_reset_vgt) \ + ((soft_reset_cp << RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT) | \ + (soft_reset_pa << RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT) | \ + (soft_reset_mh << RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT) | \ + (soft_reset_bc << RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT) | \ + (soft_reset_sq << RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT) | \ + (soft_reset_sx << RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT) | \ + (soft_reset_cib << RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT) | \ + (soft_reset_sc << RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT) | \ + (soft_reset_vgt << RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT)) + +#define RBBM_SOFT_RESET_GET_SOFT_RESET_CP(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_CP_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_PA(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_PA_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_MH(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_MH_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_BC(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_BC_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_SQ(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_SX(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SX_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_CIB(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_SC(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_SC_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT) +#define RBBM_SOFT_RESET_GET_SOFT_RESET_VGT(rbbm_soft_reset) \ + ((rbbm_soft_reset & RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) >> RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT) + +#define RBBM_SOFT_RESET_SET_SOFT_RESET_CP(rbbm_soft_reset_reg, soft_reset_cp) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_CP_MASK) | (soft_reset_cp << RBBM_SOFT_RESET_SOFT_RESET_CP_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_PA(rbbm_soft_reset_reg, soft_reset_pa) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_PA_MASK) | (soft_reset_pa << RBBM_SOFT_RESET_SOFT_RESET_PA_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_MH(rbbm_soft_reset_reg, soft_reset_mh) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_MH_MASK) | (soft_reset_mh << RBBM_SOFT_RESET_SOFT_RESET_MH_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_BC(rbbm_soft_reset_reg, soft_reset_bc) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_BC_MASK) | (soft_reset_bc << RBBM_SOFT_RESET_SOFT_RESET_BC_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_SQ(rbbm_soft_reset_reg, soft_reset_sq) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SQ_MASK) | (soft_reset_sq << RBBM_SOFT_RESET_SOFT_RESET_SQ_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_SX(rbbm_soft_reset_reg, soft_reset_sx) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SX_MASK) | (soft_reset_sx << RBBM_SOFT_RESET_SOFT_RESET_SX_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_CIB(rbbm_soft_reset_reg, soft_reset_cib) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_CIB_MASK) | (soft_reset_cib << RBBM_SOFT_RESET_SOFT_RESET_CIB_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_SC(rbbm_soft_reset_reg, soft_reset_sc) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_SC_MASK) | (soft_reset_sc << RBBM_SOFT_RESET_SOFT_RESET_SC_SHIFT) +#define RBBM_SOFT_RESET_SET_SOFT_RESET_VGT(rbbm_soft_reset_reg, soft_reset_vgt) \ + rbbm_soft_reset_reg = (rbbm_soft_reset_reg & ~RBBM_SOFT_RESET_SOFT_RESET_VGT_MASK) | (soft_reset_vgt << RBBM_SOFT_RESET_SOFT_RESET_VGT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_soft_reset_t { + unsigned int soft_reset_cp : RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE; + unsigned int : 1; + unsigned int soft_reset_pa : RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE; + unsigned int soft_reset_mh : RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE; + unsigned int soft_reset_bc : RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE; + unsigned int soft_reset_sq : RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE; + unsigned int soft_reset_sx : RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE; + unsigned int : 5; + unsigned int soft_reset_cib : RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE; + unsigned int : 2; + unsigned int soft_reset_sc : RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE; + unsigned int soft_reset_vgt : RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE; + unsigned int : 15; + } rbbm_soft_reset_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_soft_reset_t { + unsigned int : 15; + unsigned int soft_reset_vgt : RBBM_SOFT_RESET_SOFT_RESET_VGT_SIZE; + unsigned int soft_reset_sc : RBBM_SOFT_RESET_SOFT_RESET_SC_SIZE; + unsigned int : 2; + unsigned int soft_reset_cib : RBBM_SOFT_RESET_SOFT_RESET_CIB_SIZE; + unsigned int : 5; + unsigned int soft_reset_sx : RBBM_SOFT_RESET_SOFT_RESET_SX_SIZE; + unsigned int soft_reset_sq : RBBM_SOFT_RESET_SOFT_RESET_SQ_SIZE; + unsigned int soft_reset_bc : RBBM_SOFT_RESET_SOFT_RESET_BC_SIZE; + unsigned int soft_reset_mh : RBBM_SOFT_RESET_SOFT_RESET_MH_SIZE; + unsigned int soft_reset_pa : RBBM_SOFT_RESET_SOFT_RESET_PA_SIZE; + unsigned int : 1; + unsigned int soft_reset_cp : RBBM_SOFT_RESET_SOFT_RESET_CP_SIZE; + } rbbm_soft_reset_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_soft_reset_t f; +} rbbm_soft_reset_u; + + +/* + * RBBM_PM_OVERRIDE1 struct + */ + +#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE 1 + +#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT 0 +#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT 1 +#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT 2 +#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT 3 +#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT 4 +#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT 5 +#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT 6 +#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT 7 +#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT 8 +#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT 9 +#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT 10 +#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT 11 +#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT 12 +#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT 13 +#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT 14 +#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT 15 +#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT 16 +#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT 17 +#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT 18 +#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT 19 +#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT 20 +#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT 21 +#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT 22 +#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT 23 +#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT 24 +#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT 25 +#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT 26 +#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT 27 +#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT 28 +#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT 29 +#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT 30 +#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT 31 + +#define RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK 0x00000001 +#define RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK 0x00000002 +#define RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK 0x00000004 +#define RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK 0x00000008 +#define RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK 0x00000010 +#define RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK 0x00000020 +#define RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000040 +#define RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK 0x00000080 +#define RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK 0x00000100 +#define RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK 0x00000200 +#define RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK 0x00000400 +#define RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK 0x00000800 +#define RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK 0x00001000 +#define RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK 0x00002000 +#define RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK 0x00004000 +#define RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK 0x00008000 +#define RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK 0x00010000 +#define RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK 0x00020000 +#define RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK 0x00040000 +#define RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK 0x00080000 +#define RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK 0x00100000 +#define RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK 0x00200000 +#define RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK 0x00400000 +#define RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK 0x00800000 +#define RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK 0x01000000 +#define RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK 0x02000000 +#define RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK 0x04000000 +#define RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK 0x08000000 +#define RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK 0x10000000 +#define RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK 0x20000000 +#define RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK 0x40000000 +#define RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK 0x80000000 + +#define RBBM_PM_OVERRIDE1_MASK \ + (RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) + +#define RBBM_PM_OVERRIDE1(rbbm_ahbclk_pm_override, sc_reg_sclk_pm_override, sc_sclk_pm_override, sp_top_sclk_pm_override, sp_v0_sclk_pm_override, sq_reg_sclk_pm_override, sq_reg_fifos_sclk_pm_override, sq_const_mem_sclk_pm_override, sq_sq_sclk_pm_override, sx_sclk_pm_override, sx_reg_sclk_pm_override, tcm_tco_sclk_pm_override, tcm_tcm_sclk_pm_override, tcm_tcd_sclk_pm_override, tcm_reg_sclk_pm_override, tpc_tpc_sclk_pm_override, tpc_reg_sclk_pm_override, tcf_tca_sclk_pm_override, tcf_tcb_sclk_pm_override, tcf_tcb_read_sclk_pm_override, tp_tp_sclk_pm_override, tp_reg_sclk_pm_override, cp_g_sclk_pm_override, cp_reg_sclk_pm_override, cp_g_reg_sclk_pm_override, spi_sclk_pm_override, rb_reg_sclk_pm_override, rb_sclk_pm_override, mh_mh_sclk_pm_override, mh_reg_sclk_pm_override, mh_mmu_sclk_pm_override, mh_tcroq_sclk_pm_override) \ + ((rbbm_ahbclk_pm_override << RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT) | \ + (sc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (sc_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT) | \ + (sp_top_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT) | \ + (sp_v0_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT) | \ + (sq_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (sq_reg_fifos_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT) | \ + (sq_const_mem_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT) | \ + (sq_sq_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT) | \ + (sx_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT) | \ + (sx_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcm_tco_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcm_tcm_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcm_tcd_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcm_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (tpc_tpc_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT) | \ + (tpc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcf_tca_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcf_tcb_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT) | \ + (tcf_tcb_read_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT) | \ + (tp_tp_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT) | \ + (tp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (cp_g_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT) | \ + (cp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (cp_g_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (spi_sclk_pm_override << RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT) | \ + (rb_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (rb_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT) | \ + (mh_mh_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT) | \ + (mh_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (mh_mmu_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT) | \ + (mh_tcroq_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT)) + +#define RBBM_PM_OVERRIDE1_GET_RBBM_AHBCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SC_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SP_TOP_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SP_V0_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SQ_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SQ_REG_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SQ_CONST_MEM_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SQ_SQ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SX_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SX_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCM_TCO_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCM_TCM_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCM_TCD_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCM_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TPC_TPC_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TPC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCF_TCA_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCF_TCB_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TCF_TCB_READ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TP_TP_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_TP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_CP_G_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_CP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_CP_G_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_SPI_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_RB_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_RB_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_MH_MH_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_MH_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_MH_MMU_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_GET_MH_TCROQ_SCLK_PM_OVERRIDE(rbbm_pm_override1) \ + ((rbbm_pm_override1 & RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT) + +#define RBBM_PM_OVERRIDE1_SET_RBBM_AHBCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rbbm_ahbclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_MASK) | (rbbm_ahbclk_pm_override << RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sc_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_MASK) | (sc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SC_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sc_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_MASK) | (sc_sclk_pm_override << RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SP_TOP_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sp_top_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_MASK) | (sp_top_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SP_V0_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sp_v0_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_MASK) | (sp_v0_sclk_pm_override << RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SQ_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_MASK) | (sq_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SQ_REG_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_reg_fifos_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_MASK) | (sq_reg_fifos_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SQ_CONST_MEM_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_const_mem_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_MASK) | (sq_const_mem_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SQ_SQ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sq_sq_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_MASK) | (sq_sq_sclk_pm_override << RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SX_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sx_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_MASK) | (sx_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SX_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, sx_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_MASK) | (sx_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCM_TCO_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tco_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_MASK) | (tcm_tco_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCM_TCM_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tcm_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_MASK) | (tcm_tcm_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCM_TCD_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_tcd_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_MASK) | (tcm_tcd_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCM_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcm_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_MASK) | (tcm_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TPC_TPC_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tpc_tpc_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_MASK) | (tpc_tpc_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TPC_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tpc_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_MASK) | (tpc_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCF_TCA_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tca_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_MASK) | (tcf_tca_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCF_TCB_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tcb_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_MASK) | (tcf_tcb_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TCF_TCB_READ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tcf_tcb_read_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_MASK) | (tcf_tcb_read_sclk_pm_override << RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TP_TP_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tp_tp_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_MASK) | (tp_tp_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_TP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, tp_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_MASK) | (tp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_CP_G_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_g_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_MASK) | (cp_g_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_CP_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_MASK) | (cp_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_CP_G_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, cp_g_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_MASK) | (cp_g_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_SPI_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, spi_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_MASK) | (spi_sclk_pm_override << RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_RB_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rb_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_MASK) | (rb_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_RB_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, rb_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_MASK) | (rb_sclk_pm_override << RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_MH_MH_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_mh_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_MASK) | (mh_mh_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_MH_REG_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_reg_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_MASK) | (mh_reg_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_MH_MMU_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_mmu_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_MASK) | (mh_mmu_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE1_SET_MH_TCROQ_SCLK_PM_OVERRIDE(rbbm_pm_override1_reg, mh_tcroq_sclk_pm_override) \ + rbbm_pm_override1_reg = (rbbm_pm_override1_reg & ~RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_MASK) | (mh_tcroq_sclk_pm_override << RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_pm_override1_t { + unsigned int rbbm_ahbclk_pm_override : RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE; + unsigned int sc_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int sc_sclk_pm_override : RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE; + unsigned int sp_top_sclk_pm_override : RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE; + unsigned int sp_v0_sclk_pm_override : RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_reg_fifos_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_const_mem_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_sq_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE; + unsigned int sx_sclk_pm_override : RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE; + unsigned int sx_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tco_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tcm_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tcd_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tpc_tpc_sclk_pm_override : RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE; + unsigned int tpc_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tca_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tcb_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tcb_read_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE; + unsigned int tp_tp_sclk_pm_override : RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE; + unsigned int tp_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_g_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_g_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int spi_sclk_pm_override : RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE; + unsigned int rb_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int rb_sclk_pm_override : RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_mh_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_mmu_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_tcroq_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE; + } rbbm_pm_override1_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_pm_override1_t { + unsigned int mh_tcroq_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_mmu_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int mh_mh_sclk_pm_override : RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE_SIZE; + unsigned int rb_sclk_pm_override : RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE_SIZE; + unsigned int rb_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int spi_sclk_pm_override : RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_g_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int cp_g_sclk_pm_override : RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE_SIZE; + unsigned int tp_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tp_tp_sclk_pm_override : RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tcb_read_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tcb_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcf_tca_sclk_pm_override : RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE_SIZE; + unsigned int tpc_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tpc_tpc_sclk_pm_override : RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tcd_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tcm_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE_SIZE; + unsigned int tcm_tco_sclk_pm_override : RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE_SIZE; + unsigned int sx_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int sx_sclk_pm_override : RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_sq_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_const_mem_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_reg_fifos_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE_SIZE; + unsigned int sq_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int sp_v0_sclk_pm_override : RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE_SIZE; + unsigned int sp_top_sclk_pm_override : RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE_SIZE; + unsigned int sc_sclk_pm_override : RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE_SIZE; + unsigned int sc_reg_sclk_pm_override : RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int rbbm_ahbclk_pm_override : RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE_SIZE; + } rbbm_pm_override1_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_pm_override1_t f; +} rbbm_pm_override1_u; + + +/* + * RBBM_PM_OVERRIDE2 struct + */ + +#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE 1 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE 1 + +#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT 0 +#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT 1 +#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT 2 +#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT 3 +#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT 4 +#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT 5 +#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT 6 +#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT 7 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT 8 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT 9 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT 10 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT 11 + +#define RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK 0x00000001 +#define RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK 0x00000002 +#define RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK 0x00000004 +#define RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK 0x00000008 +#define RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK 0x00000010 +#define RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK 0x00000020 +#define RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK 0x00000040 +#define RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK 0x00000080 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK 0x00000100 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK 0x00000200 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK 0x00000400 +#define RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK 0x00000800 + +#define RBBM_PM_OVERRIDE2_MASK \ + (RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK | \ + RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) + +#define RBBM_PM_OVERRIDE2(pa_reg_sclk_pm_override, pa_pa_sclk_pm_override, pa_ag_sclk_pm_override, vgt_reg_sclk_pm_override, vgt_fifos_sclk_pm_override, vgt_vgt_sclk_pm_override, debug_perf_sclk_pm_override, perm_sclk_pm_override, gc_ga_gmem0_pm_override, gc_ga_gmem1_pm_override, gc_ga_gmem2_pm_override, gc_ga_gmem3_pm_override) \ + ((pa_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (pa_pa_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT) | \ + (pa_ag_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT) | \ + (vgt_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT) | \ + (vgt_fifos_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT) | \ + (vgt_vgt_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT) | \ + (debug_perf_sclk_pm_override << RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT) | \ + (perm_sclk_pm_override << RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT) | \ + (gc_ga_gmem0_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT) | \ + (gc_ga_gmem1_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT) | \ + (gc_ga_gmem2_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT) | \ + (gc_ga_gmem3_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT)) + +#define RBBM_PM_OVERRIDE2_GET_PA_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_PA_PA_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_PA_AG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_VGT_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_VGT_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_VGT_VGT_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_DEBUG_PERF_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_PERM_SCLK_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM0_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM1_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM2_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_GET_GC_GA_GMEM3_PM_OVERRIDE(rbbm_pm_override2) \ + ((rbbm_pm_override2 & RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) >> RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT) + +#define RBBM_PM_OVERRIDE2_SET_PA_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_reg_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_MASK) | (pa_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_PA_PA_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_pa_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_MASK) | (pa_pa_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_PA_AG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, pa_ag_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_MASK) | (pa_ag_sclk_pm_override << RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_VGT_REG_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_reg_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_MASK) | (vgt_reg_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_VGT_FIFOS_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_fifos_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_MASK) | (vgt_fifos_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_VGT_VGT_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, vgt_vgt_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_MASK) | (vgt_vgt_sclk_pm_override << RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_DEBUG_PERF_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, debug_perf_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_MASK) | (debug_perf_sclk_pm_override << RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_PERM_SCLK_PM_OVERRIDE(rbbm_pm_override2_reg, perm_sclk_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_MASK) | (perm_sclk_pm_override << RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM0_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem0_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_MASK) | (gc_ga_gmem0_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM1_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem1_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_MASK) | (gc_ga_gmem1_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM2_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem2_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_MASK) | (gc_ga_gmem2_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SHIFT) +#define RBBM_PM_OVERRIDE2_SET_GC_GA_GMEM3_PM_OVERRIDE(rbbm_pm_override2_reg, gc_ga_gmem3_pm_override) \ + rbbm_pm_override2_reg = (rbbm_pm_override2_reg & ~RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_MASK) | (gc_ga_gmem3_pm_override << RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_pm_override2_t { + unsigned int pa_reg_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_pa_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_ag_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_reg_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_fifos_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_vgt_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE; + unsigned int debug_perf_sclk_pm_override : RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE; + unsigned int perm_sclk_pm_override : RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem0_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem1_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem2_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem3_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE; + unsigned int : 20; + } rbbm_pm_override2_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_pm_override2_t { + unsigned int : 20; + unsigned int gc_ga_gmem3_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem2_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem1_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE_SIZE; + unsigned int gc_ga_gmem0_pm_override : RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE_SIZE; + unsigned int perm_sclk_pm_override : RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE_SIZE; + unsigned int debug_perf_sclk_pm_override : RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_vgt_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_fifos_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE_SIZE; + unsigned int vgt_reg_sclk_pm_override : RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_ag_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_pa_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE_SIZE; + unsigned int pa_reg_sclk_pm_override : RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE_SIZE; + } rbbm_pm_override2_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_pm_override2_t f; +} rbbm_pm_override2_u; + + +/* + * GC_SYS_IDLE struct + */ + +#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE 16 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SIZE 6 +#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SIZE 1 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_SIZE 1 +#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SIZE 1 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SIZE 1 +#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE 1 + +#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT 0 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT 16 +#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT 24 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT 25 +#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT 29 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT 30 +#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT 31 + +#define GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK 0x0000ffff +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK 0x003f0000 +#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK 0x01000000 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK 0x02000000 +#define GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK 0x20000000 +#define GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK 0x40000000 +#define GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK 0x80000000 + +#define GC_SYS_IDLE_MASK \ + (GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK | \ + GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK | \ + GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK | \ + GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK | \ + GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK | \ + GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK | \ + GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) + +#define GC_SYS_IDLE(gc_sys_idle_delay, gc_sys_wait_dmi_mask, gc_sys_urgent_ramp, gc_sys_wait_dmi, gc_sys_urgent_ramp_override, gc_sys_wait_dmi_override, gc_sys_idle_override) \ + ((gc_sys_idle_delay << GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT) | \ + (gc_sys_wait_dmi_mask << GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT) | \ + (gc_sys_urgent_ramp << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT) | \ + (gc_sys_wait_dmi << GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT) | \ + (gc_sys_urgent_ramp_override << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT) | \ + (gc_sys_wait_dmi_override << GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT) | \ + (gc_sys_idle_override << GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT)) + +#define GC_SYS_IDLE_GET_GC_SYS_IDLE_DELAY(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK) >> GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT) +#define GC_SYS_IDLE_GET_GC_SYS_WAIT_DMI_MASK(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK) >> GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT) +#define GC_SYS_IDLE_GET_GC_SYS_URGENT_RAMP(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK) >> GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT) +#define GC_SYS_IDLE_GET_GC_SYS_WAIT_DMI(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK) >> GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT) +#define GC_SYS_IDLE_GET_GC_SYS_URGENT_RAMP_OVERRIDE(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK) >> GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT) +#define GC_SYS_IDLE_GET_GC_SYS_WAIT_DMI_OVERRIDE(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK) >> GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT) +#define GC_SYS_IDLE_GET_GC_SYS_IDLE_OVERRIDE(gc_sys_idle) \ + ((gc_sys_idle & GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) >> GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT) + +#define GC_SYS_IDLE_SET_GC_SYS_IDLE_DELAY(gc_sys_idle_reg, gc_sys_idle_delay) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_IDLE_DELAY_MASK) | (gc_sys_idle_delay << GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SHIFT) +#define GC_SYS_IDLE_SET_GC_SYS_WAIT_DMI_MASK(gc_sys_idle_reg, gc_sys_wait_dmi_mask) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_MASK) | (gc_sys_wait_dmi_mask << GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SHIFT) +#define GC_SYS_IDLE_SET_GC_SYS_URGENT_RAMP(gc_sys_idle_reg, gc_sys_urgent_ramp) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_URGENT_RAMP_MASK) | (gc_sys_urgent_ramp << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SHIFT) +#define GC_SYS_IDLE_SET_GC_SYS_WAIT_DMI(gc_sys_idle_reg, gc_sys_wait_dmi) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK) | (gc_sys_wait_dmi << GC_SYS_IDLE_GC_SYS_WAIT_DMI_SHIFT) +#define GC_SYS_IDLE_SET_GC_SYS_URGENT_RAMP_OVERRIDE(gc_sys_idle_reg, gc_sys_urgent_ramp_override) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_MASK) | (gc_sys_urgent_ramp_override << GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SHIFT) +#define GC_SYS_IDLE_SET_GC_SYS_WAIT_DMI_OVERRIDE(gc_sys_idle_reg, gc_sys_wait_dmi_override) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_MASK) | (gc_sys_wait_dmi_override << GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SHIFT) +#define GC_SYS_IDLE_SET_GC_SYS_IDLE_OVERRIDE(gc_sys_idle_reg, gc_sys_idle_override) \ + gc_sys_idle_reg = (gc_sys_idle_reg & ~GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_MASK) | (gc_sys_idle_override << GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _gc_sys_idle_t { + unsigned int gc_sys_idle_delay : GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE; + unsigned int gc_sys_wait_dmi_mask : GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SIZE; + unsigned int : 2; + unsigned int gc_sys_urgent_ramp : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SIZE; + unsigned int gc_sys_wait_dmi : GC_SYS_IDLE_GC_SYS_WAIT_DMI_SIZE; + unsigned int : 3; + unsigned int gc_sys_urgent_ramp_override : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SIZE; + unsigned int gc_sys_wait_dmi_override : GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SIZE; + unsigned int gc_sys_idle_override : GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE; + } gc_sys_idle_t; + +#else // !BIGENDIAN_OS + + typedef struct _gc_sys_idle_t { + unsigned int gc_sys_idle_override : GC_SYS_IDLE_GC_SYS_IDLE_OVERRIDE_SIZE; + unsigned int gc_sys_wait_dmi_override : GC_SYS_IDLE_GC_SYS_WAIT_DMI_OVERRIDE_SIZE; + unsigned int gc_sys_urgent_ramp_override : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_OVERRIDE_SIZE; + unsigned int : 3; + unsigned int gc_sys_wait_dmi : GC_SYS_IDLE_GC_SYS_WAIT_DMI_SIZE; + unsigned int gc_sys_urgent_ramp : GC_SYS_IDLE_GC_SYS_URGENT_RAMP_SIZE; + unsigned int : 2; + unsigned int gc_sys_wait_dmi_mask : GC_SYS_IDLE_GC_SYS_WAIT_DMI_MASK_SIZE; + unsigned int gc_sys_idle_delay : GC_SYS_IDLE_GC_SYS_IDLE_DELAY_SIZE; + } gc_sys_idle_t; + +#endif + +typedef union { + unsigned int val : 32; + gc_sys_idle_t f; +} gc_sys_idle_u; + + +/* + * NQWAIT_UNTIL struct + */ + +#define NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE 1 + +#define NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT 0 + +#define NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK 0x00000001 + +#define NQWAIT_UNTIL_MASK \ + (NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) + +#define NQWAIT_UNTIL(wait_gui_idle) \ + ((wait_gui_idle << NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT)) + +#define NQWAIT_UNTIL_GET_WAIT_GUI_IDLE(nqwait_until) \ + ((nqwait_until & NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) >> NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT) + +#define NQWAIT_UNTIL_SET_WAIT_GUI_IDLE(nqwait_until_reg, wait_gui_idle) \ + nqwait_until_reg = (nqwait_until_reg & ~NQWAIT_UNTIL_WAIT_GUI_IDLE_MASK) | (wait_gui_idle << NQWAIT_UNTIL_WAIT_GUI_IDLE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _nqwait_until_t { + unsigned int wait_gui_idle : NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE; + unsigned int : 31; + } nqwait_until_t; + +#else // !BIGENDIAN_OS + + typedef struct _nqwait_until_t { + unsigned int : 31; + unsigned int wait_gui_idle : NQWAIT_UNTIL_WAIT_GUI_IDLE_SIZE; + } nqwait_until_t; + +#endif + +typedef union { + unsigned int val : 32; + nqwait_until_t f; +} nqwait_until_u; + + +/* + * RBBM_DEBUG_OUT struct + */ + +#define RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SIZE 32 + +#define RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT 0 + +#define RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK 0xffffffff + +#define RBBM_DEBUG_OUT_MASK \ + (RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK) + +#define RBBM_DEBUG_OUT(debug_bus_out) \ + ((debug_bus_out << RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT)) + +#define RBBM_DEBUG_OUT_GET_DEBUG_BUS_OUT(rbbm_debug_out) \ + ((rbbm_debug_out & RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK) >> RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT) + +#define RBBM_DEBUG_OUT_SET_DEBUG_BUS_OUT(rbbm_debug_out_reg, debug_bus_out) \ + rbbm_debug_out_reg = (rbbm_debug_out_reg & ~RBBM_DEBUG_OUT_DEBUG_BUS_OUT_MASK) | (debug_bus_out << RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_debug_out_t { + unsigned int debug_bus_out : RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SIZE; + } rbbm_debug_out_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_debug_out_t { + unsigned int debug_bus_out : RBBM_DEBUG_OUT_DEBUG_BUS_OUT_SIZE; + } rbbm_debug_out_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_debug_out_t f; +} rbbm_debug_out_u; + + +/* + * RBBM_DEBUG_CNTL struct + */ + +#define RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SIZE 6 +#define RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SIZE 4 +#define RBBM_DEBUG_CNTL_SW_ENABLE_SIZE 1 +#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SIZE 6 +#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SIZE 4 +#define RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SIZE 4 + +#define RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT 0 +#define RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT 8 +#define RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT 12 +#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT 16 +#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT 24 +#define RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT 28 + +#define RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK 0x0000003f +#define RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK 0x00000f00 +#define RBBM_DEBUG_CNTL_SW_ENABLE_MASK 0x00001000 +#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK 0x003f0000 +#define RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK 0x0f000000 +#define RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK 0xf0000000 + +#define RBBM_DEBUG_CNTL_MASK \ + (RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK | \ + RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK | \ + RBBM_DEBUG_CNTL_SW_ENABLE_MASK | \ + RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK | \ + RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK | \ + RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK) + +#define RBBM_DEBUG_CNTL(sub_block_addr, sub_block_sel, sw_enable, gpio_sub_block_addr, gpio_sub_block_sel, gpio_byte_lane_enb) \ + ((sub_block_addr << RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT) | \ + (sub_block_sel << RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT) | \ + (sw_enable << RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT) | \ + (gpio_sub_block_addr << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT) | \ + (gpio_sub_block_sel << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT) | \ + (gpio_byte_lane_enb << RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT)) + +#define RBBM_DEBUG_CNTL_GET_SUB_BLOCK_ADDR(rbbm_debug_cntl) \ + ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK) >> RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT) +#define RBBM_DEBUG_CNTL_GET_SUB_BLOCK_SEL(rbbm_debug_cntl) \ + ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK) >> RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT) +#define RBBM_DEBUG_CNTL_GET_SW_ENABLE(rbbm_debug_cntl) \ + ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_SW_ENABLE_MASK) >> RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT) +#define RBBM_DEBUG_CNTL_GET_GPIO_SUB_BLOCK_ADDR(rbbm_debug_cntl) \ + ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK) >> RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT) +#define RBBM_DEBUG_CNTL_GET_GPIO_SUB_BLOCK_SEL(rbbm_debug_cntl) \ + ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK) >> RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT) +#define RBBM_DEBUG_CNTL_GET_GPIO_BYTE_LANE_ENB(rbbm_debug_cntl) \ + ((rbbm_debug_cntl & RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK) >> RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT) + +#define RBBM_DEBUG_CNTL_SET_SUB_BLOCK_ADDR(rbbm_debug_cntl_reg, sub_block_addr) \ + rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_MASK) | (sub_block_addr << RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SHIFT) +#define RBBM_DEBUG_CNTL_SET_SUB_BLOCK_SEL(rbbm_debug_cntl_reg, sub_block_sel) \ + rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_MASK) | (sub_block_sel << RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SHIFT) +#define RBBM_DEBUG_CNTL_SET_SW_ENABLE(rbbm_debug_cntl_reg, sw_enable) \ + rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_SW_ENABLE_MASK) | (sw_enable << RBBM_DEBUG_CNTL_SW_ENABLE_SHIFT) +#define RBBM_DEBUG_CNTL_SET_GPIO_SUB_BLOCK_ADDR(rbbm_debug_cntl_reg, gpio_sub_block_addr) \ + rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_MASK) | (gpio_sub_block_addr << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SHIFT) +#define RBBM_DEBUG_CNTL_SET_GPIO_SUB_BLOCK_SEL(rbbm_debug_cntl_reg, gpio_sub_block_sel) \ + rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_MASK) | (gpio_sub_block_sel << RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SHIFT) +#define RBBM_DEBUG_CNTL_SET_GPIO_BYTE_LANE_ENB(rbbm_debug_cntl_reg, gpio_byte_lane_enb) \ + rbbm_debug_cntl_reg = (rbbm_debug_cntl_reg & ~RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_MASK) | (gpio_byte_lane_enb << RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_debug_cntl_t { + unsigned int sub_block_addr : RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SIZE; + unsigned int : 2; + unsigned int sub_block_sel : RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SIZE; + unsigned int sw_enable : RBBM_DEBUG_CNTL_SW_ENABLE_SIZE; + unsigned int : 3; + unsigned int gpio_sub_block_addr : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SIZE; + unsigned int : 2; + unsigned int gpio_sub_block_sel : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SIZE; + unsigned int gpio_byte_lane_enb : RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SIZE; + } rbbm_debug_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_debug_cntl_t { + unsigned int gpio_byte_lane_enb : RBBM_DEBUG_CNTL_GPIO_BYTE_LANE_ENB_SIZE; + unsigned int gpio_sub_block_sel : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_SEL_SIZE; + unsigned int : 2; + unsigned int gpio_sub_block_addr : RBBM_DEBUG_CNTL_GPIO_SUB_BLOCK_ADDR_SIZE; + unsigned int : 3; + unsigned int sw_enable : RBBM_DEBUG_CNTL_SW_ENABLE_SIZE; + unsigned int sub_block_sel : RBBM_DEBUG_CNTL_SUB_BLOCK_SEL_SIZE; + unsigned int : 2; + unsigned int sub_block_addr : RBBM_DEBUG_CNTL_SUB_BLOCK_ADDR_SIZE; + } rbbm_debug_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_debug_cntl_t f; +} rbbm_debug_cntl_u; + + +/* + * RBBM_DEBUG struct + */ + +#define RBBM_DEBUG_IGNORE_RTR_SIZE 1 +#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE 1 +#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE 1 +#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE 1 +#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE 4 +#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE 1 +#define RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE 1 +#define RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE 1 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE 1 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE 1 +#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE 1 + +#define RBBM_DEBUG_IGNORE_RTR_SHIFT 1 +#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT 2 +#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT 3 +#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT 4 +#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT 8 +#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT 16 +#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT 17 +#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT 18 +#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT 19 +#define RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT 20 +#define RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT 21 +#define RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT 22 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT 23 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT 24 +#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT 31 + +#define RBBM_DEBUG_IGNORE_RTR_MASK 0x00000002 +#define RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK 0x00000004 +#define RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK 0x00000008 +#define RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK 0x00000010 +#define RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK 0x00000f00 +#define RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK 0x00010000 +#define RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK 0x00020000 +#define RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK 0x00040000 +#define RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK 0x00080000 +#define RBBM_DEBUG_CP_RBBM_NRTRTR_MASK 0x00100000 +#define RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK 0x00200000 +#define RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK 0x00400000 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK 0x00800000 +#define RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK 0x01000000 +#define RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK 0x80000000 + +#define RBBM_DEBUG_MASK \ + (RBBM_DEBUG_IGNORE_RTR_MASK | \ + RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK | \ + RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK | \ + RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK | \ + RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK | \ + RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK | \ + RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK | \ + RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK | \ + RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK | \ + RBBM_DEBUG_CP_RBBM_NRTRTR_MASK | \ + RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK | \ + RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK | \ + RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK | \ + RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK | \ + RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) + +#define RBBM_DEBUG(ignore_rtr, ignore_cp_sched_wu, ignore_cp_sched_isync, ignore_cp_sched_nq_hi, hysteresis_nrt_gui_active, ignore_rtr_for_hi, ignore_cp_rbbm_nrtrtr_for_hi, ignore_vgt_rbbm_nrtrtr_for_hi, ignore_sq_rbbm_nrtrtr_for_hi, cp_rbbm_nrtrtr, vgt_rbbm_nrtrtr, sq_rbbm_nrtrtr, clients_for_nrt_rtr_for_hi, clients_for_nrt_rtr, ignore_sx_rbbm_busy) \ + ((ignore_rtr << RBBM_DEBUG_IGNORE_RTR_SHIFT) | \ + (ignore_cp_sched_wu << RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT) | \ + (ignore_cp_sched_isync << RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT) | \ + (ignore_cp_sched_nq_hi << RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT) | \ + (hysteresis_nrt_gui_active << RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT) | \ + (ignore_rtr_for_hi << RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT) | \ + (ignore_cp_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT) | \ + (ignore_vgt_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT) | \ + (ignore_sq_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT) | \ + (cp_rbbm_nrtrtr << RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT) | \ + (vgt_rbbm_nrtrtr << RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT) | \ + (sq_rbbm_nrtrtr << RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT) | \ + (clients_for_nrt_rtr_for_hi << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT) | \ + (clients_for_nrt_rtr << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT) | \ + (ignore_sx_rbbm_busy << RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT)) + +#define RBBM_DEBUG_GET_IGNORE_RTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_RTR_MASK) >> RBBM_DEBUG_IGNORE_RTR_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_WU(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_ISYNC(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_CP_SCHED_NQ_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK) >> RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT) +#define RBBM_DEBUG_GET_HYSTERESIS_NRT_GUI_ACTIVE(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK) >> RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_RTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_CP_RBBM_NRTRTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_VGT_RBBM_NRTRTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_SQ_RBBM_NRTRTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK) >> RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_CP_RBBM_NRTRTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_CP_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_GET_VGT_RBBM_NRTRTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_GET_SQ_RBBM_NRTRTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK) >> RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_GET_CLIENTS_FOR_NRT_RTR_FOR_HI(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK) >> RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_GET_CLIENTS_FOR_NRT_RTR(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK) >> RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT) +#define RBBM_DEBUG_GET_IGNORE_SX_RBBM_BUSY(rbbm_debug) \ + ((rbbm_debug & RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) >> RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT) + +#define RBBM_DEBUG_SET_IGNORE_RTR(rbbm_debug_reg, ignore_rtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_RTR_MASK) | (ignore_rtr << RBBM_DEBUG_IGNORE_RTR_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_WU(rbbm_debug_reg, ignore_cp_sched_wu) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_WU_MASK) | (ignore_cp_sched_wu << RBBM_DEBUG_IGNORE_CP_SCHED_WU_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_ISYNC(rbbm_debug_reg, ignore_cp_sched_isync) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_MASK) | (ignore_cp_sched_isync << RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_CP_SCHED_NQ_HI(rbbm_debug_reg, ignore_cp_sched_nq_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_MASK) | (ignore_cp_sched_nq_hi << RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SHIFT) +#define RBBM_DEBUG_SET_HYSTERESIS_NRT_GUI_ACTIVE(rbbm_debug_reg, hysteresis_nrt_gui_active) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_MASK) | (hysteresis_nrt_gui_active << RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_RTR_FOR_HI(rbbm_debug_reg, ignore_rtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_RTR_FOR_HI_MASK) | (ignore_rtr_for_hi << RBBM_DEBUG_IGNORE_RTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_CP_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_cp_rbbm_nrtrtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_cp_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_VGT_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_vgt_rbbm_nrtrtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_vgt_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_SQ_RBBM_NRTRTR_FOR_HI(rbbm_debug_reg, ignore_sq_rbbm_nrtrtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_MASK) | (ignore_sq_rbbm_nrtrtr_for_hi << RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_CP_RBBM_NRTRTR(rbbm_debug_reg, cp_rbbm_nrtrtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CP_RBBM_NRTRTR_MASK) | (cp_rbbm_nrtrtr << RBBM_DEBUG_CP_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_SET_VGT_RBBM_NRTRTR(rbbm_debug_reg, vgt_rbbm_nrtrtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_VGT_RBBM_NRTRTR_MASK) | (vgt_rbbm_nrtrtr << RBBM_DEBUG_VGT_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_SET_SQ_RBBM_NRTRTR(rbbm_debug_reg, sq_rbbm_nrtrtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_SQ_RBBM_NRTRTR_MASK) | (sq_rbbm_nrtrtr << RBBM_DEBUG_SQ_RBBM_NRTRTR_SHIFT) +#define RBBM_DEBUG_SET_CLIENTS_FOR_NRT_RTR_FOR_HI(rbbm_debug_reg, clients_for_nrt_rtr_for_hi) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_MASK) | (clients_for_nrt_rtr_for_hi << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SHIFT) +#define RBBM_DEBUG_SET_CLIENTS_FOR_NRT_RTR(rbbm_debug_reg, clients_for_nrt_rtr) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_MASK) | (clients_for_nrt_rtr << RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SHIFT) +#define RBBM_DEBUG_SET_IGNORE_SX_RBBM_BUSY(rbbm_debug_reg, ignore_sx_rbbm_busy) \ + rbbm_debug_reg = (rbbm_debug_reg & ~RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_MASK) | (ignore_sx_rbbm_busy << RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_debug_t { + unsigned int : 1; + unsigned int ignore_rtr : RBBM_DEBUG_IGNORE_RTR_SIZE; + unsigned int ignore_cp_sched_wu : RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE; + unsigned int ignore_cp_sched_isync : RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE; + unsigned int ignore_cp_sched_nq_hi : RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE; + unsigned int : 3; + unsigned int hysteresis_nrt_gui_active : RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE; + unsigned int : 4; + unsigned int ignore_rtr_for_hi : RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE; + unsigned int ignore_cp_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_vgt_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_sq_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int cp_rbbm_nrtrtr : RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE; + unsigned int vgt_rbbm_nrtrtr : RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE; + unsigned int sq_rbbm_nrtrtr : RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE; + unsigned int clients_for_nrt_rtr_for_hi : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE; + unsigned int clients_for_nrt_rtr : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE; + unsigned int : 6; + unsigned int ignore_sx_rbbm_busy : RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE; + } rbbm_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_debug_t { + unsigned int ignore_sx_rbbm_busy : RBBM_DEBUG_IGNORE_SX_RBBM_BUSY_SIZE; + unsigned int : 6; + unsigned int clients_for_nrt_rtr : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_SIZE; + unsigned int clients_for_nrt_rtr_for_hi : RBBM_DEBUG_CLIENTS_FOR_NRT_RTR_FOR_HI_SIZE; + unsigned int sq_rbbm_nrtrtr : RBBM_DEBUG_SQ_RBBM_NRTRTR_SIZE; + unsigned int vgt_rbbm_nrtrtr : RBBM_DEBUG_VGT_RBBM_NRTRTR_SIZE; + unsigned int cp_rbbm_nrtrtr : RBBM_DEBUG_CP_RBBM_NRTRTR_SIZE; + unsigned int ignore_sq_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_SQ_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_vgt_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_VGT_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_cp_rbbm_nrtrtr_for_hi : RBBM_DEBUG_IGNORE_CP_RBBM_NRTRTR_FOR_HI_SIZE; + unsigned int ignore_rtr_for_hi : RBBM_DEBUG_IGNORE_RTR_FOR_HI_SIZE; + unsigned int : 4; + unsigned int hysteresis_nrt_gui_active : RBBM_DEBUG_HYSTERESIS_NRT_GUI_ACTIVE_SIZE; + unsigned int : 3; + unsigned int ignore_cp_sched_nq_hi : RBBM_DEBUG_IGNORE_CP_SCHED_NQ_HI_SIZE; + unsigned int ignore_cp_sched_isync : RBBM_DEBUG_IGNORE_CP_SCHED_ISYNC_SIZE; + unsigned int ignore_cp_sched_wu : RBBM_DEBUG_IGNORE_CP_SCHED_WU_SIZE; + unsigned int ignore_rtr : RBBM_DEBUG_IGNORE_RTR_SIZE; + unsigned int : 1; + } rbbm_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_debug_t f; +} rbbm_debug_u; + + +/* + * RBBM_READ_ERROR struct + */ + +#define RBBM_READ_ERROR_READ_ADDRESS_SIZE 15 +#define RBBM_READ_ERROR_READ_REQUESTER_SIZE 1 +#define RBBM_READ_ERROR_READ_ERROR_SIZE 1 + +#define RBBM_READ_ERROR_READ_ADDRESS_SHIFT 2 +#define RBBM_READ_ERROR_READ_REQUESTER_SHIFT 30 +#define RBBM_READ_ERROR_READ_ERROR_SHIFT 31 + +#define RBBM_READ_ERROR_READ_ADDRESS_MASK 0x0001fffc +#define RBBM_READ_ERROR_READ_REQUESTER_MASK 0x40000000 +#define RBBM_READ_ERROR_READ_ERROR_MASK 0x80000000 + +#define RBBM_READ_ERROR_MASK \ + (RBBM_READ_ERROR_READ_ADDRESS_MASK | \ + RBBM_READ_ERROR_READ_REQUESTER_MASK | \ + RBBM_READ_ERROR_READ_ERROR_MASK) + +#define RBBM_READ_ERROR(read_address, read_requester, read_error) \ + ((read_address << RBBM_READ_ERROR_READ_ADDRESS_SHIFT) | \ + (read_requester << RBBM_READ_ERROR_READ_REQUESTER_SHIFT) | \ + (read_error << RBBM_READ_ERROR_READ_ERROR_SHIFT)) + +#define RBBM_READ_ERROR_GET_READ_ADDRESS(rbbm_read_error) \ + ((rbbm_read_error & RBBM_READ_ERROR_READ_ADDRESS_MASK) >> RBBM_READ_ERROR_READ_ADDRESS_SHIFT) +#define RBBM_READ_ERROR_GET_READ_REQUESTER(rbbm_read_error) \ + ((rbbm_read_error & RBBM_READ_ERROR_READ_REQUESTER_MASK) >> RBBM_READ_ERROR_READ_REQUESTER_SHIFT) +#define RBBM_READ_ERROR_GET_READ_ERROR(rbbm_read_error) \ + ((rbbm_read_error & RBBM_READ_ERROR_READ_ERROR_MASK) >> RBBM_READ_ERROR_READ_ERROR_SHIFT) + +#define RBBM_READ_ERROR_SET_READ_ADDRESS(rbbm_read_error_reg, read_address) \ + rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_ADDRESS_MASK) | (read_address << RBBM_READ_ERROR_READ_ADDRESS_SHIFT) +#define RBBM_READ_ERROR_SET_READ_REQUESTER(rbbm_read_error_reg, read_requester) \ + rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_REQUESTER_MASK) | (read_requester << RBBM_READ_ERROR_READ_REQUESTER_SHIFT) +#define RBBM_READ_ERROR_SET_READ_ERROR(rbbm_read_error_reg, read_error) \ + rbbm_read_error_reg = (rbbm_read_error_reg & ~RBBM_READ_ERROR_READ_ERROR_MASK) | (read_error << RBBM_READ_ERROR_READ_ERROR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_read_error_t { + unsigned int : 2; + unsigned int read_address : RBBM_READ_ERROR_READ_ADDRESS_SIZE; + unsigned int : 13; + unsigned int read_requester : RBBM_READ_ERROR_READ_REQUESTER_SIZE; + unsigned int read_error : RBBM_READ_ERROR_READ_ERROR_SIZE; + } rbbm_read_error_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_read_error_t { + unsigned int read_error : RBBM_READ_ERROR_READ_ERROR_SIZE; + unsigned int read_requester : RBBM_READ_ERROR_READ_REQUESTER_SIZE; + unsigned int : 13; + unsigned int read_address : RBBM_READ_ERROR_READ_ADDRESS_SIZE; + unsigned int : 2; + } rbbm_read_error_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_read_error_t f; +} rbbm_read_error_u; + + +/* + * RBBM_WAIT_IDLE_CLOCKS struct + */ + +#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE 8 + +#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT 0 + +#define RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK 0x000000ff + +#define RBBM_WAIT_IDLE_CLOCKS_MASK \ + (RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) + +#define RBBM_WAIT_IDLE_CLOCKS(wait_idle_clocks_nrt) \ + ((wait_idle_clocks_nrt << RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT)) + +#define RBBM_WAIT_IDLE_CLOCKS_GET_WAIT_IDLE_CLOCKS_NRT(rbbm_wait_idle_clocks) \ + ((rbbm_wait_idle_clocks & RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) >> RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT) + +#define RBBM_WAIT_IDLE_CLOCKS_SET_WAIT_IDLE_CLOCKS_NRT(rbbm_wait_idle_clocks_reg, wait_idle_clocks_nrt) \ + rbbm_wait_idle_clocks_reg = (rbbm_wait_idle_clocks_reg & ~RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_MASK) | (wait_idle_clocks_nrt << RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_wait_idle_clocks_t { + unsigned int wait_idle_clocks_nrt : RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE; + unsigned int : 24; + } rbbm_wait_idle_clocks_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_wait_idle_clocks_t { + unsigned int : 24; + unsigned int wait_idle_clocks_nrt : RBBM_WAIT_IDLE_CLOCKS_WAIT_IDLE_CLOCKS_NRT_SIZE; + } rbbm_wait_idle_clocks_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_wait_idle_clocks_t f; +} rbbm_wait_idle_clocks_u; + + +/* + * RBBM_INT_CNTL struct + */ + +#define RBBM_INT_CNTL_RDERR_INT_MASK_SIZE 1 +#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE 1 +#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE 1 + +#define RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT 0 +#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT 1 +#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT 19 + +#define RBBM_INT_CNTL_RDERR_INT_MASK_MASK 0x00000001 +#define RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK 0x00000002 +#define RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK 0x00080000 + +#define RBBM_INT_CNTL_MASK \ + (RBBM_INT_CNTL_RDERR_INT_MASK_MASK | \ + RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK | \ + RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) + +#define RBBM_INT_CNTL(rderr_int_mask, display_update_int_mask, gui_idle_int_mask) \ + ((rderr_int_mask << RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT) | \ + (display_update_int_mask << RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT) | \ + (gui_idle_int_mask << RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT)) + +#define RBBM_INT_CNTL_GET_RDERR_INT_MASK(rbbm_int_cntl) \ + ((rbbm_int_cntl & RBBM_INT_CNTL_RDERR_INT_MASK_MASK) >> RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT) +#define RBBM_INT_CNTL_GET_DISPLAY_UPDATE_INT_MASK(rbbm_int_cntl) \ + ((rbbm_int_cntl & RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK) >> RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT) +#define RBBM_INT_CNTL_GET_GUI_IDLE_INT_MASK(rbbm_int_cntl) \ + ((rbbm_int_cntl & RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) >> RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT) + +#define RBBM_INT_CNTL_SET_RDERR_INT_MASK(rbbm_int_cntl_reg, rderr_int_mask) \ + rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_RDERR_INT_MASK_MASK) | (rderr_int_mask << RBBM_INT_CNTL_RDERR_INT_MASK_SHIFT) +#define RBBM_INT_CNTL_SET_DISPLAY_UPDATE_INT_MASK(rbbm_int_cntl_reg, display_update_int_mask) \ + rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_MASK) | (display_update_int_mask << RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SHIFT) +#define RBBM_INT_CNTL_SET_GUI_IDLE_INT_MASK(rbbm_int_cntl_reg, gui_idle_int_mask) \ + rbbm_int_cntl_reg = (rbbm_int_cntl_reg & ~RBBM_INT_CNTL_GUI_IDLE_INT_MASK_MASK) | (gui_idle_int_mask << RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_int_cntl_t { + unsigned int rderr_int_mask : RBBM_INT_CNTL_RDERR_INT_MASK_SIZE; + unsigned int display_update_int_mask : RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE; + unsigned int : 17; + unsigned int gui_idle_int_mask : RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE; + unsigned int : 12; + } rbbm_int_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_int_cntl_t { + unsigned int : 12; + unsigned int gui_idle_int_mask : RBBM_INT_CNTL_GUI_IDLE_INT_MASK_SIZE; + unsigned int : 17; + unsigned int display_update_int_mask : RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK_SIZE; + unsigned int rderr_int_mask : RBBM_INT_CNTL_RDERR_INT_MASK_SIZE; + } rbbm_int_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_int_cntl_t f; +} rbbm_int_cntl_u; + + +/* + * RBBM_INT_STATUS struct + */ + +#define RBBM_INT_STATUS_RDERR_INT_STAT_SIZE 1 +#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE 1 +#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE 1 + +#define RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT 0 +#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT 1 +#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT 19 + +#define RBBM_INT_STATUS_RDERR_INT_STAT_MASK 0x00000001 +#define RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK 0x00000002 +#define RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK 0x00080000 + +#define RBBM_INT_STATUS_MASK \ + (RBBM_INT_STATUS_RDERR_INT_STAT_MASK | \ + RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK | \ + RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) + +#define RBBM_INT_STATUS(rderr_int_stat, display_update_int_stat, gui_idle_int_stat) \ + ((rderr_int_stat << RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT) | \ + (display_update_int_stat << RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT) | \ + (gui_idle_int_stat << RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT)) + +#define RBBM_INT_STATUS_GET_RDERR_INT_STAT(rbbm_int_status) \ + ((rbbm_int_status & RBBM_INT_STATUS_RDERR_INT_STAT_MASK) >> RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT) +#define RBBM_INT_STATUS_GET_DISPLAY_UPDATE_INT_STAT(rbbm_int_status) \ + ((rbbm_int_status & RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK) >> RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT) +#define RBBM_INT_STATUS_GET_GUI_IDLE_INT_STAT(rbbm_int_status) \ + ((rbbm_int_status & RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) >> RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT) + +#define RBBM_INT_STATUS_SET_RDERR_INT_STAT(rbbm_int_status_reg, rderr_int_stat) \ + rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_RDERR_INT_STAT_MASK) | (rderr_int_stat << RBBM_INT_STATUS_RDERR_INT_STAT_SHIFT) +#define RBBM_INT_STATUS_SET_DISPLAY_UPDATE_INT_STAT(rbbm_int_status_reg, display_update_int_stat) \ + rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_MASK) | (display_update_int_stat << RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SHIFT) +#define RBBM_INT_STATUS_SET_GUI_IDLE_INT_STAT(rbbm_int_status_reg, gui_idle_int_stat) \ + rbbm_int_status_reg = (rbbm_int_status_reg & ~RBBM_INT_STATUS_GUI_IDLE_INT_STAT_MASK) | (gui_idle_int_stat << RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_int_status_t { + unsigned int rderr_int_stat : RBBM_INT_STATUS_RDERR_INT_STAT_SIZE; + unsigned int display_update_int_stat : RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE; + unsigned int : 17; + unsigned int gui_idle_int_stat : RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE; + unsigned int : 12; + } rbbm_int_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_int_status_t { + unsigned int : 12; + unsigned int gui_idle_int_stat : RBBM_INT_STATUS_GUI_IDLE_INT_STAT_SIZE; + unsigned int : 17; + unsigned int display_update_int_stat : RBBM_INT_STATUS_DISPLAY_UPDATE_INT_STAT_SIZE; + unsigned int rderr_int_stat : RBBM_INT_STATUS_RDERR_INT_STAT_SIZE; + } rbbm_int_status_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_int_status_t f; +} rbbm_int_status_u; + + +/* + * RBBM_INT_ACK struct + */ + +#define RBBM_INT_ACK_RDERR_INT_ACK_SIZE 1 +#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE 1 +#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE 1 + +#define RBBM_INT_ACK_RDERR_INT_ACK_SHIFT 0 +#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT 1 +#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT 19 + +#define RBBM_INT_ACK_RDERR_INT_ACK_MASK 0x00000001 +#define RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK 0x00000002 +#define RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK 0x00080000 + +#define RBBM_INT_ACK_MASK \ + (RBBM_INT_ACK_RDERR_INT_ACK_MASK | \ + RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK | \ + RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) + +#define RBBM_INT_ACK(rderr_int_ack, display_update_int_ack, gui_idle_int_ack) \ + ((rderr_int_ack << RBBM_INT_ACK_RDERR_INT_ACK_SHIFT) | \ + (display_update_int_ack << RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT) | \ + (gui_idle_int_ack << RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT)) + +#define RBBM_INT_ACK_GET_RDERR_INT_ACK(rbbm_int_ack) \ + ((rbbm_int_ack & RBBM_INT_ACK_RDERR_INT_ACK_MASK) >> RBBM_INT_ACK_RDERR_INT_ACK_SHIFT) +#define RBBM_INT_ACK_GET_DISPLAY_UPDATE_INT_ACK(rbbm_int_ack) \ + ((rbbm_int_ack & RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK) >> RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT) +#define RBBM_INT_ACK_GET_GUI_IDLE_INT_ACK(rbbm_int_ack) \ + ((rbbm_int_ack & RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) >> RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT) + +#define RBBM_INT_ACK_SET_RDERR_INT_ACK(rbbm_int_ack_reg, rderr_int_ack) \ + rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_RDERR_INT_ACK_MASK) | (rderr_int_ack << RBBM_INT_ACK_RDERR_INT_ACK_SHIFT) +#define RBBM_INT_ACK_SET_DISPLAY_UPDATE_INT_ACK(rbbm_int_ack_reg, display_update_int_ack) \ + rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_MASK) | (display_update_int_ack << RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SHIFT) +#define RBBM_INT_ACK_SET_GUI_IDLE_INT_ACK(rbbm_int_ack_reg, gui_idle_int_ack) \ + rbbm_int_ack_reg = (rbbm_int_ack_reg & ~RBBM_INT_ACK_GUI_IDLE_INT_ACK_MASK) | (gui_idle_int_ack << RBBM_INT_ACK_GUI_IDLE_INT_ACK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_int_ack_t { + unsigned int rderr_int_ack : RBBM_INT_ACK_RDERR_INT_ACK_SIZE; + unsigned int display_update_int_ack : RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE; + unsigned int : 17; + unsigned int gui_idle_int_ack : RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE; + unsigned int : 12; + } rbbm_int_ack_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_int_ack_t { + unsigned int : 12; + unsigned int gui_idle_int_ack : RBBM_INT_ACK_GUI_IDLE_INT_ACK_SIZE; + unsigned int : 17; + unsigned int display_update_int_ack : RBBM_INT_ACK_DISPLAY_UPDATE_INT_ACK_SIZE; + unsigned int rderr_int_ack : RBBM_INT_ACK_RDERR_INT_ACK_SIZE; + } rbbm_int_ack_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_int_ack_t f; +} rbbm_int_ack_u; + + +/* + * MASTER_INT_SIGNAL struct + */ + +#define MASTER_INT_SIGNAL_MH_INT_STAT_SIZE 1 +#define MASTER_INT_SIGNAL_SQ_INT_STAT_SIZE 1 +#define MASTER_INT_SIGNAL_CP_INT_STAT_SIZE 1 +#define MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE 1 + +#define MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT 5 +#define MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT 26 +#define MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT 30 +#define MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT 31 + +#define MASTER_INT_SIGNAL_MH_INT_STAT_MASK 0x00000020 +#define MASTER_INT_SIGNAL_SQ_INT_STAT_MASK 0x04000000 +#define MASTER_INT_SIGNAL_CP_INT_STAT_MASK 0x40000000 +#define MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK 0x80000000 + +#define MASTER_INT_SIGNAL_MASK \ + (MASTER_INT_SIGNAL_MH_INT_STAT_MASK | \ + MASTER_INT_SIGNAL_SQ_INT_STAT_MASK | \ + MASTER_INT_SIGNAL_CP_INT_STAT_MASK | \ + MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) + +#define MASTER_INT_SIGNAL(mh_int_stat, sq_int_stat, cp_int_stat, rbbm_int_stat) \ + ((mh_int_stat << MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT) | \ + (sq_int_stat << MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT) | \ + (cp_int_stat << MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT) | \ + (rbbm_int_stat << MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT)) + +#define MASTER_INT_SIGNAL_GET_MH_INT_STAT(master_int_signal) \ + ((master_int_signal & MASTER_INT_SIGNAL_MH_INT_STAT_MASK) >> MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_GET_SQ_INT_STAT(master_int_signal) \ + ((master_int_signal & MASTER_INT_SIGNAL_SQ_INT_STAT_MASK) >> MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_GET_CP_INT_STAT(master_int_signal) \ + ((master_int_signal & MASTER_INT_SIGNAL_CP_INT_STAT_MASK) >> MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_GET_RBBM_INT_STAT(master_int_signal) \ + ((master_int_signal & MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) >> MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT) + +#define MASTER_INT_SIGNAL_SET_MH_INT_STAT(master_int_signal_reg, mh_int_stat) \ + master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_MH_INT_STAT_MASK) | (mh_int_stat << MASTER_INT_SIGNAL_MH_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_SET_SQ_INT_STAT(master_int_signal_reg, sq_int_stat) \ + master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_SQ_INT_STAT_MASK) | (sq_int_stat << MASTER_INT_SIGNAL_SQ_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_SET_CP_INT_STAT(master_int_signal_reg, cp_int_stat) \ + master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_CP_INT_STAT_MASK) | (cp_int_stat << MASTER_INT_SIGNAL_CP_INT_STAT_SHIFT) +#define MASTER_INT_SIGNAL_SET_RBBM_INT_STAT(master_int_signal_reg, rbbm_int_stat) \ + master_int_signal_reg = (master_int_signal_reg & ~MASTER_INT_SIGNAL_RBBM_INT_STAT_MASK) | (rbbm_int_stat << MASTER_INT_SIGNAL_RBBM_INT_STAT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _master_int_signal_t { + unsigned int : 5; + unsigned int mh_int_stat : MASTER_INT_SIGNAL_MH_INT_STAT_SIZE; + unsigned int : 20; + unsigned int sq_int_stat : MASTER_INT_SIGNAL_SQ_INT_STAT_SIZE; + unsigned int : 3; + unsigned int cp_int_stat : MASTER_INT_SIGNAL_CP_INT_STAT_SIZE; + unsigned int rbbm_int_stat : MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE; + } master_int_signal_t; + +#else // !BIGENDIAN_OS + + typedef struct _master_int_signal_t { + unsigned int rbbm_int_stat : MASTER_INT_SIGNAL_RBBM_INT_STAT_SIZE; + unsigned int cp_int_stat : MASTER_INT_SIGNAL_CP_INT_STAT_SIZE; + unsigned int : 3; + unsigned int sq_int_stat : MASTER_INT_SIGNAL_SQ_INT_STAT_SIZE; + unsigned int : 20; + unsigned int mh_int_stat : MASTER_INT_SIGNAL_MH_INT_STAT_SIZE; + unsigned int : 5; + } master_int_signal_t; + +#endif + +typedef union { + unsigned int val : 32; + master_int_signal_t f; +} master_int_signal_u; + + +/* + * RBBM_PERFCOUNTER1_SELECT struct + */ + +#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE 6 + +#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT 0 + +#define RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK 0x0000003f + +#define RBBM_PERFCOUNTER1_SELECT_MASK \ + (RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) + +#define RBBM_PERFCOUNTER1_SELECT(perf_count1_sel) \ + ((perf_count1_sel << RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT)) + +#define RBBM_PERFCOUNTER1_SELECT_GET_PERF_COUNT1_SEL(rbbm_perfcounter1_select) \ + ((rbbm_perfcounter1_select & RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) >> RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT) + +#define RBBM_PERFCOUNTER1_SELECT_SET_PERF_COUNT1_SEL(rbbm_perfcounter1_select_reg, perf_count1_sel) \ + rbbm_perfcounter1_select_reg = (rbbm_perfcounter1_select_reg & ~RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_MASK) | (perf_count1_sel << RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_select_t { + unsigned int perf_count1_sel : RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE; + unsigned int : 26; + } rbbm_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_select_t { + unsigned int : 26; + unsigned int perf_count1_sel : RBBM_PERFCOUNTER1_SELECT_PERF_COUNT1_SEL_SIZE; + } rbbm_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_perfcounter1_select_t f; +} rbbm_perfcounter1_select_u; + + +/* + * RBBM_PERFCOUNTER1_LO struct + */ + +#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE 32 + +#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT 0 + +#define RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK 0xffffffff + +#define RBBM_PERFCOUNTER1_LO_MASK \ + (RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) + +#define RBBM_PERFCOUNTER1_LO(perf_count1_lo) \ + ((perf_count1_lo << RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT)) + +#define RBBM_PERFCOUNTER1_LO_GET_PERF_COUNT1_LO(rbbm_perfcounter1_lo) \ + ((rbbm_perfcounter1_lo & RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) >> RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT) + +#define RBBM_PERFCOUNTER1_LO_SET_PERF_COUNT1_LO(rbbm_perfcounter1_lo_reg, perf_count1_lo) \ + rbbm_perfcounter1_lo_reg = (rbbm_perfcounter1_lo_reg & ~RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_MASK) | (perf_count1_lo << RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_lo_t { + unsigned int perf_count1_lo : RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE; + } rbbm_perfcounter1_lo_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_lo_t { + unsigned int perf_count1_lo : RBBM_PERFCOUNTER1_LO_PERF_COUNT1_LO_SIZE; + } rbbm_perfcounter1_lo_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_perfcounter1_lo_t f; +} rbbm_perfcounter1_lo_u; + + +/* + * RBBM_PERFCOUNTER1_HI struct + */ + +#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE 16 + +#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT 0 + +#define RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK 0x0000ffff + +#define RBBM_PERFCOUNTER1_HI_MASK \ + (RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) + +#define RBBM_PERFCOUNTER1_HI(perf_count1_hi) \ + ((perf_count1_hi << RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT)) + +#define RBBM_PERFCOUNTER1_HI_GET_PERF_COUNT1_HI(rbbm_perfcounter1_hi) \ + ((rbbm_perfcounter1_hi & RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) >> RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT) + +#define RBBM_PERFCOUNTER1_HI_SET_PERF_COUNT1_HI(rbbm_perfcounter1_hi_reg, perf_count1_hi) \ + rbbm_perfcounter1_hi_reg = (rbbm_perfcounter1_hi_reg & ~RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_MASK) | (perf_count1_hi << RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_hi_t { + unsigned int perf_count1_hi : RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE; + unsigned int : 16; + } rbbm_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _rbbm_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_count1_hi : RBBM_PERFCOUNTER1_HI_PERF_COUNT1_HI_SIZE; + } rbbm_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + rbbm_perfcounter1_hi_t f; +} rbbm_perfcounter1_hi_u; + + +#endif + + +#if !defined (_MH_FIDDLE_H) +#define _MH_FIDDLE_H + +/***************************************************************************************************************** + * + * mh_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * MH_ARBITER_CONFIG struct + */ + +#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE 6 +#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE 1 +#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE 1 +#define MH_ARBITER_CONFIG_PAGE_SIZE_SIZE 3 +#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE 6 +#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE 1 +#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SIZE 1 + +#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT 0 +#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT 6 +#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT 7 +#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT 8 +#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT 9 +#define MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT 10 +#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT 13 +#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT 14 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT 15 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT 16 +#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT 22 +#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT 23 +#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT 24 +#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT 25 +#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT 26 + +#define MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK 0x0000003f +#define MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK 0x00000040 +#define MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK 0x00000080 +#define MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK 0x00000100 +#define MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK 0x00000200 +#define MH_ARBITER_CONFIG_PAGE_SIZE_MASK 0x00001c00 +#define MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00002000 +#define MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK 0x00004000 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK 0x00008000 +#define MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK 0x003f0000 +#define MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK 0x00400000 +#define MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK 0x00800000 +#define MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK 0x01000000 +#define MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK 0x02000000 +#define MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK 0x04000000 + +#define MH_ARBITER_CONFIG_MASK \ + (MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK | \ + MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK | \ + MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK | \ + MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK | \ + MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK | \ + MH_ARBITER_CONFIG_PAGE_SIZE_MASK | \ + MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK | \ + MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK | \ + MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK | \ + MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK | \ + MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK | \ + MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK | \ + MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK | \ + MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK | \ + MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK) + +#define MH_ARBITER_CONFIG(same_page_limit, same_page_granularity, l1_arb_enable, l1_arb_hold_enable, l2_arb_control, page_size, tc_reorder_enable, tc_arb_hold_enable, in_flight_limit_enable, in_flight_limit, cp_clnt_enable, vgt_clnt_enable, tc_clnt_enable, rb_clnt_enable, pa_clnt_enable) \ + ((same_page_limit << MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT) | \ + (same_page_granularity << MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT) | \ + (l1_arb_enable << MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT) | \ + (l1_arb_hold_enable << MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT) | \ + (l2_arb_control << MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT) | \ + (page_size << MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT) | \ + (tc_reorder_enable << MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) | \ + (tc_arb_hold_enable << MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT) | \ + (in_flight_limit_enable << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT) | \ + (in_flight_limit << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT) | \ + (cp_clnt_enable << MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT) | \ + (vgt_clnt_enable << MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT) | \ + (tc_clnt_enable << MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT) | \ + (rb_clnt_enable << MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT) | \ + (pa_clnt_enable << MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT)) + +#define MH_ARBITER_CONFIG_GET_SAME_PAGE_LIMIT(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK) >> MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT) +#define MH_ARBITER_CONFIG_GET_SAME_PAGE_GRANULARITY(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK) >> MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT) +#define MH_ARBITER_CONFIG_GET_L1_ARB_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK) >> MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_L1_ARB_HOLD_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK) >> MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_L2_ARB_CONTROL(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK) >> MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT) +#define MH_ARBITER_CONFIG_GET_PAGE_SIZE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_PAGE_SIZE_MASK) >> MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT) +#define MH_ARBITER_CONFIG_GET_TC_REORDER_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_TC_ARB_HOLD_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_IN_FLIGHT_LIMIT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK) >> MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_IN_FLIGHT_LIMIT(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK) >> MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT) +#define MH_ARBITER_CONFIG_GET_CP_CLNT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_VGT_CLNT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_TC_CLNT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_RB_CLNT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_GET_PA_CLNT_ENABLE(mh_arbiter_config) \ + ((mh_arbiter_config & MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK) >> MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT) + +#define MH_ARBITER_CONFIG_SET_SAME_PAGE_LIMIT(mh_arbiter_config_reg, same_page_limit) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_MASK) | (same_page_limit << MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SHIFT) +#define MH_ARBITER_CONFIG_SET_SAME_PAGE_GRANULARITY(mh_arbiter_config_reg, same_page_granularity) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_MASK) | (same_page_granularity << MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SHIFT) +#define MH_ARBITER_CONFIG_SET_L1_ARB_ENABLE(mh_arbiter_config_reg, l1_arb_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L1_ARB_ENABLE_MASK) | (l1_arb_enable << MH_ARBITER_CONFIG_L1_ARB_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_L1_ARB_HOLD_ENABLE(mh_arbiter_config_reg, l1_arb_hold_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_MASK) | (l1_arb_hold_enable << MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_L2_ARB_CONTROL(mh_arbiter_config_reg, l2_arb_control) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_L2_ARB_CONTROL_MASK) | (l2_arb_control << MH_ARBITER_CONFIG_L2_ARB_CONTROL_SHIFT) +#define MH_ARBITER_CONFIG_SET_PAGE_SIZE(mh_arbiter_config_reg, page_size) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_PAGE_SIZE_MASK) | (page_size << MH_ARBITER_CONFIG_PAGE_SIZE_SHIFT) +#define MH_ARBITER_CONFIG_SET_TC_REORDER_ENABLE(mh_arbiter_config_reg, tc_reorder_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) | (tc_reorder_enable << MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_TC_ARB_HOLD_ENABLE(mh_arbiter_config_reg, tc_arb_hold_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_MASK) | (tc_arb_hold_enable << MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_IN_FLIGHT_LIMIT_ENABLE(mh_arbiter_config_reg, in_flight_limit_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_MASK) | (in_flight_limit_enable << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_IN_FLIGHT_LIMIT(mh_arbiter_config_reg, in_flight_limit) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_MASK) | (in_flight_limit << MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SHIFT) +#define MH_ARBITER_CONFIG_SET_CP_CLNT_ENABLE(mh_arbiter_config_reg, cp_clnt_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_CP_CLNT_ENABLE_MASK) | (cp_clnt_enable << MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_VGT_CLNT_ENABLE(mh_arbiter_config_reg, vgt_clnt_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_MASK) | (vgt_clnt_enable << MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_TC_CLNT_ENABLE(mh_arbiter_config_reg, tc_clnt_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_TC_CLNT_ENABLE_MASK) | (tc_clnt_enable << MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_RB_CLNT_ENABLE(mh_arbiter_config_reg, rb_clnt_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_RB_CLNT_ENABLE_MASK) | (rb_clnt_enable << MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SHIFT) +#define MH_ARBITER_CONFIG_SET_PA_CLNT_ENABLE(mh_arbiter_config_reg, pa_clnt_enable) \ + mh_arbiter_config_reg = (mh_arbiter_config_reg & ~MH_ARBITER_CONFIG_PA_CLNT_ENABLE_MASK) | (pa_clnt_enable << MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_arbiter_config_t { + unsigned int same_page_limit : MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE; + unsigned int same_page_granularity : MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE; + unsigned int l1_arb_enable : MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE; + unsigned int l1_arb_hold_enable : MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE; + unsigned int l2_arb_control : MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE; + unsigned int page_size : MH_ARBITER_CONFIG_PAGE_SIZE_SIZE; + unsigned int tc_reorder_enable : MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE; + unsigned int tc_arb_hold_enable : MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE; + unsigned int in_flight_limit_enable : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE; + unsigned int in_flight_limit : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE; + unsigned int cp_clnt_enable : MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE; + unsigned int vgt_clnt_enable : MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE; + unsigned int tc_clnt_enable : MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE; + unsigned int rb_clnt_enable : MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE; + unsigned int pa_clnt_enable : MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SIZE; + unsigned int : 5; + } mh_arbiter_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_arbiter_config_t { + unsigned int : 5; + unsigned int pa_clnt_enable : MH_ARBITER_CONFIG_PA_CLNT_ENABLE_SIZE; + unsigned int rb_clnt_enable : MH_ARBITER_CONFIG_RB_CLNT_ENABLE_SIZE; + unsigned int tc_clnt_enable : MH_ARBITER_CONFIG_TC_CLNT_ENABLE_SIZE; + unsigned int vgt_clnt_enable : MH_ARBITER_CONFIG_VGT_CLNT_ENABLE_SIZE; + unsigned int cp_clnt_enable : MH_ARBITER_CONFIG_CP_CLNT_ENABLE_SIZE; + unsigned int in_flight_limit : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_SIZE; + unsigned int in_flight_limit_enable : MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE_SIZE; + unsigned int tc_arb_hold_enable : MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE_SIZE; + unsigned int tc_reorder_enable : MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE; + unsigned int page_size : MH_ARBITER_CONFIG_PAGE_SIZE_SIZE; + unsigned int l2_arb_control : MH_ARBITER_CONFIG_L2_ARB_CONTROL_SIZE; + unsigned int l1_arb_hold_enable : MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE_SIZE; + unsigned int l1_arb_enable : MH_ARBITER_CONFIG_L1_ARB_ENABLE_SIZE; + unsigned int same_page_granularity : MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY_SIZE; + unsigned int same_page_limit : MH_ARBITER_CONFIG_SAME_PAGE_LIMIT_SIZE; + } mh_arbiter_config_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_arbiter_config_t f; +} mh_arbiter_config_u; + + +/* + * MH_CLNT_AXI_ID_REUSE struct + */ + +#define MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE 3 +#define MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE 1 +#define MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE 3 +#define MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE 1 +#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3 +#define MH_CLNT_AXI_ID_REUSE_RESERVED3_SIZE 1 +#define MH_CLNT_AXI_ID_REUSE_PAw_ID_SIZE 3 + +#define MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT 0 +#define MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT 3 +#define MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT 4 +#define MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT 7 +#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 8 +#define MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT 11 +#define MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT 12 + +#define MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK 0x00000007 +#define MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK 0x00000008 +#define MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK 0x00000070 +#define MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK 0x00000080 +#define MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x00000700 +#define MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK 0x00000800 +#define MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK 0x00007000 + +#define MH_CLNT_AXI_ID_REUSE_MASK \ + (MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK | \ + MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK | \ + MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK | \ + MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK | \ + MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK | \ + MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK | \ + MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK) + +#define MH_CLNT_AXI_ID_REUSE(cpw_id, reserved1, rbw_id, reserved2, mmur_id, reserved3, paw_id) \ + ((cpw_id << MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT) | \ + (reserved1 << MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT) | \ + (rbw_id << MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT) | \ + (reserved2 << MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT) | \ + (mmur_id << MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) | \ + (reserved3 << MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT) | \ + (paw_id << MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT)) + +#define MH_CLNT_AXI_ID_REUSE_GET_CPw_ID(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED1(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_RBw_ID(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED2(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_MMUr_ID(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_RESERVED3(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK) >> MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_GET_PAw_ID(mh_clnt_axi_id_reuse) \ + ((mh_clnt_axi_id_reuse & MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK) >> MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT) + +#define MH_CLNT_AXI_ID_REUSE_SET_CPw_ID(mh_clnt_axi_id_reuse_reg, cpw_id) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_CPw_ID_MASK) | (cpw_id << MH_CLNT_AXI_ID_REUSE_CPw_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED1(mh_clnt_axi_id_reuse_reg, reserved1) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED1_MASK) | (reserved1 << MH_CLNT_AXI_ID_REUSE_RESERVED1_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_RBw_ID(mh_clnt_axi_id_reuse_reg, rbw_id) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RBw_ID_MASK) | (rbw_id << MH_CLNT_AXI_ID_REUSE_RBw_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED2(mh_clnt_axi_id_reuse_reg, reserved2) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED2_MASK) | (reserved2 << MH_CLNT_AXI_ID_REUSE_RESERVED2_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_MMUr_ID(mh_clnt_axi_id_reuse_reg, mmur_id) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mmur_id << MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_RESERVED3(mh_clnt_axi_id_reuse_reg, reserved3) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_RESERVED3_MASK) | (reserved3 << MH_CLNT_AXI_ID_REUSE_RESERVED3_SHIFT) +#define MH_CLNT_AXI_ID_REUSE_SET_PAw_ID(mh_clnt_axi_id_reuse_reg, paw_id) \ + mh_clnt_axi_id_reuse_reg = (mh_clnt_axi_id_reuse_reg & ~MH_CLNT_AXI_ID_REUSE_PAw_ID_MASK) | (paw_id << MH_CLNT_AXI_ID_REUSE_PAw_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_clnt_axi_id_reuse_t { + unsigned int cpw_id : MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE; + unsigned int reserved1 : MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE; + unsigned int rbw_id : MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE; + unsigned int reserved2 : MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE; + unsigned int mmur_id : MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int reserved3 : MH_CLNT_AXI_ID_REUSE_RESERVED3_SIZE; + unsigned int paw_id : MH_CLNT_AXI_ID_REUSE_PAw_ID_SIZE; + unsigned int : 17; + } mh_clnt_axi_id_reuse_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_clnt_axi_id_reuse_t { + unsigned int : 17; + unsigned int paw_id : MH_CLNT_AXI_ID_REUSE_PAw_ID_SIZE; + unsigned int reserved3 : MH_CLNT_AXI_ID_REUSE_RESERVED3_SIZE; + unsigned int mmur_id : MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int reserved2 : MH_CLNT_AXI_ID_REUSE_RESERVED2_SIZE; + unsigned int rbw_id : MH_CLNT_AXI_ID_REUSE_RBw_ID_SIZE; + unsigned int reserved1 : MH_CLNT_AXI_ID_REUSE_RESERVED1_SIZE; + unsigned int cpw_id : MH_CLNT_AXI_ID_REUSE_CPw_ID_SIZE; + } mh_clnt_axi_id_reuse_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_clnt_axi_id_reuse_t f; +} mh_clnt_axi_id_reuse_u; + + +/* + * MH_INTERRUPT_MASK struct + */ + +#define MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE 1 +#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE 1 +#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE 1 + +#define MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT 0 +#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT 1 +#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT 2 + +#define MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK 0x00000001 +#define MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK 0x00000002 +#define MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK 0x00000004 + +#define MH_INTERRUPT_MASK_MASK \ + (MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK | \ + MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK | \ + MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) + +#define MH_INTERRUPT_MASK(axi_read_error, axi_write_error, mmu_page_fault) \ + ((axi_read_error << MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT) | \ + (axi_write_error << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT) | \ + (mmu_page_fault << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT)) + +#define MH_INTERRUPT_MASK_GET_AXI_READ_ERROR(mh_interrupt_mask) \ + ((mh_interrupt_mask & MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_MASK_GET_AXI_WRITE_ERROR(mh_interrupt_mask) \ + ((mh_interrupt_mask & MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_MASK_GET_MMU_PAGE_FAULT(mh_interrupt_mask) \ + ((mh_interrupt_mask & MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT) + +#define MH_INTERRUPT_MASK_SET_AXI_READ_ERROR(mh_interrupt_mask_reg, axi_read_error) \ + mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_MASK_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_MASK_SET_AXI_WRITE_ERROR(mh_interrupt_mask_reg, axi_write_error) \ + mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_MASK_SET_MMU_PAGE_FAULT(mh_interrupt_mask_reg, mmu_page_fault) \ + mh_interrupt_mask_reg = (mh_interrupt_mask_reg & ~MH_INTERRUPT_MASK_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_interrupt_mask_t { + unsigned int axi_read_error : MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE; + unsigned int mmu_page_fault : MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE; + unsigned int : 29; + } mh_interrupt_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_interrupt_mask_t { + unsigned int : 29; + unsigned int mmu_page_fault : MH_INTERRUPT_MASK_MMU_PAGE_FAULT_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_MASK_AXI_WRITE_ERROR_SIZE; + unsigned int axi_read_error : MH_INTERRUPT_MASK_AXI_READ_ERROR_SIZE; + } mh_interrupt_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_interrupt_mask_t f; +} mh_interrupt_mask_u; + + +/* + * MH_INTERRUPT_STATUS struct + */ + +#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE 1 +#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE 1 +#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE 1 + +#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT 0 +#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT 1 +#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT 2 + +#define MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK 0x00000001 +#define MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK 0x00000002 +#define MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK 0x00000004 + +#define MH_INTERRUPT_STATUS_MASK \ + (MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK | \ + MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK | \ + MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) + +#define MH_INTERRUPT_STATUS(axi_read_error, axi_write_error, mmu_page_fault) \ + ((axi_read_error << MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT) | \ + (axi_write_error << MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT) | \ + (mmu_page_fault << MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT)) + +#define MH_INTERRUPT_STATUS_GET_AXI_READ_ERROR(mh_interrupt_status) \ + ((mh_interrupt_status & MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_STATUS_GET_AXI_WRITE_ERROR(mh_interrupt_status) \ + ((mh_interrupt_status & MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_STATUS_GET_MMU_PAGE_FAULT(mh_interrupt_status) \ + ((mh_interrupt_status & MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT) + +#define MH_INTERRUPT_STATUS_SET_AXI_READ_ERROR(mh_interrupt_status_reg, axi_read_error) \ + mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_STATUS_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_STATUS_SET_AXI_WRITE_ERROR(mh_interrupt_status_reg, axi_write_error) \ + mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_STATUS_SET_MMU_PAGE_FAULT(mh_interrupt_status_reg, mmu_page_fault) \ + mh_interrupt_status_reg = (mh_interrupt_status_reg & ~MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_interrupt_status_t { + unsigned int axi_read_error : MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE; + unsigned int mmu_page_fault : MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE; + unsigned int : 29; + } mh_interrupt_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_interrupt_status_t { + unsigned int : 29; + unsigned int mmu_page_fault : MH_INTERRUPT_STATUS_MMU_PAGE_FAULT_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_STATUS_AXI_WRITE_ERROR_SIZE; + unsigned int axi_read_error : MH_INTERRUPT_STATUS_AXI_READ_ERROR_SIZE; + } mh_interrupt_status_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_interrupt_status_t f; +} mh_interrupt_status_u; + + +/* + * MH_INTERRUPT_CLEAR struct + */ + +#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE 1 +#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE 1 +#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE 1 + +#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT 0 +#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT 1 +#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT 2 + +#define MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK 0x00000001 +#define MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK 0x00000002 +#define MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK 0x00000004 + +#define MH_INTERRUPT_CLEAR_MASK \ + (MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK | \ + MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK | \ + MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) + +#define MH_INTERRUPT_CLEAR(axi_read_error, axi_write_error, mmu_page_fault) \ + ((axi_read_error << MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT) | \ + (axi_write_error << MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT) | \ + (mmu_page_fault << MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT)) + +#define MH_INTERRUPT_CLEAR_GET_AXI_READ_ERROR(mh_interrupt_clear) \ + ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK) >> MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_CLEAR_GET_AXI_WRITE_ERROR(mh_interrupt_clear) \ + ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK) >> MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_CLEAR_GET_MMU_PAGE_FAULT(mh_interrupt_clear) \ + ((mh_interrupt_clear & MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) >> MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT) + +#define MH_INTERRUPT_CLEAR_SET_AXI_READ_ERROR(mh_interrupt_clear_reg, axi_read_error) \ + mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_AXI_READ_ERROR_MASK) | (axi_read_error << MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SHIFT) +#define MH_INTERRUPT_CLEAR_SET_AXI_WRITE_ERROR(mh_interrupt_clear_reg, axi_write_error) \ + mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SHIFT) +#define MH_INTERRUPT_CLEAR_SET_MMU_PAGE_FAULT(mh_interrupt_clear_reg, mmu_page_fault) \ + mh_interrupt_clear_reg = (mh_interrupt_clear_reg & ~MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_MASK) | (mmu_page_fault << MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_interrupt_clear_t { + unsigned int axi_read_error : MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE; + unsigned int mmu_page_fault : MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE; + unsigned int : 29; + } mh_interrupt_clear_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_interrupt_clear_t { + unsigned int : 29; + unsigned int mmu_page_fault : MH_INTERRUPT_CLEAR_MMU_PAGE_FAULT_SIZE; + unsigned int axi_write_error : MH_INTERRUPT_CLEAR_AXI_WRITE_ERROR_SIZE; + unsigned int axi_read_error : MH_INTERRUPT_CLEAR_AXI_READ_ERROR_SIZE; + } mh_interrupt_clear_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_interrupt_clear_t f; +} mh_interrupt_clear_u; + + +/* + * MH_AXI_ERROR struct + */ + +#define MH_AXI_ERROR_AXI_READ_ID_SIZE 3 +#define MH_AXI_ERROR_AXI_READ_ERROR_SIZE 1 +#define MH_AXI_ERROR_AXI_WRITE_ID_SIZE 3 +#define MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE 1 + +#define MH_AXI_ERROR_AXI_READ_ID_SHIFT 0 +#define MH_AXI_ERROR_AXI_READ_ERROR_SHIFT 3 +#define MH_AXI_ERROR_AXI_WRITE_ID_SHIFT 4 +#define MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT 7 + +#define MH_AXI_ERROR_AXI_READ_ID_MASK 0x00000007 +#define MH_AXI_ERROR_AXI_READ_ERROR_MASK 0x00000008 +#define MH_AXI_ERROR_AXI_WRITE_ID_MASK 0x00000070 +#define MH_AXI_ERROR_AXI_WRITE_ERROR_MASK 0x00000080 + +#define MH_AXI_ERROR_MASK \ + (MH_AXI_ERROR_AXI_READ_ID_MASK | \ + MH_AXI_ERROR_AXI_READ_ERROR_MASK | \ + MH_AXI_ERROR_AXI_WRITE_ID_MASK | \ + MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) + +#define MH_AXI_ERROR(axi_read_id, axi_read_error, axi_write_id, axi_write_error) \ + ((axi_read_id << MH_AXI_ERROR_AXI_READ_ID_SHIFT) | \ + (axi_read_error << MH_AXI_ERROR_AXI_READ_ERROR_SHIFT) | \ + (axi_write_id << MH_AXI_ERROR_AXI_WRITE_ID_SHIFT) | \ + (axi_write_error << MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT)) + +#define MH_AXI_ERROR_GET_AXI_READ_ID(mh_axi_error) \ + ((mh_axi_error & MH_AXI_ERROR_AXI_READ_ID_MASK) >> MH_AXI_ERROR_AXI_READ_ID_SHIFT) +#define MH_AXI_ERROR_GET_AXI_READ_ERROR(mh_axi_error) \ + ((mh_axi_error & MH_AXI_ERROR_AXI_READ_ERROR_MASK) >> MH_AXI_ERROR_AXI_READ_ERROR_SHIFT) +#define MH_AXI_ERROR_GET_AXI_WRITE_ID(mh_axi_error) \ + ((mh_axi_error & MH_AXI_ERROR_AXI_WRITE_ID_MASK) >> MH_AXI_ERROR_AXI_WRITE_ID_SHIFT) +#define MH_AXI_ERROR_GET_AXI_WRITE_ERROR(mh_axi_error) \ + ((mh_axi_error & MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) >> MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT) + +#define MH_AXI_ERROR_SET_AXI_READ_ID(mh_axi_error_reg, axi_read_id) \ + mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_READ_ID_MASK) | (axi_read_id << MH_AXI_ERROR_AXI_READ_ID_SHIFT) +#define MH_AXI_ERROR_SET_AXI_READ_ERROR(mh_axi_error_reg, axi_read_error) \ + mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_READ_ERROR_MASK) | (axi_read_error << MH_AXI_ERROR_AXI_READ_ERROR_SHIFT) +#define MH_AXI_ERROR_SET_AXI_WRITE_ID(mh_axi_error_reg, axi_write_id) \ + mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_WRITE_ID_MASK) | (axi_write_id << MH_AXI_ERROR_AXI_WRITE_ID_SHIFT) +#define MH_AXI_ERROR_SET_AXI_WRITE_ERROR(mh_axi_error_reg, axi_write_error) \ + mh_axi_error_reg = (mh_axi_error_reg & ~MH_AXI_ERROR_AXI_WRITE_ERROR_MASK) | (axi_write_error << MH_AXI_ERROR_AXI_WRITE_ERROR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_axi_error_t { + unsigned int axi_read_id : MH_AXI_ERROR_AXI_READ_ID_SIZE; + unsigned int axi_read_error : MH_AXI_ERROR_AXI_READ_ERROR_SIZE; + unsigned int axi_write_id : MH_AXI_ERROR_AXI_WRITE_ID_SIZE; + unsigned int axi_write_error : MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE; + unsigned int : 24; + } mh_axi_error_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_axi_error_t { + unsigned int : 24; + unsigned int axi_write_error : MH_AXI_ERROR_AXI_WRITE_ERROR_SIZE; + unsigned int axi_write_id : MH_AXI_ERROR_AXI_WRITE_ID_SIZE; + unsigned int axi_read_error : MH_AXI_ERROR_AXI_READ_ERROR_SIZE; + unsigned int axi_read_id : MH_AXI_ERROR_AXI_READ_ID_SIZE; + } mh_axi_error_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_axi_error_t f; +} mh_axi_error_u; + + +/* + * MH_PERFCOUNTER0_SELECT struct + */ + +#define MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define MH_PERFCOUNTER0_SELECT_MASK \ + (MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define MH_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define MH_PERFCOUNTER0_SELECT_GET_PERF_SEL(mh_perfcounter0_select) \ + ((mh_perfcounter0_select & MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define MH_PERFCOUNTER0_SELECT_SET_PERF_SEL(mh_perfcounter0_select_reg, perf_sel) \ + mh_perfcounter0_select_reg = (mh_perfcounter0_select_reg & ~MH_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << MH_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter0_select_t { + unsigned int perf_sel : MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } mh_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : MH_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } mh_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter0_select_t f; +} mh_perfcounter0_select_u; + + +/* + * MH_PERFCOUNTER1_SELECT struct + */ + +#define MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8 + +#define MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0 + +#define MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff + +#define MH_PERFCOUNTER1_SELECT_MASK \ + (MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) + +#define MH_PERFCOUNTER1_SELECT(perf_sel) \ + ((perf_sel << MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)) + +#define MH_PERFCOUNTER1_SELECT_GET_PERF_SEL(mh_perfcounter1_select) \ + ((mh_perfcounter1_select & MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#define MH_PERFCOUNTER1_SELECT_SET_PERF_SEL(mh_perfcounter1_select_reg, perf_sel) \ + mh_perfcounter1_select_reg = (mh_perfcounter1_select_reg & ~MH_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << MH_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter1_select_t { + unsigned int perf_sel : MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } mh_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter1_select_t { + unsigned int : 24; + unsigned int perf_sel : MH_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + } mh_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter1_select_t f; +} mh_perfcounter1_select_u; + + +/* + * MH_PERFCOUNTER0_CONFIG struct + */ + +#define MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE 8 + +#define MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT 0 + +#define MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK 0x000000ff + +#define MH_PERFCOUNTER0_CONFIG_MASK \ + (MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) + +#define MH_PERFCOUNTER0_CONFIG(n_value) \ + ((n_value << MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT)) + +#define MH_PERFCOUNTER0_CONFIG_GET_N_VALUE(mh_perfcounter0_config) \ + ((mh_perfcounter0_config & MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) >> MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT) + +#define MH_PERFCOUNTER0_CONFIG_SET_N_VALUE(mh_perfcounter0_config_reg, n_value) \ + mh_perfcounter0_config_reg = (mh_perfcounter0_config_reg & ~MH_PERFCOUNTER0_CONFIG_N_VALUE_MASK) | (n_value << MH_PERFCOUNTER0_CONFIG_N_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter0_config_t { + unsigned int n_value : MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE; + unsigned int : 24; + } mh_perfcounter0_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter0_config_t { + unsigned int : 24; + unsigned int n_value : MH_PERFCOUNTER0_CONFIG_N_VALUE_SIZE; + } mh_perfcounter0_config_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter0_config_t f; +} mh_perfcounter0_config_u; + + +/* + * MH_PERFCOUNTER1_CONFIG struct + */ + +#define MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE 8 + +#define MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT 0 + +#define MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK 0x000000ff + +#define MH_PERFCOUNTER1_CONFIG_MASK \ + (MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) + +#define MH_PERFCOUNTER1_CONFIG(n_value) \ + ((n_value << MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT)) + +#define MH_PERFCOUNTER1_CONFIG_GET_N_VALUE(mh_perfcounter1_config) \ + ((mh_perfcounter1_config & MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) >> MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT) + +#define MH_PERFCOUNTER1_CONFIG_SET_N_VALUE(mh_perfcounter1_config_reg, n_value) \ + mh_perfcounter1_config_reg = (mh_perfcounter1_config_reg & ~MH_PERFCOUNTER1_CONFIG_N_VALUE_MASK) | (n_value << MH_PERFCOUNTER1_CONFIG_N_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter1_config_t { + unsigned int n_value : MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE; + unsigned int : 24; + } mh_perfcounter1_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter1_config_t { + unsigned int : 24; + unsigned int n_value : MH_PERFCOUNTER1_CONFIG_N_VALUE_SIZE; + } mh_perfcounter1_config_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter1_config_t f; +} mh_perfcounter1_config_u; + + +/* + * MH_PERFCOUNTER0_LOW struct + */ + +#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE 32 + +#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT 0 + +#define MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK 0xffffffff + +#define MH_PERFCOUNTER0_LOW_MASK \ + (MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) + +#define MH_PERFCOUNTER0_LOW(perf_counter_low) \ + ((perf_counter_low << MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT)) + +#define MH_PERFCOUNTER0_LOW_GET_PERF_COUNTER_LOW(mh_perfcounter0_low) \ + ((mh_perfcounter0_low & MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) >> MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT) + +#define MH_PERFCOUNTER0_LOW_SET_PERF_COUNTER_LOW(mh_perfcounter0_low_reg, perf_counter_low) \ + mh_perfcounter0_low_reg = (mh_perfcounter0_low_reg & ~MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_MASK) | (perf_counter_low << MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter0_low_t { + unsigned int perf_counter_low : MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE; + } mh_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter0_low_t { + unsigned int perf_counter_low : MH_PERFCOUNTER0_LOW_PERF_COUNTER_LOW_SIZE; + } mh_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter0_low_t f; +} mh_perfcounter0_low_u; + + +/* + * MH_PERFCOUNTER1_LOW struct + */ + +#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE 32 + +#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT 0 + +#define MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK 0xffffffff + +#define MH_PERFCOUNTER1_LOW_MASK \ + (MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) + +#define MH_PERFCOUNTER1_LOW(perf_counter_low) \ + ((perf_counter_low << MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT)) + +#define MH_PERFCOUNTER1_LOW_GET_PERF_COUNTER_LOW(mh_perfcounter1_low) \ + ((mh_perfcounter1_low & MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) >> MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT) + +#define MH_PERFCOUNTER1_LOW_SET_PERF_COUNTER_LOW(mh_perfcounter1_low_reg, perf_counter_low) \ + mh_perfcounter1_low_reg = (mh_perfcounter1_low_reg & ~MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_MASK) | (perf_counter_low << MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter1_low_t { + unsigned int perf_counter_low : MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE; + } mh_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter1_low_t { + unsigned int perf_counter_low : MH_PERFCOUNTER1_LOW_PERF_COUNTER_LOW_SIZE; + } mh_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter1_low_t f; +} mh_perfcounter1_low_u; + + +/* + * MH_PERFCOUNTER0_HI struct + */ + +#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE 16 + +#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT 0 + +#define MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK 0x0000ffff + +#define MH_PERFCOUNTER0_HI_MASK \ + (MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) + +#define MH_PERFCOUNTER0_HI(perf_counter_hi) \ + ((perf_counter_hi << MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT)) + +#define MH_PERFCOUNTER0_HI_GET_PERF_COUNTER_HI(mh_perfcounter0_hi) \ + ((mh_perfcounter0_hi & MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) >> MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT) + +#define MH_PERFCOUNTER0_HI_SET_PERF_COUNTER_HI(mh_perfcounter0_hi_reg, perf_counter_hi) \ + mh_perfcounter0_hi_reg = (mh_perfcounter0_hi_reg & ~MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_MASK) | (perf_counter_hi << MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter0_hi_t { + unsigned int perf_counter_hi : MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE; + unsigned int : 16; + } mh_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_counter_hi : MH_PERFCOUNTER0_HI_PERF_COUNTER_HI_SIZE; + } mh_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter0_hi_t f; +} mh_perfcounter0_hi_u; + + +/* + * MH_PERFCOUNTER1_HI struct + */ + +#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE 16 + +#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT 0 + +#define MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK 0x0000ffff + +#define MH_PERFCOUNTER1_HI_MASK \ + (MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) + +#define MH_PERFCOUNTER1_HI(perf_counter_hi) \ + ((perf_counter_hi << MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT)) + +#define MH_PERFCOUNTER1_HI_GET_PERF_COUNTER_HI(mh_perfcounter1_hi) \ + ((mh_perfcounter1_hi & MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) >> MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT) + +#define MH_PERFCOUNTER1_HI_SET_PERF_COUNTER_HI(mh_perfcounter1_hi_reg, perf_counter_hi) \ + mh_perfcounter1_hi_reg = (mh_perfcounter1_hi_reg & ~MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_MASK) | (perf_counter_hi << MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_perfcounter1_hi_t { + unsigned int perf_counter_hi : MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE; + unsigned int : 16; + } mh_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_counter_hi : MH_PERFCOUNTER1_HI_PERF_COUNTER_HI_SIZE; + } mh_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_perfcounter1_hi_t f; +} mh_perfcounter1_hi_u; + + +/* + * MH_DEBUG_CTRL struct + */ + +#define MH_DEBUG_CTRL_INDEX_SIZE 6 + +#define MH_DEBUG_CTRL_INDEX_SHIFT 0 + +#define MH_DEBUG_CTRL_INDEX_MASK 0x0000003f + +#define MH_DEBUG_CTRL_MASK \ + (MH_DEBUG_CTRL_INDEX_MASK) + +#define MH_DEBUG_CTRL(index) \ + ((index << MH_DEBUG_CTRL_INDEX_SHIFT)) + +#define MH_DEBUG_CTRL_GET_INDEX(mh_debug_ctrl) \ + ((mh_debug_ctrl & MH_DEBUG_CTRL_INDEX_MASK) >> MH_DEBUG_CTRL_INDEX_SHIFT) + +#define MH_DEBUG_CTRL_SET_INDEX(mh_debug_ctrl_reg, index) \ + mh_debug_ctrl_reg = (mh_debug_ctrl_reg & ~MH_DEBUG_CTRL_INDEX_MASK) | (index << MH_DEBUG_CTRL_INDEX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_ctrl_t { + unsigned int index : MH_DEBUG_CTRL_INDEX_SIZE; + unsigned int : 26; + } mh_debug_ctrl_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_ctrl_t { + unsigned int : 26; + unsigned int index : MH_DEBUG_CTRL_INDEX_SIZE; + } mh_debug_ctrl_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_ctrl_t f; +} mh_debug_ctrl_u; + + +/* + * MH_DEBUG_DATA struct + */ + +#define MH_DEBUG_DATA_DATA_SIZE 32 + +#define MH_DEBUG_DATA_DATA_SHIFT 0 + +#define MH_DEBUG_DATA_DATA_MASK 0xffffffff + +#define MH_DEBUG_DATA_MASK \ + (MH_DEBUG_DATA_DATA_MASK) + +#define MH_DEBUG_DATA(data) \ + ((data << MH_DEBUG_DATA_DATA_SHIFT)) + +#define MH_DEBUG_DATA_GET_DATA(mh_debug_data) \ + ((mh_debug_data & MH_DEBUG_DATA_DATA_MASK) >> MH_DEBUG_DATA_DATA_SHIFT) + +#define MH_DEBUG_DATA_SET_DATA(mh_debug_data_reg, data) \ + mh_debug_data_reg = (mh_debug_data_reg & ~MH_DEBUG_DATA_DATA_MASK) | (data << MH_DEBUG_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_data_t { + unsigned int data : MH_DEBUG_DATA_DATA_SIZE; + } mh_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_data_t { + unsigned int data : MH_DEBUG_DATA_DATA_SIZE; + } mh_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_data_t f; +} mh_debug_data_u; + + +/* + * MH_AXI_HALT_CONTROL struct + */ + +#define MH_AXI_HALT_CONTROL_AXI_HALT_SIZE 1 + +#define MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT 0 + +#define MH_AXI_HALT_CONTROL_AXI_HALT_MASK 0x00000001 + +#define MH_AXI_HALT_CONTROL_MASK \ + (MH_AXI_HALT_CONTROL_AXI_HALT_MASK) + +#define MH_AXI_HALT_CONTROL(axi_halt) \ + ((axi_halt << MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT)) + +#define MH_AXI_HALT_CONTROL_GET_AXI_HALT(mh_axi_halt_control) \ + ((mh_axi_halt_control & MH_AXI_HALT_CONTROL_AXI_HALT_MASK) >> MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT) + +#define MH_AXI_HALT_CONTROL_SET_AXI_HALT(mh_axi_halt_control_reg, axi_halt) \ + mh_axi_halt_control_reg = (mh_axi_halt_control_reg & ~MH_AXI_HALT_CONTROL_AXI_HALT_MASK) | (axi_halt << MH_AXI_HALT_CONTROL_AXI_HALT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_axi_halt_control_t { + unsigned int axi_halt : MH_AXI_HALT_CONTROL_AXI_HALT_SIZE; + unsigned int : 31; + } mh_axi_halt_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_axi_halt_control_t { + unsigned int : 31; + unsigned int axi_halt : MH_AXI_HALT_CONTROL_AXI_HALT_SIZE; + } mh_axi_halt_control_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_axi_halt_control_t f; +} mh_axi_halt_control_u; + + +/* + * MH_DEBUG_REG00 struct + */ + +#define MH_DEBUG_REG00_MH_BUSY_SIZE 1 +#define MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE 1 +#define MH_DEBUG_REG00_CP_REQUEST_SIZE 1 +#define MH_DEBUG_REG00_VGT_REQUEST_SIZE 1 +#define MH_DEBUG_REG00_TC_REQUEST_SIZE 1 +#define MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE 1 +#define MH_DEBUG_REG00_TC_CAM_FULL_SIZE 1 +#define MH_DEBUG_REG00_TCD_EMPTY_SIZE 1 +#define MH_DEBUG_REG00_TCD_FULL_SIZE 1 +#define MH_DEBUG_REG00_RB_REQUEST_SIZE 1 +#define MH_DEBUG_REG00_PA_REQUEST_SIZE 1 +#define MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE 1 +#define MH_DEBUG_REG00_ARQ_EMPTY_SIZE 1 +#define MH_DEBUG_REG00_ARQ_FULL_SIZE 1 +#define MH_DEBUG_REG00_WDB_EMPTY_SIZE 1 +#define MH_DEBUG_REG00_WDB_FULL_SIZE 1 +#define MH_DEBUG_REG00_AXI_AVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_AREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_ARVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_ARREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_WVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_WREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_RVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_RREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_BVALID_SIZE 1 +#define MH_DEBUG_REG00_AXI_BREADY_SIZE 1 +#define MH_DEBUG_REG00_AXI_HALT_REQ_SIZE 1 +#define MH_DEBUG_REG00_AXI_HALT_ACK_SIZE 1 +#define MH_DEBUG_REG00_AXI_RDY_ENA_SIZE 1 + +#define MH_DEBUG_REG00_MH_BUSY_SHIFT 0 +#define MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT 1 +#define MH_DEBUG_REG00_CP_REQUEST_SHIFT 2 +#define MH_DEBUG_REG00_VGT_REQUEST_SHIFT 3 +#define MH_DEBUG_REG00_TC_REQUEST_SHIFT 4 +#define MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT 5 +#define MH_DEBUG_REG00_TC_CAM_FULL_SHIFT 6 +#define MH_DEBUG_REG00_TCD_EMPTY_SHIFT 7 +#define MH_DEBUG_REG00_TCD_FULL_SHIFT 8 +#define MH_DEBUG_REG00_RB_REQUEST_SHIFT 9 +#define MH_DEBUG_REG00_PA_REQUEST_SHIFT 10 +#define MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT 11 +#define MH_DEBUG_REG00_ARQ_EMPTY_SHIFT 12 +#define MH_DEBUG_REG00_ARQ_FULL_SHIFT 13 +#define MH_DEBUG_REG00_WDB_EMPTY_SHIFT 14 +#define MH_DEBUG_REG00_WDB_FULL_SHIFT 15 +#define MH_DEBUG_REG00_AXI_AVALID_SHIFT 16 +#define MH_DEBUG_REG00_AXI_AREADY_SHIFT 17 +#define MH_DEBUG_REG00_AXI_ARVALID_SHIFT 18 +#define MH_DEBUG_REG00_AXI_ARREADY_SHIFT 19 +#define MH_DEBUG_REG00_AXI_WVALID_SHIFT 20 +#define MH_DEBUG_REG00_AXI_WREADY_SHIFT 21 +#define MH_DEBUG_REG00_AXI_RVALID_SHIFT 22 +#define MH_DEBUG_REG00_AXI_RREADY_SHIFT 23 +#define MH_DEBUG_REG00_AXI_BVALID_SHIFT 24 +#define MH_DEBUG_REG00_AXI_BREADY_SHIFT 25 +#define MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT 26 +#define MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT 27 +#define MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT 28 + +#define MH_DEBUG_REG00_MH_BUSY_MASK 0x00000001 +#define MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK 0x00000002 +#define MH_DEBUG_REG00_CP_REQUEST_MASK 0x00000004 +#define MH_DEBUG_REG00_VGT_REQUEST_MASK 0x00000008 +#define MH_DEBUG_REG00_TC_REQUEST_MASK 0x00000010 +#define MH_DEBUG_REG00_TC_CAM_EMPTY_MASK 0x00000020 +#define MH_DEBUG_REG00_TC_CAM_FULL_MASK 0x00000040 +#define MH_DEBUG_REG00_TCD_EMPTY_MASK 0x00000080 +#define MH_DEBUG_REG00_TCD_FULL_MASK 0x00000100 +#define MH_DEBUG_REG00_RB_REQUEST_MASK 0x00000200 +#define MH_DEBUG_REG00_PA_REQUEST_MASK 0x00000400 +#define MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK 0x00000800 +#define MH_DEBUG_REG00_ARQ_EMPTY_MASK 0x00001000 +#define MH_DEBUG_REG00_ARQ_FULL_MASK 0x00002000 +#define MH_DEBUG_REG00_WDB_EMPTY_MASK 0x00004000 +#define MH_DEBUG_REG00_WDB_FULL_MASK 0x00008000 +#define MH_DEBUG_REG00_AXI_AVALID_MASK 0x00010000 +#define MH_DEBUG_REG00_AXI_AREADY_MASK 0x00020000 +#define MH_DEBUG_REG00_AXI_ARVALID_MASK 0x00040000 +#define MH_DEBUG_REG00_AXI_ARREADY_MASK 0x00080000 +#define MH_DEBUG_REG00_AXI_WVALID_MASK 0x00100000 +#define MH_DEBUG_REG00_AXI_WREADY_MASK 0x00200000 +#define MH_DEBUG_REG00_AXI_RVALID_MASK 0x00400000 +#define MH_DEBUG_REG00_AXI_RREADY_MASK 0x00800000 +#define MH_DEBUG_REG00_AXI_BVALID_MASK 0x01000000 +#define MH_DEBUG_REG00_AXI_BREADY_MASK 0x02000000 +#define MH_DEBUG_REG00_AXI_HALT_REQ_MASK 0x04000000 +#define MH_DEBUG_REG00_AXI_HALT_ACK_MASK 0x08000000 +#define MH_DEBUG_REG00_AXI_RDY_ENA_MASK 0x10000000 + +#define MH_DEBUG_REG00_MASK \ + (MH_DEBUG_REG00_MH_BUSY_MASK | \ + MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK | \ + MH_DEBUG_REG00_CP_REQUEST_MASK | \ + MH_DEBUG_REG00_VGT_REQUEST_MASK | \ + MH_DEBUG_REG00_TC_REQUEST_MASK | \ + MH_DEBUG_REG00_TC_CAM_EMPTY_MASK | \ + MH_DEBUG_REG00_TC_CAM_FULL_MASK | \ + MH_DEBUG_REG00_TCD_EMPTY_MASK | \ + MH_DEBUG_REG00_TCD_FULL_MASK | \ + MH_DEBUG_REG00_RB_REQUEST_MASK | \ + MH_DEBUG_REG00_PA_REQUEST_MASK | \ + MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK | \ + MH_DEBUG_REG00_ARQ_EMPTY_MASK | \ + MH_DEBUG_REG00_ARQ_FULL_MASK | \ + MH_DEBUG_REG00_WDB_EMPTY_MASK | \ + MH_DEBUG_REG00_WDB_FULL_MASK | \ + MH_DEBUG_REG00_AXI_AVALID_MASK | \ + MH_DEBUG_REG00_AXI_AREADY_MASK | \ + MH_DEBUG_REG00_AXI_ARVALID_MASK | \ + MH_DEBUG_REG00_AXI_ARREADY_MASK | \ + MH_DEBUG_REG00_AXI_WVALID_MASK | \ + MH_DEBUG_REG00_AXI_WREADY_MASK | \ + MH_DEBUG_REG00_AXI_RVALID_MASK | \ + MH_DEBUG_REG00_AXI_RREADY_MASK | \ + MH_DEBUG_REG00_AXI_BVALID_MASK | \ + MH_DEBUG_REG00_AXI_BREADY_MASK | \ + MH_DEBUG_REG00_AXI_HALT_REQ_MASK | \ + MH_DEBUG_REG00_AXI_HALT_ACK_MASK | \ + MH_DEBUG_REG00_AXI_RDY_ENA_MASK) + +#define MH_DEBUG_REG00(mh_busy, trans_outstanding, cp_request, vgt_request, tc_request, tc_cam_empty, tc_cam_full, tcd_empty, tcd_full, rb_request, pa_request, mh_clk_en_state, arq_empty, arq_full, wdb_empty, wdb_full, axi_avalid, axi_aready, axi_arvalid, axi_arready, axi_wvalid, axi_wready, axi_rvalid, axi_rready, axi_bvalid, axi_bready, axi_halt_req, axi_halt_ack, axi_rdy_ena) \ + ((mh_busy << MH_DEBUG_REG00_MH_BUSY_SHIFT) | \ + (trans_outstanding << MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT) | \ + (cp_request << MH_DEBUG_REG00_CP_REQUEST_SHIFT) | \ + (vgt_request << MH_DEBUG_REG00_VGT_REQUEST_SHIFT) | \ + (tc_request << MH_DEBUG_REG00_TC_REQUEST_SHIFT) | \ + (tc_cam_empty << MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT) | \ + (tc_cam_full << MH_DEBUG_REG00_TC_CAM_FULL_SHIFT) | \ + (tcd_empty << MH_DEBUG_REG00_TCD_EMPTY_SHIFT) | \ + (tcd_full << MH_DEBUG_REG00_TCD_FULL_SHIFT) | \ + (rb_request << MH_DEBUG_REG00_RB_REQUEST_SHIFT) | \ + (pa_request << MH_DEBUG_REG00_PA_REQUEST_SHIFT) | \ + (mh_clk_en_state << MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT) | \ + (arq_empty << MH_DEBUG_REG00_ARQ_EMPTY_SHIFT) | \ + (arq_full << MH_DEBUG_REG00_ARQ_FULL_SHIFT) | \ + (wdb_empty << MH_DEBUG_REG00_WDB_EMPTY_SHIFT) | \ + (wdb_full << MH_DEBUG_REG00_WDB_FULL_SHIFT) | \ + (axi_avalid << MH_DEBUG_REG00_AXI_AVALID_SHIFT) | \ + (axi_aready << MH_DEBUG_REG00_AXI_AREADY_SHIFT) | \ + (axi_arvalid << MH_DEBUG_REG00_AXI_ARVALID_SHIFT) | \ + (axi_arready << MH_DEBUG_REG00_AXI_ARREADY_SHIFT) | \ + (axi_wvalid << MH_DEBUG_REG00_AXI_WVALID_SHIFT) | \ + (axi_wready << MH_DEBUG_REG00_AXI_WREADY_SHIFT) | \ + (axi_rvalid << MH_DEBUG_REG00_AXI_RVALID_SHIFT) | \ + (axi_rready << MH_DEBUG_REG00_AXI_RREADY_SHIFT) | \ + (axi_bvalid << MH_DEBUG_REG00_AXI_BVALID_SHIFT) | \ + (axi_bready << MH_DEBUG_REG00_AXI_BREADY_SHIFT) | \ + (axi_halt_req << MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT) | \ + (axi_halt_ack << MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT) | \ + (axi_rdy_ena << MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT)) + +#define MH_DEBUG_REG00_GET_MH_BUSY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_MH_BUSY_MASK) >> MH_DEBUG_REG00_MH_BUSY_SHIFT) +#define MH_DEBUG_REG00_GET_TRANS_OUTSTANDING(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK) >> MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT) +#define MH_DEBUG_REG00_GET_CP_REQUEST(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_CP_REQUEST_MASK) >> MH_DEBUG_REG00_CP_REQUEST_SHIFT) +#define MH_DEBUG_REG00_GET_VGT_REQUEST(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_VGT_REQUEST_MASK) >> MH_DEBUG_REG00_VGT_REQUEST_SHIFT) +#define MH_DEBUG_REG00_GET_TC_REQUEST(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TC_REQUEST_MASK) >> MH_DEBUG_REG00_TC_REQUEST_SHIFT) +#define MH_DEBUG_REG00_GET_TC_CAM_EMPTY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TC_CAM_EMPTY_MASK) >> MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT) +#define MH_DEBUG_REG00_GET_TC_CAM_FULL(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TC_CAM_FULL_MASK) >> MH_DEBUG_REG00_TC_CAM_FULL_SHIFT) +#define MH_DEBUG_REG00_GET_TCD_EMPTY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TCD_EMPTY_MASK) >> MH_DEBUG_REG00_TCD_EMPTY_SHIFT) +#define MH_DEBUG_REG00_GET_TCD_FULL(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_TCD_FULL_MASK) >> MH_DEBUG_REG00_TCD_FULL_SHIFT) +#define MH_DEBUG_REG00_GET_RB_REQUEST(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_RB_REQUEST_MASK) >> MH_DEBUG_REG00_RB_REQUEST_SHIFT) +#define MH_DEBUG_REG00_GET_PA_REQUEST(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_PA_REQUEST_MASK) >> MH_DEBUG_REG00_PA_REQUEST_SHIFT) +#define MH_DEBUG_REG00_GET_MH_CLK_EN_STATE(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK) >> MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT) +#define MH_DEBUG_REG00_GET_ARQ_EMPTY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_ARQ_EMPTY_MASK) >> MH_DEBUG_REG00_ARQ_EMPTY_SHIFT) +#define MH_DEBUG_REG00_GET_ARQ_FULL(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_ARQ_FULL_MASK) >> MH_DEBUG_REG00_ARQ_FULL_SHIFT) +#define MH_DEBUG_REG00_GET_WDB_EMPTY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_WDB_EMPTY_MASK) >> MH_DEBUG_REG00_WDB_EMPTY_SHIFT) +#define MH_DEBUG_REG00_GET_WDB_FULL(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_WDB_FULL_MASK) >> MH_DEBUG_REG00_WDB_FULL_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_AVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_AVALID_MASK) >> MH_DEBUG_REG00_AXI_AVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_AREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_AREADY_MASK) >> MH_DEBUG_REG00_AXI_AREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_ARVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_ARVALID_MASK) >> MH_DEBUG_REG00_AXI_ARVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_ARREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_ARREADY_MASK) >> MH_DEBUG_REG00_AXI_ARREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_WVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_WVALID_MASK) >> MH_DEBUG_REG00_AXI_WVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_WREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_WREADY_MASK) >> MH_DEBUG_REG00_AXI_WREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_RVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RVALID_MASK) >> MH_DEBUG_REG00_AXI_RVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_RREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RREADY_MASK) >> MH_DEBUG_REG00_AXI_RREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_BVALID(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_BVALID_MASK) >> MH_DEBUG_REG00_AXI_BVALID_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_BREADY(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_BREADY_MASK) >> MH_DEBUG_REG00_AXI_BREADY_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_HALT_REQ(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_HALT_REQ_MASK) >> MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_HALT_ACK(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_HALT_ACK_MASK) >> MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT) +#define MH_DEBUG_REG00_GET_AXI_RDY_ENA(mh_debug_reg00) \ + ((mh_debug_reg00 & MH_DEBUG_REG00_AXI_RDY_ENA_MASK) >> MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT) + +#define MH_DEBUG_REG00_SET_MH_BUSY(mh_debug_reg00_reg, mh_busy) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_MH_BUSY_MASK) | (mh_busy << MH_DEBUG_REG00_MH_BUSY_SHIFT) +#define MH_DEBUG_REG00_SET_TRANS_OUTSTANDING(mh_debug_reg00_reg, trans_outstanding) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TRANS_OUTSTANDING_MASK) | (trans_outstanding << MH_DEBUG_REG00_TRANS_OUTSTANDING_SHIFT) +#define MH_DEBUG_REG00_SET_CP_REQUEST(mh_debug_reg00_reg, cp_request) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_CP_REQUEST_MASK) | (cp_request << MH_DEBUG_REG00_CP_REQUEST_SHIFT) +#define MH_DEBUG_REG00_SET_VGT_REQUEST(mh_debug_reg00_reg, vgt_request) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_VGT_REQUEST_MASK) | (vgt_request << MH_DEBUG_REG00_VGT_REQUEST_SHIFT) +#define MH_DEBUG_REG00_SET_TC_REQUEST(mh_debug_reg00_reg, tc_request) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_REQUEST_MASK) | (tc_request << MH_DEBUG_REG00_TC_REQUEST_SHIFT) +#define MH_DEBUG_REG00_SET_TC_CAM_EMPTY(mh_debug_reg00_reg, tc_cam_empty) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_CAM_EMPTY_MASK) | (tc_cam_empty << MH_DEBUG_REG00_TC_CAM_EMPTY_SHIFT) +#define MH_DEBUG_REG00_SET_TC_CAM_FULL(mh_debug_reg00_reg, tc_cam_full) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TC_CAM_FULL_MASK) | (tc_cam_full << MH_DEBUG_REG00_TC_CAM_FULL_SHIFT) +#define MH_DEBUG_REG00_SET_TCD_EMPTY(mh_debug_reg00_reg, tcd_empty) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TCD_EMPTY_MASK) | (tcd_empty << MH_DEBUG_REG00_TCD_EMPTY_SHIFT) +#define MH_DEBUG_REG00_SET_TCD_FULL(mh_debug_reg00_reg, tcd_full) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_TCD_FULL_MASK) | (tcd_full << MH_DEBUG_REG00_TCD_FULL_SHIFT) +#define MH_DEBUG_REG00_SET_RB_REQUEST(mh_debug_reg00_reg, rb_request) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_RB_REQUEST_MASK) | (rb_request << MH_DEBUG_REG00_RB_REQUEST_SHIFT) +#define MH_DEBUG_REG00_SET_PA_REQUEST(mh_debug_reg00_reg, pa_request) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_PA_REQUEST_MASK) | (pa_request << MH_DEBUG_REG00_PA_REQUEST_SHIFT) +#define MH_DEBUG_REG00_SET_MH_CLK_EN_STATE(mh_debug_reg00_reg, mh_clk_en_state) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_MH_CLK_EN_STATE_MASK) | (mh_clk_en_state << MH_DEBUG_REG00_MH_CLK_EN_STATE_SHIFT) +#define MH_DEBUG_REG00_SET_ARQ_EMPTY(mh_debug_reg00_reg, arq_empty) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_ARQ_EMPTY_MASK) | (arq_empty << MH_DEBUG_REG00_ARQ_EMPTY_SHIFT) +#define MH_DEBUG_REG00_SET_ARQ_FULL(mh_debug_reg00_reg, arq_full) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_ARQ_FULL_MASK) | (arq_full << MH_DEBUG_REG00_ARQ_FULL_SHIFT) +#define MH_DEBUG_REG00_SET_WDB_EMPTY(mh_debug_reg00_reg, wdb_empty) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_WDB_EMPTY_MASK) | (wdb_empty << MH_DEBUG_REG00_WDB_EMPTY_SHIFT) +#define MH_DEBUG_REG00_SET_WDB_FULL(mh_debug_reg00_reg, wdb_full) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_WDB_FULL_MASK) | (wdb_full << MH_DEBUG_REG00_WDB_FULL_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_AVALID(mh_debug_reg00_reg, axi_avalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_AVALID_MASK) | (axi_avalid << MH_DEBUG_REG00_AXI_AVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_AREADY(mh_debug_reg00_reg, axi_aready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_AREADY_MASK) | (axi_aready << MH_DEBUG_REG00_AXI_AREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_ARVALID(mh_debug_reg00_reg, axi_arvalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_ARVALID_MASK) | (axi_arvalid << MH_DEBUG_REG00_AXI_ARVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_ARREADY(mh_debug_reg00_reg, axi_arready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_ARREADY_MASK) | (axi_arready << MH_DEBUG_REG00_AXI_ARREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_WVALID(mh_debug_reg00_reg, axi_wvalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_WVALID_MASK) | (axi_wvalid << MH_DEBUG_REG00_AXI_WVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_WREADY(mh_debug_reg00_reg, axi_wready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_WREADY_MASK) | (axi_wready << MH_DEBUG_REG00_AXI_WREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_RVALID(mh_debug_reg00_reg, axi_rvalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RVALID_MASK) | (axi_rvalid << MH_DEBUG_REG00_AXI_RVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_RREADY(mh_debug_reg00_reg, axi_rready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RREADY_MASK) | (axi_rready << MH_DEBUG_REG00_AXI_RREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_BVALID(mh_debug_reg00_reg, axi_bvalid) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_BVALID_MASK) | (axi_bvalid << MH_DEBUG_REG00_AXI_BVALID_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_BREADY(mh_debug_reg00_reg, axi_bready) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_BREADY_MASK) | (axi_bready << MH_DEBUG_REG00_AXI_BREADY_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_HALT_REQ(mh_debug_reg00_reg, axi_halt_req) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_HALT_REQ_MASK) | (axi_halt_req << MH_DEBUG_REG00_AXI_HALT_REQ_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_HALT_ACK(mh_debug_reg00_reg, axi_halt_ack) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_HALT_ACK_MASK) | (axi_halt_ack << MH_DEBUG_REG00_AXI_HALT_ACK_SHIFT) +#define MH_DEBUG_REG00_SET_AXI_RDY_ENA(mh_debug_reg00_reg, axi_rdy_ena) \ + mh_debug_reg00_reg = (mh_debug_reg00_reg & ~MH_DEBUG_REG00_AXI_RDY_ENA_MASK) | (axi_rdy_ena << MH_DEBUG_REG00_AXI_RDY_ENA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg00_t { + unsigned int mh_busy : MH_DEBUG_REG00_MH_BUSY_SIZE; + unsigned int trans_outstanding : MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE; + unsigned int cp_request : MH_DEBUG_REG00_CP_REQUEST_SIZE; + unsigned int vgt_request : MH_DEBUG_REG00_VGT_REQUEST_SIZE; + unsigned int tc_request : MH_DEBUG_REG00_TC_REQUEST_SIZE; + unsigned int tc_cam_empty : MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE; + unsigned int tc_cam_full : MH_DEBUG_REG00_TC_CAM_FULL_SIZE; + unsigned int tcd_empty : MH_DEBUG_REG00_TCD_EMPTY_SIZE; + unsigned int tcd_full : MH_DEBUG_REG00_TCD_FULL_SIZE; + unsigned int rb_request : MH_DEBUG_REG00_RB_REQUEST_SIZE; + unsigned int pa_request : MH_DEBUG_REG00_PA_REQUEST_SIZE; + unsigned int mh_clk_en_state : MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE; + unsigned int arq_empty : MH_DEBUG_REG00_ARQ_EMPTY_SIZE; + unsigned int arq_full : MH_DEBUG_REG00_ARQ_FULL_SIZE; + unsigned int wdb_empty : MH_DEBUG_REG00_WDB_EMPTY_SIZE; + unsigned int wdb_full : MH_DEBUG_REG00_WDB_FULL_SIZE; + unsigned int axi_avalid : MH_DEBUG_REG00_AXI_AVALID_SIZE; + unsigned int axi_aready : MH_DEBUG_REG00_AXI_AREADY_SIZE; + unsigned int axi_arvalid : MH_DEBUG_REG00_AXI_ARVALID_SIZE; + unsigned int axi_arready : MH_DEBUG_REG00_AXI_ARREADY_SIZE; + unsigned int axi_wvalid : MH_DEBUG_REG00_AXI_WVALID_SIZE; + unsigned int axi_wready : MH_DEBUG_REG00_AXI_WREADY_SIZE; + unsigned int axi_rvalid : MH_DEBUG_REG00_AXI_RVALID_SIZE; + unsigned int axi_rready : MH_DEBUG_REG00_AXI_RREADY_SIZE; + unsigned int axi_bvalid : MH_DEBUG_REG00_AXI_BVALID_SIZE; + unsigned int axi_bready : MH_DEBUG_REG00_AXI_BREADY_SIZE; + unsigned int axi_halt_req : MH_DEBUG_REG00_AXI_HALT_REQ_SIZE; + unsigned int axi_halt_ack : MH_DEBUG_REG00_AXI_HALT_ACK_SIZE; + unsigned int axi_rdy_ena : MH_DEBUG_REG00_AXI_RDY_ENA_SIZE; + unsigned int : 3; + } mh_debug_reg00_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg00_t { + unsigned int : 3; + unsigned int axi_rdy_ena : MH_DEBUG_REG00_AXI_RDY_ENA_SIZE; + unsigned int axi_halt_ack : MH_DEBUG_REG00_AXI_HALT_ACK_SIZE; + unsigned int axi_halt_req : MH_DEBUG_REG00_AXI_HALT_REQ_SIZE; + unsigned int axi_bready : MH_DEBUG_REG00_AXI_BREADY_SIZE; + unsigned int axi_bvalid : MH_DEBUG_REG00_AXI_BVALID_SIZE; + unsigned int axi_rready : MH_DEBUG_REG00_AXI_RREADY_SIZE; + unsigned int axi_rvalid : MH_DEBUG_REG00_AXI_RVALID_SIZE; + unsigned int axi_wready : MH_DEBUG_REG00_AXI_WREADY_SIZE; + unsigned int axi_wvalid : MH_DEBUG_REG00_AXI_WVALID_SIZE; + unsigned int axi_arready : MH_DEBUG_REG00_AXI_ARREADY_SIZE; + unsigned int axi_arvalid : MH_DEBUG_REG00_AXI_ARVALID_SIZE; + unsigned int axi_aready : MH_DEBUG_REG00_AXI_AREADY_SIZE; + unsigned int axi_avalid : MH_DEBUG_REG00_AXI_AVALID_SIZE; + unsigned int wdb_full : MH_DEBUG_REG00_WDB_FULL_SIZE; + unsigned int wdb_empty : MH_DEBUG_REG00_WDB_EMPTY_SIZE; + unsigned int arq_full : MH_DEBUG_REG00_ARQ_FULL_SIZE; + unsigned int arq_empty : MH_DEBUG_REG00_ARQ_EMPTY_SIZE; + unsigned int mh_clk_en_state : MH_DEBUG_REG00_MH_CLK_EN_STATE_SIZE; + unsigned int pa_request : MH_DEBUG_REG00_PA_REQUEST_SIZE; + unsigned int rb_request : MH_DEBUG_REG00_RB_REQUEST_SIZE; + unsigned int tcd_full : MH_DEBUG_REG00_TCD_FULL_SIZE; + unsigned int tcd_empty : MH_DEBUG_REG00_TCD_EMPTY_SIZE; + unsigned int tc_cam_full : MH_DEBUG_REG00_TC_CAM_FULL_SIZE; + unsigned int tc_cam_empty : MH_DEBUG_REG00_TC_CAM_EMPTY_SIZE; + unsigned int tc_request : MH_DEBUG_REG00_TC_REQUEST_SIZE; + unsigned int vgt_request : MH_DEBUG_REG00_VGT_REQUEST_SIZE; + unsigned int cp_request : MH_DEBUG_REG00_CP_REQUEST_SIZE; + unsigned int trans_outstanding : MH_DEBUG_REG00_TRANS_OUTSTANDING_SIZE; + unsigned int mh_busy : MH_DEBUG_REG00_MH_BUSY_SIZE; + } mh_debug_reg00_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg00_t f; +} mh_debug_reg00_u; + + +/* + * MH_DEBUG_REG01 struct + */ + +#define MH_DEBUG_REG01_CP_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_CP_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_CP_WRITE_q_SIZE 1 +#define MH_DEBUG_REG01_CP_TAG_q_SIZE 3 +#define MH_DEBUG_REG01_CP_BLEN_q_SIZE 1 +#define MH_DEBUG_REG01_VGT_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_VGT_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_VGT_TAG_q_SIZE 1 +#define MH_DEBUG_REG01_TC_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_TC_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_TC_BLEN_q_SIZE 1 +#define MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_TC_MH_written_SIZE 1 +#define MH_DEBUG_REG01_RB_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_RB_RTR_q_SIZE 1 +#define MH_DEBUG_REG01_PA_SEND_q_SIZE 1 +#define MH_DEBUG_REG01_PA_RTR_q_SIZE 1 + +#define MH_DEBUG_REG01_CP_SEND_q_SHIFT 0 +#define MH_DEBUG_REG01_CP_RTR_q_SHIFT 1 +#define MH_DEBUG_REG01_CP_WRITE_q_SHIFT 2 +#define MH_DEBUG_REG01_CP_TAG_q_SHIFT 3 +#define MH_DEBUG_REG01_CP_BLEN_q_SHIFT 6 +#define MH_DEBUG_REG01_VGT_SEND_q_SHIFT 7 +#define MH_DEBUG_REG01_VGT_RTR_q_SHIFT 8 +#define MH_DEBUG_REG01_VGT_TAG_q_SHIFT 9 +#define MH_DEBUG_REG01_TC_SEND_q_SHIFT 10 +#define MH_DEBUG_REG01_TC_RTR_q_SHIFT 11 +#define MH_DEBUG_REG01_TC_BLEN_q_SHIFT 12 +#define MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT 13 +#define MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT 14 +#define MH_DEBUG_REG01_TC_MH_written_SHIFT 15 +#define MH_DEBUG_REG01_RB_SEND_q_SHIFT 16 +#define MH_DEBUG_REG01_RB_RTR_q_SHIFT 17 +#define MH_DEBUG_REG01_PA_SEND_q_SHIFT 18 +#define MH_DEBUG_REG01_PA_RTR_q_SHIFT 19 + +#define MH_DEBUG_REG01_CP_SEND_q_MASK 0x00000001 +#define MH_DEBUG_REG01_CP_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG01_CP_WRITE_q_MASK 0x00000004 +#define MH_DEBUG_REG01_CP_TAG_q_MASK 0x00000038 +#define MH_DEBUG_REG01_CP_BLEN_q_MASK 0x00000040 +#define MH_DEBUG_REG01_VGT_SEND_q_MASK 0x00000080 +#define MH_DEBUG_REG01_VGT_RTR_q_MASK 0x00000100 +#define MH_DEBUG_REG01_VGT_TAG_q_MASK 0x00000200 +#define MH_DEBUG_REG01_TC_SEND_q_MASK 0x00000400 +#define MH_DEBUG_REG01_TC_RTR_q_MASK 0x00000800 +#define MH_DEBUG_REG01_TC_BLEN_q_MASK 0x00001000 +#define MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK 0x00002000 +#define MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK 0x00004000 +#define MH_DEBUG_REG01_TC_MH_written_MASK 0x00008000 +#define MH_DEBUG_REG01_RB_SEND_q_MASK 0x00010000 +#define MH_DEBUG_REG01_RB_RTR_q_MASK 0x00020000 +#define MH_DEBUG_REG01_PA_SEND_q_MASK 0x00040000 +#define MH_DEBUG_REG01_PA_RTR_q_MASK 0x00080000 + +#define MH_DEBUG_REG01_MASK \ + (MH_DEBUG_REG01_CP_SEND_q_MASK | \ + MH_DEBUG_REG01_CP_RTR_q_MASK | \ + MH_DEBUG_REG01_CP_WRITE_q_MASK | \ + MH_DEBUG_REG01_CP_TAG_q_MASK | \ + MH_DEBUG_REG01_CP_BLEN_q_MASK | \ + MH_DEBUG_REG01_VGT_SEND_q_MASK | \ + MH_DEBUG_REG01_VGT_RTR_q_MASK | \ + MH_DEBUG_REG01_VGT_TAG_q_MASK | \ + MH_DEBUG_REG01_TC_SEND_q_MASK | \ + MH_DEBUG_REG01_TC_RTR_q_MASK | \ + MH_DEBUG_REG01_TC_BLEN_q_MASK | \ + MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK | \ + MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG01_TC_MH_written_MASK | \ + MH_DEBUG_REG01_RB_SEND_q_MASK | \ + MH_DEBUG_REG01_RB_RTR_q_MASK | \ + MH_DEBUG_REG01_PA_SEND_q_MASK | \ + MH_DEBUG_REG01_PA_RTR_q_MASK) + +#define MH_DEBUG_REG01(cp_send_q, cp_rtr_q, cp_write_q, cp_tag_q, cp_blen_q, vgt_send_q, vgt_rtr_q, vgt_tag_q, tc_send_q, tc_rtr_q, tc_blen_q, tc_roq_send_q, tc_roq_rtr_q, tc_mh_written, rb_send_q, rb_rtr_q, pa_send_q, pa_rtr_q) \ + ((cp_send_q << MH_DEBUG_REG01_CP_SEND_q_SHIFT) | \ + (cp_rtr_q << MH_DEBUG_REG01_CP_RTR_q_SHIFT) | \ + (cp_write_q << MH_DEBUG_REG01_CP_WRITE_q_SHIFT) | \ + (cp_tag_q << MH_DEBUG_REG01_CP_TAG_q_SHIFT) | \ + (cp_blen_q << MH_DEBUG_REG01_CP_BLEN_q_SHIFT) | \ + (vgt_send_q << MH_DEBUG_REG01_VGT_SEND_q_SHIFT) | \ + (vgt_rtr_q << MH_DEBUG_REG01_VGT_RTR_q_SHIFT) | \ + (vgt_tag_q << MH_DEBUG_REG01_VGT_TAG_q_SHIFT) | \ + (tc_send_q << MH_DEBUG_REG01_TC_SEND_q_SHIFT) | \ + (tc_rtr_q << MH_DEBUG_REG01_TC_RTR_q_SHIFT) | \ + (tc_blen_q << MH_DEBUG_REG01_TC_BLEN_q_SHIFT) | \ + (tc_roq_send_q << MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT) | \ + (tc_mh_written << MH_DEBUG_REG01_TC_MH_written_SHIFT) | \ + (rb_send_q << MH_DEBUG_REG01_RB_SEND_q_SHIFT) | \ + (rb_rtr_q << MH_DEBUG_REG01_RB_RTR_q_SHIFT) | \ + (pa_send_q << MH_DEBUG_REG01_PA_SEND_q_SHIFT) | \ + (pa_rtr_q << MH_DEBUG_REG01_PA_RTR_q_SHIFT)) + +#define MH_DEBUG_REG01_GET_CP_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_SEND_q_MASK) >> MH_DEBUG_REG01_CP_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_CP_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_RTR_q_MASK) >> MH_DEBUG_REG01_CP_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_CP_WRITE_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_WRITE_q_MASK) >> MH_DEBUG_REG01_CP_WRITE_q_SHIFT) +#define MH_DEBUG_REG01_GET_CP_TAG_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_TAG_q_MASK) >> MH_DEBUG_REG01_CP_TAG_q_SHIFT) +#define MH_DEBUG_REG01_GET_CP_BLEN_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_CP_BLEN_q_MASK) >> MH_DEBUG_REG01_CP_BLEN_q_SHIFT) +#define MH_DEBUG_REG01_GET_VGT_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_SEND_q_MASK) >> MH_DEBUG_REG01_VGT_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_VGT_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_RTR_q_MASK) >> MH_DEBUG_REG01_VGT_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_VGT_TAG_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_VGT_TAG_q_MASK) >> MH_DEBUG_REG01_VGT_TAG_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_SEND_q_MASK) >> MH_DEBUG_REG01_TC_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_RTR_q_MASK) >> MH_DEBUG_REG01_TC_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_BLEN_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_BLEN_q_MASK) >> MH_DEBUG_REG01_TC_BLEN_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_ROQ_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_ROQ_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_TC_MH_written(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_TC_MH_written_MASK) >> MH_DEBUG_REG01_TC_MH_written_SHIFT) +#define MH_DEBUG_REG01_GET_RB_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_RB_SEND_q_MASK) >> MH_DEBUG_REG01_RB_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_RB_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_RB_RTR_q_MASK) >> MH_DEBUG_REG01_RB_RTR_q_SHIFT) +#define MH_DEBUG_REG01_GET_PA_SEND_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_PA_SEND_q_MASK) >> MH_DEBUG_REG01_PA_SEND_q_SHIFT) +#define MH_DEBUG_REG01_GET_PA_RTR_q(mh_debug_reg01) \ + ((mh_debug_reg01 & MH_DEBUG_REG01_PA_RTR_q_MASK) >> MH_DEBUG_REG01_PA_RTR_q_SHIFT) + +#define MH_DEBUG_REG01_SET_CP_SEND_q(mh_debug_reg01_reg, cp_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_SEND_q_MASK) | (cp_send_q << MH_DEBUG_REG01_CP_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_CP_RTR_q(mh_debug_reg01_reg, cp_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_RTR_q_MASK) | (cp_rtr_q << MH_DEBUG_REG01_CP_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_CP_WRITE_q(mh_debug_reg01_reg, cp_write_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_WRITE_q_MASK) | (cp_write_q << MH_DEBUG_REG01_CP_WRITE_q_SHIFT) +#define MH_DEBUG_REG01_SET_CP_TAG_q(mh_debug_reg01_reg, cp_tag_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_TAG_q_MASK) | (cp_tag_q << MH_DEBUG_REG01_CP_TAG_q_SHIFT) +#define MH_DEBUG_REG01_SET_CP_BLEN_q(mh_debug_reg01_reg, cp_blen_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_CP_BLEN_q_MASK) | (cp_blen_q << MH_DEBUG_REG01_CP_BLEN_q_SHIFT) +#define MH_DEBUG_REG01_SET_VGT_SEND_q(mh_debug_reg01_reg, vgt_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_SEND_q_MASK) | (vgt_send_q << MH_DEBUG_REG01_VGT_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_VGT_RTR_q(mh_debug_reg01_reg, vgt_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_RTR_q_MASK) | (vgt_rtr_q << MH_DEBUG_REG01_VGT_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_VGT_TAG_q(mh_debug_reg01_reg, vgt_tag_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_VGT_TAG_q_MASK) | (vgt_tag_q << MH_DEBUG_REG01_VGT_TAG_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_SEND_q(mh_debug_reg01_reg, tc_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_SEND_q_MASK) | (tc_send_q << MH_DEBUG_REG01_TC_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_RTR_q(mh_debug_reg01_reg, tc_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_RTR_q_MASK) | (tc_rtr_q << MH_DEBUG_REG01_TC_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_BLEN_q(mh_debug_reg01_reg, tc_blen_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_BLEN_q_MASK) | (tc_blen_q << MH_DEBUG_REG01_TC_BLEN_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_ROQ_SEND_q(mh_debug_reg01_reg, tc_roq_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG01_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_ROQ_RTR_q(mh_debug_reg01_reg, tc_roq_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG01_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_TC_MH_written(mh_debug_reg01_reg, tc_mh_written) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG01_TC_MH_written_SHIFT) +#define MH_DEBUG_REG01_SET_RB_SEND_q(mh_debug_reg01_reg, rb_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_RB_SEND_q_MASK) | (rb_send_q << MH_DEBUG_REG01_RB_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_RB_RTR_q(mh_debug_reg01_reg, rb_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_RB_RTR_q_MASK) | (rb_rtr_q << MH_DEBUG_REG01_RB_RTR_q_SHIFT) +#define MH_DEBUG_REG01_SET_PA_SEND_q(mh_debug_reg01_reg, pa_send_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_PA_SEND_q_MASK) | (pa_send_q << MH_DEBUG_REG01_PA_SEND_q_SHIFT) +#define MH_DEBUG_REG01_SET_PA_RTR_q(mh_debug_reg01_reg, pa_rtr_q) \ + mh_debug_reg01_reg = (mh_debug_reg01_reg & ~MH_DEBUG_REG01_PA_RTR_q_MASK) | (pa_rtr_q << MH_DEBUG_REG01_PA_RTR_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg01_t { + unsigned int cp_send_q : MH_DEBUG_REG01_CP_SEND_q_SIZE; + unsigned int cp_rtr_q : MH_DEBUG_REG01_CP_RTR_q_SIZE; + unsigned int cp_write_q : MH_DEBUG_REG01_CP_WRITE_q_SIZE; + unsigned int cp_tag_q : MH_DEBUG_REG01_CP_TAG_q_SIZE; + unsigned int cp_blen_q : MH_DEBUG_REG01_CP_BLEN_q_SIZE; + unsigned int vgt_send_q : MH_DEBUG_REG01_VGT_SEND_q_SIZE; + unsigned int vgt_rtr_q : MH_DEBUG_REG01_VGT_RTR_q_SIZE; + unsigned int vgt_tag_q : MH_DEBUG_REG01_VGT_TAG_q_SIZE; + unsigned int tc_send_q : MH_DEBUG_REG01_TC_SEND_q_SIZE; + unsigned int tc_rtr_q : MH_DEBUG_REG01_TC_RTR_q_SIZE; + unsigned int tc_blen_q : MH_DEBUG_REG01_TC_BLEN_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG01_TC_MH_written_SIZE; + unsigned int rb_send_q : MH_DEBUG_REG01_RB_SEND_q_SIZE; + unsigned int rb_rtr_q : MH_DEBUG_REG01_RB_RTR_q_SIZE; + unsigned int pa_send_q : MH_DEBUG_REG01_PA_SEND_q_SIZE; + unsigned int pa_rtr_q : MH_DEBUG_REG01_PA_RTR_q_SIZE; + unsigned int : 12; + } mh_debug_reg01_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg01_t { + unsigned int : 12; + unsigned int pa_rtr_q : MH_DEBUG_REG01_PA_RTR_q_SIZE; + unsigned int pa_send_q : MH_DEBUG_REG01_PA_SEND_q_SIZE; + unsigned int rb_rtr_q : MH_DEBUG_REG01_RB_RTR_q_SIZE; + unsigned int rb_send_q : MH_DEBUG_REG01_RB_SEND_q_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG01_TC_MH_written_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG01_TC_ROQ_RTR_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG01_TC_ROQ_SEND_q_SIZE; + unsigned int tc_blen_q : MH_DEBUG_REG01_TC_BLEN_q_SIZE; + unsigned int tc_rtr_q : MH_DEBUG_REG01_TC_RTR_q_SIZE; + unsigned int tc_send_q : MH_DEBUG_REG01_TC_SEND_q_SIZE; + unsigned int vgt_tag_q : MH_DEBUG_REG01_VGT_TAG_q_SIZE; + unsigned int vgt_rtr_q : MH_DEBUG_REG01_VGT_RTR_q_SIZE; + unsigned int vgt_send_q : MH_DEBUG_REG01_VGT_SEND_q_SIZE; + unsigned int cp_blen_q : MH_DEBUG_REG01_CP_BLEN_q_SIZE; + unsigned int cp_tag_q : MH_DEBUG_REG01_CP_TAG_q_SIZE; + unsigned int cp_write_q : MH_DEBUG_REG01_CP_WRITE_q_SIZE; + unsigned int cp_rtr_q : MH_DEBUG_REG01_CP_RTR_q_SIZE; + unsigned int cp_send_q : MH_DEBUG_REG01_CP_SEND_q_SIZE; + } mh_debug_reg01_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg01_t f; +} mh_debug_reg01_u; + + +/* + * MH_DEBUG_REG02 struct + */ + +#define MH_DEBUG_REG02_MH_CP_grb_send_SIZE 1 +#define MH_DEBUG_REG02_MH_VGT_grb_send_SIZE 1 +#define MH_DEBUG_REG02_MH_TC_mcsend_SIZE 1 +#define MH_DEBUG_REG02_MH_CLNT_rlast_SIZE 1 +#define MH_DEBUG_REG02_MH_CLNT_tag_SIZE 3 +#define MH_DEBUG_REG02_RDC_RID_SIZE 3 +#define MH_DEBUG_REG02_RDC_RRESP_SIZE 2 +#define MH_DEBUG_REG02_MH_CP_writeclean_SIZE 1 +#define MH_DEBUG_REG02_MH_RB_writeclean_SIZE 1 +#define MH_DEBUG_REG02_MH_PA_writeclean_SIZE 1 +#define MH_DEBUG_REG02_BRC_BID_SIZE 3 +#define MH_DEBUG_REG02_BRC_BRESP_SIZE 2 + +#define MH_DEBUG_REG02_MH_CP_grb_send_SHIFT 0 +#define MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT 1 +#define MH_DEBUG_REG02_MH_TC_mcsend_SHIFT 2 +#define MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT 3 +#define MH_DEBUG_REG02_MH_CLNT_tag_SHIFT 4 +#define MH_DEBUG_REG02_RDC_RID_SHIFT 7 +#define MH_DEBUG_REG02_RDC_RRESP_SHIFT 10 +#define MH_DEBUG_REG02_MH_CP_writeclean_SHIFT 12 +#define MH_DEBUG_REG02_MH_RB_writeclean_SHIFT 13 +#define MH_DEBUG_REG02_MH_PA_writeclean_SHIFT 14 +#define MH_DEBUG_REG02_BRC_BID_SHIFT 15 +#define MH_DEBUG_REG02_BRC_BRESP_SHIFT 18 + +#define MH_DEBUG_REG02_MH_CP_grb_send_MASK 0x00000001 +#define MH_DEBUG_REG02_MH_VGT_grb_send_MASK 0x00000002 +#define MH_DEBUG_REG02_MH_TC_mcsend_MASK 0x00000004 +#define MH_DEBUG_REG02_MH_CLNT_rlast_MASK 0x00000008 +#define MH_DEBUG_REG02_MH_CLNT_tag_MASK 0x00000070 +#define MH_DEBUG_REG02_RDC_RID_MASK 0x00000380 +#define MH_DEBUG_REG02_RDC_RRESP_MASK 0x00000c00 +#define MH_DEBUG_REG02_MH_CP_writeclean_MASK 0x00001000 +#define MH_DEBUG_REG02_MH_RB_writeclean_MASK 0x00002000 +#define MH_DEBUG_REG02_MH_PA_writeclean_MASK 0x00004000 +#define MH_DEBUG_REG02_BRC_BID_MASK 0x00038000 +#define MH_DEBUG_REG02_BRC_BRESP_MASK 0x000c0000 + +#define MH_DEBUG_REG02_MASK \ + (MH_DEBUG_REG02_MH_CP_grb_send_MASK | \ + MH_DEBUG_REG02_MH_VGT_grb_send_MASK | \ + MH_DEBUG_REG02_MH_TC_mcsend_MASK | \ + MH_DEBUG_REG02_MH_CLNT_rlast_MASK | \ + MH_DEBUG_REG02_MH_CLNT_tag_MASK | \ + MH_DEBUG_REG02_RDC_RID_MASK | \ + MH_DEBUG_REG02_RDC_RRESP_MASK | \ + MH_DEBUG_REG02_MH_CP_writeclean_MASK | \ + MH_DEBUG_REG02_MH_RB_writeclean_MASK | \ + MH_DEBUG_REG02_MH_PA_writeclean_MASK | \ + MH_DEBUG_REG02_BRC_BID_MASK | \ + MH_DEBUG_REG02_BRC_BRESP_MASK) + +#define MH_DEBUG_REG02(mh_cp_grb_send, mh_vgt_grb_send, mh_tc_mcsend, mh_clnt_rlast, mh_clnt_tag, rdc_rid, rdc_rresp, mh_cp_writeclean, mh_rb_writeclean, mh_pa_writeclean, brc_bid, brc_bresp) \ + ((mh_cp_grb_send << MH_DEBUG_REG02_MH_CP_grb_send_SHIFT) | \ + (mh_vgt_grb_send << MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT) | \ + (mh_tc_mcsend << MH_DEBUG_REG02_MH_TC_mcsend_SHIFT) | \ + (mh_clnt_rlast << MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT) | \ + (mh_clnt_tag << MH_DEBUG_REG02_MH_CLNT_tag_SHIFT) | \ + (rdc_rid << MH_DEBUG_REG02_RDC_RID_SHIFT) | \ + (rdc_rresp << MH_DEBUG_REG02_RDC_RRESP_SHIFT) | \ + (mh_cp_writeclean << MH_DEBUG_REG02_MH_CP_writeclean_SHIFT) | \ + (mh_rb_writeclean << MH_DEBUG_REG02_MH_RB_writeclean_SHIFT) | \ + (mh_pa_writeclean << MH_DEBUG_REG02_MH_PA_writeclean_SHIFT) | \ + (brc_bid << MH_DEBUG_REG02_BRC_BID_SHIFT) | \ + (brc_bresp << MH_DEBUG_REG02_BRC_BRESP_SHIFT)) + +#define MH_DEBUG_REG02_GET_MH_CP_grb_send(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CP_grb_send_MASK) >> MH_DEBUG_REG02_MH_CP_grb_send_SHIFT) +#define MH_DEBUG_REG02_GET_MH_VGT_grb_send(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_VGT_grb_send_MASK) >> MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT) +#define MH_DEBUG_REG02_GET_MH_TC_mcsend(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_TC_mcsend_MASK) >> MH_DEBUG_REG02_MH_TC_mcsend_SHIFT) +#define MH_DEBUG_REG02_GET_MH_CLNT_rlast(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CLNT_rlast_MASK) >> MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT) +#define MH_DEBUG_REG02_GET_MH_CLNT_tag(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CLNT_tag_MASK) >> MH_DEBUG_REG02_MH_CLNT_tag_SHIFT) +#define MH_DEBUG_REG02_GET_RDC_RID(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_RDC_RID_MASK) >> MH_DEBUG_REG02_RDC_RID_SHIFT) +#define MH_DEBUG_REG02_GET_RDC_RRESP(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_RDC_RRESP_MASK) >> MH_DEBUG_REG02_RDC_RRESP_SHIFT) +#define MH_DEBUG_REG02_GET_MH_CP_writeclean(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_CP_writeclean_MASK) >> MH_DEBUG_REG02_MH_CP_writeclean_SHIFT) +#define MH_DEBUG_REG02_GET_MH_RB_writeclean(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_RB_writeclean_MASK) >> MH_DEBUG_REG02_MH_RB_writeclean_SHIFT) +#define MH_DEBUG_REG02_GET_MH_PA_writeclean(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_MH_PA_writeclean_MASK) >> MH_DEBUG_REG02_MH_PA_writeclean_SHIFT) +#define MH_DEBUG_REG02_GET_BRC_BID(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_BRC_BID_MASK) >> MH_DEBUG_REG02_BRC_BID_SHIFT) +#define MH_DEBUG_REG02_GET_BRC_BRESP(mh_debug_reg02) \ + ((mh_debug_reg02 & MH_DEBUG_REG02_BRC_BRESP_MASK) >> MH_DEBUG_REG02_BRC_BRESP_SHIFT) + +#define MH_DEBUG_REG02_SET_MH_CP_grb_send(mh_debug_reg02_reg, mh_cp_grb_send) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CP_grb_send_MASK) | (mh_cp_grb_send << MH_DEBUG_REG02_MH_CP_grb_send_SHIFT) +#define MH_DEBUG_REG02_SET_MH_VGT_grb_send(mh_debug_reg02_reg, mh_vgt_grb_send) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_VGT_grb_send_MASK) | (mh_vgt_grb_send << MH_DEBUG_REG02_MH_VGT_grb_send_SHIFT) +#define MH_DEBUG_REG02_SET_MH_TC_mcsend(mh_debug_reg02_reg, mh_tc_mcsend) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_TC_mcsend_MASK) | (mh_tc_mcsend << MH_DEBUG_REG02_MH_TC_mcsend_SHIFT) +#define MH_DEBUG_REG02_SET_MH_CLNT_rlast(mh_debug_reg02_reg, mh_clnt_rlast) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CLNT_rlast_MASK) | (mh_clnt_rlast << MH_DEBUG_REG02_MH_CLNT_rlast_SHIFT) +#define MH_DEBUG_REG02_SET_MH_CLNT_tag(mh_debug_reg02_reg, mh_clnt_tag) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CLNT_tag_MASK) | (mh_clnt_tag << MH_DEBUG_REG02_MH_CLNT_tag_SHIFT) +#define MH_DEBUG_REG02_SET_RDC_RID(mh_debug_reg02_reg, rdc_rid) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_RDC_RID_MASK) | (rdc_rid << MH_DEBUG_REG02_RDC_RID_SHIFT) +#define MH_DEBUG_REG02_SET_RDC_RRESP(mh_debug_reg02_reg, rdc_rresp) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_RDC_RRESP_MASK) | (rdc_rresp << MH_DEBUG_REG02_RDC_RRESP_SHIFT) +#define MH_DEBUG_REG02_SET_MH_CP_writeclean(mh_debug_reg02_reg, mh_cp_writeclean) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_CP_writeclean_MASK) | (mh_cp_writeclean << MH_DEBUG_REG02_MH_CP_writeclean_SHIFT) +#define MH_DEBUG_REG02_SET_MH_RB_writeclean(mh_debug_reg02_reg, mh_rb_writeclean) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_RB_writeclean_MASK) | (mh_rb_writeclean << MH_DEBUG_REG02_MH_RB_writeclean_SHIFT) +#define MH_DEBUG_REG02_SET_MH_PA_writeclean(mh_debug_reg02_reg, mh_pa_writeclean) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_MH_PA_writeclean_MASK) | (mh_pa_writeclean << MH_DEBUG_REG02_MH_PA_writeclean_SHIFT) +#define MH_DEBUG_REG02_SET_BRC_BID(mh_debug_reg02_reg, brc_bid) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_BRC_BID_MASK) | (brc_bid << MH_DEBUG_REG02_BRC_BID_SHIFT) +#define MH_DEBUG_REG02_SET_BRC_BRESP(mh_debug_reg02_reg, brc_bresp) \ + mh_debug_reg02_reg = (mh_debug_reg02_reg & ~MH_DEBUG_REG02_BRC_BRESP_MASK) | (brc_bresp << MH_DEBUG_REG02_BRC_BRESP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg02_t { + unsigned int mh_cp_grb_send : MH_DEBUG_REG02_MH_CP_grb_send_SIZE; + unsigned int mh_vgt_grb_send : MH_DEBUG_REG02_MH_VGT_grb_send_SIZE; + unsigned int mh_tc_mcsend : MH_DEBUG_REG02_MH_TC_mcsend_SIZE; + unsigned int mh_clnt_rlast : MH_DEBUG_REG02_MH_CLNT_rlast_SIZE; + unsigned int mh_clnt_tag : MH_DEBUG_REG02_MH_CLNT_tag_SIZE; + unsigned int rdc_rid : MH_DEBUG_REG02_RDC_RID_SIZE; + unsigned int rdc_rresp : MH_DEBUG_REG02_RDC_RRESP_SIZE; + unsigned int mh_cp_writeclean : MH_DEBUG_REG02_MH_CP_writeclean_SIZE; + unsigned int mh_rb_writeclean : MH_DEBUG_REG02_MH_RB_writeclean_SIZE; + unsigned int mh_pa_writeclean : MH_DEBUG_REG02_MH_PA_writeclean_SIZE; + unsigned int brc_bid : MH_DEBUG_REG02_BRC_BID_SIZE; + unsigned int brc_bresp : MH_DEBUG_REG02_BRC_BRESP_SIZE; + unsigned int : 12; + } mh_debug_reg02_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg02_t { + unsigned int : 12; + unsigned int brc_bresp : MH_DEBUG_REG02_BRC_BRESP_SIZE; + unsigned int brc_bid : MH_DEBUG_REG02_BRC_BID_SIZE; + unsigned int mh_pa_writeclean : MH_DEBUG_REG02_MH_PA_writeclean_SIZE; + unsigned int mh_rb_writeclean : MH_DEBUG_REG02_MH_RB_writeclean_SIZE; + unsigned int mh_cp_writeclean : MH_DEBUG_REG02_MH_CP_writeclean_SIZE; + unsigned int rdc_rresp : MH_DEBUG_REG02_RDC_RRESP_SIZE; + unsigned int rdc_rid : MH_DEBUG_REG02_RDC_RID_SIZE; + unsigned int mh_clnt_tag : MH_DEBUG_REG02_MH_CLNT_tag_SIZE; + unsigned int mh_clnt_rlast : MH_DEBUG_REG02_MH_CLNT_rlast_SIZE; + unsigned int mh_tc_mcsend : MH_DEBUG_REG02_MH_TC_mcsend_SIZE; + unsigned int mh_vgt_grb_send : MH_DEBUG_REG02_MH_VGT_grb_send_SIZE; + unsigned int mh_cp_grb_send : MH_DEBUG_REG02_MH_CP_grb_send_SIZE; + } mh_debug_reg02_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg02_t f; +} mh_debug_reg02_u; + + +/* + * MH_DEBUG_REG03 struct + */ + +#define MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE 32 + +#define MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT 0 + +#define MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG03_MASK \ + (MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) + +#define MH_DEBUG_REG03(mh_clnt_data_31_0) \ + ((mh_clnt_data_31_0 << MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT)) + +#define MH_DEBUG_REG03_GET_MH_CLNT_data_31_0(mh_debug_reg03) \ + ((mh_debug_reg03 & MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) >> MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT) + +#define MH_DEBUG_REG03_SET_MH_CLNT_data_31_0(mh_debug_reg03_reg, mh_clnt_data_31_0) \ + mh_debug_reg03_reg = (mh_debug_reg03_reg & ~MH_DEBUG_REG03_MH_CLNT_data_31_0_MASK) | (mh_clnt_data_31_0 << MH_DEBUG_REG03_MH_CLNT_data_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg03_t { + unsigned int mh_clnt_data_31_0 : MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE; + } mh_debug_reg03_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg03_t { + unsigned int mh_clnt_data_31_0 : MH_DEBUG_REG03_MH_CLNT_data_31_0_SIZE; + } mh_debug_reg03_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg03_t f; +} mh_debug_reg03_u; + + +/* + * MH_DEBUG_REG04 struct + */ + +#define MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE 32 + +#define MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT 0 + +#define MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG04_MASK \ + (MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) + +#define MH_DEBUG_REG04(mh_clnt_data_63_32) \ + ((mh_clnt_data_63_32 << MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT)) + +#define MH_DEBUG_REG04_GET_MH_CLNT_data_63_32(mh_debug_reg04) \ + ((mh_debug_reg04 & MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) >> MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT) + +#define MH_DEBUG_REG04_SET_MH_CLNT_data_63_32(mh_debug_reg04_reg, mh_clnt_data_63_32) \ + mh_debug_reg04_reg = (mh_debug_reg04_reg & ~MH_DEBUG_REG04_MH_CLNT_data_63_32_MASK) | (mh_clnt_data_63_32 << MH_DEBUG_REG04_MH_CLNT_data_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg04_t { + unsigned int mh_clnt_data_63_32 : MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE; + } mh_debug_reg04_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg04_t { + unsigned int mh_clnt_data_63_32 : MH_DEBUG_REG04_MH_CLNT_data_63_32_SIZE; + } mh_debug_reg04_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg04_t f; +} mh_debug_reg04_u; + + +/* + * MH_DEBUG_REG05 struct + */ + +#define MH_DEBUG_REG05_CP_MH_send_SIZE 1 +#define MH_DEBUG_REG05_CP_MH_write_SIZE 1 +#define MH_DEBUG_REG05_CP_MH_tag_SIZE 3 +#define MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE 27 + +#define MH_DEBUG_REG05_CP_MH_send_SHIFT 0 +#define MH_DEBUG_REG05_CP_MH_write_SHIFT 1 +#define MH_DEBUG_REG05_CP_MH_tag_SHIFT 2 +#define MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT 5 + +#define MH_DEBUG_REG05_CP_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG05_CP_MH_write_MASK 0x00000002 +#define MH_DEBUG_REG05_CP_MH_tag_MASK 0x0000001c +#define MH_DEBUG_REG05_CP_MH_ad_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG05_MASK \ + (MH_DEBUG_REG05_CP_MH_send_MASK | \ + MH_DEBUG_REG05_CP_MH_write_MASK | \ + MH_DEBUG_REG05_CP_MH_tag_MASK | \ + MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) + +#define MH_DEBUG_REG05(cp_mh_send, cp_mh_write, cp_mh_tag, cp_mh_ad_31_5) \ + ((cp_mh_send << MH_DEBUG_REG05_CP_MH_send_SHIFT) | \ + (cp_mh_write << MH_DEBUG_REG05_CP_MH_write_SHIFT) | \ + (cp_mh_tag << MH_DEBUG_REG05_CP_MH_tag_SHIFT) | \ + (cp_mh_ad_31_5 << MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT)) + +#define MH_DEBUG_REG05_GET_CP_MH_send(mh_debug_reg05) \ + ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_send_MASK) >> MH_DEBUG_REG05_CP_MH_send_SHIFT) +#define MH_DEBUG_REG05_GET_CP_MH_write(mh_debug_reg05) \ + ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_write_MASK) >> MH_DEBUG_REG05_CP_MH_write_SHIFT) +#define MH_DEBUG_REG05_GET_CP_MH_tag(mh_debug_reg05) \ + ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_tag_MASK) >> MH_DEBUG_REG05_CP_MH_tag_SHIFT) +#define MH_DEBUG_REG05_GET_CP_MH_ad_31_5(mh_debug_reg05) \ + ((mh_debug_reg05 & MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) >> MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT) + +#define MH_DEBUG_REG05_SET_CP_MH_send(mh_debug_reg05_reg, cp_mh_send) \ + mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_send_MASK) | (cp_mh_send << MH_DEBUG_REG05_CP_MH_send_SHIFT) +#define MH_DEBUG_REG05_SET_CP_MH_write(mh_debug_reg05_reg, cp_mh_write) \ + mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_write_MASK) | (cp_mh_write << MH_DEBUG_REG05_CP_MH_write_SHIFT) +#define MH_DEBUG_REG05_SET_CP_MH_tag(mh_debug_reg05_reg, cp_mh_tag) \ + mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_tag_MASK) | (cp_mh_tag << MH_DEBUG_REG05_CP_MH_tag_SHIFT) +#define MH_DEBUG_REG05_SET_CP_MH_ad_31_5(mh_debug_reg05_reg, cp_mh_ad_31_5) \ + mh_debug_reg05_reg = (mh_debug_reg05_reg & ~MH_DEBUG_REG05_CP_MH_ad_31_5_MASK) | (cp_mh_ad_31_5 << MH_DEBUG_REG05_CP_MH_ad_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg05_t { + unsigned int cp_mh_send : MH_DEBUG_REG05_CP_MH_send_SIZE; + unsigned int cp_mh_write : MH_DEBUG_REG05_CP_MH_write_SIZE; + unsigned int cp_mh_tag : MH_DEBUG_REG05_CP_MH_tag_SIZE; + unsigned int cp_mh_ad_31_5 : MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE; + } mh_debug_reg05_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg05_t { + unsigned int cp_mh_ad_31_5 : MH_DEBUG_REG05_CP_MH_ad_31_5_SIZE; + unsigned int cp_mh_tag : MH_DEBUG_REG05_CP_MH_tag_SIZE; + unsigned int cp_mh_write : MH_DEBUG_REG05_CP_MH_write_SIZE; + unsigned int cp_mh_send : MH_DEBUG_REG05_CP_MH_send_SIZE; + } mh_debug_reg05_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg05_t f; +} mh_debug_reg05_u; + + +/* + * MH_DEBUG_REG06 struct + */ + +#define MH_DEBUG_REG06_CP_MH_data_31_0_SIZE 32 + +#define MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT 0 + +#define MH_DEBUG_REG06_CP_MH_data_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG06_MASK \ + (MH_DEBUG_REG06_CP_MH_data_31_0_MASK) + +#define MH_DEBUG_REG06(cp_mh_data_31_0) \ + ((cp_mh_data_31_0 << MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT)) + +#define MH_DEBUG_REG06_GET_CP_MH_data_31_0(mh_debug_reg06) \ + ((mh_debug_reg06 & MH_DEBUG_REG06_CP_MH_data_31_0_MASK) >> MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT) + +#define MH_DEBUG_REG06_SET_CP_MH_data_31_0(mh_debug_reg06_reg, cp_mh_data_31_0) \ + mh_debug_reg06_reg = (mh_debug_reg06_reg & ~MH_DEBUG_REG06_CP_MH_data_31_0_MASK) | (cp_mh_data_31_0 << MH_DEBUG_REG06_CP_MH_data_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg06_t { + unsigned int cp_mh_data_31_0 : MH_DEBUG_REG06_CP_MH_data_31_0_SIZE; + } mh_debug_reg06_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg06_t { + unsigned int cp_mh_data_31_0 : MH_DEBUG_REG06_CP_MH_data_31_0_SIZE; + } mh_debug_reg06_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg06_t f; +} mh_debug_reg06_u; + + +/* + * MH_DEBUG_REG07 struct + */ + +#define MH_DEBUG_REG07_CP_MH_data_63_32_SIZE 32 + +#define MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT 0 + +#define MH_DEBUG_REG07_CP_MH_data_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG07_MASK \ + (MH_DEBUG_REG07_CP_MH_data_63_32_MASK) + +#define MH_DEBUG_REG07(cp_mh_data_63_32) \ + ((cp_mh_data_63_32 << MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT)) + +#define MH_DEBUG_REG07_GET_CP_MH_data_63_32(mh_debug_reg07) \ + ((mh_debug_reg07 & MH_DEBUG_REG07_CP_MH_data_63_32_MASK) >> MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT) + +#define MH_DEBUG_REG07_SET_CP_MH_data_63_32(mh_debug_reg07_reg, cp_mh_data_63_32) \ + mh_debug_reg07_reg = (mh_debug_reg07_reg & ~MH_DEBUG_REG07_CP_MH_data_63_32_MASK) | (cp_mh_data_63_32 << MH_DEBUG_REG07_CP_MH_data_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg07_t { + unsigned int cp_mh_data_63_32 : MH_DEBUG_REG07_CP_MH_data_63_32_SIZE; + } mh_debug_reg07_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg07_t { + unsigned int cp_mh_data_63_32 : MH_DEBUG_REG07_CP_MH_data_63_32_SIZE; + } mh_debug_reg07_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg07_t f; +} mh_debug_reg07_u; + + +/* + * MH_DEBUG_REG08 struct + */ + +#define MH_DEBUG_REG08_CP_MH_be_SIZE 8 +#define MH_DEBUG_REG08_RB_MH_be_SIZE 8 +#define MH_DEBUG_REG08_PA_MH_be_SIZE 8 + +#define MH_DEBUG_REG08_CP_MH_be_SHIFT 0 +#define MH_DEBUG_REG08_RB_MH_be_SHIFT 8 +#define MH_DEBUG_REG08_PA_MH_be_SHIFT 16 + +#define MH_DEBUG_REG08_CP_MH_be_MASK 0x000000ff +#define MH_DEBUG_REG08_RB_MH_be_MASK 0x0000ff00 +#define MH_DEBUG_REG08_PA_MH_be_MASK 0x00ff0000 + +#define MH_DEBUG_REG08_MASK \ + (MH_DEBUG_REG08_CP_MH_be_MASK | \ + MH_DEBUG_REG08_RB_MH_be_MASK | \ + MH_DEBUG_REG08_PA_MH_be_MASK) + +#define MH_DEBUG_REG08(cp_mh_be, rb_mh_be, pa_mh_be) \ + ((cp_mh_be << MH_DEBUG_REG08_CP_MH_be_SHIFT) | \ + (rb_mh_be << MH_DEBUG_REG08_RB_MH_be_SHIFT) | \ + (pa_mh_be << MH_DEBUG_REG08_PA_MH_be_SHIFT)) + +#define MH_DEBUG_REG08_GET_CP_MH_be(mh_debug_reg08) \ + ((mh_debug_reg08 & MH_DEBUG_REG08_CP_MH_be_MASK) >> MH_DEBUG_REG08_CP_MH_be_SHIFT) +#define MH_DEBUG_REG08_GET_RB_MH_be(mh_debug_reg08) \ + ((mh_debug_reg08 & MH_DEBUG_REG08_RB_MH_be_MASK) >> MH_DEBUG_REG08_RB_MH_be_SHIFT) +#define MH_DEBUG_REG08_GET_PA_MH_be(mh_debug_reg08) \ + ((mh_debug_reg08 & MH_DEBUG_REG08_PA_MH_be_MASK) >> MH_DEBUG_REG08_PA_MH_be_SHIFT) + +#define MH_DEBUG_REG08_SET_CP_MH_be(mh_debug_reg08_reg, cp_mh_be) \ + mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_CP_MH_be_MASK) | (cp_mh_be << MH_DEBUG_REG08_CP_MH_be_SHIFT) +#define MH_DEBUG_REG08_SET_RB_MH_be(mh_debug_reg08_reg, rb_mh_be) \ + mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_RB_MH_be_MASK) | (rb_mh_be << MH_DEBUG_REG08_RB_MH_be_SHIFT) +#define MH_DEBUG_REG08_SET_PA_MH_be(mh_debug_reg08_reg, pa_mh_be) \ + mh_debug_reg08_reg = (mh_debug_reg08_reg & ~MH_DEBUG_REG08_PA_MH_be_MASK) | (pa_mh_be << MH_DEBUG_REG08_PA_MH_be_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg08_t { + unsigned int cp_mh_be : MH_DEBUG_REG08_CP_MH_be_SIZE; + unsigned int rb_mh_be : MH_DEBUG_REG08_RB_MH_be_SIZE; + unsigned int pa_mh_be : MH_DEBUG_REG08_PA_MH_be_SIZE; + unsigned int : 8; + } mh_debug_reg08_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg08_t { + unsigned int : 8; + unsigned int pa_mh_be : MH_DEBUG_REG08_PA_MH_be_SIZE; + unsigned int rb_mh_be : MH_DEBUG_REG08_RB_MH_be_SIZE; + unsigned int cp_mh_be : MH_DEBUG_REG08_CP_MH_be_SIZE; + } mh_debug_reg08_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg08_t f; +} mh_debug_reg08_u; + + +/* + * MH_DEBUG_REG09 struct + */ + +#define MH_DEBUG_REG09_ALWAYS_ZERO_SIZE 3 +#define MH_DEBUG_REG09_VGT_MH_send_SIZE 1 +#define MH_DEBUG_REG09_VGT_MH_tagbe_SIZE 1 +#define MH_DEBUG_REG09_VGT_MH_ad_31_5_SIZE 27 + +#define MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG09_VGT_MH_send_SHIFT 3 +#define MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT 4 +#define MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT 5 + +#define MH_DEBUG_REG09_ALWAYS_ZERO_MASK 0x00000007 +#define MH_DEBUG_REG09_VGT_MH_send_MASK 0x00000008 +#define MH_DEBUG_REG09_VGT_MH_tagbe_MASK 0x00000010 +#define MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG09_MASK \ + (MH_DEBUG_REG09_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG09_VGT_MH_send_MASK | \ + MH_DEBUG_REG09_VGT_MH_tagbe_MASK | \ + MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK) + +#define MH_DEBUG_REG09(always_zero, vgt_mh_send, vgt_mh_tagbe, vgt_mh_ad_31_5) \ + ((always_zero << MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT) | \ + (vgt_mh_send << MH_DEBUG_REG09_VGT_MH_send_SHIFT) | \ + (vgt_mh_tagbe << MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT) | \ + (vgt_mh_ad_31_5 << MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT)) + +#define MH_DEBUG_REG09_GET_ALWAYS_ZERO(mh_debug_reg09) \ + ((mh_debug_reg09 & MH_DEBUG_REG09_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG09_GET_VGT_MH_send(mh_debug_reg09) \ + ((mh_debug_reg09 & MH_DEBUG_REG09_VGT_MH_send_MASK) >> MH_DEBUG_REG09_VGT_MH_send_SHIFT) +#define MH_DEBUG_REG09_GET_VGT_MH_tagbe(mh_debug_reg09) \ + ((mh_debug_reg09 & MH_DEBUG_REG09_VGT_MH_tagbe_MASK) >> MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT) +#define MH_DEBUG_REG09_GET_VGT_MH_ad_31_5(mh_debug_reg09) \ + ((mh_debug_reg09 & MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK) >> MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT) + +#define MH_DEBUG_REG09_SET_ALWAYS_ZERO(mh_debug_reg09_reg, always_zero) \ + mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG09_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG09_SET_VGT_MH_send(mh_debug_reg09_reg, vgt_mh_send) \ + mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_VGT_MH_send_MASK) | (vgt_mh_send << MH_DEBUG_REG09_VGT_MH_send_SHIFT) +#define MH_DEBUG_REG09_SET_VGT_MH_tagbe(mh_debug_reg09_reg, vgt_mh_tagbe) \ + mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_VGT_MH_tagbe_MASK) | (vgt_mh_tagbe << MH_DEBUG_REG09_VGT_MH_tagbe_SHIFT) +#define MH_DEBUG_REG09_SET_VGT_MH_ad_31_5(mh_debug_reg09_reg, vgt_mh_ad_31_5) \ + mh_debug_reg09_reg = (mh_debug_reg09_reg & ~MH_DEBUG_REG09_VGT_MH_ad_31_5_MASK) | (vgt_mh_ad_31_5 << MH_DEBUG_REG09_VGT_MH_ad_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg09_t { + unsigned int always_zero : MH_DEBUG_REG09_ALWAYS_ZERO_SIZE; + unsigned int vgt_mh_send : MH_DEBUG_REG09_VGT_MH_send_SIZE; + unsigned int vgt_mh_tagbe : MH_DEBUG_REG09_VGT_MH_tagbe_SIZE; + unsigned int vgt_mh_ad_31_5 : MH_DEBUG_REG09_VGT_MH_ad_31_5_SIZE; + } mh_debug_reg09_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg09_t { + unsigned int vgt_mh_ad_31_5 : MH_DEBUG_REG09_VGT_MH_ad_31_5_SIZE; + unsigned int vgt_mh_tagbe : MH_DEBUG_REG09_VGT_MH_tagbe_SIZE; + unsigned int vgt_mh_send : MH_DEBUG_REG09_VGT_MH_send_SIZE; + unsigned int always_zero : MH_DEBUG_REG09_ALWAYS_ZERO_SIZE; + } mh_debug_reg09_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg09_t f; +} mh_debug_reg09_u; + + +/* + * MH_DEBUG_REG10 struct + */ + +#define MH_DEBUG_REG10_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG10_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG10_TC_MH_mask_SIZE 2 +#define MH_DEBUG_REG10_TC_MH_addr_31_5_SIZE 27 + +#define MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG10_TC_MH_send_SHIFT 2 +#define MH_DEBUG_REG10_TC_MH_mask_SHIFT 3 +#define MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT 5 + +#define MH_DEBUG_REG10_ALWAYS_ZERO_MASK 0x00000003 +#define MH_DEBUG_REG10_TC_MH_send_MASK 0x00000004 +#define MH_DEBUG_REG10_TC_MH_mask_MASK 0x00000018 +#define MH_DEBUG_REG10_TC_MH_addr_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG10_MASK \ + (MH_DEBUG_REG10_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG10_TC_MH_send_MASK | \ + MH_DEBUG_REG10_TC_MH_mask_MASK | \ + MH_DEBUG_REG10_TC_MH_addr_31_5_MASK) + +#define MH_DEBUG_REG10(always_zero, tc_mh_send, tc_mh_mask, tc_mh_addr_31_5) \ + ((always_zero << MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT) | \ + (tc_mh_send << MH_DEBUG_REG10_TC_MH_send_SHIFT) | \ + (tc_mh_mask << MH_DEBUG_REG10_TC_MH_mask_SHIFT) | \ + (tc_mh_addr_31_5 << MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT)) + +#define MH_DEBUG_REG10_GET_ALWAYS_ZERO(mh_debug_reg10) \ + ((mh_debug_reg10 & MH_DEBUG_REG10_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG10_GET_TC_MH_send(mh_debug_reg10) \ + ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_send_MASK) >> MH_DEBUG_REG10_TC_MH_send_SHIFT) +#define MH_DEBUG_REG10_GET_TC_MH_mask(mh_debug_reg10) \ + ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_mask_MASK) >> MH_DEBUG_REG10_TC_MH_mask_SHIFT) +#define MH_DEBUG_REG10_GET_TC_MH_addr_31_5(mh_debug_reg10) \ + ((mh_debug_reg10 & MH_DEBUG_REG10_TC_MH_addr_31_5_MASK) >> MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT) + +#define MH_DEBUG_REG10_SET_ALWAYS_ZERO(mh_debug_reg10_reg, always_zero) \ + mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG10_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG10_SET_TC_MH_send(mh_debug_reg10_reg, tc_mh_send) \ + mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG10_TC_MH_send_SHIFT) +#define MH_DEBUG_REG10_SET_TC_MH_mask(mh_debug_reg10_reg, tc_mh_mask) \ + mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_mask_MASK) | (tc_mh_mask << MH_DEBUG_REG10_TC_MH_mask_SHIFT) +#define MH_DEBUG_REG10_SET_TC_MH_addr_31_5(mh_debug_reg10_reg, tc_mh_addr_31_5) \ + mh_debug_reg10_reg = (mh_debug_reg10_reg & ~MH_DEBUG_REG10_TC_MH_addr_31_5_MASK) | (tc_mh_addr_31_5 << MH_DEBUG_REG10_TC_MH_addr_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg10_t { + unsigned int always_zero : MH_DEBUG_REG10_ALWAYS_ZERO_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG10_TC_MH_send_SIZE; + unsigned int tc_mh_mask : MH_DEBUG_REG10_TC_MH_mask_SIZE; + unsigned int tc_mh_addr_31_5 : MH_DEBUG_REG10_TC_MH_addr_31_5_SIZE; + } mh_debug_reg10_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg10_t { + unsigned int tc_mh_addr_31_5 : MH_DEBUG_REG10_TC_MH_addr_31_5_SIZE; + unsigned int tc_mh_mask : MH_DEBUG_REG10_TC_MH_mask_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG10_TC_MH_send_SIZE; + unsigned int always_zero : MH_DEBUG_REG10_ALWAYS_ZERO_SIZE; + } mh_debug_reg10_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg10_t f; +} mh_debug_reg10_u; + + +/* + * MH_DEBUG_REG11 struct + */ + +#define MH_DEBUG_REG11_TC_MH_info_SIZE 25 +#define MH_DEBUG_REG11_TC_MH_send_SIZE 1 + +#define MH_DEBUG_REG11_TC_MH_info_SHIFT 0 +#define MH_DEBUG_REG11_TC_MH_send_SHIFT 25 + +#define MH_DEBUG_REG11_TC_MH_info_MASK 0x01ffffff +#define MH_DEBUG_REG11_TC_MH_send_MASK 0x02000000 + +#define MH_DEBUG_REG11_MASK \ + (MH_DEBUG_REG11_TC_MH_info_MASK | \ + MH_DEBUG_REG11_TC_MH_send_MASK) + +#define MH_DEBUG_REG11(tc_mh_info, tc_mh_send) \ + ((tc_mh_info << MH_DEBUG_REG11_TC_MH_info_SHIFT) | \ + (tc_mh_send << MH_DEBUG_REG11_TC_MH_send_SHIFT)) + +#define MH_DEBUG_REG11_GET_TC_MH_info(mh_debug_reg11) \ + ((mh_debug_reg11 & MH_DEBUG_REG11_TC_MH_info_MASK) >> MH_DEBUG_REG11_TC_MH_info_SHIFT) +#define MH_DEBUG_REG11_GET_TC_MH_send(mh_debug_reg11) \ + ((mh_debug_reg11 & MH_DEBUG_REG11_TC_MH_send_MASK) >> MH_DEBUG_REG11_TC_MH_send_SHIFT) + +#define MH_DEBUG_REG11_SET_TC_MH_info(mh_debug_reg11_reg, tc_mh_info) \ + mh_debug_reg11_reg = (mh_debug_reg11_reg & ~MH_DEBUG_REG11_TC_MH_info_MASK) | (tc_mh_info << MH_DEBUG_REG11_TC_MH_info_SHIFT) +#define MH_DEBUG_REG11_SET_TC_MH_send(mh_debug_reg11_reg, tc_mh_send) \ + mh_debug_reg11_reg = (mh_debug_reg11_reg & ~MH_DEBUG_REG11_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG11_TC_MH_send_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg11_t { + unsigned int tc_mh_info : MH_DEBUG_REG11_TC_MH_info_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG11_TC_MH_send_SIZE; + unsigned int : 6; + } mh_debug_reg11_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg11_t { + unsigned int : 6; + unsigned int tc_mh_send : MH_DEBUG_REG11_TC_MH_send_SIZE; + unsigned int tc_mh_info : MH_DEBUG_REG11_TC_MH_info_SIZE; + } mh_debug_reg11_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg11_t f; +} mh_debug_reg11_u; + + +/* + * MH_DEBUG_REG12 struct + */ + +#define MH_DEBUG_REG12_MH_TC_mcinfo_SIZE 25 +#define MH_DEBUG_REG12_MH_TC_mcinfo_send_SIZE 1 +#define MH_DEBUG_REG12_TC_MH_written_SIZE 1 + +#define MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT 0 +#define MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT 25 +#define MH_DEBUG_REG12_TC_MH_written_SHIFT 26 + +#define MH_DEBUG_REG12_MH_TC_mcinfo_MASK 0x01ffffff +#define MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK 0x02000000 +#define MH_DEBUG_REG12_TC_MH_written_MASK 0x04000000 + +#define MH_DEBUG_REG12_MASK \ + (MH_DEBUG_REG12_MH_TC_mcinfo_MASK | \ + MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK | \ + MH_DEBUG_REG12_TC_MH_written_MASK) + +#define MH_DEBUG_REG12(mh_tc_mcinfo, mh_tc_mcinfo_send, tc_mh_written) \ + ((mh_tc_mcinfo << MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT) | \ + (mh_tc_mcinfo_send << MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT) | \ + (tc_mh_written << MH_DEBUG_REG12_TC_MH_written_SHIFT)) + +#define MH_DEBUG_REG12_GET_MH_TC_mcinfo(mh_debug_reg12) \ + ((mh_debug_reg12 & MH_DEBUG_REG12_MH_TC_mcinfo_MASK) >> MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT) +#define MH_DEBUG_REG12_GET_MH_TC_mcinfo_send(mh_debug_reg12) \ + ((mh_debug_reg12 & MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK) >> MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT) +#define MH_DEBUG_REG12_GET_TC_MH_written(mh_debug_reg12) \ + ((mh_debug_reg12 & MH_DEBUG_REG12_TC_MH_written_MASK) >> MH_DEBUG_REG12_TC_MH_written_SHIFT) + +#define MH_DEBUG_REG12_SET_MH_TC_mcinfo(mh_debug_reg12_reg, mh_tc_mcinfo) \ + mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_MH_TC_mcinfo_MASK) | (mh_tc_mcinfo << MH_DEBUG_REG12_MH_TC_mcinfo_SHIFT) +#define MH_DEBUG_REG12_SET_MH_TC_mcinfo_send(mh_debug_reg12_reg, mh_tc_mcinfo_send) \ + mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_MH_TC_mcinfo_send_MASK) | (mh_tc_mcinfo_send << MH_DEBUG_REG12_MH_TC_mcinfo_send_SHIFT) +#define MH_DEBUG_REG12_SET_TC_MH_written(mh_debug_reg12_reg, tc_mh_written) \ + mh_debug_reg12_reg = (mh_debug_reg12_reg & ~MH_DEBUG_REG12_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG12_TC_MH_written_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg12_t { + unsigned int mh_tc_mcinfo : MH_DEBUG_REG12_MH_TC_mcinfo_SIZE; + unsigned int mh_tc_mcinfo_send : MH_DEBUG_REG12_MH_TC_mcinfo_send_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG12_TC_MH_written_SIZE; + unsigned int : 5; + } mh_debug_reg12_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg12_t { + unsigned int : 5; + unsigned int tc_mh_written : MH_DEBUG_REG12_TC_MH_written_SIZE; + unsigned int mh_tc_mcinfo_send : MH_DEBUG_REG12_MH_TC_mcinfo_send_SIZE; + unsigned int mh_tc_mcinfo : MH_DEBUG_REG12_MH_TC_mcinfo_SIZE; + } mh_debug_reg12_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg12_t f; +} mh_debug_reg12_u; + + +/* + * MH_DEBUG_REG13 struct + */ + +#define MH_DEBUG_REG13_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG13_TC_ROQ_SEND_SIZE 1 +#define MH_DEBUG_REG13_TC_ROQ_MASK_SIZE 2 +#define MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SIZE 27 + +#define MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT 2 +#define MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT 3 +#define MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT 5 + +#define MH_DEBUG_REG13_ALWAYS_ZERO_MASK 0x00000003 +#define MH_DEBUG_REG13_TC_ROQ_SEND_MASK 0x00000004 +#define MH_DEBUG_REG13_TC_ROQ_MASK_MASK 0x00000018 +#define MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG13_MASK \ + (MH_DEBUG_REG13_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG13_TC_ROQ_SEND_MASK | \ + MH_DEBUG_REG13_TC_ROQ_MASK_MASK | \ + MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK) + +#define MH_DEBUG_REG13(always_zero, tc_roq_send, tc_roq_mask, tc_roq_addr_31_5) \ + ((always_zero << MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT) | \ + (tc_roq_send << MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT) | \ + (tc_roq_mask << MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT) | \ + (tc_roq_addr_31_5 << MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT)) + +#define MH_DEBUG_REG13_GET_ALWAYS_ZERO(mh_debug_reg13) \ + ((mh_debug_reg13 & MH_DEBUG_REG13_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG13_GET_TC_ROQ_SEND(mh_debug_reg13) \ + ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_SEND_MASK) >> MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT) +#define MH_DEBUG_REG13_GET_TC_ROQ_MASK(mh_debug_reg13) \ + ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_MASK_MASK) >> MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT) +#define MH_DEBUG_REG13_GET_TC_ROQ_ADDR_31_5(mh_debug_reg13) \ + ((mh_debug_reg13 & MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK) >> MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT) + +#define MH_DEBUG_REG13_SET_ALWAYS_ZERO(mh_debug_reg13_reg, always_zero) \ + mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG13_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG13_SET_TC_ROQ_SEND(mh_debug_reg13_reg, tc_roq_send) \ + mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_SEND_MASK) | (tc_roq_send << MH_DEBUG_REG13_TC_ROQ_SEND_SHIFT) +#define MH_DEBUG_REG13_SET_TC_ROQ_MASK(mh_debug_reg13_reg, tc_roq_mask) \ + mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_MASK_MASK) | (tc_roq_mask << MH_DEBUG_REG13_TC_ROQ_MASK_SHIFT) +#define MH_DEBUG_REG13_SET_TC_ROQ_ADDR_31_5(mh_debug_reg13_reg, tc_roq_addr_31_5) \ + mh_debug_reg13_reg = (mh_debug_reg13_reg & ~MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_MASK) | (tc_roq_addr_31_5 << MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg13_t { + unsigned int always_zero : MH_DEBUG_REG13_ALWAYS_ZERO_SIZE; + unsigned int tc_roq_send : MH_DEBUG_REG13_TC_ROQ_SEND_SIZE; + unsigned int tc_roq_mask : MH_DEBUG_REG13_TC_ROQ_MASK_SIZE; + unsigned int tc_roq_addr_31_5 : MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SIZE; + } mh_debug_reg13_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg13_t { + unsigned int tc_roq_addr_31_5 : MH_DEBUG_REG13_TC_ROQ_ADDR_31_5_SIZE; + unsigned int tc_roq_mask : MH_DEBUG_REG13_TC_ROQ_MASK_SIZE; + unsigned int tc_roq_send : MH_DEBUG_REG13_TC_ROQ_SEND_SIZE; + unsigned int always_zero : MH_DEBUG_REG13_ALWAYS_ZERO_SIZE; + } mh_debug_reg13_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg13_t f; +} mh_debug_reg13_u; + + +/* + * MH_DEBUG_REG14 struct + */ + +#define MH_DEBUG_REG14_TC_ROQ_INFO_SIZE 25 +#define MH_DEBUG_REG14_TC_ROQ_SEND_SIZE 1 + +#define MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT 0 +#define MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT 25 + +#define MH_DEBUG_REG14_TC_ROQ_INFO_MASK 0x01ffffff +#define MH_DEBUG_REG14_TC_ROQ_SEND_MASK 0x02000000 + +#define MH_DEBUG_REG14_MASK \ + (MH_DEBUG_REG14_TC_ROQ_INFO_MASK | \ + MH_DEBUG_REG14_TC_ROQ_SEND_MASK) + +#define MH_DEBUG_REG14(tc_roq_info, tc_roq_send) \ + ((tc_roq_info << MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT) | \ + (tc_roq_send << MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT)) + +#define MH_DEBUG_REG14_GET_TC_ROQ_INFO(mh_debug_reg14) \ + ((mh_debug_reg14 & MH_DEBUG_REG14_TC_ROQ_INFO_MASK) >> MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT) +#define MH_DEBUG_REG14_GET_TC_ROQ_SEND(mh_debug_reg14) \ + ((mh_debug_reg14 & MH_DEBUG_REG14_TC_ROQ_SEND_MASK) >> MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT) + +#define MH_DEBUG_REG14_SET_TC_ROQ_INFO(mh_debug_reg14_reg, tc_roq_info) \ + mh_debug_reg14_reg = (mh_debug_reg14_reg & ~MH_DEBUG_REG14_TC_ROQ_INFO_MASK) | (tc_roq_info << MH_DEBUG_REG14_TC_ROQ_INFO_SHIFT) +#define MH_DEBUG_REG14_SET_TC_ROQ_SEND(mh_debug_reg14_reg, tc_roq_send) \ + mh_debug_reg14_reg = (mh_debug_reg14_reg & ~MH_DEBUG_REG14_TC_ROQ_SEND_MASK) | (tc_roq_send << MH_DEBUG_REG14_TC_ROQ_SEND_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg14_t { + unsigned int tc_roq_info : MH_DEBUG_REG14_TC_ROQ_INFO_SIZE; + unsigned int tc_roq_send : MH_DEBUG_REG14_TC_ROQ_SEND_SIZE; + unsigned int : 6; + } mh_debug_reg14_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg14_t { + unsigned int : 6; + unsigned int tc_roq_send : MH_DEBUG_REG14_TC_ROQ_SEND_SIZE; + unsigned int tc_roq_info : MH_DEBUG_REG14_TC_ROQ_INFO_SIZE; + } mh_debug_reg14_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg14_t f; +} mh_debug_reg14_u; + + +/* + * MH_DEBUG_REG15 struct + */ + +#define MH_DEBUG_REG15_ALWAYS_ZERO_SIZE 4 +#define MH_DEBUG_REG15_RB_MH_send_SIZE 1 +#define MH_DEBUG_REG15_RB_MH_addr_31_5_SIZE 27 + +#define MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG15_RB_MH_send_SHIFT 4 +#define MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT 5 + +#define MH_DEBUG_REG15_ALWAYS_ZERO_MASK 0x0000000f +#define MH_DEBUG_REG15_RB_MH_send_MASK 0x00000010 +#define MH_DEBUG_REG15_RB_MH_addr_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG15_MASK \ + (MH_DEBUG_REG15_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG15_RB_MH_send_MASK | \ + MH_DEBUG_REG15_RB_MH_addr_31_5_MASK) + +#define MH_DEBUG_REG15(always_zero, rb_mh_send, rb_mh_addr_31_5) \ + ((always_zero << MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT) | \ + (rb_mh_send << MH_DEBUG_REG15_RB_MH_send_SHIFT) | \ + (rb_mh_addr_31_5 << MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT)) + +#define MH_DEBUG_REG15_GET_ALWAYS_ZERO(mh_debug_reg15) \ + ((mh_debug_reg15 & MH_DEBUG_REG15_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG15_GET_RB_MH_send(mh_debug_reg15) \ + ((mh_debug_reg15 & MH_DEBUG_REG15_RB_MH_send_MASK) >> MH_DEBUG_REG15_RB_MH_send_SHIFT) +#define MH_DEBUG_REG15_GET_RB_MH_addr_31_5(mh_debug_reg15) \ + ((mh_debug_reg15 & MH_DEBUG_REG15_RB_MH_addr_31_5_MASK) >> MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT) + +#define MH_DEBUG_REG15_SET_ALWAYS_ZERO(mh_debug_reg15_reg, always_zero) \ + mh_debug_reg15_reg = (mh_debug_reg15_reg & ~MH_DEBUG_REG15_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG15_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG15_SET_RB_MH_send(mh_debug_reg15_reg, rb_mh_send) \ + mh_debug_reg15_reg = (mh_debug_reg15_reg & ~MH_DEBUG_REG15_RB_MH_send_MASK) | (rb_mh_send << MH_DEBUG_REG15_RB_MH_send_SHIFT) +#define MH_DEBUG_REG15_SET_RB_MH_addr_31_5(mh_debug_reg15_reg, rb_mh_addr_31_5) \ + mh_debug_reg15_reg = (mh_debug_reg15_reg & ~MH_DEBUG_REG15_RB_MH_addr_31_5_MASK) | (rb_mh_addr_31_5 << MH_DEBUG_REG15_RB_MH_addr_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg15_t { + unsigned int always_zero : MH_DEBUG_REG15_ALWAYS_ZERO_SIZE; + unsigned int rb_mh_send : MH_DEBUG_REG15_RB_MH_send_SIZE; + unsigned int rb_mh_addr_31_5 : MH_DEBUG_REG15_RB_MH_addr_31_5_SIZE; + } mh_debug_reg15_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg15_t { + unsigned int rb_mh_addr_31_5 : MH_DEBUG_REG15_RB_MH_addr_31_5_SIZE; + unsigned int rb_mh_send : MH_DEBUG_REG15_RB_MH_send_SIZE; + unsigned int always_zero : MH_DEBUG_REG15_ALWAYS_ZERO_SIZE; + } mh_debug_reg15_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg15_t f; +} mh_debug_reg15_u; + + +/* + * MH_DEBUG_REG16 struct + */ + +#define MH_DEBUG_REG16_RB_MH_data_31_0_SIZE 32 + +#define MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT 0 + +#define MH_DEBUG_REG16_RB_MH_data_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG16_MASK \ + (MH_DEBUG_REG16_RB_MH_data_31_0_MASK) + +#define MH_DEBUG_REG16(rb_mh_data_31_0) \ + ((rb_mh_data_31_0 << MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT)) + +#define MH_DEBUG_REG16_GET_RB_MH_data_31_0(mh_debug_reg16) \ + ((mh_debug_reg16 & MH_DEBUG_REG16_RB_MH_data_31_0_MASK) >> MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT) + +#define MH_DEBUG_REG16_SET_RB_MH_data_31_0(mh_debug_reg16_reg, rb_mh_data_31_0) \ + mh_debug_reg16_reg = (mh_debug_reg16_reg & ~MH_DEBUG_REG16_RB_MH_data_31_0_MASK) | (rb_mh_data_31_0 << MH_DEBUG_REG16_RB_MH_data_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg16_t { + unsigned int rb_mh_data_31_0 : MH_DEBUG_REG16_RB_MH_data_31_0_SIZE; + } mh_debug_reg16_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg16_t { + unsigned int rb_mh_data_31_0 : MH_DEBUG_REG16_RB_MH_data_31_0_SIZE; + } mh_debug_reg16_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg16_t f; +} mh_debug_reg16_u; + + +/* + * MH_DEBUG_REG17 struct + */ + +#define MH_DEBUG_REG17_RB_MH_data_63_32_SIZE 32 + +#define MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT 0 + +#define MH_DEBUG_REG17_RB_MH_data_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG17_MASK \ + (MH_DEBUG_REG17_RB_MH_data_63_32_MASK) + +#define MH_DEBUG_REG17(rb_mh_data_63_32) \ + ((rb_mh_data_63_32 << MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT)) + +#define MH_DEBUG_REG17_GET_RB_MH_data_63_32(mh_debug_reg17) \ + ((mh_debug_reg17 & MH_DEBUG_REG17_RB_MH_data_63_32_MASK) >> MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT) + +#define MH_DEBUG_REG17_SET_RB_MH_data_63_32(mh_debug_reg17_reg, rb_mh_data_63_32) \ + mh_debug_reg17_reg = (mh_debug_reg17_reg & ~MH_DEBUG_REG17_RB_MH_data_63_32_MASK) | (rb_mh_data_63_32 << MH_DEBUG_REG17_RB_MH_data_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg17_t { + unsigned int rb_mh_data_63_32 : MH_DEBUG_REG17_RB_MH_data_63_32_SIZE; + } mh_debug_reg17_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg17_t { + unsigned int rb_mh_data_63_32 : MH_DEBUG_REG17_RB_MH_data_63_32_SIZE; + } mh_debug_reg17_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg17_t f; +} mh_debug_reg17_u; + + +/* + * MH_DEBUG_REG18 struct + */ + +#define MH_DEBUG_REG18_ALWAYS_ZERO_SIZE 4 +#define MH_DEBUG_REG18_PA_MH_send_SIZE 1 +#define MH_DEBUG_REG18_PA_MH_addr_31_5_SIZE 27 + +#define MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG18_PA_MH_send_SHIFT 4 +#define MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT 5 + +#define MH_DEBUG_REG18_ALWAYS_ZERO_MASK 0x0000000f +#define MH_DEBUG_REG18_PA_MH_send_MASK 0x00000010 +#define MH_DEBUG_REG18_PA_MH_addr_31_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG18_MASK \ + (MH_DEBUG_REG18_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG18_PA_MH_send_MASK | \ + MH_DEBUG_REG18_PA_MH_addr_31_5_MASK) + +#define MH_DEBUG_REG18(always_zero, pa_mh_send, pa_mh_addr_31_5) \ + ((always_zero << MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT) | \ + (pa_mh_send << MH_DEBUG_REG18_PA_MH_send_SHIFT) | \ + (pa_mh_addr_31_5 << MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT)) + +#define MH_DEBUG_REG18_GET_ALWAYS_ZERO(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG18_GET_PA_MH_send(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_PA_MH_send_MASK) >> MH_DEBUG_REG18_PA_MH_send_SHIFT) +#define MH_DEBUG_REG18_GET_PA_MH_addr_31_5(mh_debug_reg18) \ + ((mh_debug_reg18 & MH_DEBUG_REG18_PA_MH_addr_31_5_MASK) >> MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT) + +#define MH_DEBUG_REG18_SET_ALWAYS_ZERO(mh_debug_reg18_reg, always_zero) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG18_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG18_SET_PA_MH_send(mh_debug_reg18_reg, pa_mh_send) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_PA_MH_send_MASK) | (pa_mh_send << MH_DEBUG_REG18_PA_MH_send_SHIFT) +#define MH_DEBUG_REG18_SET_PA_MH_addr_31_5(mh_debug_reg18_reg, pa_mh_addr_31_5) \ + mh_debug_reg18_reg = (mh_debug_reg18_reg & ~MH_DEBUG_REG18_PA_MH_addr_31_5_MASK) | (pa_mh_addr_31_5 << MH_DEBUG_REG18_PA_MH_addr_31_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg18_t { + unsigned int always_zero : MH_DEBUG_REG18_ALWAYS_ZERO_SIZE; + unsigned int pa_mh_send : MH_DEBUG_REG18_PA_MH_send_SIZE; + unsigned int pa_mh_addr_31_5 : MH_DEBUG_REG18_PA_MH_addr_31_5_SIZE; + } mh_debug_reg18_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg18_t { + unsigned int pa_mh_addr_31_5 : MH_DEBUG_REG18_PA_MH_addr_31_5_SIZE; + unsigned int pa_mh_send : MH_DEBUG_REG18_PA_MH_send_SIZE; + unsigned int always_zero : MH_DEBUG_REG18_ALWAYS_ZERO_SIZE; + } mh_debug_reg18_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg18_t f; +} mh_debug_reg18_u; + + +/* + * MH_DEBUG_REG19 struct + */ + +#define MH_DEBUG_REG19_PA_MH_data_31_0_SIZE 32 + +#define MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT 0 + +#define MH_DEBUG_REG19_PA_MH_data_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG19_MASK \ + (MH_DEBUG_REG19_PA_MH_data_31_0_MASK) + +#define MH_DEBUG_REG19(pa_mh_data_31_0) \ + ((pa_mh_data_31_0 << MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT)) + +#define MH_DEBUG_REG19_GET_PA_MH_data_31_0(mh_debug_reg19) \ + ((mh_debug_reg19 & MH_DEBUG_REG19_PA_MH_data_31_0_MASK) >> MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT) + +#define MH_DEBUG_REG19_SET_PA_MH_data_31_0(mh_debug_reg19_reg, pa_mh_data_31_0) \ + mh_debug_reg19_reg = (mh_debug_reg19_reg & ~MH_DEBUG_REG19_PA_MH_data_31_0_MASK) | (pa_mh_data_31_0 << MH_DEBUG_REG19_PA_MH_data_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg19_t { + unsigned int pa_mh_data_31_0 : MH_DEBUG_REG19_PA_MH_data_31_0_SIZE; + } mh_debug_reg19_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg19_t { + unsigned int pa_mh_data_31_0 : MH_DEBUG_REG19_PA_MH_data_31_0_SIZE; + } mh_debug_reg19_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg19_t f; +} mh_debug_reg19_u; + + +/* + * MH_DEBUG_REG20 struct + */ + +#define MH_DEBUG_REG20_PA_MH_data_63_32_SIZE 32 + +#define MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT 0 + +#define MH_DEBUG_REG20_PA_MH_data_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG20_MASK \ + (MH_DEBUG_REG20_PA_MH_data_63_32_MASK) + +#define MH_DEBUG_REG20(pa_mh_data_63_32) \ + ((pa_mh_data_63_32 << MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT)) + +#define MH_DEBUG_REG20_GET_PA_MH_data_63_32(mh_debug_reg20) \ + ((mh_debug_reg20 & MH_DEBUG_REG20_PA_MH_data_63_32_MASK) >> MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT) + +#define MH_DEBUG_REG20_SET_PA_MH_data_63_32(mh_debug_reg20_reg, pa_mh_data_63_32) \ + mh_debug_reg20_reg = (mh_debug_reg20_reg & ~MH_DEBUG_REG20_PA_MH_data_63_32_MASK) | (pa_mh_data_63_32 << MH_DEBUG_REG20_PA_MH_data_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg20_t { + unsigned int pa_mh_data_63_32 : MH_DEBUG_REG20_PA_MH_data_63_32_SIZE; + } mh_debug_reg20_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg20_t { + unsigned int pa_mh_data_63_32 : MH_DEBUG_REG20_PA_MH_data_63_32_SIZE; + } mh_debug_reg20_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg20_t f; +} mh_debug_reg20_u; + + +/* + * MH_DEBUG_REG21 struct + */ + +#define MH_DEBUG_REG21_AVALID_q_SIZE 1 +#define MH_DEBUG_REG21_AREADY_q_SIZE 1 +#define MH_DEBUG_REG21_AID_q_SIZE 3 +#define MH_DEBUG_REG21_ALEN_q_2_0_SIZE 3 +#define MH_DEBUG_REG21_ARVALID_q_SIZE 1 +#define MH_DEBUG_REG21_ARREADY_q_SIZE 1 +#define MH_DEBUG_REG21_ARID_q_SIZE 3 +#define MH_DEBUG_REG21_ARLEN_q_1_0_SIZE 2 +#define MH_DEBUG_REG21_RVALID_q_SIZE 1 +#define MH_DEBUG_REG21_RREADY_q_SIZE 1 +#define MH_DEBUG_REG21_RLAST_q_SIZE 1 +#define MH_DEBUG_REG21_RID_q_SIZE 3 +#define MH_DEBUG_REG21_WVALID_q_SIZE 1 +#define MH_DEBUG_REG21_WREADY_q_SIZE 1 +#define MH_DEBUG_REG21_WLAST_q_SIZE 1 +#define MH_DEBUG_REG21_WID_q_SIZE 3 +#define MH_DEBUG_REG21_BVALID_q_SIZE 1 +#define MH_DEBUG_REG21_BREADY_q_SIZE 1 +#define MH_DEBUG_REG21_BID_q_SIZE 3 + +#define MH_DEBUG_REG21_AVALID_q_SHIFT 0 +#define MH_DEBUG_REG21_AREADY_q_SHIFT 1 +#define MH_DEBUG_REG21_AID_q_SHIFT 2 +#define MH_DEBUG_REG21_ALEN_q_2_0_SHIFT 5 +#define MH_DEBUG_REG21_ARVALID_q_SHIFT 8 +#define MH_DEBUG_REG21_ARREADY_q_SHIFT 9 +#define MH_DEBUG_REG21_ARID_q_SHIFT 10 +#define MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT 13 +#define MH_DEBUG_REG21_RVALID_q_SHIFT 15 +#define MH_DEBUG_REG21_RREADY_q_SHIFT 16 +#define MH_DEBUG_REG21_RLAST_q_SHIFT 17 +#define MH_DEBUG_REG21_RID_q_SHIFT 18 +#define MH_DEBUG_REG21_WVALID_q_SHIFT 21 +#define MH_DEBUG_REG21_WREADY_q_SHIFT 22 +#define MH_DEBUG_REG21_WLAST_q_SHIFT 23 +#define MH_DEBUG_REG21_WID_q_SHIFT 24 +#define MH_DEBUG_REG21_BVALID_q_SHIFT 27 +#define MH_DEBUG_REG21_BREADY_q_SHIFT 28 +#define MH_DEBUG_REG21_BID_q_SHIFT 29 + +#define MH_DEBUG_REG21_AVALID_q_MASK 0x00000001 +#define MH_DEBUG_REG21_AREADY_q_MASK 0x00000002 +#define MH_DEBUG_REG21_AID_q_MASK 0x0000001c +#define MH_DEBUG_REG21_ALEN_q_2_0_MASK 0x000000e0 +#define MH_DEBUG_REG21_ARVALID_q_MASK 0x00000100 +#define MH_DEBUG_REG21_ARREADY_q_MASK 0x00000200 +#define MH_DEBUG_REG21_ARID_q_MASK 0x00001c00 +#define MH_DEBUG_REG21_ARLEN_q_1_0_MASK 0x00006000 +#define MH_DEBUG_REG21_RVALID_q_MASK 0x00008000 +#define MH_DEBUG_REG21_RREADY_q_MASK 0x00010000 +#define MH_DEBUG_REG21_RLAST_q_MASK 0x00020000 +#define MH_DEBUG_REG21_RID_q_MASK 0x001c0000 +#define MH_DEBUG_REG21_WVALID_q_MASK 0x00200000 +#define MH_DEBUG_REG21_WREADY_q_MASK 0x00400000 +#define MH_DEBUG_REG21_WLAST_q_MASK 0x00800000 +#define MH_DEBUG_REG21_WID_q_MASK 0x07000000 +#define MH_DEBUG_REG21_BVALID_q_MASK 0x08000000 +#define MH_DEBUG_REG21_BREADY_q_MASK 0x10000000 +#define MH_DEBUG_REG21_BID_q_MASK 0xe0000000 + +#define MH_DEBUG_REG21_MASK \ + (MH_DEBUG_REG21_AVALID_q_MASK | \ + MH_DEBUG_REG21_AREADY_q_MASK | \ + MH_DEBUG_REG21_AID_q_MASK | \ + MH_DEBUG_REG21_ALEN_q_2_0_MASK | \ + MH_DEBUG_REG21_ARVALID_q_MASK | \ + MH_DEBUG_REG21_ARREADY_q_MASK | \ + MH_DEBUG_REG21_ARID_q_MASK | \ + MH_DEBUG_REG21_ARLEN_q_1_0_MASK | \ + MH_DEBUG_REG21_RVALID_q_MASK | \ + MH_DEBUG_REG21_RREADY_q_MASK | \ + MH_DEBUG_REG21_RLAST_q_MASK | \ + MH_DEBUG_REG21_RID_q_MASK | \ + MH_DEBUG_REG21_WVALID_q_MASK | \ + MH_DEBUG_REG21_WREADY_q_MASK | \ + MH_DEBUG_REG21_WLAST_q_MASK | \ + MH_DEBUG_REG21_WID_q_MASK | \ + MH_DEBUG_REG21_BVALID_q_MASK | \ + MH_DEBUG_REG21_BREADY_q_MASK | \ + MH_DEBUG_REG21_BID_q_MASK) + +#define MH_DEBUG_REG21(avalid_q, aready_q, aid_q, alen_q_2_0, arvalid_q, arready_q, arid_q, arlen_q_1_0, rvalid_q, rready_q, rlast_q, rid_q, wvalid_q, wready_q, wlast_q, wid_q, bvalid_q, bready_q, bid_q) \ + ((avalid_q << MH_DEBUG_REG21_AVALID_q_SHIFT) | \ + (aready_q << MH_DEBUG_REG21_AREADY_q_SHIFT) | \ + (aid_q << MH_DEBUG_REG21_AID_q_SHIFT) | \ + (alen_q_2_0 << MH_DEBUG_REG21_ALEN_q_2_0_SHIFT) | \ + (arvalid_q << MH_DEBUG_REG21_ARVALID_q_SHIFT) | \ + (arready_q << MH_DEBUG_REG21_ARREADY_q_SHIFT) | \ + (arid_q << MH_DEBUG_REG21_ARID_q_SHIFT) | \ + (arlen_q_1_0 << MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT) | \ + (rvalid_q << MH_DEBUG_REG21_RVALID_q_SHIFT) | \ + (rready_q << MH_DEBUG_REG21_RREADY_q_SHIFT) | \ + (rlast_q << MH_DEBUG_REG21_RLAST_q_SHIFT) | \ + (rid_q << MH_DEBUG_REG21_RID_q_SHIFT) | \ + (wvalid_q << MH_DEBUG_REG21_WVALID_q_SHIFT) | \ + (wready_q << MH_DEBUG_REG21_WREADY_q_SHIFT) | \ + (wlast_q << MH_DEBUG_REG21_WLAST_q_SHIFT) | \ + (wid_q << MH_DEBUG_REG21_WID_q_SHIFT) | \ + (bvalid_q << MH_DEBUG_REG21_BVALID_q_SHIFT) | \ + (bready_q << MH_DEBUG_REG21_BREADY_q_SHIFT) | \ + (bid_q << MH_DEBUG_REG21_BID_q_SHIFT)) + +#define MH_DEBUG_REG21_GET_AVALID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_AVALID_q_MASK) >> MH_DEBUG_REG21_AVALID_q_SHIFT) +#define MH_DEBUG_REG21_GET_AREADY_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_AREADY_q_MASK) >> MH_DEBUG_REG21_AREADY_q_SHIFT) +#define MH_DEBUG_REG21_GET_AID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_AID_q_MASK) >> MH_DEBUG_REG21_AID_q_SHIFT) +#define MH_DEBUG_REG21_GET_ALEN_q_2_0(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_ALEN_q_2_0_MASK) >> MH_DEBUG_REG21_ALEN_q_2_0_SHIFT) +#define MH_DEBUG_REG21_GET_ARVALID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_ARVALID_q_MASK) >> MH_DEBUG_REG21_ARVALID_q_SHIFT) +#define MH_DEBUG_REG21_GET_ARREADY_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_ARREADY_q_MASK) >> MH_DEBUG_REG21_ARREADY_q_SHIFT) +#define MH_DEBUG_REG21_GET_ARID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_ARID_q_MASK) >> MH_DEBUG_REG21_ARID_q_SHIFT) +#define MH_DEBUG_REG21_GET_ARLEN_q_1_0(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_ARLEN_q_1_0_MASK) >> MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT) +#define MH_DEBUG_REG21_GET_RVALID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_RVALID_q_MASK) >> MH_DEBUG_REG21_RVALID_q_SHIFT) +#define MH_DEBUG_REG21_GET_RREADY_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_RREADY_q_MASK) >> MH_DEBUG_REG21_RREADY_q_SHIFT) +#define MH_DEBUG_REG21_GET_RLAST_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_RLAST_q_MASK) >> MH_DEBUG_REG21_RLAST_q_SHIFT) +#define MH_DEBUG_REG21_GET_RID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_RID_q_MASK) >> MH_DEBUG_REG21_RID_q_SHIFT) +#define MH_DEBUG_REG21_GET_WVALID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_WVALID_q_MASK) >> MH_DEBUG_REG21_WVALID_q_SHIFT) +#define MH_DEBUG_REG21_GET_WREADY_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_WREADY_q_MASK) >> MH_DEBUG_REG21_WREADY_q_SHIFT) +#define MH_DEBUG_REG21_GET_WLAST_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_WLAST_q_MASK) >> MH_DEBUG_REG21_WLAST_q_SHIFT) +#define MH_DEBUG_REG21_GET_WID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_WID_q_MASK) >> MH_DEBUG_REG21_WID_q_SHIFT) +#define MH_DEBUG_REG21_GET_BVALID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_BVALID_q_MASK) >> MH_DEBUG_REG21_BVALID_q_SHIFT) +#define MH_DEBUG_REG21_GET_BREADY_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_BREADY_q_MASK) >> MH_DEBUG_REG21_BREADY_q_SHIFT) +#define MH_DEBUG_REG21_GET_BID_q(mh_debug_reg21) \ + ((mh_debug_reg21 & MH_DEBUG_REG21_BID_q_MASK) >> MH_DEBUG_REG21_BID_q_SHIFT) + +#define MH_DEBUG_REG21_SET_AVALID_q(mh_debug_reg21_reg, avalid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_AVALID_q_MASK) | (avalid_q << MH_DEBUG_REG21_AVALID_q_SHIFT) +#define MH_DEBUG_REG21_SET_AREADY_q(mh_debug_reg21_reg, aready_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_AREADY_q_MASK) | (aready_q << MH_DEBUG_REG21_AREADY_q_SHIFT) +#define MH_DEBUG_REG21_SET_AID_q(mh_debug_reg21_reg, aid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_AID_q_MASK) | (aid_q << MH_DEBUG_REG21_AID_q_SHIFT) +#define MH_DEBUG_REG21_SET_ALEN_q_2_0(mh_debug_reg21_reg, alen_q_2_0) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ALEN_q_2_0_MASK) | (alen_q_2_0 << MH_DEBUG_REG21_ALEN_q_2_0_SHIFT) +#define MH_DEBUG_REG21_SET_ARVALID_q(mh_debug_reg21_reg, arvalid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARVALID_q_MASK) | (arvalid_q << MH_DEBUG_REG21_ARVALID_q_SHIFT) +#define MH_DEBUG_REG21_SET_ARREADY_q(mh_debug_reg21_reg, arready_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARREADY_q_MASK) | (arready_q << MH_DEBUG_REG21_ARREADY_q_SHIFT) +#define MH_DEBUG_REG21_SET_ARID_q(mh_debug_reg21_reg, arid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARID_q_MASK) | (arid_q << MH_DEBUG_REG21_ARID_q_SHIFT) +#define MH_DEBUG_REG21_SET_ARLEN_q_1_0(mh_debug_reg21_reg, arlen_q_1_0) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_ARLEN_q_1_0_MASK) | (arlen_q_1_0 << MH_DEBUG_REG21_ARLEN_q_1_0_SHIFT) +#define MH_DEBUG_REG21_SET_RVALID_q(mh_debug_reg21_reg, rvalid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RVALID_q_MASK) | (rvalid_q << MH_DEBUG_REG21_RVALID_q_SHIFT) +#define MH_DEBUG_REG21_SET_RREADY_q(mh_debug_reg21_reg, rready_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RREADY_q_MASK) | (rready_q << MH_DEBUG_REG21_RREADY_q_SHIFT) +#define MH_DEBUG_REG21_SET_RLAST_q(mh_debug_reg21_reg, rlast_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RLAST_q_MASK) | (rlast_q << MH_DEBUG_REG21_RLAST_q_SHIFT) +#define MH_DEBUG_REG21_SET_RID_q(mh_debug_reg21_reg, rid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_RID_q_MASK) | (rid_q << MH_DEBUG_REG21_RID_q_SHIFT) +#define MH_DEBUG_REG21_SET_WVALID_q(mh_debug_reg21_reg, wvalid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WVALID_q_MASK) | (wvalid_q << MH_DEBUG_REG21_WVALID_q_SHIFT) +#define MH_DEBUG_REG21_SET_WREADY_q(mh_debug_reg21_reg, wready_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WREADY_q_MASK) | (wready_q << MH_DEBUG_REG21_WREADY_q_SHIFT) +#define MH_DEBUG_REG21_SET_WLAST_q(mh_debug_reg21_reg, wlast_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG21_WLAST_q_SHIFT) +#define MH_DEBUG_REG21_SET_WID_q(mh_debug_reg21_reg, wid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_WID_q_MASK) | (wid_q << MH_DEBUG_REG21_WID_q_SHIFT) +#define MH_DEBUG_REG21_SET_BVALID_q(mh_debug_reg21_reg, bvalid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG21_BVALID_q_SHIFT) +#define MH_DEBUG_REG21_SET_BREADY_q(mh_debug_reg21_reg, bready_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG21_BREADY_q_SHIFT) +#define MH_DEBUG_REG21_SET_BID_q(mh_debug_reg21_reg, bid_q) \ + mh_debug_reg21_reg = (mh_debug_reg21_reg & ~MH_DEBUG_REG21_BID_q_MASK) | (bid_q << MH_DEBUG_REG21_BID_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg21_t { + unsigned int avalid_q : MH_DEBUG_REG21_AVALID_q_SIZE; + unsigned int aready_q : MH_DEBUG_REG21_AREADY_q_SIZE; + unsigned int aid_q : MH_DEBUG_REG21_AID_q_SIZE; + unsigned int alen_q_2_0 : MH_DEBUG_REG21_ALEN_q_2_0_SIZE; + unsigned int arvalid_q : MH_DEBUG_REG21_ARVALID_q_SIZE; + unsigned int arready_q : MH_DEBUG_REG21_ARREADY_q_SIZE; + unsigned int arid_q : MH_DEBUG_REG21_ARID_q_SIZE; + unsigned int arlen_q_1_0 : MH_DEBUG_REG21_ARLEN_q_1_0_SIZE; + unsigned int rvalid_q : MH_DEBUG_REG21_RVALID_q_SIZE; + unsigned int rready_q : MH_DEBUG_REG21_RREADY_q_SIZE; + unsigned int rlast_q : MH_DEBUG_REG21_RLAST_q_SIZE; + unsigned int rid_q : MH_DEBUG_REG21_RID_q_SIZE; + unsigned int wvalid_q : MH_DEBUG_REG21_WVALID_q_SIZE; + unsigned int wready_q : MH_DEBUG_REG21_WREADY_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG21_WLAST_q_SIZE; + unsigned int wid_q : MH_DEBUG_REG21_WID_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG21_BVALID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG21_BREADY_q_SIZE; + unsigned int bid_q : MH_DEBUG_REG21_BID_q_SIZE; + } mh_debug_reg21_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg21_t { + unsigned int bid_q : MH_DEBUG_REG21_BID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG21_BREADY_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG21_BVALID_q_SIZE; + unsigned int wid_q : MH_DEBUG_REG21_WID_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG21_WLAST_q_SIZE; + unsigned int wready_q : MH_DEBUG_REG21_WREADY_q_SIZE; + unsigned int wvalid_q : MH_DEBUG_REG21_WVALID_q_SIZE; + unsigned int rid_q : MH_DEBUG_REG21_RID_q_SIZE; + unsigned int rlast_q : MH_DEBUG_REG21_RLAST_q_SIZE; + unsigned int rready_q : MH_DEBUG_REG21_RREADY_q_SIZE; + unsigned int rvalid_q : MH_DEBUG_REG21_RVALID_q_SIZE; + unsigned int arlen_q_1_0 : MH_DEBUG_REG21_ARLEN_q_1_0_SIZE; + unsigned int arid_q : MH_DEBUG_REG21_ARID_q_SIZE; + unsigned int arready_q : MH_DEBUG_REG21_ARREADY_q_SIZE; + unsigned int arvalid_q : MH_DEBUG_REG21_ARVALID_q_SIZE; + unsigned int alen_q_2_0 : MH_DEBUG_REG21_ALEN_q_2_0_SIZE; + unsigned int aid_q : MH_DEBUG_REG21_AID_q_SIZE; + unsigned int aready_q : MH_DEBUG_REG21_AREADY_q_SIZE; + unsigned int avalid_q : MH_DEBUG_REG21_AVALID_q_SIZE; + } mh_debug_reg21_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg21_t f; +} mh_debug_reg21_u; + + +/* + * MH_DEBUG_REG22 struct + */ + +#define MH_DEBUG_REG22_AVALID_q_SIZE 1 +#define MH_DEBUG_REG22_AREADY_q_SIZE 1 +#define MH_DEBUG_REG22_AID_q_SIZE 3 +#define MH_DEBUG_REG22_ALEN_q_1_0_SIZE 2 +#define MH_DEBUG_REG22_ARVALID_q_SIZE 1 +#define MH_DEBUG_REG22_ARREADY_q_SIZE 1 +#define MH_DEBUG_REG22_ARID_q_SIZE 3 +#define MH_DEBUG_REG22_ARLEN_q_1_1_SIZE 1 +#define MH_DEBUG_REG22_WVALID_q_SIZE 1 +#define MH_DEBUG_REG22_WREADY_q_SIZE 1 +#define MH_DEBUG_REG22_WLAST_q_SIZE 1 +#define MH_DEBUG_REG22_WID_q_SIZE 3 +#define MH_DEBUG_REG22_WSTRB_q_SIZE 8 +#define MH_DEBUG_REG22_BVALID_q_SIZE 1 +#define MH_DEBUG_REG22_BREADY_q_SIZE 1 +#define MH_DEBUG_REG22_BID_q_SIZE 3 + +#define MH_DEBUG_REG22_AVALID_q_SHIFT 0 +#define MH_DEBUG_REG22_AREADY_q_SHIFT 1 +#define MH_DEBUG_REG22_AID_q_SHIFT 2 +#define MH_DEBUG_REG22_ALEN_q_1_0_SHIFT 5 +#define MH_DEBUG_REG22_ARVALID_q_SHIFT 7 +#define MH_DEBUG_REG22_ARREADY_q_SHIFT 8 +#define MH_DEBUG_REG22_ARID_q_SHIFT 9 +#define MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT 12 +#define MH_DEBUG_REG22_WVALID_q_SHIFT 13 +#define MH_DEBUG_REG22_WREADY_q_SHIFT 14 +#define MH_DEBUG_REG22_WLAST_q_SHIFT 15 +#define MH_DEBUG_REG22_WID_q_SHIFT 16 +#define MH_DEBUG_REG22_WSTRB_q_SHIFT 19 +#define MH_DEBUG_REG22_BVALID_q_SHIFT 27 +#define MH_DEBUG_REG22_BREADY_q_SHIFT 28 +#define MH_DEBUG_REG22_BID_q_SHIFT 29 + +#define MH_DEBUG_REG22_AVALID_q_MASK 0x00000001 +#define MH_DEBUG_REG22_AREADY_q_MASK 0x00000002 +#define MH_DEBUG_REG22_AID_q_MASK 0x0000001c +#define MH_DEBUG_REG22_ALEN_q_1_0_MASK 0x00000060 +#define MH_DEBUG_REG22_ARVALID_q_MASK 0x00000080 +#define MH_DEBUG_REG22_ARREADY_q_MASK 0x00000100 +#define MH_DEBUG_REG22_ARID_q_MASK 0x00000e00 +#define MH_DEBUG_REG22_ARLEN_q_1_1_MASK 0x00001000 +#define MH_DEBUG_REG22_WVALID_q_MASK 0x00002000 +#define MH_DEBUG_REG22_WREADY_q_MASK 0x00004000 +#define MH_DEBUG_REG22_WLAST_q_MASK 0x00008000 +#define MH_DEBUG_REG22_WID_q_MASK 0x00070000 +#define MH_DEBUG_REG22_WSTRB_q_MASK 0x07f80000 +#define MH_DEBUG_REG22_BVALID_q_MASK 0x08000000 +#define MH_DEBUG_REG22_BREADY_q_MASK 0x10000000 +#define MH_DEBUG_REG22_BID_q_MASK 0xe0000000 + +#define MH_DEBUG_REG22_MASK \ + (MH_DEBUG_REG22_AVALID_q_MASK | \ + MH_DEBUG_REG22_AREADY_q_MASK | \ + MH_DEBUG_REG22_AID_q_MASK | \ + MH_DEBUG_REG22_ALEN_q_1_0_MASK | \ + MH_DEBUG_REG22_ARVALID_q_MASK | \ + MH_DEBUG_REG22_ARREADY_q_MASK | \ + MH_DEBUG_REG22_ARID_q_MASK | \ + MH_DEBUG_REG22_ARLEN_q_1_1_MASK | \ + MH_DEBUG_REG22_WVALID_q_MASK | \ + MH_DEBUG_REG22_WREADY_q_MASK | \ + MH_DEBUG_REG22_WLAST_q_MASK | \ + MH_DEBUG_REG22_WID_q_MASK | \ + MH_DEBUG_REG22_WSTRB_q_MASK | \ + MH_DEBUG_REG22_BVALID_q_MASK | \ + MH_DEBUG_REG22_BREADY_q_MASK | \ + MH_DEBUG_REG22_BID_q_MASK) + +#define MH_DEBUG_REG22(avalid_q, aready_q, aid_q, alen_q_1_0, arvalid_q, arready_q, arid_q, arlen_q_1_1, wvalid_q, wready_q, wlast_q, wid_q, wstrb_q, bvalid_q, bready_q, bid_q) \ + ((avalid_q << MH_DEBUG_REG22_AVALID_q_SHIFT) | \ + (aready_q << MH_DEBUG_REG22_AREADY_q_SHIFT) | \ + (aid_q << MH_DEBUG_REG22_AID_q_SHIFT) | \ + (alen_q_1_0 << MH_DEBUG_REG22_ALEN_q_1_0_SHIFT) | \ + (arvalid_q << MH_DEBUG_REG22_ARVALID_q_SHIFT) | \ + (arready_q << MH_DEBUG_REG22_ARREADY_q_SHIFT) | \ + (arid_q << MH_DEBUG_REG22_ARID_q_SHIFT) | \ + (arlen_q_1_1 << MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT) | \ + (wvalid_q << MH_DEBUG_REG22_WVALID_q_SHIFT) | \ + (wready_q << MH_DEBUG_REG22_WREADY_q_SHIFT) | \ + (wlast_q << MH_DEBUG_REG22_WLAST_q_SHIFT) | \ + (wid_q << MH_DEBUG_REG22_WID_q_SHIFT) | \ + (wstrb_q << MH_DEBUG_REG22_WSTRB_q_SHIFT) | \ + (bvalid_q << MH_DEBUG_REG22_BVALID_q_SHIFT) | \ + (bready_q << MH_DEBUG_REG22_BREADY_q_SHIFT) | \ + (bid_q << MH_DEBUG_REG22_BID_q_SHIFT)) + +#define MH_DEBUG_REG22_GET_AVALID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_AVALID_q_MASK) >> MH_DEBUG_REG22_AVALID_q_SHIFT) +#define MH_DEBUG_REG22_GET_AREADY_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_AREADY_q_MASK) >> MH_DEBUG_REG22_AREADY_q_SHIFT) +#define MH_DEBUG_REG22_GET_AID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_AID_q_MASK) >> MH_DEBUG_REG22_AID_q_SHIFT) +#define MH_DEBUG_REG22_GET_ALEN_q_1_0(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_ALEN_q_1_0_MASK) >> MH_DEBUG_REG22_ALEN_q_1_0_SHIFT) +#define MH_DEBUG_REG22_GET_ARVALID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_ARVALID_q_MASK) >> MH_DEBUG_REG22_ARVALID_q_SHIFT) +#define MH_DEBUG_REG22_GET_ARREADY_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_ARREADY_q_MASK) >> MH_DEBUG_REG22_ARREADY_q_SHIFT) +#define MH_DEBUG_REG22_GET_ARID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_ARID_q_MASK) >> MH_DEBUG_REG22_ARID_q_SHIFT) +#define MH_DEBUG_REG22_GET_ARLEN_q_1_1(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_ARLEN_q_1_1_MASK) >> MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT) +#define MH_DEBUG_REG22_GET_WVALID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_WVALID_q_MASK) >> MH_DEBUG_REG22_WVALID_q_SHIFT) +#define MH_DEBUG_REG22_GET_WREADY_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_WREADY_q_MASK) >> MH_DEBUG_REG22_WREADY_q_SHIFT) +#define MH_DEBUG_REG22_GET_WLAST_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_WLAST_q_MASK) >> MH_DEBUG_REG22_WLAST_q_SHIFT) +#define MH_DEBUG_REG22_GET_WID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_WID_q_MASK) >> MH_DEBUG_REG22_WID_q_SHIFT) +#define MH_DEBUG_REG22_GET_WSTRB_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_WSTRB_q_MASK) >> MH_DEBUG_REG22_WSTRB_q_SHIFT) +#define MH_DEBUG_REG22_GET_BVALID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_BVALID_q_MASK) >> MH_DEBUG_REG22_BVALID_q_SHIFT) +#define MH_DEBUG_REG22_GET_BREADY_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_BREADY_q_MASK) >> MH_DEBUG_REG22_BREADY_q_SHIFT) +#define MH_DEBUG_REG22_GET_BID_q(mh_debug_reg22) \ + ((mh_debug_reg22 & MH_DEBUG_REG22_BID_q_MASK) >> MH_DEBUG_REG22_BID_q_SHIFT) + +#define MH_DEBUG_REG22_SET_AVALID_q(mh_debug_reg22_reg, avalid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_AVALID_q_MASK) | (avalid_q << MH_DEBUG_REG22_AVALID_q_SHIFT) +#define MH_DEBUG_REG22_SET_AREADY_q(mh_debug_reg22_reg, aready_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_AREADY_q_MASK) | (aready_q << MH_DEBUG_REG22_AREADY_q_SHIFT) +#define MH_DEBUG_REG22_SET_AID_q(mh_debug_reg22_reg, aid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_AID_q_MASK) | (aid_q << MH_DEBUG_REG22_AID_q_SHIFT) +#define MH_DEBUG_REG22_SET_ALEN_q_1_0(mh_debug_reg22_reg, alen_q_1_0) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ALEN_q_1_0_MASK) | (alen_q_1_0 << MH_DEBUG_REG22_ALEN_q_1_0_SHIFT) +#define MH_DEBUG_REG22_SET_ARVALID_q(mh_debug_reg22_reg, arvalid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARVALID_q_MASK) | (arvalid_q << MH_DEBUG_REG22_ARVALID_q_SHIFT) +#define MH_DEBUG_REG22_SET_ARREADY_q(mh_debug_reg22_reg, arready_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARREADY_q_MASK) | (arready_q << MH_DEBUG_REG22_ARREADY_q_SHIFT) +#define MH_DEBUG_REG22_SET_ARID_q(mh_debug_reg22_reg, arid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARID_q_MASK) | (arid_q << MH_DEBUG_REG22_ARID_q_SHIFT) +#define MH_DEBUG_REG22_SET_ARLEN_q_1_1(mh_debug_reg22_reg, arlen_q_1_1) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_ARLEN_q_1_1_MASK) | (arlen_q_1_1 << MH_DEBUG_REG22_ARLEN_q_1_1_SHIFT) +#define MH_DEBUG_REG22_SET_WVALID_q(mh_debug_reg22_reg, wvalid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WVALID_q_MASK) | (wvalid_q << MH_DEBUG_REG22_WVALID_q_SHIFT) +#define MH_DEBUG_REG22_SET_WREADY_q(mh_debug_reg22_reg, wready_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WREADY_q_MASK) | (wready_q << MH_DEBUG_REG22_WREADY_q_SHIFT) +#define MH_DEBUG_REG22_SET_WLAST_q(mh_debug_reg22_reg, wlast_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG22_WLAST_q_SHIFT) +#define MH_DEBUG_REG22_SET_WID_q(mh_debug_reg22_reg, wid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WID_q_MASK) | (wid_q << MH_DEBUG_REG22_WID_q_SHIFT) +#define MH_DEBUG_REG22_SET_WSTRB_q(mh_debug_reg22_reg, wstrb_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_WSTRB_q_MASK) | (wstrb_q << MH_DEBUG_REG22_WSTRB_q_SHIFT) +#define MH_DEBUG_REG22_SET_BVALID_q(mh_debug_reg22_reg, bvalid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG22_BVALID_q_SHIFT) +#define MH_DEBUG_REG22_SET_BREADY_q(mh_debug_reg22_reg, bready_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG22_BREADY_q_SHIFT) +#define MH_DEBUG_REG22_SET_BID_q(mh_debug_reg22_reg, bid_q) \ + mh_debug_reg22_reg = (mh_debug_reg22_reg & ~MH_DEBUG_REG22_BID_q_MASK) | (bid_q << MH_DEBUG_REG22_BID_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg22_t { + unsigned int avalid_q : MH_DEBUG_REG22_AVALID_q_SIZE; + unsigned int aready_q : MH_DEBUG_REG22_AREADY_q_SIZE; + unsigned int aid_q : MH_DEBUG_REG22_AID_q_SIZE; + unsigned int alen_q_1_0 : MH_DEBUG_REG22_ALEN_q_1_0_SIZE; + unsigned int arvalid_q : MH_DEBUG_REG22_ARVALID_q_SIZE; + unsigned int arready_q : MH_DEBUG_REG22_ARREADY_q_SIZE; + unsigned int arid_q : MH_DEBUG_REG22_ARID_q_SIZE; + unsigned int arlen_q_1_1 : MH_DEBUG_REG22_ARLEN_q_1_1_SIZE; + unsigned int wvalid_q : MH_DEBUG_REG22_WVALID_q_SIZE; + unsigned int wready_q : MH_DEBUG_REG22_WREADY_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG22_WLAST_q_SIZE; + unsigned int wid_q : MH_DEBUG_REG22_WID_q_SIZE; + unsigned int wstrb_q : MH_DEBUG_REG22_WSTRB_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG22_BVALID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG22_BREADY_q_SIZE; + unsigned int bid_q : MH_DEBUG_REG22_BID_q_SIZE; + } mh_debug_reg22_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg22_t { + unsigned int bid_q : MH_DEBUG_REG22_BID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG22_BREADY_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG22_BVALID_q_SIZE; + unsigned int wstrb_q : MH_DEBUG_REG22_WSTRB_q_SIZE; + unsigned int wid_q : MH_DEBUG_REG22_WID_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG22_WLAST_q_SIZE; + unsigned int wready_q : MH_DEBUG_REG22_WREADY_q_SIZE; + unsigned int wvalid_q : MH_DEBUG_REG22_WVALID_q_SIZE; + unsigned int arlen_q_1_1 : MH_DEBUG_REG22_ARLEN_q_1_1_SIZE; + unsigned int arid_q : MH_DEBUG_REG22_ARID_q_SIZE; + unsigned int arready_q : MH_DEBUG_REG22_ARREADY_q_SIZE; + unsigned int arvalid_q : MH_DEBUG_REG22_ARVALID_q_SIZE; + unsigned int alen_q_1_0 : MH_DEBUG_REG22_ALEN_q_1_0_SIZE; + unsigned int aid_q : MH_DEBUG_REG22_AID_q_SIZE; + unsigned int aready_q : MH_DEBUG_REG22_AREADY_q_SIZE; + unsigned int avalid_q : MH_DEBUG_REG22_AVALID_q_SIZE; + } mh_debug_reg22_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg22_t f; +} mh_debug_reg22_u; + + +/* + * MH_DEBUG_REG23 struct + */ + +#define MH_DEBUG_REG23_ARC_CTRL_RE_q_SIZE 1 +#define MH_DEBUG_REG23_CTRL_ARC_ID_SIZE 3 +#define MH_DEBUG_REG23_CTRL_ARC_PAD_SIZE 28 + +#define MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT 0 +#define MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT 1 +#define MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT 4 + +#define MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK 0x00000001 +#define MH_DEBUG_REG23_CTRL_ARC_ID_MASK 0x0000000e +#define MH_DEBUG_REG23_CTRL_ARC_PAD_MASK 0xfffffff0 + +#define MH_DEBUG_REG23_MASK \ + (MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK | \ + MH_DEBUG_REG23_CTRL_ARC_ID_MASK | \ + MH_DEBUG_REG23_CTRL_ARC_PAD_MASK) + +#define MH_DEBUG_REG23(arc_ctrl_re_q, ctrl_arc_id, ctrl_arc_pad) \ + ((arc_ctrl_re_q << MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT) | \ + (ctrl_arc_id << MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT) | \ + (ctrl_arc_pad << MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT)) + +#define MH_DEBUG_REG23_GET_ARC_CTRL_RE_q(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG23_GET_CTRL_ARC_ID(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_CTRL_ARC_ID_MASK) >> MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT) +#define MH_DEBUG_REG23_GET_CTRL_ARC_PAD(mh_debug_reg23) \ + ((mh_debug_reg23 & MH_DEBUG_REG23_CTRL_ARC_PAD_MASK) >> MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT) + +#define MH_DEBUG_REG23_SET_ARC_CTRL_RE_q(mh_debug_reg23_reg, arc_ctrl_re_q) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_ARC_CTRL_RE_q_MASK) | (arc_ctrl_re_q << MH_DEBUG_REG23_ARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG23_SET_CTRL_ARC_ID(mh_debug_reg23_reg, ctrl_arc_id) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_CTRL_ARC_ID_MASK) | (ctrl_arc_id << MH_DEBUG_REG23_CTRL_ARC_ID_SHIFT) +#define MH_DEBUG_REG23_SET_CTRL_ARC_PAD(mh_debug_reg23_reg, ctrl_arc_pad) \ + mh_debug_reg23_reg = (mh_debug_reg23_reg & ~MH_DEBUG_REG23_CTRL_ARC_PAD_MASK) | (ctrl_arc_pad << MH_DEBUG_REG23_CTRL_ARC_PAD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg23_t { + unsigned int arc_ctrl_re_q : MH_DEBUG_REG23_ARC_CTRL_RE_q_SIZE; + unsigned int ctrl_arc_id : MH_DEBUG_REG23_CTRL_ARC_ID_SIZE; + unsigned int ctrl_arc_pad : MH_DEBUG_REG23_CTRL_ARC_PAD_SIZE; + } mh_debug_reg23_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg23_t { + unsigned int ctrl_arc_pad : MH_DEBUG_REG23_CTRL_ARC_PAD_SIZE; + unsigned int ctrl_arc_id : MH_DEBUG_REG23_CTRL_ARC_ID_SIZE; + unsigned int arc_ctrl_re_q : MH_DEBUG_REG23_ARC_CTRL_RE_q_SIZE; + } mh_debug_reg23_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg23_t f; +} mh_debug_reg23_u; + + +/* + * MH_DEBUG_REG24 struct + */ + +#define MH_DEBUG_REG24_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG24_REG_A_SIZE 14 +#define MH_DEBUG_REG24_REG_RE_SIZE 1 +#define MH_DEBUG_REG24_REG_WE_SIZE 1 +#define MH_DEBUG_REG24_BLOCK_RS_SIZE 1 + +#define MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT 0 +#define MH_DEBUG_REG24_REG_A_SHIFT 2 +#define MH_DEBUG_REG24_REG_RE_SHIFT 16 +#define MH_DEBUG_REG24_REG_WE_SHIFT 17 +#define MH_DEBUG_REG24_BLOCK_RS_SHIFT 18 + +#define MH_DEBUG_REG24_ALWAYS_ZERO_MASK 0x00000003 +#define MH_DEBUG_REG24_REG_A_MASK 0x0000fffc +#define MH_DEBUG_REG24_REG_RE_MASK 0x00010000 +#define MH_DEBUG_REG24_REG_WE_MASK 0x00020000 +#define MH_DEBUG_REG24_BLOCK_RS_MASK 0x00040000 + +#define MH_DEBUG_REG24_MASK \ + (MH_DEBUG_REG24_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG24_REG_A_MASK | \ + MH_DEBUG_REG24_REG_RE_MASK | \ + MH_DEBUG_REG24_REG_WE_MASK | \ + MH_DEBUG_REG24_BLOCK_RS_MASK) + +#define MH_DEBUG_REG24(always_zero, reg_a, reg_re, reg_we, block_rs) \ + ((always_zero << MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT) | \ + (reg_a << MH_DEBUG_REG24_REG_A_SHIFT) | \ + (reg_re << MH_DEBUG_REG24_REG_RE_SHIFT) | \ + (reg_we << MH_DEBUG_REG24_REG_WE_SHIFT) | \ + (block_rs << MH_DEBUG_REG24_BLOCK_RS_SHIFT)) + +#define MH_DEBUG_REG24_GET_ALWAYS_ZERO(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG24_GET_REG_A(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_REG_A_MASK) >> MH_DEBUG_REG24_REG_A_SHIFT) +#define MH_DEBUG_REG24_GET_REG_RE(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_REG_RE_MASK) >> MH_DEBUG_REG24_REG_RE_SHIFT) +#define MH_DEBUG_REG24_GET_REG_WE(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_REG_WE_MASK) >> MH_DEBUG_REG24_REG_WE_SHIFT) +#define MH_DEBUG_REG24_GET_BLOCK_RS(mh_debug_reg24) \ + ((mh_debug_reg24 & MH_DEBUG_REG24_BLOCK_RS_MASK) >> MH_DEBUG_REG24_BLOCK_RS_SHIFT) + +#define MH_DEBUG_REG24_SET_ALWAYS_ZERO(mh_debug_reg24_reg, always_zero) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG24_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG24_SET_REG_A(mh_debug_reg24_reg, reg_a) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_REG_A_MASK) | (reg_a << MH_DEBUG_REG24_REG_A_SHIFT) +#define MH_DEBUG_REG24_SET_REG_RE(mh_debug_reg24_reg, reg_re) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_REG_RE_MASK) | (reg_re << MH_DEBUG_REG24_REG_RE_SHIFT) +#define MH_DEBUG_REG24_SET_REG_WE(mh_debug_reg24_reg, reg_we) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_REG_WE_MASK) | (reg_we << MH_DEBUG_REG24_REG_WE_SHIFT) +#define MH_DEBUG_REG24_SET_BLOCK_RS(mh_debug_reg24_reg, block_rs) \ + mh_debug_reg24_reg = (mh_debug_reg24_reg & ~MH_DEBUG_REG24_BLOCK_RS_MASK) | (block_rs << MH_DEBUG_REG24_BLOCK_RS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg24_t { + unsigned int always_zero : MH_DEBUG_REG24_ALWAYS_ZERO_SIZE; + unsigned int reg_a : MH_DEBUG_REG24_REG_A_SIZE; + unsigned int reg_re : MH_DEBUG_REG24_REG_RE_SIZE; + unsigned int reg_we : MH_DEBUG_REG24_REG_WE_SIZE; + unsigned int block_rs : MH_DEBUG_REG24_BLOCK_RS_SIZE; + unsigned int : 13; + } mh_debug_reg24_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg24_t { + unsigned int : 13; + unsigned int block_rs : MH_DEBUG_REG24_BLOCK_RS_SIZE; + unsigned int reg_we : MH_DEBUG_REG24_REG_WE_SIZE; + unsigned int reg_re : MH_DEBUG_REG24_REG_RE_SIZE; + unsigned int reg_a : MH_DEBUG_REG24_REG_A_SIZE; + unsigned int always_zero : MH_DEBUG_REG24_ALWAYS_ZERO_SIZE; + } mh_debug_reg24_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg24_t f; +} mh_debug_reg24_u; + + +/* + * MH_DEBUG_REG25 struct + */ + +#define MH_DEBUG_REG25_REG_WD_SIZE 32 + +#define MH_DEBUG_REG25_REG_WD_SHIFT 0 + +#define MH_DEBUG_REG25_REG_WD_MASK 0xffffffff + +#define MH_DEBUG_REG25_MASK \ + (MH_DEBUG_REG25_REG_WD_MASK) + +#define MH_DEBUG_REG25(reg_wd) \ + ((reg_wd << MH_DEBUG_REG25_REG_WD_SHIFT)) + +#define MH_DEBUG_REG25_GET_REG_WD(mh_debug_reg25) \ + ((mh_debug_reg25 & MH_DEBUG_REG25_REG_WD_MASK) >> MH_DEBUG_REG25_REG_WD_SHIFT) + +#define MH_DEBUG_REG25_SET_REG_WD(mh_debug_reg25_reg, reg_wd) \ + mh_debug_reg25_reg = (mh_debug_reg25_reg & ~MH_DEBUG_REG25_REG_WD_MASK) | (reg_wd << MH_DEBUG_REG25_REG_WD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg25_t { + unsigned int reg_wd : MH_DEBUG_REG25_REG_WD_SIZE; + } mh_debug_reg25_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg25_t { + unsigned int reg_wd : MH_DEBUG_REG25_REG_WD_SIZE; + } mh_debug_reg25_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg25_t f; +} mh_debug_reg25_u; + + +/* + * MH_DEBUG_REG26 struct + */ + +#define MH_DEBUG_REG26_MH_RBBM_busy_SIZE 1 +#define MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SIZE 1 +#define MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SIZE 1 +#define MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SIZE 1 +#define MH_DEBUG_REG26_GAT_CLK_ENA_SIZE 1 +#define MH_DEBUG_REG26_RBBM_MH_clk_en_override_SIZE 1 +#define MH_DEBUG_REG26_CNT_q_SIZE 6 +#define MH_DEBUG_REG26_TCD_EMPTY_q_SIZE 1 +#define MH_DEBUG_REG26_TC_ROQ_EMPTY_SIZE 1 +#define MH_DEBUG_REG26_MH_BUSY_d_SIZE 1 +#define MH_DEBUG_REG26_ANY_CLNT_BUSY_SIZE 1 +#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE 1 +#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE 1 +#define MH_DEBUG_REG26_CP_SEND_q_SIZE 1 +#define MH_DEBUG_REG26_CP_RTR_q_SIZE 1 +#define MH_DEBUG_REG26_VGT_SEND_q_SIZE 1 +#define MH_DEBUG_REG26_VGT_RTR_q_SIZE 1 +#define MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE 1 +#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE 1 +#define MH_DEBUG_REG26_RB_SEND_q_SIZE 1 +#define MH_DEBUG_REG26_RB_RTR_q_SIZE 1 +#define MH_DEBUG_REG26_PA_SEND_q_SIZE 1 +#define MH_DEBUG_REG26_PA_RTR_q_SIZE 1 +#define MH_DEBUG_REG26_RDC_VALID_SIZE 1 +#define MH_DEBUG_REG26_RDC_RLAST_SIZE 1 +#define MH_DEBUG_REG26_TLBMISS_VALID_SIZE 1 +#define MH_DEBUG_REG26_BRC_VALID_SIZE 1 + +#define MH_DEBUG_REG26_MH_RBBM_busy_SHIFT 0 +#define MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT 1 +#define MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT 2 +#define MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT 3 +#define MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT 4 +#define MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT 5 +#define MH_DEBUG_REG26_CNT_q_SHIFT 6 +#define MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT 12 +#define MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT 13 +#define MH_DEBUG_REG26_MH_BUSY_d_SHIFT 14 +#define MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT 15 +#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT 16 +#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT 17 +#define MH_DEBUG_REG26_CP_SEND_q_SHIFT 18 +#define MH_DEBUG_REG26_CP_RTR_q_SHIFT 19 +#define MH_DEBUG_REG26_VGT_SEND_q_SHIFT 20 +#define MH_DEBUG_REG26_VGT_RTR_q_SHIFT 21 +#define MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT 22 +#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT 23 +#define MH_DEBUG_REG26_RB_SEND_q_SHIFT 24 +#define MH_DEBUG_REG26_RB_RTR_q_SHIFT 25 +#define MH_DEBUG_REG26_PA_SEND_q_SHIFT 26 +#define MH_DEBUG_REG26_PA_RTR_q_SHIFT 27 +#define MH_DEBUG_REG26_RDC_VALID_SHIFT 28 +#define MH_DEBUG_REG26_RDC_RLAST_SHIFT 29 +#define MH_DEBUG_REG26_TLBMISS_VALID_SHIFT 30 +#define MH_DEBUG_REG26_BRC_VALID_SHIFT 31 + +#define MH_DEBUG_REG26_MH_RBBM_busy_MASK 0x00000001 +#define MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK 0x00000002 +#define MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK 0x00000004 +#define MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK 0x00000008 +#define MH_DEBUG_REG26_GAT_CLK_ENA_MASK 0x00000010 +#define MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK 0x00000020 +#define MH_DEBUG_REG26_CNT_q_MASK 0x00000fc0 +#define MH_DEBUG_REG26_TCD_EMPTY_q_MASK 0x00001000 +#define MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK 0x00002000 +#define MH_DEBUG_REG26_MH_BUSY_d_MASK 0x00004000 +#define MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK 0x00008000 +#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00010000 +#define MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK 0x00020000 +#define MH_DEBUG_REG26_CP_SEND_q_MASK 0x00040000 +#define MH_DEBUG_REG26_CP_RTR_q_MASK 0x00080000 +#define MH_DEBUG_REG26_VGT_SEND_q_MASK 0x00100000 +#define MH_DEBUG_REG26_VGT_RTR_q_MASK 0x00200000 +#define MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK 0x00400000 +#define MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK 0x00800000 +#define MH_DEBUG_REG26_RB_SEND_q_MASK 0x01000000 +#define MH_DEBUG_REG26_RB_RTR_q_MASK 0x02000000 +#define MH_DEBUG_REG26_PA_SEND_q_MASK 0x04000000 +#define MH_DEBUG_REG26_PA_RTR_q_MASK 0x08000000 +#define MH_DEBUG_REG26_RDC_VALID_MASK 0x10000000 +#define MH_DEBUG_REG26_RDC_RLAST_MASK 0x20000000 +#define MH_DEBUG_REG26_TLBMISS_VALID_MASK 0x40000000 +#define MH_DEBUG_REG26_BRC_VALID_MASK 0x80000000 + +#define MH_DEBUG_REG26_MASK \ + (MH_DEBUG_REG26_MH_RBBM_busy_MASK | \ + MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK | \ + MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK | \ + MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK | \ + MH_DEBUG_REG26_GAT_CLK_ENA_MASK | \ + MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK | \ + MH_DEBUG_REG26_CNT_q_MASK | \ + MH_DEBUG_REG26_TCD_EMPTY_q_MASK | \ + MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK | \ + MH_DEBUG_REG26_MH_BUSY_d_MASK | \ + MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK | \ + MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK | \ + MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK | \ + MH_DEBUG_REG26_CP_SEND_q_MASK | \ + MH_DEBUG_REG26_CP_RTR_q_MASK | \ + MH_DEBUG_REG26_VGT_SEND_q_MASK | \ + MH_DEBUG_REG26_VGT_RTR_q_MASK | \ + MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK | \ + MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK | \ + MH_DEBUG_REG26_RB_SEND_q_MASK | \ + MH_DEBUG_REG26_RB_RTR_q_MASK | \ + MH_DEBUG_REG26_PA_SEND_q_MASK | \ + MH_DEBUG_REG26_PA_RTR_q_MASK | \ + MH_DEBUG_REG26_RDC_VALID_MASK | \ + MH_DEBUG_REG26_RDC_RLAST_MASK | \ + MH_DEBUG_REG26_TLBMISS_VALID_MASK | \ + MH_DEBUG_REG26_BRC_VALID_MASK) + +#define MH_DEBUG_REG26(mh_rbbm_busy, mh_cib_mh_clk_en_int, mh_cib_mmu_clk_en_int, mh_cib_tcroq_clk_en_int, gat_clk_ena, rbbm_mh_clk_en_override, cnt_q, tcd_empty_q, tc_roq_empty, mh_busy_d, any_clnt_busy, mh_mmu_invalidate_invalidate_all, mh_mmu_invalidate_invalidate_tc, cp_send_q, cp_rtr_q, vgt_send_q, vgt_rtr_q, tc_roq_send_q, tc_roq_rtr_dbg_q, rb_send_q, rb_rtr_q, pa_send_q, pa_rtr_q, rdc_valid, rdc_rlast, tlbmiss_valid, brc_valid) \ + ((mh_rbbm_busy << MH_DEBUG_REG26_MH_RBBM_busy_SHIFT) | \ + (mh_cib_mh_clk_en_int << MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT) | \ + (mh_cib_mmu_clk_en_int << MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT) | \ + (mh_cib_tcroq_clk_en_int << MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT) | \ + (gat_clk_ena << MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT) | \ + (rbbm_mh_clk_en_override << MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT) | \ + (cnt_q << MH_DEBUG_REG26_CNT_q_SHIFT) | \ + (tcd_empty_q << MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT) | \ + (tc_roq_empty << MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT) | \ + (mh_busy_d << MH_DEBUG_REG26_MH_BUSY_d_SHIFT) | \ + (any_clnt_busy << MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT) | \ + (mh_mmu_invalidate_invalidate_all << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) | \ + (mh_mmu_invalidate_invalidate_tc << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT) | \ + (cp_send_q << MH_DEBUG_REG26_CP_SEND_q_SHIFT) | \ + (cp_rtr_q << MH_DEBUG_REG26_CP_RTR_q_SHIFT) | \ + (vgt_send_q << MH_DEBUG_REG26_VGT_SEND_q_SHIFT) | \ + (vgt_rtr_q << MH_DEBUG_REG26_VGT_RTR_q_SHIFT) | \ + (tc_roq_send_q << MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT) | \ + (tc_roq_rtr_dbg_q << MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT) | \ + (rb_send_q << MH_DEBUG_REG26_RB_SEND_q_SHIFT) | \ + (rb_rtr_q << MH_DEBUG_REG26_RB_RTR_q_SHIFT) | \ + (pa_send_q << MH_DEBUG_REG26_PA_SEND_q_SHIFT) | \ + (pa_rtr_q << MH_DEBUG_REG26_PA_RTR_q_SHIFT) | \ + (rdc_valid << MH_DEBUG_REG26_RDC_VALID_SHIFT) | \ + (rdc_rlast << MH_DEBUG_REG26_RDC_RLAST_SHIFT) | \ + (tlbmiss_valid << MH_DEBUG_REG26_TLBMISS_VALID_SHIFT) | \ + (brc_valid << MH_DEBUG_REG26_BRC_VALID_SHIFT)) + +#define MH_DEBUG_REG26_GET_MH_RBBM_busy(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_RBBM_busy_MASK) >> MH_DEBUG_REG26_MH_RBBM_busy_SHIFT) +#define MH_DEBUG_REG26_GET_MH_CIB_mh_clk_en_int(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK) >> MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT) +#define MH_DEBUG_REG26_GET_MH_CIB_mmu_clk_en_int(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK) >> MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT) +#define MH_DEBUG_REG26_GET_MH_CIB_tcroq_clk_en_int(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK) >> MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT) +#define MH_DEBUG_REG26_GET_GAT_CLK_ENA(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_GAT_CLK_ENA_MASK) >> MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT) +#define MH_DEBUG_REG26_GET_RBBM_MH_clk_en_override(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK) >> MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT) +#define MH_DEBUG_REG26_GET_CNT_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_CNT_q_MASK) >> MH_DEBUG_REG26_CNT_q_SHIFT) +#define MH_DEBUG_REG26_GET_TCD_EMPTY_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TCD_EMPTY_q_MASK) >> MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT) +#define MH_DEBUG_REG26_GET_TC_ROQ_EMPTY(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG26_GET_MH_BUSY_d(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_BUSY_d_MASK) >> MH_DEBUG_REG26_MH_BUSY_d_SHIFT) +#define MH_DEBUG_REG26_GET_ANY_CLNT_BUSY(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK) >> MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT) +#define MH_DEBUG_REG26_GET_MH_MMU_INVALIDATE_INVALIDATE_ALL(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) >> MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) +#define MH_DEBUG_REG26_GET_MH_MMU_INVALIDATE_INVALIDATE_TC(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) >> MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT) +#define MH_DEBUG_REG26_GET_CP_SEND_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_CP_SEND_q_MASK) >> MH_DEBUG_REG26_CP_SEND_q_SHIFT) +#define MH_DEBUG_REG26_GET_CP_RTR_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_CP_RTR_q_MASK) >> MH_DEBUG_REG26_CP_RTR_q_SHIFT) +#define MH_DEBUG_REG26_GET_VGT_SEND_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_VGT_SEND_q_MASK) >> MH_DEBUG_REG26_VGT_SEND_q_SHIFT) +#define MH_DEBUG_REG26_GET_VGT_RTR_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_VGT_RTR_q_MASK) >> MH_DEBUG_REG26_VGT_RTR_q_SHIFT) +#define MH_DEBUG_REG26_GET_TC_ROQ_SEND_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG26_GET_TC_ROQ_RTR_DBG_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK) >> MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT) +#define MH_DEBUG_REG26_GET_RB_SEND_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_RB_SEND_q_MASK) >> MH_DEBUG_REG26_RB_SEND_q_SHIFT) +#define MH_DEBUG_REG26_GET_RB_RTR_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_RB_RTR_q_MASK) >> MH_DEBUG_REG26_RB_RTR_q_SHIFT) +#define MH_DEBUG_REG26_GET_PA_SEND_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_PA_SEND_q_MASK) >> MH_DEBUG_REG26_PA_SEND_q_SHIFT) +#define MH_DEBUG_REG26_GET_PA_RTR_q(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_PA_RTR_q_MASK) >> MH_DEBUG_REG26_PA_RTR_q_SHIFT) +#define MH_DEBUG_REG26_GET_RDC_VALID(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_RDC_VALID_MASK) >> MH_DEBUG_REG26_RDC_VALID_SHIFT) +#define MH_DEBUG_REG26_GET_RDC_RLAST(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_RDC_RLAST_MASK) >> MH_DEBUG_REG26_RDC_RLAST_SHIFT) +#define MH_DEBUG_REG26_GET_TLBMISS_VALID(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_TLBMISS_VALID_MASK) >> MH_DEBUG_REG26_TLBMISS_VALID_SHIFT) +#define MH_DEBUG_REG26_GET_BRC_VALID(mh_debug_reg26) \ + ((mh_debug_reg26 & MH_DEBUG_REG26_BRC_VALID_MASK) >> MH_DEBUG_REG26_BRC_VALID_SHIFT) + +#define MH_DEBUG_REG26_SET_MH_RBBM_busy(mh_debug_reg26_reg, mh_rbbm_busy) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_RBBM_busy_MASK) | (mh_rbbm_busy << MH_DEBUG_REG26_MH_RBBM_busy_SHIFT) +#define MH_DEBUG_REG26_SET_MH_CIB_mh_clk_en_int(mh_debug_reg26_reg, mh_cib_mh_clk_en_int) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_MASK) | (mh_cib_mh_clk_en_int << MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SHIFT) +#define MH_DEBUG_REG26_SET_MH_CIB_mmu_clk_en_int(mh_debug_reg26_reg, mh_cib_mmu_clk_en_int) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_MASK) | (mh_cib_mmu_clk_en_int << MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SHIFT) +#define MH_DEBUG_REG26_SET_MH_CIB_tcroq_clk_en_int(mh_debug_reg26_reg, mh_cib_tcroq_clk_en_int) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_MASK) | (mh_cib_tcroq_clk_en_int << MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SHIFT) +#define MH_DEBUG_REG26_SET_GAT_CLK_ENA(mh_debug_reg26_reg, gat_clk_ena) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_GAT_CLK_ENA_MASK) | (gat_clk_ena << MH_DEBUG_REG26_GAT_CLK_ENA_SHIFT) +#define MH_DEBUG_REG26_SET_RBBM_MH_clk_en_override(mh_debug_reg26_reg, rbbm_mh_clk_en_override) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RBBM_MH_clk_en_override_MASK) | (rbbm_mh_clk_en_override << MH_DEBUG_REG26_RBBM_MH_clk_en_override_SHIFT) +#define MH_DEBUG_REG26_SET_CNT_q(mh_debug_reg26_reg, cnt_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CNT_q_MASK) | (cnt_q << MH_DEBUG_REG26_CNT_q_SHIFT) +#define MH_DEBUG_REG26_SET_TCD_EMPTY_q(mh_debug_reg26_reg, tcd_empty_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TCD_EMPTY_q_MASK) | (tcd_empty_q << MH_DEBUG_REG26_TCD_EMPTY_q_SHIFT) +#define MH_DEBUG_REG26_SET_TC_ROQ_EMPTY(mh_debug_reg26_reg, tc_roq_empty) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG26_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG26_SET_MH_BUSY_d(mh_debug_reg26_reg, mh_busy_d) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_BUSY_d_MASK) | (mh_busy_d << MH_DEBUG_REG26_MH_BUSY_d_SHIFT) +#define MH_DEBUG_REG26_SET_ANY_CLNT_BUSY(mh_debug_reg26_reg, any_clnt_busy) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_ANY_CLNT_BUSY_MASK) | (any_clnt_busy << MH_DEBUG_REG26_ANY_CLNT_BUSY_SHIFT) +#define MH_DEBUG_REG26_SET_MH_MMU_INVALIDATE_INVALIDATE_ALL(mh_debug_reg26_reg, mh_mmu_invalidate_invalidate_all) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) | (mh_mmu_invalidate_invalidate_all << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) +#define MH_DEBUG_REG26_SET_MH_MMU_INVALIDATE_INVALIDATE_TC(mh_debug_reg26_reg, mh_mmu_invalidate_invalidate_tc) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) | (mh_mmu_invalidate_invalidate_tc << MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT) +#define MH_DEBUG_REG26_SET_CP_SEND_q(mh_debug_reg26_reg, cp_send_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CP_SEND_q_MASK) | (cp_send_q << MH_DEBUG_REG26_CP_SEND_q_SHIFT) +#define MH_DEBUG_REG26_SET_CP_RTR_q(mh_debug_reg26_reg, cp_rtr_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_CP_RTR_q_MASK) | (cp_rtr_q << MH_DEBUG_REG26_CP_RTR_q_SHIFT) +#define MH_DEBUG_REG26_SET_VGT_SEND_q(mh_debug_reg26_reg, vgt_send_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_VGT_SEND_q_MASK) | (vgt_send_q << MH_DEBUG_REG26_VGT_SEND_q_SHIFT) +#define MH_DEBUG_REG26_SET_VGT_RTR_q(mh_debug_reg26_reg, vgt_rtr_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_VGT_RTR_q_MASK) | (vgt_rtr_q << MH_DEBUG_REG26_VGT_RTR_q_SHIFT) +#define MH_DEBUG_REG26_SET_TC_ROQ_SEND_q(mh_debug_reg26_reg, tc_roq_send_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG26_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG26_SET_TC_ROQ_RTR_DBG_q(mh_debug_reg26_reg, tc_roq_rtr_dbg_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_MASK) | (tc_roq_rtr_dbg_q << MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SHIFT) +#define MH_DEBUG_REG26_SET_RB_SEND_q(mh_debug_reg26_reg, rb_send_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RB_SEND_q_MASK) | (rb_send_q << MH_DEBUG_REG26_RB_SEND_q_SHIFT) +#define MH_DEBUG_REG26_SET_RB_RTR_q(mh_debug_reg26_reg, rb_rtr_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RB_RTR_q_MASK) | (rb_rtr_q << MH_DEBUG_REG26_RB_RTR_q_SHIFT) +#define MH_DEBUG_REG26_SET_PA_SEND_q(mh_debug_reg26_reg, pa_send_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_PA_SEND_q_MASK) | (pa_send_q << MH_DEBUG_REG26_PA_SEND_q_SHIFT) +#define MH_DEBUG_REG26_SET_PA_RTR_q(mh_debug_reg26_reg, pa_rtr_q) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_PA_RTR_q_MASK) | (pa_rtr_q << MH_DEBUG_REG26_PA_RTR_q_SHIFT) +#define MH_DEBUG_REG26_SET_RDC_VALID(mh_debug_reg26_reg, rdc_valid) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RDC_VALID_MASK) | (rdc_valid << MH_DEBUG_REG26_RDC_VALID_SHIFT) +#define MH_DEBUG_REG26_SET_RDC_RLAST(mh_debug_reg26_reg, rdc_rlast) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_RDC_RLAST_MASK) | (rdc_rlast << MH_DEBUG_REG26_RDC_RLAST_SHIFT) +#define MH_DEBUG_REG26_SET_TLBMISS_VALID(mh_debug_reg26_reg, tlbmiss_valid) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_TLBMISS_VALID_MASK) | (tlbmiss_valid << MH_DEBUG_REG26_TLBMISS_VALID_SHIFT) +#define MH_DEBUG_REG26_SET_BRC_VALID(mh_debug_reg26_reg, brc_valid) \ + mh_debug_reg26_reg = (mh_debug_reg26_reg & ~MH_DEBUG_REG26_BRC_VALID_MASK) | (brc_valid << MH_DEBUG_REG26_BRC_VALID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg26_t { + unsigned int mh_rbbm_busy : MH_DEBUG_REG26_MH_RBBM_busy_SIZE; + unsigned int mh_cib_mh_clk_en_int : MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SIZE; + unsigned int mh_cib_mmu_clk_en_int : MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SIZE; + unsigned int mh_cib_tcroq_clk_en_int : MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SIZE; + unsigned int gat_clk_ena : MH_DEBUG_REG26_GAT_CLK_ENA_SIZE; + unsigned int rbbm_mh_clk_en_override : MH_DEBUG_REG26_RBBM_MH_clk_en_override_SIZE; + unsigned int cnt_q : MH_DEBUG_REG26_CNT_q_SIZE; + unsigned int tcd_empty_q : MH_DEBUG_REG26_TCD_EMPTY_q_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG26_TC_ROQ_EMPTY_SIZE; + unsigned int mh_busy_d : MH_DEBUG_REG26_MH_BUSY_d_SIZE; + unsigned int any_clnt_busy : MH_DEBUG_REG26_ANY_CLNT_BUSY_SIZE; + unsigned int mh_mmu_invalidate_invalidate_all : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE; + unsigned int mh_mmu_invalidate_invalidate_tc : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE; + unsigned int cp_send_q : MH_DEBUG_REG26_CP_SEND_q_SIZE; + unsigned int cp_rtr_q : MH_DEBUG_REG26_CP_RTR_q_SIZE; + unsigned int vgt_send_q : MH_DEBUG_REG26_VGT_SEND_q_SIZE; + unsigned int vgt_rtr_q : MH_DEBUG_REG26_VGT_RTR_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE; + unsigned int tc_roq_rtr_dbg_q : MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE; + unsigned int rb_send_q : MH_DEBUG_REG26_RB_SEND_q_SIZE; + unsigned int rb_rtr_q : MH_DEBUG_REG26_RB_RTR_q_SIZE; + unsigned int pa_send_q : MH_DEBUG_REG26_PA_SEND_q_SIZE; + unsigned int pa_rtr_q : MH_DEBUG_REG26_PA_RTR_q_SIZE; + unsigned int rdc_valid : MH_DEBUG_REG26_RDC_VALID_SIZE; + unsigned int rdc_rlast : MH_DEBUG_REG26_RDC_RLAST_SIZE; + unsigned int tlbmiss_valid : MH_DEBUG_REG26_TLBMISS_VALID_SIZE; + unsigned int brc_valid : MH_DEBUG_REG26_BRC_VALID_SIZE; + } mh_debug_reg26_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg26_t { + unsigned int brc_valid : MH_DEBUG_REG26_BRC_VALID_SIZE; + unsigned int tlbmiss_valid : MH_DEBUG_REG26_TLBMISS_VALID_SIZE; + unsigned int rdc_rlast : MH_DEBUG_REG26_RDC_RLAST_SIZE; + unsigned int rdc_valid : MH_DEBUG_REG26_RDC_VALID_SIZE; + unsigned int pa_rtr_q : MH_DEBUG_REG26_PA_RTR_q_SIZE; + unsigned int pa_send_q : MH_DEBUG_REG26_PA_SEND_q_SIZE; + unsigned int rb_rtr_q : MH_DEBUG_REG26_RB_RTR_q_SIZE; + unsigned int rb_send_q : MH_DEBUG_REG26_RB_SEND_q_SIZE; + unsigned int tc_roq_rtr_dbg_q : MH_DEBUG_REG26_TC_ROQ_RTR_DBG_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG26_TC_ROQ_SEND_q_SIZE; + unsigned int vgt_rtr_q : MH_DEBUG_REG26_VGT_RTR_q_SIZE; + unsigned int vgt_send_q : MH_DEBUG_REG26_VGT_SEND_q_SIZE; + unsigned int cp_rtr_q : MH_DEBUG_REG26_CP_RTR_q_SIZE; + unsigned int cp_send_q : MH_DEBUG_REG26_CP_SEND_q_SIZE; + unsigned int mh_mmu_invalidate_invalidate_tc : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE; + unsigned int mh_mmu_invalidate_invalidate_all : MH_DEBUG_REG26_MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE; + unsigned int any_clnt_busy : MH_DEBUG_REG26_ANY_CLNT_BUSY_SIZE; + unsigned int mh_busy_d : MH_DEBUG_REG26_MH_BUSY_d_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG26_TC_ROQ_EMPTY_SIZE; + unsigned int tcd_empty_q : MH_DEBUG_REG26_TCD_EMPTY_q_SIZE; + unsigned int cnt_q : MH_DEBUG_REG26_CNT_q_SIZE; + unsigned int rbbm_mh_clk_en_override : MH_DEBUG_REG26_RBBM_MH_clk_en_override_SIZE; + unsigned int gat_clk_ena : MH_DEBUG_REG26_GAT_CLK_ENA_SIZE; + unsigned int mh_cib_tcroq_clk_en_int : MH_DEBUG_REG26_MH_CIB_tcroq_clk_en_int_SIZE; + unsigned int mh_cib_mmu_clk_en_int : MH_DEBUG_REG26_MH_CIB_mmu_clk_en_int_SIZE; + unsigned int mh_cib_mh_clk_en_int : MH_DEBUG_REG26_MH_CIB_mh_clk_en_int_SIZE; + unsigned int mh_rbbm_busy : MH_DEBUG_REG26_MH_RBBM_busy_SIZE; + } mh_debug_reg26_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg26_t f; +} mh_debug_reg26_u; + + +/* + * MH_DEBUG_REG27 struct + */ + +#define MH_DEBUG_REG27_EFF2_FP_WINNER_SIZE 3 +#define MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SIZE 3 +#define MH_DEBUG_REG27_EFF1_WINNER_SIZE 3 +#define MH_DEBUG_REG27_ARB_WINNER_SIZE 3 +#define MH_DEBUG_REG27_ARB_WINNER_q_SIZE 3 +#define MH_DEBUG_REG27_EFF1_WIN_SIZE 1 +#define MH_DEBUG_REG27_KILL_EFF1_SIZE 1 +#define MH_DEBUG_REG27_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG27_ARB_RTR_q_SIZE 1 +#define MH_DEBUG_REG27_CP_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG27_VGT_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG27_TC_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SIZE 1 +#define MH_DEBUG_REG27_RB_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG27_PA_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG27_ARB_QUAL_SIZE 1 +#define MH_DEBUG_REG27_CP_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG27_VGT_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG27_TC_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG27_RB_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG27_TCD_NEARFULL_q_SIZE 1 +#define MH_DEBUG_REG27_TCHOLD_IP_q_SIZE 1 + +#define MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT 0 +#define MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT 3 +#define MH_DEBUG_REG27_EFF1_WINNER_SHIFT 6 +#define MH_DEBUG_REG27_ARB_WINNER_SHIFT 9 +#define MH_DEBUG_REG27_ARB_WINNER_q_SHIFT 12 +#define MH_DEBUG_REG27_EFF1_WIN_SHIFT 15 +#define MH_DEBUG_REG27_KILL_EFF1_SHIFT 16 +#define MH_DEBUG_REG27_ARB_HOLD_SHIFT 17 +#define MH_DEBUG_REG27_ARB_RTR_q_SHIFT 18 +#define MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT 19 +#define MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT 20 +#define MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT 21 +#define MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT 22 +#define MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT 23 +#define MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT 24 +#define MH_DEBUG_REG27_ARB_QUAL_SHIFT 25 +#define MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT 26 +#define MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT 27 +#define MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT 28 +#define MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT 29 +#define MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT 30 +#define MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT 31 + +#define MH_DEBUG_REG27_EFF2_FP_WINNER_MASK 0x00000007 +#define MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK 0x00000038 +#define MH_DEBUG_REG27_EFF1_WINNER_MASK 0x000001c0 +#define MH_DEBUG_REG27_ARB_WINNER_MASK 0x00000e00 +#define MH_DEBUG_REG27_ARB_WINNER_q_MASK 0x00007000 +#define MH_DEBUG_REG27_EFF1_WIN_MASK 0x00008000 +#define MH_DEBUG_REG27_KILL_EFF1_MASK 0x00010000 +#define MH_DEBUG_REG27_ARB_HOLD_MASK 0x00020000 +#define MH_DEBUG_REG27_ARB_RTR_q_MASK 0x00040000 +#define MH_DEBUG_REG27_CP_SEND_QUAL_MASK 0x00080000 +#define MH_DEBUG_REG27_VGT_SEND_QUAL_MASK 0x00100000 +#define MH_DEBUG_REG27_TC_SEND_QUAL_MASK 0x00200000 +#define MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK 0x00400000 +#define MH_DEBUG_REG27_RB_SEND_QUAL_MASK 0x00800000 +#define MH_DEBUG_REG27_PA_SEND_QUAL_MASK 0x01000000 +#define MH_DEBUG_REG27_ARB_QUAL_MASK 0x02000000 +#define MH_DEBUG_REG27_CP_EFF1_REQ_MASK 0x04000000 +#define MH_DEBUG_REG27_VGT_EFF1_REQ_MASK 0x08000000 +#define MH_DEBUG_REG27_TC_EFF1_REQ_MASK 0x10000000 +#define MH_DEBUG_REG27_RB_EFF1_REQ_MASK 0x20000000 +#define MH_DEBUG_REG27_TCD_NEARFULL_q_MASK 0x40000000 +#define MH_DEBUG_REG27_TCHOLD_IP_q_MASK 0x80000000 + +#define MH_DEBUG_REG27_MASK \ + (MH_DEBUG_REG27_EFF2_FP_WINNER_MASK | \ + MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK | \ + MH_DEBUG_REG27_EFF1_WINNER_MASK | \ + MH_DEBUG_REG27_ARB_WINNER_MASK | \ + MH_DEBUG_REG27_ARB_WINNER_q_MASK | \ + MH_DEBUG_REG27_EFF1_WIN_MASK | \ + MH_DEBUG_REG27_KILL_EFF1_MASK | \ + MH_DEBUG_REG27_ARB_HOLD_MASK | \ + MH_DEBUG_REG27_ARB_RTR_q_MASK | \ + MH_DEBUG_REG27_CP_SEND_QUAL_MASK | \ + MH_DEBUG_REG27_VGT_SEND_QUAL_MASK | \ + MH_DEBUG_REG27_TC_SEND_QUAL_MASK | \ + MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK | \ + MH_DEBUG_REG27_RB_SEND_QUAL_MASK | \ + MH_DEBUG_REG27_PA_SEND_QUAL_MASK | \ + MH_DEBUG_REG27_ARB_QUAL_MASK | \ + MH_DEBUG_REG27_CP_EFF1_REQ_MASK | \ + MH_DEBUG_REG27_VGT_EFF1_REQ_MASK | \ + MH_DEBUG_REG27_TC_EFF1_REQ_MASK | \ + MH_DEBUG_REG27_RB_EFF1_REQ_MASK | \ + MH_DEBUG_REG27_TCD_NEARFULL_q_MASK | \ + MH_DEBUG_REG27_TCHOLD_IP_q_MASK) + +#define MH_DEBUG_REG27(eff2_fp_winner, eff2_lru_winner_out, eff1_winner, arb_winner, arb_winner_q, eff1_win, kill_eff1, arb_hold, arb_rtr_q, cp_send_qual, vgt_send_qual, tc_send_qual, tc_send_eff1_qual, rb_send_qual, pa_send_qual, arb_qual, cp_eff1_req, vgt_eff1_req, tc_eff1_req, rb_eff1_req, tcd_nearfull_q, tchold_ip_q) \ + ((eff2_fp_winner << MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT) | \ + (eff2_lru_winner_out << MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT) | \ + (eff1_winner << MH_DEBUG_REG27_EFF1_WINNER_SHIFT) | \ + (arb_winner << MH_DEBUG_REG27_ARB_WINNER_SHIFT) | \ + (arb_winner_q << MH_DEBUG_REG27_ARB_WINNER_q_SHIFT) | \ + (eff1_win << MH_DEBUG_REG27_EFF1_WIN_SHIFT) | \ + (kill_eff1 << MH_DEBUG_REG27_KILL_EFF1_SHIFT) | \ + (arb_hold << MH_DEBUG_REG27_ARB_HOLD_SHIFT) | \ + (arb_rtr_q << MH_DEBUG_REG27_ARB_RTR_q_SHIFT) | \ + (cp_send_qual << MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT) | \ + (vgt_send_qual << MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT) | \ + (tc_send_qual << MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT) | \ + (tc_send_eff1_qual << MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT) | \ + (rb_send_qual << MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT) | \ + (pa_send_qual << MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT) | \ + (arb_qual << MH_DEBUG_REG27_ARB_QUAL_SHIFT) | \ + (cp_eff1_req << MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT) | \ + (vgt_eff1_req << MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT) | \ + (tc_eff1_req << MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT) | \ + (rb_eff1_req << MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT) | \ + (tcd_nearfull_q << MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT) | \ + (tchold_ip_q << MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT)) + +#define MH_DEBUG_REG27_GET_EFF2_FP_WINNER(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_EFF2_FP_WINNER_MASK) >> MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT) +#define MH_DEBUG_REG27_GET_EFF2_LRU_WINNER_out(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK) >> MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT) +#define MH_DEBUG_REG27_GET_EFF1_WINNER(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_EFF1_WINNER_MASK) >> MH_DEBUG_REG27_EFF1_WINNER_SHIFT) +#define MH_DEBUG_REG27_GET_ARB_WINNER(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_WINNER_MASK) >> MH_DEBUG_REG27_ARB_WINNER_SHIFT) +#define MH_DEBUG_REG27_GET_ARB_WINNER_q(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_WINNER_q_MASK) >> MH_DEBUG_REG27_ARB_WINNER_q_SHIFT) +#define MH_DEBUG_REG27_GET_EFF1_WIN(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_EFF1_WIN_MASK) >> MH_DEBUG_REG27_EFF1_WIN_SHIFT) +#define MH_DEBUG_REG27_GET_KILL_EFF1(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_KILL_EFF1_MASK) >> MH_DEBUG_REG27_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG27_GET_ARB_HOLD(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_HOLD_MASK) >> MH_DEBUG_REG27_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG27_GET_ARB_RTR_q(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_RTR_q_MASK) >> MH_DEBUG_REG27_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG27_GET_CP_SEND_QUAL(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_GET_VGT_SEND_QUAL(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_VGT_SEND_QUAL_MASK) >> MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_GET_TC_SEND_QUAL(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_TC_SEND_QUAL_MASK) >> MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_GET_TC_SEND_EFF1_QUAL(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK) >> MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG27_GET_RB_SEND_QUAL(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_GET_PA_SEND_QUAL(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_PA_SEND_QUAL_MASK) >> MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_GET_ARB_QUAL(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_ARB_QUAL_MASK) >> MH_DEBUG_REG27_ARB_QUAL_SHIFT) +#define MH_DEBUG_REG27_GET_CP_EFF1_REQ(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_CP_EFF1_REQ_MASK) >> MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_GET_VGT_EFF1_REQ(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_VGT_EFF1_REQ_MASK) >> MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_GET_TC_EFF1_REQ(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_TC_EFF1_REQ_MASK) >> MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_GET_RB_EFF1_REQ(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_RB_EFF1_REQ_MASK) >> MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_GET_TCD_NEARFULL_q(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG27_GET_TCHOLD_IP_q(mh_debug_reg27) \ + ((mh_debug_reg27 & MH_DEBUG_REG27_TCHOLD_IP_q_MASK) >> MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT) + +#define MH_DEBUG_REG27_SET_EFF2_FP_WINNER(mh_debug_reg27_reg, eff2_fp_winner) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF2_FP_WINNER_MASK) | (eff2_fp_winner << MH_DEBUG_REG27_EFF2_FP_WINNER_SHIFT) +#define MH_DEBUG_REG27_SET_EFF2_LRU_WINNER_out(mh_debug_reg27_reg, eff2_lru_winner_out) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF2_LRU_WINNER_out_MASK) | (eff2_lru_winner_out << MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SHIFT) +#define MH_DEBUG_REG27_SET_EFF1_WINNER(mh_debug_reg27_reg, eff1_winner) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF1_WINNER_MASK) | (eff1_winner << MH_DEBUG_REG27_EFF1_WINNER_SHIFT) +#define MH_DEBUG_REG27_SET_ARB_WINNER(mh_debug_reg27_reg, arb_winner) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG27_ARB_WINNER_SHIFT) +#define MH_DEBUG_REG27_SET_ARB_WINNER_q(mh_debug_reg27_reg, arb_winner_q) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_WINNER_q_MASK) | (arb_winner_q << MH_DEBUG_REG27_ARB_WINNER_q_SHIFT) +#define MH_DEBUG_REG27_SET_EFF1_WIN(mh_debug_reg27_reg, eff1_win) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_EFF1_WIN_MASK) | (eff1_win << MH_DEBUG_REG27_EFF1_WIN_SHIFT) +#define MH_DEBUG_REG27_SET_KILL_EFF1(mh_debug_reg27_reg, kill_eff1) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG27_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG27_SET_ARB_HOLD(mh_debug_reg27_reg, arb_hold) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG27_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG27_SET_ARB_RTR_q(mh_debug_reg27_reg, arb_rtr_q) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG27_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG27_SET_CP_SEND_QUAL(mh_debug_reg27_reg, cp_send_qual) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG27_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_SET_VGT_SEND_QUAL(mh_debug_reg27_reg, vgt_send_qual) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_VGT_SEND_QUAL_MASK) | (vgt_send_qual << MH_DEBUG_REG27_VGT_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_SET_TC_SEND_QUAL(mh_debug_reg27_reg, tc_send_qual) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TC_SEND_QUAL_MASK) | (tc_send_qual << MH_DEBUG_REG27_TC_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_SET_TC_SEND_EFF1_QUAL(mh_debug_reg27_reg, tc_send_eff1_qual) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_MASK) | (tc_send_eff1_qual << MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG27_SET_RB_SEND_QUAL(mh_debug_reg27_reg, rb_send_qual) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG27_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_SET_PA_SEND_QUAL(mh_debug_reg27_reg, pa_send_qual) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_PA_SEND_QUAL_MASK) | (pa_send_qual << MH_DEBUG_REG27_PA_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG27_SET_ARB_QUAL(mh_debug_reg27_reg, arb_qual) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_ARB_QUAL_MASK) | (arb_qual << MH_DEBUG_REG27_ARB_QUAL_SHIFT) +#define MH_DEBUG_REG27_SET_CP_EFF1_REQ(mh_debug_reg27_reg, cp_eff1_req) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_CP_EFF1_REQ_MASK) | (cp_eff1_req << MH_DEBUG_REG27_CP_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_SET_VGT_EFF1_REQ(mh_debug_reg27_reg, vgt_eff1_req) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_VGT_EFF1_REQ_MASK) | (vgt_eff1_req << MH_DEBUG_REG27_VGT_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_SET_TC_EFF1_REQ(mh_debug_reg27_reg, tc_eff1_req) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TC_EFF1_REQ_MASK) | (tc_eff1_req << MH_DEBUG_REG27_TC_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_SET_RB_EFF1_REQ(mh_debug_reg27_reg, rb_eff1_req) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_RB_EFF1_REQ_MASK) | (rb_eff1_req << MH_DEBUG_REG27_RB_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG27_SET_TCD_NEARFULL_q(mh_debug_reg27_reg, tcd_nearfull_q) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG27_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG27_SET_TCHOLD_IP_q(mh_debug_reg27_reg, tchold_ip_q) \ + mh_debug_reg27_reg = (mh_debug_reg27_reg & ~MH_DEBUG_REG27_TCHOLD_IP_q_MASK) | (tchold_ip_q << MH_DEBUG_REG27_TCHOLD_IP_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg27_t { + unsigned int eff2_fp_winner : MH_DEBUG_REG27_EFF2_FP_WINNER_SIZE; + unsigned int eff2_lru_winner_out : MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SIZE; + unsigned int eff1_winner : MH_DEBUG_REG27_EFF1_WINNER_SIZE; + unsigned int arb_winner : MH_DEBUG_REG27_ARB_WINNER_SIZE; + unsigned int arb_winner_q : MH_DEBUG_REG27_ARB_WINNER_q_SIZE; + unsigned int eff1_win : MH_DEBUG_REG27_EFF1_WIN_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG27_KILL_EFF1_SIZE; + unsigned int arb_hold : MH_DEBUG_REG27_ARB_HOLD_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG27_ARB_RTR_q_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG27_CP_SEND_QUAL_SIZE; + unsigned int vgt_send_qual : MH_DEBUG_REG27_VGT_SEND_QUAL_SIZE; + unsigned int tc_send_qual : MH_DEBUG_REG27_TC_SEND_QUAL_SIZE; + unsigned int tc_send_eff1_qual : MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG27_RB_SEND_QUAL_SIZE; + unsigned int pa_send_qual : MH_DEBUG_REG27_PA_SEND_QUAL_SIZE; + unsigned int arb_qual : MH_DEBUG_REG27_ARB_QUAL_SIZE; + unsigned int cp_eff1_req : MH_DEBUG_REG27_CP_EFF1_REQ_SIZE; + unsigned int vgt_eff1_req : MH_DEBUG_REG27_VGT_EFF1_REQ_SIZE; + unsigned int tc_eff1_req : MH_DEBUG_REG27_TC_EFF1_REQ_SIZE; + unsigned int rb_eff1_req : MH_DEBUG_REG27_RB_EFF1_REQ_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG27_TCD_NEARFULL_q_SIZE; + unsigned int tchold_ip_q : MH_DEBUG_REG27_TCHOLD_IP_q_SIZE; + } mh_debug_reg27_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg27_t { + unsigned int tchold_ip_q : MH_DEBUG_REG27_TCHOLD_IP_q_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG27_TCD_NEARFULL_q_SIZE; + unsigned int rb_eff1_req : MH_DEBUG_REG27_RB_EFF1_REQ_SIZE; + unsigned int tc_eff1_req : MH_DEBUG_REG27_TC_EFF1_REQ_SIZE; + unsigned int vgt_eff1_req : MH_DEBUG_REG27_VGT_EFF1_REQ_SIZE; + unsigned int cp_eff1_req : MH_DEBUG_REG27_CP_EFF1_REQ_SIZE; + unsigned int arb_qual : MH_DEBUG_REG27_ARB_QUAL_SIZE; + unsigned int pa_send_qual : MH_DEBUG_REG27_PA_SEND_QUAL_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG27_RB_SEND_QUAL_SIZE; + unsigned int tc_send_eff1_qual : MH_DEBUG_REG27_TC_SEND_EFF1_QUAL_SIZE; + unsigned int tc_send_qual : MH_DEBUG_REG27_TC_SEND_QUAL_SIZE; + unsigned int vgt_send_qual : MH_DEBUG_REG27_VGT_SEND_QUAL_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG27_CP_SEND_QUAL_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG27_ARB_RTR_q_SIZE; + unsigned int arb_hold : MH_DEBUG_REG27_ARB_HOLD_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG27_KILL_EFF1_SIZE; + unsigned int eff1_win : MH_DEBUG_REG27_EFF1_WIN_SIZE; + unsigned int arb_winner_q : MH_DEBUG_REG27_ARB_WINNER_q_SIZE; + unsigned int arb_winner : MH_DEBUG_REG27_ARB_WINNER_SIZE; + unsigned int eff1_winner : MH_DEBUG_REG27_EFF1_WINNER_SIZE; + unsigned int eff2_lru_winner_out : MH_DEBUG_REG27_EFF2_LRU_WINNER_out_SIZE; + unsigned int eff2_fp_winner : MH_DEBUG_REG27_EFF2_FP_WINNER_SIZE; + } mh_debug_reg27_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg27_t f; +} mh_debug_reg27_u; + + +/* + * MH_DEBUG_REG28 struct + */ + +#define MH_DEBUG_REG28_EFF1_WINNER_SIZE 3 +#define MH_DEBUG_REG28_ARB_WINNER_SIZE 3 +#define MH_DEBUG_REG28_CP_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG28_VGT_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG28_TC_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SIZE 1 +#define MH_DEBUG_REG28_RB_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG28_ARB_QUAL_SIZE 1 +#define MH_DEBUG_REG28_CP_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG28_VGT_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG28_TC_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG28_RB_EFF1_REQ_SIZE 1 +#define MH_DEBUG_REG28_EFF1_WIN_SIZE 1 +#define MH_DEBUG_REG28_KILL_EFF1_SIZE 1 +#define MH_DEBUG_REG28_TCD_NEARFULL_q_SIZE 1 +#define MH_DEBUG_REG28_TC_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG28_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG28_ARB_RTR_q_SIZE 1 +#define MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SIZE 10 + +#define MH_DEBUG_REG28_EFF1_WINNER_SHIFT 0 +#define MH_DEBUG_REG28_ARB_WINNER_SHIFT 3 +#define MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT 6 +#define MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT 7 +#define MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT 8 +#define MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT 9 +#define MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT 10 +#define MH_DEBUG_REG28_ARB_QUAL_SHIFT 11 +#define MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT 12 +#define MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT 13 +#define MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT 14 +#define MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT 15 +#define MH_DEBUG_REG28_EFF1_WIN_SHIFT 16 +#define MH_DEBUG_REG28_KILL_EFF1_SHIFT 17 +#define MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT 18 +#define MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT 19 +#define MH_DEBUG_REG28_ARB_HOLD_SHIFT 20 +#define MH_DEBUG_REG28_ARB_RTR_q_SHIFT 21 +#define MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT 22 + +#define MH_DEBUG_REG28_EFF1_WINNER_MASK 0x00000007 +#define MH_DEBUG_REG28_ARB_WINNER_MASK 0x00000038 +#define MH_DEBUG_REG28_CP_SEND_QUAL_MASK 0x00000040 +#define MH_DEBUG_REG28_VGT_SEND_QUAL_MASK 0x00000080 +#define MH_DEBUG_REG28_TC_SEND_QUAL_MASK 0x00000100 +#define MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK 0x00000200 +#define MH_DEBUG_REG28_RB_SEND_QUAL_MASK 0x00000400 +#define MH_DEBUG_REG28_ARB_QUAL_MASK 0x00000800 +#define MH_DEBUG_REG28_CP_EFF1_REQ_MASK 0x00001000 +#define MH_DEBUG_REG28_VGT_EFF1_REQ_MASK 0x00002000 +#define MH_DEBUG_REG28_TC_EFF1_REQ_MASK 0x00004000 +#define MH_DEBUG_REG28_RB_EFF1_REQ_MASK 0x00008000 +#define MH_DEBUG_REG28_EFF1_WIN_MASK 0x00010000 +#define MH_DEBUG_REG28_KILL_EFF1_MASK 0x00020000 +#define MH_DEBUG_REG28_TCD_NEARFULL_q_MASK 0x00040000 +#define MH_DEBUG_REG28_TC_ARB_HOLD_MASK 0x00080000 +#define MH_DEBUG_REG28_ARB_HOLD_MASK 0x00100000 +#define MH_DEBUG_REG28_ARB_RTR_q_MASK 0x00200000 +#define MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK 0xffc00000 + +#define MH_DEBUG_REG28_MASK \ + (MH_DEBUG_REG28_EFF1_WINNER_MASK | \ + MH_DEBUG_REG28_ARB_WINNER_MASK | \ + MH_DEBUG_REG28_CP_SEND_QUAL_MASK | \ + MH_DEBUG_REG28_VGT_SEND_QUAL_MASK | \ + MH_DEBUG_REG28_TC_SEND_QUAL_MASK | \ + MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK | \ + MH_DEBUG_REG28_RB_SEND_QUAL_MASK | \ + MH_DEBUG_REG28_ARB_QUAL_MASK | \ + MH_DEBUG_REG28_CP_EFF1_REQ_MASK | \ + MH_DEBUG_REG28_VGT_EFF1_REQ_MASK | \ + MH_DEBUG_REG28_TC_EFF1_REQ_MASK | \ + MH_DEBUG_REG28_RB_EFF1_REQ_MASK | \ + MH_DEBUG_REG28_EFF1_WIN_MASK | \ + MH_DEBUG_REG28_KILL_EFF1_MASK | \ + MH_DEBUG_REG28_TCD_NEARFULL_q_MASK | \ + MH_DEBUG_REG28_TC_ARB_HOLD_MASK | \ + MH_DEBUG_REG28_ARB_HOLD_MASK | \ + MH_DEBUG_REG28_ARB_RTR_q_MASK | \ + MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK) + +#define MH_DEBUG_REG28(eff1_winner, arb_winner, cp_send_qual, vgt_send_qual, tc_send_qual, tc_send_eff1_qual, rb_send_qual, arb_qual, cp_eff1_req, vgt_eff1_req, tc_eff1_req, rb_eff1_req, eff1_win, kill_eff1, tcd_nearfull_q, tc_arb_hold, arb_hold, arb_rtr_q, same_page_limit_count_q) \ + ((eff1_winner << MH_DEBUG_REG28_EFF1_WINNER_SHIFT) | \ + (arb_winner << MH_DEBUG_REG28_ARB_WINNER_SHIFT) | \ + (cp_send_qual << MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT) | \ + (vgt_send_qual << MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT) | \ + (tc_send_qual << MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT) | \ + (tc_send_eff1_qual << MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT) | \ + (rb_send_qual << MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT) | \ + (arb_qual << MH_DEBUG_REG28_ARB_QUAL_SHIFT) | \ + (cp_eff1_req << MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT) | \ + (vgt_eff1_req << MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT) | \ + (tc_eff1_req << MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT) | \ + (rb_eff1_req << MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT) | \ + (eff1_win << MH_DEBUG_REG28_EFF1_WIN_SHIFT) | \ + (kill_eff1 << MH_DEBUG_REG28_KILL_EFF1_SHIFT) | \ + (tcd_nearfull_q << MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT) | \ + (tc_arb_hold << MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT) | \ + (arb_hold << MH_DEBUG_REG28_ARB_HOLD_SHIFT) | \ + (arb_rtr_q << MH_DEBUG_REG28_ARB_RTR_q_SHIFT) | \ + (same_page_limit_count_q << MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT)) + +#define MH_DEBUG_REG28_GET_EFF1_WINNER(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_EFF1_WINNER_MASK) >> MH_DEBUG_REG28_EFF1_WINNER_SHIFT) +#define MH_DEBUG_REG28_GET_ARB_WINNER(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_WINNER_MASK) >> MH_DEBUG_REG28_ARB_WINNER_SHIFT) +#define MH_DEBUG_REG28_GET_CP_SEND_QUAL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_GET_VGT_SEND_QUAL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_VGT_SEND_QUAL_MASK) >> MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_GET_TC_SEND_QUAL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TC_SEND_QUAL_MASK) >> MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_GET_TC_SEND_EFF1_QUAL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK) >> MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG28_GET_RB_SEND_QUAL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_GET_ARB_QUAL(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_QUAL_MASK) >> MH_DEBUG_REG28_ARB_QUAL_SHIFT) +#define MH_DEBUG_REG28_GET_CP_EFF1_REQ(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_CP_EFF1_REQ_MASK) >> MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_GET_VGT_EFF1_REQ(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_VGT_EFF1_REQ_MASK) >> MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_GET_TC_EFF1_REQ(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TC_EFF1_REQ_MASK) >> MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_GET_RB_EFF1_REQ(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_RB_EFF1_REQ_MASK) >> MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_GET_EFF1_WIN(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_EFF1_WIN_MASK) >> MH_DEBUG_REG28_EFF1_WIN_SHIFT) +#define MH_DEBUG_REG28_GET_KILL_EFF1(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_KILL_EFF1_MASK) >> MH_DEBUG_REG28_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG28_GET_TCD_NEARFULL_q(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG28_GET_TC_ARB_HOLD(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_TC_ARB_HOLD_MASK) >> MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG28_GET_ARB_HOLD(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_HOLD_MASK) >> MH_DEBUG_REG28_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG28_GET_ARB_RTR_q(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_ARB_RTR_q_MASK) >> MH_DEBUG_REG28_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG28_GET_SAME_PAGE_LIMIT_COUNT_q(mh_debug_reg28) \ + ((mh_debug_reg28 & MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK) >> MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT) + +#define MH_DEBUG_REG28_SET_EFF1_WINNER(mh_debug_reg28_reg, eff1_winner) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_EFF1_WINNER_MASK) | (eff1_winner << MH_DEBUG_REG28_EFF1_WINNER_SHIFT) +#define MH_DEBUG_REG28_SET_ARB_WINNER(mh_debug_reg28_reg, arb_winner) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG28_ARB_WINNER_SHIFT) +#define MH_DEBUG_REG28_SET_CP_SEND_QUAL(mh_debug_reg28_reg, cp_send_qual) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG28_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_SET_VGT_SEND_QUAL(mh_debug_reg28_reg, vgt_send_qual) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_VGT_SEND_QUAL_MASK) | (vgt_send_qual << MH_DEBUG_REG28_VGT_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_SET_TC_SEND_QUAL(mh_debug_reg28_reg, tc_send_qual) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_SEND_QUAL_MASK) | (tc_send_qual << MH_DEBUG_REG28_TC_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_SET_TC_SEND_EFF1_QUAL(mh_debug_reg28_reg, tc_send_eff1_qual) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_MASK) | (tc_send_eff1_qual << MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG28_SET_RB_SEND_QUAL(mh_debug_reg28_reg, rb_send_qual) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG28_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG28_SET_ARB_QUAL(mh_debug_reg28_reg, arb_qual) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_QUAL_MASK) | (arb_qual << MH_DEBUG_REG28_ARB_QUAL_SHIFT) +#define MH_DEBUG_REG28_SET_CP_EFF1_REQ(mh_debug_reg28_reg, cp_eff1_req) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_CP_EFF1_REQ_MASK) | (cp_eff1_req << MH_DEBUG_REG28_CP_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_SET_VGT_EFF1_REQ(mh_debug_reg28_reg, vgt_eff1_req) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_VGT_EFF1_REQ_MASK) | (vgt_eff1_req << MH_DEBUG_REG28_VGT_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_SET_TC_EFF1_REQ(mh_debug_reg28_reg, tc_eff1_req) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_EFF1_REQ_MASK) | (tc_eff1_req << MH_DEBUG_REG28_TC_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_SET_RB_EFF1_REQ(mh_debug_reg28_reg, rb_eff1_req) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_RB_EFF1_REQ_MASK) | (rb_eff1_req << MH_DEBUG_REG28_RB_EFF1_REQ_SHIFT) +#define MH_DEBUG_REG28_SET_EFF1_WIN(mh_debug_reg28_reg, eff1_win) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_EFF1_WIN_MASK) | (eff1_win << MH_DEBUG_REG28_EFF1_WIN_SHIFT) +#define MH_DEBUG_REG28_SET_KILL_EFF1(mh_debug_reg28_reg, kill_eff1) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG28_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG28_SET_TCD_NEARFULL_q(mh_debug_reg28_reg, tcd_nearfull_q) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG28_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG28_SET_TC_ARB_HOLD(mh_debug_reg28_reg, tc_arb_hold) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_TC_ARB_HOLD_MASK) | (tc_arb_hold << MH_DEBUG_REG28_TC_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG28_SET_ARB_HOLD(mh_debug_reg28_reg, arb_hold) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG28_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG28_SET_ARB_RTR_q(mh_debug_reg28_reg, arb_rtr_q) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG28_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG28_SET_SAME_PAGE_LIMIT_COUNT_q(mh_debug_reg28_reg, same_page_limit_count_q) \ + mh_debug_reg28_reg = (mh_debug_reg28_reg & ~MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_MASK) | (same_page_limit_count_q << MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg28_t { + unsigned int eff1_winner : MH_DEBUG_REG28_EFF1_WINNER_SIZE; + unsigned int arb_winner : MH_DEBUG_REG28_ARB_WINNER_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG28_CP_SEND_QUAL_SIZE; + unsigned int vgt_send_qual : MH_DEBUG_REG28_VGT_SEND_QUAL_SIZE; + unsigned int tc_send_qual : MH_DEBUG_REG28_TC_SEND_QUAL_SIZE; + unsigned int tc_send_eff1_qual : MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG28_RB_SEND_QUAL_SIZE; + unsigned int arb_qual : MH_DEBUG_REG28_ARB_QUAL_SIZE; + unsigned int cp_eff1_req : MH_DEBUG_REG28_CP_EFF1_REQ_SIZE; + unsigned int vgt_eff1_req : MH_DEBUG_REG28_VGT_EFF1_REQ_SIZE; + unsigned int tc_eff1_req : MH_DEBUG_REG28_TC_EFF1_REQ_SIZE; + unsigned int rb_eff1_req : MH_DEBUG_REG28_RB_EFF1_REQ_SIZE; + unsigned int eff1_win : MH_DEBUG_REG28_EFF1_WIN_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG28_KILL_EFF1_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG28_TCD_NEARFULL_q_SIZE; + unsigned int tc_arb_hold : MH_DEBUG_REG28_TC_ARB_HOLD_SIZE; + unsigned int arb_hold : MH_DEBUG_REG28_ARB_HOLD_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG28_ARB_RTR_q_SIZE; + unsigned int same_page_limit_count_q : MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SIZE; + } mh_debug_reg28_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg28_t { + unsigned int same_page_limit_count_q : MH_DEBUG_REG28_SAME_PAGE_LIMIT_COUNT_q_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG28_ARB_RTR_q_SIZE; + unsigned int arb_hold : MH_DEBUG_REG28_ARB_HOLD_SIZE; + unsigned int tc_arb_hold : MH_DEBUG_REG28_TC_ARB_HOLD_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG28_TCD_NEARFULL_q_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG28_KILL_EFF1_SIZE; + unsigned int eff1_win : MH_DEBUG_REG28_EFF1_WIN_SIZE; + unsigned int rb_eff1_req : MH_DEBUG_REG28_RB_EFF1_REQ_SIZE; + unsigned int tc_eff1_req : MH_DEBUG_REG28_TC_EFF1_REQ_SIZE; + unsigned int vgt_eff1_req : MH_DEBUG_REG28_VGT_EFF1_REQ_SIZE; + unsigned int cp_eff1_req : MH_DEBUG_REG28_CP_EFF1_REQ_SIZE; + unsigned int arb_qual : MH_DEBUG_REG28_ARB_QUAL_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG28_RB_SEND_QUAL_SIZE; + unsigned int tc_send_eff1_qual : MH_DEBUG_REG28_TC_SEND_EFF1_QUAL_SIZE; + unsigned int tc_send_qual : MH_DEBUG_REG28_TC_SEND_QUAL_SIZE; + unsigned int vgt_send_qual : MH_DEBUG_REG28_VGT_SEND_QUAL_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG28_CP_SEND_QUAL_SIZE; + unsigned int arb_winner : MH_DEBUG_REG28_ARB_WINNER_SIZE; + unsigned int eff1_winner : MH_DEBUG_REG28_EFF1_WINNER_SIZE; + } mh_debug_reg28_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg28_t f; +} mh_debug_reg28_u; + + +/* + * MH_DEBUG_REG29 struct + */ + +#define MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SIZE 3 +#define MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SIZE 3 +#define MH_DEBUG_REG29_LEAST_RECENT_d_SIZE 3 +#define MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SIZE 1 +#define MH_DEBUG_REG29_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG29_ARB_RTR_q_SIZE 1 +#define MH_DEBUG_REG29_CLNT_REQ_SIZE 5 +#define MH_DEBUG_REG29_RECENT_d_0_SIZE 3 +#define MH_DEBUG_REG29_RECENT_d_1_SIZE 3 +#define MH_DEBUG_REG29_RECENT_d_2_SIZE 3 +#define MH_DEBUG_REG29_RECENT_d_3_SIZE 3 +#define MH_DEBUG_REG29_RECENT_d_4_SIZE 3 + +#define MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT 0 +#define MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT 3 +#define MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT 6 +#define MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT 9 +#define MH_DEBUG_REG29_ARB_HOLD_SHIFT 10 +#define MH_DEBUG_REG29_ARB_RTR_q_SHIFT 11 +#define MH_DEBUG_REG29_CLNT_REQ_SHIFT 12 +#define MH_DEBUG_REG29_RECENT_d_0_SHIFT 17 +#define MH_DEBUG_REG29_RECENT_d_1_SHIFT 20 +#define MH_DEBUG_REG29_RECENT_d_2_SHIFT 23 +#define MH_DEBUG_REG29_RECENT_d_3_SHIFT 26 +#define MH_DEBUG_REG29_RECENT_d_4_SHIFT 29 + +#define MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK 0x00000007 +#define MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK 0x00000038 +#define MH_DEBUG_REG29_LEAST_RECENT_d_MASK 0x000001c0 +#define MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK 0x00000200 +#define MH_DEBUG_REG29_ARB_HOLD_MASK 0x00000400 +#define MH_DEBUG_REG29_ARB_RTR_q_MASK 0x00000800 +#define MH_DEBUG_REG29_CLNT_REQ_MASK 0x0001f000 +#define MH_DEBUG_REG29_RECENT_d_0_MASK 0x000e0000 +#define MH_DEBUG_REG29_RECENT_d_1_MASK 0x00700000 +#define MH_DEBUG_REG29_RECENT_d_2_MASK 0x03800000 +#define MH_DEBUG_REG29_RECENT_d_3_MASK 0x1c000000 +#define MH_DEBUG_REG29_RECENT_d_4_MASK 0xe0000000 + +#define MH_DEBUG_REG29_MASK \ + (MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK | \ + MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK | \ + MH_DEBUG_REG29_LEAST_RECENT_d_MASK | \ + MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK | \ + MH_DEBUG_REG29_ARB_HOLD_MASK | \ + MH_DEBUG_REG29_ARB_RTR_q_MASK | \ + MH_DEBUG_REG29_CLNT_REQ_MASK | \ + MH_DEBUG_REG29_RECENT_d_0_MASK | \ + MH_DEBUG_REG29_RECENT_d_1_MASK | \ + MH_DEBUG_REG29_RECENT_d_2_MASK | \ + MH_DEBUG_REG29_RECENT_d_3_MASK | \ + MH_DEBUG_REG29_RECENT_d_4_MASK) + +#define MH_DEBUG_REG29(eff2_lru_winner_out, least_recent_index_d, least_recent_d, update_recent_stack_d, arb_hold, arb_rtr_q, clnt_req, recent_d_0, recent_d_1, recent_d_2, recent_d_3, recent_d_4) \ + ((eff2_lru_winner_out << MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT) | \ + (least_recent_index_d << MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT) | \ + (least_recent_d << MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT) | \ + (update_recent_stack_d << MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT) | \ + (arb_hold << MH_DEBUG_REG29_ARB_HOLD_SHIFT) | \ + (arb_rtr_q << MH_DEBUG_REG29_ARB_RTR_q_SHIFT) | \ + (clnt_req << MH_DEBUG_REG29_CLNT_REQ_SHIFT) | \ + (recent_d_0 << MH_DEBUG_REG29_RECENT_d_0_SHIFT) | \ + (recent_d_1 << MH_DEBUG_REG29_RECENT_d_1_SHIFT) | \ + (recent_d_2 << MH_DEBUG_REG29_RECENT_d_2_SHIFT) | \ + (recent_d_3 << MH_DEBUG_REG29_RECENT_d_3_SHIFT) | \ + (recent_d_4 << MH_DEBUG_REG29_RECENT_d_4_SHIFT)) + +#define MH_DEBUG_REG29_GET_EFF2_LRU_WINNER_out(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK) >> MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT) +#define MH_DEBUG_REG29_GET_LEAST_RECENT_INDEX_d(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK) >> MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT) +#define MH_DEBUG_REG29_GET_LEAST_RECENT_d(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_LEAST_RECENT_d_MASK) >> MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT) +#define MH_DEBUG_REG29_GET_UPDATE_RECENT_STACK_d(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK) >> MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT) +#define MH_DEBUG_REG29_GET_ARB_HOLD(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_ARB_HOLD_MASK) >> MH_DEBUG_REG29_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG29_GET_ARB_RTR_q(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_ARB_RTR_q_MASK) >> MH_DEBUG_REG29_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG29_GET_CLNT_REQ(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_CLNT_REQ_MASK) >> MH_DEBUG_REG29_CLNT_REQ_SHIFT) +#define MH_DEBUG_REG29_GET_RECENT_d_0(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_0_MASK) >> MH_DEBUG_REG29_RECENT_d_0_SHIFT) +#define MH_DEBUG_REG29_GET_RECENT_d_1(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_1_MASK) >> MH_DEBUG_REG29_RECENT_d_1_SHIFT) +#define MH_DEBUG_REG29_GET_RECENT_d_2(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_2_MASK) >> MH_DEBUG_REG29_RECENT_d_2_SHIFT) +#define MH_DEBUG_REG29_GET_RECENT_d_3(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_3_MASK) >> MH_DEBUG_REG29_RECENT_d_3_SHIFT) +#define MH_DEBUG_REG29_GET_RECENT_d_4(mh_debug_reg29) \ + ((mh_debug_reg29 & MH_DEBUG_REG29_RECENT_d_4_MASK) >> MH_DEBUG_REG29_RECENT_d_4_SHIFT) + +#define MH_DEBUG_REG29_SET_EFF2_LRU_WINNER_out(mh_debug_reg29_reg, eff2_lru_winner_out) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_EFF2_LRU_WINNER_out_MASK) | (eff2_lru_winner_out << MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SHIFT) +#define MH_DEBUG_REG29_SET_LEAST_RECENT_INDEX_d(mh_debug_reg29_reg, least_recent_index_d) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_MASK) | (least_recent_index_d << MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SHIFT) +#define MH_DEBUG_REG29_SET_LEAST_RECENT_d(mh_debug_reg29_reg, least_recent_d) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_LEAST_RECENT_d_MASK) | (least_recent_d << MH_DEBUG_REG29_LEAST_RECENT_d_SHIFT) +#define MH_DEBUG_REG29_SET_UPDATE_RECENT_STACK_d(mh_debug_reg29_reg, update_recent_stack_d) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_MASK) | (update_recent_stack_d << MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SHIFT) +#define MH_DEBUG_REG29_SET_ARB_HOLD(mh_debug_reg29_reg, arb_hold) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_ARB_HOLD_MASK) | (arb_hold << MH_DEBUG_REG29_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG29_SET_ARB_RTR_q(mh_debug_reg29_reg, arb_rtr_q) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG29_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG29_SET_CLNT_REQ(mh_debug_reg29_reg, clnt_req) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_CLNT_REQ_MASK) | (clnt_req << MH_DEBUG_REG29_CLNT_REQ_SHIFT) +#define MH_DEBUG_REG29_SET_RECENT_d_0(mh_debug_reg29_reg, recent_d_0) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_0_MASK) | (recent_d_0 << MH_DEBUG_REG29_RECENT_d_0_SHIFT) +#define MH_DEBUG_REG29_SET_RECENT_d_1(mh_debug_reg29_reg, recent_d_1) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_1_MASK) | (recent_d_1 << MH_DEBUG_REG29_RECENT_d_1_SHIFT) +#define MH_DEBUG_REG29_SET_RECENT_d_2(mh_debug_reg29_reg, recent_d_2) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_2_MASK) | (recent_d_2 << MH_DEBUG_REG29_RECENT_d_2_SHIFT) +#define MH_DEBUG_REG29_SET_RECENT_d_3(mh_debug_reg29_reg, recent_d_3) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_3_MASK) | (recent_d_3 << MH_DEBUG_REG29_RECENT_d_3_SHIFT) +#define MH_DEBUG_REG29_SET_RECENT_d_4(mh_debug_reg29_reg, recent_d_4) \ + mh_debug_reg29_reg = (mh_debug_reg29_reg & ~MH_DEBUG_REG29_RECENT_d_4_MASK) | (recent_d_4 << MH_DEBUG_REG29_RECENT_d_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg29_t { + unsigned int eff2_lru_winner_out : MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SIZE; + unsigned int least_recent_index_d : MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SIZE; + unsigned int least_recent_d : MH_DEBUG_REG29_LEAST_RECENT_d_SIZE; + unsigned int update_recent_stack_d : MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SIZE; + unsigned int arb_hold : MH_DEBUG_REG29_ARB_HOLD_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG29_ARB_RTR_q_SIZE; + unsigned int clnt_req : MH_DEBUG_REG29_CLNT_REQ_SIZE; + unsigned int recent_d_0 : MH_DEBUG_REG29_RECENT_d_0_SIZE; + unsigned int recent_d_1 : MH_DEBUG_REG29_RECENT_d_1_SIZE; + unsigned int recent_d_2 : MH_DEBUG_REG29_RECENT_d_2_SIZE; + unsigned int recent_d_3 : MH_DEBUG_REG29_RECENT_d_3_SIZE; + unsigned int recent_d_4 : MH_DEBUG_REG29_RECENT_d_4_SIZE; + } mh_debug_reg29_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg29_t { + unsigned int recent_d_4 : MH_DEBUG_REG29_RECENT_d_4_SIZE; + unsigned int recent_d_3 : MH_DEBUG_REG29_RECENT_d_3_SIZE; + unsigned int recent_d_2 : MH_DEBUG_REG29_RECENT_d_2_SIZE; + unsigned int recent_d_1 : MH_DEBUG_REG29_RECENT_d_1_SIZE; + unsigned int recent_d_0 : MH_DEBUG_REG29_RECENT_d_0_SIZE; + unsigned int clnt_req : MH_DEBUG_REG29_CLNT_REQ_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG29_ARB_RTR_q_SIZE; + unsigned int arb_hold : MH_DEBUG_REG29_ARB_HOLD_SIZE; + unsigned int update_recent_stack_d : MH_DEBUG_REG29_UPDATE_RECENT_STACK_d_SIZE; + unsigned int least_recent_d : MH_DEBUG_REG29_LEAST_RECENT_d_SIZE; + unsigned int least_recent_index_d : MH_DEBUG_REG29_LEAST_RECENT_INDEX_d_SIZE; + unsigned int eff2_lru_winner_out : MH_DEBUG_REG29_EFF2_LRU_WINNER_out_SIZE; + } mh_debug_reg29_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg29_t f; +} mh_debug_reg29_u; + + +/* + * MH_DEBUG_REG30 struct + */ + +#define MH_DEBUG_REG30_TC_ARB_HOLD_SIZE 1 +#define MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SIZE 1 +#define MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SIZE 1 +#define MH_DEBUG_REG30_TCD_NEARFULL_q_SIZE 1 +#define MH_DEBUG_REG30_TCHOLD_IP_q_SIZE 1 +#define MH_DEBUG_REG30_TCHOLD_CNT_q_SIZE 3 +#define MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE 1 +#define MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SIZE 1 +#define MH_DEBUG_REG30_TC_ROQ_SEND_q_SIZE 1 +#define MH_DEBUG_REG30_TC_MH_written_SIZE 1 +#define MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SIZE 7 +#define MH_DEBUG_REG30_WBURST_ACTIVE_SIZE 1 +#define MH_DEBUG_REG30_WLAST_q_SIZE 1 +#define MH_DEBUG_REG30_WBURST_IP_q_SIZE 1 +#define MH_DEBUG_REG30_WBURST_CNT_q_SIZE 3 +#define MH_DEBUG_REG30_CP_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG30_CP_MH_write_SIZE 1 +#define MH_DEBUG_REG30_RB_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG30_PA_SEND_QUAL_SIZE 1 +#define MH_DEBUG_REG30_ARB_WINNER_SIZE 3 + +#define MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT 0 +#define MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT 1 +#define MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT 2 +#define MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT 3 +#define MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT 4 +#define MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT 5 +#define MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT 8 +#define MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT 9 +#define MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT 10 +#define MH_DEBUG_REG30_TC_MH_written_SHIFT 11 +#define MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT 12 +#define MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT 19 +#define MH_DEBUG_REG30_WLAST_q_SHIFT 20 +#define MH_DEBUG_REG30_WBURST_IP_q_SHIFT 21 +#define MH_DEBUG_REG30_WBURST_CNT_q_SHIFT 22 +#define MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT 25 +#define MH_DEBUG_REG30_CP_MH_write_SHIFT 26 +#define MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT 27 +#define MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT 28 +#define MH_DEBUG_REG30_ARB_WINNER_SHIFT 29 + +#define MH_DEBUG_REG30_TC_ARB_HOLD_MASK 0x00000001 +#define MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK 0x00000002 +#define MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK 0x00000004 +#define MH_DEBUG_REG30_TCD_NEARFULL_q_MASK 0x00000008 +#define MH_DEBUG_REG30_TCHOLD_IP_q_MASK 0x00000010 +#define MH_DEBUG_REG30_TCHOLD_CNT_q_MASK 0x000000e0 +#define MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK 0x00000100 +#define MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK 0x00000200 +#define MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK 0x00000400 +#define MH_DEBUG_REG30_TC_MH_written_MASK 0x00000800 +#define MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK 0x0007f000 +#define MH_DEBUG_REG30_WBURST_ACTIVE_MASK 0x00080000 +#define MH_DEBUG_REG30_WLAST_q_MASK 0x00100000 +#define MH_DEBUG_REG30_WBURST_IP_q_MASK 0x00200000 +#define MH_DEBUG_REG30_WBURST_CNT_q_MASK 0x01c00000 +#define MH_DEBUG_REG30_CP_SEND_QUAL_MASK 0x02000000 +#define MH_DEBUG_REG30_CP_MH_write_MASK 0x04000000 +#define MH_DEBUG_REG30_RB_SEND_QUAL_MASK 0x08000000 +#define MH_DEBUG_REG30_PA_SEND_QUAL_MASK 0x10000000 +#define MH_DEBUG_REG30_ARB_WINNER_MASK 0xe0000000 + +#define MH_DEBUG_REG30_MASK \ + (MH_DEBUG_REG30_TC_ARB_HOLD_MASK | \ + MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK | \ + MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK | \ + MH_DEBUG_REG30_TCD_NEARFULL_q_MASK | \ + MH_DEBUG_REG30_TCHOLD_IP_q_MASK | \ + MH_DEBUG_REG30_TCHOLD_CNT_q_MASK | \ + MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK | \ + MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK | \ + MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK | \ + MH_DEBUG_REG30_TC_MH_written_MASK | \ + MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK | \ + MH_DEBUG_REG30_WBURST_ACTIVE_MASK | \ + MH_DEBUG_REG30_WLAST_q_MASK | \ + MH_DEBUG_REG30_WBURST_IP_q_MASK | \ + MH_DEBUG_REG30_WBURST_CNT_q_MASK | \ + MH_DEBUG_REG30_CP_SEND_QUAL_MASK | \ + MH_DEBUG_REG30_CP_MH_write_MASK | \ + MH_DEBUG_REG30_RB_SEND_QUAL_MASK | \ + MH_DEBUG_REG30_PA_SEND_QUAL_MASK | \ + MH_DEBUG_REG30_ARB_WINNER_MASK) + +#define MH_DEBUG_REG30(tc_arb_hold, tc_noroq_same_row_bank, tc_roq_same_row_bank, tcd_nearfull_q, tchold_ip_q, tchold_cnt_q, mh_arbiter_config_tc_reorder_enable, tc_roq_rtr_dbg_q, tc_roq_send_q, tc_mh_written, tcd_fullness_cnt_q, wburst_active, wlast_q, wburst_ip_q, wburst_cnt_q, cp_send_qual, cp_mh_write, rb_send_qual, pa_send_qual, arb_winner) \ + ((tc_arb_hold << MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT) | \ + (tc_noroq_same_row_bank << MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT) | \ + (tc_roq_same_row_bank << MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT) | \ + (tcd_nearfull_q << MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT) | \ + (tchold_ip_q << MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT) | \ + (tchold_cnt_q << MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT) | \ + (mh_arbiter_config_tc_reorder_enable << MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) | \ + (tc_roq_rtr_dbg_q << MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT) | \ + (tc_roq_send_q << MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT) | \ + (tc_mh_written << MH_DEBUG_REG30_TC_MH_written_SHIFT) | \ + (tcd_fullness_cnt_q << MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT) | \ + (wburst_active << MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT) | \ + (wlast_q << MH_DEBUG_REG30_WLAST_q_SHIFT) | \ + (wburst_ip_q << MH_DEBUG_REG30_WBURST_IP_q_SHIFT) | \ + (wburst_cnt_q << MH_DEBUG_REG30_WBURST_CNT_q_SHIFT) | \ + (cp_send_qual << MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT) | \ + (cp_mh_write << MH_DEBUG_REG30_CP_MH_write_SHIFT) | \ + (rb_send_qual << MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT) | \ + (pa_send_qual << MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT) | \ + (arb_winner << MH_DEBUG_REG30_ARB_WINNER_SHIFT)) + +#define MH_DEBUG_REG30_GET_TC_ARB_HOLD(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ARB_HOLD_MASK) >> MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG30_GET_TC_NOROQ_SAME_ROW_BANK(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG30_GET_TC_ROQ_SAME_ROW_BANK(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG30_GET_TCD_NEARFULL_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TCD_NEARFULL_q_MASK) >> MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG30_GET_TCHOLD_IP_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TCHOLD_IP_q_MASK) >> MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT) +#define MH_DEBUG_REG30_GET_TCHOLD_CNT_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TCHOLD_CNT_q_MASK) >> MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT) +#define MH_DEBUG_REG30_GET_MH_ARBITER_CONFIG_TC_REORDER_ENABLE(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) >> MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) +#define MH_DEBUG_REG30_GET_TC_ROQ_RTR_DBG_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK) >> MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT) +#define MH_DEBUG_REG30_GET_TC_ROQ_SEND_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK) >> MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG30_GET_TC_MH_written(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TC_MH_written_MASK) >> MH_DEBUG_REG30_TC_MH_written_SHIFT) +#define MH_DEBUG_REG30_GET_TCD_FULLNESS_CNT_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK) >> MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT) +#define MH_DEBUG_REG30_GET_WBURST_ACTIVE(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_WBURST_ACTIVE_MASK) >> MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT) +#define MH_DEBUG_REG30_GET_WLAST_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_WLAST_q_MASK) >> MH_DEBUG_REG30_WLAST_q_SHIFT) +#define MH_DEBUG_REG30_GET_WBURST_IP_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_WBURST_IP_q_MASK) >> MH_DEBUG_REG30_WBURST_IP_q_SHIFT) +#define MH_DEBUG_REG30_GET_WBURST_CNT_q(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_WBURST_CNT_q_MASK) >> MH_DEBUG_REG30_WBURST_CNT_q_SHIFT) +#define MH_DEBUG_REG30_GET_CP_SEND_QUAL(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_CP_SEND_QUAL_MASK) >> MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG30_GET_CP_MH_write(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_CP_MH_write_MASK) >> MH_DEBUG_REG30_CP_MH_write_SHIFT) +#define MH_DEBUG_REG30_GET_RB_SEND_QUAL(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_RB_SEND_QUAL_MASK) >> MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG30_GET_PA_SEND_QUAL(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_PA_SEND_QUAL_MASK) >> MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG30_GET_ARB_WINNER(mh_debug_reg30) \ + ((mh_debug_reg30 & MH_DEBUG_REG30_ARB_WINNER_MASK) >> MH_DEBUG_REG30_ARB_WINNER_SHIFT) + +#define MH_DEBUG_REG30_SET_TC_ARB_HOLD(mh_debug_reg30_reg, tc_arb_hold) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ARB_HOLD_MASK) | (tc_arb_hold << MH_DEBUG_REG30_TC_ARB_HOLD_SHIFT) +#define MH_DEBUG_REG30_SET_TC_NOROQ_SAME_ROW_BANK(mh_debug_reg30_reg, tc_noroq_same_row_bank) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_MASK) | (tc_noroq_same_row_bank << MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG30_SET_TC_ROQ_SAME_ROW_BANK(mh_debug_reg30_reg, tc_roq_same_row_bank) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_MASK) | (tc_roq_same_row_bank << MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG30_SET_TCD_NEARFULL_q(mh_debug_reg30_reg, tcd_nearfull_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCD_NEARFULL_q_MASK) | (tcd_nearfull_q << MH_DEBUG_REG30_TCD_NEARFULL_q_SHIFT) +#define MH_DEBUG_REG30_SET_TCHOLD_IP_q(mh_debug_reg30_reg, tchold_ip_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCHOLD_IP_q_MASK) | (tchold_ip_q << MH_DEBUG_REG30_TCHOLD_IP_q_SHIFT) +#define MH_DEBUG_REG30_SET_TCHOLD_CNT_q(mh_debug_reg30_reg, tchold_cnt_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCHOLD_CNT_q_MASK) | (tchold_cnt_q << MH_DEBUG_REG30_TCHOLD_CNT_q_SHIFT) +#define MH_DEBUG_REG30_SET_MH_ARBITER_CONFIG_TC_REORDER_ENABLE(mh_debug_reg30_reg, mh_arbiter_config_tc_reorder_enable) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_MASK) | (mh_arbiter_config_tc_reorder_enable << MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SHIFT) +#define MH_DEBUG_REG30_SET_TC_ROQ_RTR_DBG_q(mh_debug_reg30_reg, tc_roq_rtr_dbg_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_MASK) | (tc_roq_rtr_dbg_q << MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SHIFT) +#define MH_DEBUG_REG30_SET_TC_ROQ_SEND_q(mh_debug_reg30_reg, tc_roq_send_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_ROQ_SEND_q_MASK) | (tc_roq_send_q << MH_DEBUG_REG30_TC_ROQ_SEND_q_SHIFT) +#define MH_DEBUG_REG30_SET_TC_MH_written(mh_debug_reg30_reg, tc_mh_written) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TC_MH_written_MASK) | (tc_mh_written << MH_DEBUG_REG30_TC_MH_written_SHIFT) +#define MH_DEBUG_REG30_SET_TCD_FULLNESS_CNT_q(mh_debug_reg30_reg, tcd_fullness_cnt_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_MASK) | (tcd_fullness_cnt_q << MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SHIFT) +#define MH_DEBUG_REG30_SET_WBURST_ACTIVE(mh_debug_reg30_reg, wburst_active) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WBURST_ACTIVE_MASK) | (wburst_active << MH_DEBUG_REG30_WBURST_ACTIVE_SHIFT) +#define MH_DEBUG_REG30_SET_WLAST_q(mh_debug_reg30_reg, wlast_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WLAST_q_MASK) | (wlast_q << MH_DEBUG_REG30_WLAST_q_SHIFT) +#define MH_DEBUG_REG30_SET_WBURST_IP_q(mh_debug_reg30_reg, wburst_ip_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WBURST_IP_q_MASK) | (wburst_ip_q << MH_DEBUG_REG30_WBURST_IP_q_SHIFT) +#define MH_DEBUG_REG30_SET_WBURST_CNT_q(mh_debug_reg30_reg, wburst_cnt_q) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_WBURST_CNT_q_MASK) | (wburst_cnt_q << MH_DEBUG_REG30_WBURST_CNT_q_SHIFT) +#define MH_DEBUG_REG30_SET_CP_SEND_QUAL(mh_debug_reg30_reg, cp_send_qual) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_CP_SEND_QUAL_MASK) | (cp_send_qual << MH_DEBUG_REG30_CP_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG30_SET_CP_MH_write(mh_debug_reg30_reg, cp_mh_write) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_CP_MH_write_MASK) | (cp_mh_write << MH_DEBUG_REG30_CP_MH_write_SHIFT) +#define MH_DEBUG_REG30_SET_RB_SEND_QUAL(mh_debug_reg30_reg, rb_send_qual) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_RB_SEND_QUAL_MASK) | (rb_send_qual << MH_DEBUG_REG30_RB_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG30_SET_PA_SEND_QUAL(mh_debug_reg30_reg, pa_send_qual) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_PA_SEND_QUAL_MASK) | (pa_send_qual << MH_DEBUG_REG30_PA_SEND_QUAL_SHIFT) +#define MH_DEBUG_REG30_SET_ARB_WINNER(mh_debug_reg30_reg, arb_winner) \ + mh_debug_reg30_reg = (mh_debug_reg30_reg & ~MH_DEBUG_REG30_ARB_WINNER_MASK) | (arb_winner << MH_DEBUG_REG30_ARB_WINNER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg30_t { + unsigned int tc_arb_hold : MH_DEBUG_REG30_TC_ARB_HOLD_SIZE; + unsigned int tc_noroq_same_row_bank : MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SIZE; + unsigned int tc_roq_same_row_bank : MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG30_TCD_NEARFULL_q_SIZE; + unsigned int tchold_ip_q : MH_DEBUG_REG30_TCHOLD_IP_q_SIZE; + unsigned int tchold_cnt_q : MH_DEBUG_REG30_TCHOLD_CNT_q_SIZE; + unsigned int mh_arbiter_config_tc_reorder_enable : MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE; + unsigned int tc_roq_rtr_dbg_q : MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG30_TC_ROQ_SEND_q_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG30_TC_MH_written_SIZE; + unsigned int tcd_fullness_cnt_q : MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SIZE; + unsigned int wburst_active : MH_DEBUG_REG30_WBURST_ACTIVE_SIZE; + unsigned int wlast_q : MH_DEBUG_REG30_WLAST_q_SIZE; + unsigned int wburst_ip_q : MH_DEBUG_REG30_WBURST_IP_q_SIZE; + unsigned int wburst_cnt_q : MH_DEBUG_REG30_WBURST_CNT_q_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG30_CP_SEND_QUAL_SIZE; + unsigned int cp_mh_write : MH_DEBUG_REG30_CP_MH_write_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG30_RB_SEND_QUAL_SIZE; + unsigned int pa_send_qual : MH_DEBUG_REG30_PA_SEND_QUAL_SIZE; + unsigned int arb_winner : MH_DEBUG_REG30_ARB_WINNER_SIZE; + } mh_debug_reg30_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg30_t { + unsigned int arb_winner : MH_DEBUG_REG30_ARB_WINNER_SIZE; + unsigned int pa_send_qual : MH_DEBUG_REG30_PA_SEND_QUAL_SIZE; + unsigned int rb_send_qual : MH_DEBUG_REG30_RB_SEND_QUAL_SIZE; + unsigned int cp_mh_write : MH_DEBUG_REG30_CP_MH_write_SIZE; + unsigned int cp_send_qual : MH_DEBUG_REG30_CP_SEND_QUAL_SIZE; + unsigned int wburst_cnt_q : MH_DEBUG_REG30_WBURST_CNT_q_SIZE; + unsigned int wburst_ip_q : MH_DEBUG_REG30_WBURST_IP_q_SIZE; + unsigned int wlast_q : MH_DEBUG_REG30_WLAST_q_SIZE; + unsigned int wburst_active : MH_DEBUG_REG30_WBURST_ACTIVE_SIZE; + unsigned int tcd_fullness_cnt_q : MH_DEBUG_REG30_TCD_FULLNESS_CNT_q_SIZE; + unsigned int tc_mh_written : MH_DEBUG_REG30_TC_MH_written_SIZE; + unsigned int tc_roq_send_q : MH_DEBUG_REG30_TC_ROQ_SEND_q_SIZE; + unsigned int tc_roq_rtr_dbg_q : MH_DEBUG_REG30_TC_ROQ_RTR_DBG_q_SIZE; + unsigned int mh_arbiter_config_tc_reorder_enable : MH_DEBUG_REG30_MH_ARBITER_CONFIG_TC_REORDER_ENABLE_SIZE; + unsigned int tchold_cnt_q : MH_DEBUG_REG30_TCHOLD_CNT_q_SIZE; + unsigned int tchold_ip_q : MH_DEBUG_REG30_TCHOLD_IP_q_SIZE; + unsigned int tcd_nearfull_q : MH_DEBUG_REG30_TCD_NEARFULL_q_SIZE; + unsigned int tc_roq_same_row_bank : MH_DEBUG_REG30_TC_ROQ_SAME_ROW_BANK_SIZE; + unsigned int tc_noroq_same_row_bank : MH_DEBUG_REG30_TC_NOROQ_SAME_ROW_BANK_SIZE; + unsigned int tc_arb_hold : MH_DEBUG_REG30_TC_ARB_HOLD_SIZE; + } mh_debug_reg30_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg30_t f; +} mh_debug_reg30_u; + + +/* + * MH_DEBUG_REG31 struct + */ + +#define MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SIZE 26 +#define MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3 + +#define MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT 0 +#define MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 26 + +#define MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK 0x03ffffff +#define MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0x1c000000 + +#define MH_DEBUG_REG31_MASK \ + (MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK | \ + MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) + +#define MH_DEBUG_REG31(rf_arbiter_config_q, mh_clnt_axi_id_reuse_mmur_id) \ + ((rf_arbiter_config_q << MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT) | \ + (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)) + +#define MH_DEBUG_REG31_GET_RF_ARBITER_CONFIG_q(mh_debug_reg31) \ + ((mh_debug_reg31 & MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK) >> MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT) +#define MH_DEBUG_REG31_GET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg31) \ + ((mh_debug_reg31 & MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) + +#define MH_DEBUG_REG31_SET_RF_ARBITER_CONFIG_q(mh_debug_reg31_reg, rf_arbiter_config_q) \ + mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_MASK) | (rf_arbiter_config_q << MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SHIFT) +#define MH_DEBUG_REG31_SET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg31_reg, mh_clnt_axi_id_reuse_mmur_id) \ + mh_debug_reg31_reg = (mh_debug_reg31_reg & ~MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg31_t { + unsigned int rf_arbiter_config_q : MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SIZE; + unsigned int mh_clnt_axi_id_reuse_mmur_id : MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int : 3; + } mh_debug_reg31_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg31_t { + unsigned int : 3; + unsigned int mh_clnt_axi_id_reuse_mmur_id : MH_DEBUG_REG31_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int rf_arbiter_config_q : MH_DEBUG_REG31_RF_ARBITER_CONFIG_q_SIZE; + } mh_debug_reg31_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg31_t f; +} mh_debug_reg31_u; + + +/* + * MH_DEBUG_REG32 struct + */ + +#define MH_DEBUG_REG32_SAME_ROW_BANK_q_SIZE 8 +#define MH_DEBUG_REG32_ROQ_MARK_q_SIZE 8 +#define MH_DEBUG_REG32_ROQ_VALID_q_SIZE 8 +#define MH_DEBUG_REG32_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG32_KILL_EFF1_SIZE 1 +#define MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SIZE 1 +#define MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SIZE 1 +#define MH_DEBUG_REG32_TC_EFF1_QUAL_SIZE 1 +#define MH_DEBUG_REG32_TC_ROQ_EMPTY_SIZE 1 +#define MH_DEBUG_REG32_TC_ROQ_FULL_SIZE 1 + +#define MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT 0 +#define MH_DEBUG_REG32_ROQ_MARK_q_SHIFT 8 +#define MH_DEBUG_REG32_ROQ_VALID_q_SHIFT 16 +#define MH_DEBUG_REG32_TC_MH_send_SHIFT 24 +#define MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT 25 +#define MH_DEBUG_REG32_KILL_EFF1_SHIFT 26 +#define MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT 27 +#define MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT 28 +#define MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT 29 +#define MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT 30 +#define MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT 31 + +#define MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK 0x000000ff +#define MH_DEBUG_REG32_ROQ_MARK_q_MASK 0x0000ff00 +#define MH_DEBUG_REG32_ROQ_VALID_q_MASK 0x00ff0000 +#define MH_DEBUG_REG32_TC_MH_send_MASK 0x01000000 +#define MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK 0x02000000 +#define MH_DEBUG_REG32_KILL_EFF1_MASK 0x04000000 +#define MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000 +#define MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK 0x10000000 +#define MH_DEBUG_REG32_TC_EFF1_QUAL_MASK 0x20000000 +#define MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK 0x40000000 +#define MH_DEBUG_REG32_TC_ROQ_FULL_MASK 0x80000000 + +#define MH_DEBUG_REG32_MASK \ + (MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK | \ + MH_DEBUG_REG32_ROQ_MARK_q_MASK | \ + MH_DEBUG_REG32_ROQ_VALID_q_MASK | \ + MH_DEBUG_REG32_TC_MH_send_MASK | \ + MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG32_KILL_EFF1_MASK | \ + MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK | \ + MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK | \ + MH_DEBUG_REG32_TC_EFF1_QUAL_MASK | \ + MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK | \ + MH_DEBUG_REG32_TC_ROQ_FULL_MASK) + +#define MH_DEBUG_REG32(same_row_bank_q, roq_mark_q, roq_valid_q, tc_mh_send, tc_roq_rtr_q, kill_eff1, tc_roq_same_row_bank_sel, any_same_row_bank, tc_eff1_qual, tc_roq_empty, tc_roq_full) \ + ((same_row_bank_q << MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT) | \ + (roq_mark_q << MH_DEBUG_REG32_ROQ_MARK_q_SHIFT) | \ + (roq_valid_q << MH_DEBUG_REG32_ROQ_VALID_q_SHIFT) | \ + (tc_mh_send << MH_DEBUG_REG32_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT) | \ + (kill_eff1 << MH_DEBUG_REG32_KILL_EFF1_SHIFT) | \ + (tc_roq_same_row_bank_sel << MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) | \ + (any_same_row_bank << MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT) | \ + (tc_eff1_qual << MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT) | \ + (tc_roq_empty << MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT) | \ + (tc_roq_full << MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT)) + +#define MH_DEBUG_REG32_GET_SAME_ROW_BANK_q(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK) >> MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT) +#define MH_DEBUG_REG32_GET_ROQ_MARK_q(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_ROQ_MARK_q_MASK) >> MH_DEBUG_REG32_ROQ_MARK_q_SHIFT) +#define MH_DEBUG_REG32_GET_ROQ_VALID_q(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_ROQ_VALID_q_MASK) >> MH_DEBUG_REG32_ROQ_VALID_q_SHIFT) +#define MH_DEBUG_REG32_GET_TC_MH_send(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_TC_MH_send_MASK) >> MH_DEBUG_REG32_TC_MH_send_SHIFT) +#define MH_DEBUG_REG32_GET_TC_ROQ_RTR_q(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG32_GET_KILL_EFF1(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_KILL_EFF1_MASK) >> MH_DEBUG_REG32_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG32_GET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK) >> MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) +#define MH_DEBUG_REG32_GET_ANY_SAME_ROW_BANK(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG32_GET_TC_EFF1_QUAL(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_TC_EFF1_QUAL_MASK) >> MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG32_GET_TC_ROQ_EMPTY(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG32_GET_TC_ROQ_FULL(mh_debug_reg32) \ + ((mh_debug_reg32 & MH_DEBUG_REG32_TC_ROQ_FULL_MASK) >> MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT) + +#define MH_DEBUG_REG32_SET_SAME_ROW_BANK_q(mh_debug_reg32_reg, same_row_bank_q) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_SAME_ROW_BANK_q_MASK) | (same_row_bank_q << MH_DEBUG_REG32_SAME_ROW_BANK_q_SHIFT) +#define MH_DEBUG_REG32_SET_ROQ_MARK_q(mh_debug_reg32_reg, roq_mark_q) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ROQ_MARK_q_MASK) | (roq_mark_q << MH_DEBUG_REG32_ROQ_MARK_q_SHIFT) +#define MH_DEBUG_REG32_SET_ROQ_VALID_q(mh_debug_reg32_reg, roq_valid_q) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ROQ_VALID_q_MASK) | (roq_valid_q << MH_DEBUG_REG32_ROQ_VALID_q_SHIFT) +#define MH_DEBUG_REG32_SET_TC_MH_send(mh_debug_reg32_reg, tc_mh_send) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG32_TC_MH_send_SHIFT) +#define MH_DEBUG_REG32_SET_TC_ROQ_RTR_q(mh_debug_reg32_reg, tc_roq_rtr_q) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG32_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG32_SET_KILL_EFF1(mh_debug_reg32_reg, kill_eff1) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG32_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG32_SET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg32_reg, tc_roq_same_row_bank_sel) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_MASK) | (tc_roq_same_row_bank_sel << MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) +#define MH_DEBUG_REG32_SET_ANY_SAME_ROW_BANK(mh_debug_reg32_reg, any_same_row_bank) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_ANY_SAME_ROW_BANK_MASK) | (any_same_row_bank << MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG32_SET_TC_EFF1_QUAL(mh_debug_reg32_reg, tc_eff1_qual) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_EFF1_QUAL_MASK) | (tc_eff1_qual << MH_DEBUG_REG32_TC_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG32_SET_TC_ROQ_EMPTY(mh_debug_reg32_reg, tc_roq_empty) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG32_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG32_SET_TC_ROQ_FULL(mh_debug_reg32_reg, tc_roq_full) \ + mh_debug_reg32_reg = (mh_debug_reg32_reg & ~MH_DEBUG_REG32_TC_ROQ_FULL_MASK) | (tc_roq_full << MH_DEBUG_REG32_TC_ROQ_FULL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg32_t { + unsigned int same_row_bank_q : MH_DEBUG_REG32_SAME_ROW_BANK_q_SIZE; + unsigned int roq_mark_q : MH_DEBUG_REG32_ROQ_MARK_q_SIZE; + unsigned int roq_valid_q : MH_DEBUG_REG32_ROQ_VALID_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG32_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG32_KILL_EFF1_SIZE; + unsigned int tc_roq_same_row_bank_sel : MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SIZE; + unsigned int any_same_row_bank : MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SIZE; + unsigned int tc_eff1_qual : MH_DEBUG_REG32_TC_EFF1_QUAL_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG32_TC_ROQ_EMPTY_SIZE; + unsigned int tc_roq_full : MH_DEBUG_REG32_TC_ROQ_FULL_SIZE; + } mh_debug_reg32_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg32_t { + unsigned int tc_roq_full : MH_DEBUG_REG32_TC_ROQ_FULL_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG32_TC_ROQ_EMPTY_SIZE; + unsigned int tc_eff1_qual : MH_DEBUG_REG32_TC_EFF1_QUAL_SIZE; + unsigned int any_same_row_bank : MH_DEBUG_REG32_ANY_SAME_ROW_BANK_SIZE; + unsigned int tc_roq_same_row_bank_sel : MH_DEBUG_REG32_TC_ROQ_SAME_ROW_BANK_SEL_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG32_KILL_EFF1_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG32_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG32_TC_MH_send_SIZE; + unsigned int roq_valid_q : MH_DEBUG_REG32_ROQ_VALID_q_SIZE; + unsigned int roq_mark_q : MH_DEBUG_REG32_ROQ_MARK_q_SIZE; + unsigned int same_row_bank_q : MH_DEBUG_REG32_SAME_ROW_BANK_q_SIZE; + } mh_debug_reg32_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg32_t f; +} mh_debug_reg32_u; + + +/* + * MH_DEBUG_REG33 struct + */ + +#define MH_DEBUG_REG33_SAME_ROW_BANK_q_SIZE 8 +#define MH_DEBUG_REG33_ROQ_MARK_d_SIZE 8 +#define MH_DEBUG_REG33_ROQ_VALID_d_SIZE 8 +#define MH_DEBUG_REG33_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG33_KILL_EFF1_SIZE 1 +#define MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SIZE 1 +#define MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SIZE 1 +#define MH_DEBUG_REG33_TC_EFF1_QUAL_SIZE 1 +#define MH_DEBUG_REG33_TC_ROQ_EMPTY_SIZE 1 +#define MH_DEBUG_REG33_TC_ROQ_FULL_SIZE 1 + +#define MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT 0 +#define MH_DEBUG_REG33_ROQ_MARK_d_SHIFT 8 +#define MH_DEBUG_REG33_ROQ_VALID_d_SHIFT 16 +#define MH_DEBUG_REG33_TC_MH_send_SHIFT 24 +#define MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT 25 +#define MH_DEBUG_REG33_KILL_EFF1_SHIFT 26 +#define MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT 27 +#define MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT 28 +#define MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT 29 +#define MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT 30 +#define MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT 31 + +#define MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK 0x000000ff +#define MH_DEBUG_REG33_ROQ_MARK_d_MASK 0x0000ff00 +#define MH_DEBUG_REG33_ROQ_VALID_d_MASK 0x00ff0000 +#define MH_DEBUG_REG33_TC_MH_send_MASK 0x01000000 +#define MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK 0x02000000 +#define MH_DEBUG_REG33_KILL_EFF1_MASK 0x04000000 +#define MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK 0x08000000 +#define MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK 0x10000000 +#define MH_DEBUG_REG33_TC_EFF1_QUAL_MASK 0x20000000 +#define MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK 0x40000000 +#define MH_DEBUG_REG33_TC_ROQ_FULL_MASK 0x80000000 + +#define MH_DEBUG_REG33_MASK \ + (MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK | \ + MH_DEBUG_REG33_ROQ_MARK_d_MASK | \ + MH_DEBUG_REG33_ROQ_VALID_d_MASK | \ + MH_DEBUG_REG33_TC_MH_send_MASK | \ + MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG33_KILL_EFF1_MASK | \ + MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK | \ + MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK | \ + MH_DEBUG_REG33_TC_EFF1_QUAL_MASK | \ + MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK | \ + MH_DEBUG_REG33_TC_ROQ_FULL_MASK) + +#define MH_DEBUG_REG33(same_row_bank_q, roq_mark_d, roq_valid_d, tc_mh_send, tc_roq_rtr_q, kill_eff1, tc_roq_same_row_bank_sel, any_same_row_bank, tc_eff1_qual, tc_roq_empty, tc_roq_full) \ + ((same_row_bank_q << MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT) | \ + (roq_mark_d << MH_DEBUG_REG33_ROQ_MARK_d_SHIFT) | \ + (roq_valid_d << MH_DEBUG_REG33_ROQ_VALID_d_SHIFT) | \ + (tc_mh_send << MH_DEBUG_REG33_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT) | \ + (kill_eff1 << MH_DEBUG_REG33_KILL_EFF1_SHIFT) | \ + (tc_roq_same_row_bank_sel << MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) | \ + (any_same_row_bank << MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT) | \ + (tc_eff1_qual << MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT) | \ + (tc_roq_empty << MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT) | \ + (tc_roq_full << MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT)) + +#define MH_DEBUG_REG33_GET_SAME_ROW_BANK_q(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK) >> MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT) +#define MH_DEBUG_REG33_GET_ROQ_MARK_d(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_ROQ_MARK_d_MASK) >> MH_DEBUG_REG33_ROQ_MARK_d_SHIFT) +#define MH_DEBUG_REG33_GET_ROQ_VALID_d(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_ROQ_VALID_d_MASK) >> MH_DEBUG_REG33_ROQ_VALID_d_SHIFT) +#define MH_DEBUG_REG33_GET_TC_MH_send(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_TC_MH_send_MASK) >> MH_DEBUG_REG33_TC_MH_send_SHIFT) +#define MH_DEBUG_REG33_GET_TC_ROQ_RTR_q(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG33_GET_KILL_EFF1(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_KILL_EFF1_MASK) >> MH_DEBUG_REG33_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG33_GET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK) >> MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) +#define MH_DEBUG_REG33_GET_ANY_SAME_ROW_BANK(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK) >> MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG33_GET_TC_EFF1_QUAL(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_TC_EFF1_QUAL_MASK) >> MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG33_GET_TC_ROQ_EMPTY(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK) >> MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG33_GET_TC_ROQ_FULL(mh_debug_reg33) \ + ((mh_debug_reg33 & MH_DEBUG_REG33_TC_ROQ_FULL_MASK) >> MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT) + +#define MH_DEBUG_REG33_SET_SAME_ROW_BANK_q(mh_debug_reg33_reg, same_row_bank_q) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_SAME_ROW_BANK_q_MASK) | (same_row_bank_q << MH_DEBUG_REG33_SAME_ROW_BANK_q_SHIFT) +#define MH_DEBUG_REG33_SET_ROQ_MARK_d(mh_debug_reg33_reg, roq_mark_d) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ROQ_MARK_d_MASK) | (roq_mark_d << MH_DEBUG_REG33_ROQ_MARK_d_SHIFT) +#define MH_DEBUG_REG33_SET_ROQ_VALID_d(mh_debug_reg33_reg, roq_valid_d) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ROQ_VALID_d_MASK) | (roq_valid_d << MH_DEBUG_REG33_ROQ_VALID_d_SHIFT) +#define MH_DEBUG_REG33_SET_TC_MH_send(mh_debug_reg33_reg, tc_mh_send) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG33_TC_MH_send_SHIFT) +#define MH_DEBUG_REG33_SET_TC_ROQ_RTR_q(mh_debug_reg33_reg, tc_roq_rtr_q) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG33_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG33_SET_KILL_EFF1(mh_debug_reg33_reg, kill_eff1) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_KILL_EFF1_MASK) | (kill_eff1 << MH_DEBUG_REG33_KILL_EFF1_SHIFT) +#define MH_DEBUG_REG33_SET_TC_ROQ_SAME_ROW_BANK_SEL(mh_debug_reg33_reg, tc_roq_same_row_bank_sel) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_MASK) | (tc_roq_same_row_bank_sel << MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SHIFT) +#define MH_DEBUG_REG33_SET_ANY_SAME_ROW_BANK(mh_debug_reg33_reg, any_same_row_bank) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_ANY_SAME_ROW_BANK_MASK) | (any_same_row_bank << MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SHIFT) +#define MH_DEBUG_REG33_SET_TC_EFF1_QUAL(mh_debug_reg33_reg, tc_eff1_qual) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_EFF1_QUAL_MASK) | (tc_eff1_qual << MH_DEBUG_REG33_TC_EFF1_QUAL_SHIFT) +#define MH_DEBUG_REG33_SET_TC_ROQ_EMPTY(mh_debug_reg33_reg, tc_roq_empty) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_EMPTY_MASK) | (tc_roq_empty << MH_DEBUG_REG33_TC_ROQ_EMPTY_SHIFT) +#define MH_DEBUG_REG33_SET_TC_ROQ_FULL(mh_debug_reg33_reg, tc_roq_full) \ + mh_debug_reg33_reg = (mh_debug_reg33_reg & ~MH_DEBUG_REG33_TC_ROQ_FULL_MASK) | (tc_roq_full << MH_DEBUG_REG33_TC_ROQ_FULL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg33_t { + unsigned int same_row_bank_q : MH_DEBUG_REG33_SAME_ROW_BANK_q_SIZE; + unsigned int roq_mark_d : MH_DEBUG_REG33_ROQ_MARK_d_SIZE; + unsigned int roq_valid_d : MH_DEBUG_REG33_ROQ_VALID_d_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG33_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG33_KILL_EFF1_SIZE; + unsigned int tc_roq_same_row_bank_sel : MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SIZE; + unsigned int any_same_row_bank : MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SIZE; + unsigned int tc_eff1_qual : MH_DEBUG_REG33_TC_EFF1_QUAL_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG33_TC_ROQ_EMPTY_SIZE; + unsigned int tc_roq_full : MH_DEBUG_REG33_TC_ROQ_FULL_SIZE; + } mh_debug_reg33_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg33_t { + unsigned int tc_roq_full : MH_DEBUG_REG33_TC_ROQ_FULL_SIZE; + unsigned int tc_roq_empty : MH_DEBUG_REG33_TC_ROQ_EMPTY_SIZE; + unsigned int tc_eff1_qual : MH_DEBUG_REG33_TC_EFF1_QUAL_SIZE; + unsigned int any_same_row_bank : MH_DEBUG_REG33_ANY_SAME_ROW_BANK_SIZE; + unsigned int tc_roq_same_row_bank_sel : MH_DEBUG_REG33_TC_ROQ_SAME_ROW_BANK_SEL_SIZE; + unsigned int kill_eff1 : MH_DEBUG_REG33_KILL_EFF1_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG33_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG33_TC_MH_send_SIZE; + unsigned int roq_valid_d : MH_DEBUG_REG33_ROQ_VALID_d_SIZE; + unsigned int roq_mark_d : MH_DEBUG_REG33_ROQ_MARK_d_SIZE; + unsigned int same_row_bank_q : MH_DEBUG_REG33_SAME_ROW_BANK_q_SIZE; + } mh_debug_reg33_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg33_t f; +} mh_debug_reg33_u; + + +/* + * MH_DEBUG_REG34 struct + */ + +#define MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SIZE 8 +#define MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SIZE 8 +#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SIZE 8 +#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SIZE 8 + +#define MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT 0 +#define MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT 8 +#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT 16 +#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT 24 + +#define MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK 0x000000ff +#define MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK 0x0000ff00 +#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK 0x00ff0000 +#define MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK 0xff000000 + +#define MH_DEBUG_REG34_MASK \ + (MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK | \ + MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK | \ + MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK | \ + MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK) + +#define MH_DEBUG_REG34(same_row_bank_win, same_row_bank_req, non_same_row_bank_win, non_same_row_bank_req) \ + ((same_row_bank_win << MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT) | \ + (same_row_bank_req << MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT) | \ + (non_same_row_bank_win << MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT) | \ + (non_same_row_bank_req << MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT)) + +#define MH_DEBUG_REG34_GET_SAME_ROW_BANK_WIN(mh_debug_reg34) \ + ((mh_debug_reg34 & MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK) >> MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT) +#define MH_DEBUG_REG34_GET_SAME_ROW_BANK_REQ(mh_debug_reg34) \ + ((mh_debug_reg34 & MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK) >> MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT) +#define MH_DEBUG_REG34_GET_NON_SAME_ROW_BANK_WIN(mh_debug_reg34) \ + ((mh_debug_reg34 & MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK) >> MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT) +#define MH_DEBUG_REG34_GET_NON_SAME_ROW_BANK_REQ(mh_debug_reg34) \ + ((mh_debug_reg34 & MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK) >> MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT) + +#define MH_DEBUG_REG34_SET_SAME_ROW_BANK_WIN(mh_debug_reg34_reg, same_row_bank_win) \ + mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_SAME_ROW_BANK_WIN_MASK) | (same_row_bank_win << MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SHIFT) +#define MH_DEBUG_REG34_SET_SAME_ROW_BANK_REQ(mh_debug_reg34_reg, same_row_bank_req) \ + mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_SAME_ROW_BANK_REQ_MASK) | (same_row_bank_req << MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SHIFT) +#define MH_DEBUG_REG34_SET_NON_SAME_ROW_BANK_WIN(mh_debug_reg34_reg, non_same_row_bank_win) \ + mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_MASK) | (non_same_row_bank_win << MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SHIFT) +#define MH_DEBUG_REG34_SET_NON_SAME_ROW_BANK_REQ(mh_debug_reg34_reg, non_same_row_bank_req) \ + mh_debug_reg34_reg = (mh_debug_reg34_reg & ~MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_MASK) | (non_same_row_bank_req << MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg34_t { + unsigned int same_row_bank_win : MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SIZE; + unsigned int same_row_bank_req : MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SIZE; + unsigned int non_same_row_bank_win : MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SIZE; + unsigned int non_same_row_bank_req : MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SIZE; + } mh_debug_reg34_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg34_t { + unsigned int non_same_row_bank_req : MH_DEBUG_REG34_NON_SAME_ROW_BANK_REQ_SIZE; + unsigned int non_same_row_bank_win : MH_DEBUG_REG34_NON_SAME_ROW_BANK_WIN_SIZE; + unsigned int same_row_bank_req : MH_DEBUG_REG34_SAME_ROW_BANK_REQ_SIZE; + unsigned int same_row_bank_win : MH_DEBUG_REG34_SAME_ROW_BANK_WIN_SIZE; + } mh_debug_reg34_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg34_t f; +} mh_debug_reg34_u; + + +/* + * MH_DEBUG_REG35 struct + */ + +#define MH_DEBUG_REG35_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG35_ROQ_MARK_q_0_SIZE 1 +#define MH_DEBUG_REG35_ROQ_VALID_q_0_SIZE 1 +#define MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SIZE 1 +#define MH_DEBUG_REG35_ROQ_ADDR_0_SIZE 27 + +#define MH_DEBUG_REG35_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT 2 +#define MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT 3 +#define MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT 4 +#define MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT 5 + +#define MH_DEBUG_REG35_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG35_ROQ_MARK_q_0_MASK 0x00000004 +#define MH_DEBUG_REG35_ROQ_VALID_q_0_MASK 0x00000008 +#define MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK 0x00000010 +#define MH_DEBUG_REG35_ROQ_ADDR_0_MASK 0xffffffe0 + +#define MH_DEBUG_REG35_MASK \ + (MH_DEBUG_REG35_TC_MH_send_MASK | \ + MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG35_ROQ_MARK_q_0_MASK | \ + MH_DEBUG_REG35_ROQ_VALID_q_0_MASK | \ + MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK | \ + MH_DEBUG_REG35_ROQ_ADDR_0_MASK) + +#define MH_DEBUG_REG35(tc_mh_send, tc_roq_rtr_q, roq_mark_q_0, roq_valid_q_0, same_row_bank_q_0, roq_addr_0) \ + ((tc_mh_send << MH_DEBUG_REG35_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_0 << MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT) | \ + (roq_valid_q_0 << MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT) | \ + (same_row_bank_q_0 << MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT) | \ + (roq_addr_0 << MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT)) + +#define MH_DEBUG_REG35_GET_TC_MH_send(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_TC_MH_send_MASK) >> MH_DEBUG_REG35_TC_MH_send_SHIFT) +#define MH_DEBUG_REG35_GET_TC_ROQ_RTR_q(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG35_GET_ROQ_MARK_q_0(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_MARK_q_0_MASK) >> MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT) +#define MH_DEBUG_REG35_GET_ROQ_VALID_q_0(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_VALID_q_0_MASK) >> MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT) +#define MH_DEBUG_REG35_GET_SAME_ROW_BANK_q_0(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK) >> MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT) +#define MH_DEBUG_REG35_GET_ROQ_ADDR_0(mh_debug_reg35) \ + ((mh_debug_reg35 & MH_DEBUG_REG35_ROQ_ADDR_0_MASK) >> MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT) + +#define MH_DEBUG_REG35_SET_TC_MH_send(mh_debug_reg35_reg, tc_mh_send) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG35_TC_MH_send_SHIFT) +#define MH_DEBUG_REG35_SET_TC_ROQ_RTR_q(mh_debug_reg35_reg, tc_roq_rtr_q) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG35_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG35_SET_ROQ_MARK_q_0(mh_debug_reg35_reg, roq_mark_q_0) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_MARK_q_0_MASK) | (roq_mark_q_0 << MH_DEBUG_REG35_ROQ_MARK_q_0_SHIFT) +#define MH_DEBUG_REG35_SET_ROQ_VALID_q_0(mh_debug_reg35_reg, roq_valid_q_0) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_VALID_q_0_MASK) | (roq_valid_q_0 << MH_DEBUG_REG35_ROQ_VALID_q_0_SHIFT) +#define MH_DEBUG_REG35_SET_SAME_ROW_BANK_q_0(mh_debug_reg35_reg, same_row_bank_q_0) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_SAME_ROW_BANK_q_0_MASK) | (same_row_bank_q_0 << MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SHIFT) +#define MH_DEBUG_REG35_SET_ROQ_ADDR_0(mh_debug_reg35_reg, roq_addr_0) \ + mh_debug_reg35_reg = (mh_debug_reg35_reg & ~MH_DEBUG_REG35_ROQ_ADDR_0_MASK) | (roq_addr_0 << MH_DEBUG_REG35_ROQ_ADDR_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg35_t { + unsigned int tc_mh_send : MH_DEBUG_REG35_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_0 : MH_DEBUG_REG35_ROQ_MARK_q_0_SIZE; + unsigned int roq_valid_q_0 : MH_DEBUG_REG35_ROQ_VALID_q_0_SIZE; + unsigned int same_row_bank_q_0 : MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SIZE; + unsigned int roq_addr_0 : MH_DEBUG_REG35_ROQ_ADDR_0_SIZE; + } mh_debug_reg35_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg35_t { + unsigned int roq_addr_0 : MH_DEBUG_REG35_ROQ_ADDR_0_SIZE; + unsigned int same_row_bank_q_0 : MH_DEBUG_REG35_SAME_ROW_BANK_q_0_SIZE; + unsigned int roq_valid_q_0 : MH_DEBUG_REG35_ROQ_VALID_q_0_SIZE; + unsigned int roq_mark_q_0 : MH_DEBUG_REG35_ROQ_MARK_q_0_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG35_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG35_TC_MH_send_SIZE; + } mh_debug_reg35_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg35_t f; +} mh_debug_reg35_u; + + +/* + * MH_DEBUG_REG36 struct + */ + +#define MH_DEBUG_REG36_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG36_ROQ_MARK_q_1_SIZE 1 +#define MH_DEBUG_REG36_ROQ_VALID_q_1_SIZE 1 +#define MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SIZE 1 +#define MH_DEBUG_REG36_ROQ_ADDR_1_SIZE 27 + +#define MH_DEBUG_REG36_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT 2 +#define MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT 3 +#define MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT 4 +#define MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT 5 + +#define MH_DEBUG_REG36_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG36_ROQ_MARK_q_1_MASK 0x00000004 +#define MH_DEBUG_REG36_ROQ_VALID_q_1_MASK 0x00000008 +#define MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK 0x00000010 +#define MH_DEBUG_REG36_ROQ_ADDR_1_MASK 0xffffffe0 + +#define MH_DEBUG_REG36_MASK \ + (MH_DEBUG_REG36_TC_MH_send_MASK | \ + MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG36_ROQ_MARK_q_1_MASK | \ + MH_DEBUG_REG36_ROQ_VALID_q_1_MASK | \ + MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK | \ + MH_DEBUG_REG36_ROQ_ADDR_1_MASK) + +#define MH_DEBUG_REG36(tc_mh_send, tc_roq_rtr_q, roq_mark_q_1, roq_valid_q_1, same_row_bank_q_1, roq_addr_1) \ + ((tc_mh_send << MH_DEBUG_REG36_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_1 << MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT) | \ + (roq_valid_q_1 << MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT) | \ + (same_row_bank_q_1 << MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT) | \ + (roq_addr_1 << MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT)) + +#define MH_DEBUG_REG36_GET_TC_MH_send(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_TC_MH_send_MASK) >> MH_DEBUG_REG36_TC_MH_send_SHIFT) +#define MH_DEBUG_REG36_GET_TC_ROQ_RTR_q(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG36_GET_ROQ_MARK_q_1(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_MARK_q_1_MASK) >> MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT) +#define MH_DEBUG_REG36_GET_ROQ_VALID_q_1(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_VALID_q_1_MASK) >> MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT) +#define MH_DEBUG_REG36_GET_SAME_ROW_BANK_q_1(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK) >> MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT) +#define MH_DEBUG_REG36_GET_ROQ_ADDR_1(mh_debug_reg36) \ + ((mh_debug_reg36 & MH_DEBUG_REG36_ROQ_ADDR_1_MASK) >> MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT) + +#define MH_DEBUG_REG36_SET_TC_MH_send(mh_debug_reg36_reg, tc_mh_send) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG36_TC_MH_send_SHIFT) +#define MH_DEBUG_REG36_SET_TC_ROQ_RTR_q(mh_debug_reg36_reg, tc_roq_rtr_q) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG36_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG36_SET_ROQ_MARK_q_1(mh_debug_reg36_reg, roq_mark_q_1) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_MARK_q_1_MASK) | (roq_mark_q_1 << MH_DEBUG_REG36_ROQ_MARK_q_1_SHIFT) +#define MH_DEBUG_REG36_SET_ROQ_VALID_q_1(mh_debug_reg36_reg, roq_valid_q_1) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_VALID_q_1_MASK) | (roq_valid_q_1 << MH_DEBUG_REG36_ROQ_VALID_q_1_SHIFT) +#define MH_DEBUG_REG36_SET_SAME_ROW_BANK_q_1(mh_debug_reg36_reg, same_row_bank_q_1) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_SAME_ROW_BANK_q_1_MASK) | (same_row_bank_q_1 << MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SHIFT) +#define MH_DEBUG_REG36_SET_ROQ_ADDR_1(mh_debug_reg36_reg, roq_addr_1) \ + mh_debug_reg36_reg = (mh_debug_reg36_reg & ~MH_DEBUG_REG36_ROQ_ADDR_1_MASK) | (roq_addr_1 << MH_DEBUG_REG36_ROQ_ADDR_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg36_t { + unsigned int tc_mh_send : MH_DEBUG_REG36_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_1 : MH_DEBUG_REG36_ROQ_MARK_q_1_SIZE; + unsigned int roq_valid_q_1 : MH_DEBUG_REG36_ROQ_VALID_q_1_SIZE; + unsigned int same_row_bank_q_1 : MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SIZE; + unsigned int roq_addr_1 : MH_DEBUG_REG36_ROQ_ADDR_1_SIZE; + } mh_debug_reg36_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg36_t { + unsigned int roq_addr_1 : MH_DEBUG_REG36_ROQ_ADDR_1_SIZE; + unsigned int same_row_bank_q_1 : MH_DEBUG_REG36_SAME_ROW_BANK_q_1_SIZE; + unsigned int roq_valid_q_1 : MH_DEBUG_REG36_ROQ_VALID_q_1_SIZE; + unsigned int roq_mark_q_1 : MH_DEBUG_REG36_ROQ_MARK_q_1_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG36_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG36_TC_MH_send_SIZE; + } mh_debug_reg36_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg36_t f; +} mh_debug_reg36_u; + + +/* + * MH_DEBUG_REG37 struct + */ + +#define MH_DEBUG_REG37_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG37_ROQ_MARK_q_2_SIZE 1 +#define MH_DEBUG_REG37_ROQ_VALID_q_2_SIZE 1 +#define MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SIZE 1 +#define MH_DEBUG_REG37_ROQ_ADDR_2_SIZE 27 + +#define MH_DEBUG_REG37_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT 2 +#define MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT 3 +#define MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT 4 +#define MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT 5 + +#define MH_DEBUG_REG37_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG37_ROQ_MARK_q_2_MASK 0x00000004 +#define MH_DEBUG_REG37_ROQ_VALID_q_2_MASK 0x00000008 +#define MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK 0x00000010 +#define MH_DEBUG_REG37_ROQ_ADDR_2_MASK 0xffffffe0 + +#define MH_DEBUG_REG37_MASK \ + (MH_DEBUG_REG37_TC_MH_send_MASK | \ + MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG37_ROQ_MARK_q_2_MASK | \ + MH_DEBUG_REG37_ROQ_VALID_q_2_MASK | \ + MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK | \ + MH_DEBUG_REG37_ROQ_ADDR_2_MASK) + +#define MH_DEBUG_REG37(tc_mh_send, tc_roq_rtr_q, roq_mark_q_2, roq_valid_q_2, same_row_bank_q_2, roq_addr_2) \ + ((tc_mh_send << MH_DEBUG_REG37_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_2 << MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT) | \ + (roq_valid_q_2 << MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT) | \ + (same_row_bank_q_2 << MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT) | \ + (roq_addr_2 << MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT)) + +#define MH_DEBUG_REG37_GET_TC_MH_send(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_TC_MH_send_MASK) >> MH_DEBUG_REG37_TC_MH_send_SHIFT) +#define MH_DEBUG_REG37_GET_TC_ROQ_RTR_q(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG37_GET_ROQ_MARK_q_2(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_MARK_q_2_MASK) >> MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT) +#define MH_DEBUG_REG37_GET_ROQ_VALID_q_2(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_VALID_q_2_MASK) >> MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT) +#define MH_DEBUG_REG37_GET_SAME_ROW_BANK_q_2(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK) >> MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT) +#define MH_DEBUG_REG37_GET_ROQ_ADDR_2(mh_debug_reg37) \ + ((mh_debug_reg37 & MH_DEBUG_REG37_ROQ_ADDR_2_MASK) >> MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT) + +#define MH_DEBUG_REG37_SET_TC_MH_send(mh_debug_reg37_reg, tc_mh_send) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG37_TC_MH_send_SHIFT) +#define MH_DEBUG_REG37_SET_TC_ROQ_RTR_q(mh_debug_reg37_reg, tc_roq_rtr_q) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG37_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG37_SET_ROQ_MARK_q_2(mh_debug_reg37_reg, roq_mark_q_2) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_MARK_q_2_MASK) | (roq_mark_q_2 << MH_DEBUG_REG37_ROQ_MARK_q_2_SHIFT) +#define MH_DEBUG_REG37_SET_ROQ_VALID_q_2(mh_debug_reg37_reg, roq_valid_q_2) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_VALID_q_2_MASK) | (roq_valid_q_2 << MH_DEBUG_REG37_ROQ_VALID_q_2_SHIFT) +#define MH_DEBUG_REG37_SET_SAME_ROW_BANK_q_2(mh_debug_reg37_reg, same_row_bank_q_2) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_SAME_ROW_BANK_q_2_MASK) | (same_row_bank_q_2 << MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SHIFT) +#define MH_DEBUG_REG37_SET_ROQ_ADDR_2(mh_debug_reg37_reg, roq_addr_2) \ + mh_debug_reg37_reg = (mh_debug_reg37_reg & ~MH_DEBUG_REG37_ROQ_ADDR_2_MASK) | (roq_addr_2 << MH_DEBUG_REG37_ROQ_ADDR_2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg37_t { + unsigned int tc_mh_send : MH_DEBUG_REG37_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_2 : MH_DEBUG_REG37_ROQ_MARK_q_2_SIZE; + unsigned int roq_valid_q_2 : MH_DEBUG_REG37_ROQ_VALID_q_2_SIZE; + unsigned int same_row_bank_q_2 : MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SIZE; + unsigned int roq_addr_2 : MH_DEBUG_REG37_ROQ_ADDR_2_SIZE; + } mh_debug_reg37_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg37_t { + unsigned int roq_addr_2 : MH_DEBUG_REG37_ROQ_ADDR_2_SIZE; + unsigned int same_row_bank_q_2 : MH_DEBUG_REG37_SAME_ROW_BANK_q_2_SIZE; + unsigned int roq_valid_q_2 : MH_DEBUG_REG37_ROQ_VALID_q_2_SIZE; + unsigned int roq_mark_q_2 : MH_DEBUG_REG37_ROQ_MARK_q_2_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG37_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG37_TC_MH_send_SIZE; + } mh_debug_reg37_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg37_t f; +} mh_debug_reg37_u; + + +/* + * MH_DEBUG_REG38 struct + */ + +#define MH_DEBUG_REG38_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG38_ROQ_MARK_q_3_SIZE 1 +#define MH_DEBUG_REG38_ROQ_VALID_q_3_SIZE 1 +#define MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SIZE 1 +#define MH_DEBUG_REG38_ROQ_ADDR_3_SIZE 27 + +#define MH_DEBUG_REG38_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT 2 +#define MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT 3 +#define MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT 4 +#define MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT 5 + +#define MH_DEBUG_REG38_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG38_ROQ_MARK_q_3_MASK 0x00000004 +#define MH_DEBUG_REG38_ROQ_VALID_q_3_MASK 0x00000008 +#define MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK 0x00000010 +#define MH_DEBUG_REG38_ROQ_ADDR_3_MASK 0xffffffe0 + +#define MH_DEBUG_REG38_MASK \ + (MH_DEBUG_REG38_TC_MH_send_MASK | \ + MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG38_ROQ_MARK_q_3_MASK | \ + MH_DEBUG_REG38_ROQ_VALID_q_3_MASK | \ + MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK | \ + MH_DEBUG_REG38_ROQ_ADDR_3_MASK) + +#define MH_DEBUG_REG38(tc_mh_send, tc_roq_rtr_q, roq_mark_q_3, roq_valid_q_3, same_row_bank_q_3, roq_addr_3) \ + ((tc_mh_send << MH_DEBUG_REG38_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_3 << MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT) | \ + (roq_valid_q_3 << MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT) | \ + (same_row_bank_q_3 << MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT) | \ + (roq_addr_3 << MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT)) + +#define MH_DEBUG_REG38_GET_TC_MH_send(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_TC_MH_send_MASK) >> MH_DEBUG_REG38_TC_MH_send_SHIFT) +#define MH_DEBUG_REG38_GET_TC_ROQ_RTR_q(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG38_GET_ROQ_MARK_q_3(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_MARK_q_3_MASK) >> MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT) +#define MH_DEBUG_REG38_GET_ROQ_VALID_q_3(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_VALID_q_3_MASK) >> MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT) +#define MH_DEBUG_REG38_GET_SAME_ROW_BANK_q_3(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK) >> MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT) +#define MH_DEBUG_REG38_GET_ROQ_ADDR_3(mh_debug_reg38) \ + ((mh_debug_reg38 & MH_DEBUG_REG38_ROQ_ADDR_3_MASK) >> MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT) + +#define MH_DEBUG_REG38_SET_TC_MH_send(mh_debug_reg38_reg, tc_mh_send) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG38_TC_MH_send_SHIFT) +#define MH_DEBUG_REG38_SET_TC_ROQ_RTR_q(mh_debug_reg38_reg, tc_roq_rtr_q) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG38_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG38_SET_ROQ_MARK_q_3(mh_debug_reg38_reg, roq_mark_q_3) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_MARK_q_3_MASK) | (roq_mark_q_3 << MH_DEBUG_REG38_ROQ_MARK_q_3_SHIFT) +#define MH_DEBUG_REG38_SET_ROQ_VALID_q_3(mh_debug_reg38_reg, roq_valid_q_3) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_VALID_q_3_MASK) | (roq_valid_q_3 << MH_DEBUG_REG38_ROQ_VALID_q_3_SHIFT) +#define MH_DEBUG_REG38_SET_SAME_ROW_BANK_q_3(mh_debug_reg38_reg, same_row_bank_q_3) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_SAME_ROW_BANK_q_3_MASK) | (same_row_bank_q_3 << MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SHIFT) +#define MH_DEBUG_REG38_SET_ROQ_ADDR_3(mh_debug_reg38_reg, roq_addr_3) \ + mh_debug_reg38_reg = (mh_debug_reg38_reg & ~MH_DEBUG_REG38_ROQ_ADDR_3_MASK) | (roq_addr_3 << MH_DEBUG_REG38_ROQ_ADDR_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg38_t { + unsigned int tc_mh_send : MH_DEBUG_REG38_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_3 : MH_DEBUG_REG38_ROQ_MARK_q_3_SIZE; + unsigned int roq_valid_q_3 : MH_DEBUG_REG38_ROQ_VALID_q_3_SIZE; + unsigned int same_row_bank_q_3 : MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SIZE; + unsigned int roq_addr_3 : MH_DEBUG_REG38_ROQ_ADDR_3_SIZE; + } mh_debug_reg38_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg38_t { + unsigned int roq_addr_3 : MH_DEBUG_REG38_ROQ_ADDR_3_SIZE; + unsigned int same_row_bank_q_3 : MH_DEBUG_REG38_SAME_ROW_BANK_q_3_SIZE; + unsigned int roq_valid_q_3 : MH_DEBUG_REG38_ROQ_VALID_q_3_SIZE; + unsigned int roq_mark_q_3 : MH_DEBUG_REG38_ROQ_MARK_q_3_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG38_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG38_TC_MH_send_SIZE; + } mh_debug_reg38_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg38_t f; +} mh_debug_reg38_u; + + +/* + * MH_DEBUG_REG39 struct + */ + +#define MH_DEBUG_REG39_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG39_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG39_ROQ_MARK_q_4_SIZE 1 +#define MH_DEBUG_REG39_ROQ_VALID_q_4_SIZE 1 +#define MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SIZE 1 +#define MH_DEBUG_REG39_ROQ_ADDR_4_SIZE 27 + +#define MH_DEBUG_REG39_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT 2 +#define MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT 3 +#define MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT 4 +#define MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT 5 + +#define MH_DEBUG_REG39_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG39_ROQ_MARK_q_4_MASK 0x00000004 +#define MH_DEBUG_REG39_ROQ_VALID_q_4_MASK 0x00000008 +#define MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK 0x00000010 +#define MH_DEBUG_REG39_ROQ_ADDR_4_MASK 0xffffffe0 + +#define MH_DEBUG_REG39_MASK \ + (MH_DEBUG_REG39_TC_MH_send_MASK | \ + MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG39_ROQ_MARK_q_4_MASK | \ + MH_DEBUG_REG39_ROQ_VALID_q_4_MASK | \ + MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK | \ + MH_DEBUG_REG39_ROQ_ADDR_4_MASK) + +#define MH_DEBUG_REG39(tc_mh_send, tc_roq_rtr_q, roq_mark_q_4, roq_valid_q_4, same_row_bank_q_4, roq_addr_4) \ + ((tc_mh_send << MH_DEBUG_REG39_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_4 << MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT) | \ + (roq_valid_q_4 << MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT) | \ + (same_row_bank_q_4 << MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT) | \ + (roq_addr_4 << MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT)) + +#define MH_DEBUG_REG39_GET_TC_MH_send(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_TC_MH_send_MASK) >> MH_DEBUG_REG39_TC_MH_send_SHIFT) +#define MH_DEBUG_REG39_GET_TC_ROQ_RTR_q(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG39_GET_ROQ_MARK_q_4(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_ROQ_MARK_q_4_MASK) >> MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT) +#define MH_DEBUG_REG39_GET_ROQ_VALID_q_4(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_ROQ_VALID_q_4_MASK) >> MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT) +#define MH_DEBUG_REG39_GET_SAME_ROW_BANK_q_4(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK) >> MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT) +#define MH_DEBUG_REG39_GET_ROQ_ADDR_4(mh_debug_reg39) \ + ((mh_debug_reg39 & MH_DEBUG_REG39_ROQ_ADDR_4_MASK) >> MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT) + +#define MH_DEBUG_REG39_SET_TC_MH_send(mh_debug_reg39_reg, tc_mh_send) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG39_TC_MH_send_SHIFT) +#define MH_DEBUG_REG39_SET_TC_ROQ_RTR_q(mh_debug_reg39_reg, tc_roq_rtr_q) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG39_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG39_SET_ROQ_MARK_q_4(mh_debug_reg39_reg, roq_mark_q_4) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ROQ_MARK_q_4_MASK) | (roq_mark_q_4 << MH_DEBUG_REG39_ROQ_MARK_q_4_SHIFT) +#define MH_DEBUG_REG39_SET_ROQ_VALID_q_4(mh_debug_reg39_reg, roq_valid_q_4) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ROQ_VALID_q_4_MASK) | (roq_valid_q_4 << MH_DEBUG_REG39_ROQ_VALID_q_4_SHIFT) +#define MH_DEBUG_REG39_SET_SAME_ROW_BANK_q_4(mh_debug_reg39_reg, same_row_bank_q_4) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_SAME_ROW_BANK_q_4_MASK) | (same_row_bank_q_4 << MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SHIFT) +#define MH_DEBUG_REG39_SET_ROQ_ADDR_4(mh_debug_reg39_reg, roq_addr_4) \ + mh_debug_reg39_reg = (mh_debug_reg39_reg & ~MH_DEBUG_REG39_ROQ_ADDR_4_MASK) | (roq_addr_4 << MH_DEBUG_REG39_ROQ_ADDR_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg39_t { + unsigned int tc_mh_send : MH_DEBUG_REG39_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG39_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_4 : MH_DEBUG_REG39_ROQ_MARK_q_4_SIZE; + unsigned int roq_valid_q_4 : MH_DEBUG_REG39_ROQ_VALID_q_4_SIZE; + unsigned int same_row_bank_q_4 : MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SIZE; + unsigned int roq_addr_4 : MH_DEBUG_REG39_ROQ_ADDR_4_SIZE; + } mh_debug_reg39_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg39_t { + unsigned int roq_addr_4 : MH_DEBUG_REG39_ROQ_ADDR_4_SIZE; + unsigned int same_row_bank_q_4 : MH_DEBUG_REG39_SAME_ROW_BANK_q_4_SIZE; + unsigned int roq_valid_q_4 : MH_DEBUG_REG39_ROQ_VALID_q_4_SIZE; + unsigned int roq_mark_q_4 : MH_DEBUG_REG39_ROQ_MARK_q_4_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG39_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG39_TC_MH_send_SIZE; + } mh_debug_reg39_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg39_t f; +} mh_debug_reg39_u; + + +/* + * MH_DEBUG_REG40 struct + */ + +#define MH_DEBUG_REG40_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG40_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG40_ROQ_MARK_q_5_SIZE 1 +#define MH_DEBUG_REG40_ROQ_VALID_q_5_SIZE 1 +#define MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SIZE 1 +#define MH_DEBUG_REG40_ROQ_ADDR_5_SIZE 27 + +#define MH_DEBUG_REG40_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT 2 +#define MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT 3 +#define MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT 4 +#define MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT 5 + +#define MH_DEBUG_REG40_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG40_ROQ_MARK_q_5_MASK 0x00000004 +#define MH_DEBUG_REG40_ROQ_VALID_q_5_MASK 0x00000008 +#define MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK 0x00000010 +#define MH_DEBUG_REG40_ROQ_ADDR_5_MASK 0xffffffe0 + +#define MH_DEBUG_REG40_MASK \ + (MH_DEBUG_REG40_TC_MH_send_MASK | \ + MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG40_ROQ_MARK_q_5_MASK | \ + MH_DEBUG_REG40_ROQ_VALID_q_5_MASK | \ + MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK | \ + MH_DEBUG_REG40_ROQ_ADDR_5_MASK) + +#define MH_DEBUG_REG40(tc_mh_send, tc_roq_rtr_q, roq_mark_q_5, roq_valid_q_5, same_row_bank_q_5, roq_addr_5) \ + ((tc_mh_send << MH_DEBUG_REG40_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_5 << MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT) | \ + (roq_valid_q_5 << MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT) | \ + (same_row_bank_q_5 << MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT) | \ + (roq_addr_5 << MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT)) + +#define MH_DEBUG_REG40_GET_TC_MH_send(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_TC_MH_send_MASK) >> MH_DEBUG_REG40_TC_MH_send_SHIFT) +#define MH_DEBUG_REG40_GET_TC_ROQ_RTR_q(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG40_GET_ROQ_MARK_q_5(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_ROQ_MARK_q_5_MASK) >> MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT) +#define MH_DEBUG_REG40_GET_ROQ_VALID_q_5(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_ROQ_VALID_q_5_MASK) >> MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT) +#define MH_DEBUG_REG40_GET_SAME_ROW_BANK_q_5(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK) >> MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT) +#define MH_DEBUG_REG40_GET_ROQ_ADDR_5(mh_debug_reg40) \ + ((mh_debug_reg40 & MH_DEBUG_REG40_ROQ_ADDR_5_MASK) >> MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT) + +#define MH_DEBUG_REG40_SET_TC_MH_send(mh_debug_reg40_reg, tc_mh_send) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG40_TC_MH_send_SHIFT) +#define MH_DEBUG_REG40_SET_TC_ROQ_RTR_q(mh_debug_reg40_reg, tc_roq_rtr_q) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG40_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG40_SET_ROQ_MARK_q_5(mh_debug_reg40_reg, roq_mark_q_5) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ROQ_MARK_q_5_MASK) | (roq_mark_q_5 << MH_DEBUG_REG40_ROQ_MARK_q_5_SHIFT) +#define MH_DEBUG_REG40_SET_ROQ_VALID_q_5(mh_debug_reg40_reg, roq_valid_q_5) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ROQ_VALID_q_5_MASK) | (roq_valid_q_5 << MH_DEBUG_REG40_ROQ_VALID_q_5_SHIFT) +#define MH_DEBUG_REG40_SET_SAME_ROW_BANK_q_5(mh_debug_reg40_reg, same_row_bank_q_5) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_SAME_ROW_BANK_q_5_MASK) | (same_row_bank_q_5 << MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SHIFT) +#define MH_DEBUG_REG40_SET_ROQ_ADDR_5(mh_debug_reg40_reg, roq_addr_5) \ + mh_debug_reg40_reg = (mh_debug_reg40_reg & ~MH_DEBUG_REG40_ROQ_ADDR_5_MASK) | (roq_addr_5 << MH_DEBUG_REG40_ROQ_ADDR_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg40_t { + unsigned int tc_mh_send : MH_DEBUG_REG40_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG40_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_5 : MH_DEBUG_REG40_ROQ_MARK_q_5_SIZE; + unsigned int roq_valid_q_5 : MH_DEBUG_REG40_ROQ_VALID_q_5_SIZE; + unsigned int same_row_bank_q_5 : MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SIZE; + unsigned int roq_addr_5 : MH_DEBUG_REG40_ROQ_ADDR_5_SIZE; + } mh_debug_reg40_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg40_t { + unsigned int roq_addr_5 : MH_DEBUG_REG40_ROQ_ADDR_5_SIZE; + unsigned int same_row_bank_q_5 : MH_DEBUG_REG40_SAME_ROW_BANK_q_5_SIZE; + unsigned int roq_valid_q_5 : MH_DEBUG_REG40_ROQ_VALID_q_5_SIZE; + unsigned int roq_mark_q_5 : MH_DEBUG_REG40_ROQ_MARK_q_5_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG40_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG40_TC_MH_send_SIZE; + } mh_debug_reg40_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg40_t f; +} mh_debug_reg40_u; + + +/* + * MH_DEBUG_REG41 struct + */ + +#define MH_DEBUG_REG41_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG41_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG41_ROQ_MARK_q_6_SIZE 1 +#define MH_DEBUG_REG41_ROQ_VALID_q_6_SIZE 1 +#define MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SIZE 1 +#define MH_DEBUG_REG41_ROQ_ADDR_6_SIZE 27 + +#define MH_DEBUG_REG41_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT 2 +#define MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT 3 +#define MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT 4 +#define MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT 5 + +#define MH_DEBUG_REG41_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG41_ROQ_MARK_q_6_MASK 0x00000004 +#define MH_DEBUG_REG41_ROQ_VALID_q_6_MASK 0x00000008 +#define MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK 0x00000010 +#define MH_DEBUG_REG41_ROQ_ADDR_6_MASK 0xffffffe0 + +#define MH_DEBUG_REG41_MASK \ + (MH_DEBUG_REG41_TC_MH_send_MASK | \ + MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG41_ROQ_MARK_q_6_MASK | \ + MH_DEBUG_REG41_ROQ_VALID_q_6_MASK | \ + MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK | \ + MH_DEBUG_REG41_ROQ_ADDR_6_MASK) + +#define MH_DEBUG_REG41(tc_mh_send, tc_roq_rtr_q, roq_mark_q_6, roq_valid_q_6, same_row_bank_q_6, roq_addr_6) \ + ((tc_mh_send << MH_DEBUG_REG41_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_6 << MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT) | \ + (roq_valid_q_6 << MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT) | \ + (same_row_bank_q_6 << MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT) | \ + (roq_addr_6 << MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT)) + +#define MH_DEBUG_REG41_GET_TC_MH_send(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_TC_MH_send_MASK) >> MH_DEBUG_REG41_TC_MH_send_SHIFT) +#define MH_DEBUG_REG41_GET_TC_ROQ_RTR_q(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG41_GET_ROQ_MARK_q_6(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_ROQ_MARK_q_6_MASK) >> MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT) +#define MH_DEBUG_REG41_GET_ROQ_VALID_q_6(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_ROQ_VALID_q_6_MASK) >> MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT) +#define MH_DEBUG_REG41_GET_SAME_ROW_BANK_q_6(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK) >> MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT) +#define MH_DEBUG_REG41_GET_ROQ_ADDR_6(mh_debug_reg41) \ + ((mh_debug_reg41 & MH_DEBUG_REG41_ROQ_ADDR_6_MASK) >> MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT) + +#define MH_DEBUG_REG41_SET_TC_MH_send(mh_debug_reg41_reg, tc_mh_send) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG41_TC_MH_send_SHIFT) +#define MH_DEBUG_REG41_SET_TC_ROQ_RTR_q(mh_debug_reg41_reg, tc_roq_rtr_q) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG41_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG41_SET_ROQ_MARK_q_6(mh_debug_reg41_reg, roq_mark_q_6) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_ROQ_MARK_q_6_MASK) | (roq_mark_q_6 << MH_DEBUG_REG41_ROQ_MARK_q_6_SHIFT) +#define MH_DEBUG_REG41_SET_ROQ_VALID_q_6(mh_debug_reg41_reg, roq_valid_q_6) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_ROQ_VALID_q_6_MASK) | (roq_valid_q_6 << MH_DEBUG_REG41_ROQ_VALID_q_6_SHIFT) +#define MH_DEBUG_REG41_SET_SAME_ROW_BANK_q_6(mh_debug_reg41_reg, same_row_bank_q_6) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_SAME_ROW_BANK_q_6_MASK) | (same_row_bank_q_6 << MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SHIFT) +#define MH_DEBUG_REG41_SET_ROQ_ADDR_6(mh_debug_reg41_reg, roq_addr_6) \ + mh_debug_reg41_reg = (mh_debug_reg41_reg & ~MH_DEBUG_REG41_ROQ_ADDR_6_MASK) | (roq_addr_6 << MH_DEBUG_REG41_ROQ_ADDR_6_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg41_t { + unsigned int tc_mh_send : MH_DEBUG_REG41_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG41_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_6 : MH_DEBUG_REG41_ROQ_MARK_q_6_SIZE; + unsigned int roq_valid_q_6 : MH_DEBUG_REG41_ROQ_VALID_q_6_SIZE; + unsigned int same_row_bank_q_6 : MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SIZE; + unsigned int roq_addr_6 : MH_DEBUG_REG41_ROQ_ADDR_6_SIZE; + } mh_debug_reg41_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg41_t { + unsigned int roq_addr_6 : MH_DEBUG_REG41_ROQ_ADDR_6_SIZE; + unsigned int same_row_bank_q_6 : MH_DEBUG_REG41_SAME_ROW_BANK_q_6_SIZE; + unsigned int roq_valid_q_6 : MH_DEBUG_REG41_ROQ_VALID_q_6_SIZE; + unsigned int roq_mark_q_6 : MH_DEBUG_REG41_ROQ_MARK_q_6_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG41_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG41_TC_MH_send_SIZE; + } mh_debug_reg41_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg41_t f; +} mh_debug_reg41_u; + + +/* + * MH_DEBUG_REG42 struct + */ + +#define MH_DEBUG_REG42_TC_MH_send_SIZE 1 +#define MH_DEBUG_REG42_TC_ROQ_RTR_q_SIZE 1 +#define MH_DEBUG_REG42_ROQ_MARK_q_7_SIZE 1 +#define MH_DEBUG_REG42_ROQ_VALID_q_7_SIZE 1 +#define MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SIZE 1 +#define MH_DEBUG_REG42_ROQ_ADDR_7_SIZE 27 + +#define MH_DEBUG_REG42_TC_MH_send_SHIFT 0 +#define MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT 1 +#define MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT 2 +#define MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT 3 +#define MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT 4 +#define MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT 5 + +#define MH_DEBUG_REG42_TC_MH_send_MASK 0x00000001 +#define MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK 0x00000002 +#define MH_DEBUG_REG42_ROQ_MARK_q_7_MASK 0x00000004 +#define MH_DEBUG_REG42_ROQ_VALID_q_7_MASK 0x00000008 +#define MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK 0x00000010 +#define MH_DEBUG_REG42_ROQ_ADDR_7_MASK 0xffffffe0 + +#define MH_DEBUG_REG42_MASK \ + (MH_DEBUG_REG42_TC_MH_send_MASK | \ + MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK | \ + MH_DEBUG_REG42_ROQ_MARK_q_7_MASK | \ + MH_DEBUG_REG42_ROQ_VALID_q_7_MASK | \ + MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK | \ + MH_DEBUG_REG42_ROQ_ADDR_7_MASK) + +#define MH_DEBUG_REG42(tc_mh_send, tc_roq_rtr_q, roq_mark_q_7, roq_valid_q_7, same_row_bank_q_7, roq_addr_7) \ + ((tc_mh_send << MH_DEBUG_REG42_TC_MH_send_SHIFT) | \ + (tc_roq_rtr_q << MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT) | \ + (roq_mark_q_7 << MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT) | \ + (roq_valid_q_7 << MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT) | \ + (same_row_bank_q_7 << MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT) | \ + (roq_addr_7 << MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT)) + +#define MH_DEBUG_REG42_GET_TC_MH_send(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_TC_MH_send_MASK) >> MH_DEBUG_REG42_TC_MH_send_SHIFT) +#define MH_DEBUG_REG42_GET_TC_ROQ_RTR_q(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK) >> MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG42_GET_ROQ_MARK_q_7(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_ROQ_MARK_q_7_MASK) >> MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT) +#define MH_DEBUG_REG42_GET_ROQ_VALID_q_7(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_ROQ_VALID_q_7_MASK) >> MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT) +#define MH_DEBUG_REG42_GET_SAME_ROW_BANK_q_7(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK) >> MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT) +#define MH_DEBUG_REG42_GET_ROQ_ADDR_7(mh_debug_reg42) \ + ((mh_debug_reg42 & MH_DEBUG_REG42_ROQ_ADDR_7_MASK) >> MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT) + +#define MH_DEBUG_REG42_SET_TC_MH_send(mh_debug_reg42_reg, tc_mh_send) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_TC_MH_send_MASK) | (tc_mh_send << MH_DEBUG_REG42_TC_MH_send_SHIFT) +#define MH_DEBUG_REG42_SET_TC_ROQ_RTR_q(mh_debug_reg42_reg, tc_roq_rtr_q) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_TC_ROQ_RTR_q_MASK) | (tc_roq_rtr_q << MH_DEBUG_REG42_TC_ROQ_RTR_q_SHIFT) +#define MH_DEBUG_REG42_SET_ROQ_MARK_q_7(mh_debug_reg42_reg, roq_mark_q_7) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ROQ_MARK_q_7_MASK) | (roq_mark_q_7 << MH_DEBUG_REG42_ROQ_MARK_q_7_SHIFT) +#define MH_DEBUG_REG42_SET_ROQ_VALID_q_7(mh_debug_reg42_reg, roq_valid_q_7) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ROQ_VALID_q_7_MASK) | (roq_valid_q_7 << MH_DEBUG_REG42_ROQ_VALID_q_7_SHIFT) +#define MH_DEBUG_REG42_SET_SAME_ROW_BANK_q_7(mh_debug_reg42_reg, same_row_bank_q_7) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_SAME_ROW_BANK_q_7_MASK) | (same_row_bank_q_7 << MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SHIFT) +#define MH_DEBUG_REG42_SET_ROQ_ADDR_7(mh_debug_reg42_reg, roq_addr_7) \ + mh_debug_reg42_reg = (mh_debug_reg42_reg & ~MH_DEBUG_REG42_ROQ_ADDR_7_MASK) | (roq_addr_7 << MH_DEBUG_REG42_ROQ_ADDR_7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg42_t { + unsigned int tc_mh_send : MH_DEBUG_REG42_TC_MH_send_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG42_TC_ROQ_RTR_q_SIZE; + unsigned int roq_mark_q_7 : MH_DEBUG_REG42_ROQ_MARK_q_7_SIZE; + unsigned int roq_valid_q_7 : MH_DEBUG_REG42_ROQ_VALID_q_7_SIZE; + unsigned int same_row_bank_q_7 : MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SIZE; + unsigned int roq_addr_7 : MH_DEBUG_REG42_ROQ_ADDR_7_SIZE; + } mh_debug_reg42_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg42_t { + unsigned int roq_addr_7 : MH_DEBUG_REG42_ROQ_ADDR_7_SIZE; + unsigned int same_row_bank_q_7 : MH_DEBUG_REG42_SAME_ROW_BANK_q_7_SIZE; + unsigned int roq_valid_q_7 : MH_DEBUG_REG42_ROQ_VALID_q_7_SIZE; + unsigned int roq_mark_q_7 : MH_DEBUG_REG42_ROQ_MARK_q_7_SIZE; + unsigned int tc_roq_rtr_q : MH_DEBUG_REG42_TC_ROQ_RTR_q_SIZE; + unsigned int tc_mh_send : MH_DEBUG_REG42_TC_MH_send_SIZE; + } mh_debug_reg42_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg42_t f; +} mh_debug_reg42_u; + + +/* + * MH_DEBUG_REG43 struct + */ + +#define MH_DEBUG_REG43_ARB_REG_WE_q_SIZE 1 +#define MH_DEBUG_REG43_ARB_WE_SIZE 1 +#define MH_DEBUG_REG43_ARB_REG_VALID_q_SIZE 1 +#define MH_DEBUG_REG43_ARB_RTR_q_SIZE 1 +#define MH_DEBUG_REG43_ARB_REG_RTR_SIZE 1 +#define MH_DEBUG_REG43_WDAT_BURST_RTR_SIZE 1 +#define MH_DEBUG_REG43_MMU_RTR_SIZE 1 +#define MH_DEBUG_REG43_ARB_ID_q_SIZE 3 +#define MH_DEBUG_REG43_ARB_WRITE_q_SIZE 1 +#define MH_DEBUG_REG43_ARB_BLEN_q_SIZE 1 +#define MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SIZE 1 +#define MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SIZE 3 +#define MH_DEBUG_REG43_MMU_WE_SIZE 1 +#define MH_DEBUG_REG43_ARQ_RTR_SIZE 1 +#define MH_DEBUG_REG43_MMU_ID_SIZE 3 +#define MH_DEBUG_REG43_MMU_WRITE_SIZE 1 +#define MH_DEBUG_REG43_MMU_BLEN_SIZE 1 +#define MH_DEBUG_REG43_WBURST_IP_q_SIZE 1 +#define MH_DEBUG_REG43_WDAT_REG_WE_q_SIZE 1 +#define MH_DEBUG_REG43_WDB_WE_SIZE 1 +#define MH_DEBUG_REG43_WDB_RTR_SKID_4_SIZE 1 +#define MH_DEBUG_REG43_WDB_RTR_SKID_3_SIZE 1 + +#define MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT 0 +#define MH_DEBUG_REG43_ARB_WE_SHIFT 1 +#define MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT 2 +#define MH_DEBUG_REG43_ARB_RTR_q_SHIFT 3 +#define MH_DEBUG_REG43_ARB_REG_RTR_SHIFT 4 +#define MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT 5 +#define MH_DEBUG_REG43_MMU_RTR_SHIFT 6 +#define MH_DEBUG_REG43_ARB_ID_q_SHIFT 7 +#define MH_DEBUG_REG43_ARB_WRITE_q_SHIFT 10 +#define MH_DEBUG_REG43_ARB_BLEN_q_SHIFT 11 +#define MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT 12 +#define MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT 13 +#define MH_DEBUG_REG43_MMU_WE_SHIFT 16 +#define MH_DEBUG_REG43_ARQ_RTR_SHIFT 17 +#define MH_DEBUG_REG43_MMU_ID_SHIFT 18 +#define MH_DEBUG_REG43_MMU_WRITE_SHIFT 21 +#define MH_DEBUG_REG43_MMU_BLEN_SHIFT 22 +#define MH_DEBUG_REG43_WBURST_IP_q_SHIFT 23 +#define MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT 24 +#define MH_DEBUG_REG43_WDB_WE_SHIFT 25 +#define MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT 26 +#define MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT 27 + +#define MH_DEBUG_REG43_ARB_REG_WE_q_MASK 0x00000001 +#define MH_DEBUG_REG43_ARB_WE_MASK 0x00000002 +#define MH_DEBUG_REG43_ARB_REG_VALID_q_MASK 0x00000004 +#define MH_DEBUG_REG43_ARB_RTR_q_MASK 0x00000008 +#define MH_DEBUG_REG43_ARB_REG_RTR_MASK 0x00000010 +#define MH_DEBUG_REG43_WDAT_BURST_RTR_MASK 0x00000020 +#define MH_DEBUG_REG43_MMU_RTR_MASK 0x00000040 +#define MH_DEBUG_REG43_ARB_ID_q_MASK 0x00000380 +#define MH_DEBUG_REG43_ARB_WRITE_q_MASK 0x00000400 +#define MH_DEBUG_REG43_ARB_BLEN_q_MASK 0x00000800 +#define MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK 0x00001000 +#define MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK 0x0000e000 +#define MH_DEBUG_REG43_MMU_WE_MASK 0x00010000 +#define MH_DEBUG_REG43_ARQ_RTR_MASK 0x00020000 +#define MH_DEBUG_REG43_MMU_ID_MASK 0x001c0000 +#define MH_DEBUG_REG43_MMU_WRITE_MASK 0x00200000 +#define MH_DEBUG_REG43_MMU_BLEN_MASK 0x00400000 +#define MH_DEBUG_REG43_WBURST_IP_q_MASK 0x00800000 +#define MH_DEBUG_REG43_WDAT_REG_WE_q_MASK 0x01000000 +#define MH_DEBUG_REG43_WDB_WE_MASK 0x02000000 +#define MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK 0x04000000 +#define MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK 0x08000000 + +#define MH_DEBUG_REG43_MASK \ + (MH_DEBUG_REG43_ARB_REG_WE_q_MASK | \ + MH_DEBUG_REG43_ARB_WE_MASK | \ + MH_DEBUG_REG43_ARB_REG_VALID_q_MASK | \ + MH_DEBUG_REG43_ARB_RTR_q_MASK | \ + MH_DEBUG_REG43_ARB_REG_RTR_MASK | \ + MH_DEBUG_REG43_WDAT_BURST_RTR_MASK | \ + MH_DEBUG_REG43_MMU_RTR_MASK | \ + MH_DEBUG_REG43_ARB_ID_q_MASK | \ + MH_DEBUG_REG43_ARB_WRITE_q_MASK | \ + MH_DEBUG_REG43_ARB_BLEN_q_MASK | \ + MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK | \ + MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK | \ + MH_DEBUG_REG43_MMU_WE_MASK | \ + MH_DEBUG_REG43_ARQ_RTR_MASK | \ + MH_DEBUG_REG43_MMU_ID_MASK | \ + MH_DEBUG_REG43_MMU_WRITE_MASK | \ + MH_DEBUG_REG43_MMU_BLEN_MASK | \ + MH_DEBUG_REG43_WBURST_IP_q_MASK | \ + MH_DEBUG_REG43_WDAT_REG_WE_q_MASK | \ + MH_DEBUG_REG43_WDB_WE_MASK | \ + MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK | \ + MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK) + +#define MH_DEBUG_REG43(arb_reg_we_q, arb_we, arb_reg_valid_q, arb_rtr_q, arb_reg_rtr, wdat_burst_rtr, mmu_rtr, arb_id_q, arb_write_q, arb_blen_q, arq_ctrl_empty, arq_fifo_cnt_q, mmu_we, arq_rtr, mmu_id, mmu_write, mmu_blen, wburst_ip_q, wdat_reg_we_q, wdb_we, wdb_rtr_skid_4, wdb_rtr_skid_3) \ + ((arb_reg_we_q << MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT) | \ + (arb_we << MH_DEBUG_REG43_ARB_WE_SHIFT) | \ + (arb_reg_valid_q << MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT) | \ + (arb_rtr_q << MH_DEBUG_REG43_ARB_RTR_q_SHIFT) | \ + (arb_reg_rtr << MH_DEBUG_REG43_ARB_REG_RTR_SHIFT) | \ + (wdat_burst_rtr << MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT) | \ + (mmu_rtr << MH_DEBUG_REG43_MMU_RTR_SHIFT) | \ + (arb_id_q << MH_DEBUG_REG43_ARB_ID_q_SHIFT) | \ + (arb_write_q << MH_DEBUG_REG43_ARB_WRITE_q_SHIFT) | \ + (arb_blen_q << MH_DEBUG_REG43_ARB_BLEN_q_SHIFT) | \ + (arq_ctrl_empty << MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT) | \ + (arq_fifo_cnt_q << MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT) | \ + (mmu_we << MH_DEBUG_REG43_MMU_WE_SHIFT) | \ + (arq_rtr << MH_DEBUG_REG43_ARQ_RTR_SHIFT) | \ + (mmu_id << MH_DEBUG_REG43_MMU_ID_SHIFT) | \ + (mmu_write << MH_DEBUG_REG43_MMU_WRITE_SHIFT) | \ + (mmu_blen << MH_DEBUG_REG43_MMU_BLEN_SHIFT) | \ + (wburst_ip_q << MH_DEBUG_REG43_WBURST_IP_q_SHIFT) | \ + (wdat_reg_we_q << MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT) | \ + (wdb_we << MH_DEBUG_REG43_WDB_WE_SHIFT) | \ + (wdb_rtr_skid_4 << MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT) | \ + (wdb_rtr_skid_3 << MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT)) + +#define MH_DEBUG_REG43_GET_ARB_REG_WE_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_REG_WE_q_MASK) >> MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT) +#define MH_DEBUG_REG43_GET_ARB_WE(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_WE_MASK) >> MH_DEBUG_REG43_ARB_WE_SHIFT) +#define MH_DEBUG_REG43_GET_ARB_REG_VALID_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_REG_VALID_q_MASK) >> MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT) +#define MH_DEBUG_REG43_GET_ARB_RTR_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_RTR_q_MASK) >> MH_DEBUG_REG43_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG43_GET_ARB_REG_RTR(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_REG_RTR_MASK) >> MH_DEBUG_REG43_ARB_REG_RTR_SHIFT) +#define MH_DEBUG_REG43_GET_WDAT_BURST_RTR(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_WDAT_BURST_RTR_MASK) >> MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT) +#define MH_DEBUG_REG43_GET_MMU_RTR(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_RTR_MASK) >> MH_DEBUG_REG43_MMU_RTR_SHIFT) +#define MH_DEBUG_REG43_GET_ARB_ID_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_ID_q_MASK) >> MH_DEBUG_REG43_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG43_GET_ARB_WRITE_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_WRITE_q_MASK) >> MH_DEBUG_REG43_ARB_WRITE_q_SHIFT) +#define MH_DEBUG_REG43_GET_ARB_BLEN_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARB_BLEN_q_MASK) >> MH_DEBUG_REG43_ARB_BLEN_q_SHIFT) +#define MH_DEBUG_REG43_GET_ARQ_CTRL_EMPTY(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK) >> MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG43_GET_ARQ_FIFO_CNT_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK) >> MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT) +#define MH_DEBUG_REG43_GET_MMU_WE(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_WE_MASK) >> MH_DEBUG_REG43_MMU_WE_SHIFT) +#define MH_DEBUG_REG43_GET_ARQ_RTR(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_ARQ_RTR_MASK) >> MH_DEBUG_REG43_ARQ_RTR_SHIFT) +#define MH_DEBUG_REG43_GET_MMU_ID(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_ID_MASK) >> MH_DEBUG_REG43_MMU_ID_SHIFT) +#define MH_DEBUG_REG43_GET_MMU_WRITE(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_WRITE_MASK) >> MH_DEBUG_REG43_MMU_WRITE_SHIFT) +#define MH_DEBUG_REG43_GET_MMU_BLEN(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_MMU_BLEN_MASK) >> MH_DEBUG_REG43_MMU_BLEN_SHIFT) +#define MH_DEBUG_REG43_GET_WBURST_IP_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_WBURST_IP_q_MASK) >> MH_DEBUG_REG43_WBURST_IP_q_SHIFT) +#define MH_DEBUG_REG43_GET_WDAT_REG_WE_q(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_WDAT_REG_WE_q_MASK) >> MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT) +#define MH_DEBUG_REG43_GET_WDB_WE(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_WDB_WE_MASK) >> MH_DEBUG_REG43_WDB_WE_SHIFT) +#define MH_DEBUG_REG43_GET_WDB_RTR_SKID_4(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK) >> MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT) +#define MH_DEBUG_REG43_GET_WDB_RTR_SKID_3(mh_debug_reg43) \ + ((mh_debug_reg43 & MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK) >> MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT) + +#define MH_DEBUG_REG43_SET_ARB_REG_WE_q(mh_debug_reg43_reg, arb_reg_we_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_REG_WE_q_MASK) | (arb_reg_we_q << MH_DEBUG_REG43_ARB_REG_WE_q_SHIFT) +#define MH_DEBUG_REG43_SET_ARB_WE(mh_debug_reg43_reg, arb_we) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG43_ARB_WE_SHIFT) +#define MH_DEBUG_REG43_SET_ARB_REG_VALID_q(mh_debug_reg43_reg, arb_reg_valid_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_REG_VALID_q_MASK) | (arb_reg_valid_q << MH_DEBUG_REG43_ARB_REG_VALID_q_SHIFT) +#define MH_DEBUG_REG43_SET_ARB_RTR_q(mh_debug_reg43_reg, arb_rtr_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_RTR_q_MASK) | (arb_rtr_q << MH_DEBUG_REG43_ARB_RTR_q_SHIFT) +#define MH_DEBUG_REG43_SET_ARB_REG_RTR(mh_debug_reg43_reg, arb_reg_rtr) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_REG_RTR_MASK) | (arb_reg_rtr << MH_DEBUG_REG43_ARB_REG_RTR_SHIFT) +#define MH_DEBUG_REG43_SET_WDAT_BURST_RTR(mh_debug_reg43_reg, wdat_burst_rtr) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDAT_BURST_RTR_MASK) | (wdat_burst_rtr << MH_DEBUG_REG43_WDAT_BURST_RTR_SHIFT) +#define MH_DEBUG_REG43_SET_MMU_RTR(mh_debug_reg43_reg, mmu_rtr) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_RTR_MASK) | (mmu_rtr << MH_DEBUG_REG43_MMU_RTR_SHIFT) +#define MH_DEBUG_REG43_SET_ARB_ID_q(mh_debug_reg43_reg, arb_id_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG43_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG43_SET_ARB_WRITE_q(mh_debug_reg43_reg, arb_write_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_WRITE_q_MASK) | (arb_write_q << MH_DEBUG_REG43_ARB_WRITE_q_SHIFT) +#define MH_DEBUG_REG43_SET_ARB_BLEN_q(mh_debug_reg43_reg, arb_blen_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARB_BLEN_q_MASK) | (arb_blen_q << MH_DEBUG_REG43_ARB_BLEN_q_SHIFT) +#define MH_DEBUG_REG43_SET_ARQ_CTRL_EMPTY(mh_debug_reg43_reg, arq_ctrl_empty) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARQ_CTRL_EMPTY_MASK) | (arq_ctrl_empty << MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG43_SET_ARQ_FIFO_CNT_q(mh_debug_reg43_reg, arq_fifo_cnt_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARQ_FIFO_CNT_q_MASK) | (arq_fifo_cnt_q << MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SHIFT) +#define MH_DEBUG_REG43_SET_MMU_WE(mh_debug_reg43_reg, mmu_we) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG43_MMU_WE_SHIFT) +#define MH_DEBUG_REG43_SET_ARQ_RTR(mh_debug_reg43_reg, arq_rtr) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_ARQ_RTR_MASK) | (arq_rtr << MH_DEBUG_REG43_ARQ_RTR_SHIFT) +#define MH_DEBUG_REG43_SET_MMU_ID(mh_debug_reg43_reg, mmu_id) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_ID_MASK) | (mmu_id << MH_DEBUG_REG43_MMU_ID_SHIFT) +#define MH_DEBUG_REG43_SET_MMU_WRITE(mh_debug_reg43_reg, mmu_write) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_WRITE_MASK) | (mmu_write << MH_DEBUG_REG43_MMU_WRITE_SHIFT) +#define MH_DEBUG_REG43_SET_MMU_BLEN(mh_debug_reg43_reg, mmu_blen) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_MMU_BLEN_MASK) | (mmu_blen << MH_DEBUG_REG43_MMU_BLEN_SHIFT) +#define MH_DEBUG_REG43_SET_WBURST_IP_q(mh_debug_reg43_reg, wburst_ip_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WBURST_IP_q_MASK) | (wburst_ip_q << MH_DEBUG_REG43_WBURST_IP_q_SHIFT) +#define MH_DEBUG_REG43_SET_WDAT_REG_WE_q(mh_debug_reg43_reg, wdat_reg_we_q) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDAT_REG_WE_q_MASK) | (wdat_reg_we_q << MH_DEBUG_REG43_WDAT_REG_WE_q_SHIFT) +#define MH_DEBUG_REG43_SET_WDB_WE(mh_debug_reg43_reg, wdb_we) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDB_WE_MASK) | (wdb_we << MH_DEBUG_REG43_WDB_WE_SHIFT) +#define MH_DEBUG_REG43_SET_WDB_RTR_SKID_4(mh_debug_reg43_reg, wdb_rtr_skid_4) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDB_RTR_SKID_4_MASK) | (wdb_rtr_skid_4 << MH_DEBUG_REG43_WDB_RTR_SKID_4_SHIFT) +#define MH_DEBUG_REG43_SET_WDB_RTR_SKID_3(mh_debug_reg43_reg, wdb_rtr_skid_3) \ + mh_debug_reg43_reg = (mh_debug_reg43_reg & ~MH_DEBUG_REG43_WDB_RTR_SKID_3_MASK) | (wdb_rtr_skid_3 << MH_DEBUG_REG43_WDB_RTR_SKID_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg43_t { + unsigned int arb_reg_we_q : MH_DEBUG_REG43_ARB_REG_WE_q_SIZE; + unsigned int arb_we : MH_DEBUG_REG43_ARB_WE_SIZE; + unsigned int arb_reg_valid_q : MH_DEBUG_REG43_ARB_REG_VALID_q_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG43_ARB_RTR_q_SIZE; + unsigned int arb_reg_rtr : MH_DEBUG_REG43_ARB_REG_RTR_SIZE; + unsigned int wdat_burst_rtr : MH_DEBUG_REG43_WDAT_BURST_RTR_SIZE; + unsigned int mmu_rtr : MH_DEBUG_REG43_MMU_RTR_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG43_ARB_ID_q_SIZE; + unsigned int arb_write_q : MH_DEBUG_REG43_ARB_WRITE_q_SIZE; + unsigned int arb_blen_q : MH_DEBUG_REG43_ARB_BLEN_q_SIZE; + unsigned int arq_ctrl_empty : MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SIZE; + unsigned int arq_fifo_cnt_q : MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SIZE; + unsigned int mmu_we : MH_DEBUG_REG43_MMU_WE_SIZE; + unsigned int arq_rtr : MH_DEBUG_REG43_ARQ_RTR_SIZE; + unsigned int mmu_id : MH_DEBUG_REG43_MMU_ID_SIZE; + unsigned int mmu_write : MH_DEBUG_REG43_MMU_WRITE_SIZE; + unsigned int mmu_blen : MH_DEBUG_REG43_MMU_BLEN_SIZE; + unsigned int wburst_ip_q : MH_DEBUG_REG43_WBURST_IP_q_SIZE; + unsigned int wdat_reg_we_q : MH_DEBUG_REG43_WDAT_REG_WE_q_SIZE; + unsigned int wdb_we : MH_DEBUG_REG43_WDB_WE_SIZE; + unsigned int wdb_rtr_skid_4 : MH_DEBUG_REG43_WDB_RTR_SKID_4_SIZE; + unsigned int wdb_rtr_skid_3 : MH_DEBUG_REG43_WDB_RTR_SKID_3_SIZE; + unsigned int : 4; + } mh_debug_reg43_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg43_t { + unsigned int : 4; + unsigned int wdb_rtr_skid_3 : MH_DEBUG_REG43_WDB_RTR_SKID_3_SIZE; + unsigned int wdb_rtr_skid_4 : MH_DEBUG_REG43_WDB_RTR_SKID_4_SIZE; + unsigned int wdb_we : MH_DEBUG_REG43_WDB_WE_SIZE; + unsigned int wdat_reg_we_q : MH_DEBUG_REG43_WDAT_REG_WE_q_SIZE; + unsigned int wburst_ip_q : MH_DEBUG_REG43_WBURST_IP_q_SIZE; + unsigned int mmu_blen : MH_DEBUG_REG43_MMU_BLEN_SIZE; + unsigned int mmu_write : MH_DEBUG_REG43_MMU_WRITE_SIZE; + unsigned int mmu_id : MH_DEBUG_REG43_MMU_ID_SIZE; + unsigned int arq_rtr : MH_DEBUG_REG43_ARQ_RTR_SIZE; + unsigned int mmu_we : MH_DEBUG_REG43_MMU_WE_SIZE; + unsigned int arq_fifo_cnt_q : MH_DEBUG_REG43_ARQ_FIFO_CNT_q_SIZE; + unsigned int arq_ctrl_empty : MH_DEBUG_REG43_ARQ_CTRL_EMPTY_SIZE; + unsigned int arb_blen_q : MH_DEBUG_REG43_ARB_BLEN_q_SIZE; + unsigned int arb_write_q : MH_DEBUG_REG43_ARB_WRITE_q_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG43_ARB_ID_q_SIZE; + unsigned int mmu_rtr : MH_DEBUG_REG43_MMU_RTR_SIZE; + unsigned int wdat_burst_rtr : MH_DEBUG_REG43_WDAT_BURST_RTR_SIZE; + unsigned int arb_reg_rtr : MH_DEBUG_REG43_ARB_REG_RTR_SIZE; + unsigned int arb_rtr_q : MH_DEBUG_REG43_ARB_RTR_q_SIZE; + unsigned int arb_reg_valid_q : MH_DEBUG_REG43_ARB_REG_VALID_q_SIZE; + unsigned int arb_we : MH_DEBUG_REG43_ARB_WE_SIZE; + unsigned int arb_reg_we_q : MH_DEBUG_REG43_ARB_REG_WE_q_SIZE; + } mh_debug_reg43_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg43_t f; +} mh_debug_reg43_u; + + +/* + * MH_DEBUG_REG44 struct + */ + +#define MH_DEBUG_REG44_ARB_WE_SIZE 1 +#define MH_DEBUG_REG44_ARB_ID_q_SIZE 3 +#define MH_DEBUG_REG44_ARB_VAD_q_SIZE 28 + +#define MH_DEBUG_REG44_ARB_WE_SHIFT 0 +#define MH_DEBUG_REG44_ARB_ID_q_SHIFT 1 +#define MH_DEBUG_REG44_ARB_VAD_q_SHIFT 4 + +#define MH_DEBUG_REG44_ARB_WE_MASK 0x00000001 +#define MH_DEBUG_REG44_ARB_ID_q_MASK 0x0000000e +#define MH_DEBUG_REG44_ARB_VAD_q_MASK 0xfffffff0 + +#define MH_DEBUG_REG44_MASK \ + (MH_DEBUG_REG44_ARB_WE_MASK | \ + MH_DEBUG_REG44_ARB_ID_q_MASK | \ + MH_DEBUG_REG44_ARB_VAD_q_MASK) + +#define MH_DEBUG_REG44(arb_we, arb_id_q, arb_vad_q) \ + ((arb_we << MH_DEBUG_REG44_ARB_WE_SHIFT) | \ + (arb_id_q << MH_DEBUG_REG44_ARB_ID_q_SHIFT) | \ + (arb_vad_q << MH_DEBUG_REG44_ARB_VAD_q_SHIFT)) + +#define MH_DEBUG_REG44_GET_ARB_WE(mh_debug_reg44) \ + ((mh_debug_reg44 & MH_DEBUG_REG44_ARB_WE_MASK) >> MH_DEBUG_REG44_ARB_WE_SHIFT) +#define MH_DEBUG_REG44_GET_ARB_ID_q(mh_debug_reg44) \ + ((mh_debug_reg44 & MH_DEBUG_REG44_ARB_ID_q_MASK) >> MH_DEBUG_REG44_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG44_GET_ARB_VAD_q(mh_debug_reg44) \ + ((mh_debug_reg44 & MH_DEBUG_REG44_ARB_VAD_q_MASK) >> MH_DEBUG_REG44_ARB_VAD_q_SHIFT) + +#define MH_DEBUG_REG44_SET_ARB_WE(mh_debug_reg44_reg, arb_we) \ + mh_debug_reg44_reg = (mh_debug_reg44_reg & ~MH_DEBUG_REG44_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG44_ARB_WE_SHIFT) +#define MH_DEBUG_REG44_SET_ARB_ID_q(mh_debug_reg44_reg, arb_id_q) \ + mh_debug_reg44_reg = (mh_debug_reg44_reg & ~MH_DEBUG_REG44_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG44_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG44_SET_ARB_VAD_q(mh_debug_reg44_reg, arb_vad_q) \ + mh_debug_reg44_reg = (mh_debug_reg44_reg & ~MH_DEBUG_REG44_ARB_VAD_q_MASK) | (arb_vad_q << MH_DEBUG_REG44_ARB_VAD_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg44_t { + unsigned int arb_we : MH_DEBUG_REG44_ARB_WE_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG44_ARB_ID_q_SIZE; + unsigned int arb_vad_q : MH_DEBUG_REG44_ARB_VAD_q_SIZE; + } mh_debug_reg44_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg44_t { + unsigned int arb_vad_q : MH_DEBUG_REG44_ARB_VAD_q_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG44_ARB_ID_q_SIZE; + unsigned int arb_we : MH_DEBUG_REG44_ARB_WE_SIZE; + } mh_debug_reg44_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg44_t f; +} mh_debug_reg44_u; + + +/* + * MH_DEBUG_REG45 struct + */ + +#define MH_DEBUG_REG45_MMU_WE_SIZE 1 +#define MH_DEBUG_REG45_MMU_ID_SIZE 3 +#define MH_DEBUG_REG45_MMU_PAD_SIZE 28 + +#define MH_DEBUG_REG45_MMU_WE_SHIFT 0 +#define MH_DEBUG_REG45_MMU_ID_SHIFT 1 +#define MH_DEBUG_REG45_MMU_PAD_SHIFT 4 + +#define MH_DEBUG_REG45_MMU_WE_MASK 0x00000001 +#define MH_DEBUG_REG45_MMU_ID_MASK 0x0000000e +#define MH_DEBUG_REG45_MMU_PAD_MASK 0xfffffff0 + +#define MH_DEBUG_REG45_MASK \ + (MH_DEBUG_REG45_MMU_WE_MASK | \ + MH_DEBUG_REG45_MMU_ID_MASK | \ + MH_DEBUG_REG45_MMU_PAD_MASK) + +#define MH_DEBUG_REG45(mmu_we, mmu_id, mmu_pad) \ + ((mmu_we << MH_DEBUG_REG45_MMU_WE_SHIFT) | \ + (mmu_id << MH_DEBUG_REG45_MMU_ID_SHIFT) | \ + (mmu_pad << MH_DEBUG_REG45_MMU_PAD_SHIFT)) + +#define MH_DEBUG_REG45_GET_MMU_WE(mh_debug_reg45) \ + ((mh_debug_reg45 & MH_DEBUG_REG45_MMU_WE_MASK) >> MH_DEBUG_REG45_MMU_WE_SHIFT) +#define MH_DEBUG_REG45_GET_MMU_ID(mh_debug_reg45) \ + ((mh_debug_reg45 & MH_DEBUG_REG45_MMU_ID_MASK) >> MH_DEBUG_REG45_MMU_ID_SHIFT) +#define MH_DEBUG_REG45_GET_MMU_PAD(mh_debug_reg45) \ + ((mh_debug_reg45 & MH_DEBUG_REG45_MMU_PAD_MASK) >> MH_DEBUG_REG45_MMU_PAD_SHIFT) + +#define MH_DEBUG_REG45_SET_MMU_WE(mh_debug_reg45_reg, mmu_we) \ + mh_debug_reg45_reg = (mh_debug_reg45_reg & ~MH_DEBUG_REG45_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG45_MMU_WE_SHIFT) +#define MH_DEBUG_REG45_SET_MMU_ID(mh_debug_reg45_reg, mmu_id) \ + mh_debug_reg45_reg = (mh_debug_reg45_reg & ~MH_DEBUG_REG45_MMU_ID_MASK) | (mmu_id << MH_DEBUG_REG45_MMU_ID_SHIFT) +#define MH_DEBUG_REG45_SET_MMU_PAD(mh_debug_reg45_reg, mmu_pad) \ + mh_debug_reg45_reg = (mh_debug_reg45_reg & ~MH_DEBUG_REG45_MMU_PAD_MASK) | (mmu_pad << MH_DEBUG_REG45_MMU_PAD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg45_t { + unsigned int mmu_we : MH_DEBUG_REG45_MMU_WE_SIZE; + unsigned int mmu_id : MH_DEBUG_REG45_MMU_ID_SIZE; + unsigned int mmu_pad : MH_DEBUG_REG45_MMU_PAD_SIZE; + } mh_debug_reg45_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg45_t { + unsigned int mmu_pad : MH_DEBUG_REG45_MMU_PAD_SIZE; + unsigned int mmu_id : MH_DEBUG_REG45_MMU_ID_SIZE; + unsigned int mmu_we : MH_DEBUG_REG45_MMU_WE_SIZE; + } mh_debug_reg45_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg45_t f; +} mh_debug_reg45_u; + + +/* + * MH_DEBUG_REG46 struct + */ + +#define MH_DEBUG_REG46_WDAT_REG_WE_q_SIZE 1 +#define MH_DEBUG_REG46_WDB_WE_SIZE 1 +#define MH_DEBUG_REG46_WDAT_REG_VALID_q_SIZE 1 +#define MH_DEBUG_REG46_WDB_RTR_SKID_4_SIZE 1 +#define MH_DEBUG_REG46_ARB_WSTRB_q_SIZE 8 +#define MH_DEBUG_REG46_ARB_WLAST_SIZE 1 +#define MH_DEBUG_REG46_WDB_CTRL_EMPTY_SIZE 1 +#define MH_DEBUG_REG46_WDB_FIFO_CNT_q_SIZE 5 +#define MH_DEBUG_REG46_WDC_WDB_RE_q_SIZE 1 +#define MH_DEBUG_REG46_WDB_WDC_WID_SIZE 3 +#define MH_DEBUG_REG46_WDB_WDC_WLAST_SIZE 1 +#define MH_DEBUG_REG46_WDB_WDC_WSTRB_SIZE 8 + +#define MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT 0 +#define MH_DEBUG_REG46_WDB_WE_SHIFT 1 +#define MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT 2 +#define MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT 3 +#define MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT 4 +#define MH_DEBUG_REG46_ARB_WLAST_SHIFT 12 +#define MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT 13 +#define MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT 14 +#define MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT 19 +#define MH_DEBUG_REG46_WDB_WDC_WID_SHIFT 20 +#define MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT 23 +#define MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT 24 + +#define MH_DEBUG_REG46_WDAT_REG_WE_q_MASK 0x00000001 +#define MH_DEBUG_REG46_WDB_WE_MASK 0x00000002 +#define MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK 0x00000004 +#define MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK 0x00000008 +#define MH_DEBUG_REG46_ARB_WSTRB_q_MASK 0x00000ff0 +#define MH_DEBUG_REG46_ARB_WLAST_MASK 0x00001000 +#define MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK 0x00002000 +#define MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK 0x0007c000 +#define MH_DEBUG_REG46_WDC_WDB_RE_q_MASK 0x00080000 +#define MH_DEBUG_REG46_WDB_WDC_WID_MASK 0x00700000 +#define MH_DEBUG_REG46_WDB_WDC_WLAST_MASK 0x00800000 +#define MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK 0xff000000 + +#define MH_DEBUG_REG46_MASK \ + (MH_DEBUG_REG46_WDAT_REG_WE_q_MASK | \ + MH_DEBUG_REG46_WDB_WE_MASK | \ + MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK | \ + MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK | \ + MH_DEBUG_REG46_ARB_WSTRB_q_MASK | \ + MH_DEBUG_REG46_ARB_WLAST_MASK | \ + MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK | \ + MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK | \ + MH_DEBUG_REG46_WDC_WDB_RE_q_MASK | \ + MH_DEBUG_REG46_WDB_WDC_WID_MASK | \ + MH_DEBUG_REG46_WDB_WDC_WLAST_MASK | \ + MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK) + +#define MH_DEBUG_REG46(wdat_reg_we_q, wdb_we, wdat_reg_valid_q, wdb_rtr_skid_4, arb_wstrb_q, arb_wlast, wdb_ctrl_empty, wdb_fifo_cnt_q, wdc_wdb_re_q, wdb_wdc_wid, wdb_wdc_wlast, wdb_wdc_wstrb) \ + ((wdat_reg_we_q << MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT) | \ + (wdb_we << MH_DEBUG_REG46_WDB_WE_SHIFT) | \ + (wdat_reg_valid_q << MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT) | \ + (wdb_rtr_skid_4 << MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT) | \ + (arb_wstrb_q << MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT) | \ + (arb_wlast << MH_DEBUG_REG46_ARB_WLAST_SHIFT) | \ + (wdb_ctrl_empty << MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT) | \ + (wdb_fifo_cnt_q << MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT) | \ + (wdc_wdb_re_q << MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT) | \ + (wdb_wdc_wid << MH_DEBUG_REG46_WDB_WDC_WID_SHIFT) | \ + (wdb_wdc_wlast << MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT) | \ + (wdb_wdc_wstrb << MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT)) + +#define MH_DEBUG_REG46_GET_WDAT_REG_WE_q(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDAT_REG_WE_q_MASK) >> MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT) +#define MH_DEBUG_REG46_GET_WDB_WE(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WE_MASK) >> MH_DEBUG_REG46_WDB_WE_SHIFT) +#define MH_DEBUG_REG46_GET_WDAT_REG_VALID_q(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK) >> MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT) +#define MH_DEBUG_REG46_GET_WDB_RTR_SKID_4(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK) >> MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT) +#define MH_DEBUG_REG46_GET_ARB_WSTRB_q(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_ARB_WSTRB_q_MASK) >> MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT) +#define MH_DEBUG_REG46_GET_ARB_WLAST(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_ARB_WLAST_MASK) >> MH_DEBUG_REG46_ARB_WLAST_SHIFT) +#define MH_DEBUG_REG46_GET_WDB_CTRL_EMPTY(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK) >> MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG46_GET_WDB_FIFO_CNT_q(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK) >> MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT) +#define MH_DEBUG_REG46_GET_WDC_WDB_RE_q(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDC_WDB_RE_q_MASK) >> MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT) +#define MH_DEBUG_REG46_GET_WDB_WDC_WID(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WDC_WID_MASK) >> MH_DEBUG_REG46_WDB_WDC_WID_SHIFT) +#define MH_DEBUG_REG46_GET_WDB_WDC_WLAST(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WDC_WLAST_MASK) >> MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT) +#define MH_DEBUG_REG46_GET_WDB_WDC_WSTRB(mh_debug_reg46) \ + ((mh_debug_reg46 & MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK) >> MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT) + +#define MH_DEBUG_REG46_SET_WDAT_REG_WE_q(mh_debug_reg46_reg, wdat_reg_we_q) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDAT_REG_WE_q_MASK) | (wdat_reg_we_q << MH_DEBUG_REG46_WDAT_REG_WE_q_SHIFT) +#define MH_DEBUG_REG46_SET_WDB_WE(mh_debug_reg46_reg, wdb_we) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WE_MASK) | (wdb_we << MH_DEBUG_REG46_WDB_WE_SHIFT) +#define MH_DEBUG_REG46_SET_WDAT_REG_VALID_q(mh_debug_reg46_reg, wdat_reg_valid_q) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDAT_REG_VALID_q_MASK) | (wdat_reg_valid_q << MH_DEBUG_REG46_WDAT_REG_VALID_q_SHIFT) +#define MH_DEBUG_REG46_SET_WDB_RTR_SKID_4(mh_debug_reg46_reg, wdb_rtr_skid_4) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_RTR_SKID_4_MASK) | (wdb_rtr_skid_4 << MH_DEBUG_REG46_WDB_RTR_SKID_4_SHIFT) +#define MH_DEBUG_REG46_SET_ARB_WSTRB_q(mh_debug_reg46_reg, arb_wstrb_q) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_ARB_WSTRB_q_MASK) | (arb_wstrb_q << MH_DEBUG_REG46_ARB_WSTRB_q_SHIFT) +#define MH_DEBUG_REG46_SET_ARB_WLAST(mh_debug_reg46_reg, arb_wlast) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_ARB_WLAST_MASK) | (arb_wlast << MH_DEBUG_REG46_ARB_WLAST_SHIFT) +#define MH_DEBUG_REG46_SET_WDB_CTRL_EMPTY(mh_debug_reg46_reg, wdb_ctrl_empty) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_CTRL_EMPTY_MASK) | (wdb_ctrl_empty << MH_DEBUG_REG46_WDB_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG46_SET_WDB_FIFO_CNT_q(mh_debug_reg46_reg, wdb_fifo_cnt_q) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_FIFO_CNT_q_MASK) | (wdb_fifo_cnt_q << MH_DEBUG_REG46_WDB_FIFO_CNT_q_SHIFT) +#define MH_DEBUG_REG46_SET_WDC_WDB_RE_q(mh_debug_reg46_reg, wdc_wdb_re_q) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDC_WDB_RE_q_MASK) | (wdc_wdb_re_q << MH_DEBUG_REG46_WDC_WDB_RE_q_SHIFT) +#define MH_DEBUG_REG46_SET_WDB_WDC_WID(mh_debug_reg46_reg, wdb_wdc_wid) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WDC_WID_MASK) | (wdb_wdc_wid << MH_DEBUG_REG46_WDB_WDC_WID_SHIFT) +#define MH_DEBUG_REG46_SET_WDB_WDC_WLAST(mh_debug_reg46_reg, wdb_wdc_wlast) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WDC_WLAST_MASK) | (wdb_wdc_wlast << MH_DEBUG_REG46_WDB_WDC_WLAST_SHIFT) +#define MH_DEBUG_REG46_SET_WDB_WDC_WSTRB(mh_debug_reg46_reg, wdb_wdc_wstrb) \ + mh_debug_reg46_reg = (mh_debug_reg46_reg & ~MH_DEBUG_REG46_WDB_WDC_WSTRB_MASK) | (wdb_wdc_wstrb << MH_DEBUG_REG46_WDB_WDC_WSTRB_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg46_t { + unsigned int wdat_reg_we_q : MH_DEBUG_REG46_WDAT_REG_WE_q_SIZE; + unsigned int wdb_we : MH_DEBUG_REG46_WDB_WE_SIZE; + unsigned int wdat_reg_valid_q : MH_DEBUG_REG46_WDAT_REG_VALID_q_SIZE; + unsigned int wdb_rtr_skid_4 : MH_DEBUG_REG46_WDB_RTR_SKID_4_SIZE; + unsigned int arb_wstrb_q : MH_DEBUG_REG46_ARB_WSTRB_q_SIZE; + unsigned int arb_wlast : MH_DEBUG_REG46_ARB_WLAST_SIZE; + unsigned int wdb_ctrl_empty : MH_DEBUG_REG46_WDB_CTRL_EMPTY_SIZE; + unsigned int wdb_fifo_cnt_q : MH_DEBUG_REG46_WDB_FIFO_CNT_q_SIZE; + unsigned int wdc_wdb_re_q : MH_DEBUG_REG46_WDC_WDB_RE_q_SIZE; + unsigned int wdb_wdc_wid : MH_DEBUG_REG46_WDB_WDC_WID_SIZE; + unsigned int wdb_wdc_wlast : MH_DEBUG_REG46_WDB_WDC_WLAST_SIZE; + unsigned int wdb_wdc_wstrb : MH_DEBUG_REG46_WDB_WDC_WSTRB_SIZE; + } mh_debug_reg46_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg46_t { + unsigned int wdb_wdc_wstrb : MH_DEBUG_REG46_WDB_WDC_WSTRB_SIZE; + unsigned int wdb_wdc_wlast : MH_DEBUG_REG46_WDB_WDC_WLAST_SIZE; + unsigned int wdb_wdc_wid : MH_DEBUG_REG46_WDB_WDC_WID_SIZE; + unsigned int wdc_wdb_re_q : MH_DEBUG_REG46_WDC_WDB_RE_q_SIZE; + unsigned int wdb_fifo_cnt_q : MH_DEBUG_REG46_WDB_FIFO_CNT_q_SIZE; + unsigned int wdb_ctrl_empty : MH_DEBUG_REG46_WDB_CTRL_EMPTY_SIZE; + unsigned int arb_wlast : MH_DEBUG_REG46_ARB_WLAST_SIZE; + unsigned int arb_wstrb_q : MH_DEBUG_REG46_ARB_WSTRB_q_SIZE; + unsigned int wdb_rtr_skid_4 : MH_DEBUG_REG46_WDB_RTR_SKID_4_SIZE; + unsigned int wdat_reg_valid_q : MH_DEBUG_REG46_WDAT_REG_VALID_q_SIZE; + unsigned int wdb_we : MH_DEBUG_REG46_WDB_WE_SIZE; + unsigned int wdat_reg_we_q : MH_DEBUG_REG46_WDAT_REG_WE_q_SIZE; + } mh_debug_reg46_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg46_t f; +} mh_debug_reg46_u; + + +/* + * MH_DEBUG_REG47 struct + */ + +#define MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SIZE 32 + +#define MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT 0 + +#define MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK 0xffffffff + +#define MH_DEBUG_REG47_MASK \ + (MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK) + +#define MH_DEBUG_REG47(wdb_wdc_wdata_31_0) \ + ((wdb_wdc_wdata_31_0 << MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT)) + +#define MH_DEBUG_REG47_GET_WDB_WDC_WDATA_31_0(mh_debug_reg47) \ + ((mh_debug_reg47 & MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK) >> MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT) + +#define MH_DEBUG_REG47_SET_WDB_WDC_WDATA_31_0(mh_debug_reg47_reg, wdb_wdc_wdata_31_0) \ + mh_debug_reg47_reg = (mh_debug_reg47_reg & ~MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_MASK) | (wdb_wdc_wdata_31_0 << MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg47_t { + unsigned int wdb_wdc_wdata_31_0 : MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SIZE; + } mh_debug_reg47_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg47_t { + unsigned int wdb_wdc_wdata_31_0 : MH_DEBUG_REG47_WDB_WDC_WDATA_31_0_SIZE; + } mh_debug_reg47_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg47_t f; +} mh_debug_reg47_u; + + +/* + * MH_DEBUG_REG48 struct + */ + +#define MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SIZE 32 + +#define MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT 0 + +#define MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK 0xffffffff + +#define MH_DEBUG_REG48_MASK \ + (MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK) + +#define MH_DEBUG_REG48(wdb_wdc_wdata_63_32) \ + ((wdb_wdc_wdata_63_32 << MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT)) + +#define MH_DEBUG_REG48_GET_WDB_WDC_WDATA_63_32(mh_debug_reg48) \ + ((mh_debug_reg48 & MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK) >> MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT) + +#define MH_DEBUG_REG48_SET_WDB_WDC_WDATA_63_32(mh_debug_reg48_reg, wdb_wdc_wdata_63_32) \ + mh_debug_reg48_reg = (mh_debug_reg48_reg & ~MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_MASK) | (wdb_wdc_wdata_63_32 << MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg48_t { + unsigned int wdb_wdc_wdata_63_32 : MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SIZE; + } mh_debug_reg48_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg48_t { + unsigned int wdb_wdc_wdata_63_32 : MH_DEBUG_REG48_WDB_WDC_WDATA_63_32_SIZE; + } mh_debug_reg48_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg48_t f; +} mh_debug_reg48_u; + + +/* + * MH_DEBUG_REG49 struct + */ + +#define MH_DEBUG_REG49_CTRL_ARC_EMPTY_SIZE 1 +#define MH_DEBUG_REG49_CTRL_RARC_EMPTY_SIZE 1 +#define MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SIZE 1 +#define MH_DEBUG_REG49_ARQ_CTRL_WRITE_SIZE 1 +#define MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SIZE 1 +#define MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SIZE 1 +#define MH_DEBUG_REG49_INFLT_LIMIT_q_SIZE 1 +#define MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SIZE 6 +#define MH_DEBUG_REG49_ARC_CTRL_RE_q_SIZE 1 +#define MH_DEBUG_REG49_RARC_CTRL_RE_q_SIZE 1 +#define MH_DEBUG_REG49_RVALID_q_SIZE 1 +#define MH_DEBUG_REG49_RREADY_q_SIZE 1 +#define MH_DEBUG_REG49_RLAST_q_SIZE 1 +#define MH_DEBUG_REG49_BVALID_q_SIZE 1 +#define MH_DEBUG_REG49_BREADY_q_SIZE 1 + +#define MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT 0 +#define MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT 1 +#define MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT 2 +#define MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT 3 +#define MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT 4 +#define MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT 5 +#define MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT 6 +#define MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT 7 +#define MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT 13 +#define MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT 14 +#define MH_DEBUG_REG49_RVALID_q_SHIFT 15 +#define MH_DEBUG_REG49_RREADY_q_SHIFT 16 +#define MH_DEBUG_REG49_RLAST_q_SHIFT 17 +#define MH_DEBUG_REG49_BVALID_q_SHIFT 18 +#define MH_DEBUG_REG49_BREADY_q_SHIFT 19 + +#define MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK 0x00000001 +#define MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK 0x00000002 +#define MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK 0x00000004 +#define MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK 0x00000008 +#define MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK 0x00000010 +#define MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK 0x00000020 +#define MH_DEBUG_REG49_INFLT_LIMIT_q_MASK 0x00000040 +#define MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK 0x00001f80 +#define MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK 0x00002000 +#define MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK 0x00004000 +#define MH_DEBUG_REG49_RVALID_q_MASK 0x00008000 +#define MH_DEBUG_REG49_RREADY_q_MASK 0x00010000 +#define MH_DEBUG_REG49_RLAST_q_MASK 0x00020000 +#define MH_DEBUG_REG49_BVALID_q_MASK 0x00040000 +#define MH_DEBUG_REG49_BREADY_q_MASK 0x00080000 + +#define MH_DEBUG_REG49_MASK \ + (MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK | \ + MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK | \ + MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK | \ + MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK | \ + MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK | \ + MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK | \ + MH_DEBUG_REG49_INFLT_LIMIT_q_MASK | \ + MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK | \ + MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK | \ + MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK | \ + MH_DEBUG_REG49_RVALID_q_MASK | \ + MH_DEBUG_REG49_RREADY_q_MASK | \ + MH_DEBUG_REG49_RLAST_q_MASK | \ + MH_DEBUG_REG49_BVALID_q_MASK | \ + MH_DEBUG_REG49_BREADY_q_MASK) + +#define MH_DEBUG_REG49(ctrl_arc_empty, ctrl_rarc_empty, arq_ctrl_empty, arq_ctrl_write, tlbmiss_ctrl_rts, ctrl_tlbmiss_re_q, inflt_limit_q, inflt_limit_cnt_q, arc_ctrl_re_q, rarc_ctrl_re_q, rvalid_q, rready_q, rlast_q, bvalid_q, bready_q) \ + ((ctrl_arc_empty << MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT) | \ + (ctrl_rarc_empty << MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT) | \ + (arq_ctrl_empty << MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT) | \ + (arq_ctrl_write << MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT) | \ + (tlbmiss_ctrl_rts << MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT) | \ + (ctrl_tlbmiss_re_q << MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT) | \ + (inflt_limit_q << MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT) | \ + (inflt_limit_cnt_q << MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT) | \ + (arc_ctrl_re_q << MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT) | \ + (rarc_ctrl_re_q << MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT) | \ + (rvalid_q << MH_DEBUG_REG49_RVALID_q_SHIFT) | \ + (rready_q << MH_DEBUG_REG49_RREADY_q_SHIFT) | \ + (rlast_q << MH_DEBUG_REG49_RLAST_q_SHIFT) | \ + (bvalid_q << MH_DEBUG_REG49_BVALID_q_SHIFT) | \ + (bready_q << MH_DEBUG_REG49_BREADY_q_SHIFT)) + +#define MH_DEBUG_REG49_GET_CTRL_ARC_EMPTY(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK) >> MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT) +#define MH_DEBUG_REG49_GET_CTRL_RARC_EMPTY(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK) >> MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT) +#define MH_DEBUG_REG49_GET_ARQ_CTRL_EMPTY(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK) >> MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG49_GET_ARQ_CTRL_WRITE(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK) >> MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT) +#define MH_DEBUG_REG49_GET_TLBMISS_CTRL_RTS(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG49_GET_CTRL_TLBMISS_RE_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG49_GET_INFLT_LIMIT_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_INFLT_LIMIT_q_MASK) >> MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT) +#define MH_DEBUG_REG49_GET_INFLT_LIMIT_CNT_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK) >> MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT) +#define MH_DEBUG_REG49_GET_ARC_CTRL_RE_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG49_GET_RARC_CTRL_RE_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK) >> MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG49_GET_RVALID_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_RVALID_q_MASK) >> MH_DEBUG_REG49_RVALID_q_SHIFT) +#define MH_DEBUG_REG49_GET_RREADY_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_RREADY_q_MASK) >> MH_DEBUG_REG49_RREADY_q_SHIFT) +#define MH_DEBUG_REG49_GET_RLAST_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_RLAST_q_MASK) >> MH_DEBUG_REG49_RLAST_q_SHIFT) +#define MH_DEBUG_REG49_GET_BVALID_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_BVALID_q_MASK) >> MH_DEBUG_REG49_BVALID_q_SHIFT) +#define MH_DEBUG_REG49_GET_BREADY_q(mh_debug_reg49) \ + ((mh_debug_reg49 & MH_DEBUG_REG49_BREADY_q_MASK) >> MH_DEBUG_REG49_BREADY_q_SHIFT) + +#define MH_DEBUG_REG49_SET_CTRL_ARC_EMPTY(mh_debug_reg49_reg, ctrl_arc_empty) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_CTRL_ARC_EMPTY_MASK) | (ctrl_arc_empty << MH_DEBUG_REG49_CTRL_ARC_EMPTY_SHIFT) +#define MH_DEBUG_REG49_SET_CTRL_RARC_EMPTY(mh_debug_reg49_reg, ctrl_rarc_empty) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_CTRL_RARC_EMPTY_MASK) | (ctrl_rarc_empty << MH_DEBUG_REG49_CTRL_RARC_EMPTY_SHIFT) +#define MH_DEBUG_REG49_SET_ARQ_CTRL_EMPTY(mh_debug_reg49_reg, arq_ctrl_empty) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_ARQ_CTRL_EMPTY_MASK) | (arq_ctrl_empty << MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SHIFT) +#define MH_DEBUG_REG49_SET_ARQ_CTRL_WRITE(mh_debug_reg49_reg, arq_ctrl_write) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_ARQ_CTRL_WRITE_MASK) | (arq_ctrl_write << MH_DEBUG_REG49_ARQ_CTRL_WRITE_SHIFT) +#define MH_DEBUG_REG49_SET_TLBMISS_CTRL_RTS(mh_debug_reg49_reg, tlbmiss_ctrl_rts) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG49_SET_CTRL_TLBMISS_RE_q(mh_debug_reg49_reg, ctrl_tlbmiss_re_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG49_SET_INFLT_LIMIT_q(mh_debug_reg49_reg, inflt_limit_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_INFLT_LIMIT_q_MASK) | (inflt_limit_q << MH_DEBUG_REG49_INFLT_LIMIT_q_SHIFT) +#define MH_DEBUG_REG49_SET_INFLT_LIMIT_CNT_q(mh_debug_reg49_reg, inflt_limit_cnt_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_MASK) | (inflt_limit_cnt_q << MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SHIFT) +#define MH_DEBUG_REG49_SET_ARC_CTRL_RE_q(mh_debug_reg49_reg, arc_ctrl_re_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_ARC_CTRL_RE_q_MASK) | (arc_ctrl_re_q << MH_DEBUG_REG49_ARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG49_SET_RARC_CTRL_RE_q(mh_debug_reg49_reg, rarc_ctrl_re_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RARC_CTRL_RE_q_MASK) | (rarc_ctrl_re_q << MH_DEBUG_REG49_RARC_CTRL_RE_q_SHIFT) +#define MH_DEBUG_REG49_SET_RVALID_q(mh_debug_reg49_reg, rvalid_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RVALID_q_MASK) | (rvalid_q << MH_DEBUG_REG49_RVALID_q_SHIFT) +#define MH_DEBUG_REG49_SET_RREADY_q(mh_debug_reg49_reg, rready_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RREADY_q_MASK) | (rready_q << MH_DEBUG_REG49_RREADY_q_SHIFT) +#define MH_DEBUG_REG49_SET_RLAST_q(mh_debug_reg49_reg, rlast_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_RLAST_q_MASK) | (rlast_q << MH_DEBUG_REG49_RLAST_q_SHIFT) +#define MH_DEBUG_REG49_SET_BVALID_q(mh_debug_reg49_reg, bvalid_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_BVALID_q_MASK) | (bvalid_q << MH_DEBUG_REG49_BVALID_q_SHIFT) +#define MH_DEBUG_REG49_SET_BREADY_q(mh_debug_reg49_reg, bready_q) \ + mh_debug_reg49_reg = (mh_debug_reg49_reg & ~MH_DEBUG_REG49_BREADY_q_MASK) | (bready_q << MH_DEBUG_REG49_BREADY_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg49_t { + unsigned int ctrl_arc_empty : MH_DEBUG_REG49_CTRL_ARC_EMPTY_SIZE; + unsigned int ctrl_rarc_empty : MH_DEBUG_REG49_CTRL_RARC_EMPTY_SIZE; + unsigned int arq_ctrl_empty : MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SIZE; + unsigned int arq_ctrl_write : MH_DEBUG_REG49_ARQ_CTRL_WRITE_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SIZE; + unsigned int inflt_limit_q : MH_DEBUG_REG49_INFLT_LIMIT_q_SIZE; + unsigned int inflt_limit_cnt_q : MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SIZE; + unsigned int arc_ctrl_re_q : MH_DEBUG_REG49_ARC_CTRL_RE_q_SIZE; + unsigned int rarc_ctrl_re_q : MH_DEBUG_REG49_RARC_CTRL_RE_q_SIZE; + unsigned int rvalid_q : MH_DEBUG_REG49_RVALID_q_SIZE; + unsigned int rready_q : MH_DEBUG_REG49_RREADY_q_SIZE; + unsigned int rlast_q : MH_DEBUG_REG49_RLAST_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG49_BVALID_q_SIZE; + unsigned int bready_q : MH_DEBUG_REG49_BREADY_q_SIZE; + unsigned int : 12; + } mh_debug_reg49_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg49_t { + unsigned int : 12; + unsigned int bready_q : MH_DEBUG_REG49_BREADY_q_SIZE; + unsigned int bvalid_q : MH_DEBUG_REG49_BVALID_q_SIZE; + unsigned int rlast_q : MH_DEBUG_REG49_RLAST_q_SIZE; + unsigned int rready_q : MH_DEBUG_REG49_RREADY_q_SIZE; + unsigned int rvalid_q : MH_DEBUG_REG49_RVALID_q_SIZE; + unsigned int rarc_ctrl_re_q : MH_DEBUG_REG49_RARC_CTRL_RE_q_SIZE; + unsigned int arc_ctrl_re_q : MH_DEBUG_REG49_ARC_CTRL_RE_q_SIZE; + unsigned int inflt_limit_cnt_q : MH_DEBUG_REG49_INFLT_LIMIT_CNT_q_SIZE; + unsigned int inflt_limit_q : MH_DEBUG_REG49_INFLT_LIMIT_q_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG49_CTRL_TLBMISS_RE_q_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG49_TLBMISS_CTRL_RTS_SIZE; + unsigned int arq_ctrl_write : MH_DEBUG_REG49_ARQ_CTRL_WRITE_SIZE; + unsigned int arq_ctrl_empty : MH_DEBUG_REG49_ARQ_CTRL_EMPTY_SIZE; + unsigned int ctrl_rarc_empty : MH_DEBUG_REG49_CTRL_RARC_EMPTY_SIZE; + unsigned int ctrl_arc_empty : MH_DEBUG_REG49_CTRL_ARC_EMPTY_SIZE; + } mh_debug_reg49_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg49_t f; +} mh_debug_reg49_u; + + +/* + * MH_DEBUG_REG50 struct + */ + +#define MH_DEBUG_REG50_MH_CP_grb_send_SIZE 1 +#define MH_DEBUG_REG50_MH_VGT_grb_send_SIZE 1 +#define MH_DEBUG_REG50_MH_TC_mcsend_SIZE 1 +#define MH_DEBUG_REG50_MH_TLBMISS_SEND_SIZE 1 +#define MH_DEBUG_REG50_TLBMISS_VALID_SIZE 1 +#define MH_DEBUG_REG50_RDC_VALID_SIZE 1 +#define MH_DEBUG_REG50_RDC_RID_SIZE 3 +#define MH_DEBUG_REG50_RDC_RLAST_SIZE 1 +#define MH_DEBUG_REG50_RDC_RRESP_SIZE 2 +#define MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SIZE 1 +#define MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SIZE 1 +#define MH_DEBUG_REG50_MMU_ID_REQUEST_q_SIZE 1 +#define MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SIZE 6 +#define MH_DEBUG_REG50_MMU_ID_RESPONSE_SIZE 1 +#define MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SIZE 6 +#define MH_DEBUG_REG50_CNT_HOLD_q1_SIZE 1 +#define MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE 3 + +#define MH_DEBUG_REG50_MH_CP_grb_send_SHIFT 0 +#define MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT 1 +#define MH_DEBUG_REG50_MH_TC_mcsend_SHIFT 2 +#define MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT 3 +#define MH_DEBUG_REG50_TLBMISS_VALID_SHIFT 4 +#define MH_DEBUG_REG50_RDC_VALID_SHIFT 5 +#define MH_DEBUG_REG50_RDC_RID_SHIFT 6 +#define MH_DEBUG_REG50_RDC_RLAST_SHIFT 9 +#define MH_DEBUG_REG50_RDC_RRESP_SHIFT 10 +#define MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT 12 +#define MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT 13 +#define MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT 14 +#define MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT 15 +#define MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT 21 +#define MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT 22 +#define MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT 28 +#define MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT 29 + +#define MH_DEBUG_REG50_MH_CP_grb_send_MASK 0x00000001 +#define MH_DEBUG_REG50_MH_VGT_grb_send_MASK 0x00000002 +#define MH_DEBUG_REG50_MH_TC_mcsend_MASK 0x00000004 +#define MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK 0x00000008 +#define MH_DEBUG_REG50_TLBMISS_VALID_MASK 0x00000010 +#define MH_DEBUG_REG50_RDC_VALID_MASK 0x00000020 +#define MH_DEBUG_REG50_RDC_RID_MASK 0x000001c0 +#define MH_DEBUG_REG50_RDC_RLAST_MASK 0x00000200 +#define MH_DEBUG_REG50_RDC_RRESP_MASK 0x00000c00 +#define MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK 0x00001000 +#define MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK 0x00002000 +#define MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK 0x00004000 +#define MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK 0x001f8000 +#define MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK 0x00200000 +#define MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK 0x0fc00000 +#define MH_DEBUG_REG50_CNT_HOLD_q1_MASK 0x10000000 +#define MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK 0xe0000000 + +#define MH_DEBUG_REG50_MASK \ + (MH_DEBUG_REG50_MH_CP_grb_send_MASK | \ + MH_DEBUG_REG50_MH_VGT_grb_send_MASK | \ + MH_DEBUG_REG50_MH_TC_mcsend_MASK | \ + MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK | \ + MH_DEBUG_REG50_TLBMISS_VALID_MASK | \ + MH_DEBUG_REG50_RDC_VALID_MASK | \ + MH_DEBUG_REG50_RDC_RID_MASK | \ + MH_DEBUG_REG50_RDC_RLAST_MASK | \ + MH_DEBUG_REG50_RDC_RRESP_MASK | \ + MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK | \ + MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK | \ + MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK | \ + MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK | \ + MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK | \ + MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK | \ + MH_DEBUG_REG50_CNT_HOLD_q1_MASK | \ + MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) + +#define MH_DEBUG_REG50(mh_cp_grb_send, mh_vgt_grb_send, mh_tc_mcsend, mh_tlbmiss_send, tlbmiss_valid, rdc_valid, rdc_rid, rdc_rlast, rdc_rresp, tlbmiss_ctrl_rts, ctrl_tlbmiss_re_q, mmu_id_request_q, outstanding_mmuid_cnt_q, mmu_id_response, tlbmiss_return_cnt_q, cnt_hold_q1, mh_clnt_axi_id_reuse_mmur_id) \ + ((mh_cp_grb_send << MH_DEBUG_REG50_MH_CP_grb_send_SHIFT) | \ + (mh_vgt_grb_send << MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT) | \ + (mh_tc_mcsend << MH_DEBUG_REG50_MH_TC_mcsend_SHIFT) | \ + (mh_tlbmiss_send << MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT) | \ + (tlbmiss_valid << MH_DEBUG_REG50_TLBMISS_VALID_SHIFT) | \ + (rdc_valid << MH_DEBUG_REG50_RDC_VALID_SHIFT) | \ + (rdc_rid << MH_DEBUG_REG50_RDC_RID_SHIFT) | \ + (rdc_rlast << MH_DEBUG_REG50_RDC_RLAST_SHIFT) | \ + (rdc_rresp << MH_DEBUG_REG50_RDC_RRESP_SHIFT) | \ + (tlbmiss_ctrl_rts << MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT) | \ + (ctrl_tlbmiss_re_q << MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT) | \ + (mmu_id_request_q << MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT) | \ + (outstanding_mmuid_cnt_q << MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT) | \ + (mmu_id_response << MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT) | \ + (tlbmiss_return_cnt_q << MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT) | \ + (cnt_hold_q1 << MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT) | \ + (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT)) + +#define MH_DEBUG_REG50_GET_MH_CP_grb_send(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MH_CP_grb_send_MASK) >> MH_DEBUG_REG50_MH_CP_grb_send_SHIFT) +#define MH_DEBUG_REG50_GET_MH_VGT_grb_send(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MH_VGT_grb_send_MASK) >> MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT) +#define MH_DEBUG_REG50_GET_MH_TC_mcsend(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MH_TC_mcsend_MASK) >> MH_DEBUG_REG50_MH_TC_mcsend_SHIFT) +#define MH_DEBUG_REG50_GET_MH_TLBMISS_SEND(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK) >> MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT) +#define MH_DEBUG_REG50_GET_TLBMISS_VALID(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_TLBMISS_VALID_MASK) >> MH_DEBUG_REG50_TLBMISS_VALID_SHIFT) +#define MH_DEBUG_REG50_GET_RDC_VALID(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_VALID_MASK) >> MH_DEBUG_REG50_RDC_VALID_SHIFT) +#define MH_DEBUG_REG50_GET_RDC_RID(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_RID_MASK) >> MH_DEBUG_REG50_RDC_RID_SHIFT) +#define MH_DEBUG_REG50_GET_RDC_RLAST(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_RLAST_MASK) >> MH_DEBUG_REG50_RDC_RLAST_SHIFT) +#define MH_DEBUG_REG50_GET_RDC_RRESP(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_RDC_RRESP_MASK) >> MH_DEBUG_REG50_RDC_RRESP_SHIFT) +#define MH_DEBUG_REG50_GET_TLBMISS_CTRL_RTS(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG50_GET_CTRL_TLBMISS_RE_q(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG50_GET_MMU_ID_REQUEST_q(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK) >> MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT) +#define MH_DEBUG_REG50_GET_OUTSTANDING_MMUID_CNT_q(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK) >> MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT) +#define MH_DEBUG_REG50_GET_MMU_ID_RESPONSE(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK) >> MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT) +#define MH_DEBUG_REG50_GET_TLBMISS_RETURN_CNT_q(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK) >> MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT) +#define MH_DEBUG_REG50_GET_CNT_HOLD_q1(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_CNT_HOLD_q1_MASK) >> MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT) +#define MH_DEBUG_REG50_GET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg50) \ + ((mh_debug_reg50 & MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) >> MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) + +#define MH_DEBUG_REG50_SET_MH_CP_grb_send(mh_debug_reg50_reg, mh_cp_grb_send) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_CP_grb_send_MASK) | (mh_cp_grb_send << MH_DEBUG_REG50_MH_CP_grb_send_SHIFT) +#define MH_DEBUG_REG50_SET_MH_VGT_grb_send(mh_debug_reg50_reg, mh_vgt_grb_send) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_VGT_grb_send_MASK) | (mh_vgt_grb_send << MH_DEBUG_REG50_MH_VGT_grb_send_SHIFT) +#define MH_DEBUG_REG50_SET_MH_TC_mcsend(mh_debug_reg50_reg, mh_tc_mcsend) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_TC_mcsend_MASK) | (mh_tc_mcsend << MH_DEBUG_REG50_MH_TC_mcsend_SHIFT) +#define MH_DEBUG_REG50_SET_MH_TLBMISS_SEND(mh_debug_reg50_reg, mh_tlbmiss_send) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_TLBMISS_SEND_MASK) | (mh_tlbmiss_send << MH_DEBUG_REG50_MH_TLBMISS_SEND_SHIFT) +#define MH_DEBUG_REG50_SET_TLBMISS_VALID(mh_debug_reg50_reg, tlbmiss_valid) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_TLBMISS_VALID_MASK) | (tlbmiss_valid << MH_DEBUG_REG50_TLBMISS_VALID_SHIFT) +#define MH_DEBUG_REG50_SET_RDC_VALID(mh_debug_reg50_reg, rdc_valid) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_VALID_MASK) | (rdc_valid << MH_DEBUG_REG50_RDC_VALID_SHIFT) +#define MH_DEBUG_REG50_SET_RDC_RID(mh_debug_reg50_reg, rdc_rid) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_RID_MASK) | (rdc_rid << MH_DEBUG_REG50_RDC_RID_SHIFT) +#define MH_DEBUG_REG50_SET_RDC_RLAST(mh_debug_reg50_reg, rdc_rlast) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_RLAST_MASK) | (rdc_rlast << MH_DEBUG_REG50_RDC_RLAST_SHIFT) +#define MH_DEBUG_REG50_SET_RDC_RRESP(mh_debug_reg50_reg, rdc_rresp) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_RDC_RRESP_MASK) | (rdc_rresp << MH_DEBUG_REG50_RDC_RRESP_SHIFT) +#define MH_DEBUG_REG50_SET_TLBMISS_CTRL_RTS(mh_debug_reg50_reg, tlbmiss_ctrl_rts) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG50_SET_CTRL_TLBMISS_RE_q(mh_debug_reg50_reg, ctrl_tlbmiss_re_q) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG50_SET_MMU_ID_REQUEST_q(mh_debug_reg50_reg, mmu_id_request_q) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MMU_ID_REQUEST_q_MASK) | (mmu_id_request_q << MH_DEBUG_REG50_MMU_ID_REQUEST_q_SHIFT) +#define MH_DEBUG_REG50_SET_OUTSTANDING_MMUID_CNT_q(mh_debug_reg50_reg, outstanding_mmuid_cnt_q) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_MASK) | (outstanding_mmuid_cnt_q << MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SHIFT) +#define MH_DEBUG_REG50_SET_MMU_ID_RESPONSE(mh_debug_reg50_reg, mmu_id_response) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MMU_ID_RESPONSE_MASK) | (mmu_id_response << MH_DEBUG_REG50_MMU_ID_RESPONSE_SHIFT) +#define MH_DEBUG_REG50_SET_TLBMISS_RETURN_CNT_q(mh_debug_reg50_reg, tlbmiss_return_cnt_q) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_MASK) | (tlbmiss_return_cnt_q << MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SHIFT) +#define MH_DEBUG_REG50_SET_CNT_HOLD_q1(mh_debug_reg50_reg, cnt_hold_q1) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_CNT_HOLD_q1_MASK) | (cnt_hold_q1 << MH_DEBUG_REG50_CNT_HOLD_q1_SHIFT) +#define MH_DEBUG_REG50_SET_MH_CLNT_AXI_ID_REUSE_MMUr_ID(mh_debug_reg50_reg, mh_clnt_axi_id_reuse_mmur_id) \ + mh_debug_reg50_reg = (mh_debug_reg50_reg & ~MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_MASK) | (mh_clnt_axi_id_reuse_mmur_id << MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg50_t { + unsigned int mh_cp_grb_send : MH_DEBUG_REG50_MH_CP_grb_send_SIZE; + unsigned int mh_vgt_grb_send : MH_DEBUG_REG50_MH_VGT_grb_send_SIZE; + unsigned int mh_tc_mcsend : MH_DEBUG_REG50_MH_TC_mcsend_SIZE; + unsigned int mh_tlbmiss_send : MH_DEBUG_REG50_MH_TLBMISS_SEND_SIZE; + unsigned int tlbmiss_valid : MH_DEBUG_REG50_TLBMISS_VALID_SIZE; + unsigned int rdc_valid : MH_DEBUG_REG50_RDC_VALID_SIZE; + unsigned int rdc_rid : MH_DEBUG_REG50_RDC_RID_SIZE; + unsigned int rdc_rlast : MH_DEBUG_REG50_RDC_RLAST_SIZE; + unsigned int rdc_rresp : MH_DEBUG_REG50_RDC_RRESP_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SIZE; + unsigned int mmu_id_request_q : MH_DEBUG_REG50_MMU_ID_REQUEST_q_SIZE; + unsigned int outstanding_mmuid_cnt_q : MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SIZE; + unsigned int mmu_id_response : MH_DEBUG_REG50_MMU_ID_RESPONSE_SIZE; + unsigned int tlbmiss_return_cnt_q : MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SIZE; + unsigned int cnt_hold_q1 : MH_DEBUG_REG50_CNT_HOLD_q1_SIZE; + unsigned int mh_clnt_axi_id_reuse_mmur_id : MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + } mh_debug_reg50_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg50_t { + unsigned int mh_clnt_axi_id_reuse_mmur_id : MH_DEBUG_REG50_MH_CLNT_AXI_ID_REUSE_MMUr_ID_SIZE; + unsigned int cnt_hold_q1 : MH_DEBUG_REG50_CNT_HOLD_q1_SIZE; + unsigned int tlbmiss_return_cnt_q : MH_DEBUG_REG50_TLBMISS_RETURN_CNT_q_SIZE; + unsigned int mmu_id_response : MH_DEBUG_REG50_MMU_ID_RESPONSE_SIZE; + unsigned int outstanding_mmuid_cnt_q : MH_DEBUG_REG50_OUTSTANDING_MMUID_CNT_q_SIZE; + unsigned int mmu_id_request_q : MH_DEBUG_REG50_MMU_ID_REQUEST_q_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG50_CTRL_TLBMISS_RE_q_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG50_TLBMISS_CTRL_RTS_SIZE; + unsigned int rdc_rresp : MH_DEBUG_REG50_RDC_RRESP_SIZE; + unsigned int rdc_rlast : MH_DEBUG_REG50_RDC_RLAST_SIZE; + unsigned int rdc_rid : MH_DEBUG_REG50_RDC_RID_SIZE; + unsigned int rdc_valid : MH_DEBUG_REG50_RDC_VALID_SIZE; + unsigned int tlbmiss_valid : MH_DEBUG_REG50_TLBMISS_VALID_SIZE; + unsigned int mh_tlbmiss_send : MH_DEBUG_REG50_MH_TLBMISS_SEND_SIZE; + unsigned int mh_tc_mcsend : MH_DEBUG_REG50_MH_TC_mcsend_SIZE; + unsigned int mh_vgt_grb_send : MH_DEBUG_REG50_MH_VGT_grb_send_SIZE; + unsigned int mh_cp_grb_send : MH_DEBUG_REG50_MH_CP_grb_send_SIZE; + } mh_debug_reg50_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg50_t f; +} mh_debug_reg50_u; + + +/* + * MH_DEBUG_REG51 struct + */ + +#define MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SIZE 32 + +#define MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT 0 + +#define MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK 0xffffffff + +#define MH_DEBUG_REG51_MASK \ + (MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK) + +#define MH_DEBUG_REG51(rf_mmu_page_fault) \ + ((rf_mmu_page_fault << MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT)) + +#define MH_DEBUG_REG51_GET_RF_MMU_PAGE_FAULT(mh_debug_reg51) \ + ((mh_debug_reg51 & MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK) >> MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT) + +#define MH_DEBUG_REG51_SET_RF_MMU_PAGE_FAULT(mh_debug_reg51_reg, rf_mmu_page_fault) \ + mh_debug_reg51_reg = (mh_debug_reg51_reg & ~MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_MASK) | (rf_mmu_page_fault << MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg51_t { + unsigned int rf_mmu_page_fault : MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SIZE; + } mh_debug_reg51_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg51_t { + unsigned int rf_mmu_page_fault : MH_DEBUG_REG51_RF_MMU_PAGE_FAULT_SIZE; + } mh_debug_reg51_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg51_t f; +} mh_debug_reg51_u; + + +/* + * MH_DEBUG_REG52 struct + */ + +#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SIZE 2 +#define MH_DEBUG_REG52_ARB_WE_SIZE 1 +#define MH_DEBUG_REG52_MMU_RTR_SIZE 1 +#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SIZE 22 +#define MH_DEBUG_REG52_ARB_ID_q_SIZE 3 +#define MH_DEBUG_REG52_ARB_WRITE_q_SIZE 1 +#define MH_DEBUG_REG52_client_behavior_q_SIZE 2 + +#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT 0 +#define MH_DEBUG_REG52_ARB_WE_SHIFT 2 +#define MH_DEBUG_REG52_MMU_RTR_SHIFT 3 +#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT 4 +#define MH_DEBUG_REG52_ARB_ID_q_SHIFT 26 +#define MH_DEBUG_REG52_ARB_WRITE_q_SHIFT 29 +#define MH_DEBUG_REG52_client_behavior_q_SHIFT 30 + +#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK 0x00000003 +#define MH_DEBUG_REG52_ARB_WE_MASK 0x00000004 +#define MH_DEBUG_REG52_MMU_RTR_MASK 0x00000008 +#define MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK 0x03fffff0 +#define MH_DEBUG_REG52_ARB_ID_q_MASK 0x1c000000 +#define MH_DEBUG_REG52_ARB_WRITE_q_MASK 0x20000000 +#define MH_DEBUG_REG52_client_behavior_q_MASK 0xc0000000 + +#define MH_DEBUG_REG52_MASK \ + (MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK | \ + MH_DEBUG_REG52_ARB_WE_MASK | \ + MH_DEBUG_REG52_MMU_RTR_MASK | \ + MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK | \ + MH_DEBUG_REG52_ARB_ID_q_MASK | \ + MH_DEBUG_REG52_ARB_WRITE_q_MASK | \ + MH_DEBUG_REG52_client_behavior_q_MASK) + +#define MH_DEBUG_REG52(rf_mmu_config_q_1_to_0, arb_we, mmu_rtr, rf_mmu_config_q_25_to_4, arb_id_q, arb_write_q, client_behavior_q) \ + ((rf_mmu_config_q_1_to_0 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT) | \ + (arb_we << MH_DEBUG_REG52_ARB_WE_SHIFT) | \ + (mmu_rtr << MH_DEBUG_REG52_MMU_RTR_SHIFT) | \ + (rf_mmu_config_q_25_to_4 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT) | \ + (arb_id_q << MH_DEBUG_REG52_ARB_ID_q_SHIFT) | \ + (arb_write_q << MH_DEBUG_REG52_ARB_WRITE_q_SHIFT) | \ + (client_behavior_q << MH_DEBUG_REG52_client_behavior_q_SHIFT)) + +#define MH_DEBUG_REG52_GET_RF_MMU_CONFIG_q_1_to_0(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK) >> MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT) +#define MH_DEBUG_REG52_GET_ARB_WE(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_ARB_WE_MASK) >> MH_DEBUG_REG52_ARB_WE_SHIFT) +#define MH_DEBUG_REG52_GET_MMU_RTR(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_MMU_RTR_MASK) >> MH_DEBUG_REG52_MMU_RTR_SHIFT) +#define MH_DEBUG_REG52_GET_RF_MMU_CONFIG_q_25_to_4(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK) >> MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT) +#define MH_DEBUG_REG52_GET_ARB_ID_q(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_ARB_ID_q_MASK) >> MH_DEBUG_REG52_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG52_GET_ARB_WRITE_q(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_ARB_WRITE_q_MASK) >> MH_DEBUG_REG52_ARB_WRITE_q_SHIFT) +#define MH_DEBUG_REG52_GET_client_behavior_q(mh_debug_reg52) \ + ((mh_debug_reg52 & MH_DEBUG_REG52_client_behavior_q_MASK) >> MH_DEBUG_REG52_client_behavior_q_SHIFT) + +#define MH_DEBUG_REG52_SET_RF_MMU_CONFIG_q_1_to_0(mh_debug_reg52_reg, rf_mmu_config_q_1_to_0) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_MASK) | (rf_mmu_config_q_1_to_0 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SHIFT) +#define MH_DEBUG_REG52_SET_ARB_WE(mh_debug_reg52_reg, arb_we) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_ARB_WE_MASK) | (arb_we << MH_DEBUG_REG52_ARB_WE_SHIFT) +#define MH_DEBUG_REG52_SET_MMU_RTR(mh_debug_reg52_reg, mmu_rtr) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_MMU_RTR_MASK) | (mmu_rtr << MH_DEBUG_REG52_MMU_RTR_SHIFT) +#define MH_DEBUG_REG52_SET_RF_MMU_CONFIG_q_25_to_4(mh_debug_reg52_reg, rf_mmu_config_q_25_to_4) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_MASK) | (rf_mmu_config_q_25_to_4 << MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SHIFT) +#define MH_DEBUG_REG52_SET_ARB_ID_q(mh_debug_reg52_reg, arb_id_q) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_ARB_ID_q_MASK) | (arb_id_q << MH_DEBUG_REG52_ARB_ID_q_SHIFT) +#define MH_DEBUG_REG52_SET_ARB_WRITE_q(mh_debug_reg52_reg, arb_write_q) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_ARB_WRITE_q_MASK) | (arb_write_q << MH_DEBUG_REG52_ARB_WRITE_q_SHIFT) +#define MH_DEBUG_REG52_SET_client_behavior_q(mh_debug_reg52_reg, client_behavior_q) \ + mh_debug_reg52_reg = (mh_debug_reg52_reg & ~MH_DEBUG_REG52_client_behavior_q_MASK) | (client_behavior_q << MH_DEBUG_REG52_client_behavior_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg52_t { + unsigned int rf_mmu_config_q_1_to_0 : MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SIZE; + unsigned int arb_we : MH_DEBUG_REG52_ARB_WE_SIZE; + unsigned int mmu_rtr : MH_DEBUG_REG52_MMU_RTR_SIZE; + unsigned int rf_mmu_config_q_25_to_4 : MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG52_ARB_ID_q_SIZE; + unsigned int arb_write_q : MH_DEBUG_REG52_ARB_WRITE_q_SIZE; + unsigned int client_behavior_q : MH_DEBUG_REG52_client_behavior_q_SIZE; + } mh_debug_reg52_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg52_t { + unsigned int client_behavior_q : MH_DEBUG_REG52_client_behavior_q_SIZE; + unsigned int arb_write_q : MH_DEBUG_REG52_ARB_WRITE_q_SIZE; + unsigned int arb_id_q : MH_DEBUG_REG52_ARB_ID_q_SIZE; + unsigned int rf_mmu_config_q_25_to_4 : MH_DEBUG_REG52_RF_MMU_CONFIG_q_25_to_4_SIZE; + unsigned int mmu_rtr : MH_DEBUG_REG52_MMU_RTR_SIZE; + unsigned int arb_we : MH_DEBUG_REG52_ARB_WE_SIZE; + unsigned int rf_mmu_config_q_1_to_0 : MH_DEBUG_REG52_RF_MMU_CONFIG_q_1_to_0_SIZE; + } mh_debug_reg52_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg52_t f; +} mh_debug_reg52_u; + + +/* + * MH_DEBUG_REG53 struct + */ + +#define MH_DEBUG_REG53_stage1_valid_SIZE 1 +#define MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SIZE 1 +#define MH_DEBUG_REG53_pa_in_mpu_range_SIZE 1 +#define MH_DEBUG_REG53_tag_match_q_SIZE 1 +#define MH_DEBUG_REG53_tag_miss_q_SIZE 1 +#define MH_DEBUG_REG53_va_in_range_q_SIZE 1 +#define MH_DEBUG_REG53_MMU_MISS_SIZE 1 +#define MH_DEBUG_REG53_MMU_READ_MISS_SIZE 1 +#define MH_DEBUG_REG53_MMU_WRITE_MISS_SIZE 1 +#define MH_DEBUG_REG53_MMU_HIT_SIZE 1 +#define MH_DEBUG_REG53_MMU_READ_HIT_SIZE 1 +#define MH_DEBUG_REG53_MMU_WRITE_HIT_SIZE 1 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SIZE 1 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SIZE 1 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SIZE 1 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SIZE 1 +#define MH_DEBUG_REG53_REQ_VA_OFFSET_q_SIZE 16 + +#define MH_DEBUG_REG53_stage1_valid_SHIFT 0 +#define MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT 1 +#define MH_DEBUG_REG53_pa_in_mpu_range_SHIFT 2 +#define MH_DEBUG_REG53_tag_match_q_SHIFT 3 +#define MH_DEBUG_REG53_tag_miss_q_SHIFT 4 +#define MH_DEBUG_REG53_va_in_range_q_SHIFT 5 +#define MH_DEBUG_REG53_MMU_MISS_SHIFT 6 +#define MH_DEBUG_REG53_MMU_READ_MISS_SHIFT 7 +#define MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT 8 +#define MH_DEBUG_REG53_MMU_HIT_SHIFT 9 +#define MH_DEBUG_REG53_MMU_READ_HIT_SHIFT 10 +#define MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT 11 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT 12 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT 13 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT 14 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT 15 +#define MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT 16 + +#define MH_DEBUG_REG53_stage1_valid_MASK 0x00000001 +#define MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK 0x00000002 +#define MH_DEBUG_REG53_pa_in_mpu_range_MASK 0x00000004 +#define MH_DEBUG_REG53_tag_match_q_MASK 0x00000008 +#define MH_DEBUG_REG53_tag_miss_q_MASK 0x00000010 +#define MH_DEBUG_REG53_va_in_range_q_MASK 0x00000020 +#define MH_DEBUG_REG53_MMU_MISS_MASK 0x00000040 +#define MH_DEBUG_REG53_MMU_READ_MISS_MASK 0x00000080 +#define MH_DEBUG_REG53_MMU_WRITE_MISS_MASK 0x00000100 +#define MH_DEBUG_REG53_MMU_HIT_MASK 0x00000200 +#define MH_DEBUG_REG53_MMU_READ_HIT_MASK 0x00000400 +#define MH_DEBUG_REG53_MMU_WRITE_HIT_MASK 0x00000800 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK 0x00001000 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK 0x00002000 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK 0x00004000 +#define MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK 0x00008000 +#define MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK 0xffff0000 + +#define MH_DEBUG_REG53_MASK \ + (MH_DEBUG_REG53_stage1_valid_MASK | \ + MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK | \ + MH_DEBUG_REG53_pa_in_mpu_range_MASK | \ + MH_DEBUG_REG53_tag_match_q_MASK | \ + MH_DEBUG_REG53_tag_miss_q_MASK | \ + MH_DEBUG_REG53_va_in_range_q_MASK | \ + MH_DEBUG_REG53_MMU_MISS_MASK | \ + MH_DEBUG_REG53_MMU_READ_MISS_MASK | \ + MH_DEBUG_REG53_MMU_WRITE_MISS_MASK | \ + MH_DEBUG_REG53_MMU_HIT_MASK | \ + MH_DEBUG_REG53_MMU_READ_HIT_MASK | \ + MH_DEBUG_REG53_MMU_WRITE_HIT_MASK | \ + MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK | \ + MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK | \ + MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK | \ + MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK | \ + MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK) + +#define MH_DEBUG_REG53(stage1_valid, ignore_tag_miss_q, pa_in_mpu_range, tag_match_q, tag_miss_q, va_in_range_q, mmu_miss, mmu_read_miss, mmu_write_miss, mmu_hit, mmu_read_hit, mmu_write_hit, mmu_split_mode_tc_miss, mmu_split_mode_tc_hit, mmu_split_mode_nontc_miss, mmu_split_mode_nontc_hit, req_va_offset_q) \ + ((stage1_valid << MH_DEBUG_REG53_stage1_valid_SHIFT) | \ + (ignore_tag_miss_q << MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT) | \ + (pa_in_mpu_range << MH_DEBUG_REG53_pa_in_mpu_range_SHIFT) | \ + (tag_match_q << MH_DEBUG_REG53_tag_match_q_SHIFT) | \ + (tag_miss_q << MH_DEBUG_REG53_tag_miss_q_SHIFT) | \ + (va_in_range_q << MH_DEBUG_REG53_va_in_range_q_SHIFT) | \ + (mmu_miss << MH_DEBUG_REG53_MMU_MISS_SHIFT) | \ + (mmu_read_miss << MH_DEBUG_REG53_MMU_READ_MISS_SHIFT) | \ + (mmu_write_miss << MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT) | \ + (mmu_hit << MH_DEBUG_REG53_MMU_HIT_SHIFT) | \ + (mmu_read_hit << MH_DEBUG_REG53_MMU_READ_HIT_SHIFT) | \ + (mmu_write_hit << MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT) | \ + (mmu_split_mode_tc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT) | \ + (mmu_split_mode_tc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT) | \ + (mmu_split_mode_nontc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT) | \ + (mmu_split_mode_nontc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT) | \ + (req_va_offset_q << MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT)) + +#define MH_DEBUG_REG53_GET_stage1_valid(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_stage1_valid_MASK) >> MH_DEBUG_REG53_stage1_valid_SHIFT) +#define MH_DEBUG_REG53_GET_IGNORE_TAG_MISS_q(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK) >> MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT) +#define MH_DEBUG_REG53_GET_pa_in_mpu_range(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_pa_in_mpu_range_MASK) >> MH_DEBUG_REG53_pa_in_mpu_range_SHIFT) +#define MH_DEBUG_REG53_GET_tag_match_q(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_tag_match_q_MASK) >> MH_DEBUG_REG53_tag_match_q_SHIFT) +#define MH_DEBUG_REG53_GET_tag_miss_q(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_tag_miss_q_MASK) >> MH_DEBUG_REG53_tag_miss_q_SHIFT) +#define MH_DEBUG_REG53_GET_va_in_range_q(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_va_in_range_q_MASK) >> MH_DEBUG_REG53_va_in_range_q_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_MISS(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_MISS_MASK) >> MH_DEBUG_REG53_MMU_MISS_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_READ_MISS(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_READ_MISS_MASK) >> MH_DEBUG_REG53_MMU_READ_MISS_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_WRITE_MISS(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_WRITE_MISS_MASK) >> MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_HIT(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_HIT_MASK) >> MH_DEBUG_REG53_MMU_HIT_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_READ_HIT(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_READ_HIT_MASK) >> MH_DEBUG_REG53_MMU_READ_HIT_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_WRITE_HIT(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_WRITE_HIT_MASK) >> MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_TC_MISS(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_TC_HIT(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_nonTC_MISS(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT) +#define MH_DEBUG_REG53_GET_MMU_SPLIT_MODE_nonTC_HIT(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK) >> MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT) +#define MH_DEBUG_REG53_GET_REQ_VA_OFFSET_q(mh_debug_reg53) \ + ((mh_debug_reg53 & MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK) >> MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT) + +#define MH_DEBUG_REG53_SET_stage1_valid(mh_debug_reg53_reg, stage1_valid) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_stage1_valid_MASK) | (stage1_valid << MH_DEBUG_REG53_stage1_valid_SHIFT) +#define MH_DEBUG_REG53_SET_IGNORE_TAG_MISS_q(mh_debug_reg53_reg, ignore_tag_miss_q) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_IGNORE_TAG_MISS_q_MASK) | (ignore_tag_miss_q << MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SHIFT) +#define MH_DEBUG_REG53_SET_pa_in_mpu_range(mh_debug_reg53_reg, pa_in_mpu_range) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_pa_in_mpu_range_MASK) | (pa_in_mpu_range << MH_DEBUG_REG53_pa_in_mpu_range_SHIFT) +#define MH_DEBUG_REG53_SET_tag_match_q(mh_debug_reg53_reg, tag_match_q) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_tag_match_q_MASK) | (tag_match_q << MH_DEBUG_REG53_tag_match_q_SHIFT) +#define MH_DEBUG_REG53_SET_tag_miss_q(mh_debug_reg53_reg, tag_miss_q) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_tag_miss_q_MASK) | (tag_miss_q << MH_DEBUG_REG53_tag_miss_q_SHIFT) +#define MH_DEBUG_REG53_SET_va_in_range_q(mh_debug_reg53_reg, va_in_range_q) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_va_in_range_q_MASK) | (va_in_range_q << MH_DEBUG_REG53_va_in_range_q_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_MISS(mh_debug_reg53_reg, mmu_miss) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_MISS_MASK) | (mmu_miss << MH_DEBUG_REG53_MMU_MISS_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_READ_MISS(mh_debug_reg53_reg, mmu_read_miss) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_READ_MISS_MASK) | (mmu_read_miss << MH_DEBUG_REG53_MMU_READ_MISS_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_WRITE_MISS(mh_debug_reg53_reg, mmu_write_miss) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_WRITE_MISS_MASK) | (mmu_write_miss << MH_DEBUG_REG53_MMU_WRITE_MISS_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_HIT(mh_debug_reg53_reg, mmu_hit) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_HIT_MASK) | (mmu_hit << MH_DEBUG_REG53_MMU_HIT_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_READ_HIT(mh_debug_reg53_reg, mmu_read_hit) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_READ_HIT_MASK) | (mmu_read_hit << MH_DEBUG_REG53_MMU_READ_HIT_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_WRITE_HIT(mh_debug_reg53_reg, mmu_write_hit) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_WRITE_HIT_MASK) | (mmu_write_hit << MH_DEBUG_REG53_MMU_WRITE_HIT_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_TC_MISS(mh_debug_reg53_reg, mmu_split_mode_tc_miss) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_MASK) | (mmu_split_mode_tc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_TC_HIT(mh_debug_reg53_reg, mmu_split_mode_tc_hit) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_MASK) | (mmu_split_mode_tc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_nonTC_MISS(mh_debug_reg53_reg, mmu_split_mode_nontc_miss) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_MASK) | (mmu_split_mode_nontc_miss << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SHIFT) +#define MH_DEBUG_REG53_SET_MMU_SPLIT_MODE_nonTC_HIT(mh_debug_reg53_reg, mmu_split_mode_nontc_hit) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_MASK) | (mmu_split_mode_nontc_hit << MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SHIFT) +#define MH_DEBUG_REG53_SET_REQ_VA_OFFSET_q(mh_debug_reg53_reg, req_va_offset_q) \ + mh_debug_reg53_reg = (mh_debug_reg53_reg & ~MH_DEBUG_REG53_REQ_VA_OFFSET_q_MASK) | (req_va_offset_q << MH_DEBUG_REG53_REQ_VA_OFFSET_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg53_t { + unsigned int stage1_valid : MH_DEBUG_REG53_stage1_valid_SIZE; + unsigned int ignore_tag_miss_q : MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SIZE; + unsigned int pa_in_mpu_range : MH_DEBUG_REG53_pa_in_mpu_range_SIZE; + unsigned int tag_match_q : MH_DEBUG_REG53_tag_match_q_SIZE; + unsigned int tag_miss_q : MH_DEBUG_REG53_tag_miss_q_SIZE; + unsigned int va_in_range_q : MH_DEBUG_REG53_va_in_range_q_SIZE; + unsigned int mmu_miss : MH_DEBUG_REG53_MMU_MISS_SIZE; + unsigned int mmu_read_miss : MH_DEBUG_REG53_MMU_READ_MISS_SIZE; + unsigned int mmu_write_miss : MH_DEBUG_REG53_MMU_WRITE_MISS_SIZE; + unsigned int mmu_hit : MH_DEBUG_REG53_MMU_HIT_SIZE; + unsigned int mmu_read_hit : MH_DEBUG_REG53_MMU_READ_HIT_SIZE; + unsigned int mmu_write_hit : MH_DEBUG_REG53_MMU_WRITE_HIT_SIZE; + unsigned int mmu_split_mode_tc_miss : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SIZE; + unsigned int mmu_split_mode_tc_hit : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SIZE; + unsigned int mmu_split_mode_nontc_miss : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SIZE; + unsigned int mmu_split_mode_nontc_hit : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SIZE; + unsigned int req_va_offset_q : MH_DEBUG_REG53_REQ_VA_OFFSET_q_SIZE; + } mh_debug_reg53_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg53_t { + unsigned int req_va_offset_q : MH_DEBUG_REG53_REQ_VA_OFFSET_q_SIZE; + unsigned int mmu_split_mode_nontc_hit : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_HIT_SIZE; + unsigned int mmu_split_mode_nontc_miss : MH_DEBUG_REG53_MMU_SPLIT_MODE_nonTC_MISS_SIZE; + unsigned int mmu_split_mode_tc_hit : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_HIT_SIZE; + unsigned int mmu_split_mode_tc_miss : MH_DEBUG_REG53_MMU_SPLIT_MODE_TC_MISS_SIZE; + unsigned int mmu_write_hit : MH_DEBUG_REG53_MMU_WRITE_HIT_SIZE; + unsigned int mmu_read_hit : MH_DEBUG_REG53_MMU_READ_HIT_SIZE; + unsigned int mmu_hit : MH_DEBUG_REG53_MMU_HIT_SIZE; + unsigned int mmu_write_miss : MH_DEBUG_REG53_MMU_WRITE_MISS_SIZE; + unsigned int mmu_read_miss : MH_DEBUG_REG53_MMU_READ_MISS_SIZE; + unsigned int mmu_miss : MH_DEBUG_REG53_MMU_MISS_SIZE; + unsigned int va_in_range_q : MH_DEBUG_REG53_va_in_range_q_SIZE; + unsigned int tag_miss_q : MH_DEBUG_REG53_tag_miss_q_SIZE; + unsigned int tag_match_q : MH_DEBUG_REG53_tag_match_q_SIZE; + unsigned int pa_in_mpu_range : MH_DEBUG_REG53_pa_in_mpu_range_SIZE; + unsigned int ignore_tag_miss_q : MH_DEBUG_REG53_IGNORE_TAG_MISS_q_SIZE; + unsigned int stage1_valid : MH_DEBUG_REG53_stage1_valid_SIZE; + } mh_debug_reg53_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg53_t f; +} mh_debug_reg53_u; + + +/* + * MH_DEBUG_REG54 struct + */ + +#define MH_DEBUG_REG54_ARQ_RTR_SIZE 1 +#define MH_DEBUG_REG54_MMU_WE_SIZE 1 +#define MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SIZE 1 +#define MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SIZE 1 +#define MH_DEBUG_REG54_MH_TLBMISS_SEND_SIZE 1 +#define MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE 1 +#define MH_DEBUG_REG54_pa_in_mpu_range_SIZE 1 +#define MH_DEBUG_REG54_stage1_valid_SIZE 1 +#define MH_DEBUG_REG54_stage2_valid_SIZE 1 +#define MH_DEBUG_REG54_client_behavior_q_SIZE 2 +#define MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SIZE 1 +#define MH_DEBUG_REG54_tag_match_q_SIZE 1 +#define MH_DEBUG_REG54_tag_miss_q_SIZE 1 +#define MH_DEBUG_REG54_va_in_range_q_SIZE 1 +#define MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SIZE 1 +#define MH_DEBUG_REG54_TAG_valid_q_SIZE 16 + +#define MH_DEBUG_REG54_ARQ_RTR_SHIFT 0 +#define MH_DEBUG_REG54_MMU_WE_SHIFT 1 +#define MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT 2 +#define MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT 3 +#define MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT 4 +#define MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT 5 +#define MH_DEBUG_REG54_pa_in_mpu_range_SHIFT 6 +#define MH_DEBUG_REG54_stage1_valid_SHIFT 7 +#define MH_DEBUG_REG54_stage2_valid_SHIFT 8 +#define MH_DEBUG_REG54_client_behavior_q_SHIFT 9 +#define MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT 11 +#define MH_DEBUG_REG54_tag_match_q_SHIFT 12 +#define MH_DEBUG_REG54_tag_miss_q_SHIFT 13 +#define MH_DEBUG_REG54_va_in_range_q_SHIFT 14 +#define MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT 15 +#define MH_DEBUG_REG54_TAG_valid_q_SHIFT 16 + +#define MH_DEBUG_REG54_ARQ_RTR_MASK 0x00000001 +#define MH_DEBUG_REG54_MMU_WE_MASK 0x00000002 +#define MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK 0x00000004 +#define MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK 0x00000008 +#define MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK 0x00000010 +#define MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK 0x00000020 +#define MH_DEBUG_REG54_pa_in_mpu_range_MASK 0x00000040 +#define MH_DEBUG_REG54_stage1_valid_MASK 0x00000080 +#define MH_DEBUG_REG54_stage2_valid_MASK 0x00000100 +#define MH_DEBUG_REG54_client_behavior_q_MASK 0x00000600 +#define MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK 0x00000800 +#define MH_DEBUG_REG54_tag_match_q_MASK 0x00001000 +#define MH_DEBUG_REG54_tag_miss_q_MASK 0x00002000 +#define MH_DEBUG_REG54_va_in_range_q_MASK 0x00004000 +#define MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK 0x00008000 +#define MH_DEBUG_REG54_TAG_valid_q_MASK 0xffff0000 + +#define MH_DEBUG_REG54_MASK \ + (MH_DEBUG_REG54_ARQ_RTR_MASK | \ + MH_DEBUG_REG54_MMU_WE_MASK | \ + MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK | \ + MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK | \ + MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK | \ + MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK | \ + MH_DEBUG_REG54_pa_in_mpu_range_MASK | \ + MH_DEBUG_REG54_stage1_valid_MASK | \ + MH_DEBUG_REG54_stage2_valid_MASK | \ + MH_DEBUG_REG54_client_behavior_q_MASK | \ + MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK | \ + MH_DEBUG_REG54_tag_match_q_MASK | \ + MH_DEBUG_REG54_tag_miss_q_MASK | \ + MH_DEBUG_REG54_va_in_range_q_MASK | \ + MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK | \ + MH_DEBUG_REG54_TAG_valid_q_MASK) + +#define MH_DEBUG_REG54(arq_rtr, mmu_we, ctrl_tlbmiss_re_q, tlbmiss_ctrl_rts, mh_tlbmiss_send, mmu_stall_awaiting_tlb_miss_fetch, pa_in_mpu_range, stage1_valid, stage2_valid, client_behavior_q, ignore_tag_miss_q, tag_match_q, tag_miss_q, va_in_range_q, pte_fetch_complete_q, tag_valid_q) \ + ((arq_rtr << MH_DEBUG_REG54_ARQ_RTR_SHIFT) | \ + (mmu_we << MH_DEBUG_REG54_MMU_WE_SHIFT) | \ + (ctrl_tlbmiss_re_q << MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT) | \ + (tlbmiss_ctrl_rts << MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT) | \ + (mh_tlbmiss_send << MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT) | \ + (mmu_stall_awaiting_tlb_miss_fetch << MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT) | \ + (pa_in_mpu_range << MH_DEBUG_REG54_pa_in_mpu_range_SHIFT) | \ + (stage1_valid << MH_DEBUG_REG54_stage1_valid_SHIFT) | \ + (stage2_valid << MH_DEBUG_REG54_stage2_valid_SHIFT) | \ + (client_behavior_q << MH_DEBUG_REG54_client_behavior_q_SHIFT) | \ + (ignore_tag_miss_q << MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT) | \ + (tag_match_q << MH_DEBUG_REG54_tag_match_q_SHIFT) | \ + (tag_miss_q << MH_DEBUG_REG54_tag_miss_q_SHIFT) | \ + (va_in_range_q << MH_DEBUG_REG54_va_in_range_q_SHIFT) | \ + (pte_fetch_complete_q << MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT) | \ + (tag_valid_q << MH_DEBUG_REG54_TAG_valid_q_SHIFT)) + +#define MH_DEBUG_REG54_GET_ARQ_RTR(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_ARQ_RTR_MASK) >> MH_DEBUG_REG54_ARQ_RTR_SHIFT) +#define MH_DEBUG_REG54_GET_MMU_WE(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_MMU_WE_MASK) >> MH_DEBUG_REG54_MMU_WE_SHIFT) +#define MH_DEBUG_REG54_GET_CTRL_TLBMISS_RE_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK) >> MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG54_GET_TLBMISS_CTRL_RTS(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK) >> MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG54_GET_MH_TLBMISS_SEND(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK) >> MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT) +#define MH_DEBUG_REG54_GET_MMU_STALL_AWAITING_TLB_MISS_FETCH(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK) >> MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT) +#define MH_DEBUG_REG54_GET_pa_in_mpu_range(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_pa_in_mpu_range_MASK) >> MH_DEBUG_REG54_pa_in_mpu_range_SHIFT) +#define MH_DEBUG_REG54_GET_stage1_valid(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_stage1_valid_MASK) >> MH_DEBUG_REG54_stage1_valid_SHIFT) +#define MH_DEBUG_REG54_GET_stage2_valid(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_stage2_valid_MASK) >> MH_DEBUG_REG54_stage2_valid_SHIFT) +#define MH_DEBUG_REG54_GET_client_behavior_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_client_behavior_q_MASK) >> MH_DEBUG_REG54_client_behavior_q_SHIFT) +#define MH_DEBUG_REG54_GET_IGNORE_TAG_MISS_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK) >> MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT) +#define MH_DEBUG_REG54_GET_tag_match_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_tag_match_q_MASK) >> MH_DEBUG_REG54_tag_match_q_SHIFT) +#define MH_DEBUG_REG54_GET_tag_miss_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_tag_miss_q_MASK) >> MH_DEBUG_REG54_tag_miss_q_SHIFT) +#define MH_DEBUG_REG54_GET_va_in_range_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_va_in_range_q_MASK) >> MH_DEBUG_REG54_va_in_range_q_SHIFT) +#define MH_DEBUG_REG54_GET_PTE_FETCH_COMPLETE_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK) >> MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT) +#define MH_DEBUG_REG54_GET_TAG_valid_q(mh_debug_reg54) \ + ((mh_debug_reg54 & MH_DEBUG_REG54_TAG_valid_q_MASK) >> MH_DEBUG_REG54_TAG_valid_q_SHIFT) + +#define MH_DEBUG_REG54_SET_ARQ_RTR(mh_debug_reg54_reg, arq_rtr) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_ARQ_RTR_MASK) | (arq_rtr << MH_DEBUG_REG54_ARQ_RTR_SHIFT) +#define MH_DEBUG_REG54_SET_MMU_WE(mh_debug_reg54_reg, mmu_we) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_MMU_WE_MASK) | (mmu_we << MH_DEBUG_REG54_MMU_WE_SHIFT) +#define MH_DEBUG_REG54_SET_CTRL_TLBMISS_RE_q(mh_debug_reg54_reg, ctrl_tlbmiss_re_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_MASK) | (ctrl_tlbmiss_re_q << MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SHIFT) +#define MH_DEBUG_REG54_SET_TLBMISS_CTRL_RTS(mh_debug_reg54_reg, tlbmiss_ctrl_rts) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TLBMISS_CTRL_RTS_MASK) | (tlbmiss_ctrl_rts << MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SHIFT) +#define MH_DEBUG_REG54_SET_MH_TLBMISS_SEND(mh_debug_reg54_reg, mh_tlbmiss_send) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_MH_TLBMISS_SEND_MASK) | (mh_tlbmiss_send << MH_DEBUG_REG54_MH_TLBMISS_SEND_SHIFT) +#define MH_DEBUG_REG54_SET_MMU_STALL_AWAITING_TLB_MISS_FETCH(mh_debug_reg54_reg, mmu_stall_awaiting_tlb_miss_fetch) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_MASK) | (mmu_stall_awaiting_tlb_miss_fetch << MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SHIFT) +#define MH_DEBUG_REG54_SET_pa_in_mpu_range(mh_debug_reg54_reg, pa_in_mpu_range) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_pa_in_mpu_range_MASK) | (pa_in_mpu_range << MH_DEBUG_REG54_pa_in_mpu_range_SHIFT) +#define MH_DEBUG_REG54_SET_stage1_valid(mh_debug_reg54_reg, stage1_valid) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_stage1_valid_MASK) | (stage1_valid << MH_DEBUG_REG54_stage1_valid_SHIFT) +#define MH_DEBUG_REG54_SET_stage2_valid(mh_debug_reg54_reg, stage2_valid) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_stage2_valid_MASK) | (stage2_valid << MH_DEBUG_REG54_stage2_valid_SHIFT) +#define MH_DEBUG_REG54_SET_client_behavior_q(mh_debug_reg54_reg, client_behavior_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_client_behavior_q_MASK) | (client_behavior_q << MH_DEBUG_REG54_client_behavior_q_SHIFT) +#define MH_DEBUG_REG54_SET_IGNORE_TAG_MISS_q(mh_debug_reg54_reg, ignore_tag_miss_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_IGNORE_TAG_MISS_q_MASK) | (ignore_tag_miss_q << MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SHIFT) +#define MH_DEBUG_REG54_SET_tag_match_q(mh_debug_reg54_reg, tag_match_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_tag_match_q_MASK) | (tag_match_q << MH_DEBUG_REG54_tag_match_q_SHIFT) +#define MH_DEBUG_REG54_SET_tag_miss_q(mh_debug_reg54_reg, tag_miss_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_tag_miss_q_MASK) | (tag_miss_q << MH_DEBUG_REG54_tag_miss_q_SHIFT) +#define MH_DEBUG_REG54_SET_va_in_range_q(mh_debug_reg54_reg, va_in_range_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_va_in_range_q_MASK) | (va_in_range_q << MH_DEBUG_REG54_va_in_range_q_SHIFT) +#define MH_DEBUG_REG54_SET_PTE_FETCH_COMPLETE_q(mh_debug_reg54_reg, pte_fetch_complete_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_MASK) | (pte_fetch_complete_q << MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SHIFT) +#define MH_DEBUG_REG54_SET_TAG_valid_q(mh_debug_reg54_reg, tag_valid_q) \ + mh_debug_reg54_reg = (mh_debug_reg54_reg & ~MH_DEBUG_REG54_TAG_valid_q_MASK) | (tag_valid_q << MH_DEBUG_REG54_TAG_valid_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg54_t { + unsigned int arq_rtr : MH_DEBUG_REG54_ARQ_RTR_SIZE; + unsigned int mmu_we : MH_DEBUG_REG54_MMU_WE_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SIZE; + unsigned int mh_tlbmiss_send : MH_DEBUG_REG54_MH_TLBMISS_SEND_SIZE; + unsigned int mmu_stall_awaiting_tlb_miss_fetch : MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE; + unsigned int pa_in_mpu_range : MH_DEBUG_REG54_pa_in_mpu_range_SIZE; + unsigned int stage1_valid : MH_DEBUG_REG54_stage1_valid_SIZE; + unsigned int stage2_valid : MH_DEBUG_REG54_stage2_valid_SIZE; + unsigned int client_behavior_q : MH_DEBUG_REG54_client_behavior_q_SIZE; + unsigned int ignore_tag_miss_q : MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SIZE; + unsigned int tag_match_q : MH_DEBUG_REG54_tag_match_q_SIZE; + unsigned int tag_miss_q : MH_DEBUG_REG54_tag_miss_q_SIZE; + unsigned int va_in_range_q : MH_DEBUG_REG54_va_in_range_q_SIZE; + unsigned int pte_fetch_complete_q : MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SIZE; + unsigned int tag_valid_q : MH_DEBUG_REG54_TAG_valid_q_SIZE; + } mh_debug_reg54_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg54_t { + unsigned int tag_valid_q : MH_DEBUG_REG54_TAG_valid_q_SIZE; + unsigned int pte_fetch_complete_q : MH_DEBUG_REG54_PTE_FETCH_COMPLETE_q_SIZE; + unsigned int va_in_range_q : MH_DEBUG_REG54_va_in_range_q_SIZE; + unsigned int tag_miss_q : MH_DEBUG_REG54_tag_miss_q_SIZE; + unsigned int tag_match_q : MH_DEBUG_REG54_tag_match_q_SIZE; + unsigned int ignore_tag_miss_q : MH_DEBUG_REG54_IGNORE_TAG_MISS_q_SIZE; + unsigned int client_behavior_q : MH_DEBUG_REG54_client_behavior_q_SIZE; + unsigned int stage2_valid : MH_DEBUG_REG54_stage2_valid_SIZE; + unsigned int stage1_valid : MH_DEBUG_REG54_stage1_valid_SIZE; + unsigned int pa_in_mpu_range : MH_DEBUG_REG54_pa_in_mpu_range_SIZE; + unsigned int mmu_stall_awaiting_tlb_miss_fetch : MH_DEBUG_REG54_MMU_STALL_AWAITING_TLB_MISS_FETCH_SIZE; + unsigned int mh_tlbmiss_send : MH_DEBUG_REG54_MH_TLBMISS_SEND_SIZE; + unsigned int tlbmiss_ctrl_rts : MH_DEBUG_REG54_TLBMISS_CTRL_RTS_SIZE; + unsigned int ctrl_tlbmiss_re_q : MH_DEBUG_REG54_CTRL_TLBMISS_RE_q_SIZE; + unsigned int mmu_we : MH_DEBUG_REG54_MMU_WE_SIZE; + unsigned int arq_rtr : MH_DEBUG_REG54_ARQ_RTR_SIZE; + } mh_debug_reg54_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg54_t f; +} mh_debug_reg54_u; + + +/* + * MH_DEBUG_REG55 struct + */ + +#define MH_DEBUG_REG55_TAG0_VA_SIZE 13 +#define MH_DEBUG_REG55_TAG_valid_q_0_SIZE 1 +#define MH_DEBUG_REG55_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG55_TAG1_VA_SIZE 13 +#define MH_DEBUG_REG55_TAG_valid_q_1_SIZE 1 + +#define MH_DEBUG_REG55_TAG0_VA_SHIFT 0 +#define MH_DEBUG_REG55_TAG_valid_q_0_SHIFT 13 +#define MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG55_TAG1_VA_SHIFT 16 +#define MH_DEBUG_REG55_TAG_valid_q_1_SHIFT 29 + +#define MH_DEBUG_REG55_TAG0_VA_MASK 0x00001fff +#define MH_DEBUG_REG55_TAG_valid_q_0_MASK 0x00002000 +#define MH_DEBUG_REG55_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG55_TAG1_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG55_TAG_valid_q_1_MASK 0x20000000 + +#define MH_DEBUG_REG55_MASK \ + (MH_DEBUG_REG55_TAG0_VA_MASK | \ + MH_DEBUG_REG55_TAG_valid_q_0_MASK | \ + MH_DEBUG_REG55_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG55_TAG1_VA_MASK | \ + MH_DEBUG_REG55_TAG_valid_q_1_MASK) + +#define MH_DEBUG_REG55(tag0_va, tag_valid_q_0, always_zero, tag1_va, tag_valid_q_1) \ + ((tag0_va << MH_DEBUG_REG55_TAG0_VA_SHIFT) | \ + (tag_valid_q_0 << MH_DEBUG_REG55_TAG_valid_q_0_SHIFT) | \ + (always_zero << MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT) | \ + (tag1_va << MH_DEBUG_REG55_TAG1_VA_SHIFT) | \ + (tag_valid_q_1 << MH_DEBUG_REG55_TAG_valid_q_1_SHIFT)) + +#define MH_DEBUG_REG55_GET_TAG0_VA(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_TAG0_VA_MASK) >> MH_DEBUG_REG55_TAG0_VA_SHIFT) +#define MH_DEBUG_REG55_GET_TAG_valid_q_0(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_TAG_valid_q_0_MASK) >> MH_DEBUG_REG55_TAG_valid_q_0_SHIFT) +#define MH_DEBUG_REG55_GET_ALWAYS_ZERO(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG55_GET_TAG1_VA(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_TAG1_VA_MASK) >> MH_DEBUG_REG55_TAG1_VA_SHIFT) +#define MH_DEBUG_REG55_GET_TAG_valid_q_1(mh_debug_reg55) \ + ((mh_debug_reg55 & MH_DEBUG_REG55_TAG_valid_q_1_MASK) >> MH_DEBUG_REG55_TAG_valid_q_1_SHIFT) + +#define MH_DEBUG_REG55_SET_TAG0_VA(mh_debug_reg55_reg, tag0_va) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG0_VA_MASK) | (tag0_va << MH_DEBUG_REG55_TAG0_VA_SHIFT) +#define MH_DEBUG_REG55_SET_TAG_valid_q_0(mh_debug_reg55_reg, tag_valid_q_0) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG_valid_q_0_MASK) | (tag_valid_q_0 << MH_DEBUG_REG55_TAG_valid_q_0_SHIFT) +#define MH_DEBUG_REG55_SET_ALWAYS_ZERO(mh_debug_reg55_reg, always_zero) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG55_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG55_SET_TAG1_VA(mh_debug_reg55_reg, tag1_va) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG1_VA_MASK) | (tag1_va << MH_DEBUG_REG55_TAG1_VA_SHIFT) +#define MH_DEBUG_REG55_SET_TAG_valid_q_1(mh_debug_reg55_reg, tag_valid_q_1) \ + mh_debug_reg55_reg = (mh_debug_reg55_reg & ~MH_DEBUG_REG55_TAG_valid_q_1_MASK) | (tag_valid_q_1 << MH_DEBUG_REG55_TAG_valid_q_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg55_t { + unsigned int tag0_va : MH_DEBUG_REG55_TAG0_VA_SIZE; + unsigned int tag_valid_q_0 : MH_DEBUG_REG55_TAG_valid_q_0_SIZE; + unsigned int always_zero : MH_DEBUG_REG55_ALWAYS_ZERO_SIZE; + unsigned int tag1_va : MH_DEBUG_REG55_TAG1_VA_SIZE; + unsigned int tag_valid_q_1 : MH_DEBUG_REG55_TAG_valid_q_1_SIZE; + unsigned int : 2; + } mh_debug_reg55_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg55_t { + unsigned int : 2; + unsigned int tag_valid_q_1 : MH_DEBUG_REG55_TAG_valid_q_1_SIZE; + unsigned int tag1_va : MH_DEBUG_REG55_TAG1_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG55_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_0 : MH_DEBUG_REG55_TAG_valid_q_0_SIZE; + unsigned int tag0_va : MH_DEBUG_REG55_TAG0_VA_SIZE; + } mh_debug_reg55_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg55_t f; +} mh_debug_reg55_u; + + +/* + * MH_DEBUG_REG56 struct + */ + +#define MH_DEBUG_REG56_TAG2_VA_SIZE 13 +#define MH_DEBUG_REG56_TAG_valid_q_2_SIZE 1 +#define MH_DEBUG_REG56_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG56_TAG3_VA_SIZE 13 +#define MH_DEBUG_REG56_TAG_valid_q_3_SIZE 1 + +#define MH_DEBUG_REG56_TAG2_VA_SHIFT 0 +#define MH_DEBUG_REG56_TAG_valid_q_2_SHIFT 13 +#define MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG56_TAG3_VA_SHIFT 16 +#define MH_DEBUG_REG56_TAG_valid_q_3_SHIFT 29 + +#define MH_DEBUG_REG56_TAG2_VA_MASK 0x00001fff +#define MH_DEBUG_REG56_TAG_valid_q_2_MASK 0x00002000 +#define MH_DEBUG_REG56_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG56_TAG3_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG56_TAG_valid_q_3_MASK 0x20000000 + +#define MH_DEBUG_REG56_MASK \ + (MH_DEBUG_REG56_TAG2_VA_MASK | \ + MH_DEBUG_REG56_TAG_valid_q_2_MASK | \ + MH_DEBUG_REG56_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG56_TAG3_VA_MASK | \ + MH_DEBUG_REG56_TAG_valid_q_3_MASK) + +#define MH_DEBUG_REG56(tag2_va, tag_valid_q_2, always_zero, tag3_va, tag_valid_q_3) \ + ((tag2_va << MH_DEBUG_REG56_TAG2_VA_SHIFT) | \ + (tag_valid_q_2 << MH_DEBUG_REG56_TAG_valid_q_2_SHIFT) | \ + (always_zero << MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT) | \ + (tag3_va << MH_DEBUG_REG56_TAG3_VA_SHIFT) | \ + (tag_valid_q_3 << MH_DEBUG_REG56_TAG_valid_q_3_SHIFT)) + +#define MH_DEBUG_REG56_GET_TAG2_VA(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_TAG2_VA_MASK) >> MH_DEBUG_REG56_TAG2_VA_SHIFT) +#define MH_DEBUG_REG56_GET_TAG_valid_q_2(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_TAG_valid_q_2_MASK) >> MH_DEBUG_REG56_TAG_valid_q_2_SHIFT) +#define MH_DEBUG_REG56_GET_ALWAYS_ZERO(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG56_GET_TAG3_VA(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_TAG3_VA_MASK) >> MH_DEBUG_REG56_TAG3_VA_SHIFT) +#define MH_DEBUG_REG56_GET_TAG_valid_q_3(mh_debug_reg56) \ + ((mh_debug_reg56 & MH_DEBUG_REG56_TAG_valid_q_3_MASK) >> MH_DEBUG_REG56_TAG_valid_q_3_SHIFT) + +#define MH_DEBUG_REG56_SET_TAG2_VA(mh_debug_reg56_reg, tag2_va) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG2_VA_MASK) | (tag2_va << MH_DEBUG_REG56_TAG2_VA_SHIFT) +#define MH_DEBUG_REG56_SET_TAG_valid_q_2(mh_debug_reg56_reg, tag_valid_q_2) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG_valid_q_2_MASK) | (tag_valid_q_2 << MH_DEBUG_REG56_TAG_valid_q_2_SHIFT) +#define MH_DEBUG_REG56_SET_ALWAYS_ZERO(mh_debug_reg56_reg, always_zero) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG56_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG56_SET_TAG3_VA(mh_debug_reg56_reg, tag3_va) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG3_VA_MASK) | (tag3_va << MH_DEBUG_REG56_TAG3_VA_SHIFT) +#define MH_DEBUG_REG56_SET_TAG_valid_q_3(mh_debug_reg56_reg, tag_valid_q_3) \ + mh_debug_reg56_reg = (mh_debug_reg56_reg & ~MH_DEBUG_REG56_TAG_valid_q_3_MASK) | (tag_valid_q_3 << MH_DEBUG_REG56_TAG_valid_q_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg56_t { + unsigned int tag2_va : MH_DEBUG_REG56_TAG2_VA_SIZE; + unsigned int tag_valid_q_2 : MH_DEBUG_REG56_TAG_valid_q_2_SIZE; + unsigned int always_zero : MH_DEBUG_REG56_ALWAYS_ZERO_SIZE; + unsigned int tag3_va : MH_DEBUG_REG56_TAG3_VA_SIZE; + unsigned int tag_valid_q_3 : MH_DEBUG_REG56_TAG_valid_q_3_SIZE; + unsigned int : 2; + } mh_debug_reg56_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg56_t { + unsigned int : 2; + unsigned int tag_valid_q_3 : MH_DEBUG_REG56_TAG_valid_q_3_SIZE; + unsigned int tag3_va : MH_DEBUG_REG56_TAG3_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG56_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_2 : MH_DEBUG_REG56_TAG_valid_q_2_SIZE; + unsigned int tag2_va : MH_DEBUG_REG56_TAG2_VA_SIZE; + } mh_debug_reg56_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg56_t f; +} mh_debug_reg56_u; + + +/* + * MH_DEBUG_REG57 struct + */ + +#define MH_DEBUG_REG57_TAG4_VA_SIZE 13 +#define MH_DEBUG_REG57_TAG_valid_q_4_SIZE 1 +#define MH_DEBUG_REG57_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG57_TAG5_VA_SIZE 13 +#define MH_DEBUG_REG57_TAG_valid_q_5_SIZE 1 + +#define MH_DEBUG_REG57_TAG4_VA_SHIFT 0 +#define MH_DEBUG_REG57_TAG_valid_q_4_SHIFT 13 +#define MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG57_TAG5_VA_SHIFT 16 +#define MH_DEBUG_REG57_TAG_valid_q_5_SHIFT 29 + +#define MH_DEBUG_REG57_TAG4_VA_MASK 0x00001fff +#define MH_DEBUG_REG57_TAG_valid_q_4_MASK 0x00002000 +#define MH_DEBUG_REG57_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG57_TAG5_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG57_TAG_valid_q_5_MASK 0x20000000 + +#define MH_DEBUG_REG57_MASK \ + (MH_DEBUG_REG57_TAG4_VA_MASK | \ + MH_DEBUG_REG57_TAG_valid_q_4_MASK | \ + MH_DEBUG_REG57_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG57_TAG5_VA_MASK | \ + MH_DEBUG_REG57_TAG_valid_q_5_MASK) + +#define MH_DEBUG_REG57(tag4_va, tag_valid_q_4, always_zero, tag5_va, tag_valid_q_5) \ + ((tag4_va << MH_DEBUG_REG57_TAG4_VA_SHIFT) | \ + (tag_valid_q_4 << MH_DEBUG_REG57_TAG_valid_q_4_SHIFT) | \ + (always_zero << MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT) | \ + (tag5_va << MH_DEBUG_REG57_TAG5_VA_SHIFT) | \ + (tag_valid_q_5 << MH_DEBUG_REG57_TAG_valid_q_5_SHIFT)) + +#define MH_DEBUG_REG57_GET_TAG4_VA(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_TAG4_VA_MASK) >> MH_DEBUG_REG57_TAG4_VA_SHIFT) +#define MH_DEBUG_REG57_GET_TAG_valid_q_4(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_TAG_valid_q_4_MASK) >> MH_DEBUG_REG57_TAG_valid_q_4_SHIFT) +#define MH_DEBUG_REG57_GET_ALWAYS_ZERO(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG57_GET_TAG5_VA(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_TAG5_VA_MASK) >> MH_DEBUG_REG57_TAG5_VA_SHIFT) +#define MH_DEBUG_REG57_GET_TAG_valid_q_5(mh_debug_reg57) \ + ((mh_debug_reg57 & MH_DEBUG_REG57_TAG_valid_q_5_MASK) >> MH_DEBUG_REG57_TAG_valid_q_5_SHIFT) + +#define MH_DEBUG_REG57_SET_TAG4_VA(mh_debug_reg57_reg, tag4_va) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG4_VA_MASK) | (tag4_va << MH_DEBUG_REG57_TAG4_VA_SHIFT) +#define MH_DEBUG_REG57_SET_TAG_valid_q_4(mh_debug_reg57_reg, tag_valid_q_4) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG_valid_q_4_MASK) | (tag_valid_q_4 << MH_DEBUG_REG57_TAG_valid_q_4_SHIFT) +#define MH_DEBUG_REG57_SET_ALWAYS_ZERO(mh_debug_reg57_reg, always_zero) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG57_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG57_SET_TAG5_VA(mh_debug_reg57_reg, tag5_va) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG5_VA_MASK) | (tag5_va << MH_DEBUG_REG57_TAG5_VA_SHIFT) +#define MH_DEBUG_REG57_SET_TAG_valid_q_5(mh_debug_reg57_reg, tag_valid_q_5) \ + mh_debug_reg57_reg = (mh_debug_reg57_reg & ~MH_DEBUG_REG57_TAG_valid_q_5_MASK) | (tag_valid_q_5 << MH_DEBUG_REG57_TAG_valid_q_5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg57_t { + unsigned int tag4_va : MH_DEBUG_REG57_TAG4_VA_SIZE; + unsigned int tag_valid_q_4 : MH_DEBUG_REG57_TAG_valid_q_4_SIZE; + unsigned int always_zero : MH_DEBUG_REG57_ALWAYS_ZERO_SIZE; + unsigned int tag5_va : MH_DEBUG_REG57_TAG5_VA_SIZE; + unsigned int tag_valid_q_5 : MH_DEBUG_REG57_TAG_valid_q_5_SIZE; + unsigned int : 2; + } mh_debug_reg57_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg57_t { + unsigned int : 2; + unsigned int tag_valid_q_5 : MH_DEBUG_REG57_TAG_valid_q_5_SIZE; + unsigned int tag5_va : MH_DEBUG_REG57_TAG5_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG57_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_4 : MH_DEBUG_REG57_TAG_valid_q_4_SIZE; + unsigned int tag4_va : MH_DEBUG_REG57_TAG4_VA_SIZE; + } mh_debug_reg57_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg57_t f; +} mh_debug_reg57_u; + + +/* + * MH_DEBUG_REG58 struct + */ + +#define MH_DEBUG_REG58_TAG6_VA_SIZE 13 +#define MH_DEBUG_REG58_TAG_valid_q_6_SIZE 1 +#define MH_DEBUG_REG58_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG58_TAG7_VA_SIZE 13 +#define MH_DEBUG_REG58_TAG_valid_q_7_SIZE 1 + +#define MH_DEBUG_REG58_TAG6_VA_SHIFT 0 +#define MH_DEBUG_REG58_TAG_valid_q_6_SHIFT 13 +#define MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG58_TAG7_VA_SHIFT 16 +#define MH_DEBUG_REG58_TAG_valid_q_7_SHIFT 29 + +#define MH_DEBUG_REG58_TAG6_VA_MASK 0x00001fff +#define MH_DEBUG_REG58_TAG_valid_q_6_MASK 0x00002000 +#define MH_DEBUG_REG58_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG58_TAG7_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG58_TAG_valid_q_7_MASK 0x20000000 + +#define MH_DEBUG_REG58_MASK \ + (MH_DEBUG_REG58_TAG6_VA_MASK | \ + MH_DEBUG_REG58_TAG_valid_q_6_MASK | \ + MH_DEBUG_REG58_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG58_TAG7_VA_MASK | \ + MH_DEBUG_REG58_TAG_valid_q_7_MASK) + +#define MH_DEBUG_REG58(tag6_va, tag_valid_q_6, always_zero, tag7_va, tag_valid_q_7) \ + ((tag6_va << MH_DEBUG_REG58_TAG6_VA_SHIFT) | \ + (tag_valid_q_6 << MH_DEBUG_REG58_TAG_valid_q_6_SHIFT) | \ + (always_zero << MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT) | \ + (tag7_va << MH_DEBUG_REG58_TAG7_VA_SHIFT) | \ + (tag_valid_q_7 << MH_DEBUG_REG58_TAG_valid_q_7_SHIFT)) + +#define MH_DEBUG_REG58_GET_TAG6_VA(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_TAG6_VA_MASK) >> MH_DEBUG_REG58_TAG6_VA_SHIFT) +#define MH_DEBUG_REG58_GET_TAG_valid_q_6(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_TAG_valid_q_6_MASK) >> MH_DEBUG_REG58_TAG_valid_q_6_SHIFT) +#define MH_DEBUG_REG58_GET_ALWAYS_ZERO(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG58_GET_TAG7_VA(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_TAG7_VA_MASK) >> MH_DEBUG_REG58_TAG7_VA_SHIFT) +#define MH_DEBUG_REG58_GET_TAG_valid_q_7(mh_debug_reg58) \ + ((mh_debug_reg58 & MH_DEBUG_REG58_TAG_valid_q_7_MASK) >> MH_DEBUG_REG58_TAG_valid_q_7_SHIFT) + +#define MH_DEBUG_REG58_SET_TAG6_VA(mh_debug_reg58_reg, tag6_va) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG6_VA_MASK) | (tag6_va << MH_DEBUG_REG58_TAG6_VA_SHIFT) +#define MH_DEBUG_REG58_SET_TAG_valid_q_6(mh_debug_reg58_reg, tag_valid_q_6) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG_valid_q_6_MASK) | (tag_valid_q_6 << MH_DEBUG_REG58_TAG_valid_q_6_SHIFT) +#define MH_DEBUG_REG58_SET_ALWAYS_ZERO(mh_debug_reg58_reg, always_zero) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG58_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG58_SET_TAG7_VA(mh_debug_reg58_reg, tag7_va) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG7_VA_MASK) | (tag7_va << MH_DEBUG_REG58_TAG7_VA_SHIFT) +#define MH_DEBUG_REG58_SET_TAG_valid_q_7(mh_debug_reg58_reg, tag_valid_q_7) \ + mh_debug_reg58_reg = (mh_debug_reg58_reg & ~MH_DEBUG_REG58_TAG_valid_q_7_MASK) | (tag_valid_q_7 << MH_DEBUG_REG58_TAG_valid_q_7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg58_t { + unsigned int tag6_va : MH_DEBUG_REG58_TAG6_VA_SIZE; + unsigned int tag_valid_q_6 : MH_DEBUG_REG58_TAG_valid_q_6_SIZE; + unsigned int always_zero : MH_DEBUG_REG58_ALWAYS_ZERO_SIZE; + unsigned int tag7_va : MH_DEBUG_REG58_TAG7_VA_SIZE; + unsigned int tag_valid_q_7 : MH_DEBUG_REG58_TAG_valid_q_7_SIZE; + unsigned int : 2; + } mh_debug_reg58_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg58_t { + unsigned int : 2; + unsigned int tag_valid_q_7 : MH_DEBUG_REG58_TAG_valid_q_7_SIZE; + unsigned int tag7_va : MH_DEBUG_REG58_TAG7_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG58_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_6 : MH_DEBUG_REG58_TAG_valid_q_6_SIZE; + unsigned int tag6_va : MH_DEBUG_REG58_TAG6_VA_SIZE; + } mh_debug_reg58_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg58_t f; +} mh_debug_reg58_u; + + +/* + * MH_DEBUG_REG59 struct + */ + +#define MH_DEBUG_REG59_TAG8_VA_SIZE 13 +#define MH_DEBUG_REG59_TAG_valid_q_8_SIZE 1 +#define MH_DEBUG_REG59_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG59_TAG9_VA_SIZE 13 +#define MH_DEBUG_REG59_TAG_valid_q_9_SIZE 1 + +#define MH_DEBUG_REG59_TAG8_VA_SHIFT 0 +#define MH_DEBUG_REG59_TAG_valid_q_8_SHIFT 13 +#define MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG59_TAG9_VA_SHIFT 16 +#define MH_DEBUG_REG59_TAG_valid_q_9_SHIFT 29 + +#define MH_DEBUG_REG59_TAG8_VA_MASK 0x00001fff +#define MH_DEBUG_REG59_TAG_valid_q_8_MASK 0x00002000 +#define MH_DEBUG_REG59_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG59_TAG9_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG59_TAG_valid_q_9_MASK 0x20000000 + +#define MH_DEBUG_REG59_MASK \ + (MH_DEBUG_REG59_TAG8_VA_MASK | \ + MH_DEBUG_REG59_TAG_valid_q_8_MASK | \ + MH_DEBUG_REG59_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG59_TAG9_VA_MASK | \ + MH_DEBUG_REG59_TAG_valid_q_9_MASK) + +#define MH_DEBUG_REG59(tag8_va, tag_valid_q_8, always_zero, tag9_va, tag_valid_q_9) \ + ((tag8_va << MH_DEBUG_REG59_TAG8_VA_SHIFT) | \ + (tag_valid_q_8 << MH_DEBUG_REG59_TAG_valid_q_8_SHIFT) | \ + (always_zero << MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT) | \ + (tag9_va << MH_DEBUG_REG59_TAG9_VA_SHIFT) | \ + (tag_valid_q_9 << MH_DEBUG_REG59_TAG_valid_q_9_SHIFT)) + +#define MH_DEBUG_REG59_GET_TAG8_VA(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_TAG8_VA_MASK) >> MH_DEBUG_REG59_TAG8_VA_SHIFT) +#define MH_DEBUG_REG59_GET_TAG_valid_q_8(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_TAG_valid_q_8_MASK) >> MH_DEBUG_REG59_TAG_valid_q_8_SHIFT) +#define MH_DEBUG_REG59_GET_ALWAYS_ZERO(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG59_GET_TAG9_VA(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_TAG9_VA_MASK) >> MH_DEBUG_REG59_TAG9_VA_SHIFT) +#define MH_DEBUG_REG59_GET_TAG_valid_q_9(mh_debug_reg59) \ + ((mh_debug_reg59 & MH_DEBUG_REG59_TAG_valid_q_9_MASK) >> MH_DEBUG_REG59_TAG_valid_q_9_SHIFT) + +#define MH_DEBUG_REG59_SET_TAG8_VA(mh_debug_reg59_reg, tag8_va) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG8_VA_MASK) | (tag8_va << MH_DEBUG_REG59_TAG8_VA_SHIFT) +#define MH_DEBUG_REG59_SET_TAG_valid_q_8(mh_debug_reg59_reg, tag_valid_q_8) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG_valid_q_8_MASK) | (tag_valid_q_8 << MH_DEBUG_REG59_TAG_valid_q_8_SHIFT) +#define MH_DEBUG_REG59_SET_ALWAYS_ZERO(mh_debug_reg59_reg, always_zero) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG59_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG59_SET_TAG9_VA(mh_debug_reg59_reg, tag9_va) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG9_VA_MASK) | (tag9_va << MH_DEBUG_REG59_TAG9_VA_SHIFT) +#define MH_DEBUG_REG59_SET_TAG_valid_q_9(mh_debug_reg59_reg, tag_valid_q_9) \ + mh_debug_reg59_reg = (mh_debug_reg59_reg & ~MH_DEBUG_REG59_TAG_valid_q_9_MASK) | (tag_valid_q_9 << MH_DEBUG_REG59_TAG_valid_q_9_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg59_t { + unsigned int tag8_va : MH_DEBUG_REG59_TAG8_VA_SIZE; + unsigned int tag_valid_q_8 : MH_DEBUG_REG59_TAG_valid_q_8_SIZE; + unsigned int always_zero : MH_DEBUG_REG59_ALWAYS_ZERO_SIZE; + unsigned int tag9_va : MH_DEBUG_REG59_TAG9_VA_SIZE; + unsigned int tag_valid_q_9 : MH_DEBUG_REG59_TAG_valid_q_9_SIZE; + unsigned int : 2; + } mh_debug_reg59_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg59_t { + unsigned int : 2; + unsigned int tag_valid_q_9 : MH_DEBUG_REG59_TAG_valid_q_9_SIZE; + unsigned int tag9_va : MH_DEBUG_REG59_TAG9_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG59_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_8 : MH_DEBUG_REG59_TAG_valid_q_8_SIZE; + unsigned int tag8_va : MH_DEBUG_REG59_TAG8_VA_SIZE; + } mh_debug_reg59_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg59_t f; +} mh_debug_reg59_u; + + +/* + * MH_DEBUG_REG60 struct + */ + +#define MH_DEBUG_REG60_TAG10_VA_SIZE 13 +#define MH_DEBUG_REG60_TAG_valid_q_10_SIZE 1 +#define MH_DEBUG_REG60_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG60_TAG11_VA_SIZE 13 +#define MH_DEBUG_REG60_TAG_valid_q_11_SIZE 1 + +#define MH_DEBUG_REG60_TAG10_VA_SHIFT 0 +#define MH_DEBUG_REG60_TAG_valid_q_10_SHIFT 13 +#define MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG60_TAG11_VA_SHIFT 16 +#define MH_DEBUG_REG60_TAG_valid_q_11_SHIFT 29 + +#define MH_DEBUG_REG60_TAG10_VA_MASK 0x00001fff +#define MH_DEBUG_REG60_TAG_valid_q_10_MASK 0x00002000 +#define MH_DEBUG_REG60_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG60_TAG11_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG60_TAG_valid_q_11_MASK 0x20000000 + +#define MH_DEBUG_REG60_MASK \ + (MH_DEBUG_REG60_TAG10_VA_MASK | \ + MH_DEBUG_REG60_TAG_valid_q_10_MASK | \ + MH_DEBUG_REG60_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG60_TAG11_VA_MASK | \ + MH_DEBUG_REG60_TAG_valid_q_11_MASK) + +#define MH_DEBUG_REG60(tag10_va, tag_valid_q_10, always_zero, tag11_va, tag_valid_q_11) \ + ((tag10_va << MH_DEBUG_REG60_TAG10_VA_SHIFT) | \ + (tag_valid_q_10 << MH_DEBUG_REG60_TAG_valid_q_10_SHIFT) | \ + (always_zero << MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT) | \ + (tag11_va << MH_DEBUG_REG60_TAG11_VA_SHIFT) | \ + (tag_valid_q_11 << MH_DEBUG_REG60_TAG_valid_q_11_SHIFT)) + +#define MH_DEBUG_REG60_GET_TAG10_VA(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_TAG10_VA_MASK) >> MH_DEBUG_REG60_TAG10_VA_SHIFT) +#define MH_DEBUG_REG60_GET_TAG_valid_q_10(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_TAG_valid_q_10_MASK) >> MH_DEBUG_REG60_TAG_valid_q_10_SHIFT) +#define MH_DEBUG_REG60_GET_ALWAYS_ZERO(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG60_GET_TAG11_VA(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_TAG11_VA_MASK) >> MH_DEBUG_REG60_TAG11_VA_SHIFT) +#define MH_DEBUG_REG60_GET_TAG_valid_q_11(mh_debug_reg60) \ + ((mh_debug_reg60 & MH_DEBUG_REG60_TAG_valid_q_11_MASK) >> MH_DEBUG_REG60_TAG_valid_q_11_SHIFT) + +#define MH_DEBUG_REG60_SET_TAG10_VA(mh_debug_reg60_reg, tag10_va) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG10_VA_MASK) | (tag10_va << MH_DEBUG_REG60_TAG10_VA_SHIFT) +#define MH_DEBUG_REG60_SET_TAG_valid_q_10(mh_debug_reg60_reg, tag_valid_q_10) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG_valid_q_10_MASK) | (tag_valid_q_10 << MH_DEBUG_REG60_TAG_valid_q_10_SHIFT) +#define MH_DEBUG_REG60_SET_ALWAYS_ZERO(mh_debug_reg60_reg, always_zero) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG60_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG60_SET_TAG11_VA(mh_debug_reg60_reg, tag11_va) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG11_VA_MASK) | (tag11_va << MH_DEBUG_REG60_TAG11_VA_SHIFT) +#define MH_DEBUG_REG60_SET_TAG_valid_q_11(mh_debug_reg60_reg, tag_valid_q_11) \ + mh_debug_reg60_reg = (mh_debug_reg60_reg & ~MH_DEBUG_REG60_TAG_valid_q_11_MASK) | (tag_valid_q_11 << MH_DEBUG_REG60_TAG_valid_q_11_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg60_t { + unsigned int tag10_va : MH_DEBUG_REG60_TAG10_VA_SIZE; + unsigned int tag_valid_q_10 : MH_DEBUG_REG60_TAG_valid_q_10_SIZE; + unsigned int always_zero : MH_DEBUG_REG60_ALWAYS_ZERO_SIZE; + unsigned int tag11_va : MH_DEBUG_REG60_TAG11_VA_SIZE; + unsigned int tag_valid_q_11 : MH_DEBUG_REG60_TAG_valid_q_11_SIZE; + unsigned int : 2; + } mh_debug_reg60_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg60_t { + unsigned int : 2; + unsigned int tag_valid_q_11 : MH_DEBUG_REG60_TAG_valid_q_11_SIZE; + unsigned int tag11_va : MH_DEBUG_REG60_TAG11_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG60_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_10 : MH_DEBUG_REG60_TAG_valid_q_10_SIZE; + unsigned int tag10_va : MH_DEBUG_REG60_TAG10_VA_SIZE; + } mh_debug_reg60_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg60_t f; +} mh_debug_reg60_u; + + +/* + * MH_DEBUG_REG61 struct + */ + +#define MH_DEBUG_REG61_TAG12_VA_SIZE 13 +#define MH_DEBUG_REG61_TAG_valid_q_12_SIZE 1 +#define MH_DEBUG_REG61_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG61_TAG13_VA_SIZE 13 +#define MH_DEBUG_REG61_TAG_valid_q_13_SIZE 1 + +#define MH_DEBUG_REG61_TAG12_VA_SHIFT 0 +#define MH_DEBUG_REG61_TAG_valid_q_12_SHIFT 13 +#define MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG61_TAG13_VA_SHIFT 16 +#define MH_DEBUG_REG61_TAG_valid_q_13_SHIFT 29 + +#define MH_DEBUG_REG61_TAG12_VA_MASK 0x00001fff +#define MH_DEBUG_REG61_TAG_valid_q_12_MASK 0x00002000 +#define MH_DEBUG_REG61_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG61_TAG13_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG61_TAG_valid_q_13_MASK 0x20000000 + +#define MH_DEBUG_REG61_MASK \ + (MH_DEBUG_REG61_TAG12_VA_MASK | \ + MH_DEBUG_REG61_TAG_valid_q_12_MASK | \ + MH_DEBUG_REG61_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG61_TAG13_VA_MASK | \ + MH_DEBUG_REG61_TAG_valid_q_13_MASK) + +#define MH_DEBUG_REG61(tag12_va, tag_valid_q_12, always_zero, tag13_va, tag_valid_q_13) \ + ((tag12_va << MH_DEBUG_REG61_TAG12_VA_SHIFT) | \ + (tag_valid_q_12 << MH_DEBUG_REG61_TAG_valid_q_12_SHIFT) | \ + (always_zero << MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT) | \ + (tag13_va << MH_DEBUG_REG61_TAG13_VA_SHIFT) | \ + (tag_valid_q_13 << MH_DEBUG_REG61_TAG_valid_q_13_SHIFT)) + +#define MH_DEBUG_REG61_GET_TAG12_VA(mh_debug_reg61) \ + ((mh_debug_reg61 & MH_DEBUG_REG61_TAG12_VA_MASK) >> MH_DEBUG_REG61_TAG12_VA_SHIFT) +#define MH_DEBUG_REG61_GET_TAG_valid_q_12(mh_debug_reg61) \ + ((mh_debug_reg61 & MH_DEBUG_REG61_TAG_valid_q_12_MASK) >> MH_DEBUG_REG61_TAG_valid_q_12_SHIFT) +#define MH_DEBUG_REG61_GET_ALWAYS_ZERO(mh_debug_reg61) \ + ((mh_debug_reg61 & MH_DEBUG_REG61_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG61_GET_TAG13_VA(mh_debug_reg61) \ + ((mh_debug_reg61 & MH_DEBUG_REG61_TAG13_VA_MASK) >> MH_DEBUG_REG61_TAG13_VA_SHIFT) +#define MH_DEBUG_REG61_GET_TAG_valid_q_13(mh_debug_reg61) \ + ((mh_debug_reg61 & MH_DEBUG_REG61_TAG_valid_q_13_MASK) >> MH_DEBUG_REG61_TAG_valid_q_13_SHIFT) + +#define MH_DEBUG_REG61_SET_TAG12_VA(mh_debug_reg61_reg, tag12_va) \ + mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG12_VA_MASK) | (tag12_va << MH_DEBUG_REG61_TAG12_VA_SHIFT) +#define MH_DEBUG_REG61_SET_TAG_valid_q_12(mh_debug_reg61_reg, tag_valid_q_12) \ + mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG_valid_q_12_MASK) | (tag_valid_q_12 << MH_DEBUG_REG61_TAG_valid_q_12_SHIFT) +#define MH_DEBUG_REG61_SET_ALWAYS_ZERO(mh_debug_reg61_reg, always_zero) \ + mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG61_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG61_SET_TAG13_VA(mh_debug_reg61_reg, tag13_va) \ + mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG13_VA_MASK) | (tag13_va << MH_DEBUG_REG61_TAG13_VA_SHIFT) +#define MH_DEBUG_REG61_SET_TAG_valid_q_13(mh_debug_reg61_reg, tag_valid_q_13) \ + mh_debug_reg61_reg = (mh_debug_reg61_reg & ~MH_DEBUG_REG61_TAG_valid_q_13_MASK) | (tag_valid_q_13 << MH_DEBUG_REG61_TAG_valid_q_13_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg61_t { + unsigned int tag12_va : MH_DEBUG_REG61_TAG12_VA_SIZE; + unsigned int tag_valid_q_12 : MH_DEBUG_REG61_TAG_valid_q_12_SIZE; + unsigned int always_zero : MH_DEBUG_REG61_ALWAYS_ZERO_SIZE; + unsigned int tag13_va : MH_DEBUG_REG61_TAG13_VA_SIZE; + unsigned int tag_valid_q_13 : MH_DEBUG_REG61_TAG_valid_q_13_SIZE; + unsigned int : 2; + } mh_debug_reg61_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg61_t { + unsigned int : 2; + unsigned int tag_valid_q_13 : MH_DEBUG_REG61_TAG_valid_q_13_SIZE; + unsigned int tag13_va : MH_DEBUG_REG61_TAG13_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG61_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_12 : MH_DEBUG_REG61_TAG_valid_q_12_SIZE; + unsigned int tag12_va : MH_DEBUG_REG61_TAG12_VA_SIZE; + } mh_debug_reg61_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg61_t f; +} mh_debug_reg61_u; + + +/* + * MH_DEBUG_REG62 struct + */ + +#define MH_DEBUG_REG62_TAG14_VA_SIZE 13 +#define MH_DEBUG_REG62_TAG_valid_q_14_SIZE 1 +#define MH_DEBUG_REG62_ALWAYS_ZERO_SIZE 2 +#define MH_DEBUG_REG62_TAG15_VA_SIZE 13 +#define MH_DEBUG_REG62_TAG_valid_q_15_SIZE 1 + +#define MH_DEBUG_REG62_TAG14_VA_SHIFT 0 +#define MH_DEBUG_REG62_TAG_valid_q_14_SHIFT 13 +#define MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT 14 +#define MH_DEBUG_REG62_TAG15_VA_SHIFT 16 +#define MH_DEBUG_REG62_TAG_valid_q_15_SHIFT 29 + +#define MH_DEBUG_REG62_TAG14_VA_MASK 0x00001fff +#define MH_DEBUG_REG62_TAG_valid_q_14_MASK 0x00002000 +#define MH_DEBUG_REG62_ALWAYS_ZERO_MASK 0x0000c000 +#define MH_DEBUG_REG62_TAG15_VA_MASK 0x1fff0000 +#define MH_DEBUG_REG62_TAG_valid_q_15_MASK 0x20000000 + +#define MH_DEBUG_REG62_MASK \ + (MH_DEBUG_REG62_TAG14_VA_MASK | \ + MH_DEBUG_REG62_TAG_valid_q_14_MASK | \ + MH_DEBUG_REG62_ALWAYS_ZERO_MASK | \ + MH_DEBUG_REG62_TAG15_VA_MASK | \ + MH_DEBUG_REG62_TAG_valid_q_15_MASK) + +#define MH_DEBUG_REG62(tag14_va, tag_valid_q_14, always_zero, tag15_va, tag_valid_q_15) \ + ((tag14_va << MH_DEBUG_REG62_TAG14_VA_SHIFT) | \ + (tag_valid_q_14 << MH_DEBUG_REG62_TAG_valid_q_14_SHIFT) | \ + (always_zero << MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT) | \ + (tag15_va << MH_DEBUG_REG62_TAG15_VA_SHIFT) | \ + (tag_valid_q_15 << MH_DEBUG_REG62_TAG_valid_q_15_SHIFT)) + +#define MH_DEBUG_REG62_GET_TAG14_VA(mh_debug_reg62) \ + ((mh_debug_reg62 & MH_DEBUG_REG62_TAG14_VA_MASK) >> MH_DEBUG_REG62_TAG14_VA_SHIFT) +#define MH_DEBUG_REG62_GET_TAG_valid_q_14(mh_debug_reg62) \ + ((mh_debug_reg62 & MH_DEBUG_REG62_TAG_valid_q_14_MASK) >> MH_DEBUG_REG62_TAG_valid_q_14_SHIFT) +#define MH_DEBUG_REG62_GET_ALWAYS_ZERO(mh_debug_reg62) \ + ((mh_debug_reg62 & MH_DEBUG_REG62_ALWAYS_ZERO_MASK) >> MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG62_GET_TAG15_VA(mh_debug_reg62) \ + ((mh_debug_reg62 & MH_DEBUG_REG62_TAG15_VA_MASK) >> MH_DEBUG_REG62_TAG15_VA_SHIFT) +#define MH_DEBUG_REG62_GET_TAG_valid_q_15(mh_debug_reg62) \ + ((mh_debug_reg62 & MH_DEBUG_REG62_TAG_valid_q_15_MASK) >> MH_DEBUG_REG62_TAG_valid_q_15_SHIFT) + +#define MH_DEBUG_REG62_SET_TAG14_VA(mh_debug_reg62_reg, tag14_va) \ + mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG14_VA_MASK) | (tag14_va << MH_DEBUG_REG62_TAG14_VA_SHIFT) +#define MH_DEBUG_REG62_SET_TAG_valid_q_14(mh_debug_reg62_reg, tag_valid_q_14) \ + mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG_valid_q_14_MASK) | (tag_valid_q_14 << MH_DEBUG_REG62_TAG_valid_q_14_SHIFT) +#define MH_DEBUG_REG62_SET_ALWAYS_ZERO(mh_debug_reg62_reg, always_zero) \ + mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_ALWAYS_ZERO_MASK) | (always_zero << MH_DEBUG_REG62_ALWAYS_ZERO_SHIFT) +#define MH_DEBUG_REG62_SET_TAG15_VA(mh_debug_reg62_reg, tag15_va) \ + mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG15_VA_MASK) | (tag15_va << MH_DEBUG_REG62_TAG15_VA_SHIFT) +#define MH_DEBUG_REG62_SET_TAG_valid_q_15(mh_debug_reg62_reg, tag_valid_q_15) \ + mh_debug_reg62_reg = (mh_debug_reg62_reg & ~MH_DEBUG_REG62_TAG_valid_q_15_MASK) | (tag_valid_q_15 << MH_DEBUG_REG62_TAG_valid_q_15_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg62_t { + unsigned int tag14_va : MH_DEBUG_REG62_TAG14_VA_SIZE; + unsigned int tag_valid_q_14 : MH_DEBUG_REG62_TAG_valid_q_14_SIZE; + unsigned int always_zero : MH_DEBUG_REG62_ALWAYS_ZERO_SIZE; + unsigned int tag15_va : MH_DEBUG_REG62_TAG15_VA_SIZE; + unsigned int tag_valid_q_15 : MH_DEBUG_REG62_TAG_valid_q_15_SIZE; + unsigned int : 2; + } mh_debug_reg62_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg62_t { + unsigned int : 2; + unsigned int tag_valid_q_15 : MH_DEBUG_REG62_TAG_valid_q_15_SIZE; + unsigned int tag15_va : MH_DEBUG_REG62_TAG15_VA_SIZE; + unsigned int always_zero : MH_DEBUG_REG62_ALWAYS_ZERO_SIZE; + unsigned int tag_valid_q_14 : MH_DEBUG_REG62_TAG_valid_q_14_SIZE; + unsigned int tag14_va : MH_DEBUG_REG62_TAG14_VA_SIZE; + } mh_debug_reg62_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg62_t f; +} mh_debug_reg62_u; + + +/* + * MH_DEBUG_REG63 struct + */ + +#define MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE 32 + +#define MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT 0 + +#define MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK 0xffffffff + +#define MH_DEBUG_REG63_MASK \ + (MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) + +#define MH_DEBUG_REG63(mh_dbg_default) \ + ((mh_dbg_default << MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT)) + +#define MH_DEBUG_REG63_GET_MH_DBG_DEFAULT(mh_debug_reg63) \ + ((mh_debug_reg63 & MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) >> MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT) + +#define MH_DEBUG_REG63_SET_MH_DBG_DEFAULT(mh_debug_reg63_reg, mh_dbg_default) \ + mh_debug_reg63_reg = (mh_debug_reg63_reg & ~MH_DEBUG_REG63_MH_DBG_DEFAULT_MASK) | (mh_dbg_default << MH_DEBUG_REG63_MH_DBG_DEFAULT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_debug_reg63_t { + unsigned int mh_dbg_default : MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE; + } mh_debug_reg63_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_debug_reg63_t { + unsigned int mh_dbg_default : MH_DEBUG_REG63_MH_DBG_DEFAULT_SIZE; + } mh_debug_reg63_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_debug_reg63_t f; +} mh_debug_reg63_u; + + +/* + * MH_MMU_CONFIG struct + */ + +#define MH_MMU_CONFIG_MMU_ENABLE_SIZE 1 +#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE 1 +#define MH_MMU_CONFIG_RESERVED1_SIZE 2 +#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SIZE 2 + +#define MH_MMU_CONFIG_MMU_ENABLE_SHIFT 0 +#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT 1 +#define MH_MMU_CONFIG_RESERVED1_SHIFT 2 +#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT 4 +#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT 6 +#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT 8 +#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT 10 +#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT 12 +#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT 14 +#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT 16 +#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT 18 +#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT 20 +#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT 22 +#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT 24 + +#define MH_MMU_CONFIG_MMU_ENABLE_MASK 0x00000001 +#define MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK 0x00000002 +#define MH_MMU_CONFIG_RESERVED1_MASK 0x0000000c +#define MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK 0x00000030 +#define MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK 0x000000c0 +#define MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK 0x00000300 +#define MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK 0x00000c00 +#define MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK 0x00003000 +#define MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK 0x0000c000 +#define MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK 0x00030000 +#define MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK 0x000c0000 +#define MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK 0x00300000 +#define MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK 0x00c00000 +#define MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK 0x03000000 + +#define MH_MMU_CONFIG_MASK \ + (MH_MMU_CONFIG_MMU_ENABLE_MASK | \ + MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK | \ + MH_MMU_CONFIG_RESERVED1_MASK | \ + MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK | \ + MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK) + +#define MH_MMU_CONFIG(mmu_enable, split_mode_enable, reserved1, rb_w_clnt_behavior, cp_w_clnt_behavior, cp_r0_clnt_behavior, cp_r1_clnt_behavior, cp_r2_clnt_behavior, cp_r3_clnt_behavior, cp_r4_clnt_behavior, vgt_r0_clnt_behavior, vgt_r1_clnt_behavior, tc_r_clnt_behavior, pa_w_clnt_behavior) \ + ((mmu_enable << MH_MMU_CONFIG_MMU_ENABLE_SHIFT) | \ + (split_mode_enable << MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT) | \ + (reserved1 << MH_MMU_CONFIG_RESERVED1_SHIFT) | \ + (rb_w_clnt_behavior << MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT) | \ + (cp_w_clnt_behavior << MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r0_clnt_behavior << MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r1_clnt_behavior << MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r2_clnt_behavior << MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r3_clnt_behavior << MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT) | \ + (cp_r4_clnt_behavior << MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT) | \ + (vgt_r0_clnt_behavior << MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT) | \ + (vgt_r1_clnt_behavior << MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT) | \ + (tc_r_clnt_behavior << MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT) | \ + (pa_w_clnt_behavior << MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT)) + +#define MH_MMU_CONFIG_GET_MMU_ENABLE(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_MMU_ENABLE_MASK) >> MH_MMU_CONFIG_MMU_ENABLE_SHIFT) +#define MH_MMU_CONFIG_GET_SPLIT_MODE_ENABLE(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK) >> MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT) +#define MH_MMU_CONFIG_GET_RESERVED1(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_RESERVED1_MASK) >> MH_MMU_CONFIG_RESERVED1_SHIFT) +#define MH_MMU_CONFIG_GET_RB_W_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_W_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R0_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R1_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R2_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R3_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_CP_R4_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_VGT_R0_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_VGT_R1_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_TC_R_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_GET_PA_W_CLNT_BEHAVIOR(mh_mmu_config) \ + ((mh_mmu_config & MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK) >> MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT) + +#define MH_MMU_CONFIG_SET_MMU_ENABLE(mh_mmu_config_reg, mmu_enable) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_MMU_ENABLE_MASK) | (mmu_enable << MH_MMU_CONFIG_MMU_ENABLE_SHIFT) +#define MH_MMU_CONFIG_SET_SPLIT_MODE_ENABLE(mh_mmu_config_reg, split_mode_enable) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_SPLIT_MODE_ENABLE_MASK) | (split_mode_enable << MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SHIFT) +#define MH_MMU_CONFIG_SET_RESERVED1(mh_mmu_config_reg, reserved1) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_RESERVED1_MASK) | (reserved1 << MH_MMU_CONFIG_RESERVED1_SHIFT) +#define MH_MMU_CONFIG_SET_RB_W_CLNT_BEHAVIOR(mh_mmu_config_reg, rb_w_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_MASK) | (rb_w_clnt_behavior << MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_W_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_w_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_MASK) | (cp_w_clnt_behavior << MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R0_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r0_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_MASK) | (cp_r0_clnt_behavior << MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R1_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r1_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_MASK) | (cp_r1_clnt_behavior << MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R2_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r2_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_MASK) | (cp_r2_clnt_behavior << MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R3_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r3_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_MASK) | (cp_r3_clnt_behavior << MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_CP_R4_CLNT_BEHAVIOR(mh_mmu_config_reg, cp_r4_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_MASK) | (cp_r4_clnt_behavior << MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_VGT_R0_CLNT_BEHAVIOR(mh_mmu_config_reg, vgt_r0_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_MASK) | (vgt_r0_clnt_behavior << MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_VGT_R1_CLNT_BEHAVIOR(mh_mmu_config_reg, vgt_r1_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_MASK) | (vgt_r1_clnt_behavior << MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_TC_R_CLNT_BEHAVIOR(mh_mmu_config_reg, tc_r_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_MASK) | (tc_r_clnt_behavior << MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_CONFIG_SET_PA_W_CLNT_BEHAVIOR(mh_mmu_config_reg, pa_w_clnt_behavior) \ + mh_mmu_config_reg = (mh_mmu_config_reg & ~MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_MASK) | (pa_w_clnt_behavior << MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_config_t { + unsigned int mmu_enable : MH_MMU_CONFIG_MMU_ENABLE_SIZE; + unsigned int split_mode_enable : MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE; + unsigned int reserved1 : MH_MMU_CONFIG_RESERVED1_SIZE; + unsigned int rb_w_clnt_behavior : MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE; + unsigned int cp_w_clnt_behavior : MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r0_clnt_behavior : MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r1_clnt_behavior : MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r2_clnt_behavior : MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r3_clnt_behavior : MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r4_clnt_behavior : MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE; + unsigned int vgt_r0_clnt_behavior : MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE; + unsigned int vgt_r1_clnt_behavior : MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE; + unsigned int tc_r_clnt_behavior : MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE; + unsigned int pa_w_clnt_behavior : MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SIZE; + unsigned int : 6; + } mh_mmu_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_config_t { + unsigned int : 6; + unsigned int pa_w_clnt_behavior : MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR_SIZE; + unsigned int tc_r_clnt_behavior : MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR_SIZE; + unsigned int vgt_r1_clnt_behavior : MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR_SIZE; + unsigned int vgt_r0_clnt_behavior : MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r4_clnt_behavior : MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r3_clnt_behavior : MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r2_clnt_behavior : MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r1_clnt_behavior : MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR_SIZE; + unsigned int cp_r0_clnt_behavior : MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR_SIZE; + unsigned int cp_w_clnt_behavior : MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR_SIZE; + unsigned int rb_w_clnt_behavior : MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR_SIZE; + unsigned int reserved1 : MH_MMU_CONFIG_RESERVED1_SIZE; + unsigned int split_mode_enable : MH_MMU_CONFIG_SPLIT_MODE_ENABLE_SIZE; + unsigned int mmu_enable : MH_MMU_CONFIG_MMU_ENABLE_SIZE; + } mh_mmu_config_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_config_t f; +} mh_mmu_config_u; + + +/* + * MH_MMU_VA_RANGE struct + */ + +#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE 12 +#define MH_MMU_VA_RANGE_VA_BASE_SIZE 20 + +#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT 0 +#define MH_MMU_VA_RANGE_VA_BASE_SHIFT 12 + +#define MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK 0x00000fff +#define MH_MMU_VA_RANGE_VA_BASE_MASK 0xfffff000 + +#define MH_MMU_VA_RANGE_MASK \ + (MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK | \ + MH_MMU_VA_RANGE_VA_BASE_MASK) + +#define MH_MMU_VA_RANGE(num_64kb_regions, va_base) \ + ((num_64kb_regions << MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT) | \ + (va_base << MH_MMU_VA_RANGE_VA_BASE_SHIFT)) + +#define MH_MMU_VA_RANGE_GET_NUM_64KB_REGIONS(mh_mmu_va_range) \ + ((mh_mmu_va_range & MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK) >> MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT) +#define MH_MMU_VA_RANGE_GET_VA_BASE(mh_mmu_va_range) \ + ((mh_mmu_va_range & MH_MMU_VA_RANGE_VA_BASE_MASK) >> MH_MMU_VA_RANGE_VA_BASE_SHIFT) + +#define MH_MMU_VA_RANGE_SET_NUM_64KB_REGIONS(mh_mmu_va_range_reg, num_64kb_regions) \ + mh_mmu_va_range_reg = (mh_mmu_va_range_reg & ~MH_MMU_VA_RANGE_NUM_64KB_REGIONS_MASK) | (num_64kb_regions << MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SHIFT) +#define MH_MMU_VA_RANGE_SET_VA_BASE(mh_mmu_va_range_reg, va_base) \ + mh_mmu_va_range_reg = (mh_mmu_va_range_reg & ~MH_MMU_VA_RANGE_VA_BASE_MASK) | (va_base << MH_MMU_VA_RANGE_VA_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_va_range_t { + unsigned int num_64kb_regions : MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE; + unsigned int va_base : MH_MMU_VA_RANGE_VA_BASE_SIZE; + } mh_mmu_va_range_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_va_range_t { + unsigned int va_base : MH_MMU_VA_RANGE_VA_BASE_SIZE; + unsigned int num_64kb_regions : MH_MMU_VA_RANGE_NUM_64KB_REGIONS_SIZE; + } mh_mmu_va_range_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_va_range_t f; +} mh_mmu_va_range_u; + + +/* + * MH_MMU_PT_BASE struct + */ + +#define MH_MMU_PT_BASE_PT_BASE_SIZE 20 + +#define MH_MMU_PT_BASE_PT_BASE_SHIFT 12 + +#define MH_MMU_PT_BASE_PT_BASE_MASK 0xfffff000 + +#define MH_MMU_PT_BASE_MASK \ + (MH_MMU_PT_BASE_PT_BASE_MASK) + +#define MH_MMU_PT_BASE(pt_base) \ + ((pt_base << MH_MMU_PT_BASE_PT_BASE_SHIFT)) + +#define MH_MMU_PT_BASE_GET_PT_BASE(mh_mmu_pt_base) \ + ((mh_mmu_pt_base & MH_MMU_PT_BASE_PT_BASE_MASK) >> MH_MMU_PT_BASE_PT_BASE_SHIFT) + +#define MH_MMU_PT_BASE_SET_PT_BASE(mh_mmu_pt_base_reg, pt_base) \ + mh_mmu_pt_base_reg = (mh_mmu_pt_base_reg & ~MH_MMU_PT_BASE_PT_BASE_MASK) | (pt_base << MH_MMU_PT_BASE_PT_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_pt_base_t { + unsigned int : 12; + unsigned int pt_base : MH_MMU_PT_BASE_PT_BASE_SIZE; + } mh_mmu_pt_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_pt_base_t { + unsigned int pt_base : MH_MMU_PT_BASE_PT_BASE_SIZE; + unsigned int : 12; + } mh_mmu_pt_base_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_pt_base_t f; +} mh_mmu_pt_base_u; + + +/* + * MH_MMU_PAGE_FAULT struct + */ + +#define MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE 1 +#define MH_MMU_PAGE_FAULT_OP_TYPE_SIZE 1 +#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE 2 +#define MH_MMU_PAGE_FAULT_AXI_ID_SIZE 3 +#define MH_MMU_PAGE_FAULT_RESERVED1_SIZE 1 +#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE 1 +#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE 1 +#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE 1 +#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE 1 +#define MH_MMU_PAGE_FAULT_REQ_VA_SIZE 20 + +#define MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT 0 +#define MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT 1 +#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT 2 +#define MH_MMU_PAGE_FAULT_AXI_ID_SHIFT 4 +#define MH_MMU_PAGE_FAULT_RESERVED1_SHIFT 7 +#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT 8 +#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT 9 +#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT 10 +#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT 11 +#define MH_MMU_PAGE_FAULT_REQ_VA_SHIFT 12 + +#define MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK 0x00000001 +#define MH_MMU_PAGE_FAULT_OP_TYPE_MASK 0x00000002 +#define MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK 0x0000000c +#define MH_MMU_PAGE_FAULT_AXI_ID_MASK 0x00000070 +#define MH_MMU_PAGE_FAULT_RESERVED1_MASK 0x00000080 +#define MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK 0x00000100 +#define MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK 0x00000200 +#define MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK 0x00000400 +#define MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK 0x00000800 +#define MH_MMU_PAGE_FAULT_REQ_VA_MASK 0xfffff000 + +#define MH_MMU_PAGE_FAULT_MASK \ + (MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK | \ + MH_MMU_PAGE_FAULT_OP_TYPE_MASK | \ + MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK | \ + MH_MMU_PAGE_FAULT_AXI_ID_MASK | \ + MH_MMU_PAGE_FAULT_RESERVED1_MASK | \ + MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK | \ + MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK | \ + MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK | \ + MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK | \ + MH_MMU_PAGE_FAULT_REQ_VA_MASK) + +#define MH_MMU_PAGE_FAULT(page_fault, op_type, clnt_behavior, axi_id, reserved1, mpu_address_out_of_range, address_out_of_range, read_protection_error, write_protection_error, req_va) \ + ((page_fault << MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT) | \ + (op_type << MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT) | \ + (clnt_behavior << MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT) | \ + (axi_id << MH_MMU_PAGE_FAULT_AXI_ID_SHIFT) | \ + (reserved1 << MH_MMU_PAGE_FAULT_RESERVED1_SHIFT) | \ + (mpu_address_out_of_range << MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT) | \ + (address_out_of_range << MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT) | \ + (read_protection_error << MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT) | \ + (write_protection_error << MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT) | \ + (req_va << MH_MMU_PAGE_FAULT_REQ_VA_SHIFT)) + +#define MH_MMU_PAGE_FAULT_GET_PAGE_FAULT(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK) >> MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_OP_TYPE(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_OP_TYPE_MASK) >> MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_CLNT_BEHAVIOR(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK) >> MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_AXI_ID(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_AXI_ID_MASK) >> MH_MMU_PAGE_FAULT_AXI_ID_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_RESERVED1(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_RESERVED1_MASK) >> MH_MMU_PAGE_FAULT_RESERVED1_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_MPU_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK) >> MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK) >> MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_READ_PROTECTION_ERROR(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK) >> MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_WRITE_PROTECTION_ERROR(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK) >> MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT) +#define MH_MMU_PAGE_FAULT_GET_REQ_VA(mh_mmu_page_fault) \ + ((mh_mmu_page_fault & MH_MMU_PAGE_FAULT_REQ_VA_MASK) >> MH_MMU_PAGE_FAULT_REQ_VA_SHIFT) + +#define MH_MMU_PAGE_FAULT_SET_PAGE_FAULT(mh_mmu_page_fault_reg, page_fault) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_PAGE_FAULT_MASK) | (page_fault << MH_MMU_PAGE_FAULT_PAGE_FAULT_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_OP_TYPE(mh_mmu_page_fault_reg, op_type) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_OP_TYPE_MASK) | (op_type << MH_MMU_PAGE_FAULT_OP_TYPE_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_CLNT_BEHAVIOR(mh_mmu_page_fault_reg, clnt_behavior) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_MASK) | (clnt_behavior << MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_AXI_ID(mh_mmu_page_fault_reg, axi_id) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_AXI_ID_MASK) | (axi_id << MH_MMU_PAGE_FAULT_AXI_ID_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_RESERVED1(mh_mmu_page_fault_reg, reserved1) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_RESERVED1_MASK) | (reserved1 << MH_MMU_PAGE_FAULT_RESERVED1_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_MPU_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault_reg, mpu_address_out_of_range) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_MASK) | (mpu_address_out_of_range << MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_ADDRESS_OUT_OF_RANGE(mh_mmu_page_fault_reg, address_out_of_range) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_MASK) | (address_out_of_range << MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_READ_PROTECTION_ERROR(mh_mmu_page_fault_reg, read_protection_error) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_MASK) | (read_protection_error << MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_WRITE_PROTECTION_ERROR(mh_mmu_page_fault_reg, write_protection_error) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_MASK) | (write_protection_error << MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SHIFT) +#define MH_MMU_PAGE_FAULT_SET_REQ_VA(mh_mmu_page_fault_reg, req_va) \ + mh_mmu_page_fault_reg = (mh_mmu_page_fault_reg & ~MH_MMU_PAGE_FAULT_REQ_VA_MASK) | (req_va << MH_MMU_PAGE_FAULT_REQ_VA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_page_fault_t { + unsigned int page_fault : MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE; + unsigned int op_type : MH_MMU_PAGE_FAULT_OP_TYPE_SIZE; + unsigned int clnt_behavior : MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE; + unsigned int axi_id : MH_MMU_PAGE_FAULT_AXI_ID_SIZE; + unsigned int reserved1 : MH_MMU_PAGE_FAULT_RESERVED1_SIZE; + unsigned int mpu_address_out_of_range : MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE; + unsigned int address_out_of_range : MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE; + unsigned int read_protection_error : MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE; + unsigned int write_protection_error : MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE; + unsigned int req_va : MH_MMU_PAGE_FAULT_REQ_VA_SIZE; + } mh_mmu_page_fault_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_page_fault_t { + unsigned int req_va : MH_MMU_PAGE_FAULT_REQ_VA_SIZE; + unsigned int write_protection_error : MH_MMU_PAGE_FAULT_WRITE_PROTECTION_ERROR_SIZE; + unsigned int read_protection_error : MH_MMU_PAGE_FAULT_READ_PROTECTION_ERROR_SIZE; + unsigned int address_out_of_range : MH_MMU_PAGE_FAULT_ADDRESS_OUT_OF_RANGE_SIZE; + unsigned int mpu_address_out_of_range : MH_MMU_PAGE_FAULT_MPU_ADDRESS_OUT_OF_RANGE_SIZE; + unsigned int reserved1 : MH_MMU_PAGE_FAULT_RESERVED1_SIZE; + unsigned int axi_id : MH_MMU_PAGE_FAULT_AXI_ID_SIZE; + unsigned int clnt_behavior : MH_MMU_PAGE_FAULT_CLNT_BEHAVIOR_SIZE; + unsigned int op_type : MH_MMU_PAGE_FAULT_OP_TYPE_SIZE; + unsigned int page_fault : MH_MMU_PAGE_FAULT_PAGE_FAULT_SIZE; + } mh_mmu_page_fault_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_page_fault_t f; +} mh_mmu_page_fault_u; + + +/* + * MH_MMU_TRAN_ERROR struct + */ + +#define MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE 27 + +#define MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT 5 + +#define MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK 0xffffffe0 + +#define MH_MMU_TRAN_ERROR_MASK \ + (MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) + +#define MH_MMU_TRAN_ERROR(tran_error) \ + ((tran_error << MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT)) + +#define MH_MMU_TRAN_ERROR_GET_TRAN_ERROR(mh_mmu_tran_error) \ + ((mh_mmu_tran_error & MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) >> MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT) + +#define MH_MMU_TRAN_ERROR_SET_TRAN_ERROR(mh_mmu_tran_error_reg, tran_error) \ + mh_mmu_tran_error_reg = (mh_mmu_tran_error_reg & ~MH_MMU_TRAN_ERROR_TRAN_ERROR_MASK) | (tran_error << MH_MMU_TRAN_ERROR_TRAN_ERROR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_tran_error_t { + unsigned int : 5; + unsigned int tran_error : MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE; + } mh_mmu_tran_error_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_tran_error_t { + unsigned int tran_error : MH_MMU_TRAN_ERROR_TRAN_ERROR_SIZE; + unsigned int : 5; + } mh_mmu_tran_error_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_tran_error_t f; +} mh_mmu_tran_error_u; + + +/* + * MH_MMU_INVALIDATE struct + */ + +#define MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE 1 +#define MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE 1 + +#define MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT 0 +#define MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT 1 + +#define MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK 0x00000001 +#define MH_MMU_INVALIDATE_INVALIDATE_TC_MASK 0x00000002 + +#define MH_MMU_INVALIDATE_MASK \ + (MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK | \ + MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) + +#define MH_MMU_INVALIDATE(invalidate_all, invalidate_tc) \ + ((invalidate_all << MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) | \ + (invalidate_tc << MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT)) + +#define MH_MMU_INVALIDATE_GET_INVALIDATE_ALL(mh_mmu_invalidate) \ + ((mh_mmu_invalidate & MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) >> MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) +#define MH_MMU_INVALIDATE_GET_INVALIDATE_TC(mh_mmu_invalidate) \ + ((mh_mmu_invalidate & MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) >> MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT) + +#define MH_MMU_INVALIDATE_SET_INVALIDATE_ALL(mh_mmu_invalidate_reg, invalidate_all) \ + mh_mmu_invalidate_reg = (mh_mmu_invalidate_reg & ~MH_MMU_INVALIDATE_INVALIDATE_ALL_MASK) | (invalidate_all << MH_MMU_INVALIDATE_INVALIDATE_ALL_SHIFT) +#define MH_MMU_INVALIDATE_SET_INVALIDATE_TC(mh_mmu_invalidate_reg, invalidate_tc) \ + mh_mmu_invalidate_reg = (mh_mmu_invalidate_reg & ~MH_MMU_INVALIDATE_INVALIDATE_TC_MASK) | (invalidate_tc << MH_MMU_INVALIDATE_INVALIDATE_TC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_invalidate_t { + unsigned int invalidate_all : MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE; + unsigned int invalidate_tc : MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE; + unsigned int : 30; + } mh_mmu_invalidate_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_invalidate_t { + unsigned int : 30; + unsigned int invalidate_tc : MH_MMU_INVALIDATE_INVALIDATE_TC_SIZE; + unsigned int invalidate_all : MH_MMU_INVALIDATE_INVALIDATE_ALL_SIZE; + } mh_mmu_invalidate_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_invalidate_t f; +} mh_mmu_invalidate_u; + + +/* + * MH_MMU_MPU_BASE struct + */ + +#define MH_MMU_MPU_BASE_MPU_BASE_SIZE 20 + +#define MH_MMU_MPU_BASE_MPU_BASE_SHIFT 12 + +#define MH_MMU_MPU_BASE_MPU_BASE_MASK 0xfffff000 + +#define MH_MMU_MPU_BASE_MASK \ + (MH_MMU_MPU_BASE_MPU_BASE_MASK) + +#define MH_MMU_MPU_BASE(mpu_base) \ + ((mpu_base << MH_MMU_MPU_BASE_MPU_BASE_SHIFT)) + +#define MH_MMU_MPU_BASE_GET_MPU_BASE(mh_mmu_mpu_base) \ + ((mh_mmu_mpu_base & MH_MMU_MPU_BASE_MPU_BASE_MASK) >> MH_MMU_MPU_BASE_MPU_BASE_SHIFT) + +#define MH_MMU_MPU_BASE_SET_MPU_BASE(mh_mmu_mpu_base_reg, mpu_base) \ + mh_mmu_mpu_base_reg = (mh_mmu_mpu_base_reg & ~MH_MMU_MPU_BASE_MPU_BASE_MASK) | (mpu_base << MH_MMU_MPU_BASE_MPU_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_mpu_base_t { + unsigned int : 12; + unsigned int mpu_base : MH_MMU_MPU_BASE_MPU_BASE_SIZE; + } mh_mmu_mpu_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_mpu_base_t { + unsigned int mpu_base : MH_MMU_MPU_BASE_MPU_BASE_SIZE; + unsigned int : 12; + } mh_mmu_mpu_base_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_mpu_base_t f; +} mh_mmu_mpu_base_u; + + +/* + * MH_MMU_MPU_END struct + */ + +#define MH_MMU_MPU_END_MPU_END_SIZE 20 + +#define MH_MMU_MPU_END_MPU_END_SHIFT 12 + +#define MH_MMU_MPU_END_MPU_END_MASK 0xfffff000 + +#define MH_MMU_MPU_END_MASK \ + (MH_MMU_MPU_END_MPU_END_MASK) + +#define MH_MMU_MPU_END(mpu_end) \ + ((mpu_end << MH_MMU_MPU_END_MPU_END_SHIFT)) + +#define MH_MMU_MPU_END_GET_MPU_END(mh_mmu_mpu_end) \ + ((mh_mmu_mpu_end & MH_MMU_MPU_END_MPU_END_MASK) >> MH_MMU_MPU_END_MPU_END_SHIFT) + +#define MH_MMU_MPU_END_SET_MPU_END(mh_mmu_mpu_end_reg, mpu_end) \ + mh_mmu_mpu_end_reg = (mh_mmu_mpu_end_reg & ~MH_MMU_MPU_END_MPU_END_MASK) | (mpu_end << MH_MMU_MPU_END_MPU_END_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _mh_mmu_mpu_end_t { + unsigned int : 12; + unsigned int mpu_end : MH_MMU_MPU_END_MPU_END_SIZE; + } mh_mmu_mpu_end_t; + +#else // !BIGENDIAN_OS + + typedef struct _mh_mmu_mpu_end_t { + unsigned int mpu_end : MH_MMU_MPU_END_MPU_END_SIZE; + unsigned int : 12; + } mh_mmu_mpu_end_t; + +#endif + +typedef union { + unsigned int val : 32; + mh_mmu_mpu_end_t f; +} mh_mmu_mpu_end_u; + + +#endif + + +#if !defined (_PA_FIDDLE_H) +#define _PA_FIDDLE_H + +/***************************************************************************************************************** + * + * pa_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * PA_CL_VPORT_XSCALE struct + */ + +#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE 32 + +#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT 0 + +#define PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK 0xffffffff + +#define PA_CL_VPORT_XSCALE_MASK \ + (PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) + +#define PA_CL_VPORT_XSCALE(vport_xscale) \ + ((vport_xscale << PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT)) + +#define PA_CL_VPORT_XSCALE_GET_VPORT_XSCALE(pa_cl_vport_xscale) \ + ((pa_cl_vport_xscale & PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) >> PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT) + +#define PA_CL_VPORT_XSCALE_SET_VPORT_XSCALE(pa_cl_vport_xscale_reg, vport_xscale) \ + pa_cl_vport_xscale_reg = (pa_cl_vport_xscale_reg & ~PA_CL_VPORT_XSCALE_VPORT_XSCALE_MASK) | (vport_xscale << PA_CL_VPORT_XSCALE_VPORT_XSCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_xscale_t { + unsigned int vport_xscale : PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE; + } pa_cl_vport_xscale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_xscale_t { + unsigned int vport_xscale : PA_CL_VPORT_XSCALE_VPORT_XSCALE_SIZE; + } pa_cl_vport_xscale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_xscale_t f; +} pa_cl_vport_xscale_u; + + +/* + * PA_CL_VPORT_XOFFSET struct + */ + +#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE 32 + +#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT 0 + +#define PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK 0xffffffff + +#define PA_CL_VPORT_XOFFSET_MASK \ + (PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) + +#define PA_CL_VPORT_XOFFSET(vport_xoffset) \ + ((vport_xoffset << PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT)) + +#define PA_CL_VPORT_XOFFSET_GET_VPORT_XOFFSET(pa_cl_vport_xoffset) \ + ((pa_cl_vport_xoffset & PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) >> PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT) + +#define PA_CL_VPORT_XOFFSET_SET_VPORT_XOFFSET(pa_cl_vport_xoffset_reg, vport_xoffset) \ + pa_cl_vport_xoffset_reg = (pa_cl_vport_xoffset_reg & ~PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_MASK) | (vport_xoffset << PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_xoffset_t { + unsigned int vport_xoffset : PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE; + } pa_cl_vport_xoffset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_xoffset_t { + unsigned int vport_xoffset : PA_CL_VPORT_XOFFSET_VPORT_XOFFSET_SIZE; + } pa_cl_vport_xoffset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_xoffset_t f; +} pa_cl_vport_xoffset_u; + + +/* + * PA_CL_VPORT_YSCALE struct + */ + +#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE 32 + +#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT 0 + +#define PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK 0xffffffff + +#define PA_CL_VPORT_YSCALE_MASK \ + (PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) + +#define PA_CL_VPORT_YSCALE(vport_yscale) \ + ((vport_yscale << PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT)) + +#define PA_CL_VPORT_YSCALE_GET_VPORT_YSCALE(pa_cl_vport_yscale) \ + ((pa_cl_vport_yscale & PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) >> PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT) + +#define PA_CL_VPORT_YSCALE_SET_VPORT_YSCALE(pa_cl_vport_yscale_reg, vport_yscale) \ + pa_cl_vport_yscale_reg = (pa_cl_vport_yscale_reg & ~PA_CL_VPORT_YSCALE_VPORT_YSCALE_MASK) | (vport_yscale << PA_CL_VPORT_YSCALE_VPORT_YSCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_yscale_t { + unsigned int vport_yscale : PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE; + } pa_cl_vport_yscale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_yscale_t { + unsigned int vport_yscale : PA_CL_VPORT_YSCALE_VPORT_YSCALE_SIZE; + } pa_cl_vport_yscale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_yscale_t f; +} pa_cl_vport_yscale_u; + + +/* + * PA_CL_VPORT_YOFFSET struct + */ + +#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE 32 + +#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT 0 + +#define PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK 0xffffffff + +#define PA_CL_VPORT_YOFFSET_MASK \ + (PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) + +#define PA_CL_VPORT_YOFFSET(vport_yoffset) \ + ((vport_yoffset << PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT)) + +#define PA_CL_VPORT_YOFFSET_GET_VPORT_YOFFSET(pa_cl_vport_yoffset) \ + ((pa_cl_vport_yoffset & PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) >> PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT) + +#define PA_CL_VPORT_YOFFSET_SET_VPORT_YOFFSET(pa_cl_vport_yoffset_reg, vport_yoffset) \ + pa_cl_vport_yoffset_reg = (pa_cl_vport_yoffset_reg & ~PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_MASK) | (vport_yoffset << PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_yoffset_t { + unsigned int vport_yoffset : PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE; + } pa_cl_vport_yoffset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_yoffset_t { + unsigned int vport_yoffset : PA_CL_VPORT_YOFFSET_VPORT_YOFFSET_SIZE; + } pa_cl_vport_yoffset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_yoffset_t f; +} pa_cl_vport_yoffset_u; + + +/* + * PA_CL_VPORT_ZSCALE struct + */ + +#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE 32 + +#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT 0 + +#define PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK 0xffffffff + +#define PA_CL_VPORT_ZSCALE_MASK \ + (PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) + +#define PA_CL_VPORT_ZSCALE(vport_zscale) \ + ((vport_zscale << PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT)) + +#define PA_CL_VPORT_ZSCALE_GET_VPORT_ZSCALE(pa_cl_vport_zscale) \ + ((pa_cl_vport_zscale & PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) >> PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT) + +#define PA_CL_VPORT_ZSCALE_SET_VPORT_ZSCALE(pa_cl_vport_zscale_reg, vport_zscale) \ + pa_cl_vport_zscale_reg = (pa_cl_vport_zscale_reg & ~PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_MASK) | (vport_zscale << PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_zscale_t { + unsigned int vport_zscale : PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE; + } pa_cl_vport_zscale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_zscale_t { + unsigned int vport_zscale : PA_CL_VPORT_ZSCALE_VPORT_ZSCALE_SIZE; + } pa_cl_vport_zscale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_zscale_t f; +} pa_cl_vport_zscale_u; + + +/* + * PA_CL_VPORT_ZOFFSET struct + */ + +#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE 32 + +#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT 0 + +#define PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK 0xffffffff + +#define PA_CL_VPORT_ZOFFSET_MASK \ + (PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) + +#define PA_CL_VPORT_ZOFFSET(vport_zoffset) \ + ((vport_zoffset << PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT)) + +#define PA_CL_VPORT_ZOFFSET_GET_VPORT_ZOFFSET(pa_cl_vport_zoffset) \ + ((pa_cl_vport_zoffset & PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) >> PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT) + +#define PA_CL_VPORT_ZOFFSET_SET_VPORT_ZOFFSET(pa_cl_vport_zoffset_reg, vport_zoffset) \ + pa_cl_vport_zoffset_reg = (pa_cl_vport_zoffset_reg & ~PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_MASK) | (vport_zoffset << PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vport_zoffset_t { + unsigned int vport_zoffset : PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE; + } pa_cl_vport_zoffset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vport_zoffset_t { + unsigned int vport_zoffset : PA_CL_VPORT_ZOFFSET_VPORT_ZOFFSET_SIZE; + } pa_cl_vport_zoffset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vport_zoffset_t f; +} pa_cl_vport_zoffset_u; + + +/* + * PA_CL_VTE_CNTL struct + */ + +#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE 1 +#define PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE 1 +#define PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE 1 +#define PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE 1 +#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE 1 + +#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT 0 +#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT 1 +#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT 2 +#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT 3 +#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT 4 +#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT 5 +#define PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT 8 +#define PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT 9 +#define PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT 10 +#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT 11 + +#define PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK 0x00000001 +#define PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK 0x00000002 +#define PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK 0x00000004 +#define PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK 0x00000008 +#define PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK 0x00000010 +#define PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK 0x00000020 +#define PA_CL_VTE_CNTL_VTX_XY_FMT_MASK 0x00000100 +#define PA_CL_VTE_CNTL_VTX_Z_FMT_MASK 0x00000200 +#define PA_CL_VTE_CNTL_VTX_W0_FMT_MASK 0x00000400 +#define PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK 0x00000800 + +#define PA_CL_VTE_CNTL_MASK \ + (PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK | \ + PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK | \ + PA_CL_VTE_CNTL_VTX_XY_FMT_MASK | \ + PA_CL_VTE_CNTL_VTX_Z_FMT_MASK | \ + PA_CL_VTE_CNTL_VTX_W0_FMT_MASK | \ + PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) + +#define PA_CL_VTE_CNTL(vport_x_scale_ena, vport_x_offset_ena, vport_y_scale_ena, vport_y_offset_ena, vport_z_scale_ena, vport_z_offset_ena, vtx_xy_fmt, vtx_z_fmt, vtx_w0_fmt, perfcounter_ref) \ + ((vport_x_scale_ena << PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT) | \ + (vport_x_offset_ena << PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT) | \ + (vport_y_scale_ena << PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT) | \ + (vport_y_offset_ena << PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT) | \ + (vport_z_scale_ena << PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT) | \ + (vport_z_offset_ena << PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT) | \ + (vtx_xy_fmt << PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT) | \ + (vtx_z_fmt << PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT) | \ + (vtx_w0_fmt << PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT) | \ + (perfcounter_ref << PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT)) + +#define PA_CL_VTE_CNTL_GET_VPORT_X_SCALE_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_X_OFFSET_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_Y_SCALE_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_Y_OFFSET_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_Z_SCALE_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VPORT_Z_OFFSET_ENA(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK) >> PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_GET_VTX_XY_FMT(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_XY_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT) +#define PA_CL_VTE_CNTL_GET_VTX_Z_FMT(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_Z_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT) +#define PA_CL_VTE_CNTL_GET_VTX_W0_FMT(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_VTX_W0_FMT_MASK) >> PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT) +#define PA_CL_VTE_CNTL_GET_PERFCOUNTER_REF(pa_cl_vte_cntl) \ + ((pa_cl_vte_cntl & PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) >> PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT) + +#define PA_CL_VTE_CNTL_SET_VPORT_X_SCALE_ENA(pa_cl_vte_cntl_reg, vport_x_scale_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_MASK) | (vport_x_scale_ena << PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_X_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_x_offset_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_MASK) | (vport_x_offset_ena << PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_Y_SCALE_ENA(pa_cl_vte_cntl_reg, vport_y_scale_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_MASK) | (vport_y_scale_ena << PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_Y_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_y_offset_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_MASK) | (vport_y_offset_ena << PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_Z_SCALE_ENA(pa_cl_vte_cntl_reg, vport_z_scale_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_MASK) | (vport_z_scale_ena << PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VPORT_Z_OFFSET_ENA(pa_cl_vte_cntl_reg, vport_z_offset_ena) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_MASK) | (vport_z_offset_ena << PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SHIFT) +#define PA_CL_VTE_CNTL_SET_VTX_XY_FMT(pa_cl_vte_cntl_reg, vtx_xy_fmt) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_XY_FMT_MASK) | (vtx_xy_fmt << PA_CL_VTE_CNTL_VTX_XY_FMT_SHIFT) +#define PA_CL_VTE_CNTL_SET_VTX_Z_FMT(pa_cl_vte_cntl_reg, vtx_z_fmt) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_Z_FMT_MASK) | (vtx_z_fmt << PA_CL_VTE_CNTL_VTX_Z_FMT_SHIFT) +#define PA_CL_VTE_CNTL_SET_VTX_W0_FMT(pa_cl_vte_cntl_reg, vtx_w0_fmt) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_VTX_W0_FMT_MASK) | (vtx_w0_fmt << PA_CL_VTE_CNTL_VTX_W0_FMT_SHIFT) +#define PA_CL_VTE_CNTL_SET_PERFCOUNTER_REF(pa_cl_vte_cntl_reg, perfcounter_ref) \ + pa_cl_vte_cntl_reg = (pa_cl_vte_cntl_reg & ~PA_CL_VTE_CNTL_PERFCOUNTER_REF_MASK) | (perfcounter_ref << PA_CL_VTE_CNTL_PERFCOUNTER_REF_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_vte_cntl_t { + unsigned int vport_x_scale_ena : PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE; + unsigned int vport_x_offset_ena : PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE; + unsigned int vport_y_scale_ena : PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE; + unsigned int vport_y_offset_ena : PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE; + unsigned int vport_z_scale_ena : PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE; + unsigned int vport_z_offset_ena : PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE; + unsigned int : 2; + unsigned int vtx_xy_fmt : PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE; + unsigned int vtx_z_fmt : PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE; + unsigned int vtx_w0_fmt : PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE; + unsigned int perfcounter_ref : PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE; + unsigned int : 20; + } pa_cl_vte_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_vte_cntl_t { + unsigned int : 20; + unsigned int perfcounter_ref : PA_CL_VTE_CNTL_PERFCOUNTER_REF_SIZE; + unsigned int vtx_w0_fmt : PA_CL_VTE_CNTL_VTX_W0_FMT_SIZE; + unsigned int vtx_z_fmt : PA_CL_VTE_CNTL_VTX_Z_FMT_SIZE; + unsigned int vtx_xy_fmt : PA_CL_VTE_CNTL_VTX_XY_FMT_SIZE; + unsigned int : 2; + unsigned int vport_z_offset_ena : PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA_SIZE; + unsigned int vport_z_scale_ena : PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA_SIZE; + unsigned int vport_y_offset_ena : PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA_SIZE; + unsigned int vport_y_scale_ena : PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA_SIZE; + unsigned int vport_x_offset_ena : PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA_SIZE; + unsigned int vport_x_scale_ena : PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA_SIZE; + } pa_cl_vte_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_vte_cntl_t f; +} pa_cl_vte_cntl_u; + + +/* + * PA_CL_CLIP_CNTL struct + */ + +#define PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE 1 +#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE 1 +#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE 1 +#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE 1 +#define PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE 1 +#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE 1 +#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE 1 +#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE 1 + +#define PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT 16 +#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT 18 +#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT 19 +#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT 20 +#define PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT 21 +#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT 22 +#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT 23 +#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT 24 + +#define PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK 0x00010000 +#define PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000 +#define PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK 0x00080000 +#define PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK 0x00100000 +#define PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK 0x00200000 +#define PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK 0x00400000 +#define PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK 0x00800000 +#define PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK 0x01000000 + +#define PA_CL_CLIP_CNTL_MASK \ + (PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK | \ + PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK | \ + PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK | \ + PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK | \ + PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK | \ + PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK | \ + PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK | \ + PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) + +#define PA_CL_CLIP_CNTL(clip_disable, boundary_edge_flag_ena, dx_clip_space_def, dis_clip_err_detect, vtx_kill_or, xy_nan_retain, z_nan_retain, w_nan_retain) \ + ((clip_disable << PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT) | \ + (boundary_edge_flag_ena << PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT) | \ + (dx_clip_space_def << PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT) | \ + (dis_clip_err_detect << PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT) | \ + (vtx_kill_or << PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT) | \ + (xy_nan_retain << PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT) | \ + (z_nan_retain << PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT) | \ + (w_nan_retain << PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT)) + +#define PA_CL_CLIP_CNTL_GET_CLIP_DISABLE(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK) >> PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT) +#define PA_CL_CLIP_CNTL_GET_BOUNDARY_EDGE_FLAG_ENA(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK) >> PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT) +#define PA_CL_CLIP_CNTL_GET_DX_CLIP_SPACE_DEF(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK) >> PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT) +#define PA_CL_CLIP_CNTL_GET_DIS_CLIP_ERR_DETECT(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK) >> PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT) +#define PA_CL_CLIP_CNTL_GET_VTX_KILL_OR(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK) >> PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT) +#define PA_CL_CLIP_CNTL_GET_XY_NAN_RETAIN(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT) +#define PA_CL_CLIP_CNTL_GET_Z_NAN_RETAIN(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT) +#define PA_CL_CLIP_CNTL_GET_W_NAN_RETAIN(pa_cl_clip_cntl) \ + ((pa_cl_clip_cntl & PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) >> PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT) + +#define PA_CL_CLIP_CNTL_SET_CLIP_DISABLE(pa_cl_clip_cntl_reg, clip_disable) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK) | (clip_disable << PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT) +#define PA_CL_CLIP_CNTL_SET_BOUNDARY_EDGE_FLAG_ENA(pa_cl_clip_cntl_reg, boundary_edge_flag_ena) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK) | (boundary_edge_flag_ena << PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT) +#define PA_CL_CLIP_CNTL_SET_DX_CLIP_SPACE_DEF(pa_cl_clip_cntl_reg, dx_clip_space_def) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK) | (dx_clip_space_def << PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT) +#define PA_CL_CLIP_CNTL_SET_DIS_CLIP_ERR_DETECT(pa_cl_clip_cntl_reg, dis_clip_err_detect) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK) | (dis_clip_err_detect << PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT) +#define PA_CL_CLIP_CNTL_SET_VTX_KILL_OR(pa_cl_clip_cntl_reg, vtx_kill_or) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK) | (vtx_kill_or << PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT) +#define PA_CL_CLIP_CNTL_SET_XY_NAN_RETAIN(pa_cl_clip_cntl_reg, xy_nan_retain) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_XY_NAN_RETAIN_MASK) | (xy_nan_retain << PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SHIFT) +#define PA_CL_CLIP_CNTL_SET_Z_NAN_RETAIN(pa_cl_clip_cntl_reg, z_nan_retain) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_Z_NAN_RETAIN_MASK) | (z_nan_retain << PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SHIFT) +#define PA_CL_CLIP_CNTL_SET_W_NAN_RETAIN(pa_cl_clip_cntl_reg, w_nan_retain) \ + pa_cl_clip_cntl_reg = (pa_cl_clip_cntl_reg & ~PA_CL_CLIP_CNTL_W_NAN_RETAIN_MASK) | (w_nan_retain << PA_CL_CLIP_CNTL_W_NAN_RETAIN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_clip_cntl_t { + unsigned int : 16; + unsigned int clip_disable : PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE; + unsigned int : 1; + unsigned int boundary_edge_flag_ena : PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE; + unsigned int dx_clip_space_def : PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE; + unsigned int dis_clip_err_detect : PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE; + unsigned int vtx_kill_or : PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE; + unsigned int xy_nan_retain : PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE; + unsigned int z_nan_retain : PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE; + unsigned int w_nan_retain : PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE; + unsigned int : 7; + } pa_cl_clip_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_clip_cntl_t { + unsigned int : 7; + unsigned int w_nan_retain : PA_CL_CLIP_CNTL_W_NAN_RETAIN_SIZE; + unsigned int z_nan_retain : PA_CL_CLIP_CNTL_Z_NAN_RETAIN_SIZE; + unsigned int xy_nan_retain : PA_CL_CLIP_CNTL_XY_NAN_RETAIN_SIZE; + unsigned int vtx_kill_or : PA_CL_CLIP_CNTL_VTX_KILL_OR_SIZE; + unsigned int dis_clip_err_detect : PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SIZE; + unsigned int dx_clip_space_def : PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SIZE; + unsigned int boundary_edge_flag_ena : PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SIZE; + unsigned int : 1; + unsigned int clip_disable : PA_CL_CLIP_CNTL_CLIP_DISABLE_SIZE; + unsigned int : 16; + } pa_cl_clip_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_clip_cntl_t f; +} pa_cl_clip_cntl_u; + + +/* + * PA_CL_GB_VERT_CLIP_ADJ struct + */ + +#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE 32 + +#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT 0 + +#define PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK 0xffffffff + +#define PA_CL_GB_VERT_CLIP_ADJ_MASK \ + (PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) + +#define PA_CL_GB_VERT_CLIP_ADJ(data_register) \ + ((data_register << PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT)) + +#define PA_CL_GB_VERT_CLIP_ADJ_GET_DATA_REGISTER(pa_cl_gb_vert_clip_adj) \ + ((pa_cl_gb_vert_clip_adj & PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT) + +#define PA_CL_GB_VERT_CLIP_ADJ_SET_DATA_REGISTER(pa_cl_gb_vert_clip_adj_reg, data_register) \ + pa_cl_gb_vert_clip_adj_reg = (pa_cl_gb_vert_clip_adj_reg & ~PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_gb_vert_clip_adj_t { + unsigned int data_register : PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_vert_clip_adj_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_gb_vert_clip_adj_t { + unsigned int data_register : PA_CL_GB_VERT_CLIP_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_vert_clip_adj_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_gb_vert_clip_adj_t f; +} pa_cl_gb_vert_clip_adj_u; + + +/* + * PA_CL_GB_VERT_DISC_ADJ struct + */ + +#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE 32 + +#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT 0 + +#define PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK 0xffffffff + +#define PA_CL_GB_VERT_DISC_ADJ_MASK \ + (PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) + +#define PA_CL_GB_VERT_DISC_ADJ(data_register) \ + ((data_register << PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT)) + +#define PA_CL_GB_VERT_DISC_ADJ_GET_DATA_REGISTER(pa_cl_gb_vert_disc_adj) \ + ((pa_cl_gb_vert_disc_adj & PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT) + +#define PA_CL_GB_VERT_DISC_ADJ_SET_DATA_REGISTER(pa_cl_gb_vert_disc_adj_reg, data_register) \ + pa_cl_gb_vert_disc_adj_reg = (pa_cl_gb_vert_disc_adj_reg & ~PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_gb_vert_disc_adj_t { + unsigned int data_register : PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_vert_disc_adj_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_gb_vert_disc_adj_t { + unsigned int data_register : PA_CL_GB_VERT_DISC_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_vert_disc_adj_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_gb_vert_disc_adj_t f; +} pa_cl_gb_vert_disc_adj_u; + + +/* + * PA_CL_GB_HORZ_CLIP_ADJ struct + */ + +#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE 32 + +#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT 0 + +#define PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK 0xffffffff + +#define PA_CL_GB_HORZ_CLIP_ADJ_MASK \ + (PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) + +#define PA_CL_GB_HORZ_CLIP_ADJ(data_register) \ + ((data_register << PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT)) + +#define PA_CL_GB_HORZ_CLIP_ADJ_GET_DATA_REGISTER(pa_cl_gb_horz_clip_adj) \ + ((pa_cl_gb_horz_clip_adj & PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT) + +#define PA_CL_GB_HORZ_CLIP_ADJ_SET_DATA_REGISTER(pa_cl_gb_horz_clip_adj_reg, data_register) \ + pa_cl_gb_horz_clip_adj_reg = (pa_cl_gb_horz_clip_adj_reg & ~PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_gb_horz_clip_adj_t { + unsigned int data_register : PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_horz_clip_adj_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_gb_horz_clip_adj_t { + unsigned int data_register : PA_CL_GB_HORZ_CLIP_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_horz_clip_adj_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_gb_horz_clip_adj_t f; +} pa_cl_gb_horz_clip_adj_u; + + +/* + * PA_CL_GB_HORZ_DISC_ADJ struct + */ + +#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE 32 + +#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT 0 + +#define PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK 0xffffffff + +#define PA_CL_GB_HORZ_DISC_ADJ_MASK \ + (PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) + +#define PA_CL_GB_HORZ_DISC_ADJ(data_register) \ + ((data_register << PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT)) + +#define PA_CL_GB_HORZ_DISC_ADJ_GET_DATA_REGISTER(pa_cl_gb_horz_disc_adj) \ + ((pa_cl_gb_horz_disc_adj & PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) >> PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT) + +#define PA_CL_GB_HORZ_DISC_ADJ_SET_DATA_REGISTER(pa_cl_gb_horz_disc_adj_reg, data_register) \ + pa_cl_gb_horz_disc_adj_reg = (pa_cl_gb_horz_disc_adj_reg & ~PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_MASK) | (data_register << PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_gb_horz_disc_adj_t { + unsigned int data_register : PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_horz_disc_adj_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_gb_horz_disc_adj_t { + unsigned int data_register : PA_CL_GB_HORZ_DISC_ADJ_DATA_REGISTER_SIZE; + } pa_cl_gb_horz_disc_adj_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_gb_horz_disc_adj_t f; +} pa_cl_gb_horz_disc_adj_u; + + +/* + * PA_CL_ENHANCE struct + */ + +#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE 1 +#define PA_CL_ENHANCE_ECO_SPARE3_SIZE 1 +#define PA_CL_ENHANCE_ECO_SPARE2_SIZE 1 +#define PA_CL_ENHANCE_ECO_SPARE1_SIZE 1 +#define PA_CL_ENHANCE_ECO_SPARE0_SIZE 1 + +#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT 0 +#define PA_CL_ENHANCE_ECO_SPARE3_SHIFT 28 +#define PA_CL_ENHANCE_ECO_SPARE2_SHIFT 29 +#define PA_CL_ENHANCE_ECO_SPARE1_SHIFT 30 +#define PA_CL_ENHANCE_ECO_SPARE0_SHIFT 31 + +#define PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK 0x00000001 +#define PA_CL_ENHANCE_ECO_SPARE3_MASK 0x10000000 +#define PA_CL_ENHANCE_ECO_SPARE2_MASK 0x20000000 +#define PA_CL_ENHANCE_ECO_SPARE1_MASK 0x40000000 +#define PA_CL_ENHANCE_ECO_SPARE0_MASK 0x80000000 + +#define PA_CL_ENHANCE_MASK \ + (PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK | \ + PA_CL_ENHANCE_ECO_SPARE3_MASK | \ + PA_CL_ENHANCE_ECO_SPARE2_MASK | \ + PA_CL_ENHANCE_ECO_SPARE1_MASK | \ + PA_CL_ENHANCE_ECO_SPARE0_MASK) + +#define PA_CL_ENHANCE(clip_vtx_reorder_ena, eco_spare3, eco_spare2, eco_spare1, eco_spare0) \ + ((clip_vtx_reorder_ena << PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT) | \ + (eco_spare3 << PA_CL_ENHANCE_ECO_SPARE3_SHIFT) | \ + (eco_spare2 << PA_CL_ENHANCE_ECO_SPARE2_SHIFT) | \ + (eco_spare1 << PA_CL_ENHANCE_ECO_SPARE1_SHIFT) | \ + (eco_spare0 << PA_CL_ENHANCE_ECO_SPARE0_SHIFT)) + +#define PA_CL_ENHANCE_GET_CLIP_VTX_REORDER_ENA(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK) >> PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT) +#define PA_CL_ENHANCE_GET_ECO_SPARE3(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE3_MASK) >> PA_CL_ENHANCE_ECO_SPARE3_SHIFT) +#define PA_CL_ENHANCE_GET_ECO_SPARE2(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE2_MASK) >> PA_CL_ENHANCE_ECO_SPARE2_SHIFT) +#define PA_CL_ENHANCE_GET_ECO_SPARE1(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE1_MASK) >> PA_CL_ENHANCE_ECO_SPARE1_SHIFT) +#define PA_CL_ENHANCE_GET_ECO_SPARE0(pa_cl_enhance) \ + ((pa_cl_enhance & PA_CL_ENHANCE_ECO_SPARE0_MASK) >> PA_CL_ENHANCE_ECO_SPARE0_SHIFT) + +#define PA_CL_ENHANCE_SET_CLIP_VTX_REORDER_ENA(pa_cl_enhance_reg, clip_vtx_reorder_ena) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_MASK) | (clip_vtx_reorder_ena << PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SHIFT) +#define PA_CL_ENHANCE_SET_ECO_SPARE3(pa_cl_enhance_reg, eco_spare3) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE3_MASK) | (eco_spare3 << PA_CL_ENHANCE_ECO_SPARE3_SHIFT) +#define PA_CL_ENHANCE_SET_ECO_SPARE2(pa_cl_enhance_reg, eco_spare2) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE2_MASK) | (eco_spare2 << PA_CL_ENHANCE_ECO_SPARE2_SHIFT) +#define PA_CL_ENHANCE_SET_ECO_SPARE1(pa_cl_enhance_reg, eco_spare1) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE1_MASK) | (eco_spare1 << PA_CL_ENHANCE_ECO_SPARE1_SHIFT) +#define PA_CL_ENHANCE_SET_ECO_SPARE0(pa_cl_enhance_reg, eco_spare0) \ + pa_cl_enhance_reg = (pa_cl_enhance_reg & ~PA_CL_ENHANCE_ECO_SPARE0_MASK) | (eco_spare0 << PA_CL_ENHANCE_ECO_SPARE0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_enhance_t { + unsigned int clip_vtx_reorder_ena : PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE; + unsigned int : 27; + unsigned int eco_spare3 : PA_CL_ENHANCE_ECO_SPARE3_SIZE; + unsigned int eco_spare2 : PA_CL_ENHANCE_ECO_SPARE2_SIZE; + unsigned int eco_spare1 : PA_CL_ENHANCE_ECO_SPARE1_SIZE; + unsigned int eco_spare0 : PA_CL_ENHANCE_ECO_SPARE0_SIZE; + } pa_cl_enhance_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_enhance_t { + unsigned int eco_spare0 : PA_CL_ENHANCE_ECO_SPARE0_SIZE; + unsigned int eco_spare1 : PA_CL_ENHANCE_ECO_SPARE1_SIZE; + unsigned int eco_spare2 : PA_CL_ENHANCE_ECO_SPARE2_SIZE; + unsigned int eco_spare3 : PA_CL_ENHANCE_ECO_SPARE3_SIZE; + unsigned int : 27; + unsigned int clip_vtx_reorder_ena : PA_CL_ENHANCE_CLIP_VTX_REORDER_ENA_SIZE; + } pa_cl_enhance_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_enhance_t f; +} pa_cl_enhance_u; + + +/* + * PA_SC_ENHANCE struct + */ + +#define PA_SC_ENHANCE_ECO_SPARE3_SIZE 1 +#define PA_SC_ENHANCE_ECO_SPARE2_SIZE 1 +#define PA_SC_ENHANCE_ECO_SPARE1_SIZE 1 +#define PA_SC_ENHANCE_ECO_SPARE0_SIZE 1 + +#define PA_SC_ENHANCE_ECO_SPARE3_SHIFT 28 +#define PA_SC_ENHANCE_ECO_SPARE2_SHIFT 29 +#define PA_SC_ENHANCE_ECO_SPARE1_SHIFT 30 +#define PA_SC_ENHANCE_ECO_SPARE0_SHIFT 31 + +#define PA_SC_ENHANCE_ECO_SPARE3_MASK 0x10000000 +#define PA_SC_ENHANCE_ECO_SPARE2_MASK 0x20000000 +#define PA_SC_ENHANCE_ECO_SPARE1_MASK 0x40000000 +#define PA_SC_ENHANCE_ECO_SPARE0_MASK 0x80000000 + +#define PA_SC_ENHANCE_MASK \ + (PA_SC_ENHANCE_ECO_SPARE3_MASK | \ + PA_SC_ENHANCE_ECO_SPARE2_MASK | \ + PA_SC_ENHANCE_ECO_SPARE1_MASK | \ + PA_SC_ENHANCE_ECO_SPARE0_MASK) + +#define PA_SC_ENHANCE(eco_spare3, eco_spare2, eco_spare1, eco_spare0) \ + ((eco_spare3 << PA_SC_ENHANCE_ECO_SPARE3_SHIFT) | \ + (eco_spare2 << PA_SC_ENHANCE_ECO_SPARE2_SHIFT) | \ + (eco_spare1 << PA_SC_ENHANCE_ECO_SPARE1_SHIFT) | \ + (eco_spare0 << PA_SC_ENHANCE_ECO_SPARE0_SHIFT)) + +#define PA_SC_ENHANCE_GET_ECO_SPARE3(pa_sc_enhance) \ + ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE3_MASK) >> PA_SC_ENHANCE_ECO_SPARE3_SHIFT) +#define PA_SC_ENHANCE_GET_ECO_SPARE2(pa_sc_enhance) \ + ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE2_MASK) >> PA_SC_ENHANCE_ECO_SPARE2_SHIFT) +#define PA_SC_ENHANCE_GET_ECO_SPARE1(pa_sc_enhance) \ + ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE1_MASK) >> PA_SC_ENHANCE_ECO_SPARE1_SHIFT) +#define PA_SC_ENHANCE_GET_ECO_SPARE0(pa_sc_enhance) \ + ((pa_sc_enhance & PA_SC_ENHANCE_ECO_SPARE0_MASK) >> PA_SC_ENHANCE_ECO_SPARE0_SHIFT) + +#define PA_SC_ENHANCE_SET_ECO_SPARE3(pa_sc_enhance_reg, eco_spare3) \ + pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE3_MASK) | (eco_spare3 << PA_SC_ENHANCE_ECO_SPARE3_SHIFT) +#define PA_SC_ENHANCE_SET_ECO_SPARE2(pa_sc_enhance_reg, eco_spare2) \ + pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE2_MASK) | (eco_spare2 << PA_SC_ENHANCE_ECO_SPARE2_SHIFT) +#define PA_SC_ENHANCE_SET_ECO_SPARE1(pa_sc_enhance_reg, eco_spare1) \ + pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE1_MASK) | (eco_spare1 << PA_SC_ENHANCE_ECO_SPARE1_SHIFT) +#define PA_SC_ENHANCE_SET_ECO_SPARE0(pa_sc_enhance_reg, eco_spare0) \ + pa_sc_enhance_reg = (pa_sc_enhance_reg & ~PA_SC_ENHANCE_ECO_SPARE0_MASK) | (eco_spare0 << PA_SC_ENHANCE_ECO_SPARE0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_enhance_t { + unsigned int : 28; + unsigned int eco_spare3 : PA_SC_ENHANCE_ECO_SPARE3_SIZE; + unsigned int eco_spare2 : PA_SC_ENHANCE_ECO_SPARE2_SIZE; + unsigned int eco_spare1 : PA_SC_ENHANCE_ECO_SPARE1_SIZE; + unsigned int eco_spare0 : PA_SC_ENHANCE_ECO_SPARE0_SIZE; + } pa_sc_enhance_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_enhance_t { + unsigned int eco_spare0 : PA_SC_ENHANCE_ECO_SPARE0_SIZE; + unsigned int eco_spare1 : PA_SC_ENHANCE_ECO_SPARE1_SIZE; + unsigned int eco_spare2 : PA_SC_ENHANCE_ECO_SPARE2_SIZE; + unsigned int eco_spare3 : PA_SC_ENHANCE_ECO_SPARE3_SIZE; + unsigned int : 28; + } pa_sc_enhance_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_enhance_t f; +} pa_sc_enhance_u; + + +/* + * PA_SU_VTX_CNTL struct + */ + +#define PA_SU_VTX_CNTL_PIX_CENTER_SIZE 1 +#define PA_SU_VTX_CNTL_ROUND_MODE_SIZE 2 +#define PA_SU_VTX_CNTL_QUANT_MODE_SIZE 3 + +#define PA_SU_VTX_CNTL_PIX_CENTER_SHIFT 0 +#define PA_SU_VTX_CNTL_ROUND_MODE_SHIFT 1 +#define PA_SU_VTX_CNTL_QUANT_MODE_SHIFT 3 + +#define PA_SU_VTX_CNTL_PIX_CENTER_MASK 0x00000001 +#define PA_SU_VTX_CNTL_ROUND_MODE_MASK 0x00000006 +#define PA_SU_VTX_CNTL_QUANT_MODE_MASK 0x00000038 + +#define PA_SU_VTX_CNTL_MASK \ + (PA_SU_VTX_CNTL_PIX_CENTER_MASK | \ + PA_SU_VTX_CNTL_ROUND_MODE_MASK | \ + PA_SU_VTX_CNTL_QUANT_MODE_MASK) + +#define PA_SU_VTX_CNTL(pix_center, round_mode, quant_mode) \ + ((pix_center << PA_SU_VTX_CNTL_PIX_CENTER_SHIFT) | \ + (round_mode << PA_SU_VTX_CNTL_ROUND_MODE_SHIFT) | \ + (quant_mode << PA_SU_VTX_CNTL_QUANT_MODE_SHIFT)) + +#define PA_SU_VTX_CNTL_GET_PIX_CENTER(pa_su_vtx_cntl) \ + ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_PIX_CENTER_MASK) >> PA_SU_VTX_CNTL_PIX_CENTER_SHIFT) +#define PA_SU_VTX_CNTL_GET_ROUND_MODE(pa_su_vtx_cntl) \ + ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_ROUND_MODE_MASK) >> PA_SU_VTX_CNTL_ROUND_MODE_SHIFT) +#define PA_SU_VTX_CNTL_GET_QUANT_MODE(pa_su_vtx_cntl) \ + ((pa_su_vtx_cntl & PA_SU_VTX_CNTL_QUANT_MODE_MASK) >> PA_SU_VTX_CNTL_QUANT_MODE_SHIFT) + +#define PA_SU_VTX_CNTL_SET_PIX_CENTER(pa_su_vtx_cntl_reg, pix_center) \ + pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_PIX_CENTER_MASK) | (pix_center << PA_SU_VTX_CNTL_PIX_CENTER_SHIFT) +#define PA_SU_VTX_CNTL_SET_ROUND_MODE(pa_su_vtx_cntl_reg, round_mode) \ + pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_ROUND_MODE_MASK) | (round_mode << PA_SU_VTX_CNTL_ROUND_MODE_SHIFT) +#define PA_SU_VTX_CNTL_SET_QUANT_MODE(pa_su_vtx_cntl_reg, quant_mode) \ + pa_su_vtx_cntl_reg = (pa_su_vtx_cntl_reg & ~PA_SU_VTX_CNTL_QUANT_MODE_MASK) | (quant_mode << PA_SU_VTX_CNTL_QUANT_MODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_vtx_cntl_t { + unsigned int pix_center : PA_SU_VTX_CNTL_PIX_CENTER_SIZE; + unsigned int round_mode : PA_SU_VTX_CNTL_ROUND_MODE_SIZE; + unsigned int quant_mode : PA_SU_VTX_CNTL_QUANT_MODE_SIZE; + unsigned int : 26; + } pa_su_vtx_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_vtx_cntl_t { + unsigned int : 26; + unsigned int quant_mode : PA_SU_VTX_CNTL_QUANT_MODE_SIZE; + unsigned int round_mode : PA_SU_VTX_CNTL_ROUND_MODE_SIZE; + unsigned int pix_center : PA_SU_VTX_CNTL_PIX_CENTER_SIZE; + } pa_su_vtx_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_vtx_cntl_t f; +} pa_su_vtx_cntl_u; + + +/* + * PA_SU_POINT_SIZE struct + */ + +#define PA_SU_POINT_SIZE_HEIGHT_SIZE 16 +#define PA_SU_POINT_SIZE_WIDTH_SIZE 16 + +#define PA_SU_POINT_SIZE_HEIGHT_SHIFT 0 +#define PA_SU_POINT_SIZE_WIDTH_SHIFT 16 + +#define PA_SU_POINT_SIZE_HEIGHT_MASK 0x0000ffff +#define PA_SU_POINT_SIZE_WIDTH_MASK 0xffff0000 + +#define PA_SU_POINT_SIZE_MASK \ + (PA_SU_POINT_SIZE_HEIGHT_MASK | \ + PA_SU_POINT_SIZE_WIDTH_MASK) + +#define PA_SU_POINT_SIZE(height, width) \ + ((height << PA_SU_POINT_SIZE_HEIGHT_SHIFT) | \ + (width << PA_SU_POINT_SIZE_WIDTH_SHIFT)) + +#define PA_SU_POINT_SIZE_GET_HEIGHT(pa_su_point_size) \ + ((pa_su_point_size & PA_SU_POINT_SIZE_HEIGHT_MASK) >> PA_SU_POINT_SIZE_HEIGHT_SHIFT) +#define PA_SU_POINT_SIZE_GET_WIDTH(pa_su_point_size) \ + ((pa_su_point_size & PA_SU_POINT_SIZE_WIDTH_MASK) >> PA_SU_POINT_SIZE_WIDTH_SHIFT) + +#define PA_SU_POINT_SIZE_SET_HEIGHT(pa_su_point_size_reg, height) \ + pa_su_point_size_reg = (pa_su_point_size_reg & ~PA_SU_POINT_SIZE_HEIGHT_MASK) | (height << PA_SU_POINT_SIZE_HEIGHT_SHIFT) +#define PA_SU_POINT_SIZE_SET_WIDTH(pa_su_point_size_reg, width) \ + pa_su_point_size_reg = (pa_su_point_size_reg & ~PA_SU_POINT_SIZE_WIDTH_MASK) | (width << PA_SU_POINT_SIZE_WIDTH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_point_size_t { + unsigned int height : PA_SU_POINT_SIZE_HEIGHT_SIZE; + unsigned int width : PA_SU_POINT_SIZE_WIDTH_SIZE; + } pa_su_point_size_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_point_size_t { + unsigned int width : PA_SU_POINT_SIZE_WIDTH_SIZE; + unsigned int height : PA_SU_POINT_SIZE_HEIGHT_SIZE; + } pa_su_point_size_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_point_size_t f; +} pa_su_point_size_u; + + +/* + * PA_SU_POINT_MINMAX struct + */ + +#define PA_SU_POINT_MINMAX_MIN_SIZE_SIZE 16 +#define PA_SU_POINT_MINMAX_MAX_SIZE_SIZE 16 + +#define PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT 0 +#define PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT 16 + +#define PA_SU_POINT_MINMAX_MIN_SIZE_MASK 0x0000ffff +#define PA_SU_POINT_MINMAX_MAX_SIZE_MASK 0xffff0000 + +#define PA_SU_POINT_MINMAX_MASK \ + (PA_SU_POINT_MINMAX_MIN_SIZE_MASK | \ + PA_SU_POINT_MINMAX_MAX_SIZE_MASK) + +#define PA_SU_POINT_MINMAX(min_size, max_size) \ + ((min_size << PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT) | \ + (max_size << PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT)) + +#define PA_SU_POINT_MINMAX_GET_MIN_SIZE(pa_su_point_minmax) \ + ((pa_su_point_minmax & PA_SU_POINT_MINMAX_MIN_SIZE_MASK) >> PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT) +#define PA_SU_POINT_MINMAX_GET_MAX_SIZE(pa_su_point_minmax) \ + ((pa_su_point_minmax & PA_SU_POINT_MINMAX_MAX_SIZE_MASK) >> PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT) + +#define PA_SU_POINT_MINMAX_SET_MIN_SIZE(pa_su_point_minmax_reg, min_size) \ + pa_su_point_minmax_reg = (pa_su_point_minmax_reg & ~PA_SU_POINT_MINMAX_MIN_SIZE_MASK) | (min_size << PA_SU_POINT_MINMAX_MIN_SIZE_SHIFT) +#define PA_SU_POINT_MINMAX_SET_MAX_SIZE(pa_su_point_minmax_reg, max_size) \ + pa_su_point_minmax_reg = (pa_su_point_minmax_reg & ~PA_SU_POINT_MINMAX_MAX_SIZE_MASK) | (max_size << PA_SU_POINT_MINMAX_MAX_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_point_minmax_t { + unsigned int min_size : PA_SU_POINT_MINMAX_MIN_SIZE_SIZE; + unsigned int max_size : PA_SU_POINT_MINMAX_MAX_SIZE_SIZE; + } pa_su_point_minmax_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_point_minmax_t { + unsigned int max_size : PA_SU_POINT_MINMAX_MAX_SIZE_SIZE; + unsigned int min_size : PA_SU_POINT_MINMAX_MIN_SIZE_SIZE; + } pa_su_point_minmax_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_point_minmax_t f; +} pa_su_point_minmax_u; + + +/* + * PA_SU_LINE_CNTL struct + */ + +#define PA_SU_LINE_CNTL_WIDTH_SIZE 16 + +#define PA_SU_LINE_CNTL_WIDTH_SHIFT 0 + +#define PA_SU_LINE_CNTL_WIDTH_MASK 0x0000ffff + +#define PA_SU_LINE_CNTL_MASK \ + (PA_SU_LINE_CNTL_WIDTH_MASK) + +#define PA_SU_LINE_CNTL(width) \ + ((width << PA_SU_LINE_CNTL_WIDTH_SHIFT)) + +#define PA_SU_LINE_CNTL_GET_WIDTH(pa_su_line_cntl) \ + ((pa_su_line_cntl & PA_SU_LINE_CNTL_WIDTH_MASK) >> PA_SU_LINE_CNTL_WIDTH_SHIFT) + +#define PA_SU_LINE_CNTL_SET_WIDTH(pa_su_line_cntl_reg, width) \ + pa_su_line_cntl_reg = (pa_su_line_cntl_reg & ~PA_SU_LINE_CNTL_WIDTH_MASK) | (width << PA_SU_LINE_CNTL_WIDTH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_line_cntl_t { + unsigned int width : PA_SU_LINE_CNTL_WIDTH_SIZE; + unsigned int : 16; + } pa_su_line_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_line_cntl_t { + unsigned int : 16; + unsigned int width : PA_SU_LINE_CNTL_WIDTH_SIZE; + } pa_su_line_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_line_cntl_t f; +} pa_su_line_cntl_u; + + +/* + * PA_SU_FACE_DATA struct + */ + +#define PA_SU_FACE_DATA_BASE_ADDR_SIZE 27 + +#define PA_SU_FACE_DATA_BASE_ADDR_SHIFT 5 + +#define PA_SU_FACE_DATA_BASE_ADDR_MASK 0xffffffe0 + +#define PA_SU_FACE_DATA_MASK \ + (PA_SU_FACE_DATA_BASE_ADDR_MASK) + +#define PA_SU_FACE_DATA(base_addr) \ + ((base_addr << PA_SU_FACE_DATA_BASE_ADDR_SHIFT)) + +#define PA_SU_FACE_DATA_GET_BASE_ADDR(pa_su_face_data) \ + ((pa_su_face_data & PA_SU_FACE_DATA_BASE_ADDR_MASK) >> PA_SU_FACE_DATA_BASE_ADDR_SHIFT) + +#define PA_SU_FACE_DATA_SET_BASE_ADDR(pa_su_face_data_reg, base_addr) \ + pa_su_face_data_reg = (pa_su_face_data_reg & ~PA_SU_FACE_DATA_BASE_ADDR_MASK) | (base_addr << PA_SU_FACE_DATA_BASE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_face_data_t { + unsigned int : 5; + unsigned int base_addr : PA_SU_FACE_DATA_BASE_ADDR_SIZE; + } pa_su_face_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_face_data_t { + unsigned int base_addr : PA_SU_FACE_DATA_BASE_ADDR_SIZE; + unsigned int : 5; + } pa_su_face_data_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_face_data_t f; +} pa_su_face_data_u; + + +/* + * PA_SU_SC_MODE_CNTL struct + */ + +#define PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE 1 +#define PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE 1 +#define PA_SU_SC_MODE_CNTL_FACE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE 2 +#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE 3 +#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE 3 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE 1 +#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE 1 +#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE 1 +#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE 1 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_SIZE 1 +#define PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SIZE 1 +#define PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SIZE 1 +#define PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SIZE 1 + +#define PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT 0 +#define PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT 1 +#define PA_SU_SC_MODE_CNTL_FACE_SHIFT 2 +#define PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT 3 +#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT 5 +#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT 8 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT 11 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT 12 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT 13 +#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT 15 +#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT 16 +#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT 18 +#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT 19 +#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT 20 +#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT 21 +#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT 23 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT 25 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT 26 +#define PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_SHIFT 28 +#define PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT 29 +#define PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT 30 +#define PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT 31 + +#define PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK 0x00000001 +#define PA_SU_SC_MODE_CNTL_CULL_BACK_MASK 0x00000002 +#define PA_SU_SC_MODE_CNTL_FACE_MASK 0x00000004 +#define PA_SU_SC_MODE_CNTL_POLY_MODE_MASK 0x00000018 +#define PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK 0x000000e0 +#define PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK 0x00000700 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK 0x00001000 +#define PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK 0x00002000 +#define PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK 0x00008000 +#define PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000 +#define PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK 0x00040000 +#define PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK 0x00080000 +#define PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK 0x00100000 +#define PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK 0x00200000 +#define PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK 0x00800000 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK 0x02000000 +#define PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK 0x04000000 +#define PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_MASK 0x10000000 +#define PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK 0x20000000 +#define PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK 0x40000000 +#define PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK 0x80000000 + +#define PA_SU_SC_MODE_CNTL_MASK \ + (PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK | \ + PA_SU_SC_MODE_CNTL_CULL_BACK_MASK | \ + PA_SU_SC_MODE_CNTL_FACE_MASK | \ + PA_SU_SC_MODE_CNTL_POLY_MODE_MASK | \ + PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK | \ + PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK | \ + PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK | \ + PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK | \ + PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK | \ + PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK | \ + PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK | \ + PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_MASK | \ + PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK | \ + PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK | \ + PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK) + +#define PA_SU_SC_MODE_CNTL(cull_front, cull_back, face, poly_mode, polymode_front_ptype, polymode_back_ptype, poly_offset_front_enable, poly_offset_back_enable, poly_offset_para_enable, msaa_enable, vtx_window_offset_enable, line_stipple_enable, provoking_vtx_last, persp_corr_dis, multi_prim_ib_ena, quad_order_enable, wait_rb_idle_all_tri, wait_rb_idle_first_tri_new_state, clamped_faceness, zero_area_faceness, face_kill_enable, face_write_enable) \ + ((cull_front << PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT) | \ + (cull_back << PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT) | \ + (face << PA_SU_SC_MODE_CNTL_FACE_SHIFT) | \ + (poly_mode << PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT) | \ + (polymode_front_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT) | \ + (polymode_back_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT) | \ + (poly_offset_front_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT) | \ + (poly_offset_back_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT) | \ + (poly_offset_para_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT) | \ + (msaa_enable << PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT) | \ + (vtx_window_offset_enable << PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT) | \ + (line_stipple_enable << PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT) | \ + (provoking_vtx_last << PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT) | \ + (persp_corr_dis << PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT) | \ + (multi_prim_ib_ena << PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT) | \ + (quad_order_enable << PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT) | \ + (wait_rb_idle_all_tri << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT) | \ + (wait_rb_idle_first_tri_new_state << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT) | \ + (clamped_faceness << PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_SHIFT) | \ + (zero_area_faceness << PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT) | \ + (face_kill_enable << PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT) | \ + (face_write_enable << PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT)) + +#define PA_SU_SC_MODE_CNTL_GET_CULL_FRONT(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK) >> PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_CULL_BACK(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_CULL_BACK_MASK) >> PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_FACE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_FACE_MASK) >> PA_SU_SC_MODE_CNTL_FACE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLY_MODE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_MODE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLYMODE_FRONT_PTYPE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK) >> PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLYMODE_BACK_PTYPE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK) >> PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_FRONT_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_BACK_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_POLY_OFFSET_PARA_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_MSAA_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_VTX_WINDOW_OFFSET_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_LINE_STIPPLE_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_PROVOKING_VTX_LAST(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK) >> PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_PERSP_CORR_DIS(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK) >> PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_MULTI_PRIM_IB_ENA(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK) >> PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_QUAD_ORDER_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_WAIT_RB_IDLE_ALL_TRI(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK) >> PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK) >> PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_CLAMPED_FACENESS(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_MASK) >> PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_ZERO_AREA_FACENESS(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK) >> PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_FACE_KILL_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_GET_FACE_WRITE_ENABLE(pa_su_sc_mode_cntl) \ + ((pa_su_sc_mode_cntl & PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK) >> PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT) + +#define PA_SU_SC_MODE_CNTL_SET_CULL_FRONT(pa_su_sc_mode_cntl_reg, cull_front) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK) | (cull_front << PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_CULL_BACK(pa_su_sc_mode_cntl_reg, cull_back) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_CULL_BACK_MASK) | (cull_back << PA_SU_SC_MODE_CNTL_CULL_BACK_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_FACE(pa_su_sc_mode_cntl_reg, face) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_FACE_MASK) | (face << PA_SU_SC_MODE_CNTL_FACE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLY_MODE(pa_su_sc_mode_cntl_reg, poly_mode) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_MODE_MASK) | (poly_mode << PA_SU_SC_MODE_CNTL_POLY_MODE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLYMODE_FRONT_PTYPE(pa_su_sc_mode_cntl_reg, polymode_front_ptype) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_MASK) | (polymode_front_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLYMODE_BACK_PTYPE(pa_su_sc_mode_cntl_reg, polymode_back_ptype) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_MASK) | (polymode_back_ptype << PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_FRONT_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_front_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_MASK) | (poly_offset_front_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_BACK_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_back_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_MASK) | (poly_offset_back_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_POLY_OFFSET_PARA_ENABLE(pa_su_sc_mode_cntl_reg, poly_offset_para_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_MASK) | (poly_offset_para_enable << PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_MSAA_ENABLE(pa_su_sc_mode_cntl_reg, msaa_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_MSAA_ENABLE_MASK) | (msaa_enable << PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_VTX_WINDOW_OFFSET_ENABLE(pa_su_sc_mode_cntl_reg, vtx_window_offset_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_MASK) | (vtx_window_offset_enable << PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_LINE_STIPPLE_ENABLE(pa_su_sc_mode_cntl_reg, line_stipple_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_MASK) | (line_stipple_enable << PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_PROVOKING_VTX_LAST(pa_su_sc_mode_cntl_reg, provoking_vtx_last) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK) | (provoking_vtx_last << PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_PERSP_CORR_DIS(pa_su_sc_mode_cntl_reg, persp_corr_dis) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK) | (persp_corr_dis << PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_MULTI_PRIM_IB_ENA(pa_su_sc_mode_cntl_reg, multi_prim_ib_ena) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_MASK) | (multi_prim_ib_ena << PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_QUAD_ORDER_ENABLE(pa_su_sc_mode_cntl_reg, quad_order_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_MASK) | (quad_order_enable << PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_WAIT_RB_IDLE_ALL_TRI(pa_su_sc_mode_cntl_reg, wait_rb_idle_all_tri) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_MASK) | (wait_rb_idle_all_tri << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE(pa_su_sc_mode_cntl_reg, wait_rb_idle_first_tri_new_state) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_MASK) | (wait_rb_idle_first_tri_new_state << PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_CLAMPED_FACENESS(pa_su_sc_mode_cntl_reg, clamped_faceness) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_MASK) | (clamped_faceness << PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_ZERO_AREA_FACENESS(pa_su_sc_mode_cntl_reg, zero_area_faceness) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_MASK) | (zero_area_faceness << PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_FACE_KILL_ENABLE(pa_su_sc_mode_cntl_reg, face_kill_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_MASK) | (face_kill_enable << PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SHIFT) +#define PA_SU_SC_MODE_CNTL_SET_FACE_WRITE_ENABLE(pa_su_sc_mode_cntl_reg, face_write_enable) \ + pa_su_sc_mode_cntl_reg = (pa_su_sc_mode_cntl_reg & ~PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_MASK) | (face_write_enable << PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_sc_mode_cntl_t { + unsigned int cull_front : PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE; + unsigned int cull_back : PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE; + unsigned int face : PA_SU_SC_MODE_CNTL_FACE_SIZE; + unsigned int poly_mode : PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE; + unsigned int polymode_front_ptype : PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE; + unsigned int polymode_back_ptype : PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE; + unsigned int poly_offset_front_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE; + unsigned int poly_offset_back_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE; + unsigned int poly_offset_para_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE; + unsigned int : 1; + unsigned int msaa_enable : PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE; + unsigned int vtx_window_offset_enable : PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE; + unsigned int : 1; + unsigned int line_stipple_enable : PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE; + unsigned int provoking_vtx_last : PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE; + unsigned int persp_corr_dis : PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE; + unsigned int multi_prim_ib_ena : PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE; + unsigned int : 1; + unsigned int quad_order_enable : PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE; + unsigned int : 1; + unsigned int wait_rb_idle_all_tri : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE; + unsigned int wait_rb_idle_first_tri_new_state : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE; + unsigned int : 1; + unsigned int clamped_faceness : PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_SIZE; + unsigned int zero_area_faceness : PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SIZE; + unsigned int face_kill_enable : PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SIZE; + unsigned int face_write_enable : PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SIZE; + } pa_su_sc_mode_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_sc_mode_cntl_t { + unsigned int face_write_enable : PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE_SIZE; + unsigned int face_kill_enable : PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE_SIZE; + unsigned int zero_area_faceness : PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS_SIZE; + unsigned int clamped_faceness : PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS_SIZE; + unsigned int : 1; + unsigned int wait_rb_idle_first_tri_new_state : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE_SIZE; + unsigned int wait_rb_idle_all_tri : PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI_SIZE; + unsigned int : 1; + unsigned int quad_order_enable : PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE_SIZE; + unsigned int : 1; + unsigned int multi_prim_ib_ena : PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA_SIZE; + unsigned int persp_corr_dis : PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SIZE; + unsigned int provoking_vtx_last : PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_SIZE; + unsigned int line_stipple_enable : PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE_SIZE; + unsigned int : 1; + unsigned int vtx_window_offset_enable : PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE_SIZE; + unsigned int msaa_enable : PA_SU_SC_MODE_CNTL_MSAA_ENABLE_SIZE; + unsigned int : 1; + unsigned int poly_offset_para_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE_SIZE; + unsigned int poly_offset_back_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE_SIZE; + unsigned int poly_offset_front_enable : PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE_SIZE; + unsigned int polymode_back_ptype : PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE_SIZE; + unsigned int polymode_front_ptype : PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE_SIZE; + unsigned int poly_mode : PA_SU_SC_MODE_CNTL_POLY_MODE_SIZE; + unsigned int face : PA_SU_SC_MODE_CNTL_FACE_SIZE; + unsigned int cull_back : PA_SU_SC_MODE_CNTL_CULL_BACK_SIZE; + unsigned int cull_front : PA_SU_SC_MODE_CNTL_CULL_FRONT_SIZE; + } pa_su_sc_mode_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_sc_mode_cntl_t f; +} pa_su_sc_mode_cntl_u; + + +/* + * PA_SU_POLY_OFFSET_FRONT_SCALE struct + */ + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE 32 + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT 0 + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK 0xffffffff + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_MASK \ + (PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) + +#define PA_SU_POLY_OFFSET_FRONT_SCALE(scale) \ + ((scale << PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT)) + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_GET_SCALE(pa_su_poly_offset_front_scale) \ + ((pa_su_poly_offset_front_scale & PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) >> PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT) + +#define PA_SU_POLY_OFFSET_FRONT_SCALE_SET_SCALE(pa_su_poly_offset_front_scale_reg, scale) \ + pa_su_poly_offset_front_scale_reg = (pa_su_poly_offset_front_scale_reg & ~PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_MASK) | (scale << PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_front_scale_t { + unsigned int scale : PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE; + } pa_su_poly_offset_front_scale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_front_scale_t { + unsigned int scale : PA_SU_POLY_OFFSET_FRONT_SCALE_SCALE_SIZE; + } pa_su_poly_offset_front_scale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_poly_offset_front_scale_t f; +} pa_su_poly_offset_front_scale_u; + + +/* + * PA_SU_POLY_OFFSET_FRONT_OFFSET struct + */ + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE 32 + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT 0 + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK 0xffffffff + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_MASK \ + (PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET(offset) \ + ((offset << PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT)) + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_GET_OFFSET(pa_su_poly_offset_front_offset) \ + ((pa_su_poly_offset_front_offset & PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) >> PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT) + +#define PA_SU_POLY_OFFSET_FRONT_OFFSET_SET_OFFSET(pa_su_poly_offset_front_offset_reg, offset) \ + pa_su_poly_offset_front_offset_reg = (pa_su_poly_offset_front_offset_reg & ~PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_MASK) | (offset << PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_front_offset_t { + unsigned int offset : PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE; + } pa_su_poly_offset_front_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_front_offset_t { + unsigned int offset : PA_SU_POLY_OFFSET_FRONT_OFFSET_OFFSET_SIZE; + } pa_su_poly_offset_front_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_poly_offset_front_offset_t f; +} pa_su_poly_offset_front_offset_u; + + +/* + * PA_SU_POLY_OFFSET_BACK_SCALE struct + */ + +#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE 32 + +#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT 0 + +#define PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK 0xffffffff + +#define PA_SU_POLY_OFFSET_BACK_SCALE_MASK \ + (PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) + +#define PA_SU_POLY_OFFSET_BACK_SCALE(scale) \ + ((scale << PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT)) + +#define PA_SU_POLY_OFFSET_BACK_SCALE_GET_SCALE(pa_su_poly_offset_back_scale) \ + ((pa_su_poly_offset_back_scale & PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) >> PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT) + +#define PA_SU_POLY_OFFSET_BACK_SCALE_SET_SCALE(pa_su_poly_offset_back_scale_reg, scale) \ + pa_su_poly_offset_back_scale_reg = (pa_su_poly_offset_back_scale_reg & ~PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_MASK) | (scale << PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_back_scale_t { + unsigned int scale : PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE; + } pa_su_poly_offset_back_scale_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_back_scale_t { + unsigned int scale : PA_SU_POLY_OFFSET_BACK_SCALE_SCALE_SIZE; + } pa_su_poly_offset_back_scale_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_poly_offset_back_scale_t f; +} pa_su_poly_offset_back_scale_u; + + +/* + * PA_SU_POLY_OFFSET_BACK_OFFSET struct + */ + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE 32 + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT 0 + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK 0xffffffff + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_MASK \ + (PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) + +#define PA_SU_POLY_OFFSET_BACK_OFFSET(offset) \ + ((offset << PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT)) + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_GET_OFFSET(pa_su_poly_offset_back_offset) \ + ((pa_su_poly_offset_back_offset & PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) >> PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT) + +#define PA_SU_POLY_OFFSET_BACK_OFFSET_SET_OFFSET(pa_su_poly_offset_back_offset_reg, offset) \ + pa_su_poly_offset_back_offset_reg = (pa_su_poly_offset_back_offset_reg & ~PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_MASK) | (offset << PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_back_offset_t { + unsigned int offset : PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE; + } pa_su_poly_offset_back_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_poly_offset_back_offset_t { + unsigned int offset : PA_SU_POLY_OFFSET_BACK_OFFSET_OFFSET_SIZE; + } pa_su_poly_offset_back_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_poly_offset_back_offset_t f; +} pa_su_poly_offset_back_offset_u; + + +/* + * PA_SU_PERFCOUNTER0_SELECT struct + */ + +#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SU_PERFCOUNTER0_SELECT_MASK \ + (PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define PA_SU_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define PA_SU_PERFCOUNTER0_SELECT_GET_PERF_SEL(pa_su_perfcounter0_select) \ + ((pa_su_perfcounter0_select & PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define PA_SU_PERFCOUNTER0_SELECT_SET_PERF_SEL(pa_su_perfcounter0_select_reg, perf_sel) \ + pa_su_perfcounter0_select_reg = (pa_su_perfcounter0_select_reg & ~PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_select_t { + unsigned int perf_sel : PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_su_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SU_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } pa_su_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter0_select_t f; +} pa_su_perfcounter0_select_u; + + +/* + * PA_SU_PERFCOUNTER1_SELECT struct + */ + +#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8 + +#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SU_PERFCOUNTER1_SELECT_MASK \ + (PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) + +#define PA_SU_PERFCOUNTER1_SELECT(perf_sel) \ + ((perf_sel << PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)) + +#define PA_SU_PERFCOUNTER1_SELECT_GET_PERF_SEL(pa_su_perfcounter1_select) \ + ((pa_su_perfcounter1_select & PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#define PA_SU_PERFCOUNTER1_SELECT_SET_PERF_SEL(pa_su_perfcounter1_select_reg, perf_sel) \ + pa_su_perfcounter1_select_reg = (pa_su_perfcounter1_select_reg & ~PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_select_t { + unsigned int perf_sel : PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_su_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SU_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + } pa_su_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter1_select_t f; +} pa_su_perfcounter1_select_u; + + +/* + * PA_SU_PERFCOUNTER2_SELECT struct + */ + +#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8 + +#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SU_PERFCOUNTER2_SELECT_MASK \ + (PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) + +#define PA_SU_PERFCOUNTER2_SELECT(perf_sel) \ + ((perf_sel << PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)) + +#define PA_SU_PERFCOUNTER2_SELECT_GET_PERF_SEL(pa_su_perfcounter2_select) \ + ((pa_su_perfcounter2_select & PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#define PA_SU_PERFCOUNTER2_SELECT_SET_PERF_SEL(pa_su_perfcounter2_select_reg, perf_sel) \ + pa_su_perfcounter2_select_reg = (pa_su_perfcounter2_select_reg & ~PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_select_t { + unsigned int perf_sel : PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_su_perfcounter2_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SU_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + } pa_su_perfcounter2_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter2_select_t f; +} pa_su_perfcounter2_select_u; + + +/* + * PA_SU_PERFCOUNTER3_SELECT struct + */ + +#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8 + +#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SU_PERFCOUNTER3_SELECT_MASK \ + (PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) + +#define PA_SU_PERFCOUNTER3_SELECT(perf_sel) \ + ((perf_sel << PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)) + +#define PA_SU_PERFCOUNTER3_SELECT_GET_PERF_SEL(pa_su_perfcounter3_select) \ + ((pa_su_perfcounter3_select & PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#define PA_SU_PERFCOUNTER3_SELECT_SET_PERF_SEL(pa_su_perfcounter3_select_reg, perf_sel) \ + pa_su_perfcounter3_select_reg = (pa_su_perfcounter3_select_reg & ~PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_select_t { + unsigned int perf_sel : PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_su_perfcounter3_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SU_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + } pa_su_perfcounter3_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter3_select_t f; +} pa_su_perfcounter3_select_u; + + +/* + * PA_SU_PERFCOUNTER0_LOW struct + */ + +#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SU_PERFCOUNTER0_LOW_MASK \ + (PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER0_LOW_GET_PERF_COUNT(pa_su_perfcounter0_low) \ + ((pa_su_perfcounter0_low & PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER0_LOW_SET_PERF_COUNT(pa_su_perfcounter0_low_reg, perf_count) \ + pa_su_perfcounter0_low_reg = (pa_su_perfcounter0_low_reg & ~PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter0_low_t f; +} pa_su_perfcounter0_low_u; + + +/* + * PA_SU_PERFCOUNTER0_HI struct + */ + +#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SU_PERFCOUNTER0_HI_MASK \ + (PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER0_HI_GET_PERF_COUNT(pa_su_perfcounter0_hi) \ + ((pa_su_perfcounter0_hi & PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER0_HI_SET_PERF_COUNT(pa_su_perfcounter0_hi_reg, perf_count) \ + pa_su_perfcounter0_hi_reg = (pa_su_perfcounter0_hi_reg & ~PA_SU_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_hi_t { + unsigned int perf_count : PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_su_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SU_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } pa_su_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter0_hi_t f; +} pa_su_perfcounter0_hi_u; + + +/* + * PA_SU_PERFCOUNTER1_LOW struct + */ + +#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32 + +#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SU_PERFCOUNTER1_LOW_MASK \ + (PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER1_LOW(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER1_LOW_GET_PERF_COUNT(pa_su_perfcounter1_low) \ + ((pa_su_perfcounter1_low & PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER1_LOW_SET_PERF_COUNT(pa_su_perfcounter1_low_reg, perf_count) \ + pa_su_perfcounter1_low_reg = (pa_su_perfcounter1_low_reg & ~PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter1_low_t f; +} pa_su_perfcounter1_low_u; + + +/* + * PA_SU_PERFCOUNTER1_HI struct + */ + +#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16 + +#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SU_PERFCOUNTER1_HI_MASK \ + (PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER1_HI(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER1_HI_GET_PERF_COUNT(pa_su_perfcounter1_hi) \ + ((pa_su_perfcounter1_hi & PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER1_HI_SET_PERF_COUNT(pa_su_perfcounter1_hi_reg, perf_count) \ + pa_su_perfcounter1_hi_reg = (pa_su_perfcounter1_hi_reg & ~PA_SU_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_hi_t { + unsigned int perf_count : PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_su_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SU_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + } pa_su_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter1_hi_t f; +} pa_su_perfcounter1_hi_u; + + +/* + * PA_SU_PERFCOUNTER2_LOW struct + */ + +#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32 + +#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SU_PERFCOUNTER2_LOW_MASK \ + (PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER2_LOW(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER2_LOW_GET_PERF_COUNT(pa_su_perfcounter2_low) \ + ((pa_su_perfcounter2_low & PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER2_LOW_SET_PERF_COUNT(pa_su_perfcounter2_low_reg, perf_count) \ + pa_su_perfcounter2_low_reg = (pa_su_perfcounter2_low_reg & ~PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter2_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter2_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter2_low_t f; +} pa_su_perfcounter2_low_u; + + +/* + * PA_SU_PERFCOUNTER2_HI struct + */ + +#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16 + +#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SU_PERFCOUNTER2_HI_MASK \ + (PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER2_HI(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER2_HI_GET_PERF_COUNT(pa_su_perfcounter2_hi) \ + ((pa_su_perfcounter2_hi & PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER2_HI_SET_PERF_COUNT(pa_su_perfcounter2_hi_reg, perf_count) \ + pa_su_perfcounter2_hi_reg = (pa_su_perfcounter2_hi_reg & ~PA_SU_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_hi_t { + unsigned int perf_count : PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_su_perfcounter2_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter2_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SU_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + } pa_su_perfcounter2_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter2_hi_t f; +} pa_su_perfcounter2_hi_u; + + +/* + * PA_SU_PERFCOUNTER3_LOW struct + */ + +#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32 + +#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SU_PERFCOUNTER3_LOW_MASK \ + (PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER3_LOW(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER3_LOW_GET_PERF_COUNT(pa_su_perfcounter3_low) \ + ((pa_su_perfcounter3_low & PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER3_LOW_SET_PERF_COUNT(pa_su_perfcounter3_low_reg, perf_count) \ + pa_su_perfcounter3_low_reg = (pa_su_perfcounter3_low_reg & ~PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter3_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_low_t { + unsigned int perf_count : PA_SU_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } pa_su_perfcounter3_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter3_low_t f; +} pa_su_perfcounter3_low_u; + + +/* + * PA_SU_PERFCOUNTER3_HI struct + */ + +#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16 + +#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0 + +#define PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SU_PERFCOUNTER3_HI_MASK \ + (PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) + +#define PA_SU_PERFCOUNTER3_HI(perf_count) \ + ((perf_count << PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)) + +#define PA_SU_PERFCOUNTER3_HI_GET_PERF_COUNT(pa_su_perfcounter3_hi) \ + ((pa_su_perfcounter3_hi & PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#define PA_SU_PERFCOUNTER3_HI_SET_PERF_COUNT(pa_su_perfcounter3_hi_reg, perf_count) \ + pa_su_perfcounter3_hi_reg = (pa_su_perfcounter3_hi_reg & ~PA_SU_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_hi_t { + unsigned int perf_count : PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_su_perfcounter3_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_perfcounter3_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SU_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + } pa_su_perfcounter3_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_perfcounter3_hi_t f; +} pa_su_perfcounter3_hi_u; + + +/* + * PA_SC_WINDOW_OFFSET struct + */ + +#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE 15 +#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE 15 + +#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT 0 +#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT 16 + +#define PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK 0x00007fff +#define PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK 0x7fff0000 + +#define PA_SC_WINDOW_OFFSET_MASK \ + (PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK | \ + PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) + +#define PA_SC_WINDOW_OFFSET(window_x_offset, window_y_offset) \ + ((window_x_offset << PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT) | \ + (window_y_offset << PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT)) + +#define PA_SC_WINDOW_OFFSET_GET_WINDOW_X_OFFSET(pa_sc_window_offset) \ + ((pa_sc_window_offset & PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK) >> PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT) +#define PA_SC_WINDOW_OFFSET_GET_WINDOW_Y_OFFSET(pa_sc_window_offset) \ + ((pa_sc_window_offset & PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) >> PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT) + +#define PA_SC_WINDOW_OFFSET_SET_WINDOW_X_OFFSET(pa_sc_window_offset_reg, window_x_offset) \ + pa_sc_window_offset_reg = (pa_sc_window_offset_reg & ~PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_MASK) | (window_x_offset << PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SHIFT) +#define PA_SC_WINDOW_OFFSET_SET_WINDOW_Y_OFFSET(pa_sc_window_offset_reg, window_y_offset) \ + pa_sc_window_offset_reg = (pa_sc_window_offset_reg & ~PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_MASK) | (window_y_offset << PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_window_offset_t { + unsigned int window_x_offset : PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE; + unsigned int : 1; + unsigned int window_y_offset : PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE; + unsigned int : 1; + } pa_sc_window_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_window_offset_t { + unsigned int : 1; + unsigned int window_y_offset : PA_SC_WINDOW_OFFSET_WINDOW_Y_OFFSET_SIZE; + unsigned int : 1; + unsigned int window_x_offset : PA_SC_WINDOW_OFFSET_WINDOW_X_OFFSET_SIZE; + } pa_sc_window_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_window_offset_t f; +} pa_sc_window_offset_u; + + +/* + * PA_SC_AA_CONFIG struct + */ + +#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE 3 +#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE 4 + +#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT 0 +#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT 13 + +#define PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK 0x00000007 +#define PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK 0x0001e000 + +#define PA_SC_AA_CONFIG_MASK \ + (PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK | \ + PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) + +#define PA_SC_AA_CONFIG(msaa_num_samples, max_sample_dist) \ + ((msaa_num_samples << PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT) | \ + (max_sample_dist << PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT)) + +#define PA_SC_AA_CONFIG_GET_MSAA_NUM_SAMPLES(pa_sc_aa_config) \ + ((pa_sc_aa_config & PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK) >> PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT) +#define PA_SC_AA_CONFIG_GET_MAX_SAMPLE_DIST(pa_sc_aa_config) \ + ((pa_sc_aa_config & PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) >> PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT) + +#define PA_SC_AA_CONFIG_SET_MSAA_NUM_SAMPLES(pa_sc_aa_config_reg, msaa_num_samples) \ + pa_sc_aa_config_reg = (pa_sc_aa_config_reg & ~PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_MASK) | (msaa_num_samples << PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT) +#define PA_SC_AA_CONFIG_SET_MAX_SAMPLE_DIST(pa_sc_aa_config_reg, max_sample_dist) \ + pa_sc_aa_config_reg = (pa_sc_aa_config_reg & ~PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK) | (max_sample_dist << PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_aa_config_t { + unsigned int msaa_num_samples : PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE; + unsigned int : 10; + unsigned int max_sample_dist : PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE; + unsigned int : 15; + } pa_sc_aa_config_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_aa_config_t { + unsigned int : 15; + unsigned int max_sample_dist : PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_SIZE; + unsigned int : 10; + unsigned int msaa_num_samples : PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SIZE; + } pa_sc_aa_config_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_aa_config_t f; +} pa_sc_aa_config_u; + + +/* + * PA_SC_AA_MASK struct + */ + +#define PA_SC_AA_MASK_AA_MASK_SIZE 16 + +#define PA_SC_AA_MASK_AA_MASK_SHIFT 0 + +#define PA_SC_AA_MASK_AA_MASK_MASK 0x0000ffff + +#define PA_SC_AA_MASK_MASK \ + (PA_SC_AA_MASK_AA_MASK_MASK) + +#define PA_SC_AA_MASK(aa_mask) \ + ((aa_mask << PA_SC_AA_MASK_AA_MASK_SHIFT)) + +#define PA_SC_AA_MASK_GET_AA_MASK(pa_sc_aa_mask) \ + ((pa_sc_aa_mask & PA_SC_AA_MASK_AA_MASK_MASK) >> PA_SC_AA_MASK_AA_MASK_SHIFT) + +#define PA_SC_AA_MASK_SET_AA_MASK(pa_sc_aa_mask_reg, aa_mask) \ + pa_sc_aa_mask_reg = (pa_sc_aa_mask_reg & ~PA_SC_AA_MASK_AA_MASK_MASK) | (aa_mask << PA_SC_AA_MASK_AA_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_aa_mask_t { + unsigned int aa_mask : PA_SC_AA_MASK_AA_MASK_SIZE; + unsigned int : 16; + } pa_sc_aa_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_aa_mask_t { + unsigned int : 16; + unsigned int aa_mask : PA_SC_AA_MASK_AA_MASK_SIZE; + } pa_sc_aa_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_aa_mask_t f; +} pa_sc_aa_mask_u; + + +/* + * PA_SC_LINE_STIPPLE struct + */ + +#define PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE 16 +#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE 8 +#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE 1 +#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE 2 + +#define PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT 0 +#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT 16 +#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT 28 +#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT 29 + +#define PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK 0x0000ffff +#define PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK 0x00ff0000 +#define PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK 0x10000000 +#define PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK 0x60000000 + +#define PA_SC_LINE_STIPPLE_MASK \ + (PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK | \ + PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK | \ + PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK | \ + PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) + +#define PA_SC_LINE_STIPPLE(line_pattern, repeat_count, pattern_bit_order, auto_reset_cntl) \ + ((line_pattern << PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT) | \ + (repeat_count << PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT) | \ + (pattern_bit_order << PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT) | \ + (auto_reset_cntl << PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT)) + +#define PA_SC_LINE_STIPPLE_GET_LINE_PATTERN(pa_sc_line_stipple) \ + ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK) >> PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT) +#define PA_SC_LINE_STIPPLE_GET_REPEAT_COUNT(pa_sc_line_stipple) \ + ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK) >> PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT) +#define PA_SC_LINE_STIPPLE_GET_PATTERN_BIT_ORDER(pa_sc_line_stipple) \ + ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK) >> PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT) +#define PA_SC_LINE_STIPPLE_GET_AUTO_RESET_CNTL(pa_sc_line_stipple) \ + ((pa_sc_line_stipple & PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) >> PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT) + +#define PA_SC_LINE_STIPPLE_SET_LINE_PATTERN(pa_sc_line_stipple_reg, line_pattern) \ + pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_LINE_PATTERN_MASK) | (line_pattern << PA_SC_LINE_STIPPLE_LINE_PATTERN_SHIFT) +#define PA_SC_LINE_STIPPLE_SET_REPEAT_COUNT(pa_sc_line_stipple_reg, repeat_count) \ + pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_REPEAT_COUNT_MASK) | (repeat_count << PA_SC_LINE_STIPPLE_REPEAT_COUNT_SHIFT) +#define PA_SC_LINE_STIPPLE_SET_PATTERN_BIT_ORDER(pa_sc_line_stipple_reg, pattern_bit_order) \ + pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_MASK) | (pattern_bit_order << PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SHIFT) +#define PA_SC_LINE_STIPPLE_SET_AUTO_RESET_CNTL(pa_sc_line_stipple_reg, auto_reset_cntl) \ + pa_sc_line_stipple_reg = (pa_sc_line_stipple_reg & ~PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_MASK) | (auto_reset_cntl << PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_line_stipple_t { + unsigned int line_pattern : PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE; + unsigned int repeat_count : PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE; + unsigned int : 4; + unsigned int pattern_bit_order : PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE; + unsigned int auto_reset_cntl : PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE; + unsigned int : 1; + } pa_sc_line_stipple_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_line_stipple_t { + unsigned int : 1; + unsigned int auto_reset_cntl : PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL_SIZE; + unsigned int pattern_bit_order : PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER_SIZE; + unsigned int : 4; + unsigned int repeat_count : PA_SC_LINE_STIPPLE_REPEAT_COUNT_SIZE; + unsigned int line_pattern : PA_SC_LINE_STIPPLE_LINE_PATTERN_SIZE; + } pa_sc_line_stipple_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_line_stipple_t f; +} pa_sc_line_stipple_u; + + +/* + * PA_SC_LINE_CNTL struct + */ + +#define PA_SC_LINE_CNTL_BRES_CNTL_SIZE 8 +#define PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE 1 +#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE 1 +#define PA_SC_LINE_CNTL_LAST_PIXEL_SIZE 1 + +#define PA_SC_LINE_CNTL_BRES_CNTL_SHIFT 0 +#define PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT 8 +#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT 9 +#define PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT 10 + +#define PA_SC_LINE_CNTL_BRES_CNTL_MASK 0x000000ff +#define PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK 0x00000100 +#define PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK 0x00000200 +#define PA_SC_LINE_CNTL_LAST_PIXEL_MASK 0x00000400 + +#define PA_SC_LINE_CNTL_MASK \ + (PA_SC_LINE_CNTL_BRES_CNTL_MASK | \ + PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK | \ + PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK | \ + PA_SC_LINE_CNTL_LAST_PIXEL_MASK) + +#define PA_SC_LINE_CNTL(bres_cntl, use_bres_cntl, expand_line_width, last_pixel) \ + ((bres_cntl << PA_SC_LINE_CNTL_BRES_CNTL_SHIFT) | \ + (use_bres_cntl << PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT) | \ + (expand_line_width << PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT) | \ + (last_pixel << PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT)) + +#define PA_SC_LINE_CNTL_GET_BRES_CNTL(pa_sc_line_cntl) \ + ((pa_sc_line_cntl & PA_SC_LINE_CNTL_BRES_CNTL_MASK) >> PA_SC_LINE_CNTL_BRES_CNTL_SHIFT) +#define PA_SC_LINE_CNTL_GET_USE_BRES_CNTL(pa_sc_line_cntl) \ + ((pa_sc_line_cntl & PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK) >> PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT) +#define PA_SC_LINE_CNTL_GET_EXPAND_LINE_WIDTH(pa_sc_line_cntl) \ + ((pa_sc_line_cntl & PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK) >> PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT) +#define PA_SC_LINE_CNTL_GET_LAST_PIXEL(pa_sc_line_cntl) \ + ((pa_sc_line_cntl & PA_SC_LINE_CNTL_LAST_PIXEL_MASK) >> PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT) + +#define PA_SC_LINE_CNTL_SET_BRES_CNTL(pa_sc_line_cntl_reg, bres_cntl) \ + pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_BRES_CNTL_MASK) | (bres_cntl << PA_SC_LINE_CNTL_BRES_CNTL_SHIFT) +#define PA_SC_LINE_CNTL_SET_USE_BRES_CNTL(pa_sc_line_cntl_reg, use_bres_cntl) \ + pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_USE_BRES_CNTL_MASK) | (use_bres_cntl << PA_SC_LINE_CNTL_USE_BRES_CNTL_SHIFT) +#define PA_SC_LINE_CNTL_SET_EXPAND_LINE_WIDTH(pa_sc_line_cntl_reg, expand_line_width) \ + pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_MASK) | (expand_line_width << PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SHIFT) +#define PA_SC_LINE_CNTL_SET_LAST_PIXEL(pa_sc_line_cntl_reg, last_pixel) \ + pa_sc_line_cntl_reg = (pa_sc_line_cntl_reg & ~PA_SC_LINE_CNTL_LAST_PIXEL_MASK) | (last_pixel << PA_SC_LINE_CNTL_LAST_PIXEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_line_cntl_t { + unsigned int bres_cntl : PA_SC_LINE_CNTL_BRES_CNTL_SIZE; + unsigned int use_bres_cntl : PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE; + unsigned int expand_line_width : PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE; + unsigned int last_pixel : PA_SC_LINE_CNTL_LAST_PIXEL_SIZE; + unsigned int : 21; + } pa_sc_line_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_line_cntl_t { + unsigned int : 21; + unsigned int last_pixel : PA_SC_LINE_CNTL_LAST_PIXEL_SIZE; + unsigned int expand_line_width : PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH_SIZE; + unsigned int use_bres_cntl : PA_SC_LINE_CNTL_USE_BRES_CNTL_SIZE; + unsigned int bres_cntl : PA_SC_LINE_CNTL_BRES_CNTL_SIZE; + } pa_sc_line_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_line_cntl_t f; +} pa_sc_line_cntl_u; + + +/* + * PA_SC_WINDOW_SCISSOR_TL struct + */ + +#define PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE 14 +#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE 14 +#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE 1 + +#define PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT 0 +#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT 16 +#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT 31 + +#define PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK 0x00003fff +#define PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK 0x3fff0000 +#define PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK 0x80000000 + +#define PA_SC_WINDOW_SCISSOR_TL_MASK \ + (PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK | \ + PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK | \ + PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) + +#define PA_SC_WINDOW_SCISSOR_TL(tl_x, tl_y, window_offset_disable) \ + ((tl_x << PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT) | \ + (tl_y << PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT) | \ + (window_offset_disable << PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT)) + +#define PA_SC_WINDOW_SCISSOR_TL_GET_TL_X(pa_sc_window_scissor_tl) \ + ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK) >> PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT) +#define PA_SC_WINDOW_SCISSOR_TL_GET_TL_Y(pa_sc_window_scissor_tl) \ + ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK) >> PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT) +#define PA_SC_WINDOW_SCISSOR_TL_GET_WINDOW_OFFSET_DISABLE(pa_sc_window_scissor_tl) \ + ((pa_sc_window_scissor_tl & PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) >> PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT) + +#define PA_SC_WINDOW_SCISSOR_TL_SET_TL_X(pa_sc_window_scissor_tl_reg, tl_x) \ + pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_TL_X_MASK) | (tl_x << PA_SC_WINDOW_SCISSOR_TL_TL_X_SHIFT) +#define PA_SC_WINDOW_SCISSOR_TL_SET_TL_Y(pa_sc_window_scissor_tl_reg, tl_y) \ + pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_TL_Y_MASK) | (tl_y << PA_SC_WINDOW_SCISSOR_TL_TL_Y_SHIFT) +#define PA_SC_WINDOW_SCISSOR_TL_SET_WINDOW_OFFSET_DISABLE(pa_sc_window_scissor_tl_reg, window_offset_disable) \ + pa_sc_window_scissor_tl_reg = (pa_sc_window_scissor_tl_reg & ~PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_MASK) | (window_offset_disable << PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_window_scissor_tl_t { + unsigned int tl_x : PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE; + unsigned int : 2; + unsigned int tl_y : PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE; + unsigned int : 1; + unsigned int window_offset_disable : PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE; + } pa_sc_window_scissor_tl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_window_scissor_tl_t { + unsigned int window_offset_disable : PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE_SIZE; + unsigned int : 1; + unsigned int tl_y : PA_SC_WINDOW_SCISSOR_TL_TL_Y_SIZE; + unsigned int : 2; + unsigned int tl_x : PA_SC_WINDOW_SCISSOR_TL_TL_X_SIZE; + } pa_sc_window_scissor_tl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_window_scissor_tl_t f; +} pa_sc_window_scissor_tl_u; + + +/* + * PA_SC_WINDOW_SCISSOR_BR struct + */ + +#define PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE 14 +#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE 14 + +#define PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT 0 +#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT 16 + +#define PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK 0x00003fff +#define PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK 0x3fff0000 + +#define PA_SC_WINDOW_SCISSOR_BR_MASK \ + (PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK | \ + PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) + +#define PA_SC_WINDOW_SCISSOR_BR(br_x, br_y) \ + ((br_x << PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT) | \ + (br_y << PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT)) + +#define PA_SC_WINDOW_SCISSOR_BR_GET_BR_X(pa_sc_window_scissor_br) \ + ((pa_sc_window_scissor_br & PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK) >> PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT) +#define PA_SC_WINDOW_SCISSOR_BR_GET_BR_Y(pa_sc_window_scissor_br) \ + ((pa_sc_window_scissor_br & PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) >> PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT) + +#define PA_SC_WINDOW_SCISSOR_BR_SET_BR_X(pa_sc_window_scissor_br_reg, br_x) \ + pa_sc_window_scissor_br_reg = (pa_sc_window_scissor_br_reg & ~PA_SC_WINDOW_SCISSOR_BR_BR_X_MASK) | (br_x << PA_SC_WINDOW_SCISSOR_BR_BR_X_SHIFT) +#define PA_SC_WINDOW_SCISSOR_BR_SET_BR_Y(pa_sc_window_scissor_br_reg, br_y) \ + pa_sc_window_scissor_br_reg = (pa_sc_window_scissor_br_reg & ~PA_SC_WINDOW_SCISSOR_BR_BR_Y_MASK) | (br_y << PA_SC_WINDOW_SCISSOR_BR_BR_Y_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_window_scissor_br_t { + unsigned int br_x : PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE; + unsigned int : 2; + unsigned int br_y : PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE; + unsigned int : 2; + } pa_sc_window_scissor_br_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_window_scissor_br_t { + unsigned int : 2; + unsigned int br_y : PA_SC_WINDOW_SCISSOR_BR_BR_Y_SIZE; + unsigned int : 2; + unsigned int br_x : PA_SC_WINDOW_SCISSOR_BR_BR_X_SIZE; + } pa_sc_window_scissor_br_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_window_scissor_br_t f; +} pa_sc_window_scissor_br_u; + + +/* + * PA_SC_SCREEN_SCISSOR_TL struct + */ + +#define PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE 15 +#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE 15 + +#define PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT 0 +#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT 16 + +#define PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK 0x00007fff +#define PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK 0x7fff0000 + +#define PA_SC_SCREEN_SCISSOR_TL_MASK \ + (PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK | \ + PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) + +#define PA_SC_SCREEN_SCISSOR_TL(tl_x, tl_y) \ + ((tl_x << PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT) | \ + (tl_y << PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT)) + +#define PA_SC_SCREEN_SCISSOR_TL_GET_TL_X(pa_sc_screen_scissor_tl) \ + ((pa_sc_screen_scissor_tl & PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK) >> PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT) +#define PA_SC_SCREEN_SCISSOR_TL_GET_TL_Y(pa_sc_screen_scissor_tl) \ + ((pa_sc_screen_scissor_tl & PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) >> PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT) + +#define PA_SC_SCREEN_SCISSOR_TL_SET_TL_X(pa_sc_screen_scissor_tl_reg, tl_x) \ + pa_sc_screen_scissor_tl_reg = (pa_sc_screen_scissor_tl_reg & ~PA_SC_SCREEN_SCISSOR_TL_TL_X_MASK) | (tl_x << PA_SC_SCREEN_SCISSOR_TL_TL_X_SHIFT) +#define PA_SC_SCREEN_SCISSOR_TL_SET_TL_Y(pa_sc_screen_scissor_tl_reg, tl_y) \ + pa_sc_screen_scissor_tl_reg = (pa_sc_screen_scissor_tl_reg & ~PA_SC_SCREEN_SCISSOR_TL_TL_Y_MASK) | (tl_y << PA_SC_SCREEN_SCISSOR_TL_TL_Y_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_screen_scissor_tl_t { + unsigned int tl_x : PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE; + unsigned int : 1; + unsigned int tl_y : PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE; + unsigned int : 1; + } pa_sc_screen_scissor_tl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_screen_scissor_tl_t { + unsigned int : 1; + unsigned int tl_y : PA_SC_SCREEN_SCISSOR_TL_TL_Y_SIZE; + unsigned int : 1; + unsigned int tl_x : PA_SC_SCREEN_SCISSOR_TL_TL_X_SIZE; + } pa_sc_screen_scissor_tl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_screen_scissor_tl_t f; +} pa_sc_screen_scissor_tl_u; + + +/* + * PA_SC_SCREEN_SCISSOR_BR struct + */ + +#define PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE 15 +#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE 15 + +#define PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT 0 +#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT 16 + +#define PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK 0x00007fff +#define PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK 0x7fff0000 + +#define PA_SC_SCREEN_SCISSOR_BR_MASK \ + (PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK | \ + PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) + +#define PA_SC_SCREEN_SCISSOR_BR(br_x, br_y) \ + ((br_x << PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT) | \ + (br_y << PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT)) + +#define PA_SC_SCREEN_SCISSOR_BR_GET_BR_X(pa_sc_screen_scissor_br) \ + ((pa_sc_screen_scissor_br & PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK) >> PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT) +#define PA_SC_SCREEN_SCISSOR_BR_GET_BR_Y(pa_sc_screen_scissor_br) \ + ((pa_sc_screen_scissor_br & PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) >> PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT) + +#define PA_SC_SCREEN_SCISSOR_BR_SET_BR_X(pa_sc_screen_scissor_br_reg, br_x) \ + pa_sc_screen_scissor_br_reg = (pa_sc_screen_scissor_br_reg & ~PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK) | (br_x << PA_SC_SCREEN_SCISSOR_BR_BR_X_SHIFT) +#define PA_SC_SCREEN_SCISSOR_BR_SET_BR_Y(pa_sc_screen_scissor_br_reg, br_y) \ + pa_sc_screen_scissor_br_reg = (pa_sc_screen_scissor_br_reg & ~PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK) | (br_y << PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_screen_scissor_br_t { + unsigned int br_x : PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE; + unsigned int : 1; + unsigned int br_y : PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE; + unsigned int : 1; + } pa_sc_screen_scissor_br_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_screen_scissor_br_t { + unsigned int : 1; + unsigned int br_y : PA_SC_SCREEN_SCISSOR_BR_BR_Y_SIZE; + unsigned int : 1; + unsigned int br_x : PA_SC_SCREEN_SCISSOR_BR_BR_X_SIZE; + } pa_sc_screen_scissor_br_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_screen_scissor_br_t f; +} pa_sc_screen_scissor_br_u; + + +/* + * PA_SC_VIZ_QUERY struct + */ + +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE 1 +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE 5 +#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE 1 + +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT 0 +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT 1 +#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT 7 + +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK 0x00000001 +#define PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK 0x0000003e +#define PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK 0x00000080 + +#define PA_SC_VIZ_QUERY_MASK \ + (PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK | \ + PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK | \ + PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) + +#define PA_SC_VIZ_QUERY(viz_query_ena, viz_query_id, kill_pix_post_early_z) \ + ((viz_query_ena << PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT) | \ + (viz_query_id << PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT) | \ + (kill_pix_post_early_z << PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT)) + +#define PA_SC_VIZ_QUERY_GET_VIZ_QUERY_ENA(pa_sc_viz_query) \ + ((pa_sc_viz_query & PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK) >> PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT) +#define PA_SC_VIZ_QUERY_GET_VIZ_QUERY_ID(pa_sc_viz_query) \ + ((pa_sc_viz_query & PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK) >> PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT) +#define PA_SC_VIZ_QUERY_GET_KILL_PIX_POST_EARLY_Z(pa_sc_viz_query) \ + ((pa_sc_viz_query & PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) >> PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT) + +#define PA_SC_VIZ_QUERY_SET_VIZ_QUERY_ENA(pa_sc_viz_query_reg, viz_query_ena) \ + pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_MASK) | (viz_query_ena << PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SHIFT) +#define PA_SC_VIZ_QUERY_SET_VIZ_QUERY_ID(pa_sc_viz_query_reg, viz_query_id) \ + pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_VIZ_QUERY_ID_MASK) | (viz_query_id << PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SHIFT) +#define PA_SC_VIZ_QUERY_SET_KILL_PIX_POST_EARLY_Z(pa_sc_viz_query_reg, kill_pix_post_early_z) \ + pa_sc_viz_query_reg = (pa_sc_viz_query_reg & ~PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_MASK) | (kill_pix_post_early_z << PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_viz_query_t { + unsigned int viz_query_ena : PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE; + unsigned int viz_query_id : PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE; + unsigned int : 1; + unsigned int kill_pix_post_early_z : PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE; + unsigned int : 24; + } pa_sc_viz_query_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_viz_query_t { + unsigned int : 24; + unsigned int kill_pix_post_early_z : PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z_SIZE; + unsigned int : 1; + unsigned int viz_query_id : PA_SC_VIZ_QUERY_VIZ_QUERY_ID_SIZE; + unsigned int viz_query_ena : PA_SC_VIZ_QUERY_VIZ_QUERY_ENA_SIZE; + } pa_sc_viz_query_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_viz_query_t f; +} pa_sc_viz_query_u; + + +/* + * PA_SC_VIZ_QUERY_STATUS struct + */ + +#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE 32 + +#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT 0 + +#define PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK 0xffffffff + +#define PA_SC_VIZ_QUERY_STATUS_MASK \ + (PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) + +#define PA_SC_VIZ_QUERY_STATUS(status_bits) \ + ((status_bits << PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT)) + +#define PA_SC_VIZ_QUERY_STATUS_GET_STATUS_BITS(pa_sc_viz_query_status) \ + ((pa_sc_viz_query_status & PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) >> PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT) + +#define PA_SC_VIZ_QUERY_STATUS_SET_STATUS_BITS(pa_sc_viz_query_status_reg, status_bits) \ + pa_sc_viz_query_status_reg = (pa_sc_viz_query_status_reg & ~PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_MASK) | (status_bits << PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_viz_query_status_t { + unsigned int status_bits : PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE; + } pa_sc_viz_query_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_viz_query_status_t { + unsigned int status_bits : PA_SC_VIZ_QUERY_STATUS_STATUS_BITS_SIZE; + } pa_sc_viz_query_status_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_viz_query_status_t f; +} pa_sc_viz_query_status_u; + + +/* + * PA_SC_LINE_STIPPLE_STATE struct + */ + +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE 4 +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE 8 + +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT 0 +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT 8 + +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK 0x0000000f +#define PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK 0x0000ff00 + +#define PA_SC_LINE_STIPPLE_STATE_MASK \ + (PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK | \ + PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) + +#define PA_SC_LINE_STIPPLE_STATE(current_ptr, current_count) \ + ((current_ptr << PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT) | \ + (current_count << PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT)) + +#define PA_SC_LINE_STIPPLE_STATE_GET_CURRENT_PTR(pa_sc_line_stipple_state) \ + ((pa_sc_line_stipple_state & PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK) >> PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT) +#define PA_SC_LINE_STIPPLE_STATE_GET_CURRENT_COUNT(pa_sc_line_stipple_state) \ + ((pa_sc_line_stipple_state & PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) >> PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT) + +#define PA_SC_LINE_STIPPLE_STATE_SET_CURRENT_PTR(pa_sc_line_stipple_state_reg, current_ptr) \ + pa_sc_line_stipple_state_reg = (pa_sc_line_stipple_state_reg & ~PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_MASK) | (current_ptr << PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SHIFT) +#define PA_SC_LINE_STIPPLE_STATE_SET_CURRENT_COUNT(pa_sc_line_stipple_state_reg, current_count) \ + pa_sc_line_stipple_state_reg = (pa_sc_line_stipple_state_reg & ~PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_MASK) | (current_count << PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_line_stipple_state_t { + unsigned int current_ptr : PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE; + unsigned int : 4; + unsigned int current_count : PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE; + unsigned int : 16; + } pa_sc_line_stipple_state_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_line_stipple_state_t { + unsigned int : 16; + unsigned int current_count : PA_SC_LINE_STIPPLE_STATE_CURRENT_COUNT_SIZE; + unsigned int : 4; + unsigned int current_ptr : PA_SC_LINE_STIPPLE_STATE_CURRENT_PTR_SIZE; + } pa_sc_line_stipple_state_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_line_stipple_state_t f; +} pa_sc_line_stipple_state_u; + + +/* + * PA_SC_PERFCOUNTER0_SELECT struct + */ + +#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define PA_SC_PERFCOUNTER0_SELECT_MASK \ + (PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define PA_SC_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define PA_SC_PERFCOUNTER0_SELECT_GET_PERF_SEL(pa_sc_perfcounter0_select) \ + ((pa_sc_perfcounter0_select & PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define PA_SC_PERFCOUNTER0_SELECT_SET_PERF_SEL(pa_sc_perfcounter0_select_reg, perf_sel) \ + pa_sc_perfcounter0_select_reg = (pa_sc_perfcounter0_select_reg & ~PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_select_t { + unsigned int perf_sel : PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } pa_sc_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : PA_SC_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } pa_sc_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_perfcounter0_select_t f; +} pa_sc_perfcounter0_select_u; + + +/* + * PA_SC_PERFCOUNTER0_LOW struct + */ + +#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define PA_SC_PERFCOUNTER0_LOW_MASK \ + (PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define PA_SC_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define PA_SC_PERFCOUNTER0_LOW_GET_PERF_COUNT(pa_sc_perfcounter0_low) \ + ((pa_sc_perfcounter0_low & PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define PA_SC_PERFCOUNTER0_LOW_SET_PERF_COUNT(pa_sc_perfcounter0_low_reg, perf_count) \ + pa_sc_perfcounter0_low_reg = (pa_sc_perfcounter0_low_reg & ~PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_low_t { + unsigned int perf_count : PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } pa_sc_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_low_t { + unsigned int perf_count : PA_SC_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } pa_sc_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_perfcounter0_low_t f; +} pa_sc_perfcounter0_low_u; + + +/* + * PA_SC_PERFCOUNTER0_HI struct + */ + +#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define PA_SC_PERFCOUNTER0_HI_MASK \ + (PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define PA_SC_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define PA_SC_PERFCOUNTER0_HI_GET_PERF_COUNT(pa_sc_perfcounter0_hi) \ + ((pa_sc_perfcounter0_hi & PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define PA_SC_PERFCOUNTER0_HI_SET_PERF_COUNT(pa_sc_perfcounter0_hi_reg, perf_count) \ + pa_sc_perfcounter0_hi_reg = (pa_sc_perfcounter0_hi_reg & ~PA_SC_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_hi_t { + unsigned int perf_count : PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } pa_sc_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : PA_SC_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } pa_sc_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_perfcounter0_hi_t f; +} pa_sc_perfcounter0_hi_u; + + +/* + * PA_CL_CNTL_STATUS struct + */ + +#define PA_CL_CNTL_STATUS_CL_BUSY_SIZE 1 + +#define PA_CL_CNTL_STATUS_CL_BUSY_SHIFT 31 + +#define PA_CL_CNTL_STATUS_CL_BUSY_MASK 0x80000000 + +#define PA_CL_CNTL_STATUS_MASK \ + (PA_CL_CNTL_STATUS_CL_BUSY_MASK) + +#define PA_CL_CNTL_STATUS(cl_busy) \ + ((cl_busy << PA_CL_CNTL_STATUS_CL_BUSY_SHIFT)) + +#define PA_CL_CNTL_STATUS_GET_CL_BUSY(pa_cl_cntl_status) \ + ((pa_cl_cntl_status & PA_CL_CNTL_STATUS_CL_BUSY_MASK) >> PA_CL_CNTL_STATUS_CL_BUSY_SHIFT) + +#define PA_CL_CNTL_STATUS_SET_CL_BUSY(pa_cl_cntl_status_reg, cl_busy) \ + pa_cl_cntl_status_reg = (pa_cl_cntl_status_reg & ~PA_CL_CNTL_STATUS_CL_BUSY_MASK) | (cl_busy << PA_CL_CNTL_STATUS_CL_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_cl_cntl_status_t { + unsigned int : 31; + unsigned int cl_busy : PA_CL_CNTL_STATUS_CL_BUSY_SIZE; + } pa_cl_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_cl_cntl_status_t { + unsigned int cl_busy : PA_CL_CNTL_STATUS_CL_BUSY_SIZE; + unsigned int : 31; + } pa_cl_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_cl_cntl_status_t f; +} pa_cl_cntl_status_u; + + +/* + * PA_SU_CNTL_STATUS struct + */ + +#define PA_SU_CNTL_STATUS_SU_BUSY_SIZE 1 + +#define PA_SU_CNTL_STATUS_SU_BUSY_SHIFT 31 + +#define PA_SU_CNTL_STATUS_SU_BUSY_MASK 0x80000000 + +#define PA_SU_CNTL_STATUS_MASK \ + (PA_SU_CNTL_STATUS_SU_BUSY_MASK) + +#define PA_SU_CNTL_STATUS(su_busy) \ + ((su_busy << PA_SU_CNTL_STATUS_SU_BUSY_SHIFT)) + +#define PA_SU_CNTL_STATUS_GET_SU_BUSY(pa_su_cntl_status) \ + ((pa_su_cntl_status & PA_SU_CNTL_STATUS_SU_BUSY_MASK) >> PA_SU_CNTL_STATUS_SU_BUSY_SHIFT) + +#define PA_SU_CNTL_STATUS_SET_SU_BUSY(pa_su_cntl_status_reg, su_busy) \ + pa_su_cntl_status_reg = (pa_su_cntl_status_reg & ~PA_SU_CNTL_STATUS_SU_BUSY_MASK) | (su_busy << PA_SU_CNTL_STATUS_SU_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_cntl_status_t { + unsigned int : 31; + unsigned int su_busy : PA_SU_CNTL_STATUS_SU_BUSY_SIZE; + } pa_su_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_cntl_status_t { + unsigned int su_busy : PA_SU_CNTL_STATUS_SU_BUSY_SIZE; + unsigned int : 31; + } pa_su_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_cntl_status_t f; +} pa_su_cntl_status_u; + + +/* + * PA_SC_CNTL_STATUS struct + */ + +#define PA_SC_CNTL_STATUS_SC_BUSY_SIZE 1 + +#define PA_SC_CNTL_STATUS_SC_BUSY_SHIFT 31 + +#define PA_SC_CNTL_STATUS_SC_BUSY_MASK 0x80000000 + +#define PA_SC_CNTL_STATUS_MASK \ + (PA_SC_CNTL_STATUS_SC_BUSY_MASK) + +#define PA_SC_CNTL_STATUS(sc_busy) \ + ((sc_busy << PA_SC_CNTL_STATUS_SC_BUSY_SHIFT)) + +#define PA_SC_CNTL_STATUS_GET_SC_BUSY(pa_sc_cntl_status) \ + ((pa_sc_cntl_status & PA_SC_CNTL_STATUS_SC_BUSY_MASK) >> PA_SC_CNTL_STATUS_SC_BUSY_SHIFT) + +#define PA_SC_CNTL_STATUS_SET_SC_BUSY(pa_sc_cntl_status_reg, sc_busy) \ + pa_sc_cntl_status_reg = (pa_sc_cntl_status_reg & ~PA_SC_CNTL_STATUS_SC_BUSY_MASK) | (sc_busy << PA_SC_CNTL_STATUS_SC_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_cntl_status_t { + unsigned int : 31; + unsigned int sc_busy : PA_SC_CNTL_STATUS_SC_BUSY_SIZE; + } pa_sc_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_cntl_status_t { + unsigned int sc_busy : PA_SC_CNTL_STATUS_SC_BUSY_SIZE; + unsigned int : 31; + } pa_sc_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_cntl_status_t f; +} pa_sc_cntl_status_u; + + +/* + * PA_SU_DEBUG_CNTL struct + */ + +#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE 5 + +#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT 0 + +#define PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK 0x0000001f + +#define PA_SU_DEBUG_CNTL_MASK \ + (PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) + +#define PA_SU_DEBUG_CNTL(su_debug_indx) \ + ((su_debug_indx << PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT)) + +#define PA_SU_DEBUG_CNTL_GET_SU_DEBUG_INDX(pa_su_debug_cntl) \ + ((pa_su_debug_cntl & PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) >> PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT) + +#define PA_SU_DEBUG_CNTL_SET_SU_DEBUG_INDX(pa_su_debug_cntl_reg, su_debug_indx) \ + pa_su_debug_cntl_reg = (pa_su_debug_cntl_reg & ~PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_MASK) | (su_debug_indx << PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_debug_cntl_t { + unsigned int su_debug_indx : PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE; + unsigned int : 27; + } pa_su_debug_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_debug_cntl_t { + unsigned int : 27; + unsigned int su_debug_indx : PA_SU_DEBUG_CNTL_SU_DEBUG_INDX_SIZE; + } pa_su_debug_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_debug_cntl_t f; +} pa_su_debug_cntl_u; + + +/* + * PA_SU_DEBUG_DATA struct + */ + +#define PA_SU_DEBUG_DATA_DATA_SIZE 32 + +#define PA_SU_DEBUG_DATA_DATA_SHIFT 0 + +#define PA_SU_DEBUG_DATA_DATA_MASK 0xffffffff + +#define PA_SU_DEBUG_DATA_MASK \ + (PA_SU_DEBUG_DATA_DATA_MASK) + +#define PA_SU_DEBUG_DATA(data) \ + ((data << PA_SU_DEBUG_DATA_DATA_SHIFT)) + +#define PA_SU_DEBUG_DATA_GET_DATA(pa_su_debug_data) \ + ((pa_su_debug_data & PA_SU_DEBUG_DATA_DATA_MASK) >> PA_SU_DEBUG_DATA_DATA_SHIFT) + +#define PA_SU_DEBUG_DATA_SET_DATA(pa_su_debug_data_reg, data) \ + pa_su_debug_data_reg = (pa_su_debug_data_reg & ~PA_SU_DEBUG_DATA_DATA_MASK) | (data << PA_SU_DEBUG_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_su_debug_data_t { + unsigned int data : PA_SU_DEBUG_DATA_DATA_SIZE; + } pa_su_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_su_debug_data_t { + unsigned int data : PA_SU_DEBUG_DATA_DATA_SIZE; + } pa_su_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_su_debug_data_t f; +} pa_su_debug_data_u; + + +/* + * CLIPPER_DEBUG_REG00 struct + */ + +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE 12 + +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT 0 +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT 1 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT 2 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT 3 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT 4 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT 5 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT 6 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT 7 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT 8 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT 9 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT 10 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT 11 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT 12 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT 13 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT 14 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT 15 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT 16 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT 17 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT 18 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT 19 +#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT 20 + +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK 0x00000001 +#define CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK 0x00000002 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK 0x00000004 +#define CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK 0x00000008 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK 0x00000010 +#define CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK 0x00000020 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK 0x00000040 +#define CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK 0x00000080 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK 0x00000100 +#define CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK 0x00000200 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK 0x00000400 +#define CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK 0x00000800 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK 0x00001000 +#define CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK 0x00002000 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK 0x00004000 +#define CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK 0x00008000 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK 0x00010000 +#define CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK 0x00020000 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK 0x00040000 +#define CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK 0x00080000 +#define CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK 0xfff00000 + +#define CLIPPER_DEBUG_REG00_MASK \ + (CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK | \ + CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK | \ + CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK | \ + CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) + +#define CLIPPER_DEBUG_REG00(clip_ga_bc_fifo_write, clip_ga_bc_fifo_full, clip_to_ga_fifo_write, clip_to_ga_fifo_full, primic_to_clprim_fifo_empty, primic_to_clprim_fifo_full, clip_to_outsm_fifo_empty, clip_to_outsm_fifo_full, vgt_to_clipp_fifo_empty, vgt_to_clipp_fifo_full, vgt_to_clips_fifo_empty, vgt_to_clips_fifo_full, clipcode_fifo_fifo_empty, clipcode_fifo_full, vte_out_clip_fifo_fifo_empty, vte_out_clip_fifo_fifo_full, vte_out_orig_fifo_fifo_empty, vte_out_orig_fifo_fifo_full, ccgen_to_clipcc_fifo_empty, ccgen_to_clipcc_fifo_full, always_zero) \ + ((clip_ga_bc_fifo_write << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT) | \ + (clip_ga_bc_fifo_full << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT) | \ + (clip_to_ga_fifo_write << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT) | \ + (clip_to_ga_fifo_full << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT) | \ + (primic_to_clprim_fifo_empty << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT) | \ + (primic_to_clprim_fifo_full << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT) | \ + (clip_to_outsm_fifo_empty << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT) | \ + (clip_to_outsm_fifo_full << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT) | \ + (vgt_to_clipp_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT) | \ + (vgt_to_clipp_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT) | \ + (vgt_to_clips_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT) | \ + (vgt_to_clips_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT) | \ + (clipcode_fifo_fifo_empty << CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT) | \ + (clipcode_fifo_full << CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT) | \ + (vte_out_clip_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT) | \ + (vte_out_clip_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT) | \ + (vte_out_orig_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT) | \ + (vte_out_orig_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT) | \ + (ccgen_to_clipcc_fifo_empty << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT) | \ + (ccgen_to_clipcc_fifo_full << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT) | \ + (always_zero << CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT)) + +#define CLIPPER_DEBUG_REG00_GET_clip_ga_bc_fifo_write(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK) >> CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_ga_bc_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_to_ga_fifo_write(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK) >> CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_to_ga_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_primic_to_clprim_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_primic_to_clprim_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_to_outsm_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clip_to_outsm_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vgt_to_clipp_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vgt_to_clipp_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vgt_to_clips_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vgt_to_clips_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clipcode_fifo_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_clipcode_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vte_out_clip_fifo_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vte_out_clip_fifo_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vte_out_orig_fifo_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_vte_out_orig_fifo_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_ccgen_to_clipcc_fifo_empty(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK) >> CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_ccgen_to_clipcc_fifo_full(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK) >> CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_GET_ALWAYS_ZERO(clipper_debug_reg00) \ + ((clipper_debug_reg00 & CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT) + +#define CLIPPER_DEBUG_REG00_SET_clip_ga_bc_fifo_write(clipper_debug_reg00_reg, clip_ga_bc_fifo_write) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_MASK) | (clip_ga_bc_fifo_write << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_ga_bc_fifo_full(clipper_debug_reg00_reg, clip_ga_bc_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_MASK) | (clip_ga_bc_fifo_full << CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_to_ga_fifo_write(clipper_debug_reg00_reg, clip_to_ga_fifo_write) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_MASK) | (clip_to_ga_fifo_write << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_to_ga_fifo_full(clipper_debug_reg00_reg, clip_to_ga_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_MASK) | (clip_to_ga_fifo_full << CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_primic_to_clprim_fifo_empty(clipper_debug_reg00_reg, primic_to_clprim_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_MASK) | (primic_to_clprim_fifo_empty << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_primic_to_clprim_fifo_full(clipper_debug_reg00_reg, primic_to_clprim_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_MASK) | (primic_to_clprim_fifo_full << CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_to_outsm_fifo_empty(clipper_debug_reg00_reg, clip_to_outsm_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_MASK) | (clip_to_outsm_fifo_empty << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clip_to_outsm_fifo_full(clipper_debug_reg00_reg, clip_to_outsm_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_MASK) | (clip_to_outsm_fifo_full << CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vgt_to_clipp_fifo_empty(clipper_debug_reg00_reg, vgt_to_clipp_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_MASK) | (vgt_to_clipp_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vgt_to_clipp_fifo_full(clipper_debug_reg00_reg, vgt_to_clipp_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_MASK) | (vgt_to_clipp_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vgt_to_clips_fifo_empty(clipper_debug_reg00_reg, vgt_to_clips_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_MASK) | (vgt_to_clips_fifo_empty << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vgt_to_clips_fifo_full(clipper_debug_reg00_reg, vgt_to_clips_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_MASK) | (vgt_to_clips_fifo_full << CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clipcode_fifo_fifo_empty(clipper_debug_reg00_reg, clipcode_fifo_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_MASK) | (clipcode_fifo_fifo_empty << CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_clipcode_fifo_full(clipper_debug_reg00_reg, clipcode_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_clipcode_fifo_full_MASK) | (clipcode_fifo_full << CLIPPER_DEBUG_REG00_clipcode_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vte_out_clip_fifo_fifo_empty(clipper_debug_reg00_reg, vte_out_clip_fifo_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_MASK) | (vte_out_clip_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vte_out_clip_fifo_fifo_full(clipper_debug_reg00_reg, vte_out_clip_fifo_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_MASK) | (vte_out_clip_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vte_out_orig_fifo_fifo_empty(clipper_debug_reg00_reg, vte_out_orig_fifo_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_MASK) | (vte_out_orig_fifo_fifo_empty << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_vte_out_orig_fifo_fifo_full(clipper_debug_reg00_reg, vte_out_orig_fifo_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_MASK) | (vte_out_orig_fifo_fifo_full << CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_ccgen_to_clipcc_fifo_empty(clipper_debug_reg00_reg, ccgen_to_clipcc_fifo_empty) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_MASK) | (ccgen_to_clipcc_fifo_empty << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_ccgen_to_clipcc_fifo_full(clipper_debug_reg00_reg, ccgen_to_clipcc_fifo_full) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_MASK) | (ccgen_to_clipcc_fifo_full << CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG00_SET_ALWAYS_ZERO(clipper_debug_reg00_reg, always_zero) \ + clipper_debug_reg00_reg = (clipper_debug_reg00_reg & ~CLIPPER_DEBUG_REG00_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg00_t { + unsigned int clip_ga_bc_fifo_write : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE; + unsigned int clip_ga_bc_fifo_full : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE; + unsigned int clip_to_ga_fifo_write : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE; + unsigned int clip_to_ga_fifo_full : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE; + unsigned int primic_to_clprim_fifo_empty : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE; + unsigned int primic_to_clprim_fifo_full : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE; + unsigned int clip_to_outsm_fifo_empty : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE; + unsigned int clip_to_outsm_fifo_full : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE; + unsigned int vgt_to_clipp_fifo_empty : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE; + unsigned int vgt_to_clipp_fifo_full : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE; + unsigned int vgt_to_clips_fifo_empty : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE; + unsigned int vgt_to_clips_fifo_full : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE; + unsigned int clipcode_fifo_fifo_empty : CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE; + unsigned int clipcode_fifo_full : CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE; + unsigned int vte_out_clip_fifo_fifo_empty : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE; + unsigned int vte_out_clip_fifo_fifo_full : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE; + unsigned int vte_out_orig_fifo_fifo_empty : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE; + unsigned int vte_out_orig_fifo_fifo_full : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE; + unsigned int ccgen_to_clipcc_fifo_empty : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE; + unsigned int ccgen_to_clipcc_fifo_full : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE; + unsigned int always_zero : CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE; + } clipper_debug_reg00_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg00_t { + unsigned int always_zero : CLIPPER_DEBUG_REG00_ALWAYS_ZERO_SIZE; + unsigned int ccgen_to_clipcc_fifo_full : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_full_SIZE; + unsigned int ccgen_to_clipcc_fifo_empty : CLIPPER_DEBUG_REG00_ccgen_to_clipcc_fifo_empty_SIZE; + unsigned int vte_out_orig_fifo_fifo_full : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_full_SIZE; + unsigned int vte_out_orig_fifo_fifo_empty : CLIPPER_DEBUG_REG00_vte_out_orig_fifo_fifo_empty_SIZE; + unsigned int vte_out_clip_fifo_fifo_full : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_full_SIZE; + unsigned int vte_out_clip_fifo_fifo_empty : CLIPPER_DEBUG_REG00_vte_out_clip_fifo_fifo_empty_SIZE; + unsigned int clipcode_fifo_full : CLIPPER_DEBUG_REG00_clipcode_fifo_full_SIZE; + unsigned int clipcode_fifo_fifo_empty : CLIPPER_DEBUG_REG00_clipcode_fifo_fifo_empty_SIZE; + unsigned int vgt_to_clips_fifo_full : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_full_SIZE; + unsigned int vgt_to_clips_fifo_empty : CLIPPER_DEBUG_REG00_vgt_to_clips_fifo_empty_SIZE; + unsigned int vgt_to_clipp_fifo_full : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_full_SIZE; + unsigned int vgt_to_clipp_fifo_empty : CLIPPER_DEBUG_REG00_vgt_to_clipp_fifo_empty_SIZE; + unsigned int clip_to_outsm_fifo_full : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_full_SIZE; + unsigned int clip_to_outsm_fifo_empty : CLIPPER_DEBUG_REG00_clip_to_outsm_fifo_empty_SIZE; + unsigned int primic_to_clprim_fifo_full : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_full_SIZE; + unsigned int primic_to_clprim_fifo_empty : CLIPPER_DEBUG_REG00_primic_to_clprim_fifo_empty_SIZE; + unsigned int clip_to_ga_fifo_full : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_full_SIZE; + unsigned int clip_to_ga_fifo_write : CLIPPER_DEBUG_REG00_clip_to_ga_fifo_write_SIZE; + unsigned int clip_ga_bc_fifo_full : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_full_SIZE; + unsigned int clip_ga_bc_fifo_write : CLIPPER_DEBUG_REG00_clip_ga_bc_fifo_write_SIZE; + } clipper_debug_reg00_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg00_t f; +} clipper_debug_reg00_u; + + +/* + * CLIPPER_DEBUG_REG01 struct + */ + +#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE 3 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE 4 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE 4 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE 4 +#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE 3 +#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE 2 +#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE 8 + +#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT 0 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT 1 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT 2 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT 5 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT 6 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT 7 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT 11 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT 15 +#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT 19 +#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT 22 +#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT 24 + +#define CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK 0x00000001 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK 0x00000002 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK 0x0000001c +#define CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK 0x00000020 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK 0x00000040 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK 0x00000780 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK 0x00007800 +#define CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK 0x00078000 +#define CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK 0x00380000 +#define CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK 0x00c00000 +#define CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK 0xff000000 + +#define CLIPPER_DEBUG_REG01_MASK \ + (CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK | \ + CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK | \ + CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK | \ + CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK | \ + CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) + +#define CLIPPER_DEBUG_REG01(clip_to_outsm_end_of_packet, clip_to_outsm_first_prim_of_slot, clip_to_outsm_deallocate_slot, clip_to_outsm_clipped_prim, clip_to_outsm_null_primitive, clip_to_outsm_vertex_store_indx_2, clip_to_outsm_vertex_store_indx_1, clip_to_outsm_vertex_store_indx_0, clip_vert_vte_valid, vte_out_clip_rd_vertex_store_indx, always_zero) \ + ((clip_to_outsm_end_of_packet << CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT) | \ + (clip_to_outsm_first_prim_of_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT) | \ + (clip_to_outsm_deallocate_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT) | \ + (clip_to_outsm_clipped_prim << CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT) | \ + (clip_to_outsm_null_primitive << CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT) | \ + (clip_to_outsm_vertex_store_indx_2 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT) | \ + (clip_to_outsm_vertex_store_indx_1 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT) | \ + (clip_to_outsm_vertex_store_indx_0 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT) | \ + (clip_vert_vte_valid << CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT) | \ + (vte_out_clip_rd_vertex_store_indx << CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT) | \ + (always_zero << CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT)) + +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_end_of_packet(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_first_prim_of_slot(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_deallocate_slot(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_clipped_prim(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_null_primitive(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_2(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_1(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_to_outsm_vertex_store_indx_0(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_clip_vert_vte_valid(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK) >> CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_vte_out_clip_rd_vertex_store_indx(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK) >> CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT) +#define CLIPPER_DEBUG_REG01_GET_ALWAYS_ZERO(clipper_debug_reg01) \ + ((clipper_debug_reg01 & CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT) + +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_end_of_packet(clipper_debug_reg01_reg, clip_to_outsm_end_of_packet) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_MASK) | (clip_to_outsm_end_of_packet << CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_first_prim_of_slot(clipper_debug_reg01_reg, clip_to_outsm_first_prim_of_slot) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_MASK) | (clip_to_outsm_first_prim_of_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_deallocate_slot(clipper_debug_reg01_reg, clip_to_outsm_deallocate_slot) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_MASK) | (clip_to_outsm_deallocate_slot << CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_clipped_prim(clipper_debug_reg01_reg, clip_to_outsm_clipped_prim) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_MASK) | (clip_to_outsm_clipped_prim << CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_null_primitive(clipper_debug_reg01_reg, clip_to_outsm_null_primitive) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_MASK) | (clip_to_outsm_null_primitive << CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_2(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_2) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_MASK) | (clip_to_outsm_vertex_store_indx_2 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_1(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_1) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_MASK) | (clip_to_outsm_vertex_store_indx_1 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_to_outsm_vertex_store_indx_0(clipper_debug_reg01_reg, clip_to_outsm_vertex_store_indx_0) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_MASK) | (clip_to_outsm_vertex_store_indx_0 << CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_clip_vert_vte_valid(clipper_debug_reg01_reg, clip_vert_vte_valid) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_clip_vert_vte_valid_MASK) | (clip_vert_vte_valid << CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_vte_out_clip_rd_vertex_store_indx(clipper_debug_reg01_reg, vte_out_clip_rd_vertex_store_indx) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_MASK) | (vte_out_clip_rd_vertex_store_indx << CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SHIFT) +#define CLIPPER_DEBUG_REG01_SET_ALWAYS_ZERO(clipper_debug_reg01_reg, always_zero) \ + clipper_debug_reg01_reg = (clipper_debug_reg01_reg & ~CLIPPER_DEBUG_REG01_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg01_t { + unsigned int clip_to_outsm_end_of_packet : CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE; + unsigned int clip_to_outsm_first_prim_of_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE; + unsigned int clip_to_outsm_deallocate_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE; + unsigned int clip_to_outsm_clipped_prim : CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE; + unsigned int clip_to_outsm_null_primitive : CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_2 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_1 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_0 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE; + unsigned int clip_vert_vte_valid : CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE; + unsigned int vte_out_clip_rd_vertex_store_indx : CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE; + unsigned int always_zero : CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE; + } clipper_debug_reg01_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg01_t { + unsigned int always_zero : CLIPPER_DEBUG_REG01_ALWAYS_ZERO_SIZE; + unsigned int vte_out_clip_rd_vertex_store_indx : CLIPPER_DEBUG_REG01_vte_out_clip_rd_vertex_store_indx_SIZE; + unsigned int clip_vert_vte_valid : CLIPPER_DEBUG_REG01_clip_vert_vte_valid_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_0 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_0_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_1 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_1_SIZE; + unsigned int clip_to_outsm_vertex_store_indx_2 : CLIPPER_DEBUG_REG01_clip_to_outsm_vertex_store_indx_2_SIZE; + unsigned int clip_to_outsm_null_primitive : CLIPPER_DEBUG_REG01_clip_to_outsm_null_primitive_SIZE; + unsigned int clip_to_outsm_clipped_prim : CLIPPER_DEBUG_REG01_clip_to_outsm_clipped_prim_SIZE; + unsigned int clip_to_outsm_deallocate_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_deallocate_slot_SIZE; + unsigned int clip_to_outsm_first_prim_of_slot : CLIPPER_DEBUG_REG01_clip_to_outsm_first_prim_of_slot_SIZE; + unsigned int clip_to_outsm_end_of_packet : CLIPPER_DEBUG_REG01_clip_to_outsm_end_of_packet_SIZE; + } clipper_debug_reg01_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg01_t f; +} clipper_debug_reg01_u; + + +/* + * CLIPPER_DEBUG_REG02 struct + */ + +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE 21 +#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE 3 +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE 7 +#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE 1 + +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT 0 +#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT 21 +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT 24 +#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT 31 + +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK 0x001fffff +#define CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00e00000 +#define CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK 0x7f000000 +#define CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000 + +#define CLIPPER_DEBUG_REG02_MASK \ + (CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK | \ + CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK | \ + CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) + +#define CLIPPER_DEBUG_REG02(always_zero1, clipsm0_clip_to_clipga_clip_to_outsm_cnt, always_zero0, clipsm0_clprim_to_clip_prim_valid) \ + ((always_zero1 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT) | \ + (clipsm0_clip_to_clipga_clip_to_outsm_cnt << CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT) | \ + (clipsm0_clprim_to_clip_prim_valid << CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT)) + +#define CLIPPER_DEBUG_REG02_GET_ALWAYS_ZERO1(clipper_debug_reg02) \ + ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG02_GET_clipsm0_clip_to_clipga_clip_to_outsm_cnt(clipper_debug_reg02) \ + ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK) >> CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT) +#define CLIPPER_DEBUG_REG02_GET_ALWAYS_ZERO0(clipper_debug_reg02) \ + ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG02_GET_clipsm0_clprim_to_clip_prim_valid(clipper_debug_reg02) \ + ((clipper_debug_reg02 & CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) >> CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT) + +#define CLIPPER_DEBUG_REG02_SET_ALWAYS_ZERO1(clipper_debug_reg02_reg, always_zero1) \ + clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG02_SET_clipsm0_clip_to_clipga_clip_to_outsm_cnt(clipper_debug_reg02_reg, clipsm0_clip_to_clipga_clip_to_outsm_cnt) \ + clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK) | (clipsm0_clip_to_clipga_clip_to_outsm_cnt << CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SHIFT) +#define CLIPPER_DEBUG_REG02_SET_ALWAYS_ZERO0(clipper_debug_reg02_reg, always_zero0) \ + clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG02_SET_clipsm0_clprim_to_clip_prim_valid(clipper_debug_reg02_reg, clipsm0_clprim_to_clip_prim_valid) \ + clipper_debug_reg02_reg = (clipper_debug_reg02_reg & ~CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_MASK) | (clipsm0_clprim_to_clip_prim_valid << CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg02_t { + unsigned int always_zero1 : CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clprim_to_clip_prim_valid : CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE; + } clipper_debug_reg02_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg02_t { + unsigned int clipsm0_clprim_to_clip_prim_valid : CLIPPER_DEBUG_REG02_clipsm0_clprim_to_clip_prim_valid_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG02_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clip_to_clipga_clip_to_outsm_cnt : CLIPPER_DEBUG_REG02_clipsm0_clip_to_clipga_clip_to_outsm_cnt_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG02_ALWAYS_ZERO1_SIZE; + } clipper_debug_reg02_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg02_t f; +} clipper_debug_reg02_u; + + +/* + * CLIPPER_DEBUG_REG03 struct + */ + +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE 3 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE 1 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE 3 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE 1 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE 12 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE 6 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE 6 + +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT 0 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT 3 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT 4 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT 7 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT 8 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT 20 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT 26 + +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK 0x00000007 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK 0x00000008 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK 0x00000070 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK 0x00000080 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK 0x000fff00 +#define CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK 0x03f00000 +#define CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK 0xfc000000 + +#define CLIPPER_DEBUG_REG03_MASK \ + (CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK | \ + CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK | \ + CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK | \ + CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK | \ + CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG03(always_zero3, clipsm0_clprim_to_clip_clip_primitive, always_zero2, clipsm0_clprim_to_clip_null_primitive, always_zero1, clipsm0_clprim_to_clip_clip_code_or, always_zero0) \ + ((always_zero3 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT) | \ + (clipsm0_clprim_to_clip_clip_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT) | \ + (clipsm0_clprim_to_clip_null_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT) | \ + (clipsm0_clprim_to_clip_clip_code_or << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO3(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_clip_primitive(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO2(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_null_primitive(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO1(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_clipsm0_clprim_to_clip_clip_code_or(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK) >> CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT) +#define CLIPPER_DEBUG_REG03_GET_ALWAYS_ZERO0(clipper_debug_reg03) \ + ((clipper_debug_reg03 & CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO3(clipper_debug_reg03_reg, always_zero3) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_clip_primitive(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_clip_primitive) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_MASK) | (clipsm0_clprim_to_clip_clip_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO2(clipper_debug_reg03_reg, always_zero2) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_null_primitive(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_null_primitive) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_MASK) | (clipsm0_clprim_to_clip_null_primitive << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO1(clipper_debug_reg03_reg, always_zero1) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_clipsm0_clprim_to_clip_clip_code_or(clipper_debug_reg03_reg, clipsm0_clprim_to_clip_clip_code_or) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_MASK) | (clipsm0_clprim_to_clip_clip_code_or << CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SHIFT) +#define CLIPPER_DEBUG_REG03_SET_ALWAYS_ZERO0(clipper_debug_reg03_reg, always_zero0) \ + clipper_debug_reg03_reg = (clipper_debug_reg03_reg & ~CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg03_t { + unsigned int always_zero3 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE; + unsigned int clipsm0_clprim_to_clip_clip_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_null_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_clip_code_or : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg03_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg03_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clprim_to_clip_clip_code_or : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_code_or_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_null_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_null_primitive_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_clip_primitive : CLIPPER_DEBUG_REG03_clipsm0_clprim_to_clip_clip_primitive_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG03_ALWAYS_ZERO3_SIZE; + } clipper_debug_reg03_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg03_t f; +} clipper_debug_reg03_u; + + +/* + * CLIPPER_DEBUG_REG04 struct + */ + +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE 3 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE 1 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE 3 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE 1 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE 24 + +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT 0 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT 3 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT 4 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT 7 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT 8 + +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK 0x00000007 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x00000008 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK 0x00000070 +#define CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK 0x00000080 +#define CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK 0xffffff00 + +#define CLIPPER_DEBUG_REG04_MASK \ + (CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK | \ + CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK | \ + CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG04(always_zero2, clipsm0_clprim_to_clip_first_prim_of_slot, always_zero1, clipsm0_clprim_to_clip_event, always_zero0) \ + ((always_zero2 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT) | \ + (clipsm0_clprim_to_clip_first_prim_of_slot << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT) | \ + (clipsm0_clprim_to_clip_event << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO2(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG04_GET_clipsm0_clprim_to_clip_first_prim_of_slot(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO1(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG04_GET_clipsm0_clprim_to_clip_event(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK) >> CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT) +#define CLIPPER_DEBUG_REG04_GET_ALWAYS_ZERO0(clipper_debug_reg04) \ + ((clipper_debug_reg04 & CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO2(clipper_debug_reg04_reg, always_zero2) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG04_SET_clipsm0_clprim_to_clip_first_prim_of_slot(clipper_debug_reg04_reg, clipsm0_clprim_to_clip_first_prim_of_slot) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_MASK) | (clipsm0_clprim_to_clip_first_prim_of_slot << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO1(clipper_debug_reg04_reg, always_zero1) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG04_SET_clipsm0_clprim_to_clip_event(clipper_debug_reg04_reg, clipsm0_clprim_to_clip_event) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_MASK) | (clipsm0_clprim_to_clip_event << CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SHIFT) +#define CLIPPER_DEBUG_REG04_SET_ALWAYS_ZERO0(clipper_debug_reg04_reg, always_zero0) \ + clipper_debug_reg04_reg = (clipper_debug_reg04_reg & ~CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg04_t { + unsigned int always_zero2 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_event : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg04_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg04_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clprim_to_clip_event : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_event_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_first_prim_of_slot : CLIPPER_DEBUG_REG04_clipsm0_clprim_to_clip_first_prim_of_slot_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG04_ALWAYS_ZERO2_SIZE; + } clipper_debug_reg04_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg04_t f; +} clipper_debug_reg04_u; + + +/* + * CLIPPER_DEBUG_REG05 struct + */ + +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE 1 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE 2 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE 3 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE 6 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE 4 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE 2 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE 4 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE 2 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE 4 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE 4 + +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT 0 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT 1 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT 3 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT 6 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT 12 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT 16 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT 18 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT 22 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT 24 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT 28 + +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK 0x00000001 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK 0x00000006 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK 0x00000038 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK 0x00000fc0 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0000f000 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK 0x00030000 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x003c0000 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK 0x00c00000 +#define CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x0f000000 +#define CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK 0xf0000000 + +#define CLIPPER_DEBUG_REG05_MASK \ + (CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK | \ + CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK | \ + CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK | \ + CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK | \ + CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG05(clipsm0_clprim_to_clip_state_var_indx, always_zero3, clipsm0_clprim_to_clip_deallocate_slot, clipsm0_clprim_to_clip_event_id, clipsm0_clprim_to_clip_vertex_store_indx_2, always_zero2, clipsm0_clprim_to_clip_vertex_store_indx_1, always_zero1, clipsm0_clprim_to_clip_vertex_store_indx_0, always_zero0) \ + ((clipsm0_clprim_to_clip_state_var_indx << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT) | \ + (always_zero3 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT) | \ + (clipsm0_clprim_to_clip_deallocate_slot << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT) | \ + (clipsm0_clprim_to_clip_event_id << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT) | \ + (clipsm0_clprim_to_clip_vertex_store_indx_2 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT) | \ + (clipsm0_clprim_to_clip_vertex_store_indx_1 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT) | \ + (clipsm0_clprim_to_clip_vertex_store_indx_0 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_state_var_indx(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO3(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_deallocate_slot(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_event_id(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_2(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO2(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_1(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO1(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_clipsm0_clprim_to_clip_vertex_store_indx_0(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG05_GET_ALWAYS_ZERO0(clipper_debug_reg05) \ + ((clipper_debug_reg05 & CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_state_var_indx(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_state_var_indx) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_MASK) | (clipsm0_clprim_to_clip_state_var_indx << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO3(clipper_debug_reg05_reg, always_zero3) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_deallocate_slot(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_deallocate_slot) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_MASK) | (clipsm0_clprim_to_clip_deallocate_slot << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_event_id(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_event_id) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_MASK) | (clipsm0_clprim_to_clip_event_id << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_2(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_2) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_2 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO2(clipper_debug_reg05_reg, always_zero2) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_1(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_1) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_1 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO1(clipper_debug_reg05_reg, always_zero1) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_clipsm0_clprim_to_clip_vertex_store_indx_0(clipper_debug_reg05_reg, clipsm0_clprim_to_clip_vertex_store_indx_0) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_MASK) | (clipsm0_clprim_to_clip_vertex_store_indx_0 << CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG05_SET_ALWAYS_ZERO0(clipper_debug_reg05_reg, always_zero0) \ + clipper_debug_reg05_reg = (clipper_debug_reg05_reg & ~CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg05_t { + unsigned int clipsm0_clprim_to_clip_state_var_indx : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE; + unsigned int clipsm0_clprim_to_clip_deallocate_slot : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE; + unsigned int clipsm0_clprim_to_clip_event_id : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg05_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg05_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO0_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_0 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_0_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO1_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_1 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_1_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO2_SIZE; + unsigned int clipsm0_clprim_to_clip_vertex_store_indx_2 : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_vertex_store_indx_2_SIZE; + unsigned int clipsm0_clprim_to_clip_event_id : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_event_id_SIZE; + unsigned int clipsm0_clprim_to_clip_deallocate_slot : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_deallocate_slot_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG05_ALWAYS_ZERO3_SIZE; + unsigned int clipsm0_clprim_to_clip_state_var_indx : CLIPPER_DEBUG_REG05_clipsm0_clprim_to_clip_state_var_indx_SIZE; + } clipper_debug_reg05_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg05_t f; +} clipper_debug_reg05_u; + + +/* + * CLIPPER_DEBUG_REG09 struct + */ + +#define CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE 1 +#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE 1 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE 4 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE 2 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE 4 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE 2 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE 4 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE 2 +#define CLIPPER_DEBUG_REG09_prim_back_valid_SIZE 1 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE 4 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE 2 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE 1 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE 1 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE 2 + +#define CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT 0 +#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT 1 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT 2 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT 6 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT 8 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT 12 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT 14 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT 18 +#define CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT 20 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT 21 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT 25 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT 27 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT 28 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT 29 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT 30 + +#define CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK 0x00000001 +#define CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK 0x00000002 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK 0x0000003c +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK 0x000000c0 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK 0x00000f00 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK 0x00003000 +#define CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK 0x0003c000 +#define CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK 0x000c0000 +#define CLIPPER_DEBUG_REG09_prim_back_valid_MASK 0x00100000 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK 0x01e00000 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK 0x06000000 +#define CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK 0x08000000 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK 0x10000000 +#define CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK 0x20000000 +#define CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK 0xc0000000 + +#define CLIPPER_DEBUG_REG09_MASK \ + (CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK | \ + CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK | \ + CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK | \ + CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK | \ + CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK | \ + CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK | \ + CLIPPER_DEBUG_REG09_prim_back_valid_MASK | \ + CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK | \ + CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK | \ + CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK | \ + CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK | \ + CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) + +#define CLIPPER_DEBUG_REG09(clprim_in_back_event, outputclprimtoclip_null_primitive, clprim_in_back_vertex_store_indx_2, always_zero2, clprim_in_back_vertex_store_indx_1, always_zero1, clprim_in_back_vertex_store_indx_0, always_zero0, prim_back_valid, clip_priority_seq_indx_out_cnt, outsm_clr_rd_orig_vertices, outsm_clr_rd_clipsm_wait, outsm_clr_fifo_empty, outsm_clr_fifo_full, clip_priority_seq_indx_load) \ + ((clprim_in_back_event << CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT) | \ + (outputclprimtoclip_null_primitive << CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT) | \ + (clprim_in_back_vertex_store_indx_2 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT) | \ + (clprim_in_back_vertex_store_indx_1 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT) | \ + (clprim_in_back_vertex_store_indx_0 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT) | \ + (prim_back_valid << CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT) | \ + (clip_priority_seq_indx_out_cnt << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT) | \ + (outsm_clr_rd_orig_vertices << CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT) | \ + (outsm_clr_rd_clipsm_wait << CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT) | \ + (outsm_clr_fifo_empty << CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT) | \ + (outsm_clr_fifo_full << CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT) | \ + (clip_priority_seq_indx_load << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT)) + +#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_event(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outputclprimtoclip_null_primitive(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK) >> CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_2(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO2(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_1(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO1(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clprim_in_back_vertex_store_indx_0(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_ALWAYS_ZERO0(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_prim_back_valid(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_prim_back_valid_MASK) >> CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clip_priority_seq_indx_out_cnt(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK) >> CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outsm_clr_rd_orig_vertices(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outsm_clr_rd_clipsm_wait(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outsm_clr_fifo_empty(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_outsm_clr_fifo_full(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK) >> CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG09_GET_clip_priority_seq_indx_load(clipper_debug_reg09) \ + ((clipper_debug_reg09 & CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) >> CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT) + +#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_event(clipper_debug_reg09_reg, clprim_in_back_event) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_event_MASK) | (clprim_in_back_event << CLIPPER_DEBUG_REG09_clprim_in_back_event_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outputclprimtoclip_null_primitive(clipper_debug_reg09_reg, outputclprimtoclip_null_primitive) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_MASK) | (outputclprimtoclip_null_primitive << CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_2(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_2) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_MASK) | (clprim_in_back_vertex_store_indx_2 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO2(clipper_debug_reg09_reg, always_zero2) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_1(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_1) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_MASK) | (clprim_in_back_vertex_store_indx_1 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO1(clipper_debug_reg09_reg, always_zero1) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clprim_in_back_vertex_store_indx_0(clipper_debug_reg09_reg, clprim_in_back_vertex_store_indx_0) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_MASK) | (clprim_in_back_vertex_store_indx_0 << CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_ALWAYS_ZERO0(clipper_debug_reg09_reg, always_zero0) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_prim_back_valid(clipper_debug_reg09_reg, prim_back_valid) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_prim_back_valid_MASK) | (prim_back_valid << CLIPPER_DEBUG_REG09_prim_back_valid_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clip_priority_seq_indx_out_cnt(clipper_debug_reg09_reg, clip_priority_seq_indx_out_cnt) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_MASK) | (clip_priority_seq_indx_out_cnt << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outsm_clr_rd_orig_vertices(clipper_debug_reg09_reg, outsm_clr_rd_orig_vertices) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_MASK) | (outsm_clr_rd_orig_vertices << CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outsm_clr_rd_clipsm_wait(clipper_debug_reg09_reg, outsm_clr_rd_clipsm_wait) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_MASK) | (outsm_clr_rd_clipsm_wait << CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outsm_clr_fifo_empty(clipper_debug_reg09_reg, outsm_clr_fifo_empty) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_MASK) | (outsm_clr_fifo_empty << CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_outsm_clr_fifo_full(clipper_debug_reg09_reg, outsm_clr_fifo_full) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_MASK) | (outsm_clr_fifo_full << CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SHIFT) +#define CLIPPER_DEBUG_REG09_SET_clip_priority_seq_indx_load(clipper_debug_reg09_reg, clip_priority_seq_indx_load) \ + clipper_debug_reg09_reg = (clipper_debug_reg09_reg & ~CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_MASK) | (clip_priority_seq_indx_load << CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg09_t { + unsigned int clprim_in_back_event : CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE; + unsigned int outputclprimtoclip_null_primitive : CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE; + unsigned int clprim_in_back_vertex_store_indx_2 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE; + unsigned int clprim_in_back_vertex_store_indx_1 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE; + unsigned int clprim_in_back_vertex_store_indx_0 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE; + unsigned int prim_back_valid : CLIPPER_DEBUG_REG09_prim_back_valid_SIZE; + unsigned int clip_priority_seq_indx_out_cnt : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE; + unsigned int outsm_clr_rd_orig_vertices : CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE; + unsigned int outsm_clr_rd_clipsm_wait : CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE; + unsigned int outsm_clr_fifo_empty : CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE; + unsigned int outsm_clr_fifo_full : CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE; + unsigned int clip_priority_seq_indx_load : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE; + } clipper_debug_reg09_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg09_t { + unsigned int clip_priority_seq_indx_load : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_load_SIZE; + unsigned int outsm_clr_fifo_full : CLIPPER_DEBUG_REG09_outsm_clr_fifo_full_SIZE; + unsigned int outsm_clr_fifo_empty : CLIPPER_DEBUG_REG09_outsm_clr_fifo_empty_SIZE; + unsigned int outsm_clr_rd_clipsm_wait : CLIPPER_DEBUG_REG09_outsm_clr_rd_clipsm_wait_SIZE; + unsigned int outsm_clr_rd_orig_vertices : CLIPPER_DEBUG_REG09_outsm_clr_rd_orig_vertices_SIZE; + unsigned int clip_priority_seq_indx_out_cnt : CLIPPER_DEBUG_REG09_clip_priority_seq_indx_out_cnt_SIZE; + unsigned int prim_back_valid : CLIPPER_DEBUG_REG09_prim_back_valid_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO0_SIZE; + unsigned int clprim_in_back_vertex_store_indx_0 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_0_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO1_SIZE; + unsigned int clprim_in_back_vertex_store_indx_1 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_1_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG09_ALWAYS_ZERO2_SIZE; + unsigned int clprim_in_back_vertex_store_indx_2 : CLIPPER_DEBUG_REG09_clprim_in_back_vertex_store_indx_2_SIZE; + unsigned int outputclprimtoclip_null_primitive : CLIPPER_DEBUG_REG09_outputclprimtoclip_null_primitive_SIZE; + unsigned int clprim_in_back_event : CLIPPER_DEBUG_REG09_clprim_in_back_event_SIZE; + } clipper_debug_reg09_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg09_t f; +} clipper_debug_reg09_u; + + +/* + * CLIPPER_DEBUG_REG10 struct + */ + +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE 4 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE 2 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE 4 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE 2 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE 4 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE 2 +#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE 1 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE 2 +#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE 1 +#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE 1 +#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE 3 +#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE 6 + +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT 0 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT 4 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT 6 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT 10 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT 12 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT 16 +#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT 18 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT 19 +#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT 21 +#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT 22 +#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT 23 +#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT 26 + +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x0000000f +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK 0x00000030 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x000003c0 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK 0x00000c00 +#define CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x0000f000 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK 0x00030000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK 0x00040000 +#define CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK 0x00180000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK 0x00200000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK 0x00400000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK 0x03800000 +#define CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK 0xfc000000 + +#define CLIPPER_DEBUG_REG10_MASK \ + (CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK | \ + CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK | \ + CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK | \ + CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK | \ + CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK | \ + CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK | \ + CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) + +#define CLIPPER_DEBUG_REG10(primic_to_clprim_fifo_vertex_store_indx_2, always_zero3, primic_to_clprim_fifo_vertex_store_indx_1, always_zero2, primic_to_clprim_fifo_vertex_store_indx_0, always_zero1, clprim_in_back_state_var_indx, always_zero0, clprim_in_back_end_of_packet, clprim_in_back_first_prim_of_slot, clprim_in_back_deallocate_slot, clprim_in_back_event_id) \ + ((primic_to_clprim_fifo_vertex_store_indx_2 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT) | \ + (always_zero3 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT) | \ + (primic_to_clprim_fifo_vertex_store_indx_1 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT) | \ + (primic_to_clprim_fifo_vertex_store_indx_0 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT) | \ + (clprim_in_back_state_var_indx << CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT) | \ + (clprim_in_back_end_of_packet << CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT) | \ + (clprim_in_back_first_prim_of_slot << CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT) | \ + (clprim_in_back_deallocate_slot << CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT) | \ + (clprim_in_back_event_id << CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT)) + +#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_2(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO3(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_1(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO2(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_primic_to_clprim_fifo_vertex_store_indx_0(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK) >> CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO1(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_state_var_indx(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_ALWAYS_ZERO0(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_end_of_packet(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_first_prim_of_slot(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_deallocate_slot(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG10_GET_clprim_in_back_event_id(clipper_debug_reg10) \ + ((clipper_debug_reg10 & CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) >> CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT) + +#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_2(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_2) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_MASK) | (primic_to_clprim_fifo_vertex_store_indx_2 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO3(clipper_debug_reg10_reg, always_zero3) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_MASK) | (always_zero3 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_1(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_1) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_MASK) | (primic_to_clprim_fifo_vertex_store_indx_1 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO2(clipper_debug_reg10_reg, always_zero2) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_primic_to_clprim_fifo_vertex_store_indx_0(clipper_debug_reg10_reg, primic_to_clprim_fifo_vertex_store_indx_0) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_MASK) | (primic_to_clprim_fifo_vertex_store_indx_0 << CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO1(clipper_debug_reg10_reg, always_zero1) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_state_var_indx(clipper_debug_reg10_reg, clprim_in_back_state_var_indx) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_MASK) | (clprim_in_back_state_var_indx << CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_ALWAYS_ZERO0(clipper_debug_reg10_reg, always_zero0) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_end_of_packet(clipper_debug_reg10_reg, clprim_in_back_end_of_packet) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_MASK) | (clprim_in_back_end_of_packet << CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_first_prim_of_slot(clipper_debug_reg10_reg, clprim_in_back_first_prim_of_slot) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_MASK) | (clprim_in_back_first_prim_of_slot << CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_deallocate_slot(clipper_debug_reg10_reg, clprim_in_back_deallocate_slot) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_MASK) | (clprim_in_back_deallocate_slot << CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SHIFT) +#define CLIPPER_DEBUG_REG10_SET_clprim_in_back_event_id(clipper_debug_reg10_reg, clprim_in_back_event_id) \ + clipper_debug_reg10_reg = (clipper_debug_reg10_reg & ~CLIPPER_DEBUG_REG10_clprim_in_back_event_id_MASK) | (clprim_in_back_event_id << CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg10_t { + unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE; + unsigned int clprim_in_back_state_var_indx : CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE; + unsigned int clprim_in_back_end_of_packet : CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE; + unsigned int clprim_in_back_first_prim_of_slot : CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE; + unsigned int clprim_in_back_deallocate_slot : CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE; + unsigned int clprim_in_back_event_id : CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE; + } clipper_debug_reg10_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg10_t { + unsigned int clprim_in_back_event_id : CLIPPER_DEBUG_REG10_clprim_in_back_event_id_SIZE; + unsigned int clprim_in_back_deallocate_slot : CLIPPER_DEBUG_REG10_clprim_in_back_deallocate_slot_SIZE; + unsigned int clprim_in_back_first_prim_of_slot : CLIPPER_DEBUG_REG10_clprim_in_back_first_prim_of_slot_SIZE; + unsigned int clprim_in_back_end_of_packet : CLIPPER_DEBUG_REG10_clprim_in_back_end_of_packet_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO0_SIZE; + unsigned int clprim_in_back_state_var_indx : CLIPPER_DEBUG_REG10_clprim_in_back_state_var_indx_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO1_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_0 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_0_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO2_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_1 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_1_SIZE; + unsigned int always_zero3 : CLIPPER_DEBUG_REG10_ALWAYS_ZERO3_SIZE; + unsigned int primic_to_clprim_fifo_vertex_store_indx_2 : CLIPPER_DEBUG_REG10_primic_to_clprim_fifo_vertex_store_indx_2_SIZE; + } clipper_debug_reg10_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg10_t f; +} clipper_debug_reg10_u; + + +/* + * CLIPPER_DEBUG_REG11 struct + */ + +#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE 4 +#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE 28 + +#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT 0 +#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT 4 + +#define CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK 0x0000000f +#define CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK 0xfffffff0 + +#define CLIPPER_DEBUG_REG11_MASK \ + (CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK | \ + CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) + +#define CLIPPER_DEBUG_REG11(vertval_bits_vertex_vertex_store_msb, always_zero) \ + ((vertval_bits_vertex_vertex_store_msb << CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT) | \ + (always_zero << CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT)) + +#define CLIPPER_DEBUG_REG11_GET_vertval_bits_vertex_vertex_store_msb(clipper_debug_reg11) \ + ((clipper_debug_reg11 & CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK) >> CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT) +#define CLIPPER_DEBUG_REG11_GET_ALWAYS_ZERO(clipper_debug_reg11) \ + ((clipper_debug_reg11 & CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) >> CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT) + +#define CLIPPER_DEBUG_REG11_SET_vertval_bits_vertex_vertex_store_msb(clipper_debug_reg11_reg, vertval_bits_vertex_vertex_store_msb) \ + clipper_debug_reg11_reg = (clipper_debug_reg11_reg & ~CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_MASK) | (vertval_bits_vertex_vertex_store_msb << CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SHIFT) +#define CLIPPER_DEBUG_REG11_SET_ALWAYS_ZERO(clipper_debug_reg11_reg, always_zero) \ + clipper_debug_reg11_reg = (clipper_debug_reg11_reg & ~CLIPPER_DEBUG_REG11_ALWAYS_ZERO_MASK) | (always_zero << CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg11_t { + unsigned int vertval_bits_vertex_vertex_store_msb : CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE; + unsigned int always_zero : CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE; + } clipper_debug_reg11_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg11_t { + unsigned int always_zero : CLIPPER_DEBUG_REG11_ALWAYS_ZERO_SIZE; + unsigned int vertval_bits_vertex_vertex_store_msb : CLIPPER_DEBUG_REG11_vertval_bits_vertex_vertex_store_msb_SIZE; + } clipper_debug_reg11_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg11_t f; +} clipper_debug_reg11_u; + + +/* + * CLIPPER_DEBUG_REG12 struct + */ + +#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE 2 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE 3 +#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE 1 +#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE 5 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE 4 +#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE 4 +#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE 2 +#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE 1 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE 10 + +#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT 0 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT 2 +#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT 5 +#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT 6 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT 11 +#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT 15 +#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT 19 +#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT 21 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT 22 + +#define CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK 0x00000003 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK 0x0000001c +#define CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK 0x00000020 +#define CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK 0x000007c0 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK 0x00007800 +#define CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK 0x00078000 +#define CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK 0x00180000 +#define CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK 0x00200000 +#define CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK 0xffc00000 + +#define CLIPPER_DEBUG_REG12_MASK \ + (CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK | \ + CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK | \ + CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK | \ + CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK | \ + CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK | \ + CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK | \ + CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK | \ + CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG12(clip_priority_available_vte_out_clip, always_zero2, clip_vertex_fifo_empty, clip_priority_available_clip_verts, always_zero1, vertval_bits_vertex_cc_next_valid, clipcc_vertex_store_indx, primic_to_clprim_valid, always_zero0) \ + ((clip_priority_available_vte_out_clip << CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT) | \ + (always_zero2 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT) | \ + (clip_vertex_fifo_empty << CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT) | \ + (clip_priority_available_clip_verts << CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT) | \ + (vertval_bits_vertex_cc_next_valid << CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT) | \ + (clipcc_vertex_store_indx << CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT) | \ + (primic_to_clprim_valid << CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG12_GET_clip_priority_available_vte_out_clip(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK) >> CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO2(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_clip_vertex_fifo_empty(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK) >> CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_clip_priority_available_clip_verts(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK) >> CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO1(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_vertval_bits_vertex_cc_next_valid(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK) >> CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_clipcc_vertex_store_indx(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK) >> CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_primic_to_clprim_valid(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK) >> CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT) +#define CLIPPER_DEBUG_REG12_GET_ALWAYS_ZERO0(clipper_debug_reg12) \ + ((clipper_debug_reg12 & CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG12_SET_clip_priority_available_vte_out_clip(clipper_debug_reg12_reg, clip_priority_available_vte_out_clip) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_MASK) | (clip_priority_available_vte_out_clip << CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO2(clipper_debug_reg12_reg, always_zero2) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_MASK) | (always_zero2 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_clip_vertex_fifo_empty(clipper_debug_reg12_reg, clip_vertex_fifo_empty) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_MASK) | (clip_vertex_fifo_empty << CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_clip_priority_available_clip_verts(clipper_debug_reg12_reg, clip_priority_available_clip_verts) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_MASK) | (clip_priority_available_clip_verts << CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO1(clipper_debug_reg12_reg, always_zero1) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_vertval_bits_vertex_cc_next_valid(clipper_debug_reg12_reg, vertval_bits_vertex_cc_next_valid) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_MASK) | (vertval_bits_vertex_cc_next_valid << CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_clipcc_vertex_store_indx(clipper_debug_reg12_reg, clipcc_vertex_store_indx) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_MASK) | (clipcc_vertex_store_indx << CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_primic_to_clprim_valid(clipper_debug_reg12_reg, primic_to_clprim_valid) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_primic_to_clprim_valid_MASK) | (primic_to_clprim_valid << CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SHIFT) +#define CLIPPER_DEBUG_REG12_SET_ALWAYS_ZERO0(clipper_debug_reg12_reg, always_zero0) \ + clipper_debug_reg12_reg = (clipper_debug_reg12_reg & ~CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg12_t { + unsigned int clip_priority_available_vte_out_clip : CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE; + unsigned int clip_vertex_fifo_empty : CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE; + unsigned int clip_priority_available_clip_verts : CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE; + unsigned int vertval_bits_vertex_cc_next_valid : CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE; + unsigned int clipcc_vertex_store_indx : CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE; + unsigned int primic_to_clprim_valid : CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg12_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg12_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO0_SIZE; + unsigned int primic_to_clprim_valid : CLIPPER_DEBUG_REG12_primic_to_clprim_valid_SIZE; + unsigned int clipcc_vertex_store_indx : CLIPPER_DEBUG_REG12_clipcc_vertex_store_indx_SIZE; + unsigned int vertval_bits_vertex_cc_next_valid : CLIPPER_DEBUG_REG12_vertval_bits_vertex_cc_next_valid_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO1_SIZE; + unsigned int clip_priority_available_clip_verts : CLIPPER_DEBUG_REG12_clip_priority_available_clip_verts_SIZE; + unsigned int clip_vertex_fifo_empty : CLIPPER_DEBUG_REG12_clip_vertex_fifo_empty_SIZE; + unsigned int always_zero2 : CLIPPER_DEBUG_REG12_ALWAYS_ZERO2_SIZE; + unsigned int clip_priority_available_vte_out_clip : CLIPPER_DEBUG_REG12_clip_priority_available_vte_out_clip_SIZE; + } clipper_debug_reg12_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg12_t f; +} clipper_debug_reg12_u; + + +/* + * CLIPPER_DEBUG_REG13 struct + */ + +#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE 4 +#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE 7 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE 3 +#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE 4 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE 1 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE 1 +#define CLIPPER_DEBUG_REG13_sm0_current_state_SIZE 7 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE 5 + +#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT 0 +#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT 4 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT 11 +#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT 14 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT 18 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT 19 +#define CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT 20 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT 27 + +#define CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK 0x0000000f +#define CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK 0x000007f0 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK 0x00003800 +#define CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK 0x0003c000 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK 0x00040000 +#define CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK 0x00080000 +#define CLIPPER_DEBUG_REG13_sm0_current_state_MASK 0x07f00000 +#define CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK 0xf8000000 + +#define CLIPPER_DEBUG_REG13_MASK \ + (CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK | \ + CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK | \ + CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK | \ + CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK | \ + CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK | \ + CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK | \ + CLIPPER_DEBUG_REG13_sm0_current_state_MASK | \ + CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) + +#define CLIPPER_DEBUG_REG13(sm0_clip_vert_cnt, sm0_prim_end_state, always_zero1, sm0_vertex_clip_cnt, sm0_inv_to_clip_data_valid_1, sm0_inv_to_clip_data_valid_0, sm0_current_state, always_zero0) \ + ((sm0_clip_vert_cnt << CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT) | \ + (sm0_prim_end_state << CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT) | \ + (always_zero1 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT) | \ + (sm0_vertex_clip_cnt << CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT) | \ + (sm0_inv_to_clip_data_valid_1 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT) | \ + (sm0_inv_to_clip_data_valid_0 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT) | \ + (sm0_current_state << CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT) | \ + (always_zero0 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT)) + +#define CLIPPER_DEBUG_REG13_GET_sm0_clip_vert_cnt(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK) >> CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_prim_end_state(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK) >> CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_ALWAYS_ZERO1(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK) >> CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_vertex_clip_cnt(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK) >> CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_inv_to_clip_data_valid_1(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK) >> CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_inv_to_clip_data_valid_0(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK) >> CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_sm0_current_state(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_sm0_current_state_MASK) >> CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT) +#define CLIPPER_DEBUG_REG13_GET_ALWAYS_ZERO0(clipper_debug_reg13) \ + ((clipper_debug_reg13 & CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) >> CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT) + +#define CLIPPER_DEBUG_REG13_SET_sm0_clip_vert_cnt(clipper_debug_reg13_reg, sm0_clip_vert_cnt) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_MASK) | (sm0_clip_vert_cnt << CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_prim_end_state(clipper_debug_reg13_reg, sm0_prim_end_state) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_prim_end_state_MASK) | (sm0_prim_end_state << CLIPPER_DEBUG_REG13_sm0_prim_end_state_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_ALWAYS_ZERO1(clipper_debug_reg13_reg, always_zero1) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_MASK) | (always_zero1 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_vertex_clip_cnt(clipper_debug_reg13_reg, sm0_vertex_clip_cnt) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_MASK) | (sm0_vertex_clip_cnt << CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_inv_to_clip_data_valid_1(clipper_debug_reg13_reg, sm0_inv_to_clip_data_valid_1) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_MASK) | (sm0_inv_to_clip_data_valid_1 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_inv_to_clip_data_valid_0(clipper_debug_reg13_reg, sm0_inv_to_clip_data_valid_0) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_MASK) | (sm0_inv_to_clip_data_valid_0 << CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_sm0_current_state(clipper_debug_reg13_reg, sm0_current_state) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_sm0_current_state_MASK) | (sm0_current_state << CLIPPER_DEBUG_REG13_sm0_current_state_SHIFT) +#define CLIPPER_DEBUG_REG13_SET_ALWAYS_ZERO0(clipper_debug_reg13_reg, always_zero0) \ + clipper_debug_reg13_reg = (clipper_debug_reg13_reg & ~CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_MASK) | (always_zero0 << CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _clipper_debug_reg13_t { + unsigned int sm0_clip_vert_cnt : CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE; + unsigned int sm0_prim_end_state : CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE; + unsigned int sm0_vertex_clip_cnt : CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE; + unsigned int sm0_inv_to_clip_data_valid_1 : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE; + unsigned int sm0_inv_to_clip_data_valid_0 : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE; + unsigned int sm0_current_state : CLIPPER_DEBUG_REG13_sm0_current_state_SIZE; + unsigned int always_zero0 : CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE; + } clipper_debug_reg13_t; + +#else // !BIGENDIAN_OS + + typedef struct _clipper_debug_reg13_t { + unsigned int always_zero0 : CLIPPER_DEBUG_REG13_ALWAYS_ZERO0_SIZE; + unsigned int sm0_current_state : CLIPPER_DEBUG_REG13_sm0_current_state_SIZE; + unsigned int sm0_inv_to_clip_data_valid_0 : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_0_SIZE; + unsigned int sm0_inv_to_clip_data_valid_1 : CLIPPER_DEBUG_REG13_sm0_inv_to_clip_data_valid_1_SIZE; + unsigned int sm0_vertex_clip_cnt : CLIPPER_DEBUG_REG13_sm0_vertex_clip_cnt_SIZE; + unsigned int always_zero1 : CLIPPER_DEBUG_REG13_ALWAYS_ZERO1_SIZE; + unsigned int sm0_prim_end_state : CLIPPER_DEBUG_REG13_sm0_prim_end_state_SIZE; + unsigned int sm0_clip_vert_cnt : CLIPPER_DEBUG_REG13_sm0_clip_vert_cnt_SIZE; + } clipper_debug_reg13_t; + +#endif + +typedef union { + unsigned int val : 32; + clipper_debug_reg13_t f; +} clipper_debug_reg13_u; + + +/* + * SXIFCCG_DEBUG_REG0 struct + */ + +#define SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE 4 +#define SXIFCCG_DEBUG_REG0_position_address_SIZE 3 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE 3 +#define SXIFCCG_DEBUG_REG0_point_address_SIZE 3 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE 3 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE 1 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE 2 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE 4 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE 7 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE 1 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE 1 + +#define SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT 0 +#define SXIFCCG_DEBUG_REG0_position_address_SHIFT 4 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT 7 +#define SXIFCCG_DEBUG_REG0_point_address_SHIFT 10 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT 13 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT 16 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT 17 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT 19 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT 23 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT 30 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT 31 + +#define SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK 0x0000000f +#define SXIFCCG_DEBUG_REG0_position_address_MASK 0x00000070 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK 0x00000380 +#define SXIFCCG_DEBUG_REG0_point_address_MASK 0x00001c00 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK 0x0000e000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK 0x00010000 +#define SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK 0x00060000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK 0x00780000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK 0x3f800000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK 0x40000000 +#define SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK 0x80000000 + +#define SXIFCCG_DEBUG_REG0_MASK \ + (SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK | \ + SXIFCCG_DEBUG_REG0_position_address_MASK | \ + SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK | \ + SXIFCCG_DEBUG_REG0_point_address_MASK | \ + SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK | \ + SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK | \ + SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) + +#define SXIFCCG_DEBUG_REG0(nan_kill_flag, position_address, always_zero2, point_address, always_zero1, sx_pending_rd_state_var_indx, always_zero0, sx_pending_rd_req_mask, sx_pending_rd_pci, sx_pending_rd_aux_inc, sx_pending_rd_aux_sel) \ + ((nan_kill_flag << SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT) | \ + (position_address << SXIFCCG_DEBUG_REG0_position_address_SHIFT) | \ + (always_zero2 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT) | \ + (point_address << SXIFCCG_DEBUG_REG0_point_address_SHIFT) | \ + (always_zero1 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT) | \ + (sx_pending_rd_state_var_indx << SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT) | \ + (always_zero0 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT) | \ + (sx_pending_rd_req_mask << SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT) | \ + (sx_pending_rd_pci << SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT) | \ + (sx_pending_rd_aux_inc << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT) | \ + (sx_pending_rd_aux_sel << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT)) + +#define SXIFCCG_DEBUG_REG0_GET_nan_kill_flag(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK) >> SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_position_address(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_position_address_MASK) >> SXIFCCG_DEBUG_REG0_position_address_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO2(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_point_address(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_point_address_MASK) >> SXIFCCG_DEBUG_REG0_point_address_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO1(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_state_var_indx(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_ALWAYS_ZERO0(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_req_mask(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_pci(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_aux_inc(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT) +#define SXIFCCG_DEBUG_REG0_GET_sx_pending_rd_aux_sel(sxifccg_debug_reg0) \ + ((sxifccg_debug_reg0 & SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) >> SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT) + +#define SXIFCCG_DEBUG_REG0_SET_nan_kill_flag(sxifccg_debug_reg0_reg, nan_kill_flag) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_nan_kill_flag_MASK) | (nan_kill_flag << SXIFCCG_DEBUG_REG0_nan_kill_flag_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_position_address(sxifccg_debug_reg0_reg, position_address) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_position_address_MASK) | (position_address << SXIFCCG_DEBUG_REG0_position_address_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO2(sxifccg_debug_reg0_reg, always_zero2) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_point_address(sxifccg_debug_reg0_reg, point_address) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_point_address_MASK) | (point_address << SXIFCCG_DEBUG_REG0_point_address_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO1(sxifccg_debug_reg0_reg, always_zero1) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_state_var_indx(sxifccg_debug_reg0_reg, sx_pending_rd_state_var_indx) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_MASK) | (sx_pending_rd_state_var_indx << SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_ALWAYS_ZERO0(sxifccg_debug_reg0_reg, always_zero0) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_req_mask(sxifccg_debug_reg0_reg, sx_pending_rd_req_mask) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_MASK) | (sx_pending_rd_req_mask << SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_pci(sxifccg_debug_reg0_reg, sx_pending_rd_pci) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_MASK) | (sx_pending_rd_pci << SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_aux_inc(sxifccg_debug_reg0_reg, sx_pending_rd_aux_inc) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_MASK) | (sx_pending_rd_aux_inc << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SHIFT) +#define SXIFCCG_DEBUG_REG0_SET_sx_pending_rd_aux_sel(sxifccg_debug_reg0_reg, sx_pending_rd_aux_sel) \ + sxifccg_debug_reg0_reg = (sxifccg_debug_reg0_reg & ~SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_MASK) | (sx_pending_rd_aux_sel << SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg0_t { + unsigned int nan_kill_flag : SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE; + unsigned int position_address : SXIFCCG_DEBUG_REG0_position_address_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE; + unsigned int point_address : SXIFCCG_DEBUG_REG0_point_address_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE; + unsigned int sx_pending_rd_state_var_indx : SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE; + unsigned int sx_pending_rd_req_mask : SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE; + unsigned int sx_pending_rd_pci : SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE; + unsigned int sx_pending_rd_aux_inc : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE; + unsigned int sx_pending_rd_aux_sel : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE; + } sxifccg_debug_reg0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg0_t { + unsigned int sx_pending_rd_aux_sel : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_sel_SIZE; + unsigned int sx_pending_rd_aux_inc : SXIFCCG_DEBUG_REG0_sx_pending_rd_aux_inc_SIZE; + unsigned int sx_pending_rd_pci : SXIFCCG_DEBUG_REG0_sx_pending_rd_pci_SIZE; + unsigned int sx_pending_rd_req_mask : SXIFCCG_DEBUG_REG0_sx_pending_rd_req_mask_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO0_SIZE; + unsigned int sx_pending_rd_state_var_indx : SXIFCCG_DEBUG_REG0_sx_pending_rd_state_var_indx_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO1_SIZE; + unsigned int point_address : SXIFCCG_DEBUG_REG0_point_address_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG0_ALWAYS_ZERO2_SIZE; + unsigned int position_address : SXIFCCG_DEBUG_REG0_position_address_SIZE; + unsigned int nan_kill_flag : SXIFCCG_DEBUG_REG0_nan_kill_flag_SIZE; + } sxifccg_debug_reg0_t; + +#endif + +typedef union { + unsigned int val : 32; + sxifccg_debug_reg0_t f; +} sxifccg_debug_reg0_u; + + +/* + * SXIFCCG_DEBUG_REG1 struct + */ + +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE 2 +#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE 2 +#define SXIFCCG_DEBUG_REG1_available_positions_SIZE 3 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE 4 +#define SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE 1 +#define SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE 3 +#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE 1 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE 4 +#define SXIFCCG_DEBUG_REG1_aux_sel_SIZE 1 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE 2 +#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE 2 +#define SXIFCCG_DEBUG_REG1_param_cache_base_SIZE 7 + +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT 0 +#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT 2 +#define SXIFCCG_DEBUG_REG1_available_positions_SHIFT 4 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT 7 +#define SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT 11 +#define SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT 12 +#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT 15 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT 16 +#define SXIFCCG_DEBUG_REG1_aux_sel_SHIFT 20 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT 21 +#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT 23 +#define SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT 25 + +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK 0x00000003 +#define SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK 0x0000000c +#define SXIFCCG_DEBUG_REG1_available_positions_MASK 0x00000070 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK 0x00000780 +#define SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK 0x00000800 +#define SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK 0x00007000 +#define SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK 0x00008000 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK 0x000f0000 +#define SXIFCCG_DEBUG_REG1_aux_sel_MASK 0x00100000 +#define SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK 0x00600000 +#define SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK 0x01800000 +#define SXIFCCG_DEBUG_REG1_param_cache_base_MASK 0xfe000000 + +#define SXIFCCG_DEBUG_REG1_MASK \ + (SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK | \ + SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK | \ + SXIFCCG_DEBUG_REG1_available_positions_MASK | \ + SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK | \ + SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK | \ + SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK | \ + SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK | \ + SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK | \ + SXIFCCG_DEBUG_REG1_aux_sel_MASK | \ + SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK | \ + SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK | \ + SXIFCCG_DEBUG_REG1_param_cache_base_MASK) + +#define SXIFCCG_DEBUG_REG1(always_zero3, sx_to_pa_empty, available_positions, always_zero2, sx_pending_advance, sx_receive_indx, statevar_bits_sxpa_aux_vector, always_zero1, aux_sel, always_zero0, pasx_req_cnt, param_cache_base) \ + ((always_zero3 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT) | \ + (sx_to_pa_empty << SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT) | \ + (available_positions << SXIFCCG_DEBUG_REG1_available_positions_SHIFT) | \ + (always_zero2 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT) | \ + (sx_pending_advance << SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT) | \ + (sx_receive_indx << SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT) | \ + (statevar_bits_sxpa_aux_vector << SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT) | \ + (always_zero1 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT) | \ + (aux_sel << SXIFCCG_DEBUG_REG1_aux_sel_SHIFT) | \ + (always_zero0 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT) | \ + (pasx_req_cnt << SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT) | \ + (param_cache_base << SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT)) + +#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO3(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_sx_to_pa_empty(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK) >> SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_available_positions(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_available_positions_MASK) >> SXIFCCG_DEBUG_REG1_available_positions_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO2(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_sx_pending_advance(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK) >> SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_sx_receive_indx(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK) >> SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_statevar_bits_sxpa_aux_vector(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK) >> SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO1(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_aux_sel(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_aux_sel_MASK) >> SXIFCCG_DEBUG_REG1_aux_sel_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_ALWAYS_ZERO0(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_pasx_req_cnt(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK) >> SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT) +#define SXIFCCG_DEBUG_REG1_GET_param_cache_base(sxifccg_debug_reg1) \ + ((sxifccg_debug_reg1 & SXIFCCG_DEBUG_REG1_param_cache_base_MASK) >> SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT) + +#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO3(sxifccg_debug_reg1_reg, always_zero3) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_sx_to_pa_empty(sxifccg_debug_reg1_reg, sx_to_pa_empty) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_to_pa_empty_MASK) | (sx_to_pa_empty << SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_available_positions(sxifccg_debug_reg1_reg, available_positions) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_available_positions_MASK) | (available_positions << SXIFCCG_DEBUG_REG1_available_positions_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO2(sxifccg_debug_reg1_reg, always_zero2) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_sx_pending_advance(sxifccg_debug_reg1_reg, sx_pending_advance) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_pending_advance_MASK) | (sx_pending_advance << SXIFCCG_DEBUG_REG1_sx_pending_advance_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_sx_receive_indx(sxifccg_debug_reg1_reg, sx_receive_indx) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_sx_receive_indx_MASK) | (sx_receive_indx << SXIFCCG_DEBUG_REG1_sx_receive_indx_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_statevar_bits_sxpa_aux_vector(sxifccg_debug_reg1_reg, statevar_bits_sxpa_aux_vector) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_MASK) | (statevar_bits_sxpa_aux_vector << SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO1(sxifccg_debug_reg1_reg, always_zero1) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_aux_sel(sxifccg_debug_reg1_reg, aux_sel) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_aux_sel_MASK) | (aux_sel << SXIFCCG_DEBUG_REG1_aux_sel_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_ALWAYS_ZERO0(sxifccg_debug_reg1_reg, always_zero0) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_pasx_req_cnt(sxifccg_debug_reg1_reg, pasx_req_cnt) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_pasx_req_cnt_MASK) | (pasx_req_cnt << SXIFCCG_DEBUG_REG1_pasx_req_cnt_SHIFT) +#define SXIFCCG_DEBUG_REG1_SET_param_cache_base(sxifccg_debug_reg1_reg, param_cache_base) \ + sxifccg_debug_reg1_reg = (sxifccg_debug_reg1_reg & ~SXIFCCG_DEBUG_REG1_param_cache_base_MASK) | (param_cache_base << SXIFCCG_DEBUG_REG1_param_cache_base_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg1_t { + unsigned int always_zero3 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE; + unsigned int sx_to_pa_empty : SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE; + unsigned int available_positions : SXIFCCG_DEBUG_REG1_available_positions_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE; + unsigned int sx_pending_advance : SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE; + unsigned int sx_receive_indx : SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE; + unsigned int statevar_bits_sxpa_aux_vector : SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE; + unsigned int aux_sel : SXIFCCG_DEBUG_REG1_aux_sel_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE; + unsigned int pasx_req_cnt : SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE; + unsigned int param_cache_base : SXIFCCG_DEBUG_REG1_param_cache_base_SIZE; + } sxifccg_debug_reg1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg1_t { + unsigned int param_cache_base : SXIFCCG_DEBUG_REG1_param_cache_base_SIZE; + unsigned int pasx_req_cnt : SXIFCCG_DEBUG_REG1_pasx_req_cnt_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO0_SIZE; + unsigned int aux_sel : SXIFCCG_DEBUG_REG1_aux_sel_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO1_SIZE; + unsigned int statevar_bits_sxpa_aux_vector : SXIFCCG_DEBUG_REG1_statevar_bits_sxpa_aux_vector_SIZE; + unsigned int sx_receive_indx : SXIFCCG_DEBUG_REG1_sx_receive_indx_SIZE; + unsigned int sx_pending_advance : SXIFCCG_DEBUG_REG1_sx_pending_advance_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO2_SIZE; + unsigned int available_positions : SXIFCCG_DEBUG_REG1_available_positions_SIZE; + unsigned int sx_to_pa_empty : SXIFCCG_DEBUG_REG1_sx_to_pa_empty_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG1_ALWAYS_ZERO3_SIZE; + } sxifccg_debug_reg1_t; + +#endif + +typedef union { + unsigned int val : 32; + sxifccg_debug_reg1_t f; +} sxifccg_debug_reg1_u; + + +/* + * SXIFCCG_DEBUG_REG2 struct + */ + +#define SXIFCCG_DEBUG_REG2_sx_sent_SIZE 1 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_aux_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE 6 +#define SXIFCCG_DEBUG_REG2_req_active_verts_SIZE 7 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE 1 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE 1 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE 2 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE 2 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE 4 +#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE 1 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE 3 + +#define SXIFCCG_DEBUG_REG2_sx_sent_SHIFT 0 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT 1 +#define SXIFCCG_DEBUG_REG2_sx_aux_SHIFT 2 +#define SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT 3 +#define SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT 9 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT 16 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT 17 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT 18 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT 20 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT 22 +#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT 26 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT 27 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT 28 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT 29 + +#define SXIFCCG_DEBUG_REG2_sx_sent_MASK 0x00000001 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK 0x00000002 +#define SXIFCCG_DEBUG_REG2_sx_aux_MASK 0x00000004 +#define SXIFCCG_DEBUG_REG2_sx_request_indx_MASK 0x000001f8 +#define SXIFCCG_DEBUG_REG2_req_active_verts_MASK 0x0000fe00 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK 0x00010000 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK 0x00020000 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK 0x000c0000 +#define SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK 0x00300000 +#define SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK 0x03c00000 +#define SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK 0x04000000 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK 0x08000000 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK 0x10000000 +#define SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK 0xe0000000 + +#define SXIFCCG_DEBUG_REG2_MASK \ + (SXIFCCG_DEBUG_REG2_sx_sent_MASK | \ + SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK | \ + SXIFCCG_DEBUG_REG2_sx_aux_MASK | \ + SXIFCCG_DEBUG_REG2_sx_request_indx_MASK | \ + SXIFCCG_DEBUG_REG2_req_active_verts_MASK | \ + SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK | \ + SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK | \ + SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK | \ + SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK | \ + SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK | \ + SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK | \ + SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK | \ + SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK | \ + SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) + +#define SXIFCCG_DEBUG_REG2(sx_sent, always_zero3, sx_aux, sx_request_indx, req_active_verts, always_zero2, vgt_to_ccgen_state_var_indx, always_zero1, vgt_to_ccgen_active_verts, always_zero0, req_active_verts_loaded, sx_pending_fifo_empty, sx_pending_fifo_full, sx_pending_fifo_contents) \ + ((sx_sent << SXIFCCG_DEBUG_REG2_sx_sent_SHIFT) | \ + (always_zero3 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT) | \ + (sx_aux << SXIFCCG_DEBUG_REG2_sx_aux_SHIFT) | \ + (sx_request_indx << SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT) | \ + (req_active_verts << SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT) | \ + (always_zero2 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT) | \ + (vgt_to_ccgen_state_var_indx << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT) | \ + (always_zero1 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT) | \ + (vgt_to_ccgen_active_verts << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT) | \ + (always_zero0 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT) | \ + (req_active_verts_loaded << SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT) | \ + (sx_pending_fifo_empty << SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT) | \ + (sx_pending_fifo_full << SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT) | \ + (sx_pending_fifo_contents << SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT)) + +#define SXIFCCG_DEBUG_REG2_GET_sx_sent(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_sent_MASK) >> SXIFCCG_DEBUG_REG2_sx_sent_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO3(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_aux(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_aux_MASK) >> SXIFCCG_DEBUG_REG2_sx_aux_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_request_indx(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_request_indx_MASK) >> SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_req_active_verts(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_req_active_verts_MASK) >> SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO2(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_vgt_to_ccgen_state_var_indx(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK) >> SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO1(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_vgt_to_ccgen_active_verts(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK) >> SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_ALWAYS_ZERO0(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_req_active_verts_loaded(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK) >> SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_empty(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_full(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG2_GET_sx_pending_fifo_contents(sxifccg_debug_reg2) \ + ((sxifccg_debug_reg2 & SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) >> SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT) + +#define SXIFCCG_DEBUG_REG2_SET_sx_sent(sxifccg_debug_reg2_reg, sx_sent) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_sent_MASK) | (sx_sent << SXIFCCG_DEBUG_REG2_sx_sent_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO3(sxifccg_debug_reg2_reg, always_zero3) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_aux(sxifccg_debug_reg2_reg, sx_aux) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_aux_MASK) | (sx_aux << SXIFCCG_DEBUG_REG2_sx_aux_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_request_indx(sxifccg_debug_reg2_reg, sx_request_indx) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_request_indx_MASK) | (sx_request_indx << SXIFCCG_DEBUG_REG2_sx_request_indx_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_req_active_verts(sxifccg_debug_reg2_reg, req_active_verts) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_req_active_verts_MASK) | (req_active_verts << SXIFCCG_DEBUG_REG2_req_active_verts_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO2(sxifccg_debug_reg2_reg, always_zero2) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_vgt_to_ccgen_state_var_indx(sxifccg_debug_reg2_reg, vgt_to_ccgen_state_var_indx) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_MASK) | (vgt_to_ccgen_state_var_indx << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO1(sxifccg_debug_reg2_reg, always_zero1) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_vgt_to_ccgen_active_verts(sxifccg_debug_reg2_reg, vgt_to_ccgen_active_verts) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_MASK) | (vgt_to_ccgen_active_verts << SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_ALWAYS_ZERO0(sxifccg_debug_reg2_reg, always_zero0) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_req_active_verts_loaded(sxifccg_debug_reg2_reg, req_active_verts_loaded) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_req_active_verts_loaded_MASK) | (req_active_verts_loaded << SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_empty(sxifccg_debug_reg2_reg, sx_pending_fifo_empty) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_MASK) | (sx_pending_fifo_empty << SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_full(sxifccg_debug_reg2_reg, sx_pending_fifo_full) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_MASK) | (sx_pending_fifo_full << SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG2_SET_sx_pending_fifo_contents(sxifccg_debug_reg2_reg, sx_pending_fifo_contents) \ + sxifccg_debug_reg2_reg = (sxifccg_debug_reg2_reg & ~SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_MASK) | (sx_pending_fifo_contents << SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg2_t { + unsigned int sx_sent : SXIFCCG_DEBUG_REG2_sx_sent_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE; + unsigned int sx_aux : SXIFCCG_DEBUG_REG2_sx_aux_SIZE; + unsigned int sx_request_indx : SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE; + unsigned int req_active_verts : SXIFCCG_DEBUG_REG2_req_active_verts_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE; + unsigned int vgt_to_ccgen_state_var_indx : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE; + unsigned int vgt_to_ccgen_active_verts : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE; + unsigned int req_active_verts_loaded : SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE; + unsigned int sx_pending_fifo_empty : SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE; + unsigned int sx_pending_fifo_full : SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE; + unsigned int sx_pending_fifo_contents : SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE; + } sxifccg_debug_reg2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg2_t { + unsigned int sx_pending_fifo_contents : SXIFCCG_DEBUG_REG2_sx_pending_fifo_contents_SIZE; + unsigned int sx_pending_fifo_full : SXIFCCG_DEBUG_REG2_sx_pending_fifo_full_SIZE; + unsigned int sx_pending_fifo_empty : SXIFCCG_DEBUG_REG2_sx_pending_fifo_empty_SIZE; + unsigned int req_active_verts_loaded : SXIFCCG_DEBUG_REG2_req_active_verts_loaded_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO0_SIZE; + unsigned int vgt_to_ccgen_active_verts : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_active_verts_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO1_SIZE; + unsigned int vgt_to_ccgen_state_var_indx : SXIFCCG_DEBUG_REG2_vgt_to_ccgen_state_var_indx_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO2_SIZE; + unsigned int req_active_verts : SXIFCCG_DEBUG_REG2_req_active_verts_SIZE; + unsigned int sx_request_indx : SXIFCCG_DEBUG_REG2_sx_request_indx_SIZE; + unsigned int sx_aux : SXIFCCG_DEBUG_REG2_sx_aux_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG2_ALWAYS_ZERO3_SIZE; + unsigned int sx_sent : SXIFCCG_DEBUG_REG2_sx_sent_SIZE; + } sxifccg_debug_reg2_t; + +#endif + +typedef union { + unsigned int val : 32; + sxifccg_debug_reg2_t f; +} sxifccg_debug_reg2_u; + + +/* + * SXIFCCG_DEBUG_REG3 struct + */ + +#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE 4 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE 1 +#define SXIFCCG_DEBUG_REG3_available_positions_SIZE 3 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE 4 +#define SXIFCCG_DEBUG_REG3_current_state_SIZE 2 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE 1 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE 1 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE 2 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE 1 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE 1 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE 1 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE 1 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE 10 + +#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT 0 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT 4 +#define SXIFCCG_DEBUG_REG3_available_positions_SHIFT 5 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT 8 +#define SXIFCCG_DEBUG_REG3_current_state_SHIFT 12 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT 14 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT 15 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT 16 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT 18 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT 19 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT 20 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT 21 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT 22 + +#define SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK 0x0000000f +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK 0x00000010 +#define SXIFCCG_DEBUG_REG3_available_positions_MASK 0x000000e0 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK 0x00000f00 +#define SXIFCCG_DEBUG_REG3_current_state_MASK 0x00003000 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK 0x00004000 +#define SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK 0x00008000 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK 0x00030000 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK 0x00040000 +#define SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK 0x00080000 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK 0x00100000 +#define SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK 0x00200000 +#define SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK 0xffc00000 + +#define SXIFCCG_DEBUG_REG3_MASK \ + (SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK | \ + SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK | \ + SXIFCCG_DEBUG_REG3_available_positions_MASK | \ + SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK | \ + SXIFCCG_DEBUG_REG3_current_state_MASK | \ + SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK | \ + SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK | \ + SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK | \ + SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK | \ + SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK | \ + SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK | \ + SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK | \ + SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) + +#define SXIFCCG_DEBUG_REG3(vertex_fifo_entriesavailable, always_zero3, available_positions, always_zero2, current_state, vertex_fifo_empty, vertex_fifo_full, always_zero1, sx0_receive_fifo_empty, sx0_receive_fifo_full, vgt_to_ccgen_fifo_empty, vgt_to_ccgen_fifo_full, always_zero0) \ + ((vertex_fifo_entriesavailable << SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT) | \ + (always_zero3 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT) | \ + (available_positions << SXIFCCG_DEBUG_REG3_available_positions_SHIFT) | \ + (always_zero2 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT) | \ + (current_state << SXIFCCG_DEBUG_REG3_current_state_SHIFT) | \ + (vertex_fifo_empty << SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT) | \ + (vertex_fifo_full << SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT) | \ + (always_zero1 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT) | \ + (sx0_receive_fifo_empty << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT) | \ + (sx0_receive_fifo_full << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT) | \ + (vgt_to_ccgen_fifo_empty << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT) | \ + (vgt_to_ccgen_fifo_full << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT) | \ + (always_zero0 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT)) + +#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_entriesavailable(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO3(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_available_positions(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_available_positions_MASK) >> SXIFCCG_DEBUG_REG3_available_positions_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO2(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_current_state(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_current_state_MASK) >> SXIFCCG_DEBUG_REG3_current_state_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_empty(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_vertex_fifo_full(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO1(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_sx0_receive_fifo_empty(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_sx0_receive_fifo_full(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_vgt_to_ccgen_fifo_empty(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK) >> SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_vgt_to_ccgen_fifo_full(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK) >> SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_GET_ALWAYS_ZERO0(sxifccg_debug_reg3) \ + ((sxifccg_debug_reg3 & SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) >> SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT) + +#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_entriesavailable(sxifccg_debug_reg3_reg, vertex_fifo_entriesavailable) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_MASK) | (vertex_fifo_entriesavailable << SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO3(sxifccg_debug_reg3_reg, always_zero3) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_MASK) | (always_zero3 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_available_positions(sxifccg_debug_reg3_reg, available_positions) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_available_positions_MASK) | (available_positions << SXIFCCG_DEBUG_REG3_available_positions_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO2(sxifccg_debug_reg3_reg, always_zero2) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_MASK) | (always_zero2 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_current_state(sxifccg_debug_reg3_reg, current_state) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_current_state_MASK) | (current_state << SXIFCCG_DEBUG_REG3_current_state_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_empty(sxifccg_debug_reg3_reg, vertex_fifo_empty) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_empty_MASK) | (vertex_fifo_empty << SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_vertex_fifo_full(sxifccg_debug_reg3_reg, vertex_fifo_full) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vertex_fifo_full_MASK) | (vertex_fifo_full << SXIFCCG_DEBUG_REG3_vertex_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO1(sxifccg_debug_reg3_reg, always_zero1) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_MASK) | (always_zero1 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_sx0_receive_fifo_empty(sxifccg_debug_reg3_reg, sx0_receive_fifo_empty) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_MASK) | (sx0_receive_fifo_empty << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_sx0_receive_fifo_full(sxifccg_debug_reg3_reg, sx0_receive_fifo_full) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_MASK) | (sx0_receive_fifo_full << SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_vgt_to_ccgen_fifo_empty(sxifccg_debug_reg3_reg, vgt_to_ccgen_fifo_empty) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_MASK) | (vgt_to_ccgen_fifo_empty << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_vgt_to_ccgen_fifo_full(sxifccg_debug_reg3_reg, vgt_to_ccgen_fifo_full) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_MASK) | (vgt_to_ccgen_fifo_full << SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SHIFT) +#define SXIFCCG_DEBUG_REG3_SET_ALWAYS_ZERO0(sxifccg_debug_reg3_reg, always_zero0) \ + sxifccg_debug_reg3_reg = (sxifccg_debug_reg3_reg & ~SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_MASK) | (always_zero0 << SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg3_t { + unsigned int vertex_fifo_entriesavailable : SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE; + unsigned int available_positions : SXIFCCG_DEBUG_REG3_available_positions_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE; + unsigned int current_state : SXIFCCG_DEBUG_REG3_current_state_SIZE; + unsigned int vertex_fifo_empty : SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE; + unsigned int vertex_fifo_full : SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE; + unsigned int sx0_receive_fifo_empty : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE; + unsigned int sx0_receive_fifo_full : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE; + unsigned int vgt_to_ccgen_fifo_empty : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE; + unsigned int vgt_to_ccgen_fifo_full : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE; + unsigned int always_zero0 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE; + } sxifccg_debug_reg3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sxifccg_debug_reg3_t { + unsigned int always_zero0 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO0_SIZE; + unsigned int vgt_to_ccgen_fifo_full : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_full_SIZE; + unsigned int vgt_to_ccgen_fifo_empty : SXIFCCG_DEBUG_REG3_vgt_to_ccgen_fifo_empty_SIZE; + unsigned int sx0_receive_fifo_full : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_full_SIZE; + unsigned int sx0_receive_fifo_empty : SXIFCCG_DEBUG_REG3_sx0_receive_fifo_empty_SIZE; + unsigned int always_zero1 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO1_SIZE; + unsigned int vertex_fifo_full : SXIFCCG_DEBUG_REG3_vertex_fifo_full_SIZE; + unsigned int vertex_fifo_empty : SXIFCCG_DEBUG_REG3_vertex_fifo_empty_SIZE; + unsigned int current_state : SXIFCCG_DEBUG_REG3_current_state_SIZE; + unsigned int always_zero2 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO2_SIZE; + unsigned int available_positions : SXIFCCG_DEBUG_REG3_available_positions_SIZE; + unsigned int always_zero3 : SXIFCCG_DEBUG_REG3_ALWAYS_ZERO3_SIZE; + unsigned int vertex_fifo_entriesavailable : SXIFCCG_DEBUG_REG3_vertex_fifo_entriesavailable_SIZE; + } sxifccg_debug_reg3_t; + +#endif + +typedef union { + unsigned int val : 32; + sxifccg_debug_reg3_t f; +} sxifccg_debug_reg3_u; + + +/* + * SETUP_DEBUG_REG0 struct + */ + +#define SETUP_DEBUG_REG0_su_cntl_state_SIZE 5 +#define SETUP_DEBUG_REG0_pmode_state_SIZE 6 +#define SETUP_DEBUG_REG0_ge_stallb_SIZE 1 +#define SETUP_DEBUG_REG0_geom_enable_SIZE 1 +#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE 1 +#define SETUP_DEBUG_REG0_su_clip_rtr_SIZE 1 +#define SETUP_DEBUG_REG0_pfifo_busy_SIZE 1 +#define SETUP_DEBUG_REG0_su_cntl_busy_SIZE 1 +#define SETUP_DEBUG_REG0_geom_busy_SIZE 1 + +#define SETUP_DEBUG_REG0_su_cntl_state_SHIFT 0 +#define SETUP_DEBUG_REG0_pmode_state_SHIFT 5 +#define SETUP_DEBUG_REG0_ge_stallb_SHIFT 11 +#define SETUP_DEBUG_REG0_geom_enable_SHIFT 12 +#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT 13 +#define SETUP_DEBUG_REG0_su_clip_rtr_SHIFT 14 +#define SETUP_DEBUG_REG0_pfifo_busy_SHIFT 15 +#define SETUP_DEBUG_REG0_su_cntl_busy_SHIFT 16 +#define SETUP_DEBUG_REG0_geom_busy_SHIFT 17 + +#define SETUP_DEBUG_REG0_su_cntl_state_MASK 0x0000001f +#define SETUP_DEBUG_REG0_pmode_state_MASK 0x000007e0 +#define SETUP_DEBUG_REG0_ge_stallb_MASK 0x00000800 +#define SETUP_DEBUG_REG0_geom_enable_MASK 0x00001000 +#define SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK 0x00002000 +#define SETUP_DEBUG_REG0_su_clip_rtr_MASK 0x00004000 +#define SETUP_DEBUG_REG0_pfifo_busy_MASK 0x00008000 +#define SETUP_DEBUG_REG0_su_cntl_busy_MASK 0x00010000 +#define SETUP_DEBUG_REG0_geom_busy_MASK 0x00020000 + +#define SETUP_DEBUG_REG0_MASK \ + (SETUP_DEBUG_REG0_su_cntl_state_MASK | \ + SETUP_DEBUG_REG0_pmode_state_MASK | \ + SETUP_DEBUG_REG0_ge_stallb_MASK | \ + SETUP_DEBUG_REG0_geom_enable_MASK | \ + SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK | \ + SETUP_DEBUG_REG0_su_clip_rtr_MASK | \ + SETUP_DEBUG_REG0_pfifo_busy_MASK | \ + SETUP_DEBUG_REG0_su_cntl_busy_MASK | \ + SETUP_DEBUG_REG0_geom_busy_MASK) + +#define SETUP_DEBUG_REG0(su_cntl_state, pmode_state, ge_stallb, geom_enable, su_clip_baryc_rtr, su_clip_rtr, pfifo_busy, su_cntl_busy, geom_busy) \ + ((su_cntl_state << SETUP_DEBUG_REG0_su_cntl_state_SHIFT) | \ + (pmode_state << SETUP_DEBUG_REG0_pmode_state_SHIFT) | \ + (ge_stallb << SETUP_DEBUG_REG0_ge_stallb_SHIFT) | \ + (geom_enable << SETUP_DEBUG_REG0_geom_enable_SHIFT) | \ + (su_clip_baryc_rtr << SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT) | \ + (su_clip_rtr << SETUP_DEBUG_REG0_su_clip_rtr_SHIFT) | \ + (pfifo_busy << SETUP_DEBUG_REG0_pfifo_busy_SHIFT) | \ + (su_cntl_busy << SETUP_DEBUG_REG0_su_cntl_busy_SHIFT) | \ + (geom_busy << SETUP_DEBUG_REG0_geom_busy_SHIFT)) + +#define SETUP_DEBUG_REG0_GET_su_cntl_state(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_cntl_state_MASK) >> SETUP_DEBUG_REG0_su_cntl_state_SHIFT) +#define SETUP_DEBUG_REG0_GET_pmode_state(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_pmode_state_MASK) >> SETUP_DEBUG_REG0_pmode_state_SHIFT) +#define SETUP_DEBUG_REG0_GET_ge_stallb(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_ge_stallb_MASK) >> SETUP_DEBUG_REG0_ge_stallb_SHIFT) +#define SETUP_DEBUG_REG0_GET_geom_enable(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_geom_enable_MASK) >> SETUP_DEBUG_REG0_geom_enable_SHIFT) +#define SETUP_DEBUG_REG0_GET_su_clip_baryc_rtr(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK) >> SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT) +#define SETUP_DEBUG_REG0_GET_su_clip_rtr(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_clip_rtr_MASK) >> SETUP_DEBUG_REG0_su_clip_rtr_SHIFT) +#define SETUP_DEBUG_REG0_GET_pfifo_busy(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_pfifo_busy_MASK) >> SETUP_DEBUG_REG0_pfifo_busy_SHIFT) +#define SETUP_DEBUG_REG0_GET_su_cntl_busy(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_su_cntl_busy_MASK) >> SETUP_DEBUG_REG0_su_cntl_busy_SHIFT) +#define SETUP_DEBUG_REG0_GET_geom_busy(setup_debug_reg0) \ + ((setup_debug_reg0 & SETUP_DEBUG_REG0_geom_busy_MASK) >> SETUP_DEBUG_REG0_geom_busy_SHIFT) + +#define SETUP_DEBUG_REG0_SET_su_cntl_state(setup_debug_reg0_reg, su_cntl_state) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_cntl_state_MASK) | (su_cntl_state << SETUP_DEBUG_REG0_su_cntl_state_SHIFT) +#define SETUP_DEBUG_REG0_SET_pmode_state(setup_debug_reg0_reg, pmode_state) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_pmode_state_MASK) | (pmode_state << SETUP_DEBUG_REG0_pmode_state_SHIFT) +#define SETUP_DEBUG_REG0_SET_ge_stallb(setup_debug_reg0_reg, ge_stallb) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_ge_stallb_MASK) | (ge_stallb << SETUP_DEBUG_REG0_ge_stallb_SHIFT) +#define SETUP_DEBUG_REG0_SET_geom_enable(setup_debug_reg0_reg, geom_enable) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_geom_enable_MASK) | (geom_enable << SETUP_DEBUG_REG0_geom_enable_SHIFT) +#define SETUP_DEBUG_REG0_SET_su_clip_baryc_rtr(setup_debug_reg0_reg, su_clip_baryc_rtr) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_clip_baryc_rtr_MASK) | (su_clip_baryc_rtr << SETUP_DEBUG_REG0_su_clip_baryc_rtr_SHIFT) +#define SETUP_DEBUG_REG0_SET_su_clip_rtr(setup_debug_reg0_reg, su_clip_rtr) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_clip_rtr_MASK) | (su_clip_rtr << SETUP_DEBUG_REG0_su_clip_rtr_SHIFT) +#define SETUP_DEBUG_REG0_SET_pfifo_busy(setup_debug_reg0_reg, pfifo_busy) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_pfifo_busy_MASK) | (pfifo_busy << SETUP_DEBUG_REG0_pfifo_busy_SHIFT) +#define SETUP_DEBUG_REG0_SET_su_cntl_busy(setup_debug_reg0_reg, su_cntl_busy) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_su_cntl_busy_MASK) | (su_cntl_busy << SETUP_DEBUG_REG0_su_cntl_busy_SHIFT) +#define SETUP_DEBUG_REG0_SET_geom_busy(setup_debug_reg0_reg, geom_busy) \ + setup_debug_reg0_reg = (setup_debug_reg0_reg & ~SETUP_DEBUG_REG0_geom_busy_MASK) | (geom_busy << SETUP_DEBUG_REG0_geom_busy_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg0_t { + unsigned int su_cntl_state : SETUP_DEBUG_REG0_su_cntl_state_SIZE; + unsigned int pmode_state : SETUP_DEBUG_REG0_pmode_state_SIZE; + unsigned int ge_stallb : SETUP_DEBUG_REG0_ge_stallb_SIZE; + unsigned int geom_enable : SETUP_DEBUG_REG0_geom_enable_SIZE; + unsigned int su_clip_baryc_rtr : SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE; + unsigned int su_clip_rtr : SETUP_DEBUG_REG0_su_clip_rtr_SIZE; + unsigned int pfifo_busy : SETUP_DEBUG_REG0_pfifo_busy_SIZE; + unsigned int su_cntl_busy : SETUP_DEBUG_REG0_su_cntl_busy_SIZE; + unsigned int geom_busy : SETUP_DEBUG_REG0_geom_busy_SIZE; + unsigned int : 14; + } setup_debug_reg0_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg0_t { + unsigned int : 14; + unsigned int geom_busy : SETUP_DEBUG_REG0_geom_busy_SIZE; + unsigned int su_cntl_busy : SETUP_DEBUG_REG0_su_cntl_busy_SIZE; + unsigned int pfifo_busy : SETUP_DEBUG_REG0_pfifo_busy_SIZE; + unsigned int su_clip_rtr : SETUP_DEBUG_REG0_su_clip_rtr_SIZE; + unsigned int su_clip_baryc_rtr : SETUP_DEBUG_REG0_su_clip_baryc_rtr_SIZE; + unsigned int geom_enable : SETUP_DEBUG_REG0_geom_enable_SIZE; + unsigned int ge_stallb : SETUP_DEBUG_REG0_ge_stallb_SIZE; + unsigned int pmode_state : SETUP_DEBUG_REG0_pmode_state_SIZE; + unsigned int su_cntl_state : SETUP_DEBUG_REG0_su_cntl_state_SIZE; + } setup_debug_reg0_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg0_t f; +} setup_debug_reg0_u; + + +/* + * SETUP_DEBUG_REG1 struct + */ + +#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE 14 +#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE 14 + +#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT 0 +#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT 14 + +#define SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK 0x00003fff +#define SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK 0x0fffc000 + +#define SETUP_DEBUG_REG1_MASK \ + (SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK | \ + SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) + +#define SETUP_DEBUG_REG1(y_sort0_gated_17_4, x_sort0_gated_17_4) \ + ((y_sort0_gated_17_4 << SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT) | \ + (x_sort0_gated_17_4 << SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT)) + +#define SETUP_DEBUG_REG1_GET_y_sort0_gated_17_4(setup_debug_reg1) \ + ((setup_debug_reg1 & SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK) >> SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG1_GET_x_sort0_gated_17_4(setup_debug_reg1) \ + ((setup_debug_reg1 & SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) >> SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT) + +#define SETUP_DEBUG_REG1_SET_y_sort0_gated_17_4(setup_debug_reg1_reg, y_sort0_gated_17_4) \ + setup_debug_reg1_reg = (setup_debug_reg1_reg & ~SETUP_DEBUG_REG1_y_sort0_gated_17_4_MASK) | (y_sort0_gated_17_4 << SETUP_DEBUG_REG1_y_sort0_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG1_SET_x_sort0_gated_17_4(setup_debug_reg1_reg, x_sort0_gated_17_4) \ + setup_debug_reg1_reg = (setup_debug_reg1_reg & ~SETUP_DEBUG_REG1_x_sort0_gated_17_4_MASK) | (x_sort0_gated_17_4 << SETUP_DEBUG_REG1_x_sort0_gated_17_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg1_t { + unsigned int y_sort0_gated_17_4 : SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE; + unsigned int x_sort0_gated_17_4 : SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE; + unsigned int : 4; + } setup_debug_reg1_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg1_t { + unsigned int : 4; + unsigned int x_sort0_gated_17_4 : SETUP_DEBUG_REG1_x_sort0_gated_17_4_SIZE; + unsigned int y_sort0_gated_17_4 : SETUP_DEBUG_REG1_y_sort0_gated_17_4_SIZE; + } setup_debug_reg1_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg1_t f; +} setup_debug_reg1_u; + + +/* + * SETUP_DEBUG_REG2 struct + */ + +#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE 14 +#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE 14 + +#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT 0 +#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT 14 + +#define SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK 0x00003fff +#define SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK 0x0fffc000 + +#define SETUP_DEBUG_REG2_MASK \ + (SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK | \ + SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) + +#define SETUP_DEBUG_REG2(y_sort1_gated_17_4, x_sort1_gated_17_4) \ + ((y_sort1_gated_17_4 << SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT) | \ + (x_sort1_gated_17_4 << SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT)) + +#define SETUP_DEBUG_REG2_GET_y_sort1_gated_17_4(setup_debug_reg2) \ + ((setup_debug_reg2 & SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK) >> SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG2_GET_x_sort1_gated_17_4(setup_debug_reg2) \ + ((setup_debug_reg2 & SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) >> SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT) + +#define SETUP_DEBUG_REG2_SET_y_sort1_gated_17_4(setup_debug_reg2_reg, y_sort1_gated_17_4) \ + setup_debug_reg2_reg = (setup_debug_reg2_reg & ~SETUP_DEBUG_REG2_y_sort1_gated_17_4_MASK) | (y_sort1_gated_17_4 << SETUP_DEBUG_REG2_y_sort1_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG2_SET_x_sort1_gated_17_4(setup_debug_reg2_reg, x_sort1_gated_17_4) \ + setup_debug_reg2_reg = (setup_debug_reg2_reg & ~SETUP_DEBUG_REG2_x_sort1_gated_17_4_MASK) | (x_sort1_gated_17_4 << SETUP_DEBUG_REG2_x_sort1_gated_17_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg2_t { + unsigned int y_sort1_gated_17_4 : SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE; + unsigned int x_sort1_gated_17_4 : SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE; + unsigned int : 4; + } setup_debug_reg2_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg2_t { + unsigned int : 4; + unsigned int x_sort1_gated_17_4 : SETUP_DEBUG_REG2_x_sort1_gated_17_4_SIZE; + unsigned int y_sort1_gated_17_4 : SETUP_DEBUG_REG2_y_sort1_gated_17_4_SIZE; + } setup_debug_reg2_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg2_t f; +} setup_debug_reg2_u; + + +/* + * SETUP_DEBUG_REG3 struct + */ + +#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE 14 +#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE 14 + +#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT 0 +#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT 14 + +#define SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK 0x00003fff +#define SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK 0x0fffc000 + +#define SETUP_DEBUG_REG3_MASK \ + (SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK | \ + SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) + +#define SETUP_DEBUG_REG3(y_sort2_gated_17_4, x_sort2_gated_17_4) \ + ((y_sort2_gated_17_4 << SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT) | \ + (x_sort2_gated_17_4 << SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT)) + +#define SETUP_DEBUG_REG3_GET_y_sort2_gated_17_4(setup_debug_reg3) \ + ((setup_debug_reg3 & SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK) >> SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG3_GET_x_sort2_gated_17_4(setup_debug_reg3) \ + ((setup_debug_reg3 & SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) >> SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT) + +#define SETUP_DEBUG_REG3_SET_y_sort2_gated_17_4(setup_debug_reg3_reg, y_sort2_gated_17_4) \ + setup_debug_reg3_reg = (setup_debug_reg3_reg & ~SETUP_DEBUG_REG3_y_sort2_gated_17_4_MASK) | (y_sort2_gated_17_4 << SETUP_DEBUG_REG3_y_sort2_gated_17_4_SHIFT) +#define SETUP_DEBUG_REG3_SET_x_sort2_gated_17_4(setup_debug_reg3_reg, x_sort2_gated_17_4) \ + setup_debug_reg3_reg = (setup_debug_reg3_reg & ~SETUP_DEBUG_REG3_x_sort2_gated_17_4_MASK) | (x_sort2_gated_17_4 << SETUP_DEBUG_REG3_x_sort2_gated_17_4_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg3_t { + unsigned int y_sort2_gated_17_4 : SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE; + unsigned int x_sort2_gated_17_4 : SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE; + unsigned int : 4; + } setup_debug_reg3_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg3_t { + unsigned int : 4; + unsigned int x_sort2_gated_17_4 : SETUP_DEBUG_REG3_x_sort2_gated_17_4_SIZE; + unsigned int y_sort2_gated_17_4 : SETUP_DEBUG_REG3_y_sort2_gated_17_4_SIZE; + } setup_debug_reg3_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg3_t f; +} setup_debug_reg3_u; + + +/* + * SETUP_DEBUG_REG4 struct + */ + +#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE 11 +#define SETUP_DEBUG_REG4_null_prim_gated_SIZE 1 +#define SETUP_DEBUG_REG4_backfacing_gated_SIZE 1 +#define SETUP_DEBUG_REG4_st_indx_gated_SIZE 3 +#define SETUP_DEBUG_REG4_clipped_gated_SIZE 1 +#define SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE 3 +#define SETUP_DEBUG_REG4_xmajor_gated_SIZE 1 +#define SETUP_DEBUG_REG4_diamond_rule_gated_SIZE 2 +#define SETUP_DEBUG_REG4_type_gated_SIZE 3 +#define SETUP_DEBUG_REG4_fpov_gated_SIZE 1 +#define SETUP_DEBUG_REG4_pmode_prim_gated_SIZE 1 +#define SETUP_DEBUG_REG4_event_gated_SIZE 1 +#define SETUP_DEBUG_REG4_eop_gated_SIZE 1 + +#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT 0 +#define SETUP_DEBUG_REG4_null_prim_gated_SHIFT 11 +#define SETUP_DEBUG_REG4_backfacing_gated_SHIFT 12 +#define SETUP_DEBUG_REG4_st_indx_gated_SHIFT 13 +#define SETUP_DEBUG_REG4_clipped_gated_SHIFT 16 +#define SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT 17 +#define SETUP_DEBUG_REG4_xmajor_gated_SHIFT 20 +#define SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT 21 +#define SETUP_DEBUG_REG4_type_gated_SHIFT 23 +#define SETUP_DEBUG_REG4_fpov_gated_SHIFT 26 +#define SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT 27 +#define SETUP_DEBUG_REG4_event_gated_SHIFT 28 +#define SETUP_DEBUG_REG4_eop_gated_SHIFT 29 + +#define SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK 0x000007ff +#define SETUP_DEBUG_REG4_null_prim_gated_MASK 0x00000800 +#define SETUP_DEBUG_REG4_backfacing_gated_MASK 0x00001000 +#define SETUP_DEBUG_REG4_st_indx_gated_MASK 0x0000e000 +#define SETUP_DEBUG_REG4_clipped_gated_MASK 0x00010000 +#define SETUP_DEBUG_REG4_dealloc_slot_gated_MASK 0x000e0000 +#define SETUP_DEBUG_REG4_xmajor_gated_MASK 0x00100000 +#define SETUP_DEBUG_REG4_diamond_rule_gated_MASK 0x00600000 +#define SETUP_DEBUG_REG4_type_gated_MASK 0x03800000 +#define SETUP_DEBUG_REG4_fpov_gated_MASK 0x04000000 +#define SETUP_DEBUG_REG4_pmode_prim_gated_MASK 0x08000000 +#define SETUP_DEBUG_REG4_event_gated_MASK 0x10000000 +#define SETUP_DEBUG_REG4_eop_gated_MASK 0x20000000 + +#define SETUP_DEBUG_REG4_MASK \ + (SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK | \ + SETUP_DEBUG_REG4_null_prim_gated_MASK | \ + SETUP_DEBUG_REG4_backfacing_gated_MASK | \ + SETUP_DEBUG_REG4_st_indx_gated_MASK | \ + SETUP_DEBUG_REG4_clipped_gated_MASK | \ + SETUP_DEBUG_REG4_dealloc_slot_gated_MASK | \ + SETUP_DEBUG_REG4_xmajor_gated_MASK | \ + SETUP_DEBUG_REG4_diamond_rule_gated_MASK | \ + SETUP_DEBUG_REG4_type_gated_MASK | \ + SETUP_DEBUG_REG4_fpov_gated_MASK | \ + SETUP_DEBUG_REG4_pmode_prim_gated_MASK | \ + SETUP_DEBUG_REG4_event_gated_MASK | \ + SETUP_DEBUG_REG4_eop_gated_MASK) + +#define SETUP_DEBUG_REG4(attr_indx_sort0_gated, null_prim_gated, backfacing_gated, st_indx_gated, clipped_gated, dealloc_slot_gated, xmajor_gated, diamond_rule_gated, type_gated, fpov_gated, pmode_prim_gated, event_gated, eop_gated) \ + ((attr_indx_sort0_gated << SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT) | \ + (null_prim_gated << SETUP_DEBUG_REG4_null_prim_gated_SHIFT) | \ + (backfacing_gated << SETUP_DEBUG_REG4_backfacing_gated_SHIFT) | \ + (st_indx_gated << SETUP_DEBUG_REG4_st_indx_gated_SHIFT) | \ + (clipped_gated << SETUP_DEBUG_REG4_clipped_gated_SHIFT) | \ + (dealloc_slot_gated << SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT) | \ + (xmajor_gated << SETUP_DEBUG_REG4_xmajor_gated_SHIFT) | \ + (diamond_rule_gated << SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT) | \ + (type_gated << SETUP_DEBUG_REG4_type_gated_SHIFT) | \ + (fpov_gated << SETUP_DEBUG_REG4_fpov_gated_SHIFT) | \ + (pmode_prim_gated << SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT) | \ + (event_gated << SETUP_DEBUG_REG4_event_gated_SHIFT) | \ + (eop_gated << SETUP_DEBUG_REG4_eop_gated_SHIFT)) + +#define SETUP_DEBUG_REG4_GET_attr_indx_sort0_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK) >> SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_null_prim_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_null_prim_gated_MASK) >> SETUP_DEBUG_REG4_null_prim_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_backfacing_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_backfacing_gated_MASK) >> SETUP_DEBUG_REG4_backfacing_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_st_indx_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_st_indx_gated_MASK) >> SETUP_DEBUG_REG4_st_indx_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_clipped_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_clipped_gated_MASK) >> SETUP_DEBUG_REG4_clipped_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_dealloc_slot_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_dealloc_slot_gated_MASK) >> SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_xmajor_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_xmajor_gated_MASK) >> SETUP_DEBUG_REG4_xmajor_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_diamond_rule_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_diamond_rule_gated_MASK) >> SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_type_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_type_gated_MASK) >> SETUP_DEBUG_REG4_type_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_fpov_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_fpov_gated_MASK) >> SETUP_DEBUG_REG4_fpov_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_pmode_prim_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_pmode_prim_gated_MASK) >> SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_event_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_event_gated_MASK) >> SETUP_DEBUG_REG4_event_gated_SHIFT) +#define SETUP_DEBUG_REG4_GET_eop_gated(setup_debug_reg4) \ + ((setup_debug_reg4 & SETUP_DEBUG_REG4_eop_gated_MASK) >> SETUP_DEBUG_REG4_eop_gated_SHIFT) + +#define SETUP_DEBUG_REG4_SET_attr_indx_sort0_gated(setup_debug_reg4_reg, attr_indx_sort0_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_attr_indx_sort0_gated_MASK) | (attr_indx_sort0_gated << SETUP_DEBUG_REG4_attr_indx_sort0_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_null_prim_gated(setup_debug_reg4_reg, null_prim_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_null_prim_gated_MASK) | (null_prim_gated << SETUP_DEBUG_REG4_null_prim_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_backfacing_gated(setup_debug_reg4_reg, backfacing_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_backfacing_gated_MASK) | (backfacing_gated << SETUP_DEBUG_REG4_backfacing_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_st_indx_gated(setup_debug_reg4_reg, st_indx_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_st_indx_gated_MASK) | (st_indx_gated << SETUP_DEBUG_REG4_st_indx_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_clipped_gated(setup_debug_reg4_reg, clipped_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_clipped_gated_MASK) | (clipped_gated << SETUP_DEBUG_REG4_clipped_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_dealloc_slot_gated(setup_debug_reg4_reg, dealloc_slot_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_dealloc_slot_gated_MASK) | (dealloc_slot_gated << SETUP_DEBUG_REG4_dealloc_slot_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_xmajor_gated(setup_debug_reg4_reg, xmajor_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_xmajor_gated_MASK) | (xmajor_gated << SETUP_DEBUG_REG4_xmajor_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_diamond_rule_gated(setup_debug_reg4_reg, diamond_rule_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_diamond_rule_gated_MASK) | (diamond_rule_gated << SETUP_DEBUG_REG4_diamond_rule_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_type_gated(setup_debug_reg4_reg, type_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_type_gated_MASK) | (type_gated << SETUP_DEBUG_REG4_type_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_fpov_gated(setup_debug_reg4_reg, fpov_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_fpov_gated_MASK) | (fpov_gated << SETUP_DEBUG_REG4_fpov_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_pmode_prim_gated(setup_debug_reg4_reg, pmode_prim_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_pmode_prim_gated_MASK) | (pmode_prim_gated << SETUP_DEBUG_REG4_pmode_prim_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_event_gated(setup_debug_reg4_reg, event_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_event_gated_MASK) | (event_gated << SETUP_DEBUG_REG4_event_gated_SHIFT) +#define SETUP_DEBUG_REG4_SET_eop_gated(setup_debug_reg4_reg, eop_gated) \ + setup_debug_reg4_reg = (setup_debug_reg4_reg & ~SETUP_DEBUG_REG4_eop_gated_MASK) | (eop_gated << SETUP_DEBUG_REG4_eop_gated_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg4_t { + unsigned int attr_indx_sort0_gated : SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE; + unsigned int null_prim_gated : SETUP_DEBUG_REG4_null_prim_gated_SIZE; + unsigned int backfacing_gated : SETUP_DEBUG_REG4_backfacing_gated_SIZE; + unsigned int st_indx_gated : SETUP_DEBUG_REG4_st_indx_gated_SIZE; + unsigned int clipped_gated : SETUP_DEBUG_REG4_clipped_gated_SIZE; + unsigned int dealloc_slot_gated : SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE; + unsigned int xmajor_gated : SETUP_DEBUG_REG4_xmajor_gated_SIZE; + unsigned int diamond_rule_gated : SETUP_DEBUG_REG4_diamond_rule_gated_SIZE; + unsigned int type_gated : SETUP_DEBUG_REG4_type_gated_SIZE; + unsigned int fpov_gated : SETUP_DEBUG_REG4_fpov_gated_SIZE; + unsigned int pmode_prim_gated : SETUP_DEBUG_REG4_pmode_prim_gated_SIZE; + unsigned int event_gated : SETUP_DEBUG_REG4_event_gated_SIZE; + unsigned int eop_gated : SETUP_DEBUG_REG4_eop_gated_SIZE; + unsigned int : 2; + } setup_debug_reg4_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg4_t { + unsigned int : 2; + unsigned int eop_gated : SETUP_DEBUG_REG4_eop_gated_SIZE; + unsigned int event_gated : SETUP_DEBUG_REG4_event_gated_SIZE; + unsigned int pmode_prim_gated : SETUP_DEBUG_REG4_pmode_prim_gated_SIZE; + unsigned int fpov_gated : SETUP_DEBUG_REG4_fpov_gated_SIZE; + unsigned int type_gated : SETUP_DEBUG_REG4_type_gated_SIZE; + unsigned int diamond_rule_gated : SETUP_DEBUG_REG4_diamond_rule_gated_SIZE; + unsigned int xmajor_gated : SETUP_DEBUG_REG4_xmajor_gated_SIZE; + unsigned int dealloc_slot_gated : SETUP_DEBUG_REG4_dealloc_slot_gated_SIZE; + unsigned int clipped_gated : SETUP_DEBUG_REG4_clipped_gated_SIZE; + unsigned int st_indx_gated : SETUP_DEBUG_REG4_st_indx_gated_SIZE; + unsigned int backfacing_gated : SETUP_DEBUG_REG4_backfacing_gated_SIZE; + unsigned int null_prim_gated : SETUP_DEBUG_REG4_null_prim_gated_SIZE; + unsigned int attr_indx_sort0_gated : SETUP_DEBUG_REG4_attr_indx_sort0_gated_SIZE; + } setup_debug_reg4_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg4_t f; +} setup_debug_reg4_u; + + +/* + * SETUP_DEBUG_REG5 struct + */ + +#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE 11 +#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE 11 +#define SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE 2 +#define SETUP_DEBUG_REG5_event_id_gated_SIZE 5 + +#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT 0 +#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT 11 +#define SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT 22 +#define SETUP_DEBUG_REG5_event_id_gated_SHIFT 24 + +#define SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK 0x000007ff +#define SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK 0x003ff800 +#define SETUP_DEBUG_REG5_provoking_vtx_gated_MASK 0x00c00000 +#define SETUP_DEBUG_REG5_event_id_gated_MASK 0x1f000000 + +#define SETUP_DEBUG_REG5_MASK \ + (SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK | \ + SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK | \ + SETUP_DEBUG_REG5_provoking_vtx_gated_MASK | \ + SETUP_DEBUG_REG5_event_id_gated_MASK) + +#define SETUP_DEBUG_REG5(attr_indx_sort2_gated, attr_indx_sort1_gated, provoking_vtx_gated, event_id_gated) \ + ((attr_indx_sort2_gated << SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT) | \ + (attr_indx_sort1_gated << SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT) | \ + (provoking_vtx_gated << SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT) | \ + (event_id_gated << SETUP_DEBUG_REG5_event_id_gated_SHIFT)) + +#define SETUP_DEBUG_REG5_GET_attr_indx_sort2_gated(setup_debug_reg5) \ + ((setup_debug_reg5 & SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK) >> SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT) +#define SETUP_DEBUG_REG5_GET_attr_indx_sort1_gated(setup_debug_reg5) \ + ((setup_debug_reg5 & SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK) >> SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT) +#define SETUP_DEBUG_REG5_GET_provoking_vtx_gated(setup_debug_reg5) \ + ((setup_debug_reg5 & SETUP_DEBUG_REG5_provoking_vtx_gated_MASK) >> SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT) +#define SETUP_DEBUG_REG5_GET_event_id_gated(setup_debug_reg5) \ + ((setup_debug_reg5 & SETUP_DEBUG_REG5_event_id_gated_MASK) >> SETUP_DEBUG_REG5_event_id_gated_SHIFT) + +#define SETUP_DEBUG_REG5_SET_attr_indx_sort2_gated(setup_debug_reg5_reg, attr_indx_sort2_gated) \ + setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_attr_indx_sort2_gated_MASK) | (attr_indx_sort2_gated << SETUP_DEBUG_REG5_attr_indx_sort2_gated_SHIFT) +#define SETUP_DEBUG_REG5_SET_attr_indx_sort1_gated(setup_debug_reg5_reg, attr_indx_sort1_gated) \ + setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_attr_indx_sort1_gated_MASK) | (attr_indx_sort1_gated << SETUP_DEBUG_REG5_attr_indx_sort1_gated_SHIFT) +#define SETUP_DEBUG_REG5_SET_provoking_vtx_gated(setup_debug_reg5_reg, provoking_vtx_gated) \ + setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_provoking_vtx_gated_MASK) | (provoking_vtx_gated << SETUP_DEBUG_REG5_provoking_vtx_gated_SHIFT) +#define SETUP_DEBUG_REG5_SET_event_id_gated(setup_debug_reg5_reg, event_id_gated) \ + setup_debug_reg5_reg = (setup_debug_reg5_reg & ~SETUP_DEBUG_REG5_event_id_gated_MASK) | (event_id_gated << SETUP_DEBUG_REG5_event_id_gated_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _setup_debug_reg5_t { + unsigned int attr_indx_sort2_gated : SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE; + unsigned int attr_indx_sort1_gated : SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE; + unsigned int provoking_vtx_gated : SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE; + unsigned int event_id_gated : SETUP_DEBUG_REG5_event_id_gated_SIZE; + unsigned int : 3; + } setup_debug_reg5_t; + +#else // !BIGENDIAN_OS + + typedef struct _setup_debug_reg5_t { + unsigned int : 3; + unsigned int event_id_gated : SETUP_DEBUG_REG5_event_id_gated_SIZE; + unsigned int provoking_vtx_gated : SETUP_DEBUG_REG5_provoking_vtx_gated_SIZE; + unsigned int attr_indx_sort1_gated : SETUP_DEBUG_REG5_attr_indx_sort1_gated_SIZE; + unsigned int attr_indx_sort2_gated : SETUP_DEBUG_REG5_attr_indx_sort2_gated_SIZE; + } setup_debug_reg5_t; + +#endif + +typedef union { + unsigned int val : 32; + setup_debug_reg5_t f; +} setup_debug_reg5_u; + + +/* + * PA_SC_DEBUG_CNTL struct + */ + +#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE 5 + +#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT 0 + +#define PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK 0x0000001f + +#define PA_SC_DEBUG_CNTL_MASK \ + (PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) + +#define PA_SC_DEBUG_CNTL(sc_debug_indx) \ + ((sc_debug_indx << PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT)) + +#define PA_SC_DEBUG_CNTL_GET_SC_DEBUG_INDX(pa_sc_debug_cntl) \ + ((pa_sc_debug_cntl & PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) >> PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT) + +#define PA_SC_DEBUG_CNTL_SET_SC_DEBUG_INDX(pa_sc_debug_cntl_reg, sc_debug_indx) \ + pa_sc_debug_cntl_reg = (pa_sc_debug_cntl_reg & ~PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_MASK) | (sc_debug_indx << PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_debug_cntl_t { + unsigned int sc_debug_indx : PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE; + unsigned int : 27; + } pa_sc_debug_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_debug_cntl_t { + unsigned int : 27; + unsigned int sc_debug_indx : PA_SC_DEBUG_CNTL_SC_DEBUG_INDX_SIZE; + } pa_sc_debug_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_debug_cntl_t f; +} pa_sc_debug_cntl_u; + + +/* + * PA_SC_DEBUG_DATA struct + */ + +#define PA_SC_DEBUG_DATA_DATA_SIZE 32 + +#define PA_SC_DEBUG_DATA_DATA_SHIFT 0 + +#define PA_SC_DEBUG_DATA_DATA_MASK 0xffffffff + +#define PA_SC_DEBUG_DATA_MASK \ + (PA_SC_DEBUG_DATA_DATA_MASK) + +#define PA_SC_DEBUG_DATA(data) \ + ((data << PA_SC_DEBUG_DATA_DATA_SHIFT)) + +#define PA_SC_DEBUG_DATA_GET_DATA(pa_sc_debug_data) \ + ((pa_sc_debug_data & PA_SC_DEBUG_DATA_DATA_MASK) >> PA_SC_DEBUG_DATA_DATA_SHIFT) + +#define PA_SC_DEBUG_DATA_SET_DATA(pa_sc_debug_data_reg, data) \ + pa_sc_debug_data_reg = (pa_sc_debug_data_reg & ~PA_SC_DEBUG_DATA_DATA_MASK) | (data << PA_SC_DEBUG_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _pa_sc_debug_data_t { + unsigned int data : PA_SC_DEBUG_DATA_DATA_SIZE; + } pa_sc_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _pa_sc_debug_data_t { + unsigned int data : PA_SC_DEBUG_DATA_DATA_SIZE; + } pa_sc_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + pa_sc_debug_data_t f; +} pa_sc_debug_data_u; + + +/* + * SC_DEBUG_0 struct + */ + +#define SC_DEBUG_0_pa_freeze_b1_SIZE 1 +#define SC_DEBUG_0_pa_sc_valid_SIZE 1 +#define SC_DEBUG_0_pa_sc_phase_SIZE 3 +#define SC_DEBUG_0_cntx_cnt_SIZE 7 +#define SC_DEBUG_0_decr_cntx_cnt_SIZE 1 +#define SC_DEBUG_0_incr_cntx_cnt_SIZE 1 +#define SC_DEBUG_0_trigger_SIZE 1 + +#define SC_DEBUG_0_pa_freeze_b1_SHIFT 0 +#define SC_DEBUG_0_pa_sc_valid_SHIFT 1 +#define SC_DEBUG_0_pa_sc_phase_SHIFT 2 +#define SC_DEBUG_0_cntx_cnt_SHIFT 5 +#define SC_DEBUG_0_decr_cntx_cnt_SHIFT 12 +#define SC_DEBUG_0_incr_cntx_cnt_SHIFT 13 +#define SC_DEBUG_0_trigger_SHIFT 31 + +#define SC_DEBUG_0_pa_freeze_b1_MASK 0x00000001 +#define SC_DEBUG_0_pa_sc_valid_MASK 0x00000002 +#define SC_DEBUG_0_pa_sc_phase_MASK 0x0000001c +#define SC_DEBUG_0_cntx_cnt_MASK 0x00000fe0 +#define SC_DEBUG_0_decr_cntx_cnt_MASK 0x00001000 +#define SC_DEBUG_0_incr_cntx_cnt_MASK 0x00002000 +#define SC_DEBUG_0_trigger_MASK 0x80000000 + +#define SC_DEBUG_0_MASK \ + (SC_DEBUG_0_pa_freeze_b1_MASK | \ + SC_DEBUG_0_pa_sc_valid_MASK | \ + SC_DEBUG_0_pa_sc_phase_MASK | \ + SC_DEBUG_0_cntx_cnt_MASK | \ + SC_DEBUG_0_decr_cntx_cnt_MASK | \ + SC_DEBUG_0_incr_cntx_cnt_MASK | \ + SC_DEBUG_0_trigger_MASK) + +#define SC_DEBUG_0(pa_freeze_b1, pa_sc_valid, pa_sc_phase, cntx_cnt, decr_cntx_cnt, incr_cntx_cnt, trigger) \ + ((pa_freeze_b1 << SC_DEBUG_0_pa_freeze_b1_SHIFT) | \ + (pa_sc_valid << SC_DEBUG_0_pa_sc_valid_SHIFT) | \ + (pa_sc_phase << SC_DEBUG_0_pa_sc_phase_SHIFT) | \ + (cntx_cnt << SC_DEBUG_0_cntx_cnt_SHIFT) | \ + (decr_cntx_cnt << SC_DEBUG_0_decr_cntx_cnt_SHIFT) | \ + (incr_cntx_cnt << SC_DEBUG_0_incr_cntx_cnt_SHIFT) | \ + (trigger << SC_DEBUG_0_trigger_SHIFT)) + +#define SC_DEBUG_0_GET_pa_freeze_b1(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_pa_freeze_b1_MASK) >> SC_DEBUG_0_pa_freeze_b1_SHIFT) +#define SC_DEBUG_0_GET_pa_sc_valid(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_pa_sc_valid_MASK) >> SC_DEBUG_0_pa_sc_valid_SHIFT) +#define SC_DEBUG_0_GET_pa_sc_phase(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_pa_sc_phase_MASK) >> SC_DEBUG_0_pa_sc_phase_SHIFT) +#define SC_DEBUG_0_GET_cntx_cnt(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_cntx_cnt_MASK) >> SC_DEBUG_0_cntx_cnt_SHIFT) +#define SC_DEBUG_0_GET_decr_cntx_cnt(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_decr_cntx_cnt_MASK) >> SC_DEBUG_0_decr_cntx_cnt_SHIFT) +#define SC_DEBUG_0_GET_incr_cntx_cnt(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_incr_cntx_cnt_MASK) >> SC_DEBUG_0_incr_cntx_cnt_SHIFT) +#define SC_DEBUG_0_GET_trigger(sc_debug_0) \ + ((sc_debug_0 & SC_DEBUG_0_trigger_MASK) >> SC_DEBUG_0_trigger_SHIFT) + +#define SC_DEBUG_0_SET_pa_freeze_b1(sc_debug_0_reg, pa_freeze_b1) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_freeze_b1_MASK) | (pa_freeze_b1 << SC_DEBUG_0_pa_freeze_b1_SHIFT) +#define SC_DEBUG_0_SET_pa_sc_valid(sc_debug_0_reg, pa_sc_valid) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_sc_valid_MASK) | (pa_sc_valid << SC_DEBUG_0_pa_sc_valid_SHIFT) +#define SC_DEBUG_0_SET_pa_sc_phase(sc_debug_0_reg, pa_sc_phase) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_pa_sc_phase_MASK) | (pa_sc_phase << SC_DEBUG_0_pa_sc_phase_SHIFT) +#define SC_DEBUG_0_SET_cntx_cnt(sc_debug_0_reg, cntx_cnt) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_cntx_cnt_MASK) | (cntx_cnt << SC_DEBUG_0_cntx_cnt_SHIFT) +#define SC_DEBUG_0_SET_decr_cntx_cnt(sc_debug_0_reg, decr_cntx_cnt) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_decr_cntx_cnt_MASK) | (decr_cntx_cnt << SC_DEBUG_0_decr_cntx_cnt_SHIFT) +#define SC_DEBUG_0_SET_incr_cntx_cnt(sc_debug_0_reg, incr_cntx_cnt) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_incr_cntx_cnt_MASK) | (incr_cntx_cnt << SC_DEBUG_0_incr_cntx_cnt_SHIFT) +#define SC_DEBUG_0_SET_trigger(sc_debug_0_reg, trigger) \ + sc_debug_0_reg = (sc_debug_0_reg & ~SC_DEBUG_0_trigger_MASK) | (trigger << SC_DEBUG_0_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_0_t { + unsigned int pa_freeze_b1 : SC_DEBUG_0_pa_freeze_b1_SIZE; + unsigned int pa_sc_valid : SC_DEBUG_0_pa_sc_valid_SIZE; + unsigned int pa_sc_phase : SC_DEBUG_0_pa_sc_phase_SIZE; + unsigned int cntx_cnt : SC_DEBUG_0_cntx_cnt_SIZE; + unsigned int decr_cntx_cnt : SC_DEBUG_0_decr_cntx_cnt_SIZE; + unsigned int incr_cntx_cnt : SC_DEBUG_0_incr_cntx_cnt_SIZE; + unsigned int : 17; + unsigned int trigger : SC_DEBUG_0_trigger_SIZE; + } sc_debug_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_0_t { + unsigned int trigger : SC_DEBUG_0_trigger_SIZE; + unsigned int : 17; + unsigned int incr_cntx_cnt : SC_DEBUG_0_incr_cntx_cnt_SIZE; + unsigned int decr_cntx_cnt : SC_DEBUG_0_decr_cntx_cnt_SIZE; + unsigned int cntx_cnt : SC_DEBUG_0_cntx_cnt_SIZE; + unsigned int pa_sc_phase : SC_DEBUG_0_pa_sc_phase_SIZE; + unsigned int pa_sc_valid : SC_DEBUG_0_pa_sc_valid_SIZE; + unsigned int pa_freeze_b1 : SC_DEBUG_0_pa_freeze_b1_SIZE; + } sc_debug_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_0_t f; +} sc_debug_0_u; + + +/* + * SC_DEBUG_1 struct + */ + +#define SC_DEBUG_1_em_state_SIZE 3 +#define SC_DEBUG_1_em1_data_ready_SIZE 1 +#define SC_DEBUG_1_em2_data_ready_SIZE 1 +#define SC_DEBUG_1_move_em1_to_em2_SIZE 1 +#define SC_DEBUG_1_ef_data_ready_SIZE 1 +#define SC_DEBUG_1_ef_state_SIZE 2 +#define SC_DEBUG_1_pipe_valid_SIZE 1 +#define SC_DEBUG_1_trigger_SIZE 1 + +#define SC_DEBUG_1_em_state_SHIFT 0 +#define SC_DEBUG_1_em1_data_ready_SHIFT 3 +#define SC_DEBUG_1_em2_data_ready_SHIFT 4 +#define SC_DEBUG_1_move_em1_to_em2_SHIFT 5 +#define SC_DEBUG_1_ef_data_ready_SHIFT 6 +#define SC_DEBUG_1_ef_state_SHIFT 7 +#define SC_DEBUG_1_pipe_valid_SHIFT 9 +#define SC_DEBUG_1_trigger_SHIFT 31 + +#define SC_DEBUG_1_em_state_MASK 0x00000007 +#define SC_DEBUG_1_em1_data_ready_MASK 0x00000008 +#define SC_DEBUG_1_em2_data_ready_MASK 0x00000010 +#define SC_DEBUG_1_move_em1_to_em2_MASK 0x00000020 +#define SC_DEBUG_1_ef_data_ready_MASK 0x00000040 +#define SC_DEBUG_1_ef_state_MASK 0x00000180 +#define SC_DEBUG_1_pipe_valid_MASK 0x00000200 +#define SC_DEBUG_1_trigger_MASK 0x80000000 + +#define SC_DEBUG_1_MASK \ + (SC_DEBUG_1_em_state_MASK | \ + SC_DEBUG_1_em1_data_ready_MASK | \ + SC_DEBUG_1_em2_data_ready_MASK | \ + SC_DEBUG_1_move_em1_to_em2_MASK | \ + SC_DEBUG_1_ef_data_ready_MASK | \ + SC_DEBUG_1_ef_state_MASK | \ + SC_DEBUG_1_pipe_valid_MASK | \ + SC_DEBUG_1_trigger_MASK) + +#define SC_DEBUG_1(em_state, em1_data_ready, em2_data_ready, move_em1_to_em2, ef_data_ready, ef_state, pipe_valid, trigger) \ + ((em_state << SC_DEBUG_1_em_state_SHIFT) | \ + (em1_data_ready << SC_DEBUG_1_em1_data_ready_SHIFT) | \ + (em2_data_ready << SC_DEBUG_1_em2_data_ready_SHIFT) | \ + (move_em1_to_em2 << SC_DEBUG_1_move_em1_to_em2_SHIFT) | \ + (ef_data_ready << SC_DEBUG_1_ef_data_ready_SHIFT) | \ + (ef_state << SC_DEBUG_1_ef_state_SHIFT) | \ + (pipe_valid << SC_DEBUG_1_pipe_valid_SHIFT) | \ + (trigger << SC_DEBUG_1_trigger_SHIFT)) + +#define SC_DEBUG_1_GET_em_state(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_em_state_MASK) >> SC_DEBUG_1_em_state_SHIFT) +#define SC_DEBUG_1_GET_em1_data_ready(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_em1_data_ready_MASK) >> SC_DEBUG_1_em1_data_ready_SHIFT) +#define SC_DEBUG_1_GET_em2_data_ready(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_em2_data_ready_MASK) >> SC_DEBUG_1_em2_data_ready_SHIFT) +#define SC_DEBUG_1_GET_move_em1_to_em2(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_move_em1_to_em2_MASK) >> SC_DEBUG_1_move_em1_to_em2_SHIFT) +#define SC_DEBUG_1_GET_ef_data_ready(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_ef_data_ready_MASK) >> SC_DEBUG_1_ef_data_ready_SHIFT) +#define SC_DEBUG_1_GET_ef_state(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_ef_state_MASK) >> SC_DEBUG_1_ef_state_SHIFT) +#define SC_DEBUG_1_GET_pipe_valid(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_pipe_valid_MASK) >> SC_DEBUG_1_pipe_valid_SHIFT) +#define SC_DEBUG_1_GET_trigger(sc_debug_1) \ + ((sc_debug_1 & SC_DEBUG_1_trigger_MASK) >> SC_DEBUG_1_trigger_SHIFT) + +#define SC_DEBUG_1_SET_em_state(sc_debug_1_reg, em_state) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em_state_MASK) | (em_state << SC_DEBUG_1_em_state_SHIFT) +#define SC_DEBUG_1_SET_em1_data_ready(sc_debug_1_reg, em1_data_ready) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em1_data_ready_MASK) | (em1_data_ready << SC_DEBUG_1_em1_data_ready_SHIFT) +#define SC_DEBUG_1_SET_em2_data_ready(sc_debug_1_reg, em2_data_ready) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_em2_data_ready_MASK) | (em2_data_ready << SC_DEBUG_1_em2_data_ready_SHIFT) +#define SC_DEBUG_1_SET_move_em1_to_em2(sc_debug_1_reg, move_em1_to_em2) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_move_em1_to_em2_MASK) | (move_em1_to_em2 << SC_DEBUG_1_move_em1_to_em2_SHIFT) +#define SC_DEBUG_1_SET_ef_data_ready(sc_debug_1_reg, ef_data_ready) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_ef_data_ready_MASK) | (ef_data_ready << SC_DEBUG_1_ef_data_ready_SHIFT) +#define SC_DEBUG_1_SET_ef_state(sc_debug_1_reg, ef_state) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_ef_state_MASK) | (ef_state << SC_DEBUG_1_ef_state_SHIFT) +#define SC_DEBUG_1_SET_pipe_valid(sc_debug_1_reg, pipe_valid) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_pipe_valid_MASK) | (pipe_valid << SC_DEBUG_1_pipe_valid_SHIFT) +#define SC_DEBUG_1_SET_trigger(sc_debug_1_reg, trigger) \ + sc_debug_1_reg = (sc_debug_1_reg & ~SC_DEBUG_1_trigger_MASK) | (trigger << SC_DEBUG_1_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_1_t { + unsigned int em_state : SC_DEBUG_1_em_state_SIZE; + unsigned int em1_data_ready : SC_DEBUG_1_em1_data_ready_SIZE; + unsigned int em2_data_ready : SC_DEBUG_1_em2_data_ready_SIZE; + unsigned int move_em1_to_em2 : SC_DEBUG_1_move_em1_to_em2_SIZE; + unsigned int ef_data_ready : SC_DEBUG_1_ef_data_ready_SIZE; + unsigned int ef_state : SC_DEBUG_1_ef_state_SIZE; + unsigned int pipe_valid : SC_DEBUG_1_pipe_valid_SIZE; + unsigned int : 21; + unsigned int trigger : SC_DEBUG_1_trigger_SIZE; + } sc_debug_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_1_t { + unsigned int trigger : SC_DEBUG_1_trigger_SIZE; + unsigned int : 21; + unsigned int pipe_valid : SC_DEBUG_1_pipe_valid_SIZE; + unsigned int ef_state : SC_DEBUG_1_ef_state_SIZE; + unsigned int ef_data_ready : SC_DEBUG_1_ef_data_ready_SIZE; + unsigned int move_em1_to_em2 : SC_DEBUG_1_move_em1_to_em2_SIZE; + unsigned int em2_data_ready : SC_DEBUG_1_em2_data_ready_SIZE; + unsigned int em1_data_ready : SC_DEBUG_1_em1_data_ready_SIZE; + unsigned int em_state : SC_DEBUG_1_em_state_SIZE; + } sc_debug_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_1_t f; +} sc_debug_1_u; + + +/* + * SC_DEBUG_2 struct + */ + +#define SC_DEBUG_2_rc_rtr_dly_SIZE 1 +#define SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE 1 +#define SC_DEBUG_2_pipe_freeze_b_SIZE 1 +#define SC_DEBUG_2_prim_rts_SIZE 1 +#define SC_DEBUG_2_next_prim_rts_dly_SIZE 1 +#define SC_DEBUG_2_next_prim_rtr_dly_SIZE 1 +#define SC_DEBUG_2_pre_stage1_rts_d1_SIZE 1 +#define SC_DEBUG_2_stage0_rts_SIZE 1 +#define SC_DEBUG_2_phase_rts_dly_SIZE 1 +#define SC_DEBUG_2_end_of_prim_s1_dly_SIZE 1 +#define SC_DEBUG_2_pass_empty_prim_s1_SIZE 1 +#define SC_DEBUG_2_event_id_s1_SIZE 5 +#define SC_DEBUG_2_event_s1_SIZE 1 +#define SC_DEBUG_2_trigger_SIZE 1 + +#define SC_DEBUG_2_rc_rtr_dly_SHIFT 0 +#define SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT 1 +#define SC_DEBUG_2_pipe_freeze_b_SHIFT 3 +#define SC_DEBUG_2_prim_rts_SHIFT 4 +#define SC_DEBUG_2_next_prim_rts_dly_SHIFT 5 +#define SC_DEBUG_2_next_prim_rtr_dly_SHIFT 6 +#define SC_DEBUG_2_pre_stage1_rts_d1_SHIFT 7 +#define SC_DEBUG_2_stage0_rts_SHIFT 8 +#define SC_DEBUG_2_phase_rts_dly_SHIFT 9 +#define SC_DEBUG_2_end_of_prim_s1_dly_SHIFT 15 +#define SC_DEBUG_2_pass_empty_prim_s1_SHIFT 16 +#define SC_DEBUG_2_event_id_s1_SHIFT 17 +#define SC_DEBUG_2_event_s1_SHIFT 22 +#define SC_DEBUG_2_trigger_SHIFT 31 + +#define SC_DEBUG_2_rc_rtr_dly_MASK 0x00000001 +#define SC_DEBUG_2_qmask_ff_alm_full_d1_MASK 0x00000002 +#define SC_DEBUG_2_pipe_freeze_b_MASK 0x00000008 +#define SC_DEBUG_2_prim_rts_MASK 0x00000010 +#define SC_DEBUG_2_next_prim_rts_dly_MASK 0x00000020 +#define SC_DEBUG_2_next_prim_rtr_dly_MASK 0x00000040 +#define SC_DEBUG_2_pre_stage1_rts_d1_MASK 0x00000080 +#define SC_DEBUG_2_stage0_rts_MASK 0x00000100 +#define SC_DEBUG_2_phase_rts_dly_MASK 0x00000200 +#define SC_DEBUG_2_end_of_prim_s1_dly_MASK 0x00008000 +#define SC_DEBUG_2_pass_empty_prim_s1_MASK 0x00010000 +#define SC_DEBUG_2_event_id_s1_MASK 0x003e0000 +#define SC_DEBUG_2_event_s1_MASK 0x00400000 +#define SC_DEBUG_2_trigger_MASK 0x80000000 + +#define SC_DEBUG_2_MASK \ + (SC_DEBUG_2_rc_rtr_dly_MASK | \ + SC_DEBUG_2_qmask_ff_alm_full_d1_MASK | \ + SC_DEBUG_2_pipe_freeze_b_MASK | \ + SC_DEBUG_2_prim_rts_MASK | \ + SC_DEBUG_2_next_prim_rts_dly_MASK | \ + SC_DEBUG_2_next_prim_rtr_dly_MASK | \ + SC_DEBUG_2_pre_stage1_rts_d1_MASK | \ + SC_DEBUG_2_stage0_rts_MASK | \ + SC_DEBUG_2_phase_rts_dly_MASK | \ + SC_DEBUG_2_end_of_prim_s1_dly_MASK | \ + SC_DEBUG_2_pass_empty_prim_s1_MASK | \ + SC_DEBUG_2_event_id_s1_MASK | \ + SC_DEBUG_2_event_s1_MASK | \ + SC_DEBUG_2_trigger_MASK) + +#define SC_DEBUG_2(rc_rtr_dly, qmask_ff_alm_full_d1, pipe_freeze_b, prim_rts, next_prim_rts_dly, next_prim_rtr_dly, pre_stage1_rts_d1, stage0_rts, phase_rts_dly, end_of_prim_s1_dly, pass_empty_prim_s1, event_id_s1, event_s1, trigger) \ + ((rc_rtr_dly << SC_DEBUG_2_rc_rtr_dly_SHIFT) | \ + (qmask_ff_alm_full_d1 << SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT) | \ + (pipe_freeze_b << SC_DEBUG_2_pipe_freeze_b_SHIFT) | \ + (prim_rts << SC_DEBUG_2_prim_rts_SHIFT) | \ + (next_prim_rts_dly << SC_DEBUG_2_next_prim_rts_dly_SHIFT) | \ + (next_prim_rtr_dly << SC_DEBUG_2_next_prim_rtr_dly_SHIFT) | \ + (pre_stage1_rts_d1 << SC_DEBUG_2_pre_stage1_rts_d1_SHIFT) | \ + (stage0_rts << SC_DEBUG_2_stage0_rts_SHIFT) | \ + (phase_rts_dly << SC_DEBUG_2_phase_rts_dly_SHIFT) | \ + (end_of_prim_s1_dly << SC_DEBUG_2_end_of_prim_s1_dly_SHIFT) | \ + (pass_empty_prim_s1 << SC_DEBUG_2_pass_empty_prim_s1_SHIFT) | \ + (event_id_s1 << SC_DEBUG_2_event_id_s1_SHIFT) | \ + (event_s1 << SC_DEBUG_2_event_s1_SHIFT) | \ + (trigger << SC_DEBUG_2_trigger_SHIFT)) + +#define SC_DEBUG_2_GET_rc_rtr_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_rc_rtr_dly_MASK) >> SC_DEBUG_2_rc_rtr_dly_SHIFT) +#define SC_DEBUG_2_GET_qmask_ff_alm_full_d1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_qmask_ff_alm_full_d1_MASK) >> SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT) +#define SC_DEBUG_2_GET_pipe_freeze_b(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_pipe_freeze_b_MASK) >> SC_DEBUG_2_pipe_freeze_b_SHIFT) +#define SC_DEBUG_2_GET_prim_rts(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_prim_rts_MASK) >> SC_DEBUG_2_prim_rts_SHIFT) +#define SC_DEBUG_2_GET_next_prim_rts_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_next_prim_rts_dly_MASK) >> SC_DEBUG_2_next_prim_rts_dly_SHIFT) +#define SC_DEBUG_2_GET_next_prim_rtr_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_next_prim_rtr_dly_MASK) >> SC_DEBUG_2_next_prim_rtr_dly_SHIFT) +#define SC_DEBUG_2_GET_pre_stage1_rts_d1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_pre_stage1_rts_d1_MASK) >> SC_DEBUG_2_pre_stage1_rts_d1_SHIFT) +#define SC_DEBUG_2_GET_stage0_rts(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_stage0_rts_MASK) >> SC_DEBUG_2_stage0_rts_SHIFT) +#define SC_DEBUG_2_GET_phase_rts_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_phase_rts_dly_MASK) >> SC_DEBUG_2_phase_rts_dly_SHIFT) +#define SC_DEBUG_2_GET_end_of_prim_s1_dly(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_end_of_prim_s1_dly_MASK) >> SC_DEBUG_2_end_of_prim_s1_dly_SHIFT) +#define SC_DEBUG_2_GET_pass_empty_prim_s1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_pass_empty_prim_s1_MASK) >> SC_DEBUG_2_pass_empty_prim_s1_SHIFT) +#define SC_DEBUG_2_GET_event_id_s1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_event_id_s1_MASK) >> SC_DEBUG_2_event_id_s1_SHIFT) +#define SC_DEBUG_2_GET_event_s1(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_event_s1_MASK) >> SC_DEBUG_2_event_s1_SHIFT) +#define SC_DEBUG_2_GET_trigger(sc_debug_2) \ + ((sc_debug_2 & SC_DEBUG_2_trigger_MASK) >> SC_DEBUG_2_trigger_SHIFT) + +#define SC_DEBUG_2_SET_rc_rtr_dly(sc_debug_2_reg, rc_rtr_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_rc_rtr_dly_MASK) | (rc_rtr_dly << SC_DEBUG_2_rc_rtr_dly_SHIFT) +#define SC_DEBUG_2_SET_qmask_ff_alm_full_d1(sc_debug_2_reg, qmask_ff_alm_full_d1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_qmask_ff_alm_full_d1_MASK) | (qmask_ff_alm_full_d1 << SC_DEBUG_2_qmask_ff_alm_full_d1_SHIFT) +#define SC_DEBUG_2_SET_pipe_freeze_b(sc_debug_2_reg, pipe_freeze_b) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pipe_freeze_b_MASK) | (pipe_freeze_b << SC_DEBUG_2_pipe_freeze_b_SHIFT) +#define SC_DEBUG_2_SET_prim_rts(sc_debug_2_reg, prim_rts) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_prim_rts_MASK) | (prim_rts << SC_DEBUG_2_prim_rts_SHIFT) +#define SC_DEBUG_2_SET_next_prim_rts_dly(sc_debug_2_reg, next_prim_rts_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_next_prim_rts_dly_MASK) | (next_prim_rts_dly << SC_DEBUG_2_next_prim_rts_dly_SHIFT) +#define SC_DEBUG_2_SET_next_prim_rtr_dly(sc_debug_2_reg, next_prim_rtr_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_next_prim_rtr_dly_MASK) | (next_prim_rtr_dly << SC_DEBUG_2_next_prim_rtr_dly_SHIFT) +#define SC_DEBUG_2_SET_pre_stage1_rts_d1(sc_debug_2_reg, pre_stage1_rts_d1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pre_stage1_rts_d1_MASK) | (pre_stage1_rts_d1 << SC_DEBUG_2_pre_stage1_rts_d1_SHIFT) +#define SC_DEBUG_2_SET_stage0_rts(sc_debug_2_reg, stage0_rts) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_stage0_rts_MASK) | (stage0_rts << SC_DEBUG_2_stage0_rts_SHIFT) +#define SC_DEBUG_2_SET_phase_rts_dly(sc_debug_2_reg, phase_rts_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_phase_rts_dly_MASK) | (phase_rts_dly << SC_DEBUG_2_phase_rts_dly_SHIFT) +#define SC_DEBUG_2_SET_end_of_prim_s1_dly(sc_debug_2_reg, end_of_prim_s1_dly) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_end_of_prim_s1_dly_MASK) | (end_of_prim_s1_dly << SC_DEBUG_2_end_of_prim_s1_dly_SHIFT) +#define SC_DEBUG_2_SET_pass_empty_prim_s1(sc_debug_2_reg, pass_empty_prim_s1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_pass_empty_prim_s1_MASK) | (pass_empty_prim_s1 << SC_DEBUG_2_pass_empty_prim_s1_SHIFT) +#define SC_DEBUG_2_SET_event_id_s1(sc_debug_2_reg, event_id_s1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_event_id_s1_MASK) | (event_id_s1 << SC_DEBUG_2_event_id_s1_SHIFT) +#define SC_DEBUG_2_SET_event_s1(sc_debug_2_reg, event_s1) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_event_s1_MASK) | (event_s1 << SC_DEBUG_2_event_s1_SHIFT) +#define SC_DEBUG_2_SET_trigger(sc_debug_2_reg, trigger) \ + sc_debug_2_reg = (sc_debug_2_reg & ~SC_DEBUG_2_trigger_MASK) | (trigger << SC_DEBUG_2_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_2_t { + unsigned int rc_rtr_dly : SC_DEBUG_2_rc_rtr_dly_SIZE; + unsigned int qmask_ff_alm_full_d1 : SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE; + unsigned int : 1; + unsigned int pipe_freeze_b : SC_DEBUG_2_pipe_freeze_b_SIZE; + unsigned int prim_rts : SC_DEBUG_2_prim_rts_SIZE; + unsigned int next_prim_rts_dly : SC_DEBUG_2_next_prim_rts_dly_SIZE; + unsigned int next_prim_rtr_dly : SC_DEBUG_2_next_prim_rtr_dly_SIZE; + unsigned int pre_stage1_rts_d1 : SC_DEBUG_2_pre_stage1_rts_d1_SIZE; + unsigned int stage0_rts : SC_DEBUG_2_stage0_rts_SIZE; + unsigned int phase_rts_dly : SC_DEBUG_2_phase_rts_dly_SIZE; + unsigned int : 5; + unsigned int end_of_prim_s1_dly : SC_DEBUG_2_end_of_prim_s1_dly_SIZE; + unsigned int pass_empty_prim_s1 : SC_DEBUG_2_pass_empty_prim_s1_SIZE; + unsigned int event_id_s1 : SC_DEBUG_2_event_id_s1_SIZE; + unsigned int event_s1 : SC_DEBUG_2_event_s1_SIZE; + unsigned int : 8; + unsigned int trigger : SC_DEBUG_2_trigger_SIZE; + } sc_debug_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_2_t { + unsigned int trigger : SC_DEBUG_2_trigger_SIZE; + unsigned int : 8; + unsigned int event_s1 : SC_DEBUG_2_event_s1_SIZE; + unsigned int event_id_s1 : SC_DEBUG_2_event_id_s1_SIZE; + unsigned int pass_empty_prim_s1 : SC_DEBUG_2_pass_empty_prim_s1_SIZE; + unsigned int end_of_prim_s1_dly : SC_DEBUG_2_end_of_prim_s1_dly_SIZE; + unsigned int : 5; + unsigned int phase_rts_dly : SC_DEBUG_2_phase_rts_dly_SIZE; + unsigned int stage0_rts : SC_DEBUG_2_stage0_rts_SIZE; + unsigned int pre_stage1_rts_d1 : SC_DEBUG_2_pre_stage1_rts_d1_SIZE; + unsigned int next_prim_rtr_dly : SC_DEBUG_2_next_prim_rtr_dly_SIZE; + unsigned int next_prim_rts_dly : SC_DEBUG_2_next_prim_rts_dly_SIZE; + unsigned int prim_rts : SC_DEBUG_2_prim_rts_SIZE; + unsigned int pipe_freeze_b : SC_DEBUG_2_pipe_freeze_b_SIZE; + unsigned int : 1; + unsigned int qmask_ff_alm_full_d1 : SC_DEBUG_2_qmask_ff_alm_full_d1_SIZE; + unsigned int rc_rtr_dly : SC_DEBUG_2_rc_rtr_dly_SIZE; + } sc_debug_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_2_t f; +} sc_debug_2_u; + + +/* + * SC_DEBUG_3 struct + */ + +#define SC_DEBUG_3_x_curr_s1_SIZE 11 +#define SC_DEBUG_3_y_curr_s1_SIZE 11 +#define SC_DEBUG_3_trigger_SIZE 1 + +#define SC_DEBUG_3_x_curr_s1_SHIFT 0 +#define SC_DEBUG_3_y_curr_s1_SHIFT 11 +#define SC_DEBUG_3_trigger_SHIFT 31 + +#define SC_DEBUG_3_x_curr_s1_MASK 0x000007ff +#define SC_DEBUG_3_y_curr_s1_MASK 0x003ff800 +#define SC_DEBUG_3_trigger_MASK 0x80000000 + +#define SC_DEBUG_3_MASK \ + (SC_DEBUG_3_x_curr_s1_MASK | \ + SC_DEBUG_3_y_curr_s1_MASK | \ + SC_DEBUG_3_trigger_MASK) + +#define SC_DEBUG_3(x_curr_s1, y_curr_s1, trigger) \ + ((x_curr_s1 << SC_DEBUG_3_x_curr_s1_SHIFT) | \ + (y_curr_s1 << SC_DEBUG_3_y_curr_s1_SHIFT) | \ + (trigger << SC_DEBUG_3_trigger_SHIFT)) + +#define SC_DEBUG_3_GET_x_curr_s1(sc_debug_3) \ + ((sc_debug_3 & SC_DEBUG_3_x_curr_s1_MASK) >> SC_DEBUG_3_x_curr_s1_SHIFT) +#define SC_DEBUG_3_GET_y_curr_s1(sc_debug_3) \ + ((sc_debug_3 & SC_DEBUG_3_y_curr_s1_MASK) >> SC_DEBUG_3_y_curr_s1_SHIFT) +#define SC_DEBUG_3_GET_trigger(sc_debug_3) \ + ((sc_debug_3 & SC_DEBUG_3_trigger_MASK) >> SC_DEBUG_3_trigger_SHIFT) + +#define SC_DEBUG_3_SET_x_curr_s1(sc_debug_3_reg, x_curr_s1) \ + sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_x_curr_s1_MASK) | (x_curr_s1 << SC_DEBUG_3_x_curr_s1_SHIFT) +#define SC_DEBUG_3_SET_y_curr_s1(sc_debug_3_reg, y_curr_s1) \ + sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_y_curr_s1_MASK) | (y_curr_s1 << SC_DEBUG_3_y_curr_s1_SHIFT) +#define SC_DEBUG_3_SET_trigger(sc_debug_3_reg, trigger) \ + sc_debug_3_reg = (sc_debug_3_reg & ~SC_DEBUG_3_trigger_MASK) | (trigger << SC_DEBUG_3_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_3_t { + unsigned int x_curr_s1 : SC_DEBUG_3_x_curr_s1_SIZE; + unsigned int y_curr_s1 : SC_DEBUG_3_y_curr_s1_SIZE; + unsigned int : 9; + unsigned int trigger : SC_DEBUG_3_trigger_SIZE; + } sc_debug_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_3_t { + unsigned int trigger : SC_DEBUG_3_trigger_SIZE; + unsigned int : 9; + unsigned int y_curr_s1 : SC_DEBUG_3_y_curr_s1_SIZE; + unsigned int x_curr_s1 : SC_DEBUG_3_x_curr_s1_SIZE; + } sc_debug_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_3_t f; +} sc_debug_3_u; + + +/* + * SC_DEBUG_4 struct + */ + +#define SC_DEBUG_4_y_end_s1_SIZE 14 +#define SC_DEBUG_4_y_start_s1_SIZE 14 +#define SC_DEBUG_4_y_dir_s1_SIZE 1 +#define SC_DEBUG_4_trigger_SIZE 1 + +#define SC_DEBUG_4_y_end_s1_SHIFT 0 +#define SC_DEBUG_4_y_start_s1_SHIFT 14 +#define SC_DEBUG_4_y_dir_s1_SHIFT 28 +#define SC_DEBUG_4_trigger_SHIFT 31 + +#define SC_DEBUG_4_y_end_s1_MASK 0x00003fff +#define SC_DEBUG_4_y_start_s1_MASK 0x0fffc000 +#define SC_DEBUG_4_y_dir_s1_MASK 0x10000000 +#define SC_DEBUG_4_trigger_MASK 0x80000000 + +#define SC_DEBUG_4_MASK \ + (SC_DEBUG_4_y_end_s1_MASK | \ + SC_DEBUG_4_y_start_s1_MASK | \ + SC_DEBUG_4_y_dir_s1_MASK | \ + SC_DEBUG_4_trigger_MASK) + +#define SC_DEBUG_4(y_end_s1, y_start_s1, y_dir_s1, trigger) \ + ((y_end_s1 << SC_DEBUG_4_y_end_s1_SHIFT) | \ + (y_start_s1 << SC_DEBUG_4_y_start_s1_SHIFT) | \ + (y_dir_s1 << SC_DEBUG_4_y_dir_s1_SHIFT) | \ + (trigger << SC_DEBUG_4_trigger_SHIFT)) + +#define SC_DEBUG_4_GET_y_end_s1(sc_debug_4) \ + ((sc_debug_4 & SC_DEBUG_4_y_end_s1_MASK) >> SC_DEBUG_4_y_end_s1_SHIFT) +#define SC_DEBUG_4_GET_y_start_s1(sc_debug_4) \ + ((sc_debug_4 & SC_DEBUG_4_y_start_s1_MASK) >> SC_DEBUG_4_y_start_s1_SHIFT) +#define SC_DEBUG_4_GET_y_dir_s1(sc_debug_4) \ + ((sc_debug_4 & SC_DEBUG_4_y_dir_s1_MASK) >> SC_DEBUG_4_y_dir_s1_SHIFT) +#define SC_DEBUG_4_GET_trigger(sc_debug_4) \ + ((sc_debug_4 & SC_DEBUG_4_trigger_MASK) >> SC_DEBUG_4_trigger_SHIFT) + +#define SC_DEBUG_4_SET_y_end_s1(sc_debug_4_reg, y_end_s1) \ + sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_end_s1_MASK) | (y_end_s1 << SC_DEBUG_4_y_end_s1_SHIFT) +#define SC_DEBUG_4_SET_y_start_s1(sc_debug_4_reg, y_start_s1) \ + sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_start_s1_MASK) | (y_start_s1 << SC_DEBUG_4_y_start_s1_SHIFT) +#define SC_DEBUG_4_SET_y_dir_s1(sc_debug_4_reg, y_dir_s1) \ + sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_y_dir_s1_MASK) | (y_dir_s1 << SC_DEBUG_4_y_dir_s1_SHIFT) +#define SC_DEBUG_4_SET_trigger(sc_debug_4_reg, trigger) \ + sc_debug_4_reg = (sc_debug_4_reg & ~SC_DEBUG_4_trigger_MASK) | (trigger << SC_DEBUG_4_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_4_t { + unsigned int y_end_s1 : SC_DEBUG_4_y_end_s1_SIZE; + unsigned int y_start_s1 : SC_DEBUG_4_y_start_s1_SIZE; + unsigned int y_dir_s1 : SC_DEBUG_4_y_dir_s1_SIZE; + unsigned int : 2; + unsigned int trigger : SC_DEBUG_4_trigger_SIZE; + } sc_debug_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_4_t { + unsigned int trigger : SC_DEBUG_4_trigger_SIZE; + unsigned int : 2; + unsigned int y_dir_s1 : SC_DEBUG_4_y_dir_s1_SIZE; + unsigned int y_start_s1 : SC_DEBUG_4_y_start_s1_SIZE; + unsigned int y_end_s1 : SC_DEBUG_4_y_end_s1_SIZE; + } sc_debug_4_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_4_t f; +} sc_debug_4_u; + + +/* + * SC_DEBUG_5 struct + */ + +#define SC_DEBUG_5_x_end_s1_SIZE 14 +#define SC_DEBUG_5_x_start_s1_SIZE 14 +#define SC_DEBUG_5_x_dir_s1_SIZE 1 +#define SC_DEBUG_5_trigger_SIZE 1 + +#define SC_DEBUG_5_x_end_s1_SHIFT 0 +#define SC_DEBUG_5_x_start_s1_SHIFT 14 +#define SC_DEBUG_5_x_dir_s1_SHIFT 28 +#define SC_DEBUG_5_trigger_SHIFT 31 + +#define SC_DEBUG_5_x_end_s1_MASK 0x00003fff +#define SC_DEBUG_5_x_start_s1_MASK 0x0fffc000 +#define SC_DEBUG_5_x_dir_s1_MASK 0x10000000 +#define SC_DEBUG_5_trigger_MASK 0x80000000 + +#define SC_DEBUG_5_MASK \ + (SC_DEBUG_5_x_end_s1_MASK | \ + SC_DEBUG_5_x_start_s1_MASK | \ + SC_DEBUG_5_x_dir_s1_MASK | \ + SC_DEBUG_5_trigger_MASK) + +#define SC_DEBUG_5(x_end_s1, x_start_s1, x_dir_s1, trigger) \ + ((x_end_s1 << SC_DEBUG_5_x_end_s1_SHIFT) | \ + (x_start_s1 << SC_DEBUG_5_x_start_s1_SHIFT) | \ + (x_dir_s1 << SC_DEBUG_5_x_dir_s1_SHIFT) | \ + (trigger << SC_DEBUG_5_trigger_SHIFT)) + +#define SC_DEBUG_5_GET_x_end_s1(sc_debug_5) \ + ((sc_debug_5 & SC_DEBUG_5_x_end_s1_MASK) >> SC_DEBUG_5_x_end_s1_SHIFT) +#define SC_DEBUG_5_GET_x_start_s1(sc_debug_5) \ + ((sc_debug_5 & SC_DEBUG_5_x_start_s1_MASK) >> SC_DEBUG_5_x_start_s1_SHIFT) +#define SC_DEBUG_5_GET_x_dir_s1(sc_debug_5) \ + ((sc_debug_5 & SC_DEBUG_5_x_dir_s1_MASK) >> SC_DEBUG_5_x_dir_s1_SHIFT) +#define SC_DEBUG_5_GET_trigger(sc_debug_5) \ + ((sc_debug_5 & SC_DEBUG_5_trigger_MASK) >> SC_DEBUG_5_trigger_SHIFT) + +#define SC_DEBUG_5_SET_x_end_s1(sc_debug_5_reg, x_end_s1) \ + sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_end_s1_MASK) | (x_end_s1 << SC_DEBUG_5_x_end_s1_SHIFT) +#define SC_DEBUG_5_SET_x_start_s1(sc_debug_5_reg, x_start_s1) \ + sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_start_s1_MASK) | (x_start_s1 << SC_DEBUG_5_x_start_s1_SHIFT) +#define SC_DEBUG_5_SET_x_dir_s1(sc_debug_5_reg, x_dir_s1) \ + sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_x_dir_s1_MASK) | (x_dir_s1 << SC_DEBUG_5_x_dir_s1_SHIFT) +#define SC_DEBUG_5_SET_trigger(sc_debug_5_reg, trigger) \ + sc_debug_5_reg = (sc_debug_5_reg & ~SC_DEBUG_5_trigger_MASK) | (trigger << SC_DEBUG_5_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_5_t { + unsigned int x_end_s1 : SC_DEBUG_5_x_end_s1_SIZE; + unsigned int x_start_s1 : SC_DEBUG_5_x_start_s1_SIZE; + unsigned int x_dir_s1 : SC_DEBUG_5_x_dir_s1_SIZE; + unsigned int : 2; + unsigned int trigger : SC_DEBUG_5_trigger_SIZE; + } sc_debug_5_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_5_t { + unsigned int trigger : SC_DEBUG_5_trigger_SIZE; + unsigned int : 2; + unsigned int x_dir_s1 : SC_DEBUG_5_x_dir_s1_SIZE; + unsigned int x_start_s1 : SC_DEBUG_5_x_start_s1_SIZE; + unsigned int x_end_s1 : SC_DEBUG_5_x_end_s1_SIZE; + } sc_debug_5_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_5_t f; +} sc_debug_5_u; + + +/* + * SC_DEBUG_6 struct + */ + +#define SC_DEBUG_6_z_ff_empty_SIZE 1 +#define SC_DEBUG_6_qmcntl_ff_empty_SIZE 1 +#define SC_DEBUG_6_xy_ff_empty_SIZE 1 +#define SC_DEBUG_6_event_flag_SIZE 1 +#define SC_DEBUG_6_z_mask_needed_SIZE 1 +#define SC_DEBUG_6_state_SIZE 3 +#define SC_DEBUG_6_state_delayed_SIZE 3 +#define SC_DEBUG_6_data_valid_SIZE 1 +#define SC_DEBUG_6_data_valid_d_SIZE 1 +#define SC_DEBUG_6_tilex_delayed_SIZE 9 +#define SC_DEBUG_6_tiley_delayed_SIZE 9 +#define SC_DEBUG_6_trigger_SIZE 1 + +#define SC_DEBUG_6_z_ff_empty_SHIFT 0 +#define SC_DEBUG_6_qmcntl_ff_empty_SHIFT 1 +#define SC_DEBUG_6_xy_ff_empty_SHIFT 2 +#define SC_DEBUG_6_event_flag_SHIFT 3 +#define SC_DEBUG_6_z_mask_needed_SHIFT 4 +#define SC_DEBUG_6_state_SHIFT 5 +#define SC_DEBUG_6_state_delayed_SHIFT 8 +#define SC_DEBUG_6_data_valid_SHIFT 11 +#define SC_DEBUG_6_data_valid_d_SHIFT 12 +#define SC_DEBUG_6_tilex_delayed_SHIFT 13 +#define SC_DEBUG_6_tiley_delayed_SHIFT 22 +#define SC_DEBUG_6_trigger_SHIFT 31 + +#define SC_DEBUG_6_z_ff_empty_MASK 0x00000001 +#define SC_DEBUG_6_qmcntl_ff_empty_MASK 0x00000002 +#define SC_DEBUG_6_xy_ff_empty_MASK 0x00000004 +#define SC_DEBUG_6_event_flag_MASK 0x00000008 +#define SC_DEBUG_6_z_mask_needed_MASK 0x00000010 +#define SC_DEBUG_6_state_MASK 0x000000e0 +#define SC_DEBUG_6_state_delayed_MASK 0x00000700 +#define SC_DEBUG_6_data_valid_MASK 0x00000800 +#define SC_DEBUG_6_data_valid_d_MASK 0x00001000 +#define SC_DEBUG_6_tilex_delayed_MASK 0x003fe000 +#define SC_DEBUG_6_tiley_delayed_MASK 0x7fc00000 +#define SC_DEBUG_6_trigger_MASK 0x80000000 + +#define SC_DEBUG_6_MASK \ + (SC_DEBUG_6_z_ff_empty_MASK | \ + SC_DEBUG_6_qmcntl_ff_empty_MASK | \ + SC_DEBUG_6_xy_ff_empty_MASK | \ + SC_DEBUG_6_event_flag_MASK | \ + SC_DEBUG_6_z_mask_needed_MASK | \ + SC_DEBUG_6_state_MASK | \ + SC_DEBUG_6_state_delayed_MASK | \ + SC_DEBUG_6_data_valid_MASK | \ + SC_DEBUG_6_data_valid_d_MASK | \ + SC_DEBUG_6_tilex_delayed_MASK | \ + SC_DEBUG_6_tiley_delayed_MASK | \ + SC_DEBUG_6_trigger_MASK) + +#define SC_DEBUG_6(z_ff_empty, qmcntl_ff_empty, xy_ff_empty, event_flag, z_mask_needed, state, state_delayed, data_valid, data_valid_d, tilex_delayed, tiley_delayed, trigger) \ + ((z_ff_empty << SC_DEBUG_6_z_ff_empty_SHIFT) | \ + (qmcntl_ff_empty << SC_DEBUG_6_qmcntl_ff_empty_SHIFT) | \ + (xy_ff_empty << SC_DEBUG_6_xy_ff_empty_SHIFT) | \ + (event_flag << SC_DEBUG_6_event_flag_SHIFT) | \ + (z_mask_needed << SC_DEBUG_6_z_mask_needed_SHIFT) | \ + (state << SC_DEBUG_6_state_SHIFT) | \ + (state_delayed << SC_DEBUG_6_state_delayed_SHIFT) | \ + (data_valid << SC_DEBUG_6_data_valid_SHIFT) | \ + (data_valid_d << SC_DEBUG_6_data_valid_d_SHIFT) | \ + (tilex_delayed << SC_DEBUG_6_tilex_delayed_SHIFT) | \ + (tiley_delayed << SC_DEBUG_6_tiley_delayed_SHIFT) | \ + (trigger << SC_DEBUG_6_trigger_SHIFT)) + +#define SC_DEBUG_6_GET_z_ff_empty(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_z_ff_empty_MASK) >> SC_DEBUG_6_z_ff_empty_SHIFT) +#define SC_DEBUG_6_GET_qmcntl_ff_empty(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_qmcntl_ff_empty_MASK) >> SC_DEBUG_6_qmcntl_ff_empty_SHIFT) +#define SC_DEBUG_6_GET_xy_ff_empty(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_xy_ff_empty_MASK) >> SC_DEBUG_6_xy_ff_empty_SHIFT) +#define SC_DEBUG_6_GET_event_flag(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_event_flag_MASK) >> SC_DEBUG_6_event_flag_SHIFT) +#define SC_DEBUG_6_GET_z_mask_needed(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_z_mask_needed_MASK) >> SC_DEBUG_6_z_mask_needed_SHIFT) +#define SC_DEBUG_6_GET_state(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_state_MASK) >> SC_DEBUG_6_state_SHIFT) +#define SC_DEBUG_6_GET_state_delayed(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_state_delayed_MASK) >> SC_DEBUG_6_state_delayed_SHIFT) +#define SC_DEBUG_6_GET_data_valid(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_data_valid_MASK) >> SC_DEBUG_6_data_valid_SHIFT) +#define SC_DEBUG_6_GET_data_valid_d(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_data_valid_d_MASK) >> SC_DEBUG_6_data_valid_d_SHIFT) +#define SC_DEBUG_6_GET_tilex_delayed(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_tilex_delayed_MASK) >> SC_DEBUG_6_tilex_delayed_SHIFT) +#define SC_DEBUG_6_GET_tiley_delayed(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_tiley_delayed_MASK) >> SC_DEBUG_6_tiley_delayed_SHIFT) +#define SC_DEBUG_6_GET_trigger(sc_debug_6) \ + ((sc_debug_6 & SC_DEBUG_6_trigger_MASK) >> SC_DEBUG_6_trigger_SHIFT) + +#define SC_DEBUG_6_SET_z_ff_empty(sc_debug_6_reg, z_ff_empty) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_z_ff_empty_MASK) | (z_ff_empty << SC_DEBUG_6_z_ff_empty_SHIFT) +#define SC_DEBUG_6_SET_qmcntl_ff_empty(sc_debug_6_reg, qmcntl_ff_empty) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_qmcntl_ff_empty_MASK) | (qmcntl_ff_empty << SC_DEBUG_6_qmcntl_ff_empty_SHIFT) +#define SC_DEBUG_6_SET_xy_ff_empty(sc_debug_6_reg, xy_ff_empty) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_xy_ff_empty_MASK) | (xy_ff_empty << SC_DEBUG_6_xy_ff_empty_SHIFT) +#define SC_DEBUG_6_SET_event_flag(sc_debug_6_reg, event_flag) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_event_flag_MASK) | (event_flag << SC_DEBUG_6_event_flag_SHIFT) +#define SC_DEBUG_6_SET_z_mask_needed(sc_debug_6_reg, z_mask_needed) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_z_mask_needed_MASK) | (z_mask_needed << SC_DEBUG_6_z_mask_needed_SHIFT) +#define SC_DEBUG_6_SET_state(sc_debug_6_reg, state) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_state_MASK) | (state << SC_DEBUG_6_state_SHIFT) +#define SC_DEBUG_6_SET_state_delayed(sc_debug_6_reg, state_delayed) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_state_delayed_MASK) | (state_delayed << SC_DEBUG_6_state_delayed_SHIFT) +#define SC_DEBUG_6_SET_data_valid(sc_debug_6_reg, data_valid) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_data_valid_MASK) | (data_valid << SC_DEBUG_6_data_valid_SHIFT) +#define SC_DEBUG_6_SET_data_valid_d(sc_debug_6_reg, data_valid_d) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_data_valid_d_MASK) | (data_valid_d << SC_DEBUG_6_data_valid_d_SHIFT) +#define SC_DEBUG_6_SET_tilex_delayed(sc_debug_6_reg, tilex_delayed) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_tilex_delayed_MASK) | (tilex_delayed << SC_DEBUG_6_tilex_delayed_SHIFT) +#define SC_DEBUG_6_SET_tiley_delayed(sc_debug_6_reg, tiley_delayed) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_tiley_delayed_MASK) | (tiley_delayed << SC_DEBUG_6_tiley_delayed_SHIFT) +#define SC_DEBUG_6_SET_trigger(sc_debug_6_reg, trigger) \ + sc_debug_6_reg = (sc_debug_6_reg & ~SC_DEBUG_6_trigger_MASK) | (trigger << SC_DEBUG_6_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_6_t { + unsigned int z_ff_empty : SC_DEBUG_6_z_ff_empty_SIZE; + unsigned int qmcntl_ff_empty : SC_DEBUG_6_qmcntl_ff_empty_SIZE; + unsigned int xy_ff_empty : SC_DEBUG_6_xy_ff_empty_SIZE; + unsigned int event_flag : SC_DEBUG_6_event_flag_SIZE; + unsigned int z_mask_needed : SC_DEBUG_6_z_mask_needed_SIZE; + unsigned int state : SC_DEBUG_6_state_SIZE; + unsigned int state_delayed : SC_DEBUG_6_state_delayed_SIZE; + unsigned int data_valid : SC_DEBUG_6_data_valid_SIZE; + unsigned int data_valid_d : SC_DEBUG_6_data_valid_d_SIZE; + unsigned int tilex_delayed : SC_DEBUG_6_tilex_delayed_SIZE; + unsigned int tiley_delayed : SC_DEBUG_6_tiley_delayed_SIZE; + unsigned int trigger : SC_DEBUG_6_trigger_SIZE; + } sc_debug_6_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_6_t { + unsigned int trigger : SC_DEBUG_6_trigger_SIZE; + unsigned int tiley_delayed : SC_DEBUG_6_tiley_delayed_SIZE; + unsigned int tilex_delayed : SC_DEBUG_6_tilex_delayed_SIZE; + unsigned int data_valid_d : SC_DEBUG_6_data_valid_d_SIZE; + unsigned int data_valid : SC_DEBUG_6_data_valid_SIZE; + unsigned int state_delayed : SC_DEBUG_6_state_delayed_SIZE; + unsigned int state : SC_DEBUG_6_state_SIZE; + unsigned int z_mask_needed : SC_DEBUG_6_z_mask_needed_SIZE; + unsigned int event_flag : SC_DEBUG_6_event_flag_SIZE; + unsigned int xy_ff_empty : SC_DEBUG_6_xy_ff_empty_SIZE; + unsigned int qmcntl_ff_empty : SC_DEBUG_6_qmcntl_ff_empty_SIZE; + unsigned int z_ff_empty : SC_DEBUG_6_z_ff_empty_SIZE; + } sc_debug_6_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_6_t f; +} sc_debug_6_u; + + +/* + * SC_DEBUG_7 struct + */ + +#define SC_DEBUG_7_event_flag_SIZE 1 +#define SC_DEBUG_7_deallocate_SIZE 3 +#define SC_DEBUG_7_fposition_SIZE 1 +#define SC_DEBUG_7_sr_prim_we_SIZE 1 +#define SC_DEBUG_7_last_tile_SIZE 1 +#define SC_DEBUG_7_tile_ff_we_SIZE 1 +#define SC_DEBUG_7_qs_data_valid_SIZE 1 +#define SC_DEBUG_7_qs_q0_y_SIZE 2 +#define SC_DEBUG_7_qs_q0_x_SIZE 2 +#define SC_DEBUG_7_qs_q0_valid_SIZE 1 +#define SC_DEBUG_7_prim_ff_we_SIZE 1 +#define SC_DEBUG_7_tile_ff_re_SIZE 1 +#define SC_DEBUG_7_fw_prim_data_valid_SIZE 1 +#define SC_DEBUG_7_last_quad_of_tile_SIZE 1 +#define SC_DEBUG_7_first_quad_of_tile_SIZE 1 +#define SC_DEBUG_7_first_quad_of_prim_SIZE 1 +#define SC_DEBUG_7_new_prim_SIZE 1 +#define SC_DEBUG_7_load_new_tile_data_SIZE 1 +#define SC_DEBUG_7_state_SIZE 2 +#define SC_DEBUG_7_fifos_ready_SIZE 1 +#define SC_DEBUG_7_trigger_SIZE 1 + +#define SC_DEBUG_7_event_flag_SHIFT 0 +#define SC_DEBUG_7_deallocate_SHIFT 1 +#define SC_DEBUG_7_fposition_SHIFT 4 +#define SC_DEBUG_7_sr_prim_we_SHIFT 5 +#define SC_DEBUG_7_last_tile_SHIFT 6 +#define SC_DEBUG_7_tile_ff_we_SHIFT 7 +#define SC_DEBUG_7_qs_data_valid_SHIFT 8 +#define SC_DEBUG_7_qs_q0_y_SHIFT 9 +#define SC_DEBUG_7_qs_q0_x_SHIFT 11 +#define SC_DEBUG_7_qs_q0_valid_SHIFT 13 +#define SC_DEBUG_7_prim_ff_we_SHIFT 14 +#define SC_DEBUG_7_tile_ff_re_SHIFT 15 +#define SC_DEBUG_7_fw_prim_data_valid_SHIFT 16 +#define SC_DEBUG_7_last_quad_of_tile_SHIFT 17 +#define SC_DEBUG_7_first_quad_of_tile_SHIFT 18 +#define SC_DEBUG_7_first_quad_of_prim_SHIFT 19 +#define SC_DEBUG_7_new_prim_SHIFT 20 +#define SC_DEBUG_7_load_new_tile_data_SHIFT 21 +#define SC_DEBUG_7_state_SHIFT 22 +#define SC_DEBUG_7_fifos_ready_SHIFT 24 +#define SC_DEBUG_7_trigger_SHIFT 31 + +#define SC_DEBUG_7_event_flag_MASK 0x00000001 +#define SC_DEBUG_7_deallocate_MASK 0x0000000e +#define SC_DEBUG_7_fposition_MASK 0x00000010 +#define SC_DEBUG_7_sr_prim_we_MASK 0x00000020 +#define SC_DEBUG_7_last_tile_MASK 0x00000040 +#define SC_DEBUG_7_tile_ff_we_MASK 0x00000080 +#define SC_DEBUG_7_qs_data_valid_MASK 0x00000100 +#define SC_DEBUG_7_qs_q0_y_MASK 0x00000600 +#define SC_DEBUG_7_qs_q0_x_MASK 0x00001800 +#define SC_DEBUG_7_qs_q0_valid_MASK 0x00002000 +#define SC_DEBUG_7_prim_ff_we_MASK 0x00004000 +#define SC_DEBUG_7_tile_ff_re_MASK 0x00008000 +#define SC_DEBUG_7_fw_prim_data_valid_MASK 0x00010000 +#define SC_DEBUG_7_last_quad_of_tile_MASK 0x00020000 +#define SC_DEBUG_7_first_quad_of_tile_MASK 0x00040000 +#define SC_DEBUG_7_first_quad_of_prim_MASK 0x00080000 +#define SC_DEBUG_7_new_prim_MASK 0x00100000 +#define SC_DEBUG_7_load_new_tile_data_MASK 0x00200000 +#define SC_DEBUG_7_state_MASK 0x00c00000 +#define SC_DEBUG_7_fifos_ready_MASK 0x01000000 +#define SC_DEBUG_7_trigger_MASK 0x80000000 + +#define SC_DEBUG_7_MASK \ + (SC_DEBUG_7_event_flag_MASK | \ + SC_DEBUG_7_deallocate_MASK | \ + SC_DEBUG_7_fposition_MASK | \ + SC_DEBUG_7_sr_prim_we_MASK | \ + SC_DEBUG_7_last_tile_MASK | \ + SC_DEBUG_7_tile_ff_we_MASK | \ + SC_DEBUG_7_qs_data_valid_MASK | \ + SC_DEBUG_7_qs_q0_y_MASK | \ + SC_DEBUG_7_qs_q0_x_MASK | \ + SC_DEBUG_7_qs_q0_valid_MASK | \ + SC_DEBUG_7_prim_ff_we_MASK | \ + SC_DEBUG_7_tile_ff_re_MASK | \ + SC_DEBUG_7_fw_prim_data_valid_MASK | \ + SC_DEBUG_7_last_quad_of_tile_MASK | \ + SC_DEBUG_7_first_quad_of_tile_MASK | \ + SC_DEBUG_7_first_quad_of_prim_MASK | \ + SC_DEBUG_7_new_prim_MASK | \ + SC_DEBUG_7_load_new_tile_data_MASK | \ + SC_DEBUG_7_state_MASK | \ + SC_DEBUG_7_fifos_ready_MASK | \ + SC_DEBUG_7_trigger_MASK) + +#define SC_DEBUG_7(event_flag, deallocate, fposition, sr_prim_we, last_tile, tile_ff_we, qs_data_valid, qs_q0_y, qs_q0_x, qs_q0_valid, prim_ff_we, tile_ff_re, fw_prim_data_valid, last_quad_of_tile, first_quad_of_tile, first_quad_of_prim, new_prim, load_new_tile_data, state, fifos_ready, trigger) \ + ((event_flag << SC_DEBUG_7_event_flag_SHIFT) | \ + (deallocate << SC_DEBUG_7_deallocate_SHIFT) | \ + (fposition << SC_DEBUG_7_fposition_SHIFT) | \ + (sr_prim_we << SC_DEBUG_7_sr_prim_we_SHIFT) | \ + (last_tile << SC_DEBUG_7_last_tile_SHIFT) | \ + (tile_ff_we << SC_DEBUG_7_tile_ff_we_SHIFT) | \ + (qs_data_valid << SC_DEBUG_7_qs_data_valid_SHIFT) | \ + (qs_q0_y << SC_DEBUG_7_qs_q0_y_SHIFT) | \ + (qs_q0_x << SC_DEBUG_7_qs_q0_x_SHIFT) | \ + (qs_q0_valid << SC_DEBUG_7_qs_q0_valid_SHIFT) | \ + (prim_ff_we << SC_DEBUG_7_prim_ff_we_SHIFT) | \ + (tile_ff_re << SC_DEBUG_7_tile_ff_re_SHIFT) | \ + (fw_prim_data_valid << SC_DEBUG_7_fw_prim_data_valid_SHIFT) | \ + (last_quad_of_tile << SC_DEBUG_7_last_quad_of_tile_SHIFT) | \ + (first_quad_of_tile << SC_DEBUG_7_first_quad_of_tile_SHIFT) | \ + (first_quad_of_prim << SC_DEBUG_7_first_quad_of_prim_SHIFT) | \ + (new_prim << SC_DEBUG_7_new_prim_SHIFT) | \ + (load_new_tile_data << SC_DEBUG_7_load_new_tile_data_SHIFT) | \ + (state << SC_DEBUG_7_state_SHIFT) | \ + (fifos_ready << SC_DEBUG_7_fifos_ready_SHIFT) | \ + (trigger << SC_DEBUG_7_trigger_SHIFT)) + +#define SC_DEBUG_7_GET_event_flag(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_event_flag_MASK) >> SC_DEBUG_7_event_flag_SHIFT) +#define SC_DEBUG_7_GET_deallocate(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_deallocate_MASK) >> SC_DEBUG_7_deallocate_SHIFT) +#define SC_DEBUG_7_GET_fposition(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_fposition_MASK) >> SC_DEBUG_7_fposition_SHIFT) +#define SC_DEBUG_7_GET_sr_prim_we(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_sr_prim_we_MASK) >> SC_DEBUG_7_sr_prim_we_SHIFT) +#define SC_DEBUG_7_GET_last_tile(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_last_tile_MASK) >> SC_DEBUG_7_last_tile_SHIFT) +#define SC_DEBUG_7_GET_tile_ff_we(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_tile_ff_we_MASK) >> SC_DEBUG_7_tile_ff_we_SHIFT) +#define SC_DEBUG_7_GET_qs_data_valid(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_qs_data_valid_MASK) >> SC_DEBUG_7_qs_data_valid_SHIFT) +#define SC_DEBUG_7_GET_qs_q0_y(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_qs_q0_y_MASK) >> SC_DEBUG_7_qs_q0_y_SHIFT) +#define SC_DEBUG_7_GET_qs_q0_x(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_qs_q0_x_MASK) >> SC_DEBUG_7_qs_q0_x_SHIFT) +#define SC_DEBUG_7_GET_qs_q0_valid(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_qs_q0_valid_MASK) >> SC_DEBUG_7_qs_q0_valid_SHIFT) +#define SC_DEBUG_7_GET_prim_ff_we(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_prim_ff_we_MASK) >> SC_DEBUG_7_prim_ff_we_SHIFT) +#define SC_DEBUG_7_GET_tile_ff_re(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_tile_ff_re_MASK) >> SC_DEBUG_7_tile_ff_re_SHIFT) +#define SC_DEBUG_7_GET_fw_prim_data_valid(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_fw_prim_data_valid_MASK) >> SC_DEBUG_7_fw_prim_data_valid_SHIFT) +#define SC_DEBUG_7_GET_last_quad_of_tile(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_last_quad_of_tile_MASK) >> SC_DEBUG_7_last_quad_of_tile_SHIFT) +#define SC_DEBUG_7_GET_first_quad_of_tile(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_first_quad_of_tile_MASK) >> SC_DEBUG_7_first_quad_of_tile_SHIFT) +#define SC_DEBUG_7_GET_first_quad_of_prim(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_first_quad_of_prim_MASK) >> SC_DEBUG_7_first_quad_of_prim_SHIFT) +#define SC_DEBUG_7_GET_new_prim(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_new_prim_MASK) >> SC_DEBUG_7_new_prim_SHIFT) +#define SC_DEBUG_7_GET_load_new_tile_data(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_load_new_tile_data_MASK) >> SC_DEBUG_7_load_new_tile_data_SHIFT) +#define SC_DEBUG_7_GET_state(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_state_MASK) >> SC_DEBUG_7_state_SHIFT) +#define SC_DEBUG_7_GET_fifos_ready(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_fifos_ready_MASK) >> SC_DEBUG_7_fifos_ready_SHIFT) +#define SC_DEBUG_7_GET_trigger(sc_debug_7) \ + ((sc_debug_7 & SC_DEBUG_7_trigger_MASK) >> SC_DEBUG_7_trigger_SHIFT) + +#define SC_DEBUG_7_SET_event_flag(sc_debug_7_reg, event_flag) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_event_flag_MASK) | (event_flag << SC_DEBUG_7_event_flag_SHIFT) +#define SC_DEBUG_7_SET_deallocate(sc_debug_7_reg, deallocate) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_deallocate_MASK) | (deallocate << SC_DEBUG_7_deallocate_SHIFT) +#define SC_DEBUG_7_SET_fposition(sc_debug_7_reg, fposition) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fposition_MASK) | (fposition << SC_DEBUG_7_fposition_SHIFT) +#define SC_DEBUG_7_SET_sr_prim_we(sc_debug_7_reg, sr_prim_we) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_sr_prim_we_MASK) | (sr_prim_we << SC_DEBUG_7_sr_prim_we_SHIFT) +#define SC_DEBUG_7_SET_last_tile(sc_debug_7_reg, last_tile) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_last_tile_MASK) | (last_tile << SC_DEBUG_7_last_tile_SHIFT) +#define SC_DEBUG_7_SET_tile_ff_we(sc_debug_7_reg, tile_ff_we) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_tile_ff_we_MASK) | (tile_ff_we << SC_DEBUG_7_tile_ff_we_SHIFT) +#define SC_DEBUG_7_SET_qs_data_valid(sc_debug_7_reg, qs_data_valid) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_data_valid_MASK) | (qs_data_valid << SC_DEBUG_7_qs_data_valid_SHIFT) +#define SC_DEBUG_7_SET_qs_q0_y(sc_debug_7_reg, qs_q0_y) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_y_MASK) | (qs_q0_y << SC_DEBUG_7_qs_q0_y_SHIFT) +#define SC_DEBUG_7_SET_qs_q0_x(sc_debug_7_reg, qs_q0_x) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_x_MASK) | (qs_q0_x << SC_DEBUG_7_qs_q0_x_SHIFT) +#define SC_DEBUG_7_SET_qs_q0_valid(sc_debug_7_reg, qs_q0_valid) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_qs_q0_valid_MASK) | (qs_q0_valid << SC_DEBUG_7_qs_q0_valid_SHIFT) +#define SC_DEBUG_7_SET_prim_ff_we(sc_debug_7_reg, prim_ff_we) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_prim_ff_we_MASK) | (prim_ff_we << SC_DEBUG_7_prim_ff_we_SHIFT) +#define SC_DEBUG_7_SET_tile_ff_re(sc_debug_7_reg, tile_ff_re) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_tile_ff_re_MASK) | (tile_ff_re << SC_DEBUG_7_tile_ff_re_SHIFT) +#define SC_DEBUG_7_SET_fw_prim_data_valid(sc_debug_7_reg, fw_prim_data_valid) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fw_prim_data_valid_MASK) | (fw_prim_data_valid << SC_DEBUG_7_fw_prim_data_valid_SHIFT) +#define SC_DEBUG_7_SET_last_quad_of_tile(sc_debug_7_reg, last_quad_of_tile) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_last_quad_of_tile_MASK) | (last_quad_of_tile << SC_DEBUG_7_last_quad_of_tile_SHIFT) +#define SC_DEBUG_7_SET_first_quad_of_tile(sc_debug_7_reg, first_quad_of_tile) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_first_quad_of_tile_MASK) | (first_quad_of_tile << SC_DEBUG_7_first_quad_of_tile_SHIFT) +#define SC_DEBUG_7_SET_first_quad_of_prim(sc_debug_7_reg, first_quad_of_prim) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_first_quad_of_prim_MASK) | (first_quad_of_prim << SC_DEBUG_7_first_quad_of_prim_SHIFT) +#define SC_DEBUG_7_SET_new_prim(sc_debug_7_reg, new_prim) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_new_prim_MASK) | (new_prim << SC_DEBUG_7_new_prim_SHIFT) +#define SC_DEBUG_7_SET_load_new_tile_data(sc_debug_7_reg, load_new_tile_data) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_load_new_tile_data_MASK) | (load_new_tile_data << SC_DEBUG_7_load_new_tile_data_SHIFT) +#define SC_DEBUG_7_SET_state(sc_debug_7_reg, state) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_state_MASK) | (state << SC_DEBUG_7_state_SHIFT) +#define SC_DEBUG_7_SET_fifos_ready(sc_debug_7_reg, fifos_ready) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_fifos_ready_MASK) | (fifos_ready << SC_DEBUG_7_fifos_ready_SHIFT) +#define SC_DEBUG_7_SET_trigger(sc_debug_7_reg, trigger) \ + sc_debug_7_reg = (sc_debug_7_reg & ~SC_DEBUG_7_trigger_MASK) | (trigger << SC_DEBUG_7_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_7_t { + unsigned int event_flag : SC_DEBUG_7_event_flag_SIZE; + unsigned int deallocate : SC_DEBUG_7_deallocate_SIZE; + unsigned int fposition : SC_DEBUG_7_fposition_SIZE; + unsigned int sr_prim_we : SC_DEBUG_7_sr_prim_we_SIZE; + unsigned int last_tile : SC_DEBUG_7_last_tile_SIZE; + unsigned int tile_ff_we : SC_DEBUG_7_tile_ff_we_SIZE; + unsigned int qs_data_valid : SC_DEBUG_7_qs_data_valid_SIZE; + unsigned int qs_q0_y : SC_DEBUG_7_qs_q0_y_SIZE; + unsigned int qs_q0_x : SC_DEBUG_7_qs_q0_x_SIZE; + unsigned int qs_q0_valid : SC_DEBUG_7_qs_q0_valid_SIZE; + unsigned int prim_ff_we : SC_DEBUG_7_prim_ff_we_SIZE; + unsigned int tile_ff_re : SC_DEBUG_7_tile_ff_re_SIZE; + unsigned int fw_prim_data_valid : SC_DEBUG_7_fw_prim_data_valid_SIZE; + unsigned int last_quad_of_tile : SC_DEBUG_7_last_quad_of_tile_SIZE; + unsigned int first_quad_of_tile : SC_DEBUG_7_first_quad_of_tile_SIZE; + unsigned int first_quad_of_prim : SC_DEBUG_7_first_quad_of_prim_SIZE; + unsigned int new_prim : SC_DEBUG_7_new_prim_SIZE; + unsigned int load_new_tile_data : SC_DEBUG_7_load_new_tile_data_SIZE; + unsigned int state : SC_DEBUG_7_state_SIZE; + unsigned int fifos_ready : SC_DEBUG_7_fifos_ready_SIZE; + unsigned int : 6; + unsigned int trigger : SC_DEBUG_7_trigger_SIZE; + } sc_debug_7_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_7_t { + unsigned int trigger : SC_DEBUG_7_trigger_SIZE; + unsigned int : 6; + unsigned int fifos_ready : SC_DEBUG_7_fifos_ready_SIZE; + unsigned int state : SC_DEBUG_7_state_SIZE; + unsigned int load_new_tile_data : SC_DEBUG_7_load_new_tile_data_SIZE; + unsigned int new_prim : SC_DEBUG_7_new_prim_SIZE; + unsigned int first_quad_of_prim : SC_DEBUG_7_first_quad_of_prim_SIZE; + unsigned int first_quad_of_tile : SC_DEBUG_7_first_quad_of_tile_SIZE; + unsigned int last_quad_of_tile : SC_DEBUG_7_last_quad_of_tile_SIZE; + unsigned int fw_prim_data_valid : SC_DEBUG_7_fw_prim_data_valid_SIZE; + unsigned int tile_ff_re : SC_DEBUG_7_tile_ff_re_SIZE; + unsigned int prim_ff_we : SC_DEBUG_7_prim_ff_we_SIZE; + unsigned int qs_q0_valid : SC_DEBUG_7_qs_q0_valid_SIZE; + unsigned int qs_q0_x : SC_DEBUG_7_qs_q0_x_SIZE; + unsigned int qs_q0_y : SC_DEBUG_7_qs_q0_y_SIZE; + unsigned int qs_data_valid : SC_DEBUG_7_qs_data_valid_SIZE; + unsigned int tile_ff_we : SC_DEBUG_7_tile_ff_we_SIZE; + unsigned int last_tile : SC_DEBUG_7_last_tile_SIZE; + unsigned int sr_prim_we : SC_DEBUG_7_sr_prim_we_SIZE; + unsigned int fposition : SC_DEBUG_7_fposition_SIZE; + unsigned int deallocate : SC_DEBUG_7_deallocate_SIZE; + unsigned int event_flag : SC_DEBUG_7_event_flag_SIZE; + } sc_debug_7_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_7_t f; +} sc_debug_7_u; + + +/* + * SC_DEBUG_8 struct + */ + +#define SC_DEBUG_8_sample_last_SIZE 1 +#define SC_DEBUG_8_sample_mask_SIZE 4 +#define SC_DEBUG_8_sample_y_SIZE 2 +#define SC_DEBUG_8_sample_x_SIZE 2 +#define SC_DEBUG_8_sample_send_SIZE 1 +#define SC_DEBUG_8_next_cycle_SIZE 2 +#define SC_DEBUG_8_ez_sample_ff_full_SIZE 1 +#define SC_DEBUG_8_rb_sc_samp_rtr_SIZE 1 +#define SC_DEBUG_8_num_samples_SIZE 2 +#define SC_DEBUG_8_last_quad_of_tile_SIZE 1 +#define SC_DEBUG_8_last_quad_of_prim_SIZE 1 +#define SC_DEBUG_8_first_quad_of_prim_SIZE 1 +#define SC_DEBUG_8_sample_we_SIZE 1 +#define SC_DEBUG_8_fposition_SIZE 1 +#define SC_DEBUG_8_event_id_SIZE 5 +#define SC_DEBUG_8_event_flag_SIZE 1 +#define SC_DEBUG_8_fw_prim_data_valid_SIZE 1 +#define SC_DEBUG_8_trigger_SIZE 1 + +#define SC_DEBUG_8_sample_last_SHIFT 0 +#define SC_DEBUG_8_sample_mask_SHIFT 1 +#define SC_DEBUG_8_sample_y_SHIFT 5 +#define SC_DEBUG_8_sample_x_SHIFT 7 +#define SC_DEBUG_8_sample_send_SHIFT 9 +#define SC_DEBUG_8_next_cycle_SHIFT 10 +#define SC_DEBUG_8_ez_sample_ff_full_SHIFT 12 +#define SC_DEBUG_8_rb_sc_samp_rtr_SHIFT 13 +#define SC_DEBUG_8_num_samples_SHIFT 14 +#define SC_DEBUG_8_last_quad_of_tile_SHIFT 16 +#define SC_DEBUG_8_last_quad_of_prim_SHIFT 17 +#define SC_DEBUG_8_first_quad_of_prim_SHIFT 18 +#define SC_DEBUG_8_sample_we_SHIFT 19 +#define SC_DEBUG_8_fposition_SHIFT 20 +#define SC_DEBUG_8_event_id_SHIFT 21 +#define SC_DEBUG_8_event_flag_SHIFT 26 +#define SC_DEBUG_8_fw_prim_data_valid_SHIFT 27 +#define SC_DEBUG_8_trigger_SHIFT 31 + +#define SC_DEBUG_8_sample_last_MASK 0x00000001 +#define SC_DEBUG_8_sample_mask_MASK 0x0000001e +#define SC_DEBUG_8_sample_y_MASK 0x00000060 +#define SC_DEBUG_8_sample_x_MASK 0x00000180 +#define SC_DEBUG_8_sample_send_MASK 0x00000200 +#define SC_DEBUG_8_next_cycle_MASK 0x00000c00 +#define SC_DEBUG_8_ez_sample_ff_full_MASK 0x00001000 +#define SC_DEBUG_8_rb_sc_samp_rtr_MASK 0x00002000 +#define SC_DEBUG_8_num_samples_MASK 0x0000c000 +#define SC_DEBUG_8_last_quad_of_tile_MASK 0x00010000 +#define SC_DEBUG_8_last_quad_of_prim_MASK 0x00020000 +#define SC_DEBUG_8_first_quad_of_prim_MASK 0x00040000 +#define SC_DEBUG_8_sample_we_MASK 0x00080000 +#define SC_DEBUG_8_fposition_MASK 0x00100000 +#define SC_DEBUG_8_event_id_MASK 0x03e00000 +#define SC_DEBUG_8_event_flag_MASK 0x04000000 +#define SC_DEBUG_8_fw_prim_data_valid_MASK 0x08000000 +#define SC_DEBUG_8_trigger_MASK 0x80000000 + +#define SC_DEBUG_8_MASK \ + (SC_DEBUG_8_sample_last_MASK | \ + SC_DEBUG_8_sample_mask_MASK | \ + SC_DEBUG_8_sample_y_MASK | \ + SC_DEBUG_8_sample_x_MASK | \ + SC_DEBUG_8_sample_send_MASK | \ + SC_DEBUG_8_next_cycle_MASK | \ + SC_DEBUG_8_ez_sample_ff_full_MASK | \ + SC_DEBUG_8_rb_sc_samp_rtr_MASK | \ + SC_DEBUG_8_num_samples_MASK | \ + SC_DEBUG_8_last_quad_of_tile_MASK | \ + SC_DEBUG_8_last_quad_of_prim_MASK | \ + SC_DEBUG_8_first_quad_of_prim_MASK | \ + SC_DEBUG_8_sample_we_MASK | \ + SC_DEBUG_8_fposition_MASK | \ + SC_DEBUG_8_event_id_MASK | \ + SC_DEBUG_8_event_flag_MASK | \ + SC_DEBUG_8_fw_prim_data_valid_MASK | \ + SC_DEBUG_8_trigger_MASK) + +#define SC_DEBUG_8(sample_last, sample_mask, sample_y, sample_x, sample_send, next_cycle, ez_sample_ff_full, rb_sc_samp_rtr, num_samples, last_quad_of_tile, last_quad_of_prim, first_quad_of_prim, sample_we, fposition, event_id, event_flag, fw_prim_data_valid, trigger) \ + ((sample_last << SC_DEBUG_8_sample_last_SHIFT) | \ + (sample_mask << SC_DEBUG_8_sample_mask_SHIFT) | \ + (sample_y << SC_DEBUG_8_sample_y_SHIFT) | \ + (sample_x << SC_DEBUG_8_sample_x_SHIFT) | \ + (sample_send << SC_DEBUG_8_sample_send_SHIFT) | \ + (next_cycle << SC_DEBUG_8_next_cycle_SHIFT) | \ + (ez_sample_ff_full << SC_DEBUG_8_ez_sample_ff_full_SHIFT) | \ + (rb_sc_samp_rtr << SC_DEBUG_8_rb_sc_samp_rtr_SHIFT) | \ + (num_samples << SC_DEBUG_8_num_samples_SHIFT) | \ + (last_quad_of_tile << SC_DEBUG_8_last_quad_of_tile_SHIFT) | \ + (last_quad_of_prim << SC_DEBUG_8_last_quad_of_prim_SHIFT) | \ + (first_quad_of_prim << SC_DEBUG_8_first_quad_of_prim_SHIFT) | \ + (sample_we << SC_DEBUG_8_sample_we_SHIFT) | \ + (fposition << SC_DEBUG_8_fposition_SHIFT) | \ + (event_id << SC_DEBUG_8_event_id_SHIFT) | \ + (event_flag << SC_DEBUG_8_event_flag_SHIFT) | \ + (fw_prim_data_valid << SC_DEBUG_8_fw_prim_data_valid_SHIFT) | \ + (trigger << SC_DEBUG_8_trigger_SHIFT)) + +#define SC_DEBUG_8_GET_sample_last(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_last_MASK) >> SC_DEBUG_8_sample_last_SHIFT) +#define SC_DEBUG_8_GET_sample_mask(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_mask_MASK) >> SC_DEBUG_8_sample_mask_SHIFT) +#define SC_DEBUG_8_GET_sample_y(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_y_MASK) >> SC_DEBUG_8_sample_y_SHIFT) +#define SC_DEBUG_8_GET_sample_x(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_x_MASK) >> SC_DEBUG_8_sample_x_SHIFT) +#define SC_DEBUG_8_GET_sample_send(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_send_MASK) >> SC_DEBUG_8_sample_send_SHIFT) +#define SC_DEBUG_8_GET_next_cycle(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_next_cycle_MASK) >> SC_DEBUG_8_next_cycle_SHIFT) +#define SC_DEBUG_8_GET_ez_sample_ff_full(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_ez_sample_ff_full_MASK) >> SC_DEBUG_8_ez_sample_ff_full_SHIFT) +#define SC_DEBUG_8_GET_rb_sc_samp_rtr(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_rb_sc_samp_rtr_MASK) >> SC_DEBUG_8_rb_sc_samp_rtr_SHIFT) +#define SC_DEBUG_8_GET_num_samples(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_num_samples_MASK) >> SC_DEBUG_8_num_samples_SHIFT) +#define SC_DEBUG_8_GET_last_quad_of_tile(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_last_quad_of_tile_MASK) >> SC_DEBUG_8_last_quad_of_tile_SHIFT) +#define SC_DEBUG_8_GET_last_quad_of_prim(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_last_quad_of_prim_MASK) >> SC_DEBUG_8_last_quad_of_prim_SHIFT) +#define SC_DEBUG_8_GET_first_quad_of_prim(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_first_quad_of_prim_MASK) >> SC_DEBUG_8_first_quad_of_prim_SHIFT) +#define SC_DEBUG_8_GET_sample_we(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_sample_we_MASK) >> SC_DEBUG_8_sample_we_SHIFT) +#define SC_DEBUG_8_GET_fposition(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_fposition_MASK) >> SC_DEBUG_8_fposition_SHIFT) +#define SC_DEBUG_8_GET_event_id(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_event_id_MASK) >> SC_DEBUG_8_event_id_SHIFT) +#define SC_DEBUG_8_GET_event_flag(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_event_flag_MASK) >> SC_DEBUG_8_event_flag_SHIFT) +#define SC_DEBUG_8_GET_fw_prim_data_valid(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_fw_prim_data_valid_MASK) >> SC_DEBUG_8_fw_prim_data_valid_SHIFT) +#define SC_DEBUG_8_GET_trigger(sc_debug_8) \ + ((sc_debug_8 & SC_DEBUG_8_trigger_MASK) >> SC_DEBUG_8_trigger_SHIFT) + +#define SC_DEBUG_8_SET_sample_last(sc_debug_8_reg, sample_last) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_last_MASK) | (sample_last << SC_DEBUG_8_sample_last_SHIFT) +#define SC_DEBUG_8_SET_sample_mask(sc_debug_8_reg, sample_mask) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_mask_MASK) | (sample_mask << SC_DEBUG_8_sample_mask_SHIFT) +#define SC_DEBUG_8_SET_sample_y(sc_debug_8_reg, sample_y) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_y_MASK) | (sample_y << SC_DEBUG_8_sample_y_SHIFT) +#define SC_DEBUG_8_SET_sample_x(sc_debug_8_reg, sample_x) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_x_MASK) | (sample_x << SC_DEBUG_8_sample_x_SHIFT) +#define SC_DEBUG_8_SET_sample_send(sc_debug_8_reg, sample_send) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_send_MASK) | (sample_send << SC_DEBUG_8_sample_send_SHIFT) +#define SC_DEBUG_8_SET_next_cycle(sc_debug_8_reg, next_cycle) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_next_cycle_MASK) | (next_cycle << SC_DEBUG_8_next_cycle_SHIFT) +#define SC_DEBUG_8_SET_ez_sample_ff_full(sc_debug_8_reg, ez_sample_ff_full) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_ez_sample_ff_full_MASK) | (ez_sample_ff_full << SC_DEBUG_8_ez_sample_ff_full_SHIFT) +#define SC_DEBUG_8_SET_rb_sc_samp_rtr(sc_debug_8_reg, rb_sc_samp_rtr) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_rb_sc_samp_rtr_MASK) | (rb_sc_samp_rtr << SC_DEBUG_8_rb_sc_samp_rtr_SHIFT) +#define SC_DEBUG_8_SET_num_samples(sc_debug_8_reg, num_samples) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_num_samples_MASK) | (num_samples << SC_DEBUG_8_num_samples_SHIFT) +#define SC_DEBUG_8_SET_last_quad_of_tile(sc_debug_8_reg, last_quad_of_tile) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_last_quad_of_tile_MASK) | (last_quad_of_tile << SC_DEBUG_8_last_quad_of_tile_SHIFT) +#define SC_DEBUG_8_SET_last_quad_of_prim(sc_debug_8_reg, last_quad_of_prim) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_last_quad_of_prim_MASK) | (last_quad_of_prim << SC_DEBUG_8_last_quad_of_prim_SHIFT) +#define SC_DEBUG_8_SET_first_quad_of_prim(sc_debug_8_reg, first_quad_of_prim) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_first_quad_of_prim_MASK) | (first_quad_of_prim << SC_DEBUG_8_first_quad_of_prim_SHIFT) +#define SC_DEBUG_8_SET_sample_we(sc_debug_8_reg, sample_we) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_sample_we_MASK) | (sample_we << SC_DEBUG_8_sample_we_SHIFT) +#define SC_DEBUG_8_SET_fposition(sc_debug_8_reg, fposition) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_fposition_MASK) | (fposition << SC_DEBUG_8_fposition_SHIFT) +#define SC_DEBUG_8_SET_event_id(sc_debug_8_reg, event_id) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_event_id_MASK) | (event_id << SC_DEBUG_8_event_id_SHIFT) +#define SC_DEBUG_8_SET_event_flag(sc_debug_8_reg, event_flag) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_event_flag_MASK) | (event_flag << SC_DEBUG_8_event_flag_SHIFT) +#define SC_DEBUG_8_SET_fw_prim_data_valid(sc_debug_8_reg, fw_prim_data_valid) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_fw_prim_data_valid_MASK) | (fw_prim_data_valid << SC_DEBUG_8_fw_prim_data_valid_SHIFT) +#define SC_DEBUG_8_SET_trigger(sc_debug_8_reg, trigger) \ + sc_debug_8_reg = (sc_debug_8_reg & ~SC_DEBUG_8_trigger_MASK) | (trigger << SC_DEBUG_8_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_8_t { + unsigned int sample_last : SC_DEBUG_8_sample_last_SIZE; + unsigned int sample_mask : SC_DEBUG_8_sample_mask_SIZE; + unsigned int sample_y : SC_DEBUG_8_sample_y_SIZE; + unsigned int sample_x : SC_DEBUG_8_sample_x_SIZE; + unsigned int sample_send : SC_DEBUG_8_sample_send_SIZE; + unsigned int next_cycle : SC_DEBUG_8_next_cycle_SIZE; + unsigned int ez_sample_ff_full : SC_DEBUG_8_ez_sample_ff_full_SIZE; + unsigned int rb_sc_samp_rtr : SC_DEBUG_8_rb_sc_samp_rtr_SIZE; + unsigned int num_samples : SC_DEBUG_8_num_samples_SIZE; + unsigned int last_quad_of_tile : SC_DEBUG_8_last_quad_of_tile_SIZE; + unsigned int last_quad_of_prim : SC_DEBUG_8_last_quad_of_prim_SIZE; + unsigned int first_quad_of_prim : SC_DEBUG_8_first_quad_of_prim_SIZE; + unsigned int sample_we : SC_DEBUG_8_sample_we_SIZE; + unsigned int fposition : SC_DEBUG_8_fposition_SIZE; + unsigned int event_id : SC_DEBUG_8_event_id_SIZE; + unsigned int event_flag : SC_DEBUG_8_event_flag_SIZE; + unsigned int fw_prim_data_valid : SC_DEBUG_8_fw_prim_data_valid_SIZE; + unsigned int : 3; + unsigned int trigger : SC_DEBUG_8_trigger_SIZE; + } sc_debug_8_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_8_t { + unsigned int trigger : SC_DEBUG_8_trigger_SIZE; + unsigned int : 3; + unsigned int fw_prim_data_valid : SC_DEBUG_8_fw_prim_data_valid_SIZE; + unsigned int event_flag : SC_DEBUG_8_event_flag_SIZE; + unsigned int event_id : SC_DEBUG_8_event_id_SIZE; + unsigned int fposition : SC_DEBUG_8_fposition_SIZE; + unsigned int sample_we : SC_DEBUG_8_sample_we_SIZE; + unsigned int first_quad_of_prim : SC_DEBUG_8_first_quad_of_prim_SIZE; + unsigned int last_quad_of_prim : SC_DEBUG_8_last_quad_of_prim_SIZE; + unsigned int last_quad_of_tile : SC_DEBUG_8_last_quad_of_tile_SIZE; + unsigned int num_samples : SC_DEBUG_8_num_samples_SIZE; + unsigned int rb_sc_samp_rtr : SC_DEBUG_8_rb_sc_samp_rtr_SIZE; + unsigned int ez_sample_ff_full : SC_DEBUG_8_ez_sample_ff_full_SIZE; + unsigned int next_cycle : SC_DEBUG_8_next_cycle_SIZE; + unsigned int sample_send : SC_DEBUG_8_sample_send_SIZE; + unsigned int sample_x : SC_DEBUG_8_sample_x_SIZE; + unsigned int sample_y : SC_DEBUG_8_sample_y_SIZE; + unsigned int sample_mask : SC_DEBUG_8_sample_mask_SIZE; + unsigned int sample_last : SC_DEBUG_8_sample_last_SIZE; + } sc_debug_8_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_8_t f; +} sc_debug_8_u; + + +/* + * SC_DEBUG_9 struct + */ + +#define SC_DEBUG_9_rb_sc_send_SIZE 1 +#define SC_DEBUG_9_rb_sc_ez_mask_SIZE 4 +#define SC_DEBUG_9_fifo_data_ready_SIZE 1 +#define SC_DEBUG_9_early_z_enable_SIZE 1 +#define SC_DEBUG_9_mask_state_SIZE 2 +#define SC_DEBUG_9_next_ez_mask_SIZE 16 +#define SC_DEBUG_9_mask_ready_SIZE 1 +#define SC_DEBUG_9_drop_sample_SIZE 1 +#define SC_DEBUG_9_fetch_new_sample_data_SIZE 1 +#define SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE 1 +#define SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE 1 +#define SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE 1 +#define SC_DEBUG_9_trigger_SIZE 1 + +#define SC_DEBUG_9_rb_sc_send_SHIFT 0 +#define SC_DEBUG_9_rb_sc_ez_mask_SHIFT 1 +#define SC_DEBUG_9_fifo_data_ready_SHIFT 5 +#define SC_DEBUG_9_early_z_enable_SHIFT 6 +#define SC_DEBUG_9_mask_state_SHIFT 7 +#define SC_DEBUG_9_next_ez_mask_SHIFT 9 +#define SC_DEBUG_9_mask_ready_SHIFT 25 +#define SC_DEBUG_9_drop_sample_SHIFT 26 +#define SC_DEBUG_9_fetch_new_sample_data_SHIFT 27 +#define SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT 28 +#define SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT 29 +#define SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT 30 +#define SC_DEBUG_9_trigger_SHIFT 31 + +#define SC_DEBUG_9_rb_sc_send_MASK 0x00000001 +#define SC_DEBUG_9_rb_sc_ez_mask_MASK 0x0000001e +#define SC_DEBUG_9_fifo_data_ready_MASK 0x00000020 +#define SC_DEBUG_9_early_z_enable_MASK 0x00000040 +#define SC_DEBUG_9_mask_state_MASK 0x00000180 +#define SC_DEBUG_9_next_ez_mask_MASK 0x01fffe00 +#define SC_DEBUG_9_mask_ready_MASK 0x02000000 +#define SC_DEBUG_9_drop_sample_MASK 0x04000000 +#define SC_DEBUG_9_fetch_new_sample_data_MASK 0x08000000 +#define SC_DEBUG_9_fetch_new_ez_sample_mask_MASK 0x10000000 +#define SC_DEBUG_9_pkr_fetch_new_sample_data_MASK 0x20000000 +#define SC_DEBUG_9_pkr_fetch_new_prim_data_MASK 0x40000000 +#define SC_DEBUG_9_trigger_MASK 0x80000000 + +#define SC_DEBUG_9_MASK \ + (SC_DEBUG_9_rb_sc_send_MASK | \ + SC_DEBUG_9_rb_sc_ez_mask_MASK | \ + SC_DEBUG_9_fifo_data_ready_MASK | \ + SC_DEBUG_9_early_z_enable_MASK | \ + SC_DEBUG_9_mask_state_MASK | \ + SC_DEBUG_9_next_ez_mask_MASK | \ + SC_DEBUG_9_mask_ready_MASK | \ + SC_DEBUG_9_drop_sample_MASK | \ + SC_DEBUG_9_fetch_new_sample_data_MASK | \ + SC_DEBUG_9_fetch_new_ez_sample_mask_MASK | \ + SC_DEBUG_9_pkr_fetch_new_sample_data_MASK | \ + SC_DEBUG_9_pkr_fetch_new_prim_data_MASK | \ + SC_DEBUG_9_trigger_MASK) + +#define SC_DEBUG_9(rb_sc_send, rb_sc_ez_mask, fifo_data_ready, early_z_enable, mask_state, next_ez_mask, mask_ready, drop_sample, fetch_new_sample_data, fetch_new_ez_sample_mask, pkr_fetch_new_sample_data, pkr_fetch_new_prim_data, trigger) \ + ((rb_sc_send << SC_DEBUG_9_rb_sc_send_SHIFT) | \ + (rb_sc_ez_mask << SC_DEBUG_9_rb_sc_ez_mask_SHIFT) | \ + (fifo_data_ready << SC_DEBUG_9_fifo_data_ready_SHIFT) | \ + (early_z_enable << SC_DEBUG_9_early_z_enable_SHIFT) | \ + (mask_state << SC_DEBUG_9_mask_state_SHIFT) | \ + (next_ez_mask << SC_DEBUG_9_next_ez_mask_SHIFT) | \ + (mask_ready << SC_DEBUG_9_mask_ready_SHIFT) | \ + (drop_sample << SC_DEBUG_9_drop_sample_SHIFT) | \ + (fetch_new_sample_data << SC_DEBUG_9_fetch_new_sample_data_SHIFT) | \ + (fetch_new_ez_sample_mask << SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT) | \ + (pkr_fetch_new_sample_data << SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT) | \ + (pkr_fetch_new_prim_data << SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT) | \ + (trigger << SC_DEBUG_9_trigger_SHIFT)) + +#define SC_DEBUG_9_GET_rb_sc_send(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_rb_sc_send_MASK) >> SC_DEBUG_9_rb_sc_send_SHIFT) +#define SC_DEBUG_9_GET_rb_sc_ez_mask(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_rb_sc_ez_mask_MASK) >> SC_DEBUG_9_rb_sc_ez_mask_SHIFT) +#define SC_DEBUG_9_GET_fifo_data_ready(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_fifo_data_ready_MASK) >> SC_DEBUG_9_fifo_data_ready_SHIFT) +#define SC_DEBUG_9_GET_early_z_enable(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_early_z_enable_MASK) >> SC_DEBUG_9_early_z_enable_SHIFT) +#define SC_DEBUG_9_GET_mask_state(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_mask_state_MASK) >> SC_DEBUG_9_mask_state_SHIFT) +#define SC_DEBUG_9_GET_next_ez_mask(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_next_ez_mask_MASK) >> SC_DEBUG_9_next_ez_mask_SHIFT) +#define SC_DEBUG_9_GET_mask_ready(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_mask_ready_MASK) >> SC_DEBUG_9_mask_ready_SHIFT) +#define SC_DEBUG_9_GET_drop_sample(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_drop_sample_MASK) >> SC_DEBUG_9_drop_sample_SHIFT) +#define SC_DEBUG_9_GET_fetch_new_sample_data(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_fetch_new_sample_data_MASK) >> SC_DEBUG_9_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_9_GET_fetch_new_ez_sample_mask(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_fetch_new_ez_sample_mask_MASK) >> SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT) +#define SC_DEBUG_9_GET_pkr_fetch_new_sample_data(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_pkr_fetch_new_sample_data_MASK) >> SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_9_GET_pkr_fetch_new_prim_data(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_pkr_fetch_new_prim_data_MASK) >> SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT) +#define SC_DEBUG_9_GET_trigger(sc_debug_9) \ + ((sc_debug_9 & SC_DEBUG_9_trigger_MASK) >> SC_DEBUG_9_trigger_SHIFT) + +#define SC_DEBUG_9_SET_rb_sc_send(sc_debug_9_reg, rb_sc_send) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_rb_sc_send_MASK) | (rb_sc_send << SC_DEBUG_9_rb_sc_send_SHIFT) +#define SC_DEBUG_9_SET_rb_sc_ez_mask(sc_debug_9_reg, rb_sc_ez_mask) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_rb_sc_ez_mask_MASK) | (rb_sc_ez_mask << SC_DEBUG_9_rb_sc_ez_mask_SHIFT) +#define SC_DEBUG_9_SET_fifo_data_ready(sc_debug_9_reg, fifo_data_ready) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fifo_data_ready_MASK) | (fifo_data_ready << SC_DEBUG_9_fifo_data_ready_SHIFT) +#define SC_DEBUG_9_SET_early_z_enable(sc_debug_9_reg, early_z_enable) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_early_z_enable_MASK) | (early_z_enable << SC_DEBUG_9_early_z_enable_SHIFT) +#define SC_DEBUG_9_SET_mask_state(sc_debug_9_reg, mask_state) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_mask_state_MASK) | (mask_state << SC_DEBUG_9_mask_state_SHIFT) +#define SC_DEBUG_9_SET_next_ez_mask(sc_debug_9_reg, next_ez_mask) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_next_ez_mask_MASK) | (next_ez_mask << SC_DEBUG_9_next_ez_mask_SHIFT) +#define SC_DEBUG_9_SET_mask_ready(sc_debug_9_reg, mask_ready) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_mask_ready_MASK) | (mask_ready << SC_DEBUG_9_mask_ready_SHIFT) +#define SC_DEBUG_9_SET_drop_sample(sc_debug_9_reg, drop_sample) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_drop_sample_MASK) | (drop_sample << SC_DEBUG_9_drop_sample_SHIFT) +#define SC_DEBUG_9_SET_fetch_new_sample_data(sc_debug_9_reg, fetch_new_sample_data) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fetch_new_sample_data_MASK) | (fetch_new_sample_data << SC_DEBUG_9_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_9_SET_fetch_new_ez_sample_mask(sc_debug_9_reg, fetch_new_ez_sample_mask) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_fetch_new_ez_sample_mask_MASK) | (fetch_new_ez_sample_mask << SC_DEBUG_9_fetch_new_ez_sample_mask_SHIFT) +#define SC_DEBUG_9_SET_pkr_fetch_new_sample_data(sc_debug_9_reg, pkr_fetch_new_sample_data) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_pkr_fetch_new_sample_data_MASK) | (pkr_fetch_new_sample_data << SC_DEBUG_9_pkr_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_9_SET_pkr_fetch_new_prim_data(sc_debug_9_reg, pkr_fetch_new_prim_data) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_pkr_fetch_new_prim_data_MASK) | (pkr_fetch_new_prim_data << SC_DEBUG_9_pkr_fetch_new_prim_data_SHIFT) +#define SC_DEBUG_9_SET_trigger(sc_debug_9_reg, trigger) \ + sc_debug_9_reg = (sc_debug_9_reg & ~SC_DEBUG_9_trigger_MASK) | (trigger << SC_DEBUG_9_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_9_t { + unsigned int rb_sc_send : SC_DEBUG_9_rb_sc_send_SIZE; + unsigned int rb_sc_ez_mask : SC_DEBUG_9_rb_sc_ez_mask_SIZE; + unsigned int fifo_data_ready : SC_DEBUG_9_fifo_data_ready_SIZE; + unsigned int early_z_enable : SC_DEBUG_9_early_z_enable_SIZE; + unsigned int mask_state : SC_DEBUG_9_mask_state_SIZE; + unsigned int next_ez_mask : SC_DEBUG_9_next_ez_mask_SIZE; + unsigned int mask_ready : SC_DEBUG_9_mask_ready_SIZE; + unsigned int drop_sample : SC_DEBUG_9_drop_sample_SIZE; + unsigned int fetch_new_sample_data : SC_DEBUG_9_fetch_new_sample_data_SIZE; + unsigned int fetch_new_ez_sample_mask : SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE; + unsigned int pkr_fetch_new_sample_data : SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE; + unsigned int pkr_fetch_new_prim_data : SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE; + unsigned int trigger : SC_DEBUG_9_trigger_SIZE; + } sc_debug_9_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_9_t { + unsigned int trigger : SC_DEBUG_9_trigger_SIZE; + unsigned int pkr_fetch_new_prim_data : SC_DEBUG_9_pkr_fetch_new_prim_data_SIZE; + unsigned int pkr_fetch_new_sample_data : SC_DEBUG_9_pkr_fetch_new_sample_data_SIZE; + unsigned int fetch_new_ez_sample_mask : SC_DEBUG_9_fetch_new_ez_sample_mask_SIZE; + unsigned int fetch_new_sample_data : SC_DEBUG_9_fetch_new_sample_data_SIZE; + unsigned int drop_sample : SC_DEBUG_9_drop_sample_SIZE; + unsigned int mask_ready : SC_DEBUG_9_mask_ready_SIZE; + unsigned int next_ez_mask : SC_DEBUG_9_next_ez_mask_SIZE; + unsigned int mask_state : SC_DEBUG_9_mask_state_SIZE; + unsigned int early_z_enable : SC_DEBUG_9_early_z_enable_SIZE; + unsigned int fifo_data_ready : SC_DEBUG_9_fifo_data_ready_SIZE; + unsigned int rb_sc_ez_mask : SC_DEBUG_9_rb_sc_ez_mask_SIZE; + unsigned int rb_sc_send : SC_DEBUG_9_rb_sc_send_SIZE; + } sc_debug_9_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_9_t f; +} sc_debug_9_u; + + +/* + * SC_DEBUG_10 struct + */ + +#define SC_DEBUG_10_combined_sample_mask_SIZE 16 +#define SC_DEBUG_10_trigger_SIZE 1 + +#define SC_DEBUG_10_combined_sample_mask_SHIFT 0 +#define SC_DEBUG_10_trigger_SHIFT 31 + +#define SC_DEBUG_10_combined_sample_mask_MASK 0x0000ffff +#define SC_DEBUG_10_trigger_MASK 0x80000000 + +#define SC_DEBUG_10_MASK \ + (SC_DEBUG_10_combined_sample_mask_MASK | \ + SC_DEBUG_10_trigger_MASK) + +#define SC_DEBUG_10(combined_sample_mask, trigger) \ + ((combined_sample_mask << SC_DEBUG_10_combined_sample_mask_SHIFT) | \ + (trigger << SC_DEBUG_10_trigger_SHIFT)) + +#define SC_DEBUG_10_GET_combined_sample_mask(sc_debug_10) \ + ((sc_debug_10 & SC_DEBUG_10_combined_sample_mask_MASK) >> SC_DEBUG_10_combined_sample_mask_SHIFT) +#define SC_DEBUG_10_GET_trigger(sc_debug_10) \ + ((sc_debug_10 & SC_DEBUG_10_trigger_MASK) >> SC_DEBUG_10_trigger_SHIFT) + +#define SC_DEBUG_10_SET_combined_sample_mask(sc_debug_10_reg, combined_sample_mask) \ + sc_debug_10_reg = (sc_debug_10_reg & ~SC_DEBUG_10_combined_sample_mask_MASK) | (combined_sample_mask << SC_DEBUG_10_combined_sample_mask_SHIFT) +#define SC_DEBUG_10_SET_trigger(sc_debug_10_reg, trigger) \ + sc_debug_10_reg = (sc_debug_10_reg & ~SC_DEBUG_10_trigger_MASK) | (trigger << SC_DEBUG_10_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_10_t { + unsigned int combined_sample_mask : SC_DEBUG_10_combined_sample_mask_SIZE; + unsigned int : 15; + unsigned int trigger : SC_DEBUG_10_trigger_SIZE; + } sc_debug_10_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_10_t { + unsigned int trigger : SC_DEBUG_10_trigger_SIZE; + unsigned int : 15; + unsigned int combined_sample_mask : SC_DEBUG_10_combined_sample_mask_SIZE; + } sc_debug_10_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_10_t f; +} sc_debug_10_u; + + +/* + * SC_DEBUG_11 struct + */ + +#define SC_DEBUG_11_ez_sample_data_ready_SIZE 1 +#define SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE 1 +#define SC_DEBUG_11_ez_prim_data_ready_SIZE 1 +#define SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE 1 +#define SC_DEBUG_11_iterator_input_fz_SIZE 1 +#define SC_DEBUG_11_packer_send_quads_SIZE 1 +#define SC_DEBUG_11_packer_send_cmd_SIZE 1 +#define SC_DEBUG_11_packer_send_event_SIZE 1 +#define SC_DEBUG_11_next_state_SIZE 3 +#define SC_DEBUG_11_state_SIZE 3 +#define SC_DEBUG_11_stall_SIZE 1 +#define SC_DEBUG_11_trigger_SIZE 1 + +#define SC_DEBUG_11_ez_sample_data_ready_SHIFT 0 +#define SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT 1 +#define SC_DEBUG_11_ez_prim_data_ready_SHIFT 2 +#define SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT 3 +#define SC_DEBUG_11_iterator_input_fz_SHIFT 4 +#define SC_DEBUG_11_packer_send_quads_SHIFT 5 +#define SC_DEBUG_11_packer_send_cmd_SHIFT 6 +#define SC_DEBUG_11_packer_send_event_SHIFT 7 +#define SC_DEBUG_11_next_state_SHIFT 8 +#define SC_DEBUG_11_state_SHIFT 11 +#define SC_DEBUG_11_stall_SHIFT 14 +#define SC_DEBUG_11_trigger_SHIFT 31 + +#define SC_DEBUG_11_ez_sample_data_ready_MASK 0x00000001 +#define SC_DEBUG_11_pkr_fetch_new_sample_data_MASK 0x00000002 +#define SC_DEBUG_11_ez_prim_data_ready_MASK 0x00000004 +#define SC_DEBUG_11_pkr_fetch_new_prim_data_MASK 0x00000008 +#define SC_DEBUG_11_iterator_input_fz_MASK 0x00000010 +#define SC_DEBUG_11_packer_send_quads_MASK 0x00000020 +#define SC_DEBUG_11_packer_send_cmd_MASK 0x00000040 +#define SC_DEBUG_11_packer_send_event_MASK 0x00000080 +#define SC_DEBUG_11_next_state_MASK 0x00000700 +#define SC_DEBUG_11_state_MASK 0x00003800 +#define SC_DEBUG_11_stall_MASK 0x00004000 +#define SC_DEBUG_11_trigger_MASK 0x80000000 + +#define SC_DEBUG_11_MASK \ + (SC_DEBUG_11_ez_sample_data_ready_MASK | \ + SC_DEBUG_11_pkr_fetch_new_sample_data_MASK | \ + SC_DEBUG_11_ez_prim_data_ready_MASK | \ + SC_DEBUG_11_pkr_fetch_new_prim_data_MASK | \ + SC_DEBUG_11_iterator_input_fz_MASK | \ + SC_DEBUG_11_packer_send_quads_MASK | \ + SC_DEBUG_11_packer_send_cmd_MASK | \ + SC_DEBUG_11_packer_send_event_MASK | \ + SC_DEBUG_11_next_state_MASK | \ + SC_DEBUG_11_state_MASK | \ + SC_DEBUG_11_stall_MASK | \ + SC_DEBUG_11_trigger_MASK) + +#define SC_DEBUG_11(ez_sample_data_ready, pkr_fetch_new_sample_data, ez_prim_data_ready, pkr_fetch_new_prim_data, iterator_input_fz, packer_send_quads, packer_send_cmd, packer_send_event, next_state, state, stall, trigger) \ + ((ez_sample_data_ready << SC_DEBUG_11_ez_sample_data_ready_SHIFT) | \ + (pkr_fetch_new_sample_data << SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT) | \ + (ez_prim_data_ready << SC_DEBUG_11_ez_prim_data_ready_SHIFT) | \ + (pkr_fetch_new_prim_data << SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT) | \ + (iterator_input_fz << SC_DEBUG_11_iterator_input_fz_SHIFT) | \ + (packer_send_quads << SC_DEBUG_11_packer_send_quads_SHIFT) | \ + (packer_send_cmd << SC_DEBUG_11_packer_send_cmd_SHIFT) | \ + (packer_send_event << SC_DEBUG_11_packer_send_event_SHIFT) | \ + (next_state << SC_DEBUG_11_next_state_SHIFT) | \ + (state << SC_DEBUG_11_state_SHIFT) | \ + (stall << SC_DEBUG_11_stall_SHIFT) | \ + (trigger << SC_DEBUG_11_trigger_SHIFT)) + +#define SC_DEBUG_11_GET_ez_sample_data_ready(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_ez_sample_data_ready_MASK) >> SC_DEBUG_11_ez_sample_data_ready_SHIFT) +#define SC_DEBUG_11_GET_pkr_fetch_new_sample_data(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_pkr_fetch_new_sample_data_MASK) >> SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_11_GET_ez_prim_data_ready(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_ez_prim_data_ready_MASK) >> SC_DEBUG_11_ez_prim_data_ready_SHIFT) +#define SC_DEBUG_11_GET_pkr_fetch_new_prim_data(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_pkr_fetch_new_prim_data_MASK) >> SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT) +#define SC_DEBUG_11_GET_iterator_input_fz(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_iterator_input_fz_MASK) >> SC_DEBUG_11_iterator_input_fz_SHIFT) +#define SC_DEBUG_11_GET_packer_send_quads(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_packer_send_quads_MASK) >> SC_DEBUG_11_packer_send_quads_SHIFT) +#define SC_DEBUG_11_GET_packer_send_cmd(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_packer_send_cmd_MASK) >> SC_DEBUG_11_packer_send_cmd_SHIFT) +#define SC_DEBUG_11_GET_packer_send_event(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_packer_send_event_MASK) >> SC_DEBUG_11_packer_send_event_SHIFT) +#define SC_DEBUG_11_GET_next_state(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_next_state_MASK) >> SC_DEBUG_11_next_state_SHIFT) +#define SC_DEBUG_11_GET_state(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_state_MASK) >> SC_DEBUG_11_state_SHIFT) +#define SC_DEBUG_11_GET_stall(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_stall_MASK) >> SC_DEBUG_11_stall_SHIFT) +#define SC_DEBUG_11_GET_trigger(sc_debug_11) \ + ((sc_debug_11 & SC_DEBUG_11_trigger_MASK) >> SC_DEBUG_11_trigger_SHIFT) + +#define SC_DEBUG_11_SET_ez_sample_data_ready(sc_debug_11_reg, ez_sample_data_ready) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_ez_sample_data_ready_MASK) | (ez_sample_data_ready << SC_DEBUG_11_ez_sample_data_ready_SHIFT) +#define SC_DEBUG_11_SET_pkr_fetch_new_sample_data(sc_debug_11_reg, pkr_fetch_new_sample_data) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_pkr_fetch_new_sample_data_MASK) | (pkr_fetch_new_sample_data << SC_DEBUG_11_pkr_fetch_new_sample_data_SHIFT) +#define SC_DEBUG_11_SET_ez_prim_data_ready(sc_debug_11_reg, ez_prim_data_ready) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_ez_prim_data_ready_MASK) | (ez_prim_data_ready << SC_DEBUG_11_ez_prim_data_ready_SHIFT) +#define SC_DEBUG_11_SET_pkr_fetch_new_prim_data(sc_debug_11_reg, pkr_fetch_new_prim_data) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_pkr_fetch_new_prim_data_MASK) | (pkr_fetch_new_prim_data << SC_DEBUG_11_pkr_fetch_new_prim_data_SHIFT) +#define SC_DEBUG_11_SET_iterator_input_fz(sc_debug_11_reg, iterator_input_fz) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_iterator_input_fz_MASK) | (iterator_input_fz << SC_DEBUG_11_iterator_input_fz_SHIFT) +#define SC_DEBUG_11_SET_packer_send_quads(sc_debug_11_reg, packer_send_quads) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_quads_MASK) | (packer_send_quads << SC_DEBUG_11_packer_send_quads_SHIFT) +#define SC_DEBUG_11_SET_packer_send_cmd(sc_debug_11_reg, packer_send_cmd) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_cmd_MASK) | (packer_send_cmd << SC_DEBUG_11_packer_send_cmd_SHIFT) +#define SC_DEBUG_11_SET_packer_send_event(sc_debug_11_reg, packer_send_event) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_packer_send_event_MASK) | (packer_send_event << SC_DEBUG_11_packer_send_event_SHIFT) +#define SC_DEBUG_11_SET_next_state(sc_debug_11_reg, next_state) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_next_state_MASK) | (next_state << SC_DEBUG_11_next_state_SHIFT) +#define SC_DEBUG_11_SET_state(sc_debug_11_reg, state) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_state_MASK) | (state << SC_DEBUG_11_state_SHIFT) +#define SC_DEBUG_11_SET_stall(sc_debug_11_reg, stall) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_stall_MASK) | (stall << SC_DEBUG_11_stall_SHIFT) +#define SC_DEBUG_11_SET_trigger(sc_debug_11_reg, trigger) \ + sc_debug_11_reg = (sc_debug_11_reg & ~SC_DEBUG_11_trigger_MASK) | (trigger << SC_DEBUG_11_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_11_t { + unsigned int ez_sample_data_ready : SC_DEBUG_11_ez_sample_data_ready_SIZE; + unsigned int pkr_fetch_new_sample_data : SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE; + unsigned int ez_prim_data_ready : SC_DEBUG_11_ez_prim_data_ready_SIZE; + unsigned int pkr_fetch_new_prim_data : SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE; + unsigned int iterator_input_fz : SC_DEBUG_11_iterator_input_fz_SIZE; + unsigned int packer_send_quads : SC_DEBUG_11_packer_send_quads_SIZE; + unsigned int packer_send_cmd : SC_DEBUG_11_packer_send_cmd_SIZE; + unsigned int packer_send_event : SC_DEBUG_11_packer_send_event_SIZE; + unsigned int next_state : SC_DEBUG_11_next_state_SIZE; + unsigned int state : SC_DEBUG_11_state_SIZE; + unsigned int stall : SC_DEBUG_11_stall_SIZE; + unsigned int : 16; + unsigned int trigger : SC_DEBUG_11_trigger_SIZE; + } sc_debug_11_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_11_t { + unsigned int trigger : SC_DEBUG_11_trigger_SIZE; + unsigned int : 16; + unsigned int stall : SC_DEBUG_11_stall_SIZE; + unsigned int state : SC_DEBUG_11_state_SIZE; + unsigned int next_state : SC_DEBUG_11_next_state_SIZE; + unsigned int packer_send_event : SC_DEBUG_11_packer_send_event_SIZE; + unsigned int packer_send_cmd : SC_DEBUG_11_packer_send_cmd_SIZE; + unsigned int packer_send_quads : SC_DEBUG_11_packer_send_quads_SIZE; + unsigned int iterator_input_fz : SC_DEBUG_11_iterator_input_fz_SIZE; + unsigned int pkr_fetch_new_prim_data : SC_DEBUG_11_pkr_fetch_new_prim_data_SIZE; + unsigned int ez_prim_data_ready : SC_DEBUG_11_ez_prim_data_ready_SIZE; + unsigned int pkr_fetch_new_sample_data : SC_DEBUG_11_pkr_fetch_new_sample_data_SIZE; + unsigned int ez_sample_data_ready : SC_DEBUG_11_ez_sample_data_ready_SIZE; + } sc_debug_11_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_11_t f; +} sc_debug_11_u; + + +/* + * SC_DEBUG_12 struct + */ + +#define SC_DEBUG_12_SQ_iterator_free_buff_SIZE 1 +#define SC_DEBUG_12_event_id_SIZE 5 +#define SC_DEBUG_12_event_flag_SIZE 1 +#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE 1 +#define SC_DEBUG_12_itercmdfifo_full_SIZE 1 +#define SC_DEBUG_12_itercmdfifo_empty_SIZE 1 +#define SC_DEBUG_12_iter_ds_one_clk_command_SIZE 1 +#define SC_DEBUG_12_iter_ds_end_of_prim0_SIZE 1 +#define SC_DEBUG_12_iter_ds_end_of_vector_SIZE 1 +#define SC_DEBUG_12_iter_qdhit0_SIZE 1 +#define SC_DEBUG_12_bc_use_centers_reg_SIZE 1 +#define SC_DEBUG_12_bc_output_xy_reg_SIZE 1 +#define SC_DEBUG_12_iter_phase_out_SIZE 2 +#define SC_DEBUG_12_iter_phase_reg_SIZE 2 +#define SC_DEBUG_12_iterator_SP_valid_SIZE 1 +#define SC_DEBUG_12_eopv_reg_SIZE 1 +#define SC_DEBUG_12_one_clk_cmd_reg_SIZE 1 +#define SC_DEBUG_12_iter_dx_end_of_prim_SIZE 1 +#define SC_DEBUG_12_trigger_SIZE 1 + +#define SC_DEBUG_12_SQ_iterator_free_buff_SHIFT 0 +#define SC_DEBUG_12_event_id_SHIFT 1 +#define SC_DEBUG_12_event_flag_SHIFT 6 +#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT 7 +#define SC_DEBUG_12_itercmdfifo_full_SHIFT 8 +#define SC_DEBUG_12_itercmdfifo_empty_SHIFT 9 +#define SC_DEBUG_12_iter_ds_one_clk_command_SHIFT 10 +#define SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT 11 +#define SC_DEBUG_12_iter_ds_end_of_vector_SHIFT 12 +#define SC_DEBUG_12_iter_qdhit0_SHIFT 13 +#define SC_DEBUG_12_bc_use_centers_reg_SHIFT 14 +#define SC_DEBUG_12_bc_output_xy_reg_SHIFT 15 +#define SC_DEBUG_12_iter_phase_out_SHIFT 16 +#define SC_DEBUG_12_iter_phase_reg_SHIFT 18 +#define SC_DEBUG_12_iterator_SP_valid_SHIFT 20 +#define SC_DEBUG_12_eopv_reg_SHIFT 21 +#define SC_DEBUG_12_one_clk_cmd_reg_SHIFT 22 +#define SC_DEBUG_12_iter_dx_end_of_prim_SHIFT 23 +#define SC_DEBUG_12_trigger_SHIFT 31 + +#define SC_DEBUG_12_SQ_iterator_free_buff_MASK 0x00000001 +#define SC_DEBUG_12_event_id_MASK 0x0000003e +#define SC_DEBUG_12_event_flag_MASK 0x00000040 +#define SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK 0x00000080 +#define SC_DEBUG_12_itercmdfifo_full_MASK 0x00000100 +#define SC_DEBUG_12_itercmdfifo_empty_MASK 0x00000200 +#define SC_DEBUG_12_iter_ds_one_clk_command_MASK 0x00000400 +#define SC_DEBUG_12_iter_ds_end_of_prim0_MASK 0x00000800 +#define SC_DEBUG_12_iter_ds_end_of_vector_MASK 0x00001000 +#define SC_DEBUG_12_iter_qdhit0_MASK 0x00002000 +#define SC_DEBUG_12_bc_use_centers_reg_MASK 0x00004000 +#define SC_DEBUG_12_bc_output_xy_reg_MASK 0x00008000 +#define SC_DEBUG_12_iter_phase_out_MASK 0x00030000 +#define SC_DEBUG_12_iter_phase_reg_MASK 0x000c0000 +#define SC_DEBUG_12_iterator_SP_valid_MASK 0x00100000 +#define SC_DEBUG_12_eopv_reg_MASK 0x00200000 +#define SC_DEBUG_12_one_clk_cmd_reg_MASK 0x00400000 +#define SC_DEBUG_12_iter_dx_end_of_prim_MASK 0x00800000 +#define SC_DEBUG_12_trigger_MASK 0x80000000 + +#define SC_DEBUG_12_MASK \ + (SC_DEBUG_12_SQ_iterator_free_buff_MASK | \ + SC_DEBUG_12_event_id_MASK | \ + SC_DEBUG_12_event_flag_MASK | \ + SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK | \ + SC_DEBUG_12_itercmdfifo_full_MASK | \ + SC_DEBUG_12_itercmdfifo_empty_MASK | \ + SC_DEBUG_12_iter_ds_one_clk_command_MASK | \ + SC_DEBUG_12_iter_ds_end_of_prim0_MASK | \ + SC_DEBUG_12_iter_ds_end_of_vector_MASK | \ + SC_DEBUG_12_iter_qdhit0_MASK | \ + SC_DEBUG_12_bc_use_centers_reg_MASK | \ + SC_DEBUG_12_bc_output_xy_reg_MASK | \ + SC_DEBUG_12_iter_phase_out_MASK | \ + SC_DEBUG_12_iter_phase_reg_MASK | \ + SC_DEBUG_12_iterator_SP_valid_MASK | \ + SC_DEBUG_12_eopv_reg_MASK | \ + SC_DEBUG_12_one_clk_cmd_reg_MASK | \ + SC_DEBUG_12_iter_dx_end_of_prim_MASK | \ + SC_DEBUG_12_trigger_MASK) + +#define SC_DEBUG_12(sq_iterator_free_buff, event_id, event_flag, itercmdfifo_busy_nc_dly, itercmdfifo_full, itercmdfifo_empty, iter_ds_one_clk_command, iter_ds_end_of_prim0, iter_ds_end_of_vector, iter_qdhit0, bc_use_centers_reg, bc_output_xy_reg, iter_phase_out, iter_phase_reg, iterator_sp_valid, eopv_reg, one_clk_cmd_reg, iter_dx_end_of_prim, trigger) \ + ((sq_iterator_free_buff << SC_DEBUG_12_SQ_iterator_free_buff_SHIFT) | \ + (event_id << SC_DEBUG_12_event_id_SHIFT) | \ + (event_flag << SC_DEBUG_12_event_flag_SHIFT) | \ + (itercmdfifo_busy_nc_dly << SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT) | \ + (itercmdfifo_full << SC_DEBUG_12_itercmdfifo_full_SHIFT) | \ + (itercmdfifo_empty << SC_DEBUG_12_itercmdfifo_empty_SHIFT) | \ + (iter_ds_one_clk_command << SC_DEBUG_12_iter_ds_one_clk_command_SHIFT) | \ + (iter_ds_end_of_prim0 << SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT) | \ + (iter_ds_end_of_vector << SC_DEBUG_12_iter_ds_end_of_vector_SHIFT) | \ + (iter_qdhit0 << SC_DEBUG_12_iter_qdhit0_SHIFT) | \ + (bc_use_centers_reg << SC_DEBUG_12_bc_use_centers_reg_SHIFT) | \ + (bc_output_xy_reg << SC_DEBUG_12_bc_output_xy_reg_SHIFT) | \ + (iter_phase_out << SC_DEBUG_12_iter_phase_out_SHIFT) | \ + (iter_phase_reg << SC_DEBUG_12_iter_phase_reg_SHIFT) | \ + (iterator_sp_valid << SC_DEBUG_12_iterator_SP_valid_SHIFT) | \ + (eopv_reg << SC_DEBUG_12_eopv_reg_SHIFT) | \ + (one_clk_cmd_reg << SC_DEBUG_12_one_clk_cmd_reg_SHIFT) | \ + (iter_dx_end_of_prim << SC_DEBUG_12_iter_dx_end_of_prim_SHIFT) | \ + (trigger << SC_DEBUG_12_trigger_SHIFT)) + +#define SC_DEBUG_12_GET_SQ_iterator_free_buff(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_SQ_iterator_free_buff_MASK) >> SC_DEBUG_12_SQ_iterator_free_buff_SHIFT) +#define SC_DEBUG_12_GET_event_id(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_event_id_MASK) >> SC_DEBUG_12_event_id_SHIFT) +#define SC_DEBUG_12_GET_event_flag(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_event_flag_MASK) >> SC_DEBUG_12_event_flag_SHIFT) +#define SC_DEBUG_12_GET_itercmdfifo_busy_nc_dly(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK) >> SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT) +#define SC_DEBUG_12_GET_itercmdfifo_full(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_full_MASK) >> SC_DEBUG_12_itercmdfifo_full_SHIFT) +#define SC_DEBUG_12_GET_itercmdfifo_empty(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_itercmdfifo_empty_MASK) >> SC_DEBUG_12_itercmdfifo_empty_SHIFT) +#define SC_DEBUG_12_GET_iter_ds_one_clk_command(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_ds_one_clk_command_MASK) >> SC_DEBUG_12_iter_ds_one_clk_command_SHIFT) +#define SC_DEBUG_12_GET_iter_ds_end_of_prim0(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_ds_end_of_prim0_MASK) >> SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT) +#define SC_DEBUG_12_GET_iter_ds_end_of_vector(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_ds_end_of_vector_MASK) >> SC_DEBUG_12_iter_ds_end_of_vector_SHIFT) +#define SC_DEBUG_12_GET_iter_qdhit0(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_qdhit0_MASK) >> SC_DEBUG_12_iter_qdhit0_SHIFT) +#define SC_DEBUG_12_GET_bc_use_centers_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_bc_use_centers_reg_MASK) >> SC_DEBUG_12_bc_use_centers_reg_SHIFT) +#define SC_DEBUG_12_GET_bc_output_xy_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_bc_output_xy_reg_MASK) >> SC_DEBUG_12_bc_output_xy_reg_SHIFT) +#define SC_DEBUG_12_GET_iter_phase_out(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_phase_out_MASK) >> SC_DEBUG_12_iter_phase_out_SHIFT) +#define SC_DEBUG_12_GET_iter_phase_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_phase_reg_MASK) >> SC_DEBUG_12_iter_phase_reg_SHIFT) +#define SC_DEBUG_12_GET_iterator_SP_valid(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iterator_SP_valid_MASK) >> SC_DEBUG_12_iterator_SP_valid_SHIFT) +#define SC_DEBUG_12_GET_eopv_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_eopv_reg_MASK) >> SC_DEBUG_12_eopv_reg_SHIFT) +#define SC_DEBUG_12_GET_one_clk_cmd_reg(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_one_clk_cmd_reg_MASK) >> SC_DEBUG_12_one_clk_cmd_reg_SHIFT) +#define SC_DEBUG_12_GET_iter_dx_end_of_prim(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_iter_dx_end_of_prim_MASK) >> SC_DEBUG_12_iter_dx_end_of_prim_SHIFT) +#define SC_DEBUG_12_GET_trigger(sc_debug_12) \ + ((sc_debug_12 & SC_DEBUG_12_trigger_MASK) >> SC_DEBUG_12_trigger_SHIFT) + +#define SC_DEBUG_12_SET_SQ_iterator_free_buff(sc_debug_12_reg, sq_iterator_free_buff) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_SQ_iterator_free_buff_MASK) | (sq_iterator_free_buff << SC_DEBUG_12_SQ_iterator_free_buff_SHIFT) +#define SC_DEBUG_12_SET_event_id(sc_debug_12_reg, event_id) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_event_id_MASK) | (event_id << SC_DEBUG_12_event_id_SHIFT) +#define SC_DEBUG_12_SET_event_flag(sc_debug_12_reg, event_flag) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_event_flag_MASK) | (event_flag << SC_DEBUG_12_event_flag_SHIFT) +#define SC_DEBUG_12_SET_itercmdfifo_busy_nc_dly(sc_debug_12_reg, itercmdfifo_busy_nc_dly) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_busy_nc_dly_MASK) | (itercmdfifo_busy_nc_dly << SC_DEBUG_12_itercmdfifo_busy_nc_dly_SHIFT) +#define SC_DEBUG_12_SET_itercmdfifo_full(sc_debug_12_reg, itercmdfifo_full) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_full_MASK) | (itercmdfifo_full << SC_DEBUG_12_itercmdfifo_full_SHIFT) +#define SC_DEBUG_12_SET_itercmdfifo_empty(sc_debug_12_reg, itercmdfifo_empty) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_itercmdfifo_empty_MASK) | (itercmdfifo_empty << SC_DEBUG_12_itercmdfifo_empty_SHIFT) +#define SC_DEBUG_12_SET_iter_ds_one_clk_command(sc_debug_12_reg, iter_ds_one_clk_command) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_one_clk_command_MASK) | (iter_ds_one_clk_command << SC_DEBUG_12_iter_ds_one_clk_command_SHIFT) +#define SC_DEBUG_12_SET_iter_ds_end_of_prim0(sc_debug_12_reg, iter_ds_end_of_prim0) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_end_of_prim0_MASK) | (iter_ds_end_of_prim0 << SC_DEBUG_12_iter_ds_end_of_prim0_SHIFT) +#define SC_DEBUG_12_SET_iter_ds_end_of_vector(sc_debug_12_reg, iter_ds_end_of_vector) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_ds_end_of_vector_MASK) | (iter_ds_end_of_vector << SC_DEBUG_12_iter_ds_end_of_vector_SHIFT) +#define SC_DEBUG_12_SET_iter_qdhit0(sc_debug_12_reg, iter_qdhit0) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_qdhit0_MASK) | (iter_qdhit0 << SC_DEBUG_12_iter_qdhit0_SHIFT) +#define SC_DEBUG_12_SET_bc_use_centers_reg(sc_debug_12_reg, bc_use_centers_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_bc_use_centers_reg_MASK) | (bc_use_centers_reg << SC_DEBUG_12_bc_use_centers_reg_SHIFT) +#define SC_DEBUG_12_SET_bc_output_xy_reg(sc_debug_12_reg, bc_output_xy_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_bc_output_xy_reg_MASK) | (bc_output_xy_reg << SC_DEBUG_12_bc_output_xy_reg_SHIFT) +#define SC_DEBUG_12_SET_iter_phase_out(sc_debug_12_reg, iter_phase_out) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_phase_out_MASK) | (iter_phase_out << SC_DEBUG_12_iter_phase_out_SHIFT) +#define SC_DEBUG_12_SET_iter_phase_reg(sc_debug_12_reg, iter_phase_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_phase_reg_MASK) | (iter_phase_reg << SC_DEBUG_12_iter_phase_reg_SHIFT) +#define SC_DEBUG_12_SET_iterator_SP_valid(sc_debug_12_reg, iterator_sp_valid) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iterator_SP_valid_MASK) | (iterator_sp_valid << SC_DEBUG_12_iterator_SP_valid_SHIFT) +#define SC_DEBUG_12_SET_eopv_reg(sc_debug_12_reg, eopv_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_eopv_reg_MASK) | (eopv_reg << SC_DEBUG_12_eopv_reg_SHIFT) +#define SC_DEBUG_12_SET_one_clk_cmd_reg(sc_debug_12_reg, one_clk_cmd_reg) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_one_clk_cmd_reg_MASK) | (one_clk_cmd_reg << SC_DEBUG_12_one_clk_cmd_reg_SHIFT) +#define SC_DEBUG_12_SET_iter_dx_end_of_prim(sc_debug_12_reg, iter_dx_end_of_prim) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_iter_dx_end_of_prim_MASK) | (iter_dx_end_of_prim << SC_DEBUG_12_iter_dx_end_of_prim_SHIFT) +#define SC_DEBUG_12_SET_trigger(sc_debug_12_reg, trigger) \ + sc_debug_12_reg = (sc_debug_12_reg & ~SC_DEBUG_12_trigger_MASK) | (trigger << SC_DEBUG_12_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sc_debug_12_t { + unsigned int sq_iterator_free_buff : SC_DEBUG_12_SQ_iterator_free_buff_SIZE; + unsigned int event_id : SC_DEBUG_12_event_id_SIZE; + unsigned int event_flag : SC_DEBUG_12_event_flag_SIZE; + unsigned int itercmdfifo_busy_nc_dly : SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE; + unsigned int itercmdfifo_full : SC_DEBUG_12_itercmdfifo_full_SIZE; + unsigned int itercmdfifo_empty : SC_DEBUG_12_itercmdfifo_empty_SIZE; + unsigned int iter_ds_one_clk_command : SC_DEBUG_12_iter_ds_one_clk_command_SIZE; + unsigned int iter_ds_end_of_prim0 : SC_DEBUG_12_iter_ds_end_of_prim0_SIZE; + unsigned int iter_ds_end_of_vector : SC_DEBUG_12_iter_ds_end_of_vector_SIZE; + unsigned int iter_qdhit0 : SC_DEBUG_12_iter_qdhit0_SIZE; + unsigned int bc_use_centers_reg : SC_DEBUG_12_bc_use_centers_reg_SIZE; + unsigned int bc_output_xy_reg : SC_DEBUG_12_bc_output_xy_reg_SIZE; + unsigned int iter_phase_out : SC_DEBUG_12_iter_phase_out_SIZE; + unsigned int iter_phase_reg : SC_DEBUG_12_iter_phase_reg_SIZE; + unsigned int iterator_sp_valid : SC_DEBUG_12_iterator_SP_valid_SIZE; + unsigned int eopv_reg : SC_DEBUG_12_eopv_reg_SIZE; + unsigned int one_clk_cmd_reg : SC_DEBUG_12_one_clk_cmd_reg_SIZE; + unsigned int iter_dx_end_of_prim : SC_DEBUG_12_iter_dx_end_of_prim_SIZE; + unsigned int : 7; + unsigned int trigger : SC_DEBUG_12_trigger_SIZE; + } sc_debug_12_t; + +#else // !BIGENDIAN_OS + + typedef struct _sc_debug_12_t { + unsigned int trigger : SC_DEBUG_12_trigger_SIZE; + unsigned int : 7; + unsigned int iter_dx_end_of_prim : SC_DEBUG_12_iter_dx_end_of_prim_SIZE; + unsigned int one_clk_cmd_reg : SC_DEBUG_12_one_clk_cmd_reg_SIZE; + unsigned int eopv_reg : SC_DEBUG_12_eopv_reg_SIZE; + unsigned int iterator_sp_valid : SC_DEBUG_12_iterator_SP_valid_SIZE; + unsigned int iter_phase_reg : SC_DEBUG_12_iter_phase_reg_SIZE; + unsigned int iter_phase_out : SC_DEBUG_12_iter_phase_out_SIZE; + unsigned int bc_output_xy_reg : SC_DEBUG_12_bc_output_xy_reg_SIZE; + unsigned int bc_use_centers_reg : SC_DEBUG_12_bc_use_centers_reg_SIZE; + unsigned int iter_qdhit0 : SC_DEBUG_12_iter_qdhit0_SIZE; + unsigned int iter_ds_end_of_vector : SC_DEBUG_12_iter_ds_end_of_vector_SIZE; + unsigned int iter_ds_end_of_prim0 : SC_DEBUG_12_iter_ds_end_of_prim0_SIZE; + unsigned int iter_ds_one_clk_command : SC_DEBUG_12_iter_ds_one_clk_command_SIZE; + unsigned int itercmdfifo_empty : SC_DEBUG_12_itercmdfifo_empty_SIZE; + unsigned int itercmdfifo_full : SC_DEBUG_12_itercmdfifo_full_SIZE; + unsigned int itercmdfifo_busy_nc_dly : SC_DEBUG_12_itercmdfifo_busy_nc_dly_SIZE; + unsigned int event_flag : SC_DEBUG_12_event_flag_SIZE; + unsigned int event_id : SC_DEBUG_12_event_id_SIZE; + unsigned int sq_iterator_free_buff : SC_DEBUG_12_SQ_iterator_free_buff_SIZE; + } sc_debug_12_t; + +#endif + +typedef union { + unsigned int val : 32; + sc_debug_12_t f; +} sc_debug_12_u; + + +#endif + + +#if !defined (_VGT_FIDDLE_H) +#define _VGT_FIDDLE_H + +/***************************************************************************************************************** + * + * vgt_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + +/* + * VGT_OUT_PRIM_TYPE enum + */ + +#define VGT_OUT_POINT 0x00000000 +#define VGT_OUT_LINE 0x00000001 +#define VGT_OUT_TRI 0x00000002 +#define VGT_OUT_RECT_V0 0x00000003 +#define VGT_OUT_RECT_V1 0x00000004 +#define VGT_OUT_RECT_V2 0x00000005 +#define VGT_OUT_RECT_V3 0x00000006 +#define VGT_OUT_RESERVED 0x00000007 +#define VGT_TE_QUAD 0x00000008 +#define VGT_TE_PRIM_INDEX_LINE 0x00000009 +#define VGT_TE_PRIM_INDEX_TRI 0x0000000a +#define VGT_TE_PRIM_INDEX_QUAD 0x0000000b + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * GFX_COPY_STATE struct + */ + +#define GFX_COPY_STATE_SRC_STATE_ID_SIZE 1 + +#define GFX_COPY_STATE_SRC_STATE_ID_SHIFT 0 + +#define GFX_COPY_STATE_SRC_STATE_ID_MASK 0x00000001 + +#define GFX_COPY_STATE_MASK \ + (GFX_COPY_STATE_SRC_STATE_ID_MASK) + +#define GFX_COPY_STATE(src_state_id) \ + ((src_state_id << GFX_COPY_STATE_SRC_STATE_ID_SHIFT)) + +#define GFX_COPY_STATE_GET_SRC_STATE_ID(gfx_copy_state) \ + ((gfx_copy_state & GFX_COPY_STATE_SRC_STATE_ID_MASK) >> GFX_COPY_STATE_SRC_STATE_ID_SHIFT) + +#define GFX_COPY_STATE_SET_SRC_STATE_ID(gfx_copy_state_reg, src_state_id) \ + gfx_copy_state_reg = (gfx_copy_state_reg & ~GFX_COPY_STATE_SRC_STATE_ID_MASK) | (src_state_id << GFX_COPY_STATE_SRC_STATE_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _gfx_copy_state_t { + unsigned int src_state_id : GFX_COPY_STATE_SRC_STATE_ID_SIZE; + unsigned int : 31; + } gfx_copy_state_t; + +#else // !BIGENDIAN_OS + + typedef struct _gfx_copy_state_t { + unsigned int : 31; + unsigned int src_state_id : GFX_COPY_STATE_SRC_STATE_ID_SIZE; + } gfx_copy_state_t; + +#endif + +typedef union { + unsigned int val : 32; + gfx_copy_state_t f; +} gfx_copy_state_u; + + +/* + * VGT_DRAW_INITIATOR struct + */ + +#define VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE 6 +#define VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE 2 +#define VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SIZE 2 +#define VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE 1 +#define VGT_DRAW_INITIATOR_NOT_EOP_SIZE 1 +#define VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE 1 +#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE 1 +#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE 1 +#define VGT_DRAW_INITIATOR_NUM_INDICES_SIZE 16 + +#define VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT 0 +#define VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT 6 +#define VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT 8 +#define VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT 11 +#define VGT_DRAW_INITIATOR_NOT_EOP_SHIFT 12 +#define VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT 13 +#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT 14 +#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT 15 +#define VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT 16 + +#define VGT_DRAW_INITIATOR_PRIM_TYPE_MASK 0x0000003f +#define VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK 0x000000c0 +#define VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK 0x00000300 +#define VGT_DRAW_INITIATOR_INDEX_SIZE_MASK 0x00000800 +#define VGT_DRAW_INITIATOR_NOT_EOP_MASK 0x00001000 +#define VGT_DRAW_INITIATOR_SMALL_INDEX_MASK 0x00002000 +#define VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK 0x00004000 +#define VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK 0x00008000 +#define VGT_DRAW_INITIATOR_NUM_INDICES_MASK 0xffff0000 + +#define VGT_DRAW_INITIATOR_MASK \ + (VGT_DRAW_INITIATOR_PRIM_TYPE_MASK | \ + VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK | \ + VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK | \ + VGT_DRAW_INITIATOR_INDEX_SIZE_MASK | \ + VGT_DRAW_INITIATOR_NOT_EOP_MASK | \ + VGT_DRAW_INITIATOR_SMALL_INDEX_MASK | \ + VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK | \ + VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK | \ + VGT_DRAW_INITIATOR_NUM_INDICES_MASK) + +#define VGT_DRAW_INITIATOR(prim_type, source_select, faceness_cull_select, index_size, not_eop, small_index, pre_fetch_cull_enable, grp_cull_enable, num_indices) \ + ((prim_type << VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT) | \ + (source_select << VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT) | \ + (faceness_cull_select << VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT) | \ + (index_size << VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT) | \ + (not_eop << VGT_DRAW_INITIATOR_NOT_EOP_SHIFT) | \ + (small_index << VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT) | \ + (pre_fetch_cull_enable << VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT) | \ + (grp_cull_enable << VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT) | \ + (num_indices << VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT)) + +#define VGT_DRAW_INITIATOR_GET_PRIM_TYPE(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_PRIM_TYPE_MASK) >> VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT) +#define VGT_DRAW_INITIATOR_GET_SOURCE_SELECT(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK) >> VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT) +#define VGT_DRAW_INITIATOR_GET_FACENESS_CULL_SELECT(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK) >> VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT) +#define VGT_DRAW_INITIATOR_GET_INDEX_SIZE(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_INDEX_SIZE_MASK) >> VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT) +#define VGT_DRAW_INITIATOR_GET_NOT_EOP(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_NOT_EOP_MASK) >> VGT_DRAW_INITIATOR_NOT_EOP_SHIFT) +#define VGT_DRAW_INITIATOR_GET_SMALL_INDEX(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_SMALL_INDEX_MASK) >> VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT) +#define VGT_DRAW_INITIATOR_GET_PRE_FETCH_CULL_ENABLE(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK) >> VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT) +#define VGT_DRAW_INITIATOR_GET_GRP_CULL_ENABLE(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK) >> VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT) +#define VGT_DRAW_INITIATOR_GET_NUM_INDICES(vgt_draw_initiator) \ + ((vgt_draw_initiator & VGT_DRAW_INITIATOR_NUM_INDICES_MASK) >> VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT) + +#define VGT_DRAW_INITIATOR_SET_PRIM_TYPE(vgt_draw_initiator_reg, prim_type) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_PRIM_TYPE_MASK) | (prim_type << VGT_DRAW_INITIATOR_PRIM_TYPE_SHIFT) +#define VGT_DRAW_INITIATOR_SET_SOURCE_SELECT(vgt_draw_initiator_reg, source_select) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_SOURCE_SELECT_MASK) | (source_select << VGT_DRAW_INITIATOR_SOURCE_SELECT_SHIFT) +#define VGT_DRAW_INITIATOR_SET_FACENESS_CULL_SELECT(vgt_draw_initiator_reg, faceness_cull_select) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_MASK) | (faceness_cull_select << VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SHIFT) +#define VGT_DRAW_INITIATOR_SET_INDEX_SIZE(vgt_draw_initiator_reg, index_size) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_INDEX_SIZE_MASK) | (index_size << VGT_DRAW_INITIATOR_INDEX_SIZE_SHIFT) +#define VGT_DRAW_INITIATOR_SET_NOT_EOP(vgt_draw_initiator_reg, not_eop) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_NOT_EOP_MASK) | (not_eop << VGT_DRAW_INITIATOR_NOT_EOP_SHIFT) +#define VGT_DRAW_INITIATOR_SET_SMALL_INDEX(vgt_draw_initiator_reg, small_index) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_SMALL_INDEX_MASK) | (small_index << VGT_DRAW_INITIATOR_SMALL_INDEX_SHIFT) +#define VGT_DRAW_INITIATOR_SET_PRE_FETCH_CULL_ENABLE(vgt_draw_initiator_reg, pre_fetch_cull_enable) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_MASK) | (pre_fetch_cull_enable << VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SHIFT) +#define VGT_DRAW_INITIATOR_SET_GRP_CULL_ENABLE(vgt_draw_initiator_reg, grp_cull_enable) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_MASK) | (grp_cull_enable << VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SHIFT) +#define VGT_DRAW_INITIATOR_SET_NUM_INDICES(vgt_draw_initiator_reg, num_indices) \ + vgt_draw_initiator_reg = (vgt_draw_initiator_reg & ~VGT_DRAW_INITIATOR_NUM_INDICES_MASK) | (num_indices << VGT_DRAW_INITIATOR_NUM_INDICES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_draw_initiator_t { + unsigned int prim_type : VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE; + unsigned int source_select : VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE; + unsigned int faceness_cull_select : VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SIZE; + unsigned int : 1; + unsigned int index_size : VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE; + unsigned int not_eop : VGT_DRAW_INITIATOR_NOT_EOP_SIZE; + unsigned int small_index : VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE; + unsigned int pre_fetch_cull_enable : VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE; + unsigned int grp_cull_enable : VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE; + unsigned int num_indices : VGT_DRAW_INITIATOR_NUM_INDICES_SIZE; + } vgt_draw_initiator_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_draw_initiator_t { + unsigned int num_indices : VGT_DRAW_INITIATOR_NUM_INDICES_SIZE; + unsigned int grp_cull_enable : VGT_DRAW_INITIATOR_GRP_CULL_ENABLE_SIZE; + unsigned int pre_fetch_cull_enable : VGT_DRAW_INITIATOR_PRE_FETCH_CULL_ENABLE_SIZE; + unsigned int small_index : VGT_DRAW_INITIATOR_SMALL_INDEX_SIZE; + unsigned int not_eop : VGT_DRAW_INITIATOR_NOT_EOP_SIZE; + unsigned int index_size : VGT_DRAW_INITIATOR_INDEX_SIZE_SIZE; + unsigned int : 1; + unsigned int faceness_cull_select : VGT_DRAW_INITIATOR_FACENESS_CULL_SELECT_SIZE; + unsigned int source_select : VGT_DRAW_INITIATOR_SOURCE_SELECT_SIZE; + unsigned int prim_type : VGT_DRAW_INITIATOR_PRIM_TYPE_SIZE; + } vgt_draw_initiator_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_draw_initiator_t f; +} vgt_draw_initiator_u; + + +/* + * VGT_EVENT_INITIATOR struct + */ + +#define VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE 6 + +#define VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT 0 + +#define VGT_EVENT_INITIATOR_EVENT_TYPE_MASK 0x0000003f + +#define VGT_EVENT_INITIATOR_MASK \ + (VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) + +#define VGT_EVENT_INITIATOR(event_type) \ + ((event_type << VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT)) + +#define VGT_EVENT_INITIATOR_GET_EVENT_TYPE(vgt_event_initiator) \ + ((vgt_event_initiator & VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) >> VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT) + +#define VGT_EVENT_INITIATOR_SET_EVENT_TYPE(vgt_event_initiator_reg, event_type) \ + vgt_event_initiator_reg = (vgt_event_initiator_reg & ~VGT_EVENT_INITIATOR_EVENT_TYPE_MASK) | (event_type << VGT_EVENT_INITIATOR_EVENT_TYPE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_event_initiator_t { + unsigned int event_type : VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE; + unsigned int : 26; + } vgt_event_initiator_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_event_initiator_t { + unsigned int : 26; + unsigned int event_type : VGT_EVENT_INITIATOR_EVENT_TYPE_SIZE; + } vgt_event_initiator_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_event_initiator_t f; +} vgt_event_initiator_u; + + +/* + * VGT_DMA_BASE struct + */ + +#define VGT_DMA_BASE_BASE_ADDR_SIZE 32 + +#define VGT_DMA_BASE_BASE_ADDR_SHIFT 0 + +#define VGT_DMA_BASE_BASE_ADDR_MASK 0xffffffff + +#define VGT_DMA_BASE_MASK \ + (VGT_DMA_BASE_BASE_ADDR_MASK) + +#define VGT_DMA_BASE(base_addr) \ + ((base_addr << VGT_DMA_BASE_BASE_ADDR_SHIFT)) + +#define VGT_DMA_BASE_GET_BASE_ADDR(vgt_dma_base) \ + ((vgt_dma_base & VGT_DMA_BASE_BASE_ADDR_MASK) >> VGT_DMA_BASE_BASE_ADDR_SHIFT) + +#define VGT_DMA_BASE_SET_BASE_ADDR(vgt_dma_base_reg, base_addr) \ + vgt_dma_base_reg = (vgt_dma_base_reg & ~VGT_DMA_BASE_BASE_ADDR_MASK) | (base_addr << VGT_DMA_BASE_BASE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_dma_base_t { + unsigned int base_addr : VGT_DMA_BASE_BASE_ADDR_SIZE; + } vgt_dma_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_dma_base_t { + unsigned int base_addr : VGT_DMA_BASE_BASE_ADDR_SIZE; + } vgt_dma_base_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_dma_base_t f; +} vgt_dma_base_u; + + +/* + * VGT_DMA_SIZE struct + */ + +#define VGT_DMA_SIZE_NUM_WORDS_SIZE 24 +#define VGT_DMA_SIZE_SWAP_MODE_SIZE 2 + +#define VGT_DMA_SIZE_NUM_WORDS_SHIFT 0 +#define VGT_DMA_SIZE_SWAP_MODE_SHIFT 30 + +#define VGT_DMA_SIZE_NUM_WORDS_MASK 0x00ffffff +#define VGT_DMA_SIZE_SWAP_MODE_MASK 0xc0000000 + +#define VGT_DMA_SIZE_MASK \ + (VGT_DMA_SIZE_NUM_WORDS_MASK | \ + VGT_DMA_SIZE_SWAP_MODE_MASK) + +#define VGT_DMA_SIZE(num_words, swap_mode) \ + ((num_words << VGT_DMA_SIZE_NUM_WORDS_SHIFT) | \ + (swap_mode << VGT_DMA_SIZE_SWAP_MODE_SHIFT)) + +#define VGT_DMA_SIZE_GET_NUM_WORDS(vgt_dma_size) \ + ((vgt_dma_size & VGT_DMA_SIZE_NUM_WORDS_MASK) >> VGT_DMA_SIZE_NUM_WORDS_SHIFT) +#define VGT_DMA_SIZE_GET_SWAP_MODE(vgt_dma_size) \ + ((vgt_dma_size & VGT_DMA_SIZE_SWAP_MODE_MASK) >> VGT_DMA_SIZE_SWAP_MODE_SHIFT) + +#define VGT_DMA_SIZE_SET_NUM_WORDS(vgt_dma_size_reg, num_words) \ + vgt_dma_size_reg = (vgt_dma_size_reg & ~VGT_DMA_SIZE_NUM_WORDS_MASK) | (num_words << VGT_DMA_SIZE_NUM_WORDS_SHIFT) +#define VGT_DMA_SIZE_SET_SWAP_MODE(vgt_dma_size_reg, swap_mode) \ + vgt_dma_size_reg = (vgt_dma_size_reg & ~VGT_DMA_SIZE_SWAP_MODE_MASK) | (swap_mode << VGT_DMA_SIZE_SWAP_MODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_dma_size_t { + unsigned int num_words : VGT_DMA_SIZE_NUM_WORDS_SIZE; + unsigned int : 6; + unsigned int swap_mode : VGT_DMA_SIZE_SWAP_MODE_SIZE; + } vgt_dma_size_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_dma_size_t { + unsigned int swap_mode : VGT_DMA_SIZE_SWAP_MODE_SIZE; + unsigned int : 6; + unsigned int num_words : VGT_DMA_SIZE_NUM_WORDS_SIZE; + } vgt_dma_size_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_dma_size_t f; +} vgt_dma_size_u; + + +/* + * VGT_BIN_BASE struct + */ + +#define VGT_BIN_BASE_BIN_BASE_ADDR_SIZE 32 + +#define VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT 0 + +#define VGT_BIN_BASE_BIN_BASE_ADDR_MASK 0xffffffff + +#define VGT_BIN_BASE_MASK \ + (VGT_BIN_BASE_BIN_BASE_ADDR_MASK) + +#define VGT_BIN_BASE(bin_base_addr) \ + ((bin_base_addr << VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT)) + +#define VGT_BIN_BASE_GET_BIN_BASE_ADDR(vgt_bin_base) \ + ((vgt_bin_base & VGT_BIN_BASE_BIN_BASE_ADDR_MASK) >> VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT) + +#define VGT_BIN_BASE_SET_BIN_BASE_ADDR(vgt_bin_base_reg, bin_base_addr) \ + vgt_bin_base_reg = (vgt_bin_base_reg & ~VGT_BIN_BASE_BIN_BASE_ADDR_MASK) | (bin_base_addr << VGT_BIN_BASE_BIN_BASE_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_bin_base_t { + unsigned int bin_base_addr : VGT_BIN_BASE_BIN_BASE_ADDR_SIZE; + } vgt_bin_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_bin_base_t { + unsigned int bin_base_addr : VGT_BIN_BASE_BIN_BASE_ADDR_SIZE; + } vgt_bin_base_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_bin_base_t f; +} vgt_bin_base_u; + + +/* + * VGT_BIN_SIZE struct + */ + +#define VGT_BIN_SIZE_NUM_WORDS_SIZE 24 +#define VGT_BIN_SIZE_FACENESS_FETCH_SIZE 1 +#define VGT_BIN_SIZE_FACENESS_RESET_SIZE 1 + +#define VGT_BIN_SIZE_NUM_WORDS_SHIFT 0 +#define VGT_BIN_SIZE_FACENESS_FETCH_SHIFT 30 +#define VGT_BIN_SIZE_FACENESS_RESET_SHIFT 31 + +#define VGT_BIN_SIZE_NUM_WORDS_MASK 0x00ffffff +#define VGT_BIN_SIZE_FACENESS_FETCH_MASK 0x40000000 +#define VGT_BIN_SIZE_FACENESS_RESET_MASK 0x80000000 + +#define VGT_BIN_SIZE_MASK \ + (VGT_BIN_SIZE_NUM_WORDS_MASK | \ + VGT_BIN_SIZE_FACENESS_FETCH_MASK | \ + VGT_BIN_SIZE_FACENESS_RESET_MASK) + +#define VGT_BIN_SIZE(num_words, faceness_fetch, faceness_reset) \ + ((num_words << VGT_BIN_SIZE_NUM_WORDS_SHIFT) | \ + (faceness_fetch << VGT_BIN_SIZE_FACENESS_FETCH_SHIFT) | \ + (faceness_reset << VGT_BIN_SIZE_FACENESS_RESET_SHIFT)) + +#define VGT_BIN_SIZE_GET_NUM_WORDS(vgt_bin_size) \ + ((vgt_bin_size & VGT_BIN_SIZE_NUM_WORDS_MASK) >> VGT_BIN_SIZE_NUM_WORDS_SHIFT) +#define VGT_BIN_SIZE_GET_FACENESS_FETCH(vgt_bin_size) \ + ((vgt_bin_size & VGT_BIN_SIZE_FACENESS_FETCH_MASK) >> VGT_BIN_SIZE_FACENESS_FETCH_SHIFT) +#define VGT_BIN_SIZE_GET_FACENESS_RESET(vgt_bin_size) \ + ((vgt_bin_size & VGT_BIN_SIZE_FACENESS_RESET_MASK) >> VGT_BIN_SIZE_FACENESS_RESET_SHIFT) + +#define VGT_BIN_SIZE_SET_NUM_WORDS(vgt_bin_size_reg, num_words) \ + vgt_bin_size_reg = (vgt_bin_size_reg & ~VGT_BIN_SIZE_NUM_WORDS_MASK) | (num_words << VGT_BIN_SIZE_NUM_WORDS_SHIFT) +#define VGT_BIN_SIZE_SET_FACENESS_FETCH(vgt_bin_size_reg, faceness_fetch) \ + vgt_bin_size_reg = (vgt_bin_size_reg & ~VGT_BIN_SIZE_FACENESS_FETCH_MASK) | (faceness_fetch << VGT_BIN_SIZE_FACENESS_FETCH_SHIFT) +#define VGT_BIN_SIZE_SET_FACENESS_RESET(vgt_bin_size_reg, faceness_reset) \ + vgt_bin_size_reg = (vgt_bin_size_reg & ~VGT_BIN_SIZE_FACENESS_RESET_MASK) | (faceness_reset << VGT_BIN_SIZE_FACENESS_RESET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_bin_size_t { + unsigned int num_words : VGT_BIN_SIZE_NUM_WORDS_SIZE; + unsigned int : 6; + unsigned int faceness_fetch : VGT_BIN_SIZE_FACENESS_FETCH_SIZE; + unsigned int faceness_reset : VGT_BIN_SIZE_FACENESS_RESET_SIZE; + } vgt_bin_size_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_bin_size_t { + unsigned int faceness_reset : VGT_BIN_SIZE_FACENESS_RESET_SIZE; + unsigned int faceness_fetch : VGT_BIN_SIZE_FACENESS_FETCH_SIZE; + unsigned int : 6; + unsigned int num_words : VGT_BIN_SIZE_NUM_WORDS_SIZE; + } vgt_bin_size_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_bin_size_t f; +} vgt_bin_size_u; + + +/* + * VGT_CURRENT_BIN_ID_MIN struct + */ + +#define VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE 3 +#define VGT_CURRENT_BIN_ID_MIN_ROW_SIZE 3 +#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE 3 + +#define VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT 0 +#define VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT 3 +#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT 6 + +#define VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK 0x00000007 +#define VGT_CURRENT_BIN_ID_MIN_ROW_MASK 0x00000038 +#define VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK 0x000001c0 + +#define VGT_CURRENT_BIN_ID_MIN_MASK \ + (VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK | \ + VGT_CURRENT_BIN_ID_MIN_ROW_MASK | \ + VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) + +#define VGT_CURRENT_BIN_ID_MIN(column, row, guard_band) \ + ((column << VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT) | \ + (row << VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT) | \ + (guard_band << VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT)) + +#define VGT_CURRENT_BIN_ID_MIN_GET_COLUMN(vgt_current_bin_id_min) \ + ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK) >> VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT) +#define VGT_CURRENT_BIN_ID_MIN_GET_ROW(vgt_current_bin_id_min) \ + ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_ROW_MASK) >> VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT) +#define VGT_CURRENT_BIN_ID_MIN_GET_GUARD_BAND(vgt_current_bin_id_min) \ + ((vgt_current_bin_id_min & VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) >> VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT) + +#define VGT_CURRENT_BIN_ID_MIN_SET_COLUMN(vgt_current_bin_id_min_reg, column) \ + vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_COLUMN_MASK) | (column << VGT_CURRENT_BIN_ID_MIN_COLUMN_SHIFT) +#define VGT_CURRENT_BIN_ID_MIN_SET_ROW(vgt_current_bin_id_min_reg, row) \ + vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_ROW_MASK) | (row << VGT_CURRENT_BIN_ID_MIN_ROW_SHIFT) +#define VGT_CURRENT_BIN_ID_MIN_SET_GUARD_BAND(vgt_current_bin_id_min_reg, guard_band) \ + vgt_current_bin_id_min_reg = (vgt_current_bin_id_min_reg & ~VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK) | (guard_band << VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_current_bin_id_min_t { + unsigned int column : VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE; + unsigned int row : VGT_CURRENT_BIN_ID_MIN_ROW_SIZE; + unsigned int guard_band : VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE; + unsigned int : 23; + } vgt_current_bin_id_min_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_current_bin_id_min_t { + unsigned int : 23; + unsigned int guard_band : VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_SIZE; + unsigned int row : VGT_CURRENT_BIN_ID_MIN_ROW_SIZE; + unsigned int column : VGT_CURRENT_BIN_ID_MIN_COLUMN_SIZE; + } vgt_current_bin_id_min_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_current_bin_id_min_t f; +} vgt_current_bin_id_min_u; + + +/* + * VGT_CURRENT_BIN_ID_MAX struct + */ + +#define VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE 3 +#define VGT_CURRENT_BIN_ID_MAX_ROW_SIZE 3 +#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE 3 + +#define VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT 0 +#define VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT 3 +#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT 6 + +#define VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK 0x00000007 +#define VGT_CURRENT_BIN_ID_MAX_ROW_MASK 0x00000038 +#define VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK 0x000001c0 + +#define VGT_CURRENT_BIN_ID_MAX_MASK \ + (VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK | \ + VGT_CURRENT_BIN_ID_MAX_ROW_MASK | \ + VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) + +#define VGT_CURRENT_BIN_ID_MAX(column, row, guard_band) \ + ((column << VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT) | \ + (row << VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT) | \ + (guard_band << VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT)) + +#define VGT_CURRENT_BIN_ID_MAX_GET_COLUMN(vgt_current_bin_id_max) \ + ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK) >> VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT) +#define VGT_CURRENT_BIN_ID_MAX_GET_ROW(vgt_current_bin_id_max) \ + ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_ROW_MASK) >> VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT) +#define VGT_CURRENT_BIN_ID_MAX_GET_GUARD_BAND(vgt_current_bin_id_max) \ + ((vgt_current_bin_id_max & VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) >> VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT) + +#define VGT_CURRENT_BIN_ID_MAX_SET_COLUMN(vgt_current_bin_id_max_reg, column) \ + vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_COLUMN_MASK) | (column << VGT_CURRENT_BIN_ID_MAX_COLUMN_SHIFT) +#define VGT_CURRENT_BIN_ID_MAX_SET_ROW(vgt_current_bin_id_max_reg, row) \ + vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_ROW_MASK) | (row << VGT_CURRENT_BIN_ID_MAX_ROW_SHIFT) +#define VGT_CURRENT_BIN_ID_MAX_SET_GUARD_BAND(vgt_current_bin_id_max_reg, guard_band) \ + vgt_current_bin_id_max_reg = (vgt_current_bin_id_max_reg & ~VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK) | (guard_band << VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_current_bin_id_max_t { + unsigned int column : VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE; + unsigned int row : VGT_CURRENT_BIN_ID_MAX_ROW_SIZE; + unsigned int guard_band : VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE; + unsigned int : 23; + } vgt_current_bin_id_max_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_current_bin_id_max_t { + unsigned int : 23; + unsigned int guard_band : VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_SIZE; + unsigned int row : VGT_CURRENT_BIN_ID_MAX_ROW_SIZE; + unsigned int column : VGT_CURRENT_BIN_ID_MAX_COLUMN_SIZE; + } vgt_current_bin_id_max_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_current_bin_id_max_t f; +} vgt_current_bin_id_max_u; + + +/* + * VGT_IMMED_DATA struct + */ + +#define VGT_IMMED_DATA_DATA_SIZE 32 + +#define VGT_IMMED_DATA_DATA_SHIFT 0 + +#define VGT_IMMED_DATA_DATA_MASK 0xffffffff + +#define VGT_IMMED_DATA_MASK \ + (VGT_IMMED_DATA_DATA_MASK) + +#define VGT_IMMED_DATA(data) \ + ((data << VGT_IMMED_DATA_DATA_SHIFT)) + +#define VGT_IMMED_DATA_GET_DATA(vgt_immed_data) \ + ((vgt_immed_data & VGT_IMMED_DATA_DATA_MASK) >> VGT_IMMED_DATA_DATA_SHIFT) + +#define VGT_IMMED_DATA_SET_DATA(vgt_immed_data_reg, data) \ + vgt_immed_data_reg = (vgt_immed_data_reg & ~VGT_IMMED_DATA_DATA_MASK) | (data << VGT_IMMED_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_immed_data_t { + unsigned int data : VGT_IMMED_DATA_DATA_SIZE; + } vgt_immed_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_immed_data_t { + unsigned int data : VGT_IMMED_DATA_DATA_SIZE; + } vgt_immed_data_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_immed_data_t f; +} vgt_immed_data_u; + + +/* + * VGT_MAX_VTX_INDX struct + */ + +#define VGT_MAX_VTX_INDX_MAX_INDX_SIZE 24 + +#define VGT_MAX_VTX_INDX_MAX_INDX_SHIFT 0 + +#define VGT_MAX_VTX_INDX_MAX_INDX_MASK 0x00ffffff + +#define VGT_MAX_VTX_INDX_MASK \ + (VGT_MAX_VTX_INDX_MAX_INDX_MASK) + +#define VGT_MAX_VTX_INDX(max_indx) \ + ((max_indx << VGT_MAX_VTX_INDX_MAX_INDX_SHIFT)) + +#define VGT_MAX_VTX_INDX_GET_MAX_INDX(vgt_max_vtx_indx) \ + ((vgt_max_vtx_indx & VGT_MAX_VTX_INDX_MAX_INDX_MASK) >> VGT_MAX_VTX_INDX_MAX_INDX_SHIFT) + +#define VGT_MAX_VTX_INDX_SET_MAX_INDX(vgt_max_vtx_indx_reg, max_indx) \ + vgt_max_vtx_indx_reg = (vgt_max_vtx_indx_reg & ~VGT_MAX_VTX_INDX_MAX_INDX_MASK) | (max_indx << VGT_MAX_VTX_INDX_MAX_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_max_vtx_indx_t { + unsigned int max_indx : VGT_MAX_VTX_INDX_MAX_INDX_SIZE; + unsigned int : 8; + } vgt_max_vtx_indx_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_max_vtx_indx_t { + unsigned int : 8; + unsigned int max_indx : VGT_MAX_VTX_INDX_MAX_INDX_SIZE; + } vgt_max_vtx_indx_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_max_vtx_indx_t f; +} vgt_max_vtx_indx_u; + + +/* + * VGT_MIN_VTX_INDX struct + */ + +#define VGT_MIN_VTX_INDX_MIN_INDX_SIZE 24 + +#define VGT_MIN_VTX_INDX_MIN_INDX_SHIFT 0 + +#define VGT_MIN_VTX_INDX_MIN_INDX_MASK 0x00ffffff + +#define VGT_MIN_VTX_INDX_MASK \ + (VGT_MIN_VTX_INDX_MIN_INDX_MASK) + +#define VGT_MIN_VTX_INDX(min_indx) \ + ((min_indx << VGT_MIN_VTX_INDX_MIN_INDX_SHIFT)) + +#define VGT_MIN_VTX_INDX_GET_MIN_INDX(vgt_min_vtx_indx) \ + ((vgt_min_vtx_indx & VGT_MIN_VTX_INDX_MIN_INDX_MASK) >> VGT_MIN_VTX_INDX_MIN_INDX_SHIFT) + +#define VGT_MIN_VTX_INDX_SET_MIN_INDX(vgt_min_vtx_indx_reg, min_indx) \ + vgt_min_vtx_indx_reg = (vgt_min_vtx_indx_reg & ~VGT_MIN_VTX_INDX_MIN_INDX_MASK) | (min_indx << VGT_MIN_VTX_INDX_MIN_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_min_vtx_indx_t { + unsigned int min_indx : VGT_MIN_VTX_INDX_MIN_INDX_SIZE; + unsigned int : 8; + } vgt_min_vtx_indx_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_min_vtx_indx_t { + unsigned int : 8; + unsigned int min_indx : VGT_MIN_VTX_INDX_MIN_INDX_SIZE; + } vgt_min_vtx_indx_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_min_vtx_indx_t f; +} vgt_min_vtx_indx_u; + + +/* + * VGT_INDX_OFFSET struct + */ + +#define VGT_INDX_OFFSET_INDX_OFFSET_SIZE 24 + +#define VGT_INDX_OFFSET_INDX_OFFSET_SHIFT 0 + +#define VGT_INDX_OFFSET_INDX_OFFSET_MASK 0x00ffffff + +#define VGT_INDX_OFFSET_MASK \ + (VGT_INDX_OFFSET_INDX_OFFSET_MASK) + +#define VGT_INDX_OFFSET(indx_offset) \ + ((indx_offset << VGT_INDX_OFFSET_INDX_OFFSET_SHIFT)) + +#define VGT_INDX_OFFSET_GET_INDX_OFFSET(vgt_indx_offset) \ + ((vgt_indx_offset & VGT_INDX_OFFSET_INDX_OFFSET_MASK) >> VGT_INDX_OFFSET_INDX_OFFSET_SHIFT) + +#define VGT_INDX_OFFSET_SET_INDX_OFFSET(vgt_indx_offset_reg, indx_offset) \ + vgt_indx_offset_reg = (vgt_indx_offset_reg & ~VGT_INDX_OFFSET_INDX_OFFSET_MASK) | (indx_offset << VGT_INDX_OFFSET_INDX_OFFSET_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_indx_offset_t { + unsigned int indx_offset : VGT_INDX_OFFSET_INDX_OFFSET_SIZE; + unsigned int : 8; + } vgt_indx_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_indx_offset_t { + unsigned int : 8; + unsigned int indx_offset : VGT_INDX_OFFSET_INDX_OFFSET_SIZE; + } vgt_indx_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_indx_offset_t f; +} vgt_indx_offset_u; + + +/* + * VGT_VERTEX_REUSE_BLOCK_CNTL struct + */ + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE 3 + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT 0 + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK 0x00000007 + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_MASK \ + (VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) + +#define VGT_VERTEX_REUSE_BLOCK_CNTL(vtx_reuse_depth) \ + ((vtx_reuse_depth << VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT)) + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_GET_VTX_REUSE_DEPTH(vgt_vertex_reuse_block_cntl) \ + ((vgt_vertex_reuse_block_cntl & VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) >> VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT) + +#define VGT_VERTEX_REUSE_BLOCK_CNTL_SET_VTX_REUSE_DEPTH(vgt_vertex_reuse_block_cntl_reg, vtx_reuse_depth) \ + vgt_vertex_reuse_block_cntl_reg = (vgt_vertex_reuse_block_cntl_reg & ~VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_MASK) | (vtx_reuse_depth << VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_vertex_reuse_block_cntl_t { + unsigned int vtx_reuse_depth : VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE; + unsigned int : 29; + } vgt_vertex_reuse_block_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_vertex_reuse_block_cntl_t { + unsigned int : 29; + unsigned int vtx_reuse_depth : VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH_SIZE; + } vgt_vertex_reuse_block_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_vertex_reuse_block_cntl_t f; +} vgt_vertex_reuse_block_cntl_u; + + +/* + * VGT_OUT_DEALLOC_CNTL struct + */ + +#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE 2 + +#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT 0 + +#define VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK 0x00000003 + +#define VGT_OUT_DEALLOC_CNTL_MASK \ + (VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) + +#define VGT_OUT_DEALLOC_CNTL(dealloc_dist) \ + ((dealloc_dist << VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT)) + +#define VGT_OUT_DEALLOC_CNTL_GET_DEALLOC_DIST(vgt_out_dealloc_cntl) \ + ((vgt_out_dealloc_cntl & VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) >> VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT) + +#define VGT_OUT_DEALLOC_CNTL_SET_DEALLOC_DIST(vgt_out_dealloc_cntl_reg, dealloc_dist) \ + vgt_out_dealloc_cntl_reg = (vgt_out_dealloc_cntl_reg & ~VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_MASK) | (dealloc_dist << VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_out_dealloc_cntl_t { + unsigned int dealloc_dist : VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE; + unsigned int : 30; + } vgt_out_dealloc_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_out_dealloc_cntl_t { + unsigned int : 30; + unsigned int dealloc_dist : VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST_SIZE; + } vgt_out_dealloc_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_out_dealloc_cntl_t f; +} vgt_out_dealloc_cntl_u; + + +/* + * VGT_MULTI_PRIM_IB_RESET_INDX struct + */ + +#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE 24 + +#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT 0 + +#define VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK 0x00ffffff + +#define VGT_MULTI_PRIM_IB_RESET_INDX_MASK \ + (VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) + +#define VGT_MULTI_PRIM_IB_RESET_INDX(reset_indx) \ + ((reset_indx << VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT)) + +#define VGT_MULTI_PRIM_IB_RESET_INDX_GET_RESET_INDX(vgt_multi_prim_ib_reset_indx) \ + ((vgt_multi_prim_ib_reset_indx & VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) >> VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT) + +#define VGT_MULTI_PRIM_IB_RESET_INDX_SET_RESET_INDX(vgt_multi_prim_ib_reset_indx_reg, reset_indx) \ + vgt_multi_prim_ib_reset_indx_reg = (vgt_multi_prim_ib_reset_indx_reg & ~VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_MASK) | (reset_indx << VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_multi_prim_ib_reset_indx_t { + unsigned int reset_indx : VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE; + unsigned int : 8; + } vgt_multi_prim_ib_reset_indx_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_multi_prim_ib_reset_indx_t { + unsigned int : 8; + unsigned int reset_indx : VGT_MULTI_PRIM_IB_RESET_INDX_RESET_INDX_SIZE; + } vgt_multi_prim_ib_reset_indx_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_multi_prim_ib_reset_indx_t f; +} vgt_multi_prim_ib_reset_indx_u; + + +/* + * VGT_ENHANCE struct + */ + +#define VGT_ENHANCE_MISC_SIZE 16 + +#define VGT_ENHANCE_MISC_SHIFT 0 + +#define VGT_ENHANCE_MISC_MASK 0x0000ffff + +#define VGT_ENHANCE_MASK \ + (VGT_ENHANCE_MISC_MASK) + +#define VGT_ENHANCE(misc) \ + ((misc << VGT_ENHANCE_MISC_SHIFT)) + +#define VGT_ENHANCE_GET_MISC(vgt_enhance) \ + ((vgt_enhance & VGT_ENHANCE_MISC_MASK) >> VGT_ENHANCE_MISC_SHIFT) + +#define VGT_ENHANCE_SET_MISC(vgt_enhance_reg, misc) \ + vgt_enhance_reg = (vgt_enhance_reg & ~VGT_ENHANCE_MISC_MASK) | (misc << VGT_ENHANCE_MISC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_enhance_t { + unsigned int misc : VGT_ENHANCE_MISC_SIZE; + unsigned int : 16; + } vgt_enhance_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_enhance_t { + unsigned int : 16; + unsigned int misc : VGT_ENHANCE_MISC_SIZE; + } vgt_enhance_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_enhance_t f; +} vgt_enhance_u; + + +/* + * VGT_VTX_VECT_EJECT_REG struct + */ + +#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE 5 + +#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT 0 + +#define VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK 0x0000001f + +#define VGT_VTX_VECT_EJECT_REG_MASK \ + (VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) + +#define VGT_VTX_VECT_EJECT_REG(prim_count) \ + ((prim_count << VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT)) + +#define VGT_VTX_VECT_EJECT_REG_GET_PRIM_COUNT(vgt_vtx_vect_eject_reg) \ + ((vgt_vtx_vect_eject_reg & VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) >> VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT) + +#define VGT_VTX_VECT_EJECT_REG_SET_PRIM_COUNT(vgt_vtx_vect_eject_reg_reg, prim_count) \ + vgt_vtx_vect_eject_reg_reg = (vgt_vtx_vect_eject_reg_reg & ~VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_MASK) | (prim_count << VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_vtx_vect_eject_reg_t { + unsigned int prim_count : VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE; + unsigned int : 27; + } vgt_vtx_vect_eject_reg_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_vtx_vect_eject_reg_t { + unsigned int : 27; + unsigned int prim_count : VGT_VTX_VECT_EJECT_REG_PRIM_COUNT_SIZE; + } vgt_vtx_vect_eject_reg_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_vtx_vect_eject_reg_t f; +} vgt_vtx_vect_eject_reg_u; + + +/* + * VGT_LAST_COPY_STATE struct + */ + +#define VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE 1 +#define VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE 1 + +#define VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT 0 +#define VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT 16 + +#define VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK 0x00000001 +#define VGT_LAST_COPY_STATE_DST_STATE_ID_MASK 0x00010000 + +#define VGT_LAST_COPY_STATE_MASK \ + (VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK | \ + VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) + +#define VGT_LAST_COPY_STATE(src_state_id, dst_state_id) \ + ((src_state_id << VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT) | \ + (dst_state_id << VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT)) + +#define VGT_LAST_COPY_STATE_GET_SRC_STATE_ID(vgt_last_copy_state) \ + ((vgt_last_copy_state & VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK) >> VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT) +#define VGT_LAST_COPY_STATE_GET_DST_STATE_ID(vgt_last_copy_state) \ + ((vgt_last_copy_state & VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) >> VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT) + +#define VGT_LAST_COPY_STATE_SET_SRC_STATE_ID(vgt_last_copy_state_reg, src_state_id) \ + vgt_last_copy_state_reg = (vgt_last_copy_state_reg & ~VGT_LAST_COPY_STATE_SRC_STATE_ID_MASK) | (src_state_id << VGT_LAST_COPY_STATE_SRC_STATE_ID_SHIFT) +#define VGT_LAST_COPY_STATE_SET_DST_STATE_ID(vgt_last_copy_state_reg, dst_state_id) \ + vgt_last_copy_state_reg = (vgt_last_copy_state_reg & ~VGT_LAST_COPY_STATE_DST_STATE_ID_MASK) | (dst_state_id << VGT_LAST_COPY_STATE_DST_STATE_ID_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_last_copy_state_t { + unsigned int src_state_id : VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE; + unsigned int : 15; + unsigned int dst_state_id : VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE; + unsigned int : 15; + } vgt_last_copy_state_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_last_copy_state_t { + unsigned int : 15; + unsigned int dst_state_id : VGT_LAST_COPY_STATE_DST_STATE_ID_SIZE; + unsigned int : 15; + unsigned int src_state_id : VGT_LAST_COPY_STATE_SRC_STATE_ID_SIZE; + } vgt_last_copy_state_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_last_copy_state_t f; +} vgt_last_copy_state_u; + + +/* + * VGT_DEBUG_CNTL struct + */ + +#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE 5 + +#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT 0 + +#define VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK 0x0000001f + +#define VGT_DEBUG_CNTL_MASK \ + (VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) + +#define VGT_DEBUG_CNTL(vgt_debug_indx) \ + ((vgt_debug_indx << VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT)) + +#define VGT_DEBUG_CNTL_GET_VGT_DEBUG_INDX(vgt_debug_cntl) \ + ((vgt_debug_cntl & VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) >> VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT) + +#define VGT_DEBUG_CNTL_SET_VGT_DEBUG_INDX(vgt_debug_cntl_reg, vgt_debug_indx) \ + vgt_debug_cntl_reg = (vgt_debug_cntl_reg & ~VGT_DEBUG_CNTL_VGT_DEBUG_INDX_MASK) | (vgt_debug_indx << VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_cntl_t { + unsigned int vgt_debug_indx : VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE; + unsigned int : 27; + } vgt_debug_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_cntl_t { + unsigned int : 27; + unsigned int vgt_debug_indx : VGT_DEBUG_CNTL_VGT_DEBUG_INDX_SIZE; + } vgt_debug_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_cntl_t f; +} vgt_debug_cntl_u; + + +/* + * VGT_DEBUG_DATA struct + */ + +#define VGT_DEBUG_DATA_DATA_SIZE 32 + +#define VGT_DEBUG_DATA_DATA_SHIFT 0 + +#define VGT_DEBUG_DATA_DATA_MASK 0xffffffff + +#define VGT_DEBUG_DATA_MASK \ + (VGT_DEBUG_DATA_DATA_MASK) + +#define VGT_DEBUG_DATA(data) \ + ((data << VGT_DEBUG_DATA_DATA_SHIFT)) + +#define VGT_DEBUG_DATA_GET_DATA(vgt_debug_data) \ + ((vgt_debug_data & VGT_DEBUG_DATA_DATA_MASK) >> VGT_DEBUG_DATA_DATA_SHIFT) + +#define VGT_DEBUG_DATA_SET_DATA(vgt_debug_data_reg, data) \ + vgt_debug_data_reg = (vgt_debug_data_reg & ~VGT_DEBUG_DATA_DATA_MASK) | (data << VGT_DEBUG_DATA_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_data_t { + unsigned int data : VGT_DEBUG_DATA_DATA_SIZE; + } vgt_debug_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_data_t { + unsigned int data : VGT_DEBUG_DATA_DATA_SIZE; + } vgt_debug_data_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_data_t f; +} vgt_debug_data_u; + + +/* + * VGT_CNTL_STATUS struct + */ + +#define VGT_CNTL_STATUS_VGT_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE 1 +#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE 1 + +#define VGT_CNTL_STATUS_VGT_BUSY_SHIFT 0 +#define VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT 1 +#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT 2 +#define VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT 3 +#define VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT 4 +#define VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT 5 +#define VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT 6 +#define VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT 7 +#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT 8 + +#define VGT_CNTL_STATUS_VGT_BUSY_MASK 0x00000001 +#define VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK 0x00000002 +#define VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK 0x00000004 +#define VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK 0x00000008 +#define VGT_CNTL_STATUS_VGT_VR_BUSY_MASK 0x00000010 +#define VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK 0x00000020 +#define VGT_CNTL_STATUS_VGT_PT_BUSY_MASK 0x00000040 +#define VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK 0x00000080 +#define VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK 0x00000100 + +#define VGT_CNTL_STATUS_MASK \ + (VGT_CNTL_STATUS_VGT_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_VR_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_PT_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK | \ + VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) + +#define VGT_CNTL_STATUS(vgt_busy, vgt_dma_busy, vgt_dma_req_busy, vgt_grp_busy, vgt_vr_busy, vgt_bin_busy, vgt_pt_busy, vgt_out_busy, vgt_out_indx_busy) \ + ((vgt_busy << VGT_CNTL_STATUS_VGT_BUSY_SHIFT) | \ + (vgt_dma_busy << VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT) | \ + (vgt_dma_req_busy << VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT) | \ + (vgt_grp_busy << VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT) | \ + (vgt_vr_busy << VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT) | \ + (vgt_bin_busy << VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT) | \ + (vgt_pt_busy << VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT) | \ + (vgt_out_busy << VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT) | \ + (vgt_out_indx_busy << VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT)) + +#define VGT_CNTL_STATUS_GET_VGT_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_DMA_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_DMA_REQ_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_GRP_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_VR_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_VR_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_BIN_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_PT_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_PT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_OUT_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_GET_VGT_OUT_INDX_BUSY(vgt_cntl_status) \ + ((vgt_cntl_status & VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) >> VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT) + +#define VGT_CNTL_STATUS_SET_VGT_BUSY(vgt_cntl_status_reg, vgt_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_BUSY_MASK) | (vgt_busy << VGT_CNTL_STATUS_VGT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_DMA_BUSY(vgt_cntl_status_reg, vgt_dma_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_DMA_BUSY_MASK) | (vgt_dma_busy << VGT_CNTL_STATUS_VGT_DMA_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_DMA_REQ_BUSY(vgt_cntl_status_reg, vgt_dma_req_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_MASK) | (vgt_dma_req_busy << VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_GRP_BUSY(vgt_cntl_status_reg, vgt_grp_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_GRP_BUSY_MASK) | (vgt_grp_busy << VGT_CNTL_STATUS_VGT_GRP_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_VR_BUSY(vgt_cntl_status_reg, vgt_vr_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_VR_BUSY_MASK) | (vgt_vr_busy << VGT_CNTL_STATUS_VGT_VR_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_BIN_BUSY(vgt_cntl_status_reg, vgt_bin_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_BIN_BUSY_MASK) | (vgt_bin_busy << VGT_CNTL_STATUS_VGT_BIN_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_PT_BUSY(vgt_cntl_status_reg, vgt_pt_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_PT_BUSY_MASK) | (vgt_pt_busy << VGT_CNTL_STATUS_VGT_PT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_OUT_BUSY(vgt_cntl_status_reg, vgt_out_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_OUT_BUSY_MASK) | (vgt_out_busy << VGT_CNTL_STATUS_VGT_OUT_BUSY_SHIFT) +#define VGT_CNTL_STATUS_SET_VGT_OUT_INDX_BUSY(vgt_cntl_status_reg, vgt_out_indx_busy) \ + vgt_cntl_status_reg = (vgt_cntl_status_reg & ~VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_MASK) | (vgt_out_indx_busy << VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_cntl_status_t { + unsigned int vgt_busy : VGT_CNTL_STATUS_VGT_BUSY_SIZE; + unsigned int vgt_dma_busy : VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE; + unsigned int vgt_dma_req_busy : VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE; + unsigned int vgt_grp_busy : VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE; + unsigned int vgt_vr_busy : VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE; + unsigned int vgt_bin_busy : VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE; + unsigned int vgt_pt_busy : VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE; + unsigned int vgt_out_busy : VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE; + unsigned int vgt_out_indx_busy : VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE; + unsigned int : 23; + } vgt_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_cntl_status_t { + unsigned int : 23; + unsigned int vgt_out_indx_busy : VGT_CNTL_STATUS_VGT_OUT_INDX_BUSY_SIZE; + unsigned int vgt_out_busy : VGT_CNTL_STATUS_VGT_OUT_BUSY_SIZE; + unsigned int vgt_pt_busy : VGT_CNTL_STATUS_VGT_PT_BUSY_SIZE; + unsigned int vgt_bin_busy : VGT_CNTL_STATUS_VGT_BIN_BUSY_SIZE; + unsigned int vgt_vr_busy : VGT_CNTL_STATUS_VGT_VR_BUSY_SIZE; + unsigned int vgt_grp_busy : VGT_CNTL_STATUS_VGT_GRP_BUSY_SIZE; + unsigned int vgt_dma_req_busy : VGT_CNTL_STATUS_VGT_DMA_REQ_BUSY_SIZE; + unsigned int vgt_dma_busy : VGT_CNTL_STATUS_VGT_DMA_BUSY_SIZE; + unsigned int vgt_busy : VGT_CNTL_STATUS_VGT_BUSY_SIZE; + } vgt_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_cntl_status_t f; +} vgt_cntl_status_u; + + +/* + * VGT_DEBUG_REG0 struct + */ + +#define VGT_DEBUG_REG0_te_grp_busy_SIZE 1 +#define VGT_DEBUG_REG0_pt_grp_busy_SIZE 1 +#define VGT_DEBUG_REG0_vr_grp_busy_SIZE 1 +#define VGT_DEBUG_REG0_dma_request_busy_SIZE 1 +#define VGT_DEBUG_REG0_out_busy_SIZE 1 +#define VGT_DEBUG_REG0_grp_backend_busy_SIZE 1 +#define VGT_DEBUG_REG0_grp_busy_SIZE 1 +#define VGT_DEBUG_REG0_dma_busy_SIZE 1 +#define VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE 1 +#define VGT_DEBUG_REG0_rbiu_busy_SIZE 1 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE 1 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE 1 +#define VGT_DEBUG_REG0_vgt_busy_extended_SIZE 1 +#define VGT_DEBUG_REG0_vgt_busy_SIZE 1 +#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE 1 +#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE 1 +#define VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE 1 + +#define VGT_DEBUG_REG0_te_grp_busy_SHIFT 0 +#define VGT_DEBUG_REG0_pt_grp_busy_SHIFT 1 +#define VGT_DEBUG_REG0_vr_grp_busy_SHIFT 2 +#define VGT_DEBUG_REG0_dma_request_busy_SHIFT 3 +#define VGT_DEBUG_REG0_out_busy_SHIFT 4 +#define VGT_DEBUG_REG0_grp_backend_busy_SHIFT 5 +#define VGT_DEBUG_REG0_grp_busy_SHIFT 6 +#define VGT_DEBUG_REG0_dma_busy_SHIFT 7 +#define VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT 8 +#define VGT_DEBUG_REG0_rbiu_busy_SHIFT 9 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT 10 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT 11 +#define VGT_DEBUG_REG0_vgt_busy_extended_SHIFT 12 +#define VGT_DEBUG_REG0_vgt_busy_SHIFT 13 +#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT 14 +#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT 15 +#define VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT 16 + +#define VGT_DEBUG_REG0_te_grp_busy_MASK 0x00000001 +#define VGT_DEBUG_REG0_pt_grp_busy_MASK 0x00000002 +#define VGT_DEBUG_REG0_vr_grp_busy_MASK 0x00000004 +#define VGT_DEBUG_REG0_dma_request_busy_MASK 0x00000008 +#define VGT_DEBUG_REG0_out_busy_MASK 0x00000010 +#define VGT_DEBUG_REG0_grp_backend_busy_MASK 0x00000020 +#define VGT_DEBUG_REG0_grp_busy_MASK 0x00000040 +#define VGT_DEBUG_REG0_dma_busy_MASK 0x00000080 +#define VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK 0x00000100 +#define VGT_DEBUG_REG0_rbiu_busy_MASK 0x00000200 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK 0x00000400 +#define VGT_DEBUG_REG0_vgt_no_dma_busy_MASK 0x00000800 +#define VGT_DEBUG_REG0_vgt_busy_extended_MASK 0x00001000 +#define VGT_DEBUG_REG0_vgt_busy_MASK 0x00002000 +#define VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK 0x00004000 +#define VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK 0x00008000 +#define VGT_DEBUG_REG0_VGT_RBBM_busy_MASK 0x00010000 + +#define VGT_DEBUG_REG0_MASK \ + (VGT_DEBUG_REG0_te_grp_busy_MASK | \ + VGT_DEBUG_REG0_pt_grp_busy_MASK | \ + VGT_DEBUG_REG0_vr_grp_busy_MASK | \ + VGT_DEBUG_REG0_dma_request_busy_MASK | \ + VGT_DEBUG_REG0_out_busy_MASK | \ + VGT_DEBUG_REG0_grp_backend_busy_MASK | \ + VGT_DEBUG_REG0_grp_busy_MASK | \ + VGT_DEBUG_REG0_dma_busy_MASK | \ + VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK | \ + VGT_DEBUG_REG0_rbiu_busy_MASK | \ + VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK | \ + VGT_DEBUG_REG0_vgt_no_dma_busy_MASK | \ + VGT_DEBUG_REG0_vgt_busy_extended_MASK | \ + VGT_DEBUG_REG0_vgt_busy_MASK | \ + VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK | \ + VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK | \ + VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) + +#define VGT_DEBUG_REG0(te_grp_busy, pt_grp_busy, vr_grp_busy, dma_request_busy, out_busy, grp_backend_busy, grp_busy, dma_busy, rbiu_dma_request_busy, rbiu_busy, vgt_no_dma_busy_extended, vgt_no_dma_busy, vgt_busy_extended, vgt_busy, rbbm_skid_fifo_busy_out, vgt_rbbm_no_dma_busy, vgt_rbbm_busy) \ + ((te_grp_busy << VGT_DEBUG_REG0_te_grp_busy_SHIFT) | \ + (pt_grp_busy << VGT_DEBUG_REG0_pt_grp_busy_SHIFT) | \ + (vr_grp_busy << VGT_DEBUG_REG0_vr_grp_busy_SHIFT) | \ + (dma_request_busy << VGT_DEBUG_REG0_dma_request_busy_SHIFT) | \ + (out_busy << VGT_DEBUG_REG0_out_busy_SHIFT) | \ + (grp_backend_busy << VGT_DEBUG_REG0_grp_backend_busy_SHIFT) | \ + (grp_busy << VGT_DEBUG_REG0_grp_busy_SHIFT) | \ + (dma_busy << VGT_DEBUG_REG0_dma_busy_SHIFT) | \ + (rbiu_dma_request_busy << VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT) | \ + (rbiu_busy << VGT_DEBUG_REG0_rbiu_busy_SHIFT) | \ + (vgt_no_dma_busy_extended << VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT) | \ + (vgt_no_dma_busy << VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT) | \ + (vgt_busy_extended << VGT_DEBUG_REG0_vgt_busy_extended_SHIFT) | \ + (vgt_busy << VGT_DEBUG_REG0_vgt_busy_SHIFT) | \ + (rbbm_skid_fifo_busy_out << VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT) | \ + (vgt_rbbm_no_dma_busy << VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT) | \ + (vgt_rbbm_busy << VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT)) + +#define VGT_DEBUG_REG0_GET_te_grp_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_te_grp_busy_MASK) >> VGT_DEBUG_REG0_te_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_pt_grp_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_pt_grp_busy_MASK) >> VGT_DEBUG_REG0_pt_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_vr_grp_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vr_grp_busy_MASK) >> VGT_DEBUG_REG0_vr_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_dma_request_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_dma_request_busy_MASK) >> VGT_DEBUG_REG0_dma_request_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_out_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_out_busy_MASK) >> VGT_DEBUG_REG0_out_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_grp_backend_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_grp_backend_busy_MASK) >> VGT_DEBUG_REG0_grp_backend_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_grp_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_grp_busy_MASK) >> VGT_DEBUG_REG0_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_dma_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_dma_busy_MASK) >> VGT_DEBUG_REG0_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_rbiu_dma_request_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK) >> VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_rbiu_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbiu_busy_MASK) >> VGT_DEBUG_REG0_rbiu_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_vgt_no_dma_busy_extended(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK) >> VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT) +#define VGT_DEBUG_REG0_GET_vgt_no_dma_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_no_dma_busy_MASK) >> VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_vgt_busy_extended(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_busy_extended_MASK) >> VGT_DEBUG_REG0_vgt_busy_extended_SHIFT) +#define VGT_DEBUG_REG0_GET_vgt_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_vgt_busy_MASK) >> VGT_DEBUG_REG0_vgt_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_rbbm_skid_fifo_busy_out(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK) >> VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT) +#define VGT_DEBUG_REG0_GET_VGT_RBBM_no_dma_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK) >> VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_GET_VGT_RBBM_busy(vgt_debug_reg0) \ + ((vgt_debug_reg0 & VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) >> VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT) + +#define VGT_DEBUG_REG0_SET_te_grp_busy(vgt_debug_reg0_reg, te_grp_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_te_grp_busy_MASK) | (te_grp_busy << VGT_DEBUG_REG0_te_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_pt_grp_busy(vgt_debug_reg0_reg, pt_grp_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_pt_grp_busy_MASK) | (pt_grp_busy << VGT_DEBUG_REG0_pt_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_vr_grp_busy(vgt_debug_reg0_reg, vr_grp_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vr_grp_busy_MASK) | (vr_grp_busy << VGT_DEBUG_REG0_vr_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_dma_request_busy(vgt_debug_reg0_reg, dma_request_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_dma_request_busy_MASK) | (dma_request_busy << VGT_DEBUG_REG0_dma_request_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_out_busy(vgt_debug_reg0_reg, out_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_out_busy_MASK) | (out_busy << VGT_DEBUG_REG0_out_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_grp_backend_busy(vgt_debug_reg0_reg, grp_backend_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_grp_backend_busy_MASK) | (grp_backend_busy << VGT_DEBUG_REG0_grp_backend_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_grp_busy(vgt_debug_reg0_reg, grp_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_grp_busy_MASK) | (grp_busy << VGT_DEBUG_REG0_grp_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_dma_busy(vgt_debug_reg0_reg, dma_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_dma_busy_MASK) | (dma_busy << VGT_DEBUG_REG0_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_rbiu_dma_request_busy(vgt_debug_reg0_reg, rbiu_dma_request_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbiu_dma_request_busy_MASK) | (rbiu_dma_request_busy << VGT_DEBUG_REG0_rbiu_dma_request_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_rbiu_busy(vgt_debug_reg0_reg, rbiu_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbiu_busy_MASK) | (rbiu_busy << VGT_DEBUG_REG0_rbiu_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_vgt_no_dma_busy_extended(vgt_debug_reg0_reg, vgt_no_dma_busy_extended) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_no_dma_busy_extended_MASK) | (vgt_no_dma_busy_extended << VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SHIFT) +#define VGT_DEBUG_REG0_SET_vgt_no_dma_busy(vgt_debug_reg0_reg, vgt_no_dma_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_no_dma_busy_MASK) | (vgt_no_dma_busy << VGT_DEBUG_REG0_vgt_no_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_vgt_busy_extended(vgt_debug_reg0_reg, vgt_busy_extended) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_busy_extended_MASK) | (vgt_busy_extended << VGT_DEBUG_REG0_vgt_busy_extended_SHIFT) +#define VGT_DEBUG_REG0_SET_vgt_busy(vgt_debug_reg0_reg, vgt_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_vgt_busy_MASK) | (vgt_busy << VGT_DEBUG_REG0_vgt_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_rbbm_skid_fifo_busy_out(vgt_debug_reg0_reg, rbbm_skid_fifo_busy_out) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_MASK) | (rbbm_skid_fifo_busy_out << VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SHIFT) +#define VGT_DEBUG_REG0_SET_VGT_RBBM_no_dma_busy(vgt_debug_reg0_reg, vgt_rbbm_no_dma_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_MASK) | (vgt_rbbm_no_dma_busy << VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SHIFT) +#define VGT_DEBUG_REG0_SET_VGT_RBBM_busy(vgt_debug_reg0_reg, vgt_rbbm_busy) \ + vgt_debug_reg0_reg = (vgt_debug_reg0_reg & ~VGT_DEBUG_REG0_VGT_RBBM_busy_MASK) | (vgt_rbbm_busy << VGT_DEBUG_REG0_VGT_RBBM_busy_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg0_t { + unsigned int te_grp_busy : VGT_DEBUG_REG0_te_grp_busy_SIZE; + unsigned int pt_grp_busy : VGT_DEBUG_REG0_pt_grp_busy_SIZE; + unsigned int vr_grp_busy : VGT_DEBUG_REG0_vr_grp_busy_SIZE; + unsigned int dma_request_busy : VGT_DEBUG_REG0_dma_request_busy_SIZE; + unsigned int out_busy : VGT_DEBUG_REG0_out_busy_SIZE; + unsigned int grp_backend_busy : VGT_DEBUG_REG0_grp_backend_busy_SIZE; + unsigned int grp_busy : VGT_DEBUG_REG0_grp_busy_SIZE; + unsigned int dma_busy : VGT_DEBUG_REG0_dma_busy_SIZE; + unsigned int rbiu_dma_request_busy : VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE; + unsigned int rbiu_busy : VGT_DEBUG_REG0_rbiu_busy_SIZE; + unsigned int vgt_no_dma_busy_extended : VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE; + unsigned int vgt_no_dma_busy : VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE; + unsigned int vgt_busy_extended : VGT_DEBUG_REG0_vgt_busy_extended_SIZE; + unsigned int vgt_busy : VGT_DEBUG_REG0_vgt_busy_SIZE; + unsigned int rbbm_skid_fifo_busy_out : VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE; + unsigned int vgt_rbbm_no_dma_busy : VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE; + unsigned int vgt_rbbm_busy : VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE; + unsigned int : 15; + } vgt_debug_reg0_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg0_t { + unsigned int : 15; + unsigned int vgt_rbbm_busy : VGT_DEBUG_REG0_VGT_RBBM_busy_SIZE; + unsigned int vgt_rbbm_no_dma_busy : VGT_DEBUG_REG0_VGT_RBBM_no_dma_busy_SIZE; + unsigned int rbbm_skid_fifo_busy_out : VGT_DEBUG_REG0_rbbm_skid_fifo_busy_out_SIZE; + unsigned int vgt_busy : VGT_DEBUG_REG0_vgt_busy_SIZE; + unsigned int vgt_busy_extended : VGT_DEBUG_REG0_vgt_busy_extended_SIZE; + unsigned int vgt_no_dma_busy : VGT_DEBUG_REG0_vgt_no_dma_busy_SIZE; + unsigned int vgt_no_dma_busy_extended : VGT_DEBUG_REG0_vgt_no_dma_busy_extended_SIZE; + unsigned int rbiu_busy : VGT_DEBUG_REG0_rbiu_busy_SIZE; + unsigned int rbiu_dma_request_busy : VGT_DEBUG_REG0_rbiu_dma_request_busy_SIZE; + unsigned int dma_busy : VGT_DEBUG_REG0_dma_busy_SIZE; + unsigned int grp_busy : VGT_DEBUG_REG0_grp_busy_SIZE; + unsigned int grp_backend_busy : VGT_DEBUG_REG0_grp_backend_busy_SIZE; + unsigned int out_busy : VGT_DEBUG_REG0_out_busy_SIZE; + unsigned int dma_request_busy : VGT_DEBUG_REG0_dma_request_busy_SIZE; + unsigned int vr_grp_busy : VGT_DEBUG_REG0_vr_grp_busy_SIZE; + unsigned int pt_grp_busy : VGT_DEBUG_REG0_pt_grp_busy_SIZE; + unsigned int te_grp_busy : VGT_DEBUG_REG0_te_grp_busy_SIZE; + } vgt_debug_reg0_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg0_t f; +} vgt_debug_reg0_u; + + +/* + * VGT_DEBUG_REG1 struct + */ + +#define VGT_DEBUG_REG1_out_te_data_read_SIZE 1 +#define VGT_DEBUG_REG1_te_out_data_valid_SIZE 1 +#define VGT_DEBUG_REG1_out_pt_prim_read_SIZE 1 +#define VGT_DEBUG_REG1_pt_out_prim_valid_SIZE 1 +#define VGT_DEBUG_REG1_out_pt_data_read_SIZE 1 +#define VGT_DEBUG_REG1_pt_out_indx_valid_SIZE 1 +#define VGT_DEBUG_REG1_out_vr_prim_read_SIZE 1 +#define VGT_DEBUG_REG1_vr_out_prim_valid_SIZE 1 +#define VGT_DEBUG_REG1_out_vr_indx_read_SIZE 1 +#define VGT_DEBUG_REG1_vr_out_indx_valid_SIZE 1 +#define VGT_DEBUG_REG1_te_grp_read_SIZE 1 +#define VGT_DEBUG_REG1_grp_te_valid_SIZE 1 +#define VGT_DEBUG_REG1_pt_grp_read_SIZE 1 +#define VGT_DEBUG_REG1_grp_pt_valid_SIZE 1 +#define VGT_DEBUG_REG1_vr_grp_read_SIZE 1 +#define VGT_DEBUG_REG1_grp_vr_valid_SIZE 1 +#define VGT_DEBUG_REG1_grp_dma_read_SIZE 1 +#define VGT_DEBUG_REG1_dma_grp_valid_SIZE 1 +#define VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE 1 +#define VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE 1 +#define VGT_DEBUG_REG1_MH_VGT_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_MH_send_SIZE 1 +#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE 1 +#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE 1 +#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE 1 +#define VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE 1 +#define VGT_DEBUG_REG1_VGT_SQ_send_SIZE 1 +#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE 1 + +#define VGT_DEBUG_REG1_out_te_data_read_SHIFT 0 +#define VGT_DEBUG_REG1_te_out_data_valid_SHIFT 1 +#define VGT_DEBUG_REG1_out_pt_prim_read_SHIFT 2 +#define VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT 3 +#define VGT_DEBUG_REG1_out_pt_data_read_SHIFT 4 +#define VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT 5 +#define VGT_DEBUG_REG1_out_vr_prim_read_SHIFT 6 +#define VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT 7 +#define VGT_DEBUG_REG1_out_vr_indx_read_SHIFT 8 +#define VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT 9 +#define VGT_DEBUG_REG1_te_grp_read_SHIFT 10 +#define VGT_DEBUG_REG1_grp_te_valid_SHIFT 11 +#define VGT_DEBUG_REG1_pt_grp_read_SHIFT 12 +#define VGT_DEBUG_REG1_grp_pt_valid_SHIFT 13 +#define VGT_DEBUG_REG1_vr_grp_read_SHIFT 14 +#define VGT_DEBUG_REG1_grp_vr_valid_SHIFT 15 +#define VGT_DEBUG_REG1_grp_dma_read_SHIFT 16 +#define VGT_DEBUG_REG1_dma_grp_valid_SHIFT 17 +#define VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT 18 +#define VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT 19 +#define VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT 20 +#define VGT_DEBUG_REG1_VGT_MH_send_SHIFT 21 +#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT 22 +#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT 23 +#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT 24 +#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT 25 +#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT 26 +#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT 27 +#define VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT 28 +#define VGT_DEBUG_REG1_VGT_SQ_send_SHIFT 29 +#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT 30 + +#define VGT_DEBUG_REG1_out_te_data_read_MASK 0x00000001 +#define VGT_DEBUG_REG1_te_out_data_valid_MASK 0x00000002 +#define VGT_DEBUG_REG1_out_pt_prim_read_MASK 0x00000004 +#define VGT_DEBUG_REG1_pt_out_prim_valid_MASK 0x00000008 +#define VGT_DEBUG_REG1_out_pt_data_read_MASK 0x00000010 +#define VGT_DEBUG_REG1_pt_out_indx_valid_MASK 0x00000020 +#define VGT_DEBUG_REG1_out_vr_prim_read_MASK 0x00000040 +#define VGT_DEBUG_REG1_vr_out_prim_valid_MASK 0x00000080 +#define VGT_DEBUG_REG1_out_vr_indx_read_MASK 0x00000100 +#define VGT_DEBUG_REG1_vr_out_indx_valid_MASK 0x00000200 +#define VGT_DEBUG_REG1_te_grp_read_MASK 0x00000400 +#define VGT_DEBUG_REG1_grp_te_valid_MASK 0x00000800 +#define VGT_DEBUG_REG1_pt_grp_read_MASK 0x00001000 +#define VGT_DEBUG_REG1_grp_pt_valid_MASK 0x00002000 +#define VGT_DEBUG_REG1_vr_grp_read_MASK 0x00004000 +#define VGT_DEBUG_REG1_grp_vr_valid_MASK 0x00008000 +#define VGT_DEBUG_REG1_grp_dma_read_MASK 0x00010000 +#define VGT_DEBUG_REG1_dma_grp_valid_MASK 0x00020000 +#define VGT_DEBUG_REG1_grp_rbiu_di_read_MASK 0x00040000 +#define VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK 0x00080000 +#define VGT_DEBUG_REG1_MH_VGT_rtr_MASK 0x00100000 +#define VGT_DEBUG_REG1_VGT_MH_send_MASK 0x00200000 +#define VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK 0x00400000 +#define VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK 0x00800000 +#define VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK 0x01000000 +#define VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK 0x02000000 +#define VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK 0x04000000 +#define VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK 0x08000000 +#define VGT_DEBUG_REG1_SQ_VGT_rtr_MASK 0x10000000 +#define VGT_DEBUG_REG1_VGT_SQ_send_MASK 0x20000000 +#define VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK 0x40000000 + +#define VGT_DEBUG_REG1_MASK \ + (VGT_DEBUG_REG1_out_te_data_read_MASK | \ + VGT_DEBUG_REG1_te_out_data_valid_MASK | \ + VGT_DEBUG_REG1_out_pt_prim_read_MASK | \ + VGT_DEBUG_REG1_pt_out_prim_valid_MASK | \ + VGT_DEBUG_REG1_out_pt_data_read_MASK | \ + VGT_DEBUG_REG1_pt_out_indx_valid_MASK | \ + VGT_DEBUG_REG1_out_vr_prim_read_MASK | \ + VGT_DEBUG_REG1_vr_out_prim_valid_MASK | \ + VGT_DEBUG_REG1_out_vr_indx_read_MASK | \ + VGT_DEBUG_REG1_vr_out_indx_valid_MASK | \ + VGT_DEBUG_REG1_te_grp_read_MASK | \ + VGT_DEBUG_REG1_grp_te_valid_MASK | \ + VGT_DEBUG_REG1_pt_grp_read_MASK | \ + VGT_DEBUG_REG1_grp_pt_valid_MASK | \ + VGT_DEBUG_REG1_vr_grp_read_MASK | \ + VGT_DEBUG_REG1_grp_vr_valid_MASK | \ + VGT_DEBUG_REG1_grp_dma_read_MASK | \ + VGT_DEBUG_REG1_dma_grp_valid_MASK | \ + VGT_DEBUG_REG1_grp_rbiu_di_read_MASK | \ + VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK | \ + VGT_DEBUG_REG1_MH_VGT_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_MH_send_MASK | \ + VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK | \ + VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK | \ + VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK | \ + VGT_DEBUG_REG1_SQ_VGT_rtr_MASK | \ + VGT_DEBUG_REG1_VGT_SQ_send_MASK | \ + VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) + +#define VGT_DEBUG_REG1(out_te_data_read, te_out_data_valid, out_pt_prim_read, pt_out_prim_valid, out_pt_data_read, pt_out_indx_valid, out_vr_prim_read, vr_out_prim_valid, out_vr_indx_read, vr_out_indx_valid, te_grp_read, grp_te_valid, pt_grp_read, grp_pt_valid, vr_grp_read, grp_vr_valid, grp_dma_read, dma_grp_valid, grp_rbiu_di_read, rbiu_grp_di_valid, mh_vgt_rtr, vgt_mh_send, pa_vgt_clip_s_rtr, vgt_pa_clip_s_send, pa_vgt_clip_p_rtr, vgt_pa_clip_p_send, pa_vgt_clip_v_rtr, vgt_pa_clip_v_send, sq_vgt_rtr, vgt_sq_send, mh_vgt_tag_7_q) \ + ((out_te_data_read << VGT_DEBUG_REG1_out_te_data_read_SHIFT) | \ + (te_out_data_valid << VGT_DEBUG_REG1_te_out_data_valid_SHIFT) | \ + (out_pt_prim_read << VGT_DEBUG_REG1_out_pt_prim_read_SHIFT) | \ + (pt_out_prim_valid << VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT) | \ + (out_pt_data_read << VGT_DEBUG_REG1_out_pt_data_read_SHIFT) | \ + (pt_out_indx_valid << VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT) | \ + (out_vr_prim_read << VGT_DEBUG_REG1_out_vr_prim_read_SHIFT) | \ + (vr_out_prim_valid << VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT) | \ + (out_vr_indx_read << VGT_DEBUG_REG1_out_vr_indx_read_SHIFT) | \ + (vr_out_indx_valid << VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT) | \ + (te_grp_read << VGT_DEBUG_REG1_te_grp_read_SHIFT) | \ + (grp_te_valid << VGT_DEBUG_REG1_grp_te_valid_SHIFT) | \ + (pt_grp_read << VGT_DEBUG_REG1_pt_grp_read_SHIFT) | \ + (grp_pt_valid << VGT_DEBUG_REG1_grp_pt_valid_SHIFT) | \ + (vr_grp_read << VGT_DEBUG_REG1_vr_grp_read_SHIFT) | \ + (grp_vr_valid << VGT_DEBUG_REG1_grp_vr_valid_SHIFT) | \ + (grp_dma_read << VGT_DEBUG_REG1_grp_dma_read_SHIFT) | \ + (dma_grp_valid << VGT_DEBUG_REG1_dma_grp_valid_SHIFT) | \ + (grp_rbiu_di_read << VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT) | \ + (rbiu_grp_di_valid << VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT) | \ + (mh_vgt_rtr << VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT) | \ + (vgt_mh_send << VGT_DEBUG_REG1_VGT_MH_send_SHIFT) | \ + (pa_vgt_clip_s_rtr << VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT) | \ + (vgt_pa_clip_s_send << VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT) | \ + (pa_vgt_clip_p_rtr << VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT) | \ + (vgt_pa_clip_p_send << VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT) | \ + (pa_vgt_clip_v_rtr << VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT) | \ + (vgt_pa_clip_v_send << VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT) | \ + (sq_vgt_rtr << VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT) | \ + (vgt_sq_send << VGT_DEBUG_REG1_VGT_SQ_send_SHIFT) | \ + (mh_vgt_tag_7_q << VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT)) + +#define VGT_DEBUG_REG1_GET_out_te_data_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_te_data_read_MASK) >> VGT_DEBUG_REG1_out_te_data_read_SHIFT) +#define VGT_DEBUG_REG1_GET_te_out_data_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_te_out_data_valid_MASK) >> VGT_DEBUG_REG1_te_out_data_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_out_pt_prim_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_pt_prim_read_MASK) >> VGT_DEBUG_REG1_out_pt_prim_read_SHIFT) +#define VGT_DEBUG_REG1_GET_pt_out_prim_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_out_prim_valid_MASK) >> VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_out_pt_data_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_pt_data_read_MASK) >> VGT_DEBUG_REG1_out_pt_data_read_SHIFT) +#define VGT_DEBUG_REG1_GET_pt_out_indx_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_out_indx_valid_MASK) >> VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_out_vr_prim_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_vr_prim_read_MASK) >> VGT_DEBUG_REG1_out_vr_prim_read_SHIFT) +#define VGT_DEBUG_REG1_GET_vr_out_prim_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_out_prim_valid_MASK) >> VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_out_vr_indx_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_out_vr_indx_read_MASK) >> VGT_DEBUG_REG1_out_vr_indx_read_SHIFT) +#define VGT_DEBUG_REG1_GET_vr_out_indx_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_out_indx_valid_MASK) >> VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_te_grp_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_te_grp_read_MASK) >> VGT_DEBUG_REG1_te_grp_read_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_te_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_te_valid_MASK) >> VGT_DEBUG_REG1_grp_te_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_pt_grp_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_pt_grp_read_MASK) >> VGT_DEBUG_REG1_pt_grp_read_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_pt_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_pt_valid_MASK) >> VGT_DEBUG_REG1_grp_pt_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_vr_grp_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_vr_grp_read_MASK) >> VGT_DEBUG_REG1_vr_grp_read_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_vr_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_vr_valid_MASK) >> VGT_DEBUG_REG1_grp_vr_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_dma_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_dma_read_MASK) >> VGT_DEBUG_REG1_grp_dma_read_SHIFT) +#define VGT_DEBUG_REG1_GET_dma_grp_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_dma_grp_valid_MASK) >> VGT_DEBUG_REG1_dma_grp_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_grp_rbiu_di_read(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_grp_rbiu_di_read_MASK) >> VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT) +#define VGT_DEBUG_REG1_GET_rbiu_grp_di_valid(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK) >> VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT) +#define VGT_DEBUG_REG1_GET_MH_VGT_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_MH_VGT_rtr_MASK) >> VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_MH_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_MH_send_MASK) >> VGT_DEBUG_REG1_VGT_MH_send_SHIFT) +#define VGT_DEBUG_REG1_GET_PA_VGT_clip_s_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_PA_clip_s_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT) +#define VGT_DEBUG_REG1_GET_PA_VGT_clip_p_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_PA_clip_p_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT) +#define VGT_DEBUG_REG1_GET_PA_VGT_clip_v_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK) >> VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_PA_clip_v_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK) >> VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT) +#define VGT_DEBUG_REG1_GET_SQ_VGT_rtr(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_SQ_VGT_rtr_MASK) >> VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT) +#define VGT_DEBUG_REG1_GET_VGT_SQ_send(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_VGT_SQ_send_MASK) >> VGT_DEBUG_REG1_VGT_SQ_send_SHIFT) +#define VGT_DEBUG_REG1_GET_mh_vgt_tag_7_q(vgt_debug_reg1) \ + ((vgt_debug_reg1 & VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) >> VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT) + +#define VGT_DEBUG_REG1_SET_out_te_data_read(vgt_debug_reg1_reg, out_te_data_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_te_data_read_MASK) | (out_te_data_read << VGT_DEBUG_REG1_out_te_data_read_SHIFT) +#define VGT_DEBUG_REG1_SET_te_out_data_valid(vgt_debug_reg1_reg, te_out_data_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_te_out_data_valid_MASK) | (te_out_data_valid << VGT_DEBUG_REG1_te_out_data_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_out_pt_prim_read(vgt_debug_reg1_reg, out_pt_prim_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_pt_prim_read_MASK) | (out_pt_prim_read << VGT_DEBUG_REG1_out_pt_prim_read_SHIFT) +#define VGT_DEBUG_REG1_SET_pt_out_prim_valid(vgt_debug_reg1_reg, pt_out_prim_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_out_prim_valid_MASK) | (pt_out_prim_valid << VGT_DEBUG_REG1_pt_out_prim_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_out_pt_data_read(vgt_debug_reg1_reg, out_pt_data_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_pt_data_read_MASK) | (out_pt_data_read << VGT_DEBUG_REG1_out_pt_data_read_SHIFT) +#define VGT_DEBUG_REG1_SET_pt_out_indx_valid(vgt_debug_reg1_reg, pt_out_indx_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_out_indx_valid_MASK) | (pt_out_indx_valid << VGT_DEBUG_REG1_pt_out_indx_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_out_vr_prim_read(vgt_debug_reg1_reg, out_vr_prim_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_vr_prim_read_MASK) | (out_vr_prim_read << VGT_DEBUG_REG1_out_vr_prim_read_SHIFT) +#define VGT_DEBUG_REG1_SET_vr_out_prim_valid(vgt_debug_reg1_reg, vr_out_prim_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_out_prim_valid_MASK) | (vr_out_prim_valid << VGT_DEBUG_REG1_vr_out_prim_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_out_vr_indx_read(vgt_debug_reg1_reg, out_vr_indx_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_out_vr_indx_read_MASK) | (out_vr_indx_read << VGT_DEBUG_REG1_out_vr_indx_read_SHIFT) +#define VGT_DEBUG_REG1_SET_vr_out_indx_valid(vgt_debug_reg1_reg, vr_out_indx_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_out_indx_valid_MASK) | (vr_out_indx_valid << VGT_DEBUG_REG1_vr_out_indx_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_te_grp_read(vgt_debug_reg1_reg, te_grp_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_te_grp_read_MASK) | (te_grp_read << VGT_DEBUG_REG1_te_grp_read_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_te_valid(vgt_debug_reg1_reg, grp_te_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_te_valid_MASK) | (grp_te_valid << VGT_DEBUG_REG1_grp_te_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_pt_grp_read(vgt_debug_reg1_reg, pt_grp_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_pt_grp_read_MASK) | (pt_grp_read << VGT_DEBUG_REG1_pt_grp_read_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_pt_valid(vgt_debug_reg1_reg, grp_pt_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_pt_valid_MASK) | (grp_pt_valid << VGT_DEBUG_REG1_grp_pt_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_vr_grp_read(vgt_debug_reg1_reg, vr_grp_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_vr_grp_read_MASK) | (vr_grp_read << VGT_DEBUG_REG1_vr_grp_read_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_vr_valid(vgt_debug_reg1_reg, grp_vr_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_vr_valid_MASK) | (grp_vr_valid << VGT_DEBUG_REG1_grp_vr_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_dma_read(vgt_debug_reg1_reg, grp_dma_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_dma_read_MASK) | (grp_dma_read << VGT_DEBUG_REG1_grp_dma_read_SHIFT) +#define VGT_DEBUG_REG1_SET_dma_grp_valid(vgt_debug_reg1_reg, dma_grp_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_dma_grp_valid_MASK) | (dma_grp_valid << VGT_DEBUG_REG1_dma_grp_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_grp_rbiu_di_read(vgt_debug_reg1_reg, grp_rbiu_di_read) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_grp_rbiu_di_read_MASK) | (grp_rbiu_di_read << VGT_DEBUG_REG1_grp_rbiu_di_read_SHIFT) +#define VGT_DEBUG_REG1_SET_rbiu_grp_di_valid(vgt_debug_reg1_reg, rbiu_grp_di_valid) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_rbiu_grp_di_valid_MASK) | (rbiu_grp_di_valid << VGT_DEBUG_REG1_rbiu_grp_di_valid_SHIFT) +#define VGT_DEBUG_REG1_SET_MH_VGT_rtr(vgt_debug_reg1_reg, mh_vgt_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_MH_VGT_rtr_MASK) | (mh_vgt_rtr << VGT_DEBUG_REG1_MH_VGT_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_MH_send(vgt_debug_reg1_reg, vgt_mh_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_MH_send_MASK) | (vgt_mh_send << VGT_DEBUG_REG1_VGT_MH_send_SHIFT) +#define VGT_DEBUG_REG1_SET_PA_VGT_clip_s_rtr(vgt_debug_reg1_reg, pa_vgt_clip_s_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_MASK) | (pa_vgt_clip_s_rtr << VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_PA_clip_s_send(vgt_debug_reg1_reg, vgt_pa_clip_s_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_s_send_MASK) | (vgt_pa_clip_s_send << VGT_DEBUG_REG1_VGT_PA_clip_s_send_SHIFT) +#define VGT_DEBUG_REG1_SET_PA_VGT_clip_p_rtr(vgt_debug_reg1_reg, pa_vgt_clip_p_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_MASK) | (pa_vgt_clip_p_rtr << VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_PA_clip_p_send(vgt_debug_reg1_reg, vgt_pa_clip_p_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_p_send_MASK) | (vgt_pa_clip_p_send << VGT_DEBUG_REG1_VGT_PA_clip_p_send_SHIFT) +#define VGT_DEBUG_REG1_SET_PA_VGT_clip_v_rtr(vgt_debug_reg1_reg, pa_vgt_clip_v_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_MASK) | (pa_vgt_clip_v_rtr << VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_PA_clip_v_send(vgt_debug_reg1_reg, vgt_pa_clip_v_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_PA_clip_v_send_MASK) | (vgt_pa_clip_v_send << VGT_DEBUG_REG1_VGT_PA_clip_v_send_SHIFT) +#define VGT_DEBUG_REG1_SET_SQ_VGT_rtr(vgt_debug_reg1_reg, sq_vgt_rtr) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_SQ_VGT_rtr_MASK) | (sq_vgt_rtr << VGT_DEBUG_REG1_SQ_VGT_rtr_SHIFT) +#define VGT_DEBUG_REG1_SET_VGT_SQ_send(vgt_debug_reg1_reg, vgt_sq_send) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_VGT_SQ_send_MASK) | (vgt_sq_send << VGT_DEBUG_REG1_VGT_SQ_send_SHIFT) +#define VGT_DEBUG_REG1_SET_mh_vgt_tag_7_q(vgt_debug_reg1_reg, mh_vgt_tag_7_q) \ + vgt_debug_reg1_reg = (vgt_debug_reg1_reg & ~VGT_DEBUG_REG1_mh_vgt_tag_7_q_MASK) | (mh_vgt_tag_7_q << VGT_DEBUG_REG1_mh_vgt_tag_7_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg1_t { + unsigned int out_te_data_read : VGT_DEBUG_REG1_out_te_data_read_SIZE; + unsigned int te_out_data_valid : VGT_DEBUG_REG1_te_out_data_valid_SIZE; + unsigned int out_pt_prim_read : VGT_DEBUG_REG1_out_pt_prim_read_SIZE; + unsigned int pt_out_prim_valid : VGT_DEBUG_REG1_pt_out_prim_valid_SIZE; + unsigned int out_pt_data_read : VGT_DEBUG_REG1_out_pt_data_read_SIZE; + unsigned int pt_out_indx_valid : VGT_DEBUG_REG1_pt_out_indx_valid_SIZE; + unsigned int out_vr_prim_read : VGT_DEBUG_REG1_out_vr_prim_read_SIZE; + unsigned int vr_out_prim_valid : VGT_DEBUG_REG1_vr_out_prim_valid_SIZE; + unsigned int out_vr_indx_read : VGT_DEBUG_REG1_out_vr_indx_read_SIZE; + unsigned int vr_out_indx_valid : VGT_DEBUG_REG1_vr_out_indx_valid_SIZE; + unsigned int te_grp_read : VGT_DEBUG_REG1_te_grp_read_SIZE; + unsigned int grp_te_valid : VGT_DEBUG_REG1_grp_te_valid_SIZE; + unsigned int pt_grp_read : VGT_DEBUG_REG1_pt_grp_read_SIZE; + unsigned int grp_pt_valid : VGT_DEBUG_REG1_grp_pt_valid_SIZE; + unsigned int vr_grp_read : VGT_DEBUG_REG1_vr_grp_read_SIZE; + unsigned int grp_vr_valid : VGT_DEBUG_REG1_grp_vr_valid_SIZE; + unsigned int grp_dma_read : VGT_DEBUG_REG1_grp_dma_read_SIZE; + unsigned int dma_grp_valid : VGT_DEBUG_REG1_dma_grp_valid_SIZE; + unsigned int grp_rbiu_di_read : VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE; + unsigned int rbiu_grp_di_valid : VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE; + unsigned int mh_vgt_rtr : VGT_DEBUG_REG1_MH_VGT_rtr_SIZE; + unsigned int vgt_mh_send : VGT_DEBUG_REG1_VGT_MH_send_SIZE; + unsigned int pa_vgt_clip_s_rtr : VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE; + unsigned int vgt_pa_clip_s_send : VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE; + unsigned int pa_vgt_clip_p_rtr : VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE; + unsigned int vgt_pa_clip_p_send : VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE; + unsigned int pa_vgt_clip_v_rtr : VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE; + unsigned int vgt_pa_clip_v_send : VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE; + unsigned int sq_vgt_rtr : VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE; + unsigned int vgt_sq_send : VGT_DEBUG_REG1_VGT_SQ_send_SIZE; + unsigned int mh_vgt_tag_7_q : VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE; + unsigned int : 1; + } vgt_debug_reg1_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg1_t { + unsigned int : 1; + unsigned int mh_vgt_tag_7_q : VGT_DEBUG_REG1_mh_vgt_tag_7_q_SIZE; + unsigned int vgt_sq_send : VGT_DEBUG_REG1_VGT_SQ_send_SIZE; + unsigned int sq_vgt_rtr : VGT_DEBUG_REG1_SQ_VGT_rtr_SIZE; + unsigned int vgt_pa_clip_v_send : VGT_DEBUG_REG1_VGT_PA_clip_v_send_SIZE; + unsigned int pa_vgt_clip_v_rtr : VGT_DEBUG_REG1_PA_VGT_clip_v_rtr_SIZE; + unsigned int vgt_pa_clip_p_send : VGT_DEBUG_REG1_VGT_PA_clip_p_send_SIZE; + unsigned int pa_vgt_clip_p_rtr : VGT_DEBUG_REG1_PA_VGT_clip_p_rtr_SIZE; + unsigned int vgt_pa_clip_s_send : VGT_DEBUG_REG1_VGT_PA_clip_s_send_SIZE; + unsigned int pa_vgt_clip_s_rtr : VGT_DEBUG_REG1_PA_VGT_clip_s_rtr_SIZE; + unsigned int vgt_mh_send : VGT_DEBUG_REG1_VGT_MH_send_SIZE; + unsigned int mh_vgt_rtr : VGT_DEBUG_REG1_MH_VGT_rtr_SIZE; + unsigned int rbiu_grp_di_valid : VGT_DEBUG_REG1_rbiu_grp_di_valid_SIZE; + unsigned int grp_rbiu_di_read : VGT_DEBUG_REG1_grp_rbiu_di_read_SIZE; + unsigned int dma_grp_valid : VGT_DEBUG_REG1_dma_grp_valid_SIZE; + unsigned int grp_dma_read : VGT_DEBUG_REG1_grp_dma_read_SIZE; + unsigned int grp_vr_valid : VGT_DEBUG_REG1_grp_vr_valid_SIZE; + unsigned int vr_grp_read : VGT_DEBUG_REG1_vr_grp_read_SIZE; + unsigned int grp_pt_valid : VGT_DEBUG_REG1_grp_pt_valid_SIZE; + unsigned int pt_grp_read : VGT_DEBUG_REG1_pt_grp_read_SIZE; + unsigned int grp_te_valid : VGT_DEBUG_REG1_grp_te_valid_SIZE; + unsigned int te_grp_read : VGT_DEBUG_REG1_te_grp_read_SIZE; + unsigned int vr_out_indx_valid : VGT_DEBUG_REG1_vr_out_indx_valid_SIZE; + unsigned int out_vr_indx_read : VGT_DEBUG_REG1_out_vr_indx_read_SIZE; + unsigned int vr_out_prim_valid : VGT_DEBUG_REG1_vr_out_prim_valid_SIZE; + unsigned int out_vr_prim_read : VGT_DEBUG_REG1_out_vr_prim_read_SIZE; + unsigned int pt_out_indx_valid : VGT_DEBUG_REG1_pt_out_indx_valid_SIZE; + unsigned int out_pt_data_read : VGT_DEBUG_REG1_out_pt_data_read_SIZE; + unsigned int pt_out_prim_valid : VGT_DEBUG_REG1_pt_out_prim_valid_SIZE; + unsigned int out_pt_prim_read : VGT_DEBUG_REG1_out_pt_prim_read_SIZE; + unsigned int te_out_data_valid : VGT_DEBUG_REG1_te_out_data_valid_SIZE; + unsigned int out_te_data_read : VGT_DEBUG_REG1_out_te_data_read_SIZE; + } vgt_debug_reg1_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg1_t f; +} vgt_debug_reg1_u; + + +/* + * VGT_DEBUG_REG3 struct + */ + +#define VGT_DEBUG_REG3_vgt_clk_en_SIZE 1 +#define VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE 1 + +#define VGT_DEBUG_REG3_vgt_clk_en_SHIFT 0 +#define VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT 1 + +#define VGT_DEBUG_REG3_vgt_clk_en_MASK 0x00000001 +#define VGT_DEBUG_REG3_reg_fifos_clk_en_MASK 0x00000002 + +#define VGT_DEBUG_REG3_MASK \ + (VGT_DEBUG_REG3_vgt_clk_en_MASK | \ + VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) + +#define VGT_DEBUG_REG3(vgt_clk_en, reg_fifos_clk_en) \ + ((vgt_clk_en << VGT_DEBUG_REG3_vgt_clk_en_SHIFT) | \ + (reg_fifos_clk_en << VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT)) + +#define VGT_DEBUG_REG3_GET_vgt_clk_en(vgt_debug_reg3) \ + ((vgt_debug_reg3 & VGT_DEBUG_REG3_vgt_clk_en_MASK) >> VGT_DEBUG_REG3_vgt_clk_en_SHIFT) +#define VGT_DEBUG_REG3_GET_reg_fifos_clk_en(vgt_debug_reg3) \ + ((vgt_debug_reg3 & VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) >> VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT) + +#define VGT_DEBUG_REG3_SET_vgt_clk_en(vgt_debug_reg3_reg, vgt_clk_en) \ + vgt_debug_reg3_reg = (vgt_debug_reg3_reg & ~VGT_DEBUG_REG3_vgt_clk_en_MASK) | (vgt_clk_en << VGT_DEBUG_REG3_vgt_clk_en_SHIFT) +#define VGT_DEBUG_REG3_SET_reg_fifos_clk_en(vgt_debug_reg3_reg, reg_fifos_clk_en) \ + vgt_debug_reg3_reg = (vgt_debug_reg3_reg & ~VGT_DEBUG_REG3_reg_fifos_clk_en_MASK) | (reg_fifos_clk_en << VGT_DEBUG_REG3_reg_fifos_clk_en_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg3_t { + unsigned int vgt_clk_en : VGT_DEBUG_REG3_vgt_clk_en_SIZE; + unsigned int reg_fifos_clk_en : VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE; + unsigned int : 30; + } vgt_debug_reg3_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg3_t { + unsigned int : 30; + unsigned int reg_fifos_clk_en : VGT_DEBUG_REG3_reg_fifos_clk_en_SIZE; + unsigned int vgt_clk_en : VGT_DEBUG_REG3_vgt_clk_en_SIZE; + } vgt_debug_reg3_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg3_t f; +} vgt_debug_reg3_u; + + +/* + * VGT_DEBUG_REG6 struct + */ + +#define VGT_DEBUG_REG6_shifter_byte_count_q_SIZE 5 +#define VGT_DEBUG_REG6_right_word_indx_q_SIZE 5 +#define VGT_DEBUG_REG6_input_data_valid_SIZE 1 +#define VGT_DEBUG_REG6_input_data_xfer_SIZE 1 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE 1 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE 1 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE 1 +#define VGT_DEBUG_REG6_space_avail_from_shift_SIZE 1 +#define VGT_DEBUG_REG6_shifter_first_load_SIZE 1 +#define VGT_DEBUG_REG6_di_state_sel_q_SIZE 1 +#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE 1 +#define VGT_DEBUG_REG6_di_first_group_flag_q_SIZE 1 +#define VGT_DEBUG_REG6_di_event_flag_q_SIZE 1 +#define VGT_DEBUG_REG6_read_draw_initiator_SIZE 1 +#define VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE 1 +#define VGT_DEBUG_REG6_last_shift_of_packet_SIZE 1 +#define VGT_DEBUG_REG6_last_decr_of_packet_SIZE 1 +#define VGT_DEBUG_REG6_extract_vector_SIZE 1 +#define VGT_DEBUG_REG6_shift_vect_rtr_SIZE 1 +#define VGT_DEBUG_REG6_destination_rtr_SIZE 1 +#define VGT_DEBUG_REG6_grp_trigger_SIZE 1 + +#define VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT 0 +#define VGT_DEBUG_REG6_right_word_indx_q_SHIFT 5 +#define VGT_DEBUG_REG6_input_data_valid_SHIFT 10 +#define VGT_DEBUG_REG6_input_data_xfer_SHIFT 11 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT 12 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT 13 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT 14 +#define VGT_DEBUG_REG6_space_avail_from_shift_SHIFT 15 +#define VGT_DEBUG_REG6_shifter_first_load_SHIFT 16 +#define VGT_DEBUG_REG6_di_state_sel_q_SHIFT 17 +#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT 18 +#define VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT 19 +#define VGT_DEBUG_REG6_di_event_flag_q_SHIFT 20 +#define VGT_DEBUG_REG6_read_draw_initiator_SHIFT 21 +#define VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT 22 +#define VGT_DEBUG_REG6_last_shift_of_packet_SHIFT 23 +#define VGT_DEBUG_REG6_last_decr_of_packet_SHIFT 24 +#define VGT_DEBUG_REG6_extract_vector_SHIFT 25 +#define VGT_DEBUG_REG6_shift_vect_rtr_SHIFT 26 +#define VGT_DEBUG_REG6_destination_rtr_SHIFT 27 +#define VGT_DEBUG_REG6_grp_trigger_SHIFT 28 + +#define VGT_DEBUG_REG6_shifter_byte_count_q_MASK 0x0000001f +#define VGT_DEBUG_REG6_right_word_indx_q_MASK 0x000003e0 +#define VGT_DEBUG_REG6_input_data_valid_MASK 0x00000400 +#define VGT_DEBUG_REG6_input_data_xfer_MASK 0x00000800 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK 0x00001000 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK 0x00002000 +#define VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK 0x00004000 +#define VGT_DEBUG_REG6_space_avail_from_shift_MASK 0x00008000 +#define VGT_DEBUG_REG6_shifter_first_load_MASK 0x00010000 +#define VGT_DEBUG_REG6_di_state_sel_q_MASK 0x00020000 +#define VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK 0x00040000 +#define VGT_DEBUG_REG6_di_first_group_flag_q_MASK 0x00080000 +#define VGT_DEBUG_REG6_di_event_flag_q_MASK 0x00100000 +#define VGT_DEBUG_REG6_read_draw_initiator_MASK 0x00200000 +#define VGT_DEBUG_REG6_loading_di_requires_shifter_MASK 0x00400000 +#define VGT_DEBUG_REG6_last_shift_of_packet_MASK 0x00800000 +#define VGT_DEBUG_REG6_last_decr_of_packet_MASK 0x01000000 +#define VGT_DEBUG_REG6_extract_vector_MASK 0x02000000 +#define VGT_DEBUG_REG6_shift_vect_rtr_MASK 0x04000000 +#define VGT_DEBUG_REG6_destination_rtr_MASK 0x08000000 +#define VGT_DEBUG_REG6_grp_trigger_MASK 0x10000000 + +#define VGT_DEBUG_REG6_MASK \ + (VGT_DEBUG_REG6_shifter_byte_count_q_MASK | \ + VGT_DEBUG_REG6_right_word_indx_q_MASK | \ + VGT_DEBUG_REG6_input_data_valid_MASK | \ + VGT_DEBUG_REG6_input_data_xfer_MASK | \ + VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK | \ + VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK | \ + VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK | \ + VGT_DEBUG_REG6_space_avail_from_shift_MASK | \ + VGT_DEBUG_REG6_shifter_first_load_MASK | \ + VGT_DEBUG_REG6_di_state_sel_q_MASK | \ + VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK | \ + VGT_DEBUG_REG6_di_first_group_flag_q_MASK | \ + VGT_DEBUG_REG6_di_event_flag_q_MASK | \ + VGT_DEBUG_REG6_read_draw_initiator_MASK | \ + VGT_DEBUG_REG6_loading_di_requires_shifter_MASK | \ + VGT_DEBUG_REG6_last_shift_of_packet_MASK | \ + VGT_DEBUG_REG6_last_decr_of_packet_MASK | \ + VGT_DEBUG_REG6_extract_vector_MASK | \ + VGT_DEBUG_REG6_shift_vect_rtr_MASK | \ + VGT_DEBUG_REG6_destination_rtr_MASK | \ + VGT_DEBUG_REG6_grp_trigger_MASK) + +#define VGT_DEBUG_REG6(shifter_byte_count_q, right_word_indx_q, input_data_valid, input_data_xfer, next_shift_is_vect_1_q, next_shift_is_vect_1_d, next_shift_is_vect_1_pre_d, space_avail_from_shift, shifter_first_load, di_state_sel_q, shifter_waiting_for_first_load_q, di_first_group_flag_q, di_event_flag_q, read_draw_initiator, loading_di_requires_shifter, last_shift_of_packet, last_decr_of_packet, extract_vector, shift_vect_rtr, destination_rtr, grp_trigger) \ + ((shifter_byte_count_q << VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT) | \ + (right_word_indx_q << VGT_DEBUG_REG6_right_word_indx_q_SHIFT) | \ + (input_data_valid << VGT_DEBUG_REG6_input_data_valid_SHIFT) | \ + (input_data_xfer << VGT_DEBUG_REG6_input_data_xfer_SHIFT) | \ + (next_shift_is_vect_1_q << VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT) | \ + (next_shift_is_vect_1_d << VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT) | \ + (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT) | \ + (space_avail_from_shift << VGT_DEBUG_REG6_space_avail_from_shift_SHIFT) | \ + (shifter_first_load << VGT_DEBUG_REG6_shifter_first_load_SHIFT) | \ + (di_state_sel_q << VGT_DEBUG_REG6_di_state_sel_q_SHIFT) | \ + (shifter_waiting_for_first_load_q << VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT) | \ + (di_first_group_flag_q << VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT) | \ + (di_event_flag_q << VGT_DEBUG_REG6_di_event_flag_q_SHIFT) | \ + (read_draw_initiator << VGT_DEBUG_REG6_read_draw_initiator_SHIFT) | \ + (loading_di_requires_shifter << VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT) | \ + (last_shift_of_packet << VGT_DEBUG_REG6_last_shift_of_packet_SHIFT) | \ + (last_decr_of_packet << VGT_DEBUG_REG6_last_decr_of_packet_SHIFT) | \ + (extract_vector << VGT_DEBUG_REG6_extract_vector_SHIFT) | \ + (shift_vect_rtr << VGT_DEBUG_REG6_shift_vect_rtr_SHIFT) | \ + (destination_rtr << VGT_DEBUG_REG6_destination_rtr_SHIFT) | \ + (grp_trigger << VGT_DEBUG_REG6_grp_trigger_SHIFT)) + +#define VGT_DEBUG_REG6_GET_shifter_byte_count_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_byte_count_q_MASK) >> VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT) +#define VGT_DEBUG_REG6_GET_right_word_indx_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_right_word_indx_q_MASK) >> VGT_DEBUG_REG6_right_word_indx_q_SHIFT) +#define VGT_DEBUG_REG6_GET_input_data_valid(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_input_data_valid_MASK) >> VGT_DEBUG_REG6_input_data_valid_SHIFT) +#define VGT_DEBUG_REG6_GET_input_data_xfer(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_input_data_xfer_MASK) >> VGT_DEBUG_REG6_input_data_xfer_SHIFT) +#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT) +#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_d(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT) +#define VGT_DEBUG_REG6_GET_next_shift_is_vect_1_pre_d(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK) >> VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT) +#define VGT_DEBUG_REG6_GET_space_avail_from_shift(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_space_avail_from_shift_MASK) >> VGT_DEBUG_REG6_space_avail_from_shift_SHIFT) +#define VGT_DEBUG_REG6_GET_shifter_first_load(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_first_load_MASK) >> VGT_DEBUG_REG6_shifter_first_load_SHIFT) +#define VGT_DEBUG_REG6_GET_di_state_sel_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_state_sel_q_MASK) >> VGT_DEBUG_REG6_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG6_GET_shifter_waiting_for_first_load_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK) >> VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT) +#define VGT_DEBUG_REG6_GET_di_first_group_flag_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_first_group_flag_q_MASK) >> VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT) +#define VGT_DEBUG_REG6_GET_di_event_flag_q(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_di_event_flag_q_MASK) >> VGT_DEBUG_REG6_di_event_flag_q_SHIFT) +#define VGT_DEBUG_REG6_GET_read_draw_initiator(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_read_draw_initiator_MASK) >> VGT_DEBUG_REG6_read_draw_initiator_SHIFT) +#define VGT_DEBUG_REG6_GET_loading_di_requires_shifter(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_loading_di_requires_shifter_MASK) >> VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT) +#define VGT_DEBUG_REG6_GET_last_shift_of_packet(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_last_shift_of_packet_MASK) >> VGT_DEBUG_REG6_last_shift_of_packet_SHIFT) +#define VGT_DEBUG_REG6_GET_last_decr_of_packet(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_last_decr_of_packet_MASK) >> VGT_DEBUG_REG6_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG6_GET_extract_vector(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_extract_vector_MASK) >> VGT_DEBUG_REG6_extract_vector_SHIFT) +#define VGT_DEBUG_REG6_GET_shift_vect_rtr(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_shift_vect_rtr_MASK) >> VGT_DEBUG_REG6_shift_vect_rtr_SHIFT) +#define VGT_DEBUG_REG6_GET_destination_rtr(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_destination_rtr_MASK) >> VGT_DEBUG_REG6_destination_rtr_SHIFT) +#define VGT_DEBUG_REG6_GET_grp_trigger(vgt_debug_reg6) \ + ((vgt_debug_reg6 & VGT_DEBUG_REG6_grp_trigger_MASK) >> VGT_DEBUG_REG6_grp_trigger_SHIFT) + +#define VGT_DEBUG_REG6_SET_shifter_byte_count_q(vgt_debug_reg6_reg, shifter_byte_count_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_byte_count_q_MASK) | (shifter_byte_count_q << VGT_DEBUG_REG6_shifter_byte_count_q_SHIFT) +#define VGT_DEBUG_REG6_SET_right_word_indx_q(vgt_debug_reg6_reg, right_word_indx_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_right_word_indx_q_MASK) | (right_word_indx_q << VGT_DEBUG_REG6_right_word_indx_q_SHIFT) +#define VGT_DEBUG_REG6_SET_input_data_valid(vgt_debug_reg6_reg, input_data_valid) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_input_data_valid_MASK) | (input_data_valid << VGT_DEBUG_REG6_input_data_valid_SHIFT) +#define VGT_DEBUG_REG6_SET_input_data_xfer(vgt_debug_reg6_reg, input_data_xfer) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_input_data_xfer_MASK) | (input_data_xfer << VGT_DEBUG_REG6_input_data_xfer_SHIFT) +#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_q(vgt_debug_reg6_reg, next_shift_is_vect_1_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_q_MASK) | (next_shift_is_vect_1_q << VGT_DEBUG_REG6_next_shift_is_vect_1_q_SHIFT) +#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_d(vgt_debug_reg6_reg, next_shift_is_vect_1_d) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_d_MASK) | (next_shift_is_vect_1_d << VGT_DEBUG_REG6_next_shift_is_vect_1_d_SHIFT) +#define VGT_DEBUG_REG6_SET_next_shift_is_vect_1_pre_d(vgt_debug_reg6_reg, next_shift_is_vect_1_pre_d) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_MASK) | (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SHIFT) +#define VGT_DEBUG_REG6_SET_space_avail_from_shift(vgt_debug_reg6_reg, space_avail_from_shift) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_space_avail_from_shift_MASK) | (space_avail_from_shift << VGT_DEBUG_REG6_space_avail_from_shift_SHIFT) +#define VGT_DEBUG_REG6_SET_shifter_first_load(vgt_debug_reg6_reg, shifter_first_load) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_first_load_MASK) | (shifter_first_load << VGT_DEBUG_REG6_shifter_first_load_SHIFT) +#define VGT_DEBUG_REG6_SET_di_state_sel_q(vgt_debug_reg6_reg, di_state_sel_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG6_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG6_SET_shifter_waiting_for_first_load_q(vgt_debug_reg6_reg, shifter_waiting_for_first_load_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_MASK) | (shifter_waiting_for_first_load_q << VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SHIFT) +#define VGT_DEBUG_REG6_SET_di_first_group_flag_q(vgt_debug_reg6_reg, di_first_group_flag_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_first_group_flag_q_MASK) | (di_first_group_flag_q << VGT_DEBUG_REG6_di_first_group_flag_q_SHIFT) +#define VGT_DEBUG_REG6_SET_di_event_flag_q(vgt_debug_reg6_reg, di_event_flag_q) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_di_event_flag_q_MASK) | (di_event_flag_q << VGT_DEBUG_REG6_di_event_flag_q_SHIFT) +#define VGT_DEBUG_REG6_SET_read_draw_initiator(vgt_debug_reg6_reg, read_draw_initiator) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_read_draw_initiator_MASK) | (read_draw_initiator << VGT_DEBUG_REG6_read_draw_initiator_SHIFT) +#define VGT_DEBUG_REG6_SET_loading_di_requires_shifter(vgt_debug_reg6_reg, loading_di_requires_shifter) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_loading_di_requires_shifter_MASK) | (loading_di_requires_shifter << VGT_DEBUG_REG6_loading_di_requires_shifter_SHIFT) +#define VGT_DEBUG_REG6_SET_last_shift_of_packet(vgt_debug_reg6_reg, last_shift_of_packet) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_last_shift_of_packet_MASK) | (last_shift_of_packet << VGT_DEBUG_REG6_last_shift_of_packet_SHIFT) +#define VGT_DEBUG_REG6_SET_last_decr_of_packet(vgt_debug_reg6_reg, last_decr_of_packet) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG6_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG6_SET_extract_vector(vgt_debug_reg6_reg, extract_vector) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_extract_vector_MASK) | (extract_vector << VGT_DEBUG_REG6_extract_vector_SHIFT) +#define VGT_DEBUG_REG6_SET_shift_vect_rtr(vgt_debug_reg6_reg, shift_vect_rtr) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_shift_vect_rtr_MASK) | (shift_vect_rtr << VGT_DEBUG_REG6_shift_vect_rtr_SHIFT) +#define VGT_DEBUG_REG6_SET_destination_rtr(vgt_debug_reg6_reg, destination_rtr) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_destination_rtr_MASK) | (destination_rtr << VGT_DEBUG_REG6_destination_rtr_SHIFT) +#define VGT_DEBUG_REG6_SET_grp_trigger(vgt_debug_reg6_reg, grp_trigger) \ + vgt_debug_reg6_reg = (vgt_debug_reg6_reg & ~VGT_DEBUG_REG6_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG6_grp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg6_t { + unsigned int shifter_byte_count_q : VGT_DEBUG_REG6_shifter_byte_count_q_SIZE; + unsigned int right_word_indx_q : VGT_DEBUG_REG6_right_word_indx_q_SIZE; + unsigned int input_data_valid : VGT_DEBUG_REG6_input_data_valid_SIZE; + unsigned int input_data_xfer : VGT_DEBUG_REG6_input_data_xfer_SIZE; + unsigned int next_shift_is_vect_1_q : VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE; + unsigned int next_shift_is_vect_1_d : VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE; + unsigned int next_shift_is_vect_1_pre_d : VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE; + unsigned int space_avail_from_shift : VGT_DEBUG_REG6_space_avail_from_shift_SIZE; + unsigned int shifter_first_load : VGT_DEBUG_REG6_shifter_first_load_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG6_di_state_sel_q_SIZE; + unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE; + unsigned int di_first_group_flag_q : VGT_DEBUG_REG6_di_first_group_flag_q_SIZE; + unsigned int di_event_flag_q : VGT_DEBUG_REG6_di_event_flag_q_SIZE; + unsigned int read_draw_initiator : VGT_DEBUG_REG6_read_draw_initiator_SIZE; + unsigned int loading_di_requires_shifter : VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE; + unsigned int last_shift_of_packet : VGT_DEBUG_REG6_last_shift_of_packet_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG6_last_decr_of_packet_SIZE; + unsigned int extract_vector : VGT_DEBUG_REG6_extract_vector_SIZE; + unsigned int shift_vect_rtr : VGT_DEBUG_REG6_shift_vect_rtr_SIZE; + unsigned int destination_rtr : VGT_DEBUG_REG6_destination_rtr_SIZE; + unsigned int grp_trigger : VGT_DEBUG_REG6_grp_trigger_SIZE; + unsigned int : 3; + } vgt_debug_reg6_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg6_t { + unsigned int : 3; + unsigned int grp_trigger : VGT_DEBUG_REG6_grp_trigger_SIZE; + unsigned int destination_rtr : VGT_DEBUG_REG6_destination_rtr_SIZE; + unsigned int shift_vect_rtr : VGT_DEBUG_REG6_shift_vect_rtr_SIZE; + unsigned int extract_vector : VGT_DEBUG_REG6_extract_vector_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG6_last_decr_of_packet_SIZE; + unsigned int last_shift_of_packet : VGT_DEBUG_REG6_last_shift_of_packet_SIZE; + unsigned int loading_di_requires_shifter : VGT_DEBUG_REG6_loading_di_requires_shifter_SIZE; + unsigned int read_draw_initiator : VGT_DEBUG_REG6_read_draw_initiator_SIZE; + unsigned int di_event_flag_q : VGT_DEBUG_REG6_di_event_flag_q_SIZE; + unsigned int di_first_group_flag_q : VGT_DEBUG_REG6_di_first_group_flag_q_SIZE; + unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG6_shifter_waiting_for_first_load_q_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG6_di_state_sel_q_SIZE; + unsigned int shifter_first_load : VGT_DEBUG_REG6_shifter_first_load_SIZE; + unsigned int space_avail_from_shift : VGT_DEBUG_REG6_space_avail_from_shift_SIZE; + unsigned int next_shift_is_vect_1_pre_d : VGT_DEBUG_REG6_next_shift_is_vect_1_pre_d_SIZE; + unsigned int next_shift_is_vect_1_d : VGT_DEBUG_REG6_next_shift_is_vect_1_d_SIZE; + unsigned int next_shift_is_vect_1_q : VGT_DEBUG_REG6_next_shift_is_vect_1_q_SIZE; + unsigned int input_data_xfer : VGT_DEBUG_REG6_input_data_xfer_SIZE; + unsigned int input_data_valid : VGT_DEBUG_REG6_input_data_valid_SIZE; + unsigned int right_word_indx_q : VGT_DEBUG_REG6_right_word_indx_q_SIZE; + unsigned int shifter_byte_count_q : VGT_DEBUG_REG6_shifter_byte_count_q_SIZE; + } vgt_debug_reg6_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg6_t f; +} vgt_debug_reg6_u; + + +/* + * VGT_DEBUG_REG7 struct + */ + +#define VGT_DEBUG_REG7_di_index_counter_q_SIZE 16 +#define VGT_DEBUG_REG7_shift_amount_no_extract_SIZE 4 +#define VGT_DEBUG_REG7_shift_amount_extract_SIZE 4 +#define VGT_DEBUG_REG7_di_prim_type_q_SIZE 6 +#define VGT_DEBUG_REG7_current_source_sel_SIZE 2 + +#define VGT_DEBUG_REG7_di_index_counter_q_SHIFT 0 +#define VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT 16 +#define VGT_DEBUG_REG7_shift_amount_extract_SHIFT 20 +#define VGT_DEBUG_REG7_di_prim_type_q_SHIFT 24 +#define VGT_DEBUG_REG7_current_source_sel_SHIFT 30 + +#define VGT_DEBUG_REG7_di_index_counter_q_MASK 0x0000ffff +#define VGT_DEBUG_REG7_shift_amount_no_extract_MASK 0x000f0000 +#define VGT_DEBUG_REG7_shift_amount_extract_MASK 0x00f00000 +#define VGT_DEBUG_REG7_di_prim_type_q_MASK 0x3f000000 +#define VGT_DEBUG_REG7_current_source_sel_MASK 0xc0000000 + +#define VGT_DEBUG_REG7_MASK \ + (VGT_DEBUG_REG7_di_index_counter_q_MASK | \ + VGT_DEBUG_REG7_shift_amount_no_extract_MASK | \ + VGT_DEBUG_REG7_shift_amount_extract_MASK | \ + VGT_DEBUG_REG7_di_prim_type_q_MASK | \ + VGT_DEBUG_REG7_current_source_sel_MASK) + +#define VGT_DEBUG_REG7(di_index_counter_q, shift_amount_no_extract, shift_amount_extract, di_prim_type_q, current_source_sel) \ + ((di_index_counter_q << VGT_DEBUG_REG7_di_index_counter_q_SHIFT) | \ + (shift_amount_no_extract << VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT) | \ + (shift_amount_extract << VGT_DEBUG_REG7_shift_amount_extract_SHIFT) | \ + (di_prim_type_q << VGT_DEBUG_REG7_di_prim_type_q_SHIFT) | \ + (current_source_sel << VGT_DEBUG_REG7_current_source_sel_SHIFT)) + +#define VGT_DEBUG_REG7_GET_di_index_counter_q(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_di_index_counter_q_MASK) >> VGT_DEBUG_REG7_di_index_counter_q_SHIFT) +#define VGT_DEBUG_REG7_GET_shift_amount_no_extract(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_shift_amount_no_extract_MASK) >> VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT) +#define VGT_DEBUG_REG7_GET_shift_amount_extract(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_shift_amount_extract_MASK) >> VGT_DEBUG_REG7_shift_amount_extract_SHIFT) +#define VGT_DEBUG_REG7_GET_di_prim_type_q(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_di_prim_type_q_MASK) >> VGT_DEBUG_REG7_di_prim_type_q_SHIFT) +#define VGT_DEBUG_REG7_GET_current_source_sel(vgt_debug_reg7) \ + ((vgt_debug_reg7 & VGT_DEBUG_REG7_current_source_sel_MASK) >> VGT_DEBUG_REG7_current_source_sel_SHIFT) + +#define VGT_DEBUG_REG7_SET_di_index_counter_q(vgt_debug_reg7_reg, di_index_counter_q) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_di_index_counter_q_MASK) | (di_index_counter_q << VGT_DEBUG_REG7_di_index_counter_q_SHIFT) +#define VGT_DEBUG_REG7_SET_shift_amount_no_extract(vgt_debug_reg7_reg, shift_amount_no_extract) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_shift_amount_no_extract_MASK) | (shift_amount_no_extract << VGT_DEBUG_REG7_shift_amount_no_extract_SHIFT) +#define VGT_DEBUG_REG7_SET_shift_amount_extract(vgt_debug_reg7_reg, shift_amount_extract) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_shift_amount_extract_MASK) | (shift_amount_extract << VGT_DEBUG_REG7_shift_amount_extract_SHIFT) +#define VGT_DEBUG_REG7_SET_di_prim_type_q(vgt_debug_reg7_reg, di_prim_type_q) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_di_prim_type_q_MASK) | (di_prim_type_q << VGT_DEBUG_REG7_di_prim_type_q_SHIFT) +#define VGT_DEBUG_REG7_SET_current_source_sel(vgt_debug_reg7_reg, current_source_sel) \ + vgt_debug_reg7_reg = (vgt_debug_reg7_reg & ~VGT_DEBUG_REG7_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG7_current_source_sel_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg7_t { + unsigned int di_index_counter_q : VGT_DEBUG_REG7_di_index_counter_q_SIZE; + unsigned int shift_amount_no_extract : VGT_DEBUG_REG7_shift_amount_no_extract_SIZE; + unsigned int shift_amount_extract : VGT_DEBUG_REG7_shift_amount_extract_SIZE; + unsigned int di_prim_type_q : VGT_DEBUG_REG7_di_prim_type_q_SIZE; + unsigned int current_source_sel : VGT_DEBUG_REG7_current_source_sel_SIZE; + } vgt_debug_reg7_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg7_t { + unsigned int current_source_sel : VGT_DEBUG_REG7_current_source_sel_SIZE; + unsigned int di_prim_type_q : VGT_DEBUG_REG7_di_prim_type_q_SIZE; + unsigned int shift_amount_extract : VGT_DEBUG_REG7_shift_amount_extract_SIZE; + unsigned int shift_amount_no_extract : VGT_DEBUG_REG7_shift_amount_no_extract_SIZE; + unsigned int di_index_counter_q : VGT_DEBUG_REG7_di_index_counter_q_SIZE; + } vgt_debug_reg7_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg7_t f; +} vgt_debug_reg7_u; + + +/* + * VGT_DEBUG_REG8 struct + */ + +#define VGT_DEBUG_REG8_current_source_sel_SIZE 2 +#define VGT_DEBUG_REG8_left_word_indx_q_SIZE 5 +#define VGT_DEBUG_REG8_input_data_cnt_SIZE 5 +#define VGT_DEBUG_REG8_input_data_lsw_SIZE 5 +#define VGT_DEBUG_REG8_input_data_msw_SIZE 5 +#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE 5 +#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE 5 + +#define VGT_DEBUG_REG8_current_source_sel_SHIFT 0 +#define VGT_DEBUG_REG8_left_word_indx_q_SHIFT 2 +#define VGT_DEBUG_REG8_input_data_cnt_SHIFT 7 +#define VGT_DEBUG_REG8_input_data_lsw_SHIFT 12 +#define VGT_DEBUG_REG8_input_data_msw_SHIFT 17 +#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT 22 +#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT 27 + +#define VGT_DEBUG_REG8_current_source_sel_MASK 0x00000003 +#define VGT_DEBUG_REG8_left_word_indx_q_MASK 0x0000007c +#define VGT_DEBUG_REG8_input_data_cnt_MASK 0x00000f80 +#define VGT_DEBUG_REG8_input_data_lsw_MASK 0x0001f000 +#define VGT_DEBUG_REG8_input_data_msw_MASK 0x003e0000 +#define VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK 0x07c00000 +#define VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK 0xf8000000 + +#define VGT_DEBUG_REG8_MASK \ + (VGT_DEBUG_REG8_current_source_sel_MASK | \ + VGT_DEBUG_REG8_left_word_indx_q_MASK | \ + VGT_DEBUG_REG8_input_data_cnt_MASK | \ + VGT_DEBUG_REG8_input_data_lsw_MASK | \ + VGT_DEBUG_REG8_input_data_msw_MASK | \ + VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK | \ + VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) + +#define VGT_DEBUG_REG8(current_source_sel, left_word_indx_q, input_data_cnt, input_data_lsw, input_data_msw, next_small_stride_shift_limit_q, current_small_stride_shift_limit_q) \ + ((current_source_sel << VGT_DEBUG_REG8_current_source_sel_SHIFT) | \ + (left_word_indx_q << VGT_DEBUG_REG8_left_word_indx_q_SHIFT) | \ + (input_data_cnt << VGT_DEBUG_REG8_input_data_cnt_SHIFT) | \ + (input_data_lsw << VGT_DEBUG_REG8_input_data_lsw_SHIFT) | \ + (input_data_msw << VGT_DEBUG_REG8_input_data_msw_SHIFT) | \ + (next_small_stride_shift_limit_q << VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT) | \ + (current_small_stride_shift_limit_q << VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT)) + +#define VGT_DEBUG_REG8_GET_current_source_sel(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_current_source_sel_MASK) >> VGT_DEBUG_REG8_current_source_sel_SHIFT) +#define VGT_DEBUG_REG8_GET_left_word_indx_q(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_left_word_indx_q_MASK) >> VGT_DEBUG_REG8_left_word_indx_q_SHIFT) +#define VGT_DEBUG_REG8_GET_input_data_cnt(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_cnt_MASK) >> VGT_DEBUG_REG8_input_data_cnt_SHIFT) +#define VGT_DEBUG_REG8_GET_input_data_lsw(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_lsw_MASK) >> VGT_DEBUG_REG8_input_data_lsw_SHIFT) +#define VGT_DEBUG_REG8_GET_input_data_msw(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_input_data_msw_MASK) >> VGT_DEBUG_REG8_input_data_msw_SHIFT) +#define VGT_DEBUG_REG8_GET_next_small_stride_shift_limit_q(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT) +#define VGT_DEBUG_REG8_GET_current_small_stride_shift_limit_q(vgt_debug_reg8) \ + ((vgt_debug_reg8 & VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT) + +#define VGT_DEBUG_REG8_SET_current_source_sel(vgt_debug_reg8_reg, current_source_sel) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG8_current_source_sel_SHIFT) +#define VGT_DEBUG_REG8_SET_left_word_indx_q(vgt_debug_reg8_reg, left_word_indx_q) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_left_word_indx_q_MASK) | (left_word_indx_q << VGT_DEBUG_REG8_left_word_indx_q_SHIFT) +#define VGT_DEBUG_REG8_SET_input_data_cnt(vgt_debug_reg8_reg, input_data_cnt) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_cnt_MASK) | (input_data_cnt << VGT_DEBUG_REG8_input_data_cnt_SHIFT) +#define VGT_DEBUG_REG8_SET_input_data_lsw(vgt_debug_reg8_reg, input_data_lsw) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_lsw_MASK) | (input_data_lsw << VGT_DEBUG_REG8_input_data_lsw_SHIFT) +#define VGT_DEBUG_REG8_SET_input_data_msw(vgt_debug_reg8_reg, input_data_msw) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_input_data_msw_MASK) | (input_data_msw << VGT_DEBUG_REG8_input_data_msw_SHIFT) +#define VGT_DEBUG_REG8_SET_next_small_stride_shift_limit_q(vgt_debug_reg8_reg, next_small_stride_shift_limit_q) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_next_small_stride_shift_limit_q_MASK) | (next_small_stride_shift_limit_q << VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SHIFT) +#define VGT_DEBUG_REG8_SET_current_small_stride_shift_limit_q(vgt_debug_reg8_reg, current_small_stride_shift_limit_q) \ + vgt_debug_reg8_reg = (vgt_debug_reg8_reg & ~VGT_DEBUG_REG8_current_small_stride_shift_limit_q_MASK) | (current_small_stride_shift_limit_q << VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg8_t { + unsigned int current_source_sel : VGT_DEBUG_REG8_current_source_sel_SIZE; + unsigned int left_word_indx_q : VGT_DEBUG_REG8_left_word_indx_q_SIZE; + unsigned int input_data_cnt : VGT_DEBUG_REG8_input_data_cnt_SIZE; + unsigned int input_data_lsw : VGT_DEBUG_REG8_input_data_lsw_SIZE; + unsigned int input_data_msw : VGT_DEBUG_REG8_input_data_msw_SIZE; + unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE; + unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE; + } vgt_debug_reg8_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg8_t { + unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG8_current_small_stride_shift_limit_q_SIZE; + unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG8_next_small_stride_shift_limit_q_SIZE; + unsigned int input_data_msw : VGT_DEBUG_REG8_input_data_msw_SIZE; + unsigned int input_data_lsw : VGT_DEBUG_REG8_input_data_lsw_SIZE; + unsigned int input_data_cnt : VGT_DEBUG_REG8_input_data_cnt_SIZE; + unsigned int left_word_indx_q : VGT_DEBUG_REG8_left_word_indx_q_SIZE; + unsigned int current_source_sel : VGT_DEBUG_REG8_current_source_sel_SIZE; + } vgt_debug_reg8_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg8_t f; +} vgt_debug_reg8_u; + + +/* + * VGT_DEBUG_REG9 struct + */ + +#define VGT_DEBUG_REG9_next_stride_q_SIZE 5 +#define VGT_DEBUG_REG9_next_stride_d_SIZE 5 +#define VGT_DEBUG_REG9_current_shift_q_SIZE 5 +#define VGT_DEBUG_REG9_current_shift_d_SIZE 5 +#define VGT_DEBUG_REG9_current_stride_q_SIZE 5 +#define VGT_DEBUG_REG9_current_stride_d_SIZE 5 +#define VGT_DEBUG_REG9_grp_trigger_SIZE 1 + +#define VGT_DEBUG_REG9_next_stride_q_SHIFT 0 +#define VGT_DEBUG_REG9_next_stride_d_SHIFT 5 +#define VGT_DEBUG_REG9_current_shift_q_SHIFT 10 +#define VGT_DEBUG_REG9_current_shift_d_SHIFT 15 +#define VGT_DEBUG_REG9_current_stride_q_SHIFT 20 +#define VGT_DEBUG_REG9_current_stride_d_SHIFT 25 +#define VGT_DEBUG_REG9_grp_trigger_SHIFT 30 + +#define VGT_DEBUG_REG9_next_stride_q_MASK 0x0000001f +#define VGT_DEBUG_REG9_next_stride_d_MASK 0x000003e0 +#define VGT_DEBUG_REG9_current_shift_q_MASK 0x00007c00 +#define VGT_DEBUG_REG9_current_shift_d_MASK 0x000f8000 +#define VGT_DEBUG_REG9_current_stride_q_MASK 0x01f00000 +#define VGT_DEBUG_REG9_current_stride_d_MASK 0x3e000000 +#define VGT_DEBUG_REG9_grp_trigger_MASK 0x40000000 + +#define VGT_DEBUG_REG9_MASK \ + (VGT_DEBUG_REG9_next_stride_q_MASK | \ + VGT_DEBUG_REG9_next_stride_d_MASK | \ + VGT_DEBUG_REG9_current_shift_q_MASK | \ + VGT_DEBUG_REG9_current_shift_d_MASK | \ + VGT_DEBUG_REG9_current_stride_q_MASK | \ + VGT_DEBUG_REG9_current_stride_d_MASK | \ + VGT_DEBUG_REG9_grp_trigger_MASK) + +#define VGT_DEBUG_REG9(next_stride_q, next_stride_d, current_shift_q, current_shift_d, current_stride_q, current_stride_d, grp_trigger) \ + ((next_stride_q << VGT_DEBUG_REG9_next_stride_q_SHIFT) | \ + (next_stride_d << VGT_DEBUG_REG9_next_stride_d_SHIFT) | \ + (current_shift_q << VGT_DEBUG_REG9_current_shift_q_SHIFT) | \ + (current_shift_d << VGT_DEBUG_REG9_current_shift_d_SHIFT) | \ + (current_stride_q << VGT_DEBUG_REG9_current_stride_q_SHIFT) | \ + (current_stride_d << VGT_DEBUG_REG9_current_stride_d_SHIFT) | \ + (grp_trigger << VGT_DEBUG_REG9_grp_trigger_SHIFT)) + +#define VGT_DEBUG_REG9_GET_next_stride_q(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_next_stride_q_MASK) >> VGT_DEBUG_REG9_next_stride_q_SHIFT) +#define VGT_DEBUG_REG9_GET_next_stride_d(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_next_stride_d_MASK) >> VGT_DEBUG_REG9_next_stride_d_SHIFT) +#define VGT_DEBUG_REG9_GET_current_shift_q(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_shift_q_MASK) >> VGT_DEBUG_REG9_current_shift_q_SHIFT) +#define VGT_DEBUG_REG9_GET_current_shift_d(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_shift_d_MASK) >> VGT_DEBUG_REG9_current_shift_d_SHIFT) +#define VGT_DEBUG_REG9_GET_current_stride_q(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_stride_q_MASK) >> VGT_DEBUG_REG9_current_stride_q_SHIFT) +#define VGT_DEBUG_REG9_GET_current_stride_d(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_current_stride_d_MASK) >> VGT_DEBUG_REG9_current_stride_d_SHIFT) +#define VGT_DEBUG_REG9_GET_grp_trigger(vgt_debug_reg9) \ + ((vgt_debug_reg9 & VGT_DEBUG_REG9_grp_trigger_MASK) >> VGT_DEBUG_REG9_grp_trigger_SHIFT) + +#define VGT_DEBUG_REG9_SET_next_stride_q(vgt_debug_reg9_reg, next_stride_q) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_next_stride_q_MASK) | (next_stride_q << VGT_DEBUG_REG9_next_stride_q_SHIFT) +#define VGT_DEBUG_REG9_SET_next_stride_d(vgt_debug_reg9_reg, next_stride_d) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_next_stride_d_MASK) | (next_stride_d << VGT_DEBUG_REG9_next_stride_d_SHIFT) +#define VGT_DEBUG_REG9_SET_current_shift_q(vgt_debug_reg9_reg, current_shift_q) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_shift_q_MASK) | (current_shift_q << VGT_DEBUG_REG9_current_shift_q_SHIFT) +#define VGT_DEBUG_REG9_SET_current_shift_d(vgt_debug_reg9_reg, current_shift_d) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_shift_d_MASK) | (current_shift_d << VGT_DEBUG_REG9_current_shift_d_SHIFT) +#define VGT_DEBUG_REG9_SET_current_stride_q(vgt_debug_reg9_reg, current_stride_q) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_stride_q_MASK) | (current_stride_q << VGT_DEBUG_REG9_current_stride_q_SHIFT) +#define VGT_DEBUG_REG9_SET_current_stride_d(vgt_debug_reg9_reg, current_stride_d) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_current_stride_d_MASK) | (current_stride_d << VGT_DEBUG_REG9_current_stride_d_SHIFT) +#define VGT_DEBUG_REG9_SET_grp_trigger(vgt_debug_reg9_reg, grp_trigger) \ + vgt_debug_reg9_reg = (vgt_debug_reg9_reg & ~VGT_DEBUG_REG9_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG9_grp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg9_t { + unsigned int next_stride_q : VGT_DEBUG_REG9_next_stride_q_SIZE; + unsigned int next_stride_d : VGT_DEBUG_REG9_next_stride_d_SIZE; + unsigned int current_shift_q : VGT_DEBUG_REG9_current_shift_q_SIZE; + unsigned int current_shift_d : VGT_DEBUG_REG9_current_shift_d_SIZE; + unsigned int current_stride_q : VGT_DEBUG_REG9_current_stride_q_SIZE; + unsigned int current_stride_d : VGT_DEBUG_REG9_current_stride_d_SIZE; + unsigned int grp_trigger : VGT_DEBUG_REG9_grp_trigger_SIZE; + unsigned int : 1; + } vgt_debug_reg9_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg9_t { + unsigned int : 1; + unsigned int grp_trigger : VGT_DEBUG_REG9_grp_trigger_SIZE; + unsigned int current_stride_d : VGT_DEBUG_REG9_current_stride_d_SIZE; + unsigned int current_stride_q : VGT_DEBUG_REG9_current_stride_q_SIZE; + unsigned int current_shift_d : VGT_DEBUG_REG9_current_shift_d_SIZE; + unsigned int current_shift_q : VGT_DEBUG_REG9_current_shift_q_SIZE; + unsigned int next_stride_d : VGT_DEBUG_REG9_next_stride_d_SIZE; + unsigned int next_stride_q : VGT_DEBUG_REG9_next_stride_q_SIZE; + } vgt_debug_reg9_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg9_t f; +} vgt_debug_reg9_u; + + +/* + * VGT_DEBUG_REG10 struct + */ + +#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE 1 +#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE 1 +#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE 1 +#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE 1 +#define VGT_DEBUG_REG10_di_state_sel_q_SIZE 1 +#define VGT_DEBUG_REG10_last_decr_of_packet_SIZE 1 +#define VGT_DEBUG_REG10_bin_valid_SIZE 1 +#define VGT_DEBUG_REG10_read_block_SIZE 1 +#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE 1 +#define VGT_DEBUG_REG10_last_bit_enable_q_SIZE 1 +#define VGT_DEBUG_REG10_last_bit_end_di_q_SIZE 1 +#define VGT_DEBUG_REG10_selected_data_SIZE 8 +#define VGT_DEBUG_REG10_mask_input_data_SIZE 8 +#define VGT_DEBUG_REG10_gap_q_SIZE 1 +#define VGT_DEBUG_REG10_temp_mini_reset_z_SIZE 1 +#define VGT_DEBUG_REG10_temp_mini_reset_y_SIZE 1 +#define VGT_DEBUG_REG10_temp_mini_reset_x_SIZE 1 +#define VGT_DEBUG_REG10_grp_trigger_SIZE 1 + +#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT 0 +#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT 1 +#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT 2 +#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT 3 +#define VGT_DEBUG_REG10_di_state_sel_q_SHIFT 4 +#define VGT_DEBUG_REG10_last_decr_of_packet_SHIFT 5 +#define VGT_DEBUG_REG10_bin_valid_SHIFT 6 +#define VGT_DEBUG_REG10_read_block_SHIFT 7 +#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT 8 +#define VGT_DEBUG_REG10_last_bit_enable_q_SHIFT 9 +#define VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT 10 +#define VGT_DEBUG_REG10_selected_data_SHIFT 11 +#define VGT_DEBUG_REG10_mask_input_data_SHIFT 19 +#define VGT_DEBUG_REG10_gap_q_SHIFT 27 +#define VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT 28 +#define VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT 29 +#define VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT 30 +#define VGT_DEBUG_REG10_grp_trigger_SHIFT 31 + +#define VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK 0x00000001 +#define VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK 0x00000002 +#define VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK 0x00000004 +#define VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK 0x00000008 +#define VGT_DEBUG_REG10_di_state_sel_q_MASK 0x00000010 +#define VGT_DEBUG_REG10_last_decr_of_packet_MASK 0x00000020 +#define VGT_DEBUG_REG10_bin_valid_MASK 0x00000040 +#define VGT_DEBUG_REG10_read_block_MASK 0x00000080 +#define VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK 0x00000100 +#define VGT_DEBUG_REG10_last_bit_enable_q_MASK 0x00000200 +#define VGT_DEBUG_REG10_last_bit_end_di_q_MASK 0x00000400 +#define VGT_DEBUG_REG10_selected_data_MASK 0x0007f800 +#define VGT_DEBUG_REG10_mask_input_data_MASK 0x07f80000 +#define VGT_DEBUG_REG10_gap_q_MASK 0x08000000 +#define VGT_DEBUG_REG10_temp_mini_reset_z_MASK 0x10000000 +#define VGT_DEBUG_REG10_temp_mini_reset_y_MASK 0x20000000 +#define VGT_DEBUG_REG10_temp_mini_reset_x_MASK 0x40000000 +#define VGT_DEBUG_REG10_grp_trigger_MASK 0x80000000 + +#define VGT_DEBUG_REG10_MASK \ + (VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK | \ + VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK | \ + VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK | \ + VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK | \ + VGT_DEBUG_REG10_di_state_sel_q_MASK | \ + VGT_DEBUG_REG10_last_decr_of_packet_MASK | \ + VGT_DEBUG_REG10_bin_valid_MASK | \ + VGT_DEBUG_REG10_read_block_MASK | \ + VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK | \ + VGT_DEBUG_REG10_last_bit_enable_q_MASK | \ + VGT_DEBUG_REG10_last_bit_end_di_q_MASK | \ + VGT_DEBUG_REG10_selected_data_MASK | \ + VGT_DEBUG_REG10_mask_input_data_MASK | \ + VGT_DEBUG_REG10_gap_q_MASK | \ + VGT_DEBUG_REG10_temp_mini_reset_z_MASK | \ + VGT_DEBUG_REG10_temp_mini_reset_y_MASK | \ + VGT_DEBUG_REG10_temp_mini_reset_x_MASK | \ + VGT_DEBUG_REG10_grp_trigger_MASK) + +#define VGT_DEBUG_REG10(temp_derived_di_prim_type_t0, temp_derived_di_small_index_t0, temp_derived_di_cull_enable_t0, temp_derived_di_pre_fetch_cull_enable_t0, di_state_sel_q, last_decr_of_packet, bin_valid, read_block, grp_bgrp_last_bit_read, last_bit_enable_q, last_bit_end_di_q, selected_data, mask_input_data, gap_q, temp_mini_reset_z, temp_mini_reset_y, temp_mini_reset_x, grp_trigger) \ + ((temp_derived_di_prim_type_t0 << VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT) | \ + (temp_derived_di_small_index_t0 << VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT) | \ + (temp_derived_di_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT) | \ + (temp_derived_di_pre_fetch_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT) | \ + (di_state_sel_q << VGT_DEBUG_REG10_di_state_sel_q_SHIFT) | \ + (last_decr_of_packet << VGT_DEBUG_REG10_last_decr_of_packet_SHIFT) | \ + (bin_valid << VGT_DEBUG_REG10_bin_valid_SHIFT) | \ + (read_block << VGT_DEBUG_REG10_read_block_SHIFT) | \ + (grp_bgrp_last_bit_read << VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT) | \ + (last_bit_enable_q << VGT_DEBUG_REG10_last_bit_enable_q_SHIFT) | \ + (last_bit_end_di_q << VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT) | \ + (selected_data << VGT_DEBUG_REG10_selected_data_SHIFT) | \ + (mask_input_data << VGT_DEBUG_REG10_mask_input_data_SHIFT) | \ + (gap_q << VGT_DEBUG_REG10_gap_q_SHIFT) | \ + (temp_mini_reset_z << VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT) | \ + (temp_mini_reset_y << VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT) | \ + (temp_mini_reset_x << VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT) | \ + (grp_trigger << VGT_DEBUG_REG10_grp_trigger_SHIFT)) + +#define VGT_DEBUG_REG10_GET_temp_derived_di_prim_type_t0(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_derived_di_small_index_t0(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_derived_di_cull_enable_t0(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_derived_di_pre_fetch_cull_enable_t0(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK) >> VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT) +#define VGT_DEBUG_REG10_GET_di_state_sel_q(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_di_state_sel_q_MASK) >> VGT_DEBUG_REG10_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG10_GET_last_decr_of_packet(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_decr_of_packet_MASK) >> VGT_DEBUG_REG10_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG10_GET_bin_valid(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_bin_valid_MASK) >> VGT_DEBUG_REG10_bin_valid_SHIFT) +#define VGT_DEBUG_REG10_GET_read_block(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_read_block_MASK) >> VGT_DEBUG_REG10_read_block_SHIFT) +#define VGT_DEBUG_REG10_GET_grp_bgrp_last_bit_read(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK) >> VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT) +#define VGT_DEBUG_REG10_GET_last_bit_enable_q(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_bit_enable_q_MASK) >> VGT_DEBUG_REG10_last_bit_enable_q_SHIFT) +#define VGT_DEBUG_REG10_GET_last_bit_end_di_q(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_last_bit_end_di_q_MASK) >> VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT) +#define VGT_DEBUG_REG10_GET_selected_data(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_selected_data_MASK) >> VGT_DEBUG_REG10_selected_data_SHIFT) +#define VGT_DEBUG_REG10_GET_mask_input_data(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_mask_input_data_MASK) >> VGT_DEBUG_REG10_mask_input_data_SHIFT) +#define VGT_DEBUG_REG10_GET_gap_q(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_gap_q_MASK) >> VGT_DEBUG_REG10_gap_q_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_mini_reset_z(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_z_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_mini_reset_y(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_y_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT) +#define VGT_DEBUG_REG10_GET_temp_mini_reset_x(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_temp_mini_reset_x_MASK) >> VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT) +#define VGT_DEBUG_REG10_GET_grp_trigger(vgt_debug_reg10) \ + ((vgt_debug_reg10 & VGT_DEBUG_REG10_grp_trigger_MASK) >> VGT_DEBUG_REG10_grp_trigger_SHIFT) + +#define VGT_DEBUG_REG10_SET_temp_derived_di_prim_type_t0(vgt_debug_reg10_reg, temp_derived_di_prim_type_t0) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_MASK) | (temp_derived_di_prim_type_t0 << VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_derived_di_small_index_t0(vgt_debug_reg10_reg, temp_derived_di_small_index_t0) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_small_index_t0_MASK) | (temp_derived_di_small_index_t0 << VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_derived_di_cull_enable_t0(vgt_debug_reg10_reg, temp_derived_di_cull_enable_t0) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_MASK) | (temp_derived_di_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_derived_di_pre_fetch_cull_enable_t0(vgt_debug_reg10_reg, temp_derived_di_pre_fetch_cull_enable_t0) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_MASK) | (temp_derived_di_pre_fetch_cull_enable_t0 << VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SHIFT) +#define VGT_DEBUG_REG10_SET_di_state_sel_q(vgt_debug_reg10_reg, di_state_sel_q) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG10_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG10_SET_last_decr_of_packet(vgt_debug_reg10_reg, last_decr_of_packet) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG10_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG10_SET_bin_valid(vgt_debug_reg10_reg, bin_valid) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_bin_valid_MASK) | (bin_valid << VGT_DEBUG_REG10_bin_valid_SHIFT) +#define VGT_DEBUG_REG10_SET_read_block(vgt_debug_reg10_reg, read_block) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_read_block_MASK) | (read_block << VGT_DEBUG_REG10_read_block_SHIFT) +#define VGT_DEBUG_REG10_SET_grp_bgrp_last_bit_read(vgt_debug_reg10_reg, grp_bgrp_last_bit_read) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_grp_bgrp_last_bit_read_MASK) | (grp_bgrp_last_bit_read << VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SHIFT) +#define VGT_DEBUG_REG10_SET_last_bit_enable_q(vgt_debug_reg10_reg, last_bit_enable_q) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_bit_enable_q_MASK) | (last_bit_enable_q << VGT_DEBUG_REG10_last_bit_enable_q_SHIFT) +#define VGT_DEBUG_REG10_SET_last_bit_end_di_q(vgt_debug_reg10_reg, last_bit_end_di_q) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_last_bit_end_di_q_MASK) | (last_bit_end_di_q << VGT_DEBUG_REG10_last_bit_end_di_q_SHIFT) +#define VGT_DEBUG_REG10_SET_selected_data(vgt_debug_reg10_reg, selected_data) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_selected_data_MASK) | (selected_data << VGT_DEBUG_REG10_selected_data_SHIFT) +#define VGT_DEBUG_REG10_SET_mask_input_data(vgt_debug_reg10_reg, mask_input_data) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_mask_input_data_MASK) | (mask_input_data << VGT_DEBUG_REG10_mask_input_data_SHIFT) +#define VGT_DEBUG_REG10_SET_gap_q(vgt_debug_reg10_reg, gap_q) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_gap_q_MASK) | (gap_q << VGT_DEBUG_REG10_gap_q_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_mini_reset_z(vgt_debug_reg10_reg, temp_mini_reset_z) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_z_MASK) | (temp_mini_reset_z << VGT_DEBUG_REG10_temp_mini_reset_z_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_mini_reset_y(vgt_debug_reg10_reg, temp_mini_reset_y) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_y_MASK) | (temp_mini_reset_y << VGT_DEBUG_REG10_temp_mini_reset_y_SHIFT) +#define VGT_DEBUG_REG10_SET_temp_mini_reset_x(vgt_debug_reg10_reg, temp_mini_reset_x) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_temp_mini_reset_x_MASK) | (temp_mini_reset_x << VGT_DEBUG_REG10_temp_mini_reset_x_SHIFT) +#define VGT_DEBUG_REG10_SET_grp_trigger(vgt_debug_reg10_reg, grp_trigger) \ + vgt_debug_reg10_reg = (vgt_debug_reg10_reg & ~VGT_DEBUG_REG10_grp_trigger_MASK) | (grp_trigger << VGT_DEBUG_REG10_grp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg10_t { + unsigned int temp_derived_di_prim_type_t0 : VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE; + unsigned int temp_derived_di_small_index_t0 : VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE; + unsigned int temp_derived_di_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE; + unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG10_di_state_sel_q_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG10_last_decr_of_packet_SIZE; + unsigned int bin_valid : VGT_DEBUG_REG10_bin_valid_SIZE; + unsigned int read_block : VGT_DEBUG_REG10_read_block_SIZE; + unsigned int grp_bgrp_last_bit_read : VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE; + unsigned int last_bit_enable_q : VGT_DEBUG_REG10_last_bit_enable_q_SIZE; + unsigned int last_bit_end_di_q : VGT_DEBUG_REG10_last_bit_end_di_q_SIZE; + unsigned int selected_data : VGT_DEBUG_REG10_selected_data_SIZE; + unsigned int mask_input_data : VGT_DEBUG_REG10_mask_input_data_SIZE; + unsigned int gap_q : VGT_DEBUG_REG10_gap_q_SIZE; + unsigned int temp_mini_reset_z : VGT_DEBUG_REG10_temp_mini_reset_z_SIZE; + unsigned int temp_mini_reset_y : VGT_DEBUG_REG10_temp_mini_reset_y_SIZE; + unsigned int temp_mini_reset_x : VGT_DEBUG_REG10_temp_mini_reset_x_SIZE; + unsigned int grp_trigger : VGT_DEBUG_REG10_grp_trigger_SIZE; + } vgt_debug_reg10_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg10_t { + unsigned int grp_trigger : VGT_DEBUG_REG10_grp_trigger_SIZE; + unsigned int temp_mini_reset_x : VGT_DEBUG_REG10_temp_mini_reset_x_SIZE; + unsigned int temp_mini_reset_y : VGT_DEBUG_REG10_temp_mini_reset_y_SIZE; + unsigned int temp_mini_reset_z : VGT_DEBUG_REG10_temp_mini_reset_z_SIZE; + unsigned int gap_q : VGT_DEBUG_REG10_gap_q_SIZE; + unsigned int mask_input_data : VGT_DEBUG_REG10_mask_input_data_SIZE; + unsigned int selected_data : VGT_DEBUG_REG10_selected_data_SIZE; + unsigned int last_bit_end_di_q : VGT_DEBUG_REG10_last_bit_end_di_q_SIZE; + unsigned int last_bit_enable_q : VGT_DEBUG_REG10_last_bit_enable_q_SIZE; + unsigned int grp_bgrp_last_bit_read : VGT_DEBUG_REG10_grp_bgrp_last_bit_read_SIZE; + unsigned int read_block : VGT_DEBUG_REG10_read_block_SIZE; + unsigned int bin_valid : VGT_DEBUG_REG10_bin_valid_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG10_last_decr_of_packet_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG10_di_state_sel_q_SIZE; + unsigned int temp_derived_di_pre_fetch_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_pre_fetch_cull_enable_t0_SIZE; + unsigned int temp_derived_di_cull_enable_t0 : VGT_DEBUG_REG10_temp_derived_di_cull_enable_t0_SIZE; + unsigned int temp_derived_di_small_index_t0 : VGT_DEBUG_REG10_temp_derived_di_small_index_t0_SIZE; + unsigned int temp_derived_di_prim_type_t0 : VGT_DEBUG_REG10_temp_derived_di_prim_type_t0_SIZE; + } vgt_debug_reg10_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg10_t f; +} vgt_debug_reg10_u; + + +/* + * VGT_DEBUG_REG12 struct + */ + +#define VGT_DEBUG_REG12_shifter_byte_count_q_SIZE 5 +#define VGT_DEBUG_REG12_right_word_indx_q_SIZE 5 +#define VGT_DEBUG_REG12_input_data_valid_SIZE 1 +#define VGT_DEBUG_REG12_input_data_xfer_SIZE 1 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE 1 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE 1 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE 1 +#define VGT_DEBUG_REG12_space_avail_from_shift_SIZE 1 +#define VGT_DEBUG_REG12_shifter_first_load_SIZE 1 +#define VGT_DEBUG_REG12_di_state_sel_q_SIZE 1 +#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE 1 +#define VGT_DEBUG_REG12_di_first_group_flag_q_SIZE 1 +#define VGT_DEBUG_REG12_di_event_flag_q_SIZE 1 +#define VGT_DEBUG_REG12_read_draw_initiator_SIZE 1 +#define VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE 1 +#define VGT_DEBUG_REG12_last_shift_of_packet_SIZE 1 +#define VGT_DEBUG_REG12_last_decr_of_packet_SIZE 1 +#define VGT_DEBUG_REG12_extract_vector_SIZE 1 +#define VGT_DEBUG_REG12_shift_vect_rtr_SIZE 1 +#define VGT_DEBUG_REG12_destination_rtr_SIZE 1 +#define VGT_DEBUG_REG12_bgrp_trigger_SIZE 1 + +#define VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT 0 +#define VGT_DEBUG_REG12_right_word_indx_q_SHIFT 5 +#define VGT_DEBUG_REG12_input_data_valid_SHIFT 10 +#define VGT_DEBUG_REG12_input_data_xfer_SHIFT 11 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT 12 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT 13 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT 14 +#define VGT_DEBUG_REG12_space_avail_from_shift_SHIFT 15 +#define VGT_DEBUG_REG12_shifter_first_load_SHIFT 16 +#define VGT_DEBUG_REG12_di_state_sel_q_SHIFT 17 +#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT 18 +#define VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT 19 +#define VGT_DEBUG_REG12_di_event_flag_q_SHIFT 20 +#define VGT_DEBUG_REG12_read_draw_initiator_SHIFT 21 +#define VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT 22 +#define VGT_DEBUG_REG12_last_shift_of_packet_SHIFT 23 +#define VGT_DEBUG_REG12_last_decr_of_packet_SHIFT 24 +#define VGT_DEBUG_REG12_extract_vector_SHIFT 25 +#define VGT_DEBUG_REG12_shift_vect_rtr_SHIFT 26 +#define VGT_DEBUG_REG12_destination_rtr_SHIFT 27 +#define VGT_DEBUG_REG12_bgrp_trigger_SHIFT 28 + +#define VGT_DEBUG_REG12_shifter_byte_count_q_MASK 0x0000001f +#define VGT_DEBUG_REG12_right_word_indx_q_MASK 0x000003e0 +#define VGT_DEBUG_REG12_input_data_valid_MASK 0x00000400 +#define VGT_DEBUG_REG12_input_data_xfer_MASK 0x00000800 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK 0x00001000 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK 0x00002000 +#define VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK 0x00004000 +#define VGT_DEBUG_REG12_space_avail_from_shift_MASK 0x00008000 +#define VGT_DEBUG_REG12_shifter_first_load_MASK 0x00010000 +#define VGT_DEBUG_REG12_di_state_sel_q_MASK 0x00020000 +#define VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK 0x00040000 +#define VGT_DEBUG_REG12_di_first_group_flag_q_MASK 0x00080000 +#define VGT_DEBUG_REG12_di_event_flag_q_MASK 0x00100000 +#define VGT_DEBUG_REG12_read_draw_initiator_MASK 0x00200000 +#define VGT_DEBUG_REG12_loading_di_requires_shifter_MASK 0x00400000 +#define VGT_DEBUG_REG12_last_shift_of_packet_MASK 0x00800000 +#define VGT_DEBUG_REG12_last_decr_of_packet_MASK 0x01000000 +#define VGT_DEBUG_REG12_extract_vector_MASK 0x02000000 +#define VGT_DEBUG_REG12_shift_vect_rtr_MASK 0x04000000 +#define VGT_DEBUG_REG12_destination_rtr_MASK 0x08000000 +#define VGT_DEBUG_REG12_bgrp_trigger_MASK 0x10000000 + +#define VGT_DEBUG_REG12_MASK \ + (VGT_DEBUG_REG12_shifter_byte_count_q_MASK | \ + VGT_DEBUG_REG12_right_word_indx_q_MASK | \ + VGT_DEBUG_REG12_input_data_valid_MASK | \ + VGT_DEBUG_REG12_input_data_xfer_MASK | \ + VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK | \ + VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK | \ + VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK | \ + VGT_DEBUG_REG12_space_avail_from_shift_MASK | \ + VGT_DEBUG_REG12_shifter_first_load_MASK | \ + VGT_DEBUG_REG12_di_state_sel_q_MASK | \ + VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK | \ + VGT_DEBUG_REG12_di_first_group_flag_q_MASK | \ + VGT_DEBUG_REG12_di_event_flag_q_MASK | \ + VGT_DEBUG_REG12_read_draw_initiator_MASK | \ + VGT_DEBUG_REG12_loading_di_requires_shifter_MASK | \ + VGT_DEBUG_REG12_last_shift_of_packet_MASK | \ + VGT_DEBUG_REG12_last_decr_of_packet_MASK | \ + VGT_DEBUG_REG12_extract_vector_MASK | \ + VGT_DEBUG_REG12_shift_vect_rtr_MASK | \ + VGT_DEBUG_REG12_destination_rtr_MASK | \ + VGT_DEBUG_REG12_bgrp_trigger_MASK) + +#define VGT_DEBUG_REG12(shifter_byte_count_q, right_word_indx_q, input_data_valid, input_data_xfer, next_shift_is_vect_1_q, next_shift_is_vect_1_d, next_shift_is_vect_1_pre_d, space_avail_from_shift, shifter_first_load, di_state_sel_q, shifter_waiting_for_first_load_q, di_first_group_flag_q, di_event_flag_q, read_draw_initiator, loading_di_requires_shifter, last_shift_of_packet, last_decr_of_packet, extract_vector, shift_vect_rtr, destination_rtr, bgrp_trigger) \ + ((shifter_byte_count_q << VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT) | \ + (right_word_indx_q << VGT_DEBUG_REG12_right_word_indx_q_SHIFT) | \ + (input_data_valid << VGT_DEBUG_REG12_input_data_valid_SHIFT) | \ + (input_data_xfer << VGT_DEBUG_REG12_input_data_xfer_SHIFT) | \ + (next_shift_is_vect_1_q << VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT) | \ + (next_shift_is_vect_1_d << VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT) | \ + (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT) | \ + (space_avail_from_shift << VGT_DEBUG_REG12_space_avail_from_shift_SHIFT) | \ + (shifter_first_load << VGT_DEBUG_REG12_shifter_first_load_SHIFT) | \ + (di_state_sel_q << VGT_DEBUG_REG12_di_state_sel_q_SHIFT) | \ + (shifter_waiting_for_first_load_q << VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT) | \ + (di_first_group_flag_q << VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT) | \ + (di_event_flag_q << VGT_DEBUG_REG12_di_event_flag_q_SHIFT) | \ + (read_draw_initiator << VGT_DEBUG_REG12_read_draw_initiator_SHIFT) | \ + (loading_di_requires_shifter << VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT) | \ + (last_shift_of_packet << VGT_DEBUG_REG12_last_shift_of_packet_SHIFT) | \ + (last_decr_of_packet << VGT_DEBUG_REG12_last_decr_of_packet_SHIFT) | \ + (extract_vector << VGT_DEBUG_REG12_extract_vector_SHIFT) | \ + (shift_vect_rtr << VGT_DEBUG_REG12_shift_vect_rtr_SHIFT) | \ + (destination_rtr << VGT_DEBUG_REG12_destination_rtr_SHIFT) | \ + (bgrp_trigger << VGT_DEBUG_REG12_bgrp_trigger_SHIFT)) + +#define VGT_DEBUG_REG12_GET_shifter_byte_count_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_byte_count_q_MASK) >> VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT) +#define VGT_DEBUG_REG12_GET_right_word_indx_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_right_word_indx_q_MASK) >> VGT_DEBUG_REG12_right_word_indx_q_SHIFT) +#define VGT_DEBUG_REG12_GET_input_data_valid(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_input_data_valid_MASK) >> VGT_DEBUG_REG12_input_data_valid_SHIFT) +#define VGT_DEBUG_REG12_GET_input_data_xfer(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_input_data_xfer_MASK) >> VGT_DEBUG_REG12_input_data_xfer_SHIFT) +#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT) +#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_d(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT) +#define VGT_DEBUG_REG12_GET_next_shift_is_vect_1_pre_d(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK) >> VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT) +#define VGT_DEBUG_REG12_GET_space_avail_from_shift(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_space_avail_from_shift_MASK) >> VGT_DEBUG_REG12_space_avail_from_shift_SHIFT) +#define VGT_DEBUG_REG12_GET_shifter_first_load(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_first_load_MASK) >> VGT_DEBUG_REG12_shifter_first_load_SHIFT) +#define VGT_DEBUG_REG12_GET_di_state_sel_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_state_sel_q_MASK) >> VGT_DEBUG_REG12_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG12_GET_shifter_waiting_for_first_load_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK) >> VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT) +#define VGT_DEBUG_REG12_GET_di_first_group_flag_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_first_group_flag_q_MASK) >> VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT) +#define VGT_DEBUG_REG12_GET_di_event_flag_q(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_di_event_flag_q_MASK) >> VGT_DEBUG_REG12_di_event_flag_q_SHIFT) +#define VGT_DEBUG_REG12_GET_read_draw_initiator(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_read_draw_initiator_MASK) >> VGT_DEBUG_REG12_read_draw_initiator_SHIFT) +#define VGT_DEBUG_REG12_GET_loading_di_requires_shifter(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_loading_di_requires_shifter_MASK) >> VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT) +#define VGT_DEBUG_REG12_GET_last_shift_of_packet(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_last_shift_of_packet_MASK) >> VGT_DEBUG_REG12_last_shift_of_packet_SHIFT) +#define VGT_DEBUG_REG12_GET_last_decr_of_packet(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_last_decr_of_packet_MASK) >> VGT_DEBUG_REG12_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG12_GET_extract_vector(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_extract_vector_MASK) >> VGT_DEBUG_REG12_extract_vector_SHIFT) +#define VGT_DEBUG_REG12_GET_shift_vect_rtr(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_shift_vect_rtr_MASK) >> VGT_DEBUG_REG12_shift_vect_rtr_SHIFT) +#define VGT_DEBUG_REG12_GET_destination_rtr(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_destination_rtr_MASK) >> VGT_DEBUG_REG12_destination_rtr_SHIFT) +#define VGT_DEBUG_REG12_GET_bgrp_trigger(vgt_debug_reg12) \ + ((vgt_debug_reg12 & VGT_DEBUG_REG12_bgrp_trigger_MASK) >> VGT_DEBUG_REG12_bgrp_trigger_SHIFT) + +#define VGT_DEBUG_REG12_SET_shifter_byte_count_q(vgt_debug_reg12_reg, shifter_byte_count_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_byte_count_q_MASK) | (shifter_byte_count_q << VGT_DEBUG_REG12_shifter_byte_count_q_SHIFT) +#define VGT_DEBUG_REG12_SET_right_word_indx_q(vgt_debug_reg12_reg, right_word_indx_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_right_word_indx_q_MASK) | (right_word_indx_q << VGT_DEBUG_REG12_right_word_indx_q_SHIFT) +#define VGT_DEBUG_REG12_SET_input_data_valid(vgt_debug_reg12_reg, input_data_valid) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_input_data_valid_MASK) | (input_data_valid << VGT_DEBUG_REG12_input_data_valid_SHIFT) +#define VGT_DEBUG_REG12_SET_input_data_xfer(vgt_debug_reg12_reg, input_data_xfer) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_input_data_xfer_MASK) | (input_data_xfer << VGT_DEBUG_REG12_input_data_xfer_SHIFT) +#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_q(vgt_debug_reg12_reg, next_shift_is_vect_1_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_q_MASK) | (next_shift_is_vect_1_q << VGT_DEBUG_REG12_next_shift_is_vect_1_q_SHIFT) +#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_d(vgt_debug_reg12_reg, next_shift_is_vect_1_d) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_d_MASK) | (next_shift_is_vect_1_d << VGT_DEBUG_REG12_next_shift_is_vect_1_d_SHIFT) +#define VGT_DEBUG_REG12_SET_next_shift_is_vect_1_pre_d(vgt_debug_reg12_reg, next_shift_is_vect_1_pre_d) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_MASK) | (next_shift_is_vect_1_pre_d << VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SHIFT) +#define VGT_DEBUG_REG12_SET_space_avail_from_shift(vgt_debug_reg12_reg, space_avail_from_shift) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_space_avail_from_shift_MASK) | (space_avail_from_shift << VGT_DEBUG_REG12_space_avail_from_shift_SHIFT) +#define VGT_DEBUG_REG12_SET_shifter_first_load(vgt_debug_reg12_reg, shifter_first_load) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_first_load_MASK) | (shifter_first_load << VGT_DEBUG_REG12_shifter_first_load_SHIFT) +#define VGT_DEBUG_REG12_SET_di_state_sel_q(vgt_debug_reg12_reg, di_state_sel_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_state_sel_q_MASK) | (di_state_sel_q << VGT_DEBUG_REG12_di_state_sel_q_SHIFT) +#define VGT_DEBUG_REG12_SET_shifter_waiting_for_first_load_q(vgt_debug_reg12_reg, shifter_waiting_for_first_load_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_MASK) | (shifter_waiting_for_first_load_q << VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SHIFT) +#define VGT_DEBUG_REG12_SET_di_first_group_flag_q(vgt_debug_reg12_reg, di_first_group_flag_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_first_group_flag_q_MASK) | (di_first_group_flag_q << VGT_DEBUG_REG12_di_first_group_flag_q_SHIFT) +#define VGT_DEBUG_REG12_SET_di_event_flag_q(vgt_debug_reg12_reg, di_event_flag_q) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_di_event_flag_q_MASK) | (di_event_flag_q << VGT_DEBUG_REG12_di_event_flag_q_SHIFT) +#define VGT_DEBUG_REG12_SET_read_draw_initiator(vgt_debug_reg12_reg, read_draw_initiator) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_read_draw_initiator_MASK) | (read_draw_initiator << VGT_DEBUG_REG12_read_draw_initiator_SHIFT) +#define VGT_DEBUG_REG12_SET_loading_di_requires_shifter(vgt_debug_reg12_reg, loading_di_requires_shifter) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_loading_di_requires_shifter_MASK) | (loading_di_requires_shifter << VGT_DEBUG_REG12_loading_di_requires_shifter_SHIFT) +#define VGT_DEBUG_REG12_SET_last_shift_of_packet(vgt_debug_reg12_reg, last_shift_of_packet) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_last_shift_of_packet_MASK) | (last_shift_of_packet << VGT_DEBUG_REG12_last_shift_of_packet_SHIFT) +#define VGT_DEBUG_REG12_SET_last_decr_of_packet(vgt_debug_reg12_reg, last_decr_of_packet) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_last_decr_of_packet_MASK) | (last_decr_of_packet << VGT_DEBUG_REG12_last_decr_of_packet_SHIFT) +#define VGT_DEBUG_REG12_SET_extract_vector(vgt_debug_reg12_reg, extract_vector) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_extract_vector_MASK) | (extract_vector << VGT_DEBUG_REG12_extract_vector_SHIFT) +#define VGT_DEBUG_REG12_SET_shift_vect_rtr(vgt_debug_reg12_reg, shift_vect_rtr) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_shift_vect_rtr_MASK) | (shift_vect_rtr << VGT_DEBUG_REG12_shift_vect_rtr_SHIFT) +#define VGT_DEBUG_REG12_SET_destination_rtr(vgt_debug_reg12_reg, destination_rtr) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_destination_rtr_MASK) | (destination_rtr << VGT_DEBUG_REG12_destination_rtr_SHIFT) +#define VGT_DEBUG_REG12_SET_bgrp_trigger(vgt_debug_reg12_reg, bgrp_trigger) \ + vgt_debug_reg12_reg = (vgt_debug_reg12_reg & ~VGT_DEBUG_REG12_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG12_bgrp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg12_t { + unsigned int shifter_byte_count_q : VGT_DEBUG_REG12_shifter_byte_count_q_SIZE; + unsigned int right_word_indx_q : VGT_DEBUG_REG12_right_word_indx_q_SIZE; + unsigned int input_data_valid : VGT_DEBUG_REG12_input_data_valid_SIZE; + unsigned int input_data_xfer : VGT_DEBUG_REG12_input_data_xfer_SIZE; + unsigned int next_shift_is_vect_1_q : VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE; + unsigned int next_shift_is_vect_1_d : VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE; + unsigned int next_shift_is_vect_1_pre_d : VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE; + unsigned int space_avail_from_shift : VGT_DEBUG_REG12_space_avail_from_shift_SIZE; + unsigned int shifter_first_load : VGT_DEBUG_REG12_shifter_first_load_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG12_di_state_sel_q_SIZE; + unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE; + unsigned int di_first_group_flag_q : VGT_DEBUG_REG12_di_first_group_flag_q_SIZE; + unsigned int di_event_flag_q : VGT_DEBUG_REG12_di_event_flag_q_SIZE; + unsigned int read_draw_initiator : VGT_DEBUG_REG12_read_draw_initiator_SIZE; + unsigned int loading_di_requires_shifter : VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE; + unsigned int last_shift_of_packet : VGT_DEBUG_REG12_last_shift_of_packet_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG12_last_decr_of_packet_SIZE; + unsigned int extract_vector : VGT_DEBUG_REG12_extract_vector_SIZE; + unsigned int shift_vect_rtr : VGT_DEBUG_REG12_shift_vect_rtr_SIZE; + unsigned int destination_rtr : VGT_DEBUG_REG12_destination_rtr_SIZE; + unsigned int bgrp_trigger : VGT_DEBUG_REG12_bgrp_trigger_SIZE; + unsigned int : 3; + } vgt_debug_reg12_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg12_t { + unsigned int : 3; + unsigned int bgrp_trigger : VGT_DEBUG_REG12_bgrp_trigger_SIZE; + unsigned int destination_rtr : VGT_DEBUG_REG12_destination_rtr_SIZE; + unsigned int shift_vect_rtr : VGT_DEBUG_REG12_shift_vect_rtr_SIZE; + unsigned int extract_vector : VGT_DEBUG_REG12_extract_vector_SIZE; + unsigned int last_decr_of_packet : VGT_DEBUG_REG12_last_decr_of_packet_SIZE; + unsigned int last_shift_of_packet : VGT_DEBUG_REG12_last_shift_of_packet_SIZE; + unsigned int loading_di_requires_shifter : VGT_DEBUG_REG12_loading_di_requires_shifter_SIZE; + unsigned int read_draw_initiator : VGT_DEBUG_REG12_read_draw_initiator_SIZE; + unsigned int di_event_flag_q : VGT_DEBUG_REG12_di_event_flag_q_SIZE; + unsigned int di_first_group_flag_q : VGT_DEBUG_REG12_di_first_group_flag_q_SIZE; + unsigned int shifter_waiting_for_first_load_q : VGT_DEBUG_REG12_shifter_waiting_for_first_load_q_SIZE; + unsigned int di_state_sel_q : VGT_DEBUG_REG12_di_state_sel_q_SIZE; + unsigned int shifter_first_load : VGT_DEBUG_REG12_shifter_first_load_SIZE; + unsigned int space_avail_from_shift : VGT_DEBUG_REG12_space_avail_from_shift_SIZE; + unsigned int next_shift_is_vect_1_pre_d : VGT_DEBUG_REG12_next_shift_is_vect_1_pre_d_SIZE; + unsigned int next_shift_is_vect_1_d : VGT_DEBUG_REG12_next_shift_is_vect_1_d_SIZE; + unsigned int next_shift_is_vect_1_q : VGT_DEBUG_REG12_next_shift_is_vect_1_q_SIZE; + unsigned int input_data_xfer : VGT_DEBUG_REG12_input_data_xfer_SIZE; + unsigned int input_data_valid : VGT_DEBUG_REG12_input_data_valid_SIZE; + unsigned int right_word_indx_q : VGT_DEBUG_REG12_right_word_indx_q_SIZE; + unsigned int shifter_byte_count_q : VGT_DEBUG_REG12_shifter_byte_count_q_SIZE; + } vgt_debug_reg12_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg12_t f; +} vgt_debug_reg12_u; + + +/* + * VGT_DEBUG_REG13 struct + */ + +#define VGT_DEBUG_REG13_di_index_counter_q_SIZE 16 +#define VGT_DEBUG_REG13_shift_amount_no_extract_SIZE 4 +#define VGT_DEBUG_REG13_shift_amount_extract_SIZE 4 +#define VGT_DEBUG_REG13_di_prim_type_q_SIZE 6 +#define VGT_DEBUG_REG13_current_source_sel_SIZE 2 + +#define VGT_DEBUG_REG13_di_index_counter_q_SHIFT 0 +#define VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT 16 +#define VGT_DEBUG_REG13_shift_amount_extract_SHIFT 20 +#define VGT_DEBUG_REG13_di_prim_type_q_SHIFT 24 +#define VGT_DEBUG_REG13_current_source_sel_SHIFT 30 + +#define VGT_DEBUG_REG13_di_index_counter_q_MASK 0x0000ffff +#define VGT_DEBUG_REG13_shift_amount_no_extract_MASK 0x000f0000 +#define VGT_DEBUG_REG13_shift_amount_extract_MASK 0x00f00000 +#define VGT_DEBUG_REG13_di_prim_type_q_MASK 0x3f000000 +#define VGT_DEBUG_REG13_current_source_sel_MASK 0xc0000000 + +#define VGT_DEBUG_REG13_MASK \ + (VGT_DEBUG_REG13_di_index_counter_q_MASK | \ + VGT_DEBUG_REG13_shift_amount_no_extract_MASK | \ + VGT_DEBUG_REG13_shift_amount_extract_MASK | \ + VGT_DEBUG_REG13_di_prim_type_q_MASK | \ + VGT_DEBUG_REG13_current_source_sel_MASK) + +#define VGT_DEBUG_REG13(di_index_counter_q, shift_amount_no_extract, shift_amount_extract, di_prim_type_q, current_source_sel) \ + ((di_index_counter_q << VGT_DEBUG_REG13_di_index_counter_q_SHIFT) | \ + (shift_amount_no_extract << VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT) | \ + (shift_amount_extract << VGT_DEBUG_REG13_shift_amount_extract_SHIFT) | \ + (di_prim_type_q << VGT_DEBUG_REG13_di_prim_type_q_SHIFT) | \ + (current_source_sel << VGT_DEBUG_REG13_current_source_sel_SHIFT)) + +#define VGT_DEBUG_REG13_GET_di_index_counter_q(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_di_index_counter_q_MASK) >> VGT_DEBUG_REG13_di_index_counter_q_SHIFT) +#define VGT_DEBUG_REG13_GET_shift_amount_no_extract(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_shift_amount_no_extract_MASK) >> VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT) +#define VGT_DEBUG_REG13_GET_shift_amount_extract(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_shift_amount_extract_MASK) >> VGT_DEBUG_REG13_shift_amount_extract_SHIFT) +#define VGT_DEBUG_REG13_GET_di_prim_type_q(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_di_prim_type_q_MASK) >> VGT_DEBUG_REG13_di_prim_type_q_SHIFT) +#define VGT_DEBUG_REG13_GET_current_source_sel(vgt_debug_reg13) \ + ((vgt_debug_reg13 & VGT_DEBUG_REG13_current_source_sel_MASK) >> VGT_DEBUG_REG13_current_source_sel_SHIFT) + +#define VGT_DEBUG_REG13_SET_di_index_counter_q(vgt_debug_reg13_reg, di_index_counter_q) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_di_index_counter_q_MASK) | (di_index_counter_q << VGT_DEBUG_REG13_di_index_counter_q_SHIFT) +#define VGT_DEBUG_REG13_SET_shift_amount_no_extract(vgt_debug_reg13_reg, shift_amount_no_extract) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_shift_amount_no_extract_MASK) | (shift_amount_no_extract << VGT_DEBUG_REG13_shift_amount_no_extract_SHIFT) +#define VGT_DEBUG_REG13_SET_shift_amount_extract(vgt_debug_reg13_reg, shift_amount_extract) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_shift_amount_extract_MASK) | (shift_amount_extract << VGT_DEBUG_REG13_shift_amount_extract_SHIFT) +#define VGT_DEBUG_REG13_SET_di_prim_type_q(vgt_debug_reg13_reg, di_prim_type_q) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_di_prim_type_q_MASK) | (di_prim_type_q << VGT_DEBUG_REG13_di_prim_type_q_SHIFT) +#define VGT_DEBUG_REG13_SET_current_source_sel(vgt_debug_reg13_reg, current_source_sel) \ + vgt_debug_reg13_reg = (vgt_debug_reg13_reg & ~VGT_DEBUG_REG13_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG13_current_source_sel_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg13_t { + unsigned int di_index_counter_q : VGT_DEBUG_REG13_di_index_counter_q_SIZE; + unsigned int shift_amount_no_extract : VGT_DEBUG_REG13_shift_amount_no_extract_SIZE; + unsigned int shift_amount_extract : VGT_DEBUG_REG13_shift_amount_extract_SIZE; + unsigned int di_prim_type_q : VGT_DEBUG_REG13_di_prim_type_q_SIZE; + unsigned int current_source_sel : VGT_DEBUG_REG13_current_source_sel_SIZE; + } vgt_debug_reg13_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg13_t { + unsigned int current_source_sel : VGT_DEBUG_REG13_current_source_sel_SIZE; + unsigned int di_prim_type_q : VGT_DEBUG_REG13_di_prim_type_q_SIZE; + unsigned int shift_amount_extract : VGT_DEBUG_REG13_shift_amount_extract_SIZE; + unsigned int shift_amount_no_extract : VGT_DEBUG_REG13_shift_amount_no_extract_SIZE; + unsigned int di_index_counter_q : VGT_DEBUG_REG13_di_index_counter_q_SIZE; + } vgt_debug_reg13_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg13_t f; +} vgt_debug_reg13_u; + + +/* + * VGT_DEBUG_REG14 struct + */ + +#define VGT_DEBUG_REG14_current_source_sel_SIZE 2 +#define VGT_DEBUG_REG14_left_word_indx_q_SIZE 5 +#define VGT_DEBUG_REG14_input_data_cnt_SIZE 5 +#define VGT_DEBUG_REG14_input_data_lsw_SIZE 5 +#define VGT_DEBUG_REG14_input_data_msw_SIZE 5 +#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE 5 +#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE 5 + +#define VGT_DEBUG_REG14_current_source_sel_SHIFT 0 +#define VGT_DEBUG_REG14_left_word_indx_q_SHIFT 2 +#define VGT_DEBUG_REG14_input_data_cnt_SHIFT 7 +#define VGT_DEBUG_REG14_input_data_lsw_SHIFT 12 +#define VGT_DEBUG_REG14_input_data_msw_SHIFT 17 +#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT 22 +#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT 27 + +#define VGT_DEBUG_REG14_current_source_sel_MASK 0x00000003 +#define VGT_DEBUG_REG14_left_word_indx_q_MASK 0x0000007c +#define VGT_DEBUG_REG14_input_data_cnt_MASK 0x00000f80 +#define VGT_DEBUG_REG14_input_data_lsw_MASK 0x0001f000 +#define VGT_DEBUG_REG14_input_data_msw_MASK 0x003e0000 +#define VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK 0x07c00000 +#define VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK 0xf8000000 + +#define VGT_DEBUG_REG14_MASK \ + (VGT_DEBUG_REG14_current_source_sel_MASK | \ + VGT_DEBUG_REG14_left_word_indx_q_MASK | \ + VGT_DEBUG_REG14_input_data_cnt_MASK | \ + VGT_DEBUG_REG14_input_data_lsw_MASK | \ + VGT_DEBUG_REG14_input_data_msw_MASK | \ + VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK | \ + VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) + +#define VGT_DEBUG_REG14(current_source_sel, left_word_indx_q, input_data_cnt, input_data_lsw, input_data_msw, next_small_stride_shift_limit_q, current_small_stride_shift_limit_q) \ + ((current_source_sel << VGT_DEBUG_REG14_current_source_sel_SHIFT) | \ + (left_word_indx_q << VGT_DEBUG_REG14_left_word_indx_q_SHIFT) | \ + (input_data_cnt << VGT_DEBUG_REG14_input_data_cnt_SHIFT) | \ + (input_data_lsw << VGT_DEBUG_REG14_input_data_lsw_SHIFT) | \ + (input_data_msw << VGT_DEBUG_REG14_input_data_msw_SHIFT) | \ + (next_small_stride_shift_limit_q << VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT) | \ + (current_small_stride_shift_limit_q << VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT)) + +#define VGT_DEBUG_REG14_GET_current_source_sel(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_current_source_sel_MASK) >> VGT_DEBUG_REG14_current_source_sel_SHIFT) +#define VGT_DEBUG_REG14_GET_left_word_indx_q(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_left_word_indx_q_MASK) >> VGT_DEBUG_REG14_left_word_indx_q_SHIFT) +#define VGT_DEBUG_REG14_GET_input_data_cnt(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_cnt_MASK) >> VGT_DEBUG_REG14_input_data_cnt_SHIFT) +#define VGT_DEBUG_REG14_GET_input_data_lsw(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_lsw_MASK) >> VGT_DEBUG_REG14_input_data_lsw_SHIFT) +#define VGT_DEBUG_REG14_GET_input_data_msw(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_input_data_msw_MASK) >> VGT_DEBUG_REG14_input_data_msw_SHIFT) +#define VGT_DEBUG_REG14_GET_next_small_stride_shift_limit_q(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT) +#define VGT_DEBUG_REG14_GET_current_small_stride_shift_limit_q(vgt_debug_reg14) \ + ((vgt_debug_reg14 & VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) >> VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT) + +#define VGT_DEBUG_REG14_SET_current_source_sel(vgt_debug_reg14_reg, current_source_sel) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_current_source_sel_MASK) | (current_source_sel << VGT_DEBUG_REG14_current_source_sel_SHIFT) +#define VGT_DEBUG_REG14_SET_left_word_indx_q(vgt_debug_reg14_reg, left_word_indx_q) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_left_word_indx_q_MASK) | (left_word_indx_q << VGT_DEBUG_REG14_left_word_indx_q_SHIFT) +#define VGT_DEBUG_REG14_SET_input_data_cnt(vgt_debug_reg14_reg, input_data_cnt) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_cnt_MASK) | (input_data_cnt << VGT_DEBUG_REG14_input_data_cnt_SHIFT) +#define VGT_DEBUG_REG14_SET_input_data_lsw(vgt_debug_reg14_reg, input_data_lsw) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_lsw_MASK) | (input_data_lsw << VGT_DEBUG_REG14_input_data_lsw_SHIFT) +#define VGT_DEBUG_REG14_SET_input_data_msw(vgt_debug_reg14_reg, input_data_msw) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_input_data_msw_MASK) | (input_data_msw << VGT_DEBUG_REG14_input_data_msw_SHIFT) +#define VGT_DEBUG_REG14_SET_next_small_stride_shift_limit_q(vgt_debug_reg14_reg, next_small_stride_shift_limit_q) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_next_small_stride_shift_limit_q_MASK) | (next_small_stride_shift_limit_q << VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SHIFT) +#define VGT_DEBUG_REG14_SET_current_small_stride_shift_limit_q(vgt_debug_reg14_reg, current_small_stride_shift_limit_q) \ + vgt_debug_reg14_reg = (vgt_debug_reg14_reg & ~VGT_DEBUG_REG14_current_small_stride_shift_limit_q_MASK) | (current_small_stride_shift_limit_q << VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg14_t { + unsigned int current_source_sel : VGT_DEBUG_REG14_current_source_sel_SIZE; + unsigned int left_word_indx_q : VGT_DEBUG_REG14_left_word_indx_q_SIZE; + unsigned int input_data_cnt : VGT_DEBUG_REG14_input_data_cnt_SIZE; + unsigned int input_data_lsw : VGT_DEBUG_REG14_input_data_lsw_SIZE; + unsigned int input_data_msw : VGT_DEBUG_REG14_input_data_msw_SIZE; + unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE; + unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE; + } vgt_debug_reg14_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg14_t { + unsigned int current_small_stride_shift_limit_q : VGT_DEBUG_REG14_current_small_stride_shift_limit_q_SIZE; + unsigned int next_small_stride_shift_limit_q : VGT_DEBUG_REG14_next_small_stride_shift_limit_q_SIZE; + unsigned int input_data_msw : VGT_DEBUG_REG14_input_data_msw_SIZE; + unsigned int input_data_lsw : VGT_DEBUG_REG14_input_data_lsw_SIZE; + unsigned int input_data_cnt : VGT_DEBUG_REG14_input_data_cnt_SIZE; + unsigned int left_word_indx_q : VGT_DEBUG_REG14_left_word_indx_q_SIZE; + unsigned int current_source_sel : VGT_DEBUG_REG14_current_source_sel_SIZE; + } vgt_debug_reg14_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg14_t f; +} vgt_debug_reg14_u; + + +/* + * VGT_DEBUG_REG15 struct + */ + +#define VGT_DEBUG_REG15_next_stride_q_SIZE 5 +#define VGT_DEBUG_REG15_next_stride_d_SIZE 5 +#define VGT_DEBUG_REG15_current_shift_q_SIZE 5 +#define VGT_DEBUG_REG15_current_shift_d_SIZE 5 +#define VGT_DEBUG_REG15_current_stride_q_SIZE 5 +#define VGT_DEBUG_REG15_current_stride_d_SIZE 5 +#define VGT_DEBUG_REG15_bgrp_trigger_SIZE 1 + +#define VGT_DEBUG_REG15_next_stride_q_SHIFT 0 +#define VGT_DEBUG_REG15_next_stride_d_SHIFT 5 +#define VGT_DEBUG_REG15_current_shift_q_SHIFT 10 +#define VGT_DEBUG_REG15_current_shift_d_SHIFT 15 +#define VGT_DEBUG_REG15_current_stride_q_SHIFT 20 +#define VGT_DEBUG_REG15_current_stride_d_SHIFT 25 +#define VGT_DEBUG_REG15_bgrp_trigger_SHIFT 30 + +#define VGT_DEBUG_REG15_next_stride_q_MASK 0x0000001f +#define VGT_DEBUG_REG15_next_stride_d_MASK 0x000003e0 +#define VGT_DEBUG_REG15_current_shift_q_MASK 0x00007c00 +#define VGT_DEBUG_REG15_current_shift_d_MASK 0x000f8000 +#define VGT_DEBUG_REG15_current_stride_q_MASK 0x01f00000 +#define VGT_DEBUG_REG15_current_stride_d_MASK 0x3e000000 +#define VGT_DEBUG_REG15_bgrp_trigger_MASK 0x40000000 + +#define VGT_DEBUG_REG15_MASK \ + (VGT_DEBUG_REG15_next_stride_q_MASK | \ + VGT_DEBUG_REG15_next_stride_d_MASK | \ + VGT_DEBUG_REG15_current_shift_q_MASK | \ + VGT_DEBUG_REG15_current_shift_d_MASK | \ + VGT_DEBUG_REG15_current_stride_q_MASK | \ + VGT_DEBUG_REG15_current_stride_d_MASK | \ + VGT_DEBUG_REG15_bgrp_trigger_MASK) + +#define VGT_DEBUG_REG15(next_stride_q, next_stride_d, current_shift_q, current_shift_d, current_stride_q, current_stride_d, bgrp_trigger) \ + ((next_stride_q << VGT_DEBUG_REG15_next_stride_q_SHIFT) | \ + (next_stride_d << VGT_DEBUG_REG15_next_stride_d_SHIFT) | \ + (current_shift_q << VGT_DEBUG_REG15_current_shift_q_SHIFT) | \ + (current_shift_d << VGT_DEBUG_REG15_current_shift_d_SHIFT) | \ + (current_stride_q << VGT_DEBUG_REG15_current_stride_q_SHIFT) | \ + (current_stride_d << VGT_DEBUG_REG15_current_stride_d_SHIFT) | \ + (bgrp_trigger << VGT_DEBUG_REG15_bgrp_trigger_SHIFT)) + +#define VGT_DEBUG_REG15_GET_next_stride_q(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_next_stride_q_MASK) >> VGT_DEBUG_REG15_next_stride_q_SHIFT) +#define VGT_DEBUG_REG15_GET_next_stride_d(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_next_stride_d_MASK) >> VGT_DEBUG_REG15_next_stride_d_SHIFT) +#define VGT_DEBUG_REG15_GET_current_shift_q(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_shift_q_MASK) >> VGT_DEBUG_REG15_current_shift_q_SHIFT) +#define VGT_DEBUG_REG15_GET_current_shift_d(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_shift_d_MASK) >> VGT_DEBUG_REG15_current_shift_d_SHIFT) +#define VGT_DEBUG_REG15_GET_current_stride_q(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_stride_q_MASK) >> VGT_DEBUG_REG15_current_stride_q_SHIFT) +#define VGT_DEBUG_REG15_GET_current_stride_d(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_current_stride_d_MASK) >> VGT_DEBUG_REG15_current_stride_d_SHIFT) +#define VGT_DEBUG_REG15_GET_bgrp_trigger(vgt_debug_reg15) \ + ((vgt_debug_reg15 & VGT_DEBUG_REG15_bgrp_trigger_MASK) >> VGT_DEBUG_REG15_bgrp_trigger_SHIFT) + +#define VGT_DEBUG_REG15_SET_next_stride_q(vgt_debug_reg15_reg, next_stride_q) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_next_stride_q_MASK) | (next_stride_q << VGT_DEBUG_REG15_next_stride_q_SHIFT) +#define VGT_DEBUG_REG15_SET_next_stride_d(vgt_debug_reg15_reg, next_stride_d) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_next_stride_d_MASK) | (next_stride_d << VGT_DEBUG_REG15_next_stride_d_SHIFT) +#define VGT_DEBUG_REG15_SET_current_shift_q(vgt_debug_reg15_reg, current_shift_q) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_shift_q_MASK) | (current_shift_q << VGT_DEBUG_REG15_current_shift_q_SHIFT) +#define VGT_DEBUG_REG15_SET_current_shift_d(vgt_debug_reg15_reg, current_shift_d) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_shift_d_MASK) | (current_shift_d << VGT_DEBUG_REG15_current_shift_d_SHIFT) +#define VGT_DEBUG_REG15_SET_current_stride_q(vgt_debug_reg15_reg, current_stride_q) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_stride_q_MASK) | (current_stride_q << VGT_DEBUG_REG15_current_stride_q_SHIFT) +#define VGT_DEBUG_REG15_SET_current_stride_d(vgt_debug_reg15_reg, current_stride_d) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_current_stride_d_MASK) | (current_stride_d << VGT_DEBUG_REG15_current_stride_d_SHIFT) +#define VGT_DEBUG_REG15_SET_bgrp_trigger(vgt_debug_reg15_reg, bgrp_trigger) \ + vgt_debug_reg15_reg = (vgt_debug_reg15_reg & ~VGT_DEBUG_REG15_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG15_bgrp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg15_t { + unsigned int next_stride_q : VGT_DEBUG_REG15_next_stride_q_SIZE; + unsigned int next_stride_d : VGT_DEBUG_REG15_next_stride_d_SIZE; + unsigned int current_shift_q : VGT_DEBUG_REG15_current_shift_q_SIZE; + unsigned int current_shift_d : VGT_DEBUG_REG15_current_shift_d_SIZE; + unsigned int current_stride_q : VGT_DEBUG_REG15_current_stride_q_SIZE; + unsigned int current_stride_d : VGT_DEBUG_REG15_current_stride_d_SIZE; + unsigned int bgrp_trigger : VGT_DEBUG_REG15_bgrp_trigger_SIZE; + unsigned int : 1; + } vgt_debug_reg15_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg15_t { + unsigned int : 1; + unsigned int bgrp_trigger : VGT_DEBUG_REG15_bgrp_trigger_SIZE; + unsigned int current_stride_d : VGT_DEBUG_REG15_current_stride_d_SIZE; + unsigned int current_stride_q : VGT_DEBUG_REG15_current_stride_q_SIZE; + unsigned int current_shift_d : VGT_DEBUG_REG15_current_shift_d_SIZE; + unsigned int current_shift_q : VGT_DEBUG_REG15_current_shift_q_SIZE; + unsigned int next_stride_d : VGT_DEBUG_REG15_next_stride_d_SIZE; + unsigned int next_stride_q : VGT_DEBUG_REG15_next_stride_q_SIZE; + } vgt_debug_reg15_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg15_t f; +} vgt_debug_reg15_u; + + +/* + * VGT_DEBUG_REG16 struct + */ + +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE 1 +#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE 1 +#define VGT_DEBUG_REG16_rst_last_bit_SIZE 1 +#define VGT_DEBUG_REG16_current_state_q_SIZE 1 +#define VGT_DEBUG_REG16_old_state_q_SIZE 1 +#define VGT_DEBUG_REG16_old_state_en_SIZE 1 +#define VGT_DEBUG_REG16_prev_last_bit_q_SIZE 1 +#define VGT_DEBUG_REG16_dbl_last_bit_q_SIZE 1 +#define VGT_DEBUG_REG16_last_bit_block_q_SIZE 1 +#define VGT_DEBUG_REG16_ast_bit_block2_q_SIZE 1 +#define VGT_DEBUG_REG16_load_empty_reg_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE 8 +#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE 2 +#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE 1 +#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE 1 +#define VGT_DEBUG_REG16_bgrp_trigger_SIZE 1 + +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT 0 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT 1 +#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT 2 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT 3 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT 4 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT 5 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT 6 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT 7 +#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT 8 +#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT 9 +#define VGT_DEBUG_REG16_rst_last_bit_SHIFT 10 +#define VGT_DEBUG_REG16_current_state_q_SHIFT 11 +#define VGT_DEBUG_REG16_old_state_q_SHIFT 12 +#define VGT_DEBUG_REG16_old_state_en_SHIFT 13 +#define VGT_DEBUG_REG16_prev_last_bit_q_SHIFT 14 +#define VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT 15 +#define VGT_DEBUG_REG16_last_bit_block_q_SHIFT 16 +#define VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT 17 +#define VGT_DEBUG_REG16_load_empty_reg_SHIFT 18 +#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT 19 +#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT 27 +#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT 29 +#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT 30 +#define VGT_DEBUG_REG16_bgrp_trigger_SHIFT 31 + +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK 0x00000001 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK 0x00000002 +#define VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK 0x00000004 +#define VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK 0x00000008 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK 0x00000010 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK 0x00000020 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK 0x00000040 +#define VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK 0x00000080 +#define VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK 0x00000100 +#define VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK 0x00000200 +#define VGT_DEBUG_REG16_rst_last_bit_MASK 0x00000400 +#define VGT_DEBUG_REG16_current_state_q_MASK 0x00000800 +#define VGT_DEBUG_REG16_old_state_q_MASK 0x00001000 +#define VGT_DEBUG_REG16_old_state_en_MASK 0x00002000 +#define VGT_DEBUG_REG16_prev_last_bit_q_MASK 0x00004000 +#define VGT_DEBUG_REG16_dbl_last_bit_q_MASK 0x00008000 +#define VGT_DEBUG_REG16_last_bit_block_q_MASK 0x00010000 +#define VGT_DEBUG_REG16_ast_bit_block2_q_MASK 0x00020000 +#define VGT_DEBUG_REG16_load_empty_reg_MASK 0x00040000 +#define VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK 0x07f80000 +#define VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK 0x18000000 +#define VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK 0x20000000 +#define VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK 0x40000000 +#define VGT_DEBUG_REG16_bgrp_trigger_MASK 0x80000000 + +#define VGT_DEBUG_REG16_MASK \ + (VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK | \ + VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK | \ + VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK | \ + VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK | \ + VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK | \ + VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK | \ + VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK | \ + VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK | \ + VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK | \ + VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK | \ + VGT_DEBUG_REG16_rst_last_bit_MASK | \ + VGT_DEBUG_REG16_current_state_q_MASK | \ + VGT_DEBUG_REG16_old_state_q_MASK | \ + VGT_DEBUG_REG16_old_state_en_MASK | \ + VGT_DEBUG_REG16_prev_last_bit_q_MASK | \ + VGT_DEBUG_REG16_dbl_last_bit_q_MASK | \ + VGT_DEBUG_REG16_last_bit_block_q_MASK | \ + VGT_DEBUG_REG16_ast_bit_block2_q_MASK | \ + VGT_DEBUG_REG16_load_empty_reg_MASK | \ + VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK | \ + VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK | \ + VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK | \ + VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK | \ + VGT_DEBUG_REG16_bgrp_trigger_MASK) + +#define VGT_DEBUG_REG16(bgrp_cull_fetch_fifo_full, bgrp_cull_fetch_fifo_empty, dma_bgrp_cull_fetch_read, bgrp_cull_fetch_fifo_we, bgrp_byte_mask_fifo_full, bgrp_byte_mask_fifo_empty, bgrp_byte_mask_fifo_re_q, bgrp_byte_mask_fifo_we, bgrp_dma_mask_kill, bgrp_grp_bin_valid, rst_last_bit, current_state_q, old_state_q, old_state_en, prev_last_bit_q, dbl_last_bit_q, last_bit_block_q, ast_bit_block2_q, load_empty_reg, bgrp_grp_byte_mask_rdata, dma_bgrp_dma_data_fifo_rptr, top_di_pre_fetch_cull_enable, top_di_grp_cull_enable_q, bgrp_trigger) \ + ((bgrp_cull_fetch_fifo_full << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT) | \ + (bgrp_cull_fetch_fifo_empty << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT) | \ + (dma_bgrp_cull_fetch_read << VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT) | \ + (bgrp_cull_fetch_fifo_we << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT) | \ + (bgrp_byte_mask_fifo_full << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT) | \ + (bgrp_byte_mask_fifo_empty << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT) | \ + (bgrp_byte_mask_fifo_re_q << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT) | \ + (bgrp_byte_mask_fifo_we << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT) | \ + (bgrp_dma_mask_kill << VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT) | \ + (bgrp_grp_bin_valid << VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT) | \ + (rst_last_bit << VGT_DEBUG_REG16_rst_last_bit_SHIFT) | \ + (current_state_q << VGT_DEBUG_REG16_current_state_q_SHIFT) | \ + (old_state_q << VGT_DEBUG_REG16_old_state_q_SHIFT) | \ + (old_state_en << VGT_DEBUG_REG16_old_state_en_SHIFT) | \ + (prev_last_bit_q << VGT_DEBUG_REG16_prev_last_bit_q_SHIFT) | \ + (dbl_last_bit_q << VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT) | \ + (last_bit_block_q << VGT_DEBUG_REG16_last_bit_block_q_SHIFT) | \ + (ast_bit_block2_q << VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT) | \ + (load_empty_reg << VGT_DEBUG_REG16_load_empty_reg_SHIFT) | \ + (bgrp_grp_byte_mask_rdata << VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT) | \ + (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT) | \ + (top_di_pre_fetch_cull_enable << VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT) | \ + (top_di_grp_cull_enable_q << VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT) | \ + (bgrp_trigger << VGT_DEBUG_REG16_bgrp_trigger_SHIFT)) + +#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_full(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_empty(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT) +#define VGT_DEBUG_REG16_GET_dma_bgrp_cull_fetch_read(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK) >> VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_cull_fetch_fifo_we(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK) >> VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_full(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_empty(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_re_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_byte_mask_fifo_we(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK) >> VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_dma_mask_kill(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK) >> VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_grp_bin_valid(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK) >> VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT) +#define VGT_DEBUG_REG16_GET_rst_last_bit(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_rst_last_bit_MASK) >> VGT_DEBUG_REG16_rst_last_bit_SHIFT) +#define VGT_DEBUG_REG16_GET_current_state_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_current_state_q_MASK) >> VGT_DEBUG_REG16_current_state_q_SHIFT) +#define VGT_DEBUG_REG16_GET_old_state_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_old_state_q_MASK) >> VGT_DEBUG_REG16_old_state_q_SHIFT) +#define VGT_DEBUG_REG16_GET_old_state_en(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_old_state_en_MASK) >> VGT_DEBUG_REG16_old_state_en_SHIFT) +#define VGT_DEBUG_REG16_GET_prev_last_bit_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_prev_last_bit_q_MASK) >> VGT_DEBUG_REG16_prev_last_bit_q_SHIFT) +#define VGT_DEBUG_REG16_GET_dbl_last_bit_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_dbl_last_bit_q_MASK) >> VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT) +#define VGT_DEBUG_REG16_GET_last_bit_block_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_last_bit_block_q_MASK) >> VGT_DEBUG_REG16_last_bit_block_q_SHIFT) +#define VGT_DEBUG_REG16_GET_ast_bit_block2_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_ast_bit_block2_q_MASK) >> VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT) +#define VGT_DEBUG_REG16_GET_load_empty_reg(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_load_empty_reg_MASK) >> VGT_DEBUG_REG16_load_empty_reg_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_grp_byte_mask_rdata(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK) >> VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT) +#define VGT_DEBUG_REG16_GET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK) >> VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT) +#define VGT_DEBUG_REG16_GET_top_di_pre_fetch_cull_enable(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK) >> VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT) +#define VGT_DEBUG_REG16_GET_top_di_grp_cull_enable_q(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK) >> VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT) +#define VGT_DEBUG_REG16_GET_bgrp_trigger(vgt_debug_reg16) \ + ((vgt_debug_reg16 & VGT_DEBUG_REG16_bgrp_trigger_MASK) >> VGT_DEBUG_REG16_bgrp_trigger_SHIFT) + +#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_full(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_full) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_MASK) | (bgrp_cull_fetch_fifo_full << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_empty(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_empty) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_MASK) | (bgrp_cull_fetch_fifo_empty << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SHIFT) +#define VGT_DEBUG_REG16_SET_dma_bgrp_cull_fetch_read(vgt_debug_reg16_reg, dma_bgrp_cull_fetch_read) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_MASK) | (dma_bgrp_cull_fetch_read << VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_cull_fetch_fifo_we(vgt_debug_reg16_reg, bgrp_cull_fetch_fifo_we) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_MASK) | (bgrp_cull_fetch_fifo_we << VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_full(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_full) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_MASK) | (bgrp_byte_mask_fifo_full << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_empty(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_empty) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_MASK) | (bgrp_byte_mask_fifo_empty << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_re_q(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_re_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_MASK) | (bgrp_byte_mask_fifo_re_q << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_byte_mask_fifo_we(vgt_debug_reg16_reg, bgrp_byte_mask_fifo_we) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_MASK) | (bgrp_byte_mask_fifo_we << VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_dma_mask_kill(vgt_debug_reg16_reg, bgrp_dma_mask_kill) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_dma_mask_kill_MASK) | (bgrp_dma_mask_kill << VGT_DEBUG_REG16_bgrp_dma_mask_kill_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_grp_bin_valid(vgt_debug_reg16_reg, bgrp_grp_bin_valid) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_grp_bin_valid_MASK) | (bgrp_grp_bin_valid << VGT_DEBUG_REG16_bgrp_grp_bin_valid_SHIFT) +#define VGT_DEBUG_REG16_SET_rst_last_bit(vgt_debug_reg16_reg, rst_last_bit) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_rst_last_bit_MASK) | (rst_last_bit << VGT_DEBUG_REG16_rst_last_bit_SHIFT) +#define VGT_DEBUG_REG16_SET_current_state_q(vgt_debug_reg16_reg, current_state_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_current_state_q_MASK) | (current_state_q << VGT_DEBUG_REG16_current_state_q_SHIFT) +#define VGT_DEBUG_REG16_SET_old_state_q(vgt_debug_reg16_reg, old_state_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_old_state_q_MASK) | (old_state_q << VGT_DEBUG_REG16_old_state_q_SHIFT) +#define VGT_DEBUG_REG16_SET_old_state_en(vgt_debug_reg16_reg, old_state_en) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_old_state_en_MASK) | (old_state_en << VGT_DEBUG_REG16_old_state_en_SHIFT) +#define VGT_DEBUG_REG16_SET_prev_last_bit_q(vgt_debug_reg16_reg, prev_last_bit_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_prev_last_bit_q_MASK) | (prev_last_bit_q << VGT_DEBUG_REG16_prev_last_bit_q_SHIFT) +#define VGT_DEBUG_REG16_SET_dbl_last_bit_q(vgt_debug_reg16_reg, dbl_last_bit_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dbl_last_bit_q_MASK) | (dbl_last_bit_q << VGT_DEBUG_REG16_dbl_last_bit_q_SHIFT) +#define VGT_DEBUG_REG16_SET_last_bit_block_q(vgt_debug_reg16_reg, last_bit_block_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_last_bit_block_q_MASK) | (last_bit_block_q << VGT_DEBUG_REG16_last_bit_block_q_SHIFT) +#define VGT_DEBUG_REG16_SET_ast_bit_block2_q(vgt_debug_reg16_reg, ast_bit_block2_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_ast_bit_block2_q_MASK) | (ast_bit_block2_q << VGT_DEBUG_REG16_ast_bit_block2_q_SHIFT) +#define VGT_DEBUG_REG16_SET_load_empty_reg(vgt_debug_reg16_reg, load_empty_reg) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_load_empty_reg_MASK) | (load_empty_reg << VGT_DEBUG_REG16_load_empty_reg_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_grp_byte_mask_rdata(vgt_debug_reg16_reg, bgrp_grp_byte_mask_rdata) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_MASK) | (bgrp_grp_byte_mask_rdata << VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SHIFT) +#define VGT_DEBUG_REG16_SET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg16_reg, dma_bgrp_dma_data_fifo_rptr) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_MASK) | (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SHIFT) +#define VGT_DEBUG_REG16_SET_top_di_pre_fetch_cull_enable(vgt_debug_reg16_reg, top_di_pre_fetch_cull_enable) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_MASK) | (top_di_pre_fetch_cull_enable << VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SHIFT) +#define VGT_DEBUG_REG16_SET_top_di_grp_cull_enable_q(vgt_debug_reg16_reg, top_di_grp_cull_enable_q) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_top_di_grp_cull_enable_q_MASK) | (top_di_grp_cull_enable_q << VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SHIFT) +#define VGT_DEBUG_REG16_SET_bgrp_trigger(vgt_debug_reg16_reg, bgrp_trigger) \ + vgt_debug_reg16_reg = (vgt_debug_reg16_reg & ~VGT_DEBUG_REG16_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG16_bgrp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg16_t { + unsigned int bgrp_cull_fetch_fifo_full : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE; + unsigned int bgrp_cull_fetch_fifo_empty : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE; + unsigned int dma_bgrp_cull_fetch_read : VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE; + unsigned int bgrp_cull_fetch_fifo_we : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE; + unsigned int bgrp_byte_mask_fifo_full : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE; + unsigned int bgrp_byte_mask_fifo_empty : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE; + unsigned int bgrp_byte_mask_fifo_re_q : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE; + unsigned int bgrp_byte_mask_fifo_we : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE; + unsigned int bgrp_dma_mask_kill : VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE; + unsigned int bgrp_grp_bin_valid : VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE; + unsigned int rst_last_bit : VGT_DEBUG_REG16_rst_last_bit_SIZE; + unsigned int current_state_q : VGT_DEBUG_REG16_current_state_q_SIZE; + unsigned int old_state_q : VGT_DEBUG_REG16_old_state_q_SIZE; + unsigned int old_state_en : VGT_DEBUG_REG16_old_state_en_SIZE; + unsigned int prev_last_bit_q : VGT_DEBUG_REG16_prev_last_bit_q_SIZE; + unsigned int dbl_last_bit_q : VGT_DEBUG_REG16_dbl_last_bit_q_SIZE; + unsigned int last_bit_block_q : VGT_DEBUG_REG16_last_bit_block_q_SIZE; + unsigned int ast_bit_block2_q : VGT_DEBUG_REG16_ast_bit_block2_q_SIZE; + unsigned int load_empty_reg : VGT_DEBUG_REG16_load_empty_reg_SIZE; + unsigned int bgrp_grp_byte_mask_rdata : VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE; + unsigned int dma_bgrp_dma_data_fifo_rptr : VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE; + unsigned int top_di_pre_fetch_cull_enable : VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE; + unsigned int top_di_grp_cull_enable_q : VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE; + unsigned int bgrp_trigger : VGT_DEBUG_REG16_bgrp_trigger_SIZE; + } vgt_debug_reg16_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg16_t { + unsigned int bgrp_trigger : VGT_DEBUG_REG16_bgrp_trigger_SIZE; + unsigned int top_di_grp_cull_enable_q : VGT_DEBUG_REG16_top_di_grp_cull_enable_q_SIZE; + unsigned int top_di_pre_fetch_cull_enable : VGT_DEBUG_REG16_top_di_pre_fetch_cull_enable_SIZE; + unsigned int dma_bgrp_dma_data_fifo_rptr : VGT_DEBUG_REG16_dma_bgrp_dma_data_fifo_rptr_SIZE; + unsigned int bgrp_grp_byte_mask_rdata : VGT_DEBUG_REG16_bgrp_grp_byte_mask_rdata_SIZE; + unsigned int load_empty_reg : VGT_DEBUG_REG16_load_empty_reg_SIZE; + unsigned int ast_bit_block2_q : VGT_DEBUG_REG16_ast_bit_block2_q_SIZE; + unsigned int last_bit_block_q : VGT_DEBUG_REG16_last_bit_block_q_SIZE; + unsigned int dbl_last_bit_q : VGT_DEBUG_REG16_dbl_last_bit_q_SIZE; + unsigned int prev_last_bit_q : VGT_DEBUG_REG16_prev_last_bit_q_SIZE; + unsigned int old_state_en : VGT_DEBUG_REG16_old_state_en_SIZE; + unsigned int old_state_q : VGT_DEBUG_REG16_old_state_q_SIZE; + unsigned int current_state_q : VGT_DEBUG_REG16_current_state_q_SIZE; + unsigned int rst_last_bit : VGT_DEBUG_REG16_rst_last_bit_SIZE; + unsigned int bgrp_grp_bin_valid : VGT_DEBUG_REG16_bgrp_grp_bin_valid_SIZE; + unsigned int bgrp_dma_mask_kill : VGT_DEBUG_REG16_bgrp_dma_mask_kill_SIZE; + unsigned int bgrp_byte_mask_fifo_we : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_we_SIZE; + unsigned int bgrp_byte_mask_fifo_re_q : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_re_q_SIZE; + unsigned int bgrp_byte_mask_fifo_empty : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_empty_SIZE; + unsigned int bgrp_byte_mask_fifo_full : VGT_DEBUG_REG16_bgrp_byte_mask_fifo_full_SIZE; + unsigned int bgrp_cull_fetch_fifo_we : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_we_SIZE; + unsigned int dma_bgrp_cull_fetch_read : VGT_DEBUG_REG16_dma_bgrp_cull_fetch_read_SIZE; + unsigned int bgrp_cull_fetch_fifo_empty : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_empty_SIZE; + unsigned int bgrp_cull_fetch_fifo_full : VGT_DEBUG_REG16_bgrp_cull_fetch_fifo_full_SIZE; + } vgt_debug_reg16_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg16_t f; +} vgt_debug_reg16_u; + + +/* + * VGT_DEBUG_REG17 struct + */ + +#define VGT_DEBUG_REG17_save_read_q_SIZE 1 +#define VGT_DEBUG_REG17_extend_read_q_SIZE 1 +#define VGT_DEBUG_REG17_grp_indx_size_SIZE 2 +#define VGT_DEBUG_REG17_cull_prim_true_SIZE 1 +#define VGT_DEBUG_REG17_reset_bit2_q_SIZE 1 +#define VGT_DEBUG_REG17_reset_bit1_q_SIZE 1 +#define VGT_DEBUG_REG17_first_reg_first_q_SIZE 1 +#define VGT_DEBUG_REG17_check_second_reg_SIZE 1 +#define VGT_DEBUG_REG17_check_first_reg_SIZE 1 +#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE 1 +#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE 1 +#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE 1 +#define VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE 1 +#define VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE 1 +#define VGT_DEBUG_REG17_to_second_reg_q_SIZE 1 +#define VGT_DEBUG_REG17_roll_over_msk_q_SIZE 1 +#define VGT_DEBUG_REG17_max_msk_ptr_q_SIZE 7 +#define VGT_DEBUG_REG17_min_msk_ptr_q_SIZE 7 +#define VGT_DEBUG_REG17_bgrp_trigger_SIZE 1 + +#define VGT_DEBUG_REG17_save_read_q_SHIFT 0 +#define VGT_DEBUG_REG17_extend_read_q_SHIFT 1 +#define VGT_DEBUG_REG17_grp_indx_size_SHIFT 2 +#define VGT_DEBUG_REG17_cull_prim_true_SHIFT 4 +#define VGT_DEBUG_REG17_reset_bit2_q_SHIFT 5 +#define VGT_DEBUG_REG17_reset_bit1_q_SHIFT 6 +#define VGT_DEBUG_REG17_first_reg_first_q_SHIFT 7 +#define VGT_DEBUG_REG17_check_second_reg_SHIFT 8 +#define VGT_DEBUG_REG17_check_first_reg_SHIFT 9 +#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT 10 +#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT 11 +#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT 12 +#define VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT 13 +#define VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT 14 +#define VGT_DEBUG_REG17_to_second_reg_q_SHIFT 15 +#define VGT_DEBUG_REG17_roll_over_msk_q_SHIFT 16 +#define VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT 17 +#define VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT 24 +#define VGT_DEBUG_REG17_bgrp_trigger_SHIFT 31 + +#define VGT_DEBUG_REG17_save_read_q_MASK 0x00000001 +#define VGT_DEBUG_REG17_extend_read_q_MASK 0x00000002 +#define VGT_DEBUG_REG17_grp_indx_size_MASK 0x0000000c +#define VGT_DEBUG_REG17_cull_prim_true_MASK 0x00000010 +#define VGT_DEBUG_REG17_reset_bit2_q_MASK 0x00000020 +#define VGT_DEBUG_REG17_reset_bit1_q_MASK 0x00000040 +#define VGT_DEBUG_REG17_first_reg_first_q_MASK 0x00000080 +#define VGT_DEBUG_REG17_check_second_reg_MASK 0x00000100 +#define VGT_DEBUG_REG17_check_first_reg_MASK 0x00000200 +#define VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK 0x00000400 +#define VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK 0x00000800 +#define VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK 0x00001000 +#define VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK 0x00002000 +#define VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK 0x00004000 +#define VGT_DEBUG_REG17_to_second_reg_q_MASK 0x00008000 +#define VGT_DEBUG_REG17_roll_over_msk_q_MASK 0x00010000 +#define VGT_DEBUG_REG17_max_msk_ptr_q_MASK 0x00fe0000 +#define VGT_DEBUG_REG17_min_msk_ptr_q_MASK 0x7f000000 +#define VGT_DEBUG_REG17_bgrp_trigger_MASK 0x80000000 + +#define VGT_DEBUG_REG17_MASK \ + (VGT_DEBUG_REG17_save_read_q_MASK | \ + VGT_DEBUG_REG17_extend_read_q_MASK | \ + VGT_DEBUG_REG17_grp_indx_size_MASK | \ + VGT_DEBUG_REG17_cull_prim_true_MASK | \ + VGT_DEBUG_REG17_reset_bit2_q_MASK | \ + VGT_DEBUG_REG17_reset_bit1_q_MASK | \ + VGT_DEBUG_REG17_first_reg_first_q_MASK | \ + VGT_DEBUG_REG17_check_second_reg_MASK | \ + VGT_DEBUG_REG17_check_first_reg_MASK | \ + VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK | \ + VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK | \ + VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK | \ + VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK | \ + VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK | \ + VGT_DEBUG_REG17_to_second_reg_q_MASK | \ + VGT_DEBUG_REG17_roll_over_msk_q_MASK | \ + VGT_DEBUG_REG17_max_msk_ptr_q_MASK | \ + VGT_DEBUG_REG17_min_msk_ptr_q_MASK | \ + VGT_DEBUG_REG17_bgrp_trigger_MASK) + +#define VGT_DEBUG_REG17(save_read_q, extend_read_q, grp_indx_size, cull_prim_true, reset_bit2_q, reset_bit1_q, first_reg_first_q, check_second_reg, check_first_reg, bgrp_cull_fetch_fifo_wdata, save_cull_fetch_data2_q, save_cull_fetch_data1_q, save_byte_mask_data2_q, save_byte_mask_data1_q, to_second_reg_q, roll_over_msk_q, max_msk_ptr_q, min_msk_ptr_q, bgrp_trigger) \ + ((save_read_q << VGT_DEBUG_REG17_save_read_q_SHIFT) | \ + (extend_read_q << VGT_DEBUG_REG17_extend_read_q_SHIFT) | \ + (grp_indx_size << VGT_DEBUG_REG17_grp_indx_size_SHIFT) | \ + (cull_prim_true << VGT_DEBUG_REG17_cull_prim_true_SHIFT) | \ + (reset_bit2_q << VGT_DEBUG_REG17_reset_bit2_q_SHIFT) | \ + (reset_bit1_q << VGT_DEBUG_REG17_reset_bit1_q_SHIFT) | \ + (first_reg_first_q << VGT_DEBUG_REG17_first_reg_first_q_SHIFT) | \ + (check_second_reg << VGT_DEBUG_REG17_check_second_reg_SHIFT) | \ + (check_first_reg << VGT_DEBUG_REG17_check_first_reg_SHIFT) | \ + (bgrp_cull_fetch_fifo_wdata << VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT) | \ + (save_cull_fetch_data2_q << VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT) | \ + (save_cull_fetch_data1_q << VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT) | \ + (save_byte_mask_data2_q << VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT) | \ + (save_byte_mask_data1_q << VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT) | \ + (to_second_reg_q << VGT_DEBUG_REG17_to_second_reg_q_SHIFT) | \ + (roll_over_msk_q << VGT_DEBUG_REG17_roll_over_msk_q_SHIFT) | \ + (max_msk_ptr_q << VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT) | \ + (min_msk_ptr_q << VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT) | \ + (bgrp_trigger << VGT_DEBUG_REG17_bgrp_trigger_SHIFT)) + +#define VGT_DEBUG_REG17_GET_save_read_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_read_q_MASK) >> VGT_DEBUG_REG17_save_read_q_SHIFT) +#define VGT_DEBUG_REG17_GET_extend_read_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_extend_read_q_MASK) >> VGT_DEBUG_REG17_extend_read_q_SHIFT) +#define VGT_DEBUG_REG17_GET_grp_indx_size(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_grp_indx_size_MASK) >> VGT_DEBUG_REG17_grp_indx_size_SHIFT) +#define VGT_DEBUG_REG17_GET_cull_prim_true(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_cull_prim_true_MASK) >> VGT_DEBUG_REG17_cull_prim_true_SHIFT) +#define VGT_DEBUG_REG17_GET_reset_bit2_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_reset_bit2_q_MASK) >> VGT_DEBUG_REG17_reset_bit2_q_SHIFT) +#define VGT_DEBUG_REG17_GET_reset_bit1_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_reset_bit1_q_MASK) >> VGT_DEBUG_REG17_reset_bit1_q_SHIFT) +#define VGT_DEBUG_REG17_GET_first_reg_first_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_first_reg_first_q_MASK) >> VGT_DEBUG_REG17_first_reg_first_q_SHIFT) +#define VGT_DEBUG_REG17_GET_check_second_reg(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_check_second_reg_MASK) >> VGT_DEBUG_REG17_check_second_reg_SHIFT) +#define VGT_DEBUG_REG17_GET_check_first_reg(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_check_first_reg_MASK) >> VGT_DEBUG_REG17_check_first_reg_SHIFT) +#define VGT_DEBUG_REG17_GET_bgrp_cull_fetch_fifo_wdata(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK) >> VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT) +#define VGT_DEBUG_REG17_GET_save_cull_fetch_data2_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK) >> VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT) +#define VGT_DEBUG_REG17_GET_save_cull_fetch_data1_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK) >> VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT) +#define VGT_DEBUG_REG17_GET_save_byte_mask_data2_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK) >> VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT) +#define VGT_DEBUG_REG17_GET_save_byte_mask_data1_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK) >> VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT) +#define VGT_DEBUG_REG17_GET_to_second_reg_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_to_second_reg_q_MASK) >> VGT_DEBUG_REG17_to_second_reg_q_SHIFT) +#define VGT_DEBUG_REG17_GET_roll_over_msk_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_roll_over_msk_q_MASK) >> VGT_DEBUG_REG17_roll_over_msk_q_SHIFT) +#define VGT_DEBUG_REG17_GET_max_msk_ptr_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_max_msk_ptr_q_MASK) >> VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT) +#define VGT_DEBUG_REG17_GET_min_msk_ptr_q(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_min_msk_ptr_q_MASK) >> VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT) +#define VGT_DEBUG_REG17_GET_bgrp_trigger(vgt_debug_reg17) \ + ((vgt_debug_reg17 & VGT_DEBUG_REG17_bgrp_trigger_MASK) >> VGT_DEBUG_REG17_bgrp_trigger_SHIFT) + +#define VGT_DEBUG_REG17_SET_save_read_q(vgt_debug_reg17_reg, save_read_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_read_q_MASK) | (save_read_q << VGT_DEBUG_REG17_save_read_q_SHIFT) +#define VGT_DEBUG_REG17_SET_extend_read_q(vgt_debug_reg17_reg, extend_read_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_extend_read_q_MASK) | (extend_read_q << VGT_DEBUG_REG17_extend_read_q_SHIFT) +#define VGT_DEBUG_REG17_SET_grp_indx_size(vgt_debug_reg17_reg, grp_indx_size) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_grp_indx_size_MASK) | (grp_indx_size << VGT_DEBUG_REG17_grp_indx_size_SHIFT) +#define VGT_DEBUG_REG17_SET_cull_prim_true(vgt_debug_reg17_reg, cull_prim_true) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_cull_prim_true_MASK) | (cull_prim_true << VGT_DEBUG_REG17_cull_prim_true_SHIFT) +#define VGT_DEBUG_REG17_SET_reset_bit2_q(vgt_debug_reg17_reg, reset_bit2_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_reset_bit2_q_MASK) | (reset_bit2_q << VGT_DEBUG_REG17_reset_bit2_q_SHIFT) +#define VGT_DEBUG_REG17_SET_reset_bit1_q(vgt_debug_reg17_reg, reset_bit1_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_reset_bit1_q_MASK) | (reset_bit1_q << VGT_DEBUG_REG17_reset_bit1_q_SHIFT) +#define VGT_DEBUG_REG17_SET_first_reg_first_q(vgt_debug_reg17_reg, first_reg_first_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_first_reg_first_q_MASK) | (first_reg_first_q << VGT_DEBUG_REG17_first_reg_first_q_SHIFT) +#define VGT_DEBUG_REG17_SET_check_second_reg(vgt_debug_reg17_reg, check_second_reg) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_check_second_reg_MASK) | (check_second_reg << VGT_DEBUG_REG17_check_second_reg_SHIFT) +#define VGT_DEBUG_REG17_SET_check_first_reg(vgt_debug_reg17_reg, check_first_reg) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_check_first_reg_MASK) | (check_first_reg << VGT_DEBUG_REG17_check_first_reg_SHIFT) +#define VGT_DEBUG_REG17_SET_bgrp_cull_fetch_fifo_wdata(vgt_debug_reg17_reg, bgrp_cull_fetch_fifo_wdata) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_MASK) | (bgrp_cull_fetch_fifo_wdata << VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SHIFT) +#define VGT_DEBUG_REG17_SET_save_cull_fetch_data2_q(vgt_debug_reg17_reg, save_cull_fetch_data2_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_cull_fetch_data2_q_MASK) | (save_cull_fetch_data2_q << VGT_DEBUG_REG17_save_cull_fetch_data2_q_SHIFT) +#define VGT_DEBUG_REG17_SET_save_cull_fetch_data1_q(vgt_debug_reg17_reg, save_cull_fetch_data1_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_cull_fetch_data1_q_MASK) | (save_cull_fetch_data1_q << VGT_DEBUG_REG17_save_cull_fetch_data1_q_SHIFT) +#define VGT_DEBUG_REG17_SET_save_byte_mask_data2_q(vgt_debug_reg17_reg, save_byte_mask_data2_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_byte_mask_data2_q_MASK) | (save_byte_mask_data2_q << VGT_DEBUG_REG17_save_byte_mask_data2_q_SHIFT) +#define VGT_DEBUG_REG17_SET_save_byte_mask_data1_q(vgt_debug_reg17_reg, save_byte_mask_data1_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_save_byte_mask_data1_q_MASK) | (save_byte_mask_data1_q << VGT_DEBUG_REG17_save_byte_mask_data1_q_SHIFT) +#define VGT_DEBUG_REG17_SET_to_second_reg_q(vgt_debug_reg17_reg, to_second_reg_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_to_second_reg_q_MASK) | (to_second_reg_q << VGT_DEBUG_REG17_to_second_reg_q_SHIFT) +#define VGT_DEBUG_REG17_SET_roll_over_msk_q(vgt_debug_reg17_reg, roll_over_msk_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_roll_over_msk_q_MASK) | (roll_over_msk_q << VGT_DEBUG_REG17_roll_over_msk_q_SHIFT) +#define VGT_DEBUG_REG17_SET_max_msk_ptr_q(vgt_debug_reg17_reg, max_msk_ptr_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_max_msk_ptr_q_MASK) | (max_msk_ptr_q << VGT_DEBUG_REG17_max_msk_ptr_q_SHIFT) +#define VGT_DEBUG_REG17_SET_min_msk_ptr_q(vgt_debug_reg17_reg, min_msk_ptr_q) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_min_msk_ptr_q_MASK) | (min_msk_ptr_q << VGT_DEBUG_REG17_min_msk_ptr_q_SHIFT) +#define VGT_DEBUG_REG17_SET_bgrp_trigger(vgt_debug_reg17_reg, bgrp_trigger) \ + vgt_debug_reg17_reg = (vgt_debug_reg17_reg & ~VGT_DEBUG_REG17_bgrp_trigger_MASK) | (bgrp_trigger << VGT_DEBUG_REG17_bgrp_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg17_t { + unsigned int save_read_q : VGT_DEBUG_REG17_save_read_q_SIZE; + unsigned int extend_read_q : VGT_DEBUG_REG17_extend_read_q_SIZE; + unsigned int grp_indx_size : VGT_DEBUG_REG17_grp_indx_size_SIZE; + unsigned int cull_prim_true : VGT_DEBUG_REG17_cull_prim_true_SIZE; + unsigned int reset_bit2_q : VGT_DEBUG_REG17_reset_bit2_q_SIZE; + unsigned int reset_bit1_q : VGT_DEBUG_REG17_reset_bit1_q_SIZE; + unsigned int first_reg_first_q : VGT_DEBUG_REG17_first_reg_first_q_SIZE; + unsigned int check_second_reg : VGT_DEBUG_REG17_check_second_reg_SIZE; + unsigned int check_first_reg : VGT_DEBUG_REG17_check_first_reg_SIZE; + unsigned int bgrp_cull_fetch_fifo_wdata : VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE; + unsigned int save_cull_fetch_data2_q : VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE; + unsigned int save_cull_fetch_data1_q : VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE; + unsigned int save_byte_mask_data2_q : VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE; + unsigned int save_byte_mask_data1_q : VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE; + unsigned int to_second_reg_q : VGT_DEBUG_REG17_to_second_reg_q_SIZE; + unsigned int roll_over_msk_q : VGT_DEBUG_REG17_roll_over_msk_q_SIZE; + unsigned int max_msk_ptr_q : VGT_DEBUG_REG17_max_msk_ptr_q_SIZE; + unsigned int min_msk_ptr_q : VGT_DEBUG_REG17_min_msk_ptr_q_SIZE; + unsigned int bgrp_trigger : VGT_DEBUG_REG17_bgrp_trigger_SIZE; + } vgt_debug_reg17_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg17_t { + unsigned int bgrp_trigger : VGT_DEBUG_REG17_bgrp_trigger_SIZE; + unsigned int min_msk_ptr_q : VGT_DEBUG_REG17_min_msk_ptr_q_SIZE; + unsigned int max_msk_ptr_q : VGT_DEBUG_REG17_max_msk_ptr_q_SIZE; + unsigned int roll_over_msk_q : VGT_DEBUG_REG17_roll_over_msk_q_SIZE; + unsigned int to_second_reg_q : VGT_DEBUG_REG17_to_second_reg_q_SIZE; + unsigned int save_byte_mask_data1_q : VGT_DEBUG_REG17_save_byte_mask_data1_q_SIZE; + unsigned int save_byte_mask_data2_q : VGT_DEBUG_REG17_save_byte_mask_data2_q_SIZE; + unsigned int save_cull_fetch_data1_q : VGT_DEBUG_REG17_save_cull_fetch_data1_q_SIZE; + unsigned int save_cull_fetch_data2_q : VGT_DEBUG_REG17_save_cull_fetch_data2_q_SIZE; + unsigned int bgrp_cull_fetch_fifo_wdata : VGT_DEBUG_REG17_bgrp_cull_fetch_fifo_wdata_SIZE; + unsigned int check_first_reg : VGT_DEBUG_REG17_check_first_reg_SIZE; + unsigned int check_second_reg : VGT_DEBUG_REG17_check_second_reg_SIZE; + unsigned int first_reg_first_q : VGT_DEBUG_REG17_first_reg_first_q_SIZE; + unsigned int reset_bit1_q : VGT_DEBUG_REG17_reset_bit1_q_SIZE; + unsigned int reset_bit2_q : VGT_DEBUG_REG17_reset_bit2_q_SIZE; + unsigned int cull_prim_true : VGT_DEBUG_REG17_cull_prim_true_SIZE; + unsigned int grp_indx_size : VGT_DEBUG_REG17_grp_indx_size_SIZE; + unsigned int extend_read_q : VGT_DEBUG_REG17_extend_read_q_SIZE; + unsigned int save_read_q : VGT_DEBUG_REG17_save_read_q_SIZE; + } vgt_debug_reg17_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg17_t f; +} vgt_debug_reg17_u; + + +/* + * VGT_DEBUG_REG18 struct + */ + +#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE 6 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE 6 +#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE 1 +#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE 2 +#define VGT_DEBUG_REG18_dma_mem_full_SIZE 1 +#define VGT_DEBUG_REG18_dma_ram_re_SIZE 1 +#define VGT_DEBUG_REG18_dma_ram_we_SIZE 1 +#define VGT_DEBUG_REG18_dma_mem_empty_SIZE 1 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE 1 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE 1 +#define VGT_DEBUG_REG18_bin_mem_full_SIZE 1 +#define VGT_DEBUG_REG18_bin_ram_we_SIZE 1 +#define VGT_DEBUG_REG18_bin_ram_re_SIZE 1 +#define VGT_DEBUG_REG18_bin_mem_empty_SIZE 1 +#define VGT_DEBUG_REG18_start_bin_req_SIZE 1 +#define VGT_DEBUG_REG18_fetch_cull_not_used_SIZE 1 +#define VGT_DEBUG_REG18_dma_req_xfer_SIZE 1 +#define VGT_DEBUG_REG18_have_valid_bin_req_SIZE 1 +#define VGT_DEBUG_REG18_have_valid_dma_req_SIZE 1 +#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE 1 +#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE 1 + +#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT 0 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT 6 +#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT 12 +#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT 13 +#define VGT_DEBUG_REG18_dma_mem_full_SHIFT 15 +#define VGT_DEBUG_REG18_dma_ram_re_SHIFT 16 +#define VGT_DEBUG_REG18_dma_ram_we_SHIFT 17 +#define VGT_DEBUG_REG18_dma_mem_empty_SHIFT 18 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT 19 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT 20 +#define VGT_DEBUG_REG18_bin_mem_full_SHIFT 21 +#define VGT_DEBUG_REG18_bin_ram_we_SHIFT 22 +#define VGT_DEBUG_REG18_bin_ram_re_SHIFT 23 +#define VGT_DEBUG_REG18_bin_mem_empty_SHIFT 24 +#define VGT_DEBUG_REG18_start_bin_req_SHIFT 25 +#define VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT 26 +#define VGT_DEBUG_REG18_dma_req_xfer_SHIFT 27 +#define VGT_DEBUG_REG18_have_valid_bin_req_SHIFT 28 +#define VGT_DEBUG_REG18_have_valid_dma_req_SHIFT 29 +#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT 30 +#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT 31 + +#define VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK 0x0000003f +#define VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK 0x00000fc0 +#define VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK 0x00001000 +#define VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK 0x00006000 +#define VGT_DEBUG_REG18_dma_mem_full_MASK 0x00008000 +#define VGT_DEBUG_REG18_dma_ram_re_MASK 0x00010000 +#define VGT_DEBUG_REG18_dma_ram_we_MASK 0x00020000 +#define VGT_DEBUG_REG18_dma_mem_empty_MASK 0x00040000 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK 0x00080000 +#define VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK 0x00100000 +#define VGT_DEBUG_REG18_bin_mem_full_MASK 0x00200000 +#define VGT_DEBUG_REG18_bin_ram_we_MASK 0x00400000 +#define VGT_DEBUG_REG18_bin_ram_re_MASK 0x00800000 +#define VGT_DEBUG_REG18_bin_mem_empty_MASK 0x01000000 +#define VGT_DEBUG_REG18_start_bin_req_MASK 0x02000000 +#define VGT_DEBUG_REG18_fetch_cull_not_used_MASK 0x04000000 +#define VGT_DEBUG_REG18_dma_req_xfer_MASK 0x08000000 +#define VGT_DEBUG_REG18_have_valid_bin_req_MASK 0x10000000 +#define VGT_DEBUG_REG18_have_valid_dma_req_MASK 0x20000000 +#define VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK 0x40000000 +#define VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK 0x80000000 + +#define VGT_DEBUG_REG18_MASK \ + (VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK | \ + VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK | \ + VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK | \ + VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK | \ + VGT_DEBUG_REG18_dma_mem_full_MASK | \ + VGT_DEBUG_REG18_dma_ram_re_MASK | \ + VGT_DEBUG_REG18_dma_ram_we_MASK | \ + VGT_DEBUG_REG18_dma_mem_empty_MASK | \ + VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK | \ + VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK | \ + VGT_DEBUG_REG18_bin_mem_full_MASK | \ + VGT_DEBUG_REG18_bin_ram_we_MASK | \ + VGT_DEBUG_REG18_bin_ram_re_MASK | \ + VGT_DEBUG_REG18_bin_mem_empty_MASK | \ + VGT_DEBUG_REG18_start_bin_req_MASK | \ + VGT_DEBUG_REG18_fetch_cull_not_used_MASK | \ + VGT_DEBUG_REG18_dma_req_xfer_MASK | \ + VGT_DEBUG_REG18_have_valid_bin_req_MASK | \ + VGT_DEBUG_REG18_have_valid_dma_req_MASK | \ + VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK | \ + VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) + +#define VGT_DEBUG_REG18(dma_data_fifo_mem_raddr, dma_data_fifo_mem_waddr, dma_bgrp_byte_mask_fifo_re, dma_bgrp_dma_data_fifo_rptr, dma_mem_full, dma_ram_re, dma_ram_we, dma_mem_empty, dma_data_fifo_mem_re, dma_data_fifo_mem_we, bin_mem_full, bin_ram_we, bin_ram_re, bin_mem_empty, start_bin_req, fetch_cull_not_used, dma_req_xfer, have_valid_bin_req, have_valid_dma_req, bgrp_dma_di_grp_cull_enable, bgrp_dma_di_pre_fetch_cull_enable) \ + ((dma_data_fifo_mem_raddr << VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT) | \ + (dma_data_fifo_mem_waddr << VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT) | \ + (dma_bgrp_byte_mask_fifo_re << VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT) | \ + (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT) | \ + (dma_mem_full << VGT_DEBUG_REG18_dma_mem_full_SHIFT) | \ + (dma_ram_re << VGT_DEBUG_REG18_dma_ram_re_SHIFT) | \ + (dma_ram_we << VGT_DEBUG_REG18_dma_ram_we_SHIFT) | \ + (dma_mem_empty << VGT_DEBUG_REG18_dma_mem_empty_SHIFT) | \ + (dma_data_fifo_mem_re << VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT) | \ + (dma_data_fifo_mem_we << VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT) | \ + (bin_mem_full << VGT_DEBUG_REG18_bin_mem_full_SHIFT) | \ + (bin_ram_we << VGT_DEBUG_REG18_bin_ram_we_SHIFT) | \ + (bin_ram_re << VGT_DEBUG_REG18_bin_ram_re_SHIFT) | \ + (bin_mem_empty << VGT_DEBUG_REG18_bin_mem_empty_SHIFT) | \ + (start_bin_req << VGT_DEBUG_REG18_start_bin_req_SHIFT) | \ + (fetch_cull_not_used << VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT) | \ + (dma_req_xfer << VGT_DEBUG_REG18_dma_req_xfer_SHIFT) | \ + (have_valid_bin_req << VGT_DEBUG_REG18_have_valid_bin_req_SHIFT) | \ + (have_valid_dma_req << VGT_DEBUG_REG18_have_valid_dma_req_SHIFT) | \ + (bgrp_dma_di_grp_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT) | \ + (bgrp_dma_di_pre_fetch_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT)) + +#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_raddr(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_waddr(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_bgrp_byte_mask_fifo_re(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK) >> VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK) >> VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_mem_full(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_mem_full_MASK) >> VGT_DEBUG_REG18_dma_mem_full_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_ram_re(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_ram_re_MASK) >> VGT_DEBUG_REG18_dma_ram_re_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_ram_we(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_ram_we_MASK) >> VGT_DEBUG_REG18_dma_ram_we_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_mem_empty(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_mem_empty_MASK) >> VGT_DEBUG_REG18_dma_mem_empty_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_re(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_data_fifo_mem_we(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK) >> VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT) +#define VGT_DEBUG_REG18_GET_bin_mem_full(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_mem_full_MASK) >> VGT_DEBUG_REG18_bin_mem_full_SHIFT) +#define VGT_DEBUG_REG18_GET_bin_ram_we(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_ram_we_MASK) >> VGT_DEBUG_REG18_bin_ram_we_SHIFT) +#define VGT_DEBUG_REG18_GET_bin_ram_re(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_ram_re_MASK) >> VGT_DEBUG_REG18_bin_ram_re_SHIFT) +#define VGT_DEBUG_REG18_GET_bin_mem_empty(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bin_mem_empty_MASK) >> VGT_DEBUG_REG18_bin_mem_empty_SHIFT) +#define VGT_DEBUG_REG18_GET_start_bin_req(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_start_bin_req_MASK) >> VGT_DEBUG_REG18_start_bin_req_SHIFT) +#define VGT_DEBUG_REG18_GET_fetch_cull_not_used(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_fetch_cull_not_used_MASK) >> VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT) +#define VGT_DEBUG_REG18_GET_dma_req_xfer(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_dma_req_xfer_MASK) >> VGT_DEBUG_REG18_dma_req_xfer_SHIFT) +#define VGT_DEBUG_REG18_GET_have_valid_bin_req(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_have_valid_bin_req_MASK) >> VGT_DEBUG_REG18_have_valid_bin_req_SHIFT) +#define VGT_DEBUG_REG18_GET_have_valid_dma_req(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_have_valid_dma_req_MASK) >> VGT_DEBUG_REG18_have_valid_dma_req_SHIFT) +#define VGT_DEBUG_REG18_GET_bgrp_dma_di_grp_cull_enable(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK) >> VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT) +#define VGT_DEBUG_REG18_GET_bgrp_dma_di_pre_fetch_cull_enable(vgt_debug_reg18) \ + ((vgt_debug_reg18 & VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) >> VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT) + +#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_raddr(vgt_debug_reg18_reg, dma_data_fifo_mem_raddr) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_MASK) | (dma_data_fifo_mem_raddr << VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_waddr(vgt_debug_reg18_reg, dma_data_fifo_mem_waddr) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_MASK) | (dma_data_fifo_mem_waddr << VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_bgrp_byte_mask_fifo_re(vgt_debug_reg18_reg, dma_bgrp_byte_mask_fifo_re) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_MASK) | (dma_bgrp_byte_mask_fifo_re << VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_bgrp_dma_data_fifo_rptr(vgt_debug_reg18_reg, dma_bgrp_dma_data_fifo_rptr) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_MASK) | (dma_bgrp_dma_data_fifo_rptr << VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_mem_full(vgt_debug_reg18_reg, dma_mem_full) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_mem_full_MASK) | (dma_mem_full << VGT_DEBUG_REG18_dma_mem_full_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_ram_re(vgt_debug_reg18_reg, dma_ram_re) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_ram_re_MASK) | (dma_ram_re << VGT_DEBUG_REG18_dma_ram_re_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_ram_we(vgt_debug_reg18_reg, dma_ram_we) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_ram_we_MASK) | (dma_ram_we << VGT_DEBUG_REG18_dma_ram_we_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_mem_empty(vgt_debug_reg18_reg, dma_mem_empty) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_mem_empty_MASK) | (dma_mem_empty << VGT_DEBUG_REG18_dma_mem_empty_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_re(vgt_debug_reg18_reg, dma_data_fifo_mem_re) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_re_MASK) | (dma_data_fifo_mem_re << VGT_DEBUG_REG18_dma_data_fifo_mem_re_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_data_fifo_mem_we(vgt_debug_reg18_reg, dma_data_fifo_mem_we) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_data_fifo_mem_we_MASK) | (dma_data_fifo_mem_we << VGT_DEBUG_REG18_dma_data_fifo_mem_we_SHIFT) +#define VGT_DEBUG_REG18_SET_bin_mem_full(vgt_debug_reg18_reg, bin_mem_full) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_mem_full_MASK) | (bin_mem_full << VGT_DEBUG_REG18_bin_mem_full_SHIFT) +#define VGT_DEBUG_REG18_SET_bin_ram_we(vgt_debug_reg18_reg, bin_ram_we) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_ram_we_MASK) | (bin_ram_we << VGT_DEBUG_REG18_bin_ram_we_SHIFT) +#define VGT_DEBUG_REG18_SET_bin_ram_re(vgt_debug_reg18_reg, bin_ram_re) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_ram_re_MASK) | (bin_ram_re << VGT_DEBUG_REG18_bin_ram_re_SHIFT) +#define VGT_DEBUG_REG18_SET_bin_mem_empty(vgt_debug_reg18_reg, bin_mem_empty) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bin_mem_empty_MASK) | (bin_mem_empty << VGT_DEBUG_REG18_bin_mem_empty_SHIFT) +#define VGT_DEBUG_REG18_SET_start_bin_req(vgt_debug_reg18_reg, start_bin_req) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_start_bin_req_MASK) | (start_bin_req << VGT_DEBUG_REG18_start_bin_req_SHIFT) +#define VGT_DEBUG_REG18_SET_fetch_cull_not_used(vgt_debug_reg18_reg, fetch_cull_not_used) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_fetch_cull_not_used_MASK) | (fetch_cull_not_used << VGT_DEBUG_REG18_fetch_cull_not_used_SHIFT) +#define VGT_DEBUG_REG18_SET_dma_req_xfer(vgt_debug_reg18_reg, dma_req_xfer) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_dma_req_xfer_MASK) | (dma_req_xfer << VGT_DEBUG_REG18_dma_req_xfer_SHIFT) +#define VGT_DEBUG_REG18_SET_have_valid_bin_req(vgt_debug_reg18_reg, have_valid_bin_req) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_have_valid_bin_req_MASK) | (have_valid_bin_req << VGT_DEBUG_REG18_have_valid_bin_req_SHIFT) +#define VGT_DEBUG_REG18_SET_have_valid_dma_req(vgt_debug_reg18_reg, have_valid_dma_req) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_have_valid_dma_req_MASK) | (have_valid_dma_req << VGT_DEBUG_REG18_have_valid_dma_req_SHIFT) +#define VGT_DEBUG_REG18_SET_bgrp_dma_di_grp_cull_enable(vgt_debug_reg18_reg, bgrp_dma_di_grp_cull_enable) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_MASK) | (bgrp_dma_di_grp_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SHIFT) +#define VGT_DEBUG_REG18_SET_bgrp_dma_di_pre_fetch_cull_enable(vgt_debug_reg18_reg, bgrp_dma_di_pre_fetch_cull_enable) \ + vgt_debug_reg18_reg = (vgt_debug_reg18_reg & ~VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_MASK) | (bgrp_dma_di_pre_fetch_cull_enable << VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg18_t { + unsigned int dma_data_fifo_mem_raddr : VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE; + unsigned int dma_data_fifo_mem_waddr : VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE; + unsigned int dma_bgrp_byte_mask_fifo_re : VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE; + unsigned int dma_bgrp_dma_data_fifo_rptr : VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE; + unsigned int dma_mem_full : VGT_DEBUG_REG18_dma_mem_full_SIZE; + unsigned int dma_ram_re : VGT_DEBUG_REG18_dma_ram_re_SIZE; + unsigned int dma_ram_we : VGT_DEBUG_REG18_dma_ram_we_SIZE; + unsigned int dma_mem_empty : VGT_DEBUG_REG18_dma_mem_empty_SIZE; + unsigned int dma_data_fifo_mem_re : VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE; + unsigned int dma_data_fifo_mem_we : VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE; + unsigned int bin_mem_full : VGT_DEBUG_REG18_bin_mem_full_SIZE; + unsigned int bin_ram_we : VGT_DEBUG_REG18_bin_ram_we_SIZE; + unsigned int bin_ram_re : VGT_DEBUG_REG18_bin_ram_re_SIZE; + unsigned int bin_mem_empty : VGT_DEBUG_REG18_bin_mem_empty_SIZE; + unsigned int start_bin_req : VGT_DEBUG_REG18_start_bin_req_SIZE; + unsigned int fetch_cull_not_used : VGT_DEBUG_REG18_fetch_cull_not_used_SIZE; + unsigned int dma_req_xfer : VGT_DEBUG_REG18_dma_req_xfer_SIZE; + unsigned int have_valid_bin_req : VGT_DEBUG_REG18_have_valid_bin_req_SIZE; + unsigned int have_valid_dma_req : VGT_DEBUG_REG18_have_valid_dma_req_SIZE; + unsigned int bgrp_dma_di_grp_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE; + unsigned int bgrp_dma_di_pre_fetch_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE; + } vgt_debug_reg18_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg18_t { + unsigned int bgrp_dma_di_pre_fetch_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_pre_fetch_cull_enable_SIZE; + unsigned int bgrp_dma_di_grp_cull_enable : VGT_DEBUG_REG18_bgrp_dma_di_grp_cull_enable_SIZE; + unsigned int have_valid_dma_req : VGT_DEBUG_REG18_have_valid_dma_req_SIZE; + unsigned int have_valid_bin_req : VGT_DEBUG_REG18_have_valid_bin_req_SIZE; + unsigned int dma_req_xfer : VGT_DEBUG_REG18_dma_req_xfer_SIZE; + unsigned int fetch_cull_not_used : VGT_DEBUG_REG18_fetch_cull_not_used_SIZE; + unsigned int start_bin_req : VGT_DEBUG_REG18_start_bin_req_SIZE; + unsigned int bin_mem_empty : VGT_DEBUG_REG18_bin_mem_empty_SIZE; + unsigned int bin_ram_re : VGT_DEBUG_REG18_bin_ram_re_SIZE; + unsigned int bin_ram_we : VGT_DEBUG_REG18_bin_ram_we_SIZE; + unsigned int bin_mem_full : VGT_DEBUG_REG18_bin_mem_full_SIZE; + unsigned int dma_data_fifo_mem_we : VGT_DEBUG_REG18_dma_data_fifo_mem_we_SIZE; + unsigned int dma_data_fifo_mem_re : VGT_DEBUG_REG18_dma_data_fifo_mem_re_SIZE; + unsigned int dma_mem_empty : VGT_DEBUG_REG18_dma_mem_empty_SIZE; + unsigned int dma_ram_we : VGT_DEBUG_REG18_dma_ram_we_SIZE; + unsigned int dma_ram_re : VGT_DEBUG_REG18_dma_ram_re_SIZE; + unsigned int dma_mem_full : VGT_DEBUG_REG18_dma_mem_full_SIZE; + unsigned int dma_bgrp_dma_data_fifo_rptr : VGT_DEBUG_REG18_dma_bgrp_dma_data_fifo_rptr_SIZE; + unsigned int dma_bgrp_byte_mask_fifo_re : VGT_DEBUG_REG18_dma_bgrp_byte_mask_fifo_re_SIZE; + unsigned int dma_data_fifo_mem_waddr : VGT_DEBUG_REG18_dma_data_fifo_mem_waddr_SIZE; + unsigned int dma_data_fifo_mem_raddr : VGT_DEBUG_REG18_dma_data_fifo_mem_raddr_SIZE; + } vgt_debug_reg18_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg18_t f; +} vgt_debug_reg18_u; + + +/* + * VGT_DEBUG_REG20 struct + */ + +#define VGT_DEBUG_REG20_prim_side_indx_valid_SIZE 1 +#define VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE 1 +#define VGT_DEBUG_REG20_indx_side_fifo_re_SIZE 1 +#define VGT_DEBUG_REG20_indx_side_fifo_we_SIZE 1 +#define VGT_DEBUG_REG20_indx_side_fifo_full_SIZE 1 +#define VGT_DEBUG_REG20_prim_buffer_empty_SIZE 1 +#define VGT_DEBUG_REG20_prim_buffer_re_SIZE 1 +#define VGT_DEBUG_REG20_prim_buffer_we_SIZE 1 +#define VGT_DEBUG_REG20_prim_buffer_full_SIZE 1 +#define VGT_DEBUG_REG20_indx_buffer_empty_SIZE 1 +#define VGT_DEBUG_REG20_indx_buffer_re_SIZE 1 +#define VGT_DEBUG_REG20_indx_buffer_we_SIZE 1 +#define VGT_DEBUG_REG20_indx_buffer_full_SIZE 1 +#define VGT_DEBUG_REG20_hold_prim_SIZE 1 +#define VGT_DEBUG_REG20_sent_cnt_SIZE 4 +#define VGT_DEBUG_REG20_start_of_vtx_vector_SIZE 1 +#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE 1 +#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE 1 +#define VGT_DEBUG_REG20_buffered_prim_type_event_SIZE 5 +#define VGT_DEBUG_REG20_out_trigger_SIZE 1 + +#define VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT 0 +#define VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT 1 +#define VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT 2 +#define VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT 3 +#define VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT 4 +#define VGT_DEBUG_REG20_prim_buffer_empty_SHIFT 5 +#define VGT_DEBUG_REG20_prim_buffer_re_SHIFT 6 +#define VGT_DEBUG_REG20_prim_buffer_we_SHIFT 7 +#define VGT_DEBUG_REG20_prim_buffer_full_SHIFT 8 +#define VGT_DEBUG_REG20_indx_buffer_empty_SHIFT 9 +#define VGT_DEBUG_REG20_indx_buffer_re_SHIFT 10 +#define VGT_DEBUG_REG20_indx_buffer_we_SHIFT 11 +#define VGT_DEBUG_REG20_indx_buffer_full_SHIFT 12 +#define VGT_DEBUG_REG20_hold_prim_SHIFT 13 +#define VGT_DEBUG_REG20_sent_cnt_SHIFT 14 +#define VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT 18 +#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT 19 +#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT 20 +#define VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT 21 +#define VGT_DEBUG_REG20_out_trigger_SHIFT 26 + +#define VGT_DEBUG_REG20_prim_side_indx_valid_MASK 0x00000001 +#define VGT_DEBUG_REG20_indx_side_fifo_empty_MASK 0x00000002 +#define VGT_DEBUG_REG20_indx_side_fifo_re_MASK 0x00000004 +#define VGT_DEBUG_REG20_indx_side_fifo_we_MASK 0x00000008 +#define VGT_DEBUG_REG20_indx_side_fifo_full_MASK 0x00000010 +#define VGT_DEBUG_REG20_prim_buffer_empty_MASK 0x00000020 +#define VGT_DEBUG_REG20_prim_buffer_re_MASK 0x00000040 +#define VGT_DEBUG_REG20_prim_buffer_we_MASK 0x00000080 +#define VGT_DEBUG_REG20_prim_buffer_full_MASK 0x00000100 +#define VGT_DEBUG_REG20_indx_buffer_empty_MASK 0x00000200 +#define VGT_DEBUG_REG20_indx_buffer_re_MASK 0x00000400 +#define VGT_DEBUG_REG20_indx_buffer_we_MASK 0x00000800 +#define VGT_DEBUG_REG20_indx_buffer_full_MASK 0x00001000 +#define VGT_DEBUG_REG20_hold_prim_MASK 0x00002000 +#define VGT_DEBUG_REG20_sent_cnt_MASK 0x0003c000 +#define VGT_DEBUG_REG20_start_of_vtx_vector_MASK 0x00040000 +#define VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK 0x00080000 +#define VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK 0x00100000 +#define VGT_DEBUG_REG20_buffered_prim_type_event_MASK 0x03e00000 +#define VGT_DEBUG_REG20_out_trigger_MASK 0x04000000 + +#define VGT_DEBUG_REG20_MASK \ + (VGT_DEBUG_REG20_prim_side_indx_valid_MASK | \ + VGT_DEBUG_REG20_indx_side_fifo_empty_MASK | \ + VGT_DEBUG_REG20_indx_side_fifo_re_MASK | \ + VGT_DEBUG_REG20_indx_side_fifo_we_MASK | \ + VGT_DEBUG_REG20_indx_side_fifo_full_MASK | \ + VGT_DEBUG_REG20_prim_buffer_empty_MASK | \ + VGT_DEBUG_REG20_prim_buffer_re_MASK | \ + VGT_DEBUG_REG20_prim_buffer_we_MASK | \ + VGT_DEBUG_REG20_prim_buffer_full_MASK | \ + VGT_DEBUG_REG20_indx_buffer_empty_MASK | \ + VGT_DEBUG_REG20_indx_buffer_re_MASK | \ + VGT_DEBUG_REG20_indx_buffer_we_MASK | \ + VGT_DEBUG_REG20_indx_buffer_full_MASK | \ + VGT_DEBUG_REG20_hold_prim_MASK | \ + VGT_DEBUG_REG20_sent_cnt_MASK | \ + VGT_DEBUG_REG20_start_of_vtx_vector_MASK | \ + VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK | \ + VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK | \ + VGT_DEBUG_REG20_buffered_prim_type_event_MASK | \ + VGT_DEBUG_REG20_out_trigger_MASK) + +#define VGT_DEBUG_REG20(prim_side_indx_valid, indx_side_fifo_empty, indx_side_fifo_re, indx_side_fifo_we, indx_side_fifo_full, prim_buffer_empty, prim_buffer_re, prim_buffer_we, prim_buffer_full, indx_buffer_empty, indx_buffer_re, indx_buffer_we, indx_buffer_full, hold_prim, sent_cnt, start_of_vtx_vector, clip_s_pre_hold_prim, clip_p_pre_hold_prim, buffered_prim_type_event, out_trigger) \ + ((prim_side_indx_valid << VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT) | \ + (indx_side_fifo_empty << VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT) | \ + (indx_side_fifo_re << VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT) | \ + (indx_side_fifo_we << VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT) | \ + (indx_side_fifo_full << VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT) | \ + (prim_buffer_empty << VGT_DEBUG_REG20_prim_buffer_empty_SHIFT) | \ + (prim_buffer_re << VGT_DEBUG_REG20_prim_buffer_re_SHIFT) | \ + (prim_buffer_we << VGT_DEBUG_REG20_prim_buffer_we_SHIFT) | \ + (prim_buffer_full << VGT_DEBUG_REG20_prim_buffer_full_SHIFT) | \ + (indx_buffer_empty << VGT_DEBUG_REG20_indx_buffer_empty_SHIFT) | \ + (indx_buffer_re << VGT_DEBUG_REG20_indx_buffer_re_SHIFT) | \ + (indx_buffer_we << VGT_DEBUG_REG20_indx_buffer_we_SHIFT) | \ + (indx_buffer_full << VGT_DEBUG_REG20_indx_buffer_full_SHIFT) | \ + (hold_prim << VGT_DEBUG_REG20_hold_prim_SHIFT) | \ + (sent_cnt << VGT_DEBUG_REG20_sent_cnt_SHIFT) | \ + (start_of_vtx_vector << VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT) | \ + (clip_s_pre_hold_prim << VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT) | \ + (clip_p_pre_hold_prim << VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT) | \ + (buffered_prim_type_event << VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT) | \ + (out_trigger << VGT_DEBUG_REG20_out_trigger_SHIFT)) + +#define VGT_DEBUG_REG20_GET_prim_side_indx_valid(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_side_indx_valid_MASK) >> VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_side_fifo_empty(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_empty_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_side_fifo_re(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_re_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_side_fifo_we(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_we_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_side_fifo_full(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_side_fifo_full_MASK) >> VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT) +#define VGT_DEBUG_REG20_GET_prim_buffer_empty(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_empty_MASK) >> VGT_DEBUG_REG20_prim_buffer_empty_SHIFT) +#define VGT_DEBUG_REG20_GET_prim_buffer_re(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_re_MASK) >> VGT_DEBUG_REG20_prim_buffer_re_SHIFT) +#define VGT_DEBUG_REG20_GET_prim_buffer_we(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_we_MASK) >> VGT_DEBUG_REG20_prim_buffer_we_SHIFT) +#define VGT_DEBUG_REG20_GET_prim_buffer_full(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_prim_buffer_full_MASK) >> VGT_DEBUG_REG20_prim_buffer_full_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_buffer_empty(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_empty_MASK) >> VGT_DEBUG_REG20_indx_buffer_empty_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_buffer_re(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_re_MASK) >> VGT_DEBUG_REG20_indx_buffer_re_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_buffer_we(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_we_MASK) >> VGT_DEBUG_REG20_indx_buffer_we_SHIFT) +#define VGT_DEBUG_REG20_GET_indx_buffer_full(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_indx_buffer_full_MASK) >> VGT_DEBUG_REG20_indx_buffer_full_SHIFT) +#define VGT_DEBUG_REG20_GET_hold_prim(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_hold_prim_MASK) >> VGT_DEBUG_REG20_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_GET_sent_cnt(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_sent_cnt_MASK) >> VGT_DEBUG_REG20_sent_cnt_SHIFT) +#define VGT_DEBUG_REG20_GET_start_of_vtx_vector(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_start_of_vtx_vector_MASK) >> VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT) +#define VGT_DEBUG_REG20_GET_clip_s_pre_hold_prim(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK) >> VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_GET_clip_p_pre_hold_prim(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK) >> VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_GET_buffered_prim_type_event(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_buffered_prim_type_event_MASK) >> VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT) +#define VGT_DEBUG_REG20_GET_out_trigger(vgt_debug_reg20) \ + ((vgt_debug_reg20 & VGT_DEBUG_REG20_out_trigger_MASK) >> VGT_DEBUG_REG20_out_trigger_SHIFT) + +#define VGT_DEBUG_REG20_SET_prim_side_indx_valid(vgt_debug_reg20_reg, prim_side_indx_valid) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_side_indx_valid_MASK) | (prim_side_indx_valid << VGT_DEBUG_REG20_prim_side_indx_valid_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_side_fifo_empty(vgt_debug_reg20_reg, indx_side_fifo_empty) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_empty_MASK) | (indx_side_fifo_empty << VGT_DEBUG_REG20_indx_side_fifo_empty_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_side_fifo_re(vgt_debug_reg20_reg, indx_side_fifo_re) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_re_MASK) | (indx_side_fifo_re << VGT_DEBUG_REG20_indx_side_fifo_re_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_side_fifo_we(vgt_debug_reg20_reg, indx_side_fifo_we) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_we_MASK) | (indx_side_fifo_we << VGT_DEBUG_REG20_indx_side_fifo_we_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_side_fifo_full(vgt_debug_reg20_reg, indx_side_fifo_full) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_side_fifo_full_MASK) | (indx_side_fifo_full << VGT_DEBUG_REG20_indx_side_fifo_full_SHIFT) +#define VGT_DEBUG_REG20_SET_prim_buffer_empty(vgt_debug_reg20_reg, prim_buffer_empty) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_empty_MASK) | (prim_buffer_empty << VGT_DEBUG_REG20_prim_buffer_empty_SHIFT) +#define VGT_DEBUG_REG20_SET_prim_buffer_re(vgt_debug_reg20_reg, prim_buffer_re) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_re_MASK) | (prim_buffer_re << VGT_DEBUG_REG20_prim_buffer_re_SHIFT) +#define VGT_DEBUG_REG20_SET_prim_buffer_we(vgt_debug_reg20_reg, prim_buffer_we) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_we_MASK) | (prim_buffer_we << VGT_DEBUG_REG20_prim_buffer_we_SHIFT) +#define VGT_DEBUG_REG20_SET_prim_buffer_full(vgt_debug_reg20_reg, prim_buffer_full) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_prim_buffer_full_MASK) | (prim_buffer_full << VGT_DEBUG_REG20_prim_buffer_full_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_buffer_empty(vgt_debug_reg20_reg, indx_buffer_empty) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_empty_MASK) | (indx_buffer_empty << VGT_DEBUG_REG20_indx_buffer_empty_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_buffer_re(vgt_debug_reg20_reg, indx_buffer_re) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_re_MASK) | (indx_buffer_re << VGT_DEBUG_REG20_indx_buffer_re_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_buffer_we(vgt_debug_reg20_reg, indx_buffer_we) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_we_MASK) | (indx_buffer_we << VGT_DEBUG_REG20_indx_buffer_we_SHIFT) +#define VGT_DEBUG_REG20_SET_indx_buffer_full(vgt_debug_reg20_reg, indx_buffer_full) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_indx_buffer_full_MASK) | (indx_buffer_full << VGT_DEBUG_REG20_indx_buffer_full_SHIFT) +#define VGT_DEBUG_REG20_SET_hold_prim(vgt_debug_reg20_reg, hold_prim) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_hold_prim_MASK) | (hold_prim << VGT_DEBUG_REG20_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_SET_sent_cnt(vgt_debug_reg20_reg, sent_cnt) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_sent_cnt_MASK) | (sent_cnt << VGT_DEBUG_REG20_sent_cnt_SHIFT) +#define VGT_DEBUG_REG20_SET_start_of_vtx_vector(vgt_debug_reg20_reg, start_of_vtx_vector) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_start_of_vtx_vector_MASK) | (start_of_vtx_vector << VGT_DEBUG_REG20_start_of_vtx_vector_SHIFT) +#define VGT_DEBUG_REG20_SET_clip_s_pre_hold_prim(vgt_debug_reg20_reg, clip_s_pre_hold_prim) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_clip_s_pre_hold_prim_MASK) | (clip_s_pre_hold_prim << VGT_DEBUG_REG20_clip_s_pre_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_SET_clip_p_pre_hold_prim(vgt_debug_reg20_reg, clip_p_pre_hold_prim) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_clip_p_pre_hold_prim_MASK) | (clip_p_pre_hold_prim << VGT_DEBUG_REG20_clip_p_pre_hold_prim_SHIFT) +#define VGT_DEBUG_REG20_SET_buffered_prim_type_event(vgt_debug_reg20_reg, buffered_prim_type_event) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_buffered_prim_type_event_MASK) | (buffered_prim_type_event << VGT_DEBUG_REG20_buffered_prim_type_event_SHIFT) +#define VGT_DEBUG_REG20_SET_out_trigger(vgt_debug_reg20_reg, out_trigger) \ + vgt_debug_reg20_reg = (vgt_debug_reg20_reg & ~VGT_DEBUG_REG20_out_trigger_MASK) | (out_trigger << VGT_DEBUG_REG20_out_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg20_t { + unsigned int prim_side_indx_valid : VGT_DEBUG_REG20_prim_side_indx_valid_SIZE; + unsigned int indx_side_fifo_empty : VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE; + unsigned int indx_side_fifo_re : VGT_DEBUG_REG20_indx_side_fifo_re_SIZE; + unsigned int indx_side_fifo_we : VGT_DEBUG_REG20_indx_side_fifo_we_SIZE; + unsigned int indx_side_fifo_full : VGT_DEBUG_REG20_indx_side_fifo_full_SIZE; + unsigned int prim_buffer_empty : VGT_DEBUG_REG20_prim_buffer_empty_SIZE; + unsigned int prim_buffer_re : VGT_DEBUG_REG20_prim_buffer_re_SIZE; + unsigned int prim_buffer_we : VGT_DEBUG_REG20_prim_buffer_we_SIZE; + unsigned int prim_buffer_full : VGT_DEBUG_REG20_prim_buffer_full_SIZE; + unsigned int indx_buffer_empty : VGT_DEBUG_REG20_indx_buffer_empty_SIZE; + unsigned int indx_buffer_re : VGT_DEBUG_REG20_indx_buffer_re_SIZE; + unsigned int indx_buffer_we : VGT_DEBUG_REG20_indx_buffer_we_SIZE; + unsigned int indx_buffer_full : VGT_DEBUG_REG20_indx_buffer_full_SIZE; + unsigned int hold_prim : VGT_DEBUG_REG20_hold_prim_SIZE; + unsigned int sent_cnt : VGT_DEBUG_REG20_sent_cnt_SIZE; + unsigned int start_of_vtx_vector : VGT_DEBUG_REG20_start_of_vtx_vector_SIZE; + unsigned int clip_s_pre_hold_prim : VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE; + unsigned int clip_p_pre_hold_prim : VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE; + unsigned int buffered_prim_type_event : VGT_DEBUG_REG20_buffered_prim_type_event_SIZE; + unsigned int out_trigger : VGT_DEBUG_REG20_out_trigger_SIZE; + unsigned int : 5; + } vgt_debug_reg20_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg20_t { + unsigned int : 5; + unsigned int out_trigger : VGT_DEBUG_REG20_out_trigger_SIZE; + unsigned int buffered_prim_type_event : VGT_DEBUG_REG20_buffered_prim_type_event_SIZE; + unsigned int clip_p_pre_hold_prim : VGT_DEBUG_REG20_clip_p_pre_hold_prim_SIZE; + unsigned int clip_s_pre_hold_prim : VGT_DEBUG_REG20_clip_s_pre_hold_prim_SIZE; + unsigned int start_of_vtx_vector : VGT_DEBUG_REG20_start_of_vtx_vector_SIZE; + unsigned int sent_cnt : VGT_DEBUG_REG20_sent_cnt_SIZE; + unsigned int hold_prim : VGT_DEBUG_REG20_hold_prim_SIZE; + unsigned int indx_buffer_full : VGT_DEBUG_REG20_indx_buffer_full_SIZE; + unsigned int indx_buffer_we : VGT_DEBUG_REG20_indx_buffer_we_SIZE; + unsigned int indx_buffer_re : VGT_DEBUG_REG20_indx_buffer_re_SIZE; + unsigned int indx_buffer_empty : VGT_DEBUG_REG20_indx_buffer_empty_SIZE; + unsigned int prim_buffer_full : VGT_DEBUG_REG20_prim_buffer_full_SIZE; + unsigned int prim_buffer_we : VGT_DEBUG_REG20_prim_buffer_we_SIZE; + unsigned int prim_buffer_re : VGT_DEBUG_REG20_prim_buffer_re_SIZE; + unsigned int prim_buffer_empty : VGT_DEBUG_REG20_prim_buffer_empty_SIZE; + unsigned int indx_side_fifo_full : VGT_DEBUG_REG20_indx_side_fifo_full_SIZE; + unsigned int indx_side_fifo_we : VGT_DEBUG_REG20_indx_side_fifo_we_SIZE; + unsigned int indx_side_fifo_re : VGT_DEBUG_REG20_indx_side_fifo_re_SIZE; + unsigned int indx_side_fifo_empty : VGT_DEBUG_REG20_indx_side_fifo_empty_SIZE; + unsigned int prim_side_indx_valid : VGT_DEBUG_REG20_prim_side_indx_valid_SIZE; + } vgt_debug_reg20_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg20_t f; +} vgt_debug_reg20_u; + + +/* + * VGT_DEBUG_REG21 struct + */ + +#define VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE 1 +#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE 3 +#define VGT_DEBUG_REG21_alloc_counter_q_SIZE 3 +#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE 3 +#define VGT_DEBUG_REG21_int_vtx_counter_q_SIZE 4 +#define VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE 4 +#define VGT_DEBUG_REG21_new_packet_q_SIZE 1 +#define VGT_DEBUG_REG21_new_allocate_q_SIZE 1 +#define VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE 2 +#define VGT_DEBUG_REG21_inserted_null_prim_q_SIZE 1 +#define VGT_DEBUG_REG21_insert_null_prim_SIZE 1 +#define VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE 1 +#define VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE 1 +#define VGT_DEBUG_REG21_buffered_thread_size_SIZE 1 +#define VGT_DEBUG_REG21_out_trigger_SIZE 1 + +#define VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT 0 +#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT 1 +#define VGT_DEBUG_REG21_alloc_counter_q_SHIFT 4 +#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT 7 +#define VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT 10 +#define VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT 14 +#define VGT_DEBUG_REG21_new_packet_q_SHIFT 18 +#define VGT_DEBUG_REG21_new_allocate_q_SHIFT 19 +#define VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT 20 +#define VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT 22 +#define VGT_DEBUG_REG21_insert_null_prim_SHIFT 23 +#define VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT 24 +#define VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT 25 +#define VGT_DEBUG_REG21_buffered_thread_size_SHIFT 26 +#define VGT_DEBUG_REG21_out_trigger_SHIFT 31 + +#define VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK 0x00000001 +#define VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK 0x0000000e +#define VGT_DEBUG_REG21_alloc_counter_q_MASK 0x00000070 +#define VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK 0x00000380 +#define VGT_DEBUG_REG21_int_vtx_counter_q_MASK 0x00003c00 +#define VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK 0x0003c000 +#define VGT_DEBUG_REG21_new_packet_q_MASK 0x00040000 +#define VGT_DEBUG_REG21_new_allocate_q_MASK 0x00080000 +#define VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK 0x00300000 +#define VGT_DEBUG_REG21_inserted_null_prim_q_MASK 0x00400000 +#define VGT_DEBUG_REG21_insert_null_prim_MASK 0x00800000 +#define VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK 0x01000000 +#define VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK 0x02000000 +#define VGT_DEBUG_REG21_buffered_thread_size_MASK 0x04000000 +#define VGT_DEBUG_REG21_out_trigger_MASK 0x80000000 + +#define VGT_DEBUG_REG21_MASK \ + (VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK | \ + VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK | \ + VGT_DEBUG_REG21_alloc_counter_q_MASK | \ + VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK | \ + VGT_DEBUG_REG21_int_vtx_counter_q_MASK | \ + VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK | \ + VGT_DEBUG_REG21_new_packet_q_MASK | \ + VGT_DEBUG_REG21_new_allocate_q_MASK | \ + VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK | \ + VGT_DEBUG_REG21_inserted_null_prim_q_MASK | \ + VGT_DEBUG_REG21_insert_null_prim_MASK | \ + VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK | \ + VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK | \ + VGT_DEBUG_REG21_buffered_thread_size_MASK | \ + VGT_DEBUG_REG21_out_trigger_MASK) + +#define VGT_DEBUG_REG21(null_terminate_vtx_vector, prim_end_of_vtx_vect_flags, alloc_counter_q, curr_slot_in_vtx_vect_q, int_vtx_counter_q, curr_dealloc_distance_q, new_packet_q, new_allocate_q, num_new_unique_rel_indx, inserted_null_prim_q, insert_null_prim, buffered_prim_eop_mux, prim_buffer_empty_mux, buffered_thread_size, out_trigger) \ + ((null_terminate_vtx_vector << VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT) | \ + (prim_end_of_vtx_vect_flags << VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT) | \ + (alloc_counter_q << VGT_DEBUG_REG21_alloc_counter_q_SHIFT) | \ + (curr_slot_in_vtx_vect_q << VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT) | \ + (int_vtx_counter_q << VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT) | \ + (curr_dealloc_distance_q << VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT) | \ + (new_packet_q << VGT_DEBUG_REG21_new_packet_q_SHIFT) | \ + (new_allocate_q << VGT_DEBUG_REG21_new_allocate_q_SHIFT) | \ + (num_new_unique_rel_indx << VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT) | \ + (inserted_null_prim_q << VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT) | \ + (insert_null_prim << VGT_DEBUG_REG21_insert_null_prim_SHIFT) | \ + (buffered_prim_eop_mux << VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT) | \ + (prim_buffer_empty_mux << VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT) | \ + (buffered_thread_size << VGT_DEBUG_REG21_buffered_thread_size_SHIFT) | \ + (out_trigger << VGT_DEBUG_REG21_out_trigger_SHIFT)) + +#define VGT_DEBUG_REG21_GET_null_terminate_vtx_vector(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK) >> VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT) +#define VGT_DEBUG_REG21_GET_prim_end_of_vtx_vect_flags(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK) >> VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT) +#define VGT_DEBUG_REG21_GET_alloc_counter_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_alloc_counter_q_MASK) >> VGT_DEBUG_REG21_alloc_counter_q_SHIFT) +#define VGT_DEBUG_REG21_GET_curr_slot_in_vtx_vect_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK) >> VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT) +#define VGT_DEBUG_REG21_GET_int_vtx_counter_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_int_vtx_counter_q_MASK) >> VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT) +#define VGT_DEBUG_REG21_GET_curr_dealloc_distance_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK) >> VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT) +#define VGT_DEBUG_REG21_GET_new_packet_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_new_packet_q_MASK) >> VGT_DEBUG_REG21_new_packet_q_SHIFT) +#define VGT_DEBUG_REG21_GET_new_allocate_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_new_allocate_q_MASK) >> VGT_DEBUG_REG21_new_allocate_q_SHIFT) +#define VGT_DEBUG_REG21_GET_num_new_unique_rel_indx(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK) >> VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT) +#define VGT_DEBUG_REG21_GET_inserted_null_prim_q(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_inserted_null_prim_q_MASK) >> VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT) +#define VGT_DEBUG_REG21_GET_insert_null_prim(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_insert_null_prim_MASK) >> VGT_DEBUG_REG21_insert_null_prim_SHIFT) +#define VGT_DEBUG_REG21_GET_buffered_prim_eop_mux(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK) >> VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT) +#define VGT_DEBUG_REG21_GET_prim_buffer_empty_mux(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK) >> VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT) +#define VGT_DEBUG_REG21_GET_buffered_thread_size(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_buffered_thread_size_MASK) >> VGT_DEBUG_REG21_buffered_thread_size_SHIFT) +#define VGT_DEBUG_REG21_GET_out_trigger(vgt_debug_reg21) \ + ((vgt_debug_reg21 & VGT_DEBUG_REG21_out_trigger_MASK) >> VGT_DEBUG_REG21_out_trigger_SHIFT) + +#define VGT_DEBUG_REG21_SET_null_terminate_vtx_vector(vgt_debug_reg21_reg, null_terminate_vtx_vector) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_null_terminate_vtx_vector_MASK) | (null_terminate_vtx_vector << VGT_DEBUG_REG21_null_terminate_vtx_vector_SHIFT) +#define VGT_DEBUG_REG21_SET_prim_end_of_vtx_vect_flags(vgt_debug_reg21_reg, prim_end_of_vtx_vect_flags) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_MASK) | (prim_end_of_vtx_vect_flags << VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SHIFT) +#define VGT_DEBUG_REG21_SET_alloc_counter_q(vgt_debug_reg21_reg, alloc_counter_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_alloc_counter_q_MASK) | (alloc_counter_q << VGT_DEBUG_REG21_alloc_counter_q_SHIFT) +#define VGT_DEBUG_REG21_SET_curr_slot_in_vtx_vect_q(vgt_debug_reg21_reg, curr_slot_in_vtx_vect_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_MASK) | (curr_slot_in_vtx_vect_q << VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SHIFT) +#define VGT_DEBUG_REG21_SET_int_vtx_counter_q(vgt_debug_reg21_reg, int_vtx_counter_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_int_vtx_counter_q_MASK) | (int_vtx_counter_q << VGT_DEBUG_REG21_int_vtx_counter_q_SHIFT) +#define VGT_DEBUG_REG21_SET_curr_dealloc_distance_q(vgt_debug_reg21_reg, curr_dealloc_distance_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_curr_dealloc_distance_q_MASK) | (curr_dealloc_distance_q << VGT_DEBUG_REG21_curr_dealloc_distance_q_SHIFT) +#define VGT_DEBUG_REG21_SET_new_packet_q(vgt_debug_reg21_reg, new_packet_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_new_packet_q_MASK) | (new_packet_q << VGT_DEBUG_REG21_new_packet_q_SHIFT) +#define VGT_DEBUG_REG21_SET_new_allocate_q(vgt_debug_reg21_reg, new_allocate_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_new_allocate_q_MASK) | (new_allocate_q << VGT_DEBUG_REG21_new_allocate_q_SHIFT) +#define VGT_DEBUG_REG21_SET_num_new_unique_rel_indx(vgt_debug_reg21_reg, num_new_unique_rel_indx) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_num_new_unique_rel_indx_MASK) | (num_new_unique_rel_indx << VGT_DEBUG_REG21_num_new_unique_rel_indx_SHIFT) +#define VGT_DEBUG_REG21_SET_inserted_null_prim_q(vgt_debug_reg21_reg, inserted_null_prim_q) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_inserted_null_prim_q_MASK) | (inserted_null_prim_q << VGT_DEBUG_REG21_inserted_null_prim_q_SHIFT) +#define VGT_DEBUG_REG21_SET_insert_null_prim(vgt_debug_reg21_reg, insert_null_prim) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_insert_null_prim_MASK) | (insert_null_prim << VGT_DEBUG_REG21_insert_null_prim_SHIFT) +#define VGT_DEBUG_REG21_SET_buffered_prim_eop_mux(vgt_debug_reg21_reg, buffered_prim_eop_mux) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_buffered_prim_eop_mux_MASK) | (buffered_prim_eop_mux << VGT_DEBUG_REG21_buffered_prim_eop_mux_SHIFT) +#define VGT_DEBUG_REG21_SET_prim_buffer_empty_mux(vgt_debug_reg21_reg, prim_buffer_empty_mux) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_prim_buffer_empty_mux_MASK) | (prim_buffer_empty_mux << VGT_DEBUG_REG21_prim_buffer_empty_mux_SHIFT) +#define VGT_DEBUG_REG21_SET_buffered_thread_size(vgt_debug_reg21_reg, buffered_thread_size) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_buffered_thread_size_MASK) | (buffered_thread_size << VGT_DEBUG_REG21_buffered_thread_size_SHIFT) +#define VGT_DEBUG_REG21_SET_out_trigger(vgt_debug_reg21_reg, out_trigger) \ + vgt_debug_reg21_reg = (vgt_debug_reg21_reg & ~VGT_DEBUG_REG21_out_trigger_MASK) | (out_trigger << VGT_DEBUG_REG21_out_trigger_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_debug_reg21_t { + unsigned int null_terminate_vtx_vector : VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE; + unsigned int prim_end_of_vtx_vect_flags : VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE; + unsigned int alloc_counter_q : VGT_DEBUG_REG21_alloc_counter_q_SIZE; + unsigned int curr_slot_in_vtx_vect_q : VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE; + unsigned int int_vtx_counter_q : VGT_DEBUG_REG21_int_vtx_counter_q_SIZE; + unsigned int curr_dealloc_distance_q : VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE; + unsigned int new_packet_q : VGT_DEBUG_REG21_new_packet_q_SIZE; + unsigned int new_allocate_q : VGT_DEBUG_REG21_new_allocate_q_SIZE; + unsigned int num_new_unique_rel_indx : VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE; + unsigned int inserted_null_prim_q : VGT_DEBUG_REG21_inserted_null_prim_q_SIZE; + unsigned int insert_null_prim : VGT_DEBUG_REG21_insert_null_prim_SIZE; + unsigned int buffered_prim_eop_mux : VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE; + unsigned int prim_buffer_empty_mux : VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE; + unsigned int buffered_thread_size : VGT_DEBUG_REG21_buffered_thread_size_SIZE; + unsigned int : 4; + unsigned int out_trigger : VGT_DEBUG_REG21_out_trigger_SIZE; + } vgt_debug_reg21_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_debug_reg21_t { + unsigned int out_trigger : VGT_DEBUG_REG21_out_trigger_SIZE; + unsigned int : 4; + unsigned int buffered_thread_size : VGT_DEBUG_REG21_buffered_thread_size_SIZE; + unsigned int prim_buffer_empty_mux : VGT_DEBUG_REG21_prim_buffer_empty_mux_SIZE; + unsigned int buffered_prim_eop_mux : VGT_DEBUG_REG21_buffered_prim_eop_mux_SIZE; + unsigned int insert_null_prim : VGT_DEBUG_REG21_insert_null_prim_SIZE; + unsigned int inserted_null_prim_q : VGT_DEBUG_REG21_inserted_null_prim_q_SIZE; + unsigned int num_new_unique_rel_indx : VGT_DEBUG_REG21_num_new_unique_rel_indx_SIZE; + unsigned int new_allocate_q : VGT_DEBUG_REG21_new_allocate_q_SIZE; + unsigned int new_packet_q : VGT_DEBUG_REG21_new_packet_q_SIZE; + unsigned int curr_dealloc_distance_q : VGT_DEBUG_REG21_curr_dealloc_distance_q_SIZE; + unsigned int int_vtx_counter_q : VGT_DEBUG_REG21_int_vtx_counter_q_SIZE; + unsigned int curr_slot_in_vtx_vect_q : VGT_DEBUG_REG21_curr_slot_in_vtx_vect_q_SIZE; + unsigned int alloc_counter_q : VGT_DEBUG_REG21_alloc_counter_q_SIZE; + unsigned int prim_end_of_vtx_vect_flags : VGT_DEBUG_REG21_prim_end_of_vtx_vect_flags_SIZE; + unsigned int null_terminate_vtx_vector : VGT_DEBUG_REG21_null_terminate_vtx_vector_SIZE; + } vgt_debug_reg21_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_debug_reg21_t f; +} vgt_debug_reg21_u; + + +/* + * VGT_CRC_SQ_DATA struct + */ + +#define VGT_CRC_SQ_DATA_CRC_SIZE 32 + +#define VGT_CRC_SQ_DATA_CRC_SHIFT 0 + +#define VGT_CRC_SQ_DATA_CRC_MASK 0xffffffff + +#define VGT_CRC_SQ_DATA_MASK \ + (VGT_CRC_SQ_DATA_CRC_MASK) + +#define VGT_CRC_SQ_DATA(crc) \ + ((crc << VGT_CRC_SQ_DATA_CRC_SHIFT)) + +#define VGT_CRC_SQ_DATA_GET_CRC(vgt_crc_sq_data) \ + ((vgt_crc_sq_data & VGT_CRC_SQ_DATA_CRC_MASK) >> VGT_CRC_SQ_DATA_CRC_SHIFT) + +#define VGT_CRC_SQ_DATA_SET_CRC(vgt_crc_sq_data_reg, crc) \ + vgt_crc_sq_data_reg = (vgt_crc_sq_data_reg & ~VGT_CRC_SQ_DATA_CRC_MASK) | (crc << VGT_CRC_SQ_DATA_CRC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_crc_sq_data_t { + unsigned int crc : VGT_CRC_SQ_DATA_CRC_SIZE; + } vgt_crc_sq_data_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_crc_sq_data_t { + unsigned int crc : VGT_CRC_SQ_DATA_CRC_SIZE; + } vgt_crc_sq_data_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_crc_sq_data_t f; +} vgt_crc_sq_data_u; + + +/* + * VGT_CRC_SQ_CTRL struct + */ + +#define VGT_CRC_SQ_CTRL_CRC_SIZE 32 + +#define VGT_CRC_SQ_CTRL_CRC_SHIFT 0 + +#define VGT_CRC_SQ_CTRL_CRC_MASK 0xffffffff + +#define VGT_CRC_SQ_CTRL_MASK \ + (VGT_CRC_SQ_CTRL_CRC_MASK) + +#define VGT_CRC_SQ_CTRL(crc) \ + ((crc << VGT_CRC_SQ_CTRL_CRC_SHIFT)) + +#define VGT_CRC_SQ_CTRL_GET_CRC(vgt_crc_sq_ctrl) \ + ((vgt_crc_sq_ctrl & VGT_CRC_SQ_CTRL_CRC_MASK) >> VGT_CRC_SQ_CTRL_CRC_SHIFT) + +#define VGT_CRC_SQ_CTRL_SET_CRC(vgt_crc_sq_ctrl_reg, crc) \ + vgt_crc_sq_ctrl_reg = (vgt_crc_sq_ctrl_reg & ~VGT_CRC_SQ_CTRL_CRC_MASK) | (crc << VGT_CRC_SQ_CTRL_CRC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_crc_sq_ctrl_t { + unsigned int crc : VGT_CRC_SQ_CTRL_CRC_SIZE; + } vgt_crc_sq_ctrl_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_crc_sq_ctrl_t { + unsigned int crc : VGT_CRC_SQ_CTRL_CRC_SIZE; + } vgt_crc_sq_ctrl_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_crc_sq_ctrl_t f; +} vgt_crc_sq_ctrl_u; + + +/* + * VGT_PERFCOUNTER0_SELECT struct + */ + +#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define VGT_PERFCOUNTER0_SELECT_MASK \ + (VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define VGT_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define VGT_PERFCOUNTER0_SELECT_GET_PERF_SEL(vgt_perfcounter0_select) \ + ((vgt_perfcounter0_select & VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define VGT_PERFCOUNTER0_SELECT_SET_PERF_SEL(vgt_perfcounter0_select_reg, perf_sel) \ + vgt_perfcounter0_select_reg = (vgt_perfcounter0_select_reg & ~VGT_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_select_t { + unsigned int perf_sel : VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } vgt_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : VGT_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } vgt_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter0_select_t f; +} vgt_perfcounter0_select_u; + + +/* + * VGT_PERFCOUNTER1_SELECT struct + */ + +#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8 + +#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0 + +#define VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff + +#define VGT_PERFCOUNTER1_SELECT_MASK \ + (VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) + +#define VGT_PERFCOUNTER1_SELECT(perf_sel) \ + ((perf_sel << VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)) + +#define VGT_PERFCOUNTER1_SELECT_GET_PERF_SEL(vgt_perfcounter1_select) \ + ((vgt_perfcounter1_select & VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#define VGT_PERFCOUNTER1_SELECT_SET_PERF_SEL(vgt_perfcounter1_select_reg, perf_sel) \ + vgt_perfcounter1_select_reg = (vgt_perfcounter1_select_reg & ~VGT_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_select_t { + unsigned int perf_sel : VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } vgt_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_select_t { + unsigned int : 24; + unsigned int perf_sel : VGT_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + } vgt_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter1_select_t f; +} vgt_perfcounter1_select_u; + + +/* + * VGT_PERFCOUNTER2_SELECT struct + */ + +#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8 + +#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0 + +#define VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff + +#define VGT_PERFCOUNTER2_SELECT_MASK \ + (VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) + +#define VGT_PERFCOUNTER2_SELECT(perf_sel) \ + ((perf_sel << VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)) + +#define VGT_PERFCOUNTER2_SELECT_GET_PERF_SEL(vgt_perfcounter2_select) \ + ((vgt_perfcounter2_select & VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#define VGT_PERFCOUNTER2_SELECT_SET_PERF_SEL(vgt_perfcounter2_select_reg, perf_sel) \ + vgt_perfcounter2_select_reg = (vgt_perfcounter2_select_reg & ~VGT_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_select_t { + unsigned int perf_sel : VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } vgt_perfcounter2_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_select_t { + unsigned int : 24; + unsigned int perf_sel : VGT_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + } vgt_perfcounter2_select_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter2_select_t f; +} vgt_perfcounter2_select_u; + + +/* + * VGT_PERFCOUNTER3_SELECT struct + */ + +#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8 + +#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0 + +#define VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff + +#define VGT_PERFCOUNTER3_SELECT_MASK \ + (VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) + +#define VGT_PERFCOUNTER3_SELECT(perf_sel) \ + ((perf_sel << VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)) + +#define VGT_PERFCOUNTER3_SELECT_GET_PERF_SEL(vgt_perfcounter3_select) \ + ((vgt_perfcounter3_select & VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#define VGT_PERFCOUNTER3_SELECT_SET_PERF_SEL(vgt_perfcounter3_select_reg, perf_sel) \ + vgt_perfcounter3_select_reg = (vgt_perfcounter3_select_reg & ~VGT_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << VGT_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_select_t { + unsigned int perf_sel : VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } vgt_perfcounter3_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_select_t { + unsigned int : 24; + unsigned int perf_sel : VGT_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + } vgt_perfcounter3_select_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter3_select_t f; +} vgt_perfcounter3_select_u; + + +/* + * VGT_PERFCOUNTER0_LOW struct + */ + +#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define VGT_PERFCOUNTER0_LOW_MASK \ + (VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER0_LOW_GET_PERF_COUNT(vgt_perfcounter0_low) \ + ((vgt_perfcounter0_low & VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER0_LOW_SET_PERF_COUNT(vgt_perfcounter0_low_reg, perf_count) \ + vgt_perfcounter0_low_reg = (vgt_perfcounter0_low_reg & ~VGT_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_low_t { + unsigned int perf_count : VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_low_t { + unsigned int perf_count : VGT_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter0_low_t f; +} vgt_perfcounter0_low_u; + + +/* + * VGT_PERFCOUNTER1_LOW struct + */ + +#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32 + +#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff + +#define VGT_PERFCOUNTER1_LOW_MASK \ + (VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER1_LOW(perf_count) \ + ((perf_count << VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER1_LOW_GET_PERF_COUNT(vgt_perfcounter1_low) \ + ((vgt_perfcounter1_low & VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER1_LOW_SET_PERF_COUNT(vgt_perfcounter1_low_reg, perf_count) \ + vgt_perfcounter1_low_reg = (vgt_perfcounter1_low_reg & ~VGT_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_low_t { + unsigned int perf_count : VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_low_t { + unsigned int perf_count : VGT_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter1_low_t f; +} vgt_perfcounter1_low_u; + + +/* + * VGT_PERFCOUNTER2_LOW struct + */ + +#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32 + +#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff + +#define VGT_PERFCOUNTER2_LOW_MASK \ + (VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER2_LOW(perf_count) \ + ((perf_count << VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER2_LOW_GET_PERF_COUNT(vgt_perfcounter2_low) \ + ((vgt_perfcounter2_low & VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER2_LOW_SET_PERF_COUNT(vgt_perfcounter2_low_reg, perf_count) \ + vgt_perfcounter2_low_reg = (vgt_perfcounter2_low_reg & ~VGT_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_low_t { + unsigned int perf_count : VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter2_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_low_t { + unsigned int perf_count : VGT_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter2_low_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter2_low_t f; +} vgt_perfcounter2_low_u; + + +/* + * VGT_PERFCOUNTER3_LOW struct + */ + +#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32 + +#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff + +#define VGT_PERFCOUNTER3_LOW_MASK \ + (VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER3_LOW(perf_count) \ + ((perf_count << VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER3_LOW_GET_PERF_COUNT(vgt_perfcounter3_low) \ + ((vgt_perfcounter3_low & VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER3_LOW_SET_PERF_COUNT(vgt_perfcounter3_low_reg, perf_count) \ + vgt_perfcounter3_low_reg = (vgt_perfcounter3_low_reg & ~VGT_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_low_t { + unsigned int perf_count : VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter3_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_low_t { + unsigned int perf_count : VGT_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } vgt_perfcounter3_low_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter3_low_t f; +} vgt_perfcounter3_low_u; + + +/* + * VGT_PERFCOUNTER0_HI struct + */ + +#define VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define VGT_PERFCOUNTER0_HI_MASK \ + (VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER0_HI_GET_PERF_COUNT(vgt_perfcounter0_hi) \ + ((vgt_perfcounter0_hi & VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER0_HI_SET_PERF_COUNT(vgt_perfcounter0_hi_reg, perf_count) \ + vgt_perfcounter0_hi_reg = (vgt_perfcounter0_hi_reg & ~VGT_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_hi_t { + unsigned int perf_count : VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } vgt_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : VGT_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } vgt_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter0_hi_t f; +} vgt_perfcounter0_hi_u; + + +/* + * VGT_PERFCOUNTER1_HI struct + */ + +#define VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16 + +#define VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff + +#define VGT_PERFCOUNTER1_HI_MASK \ + (VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER1_HI(perf_count) \ + ((perf_count << VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER1_HI_GET_PERF_COUNT(vgt_perfcounter1_hi) \ + ((vgt_perfcounter1_hi & VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER1_HI_SET_PERF_COUNT(vgt_perfcounter1_hi_reg, perf_count) \ + vgt_perfcounter1_hi_reg = (vgt_perfcounter1_hi_reg & ~VGT_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_hi_t { + unsigned int perf_count : VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } vgt_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_count : VGT_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + } vgt_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter1_hi_t f; +} vgt_perfcounter1_hi_u; + + +/* + * VGT_PERFCOUNTER2_HI struct + */ + +#define VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16 + +#define VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff + +#define VGT_PERFCOUNTER2_HI_MASK \ + (VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER2_HI(perf_count) \ + ((perf_count << VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER2_HI_GET_PERF_COUNT(vgt_perfcounter2_hi) \ + ((vgt_perfcounter2_hi & VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER2_HI_SET_PERF_COUNT(vgt_perfcounter2_hi_reg, perf_count) \ + vgt_perfcounter2_hi_reg = (vgt_perfcounter2_hi_reg & ~VGT_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_hi_t { + unsigned int perf_count : VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } vgt_perfcounter2_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter2_hi_t { + unsigned int : 16; + unsigned int perf_count : VGT_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + } vgt_perfcounter2_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter2_hi_t f; +} vgt_perfcounter2_hi_u; + + +/* + * VGT_PERFCOUNTER3_HI struct + */ + +#define VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16 + +#define VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0 + +#define VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff + +#define VGT_PERFCOUNTER3_HI_MASK \ + (VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) + +#define VGT_PERFCOUNTER3_HI(perf_count) \ + ((perf_count << VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)) + +#define VGT_PERFCOUNTER3_HI_GET_PERF_COUNT(vgt_perfcounter3_hi) \ + ((vgt_perfcounter3_hi & VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#define VGT_PERFCOUNTER3_HI_SET_PERF_COUNT(vgt_perfcounter3_hi_reg, perf_count) \ + vgt_perfcounter3_hi_reg = (vgt_perfcounter3_hi_reg & ~VGT_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << VGT_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_hi_t { + unsigned int perf_count : VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } vgt_perfcounter3_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _vgt_perfcounter3_hi_t { + unsigned int : 16; + unsigned int perf_count : VGT_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + } vgt_perfcounter3_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + vgt_perfcounter3_hi_t f; +} vgt_perfcounter3_hi_u; + + +#endif + + +#if !defined (_SQ_FIDDLE_H) +#define _SQ_FIDDLE_H + +/***************************************************************************************************************** + * + * sq_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * SQ_GPR_MANAGEMENT struct + */ + +#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE 1 +#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE 7 +#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE 7 + +#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT 0 +#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT 4 +#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT 12 + +#define SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK 0x00000001 +#define SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK 0x000007f0 +#define SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK 0x0007f000 + +#define SQ_GPR_MANAGEMENT_MASK \ + (SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK | \ + SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK | \ + SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) + +#define SQ_GPR_MANAGEMENT(reg_dynamic, reg_size_pix, reg_size_vtx) \ + ((reg_dynamic << SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT) | \ + (reg_size_pix << SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT) | \ + (reg_size_vtx << SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT)) + +#define SQ_GPR_MANAGEMENT_GET_REG_DYNAMIC(sq_gpr_management) \ + ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK) >> SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT) +#define SQ_GPR_MANAGEMENT_GET_REG_SIZE_PIX(sq_gpr_management) \ + ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK) >> SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT) +#define SQ_GPR_MANAGEMENT_GET_REG_SIZE_VTX(sq_gpr_management) \ + ((sq_gpr_management & SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) >> SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT) + +#define SQ_GPR_MANAGEMENT_SET_REG_DYNAMIC(sq_gpr_management_reg, reg_dynamic) \ + sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_DYNAMIC_MASK) | (reg_dynamic << SQ_GPR_MANAGEMENT_REG_DYNAMIC_SHIFT) +#define SQ_GPR_MANAGEMENT_SET_REG_SIZE_PIX(sq_gpr_management_reg, reg_size_pix) \ + sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_SIZE_PIX_MASK) | (reg_size_pix << SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SHIFT) +#define SQ_GPR_MANAGEMENT_SET_REG_SIZE_VTX(sq_gpr_management_reg, reg_size_vtx) \ + sq_gpr_management_reg = (sq_gpr_management_reg & ~SQ_GPR_MANAGEMENT_REG_SIZE_VTX_MASK) | (reg_size_vtx << SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_gpr_management_t { + unsigned int reg_dynamic : SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE; + unsigned int : 3; + unsigned int reg_size_pix : SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE; + unsigned int : 1; + unsigned int reg_size_vtx : SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE; + unsigned int : 13; + } sq_gpr_management_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_gpr_management_t { + unsigned int : 13; + unsigned int reg_size_vtx : SQ_GPR_MANAGEMENT_REG_SIZE_VTX_SIZE; + unsigned int : 1; + unsigned int reg_size_pix : SQ_GPR_MANAGEMENT_REG_SIZE_PIX_SIZE; + unsigned int : 3; + unsigned int reg_dynamic : SQ_GPR_MANAGEMENT_REG_DYNAMIC_SIZE; + } sq_gpr_management_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_gpr_management_t f; +} sq_gpr_management_u; + + +/* + * SQ_FLOW_CONTROL struct + */ + +#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE 2 +#define SQ_FLOW_CONTROL_ONE_THREAD_SIZE 1 +#define SQ_FLOW_CONTROL_ONE_ALU_SIZE 1 +#define SQ_FLOW_CONTROL_CF_WR_BASE_SIZE 4 +#define SQ_FLOW_CONTROL_NO_PV_PS_SIZE 1 +#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE 1 +#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE 1 +#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE 2 +#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE 1 +#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE 1 +#define SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE 1 +#define SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE 1 +#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE 1 +#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE 1 +#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE 1 + +#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT 0 +#define SQ_FLOW_CONTROL_ONE_THREAD_SHIFT 4 +#define SQ_FLOW_CONTROL_ONE_ALU_SHIFT 8 +#define SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT 12 +#define SQ_FLOW_CONTROL_NO_PV_PS_SHIFT 16 +#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT 17 +#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT 18 +#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT 19 +#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT 21 +#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT 22 +#define SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT 23 +#define SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT 24 +#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT 25 +#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT 26 +#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT 27 + +#define SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK 0x00000003 +#define SQ_FLOW_CONTROL_ONE_THREAD_MASK 0x00000010 +#define SQ_FLOW_CONTROL_ONE_ALU_MASK 0x00000100 +#define SQ_FLOW_CONTROL_CF_WR_BASE_MASK 0x0000f000 +#define SQ_FLOW_CONTROL_NO_PV_PS_MASK 0x00010000 +#define SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK 0x00020000 +#define SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK 0x00040000 +#define SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK 0x00180000 +#define SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK 0x00200000 +#define SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK 0x00400000 +#define SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK 0x00800000 +#define SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK 0x01000000 +#define SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK 0x02000000 +#define SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK 0x04000000 +#define SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK 0x08000000 + +#define SQ_FLOW_CONTROL_MASK \ + (SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK | \ + SQ_FLOW_CONTROL_ONE_THREAD_MASK | \ + SQ_FLOW_CONTROL_ONE_ALU_MASK | \ + SQ_FLOW_CONTROL_CF_WR_BASE_MASK | \ + SQ_FLOW_CONTROL_NO_PV_PS_MASK | \ + SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK | \ + SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK | \ + SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK | \ + SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK | \ + SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK | \ + SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK | \ + SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK | \ + SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK | \ + SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK | \ + SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) + +#define SQ_FLOW_CONTROL(input_arbitration_policy, one_thread, one_alu, cf_wr_base, no_pv_ps, no_loop_exit, no_cexec_optimize, texture_arbitration_policy, vc_arbitration_policy, alu_arbitration_policy, no_arb_eject, no_cfs_eject, pos_exp_priority, no_early_thread_termination, ps_prefetch_color_alloc) \ + ((input_arbitration_policy << SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT) | \ + (one_thread << SQ_FLOW_CONTROL_ONE_THREAD_SHIFT) | \ + (one_alu << SQ_FLOW_CONTROL_ONE_ALU_SHIFT) | \ + (cf_wr_base << SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT) | \ + (no_pv_ps << SQ_FLOW_CONTROL_NO_PV_PS_SHIFT) | \ + (no_loop_exit << SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT) | \ + (no_cexec_optimize << SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT) | \ + (texture_arbitration_policy << SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT) | \ + (vc_arbitration_policy << SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT) | \ + (alu_arbitration_policy << SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT) | \ + (no_arb_eject << SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT) | \ + (no_cfs_eject << SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT) | \ + (pos_exp_priority << SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT) | \ + (no_early_thread_termination << SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT) | \ + (ps_prefetch_color_alloc << SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT)) + +#define SQ_FLOW_CONTROL_GET_INPUT_ARBITRATION_POLICY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_GET_ONE_THREAD(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_ONE_THREAD_MASK) >> SQ_FLOW_CONTROL_ONE_THREAD_SHIFT) +#define SQ_FLOW_CONTROL_GET_ONE_ALU(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_ONE_ALU_MASK) >> SQ_FLOW_CONTROL_ONE_ALU_SHIFT) +#define SQ_FLOW_CONTROL_GET_CF_WR_BASE(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_CF_WR_BASE_MASK) >> SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_PV_PS(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_PV_PS_MASK) >> SQ_FLOW_CONTROL_NO_PV_PS_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_LOOP_EXIT(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK) >> SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_CEXEC_OPTIMIZE(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK) >> SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT) +#define SQ_FLOW_CONTROL_GET_TEXTURE_ARBITRATION_POLICY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_GET_VC_ARBITRATION_POLICY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_GET_ALU_ARBITRATION_POLICY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK) >> SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_ARB_EJECT(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK) >> SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_CFS_EJECT(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK) >> SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT) +#define SQ_FLOW_CONTROL_GET_POS_EXP_PRIORITY(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK) >> SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT) +#define SQ_FLOW_CONTROL_GET_NO_EARLY_THREAD_TERMINATION(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK) >> SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT) +#define SQ_FLOW_CONTROL_GET_PS_PREFETCH_COLOR_ALLOC(sq_flow_control) \ + ((sq_flow_control & SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) >> SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT) + +#define SQ_FLOW_CONTROL_SET_INPUT_ARBITRATION_POLICY(sq_flow_control_reg, input_arbitration_policy) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_MASK) | (input_arbitration_policy << SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_SET_ONE_THREAD(sq_flow_control_reg, one_thread) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ONE_THREAD_MASK) | (one_thread << SQ_FLOW_CONTROL_ONE_THREAD_SHIFT) +#define SQ_FLOW_CONTROL_SET_ONE_ALU(sq_flow_control_reg, one_alu) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ONE_ALU_MASK) | (one_alu << SQ_FLOW_CONTROL_ONE_ALU_SHIFT) +#define SQ_FLOW_CONTROL_SET_CF_WR_BASE(sq_flow_control_reg, cf_wr_base) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_CF_WR_BASE_MASK) | (cf_wr_base << SQ_FLOW_CONTROL_CF_WR_BASE_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_PV_PS(sq_flow_control_reg, no_pv_ps) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_PV_PS_MASK) | (no_pv_ps << SQ_FLOW_CONTROL_NO_PV_PS_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_LOOP_EXIT(sq_flow_control_reg, no_loop_exit) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_LOOP_EXIT_MASK) | (no_loop_exit << SQ_FLOW_CONTROL_NO_LOOP_EXIT_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_CEXEC_OPTIMIZE(sq_flow_control_reg, no_cexec_optimize) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_MASK) | (no_cexec_optimize << SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SHIFT) +#define SQ_FLOW_CONTROL_SET_TEXTURE_ARBITRATION_POLICY(sq_flow_control_reg, texture_arbitration_policy) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_MASK) | (texture_arbitration_policy << SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_SET_VC_ARBITRATION_POLICY(sq_flow_control_reg, vc_arbitration_policy) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_MASK) | (vc_arbitration_policy << SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_SET_ALU_ARBITRATION_POLICY(sq_flow_control_reg, alu_arbitration_policy) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_MASK) | (alu_arbitration_policy << SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_ARB_EJECT(sq_flow_control_reg, no_arb_eject) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_ARB_EJECT_MASK) | (no_arb_eject << SQ_FLOW_CONTROL_NO_ARB_EJECT_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_CFS_EJECT(sq_flow_control_reg, no_cfs_eject) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_CFS_EJECT_MASK) | (no_cfs_eject << SQ_FLOW_CONTROL_NO_CFS_EJECT_SHIFT) +#define SQ_FLOW_CONTROL_SET_POS_EXP_PRIORITY(sq_flow_control_reg, pos_exp_priority) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_POS_EXP_PRIORITY_MASK) | (pos_exp_priority << SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SHIFT) +#define SQ_FLOW_CONTROL_SET_NO_EARLY_THREAD_TERMINATION(sq_flow_control_reg, no_early_thread_termination) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_MASK) | (no_early_thread_termination << SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SHIFT) +#define SQ_FLOW_CONTROL_SET_PS_PREFETCH_COLOR_ALLOC(sq_flow_control_reg, ps_prefetch_color_alloc) \ + sq_flow_control_reg = (sq_flow_control_reg & ~SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_MASK) | (ps_prefetch_color_alloc << SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_flow_control_t { + unsigned int input_arbitration_policy : SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE; + unsigned int : 2; + unsigned int one_thread : SQ_FLOW_CONTROL_ONE_THREAD_SIZE; + unsigned int : 3; + unsigned int one_alu : SQ_FLOW_CONTROL_ONE_ALU_SIZE; + unsigned int : 3; + unsigned int cf_wr_base : SQ_FLOW_CONTROL_CF_WR_BASE_SIZE; + unsigned int no_pv_ps : SQ_FLOW_CONTROL_NO_PV_PS_SIZE; + unsigned int no_loop_exit : SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE; + unsigned int no_cexec_optimize : SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE; + unsigned int texture_arbitration_policy : SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE; + unsigned int vc_arbitration_policy : SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE; + unsigned int alu_arbitration_policy : SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE; + unsigned int no_arb_eject : SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE; + unsigned int no_cfs_eject : SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE; + unsigned int pos_exp_priority : SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE; + unsigned int no_early_thread_termination : SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE; + unsigned int ps_prefetch_color_alloc : SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE; + unsigned int : 4; + } sq_flow_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_flow_control_t { + unsigned int : 4; + unsigned int ps_prefetch_color_alloc : SQ_FLOW_CONTROL_PS_PREFETCH_COLOR_ALLOC_SIZE; + unsigned int no_early_thread_termination : SQ_FLOW_CONTROL_NO_EARLY_THREAD_TERMINATION_SIZE; + unsigned int pos_exp_priority : SQ_FLOW_CONTROL_POS_EXP_PRIORITY_SIZE; + unsigned int no_cfs_eject : SQ_FLOW_CONTROL_NO_CFS_EJECT_SIZE; + unsigned int no_arb_eject : SQ_FLOW_CONTROL_NO_ARB_EJECT_SIZE; + unsigned int alu_arbitration_policy : SQ_FLOW_CONTROL_ALU_ARBITRATION_POLICY_SIZE; + unsigned int vc_arbitration_policy : SQ_FLOW_CONTROL_VC_ARBITRATION_POLICY_SIZE; + unsigned int texture_arbitration_policy : SQ_FLOW_CONTROL_TEXTURE_ARBITRATION_POLICY_SIZE; + unsigned int no_cexec_optimize : SQ_FLOW_CONTROL_NO_CEXEC_OPTIMIZE_SIZE; + unsigned int no_loop_exit : SQ_FLOW_CONTROL_NO_LOOP_EXIT_SIZE; + unsigned int no_pv_ps : SQ_FLOW_CONTROL_NO_PV_PS_SIZE; + unsigned int cf_wr_base : SQ_FLOW_CONTROL_CF_WR_BASE_SIZE; + unsigned int : 3; + unsigned int one_alu : SQ_FLOW_CONTROL_ONE_ALU_SIZE; + unsigned int : 3; + unsigned int one_thread : SQ_FLOW_CONTROL_ONE_THREAD_SIZE; + unsigned int : 2; + unsigned int input_arbitration_policy : SQ_FLOW_CONTROL_INPUT_ARBITRATION_POLICY_SIZE; + } sq_flow_control_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_flow_control_t f; +} sq_flow_control_u; + + +/* + * SQ_INST_STORE_MANAGMENT struct + */ + +#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE 12 +#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE 12 + +#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT 0 +#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT 16 + +#define SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK 0x00000fff +#define SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK 0x0fff0000 + +#define SQ_INST_STORE_MANAGMENT_MASK \ + (SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK | \ + SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) + +#define SQ_INST_STORE_MANAGMENT(inst_base_pix, inst_base_vtx) \ + ((inst_base_pix << SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT) | \ + (inst_base_vtx << SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT)) + +#define SQ_INST_STORE_MANAGMENT_GET_INST_BASE_PIX(sq_inst_store_managment) \ + ((sq_inst_store_managment & SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK) >> SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT) +#define SQ_INST_STORE_MANAGMENT_GET_INST_BASE_VTX(sq_inst_store_managment) \ + ((sq_inst_store_managment & SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) >> SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT) + +#define SQ_INST_STORE_MANAGMENT_SET_INST_BASE_PIX(sq_inst_store_managment_reg, inst_base_pix) \ + sq_inst_store_managment_reg = (sq_inst_store_managment_reg & ~SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_MASK) | (inst_base_pix << SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SHIFT) +#define SQ_INST_STORE_MANAGMENT_SET_INST_BASE_VTX(sq_inst_store_managment_reg, inst_base_vtx) \ + sq_inst_store_managment_reg = (sq_inst_store_managment_reg & ~SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_MASK) | (inst_base_vtx << SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_inst_store_managment_t { + unsigned int inst_base_pix : SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE; + unsigned int : 4; + unsigned int inst_base_vtx : SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE; + unsigned int : 4; + } sq_inst_store_managment_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_inst_store_managment_t { + unsigned int : 4; + unsigned int inst_base_vtx : SQ_INST_STORE_MANAGMENT_INST_BASE_VTX_SIZE; + unsigned int : 4; + unsigned int inst_base_pix : SQ_INST_STORE_MANAGMENT_INST_BASE_PIX_SIZE; + } sq_inst_store_managment_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_inst_store_managment_t f; +} sq_inst_store_managment_u; + + +/* + * SQ_RESOURCE_MANAGMENT struct + */ + +#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE 8 +#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE 8 +#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE 9 + +#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT 0 +#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT 8 +#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT 16 + +#define SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK 0x000000ff +#define SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK 0x0000ff00 +#define SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK 0x01ff0000 + +#define SQ_RESOURCE_MANAGMENT_MASK \ + (SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK | \ + SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK | \ + SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) + +#define SQ_RESOURCE_MANAGMENT(vtx_thread_buf_entries, pix_thread_buf_entries, export_buf_entries) \ + ((vtx_thread_buf_entries << SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT) | \ + (pix_thread_buf_entries << SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT) | \ + (export_buf_entries << SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT)) + +#define SQ_RESOURCE_MANAGMENT_GET_VTX_THREAD_BUF_ENTRIES(sq_resource_managment) \ + ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT) +#define SQ_RESOURCE_MANAGMENT_GET_PIX_THREAD_BUF_ENTRIES(sq_resource_managment) \ + ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT) +#define SQ_RESOURCE_MANAGMENT_GET_EXPORT_BUF_ENTRIES(sq_resource_managment) \ + ((sq_resource_managment & SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) >> SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT) + +#define SQ_RESOURCE_MANAGMENT_SET_VTX_THREAD_BUF_ENTRIES(sq_resource_managment_reg, vtx_thread_buf_entries) \ + sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_MASK) | (vtx_thread_buf_entries << SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SHIFT) +#define SQ_RESOURCE_MANAGMENT_SET_PIX_THREAD_BUF_ENTRIES(sq_resource_managment_reg, pix_thread_buf_entries) \ + sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_MASK) | (pix_thread_buf_entries << SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SHIFT) +#define SQ_RESOURCE_MANAGMENT_SET_EXPORT_BUF_ENTRIES(sq_resource_managment_reg, export_buf_entries) \ + sq_resource_managment_reg = (sq_resource_managment_reg & ~SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_MASK) | (export_buf_entries << SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_resource_managment_t { + unsigned int vtx_thread_buf_entries : SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE; + unsigned int pix_thread_buf_entries : SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE; + unsigned int export_buf_entries : SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE; + unsigned int : 7; + } sq_resource_managment_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_resource_managment_t { + unsigned int : 7; + unsigned int export_buf_entries : SQ_RESOURCE_MANAGMENT_EXPORT_BUF_ENTRIES_SIZE; + unsigned int pix_thread_buf_entries : SQ_RESOURCE_MANAGMENT_PIX_THREAD_BUF_ENTRIES_SIZE; + unsigned int vtx_thread_buf_entries : SQ_RESOURCE_MANAGMENT_VTX_THREAD_BUF_ENTRIES_SIZE; + } sq_resource_managment_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_resource_managment_t f; +} sq_resource_managment_u; + + +/* + * SQ_EO_RT struct + */ + +#define SQ_EO_RT_EO_CONSTANTS_RT_SIZE 8 +#define SQ_EO_RT_EO_TSTATE_RT_SIZE 8 + +#define SQ_EO_RT_EO_CONSTANTS_RT_SHIFT 0 +#define SQ_EO_RT_EO_TSTATE_RT_SHIFT 16 + +#define SQ_EO_RT_EO_CONSTANTS_RT_MASK 0x000000ff +#define SQ_EO_RT_EO_TSTATE_RT_MASK 0x00ff0000 + +#define SQ_EO_RT_MASK \ + (SQ_EO_RT_EO_CONSTANTS_RT_MASK | \ + SQ_EO_RT_EO_TSTATE_RT_MASK) + +#define SQ_EO_RT(eo_constants_rt, eo_tstate_rt) \ + ((eo_constants_rt << SQ_EO_RT_EO_CONSTANTS_RT_SHIFT) | \ + (eo_tstate_rt << SQ_EO_RT_EO_TSTATE_RT_SHIFT)) + +#define SQ_EO_RT_GET_EO_CONSTANTS_RT(sq_eo_rt) \ + ((sq_eo_rt & SQ_EO_RT_EO_CONSTANTS_RT_MASK) >> SQ_EO_RT_EO_CONSTANTS_RT_SHIFT) +#define SQ_EO_RT_GET_EO_TSTATE_RT(sq_eo_rt) \ + ((sq_eo_rt & SQ_EO_RT_EO_TSTATE_RT_MASK) >> SQ_EO_RT_EO_TSTATE_RT_SHIFT) + +#define SQ_EO_RT_SET_EO_CONSTANTS_RT(sq_eo_rt_reg, eo_constants_rt) \ + sq_eo_rt_reg = (sq_eo_rt_reg & ~SQ_EO_RT_EO_CONSTANTS_RT_MASK) | (eo_constants_rt << SQ_EO_RT_EO_CONSTANTS_RT_SHIFT) +#define SQ_EO_RT_SET_EO_TSTATE_RT(sq_eo_rt_reg, eo_tstate_rt) \ + sq_eo_rt_reg = (sq_eo_rt_reg & ~SQ_EO_RT_EO_TSTATE_RT_MASK) | (eo_tstate_rt << SQ_EO_RT_EO_TSTATE_RT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_eo_rt_t { + unsigned int eo_constants_rt : SQ_EO_RT_EO_CONSTANTS_RT_SIZE; + unsigned int : 8; + unsigned int eo_tstate_rt : SQ_EO_RT_EO_TSTATE_RT_SIZE; + unsigned int : 8; + } sq_eo_rt_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_eo_rt_t { + unsigned int : 8; + unsigned int eo_tstate_rt : SQ_EO_RT_EO_TSTATE_RT_SIZE; + unsigned int : 8; + unsigned int eo_constants_rt : SQ_EO_RT_EO_CONSTANTS_RT_SIZE; + } sq_eo_rt_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_eo_rt_t f; +} sq_eo_rt_u; + + +/* + * SQ_DEBUG_MISC struct + */ + +#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE 11 +#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE 8 +#define SQ_DEBUG_MISC_DB_READ_CTX_SIZE 1 +#define SQ_DEBUG_MISC_RESERVED_SIZE 2 +#define SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE 2 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE 1 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE 1 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE 1 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE 1 + +#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT 0 +#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT 12 +#define SQ_DEBUG_MISC_DB_READ_CTX_SHIFT 20 +#define SQ_DEBUG_MISC_RESERVED_SHIFT 21 +#define SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT 23 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT 25 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT 26 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT 27 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT 28 + +#define SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK 0x000007ff +#define SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK 0x000ff000 +#define SQ_DEBUG_MISC_DB_READ_CTX_MASK 0x00100000 +#define SQ_DEBUG_MISC_RESERVED_MASK 0x00600000 +#define SQ_DEBUG_MISC_DB_READ_MEMORY_MASK 0x01800000 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK 0x02000000 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK 0x04000000 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK 0x08000000 +#define SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK 0x10000000 + +#define SQ_DEBUG_MISC_MASK \ + (SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK | \ + SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK | \ + SQ_DEBUG_MISC_DB_READ_CTX_MASK | \ + SQ_DEBUG_MISC_RESERVED_MASK | \ + SQ_DEBUG_MISC_DB_READ_MEMORY_MASK | \ + SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK | \ + SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK | \ + SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK | \ + SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) + +#define SQ_DEBUG_MISC(db_alucst_size, db_tstate_size, db_read_ctx, reserved, db_read_memory, db_wen_memory_0, db_wen_memory_1, db_wen_memory_2, db_wen_memory_3) \ + ((db_alucst_size << SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT) | \ + (db_tstate_size << SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT) | \ + (db_read_ctx << SQ_DEBUG_MISC_DB_READ_CTX_SHIFT) | \ + (reserved << SQ_DEBUG_MISC_RESERVED_SHIFT) | \ + (db_read_memory << SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT) | \ + (db_wen_memory_0 << SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT) | \ + (db_wen_memory_1 << SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT) | \ + (db_wen_memory_2 << SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT) | \ + (db_wen_memory_3 << SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT)) + +#define SQ_DEBUG_MISC_GET_DB_ALUCST_SIZE(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK) >> SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_TSTATE_SIZE(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK) >> SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_READ_CTX(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_READ_CTX_MASK) >> SQ_DEBUG_MISC_DB_READ_CTX_SHIFT) +#define SQ_DEBUG_MISC_GET_RESERVED(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_RESERVED_MASK) >> SQ_DEBUG_MISC_RESERVED_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_READ_MEMORY(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_READ_MEMORY_MASK) >> SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_0(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_1(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_2(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT) +#define SQ_DEBUG_MISC_GET_DB_WEN_MEMORY_3(sq_debug_misc) \ + ((sq_debug_misc & SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) >> SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT) + +#define SQ_DEBUG_MISC_SET_DB_ALUCST_SIZE(sq_debug_misc_reg, db_alucst_size) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_ALUCST_SIZE_MASK) | (db_alucst_size << SQ_DEBUG_MISC_DB_ALUCST_SIZE_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_TSTATE_SIZE(sq_debug_misc_reg, db_tstate_size) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_TSTATE_SIZE_MASK) | (db_tstate_size << SQ_DEBUG_MISC_DB_TSTATE_SIZE_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_READ_CTX(sq_debug_misc_reg, db_read_ctx) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_READ_CTX_MASK) | (db_read_ctx << SQ_DEBUG_MISC_DB_READ_CTX_SHIFT) +#define SQ_DEBUG_MISC_SET_RESERVED(sq_debug_misc_reg, reserved) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_RESERVED_MASK) | (reserved << SQ_DEBUG_MISC_RESERVED_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_READ_MEMORY(sq_debug_misc_reg, db_read_memory) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_READ_MEMORY_MASK) | (db_read_memory << SQ_DEBUG_MISC_DB_READ_MEMORY_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_0(sq_debug_misc_reg, db_wen_memory_0) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_0_MASK) | (db_wen_memory_0 << SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_1(sq_debug_misc_reg, db_wen_memory_1) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_1_MASK) | (db_wen_memory_1 << SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_2(sq_debug_misc_reg, db_wen_memory_2) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_2_MASK) | (db_wen_memory_2 << SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SHIFT) +#define SQ_DEBUG_MISC_SET_DB_WEN_MEMORY_3(sq_debug_misc_reg, db_wen_memory_3) \ + sq_debug_misc_reg = (sq_debug_misc_reg & ~SQ_DEBUG_MISC_DB_WEN_MEMORY_3_MASK) | (db_wen_memory_3 << SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_misc_t { + unsigned int db_alucst_size : SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE; + unsigned int : 1; + unsigned int db_tstate_size : SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE; + unsigned int db_read_ctx : SQ_DEBUG_MISC_DB_READ_CTX_SIZE; + unsigned int reserved : SQ_DEBUG_MISC_RESERVED_SIZE; + unsigned int db_read_memory : SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE; + unsigned int db_wen_memory_0 : SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE; + unsigned int db_wen_memory_1 : SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE; + unsigned int db_wen_memory_2 : SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE; + unsigned int db_wen_memory_3 : SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE; + unsigned int : 3; + } sq_debug_misc_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_misc_t { + unsigned int : 3; + unsigned int db_wen_memory_3 : SQ_DEBUG_MISC_DB_WEN_MEMORY_3_SIZE; + unsigned int db_wen_memory_2 : SQ_DEBUG_MISC_DB_WEN_MEMORY_2_SIZE; + unsigned int db_wen_memory_1 : SQ_DEBUG_MISC_DB_WEN_MEMORY_1_SIZE; + unsigned int db_wen_memory_0 : SQ_DEBUG_MISC_DB_WEN_MEMORY_0_SIZE; + unsigned int db_read_memory : SQ_DEBUG_MISC_DB_READ_MEMORY_SIZE; + unsigned int reserved : SQ_DEBUG_MISC_RESERVED_SIZE; + unsigned int db_read_ctx : SQ_DEBUG_MISC_DB_READ_CTX_SIZE; + unsigned int db_tstate_size : SQ_DEBUG_MISC_DB_TSTATE_SIZE_SIZE; + unsigned int : 1; + unsigned int db_alucst_size : SQ_DEBUG_MISC_DB_ALUCST_SIZE_SIZE; + } sq_debug_misc_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_misc_t f; +} sq_debug_misc_u; + + +/* + * SQ_ACTIVITY_METER_CNTL struct + */ + +#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE 8 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE 8 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE 8 +#define SQ_ACTIVITY_METER_CNTL_SPARE_SIZE 8 + +#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT 0 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT 8 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT 16 +#define SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT 24 + +#define SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK 0x000000ff +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK 0x0000ff00 +#define SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK 0x00ff0000 +#define SQ_ACTIVITY_METER_CNTL_SPARE_MASK 0xff000000 + +#define SQ_ACTIVITY_METER_CNTL_MASK \ + (SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK | \ + SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK | \ + SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK | \ + SQ_ACTIVITY_METER_CNTL_SPARE_MASK) + +#define SQ_ACTIVITY_METER_CNTL(timebase, threshold_low, threshold_high, spare) \ + ((timebase << SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT) | \ + (threshold_low << SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT) | \ + (threshold_high << SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT) | \ + (spare << SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT)) + +#define SQ_ACTIVITY_METER_CNTL_GET_TIMEBASE(sq_activity_meter_cntl) \ + ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK) >> SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_GET_THRESHOLD_LOW(sq_activity_meter_cntl) \ + ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK) >> SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_GET_THRESHOLD_HIGH(sq_activity_meter_cntl) \ + ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK) >> SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_GET_SPARE(sq_activity_meter_cntl) \ + ((sq_activity_meter_cntl & SQ_ACTIVITY_METER_CNTL_SPARE_MASK) >> SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT) + +#define SQ_ACTIVITY_METER_CNTL_SET_TIMEBASE(sq_activity_meter_cntl_reg, timebase) \ + sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_TIMEBASE_MASK) | (timebase << SQ_ACTIVITY_METER_CNTL_TIMEBASE_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_SET_THRESHOLD_LOW(sq_activity_meter_cntl_reg, threshold_low) \ + sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_MASK) | (threshold_low << SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_SET_THRESHOLD_HIGH(sq_activity_meter_cntl_reg, threshold_high) \ + sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_MASK) | (threshold_high << SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SHIFT) +#define SQ_ACTIVITY_METER_CNTL_SET_SPARE(sq_activity_meter_cntl_reg, spare) \ + sq_activity_meter_cntl_reg = (sq_activity_meter_cntl_reg & ~SQ_ACTIVITY_METER_CNTL_SPARE_MASK) | (spare << SQ_ACTIVITY_METER_CNTL_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_activity_meter_cntl_t { + unsigned int timebase : SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE; + unsigned int threshold_low : SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE; + unsigned int threshold_high : SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE; + unsigned int spare : SQ_ACTIVITY_METER_CNTL_SPARE_SIZE; + } sq_activity_meter_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_activity_meter_cntl_t { + unsigned int spare : SQ_ACTIVITY_METER_CNTL_SPARE_SIZE; + unsigned int threshold_high : SQ_ACTIVITY_METER_CNTL_THRESHOLD_HIGH_SIZE; + unsigned int threshold_low : SQ_ACTIVITY_METER_CNTL_THRESHOLD_LOW_SIZE; + unsigned int timebase : SQ_ACTIVITY_METER_CNTL_TIMEBASE_SIZE; + } sq_activity_meter_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_activity_meter_cntl_t f; +} sq_activity_meter_cntl_u; + + +/* + * SQ_ACTIVITY_METER_STATUS struct + */ + +#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE 8 + +#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT 0 + +#define SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK 0x000000ff + +#define SQ_ACTIVITY_METER_STATUS_MASK \ + (SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) + +#define SQ_ACTIVITY_METER_STATUS(percent_busy) \ + ((percent_busy << SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT)) + +#define SQ_ACTIVITY_METER_STATUS_GET_PERCENT_BUSY(sq_activity_meter_status) \ + ((sq_activity_meter_status & SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) >> SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT) + +#define SQ_ACTIVITY_METER_STATUS_SET_PERCENT_BUSY(sq_activity_meter_status_reg, percent_busy) \ + sq_activity_meter_status_reg = (sq_activity_meter_status_reg & ~SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_MASK) | (percent_busy << SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_activity_meter_status_t { + unsigned int percent_busy : SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE; + unsigned int : 24; + } sq_activity_meter_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_activity_meter_status_t { + unsigned int : 24; + unsigned int percent_busy : SQ_ACTIVITY_METER_STATUS_PERCENT_BUSY_SIZE; + } sq_activity_meter_status_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_activity_meter_status_t f; +} sq_activity_meter_status_u; + + +/* + * SQ_INPUT_ARB_PRIORITY struct + */ + +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE 3 +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE 1 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE 3 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE 1 +#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE 10 + +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT 0 +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT 3 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT 4 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT 7 +#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT 8 + +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK 0x00000007 +#define SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK 0x00000008 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK 0x00000070 +#define SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK 0x00000080 +#define SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK 0x0003ff00 + +#define SQ_INPUT_ARB_PRIORITY_MASK \ + (SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK | \ + SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK | \ + SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK | \ + SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK | \ + SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) + +#define SQ_INPUT_ARB_PRIORITY(pc_avail_weight, pc_avail_sign, sx_avail_weight, sx_avail_sign, threshold) \ + ((pc_avail_weight << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) | \ + (pc_avail_sign << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) | \ + (sx_avail_weight << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) | \ + (sx_avail_sign << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) | \ + (threshold << SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT)) + +#define SQ_INPUT_ARB_PRIORITY_GET_PC_AVAIL_WEIGHT(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) >> SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_GET_PC_AVAIL_SIGN(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) >> SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_GET_SX_AVAIL_WEIGHT(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) >> SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_GET_SX_AVAIL_SIGN(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) >> SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_GET_THRESHOLD(sq_input_arb_priority) \ + ((sq_input_arb_priority & SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) >> SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT) + +#define SQ_INPUT_ARB_PRIORITY_SET_PC_AVAIL_WEIGHT(sq_input_arb_priority_reg, pc_avail_weight) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) | (pc_avail_weight << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_SET_PC_AVAIL_SIGN(sq_input_arb_priority_reg, pc_avail_sign) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) | (pc_avail_sign << SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_SET_SX_AVAIL_WEIGHT(sq_input_arb_priority_reg, sx_avail_weight) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) | (sx_avail_weight << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_SET_SX_AVAIL_SIGN(sq_input_arb_priority_reg, sx_avail_sign) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) | (sx_avail_sign << SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) +#define SQ_INPUT_ARB_PRIORITY_SET_THRESHOLD(sq_input_arb_priority_reg, threshold) \ + sq_input_arb_priority_reg = (sq_input_arb_priority_reg & ~SQ_INPUT_ARB_PRIORITY_THRESHOLD_MASK) | (threshold << SQ_INPUT_ARB_PRIORITY_THRESHOLD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_input_arb_priority_t { + unsigned int pc_avail_weight : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE; + unsigned int pc_avail_sign : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE; + unsigned int sx_avail_weight : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE; + unsigned int sx_avail_sign : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE; + unsigned int threshold : SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE; + unsigned int : 14; + } sq_input_arb_priority_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_input_arb_priority_t { + unsigned int : 14; + unsigned int threshold : SQ_INPUT_ARB_PRIORITY_THRESHOLD_SIZE; + unsigned int sx_avail_sign : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE; + unsigned int sx_avail_weight : SQ_INPUT_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE; + unsigned int pc_avail_sign : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE; + unsigned int pc_avail_weight : SQ_INPUT_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE; + } sq_input_arb_priority_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_input_arb_priority_t f; +} sq_input_arb_priority_u; + + +/* + * SQ_THREAD_ARB_PRIORITY struct + */ + +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE 3 +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE 1 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE 3 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE 1 +#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE 10 +#define SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE 2 +#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE 1 +#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE 1 +#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE 1 + +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT 0 +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT 3 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT 4 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT 7 +#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT 8 +#define SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT 18 +#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT 20 +#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT 21 +#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT 22 + +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK 0x00000007 +#define SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK 0x00000008 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK 0x00000070 +#define SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK 0x00000080 +#define SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK 0x0003ff00 +#define SQ_THREAD_ARB_PRIORITY_RESERVED_MASK 0x000c0000 +#define SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK 0x00100000 +#define SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK 0x00200000 +#define SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK 0x00400000 + +#define SQ_THREAD_ARB_PRIORITY_MASK \ + (SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK | \ + SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK | \ + SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK | \ + SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK | \ + SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK | \ + SQ_THREAD_ARB_PRIORITY_RESERVED_MASK | \ + SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK | \ + SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK | \ + SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) + +#define SQ_THREAD_ARB_PRIORITY(pc_avail_weight, pc_avail_sign, sx_avail_weight, sx_avail_sign, threshold, reserved, vs_prioritize_serial, ps_prioritize_serial, use_serial_count_threshold) \ + ((pc_avail_weight << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) | \ + (pc_avail_sign << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) | \ + (sx_avail_weight << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) | \ + (sx_avail_sign << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) | \ + (threshold << SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT) | \ + (reserved << SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT) | \ + (vs_prioritize_serial << SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT) | \ + (ps_prioritize_serial << SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT) | \ + (use_serial_count_threshold << SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT)) + +#define SQ_THREAD_ARB_PRIORITY_GET_PC_AVAIL_WEIGHT(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) >> SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_PC_AVAIL_SIGN(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) >> SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_SX_AVAIL_WEIGHT(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) >> SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_SX_AVAIL_SIGN(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) >> SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_THRESHOLD(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK) >> SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_RESERVED(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_RESERVED_MASK) >> SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_VS_PRIORITIZE_SERIAL(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK) >> SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_PS_PRIORITIZE_SERIAL(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK) >> SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_GET_USE_SERIAL_COUNT_THRESHOLD(sq_thread_arb_priority) \ + ((sq_thread_arb_priority & SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) >> SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT) + +#define SQ_THREAD_ARB_PRIORITY_SET_PC_AVAIL_WEIGHT(sq_thread_arb_priority_reg, pc_avail_weight) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_MASK) | (pc_avail_weight << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_PC_AVAIL_SIGN(sq_thread_arb_priority_reg, pc_avail_sign) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_MASK) | (pc_avail_sign << SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_SX_AVAIL_WEIGHT(sq_thread_arb_priority_reg, sx_avail_weight) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_MASK) | (sx_avail_weight << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_SX_AVAIL_SIGN(sq_thread_arb_priority_reg, sx_avail_sign) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_MASK) | (sx_avail_sign << SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_THRESHOLD(sq_thread_arb_priority_reg, threshold) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_THRESHOLD_MASK) | (threshold << SQ_THREAD_ARB_PRIORITY_THRESHOLD_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_RESERVED(sq_thread_arb_priority_reg, reserved) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_RESERVED_MASK) | (reserved << SQ_THREAD_ARB_PRIORITY_RESERVED_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_VS_PRIORITIZE_SERIAL(sq_thread_arb_priority_reg, vs_prioritize_serial) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_MASK) | (vs_prioritize_serial << SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_PS_PRIORITIZE_SERIAL(sq_thread_arb_priority_reg, ps_prioritize_serial) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_MASK) | (ps_prioritize_serial << SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SHIFT) +#define SQ_THREAD_ARB_PRIORITY_SET_USE_SERIAL_COUNT_THRESHOLD(sq_thread_arb_priority_reg, use_serial_count_threshold) \ + sq_thread_arb_priority_reg = (sq_thread_arb_priority_reg & ~SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_MASK) | (use_serial_count_threshold << SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_thread_arb_priority_t { + unsigned int pc_avail_weight : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE; + unsigned int pc_avail_sign : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE; + unsigned int sx_avail_weight : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE; + unsigned int sx_avail_sign : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE; + unsigned int threshold : SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE; + unsigned int reserved : SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE; + unsigned int vs_prioritize_serial : SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE; + unsigned int ps_prioritize_serial : SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE; + unsigned int use_serial_count_threshold : SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE; + unsigned int : 9; + } sq_thread_arb_priority_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_thread_arb_priority_t { + unsigned int : 9; + unsigned int use_serial_count_threshold : SQ_THREAD_ARB_PRIORITY_USE_SERIAL_COUNT_THRESHOLD_SIZE; + unsigned int ps_prioritize_serial : SQ_THREAD_ARB_PRIORITY_PS_PRIORITIZE_SERIAL_SIZE; + unsigned int vs_prioritize_serial : SQ_THREAD_ARB_PRIORITY_VS_PRIORITIZE_SERIAL_SIZE; + unsigned int reserved : SQ_THREAD_ARB_PRIORITY_RESERVED_SIZE; + unsigned int threshold : SQ_THREAD_ARB_PRIORITY_THRESHOLD_SIZE; + unsigned int sx_avail_sign : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_SIGN_SIZE; + unsigned int sx_avail_weight : SQ_THREAD_ARB_PRIORITY_SX_AVAIL_WEIGHT_SIZE; + unsigned int pc_avail_sign : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_SIGN_SIZE; + unsigned int pc_avail_weight : SQ_THREAD_ARB_PRIORITY_PC_AVAIL_WEIGHT_SIZE; + } sq_thread_arb_priority_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_thread_arb_priority_t f; +} sq_thread_arb_priority_u; + + +/* + * SQ_VS_WATCHDOG_TIMER struct + */ + +#define SQ_VS_WATCHDOG_TIMER_ENABLE_SIZE 1 +#define SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE 31 + +#define SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT 0 +#define SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT 1 + +#define SQ_VS_WATCHDOG_TIMER_ENABLE_MASK 0x00000001 +#define SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK 0xfffffffe + +#define SQ_VS_WATCHDOG_TIMER_MASK \ + (SQ_VS_WATCHDOG_TIMER_ENABLE_MASK | \ + SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) + +#define SQ_VS_WATCHDOG_TIMER(enable, timeout_count) \ + ((enable << SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT) | \ + (timeout_count << SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT)) + +#define SQ_VS_WATCHDOG_TIMER_GET_ENABLE(sq_vs_watchdog_timer) \ + ((sq_vs_watchdog_timer & SQ_VS_WATCHDOG_TIMER_ENABLE_MASK) >> SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT) +#define SQ_VS_WATCHDOG_TIMER_GET_TIMEOUT_COUNT(sq_vs_watchdog_timer) \ + ((sq_vs_watchdog_timer & SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) >> SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT) + +#define SQ_VS_WATCHDOG_TIMER_SET_ENABLE(sq_vs_watchdog_timer_reg, enable) \ + sq_vs_watchdog_timer_reg = (sq_vs_watchdog_timer_reg & ~SQ_VS_WATCHDOG_TIMER_ENABLE_MASK) | (enable << SQ_VS_WATCHDOG_TIMER_ENABLE_SHIFT) +#define SQ_VS_WATCHDOG_TIMER_SET_TIMEOUT_COUNT(sq_vs_watchdog_timer_reg, timeout_count) \ + sq_vs_watchdog_timer_reg = (sq_vs_watchdog_timer_reg & ~SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) | (timeout_count << SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_vs_watchdog_timer_t { + unsigned int enable : SQ_VS_WATCHDOG_TIMER_ENABLE_SIZE; + unsigned int timeout_count : SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE; + } sq_vs_watchdog_timer_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_vs_watchdog_timer_t { + unsigned int timeout_count : SQ_VS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE; + unsigned int enable : SQ_VS_WATCHDOG_TIMER_ENABLE_SIZE; + } sq_vs_watchdog_timer_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_vs_watchdog_timer_t f; +} sq_vs_watchdog_timer_u; + + +/* + * SQ_PS_WATCHDOG_TIMER struct + */ + +#define SQ_PS_WATCHDOG_TIMER_ENABLE_SIZE 1 +#define SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE 31 + +#define SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT 0 +#define SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT 1 + +#define SQ_PS_WATCHDOG_TIMER_ENABLE_MASK 0x00000001 +#define SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK 0xfffffffe + +#define SQ_PS_WATCHDOG_TIMER_MASK \ + (SQ_PS_WATCHDOG_TIMER_ENABLE_MASK | \ + SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) + +#define SQ_PS_WATCHDOG_TIMER(enable, timeout_count) \ + ((enable << SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT) | \ + (timeout_count << SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT)) + +#define SQ_PS_WATCHDOG_TIMER_GET_ENABLE(sq_ps_watchdog_timer) \ + ((sq_ps_watchdog_timer & SQ_PS_WATCHDOG_TIMER_ENABLE_MASK) >> SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT) +#define SQ_PS_WATCHDOG_TIMER_GET_TIMEOUT_COUNT(sq_ps_watchdog_timer) \ + ((sq_ps_watchdog_timer & SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) >> SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT) + +#define SQ_PS_WATCHDOG_TIMER_SET_ENABLE(sq_ps_watchdog_timer_reg, enable) \ + sq_ps_watchdog_timer_reg = (sq_ps_watchdog_timer_reg & ~SQ_PS_WATCHDOG_TIMER_ENABLE_MASK) | (enable << SQ_PS_WATCHDOG_TIMER_ENABLE_SHIFT) +#define SQ_PS_WATCHDOG_TIMER_SET_TIMEOUT_COUNT(sq_ps_watchdog_timer_reg, timeout_count) \ + sq_ps_watchdog_timer_reg = (sq_ps_watchdog_timer_reg & ~SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_MASK) | (timeout_count << SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_ps_watchdog_timer_t { + unsigned int enable : SQ_PS_WATCHDOG_TIMER_ENABLE_SIZE; + unsigned int timeout_count : SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE; + } sq_ps_watchdog_timer_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_ps_watchdog_timer_t { + unsigned int timeout_count : SQ_PS_WATCHDOG_TIMER_TIMEOUT_COUNT_SIZE; + unsigned int enable : SQ_PS_WATCHDOG_TIMER_ENABLE_SIZE; + } sq_ps_watchdog_timer_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_ps_watchdog_timer_t f; +} sq_ps_watchdog_timer_u; + + +/* + * SQ_INT_CNTL struct + */ + +#define SQ_INT_CNTL_PS_WATCHDOG_MASK_SIZE 1 +#define SQ_INT_CNTL_VS_WATCHDOG_MASK_SIZE 1 + +#define SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT 0 +#define SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT 1 + +#define SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK 0x00000001 +#define SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK 0x00000002 + +#define SQ_INT_CNTL_MASK \ + (SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK | \ + SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK) + +#define SQ_INT_CNTL(ps_watchdog_mask, vs_watchdog_mask) \ + ((ps_watchdog_mask << SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT) | \ + (vs_watchdog_mask << SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT)) + +#define SQ_INT_CNTL_GET_PS_WATCHDOG_MASK(sq_int_cntl) \ + ((sq_int_cntl & SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK) >> SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT) +#define SQ_INT_CNTL_GET_VS_WATCHDOG_MASK(sq_int_cntl) \ + ((sq_int_cntl & SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK) >> SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT) + +#define SQ_INT_CNTL_SET_PS_WATCHDOG_MASK(sq_int_cntl_reg, ps_watchdog_mask) \ + sq_int_cntl_reg = (sq_int_cntl_reg & ~SQ_INT_CNTL_PS_WATCHDOG_MASK_MASK) | (ps_watchdog_mask << SQ_INT_CNTL_PS_WATCHDOG_MASK_SHIFT) +#define SQ_INT_CNTL_SET_VS_WATCHDOG_MASK(sq_int_cntl_reg, vs_watchdog_mask) \ + sq_int_cntl_reg = (sq_int_cntl_reg & ~SQ_INT_CNTL_VS_WATCHDOG_MASK_MASK) | (vs_watchdog_mask << SQ_INT_CNTL_VS_WATCHDOG_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_int_cntl_t { + unsigned int ps_watchdog_mask : SQ_INT_CNTL_PS_WATCHDOG_MASK_SIZE; + unsigned int vs_watchdog_mask : SQ_INT_CNTL_VS_WATCHDOG_MASK_SIZE; + unsigned int : 30; + } sq_int_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_int_cntl_t { + unsigned int : 30; + unsigned int vs_watchdog_mask : SQ_INT_CNTL_VS_WATCHDOG_MASK_SIZE; + unsigned int ps_watchdog_mask : SQ_INT_CNTL_PS_WATCHDOG_MASK_SIZE; + } sq_int_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_int_cntl_t f; +} sq_int_cntl_u; + + +/* + * SQ_INT_STATUS struct + */ + +#define SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SIZE 1 +#define SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SIZE 1 + +#define SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT 0 +#define SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT 1 + +#define SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK 0x00000001 +#define SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK 0x00000002 + +#define SQ_INT_STATUS_MASK \ + (SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK | \ + SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK) + +#define SQ_INT_STATUS(ps_watchdog_timeout, vs_watchdog_timeout) \ + ((ps_watchdog_timeout << SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT) | \ + (vs_watchdog_timeout << SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT)) + +#define SQ_INT_STATUS_GET_PS_WATCHDOG_TIMEOUT(sq_int_status) \ + ((sq_int_status & SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK) >> SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT) +#define SQ_INT_STATUS_GET_VS_WATCHDOG_TIMEOUT(sq_int_status) \ + ((sq_int_status & SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK) >> SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT) + +#define SQ_INT_STATUS_SET_PS_WATCHDOG_TIMEOUT(sq_int_status_reg, ps_watchdog_timeout) \ + sq_int_status_reg = (sq_int_status_reg & ~SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_MASK) | (ps_watchdog_timeout << SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SHIFT) +#define SQ_INT_STATUS_SET_VS_WATCHDOG_TIMEOUT(sq_int_status_reg, vs_watchdog_timeout) \ + sq_int_status_reg = (sq_int_status_reg & ~SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_MASK) | (vs_watchdog_timeout << SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_int_status_t { + unsigned int ps_watchdog_timeout : SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SIZE; + unsigned int vs_watchdog_timeout : SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SIZE; + unsigned int : 30; + } sq_int_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_int_status_t { + unsigned int : 30; + unsigned int vs_watchdog_timeout : SQ_INT_STATUS_VS_WATCHDOG_TIMEOUT_SIZE; + unsigned int ps_watchdog_timeout : SQ_INT_STATUS_PS_WATCHDOG_TIMEOUT_SIZE; + } sq_int_status_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_int_status_t f; +} sq_int_status_u; + + +/* + * SQ_INT_ACK struct + */ + +#define SQ_INT_ACK_PS_WATCHDOG_ACK_SIZE 1 +#define SQ_INT_ACK_VS_WATCHDOG_ACK_SIZE 1 + +#define SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT 0 +#define SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT 1 + +#define SQ_INT_ACK_PS_WATCHDOG_ACK_MASK 0x00000001 +#define SQ_INT_ACK_VS_WATCHDOG_ACK_MASK 0x00000002 + +#define SQ_INT_ACK_MASK \ + (SQ_INT_ACK_PS_WATCHDOG_ACK_MASK | \ + SQ_INT_ACK_VS_WATCHDOG_ACK_MASK) + +#define SQ_INT_ACK(ps_watchdog_ack, vs_watchdog_ack) \ + ((ps_watchdog_ack << SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT) | \ + (vs_watchdog_ack << SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT)) + +#define SQ_INT_ACK_GET_PS_WATCHDOG_ACK(sq_int_ack) \ + ((sq_int_ack & SQ_INT_ACK_PS_WATCHDOG_ACK_MASK) >> SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT) +#define SQ_INT_ACK_GET_VS_WATCHDOG_ACK(sq_int_ack) \ + ((sq_int_ack & SQ_INT_ACK_VS_WATCHDOG_ACK_MASK) >> SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT) + +#define SQ_INT_ACK_SET_PS_WATCHDOG_ACK(sq_int_ack_reg, ps_watchdog_ack) \ + sq_int_ack_reg = (sq_int_ack_reg & ~SQ_INT_ACK_PS_WATCHDOG_ACK_MASK) | (ps_watchdog_ack << SQ_INT_ACK_PS_WATCHDOG_ACK_SHIFT) +#define SQ_INT_ACK_SET_VS_WATCHDOG_ACK(sq_int_ack_reg, vs_watchdog_ack) \ + sq_int_ack_reg = (sq_int_ack_reg & ~SQ_INT_ACK_VS_WATCHDOG_ACK_MASK) | (vs_watchdog_ack << SQ_INT_ACK_VS_WATCHDOG_ACK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_int_ack_t { + unsigned int ps_watchdog_ack : SQ_INT_ACK_PS_WATCHDOG_ACK_SIZE; + unsigned int vs_watchdog_ack : SQ_INT_ACK_VS_WATCHDOG_ACK_SIZE; + unsigned int : 30; + } sq_int_ack_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_int_ack_t { + unsigned int : 30; + unsigned int vs_watchdog_ack : SQ_INT_ACK_VS_WATCHDOG_ACK_SIZE; + unsigned int ps_watchdog_ack : SQ_INT_ACK_PS_WATCHDOG_ACK_SIZE; + } sq_int_ack_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_int_ack_t f; +} sq_int_ack_u; + + +/* + * SQ_DEBUG_INPUT_FSM struct + */ + +#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE 3 +#define SQ_DEBUG_INPUT_FSM_RESERVED_SIZE 1 +#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE 4 +#define SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE 3 +#define SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE 1 +#define SQ_DEBUG_INPUT_FSM_PC_AS_SIZE 3 +#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE 5 +#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE 8 + +#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT 0 +#define SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT 3 +#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT 4 +#define SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT 8 +#define SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT 11 +#define SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT 12 +#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT 15 +#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT 20 + +#define SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK 0x00000007 +#define SQ_DEBUG_INPUT_FSM_RESERVED_MASK 0x00000008 +#define SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK 0x000000f0 +#define SQ_DEBUG_INPUT_FSM_PC_PISM_MASK 0x00000700 +#define SQ_DEBUG_INPUT_FSM_RESERVED1_MASK 0x00000800 +#define SQ_DEBUG_INPUT_FSM_PC_AS_MASK 0x00007000 +#define SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK 0x000f8000 +#define SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK 0x0ff00000 + +#define SQ_DEBUG_INPUT_FSM_MASK \ + (SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK | \ + SQ_DEBUG_INPUT_FSM_RESERVED_MASK | \ + SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK | \ + SQ_DEBUG_INPUT_FSM_PC_PISM_MASK | \ + SQ_DEBUG_INPUT_FSM_RESERVED1_MASK | \ + SQ_DEBUG_INPUT_FSM_PC_AS_MASK | \ + SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK | \ + SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) + +#define SQ_DEBUG_INPUT_FSM(vc_vsr_ld, reserved, vc_gpr_ld, pc_pism, reserved1, pc_as, pc_interp_cnt, pc_gpr_size) \ + ((vc_vsr_ld << SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT) | \ + (reserved << SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT) | \ + (vc_gpr_ld << SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT) | \ + (pc_pism << SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT) | \ + (reserved1 << SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT) | \ + (pc_as << SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT) | \ + (pc_interp_cnt << SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT) | \ + (pc_gpr_size << SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT)) + +#define SQ_DEBUG_INPUT_FSM_GET_VC_VSR_LD(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK) >> SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_RESERVED(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_RESERVED_MASK) >> SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_VC_GPR_LD(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK) >> SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_PC_PISM(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_PISM_MASK) >> SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_RESERVED1(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_RESERVED1_MASK) >> SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_PC_AS(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_AS_MASK) >> SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_PC_INTERP_CNT(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK) >> SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT) +#define SQ_DEBUG_INPUT_FSM_GET_PC_GPR_SIZE(sq_debug_input_fsm) \ + ((sq_debug_input_fsm & SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) >> SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT) + +#define SQ_DEBUG_INPUT_FSM_SET_VC_VSR_LD(sq_debug_input_fsm_reg, vc_vsr_ld) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_VC_VSR_LD_MASK) | (vc_vsr_ld << SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_RESERVED(sq_debug_input_fsm_reg, reserved) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_RESERVED_MASK) | (reserved << SQ_DEBUG_INPUT_FSM_RESERVED_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_VC_GPR_LD(sq_debug_input_fsm_reg, vc_gpr_ld) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_VC_GPR_LD_MASK) | (vc_gpr_ld << SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_PC_PISM(sq_debug_input_fsm_reg, pc_pism) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_PISM_MASK) | (pc_pism << SQ_DEBUG_INPUT_FSM_PC_PISM_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_RESERVED1(sq_debug_input_fsm_reg, reserved1) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_INPUT_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_PC_AS(sq_debug_input_fsm_reg, pc_as) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_AS_MASK) | (pc_as << SQ_DEBUG_INPUT_FSM_PC_AS_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_PC_INTERP_CNT(sq_debug_input_fsm_reg, pc_interp_cnt) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_MASK) | (pc_interp_cnt << SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SHIFT) +#define SQ_DEBUG_INPUT_FSM_SET_PC_GPR_SIZE(sq_debug_input_fsm_reg, pc_gpr_size) \ + sq_debug_input_fsm_reg = (sq_debug_input_fsm_reg & ~SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_MASK) | (pc_gpr_size << SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_input_fsm_t { + unsigned int vc_vsr_ld : SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE; + unsigned int reserved : SQ_DEBUG_INPUT_FSM_RESERVED_SIZE; + unsigned int vc_gpr_ld : SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE; + unsigned int pc_pism : SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE; + unsigned int reserved1 : SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE; + unsigned int pc_as : SQ_DEBUG_INPUT_FSM_PC_AS_SIZE; + unsigned int pc_interp_cnt : SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE; + unsigned int pc_gpr_size : SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE; + unsigned int : 4; + } sq_debug_input_fsm_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_input_fsm_t { + unsigned int : 4; + unsigned int pc_gpr_size : SQ_DEBUG_INPUT_FSM_PC_GPR_SIZE_SIZE; + unsigned int pc_interp_cnt : SQ_DEBUG_INPUT_FSM_PC_INTERP_CNT_SIZE; + unsigned int pc_as : SQ_DEBUG_INPUT_FSM_PC_AS_SIZE; + unsigned int reserved1 : SQ_DEBUG_INPUT_FSM_RESERVED1_SIZE; + unsigned int pc_pism : SQ_DEBUG_INPUT_FSM_PC_PISM_SIZE; + unsigned int vc_gpr_ld : SQ_DEBUG_INPUT_FSM_VC_GPR_LD_SIZE; + unsigned int reserved : SQ_DEBUG_INPUT_FSM_RESERVED_SIZE; + unsigned int vc_vsr_ld : SQ_DEBUG_INPUT_FSM_VC_VSR_LD_SIZE; + } sq_debug_input_fsm_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_input_fsm_t f; +} sq_debug_input_fsm_u; + + +/* + * SQ_DEBUG_CONST_MGR_FSM struct + */ + +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE 5 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE 3 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE 5 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE 3 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE 2 +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE 2 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE 1 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE 1 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE 1 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE 1 + +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT 0 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT 5 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT 8 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT 13 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT 16 +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT 18 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT 20 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT 21 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT 22 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT 23 + +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK 0x0000001f +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK 0x000000e0 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK 0x00001f00 +#define SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK 0x0000e000 +#define SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK 0x00030000 +#define SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK 0x000c0000 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK 0x00100000 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK 0x00200000 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK 0x00400000 +#define SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK 0x00800000 + +#define SQ_DEBUG_CONST_MGR_FSM_MASK \ + (SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK | \ + SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) + +#define SQ_DEBUG_CONST_MGR_FSM(tex_const_event_state, reserved1, alu_const_event_state, reserved2, alu_const_cntx_valid, tex_const_cntx_valid, cntx0_vtx_event_done, cntx0_pix_event_done, cntx1_vtx_event_done, cntx1_pix_event_done) \ + ((tex_const_event_state << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT) | \ + (reserved1 << SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT) | \ + (alu_const_event_state << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT) | \ + (reserved2 << SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT) | \ + (alu_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT) | \ + (tex_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT) | \ + (cntx0_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT) | \ + (cntx0_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT) | \ + (cntx1_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT) | \ + (cntx1_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT)) + +#define SQ_DEBUG_CONST_MGR_FSM_GET_TEX_CONST_EVENT_STATE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_RESERVED1(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK) >> SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_ALU_CONST_EVENT_STATE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_RESERVED2(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK) >> SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_ALU_CONST_CNTX_VALID(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK) >> SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_TEX_CONST_CNTX_VALID(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK) >> SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX0_VTX_EVENT_DONE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX0_PIX_EVENT_DONE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX1_VTX_EVENT_DONE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_GET_CNTX1_PIX_EVENT_DONE(sq_debug_const_mgr_fsm) \ + ((sq_debug_const_mgr_fsm & SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) >> SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT) + +#define SQ_DEBUG_CONST_MGR_FSM_SET_TEX_CONST_EVENT_STATE(sq_debug_const_mgr_fsm_reg, tex_const_event_state) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_MASK) | (tex_const_event_state << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_RESERVED1(sq_debug_const_mgr_fsm_reg, reserved1) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_ALU_CONST_EVENT_STATE(sq_debug_const_mgr_fsm_reg, alu_const_event_state) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_MASK) | (alu_const_event_state << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_RESERVED2(sq_debug_const_mgr_fsm_reg, reserved2) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_ALU_CONST_CNTX_VALID(sq_debug_const_mgr_fsm_reg, alu_const_cntx_valid) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_MASK) | (alu_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_TEX_CONST_CNTX_VALID(sq_debug_const_mgr_fsm_reg, tex_const_cntx_valid) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_MASK) | (tex_const_cntx_valid << SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX0_VTX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx0_vtx_event_done) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_MASK) | (cntx0_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX0_PIX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx0_pix_event_done) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_MASK) | (cntx0_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX1_VTX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx1_vtx_event_done) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_MASK) | (cntx1_vtx_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SHIFT) +#define SQ_DEBUG_CONST_MGR_FSM_SET_CNTX1_PIX_EVENT_DONE(sq_debug_const_mgr_fsm_reg, cntx1_pix_event_done) \ + sq_debug_const_mgr_fsm_reg = (sq_debug_const_mgr_fsm_reg & ~SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_MASK) | (cntx1_pix_event_done << SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_const_mgr_fsm_t { + unsigned int tex_const_event_state : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE; + unsigned int reserved1 : SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE; + unsigned int alu_const_event_state : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE; + unsigned int reserved2 : SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE; + unsigned int alu_const_cntx_valid : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE; + unsigned int tex_const_cntx_valid : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE; + unsigned int cntx0_vtx_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE; + unsigned int cntx0_pix_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE; + unsigned int cntx1_vtx_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE; + unsigned int cntx1_pix_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE; + unsigned int : 8; + } sq_debug_const_mgr_fsm_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_const_mgr_fsm_t { + unsigned int : 8; + unsigned int cntx1_pix_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX1_PIX_EVENT_DONE_SIZE; + unsigned int cntx1_vtx_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX1_VTX_EVENT_DONE_SIZE; + unsigned int cntx0_pix_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX0_PIX_EVENT_DONE_SIZE; + unsigned int cntx0_vtx_event_done : SQ_DEBUG_CONST_MGR_FSM_CNTX0_VTX_EVENT_DONE_SIZE; + unsigned int tex_const_cntx_valid : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_CNTX_VALID_SIZE; + unsigned int alu_const_cntx_valid : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_CNTX_VALID_SIZE; + unsigned int reserved2 : SQ_DEBUG_CONST_MGR_FSM_RESERVED2_SIZE; + unsigned int alu_const_event_state : SQ_DEBUG_CONST_MGR_FSM_ALU_CONST_EVENT_STATE_SIZE; + unsigned int reserved1 : SQ_DEBUG_CONST_MGR_FSM_RESERVED1_SIZE; + unsigned int tex_const_event_state : SQ_DEBUG_CONST_MGR_FSM_TEX_CONST_EVENT_STATE_SIZE; + } sq_debug_const_mgr_fsm_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_const_mgr_fsm_t f; +} sq_debug_const_mgr_fsm_u; + + +/* + * SQ_DEBUG_TP_FSM struct + */ + +#define SQ_DEBUG_TP_FSM_EX_TP_SIZE 3 +#define SQ_DEBUG_TP_FSM_RESERVED0_SIZE 1 +#define SQ_DEBUG_TP_FSM_CF_TP_SIZE 4 +#define SQ_DEBUG_TP_FSM_IF_TP_SIZE 3 +#define SQ_DEBUG_TP_FSM_RESERVED1_SIZE 1 +#define SQ_DEBUG_TP_FSM_TIS_TP_SIZE 2 +#define SQ_DEBUG_TP_FSM_RESERVED2_SIZE 2 +#define SQ_DEBUG_TP_FSM_GS_TP_SIZE 2 +#define SQ_DEBUG_TP_FSM_RESERVED3_SIZE 2 +#define SQ_DEBUG_TP_FSM_FCR_TP_SIZE 2 +#define SQ_DEBUG_TP_FSM_RESERVED4_SIZE 2 +#define SQ_DEBUG_TP_FSM_FCS_TP_SIZE 2 +#define SQ_DEBUG_TP_FSM_RESERVED5_SIZE 2 +#define SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE 3 + +#define SQ_DEBUG_TP_FSM_EX_TP_SHIFT 0 +#define SQ_DEBUG_TP_FSM_RESERVED0_SHIFT 3 +#define SQ_DEBUG_TP_FSM_CF_TP_SHIFT 4 +#define SQ_DEBUG_TP_FSM_IF_TP_SHIFT 8 +#define SQ_DEBUG_TP_FSM_RESERVED1_SHIFT 11 +#define SQ_DEBUG_TP_FSM_TIS_TP_SHIFT 12 +#define SQ_DEBUG_TP_FSM_RESERVED2_SHIFT 14 +#define SQ_DEBUG_TP_FSM_GS_TP_SHIFT 16 +#define SQ_DEBUG_TP_FSM_RESERVED3_SHIFT 18 +#define SQ_DEBUG_TP_FSM_FCR_TP_SHIFT 20 +#define SQ_DEBUG_TP_FSM_RESERVED4_SHIFT 22 +#define SQ_DEBUG_TP_FSM_FCS_TP_SHIFT 24 +#define SQ_DEBUG_TP_FSM_RESERVED5_SHIFT 26 +#define SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT 28 + +#define SQ_DEBUG_TP_FSM_EX_TP_MASK 0x00000007 +#define SQ_DEBUG_TP_FSM_RESERVED0_MASK 0x00000008 +#define SQ_DEBUG_TP_FSM_CF_TP_MASK 0x000000f0 +#define SQ_DEBUG_TP_FSM_IF_TP_MASK 0x00000700 +#define SQ_DEBUG_TP_FSM_RESERVED1_MASK 0x00000800 +#define SQ_DEBUG_TP_FSM_TIS_TP_MASK 0x00003000 +#define SQ_DEBUG_TP_FSM_RESERVED2_MASK 0x0000c000 +#define SQ_DEBUG_TP_FSM_GS_TP_MASK 0x00030000 +#define SQ_DEBUG_TP_FSM_RESERVED3_MASK 0x000c0000 +#define SQ_DEBUG_TP_FSM_FCR_TP_MASK 0x00300000 +#define SQ_DEBUG_TP_FSM_RESERVED4_MASK 0x00c00000 +#define SQ_DEBUG_TP_FSM_FCS_TP_MASK 0x03000000 +#define SQ_DEBUG_TP_FSM_RESERVED5_MASK 0x0c000000 +#define SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK 0x70000000 + +#define SQ_DEBUG_TP_FSM_MASK \ + (SQ_DEBUG_TP_FSM_EX_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED0_MASK | \ + SQ_DEBUG_TP_FSM_CF_TP_MASK | \ + SQ_DEBUG_TP_FSM_IF_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED1_MASK | \ + SQ_DEBUG_TP_FSM_TIS_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED2_MASK | \ + SQ_DEBUG_TP_FSM_GS_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED3_MASK | \ + SQ_DEBUG_TP_FSM_FCR_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED4_MASK | \ + SQ_DEBUG_TP_FSM_FCS_TP_MASK | \ + SQ_DEBUG_TP_FSM_RESERVED5_MASK | \ + SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) + +#define SQ_DEBUG_TP_FSM(ex_tp, reserved0, cf_tp, if_tp, reserved1, tis_tp, reserved2, gs_tp, reserved3, fcr_tp, reserved4, fcs_tp, reserved5, arb_tr_tp) \ + ((ex_tp << SQ_DEBUG_TP_FSM_EX_TP_SHIFT) | \ + (reserved0 << SQ_DEBUG_TP_FSM_RESERVED0_SHIFT) | \ + (cf_tp << SQ_DEBUG_TP_FSM_CF_TP_SHIFT) | \ + (if_tp << SQ_DEBUG_TP_FSM_IF_TP_SHIFT) | \ + (reserved1 << SQ_DEBUG_TP_FSM_RESERVED1_SHIFT) | \ + (tis_tp << SQ_DEBUG_TP_FSM_TIS_TP_SHIFT) | \ + (reserved2 << SQ_DEBUG_TP_FSM_RESERVED2_SHIFT) | \ + (gs_tp << SQ_DEBUG_TP_FSM_GS_TP_SHIFT) | \ + (reserved3 << SQ_DEBUG_TP_FSM_RESERVED3_SHIFT) | \ + (fcr_tp << SQ_DEBUG_TP_FSM_FCR_TP_SHIFT) | \ + (reserved4 << SQ_DEBUG_TP_FSM_RESERVED4_SHIFT) | \ + (fcs_tp << SQ_DEBUG_TP_FSM_FCS_TP_SHIFT) | \ + (reserved5 << SQ_DEBUG_TP_FSM_RESERVED5_SHIFT) | \ + (arb_tr_tp << SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT)) + +#define SQ_DEBUG_TP_FSM_GET_EX_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_EX_TP_MASK) >> SQ_DEBUG_TP_FSM_EX_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED0(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED0_MASK) >> SQ_DEBUG_TP_FSM_RESERVED0_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_CF_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_CF_TP_MASK) >> SQ_DEBUG_TP_FSM_CF_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_IF_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_IF_TP_MASK) >> SQ_DEBUG_TP_FSM_IF_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED1(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED1_MASK) >> SQ_DEBUG_TP_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_TIS_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_TIS_TP_MASK) >> SQ_DEBUG_TP_FSM_TIS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED2(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED2_MASK) >> SQ_DEBUG_TP_FSM_RESERVED2_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_GS_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_GS_TP_MASK) >> SQ_DEBUG_TP_FSM_GS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED3(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED3_MASK) >> SQ_DEBUG_TP_FSM_RESERVED3_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_FCR_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_FCR_TP_MASK) >> SQ_DEBUG_TP_FSM_FCR_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED4(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED4_MASK) >> SQ_DEBUG_TP_FSM_RESERVED4_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_FCS_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_FCS_TP_MASK) >> SQ_DEBUG_TP_FSM_FCS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_RESERVED5(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_RESERVED5_MASK) >> SQ_DEBUG_TP_FSM_RESERVED5_SHIFT) +#define SQ_DEBUG_TP_FSM_GET_ARB_TR_TP(sq_debug_tp_fsm) \ + ((sq_debug_tp_fsm & SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) >> SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT) + +#define SQ_DEBUG_TP_FSM_SET_EX_TP(sq_debug_tp_fsm_reg, ex_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_EX_TP_MASK) | (ex_tp << SQ_DEBUG_TP_FSM_EX_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED0(sq_debug_tp_fsm_reg, reserved0) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_TP_FSM_RESERVED0_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_CF_TP(sq_debug_tp_fsm_reg, cf_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_CF_TP_MASK) | (cf_tp << SQ_DEBUG_TP_FSM_CF_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_IF_TP(sq_debug_tp_fsm_reg, if_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_IF_TP_MASK) | (if_tp << SQ_DEBUG_TP_FSM_IF_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED1(sq_debug_tp_fsm_reg, reserved1) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_TP_FSM_RESERVED1_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_TIS_TP(sq_debug_tp_fsm_reg, tis_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_TIS_TP_MASK) | (tis_tp << SQ_DEBUG_TP_FSM_TIS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED2(sq_debug_tp_fsm_reg, reserved2) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_TP_FSM_RESERVED2_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_GS_TP(sq_debug_tp_fsm_reg, gs_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_GS_TP_MASK) | (gs_tp << SQ_DEBUG_TP_FSM_GS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED3(sq_debug_tp_fsm_reg, reserved3) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_TP_FSM_RESERVED3_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_FCR_TP(sq_debug_tp_fsm_reg, fcr_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_FCR_TP_MASK) | (fcr_tp << SQ_DEBUG_TP_FSM_FCR_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED4(sq_debug_tp_fsm_reg, reserved4) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_TP_FSM_RESERVED4_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_FCS_TP(sq_debug_tp_fsm_reg, fcs_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_FCS_TP_MASK) | (fcs_tp << SQ_DEBUG_TP_FSM_FCS_TP_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_RESERVED5(sq_debug_tp_fsm_reg, reserved5) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_TP_FSM_RESERVED5_SHIFT) +#define SQ_DEBUG_TP_FSM_SET_ARB_TR_TP(sq_debug_tp_fsm_reg, arb_tr_tp) \ + sq_debug_tp_fsm_reg = (sq_debug_tp_fsm_reg & ~SQ_DEBUG_TP_FSM_ARB_TR_TP_MASK) | (arb_tr_tp << SQ_DEBUG_TP_FSM_ARB_TR_TP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_tp_fsm_t { + unsigned int ex_tp : SQ_DEBUG_TP_FSM_EX_TP_SIZE; + unsigned int reserved0 : SQ_DEBUG_TP_FSM_RESERVED0_SIZE; + unsigned int cf_tp : SQ_DEBUG_TP_FSM_CF_TP_SIZE; + unsigned int if_tp : SQ_DEBUG_TP_FSM_IF_TP_SIZE; + unsigned int reserved1 : SQ_DEBUG_TP_FSM_RESERVED1_SIZE; + unsigned int tis_tp : SQ_DEBUG_TP_FSM_TIS_TP_SIZE; + unsigned int reserved2 : SQ_DEBUG_TP_FSM_RESERVED2_SIZE; + unsigned int gs_tp : SQ_DEBUG_TP_FSM_GS_TP_SIZE; + unsigned int reserved3 : SQ_DEBUG_TP_FSM_RESERVED3_SIZE; + unsigned int fcr_tp : SQ_DEBUG_TP_FSM_FCR_TP_SIZE; + unsigned int reserved4 : SQ_DEBUG_TP_FSM_RESERVED4_SIZE; + unsigned int fcs_tp : SQ_DEBUG_TP_FSM_FCS_TP_SIZE; + unsigned int reserved5 : SQ_DEBUG_TP_FSM_RESERVED5_SIZE; + unsigned int arb_tr_tp : SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE; + unsigned int : 1; + } sq_debug_tp_fsm_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_tp_fsm_t { + unsigned int : 1; + unsigned int arb_tr_tp : SQ_DEBUG_TP_FSM_ARB_TR_TP_SIZE; + unsigned int reserved5 : SQ_DEBUG_TP_FSM_RESERVED5_SIZE; + unsigned int fcs_tp : SQ_DEBUG_TP_FSM_FCS_TP_SIZE; + unsigned int reserved4 : SQ_DEBUG_TP_FSM_RESERVED4_SIZE; + unsigned int fcr_tp : SQ_DEBUG_TP_FSM_FCR_TP_SIZE; + unsigned int reserved3 : SQ_DEBUG_TP_FSM_RESERVED3_SIZE; + unsigned int gs_tp : SQ_DEBUG_TP_FSM_GS_TP_SIZE; + unsigned int reserved2 : SQ_DEBUG_TP_FSM_RESERVED2_SIZE; + unsigned int tis_tp : SQ_DEBUG_TP_FSM_TIS_TP_SIZE; + unsigned int reserved1 : SQ_DEBUG_TP_FSM_RESERVED1_SIZE; + unsigned int if_tp : SQ_DEBUG_TP_FSM_IF_TP_SIZE; + unsigned int cf_tp : SQ_DEBUG_TP_FSM_CF_TP_SIZE; + unsigned int reserved0 : SQ_DEBUG_TP_FSM_RESERVED0_SIZE; + unsigned int ex_tp : SQ_DEBUG_TP_FSM_EX_TP_SIZE; + } sq_debug_tp_fsm_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_tp_fsm_t f; +} sq_debug_tp_fsm_u; + + +/* + * SQ_DEBUG_FSM_ALU_0 struct + */ + +#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE 4 +#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE 1 +#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE 3 + +#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT 0 +#define SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT 3 +#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT 4 +#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT 8 +#define SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT 11 +#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT 12 +#define SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT 15 +#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT 16 +#define SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT 19 +#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT 20 +#define SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT 23 +#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT 24 +#define SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT 27 +#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT 28 + +#define SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK 0x00000007 +#define SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK 0x00000008 +#define SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK 0x000000f0 +#define SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK 0x00000700 +#define SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK 0x00000800 +#define SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK 0x00007000 +#define SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK 0x00008000 +#define SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK 0x00070000 +#define SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK 0x00080000 +#define SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK 0x00700000 +#define SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK 0x00800000 +#define SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK 0x07000000 +#define SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK 0x08000000 +#define SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK 0x70000000 + +#define SQ_DEBUG_FSM_ALU_0_MASK \ + (SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK | \ + SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK | \ + SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK | \ + SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK | \ + SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK | \ + SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK | \ + SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) + +#define SQ_DEBUG_FSM_ALU_0(ex_alu_0, reserved0, cf_alu_0, if_alu_0, reserved1, du1_alu_0, reserved2, du0_alu_0, reserved3, ais_alu_0, reserved4, acs_alu_0, reserved5, arb_tr_alu) \ + ((ex_alu_0 << SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT) | \ + (reserved0 << SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT) | \ + (cf_alu_0 << SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT) | \ + (if_alu_0 << SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT) | \ + (reserved1 << SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT) | \ + (du1_alu_0 << SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT) | \ + (reserved2 << SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT) | \ + (du0_alu_0 << SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT) | \ + (reserved3 << SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT) | \ + (ais_alu_0 << SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT) | \ + (reserved4 << SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT) | \ + (acs_alu_0 << SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT) | \ + (reserved5 << SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT) | \ + (arb_tr_alu << SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT)) + +#define SQ_DEBUG_FSM_ALU_0_GET_EX_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_CF_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_IF_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED1(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_DU1_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED2(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_DU0_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED3(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_AIS_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED4(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_ACS_ALU_0(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_RESERVED5(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK) >> SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_GET_ARB_TR_ALU(sq_debug_fsm_alu_0) \ + ((sq_debug_fsm_alu_0 & SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) >> SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT) + +#define SQ_DEBUG_FSM_ALU_0_SET_EX_ALU_0(sq_debug_fsm_alu_0_reg, ex_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_EX_ALU_0_MASK) | (ex_alu_0 << SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED0(sq_debug_fsm_alu_0_reg, reserved0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_FSM_ALU_0_RESERVED0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_CF_ALU_0(sq_debug_fsm_alu_0_reg, cf_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_CF_ALU_0_MASK) | (cf_alu_0 << SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_IF_ALU_0(sq_debug_fsm_alu_0_reg, if_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_IF_ALU_0_MASK) | (if_alu_0 << SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED1(sq_debug_fsm_alu_0_reg, reserved1) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_FSM_ALU_0_RESERVED1_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_DU1_ALU_0(sq_debug_fsm_alu_0_reg, du1_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_MASK) | (du1_alu_0 << SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED2(sq_debug_fsm_alu_0_reg, reserved2) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_FSM_ALU_0_RESERVED2_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_DU0_ALU_0(sq_debug_fsm_alu_0_reg, du0_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_MASK) | (du0_alu_0 << SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED3(sq_debug_fsm_alu_0_reg, reserved3) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_FSM_ALU_0_RESERVED3_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_AIS_ALU_0(sq_debug_fsm_alu_0_reg, ais_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_MASK) | (ais_alu_0 << SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED4(sq_debug_fsm_alu_0_reg, reserved4) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_FSM_ALU_0_RESERVED4_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_ACS_ALU_0(sq_debug_fsm_alu_0_reg, acs_alu_0) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_MASK) | (acs_alu_0 << SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_RESERVED5(sq_debug_fsm_alu_0_reg, reserved5) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_FSM_ALU_0_RESERVED5_SHIFT) +#define SQ_DEBUG_FSM_ALU_0_SET_ARB_TR_ALU(sq_debug_fsm_alu_0_reg, arb_tr_alu) \ + sq_debug_fsm_alu_0_reg = (sq_debug_fsm_alu_0_reg & ~SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_MASK) | (arb_tr_alu << SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_fsm_alu_0_t { + unsigned int ex_alu_0 : SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE; + unsigned int reserved0 : SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE; + unsigned int cf_alu_0 : SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE; + unsigned int if_alu_0 : SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE; + unsigned int reserved1 : SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE; + unsigned int du1_alu_0 : SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE; + unsigned int reserved2 : SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE; + unsigned int du0_alu_0 : SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE; + unsigned int reserved3 : SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE; + unsigned int ais_alu_0 : SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE; + unsigned int reserved4 : SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE; + unsigned int acs_alu_0 : SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE; + unsigned int reserved5 : SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE; + unsigned int arb_tr_alu : SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE; + unsigned int : 1; + } sq_debug_fsm_alu_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_fsm_alu_0_t { + unsigned int : 1; + unsigned int arb_tr_alu : SQ_DEBUG_FSM_ALU_0_ARB_TR_ALU_SIZE; + unsigned int reserved5 : SQ_DEBUG_FSM_ALU_0_RESERVED5_SIZE; + unsigned int acs_alu_0 : SQ_DEBUG_FSM_ALU_0_ACS_ALU_0_SIZE; + unsigned int reserved4 : SQ_DEBUG_FSM_ALU_0_RESERVED4_SIZE; + unsigned int ais_alu_0 : SQ_DEBUG_FSM_ALU_0_AIS_ALU_0_SIZE; + unsigned int reserved3 : SQ_DEBUG_FSM_ALU_0_RESERVED3_SIZE; + unsigned int du0_alu_0 : SQ_DEBUG_FSM_ALU_0_DU0_ALU_0_SIZE; + unsigned int reserved2 : SQ_DEBUG_FSM_ALU_0_RESERVED2_SIZE; + unsigned int du1_alu_0 : SQ_DEBUG_FSM_ALU_0_DU1_ALU_0_SIZE; + unsigned int reserved1 : SQ_DEBUG_FSM_ALU_0_RESERVED1_SIZE; + unsigned int if_alu_0 : SQ_DEBUG_FSM_ALU_0_IF_ALU_0_SIZE; + unsigned int cf_alu_0 : SQ_DEBUG_FSM_ALU_0_CF_ALU_0_SIZE; + unsigned int reserved0 : SQ_DEBUG_FSM_ALU_0_RESERVED0_SIZE; + unsigned int ex_alu_0 : SQ_DEBUG_FSM_ALU_0_EX_ALU_0_SIZE; + } sq_debug_fsm_alu_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_fsm_alu_0_t f; +} sq_debug_fsm_alu_0_u; + + +/* + * SQ_DEBUG_FSM_ALU_1 struct + */ + +#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE 4 +#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE 3 +#define SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE 1 +#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE 3 + +#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT 0 +#define SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT 3 +#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT 4 +#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT 8 +#define SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT 11 +#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT 12 +#define SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT 15 +#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT 16 +#define SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT 19 +#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT 20 +#define SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT 23 +#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT 24 +#define SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT 27 +#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT 28 + +#define SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK 0x00000007 +#define SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK 0x00000008 +#define SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK 0x000000f0 +#define SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK 0x00000700 +#define SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK 0x00000800 +#define SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK 0x00007000 +#define SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK 0x00008000 +#define SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK 0x00070000 +#define SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK 0x00080000 +#define SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK 0x00700000 +#define SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK 0x00800000 +#define SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK 0x07000000 +#define SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK 0x08000000 +#define SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK 0x70000000 + +#define SQ_DEBUG_FSM_ALU_1_MASK \ + (SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK | \ + SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK | \ + SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK | \ + SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK | \ + SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK | \ + SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK | \ + SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK | \ + SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) + +#define SQ_DEBUG_FSM_ALU_1(ex_alu_0, reserved0, cf_alu_0, if_alu_0, reserved1, du1_alu_0, reserved2, du0_alu_0, reserved3, ais_alu_0, reserved4, acs_alu_0, reserved5, arb_tr_alu) \ + ((ex_alu_0 << SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT) | \ + (reserved0 << SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT) | \ + (cf_alu_0 << SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT) | \ + (if_alu_0 << SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT) | \ + (reserved1 << SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT) | \ + (du1_alu_0 << SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT) | \ + (reserved2 << SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT) | \ + (du0_alu_0 << SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT) | \ + (reserved3 << SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT) | \ + (ais_alu_0 << SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT) | \ + (reserved4 << SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT) | \ + (acs_alu_0 << SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT) | \ + (reserved5 << SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT) | \ + (arb_tr_alu << SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT)) + +#define SQ_DEBUG_FSM_ALU_1_GET_EX_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_CF_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_IF_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED1(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_DU1_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED2(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_DU0_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED3(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_AIS_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED4(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_ACS_ALU_0(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK) >> SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_RESERVED5(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK) >> SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_GET_ARB_TR_ALU(sq_debug_fsm_alu_1) \ + ((sq_debug_fsm_alu_1 & SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) >> SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT) + +#define SQ_DEBUG_FSM_ALU_1_SET_EX_ALU_0(sq_debug_fsm_alu_1_reg, ex_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_EX_ALU_0_MASK) | (ex_alu_0 << SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED0(sq_debug_fsm_alu_1_reg, reserved0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED0_MASK) | (reserved0 << SQ_DEBUG_FSM_ALU_1_RESERVED0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_CF_ALU_0(sq_debug_fsm_alu_1_reg, cf_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_CF_ALU_0_MASK) | (cf_alu_0 << SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_IF_ALU_0(sq_debug_fsm_alu_1_reg, if_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_IF_ALU_0_MASK) | (if_alu_0 << SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED1(sq_debug_fsm_alu_1_reg, reserved1) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_FSM_ALU_1_RESERVED1_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_DU1_ALU_0(sq_debug_fsm_alu_1_reg, du1_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_MASK) | (du1_alu_0 << SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED2(sq_debug_fsm_alu_1_reg, reserved2) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_FSM_ALU_1_RESERVED2_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_DU0_ALU_0(sq_debug_fsm_alu_1_reg, du0_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_MASK) | (du0_alu_0 << SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED3(sq_debug_fsm_alu_1_reg, reserved3) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED3_MASK) | (reserved3 << SQ_DEBUG_FSM_ALU_1_RESERVED3_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_AIS_ALU_0(sq_debug_fsm_alu_1_reg, ais_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_MASK) | (ais_alu_0 << SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED4(sq_debug_fsm_alu_1_reg, reserved4) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED4_MASK) | (reserved4 << SQ_DEBUG_FSM_ALU_1_RESERVED4_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_ACS_ALU_0(sq_debug_fsm_alu_1_reg, acs_alu_0) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_MASK) | (acs_alu_0 << SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_RESERVED5(sq_debug_fsm_alu_1_reg, reserved5) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_RESERVED5_MASK) | (reserved5 << SQ_DEBUG_FSM_ALU_1_RESERVED5_SHIFT) +#define SQ_DEBUG_FSM_ALU_1_SET_ARB_TR_ALU(sq_debug_fsm_alu_1_reg, arb_tr_alu) \ + sq_debug_fsm_alu_1_reg = (sq_debug_fsm_alu_1_reg & ~SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_MASK) | (arb_tr_alu << SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_fsm_alu_1_t { + unsigned int ex_alu_0 : SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE; + unsigned int reserved0 : SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE; + unsigned int cf_alu_0 : SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE; + unsigned int if_alu_0 : SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE; + unsigned int reserved1 : SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE; + unsigned int du1_alu_0 : SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE; + unsigned int reserved2 : SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE; + unsigned int du0_alu_0 : SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE; + unsigned int reserved3 : SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE; + unsigned int ais_alu_0 : SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE; + unsigned int reserved4 : SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE; + unsigned int acs_alu_0 : SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE; + unsigned int reserved5 : SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE; + unsigned int arb_tr_alu : SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE; + unsigned int : 1; + } sq_debug_fsm_alu_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_fsm_alu_1_t { + unsigned int : 1; + unsigned int arb_tr_alu : SQ_DEBUG_FSM_ALU_1_ARB_TR_ALU_SIZE; + unsigned int reserved5 : SQ_DEBUG_FSM_ALU_1_RESERVED5_SIZE; + unsigned int acs_alu_0 : SQ_DEBUG_FSM_ALU_1_ACS_ALU_0_SIZE; + unsigned int reserved4 : SQ_DEBUG_FSM_ALU_1_RESERVED4_SIZE; + unsigned int ais_alu_0 : SQ_DEBUG_FSM_ALU_1_AIS_ALU_0_SIZE; + unsigned int reserved3 : SQ_DEBUG_FSM_ALU_1_RESERVED3_SIZE; + unsigned int du0_alu_0 : SQ_DEBUG_FSM_ALU_1_DU0_ALU_0_SIZE; + unsigned int reserved2 : SQ_DEBUG_FSM_ALU_1_RESERVED2_SIZE; + unsigned int du1_alu_0 : SQ_DEBUG_FSM_ALU_1_DU1_ALU_0_SIZE; + unsigned int reserved1 : SQ_DEBUG_FSM_ALU_1_RESERVED1_SIZE; + unsigned int if_alu_0 : SQ_DEBUG_FSM_ALU_1_IF_ALU_0_SIZE; + unsigned int cf_alu_0 : SQ_DEBUG_FSM_ALU_1_CF_ALU_0_SIZE; + unsigned int reserved0 : SQ_DEBUG_FSM_ALU_1_RESERVED0_SIZE; + unsigned int ex_alu_0 : SQ_DEBUG_FSM_ALU_1_EX_ALU_0_SIZE; + } sq_debug_fsm_alu_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_fsm_alu_1_t f; +} sq_debug_fsm_alu_1_u; + + +/* + * SQ_DEBUG_EXP_ALLOC struct + */ + +#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE 4 +#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE 8 +#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE 3 +#define SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE 1 +#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE 6 + +#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT 0 +#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT 4 +#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT 12 +#define SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT 15 +#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT 16 + +#define SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK 0x0000000f +#define SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK 0x00000ff0 +#define SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK 0x00007000 +#define SQ_DEBUG_EXP_ALLOC_RESERVED_MASK 0x00008000 +#define SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK 0x003f0000 + +#define SQ_DEBUG_EXP_ALLOC_MASK \ + (SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK | \ + SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK | \ + SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK | \ + SQ_DEBUG_EXP_ALLOC_RESERVED_MASK | \ + SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) + +#define SQ_DEBUG_EXP_ALLOC(pos_buf_avail, color_buf_avail, ea_buf_avail, reserved, alloc_tbl_buf_avail) \ + ((pos_buf_avail << SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT) | \ + (color_buf_avail << SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT) | \ + (ea_buf_avail << SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT) | \ + (reserved << SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT) | \ + (alloc_tbl_buf_avail << SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT)) + +#define SQ_DEBUG_EXP_ALLOC_GET_POS_BUF_AVAIL(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_GET_COLOR_BUF_AVAIL(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_GET_EA_BUF_AVAIL(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_GET_RESERVED(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_RESERVED_MASK) >> SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_GET_ALLOC_TBL_BUF_AVAIL(sq_debug_exp_alloc) \ + ((sq_debug_exp_alloc & SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) >> SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT) + +#define SQ_DEBUG_EXP_ALLOC_SET_POS_BUF_AVAIL(sq_debug_exp_alloc_reg, pos_buf_avail) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_MASK) | (pos_buf_avail << SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_SET_COLOR_BUF_AVAIL(sq_debug_exp_alloc_reg, color_buf_avail) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_MASK) | (color_buf_avail << SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_SET_EA_BUF_AVAIL(sq_debug_exp_alloc_reg, ea_buf_avail) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_MASK) | (ea_buf_avail << SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_SET_RESERVED(sq_debug_exp_alloc_reg, reserved) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_RESERVED_MASK) | (reserved << SQ_DEBUG_EXP_ALLOC_RESERVED_SHIFT) +#define SQ_DEBUG_EXP_ALLOC_SET_ALLOC_TBL_BUF_AVAIL(sq_debug_exp_alloc_reg, alloc_tbl_buf_avail) \ + sq_debug_exp_alloc_reg = (sq_debug_exp_alloc_reg & ~SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_MASK) | (alloc_tbl_buf_avail << SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_exp_alloc_t { + unsigned int pos_buf_avail : SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE; + unsigned int color_buf_avail : SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE; + unsigned int ea_buf_avail : SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE; + unsigned int reserved : SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE; + unsigned int alloc_tbl_buf_avail : SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE; + unsigned int : 10; + } sq_debug_exp_alloc_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_exp_alloc_t { + unsigned int : 10; + unsigned int alloc_tbl_buf_avail : SQ_DEBUG_EXP_ALLOC_ALLOC_TBL_BUF_AVAIL_SIZE; + unsigned int reserved : SQ_DEBUG_EXP_ALLOC_RESERVED_SIZE; + unsigned int ea_buf_avail : SQ_DEBUG_EXP_ALLOC_EA_BUF_AVAIL_SIZE; + unsigned int color_buf_avail : SQ_DEBUG_EXP_ALLOC_COLOR_BUF_AVAIL_SIZE; + unsigned int pos_buf_avail : SQ_DEBUG_EXP_ALLOC_POS_BUF_AVAIL_SIZE; + } sq_debug_exp_alloc_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_exp_alloc_t f; +} sq_debug_exp_alloc_u; + + +/* + * SQ_DEBUG_PTR_BUFF struct + */ + +#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE 4 +#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE 3 +#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE 5 +#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE 1 +#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE 11 + +#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT 0 +#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT 1 +#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT 5 +#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT 6 +#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT 9 +#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT 14 +#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT 15 +#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT 16 +#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT 17 + +#define SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK 0x00000001 +#define SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK 0x0000001e +#define SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK 0x00000020 +#define SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK 0x000001c0 +#define SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK 0x00003e00 +#define SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK 0x00004000 +#define SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK 0x00008000 +#define SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK 0x00010000 +#define SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK 0x0ffe0000 + +#define SQ_DEBUG_PTR_BUFF_MASK \ + (SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK | \ + SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK | \ + SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK | \ + SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK | \ + SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK | \ + SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK | \ + SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK | \ + SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK | \ + SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) + +#define SQ_DEBUG_PTR_BUFF(end_of_buffer, dealloc_cnt, qual_new_vector, event_context_id, sc_event_id, qual_event, prim_type_polygon, ef_empty, vtx_sync_cnt) \ + ((end_of_buffer << SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT) | \ + (dealloc_cnt << SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT) | \ + (qual_new_vector << SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT) | \ + (event_context_id << SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT) | \ + (sc_event_id << SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT) | \ + (qual_event << SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT) | \ + (prim_type_polygon << SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT) | \ + (ef_empty << SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT) | \ + (vtx_sync_cnt << SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT)) + +#define SQ_DEBUG_PTR_BUFF_GET_END_OF_BUFFER(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK) >> SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_DEALLOC_CNT(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK) >> SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_QUAL_NEW_VECTOR(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK) >> SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_EVENT_CONTEXT_ID(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK) >> SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_SC_EVENT_ID(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK) >> SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_QUAL_EVENT(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK) >> SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_PRIM_TYPE_POLYGON(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK) >> SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_EF_EMPTY(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK) >> SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT) +#define SQ_DEBUG_PTR_BUFF_GET_VTX_SYNC_CNT(sq_debug_ptr_buff) \ + ((sq_debug_ptr_buff & SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) >> SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT) + +#define SQ_DEBUG_PTR_BUFF_SET_END_OF_BUFFER(sq_debug_ptr_buff_reg, end_of_buffer) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_MASK) | (end_of_buffer << SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_DEALLOC_CNT(sq_debug_ptr_buff_reg, dealloc_cnt) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_MASK) | (dealloc_cnt << SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_QUAL_NEW_VECTOR(sq_debug_ptr_buff_reg, qual_new_vector) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_MASK) | (qual_new_vector << SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_EVENT_CONTEXT_ID(sq_debug_ptr_buff_reg, event_context_id) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_MASK) | (event_context_id << SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_SC_EVENT_ID(sq_debug_ptr_buff_reg, sc_event_id) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_MASK) | (sc_event_id << SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_QUAL_EVENT(sq_debug_ptr_buff_reg, qual_event) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_QUAL_EVENT_MASK) | (qual_event << SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_PRIM_TYPE_POLYGON(sq_debug_ptr_buff_reg, prim_type_polygon) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_MASK) | (prim_type_polygon << SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_EF_EMPTY(sq_debug_ptr_buff_reg, ef_empty) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_EF_EMPTY_MASK) | (ef_empty << SQ_DEBUG_PTR_BUFF_EF_EMPTY_SHIFT) +#define SQ_DEBUG_PTR_BUFF_SET_VTX_SYNC_CNT(sq_debug_ptr_buff_reg, vtx_sync_cnt) \ + sq_debug_ptr_buff_reg = (sq_debug_ptr_buff_reg & ~SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_MASK) | (vtx_sync_cnt << SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_ptr_buff_t { + unsigned int end_of_buffer : SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE; + unsigned int dealloc_cnt : SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE; + unsigned int qual_new_vector : SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE; + unsigned int event_context_id : SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE; + unsigned int sc_event_id : SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE; + unsigned int qual_event : SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE; + unsigned int prim_type_polygon : SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE; + unsigned int ef_empty : SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE; + unsigned int vtx_sync_cnt : SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE; + unsigned int : 4; + } sq_debug_ptr_buff_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_ptr_buff_t { + unsigned int : 4; + unsigned int vtx_sync_cnt : SQ_DEBUG_PTR_BUFF_VTX_SYNC_CNT_SIZE; + unsigned int ef_empty : SQ_DEBUG_PTR_BUFF_EF_EMPTY_SIZE; + unsigned int prim_type_polygon : SQ_DEBUG_PTR_BUFF_PRIM_TYPE_POLYGON_SIZE; + unsigned int qual_event : SQ_DEBUG_PTR_BUFF_QUAL_EVENT_SIZE; + unsigned int sc_event_id : SQ_DEBUG_PTR_BUFF_SC_EVENT_ID_SIZE; + unsigned int event_context_id : SQ_DEBUG_PTR_BUFF_EVENT_CONTEXT_ID_SIZE; + unsigned int qual_new_vector : SQ_DEBUG_PTR_BUFF_QUAL_NEW_VECTOR_SIZE; + unsigned int dealloc_cnt : SQ_DEBUG_PTR_BUFF_DEALLOC_CNT_SIZE; + unsigned int end_of_buffer : SQ_DEBUG_PTR_BUFF_END_OF_BUFFER_SIZE; + } sq_debug_ptr_buff_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_ptr_buff_t f; +} sq_debug_ptr_buff_u; + + +/* + * SQ_DEBUG_GPR_VTX struct + */ + +#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE 7 +#define SQ_DEBUG_GPR_VTX_RESERVED_SIZE 1 +#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE 7 +#define SQ_DEBUG_GPR_VTX_RESERVED1_SIZE 1 +#define SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE 7 +#define SQ_DEBUG_GPR_VTX_RESERVED2_SIZE 1 +#define SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE 7 + +#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT 0 +#define SQ_DEBUG_GPR_VTX_RESERVED_SHIFT 7 +#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT 8 +#define SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT 15 +#define SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT 16 +#define SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT 23 +#define SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT 24 + +#define SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK 0x0000007f +#define SQ_DEBUG_GPR_VTX_RESERVED_MASK 0x00000080 +#define SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK 0x00007f00 +#define SQ_DEBUG_GPR_VTX_RESERVED1_MASK 0x00008000 +#define SQ_DEBUG_GPR_VTX_VTX_MAX_MASK 0x007f0000 +#define SQ_DEBUG_GPR_VTX_RESERVED2_MASK 0x00800000 +#define SQ_DEBUG_GPR_VTX_VTX_FREE_MASK 0x7f000000 + +#define SQ_DEBUG_GPR_VTX_MASK \ + (SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK | \ + SQ_DEBUG_GPR_VTX_RESERVED_MASK | \ + SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK | \ + SQ_DEBUG_GPR_VTX_RESERVED1_MASK | \ + SQ_DEBUG_GPR_VTX_VTX_MAX_MASK | \ + SQ_DEBUG_GPR_VTX_RESERVED2_MASK | \ + SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) + +#define SQ_DEBUG_GPR_VTX(vtx_tail_ptr, reserved, vtx_head_ptr, reserved1, vtx_max, reserved2, vtx_free) \ + ((vtx_tail_ptr << SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT) | \ + (reserved << SQ_DEBUG_GPR_VTX_RESERVED_SHIFT) | \ + (vtx_head_ptr << SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT) | \ + (reserved1 << SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT) | \ + (vtx_max << SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT) | \ + (reserved2 << SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT) | \ + (vtx_free << SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT)) + +#define SQ_DEBUG_GPR_VTX_GET_VTX_TAIL_PTR(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK) >> SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_RESERVED(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_VTX_HEAD_PTR(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK) >> SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_RESERVED1(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED1_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_VTX_MAX(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_MAX_MASK) >> SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_RESERVED2(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_RESERVED2_MASK) >> SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT) +#define SQ_DEBUG_GPR_VTX_GET_VTX_FREE(sq_debug_gpr_vtx) \ + ((sq_debug_gpr_vtx & SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) >> SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT) + +#define SQ_DEBUG_GPR_VTX_SET_VTX_TAIL_PTR(sq_debug_gpr_vtx_reg, vtx_tail_ptr) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_MASK) | (vtx_tail_ptr << SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_RESERVED(sq_debug_gpr_vtx_reg, reserved) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED_MASK) | (reserved << SQ_DEBUG_GPR_VTX_RESERVED_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_VTX_HEAD_PTR(sq_debug_gpr_vtx_reg, vtx_head_ptr) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_MASK) | (vtx_head_ptr << SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_RESERVED1(sq_debug_gpr_vtx_reg, reserved1) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_GPR_VTX_RESERVED1_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_VTX_MAX(sq_debug_gpr_vtx_reg, vtx_max) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_MAX_MASK) | (vtx_max << SQ_DEBUG_GPR_VTX_VTX_MAX_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_RESERVED2(sq_debug_gpr_vtx_reg, reserved2) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_GPR_VTX_RESERVED2_SHIFT) +#define SQ_DEBUG_GPR_VTX_SET_VTX_FREE(sq_debug_gpr_vtx_reg, vtx_free) \ + sq_debug_gpr_vtx_reg = (sq_debug_gpr_vtx_reg & ~SQ_DEBUG_GPR_VTX_VTX_FREE_MASK) | (vtx_free << SQ_DEBUG_GPR_VTX_VTX_FREE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_gpr_vtx_t { + unsigned int vtx_tail_ptr : SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE; + unsigned int reserved : SQ_DEBUG_GPR_VTX_RESERVED_SIZE; + unsigned int vtx_head_ptr : SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE; + unsigned int reserved1 : SQ_DEBUG_GPR_VTX_RESERVED1_SIZE; + unsigned int vtx_max : SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE; + unsigned int reserved2 : SQ_DEBUG_GPR_VTX_RESERVED2_SIZE; + unsigned int vtx_free : SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE; + unsigned int : 1; + } sq_debug_gpr_vtx_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_gpr_vtx_t { + unsigned int : 1; + unsigned int vtx_free : SQ_DEBUG_GPR_VTX_VTX_FREE_SIZE; + unsigned int reserved2 : SQ_DEBUG_GPR_VTX_RESERVED2_SIZE; + unsigned int vtx_max : SQ_DEBUG_GPR_VTX_VTX_MAX_SIZE; + unsigned int reserved1 : SQ_DEBUG_GPR_VTX_RESERVED1_SIZE; + unsigned int vtx_head_ptr : SQ_DEBUG_GPR_VTX_VTX_HEAD_PTR_SIZE; + unsigned int reserved : SQ_DEBUG_GPR_VTX_RESERVED_SIZE; + unsigned int vtx_tail_ptr : SQ_DEBUG_GPR_VTX_VTX_TAIL_PTR_SIZE; + } sq_debug_gpr_vtx_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_gpr_vtx_t f; +} sq_debug_gpr_vtx_u; + + +/* + * SQ_DEBUG_GPR_PIX struct + */ + +#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE 7 +#define SQ_DEBUG_GPR_PIX_RESERVED_SIZE 1 +#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE 7 +#define SQ_DEBUG_GPR_PIX_RESERVED1_SIZE 1 +#define SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE 7 +#define SQ_DEBUG_GPR_PIX_RESERVED2_SIZE 1 +#define SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE 7 + +#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT 0 +#define SQ_DEBUG_GPR_PIX_RESERVED_SHIFT 7 +#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT 8 +#define SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT 15 +#define SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT 16 +#define SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT 23 +#define SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT 24 + +#define SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK 0x0000007f +#define SQ_DEBUG_GPR_PIX_RESERVED_MASK 0x00000080 +#define SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK 0x00007f00 +#define SQ_DEBUG_GPR_PIX_RESERVED1_MASK 0x00008000 +#define SQ_DEBUG_GPR_PIX_PIX_MAX_MASK 0x007f0000 +#define SQ_DEBUG_GPR_PIX_RESERVED2_MASK 0x00800000 +#define SQ_DEBUG_GPR_PIX_PIX_FREE_MASK 0x7f000000 + +#define SQ_DEBUG_GPR_PIX_MASK \ + (SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK | \ + SQ_DEBUG_GPR_PIX_RESERVED_MASK | \ + SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK | \ + SQ_DEBUG_GPR_PIX_RESERVED1_MASK | \ + SQ_DEBUG_GPR_PIX_PIX_MAX_MASK | \ + SQ_DEBUG_GPR_PIX_RESERVED2_MASK | \ + SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) + +#define SQ_DEBUG_GPR_PIX(pix_tail_ptr, reserved, pix_head_ptr, reserved1, pix_max, reserved2, pix_free) \ + ((pix_tail_ptr << SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT) | \ + (reserved << SQ_DEBUG_GPR_PIX_RESERVED_SHIFT) | \ + (pix_head_ptr << SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT) | \ + (reserved1 << SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT) | \ + (pix_max << SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT) | \ + (reserved2 << SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT) | \ + (pix_free << SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT)) + +#define SQ_DEBUG_GPR_PIX_GET_PIX_TAIL_PTR(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK) >> SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_RESERVED(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_PIX_HEAD_PTR(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK) >> SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_RESERVED1(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED1_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_PIX_MAX(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_MAX_MASK) >> SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_RESERVED2(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_RESERVED2_MASK) >> SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT) +#define SQ_DEBUG_GPR_PIX_GET_PIX_FREE(sq_debug_gpr_pix) \ + ((sq_debug_gpr_pix & SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) >> SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT) + +#define SQ_DEBUG_GPR_PIX_SET_PIX_TAIL_PTR(sq_debug_gpr_pix_reg, pix_tail_ptr) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_MASK) | (pix_tail_ptr << SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_RESERVED(sq_debug_gpr_pix_reg, reserved) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED_MASK) | (reserved << SQ_DEBUG_GPR_PIX_RESERVED_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_PIX_HEAD_PTR(sq_debug_gpr_pix_reg, pix_head_ptr) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_MASK) | (pix_head_ptr << SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_RESERVED1(sq_debug_gpr_pix_reg, reserved1) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED1_MASK) | (reserved1 << SQ_DEBUG_GPR_PIX_RESERVED1_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_PIX_MAX(sq_debug_gpr_pix_reg, pix_max) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_MAX_MASK) | (pix_max << SQ_DEBUG_GPR_PIX_PIX_MAX_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_RESERVED2(sq_debug_gpr_pix_reg, reserved2) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_RESERVED2_MASK) | (reserved2 << SQ_DEBUG_GPR_PIX_RESERVED2_SHIFT) +#define SQ_DEBUG_GPR_PIX_SET_PIX_FREE(sq_debug_gpr_pix_reg, pix_free) \ + sq_debug_gpr_pix_reg = (sq_debug_gpr_pix_reg & ~SQ_DEBUG_GPR_PIX_PIX_FREE_MASK) | (pix_free << SQ_DEBUG_GPR_PIX_PIX_FREE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_gpr_pix_t { + unsigned int pix_tail_ptr : SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE; + unsigned int reserved : SQ_DEBUG_GPR_PIX_RESERVED_SIZE; + unsigned int pix_head_ptr : SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE; + unsigned int reserved1 : SQ_DEBUG_GPR_PIX_RESERVED1_SIZE; + unsigned int pix_max : SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE; + unsigned int reserved2 : SQ_DEBUG_GPR_PIX_RESERVED2_SIZE; + unsigned int pix_free : SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE; + unsigned int : 1; + } sq_debug_gpr_pix_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_gpr_pix_t { + unsigned int : 1; + unsigned int pix_free : SQ_DEBUG_GPR_PIX_PIX_FREE_SIZE; + unsigned int reserved2 : SQ_DEBUG_GPR_PIX_RESERVED2_SIZE; + unsigned int pix_max : SQ_DEBUG_GPR_PIX_PIX_MAX_SIZE; + unsigned int reserved1 : SQ_DEBUG_GPR_PIX_RESERVED1_SIZE; + unsigned int pix_head_ptr : SQ_DEBUG_GPR_PIX_PIX_HEAD_PTR_SIZE; + unsigned int reserved : SQ_DEBUG_GPR_PIX_RESERVED_SIZE; + unsigned int pix_tail_ptr : SQ_DEBUG_GPR_PIX_PIX_TAIL_PTR_SIZE; + } sq_debug_gpr_pix_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_gpr_pix_t f; +} sq_debug_gpr_pix_u; + + +/* + * SQ_DEBUG_TB_STATUS_SEL struct + */ + +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE 4 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE 3 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE 4 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE 1 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE 1 +#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE 2 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE 4 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE 3 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE 6 +#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE 2 +#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE 1 + +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT 0 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT 4 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT 7 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT 11 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT 12 +#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT 14 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT 16 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT 20 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT 23 +#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT 29 +#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT 31 + +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK 0x0000000f +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK 0x00000070 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK 0x00000780 +#define SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK 0x00000800 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK 0x00001000 +#define SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK 0x0000c000 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK 0x000f0000 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK 0x00700000 +#define SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK 0x1f800000 +#define SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK 0x60000000 +#define SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK 0x80000000 + +#define SQ_DEBUG_TB_STATUS_SEL_MASK \ + (SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK | \ + SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) + +#define SQ_DEBUG_TB_STATUS_SEL(vtx_tb_status_reg_sel, vtx_tb_state_mem_dw_sel, vtx_tb_state_mem_rd_addr, vtx_tb_state_mem_rd_en, pix_tb_state_mem_rd_en, debug_bus_trigger_sel, pix_tb_status_reg_sel, pix_tb_state_mem_dw_sel, pix_tb_state_mem_rd_addr, vc_thread_buf_dly, disable_strict_ctx_sync) \ + ((vtx_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT) | \ + (vtx_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT) | \ + (vtx_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT) | \ + (vtx_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT) | \ + (pix_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT) | \ + (debug_bus_trigger_sel << SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT) | \ + (pix_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT) | \ + (pix_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT) | \ + (pix_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT) | \ + (vc_thread_buf_dly << SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT) | \ + (disable_strict_ctx_sync << SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT)) + +#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_VTX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_DEBUG_BUS_TRIGGER_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_PIX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK) >> SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_VC_THREAD_BUF_DLY(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK) >> SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_GET_DISABLE_STRICT_CTX_SYNC(sq_debug_tb_status_sel) \ + ((sq_debug_tb_status_sel & SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) >> SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT) + +#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel_reg, vtx_tb_status_reg_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_MASK) | (vtx_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_dw_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_MASK) | (vtx_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_rd_addr) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_MASK) | (vtx_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_VTX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel_reg, vtx_tb_state_mem_rd_en) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_MASK) | (vtx_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_RD_EN(sq_debug_tb_status_sel_reg, pix_tb_state_mem_rd_en) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_MASK) | (pix_tb_state_mem_rd_en << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_DEBUG_BUS_TRIGGER_SEL(sq_debug_tb_status_sel_reg, debug_bus_trigger_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_MASK) | (debug_bus_trigger_sel << SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATUS_REG_SEL(sq_debug_tb_status_sel_reg, pix_tb_status_reg_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_MASK) | (pix_tb_status_reg_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_DW_SEL(sq_debug_tb_status_sel_reg, pix_tb_state_mem_dw_sel) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_MASK) | (pix_tb_state_mem_dw_sel << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_PIX_TB_STATE_MEM_RD_ADDR(sq_debug_tb_status_sel_reg, pix_tb_state_mem_rd_addr) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_MASK) | (pix_tb_state_mem_rd_addr << SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_VC_THREAD_BUF_DLY(sq_debug_tb_status_sel_reg, vc_thread_buf_dly) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_MASK) | (vc_thread_buf_dly << SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SHIFT) +#define SQ_DEBUG_TB_STATUS_SEL_SET_DISABLE_STRICT_CTX_SYNC(sq_debug_tb_status_sel_reg, disable_strict_ctx_sync) \ + sq_debug_tb_status_sel_reg = (sq_debug_tb_status_sel_reg & ~SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_MASK) | (disable_strict_ctx_sync << SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_tb_status_sel_t { + unsigned int vtx_tb_status_reg_sel : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE; + unsigned int vtx_tb_state_mem_dw_sel : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE; + unsigned int vtx_tb_state_mem_rd_addr : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE; + unsigned int vtx_tb_state_mem_rd_en : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE; + unsigned int pix_tb_state_mem_rd_en : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE; + unsigned int : 1; + unsigned int debug_bus_trigger_sel : SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE; + unsigned int pix_tb_status_reg_sel : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE; + unsigned int pix_tb_state_mem_dw_sel : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE; + unsigned int pix_tb_state_mem_rd_addr : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE; + unsigned int vc_thread_buf_dly : SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE; + unsigned int disable_strict_ctx_sync : SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE; + } sq_debug_tb_status_sel_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_tb_status_sel_t { + unsigned int disable_strict_ctx_sync : SQ_DEBUG_TB_STATUS_SEL_DISABLE_STRICT_CTX_SYNC_SIZE; + unsigned int vc_thread_buf_dly : SQ_DEBUG_TB_STATUS_SEL_VC_THREAD_BUF_DLY_SIZE; + unsigned int pix_tb_state_mem_rd_addr : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_ADDR_SIZE; + unsigned int pix_tb_state_mem_dw_sel : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_DW_SEL_SIZE; + unsigned int pix_tb_status_reg_sel : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATUS_REG_SEL_SIZE; + unsigned int debug_bus_trigger_sel : SQ_DEBUG_TB_STATUS_SEL_DEBUG_BUS_TRIGGER_SEL_SIZE; + unsigned int : 1; + unsigned int pix_tb_state_mem_rd_en : SQ_DEBUG_TB_STATUS_SEL_PIX_TB_STATE_MEM_RD_EN_SIZE; + unsigned int vtx_tb_state_mem_rd_en : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_EN_SIZE; + unsigned int vtx_tb_state_mem_rd_addr : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_RD_ADDR_SIZE; + unsigned int vtx_tb_state_mem_dw_sel : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATE_MEM_DW_SEL_SIZE; + unsigned int vtx_tb_status_reg_sel : SQ_DEBUG_TB_STATUS_SEL_VTX_TB_STATUS_REG_SEL_SIZE; + } sq_debug_tb_status_sel_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_tb_status_sel_t f; +} sq_debug_tb_status_sel_u; + + +/* + * SQ_DEBUG_VTX_TB_0 struct + */ + +#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE 4 +#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE 1 +#define SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE 1 + +#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT 0 +#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT 4 +#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT 8 +#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT 12 +#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT 16 +#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT 20 +#define SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT 21 + +#define SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK 0x0000000f +#define SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK 0x000000f0 +#define SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK 0x00000f00 +#define SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK 0x0000f000 +#define SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK 0x000f0000 +#define SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK 0x00100000 +#define SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK 0x00200000 + +#define SQ_DEBUG_VTX_TB_0_MASK \ + (SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK | \ + SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK | \ + SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK | \ + SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK | \ + SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK | \ + SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK | \ + SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) + +#define SQ_DEBUG_VTX_TB_0(vtx_head_ptr_q, tail_ptr_q, full_cnt_q, nxt_pos_alloc_cnt, nxt_pc_alloc_cnt, sx_event_full, busy_q) \ + ((vtx_head_ptr_q << SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT) | \ + (tail_ptr_q << SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT) | \ + (full_cnt_q << SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT) | \ + (nxt_pos_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT) | \ + (nxt_pc_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT) | \ + (sx_event_full << SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT) | \ + (busy_q << SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT)) + +#define SQ_DEBUG_VTX_TB_0_GET_VTX_HEAD_PTR_Q(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK) >> SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_TAIL_PTR_Q(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK) >> SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_FULL_CNT_Q(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK) >> SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_NXT_POS_ALLOC_CNT(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK) >> SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_NXT_PC_ALLOC_CNT(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK) >> SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_SX_EVENT_FULL(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK) >> SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT) +#define SQ_DEBUG_VTX_TB_0_GET_BUSY_Q(sq_debug_vtx_tb_0) \ + ((sq_debug_vtx_tb_0 & SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) >> SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT) + +#define SQ_DEBUG_VTX_TB_0_SET_VTX_HEAD_PTR_Q(sq_debug_vtx_tb_0_reg, vtx_head_ptr_q) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_MASK) | (vtx_head_ptr_q << SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_TAIL_PTR_Q(sq_debug_vtx_tb_0_reg, tail_ptr_q) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_MASK) | (tail_ptr_q << SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_FULL_CNT_Q(sq_debug_vtx_tb_0_reg, full_cnt_q) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_MASK) | (full_cnt_q << SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_NXT_POS_ALLOC_CNT(sq_debug_vtx_tb_0_reg, nxt_pos_alloc_cnt) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_MASK) | (nxt_pos_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_NXT_PC_ALLOC_CNT(sq_debug_vtx_tb_0_reg, nxt_pc_alloc_cnt) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_MASK) | (nxt_pc_alloc_cnt << SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_SX_EVENT_FULL(sq_debug_vtx_tb_0_reg, sx_event_full) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_MASK) | (sx_event_full << SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SHIFT) +#define SQ_DEBUG_VTX_TB_0_SET_BUSY_Q(sq_debug_vtx_tb_0_reg, busy_q) \ + sq_debug_vtx_tb_0_reg = (sq_debug_vtx_tb_0_reg & ~SQ_DEBUG_VTX_TB_0_BUSY_Q_MASK) | (busy_q << SQ_DEBUG_VTX_TB_0_BUSY_Q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_0_t { + unsigned int vtx_head_ptr_q : SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE; + unsigned int tail_ptr_q : SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE; + unsigned int full_cnt_q : SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE; + unsigned int nxt_pos_alloc_cnt : SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE; + unsigned int nxt_pc_alloc_cnt : SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE; + unsigned int sx_event_full : SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE; + unsigned int busy_q : SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE; + unsigned int : 10; + } sq_debug_vtx_tb_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_0_t { + unsigned int : 10; + unsigned int busy_q : SQ_DEBUG_VTX_TB_0_BUSY_Q_SIZE; + unsigned int sx_event_full : SQ_DEBUG_VTX_TB_0_SX_EVENT_FULL_SIZE; + unsigned int nxt_pc_alloc_cnt : SQ_DEBUG_VTX_TB_0_NXT_PC_ALLOC_CNT_SIZE; + unsigned int nxt_pos_alloc_cnt : SQ_DEBUG_VTX_TB_0_NXT_POS_ALLOC_CNT_SIZE; + unsigned int full_cnt_q : SQ_DEBUG_VTX_TB_0_FULL_CNT_Q_SIZE; + unsigned int tail_ptr_q : SQ_DEBUG_VTX_TB_0_TAIL_PTR_Q_SIZE; + unsigned int vtx_head_ptr_q : SQ_DEBUG_VTX_TB_0_VTX_HEAD_PTR_Q_SIZE; + } sq_debug_vtx_tb_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_vtx_tb_0_t f; +} sq_debug_vtx_tb_0_u; + + +/* + * SQ_DEBUG_VTX_TB_1 struct + */ + +#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE 16 + +#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT 0 + +#define SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK 0x0000ffff + +#define SQ_DEBUG_VTX_TB_1_MASK \ + (SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) + +#define SQ_DEBUG_VTX_TB_1(vs_done_ptr) \ + ((vs_done_ptr << SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT)) + +#define SQ_DEBUG_VTX_TB_1_GET_VS_DONE_PTR(sq_debug_vtx_tb_1) \ + ((sq_debug_vtx_tb_1 & SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) >> SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT) + +#define SQ_DEBUG_VTX_TB_1_SET_VS_DONE_PTR(sq_debug_vtx_tb_1_reg, vs_done_ptr) \ + sq_debug_vtx_tb_1_reg = (sq_debug_vtx_tb_1_reg & ~SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_MASK) | (vs_done_ptr << SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_1_t { + unsigned int vs_done_ptr : SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE; + unsigned int : 16; + } sq_debug_vtx_tb_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_1_t { + unsigned int : 16; + unsigned int vs_done_ptr : SQ_DEBUG_VTX_TB_1_VS_DONE_PTR_SIZE; + } sq_debug_vtx_tb_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_vtx_tb_1_t f; +} sq_debug_vtx_tb_1_u; + + +/* + * SQ_DEBUG_VTX_TB_STATUS_REG struct + */ + +#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE 32 + +#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT 0 + +#define SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK 0xffffffff + +#define SQ_DEBUG_VTX_TB_STATUS_REG_MASK \ + (SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) + +#define SQ_DEBUG_VTX_TB_STATUS_REG(vs_status_reg) \ + ((vs_status_reg << SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT)) + +#define SQ_DEBUG_VTX_TB_STATUS_REG_GET_VS_STATUS_REG(sq_debug_vtx_tb_status_reg) \ + ((sq_debug_vtx_tb_status_reg & SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) >> SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT) + +#define SQ_DEBUG_VTX_TB_STATUS_REG_SET_VS_STATUS_REG(sq_debug_vtx_tb_status_reg_reg, vs_status_reg) \ + sq_debug_vtx_tb_status_reg_reg = (sq_debug_vtx_tb_status_reg_reg & ~SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_MASK) | (vs_status_reg << SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_status_reg_t { + unsigned int vs_status_reg : SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE; + } sq_debug_vtx_tb_status_reg_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_status_reg_t { + unsigned int vs_status_reg : SQ_DEBUG_VTX_TB_STATUS_REG_VS_STATUS_REG_SIZE; + } sq_debug_vtx_tb_status_reg_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_vtx_tb_status_reg_t f; +} sq_debug_vtx_tb_status_reg_u; + + +/* + * SQ_DEBUG_VTX_TB_STATE_MEM struct + */ + +#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE 32 + +#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT 0 + +#define SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK 0xffffffff + +#define SQ_DEBUG_VTX_TB_STATE_MEM_MASK \ + (SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) + +#define SQ_DEBUG_VTX_TB_STATE_MEM(vs_state_mem) \ + ((vs_state_mem << SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT)) + +#define SQ_DEBUG_VTX_TB_STATE_MEM_GET_VS_STATE_MEM(sq_debug_vtx_tb_state_mem) \ + ((sq_debug_vtx_tb_state_mem & SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) >> SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT) + +#define SQ_DEBUG_VTX_TB_STATE_MEM_SET_VS_STATE_MEM(sq_debug_vtx_tb_state_mem_reg, vs_state_mem) \ + sq_debug_vtx_tb_state_mem_reg = (sq_debug_vtx_tb_state_mem_reg & ~SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_MASK) | (vs_state_mem << SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_state_mem_t { + unsigned int vs_state_mem : SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE; + } sq_debug_vtx_tb_state_mem_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_vtx_tb_state_mem_t { + unsigned int vs_state_mem : SQ_DEBUG_VTX_TB_STATE_MEM_VS_STATE_MEM_SIZE; + } sq_debug_vtx_tb_state_mem_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_vtx_tb_state_mem_t f; +} sq_debug_vtx_tb_state_mem_u; + + +/* + * SQ_DEBUG_PIX_TB_0 struct + */ + +#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE 6 +#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE 6 +#define SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE 7 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE 6 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE 6 +#define SQ_DEBUG_PIX_TB_0_BUSY_SIZE 1 + +#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT 0 +#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT 6 +#define SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT 12 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT 19 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT 25 +#define SQ_DEBUG_PIX_TB_0_BUSY_SHIFT 31 + +#define SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK 0x0000003f +#define SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK 0x00000fc0 +#define SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK 0x0007f000 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK 0x01f80000 +#define SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK 0x7e000000 +#define SQ_DEBUG_PIX_TB_0_BUSY_MASK 0x80000000 + +#define SQ_DEBUG_PIX_TB_0_MASK \ + (SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK | \ + SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK | \ + SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK | \ + SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK | \ + SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK | \ + SQ_DEBUG_PIX_TB_0_BUSY_MASK) + +#define SQ_DEBUG_PIX_TB_0(pix_head_ptr, tail_ptr, full_cnt, nxt_pix_alloc_cnt, nxt_pix_exp_cnt, busy) \ + ((pix_head_ptr << SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT) | \ + (tail_ptr << SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT) | \ + (full_cnt << SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT) | \ + (nxt_pix_alloc_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT) | \ + (nxt_pix_exp_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT) | \ + (busy << SQ_DEBUG_PIX_TB_0_BUSY_SHIFT)) + +#define SQ_DEBUG_PIX_TB_0_GET_PIX_HEAD_PTR(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK) >> SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_TAIL_PTR(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK) >> SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_FULL_CNT(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_NXT_PIX_ALLOC_CNT(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_NXT_PIX_EXP_CNT(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK) >> SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_GET_BUSY(sq_debug_pix_tb_0) \ + ((sq_debug_pix_tb_0 & SQ_DEBUG_PIX_TB_0_BUSY_MASK) >> SQ_DEBUG_PIX_TB_0_BUSY_SHIFT) + +#define SQ_DEBUG_PIX_TB_0_SET_PIX_HEAD_PTR(sq_debug_pix_tb_0_reg, pix_head_ptr) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_MASK) | (pix_head_ptr << SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_TAIL_PTR(sq_debug_pix_tb_0_reg, tail_ptr) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_TAIL_PTR_MASK) | (tail_ptr << SQ_DEBUG_PIX_TB_0_TAIL_PTR_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_FULL_CNT(sq_debug_pix_tb_0_reg, full_cnt) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_FULL_CNT_MASK) | (full_cnt << SQ_DEBUG_PIX_TB_0_FULL_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_NXT_PIX_ALLOC_CNT(sq_debug_pix_tb_0_reg, nxt_pix_alloc_cnt) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_MASK) | (nxt_pix_alloc_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_NXT_PIX_EXP_CNT(sq_debug_pix_tb_0_reg, nxt_pix_exp_cnt) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_MASK) | (nxt_pix_exp_cnt << SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SHIFT) +#define SQ_DEBUG_PIX_TB_0_SET_BUSY(sq_debug_pix_tb_0_reg, busy) \ + sq_debug_pix_tb_0_reg = (sq_debug_pix_tb_0_reg & ~SQ_DEBUG_PIX_TB_0_BUSY_MASK) | (busy << SQ_DEBUG_PIX_TB_0_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_0_t { + unsigned int pix_head_ptr : SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE; + unsigned int tail_ptr : SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE; + unsigned int full_cnt : SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE; + unsigned int nxt_pix_alloc_cnt : SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE; + unsigned int nxt_pix_exp_cnt : SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE; + unsigned int busy : SQ_DEBUG_PIX_TB_0_BUSY_SIZE; + } sq_debug_pix_tb_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_0_t { + unsigned int busy : SQ_DEBUG_PIX_TB_0_BUSY_SIZE; + unsigned int nxt_pix_exp_cnt : SQ_DEBUG_PIX_TB_0_NXT_PIX_EXP_CNT_SIZE; + unsigned int nxt_pix_alloc_cnt : SQ_DEBUG_PIX_TB_0_NXT_PIX_ALLOC_CNT_SIZE; + unsigned int full_cnt : SQ_DEBUG_PIX_TB_0_FULL_CNT_SIZE; + unsigned int tail_ptr : SQ_DEBUG_PIX_TB_0_TAIL_PTR_SIZE; + unsigned int pix_head_ptr : SQ_DEBUG_PIX_TB_0_PIX_HEAD_PTR_SIZE; + } sq_debug_pix_tb_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_0_t f; +} sq_debug_pix_tb_0_u; + + +/* + * SQ_DEBUG_PIX_TB_STATUS_REG_0 struct + */ + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_MASK \ + (SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0(pix_tb_status_reg_0) \ + ((pix_tb_status_reg_0 << SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_GET_PIX_TB_STATUS_REG_0(sq_debug_pix_tb_status_reg_0) \ + ((sq_debug_pix_tb_status_reg_0 & SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_0_SET_PIX_TB_STATUS_REG_0(sq_debug_pix_tb_status_reg_0_reg, pix_tb_status_reg_0) \ + sq_debug_pix_tb_status_reg_0_reg = (sq_debug_pix_tb_status_reg_0_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_MASK) | (pix_tb_status_reg_0 << SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_0_t { + unsigned int pix_tb_status_reg_0 : SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE; + } sq_debug_pix_tb_status_reg_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_0_t { + unsigned int pix_tb_status_reg_0 : SQ_DEBUG_PIX_TB_STATUS_REG_0_PIX_TB_STATUS_REG_0_SIZE; + } sq_debug_pix_tb_status_reg_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_status_reg_0_t f; +} sq_debug_pix_tb_status_reg_0_u; + + +/* + * SQ_DEBUG_PIX_TB_STATUS_REG_1 struct + */ + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_MASK \ + (SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1(pix_tb_status_reg_1) \ + ((pix_tb_status_reg_1 << SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_GET_PIX_TB_STATUS_REG_1(sq_debug_pix_tb_status_reg_1) \ + ((sq_debug_pix_tb_status_reg_1 & SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_1_SET_PIX_TB_STATUS_REG_1(sq_debug_pix_tb_status_reg_1_reg, pix_tb_status_reg_1) \ + sq_debug_pix_tb_status_reg_1_reg = (sq_debug_pix_tb_status_reg_1_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_MASK) | (pix_tb_status_reg_1 << SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_1_t { + unsigned int pix_tb_status_reg_1 : SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE; + } sq_debug_pix_tb_status_reg_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_1_t { + unsigned int pix_tb_status_reg_1 : SQ_DEBUG_PIX_TB_STATUS_REG_1_PIX_TB_STATUS_REG_1_SIZE; + } sq_debug_pix_tb_status_reg_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_status_reg_1_t f; +} sq_debug_pix_tb_status_reg_1_u; + + +/* + * SQ_DEBUG_PIX_TB_STATUS_REG_2 struct + */ + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_MASK \ + (SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2(pix_tb_status_reg_2) \ + ((pix_tb_status_reg_2 << SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_GET_PIX_TB_STATUS_REG_2(sq_debug_pix_tb_status_reg_2) \ + ((sq_debug_pix_tb_status_reg_2 & SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_2_SET_PIX_TB_STATUS_REG_2(sq_debug_pix_tb_status_reg_2_reg, pix_tb_status_reg_2) \ + sq_debug_pix_tb_status_reg_2_reg = (sq_debug_pix_tb_status_reg_2_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_MASK) | (pix_tb_status_reg_2 << SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_2_t { + unsigned int pix_tb_status_reg_2 : SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE; + } sq_debug_pix_tb_status_reg_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_2_t { + unsigned int pix_tb_status_reg_2 : SQ_DEBUG_PIX_TB_STATUS_REG_2_PIX_TB_STATUS_REG_2_SIZE; + } sq_debug_pix_tb_status_reg_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_status_reg_2_t f; +} sq_debug_pix_tb_status_reg_2_u; + + +/* + * SQ_DEBUG_PIX_TB_STATUS_REG_3 struct + */ + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_MASK \ + (SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3(pix_tb_status_reg_3) \ + ((pix_tb_status_reg_3 << SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_GET_PIX_TB_STATUS_REG_3(sq_debug_pix_tb_status_reg_3) \ + ((sq_debug_pix_tb_status_reg_3 & SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) >> SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATUS_REG_3_SET_PIX_TB_STATUS_REG_3(sq_debug_pix_tb_status_reg_3_reg, pix_tb_status_reg_3) \ + sq_debug_pix_tb_status_reg_3_reg = (sq_debug_pix_tb_status_reg_3_reg & ~SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_MASK) | (pix_tb_status_reg_3 << SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_3_t { + unsigned int pix_tb_status_reg_3 : SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE; + } sq_debug_pix_tb_status_reg_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_status_reg_3_t { + unsigned int pix_tb_status_reg_3 : SQ_DEBUG_PIX_TB_STATUS_REG_3_PIX_TB_STATUS_REG_3_SIZE; + } sq_debug_pix_tb_status_reg_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_status_reg_3_t f; +} sq_debug_pix_tb_status_reg_3_u; + + +/* + * SQ_DEBUG_PIX_TB_STATE_MEM struct + */ + +#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE 32 + +#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT 0 + +#define SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK 0xffffffff + +#define SQ_DEBUG_PIX_TB_STATE_MEM_MASK \ + (SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) + +#define SQ_DEBUG_PIX_TB_STATE_MEM(pix_tb_state_mem) \ + ((pix_tb_state_mem << SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT)) + +#define SQ_DEBUG_PIX_TB_STATE_MEM_GET_PIX_TB_STATE_MEM(sq_debug_pix_tb_state_mem) \ + ((sq_debug_pix_tb_state_mem & SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) >> SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT) + +#define SQ_DEBUG_PIX_TB_STATE_MEM_SET_PIX_TB_STATE_MEM(sq_debug_pix_tb_state_mem_reg, pix_tb_state_mem) \ + sq_debug_pix_tb_state_mem_reg = (sq_debug_pix_tb_state_mem_reg & ~SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_MASK) | (pix_tb_state_mem << SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_state_mem_t { + unsigned int pix_tb_state_mem : SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE; + } sq_debug_pix_tb_state_mem_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_pix_tb_state_mem_t { + unsigned int pix_tb_state_mem : SQ_DEBUG_PIX_TB_STATE_MEM_PIX_TB_STATE_MEM_SIZE; + } sq_debug_pix_tb_state_mem_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_pix_tb_state_mem_t f; +} sq_debug_pix_tb_state_mem_u; + + +/* + * SQ_PERFCOUNTER0_SELECT struct + */ + +#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define SQ_PERFCOUNTER0_SELECT_MASK \ + (SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define SQ_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define SQ_PERFCOUNTER0_SELECT_GET_PERF_SEL(sq_perfcounter0_select) \ + ((sq_perfcounter0_select & SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define SQ_PERFCOUNTER0_SELECT_SET_PERF_SEL(sq_perfcounter0_select_reg, perf_sel) \ + sq_perfcounter0_select_reg = (sq_perfcounter0_select_reg & ~SQ_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter0_select_t { + unsigned int perf_sel : SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sq_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : SQ_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } sq_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter0_select_t f; +} sq_perfcounter0_select_u; + + +/* + * SQ_PERFCOUNTER1_SELECT struct + */ + +#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE 8 + +#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT 0 + +#define SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK 0x000000ff + +#define SQ_PERFCOUNTER1_SELECT_MASK \ + (SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) + +#define SQ_PERFCOUNTER1_SELECT(perf_sel) \ + ((perf_sel << SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT)) + +#define SQ_PERFCOUNTER1_SELECT_GET_PERF_SEL(sq_perfcounter1_select) \ + ((sq_perfcounter1_select & SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#define SQ_PERFCOUNTER1_SELECT_SET_PERF_SEL(sq_perfcounter1_select_reg, perf_sel) \ + sq_perfcounter1_select_reg = (sq_perfcounter1_select_reg & ~SQ_PERFCOUNTER1_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER1_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter1_select_t { + unsigned int perf_sel : SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sq_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter1_select_t { + unsigned int : 24; + unsigned int perf_sel : SQ_PERFCOUNTER1_SELECT_PERF_SEL_SIZE; + } sq_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter1_select_t f; +} sq_perfcounter1_select_u; + + +/* + * SQ_PERFCOUNTER2_SELECT struct + */ + +#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE 8 + +#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT 0 + +#define SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK 0x000000ff + +#define SQ_PERFCOUNTER2_SELECT_MASK \ + (SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) + +#define SQ_PERFCOUNTER2_SELECT(perf_sel) \ + ((perf_sel << SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT)) + +#define SQ_PERFCOUNTER2_SELECT_GET_PERF_SEL(sq_perfcounter2_select) \ + ((sq_perfcounter2_select & SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#define SQ_PERFCOUNTER2_SELECT_SET_PERF_SEL(sq_perfcounter2_select_reg, perf_sel) \ + sq_perfcounter2_select_reg = (sq_perfcounter2_select_reg & ~SQ_PERFCOUNTER2_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER2_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter2_select_t { + unsigned int perf_sel : SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sq_perfcounter2_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter2_select_t { + unsigned int : 24; + unsigned int perf_sel : SQ_PERFCOUNTER2_SELECT_PERF_SEL_SIZE; + } sq_perfcounter2_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter2_select_t f; +} sq_perfcounter2_select_u; + + +/* + * SQ_PERFCOUNTER3_SELECT struct + */ + +#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE 8 + +#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT 0 + +#define SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK 0x000000ff + +#define SQ_PERFCOUNTER3_SELECT_MASK \ + (SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) + +#define SQ_PERFCOUNTER3_SELECT(perf_sel) \ + ((perf_sel << SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT)) + +#define SQ_PERFCOUNTER3_SELECT_GET_PERF_SEL(sq_perfcounter3_select) \ + ((sq_perfcounter3_select & SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) >> SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#define SQ_PERFCOUNTER3_SELECT_SET_PERF_SEL(sq_perfcounter3_select_reg, perf_sel) \ + sq_perfcounter3_select_reg = (sq_perfcounter3_select_reg & ~SQ_PERFCOUNTER3_SELECT_PERF_SEL_MASK) | (perf_sel << SQ_PERFCOUNTER3_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter3_select_t { + unsigned int perf_sel : SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sq_perfcounter3_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter3_select_t { + unsigned int : 24; + unsigned int perf_sel : SQ_PERFCOUNTER3_SELECT_PERF_SEL_SIZE; + } sq_perfcounter3_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter3_select_t f; +} sq_perfcounter3_select_u; + + +/* + * SQ_PERFCOUNTER0_LOW struct + */ + +#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define SQ_PERFCOUNTER0_LOW_MASK \ + (SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER0_LOW_GET_PERF_COUNT(sq_perfcounter0_low) \ + ((sq_perfcounter0_low & SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER0_LOW_SET_PERF_COUNT(sq_perfcounter0_low_reg, perf_count) \ + sq_perfcounter0_low_reg = (sq_perfcounter0_low_reg & ~SQ_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter0_low_t { + unsigned int perf_count : SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } sq_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter0_low_t { + unsigned int perf_count : SQ_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } sq_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter0_low_t f; +} sq_perfcounter0_low_u; + + +/* + * SQ_PERFCOUNTER0_HI struct + */ + +#define SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define SQ_PERFCOUNTER0_HI_MASK \ + (SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER0_HI_GET_PERF_COUNT(sq_perfcounter0_hi) \ + ((sq_perfcounter0_hi & SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER0_HI_SET_PERF_COUNT(sq_perfcounter0_hi_reg, perf_count) \ + sq_perfcounter0_hi_reg = (sq_perfcounter0_hi_reg & ~SQ_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter0_hi_t { + unsigned int perf_count : SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sq_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : SQ_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } sq_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter0_hi_t f; +} sq_perfcounter0_hi_u; + + +/* + * SQ_PERFCOUNTER1_LOW struct + */ + +#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE 32 + +#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK 0xffffffff + +#define SQ_PERFCOUNTER1_LOW_MASK \ + (SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER1_LOW(perf_count) \ + ((perf_count << SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER1_LOW_GET_PERF_COUNT(sq_perfcounter1_low) \ + ((sq_perfcounter1_low & SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER1_LOW_SET_PERF_COUNT(sq_perfcounter1_low_reg, perf_count) \ + sq_perfcounter1_low_reg = (sq_perfcounter1_low_reg & ~SQ_PERFCOUNTER1_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER1_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter1_low_t { + unsigned int perf_count : SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } sq_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter1_low_t { + unsigned int perf_count : SQ_PERFCOUNTER1_LOW_PERF_COUNT_SIZE; + } sq_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter1_low_t f; +} sq_perfcounter1_low_u; + + +/* + * SQ_PERFCOUNTER1_HI struct + */ + +#define SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE 16 + +#define SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK 0x0000ffff + +#define SQ_PERFCOUNTER1_HI_MASK \ + (SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER1_HI(perf_count) \ + ((perf_count << SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER1_HI_GET_PERF_COUNT(sq_perfcounter1_hi) \ + ((sq_perfcounter1_hi & SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER1_HI_SET_PERF_COUNT(sq_perfcounter1_hi_reg, perf_count) \ + sq_perfcounter1_hi_reg = (sq_perfcounter1_hi_reg & ~SQ_PERFCOUNTER1_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER1_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter1_hi_t { + unsigned int perf_count : SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sq_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perf_count : SQ_PERFCOUNTER1_HI_PERF_COUNT_SIZE; + } sq_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter1_hi_t f; +} sq_perfcounter1_hi_u; + + +/* + * SQ_PERFCOUNTER2_LOW struct + */ + +#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE 32 + +#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK 0xffffffff + +#define SQ_PERFCOUNTER2_LOW_MASK \ + (SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER2_LOW(perf_count) \ + ((perf_count << SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER2_LOW_GET_PERF_COUNT(sq_perfcounter2_low) \ + ((sq_perfcounter2_low & SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER2_LOW_SET_PERF_COUNT(sq_perfcounter2_low_reg, perf_count) \ + sq_perfcounter2_low_reg = (sq_perfcounter2_low_reg & ~SQ_PERFCOUNTER2_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER2_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter2_low_t { + unsigned int perf_count : SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } sq_perfcounter2_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter2_low_t { + unsigned int perf_count : SQ_PERFCOUNTER2_LOW_PERF_COUNT_SIZE; + } sq_perfcounter2_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter2_low_t f; +} sq_perfcounter2_low_u; + + +/* + * SQ_PERFCOUNTER2_HI struct + */ + +#define SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE 16 + +#define SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK 0x0000ffff + +#define SQ_PERFCOUNTER2_HI_MASK \ + (SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER2_HI(perf_count) \ + ((perf_count << SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER2_HI_GET_PERF_COUNT(sq_perfcounter2_hi) \ + ((sq_perfcounter2_hi & SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER2_HI_SET_PERF_COUNT(sq_perfcounter2_hi_reg, perf_count) \ + sq_perfcounter2_hi_reg = (sq_perfcounter2_hi_reg & ~SQ_PERFCOUNTER2_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER2_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter2_hi_t { + unsigned int perf_count : SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sq_perfcounter2_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter2_hi_t { + unsigned int : 16; + unsigned int perf_count : SQ_PERFCOUNTER2_HI_PERF_COUNT_SIZE; + } sq_perfcounter2_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter2_hi_t f; +} sq_perfcounter2_hi_u; + + +/* + * SQ_PERFCOUNTER3_LOW struct + */ + +#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE 32 + +#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK 0xffffffff + +#define SQ_PERFCOUNTER3_LOW_MASK \ + (SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER3_LOW(perf_count) \ + ((perf_count << SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER3_LOW_GET_PERF_COUNT(sq_perfcounter3_low) \ + ((sq_perfcounter3_low & SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) >> SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER3_LOW_SET_PERF_COUNT(sq_perfcounter3_low_reg, perf_count) \ + sq_perfcounter3_low_reg = (sq_perfcounter3_low_reg & ~SQ_PERFCOUNTER3_LOW_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER3_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter3_low_t { + unsigned int perf_count : SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } sq_perfcounter3_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter3_low_t { + unsigned int perf_count : SQ_PERFCOUNTER3_LOW_PERF_COUNT_SIZE; + } sq_perfcounter3_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter3_low_t f; +} sq_perfcounter3_low_u; + + +/* + * SQ_PERFCOUNTER3_HI struct + */ + +#define SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE 16 + +#define SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT 0 + +#define SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK 0x0000ffff + +#define SQ_PERFCOUNTER3_HI_MASK \ + (SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) + +#define SQ_PERFCOUNTER3_HI(perf_count) \ + ((perf_count << SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT)) + +#define SQ_PERFCOUNTER3_HI_GET_PERF_COUNT(sq_perfcounter3_hi) \ + ((sq_perfcounter3_hi & SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) >> SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#define SQ_PERFCOUNTER3_HI_SET_PERF_COUNT(sq_perfcounter3_hi_reg, perf_count) \ + sq_perfcounter3_hi_reg = (sq_perfcounter3_hi_reg & ~SQ_PERFCOUNTER3_HI_PERF_COUNT_MASK) | (perf_count << SQ_PERFCOUNTER3_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_perfcounter3_hi_t { + unsigned int perf_count : SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sq_perfcounter3_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_perfcounter3_hi_t { + unsigned int : 16; + unsigned int perf_count : SQ_PERFCOUNTER3_HI_PERF_COUNT_SIZE; + } sq_perfcounter3_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_perfcounter3_hi_t f; +} sq_perfcounter3_hi_u; + + +/* + * SX_PERFCOUNTER0_SELECT struct + */ + +#define SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define SX_PERFCOUNTER0_SELECT_MASK \ + (SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define SX_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define SX_PERFCOUNTER0_SELECT_GET_PERF_SEL(sx_perfcounter0_select) \ + ((sx_perfcounter0_select & SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define SX_PERFCOUNTER0_SELECT_SET_PERF_SEL(sx_perfcounter0_select_reg, perf_sel) \ + sx_perfcounter0_select_reg = (sx_perfcounter0_select_reg & ~SX_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << SX_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sx_perfcounter0_select_t { + unsigned int perf_sel : SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } sx_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _sx_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : SX_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } sx_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + sx_perfcounter0_select_t f; +} sx_perfcounter0_select_u; + + +/* + * SX_PERFCOUNTER0_LOW struct + */ + +#define SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define SX_PERFCOUNTER0_LOW_MASK \ + (SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define SX_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define SX_PERFCOUNTER0_LOW_GET_PERF_COUNT(sx_perfcounter0_low) \ + ((sx_perfcounter0_low & SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define SX_PERFCOUNTER0_LOW_SET_PERF_COUNT(sx_perfcounter0_low_reg, perf_count) \ + sx_perfcounter0_low_reg = (sx_perfcounter0_low_reg & ~SX_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << SX_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sx_perfcounter0_low_t { + unsigned int perf_count : SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } sx_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _sx_perfcounter0_low_t { + unsigned int perf_count : SX_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } sx_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + sx_perfcounter0_low_t f; +} sx_perfcounter0_low_u; + + +/* + * SX_PERFCOUNTER0_HI struct + */ + +#define SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define SX_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define SX_PERFCOUNTER0_HI_MASK \ + (SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define SX_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define SX_PERFCOUNTER0_HI_GET_PERF_COUNT(sx_perfcounter0_hi) \ + ((sx_perfcounter0_hi & SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define SX_PERFCOUNTER0_HI_SET_PERF_COUNT(sx_perfcounter0_hi_reg, perf_count) \ + sx_perfcounter0_hi_reg = (sx_perfcounter0_hi_reg & ~SX_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << SX_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sx_perfcounter0_hi_t { + unsigned int perf_count : SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } sx_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _sx_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : SX_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } sx_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + sx_perfcounter0_hi_t f; +} sx_perfcounter0_hi_u; + + +/* + * SQ_INSTRUCTION_ALU_0 struct + */ + +#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE 6 +#define SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE 6 +#define SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE 4 +#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE 4 +#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE 1 +#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE 6 + +#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT 0 +#define SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT 6 +#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT 7 +#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT 8 +#define SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT 14 +#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT 15 +#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT 16 +#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT 20 +#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT 24 +#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT 25 +#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT 26 + +#define SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK 0x0000003f +#define SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK 0x00000040 +#define SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK 0x00000080 +#define SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK 0x00003f00 +#define SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK 0x00004000 +#define SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK 0x00008000 +#define SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK 0x000f0000 +#define SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK 0x00f00000 +#define SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK 0x01000000 +#define SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK 0x02000000 +#define SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK 0xfc000000 + +#define SQ_INSTRUCTION_ALU_0_MASK \ + (SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK | \ + SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK | \ + SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK | \ + SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK | \ + SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK | \ + SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK | \ + SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK | \ + SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK | \ + SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK | \ + SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK | \ + SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) + +#define SQ_INSTRUCTION_ALU_0(vector_result, vector_dst_rel, low_precision_16b_fp, scalar_result, scalar_dst_rel, export_data, vector_wrt_msk, scalar_wrt_msk, vector_clamp, scalar_clamp, scalar_opcode) \ + ((vector_result << SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT) | \ + (vector_dst_rel << SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT) | \ + (low_precision_16b_fp << SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT) | \ + (scalar_result << SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT) | \ + (scalar_dst_rel << SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT) | \ + (export_data << SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT) | \ + (vector_wrt_msk << SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT) | \ + (scalar_wrt_msk << SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT) | \ + (vector_clamp << SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT) | \ + (scalar_clamp << SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT) | \ + (scalar_opcode << SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_RESULT(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_DST_REL(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_LOW_PRECISION_16B_FP(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK) >> SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_RESULT(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_DST_REL(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_EXPORT_DATA(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK) >> SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_WRT_MSK(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_WRT_MSK(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_VECTOR_CLAMP(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK) >> SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_CLAMP(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_GET_SCALAR_OPCODE(sq_instruction_alu_0) \ + ((sq_instruction_alu_0 & SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) >> SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_RESULT(sq_instruction_alu_0_reg, vector_result) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_MASK) | (vector_result << SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_DST_REL(sq_instruction_alu_0_reg, vector_dst_rel) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_MASK) | (vector_dst_rel << SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_LOW_PRECISION_16B_FP(sq_instruction_alu_0_reg, low_precision_16b_fp) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_MASK) | (low_precision_16b_fp << SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_RESULT(sq_instruction_alu_0_reg, scalar_result) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_MASK) | (scalar_result << SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_DST_REL(sq_instruction_alu_0_reg, scalar_dst_rel) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_MASK) | (scalar_dst_rel << SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_EXPORT_DATA(sq_instruction_alu_0_reg, export_data) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_EXPORT_DATA_MASK) | (export_data << SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_WRT_MSK(sq_instruction_alu_0_reg, vector_wrt_msk) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_MASK) | (vector_wrt_msk << SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_WRT_MSK(sq_instruction_alu_0_reg, scalar_wrt_msk) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_MASK) | (scalar_wrt_msk << SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_VECTOR_CLAMP(sq_instruction_alu_0_reg, vector_clamp) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_MASK) | (vector_clamp << SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_CLAMP(sq_instruction_alu_0_reg, scalar_clamp) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_MASK) | (scalar_clamp << SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SHIFT) +#define SQ_INSTRUCTION_ALU_0_SET_SCALAR_OPCODE(sq_instruction_alu_0_reg, scalar_opcode) \ + sq_instruction_alu_0_reg = (sq_instruction_alu_0_reg & ~SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_MASK) | (scalar_opcode << SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_alu_0_t { + unsigned int vector_result : SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE; + unsigned int vector_dst_rel : SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SIZE; + unsigned int low_precision_16b_fp : SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE; + unsigned int scalar_result : SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE; + unsigned int scalar_dst_rel : SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SIZE; + unsigned int export_data : SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE; + unsigned int vector_wrt_msk : SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE; + unsigned int scalar_wrt_msk : SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE; + unsigned int vector_clamp : SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE; + unsigned int scalar_clamp : SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE; + unsigned int scalar_opcode : SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE; + } sq_instruction_alu_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_alu_0_t { + unsigned int scalar_opcode : SQ_INSTRUCTION_ALU_0_SCALAR_OPCODE_SIZE; + unsigned int scalar_clamp : SQ_INSTRUCTION_ALU_0_SCALAR_CLAMP_SIZE; + unsigned int vector_clamp : SQ_INSTRUCTION_ALU_0_VECTOR_CLAMP_SIZE; + unsigned int scalar_wrt_msk : SQ_INSTRUCTION_ALU_0_SCALAR_WRT_MSK_SIZE; + unsigned int vector_wrt_msk : SQ_INSTRUCTION_ALU_0_VECTOR_WRT_MSK_SIZE; + unsigned int export_data : SQ_INSTRUCTION_ALU_0_EXPORT_DATA_SIZE; + unsigned int scalar_dst_rel : SQ_INSTRUCTION_ALU_0_SCALAR_DST_REL_SIZE; + unsigned int scalar_result : SQ_INSTRUCTION_ALU_0_SCALAR_RESULT_SIZE; + unsigned int low_precision_16b_fp : SQ_INSTRUCTION_ALU_0_LOW_PRECISION_16B_FP_SIZE; + unsigned int vector_dst_rel : SQ_INSTRUCTION_ALU_0_VECTOR_DST_REL_SIZE; + unsigned int vector_result : SQ_INSTRUCTION_ALU_0_VECTOR_RESULT_SIZE; + } sq_instruction_alu_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_alu_0_t f; +} sq_instruction_alu_0_u; + + +/* + * SQ_INSTRUCTION_ALU_1 struct + */ + +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE 2 +#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE 1 +#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE 1 + +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT 0 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT 2 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT 4 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT 6 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT 8 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT 10 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT 12 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT 14 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT 16 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT 18 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT 20 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT 22 +#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT 24 +#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT 25 +#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT 26 +#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT 27 +#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT 29 +#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT 30 +#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT 31 + +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK 0x00000003 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK 0x0000000c +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK 0x00000030 +#define SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK 0x000000c0 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK 0x00000300 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK 0x00000c00 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK 0x00003000 +#define SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK 0x0000c000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK 0x00030000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK 0x000c0000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK 0x00300000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK 0x00c00000 +#define SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK 0x01000000 +#define SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK 0x02000000 +#define SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK 0x04000000 +#define SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK 0x18000000 +#define SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK 0x20000000 +#define SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK 0x40000000 +#define SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK 0x80000000 + +#define SQ_INSTRUCTION_ALU_1_MASK \ + (SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK | \ + SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK | \ + SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK | \ + SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK | \ + SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK | \ + SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) + +#define SQ_INSTRUCTION_ALU_1(src_c_swizzle_r, src_c_swizzle_g, src_c_swizzle_b, src_c_swizzle_a, src_b_swizzle_r, src_b_swizzle_g, src_b_swizzle_b, src_b_swizzle_a, src_a_swizzle_r, src_a_swizzle_g, src_a_swizzle_b, src_a_swizzle_a, src_c_arg_mod, src_b_arg_mod, src_a_arg_mod, pred_select, relative_addr, const_1_rel_abs, const_0_rel_abs) \ + ((src_c_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT) | \ + (src_c_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT) | \ + (src_c_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT) | \ + (src_c_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT) | \ + (src_b_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT) | \ + (src_b_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT) | \ + (src_b_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT) | \ + (src_b_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT) | \ + (src_a_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT) | \ + (src_a_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT) | \ + (src_a_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT) | \ + (src_a_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT) | \ + (src_c_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT) | \ + (src_b_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT) | \ + (src_a_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT) | \ + (pred_select << SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT) | \ + (relative_addr << SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT) | \ + (const_1_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT) | \ + (const_0_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT)) + +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_R(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_G(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_B(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_SWIZZLE_A(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_R(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_G(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_B(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_SWIZZLE_A(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_R(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_G(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_B(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_SWIZZLE_A(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_C_ARG_MOD(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_B_ARG_MOD(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_SRC_A_ARG_MOD(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK) >> SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_PRED_SELECT(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_RELATIVE_ADDR(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK) >> SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_CONST_1_REL_ABS(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK) >> SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT) +#define SQ_INSTRUCTION_ALU_1_GET_CONST_0_REL_ABS(sq_instruction_alu_1) \ + ((sq_instruction_alu_1 & SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) >> SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT) + +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_R(sq_instruction_alu_1_reg, src_c_swizzle_r) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_MASK) | (src_c_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_G(sq_instruction_alu_1_reg, src_c_swizzle_g) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_MASK) | (src_c_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_B(sq_instruction_alu_1_reg, src_c_swizzle_b) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_MASK) | (src_c_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_SWIZZLE_A(sq_instruction_alu_1_reg, src_c_swizzle_a) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_MASK) | (src_c_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_R(sq_instruction_alu_1_reg, src_b_swizzle_r) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_MASK) | (src_b_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_G(sq_instruction_alu_1_reg, src_b_swizzle_g) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_MASK) | (src_b_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_B(sq_instruction_alu_1_reg, src_b_swizzle_b) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_MASK) | (src_b_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_SWIZZLE_A(sq_instruction_alu_1_reg, src_b_swizzle_a) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_MASK) | (src_b_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_R(sq_instruction_alu_1_reg, src_a_swizzle_r) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_MASK) | (src_a_swizzle_r << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_G(sq_instruction_alu_1_reg, src_a_swizzle_g) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_MASK) | (src_a_swizzle_g << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_B(sq_instruction_alu_1_reg, src_a_swizzle_b) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_MASK) | (src_a_swizzle_b << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_SWIZZLE_A(sq_instruction_alu_1_reg, src_a_swizzle_a) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_MASK) | (src_a_swizzle_a << SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_C_ARG_MOD(sq_instruction_alu_1_reg, src_c_arg_mod) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_MASK) | (src_c_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_B_ARG_MOD(sq_instruction_alu_1_reg, src_b_arg_mod) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_MASK) | (src_b_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_SRC_A_ARG_MOD(sq_instruction_alu_1_reg, src_a_arg_mod) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_MASK) | (src_a_arg_mod << SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_PRED_SELECT(sq_instruction_alu_1_reg, pred_select) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_ALU_1_PRED_SELECT_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_RELATIVE_ADDR(sq_instruction_alu_1_reg, relative_addr) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_MASK) | (relative_addr << SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_CONST_1_REL_ABS(sq_instruction_alu_1_reg, const_1_rel_abs) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_MASK) | (const_1_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SHIFT) +#define SQ_INSTRUCTION_ALU_1_SET_CONST_0_REL_ABS(sq_instruction_alu_1_reg, const_0_rel_abs) \ + sq_instruction_alu_1_reg = (sq_instruction_alu_1_reg & ~SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_MASK) | (const_0_rel_abs << SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_alu_1_t { + unsigned int src_c_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE; + unsigned int src_c_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE; + unsigned int src_c_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE; + unsigned int src_c_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE; + unsigned int src_b_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE; + unsigned int src_b_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE; + unsigned int src_b_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE; + unsigned int src_b_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE; + unsigned int src_a_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE; + unsigned int src_a_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE; + unsigned int src_a_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE; + unsigned int src_a_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE; + unsigned int src_c_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE; + unsigned int src_b_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE; + unsigned int src_a_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE; + unsigned int pred_select : SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE; + unsigned int relative_addr : SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE; + unsigned int const_1_rel_abs : SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE; + unsigned int const_0_rel_abs : SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE; + } sq_instruction_alu_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_alu_1_t { + unsigned int const_0_rel_abs : SQ_INSTRUCTION_ALU_1_CONST_0_REL_ABS_SIZE; + unsigned int const_1_rel_abs : SQ_INSTRUCTION_ALU_1_CONST_1_REL_ABS_SIZE; + unsigned int relative_addr : SQ_INSTRUCTION_ALU_1_RELATIVE_ADDR_SIZE; + unsigned int pred_select : SQ_INSTRUCTION_ALU_1_PRED_SELECT_SIZE; + unsigned int src_a_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_A_ARG_MOD_SIZE; + unsigned int src_b_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_B_ARG_MOD_SIZE; + unsigned int src_c_arg_mod : SQ_INSTRUCTION_ALU_1_SRC_C_ARG_MOD_SIZE; + unsigned int src_a_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_A_SIZE; + unsigned int src_a_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_B_SIZE; + unsigned int src_a_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_G_SIZE; + unsigned int src_a_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_A_SWIZZLE_R_SIZE; + unsigned int src_b_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_A_SIZE; + unsigned int src_b_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_B_SIZE; + unsigned int src_b_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_G_SIZE; + unsigned int src_b_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_B_SWIZZLE_R_SIZE; + unsigned int src_c_swizzle_a : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_A_SIZE; + unsigned int src_c_swizzle_b : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_B_SIZE; + unsigned int src_c_swizzle_g : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_G_SIZE; + unsigned int src_c_swizzle_r : SQ_INSTRUCTION_ALU_1_SRC_C_SWIZZLE_R_SIZE; + } sq_instruction_alu_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_alu_1_t f; +} sq_instruction_alu_1_u; + + +/* + * SQ_INSTRUCTION_ALU_2 struct + */ + +#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE 6 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE 6 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE 6 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE 5 +#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE 1 +#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE 1 + +#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT 0 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT 6 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT 7 +#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT 8 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT 14 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT 15 +#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT 16 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT 22 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT 23 +#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT 24 +#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT 29 +#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT 30 +#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT 31 + +#define SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK 0x0000003f +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK 0x00000040 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK 0x00000080 +#define SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK 0x00003f00 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK 0x00004000 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK 0x00008000 +#define SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK 0x003f0000 +#define SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK 0x00400000 +#define SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK 0x00800000 +#define SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK 0x1f000000 +#define SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK 0x20000000 +#define SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK 0x40000000 +#define SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK 0x80000000 + +#define SQ_INSTRUCTION_ALU_2_MASK \ + (SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK | \ + SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK | \ + SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK | \ + SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) + +#define SQ_INSTRUCTION_ALU_2(src_c_reg_ptr, reg_select_c, reg_abs_mod_c, src_b_reg_ptr, reg_select_b, reg_abs_mod_b, src_a_reg_ptr, reg_select_a, reg_abs_mod_a, vector_opcode, src_c_sel, src_b_sel, src_a_sel) \ + ((src_c_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT) | \ + (reg_select_c << SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT) | \ + (reg_abs_mod_c << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT) | \ + (src_b_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT) | \ + (reg_select_b << SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT) | \ + (reg_abs_mod_b << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT) | \ + (src_a_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT) | \ + (reg_select_a << SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT) | \ + (reg_abs_mod_a << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT) | \ + (vector_opcode << SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT) | \ + (src_c_sel << SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT) | \ + (src_b_sel << SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT) | \ + (src_a_sel << SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT)) + +#define SQ_INSTRUCTION_ALU_2_GET_SRC_C_REG_PTR(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_C(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_C(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_B_REG_PTR(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_B(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_B(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_A_REG_PTR(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_SELECT_A(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK) >> SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_REG_ABS_MOD_A(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK) >> SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_VECTOR_OPCODE(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK) >> SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_C_SEL(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_B_SEL(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT) +#define SQ_INSTRUCTION_ALU_2_GET_SRC_A_SEL(sq_instruction_alu_2) \ + ((sq_instruction_alu_2 & SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) >> SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT) + +#define SQ_INSTRUCTION_ALU_2_SET_SRC_C_REG_PTR(sq_instruction_alu_2_reg, src_c_reg_ptr) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_MASK) | (src_c_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_C(sq_instruction_alu_2_reg, reg_select_c) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_C_MASK) | (reg_select_c << SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_C(sq_instruction_alu_2_reg, reg_abs_mod_c) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_MASK) | (reg_abs_mod_c << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_B_REG_PTR(sq_instruction_alu_2_reg, src_b_reg_ptr) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_MASK) | (src_b_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_B(sq_instruction_alu_2_reg, reg_select_b) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_B_MASK) | (reg_select_b << SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_B(sq_instruction_alu_2_reg, reg_abs_mod_b) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_MASK) | (reg_abs_mod_b << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_A_REG_PTR(sq_instruction_alu_2_reg, src_a_reg_ptr) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_MASK) | (src_a_reg_ptr << SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_SELECT_A(sq_instruction_alu_2_reg, reg_select_a) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_SELECT_A_MASK) | (reg_select_a << SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_REG_ABS_MOD_A(sq_instruction_alu_2_reg, reg_abs_mod_a) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_MASK) | (reg_abs_mod_a << SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_VECTOR_OPCODE(sq_instruction_alu_2_reg, vector_opcode) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_MASK) | (vector_opcode << SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_C_SEL(sq_instruction_alu_2_reg, src_c_sel) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_C_SEL_MASK) | (src_c_sel << SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_B_SEL(sq_instruction_alu_2_reg, src_b_sel) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_B_SEL_MASK) | (src_b_sel << SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SHIFT) +#define SQ_INSTRUCTION_ALU_2_SET_SRC_A_SEL(sq_instruction_alu_2_reg, src_a_sel) \ + sq_instruction_alu_2_reg = (sq_instruction_alu_2_reg & ~SQ_INSTRUCTION_ALU_2_SRC_A_SEL_MASK) | (src_a_sel << SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_alu_2_t { + unsigned int src_c_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE; + unsigned int reg_select_c : SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE; + unsigned int reg_abs_mod_c : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE; + unsigned int src_b_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE; + unsigned int reg_select_b : SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE; + unsigned int reg_abs_mod_b : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE; + unsigned int src_a_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE; + unsigned int reg_select_a : SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE; + unsigned int reg_abs_mod_a : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE; + unsigned int vector_opcode : SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE; + unsigned int src_c_sel : SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE; + unsigned int src_b_sel : SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE; + unsigned int src_a_sel : SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE; + } sq_instruction_alu_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_alu_2_t { + unsigned int src_a_sel : SQ_INSTRUCTION_ALU_2_SRC_A_SEL_SIZE; + unsigned int src_b_sel : SQ_INSTRUCTION_ALU_2_SRC_B_SEL_SIZE; + unsigned int src_c_sel : SQ_INSTRUCTION_ALU_2_SRC_C_SEL_SIZE; + unsigned int vector_opcode : SQ_INSTRUCTION_ALU_2_VECTOR_OPCODE_SIZE; + unsigned int reg_abs_mod_a : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_A_SIZE; + unsigned int reg_select_a : SQ_INSTRUCTION_ALU_2_REG_SELECT_A_SIZE; + unsigned int src_a_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_A_REG_PTR_SIZE; + unsigned int reg_abs_mod_b : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_B_SIZE; + unsigned int reg_select_b : SQ_INSTRUCTION_ALU_2_REG_SELECT_B_SIZE; + unsigned int src_b_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_B_REG_PTR_SIZE; + unsigned int reg_abs_mod_c : SQ_INSTRUCTION_ALU_2_REG_ABS_MOD_C_SIZE; + unsigned int reg_select_c : SQ_INSTRUCTION_ALU_2_REG_SELECT_C_SIZE; + unsigned int src_c_reg_ptr : SQ_INSTRUCTION_ALU_2_SRC_C_REG_PTR_SIZE; + } sq_instruction_alu_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_alu_2_t f; +} sq_instruction_alu_2_u; + + +/* + * SQ_INSTRUCTION_CF_EXEC_0 struct + */ + +#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE 9 +#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE 3 +#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE 3 +#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE 1 + +#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT 0 +#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT 9 +#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT 12 +#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT 15 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT 16 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT 17 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT 18 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT 19 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT 20 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT 21 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT 22 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT 23 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT 24 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT 25 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT 26 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT 27 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT 28 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT 29 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT 30 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT 31 + +#define SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK 0x000001ff +#define SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK 0x00000e00 +#define SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK 0x00007000 +#define SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK 0x00008000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK 0x00010000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK 0x00020000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK 0x00040000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK 0x00080000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK 0x00100000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK 0x00200000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK 0x00400000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK 0x00800000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK 0x01000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK 0x02000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK 0x04000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK 0x10000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK 0x20000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK 0x40000000 +#define SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK 0x80000000 + +#define SQ_INSTRUCTION_CF_EXEC_0_MASK \ + (SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) + +#define SQ_INSTRUCTION_CF_EXEC_0(address, reserved, count, yield, inst_type_0, inst_serial_0, inst_type_1, inst_serial_1, inst_type_2, inst_serial_2, inst_type_3, inst_serial_3, inst_type_4, inst_serial_4, inst_type_5, inst_serial_5, inst_vc_0, inst_vc_1, inst_vc_2, inst_vc_3) \ + ((address << SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT) | \ + (reserved << SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT) | \ + (count << SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT) | \ + (yield << SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT) | \ + (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT) | \ + (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT) | \ + (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT) | \ + (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT) | \ + (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT) | \ + (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT) | \ + (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT) | \ + (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT) | \ + (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT) | \ + (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT) | \ + (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT) | \ + (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT) | \ + (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT) | \ + (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT) | \ + (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT) | \ + (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT)) + +#define SQ_INSTRUCTION_CF_EXEC_0_GET_ADDRESS(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_RESERVED(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_COUNT(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_YIELD(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_0(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_0(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_1(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_1(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_2(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_2(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_3(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_3(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_4(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_4(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_TYPE_5(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_SERIAL_5(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_0(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_1(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_2(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_GET_INST_VC_3(sq_instruction_cf_exec_0) \ + ((sq_instruction_cf_exec_0 & SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT) + +#define SQ_INSTRUCTION_CF_EXEC_0_SET_ADDRESS(sq_instruction_cf_exec_0_reg, address) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_RESERVED(sq_instruction_cf_exec_0_reg, reserved) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_COUNT(sq_instruction_cf_exec_0_reg, count) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_COUNT_MASK) | (count << SQ_INSTRUCTION_CF_EXEC_0_COUNT_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_YIELD(sq_instruction_cf_exec_0_reg, yield) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_YIELD_MASK) | (yield << SQ_INSTRUCTION_CF_EXEC_0_YIELD_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_0(sq_instruction_cf_exec_0_reg, inst_type_0) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_MASK) | (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_0(sq_instruction_cf_exec_0_reg, inst_serial_0) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_MASK) | (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_1(sq_instruction_cf_exec_0_reg, inst_type_1) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_MASK) | (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_1(sq_instruction_cf_exec_0_reg, inst_serial_1) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_MASK) | (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_2(sq_instruction_cf_exec_0_reg, inst_type_2) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_MASK) | (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_2(sq_instruction_cf_exec_0_reg, inst_serial_2) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_MASK) | (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_3(sq_instruction_cf_exec_0_reg, inst_type_3) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_MASK) | (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_3(sq_instruction_cf_exec_0_reg, inst_serial_3) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_MASK) | (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_4(sq_instruction_cf_exec_0_reg, inst_type_4) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_MASK) | (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_4(sq_instruction_cf_exec_0_reg, inst_serial_4) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_MASK) | (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_TYPE_5(sq_instruction_cf_exec_0_reg, inst_type_5) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_MASK) | (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_SERIAL_5(sq_instruction_cf_exec_0_reg, inst_serial_5) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_MASK) | (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_0(sq_instruction_cf_exec_0_reg, inst_vc_0) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_MASK) | (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_1(sq_instruction_cf_exec_0_reg, inst_vc_1) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_MASK) | (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_2(sq_instruction_cf_exec_0_reg, inst_vc_2) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_MASK) | (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_0_SET_INST_VC_3(sq_instruction_cf_exec_0_reg, inst_vc_3) \ + sq_instruction_cf_exec_0_reg = (sq_instruction_cf_exec_0_reg & ~SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_MASK) | (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_0_t { + unsigned int address : SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE; + unsigned int count : SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE; + unsigned int yield : SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE; + unsigned int inst_type_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE; + unsigned int inst_serial_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE; + unsigned int inst_type_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE; + unsigned int inst_serial_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE; + unsigned int inst_type_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE; + unsigned int inst_serial_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE; + unsigned int inst_type_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE; + unsigned int inst_serial_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE; + unsigned int inst_type_4 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE; + unsigned int inst_serial_4 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE; + unsigned int inst_type_5 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE; + unsigned int inst_serial_5 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE; + unsigned int inst_vc_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE; + unsigned int inst_vc_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE; + unsigned int inst_vc_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE; + unsigned int inst_vc_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE; + } sq_instruction_cf_exec_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_0_t { + unsigned int inst_vc_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_3_SIZE; + unsigned int inst_vc_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_2_SIZE; + unsigned int inst_vc_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_1_SIZE; + unsigned int inst_vc_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_VC_0_SIZE; + unsigned int inst_serial_5 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_5_SIZE; + unsigned int inst_type_5 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_5_SIZE; + unsigned int inst_serial_4 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_4_SIZE; + unsigned int inst_type_4 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_4_SIZE; + unsigned int inst_serial_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_3_SIZE; + unsigned int inst_type_3 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_3_SIZE; + unsigned int inst_serial_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_2_SIZE; + unsigned int inst_type_2 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_2_SIZE; + unsigned int inst_serial_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_1_SIZE; + unsigned int inst_type_1 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_1_SIZE; + unsigned int inst_serial_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_SERIAL_0_SIZE; + unsigned int inst_type_0 : SQ_INSTRUCTION_CF_EXEC_0_INST_TYPE_0_SIZE; + unsigned int yield : SQ_INSTRUCTION_CF_EXEC_0_YIELD_SIZE; + unsigned int count : SQ_INSTRUCTION_CF_EXEC_0_COUNT_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_EXEC_0_RESERVED_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_EXEC_0_ADDRESS_SIZE; + } sq_instruction_cf_exec_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_exec_0_t f; +} sq_instruction_cf_exec_0_u; + + +/* + * SQ_INSTRUCTION_CF_EXEC_1 struct + */ + +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE 8 +#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE 4 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE 9 +#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE 3 +#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE 3 +#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE 1 + +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT 0 +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT 1 +#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT 2 +#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT 10 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT 11 +#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT 12 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT 16 +#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT 25 +#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT 28 +#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT 31 + +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK 0x00000001 +#define SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK 0x00000002 +#define SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK 0x000003fc +#define SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK 0x00000400 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK 0x0000f000 +#define SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK 0x01ff0000 +#define SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK 0x0e000000 +#define SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK 0x70000000 +#define SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK 0x80000000 + +#define SQ_INSTRUCTION_CF_EXEC_1_MASK \ + (SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK | \ + SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) + +#define SQ_INSTRUCTION_CF_EXEC_1(inst_vc_4, inst_vc_5, bool_addr, condition, address_mode, opcode, address, reserved, count, yield) \ + ((inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT) | \ + (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT) | \ + (bool_addr << SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT) | \ + (condition << SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT) | \ + (address << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT) | \ + (reserved << SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT) | \ + (count << SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT) | \ + (yield << SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT)) + +#define SQ_INSTRUCTION_CF_EXEC_1_GET_INST_VC_4(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_INST_VC_5(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_BOOL_ADDR(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_CONDITION(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_ADDRESS_MODE(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_OPCODE(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_ADDRESS(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_RESERVED(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_COUNT(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_GET_YIELD(sq_instruction_cf_exec_1) \ + ((sq_instruction_cf_exec_1 & SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) >> SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT) + +#define SQ_INSTRUCTION_CF_EXEC_1_SET_INST_VC_4(sq_instruction_cf_exec_1_reg, inst_vc_4) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_MASK) | (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_INST_VC_5(sq_instruction_cf_exec_1_reg, inst_vc_5) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_MASK) | (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_BOOL_ADDR(sq_instruction_cf_exec_1_reg, bool_addr) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_CONDITION(sq_instruction_cf_exec_1_reg, condition) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_ADDRESS_MODE(sq_instruction_cf_exec_1_reg, address_mode) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_OPCODE(sq_instruction_cf_exec_1_reg, opcode) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_ADDRESS(sq_instruction_cf_exec_1_reg, address) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_RESERVED(sq_instruction_cf_exec_1_reg, reserved) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_COUNT(sq_instruction_cf_exec_1_reg, count) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_COUNT_MASK) | (count << SQ_INSTRUCTION_CF_EXEC_1_COUNT_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_1_SET_YIELD(sq_instruction_cf_exec_1_reg, yield) \ + sq_instruction_cf_exec_1_reg = (sq_instruction_cf_exec_1_reg & ~SQ_INSTRUCTION_CF_EXEC_1_YIELD_MASK) | (yield << SQ_INSTRUCTION_CF_EXEC_1_YIELD_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_1_t { + unsigned int inst_vc_4 : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE; + unsigned int inst_vc_5 : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE; + unsigned int count : SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE; + unsigned int yield : SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE; + } sq_instruction_cf_exec_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_1_t { + unsigned int yield : SQ_INSTRUCTION_CF_EXEC_1_YIELD_SIZE; + unsigned int count : SQ_INSTRUCTION_CF_EXEC_1_COUNT_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_EXEC_1_RESERVED_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_EXEC_1_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_EXEC_1_ADDRESS_MODE_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_EXEC_1_CONDITION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_EXEC_1_BOOL_ADDR_SIZE; + unsigned int inst_vc_5 : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_5_SIZE; + unsigned int inst_vc_4 : SQ_INSTRUCTION_CF_EXEC_1_INST_VC_4_SIZE; + } sq_instruction_cf_exec_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_exec_1_t f; +} sq_instruction_cf_exec_1_u; + + +/* + * SQ_INSTRUCTION_CF_EXEC_2 struct + */ + +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE 8 +#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE 4 + +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT 0 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT 1 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT 2 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT 3 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT 4 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT 5 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT 6 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT 7 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT 8 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT 9 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT 10 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT 11 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT 12 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT 13 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT 14 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT 15 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT 16 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT 17 +#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT 18 +#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT 26 +#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT 27 +#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT 28 + +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK 0x00000001 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK 0x00000002 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK 0x00000004 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK 0x00000008 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK 0x00000010 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK 0x00000020 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK 0x00000040 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK 0x00000080 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK 0x00000100 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK 0x00000200 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK 0x00000400 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK 0x00001000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK 0x00002000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK 0x00004000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK 0x00008000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK 0x00010000 +#define SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK 0x00020000 +#define SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK 0x03fc0000 +#define SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK 0x04000000 +#define SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK 0xf0000000 + +#define SQ_INSTRUCTION_CF_EXEC_2_MASK \ + (SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) + +#define SQ_INSTRUCTION_CF_EXEC_2(inst_type_0, inst_serial_0, inst_type_1, inst_serial_1, inst_type_2, inst_serial_2, inst_type_3, inst_serial_3, inst_type_4, inst_serial_4, inst_type_5, inst_serial_5, inst_vc_0, inst_vc_1, inst_vc_2, inst_vc_3, inst_vc_4, inst_vc_5, bool_addr, condition, address_mode, opcode) \ + ((inst_type_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT) | \ + (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT) | \ + (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT) | \ + (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT) | \ + (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT) | \ + (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT) | \ + (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT) | \ + (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT) | \ + (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT) | \ + (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT) | \ + (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT) | \ + (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT) | \ + (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT) | \ + (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT) | \ + (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT) | \ + (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT) | \ + (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT) | \ + (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT) | \ + (bool_addr << SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT) | \ + (condition << SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_0(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_0(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_1(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_1(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_2(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_2(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_3(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_3(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_4(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_4(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_TYPE_5(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_SERIAL_5(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_0(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_1(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_2(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_3(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_4(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_INST_VC_5(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_BOOL_ADDR(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_CONDITION(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_ADDRESS_MODE(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_GET_OPCODE(sq_instruction_cf_exec_2) \ + ((sq_instruction_cf_exec_2 & SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_0(sq_instruction_cf_exec_2_reg, inst_type_0) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_MASK) | (inst_type_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_0(sq_instruction_cf_exec_2_reg, inst_serial_0) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_MASK) | (inst_serial_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_1(sq_instruction_cf_exec_2_reg, inst_type_1) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_MASK) | (inst_type_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_1(sq_instruction_cf_exec_2_reg, inst_serial_1) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_MASK) | (inst_serial_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_2(sq_instruction_cf_exec_2_reg, inst_type_2) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_MASK) | (inst_type_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_2(sq_instruction_cf_exec_2_reg, inst_serial_2) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_MASK) | (inst_serial_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_3(sq_instruction_cf_exec_2_reg, inst_type_3) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_MASK) | (inst_type_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_3(sq_instruction_cf_exec_2_reg, inst_serial_3) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_MASK) | (inst_serial_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_4(sq_instruction_cf_exec_2_reg, inst_type_4) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_MASK) | (inst_type_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_4(sq_instruction_cf_exec_2_reg, inst_serial_4) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_MASK) | (inst_serial_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_TYPE_5(sq_instruction_cf_exec_2_reg, inst_type_5) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_MASK) | (inst_type_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_SERIAL_5(sq_instruction_cf_exec_2_reg, inst_serial_5) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_MASK) | (inst_serial_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_0(sq_instruction_cf_exec_2_reg, inst_vc_0) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_MASK) | (inst_vc_0 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_1(sq_instruction_cf_exec_2_reg, inst_vc_1) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_MASK) | (inst_vc_1 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_2(sq_instruction_cf_exec_2_reg, inst_vc_2) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_MASK) | (inst_vc_2 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_3(sq_instruction_cf_exec_2_reg, inst_vc_3) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_MASK) | (inst_vc_3 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_4(sq_instruction_cf_exec_2_reg, inst_vc_4) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_MASK) | (inst_vc_4 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_INST_VC_5(sq_instruction_cf_exec_2_reg, inst_vc_5) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_MASK) | (inst_vc_5 << SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_BOOL_ADDR(sq_instruction_cf_exec_2_reg, bool_addr) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_CONDITION(sq_instruction_cf_exec_2_reg, condition) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_ADDRESS_MODE(sq_instruction_cf_exec_2_reg, address_mode) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_EXEC_2_SET_OPCODE(sq_instruction_cf_exec_2_reg, opcode) \ + sq_instruction_cf_exec_2_reg = (sq_instruction_cf_exec_2_reg & ~SQ_INSTRUCTION_CF_EXEC_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_2_t { + unsigned int inst_type_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE; + unsigned int inst_serial_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE; + unsigned int inst_type_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE; + unsigned int inst_serial_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE; + unsigned int inst_type_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE; + unsigned int inst_serial_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE; + unsigned int inst_type_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE; + unsigned int inst_serial_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE; + unsigned int inst_type_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE; + unsigned int inst_serial_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE; + unsigned int inst_type_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE; + unsigned int inst_serial_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE; + unsigned int inst_vc_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE; + unsigned int inst_vc_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE; + unsigned int inst_vc_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE; + unsigned int inst_vc_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE; + unsigned int inst_vc_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE; + unsigned int inst_vc_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE; + } sq_instruction_cf_exec_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_exec_2_t { + unsigned int opcode : SQ_INSTRUCTION_CF_EXEC_2_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_EXEC_2_ADDRESS_MODE_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_EXEC_2_CONDITION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_EXEC_2_BOOL_ADDR_SIZE; + unsigned int inst_vc_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_5_SIZE; + unsigned int inst_vc_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_4_SIZE; + unsigned int inst_vc_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_3_SIZE; + unsigned int inst_vc_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_2_SIZE; + unsigned int inst_vc_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_1_SIZE; + unsigned int inst_vc_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_VC_0_SIZE; + unsigned int inst_serial_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_5_SIZE; + unsigned int inst_type_5 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_5_SIZE; + unsigned int inst_serial_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_4_SIZE; + unsigned int inst_type_4 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_4_SIZE; + unsigned int inst_serial_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_3_SIZE; + unsigned int inst_type_3 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_3_SIZE; + unsigned int inst_serial_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_2_SIZE; + unsigned int inst_type_2 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_2_SIZE; + unsigned int inst_serial_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_1_SIZE; + unsigned int inst_type_1 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_1_SIZE; + unsigned int inst_serial_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_SERIAL_0_SIZE; + unsigned int inst_type_0 : SQ_INSTRUCTION_CF_EXEC_2_INST_TYPE_0_SIZE; + } sq_instruction_cf_exec_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_exec_2_t f; +} sq_instruction_cf_exec_2_u; + + +/* + * SQ_INSTRUCTION_CF_LOOP_0 struct + */ + +#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE 10 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE 6 +#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE 5 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE 11 + +#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT 0 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT 10 +#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT 16 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT 21 + +#define SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK 0x000003ff +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK 0x0000fc00 +#define SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK 0x001f0000 +#define SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK 0xffe00000 + +#define SQ_INSTRUCTION_CF_LOOP_0_MASK \ + (SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK | \ + SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) + +#define SQ_INSTRUCTION_CF_LOOP_0(address, reserved_0, loop_id, reserved_1) \ + ((address << SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT) | \ + (reserved_0 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT) | \ + (loop_id << SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT)) + +#define SQ_INSTRUCTION_CF_LOOP_0_GET_ADDRESS(sq_instruction_cf_loop_0) \ + ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_GET_RESERVED_0(sq_instruction_cf_loop_0) \ + ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_GET_LOOP_ID(sq_instruction_cf_loop_0) \ + ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_GET_RESERVED_1(sq_instruction_cf_loop_0) \ + ((sq_instruction_cf_loop_0 & SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT) + +#define SQ_INSTRUCTION_CF_LOOP_0_SET_ADDRESS(sq_instruction_cf_loop_0_reg, address) \ + sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_SET_RESERVED_0(sq_instruction_cf_loop_0_reg, reserved_0) \ + sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_SET_LOOP_ID(sq_instruction_cf_loop_0_reg, loop_id) \ + sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_MASK) | (loop_id << SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_0_SET_RESERVED_1(sq_instruction_cf_loop_0_reg, reserved_1) \ + sq_instruction_cf_loop_0_reg = (sq_instruction_cf_loop_0_reg & ~SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_0_t { + unsigned int address : SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE; + unsigned int loop_id : SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE; + } sq_instruction_cf_loop_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_0_t { + unsigned int reserved_1 : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_1_SIZE; + unsigned int loop_id : SQ_INSTRUCTION_CF_LOOP_0_LOOP_ID_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_LOOP_0_RESERVED_0_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_LOOP_0_ADDRESS_SIZE; + } sq_instruction_cf_loop_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_loop_0_t f; +} sq_instruction_cf_loop_0_u; + + +/* + * SQ_INSTRUCTION_CF_LOOP_1 struct + */ + +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE 11 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE 4 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE 10 +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE 6 + +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT 0 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT 11 +#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT 12 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT 16 +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT 26 + +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK 0x000007ff +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK 0x0000f000 +#define SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK 0x03ff0000 +#define SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK 0xfc000000 + +#define SQ_INSTRUCTION_CF_LOOP_1_MASK \ + (SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK | \ + SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) + +#define SQ_INSTRUCTION_CF_LOOP_1(reserved_0, address_mode, opcode, address, reserved_1) \ + ((reserved_0 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT) | \ + (address << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT)) + +#define SQ_INSTRUCTION_CF_LOOP_1_GET_RESERVED_0(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_GET_ADDRESS_MODE(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_GET_OPCODE(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_GET_ADDRESS(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_GET_RESERVED_1(sq_instruction_cf_loop_1) \ + ((sq_instruction_cf_loop_1 & SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT) + +#define SQ_INSTRUCTION_CF_LOOP_1_SET_RESERVED_0(sq_instruction_cf_loop_1_reg, reserved_0) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_SET_ADDRESS_MODE(sq_instruction_cf_loop_1_reg, address_mode) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_SET_OPCODE(sq_instruction_cf_loop_1_reg, opcode) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_SET_ADDRESS(sq_instruction_cf_loop_1_reg, address) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_1_SET_RESERVED_1(sq_instruction_cf_loop_1_reg, reserved_1) \ + sq_instruction_cf_loop_1_reg = (sq_instruction_cf_loop_1_reg & ~SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_1_t { + unsigned int reserved_0 : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE; + } sq_instruction_cf_loop_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_1_t { + unsigned int reserved_1 : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_1_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_LOOP_1_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_LOOP_1_ADDRESS_MODE_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_LOOP_1_RESERVED_0_SIZE; + } sq_instruction_cf_loop_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_loop_1_t f; +} sq_instruction_cf_loop_1_u; + + +/* + * SQ_INSTRUCTION_CF_LOOP_2 struct + */ + +#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE 5 +#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE 22 +#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE 4 + +#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT 0 +#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT 5 +#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT 27 +#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT 28 + +#define SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK 0x0000001f +#define SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK 0x07ffffe0 +#define SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK 0xf0000000 + +#define SQ_INSTRUCTION_CF_LOOP_2_MASK \ + (SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK | \ + SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) + +#define SQ_INSTRUCTION_CF_LOOP_2(loop_id, reserved, address_mode, opcode) \ + ((loop_id << SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT) | \ + (reserved << SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_CF_LOOP_2_GET_LOOP_ID(sq_instruction_cf_loop_2) \ + ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_GET_RESERVED(sq_instruction_cf_loop_2) \ + ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_GET_ADDRESS_MODE(sq_instruction_cf_loop_2) \ + ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_GET_OPCODE(sq_instruction_cf_loop_2) \ + ((sq_instruction_cf_loop_2 & SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_CF_LOOP_2_SET_LOOP_ID(sq_instruction_cf_loop_2_reg, loop_id) \ + sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_MASK) | (loop_id << SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_SET_RESERVED(sq_instruction_cf_loop_2_reg, reserved) \ + sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_SET_ADDRESS_MODE(sq_instruction_cf_loop_2_reg, address_mode) \ + sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_LOOP_2_SET_OPCODE(sq_instruction_cf_loop_2_reg, opcode) \ + sq_instruction_cf_loop_2_reg = (sq_instruction_cf_loop_2_reg & ~SQ_INSTRUCTION_CF_LOOP_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_2_t { + unsigned int loop_id : SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE; + } sq_instruction_cf_loop_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_loop_2_t { + unsigned int opcode : SQ_INSTRUCTION_CF_LOOP_2_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_LOOP_2_ADDRESS_MODE_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_LOOP_2_RESERVED_SIZE; + unsigned int loop_id : SQ_INSTRUCTION_CF_LOOP_2_LOOP_ID_SIZE; + } sq_instruction_cf_loop_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_loop_2_t f; +} sq_instruction_cf_loop_2_u; + + +/* + * SQ_INSTRUCTION_CF_JMP_CALL_0 struct + */ + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE 10 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE 3 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE 17 + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT 0 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT 10 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT 13 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT 14 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT 15 + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK 0x000003ff +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK 0x00001c00 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK 0x00002000 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK 0x00004000 +#define SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK 0xffff8000 + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_MASK \ + (SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) + +#define SQ_INSTRUCTION_CF_JMP_CALL_0(address, reserved_0, force_call, predicated_jmp, reserved_1) \ + ((address << SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT) | \ + (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT) | \ + (force_call << SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT) | \ + (predicated_jmp << SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT)) + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_ADDRESS(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_RESERVED_0(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_FORCE_CALL(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_PREDICATED_JMP(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_GET_RESERVED_1(sq_instruction_cf_jmp_call_0) \ + ((sq_instruction_cf_jmp_call_0 & SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT) + +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_ADDRESS(sq_instruction_cf_jmp_call_0_reg, address) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_RESERVED_0(sq_instruction_cf_jmp_call_0_reg, reserved_0) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_FORCE_CALL(sq_instruction_cf_jmp_call_0_reg, force_call) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_MASK) | (force_call << SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_PREDICATED_JMP(sq_instruction_cf_jmp_call_0_reg, predicated_jmp) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_MASK) | (predicated_jmp << SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_0_SET_RESERVED_1(sq_instruction_cf_jmp_call_0_reg, reserved_1) \ + sq_instruction_cf_jmp_call_0_reg = (sq_instruction_cf_jmp_call_0_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_0_t { + unsigned int address : SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE; + unsigned int force_call : SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE; + unsigned int predicated_jmp : SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE; + } sq_instruction_cf_jmp_call_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_0_t { + unsigned int reserved_1 : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_1_SIZE; + unsigned int predicated_jmp : SQ_INSTRUCTION_CF_JMP_CALL_0_PREDICATED_JMP_SIZE; + unsigned int force_call : SQ_INSTRUCTION_CF_JMP_CALL_0_FORCE_CALL_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_JMP_CALL_0_RESERVED_0_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_JMP_CALL_0_ADDRESS_SIZE; + } sq_instruction_cf_jmp_call_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_jmp_call_0_t f; +} sq_instruction_cf_jmp_call_0_u; + + +/* + * SQ_INSTRUCTION_CF_JMP_CALL_1 struct + */ + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE 8 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE 4 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE 10 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE 3 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE 2 + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT 0 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT 2 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT 10 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT 11 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT 12 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT 16 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT 26 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT 29 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT 30 + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK 0x00000001 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK 0x00000002 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK 0x000003fc +#define SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK 0x00000400 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK 0x0000f000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK 0x03ff0000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK 0x1c000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK 0x20000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK 0xc0000000 + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_MASK \ + (SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) + +#define SQ_INSTRUCTION_CF_JMP_CALL_1(reserved_0, direction, bool_addr, condition, address_mode, opcode, address, reserved_1, force_call, reserved_2) \ + ((reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT) | \ + (direction << SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT) | \ + (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT) | \ + (condition << SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT) | \ + (address << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT) | \ + (force_call << SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT) | \ + (reserved_2 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT)) + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_0(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_DIRECTION(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_BOOL_ADDR(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_CONDITION(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_ADDRESS_MODE(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_OPCODE(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_ADDRESS(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_1(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_FORCE_CALL(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_GET_RESERVED_2(sq_instruction_cf_jmp_call_1) \ + ((sq_instruction_cf_jmp_call_1 & SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT) + +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_0(sq_instruction_cf_jmp_call_1_reg, reserved_0) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_DIRECTION(sq_instruction_cf_jmp_call_1_reg, direction) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_MASK) | (direction << SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_BOOL_ADDR(sq_instruction_cf_jmp_call_1_reg, bool_addr) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_CONDITION(sq_instruction_cf_jmp_call_1_reg, condition) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_ADDRESS_MODE(sq_instruction_cf_jmp_call_1_reg, address_mode) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_OPCODE(sq_instruction_cf_jmp_call_1_reg, opcode) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_ADDRESS(sq_instruction_cf_jmp_call_1_reg, address) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MASK) | (address << SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_1(sq_instruction_cf_jmp_call_1_reg, reserved_1) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_FORCE_CALL(sq_instruction_cf_jmp_call_1_reg, force_call) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_MASK) | (force_call << SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_1_SET_RESERVED_2(sq_instruction_cf_jmp_call_1_reg, reserved_2) \ + sq_instruction_cf_jmp_call_1_reg = (sq_instruction_cf_jmp_call_1_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_MASK) | (reserved_2 << SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_1_t { + unsigned int reserved_0 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE; + unsigned int direction : SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE; + unsigned int force_call : SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE; + unsigned int reserved_2 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE; + } sq_instruction_cf_jmp_call_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_1_t { + unsigned int reserved_2 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_2_SIZE; + unsigned int force_call : SQ_INSTRUCTION_CF_JMP_CALL_1_FORCE_CALL_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_1_SIZE; + unsigned int address : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_JMP_CALL_1_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_JMP_CALL_1_ADDRESS_MODE_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_JMP_CALL_1_CONDITION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_JMP_CALL_1_BOOL_ADDR_SIZE; + unsigned int direction : SQ_INSTRUCTION_CF_JMP_CALL_1_DIRECTION_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_JMP_CALL_1_RESERVED_0_SIZE; + } sq_instruction_cf_jmp_call_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_jmp_call_1_t f; +} sq_instruction_cf_jmp_call_1_u; + + +/* + * SQ_INSTRUCTION_CF_JMP_CALL_2 struct + */ + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE 17 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE 8 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE 4 + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT 0 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT 17 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT 18 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT 26 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT 27 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT 28 + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK 0x0001ffff +#define SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK 0x00020000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK 0x03fc0000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK 0x04000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK 0xf0000000 + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_MASK \ + (SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK | \ + SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) + +#define SQ_INSTRUCTION_CF_JMP_CALL_2(reserved, direction, bool_addr, condition, address_mode, opcode) \ + ((reserved << SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT) | \ + (direction << SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT) | \ + (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT) | \ + (condition << SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT) | \ + (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_RESERVED(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_DIRECTION(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_BOOL_ADDR(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_CONDITION(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_ADDRESS_MODE(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_GET_OPCODE(sq_instruction_cf_jmp_call_2) \ + ((sq_instruction_cf_jmp_call_2 & SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_RESERVED(sq_instruction_cf_jmp_call_2_reg, reserved) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_DIRECTION(sq_instruction_cf_jmp_call_2_reg, direction) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_MASK) | (direction << SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_BOOL_ADDR(sq_instruction_cf_jmp_call_2_reg, bool_addr) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_MASK) | (bool_addr << SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_CONDITION(sq_instruction_cf_jmp_call_2_reg, condition) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_MASK) | (condition << SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_ADDRESS_MODE(sq_instruction_cf_jmp_call_2_reg, address_mode) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_MASK) | (address_mode << SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_JMP_CALL_2_SET_OPCODE(sq_instruction_cf_jmp_call_2_reg, opcode) \ + sq_instruction_cf_jmp_call_2_reg = (sq_instruction_cf_jmp_call_2_reg & ~SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_2_t { + unsigned int reserved : SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE; + unsigned int direction : SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE; + } sq_instruction_cf_jmp_call_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_jmp_call_2_t { + unsigned int opcode : SQ_INSTRUCTION_CF_JMP_CALL_2_OPCODE_SIZE; + unsigned int address_mode : SQ_INSTRUCTION_CF_JMP_CALL_2_ADDRESS_MODE_SIZE; + unsigned int condition : SQ_INSTRUCTION_CF_JMP_CALL_2_CONDITION_SIZE; + unsigned int bool_addr : SQ_INSTRUCTION_CF_JMP_CALL_2_BOOL_ADDR_SIZE; + unsigned int direction : SQ_INSTRUCTION_CF_JMP_CALL_2_DIRECTION_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_JMP_CALL_2_RESERVED_SIZE; + } sq_instruction_cf_jmp_call_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_jmp_call_2_t f; +} sq_instruction_cf_jmp_call_2_u; + + +/* + * SQ_INSTRUCTION_CF_ALLOC_0 struct + */ + +#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE 4 +#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE 28 + +#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT 0 +#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT 4 + +#define SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK 0x0000000f +#define SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK 0xfffffff0 + +#define SQ_INSTRUCTION_CF_ALLOC_0_MASK \ + (SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) + +#define SQ_INSTRUCTION_CF_ALLOC_0(size, reserved) \ + ((size << SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT) | \ + (reserved << SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT)) + +#define SQ_INSTRUCTION_CF_ALLOC_0_GET_SIZE(sq_instruction_cf_alloc_0) \ + ((sq_instruction_cf_alloc_0 & SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_0_GET_RESERVED(sq_instruction_cf_alloc_0) \ + ((sq_instruction_cf_alloc_0 & SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) >> SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT) + +#define SQ_INSTRUCTION_CF_ALLOC_0_SET_SIZE(sq_instruction_cf_alloc_0_reg, size) \ + sq_instruction_cf_alloc_0_reg = (sq_instruction_cf_alloc_0_reg & ~SQ_INSTRUCTION_CF_ALLOC_0_SIZE_MASK) | (size << SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_0_SET_RESERVED(sq_instruction_cf_alloc_0_reg, reserved) \ + sq_instruction_cf_alloc_0_reg = (sq_instruction_cf_alloc_0_reg & ~SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_0_t { + unsigned int size : SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE; + } sq_instruction_cf_alloc_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_0_t { + unsigned int reserved : SQ_INSTRUCTION_CF_ALLOC_0_RESERVED_SIZE; + unsigned int size : SQ_INSTRUCTION_CF_ALLOC_0_SIZE_SIZE; + } sq_instruction_cf_alloc_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_alloc_0_t f; +} sq_instruction_cf_alloc_0_u; + + +/* + * SQ_INSTRUCTION_CF_ALLOC_1 struct + */ + +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE 8 +#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE 1 +#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE 2 +#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE 4 +#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE 4 +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE 12 + +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT 0 +#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT 8 +#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT 9 +#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT 11 +#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT 12 +#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT 16 +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT 20 + +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK 0x000000ff +#define SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK 0x00000100 +#define SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK 0x00000600 +#define SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK 0x00000800 +#define SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK 0x0000f000 +#define SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK 0x000f0000 +#define SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK 0xfff00000 + +#define SQ_INSTRUCTION_CF_ALLOC_1_MASK \ + (SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) + +#define SQ_INSTRUCTION_CF_ALLOC_1(reserved_0, no_serial, buffer_select, alloc_mode, opcode, size, reserved_1) \ + ((reserved_0 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT) | \ + (no_serial << SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT) | \ + (buffer_select << SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT) | \ + (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT) | \ + (size << SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT) | \ + (reserved_1 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT)) + +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_RESERVED_0(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_NO_SERIAL(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_BUFFER_SELECT(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_ALLOC_MODE(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_OPCODE(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_SIZE(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_GET_RESERVED_1(sq_instruction_cf_alloc_1) \ + ((sq_instruction_cf_alloc_1 & SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) >> SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT) + +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_RESERVED_0(sq_instruction_cf_alloc_1_reg, reserved_0) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_MASK) | (reserved_0 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_NO_SERIAL(sq_instruction_cf_alloc_1_reg, no_serial) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_MASK) | (no_serial << SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_BUFFER_SELECT(sq_instruction_cf_alloc_1_reg, buffer_select) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_MASK) | (buffer_select << SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_ALLOC_MODE(sq_instruction_cf_alloc_1_reg, alloc_mode) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_MASK) | (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_OPCODE(sq_instruction_cf_alloc_1_reg, opcode) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_SIZE(sq_instruction_cf_alloc_1_reg, size) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_SIZE_MASK) | (size << SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_1_SET_RESERVED_1(sq_instruction_cf_alloc_1_reg, reserved_1) \ + sq_instruction_cf_alloc_1_reg = (sq_instruction_cf_alloc_1_reg & ~SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_MASK) | (reserved_1 << SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_1_t { + unsigned int reserved_0 : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE; + unsigned int no_serial : SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE; + unsigned int buffer_select : SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE; + unsigned int alloc_mode : SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE; + unsigned int size : SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE; + unsigned int reserved_1 : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE; + } sq_instruction_cf_alloc_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_1_t { + unsigned int reserved_1 : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_1_SIZE; + unsigned int size : SQ_INSTRUCTION_CF_ALLOC_1_SIZE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_ALLOC_1_OPCODE_SIZE; + unsigned int alloc_mode : SQ_INSTRUCTION_CF_ALLOC_1_ALLOC_MODE_SIZE; + unsigned int buffer_select : SQ_INSTRUCTION_CF_ALLOC_1_BUFFER_SELECT_SIZE; + unsigned int no_serial : SQ_INSTRUCTION_CF_ALLOC_1_NO_SERIAL_SIZE; + unsigned int reserved_0 : SQ_INSTRUCTION_CF_ALLOC_1_RESERVED_0_SIZE; + } sq_instruction_cf_alloc_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_alloc_1_t f; +} sq_instruction_cf_alloc_1_u; + + +/* + * SQ_INSTRUCTION_CF_ALLOC_2 struct + */ + +#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE 24 +#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE 1 +#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE 2 +#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE 1 +#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE 4 + +#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT 0 +#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT 24 +#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT 25 +#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT 27 +#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT 28 + +#define SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK 0x00ffffff +#define SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK 0x01000000 +#define SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK 0x06000000 +#define SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK 0x08000000 +#define SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK 0xf0000000 + +#define SQ_INSTRUCTION_CF_ALLOC_2_MASK \ + (SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK | \ + SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) + +#define SQ_INSTRUCTION_CF_ALLOC_2(reserved, no_serial, buffer_select, alloc_mode, opcode) \ + ((reserved << SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT) | \ + (no_serial << SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT) | \ + (buffer_select << SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT) | \ + (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT) | \ + (opcode << SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT)) + +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_RESERVED(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_NO_SERIAL(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_BUFFER_SELECT(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_ALLOC_MODE(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_GET_OPCODE(sq_instruction_cf_alloc_2) \ + ((sq_instruction_cf_alloc_2 & SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) >> SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT) + +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_RESERVED(sq_instruction_cf_alloc_2_reg, reserved) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_MASK) | (reserved << SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_NO_SERIAL(sq_instruction_cf_alloc_2_reg, no_serial) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_MASK) | (no_serial << SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_BUFFER_SELECT(sq_instruction_cf_alloc_2_reg, buffer_select) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_MASK) | (buffer_select << SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_ALLOC_MODE(sq_instruction_cf_alloc_2_reg, alloc_mode) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_MASK) | (alloc_mode << SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SHIFT) +#define SQ_INSTRUCTION_CF_ALLOC_2_SET_OPCODE(sq_instruction_cf_alloc_2_reg, opcode) \ + sq_instruction_cf_alloc_2_reg = (sq_instruction_cf_alloc_2_reg & ~SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_2_t { + unsigned int reserved : SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE; + unsigned int no_serial : SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE; + unsigned int buffer_select : SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE; + unsigned int alloc_mode : SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE; + unsigned int opcode : SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE; + } sq_instruction_cf_alloc_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_cf_alloc_2_t { + unsigned int opcode : SQ_INSTRUCTION_CF_ALLOC_2_OPCODE_SIZE; + unsigned int alloc_mode : SQ_INSTRUCTION_CF_ALLOC_2_ALLOC_MODE_SIZE; + unsigned int buffer_select : SQ_INSTRUCTION_CF_ALLOC_2_BUFFER_SELECT_SIZE; + unsigned int no_serial : SQ_INSTRUCTION_CF_ALLOC_2_NO_SERIAL_SIZE; + unsigned int reserved : SQ_INSTRUCTION_CF_ALLOC_2_RESERVED_SIZE; + } sq_instruction_cf_alloc_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_cf_alloc_2_t f; +} sq_instruction_cf_alloc_2_u; + + +/* + * SQ_INSTRUCTION_TFETCH_0 struct + */ + +#define SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE 6 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE 6 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE 2 + +#define SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT 0 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT 5 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT 11 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT 12 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT 18 +#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT 19 +#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT 20 +#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT 25 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT 26 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT 28 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT 30 + +#define SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK 0x0000001f +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK 0x000007e0 +#define SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK 0x00000800 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK 0x0003f000 +#define SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK 0x00040000 +#define SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK 0x00080000 +#define SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK 0x01f00000 +#define SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK 0x02000000 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK 0x0c000000 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK 0x30000000 +#define SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK 0xc0000000 + +#define SQ_INSTRUCTION_TFETCH_0_MASK \ + (SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK | \ + SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK | \ + SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK | \ + SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK | \ + SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK | \ + SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK | \ + SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) + +#define SQ_INSTRUCTION_TFETCH_0(opcode, src_gpr, src_gpr_am, dst_gpr, dst_gpr_am, fetch_valid_only, const_index, tx_coord_denorm, src_sel_x, src_sel_y, src_sel_z) \ + ((opcode << SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT) | \ + (src_gpr << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT) | \ + (src_gpr_am << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT) | \ + (dst_gpr << SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT) | \ + (dst_gpr_am << SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT) | \ + (fetch_valid_only << SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT) | \ + (const_index << SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT) | \ + (tx_coord_denorm << SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT) | \ + (src_sel_x << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT) | \ + (src_sel_y << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT) | \ + (src_sel_z << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT)) + +#define SQ_INSTRUCTION_TFETCH_0_GET_OPCODE(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK) >> SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_GPR(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_GPR_AM(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_DST_GPR(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK) >> SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_DST_GPR_AM(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK) >> SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_FETCH_VALID_ONLY(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK) >> SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_CONST_INDEX(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK) >> SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_TX_COORD_DENORM(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK) >> SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_X(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_Y(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_GET_SRC_SEL_Z(sq_instruction_tfetch_0) \ + ((sq_instruction_tfetch_0 & SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) >> SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT) + +#define SQ_INSTRUCTION_TFETCH_0_SET_OPCODE(sq_instruction_tfetch_0_reg, opcode) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_TFETCH_0_OPCODE_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_GPR(sq_instruction_tfetch_0_reg, src_gpr) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_GPR_MASK) | (src_gpr << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_GPR_AM(sq_instruction_tfetch_0_reg, src_gpr_am) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_MASK) | (src_gpr_am << SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_DST_GPR(sq_instruction_tfetch_0_reg, dst_gpr) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_DST_GPR_MASK) | (dst_gpr << SQ_INSTRUCTION_TFETCH_0_DST_GPR_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_DST_GPR_AM(sq_instruction_tfetch_0_reg, dst_gpr_am) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_MASK) | (dst_gpr_am << SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_FETCH_VALID_ONLY(sq_instruction_tfetch_0_reg, fetch_valid_only) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_MASK) | (fetch_valid_only << SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_CONST_INDEX(sq_instruction_tfetch_0_reg, const_index) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_MASK) | (const_index << SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_TX_COORD_DENORM(sq_instruction_tfetch_0_reg, tx_coord_denorm) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_MASK) | (tx_coord_denorm << SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_X(sq_instruction_tfetch_0_reg, src_sel_x) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_MASK) | (src_sel_x << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_Y(sq_instruction_tfetch_0_reg, src_sel_y) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_MASK) | (src_sel_y << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_0_SET_SRC_SEL_Z(sq_instruction_tfetch_0_reg, src_sel_z) \ + sq_instruction_tfetch_0_reg = (sq_instruction_tfetch_0_reg & ~SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_MASK) | (src_sel_z << SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_0_t { + unsigned int opcode : SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE; + unsigned int src_gpr : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE; + unsigned int src_gpr_am : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE; + unsigned int dst_gpr : SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE; + unsigned int dst_gpr_am : SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE; + unsigned int fetch_valid_only : SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE; + unsigned int const_index : SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE; + unsigned int tx_coord_denorm : SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE; + unsigned int src_sel_x : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE; + unsigned int src_sel_y : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE; + unsigned int src_sel_z : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE; + } sq_instruction_tfetch_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_0_t { + unsigned int src_sel_z : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Z_SIZE; + unsigned int src_sel_y : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_Y_SIZE; + unsigned int src_sel_x : SQ_INSTRUCTION_TFETCH_0_SRC_SEL_X_SIZE; + unsigned int tx_coord_denorm : SQ_INSTRUCTION_TFETCH_0_TX_COORD_DENORM_SIZE; + unsigned int const_index : SQ_INSTRUCTION_TFETCH_0_CONST_INDEX_SIZE; + unsigned int fetch_valid_only : SQ_INSTRUCTION_TFETCH_0_FETCH_VALID_ONLY_SIZE; + unsigned int dst_gpr_am : SQ_INSTRUCTION_TFETCH_0_DST_GPR_AM_SIZE; + unsigned int dst_gpr : SQ_INSTRUCTION_TFETCH_0_DST_GPR_SIZE; + unsigned int src_gpr_am : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_AM_SIZE; + unsigned int src_gpr : SQ_INSTRUCTION_TFETCH_0_SRC_GPR_SIZE; + unsigned int opcode : SQ_INSTRUCTION_TFETCH_0_OPCODE_SIZE; + } sq_instruction_tfetch_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_tfetch_0_t f; +} sq_instruction_tfetch_0_u; + + +/* + * SQ_INSTRUCTION_TFETCH_1 struct + */ + +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE 3 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE 2 +#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE 1 + +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT 0 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT 3 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT 6 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT 9 +#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT 12 +#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT 14 +#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT 16 +#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT 18 +#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT 21 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT 24 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT 26 +#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT 28 +#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT 29 +#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT 31 + +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK 0x00000007 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK 0x00000038 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK 0x000001c0 +#define SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK 0x00000e00 +#define SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK 0x00003000 +#define SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK 0x0000c000 +#define SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK 0x00030000 +#define SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK 0x001c0000 +#define SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK 0x00e00000 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK 0x03000000 +#define SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK 0x0c000000 +#define SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK 0x10000000 +#define SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK 0x60000000 +#define SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK 0x80000000 + +#define SQ_INSTRUCTION_TFETCH_1_MASK \ + (SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK | \ + SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK | \ + SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK | \ + SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK | \ + SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK | \ + SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK | \ + SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK | \ + SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) + +#define SQ_INSTRUCTION_TFETCH_1(dst_sel_x, dst_sel_y, dst_sel_z, dst_sel_w, mag_filter, min_filter, mip_filter, aniso_filter, arbitrary_filter, vol_mag_filter, vol_min_filter, use_comp_lod, use_reg_lod, pred_select) \ + ((dst_sel_x << SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT) | \ + (dst_sel_y << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT) | \ + (dst_sel_z << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT) | \ + (dst_sel_w << SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT) | \ + (mag_filter << SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT) | \ + (min_filter << SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT) | \ + (mip_filter << SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT) | \ + (aniso_filter << SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT) | \ + (arbitrary_filter << SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT) | \ + (vol_mag_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT) | \ + (vol_min_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT) | \ + (use_comp_lod << SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT) | \ + (use_reg_lod << SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT) | \ + (pred_select << SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT)) + +#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_X(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_Y(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_Z(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_DST_SEL_W(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK) >> SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_MAG_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_MIN_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_MIP_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_ANISO_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_ARBITRARY_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_VOL_MAG_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_VOL_MIN_FILTER(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK) >> SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_USE_COMP_LOD(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK) >> SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_USE_REG_LOD(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK) >> SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_GET_PRED_SELECT(sq_instruction_tfetch_1) \ + ((sq_instruction_tfetch_1 & SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT) + +#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_X(sq_instruction_tfetch_1_reg, dst_sel_x) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_MASK) | (dst_sel_x << SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_Y(sq_instruction_tfetch_1_reg, dst_sel_y) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_MASK) | (dst_sel_y << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_Z(sq_instruction_tfetch_1_reg, dst_sel_z) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_MASK) | (dst_sel_z << SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_DST_SEL_W(sq_instruction_tfetch_1_reg, dst_sel_w) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_MASK) | (dst_sel_w << SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_MAG_FILTER(sq_instruction_tfetch_1_reg, mag_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_MASK) | (mag_filter << SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_MIN_FILTER(sq_instruction_tfetch_1_reg, min_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_MASK) | (min_filter << SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_MIP_FILTER(sq_instruction_tfetch_1_reg, mip_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_MASK) | (mip_filter << SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_ANISO_FILTER(sq_instruction_tfetch_1_reg, aniso_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_MASK) | (aniso_filter << SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_ARBITRARY_FILTER(sq_instruction_tfetch_1_reg, arbitrary_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_MASK) | (arbitrary_filter << SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_VOL_MAG_FILTER(sq_instruction_tfetch_1_reg, vol_mag_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_MASK) | (vol_mag_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_VOL_MIN_FILTER(sq_instruction_tfetch_1_reg, vol_min_filter) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_MASK) | (vol_min_filter << SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_USE_COMP_LOD(sq_instruction_tfetch_1_reg, use_comp_lod) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_MASK) | (use_comp_lod << SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_USE_REG_LOD(sq_instruction_tfetch_1_reg, use_reg_lod) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_MASK) | (use_reg_lod << SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SHIFT) +#define SQ_INSTRUCTION_TFETCH_1_SET_PRED_SELECT(sq_instruction_tfetch_1_reg, pred_select) \ + sq_instruction_tfetch_1_reg = (sq_instruction_tfetch_1_reg & ~SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_1_t { + unsigned int dst_sel_x : SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE; + unsigned int dst_sel_y : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE; + unsigned int dst_sel_z : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE; + unsigned int dst_sel_w : SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE; + unsigned int mag_filter : SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE; + unsigned int min_filter : SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE; + unsigned int mip_filter : SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE; + unsigned int aniso_filter : SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE; + unsigned int arbitrary_filter : SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE; + unsigned int vol_mag_filter : SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE; + unsigned int vol_min_filter : SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE; + unsigned int use_comp_lod : SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE; + unsigned int use_reg_lod : SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE; + unsigned int pred_select : SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE; + } sq_instruction_tfetch_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_1_t { + unsigned int pred_select : SQ_INSTRUCTION_TFETCH_1_PRED_SELECT_SIZE; + unsigned int use_reg_lod : SQ_INSTRUCTION_TFETCH_1_USE_REG_LOD_SIZE; + unsigned int use_comp_lod : SQ_INSTRUCTION_TFETCH_1_USE_COMP_LOD_SIZE; + unsigned int vol_min_filter : SQ_INSTRUCTION_TFETCH_1_VOL_MIN_FILTER_SIZE; + unsigned int vol_mag_filter : SQ_INSTRUCTION_TFETCH_1_VOL_MAG_FILTER_SIZE; + unsigned int arbitrary_filter : SQ_INSTRUCTION_TFETCH_1_ARBITRARY_FILTER_SIZE; + unsigned int aniso_filter : SQ_INSTRUCTION_TFETCH_1_ANISO_FILTER_SIZE; + unsigned int mip_filter : SQ_INSTRUCTION_TFETCH_1_MIP_FILTER_SIZE; + unsigned int min_filter : SQ_INSTRUCTION_TFETCH_1_MIN_FILTER_SIZE; + unsigned int mag_filter : SQ_INSTRUCTION_TFETCH_1_MAG_FILTER_SIZE; + unsigned int dst_sel_w : SQ_INSTRUCTION_TFETCH_1_DST_SEL_W_SIZE; + unsigned int dst_sel_z : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Z_SIZE; + unsigned int dst_sel_y : SQ_INSTRUCTION_TFETCH_1_DST_SEL_Y_SIZE; + unsigned int dst_sel_x : SQ_INSTRUCTION_TFETCH_1_DST_SEL_X_SIZE; + } sq_instruction_tfetch_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_tfetch_1_t f; +} sq_instruction_tfetch_1_u; + + +/* + * SQ_INSTRUCTION_TFETCH_2 struct + */ + +#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE 1 +#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE 7 +#define SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE 7 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE 5 +#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE 1 + +#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT 0 +#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT 1 +#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT 2 +#define SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT 9 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT 16 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT 21 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT 26 +#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT 31 + +#define SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK 0x00000001 +#define SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK 0x00000002 +#define SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK 0x000001fc +#define SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK 0x0000fe00 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK 0x001f0000 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK 0x03e00000 +#define SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK 0x7c000000 +#define SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK 0x80000000 + +#define SQ_INSTRUCTION_TFETCH_2_MASK \ + (SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK | \ + SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK | \ + SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK | \ + SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK | \ + SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK | \ + SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK | \ + SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK | \ + SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) + +#define SQ_INSTRUCTION_TFETCH_2(use_reg_gradients, sample_location, lod_bias, unused, offset_x, offset_y, offset_z, pred_condition) \ + ((use_reg_gradients << SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT) | \ + (sample_location << SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT) | \ + (lod_bias << SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT) | \ + (unused << SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT) | \ + (offset_x << SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT) | \ + (offset_y << SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT) | \ + (offset_z << SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT) | \ + (pred_condition << SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT)) + +#define SQ_INSTRUCTION_TFETCH_2_GET_USE_REG_GRADIENTS(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK) >> SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_SAMPLE_LOCATION(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK) >> SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_LOD_BIAS(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK) >> SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_UNUSED(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK) >> SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_X(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_Y(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_OFFSET_Z(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK) >> SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_GET_PRED_CONDITION(sq_instruction_tfetch_2) \ + ((sq_instruction_tfetch_2 & SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) >> SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT) + +#define SQ_INSTRUCTION_TFETCH_2_SET_USE_REG_GRADIENTS(sq_instruction_tfetch_2_reg, use_reg_gradients) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_MASK) | (use_reg_gradients << SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_SAMPLE_LOCATION(sq_instruction_tfetch_2_reg, sample_location) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_MASK) | (sample_location << SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_LOD_BIAS(sq_instruction_tfetch_2_reg, lod_bias) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_MASK) | (lod_bias << SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_UNUSED(sq_instruction_tfetch_2_reg, unused) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_UNUSED_MASK) | (unused << SQ_INSTRUCTION_TFETCH_2_UNUSED_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_X(sq_instruction_tfetch_2_reg, offset_x) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_X_MASK) | (offset_x << SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_Y(sq_instruction_tfetch_2_reg, offset_y) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_MASK) | (offset_y << SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_OFFSET_Z(sq_instruction_tfetch_2_reg, offset_z) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_MASK) | (offset_z << SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SHIFT) +#define SQ_INSTRUCTION_TFETCH_2_SET_PRED_CONDITION(sq_instruction_tfetch_2_reg, pred_condition) \ + sq_instruction_tfetch_2_reg = (sq_instruction_tfetch_2_reg & ~SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_MASK) | (pred_condition << SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_2_t { + unsigned int use_reg_gradients : SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE; + unsigned int sample_location : SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE; + unsigned int lod_bias : SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE; + unsigned int unused : SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE; + unsigned int offset_x : SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE; + unsigned int offset_y : SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE; + unsigned int offset_z : SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE; + unsigned int pred_condition : SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE; + } sq_instruction_tfetch_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_tfetch_2_t { + unsigned int pred_condition : SQ_INSTRUCTION_TFETCH_2_PRED_CONDITION_SIZE; + unsigned int offset_z : SQ_INSTRUCTION_TFETCH_2_OFFSET_Z_SIZE; + unsigned int offset_y : SQ_INSTRUCTION_TFETCH_2_OFFSET_Y_SIZE; + unsigned int offset_x : SQ_INSTRUCTION_TFETCH_2_OFFSET_X_SIZE; + unsigned int unused : SQ_INSTRUCTION_TFETCH_2_UNUSED_SIZE; + unsigned int lod_bias : SQ_INSTRUCTION_TFETCH_2_LOD_BIAS_SIZE; + unsigned int sample_location : SQ_INSTRUCTION_TFETCH_2_SAMPLE_LOCATION_SIZE; + unsigned int use_reg_gradients : SQ_INSTRUCTION_TFETCH_2_USE_REG_GRADIENTS_SIZE; + } sq_instruction_tfetch_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_tfetch_2_t f; +} sq_instruction_tfetch_2_u; + + +/* + * SQ_INSTRUCTION_VFETCH_0 struct + */ + +#define SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE 5 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE 6 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE 6 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE 5 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE 2 +#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE 2 + +#define SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT 0 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT 5 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT 11 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT 12 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT 18 +#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT 19 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT 20 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT 25 +#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT 30 + +#define SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK 0x0000001f +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK 0x000007e0 +#define SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK 0x00000800 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK 0x0003f000 +#define SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK 0x00040000 +#define SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK 0x00080000 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK 0x01f00000 +#define SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK 0x06000000 +#define SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK 0xc0000000 + +#define SQ_INSTRUCTION_VFETCH_0_MASK \ + (SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK | \ + SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK | \ + SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK | \ + SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK | \ + SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK | \ + SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK | \ + SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK | \ + SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK | \ + SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) + +#define SQ_INSTRUCTION_VFETCH_0(opcode, src_gpr, src_gpr_am, dst_gpr, dst_gpr_am, must_be_one, const_index, const_index_sel, src_sel) \ + ((opcode << SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT) | \ + (src_gpr << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT) | \ + (src_gpr_am << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT) | \ + (dst_gpr << SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT) | \ + (dst_gpr_am << SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT) | \ + (must_be_one << SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT) | \ + (const_index << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT) | \ + (const_index_sel << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT) | \ + (src_sel << SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT)) + +#define SQ_INSTRUCTION_VFETCH_0_GET_OPCODE(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK) >> SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_GPR(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_GPR_AM(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_DST_GPR(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK) >> SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_DST_GPR_AM(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK) >> SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_MUST_BE_ONE(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK) >> SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_CONST_INDEX(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK) >> SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_CONST_INDEX_SEL(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK) >> SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_GET_SRC_SEL(sq_instruction_vfetch_0) \ + ((sq_instruction_vfetch_0 & SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) >> SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT) + +#define SQ_INSTRUCTION_VFETCH_0_SET_OPCODE(sq_instruction_vfetch_0_reg, opcode) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_OPCODE_MASK) | (opcode << SQ_INSTRUCTION_VFETCH_0_OPCODE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_GPR(sq_instruction_vfetch_0_reg, src_gpr) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_GPR_MASK) | (src_gpr << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_GPR_AM(sq_instruction_vfetch_0_reg, src_gpr_am) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_MASK) | (src_gpr_am << SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_DST_GPR(sq_instruction_vfetch_0_reg, dst_gpr) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_DST_GPR_MASK) | (dst_gpr << SQ_INSTRUCTION_VFETCH_0_DST_GPR_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_DST_GPR_AM(sq_instruction_vfetch_0_reg, dst_gpr_am) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_MASK) | (dst_gpr_am << SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_MUST_BE_ONE(sq_instruction_vfetch_0_reg, must_be_one) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_MASK) | (must_be_one << SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_CONST_INDEX(sq_instruction_vfetch_0_reg, const_index) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_MASK) | (const_index << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_CONST_INDEX_SEL(sq_instruction_vfetch_0_reg, const_index_sel) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_MASK) | (const_index_sel << SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_0_SET_SRC_SEL(sq_instruction_vfetch_0_reg, src_sel) \ + sq_instruction_vfetch_0_reg = (sq_instruction_vfetch_0_reg & ~SQ_INSTRUCTION_VFETCH_0_SRC_SEL_MASK) | (src_sel << SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_0_t { + unsigned int opcode : SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE; + unsigned int src_gpr : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE; + unsigned int src_gpr_am : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE; + unsigned int dst_gpr : SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE; + unsigned int dst_gpr_am : SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE; + unsigned int must_be_one : SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE; + unsigned int const_index : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE; + unsigned int const_index_sel : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE; + unsigned int : 3; + unsigned int src_sel : SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE; + } sq_instruction_vfetch_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_0_t { + unsigned int src_sel : SQ_INSTRUCTION_VFETCH_0_SRC_SEL_SIZE; + unsigned int : 3; + unsigned int const_index_sel : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SEL_SIZE; + unsigned int const_index : SQ_INSTRUCTION_VFETCH_0_CONST_INDEX_SIZE; + unsigned int must_be_one : SQ_INSTRUCTION_VFETCH_0_MUST_BE_ONE_SIZE; + unsigned int dst_gpr_am : SQ_INSTRUCTION_VFETCH_0_DST_GPR_AM_SIZE; + unsigned int dst_gpr : SQ_INSTRUCTION_VFETCH_0_DST_GPR_SIZE; + unsigned int src_gpr_am : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_AM_SIZE; + unsigned int src_gpr : SQ_INSTRUCTION_VFETCH_0_SRC_GPR_SIZE; + unsigned int opcode : SQ_INSTRUCTION_VFETCH_0_OPCODE_SIZE; + } sq_instruction_vfetch_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_vfetch_0_t f; +} sq_instruction_vfetch_0_u; + + +/* + * SQ_INSTRUCTION_VFETCH_1 struct + */ + +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE 3 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE 3 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE 3 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE 3 +#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE 1 +#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE 6 +#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE 7 +#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE 1 + +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT 0 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT 3 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT 6 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT 9 +#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT 12 +#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT 13 +#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT 14 +#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT 16 +#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT 23 +#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT 31 + +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK 0x00000007 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK 0x00000038 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK 0x000001c0 +#define SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK 0x00000e00 +#define SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK 0x00001000 +#define SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK 0x00002000 +#define SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK 0x00004000 +#define SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK 0x003f0000 +#define SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK 0x3f800000 +#define SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK 0x80000000 + +#define SQ_INSTRUCTION_VFETCH_1_MASK \ + (SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK | \ + SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK | \ + SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK | \ + SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK | \ + SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK | \ + SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK | \ + SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK | \ + SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK | \ + SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK | \ + SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) + +#define SQ_INSTRUCTION_VFETCH_1(dst_sel_x, dst_sel_y, dst_sel_z, dst_sel_w, format_comp_all, num_format_all, signed_rf_mode_all, data_format, exp_adjust_all, pred_select) \ + ((dst_sel_x << SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT) | \ + (dst_sel_y << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT) | \ + (dst_sel_z << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT) | \ + (dst_sel_w << SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT) | \ + (format_comp_all << SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT) | \ + (num_format_all << SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT) | \ + (signed_rf_mode_all << SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT) | \ + (data_format << SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT) | \ + (exp_adjust_all << SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT) | \ + (pred_select << SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT)) + +#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_X(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_Y(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_Z(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_DST_SEL_W(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK) >> SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_FORMAT_COMP_ALL(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_NUM_FORMAT_ALL(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_SIGNED_RF_MODE_ALL(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_DATA_FORMAT(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK) >> SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_EXP_ADJUST_ALL(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK) >> SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_GET_PRED_SELECT(sq_instruction_vfetch_1) \ + ((sq_instruction_vfetch_1 & SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) >> SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT) + +#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_X(sq_instruction_vfetch_1_reg, dst_sel_x) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_MASK) | (dst_sel_x << SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_Y(sq_instruction_vfetch_1_reg, dst_sel_y) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_MASK) | (dst_sel_y << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_Z(sq_instruction_vfetch_1_reg, dst_sel_z) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_MASK) | (dst_sel_z << SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_DST_SEL_W(sq_instruction_vfetch_1_reg, dst_sel_w) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_MASK) | (dst_sel_w << SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_FORMAT_COMP_ALL(sq_instruction_vfetch_1_reg, format_comp_all) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_MASK) | (format_comp_all << SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_NUM_FORMAT_ALL(sq_instruction_vfetch_1_reg, num_format_all) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_MASK) | (num_format_all << SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_SIGNED_RF_MODE_ALL(sq_instruction_vfetch_1_reg, signed_rf_mode_all) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_MASK) | (signed_rf_mode_all << SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_DATA_FORMAT(sq_instruction_vfetch_1_reg, data_format) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_MASK) | (data_format << SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_EXP_ADJUST_ALL(sq_instruction_vfetch_1_reg, exp_adjust_all) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_MASK) | (exp_adjust_all << SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SHIFT) +#define SQ_INSTRUCTION_VFETCH_1_SET_PRED_SELECT(sq_instruction_vfetch_1_reg, pred_select) \ + sq_instruction_vfetch_1_reg = (sq_instruction_vfetch_1_reg & ~SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_MASK) | (pred_select << SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_1_t { + unsigned int dst_sel_x : SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE; + unsigned int dst_sel_y : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE; + unsigned int dst_sel_z : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE; + unsigned int dst_sel_w : SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE; + unsigned int format_comp_all : SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE; + unsigned int num_format_all : SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE; + unsigned int signed_rf_mode_all : SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE; + unsigned int : 1; + unsigned int data_format : SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE; + unsigned int : 1; + unsigned int exp_adjust_all : SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE; + unsigned int : 1; + unsigned int pred_select : SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE; + } sq_instruction_vfetch_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_1_t { + unsigned int pred_select : SQ_INSTRUCTION_VFETCH_1_PRED_SELECT_SIZE; + unsigned int : 1; + unsigned int exp_adjust_all : SQ_INSTRUCTION_VFETCH_1_EXP_ADJUST_ALL_SIZE; + unsigned int : 1; + unsigned int data_format : SQ_INSTRUCTION_VFETCH_1_DATA_FORMAT_SIZE; + unsigned int : 1; + unsigned int signed_rf_mode_all : SQ_INSTRUCTION_VFETCH_1_SIGNED_RF_MODE_ALL_SIZE; + unsigned int num_format_all : SQ_INSTRUCTION_VFETCH_1_NUM_FORMAT_ALL_SIZE; + unsigned int format_comp_all : SQ_INSTRUCTION_VFETCH_1_FORMAT_COMP_ALL_SIZE; + unsigned int dst_sel_w : SQ_INSTRUCTION_VFETCH_1_DST_SEL_W_SIZE; + unsigned int dst_sel_z : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Z_SIZE; + unsigned int dst_sel_y : SQ_INSTRUCTION_VFETCH_1_DST_SEL_Y_SIZE; + unsigned int dst_sel_x : SQ_INSTRUCTION_VFETCH_1_DST_SEL_X_SIZE; + } sq_instruction_vfetch_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_vfetch_1_t f; +} sq_instruction_vfetch_1_u; + + +/* + * SQ_INSTRUCTION_VFETCH_2 struct + */ + +#define SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE 8 +#define SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE 8 +#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE 1 + +#define SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT 0 +#define SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT 16 +#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT 31 + +#define SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK 0x000000ff +#define SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK 0x00ff0000 +#define SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK 0x80000000 + +#define SQ_INSTRUCTION_VFETCH_2_MASK \ + (SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK | \ + SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK | \ + SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) + +#define SQ_INSTRUCTION_VFETCH_2(stride, offset, pred_condition) \ + ((stride << SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT) | \ + (offset << SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT) | \ + (pred_condition << SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT)) + +#define SQ_INSTRUCTION_VFETCH_2_GET_STRIDE(sq_instruction_vfetch_2) \ + ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK) >> SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_2_GET_OFFSET(sq_instruction_vfetch_2) \ + ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK) >> SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT) +#define SQ_INSTRUCTION_VFETCH_2_GET_PRED_CONDITION(sq_instruction_vfetch_2) \ + ((sq_instruction_vfetch_2 & SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) >> SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT) + +#define SQ_INSTRUCTION_VFETCH_2_SET_STRIDE(sq_instruction_vfetch_2_reg, stride) \ + sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_STRIDE_MASK) | (stride << SQ_INSTRUCTION_VFETCH_2_STRIDE_SHIFT) +#define SQ_INSTRUCTION_VFETCH_2_SET_OFFSET(sq_instruction_vfetch_2_reg, offset) \ + sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_OFFSET_MASK) | (offset << SQ_INSTRUCTION_VFETCH_2_OFFSET_SHIFT) +#define SQ_INSTRUCTION_VFETCH_2_SET_PRED_CONDITION(sq_instruction_vfetch_2_reg, pred_condition) \ + sq_instruction_vfetch_2_reg = (sq_instruction_vfetch_2_reg & ~SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_MASK) | (pred_condition << SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_2_t { + unsigned int stride : SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE; + unsigned int : 8; + unsigned int offset : SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE; + unsigned int : 7; + unsigned int pred_condition : SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE; + } sq_instruction_vfetch_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_instruction_vfetch_2_t { + unsigned int pred_condition : SQ_INSTRUCTION_VFETCH_2_PRED_CONDITION_SIZE; + unsigned int : 7; + unsigned int offset : SQ_INSTRUCTION_VFETCH_2_OFFSET_SIZE; + unsigned int : 8; + unsigned int stride : SQ_INSTRUCTION_VFETCH_2_STRIDE_SIZE; + } sq_instruction_vfetch_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_instruction_vfetch_2_t f; +} sq_instruction_vfetch_2_u; + + +/* + * SQ_CONSTANT_0 struct + */ + +#define SQ_CONSTANT_0_RED_SIZE 32 + +#define SQ_CONSTANT_0_RED_SHIFT 0 + +#define SQ_CONSTANT_0_RED_MASK 0xffffffff + +#define SQ_CONSTANT_0_MASK \ + (SQ_CONSTANT_0_RED_MASK) + +#define SQ_CONSTANT_0(red) \ + ((red << SQ_CONSTANT_0_RED_SHIFT)) + +#define SQ_CONSTANT_0_GET_RED(sq_constant_0) \ + ((sq_constant_0 & SQ_CONSTANT_0_RED_MASK) >> SQ_CONSTANT_0_RED_SHIFT) + +#define SQ_CONSTANT_0_SET_RED(sq_constant_0_reg, red) \ + sq_constant_0_reg = (sq_constant_0_reg & ~SQ_CONSTANT_0_RED_MASK) | (red << SQ_CONSTANT_0_RED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_0_t { + unsigned int red : SQ_CONSTANT_0_RED_SIZE; + } sq_constant_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_0_t { + unsigned int red : SQ_CONSTANT_0_RED_SIZE; + } sq_constant_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_0_t f; +} sq_constant_0_u; + + +/* + * SQ_CONSTANT_1 struct + */ + +#define SQ_CONSTANT_1_GREEN_SIZE 32 + +#define SQ_CONSTANT_1_GREEN_SHIFT 0 + +#define SQ_CONSTANT_1_GREEN_MASK 0xffffffff + +#define SQ_CONSTANT_1_MASK \ + (SQ_CONSTANT_1_GREEN_MASK) + +#define SQ_CONSTANT_1(green) \ + ((green << SQ_CONSTANT_1_GREEN_SHIFT)) + +#define SQ_CONSTANT_1_GET_GREEN(sq_constant_1) \ + ((sq_constant_1 & SQ_CONSTANT_1_GREEN_MASK) >> SQ_CONSTANT_1_GREEN_SHIFT) + +#define SQ_CONSTANT_1_SET_GREEN(sq_constant_1_reg, green) \ + sq_constant_1_reg = (sq_constant_1_reg & ~SQ_CONSTANT_1_GREEN_MASK) | (green << SQ_CONSTANT_1_GREEN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_1_t { + unsigned int green : SQ_CONSTANT_1_GREEN_SIZE; + } sq_constant_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_1_t { + unsigned int green : SQ_CONSTANT_1_GREEN_SIZE; + } sq_constant_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_1_t f; +} sq_constant_1_u; + + +/* + * SQ_CONSTANT_2 struct + */ + +#define SQ_CONSTANT_2_BLUE_SIZE 32 + +#define SQ_CONSTANT_2_BLUE_SHIFT 0 + +#define SQ_CONSTANT_2_BLUE_MASK 0xffffffff + +#define SQ_CONSTANT_2_MASK \ + (SQ_CONSTANT_2_BLUE_MASK) + +#define SQ_CONSTANT_2(blue) \ + ((blue << SQ_CONSTANT_2_BLUE_SHIFT)) + +#define SQ_CONSTANT_2_GET_BLUE(sq_constant_2) \ + ((sq_constant_2 & SQ_CONSTANT_2_BLUE_MASK) >> SQ_CONSTANT_2_BLUE_SHIFT) + +#define SQ_CONSTANT_2_SET_BLUE(sq_constant_2_reg, blue) \ + sq_constant_2_reg = (sq_constant_2_reg & ~SQ_CONSTANT_2_BLUE_MASK) | (blue << SQ_CONSTANT_2_BLUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_2_t { + unsigned int blue : SQ_CONSTANT_2_BLUE_SIZE; + } sq_constant_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_2_t { + unsigned int blue : SQ_CONSTANT_2_BLUE_SIZE; + } sq_constant_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_2_t f; +} sq_constant_2_u; + + +/* + * SQ_CONSTANT_3 struct + */ + +#define SQ_CONSTANT_3_ALPHA_SIZE 32 + +#define SQ_CONSTANT_3_ALPHA_SHIFT 0 + +#define SQ_CONSTANT_3_ALPHA_MASK 0xffffffff + +#define SQ_CONSTANT_3_MASK \ + (SQ_CONSTANT_3_ALPHA_MASK) + +#define SQ_CONSTANT_3(alpha) \ + ((alpha << SQ_CONSTANT_3_ALPHA_SHIFT)) + +#define SQ_CONSTANT_3_GET_ALPHA(sq_constant_3) \ + ((sq_constant_3 & SQ_CONSTANT_3_ALPHA_MASK) >> SQ_CONSTANT_3_ALPHA_SHIFT) + +#define SQ_CONSTANT_3_SET_ALPHA(sq_constant_3_reg, alpha) \ + sq_constant_3_reg = (sq_constant_3_reg & ~SQ_CONSTANT_3_ALPHA_MASK) | (alpha << SQ_CONSTANT_3_ALPHA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_3_t { + unsigned int alpha : SQ_CONSTANT_3_ALPHA_SIZE; + } sq_constant_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_3_t { + unsigned int alpha : SQ_CONSTANT_3_ALPHA_SIZE; + } sq_constant_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_3_t f; +} sq_constant_3_u; + + +/* + * SQ_FETCH_0 struct + */ + +#define SQ_FETCH_0_VALUE_SIZE 32 + +#define SQ_FETCH_0_VALUE_SHIFT 0 + +#define SQ_FETCH_0_VALUE_MASK 0xffffffff + +#define SQ_FETCH_0_MASK \ + (SQ_FETCH_0_VALUE_MASK) + +#define SQ_FETCH_0(value) \ + ((value << SQ_FETCH_0_VALUE_SHIFT)) + +#define SQ_FETCH_0_GET_VALUE(sq_fetch_0) \ + ((sq_fetch_0 & SQ_FETCH_0_VALUE_MASK) >> SQ_FETCH_0_VALUE_SHIFT) + +#define SQ_FETCH_0_SET_VALUE(sq_fetch_0_reg, value) \ + sq_fetch_0_reg = (sq_fetch_0_reg & ~SQ_FETCH_0_VALUE_MASK) | (value << SQ_FETCH_0_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_0_t { + unsigned int value : SQ_FETCH_0_VALUE_SIZE; + } sq_fetch_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_0_t { + unsigned int value : SQ_FETCH_0_VALUE_SIZE; + } sq_fetch_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_0_t f; +} sq_fetch_0_u; + + +/* + * SQ_FETCH_1 struct + */ + +#define SQ_FETCH_1_VALUE_SIZE 32 + +#define SQ_FETCH_1_VALUE_SHIFT 0 + +#define SQ_FETCH_1_VALUE_MASK 0xffffffff + +#define SQ_FETCH_1_MASK \ + (SQ_FETCH_1_VALUE_MASK) + +#define SQ_FETCH_1(value) \ + ((value << SQ_FETCH_1_VALUE_SHIFT)) + +#define SQ_FETCH_1_GET_VALUE(sq_fetch_1) \ + ((sq_fetch_1 & SQ_FETCH_1_VALUE_MASK) >> SQ_FETCH_1_VALUE_SHIFT) + +#define SQ_FETCH_1_SET_VALUE(sq_fetch_1_reg, value) \ + sq_fetch_1_reg = (sq_fetch_1_reg & ~SQ_FETCH_1_VALUE_MASK) | (value << SQ_FETCH_1_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_1_t { + unsigned int value : SQ_FETCH_1_VALUE_SIZE; + } sq_fetch_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_1_t { + unsigned int value : SQ_FETCH_1_VALUE_SIZE; + } sq_fetch_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_1_t f; +} sq_fetch_1_u; + + +/* + * SQ_FETCH_2 struct + */ + +#define SQ_FETCH_2_VALUE_SIZE 32 + +#define SQ_FETCH_2_VALUE_SHIFT 0 + +#define SQ_FETCH_2_VALUE_MASK 0xffffffff + +#define SQ_FETCH_2_MASK \ + (SQ_FETCH_2_VALUE_MASK) + +#define SQ_FETCH_2(value) \ + ((value << SQ_FETCH_2_VALUE_SHIFT)) + +#define SQ_FETCH_2_GET_VALUE(sq_fetch_2) \ + ((sq_fetch_2 & SQ_FETCH_2_VALUE_MASK) >> SQ_FETCH_2_VALUE_SHIFT) + +#define SQ_FETCH_2_SET_VALUE(sq_fetch_2_reg, value) \ + sq_fetch_2_reg = (sq_fetch_2_reg & ~SQ_FETCH_2_VALUE_MASK) | (value << SQ_FETCH_2_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_2_t { + unsigned int value : SQ_FETCH_2_VALUE_SIZE; + } sq_fetch_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_2_t { + unsigned int value : SQ_FETCH_2_VALUE_SIZE; + } sq_fetch_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_2_t f; +} sq_fetch_2_u; + + +/* + * SQ_FETCH_3 struct + */ + +#define SQ_FETCH_3_VALUE_SIZE 32 + +#define SQ_FETCH_3_VALUE_SHIFT 0 + +#define SQ_FETCH_3_VALUE_MASK 0xffffffff + +#define SQ_FETCH_3_MASK \ + (SQ_FETCH_3_VALUE_MASK) + +#define SQ_FETCH_3(value) \ + ((value << SQ_FETCH_3_VALUE_SHIFT)) + +#define SQ_FETCH_3_GET_VALUE(sq_fetch_3) \ + ((sq_fetch_3 & SQ_FETCH_3_VALUE_MASK) >> SQ_FETCH_3_VALUE_SHIFT) + +#define SQ_FETCH_3_SET_VALUE(sq_fetch_3_reg, value) \ + sq_fetch_3_reg = (sq_fetch_3_reg & ~SQ_FETCH_3_VALUE_MASK) | (value << SQ_FETCH_3_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_3_t { + unsigned int value : SQ_FETCH_3_VALUE_SIZE; + } sq_fetch_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_3_t { + unsigned int value : SQ_FETCH_3_VALUE_SIZE; + } sq_fetch_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_3_t f; +} sq_fetch_3_u; + + +/* + * SQ_FETCH_4 struct + */ + +#define SQ_FETCH_4_VALUE_SIZE 32 + +#define SQ_FETCH_4_VALUE_SHIFT 0 + +#define SQ_FETCH_4_VALUE_MASK 0xffffffff + +#define SQ_FETCH_4_MASK \ + (SQ_FETCH_4_VALUE_MASK) + +#define SQ_FETCH_4(value) \ + ((value << SQ_FETCH_4_VALUE_SHIFT)) + +#define SQ_FETCH_4_GET_VALUE(sq_fetch_4) \ + ((sq_fetch_4 & SQ_FETCH_4_VALUE_MASK) >> SQ_FETCH_4_VALUE_SHIFT) + +#define SQ_FETCH_4_SET_VALUE(sq_fetch_4_reg, value) \ + sq_fetch_4_reg = (sq_fetch_4_reg & ~SQ_FETCH_4_VALUE_MASK) | (value << SQ_FETCH_4_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_4_t { + unsigned int value : SQ_FETCH_4_VALUE_SIZE; + } sq_fetch_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_4_t { + unsigned int value : SQ_FETCH_4_VALUE_SIZE; + } sq_fetch_4_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_4_t f; +} sq_fetch_4_u; + + +/* + * SQ_FETCH_5 struct + */ + +#define SQ_FETCH_5_VALUE_SIZE 32 + +#define SQ_FETCH_5_VALUE_SHIFT 0 + +#define SQ_FETCH_5_VALUE_MASK 0xffffffff + +#define SQ_FETCH_5_MASK \ + (SQ_FETCH_5_VALUE_MASK) + +#define SQ_FETCH_5(value) \ + ((value << SQ_FETCH_5_VALUE_SHIFT)) + +#define SQ_FETCH_5_GET_VALUE(sq_fetch_5) \ + ((sq_fetch_5 & SQ_FETCH_5_VALUE_MASK) >> SQ_FETCH_5_VALUE_SHIFT) + +#define SQ_FETCH_5_SET_VALUE(sq_fetch_5_reg, value) \ + sq_fetch_5_reg = (sq_fetch_5_reg & ~SQ_FETCH_5_VALUE_MASK) | (value << SQ_FETCH_5_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_5_t { + unsigned int value : SQ_FETCH_5_VALUE_SIZE; + } sq_fetch_5_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_5_t { + unsigned int value : SQ_FETCH_5_VALUE_SIZE; + } sq_fetch_5_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_5_t f; +} sq_fetch_5_u; + + +/* + * SQ_CONSTANT_VFETCH_0 struct + */ + +#define SQ_CONSTANT_VFETCH_0_TYPE_SIZE 1 +#define SQ_CONSTANT_VFETCH_0_STATE_SIZE 1 +#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE 30 + +#define SQ_CONSTANT_VFETCH_0_TYPE_SHIFT 0 +#define SQ_CONSTANT_VFETCH_0_STATE_SHIFT 1 +#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT 2 + +#define SQ_CONSTANT_VFETCH_0_TYPE_MASK 0x00000001 +#define SQ_CONSTANT_VFETCH_0_STATE_MASK 0x00000002 +#define SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK 0xfffffffc + +#define SQ_CONSTANT_VFETCH_0_MASK \ + (SQ_CONSTANT_VFETCH_0_TYPE_MASK | \ + SQ_CONSTANT_VFETCH_0_STATE_MASK | \ + SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) + +#define SQ_CONSTANT_VFETCH_0(type, state, base_address) \ + ((type << SQ_CONSTANT_VFETCH_0_TYPE_SHIFT) | \ + (state << SQ_CONSTANT_VFETCH_0_STATE_SHIFT) | \ + (base_address << SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT)) + +#define SQ_CONSTANT_VFETCH_0_GET_TYPE(sq_constant_vfetch_0) \ + ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_TYPE_MASK) >> SQ_CONSTANT_VFETCH_0_TYPE_SHIFT) +#define SQ_CONSTANT_VFETCH_0_GET_STATE(sq_constant_vfetch_0) \ + ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_STATE_MASK) >> SQ_CONSTANT_VFETCH_0_STATE_SHIFT) +#define SQ_CONSTANT_VFETCH_0_GET_BASE_ADDRESS(sq_constant_vfetch_0) \ + ((sq_constant_vfetch_0 & SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) >> SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT) + +#define SQ_CONSTANT_VFETCH_0_SET_TYPE(sq_constant_vfetch_0_reg, type) \ + sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_TYPE_MASK) | (type << SQ_CONSTANT_VFETCH_0_TYPE_SHIFT) +#define SQ_CONSTANT_VFETCH_0_SET_STATE(sq_constant_vfetch_0_reg, state) \ + sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_STATE_MASK) | (state << SQ_CONSTANT_VFETCH_0_STATE_SHIFT) +#define SQ_CONSTANT_VFETCH_0_SET_BASE_ADDRESS(sq_constant_vfetch_0_reg, base_address) \ + sq_constant_vfetch_0_reg = (sq_constant_vfetch_0_reg & ~SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_MASK) | (base_address << SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_vfetch_0_t { + unsigned int type : SQ_CONSTANT_VFETCH_0_TYPE_SIZE; + unsigned int state : SQ_CONSTANT_VFETCH_0_STATE_SIZE; + unsigned int base_address : SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE; + } sq_constant_vfetch_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_vfetch_0_t { + unsigned int base_address : SQ_CONSTANT_VFETCH_0_BASE_ADDRESS_SIZE; + unsigned int state : SQ_CONSTANT_VFETCH_0_STATE_SIZE; + unsigned int type : SQ_CONSTANT_VFETCH_0_TYPE_SIZE; + } sq_constant_vfetch_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_vfetch_0_t f; +} sq_constant_vfetch_0_u; + + +/* + * SQ_CONSTANT_VFETCH_1 struct + */ + +#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE 2 +#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE 30 + +#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT 0 +#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT 2 + +#define SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK 0x00000003 +#define SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK 0xfffffffc + +#define SQ_CONSTANT_VFETCH_1_MASK \ + (SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK | \ + SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) + +#define SQ_CONSTANT_VFETCH_1(endian_swap, limit_address) \ + ((endian_swap << SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT) | \ + (limit_address << SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT)) + +#define SQ_CONSTANT_VFETCH_1_GET_ENDIAN_SWAP(sq_constant_vfetch_1) \ + ((sq_constant_vfetch_1 & SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK) >> SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT) +#define SQ_CONSTANT_VFETCH_1_GET_LIMIT_ADDRESS(sq_constant_vfetch_1) \ + ((sq_constant_vfetch_1 & SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) >> SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT) + +#define SQ_CONSTANT_VFETCH_1_SET_ENDIAN_SWAP(sq_constant_vfetch_1_reg, endian_swap) \ + sq_constant_vfetch_1_reg = (sq_constant_vfetch_1_reg & ~SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_MASK) | (endian_swap << SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SHIFT) +#define SQ_CONSTANT_VFETCH_1_SET_LIMIT_ADDRESS(sq_constant_vfetch_1_reg, limit_address) \ + sq_constant_vfetch_1_reg = (sq_constant_vfetch_1_reg & ~SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_MASK) | (limit_address << SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_vfetch_1_t { + unsigned int endian_swap : SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE; + unsigned int limit_address : SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE; + } sq_constant_vfetch_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_vfetch_1_t { + unsigned int limit_address : SQ_CONSTANT_VFETCH_1_LIMIT_ADDRESS_SIZE; + unsigned int endian_swap : SQ_CONSTANT_VFETCH_1_ENDIAN_SWAP_SIZE; + } sq_constant_vfetch_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_vfetch_1_t f; +} sq_constant_vfetch_1_u; + + +/* + * SQ_CONSTANT_T2 struct + */ + +#define SQ_CONSTANT_T2_VALUE_SIZE 32 + +#define SQ_CONSTANT_T2_VALUE_SHIFT 0 + +#define SQ_CONSTANT_T2_VALUE_MASK 0xffffffff + +#define SQ_CONSTANT_T2_MASK \ + (SQ_CONSTANT_T2_VALUE_MASK) + +#define SQ_CONSTANT_T2(value) \ + ((value << SQ_CONSTANT_T2_VALUE_SHIFT)) + +#define SQ_CONSTANT_T2_GET_VALUE(sq_constant_t2) \ + ((sq_constant_t2 & SQ_CONSTANT_T2_VALUE_MASK) >> SQ_CONSTANT_T2_VALUE_SHIFT) + +#define SQ_CONSTANT_T2_SET_VALUE(sq_constant_t2_reg, value) \ + sq_constant_t2_reg = (sq_constant_t2_reg & ~SQ_CONSTANT_T2_VALUE_MASK) | (value << SQ_CONSTANT_T2_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_t2_t { + unsigned int value : SQ_CONSTANT_T2_VALUE_SIZE; + } sq_constant_t2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_t2_t { + unsigned int value : SQ_CONSTANT_T2_VALUE_SIZE; + } sq_constant_t2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_t2_t f; +} sq_constant_t2_u; + + +/* + * SQ_CONSTANT_T3 struct + */ + +#define SQ_CONSTANT_T3_VALUE_SIZE 32 + +#define SQ_CONSTANT_T3_VALUE_SHIFT 0 + +#define SQ_CONSTANT_T3_VALUE_MASK 0xffffffff + +#define SQ_CONSTANT_T3_MASK \ + (SQ_CONSTANT_T3_VALUE_MASK) + +#define SQ_CONSTANT_T3(value) \ + ((value << SQ_CONSTANT_T3_VALUE_SHIFT)) + +#define SQ_CONSTANT_T3_GET_VALUE(sq_constant_t3) \ + ((sq_constant_t3 & SQ_CONSTANT_T3_VALUE_MASK) >> SQ_CONSTANT_T3_VALUE_SHIFT) + +#define SQ_CONSTANT_T3_SET_VALUE(sq_constant_t3_reg, value) \ + sq_constant_t3_reg = (sq_constant_t3_reg & ~SQ_CONSTANT_T3_VALUE_MASK) | (value << SQ_CONSTANT_T3_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_t3_t { + unsigned int value : SQ_CONSTANT_T3_VALUE_SIZE; + } sq_constant_t3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_t3_t { + unsigned int value : SQ_CONSTANT_T3_VALUE_SIZE; + } sq_constant_t3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_t3_t f; +} sq_constant_t3_u; + + +/* + * SQ_CF_BOOLEANS struct + */ + +#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE 8 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE 8 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE 8 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE 8 + +#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT 0 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT 8 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT 16 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT 24 + +#define SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK 0x000000ff +#define SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK 0x0000ff00 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK 0x00ff0000 +#define SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK 0xff000000 + +#define SQ_CF_BOOLEANS_MASK \ + (SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK | \ + SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK | \ + SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK | \ + SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) + +#define SQ_CF_BOOLEANS(cf_booleans_0, cf_booleans_1, cf_booleans_2, cf_booleans_3) \ + ((cf_booleans_0 << SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT) | \ + (cf_booleans_1 << SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT) | \ + (cf_booleans_2 << SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT) | \ + (cf_booleans_3 << SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT)) + +#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_0(sq_cf_booleans) \ + ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT) +#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_1(sq_cf_booleans) \ + ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT) +#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_2(sq_cf_booleans) \ + ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT) +#define SQ_CF_BOOLEANS_GET_CF_BOOLEANS_3(sq_cf_booleans) \ + ((sq_cf_booleans & SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) >> SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT) + +#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_0(sq_cf_booleans_reg, cf_booleans_0) \ + sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_0_MASK) | (cf_booleans_0 << SQ_CF_BOOLEANS_CF_BOOLEANS_0_SHIFT) +#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_1(sq_cf_booleans_reg, cf_booleans_1) \ + sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_1_MASK) | (cf_booleans_1 << SQ_CF_BOOLEANS_CF_BOOLEANS_1_SHIFT) +#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_2(sq_cf_booleans_reg, cf_booleans_2) \ + sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_2_MASK) | (cf_booleans_2 << SQ_CF_BOOLEANS_CF_BOOLEANS_2_SHIFT) +#define SQ_CF_BOOLEANS_SET_CF_BOOLEANS_3(sq_cf_booleans_reg, cf_booleans_3) \ + sq_cf_booleans_reg = (sq_cf_booleans_reg & ~SQ_CF_BOOLEANS_CF_BOOLEANS_3_MASK) | (cf_booleans_3 << SQ_CF_BOOLEANS_CF_BOOLEANS_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_booleans_t { + unsigned int cf_booleans_0 : SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE; + unsigned int cf_booleans_1 : SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE; + unsigned int cf_booleans_2 : SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE; + unsigned int cf_booleans_3 : SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE; + } sq_cf_booleans_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_booleans_t { + unsigned int cf_booleans_3 : SQ_CF_BOOLEANS_CF_BOOLEANS_3_SIZE; + unsigned int cf_booleans_2 : SQ_CF_BOOLEANS_CF_BOOLEANS_2_SIZE; + unsigned int cf_booleans_1 : SQ_CF_BOOLEANS_CF_BOOLEANS_1_SIZE; + unsigned int cf_booleans_0 : SQ_CF_BOOLEANS_CF_BOOLEANS_0_SIZE; + } sq_cf_booleans_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_booleans_t f; +} sq_cf_booleans_u; + + +/* + * SQ_CF_LOOP struct + */ + +#define SQ_CF_LOOP_CF_LOOP_COUNT_SIZE 8 +#define SQ_CF_LOOP_CF_LOOP_START_SIZE 8 +#define SQ_CF_LOOP_CF_LOOP_STEP_SIZE 8 + +#define SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT 0 +#define SQ_CF_LOOP_CF_LOOP_START_SHIFT 8 +#define SQ_CF_LOOP_CF_LOOP_STEP_SHIFT 16 + +#define SQ_CF_LOOP_CF_LOOP_COUNT_MASK 0x000000ff +#define SQ_CF_LOOP_CF_LOOP_START_MASK 0x0000ff00 +#define SQ_CF_LOOP_CF_LOOP_STEP_MASK 0x00ff0000 + +#define SQ_CF_LOOP_MASK \ + (SQ_CF_LOOP_CF_LOOP_COUNT_MASK | \ + SQ_CF_LOOP_CF_LOOP_START_MASK | \ + SQ_CF_LOOP_CF_LOOP_STEP_MASK) + +#define SQ_CF_LOOP(cf_loop_count, cf_loop_start, cf_loop_step) \ + ((cf_loop_count << SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT) | \ + (cf_loop_start << SQ_CF_LOOP_CF_LOOP_START_SHIFT) | \ + (cf_loop_step << SQ_CF_LOOP_CF_LOOP_STEP_SHIFT)) + +#define SQ_CF_LOOP_GET_CF_LOOP_COUNT(sq_cf_loop) \ + ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_COUNT_MASK) >> SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT) +#define SQ_CF_LOOP_GET_CF_LOOP_START(sq_cf_loop) \ + ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_START_MASK) >> SQ_CF_LOOP_CF_LOOP_START_SHIFT) +#define SQ_CF_LOOP_GET_CF_LOOP_STEP(sq_cf_loop) \ + ((sq_cf_loop & SQ_CF_LOOP_CF_LOOP_STEP_MASK) >> SQ_CF_LOOP_CF_LOOP_STEP_SHIFT) + +#define SQ_CF_LOOP_SET_CF_LOOP_COUNT(sq_cf_loop_reg, cf_loop_count) \ + sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_COUNT_MASK) | (cf_loop_count << SQ_CF_LOOP_CF_LOOP_COUNT_SHIFT) +#define SQ_CF_LOOP_SET_CF_LOOP_START(sq_cf_loop_reg, cf_loop_start) \ + sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_START_MASK) | (cf_loop_start << SQ_CF_LOOP_CF_LOOP_START_SHIFT) +#define SQ_CF_LOOP_SET_CF_LOOP_STEP(sq_cf_loop_reg, cf_loop_step) \ + sq_cf_loop_reg = (sq_cf_loop_reg & ~SQ_CF_LOOP_CF_LOOP_STEP_MASK) | (cf_loop_step << SQ_CF_LOOP_CF_LOOP_STEP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_loop_t { + unsigned int cf_loop_count : SQ_CF_LOOP_CF_LOOP_COUNT_SIZE; + unsigned int cf_loop_start : SQ_CF_LOOP_CF_LOOP_START_SIZE; + unsigned int cf_loop_step : SQ_CF_LOOP_CF_LOOP_STEP_SIZE; + unsigned int : 8; + } sq_cf_loop_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_loop_t { + unsigned int : 8; + unsigned int cf_loop_step : SQ_CF_LOOP_CF_LOOP_STEP_SIZE; + unsigned int cf_loop_start : SQ_CF_LOOP_CF_LOOP_START_SIZE; + unsigned int cf_loop_count : SQ_CF_LOOP_CF_LOOP_COUNT_SIZE; + } sq_cf_loop_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_loop_t f; +} sq_cf_loop_u; + + +/* + * SQ_CONSTANT_RT_0 struct + */ + +#define SQ_CONSTANT_RT_0_RED_SIZE 32 + +#define SQ_CONSTANT_RT_0_RED_SHIFT 0 + +#define SQ_CONSTANT_RT_0_RED_MASK 0xffffffff + +#define SQ_CONSTANT_RT_0_MASK \ + (SQ_CONSTANT_RT_0_RED_MASK) + +#define SQ_CONSTANT_RT_0(red) \ + ((red << SQ_CONSTANT_RT_0_RED_SHIFT)) + +#define SQ_CONSTANT_RT_0_GET_RED(sq_constant_rt_0) \ + ((sq_constant_rt_0 & SQ_CONSTANT_RT_0_RED_MASK) >> SQ_CONSTANT_RT_0_RED_SHIFT) + +#define SQ_CONSTANT_RT_0_SET_RED(sq_constant_rt_0_reg, red) \ + sq_constant_rt_0_reg = (sq_constant_rt_0_reg & ~SQ_CONSTANT_RT_0_RED_MASK) | (red << SQ_CONSTANT_RT_0_RED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_rt_0_t { + unsigned int red : SQ_CONSTANT_RT_0_RED_SIZE; + } sq_constant_rt_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_rt_0_t { + unsigned int red : SQ_CONSTANT_RT_0_RED_SIZE; + } sq_constant_rt_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_rt_0_t f; +} sq_constant_rt_0_u; + + +/* + * SQ_CONSTANT_RT_1 struct + */ + +#define SQ_CONSTANT_RT_1_GREEN_SIZE 32 + +#define SQ_CONSTANT_RT_1_GREEN_SHIFT 0 + +#define SQ_CONSTANT_RT_1_GREEN_MASK 0xffffffff + +#define SQ_CONSTANT_RT_1_MASK \ + (SQ_CONSTANT_RT_1_GREEN_MASK) + +#define SQ_CONSTANT_RT_1(green) \ + ((green << SQ_CONSTANT_RT_1_GREEN_SHIFT)) + +#define SQ_CONSTANT_RT_1_GET_GREEN(sq_constant_rt_1) \ + ((sq_constant_rt_1 & SQ_CONSTANT_RT_1_GREEN_MASK) >> SQ_CONSTANT_RT_1_GREEN_SHIFT) + +#define SQ_CONSTANT_RT_1_SET_GREEN(sq_constant_rt_1_reg, green) \ + sq_constant_rt_1_reg = (sq_constant_rt_1_reg & ~SQ_CONSTANT_RT_1_GREEN_MASK) | (green << SQ_CONSTANT_RT_1_GREEN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_rt_1_t { + unsigned int green : SQ_CONSTANT_RT_1_GREEN_SIZE; + } sq_constant_rt_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_rt_1_t { + unsigned int green : SQ_CONSTANT_RT_1_GREEN_SIZE; + } sq_constant_rt_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_rt_1_t f; +} sq_constant_rt_1_u; + + +/* + * SQ_CONSTANT_RT_2 struct + */ + +#define SQ_CONSTANT_RT_2_BLUE_SIZE 32 + +#define SQ_CONSTANT_RT_2_BLUE_SHIFT 0 + +#define SQ_CONSTANT_RT_2_BLUE_MASK 0xffffffff + +#define SQ_CONSTANT_RT_2_MASK \ + (SQ_CONSTANT_RT_2_BLUE_MASK) + +#define SQ_CONSTANT_RT_2(blue) \ + ((blue << SQ_CONSTANT_RT_2_BLUE_SHIFT)) + +#define SQ_CONSTANT_RT_2_GET_BLUE(sq_constant_rt_2) \ + ((sq_constant_rt_2 & SQ_CONSTANT_RT_2_BLUE_MASK) >> SQ_CONSTANT_RT_2_BLUE_SHIFT) + +#define SQ_CONSTANT_RT_2_SET_BLUE(sq_constant_rt_2_reg, blue) \ + sq_constant_rt_2_reg = (sq_constant_rt_2_reg & ~SQ_CONSTANT_RT_2_BLUE_MASK) | (blue << SQ_CONSTANT_RT_2_BLUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_rt_2_t { + unsigned int blue : SQ_CONSTANT_RT_2_BLUE_SIZE; + } sq_constant_rt_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_rt_2_t { + unsigned int blue : SQ_CONSTANT_RT_2_BLUE_SIZE; + } sq_constant_rt_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_rt_2_t f; +} sq_constant_rt_2_u; + + +/* + * SQ_CONSTANT_RT_3 struct + */ + +#define SQ_CONSTANT_RT_3_ALPHA_SIZE 32 + +#define SQ_CONSTANT_RT_3_ALPHA_SHIFT 0 + +#define SQ_CONSTANT_RT_3_ALPHA_MASK 0xffffffff + +#define SQ_CONSTANT_RT_3_MASK \ + (SQ_CONSTANT_RT_3_ALPHA_MASK) + +#define SQ_CONSTANT_RT_3(alpha) \ + ((alpha << SQ_CONSTANT_RT_3_ALPHA_SHIFT)) + +#define SQ_CONSTANT_RT_3_GET_ALPHA(sq_constant_rt_3) \ + ((sq_constant_rt_3 & SQ_CONSTANT_RT_3_ALPHA_MASK) >> SQ_CONSTANT_RT_3_ALPHA_SHIFT) + +#define SQ_CONSTANT_RT_3_SET_ALPHA(sq_constant_rt_3_reg, alpha) \ + sq_constant_rt_3_reg = (sq_constant_rt_3_reg & ~SQ_CONSTANT_RT_3_ALPHA_MASK) | (alpha << SQ_CONSTANT_RT_3_ALPHA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_constant_rt_3_t { + unsigned int alpha : SQ_CONSTANT_RT_3_ALPHA_SIZE; + } sq_constant_rt_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_constant_rt_3_t { + unsigned int alpha : SQ_CONSTANT_RT_3_ALPHA_SIZE; + } sq_constant_rt_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_constant_rt_3_t f; +} sq_constant_rt_3_u; + + +/* + * SQ_FETCH_RT_0 struct + */ + +#define SQ_FETCH_RT_0_VALUE_SIZE 32 + +#define SQ_FETCH_RT_0_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_0_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_0_MASK \ + (SQ_FETCH_RT_0_VALUE_MASK) + +#define SQ_FETCH_RT_0(value) \ + ((value << SQ_FETCH_RT_0_VALUE_SHIFT)) + +#define SQ_FETCH_RT_0_GET_VALUE(sq_fetch_rt_0) \ + ((sq_fetch_rt_0 & SQ_FETCH_RT_0_VALUE_MASK) >> SQ_FETCH_RT_0_VALUE_SHIFT) + +#define SQ_FETCH_RT_0_SET_VALUE(sq_fetch_rt_0_reg, value) \ + sq_fetch_rt_0_reg = (sq_fetch_rt_0_reg & ~SQ_FETCH_RT_0_VALUE_MASK) | (value << SQ_FETCH_RT_0_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_0_t { + unsigned int value : SQ_FETCH_RT_0_VALUE_SIZE; + } sq_fetch_rt_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_0_t { + unsigned int value : SQ_FETCH_RT_0_VALUE_SIZE; + } sq_fetch_rt_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_0_t f; +} sq_fetch_rt_0_u; + + +/* + * SQ_FETCH_RT_1 struct + */ + +#define SQ_FETCH_RT_1_VALUE_SIZE 32 + +#define SQ_FETCH_RT_1_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_1_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_1_MASK \ + (SQ_FETCH_RT_1_VALUE_MASK) + +#define SQ_FETCH_RT_1(value) \ + ((value << SQ_FETCH_RT_1_VALUE_SHIFT)) + +#define SQ_FETCH_RT_1_GET_VALUE(sq_fetch_rt_1) \ + ((sq_fetch_rt_1 & SQ_FETCH_RT_1_VALUE_MASK) >> SQ_FETCH_RT_1_VALUE_SHIFT) + +#define SQ_FETCH_RT_1_SET_VALUE(sq_fetch_rt_1_reg, value) \ + sq_fetch_rt_1_reg = (sq_fetch_rt_1_reg & ~SQ_FETCH_RT_1_VALUE_MASK) | (value << SQ_FETCH_RT_1_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_1_t { + unsigned int value : SQ_FETCH_RT_1_VALUE_SIZE; + } sq_fetch_rt_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_1_t { + unsigned int value : SQ_FETCH_RT_1_VALUE_SIZE; + } sq_fetch_rt_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_1_t f; +} sq_fetch_rt_1_u; + + +/* + * SQ_FETCH_RT_2 struct + */ + +#define SQ_FETCH_RT_2_VALUE_SIZE 32 + +#define SQ_FETCH_RT_2_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_2_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_2_MASK \ + (SQ_FETCH_RT_2_VALUE_MASK) + +#define SQ_FETCH_RT_2(value) \ + ((value << SQ_FETCH_RT_2_VALUE_SHIFT)) + +#define SQ_FETCH_RT_2_GET_VALUE(sq_fetch_rt_2) \ + ((sq_fetch_rt_2 & SQ_FETCH_RT_2_VALUE_MASK) >> SQ_FETCH_RT_2_VALUE_SHIFT) + +#define SQ_FETCH_RT_2_SET_VALUE(sq_fetch_rt_2_reg, value) \ + sq_fetch_rt_2_reg = (sq_fetch_rt_2_reg & ~SQ_FETCH_RT_2_VALUE_MASK) | (value << SQ_FETCH_RT_2_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_2_t { + unsigned int value : SQ_FETCH_RT_2_VALUE_SIZE; + } sq_fetch_rt_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_2_t { + unsigned int value : SQ_FETCH_RT_2_VALUE_SIZE; + } sq_fetch_rt_2_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_2_t f; +} sq_fetch_rt_2_u; + + +/* + * SQ_FETCH_RT_3 struct + */ + +#define SQ_FETCH_RT_3_VALUE_SIZE 32 + +#define SQ_FETCH_RT_3_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_3_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_3_MASK \ + (SQ_FETCH_RT_3_VALUE_MASK) + +#define SQ_FETCH_RT_3(value) \ + ((value << SQ_FETCH_RT_3_VALUE_SHIFT)) + +#define SQ_FETCH_RT_3_GET_VALUE(sq_fetch_rt_3) \ + ((sq_fetch_rt_3 & SQ_FETCH_RT_3_VALUE_MASK) >> SQ_FETCH_RT_3_VALUE_SHIFT) + +#define SQ_FETCH_RT_3_SET_VALUE(sq_fetch_rt_3_reg, value) \ + sq_fetch_rt_3_reg = (sq_fetch_rt_3_reg & ~SQ_FETCH_RT_3_VALUE_MASK) | (value << SQ_FETCH_RT_3_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_3_t { + unsigned int value : SQ_FETCH_RT_3_VALUE_SIZE; + } sq_fetch_rt_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_3_t { + unsigned int value : SQ_FETCH_RT_3_VALUE_SIZE; + } sq_fetch_rt_3_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_3_t f; +} sq_fetch_rt_3_u; + + +/* + * SQ_FETCH_RT_4 struct + */ + +#define SQ_FETCH_RT_4_VALUE_SIZE 32 + +#define SQ_FETCH_RT_4_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_4_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_4_MASK \ + (SQ_FETCH_RT_4_VALUE_MASK) + +#define SQ_FETCH_RT_4(value) \ + ((value << SQ_FETCH_RT_4_VALUE_SHIFT)) + +#define SQ_FETCH_RT_4_GET_VALUE(sq_fetch_rt_4) \ + ((sq_fetch_rt_4 & SQ_FETCH_RT_4_VALUE_MASK) >> SQ_FETCH_RT_4_VALUE_SHIFT) + +#define SQ_FETCH_RT_4_SET_VALUE(sq_fetch_rt_4_reg, value) \ + sq_fetch_rt_4_reg = (sq_fetch_rt_4_reg & ~SQ_FETCH_RT_4_VALUE_MASK) | (value << SQ_FETCH_RT_4_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_4_t { + unsigned int value : SQ_FETCH_RT_4_VALUE_SIZE; + } sq_fetch_rt_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_4_t { + unsigned int value : SQ_FETCH_RT_4_VALUE_SIZE; + } sq_fetch_rt_4_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_4_t f; +} sq_fetch_rt_4_u; + + +/* + * SQ_FETCH_RT_5 struct + */ + +#define SQ_FETCH_RT_5_VALUE_SIZE 32 + +#define SQ_FETCH_RT_5_VALUE_SHIFT 0 + +#define SQ_FETCH_RT_5_VALUE_MASK 0xffffffff + +#define SQ_FETCH_RT_5_MASK \ + (SQ_FETCH_RT_5_VALUE_MASK) + +#define SQ_FETCH_RT_5(value) \ + ((value << SQ_FETCH_RT_5_VALUE_SHIFT)) + +#define SQ_FETCH_RT_5_GET_VALUE(sq_fetch_rt_5) \ + ((sq_fetch_rt_5 & SQ_FETCH_RT_5_VALUE_MASK) >> SQ_FETCH_RT_5_VALUE_SHIFT) + +#define SQ_FETCH_RT_5_SET_VALUE(sq_fetch_rt_5_reg, value) \ + sq_fetch_rt_5_reg = (sq_fetch_rt_5_reg & ~SQ_FETCH_RT_5_VALUE_MASK) | (value << SQ_FETCH_RT_5_VALUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_fetch_rt_5_t { + unsigned int value : SQ_FETCH_RT_5_VALUE_SIZE; + } sq_fetch_rt_5_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_fetch_rt_5_t { + unsigned int value : SQ_FETCH_RT_5_VALUE_SIZE; + } sq_fetch_rt_5_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_fetch_rt_5_t f; +} sq_fetch_rt_5_u; + + +/* + * SQ_CF_RT_BOOLEANS struct + */ + +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE 8 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE 8 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE 8 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE 8 + +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT 0 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT 8 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT 16 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT 24 + +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK 0x000000ff +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK 0x0000ff00 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK 0x00ff0000 +#define SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK 0xff000000 + +#define SQ_CF_RT_BOOLEANS_MASK \ + (SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK | \ + SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK | \ + SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK | \ + SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) + +#define SQ_CF_RT_BOOLEANS(cf_booleans_0, cf_booleans_1, cf_booleans_2, cf_booleans_3) \ + ((cf_booleans_0 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT) | \ + (cf_booleans_1 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT) | \ + (cf_booleans_2 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT) | \ + (cf_booleans_3 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT)) + +#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_0(sq_cf_rt_booleans) \ + ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT) +#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_1(sq_cf_rt_booleans) \ + ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT) +#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_2(sq_cf_rt_booleans) \ + ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT) +#define SQ_CF_RT_BOOLEANS_GET_CF_BOOLEANS_3(sq_cf_rt_booleans) \ + ((sq_cf_rt_booleans & SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) >> SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT) + +#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_0(sq_cf_rt_booleans_reg, cf_booleans_0) \ + sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_MASK) | (cf_booleans_0 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SHIFT) +#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_1(sq_cf_rt_booleans_reg, cf_booleans_1) \ + sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_MASK) | (cf_booleans_1 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SHIFT) +#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_2(sq_cf_rt_booleans_reg, cf_booleans_2) \ + sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_MASK) | (cf_booleans_2 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SHIFT) +#define SQ_CF_RT_BOOLEANS_SET_CF_BOOLEANS_3(sq_cf_rt_booleans_reg, cf_booleans_3) \ + sq_cf_rt_booleans_reg = (sq_cf_rt_booleans_reg & ~SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_MASK) | (cf_booleans_3 << SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_rt_booleans_t { + unsigned int cf_booleans_0 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE; + unsigned int cf_booleans_1 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE; + unsigned int cf_booleans_2 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE; + unsigned int cf_booleans_3 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE; + } sq_cf_rt_booleans_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_rt_booleans_t { + unsigned int cf_booleans_3 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_3_SIZE; + unsigned int cf_booleans_2 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_2_SIZE; + unsigned int cf_booleans_1 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_1_SIZE; + unsigned int cf_booleans_0 : SQ_CF_RT_BOOLEANS_CF_BOOLEANS_0_SIZE; + } sq_cf_rt_booleans_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_rt_booleans_t f; +} sq_cf_rt_booleans_u; + + +/* + * SQ_CF_RT_LOOP struct + */ + +#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE 8 +#define SQ_CF_RT_LOOP_CF_LOOP_START_SIZE 8 +#define SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE 8 + +#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT 0 +#define SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT 8 +#define SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT 16 + +#define SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK 0x000000ff +#define SQ_CF_RT_LOOP_CF_LOOP_START_MASK 0x0000ff00 +#define SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK 0x00ff0000 + +#define SQ_CF_RT_LOOP_MASK \ + (SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK | \ + SQ_CF_RT_LOOP_CF_LOOP_START_MASK | \ + SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) + +#define SQ_CF_RT_LOOP(cf_loop_count, cf_loop_start, cf_loop_step) \ + ((cf_loop_count << SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT) | \ + (cf_loop_start << SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT) | \ + (cf_loop_step << SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT)) + +#define SQ_CF_RT_LOOP_GET_CF_LOOP_COUNT(sq_cf_rt_loop) \ + ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT) +#define SQ_CF_RT_LOOP_GET_CF_LOOP_START(sq_cf_rt_loop) \ + ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_START_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT) +#define SQ_CF_RT_LOOP_GET_CF_LOOP_STEP(sq_cf_rt_loop) \ + ((sq_cf_rt_loop & SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) >> SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT) + +#define SQ_CF_RT_LOOP_SET_CF_LOOP_COUNT(sq_cf_rt_loop_reg, cf_loop_count) \ + sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_COUNT_MASK) | (cf_loop_count << SQ_CF_RT_LOOP_CF_LOOP_COUNT_SHIFT) +#define SQ_CF_RT_LOOP_SET_CF_LOOP_START(sq_cf_rt_loop_reg, cf_loop_start) \ + sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_START_MASK) | (cf_loop_start << SQ_CF_RT_LOOP_CF_LOOP_START_SHIFT) +#define SQ_CF_RT_LOOP_SET_CF_LOOP_STEP(sq_cf_rt_loop_reg, cf_loop_step) \ + sq_cf_rt_loop_reg = (sq_cf_rt_loop_reg & ~SQ_CF_RT_LOOP_CF_LOOP_STEP_MASK) | (cf_loop_step << SQ_CF_RT_LOOP_CF_LOOP_STEP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_rt_loop_t { + unsigned int cf_loop_count : SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE; + unsigned int cf_loop_start : SQ_CF_RT_LOOP_CF_LOOP_START_SIZE; + unsigned int cf_loop_step : SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE; + unsigned int : 8; + } sq_cf_rt_loop_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_rt_loop_t { + unsigned int : 8; + unsigned int cf_loop_step : SQ_CF_RT_LOOP_CF_LOOP_STEP_SIZE; + unsigned int cf_loop_start : SQ_CF_RT_LOOP_CF_LOOP_START_SIZE; + unsigned int cf_loop_count : SQ_CF_RT_LOOP_CF_LOOP_COUNT_SIZE; + } sq_cf_rt_loop_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_rt_loop_t f; +} sq_cf_rt_loop_u; + + +/* + * SQ_VS_PROGRAM struct + */ + +#define SQ_VS_PROGRAM_BASE_SIZE 12 +#define SQ_VS_PROGRAM_SIZE_SIZE 12 + +#define SQ_VS_PROGRAM_BASE_SHIFT 0 +#define SQ_VS_PROGRAM_SIZE_SHIFT 12 + +#define SQ_VS_PROGRAM_BASE_MASK 0x00000fff +#define SQ_VS_PROGRAM_SIZE_MASK 0x00fff000 + +#define SQ_VS_PROGRAM_MASK \ + (SQ_VS_PROGRAM_BASE_MASK | \ + SQ_VS_PROGRAM_SIZE_MASK) + +#define SQ_VS_PROGRAM(base, size) \ + ((base << SQ_VS_PROGRAM_BASE_SHIFT) | \ + (size << SQ_VS_PROGRAM_SIZE_SHIFT)) + +#define SQ_VS_PROGRAM_GET_BASE(sq_vs_program) \ + ((sq_vs_program & SQ_VS_PROGRAM_BASE_MASK) >> SQ_VS_PROGRAM_BASE_SHIFT) +#define SQ_VS_PROGRAM_GET_SIZE(sq_vs_program) \ + ((sq_vs_program & SQ_VS_PROGRAM_SIZE_MASK) >> SQ_VS_PROGRAM_SIZE_SHIFT) + +#define SQ_VS_PROGRAM_SET_BASE(sq_vs_program_reg, base) \ + sq_vs_program_reg = (sq_vs_program_reg & ~SQ_VS_PROGRAM_BASE_MASK) | (base << SQ_VS_PROGRAM_BASE_SHIFT) +#define SQ_VS_PROGRAM_SET_SIZE(sq_vs_program_reg, size) \ + sq_vs_program_reg = (sq_vs_program_reg & ~SQ_VS_PROGRAM_SIZE_MASK) | (size << SQ_VS_PROGRAM_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_vs_program_t { + unsigned int base : SQ_VS_PROGRAM_BASE_SIZE; + unsigned int size : SQ_VS_PROGRAM_SIZE_SIZE; + unsigned int : 8; + } sq_vs_program_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_vs_program_t { + unsigned int : 8; + unsigned int size : SQ_VS_PROGRAM_SIZE_SIZE; + unsigned int base : SQ_VS_PROGRAM_BASE_SIZE; + } sq_vs_program_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_vs_program_t f; +} sq_vs_program_u; + + +/* + * SQ_PS_PROGRAM struct + */ + +#define SQ_PS_PROGRAM_BASE_SIZE 12 +#define SQ_PS_PROGRAM_SIZE_SIZE 12 + +#define SQ_PS_PROGRAM_BASE_SHIFT 0 +#define SQ_PS_PROGRAM_SIZE_SHIFT 12 + +#define SQ_PS_PROGRAM_BASE_MASK 0x00000fff +#define SQ_PS_PROGRAM_SIZE_MASK 0x00fff000 + +#define SQ_PS_PROGRAM_MASK \ + (SQ_PS_PROGRAM_BASE_MASK | \ + SQ_PS_PROGRAM_SIZE_MASK) + +#define SQ_PS_PROGRAM(base, size) \ + ((base << SQ_PS_PROGRAM_BASE_SHIFT) | \ + (size << SQ_PS_PROGRAM_SIZE_SHIFT)) + +#define SQ_PS_PROGRAM_GET_BASE(sq_ps_program) \ + ((sq_ps_program & SQ_PS_PROGRAM_BASE_MASK) >> SQ_PS_PROGRAM_BASE_SHIFT) +#define SQ_PS_PROGRAM_GET_SIZE(sq_ps_program) \ + ((sq_ps_program & SQ_PS_PROGRAM_SIZE_MASK) >> SQ_PS_PROGRAM_SIZE_SHIFT) + +#define SQ_PS_PROGRAM_SET_BASE(sq_ps_program_reg, base) \ + sq_ps_program_reg = (sq_ps_program_reg & ~SQ_PS_PROGRAM_BASE_MASK) | (base << SQ_PS_PROGRAM_BASE_SHIFT) +#define SQ_PS_PROGRAM_SET_SIZE(sq_ps_program_reg, size) \ + sq_ps_program_reg = (sq_ps_program_reg & ~SQ_PS_PROGRAM_SIZE_MASK) | (size << SQ_PS_PROGRAM_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_ps_program_t { + unsigned int base : SQ_PS_PROGRAM_BASE_SIZE; + unsigned int size : SQ_PS_PROGRAM_SIZE_SIZE; + unsigned int : 8; + } sq_ps_program_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_ps_program_t { + unsigned int : 8; + unsigned int size : SQ_PS_PROGRAM_SIZE_SIZE; + unsigned int base : SQ_PS_PROGRAM_BASE_SIZE; + } sq_ps_program_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_ps_program_t f; +} sq_ps_program_u; + + +/* + * SQ_CF_PROGRAM_SIZE struct + */ + +#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE 11 +#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE 11 + +#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT 0 +#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT 12 + +#define SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK 0x000007ff +#define SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK 0x007ff000 + +#define SQ_CF_PROGRAM_SIZE_MASK \ + (SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK | \ + SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) + +#define SQ_CF_PROGRAM_SIZE(vs_cf_size, ps_cf_size) \ + ((vs_cf_size << SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT) | \ + (ps_cf_size << SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT)) + +#define SQ_CF_PROGRAM_SIZE_GET_VS_CF_SIZE(sq_cf_program_size) \ + ((sq_cf_program_size & SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK) >> SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT) +#define SQ_CF_PROGRAM_SIZE_GET_PS_CF_SIZE(sq_cf_program_size) \ + ((sq_cf_program_size & SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) >> SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT) + +#define SQ_CF_PROGRAM_SIZE_SET_VS_CF_SIZE(sq_cf_program_size_reg, vs_cf_size) \ + sq_cf_program_size_reg = (sq_cf_program_size_reg & ~SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_MASK) | (vs_cf_size << SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SHIFT) +#define SQ_CF_PROGRAM_SIZE_SET_PS_CF_SIZE(sq_cf_program_size_reg, ps_cf_size) \ + sq_cf_program_size_reg = (sq_cf_program_size_reg & ~SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_MASK) | (ps_cf_size << SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_program_size_t { + unsigned int vs_cf_size : SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE; + unsigned int : 1; + unsigned int ps_cf_size : SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE; + unsigned int : 9; + } sq_cf_program_size_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_program_size_t { + unsigned int : 9; + unsigned int ps_cf_size : SQ_CF_PROGRAM_SIZE_PS_CF_SIZE_SIZE; + unsigned int : 1; + unsigned int vs_cf_size : SQ_CF_PROGRAM_SIZE_VS_CF_SIZE_SIZE; + } sq_cf_program_size_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_program_size_t f; +} sq_cf_program_size_u; + + +/* + * SQ_INTERPOLATOR_CNTL struct + */ + +#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE 16 +#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE 16 + +#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT 0 +#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT 16 + +#define SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK 0x0000ffff +#define SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK 0xffff0000 + +#define SQ_INTERPOLATOR_CNTL_MASK \ + (SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK | \ + SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) + +#define SQ_INTERPOLATOR_CNTL(param_shade, sampling_pattern) \ + ((param_shade << SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT) | \ + (sampling_pattern << SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT)) + +#define SQ_INTERPOLATOR_CNTL_GET_PARAM_SHADE(sq_interpolator_cntl) \ + ((sq_interpolator_cntl & SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK) >> SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT) +#define SQ_INTERPOLATOR_CNTL_GET_SAMPLING_PATTERN(sq_interpolator_cntl) \ + ((sq_interpolator_cntl & SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) >> SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT) + +#define SQ_INTERPOLATOR_CNTL_SET_PARAM_SHADE(sq_interpolator_cntl_reg, param_shade) \ + sq_interpolator_cntl_reg = (sq_interpolator_cntl_reg & ~SQ_INTERPOLATOR_CNTL_PARAM_SHADE_MASK) | (param_shade << SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SHIFT) +#define SQ_INTERPOLATOR_CNTL_SET_SAMPLING_PATTERN(sq_interpolator_cntl_reg, sampling_pattern) \ + sq_interpolator_cntl_reg = (sq_interpolator_cntl_reg & ~SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_MASK) | (sampling_pattern << SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_interpolator_cntl_t { + unsigned int param_shade : SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE; + unsigned int sampling_pattern : SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE; + } sq_interpolator_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_interpolator_cntl_t { + unsigned int sampling_pattern : SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN_SIZE; + unsigned int param_shade : SQ_INTERPOLATOR_CNTL_PARAM_SHADE_SIZE; + } sq_interpolator_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_interpolator_cntl_t f; +} sq_interpolator_cntl_u; + + +/* + * SQ_PROGRAM_CNTL struct + */ + +#define SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE 6 +#define SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE 6 +#define SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE 1 +#define SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE 1 +#define SQ_PROGRAM_CNTL_PARAM_GEN_SIZE 1 +#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE 1 +#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE 4 +#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE 3 +#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE 4 +#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE 1 + +#define SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT 0 +#define SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT 8 +#define SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT 16 +#define SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT 17 +#define SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT 18 +#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT 19 +#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT 20 +#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT 24 +#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT 27 +#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT 31 + +#define SQ_PROGRAM_CNTL_VS_NUM_REG_MASK 0x0000003f +#define SQ_PROGRAM_CNTL_PS_NUM_REG_MASK 0x00003f00 +#define SQ_PROGRAM_CNTL_VS_RESOURCE_MASK 0x00010000 +#define SQ_PROGRAM_CNTL_PS_RESOURCE_MASK 0x00020000 +#define SQ_PROGRAM_CNTL_PARAM_GEN_MASK 0x00040000 +#define SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK 0x00080000 +#define SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK 0x00f00000 +#define SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK 0x07000000 +#define SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK 0x78000000 +#define SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK 0x80000000 + +#define SQ_PROGRAM_CNTL_MASK \ + (SQ_PROGRAM_CNTL_VS_NUM_REG_MASK | \ + SQ_PROGRAM_CNTL_PS_NUM_REG_MASK | \ + SQ_PROGRAM_CNTL_VS_RESOURCE_MASK | \ + SQ_PROGRAM_CNTL_PS_RESOURCE_MASK | \ + SQ_PROGRAM_CNTL_PARAM_GEN_MASK | \ + SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK | \ + SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK | \ + SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK | \ + SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK | \ + SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) + +#define SQ_PROGRAM_CNTL(vs_num_reg, ps_num_reg, vs_resource, ps_resource, param_gen, gen_index_pix, vs_export_count, vs_export_mode, ps_export_mode, gen_index_vtx) \ + ((vs_num_reg << SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT) | \ + (ps_num_reg << SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT) | \ + (vs_resource << SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT) | \ + (ps_resource << SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT) | \ + (param_gen << SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT) | \ + (gen_index_pix << SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT) | \ + (vs_export_count << SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT) | \ + (vs_export_mode << SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT) | \ + (ps_export_mode << SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT) | \ + (gen_index_vtx << SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT)) + +#define SQ_PROGRAM_CNTL_GET_VS_NUM_REG(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_NUM_REG_MASK) >> SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT) +#define SQ_PROGRAM_CNTL_GET_PS_NUM_REG(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_NUM_REG_MASK) >> SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT) +#define SQ_PROGRAM_CNTL_GET_VS_RESOURCE(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_RESOURCE_MASK) >> SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT) +#define SQ_PROGRAM_CNTL_GET_PS_RESOURCE(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_RESOURCE_MASK) >> SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT) +#define SQ_PROGRAM_CNTL_GET_PARAM_GEN(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_PARAM_GEN_MASK) >> SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT) +#define SQ_PROGRAM_CNTL_GET_GEN_INDEX_PIX(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK) >> SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT) +#define SQ_PROGRAM_CNTL_GET_VS_EXPORT_COUNT(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK) >> SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT) +#define SQ_PROGRAM_CNTL_GET_VS_EXPORT_MODE(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK) >> SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT) +#define SQ_PROGRAM_CNTL_GET_PS_EXPORT_MODE(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK) >> SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT) +#define SQ_PROGRAM_CNTL_GET_GEN_INDEX_VTX(sq_program_cntl) \ + ((sq_program_cntl & SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) >> SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT) + +#define SQ_PROGRAM_CNTL_SET_VS_NUM_REG(sq_program_cntl_reg, vs_num_reg) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_NUM_REG_MASK) | (vs_num_reg << SQ_PROGRAM_CNTL_VS_NUM_REG_SHIFT) +#define SQ_PROGRAM_CNTL_SET_PS_NUM_REG(sq_program_cntl_reg, ps_num_reg) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_NUM_REG_MASK) | (ps_num_reg << SQ_PROGRAM_CNTL_PS_NUM_REG_SHIFT) +#define SQ_PROGRAM_CNTL_SET_VS_RESOURCE(sq_program_cntl_reg, vs_resource) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_RESOURCE_MASK) | (vs_resource << SQ_PROGRAM_CNTL_VS_RESOURCE_SHIFT) +#define SQ_PROGRAM_CNTL_SET_PS_RESOURCE(sq_program_cntl_reg, ps_resource) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_RESOURCE_MASK) | (ps_resource << SQ_PROGRAM_CNTL_PS_RESOURCE_SHIFT) +#define SQ_PROGRAM_CNTL_SET_PARAM_GEN(sq_program_cntl_reg, param_gen) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PARAM_GEN_MASK) | (param_gen << SQ_PROGRAM_CNTL_PARAM_GEN_SHIFT) +#define SQ_PROGRAM_CNTL_SET_GEN_INDEX_PIX(sq_program_cntl_reg, gen_index_pix) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_GEN_INDEX_PIX_MASK) | (gen_index_pix << SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SHIFT) +#define SQ_PROGRAM_CNTL_SET_VS_EXPORT_COUNT(sq_program_cntl_reg, vs_export_count) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_MASK) | (vs_export_count << SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SHIFT) +#define SQ_PROGRAM_CNTL_SET_VS_EXPORT_MODE(sq_program_cntl_reg, vs_export_mode) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_VS_EXPORT_MODE_MASK) | (vs_export_mode << SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SHIFT) +#define SQ_PROGRAM_CNTL_SET_PS_EXPORT_MODE(sq_program_cntl_reg, ps_export_mode) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_PS_EXPORT_MODE_MASK) | (ps_export_mode << SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SHIFT) +#define SQ_PROGRAM_CNTL_SET_GEN_INDEX_VTX(sq_program_cntl_reg, gen_index_vtx) \ + sq_program_cntl_reg = (sq_program_cntl_reg & ~SQ_PROGRAM_CNTL_GEN_INDEX_VTX_MASK) | (gen_index_vtx << SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_program_cntl_t { + unsigned int vs_num_reg : SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE; + unsigned int : 2; + unsigned int ps_num_reg : SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE; + unsigned int : 2; + unsigned int vs_resource : SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE; + unsigned int ps_resource : SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE; + unsigned int param_gen : SQ_PROGRAM_CNTL_PARAM_GEN_SIZE; + unsigned int gen_index_pix : SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE; + unsigned int vs_export_count : SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE; + unsigned int vs_export_mode : SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE; + unsigned int ps_export_mode : SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE; + unsigned int gen_index_vtx : SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE; + } sq_program_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_program_cntl_t { + unsigned int gen_index_vtx : SQ_PROGRAM_CNTL_GEN_INDEX_VTX_SIZE; + unsigned int ps_export_mode : SQ_PROGRAM_CNTL_PS_EXPORT_MODE_SIZE; + unsigned int vs_export_mode : SQ_PROGRAM_CNTL_VS_EXPORT_MODE_SIZE; + unsigned int vs_export_count : SQ_PROGRAM_CNTL_VS_EXPORT_COUNT_SIZE; + unsigned int gen_index_pix : SQ_PROGRAM_CNTL_GEN_INDEX_PIX_SIZE; + unsigned int param_gen : SQ_PROGRAM_CNTL_PARAM_GEN_SIZE; + unsigned int ps_resource : SQ_PROGRAM_CNTL_PS_RESOURCE_SIZE; + unsigned int vs_resource : SQ_PROGRAM_CNTL_VS_RESOURCE_SIZE; + unsigned int : 2; + unsigned int ps_num_reg : SQ_PROGRAM_CNTL_PS_NUM_REG_SIZE; + unsigned int : 2; + unsigned int vs_num_reg : SQ_PROGRAM_CNTL_VS_NUM_REG_SIZE; + } sq_program_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_program_cntl_t f; +} sq_program_cntl_u; + + +/* + * SQ_WRAPPING_0 struct + */ + +#define SQ_WRAPPING_0_PARAM_WRAP_0_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_1_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_2_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_3_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_4_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_5_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_6_SIZE 4 +#define SQ_WRAPPING_0_PARAM_WRAP_7_SIZE 4 + +#define SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT 0 +#define SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT 4 +#define SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT 8 +#define SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT 12 +#define SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT 16 +#define SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT 20 +#define SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT 24 +#define SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT 28 + +#define SQ_WRAPPING_0_PARAM_WRAP_0_MASK 0x0000000f +#define SQ_WRAPPING_0_PARAM_WRAP_1_MASK 0x000000f0 +#define SQ_WRAPPING_0_PARAM_WRAP_2_MASK 0x00000f00 +#define SQ_WRAPPING_0_PARAM_WRAP_3_MASK 0x0000f000 +#define SQ_WRAPPING_0_PARAM_WRAP_4_MASK 0x000f0000 +#define SQ_WRAPPING_0_PARAM_WRAP_5_MASK 0x00f00000 +#define SQ_WRAPPING_0_PARAM_WRAP_6_MASK 0x0f000000 +#define SQ_WRAPPING_0_PARAM_WRAP_7_MASK 0xf0000000 + +#define SQ_WRAPPING_0_MASK \ + (SQ_WRAPPING_0_PARAM_WRAP_0_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_1_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_2_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_3_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_4_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_5_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_6_MASK | \ + SQ_WRAPPING_0_PARAM_WRAP_7_MASK) + +#define SQ_WRAPPING_0(param_wrap_0, param_wrap_1, param_wrap_2, param_wrap_3, param_wrap_4, param_wrap_5, param_wrap_6, param_wrap_7) \ + ((param_wrap_0 << SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT) | \ + (param_wrap_1 << SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT) | \ + (param_wrap_2 << SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT) | \ + (param_wrap_3 << SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT) | \ + (param_wrap_4 << SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT) | \ + (param_wrap_5 << SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT) | \ + (param_wrap_6 << SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT) | \ + (param_wrap_7 << SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT)) + +#define SQ_WRAPPING_0_GET_PARAM_WRAP_0(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_0_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_1(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_1_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_2(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_2_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_3(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_3_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_4(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_4_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_5(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_5_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_6(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_6_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT) +#define SQ_WRAPPING_0_GET_PARAM_WRAP_7(sq_wrapping_0) \ + ((sq_wrapping_0 & SQ_WRAPPING_0_PARAM_WRAP_7_MASK) >> SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT) + +#define SQ_WRAPPING_0_SET_PARAM_WRAP_0(sq_wrapping_0_reg, param_wrap_0) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_0_MASK) | (param_wrap_0 << SQ_WRAPPING_0_PARAM_WRAP_0_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_1(sq_wrapping_0_reg, param_wrap_1) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_1_MASK) | (param_wrap_1 << SQ_WRAPPING_0_PARAM_WRAP_1_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_2(sq_wrapping_0_reg, param_wrap_2) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_2_MASK) | (param_wrap_2 << SQ_WRAPPING_0_PARAM_WRAP_2_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_3(sq_wrapping_0_reg, param_wrap_3) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_3_MASK) | (param_wrap_3 << SQ_WRAPPING_0_PARAM_WRAP_3_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_4(sq_wrapping_0_reg, param_wrap_4) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_4_MASK) | (param_wrap_4 << SQ_WRAPPING_0_PARAM_WRAP_4_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_5(sq_wrapping_0_reg, param_wrap_5) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_5_MASK) | (param_wrap_5 << SQ_WRAPPING_0_PARAM_WRAP_5_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_6(sq_wrapping_0_reg, param_wrap_6) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_6_MASK) | (param_wrap_6 << SQ_WRAPPING_0_PARAM_WRAP_6_SHIFT) +#define SQ_WRAPPING_0_SET_PARAM_WRAP_7(sq_wrapping_0_reg, param_wrap_7) \ + sq_wrapping_0_reg = (sq_wrapping_0_reg & ~SQ_WRAPPING_0_PARAM_WRAP_7_MASK) | (param_wrap_7 << SQ_WRAPPING_0_PARAM_WRAP_7_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_wrapping_0_t { + unsigned int param_wrap_0 : SQ_WRAPPING_0_PARAM_WRAP_0_SIZE; + unsigned int param_wrap_1 : SQ_WRAPPING_0_PARAM_WRAP_1_SIZE; + unsigned int param_wrap_2 : SQ_WRAPPING_0_PARAM_WRAP_2_SIZE; + unsigned int param_wrap_3 : SQ_WRAPPING_0_PARAM_WRAP_3_SIZE; + unsigned int param_wrap_4 : SQ_WRAPPING_0_PARAM_WRAP_4_SIZE; + unsigned int param_wrap_5 : SQ_WRAPPING_0_PARAM_WRAP_5_SIZE; + unsigned int param_wrap_6 : SQ_WRAPPING_0_PARAM_WRAP_6_SIZE; + unsigned int param_wrap_7 : SQ_WRAPPING_0_PARAM_WRAP_7_SIZE; + } sq_wrapping_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_wrapping_0_t { + unsigned int param_wrap_7 : SQ_WRAPPING_0_PARAM_WRAP_7_SIZE; + unsigned int param_wrap_6 : SQ_WRAPPING_0_PARAM_WRAP_6_SIZE; + unsigned int param_wrap_5 : SQ_WRAPPING_0_PARAM_WRAP_5_SIZE; + unsigned int param_wrap_4 : SQ_WRAPPING_0_PARAM_WRAP_4_SIZE; + unsigned int param_wrap_3 : SQ_WRAPPING_0_PARAM_WRAP_3_SIZE; + unsigned int param_wrap_2 : SQ_WRAPPING_0_PARAM_WRAP_2_SIZE; + unsigned int param_wrap_1 : SQ_WRAPPING_0_PARAM_WRAP_1_SIZE; + unsigned int param_wrap_0 : SQ_WRAPPING_0_PARAM_WRAP_0_SIZE; + } sq_wrapping_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_wrapping_0_t f; +} sq_wrapping_0_u; + + +/* + * SQ_WRAPPING_1 struct + */ + +#define SQ_WRAPPING_1_PARAM_WRAP_8_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_9_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_10_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_11_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_12_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_13_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_14_SIZE 4 +#define SQ_WRAPPING_1_PARAM_WRAP_15_SIZE 4 + +#define SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT 0 +#define SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT 4 +#define SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT 8 +#define SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT 12 +#define SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT 16 +#define SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT 20 +#define SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT 24 +#define SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT 28 + +#define SQ_WRAPPING_1_PARAM_WRAP_8_MASK 0x0000000f +#define SQ_WRAPPING_1_PARAM_WRAP_9_MASK 0x000000f0 +#define SQ_WRAPPING_1_PARAM_WRAP_10_MASK 0x00000f00 +#define SQ_WRAPPING_1_PARAM_WRAP_11_MASK 0x0000f000 +#define SQ_WRAPPING_1_PARAM_WRAP_12_MASK 0x000f0000 +#define SQ_WRAPPING_1_PARAM_WRAP_13_MASK 0x00f00000 +#define SQ_WRAPPING_1_PARAM_WRAP_14_MASK 0x0f000000 +#define SQ_WRAPPING_1_PARAM_WRAP_15_MASK 0xf0000000 + +#define SQ_WRAPPING_1_MASK \ + (SQ_WRAPPING_1_PARAM_WRAP_8_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_9_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_10_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_11_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_12_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_13_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_14_MASK | \ + SQ_WRAPPING_1_PARAM_WRAP_15_MASK) + +#define SQ_WRAPPING_1(param_wrap_8, param_wrap_9, param_wrap_10, param_wrap_11, param_wrap_12, param_wrap_13, param_wrap_14, param_wrap_15) \ + ((param_wrap_8 << SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT) | \ + (param_wrap_9 << SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT) | \ + (param_wrap_10 << SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT) | \ + (param_wrap_11 << SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT) | \ + (param_wrap_12 << SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT) | \ + (param_wrap_13 << SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT) | \ + (param_wrap_14 << SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT) | \ + (param_wrap_15 << SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT)) + +#define SQ_WRAPPING_1_GET_PARAM_WRAP_8(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_8_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_9(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_9_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_10(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_10_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_11(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_11_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_12(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_12_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_13(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_13_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_14(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_14_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT) +#define SQ_WRAPPING_1_GET_PARAM_WRAP_15(sq_wrapping_1) \ + ((sq_wrapping_1 & SQ_WRAPPING_1_PARAM_WRAP_15_MASK) >> SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT) + +#define SQ_WRAPPING_1_SET_PARAM_WRAP_8(sq_wrapping_1_reg, param_wrap_8) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_8_MASK) | (param_wrap_8 << SQ_WRAPPING_1_PARAM_WRAP_8_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_9(sq_wrapping_1_reg, param_wrap_9) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_9_MASK) | (param_wrap_9 << SQ_WRAPPING_1_PARAM_WRAP_9_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_10(sq_wrapping_1_reg, param_wrap_10) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_10_MASK) | (param_wrap_10 << SQ_WRAPPING_1_PARAM_WRAP_10_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_11(sq_wrapping_1_reg, param_wrap_11) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_11_MASK) | (param_wrap_11 << SQ_WRAPPING_1_PARAM_WRAP_11_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_12(sq_wrapping_1_reg, param_wrap_12) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_12_MASK) | (param_wrap_12 << SQ_WRAPPING_1_PARAM_WRAP_12_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_13(sq_wrapping_1_reg, param_wrap_13) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_13_MASK) | (param_wrap_13 << SQ_WRAPPING_1_PARAM_WRAP_13_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_14(sq_wrapping_1_reg, param_wrap_14) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_14_MASK) | (param_wrap_14 << SQ_WRAPPING_1_PARAM_WRAP_14_SHIFT) +#define SQ_WRAPPING_1_SET_PARAM_WRAP_15(sq_wrapping_1_reg, param_wrap_15) \ + sq_wrapping_1_reg = (sq_wrapping_1_reg & ~SQ_WRAPPING_1_PARAM_WRAP_15_MASK) | (param_wrap_15 << SQ_WRAPPING_1_PARAM_WRAP_15_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_wrapping_1_t { + unsigned int param_wrap_8 : SQ_WRAPPING_1_PARAM_WRAP_8_SIZE; + unsigned int param_wrap_9 : SQ_WRAPPING_1_PARAM_WRAP_9_SIZE; + unsigned int param_wrap_10 : SQ_WRAPPING_1_PARAM_WRAP_10_SIZE; + unsigned int param_wrap_11 : SQ_WRAPPING_1_PARAM_WRAP_11_SIZE; + unsigned int param_wrap_12 : SQ_WRAPPING_1_PARAM_WRAP_12_SIZE; + unsigned int param_wrap_13 : SQ_WRAPPING_1_PARAM_WRAP_13_SIZE; + unsigned int param_wrap_14 : SQ_WRAPPING_1_PARAM_WRAP_14_SIZE; + unsigned int param_wrap_15 : SQ_WRAPPING_1_PARAM_WRAP_15_SIZE; + } sq_wrapping_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_wrapping_1_t { + unsigned int param_wrap_15 : SQ_WRAPPING_1_PARAM_WRAP_15_SIZE; + unsigned int param_wrap_14 : SQ_WRAPPING_1_PARAM_WRAP_14_SIZE; + unsigned int param_wrap_13 : SQ_WRAPPING_1_PARAM_WRAP_13_SIZE; + unsigned int param_wrap_12 : SQ_WRAPPING_1_PARAM_WRAP_12_SIZE; + unsigned int param_wrap_11 : SQ_WRAPPING_1_PARAM_WRAP_11_SIZE; + unsigned int param_wrap_10 : SQ_WRAPPING_1_PARAM_WRAP_10_SIZE; + unsigned int param_wrap_9 : SQ_WRAPPING_1_PARAM_WRAP_9_SIZE; + unsigned int param_wrap_8 : SQ_WRAPPING_1_PARAM_WRAP_8_SIZE; + } sq_wrapping_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_wrapping_1_t f; +} sq_wrapping_1_u; + + +/* + * SQ_VS_CONST struct + */ + +#define SQ_VS_CONST_BASE_SIZE 9 +#define SQ_VS_CONST_SIZE_SIZE 9 + +#define SQ_VS_CONST_BASE_SHIFT 0 +#define SQ_VS_CONST_SIZE_SHIFT 12 + +#define SQ_VS_CONST_BASE_MASK 0x000001ff +#define SQ_VS_CONST_SIZE_MASK 0x001ff000 + +#define SQ_VS_CONST_MASK \ + (SQ_VS_CONST_BASE_MASK | \ + SQ_VS_CONST_SIZE_MASK) + +#define SQ_VS_CONST(base, size) \ + ((base << SQ_VS_CONST_BASE_SHIFT) | \ + (size << SQ_VS_CONST_SIZE_SHIFT)) + +#define SQ_VS_CONST_GET_BASE(sq_vs_const) \ + ((sq_vs_const & SQ_VS_CONST_BASE_MASK) >> SQ_VS_CONST_BASE_SHIFT) +#define SQ_VS_CONST_GET_SIZE(sq_vs_const) \ + ((sq_vs_const & SQ_VS_CONST_SIZE_MASK) >> SQ_VS_CONST_SIZE_SHIFT) + +#define SQ_VS_CONST_SET_BASE(sq_vs_const_reg, base) \ + sq_vs_const_reg = (sq_vs_const_reg & ~SQ_VS_CONST_BASE_MASK) | (base << SQ_VS_CONST_BASE_SHIFT) +#define SQ_VS_CONST_SET_SIZE(sq_vs_const_reg, size) \ + sq_vs_const_reg = (sq_vs_const_reg & ~SQ_VS_CONST_SIZE_MASK) | (size << SQ_VS_CONST_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_vs_const_t { + unsigned int base : SQ_VS_CONST_BASE_SIZE; + unsigned int : 3; + unsigned int size : SQ_VS_CONST_SIZE_SIZE; + unsigned int : 11; + } sq_vs_const_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_vs_const_t { + unsigned int : 11; + unsigned int size : SQ_VS_CONST_SIZE_SIZE; + unsigned int : 3; + unsigned int base : SQ_VS_CONST_BASE_SIZE; + } sq_vs_const_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_vs_const_t f; +} sq_vs_const_u; + + +/* + * SQ_PS_CONST struct + */ + +#define SQ_PS_CONST_BASE_SIZE 9 +#define SQ_PS_CONST_SIZE_SIZE 9 + +#define SQ_PS_CONST_BASE_SHIFT 0 +#define SQ_PS_CONST_SIZE_SHIFT 12 + +#define SQ_PS_CONST_BASE_MASK 0x000001ff +#define SQ_PS_CONST_SIZE_MASK 0x001ff000 + +#define SQ_PS_CONST_MASK \ + (SQ_PS_CONST_BASE_MASK | \ + SQ_PS_CONST_SIZE_MASK) + +#define SQ_PS_CONST(base, size) \ + ((base << SQ_PS_CONST_BASE_SHIFT) | \ + (size << SQ_PS_CONST_SIZE_SHIFT)) + +#define SQ_PS_CONST_GET_BASE(sq_ps_const) \ + ((sq_ps_const & SQ_PS_CONST_BASE_MASK) >> SQ_PS_CONST_BASE_SHIFT) +#define SQ_PS_CONST_GET_SIZE(sq_ps_const) \ + ((sq_ps_const & SQ_PS_CONST_SIZE_MASK) >> SQ_PS_CONST_SIZE_SHIFT) + +#define SQ_PS_CONST_SET_BASE(sq_ps_const_reg, base) \ + sq_ps_const_reg = (sq_ps_const_reg & ~SQ_PS_CONST_BASE_MASK) | (base << SQ_PS_CONST_BASE_SHIFT) +#define SQ_PS_CONST_SET_SIZE(sq_ps_const_reg, size) \ + sq_ps_const_reg = (sq_ps_const_reg & ~SQ_PS_CONST_SIZE_MASK) | (size << SQ_PS_CONST_SIZE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_ps_const_t { + unsigned int base : SQ_PS_CONST_BASE_SIZE; + unsigned int : 3; + unsigned int size : SQ_PS_CONST_SIZE_SIZE; + unsigned int : 11; + } sq_ps_const_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_ps_const_t { + unsigned int : 11; + unsigned int size : SQ_PS_CONST_SIZE_SIZE; + unsigned int : 3; + unsigned int base : SQ_PS_CONST_BASE_SIZE; + } sq_ps_const_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_ps_const_t f; +} sq_ps_const_u; + + +/* + * SQ_CONTEXT_MISC struct + */ + +#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE 1 +#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE 1 +#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE 2 +#define SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE 8 +#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE 1 +#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE 1 +#define SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE 1 + +#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT 0 +#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT 1 +#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT 2 +#define SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT 8 +#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT 16 +#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT 17 +#define SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT 18 + +#define SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK 0x00000001 +#define SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK 0x00000002 +#define SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK 0x0000000c +#define SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK 0x0000ff00 +#define SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK 0x00010000 +#define SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK 0x00020000 +#define SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK 0x00040000 + +#define SQ_CONTEXT_MISC_MASK \ + (SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK | \ + SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK | \ + SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK | \ + SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK | \ + SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK | \ + SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK | \ + SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) + +#define SQ_CONTEXT_MISC(inst_pred_optimize, sc_output_screen_xy, sc_sample_cntl, param_gen_pos, perfcounter_ref, yeild_optimize, tx_cache_sel) \ + ((inst_pred_optimize << SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT) | \ + (sc_output_screen_xy << SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT) | \ + (sc_sample_cntl << SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT) | \ + (param_gen_pos << SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT) | \ + (perfcounter_ref << SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT) | \ + (yeild_optimize << SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT) | \ + (tx_cache_sel << SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT)) + +#define SQ_CONTEXT_MISC_GET_INST_PRED_OPTIMIZE(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK) >> SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT) +#define SQ_CONTEXT_MISC_GET_SC_OUTPUT_SCREEN_XY(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK) >> SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT) +#define SQ_CONTEXT_MISC_GET_SC_SAMPLE_CNTL(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK) >> SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT) +#define SQ_CONTEXT_MISC_GET_PARAM_GEN_POS(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK) >> SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT) +#define SQ_CONTEXT_MISC_GET_PERFCOUNTER_REF(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK) >> SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT) +#define SQ_CONTEXT_MISC_GET_YEILD_OPTIMIZE(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK) >> SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT) +#define SQ_CONTEXT_MISC_GET_TX_CACHE_SEL(sq_context_misc) \ + ((sq_context_misc & SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) >> SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT) + +#define SQ_CONTEXT_MISC_SET_INST_PRED_OPTIMIZE(sq_context_misc_reg, inst_pred_optimize) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_MASK) | (inst_pred_optimize << SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SHIFT) +#define SQ_CONTEXT_MISC_SET_SC_OUTPUT_SCREEN_XY(sq_context_misc_reg, sc_output_screen_xy) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_MASK) | (sc_output_screen_xy << SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SHIFT) +#define SQ_CONTEXT_MISC_SET_SC_SAMPLE_CNTL(sq_context_misc_reg, sc_sample_cntl) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_MASK) | (sc_sample_cntl << SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SHIFT) +#define SQ_CONTEXT_MISC_SET_PARAM_GEN_POS(sq_context_misc_reg, param_gen_pos) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_PARAM_GEN_POS_MASK) | (param_gen_pos << SQ_CONTEXT_MISC_PARAM_GEN_POS_SHIFT) +#define SQ_CONTEXT_MISC_SET_PERFCOUNTER_REF(sq_context_misc_reg, perfcounter_ref) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_PERFCOUNTER_REF_MASK) | (perfcounter_ref << SQ_CONTEXT_MISC_PERFCOUNTER_REF_SHIFT) +#define SQ_CONTEXT_MISC_SET_YEILD_OPTIMIZE(sq_context_misc_reg, yeild_optimize) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_YEILD_OPTIMIZE_MASK) | (yeild_optimize << SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SHIFT) +#define SQ_CONTEXT_MISC_SET_TX_CACHE_SEL(sq_context_misc_reg, tx_cache_sel) \ + sq_context_misc_reg = (sq_context_misc_reg & ~SQ_CONTEXT_MISC_TX_CACHE_SEL_MASK) | (tx_cache_sel << SQ_CONTEXT_MISC_TX_CACHE_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_context_misc_t { + unsigned int inst_pred_optimize : SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE; + unsigned int sc_output_screen_xy : SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE; + unsigned int sc_sample_cntl : SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE; + unsigned int : 4; + unsigned int param_gen_pos : SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE; + unsigned int perfcounter_ref : SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE; + unsigned int yeild_optimize : SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE; + unsigned int tx_cache_sel : SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE; + unsigned int : 13; + } sq_context_misc_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_context_misc_t { + unsigned int : 13; + unsigned int tx_cache_sel : SQ_CONTEXT_MISC_TX_CACHE_SEL_SIZE; + unsigned int yeild_optimize : SQ_CONTEXT_MISC_YEILD_OPTIMIZE_SIZE; + unsigned int perfcounter_ref : SQ_CONTEXT_MISC_PERFCOUNTER_REF_SIZE; + unsigned int param_gen_pos : SQ_CONTEXT_MISC_PARAM_GEN_POS_SIZE; + unsigned int : 4; + unsigned int sc_sample_cntl : SQ_CONTEXT_MISC_SC_SAMPLE_CNTL_SIZE; + unsigned int sc_output_screen_xy : SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY_SIZE; + unsigned int inst_pred_optimize : SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE_SIZE; + } sq_context_misc_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_context_misc_t f; +} sq_context_misc_u; + + +/* + * SQ_CF_RD_BASE struct + */ + +#define SQ_CF_RD_BASE_RD_BASE_SIZE 3 + +#define SQ_CF_RD_BASE_RD_BASE_SHIFT 0 + +#define SQ_CF_RD_BASE_RD_BASE_MASK 0x00000007 + +#define SQ_CF_RD_BASE_MASK \ + (SQ_CF_RD_BASE_RD_BASE_MASK) + +#define SQ_CF_RD_BASE(rd_base) \ + ((rd_base << SQ_CF_RD_BASE_RD_BASE_SHIFT)) + +#define SQ_CF_RD_BASE_GET_RD_BASE(sq_cf_rd_base) \ + ((sq_cf_rd_base & SQ_CF_RD_BASE_RD_BASE_MASK) >> SQ_CF_RD_BASE_RD_BASE_SHIFT) + +#define SQ_CF_RD_BASE_SET_RD_BASE(sq_cf_rd_base_reg, rd_base) \ + sq_cf_rd_base_reg = (sq_cf_rd_base_reg & ~SQ_CF_RD_BASE_RD_BASE_MASK) | (rd_base << SQ_CF_RD_BASE_RD_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_cf_rd_base_t { + unsigned int rd_base : SQ_CF_RD_BASE_RD_BASE_SIZE; + unsigned int : 29; + } sq_cf_rd_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_cf_rd_base_t { + unsigned int : 29; + unsigned int rd_base : SQ_CF_RD_BASE_RD_BASE_SIZE; + } sq_cf_rd_base_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_cf_rd_base_t f; +} sq_cf_rd_base_u; + + +/* + * SQ_DEBUG_MISC_0 struct + */ + +#define SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE 1 +#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE 1 +#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE 11 +#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE 8 + +#define SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT 0 +#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT 4 +#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT 8 +#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT 24 + +#define SQ_DEBUG_MISC_0_DB_PROB_ON_MASK 0x00000001 +#define SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK 0x00000010 +#define SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK 0x0007ff00 +#define SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK 0xff000000 + +#define SQ_DEBUG_MISC_0_MASK \ + (SQ_DEBUG_MISC_0_DB_PROB_ON_MASK | \ + SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK | \ + SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK | \ + SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) + +#define SQ_DEBUG_MISC_0(db_prob_on, db_prob_break, db_prob_addr, db_prob_count) \ + ((db_prob_on << SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT) | \ + (db_prob_break << SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT) | \ + (db_prob_addr << SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT) | \ + (db_prob_count << SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT)) + +#define SQ_DEBUG_MISC_0_GET_DB_PROB_ON(sq_debug_misc_0) \ + ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_ON_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT) +#define SQ_DEBUG_MISC_0_GET_DB_PROB_BREAK(sq_debug_misc_0) \ + ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT) +#define SQ_DEBUG_MISC_0_GET_DB_PROB_ADDR(sq_debug_misc_0) \ + ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT) +#define SQ_DEBUG_MISC_0_GET_DB_PROB_COUNT(sq_debug_misc_0) \ + ((sq_debug_misc_0 & SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) >> SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT) + +#define SQ_DEBUG_MISC_0_SET_DB_PROB_ON(sq_debug_misc_0_reg, db_prob_on) \ + sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_ON_MASK) | (db_prob_on << SQ_DEBUG_MISC_0_DB_PROB_ON_SHIFT) +#define SQ_DEBUG_MISC_0_SET_DB_PROB_BREAK(sq_debug_misc_0_reg, db_prob_break) \ + sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_BREAK_MASK) | (db_prob_break << SQ_DEBUG_MISC_0_DB_PROB_BREAK_SHIFT) +#define SQ_DEBUG_MISC_0_SET_DB_PROB_ADDR(sq_debug_misc_0_reg, db_prob_addr) \ + sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_ADDR_MASK) | (db_prob_addr << SQ_DEBUG_MISC_0_DB_PROB_ADDR_SHIFT) +#define SQ_DEBUG_MISC_0_SET_DB_PROB_COUNT(sq_debug_misc_0_reg, db_prob_count) \ + sq_debug_misc_0_reg = (sq_debug_misc_0_reg & ~SQ_DEBUG_MISC_0_DB_PROB_COUNT_MASK) | (db_prob_count << SQ_DEBUG_MISC_0_DB_PROB_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_misc_0_t { + unsigned int db_prob_on : SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE; + unsigned int : 3; + unsigned int db_prob_break : SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE; + unsigned int : 3; + unsigned int db_prob_addr : SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE; + unsigned int : 5; + unsigned int db_prob_count : SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE; + } sq_debug_misc_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_misc_0_t { + unsigned int db_prob_count : SQ_DEBUG_MISC_0_DB_PROB_COUNT_SIZE; + unsigned int : 5; + unsigned int db_prob_addr : SQ_DEBUG_MISC_0_DB_PROB_ADDR_SIZE; + unsigned int : 3; + unsigned int db_prob_break : SQ_DEBUG_MISC_0_DB_PROB_BREAK_SIZE; + unsigned int : 3; + unsigned int db_prob_on : SQ_DEBUG_MISC_0_DB_PROB_ON_SIZE; + } sq_debug_misc_0_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_misc_0_t f; +} sq_debug_misc_0_u; + + +/* + * SQ_DEBUG_MISC_1 struct + */ + +#define SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE 1 +#define SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE 1 +#define SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE 8 +#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE 11 + +#define SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT 0 +#define SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT 1 +#define SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT 8 +#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT 16 + +#define SQ_DEBUG_MISC_1_DB_ON_PIX_MASK 0x00000001 +#define SQ_DEBUG_MISC_1_DB_ON_VTX_MASK 0x00000002 +#define SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK 0x0000ff00 +#define SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK 0x07ff0000 + +#define SQ_DEBUG_MISC_1_MASK \ + (SQ_DEBUG_MISC_1_DB_ON_PIX_MASK | \ + SQ_DEBUG_MISC_1_DB_ON_VTX_MASK | \ + SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK | \ + SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) + +#define SQ_DEBUG_MISC_1(db_on_pix, db_on_vtx, db_inst_count, db_break_addr) \ + ((db_on_pix << SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT) | \ + (db_on_vtx << SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT) | \ + (db_inst_count << SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT) | \ + (db_break_addr << SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT)) + +#define SQ_DEBUG_MISC_1_GET_DB_ON_PIX(sq_debug_misc_1) \ + ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_ON_PIX_MASK) >> SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT) +#define SQ_DEBUG_MISC_1_GET_DB_ON_VTX(sq_debug_misc_1) \ + ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_ON_VTX_MASK) >> SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT) +#define SQ_DEBUG_MISC_1_GET_DB_INST_COUNT(sq_debug_misc_1) \ + ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK) >> SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT) +#define SQ_DEBUG_MISC_1_GET_DB_BREAK_ADDR(sq_debug_misc_1) \ + ((sq_debug_misc_1 & SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) >> SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT) + +#define SQ_DEBUG_MISC_1_SET_DB_ON_PIX(sq_debug_misc_1_reg, db_on_pix) \ + sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_ON_PIX_MASK) | (db_on_pix << SQ_DEBUG_MISC_1_DB_ON_PIX_SHIFT) +#define SQ_DEBUG_MISC_1_SET_DB_ON_VTX(sq_debug_misc_1_reg, db_on_vtx) \ + sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_ON_VTX_MASK) | (db_on_vtx << SQ_DEBUG_MISC_1_DB_ON_VTX_SHIFT) +#define SQ_DEBUG_MISC_1_SET_DB_INST_COUNT(sq_debug_misc_1_reg, db_inst_count) \ + sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_INST_COUNT_MASK) | (db_inst_count << SQ_DEBUG_MISC_1_DB_INST_COUNT_SHIFT) +#define SQ_DEBUG_MISC_1_SET_DB_BREAK_ADDR(sq_debug_misc_1_reg, db_break_addr) \ + sq_debug_misc_1_reg = (sq_debug_misc_1_reg & ~SQ_DEBUG_MISC_1_DB_BREAK_ADDR_MASK) | (db_break_addr << SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _sq_debug_misc_1_t { + unsigned int db_on_pix : SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE; + unsigned int db_on_vtx : SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE; + unsigned int : 6; + unsigned int db_inst_count : SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE; + unsigned int db_break_addr : SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE; + unsigned int : 5; + } sq_debug_misc_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _sq_debug_misc_1_t { + unsigned int : 5; + unsigned int db_break_addr : SQ_DEBUG_MISC_1_DB_BREAK_ADDR_SIZE; + unsigned int db_inst_count : SQ_DEBUG_MISC_1_DB_INST_COUNT_SIZE; + unsigned int : 6; + unsigned int db_on_vtx : SQ_DEBUG_MISC_1_DB_ON_VTX_SIZE; + unsigned int db_on_pix : SQ_DEBUG_MISC_1_DB_ON_PIX_SIZE; + } sq_debug_misc_1_t; + +#endif + +typedef union { + unsigned int val : 32; + sq_debug_misc_1_t f; +} sq_debug_misc_1_u; + + +#endif + + +#if !defined (_SX_FIDDLE_H) +#define _SX_FIDDLE_H + +/***************************************************************************************************************** + * + * sx_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +#endif + + +#if !defined (_TP_FIDDLE_H) +#define _TP_FIDDLE_H + +/***************************************************************************************************************** + * + * tp_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * TC_CNTL_STATUS struct + */ + +#define TC_CNTL_STATUS_L2_INVALIDATE_SIZE 1 +#define TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE 2 +#define TC_CNTL_STATUS_TC_BUSY_SIZE 1 + +#define TC_CNTL_STATUS_L2_INVALIDATE_SHIFT 0 +#define TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT 18 +#define TC_CNTL_STATUS_TC_BUSY_SHIFT 31 + +#define TC_CNTL_STATUS_L2_INVALIDATE_MASK 0x00000001 +#define TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK 0x000c0000 +#define TC_CNTL_STATUS_TC_BUSY_MASK 0x80000000 + +#define TC_CNTL_STATUS_MASK \ + (TC_CNTL_STATUS_L2_INVALIDATE_MASK | \ + TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK | \ + TC_CNTL_STATUS_TC_BUSY_MASK) + +#define TC_CNTL_STATUS(l2_invalidate, tc_l2_hit_miss, tc_busy) \ + ((l2_invalidate << TC_CNTL_STATUS_L2_INVALIDATE_SHIFT) | \ + (tc_l2_hit_miss << TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT) | \ + (tc_busy << TC_CNTL_STATUS_TC_BUSY_SHIFT)) + +#define TC_CNTL_STATUS_GET_L2_INVALIDATE(tc_cntl_status) \ + ((tc_cntl_status & TC_CNTL_STATUS_L2_INVALIDATE_MASK) >> TC_CNTL_STATUS_L2_INVALIDATE_SHIFT) +#define TC_CNTL_STATUS_GET_TC_L2_HIT_MISS(tc_cntl_status) \ + ((tc_cntl_status & TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK) >> TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT) +#define TC_CNTL_STATUS_GET_TC_BUSY(tc_cntl_status) \ + ((tc_cntl_status & TC_CNTL_STATUS_TC_BUSY_MASK) >> TC_CNTL_STATUS_TC_BUSY_SHIFT) + +#define TC_CNTL_STATUS_SET_L2_INVALIDATE(tc_cntl_status_reg, l2_invalidate) \ + tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_L2_INVALIDATE_MASK) | (l2_invalidate << TC_CNTL_STATUS_L2_INVALIDATE_SHIFT) +#define TC_CNTL_STATUS_SET_TC_L2_HIT_MISS(tc_cntl_status_reg, tc_l2_hit_miss) \ + tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_TC_L2_HIT_MISS_MASK) | (tc_l2_hit_miss << TC_CNTL_STATUS_TC_L2_HIT_MISS_SHIFT) +#define TC_CNTL_STATUS_SET_TC_BUSY(tc_cntl_status_reg, tc_busy) \ + tc_cntl_status_reg = (tc_cntl_status_reg & ~TC_CNTL_STATUS_TC_BUSY_MASK) | (tc_busy << TC_CNTL_STATUS_TC_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tc_cntl_status_t { + unsigned int l2_invalidate : TC_CNTL_STATUS_L2_INVALIDATE_SIZE; + unsigned int : 17; + unsigned int tc_l2_hit_miss : TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE; + unsigned int : 11; + unsigned int tc_busy : TC_CNTL_STATUS_TC_BUSY_SIZE; + } tc_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _tc_cntl_status_t { + unsigned int tc_busy : TC_CNTL_STATUS_TC_BUSY_SIZE; + unsigned int : 11; + unsigned int tc_l2_hit_miss : TC_CNTL_STATUS_TC_L2_HIT_MISS_SIZE; + unsigned int : 17; + unsigned int l2_invalidate : TC_CNTL_STATUS_L2_INVALIDATE_SIZE; + } tc_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + tc_cntl_status_t f; +} tc_cntl_status_u; + + +/* + * TCR_CHICKEN struct + */ + +#define TCR_CHICKEN_SPARE_SIZE 32 + +#define TCR_CHICKEN_SPARE_SHIFT 0 + +#define TCR_CHICKEN_SPARE_MASK 0xffffffff + +#define TCR_CHICKEN_MASK \ + (TCR_CHICKEN_SPARE_MASK) + +#define TCR_CHICKEN(spare) \ + ((spare << TCR_CHICKEN_SPARE_SHIFT)) + +#define TCR_CHICKEN_GET_SPARE(tcr_chicken) \ + ((tcr_chicken & TCR_CHICKEN_SPARE_MASK) >> TCR_CHICKEN_SPARE_SHIFT) + +#define TCR_CHICKEN_SET_SPARE(tcr_chicken_reg, spare) \ + tcr_chicken_reg = (tcr_chicken_reg & ~TCR_CHICKEN_SPARE_MASK) | (spare << TCR_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_chicken_t { + unsigned int spare : TCR_CHICKEN_SPARE_SIZE; + } tcr_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_chicken_t { + unsigned int spare : TCR_CHICKEN_SPARE_SIZE; + } tcr_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_chicken_t f; +} tcr_chicken_u; + + +/* + * TCF_CHICKEN struct + */ + +#define TCF_CHICKEN_SPARE_SIZE 32 + +#define TCF_CHICKEN_SPARE_SHIFT 0 + +#define TCF_CHICKEN_SPARE_MASK 0xffffffff + +#define TCF_CHICKEN_MASK \ + (TCF_CHICKEN_SPARE_MASK) + +#define TCF_CHICKEN(spare) \ + ((spare << TCF_CHICKEN_SPARE_SHIFT)) + +#define TCF_CHICKEN_GET_SPARE(tcf_chicken) \ + ((tcf_chicken & TCF_CHICKEN_SPARE_MASK) >> TCF_CHICKEN_SPARE_SHIFT) + +#define TCF_CHICKEN_SET_SPARE(tcf_chicken_reg, spare) \ + tcf_chicken_reg = (tcf_chicken_reg & ~TCF_CHICKEN_SPARE_MASK) | (spare << TCF_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_chicken_t { + unsigned int spare : TCF_CHICKEN_SPARE_SIZE; + } tcf_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_chicken_t { + unsigned int spare : TCF_CHICKEN_SPARE_SIZE; + } tcf_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_chicken_t f; +} tcf_chicken_u; + + +/* + * TCM_CHICKEN struct + */ + +#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE 8 +#define TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE 1 +#define TCM_CHICKEN_SPARE_SIZE 23 + +#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT 0 +#define TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT 8 +#define TCM_CHICKEN_SPARE_SHIFT 9 + +#define TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK 0x000000ff +#define TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK 0x00000100 +#define TCM_CHICKEN_SPARE_MASK 0xfffffe00 + +#define TCM_CHICKEN_MASK \ + (TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK | \ + TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK | \ + TCM_CHICKEN_SPARE_MASK) + +#define TCM_CHICKEN(tco_read_latency_fifo_prog_depth, etc_color_endian, spare) \ + ((tco_read_latency_fifo_prog_depth << TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT) | \ + (etc_color_endian << TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT) | \ + (spare << TCM_CHICKEN_SPARE_SHIFT)) + +#define TCM_CHICKEN_GET_TCO_READ_LATENCY_FIFO_PROG_DEPTH(tcm_chicken) \ + ((tcm_chicken & TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK) >> TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT) +#define TCM_CHICKEN_GET_ETC_COLOR_ENDIAN(tcm_chicken) \ + ((tcm_chicken & TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK) >> TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT) +#define TCM_CHICKEN_GET_SPARE(tcm_chicken) \ + ((tcm_chicken & TCM_CHICKEN_SPARE_MASK) >> TCM_CHICKEN_SPARE_SHIFT) + +#define TCM_CHICKEN_SET_TCO_READ_LATENCY_FIFO_PROG_DEPTH(tcm_chicken_reg, tco_read_latency_fifo_prog_depth) \ + tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_MASK) | (tco_read_latency_fifo_prog_depth << TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SHIFT) +#define TCM_CHICKEN_SET_ETC_COLOR_ENDIAN(tcm_chicken_reg, etc_color_endian) \ + tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_ETC_COLOR_ENDIAN_MASK) | (etc_color_endian << TCM_CHICKEN_ETC_COLOR_ENDIAN_SHIFT) +#define TCM_CHICKEN_SET_SPARE(tcm_chicken_reg, spare) \ + tcm_chicken_reg = (tcm_chicken_reg & ~TCM_CHICKEN_SPARE_MASK) | (spare << TCM_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_chicken_t { + unsigned int tco_read_latency_fifo_prog_depth : TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE; + unsigned int etc_color_endian : TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE; + unsigned int spare : TCM_CHICKEN_SPARE_SIZE; + } tcm_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_chicken_t { + unsigned int spare : TCM_CHICKEN_SPARE_SIZE; + unsigned int etc_color_endian : TCM_CHICKEN_ETC_COLOR_ENDIAN_SIZE; + unsigned int tco_read_latency_fifo_prog_depth : TCM_CHICKEN_TCO_READ_LATENCY_FIFO_PROG_DEPTH_SIZE; + } tcm_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_chicken_t f; +} tcm_chicken_u; + + +/* + * TCR_PERFCOUNTER0_SELECT struct + */ + +#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCR_PERFCOUNTER0_SELECT_MASK \ + (TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCR_PERFCOUNTER0_SELECT(perfcounter_select) \ + ((perfcounter_select << TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCR_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcr_perfcounter0_select) \ + ((tcr_perfcounter0_select & TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCR_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcr_perfcounter0_select_reg, perfcounter_select) \ + tcr_perfcounter0_select_reg = (tcr_perfcounter0_select_reg & ~TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_select_t { + unsigned int perfcounter_select : TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcr_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCR_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcr_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter0_select_t f; +} tcr_perfcounter0_select_u; + + +/* + * TCR_PERFCOUNTER1_SELECT struct + */ + +#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCR_PERFCOUNTER1_SELECT_MASK \ + (TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCR_PERFCOUNTER1_SELECT(perfcounter_select) \ + ((perfcounter_select << TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCR_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcr_perfcounter1_select) \ + ((tcr_perfcounter1_select & TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCR_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcr_perfcounter1_select_reg, perfcounter_select) \ + tcr_perfcounter1_select_reg = (tcr_perfcounter1_select_reg & ~TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_select_t { + unsigned int perfcounter_select : TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcr_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCR_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcr_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter1_select_t f; +} tcr_perfcounter1_select_u; + + +/* + * TCR_PERFCOUNTER0_HI struct + */ + +#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCR_PERFCOUNTER0_HI_MASK \ + (TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) + +#define TCR_PERFCOUNTER0_HI(perfcounter_hi) \ + ((perfcounter_hi << TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCR_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcr_perfcounter0_hi) \ + ((tcr_perfcounter0_hi & TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#define TCR_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcr_perfcounter0_hi_reg, perfcounter_hi) \ + tcr_perfcounter0_hi_reg = (tcr_perfcounter0_hi_reg & ~TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_hi_t { + unsigned int perfcounter_hi : TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcr_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCR_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + } tcr_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter0_hi_t f; +} tcr_perfcounter0_hi_u; + + +/* + * TCR_PERFCOUNTER1_HI struct + */ + +#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCR_PERFCOUNTER1_HI_MASK \ + (TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) + +#define TCR_PERFCOUNTER1_HI(perfcounter_hi) \ + ((perfcounter_hi << TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCR_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcr_perfcounter1_hi) \ + ((tcr_perfcounter1_hi & TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#define TCR_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcr_perfcounter1_hi_reg, perfcounter_hi) \ + tcr_perfcounter1_hi_reg = (tcr_perfcounter1_hi_reg & ~TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_hi_t { + unsigned int perfcounter_hi : TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcr_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCR_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + } tcr_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter1_hi_t f; +} tcr_perfcounter1_hi_u; + + +/* + * TCR_PERFCOUNTER0_LOW struct + */ + +#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCR_PERFCOUNTER0_LOW_MASK \ + (TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) + +#define TCR_PERFCOUNTER0_LOW(perfcounter_low) \ + ((perfcounter_low << TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCR_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcr_perfcounter0_low) \ + ((tcr_perfcounter0_low & TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCR_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcr_perfcounter0_low_reg, perfcounter_low) \ + tcr_perfcounter0_low_reg = (tcr_perfcounter0_low_reg & ~TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_low_t { + unsigned int perfcounter_low : TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcr_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter0_low_t { + unsigned int perfcounter_low : TCR_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcr_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter0_low_t f; +} tcr_perfcounter0_low_u; + + +/* + * TCR_PERFCOUNTER1_LOW struct + */ + +#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCR_PERFCOUNTER1_LOW_MASK \ + (TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) + +#define TCR_PERFCOUNTER1_LOW(perfcounter_low) \ + ((perfcounter_low << TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCR_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcr_perfcounter1_low) \ + ((tcr_perfcounter1_low & TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCR_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcr_perfcounter1_low_reg, perfcounter_low) \ + tcr_perfcounter1_low_reg = (tcr_perfcounter1_low_reg & ~TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_low_t { + unsigned int perfcounter_low : TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcr_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcr_perfcounter1_low_t { + unsigned int perfcounter_low : TCR_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcr_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcr_perfcounter1_low_t f; +} tcr_perfcounter1_low_u; + + +/* + * TP_TC_CLKGATE_CNTL struct + */ + +#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE 3 +#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE 3 + +#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT 0 +#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT 3 + +#define TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK 0x00000007 +#define TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK 0x00000038 + +#define TP_TC_CLKGATE_CNTL_MASK \ + (TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK | \ + TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) + +#define TP_TC_CLKGATE_CNTL(tp_busy_extend, tc_busy_extend) \ + ((tp_busy_extend << TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT) | \ + (tc_busy_extend << TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT)) + +#define TP_TC_CLKGATE_CNTL_GET_TP_BUSY_EXTEND(tp_tc_clkgate_cntl) \ + ((tp_tc_clkgate_cntl & TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK) >> TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT) +#define TP_TC_CLKGATE_CNTL_GET_TC_BUSY_EXTEND(tp_tc_clkgate_cntl) \ + ((tp_tc_clkgate_cntl & TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) >> TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT) + +#define TP_TC_CLKGATE_CNTL_SET_TP_BUSY_EXTEND(tp_tc_clkgate_cntl_reg, tp_busy_extend) \ + tp_tc_clkgate_cntl_reg = (tp_tc_clkgate_cntl_reg & ~TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_MASK) | (tp_busy_extend << TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SHIFT) +#define TP_TC_CLKGATE_CNTL_SET_TC_BUSY_EXTEND(tp_tc_clkgate_cntl_reg, tc_busy_extend) \ + tp_tc_clkgate_cntl_reg = (tp_tc_clkgate_cntl_reg & ~TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_MASK) | (tc_busy_extend << TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp_tc_clkgate_cntl_t { + unsigned int tp_busy_extend : TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE; + unsigned int tc_busy_extend : TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE; + unsigned int : 26; + } tp_tc_clkgate_cntl_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp_tc_clkgate_cntl_t { + unsigned int : 26; + unsigned int tc_busy_extend : TP_TC_CLKGATE_CNTL_TC_BUSY_EXTEND_SIZE; + unsigned int tp_busy_extend : TP_TC_CLKGATE_CNTL_TP_BUSY_EXTEND_SIZE; + } tp_tc_clkgate_cntl_t; + +#endif + +typedef union { + unsigned int val : 32; + tp_tc_clkgate_cntl_t f; +} tp_tc_clkgate_cntl_u; + + +/* + * TPC_CNTL_STATUS struct + */ + +#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE 1 +#define TPC_CNTL_STATUS_TF_TW_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TF_TW_RTR_SIZE 1 +#define TPC_CNTL_STATUS_TW_TA_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TW_TA_RTR_SIZE 1 +#define TPC_CNTL_STATUS_TA_TB_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TA_TB_RTR_SIZE 1 +#define TPC_CNTL_STATUS_TA_TF_RTS_SIZE 1 +#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE 1 +#define TPC_CNTL_STATUS_TP_SQ_DEC_SIZE 1 +#define TPC_CNTL_STATUS_TPC_BUSY_SIZE 1 + +#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT 0 +#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT 1 +#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT 2 +#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT 3 +#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT 4 +#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT 5 +#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT 6 +#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT 8 +#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT 9 +#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT 10 +#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT 12 +#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT 13 +#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT 14 +#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT 15 +#define TPC_CNTL_STATUS_TF_TW_RTS_SHIFT 16 +#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT 17 +#define TPC_CNTL_STATUS_TF_TW_RTR_SHIFT 19 +#define TPC_CNTL_STATUS_TW_TA_RTS_SHIFT 20 +#define TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT 21 +#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT 22 +#define TPC_CNTL_STATUS_TW_TA_RTR_SHIFT 23 +#define TPC_CNTL_STATUS_TA_TB_RTS_SHIFT 24 +#define TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT 25 +#define TPC_CNTL_STATUS_TA_TB_RTR_SHIFT 27 +#define TPC_CNTL_STATUS_TA_TF_RTS_SHIFT 28 +#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT 29 +#define TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT 30 +#define TPC_CNTL_STATUS_TPC_BUSY_SHIFT 31 + +#define TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK 0x00000001 +#define TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK 0x00000002 +#define TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK 0x00000004 +#define TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK 0x00000008 +#define TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK 0x00000010 +#define TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK 0x00000020 +#define TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK 0x00000040 +#define TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK 0x00000100 +#define TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK 0x00000200 +#define TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK 0x00000400 +#define TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK 0x00001000 +#define TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK 0x00002000 +#define TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK 0x00004000 +#define TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK 0x00008000 +#define TPC_CNTL_STATUS_TF_TW_RTS_MASK 0x00010000 +#define TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK 0x00020000 +#define TPC_CNTL_STATUS_TF_TW_RTR_MASK 0x00080000 +#define TPC_CNTL_STATUS_TW_TA_RTS_MASK 0x00100000 +#define TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK 0x00200000 +#define TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK 0x00400000 +#define TPC_CNTL_STATUS_TW_TA_RTR_MASK 0x00800000 +#define TPC_CNTL_STATUS_TA_TB_RTS_MASK 0x01000000 +#define TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK 0x02000000 +#define TPC_CNTL_STATUS_TA_TB_RTR_MASK 0x08000000 +#define TPC_CNTL_STATUS_TA_TF_RTS_MASK 0x10000000 +#define TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK 0x20000000 +#define TPC_CNTL_STATUS_TP_SQ_DEC_MASK 0x40000000 +#define TPC_CNTL_STATUS_TPC_BUSY_MASK 0x80000000 + +#define TPC_CNTL_STATUS_MASK \ + (TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK | \ + TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK | \ + TPC_CNTL_STATUS_TF_TW_RTS_MASK | \ + TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK | \ + TPC_CNTL_STATUS_TF_TW_RTR_MASK | \ + TPC_CNTL_STATUS_TW_TA_RTS_MASK | \ + TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK | \ + TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK | \ + TPC_CNTL_STATUS_TW_TA_RTR_MASK | \ + TPC_CNTL_STATUS_TA_TB_RTS_MASK | \ + TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK | \ + TPC_CNTL_STATUS_TA_TB_RTR_MASK | \ + TPC_CNTL_STATUS_TA_TF_RTS_MASK | \ + TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK | \ + TPC_CNTL_STATUS_TP_SQ_DEC_MASK | \ + TPC_CNTL_STATUS_TPC_BUSY_MASK) + +#define TPC_CNTL_STATUS(tpc_input_busy, tpc_tc_fifo_busy, tpc_state_fifo_busy, tpc_fetch_fifo_busy, tpc_walker_pipe_busy, tpc_walk_fifo_busy, tpc_walker_busy, tpc_aligner_pipe_busy, tpc_align_fifo_busy, tpc_aligner_busy, tpc_rr_fifo_busy, tpc_blend_pipe_busy, tpc_out_fifo_busy, tpc_blend_busy, tf_tw_rts, tf_tw_state_rts, tf_tw_rtr, tw_ta_rts, tw_ta_tt_rts, tw_ta_last_rts, tw_ta_rtr, ta_tb_rts, ta_tb_tt_rts, ta_tb_rtr, ta_tf_rts, ta_tf_tc_fifo_ren, tp_sq_dec, tpc_busy) \ + ((tpc_input_busy << TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT) | \ + (tpc_tc_fifo_busy << TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT) | \ + (tpc_state_fifo_busy << TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT) | \ + (tpc_fetch_fifo_busy << TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT) | \ + (tpc_walker_pipe_busy << TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT) | \ + (tpc_walk_fifo_busy << TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT) | \ + (tpc_walker_busy << TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT) | \ + (tpc_aligner_pipe_busy << TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT) | \ + (tpc_align_fifo_busy << TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT) | \ + (tpc_aligner_busy << TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT) | \ + (tpc_rr_fifo_busy << TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT) | \ + (tpc_blend_pipe_busy << TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT) | \ + (tpc_out_fifo_busy << TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT) | \ + (tpc_blend_busy << TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT) | \ + (tf_tw_rts << TPC_CNTL_STATUS_TF_TW_RTS_SHIFT) | \ + (tf_tw_state_rts << TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT) | \ + (tf_tw_rtr << TPC_CNTL_STATUS_TF_TW_RTR_SHIFT) | \ + (tw_ta_rts << TPC_CNTL_STATUS_TW_TA_RTS_SHIFT) | \ + (tw_ta_tt_rts << TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT) | \ + (tw_ta_last_rts << TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT) | \ + (tw_ta_rtr << TPC_CNTL_STATUS_TW_TA_RTR_SHIFT) | \ + (ta_tb_rts << TPC_CNTL_STATUS_TA_TB_RTS_SHIFT) | \ + (ta_tb_tt_rts << TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT) | \ + (ta_tb_rtr << TPC_CNTL_STATUS_TA_TB_RTR_SHIFT) | \ + (ta_tf_rts << TPC_CNTL_STATUS_TA_TF_RTS_SHIFT) | \ + (ta_tf_tc_fifo_ren << TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT) | \ + (tp_sq_dec << TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT) | \ + (tpc_busy << TPC_CNTL_STATUS_TPC_BUSY_SHIFT)) + +#define TPC_CNTL_STATUS_GET_TPC_INPUT_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_TC_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_STATE_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_FETCH_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_WALKER_PIPE_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_WALK_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_WALKER_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_ALIGNER_PIPE_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_ALIGN_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_ALIGNER_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_RR_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_BLEND_PIPE_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_OUT_FIFO_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_BLEND_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT) +#define TPC_CNTL_STATUS_GET_TF_TW_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_RTS_MASK) >> TPC_CNTL_STATUS_TF_TW_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TF_TW_STATE_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK) >> TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TF_TW_RTR(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TF_TW_RTR_MASK) >> TPC_CNTL_STATUS_TF_TW_RTR_SHIFT) +#define TPC_CNTL_STATUS_GET_TW_TA_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TW_TA_TT_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TW_TA_LAST_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK) >> TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TW_TA_RTR(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TW_TA_RTR_MASK) >> TPC_CNTL_STATUS_TW_TA_RTR_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TB_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_RTS_MASK) >> TPC_CNTL_STATUS_TA_TB_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TB_TT_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK) >> TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TB_RTR(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TB_RTR_MASK) >> TPC_CNTL_STATUS_TA_TB_RTR_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TF_RTS(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TF_RTS_MASK) >> TPC_CNTL_STATUS_TA_TF_RTS_SHIFT) +#define TPC_CNTL_STATUS_GET_TA_TF_TC_FIFO_REN(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK) >> TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT) +#define TPC_CNTL_STATUS_GET_TP_SQ_DEC(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TP_SQ_DEC_MASK) >> TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT) +#define TPC_CNTL_STATUS_GET_TPC_BUSY(tpc_cntl_status) \ + ((tpc_cntl_status & TPC_CNTL_STATUS_TPC_BUSY_MASK) >> TPC_CNTL_STATUS_TPC_BUSY_SHIFT) + +#define TPC_CNTL_STATUS_SET_TPC_INPUT_BUSY(tpc_cntl_status_reg, tpc_input_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_INPUT_BUSY_MASK) | (tpc_input_busy << TPC_CNTL_STATUS_TPC_INPUT_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_TC_FIFO_BUSY(tpc_cntl_status_reg, tpc_tc_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_MASK) | (tpc_tc_fifo_busy << TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_STATE_FIFO_BUSY(tpc_cntl_status_reg, tpc_state_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_MASK) | (tpc_state_fifo_busy << TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_FETCH_FIFO_BUSY(tpc_cntl_status_reg, tpc_fetch_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_MASK) | (tpc_fetch_fifo_busy << TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_WALKER_PIPE_BUSY(tpc_cntl_status_reg, tpc_walker_pipe_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_MASK) | (tpc_walker_pipe_busy << TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_WALK_FIFO_BUSY(tpc_cntl_status_reg, tpc_walk_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_MASK) | (tpc_walk_fifo_busy << TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_WALKER_BUSY(tpc_cntl_status_reg, tpc_walker_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_WALKER_BUSY_MASK) | (tpc_walker_busy << TPC_CNTL_STATUS_TPC_WALKER_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_ALIGNER_PIPE_BUSY(tpc_cntl_status_reg, tpc_aligner_pipe_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_MASK) | (tpc_aligner_pipe_busy << TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_ALIGN_FIFO_BUSY(tpc_cntl_status_reg, tpc_align_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_MASK) | (tpc_align_fifo_busy << TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_ALIGNER_BUSY(tpc_cntl_status_reg, tpc_aligner_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_MASK) | (tpc_aligner_busy << TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_RR_FIFO_BUSY(tpc_cntl_status_reg, tpc_rr_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_MASK) | (tpc_rr_fifo_busy << TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_BLEND_PIPE_BUSY(tpc_cntl_status_reg, tpc_blend_pipe_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_MASK) | (tpc_blend_pipe_busy << TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_OUT_FIFO_BUSY(tpc_cntl_status_reg, tpc_out_fifo_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_MASK) | (tpc_out_fifo_busy << TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_BLEND_BUSY(tpc_cntl_status_reg, tpc_blend_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BLEND_BUSY_MASK) | (tpc_blend_busy << TPC_CNTL_STATUS_TPC_BLEND_BUSY_SHIFT) +#define TPC_CNTL_STATUS_SET_TF_TW_RTS(tpc_cntl_status_reg, tf_tw_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_RTS_MASK) | (tf_tw_rts << TPC_CNTL_STATUS_TF_TW_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TF_TW_STATE_RTS(tpc_cntl_status_reg, tf_tw_state_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_STATE_RTS_MASK) | (tf_tw_state_rts << TPC_CNTL_STATUS_TF_TW_STATE_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TF_TW_RTR(tpc_cntl_status_reg, tf_tw_rtr) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TF_TW_RTR_MASK) | (tf_tw_rtr << TPC_CNTL_STATUS_TF_TW_RTR_SHIFT) +#define TPC_CNTL_STATUS_SET_TW_TA_RTS(tpc_cntl_status_reg, tw_ta_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_RTS_MASK) | (tw_ta_rts << TPC_CNTL_STATUS_TW_TA_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TW_TA_TT_RTS(tpc_cntl_status_reg, tw_ta_tt_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_TT_RTS_MASK) | (tw_ta_tt_rts << TPC_CNTL_STATUS_TW_TA_TT_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TW_TA_LAST_RTS(tpc_cntl_status_reg, tw_ta_last_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_LAST_RTS_MASK) | (tw_ta_last_rts << TPC_CNTL_STATUS_TW_TA_LAST_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TW_TA_RTR(tpc_cntl_status_reg, tw_ta_rtr) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TW_TA_RTR_MASK) | (tw_ta_rtr << TPC_CNTL_STATUS_TW_TA_RTR_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TB_RTS(tpc_cntl_status_reg, ta_tb_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_RTS_MASK) | (ta_tb_rts << TPC_CNTL_STATUS_TA_TB_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TB_TT_RTS(tpc_cntl_status_reg, ta_tb_tt_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_TT_RTS_MASK) | (ta_tb_tt_rts << TPC_CNTL_STATUS_TA_TB_TT_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TB_RTR(tpc_cntl_status_reg, ta_tb_rtr) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TB_RTR_MASK) | (ta_tb_rtr << TPC_CNTL_STATUS_TA_TB_RTR_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TF_RTS(tpc_cntl_status_reg, ta_tf_rts) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TF_RTS_MASK) | (ta_tf_rts << TPC_CNTL_STATUS_TA_TF_RTS_SHIFT) +#define TPC_CNTL_STATUS_SET_TA_TF_TC_FIFO_REN(tpc_cntl_status_reg, ta_tf_tc_fifo_ren) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_MASK) | (ta_tf_tc_fifo_ren << TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SHIFT) +#define TPC_CNTL_STATUS_SET_TP_SQ_DEC(tpc_cntl_status_reg, tp_sq_dec) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TP_SQ_DEC_MASK) | (tp_sq_dec << TPC_CNTL_STATUS_TP_SQ_DEC_SHIFT) +#define TPC_CNTL_STATUS_SET_TPC_BUSY(tpc_cntl_status_reg, tpc_busy) \ + tpc_cntl_status_reg = (tpc_cntl_status_reg & ~TPC_CNTL_STATUS_TPC_BUSY_MASK) | (tpc_busy << TPC_CNTL_STATUS_TPC_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tpc_cntl_status_t { + unsigned int tpc_input_busy : TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE; + unsigned int tpc_tc_fifo_busy : TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE; + unsigned int tpc_state_fifo_busy : TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE; + unsigned int tpc_fetch_fifo_busy : TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE; + unsigned int tpc_walker_pipe_busy : TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE; + unsigned int tpc_walk_fifo_busy : TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE; + unsigned int tpc_walker_busy : TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_aligner_pipe_busy : TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE; + unsigned int tpc_align_fifo_busy : TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE; + unsigned int tpc_aligner_busy : TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_rr_fifo_busy : TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE; + unsigned int tpc_blend_pipe_busy : TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE; + unsigned int tpc_out_fifo_busy : TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE; + unsigned int tpc_blend_busy : TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE; + unsigned int tf_tw_rts : TPC_CNTL_STATUS_TF_TW_RTS_SIZE; + unsigned int tf_tw_state_rts : TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE; + unsigned int : 1; + unsigned int tf_tw_rtr : TPC_CNTL_STATUS_TF_TW_RTR_SIZE; + unsigned int tw_ta_rts : TPC_CNTL_STATUS_TW_TA_RTS_SIZE; + unsigned int tw_ta_tt_rts : TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE; + unsigned int tw_ta_last_rts : TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE; + unsigned int tw_ta_rtr : TPC_CNTL_STATUS_TW_TA_RTR_SIZE; + unsigned int ta_tb_rts : TPC_CNTL_STATUS_TA_TB_RTS_SIZE; + unsigned int ta_tb_tt_rts : TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE; + unsigned int : 1; + unsigned int ta_tb_rtr : TPC_CNTL_STATUS_TA_TB_RTR_SIZE; + unsigned int ta_tf_rts : TPC_CNTL_STATUS_TA_TF_RTS_SIZE; + unsigned int ta_tf_tc_fifo_ren : TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE; + unsigned int tp_sq_dec : TPC_CNTL_STATUS_TP_SQ_DEC_SIZE; + unsigned int tpc_busy : TPC_CNTL_STATUS_TPC_BUSY_SIZE; + } tpc_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _tpc_cntl_status_t { + unsigned int tpc_busy : TPC_CNTL_STATUS_TPC_BUSY_SIZE; + unsigned int tp_sq_dec : TPC_CNTL_STATUS_TP_SQ_DEC_SIZE; + unsigned int ta_tf_tc_fifo_ren : TPC_CNTL_STATUS_TA_TF_TC_FIFO_REN_SIZE; + unsigned int ta_tf_rts : TPC_CNTL_STATUS_TA_TF_RTS_SIZE; + unsigned int ta_tb_rtr : TPC_CNTL_STATUS_TA_TB_RTR_SIZE; + unsigned int : 1; + unsigned int ta_tb_tt_rts : TPC_CNTL_STATUS_TA_TB_TT_RTS_SIZE; + unsigned int ta_tb_rts : TPC_CNTL_STATUS_TA_TB_RTS_SIZE; + unsigned int tw_ta_rtr : TPC_CNTL_STATUS_TW_TA_RTR_SIZE; + unsigned int tw_ta_last_rts : TPC_CNTL_STATUS_TW_TA_LAST_RTS_SIZE; + unsigned int tw_ta_tt_rts : TPC_CNTL_STATUS_TW_TA_TT_RTS_SIZE; + unsigned int tw_ta_rts : TPC_CNTL_STATUS_TW_TA_RTS_SIZE; + unsigned int tf_tw_rtr : TPC_CNTL_STATUS_TF_TW_RTR_SIZE; + unsigned int : 1; + unsigned int tf_tw_state_rts : TPC_CNTL_STATUS_TF_TW_STATE_RTS_SIZE; + unsigned int tf_tw_rts : TPC_CNTL_STATUS_TF_TW_RTS_SIZE; + unsigned int tpc_blend_busy : TPC_CNTL_STATUS_TPC_BLEND_BUSY_SIZE; + unsigned int tpc_out_fifo_busy : TPC_CNTL_STATUS_TPC_OUT_FIFO_BUSY_SIZE; + unsigned int tpc_blend_pipe_busy : TPC_CNTL_STATUS_TPC_BLEND_PIPE_BUSY_SIZE; + unsigned int tpc_rr_fifo_busy : TPC_CNTL_STATUS_TPC_RR_FIFO_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_aligner_busy : TPC_CNTL_STATUS_TPC_ALIGNER_BUSY_SIZE; + unsigned int tpc_align_fifo_busy : TPC_CNTL_STATUS_TPC_ALIGN_FIFO_BUSY_SIZE; + unsigned int tpc_aligner_pipe_busy : TPC_CNTL_STATUS_TPC_ALIGNER_PIPE_BUSY_SIZE; + unsigned int : 1; + unsigned int tpc_walker_busy : TPC_CNTL_STATUS_TPC_WALKER_BUSY_SIZE; + unsigned int tpc_walk_fifo_busy : TPC_CNTL_STATUS_TPC_WALK_FIFO_BUSY_SIZE; + unsigned int tpc_walker_pipe_busy : TPC_CNTL_STATUS_TPC_WALKER_PIPE_BUSY_SIZE; + unsigned int tpc_fetch_fifo_busy : TPC_CNTL_STATUS_TPC_FETCH_FIFO_BUSY_SIZE; + unsigned int tpc_state_fifo_busy : TPC_CNTL_STATUS_TPC_STATE_FIFO_BUSY_SIZE; + unsigned int tpc_tc_fifo_busy : TPC_CNTL_STATUS_TPC_TC_FIFO_BUSY_SIZE; + unsigned int tpc_input_busy : TPC_CNTL_STATUS_TPC_INPUT_BUSY_SIZE; + } tpc_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + tpc_cntl_status_t f; +} tpc_cntl_status_u; + + +/* + * TPC_DEBUG0 struct + */ + +#define TPC_DEBUG0_LOD_CNTL_SIZE 2 +#define TPC_DEBUG0_IC_CTR_SIZE 2 +#define TPC_DEBUG0_WALKER_CNTL_SIZE 4 +#define TPC_DEBUG0_ALIGNER_CNTL_SIZE 3 +#define TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE 1 +#define TPC_DEBUG0_WALKER_STATE_SIZE 10 +#define TPC_DEBUG0_ALIGNER_STATE_SIZE 2 +#define TPC_DEBUG0_REG_CLK_EN_SIZE 1 +#define TPC_DEBUG0_TPC_CLK_EN_SIZE 1 +#define TPC_DEBUG0_SQ_TP_WAKEUP_SIZE 1 + +#define TPC_DEBUG0_LOD_CNTL_SHIFT 0 +#define TPC_DEBUG0_IC_CTR_SHIFT 2 +#define TPC_DEBUG0_WALKER_CNTL_SHIFT 4 +#define TPC_DEBUG0_ALIGNER_CNTL_SHIFT 8 +#define TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT 12 +#define TPC_DEBUG0_WALKER_STATE_SHIFT 16 +#define TPC_DEBUG0_ALIGNER_STATE_SHIFT 26 +#define TPC_DEBUG0_REG_CLK_EN_SHIFT 29 +#define TPC_DEBUG0_TPC_CLK_EN_SHIFT 30 +#define TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT 31 + +#define TPC_DEBUG0_LOD_CNTL_MASK 0x00000003 +#define TPC_DEBUG0_IC_CTR_MASK 0x0000000c +#define TPC_DEBUG0_WALKER_CNTL_MASK 0x000000f0 +#define TPC_DEBUG0_ALIGNER_CNTL_MASK 0x00000700 +#define TPC_DEBUG0_PREV_TC_STATE_VALID_MASK 0x00001000 +#define TPC_DEBUG0_WALKER_STATE_MASK 0x03ff0000 +#define TPC_DEBUG0_ALIGNER_STATE_MASK 0x0c000000 +#define TPC_DEBUG0_REG_CLK_EN_MASK 0x20000000 +#define TPC_DEBUG0_TPC_CLK_EN_MASK 0x40000000 +#define TPC_DEBUG0_SQ_TP_WAKEUP_MASK 0x80000000 + +#define TPC_DEBUG0_MASK \ + (TPC_DEBUG0_LOD_CNTL_MASK | \ + TPC_DEBUG0_IC_CTR_MASK | \ + TPC_DEBUG0_WALKER_CNTL_MASK | \ + TPC_DEBUG0_ALIGNER_CNTL_MASK | \ + TPC_DEBUG0_PREV_TC_STATE_VALID_MASK | \ + TPC_DEBUG0_WALKER_STATE_MASK | \ + TPC_DEBUG0_ALIGNER_STATE_MASK | \ + TPC_DEBUG0_REG_CLK_EN_MASK | \ + TPC_DEBUG0_TPC_CLK_EN_MASK | \ + TPC_DEBUG0_SQ_TP_WAKEUP_MASK) + +#define TPC_DEBUG0(lod_cntl, ic_ctr, walker_cntl, aligner_cntl, prev_tc_state_valid, walker_state, aligner_state, reg_clk_en, tpc_clk_en, sq_tp_wakeup) \ + ((lod_cntl << TPC_DEBUG0_LOD_CNTL_SHIFT) | \ + (ic_ctr << TPC_DEBUG0_IC_CTR_SHIFT) | \ + (walker_cntl << TPC_DEBUG0_WALKER_CNTL_SHIFT) | \ + (aligner_cntl << TPC_DEBUG0_ALIGNER_CNTL_SHIFT) | \ + (prev_tc_state_valid << TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT) | \ + (walker_state << TPC_DEBUG0_WALKER_STATE_SHIFT) | \ + (aligner_state << TPC_DEBUG0_ALIGNER_STATE_SHIFT) | \ + (reg_clk_en << TPC_DEBUG0_REG_CLK_EN_SHIFT) | \ + (tpc_clk_en << TPC_DEBUG0_TPC_CLK_EN_SHIFT) | \ + (sq_tp_wakeup << TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT)) + +#define TPC_DEBUG0_GET_LOD_CNTL(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_LOD_CNTL_MASK) >> TPC_DEBUG0_LOD_CNTL_SHIFT) +#define TPC_DEBUG0_GET_IC_CTR(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_IC_CTR_MASK) >> TPC_DEBUG0_IC_CTR_SHIFT) +#define TPC_DEBUG0_GET_WALKER_CNTL(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_WALKER_CNTL_MASK) >> TPC_DEBUG0_WALKER_CNTL_SHIFT) +#define TPC_DEBUG0_GET_ALIGNER_CNTL(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_ALIGNER_CNTL_MASK) >> TPC_DEBUG0_ALIGNER_CNTL_SHIFT) +#define TPC_DEBUG0_GET_PREV_TC_STATE_VALID(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_PREV_TC_STATE_VALID_MASK) >> TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT) +#define TPC_DEBUG0_GET_WALKER_STATE(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_WALKER_STATE_MASK) >> TPC_DEBUG0_WALKER_STATE_SHIFT) +#define TPC_DEBUG0_GET_ALIGNER_STATE(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_ALIGNER_STATE_MASK) >> TPC_DEBUG0_ALIGNER_STATE_SHIFT) +#define TPC_DEBUG0_GET_REG_CLK_EN(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_REG_CLK_EN_MASK) >> TPC_DEBUG0_REG_CLK_EN_SHIFT) +#define TPC_DEBUG0_GET_TPC_CLK_EN(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_TPC_CLK_EN_MASK) >> TPC_DEBUG0_TPC_CLK_EN_SHIFT) +#define TPC_DEBUG0_GET_SQ_TP_WAKEUP(tpc_debug0) \ + ((tpc_debug0 & TPC_DEBUG0_SQ_TP_WAKEUP_MASK) >> TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT) + +#define TPC_DEBUG0_SET_LOD_CNTL(tpc_debug0_reg, lod_cntl) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_LOD_CNTL_MASK) | (lod_cntl << TPC_DEBUG0_LOD_CNTL_SHIFT) +#define TPC_DEBUG0_SET_IC_CTR(tpc_debug0_reg, ic_ctr) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_IC_CTR_MASK) | (ic_ctr << TPC_DEBUG0_IC_CTR_SHIFT) +#define TPC_DEBUG0_SET_WALKER_CNTL(tpc_debug0_reg, walker_cntl) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_WALKER_CNTL_MASK) | (walker_cntl << TPC_DEBUG0_WALKER_CNTL_SHIFT) +#define TPC_DEBUG0_SET_ALIGNER_CNTL(tpc_debug0_reg, aligner_cntl) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_ALIGNER_CNTL_MASK) | (aligner_cntl << TPC_DEBUG0_ALIGNER_CNTL_SHIFT) +#define TPC_DEBUG0_SET_PREV_TC_STATE_VALID(tpc_debug0_reg, prev_tc_state_valid) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_PREV_TC_STATE_VALID_MASK) | (prev_tc_state_valid << TPC_DEBUG0_PREV_TC_STATE_VALID_SHIFT) +#define TPC_DEBUG0_SET_WALKER_STATE(tpc_debug0_reg, walker_state) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_WALKER_STATE_MASK) | (walker_state << TPC_DEBUG0_WALKER_STATE_SHIFT) +#define TPC_DEBUG0_SET_ALIGNER_STATE(tpc_debug0_reg, aligner_state) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_ALIGNER_STATE_MASK) | (aligner_state << TPC_DEBUG0_ALIGNER_STATE_SHIFT) +#define TPC_DEBUG0_SET_REG_CLK_EN(tpc_debug0_reg, reg_clk_en) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_REG_CLK_EN_MASK) | (reg_clk_en << TPC_DEBUG0_REG_CLK_EN_SHIFT) +#define TPC_DEBUG0_SET_TPC_CLK_EN(tpc_debug0_reg, tpc_clk_en) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_TPC_CLK_EN_MASK) | (tpc_clk_en << TPC_DEBUG0_TPC_CLK_EN_SHIFT) +#define TPC_DEBUG0_SET_SQ_TP_WAKEUP(tpc_debug0_reg, sq_tp_wakeup) \ + tpc_debug0_reg = (tpc_debug0_reg & ~TPC_DEBUG0_SQ_TP_WAKEUP_MASK) | (sq_tp_wakeup << TPC_DEBUG0_SQ_TP_WAKEUP_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tpc_debug0_t { + unsigned int lod_cntl : TPC_DEBUG0_LOD_CNTL_SIZE; + unsigned int ic_ctr : TPC_DEBUG0_IC_CTR_SIZE; + unsigned int walker_cntl : TPC_DEBUG0_WALKER_CNTL_SIZE; + unsigned int aligner_cntl : TPC_DEBUG0_ALIGNER_CNTL_SIZE; + unsigned int : 1; + unsigned int prev_tc_state_valid : TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE; + unsigned int : 3; + unsigned int walker_state : TPC_DEBUG0_WALKER_STATE_SIZE; + unsigned int aligner_state : TPC_DEBUG0_ALIGNER_STATE_SIZE; + unsigned int : 1; + unsigned int reg_clk_en : TPC_DEBUG0_REG_CLK_EN_SIZE; + unsigned int tpc_clk_en : TPC_DEBUG0_TPC_CLK_EN_SIZE; + unsigned int sq_tp_wakeup : TPC_DEBUG0_SQ_TP_WAKEUP_SIZE; + } tpc_debug0_t; + +#else // !BIGENDIAN_OS + + typedef struct _tpc_debug0_t { + unsigned int sq_tp_wakeup : TPC_DEBUG0_SQ_TP_WAKEUP_SIZE; + unsigned int tpc_clk_en : TPC_DEBUG0_TPC_CLK_EN_SIZE; + unsigned int reg_clk_en : TPC_DEBUG0_REG_CLK_EN_SIZE; + unsigned int : 1; + unsigned int aligner_state : TPC_DEBUG0_ALIGNER_STATE_SIZE; + unsigned int walker_state : TPC_DEBUG0_WALKER_STATE_SIZE; + unsigned int : 3; + unsigned int prev_tc_state_valid : TPC_DEBUG0_PREV_TC_STATE_VALID_SIZE; + unsigned int : 1; + unsigned int aligner_cntl : TPC_DEBUG0_ALIGNER_CNTL_SIZE; + unsigned int walker_cntl : TPC_DEBUG0_WALKER_CNTL_SIZE; + unsigned int ic_ctr : TPC_DEBUG0_IC_CTR_SIZE; + unsigned int lod_cntl : TPC_DEBUG0_LOD_CNTL_SIZE; + } tpc_debug0_t; + +#endif + +typedef union { + unsigned int val : 32; + tpc_debug0_t f; +} tpc_debug0_u; + + +/* + * TPC_DEBUG1 struct + */ + +#define TPC_DEBUG1_UNUSED_SIZE 1 + +#define TPC_DEBUG1_UNUSED_SHIFT 0 + +#define TPC_DEBUG1_UNUSED_MASK 0x00000001 + +#define TPC_DEBUG1_MASK \ + (TPC_DEBUG1_UNUSED_MASK) + +#define TPC_DEBUG1(unused) \ + ((unused << TPC_DEBUG1_UNUSED_SHIFT)) + +#define TPC_DEBUG1_GET_UNUSED(tpc_debug1) \ + ((tpc_debug1 & TPC_DEBUG1_UNUSED_MASK) >> TPC_DEBUG1_UNUSED_SHIFT) + +#define TPC_DEBUG1_SET_UNUSED(tpc_debug1_reg, unused) \ + tpc_debug1_reg = (tpc_debug1_reg & ~TPC_DEBUG1_UNUSED_MASK) | (unused << TPC_DEBUG1_UNUSED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tpc_debug1_t { + unsigned int unused : TPC_DEBUG1_UNUSED_SIZE; + unsigned int : 31; + } tpc_debug1_t; + +#else // !BIGENDIAN_OS + + typedef struct _tpc_debug1_t { + unsigned int : 31; + unsigned int unused : TPC_DEBUG1_UNUSED_SIZE; + } tpc_debug1_t; + +#endif + +typedef union { + unsigned int val : 32; + tpc_debug1_t f; +} tpc_debug1_u; + + +/* + * TPC_CHICKEN struct + */ + +#define TPC_CHICKEN_BLEND_PRECISION_SIZE 1 +#define TPC_CHICKEN_SPARE_SIZE 31 + +#define TPC_CHICKEN_BLEND_PRECISION_SHIFT 0 +#define TPC_CHICKEN_SPARE_SHIFT 1 + +#define TPC_CHICKEN_BLEND_PRECISION_MASK 0x00000001 +#define TPC_CHICKEN_SPARE_MASK 0xfffffffe + +#define TPC_CHICKEN_MASK \ + (TPC_CHICKEN_BLEND_PRECISION_MASK | \ + TPC_CHICKEN_SPARE_MASK) + +#define TPC_CHICKEN(blend_precision, spare) \ + ((blend_precision << TPC_CHICKEN_BLEND_PRECISION_SHIFT) | \ + (spare << TPC_CHICKEN_SPARE_SHIFT)) + +#define TPC_CHICKEN_GET_BLEND_PRECISION(tpc_chicken) \ + ((tpc_chicken & TPC_CHICKEN_BLEND_PRECISION_MASK) >> TPC_CHICKEN_BLEND_PRECISION_SHIFT) +#define TPC_CHICKEN_GET_SPARE(tpc_chicken) \ + ((tpc_chicken & TPC_CHICKEN_SPARE_MASK) >> TPC_CHICKEN_SPARE_SHIFT) + +#define TPC_CHICKEN_SET_BLEND_PRECISION(tpc_chicken_reg, blend_precision) \ + tpc_chicken_reg = (tpc_chicken_reg & ~TPC_CHICKEN_BLEND_PRECISION_MASK) | (blend_precision << TPC_CHICKEN_BLEND_PRECISION_SHIFT) +#define TPC_CHICKEN_SET_SPARE(tpc_chicken_reg, spare) \ + tpc_chicken_reg = (tpc_chicken_reg & ~TPC_CHICKEN_SPARE_MASK) | (spare << TPC_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tpc_chicken_t { + unsigned int blend_precision : TPC_CHICKEN_BLEND_PRECISION_SIZE; + unsigned int spare : TPC_CHICKEN_SPARE_SIZE; + } tpc_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tpc_chicken_t { + unsigned int spare : TPC_CHICKEN_SPARE_SIZE; + unsigned int blend_precision : TPC_CHICKEN_BLEND_PRECISION_SIZE; + } tpc_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tpc_chicken_t f; +} tpc_chicken_u; + + +/* + * TP0_CNTL_STATUS struct + */ + +#define TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_TT_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE 1 +#define TP0_CNTL_STATUS_IN_LC_RTS_SIZE 1 +#define TP0_CNTL_STATUS_LC_LA_RTS_SIZE 1 +#define TP0_CNTL_STATUS_LA_FL_RTS_SIZE 1 +#define TP0_CNTL_STATUS_FL_TA_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TA_FA_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_FA_AL_RTS_SIZE 1 +#define TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_AL_TF_RTS_SIZE 1 +#define TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TF_TB_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TB_TT_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE 1 +#define TP0_CNTL_STATUS_TB_TO_RTS_SIZE 1 +#define TP0_CNTL_STATUS_TP_BUSY_SIZE 1 + +#define TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT 0 +#define TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT 1 +#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT 2 +#define TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT 3 +#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT 4 +#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT 5 +#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT 6 +#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT 7 +#define TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT 8 +#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT 9 +#define TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT 10 +#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT 11 +#define TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT 12 +#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT 13 +#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT 14 +#define TP0_CNTL_STATUS_IN_LC_RTS_SHIFT 16 +#define TP0_CNTL_STATUS_LC_LA_RTS_SHIFT 17 +#define TP0_CNTL_STATUS_LA_FL_RTS_SHIFT 18 +#define TP0_CNTL_STATUS_FL_TA_RTS_SHIFT 19 +#define TP0_CNTL_STATUS_TA_FA_RTS_SHIFT 20 +#define TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT 21 +#define TP0_CNTL_STATUS_FA_AL_RTS_SHIFT 22 +#define TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT 23 +#define TP0_CNTL_STATUS_AL_TF_RTS_SHIFT 24 +#define TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT 25 +#define TP0_CNTL_STATUS_TF_TB_RTS_SHIFT 26 +#define TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT 27 +#define TP0_CNTL_STATUS_TB_TT_RTS_SHIFT 28 +#define TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT 29 +#define TP0_CNTL_STATUS_TB_TO_RTS_SHIFT 30 +#define TP0_CNTL_STATUS_TP_BUSY_SHIFT 31 + +#define TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK 0x00000001 +#define TP0_CNTL_STATUS_TP_LOD_BUSY_MASK 0x00000002 +#define TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK 0x00000004 +#define TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK 0x00000008 +#define TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK 0x00000010 +#define TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK 0x00000020 +#define TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK 0x00000040 +#define TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK 0x00000080 +#define TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK 0x00000100 +#define TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK 0x00000200 +#define TP0_CNTL_STATUS_TP_TT_BUSY_MASK 0x00000400 +#define TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK 0x00000800 +#define TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK 0x00001000 +#define TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK 0x00002000 +#define TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK 0x00004000 +#define TP0_CNTL_STATUS_IN_LC_RTS_MASK 0x00010000 +#define TP0_CNTL_STATUS_LC_LA_RTS_MASK 0x00020000 +#define TP0_CNTL_STATUS_LA_FL_RTS_MASK 0x00040000 +#define TP0_CNTL_STATUS_FL_TA_RTS_MASK 0x00080000 +#define TP0_CNTL_STATUS_TA_FA_RTS_MASK 0x00100000 +#define TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK 0x00200000 +#define TP0_CNTL_STATUS_FA_AL_RTS_MASK 0x00400000 +#define TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK 0x00800000 +#define TP0_CNTL_STATUS_AL_TF_RTS_MASK 0x01000000 +#define TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK 0x02000000 +#define TP0_CNTL_STATUS_TF_TB_RTS_MASK 0x04000000 +#define TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK 0x08000000 +#define TP0_CNTL_STATUS_TB_TT_RTS_MASK 0x10000000 +#define TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK 0x20000000 +#define TP0_CNTL_STATUS_TB_TO_RTS_MASK 0x40000000 +#define TP0_CNTL_STATUS_TP_BUSY_MASK 0x80000000 + +#define TP0_CNTL_STATUS_MASK \ + (TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_LOD_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_TT_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK | \ + TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK | \ + TP0_CNTL_STATUS_IN_LC_RTS_MASK | \ + TP0_CNTL_STATUS_LC_LA_RTS_MASK | \ + TP0_CNTL_STATUS_LA_FL_RTS_MASK | \ + TP0_CNTL_STATUS_FL_TA_RTS_MASK | \ + TP0_CNTL_STATUS_TA_FA_RTS_MASK | \ + TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK | \ + TP0_CNTL_STATUS_FA_AL_RTS_MASK | \ + TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK | \ + TP0_CNTL_STATUS_AL_TF_RTS_MASK | \ + TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK | \ + TP0_CNTL_STATUS_TF_TB_RTS_MASK | \ + TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK | \ + TP0_CNTL_STATUS_TB_TT_RTS_MASK | \ + TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK | \ + TP0_CNTL_STATUS_TB_TO_RTS_MASK | \ + TP0_CNTL_STATUS_TP_BUSY_MASK) + +#define TP0_CNTL_STATUS(tp_input_busy, tp_lod_busy, tp_lod_fifo_busy, tp_addr_busy, tp_align_fifo_busy, tp_aligner_busy, tp_tc_fifo_busy, tp_rr_fifo_busy, tp_fetch_busy, tp_ch_blend_busy, tp_tt_busy, tp_hicolor_busy, tp_blend_busy, tp_out_fifo_busy, tp_output_busy, in_lc_rts, lc_la_rts, la_fl_rts, fl_ta_rts, ta_fa_rts, ta_fa_tt_rts, fa_al_rts, fa_al_tt_rts, al_tf_rts, al_tf_tt_rts, tf_tb_rts, tf_tb_tt_rts, tb_tt_rts, tb_tt_tt_reset, tb_to_rts, tp_busy) \ + ((tp_input_busy << TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT) | \ + (tp_lod_busy << TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT) | \ + (tp_lod_fifo_busy << TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT) | \ + (tp_addr_busy << TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT) | \ + (tp_align_fifo_busy << TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT) | \ + (tp_aligner_busy << TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT) | \ + (tp_tc_fifo_busy << TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT) | \ + (tp_rr_fifo_busy << TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT) | \ + (tp_fetch_busy << TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT) | \ + (tp_ch_blend_busy << TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT) | \ + (tp_tt_busy << TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT) | \ + (tp_hicolor_busy << TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT) | \ + (tp_blend_busy << TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT) | \ + (tp_out_fifo_busy << TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT) | \ + (tp_output_busy << TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT) | \ + (in_lc_rts << TP0_CNTL_STATUS_IN_LC_RTS_SHIFT) | \ + (lc_la_rts << TP0_CNTL_STATUS_LC_LA_RTS_SHIFT) | \ + (la_fl_rts << TP0_CNTL_STATUS_LA_FL_RTS_SHIFT) | \ + (fl_ta_rts << TP0_CNTL_STATUS_FL_TA_RTS_SHIFT) | \ + (ta_fa_rts << TP0_CNTL_STATUS_TA_FA_RTS_SHIFT) | \ + (ta_fa_tt_rts << TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT) | \ + (fa_al_rts << TP0_CNTL_STATUS_FA_AL_RTS_SHIFT) | \ + (fa_al_tt_rts << TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT) | \ + (al_tf_rts << TP0_CNTL_STATUS_AL_TF_RTS_SHIFT) | \ + (al_tf_tt_rts << TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT) | \ + (tf_tb_rts << TP0_CNTL_STATUS_TF_TB_RTS_SHIFT) | \ + (tf_tb_tt_rts << TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT) | \ + (tb_tt_rts << TP0_CNTL_STATUS_TB_TT_RTS_SHIFT) | \ + (tb_tt_tt_reset << TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT) | \ + (tb_to_rts << TP0_CNTL_STATUS_TB_TO_RTS_SHIFT) | \ + (tp_busy << TP0_CNTL_STATUS_TP_BUSY_SHIFT)) + +#define TP0_CNTL_STATUS_GET_TP_INPUT_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_LOD_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_LOD_BUSY_MASK) >> TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_LOD_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_ADDR_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_ALIGN_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_ALIGNER_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK) >> TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_TC_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_RR_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_FETCH_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK) >> TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_CH_BLEND_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK) >> TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_TT_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_TT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_HICOLOR_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK) >> TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_BLEND_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK) >> TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_OUT_FIFO_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK) >> TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_OUTPUT_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK) >> TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_GET_IN_LC_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_IN_LC_RTS_MASK) >> TP0_CNTL_STATUS_IN_LC_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_LC_LA_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_LC_LA_RTS_MASK) >> TP0_CNTL_STATUS_LC_LA_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_LA_FL_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_LA_FL_RTS_MASK) >> TP0_CNTL_STATUS_LA_FL_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_FL_TA_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_FL_TA_RTS_MASK) >> TP0_CNTL_STATUS_FL_TA_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TA_FA_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TA_FA_RTS_MASK) >> TP0_CNTL_STATUS_TA_FA_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TA_FA_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK) >> TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_FA_AL_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_FA_AL_RTS_MASK) >> TP0_CNTL_STATUS_FA_AL_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_FA_AL_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK) >> TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_AL_TF_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_AL_TF_RTS_MASK) >> TP0_CNTL_STATUS_AL_TF_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_AL_TF_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK) >> TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TF_TB_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TF_TB_RTS_MASK) >> TP0_CNTL_STATUS_TF_TB_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TF_TB_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK) >> TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TB_TT_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TT_RTS_MASK) >> TP0_CNTL_STATUS_TB_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TB_TT_TT_RESET(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK) >> TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT) +#define TP0_CNTL_STATUS_GET_TB_TO_RTS(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TB_TO_RTS_MASK) >> TP0_CNTL_STATUS_TB_TO_RTS_SHIFT) +#define TP0_CNTL_STATUS_GET_TP_BUSY(tp0_cntl_status) \ + ((tp0_cntl_status & TP0_CNTL_STATUS_TP_BUSY_MASK) >> TP0_CNTL_STATUS_TP_BUSY_SHIFT) + +#define TP0_CNTL_STATUS_SET_TP_INPUT_BUSY(tp0_cntl_status_reg, tp_input_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_INPUT_BUSY_MASK) | (tp_input_busy << TP0_CNTL_STATUS_TP_INPUT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_LOD_BUSY(tp0_cntl_status_reg, tp_lod_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_LOD_BUSY_MASK) | (tp_lod_busy << TP0_CNTL_STATUS_TP_LOD_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_LOD_FIFO_BUSY(tp0_cntl_status_reg, tp_lod_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_MASK) | (tp_lod_fifo_busy << TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_ADDR_BUSY(tp0_cntl_status_reg, tp_addr_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ADDR_BUSY_MASK) | (tp_addr_busy << TP0_CNTL_STATUS_TP_ADDR_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_ALIGN_FIFO_BUSY(tp0_cntl_status_reg, tp_align_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_MASK) | (tp_align_fifo_busy << TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_ALIGNER_BUSY(tp0_cntl_status_reg, tp_aligner_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_ALIGNER_BUSY_MASK) | (tp_aligner_busy << TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_TC_FIFO_BUSY(tp0_cntl_status_reg, tp_tc_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_MASK) | (tp_tc_fifo_busy << TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_RR_FIFO_BUSY(tp0_cntl_status_reg, tp_rr_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_MASK) | (tp_rr_fifo_busy << TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_FETCH_BUSY(tp0_cntl_status_reg, tp_fetch_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_FETCH_BUSY_MASK) | (tp_fetch_busy << TP0_CNTL_STATUS_TP_FETCH_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_CH_BLEND_BUSY(tp0_cntl_status_reg, tp_ch_blend_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_MASK) | (tp_ch_blend_busy << TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_TT_BUSY(tp0_cntl_status_reg, tp_tt_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_TT_BUSY_MASK) | (tp_tt_busy << TP0_CNTL_STATUS_TP_TT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_HICOLOR_BUSY(tp0_cntl_status_reg, tp_hicolor_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_HICOLOR_BUSY_MASK) | (tp_hicolor_busy << TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_BLEND_BUSY(tp0_cntl_status_reg, tp_blend_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_BLEND_BUSY_MASK) | (tp_blend_busy << TP0_CNTL_STATUS_TP_BLEND_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_OUT_FIFO_BUSY(tp0_cntl_status_reg, tp_out_fifo_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_MASK) | (tp_out_fifo_busy << TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_OUTPUT_BUSY(tp0_cntl_status_reg, tp_output_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_OUTPUT_BUSY_MASK) | (tp_output_busy << TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SHIFT) +#define TP0_CNTL_STATUS_SET_IN_LC_RTS(tp0_cntl_status_reg, in_lc_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_IN_LC_RTS_MASK) | (in_lc_rts << TP0_CNTL_STATUS_IN_LC_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_LC_LA_RTS(tp0_cntl_status_reg, lc_la_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_LC_LA_RTS_MASK) | (lc_la_rts << TP0_CNTL_STATUS_LC_LA_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_LA_FL_RTS(tp0_cntl_status_reg, la_fl_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_LA_FL_RTS_MASK) | (la_fl_rts << TP0_CNTL_STATUS_LA_FL_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_FL_TA_RTS(tp0_cntl_status_reg, fl_ta_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FL_TA_RTS_MASK) | (fl_ta_rts << TP0_CNTL_STATUS_FL_TA_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TA_FA_RTS(tp0_cntl_status_reg, ta_fa_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TA_FA_RTS_MASK) | (ta_fa_rts << TP0_CNTL_STATUS_TA_FA_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TA_FA_TT_RTS(tp0_cntl_status_reg, ta_fa_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TA_FA_TT_RTS_MASK) | (ta_fa_tt_rts << TP0_CNTL_STATUS_TA_FA_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_FA_AL_RTS(tp0_cntl_status_reg, fa_al_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FA_AL_RTS_MASK) | (fa_al_rts << TP0_CNTL_STATUS_FA_AL_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_FA_AL_TT_RTS(tp0_cntl_status_reg, fa_al_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_FA_AL_TT_RTS_MASK) | (fa_al_tt_rts << TP0_CNTL_STATUS_FA_AL_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_AL_TF_RTS(tp0_cntl_status_reg, al_tf_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_AL_TF_RTS_MASK) | (al_tf_rts << TP0_CNTL_STATUS_AL_TF_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_AL_TF_TT_RTS(tp0_cntl_status_reg, al_tf_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_AL_TF_TT_RTS_MASK) | (al_tf_tt_rts << TP0_CNTL_STATUS_AL_TF_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TF_TB_RTS(tp0_cntl_status_reg, tf_tb_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TF_TB_RTS_MASK) | (tf_tb_rts << TP0_CNTL_STATUS_TF_TB_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TF_TB_TT_RTS(tp0_cntl_status_reg, tf_tb_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TF_TB_TT_RTS_MASK) | (tf_tb_tt_rts << TP0_CNTL_STATUS_TF_TB_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TB_TT_RTS(tp0_cntl_status_reg, tb_tt_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TT_RTS_MASK) | (tb_tt_rts << TP0_CNTL_STATUS_TB_TT_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TB_TT_TT_RESET(tp0_cntl_status_reg, tb_tt_tt_reset) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TT_TT_RESET_MASK) | (tb_tt_tt_reset << TP0_CNTL_STATUS_TB_TT_TT_RESET_SHIFT) +#define TP0_CNTL_STATUS_SET_TB_TO_RTS(tp0_cntl_status_reg, tb_to_rts) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TB_TO_RTS_MASK) | (tb_to_rts << TP0_CNTL_STATUS_TB_TO_RTS_SHIFT) +#define TP0_CNTL_STATUS_SET_TP_BUSY(tp0_cntl_status_reg, tp_busy) \ + tp0_cntl_status_reg = (tp0_cntl_status_reg & ~TP0_CNTL_STATUS_TP_BUSY_MASK) | (tp_busy << TP0_CNTL_STATUS_TP_BUSY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_cntl_status_t { + unsigned int tp_input_busy : TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE; + unsigned int tp_lod_busy : TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE; + unsigned int tp_lod_fifo_busy : TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE; + unsigned int tp_addr_busy : TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE; + unsigned int tp_align_fifo_busy : TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE; + unsigned int tp_aligner_busy : TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE; + unsigned int tp_tc_fifo_busy : TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE; + unsigned int tp_rr_fifo_busy : TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE; + unsigned int tp_fetch_busy : TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE; + unsigned int tp_ch_blend_busy : TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE; + unsigned int tp_tt_busy : TP0_CNTL_STATUS_TP_TT_BUSY_SIZE; + unsigned int tp_hicolor_busy : TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE; + unsigned int tp_blend_busy : TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE; + unsigned int tp_out_fifo_busy : TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE; + unsigned int tp_output_busy : TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE; + unsigned int : 1; + unsigned int in_lc_rts : TP0_CNTL_STATUS_IN_LC_RTS_SIZE; + unsigned int lc_la_rts : TP0_CNTL_STATUS_LC_LA_RTS_SIZE; + unsigned int la_fl_rts : TP0_CNTL_STATUS_LA_FL_RTS_SIZE; + unsigned int fl_ta_rts : TP0_CNTL_STATUS_FL_TA_RTS_SIZE; + unsigned int ta_fa_rts : TP0_CNTL_STATUS_TA_FA_RTS_SIZE; + unsigned int ta_fa_tt_rts : TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE; + unsigned int fa_al_rts : TP0_CNTL_STATUS_FA_AL_RTS_SIZE; + unsigned int fa_al_tt_rts : TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE; + unsigned int al_tf_rts : TP0_CNTL_STATUS_AL_TF_RTS_SIZE; + unsigned int al_tf_tt_rts : TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE; + unsigned int tf_tb_rts : TP0_CNTL_STATUS_TF_TB_RTS_SIZE; + unsigned int tf_tb_tt_rts : TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE; + unsigned int tb_tt_rts : TP0_CNTL_STATUS_TB_TT_RTS_SIZE; + unsigned int tb_tt_tt_reset : TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE; + unsigned int tb_to_rts : TP0_CNTL_STATUS_TB_TO_RTS_SIZE; + unsigned int tp_busy : TP0_CNTL_STATUS_TP_BUSY_SIZE; + } tp0_cntl_status_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_cntl_status_t { + unsigned int tp_busy : TP0_CNTL_STATUS_TP_BUSY_SIZE; + unsigned int tb_to_rts : TP0_CNTL_STATUS_TB_TO_RTS_SIZE; + unsigned int tb_tt_tt_reset : TP0_CNTL_STATUS_TB_TT_TT_RESET_SIZE; + unsigned int tb_tt_rts : TP0_CNTL_STATUS_TB_TT_RTS_SIZE; + unsigned int tf_tb_tt_rts : TP0_CNTL_STATUS_TF_TB_TT_RTS_SIZE; + unsigned int tf_tb_rts : TP0_CNTL_STATUS_TF_TB_RTS_SIZE; + unsigned int al_tf_tt_rts : TP0_CNTL_STATUS_AL_TF_TT_RTS_SIZE; + unsigned int al_tf_rts : TP0_CNTL_STATUS_AL_TF_RTS_SIZE; + unsigned int fa_al_tt_rts : TP0_CNTL_STATUS_FA_AL_TT_RTS_SIZE; + unsigned int fa_al_rts : TP0_CNTL_STATUS_FA_AL_RTS_SIZE; + unsigned int ta_fa_tt_rts : TP0_CNTL_STATUS_TA_FA_TT_RTS_SIZE; + unsigned int ta_fa_rts : TP0_CNTL_STATUS_TA_FA_RTS_SIZE; + unsigned int fl_ta_rts : TP0_CNTL_STATUS_FL_TA_RTS_SIZE; + unsigned int la_fl_rts : TP0_CNTL_STATUS_LA_FL_RTS_SIZE; + unsigned int lc_la_rts : TP0_CNTL_STATUS_LC_LA_RTS_SIZE; + unsigned int in_lc_rts : TP0_CNTL_STATUS_IN_LC_RTS_SIZE; + unsigned int : 1; + unsigned int tp_output_busy : TP0_CNTL_STATUS_TP_OUTPUT_BUSY_SIZE; + unsigned int tp_out_fifo_busy : TP0_CNTL_STATUS_TP_OUT_FIFO_BUSY_SIZE; + unsigned int tp_blend_busy : TP0_CNTL_STATUS_TP_BLEND_BUSY_SIZE; + unsigned int tp_hicolor_busy : TP0_CNTL_STATUS_TP_HICOLOR_BUSY_SIZE; + unsigned int tp_tt_busy : TP0_CNTL_STATUS_TP_TT_BUSY_SIZE; + unsigned int tp_ch_blend_busy : TP0_CNTL_STATUS_TP_CH_BLEND_BUSY_SIZE; + unsigned int tp_fetch_busy : TP0_CNTL_STATUS_TP_FETCH_BUSY_SIZE; + unsigned int tp_rr_fifo_busy : TP0_CNTL_STATUS_TP_RR_FIFO_BUSY_SIZE; + unsigned int tp_tc_fifo_busy : TP0_CNTL_STATUS_TP_TC_FIFO_BUSY_SIZE; + unsigned int tp_aligner_busy : TP0_CNTL_STATUS_TP_ALIGNER_BUSY_SIZE; + unsigned int tp_align_fifo_busy : TP0_CNTL_STATUS_TP_ALIGN_FIFO_BUSY_SIZE; + unsigned int tp_addr_busy : TP0_CNTL_STATUS_TP_ADDR_BUSY_SIZE; + unsigned int tp_lod_fifo_busy : TP0_CNTL_STATUS_TP_LOD_FIFO_BUSY_SIZE; + unsigned int tp_lod_busy : TP0_CNTL_STATUS_TP_LOD_BUSY_SIZE; + unsigned int tp_input_busy : TP0_CNTL_STATUS_TP_INPUT_BUSY_SIZE; + } tp0_cntl_status_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_cntl_status_t f; +} tp0_cntl_status_u; + + +/* + * TP0_DEBUG struct + */ + +#define TP0_DEBUG_Q_LOD_CNTL_SIZE 2 +#define TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE 1 +#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE 17 +#define TP0_DEBUG_REG_CLK_EN_SIZE 1 +#define TP0_DEBUG_PERF_CLK_EN_SIZE 1 +#define TP0_DEBUG_TP_CLK_EN_SIZE 1 +#define TP0_DEBUG_Q_WALKER_CNTL_SIZE 4 +#define TP0_DEBUG_Q_ALIGNER_CNTL_SIZE 3 + +#define TP0_DEBUG_Q_LOD_CNTL_SHIFT 0 +#define TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT 3 +#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT 4 +#define TP0_DEBUG_REG_CLK_EN_SHIFT 21 +#define TP0_DEBUG_PERF_CLK_EN_SHIFT 22 +#define TP0_DEBUG_TP_CLK_EN_SHIFT 23 +#define TP0_DEBUG_Q_WALKER_CNTL_SHIFT 24 +#define TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT 28 + +#define TP0_DEBUG_Q_LOD_CNTL_MASK 0x00000003 +#define TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK 0x00000008 +#define TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK 0x001ffff0 +#define TP0_DEBUG_REG_CLK_EN_MASK 0x00200000 +#define TP0_DEBUG_PERF_CLK_EN_MASK 0x00400000 +#define TP0_DEBUG_TP_CLK_EN_MASK 0x00800000 +#define TP0_DEBUG_Q_WALKER_CNTL_MASK 0x0f000000 +#define TP0_DEBUG_Q_ALIGNER_CNTL_MASK 0x70000000 + +#define TP0_DEBUG_MASK \ + (TP0_DEBUG_Q_LOD_CNTL_MASK | \ + TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK | \ + TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK | \ + TP0_DEBUG_REG_CLK_EN_MASK | \ + TP0_DEBUG_PERF_CLK_EN_MASK | \ + TP0_DEBUG_TP_CLK_EN_MASK | \ + TP0_DEBUG_Q_WALKER_CNTL_MASK | \ + TP0_DEBUG_Q_ALIGNER_CNTL_MASK) + +#define TP0_DEBUG(q_lod_cntl, q_sq_tp_wakeup, fl_ta_addresser_cntl, reg_clk_en, perf_clk_en, tp_clk_en, q_walker_cntl, q_aligner_cntl) \ + ((q_lod_cntl << TP0_DEBUG_Q_LOD_CNTL_SHIFT) | \ + (q_sq_tp_wakeup << TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT) | \ + (fl_ta_addresser_cntl << TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT) | \ + (reg_clk_en << TP0_DEBUG_REG_CLK_EN_SHIFT) | \ + (perf_clk_en << TP0_DEBUG_PERF_CLK_EN_SHIFT) | \ + (tp_clk_en << TP0_DEBUG_TP_CLK_EN_SHIFT) | \ + (q_walker_cntl << TP0_DEBUG_Q_WALKER_CNTL_SHIFT) | \ + (q_aligner_cntl << TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT)) + +#define TP0_DEBUG_GET_Q_LOD_CNTL(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_Q_LOD_CNTL_MASK) >> TP0_DEBUG_Q_LOD_CNTL_SHIFT) +#define TP0_DEBUG_GET_Q_SQ_TP_WAKEUP(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK) >> TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT) +#define TP0_DEBUG_GET_FL_TA_ADDRESSER_CNTL(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK) >> TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT) +#define TP0_DEBUG_GET_REG_CLK_EN(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_REG_CLK_EN_MASK) >> TP0_DEBUG_REG_CLK_EN_SHIFT) +#define TP0_DEBUG_GET_PERF_CLK_EN(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_PERF_CLK_EN_MASK) >> TP0_DEBUG_PERF_CLK_EN_SHIFT) +#define TP0_DEBUG_GET_TP_CLK_EN(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_TP_CLK_EN_MASK) >> TP0_DEBUG_TP_CLK_EN_SHIFT) +#define TP0_DEBUG_GET_Q_WALKER_CNTL(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_Q_WALKER_CNTL_MASK) >> TP0_DEBUG_Q_WALKER_CNTL_SHIFT) +#define TP0_DEBUG_GET_Q_ALIGNER_CNTL(tp0_debug) \ + ((tp0_debug & TP0_DEBUG_Q_ALIGNER_CNTL_MASK) >> TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT) + +#define TP0_DEBUG_SET_Q_LOD_CNTL(tp0_debug_reg, q_lod_cntl) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_LOD_CNTL_MASK) | (q_lod_cntl << TP0_DEBUG_Q_LOD_CNTL_SHIFT) +#define TP0_DEBUG_SET_Q_SQ_TP_WAKEUP(tp0_debug_reg, q_sq_tp_wakeup) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_SQ_TP_WAKEUP_MASK) | (q_sq_tp_wakeup << TP0_DEBUG_Q_SQ_TP_WAKEUP_SHIFT) +#define TP0_DEBUG_SET_FL_TA_ADDRESSER_CNTL(tp0_debug_reg, fl_ta_addresser_cntl) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_FL_TA_ADDRESSER_CNTL_MASK) | (fl_ta_addresser_cntl << TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SHIFT) +#define TP0_DEBUG_SET_REG_CLK_EN(tp0_debug_reg, reg_clk_en) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_REG_CLK_EN_MASK) | (reg_clk_en << TP0_DEBUG_REG_CLK_EN_SHIFT) +#define TP0_DEBUG_SET_PERF_CLK_EN(tp0_debug_reg, perf_clk_en) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_PERF_CLK_EN_MASK) | (perf_clk_en << TP0_DEBUG_PERF_CLK_EN_SHIFT) +#define TP0_DEBUG_SET_TP_CLK_EN(tp0_debug_reg, tp_clk_en) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_TP_CLK_EN_MASK) | (tp_clk_en << TP0_DEBUG_TP_CLK_EN_SHIFT) +#define TP0_DEBUG_SET_Q_WALKER_CNTL(tp0_debug_reg, q_walker_cntl) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_WALKER_CNTL_MASK) | (q_walker_cntl << TP0_DEBUG_Q_WALKER_CNTL_SHIFT) +#define TP0_DEBUG_SET_Q_ALIGNER_CNTL(tp0_debug_reg, q_aligner_cntl) \ + tp0_debug_reg = (tp0_debug_reg & ~TP0_DEBUG_Q_ALIGNER_CNTL_MASK) | (q_aligner_cntl << TP0_DEBUG_Q_ALIGNER_CNTL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_debug_t { + unsigned int q_lod_cntl : TP0_DEBUG_Q_LOD_CNTL_SIZE; + unsigned int : 1; + unsigned int q_sq_tp_wakeup : TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE; + unsigned int fl_ta_addresser_cntl : TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE; + unsigned int reg_clk_en : TP0_DEBUG_REG_CLK_EN_SIZE; + unsigned int perf_clk_en : TP0_DEBUG_PERF_CLK_EN_SIZE; + unsigned int tp_clk_en : TP0_DEBUG_TP_CLK_EN_SIZE; + unsigned int q_walker_cntl : TP0_DEBUG_Q_WALKER_CNTL_SIZE; + unsigned int q_aligner_cntl : TP0_DEBUG_Q_ALIGNER_CNTL_SIZE; + unsigned int : 1; + } tp0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_debug_t { + unsigned int : 1; + unsigned int q_aligner_cntl : TP0_DEBUG_Q_ALIGNER_CNTL_SIZE; + unsigned int q_walker_cntl : TP0_DEBUG_Q_WALKER_CNTL_SIZE; + unsigned int tp_clk_en : TP0_DEBUG_TP_CLK_EN_SIZE; + unsigned int perf_clk_en : TP0_DEBUG_PERF_CLK_EN_SIZE; + unsigned int reg_clk_en : TP0_DEBUG_REG_CLK_EN_SIZE; + unsigned int fl_ta_addresser_cntl : TP0_DEBUG_FL_TA_ADDRESSER_CNTL_SIZE; + unsigned int q_sq_tp_wakeup : TP0_DEBUG_Q_SQ_TP_WAKEUP_SIZE; + unsigned int : 1; + unsigned int q_lod_cntl : TP0_DEBUG_Q_LOD_CNTL_SIZE; + } tp0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_debug_t f; +} tp0_debug_u; + + +/* + * TP0_CHICKEN struct + */ + +#define TP0_CHICKEN_TT_MODE_SIZE 1 +#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE 1 +#define TP0_CHICKEN_SPARE_SIZE 30 + +#define TP0_CHICKEN_TT_MODE_SHIFT 0 +#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT 1 +#define TP0_CHICKEN_SPARE_SHIFT 2 + +#define TP0_CHICKEN_TT_MODE_MASK 0x00000001 +#define TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK 0x00000002 +#define TP0_CHICKEN_SPARE_MASK 0xfffffffc + +#define TP0_CHICKEN_MASK \ + (TP0_CHICKEN_TT_MODE_MASK | \ + TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK | \ + TP0_CHICKEN_SPARE_MASK) + +#define TP0_CHICKEN(tt_mode, vfetch_address_mode, spare) \ + ((tt_mode << TP0_CHICKEN_TT_MODE_SHIFT) | \ + (vfetch_address_mode << TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT) | \ + (spare << TP0_CHICKEN_SPARE_SHIFT)) + +#define TP0_CHICKEN_GET_TT_MODE(tp0_chicken) \ + ((tp0_chicken & TP0_CHICKEN_TT_MODE_MASK) >> TP0_CHICKEN_TT_MODE_SHIFT) +#define TP0_CHICKEN_GET_VFETCH_ADDRESS_MODE(tp0_chicken) \ + ((tp0_chicken & TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK) >> TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT) +#define TP0_CHICKEN_GET_SPARE(tp0_chicken) \ + ((tp0_chicken & TP0_CHICKEN_SPARE_MASK) >> TP0_CHICKEN_SPARE_SHIFT) + +#define TP0_CHICKEN_SET_TT_MODE(tp0_chicken_reg, tt_mode) \ + tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_TT_MODE_MASK) | (tt_mode << TP0_CHICKEN_TT_MODE_SHIFT) +#define TP0_CHICKEN_SET_VFETCH_ADDRESS_MODE(tp0_chicken_reg, vfetch_address_mode) \ + tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_VFETCH_ADDRESS_MODE_MASK) | (vfetch_address_mode << TP0_CHICKEN_VFETCH_ADDRESS_MODE_SHIFT) +#define TP0_CHICKEN_SET_SPARE(tp0_chicken_reg, spare) \ + tp0_chicken_reg = (tp0_chicken_reg & ~TP0_CHICKEN_SPARE_MASK) | (spare << TP0_CHICKEN_SPARE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_chicken_t { + unsigned int tt_mode : TP0_CHICKEN_TT_MODE_SIZE; + unsigned int vfetch_address_mode : TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE; + unsigned int spare : TP0_CHICKEN_SPARE_SIZE; + } tp0_chicken_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_chicken_t { + unsigned int spare : TP0_CHICKEN_SPARE_SIZE; + unsigned int vfetch_address_mode : TP0_CHICKEN_VFETCH_ADDRESS_MODE_SIZE; + unsigned int tt_mode : TP0_CHICKEN_TT_MODE_SIZE; + } tp0_chicken_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_chicken_t f; +} tp0_chicken_u; + + +/* + * TP0_PERFCOUNTER0_SELECT struct + */ + +#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TP0_PERFCOUNTER0_SELECT_MASK \ + (TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TP0_PERFCOUNTER0_SELECT(perfcounter_select) \ + ((perfcounter_select << TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TP0_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tp0_perfcounter0_select) \ + ((tp0_perfcounter0_select & TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TP0_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tp0_perfcounter0_select_reg, perfcounter_select) \ + tp0_perfcounter0_select_reg = (tp0_perfcounter0_select_reg & ~TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_select_t { + unsigned int perfcounter_select : TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tp0_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TP0_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + } tp0_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter0_select_t f; +} tp0_perfcounter0_select_u; + + +/* + * TP0_PERFCOUNTER0_HI struct + */ + +#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16 + +#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TP0_PERFCOUNTER0_HI_MASK \ + (TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) + +#define TP0_PERFCOUNTER0_HI(perfcounter_hi) \ + ((perfcounter_hi << TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)) + +#define TP0_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tp0_perfcounter0_hi) \ + ((tp0_perfcounter0_hi & TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#define TP0_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tp0_perfcounter0_hi_reg, perfcounter_hi) \ + tp0_perfcounter0_hi_reg = (tp0_perfcounter0_hi_reg & ~TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_hi_t { + unsigned int perfcounter_hi : TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tp0_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TP0_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + } tp0_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter0_hi_t f; +} tp0_perfcounter0_hi_u; + + +/* + * TP0_PERFCOUNTER0_LOW struct + */ + +#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TP0_PERFCOUNTER0_LOW_MASK \ + (TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) + +#define TP0_PERFCOUNTER0_LOW(perfcounter_low) \ + ((perfcounter_low << TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TP0_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tp0_perfcounter0_low) \ + ((tp0_perfcounter0_low & TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TP0_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tp0_perfcounter0_low_reg, perfcounter_low) \ + tp0_perfcounter0_low_reg = (tp0_perfcounter0_low_reg & ~TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_low_t { + unsigned int perfcounter_low : TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tp0_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter0_low_t { + unsigned int perfcounter_low : TP0_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tp0_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter0_low_t f; +} tp0_perfcounter0_low_u; + + +/* + * TP0_PERFCOUNTER1_SELECT struct + */ + +#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TP0_PERFCOUNTER1_SELECT_MASK \ + (TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TP0_PERFCOUNTER1_SELECT(perfcounter_select) \ + ((perfcounter_select << TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TP0_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tp0_perfcounter1_select) \ + ((tp0_perfcounter1_select & TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TP0_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tp0_perfcounter1_select_reg, perfcounter_select) \ + tp0_perfcounter1_select_reg = (tp0_perfcounter1_select_reg & ~TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_select_t { + unsigned int perfcounter_select : TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tp0_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TP0_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + } tp0_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter1_select_t f; +} tp0_perfcounter1_select_u; + + +/* + * TP0_PERFCOUNTER1_HI struct + */ + +#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16 + +#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TP0_PERFCOUNTER1_HI_MASK \ + (TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) + +#define TP0_PERFCOUNTER1_HI(perfcounter_hi) \ + ((perfcounter_hi << TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)) + +#define TP0_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tp0_perfcounter1_hi) \ + ((tp0_perfcounter1_hi & TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#define TP0_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tp0_perfcounter1_hi_reg, perfcounter_hi) \ + tp0_perfcounter1_hi_reg = (tp0_perfcounter1_hi_reg & ~TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_hi_t { + unsigned int perfcounter_hi : TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tp0_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TP0_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + } tp0_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter1_hi_t f; +} tp0_perfcounter1_hi_u; + + +/* + * TP0_PERFCOUNTER1_LOW struct + */ + +#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TP0_PERFCOUNTER1_LOW_MASK \ + (TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) + +#define TP0_PERFCOUNTER1_LOW(perfcounter_low) \ + ((perfcounter_low << TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TP0_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tp0_perfcounter1_low) \ + ((tp0_perfcounter1_low & TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TP0_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tp0_perfcounter1_low_reg, perfcounter_low) \ + tp0_perfcounter1_low_reg = (tp0_perfcounter1_low_reg & ~TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_low_t { + unsigned int perfcounter_low : TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tp0_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tp0_perfcounter1_low_t { + unsigned int perfcounter_low : TP0_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tp0_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tp0_perfcounter1_low_t f; +} tp0_perfcounter1_low_u; + + +/* + * TCM_PERFCOUNTER0_SELECT struct + */ + +#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCM_PERFCOUNTER0_SELECT_MASK \ + (TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCM_PERFCOUNTER0_SELECT(perfcounter_select) \ + ((perfcounter_select << TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCM_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcm_perfcounter0_select) \ + ((tcm_perfcounter0_select & TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCM_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcm_perfcounter0_select_reg, perfcounter_select) \ + tcm_perfcounter0_select_reg = (tcm_perfcounter0_select_reg & ~TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_select_t { + unsigned int perfcounter_select : TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcm_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCM_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcm_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter0_select_t f; +} tcm_perfcounter0_select_u; + + +/* + * TCM_PERFCOUNTER1_SELECT struct + */ + +#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCM_PERFCOUNTER1_SELECT_MASK \ + (TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCM_PERFCOUNTER1_SELECT(perfcounter_select) \ + ((perfcounter_select << TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCM_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcm_perfcounter1_select) \ + ((tcm_perfcounter1_select & TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCM_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcm_perfcounter1_select_reg, perfcounter_select) \ + tcm_perfcounter1_select_reg = (tcm_perfcounter1_select_reg & ~TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_select_t { + unsigned int perfcounter_select : TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcm_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCM_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcm_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter1_select_t f; +} tcm_perfcounter1_select_u; + + +/* + * TCM_PERFCOUNTER0_HI struct + */ + +#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCM_PERFCOUNTER0_HI_MASK \ + (TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) + +#define TCM_PERFCOUNTER0_HI(perfcounter_hi) \ + ((perfcounter_hi << TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCM_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcm_perfcounter0_hi) \ + ((tcm_perfcounter0_hi & TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#define TCM_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcm_perfcounter0_hi_reg, perfcounter_hi) \ + tcm_perfcounter0_hi_reg = (tcm_perfcounter0_hi_reg & ~TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_hi_t { + unsigned int perfcounter_hi : TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcm_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCM_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + } tcm_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter0_hi_t f; +} tcm_perfcounter0_hi_u; + + +/* + * TCM_PERFCOUNTER1_HI struct + */ + +#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCM_PERFCOUNTER1_HI_MASK \ + (TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) + +#define TCM_PERFCOUNTER1_HI(perfcounter_hi) \ + ((perfcounter_hi << TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCM_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcm_perfcounter1_hi) \ + ((tcm_perfcounter1_hi & TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#define TCM_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcm_perfcounter1_hi_reg, perfcounter_hi) \ + tcm_perfcounter1_hi_reg = (tcm_perfcounter1_hi_reg & ~TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_hi_t { + unsigned int perfcounter_hi : TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcm_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCM_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + } tcm_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter1_hi_t f; +} tcm_perfcounter1_hi_u; + + +/* + * TCM_PERFCOUNTER0_LOW struct + */ + +#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCM_PERFCOUNTER0_LOW_MASK \ + (TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) + +#define TCM_PERFCOUNTER0_LOW(perfcounter_low) \ + ((perfcounter_low << TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCM_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcm_perfcounter0_low) \ + ((tcm_perfcounter0_low & TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCM_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcm_perfcounter0_low_reg, perfcounter_low) \ + tcm_perfcounter0_low_reg = (tcm_perfcounter0_low_reg & ~TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_low_t { + unsigned int perfcounter_low : TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcm_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter0_low_t { + unsigned int perfcounter_low : TCM_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcm_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter0_low_t f; +} tcm_perfcounter0_low_u; + + +/* + * TCM_PERFCOUNTER1_LOW struct + */ + +#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCM_PERFCOUNTER1_LOW_MASK \ + (TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) + +#define TCM_PERFCOUNTER1_LOW(perfcounter_low) \ + ((perfcounter_low << TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCM_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcm_perfcounter1_low) \ + ((tcm_perfcounter1_low & TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCM_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcm_perfcounter1_low_reg, perfcounter_low) \ + tcm_perfcounter1_low_reg = (tcm_perfcounter1_low_reg & ~TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_low_t { + unsigned int perfcounter_low : TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcm_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcm_perfcounter1_low_t { + unsigned int perfcounter_low : TCM_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcm_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcm_perfcounter1_low_t f; +} tcm_perfcounter1_low_u; + + +/* + * TCF_PERFCOUNTER0_SELECT struct + */ + +#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER0_SELECT_MASK \ + (TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER0_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER0_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter0_select) \ + ((tcf_perfcounter0_select & TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER0_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter0_select_reg, perfcounter_select) \ + tcf_perfcounter0_select_reg = (tcf_perfcounter0_select_reg & ~TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER0_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter0_select_t f; +} tcf_perfcounter0_select_u; + + +/* + * TCF_PERFCOUNTER1_SELECT struct + */ + +#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER1_SELECT_MASK \ + (TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER1_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER1_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter1_select) \ + ((tcf_perfcounter1_select & TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER1_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter1_select_reg, perfcounter_select) \ + tcf_perfcounter1_select_reg = (tcf_perfcounter1_select_reg & ~TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter1_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER1_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter1_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter1_select_t f; +} tcf_perfcounter1_select_u; + + +/* + * TCF_PERFCOUNTER2_SELECT struct + */ + +#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER2_SELECT_MASK \ + (TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER2_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER2_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter2_select) \ + ((tcf_perfcounter2_select & TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER2_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter2_select_reg, perfcounter_select) \ + tcf_perfcounter2_select_reg = (tcf_perfcounter2_select_reg & ~TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter2_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER2_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter2_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter2_select_t f; +} tcf_perfcounter2_select_u; + + +/* + * TCF_PERFCOUNTER3_SELECT struct + */ + +#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER3_SELECT_MASK \ + (TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER3_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER3_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter3_select) \ + ((tcf_perfcounter3_select & TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER3_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter3_select_reg, perfcounter_select) \ + tcf_perfcounter3_select_reg = (tcf_perfcounter3_select_reg & ~TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter3_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER3_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter3_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter3_select_t f; +} tcf_perfcounter3_select_u; + + +/* + * TCF_PERFCOUNTER4_SELECT struct + */ + +#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER4_SELECT_MASK \ + (TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER4_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER4_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter4_select) \ + ((tcf_perfcounter4_select & TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER4_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter4_select_reg, perfcounter_select) \ + tcf_perfcounter4_select_reg = (tcf_perfcounter4_select_reg & ~TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter4_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER4_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter4_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter4_select_t f; +} tcf_perfcounter4_select_u; + + +/* + * TCF_PERFCOUNTER5_SELECT struct + */ + +#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER5_SELECT_MASK \ + (TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER5_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER5_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter5_select) \ + ((tcf_perfcounter5_select & TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER5_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter5_select_reg, perfcounter_select) \ + tcf_perfcounter5_select_reg = (tcf_perfcounter5_select_reg & ~TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter5_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER5_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter5_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter5_select_t f; +} tcf_perfcounter5_select_u; + + +/* + * TCF_PERFCOUNTER6_SELECT struct + */ + +#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER6_SELECT_MASK \ + (TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER6_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER6_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter6_select) \ + ((tcf_perfcounter6_select & TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER6_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter6_select_reg, perfcounter_select) \ + tcf_perfcounter6_select_reg = (tcf_perfcounter6_select_reg & ~TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter6_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER6_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter6_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter6_select_t f; +} tcf_perfcounter6_select_u; + + +/* + * TCF_PERFCOUNTER7_SELECT struct + */ + +#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER7_SELECT_MASK \ + (TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER7_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER7_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter7_select) \ + ((tcf_perfcounter7_select & TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER7_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter7_select_reg, perfcounter_select) \ + tcf_perfcounter7_select_reg = (tcf_perfcounter7_select_reg & ~TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter7_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER7_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter7_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter7_select_t f; +} tcf_perfcounter7_select_u; + + +/* + * TCF_PERFCOUNTER8_SELECT struct + */ + +#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER8_SELECT_MASK \ + (TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER8_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER8_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter8_select) \ + ((tcf_perfcounter8_select & TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER8_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter8_select_reg, perfcounter_select) \ + tcf_perfcounter8_select_reg = (tcf_perfcounter8_select_reg & ~TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter8_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER8_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter8_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter8_select_t f; +} tcf_perfcounter8_select_u; + + +/* + * TCF_PERFCOUNTER9_SELECT struct + */ + +#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER9_SELECT_MASK \ + (TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER9_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER9_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter9_select) \ + ((tcf_perfcounter9_select & TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER9_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter9_select_reg, perfcounter_select) \ + tcf_perfcounter9_select_reg = (tcf_perfcounter9_select_reg & ~TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter9_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER9_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter9_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter9_select_t f; +} tcf_perfcounter9_select_u; + + +/* + * TCF_PERFCOUNTER10_SELECT struct + */ + +#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER10_SELECT_MASK \ + (TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER10_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER10_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter10_select) \ + ((tcf_perfcounter10_select & TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER10_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter10_select_reg, perfcounter_select) \ + tcf_perfcounter10_select_reg = (tcf_perfcounter10_select_reg & ~TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter10_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER10_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter10_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter10_select_t f; +} tcf_perfcounter10_select_u; + + +/* + * TCF_PERFCOUNTER11_SELECT struct + */ + +#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE 8 + +#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT 0 + +#define TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK 0x000000ff + +#define TCF_PERFCOUNTER11_SELECT_MASK \ + (TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) + +#define TCF_PERFCOUNTER11_SELECT(perfcounter_select) \ + ((perfcounter_select << TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT)) + +#define TCF_PERFCOUNTER11_SELECT_GET_PERFCOUNTER_SELECT(tcf_perfcounter11_select) \ + ((tcf_perfcounter11_select & TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) >> TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#define TCF_PERFCOUNTER11_SELECT_SET_PERFCOUNTER_SELECT(tcf_perfcounter11_select_reg, perfcounter_select) \ + tcf_perfcounter11_select_reg = (tcf_perfcounter11_select_reg & ~TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_MASK) | (perfcounter_select << TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_select_t { + unsigned int perfcounter_select : TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE; + unsigned int : 24; + } tcf_perfcounter11_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_select_t { + unsigned int : 24; + unsigned int perfcounter_select : TCF_PERFCOUNTER11_SELECT_PERFCOUNTER_SELECT_SIZE; + } tcf_perfcounter11_select_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter11_select_t f; +} tcf_perfcounter11_select_u; + + +/* + * TCF_PERFCOUNTER0_HI struct + */ + +#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER0_HI_MASK \ + (TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER0_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER0_HI_GET_PERFCOUNTER_HI(tcf_perfcounter0_hi) \ + ((tcf_perfcounter0_hi & TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER0_HI_SET_PERFCOUNTER_HI(tcf_perfcounter0_hi_reg, perfcounter_hi) \ + tcf_perfcounter0_hi_reg = (tcf_perfcounter0_hi_reg & ~TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER0_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter0_hi_t f; +} tcf_perfcounter0_hi_u; + + +/* + * TCF_PERFCOUNTER1_HI struct + */ + +#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER1_HI_MASK \ + (TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER1_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER1_HI_GET_PERFCOUNTER_HI(tcf_perfcounter1_hi) \ + ((tcf_perfcounter1_hi & TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER1_HI_SET_PERFCOUNTER_HI(tcf_perfcounter1_hi_reg, perfcounter_hi) \ + tcf_perfcounter1_hi_reg = (tcf_perfcounter1_hi_reg & ~TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter1_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER1_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter1_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter1_hi_t f; +} tcf_perfcounter1_hi_u; + + +/* + * TCF_PERFCOUNTER2_HI struct + */ + +#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER2_HI_MASK \ + (TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER2_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER2_HI_GET_PERFCOUNTER_HI(tcf_perfcounter2_hi) \ + ((tcf_perfcounter2_hi & TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER2_HI_SET_PERFCOUNTER_HI(tcf_perfcounter2_hi_reg, perfcounter_hi) \ + tcf_perfcounter2_hi_reg = (tcf_perfcounter2_hi_reg & ~TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter2_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER2_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter2_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter2_hi_t f; +} tcf_perfcounter2_hi_u; + + +/* + * TCF_PERFCOUNTER3_HI struct + */ + +#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER3_HI_MASK \ + (TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER3_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER3_HI_GET_PERFCOUNTER_HI(tcf_perfcounter3_hi) \ + ((tcf_perfcounter3_hi & TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER3_HI_SET_PERFCOUNTER_HI(tcf_perfcounter3_hi_reg, perfcounter_hi) \ + tcf_perfcounter3_hi_reg = (tcf_perfcounter3_hi_reg & ~TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter3_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER3_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter3_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter3_hi_t f; +} tcf_perfcounter3_hi_u; + + +/* + * TCF_PERFCOUNTER4_HI struct + */ + +#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER4_HI_MASK \ + (TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER4_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER4_HI_GET_PERFCOUNTER_HI(tcf_perfcounter4_hi) \ + ((tcf_perfcounter4_hi & TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER4_HI_SET_PERFCOUNTER_HI(tcf_perfcounter4_hi_reg, perfcounter_hi) \ + tcf_perfcounter4_hi_reg = (tcf_perfcounter4_hi_reg & ~TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter4_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER4_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter4_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter4_hi_t f; +} tcf_perfcounter4_hi_u; + + +/* + * TCF_PERFCOUNTER5_HI struct + */ + +#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER5_HI_MASK \ + (TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER5_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER5_HI_GET_PERFCOUNTER_HI(tcf_perfcounter5_hi) \ + ((tcf_perfcounter5_hi & TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER5_HI_SET_PERFCOUNTER_HI(tcf_perfcounter5_hi_reg, perfcounter_hi) \ + tcf_perfcounter5_hi_reg = (tcf_perfcounter5_hi_reg & ~TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter5_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER5_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter5_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter5_hi_t f; +} tcf_perfcounter5_hi_u; + + +/* + * TCF_PERFCOUNTER6_HI struct + */ + +#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER6_HI_MASK \ + (TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER6_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER6_HI_GET_PERFCOUNTER_HI(tcf_perfcounter6_hi) \ + ((tcf_perfcounter6_hi & TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER6_HI_SET_PERFCOUNTER_HI(tcf_perfcounter6_hi_reg, perfcounter_hi) \ + tcf_perfcounter6_hi_reg = (tcf_perfcounter6_hi_reg & ~TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter6_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER6_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter6_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter6_hi_t f; +} tcf_perfcounter6_hi_u; + + +/* + * TCF_PERFCOUNTER7_HI struct + */ + +#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER7_HI_MASK \ + (TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER7_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER7_HI_GET_PERFCOUNTER_HI(tcf_perfcounter7_hi) \ + ((tcf_perfcounter7_hi & TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER7_HI_SET_PERFCOUNTER_HI(tcf_perfcounter7_hi_reg, perfcounter_hi) \ + tcf_perfcounter7_hi_reg = (tcf_perfcounter7_hi_reg & ~TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter7_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER7_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter7_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter7_hi_t f; +} tcf_perfcounter7_hi_u; + + +/* + * TCF_PERFCOUNTER8_HI struct + */ + +#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER8_HI_MASK \ + (TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER8_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER8_HI_GET_PERFCOUNTER_HI(tcf_perfcounter8_hi) \ + ((tcf_perfcounter8_hi & TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER8_HI_SET_PERFCOUNTER_HI(tcf_perfcounter8_hi_reg, perfcounter_hi) \ + tcf_perfcounter8_hi_reg = (tcf_perfcounter8_hi_reg & ~TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter8_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER8_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter8_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter8_hi_t f; +} tcf_perfcounter8_hi_u; + + +/* + * TCF_PERFCOUNTER9_HI struct + */ + +#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER9_HI_MASK \ + (TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER9_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER9_HI_GET_PERFCOUNTER_HI(tcf_perfcounter9_hi) \ + ((tcf_perfcounter9_hi & TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER9_HI_SET_PERFCOUNTER_HI(tcf_perfcounter9_hi_reg, perfcounter_hi) \ + tcf_perfcounter9_hi_reg = (tcf_perfcounter9_hi_reg & ~TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter9_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER9_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter9_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter9_hi_t f; +} tcf_perfcounter9_hi_u; + + +/* + * TCF_PERFCOUNTER10_HI struct + */ + +#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER10_HI_MASK \ + (TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER10_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER10_HI_GET_PERFCOUNTER_HI(tcf_perfcounter10_hi) \ + ((tcf_perfcounter10_hi & TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER10_HI_SET_PERFCOUNTER_HI(tcf_perfcounter10_hi_reg, perfcounter_hi) \ + tcf_perfcounter10_hi_reg = (tcf_perfcounter10_hi_reg & ~TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter10_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER10_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter10_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter10_hi_t f; +} tcf_perfcounter10_hi_u; + + +/* + * TCF_PERFCOUNTER11_HI struct + */ + +#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE 16 + +#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT 0 + +#define TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK 0x0000ffff + +#define TCF_PERFCOUNTER11_HI_MASK \ + (TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) + +#define TCF_PERFCOUNTER11_HI(perfcounter_hi) \ + ((perfcounter_hi << TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT)) + +#define TCF_PERFCOUNTER11_HI_GET_PERFCOUNTER_HI(tcf_perfcounter11_hi) \ + ((tcf_perfcounter11_hi & TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) >> TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT) + +#define TCF_PERFCOUNTER11_HI_SET_PERFCOUNTER_HI(tcf_perfcounter11_hi_reg, perfcounter_hi) \ + tcf_perfcounter11_hi_reg = (tcf_perfcounter11_hi_reg & ~TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_MASK) | (perfcounter_hi << TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_hi_t { + unsigned int perfcounter_hi : TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE; + unsigned int : 16; + } tcf_perfcounter11_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_hi_t { + unsigned int : 16; + unsigned int perfcounter_hi : TCF_PERFCOUNTER11_HI_PERFCOUNTER_HI_SIZE; + } tcf_perfcounter11_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter11_hi_t f; +} tcf_perfcounter11_hi_u; + + +/* + * TCF_PERFCOUNTER0_LOW struct + */ + +#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER0_LOW_MASK \ + (TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER0_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER0_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter0_low) \ + ((tcf_perfcounter0_low & TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER0_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter0_low_reg, perfcounter_low) \ + tcf_perfcounter0_low_reg = (tcf_perfcounter0_low_reg & ~TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter0_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER0_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter0_low_t f; +} tcf_perfcounter0_low_u; + + +/* + * TCF_PERFCOUNTER1_LOW struct + */ + +#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER1_LOW_MASK \ + (TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER1_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER1_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter1_low) \ + ((tcf_perfcounter1_low & TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER1_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter1_low_reg, perfcounter_low) \ + tcf_perfcounter1_low_reg = (tcf_perfcounter1_low_reg & ~TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter1_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter1_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER1_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter1_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter1_low_t f; +} tcf_perfcounter1_low_u; + + +/* + * TCF_PERFCOUNTER2_LOW struct + */ + +#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER2_LOW_MASK \ + (TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER2_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER2_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter2_low) \ + ((tcf_perfcounter2_low & TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER2_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter2_low_reg, perfcounter_low) \ + tcf_perfcounter2_low_reg = (tcf_perfcounter2_low_reg & ~TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter2_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter2_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER2_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter2_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter2_low_t f; +} tcf_perfcounter2_low_u; + + +/* + * TCF_PERFCOUNTER3_LOW struct + */ + +#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER3_LOW_MASK \ + (TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER3_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER3_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter3_low) \ + ((tcf_perfcounter3_low & TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER3_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter3_low_reg, perfcounter_low) \ + tcf_perfcounter3_low_reg = (tcf_perfcounter3_low_reg & ~TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter3_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter3_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER3_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter3_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter3_low_t f; +} tcf_perfcounter3_low_u; + + +/* + * TCF_PERFCOUNTER4_LOW struct + */ + +#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER4_LOW_MASK \ + (TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER4_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER4_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter4_low) \ + ((tcf_perfcounter4_low & TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER4_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter4_low_reg, perfcounter_low) \ + tcf_perfcounter4_low_reg = (tcf_perfcounter4_low_reg & ~TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter4_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter4_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER4_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter4_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter4_low_t f; +} tcf_perfcounter4_low_u; + + +/* + * TCF_PERFCOUNTER5_LOW struct + */ + +#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER5_LOW_MASK \ + (TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER5_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER5_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter5_low) \ + ((tcf_perfcounter5_low & TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER5_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter5_low_reg, perfcounter_low) \ + tcf_perfcounter5_low_reg = (tcf_perfcounter5_low_reg & ~TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter5_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter5_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER5_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter5_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter5_low_t f; +} tcf_perfcounter5_low_u; + + +/* + * TCF_PERFCOUNTER6_LOW struct + */ + +#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER6_LOW_MASK \ + (TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER6_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER6_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter6_low) \ + ((tcf_perfcounter6_low & TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER6_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter6_low_reg, perfcounter_low) \ + tcf_perfcounter6_low_reg = (tcf_perfcounter6_low_reg & ~TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter6_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter6_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER6_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter6_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter6_low_t f; +} tcf_perfcounter6_low_u; + + +/* + * TCF_PERFCOUNTER7_LOW struct + */ + +#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER7_LOW_MASK \ + (TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER7_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER7_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter7_low) \ + ((tcf_perfcounter7_low & TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER7_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter7_low_reg, perfcounter_low) \ + tcf_perfcounter7_low_reg = (tcf_perfcounter7_low_reg & ~TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter7_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter7_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER7_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter7_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter7_low_t f; +} tcf_perfcounter7_low_u; + + +/* + * TCF_PERFCOUNTER8_LOW struct + */ + +#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER8_LOW_MASK \ + (TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER8_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER8_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter8_low) \ + ((tcf_perfcounter8_low & TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER8_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter8_low_reg, perfcounter_low) \ + tcf_perfcounter8_low_reg = (tcf_perfcounter8_low_reg & ~TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter8_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter8_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER8_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter8_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter8_low_t f; +} tcf_perfcounter8_low_u; + + +/* + * TCF_PERFCOUNTER9_LOW struct + */ + +#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER9_LOW_MASK \ + (TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER9_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER9_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter9_low) \ + ((tcf_perfcounter9_low & TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER9_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter9_low_reg, perfcounter_low) \ + tcf_perfcounter9_low_reg = (tcf_perfcounter9_low_reg & ~TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter9_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter9_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER9_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter9_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter9_low_t f; +} tcf_perfcounter9_low_u; + + +/* + * TCF_PERFCOUNTER10_LOW struct + */ + +#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER10_LOW_MASK \ + (TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER10_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER10_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter10_low) \ + ((tcf_perfcounter10_low & TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER10_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter10_low_reg, perfcounter_low) \ + tcf_perfcounter10_low_reg = (tcf_perfcounter10_low_reg & ~TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter10_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter10_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER10_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter10_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter10_low_t f; +} tcf_perfcounter10_low_u; + + +/* + * TCF_PERFCOUNTER11_LOW struct + */ + +#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE 32 + +#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT 0 + +#define TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK 0xffffffff + +#define TCF_PERFCOUNTER11_LOW_MASK \ + (TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) + +#define TCF_PERFCOUNTER11_LOW(perfcounter_low) \ + ((perfcounter_low << TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT)) + +#define TCF_PERFCOUNTER11_LOW_GET_PERFCOUNTER_LOW(tcf_perfcounter11_low) \ + ((tcf_perfcounter11_low & TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) >> TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT) + +#define TCF_PERFCOUNTER11_LOW_SET_PERFCOUNTER_LOW(tcf_perfcounter11_low_reg, perfcounter_low) \ + tcf_perfcounter11_low_reg = (tcf_perfcounter11_low_reg & ~TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_MASK) | (perfcounter_low << TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter11_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_perfcounter11_low_t { + unsigned int perfcounter_low : TCF_PERFCOUNTER11_LOW_PERFCOUNTER_LOW_SIZE; + } tcf_perfcounter11_low_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_perfcounter11_low_t f; +} tcf_perfcounter11_low_u; + + +/* + * TCF_DEBUG struct + */ + +#define TCF_DEBUG_not_MH_TC_rtr_SIZE 1 +#define TCF_DEBUG_TC_MH_send_SIZE 1 +#define TCF_DEBUG_not_FG0_rtr_SIZE 1 +#define TCF_DEBUG_not_TCB_TCO_rtr_SIZE 1 +#define TCF_DEBUG_TCB_ff_stall_SIZE 1 +#define TCF_DEBUG_TCB_miss_stall_SIZE 1 +#define TCF_DEBUG_TCA_TCB_stall_SIZE 1 +#define TCF_DEBUG_PF0_stall_SIZE 1 +#define TCF_DEBUG_TP0_full_SIZE 1 +#define TCF_DEBUG_TPC_full_SIZE 1 +#define TCF_DEBUG_not_TPC_rtr_SIZE 1 +#define TCF_DEBUG_tca_state_rts_SIZE 1 +#define TCF_DEBUG_tca_rts_SIZE 1 + +#define TCF_DEBUG_not_MH_TC_rtr_SHIFT 6 +#define TCF_DEBUG_TC_MH_send_SHIFT 7 +#define TCF_DEBUG_not_FG0_rtr_SHIFT 8 +#define TCF_DEBUG_not_TCB_TCO_rtr_SHIFT 12 +#define TCF_DEBUG_TCB_ff_stall_SHIFT 13 +#define TCF_DEBUG_TCB_miss_stall_SHIFT 14 +#define TCF_DEBUG_TCA_TCB_stall_SHIFT 15 +#define TCF_DEBUG_PF0_stall_SHIFT 16 +#define TCF_DEBUG_TP0_full_SHIFT 20 +#define TCF_DEBUG_TPC_full_SHIFT 24 +#define TCF_DEBUG_not_TPC_rtr_SHIFT 25 +#define TCF_DEBUG_tca_state_rts_SHIFT 26 +#define TCF_DEBUG_tca_rts_SHIFT 27 + +#define TCF_DEBUG_not_MH_TC_rtr_MASK 0x00000040 +#define TCF_DEBUG_TC_MH_send_MASK 0x00000080 +#define TCF_DEBUG_not_FG0_rtr_MASK 0x00000100 +#define TCF_DEBUG_not_TCB_TCO_rtr_MASK 0x00001000 +#define TCF_DEBUG_TCB_ff_stall_MASK 0x00002000 +#define TCF_DEBUG_TCB_miss_stall_MASK 0x00004000 +#define TCF_DEBUG_TCA_TCB_stall_MASK 0x00008000 +#define TCF_DEBUG_PF0_stall_MASK 0x00010000 +#define TCF_DEBUG_TP0_full_MASK 0x00100000 +#define TCF_DEBUG_TPC_full_MASK 0x01000000 +#define TCF_DEBUG_not_TPC_rtr_MASK 0x02000000 +#define TCF_DEBUG_tca_state_rts_MASK 0x04000000 +#define TCF_DEBUG_tca_rts_MASK 0x08000000 + +#define TCF_DEBUG_MASK \ + (TCF_DEBUG_not_MH_TC_rtr_MASK | \ + TCF_DEBUG_TC_MH_send_MASK | \ + TCF_DEBUG_not_FG0_rtr_MASK | \ + TCF_DEBUG_not_TCB_TCO_rtr_MASK | \ + TCF_DEBUG_TCB_ff_stall_MASK | \ + TCF_DEBUG_TCB_miss_stall_MASK | \ + TCF_DEBUG_TCA_TCB_stall_MASK | \ + TCF_DEBUG_PF0_stall_MASK | \ + TCF_DEBUG_TP0_full_MASK | \ + TCF_DEBUG_TPC_full_MASK | \ + TCF_DEBUG_not_TPC_rtr_MASK | \ + TCF_DEBUG_tca_state_rts_MASK | \ + TCF_DEBUG_tca_rts_MASK) + +#define TCF_DEBUG(not_mh_tc_rtr, tc_mh_send, not_fg0_rtr, not_tcb_tco_rtr, tcb_ff_stall, tcb_miss_stall, tca_tcb_stall, pf0_stall, tp0_full, tpc_full, not_tpc_rtr, tca_state_rts, tca_rts) \ + ((not_mh_tc_rtr << TCF_DEBUG_not_MH_TC_rtr_SHIFT) | \ + (tc_mh_send << TCF_DEBUG_TC_MH_send_SHIFT) | \ + (not_fg0_rtr << TCF_DEBUG_not_FG0_rtr_SHIFT) | \ + (not_tcb_tco_rtr << TCF_DEBUG_not_TCB_TCO_rtr_SHIFT) | \ + (tcb_ff_stall << TCF_DEBUG_TCB_ff_stall_SHIFT) | \ + (tcb_miss_stall << TCF_DEBUG_TCB_miss_stall_SHIFT) | \ + (tca_tcb_stall << TCF_DEBUG_TCA_TCB_stall_SHIFT) | \ + (pf0_stall << TCF_DEBUG_PF0_stall_SHIFT) | \ + (tp0_full << TCF_DEBUG_TP0_full_SHIFT) | \ + (tpc_full << TCF_DEBUG_TPC_full_SHIFT) | \ + (not_tpc_rtr << TCF_DEBUG_not_TPC_rtr_SHIFT) | \ + (tca_state_rts << TCF_DEBUG_tca_state_rts_SHIFT) | \ + (tca_rts << TCF_DEBUG_tca_rts_SHIFT)) + +#define TCF_DEBUG_GET_not_MH_TC_rtr(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_not_MH_TC_rtr_MASK) >> TCF_DEBUG_not_MH_TC_rtr_SHIFT) +#define TCF_DEBUG_GET_TC_MH_send(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TC_MH_send_MASK) >> TCF_DEBUG_TC_MH_send_SHIFT) +#define TCF_DEBUG_GET_not_FG0_rtr(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_not_FG0_rtr_MASK) >> TCF_DEBUG_not_FG0_rtr_SHIFT) +#define TCF_DEBUG_GET_not_TCB_TCO_rtr(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_not_TCB_TCO_rtr_MASK) >> TCF_DEBUG_not_TCB_TCO_rtr_SHIFT) +#define TCF_DEBUG_GET_TCB_ff_stall(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TCB_ff_stall_MASK) >> TCF_DEBUG_TCB_ff_stall_SHIFT) +#define TCF_DEBUG_GET_TCB_miss_stall(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TCB_miss_stall_MASK) >> TCF_DEBUG_TCB_miss_stall_SHIFT) +#define TCF_DEBUG_GET_TCA_TCB_stall(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TCA_TCB_stall_MASK) >> TCF_DEBUG_TCA_TCB_stall_SHIFT) +#define TCF_DEBUG_GET_PF0_stall(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_PF0_stall_MASK) >> TCF_DEBUG_PF0_stall_SHIFT) +#define TCF_DEBUG_GET_TP0_full(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TP0_full_MASK) >> TCF_DEBUG_TP0_full_SHIFT) +#define TCF_DEBUG_GET_TPC_full(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_TPC_full_MASK) >> TCF_DEBUG_TPC_full_SHIFT) +#define TCF_DEBUG_GET_not_TPC_rtr(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_not_TPC_rtr_MASK) >> TCF_DEBUG_not_TPC_rtr_SHIFT) +#define TCF_DEBUG_GET_tca_state_rts(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_tca_state_rts_MASK) >> TCF_DEBUG_tca_state_rts_SHIFT) +#define TCF_DEBUG_GET_tca_rts(tcf_debug) \ + ((tcf_debug & TCF_DEBUG_tca_rts_MASK) >> TCF_DEBUG_tca_rts_SHIFT) + +#define TCF_DEBUG_SET_not_MH_TC_rtr(tcf_debug_reg, not_mh_tc_rtr) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_MH_TC_rtr_MASK) | (not_mh_tc_rtr << TCF_DEBUG_not_MH_TC_rtr_SHIFT) +#define TCF_DEBUG_SET_TC_MH_send(tcf_debug_reg, tc_mh_send) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TC_MH_send_MASK) | (tc_mh_send << TCF_DEBUG_TC_MH_send_SHIFT) +#define TCF_DEBUG_SET_not_FG0_rtr(tcf_debug_reg, not_fg0_rtr) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_FG0_rtr_MASK) | (not_fg0_rtr << TCF_DEBUG_not_FG0_rtr_SHIFT) +#define TCF_DEBUG_SET_not_TCB_TCO_rtr(tcf_debug_reg, not_tcb_tco_rtr) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_TCB_TCO_rtr_MASK) | (not_tcb_tco_rtr << TCF_DEBUG_not_TCB_TCO_rtr_SHIFT) +#define TCF_DEBUG_SET_TCB_ff_stall(tcf_debug_reg, tcb_ff_stall) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCB_ff_stall_MASK) | (tcb_ff_stall << TCF_DEBUG_TCB_ff_stall_SHIFT) +#define TCF_DEBUG_SET_TCB_miss_stall(tcf_debug_reg, tcb_miss_stall) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCB_miss_stall_MASK) | (tcb_miss_stall << TCF_DEBUG_TCB_miss_stall_SHIFT) +#define TCF_DEBUG_SET_TCA_TCB_stall(tcf_debug_reg, tca_tcb_stall) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TCA_TCB_stall_MASK) | (tca_tcb_stall << TCF_DEBUG_TCA_TCB_stall_SHIFT) +#define TCF_DEBUG_SET_PF0_stall(tcf_debug_reg, pf0_stall) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_PF0_stall_MASK) | (pf0_stall << TCF_DEBUG_PF0_stall_SHIFT) +#define TCF_DEBUG_SET_TP0_full(tcf_debug_reg, tp0_full) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TP0_full_MASK) | (tp0_full << TCF_DEBUG_TP0_full_SHIFT) +#define TCF_DEBUG_SET_TPC_full(tcf_debug_reg, tpc_full) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_TPC_full_MASK) | (tpc_full << TCF_DEBUG_TPC_full_SHIFT) +#define TCF_DEBUG_SET_not_TPC_rtr(tcf_debug_reg, not_tpc_rtr) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_not_TPC_rtr_MASK) | (not_tpc_rtr << TCF_DEBUG_not_TPC_rtr_SHIFT) +#define TCF_DEBUG_SET_tca_state_rts(tcf_debug_reg, tca_state_rts) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_tca_state_rts_MASK) | (tca_state_rts << TCF_DEBUG_tca_state_rts_SHIFT) +#define TCF_DEBUG_SET_tca_rts(tcf_debug_reg, tca_rts) \ + tcf_debug_reg = (tcf_debug_reg & ~TCF_DEBUG_tca_rts_MASK) | (tca_rts << TCF_DEBUG_tca_rts_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcf_debug_t { + unsigned int : 6; + unsigned int not_mh_tc_rtr : TCF_DEBUG_not_MH_TC_rtr_SIZE; + unsigned int tc_mh_send : TCF_DEBUG_TC_MH_send_SIZE; + unsigned int not_fg0_rtr : TCF_DEBUG_not_FG0_rtr_SIZE; + unsigned int : 3; + unsigned int not_tcb_tco_rtr : TCF_DEBUG_not_TCB_TCO_rtr_SIZE; + unsigned int tcb_ff_stall : TCF_DEBUG_TCB_ff_stall_SIZE; + unsigned int tcb_miss_stall : TCF_DEBUG_TCB_miss_stall_SIZE; + unsigned int tca_tcb_stall : TCF_DEBUG_TCA_TCB_stall_SIZE; + unsigned int pf0_stall : TCF_DEBUG_PF0_stall_SIZE; + unsigned int : 3; + unsigned int tp0_full : TCF_DEBUG_TP0_full_SIZE; + unsigned int : 3; + unsigned int tpc_full : TCF_DEBUG_TPC_full_SIZE; + unsigned int not_tpc_rtr : TCF_DEBUG_not_TPC_rtr_SIZE; + unsigned int tca_state_rts : TCF_DEBUG_tca_state_rts_SIZE; + unsigned int tca_rts : TCF_DEBUG_tca_rts_SIZE; + unsigned int : 4; + } tcf_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcf_debug_t { + unsigned int : 4; + unsigned int tca_rts : TCF_DEBUG_tca_rts_SIZE; + unsigned int tca_state_rts : TCF_DEBUG_tca_state_rts_SIZE; + unsigned int not_tpc_rtr : TCF_DEBUG_not_TPC_rtr_SIZE; + unsigned int tpc_full : TCF_DEBUG_TPC_full_SIZE; + unsigned int : 3; + unsigned int tp0_full : TCF_DEBUG_TP0_full_SIZE; + unsigned int : 3; + unsigned int pf0_stall : TCF_DEBUG_PF0_stall_SIZE; + unsigned int tca_tcb_stall : TCF_DEBUG_TCA_TCB_stall_SIZE; + unsigned int tcb_miss_stall : TCF_DEBUG_TCB_miss_stall_SIZE; + unsigned int tcb_ff_stall : TCF_DEBUG_TCB_ff_stall_SIZE; + unsigned int not_tcb_tco_rtr : TCF_DEBUG_not_TCB_TCO_rtr_SIZE; + unsigned int : 3; + unsigned int not_fg0_rtr : TCF_DEBUG_not_FG0_rtr_SIZE; + unsigned int tc_mh_send : TCF_DEBUG_TC_MH_send_SIZE; + unsigned int not_mh_tc_rtr : TCF_DEBUG_not_MH_TC_rtr_SIZE; + unsigned int : 6; + } tcf_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcf_debug_t f; +} tcf_debug_u; + + +/* + * TCA_FIFO_DEBUG struct + */ + +#define TCA_FIFO_DEBUG_tp0_full_SIZE 1 +#define TCA_FIFO_DEBUG_tpc_full_SIZE 1 +#define TCA_FIFO_DEBUG_load_tpc_fifo_SIZE 1 +#define TCA_FIFO_DEBUG_load_tp_fifos_SIZE 1 +#define TCA_FIFO_DEBUG_FW_full_SIZE 1 +#define TCA_FIFO_DEBUG_not_FW_rtr0_SIZE 1 +#define TCA_FIFO_DEBUG_FW_rts0_SIZE 1 +#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE 1 +#define TCA_FIFO_DEBUG_FW_tpc_rts_SIZE 1 + +#define TCA_FIFO_DEBUG_tp0_full_SHIFT 0 +#define TCA_FIFO_DEBUG_tpc_full_SHIFT 4 +#define TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT 5 +#define TCA_FIFO_DEBUG_load_tp_fifos_SHIFT 6 +#define TCA_FIFO_DEBUG_FW_full_SHIFT 7 +#define TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT 8 +#define TCA_FIFO_DEBUG_FW_rts0_SHIFT 12 +#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT 16 +#define TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT 17 + +#define TCA_FIFO_DEBUG_tp0_full_MASK 0x00000001 +#define TCA_FIFO_DEBUG_tpc_full_MASK 0x00000010 +#define TCA_FIFO_DEBUG_load_tpc_fifo_MASK 0x00000020 +#define TCA_FIFO_DEBUG_load_tp_fifos_MASK 0x00000040 +#define TCA_FIFO_DEBUG_FW_full_MASK 0x00000080 +#define TCA_FIFO_DEBUG_not_FW_rtr0_MASK 0x00000100 +#define TCA_FIFO_DEBUG_FW_rts0_MASK 0x00001000 +#define TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK 0x00010000 +#define TCA_FIFO_DEBUG_FW_tpc_rts_MASK 0x00020000 + +#define TCA_FIFO_DEBUG_MASK \ + (TCA_FIFO_DEBUG_tp0_full_MASK | \ + TCA_FIFO_DEBUG_tpc_full_MASK | \ + TCA_FIFO_DEBUG_load_tpc_fifo_MASK | \ + TCA_FIFO_DEBUG_load_tp_fifos_MASK | \ + TCA_FIFO_DEBUG_FW_full_MASK | \ + TCA_FIFO_DEBUG_not_FW_rtr0_MASK | \ + TCA_FIFO_DEBUG_FW_rts0_MASK | \ + TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK | \ + TCA_FIFO_DEBUG_FW_tpc_rts_MASK) + +#define TCA_FIFO_DEBUG(tp0_full, tpc_full, load_tpc_fifo, load_tp_fifos, fw_full, not_fw_rtr0, fw_rts0, not_fw_tpc_rtr, fw_tpc_rts) \ + ((tp0_full << TCA_FIFO_DEBUG_tp0_full_SHIFT) | \ + (tpc_full << TCA_FIFO_DEBUG_tpc_full_SHIFT) | \ + (load_tpc_fifo << TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT) | \ + (load_tp_fifos << TCA_FIFO_DEBUG_load_tp_fifos_SHIFT) | \ + (fw_full << TCA_FIFO_DEBUG_FW_full_SHIFT) | \ + (not_fw_rtr0 << TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT) | \ + (fw_rts0 << TCA_FIFO_DEBUG_FW_rts0_SHIFT) | \ + (not_fw_tpc_rtr << TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT) | \ + (fw_tpc_rts << TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT)) + +#define TCA_FIFO_DEBUG_GET_tp0_full(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_tp0_full_MASK) >> TCA_FIFO_DEBUG_tp0_full_SHIFT) +#define TCA_FIFO_DEBUG_GET_tpc_full(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_tpc_full_MASK) >> TCA_FIFO_DEBUG_tpc_full_SHIFT) +#define TCA_FIFO_DEBUG_GET_load_tpc_fifo(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_load_tpc_fifo_MASK) >> TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT) +#define TCA_FIFO_DEBUG_GET_load_tp_fifos(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_load_tp_fifos_MASK) >> TCA_FIFO_DEBUG_load_tp_fifos_SHIFT) +#define TCA_FIFO_DEBUG_GET_FW_full(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_full_MASK) >> TCA_FIFO_DEBUG_FW_full_SHIFT) +#define TCA_FIFO_DEBUG_GET_not_FW_rtr0(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_not_FW_rtr0_MASK) >> TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT) +#define TCA_FIFO_DEBUG_GET_FW_rts0(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_rts0_MASK) >> TCA_FIFO_DEBUG_FW_rts0_SHIFT) +#define TCA_FIFO_DEBUG_GET_not_FW_tpc_rtr(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK) >> TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT) +#define TCA_FIFO_DEBUG_GET_FW_tpc_rts(tca_fifo_debug) \ + ((tca_fifo_debug & TCA_FIFO_DEBUG_FW_tpc_rts_MASK) >> TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT) + +#define TCA_FIFO_DEBUG_SET_tp0_full(tca_fifo_debug_reg, tp0_full) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_tp0_full_MASK) | (tp0_full << TCA_FIFO_DEBUG_tp0_full_SHIFT) +#define TCA_FIFO_DEBUG_SET_tpc_full(tca_fifo_debug_reg, tpc_full) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_tpc_full_MASK) | (tpc_full << TCA_FIFO_DEBUG_tpc_full_SHIFT) +#define TCA_FIFO_DEBUG_SET_load_tpc_fifo(tca_fifo_debug_reg, load_tpc_fifo) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_load_tpc_fifo_MASK) | (load_tpc_fifo << TCA_FIFO_DEBUG_load_tpc_fifo_SHIFT) +#define TCA_FIFO_DEBUG_SET_load_tp_fifos(tca_fifo_debug_reg, load_tp_fifos) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_load_tp_fifos_MASK) | (load_tp_fifos << TCA_FIFO_DEBUG_load_tp_fifos_SHIFT) +#define TCA_FIFO_DEBUG_SET_FW_full(tca_fifo_debug_reg, fw_full) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_full_MASK) | (fw_full << TCA_FIFO_DEBUG_FW_full_SHIFT) +#define TCA_FIFO_DEBUG_SET_not_FW_rtr0(tca_fifo_debug_reg, not_fw_rtr0) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_not_FW_rtr0_MASK) | (not_fw_rtr0 << TCA_FIFO_DEBUG_not_FW_rtr0_SHIFT) +#define TCA_FIFO_DEBUG_SET_FW_rts0(tca_fifo_debug_reg, fw_rts0) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_rts0_MASK) | (fw_rts0 << TCA_FIFO_DEBUG_FW_rts0_SHIFT) +#define TCA_FIFO_DEBUG_SET_not_FW_tpc_rtr(tca_fifo_debug_reg, not_fw_tpc_rtr) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_not_FW_tpc_rtr_MASK) | (not_fw_tpc_rtr << TCA_FIFO_DEBUG_not_FW_tpc_rtr_SHIFT) +#define TCA_FIFO_DEBUG_SET_FW_tpc_rts(tca_fifo_debug_reg, fw_tpc_rts) \ + tca_fifo_debug_reg = (tca_fifo_debug_reg & ~TCA_FIFO_DEBUG_FW_tpc_rts_MASK) | (fw_tpc_rts << TCA_FIFO_DEBUG_FW_tpc_rts_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tca_fifo_debug_t { + unsigned int tp0_full : TCA_FIFO_DEBUG_tp0_full_SIZE; + unsigned int : 3; + unsigned int tpc_full : TCA_FIFO_DEBUG_tpc_full_SIZE; + unsigned int load_tpc_fifo : TCA_FIFO_DEBUG_load_tpc_fifo_SIZE; + unsigned int load_tp_fifos : TCA_FIFO_DEBUG_load_tp_fifos_SIZE; + unsigned int fw_full : TCA_FIFO_DEBUG_FW_full_SIZE; + unsigned int not_fw_rtr0 : TCA_FIFO_DEBUG_not_FW_rtr0_SIZE; + unsigned int : 3; + unsigned int fw_rts0 : TCA_FIFO_DEBUG_FW_rts0_SIZE; + unsigned int : 3; + unsigned int not_fw_tpc_rtr : TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE; + unsigned int fw_tpc_rts : TCA_FIFO_DEBUG_FW_tpc_rts_SIZE; + unsigned int : 14; + } tca_fifo_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tca_fifo_debug_t { + unsigned int : 14; + unsigned int fw_tpc_rts : TCA_FIFO_DEBUG_FW_tpc_rts_SIZE; + unsigned int not_fw_tpc_rtr : TCA_FIFO_DEBUG_not_FW_tpc_rtr_SIZE; + unsigned int : 3; + unsigned int fw_rts0 : TCA_FIFO_DEBUG_FW_rts0_SIZE; + unsigned int : 3; + unsigned int not_fw_rtr0 : TCA_FIFO_DEBUG_not_FW_rtr0_SIZE; + unsigned int fw_full : TCA_FIFO_DEBUG_FW_full_SIZE; + unsigned int load_tp_fifos : TCA_FIFO_DEBUG_load_tp_fifos_SIZE; + unsigned int load_tpc_fifo : TCA_FIFO_DEBUG_load_tpc_fifo_SIZE; + unsigned int tpc_full : TCA_FIFO_DEBUG_tpc_full_SIZE; + unsigned int : 3; + unsigned int tp0_full : TCA_FIFO_DEBUG_tp0_full_SIZE; + } tca_fifo_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tca_fifo_debug_t f; +} tca_fifo_debug_u; + + +/* + * TCA_PROBE_DEBUG struct + */ + +#define TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE 1 + +#define TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT 0 + +#define TCA_PROBE_DEBUG_ProbeFilter_stall_MASK 0x00000001 + +#define TCA_PROBE_DEBUG_MASK \ + (TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) + +#define TCA_PROBE_DEBUG(probefilter_stall) \ + ((probefilter_stall << TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT)) + +#define TCA_PROBE_DEBUG_GET_ProbeFilter_stall(tca_probe_debug) \ + ((tca_probe_debug & TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) >> TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT) + +#define TCA_PROBE_DEBUG_SET_ProbeFilter_stall(tca_probe_debug_reg, probefilter_stall) \ + tca_probe_debug_reg = (tca_probe_debug_reg & ~TCA_PROBE_DEBUG_ProbeFilter_stall_MASK) | (probefilter_stall << TCA_PROBE_DEBUG_ProbeFilter_stall_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tca_probe_debug_t { + unsigned int probefilter_stall : TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE; + unsigned int : 31; + } tca_probe_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tca_probe_debug_t { + unsigned int : 31; + unsigned int probefilter_stall : TCA_PROBE_DEBUG_ProbeFilter_stall_SIZE; + } tca_probe_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tca_probe_debug_t f; +} tca_probe_debug_u; + + +/* + * TCA_TPC_DEBUG struct + */ + +#define TCA_TPC_DEBUG_captue_state_rts_SIZE 1 +#define TCA_TPC_DEBUG_capture_tca_rts_SIZE 1 + +#define TCA_TPC_DEBUG_captue_state_rts_SHIFT 12 +#define TCA_TPC_DEBUG_capture_tca_rts_SHIFT 13 + +#define TCA_TPC_DEBUG_captue_state_rts_MASK 0x00001000 +#define TCA_TPC_DEBUG_capture_tca_rts_MASK 0x00002000 + +#define TCA_TPC_DEBUG_MASK \ + (TCA_TPC_DEBUG_captue_state_rts_MASK | \ + TCA_TPC_DEBUG_capture_tca_rts_MASK) + +#define TCA_TPC_DEBUG(captue_state_rts, capture_tca_rts) \ + ((captue_state_rts << TCA_TPC_DEBUG_captue_state_rts_SHIFT) | \ + (capture_tca_rts << TCA_TPC_DEBUG_capture_tca_rts_SHIFT)) + +#define TCA_TPC_DEBUG_GET_captue_state_rts(tca_tpc_debug) \ + ((tca_tpc_debug & TCA_TPC_DEBUG_captue_state_rts_MASK) >> TCA_TPC_DEBUG_captue_state_rts_SHIFT) +#define TCA_TPC_DEBUG_GET_capture_tca_rts(tca_tpc_debug) \ + ((tca_tpc_debug & TCA_TPC_DEBUG_capture_tca_rts_MASK) >> TCA_TPC_DEBUG_capture_tca_rts_SHIFT) + +#define TCA_TPC_DEBUG_SET_captue_state_rts(tca_tpc_debug_reg, captue_state_rts) \ + tca_tpc_debug_reg = (tca_tpc_debug_reg & ~TCA_TPC_DEBUG_captue_state_rts_MASK) | (captue_state_rts << TCA_TPC_DEBUG_captue_state_rts_SHIFT) +#define TCA_TPC_DEBUG_SET_capture_tca_rts(tca_tpc_debug_reg, capture_tca_rts) \ + tca_tpc_debug_reg = (tca_tpc_debug_reg & ~TCA_TPC_DEBUG_capture_tca_rts_MASK) | (capture_tca_rts << TCA_TPC_DEBUG_capture_tca_rts_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tca_tpc_debug_t { + unsigned int : 12; + unsigned int captue_state_rts : TCA_TPC_DEBUG_captue_state_rts_SIZE; + unsigned int capture_tca_rts : TCA_TPC_DEBUG_capture_tca_rts_SIZE; + unsigned int : 18; + } tca_tpc_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tca_tpc_debug_t { + unsigned int : 18; + unsigned int capture_tca_rts : TCA_TPC_DEBUG_capture_tca_rts_SIZE; + unsigned int captue_state_rts : TCA_TPC_DEBUG_captue_state_rts_SIZE; + unsigned int : 12; + } tca_tpc_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tca_tpc_debug_t f; +} tca_tpc_debug_u; + + +/* + * TCB_CORE_DEBUG struct + */ + +#define TCB_CORE_DEBUG_access512_SIZE 1 +#define TCB_CORE_DEBUG_tiled_SIZE 1 +#define TCB_CORE_DEBUG_opcode_SIZE 3 +#define TCB_CORE_DEBUG_format_SIZE 6 +#define TCB_CORE_DEBUG_sector_format_SIZE 5 +#define TCB_CORE_DEBUG_sector_format512_SIZE 3 + +#define TCB_CORE_DEBUG_access512_SHIFT 0 +#define TCB_CORE_DEBUG_tiled_SHIFT 1 +#define TCB_CORE_DEBUG_opcode_SHIFT 4 +#define TCB_CORE_DEBUG_format_SHIFT 8 +#define TCB_CORE_DEBUG_sector_format_SHIFT 16 +#define TCB_CORE_DEBUG_sector_format512_SHIFT 24 + +#define TCB_CORE_DEBUG_access512_MASK 0x00000001 +#define TCB_CORE_DEBUG_tiled_MASK 0x00000002 +#define TCB_CORE_DEBUG_opcode_MASK 0x00000070 +#define TCB_CORE_DEBUG_format_MASK 0x00003f00 +#define TCB_CORE_DEBUG_sector_format_MASK 0x001f0000 +#define TCB_CORE_DEBUG_sector_format512_MASK 0x07000000 + +#define TCB_CORE_DEBUG_MASK \ + (TCB_CORE_DEBUG_access512_MASK | \ + TCB_CORE_DEBUG_tiled_MASK | \ + TCB_CORE_DEBUG_opcode_MASK | \ + TCB_CORE_DEBUG_format_MASK | \ + TCB_CORE_DEBUG_sector_format_MASK | \ + TCB_CORE_DEBUG_sector_format512_MASK) + +#define TCB_CORE_DEBUG(access512, tiled, opcode, format, sector_format, sector_format512) \ + ((access512 << TCB_CORE_DEBUG_access512_SHIFT) | \ + (tiled << TCB_CORE_DEBUG_tiled_SHIFT) | \ + (opcode << TCB_CORE_DEBUG_opcode_SHIFT) | \ + (format << TCB_CORE_DEBUG_format_SHIFT) | \ + (sector_format << TCB_CORE_DEBUG_sector_format_SHIFT) | \ + (sector_format512 << TCB_CORE_DEBUG_sector_format512_SHIFT)) + +#define TCB_CORE_DEBUG_GET_access512(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_access512_MASK) >> TCB_CORE_DEBUG_access512_SHIFT) +#define TCB_CORE_DEBUG_GET_tiled(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_tiled_MASK) >> TCB_CORE_DEBUG_tiled_SHIFT) +#define TCB_CORE_DEBUG_GET_opcode(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_opcode_MASK) >> TCB_CORE_DEBUG_opcode_SHIFT) +#define TCB_CORE_DEBUG_GET_format(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_format_MASK) >> TCB_CORE_DEBUG_format_SHIFT) +#define TCB_CORE_DEBUG_GET_sector_format(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_sector_format_MASK) >> TCB_CORE_DEBUG_sector_format_SHIFT) +#define TCB_CORE_DEBUG_GET_sector_format512(tcb_core_debug) \ + ((tcb_core_debug & TCB_CORE_DEBUG_sector_format512_MASK) >> TCB_CORE_DEBUG_sector_format512_SHIFT) + +#define TCB_CORE_DEBUG_SET_access512(tcb_core_debug_reg, access512) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_access512_MASK) | (access512 << TCB_CORE_DEBUG_access512_SHIFT) +#define TCB_CORE_DEBUG_SET_tiled(tcb_core_debug_reg, tiled) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_tiled_MASK) | (tiled << TCB_CORE_DEBUG_tiled_SHIFT) +#define TCB_CORE_DEBUG_SET_opcode(tcb_core_debug_reg, opcode) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_opcode_MASK) | (opcode << TCB_CORE_DEBUG_opcode_SHIFT) +#define TCB_CORE_DEBUG_SET_format(tcb_core_debug_reg, format) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_format_MASK) | (format << TCB_CORE_DEBUG_format_SHIFT) +#define TCB_CORE_DEBUG_SET_sector_format(tcb_core_debug_reg, sector_format) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_sector_format_MASK) | (sector_format << TCB_CORE_DEBUG_sector_format_SHIFT) +#define TCB_CORE_DEBUG_SET_sector_format512(tcb_core_debug_reg, sector_format512) \ + tcb_core_debug_reg = (tcb_core_debug_reg & ~TCB_CORE_DEBUG_sector_format512_MASK) | (sector_format512 << TCB_CORE_DEBUG_sector_format512_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_core_debug_t { + unsigned int access512 : TCB_CORE_DEBUG_access512_SIZE; + unsigned int tiled : TCB_CORE_DEBUG_tiled_SIZE; + unsigned int : 2; + unsigned int opcode : TCB_CORE_DEBUG_opcode_SIZE; + unsigned int : 1; + unsigned int format : TCB_CORE_DEBUG_format_SIZE; + unsigned int : 2; + unsigned int sector_format : TCB_CORE_DEBUG_sector_format_SIZE; + unsigned int : 3; + unsigned int sector_format512 : TCB_CORE_DEBUG_sector_format512_SIZE; + unsigned int : 5; + } tcb_core_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_core_debug_t { + unsigned int : 5; + unsigned int sector_format512 : TCB_CORE_DEBUG_sector_format512_SIZE; + unsigned int : 3; + unsigned int sector_format : TCB_CORE_DEBUG_sector_format_SIZE; + unsigned int : 2; + unsigned int format : TCB_CORE_DEBUG_format_SIZE; + unsigned int : 1; + unsigned int opcode : TCB_CORE_DEBUG_opcode_SIZE; + unsigned int : 2; + unsigned int tiled : TCB_CORE_DEBUG_tiled_SIZE; + unsigned int access512 : TCB_CORE_DEBUG_access512_SIZE; + } tcb_core_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_core_debug_t f; +} tcb_core_debug_u; + + +/* + * TCB_TAG0_DEBUG struct + */ + +#define TCB_TAG0_DEBUG_mem_read_cycle_SIZE 10 +#define TCB_TAG0_DEBUG_tag_access_cycle_SIZE 9 +#define TCB_TAG0_DEBUG_miss_stall_SIZE 1 +#define TCB_TAG0_DEBUG_num_feee_lines_SIZE 5 +#define TCB_TAG0_DEBUG_max_misses_SIZE 3 + +#define TCB_TAG0_DEBUG_mem_read_cycle_SHIFT 0 +#define TCB_TAG0_DEBUG_tag_access_cycle_SHIFT 12 +#define TCB_TAG0_DEBUG_miss_stall_SHIFT 23 +#define TCB_TAG0_DEBUG_num_feee_lines_SHIFT 24 +#define TCB_TAG0_DEBUG_max_misses_SHIFT 29 + +#define TCB_TAG0_DEBUG_mem_read_cycle_MASK 0x000003ff +#define TCB_TAG0_DEBUG_tag_access_cycle_MASK 0x001ff000 +#define TCB_TAG0_DEBUG_miss_stall_MASK 0x00800000 +#define TCB_TAG0_DEBUG_num_feee_lines_MASK 0x1f000000 +#define TCB_TAG0_DEBUG_max_misses_MASK 0xe0000000 + +#define TCB_TAG0_DEBUG_MASK \ + (TCB_TAG0_DEBUG_mem_read_cycle_MASK | \ + TCB_TAG0_DEBUG_tag_access_cycle_MASK | \ + TCB_TAG0_DEBUG_miss_stall_MASK | \ + TCB_TAG0_DEBUG_num_feee_lines_MASK | \ + TCB_TAG0_DEBUG_max_misses_MASK) + +#define TCB_TAG0_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \ + ((mem_read_cycle << TCB_TAG0_DEBUG_mem_read_cycle_SHIFT) | \ + (tag_access_cycle << TCB_TAG0_DEBUG_tag_access_cycle_SHIFT) | \ + (miss_stall << TCB_TAG0_DEBUG_miss_stall_SHIFT) | \ + (num_feee_lines << TCB_TAG0_DEBUG_num_feee_lines_SHIFT) | \ + (max_misses << TCB_TAG0_DEBUG_max_misses_SHIFT)) + +#define TCB_TAG0_DEBUG_GET_mem_read_cycle(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_mem_read_cycle_MASK) >> TCB_TAG0_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG0_DEBUG_GET_tag_access_cycle(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_tag_access_cycle_MASK) >> TCB_TAG0_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG0_DEBUG_GET_miss_stall(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_miss_stall_MASK) >> TCB_TAG0_DEBUG_miss_stall_SHIFT) +#define TCB_TAG0_DEBUG_GET_num_feee_lines(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_num_feee_lines_MASK) >> TCB_TAG0_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG0_DEBUG_GET_max_misses(tcb_tag0_debug) \ + ((tcb_tag0_debug & TCB_TAG0_DEBUG_max_misses_MASK) >> TCB_TAG0_DEBUG_max_misses_SHIFT) + +#define TCB_TAG0_DEBUG_SET_mem_read_cycle(tcb_tag0_debug_reg, mem_read_cycle) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG0_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG0_DEBUG_SET_tag_access_cycle(tcb_tag0_debug_reg, tag_access_cycle) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG0_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG0_DEBUG_SET_miss_stall(tcb_tag0_debug_reg, miss_stall) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG0_DEBUG_miss_stall_SHIFT) +#define TCB_TAG0_DEBUG_SET_num_feee_lines(tcb_tag0_debug_reg, num_feee_lines) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG0_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG0_DEBUG_SET_max_misses(tcb_tag0_debug_reg, max_misses) \ + tcb_tag0_debug_reg = (tcb_tag0_debug_reg & ~TCB_TAG0_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG0_DEBUG_max_misses_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_tag0_debug_t { + unsigned int mem_read_cycle : TCB_TAG0_DEBUG_mem_read_cycle_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG0_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int miss_stall : TCB_TAG0_DEBUG_miss_stall_SIZE; + unsigned int num_feee_lines : TCB_TAG0_DEBUG_num_feee_lines_SIZE; + unsigned int max_misses : TCB_TAG0_DEBUG_max_misses_SIZE; + } tcb_tag0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_tag0_debug_t { + unsigned int max_misses : TCB_TAG0_DEBUG_max_misses_SIZE; + unsigned int num_feee_lines : TCB_TAG0_DEBUG_num_feee_lines_SIZE; + unsigned int miss_stall : TCB_TAG0_DEBUG_miss_stall_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG0_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int mem_read_cycle : TCB_TAG0_DEBUG_mem_read_cycle_SIZE; + } tcb_tag0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_tag0_debug_t f; +} tcb_tag0_debug_u; + + +/* + * TCB_TAG1_DEBUG struct + */ + +#define TCB_TAG1_DEBUG_mem_read_cycle_SIZE 10 +#define TCB_TAG1_DEBUG_tag_access_cycle_SIZE 9 +#define TCB_TAG1_DEBUG_miss_stall_SIZE 1 +#define TCB_TAG1_DEBUG_num_feee_lines_SIZE 5 +#define TCB_TAG1_DEBUG_max_misses_SIZE 3 + +#define TCB_TAG1_DEBUG_mem_read_cycle_SHIFT 0 +#define TCB_TAG1_DEBUG_tag_access_cycle_SHIFT 12 +#define TCB_TAG1_DEBUG_miss_stall_SHIFT 23 +#define TCB_TAG1_DEBUG_num_feee_lines_SHIFT 24 +#define TCB_TAG1_DEBUG_max_misses_SHIFT 29 + +#define TCB_TAG1_DEBUG_mem_read_cycle_MASK 0x000003ff +#define TCB_TAG1_DEBUG_tag_access_cycle_MASK 0x001ff000 +#define TCB_TAG1_DEBUG_miss_stall_MASK 0x00800000 +#define TCB_TAG1_DEBUG_num_feee_lines_MASK 0x1f000000 +#define TCB_TAG1_DEBUG_max_misses_MASK 0xe0000000 + +#define TCB_TAG1_DEBUG_MASK \ + (TCB_TAG1_DEBUG_mem_read_cycle_MASK | \ + TCB_TAG1_DEBUG_tag_access_cycle_MASK | \ + TCB_TAG1_DEBUG_miss_stall_MASK | \ + TCB_TAG1_DEBUG_num_feee_lines_MASK | \ + TCB_TAG1_DEBUG_max_misses_MASK) + +#define TCB_TAG1_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \ + ((mem_read_cycle << TCB_TAG1_DEBUG_mem_read_cycle_SHIFT) | \ + (tag_access_cycle << TCB_TAG1_DEBUG_tag_access_cycle_SHIFT) | \ + (miss_stall << TCB_TAG1_DEBUG_miss_stall_SHIFT) | \ + (num_feee_lines << TCB_TAG1_DEBUG_num_feee_lines_SHIFT) | \ + (max_misses << TCB_TAG1_DEBUG_max_misses_SHIFT)) + +#define TCB_TAG1_DEBUG_GET_mem_read_cycle(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_mem_read_cycle_MASK) >> TCB_TAG1_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG1_DEBUG_GET_tag_access_cycle(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_tag_access_cycle_MASK) >> TCB_TAG1_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG1_DEBUG_GET_miss_stall(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_miss_stall_MASK) >> TCB_TAG1_DEBUG_miss_stall_SHIFT) +#define TCB_TAG1_DEBUG_GET_num_feee_lines(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_num_feee_lines_MASK) >> TCB_TAG1_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG1_DEBUG_GET_max_misses(tcb_tag1_debug) \ + ((tcb_tag1_debug & TCB_TAG1_DEBUG_max_misses_MASK) >> TCB_TAG1_DEBUG_max_misses_SHIFT) + +#define TCB_TAG1_DEBUG_SET_mem_read_cycle(tcb_tag1_debug_reg, mem_read_cycle) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG1_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG1_DEBUG_SET_tag_access_cycle(tcb_tag1_debug_reg, tag_access_cycle) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG1_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG1_DEBUG_SET_miss_stall(tcb_tag1_debug_reg, miss_stall) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG1_DEBUG_miss_stall_SHIFT) +#define TCB_TAG1_DEBUG_SET_num_feee_lines(tcb_tag1_debug_reg, num_feee_lines) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG1_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG1_DEBUG_SET_max_misses(tcb_tag1_debug_reg, max_misses) \ + tcb_tag1_debug_reg = (tcb_tag1_debug_reg & ~TCB_TAG1_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG1_DEBUG_max_misses_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_tag1_debug_t { + unsigned int mem_read_cycle : TCB_TAG1_DEBUG_mem_read_cycle_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG1_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int miss_stall : TCB_TAG1_DEBUG_miss_stall_SIZE; + unsigned int num_feee_lines : TCB_TAG1_DEBUG_num_feee_lines_SIZE; + unsigned int max_misses : TCB_TAG1_DEBUG_max_misses_SIZE; + } tcb_tag1_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_tag1_debug_t { + unsigned int max_misses : TCB_TAG1_DEBUG_max_misses_SIZE; + unsigned int num_feee_lines : TCB_TAG1_DEBUG_num_feee_lines_SIZE; + unsigned int miss_stall : TCB_TAG1_DEBUG_miss_stall_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG1_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int mem_read_cycle : TCB_TAG1_DEBUG_mem_read_cycle_SIZE; + } tcb_tag1_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_tag1_debug_t f; +} tcb_tag1_debug_u; + + +/* + * TCB_TAG2_DEBUG struct + */ + +#define TCB_TAG2_DEBUG_mem_read_cycle_SIZE 10 +#define TCB_TAG2_DEBUG_tag_access_cycle_SIZE 9 +#define TCB_TAG2_DEBUG_miss_stall_SIZE 1 +#define TCB_TAG2_DEBUG_num_feee_lines_SIZE 5 +#define TCB_TAG2_DEBUG_max_misses_SIZE 3 + +#define TCB_TAG2_DEBUG_mem_read_cycle_SHIFT 0 +#define TCB_TAG2_DEBUG_tag_access_cycle_SHIFT 12 +#define TCB_TAG2_DEBUG_miss_stall_SHIFT 23 +#define TCB_TAG2_DEBUG_num_feee_lines_SHIFT 24 +#define TCB_TAG2_DEBUG_max_misses_SHIFT 29 + +#define TCB_TAG2_DEBUG_mem_read_cycle_MASK 0x000003ff +#define TCB_TAG2_DEBUG_tag_access_cycle_MASK 0x001ff000 +#define TCB_TAG2_DEBUG_miss_stall_MASK 0x00800000 +#define TCB_TAG2_DEBUG_num_feee_lines_MASK 0x1f000000 +#define TCB_TAG2_DEBUG_max_misses_MASK 0xe0000000 + +#define TCB_TAG2_DEBUG_MASK \ + (TCB_TAG2_DEBUG_mem_read_cycle_MASK | \ + TCB_TAG2_DEBUG_tag_access_cycle_MASK | \ + TCB_TAG2_DEBUG_miss_stall_MASK | \ + TCB_TAG2_DEBUG_num_feee_lines_MASK | \ + TCB_TAG2_DEBUG_max_misses_MASK) + +#define TCB_TAG2_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \ + ((mem_read_cycle << TCB_TAG2_DEBUG_mem_read_cycle_SHIFT) | \ + (tag_access_cycle << TCB_TAG2_DEBUG_tag_access_cycle_SHIFT) | \ + (miss_stall << TCB_TAG2_DEBUG_miss_stall_SHIFT) | \ + (num_feee_lines << TCB_TAG2_DEBUG_num_feee_lines_SHIFT) | \ + (max_misses << TCB_TAG2_DEBUG_max_misses_SHIFT)) + +#define TCB_TAG2_DEBUG_GET_mem_read_cycle(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_mem_read_cycle_MASK) >> TCB_TAG2_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG2_DEBUG_GET_tag_access_cycle(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_tag_access_cycle_MASK) >> TCB_TAG2_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG2_DEBUG_GET_miss_stall(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_miss_stall_MASK) >> TCB_TAG2_DEBUG_miss_stall_SHIFT) +#define TCB_TAG2_DEBUG_GET_num_feee_lines(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_num_feee_lines_MASK) >> TCB_TAG2_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG2_DEBUG_GET_max_misses(tcb_tag2_debug) \ + ((tcb_tag2_debug & TCB_TAG2_DEBUG_max_misses_MASK) >> TCB_TAG2_DEBUG_max_misses_SHIFT) + +#define TCB_TAG2_DEBUG_SET_mem_read_cycle(tcb_tag2_debug_reg, mem_read_cycle) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG2_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG2_DEBUG_SET_tag_access_cycle(tcb_tag2_debug_reg, tag_access_cycle) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG2_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG2_DEBUG_SET_miss_stall(tcb_tag2_debug_reg, miss_stall) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG2_DEBUG_miss_stall_SHIFT) +#define TCB_TAG2_DEBUG_SET_num_feee_lines(tcb_tag2_debug_reg, num_feee_lines) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG2_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG2_DEBUG_SET_max_misses(tcb_tag2_debug_reg, max_misses) \ + tcb_tag2_debug_reg = (tcb_tag2_debug_reg & ~TCB_TAG2_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG2_DEBUG_max_misses_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_tag2_debug_t { + unsigned int mem_read_cycle : TCB_TAG2_DEBUG_mem_read_cycle_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG2_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int miss_stall : TCB_TAG2_DEBUG_miss_stall_SIZE; + unsigned int num_feee_lines : TCB_TAG2_DEBUG_num_feee_lines_SIZE; + unsigned int max_misses : TCB_TAG2_DEBUG_max_misses_SIZE; + } tcb_tag2_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_tag2_debug_t { + unsigned int max_misses : TCB_TAG2_DEBUG_max_misses_SIZE; + unsigned int num_feee_lines : TCB_TAG2_DEBUG_num_feee_lines_SIZE; + unsigned int miss_stall : TCB_TAG2_DEBUG_miss_stall_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG2_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int mem_read_cycle : TCB_TAG2_DEBUG_mem_read_cycle_SIZE; + } tcb_tag2_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_tag2_debug_t f; +} tcb_tag2_debug_u; + + +/* + * TCB_TAG3_DEBUG struct + */ + +#define TCB_TAG3_DEBUG_mem_read_cycle_SIZE 10 +#define TCB_TAG3_DEBUG_tag_access_cycle_SIZE 9 +#define TCB_TAG3_DEBUG_miss_stall_SIZE 1 +#define TCB_TAG3_DEBUG_num_feee_lines_SIZE 5 +#define TCB_TAG3_DEBUG_max_misses_SIZE 3 + +#define TCB_TAG3_DEBUG_mem_read_cycle_SHIFT 0 +#define TCB_TAG3_DEBUG_tag_access_cycle_SHIFT 12 +#define TCB_TAG3_DEBUG_miss_stall_SHIFT 23 +#define TCB_TAG3_DEBUG_num_feee_lines_SHIFT 24 +#define TCB_TAG3_DEBUG_max_misses_SHIFT 29 + +#define TCB_TAG3_DEBUG_mem_read_cycle_MASK 0x000003ff +#define TCB_TAG3_DEBUG_tag_access_cycle_MASK 0x001ff000 +#define TCB_TAG3_DEBUG_miss_stall_MASK 0x00800000 +#define TCB_TAG3_DEBUG_num_feee_lines_MASK 0x1f000000 +#define TCB_TAG3_DEBUG_max_misses_MASK 0xe0000000 + +#define TCB_TAG3_DEBUG_MASK \ + (TCB_TAG3_DEBUG_mem_read_cycle_MASK | \ + TCB_TAG3_DEBUG_tag_access_cycle_MASK | \ + TCB_TAG3_DEBUG_miss_stall_MASK | \ + TCB_TAG3_DEBUG_num_feee_lines_MASK | \ + TCB_TAG3_DEBUG_max_misses_MASK) + +#define TCB_TAG3_DEBUG(mem_read_cycle, tag_access_cycle, miss_stall, num_feee_lines, max_misses) \ + ((mem_read_cycle << TCB_TAG3_DEBUG_mem_read_cycle_SHIFT) | \ + (tag_access_cycle << TCB_TAG3_DEBUG_tag_access_cycle_SHIFT) | \ + (miss_stall << TCB_TAG3_DEBUG_miss_stall_SHIFT) | \ + (num_feee_lines << TCB_TAG3_DEBUG_num_feee_lines_SHIFT) | \ + (max_misses << TCB_TAG3_DEBUG_max_misses_SHIFT)) + +#define TCB_TAG3_DEBUG_GET_mem_read_cycle(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_mem_read_cycle_MASK) >> TCB_TAG3_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG3_DEBUG_GET_tag_access_cycle(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_tag_access_cycle_MASK) >> TCB_TAG3_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG3_DEBUG_GET_miss_stall(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_miss_stall_MASK) >> TCB_TAG3_DEBUG_miss_stall_SHIFT) +#define TCB_TAG3_DEBUG_GET_num_feee_lines(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_num_feee_lines_MASK) >> TCB_TAG3_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG3_DEBUG_GET_max_misses(tcb_tag3_debug) \ + ((tcb_tag3_debug & TCB_TAG3_DEBUG_max_misses_MASK) >> TCB_TAG3_DEBUG_max_misses_SHIFT) + +#define TCB_TAG3_DEBUG_SET_mem_read_cycle(tcb_tag3_debug_reg, mem_read_cycle) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_mem_read_cycle_MASK) | (mem_read_cycle << TCB_TAG3_DEBUG_mem_read_cycle_SHIFT) +#define TCB_TAG3_DEBUG_SET_tag_access_cycle(tcb_tag3_debug_reg, tag_access_cycle) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_tag_access_cycle_MASK) | (tag_access_cycle << TCB_TAG3_DEBUG_tag_access_cycle_SHIFT) +#define TCB_TAG3_DEBUG_SET_miss_stall(tcb_tag3_debug_reg, miss_stall) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_miss_stall_MASK) | (miss_stall << TCB_TAG3_DEBUG_miss_stall_SHIFT) +#define TCB_TAG3_DEBUG_SET_num_feee_lines(tcb_tag3_debug_reg, num_feee_lines) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_num_feee_lines_MASK) | (num_feee_lines << TCB_TAG3_DEBUG_num_feee_lines_SHIFT) +#define TCB_TAG3_DEBUG_SET_max_misses(tcb_tag3_debug_reg, max_misses) \ + tcb_tag3_debug_reg = (tcb_tag3_debug_reg & ~TCB_TAG3_DEBUG_max_misses_MASK) | (max_misses << TCB_TAG3_DEBUG_max_misses_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_tag3_debug_t { + unsigned int mem_read_cycle : TCB_TAG3_DEBUG_mem_read_cycle_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG3_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int miss_stall : TCB_TAG3_DEBUG_miss_stall_SIZE; + unsigned int num_feee_lines : TCB_TAG3_DEBUG_num_feee_lines_SIZE; + unsigned int max_misses : TCB_TAG3_DEBUG_max_misses_SIZE; + } tcb_tag3_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_tag3_debug_t { + unsigned int max_misses : TCB_TAG3_DEBUG_max_misses_SIZE; + unsigned int num_feee_lines : TCB_TAG3_DEBUG_num_feee_lines_SIZE; + unsigned int miss_stall : TCB_TAG3_DEBUG_miss_stall_SIZE; + unsigned int : 2; + unsigned int tag_access_cycle : TCB_TAG3_DEBUG_tag_access_cycle_SIZE; + unsigned int : 2; + unsigned int mem_read_cycle : TCB_TAG3_DEBUG_mem_read_cycle_SIZE; + } tcb_tag3_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_tag3_debug_t f; +} tcb_tag3_debug_u; + + +/* + * TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG struct + */ + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE 1 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE 5 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE 16 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE 1 + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT 0 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT 2 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT 4 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT 5 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT 6 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT 7 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT 12 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT 28 + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK 0x00000001 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK 0x00000004 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK 0x00000010 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK 0x00000020 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK 0x00000040 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK 0x00000f80 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK 0x0ffff000 +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK 0x10000000 + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_MASK \ + (TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK | \ + TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG(left_done, fg0_sends_left, one_sector_to_go_left_q, no_sectors_to_go, update_left, sector_mask_left_count_q, sector_mask_left_q, valid_left_q) \ + ((left_done << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT) | \ + (fg0_sends_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT) | \ + (one_sector_to_go_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT) | \ + (no_sectors_to_go << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT) | \ + (update_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT) | \ + (sector_mask_left_count_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT) | \ + (sector_mask_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT) | \ + (valid_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT)) + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_left_done(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_fg0_sends_left(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_one_sector_to_go_left_q(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_no_sectors_to_go(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_update_left(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_sector_mask_left_count_q(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_sector_mask_left_q(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_GET_valid_left_q(tcb_fetch_gen_sector_walker0_debug) \ + ((tcb_fetch_gen_sector_walker0_debug & TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) >> TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT) + +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_left_done(tcb_fetch_gen_sector_walker0_debug_reg, left_done) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_MASK) | (left_done << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_fg0_sends_left(tcb_fetch_gen_sector_walker0_debug_reg, fg0_sends_left) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_MASK) | (fg0_sends_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_one_sector_to_go_left_q(tcb_fetch_gen_sector_walker0_debug_reg, one_sector_to_go_left_q) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_MASK) | (one_sector_to_go_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_no_sectors_to_go(tcb_fetch_gen_sector_walker0_debug_reg, no_sectors_to_go) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_MASK) | (no_sectors_to_go << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_update_left(tcb_fetch_gen_sector_walker0_debug_reg, update_left) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_MASK) | (update_left << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_sector_mask_left_count_q(tcb_fetch_gen_sector_walker0_debug_reg, sector_mask_left_count_q) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_MASK) | (sector_mask_left_count_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_sector_mask_left_q(tcb_fetch_gen_sector_walker0_debug_reg, sector_mask_left_q) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_MASK) | (sector_mask_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SHIFT) +#define TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_SET_valid_left_q(tcb_fetch_gen_sector_walker0_debug_reg, valid_left_q) \ + tcb_fetch_gen_sector_walker0_debug_reg = (tcb_fetch_gen_sector_walker0_debug_reg & ~TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_MASK) | (valid_left_q << TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_sector_walker0_debug_t { + unsigned int left_done : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE; + unsigned int : 1; + unsigned int fg0_sends_left : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE; + unsigned int : 1; + unsigned int one_sector_to_go_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE; + unsigned int no_sectors_to_go : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE; + unsigned int update_left : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE; + unsigned int sector_mask_left_count_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE; + unsigned int sector_mask_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE; + unsigned int valid_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE; + unsigned int : 3; + } tcb_fetch_gen_sector_walker0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_sector_walker0_debug_t { + unsigned int : 3; + unsigned int valid_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_valid_left_q_SIZE; + unsigned int sector_mask_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_q_SIZE; + unsigned int sector_mask_left_count_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_sector_mask_left_count_q_SIZE; + unsigned int update_left : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_update_left_SIZE; + unsigned int no_sectors_to_go : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_no_sectors_to_go_SIZE; + unsigned int one_sector_to_go_left_q : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_one_sector_to_go_left_q_SIZE; + unsigned int : 1; + unsigned int fg0_sends_left : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_fg0_sends_left_SIZE; + unsigned int : 1; + unsigned int left_done : TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG_left_done_SIZE; + } tcb_fetch_gen_sector_walker0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_fetch_gen_sector_walker0_debug_t f; +} tcb_fetch_gen_sector_walker0_debug_u; + + +/* + * TCB_FETCH_GEN_WALKER_DEBUG struct + */ + +#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE 2 +#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE 2 +#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE 1 +#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE 3 +#define TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE 1 +#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE 4 + +#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT 4 +#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT 6 +#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT 11 +#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT 12 +#define TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT 15 +#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT 16 + +#define TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK 0x00000030 +#define TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK 0x000000c0 +#define TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK 0x00000800 +#define TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK 0x00007000 +#define TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK 0x00008000 +#define TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK 0x000f0000 + +#define TCB_FETCH_GEN_WALKER_DEBUG_MASK \ + (TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK | \ + TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) + +#define TCB_FETCH_GEN_WALKER_DEBUG(quad_sel_left, set_sel_left, right_eq_left, ff_fg_type512, busy, setquads_to_send) \ + ((quad_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT) | \ + (set_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT) | \ + (right_eq_left << TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT) | \ + (ff_fg_type512 << TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT) | \ + (busy << TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT) | \ + (setquads_to_send << TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT)) + +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_quad_sel_left(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_set_sel_left(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_right_eq_left(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_ff_fg_type512(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_busy(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_GET_setquads_to_send(tcb_fetch_gen_walker_debug) \ + ((tcb_fetch_gen_walker_debug & TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) >> TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT) + +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_quad_sel_left(tcb_fetch_gen_walker_debug_reg, quad_sel_left) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_MASK) | (quad_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_set_sel_left(tcb_fetch_gen_walker_debug_reg, set_sel_left) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_MASK) | (set_sel_left << TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_right_eq_left(tcb_fetch_gen_walker_debug_reg, right_eq_left) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_MASK) | (right_eq_left << TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_ff_fg_type512(tcb_fetch_gen_walker_debug_reg, ff_fg_type512) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_MASK) | (ff_fg_type512 << TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_busy(tcb_fetch_gen_walker_debug_reg, busy) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_busy_MASK) | (busy << TCB_FETCH_GEN_WALKER_DEBUG_busy_SHIFT) +#define TCB_FETCH_GEN_WALKER_DEBUG_SET_setquads_to_send(tcb_fetch_gen_walker_debug_reg, setquads_to_send) \ + tcb_fetch_gen_walker_debug_reg = (tcb_fetch_gen_walker_debug_reg & ~TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_MASK) | (setquads_to_send << TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_walker_debug_t { + unsigned int : 4; + unsigned int quad_sel_left : TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE; + unsigned int set_sel_left : TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE; + unsigned int : 3; + unsigned int right_eq_left : TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE; + unsigned int ff_fg_type512 : TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE; + unsigned int busy : TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE; + unsigned int setquads_to_send : TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE; + unsigned int : 12; + } tcb_fetch_gen_walker_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_walker_debug_t { + unsigned int : 12; + unsigned int setquads_to_send : TCB_FETCH_GEN_WALKER_DEBUG_setquads_to_send_SIZE; + unsigned int busy : TCB_FETCH_GEN_WALKER_DEBUG_busy_SIZE; + unsigned int ff_fg_type512 : TCB_FETCH_GEN_WALKER_DEBUG_ff_fg_type512_SIZE; + unsigned int right_eq_left : TCB_FETCH_GEN_WALKER_DEBUG_right_eq_left_SIZE; + unsigned int : 3; + unsigned int set_sel_left : TCB_FETCH_GEN_WALKER_DEBUG_set_sel_left_SIZE; + unsigned int quad_sel_left : TCB_FETCH_GEN_WALKER_DEBUG_quad_sel_left_SIZE; + unsigned int : 4; + } tcb_fetch_gen_walker_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_fetch_gen_walker_debug_t f; +} tcb_fetch_gen_walker_debug_u; + + +/* + * TCB_FETCH_GEN_PIPE0_DEBUG struct + */ + +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE 12 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE 5 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE 2 +#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE 2 +#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE 1 +#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE 1 + +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT 0 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT 2 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT 4 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT 16 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT 21 +#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT 23 +#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT 24 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT 25 +#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT 26 +#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT 28 +#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT 30 + +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK 0x00000001 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK 0x00000004 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK 0x0000fff0 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK 0x001f0000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK 0x00600000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK 0x00800000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK 0x01000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK 0x02000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK 0x0c000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK 0x10000000 +#define TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK 0x40000000 + +#define TCB_FETCH_GEN_PIPE0_DEBUG_MASK \ + (TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK | \ + TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) + +#define TCB_FETCH_GEN_PIPE0_DEBUG(tc0_arb_rts, ga_out_rts, tc_arb_format, tc_arb_fmsopcode, tc_arb_request_type, busy, fgo_busy, ga_busy, mc_sel_q, valid_q, arb_rtr) \ + ((tc0_arb_rts << TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT) | \ + (ga_out_rts << TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT) | \ + (tc_arb_format << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT) | \ + (tc_arb_fmsopcode << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT) | \ + (tc_arb_request_type << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT) | \ + (busy << TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT) | \ + (fgo_busy << TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT) | \ + (ga_busy << TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT) | \ + (mc_sel_q << TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT) | \ + (valid_q << TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT) | \ + (arb_rtr << TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT)) + +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc0_arb_rts(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_ga_out_rts(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_format(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_fmsopcode(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_tc_arb_request_type(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_busy(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_fgo_busy(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_ga_busy(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_mc_sel_q(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_valid_q(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_GET_arb_RTR(tcb_fetch_gen_pipe0_debug) \ + ((tcb_fetch_gen_pipe0_debug & TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) >> TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT) + +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc0_arb_rts(tcb_fetch_gen_pipe0_debug_reg, tc0_arb_rts) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_MASK) | (tc0_arb_rts << TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_ga_out_rts(tcb_fetch_gen_pipe0_debug_reg, ga_out_rts) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_MASK) | (ga_out_rts << TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_format(tcb_fetch_gen_pipe0_debug_reg, tc_arb_format) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_MASK) | (tc_arb_format << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_fmsopcode(tcb_fetch_gen_pipe0_debug_reg, tc_arb_fmsopcode) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_MASK) | (tc_arb_fmsopcode << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_tc_arb_request_type(tcb_fetch_gen_pipe0_debug_reg, tc_arb_request_type) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_MASK) | (tc_arb_request_type << TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_busy(tcb_fetch_gen_pipe0_debug_reg, busy) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_busy_MASK) | (busy << TCB_FETCH_GEN_PIPE0_DEBUG_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_fgo_busy(tcb_fetch_gen_pipe0_debug_reg, fgo_busy) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_MASK) | (fgo_busy << TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_ga_busy(tcb_fetch_gen_pipe0_debug_reg, ga_busy) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_MASK) | (ga_busy << TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_mc_sel_q(tcb_fetch_gen_pipe0_debug_reg, mc_sel_q) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_MASK) | (mc_sel_q << TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_valid_q(tcb_fetch_gen_pipe0_debug_reg, valid_q) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_MASK) | (valid_q << TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SHIFT) +#define TCB_FETCH_GEN_PIPE0_DEBUG_SET_arb_RTR(tcb_fetch_gen_pipe0_debug_reg, arb_rtr) \ + tcb_fetch_gen_pipe0_debug_reg = (tcb_fetch_gen_pipe0_debug_reg & ~TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_MASK) | (arb_rtr << TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_pipe0_debug_t { + unsigned int tc0_arb_rts : TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE; + unsigned int : 1; + unsigned int ga_out_rts : TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE; + unsigned int : 1; + unsigned int tc_arb_format : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE; + unsigned int tc_arb_fmsopcode : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE; + unsigned int tc_arb_request_type : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE; + unsigned int busy : TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE; + unsigned int fgo_busy : TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE; + unsigned int ga_busy : TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE; + unsigned int mc_sel_q : TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE; + unsigned int valid_q : TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE; + unsigned int : 1; + unsigned int arb_rtr : TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE; + unsigned int : 1; + } tcb_fetch_gen_pipe0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcb_fetch_gen_pipe0_debug_t { + unsigned int : 1; + unsigned int arb_rtr : TCB_FETCH_GEN_PIPE0_DEBUG_arb_RTR_SIZE; + unsigned int : 1; + unsigned int valid_q : TCB_FETCH_GEN_PIPE0_DEBUG_valid_q_SIZE; + unsigned int mc_sel_q : TCB_FETCH_GEN_PIPE0_DEBUG_mc_sel_q_SIZE; + unsigned int ga_busy : TCB_FETCH_GEN_PIPE0_DEBUG_ga_busy_SIZE; + unsigned int fgo_busy : TCB_FETCH_GEN_PIPE0_DEBUG_fgo_busy_SIZE; + unsigned int busy : TCB_FETCH_GEN_PIPE0_DEBUG_busy_SIZE; + unsigned int tc_arb_request_type : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_request_type_SIZE; + unsigned int tc_arb_fmsopcode : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_fmsopcode_SIZE; + unsigned int tc_arb_format : TCB_FETCH_GEN_PIPE0_DEBUG_tc_arb_format_SIZE; + unsigned int : 1; + unsigned int ga_out_rts : TCB_FETCH_GEN_PIPE0_DEBUG_ga_out_rts_SIZE; + unsigned int : 1; + unsigned int tc0_arb_rts : TCB_FETCH_GEN_PIPE0_DEBUG_tc0_arb_rts_SIZE; + } tcb_fetch_gen_pipe0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcb_fetch_gen_pipe0_debug_t f; +} tcb_fetch_gen_pipe0_debug_u; + + +/* + * TCD_INPUT0_DEBUG struct + */ + +#define TCD_INPUT0_DEBUG_empty_SIZE 1 +#define TCD_INPUT0_DEBUG_full_SIZE 1 +#define TCD_INPUT0_DEBUG_valid_q1_SIZE 1 +#define TCD_INPUT0_DEBUG_cnt_q1_SIZE 2 +#define TCD_INPUT0_DEBUG_last_send_q1_SIZE 1 +#define TCD_INPUT0_DEBUG_ip_send_SIZE 1 +#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE 1 +#define TCD_INPUT0_DEBUG_ipbuf_busy_SIZE 1 + +#define TCD_INPUT0_DEBUG_empty_SHIFT 16 +#define TCD_INPUT0_DEBUG_full_SHIFT 17 +#define TCD_INPUT0_DEBUG_valid_q1_SHIFT 20 +#define TCD_INPUT0_DEBUG_cnt_q1_SHIFT 21 +#define TCD_INPUT0_DEBUG_last_send_q1_SHIFT 23 +#define TCD_INPUT0_DEBUG_ip_send_SHIFT 24 +#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT 25 +#define TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT 26 + +#define TCD_INPUT0_DEBUG_empty_MASK 0x00010000 +#define TCD_INPUT0_DEBUG_full_MASK 0x00020000 +#define TCD_INPUT0_DEBUG_valid_q1_MASK 0x00100000 +#define TCD_INPUT0_DEBUG_cnt_q1_MASK 0x00600000 +#define TCD_INPUT0_DEBUG_last_send_q1_MASK 0x00800000 +#define TCD_INPUT0_DEBUG_ip_send_MASK 0x01000000 +#define TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK 0x02000000 +#define TCD_INPUT0_DEBUG_ipbuf_busy_MASK 0x04000000 + +#define TCD_INPUT0_DEBUG_MASK \ + (TCD_INPUT0_DEBUG_empty_MASK | \ + TCD_INPUT0_DEBUG_full_MASK | \ + TCD_INPUT0_DEBUG_valid_q1_MASK | \ + TCD_INPUT0_DEBUG_cnt_q1_MASK | \ + TCD_INPUT0_DEBUG_last_send_q1_MASK | \ + TCD_INPUT0_DEBUG_ip_send_MASK | \ + TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK | \ + TCD_INPUT0_DEBUG_ipbuf_busy_MASK) + +#define TCD_INPUT0_DEBUG(empty, full, valid_q1, cnt_q1, last_send_q1, ip_send, ipbuf_dxt_send, ipbuf_busy) \ + ((empty << TCD_INPUT0_DEBUG_empty_SHIFT) | \ + (full << TCD_INPUT0_DEBUG_full_SHIFT) | \ + (valid_q1 << TCD_INPUT0_DEBUG_valid_q1_SHIFT) | \ + (cnt_q1 << TCD_INPUT0_DEBUG_cnt_q1_SHIFT) | \ + (last_send_q1 << TCD_INPUT0_DEBUG_last_send_q1_SHIFT) | \ + (ip_send << TCD_INPUT0_DEBUG_ip_send_SHIFT) | \ + (ipbuf_dxt_send << TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT) | \ + (ipbuf_busy << TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT)) + +#define TCD_INPUT0_DEBUG_GET_empty(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_empty_MASK) >> TCD_INPUT0_DEBUG_empty_SHIFT) +#define TCD_INPUT0_DEBUG_GET_full(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_full_MASK) >> TCD_INPUT0_DEBUG_full_SHIFT) +#define TCD_INPUT0_DEBUG_GET_valid_q1(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_valid_q1_MASK) >> TCD_INPUT0_DEBUG_valid_q1_SHIFT) +#define TCD_INPUT0_DEBUG_GET_cnt_q1(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_cnt_q1_MASK) >> TCD_INPUT0_DEBUG_cnt_q1_SHIFT) +#define TCD_INPUT0_DEBUG_GET_last_send_q1(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_last_send_q1_MASK) >> TCD_INPUT0_DEBUG_last_send_q1_SHIFT) +#define TCD_INPUT0_DEBUG_GET_ip_send(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_ip_send_MASK) >> TCD_INPUT0_DEBUG_ip_send_SHIFT) +#define TCD_INPUT0_DEBUG_GET_ipbuf_dxt_send(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK) >> TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT) +#define TCD_INPUT0_DEBUG_GET_ipbuf_busy(tcd_input0_debug) \ + ((tcd_input0_debug & TCD_INPUT0_DEBUG_ipbuf_busy_MASK) >> TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT) + +#define TCD_INPUT0_DEBUG_SET_empty(tcd_input0_debug_reg, empty) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_empty_MASK) | (empty << TCD_INPUT0_DEBUG_empty_SHIFT) +#define TCD_INPUT0_DEBUG_SET_full(tcd_input0_debug_reg, full) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_full_MASK) | (full << TCD_INPUT0_DEBUG_full_SHIFT) +#define TCD_INPUT0_DEBUG_SET_valid_q1(tcd_input0_debug_reg, valid_q1) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_valid_q1_MASK) | (valid_q1 << TCD_INPUT0_DEBUG_valid_q1_SHIFT) +#define TCD_INPUT0_DEBUG_SET_cnt_q1(tcd_input0_debug_reg, cnt_q1) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_cnt_q1_MASK) | (cnt_q1 << TCD_INPUT0_DEBUG_cnt_q1_SHIFT) +#define TCD_INPUT0_DEBUG_SET_last_send_q1(tcd_input0_debug_reg, last_send_q1) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_last_send_q1_MASK) | (last_send_q1 << TCD_INPUT0_DEBUG_last_send_q1_SHIFT) +#define TCD_INPUT0_DEBUG_SET_ip_send(tcd_input0_debug_reg, ip_send) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ip_send_MASK) | (ip_send << TCD_INPUT0_DEBUG_ip_send_SHIFT) +#define TCD_INPUT0_DEBUG_SET_ipbuf_dxt_send(tcd_input0_debug_reg, ipbuf_dxt_send) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ipbuf_dxt_send_MASK) | (ipbuf_dxt_send << TCD_INPUT0_DEBUG_ipbuf_dxt_send_SHIFT) +#define TCD_INPUT0_DEBUG_SET_ipbuf_busy(tcd_input0_debug_reg, ipbuf_busy) \ + tcd_input0_debug_reg = (tcd_input0_debug_reg & ~TCD_INPUT0_DEBUG_ipbuf_busy_MASK) | (ipbuf_busy << TCD_INPUT0_DEBUG_ipbuf_busy_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_input0_debug_t { + unsigned int : 16; + unsigned int empty : TCD_INPUT0_DEBUG_empty_SIZE; + unsigned int full : TCD_INPUT0_DEBUG_full_SIZE; + unsigned int : 2; + unsigned int valid_q1 : TCD_INPUT0_DEBUG_valid_q1_SIZE; + unsigned int cnt_q1 : TCD_INPUT0_DEBUG_cnt_q1_SIZE; + unsigned int last_send_q1 : TCD_INPUT0_DEBUG_last_send_q1_SIZE; + unsigned int ip_send : TCD_INPUT0_DEBUG_ip_send_SIZE; + unsigned int ipbuf_dxt_send : TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE; + unsigned int ipbuf_busy : TCD_INPUT0_DEBUG_ipbuf_busy_SIZE; + unsigned int : 5; + } tcd_input0_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_input0_debug_t { + unsigned int : 5; + unsigned int ipbuf_busy : TCD_INPUT0_DEBUG_ipbuf_busy_SIZE; + unsigned int ipbuf_dxt_send : TCD_INPUT0_DEBUG_ipbuf_dxt_send_SIZE; + unsigned int ip_send : TCD_INPUT0_DEBUG_ip_send_SIZE; + unsigned int last_send_q1 : TCD_INPUT0_DEBUG_last_send_q1_SIZE; + unsigned int cnt_q1 : TCD_INPUT0_DEBUG_cnt_q1_SIZE; + unsigned int valid_q1 : TCD_INPUT0_DEBUG_valid_q1_SIZE; + unsigned int : 2; + unsigned int full : TCD_INPUT0_DEBUG_full_SIZE; + unsigned int empty : TCD_INPUT0_DEBUG_empty_SIZE; + unsigned int : 16; + } tcd_input0_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_input0_debug_t f; +} tcd_input0_debug_u; + + +/* + * TCD_DEGAMMA_DEBUG struct + */ + +#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE 2 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE 1 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE 1 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE 1 +#define TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE 1 +#define TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE 1 + +#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT 0 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT 2 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT 3 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT 4 +#define TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT 5 +#define TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT 6 + +#define TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK 0x00000003 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK 0x00000004 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK 0x00000008 +#define TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK 0x00000010 +#define TCD_DEGAMMA_DEBUG_dgmm_stall_MASK 0x00000020 +#define TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK 0x00000040 + +#define TCD_DEGAMMA_DEBUG_MASK \ + (TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_stall_MASK | \ + TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) + +#define TCD_DEGAMMA_DEBUG(dgmm_ftfconv_dgmmen, dgmm_ctrl_dgmm8, dgmm_ctrl_last_send, dgmm_ctrl_send, dgmm_stall, dgmm_pstate) \ + ((dgmm_ftfconv_dgmmen << TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT) | \ + (dgmm_ctrl_dgmm8 << TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT) | \ + (dgmm_ctrl_last_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT) | \ + (dgmm_ctrl_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT) | \ + (dgmm_stall << TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT) | \ + (dgmm_pstate << TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT)) + +#define TCD_DEGAMMA_DEBUG_GET_dgmm_ftfconv_dgmmen(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_dgmm8(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_last_send(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_ctrl_send(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_stall(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_stall_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT) +#define TCD_DEGAMMA_DEBUG_GET_dgmm_pstate(tcd_degamma_debug) \ + ((tcd_degamma_debug & TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) >> TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT) + +#define TCD_DEGAMMA_DEBUG_SET_dgmm_ftfconv_dgmmen(tcd_degamma_debug_reg, dgmm_ftfconv_dgmmen) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_MASK) | (dgmm_ftfconv_dgmmen << TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_dgmm8(tcd_degamma_debug_reg, dgmm_ctrl_dgmm8) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_MASK) | (dgmm_ctrl_dgmm8 << TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_last_send(tcd_degamma_debug_reg, dgmm_ctrl_last_send) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_MASK) | (dgmm_ctrl_last_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_ctrl_send(tcd_degamma_debug_reg, dgmm_ctrl_send) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_MASK) | (dgmm_ctrl_send << TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_stall(tcd_degamma_debug_reg, dgmm_stall) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_stall_MASK) | (dgmm_stall << TCD_DEGAMMA_DEBUG_dgmm_stall_SHIFT) +#define TCD_DEGAMMA_DEBUG_SET_dgmm_pstate(tcd_degamma_debug_reg, dgmm_pstate) \ + tcd_degamma_debug_reg = (tcd_degamma_debug_reg & ~TCD_DEGAMMA_DEBUG_dgmm_pstate_MASK) | (dgmm_pstate << TCD_DEGAMMA_DEBUG_dgmm_pstate_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_degamma_debug_t { + unsigned int dgmm_ftfconv_dgmmen : TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE; + unsigned int dgmm_ctrl_dgmm8 : TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE; + unsigned int dgmm_ctrl_last_send : TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE; + unsigned int dgmm_ctrl_send : TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE; + unsigned int dgmm_stall : TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE; + unsigned int dgmm_pstate : TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE; + unsigned int : 25; + } tcd_degamma_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_degamma_debug_t { + unsigned int : 25; + unsigned int dgmm_pstate : TCD_DEGAMMA_DEBUG_dgmm_pstate_SIZE; + unsigned int dgmm_stall : TCD_DEGAMMA_DEBUG_dgmm_stall_SIZE; + unsigned int dgmm_ctrl_send : TCD_DEGAMMA_DEBUG_dgmm_ctrl_send_SIZE; + unsigned int dgmm_ctrl_last_send : TCD_DEGAMMA_DEBUG_dgmm_ctrl_last_send_SIZE; + unsigned int dgmm_ctrl_dgmm8 : TCD_DEGAMMA_DEBUG_dgmm_ctrl_dgmm8_SIZE; + unsigned int dgmm_ftfconv_dgmmen : TCD_DEGAMMA_DEBUG_dgmm_ftfconv_dgmmen_SIZE; + } tcd_degamma_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_degamma_debug_t f; +} tcd_degamma_debug_u; + + +/* + * TCD_DXTMUX_SCTARB_DEBUG struct + */ + +#define TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE 1 +#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE 1 + +#define TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT 9 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT 10 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT 11 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT 15 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT 16 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT 20 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT 27 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT 28 +#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT 29 + +#define TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK 0x00000200 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK 0x00000400 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK 0x00000800 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK 0x00008000 +#define TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK 0x00010000 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK 0x00100000 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK 0x08000000 +#define TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK 0x10000000 +#define TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK 0x20000000 + +#define TCD_DXTMUX_SCTARB_DEBUG_MASK \ + (TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK | \ + TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) + +#define TCD_DXTMUX_SCTARB_DEBUG(pstate, sctrmx_rtr, dxtc_rtr, sctrarb_multcyl_send, sctrmx0_sctrarb_rts, dxtc_sctrarb_send, dxtc_dgmmpd_last_send, dxtc_dgmmpd_send, dcmp_mux_send) \ + ((pstate << TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT) | \ + (sctrmx_rtr << TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT) | \ + (dxtc_rtr << TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT) | \ + (sctrarb_multcyl_send << TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT) | \ + (sctrmx0_sctrarb_rts << TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT) | \ + (dxtc_sctrarb_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT) | \ + (dxtc_dgmmpd_last_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT) | \ + (dxtc_dgmmpd_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT) | \ + (dcmp_mux_send << TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT)) + +#define TCD_DXTMUX_SCTARB_DEBUG_GET_pstate(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrmx_rtr(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_rtr(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrarb_multcyl_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_sctrmx0_sctrarb_rts(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_sctrarb_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_dgmmpd_last_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dxtc_dgmmpd_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_GET_dcmp_mux_send(tcd_dxtmux_sctarb_debug) \ + ((tcd_dxtmux_sctarb_debug & TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) >> TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT) + +#define TCD_DXTMUX_SCTARB_DEBUG_SET_pstate(tcd_dxtmux_sctarb_debug_reg, pstate) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_pstate_MASK) | (pstate << TCD_DXTMUX_SCTARB_DEBUG_pstate_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrmx_rtr(tcd_dxtmux_sctarb_debug_reg, sctrmx_rtr) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_MASK) | (sctrmx_rtr << TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_rtr(tcd_dxtmux_sctarb_debug_reg, dxtc_rtr) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_MASK) | (dxtc_rtr << TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrarb_multcyl_send(tcd_dxtmux_sctarb_debug_reg, sctrarb_multcyl_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_MASK) | (sctrarb_multcyl_send << TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_sctrmx0_sctrarb_rts(tcd_dxtmux_sctarb_debug_reg, sctrmx0_sctrarb_rts) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_MASK) | (sctrmx0_sctrarb_rts << TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_sctrarb_send(tcd_dxtmux_sctarb_debug_reg, dxtc_sctrarb_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_MASK) | (dxtc_sctrarb_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_dgmmpd_last_send(tcd_dxtmux_sctarb_debug_reg, dxtc_dgmmpd_last_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_MASK) | (dxtc_dgmmpd_last_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dxtc_dgmmpd_send(tcd_dxtmux_sctarb_debug_reg, dxtc_dgmmpd_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_MASK) | (dxtc_dgmmpd_send << TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SHIFT) +#define TCD_DXTMUX_SCTARB_DEBUG_SET_dcmp_mux_send(tcd_dxtmux_sctarb_debug_reg, dcmp_mux_send) \ + tcd_dxtmux_sctarb_debug_reg = (tcd_dxtmux_sctarb_debug_reg & ~TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_MASK) | (dcmp_mux_send << TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_dxtmux_sctarb_debug_t { + unsigned int : 9; + unsigned int pstate : TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE; + unsigned int sctrmx_rtr : TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE; + unsigned int dxtc_rtr : TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE; + unsigned int : 3; + unsigned int sctrarb_multcyl_send : TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE; + unsigned int sctrmx0_sctrarb_rts : TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE; + unsigned int : 3; + unsigned int dxtc_sctrarb_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE; + unsigned int : 6; + unsigned int dxtc_dgmmpd_last_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE; + unsigned int dxtc_dgmmpd_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE; + unsigned int dcmp_mux_send : TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE; + unsigned int : 2; + } tcd_dxtmux_sctarb_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_dxtmux_sctarb_debug_t { + unsigned int : 2; + unsigned int dcmp_mux_send : TCD_DXTMUX_SCTARB_DEBUG_dcmp_mux_send_SIZE; + unsigned int dxtc_dgmmpd_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_send_SIZE; + unsigned int dxtc_dgmmpd_last_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_dgmmpd_last_send_SIZE; + unsigned int : 6; + unsigned int dxtc_sctrarb_send : TCD_DXTMUX_SCTARB_DEBUG_dxtc_sctrarb_send_SIZE; + unsigned int : 3; + unsigned int sctrmx0_sctrarb_rts : TCD_DXTMUX_SCTARB_DEBUG_sctrmx0_sctrarb_rts_SIZE; + unsigned int sctrarb_multcyl_send : TCD_DXTMUX_SCTARB_DEBUG_sctrarb_multcyl_send_SIZE; + unsigned int : 3; + unsigned int dxtc_rtr : TCD_DXTMUX_SCTARB_DEBUG_dxtc_rtr_SIZE; + unsigned int sctrmx_rtr : TCD_DXTMUX_SCTARB_DEBUG_sctrmx_rtr_SIZE; + unsigned int pstate : TCD_DXTMUX_SCTARB_DEBUG_pstate_SIZE; + unsigned int : 9; + } tcd_dxtmux_sctarb_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_dxtmux_sctarb_debug_t f; +} tcd_dxtmux_sctarb_debug_u; + + +/* + * TCD_DXTC_ARB_DEBUG struct + */ + +#define TCD_DXTC_ARB_DEBUG_n0_stall_SIZE 1 +#define TCD_DXTC_ARB_DEBUG_pstate_SIZE 1 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE 1 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE 2 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE 3 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE 6 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE 12 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE 1 +#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE 1 + +#define TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT 4 +#define TCD_DXTC_ARB_DEBUG_pstate_SHIFT 5 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT 6 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT 7 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT 9 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT 12 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT 18 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT 30 +#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT 31 + +#define TCD_DXTC_ARB_DEBUG_n0_stall_MASK 0x00000010 +#define TCD_DXTC_ARB_DEBUG_pstate_MASK 0x00000020 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK 0x00000040 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK 0x00000180 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK 0x00000e00 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK 0x0003f000 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK 0x3ffc0000 +#define TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK 0x40000000 +#define TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK 0x80000000 + +#define TCD_DXTC_ARB_DEBUG_MASK \ + (TCD_DXTC_ARB_DEBUG_n0_stall_MASK | \ + TCD_DXTC_ARB_DEBUG_pstate_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK | \ + TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK | \ + TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) + +#define TCD_DXTC_ARB_DEBUG(n0_stall, pstate, arb_dcmp01_last_send, arb_dcmp01_cnt, arb_dcmp01_sector, arb_dcmp01_cacheline, arb_dcmp01_format, arb_dcmp01_send, n0_dxt2_4_types) \ + ((n0_stall << TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT) | \ + (pstate << TCD_DXTC_ARB_DEBUG_pstate_SHIFT) | \ + (arb_dcmp01_last_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT) | \ + (arb_dcmp01_cnt << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT) | \ + (arb_dcmp01_sector << TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT) | \ + (arb_dcmp01_cacheline << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT) | \ + (arb_dcmp01_format << TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT) | \ + (arb_dcmp01_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT) | \ + (n0_dxt2_4_types << TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT)) + +#define TCD_DXTC_ARB_DEBUG_GET_n0_stall(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_n0_stall_MASK) >> TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_pstate(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_pstate_MASK) >> TCD_DXTC_ARB_DEBUG_pstate_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_last_send(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_cnt(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_sector(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_cacheline(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_format(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_arb_dcmp01_send(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK) >> TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT) +#define TCD_DXTC_ARB_DEBUG_GET_n0_dxt2_4_types(tcd_dxtc_arb_debug) \ + ((tcd_dxtc_arb_debug & TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) >> TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT) + +#define TCD_DXTC_ARB_DEBUG_SET_n0_stall(tcd_dxtc_arb_debug_reg, n0_stall) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_n0_stall_MASK) | (n0_stall << TCD_DXTC_ARB_DEBUG_n0_stall_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_pstate(tcd_dxtc_arb_debug_reg, pstate) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_pstate_MASK) | (pstate << TCD_DXTC_ARB_DEBUG_pstate_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_last_send(tcd_dxtc_arb_debug_reg, arb_dcmp01_last_send) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_MASK) | (arb_dcmp01_last_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_cnt(tcd_dxtc_arb_debug_reg, arb_dcmp01_cnt) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_MASK) | (arb_dcmp01_cnt << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_sector(tcd_dxtc_arb_debug_reg, arb_dcmp01_sector) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_MASK) | (arb_dcmp01_sector << TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_cacheline(tcd_dxtc_arb_debug_reg, arb_dcmp01_cacheline) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_MASK) | (arb_dcmp01_cacheline << TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_format(tcd_dxtc_arb_debug_reg, arb_dcmp01_format) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_MASK) | (arb_dcmp01_format << TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_arb_dcmp01_send(tcd_dxtc_arb_debug_reg, arb_dcmp01_send) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_MASK) | (arb_dcmp01_send << TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SHIFT) +#define TCD_DXTC_ARB_DEBUG_SET_n0_dxt2_4_types(tcd_dxtc_arb_debug_reg, n0_dxt2_4_types) \ + tcd_dxtc_arb_debug_reg = (tcd_dxtc_arb_debug_reg & ~TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_MASK) | (n0_dxt2_4_types << TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_dxtc_arb_debug_t { + unsigned int : 4; + unsigned int n0_stall : TCD_DXTC_ARB_DEBUG_n0_stall_SIZE; + unsigned int pstate : TCD_DXTC_ARB_DEBUG_pstate_SIZE; + unsigned int arb_dcmp01_last_send : TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE; + unsigned int arb_dcmp01_cnt : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE; + unsigned int arb_dcmp01_sector : TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE; + unsigned int arb_dcmp01_cacheline : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE; + unsigned int arb_dcmp01_format : TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE; + unsigned int arb_dcmp01_send : TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE; + unsigned int n0_dxt2_4_types : TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE; + } tcd_dxtc_arb_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_dxtc_arb_debug_t { + unsigned int n0_dxt2_4_types : TCD_DXTC_ARB_DEBUG_n0_dxt2_4_types_SIZE; + unsigned int arb_dcmp01_send : TCD_DXTC_ARB_DEBUG_arb_dcmp01_send_SIZE; + unsigned int arb_dcmp01_format : TCD_DXTC_ARB_DEBUG_arb_dcmp01_format_SIZE; + unsigned int arb_dcmp01_cacheline : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cacheline_SIZE; + unsigned int arb_dcmp01_sector : TCD_DXTC_ARB_DEBUG_arb_dcmp01_sector_SIZE; + unsigned int arb_dcmp01_cnt : TCD_DXTC_ARB_DEBUG_arb_dcmp01_cnt_SIZE; + unsigned int arb_dcmp01_last_send : TCD_DXTC_ARB_DEBUG_arb_dcmp01_last_send_SIZE; + unsigned int pstate : TCD_DXTC_ARB_DEBUG_pstate_SIZE; + unsigned int n0_stall : TCD_DXTC_ARB_DEBUG_n0_stall_SIZE; + unsigned int : 4; + } tcd_dxtc_arb_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_dxtc_arb_debug_t f; +} tcd_dxtc_arb_debug_u; + + +/* + * TCD_STALLS_DEBUG struct + */ + +#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE 1 +#define TCD_STALLS_DEBUG_not_incoming_rtr_SIZE 1 + +#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT 10 +#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT 11 +#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT 17 +#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT 18 +#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT 19 +#define TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT 31 + +#define TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK 0x00000400 +#define TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK 0x00000800 +#define TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK 0x00020000 +#define TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK 0x00040000 +#define TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK 0x00080000 +#define TCD_STALLS_DEBUG_not_incoming_rtr_MASK 0x80000000 + +#define TCD_STALLS_DEBUG_MASK \ + (TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK | \ + TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK | \ + TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK | \ + TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK | \ + TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK | \ + TCD_STALLS_DEBUG_not_incoming_rtr_MASK) + +#define TCD_STALLS_DEBUG(not_multcyl_sctrarb_rtr, not_sctrmx0_sctrarb_rtr, not_dcmp0_arb_rtr, not_dgmmpd_dxtc_rtr, not_mux_dcmp_rtr, not_incoming_rtr) \ + ((not_multcyl_sctrarb_rtr << TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT) | \ + (not_sctrmx0_sctrarb_rtr << TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT) | \ + (not_dcmp0_arb_rtr << TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT) | \ + (not_dgmmpd_dxtc_rtr << TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT) | \ + (not_mux_dcmp_rtr << TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT) | \ + (not_incoming_rtr << TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT)) + +#define TCD_STALLS_DEBUG_GET_not_multcyl_sctrarb_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK) >> TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_sctrmx0_sctrarb_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK) >> TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_dcmp0_arb_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK) >> TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_dgmmpd_dxtc_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK) >> TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_mux_dcmp_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK) >> TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT) +#define TCD_STALLS_DEBUG_GET_not_incoming_rtr(tcd_stalls_debug) \ + ((tcd_stalls_debug & TCD_STALLS_DEBUG_not_incoming_rtr_MASK) >> TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT) + +#define TCD_STALLS_DEBUG_SET_not_multcyl_sctrarb_rtr(tcd_stalls_debug_reg, not_multcyl_sctrarb_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_MASK) | (not_multcyl_sctrarb_rtr << TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_sctrmx0_sctrarb_rtr(tcd_stalls_debug_reg, not_sctrmx0_sctrarb_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_MASK) | (not_sctrmx0_sctrarb_rtr << TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_dcmp0_arb_rtr(tcd_stalls_debug_reg, not_dcmp0_arb_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_MASK) | (not_dcmp0_arb_rtr << TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_dgmmpd_dxtc_rtr(tcd_stalls_debug_reg, not_dgmmpd_dxtc_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_MASK) | (not_dgmmpd_dxtc_rtr << TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_mux_dcmp_rtr(tcd_stalls_debug_reg, not_mux_dcmp_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_mux_dcmp_rtr_MASK) | (not_mux_dcmp_rtr << TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SHIFT) +#define TCD_STALLS_DEBUG_SET_not_incoming_rtr(tcd_stalls_debug_reg, not_incoming_rtr) \ + tcd_stalls_debug_reg = (tcd_stalls_debug_reg & ~TCD_STALLS_DEBUG_not_incoming_rtr_MASK) | (not_incoming_rtr << TCD_STALLS_DEBUG_not_incoming_rtr_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tcd_stalls_debug_t { + unsigned int : 10; + unsigned int not_multcyl_sctrarb_rtr : TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE; + unsigned int not_sctrmx0_sctrarb_rtr : TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE; + unsigned int : 5; + unsigned int not_dcmp0_arb_rtr : TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE; + unsigned int not_dgmmpd_dxtc_rtr : TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE; + unsigned int not_mux_dcmp_rtr : TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE; + unsigned int : 11; + unsigned int not_incoming_rtr : TCD_STALLS_DEBUG_not_incoming_rtr_SIZE; + } tcd_stalls_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tcd_stalls_debug_t { + unsigned int not_incoming_rtr : TCD_STALLS_DEBUG_not_incoming_rtr_SIZE; + unsigned int : 11; + unsigned int not_mux_dcmp_rtr : TCD_STALLS_DEBUG_not_mux_dcmp_rtr_SIZE; + unsigned int not_dgmmpd_dxtc_rtr : TCD_STALLS_DEBUG_not_dgmmpd_dxtc_rtr_SIZE; + unsigned int not_dcmp0_arb_rtr : TCD_STALLS_DEBUG_not_dcmp0_arb_rtr_SIZE; + unsigned int : 5; + unsigned int not_sctrmx0_sctrarb_rtr : TCD_STALLS_DEBUG_not_sctrmx0_sctrarb_rtr_SIZE; + unsigned int not_multcyl_sctrarb_rtr : TCD_STALLS_DEBUG_not_multcyl_sctrarb_rtr_SIZE; + unsigned int : 10; + } tcd_stalls_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tcd_stalls_debug_t f; +} tcd_stalls_debug_u; + + +/* + * TCO_STALLS_DEBUG struct + */ + +#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE 1 +#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE 1 +#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE 1 + +#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT 5 +#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT 6 +#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT 7 + +#define TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK 0x00000020 +#define TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK 0x00000040 +#define TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK 0x00000080 + +#define TCO_STALLS_DEBUG_MASK \ + (TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK | \ + TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK | \ + TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) + +#define TCO_STALLS_DEBUG(quad0_sg_crd_rtr, quad0_rl_sg_rtr, quad0_tco_tcb_rtr_d) \ + ((quad0_sg_crd_rtr << TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT) | \ + (quad0_rl_sg_rtr << TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT) | \ + (quad0_tco_tcb_rtr_d << TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT)) + +#define TCO_STALLS_DEBUG_GET_quad0_sg_crd_RTR(tco_stalls_debug) \ + ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK) >> TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT) +#define TCO_STALLS_DEBUG_GET_quad0_rl_sg_RTR(tco_stalls_debug) \ + ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK) >> TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT) +#define TCO_STALLS_DEBUG_GET_quad0_TCO_TCB_rtr_d(tco_stalls_debug) \ + ((tco_stalls_debug & TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) >> TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT) + +#define TCO_STALLS_DEBUG_SET_quad0_sg_crd_RTR(tco_stalls_debug_reg, quad0_sg_crd_rtr) \ + tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_sg_crd_RTR_MASK) | (quad0_sg_crd_rtr << TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SHIFT) +#define TCO_STALLS_DEBUG_SET_quad0_rl_sg_RTR(tco_stalls_debug_reg, quad0_rl_sg_rtr) \ + tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_rl_sg_RTR_MASK) | (quad0_rl_sg_rtr << TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SHIFT) +#define TCO_STALLS_DEBUG_SET_quad0_TCO_TCB_rtr_d(tco_stalls_debug_reg, quad0_tco_tcb_rtr_d) \ + tco_stalls_debug_reg = (tco_stalls_debug_reg & ~TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_MASK) | (quad0_tco_tcb_rtr_d << TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tco_stalls_debug_t { + unsigned int : 5; + unsigned int quad0_sg_crd_rtr : TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE; + unsigned int quad0_rl_sg_rtr : TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE; + unsigned int quad0_tco_tcb_rtr_d : TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE; + unsigned int : 24; + } tco_stalls_debug_t; + +#else // !BIGENDIAN_OS + + typedef struct _tco_stalls_debug_t { + unsigned int : 24; + unsigned int quad0_tco_tcb_rtr_d : TCO_STALLS_DEBUG_quad0_TCO_TCB_rtr_d_SIZE; + unsigned int quad0_rl_sg_rtr : TCO_STALLS_DEBUG_quad0_rl_sg_RTR_SIZE; + unsigned int quad0_sg_crd_rtr : TCO_STALLS_DEBUG_quad0_sg_crd_RTR_SIZE; + unsigned int : 5; + } tco_stalls_debug_t; + +#endif + +typedef union { + unsigned int val : 32; + tco_stalls_debug_t f; +} tco_stalls_debug_u; + + +/* + * TCO_QUAD0_DEBUG0 struct + */ + +#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE 8 +#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE 1 +#define TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE 1 +#define TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE 1 +#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE 1 +#define TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE 1 +#define TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE 1 +#define TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE 1 +#define TCO_QUAD0_DEBUG0_read_cache_q_SIZE 1 +#define TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE 1 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE 1 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE 1 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE 1 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE 1 +#define TCO_QUAD0_DEBUG0_busy_SIZE 1 + +#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT 0 +#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT 8 +#define TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT 9 +#define TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT 10 +#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT 11 +#define TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT 12 +#define TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT 13 +#define TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT 16 +#define TCO_QUAD0_DEBUG0_read_cache_q_SHIFT 24 +#define TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT 25 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT 26 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT 27 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT 28 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT 29 +#define TCO_QUAD0_DEBUG0_busy_SHIFT 30 + +#define TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK 0x000000ff +#define TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK 0x00000100 +#define TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK 0x00000200 +#define TCO_QUAD0_DEBUG0_rl_sg_rts_MASK 0x00000400 +#define TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK 0x00000800 +#define TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK 0x00001000 +#define TCO_QUAD0_DEBUG0_sg_crd_rts_MASK 0x00002000 +#define TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK 0x00010000 +#define TCO_QUAD0_DEBUG0_read_cache_q_MASK 0x01000000 +#define TCO_QUAD0_DEBUG0_cache_read_RTR_MASK 0x02000000 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK 0x04000000 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK 0x08000000 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK 0x10000000 +#define TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK 0x20000000 +#define TCO_QUAD0_DEBUG0_busy_MASK 0x40000000 + +#define TCO_QUAD0_DEBUG0_MASK \ + (TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK | \ + TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK | \ + TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK | \ + TCO_QUAD0_DEBUG0_rl_sg_rts_MASK | \ + TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK | \ + TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK | \ + TCO_QUAD0_DEBUG0_sg_crd_rts_MASK | \ + TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK | \ + TCO_QUAD0_DEBUG0_read_cache_q_MASK | \ + TCO_QUAD0_DEBUG0_cache_read_RTR_MASK | \ + TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK | \ + TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK | \ + TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK | \ + TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK | \ + TCO_QUAD0_DEBUG0_busy_MASK) + +#define TCO_QUAD0_DEBUG0(rl_sg_sector_format, rl_sg_end_of_sample, rl_sg_rtr, rl_sg_rts, sg_crd_end_of_sample, sg_crd_rtr, sg_crd_rts, stagen1_valid_q, read_cache_q, cache_read_rtr, all_sectors_written_set3, all_sectors_written_set2, all_sectors_written_set1, all_sectors_written_set0, busy) \ + ((rl_sg_sector_format << TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT) | \ + (rl_sg_end_of_sample << TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT) | \ + (rl_sg_rtr << TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT) | \ + (rl_sg_rts << TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT) | \ + (sg_crd_end_of_sample << TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT) | \ + (sg_crd_rtr << TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT) | \ + (sg_crd_rts << TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT) | \ + (stagen1_valid_q << TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT) | \ + (read_cache_q << TCO_QUAD0_DEBUG0_read_cache_q_SHIFT) | \ + (cache_read_rtr << TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT) | \ + (all_sectors_written_set3 << TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT) | \ + (all_sectors_written_set2 << TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT) | \ + (all_sectors_written_set1 << TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT) | \ + (all_sectors_written_set0 << TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT) | \ + (busy << TCO_QUAD0_DEBUG0_busy_SHIFT)) + +#define TCO_QUAD0_DEBUG0_GET_rl_sg_sector_format(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_rl_sg_end_of_sample(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_rl_sg_rtr(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_rl_sg_rts(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_rl_sg_rts_MASK) >> TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_sg_crd_end_of_sample(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_sg_crd_rtr(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_sg_crd_rts(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_sg_crd_rts_MASK) >> TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_stageN1_valid_q(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK) >> TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_read_cache_q(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_read_cache_q_MASK) >> TCO_QUAD0_DEBUG0_read_cache_q_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_cache_read_RTR(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_cache_read_RTR_MASK) >> TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set3(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set2(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set1(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_all_sectors_written_set0(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK) >> TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT) +#define TCO_QUAD0_DEBUG0_GET_busy(tco_quad0_debug0) \ + ((tco_quad0_debug0 & TCO_QUAD0_DEBUG0_busy_MASK) >> TCO_QUAD0_DEBUG0_busy_SHIFT) + +#define TCO_QUAD0_DEBUG0_SET_rl_sg_sector_format(tco_quad0_debug0_reg, rl_sg_sector_format) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_sector_format_MASK) | (rl_sg_sector_format << TCO_QUAD0_DEBUG0_rl_sg_sector_format_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_rl_sg_end_of_sample(tco_quad0_debug0_reg, rl_sg_end_of_sample) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_MASK) | (rl_sg_end_of_sample << TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_rl_sg_rtr(tco_quad0_debug0_reg, rl_sg_rtr) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_rtr_MASK) | (rl_sg_rtr << TCO_QUAD0_DEBUG0_rl_sg_rtr_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_rl_sg_rts(tco_quad0_debug0_reg, rl_sg_rts) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_rl_sg_rts_MASK) | (rl_sg_rts << TCO_QUAD0_DEBUG0_rl_sg_rts_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_sg_crd_end_of_sample(tco_quad0_debug0_reg, sg_crd_end_of_sample) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_MASK) | (sg_crd_end_of_sample << TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_sg_crd_rtr(tco_quad0_debug0_reg, sg_crd_rtr) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_rtr_MASK) | (sg_crd_rtr << TCO_QUAD0_DEBUG0_sg_crd_rtr_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_sg_crd_rts(tco_quad0_debug0_reg, sg_crd_rts) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_sg_crd_rts_MASK) | (sg_crd_rts << TCO_QUAD0_DEBUG0_sg_crd_rts_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_stageN1_valid_q(tco_quad0_debug0_reg, stagen1_valid_q) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_stageN1_valid_q_MASK) | (stagen1_valid_q << TCO_QUAD0_DEBUG0_stageN1_valid_q_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_read_cache_q(tco_quad0_debug0_reg, read_cache_q) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_read_cache_q_MASK) | (read_cache_q << TCO_QUAD0_DEBUG0_read_cache_q_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_cache_read_RTR(tco_quad0_debug0_reg, cache_read_rtr) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_cache_read_RTR_MASK) | (cache_read_rtr << TCO_QUAD0_DEBUG0_cache_read_RTR_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set3(tco_quad0_debug0_reg, all_sectors_written_set3) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set3_MASK) | (all_sectors_written_set3 << TCO_QUAD0_DEBUG0_all_sectors_written_set3_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set2(tco_quad0_debug0_reg, all_sectors_written_set2) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set2_MASK) | (all_sectors_written_set2 << TCO_QUAD0_DEBUG0_all_sectors_written_set2_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set1(tco_quad0_debug0_reg, all_sectors_written_set1) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set1_MASK) | (all_sectors_written_set1 << TCO_QUAD0_DEBUG0_all_sectors_written_set1_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_all_sectors_written_set0(tco_quad0_debug0_reg, all_sectors_written_set0) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_all_sectors_written_set0_MASK) | (all_sectors_written_set0 << TCO_QUAD0_DEBUG0_all_sectors_written_set0_SHIFT) +#define TCO_QUAD0_DEBUG0_SET_busy(tco_quad0_debug0_reg, busy) \ + tco_quad0_debug0_reg = (tco_quad0_debug0_reg & ~TCO_QUAD0_DEBUG0_busy_MASK) | (busy << TCO_QUAD0_DEBUG0_busy_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tco_quad0_debug0_t { + unsigned int rl_sg_sector_format : TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE; + unsigned int rl_sg_end_of_sample : TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE; + unsigned int rl_sg_rtr : TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE; + unsigned int rl_sg_rts : TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE; + unsigned int sg_crd_end_of_sample : TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE; + unsigned int sg_crd_rtr : TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE; + unsigned int sg_crd_rts : TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE; + unsigned int : 2; + unsigned int stagen1_valid_q : TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE; + unsigned int : 7; + unsigned int read_cache_q : TCO_QUAD0_DEBUG0_read_cache_q_SIZE; + unsigned int cache_read_rtr : TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE; + unsigned int all_sectors_written_set3 : TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE; + unsigned int all_sectors_written_set2 : TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE; + unsigned int all_sectors_written_set1 : TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE; + unsigned int all_sectors_written_set0 : TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE; + unsigned int busy : TCO_QUAD0_DEBUG0_busy_SIZE; + unsigned int : 1; + } tco_quad0_debug0_t; + +#else // !BIGENDIAN_OS + + typedef struct _tco_quad0_debug0_t { + unsigned int : 1; + unsigned int busy : TCO_QUAD0_DEBUG0_busy_SIZE; + unsigned int all_sectors_written_set0 : TCO_QUAD0_DEBUG0_all_sectors_written_set0_SIZE; + unsigned int all_sectors_written_set1 : TCO_QUAD0_DEBUG0_all_sectors_written_set1_SIZE; + unsigned int all_sectors_written_set2 : TCO_QUAD0_DEBUG0_all_sectors_written_set2_SIZE; + unsigned int all_sectors_written_set3 : TCO_QUAD0_DEBUG0_all_sectors_written_set3_SIZE; + unsigned int cache_read_rtr : TCO_QUAD0_DEBUG0_cache_read_RTR_SIZE; + unsigned int read_cache_q : TCO_QUAD0_DEBUG0_read_cache_q_SIZE; + unsigned int : 7; + unsigned int stagen1_valid_q : TCO_QUAD0_DEBUG0_stageN1_valid_q_SIZE; + unsigned int : 2; + unsigned int sg_crd_rts : TCO_QUAD0_DEBUG0_sg_crd_rts_SIZE; + unsigned int sg_crd_rtr : TCO_QUAD0_DEBUG0_sg_crd_rtr_SIZE; + unsigned int sg_crd_end_of_sample : TCO_QUAD0_DEBUG0_sg_crd_end_of_sample_SIZE; + unsigned int rl_sg_rts : TCO_QUAD0_DEBUG0_rl_sg_rts_SIZE; + unsigned int rl_sg_rtr : TCO_QUAD0_DEBUG0_rl_sg_rtr_SIZE; + unsigned int rl_sg_end_of_sample : TCO_QUAD0_DEBUG0_rl_sg_end_of_sample_SIZE; + unsigned int rl_sg_sector_format : TCO_QUAD0_DEBUG0_rl_sg_sector_format_SIZE; + } tco_quad0_debug0_t; + +#endif + +typedef union { + unsigned int val : 32; + tco_quad0_debug0_t f; +} tco_quad0_debug0_u; + + +/* + * TCO_QUAD0_DEBUG1 struct + */ + +#define TCO_QUAD0_DEBUG1_fifo_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_empty_SIZE 1 +#define TCO_QUAD0_DEBUG1_full_SIZE 1 +#define TCO_QUAD0_DEBUG1_write_enable_SIZE 1 +#define TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE 7 +#define TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE 7 +#define TCO_QUAD0_DEBUG1_cache_read_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_input_quad_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE 1 +#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE 1 +#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE 1 +#define TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE 1 +#define TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE 1 +#define TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE 1 +#define TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE 1 +#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE 1 + +#define TCO_QUAD0_DEBUG1_fifo_busy_SHIFT 0 +#define TCO_QUAD0_DEBUG1_empty_SHIFT 1 +#define TCO_QUAD0_DEBUG1_full_SHIFT 2 +#define TCO_QUAD0_DEBUG1_write_enable_SHIFT 3 +#define TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT 4 +#define TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT 11 +#define TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT 20 +#define TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT 21 +#define TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT 22 +#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT 23 +#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT 24 +#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT 25 +#define TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT 26 +#define TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT 27 +#define TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT 28 +#define TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT 29 +#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT 30 + +#define TCO_QUAD0_DEBUG1_fifo_busy_MASK 0x00000001 +#define TCO_QUAD0_DEBUG1_empty_MASK 0x00000002 +#define TCO_QUAD0_DEBUG1_full_MASK 0x00000004 +#define TCO_QUAD0_DEBUG1_write_enable_MASK 0x00000008 +#define TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK 0x000007f0 +#define TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK 0x0003f800 +#define TCO_QUAD0_DEBUG1_cache_read_busy_MASK 0x00100000 +#define TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK 0x00200000 +#define TCO_QUAD0_DEBUG1_input_quad_busy_MASK 0x00400000 +#define TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK 0x00800000 +#define TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK 0x01000000 +#define TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK 0x02000000 +#define TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK 0x04000000 +#define TCO_QUAD0_DEBUG1_rl_sg_rts_MASK 0x08000000 +#define TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK 0x10000000 +#define TCO_QUAD0_DEBUG1_sg_crd_rts_MASK 0x20000000 +#define TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK 0x40000000 + +#define TCO_QUAD0_DEBUG1_MASK \ + (TCO_QUAD0_DEBUG1_fifo_busy_MASK | \ + TCO_QUAD0_DEBUG1_empty_MASK | \ + TCO_QUAD0_DEBUG1_full_MASK | \ + TCO_QUAD0_DEBUG1_write_enable_MASK | \ + TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK | \ + TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK | \ + TCO_QUAD0_DEBUG1_cache_read_busy_MASK | \ + TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK | \ + TCO_QUAD0_DEBUG1_input_quad_busy_MASK | \ + TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK | \ + TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK | \ + TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK | \ + TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK | \ + TCO_QUAD0_DEBUG1_rl_sg_rts_MASK | \ + TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK | \ + TCO_QUAD0_DEBUG1_sg_crd_rts_MASK | \ + TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) + +#define TCO_QUAD0_DEBUG1(fifo_busy, empty, full, write_enable, fifo_write_ptr, fifo_read_ptr, cache_read_busy, latency_fifo_busy, input_quad_busy, tco_quad_pipe_busy, tcb_tco_rtr_d, tcb_tco_xfc_q, rl_sg_rtr, rl_sg_rts, sg_crd_rtr, sg_crd_rts, tco_tcb_read_xfc) \ + ((fifo_busy << TCO_QUAD0_DEBUG1_fifo_busy_SHIFT) | \ + (empty << TCO_QUAD0_DEBUG1_empty_SHIFT) | \ + (full << TCO_QUAD0_DEBUG1_full_SHIFT) | \ + (write_enable << TCO_QUAD0_DEBUG1_write_enable_SHIFT) | \ + (fifo_write_ptr << TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT) | \ + (fifo_read_ptr << TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT) | \ + (cache_read_busy << TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT) | \ + (latency_fifo_busy << TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT) | \ + (input_quad_busy << TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT) | \ + (tco_quad_pipe_busy << TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT) | \ + (tcb_tco_rtr_d << TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT) | \ + (tcb_tco_xfc_q << TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT) | \ + (rl_sg_rtr << TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT) | \ + (rl_sg_rts << TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT) | \ + (sg_crd_rtr << TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT) | \ + (sg_crd_rts << TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT) | \ + (tco_tcb_read_xfc << TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT)) + +#define TCO_QUAD0_DEBUG1_GET_fifo_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_busy_MASK) >> TCO_QUAD0_DEBUG1_fifo_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_empty(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_empty_MASK) >> TCO_QUAD0_DEBUG1_empty_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_full(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_full_MASK) >> TCO_QUAD0_DEBUG1_full_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_write_enable(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_write_enable_MASK) >> TCO_QUAD0_DEBUG1_write_enable_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_fifo_write_ptr(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK) >> TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_fifo_read_ptr(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK) >> TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_cache_read_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_cache_read_busy_MASK) >> TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_latency_fifo_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK) >> TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_input_quad_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_input_quad_busy_MASK) >> TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_tco_quad_pipe_busy(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK) >> TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_TCB_TCO_rtr_d(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK) >> TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_TCB_TCO_xfc_q(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK) >> TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_rl_sg_rtr(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK) >> TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_rl_sg_rts(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_rl_sg_rts_MASK) >> TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_sg_crd_rtr(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK) >> TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_sg_crd_rts(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_sg_crd_rts_MASK) >> TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT) +#define TCO_QUAD0_DEBUG1_GET_TCO_TCB_read_xfc(tco_quad0_debug1) \ + ((tco_quad0_debug1 & TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) >> TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT) + +#define TCO_QUAD0_DEBUG1_SET_fifo_busy(tco_quad0_debug1_reg, fifo_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_busy_MASK) | (fifo_busy << TCO_QUAD0_DEBUG1_fifo_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_empty(tco_quad0_debug1_reg, empty) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_empty_MASK) | (empty << TCO_QUAD0_DEBUG1_empty_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_full(tco_quad0_debug1_reg, full) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_full_MASK) | (full << TCO_QUAD0_DEBUG1_full_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_write_enable(tco_quad0_debug1_reg, write_enable) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_write_enable_MASK) | (write_enable << TCO_QUAD0_DEBUG1_write_enable_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_fifo_write_ptr(tco_quad0_debug1_reg, fifo_write_ptr) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_write_ptr_MASK) | (fifo_write_ptr << TCO_QUAD0_DEBUG1_fifo_write_ptr_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_fifo_read_ptr(tco_quad0_debug1_reg, fifo_read_ptr) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_fifo_read_ptr_MASK) | (fifo_read_ptr << TCO_QUAD0_DEBUG1_fifo_read_ptr_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_cache_read_busy(tco_quad0_debug1_reg, cache_read_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_cache_read_busy_MASK) | (cache_read_busy << TCO_QUAD0_DEBUG1_cache_read_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_latency_fifo_busy(tco_quad0_debug1_reg, latency_fifo_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_latency_fifo_busy_MASK) | (latency_fifo_busy << TCO_QUAD0_DEBUG1_latency_fifo_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_input_quad_busy(tco_quad0_debug1_reg, input_quad_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_input_quad_busy_MASK) | (input_quad_busy << TCO_QUAD0_DEBUG1_input_quad_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_tco_quad_pipe_busy(tco_quad0_debug1_reg, tco_quad_pipe_busy) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_MASK) | (tco_quad_pipe_busy << TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_TCB_TCO_rtr_d(tco_quad0_debug1_reg, tcb_tco_rtr_d) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_MASK) | (tcb_tco_rtr_d << TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_TCB_TCO_xfc_q(tco_quad0_debug1_reg, tcb_tco_xfc_q) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_MASK) | (tcb_tco_xfc_q << TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_rl_sg_rtr(tco_quad0_debug1_reg, rl_sg_rtr) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_rl_sg_rtr_MASK) | (rl_sg_rtr << TCO_QUAD0_DEBUG1_rl_sg_rtr_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_rl_sg_rts(tco_quad0_debug1_reg, rl_sg_rts) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_rl_sg_rts_MASK) | (rl_sg_rts << TCO_QUAD0_DEBUG1_rl_sg_rts_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_sg_crd_rtr(tco_quad0_debug1_reg, sg_crd_rtr) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_sg_crd_rtr_MASK) | (sg_crd_rtr << TCO_QUAD0_DEBUG1_sg_crd_rtr_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_sg_crd_rts(tco_quad0_debug1_reg, sg_crd_rts) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_sg_crd_rts_MASK) | (sg_crd_rts << TCO_QUAD0_DEBUG1_sg_crd_rts_SHIFT) +#define TCO_QUAD0_DEBUG1_SET_TCO_TCB_read_xfc(tco_quad0_debug1_reg, tco_tcb_read_xfc) \ + tco_quad0_debug1_reg = (tco_quad0_debug1_reg & ~TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_MASK) | (tco_tcb_read_xfc << TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _tco_quad0_debug1_t { + unsigned int fifo_busy : TCO_QUAD0_DEBUG1_fifo_busy_SIZE; + unsigned int empty : TCO_QUAD0_DEBUG1_empty_SIZE; + unsigned int full : TCO_QUAD0_DEBUG1_full_SIZE; + unsigned int write_enable : TCO_QUAD0_DEBUG1_write_enable_SIZE; + unsigned int fifo_write_ptr : TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE; + unsigned int fifo_read_ptr : TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE; + unsigned int : 2; + unsigned int cache_read_busy : TCO_QUAD0_DEBUG1_cache_read_busy_SIZE; + unsigned int latency_fifo_busy : TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE; + unsigned int input_quad_busy : TCO_QUAD0_DEBUG1_input_quad_busy_SIZE; + unsigned int tco_quad_pipe_busy : TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE; + unsigned int tcb_tco_rtr_d : TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE; + unsigned int tcb_tco_xfc_q : TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE; + unsigned int rl_sg_rtr : TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE; + unsigned int rl_sg_rts : TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE; + unsigned int sg_crd_rtr : TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE; + unsigned int sg_crd_rts : TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE; + unsigned int tco_tcb_read_xfc : TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE; + unsigned int : 1; + } tco_quad0_debug1_t; + +#else // !BIGENDIAN_OS + + typedef struct _tco_quad0_debug1_t { + unsigned int : 1; + unsigned int tco_tcb_read_xfc : TCO_QUAD0_DEBUG1_TCO_TCB_read_xfc_SIZE; + unsigned int sg_crd_rts : TCO_QUAD0_DEBUG1_sg_crd_rts_SIZE; + unsigned int sg_crd_rtr : TCO_QUAD0_DEBUG1_sg_crd_rtr_SIZE; + unsigned int rl_sg_rts : TCO_QUAD0_DEBUG1_rl_sg_rts_SIZE; + unsigned int rl_sg_rtr : TCO_QUAD0_DEBUG1_rl_sg_rtr_SIZE; + unsigned int tcb_tco_xfc_q : TCO_QUAD0_DEBUG1_TCB_TCO_xfc_q_SIZE; + unsigned int tcb_tco_rtr_d : TCO_QUAD0_DEBUG1_TCB_TCO_rtr_d_SIZE; + unsigned int tco_quad_pipe_busy : TCO_QUAD0_DEBUG1_tco_quad_pipe_busy_SIZE; + unsigned int input_quad_busy : TCO_QUAD0_DEBUG1_input_quad_busy_SIZE; + unsigned int latency_fifo_busy : TCO_QUAD0_DEBUG1_latency_fifo_busy_SIZE; + unsigned int cache_read_busy : TCO_QUAD0_DEBUG1_cache_read_busy_SIZE; + unsigned int : 2; + unsigned int fifo_read_ptr : TCO_QUAD0_DEBUG1_fifo_read_ptr_SIZE; + unsigned int fifo_write_ptr : TCO_QUAD0_DEBUG1_fifo_write_ptr_SIZE; + unsigned int write_enable : TCO_QUAD0_DEBUG1_write_enable_SIZE; + unsigned int full : TCO_QUAD0_DEBUG1_full_SIZE; + unsigned int empty : TCO_QUAD0_DEBUG1_empty_SIZE; + unsigned int fifo_busy : TCO_QUAD0_DEBUG1_fifo_busy_SIZE; + } tco_quad0_debug1_t; + +#endif + +typedef union { + unsigned int val : 32; + tco_quad0_debug1_t f; +} tco_quad0_debug1_u; + + +#endif + + +#if !defined (_TC_FIDDLE_H) +#define _TC_FIDDLE_H + +/***************************************************************************************************************** + * + * tc_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +#endif + + +#if !defined (_SC_FIDDLE_H) +#define _SC_FIDDLE_H + +/***************************************************************************************************************** + * + * sc_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +#endif + + +#if !defined (_BC_FIDDLE_H) +#define _BC_FIDDLE_H + +/***************************************************************************************************************** + * + * bc_reg.h + * + * Register Spec Release: Block Spec 1.0 + * + * (c) 2000 ATI Technologies Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + *****************************************************************************************************************/ + +/******************************************************* + * Enums + *******************************************************/ + + +/******************************************************* + * Values + *******************************************************/ + + +/******************************************************* + * Structures + *******************************************************/ + +/* + * RB_SURFACE_INFO struct + */ + +#define RB_SURFACE_INFO_SURFACE_PITCH_SIZE 14 +#define RB_SURFACE_INFO_MSAA_SAMPLES_SIZE 2 + +#define RB_SURFACE_INFO_SURFACE_PITCH_SHIFT 0 +#define RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT 14 + +#define RB_SURFACE_INFO_SURFACE_PITCH_MASK 0x00003fff +#define RB_SURFACE_INFO_MSAA_SAMPLES_MASK 0x0000c000 + +#define RB_SURFACE_INFO_MASK \ + (RB_SURFACE_INFO_SURFACE_PITCH_MASK | \ + RB_SURFACE_INFO_MSAA_SAMPLES_MASK) + +#define RB_SURFACE_INFO(surface_pitch, msaa_samples) \ + ((surface_pitch << RB_SURFACE_INFO_SURFACE_PITCH_SHIFT) | \ + (msaa_samples << RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT)) + +#define RB_SURFACE_INFO_GET_SURFACE_PITCH(rb_surface_info) \ + ((rb_surface_info & RB_SURFACE_INFO_SURFACE_PITCH_MASK) >> RB_SURFACE_INFO_SURFACE_PITCH_SHIFT) +#define RB_SURFACE_INFO_GET_MSAA_SAMPLES(rb_surface_info) \ + ((rb_surface_info & RB_SURFACE_INFO_MSAA_SAMPLES_MASK) >> RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT) + +#define RB_SURFACE_INFO_SET_SURFACE_PITCH(rb_surface_info_reg, surface_pitch) \ + rb_surface_info_reg = (rb_surface_info_reg & ~RB_SURFACE_INFO_SURFACE_PITCH_MASK) | (surface_pitch << RB_SURFACE_INFO_SURFACE_PITCH_SHIFT) +#define RB_SURFACE_INFO_SET_MSAA_SAMPLES(rb_surface_info_reg, msaa_samples) \ + rb_surface_info_reg = (rb_surface_info_reg & ~RB_SURFACE_INFO_MSAA_SAMPLES_MASK) | (msaa_samples << RB_SURFACE_INFO_MSAA_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_surface_info_t { + unsigned int surface_pitch : RB_SURFACE_INFO_SURFACE_PITCH_SIZE; + unsigned int msaa_samples : RB_SURFACE_INFO_MSAA_SAMPLES_SIZE; + unsigned int : 16; + } rb_surface_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_surface_info_t { + unsigned int : 16; + unsigned int msaa_samples : RB_SURFACE_INFO_MSAA_SAMPLES_SIZE; + unsigned int surface_pitch : RB_SURFACE_INFO_SURFACE_PITCH_SIZE; + } rb_surface_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_surface_info_t f; +} rb_surface_info_u; + + +/* + * RB_COLOR_INFO struct + */ + +#define RB_COLOR_INFO_COLOR_FORMAT_SIZE 4 +#define RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE 2 +#define RB_COLOR_INFO_COLOR_LINEAR_SIZE 1 +#define RB_COLOR_INFO_COLOR_ENDIAN_SIZE 2 +#define RB_COLOR_INFO_COLOR_SWAP_SIZE 2 +#define RB_COLOR_INFO_COLOR_BASE_SIZE 20 + +#define RB_COLOR_INFO_COLOR_FORMAT_SHIFT 0 +#define RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT 4 +#define RB_COLOR_INFO_COLOR_LINEAR_SHIFT 6 +#define RB_COLOR_INFO_COLOR_ENDIAN_SHIFT 7 +#define RB_COLOR_INFO_COLOR_SWAP_SHIFT 9 +#define RB_COLOR_INFO_COLOR_BASE_SHIFT 12 + +#define RB_COLOR_INFO_COLOR_FORMAT_MASK 0x0000000f +#define RB_COLOR_INFO_COLOR_ROUND_MODE_MASK 0x00000030 +#define RB_COLOR_INFO_COLOR_LINEAR_MASK 0x00000040 +#define RB_COLOR_INFO_COLOR_ENDIAN_MASK 0x00000180 +#define RB_COLOR_INFO_COLOR_SWAP_MASK 0x00000600 +#define RB_COLOR_INFO_COLOR_BASE_MASK 0xfffff000 + +#define RB_COLOR_INFO_MASK \ + (RB_COLOR_INFO_COLOR_FORMAT_MASK | \ + RB_COLOR_INFO_COLOR_ROUND_MODE_MASK | \ + RB_COLOR_INFO_COLOR_LINEAR_MASK | \ + RB_COLOR_INFO_COLOR_ENDIAN_MASK | \ + RB_COLOR_INFO_COLOR_SWAP_MASK | \ + RB_COLOR_INFO_COLOR_BASE_MASK) + +#define RB_COLOR_INFO(color_format, color_round_mode, color_linear, color_endian, color_swap, color_base) \ + ((color_format << RB_COLOR_INFO_COLOR_FORMAT_SHIFT) | \ + (color_round_mode << RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT) | \ + (color_linear << RB_COLOR_INFO_COLOR_LINEAR_SHIFT) | \ + (color_endian << RB_COLOR_INFO_COLOR_ENDIAN_SHIFT) | \ + (color_swap << RB_COLOR_INFO_COLOR_SWAP_SHIFT) | \ + (color_base << RB_COLOR_INFO_COLOR_BASE_SHIFT)) + +#define RB_COLOR_INFO_GET_COLOR_FORMAT(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_FORMAT_MASK) >> RB_COLOR_INFO_COLOR_FORMAT_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_ROUND_MODE(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_ROUND_MODE_MASK) >> RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_LINEAR(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_LINEAR_MASK) >> RB_COLOR_INFO_COLOR_LINEAR_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_ENDIAN(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_ENDIAN_MASK) >> RB_COLOR_INFO_COLOR_ENDIAN_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_SWAP(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_SWAP_MASK) >> RB_COLOR_INFO_COLOR_SWAP_SHIFT) +#define RB_COLOR_INFO_GET_COLOR_BASE(rb_color_info) \ + ((rb_color_info & RB_COLOR_INFO_COLOR_BASE_MASK) >> RB_COLOR_INFO_COLOR_BASE_SHIFT) + +#define RB_COLOR_INFO_SET_COLOR_FORMAT(rb_color_info_reg, color_format) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_FORMAT_MASK) | (color_format << RB_COLOR_INFO_COLOR_FORMAT_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_ROUND_MODE(rb_color_info_reg, color_round_mode) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_ROUND_MODE_MASK) | (color_round_mode << RB_COLOR_INFO_COLOR_ROUND_MODE_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_LINEAR(rb_color_info_reg, color_linear) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_LINEAR_MASK) | (color_linear << RB_COLOR_INFO_COLOR_LINEAR_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_ENDIAN(rb_color_info_reg, color_endian) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_ENDIAN_MASK) | (color_endian << RB_COLOR_INFO_COLOR_ENDIAN_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_SWAP(rb_color_info_reg, color_swap) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_SWAP_MASK) | (color_swap << RB_COLOR_INFO_COLOR_SWAP_SHIFT) +#define RB_COLOR_INFO_SET_COLOR_BASE(rb_color_info_reg, color_base) \ + rb_color_info_reg = (rb_color_info_reg & ~RB_COLOR_INFO_COLOR_BASE_MASK) | (color_base << RB_COLOR_INFO_COLOR_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_color_info_t { + unsigned int color_format : RB_COLOR_INFO_COLOR_FORMAT_SIZE; + unsigned int color_round_mode : RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE; + unsigned int color_linear : RB_COLOR_INFO_COLOR_LINEAR_SIZE; + unsigned int color_endian : RB_COLOR_INFO_COLOR_ENDIAN_SIZE; + unsigned int color_swap : RB_COLOR_INFO_COLOR_SWAP_SIZE; + unsigned int : 1; + unsigned int color_base : RB_COLOR_INFO_COLOR_BASE_SIZE; + } rb_color_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_color_info_t { + unsigned int color_base : RB_COLOR_INFO_COLOR_BASE_SIZE; + unsigned int : 1; + unsigned int color_swap : RB_COLOR_INFO_COLOR_SWAP_SIZE; + unsigned int color_endian : RB_COLOR_INFO_COLOR_ENDIAN_SIZE; + unsigned int color_linear : RB_COLOR_INFO_COLOR_LINEAR_SIZE; + unsigned int color_round_mode : RB_COLOR_INFO_COLOR_ROUND_MODE_SIZE; + unsigned int color_format : RB_COLOR_INFO_COLOR_FORMAT_SIZE; + } rb_color_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_color_info_t f; +} rb_color_info_u; + + +/* + * RB_DEPTH_INFO struct + */ + +#define RB_DEPTH_INFO_DEPTH_FORMAT_SIZE 1 +#define RB_DEPTH_INFO_DEPTH_BASE_SIZE 20 + +#define RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT 0 +#define RB_DEPTH_INFO_DEPTH_BASE_SHIFT 12 + +#define RB_DEPTH_INFO_DEPTH_FORMAT_MASK 0x00000001 +#define RB_DEPTH_INFO_DEPTH_BASE_MASK 0xfffff000 + +#define RB_DEPTH_INFO_MASK \ + (RB_DEPTH_INFO_DEPTH_FORMAT_MASK | \ + RB_DEPTH_INFO_DEPTH_BASE_MASK) + +#define RB_DEPTH_INFO(depth_format, depth_base) \ + ((depth_format << RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT) | \ + (depth_base << RB_DEPTH_INFO_DEPTH_BASE_SHIFT)) + +#define RB_DEPTH_INFO_GET_DEPTH_FORMAT(rb_depth_info) \ + ((rb_depth_info & RB_DEPTH_INFO_DEPTH_FORMAT_MASK) >> RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT) +#define RB_DEPTH_INFO_GET_DEPTH_BASE(rb_depth_info) \ + ((rb_depth_info & RB_DEPTH_INFO_DEPTH_BASE_MASK) >> RB_DEPTH_INFO_DEPTH_BASE_SHIFT) + +#define RB_DEPTH_INFO_SET_DEPTH_FORMAT(rb_depth_info_reg, depth_format) \ + rb_depth_info_reg = (rb_depth_info_reg & ~RB_DEPTH_INFO_DEPTH_FORMAT_MASK) | (depth_format << RB_DEPTH_INFO_DEPTH_FORMAT_SHIFT) +#define RB_DEPTH_INFO_SET_DEPTH_BASE(rb_depth_info_reg, depth_base) \ + rb_depth_info_reg = (rb_depth_info_reg & ~RB_DEPTH_INFO_DEPTH_BASE_MASK) | (depth_base << RB_DEPTH_INFO_DEPTH_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_depth_info_t { + unsigned int depth_format : RB_DEPTH_INFO_DEPTH_FORMAT_SIZE; + unsigned int : 11; + unsigned int depth_base : RB_DEPTH_INFO_DEPTH_BASE_SIZE; + } rb_depth_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_depth_info_t { + unsigned int depth_base : RB_DEPTH_INFO_DEPTH_BASE_SIZE; + unsigned int : 11; + unsigned int depth_format : RB_DEPTH_INFO_DEPTH_FORMAT_SIZE; + } rb_depth_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_depth_info_t f; +} rb_depth_info_u; + + +/* + * RB_STENCILREFMASK struct + */ + +#define RB_STENCILREFMASK_STENCILREF_SIZE 8 +#define RB_STENCILREFMASK_STENCILMASK_SIZE 8 +#define RB_STENCILREFMASK_STENCILWRITEMASK_SIZE 8 +#define RB_STENCILREFMASK_RESERVED0_SIZE 1 +#define RB_STENCILREFMASK_RESERVED1_SIZE 1 + +#define RB_STENCILREFMASK_STENCILREF_SHIFT 0 +#define RB_STENCILREFMASK_STENCILMASK_SHIFT 8 +#define RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT 16 +#define RB_STENCILREFMASK_RESERVED0_SHIFT 24 +#define RB_STENCILREFMASK_RESERVED1_SHIFT 25 + +#define RB_STENCILREFMASK_STENCILREF_MASK 0x000000ff +#define RB_STENCILREFMASK_STENCILMASK_MASK 0x0000ff00 +#define RB_STENCILREFMASK_STENCILWRITEMASK_MASK 0x00ff0000 +#define RB_STENCILREFMASK_RESERVED0_MASK 0x01000000 +#define RB_STENCILREFMASK_RESERVED1_MASK 0x02000000 + +#define RB_STENCILREFMASK_MASK \ + (RB_STENCILREFMASK_STENCILREF_MASK | \ + RB_STENCILREFMASK_STENCILMASK_MASK | \ + RB_STENCILREFMASK_STENCILWRITEMASK_MASK | \ + RB_STENCILREFMASK_RESERVED0_MASK | \ + RB_STENCILREFMASK_RESERVED1_MASK) + +#define RB_STENCILREFMASK(stencilref, stencilmask, stencilwritemask, reserved0, reserved1) \ + ((stencilref << RB_STENCILREFMASK_STENCILREF_SHIFT) | \ + (stencilmask << RB_STENCILREFMASK_STENCILMASK_SHIFT) | \ + (stencilwritemask << RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT) | \ + (reserved0 << RB_STENCILREFMASK_RESERVED0_SHIFT) | \ + (reserved1 << RB_STENCILREFMASK_RESERVED1_SHIFT)) + +#define RB_STENCILREFMASK_GET_STENCILREF(rb_stencilrefmask) \ + ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILREF_MASK) >> RB_STENCILREFMASK_STENCILREF_SHIFT) +#define RB_STENCILREFMASK_GET_STENCILMASK(rb_stencilrefmask) \ + ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILMASK_MASK) >> RB_STENCILREFMASK_STENCILMASK_SHIFT) +#define RB_STENCILREFMASK_GET_STENCILWRITEMASK(rb_stencilrefmask) \ + ((rb_stencilrefmask & RB_STENCILREFMASK_STENCILWRITEMASK_MASK) >> RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT) +#define RB_STENCILREFMASK_GET_RESERVED0(rb_stencilrefmask) \ + ((rb_stencilrefmask & RB_STENCILREFMASK_RESERVED0_MASK) >> RB_STENCILREFMASK_RESERVED0_SHIFT) +#define RB_STENCILREFMASK_GET_RESERVED1(rb_stencilrefmask) \ + ((rb_stencilrefmask & RB_STENCILREFMASK_RESERVED1_MASK) >> RB_STENCILREFMASK_RESERVED1_SHIFT) + +#define RB_STENCILREFMASK_SET_STENCILREF(rb_stencilrefmask_reg, stencilref) \ + rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILREF_MASK) | (stencilref << RB_STENCILREFMASK_STENCILREF_SHIFT) +#define RB_STENCILREFMASK_SET_STENCILMASK(rb_stencilrefmask_reg, stencilmask) \ + rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILMASK_MASK) | (stencilmask << RB_STENCILREFMASK_STENCILMASK_SHIFT) +#define RB_STENCILREFMASK_SET_STENCILWRITEMASK(rb_stencilrefmask_reg, stencilwritemask) \ + rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_STENCILWRITEMASK_MASK) | (stencilwritemask << RB_STENCILREFMASK_STENCILWRITEMASK_SHIFT) +#define RB_STENCILREFMASK_SET_RESERVED0(rb_stencilrefmask_reg, reserved0) \ + rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_RESERVED0_MASK) | (reserved0 << RB_STENCILREFMASK_RESERVED0_SHIFT) +#define RB_STENCILREFMASK_SET_RESERVED1(rb_stencilrefmask_reg, reserved1) \ + rb_stencilrefmask_reg = (rb_stencilrefmask_reg & ~RB_STENCILREFMASK_RESERVED1_MASK) | (reserved1 << RB_STENCILREFMASK_RESERVED1_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_stencilrefmask_t { + unsigned int stencilref : RB_STENCILREFMASK_STENCILREF_SIZE; + unsigned int stencilmask : RB_STENCILREFMASK_STENCILMASK_SIZE; + unsigned int stencilwritemask : RB_STENCILREFMASK_STENCILWRITEMASK_SIZE; + unsigned int reserved0 : RB_STENCILREFMASK_RESERVED0_SIZE; + unsigned int reserved1 : RB_STENCILREFMASK_RESERVED1_SIZE; + unsigned int : 6; + } rb_stencilrefmask_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_stencilrefmask_t { + unsigned int : 6; + unsigned int reserved1 : RB_STENCILREFMASK_RESERVED1_SIZE; + unsigned int reserved0 : RB_STENCILREFMASK_RESERVED0_SIZE; + unsigned int stencilwritemask : RB_STENCILREFMASK_STENCILWRITEMASK_SIZE; + unsigned int stencilmask : RB_STENCILREFMASK_STENCILMASK_SIZE; + unsigned int stencilref : RB_STENCILREFMASK_STENCILREF_SIZE; + } rb_stencilrefmask_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_stencilrefmask_t f; +} rb_stencilrefmask_u; + + +/* + * RB_ALPHA_REF struct + */ + +#define RB_ALPHA_REF_ALPHA_REF_SIZE 32 + +#define RB_ALPHA_REF_ALPHA_REF_SHIFT 0 + +#define RB_ALPHA_REF_ALPHA_REF_MASK 0xffffffff + +#define RB_ALPHA_REF_MASK \ + (RB_ALPHA_REF_ALPHA_REF_MASK) + +#define RB_ALPHA_REF(alpha_ref) \ + ((alpha_ref << RB_ALPHA_REF_ALPHA_REF_SHIFT)) + +#define RB_ALPHA_REF_GET_ALPHA_REF(rb_alpha_ref) \ + ((rb_alpha_ref & RB_ALPHA_REF_ALPHA_REF_MASK) >> RB_ALPHA_REF_ALPHA_REF_SHIFT) + +#define RB_ALPHA_REF_SET_ALPHA_REF(rb_alpha_ref_reg, alpha_ref) \ + rb_alpha_ref_reg = (rb_alpha_ref_reg & ~RB_ALPHA_REF_ALPHA_REF_MASK) | (alpha_ref << RB_ALPHA_REF_ALPHA_REF_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_alpha_ref_t { + unsigned int alpha_ref : RB_ALPHA_REF_ALPHA_REF_SIZE; + } rb_alpha_ref_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_alpha_ref_t { + unsigned int alpha_ref : RB_ALPHA_REF_ALPHA_REF_SIZE; + } rb_alpha_ref_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_alpha_ref_t f; +} rb_alpha_ref_u; + + +/* + * RB_COLOR_MASK struct + */ + +#define RB_COLOR_MASK_WRITE_RED_SIZE 1 +#define RB_COLOR_MASK_WRITE_GREEN_SIZE 1 +#define RB_COLOR_MASK_WRITE_BLUE_SIZE 1 +#define RB_COLOR_MASK_WRITE_ALPHA_SIZE 1 +#define RB_COLOR_MASK_RESERVED2_SIZE 1 +#define RB_COLOR_MASK_RESERVED3_SIZE 1 + +#define RB_COLOR_MASK_WRITE_RED_SHIFT 0 +#define RB_COLOR_MASK_WRITE_GREEN_SHIFT 1 +#define RB_COLOR_MASK_WRITE_BLUE_SHIFT 2 +#define RB_COLOR_MASK_WRITE_ALPHA_SHIFT 3 +#define RB_COLOR_MASK_RESERVED2_SHIFT 4 +#define RB_COLOR_MASK_RESERVED3_SHIFT 5 + +#define RB_COLOR_MASK_WRITE_RED_MASK 0x00000001 +#define RB_COLOR_MASK_WRITE_GREEN_MASK 0x00000002 +#define RB_COLOR_MASK_WRITE_BLUE_MASK 0x00000004 +#define RB_COLOR_MASK_WRITE_ALPHA_MASK 0x00000008 +#define RB_COLOR_MASK_RESERVED2_MASK 0x00000010 +#define RB_COLOR_MASK_RESERVED3_MASK 0x00000020 + +#define RB_COLOR_MASK_MASK \ + (RB_COLOR_MASK_WRITE_RED_MASK | \ + RB_COLOR_MASK_WRITE_GREEN_MASK | \ + RB_COLOR_MASK_WRITE_BLUE_MASK | \ + RB_COLOR_MASK_WRITE_ALPHA_MASK | \ + RB_COLOR_MASK_RESERVED2_MASK | \ + RB_COLOR_MASK_RESERVED3_MASK) + +#define RB_COLOR_MASK(write_red, write_green, write_blue, write_alpha, reserved2, reserved3) \ + ((write_red << RB_COLOR_MASK_WRITE_RED_SHIFT) | \ + (write_green << RB_COLOR_MASK_WRITE_GREEN_SHIFT) | \ + (write_blue << RB_COLOR_MASK_WRITE_BLUE_SHIFT) | \ + (write_alpha << RB_COLOR_MASK_WRITE_ALPHA_SHIFT) | \ + (reserved2 << RB_COLOR_MASK_RESERVED2_SHIFT) | \ + (reserved3 << RB_COLOR_MASK_RESERVED3_SHIFT)) + +#define RB_COLOR_MASK_GET_WRITE_RED(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_WRITE_RED_MASK) >> RB_COLOR_MASK_WRITE_RED_SHIFT) +#define RB_COLOR_MASK_GET_WRITE_GREEN(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_WRITE_GREEN_MASK) >> RB_COLOR_MASK_WRITE_GREEN_SHIFT) +#define RB_COLOR_MASK_GET_WRITE_BLUE(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_WRITE_BLUE_MASK) >> RB_COLOR_MASK_WRITE_BLUE_SHIFT) +#define RB_COLOR_MASK_GET_WRITE_ALPHA(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_WRITE_ALPHA_MASK) >> RB_COLOR_MASK_WRITE_ALPHA_SHIFT) +#define RB_COLOR_MASK_GET_RESERVED2(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_RESERVED2_MASK) >> RB_COLOR_MASK_RESERVED2_SHIFT) +#define RB_COLOR_MASK_GET_RESERVED3(rb_color_mask) \ + ((rb_color_mask & RB_COLOR_MASK_RESERVED3_MASK) >> RB_COLOR_MASK_RESERVED3_SHIFT) + +#define RB_COLOR_MASK_SET_WRITE_RED(rb_color_mask_reg, write_red) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_RED_MASK) | (write_red << RB_COLOR_MASK_WRITE_RED_SHIFT) +#define RB_COLOR_MASK_SET_WRITE_GREEN(rb_color_mask_reg, write_green) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_GREEN_MASK) | (write_green << RB_COLOR_MASK_WRITE_GREEN_SHIFT) +#define RB_COLOR_MASK_SET_WRITE_BLUE(rb_color_mask_reg, write_blue) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_BLUE_MASK) | (write_blue << RB_COLOR_MASK_WRITE_BLUE_SHIFT) +#define RB_COLOR_MASK_SET_WRITE_ALPHA(rb_color_mask_reg, write_alpha) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_WRITE_ALPHA_MASK) | (write_alpha << RB_COLOR_MASK_WRITE_ALPHA_SHIFT) +#define RB_COLOR_MASK_SET_RESERVED2(rb_color_mask_reg, reserved2) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_RESERVED2_MASK) | (reserved2 << RB_COLOR_MASK_RESERVED2_SHIFT) +#define RB_COLOR_MASK_SET_RESERVED3(rb_color_mask_reg, reserved3) \ + rb_color_mask_reg = (rb_color_mask_reg & ~RB_COLOR_MASK_RESERVED3_MASK) | (reserved3 << RB_COLOR_MASK_RESERVED3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_color_mask_t { + unsigned int write_red : RB_COLOR_MASK_WRITE_RED_SIZE; + unsigned int write_green : RB_COLOR_MASK_WRITE_GREEN_SIZE; + unsigned int write_blue : RB_COLOR_MASK_WRITE_BLUE_SIZE; + unsigned int write_alpha : RB_COLOR_MASK_WRITE_ALPHA_SIZE; + unsigned int reserved2 : RB_COLOR_MASK_RESERVED2_SIZE; + unsigned int reserved3 : RB_COLOR_MASK_RESERVED3_SIZE; + unsigned int : 26; + } rb_color_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_color_mask_t { + unsigned int : 26; + unsigned int reserved3 : RB_COLOR_MASK_RESERVED3_SIZE; + unsigned int reserved2 : RB_COLOR_MASK_RESERVED2_SIZE; + unsigned int write_alpha : RB_COLOR_MASK_WRITE_ALPHA_SIZE; + unsigned int write_blue : RB_COLOR_MASK_WRITE_BLUE_SIZE; + unsigned int write_green : RB_COLOR_MASK_WRITE_GREEN_SIZE; + unsigned int write_red : RB_COLOR_MASK_WRITE_RED_SIZE; + } rb_color_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_color_mask_t f; +} rb_color_mask_u; + + +/* + * RB_BLEND_RED struct + */ + +#define RB_BLEND_RED_BLEND_RED_SIZE 8 + +#define RB_BLEND_RED_BLEND_RED_SHIFT 0 + +#define RB_BLEND_RED_BLEND_RED_MASK 0x000000ff + +#define RB_BLEND_RED_MASK \ + (RB_BLEND_RED_BLEND_RED_MASK) + +#define RB_BLEND_RED(blend_red) \ + ((blend_red << RB_BLEND_RED_BLEND_RED_SHIFT)) + +#define RB_BLEND_RED_GET_BLEND_RED(rb_blend_red) \ + ((rb_blend_red & RB_BLEND_RED_BLEND_RED_MASK) >> RB_BLEND_RED_BLEND_RED_SHIFT) + +#define RB_BLEND_RED_SET_BLEND_RED(rb_blend_red_reg, blend_red) \ + rb_blend_red_reg = (rb_blend_red_reg & ~RB_BLEND_RED_BLEND_RED_MASK) | (blend_red << RB_BLEND_RED_BLEND_RED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blend_red_t { + unsigned int blend_red : RB_BLEND_RED_BLEND_RED_SIZE; + unsigned int : 24; + } rb_blend_red_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blend_red_t { + unsigned int : 24; + unsigned int blend_red : RB_BLEND_RED_BLEND_RED_SIZE; + } rb_blend_red_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blend_red_t f; +} rb_blend_red_u; + + +/* + * RB_BLEND_GREEN struct + */ + +#define RB_BLEND_GREEN_BLEND_GREEN_SIZE 8 + +#define RB_BLEND_GREEN_BLEND_GREEN_SHIFT 0 + +#define RB_BLEND_GREEN_BLEND_GREEN_MASK 0x000000ff + +#define RB_BLEND_GREEN_MASK \ + (RB_BLEND_GREEN_BLEND_GREEN_MASK) + +#define RB_BLEND_GREEN(blend_green) \ + ((blend_green << RB_BLEND_GREEN_BLEND_GREEN_SHIFT)) + +#define RB_BLEND_GREEN_GET_BLEND_GREEN(rb_blend_green) \ + ((rb_blend_green & RB_BLEND_GREEN_BLEND_GREEN_MASK) >> RB_BLEND_GREEN_BLEND_GREEN_SHIFT) + +#define RB_BLEND_GREEN_SET_BLEND_GREEN(rb_blend_green_reg, blend_green) \ + rb_blend_green_reg = (rb_blend_green_reg & ~RB_BLEND_GREEN_BLEND_GREEN_MASK) | (blend_green << RB_BLEND_GREEN_BLEND_GREEN_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blend_green_t { + unsigned int blend_green : RB_BLEND_GREEN_BLEND_GREEN_SIZE; + unsigned int : 24; + } rb_blend_green_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blend_green_t { + unsigned int : 24; + unsigned int blend_green : RB_BLEND_GREEN_BLEND_GREEN_SIZE; + } rb_blend_green_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blend_green_t f; +} rb_blend_green_u; + + +/* + * RB_BLEND_BLUE struct + */ + +#define RB_BLEND_BLUE_BLEND_BLUE_SIZE 8 + +#define RB_BLEND_BLUE_BLEND_BLUE_SHIFT 0 + +#define RB_BLEND_BLUE_BLEND_BLUE_MASK 0x000000ff + +#define RB_BLEND_BLUE_MASK \ + (RB_BLEND_BLUE_BLEND_BLUE_MASK) + +#define RB_BLEND_BLUE(blend_blue) \ + ((blend_blue << RB_BLEND_BLUE_BLEND_BLUE_SHIFT)) + +#define RB_BLEND_BLUE_GET_BLEND_BLUE(rb_blend_blue) \ + ((rb_blend_blue & RB_BLEND_BLUE_BLEND_BLUE_MASK) >> RB_BLEND_BLUE_BLEND_BLUE_SHIFT) + +#define RB_BLEND_BLUE_SET_BLEND_BLUE(rb_blend_blue_reg, blend_blue) \ + rb_blend_blue_reg = (rb_blend_blue_reg & ~RB_BLEND_BLUE_BLEND_BLUE_MASK) | (blend_blue << RB_BLEND_BLUE_BLEND_BLUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blend_blue_t { + unsigned int blend_blue : RB_BLEND_BLUE_BLEND_BLUE_SIZE; + unsigned int : 24; + } rb_blend_blue_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blend_blue_t { + unsigned int : 24; + unsigned int blend_blue : RB_BLEND_BLUE_BLEND_BLUE_SIZE; + } rb_blend_blue_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blend_blue_t f; +} rb_blend_blue_u; + + +/* + * RB_BLEND_ALPHA struct + */ + +#define RB_BLEND_ALPHA_BLEND_ALPHA_SIZE 8 + +#define RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT 0 + +#define RB_BLEND_ALPHA_BLEND_ALPHA_MASK 0x000000ff + +#define RB_BLEND_ALPHA_MASK \ + (RB_BLEND_ALPHA_BLEND_ALPHA_MASK) + +#define RB_BLEND_ALPHA(blend_alpha) \ + ((blend_alpha << RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT)) + +#define RB_BLEND_ALPHA_GET_BLEND_ALPHA(rb_blend_alpha) \ + ((rb_blend_alpha & RB_BLEND_ALPHA_BLEND_ALPHA_MASK) >> RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT) + +#define RB_BLEND_ALPHA_SET_BLEND_ALPHA(rb_blend_alpha_reg, blend_alpha) \ + rb_blend_alpha_reg = (rb_blend_alpha_reg & ~RB_BLEND_ALPHA_BLEND_ALPHA_MASK) | (blend_alpha << RB_BLEND_ALPHA_BLEND_ALPHA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blend_alpha_t { + unsigned int blend_alpha : RB_BLEND_ALPHA_BLEND_ALPHA_SIZE; + unsigned int : 24; + } rb_blend_alpha_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blend_alpha_t { + unsigned int : 24; + unsigned int blend_alpha : RB_BLEND_ALPHA_BLEND_ALPHA_SIZE; + } rb_blend_alpha_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blend_alpha_t f; +} rb_blend_alpha_u; + + +/* + * RB_FOG_COLOR struct + */ + +#define RB_FOG_COLOR_FOG_RED_SIZE 8 +#define RB_FOG_COLOR_FOG_GREEN_SIZE 8 +#define RB_FOG_COLOR_FOG_BLUE_SIZE 8 + +#define RB_FOG_COLOR_FOG_RED_SHIFT 0 +#define RB_FOG_COLOR_FOG_GREEN_SHIFT 8 +#define RB_FOG_COLOR_FOG_BLUE_SHIFT 16 + +#define RB_FOG_COLOR_FOG_RED_MASK 0x000000ff +#define RB_FOG_COLOR_FOG_GREEN_MASK 0x0000ff00 +#define RB_FOG_COLOR_FOG_BLUE_MASK 0x00ff0000 + +#define RB_FOG_COLOR_MASK \ + (RB_FOG_COLOR_FOG_RED_MASK | \ + RB_FOG_COLOR_FOG_GREEN_MASK | \ + RB_FOG_COLOR_FOG_BLUE_MASK) + +#define RB_FOG_COLOR(fog_red, fog_green, fog_blue) \ + ((fog_red << RB_FOG_COLOR_FOG_RED_SHIFT) | \ + (fog_green << RB_FOG_COLOR_FOG_GREEN_SHIFT) | \ + (fog_blue << RB_FOG_COLOR_FOG_BLUE_SHIFT)) + +#define RB_FOG_COLOR_GET_FOG_RED(rb_fog_color) \ + ((rb_fog_color & RB_FOG_COLOR_FOG_RED_MASK) >> RB_FOG_COLOR_FOG_RED_SHIFT) +#define RB_FOG_COLOR_GET_FOG_GREEN(rb_fog_color) \ + ((rb_fog_color & RB_FOG_COLOR_FOG_GREEN_MASK) >> RB_FOG_COLOR_FOG_GREEN_SHIFT) +#define RB_FOG_COLOR_GET_FOG_BLUE(rb_fog_color) \ + ((rb_fog_color & RB_FOG_COLOR_FOG_BLUE_MASK) >> RB_FOG_COLOR_FOG_BLUE_SHIFT) + +#define RB_FOG_COLOR_SET_FOG_RED(rb_fog_color_reg, fog_red) \ + rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_RED_MASK) | (fog_red << RB_FOG_COLOR_FOG_RED_SHIFT) +#define RB_FOG_COLOR_SET_FOG_GREEN(rb_fog_color_reg, fog_green) \ + rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_GREEN_MASK) | (fog_green << RB_FOG_COLOR_FOG_GREEN_SHIFT) +#define RB_FOG_COLOR_SET_FOG_BLUE(rb_fog_color_reg, fog_blue) \ + rb_fog_color_reg = (rb_fog_color_reg & ~RB_FOG_COLOR_FOG_BLUE_MASK) | (fog_blue << RB_FOG_COLOR_FOG_BLUE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_fog_color_t { + unsigned int fog_red : RB_FOG_COLOR_FOG_RED_SIZE; + unsigned int fog_green : RB_FOG_COLOR_FOG_GREEN_SIZE; + unsigned int fog_blue : RB_FOG_COLOR_FOG_BLUE_SIZE; + unsigned int : 8; + } rb_fog_color_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_fog_color_t { + unsigned int : 8; + unsigned int fog_blue : RB_FOG_COLOR_FOG_BLUE_SIZE; + unsigned int fog_green : RB_FOG_COLOR_FOG_GREEN_SIZE; + unsigned int fog_red : RB_FOG_COLOR_FOG_RED_SIZE; + } rb_fog_color_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_fog_color_t f; +} rb_fog_color_u; + + +/* + * RB_STENCILREFMASK_BF struct + */ + +#define RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE 8 +#define RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE 8 +#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE 8 +#define RB_STENCILREFMASK_BF_RESERVED4_SIZE 1 +#define RB_STENCILREFMASK_BF_RESERVED5_SIZE 1 + +#define RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT 0 +#define RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT 8 +#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT 16 +#define RB_STENCILREFMASK_BF_RESERVED4_SHIFT 24 +#define RB_STENCILREFMASK_BF_RESERVED5_SHIFT 25 + +#define RB_STENCILREFMASK_BF_STENCILREF_BF_MASK 0x000000ff +#define RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK 0x0000ff00 +#define RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK 0x00ff0000 +#define RB_STENCILREFMASK_BF_RESERVED4_MASK 0x01000000 +#define RB_STENCILREFMASK_BF_RESERVED5_MASK 0x02000000 + +#define RB_STENCILREFMASK_BF_MASK \ + (RB_STENCILREFMASK_BF_STENCILREF_BF_MASK | \ + RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK | \ + RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK | \ + RB_STENCILREFMASK_BF_RESERVED4_MASK | \ + RB_STENCILREFMASK_BF_RESERVED5_MASK) + +#define RB_STENCILREFMASK_BF(stencilref_bf, stencilmask_bf, stencilwritemask_bf, reserved4, reserved5) \ + ((stencilref_bf << RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT) | \ + (stencilmask_bf << RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT) | \ + (stencilwritemask_bf << RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT) | \ + (reserved4 << RB_STENCILREFMASK_BF_RESERVED4_SHIFT) | \ + (reserved5 << RB_STENCILREFMASK_BF_RESERVED5_SHIFT)) + +#define RB_STENCILREFMASK_BF_GET_STENCILREF_BF(rb_stencilrefmask_bf) \ + ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILREF_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT) +#define RB_STENCILREFMASK_BF_GET_STENCILMASK_BF(rb_stencilrefmask_bf) \ + ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT) +#define RB_STENCILREFMASK_BF_GET_STENCILWRITEMASK_BF(rb_stencilrefmask_bf) \ + ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK) >> RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT) +#define RB_STENCILREFMASK_BF_GET_RESERVED4(rb_stencilrefmask_bf) \ + ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_RESERVED4_MASK) >> RB_STENCILREFMASK_BF_RESERVED4_SHIFT) +#define RB_STENCILREFMASK_BF_GET_RESERVED5(rb_stencilrefmask_bf) \ + ((rb_stencilrefmask_bf & RB_STENCILREFMASK_BF_RESERVED5_MASK) >> RB_STENCILREFMASK_BF_RESERVED5_SHIFT) + +#define RB_STENCILREFMASK_BF_SET_STENCILREF_BF(rb_stencilrefmask_bf_reg, stencilref_bf) \ + rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILREF_BF_MASK) | (stencilref_bf << RB_STENCILREFMASK_BF_STENCILREF_BF_SHIFT) +#define RB_STENCILREFMASK_BF_SET_STENCILMASK_BF(rb_stencilrefmask_bf_reg, stencilmask_bf) \ + rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILMASK_BF_MASK) | (stencilmask_bf << RB_STENCILREFMASK_BF_STENCILMASK_BF_SHIFT) +#define RB_STENCILREFMASK_BF_SET_STENCILWRITEMASK_BF(rb_stencilrefmask_bf_reg, stencilwritemask_bf) \ + rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK) | (stencilwritemask_bf << RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SHIFT) +#define RB_STENCILREFMASK_BF_SET_RESERVED4(rb_stencilrefmask_bf_reg, reserved4) \ + rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_RESERVED4_MASK) | (reserved4 << RB_STENCILREFMASK_BF_RESERVED4_SHIFT) +#define RB_STENCILREFMASK_BF_SET_RESERVED5(rb_stencilrefmask_bf_reg, reserved5) \ + rb_stencilrefmask_bf_reg = (rb_stencilrefmask_bf_reg & ~RB_STENCILREFMASK_BF_RESERVED5_MASK) | (reserved5 << RB_STENCILREFMASK_BF_RESERVED5_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_stencilrefmask_bf_t { + unsigned int stencilref_bf : RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE; + unsigned int stencilmask_bf : RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE; + unsigned int stencilwritemask_bf : RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE; + unsigned int reserved4 : RB_STENCILREFMASK_BF_RESERVED4_SIZE; + unsigned int reserved5 : RB_STENCILREFMASK_BF_RESERVED5_SIZE; + unsigned int : 6; + } rb_stencilrefmask_bf_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_stencilrefmask_bf_t { + unsigned int : 6; + unsigned int reserved5 : RB_STENCILREFMASK_BF_RESERVED5_SIZE; + unsigned int reserved4 : RB_STENCILREFMASK_BF_RESERVED4_SIZE; + unsigned int stencilwritemask_bf : RB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_SIZE; + unsigned int stencilmask_bf : RB_STENCILREFMASK_BF_STENCILMASK_BF_SIZE; + unsigned int stencilref_bf : RB_STENCILREFMASK_BF_STENCILREF_BF_SIZE; + } rb_stencilrefmask_bf_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_stencilrefmask_bf_t f; +} rb_stencilrefmask_bf_u; + + +/* + * RB_DEPTHCONTROL struct + */ + +#define RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_Z_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_ZFUNC_SIZE 3 +#define RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE 1 +#define RB_DEPTHCONTROL_STENCILFUNC_SIZE 3 +#define RB_DEPTHCONTROL_STENCILFAIL_SIZE 3 +#define RB_DEPTHCONTROL_STENCILZPASS_SIZE 3 +#define RB_DEPTHCONTROL_STENCILZFAIL_SIZE 3 +#define RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE 3 +#define RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE 3 +#define RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE 3 +#define RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE 3 + +#define RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT 0 +#define RB_DEPTHCONTROL_Z_ENABLE_SHIFT 1 +#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT 2 +#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT 3 +#define RB_DEPTHCONTROL_ZFUNC_SHIFT 4 +#define RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT 7 +#define RB_DEPTHCONTROL_STENCILFUNC_SHIFT 8 +#define RB_DEPTHCONTROL_STENCILFAIL_SHIFT 11 +#define RB_DEPTHCONTROL_STENCILZPASS_SHIFT 14 +#define RB_DEPTHCONTROL_STENCILZFAIL_SHIFT 17 +#define RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT 20 +#define RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT 23 +#define RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT 26 +#define RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT 29 + +#define RB_DEPTHCONTROL_STENCIL_ENABLE_MASK 0x00000001 +#define RB_DEPTHCONTROL_Z_ENABLE_MASK 0x00000002 +#define RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK 0x00000004 +#define RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK 0x00000008 +#define RB_DEPTHCONTROL_ZFUNC_MASK 0x00000070 +#define RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK 0x00000080 +#define RB_DEPTHCONTROL_STENCILFUNC_MASK 0x00000700 +#define RB_DEPTHCONTROL_STENCILFAIL_MASK 0x00003800 +#define RB_DEPTHCONTROL_STENCILZPASS_MASK 0x0001c000 +#define RB_DEPTHCONTROL_STENCILZFAIL_MASK 0x000e0000 +#define RB_DEPTHCONTROL_STENCILFUNC_BF_MASK 0x00700000 +#define RB_DEPTHCONTROL_STENCILFAIL_BF_MASK 0x03800000 +#define RB_DEPTHCONTROL_STENCILZPASS_BF_MASK 0x1c000000 +#define RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK 0xe0000000 + +#define RB_DEPTHCONTROL_MASK \ + (RB_DEPTHCONTROL_STENCIL_ENABLE_MASK | \ + RB_DEPTHCONTROL_Z_ENABLE_MASK | \ + RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK | \ + RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK | \ + RB_DEPTHCONTROL_ZFUNC_MASK | \ + RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK | \ + RB_DEPTHCONTROL_STENCILFUNC_MASK | \ + RB_DEPTHCONTROL_STENCILFAIL_MASK | \ + RB_DEPTHCONTROL_STENCILZPASS_MASK | \ + RB_DEPTHCONTROL_STENCILZFAIL_MASK | \ + RB_DEPTHCONTROL_STENCILFUNC_BF_MASK | \ + RB_DEPTHCONTROL_STENCILFAIL_BF_MASK | \ + RB_DEPTHCONTROL_STENCILZPASS_BF_MASK | \ + RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) + +#define RB_DEPTHCONTROL(stencil_enable, z_enable, z_write_enable, early_z_enable, zfunc, backface_enable, stencilfunc, stencilfail, stencilzpass, stencilzfail, stencilfunc_bf, stencilfail_bf, stencilzpass_bf, stencilzfail_bf) \ + ((stencil_enable << RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT) | \ + (z_enable << RB_DEPTHCONTROL_Z_ENABLE_SHIFT) | \ + (z_write_enable << RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT) | \ + (early_z_enable << RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT) | \ + (zfunc << RB_DEPTHCONTROL_ZFUNC_SHIFT) | \ + (backface_enable << RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT) | \ + (stencilfunc << RB_DEPTHCONTROL_STENCILFUNC_SHIFT) | \ + (stencilfail << RB_DEPTHCONTROL_STENCILFAIL_SHIFT) | \ + (stencilzpass << RB_DEPTHCONTROL_STENCILZPASS_SHIFT) | \ + (stencilzfail << RB_DEPTHCONTROL_STENCILZFAIL_SHIFT) | \ + (stencilfunc_bf << RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT) | \ + (stencilfail_bf << RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT) | \ + (stencilzpass_bf << RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT) | \ + (stencilzfail_bf << RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT)) + +#define RB_DEPTHCONTROL_GET_STENCIL_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCIL_ENABLE_MASK) >> RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_Z_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_Z_ENABLE_MASK) >> RB_DEPTHCONTROL_Z_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_Z_WRITE_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK) >> RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_EARLY_Z_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK) >> RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_ZFUNC(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_ZFUNC_MASK) >> RB_DEPTHCONTROL_ZFUNC_SHIFT) +#define RB_DEPTHCONTROL_GET_BACKFACE_ENABLE(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK) >> RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILFUNC(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFUNC_MASK) >> RB_DEPTHCONTROL_STENCILFUNC_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILFAIL(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFAIL_MASK) >> RB_DEPTHCONTROL_STENCILFAIL_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILZPASS(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZPASS_MASK) >> RB_DEPTHCONTROL_STENCILZPASS_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILZFAIL(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZFAIL_MASK) >> RB_DEPTHCONTROL_STENCILZFAIL_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILFUNC_BF(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFUNC_BF_MASK) >> RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILFAIL_BF(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILFAIL_BF_MASK) >> RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILZPASS_BF(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZPASS_BF_MASK) >> RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT) +#define RB_DEPTHCONTROL_GET_STENCILZFAIL_BF(rb_depthcontrol) \ + ((rb_depthcontrol & RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) >> RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT) + +#define RB_DEPTHCONTROL_SET_STENCIL_ENABLE(rb_depthcontrol_reg, stencil_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCIL_ENABLE_MASK) | (stencil_enable << RB_DEPTHCONTROL_STENCIL_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_Z_ENABLE(rb_depthcontrol_reg, z_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_Z_ENABLE_MASK) | (z_enable << RB_DEPTHCONTROL_Z_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_Z_WRITE_ENABLE(rb_depthcontrol_reg, z_write_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_Z_WRITE_ENABLE_MASK) | (z_write_enable << RB_DEPTHCONTROL_Z_WRITE_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_EARLY_Z_ENABLE(rb_depthcontrol_reg, early_z_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_EARLY_Z_ENABLE_MASK) | (early_z_enable << RB_DEPTHCONTROL_EARLY_Z_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_ZFUNC(rb_depthcontrol_reg, zfunc) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_ZFUNC_MASK) | (zfunc << RB_DEPTHCONTROL_ZFUNC_SHIFT) +#define RB_DEPTHCONTROL_SET_BACKFACE_ENABLE(rb_depthcontrol_reg, backface_enable) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_BACKFACE_ENABLE_MASK) | (backface_enable << RB_DEPTHCONTROL_BACKFACE_ENABLE_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILFUNC(rb_depthcontrol_reg, stencilfunc) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFUNC_MASK) | (stencilfunc << RB_DEPTHCONTROL_STENCILFUNC_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILFAIL(rb_depthcontrol_reg, stencilfail) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFAIL_MASK) | (stencilfail << RB_DEPTHCONTROL_STENCILFAIL_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILZPASS(rb_depthcontrol_reg, stencilzpass) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZPASS_MASK) | (stencilzpass << RB_DEPTHCONTROL_STENCILZPASS_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILZFAIL(rb_depthcontrol_reg, stencilzfail) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZFAIL_MASK) | (stencilzfail << RB_DEPTHCONTROL_STENCILZFAIL_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILFUNC_BF(rb_depthcontrol_reg, stencilfunc_bf) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFUNC_BF_MASK) | (stencilfunc_bf << RB_DEPTHCONTROL_STENCILFUNC_BF_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILFAIL_BF(rb_depthcontrol_reg, stencilfail_bf) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILFAIL_BF_MASK) | (stencilfail_bf << RB_DEPTHCONTROL_STENCILFAIL_BF_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILZPASS_BF(rb_depthcontrol_reg, stencilzpass_bf) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZPASS_BF_MASK) | (stencilzpass_bf << RB_DEPTHCONTROL_STENCILZPASS_BF_SHIFT) +#define RB_DEPTHCONTROL_SET_STENCILZFAIL_BF(rb_depthcontrol_reg, stencilzfail_bf) \ + rb_depthcontrol_reg = (rb_depthcontrol_reg & ~RB_DEPTHCONTROL_STENCILZFAIL_BF_MASK) | (stencilzfail_bf << RB_DEPTHCONTROL_STENCILZFAIL_BF_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_depthcontrol_t { + unsigned int stencil_enable : RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE; + unsigned int z_enable : RB_DEPTHCONTROL_Z_ENABLE_SIZE; + unsigned int z_write_enable : RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE; + unsigned int early_z_enable : RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE; + unsigned int zfunc : RB_DEPTHCONTROL_ZFUNC_SIZE; + unsigned int backface_enable : RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE; + unsigned int stencilfunc : RB_DEPTHCONTROL_STENCILFUNC_SIZE; + unsigned int stencilfail : RB_DEPTHCONTROL_STENCILFAIL_SIZE; + unsigned int stencilzpass : RB_DEPTHCONTROL_STENCILZPASS_SIZE; + unsigned int stencilzfail : RB_DEPTHCONTROL_STENCILZFAIL_SIZE; + unsigned int stencilfunc_bf : RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE; + unsigned int stencilfail_bf : RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE; + unsigned int stencilzpass_bf : RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE; + unsigned int stencilzfail_bf : RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE; + } rb_depthcontrol_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_depthcontrol_t { + unsigned int stencilzfail_bf : RB_DEPTHCONTROL_STENCILZFAIL_BF_SIZE; + unsigned int stencilzpass_bf : RB_DEPTHCONTROL_STENCILZPASS_BF_SIZE; + unsigned int stencilfail_bf : RB_DEPTHCONTROL_STENCILFAIL_BF_SIZE; + unsigned int stencilfunc_bf : RB_DEPTHCONTROL_STENCILFUNC_BF_SIZE; + unsigned int stencilzfail : RB_DEPTHCONTROL_STENCILZFAIL_SIZE; + unsigned int stencilzpass : RB_DEPTHCONTROL_STENCILZPASS_SIZE; + unsigned int stencilfail : RB_DEPTHCONTROL_STENCILFAIL_SIZE; + unsigned int stencilfunc : RB_DEPTHCONTROL_STENCILFUNC_SIZE; + unsigned int backface_enable : RB_DEPTHCONTROL_BACKFACE_ENABLE_SIZE; + unsigned int zfunc : RB_DEPTHCONTROL_ZFUNC_SIZE; + unsigned int early_z_enable : RB_DEPTHCONTROL_EARLY_Z_ENABLE_SIZE; + unsigned int z_write_enable : RB_DEPTHCONTROL_Z_WRITE_ENABLE_SIZE; + unsigned int z_enable : RB_DEPTHCONTROL_Z_ENABLE_SIZE; + unsigned int stencil_enable : RB_DEPTHCONTROL_STENCIL_ENABLE_SIZE; + } rb_depthcontrol_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_depthcontrol_t f; +} rb_depthcontrol_u; + + +/* + * RB_BLENDCONTROL struct + */ + +#define RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE 5 +#define RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE 3 +#define RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE 5 +#define RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE 5 +#define RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE 3 +#define RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE 5 +#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE 1 +#define RB_BLENDCONTROL_BLEND_FORCE_SIZE 1 + +#define RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT 0 +#define RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT 5 +#define RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT 8 +#define RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT 16 +#define RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT 21 +#define RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT 24 +#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT 29 +#define RB_BLENDCONTROL_BLEND_FORCE_SHIFT 30 + +#define RB_BLENDCONTROL_COLOR_SRCBLEND_MASK 0x0000001f +#define RB_BLENDCONTROL_COLOR_COMB_FCN_MASK 0x000000e0 +#define RB_BLENDCONTROL_COLOR_DESTBLEND_MASK 0x00001f00 +#define RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK 0x001f0000 +#define RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK 0x00e00000 +#define RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK 0x1f000000 +#define RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK 0x20000000 +#define RB_BLENDCONTROL_BLEND_FORCE_MASK 0x40000000 + +#define RB_BLENDCONTROL_MASK \ + (RB_BLENDCONTROL_COLOR_SRCBLEND_MASK | \ + RB_BLENDCONTROL_COLOR_COMB_FCN_MASK | \ + RB_BLENDCONTROL_COLOR_DESTBLEND_MASK | \ + RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK | \ + RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK | \ + RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK | \ + RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK | \ + RB_BLENDCONTROL_BLEND_FORCE_MASK) + +#define RB_BLENDCONTROL(color_srcblend, color_comb_fcn, color_destblend, alpha_srcblend, alpha_comb_fcn, alpha_destblend, blend_force_enable, blend_force) \ + ((color_srcblend << RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT) | \ + (color_comb_fcn << RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT) | \ + (color_destblend << RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT) | \ + (alpha_srcblend << RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT) | \ + (alpha_comb_fcn << RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT) | \ + (alpha_destblend << RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT) | \ + (blend_force_enable << RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT) | \ + (blend_force << RB_BLENDCONTROL_BLEND_FORCE_SHIFT)) + +#define RB_BLENDCONTROL_GET_COLOR_SRCBLEND(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_SRCBLEND_MASK) >> RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT) +#define RB_BLENDCONTROL_GET_COLOR_COMB_FCN(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_COMB_FCN_MASK) >> RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT) +#define RB_BLENDCONTROL_GET_COLOR_DESTBLEND(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_COLOR_DESTBLEND_MASK) >> RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT) +#define RB_BLENDCONTROL_GET_ALPHA_SRCBLEND(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK) >> RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT) +#define RB_BLENDCONTROL_GET_ALPHA_COMB_FCN(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK) >> RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT) +#define RB_BLENDCONTROL_GET_ALPHA_DESTBLEND(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK) >> RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT) +#define RB_BLENDCONTROL_GET_BLEND_FORCE_ENABLE(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK) >> RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT) +#define RB_BLENDCONTROL_GET_BLEND_FORCE(rb_blendcontrol) \ + ((rb_blendcontrol & RB_BLENDCONTROL_BLEND_FORCE_MASK) >> RB_BLENDCONTROL_BLEND_FORCE_SHIFT) + +#define RB_BLENDCONTROL_SET_COLOR_SRCBLEND(rb_blendcontrol_reg, color_srcblend) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_SRCBLEND_MASK) | (color_srcblend << RB_BLENDCONTROL_COLOR_SRCBLEND_SHIFT) +#define RB_BLENDCONTROL_SET_COLOR_COMB_FCN(rb_blendcontrol_reg, color_comb_fcn) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_COMB_FCN_MASK) | (color_comb_fcn << RB_BLENDCONTROL_COLOR_COMB_FCN_SHIFT) +#define RB_BLENDCONTROL_SET_COLOR_DESTBLEND(rb_blendcontrol_reg, color_destblend) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_COLOR_DESTBLEND_MASK) | (color_destblend << RB_BLENDCONTROL_COLOR_DESTBLEND_SHIFT) +#define RB_BLENDCONTROL_SET_ALPHA_SRCBLEND(rb_blendcontrol_reg, alpha_srcblend) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_SRCBLEND_MASK) | (alpha_srcblend << RB_BLENDCONTROL_ALPHA_SRCBLEND_SHIFT) +#define RB_BLENDCONTROL_SET_ALPHA_COMB_FCN(rb_blendcontrol_reg, alpha_comb_fcn) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_COMB_FCN_MASK) | (alpha_comb_fcn << RB_BLENDCONTROL_ALPHA_COMB_FCN_SHIFT) +#define RB_BLENDCONTROL_SET_ALPHA_DESTBLEND(rb_blendcontrol_reg, alpha_destblend) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_ALPHA_DESTBLEND_MASK) | (alpha_destblend << RB_BLENDCONTROL_ALPHA_DESTBLEND_SHIFT) +#define RB_BLENDCONTROL_SET_BLEND_FORCE_ENABLE(rb_blendcontrol_reg, blend_force_enable) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_BLEND_FORCE_ENABLE_MASK) | (blend_force_enable << RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SHIFT) +#define RB_BLENDCONTROL_SET_BLEND_FORCE(rb_blendcontrol_reg, blend_force) \ + rb_blendcontrol_reg = (rb_blendcontrol_reg & ~RB_BLENDCONTROL_BLEND_FORCE_MASK) | (blend_force << RB_BLENDCONTROL_BLEND_FORCE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_blendcontrol_t { + unsigned int color_srcblend : RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE; + unsigned int color_comb_fcn : RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE; + unsigned int color_destblend : RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE; + unsigned int : 3; + unsigned int alpha_srcblend : RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE; + unsigned int alpha_comb_fcn : RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE; + unsigned int alpha_destblend : RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE; + unsigned int blend_force_enable : RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE; + unsigned int blend_force : RB_BLENDCONTROL_BLEND_FORCE_SIZE; + unsigned int : 1; + } rb_blendcontrol_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_blendcontrol_t { + unsigned int : 1; + unsigned int blend_force : RB_BLENDCONTROL_BLEND_FORCE_SIZE; + unsigned int blend_force_enable : RB_BLENDCONTROL_BLEND_FORCE_ENABLE_SIZE; + unsigned int alpha_destblend : RB_BLENDCONTROL_ALPHA_DESTBLEND_SIZE; + unsigned int alpha_comb_fcn : RB_BLENDCONTROL_ALPHA_COMB_FCN_SIZE; + unsigned int alpha_srcblend : RB_BLENDCONTROL_ALPHA_SRCBLEND_SIZE; + unsigned int : 3; + unsigned int color_destblend : RB_BLENDCONTROL_COLOR_DESTBLEND_SIZE; + unsigned int color_comb_fcn : RB_BLENDCONTROL_COLOR_COMB_FCN_SIZE; + unsigned int color_srcblend : RB_BLENDCONTROL_COLOR_SRCBLEND_SIZE; + } rb_blendcontrol_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_blendcontrol_t f; +} rb_blendcontrol_u; + + +/* + * RB_COLORCONTROL struct + */ + +#define RB_COLORCONTROL_ALPHA_FUNC_SIZE 3 +#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE 1 +#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE 1 +#define RB_COLORCONTROL_BLEND_DISABLE_SIZE 1 +#define RB_COLORCONTROL_FOG_ENABLE_SIZE 1 +#define RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE 1 +#define RB_COLORCONTROL_ROP_CODE_SIZE 4 +#define RB_COLORCONTROL_DITHER_MODE_SIZE 2 +#define RB_COLORCONTROL_DITHER_TYPE_SIZE 2 +#define RB_COLORCONTROL_PIXEL_FOG_SIZE 1 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE 2 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE 2 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE 2 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE 2 + +#define RB_COLORCONTROL_ALPHA_FUNC_SHIFT 0 +#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT 3 +#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT 4 +#define RB_COLORCONTROL_BLEND_DISABLE_SHIFT 5 +#define RB_COLORCONTROL_FOG_ENABLE_SHIFT 6 +#define RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT 7 +#define RB_COLORCONTROL_ROP_CODE_SHIFT 8 +#define RB_COLORCONTROL_DITHER_MODE_SHIFT 12 +#define RB_COLORCONTROL_DITHER_TYPE_SHIFT 14 +#define RB_COLORCONTROL_PIXEL_FOG_SHIFT 16 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT 24 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT 26 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT 28 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT 30 + +#define RB_COLORCONTROL_ALPHA_FUNC_MASK 0x00000007 +#define RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK 0x00000008 +#define RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK 0x00000010 +#define RB_COLORCONTROL_BLEND_DISABLE_MASK 0x00000020 +#define RB_COLORCONTROL_FOG_ENABLE_MASK 0x00000040 +#define RB_COLORCONTROL_VS_EXPORTS_FOG_MASK 0x00000080 +#define RB_COLORCONTROL_ROP_CODE_MASK 0x00000f00 +#define RB_COLORCONTROL_DITHER_MODE_MASK 0x00003000 +#define RB_COLORCONTROL_DITHER_TYPE_MASK 0x0000c000 +#define RB_COLORCONTROL_PIXEL_FOG_MASK 0x00010000 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK 0x03000000 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK 0x0c000000 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK 0x30000000 +#define RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK 0xc0000000 + +#define RB_COLORCONTROL_MASK \ + (RB_COLORCONTROL_ALPHA_FUNC_MASK | \ + RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK | \ + RB_COLORCONTROL_BLEND_DISABLE_MASK | \ + RB_COLORCONTROL_FOG_ENABLE_MASK | \ + RB_COLORCONTROL_VS_EXPORTS_FOG_MASK | \ + RB_COLORCONTROL_ROP_CODE_MASK | \ + RB_COLORCONTROL_DITHER_MODE_MASK | \ + RB_COLORCONTROL_DITHER_TYPE_MASK | \ + RB_COLORCONTROL_PIXEL_FOG_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK | \ + RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) + +#define RB_COLORCONTROL(alpha_func, alpha_test_enable, alpha_to_mask_enable, blend_disable, fog_enable, vs_exports_fog, rop_code, dither_mode, dither_type, pixel_fog, alpha_to_mask_offset0, alpha_to_mask_offset1, alpha_to_mask_offset2, alpha_to_mask_offset3) \ + ((alpha_func << RB_COLORCONTROL_ALPHA_FUNC_SHIFT) | \ + (alpha_test_enable << RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT) | \ + (alpha_to_mask_enable << RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT) | \ + (blend_disable << RB_COLORCONTROL_BLEND_DISABLE_SHIFT) | \ + (fog_enable << RB_COLORCONTROL_FOG_ENABLE_SHIFT) | \ + (vs_exports_fog << RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT) | \ + (rop_code << RB_COLORCONTROL_ROP_CODE_SHIFT) | \ + (dither_mode << RB_COLORCONTROL_DITHER_MODE_SHIFT) | \ + (dither_type << RB_COLORCONTROL_DITHER_TYPE_SHIFT) | \ + (pixel_fog << RB_COLORCONTROL_PIXEL_FOG_SHIFT) | \ + (alpha_to_mask_offset0 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT) | \ + (alpha_to_mask_offset1 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT) | \ + (alpha_to_mask_offset2 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT) | \ + (alpha_to_mask_offset3 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT)) + +#define RB_COLORCONTROL_GET_ALPHA_FUNC(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_FUNC_MASK) >> RB_COLORCONTROL_ALPHA_FUNC_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TEST_ENABLE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK) >> RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_ENABLE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT) +#define RB_COLORCONTROL_GET_BLEND_DISABLE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_BLEND_DISABLE_MASK) >> RB_COLORCONTROL_BLEND_DISABLE_SHIFT) +#define RB_COLORCONTROL_GET_FOG_ENABLE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_FOG_ENABLE_MASK) >> RB_COLORCONTROL_FOG_ENABLE_SHIFT) +#define RB_COLORCONTROL_GET_VS_EXPORTS_FOG(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_VS_EXPORTS_FOG_MASK) >> RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT) +#define RB_COLORCONTROL_GET_ROP_CODE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ROP_CODE_MASK) >> RB_COLORCONTROL_ROP_CODE_SHIFT) +#define RB_COLORCONTROL_GET_DITHER_MODE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_DITHER_MODE_MASK) >> RB_COLORCONTROL_DITHER_MODE_SHIFT) +#define RB_COLORCONTROL_GET_DITHER_TYPE(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_DITHER_TYPE_MASK) >> RB_COLORCONTROL_DITHER_TYPE_SHIFT) +#define RB_COLORCONTROL_GET_PIXEL_FOG(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_PIXEL_FOG_MASK) >> RB_COLORCONTROL_PIXEL_FOG_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET0(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET1(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET2(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT) +#define RB_COLORCONTROL_GET_ALPHA_TO_MASK_OFFSET3(rb_colorcontrol) \ + ((rb_colorcontrol & RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) >> RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT) + +#define RB_COLORCONTROL_SET_ALPHA_FUNC(rb_colorcontrol_reg, alpha_func) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_FUNC_MASK) | (alpha_func << RB_COLORCONTROL_ALPHA_FUNC_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TEST_ENABLE(rb_colorcontrol_reg, alpha_test_enable) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TEST_ENABLE_MASK) | (alpha_test_enable << RB_COLORCONTROL_ALPHA_TEST_ENABLE_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_ENABLE(rb_colorcontrol_reg, alpha_to_mask_enable) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_MASK) | (alpha_to_mask_enable << RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SHIFT) +#define RB_COLORCONTROL_SET_BLEND_DISABLE(rb_colorcontrol_reg, blend_disable) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_BLEND_DISABLE_MASK) | (blend_disable << RB_COLORCONTROL_BLEND_DISABLE_SHIFT) +#define RB_COLORCONTROL_SET_FOG_ENABLE(rb_colorcontrol_reg, fog_enable) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_FOG_ENABLE_MASK) | (fog_enable << RB_COLORCONTROL_FOG_ENABLE_SHIFT) +#define RB_COLORCONTROL_SET_VS_EXPORTS_FOG(rb_colorcontrol_reg, vs_exports_fog) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_VS_EXPORTS_FOG_MASK) | (vs_exports_fog << RB_COLORCONTROL_VS_EXPORTS_FOG_SHIFT) +#define RB_COLORCONTROL_SET_ROP_CODE(rb_colorcontrol_reg, rop_code) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ROP_CODE_MASK) | (rop_code << RB_COLORCONTROL_ROP_CODE_SHIFT) +#define RB_COLORCONTROL_SET_DITHER_MODE(rb_colorcontrol_reg, dither_mode) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_DITHER_MODE_MASK) | (dither_mode << RB_COLORCONTROL_DITHER_MODE_SHIFT) +#define RB_COLORCONTROL_SET_DITHER_TYPE(rb_colorcontrol_reg, dither_type) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_DITHER_TYPE_MASK) | (dither_type << RB_COLORCONTROL_DITHER_TYPE_SHIFT) +#define RB_COLORCONTROL_SET_PIXEL_FOG(rb_colorcontrol_reg, pixel_fog) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_PIXEL_FOG_MASK) | (pixel_fog << RB_COLORCONTROL_PIXEL_FOG_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET0(rb_colorcontrol_reg, alpha_to_mask_offset0) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_MASK) | (alpha_to_mask_offset0 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET1(rb_colorcontrol_reg, alpha_to_mask_offset1) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_MASK) | (alpha_to_mask_offset1 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET2(rb_colorcontrol_reg, alpha_to_mask_offset2) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_MASK) | (alpha_to_mask_offset2 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SHIFT) +#define RB_COLORCONTROL_SET_ALPHA_TO_MASK_OFFSET3(rb_colorcontrol_reg, alpha_to_mask_offset3) \ + rb_colorcontrol_reg = (rb_colorcontrol_reg & ~RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_MASK) | (alpha_to_mask_offset3 << RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_colorcontrol_t { + unsigned int alpha_func : RB_COLORCONTROL_ALPHA_FUNC_SIZE; + unsigned int alpha_test_enable : RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE; + unsigned int alpha_to_mask_enable : RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE; + unsigned int blend_disable : RB_COLORCONTROL_BLEND_DISABLE_SIZE; + unsigned int fog_enable : RB_COLORCONTROL_FOG_ENABLE_SIZE; + unsigned int vs_exports_fog : RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE; + unsigned int rop_code : RB_COLORCONTROL_ROP_CODE_SIZE; + unsigned int dither_mode : RB_COLORCONTROL_DITHER_MODE_SIZE; + unsigned int dither_type : RB_COLORCONTROL_DITHER_TYPE_SIZE; + unsigned int pixel_fog : RB_COLORCONTROL_PIXEL_FOG_SIZE; + unsigned int : 7; + unsigned int alpha_to_mask_offset0 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE; + unsigned int alpha_to_mask_offset1 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE; + unsigned int alpha_to_mask_offset2 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE; + unsigned int alpha_to_mask_offset3 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE; + } rb_colorcontrol_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_colorcontrol_t { + unsigned int alpha_to_mask_offset3 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3_SIZE; + unsigned int alpha_to_mask_offset2 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2_SIZE; + unsigned int alpha_to_mask_offset1 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1_SIZE; + unsigned int alpha_to_mask_offset0 : RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0_SIZE; + unsigned int : 7; + unsigned int pixel_fog : RB_COLORCONTROL_PIXEL_FOG_SIZE; + unsigned int dither_type : RB_COLORCONTROL_DITHER_TYPE_SIZE; + unsigned int dither_mode : RB_COLORCONTROL_DITHER_MODE_SIZE; + unsigned int rop_code : RB_COLORCONTROL_ROP_CODE_SIZE; + unsigned int vs_exports_fog : RB_COLORCONTROL_VS_EXPORTS_FOG_SIZE; + unsigned int fog_enable : RB_COLORCONTROL_FOG_ENABLE_SIZE; + unsigned int blend_disable : RB_COLORCONTROL_BLEND_DISABLE_SIZE; + unsigned int alpha_to_mask_enable : RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE_SIZE; + unsigned int alpha_test_enable : RB_COLORCONTROL_ALPHA_TEST_ENABLE_SIZE; + unsigned int alpha_func : RB_COLORCONTROL_ALPHA_FUNC_SIZE; + } rb_colorcontrol_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_colorcontrol_t f; +} rb_colorcontrol_u; + + +/* + * RB_MODECONTROL struct + */ + +#define RB_MODECONTROL_EDRAM_MODE_SIZE 3 + +#define RB_MODECONTROL_EDRAM_MODE_SHIFT 0 + +#define RB_MODECONTROL_EDRAM_MODE_MASK 0x00000007 + +#define RB_MODECONTROL_MASK \ + (RB_MODECONTROL_EDRAM_MODE_MASK) + +#define RB_MODECONTROL(edram_mode) \ + ((edram_mode << RB_MODECONTROL_EDRAM_MODE_SHIFT)) + +#define RB_MODECONTROL_GET_EDRAM_MODE(rb_modecontrol) \ + ((rb_modecontrol & RB_MODECONTROL_EDRAM_MODE_MASK) >> RB_MODECONTROL_EDRAM_MODE_SHIFT) + +#define RB_MODECONTROL_SET_EDRAM_MODE(rb_modecontrol_reg, edram_mode) \ + rb_modecontrol_reg = (rb_modecontrol_reg & ~RB_MODECONTROL_EDRAM_MODE_MASK) | (edram_mode << RB_MODECONTROL_EDRAM_MODE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_modecontrol_t { + unsigned int edram_mode : RB_MODECONTROL_EDRAM_MODE_SIZE; + unsigned int : 29; + } rb_modecontrol_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_modecontrol_t { + unsigned int : 29; + unsigned int edram_mode : RB_MODECONTROL_EDRAM_MODE_SIZE; + } rb_modecontrol_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_modecontrol_t f; +} rb_modecontrol_u; + + +/* + * RB_COLOR_DEST_MASK struct + */ + +#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE 32 + +#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT 0 + +#define RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK 0xffffffff + +#define RB_COLOR_DEST_MASK_MASK \ + (RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) + +#define RB_COLOR_DEST_MASK(color_dest_mask) \ + ((color_dest_mask << RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT)) + +#define RB_COLOR_DEST_MASK_GET_COLOR_DEST_MASK(rb_color_dest_mask) \ + ((rb_color_dest_mask & RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) >> RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT) + +#define RB_COLOR_DEST_MASK_SET_COLOR_DEST_MASK(rb_color_dest_mask_reg, color_dest_mask) \ + rb_color_dest_mask_reg = (rb_color_dest_mask_reg & ~RB_COLOR_DEST_MASK_COLOR_DEST_MASK_MASK) | (color_dest_mask << RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_color_dest_mask_t { + unsigned int color_dest_mask : RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE; + } rb_color_dest_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_color_dest_mask_t { + unsigned int color_dest_mask : RB_COLOR_DEST_MASK_COLOR_DEST_MASK_SIZE; + } rb_color_dest_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_color_dest_mask_t f; +} rb_color_dest_mask_u; + + +/* + * RB_COPY_CONTROL struct + */ + +#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE 3 +#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE 1 +#define RB_COPY_CONTROL_CLEAR_MASK_SIZE 4 + +#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT 0 +#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT 3 +#define RB_COPY_CONTROL_CLEAR_MASK_SHIFT 4 + +#define RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK 0x00000007 +#define RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK 0x00000008 +#define RB_COPY_CONTROL_CLEAR_MASK_MASK 0x000000f0 + +#define RB_COPY_CONTROL_MASK \ + (RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK | \ + RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK | \ + RB_COPY_CONTROL_CLEAR_MASK_MASK) + +#define RB_COPY_CONTROL(copy_sample_select, depth_clear_enable, clear_mask) \ + ((copy_sample_select << RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT) | \ + (depth_clear_enable << RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT) | \ + (clear_mask << RB_COPY_CONTROL_CLEAR_MASK_SHIFT)) + +#define RB_COPY_CONTROL_GET_COPY_SAMPLE_SELECT(rb_copy_control) \ + ((rb_copy_control & RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK) >> RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT) +#define RB_COPY_CONTROL_GET_DEPTH_CLEAR_ENABLE(rb_copy_control) \ + ((rb_copy_control & RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK) >> RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT) +#define RB_COPY_CONTROL_GET_CLEAR_MASK(rb_copy_control) \ + ((rb_copy_control & RB_COPY_CONTROL_CLEAR_MASK_MASK) >> RB_COPY_CONTROL_CLEAR_MASK_SHIFT) + +#define RB_COPY_CONTROL_SET_COPY_SAMPLE_SELECT(rb_copy_control_reg, copy_sample_select) \ + rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_COPY_SAMPLE_SELECT_MASK) | (copy_sample_select << RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SHIFT) +#define RB_COPY_CONTROL_SET_DEPTH_CLEAR_ENABLE(rb_copy_control_reg, depth_clear_enable) \ + rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_MASK) | (depth_clear_enable << RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT) +#define RB_COPY_CONTROL_SET_CLEAR_MASK(rb_copy_control_reg, clear_mask) \ + rb_copy_control_reg = (rb_copy_control_reg & ~RB_COPY_CONTROL_CLEAR_MASK_MASK) | (clear_mask << RB_COPY_CONTROL_CLEAR_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_control_t { + unsigned int copy_sample_select : RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE; + unsigned int depth_clear_enable : RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE; + unsigned int clear_mask : RB_COPY_CONTROL_CLEAR_MASK_SIZE; + unsigned int : 24; + } rb_copy_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_control_t { + unsigned int : 24; + unsigned int clear_mask : RB_COPY_CONTROL_CLEAR_MASK_SIZE; + unsigned int depth_clear_enable : RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE_SIZE; + unsigned int copy_sample_select : RB_COPY_CONTROL_COPY_SAMPLE_SELECT_SIZE; + } rb_copy_control_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_control_t f; +} rb_copy_control_u; + + +/* + * RB_COPY_DEST_BASE struct + */ + +#define RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE 20 + +#define RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT 12 + +#define RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK 0xfffff000 + +#define RB_COPY_DEST_BASE_MASK \ + (RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) + +#define RB_COPY_DEST_BASE(copy_dest_base) \ + ((copy_dest_base << RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT)) + +#define RB_COPY_DEST_BASE_GET_COPY_DEST_BASE(rb_copy_dest_base) \ + ((rb_copy_dest_base & RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) >> RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT) + +#define RB_COPY_DEST_BASE_SET_COPY_DEST_BASE(rb_copy_dest_base_reg, copy_dest_base) \ + rb_copy_dest_base_reg = (rb_copy_dest_base_reg & ~RB_COPY_DEST_BASE_COPY_DEST_BASE_MASK) | (copy_dest_base << RB_COPY_DEST_BASE_COPY_DEST_BASE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_dest_base_t { + unsigned int : 12; + unsigned int copy_dest_base : RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE; + } rb_copy_dest_base_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_dest_base_t { + unsigned int copy_dest_base : RB_COPY_DEST_BASE_COPY_DEST_BASE_SIZE; + unsigned int : 12; + } rb_copy_dest_base_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_dest_base_t f; +} rb_copy_dest_base_u; + + +/* + * RB_COPY_DEST_PITCH struct + */ + +#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE 9 + +#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT 0 + +#define RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK 0x000001ff + +#define RB_COPY_DEST_PITCH_MASK \ + (RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) + +#define RB_COPY_DEST_PITCH(copy_dest_pitch) \ + ((copy_dest_pitch << RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT)) + +#define RB_COPY_DEST_PITCH_GET_COPY_DEST_PITCH(rb_copy_dest_pitch) \ + ((rb_copy_dest_pitch & RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) >> RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT) + +#define RB_COPY_DEST_PITCH_SET_COPY_DEST_PITCH(rb_copy_dest_pitch_reg, copy_dest_pitch) \ + rb_copy_dest_pitch_reg = (rb_copy_dest_pitch_reg & ~RB_COPY_DEST_PITCH_COPY_DEST_PITCH_MASK) | (copy_dest_pitch << RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_dest_pitch_t { + unsigned int copy_dest_pitch : RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE; + unsigned int : 23; + } rb_copy_dest_pitch_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_dest_pitch_t { + unsigned int : 23; + unsigned int copy_dest_pitch : RB_COPY_DEST_PITCH_COPY_DEST_PITCH_SIZE; + } rb_copy_dest_pitch_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_dest_pitch_t f; +} rb_copy_dest_pitch_u; + + +/* + * RB_COPY_DEST_INFO struct + */ + +#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE 3 +#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE 1 +#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE 4 +#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE 2 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE 2 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE 2 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE 1 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE 1 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE 1 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE 1 + +#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT 0 +#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT 3 +#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT 4 +#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT 8 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT 10 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT 12 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT 14 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT 15 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT 16 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT 17 + +#define RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK 0x00000007 +#define RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK 0x00000008 +#define RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK 0x000000f0 +#define RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK 0x00000300 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK 0x00000c00 +#define RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK 0x00003000 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK 0x00004000 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK 0x00008000 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK 0x00010000 +#define RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK 0x00020000 + +#define RB_COPY_DEST_INFO_MASK \ + (RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK | \ + RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK | \ + RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK | \ + RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK | \ + RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK | \ + RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) + +#define RB_COPY_DEST_INFO(copy_dest_endian, copy_dest_linear, copy_dest_format, copy_dest_swap, copy_dest_dither_mode, copy_dest_dither_type, copy_mask_write_red, copy_mask_write_green, copy_mask_write_blue, copy_mask_write_alpha) \ + ((copy_dest_endian << RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT) | \ + (copy_dest_linear << RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT) | \ + (copy_dest_format << RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT) | \ + (copy_dest_swap << RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT) | \ + (copy_dest_dither_mode << RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT) | \ + (copy_dest_dither_type << RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT) | \ + (copy_mask_write_red << RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT) | \ + (copy_mask_write_green << RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT) | \ + (copy_mask_write_blue << RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT) | \ + (copy_mask_write_alpha << RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT)) + +#define RB_COPY_DEST_INFO_GET_COPY_DEST_ENDIAN(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_LINEAR(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_FORMAT(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_SWAP(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_DITHER_MODE(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_DEST_DITHER_TYPE(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK) >> RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_RED(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_GREEN(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_BLUE(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT) +#define RB_COPY_DEST_INFO_GET_COPY_MASK_WRITE_ALPHA(rb_copy_dest_info) \ + ((rb_copy_dest_info & RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) >> RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT) + +#define RB_COPY_DEST_INFO_SET_COPY_DEST_ENDIAN(rb_copy_dest_info_reg, copy_dest_endian) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_MASK) | (copy_dest_endian << RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_LINEAR(rb_copy_dest_info_reg, copy_dest_linear) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_LINEAR_MASK) | (copy_dest_linear << RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_FORMAT(rb_copy_dest_info_reg, copy_dest_format) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_FORMAT_MASK) | (copy_dest_format << RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_SWAP(rb_copy_dest_info_reg, copy_dest_swap) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_SWAP_MASK) | (copy_dest_swap << RB_COPY_DEST_INFO_COPY_DEST_SWAP_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_DITHER_MODE(rb_copy_dest_info_reg, copy_dest_dither_mode) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_MASK) | (copy_dest_dither_mode << RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_DEST_DITHER_TYPE(rb_copy_dest_info_reg, copy_dest_dither_type) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_MASK) | (copy_dest_dither_type << RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_RED(rb_copy_dest_info_reg, copy_mask_write_red) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_MASK) | (copy_mask_write_red << RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_GREEN(rb_copy_dest_info_reg, copy_mask_write_green) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_MASK) | (copy_mask_write_green << RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_BLUE(rb_copy_dest_info_reg, copy_mask_write_blue) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_MASK) | (copy_mask_write_blue << RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SHIFT) +#define RB_COPY_DEST_INFO_SET_COPY_MASK_WRITE_ALPHA(rb_copy_dest_info_reg, copy_mask_write_alpha) \ + rb_copy_dest_info_reg = (rb_copy_dest_info_reg & ~RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_MASK) | (copy_mask_write_alpha << RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_dest_info_t { + unsigned int copy_dest_endian : RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE; + unsigned int copy_dest_linear : RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE; + unsigned int copy_dest_format : RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE; + unsigned int copy_dest_swap : RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE; + unsigned int copy_dest_dither_mode : RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE; + unsigned int copy_dest_dither_type : RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE; + unsigned int copy_mask_write_red : RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE; + unsigned int copy_mask_write_green : RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE; + unsigned int copy_mask_write_blue : RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE; + unsigned int copy_mask_write_alpha : RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE; + unsigned int : 14; + } rb_copy_dest_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_dest_info_t { + unsigned int : 14; + unsigned int copy_mask_write_alpha : RB_COPY_DEST_INFO_COPY_MASK_WRITE_ALPHA_SIZE; + unsigned int copy_mask_write_blue : RB_COPY_DEST_INFO_COPY_MASK_WRITE_BLUE_SIZE; + unsigned int copy_mask_write_green : RB_COPY_DEST_INFO_COPY_MASK_WRITE_GREEN_SIZE; + unsigned int copy_mask_write_red : RB_COPY_DEST_INFO_COPY_MASK_WRITE_RED_SIZE; + unsigned int copy_dest_dither_type : RB_COPY_DEST_INFO_COPY_DEST_DITHER_TYPE_SIZE; + unsigned int copy_dest_dither_mode : RB_COPY_DEST_INFO_COPY_DEST_DITHER_MODE_SIZE; + unsigned int copy_dest_swap : RB_COPY_DEST_INFO_COPY_DEST_SWAP_SIZE; + unsigned int copy_dest_format : RB_COPY_DEST_INFO_COPY_DEST_FORMAT_SIZE; + unsigned int copy_dest_linear : RB_COPY_DEST_INFO_COPY_DEST_LINEAR_SIZE; + unsigned int copy_dest_endian : RB_COPY_DEST_INFO_COPY_DEST_ENDIAN_SIZE; + } rb_copy_dest_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_dest_info_t f; +} rb_copy_dest_info_u; + + +/* + * RB_COPY_DEST_PIXEL_OFFSET struct + */ + +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE 13 +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE 13 + +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT 0 +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT 13 + +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK 0x00001fff +#define RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK 0x03ffe000 + +#define RB_COPY_DEST_PIXEL_OFFSET_MASK \ + (RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK | \ + RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) + +#define RB_COPY_DEST_PIXEL_OFFSET(offset_x, offset_y) \ + ((offset_x << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT) | \ + (offset_y << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT)) + +#define RB_COPY_DEST_PIXEL_OFFSET_GET_OFFSET_X(rb_copy_dest_pixel_offset) \ + ((rb_copy_dest_pixel_offset & RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK) >> RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT) +#define RB_COPY_DEST_PIXEL_OFFSET_GET_OFFSET_Y(rb_copy_dest_pixel_offset) \ + ((rb_copy_dest_pixel_offset & RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) >> RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT) + +#define RB_COPY_DEST_PIXEL_OFFSET_SET_OFFSET_X(rb_copy_dest_pixel_offset_reg, offset_x) \ + rb_copy_dest_pixel_offset_reg = (rb_copy_dest_pixel_offset_reg & ~RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_MASK) | (offset_x << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SHIFT) +#define RB_COPY_DEST_PIXEL_OFFSET_SET_OFFSET_Y(rb_copy_dest_pixel_offset_reg, offset_y) \ + rb_copy_dest_pixel_offset_reg = (rb_copy_dest_pixel_offset_reg & ~RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_MASK) | (offset_y << RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_copy_dest_pixel_offset_t { + unsigned int offset_x : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE; + unsigned int offset_y : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE; + unsigned int : 6; + } rb_copy_dest_pixel_offset_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_copy_dest_pixel_offset_t { + unsigned int : 6; + unsigned int offset_y : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_Y_SIZE; + unsigned int offset_x : RB_COPY_DEST_PIXEL_OFFSET_OFFSET_X_SIZE; + } rb_copy_dest_pixel_offset_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_copy_dest_pixel_offset_t f; +} rb_copy_dest_pixel_offset_u; + + +/* + * RB_DEPTH_CLEAR struct + */ + +#define RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE 32 + +#define RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT 0 + +#define RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK 0xffffffff + +#define RB_DEPTH_CLEAR_MASK \ + (RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) + +#define RB_DEPTH_CLEAR(depth_clear) \ + ((depth_clear << RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT)) + +#define RB_DEPTH_CLEAR_GET_DEPTH_CLEAR(rb_depth_clear) \ + ((rb_depth_clear & RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) >> RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT) + +#define RB_DEPTH_CLEAR_SET_DEPTH_CLEAR(rb_depth_clear_reg, depth_clear) \ + rb_depth_clear_reg = (rb_depth_clear_reg & ~RB_DEPTH_CLEAR_DEPTH_CLEAR_MASK) | (depth_clear << RB_DEPTH_CLEAR_DEPTH_CLEAR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_depth_clear_t { + unsigned int depth_clear : RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE; + } rb_depth_clear_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_depth_clear_t { + unsigned int depth_clear : RB_DEPTH_CLEAR_DEPTH_CLEAR_SIZE; + } rb_depth_clear_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_depth_clear_t f; +} rb_depth_clear_u; + + +/* + * RB_SAMPLE_COUNT_CTL struct + */ + +#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE 1 +#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE 1 + +#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT 0 +#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT 1 + +#define RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK 0x00000001 +#define RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK 0x00000002 + +#define RB_SAMPLE_COUNT_CTL_MASK \ + (RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK | \ + RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) + +#define RB_SAMPLE_COUNT_CTL(reset_sample_count, copy_sample_count) \ + ((reset_sample_count << RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT) | \ + (copy_sample_count << RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT)) + +#define RB_SAMPLE_COUNT_CTL_GET_RESET_SAMPLE_COUNT(rb_sample_count_ctl) \ + ((rb_sample_count_ctl & RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK) >> RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT) +#define RB_SAMPLE_COUNT_CTL_GET_COPY_SAMPLE_COUNT(rb_sample_count_ctl) \ + ((rb_sample_count_ctl & RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) >> RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT) + +#define RB_SAMPLE_COUNT_CTL_SET_RESET_SAMPLE_COUNT(rb_sample_count_ctl_reg, reset_sample_count) \ + rb_sample_count_ctl_reg = (rb_sample_count_ctl_reg & ~RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_MASK) | (reset_sample_count << RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SHIFT) +#define RB_SAMPLE_COUNT_CTL_SET_COPY_SAMPLE_COUNT(rb_sample_count_ctl_reg, copy_sample_count) \ + rb_sample_count_ctl_reg = (rb_sample_count_ctl_reg & ~RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_MASK) | (copy_sample_count << RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_sample_count_ctl_t { + unsigned int reset_sample_count : RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE; + unsigned int copy_sample_count : RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE; + unsigned int : 30; + } rb_sample_count_ctl_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_sample_count_ctl_t { + unsigned int : 30; + unsigned int copy_sample_count : RB_SAMPLE_COUNT_CTL_COPY_SAMPLE_COUNT_SIZE; + unsigned int reset_sample_count : RB_SAMPLE_COUNT_CTL_RESET_SAMPLE_COUNT_SIZE; + } rb_sample_count_ctl_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_sample_count_ctl_t f; +} rb_sample_count_ctl_u; + + +/* + * RB_SAMPLE_COUNT_ADDR struct + */ + +#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE 32 + +#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT 0 + +#define RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK 0xffffffff + +#define RB_SAMPLE_COUNT_ADDR_MASK \ + (RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) + +#define RB_SAMPLE_COUNT_ADDR(sample_count_addr) \ + ((sample_count_addr << RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT)) + +#define RB_SAMPLE_COUNT_ADDR_GET_SAMPLE_COUNT_ADDR(rb_sample_count_addr) \ + ((rb_sample_count_addr & RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) >> RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT) + +#define RB_SAMPLE_COUNT_ADDR_SET_SAMPLE_COUNT_ADDR(rb_sample_count_addr_reg, sample_count_addr) \ + rb_sample_count_addr_reg = (rb_sample_count_addr_reg & ~RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_MASK) | (sample_count_addr << RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_sample_count_addr_t { + unsigned int sample_count_addr : RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE; + } rb_sample_count_addr_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_sample_count_addr_t { + unsigned int sample_count_addr : RB_SAMPLE_COUNT_ADDR_SAMPLE_COUNT_ADDR_SIZE; + } rb_sample_count_addr_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_sample_count_addr_t f; +} rb_sample_count_addr_u; + + +/* + * RB_BC_CONTROL struct + */ + +#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE 1 +#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE 2 +#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE 1 +#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE 1 +#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE 1 +#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE 1 +#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE 1 +#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE 5 +#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE 1 +#define RB_BC_CONTROL_CRC_MODE_SIZE 1 +#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE 1 +#define RB_BC_CONTROL_DISABLE_ACCUM_SIZE 1 +#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE 4 +#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE 1 +#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE 4 +#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE 2 +#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE 1 +#define RB_BC_CONTROL_CRC_SYSTEM_SIZE 1 +#define RB_BC_CONTROL_RESERVED6_SIZE 1 + +#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT 0 +#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT 1 +#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT 3 +#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT 4 +#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT 5 +#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT 6 +#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT 7 +#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT 8 +#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT 14 +#define RB_BC_CONTROL_CRC_MODE_SHIFT 15 +#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT 16 +#define RB_BC_CONTROL_DISABLE_ACCUM_SHIFT 17 +#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT 18 +#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT 22 +#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT 23 +#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT 27 +#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT 29 +#define RB_BC_CONTROL_CRC_SYSTEM_SHIFT 30 +#define RB_BC_CONTROL_RESERVED6_SHIFT 31 + +#define RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK 0x00000001 +#define RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK 0x00000006 +#define RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK 0x00000008 +#define RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK 0x00000010 +#define RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK 0x00000020 +#define RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK 0x00000040 +#define RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK 0x00000080 +#define RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK 0x00001f00 +#define RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK 0x00004000 +#define RB_BC_CONTROL_CRC_MODE_MASK 0x00008000 +#define RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK 0x00010000 +#define RB_BC_CONTROL_DISABLE_ACCUM_MASK 0x00020000 +#define RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK 0x003c0000 +#define RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK 0x00400000 +#define RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK 0x07800000 +#define RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK 0x18000000 +#define RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK 0x20000000 +#define RB_BC_CONTROL_CRC_SYSTEM_MASK 0x40000000 +#define RB_BC_CONTROL_RESERVED6_MASK 0x80000000 + +#define RB_BC_CONTROL_MASK \ + (RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK | \ + RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK | \ + RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK | \ + RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK | \ + RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK | \ + RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK | \ + RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK | \ + RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK | \ + RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK | \ + RB_BC_CONTROL_CRC_MODE_MASK | \ + RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK | \ + RB_BC_CONTROL_DISABLE_ACCUM_MASK | \ + RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK | \ + RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK | \ + RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK | \ + RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK | \ + RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK | \ + RB_BC_CONTROL_CRC_SYSTEM_MASK | \ + RB_BC_CONTROL_RESERVED6_MASK) + +#define RB_BC_CONTROL(accum_linear_mode_enable, accum_timeout_select, disable_edram_cam, disable_ez_fast_context_switch, disable_ez_null_zcmd_drop, disable_lz_null_zcmd_drop, enable_az_throttle, az_throttle_count, enable_crc_update, crc_mode, disable_sample_counters, disable_accum, accum_alloc_mask, linear_performance_enable, accum_data_fifo_limit, mem_export_timeout_select, mem_export_linear_mode_enable, crc_system, reserved6) \ + ((accum_linear_mode_enable << RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT) | \ + (accum_timeout_select << RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT) | \ + (disable_edram_cam << RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT) | \ + (disable_ez_fast_context_switch << RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT) | \ + (disable_ez_null_zcmd_drop << RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT) | \ + (disable_lz_null_zcmd_drop << RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT) | \ + (enable_az_throttle << RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT) | \ + (az_throttle_count << RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT) | \ + (enable_crc_update << RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT) | \ + (crc_mode << RB_BC_CONTROL_CRC_MODE_SHIFT) | \ + (disable_sample_counters << RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT) | \ + (disable_accum << RB_BC_CONTROL_DISABLE_ACCUM_SHIFT) | \ + (accum_alloc_mask << RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT) | \ + (linear_performance_enable << RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT) | \ + (accum_data_fifo_limit << RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT) | \ + (mem_export_timeout_select << RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT) | \ + (mem_export_linear_mode_enable << RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT) | \ + (crc_system << RB_BC_CONTROL_CRC_SYSTEM_SHIFT) | \ + (reserved6 << RB_BC_CONTROL_RESERVED6_SHIFT)) + +#define RB_BC_CONTROL_GET_ACCUM_LINEAR_MODE_ENABLE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK) >> RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT) +#define RB_BC_CONTROL_GET_ACCUM_TIMEOUT_SELECT(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK) >> RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_EDRAM_CAM(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK) >> RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_EZ_FAST_CONTEXT_SWITCH(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK) >> RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_EZ_NULL_ZCMD_DROP(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK) >> RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_LZ_NULL_ZCMD_DROP(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK) >> RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT) +#define RB_BC_CONTROL_GET_ENABLE_AZ_THROTTLE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK) >> RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT) +#define RB_BC_CONTROL_GET_AZ_THROTTLE_COUNT(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK) >> RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT) +#define RB_BC_CONTROL_GET_ENABLE_CRC_UPDATE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK) >> RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT) +#define RB_BC_CONTROL_GET_CRC_MODE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_CRC_MODE_MASK) >> RB_BC_CONTROL_CRC_MODE_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_SAMPLE_COUNTERS(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK) >> RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT) +#define RB_BC_CONTROL_GET_DISABLE_ACCUM(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_DISABLE_ACCUM_MASK) >> RB_BC_CONTROL_DISABLE_ACCUM_SHIFT) +#define RB_BC_CONTROL_GET_ACCUM_ALLOC_MASK(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK) >> RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT) +#define RB_BC_CONTROL_GET_LINEAR_PERFORMANCE_ENABLE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK) >> RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT) +#define RB_BC_CONTROL_GET_ACCUM_DATA_FIFO_LIMIT(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK) >> RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT) +#define RB_BC_CONTROL_GET_MEM_EXPORT_TIMEOUT_SELECT(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK) >> RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT) +#define RB_BC_CONTROL_GET_MEM_EXPORT_LINEAR_MODE_ENABLE(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK) >> RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT) +#define RB_BC_CONTROL_GET_CRC_SYSTEM(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_CRC_SYSTEM_MASK) >> RB_BC_CONTROL_CRC_SYSTEM_SHIFT) +#define RB_BC_CONTROL_GET_RESERVED6(rb_bc_control) \ + ((rb_bc_control & RB_BC_CONTROL_RESERVED6_MASK) >> RB_BC_CONTROL_RESERVED6_SHIFT) + +#define RB_BC_CONTROL_SET_ACCUM_LINEAR_MODE_ENABLE(rb_bc_control_reg, accum_linear_mode_enable) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_MASK) | (accum_linear_mode_enable << RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SHIFT) +#define RB_BC_CONTROL_SET_ACCUM_TIMEOUT_SELECT(rb_bc_control_reg, accum_timeout_select) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_MASK) | (accum_timeout_select << RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_EDRAM_CAM(rb_bc_control_reg, disable_edram_cam) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EDRAM_CAM_MASK) | (disable_edram_cam << RB_BC_CONTROL_DISABLE_EDRAM_CAM_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_EZ_FAST_CONTEXT_SWITCH(rb_bc_control_reg, disable_ez_fast_context_switch) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_MASK) | (disable_ez_fast_context_switch << RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_EZ_NULL_ZCMD_DROP(rb_bc_control_reg, disable_ez_null_zcmd_drop) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_MASK) | (disable_ez_null_zcmd_drop << RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_LZ_NULL_ZCMD_DROP(rb_bc_control_reg, disable_lz_null_zcmd_drop) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_MASK) | (disable_lz_null_zcmd_drop << RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SHIFT) +#define RB_BC_CONTROL_SET_ENABLE_AZ_THROTTLE(rb_bc_control_reg, enable_az_throttle) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ENABLE_AZ_THROTTLE_MASK) | (enable_az_throttle << RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SHIFT) +#define RB_BC_CONTROL_SET_AZ_THROTTLE_COUNT(rb_bc_control_reg, az_throttle_count) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_AZ_THROTTLE_COUNT_MASK) | (az_throttle_count << RB_BC_CONTROL_AZ_THROTTLE_COUNT_SHIFT) +#define RB_BC_CONTROL_SET_ENABLE_CRC_UPDATE(rb_bc_control_reg, enable_crc_update) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ENABLE_CRC_UPDATE_MASK) | (enable_crc_update << RB_BC_CONTROL_ENABLE_CRC_UPDATE_SHIFT) +#define RB_BC_CONTROL_SET_CRC_MODE(rb_bc_control_reg, crc_mode) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_CRC_MODE_MASK) | (crc_mode << RB_BC_CONTROL_CRC_MODE_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_SAMPLE_COUNTERS(rb_bc_control_reg, disable_sample_counters) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_MASK) | (disable_sample_counters << RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SHIFT) +#define RB_BC_CONTROL_SET_DISABLE_ACCUM(rb_bc_control_reg, disable_accum) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_DISABLE_ACCUM_MASK) | (disable_accum << RB_BC_CONTROL_DISABLE_ACCUM_SHIFT) +#define RB_BC_CONTROL_SET_ACCUM_ALLOC_MASK(rb_bc_control_reg, accum_alloc_mask) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_ALLOC_MASK_MASK) | (accum_alloc_mask << RB_BC_CONTROL_ACCUM_ALLOC_MASK_SHIFT) +#define RB_BC_CONTROL_SET_LINEAR_PERFORMANCE_ENABLE(rb_bc_control_reg, linear_performance_enable) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_MASK) | (linear_performance_enable << RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SHIFT) +#define RB_BC_CONTROL_SET_ACCUM_DATA_FIFO_LIMIT(rb_bc_control_reg, accum_data_fifo_limit) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_MASK) | (accum_data_fifo_limit << RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SHIFT) +#define RB_BC_CONTROL_SET_MEM_EXPORT_TIMEOUT_SELECT(rb_bc_control_reg, mem_export_timeout_select) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_MASK) | (mem_export_timeout_select << RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SHIFT) +#define RB_BC_CONTROL_SET_MEM_EXPORT_LINEAR_MODE_ENABLE(rb_bc_control_reg, mem_export_linear_mode_enable) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_MASK) | (mem_export_linear_mode_enable << RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SHIFT) +#define RB_BC_CONTROL_SET_CRC_SYSTEM(rb_bc_control_reg, crc_system) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_CRC_SYSTEM_MASK) | (crc_system << RB_BC_CONTROL_CRC_SYSTEM_SHIFT) +#define RB_BC_CONTROL_SET_RESERVED6(rb_bc_control_reg, reserved6) \ + rb_bc_control_reg = (rb_bc_control_reg & ~RB_BC_CONTROL_RESERVED6_MASK) | (reserved6 << RB_BC_CONTROL_RESERVED6_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_bc_control_t { + unsigned int accum_linear_mode_enable : RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE; + unsigned int accum_timeout_select : RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE; + unsigned int disable_edram_cam : RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE; + unsigned int disable_ez_fast_context_switch : RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE; + unsigned int disable_ez_null_zcmd_drop : RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE; + unsigned int disable_lz_null_zcmd_drop : RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE; + unsigned int enable_az_throttle : RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE; + unsigned int az_throttle_count : RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE; + unsigned int : 1; + unsigned int enable_crc_update : RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE; + unsigned int crc_mode : RB_BC_CONTROL_CRC_MODE_SIZE; + unsigned int disable_sample_counters : RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE; + unsigned int disable_accum : RB_BC_CONTROL_DISABLE_ACCUM_SIZE; + unsigned int accum_alloc_mask : RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE; + unsigned int linear_performance_enable : RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE; + unsigned int accum_data_fifo_limit : RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE; + unsigned int mem_export_timeout_select : RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE; + unsigned int mem_export_linear_mode_enable : RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE; + unsigned int crc_system : RB_BC_CONTROL_CRC_SYSTEM_SIZE; + unsigned int reserved6 : RB_BC_CONTROL_RESERVED6_SIZE; + } rb_bc_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_bc_control_t { + unsigned int reserved6 : RB_BC_CONTROL_RESERVED6_SIZE; + unsigned int crc_system : RB_BC_CONTROL_CRC_SYSTEM_SIZE; + unsigned int mem_export_linear_mode_enable : RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE_SIZE; + unsigned int mem_export_timeout_select : RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT_SIZE; + unsigned int accum_data_fifo_limit : RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT_SIZE; + unsigned int linear_performance_enable : RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE_SIZE; + unsigned int accum_alloc_mask : RB_BC_CONTROL_ACCUM_ALLOC_MASK_SIZE; + unsigned int disable_accum : RB_BC_CONTROL_DISABLE_ACCUM_SIZE; + unsigned int disable_sample_counters : RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS_SIZE; + unsigned int crc_mode : RB_BC_CONTROL_CRC_MODE_SIZE; + unsigned int enable_crc_update : RB_BC_CONTROL_ENABLE_CRC_UPDATE_SIZE; + unsigned int : 1; + unsigned int az_throttle_count : RB_BC_CONTROL_AZ_THROTTLE_COUNT_SIZE; + unsigned int enable_az_throttle : RB_BC_CONTROL_ENABLE_AZ_THROTTLE_SIZE; + unsigned int disable_lz_null_zcmd_drop : RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP_SIZE; + unsigned int disable_ez_null_zcmd_drop : RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP_SIZE; + unsigned int disable_ez_fast_context_switch : RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH_SIZE; + unsigned int disable_edram_cam : RB_BC_CONTROL_DISABLE_EDRAM_CAM_SIZE; + unsigned int accum_timeout_select : RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT_SIZE; + unsigned int accum_linear_mode_enable : RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE_SIZE; + } rb_bc_control_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_bc_control_t f; +} rb_bc_control_u; + + +/* + * RB_EDRAM_INFO struct + */ + +#define RB_EDRAM_INFO_EDRAM_SIZE_SIZE 4 +#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE 2 +#define RB_EDRAM_INFO_EDRAM_RANGE_SIZE 18 + +#define RB_EDRAM_INFO_EDRAM_SIZE_SHIFT 0 +#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT 4 +#define RB_EDRAM_INFO_EDRAM_RANGE_SHIFT 14 + +#define RB_EDRAM_INFO_EDRAM_SIZE_MASK 0x0000000f +#define RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK 0x00000030 +#define RB_EDRAM_INFO_EDRAM_RANGE_MASK 0xffffc000 + +#define RB_EDRAM_INFO_MASK \ + (RB_EDRAM_INFO_EDRAM_SIZE_MASK | \ + RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK | \ + RB_EDRAM_INFO_EDRAM_RANGE_MASK) + +#define RB_EDRAM_INFO(edram_size, edram_mapping_mode, edram_range) \ + ((edram_size << RB_EDRAM_INFO_EDRAM_SIZE_SHIFT) | \ + (edram_mapping_mode << RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT) | \ + (edram_range << RB_EDRAM_INFO_EDRAM_RANGE_SHIFT)) + +#define RB_EDRAM_INFO_GET_EDRAM_SIZE(rb_edram_info) \ + ((rb_edram_info & RB_EDRAM_INFO_EDRAM_SIZE_MASK) >> RB_EDRAM_INFO_EDRAM_SIZE_SHIFT) +#define RB_EDRAM_INFO_GET_EDRAM_MAPPING_MODE(rb_edram_info) \ + ((rb_edram_info & RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK) >> RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT) +#define RB_EDRAM_INFO_GET_EDRAM_RANGE(rb_edram_info) \ + ((rb_edram_info & RB_EDRAM_INFO_EDRAM_RANGE_MASK) >> RB_EDRAM_INFO_EDRAM_RANGE_SHIFT) + +#define RB_EDRAM_INFO_SET_EDRAM_SIZE(rb_edram_info_reg, edram_size) \ + rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_SIZE_MASK) | (edram_size << RB_EDRAM_INFO_EDRAM_SIZE_SHIFT) +#define RB_EDRAM_INFO_SET_EDRAM_MAPPING_MODE(rb_edram_info_reg, edram_mapping_mode) \ + rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_MAPPING_MODE_MASK) | (edram_mapping_mode << RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SHIFT) +#define RB_EDRAM_INFO_SET_EDRAM_RANGE(rb_edram_info_reg, edram_range) \ + rb_edram_info_reg = (rb_edram_info_reg & ~RB_EDRAM_INFO_EDRAM_RANGE_MASK) | (edram_range << RB_EDRAM_INFO_EDRAM_RANGE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_edram_info_t { + unsigned int edram_size : RB_EDRAM_INFO_EDRAM_SIZE_SIZE; + unsigned int edram_mapping_mode : RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE; + unsigned int : 8; + unsigned int edram_range : RB_EDRAM_INFO_EDRAM_RANGE_SIZE; + } rb_edram_info_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_edram_info_t { + unsigned int edram_range : RB_EDRAM_INFO_EDRAM_RANGE_SIZE; + unsigned int : 8; + unsigned int edram_mapping_mode : RB_EDRAM_INFO_EDRAM_MAPPING_MODE_SIZE; + unsigned int edram_size : RB_EDRAM_INFO_EDRAM_SIZE_SIZE; + } rb_edram_info_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_edram_info_t f; +} rb_edram_info_u; + + +/* + * RB_CRC_RD_PORT struct + */ + +#define RB_CRC_RD_PORT_CRC_DATA_SIZE 32 + +#define RB_CRC_RD_PORT_CRC_DATA_SHIFT 0 + +#define RB_CRC_RD_PORT_CRC_DATA_MASK 0xffffffff + +#define RB_CRC_RD_PORT_MASK \ + (RB_CRC_RD_PORT_CRC_DATA_MASK) + +#define RB_CRC_RD_PORT(crc_data) \ + ((crc_data << RB_CRC_RD_PORT_CRC_DATA_SHIFT)) + +#define RB_CRC_RD_PORT_GET_CRC_DATA(rb_crc_rd_port) \ + ((rb_crc_rd_port & RB_CRC_RD_PORT_CRC_DATA_MASK) >> RB_CRC_RD_PORT_CRC_DATA_SHIFT) + +#define RB_CRC_RD_PORT_SET_CRC_DATA(rb_crc_rd_port_reg, crc_data) \ + rb_crc_rd_port_reg = (rb_crc_rd_port_reg & ~RB_CRC_RD_PORT_CRC_DATA_MASK) | (crc_data << RB_CRC_RD_PORT_CRC_DATA_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_crc_rd_port_t { + unsigned int crc_data : RB_CRC_RD_PORT_CRC_DATA_SIZE; + } rb_crc_rd_port_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_crc_rd_port_t { + unsigned int crc_data : RB_CRC_RD_PORT_CRC_DATA_SIZE; + } rb_crc_rd_port_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_crc_rd_port_t f; +} rb_crc_rd_port_u; + + +/* + * RB_CRC_CONTROL struct + */ + +#define RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE 1 + +#define RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT 0 + +#define RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK 0x00000001 + +#define RB_CRC_CONTROL_MASK \ + (RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) + +#define RB_CRC_CONTROL(crc_rd_advance) \ + ((crc_rd_advance << RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT)) + +#define RB_CRC_CONTROL_GET_CRC_RD_ADVANCE(rb_crc_control) \ + ((rb_crc_control & RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) >> RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT) + +#define RB_CRC_CONTROL_SET_CRC_RD_ADVANCE(rb_crc_control_reg, crc_rd_advance) \ + rb_crc_control_reg = (rb_crc_control_reg & ~RB_CRC_CONTROL_CRC_RD_ADVANCE_MASK) | (crc_rd_advance << RB_CRC_CONTROL_CRC_RD_ADVANCE_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_crc_control_t { + unsigned int crc_rd_advance : RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE; + unsigned int : 31; + } rb_crc_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_crc_control_t { + unsigned int : 31; + unsigned int crc_rd_advance : RB_CRC_CONTROL_CRC_RD_ADVANCE_SIZE; + } rb_crc_control_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_crc_control_t f; +} rb_crc_control_u; + + +/* + * RB_CRC_MASK struct + */ + +#define RB_CRC_MASK_CRC_MASK_SIZE 32 + +#define RB_CRC_MASK_CRC_MASK_SHIFT 0 + +#define RB_CRC_MASK_CRC_MASK_MASK 0xffffffff + +#define RB_CRC_MASK_MASK \ + (RB_CRC_MASK_CRC_MASK_MASK) + +#define RB_CRC_MASK(crc_mask) \ + ((crc_mask << RB_CRC_MASK_CRC_MASK_SHIFT)) + +#define RB_CRC_MASK_GET_CRC_MASK(rb_crc_mask) \ + ((rb_crc_mask & RB_CRC_MASK_CRC_MASK_MASK) >> RB_CRC_MASK_CRC_MASK_SHIFT) + +#define RB_CRC_MASK_SET_CRC_MASK(rb_crc_mask_reg, crc_mask) \ + rb_crc_mask_reg = (rb_crc_mask_reg & ~RB_CRC_MASK_CRC_MASK_MASK) | (crc_mask << RB_CRC_MASK_CRC_MASK_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_crc_mask_t { + unsigned int crc_mask : RB_CRC_MASK_CRC_MASK_SIZE; + } rb_crc_mask_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_crc_mask_t { + unsigned int crc_mask : RB_CRC_MASK_CRC_MASK_SIZE; + } rb_crc_mask_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_crc_mask_t f; +} rb_crc_mask_u; + + +/* + * RB_PERFCOUNTER0_SELECT struct + */ + +#define RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE 8 + +#define RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT 0 + +#define RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK 0x000000ff + +#define RB_PERFCOUNTER0_SELECT_MASK \ + (RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) + +#define RB_PERFCOUNTER0_SELECT(perf_sel) \ + ((perf_sel << RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT)) + +#define RB_PERFCOUNTER0_SELECT_GET_PERF_SEL(rb_perfcounter0_select) \ + ((rb_perfcounter0_select & RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) >> RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#define RB_PERFCOUNTER0_SELECT_SET_PERF_SEL(rb_perfcounter0_select_reg, perf_sel) \ + rb_perfcounter0_select_reg = (rb_perfcounter0_select_reg & ~RB_PERFCOUNTER0_SELECT_PERF_SEL_MASK) | (perf_sel << RB_PERFCOUNTER0_SELECT_PERF_SEL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_perfcounter0_select_t { + unsigned int perf_sel : RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + unsigned int : 24; + } rb_perfcounter0_select_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_perfcounter0_select_t { + unsigned int : 24; + unsigned int perf_sel : RB_PERFCOUNTER0_SELECT_PERF_SEL_SIZE; + } rb_perfcounter0_select_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_perfcounter0_select_t f; +} rb_perfcounter0_select_u; + + +/* + * RB_PERFCOUNTER0_LOW struct + */ + +#define RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE 32 + +#define RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT 0 + +#define RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK 0xffffffff + +#define RB_PERFCOUNTER0_LOW_MASK \ + (RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) + +#define RB_PERFCOUNTER0_LOW(perf_count) \ + ((perf_count << RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT)) + +#define RB_PERFCOUNTER0_LOW_GET_PERF_COUNT(rb_perfcounter0_low) \ + ((rb_perfcounter0_low & RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) >> RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#define RB_PERFCOUNTER0_LOW_SET_PERF_COUNT(rb_perfcounter0_low_reg, perf_count) \ + rb_perfcounter0_low_reg = (rb_perfcounter0_low_reg & ~RB_PERFCOUNTER0_LOW_PERF_COUNT_MASK) | (perf_count << RB_PERFCOUNTER0_LOW_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_perfcounter0_low_t { + unsigned int perf_count : RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } rb_perfcounter0_low_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_perfcounter0_low_t { + unsigned int perf_count : RB_PERFCOUNTER0_LOW_PERF_COUNT_SIZE; + } rb_perfcounter0_low_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_perfcounter0_low_t f; +} rb_perfcounter0_low_u; + + +/* + * RB_PERFCOUNTER0_HI struct + */ + +#define RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE 16 + +#define RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT 0 + +#define RB_PERFCOUNTER0_HI_PERF_COUNT_MASK 0x0000ffff + +#define RB_PERFCOUNTER0_HI_MASK \ + (RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) + +#define RB_PERFCOUNTER0_HI(perf_count) \ + ((perf_count << RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT)) + +#define RB_PERFCOUNTER0_HI_GET_PERF_COUNT(rb_perfcounter0_hi) \ + ((rb_perfcounter0_hi & RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) >> RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#define RB_PERFCOUNTER0_HI_SET_PERF_COUNT(rb_perfcounter0_hi_reg, perf_count) \ + rb_perfcounter0_hi_reg = (rb_perfcounter0_hi_reg & ~RB_PERFCOUNTER0_HI_PERF_COUNT_MASK) | (perf_count << RB_PERFCOUNTER0_HI_PERF_COUNT_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_perfcounter0_hi_t { + unsigned int perf_count : RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + unsigned int : 16; + } rb_perfcounter0_hi_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_perfcounter0_hi_t { + unsigned int : 16; + unsigned int perf_count : RB_PERFCOUNTER0_HI_PERF_COUNT_SIZE; + } rb_perfcounter0_hi_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_perfcounter0_hi_t f; +} rb_perfcounter0_hi_u; + + +/* + * RB_TOTAL_SAMPLES struct + */ + +#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE 32 + +#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT 0 + +#define RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK 0xffffffff + +#define RB_TOTAL_SAMPLES_MASK \ + (RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) + +#define RB_TOTAL_SAMPLES(total_samples) \ + ((total_samples << RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT)) + +#define RB_TOTAL_SAMPLES_GET_TOTAL_SAMPLES(rb_total_samples) \ + ((rb_total_samples & RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) >> RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT) + +#define RB_TOTAL_SAMPLES_SET_TOTAL_SAMPLES(rb_total_samples_reg, total_samples) \ + rb_total_samples_reg = (rb_total_samples_reg & ~RB_TOTAL_SAMPLES_TOTAL_SAMPLES_MASK) | (total_samples << RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_total_samples_t { + unsigned int total_samples : RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE; + } rb_total_samples_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_total_samples_t { + unsigned int total_samples : RB_TOTAL_SAMPLES_TOTAL_SAMPLES_SIZE; + } rb_total_samples_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_total_samples_t f; +} rb_total_samples_u; + + +/* + * RB_ZPASS_SAMPLES struct + */ + +#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE 32 + +#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT 0 + +#define RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK 0xffffffff + +#define RB_ZPASS_SAMPLES_MASK \ + (RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) + +#define RB_ZPASS_SAMPLES(zpass_samples) \ + ((zpass_samples << RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT)) + +#define RB_ZPASS_SAMPLES_GET_ZPASS_SAMPLES(rb_zpass_samples) \ + ((rb_zpass_samples & RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) >> RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT) + +#define RB_ZPASS_SAMPLES_SET_ZPASS_SAMPLES(rb_zpass_samples_reg, zpass_samples) \ + rb_zpass_samples_reg = (rb_zpass_samples_reg & ~RB_ZPASS_SAMPLES_ZPASS_SAMPLES_MASK) | (zpass_samples << RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_zpass_samples_t { + unsigned int zpass_samples : RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE; + } rb_zpass_samples_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_zpass_samples_t { + unsigned int zpass_samples : RB_ZPASS_SAMPLES_ZPASS_SAMPLES_SIZE; + } rb_zpass_samples_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_zpass_samples_t f; +} rb_zpass_samples_u; + + +/* + * RB_ZFAIL_SAMPLES struct + */ + +#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE 32 + +#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT 0 + +#define RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK 0xffffffff + +#define RB_ZFAIL_SAMPLES_MASK \ + (RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) + +#define RB_ZFAIL_SAMPLES(zfail_samples) \ + ((zfail_samples << RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT)) + +#define RB_ZFAIL_SAMPLES_GET_ZFAIL_SAMPLES(rb_zfail_samples) \ + ((rb_zfail_samples & RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) >> RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT) + +#define RB_ZFAIL_SAMPLES_SET_ZFAIL_SAMPLES(rb_zfail_samples_reg, zfail_samples) \ + rb_zfail_samples_reg = (rb_zfail_samples_reg & ~RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_MASK) | (zfail_samples << RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_zfail_samples_t { + unsigned int zfail_samples : RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE; + } rb_zfail_samples_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_zfail_samples_t { + unsigned int zfail_samples : RB_ZFAIL_SAMPLES_ZFAIL_SAMPLES_SIZE; + } rb_zfail_samples_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_zfail_samples_t f; +} rb_zfail_samples_u; + + +/* + * RB_SFAIL_SAMPLES struct + */ + +#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE 32 + +#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT 0 + +#define RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK 0xffffffff + +#define RB_SFAIL_SAMPLES_MASK \ + (RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) + +#define RB_SFAIL_SAMPLES(sfail_samples) \ + ((sfail_samples << RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT)) + +#define RB_SFAIL_SAMPLES_GET_SFAIL_SAMPLES(rb_sfail_samples) \ + ((rb_sfail_samples & RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) >> RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT) + +#define RB_SFAIL_SAMPLES_SET_SFAIL_SAMPLES(rb_sfail_samples_reg, sfail_samples) \ + rb_sfail_samples_reg = (rb_sfail_samples_reg & ~RB_SFAIL_SAMPLES_SFAIL_SAMPLES_MASK) | (sfail_samples << RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_sfail_samples_t { + unsigned int sfail_samples : RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE; + } rb_sfail_samples_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_sfail_samples_t { + unsigned int sfail_samples : RB_SFAIL_SAMPLES_SFAIL_SAMPLES_SIZE; + } rb_sfail_samples_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_sfail_samples_t f; +} rb_sfail_samples_u; + + +/* + * RB_DEBUG_0 struct + */ + +#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_Z1_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_Z0_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_C1_FULL_SIZE 1 +#define RB_DEBUG_0_RDREQ_C0_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_Z1_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_Z0_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_C1_FULL_SIZE 1 +#define RB_DEBUG_0_WRREQ_C0_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE 1 +#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE 1 +#define RB_DEBUG_0_C_SX_LAT_FULL_SIZE 1 +#define RB_DEBUG_0_C_SX_CMD_FULL_SIZE 1 +#define RB_DEBUG_0_C_EZ_TILE_FULL_SIZE 1 +#define RB_DEBUG_0_C_REQ_FULL_SIZE 1 +#define RB_DEBUG_0_C_MASK_FULL_SIZE 1 +#define RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE 1 + +#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT 0 +#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT 1 +#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT 2 +#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT 3 +#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT 4 +#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT 5 +#define RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT 6 +#define RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT 7 +#define RB_DEBUG_0_RDREQ_C1_FULL_SHIFT 8 +#define RB_DEBUG_0_RDREQ_C0_FULL_SHIFT 9 +#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT 10 +#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT 11 +#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT 12 +#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT 13 +#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT 14 +#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT 15 +#define RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT 16 +#define RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT 17 +#define RB_DEBUG_0_WRREQ_C1_FULL_SHIFT 18 +#define RB_DEBUG_0_WRREQ_C0_FULL_SHIFT 19 +#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT 20 +#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT 21 +#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT 22 +#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT 23 +#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT 24 +#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT 25 +#define RB_DEBUG_0_C_SX_LAT_FULL_SHIFT 26 +#define RB_DEBUG_0_C_SX_CMD_FULL_SHIFT 27 +#define RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT 28 +#define RB_DEBUG_0_C_REQ_FULL_SHIFT 29 +#define RB_DEBUG_0_C_MASK_FULL_SHIFT 30 +#define RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT 31 + +#define RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK 0x00000001 +#define RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK 0x00000002 +#define RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK 0x00000004 +#define RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK 0x00000008 +#define RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK 0x00000010 +#define RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK 0x00000020 +#define RB_DEBUG_0_RDREQ_Z1_FULL_MASK 0x00000040 +#define RB_DEBUG_0_RDREQ_Z0_FULL_MASK 0x00000080 +#define RB_DEBUG_0_RDREQ_C1_FULL_MASK 0x00000100 +#define RB_DEBUG_0_RDREQ_C0_FULL_MASK 0x00000200 +#define RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK 0x00000400 +#define RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK 0x00000800 +#define RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK 0x00001000 +#define RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK 0x00002000 +#define RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK 0x00004000 +#define RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK 0x00008000 +#define RB_DEBUG_0_WRREQ_Z1_FULL_MASK 0x00010000 +#define RB_DEBUG_0_WRREQ_Z0_FULL_MASK 0x00020000 +#define RB_DEBUG_0_WRREQ_C1_FULL_MASK 0x00040000 +#define RB_DEBUG_0_WRREQ_C0_FULL_MASK 0x00080000 +#define RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK 0x00100000 +#define RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK 0x00200000 +#define RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK 0x00400000 +#define RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK 0x00800000 +#define RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK 0x01000000 +#define RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK 0x02000000 +#define RB_DEBUG_0_C_SX_LAT_FULL_MASK 0x04000000 +#define RB_DEBUG_0_C_SX_CMD_FULL_MASK 0x08000000 +#define RB_DEBUG_0_C_EZ_TILE_FULL_MASK 0x10000000 +#define RB_DEBUG_0_C_REQ_FULL_MASK 0x20000000 +#define RB_DEBUG_0_C_MASK_FULL_MASK 0x40000000 +#define RB_DEBUG_0_EZ_INFSAMP_FULL_MASK 0x80000000 + +#define RB_DEBUG_0_MASK \ + (RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK | \ + RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK | \ + RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK | \ + RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK | \ + RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK | \ + RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK | \ + RB_DEBUG_0_RDREQ_Z1_FULL_MASK | \ + RB_DEBUG_0_RDREQ_Z0_FULL_MASK | \ + RB_DEBUG_0_RDREQ_C1_FULL_MASK | \ + RB_DEBUG_0_RDREQ_C0_FULL_MASK | \ + RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK | \ + RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK | \ + RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK | \ + RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK | \ + RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK | \ + RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK | \ + RB_DEBUG_0_WRREQ_Z1_FULL_MASK | \ + RB_DEBUG_0_WRREQ_Z0_FULL_MASK | \ + RB_DEBUG_0_WRREQ_C1_FULL_MASK | \ + RB_DEBUG_0_WRREQ_C0_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK | \ + RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK | \ + RB_DEBUG_0_C_SX_LAT_FULL_MASK | \ + RB_DEBUG_0_C_SX_CMD_FULL_MASK | \ + RB_DEBUG_0_C_EZ_TILE_FULL_MASK | \ + RB_DEBUG_0_C_REQ_FULL_MASK | \ + RB_DEBUG_0_C_MASK_FULL_MASK | \ + RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) + +#define RB_DEBUG_0(rdreq_ctl_z1_pre_full, rdreq_ctl_z0_pre_full, rdreq_ctl_c1_pre_full, rdreq_ctl_c0_pre_full, rdreq_e1_ordering_full, rdreq_e0_ordering_full, rdreq_z1_full, rdreq_z0_full, rdreq_c1_full, rdreq_c0_full, wrreq_e1_macro_hi_full, wrreq_e1_macro_lo_full, wrreq_e0_macro_hi_full, wrreq_e0_macro_lo_full, wrreq_c_we_hi_full, wrreq_c_we_lo_full, wrreq_z1_full, wrreq_z0_full, wrreq_c1_full, wrreq_c0_full, cmdfifo_z1_hold_full, cmdfifo_z0_hold_full, cmdfifo_c1_hold_full, cmdfifo_c0_hold_full, cmdfifo_z_ordering_full, cmdfifo_c_ordering_full, c_sx_lat_full, c_sx_cmd_full, c_ez_tile_full, c_req_full, c_mask_full, ez_infsamp_full) \ + ((rdreq_ctl_z1_pre_full << RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT) | \ + (rdreq_ctl_z0_pre_full << RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT) | \ + (rdreq_ctl_c1_pre_full << RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT) | \ + (rdreq_ctl_c0_pre_full << RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT) | \ + (rdreq_e1_ordering_full << RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT) | \ + (rdreq_e0_ordering_full << RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT) | \ + (rdreq_z1_full << RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT) | \ + (rdreq_z0_full << RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT) | \ + (rdreq_c1_full << RB_DEBUG_0_RDREQ_C1_FULL_SHIFT) | \ + (rdreq_c0_full << RB_DEBUG_0_RDREQ_C0_FULL_SHIFT) | \ + (wrreq_e1_macro_hi_full << RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT) | \ + (wrreq_e1_macro_lo_full << RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT) | \ + (wrreq_e0_macro_hi_full << RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT) | \ + (wrreq_e0_macro_lo_full << RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT) | \ + (wrreq_c_we_hi_full << RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT) | \ + (wrreq_c_we_lo_full << RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT) | \ + (wrreq_z1_full << RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT) | \ + (wrreq_z0_full << RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT) | \ + (wrreq_c1_full << RB_DEBUG_0_WRREQ_C1_FULL_SHIFT) | \ + (wrreq_c0_full << RB_DEBUG_0_WRREQ_C0_FULL_SHIFT) | \ + (cmdfifo_z1_hold_full << RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT) | \ + (cmdfifo_z0_hold_full << RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT) | \ + (cmdfifo_c1_hold_full << RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT) | \ + (cmdfifo_c0_hold_full << RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT) | \ + (cmdfifo_z_ordering_full << RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT) | \ + (cmdfifo_c_ordering_full << RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT) | \ + (c_sx_lat_full << RB_DEBUG_0_C_SX_LAT_FULL_SHIFT) | \ + (c_sx_cmd_full << RB_DEBUG_0_C_SX_CMD_FULL_SHIFT) | \ + (c_ez_tile_full << RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT) | \ + (c_req_full << RB_DEBUG_0_C_REQ_FULL_SHIFT) | \ + (c_mask_full << RB_DEBUG_0_C_MASK_FULL_SHIFT) | \ + (ez_infsamp_full << RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT)) + +#define RB_DEBUG_0_GET_RDREQ_CTL_Z1_PRE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_CTL_Z0_PRE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_CTL_C1_PRE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_CTL_C0_PRE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK) >> RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_E1_ORDERING_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK) >> RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_E0_ORDERING_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK) >> RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_Z1_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_Z1_FULL_MASK) >> RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_Z0_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_Z0_FULL_MASK) >> RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_C1_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_C1_FULL_MASK) >> RB_DEBUG_0_RDREQ_C1_FULL_SHIFT) +#define RB_DEBUG_0_GET_RDREQ_C0_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_RDREQ_C0_FULL_MASK) >> RB_DEBUG_0_RDREQ_C0_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_E1_MACRO_HI_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_E1_MACRO_LO_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_E0_MACRO_HI_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_E0_MACRO_LO_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_C_WE_HI_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK) >> RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_C_WE_LO_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK) >> RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_Z1_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_Z1_FULL_MASK) >> RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_Z0_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_Z0_FULL_MASK) >> RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_C1_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_C1_FULL_MASK) >> RB_DEBUG_0_WRREQ_C1_FULL_SHIFT) +#define RB_DEBUG_0_GET_WRREQ_C0_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_WRREQ_C0_FULL_MASK) >> RB_DEBUG_0_WRREQ_C0_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_Z1_HOLD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_Z0_HOLD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_C1_HOLD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_C0_HOLD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_Z_ORDERING_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_GET_CMDFIFO_C_ORDERING_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK) >> RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_SX_LAT_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_SX_LAT_FULL_MASK) >> RB_DEBUG_0_C_SX_LAT_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_SX_CMD_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_SX_CMD_FULL_MASK) >> RB_DEBUG_0_C_SX_CMD_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_EZ_TILE_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_EZ_TILE_FULL_MASK) >> RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_REQ_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_REQ_FULL_MASK) >> RB_DEBUG_0_C_REQ_FULL_SHIFT) +#define RB_DEBUG_0_GET_C_MASK_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_C_MASK_FULL_MASK) >> RB_DEBUG_0_C_MASK_FULL_SHIFT) +#define RB_DEBUG_0_GET_EZ_INFSAMP_FULL(rb_debug_0) \ + ((rb_debug_0 & RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) >> RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT) + +#define RB_DEBUG_0_SET_RDREQ_CTL_Z1_PRE_FULL(rb_debug_0_reg, rdreq_ctl_z1_pre_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_MASK) | (rdreq_ctl_z1_pre_full << RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_CTL_Z0_PRE_FULL(rb_debug_0_reg, rdreq_ctl_z0_pre_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_MASK) | (rdreq_ctl_z0_pre_full << RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_CTL_C1_PRE_FULL(rb_debug_0_reg, rdreq_ctl_c1_pre_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_MASK) | (rdreq_ctl_c1_pre_full << RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_CTL_C0_PRE_FULL(rb_debug_0_reg, rdreq_ctl_c0_pre_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_MASK) | (rdreq_ctl_c0_pre_full << RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_E1_ORDERING_FULL(rb_debug_0_reg, rdreq_e1_ordering_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_MASK) | (rdreq_e1_ordering_full << RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_E0_ORDERING_FULL(rb_debug_0_reg, rdreq_e0_ordering_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_MASK) | (rdreq_e0_ordering_full << RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_Z1_FULL(rb_debug_0_reg, rdreq_z1_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_Z1_FULL_MASK) | (rdreq_z1_full << RB_DEBUG_0_RDREQ_Z1_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_Z0_FULL(rb_debug_0_reg, rdreq_z0_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_Z0_FULL_MASK) | (rdreq_z0_full << RB_DEBUG_0_RDREQ_Z0_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_C1_FULL(rb_debug_0_reg, rdreq_c1_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_C1_FULL_MASK) | (rdreq_c1_full << RB_DEBUG_0_RDREQ_C1_FULL_SHIFT) +#define RB_DEBUG_0_SET_RDREQ_C0_FULL(rb_debug_0_reg, rdreq_c0_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_RDREQ_C0_FULL_MASK) | (rdreq_c0_full << RB_DEBUG_0_RDREQ_C0_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_E1_MACRO_HI_FULL(rb_debug_0_reg, wrreq_e1_macro_hi_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_MASK) | (wrreq_e1_macro_hi_full << RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_E1_MACRO_LO_FULL(rb_debug_0_reg, wrreq_e1_macro_lo_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_MASK) | (wrreq_e1_macro_lo_full << RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_E0_MACRO_HI_FULL(rb_debug_0_reg, wrreq_e0_macro_hi_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_MASK) | (wrreq_e0_macro_hi_full << RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_E0_MACRO_LO_FULL(rb_debug_0_reg, wrreq_e0_macro_lo_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_MASK) | (wrreq_e0_macro_lo_full << RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_C_WE_HI_FULL(rb_debug_0_reg, wrreq_c_we_hi_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C_WE_HI_FULL_MASK) | (wrreq_c_we_hi_full << RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_C_WE_LO_FULL(rb_debug_0_reg, wrreq_c_we_lo_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C_WE_LO_FULL_MASK) | (wrreq_c_we_lo_full << RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_Z1_FULL(rb_debug_0_reg, wrreq_z1_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_Z1_FULL_MASK) | (wrreq_z1_full << RB_DEBUG_0_WRREQ_Z1_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_Z0_FULL(rb_debug_0_reg, wrreq_z0_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_Z0_FULL_MASK) | (wrreq_z0_full << RB_DEBUG_0_WRREQ_Z0_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_C1_FULL(rb_debug_0_reg, wrreq_c1_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C1_FULL_MASK) | (wrreq_c1_full << RB_DEBUG_0_WRREQ_C1_FULL_SHIFT) +#define RB_DEBUG_0_SET_WRREQ_C0_FULL(rb_debug_0_reg, wrreq_c0_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_WRREQ_C0_FULL_MASK) | (wrreq_c0_full << RB_DEBUG_0_WRREQ_C0_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_Z1_HOLD_FULL(rb_debug_0_reg, cmdfifo_z1_hold_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_MASK) | (cmdfifo_z1_hold_full << RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_Z0_HOLD_FULL(rb_debug_0_reg, cmdfifo_z0_hold_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_MASK) | (cmdfifo_z0_hold_full << RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_C1_HOLD_FULL(rb_debug_0_reg, cmdfifo_c1_hold_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_MASK) | (cmdfifo_c1_hold_full << RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_C0_HOLD_FULL(rb_debug_0_reg, cmdfifo_c0_hold_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_MASK) | (cmdfifo_c0_hold_full << RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_Z_ORDERING_FULL(rb_debug_0_reg, cmdfifo_z_ordering_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_MASK) | (cmdfifo_z_ordering_full << RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_SET_CMDFIFO_C_ORDERING_FULL(rb_debug_0_reg, cmdfifo_c_ordering_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_MASK) | (cmdfifo_c_ordering_full << RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_SX_LAT_FULL(rb_debug_0_reg, c_sx_lat_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_SX_LAT_FULL_MASK) | (c_sx_lat_full << RB_DEBUG_0_C_SX_LAT_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_SX_CMD_FULL(rb_debug_0_reg, c_sx_cmd_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_SX_CMD_FULL_MASK) | (c_sx_cmd_full << RB_DEBUG_0_C_SX_CMD_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_EZ_TILE_FULL(rb_debug_0_reg, c_ez_tile_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_EZ_TILE_FULL_MASK) | (c_ez_tile_full << RB_DEBUG_0_C_EZ_TILE_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_REQ_FULL(rb_debug_0_reg, c_req_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_REQ_FULL_MASK) | (c_req_full << RB_DEBUG_0_C_REQ_FULL_SHIFT) +#define RB_DEBUG_0_SET_C_MASK_FULL(rb_debug_0_reg, c_mask_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_C_MASK_FULL_MASK) | (c_mask_full << RB_DEBUG_0_C_MASK_FULL_SHIFT) +#define RB_DEBUG_0_SET_EZ_INFSAMP_FULL(rb_debug_0_reg, ez_infsamp_full) \ + rb_debug_0_reg = (rb_debug_0_reg & ~RB_DEBUG_0_EZ_INFSAMP_FULL_MASK) | (ez_infsamp_full << RB_DEBUG_0_EZ_INFSAMP_FULL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_0_t { + unsigned int rdreq_ctl_z1_pre_full : RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE; + unsigned int rdreq_ctl_z0_pre_full : RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE; + unsigned int rdreq_ctl_c1_pre_full : RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE; + unsigned int rdreq_ctl_c0_pre_full : RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE; + unsigned int rdreq_e1_ordering_full : RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE; + unsigned int rdreq_e0_ordering_full : RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE; + unsigned int rdreq_z1_full : RB_DEBUG_0_RDREQ_Z1_FULL_SIZE; + unsigned int rdreq_z0_full : RB_DEBUG_0_RDREQ_Z0_FULL_SIZE; + unsigned int rdreq_c1_full : RB_DEBUG_0_RDREQ_C1_FULL_SIZE; + unsigned int rdreq_c0_full : RB_DEBUG_0_RDREQ_C0_FULL_SIZE; + unsigned int wrreq_e1_macro_hi_full : RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE; + unsigned int wrreq_e1_macro_lo_full : RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE; + unsigned int wrreq_e0_macro_hi_full : RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE; + unsigned int wrreq_e0_macro_lo_full : RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE; + unsigned int wrreq_c_we_hi_full : RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE; + unsigned int wrreq_c_we_lo_full : RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE; + unsigned int wrreq_z1_full : RB_DEBUG_0_WRREQ_Z1_FULL_SIZE; + unsigned int wrreq_z0_full : RB_DEBUG_0_WRREQ_Z0_FULL_SIZE; + unsigned int wrreq_c1_full : RB_DEBUG_0_WRREQ_C1_FULL_SIZE; + unsigned int wrreq_c0_full : RB_DEBUG_0_WRREQ_C0_FULL_SIZE; + unsigned int cmdfifo_z1_hold_full : RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE; + unsigned int cmdfifo_z0_hold_full : RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE; + unsigned int cmdfifo_c1_hold_full : RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE; + unsigned int cmdfifo_c0_hold_full : RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE; + unsigned int cmdfifo_z_ordering_full : RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE; + unsigned int cmdfifo_c_ordering_full : RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE; + unsigned int c_sx_lat_full : RB_DEBUG_0_C_SX_LAT_FULL_SIZE; + unsigned int c_sx_cmd_full : RB_DEBUG_0_C_SX_CMD_FULL_SIZE; + unsigned int c_ez_tile_full : RB_DEBUG_0_C_EZ_TILE_FULL_SIZE; + unsigned int c_req_full : RB_DEBUG_0_C_REQ_FULL_SIZE; + unsigned int c_mask_full : RB_DEBUG_0_C_MASK_FULL_SIZE; + unsigned int ez_infsamp_full : RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE; + } rb_debug_0_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_0_t { + unsigned int ez_infsamp_full : RB_DEBUG_0_EZ_INFSAMP_FULL_SIZE; + unsigned int c_mask_full : RB_DEBUG_0_C_MASK_FULL_SIZE; + unsigned int c_req_full : RB_DEBUG_0_C_REQ_FULL_SIZE; + unsigned int c_ez_tile_full : RB_DEBUG_0_C_EZ_TILE_FULL_SIZE; + unsigned int c_sx_cmd_full : RB_DEBUG_0_C_SX_CMD_FULL_SIZE; + unsigned int c_sx_lat_full : RB_DEBUG_0_C_SX_LAT_FULL_SIZE; + unsigned int cmdfifo_c_ordering_full : RB_DEBUG_0_CMDFIFO_C_ORDERING_FULL_SIZE; + unsigned int cmdfifo_z_ordering_full : RB_DEBUG_0_CMDFIFO_Z_ORDERING_FULL_SIZE; + unsigned int cmdfifo_c0_hold_full : RB_DEBUG_0_CMDFIFO_C0_HOLD_FULL_SIZE; + unsigned int cmdfifo_c1_hold_full : RB_DEBUG_0_CMDFIFO_C1_HOLD_FULL_SIZE; + unsigned int cmdfifo_z0_hold_full : RB_DEBUG_0_CMDFIFO_Z0_HOLD_FULL_SIZE; + unsigned int cmdfifo_z1_hold_full : RB_DEBUG_0_CMDFIFO_Z1_HOLD_FULL_SIZE; + unsigned int wrreq_c0_full : RB_DEBUG_0_WRREQ_C0_FULL_SIZE; + unsigned int wrreq_c1_full : RB_DEBUG_0_WRREQ_C1_FULL_SIZE; + unsigned int wrreq_z0_full : RB_DEBUG_0_WRREQ_Z0_FULL_SIZE; + unsigned int wrreq_z1_full : RB_DEBUG_0_WRREQ_Z1_FULL_SIZE; + unsigned int wrreq_c_we_lo_full : RB_DEBUG_0_WRREQ_C_WE_LO_FULL_SIZE; + unsigned int wrreq_c_we_hi_full : RB_DEBUG_0_WRREQ_C_WE_HI_FULL_SIZE; + unsigned int wrreq_e0_macro_lo_full : RB_DEBUG_0_WRREQ_E0_MACRO_LO_FULL_SIZE; + unsigned int wrreq_e0_macro_hi_full : RB_DEBUG_0_WRREQ_E0_MACRO_HI_FULL_SIZE; + unsigned int wrreq_e1_macro_lo_full : RB_DEBUG_0_WRREQ_E1_MACRO_LO_FULL_SIZE; + unsigned int wrreq_e1_macro_hi_full : RB_DEBUG_0_WRREQ_E1_MACRO_HI_FULL_SIZE; + unsigned int rdreq_c0_full : RB_DEBUG_0_RDREQ_C0_FULL_SIZE; + unsigned int rdreq_c1_full : RB_DEBUG_0_RDREQ_C1_FULL_SIZE; + unsigned int rdreq_z0_full : RB_DEBUG_0_RDREQ_Z0_FULL_SIZE; + unsigned int rdreq_z1_full : RB_DEBUG_0_RDREQ_Z1_FULL_SIZE; + unsigned int rdreq_e0_ordering_full : RB_DEBUG_0_RDREQ_E0_ORDERING_FULL_SIZE; + unsigned int rdreq_e1_ordering_full : RB_DEBUG_0_RDREQ_E1_ORDERING_FULL_SIZE; + unsigned int rdreq_ctl_c0_pre_full : RB_DEBUG_0_RDREQ_CTL_C0_PRE_FULL_SIZE; + unsigned int rdreq_ctl_c1_pre_full : RB_DEBUG_0_RDREQ_CTL_C1_PRE_FULL_SIZE; + unsigned int rdreq_ctl_z0_pre_full : RB_DEBUG_0_RDREQ_CTL_Z0_PRE_FULL_SIZE; + unsigned int rdreq_ctl_z1_pre_full : RB_DEBUG_0_RDREQ_CTL_Z1_PRE_FULL_SIZE; + } rb_debug_0_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_0_t f; +} rb_debug_0_u; + + +/* + * RB_DEBUG_1 struct + */ + +#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE 1 +#define RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE 1 +#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE 1 +#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_REQ_EMPTY_SIZE 1 +#define RB_DEBUG_1_C_MASK_EMPTY_SIZE 1 +#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE 1 + +#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT 0 +#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT 1 +#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT 2 +#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT 3 +#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT 4 +#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT 5 +#define RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT 6 +#define RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT 7 +#define RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT 8 +#define RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT 9 +#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT 10 +#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT 11 +#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT 12 +#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT 13 +#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT 14 +#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT 15 +#define RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT 16 +#define RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT 17 +#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT 18 +#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT 19 +#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT 20 +#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT 21 +#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT 22 +#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT 23 +#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT 24 +#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT 25 +#define RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT 26 +#define RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT 27 +#define RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT 28 +#define RB_DEBUG_1_C_REQ_EMPTY_SHIFT 29 +#define RB_DEBUG_1_C_MASK_EMPTY_SHIFT 30 +#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT 31 + +#define RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK 0x00000001 +#define RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK 0x00000002 +#define RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK 0x00000004 +#define RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK 0x00000008 +#define RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK 0x00000010 +#define RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK 0x00000020 +#define RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK 0x00000040 +#define RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK 0x00000080 +#define RB_DEBUG_1_RDREQ_C1_EMPTY_MASK 0x00000100 +#define RB_DEBUG_1_RDREQ_C0_EMPTY_MASK 0x00000200 +#define RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK 0x00000400 +#define RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK 0x00000800 +#define RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK 0x00001000 +#define RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK 0x00002000 +#define RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK 0x00004000 +#define RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK 0x00008000 +#define RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK 0x00010000 +#define RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK 0x00020000 +#define RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK 0x00040000 +#define RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK 0x00080000 +#define RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK 0x00100000 +#define RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK 0x00200000 +#define RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK 0x00400000 +#define RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK 0x00800000 +#define RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK 0x01000000 +#define RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK 0x02000000 +#define RB_DEBUG_1_C_SX_LAT_EMPTY_MASK 0x04000000 +#define RB_DEBUG_1_C_SX_CMD_EMPTY_MASK 0x08000000 +#define RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK 0x10000000 +#define RB_DEBUG_1_C_REQ_EMPTY_MASK 0x20000000 +#define RB_DEBUG_1_C_MASK_EMPTY_MASK 0x40000000 +#define RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK 0x80000000 + +#define RB_DEBUG_1_MASK \ + (RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_C1_EMPTY_MASK | \ + RB_DEBUG_1_RDREQ_C0_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK | \ + RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK | \ + RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK | \ + RB_DEBUG_1_C_SX_LAT_EMPTY_MASK | \ + RB_DEBUG_1_C_SX_CMD_EMPTY_MASK | \ + RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK | \ + RB_DEBUG_1_C_REQ_EMPTY_MASK | \ + RB_DEBUG_1_C_MASK_EMPTY_MASK | \ + RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) + +#define RB_DEBUG_1(rdreq_z1_cmd_empty, rdreq_z0_cmd_empty, rdreq_c1_cmd_empty, rdreq_c0_cmd_empty, rdreq_e1_ordering_empty, rdreq_e0_ordering_empty, rdreq_z1_empty, rdreq_z0_empty, rdreq_c1_empty, rdreq_c0_empty, wrreq_e1_macro_hi_empty, wrreq_e1_macro_lo_empty, wrreq_e0_macro_hi_empty, wrreq_e0_macro_lo_empty, wrreq_c_we_hi_empty, wrreq_c_we_lo_empty, wrreq_z1_empty, wrreq_z0_empty, wrreq_c1_pre_empty, wrreq_c0_pre_empty, cmdfifo_z1_hold_empty, cmdfifo_z0_hold_empty, cmdfifo_c1_hold_empty, cmdfifo_c0_hold_empty, cmdfifo_z_ordering_empty, cmdfifo_c_ordering_empty, c_sx_lat_empty, c_sx_cmd_empty, c_ez_tile_empty, c_req_empty, c_mask_empty, ez_infsamp_empty) \ + ((rdreq_z1_cmd_empty << RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT) | \ + (rdreq_z0_cmd_empty << RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT) | \ + (rdreq_c1_cmd_empty << RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT) | \ + (rdreq_c0_cmd_empty << RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT) | \ + (rdreq_e1_ordering_empty << RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT) | \ + (rdreq_e0_ordering_empty << RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT) | \ + (rdreq_z1_empty << RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT) | \ + (rdreq_z0_empty << RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT) | \ + (rdreq_c1_empty << RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT) | \ + (rdreq_c0_empty << RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT) | \ + (wrreq_e1_macro_hi_empty << RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT) | \ + (wrreq_e1_macro_lo_empty << RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT) | \ + (wrreq_e0_macro_hi_empty << RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT) | \ + (wrreq_e0_macro_lo_empty << RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT) | \ + (wrreq_c_we_hi_empty << RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT) | \ + (wrreq_c_we_lo_empty << RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT) | \ + (wrreq_z1_empty << RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT) | \ + (wrreq_z0_empty << RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT) | \ + (wrreq_c1_pre_empty << RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT) | \ + (wrreq_c0_pre_empty << RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT) | \ + (cmdfifo_z1_hold_empty << RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT) | \ + (cmdfifo_z0_hold_empty << RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT) | \ + (cmdfifo_c1_hold_empty << RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT) | \ + (cmdfifo_c0_hold_empty << RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT) | \ + (cmdfifo_z_ordering_empty << RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT) | \ + (cmdfifo_c_ordering_empty << RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT) | \ + (c_sx_lat_empty << RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT) | \ + (c_sx_cmd_empty << RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT) | \ + (c_ez_tile_empty << RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT) | \ + (c_req_empty << RB_DEBUG_1_C_REQ_EMPTY_SHIFT) | \ + (c_mask_empty << RB_DEBUG_1_C_MASK_EMPTY_SHIFT) | \ + (ez_infsamp_empty << RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT)) + +#define RB_DEBUG_1_GET_RDREQ_Z1_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_Z0_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_C1_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_C0_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_E1_ORDERING_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_E0_ORDERING_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_Z1_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_Z0_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_C1_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_C1_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_RDREQ_C0_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_RDREQ_C0_EMPTY_MASK) >> RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_E1_MACRO_HI_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_E1_MACRO_LO_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_E0_MACRO_HI_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_E0_MACRO_LO_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_C_WE_HI_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_C_WE_LO_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_Z1_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_Z0_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_C1_PRE_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_WRREQ_C0_PRE_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK) >> RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_Z1_HOLD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_Z0_HOLD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_C1_HOLD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_C0_HOLD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_Z_ORDERING_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_CMDFIFO_C_ORDERING_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK) >> RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_SX_LAT_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_SX_LAT_EMPTY_MASK) >> RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_SX_CMD_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_SX_CMD_EMPTY_MASK) >> RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_EZ_TILE_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK) >> RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_REQ_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_REQ_EMPTY_MASK) >> RB_DEBUG_1_C_REQ_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_C_MASK_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_C_MASK_EMPTY_MASK) >> RB_DEBUG_1_C_MASK_EMPTY_SHIFT) +#define RB_DEBUG_1_GET_EZ_INFSAMP_EMPTY(rb_debug_1) \ + ((rb_debug_1 & RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) >> RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT) + +#define RB_DEBUG_1_SET_RDREQ_Z1_CMD_EMPTY(rb_debug_1_reg, rdreq_z1_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_MASK) | (rdreq_z1_cmd_empty << RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_Z0_CMD_EMPTY(rb_debug_1_reg, rdreq_z0_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_MASK) | (rdreq_z0_cmd_empty << RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_C1_CMD_EMPTY(rb_debug_1_reg, rdreq_c1_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_MASK) | (rdreq_c1_cmd_empty << RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_C0_CMD_EMPTY(rb_debug_1_reg, rdreq_c0_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_MASK) | (rdreq_c0_cmd_empty << RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_E1_ORDERING_EMPTY(rb_debug_1_reg, rdreq_e1_ordering_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_MASK) | (rdreq_e1_ordering_empty << RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_E0_ORDERING_EMPTY(rb_debug_1_reg, rdreq_e0_ordering_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_MASK) | (rdreq_e0_ordering_empty << RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_Z1_EMPTY(rb_debug_1_reg, rdreq_z1_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z1_EMPTY_MASK) | (rdreq_z1_empty << RB_DEBUG_1_RDREQ_Z1_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_Z0_EMPTY(rb_debug_1_reg, rdreq_z0_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_Z0_EMPTY_MASK) | (rdreq_z0_empty << RB_DEBUG_1_RDREQ_Z0_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_C1_EMPTY(rb_debug_1_reg, rdreq_c1_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C1_EMPTY_MASK) | (rdreq_c1_empty << RB_DEBUG_1_RDREQ_C1_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_RDREQ_C0_EMPTY(rb_debug_1_reg, rdreq_c0_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_RDREQ_C0_EMPTY_MASK) | (rdreq_c0_empty << RB_DEBUG_1_RDREQ_C0_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_E1_MACRO_HI_EMPTY(rb_debug_1_reg, wrreq_e1_macro_hi_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_MASK) | (wrreq_e1_macro_hi_empty << RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_E1_MACRO_LO_EMPTY(rb_debug_1_reg, wrreq_e1_macro_lo_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_MASK) | (wrreq_e1_macro_lo_empty << RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_E0_MACRO_HI_EMPTY(rb_debug_1_reg, wrreq_e0_macro_hi_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_MASK) | (wrreq_e0_macro_hi_empty << RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_E0_MACRO_LO_EMPTY(rb_debug_1_reg, wrreq_e0_macro_lo_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_MASK) | (wrreq_e0_macro_lo_empty << RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_C_WE_HI_EMPTY(rb_debug_1_reg, wrreq_c_we_hi_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_MASK) | (wrreq_c_we_hi_empty << RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_C_WE_LO_EMPTY(rb_debug_1_reg, wrreq_c_we_lo_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_MASK) | (wrreq_c_we_lo_empty << RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_Z1_EMPTY(rb_debug_1_reg, wrreq_z1_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_Z1_EMPTY_MASK) | (wrreq_z1_empty << RB_DEBUG_1_WRREQ_Z1_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_Z0_EMPTY(rb_debug_1_reg, wrreq_z0_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_Z0_EMPTY_MASK) | (wrreq_z0_empty << RB_DEBUG_1_WRREQ_Z0_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_C1_PRE_EMPTY(rb_debug_1_reg, wrreq_c1_pre_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_MASK) | (wrreq_c1_pre_empty << RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_WRREQ_C0_PRE_EMPTY(rb_debug_1_reg, wrreq_c0_pre_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_MASK) | (wrreq_c0_pre_empty << RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_Z1_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_z1_hold_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_MASK) | (cmdfifo_z1_hold_empty << RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_Z0_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_z0_hold_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_MASK) | (cmdfifo_z0_hold_empty << RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_C1_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_c1_hold_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_MASK) | (cmdfifo_c1_hold_empty << RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_C0_HOLD_EMPTY(rb_debug_1_reg, cmdfifo_c0_hold_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_MASK) | (cmdfifo_c0_hold_empty << RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_Z_ORDERING_EMPTY(rb_debug_1_reg, cmdfifo_z_ordering_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_MASK) | (cmdfifo_z_ordering_empty << RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_CMDFIFO_C_ORDERING_EMPTY(rb_debug_1_reg, cmdfifo_c_ordering_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_MASK) | (cmdfifo_c_ordering_empty << RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_SX_LAT_EMPTY(rb_debug_1_reg, c_sx_lat_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_SX_LAT_EMPTY_MASK) | (c_sx_lat_empty << RB_DEBUG_1_C_SX_LAT_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_SX_CMD_EMPTY(rb_debug_1_reg, c_sx_cmd_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_SX_CMD_EMPTY_MASK) | (c_sx_cmd_empty << RB_DEBUG_1_C_SX_CMD_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_EZ_TILE_EMPTY(rb_debug_1_reg, c_ez_tile_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_EZ_TILE_EMPTY_MASK) | (c_ez_tile_empty << RB_DEBUG_1_C_EZ_TILE_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_REQ_EMPTY(rb_debug_1_reg, c_req_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_REQ_EMPTY_MASK) | (c_req_empty << RB_DEBUG_1_C_REQ_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_C_MASK_EMPTY(rb_debug_1_reg, c_mask_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_C_MASK_EMPTY_MASK) | (c_mask_empty << RB_DEBUG_1_C_MASK_EMPTY_SHIFT) +#define RB_DEBUG_1_SET_EZ_INFSAMP_EMPTY(rb_debug_1_reg, ez_infsamp_empty) \ + rb_debug_1_reg = (rb_debug_1_reg & ~RB_DEBUG_1_EZ_INFSAMP_EMPTY_MASK) | (ez_infsamp_empty << RB_DEBUG_1_EZ_INFSAMP_EMPTY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_1_t { + unsigned int rdreq_z1_cmd_empty : RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE; + unsigned int rdreq_z0_cmd_empty : RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE; + unsigned int rdreq_c1_cmd_empty : RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE; + unsigned int rdreq_c0_cmd_empty : RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE; + unsigned int rdreq_e1_ordering_empty : RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE; + unsigned int rdreq_e0_ordering_empty : RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE; + unsigned int rdreq_z1_empty : RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE; + unsigned int rdreq_z0_empty : RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE; + unsigned int rdreq_c1_empty : RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE; + unsigned int rdreq_c0_empty : RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE; + unsigned int wrreq_e1_macro_hi_empty : RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE; + unsigned int wrreq_e1_macro_lo_empty : RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE; + unsigned int wrreq_e0_macro_hi_empty : RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE; + unsigned int wrreq_e0_macro_lo_empty : RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE; + unsigned int wrreq_c_we_hi_empty : RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE; + unsigned int wrreq_c_we_lo_empty : RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE; + unsigned int wrreq_z1_empty : RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE; + unsigned int wrreq_z0_empty : RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE; + unsigned int wrreq_c1_pre_empty : RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE; + unsigned int wrreq_c0_pre_empty : RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE; + unsigned int cmdfifo_z1_hold_empty : RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_z0_hold_empty : RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_c1_hold_empty : RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_c0_hold_empty : RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_z_ordering_empty : RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE; + unsigned int cmdfifo_c_ordering_empty : RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE; + unsigned int c_sx_lat_empty : RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE; + unsigned int c_sx_cmd_empty : RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE; + unsigned int c_ez_tile_empty : RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE; + unsigned int c_req_empty : RB_DEBUG_1_C_REQ_EMPTY_SIZE; + unsigned int c_mask_empty : RB_DEBUG_1_C_MASK_EMPTY_SIZE; + unsigned int ez_infsamp_empty : RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE; + } rb_debug_1_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_1_t { + unsigned int ez_infsamp_empty : RB_DEBUG_1_EZ_INFSAMP_EMPTY_SIZE; + unsigned int c_mask_empty : RB_DEBUG_1_C_MASK_EMPTY_SIZE; + unsigned int c_req_empty : RB_DEBUG_1_C_REQ_EMPTY_SIZE; + unsigned int c_ez_tile_empty : RB_DEBUG_1_C_EZ_TILE_EMPTY_SIZE; + unsigned int c_sx_cmd_empty : RB_DEBUG_1_C_SX_CMD_EMPTY_SIZE; + unsigned int c_sx_lat_empty : RB_DEBUG_1_C_SX_LAT_EMPTY_SIZE; + unsigned int cmdfifo_c_ordering_empty : RB_DEBUG_1_CMDFIFO_C_ORDERING_EMPTY_SIZE; + unsigned int cmdfifo_z_ordering_empty : RB_DEBUG_1_CMDFIFO_Z_ORDERING_EMPTY_SIZE; + unsigned int cmdfifo_c0_hold_empty : RB_DEBUG_1_CMDFIFO_C0_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_c1_hold_empty : RB_DEBUG_1_CMDFIFO_C1_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_z0_hold_empty : RB_DEBUG_1_CMDFIFO_Z0_HOLD_EMPTY_SIZE; + unsigned int cmdfifo_z1_hold_empty : RB_DEBUG_1_CMDFIFO_Z1_HOLD_EMPTY_SIZE; + unsigned int wrreq_c0_pre_empty : RB_DEBUG_1_WRREQ_C0_PRE_EMPTY_SIZE; + unsigned int wrreq_c1_pre_empty : RB_DEBUG_1_WRREQ_C1_PRE_EMPTY_SIZE; + unsigned int wrreq_z0_empty : RB_DEBUG_1_WRREQ_Z0_EMPTY_SIZE; + unsigned int wrreq_z1_empty : RB_DEBUG_1_WRREQ_Z1_EMPTY_SIZE; + unsigned int wrreq_c_we_lo_empty : RB_DEBUG_1_WRREQ_C_WE_LO_EMPTY_SIZE; + unsigned int wrreq_c_we_hi_empty : RB_DEBUG_1_WRREQ_C_WE_HI_EMPTY_SIZE; + unsigned int wrreq_e0_macro_lo_empty : RB_DEBUG_1_WRREQ_E0_MACRO_LO_EMPTY_SIZE; + unsigned int wrreq_e0_macro_hi_empty : RB_DEBUG_1_WRREQ_E0_MACRO_HI_EMPTY_SIZE; + unsigned int wrreq_e1_macro_lo_empty : RB_DEBUG_1_WRREQ_E1_MACRO_LO_EMPTY_SIZE; + unsigned int wrreq_e1_macro_hi_empty : RB_DEBUG_1_WRREQ_E1_MACRO_HI_EMPTY_SIZE; + unsigned int rdreq_c0_empty : RB_DEBUG_1_RDREQ_C0_EMPTY_SIZE; + unsigned int rdreq_c1_empty : RB_DEBUG_1_RDREQ_C1_EMPTY_SIZE; + unsigned int rdreq_z0_empty : RB_DEBUG_1_RDREQ_Z0_EMPTY_SIZE; + unsigned int rdreq_z1_empty : RB_DEBUG_1_RDREQ_Z1_EMPTY_SIZE; + unsigned int rdreq_e0_ordering_empty : RB_DEBUG_1_RDREQ_E0_ORDERING_EMPTY_SIZE; + unsigned int rdreq_e1_ordering_empty : RB_DEBUG_1_RDREQ_E1_ORDERING_EMPTY_SIZE; + unsigned int rdreq_c0_cmd_empty : RB_DEBUG_1_RDREQ_C0_CMD_EMPTY_SIZE; + unsigned int rdreq_c1_cmd_empty : RB_DEBUG_1_RDREQ_C1_CMD_EMPTY_SIZE; + unsigned int rdreq_z0_cmd_empty : RB_DEBUG_1_RDREQ_Z0_CMD_EMPTY_SIZE; + unsigned int rdreq_z1_cmd_empty : RB_DEBUG_1_RDREQ_Z1_CMD_EMPTY_SIZE; + } rb_debug_1_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_1_t f; +} rb_debug_1_u; + + +/* + * RB_DEBUG_2 struct + */ + +#define RB_DEBUG_2_TILE_FIFO_COUNT_SIZE 4 +#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE 7 +#define RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE 1 +#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE 1 +#define RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE 1 +#define RB_DEBUG_2_EZ_INFTILE_FULL_SIZE 1 +#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE 1 +#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE 1 +#define RB_DEBUG_2_Z0_MASK_FULL_SIZE 1 +#define RB_DEBUG_2_Z1_MASK_FULL_SIZE 1 +#define RB_DEBUG_2_Z0_REQ_FULL_SIZE 1 +#define RB_DEBUG_2_Z1_REQ_FULL_SIZE 1 +#define RB_DEBUG_2_Z_SAMP_FULL_SIZE 1 +#define RB_DEBUG_2_Z_TILE_FULL_SIZE 1 +#define RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE 1 +#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE 1 +#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z0_MASK_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z1_MASK_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z0_REQ_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z1_REQ_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z_SAMP_EMPTY_SIZE 1 +#define RB_DEBUG_2_Z_TILE_EMPTY_SIZE 1 + +#define RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT 0 +#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT 4 +#define RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT 11 +#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT 12 +#define RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT 13 +#define RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT 14 +#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT 15 +#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT 16 +#define RB_DEBUG_2_Z0_MASK_FULL_SHIFT 17 +#define RB_DEBUG_2_Z1_MASK_FULL_SHIFT 18 +#define RB_DEBUG_2_Z0_REQ_FULL_SHIFT 19 +#define RB_DEBUG_2_Z1_REQ_FULL_SHIFT 20 +#define RB_DEBUG_2_Z_SAMP_FULL_SHIFT 21 +#define RB_DEBUG_2_Z_TILE_FULL_SHIFT 22 +#define RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT 23 +#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT 24 +#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT 25 +#define RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT 26 +#define RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT 27 +#define RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT 28 +#define RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT 29 +#define RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT 30 +#define RB_DEBUG_2_Z_TILE_EMPTY_SHIFT 31 + +#define RB_DEBUG_2_TILE_FIFO_COUNT_MASK 0x0000000f +#define RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK 0x000007f0 +#define RB_DEBUG_2_MEM_EXPORT_FLAG_MASK 0x00000800 +#define RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK 0x00001000 +#define RB_DEBUG_2_CURRENT_TILE_EVENT_MASK 0x00002000 +#define RB_DEBUG_2_EZ_INFTILE_FULL_MASK 0x00004000 +#define RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK 0x00008000 +#define RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK 0x00010000 +#define RB_DEBUG_2_Z0_MASK_FULL_MASK 0x00020000 +#define RB_DEBUG_2_Z1_MASK_FULL_MASK 0x00040000 +#define RB_DEBUG_2_Z0_REQ_FULL_MASK 0x00080000 +#define RB_DEBUG_2_Z1_REQ_FULL_MASK 0x00100000 +#define RB_DEBUG_2_Z_SAMP_FULL_MASK 0x00200000 +#define RB_DEBUG_2_Z_TILE_FULL_MASK 0x00400000 +#define RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK 0x00800000 +#define RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK 0x01000000 +#define RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK 0x02000000 +#define RB_DEBUG_2_Z0_MASK_EMPTY_MASK 0x04000000 +#define RB_DEBUG_2_Z1_MASK_EMPTY_MASK 0x08000000 +#define RB_DEBUG_2_Z0_REQ_EMPTY_MASK 0x10000000 +#define RB_DEBUG_2_Z1_REQ_EMPTY_MASK 0x20000000 +#define RB_DEBUG_2_Z_SAMP_EMPTY_MASK 0x40000000 +#define RB_DEBUG_2_Z_TILE_EMPTY_MASK 0x80000000 + +#define RB_DEBUG_2_MASK \ + (RB_DEBUG_2_TILE_FIFO_COUNT_MASK | \ + RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK | \ + RB_DEBUG_2_MEM_EXPORT_FLAG_MASK | \ + RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK | \ + RB_DEBUG_2_CURRENT_TILE_EVENT_MASK | \ + RB_DEBUG_2_EZ_INFTILE_FULL_MASK | \ + RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK | \ + RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK | \ + RB_DEBUG_2_Z0_MASK_FULL_MASK | \ + RB_DEBUG_2_Z1_MASK_FULL_MASK | \ + RB_DEBUG_2_Z0_REQ_FULL_MASK | \ + RB_DEBUG_2_Z1_REQ_FULL_MASK | \ + RB_DEBUG_2_Z_SAMP_FULL_MASK | \ + RB_DEBUG_2_Z_TILE_FULL_MASK | \ + RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK | \ + RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK | \ + RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK | \ + RB_DEBUG_2_Z0_MASK_EMPTY_MASK | \ + RB_DEBUG_2_Z1_MASK_EMPTY_MASK | \ + RB_DEBUG_2_Z0_REQ_EMPTY_MASK | \ + RB_DEBUG_2_Z1_REQ_EMPTY_MASK | \ + RB_DEBUG_2_Z_SAMP_EMPTY_MASK | \ + RB_DEBUG_2_Z_TILE_EMPTY_MASK) + +#define RB_DEBUG_2(tile_fifo_count, sx_lat_fifo_count, mem_export_flag, sysmem_blend_flag, current_tile_event, ez_inftile_full, ez_mask_lower_full, ez_mask_upper_full, z0_mask_full, z1_mask_full, z0_req_full, z1_req_full, z_samp_full, z_tile_full, ez_inftile_empty, ez_mask_lower_empty, ez_mask_upper_empty, z0_mask_empty, z1_mask_empty, z0_req_empty, z1_req_empty, z_samp_empty, z_tile_empty) \ + ((tile_fifo_count << RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT) | \ + (sx_lat_fifo_count << RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT) | \ + (mem_export_flag << RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT) | \ + (sysmem_blend_flag << RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT) | \ + (current_tile_event << RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT) | \ + (ez_inftile_full << RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT) | \ + (ez_mask_lower_full << RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT) | \ + (ez_mask_upper_full << RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT) | \ + (z0_mask_full << RB_DEBUG_2_Z0_MASK_FULL_SHIFT) | \ + (z1_mask_full << RB_DEBUG_2_Z1_MASK_FULL_SHIFT) | \ + (z0_req_full << RB_DEBUG_2_Z0_REQ_FULL_SHIFT) | \ + (z1_req_full << RB_DEBUG_2_Z1_REQ_FULL_SHIFT) | \ + (z_samp_full << RB_DEBUG_2_Z_SAMP_FULL_SHIFT) | \ + (z_tile_full << RB_DEBUG_2_Z_TILE_FULL_SHIFT) | \ + (ez_inftile_empty << RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT) | \ + (ez_mask_lower_empty << RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT) | \ + (ez_mask_upper_empty << RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT) | \ + (z0_mask_empty << RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT) | \ + (z1_mask_empty << RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT) | \ + (z0_req_empty << RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT) | \ + (z1_req_empty << RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT) | \ + (z_samp_empty << RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT) | \ + (z_tile_empty << RB_DEBUG_2_Z_TILE_EMPTY_SHIFT)) + +#define RB_DEBUG_2_GET_TILE_FIFO_COUNT(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_TILE_FIFO_COUNT_MASK) >> RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT) +#define RB_DEBUG_2_GET_SX_LAT_FIFO_COUNT(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK) >> RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT) +#define RB_DEBUG_2_GET_MEM_EXPORT_FLAG(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_MEM_EXPORT_FLAG_MASK) >> RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT) +#define RB_DEBUG_2_GET_SYSMEM_BLEND_FLAG(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK) >> RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT) +#define RB_DEBUG_2_GET_CURRENT_TILE_EVENT(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_CURRENT_TILE_EVENT_MASK) >> RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT) +#define RB_DEBUG_2_GET_EZ_INFTILE_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_INFTILE_FULL_MASK) >> RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT) +#define RB_DEBUG_2_GET_EZ_MASK_LOWER_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK) >> RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT) +#define RB_DEBUG_2_GET_EZ_MASK_UPPER_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK) >> RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z0_MASK_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z0_MASK_FULL_MASK) >> RB_DEBUG_2_Z0_MASK_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z1_MASK_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z1_MASK_FULL_MASK) >> RB_DEBUG_2_Z1_MASK_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z0_REQ_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z0_REQ_FULL_MASK) >> RB_DEBUG_2_Z0_REQ_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z1_REQ_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z1_REQ_FULL_MASK) >> RB_DEBUG_2_Z1_REQ_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z_SAMP_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z_SAMP_FULL_MASK) >> RB_DEBUG_2_Z_SAMP_FULL_SHIFT) +#define RB_DEBUG_2_GET_Z_TILE_FULL(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z_TILE_FULL_MASK) >> RB_DEBUG_2_Z_TILE_FULL_SHIFT) +#define RB_DEBUG_2_GET_EZ_INFTILE_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK) >> RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_EZ_MASK_LOWER_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK) >> RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_EZ_MASK_UPPER_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK) >> RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z0_MASK_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z0_MASK_EMPTY_MASK) >> RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z1_MASK_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z1_MASK_EMPTY_MASK) >> RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z0_REQ_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z0_REQ_EMPTY_MASK) >> RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z1_REQ_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z1_REQ_EMPTY_MASK) >> RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z_SAMP_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z_SAMP_EMPTY_MASK) >> RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT) +#define RB_DEBUG_2_GET_Z_TILE_EMPTY(rb_debug_2) \ + ((rb_debug_2 & RB_DEBUG_2_Z_TILE_EMPTY_MASK) >> RB_DEBUG_2_Z_TILE_EMPTY_SHIFT) + +#define RB_DEBUG_2_SET_TILE_FIFO_COUNT(rb_debug_2_reg, tile_fifo_count) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_TILE_FIFO_COUNT_MASK) | (tile_fifo_count << RB_DEBUG_2_TILE_FIFO_COUNT_SHIFT) +#define RB_DEBUG_2_SET_SX_LAT_FIFO_COUNT(rb_debug_2_reg, sx_lat_fifo_count) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_SX_LAT_FIFO_COUNT_MASK) | (sx_lat_fifo_count << RB_DEBUG_2_SX_LAT_FIFO_COUNT_SHIFT) +#define RB_DEBUG_2_SET_MEM_EXPORT_FLAG(rb_debug_2_reg, mem_export_flag) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_MEM_EXPORT_FLAG_MASK) | (mem_export_flag << RB_DEBUG_2_MEM_EXPORT_FLAG_SHIFT) +#define RB_DEBUG_2_SET_SYSMEM_BLEND_FLAG(rb_debug_2_reg, sysmem_blend_flag) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_SYSMEM_BLEND_FLAG_MASK) | (sysmem_blend_flag << RB_DEBUG_2_SYSMEM_BLEND_FLAG_SHIFT) +#define RB_DEBUG_2_SET_CURRENT_TILE_EVENT(rb_debug_2_reg, current_tile_event) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_CURRENT_TILE_EVENT_MASK) | (current_tile_event << RB_DEBUG_2_CURRENT_TILE_EVENT_SHIFT) +#define RB_DEBUG_2_SET_EZ_INFTILE_FULL(rb_debug_2_reg, ez_inftile_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_INFTILE_FULL_MASK) | (ez_inftile_full << RB_DEBUG_2_EZ_INFTILE_FULL_SHIFT) +#define RB_DEBUG_2_SET_EZ_MASK_LOWER_FULL(rb_debug_2_reg, ez_mask_lower_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_LOWER_FULL_MASK) | (ez_mask_lower_full << RB_DEBUG_2_EZ_MASK_LOWER_FULL_SHIFT) +#define RB_DEBUG_2_SET_EZ_MASK_UPPER_FULL(rb_debug_2_reg, ez_mask_upper_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_UPPER_FULL_MASK) | (ez_mask_upper_full << RB_DEBUG_2_EZ_MASK_UPPER_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z0_MASK_FULL(rb_debug_2_reg, z0_mask_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_MASK_FULL_MASK) | (z0_mask_full << RB_DEBUG_2_Z0_MASK_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z1_MASK_FULL(rb_debug_2_reg, z1_mask_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_MASK_FULL_MASK) | (z1_mask_full << RB_DEBUG_2_Z1_MASK_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z0_REQ_FULL(rb_debug_2_reg, z0_req_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_REQ_FULL_MASK) | (z0_req_full << RB_DEBUG_2_Z0_REQ_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z1_REQ_FULL(rb_debug_2_reg, z1_req_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_REQ_FULL_MASK) | (z1_req_full << RB_DEBUG_2_Z1_REQ_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z_SAMP_FULL(rb_debug_2_reg, z_samp_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_SAMP_FULL_MASK) | (z_samp_full << RB_DEBUG_2_Z_SAMP_FULL_SHIFT) +#define RB_DEBUG_2_SET_Z_TILE_FULL(rb_debug_2_reg, z_tile_full) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_TILE_FULL_MASK) | (z_tile_full << RB_DEBUG_2_Z_TILE_FULL_SHIFT) +#define RB_DEBUG_2_SET_EZ_INFTILE_EMPTY(rb_debug_2_reg, ez_inftile_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_INFTILE_EMPTY_MASK) | (ez_inftile_empty << RB_DEBUG_2_EZ_INFTILE_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_EZ_MASK_LOWER_EMPTY(rb_debug_2_reg, ez_mask_lower_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_MASK) | (ez_mask_lower_empty << RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_EZ_MASK_UPPER_EMPTY(rb_debug_2_reg, ez_mask_upper_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_MASK) | (ez_mask_upper_empty << RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z0_MASK_EMPTY(rb_debug_2_reg, z0_mask_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_MASK_EMPTY_MASK) | (z0_mask_empty << RB_DEBUG_2_Z0_MASK_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z1_MASK_EMPTY(rb_debug_2_reg, z1_mask_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_MASK_EMPTY_MASK) | (z1_mask_empty << RB_DEBUG_2_Z1_MASK_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z0_REQ_EMPTY(rb_debug_2_reg, z0_req_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z0_REQ_EMPTY_MASK) | (z0_req_empty << RB_DEBUG_2_Z0_REQ_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z1_REQ_EMPTY(rb_debug_2_reg, z1_req_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z1_REQ_EMPTY_MASK) | (z1_req_empty << RB_DEBUG_2_Z1_REQ_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z_SAMP_EMPTY(rb_debug_2_reg, z_samp_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_SAMP_EMPTY_MASK) | (z_samp_empty << RB_DEBUG_2_Z_SAMP_EMPTY_SHIFT) +#define RB_DEBUG_2_SET_Z_TILE_EMPTY(rb_debug_2_reg, z_tile_empty) \ + rb_debug_2_reg = (rb_debug_2_reg & ~RB_DEBUG_2_Z_TILE_EMPTY_MASK) | (z_tile_empty << RB_DEBUG_2_Z_TILE_EMPTY_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_2_t { + unsigned int tile_fifo_count : RB_DEBUG_2_TILE_FIFO_COUNT_SIZE; + unsigned int sx_lat_fifo_count : RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE; + unsigned int mem_export_flag : RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE; + unsigned int sysmem_blend_flag : RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE; + unsigned int current_tile_event : RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE; + unsigned int ez_inftile_full : RB_DEBUG_2_EZ_INFTILE_FULL_SIZE; + unsigned int ez_mask_lower_full : RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE; + unsigned int ez_mask_upper_full : RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE; + unsigned int z0_mask_full : RB_DEBUG_2_Z0_MASK_FULL_SIZE; + unsigned int z1_mask_full : RB_DEBUG_2_Z1_MASK_FULL_SIZE; + unsigned int z0_req_full : RB_DEBUG_2_Z0_REQ_FULL_SIZE; + unsigned int z1_req_full : RB_DEBUG_2_Z1_REQ_FULL_SIZE; + unsigned int z_samp_full : RB_DEBUG_2_Z_SAMP_FULL_SIZE; + unsigned int z_tile_full : RB_DEBUG_2_Z_TILE_FULL_SIZE; + unsigned int ez_inftile_empty : RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE; + unsigned int ez_mask_lower_empty : RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE; + unsigned int ez_mask_upper_empty : RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE; + unsigned int z0_mask_empty : RB_DEBUG_2_Z0_MASK_EMPTY_SIZE; + unsigned int z1_mask_empty : RB_DEBUG_2_Z1_MASK_EMPTY_SIZE; + unsigned int z0_req_empty : RB_DEBUG_2_Z0_REQ_EMPTY_SIZE; + unsigned int z1_req_empty : RB_DEBUG_2_Z1_REQ_EMPTY_SIZE; + unsigned int z_samp_empty : RB_DEBUG_2_Z_SAMP_EMPTY_SIZE; + unsigned int z_tile_empty : RB_DEBUG_2_Z_TILE_EMPTY_SIZE; + } rb_debug_2_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_2_t { + unsigned int z_tile_empty : RB_DEBUG_2_Z_TILE_EMPTY_SIZE; + unsigned int z_samp_empty : RB_DEBUG_2_Z_SAMP_EMPTY_SIZE; + unsigned int z1_req_empty : RB_DEBUG_2_Z1_REQ_EMPTY_SIZE; + unsigned int z0_req_empty : RB_DEBUG_2_Z0_REQ_EMPTY_SIZE; + unsigned int z1_mask_empty : RB_DEBUG_2_Z1_MASK_EMPTY_SIZE; + unsigned int z0_mask_empty : RB_DEBUG_2_Z0_MASK_EMPTY_SIZE; + unsigned int ez_mask_upper_empty : RB_DEBUG_2_EZ_MASK_UPPER_EMPTY_SIZE; + unsigned int ez_mask_lower_empty : RB_DEBUG_2_EZ_MASK_LOWER_EMPTY_SIZE; + unsigned int ez_inftile_empty : RB_DEBUG_2_EZ_INFTILE_EMPTY_SIZE; + unsigned int z_tile_full : RB_DEBUG_2_Z_TILE_FULL_SIZE; + unsigned int z_samp_full : RB_DEBUG_2_Z_SAMP_FULL_SIZE; + unsigned int z1_req_full : RB_DEBUG_2_Z1_REQ_FULL_SIZE; + unsigned int z0_req_full : RB_DEBUG_2_Z0_REQ_FULL_SIZE; + unsigned int z1_mask_full : RB_DEBUG_2_Z1_MASK_FULL_SIZE; + unsigned int z0_mask_full : RB_DEBUG_2_Z0_MASK_FULL_SIZE; + unsigned int ez_mask_upper_full : RB_DEBUG_2_EZ_MASK_UPPER_FULL_SIZE; + unsigned int ez_mask_lower_full : RB_DEBUG_2_EZ_MASK_LOWER_FULL_SIZE; + unsigned int ez_inftile_full : RB_DEBUG_2_EZ_INFTILE_FULL_SIZE; + unsigned int current_tile_event : RB_DEBUG_2_CURRENT_TILE_EVENT_SIZE; + unsigned int sysmem_blend_flag : RB_DEBUG_2_SYSMEM_BLEND_FLAG_SIZE; + unsigned int mem_export_flag : RB_DEBUG_2_MEM_EXPORT_FLAG_SIZE; + unsigned int sx_lat_fifo_count : RB_DEBUG_2_SX_LAT_FIFO_COUNT_SIZE; + unsigned int tile_fifo_count : RB_DEBUG_2_TILE_FIFO_COUNT_SIZE; + } rb_debug_2_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_2_t f; +} rb_debug_2_u; + + +/* + * RB_DEBUG_3 struct + */ + +#define RB_DEBUG_3_ACCUM_VALID_SIZE 4 +#define RB_DEBUG_3_ACCUM_FLUSHING_SIZE 4 +#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE 6 +#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE 1 +#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE 4 +#define RB_DEBUG_3_SHD_FULL_SIZE 1 +#define RB_DEBUG_3_SHD_EMPTY_SIZE 1 +#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE 1 +#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE 1 +#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE 1 +#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE 1 +#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE 1 +#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE 1 +#define RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE 1 +#define RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE 1 + +#define RB_DEBUG_3_ACCUM_VALID_SHIFT 0 +#define RB_DEBUG_3_ACCUM_FLUSHING_SHIFT 4 +#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT 8 +#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT 14 +#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT 15 +#define RB_DEBUG_3_SHD_FULL_SHIFT 19 +#define RB_DEBUG_3_SHD_EMPTY_SHIFT 20 +#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT 21 +#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT 22 +#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT 23 +#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT 24 +#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT 25 +#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT 26 +#define RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT 27 +#define RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT 28 + +#define RB_DEBUG_3_ACCUM_VALID_MASK 0x0000000f +#define RB_DEBUG_3_ACCUM_FLUSHING_MASK 0x000000f0 +#define RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK 0x00003f00 +#define RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK 0x00004000 +#define RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK 0x00078000 +#define RB_DEBUG_3_SHD_FULL_MASK 0x00080000 +#define RB_DEBUG_3_SHD_EMPTY_MASK 0x00100000 +#define RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK 0x00200000 +#define RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK 0x00400000 +#define RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK 0x00800000 +#define RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK 0x01000000 +#define RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK 0x02000000 +#define RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK 0x04000000 +#define RB_DEBUG_3_ZEXP_LOWER_FULL_MASK 0x08000000 +#define RB_DEBUG_3_ZEXP_UPPER_FULL_MASK 0x10000000 + +#define RB_DEBUG_3_MASK \ + (RB_DEBUG_3_ACCUM_VALID_MASK | \ + RB_DEBUG_3_ACCUM_FLUSHING_MASK | \ + RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK | \ + RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK | \ + RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK | \ + RB_DEBUG_3_SHD_FULL_MASK | \ + RB_DEBUG_3_SHD_EMPTY_MASK | \ + RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK | \ + RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK | \ + RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK | \ + RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK | \ + RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK | \ + RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK | \ + RB_DEBUG_3_ZEXP_LOWER_FULL_MASK | \ + RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) + +#define RB_DEBUG_3(accum_valid, accum_flushing, accum_write_clean_count, accum_input_reg_valid, accum_data_fifo_cnt, shd_full, shd_empty, ez_return_lower_empty, ez_return_upper_empty, ez_return_lower_full, ez_return_upper_full, zexp_lower_empty, zexp_upper_empty, zexp_lower_full, zexp_upper_full) \ + ((accum_valid << RB_DEBUG_3_ACCUM_VALID_SHIFT) | \ + (accum_flushing << RB_DEBUG_3_ACCUM_FLUSHING_SHIFT) | \ + (accum_write_clean_count << RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT) | \ + (accum_input_reg_valid << RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT) | \ + (accum_data_fifo_cnt << RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT) | \ + (shd_full << RB_DEBUG_3_SHD_FULL_SHIFT) | \ + (shd_empty << RB_DEBUG_3_SHD_EMPTY_SHIFT) | \ + (ez_return_lower_empty << RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT) | \ + (ez_return_upper_empty << RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT) | \ + (ez_return_lower_full << RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT) | \ + (ez_return_upper_full << RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT) | \ + (zexp_lower_empty << RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT) | \ + (zexp_upper_empty << RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT) | \ + (zexp_lower_full << RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT) | \ + (zexp_upper_full << RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT)) + +#define RB_DEBUG_3_GET_ACCUM_VALID(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_VALID_MASK) >> RB_DEBUG_3_ACCUM_VALID_SHIFT) +#define RB_DEBUG_3_GET_ACCUM_FLUSHING(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_FLUSHING_MASK) >> RB_DEBUG_3_ACCUM_FLUSHING_SHIFT) +#define RB_DEBUG_3_GET_ACCUM_WRITE_CLEAN_COUNT(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK) >> RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT) +#define RB_DEBUG_3_GET_ACCUM_INPUT_REG_VALID(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK) >> RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT) +#define RB_DEBUG_3_GET_ACCUM_DATA_FIFO_CNT(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK) >> RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT) +#define RB_DEBUG_3_GET_SHD_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_SHD_FULL_MASK) >> RB_DEBUG_3_SHD_FULL_SHIFT) +#define RB_DEBUG_3_GET_SHD_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_SHD_EMPTY_MASK) >> RB_DEBUG_3_SHD_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_EZ_RETURN_LOWER_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK) >> RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_EZ_RETURN_UPPER_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK) >> RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_EZ_RETURN_LOWER_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK) >> RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT) +#define RB_DEBUG_3_GET_EZ_RETURN_UPPER_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK) >> RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT) +#define RB_DEBUG_3_GET_ZEXP_LOWER_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK) >> RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_ZEXP_UPPER_EMPTY(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK) >> RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_3_GET_ZEXP_LOWER_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ZEXP_LOWER_FULL_MASK) >> RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT) +#define RB_DEBUG_3_GET_ZEXP_UPPER_FULL(rb_debug_3) \ + ((rb_debug_3 & RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) >> RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT) + +#define RB_DEBUG_3_SET_ACCUM_VALID(rb_debug_3_reg, accum_valid) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_VALID_MASK) | (accum_valid << RB_DEBUG_3_ACCUM_VALID_SHIFT) +#define RB_DEBUG_3_SET_ACCUM_FLUSHING(rb_debug_3_reg, accum_flushing) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_FLUSHING_MASK) | (accum_flushing << RB_DEBUG_3_ACCUM_FLUSHING_SHIFT) +#define RB_DEBUG_3_SET_ACCUM_WRITE_CLEAN_COUNT(rb_debug_3_reg, accum_write_clean_count) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_MASK) | (accum_write_clean_count << RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SHIFT) +#define RB_DEBUG_3_SET_ACCUM_INPUT_REG_VALID(rb_debug_3_reg, accum_input_reg_valid) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_INPUT_REG_VALID_MASK) | (accum_input_reg_valid << RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SHIFT) +#define RB_DEBUG_3_SET_ACCUM_DATA_FIFO_CNT(rb_debug_3_reg, accum_data_fifo_cnt) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_MASK) | (accum_data_fifo_cnt << RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SHIFT) +#define RB_DEBUG_3_SET_SHD_FULL(rb_debug_3_reg, shd_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_SHD_FULL_MASK) | (shd_full << RB_DEBUG_3_SHD_FULL_SHIFT) +#define RB_DEBUG_3_SET_SHD_EMPTY(rb_debug_3_reg, shd_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_SHD_EMPTY_MASK) | (shd_empty << RB_DEBUG_3_SHD_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_EZ_RETURN_LOWER_EMPTY(rb_debug_3_reg, ez_return_lower_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_MASK) | (ez_return_lower_empty << RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_EZ_RETURN_UPPER_EMPTY(rb_debug_3_reg, ez_return_upper_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_MASK) | (ez_return_upper_empty << RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_EZ_RETURN_LOWER_FULL(rb_debug_3_reg, ez_return_lower_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_LOWER_FULL_MASK) | (ez_return_lower_full << RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SHIFT) +#define RB_DEBUG_3_SET_EZ_RETURN_UPPER_FULL(rb_debug_3_reg, ez_return_upper_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_EZ_RETURN_UPPER_FULL_MASK) | (ez_return_upper_full << RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SHIFT) +#define RB_DEBUG_3_SET_ZEXP_LOWER_EMPTY(rb_debug_3_reg, zexp_lower_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_LOWER_EMPTY_MASK) | (zexp_lower_empty << RB_DEBUG_3_ZEXP_LOWER_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_ZEXP_UPPER_EMPTY(rb_debug_3_reg, zexp_upper_empty) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_UPPER_EMPTY_MASK) | (zexp_upper_empty << RB_DEBUG_3_ZEXP_UPPER_EMPTY_SHIFT) +#define RB_DEBUG_3_SET_ZEXP_LOWER_FULL(rb_debug_3_reg, zexp_lower_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_LOWER_FULL_MASK) | (zexp_lower_full << RB_DEBUG_3_ZEXP_LOWER_FULL_SHIFT) +#define RB_DEBUG_3_SET_ZEXP_UPPER_FULL(rb_debug_3_reg, zexp_upper_full) \ + rb_debug_3_reg = (rb_debug_3_reg & ~RB_DEBUG_3_ZEXP_UPPER_FULL_MASK) | (zexp_upper_full << RB_DEBUG_3_ZEXP_UPPER_FULL_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_3_t { + unsigned int accum_valid : RB_DEBUG_3_ACCUM_VALID_SIZE; + unsigned int accum_flushing : RB_DEBUG_3_ACCUM_FLUSHING_SIZE; + unsigned int accum_write_clean_count : RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE; + unsigned int accum_input_reg_valid : RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE; + unsigned int accum_data_fifo_cnt : RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE; + unsigned int shd_full : RB_DEBUG_3_SHD_FULL_SIZE; + unsigned int shd_empty : RB_DEBUG_3_SHD_EMPTY_SIZE; + unsigned int ez_return_lower_empty : RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE; + unsigned int ez_return_upper_empty : RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE; + unsigned int ez_return_lower_full : RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE; + unsigned int ez_return_upper_full : RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE; + unsigned int zexp_lower_empty : RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE; + unsigned int zexp_upper_empty : RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE; + unsigned int zexp_lower_full : RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE; + unsigned int zexp_upper_full : RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE; + unsigned int : 3; + } rb_debug_3_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_3_t { + unsigned int : 3; + unsigned int zexp_upper_full : RB_DEBUG_3_ZEXP_UPPER_FULL_SIZE; + unsigned int zexp_lower_full : RB_DEBUG_3_ZEXP_LOWER_FULL_SIZE; + unsigned int zexp_upper_empty : RB_DEBUG_3_ZEXP_UPPER_EMPTY_SIZE; + unsigned int zexp_lower_empty : RB_DEBUG_3_ZEXP_LOWER_EMPTY_SIZE; + unsigned int ez_return_upper_full : RB_DEBUG_3_EZ_RETURN_UPPER_FULL_SIZE; + unsigned int ez_return_lower_full : RB_DEBUG_3_EZ_RETURN_LOWER_FULL_SIZE; + unsigned int ez_return_upper_empty : RB_DEBUG_3_EZ_RETURN_UPPER_EMPTY_SIZE; + unsigned int ez_return_lower_empty : RB_DEBUG_3_EZ_RETURN_LOWER_EMPTY_SIZE; + unsigned int shd_empty : RB_DEBUG_3_SHD_EMPTY_SIZE; + unsigned int shd_full : RB_DEBUG_3_SHD_FULL_SIZE; + unsigned int accum_data_fifo_cnt : RB_DEBUG_3_ACCUM_DATA_FIFO_CNT_SIZE; + unsigned int accum_input_reg_valid : RB_DEBUG_3_ACCUM_INPUT_REG_VALID_SIZE; + unsigned int accum_write_clean_count : RB_DEBUG_3_ACCUM_WRITE_CLEAN_COUNT_SIZE; + unsigned int accum_flushing : RB_DEBUG_3_ACCUM_FLUSHING_SIZE; + unsigned int accum_valid : RB_DEBUG_3_ACCUM_VALID_SIZE; + } rb_debug_3_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_3_t f; +} rb_debug_3_u; + + +/* + * RB_DEBUG_4 struct + */ + +#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE 1 +#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE 1 +#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE 1 +#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE 1 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE 1 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE 1 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE 1 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE 1 +#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE 1 +#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE 4 + +#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT 0 +#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT 1 +#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT 2 +#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT 3 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT 4 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT 5 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT 6 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT 7 +#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT 8 +#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT 9 + +#define RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK 0x00000001 +#define RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK 0x00000002 +#define RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK 0x00000004 +#define RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK 0x00000008 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK 0x00000010 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK 0x00000020 +#define RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK 0x00000040 +#define RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK 0x00000080 +#define RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK 0x00000100 +#define RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK 0x00001e00 + +#define RB_DEBUG_4_MASK \ + (RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK | \ + RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK | \ + RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK | \ + RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK | \ + RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK | \ + RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK | \ + RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK | \ + RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK | \ + RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK | \ + RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) + +#define RB_DEBUG_4(gmem_rd_access_flag, gmem_wr_access_flag, sysmem_rd_access_flag, sysmem_wr_access_flag, accum_data_fifo_empty, accum_order_fifo_empty, accum_data_fifo_full, accum_order_fifo_full, sysmem_write_count_overflow, context_count_debug) \ + ((gmem_rd_access_flag << RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT) | \ + (gmem_wr_access_flag << RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT) | \ + (sysmem_rd_access_flag << RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT) | \ + (sysmem_wr_access_flag << RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT) | \ + (accum_data_fifo_empty << RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT) | \ + (accum_order_fifo_empty << RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT) | \ + (accum_data_fifo_full << RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT) | \ + (accum_order_fifo_full << RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT) | \ + (sysmem_write_count_overflow << RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT) | \ + (context_count_debug << RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT)) + +#define RB_DEBUG_4_GET_GMEM_RD_ACCESS_FLAG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK) >> RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_GET_GMEM_WR_ACCESS_FLAG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK) >> RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_GET_SYSMEM_RD_ACCESS_FLAG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK) >> RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_GET_SYSMEM_WR_ACCESS_FLAG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK) >> RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_GET_ACCUM_DATA_FIFO_EMPTY(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK) >> RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT) +#define RB_DEBUG_4_GET_ACCUM_ORDER_FIFO_EMPTY(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK) >> RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT) +#define RB_DEBUG_4_GET_ACCUM_DATA_FIFO_FULL(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK) >> RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT) +#define RB_DEBUG_4_GET_ACCUM_ORDER_FIFO_FULL(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK) >> RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT) +#define RB_DEBUG_4_GET_SYSMEM_WRITE_COUNT_OVERFLOW(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK) >> RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT) +#define RB_DEBUG_4_GET_CONTEXT_COUNT_DEBUG(rb_debug_4) \ + ((rb_debug_4 & RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) >> RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT) + +#define RB_DEBUG_4_SET_GMEM_RD_ACCESS_FLAG(rb_debug_4_reg, gmem_rd_access_flag) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_MASK) | (gmem_rd_access_flag << RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_SET_GMEM_WR_ACCESS_FLAG(rb_debug_4_reg, gmem_wr_access_flag) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_MASK) | (gmem_wr_access_flag << RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_SET_SYSMEM_RD_ACCESS_FLAG(rb_debug_4_reg, sysmem_rd_access_flag) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_MASK) | (sysmem_rd_access_flag << RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_SET_SYSMEM_WR_ACCESS_FLAG(rb_debug_4_reg, sysmem_wr_access_flag) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_MASK) | (sysmem_wr_access_flag << RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SHIFT) +#define RB_DEBUG_4_SET_ACCUM_DATA_FIFO_EMPTY(rb_debug_4_reg, accum_data_fifo_empty) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_MASK) | (accum_data_fifo_empty << RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SHIFT) +#define RB_DEBUG_4_SET_ACCUM_ORDER_FIFO_EMPTY(rb_debug_4_reg, accum_order_fifo_empty) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_MASK) | (accum_order_fifo_empty << RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SHIFT) +#define RB_DEBUG_4_SET_ACCUM_DATA_FIFO_FULL(rb_debug_4_reg, accum_data_fifo_full) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_MASK) | (accum_data_fifo_full << RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SHIFT) +#define RB_DEBUG_4_SET_ACCUM_ORDER_FIFO_FULL(rb_debug_4_reg, accum_order_fifo_full) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_MASK) | (accum_order_fifo_full << RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SHIFT) +#define RB_DEBUG_4_SET_SYSMEM_WRITE_COUNT_OVERFLOW(rb_debug_4_reg, sysmem_write_count_overflow) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_MASK) | (sysmem_write_count_overflow << RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SHIFT) +#define RB_DEBUG_4_SET_CONTEXT_COUNT_DEBUG(rb_debug_4_reg, context_count_debug) \ + rb_debug_4_reg = (rb_debug_4_reg & ~RB_DEBUG_4_CONTEXT_COUNT_DEBUG_MASK) | (context_count_debug << RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_debug_4_t { + unsigned int gmem_rd_access_flag : RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE; + unsigned int gmem_wr_access_flag : RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE; + unsigned int sysmem_rd_access_flag : RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE; + unsigned int sysmem_wr_access_flag : RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE; + unsigned int accum_data_fifo_empty : RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE; + unsigned int accum_order_fifo_empty : RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE; + unsigned int accum_data_fifo_full : RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE; + unsigned int accum_order_fifo_full : RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE; + unsigned int sysmem_write_count_overflow : RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE; + unsigned int context_count_debug : RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE; + unsigned int : 19; + } rb_debug_4_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_debug_4_t { + unsigned int : 19; + unsigned int context_count_debug : RB_DEBUG_4_CONTEXT_COUNT_DEBUG_SIZE; + unsigned int sysmem_write_count_overflow : RB_DEBUG_4_SYSMEM_WRITE_COUNT_OVERFLOW_SIZE; + unsigned int accum_order_fifo_full : RB_DEBUG_4_ACCUM_ORDER_FIFO_FULL_SIZE; + unsigned int accum_data_fifo_full : RB_DEBUG_4_ACCUM_DATA_FIFO_FULL_SIZE; + unsigned int accum_order_fifo_empty : RB_DEBUG_4_ACCUM_ORDER_FIFO_EMPTY_SIZE; + unsigned int accum_data_fifo_empty : RB_DEBUG_4_ACCUM_DATA_FIFO_EMPTY_SIZE; + unsigned int sysmem_wr_access_flag : RB_DEBUG_4_SYSMEM_WR_ACCESS_FLAG_SIZE; + unsigned int sysmem_rd_access_flag : RB_DEBUG_4_SYSMEM_RD_ACCESS_FLAG_SIZE; + unsigned int gmem_wr_access_flag : RB_DEBUG_4_GMEM_WR_ACCESS_FLAG_SIZE; + unsigned int gmem_rd_access_flag : RB_DEBUG_4_GMEM_RD_ACCESS_FLAG_SIZE; + } rb_debug_4_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_debug_4_t f; +} rb_debug_4_u; + + +/* + * RB_FLAG_CONTROL struct + */ + +#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE 1 + +#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT 0 + +#define RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK 0x00000001 + +#define RB_FLAG_CONTROL_MASK \ + (RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) + +#define RB_FLAG_CONTROL(debug_flag_clear) \ + ((debug_flag_clear << RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT)) + +#define RB_FLAG_CONTROL_GET_DEBUG_FLAG_CLEAR(rb_flag_control) \ + ((rb_flag_control & RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) >> RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT) + +#define RB_FLAG_CONTROL_SET_DEBUG_FLAG_CLEAR(rb_flag_control_reg, debug_flag_clear) \ + rb_flag_control_reg = (rb_flag_control_reg & ~RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_MASK) | (debug_flag_clear << RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_flag_control_t { + unsigned int debug_flag_clear : RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE; + unsigned int : 31; + } rb_flag_control_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_flag_control_t { + unsigned int : 31; + unsigned int debug_flag_clear : RB_FLAG_CONTROL_DEBUG_FLAG_CLEAR_SIZE; + } rb_flag_control_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_flag_control_t f; +} rb_flag_control_u; + + +/* + * RB_BC_SPARES struct + */ + +#define RB_BC_SPARES_RESERVED_SIZE 32 + +#define RB_BC_SPARES_RESERVED_SHIFT 0 + +#define RB_BC_SPARES_RESERVED_MASK 0xffffffff + +#define RB_BC_SPARES_MASK \ + (RB_BC_SPARES_RESERVED_MASK) + +#define RB_BC_SPARES(reserved) \ + ((reserved << RB_BC_SPARES_RESERVED_SHIFT)) + +#define RB_BC_SPARES_GET_RESERVED(rb_bc_spares) \ + ((rb_bc_spares & RB_BC_SPARES_RESERVED_MASK) >> RB_BC_SPARES_RESERVED_SHIFT) + +#define RB_BC_SPARES_SET_RESERVED(rb_bc_spares_reg, reserved) \ + rb_bc_spares_reg = (rb_bc_spares_reg & ~RB_BC_SPARES_RESERVED_MASK) | (reserved << RB_BC_SPARES_RESERVED_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _rb_bc_spares_t { + unsigned int reserved : RB_BC_SPARES_RESERVED_SIZE; + } rb_bc_spares_t; + +#else // !BIGENDIAN_OS + + typedef struct _rb_bc_spares_t { + unsigned int reserved : RB_BC_SPARES_RESERVED_SIZE; + } rb_bc_spares_t; + +#endif + +typedef union { + unsigned int val : 32; + rb_bc_spares_t f; +} rb_bc_spares_u; + + +/* + * BC_DUMMY_CRAYRB_ENUMS struct + */ + +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE 6 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE 1 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE 2 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE 2 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE 6 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE 3 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE 6 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE 1 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE 2 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE 3 + +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT 0 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT 6 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT 7 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT 9 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT 11 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT 17 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT 20 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT 26 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT 27 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT 29 + +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK 0x0000003f +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK 0x00000040 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK 0x00000180 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK 0x00000600 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK 0x0001f800 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK 0x000e0000 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK 0x03f00000 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK 0x04000000 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK 0x18000000 +#define BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK 0xe0000000 + +#define BC_DUMMY_CRAYRB_ENUMS_MASK \ + (BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK | \ + BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) + +#define BC_DUMMY_CRAYRB_ENUMS(dummy_crayrb_depth_format, dummy_crayrb_surface_swap, dummy_crayrb_depth_array, dummy_crayrb_array, dummy_crayrb_color_format, dummy_crayrb_surface_number, dummy_crayrb_surface_format, dummy_crayrb_surface_tiling, dummy_crayrb_surface_array, dummy_rb_copy_dest_info_number) \ + ((dummy_crayrb_depth_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT) | \ + (dummy_crayrb_surface_swap << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT) | \ + (dummy_crayrb_depth_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT) | \ + (dummy_crayrb_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT) | \ + (dummy_crayrb_color_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT) | \ + (dummy_crayrb_surface_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT) | \ + (dummy_crayrb_surface_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT) | \ + (dummy_crayrb_surface_tiling << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT) | \ + (dummy_crayrb_surface_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT) | \ + (dummy_rb_copy_dest_info_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT)) + +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_DEPTH_FORMAT(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_SWAP(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_DEPTH_ARRAY(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_ARRAY(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_COLOR_FORMAT(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_NUMBER(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_FORMAT(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_TILING(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_CRAYRB_SURFACE_ARRAY(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_GET_DUMMY_RB_COPY_DEST_INFO_NUMBER(bc_dummy_crayrb_enums) \ + ((bc_dummy_crayrb_enums & BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) >> BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT) + +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_DEPTH_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_depth_format) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_MASK) | (dummy_crayrb_depth_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_SWAP(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_swap) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_MASK) | (dummy_crayrb_surface_swap << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_DEPTH_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_depth_array) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_MASK) | (dummy_crayrb_depth_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_array) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_MASK) | (dummy_crayrb_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_COLOR_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_color_format) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_MASK) | (dummy_crayrb_color_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_NUMBER(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_number) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_MASK) | (dummy_crayrb_surface_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_FORMAT(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_format) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_MASK) | (dummy_crayrb_surface_format << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_TILING(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_tiling) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_MASK) | (dummy_crayrb_surface_tiling << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_CRAYRB_SURFACE_ARRAY(bc_dummy_crayrb_enums_reg, dummy_crayrb_surface_array) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_MASK) | (dummy_crayrb_surface_array << BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SHIFT) +#define BC_DUMMY_CRAYRB_ENUMS_SET_DUMMY_RB_COPY_DEST_INFO_NUMBER(bc_dummy_crayrb_enums_reg, dummy_rb_copy_dest_info_number) \ + bc_dummy_crayrb_enums_reg = (bc_dummy_crayrb_enums_reg & ~BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_MASK) | (dummy_rb_copy_dest_info_number << BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bc_dummy_crayrb_enums_t { + unsigned int dummy_crayrb_depth_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE; + unsigned int dummy_crayrb_surface_swap : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE; + unsigned int dummy_crayrb_depth_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE; + unsigned int dummy_crayrb_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE; + unsigned int dummy_crayrb_color_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE; + unsigned int dummy_crayrb_surface_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE; + unsigned int dummy_crayrb_surface_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE; + unsigned int dummy_crayrb_surface_tiling : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE; + unsigned int dummy_crayrb_surface_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE; + unsigned int dummy_rb_copy_dest_info_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE; + } bc_dummy_crayrb_enums_t; + +#else // !BIGENDIAN_OS + + typedef struct _bc_dummy_crayrb_enums_t { + unsigned int dummy_rb_copy_dest_info_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_RB_COPY_DEST_INFO_NUMBER_SIZE; + unsigned int dummy_crayrb_surface_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_ARRAY_SIZE; + unsigned int dummy_crayrb_surface_tiling : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_TILING_SIZE; + unsigned int dummy_crayrb_surface_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_FORMAT_SIZE; + unsigned int dummy_crayrb_surface_number : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_NUMBER_SIZE; + unsigned int dummy_crayrb_color_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_COLOR_FORMAT_SIZE; + unsigned int dummy_crayrb_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_ARRAY_SIZE; + unsigned int dummy_crayrb_depth_array : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_ARRAY_SIZE; + unsigned int dummy_crayrb_surface_swap : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_SURFACE_SWAP_SIZE; + unsigned int dummy_crayrb_depth_format : BC_DUMMY_CRAYRB_ENUMS_DUMMY_CRAYRB_DEPTH_FORMAT_SIZE; + } bc_dummy_crayrb_enums_t; + +#endif + +typedef union { + unsigned int val : 32; + bc_dummy_crayrb_enums_t f; +} bc_dummy_crayrb_enums_u; + + +/* + * BC_DUMMY_CRAYRB_MOREENUMS struct + */ + +#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE 2 + +#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT 0 + +#define BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK 0x00000003 + +#define BC_DUMMY_CRAYRB_MOREENUMS_MASK \ + (BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) + +#define BC_DUMMY_CRAYRB_MOREENUMS(dummy_crayrb_colorarrayx) \ + ((dummy_crayrb_colorarrayx << BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT)) + +#define BC_DUMMY_CRAYRB_MOREENUMS_GET_DUMMY_CRAYRB_COLORARRAYX(bc_dummy_crayrb_moreenums) \ + ((bc_dummy_crayrb_moreenums & BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) >> BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT) + +#define BC_DUMMY_CRAYRB_MOREENUMS_SET_DUMMY_CRAYRB_COLORARRAYX(bc_dummy_crayrb_moreenums_reg, dummy_crayrb_colorarrayx) \ + bc_dummy_crayrb_moreenums_reg = (bc_dummy_crayrb_moreenums_reg & ~BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_MASK) | (dummy_crayrb_colorarrayx << BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SHIFT) + +#ifndef BIGENDIAN_OS + + typedef struct _bc_dummy_crayrb_moreenums_t { + unsigned int dummy_crayrb_colorarrayx : BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE; + unsigned int : 30; + } bc_dummy_crayrb_moreenums_t; + +#else // !BIGENDIAN_OS + + typedef struct _bc_dummy_crayrb_moreenums_t { + unsigned int : 30; + unsigned int dummy_crayrb_colorarrayx : BC_DUMMY_CRAYRB_MOREENUMS_DUMMY_CRAYRB_COLORARRAYX_SIZE; + } bc_dummy_crayrb_moreenums_t; + +#endif + +typedef union { + unsigned int val : 32; + bc_dummy_crayrb_moreenums_t f; +} bc_dummy_crayrb_moreenums_u; + + +#endif + + diff --git a/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_typedef.h b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_typedef.h new file mode 100644 index 000000000000..6968abb48bd7 --- /dev/null +++ b/drivers/mxc/amd-gpu/include/reg/yamato/22/yamato_typedef.h @@ -0,0 +1,550 @@ +/* Copyright (c) 2002,2007-2009, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#if !defined (_yamato_TYPEDEF_HEADER) +#define _yamato_TYPEDEF_HEADER + +#include "yamato_registers.h" + +typedef union PA_CL_VPORT_XSCALE regPA_CL_VPORT_XSCALE; +typedef union PA_CL_VPORT_XOFFSET regPA_CL_VPORT_XOFFSET; +typedef union PA_CL_VPORT_YSCALE regPA_CL_VPORT_YSCALE; +typedef union PA_CL_VPORT_YOFFSET regPA_CL_VPORT_YOFFSET; +typedef union PA_CL_VPORT_ZSCALE regPA_CL_VPORT_ZSCALE; +typedef union PA_CL_VPORT_ZOFFSET regPA_CL_VPORT_ZOFFSET; +typedef union PA_CL_VTE_CNTL regPA_CL_VTE_CNTL; +typedef union PA_CL_CLIP_CNTL regPA_CL_CLIP_CNTL; +typedef union PA_CL_GB_VERT_CLIP_ADJ regPA_CL_GB_VERT_CLIP_ADJ; +typedef union PA_CL_GB_VERT_DISC_ADJ regPA_CL_GB_VERT_DISC_ADJ; +typedef union PA_CL_GB_HORZ_CLIP_ADJ regPA_CL_GB_HORZ_CLIP_ADJ; +typedef union PA_CL_GB_HORZ_DISC_ADJ regPA_CL_GB_HORZ_DISC_ADJ; +typedef union PA_CL_ENHANCE regPA_CL_ENHANCE; +typedef union PA_SC_ENHANCE regPA_SC_ENHANCE; +typedef union PA_SU_VTX_CNTL regPA_SU_VTX_CNTL; +typedef union PA_SU_POINT_SIZE regPA_SU_POINT_SIZE; +typedef union PA_SU_POINT_MINMAX regPA_SU_POINT_MINMAX; +typedef union PA_SU_LINE_CNTL regPA_SU_LINE_CNTL; +typedef union PA_SU_FACE_DATA regPA_SU_FACE_DATA; +typedef union PA_SU_SC_MODE_CNTL regPA_SU_SC_MODE_CNTL; +typedef union PA_SU_POLY_OFFSET_FRONT_SCALE regPA_SU_POLY_OFFSET_FRONT_SCALE; +typedef union PA_SU_POLY_OFFSET_FRONT_OFFSET regPA_SU_POLY_OFFSET_FRONT_OFFSET; +typedef union PA_SU_POLY_OFFSET_BACK_SCALE regPA_SU_POLY_OFFSET_BACK_SCALE; +typedef union PA_SU_POLY_OFFSET_BACK_OFFSET regPA_SU_POLY_OFFSET_BACK_OFFSET; +typedef union PA_SU_PERFCOUNTER0_SELECT regPA_SU_PERFCOUNTER0_SELECT; +typedef union PA_SU_PERFCOUNTER1_SELECT regPA_SU_PERFCOUNTER1_SELECT; +typedef union PA_SU_PERFCOUNTER2_SELECT regPA_SU_PERFCOUNTER2_SELECT; +typedef union PA_SU_PERFCOUNTER3_SELECT regPA_SU_PERFCOUNTER3_SELECT; +typedef union PA_SU_PERFCOUNTER0_LOW regPA_SU_PERFCOUNTER0_LOW; +typedef union PA_SU_PERFCOUNTER0_HI regPA_SU_PERFCOUNTER0_HI; +typedef union PA_SU_PERFCOUNTER1_LOW regPA_SU_PERFCOUNTER1_LOW; +typedef union PA_SU_PERFCOUNTER1_HI regPA_SU_PERFCOUNTER1_HI; +typedef union PA_SU_PERFCOUNTER2_LOW regPA_SU_PERFCOUNTER2_LOW; +typedef union PA_SU_PERFCOUNTER2_HI regPA_SU_PERFCOUNTER2_HI; +typedef union PA_SU_PERFCOUNTER3_LOW regPA_SU_PERFCOUNTER3_LOW; +typedef union PA_SU_PERFCOUNTER3_HI regPA_SU_PERFCOUNTER3_HI; +typedef union PA_SC_WINDOW_OFFSET regPA_SC_WINDOW_OFFSET; +typedef union PA_SC_AA_CONFIG regPA_SC_AA_CONFIG; +typedef union PA_SC_AA_MASK regPA_SC_AA_MASK; +typedef union PA_SC_LINE_STIPPLE regPA_SC_LINE_STIPPLE; +typedef union PA_SC_LINE_CNTL regPA_SC_LINE_CNTL; +typedef union PA_SC_WINDOW_SCISSOR_TL regPA_SC_WINDOW_SCISSOR_TL; +typedef union PA_SC_WINDOW_SCISSOR_BR regPA_SC_WINDOW_SCISSOR_BR; +typedef union PA_SC_SCREEN_SCISSOR_TL regPA_SC_SCREEN_SCISSOR_TL; +typedef union PA_SC_SCREEN_SCISSOR_BR regPA_SC_SCREEN_SCISSOR_BR; +typedef union PA_SC_VIZ_QUERY regPA_SC_VIZ_QUERY; +typedef union PA_SC_VIZ_QUERY_STATUS regPA_SC_VIZ_QUERY_STATUS; +typedef union PA_SC_LINE_STIPPLE_STATE regPA_SC_LINE_STIPPLE_STATE; +typedef union PA_SC_PERFCOUNTER0_SELECT regPA_SC_PERFCOUNTER0_SELECT; +typedef union PA_SC_PERFCOUNTER0_LOW regPA_SC_PERFCOUNTER0_LOW; +typedef union PA_SC_PERFCOUNTER0_HI regPA_SC_PERFCOUNTER0_HI; +typedef union PA_CL_CNTL_STATUS regPA_CL_CNTL_STATUS; +typedef union PA_SU_CNTL_STATUS regPA_SU_CNTL_STATUS; +typedef union PA_SC_CNTL_STATUS regPA_SC_CNTL_STATUS; +typedef union PA_SU_DEBUG_CNTL regPA_SU_DEBUG_CNTL; +typedef union PA_SU_DEBUG_DATA regPA_SU_DEBUG_DATA; +typedef union PA_SC_DEBUG_CNTL regPA_SC_DEBUG_CNTL; +typedef union PA_SC_DEBUG_DATA regPA_SC_DEBUG_DATA; +typedef union GFX_COPY_STATE regGFX_COPY_STATE; +typedef union VGT_DRAW_INITIATOR regVGT_DRAW_INITIATOR; +typedef union VGT_EVENT_INITIATOR regVGT_EVENT_INITIATOR; +typedef union VGT_DMA_BASE regVGT_DMA_BASE; +typedef union VGT_DMA_SIZE regVGT_DMA_SIZE; +typedef union VGT_BIN_BASE regVGT_BIN_BASE; +typedef union VGT_BIN_SIZE regVGT_BIN_SIZE; +typedef union VGT_CURRENT_BIN_ID_MIN regVGT_CURRENT_BIN_ID_MIN; +typedef union VGT_CURRENT_BIN_ID_MAX regVGT_CURRENT_BIN_ID_MAX; +typedef union VGT_IMMED_DATA regVGT_IMMED_DATA; +typedef union VGT_MAX_VTX_INDX regVGT_MAX_VTX_INDX; +typedef union VGT_MIN_VTX_INDX regVGT_MIN_VTX_INDX; +typedef union VGT_INDX_OFFSET regVGT_INDX_OFFSET; +typedef union VGT_VERTEX_REUSE_BLOCK_CNTL regVGT_VERTEX_REUSE_BLOCK_CNTL; +typedef union VGT_OUT_DEALLOC_CNTL regVGT_OUT_DEALLOC_CNTL; +typedef union VGT_MULTI_PRIM_IB_RESET_INDX regVGT_MULTI_PRIM_IB_RESET_INDX; +typedef union VGT_ENHANCE regVGT_ENHANCE; +typedef union VGT_VTX_VECT_EJECT_REG regVGT_VTX_VECT_EJECT_REG; +typedef union VGT_LAST_COPY_STATE regVGT_LAST_COPY_STATE; +typedef union VGT_DEBUG_CNTL regVGT_DEBUG_CNTL; +typedef union VGT_DEBUG_DATA regVGT_DEBUG_DATA; +typedef union VGT_CNTL_STATUS regVGT_CNTL_STATUS; +typedef union VGT_CRC_SQ_DATA regVGT_CRC_SQ_DATA; +typedef union VGT_CRC_SQ_CTRL regVGT_CRC_SQ_CTRL; +typedef union VGT_PERFCOUNTER0_SELECT regVGT_PERFCOUNTER0_SELECT; +typedef union VGT_PERFCOUNTER1_SELECT regVGT_PERFCOUNTER1_SELECT; +typedef union VGT_PERFCOUNTER2_SELECT regVGT_PERFCOUNTER2_SELECT; +typedef union VGT_PERFCOUNTER3_SELECT regVGT_PERFCOUNTER3_SELECT; +typedef union VGT_PERFCOUNTER0_LOW regVGT_PERFCOUNTER0_LOW; +typedef union VGT_PERFCOUNTER1_LOW regVGT_PERFCOUNTER1_LOW; +typedef union VGT_PERFCOUNTER2_LOW regVGT_PERFCOUNTER2_LOW; +typedef union VGT_PERFCOUNTER3_LOW regVGT_PERFCOUNTER3_LOW; +typedef union VGT_PERFCOUNTER0_HI regVGT_PERFCOUNTER0_HI; +typedef union VGT_PERFCOUNTER1_HI regVGT_PERFCOUNTER1_HI; +typedef union VGT_PERFCOUNTER2_HI regVGT_PERFCOUNTER2_HI; +typedef union VGT_PERFCOUNTER3_HI regVGT_PERFCOUNTER3_HI; +typedef union TC_CNTL_STATUS regTC_CNTL_STATUS; +typedef union TCR_CHICKEN regTCR_CHICKEN; +typedef union TCF_CHICKEN regTCF_CHICKEN; +typedef union TCM_CHICKEN regTCM_CHICKEN; +typedef union TCR_PERFCOUNTER0_SELECT regTCR_PERFCOUNTER0_SELECT; +typedef union TCR_PERFCOUNTER1_SELECT regTCR_PERFCOUNTER1_SELECT; +typedef union TCR_PERFCOUNTER0_HI regTCR_PERFCOUNTER0_HI; +typedef union TCR_PERFCOUNTER1_HI regTCR_PERFCOUNTER1_HI; +typedef union TCR_PERFCOUNTER0_LOW regTCR_PERFCOUNTER0_LOW; +typedef union TCR_PERFCOUNTER1_LOW regTCR_PERFCOUNTER1_LOW; +typedef union TP_TC_CLKGATE_CNTL regTP_TC_CLKGATE_CNTL; +typedef union TPC_CNTL_STATUS regTPC_CNTL_STATUS; +typedef union TPC_DEBUG0 regTPC_DEBUG0; +typedef union TPC_DEBUG1 regTPC_DEBUG1; +typedef union TPC_CHICKEN regTPC_CHICKEN; +typedef union TP0_CNTL_STATUS regTP0_CNTL_STATUS; +typedef union TP0_DEBUG regTP0_DEBUG; +typedef union TP0_CHICKEN regTP0_CHICKEN; +typedef union TP0_PERFCOUNTER0_SELECT regTP0_PERFCOUNTER0_SELECT; +typedef union TP0_PERFCOUNTER0_HI regTP0_PERFCOUNTER0_HI; +typedef union TP0_PERFCOUNTER0_LOW regTP0_PERFCOUNTER0_LOW; +typedef union TP0_PERFCOUNTER1_SELECT regTP0_PERFCOUNTER1_SELECT; +typedef union TP0_PERFCOUNTER1_HI regTP0_PERFCOUNTER1_HI; +typedef union TP0_PERFCOUNTER1_LOW regTP0_PERFCOUNTER1_LOW; +typedef union TCM_PERFCOUNTER0_SELECT regTCM_PERFCOUNTER0_SELECT; +typedef union TCM_PERFCOUNTER1_SELECT regTCM_PERFCOUNTER1_SELECT; +typedef union TCM_PERFCOUNTER0_HI regTCM_PERFCOUNTER0_HI; +typedef union TCM_PERFCOUNTER1_HI regTCM_PERFCOUNTER1_HI; +typedef union TCM_PERFCOUNTER0_LOW regTCM_PERFCOUNTER0_LOW; +typedef union TCM_PERFCOUNTER1_LOW regTCM_PERFCOUNTER1_LOW; +typedef union TCF_PERFCOUNTER0_SELECT regTCF_PERFCOUNTER0_SELECT; +typedef union TCF_PERFCOUNTER1_SELECT regTCF_PERFCOUNTER1_SELECT; +typedef union TCF_PERFCOUNTER2_SELECT regTCF_PERFCOUNTER2_SELECT; +typedef union TCF_PERFCOUNTER3_SELECT regTCF_PERFCOUNTER3_SELECT; +typedef union TCF_PERFCOUNTER4_SELECT regTCF_PERFCOUNTER4_SELECT; +typedef union TCF_PERFCOUNTER5_SELECT regTCF_PERFCOUNTER5_SELECT; +typedef union TCF_PERFCOUNTER6_SELECT regTCF_PERFCOUNTER6_SELECT; +typedef union TCF_PERFCOUNTER7_SELECT regTCF_PERFCOUNTER7_SELECT; +typedef union TCF_PERFCOUNTER8_SELECT regTCF_PERFCOUNTER8_SELECT; +typedef union TCF_PERFCOUNTER9_SELECT regTCF_PERFCOUNTER9_SELECT; +typedef union TCF_PERFCOUNTER10_SELECT regTCF_PERFCOUNTER10_SELECT; +typedef union TCF_PERFCOUNTER11_SELECT regTCF_PERFCOUNTER11_SELECT; +typedef union TCF_PERFCOUNTER0_HI regTCF_PERFCOUNTER0_HI; +typedef union TCF_PERFCOUNTER1_HI regTCF_PERFCOUNTER1_HI; +typedef union TCF_PERFCOUNTER2_HI regTCF_PERFCOUNTER2_HI; +typedef union TCF_PERFCOUNTER3_HI regTCF_PERFCOUNTER3_HI; +typedef union TCF_PERFCOUNTER4_HI regTCF_PERFCOUNTER4_HI; +typedef union TCF_PERFCOUNTER5_HI regTCF_PERFCOUNTER5_HI; +typedef union TCF_PERFCOUNTER6_HI regTCF_PERFCOUNTER6_HI; +typedef union TCF_PERFCOUNTER7_HI regTCF_PERFCOUNTER7_HI; +typedef union TCF_PERFCOUNTER8_HI regTCF_PERFCOUNTER8_HI; +typedef union TCF_PERFCOUNTER9_HI regTCF_PERFCOUNTER9_HI; +typedef union TCF_PERFCOUNTER10_HI regTCF_PERFCOUNTER10_HI; +typedef union TCF_PERFCOUNTER11_HI regTCF_PERFCOUNTER11_HI; +typedef union TCF_PERFCOUNTER0_LOW regTCF_PERFCOUNTER0_LOW; +typedef union TCF_PERFCOUNTER1_LOW regTCF_PERFCOUNTER1_LOW; +typedef union TCF_PERFCOUNTER2_LOW regTCF_PERFCOUNTER2_LOW; +typedef union TCF_PERFCOUNTER3_LOW regTCF_PERFCOUNTER3_LOW; +typedef union TCF_PERFCOUNTER4_LOW regTCF_PERFCOUNTER4_LOW; +typedef union TCF_PERFCOUNTER5_LOW regTCF_PERFCOUNTER5_LOW; +typedef union TCF_PERFCOUNTER6_LOW regTCF_PERFCOUNTER6_LOW; +typedef union TCF_PERFCOUNTER7_LOW regTCF_PERFCOUNTER7_LOW; +typedef union TCF_PERFCOUNTER8_LOW regTCF_PERFCOUNTER8_LOW; +typedef union TCF_PERFCOUNTER9_LOW regTCF_PERFCOUNTER9_LOW; +typedef union TCF_PERFCOUNTER10_LOW regTCF_PERFCOUNTER10_LOW; +typedef union TCF_PERFCOUNTER11_LOW regTCF_PERFCOUNTER11_LOW; +typedef union TCF_DEBUG regTCF_DEBUG; +typedef union TCA_FIFO_DEBUG regTCA_FIFO_DEBUG; +typedef union TCA_PROBE_DEBUG regTCA_PROBE_DEBUG; +typedef union TCA_TPC_DEBUG regTCA_TPC_DEBUG; +typedef union TCB_CORE_DEBUG regTCB_CORE_DEBUG; +typedef union TCB_TAG0_DEBUG regTCB_TAG0_DEBUG; +typedef union TCB_TAG1_DEBUG regTCB_TAG1_DEBUG; +typedef union TCB_TAG2_DEBUG regTCB_TAG2_DEBUG; +typedef union TCB_TAG3_DEBUG regTCB_TAG3_DEBUG; +typedef union TCB_FETCH_GEN_SECTOR_WALKER0_DEBUG regTCB_FETCH_GEN_SECTOR_WALKER0_DEBUG; +typedef union TCB_FETCH_GEN_WALKER_DEBUG regTCB_FETCH_GEN_WALKER_DEBUG; +typedef union TCB_FETCH_GEN_PIPE0_DEBUG regTCB_FETCH_GEN_PIPE0_DEBUG; +typedef union TCD_INPUT0_DEBUG regTCD_INPUT0_DEBUG; +typedef union TCD_DEGAMMA_DEBUG regTCD_DEGAMMA_DEBUG; +typedef union TCD_DXTMUX_SCTARB_DEBUG regTCD_DXTMUX_SCTARB_DEBUG; +typedef union TCD_DXTC_ARB_DEBUG regTCD_DXTC_ARB_DEBUG; +typedef union TCD_STALLS_DEBUG regTCD_STALLS_DEBUG; +typedef union TCO_STALLS_DEBUG regTCO_STALLS_DEBUG; +typedef union TCO_QUAD0_DEBUG0 regTCO_QUAD0_DEBUG0; +typedef union TCO_QUAD0_DEBUG1 regTCO_QUAD0_DEBUG1; +typedef union SQ_GPR_MANAGEMENT regSQ_GPR_MANAGEMENT; +typedef union SQ_FLOW_CONTROL regSQ_FLOW_CONTROL; +typedef union SQ_INST_STORE_MANAGMENT regSQ_INST_STORE_MANAGMENT; +typedef union SQ_RESOURCE_MANAGMENT regSQ_RESOURCE_MANAGMENT; +typedef union SQ_EO_RT regSQ_EO_RT; +typedef union SQ_DEBUG_MISC regSQ_DEBUG_MISC; +typedef union SQ_ACTIVITY_METER_CNTL regSQ_ACTIVITY_METER_CNTL; +typedef union SQ_ACTIVITY_METER_STATUS regSQ_ACTIVITY_METER_STATUS; +typedef union SQ_INPUT_ARB_PRIORITY regSQ_INPUT_ARB_PRIORITY; +typedef union SQ_THREAD_ARB_PRIORITY regSQ_THREAD_ARB_PRIORITY; +typedef union SQ_VS_WATCHDOG_TIMER regSQ_VS_WATCHDOG_TIMER; +typedef union SQ_PS_WATCHDOG_TIMER regSQ_PS_WATCHDOG_TIMER; +typedef union SQ_INT_CNTL regSQ_INT_CNTL; +typedef union SQ_INT_STATUS regSQ_INT_STATUS; +typedef union SQ_INT_ACK regSQ_INT_ACK; +typedef union SQ_DEBUG_INPUT_FSM regSQ_DEBUG_INPUT_FSM; +typedef union SQ_DEBUG_CONST_MGR_FSM regSQ_DEBUG_CONST_MGR_FSM; +typedef union SQ_DEBUG_TP_FSM regSQ_DEBUG_TP_FSM; +typedef union SQ_DEBUG_FSM_ALU_0 regSQ_DEBUG_FSM_ALU_0; +typedef union SQ_DEBUG_FSM_ALU_1 regSQ_DEBUG_FSM_ALU_1; +typedef union SQ_DEBUG_EXP_ALLOC regSQ_DEBUG_EXP_ALLOC; +typedef union SQ_DEBUG_PTR_BUFF regSQ_DEBUG_PTR_BUFF; +typedef union SQ_DEBUG_GPR_VTX regSQ_DEBUG_GPR_VTX; +typedef union SQ_DEBUG_GPR_PIX regSQ_DEBUG_GPR_PIX; +typedef union SQ_DEBUG_TB_STATUS_SEL regSQ_DEBUG_TB_STATUS_SEL; +typedef union SQ_DEBUG_VTX_TB_0 regSQ_DEBUG_VTX_TB_0; +typedef union SQ_DEBUG_VTX_TB_1 regSQ_DEBUG_VTX_TB_1; +typedef union SQ_DEBUG_VTX_TB_STATUS_REG regSQ_DEBUG_VTX_TB_STATUS_REG; +typedef union SQ_DEBUG_VTX_TB_STATE_MEM regSQ_DEBUG_VTX_TB_STATE_MEM; +typedef union SQ_DEBUG_PIX_TB_0 regSQ_DEBUG_PIX_TB_0; +typedef union SQ_DEBUG_PIX_TB_STATUS_REG_0 regSQ_DEBUG_PIX_TB_STATUS_REG_0; +typedef union SQ_DEBUG_PIX_TB_STATUS_REG_1 regSQ_DEBUG_PIX_TB_STATUS_REG_1; +typedef union SQ_DEBUG_PIX_TB_STATUS_REG_2 regSQ_DEBUG_PIX_TB_STATUS_REG_2; +typedef union SQ_DEBUG_PIX_TB_STATUS_REG_3 regSQ_DEBUG_PIX_TB_STATUS_REG_3; +typedef union SQ_DEBUG_PIX_TB_STATE_MEM regSQ_DEBUG_PIX_TB_STATE_MEM; +typedef union SQ_PERFCOUNTER0_SELECT regSQ_PERFCOUNTER0_SELECT; +typedef union SQ_PERFCOUNTER1_SELECT regSQ_PERFCOUNTER1_SELECT; +typedef union SQ_PERFCOUNTER2_SELECT regSQ_PERFCOUNTER2_SELECT; +typedef union SQ_PERFCOUNTER3_SELECT regSQ_PERFCOUNTER3_SELECT; +typedef union SQ_PERFCOUNTER0_LOW regSQ_PERFCOUNTER0_LOW; +typedef union SQ_PERFCOUNTER0_HI regSQ_PERFCOUNTER0_HI; +typedef union SQ_PERFCOUNTER1_LOW regSQ_PERFCOUNTER1_LOW; +typedef union SQ_PERFCOUNTER1_HI regSQ_PERFCOUNTER1_HI; +typedef union SQ_PERFCOUNTER2_LOW regSQ_PERFCOUNTER2_LOW; +typedef union SQ_PERFCOUNTER2_HI regSQ_PERFCOUNTER2_HI; +typedef union SQ_PERFCOUNTER3_LOW regSQ_PERFCOUNTER3_LOW; +typedef union SQ_PERFCOUNTER3_HI regSQ_PERFCOUNTER3_HI; +typedef union SX_PERFCOUNTER0_SELECT regSX_PERFCOUNTER0_SELECT; +typedef union SX_PERFCOUNTER0_LOW regSX_PERFCOUNTER0_LOW; +typedef union SX_PERFCOUNTER0_HI regSX_PERFCOUNTER0_HI; +typedef union SQ_INSTRUCTION_ALU_0 regSQ_INSTRUCTION_ALU_0; +typedef union SQ_INSTRUCTION_ALU_1 regSQ_INSTRUCTION_ALU_1; +typedef union SQ_INSTRUCTION_ALU_2 regSQ_INSTRUCTION_ALU_2; +typedef union SQ_INSTRUCTION_CF_EXEC_0 regSQ_INSTRUCTION_CF_EXEC_0; +typedef union SQ_INSTRUCTION_CF_EXEC_1 regSQ_INSTRUCTION_CF_EXEC_1; +typedef union SQ_INSTRUCTION_CF_EXEC_2 regSQ_INSTRUCTION_CF_EXEC_2; +typedef union SQ_INSTRUCTION_CF_LOOP_0 regSQ_INSTRUCTION_CF_LOOP_0; +typedef union SQ_INSTRUCTION_CF_LOOP_1 regSQ_INSTRUCTION_CF_LOOP_1; +typedef union SQ_INSTRUCTION_CF_LOOP_2 regSQ_INSTRUCTION_CF_LOOP_2; +typedef union SQ_INSTRUCTION_CF_JMP_CALL_0 regSQ_INSTRUCTION_CF_JMP_CALL_0; +typedef union SQ_INSTRUCTION_CF_JMP_CALL_1 regSQ_INSTRUCTION_CF_JMP_CALL_1; +typedef union SQ_INSTRUCTION_CF_JMP_CALL_2 regSQ_INSTRUCTION_CF_JMP_CALL_2; +typedef union SQ_INSTRUCTION_CF_ALLOC_0 regSQ_INSTRUCTION_CF_ALLOC_0; +typedef union SQ_INSTRUCTION_CF_ALLOC_1 regSQ_INSTRUCTION_CF_ALLOC_1; +typedef union SQ_INSTRUCTION_CF_ALLOC_2 regSQ_INSTRUCTION_CF_ALLOC_2; +typedef union SQ_INSTRUCTION_TFETCH_0 regSQ_INSTRUCTION_TFETCH_0; +typedef union SQ_INSTRUCTION_TFETCH_1 regSQ_INSTRUCTION_TFETCH_1; +typedef union SQ_INSTRUCTION_TFETCH_2 regSQ_INSTRUCTION_TFETCH_2; +typedef union SQ_INSTRUCTION_VFETCH_0 regSQ_INSTRUCTION_VFETCH_0; +typedef union SQ_INSTRUCTION_VFETCH_1 regSQ_INSTRUCTION_VFETCH_1; +typedef union SQ_INSTRUCTION_VFETCH_2 regSQ_INSTRUCTION_VFETCH_2; +typedef union SQ_CONSTANT_0 regSQ_CONSTANT_0; +typedef union SQ_CONSTANT_1 regSQ_CONSTANT_1; +typedef union SQ_CONSTANT_2 regSQ_CONSTANT_2; +typedef union SQ_CONSTANT_3 regSQ_CONSTANT_3; +typedef union SQ_FETCH_0 regSQ_FETCH_0; +typedef union SQ_FETCH_1 regSQ_FETCH_1; +typedef union SQ_FETCH_2 regSQ_FETCH_2; +typedef union SQ_FETCH_3 regSQ_FETCH_3; +typedef union SQ_FETCH_4 regSQ_FETCH_4; +typedef union SQ_FETCH_5 regSQ_FETCH_5; +typedef union SQ_CONSTANT_VFETCH_0 regSQ_CONSTANT_VFETCH_0; +typedef union SQ_CONSTANT_VFETCH_1 regSQ_CONSTANT_VFETCH_1; +typedef union SQ_CONSTANT_T2 regSQ_CONSTANT_T2; +typedef union SQ_CONSTANT_T3 regSQ_CONSTANT_T3; +typedef union SQ_CF_BOOLEANS regSQ_CF_BOOLEANS; +typedef union SQ_CF_LOOP regSQ_CF_LOOP; +typedef union SQ_CONSTANT_RT_0 regSQ_CONSTANT_RT_0; +typedef union SQ_CONSTANT_RT_1 regSQ_CONSTANT_RT_1; +typedef union SQ_CONSTANT_RT_2 regSQ_CONSTANT_RT_2; +typedef union SQ_CONSTANT_RT_3 regSQ_CONSTANT_RT_3; +typedef union SQ_FETCH_RT_0 regSQ_FETCH_RT_0; +typedef union SQ_FETCH_RT_1 regSQ_FETCH_RT_1; +typedef union SQ_FETCH_RT_2 regSQ_FETCH_RT_2; +typedef union SQ_FETCH_RT_3 regSQ_FETCH_RT_3; +typedef union SQ_FETCH_RT_4 regSQ_FETCH_RT_4; +typedef union SQ_FETCH_RT_5 regSQ_FETCH_RT_5; +typedef union SQ_CF_RT_BOOLEANS regSQ_CF_RT_BOOLEANS; +typedef union SQ_CF_RT_LOOP regSQ_CF_RT_LOOP; +typedef union SQ_VS_PROGRAM regSQ_VS_PROGRAM; +typedef union SQ_PS_PROGRAM regSQ_PS_PROGRAM; +typedef union SQ_CF_PROGRAM_SIZE regSQ_CF_PROGRAM_SIZE; +typedef union SQ_INTERPOLATOR_CNTL regSQ_INTERPOLATOR_CNTL; +typedef union SQ_PROGRAM_CNTL regSQ_PROGRAM_CNTL; +typedef union SQ_WRAPPING_0 regSQ_WRAPPING_0; +typedef union SQ_WRAPPING_1 regSQ_WRAPPING_1; +typedef union SQ_VS_CONST regSQ_VS_CONST; +typedef union SQ_PS_CONST regSQ_PS_CONST; +typedef union SQ_CONTEXT_MISC regSQ_CONTEXT_MISC; +typedef union SQ_CF_RD_BASE regSQ_CF_RD_BASE; +typedef union SQ_DEBUG_MISC_0 regSQ_DEBUG_MISC_0; +typedef union SQ_DEBUG_MISC_1 regSQ_DEBUG_MISC_1; +typedef union MH_ARBITER_CONFIG regMH_ARBITER_CONFIG; +typedef union MH_CLNT_AXI_ID_REUSE regMH_CLNT_AXI_ID_REUSE; +typedef union MH_INTERRUPT_MASK regMH_INTERRUPT_MASK; +typedef union MH_INTERRUPT_STATUS regMH_INTERRUPT_STATUS; +typedef union MH_INTERRUPT_CLEAR regMH_INTERRUPT_CLEAR; +typedef union MH_AXI_ERROR regMH_AXI_ERROR; +typedef union MH_PERFCOUNTER0_SELECT regMH_PERFCOUNTER0_SELECT; +typedef union MH_PERFCOUNTER1_SELECT regMH_PERFCOUNTER1_SELECT; +typedef union MH_PERFCOUNTER0_CONFIG regMH_PERFCOUNTER0_CONFIG; +typedef union MH_PERFCOUNTER1_CONFIG regMH_PERFCOUNTER1_CONFIG; +typedef union MH_PERFCOUNTER0_LOW regMH_PERFCOUNTER0_LOW; +typedef union MH_PERFCOUNTER1_LOW regMH_PERFCOUNTER1_LOW; +typedef union MH_PERFCOUNTER0_HI regMH_PERFCOUNTER0_HI; +typedef union MH_PERFCOUNTER1_HI regMH_PERFCOUNTER1_HI; +typedef union MH_DEBUG_CTRL regMH_DEBUG_CTRL; +typedef union MH_DEBUG_DATA regMH_DEBUG_DATA; +typedef union MH_AXI_HALT_CONTROL regMH_AXI_HALT_CONTROL; +typedef union MH_MMU_CONFIG regMH_MMU_CONFIG; +typedef union MH_MMU_VA_RANGE regMH_MMU_VA_RANGE; +typedef union MH_MMU_PT_BASE regMH_MMU_PT_BASE; +typedef union MH_MMU_PAGE_FAULT regMH_MMU_PAGE_FAULT; +typedef union MH_MMU_TRAN_ERROR regMH_MMU_TRAN_ERROR; +typedef union MH_MMU_INVALIDATE regMH_MMU_INVALIDATE; +typedef union MH_MMU_MPU_BASE regMH_MMU_MPU_BASE; +typedef union MH_MMU_MPU_END regMH_MMU_MPU_END; +typedef union WAIT_UNTIL regWAIT_UNTIL; +typedef union RBBM_ISYNC_CNTL regRBBM_ISYNC_CNTL; +typedef union RBBM_STATUS regRBBM_STATUS; +typedef union RBBM_DSPLY regRBBM_DSPLY; +typedef union RBBM_RENDER_LATEST regRBBM_RENDER_LATEST; +typedef union RBBM_RTL_RELEASE regRBBM_RTL_RELEASE; +typedef union RBBM_PATCH_RELEASE regRBBM_PATCH_RELEASE; +typedef union RBBM_AUXILIARY_CONFIG regRBBM_AUXILIARY_CONFIG; +typedef union RBBM_PERIPHID0 regRBBM_PERIPHID0; +typedef union RBBM_PERIPHID1 regRBBM_PERIPHID1; +typedef union RBBM_PERIPHID2 regRBBM_PERIPHID2; +typedef union RBBM_PERIPHID3 regRBBM_PERIPHID3; +typedef union RBBM_CNTL regRBBM_CNTL; +typedef union RBBM_SKEW_CNTL regRBBM_SKEW_CNTL; +typedef union RBBM_SOFT_RESET regRBBM_SOFT_RESET; +typedef union RBBM_PM_OVERRIDE1 regRBBM_PM_OVERRIDE1; +typedef union RBBM_PM_OVERRIDE2 regRBBM_PM_OVERRIDE2; +typedef union GC_SYS_IDLE regGC_SYS_IDLE; +typedef union NQWAIT_UNTIL regNQWAIT_UNTIL; +typedef union RBBM_DEBUG_OUT regRBBM_DEBUG_OUT; +typedef union RBBM_DEBUG_CNTL regRBBM_DEBUG_CNTL; +typedef union RBBM_DEBUG regRBBM_DEBUG; +typedef union RBBM_READ_ERROR regRBBM_READ_ERROR; +typedef union RBBM_WAIT_IDLE_CLOCKS regRBBM_WAIT_IDLE_CLOCKS; +typedef union RBBM_INT_CNTL regRBBM_INT_CNTL; +typedef union RBBM_INT_STATUS regRBBM_INT_STATUS; +typedef union RBBM_INT_ACK regRBBM_INT_ACK; +typedef union MASTER_INT_SIGNAL regMASTER_INT_SIGNAL; +typedef union RBBM_PERFCOUNTER1_SELECT regRBBM_PERFCOUNTER1_SELECT; +typedef union RBBM_PERFCOUNTER1_LO regRBBM_PERFCOUNTER1_LO; +typedef union RBBM_PERFCOUNTER1_HI regRBBM_PERFCOUNTER1_HI; +typedef union CP_RB_BASE regCP_RB_BASE; +typedef union CP_RB_CNTL regCP_RB_CNTL; +typedef union CP_RB_RPTR_ADDR regCP_RB_RPTR_ADDR; +typedef union CP_RB_RPTR regCP_RB_RPTR; +typedef union CP_RB_RPTR_WR regCP_RB_RPTR_WR; +typedef union CP_RB_WPTR regCP_RB_WPTR; +typedef union CP_RB_WPTR_DELAY regCP_RB_WPTR_DELAY; +typedef union CP_RB_WPTR_BASE regCP_RB_WPTR_BASE; +typedef union CP_IB1_BASE regCP_IB1_BASE; +typedef union CP_IB1_BUFSZ regCP_IB1_BUFSZ; +typedef union CP_IB2_BASE regCP_IB2_BASE; +typedef union CP_IB2_BUFSZ regCP_IB2_BUFSZ; +typedef union CP_ST_BASE regCP_ST_BASE; +typedef union CP_ST_BUFSZ regCP_ST_BUFSZ; +typedef union CP_QUEUE_THRESHOLDS regCP_QUEUE_THRESHOLDS; +typedef union CP_MEQ_THRESHOLDS regCP_MEQ_THRESHOLDS; +typedef union CP_CSQ_AVAIL regCP_CSQ_AVAIL; +typedef union CP_STQ_AVAIL regCP_STQ_AVAIL; +typedef union CP_MEQ_AVAIL regCP_MEQ_AVAIL; +typedef union CP_CSQ_RB_STAT regCP_CSQ_RB_STAT; +typedef union CP_CSQ_IB1_STAT regCP_CSQ_IB1_STAT; +typedef union CP_CSQ_IB2_STAT regCP_CSQ_IB2_STAT; +typedef union CP_NON_PREFETCH_CNTRS regCP_NON_PREFETCH_CNTRS; +typedef union CP_STQ_ST_STAT regCP_STQ_ST_STAT; +typedef union CP_MEQ_STAT regCP_MEQ_STAT; +typedef union CP_MIU_TAG_STAT regCP_MIU_TAG_STAT; +typedef union CP_CMD_INDEX regCP_CMD_INDEX; +typedef union CP_CMD_DATA regCP_CMD_DATA; +typedef union CP_ME_CNTL regCP_ME_CNTL; +typedef union CP_ME_STATUS regCP_ME_STATUS; +typedef union CP_ME_RAM_WADDR regCP_ME_RAM_WADDR; +typedef union CP_ME_RAM_RADDR regCP_ME_RAM_RADDR; +typedef union CP_ME_RAM_DATA regCP_ME_RAM_DATA; +typedef union CP_ME_RDADDR regCP_ME_RDADDR; +typedef union CP_DEBUG regCP_DEBUG; +typedef union SCRATCH_REG0 regSCRATCH_REG0; +typedef union GUI_SCRATCH_REG0 regGUI_SCRATCH_REG0; +typedef union SCRATCH_REG1 regSCRATCH_REG1; +typedef union GUI_SCRATCH_REG1 regGUI_SCRATCH_REG1; +typedef union SCRATCH_REG2 regSCRATCH_REG2; +typedef union GUI_SCRATCH_REG2 regGUI_SCRATCH_REG2; +typedef union SCRATCH_REG3 regSCRATCH_REG3; +typedef union GUI_SCRATCH_REG3 regGUI_SCRATCH_REG3; +typedef union SCRATCH_REG4 regSCRATCH_REG4; +typedef union GUI_SCRATCH_REG4 regGUI_SCRATCH_REG4; +typedef union SCRATCH_REG5 regSCRATCH_REG5; +typedef union GUI_SCRATCH_REG5 regGUI_SCRATCH_REG5; +typedef union SCRATCH_REG6 regSCRATCH_REG6; +typedef union GUI_SCRATCH_REG6 regGUI_SCRATCH_REG6; +typedef union SCRATCH_REG7 regSCRATCH_REG7; +typedef union GUI_SCRATCH_REG7 regGUI_SCRATCH_REG7; +typedef union SCRATCH_UMSK regSCRATCH_UMSK; +typedef union SCRATCH_ADDR regSCRATCH_ADDR; +typedef union CP_ME_VS_EVENT_SRC regCP_ME_VS_EVENT_SRC; +typedef union CP_ME_VS_EVENT_ADDR regCP_ME_VS_EVENT_ADDR; +typedef union CP_ME_VS_EVENT_DATA regCP_ME_VS_EVENT_DATA; +typedef union CP_ME_VS_EVENT_ADDR_SWM regCP_ME_VS_EVENT_ADDR_SWM; +typedef union CP_ME_VS_EVENT_DATA_SWM regCP_ME_VS_EVENT_DATA_SWM; +typedef union CP_ME_PS_EVENT_SRC regCP_ME_PS_EVENT_SRC; +typedef union CP_ME_PS_EVENT_ADDR regCP_ME_PS_EVENT_ADDR; +typedef union CP_ME_PS_EVENT_DATA regCP_ME_PS_EVENT_DATA; +typedef union CP_ME_PS_EVENT_ADDR_SWM regCP_ME_PS_EVENT_ADDR_SWM; +typedef union CP_ME_PS_EVENT_DATA_SWM regCP_ME_PS_EVENT_DATA_SWM; +typedef union CP_ME_CF_EVENT_SRC regCP_ME_CF_EVENT_SRC; +typedef union CP_ME_CF_EVENT_ADDR regCP_ME_CF_EVENT_ADDR; +typedef union CP_ME_CF_EVENT_DATA regCP_ME_CF_EVENT_DATA; +typedef union CP_ME_NRT_ADDR regCP_ME_NRT_ADDR; +typedef union CP_ME_NRT_DATA regCP_ME_NRT_DATA; +typedef union CP_ME_VS_FETCH_DONE_SRC regCP_ME_VS_FETCH_DONE_SRC; +typedef union CP_ME_VS_FETCH_DONE_ADDR regCP_ME_VS_FETCH_DONE_ADDR; +typedef union CP_ME_VS_FETCH_DONE_DATA regCP_ME_VS_FETCH_DONE_DATA; +typedef union CP_INT_CNTL regCP_INT_CNTL; +typedef union CP_INT_STATUS regCP_INT_STATUS; +typedef union CP_INT_ACK regCP_INT_ACK; +typedef union CP_PFP_UCODE_ADDR regCP_PFP_UCODE_ADDR; +typedef union CP_PFP_UCODE_DATA regCP_PFP_UCODE_DATA; +typedef union CP_PERFMON_CNTL regCP_PERFMON_CNTL; +typedef union CP_PERFCOUNTER_SELECT regCP_PERFCOUNTER_SELECT; +typedef union CP_PERFCOUNTER_LO regCP_PERFCOUNTER_LO; +typedef union CP_PERFCOUNTER_HI regCP_PERFCOUNTER_HI; +typedef union CP_BIN_MASK_LO regCP_BIN_MASK_LO; +typedef union CP_BIN_MASK_HI regCP_BIN_MASK_HI; +typedef union CP_BIN_SELECT_LO regCP_BIN_SELECT_LO; +typedef union CP_BIN_SELECT_HI regCP_BIN_SELECT_HI; +typedef union CP_NV_FLAGS_0 regCP_NV_FLAGS_0; +typedef union CP_NV_FLAGS_1 regCP_NV_FLAGS_1; +typedef union CP_NV_FLAGS_2 regCP_NV_FLAGS_2; +typedef union CP_NV_FLAGS_3 regCP_NV_FLAGS_3; +typedef union CP_STATE_DEBUG_INDEX regCP_STATE_DEBUG_INDEX; +typedef union CP_STATE_DEBUG_DATA regCP_STATE_DEBUG_DATA; +typedef union CP_PROG_COUNTER regCP_PROG_COUNTER; +typedef union CP_STAT regCP_STAT; +typedef union BIOS_0_SCRATCH regBIOS_0_SCRATCH; +typedef union BIOS_1_SCRATCH regBIOS_1_SCRATCH; +typedef union BIOS_2_SCRATCH regBIOS_2_SCRATCH; +typedef union BIOS_3_SCRATCH regBIOS_3_SCRATCH; +typedef union BIOS_4_SCRATCH regBIOS_4_SCRATCH; +typedef union BIOS_5_SCRATCH regBIOS_5_SCRATCH; +typedef union BIOS_6_SCRATCH regBIOS_6_SCRATCH; +typedef union BIOS_7_SCRATCH regBIOS_7_SCRATCH; +typedef union BIOS_8_SCRATCH regBIOS_8_SCRATCH; +typedef union BIOS_9_SCRATCH regBIOS_9_SCRATCH; +typedef union BIOS_10_SCRATCH regBIOS_10_SCRATCH; +typedef union BIOS_11_SCRATCH regBIOS_11_SCRATCH; +typedef union BIOS_12_SCRATCH regBIOS_12_SCRATCH; +typedef union BIOS_13_SCRATCH regBIOS_13_SCRATCH; +typedef union BIOS_14_SCRATCH regBIOS_14_SCRATCH; +typedef union BIOS_15_SCRATCH regBIOS_15_SCRATCH; +typedef union COHER_SIZE_PM4 regCOHER_SIZE_PM4; +typedef union COHER_BASE_PM4 regCOHER_BASE_PM4; +typedef union COHER_STATUS_PM4 regCOHER_STATUS_PM4; +typedef union COHER_SIZE_HOST regCOHER_SIZE_HOST; +typedef union COHER_BASE_HOST regCOHER_BASE_HOST; +typedef union COHER_STATUS_HOST regCOHER_STATUS_HOST; +typedef union COHER_DEST_BASE_0 regCOHER_DEST_BASE_0; +typedef union COHER_DEST_BASE_1 regCOHER_DEST_BASE_1; +typedef union COHER_DEST_BASE_2 regCOHER_DEST_BASE_2; +typedef union COHER_DEST_BASE_3 regCOHER_DEST_BASE_3; +typedef union COHER_DEST_BASE_4 regCOHER_DEST_BASE_4; +typedef union COHER_DEST_BASE_5 regCOHER_DEST_BASE_5; +typedef union COHER_DEST_BASE_6 regCOHER_DEST_BASE_6; +typedef union COHER_DEST_BASE_7 regCOHER_DEST_BASE_7; +typedef union RB_SURFACE_INFO regRB_SURFACE_INFO; +typedef union RB_COLOR_INFO regRB_COLOR_INFO; +typedef union RB_DEPTH_INFO regRB_DEPTH_INFO; +typedef union RB_STENCILREFMASK regRB_STENCILREFMASK; +typedef union RB_ALPHA_REF regRB_ALPHA_REF; +typedef union RB_COLOR_MASK regRB_COLOR_MASK; +typedef union RB_BLEND_RED regRB_BLEND_RED; +typedef union RB_BLEND_GREEN regRB_BLEND_GREEN; +typedef union RB_BLEND_BLUE regRB_BLEND_BLUE; +typedef union RB_BLEND_ALPHA regRB_BLEND_ALPHA; +typedef union RB_FOG_COLOR regRB_FOG_COLOR; +typedef union RB_STENCILREFMASK_BF regRB_STENCILREFMASK_BF; +typedef union RB_DEPTHCONTROL regRB_DEPTHCONTROL; +typedef union RB_BLENDCONTROL regRB_BLENDCONTROL; +typedef union RB_COLORCONTROL regRB_COLORCONTROL; +typedef union RB_MODECONTROL regRB_MODECONTROL; +typedef union RB_COLOR_DEST_MASK regRB_COLOR_DEST_MASK; +typedef union RB_COPY_CONTROL regRB_COPY_CONTROL; +typedef union RB_COPY_DEST_BASE regRB_COPY_DEST_BASE; +typedef union RB_COPY_DEST_PITCH regRB_COPY_DEST_PITCH; +typedef union RB_COPY_DEST_INFO regRB_COPY_DEST_INFO; +typedef union RB_COPY_DEST_PIXEL_OFFSET regRB_COPY_DEST_PIXEL_OFFSET; +typedef union RB_DEPTH_CLEAR regRB_DEPTH_CLEAR; +typedef union RB_SAMPLE_COUNT_CTL regRB_SAMPLE_COUNT_CTL; +typedef union RB_SAMPLE_COUNT_ADDR regRB_SAMPLE_COUNT_ADDR; +typedef union RB_BC_CONTROL regRB_BC_CONTROL; +typedef union RB_EDRAM_INFO regRB_EDRAM_INFO; +typedef union RB_CRC_RD_PORT regRB_CRC_RD_PORT; +typedef union RB_CRC_CONTROL regRB_CRC_CONTROL; +typedef union RB_CRC_MASK regRB_CRC_MASK; +typedef union RB_PERFCOUNTER0_SELECT regRB_PERFCOUNTER0_SELECT; +typedef union RB_PERFCOUNTER0_LOW regRB_PERFCOUNTER0_LOW; +typedef union RB_PERFCOUNTER0_HI regRB_PERFCOUNTER0_HI; +typedef union RB_TOTAL_SAMPLES regRB_TOTAL_SAMPLES; +typedef union RB_ZPASS_SAMPLES regRB_ZPASS_SAMPLES; +typedef union RB_ZFAIL_SAMPLES regRB_ZFAIL_SAMPLES; +typedef union RB_SFAIL_SAMPLES regRB_SFAIL_SAMPLES; +typedef union RB_DEBUG_0 regRB_DEBUG_0; +typedef union RB_DEBUG_1 regRB_DEBUG_1; +typedef union RB_DEBUG_2 regRB_DEBUG_2; +typedef union RB_DEBUG_3 regRB_DEBUG_3; +typedef union RB_DEBUG_4 regRB_DEBUG_4; +typedef union RB_FLAG_CONTROL regRB_FLAG_CONTROL; +typedef union RB_BC_SPARES regRB_BC_SPARES; +typedef union BC_DUMMY_CRAYRB_ENUMS regBC_DUMMY_CRAYRB_ENUMS; +typedef union BC_DUMMY_CRAYRB_MOREENUMS regBC_DUMMY_CRAYRB_MOREENUMS; +#endif -- cgit v1.2.3